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* gas/testsuite/gas/arm/neon-const.s: New testcase. Neon floating-point
[deliverable/binutils-gdb.git] / gas / ChangeLog
CommitLineData
dcbf9037
JB		 12006-04-26 Julian Brown <julian@codesourcery.com>
2
3 * config/tc-arm.c (neon_el_type): Make NT_invtype be the zero (so
4 zero-initialising structures containing it will lead to invalid types).
5 (arm_it): Add vectype to each operand.
6 (NTA_HASTYPE, NTA_HASINDEX): Constants used in neon_typed_alias
7 defined field.
8 (neon_typed_alias): New structure. Extra information for typed
9 register aliases.
10 (reg_entry): Add neon type info field.
11 (arm_reg_parse): Remove RTYPE argument (revert to previous arguments).
12 Break out alternative syntax for coprocessor registers, etc. into...
13 (arm_reg_alt_syntax): New function. Alternate syntax handling broken
14 out from arm_reg_parse.
15 (parse_neon_type): Move. Return SUCCESS/FAIL.
16 (first_error): New function. Call to ensure first error which occurs is
17 reported.
18 (parse_neon_operand_type): Parse exactly one type.
19 (NEON_ALL_LANES, NEON_INTERLEAVE_LANES): Move.
20 (parse_typed_reg_or_scalar): New function. Handle core of both
21 arm_typed_reg_parse and parse_scalar.
22 (arm_typed_reg_parse): Parse a register with an optional type.
23 (NEON_SCALAR_REG, NEON_SCALAR_INDEX): Extract parts of parse_scalar
24 result.
25 (parse_scalar): Parse a Neon scalar with optional type.
26 (parse_reg_list): Use first_error.
27 (parse_vfp_reg_list): Use arm_typed_reg_parse instead of arm_reg_parse.
28 (neon_alias_types_same): New function. Return true if two (alias) types
29 are the same.
30 (parse_neon_el_struct_list): Use parse_typed_reg_or_scalar. Return type
31 of elements.
32 (insert_reg_alias): Return new reg_entry not void.
33 (insert_neon_reg_alias): New function. Insert type/index information as
34 well as register for alias.
35 (create_neon_reg_alias): New function. Parse .dn/.qn directives and
36 make typed register aliases accordingly.
37 (s_dn, s_qn): New functions. Handle incorrectly used .dn/.qn at start
38 of line.
39 (s_unreq): Delete type information if present.
40 (s_arm_unwind_save_mmxwr): Remove arg 3 from arm_reg_parse calls.
41 (s_arm_unwind_save_mmxwcg): Likewise.
42 (s_arm_unwind_movsp): Likewise.
43 (s_arm_unwind_setfp): Likewise.
44 (parse_shift): Likewise.
45 (parse_shifter_operand): Likewise.
46 (parse_address): Likewise.
47 (parse_tb): Likewise.
48 (tc_arm_regname_to_dw2regnum): Likewise.
49 (md_pseudo_table): Add dn, qn.
50 (parse_neon_mov): Handle typed operands.
51 (parse_operands): Likewise.
52 (neon_type_mask): Add N_SIZ.
53 (N_ALLMODS): New macro.
54 (neon_check_shape): Fix typo in NS_DDD_QQQ case. Use first_error.
55 (el_type_of_type_chk): Add some safeguards.
56 (modify_types_allowed): Fix logic bug.
57 (neon_check_type): Handle operands with types.
58 (neon_three_same): Remove redundant optional arg handling.
59 (do_neon_dyadic_i64_su, do_neon_shl_imm, do_neon_qshl_imm)
60 (do_neon_logic, do_neon_qdmulh, do_neon_fcmp_absolute)
61 (do_neon_step): Adjust accordingly.
62 (neon_cmode_for_logic_imm): Use first_error.
63 (do_neon_bitfield): Call neon_check_type.
64 (neon_dyadic): Rename to...
65 (neon_dyadic_misc): ...this. New name for neon_dyadic. Add bitfield
66 to allow modification of type of the destination.
67 (do_neon_dyadic_if_su, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
68 (do_neon_addsub_if_i, do_neon_mul): Adjust accordingly.
69 (do_neon_compare): Make destination be an untyped bitfield.
70 (neon_scalar_for_mul): Use NEON_SCALAR_REG, NEON_SCALAR_INDEX.
71 (neon_mul_mac): Return early in case of errors.
72 (neon_move_immediate): Use first_error.
73 (neon_mac_reg_scalar_long): Fix type to include scalar.
74 (do_neon_dup): Likewise.
75 (do_neon_mov): Likewise (in several places).
76 (do_neon_tbl_tbx): Fix type.
77 (do_neon_ld_st_interleave, neon_alignment_bit, do_neon_ld_st_lane)
78 (do_neon_ld_dup): Exit early in case of errors and/or use
79 first_error.
80 (opcode_lookup): Update for parse_neon_type returning SUCCESS/FAIL.
81 Handle .dn/.qn directives.
82 (REGDEF): Add zero for reg_entry neon field.
83
5287ad62
JB		 842006-04-26 Julian Brown <julian@codesourcery.com>
85
86 * config/tc-arm.c (limits.h): Include.
87 (fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1)
88 (fpu_vfp_v3_or_neon_ext): Declare constants.
89 (neon_el_type): New enumeration of types for Neon vector elements.
90 (neon_type_el): New struct. Define type and size of a vector element.
91 (NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per
92 instruction.
93 (neon_type): Define struct. The type of an instruction.
94 (arm_it): Add 'vectype' for the current instruction.
95 (isscalar, immisalign, regisimm, isquad): New predicates for operands.
96 (vfp_sp_reg_pos): Rename to...
97 (vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
98 tags.
99 (arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ
100 (Neon D or Q register).
101 (reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D
102 register.
103 (GE_OPT_PREFIX_BIG): Define constant, for use in...
104 (my_get_expression): Allow above constant as argument to accept
105 64-bit constants with optional prefix.
106 (arm_reg_parse): Add extra argument to return the specific type of
107 register in when either a D or Q register (REG_TYPE_NDQ) is
108 requested. Can be NULL.
109 (parse_scalar): New function. Parse Neon scalar (vector reg and index).
110 (parse_reg_list): Update for new arm_reg_parse args.
111 (parse_vfp_reg_list): Allow parsing of Neon D/Q register lists.
112 (parse_neon_el_struct_list): New function. Parse element/structure
113 register lists for VLD<n>/VST<n> instructions.
114 (s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args.
115 (s_arm_unwind_save_mmxwr): Likewise.
116 (s_arm_unwind_save_mmxwcg): Likewise.
117 (s_arm_unwind_movsp): Likewise.
118 (s_arm_unwind_setfp): Likewise.
119 (parse_big_immediate): New function. Parse an immediate, which may be
120 64 bits wide. Put results in inst.operands[i].
121 (parse_shift): Update for new arm_reg_parse args.
122 (parse_address): Likewise. Add parsing of alignment specifiers.
123 (parse_neon_mov): Parse the operands of a VMOV instruction.
124 (operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST,
125 OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC,
126 OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64,
127 OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ.
128 (parse_operands): Handle new codes above.
129 (encode_arm_vfp_sp_reg): Rename to...
130 (encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if
131 selected VFP version only supports D0-D15.
132 (do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z)
133 (do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2)
134 (do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst)
135 (do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new
136 encode_arm_vfp_reg name, and allow 32 D regs.
137 (do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm)
138 (do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D
139 regs.
140 (do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16)
141 (do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle
142 constant-load and conversion insns introduced with VFPv3.
143 (neon_tab_entry): New struct.
144 (NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and
145 those which are the targets of pseudo-instructions.
146 (neon_opc): Enumerate opcodes, use as indices into...
147 (neon_enc_tab): ...this. Hold data from NEON_ENC_TAB.
148 (NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT)
149 (NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE)
150 (NEON_ENC_DUP): Define meaningful helper macros to look up values in
151 neon_enc_tab.
152 (neon_shape): Enumerate shapes (permitted register widths, etc.) for
153 Neon instructions.
154 (neon_type_mask): New. Compact type representation for type checking.
155 (N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common
156 permitted type combinations.
157 (N_IGNORE_TYPE): New macro.
158 (neon_check_shape): New function. Check an instruction shape for
159 multiple alternatives. Return the specific shape for the current
160 instruction.
161 (neon_modify_type_size): New function. Modify a vector type and size,
162 depending on the bit mask in argument 1.
163 (neon_type_promote): New function. Convert a given "key" type (of an
164 operand) into the correct type for a different operand, based on a bit
165 mask.
166 (type_chk_of_el_type): New function. Convert a type and size into the
167 compact representation used for type checking.
168 (el_type_of_type_ckh): New function. Reverse of above (only when a
169 single bit is set in the bit mask).
170 (modify_types_allowed): New function. Alter a mask of allowed types
171 based on a bit mask of modifications.
172 (neon_check_type): New function. Check the type of the current
173 instruction against the variable argument list. The "key" type of the
174 instruction is returned.
175 (neon_dp_fixup): New function. Fill in and modify instruction bits for
176 a Neon data-processing instruction depending on whether we're in ARM
177 mode or Thumb-2 mode.
178 (neon_logbits): New function.
179 (neon_three_same, neon_two_same, do_neon_dyadic_i_su)
180 (do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm)
181 (do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes)
182 (neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits)
183 (neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size)
184 (do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su)
185 (do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
186 (do_neon_addsub_if_i, neon_exchange_operands, neon_compare)
187 (do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul)
188 (neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul)
189 (do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv)
190 (do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri)
191 (do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun)
192 (do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn)
193 (do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt)
194 (neon_move_immediate, do_neon_mvn, neon_mixed_length)
195 (do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long)
196 (do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull)
197 (do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov)
198 (do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp)
199 (do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est)
200 (do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx)
201 (do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave)
202 (neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup)
203 (do_neon_ldx_stx): New functions. Neon bit encoding and encoding
204 helpers.
205 (parse_neon_type): New function. Parse Neon type specifier.
206 (opcode_lookup): Allow parsing of Neon type specifiers.
207 (REGNUM2, REGSETH, REGSET2): New macros.
208 (reg_names): Add new VFPv3 and Neon registers.
209 (NUF, nUF, NCE, nCE): New macros for opcode table.
210 (insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh,
211 fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd,
212 fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd.
213 Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl,
214 vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif,
215 vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla,
216 vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt,
217 vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr, v{r}sra, vsli,
218 vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal,
219 vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn,
220 vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup,
221 vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe,
222 vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr,
223 vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd],
224 fto[us][lh][sd].
225 (tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args.
226 (arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8.
227 (arm_option_cpu_value): Add vfp3 and neon.
228 (aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix
229 VFPv1 attribute.
230
1946c96e
BW		 2312006-04-25 Bob Wilson <bob.wilson@acm.org>
232
233 * config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>"
234 syntax instead of hardcoded opcodes with ".w18" suffixes.
235 (wide_branch_opcode): New.
236 (build_transition): Use it to check for wide branch opcodes with
237 either ".w18" or ".w15" suffixes.
238
5033a645
BW		 2392006-04-25 Bob Wilson <bob.wilson@acm.org>
240
241 * config/tc-xtensa.c (xtensa_create_literal_symbol,
242 xg_assemble_literal, xg_assemble_literal_space): Do not set the
243 frag's is_literal flag.
244
395fa56f
BW		 2452006-04-25 Bob Wilson <bob.wilson@acm.org>
246
247 * config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default.
248
708587a4
KH		 2492006-04-23 Kazu Hirata <kazu@codesourcery.com>
250
251 * config/obj-coff.c, config/tc-arm.c, config/tc-bfin.c,
252 config/tc-cris.c, config/tc-crx.c, config/tc-i386.c,
253 config/tc-ia64.c, config/tc-maxq.c, config/tc-maxq.h,
254 config/tc-mips.c, config/tc-msp430.c, config/tc-sh.c,
255 config/tc-tic4x.c, config/tc-xtensa.c: Fix comment typos.
256
8463be01
PB		 2572005-04-20 Paul Brook <paul@codesourcery.com>
258
259 * config/tc-arm.c (s_arm_arch, s_arm_cpu, s_arm_fpu): Enable for
260 all targets.
261 (md_pseudo_table): Enable .arch, .cpu and .fpu for all targets.
262
f26a5955
AM		 2632006-04-19 Alan Modra <amodra@bigpond.net.au>
264
265 * Makefile.am (CPU_TYPES): Add maxq and mt. Sort.
266 (CPU_OBJ_VALID): Change sense of COFF test to default to invalid.
267 Make some cpus unsupported on ELF. Run "make dep-am".
268 * Makefile.in: Regenerate.
269
241a6c40
AM		 2702006-04-19 Alan Modra <amodra@bigpond.net.au>
271
272 * configure.in (--enable-targets): Indent help message.
273 * configure: Regenerate.
274
bb8f5920
L		 2752006-04-18 H.J. Lu <hongjiu.lu@intel.com>
276
277 PR gas/2533
278 * config/tc-i386.c (i386_immediate): Check illegal immediate
279 register operand.
280
23d9d9de
AM		 2812006-04-18 Alan Modra <amodra@bigpond.net.au>
282
64e74474
AM		 283 * config/tc-i386.c: Formatting.
284 (output_disp, output_imm): ISO C90 params.
285
6cbe03fb
AM		 286 * frags.c (frag_offset_fixed_p): Constify args.
287 * frags.h (frag_offset_fixed_p): Ditto.
288
23d9d9de
AM		 289 * config/tc-dlx.h (tc_coff_symbol_emit_hook): Delete.
290 (COFF_MAGIC): Delete.
a37d486e
AM		 291
292 * config/tc-xc16x.h (TC_LINKRELAX_FIXUP): Delete.
293
e7403566
DJ		 2942006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
295
296 * po/POTFILES.in: Regenerated.
297
58ab4f3d
MM		 2982006-04-16 Mark Mitchell <mark@codesourcery.com>
299
300 * doc/as.texinfo: Mention that some .type syntaxes are not
301 supported on all architectures.
302
482fd9f9
BW		 3032006-04-14 Sterling Augustine <sterling@tensilica.com>
304
305 * config/tc-xtensa.c (emit_single_op): Do not relax MOVI
306 instructions when such transformations have been disabled.
307
05d58145
BW		 3082006-04-10 Sterling Augustine <sterling@tensilica.com>
309
310 * config/tc-xtensa.c (xg_assemble_vliw_tokens): Record loop target
311 symbols in RELAX[_CHECK]_ALIGN_NEXT_OPCODE frags.
312 (xtensa_fix_close_loop_end_frags): Use the recorded values instead of
313 decoding the loop instructions. Remove current_offset variable.
314 (xtensa_fix_short_loop_frags): Likewise.
315 (min_bytes_to_other_loop_end): Remove current_offset argument.
316
9e75b3fa
AM		 3172006-04-09 Arnold Metselaar <arnold.metselaar@planet.nl>
318
a37d486e 319 * config/tc-z80.c (z80_optimize_expr): Removed.
9e75b3fa
AM		 320 * config/tc-z80.h (z80_optimize_expr, md_optimize_expr): Removed.
321
d727e8c2
NC		 3222006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
323
324 * gas/config/tc-avr.c (mcu_types): Add support for attiny261,
325 attiny461, attiny861, attiny25, attiny45, attiny85,attiny24,
326 attiny44, attiny84, at90pwm2, at90pwm3, atmega164, atmega324,
327 atmega644, atmega329, atmega3290, atmega649, atmega6490,
328 atmega406, atmega640, atmega1280, atmega1281, at90can32,
329 at90can64, at90usb646, at90usb647, at90usb1286 and
330 at90usb1287.
331 Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
332
d252fdde
PB		 3332006-04-07 Paul Brook <paul@codesourcery.com>
334
335 * config/tc-arm.c (parse_operands): Set default error message.
336
ab1eb5fe
PB		 3372006-04-07 Paul Brook <paul@codesourcery.com>
338
339 * config/tc-arm.c (parse_tb): Set inst.error before returning FAIL.
340
7ae2971b
PB		 3412006-04-07 Paul Brook <paul@codesourcery.com>
342
343 * config/tc-arm.c (md_apply_fix): Set H bit on blx instruction.
344
53365c0d
PB		 3452006-04-07 Paul Brook <paul@codesourcery.com>
346
347 * config/tc-arm.c (THUMB2_LOAD_BIT): Define.
348 (move_or_literal_pool): Handle Thumb-2 instructions.
349 (do_t_ldst): Call move_or_literal_pool for =N addressing modes.
350
45aa61fe
AM		 3512006-04-07 Alan Modra <amodra@bigpond.net.au>
352
353 PR 2512.
354 * config/tc-i386.c (match_template): Move 64-bit operand tests
355 inside loop.
356
108a6f8e
CD		 3572006-04-06 Carlos O'Donell <carlos@codesourcery.com>
358
359 * po/Make-in: Add install-html target.
360 * Makefile.am: Add install-html and install-html-recursive targets.
361 * Makefile.in: Regenerate.
362 * configure.in: AC_SUBST datarootdir, docdir, htmldir.
363 * configure: Regenerate.
364 * doc/Makefile.am: Add install-html and install-html-am targets.
365 * doc/Makefile.in: Regenerate.
366
ec651a3b
AM		 3672006-04-06 Alan Modra <amodra@bigpond.net.au>
368
369 * frags.c (frag_offset_fixed_p): Reinitialise offset before
370 second scan.
371
910600e9
RS		 3722006-04-05 Richard Sandiford <richard@codesourcery.com>
373 Daniel Jacobowitz <dan@codesourcery.com>
374
375 * config/tc-sparc.c (sparc_target_format): Handle TE_VXWORKS.
376 (GOTT_BASE, GOTT_INDEX): New.
377 (tc_gen_reloc): Don't alter relocations against GOTT_BASE and
378 GOTT_INDEX when generating VxWorks PIC.
379 * configure.tgt (sparc*-*-vxworks*): Remove this special case;
380 use the generic *-*-vxworks* stanza instead.
381
99630778
AM		 3822006-04-04 Alan Modra <amodra@bigpond.net.au>
383
384 PR 997
385 * frags.c (frag_offset_fixed_p): New function.
386 * frags.h (frag_offset_fixed_p): Declare.
387 * expr.c (expr): Use frag_offset_fixed_p when simplifying subtraction.
388 (resolve_expression): Likewise.
389
a02728c8
BW		 3902006-04-03 Sterling Augustine <sterling@tensilica.com>
391
392 * config/tc-xtensa.c (init_op_placement_info_table): Check for formats
393 of the same length but different numbers of slots.
394
9dfde49d
AS		 3952006-03-30 Andreas Schwab <schwab@suse.de>
396
397 * configure.in: Fix help string for --enable-targets option.
398 * configure: Regenerate.
399
2da12c60
NS		 4002006-03-28 Nathan Sidwell <nathan@codesourcery.com>
401
6d89cc8f
NS		 402 * gas/config/tc-m68k.c (find_cf_chip): Merge into ...
403 (m68k_ip): ... here. Use for all chips. Protect against buffer
404 overrun and avoid excessive copying.
405
2da12c60
NS		 406 * config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
407 m68020_control_regs, m68040_control_regs, m68060_control_regs,
408 mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
409 mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
410 mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
411 (m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
412 mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl,
413 mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
414 mcf5282_ctrl, mcfv4e_ctrl): ... these.
415 (mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
416 (struct m68k_cpu): Change chip field to control_regs.
417 (current_chip): Remove.
418 (control_regs): New.
419 (m68k_archs, m68k_extensions): Adjust.
420 (m68k_cpus): Reorder to be in cpu number order. Adjust.
421 (CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
422 (find_cf_chip): Reimplement for new organization of cpu table.
423 (select_control_regs): Remove.
424 (mri_chip): Adjust.
425 (struct save_opts): Save control regs, not chip.
426 (s_save, s_restore): Adjust.
427 (m68k_lookup_cpu): Give deprecated warning when necessary.
428 (m68k_init_arch): Adjust.
429 (md_show_usage): Adjust for new cpu table organization.
430
1ac4baed
BS		 4312006-03-25 Bernd Schmidt <bernd.schmidt@analog.com>
432
433 * config/bfin-defs.h (Expr_Node_Type enum): Add Expr_Node_GOT_Reloc.
434 * config/bfin-lex.l: Recognize GOT17M4 and FUNCDESC_GOT17M4.
435 * config/bfin-parse.y: Include "libbfd.h", "elf/common.h" and
436 "elf/bfin.h".
437 (GOT17M4, FUNCDESC_GOT17M4): New tokens of type <value>.
438 (any_gotrel): New rule.
439 (got): Use it, and create Expr_Node_GOT_Reloc nodes.
440 * config/tc-bfin.c: Include "libbfd.h", "elf/common.h" and
441 "elf/bfin.h".
442 (DEFAULT_FLAGS, bfin_flags, bfin_pic_flag): New.
443 (bfin_pic_ptr): New function.
444 (md_pseudo_table): Add it for ".picptr".
445 (OPTION_FDPIC): New macro.
446 (md_longopts): Add -mfdpic.
447 (md_parse_option): Handle it.
448 (md_begin): Set BFD flags.
449 (md_apply_fix3, bfin_fix_adjustable): Handle new relocs.
450 (bfin_gen_ldstidxi): Adjust to match the trees that the parser gives
451 us for GOT relocs.
452 * Makefile.am (bfin-parse.o): Update dependencies.
453 (DEPTC_bfin_elf): Likewise.
454 * Makefile.in: Regenerate.
455
a9d34880
RS		 4562006-03-25 Richard Sandiford <richard@codesourcery.com>
457
458 * config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use
459 mcfemac instead of mcfmac.
460
9ca26584
AJ		 4612006-03-23 Michael Matz <matz@suse.de>
462
463 * config/tc-i386.c (type_names): Correct placement of 'static'.
464 (reloc): Map some more relocs to their 64 bit counterpart when
465 size is 8.
466 (output_insn): Work around breakage if DEBUG386 is defined.
467 (output_disp): A BFD_RELOC_64 with GOT_symbol as operand also
468 needs to be mapped to BFD_RELOC_X86_64_GOTPC64 or
469 BFD_RELOC_X86_64_GOTPC32. Also x86-64 handles pcrel addressing
470 different from i386.
471 (output_imm): Ditto.
472 (lex_got): Recognize @PLTOFF and @GOTPLT. Make @GOT accept also
473 Imm64.
474 (md_convert_frag): Jumps can now be larger than 2GB away, error
475 out in that case.
476 (tc_gen_reloc): New relocs are passed through. BFD_RELOC_64
477 and BFD_RELOC_64_PCREL are mapped to BFD_RELOC_X86_64_GOTPC64.
478
0a44bf69
RS		 4792006-03-22 Richard Sandiford <richard@codesourcery.com>
480 Daniel Jacobowitz <dan@codesourcery.com>
481 Phil Edwards <phil@codesourcery.com>
482 Zack Weinberg <zack@codesourcery.com>
483 Mark Mitchell <mark@codesourcery.com>
484 Nathan Sidwell <nathan@codesourcery.com>
485
486 * config/tc-mips.c (mips_target_format): Handle vxworks targets.
487 (md_begin): Complain about -G being used for PIC. Don't change
488 the text, data and bss alignments on VxWorks.
489 (reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
490 generating VxWorks PIC.
491 (load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
492 (macro): Likewise, but do not treat la $25 specially for
493 VxWorks PIC, and do not handle jal.
494 (OPTION_MVXWORKS_PIC): New macro.
495 (md_longopts): Add -mvxworks-pic.
496 (md_parse_option): Don't complain about using PIC and -G together here.
497 Handle OPTION_MVXWORKS_PIC.
498 (md_estimate_size_before_relax): Always use the first relaxation
499 sequence on VxWorks.
500 * config/tc-mips.h (VXWORKS_PIC): New.
501
080eb7fe
PB		 5022006-03-21 Paul Brook <paul@codesourcery.com>
503
504 * config/tc-arm.c (md_apply_fix): Fix typo in offset mask.
505
03aaa593
BW		 5062006-03-21 Sterling Augustine <sterling@tensilica.com>
507
508 * config/tc-xtensa.c (enforce_three_byte_loop_align): New flag.
509 (xtensa_setup_hw_workarounds): Set this new flag for older hardware.
510 (get_loop_align_size): New.
511 (xtensa_end): Skip xtensa_mark_narrow_branches when not aligning.
512 (xtensa_mark_zcl_first_insns): Prevent widening of first loop frag.
513 (get_text_align_power): Rewrite to handle inputs in the range 2-8.
514 (get_noop_aligned_address): Use get_loop_align_size.
515 (get_aligned_diff): Likewise.
516
3e94bf1a
PB		 5172006-03-21 Paul Brook <paul@codesourcery.com>
518
519 * config/tc-arm.c (insns): Correct opcodes for ldrbt and strbt.
520
dfa9f0d5
PB		 5212006-03-20 Paul Brook <paul@codesourcery.com>
522
523 * config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define.
524 (do_t_branch): Encode branches inside IT blocks as unconditional.
525 (do_t_cps): New function.
526 (do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi,
527 do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints.
528 (opcode_lookup): Allow conditional suffixes on all instructions in
529 Thumb mode.
530 (md_assemble): Advance condexec state before checking for errors.
531 (insns): Use do_t_cps.
532
6e1cb1a6
PB		 5332006-03-20 Paul Brook <paul@codesourcery.com>
534
535 * config/tc-arm.c (output_relax_insn): Call dwarf2_emit_insn before
536 outputting the insn.
537
0a966e2d
JBG		 5382006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
539
540 * config/tc-vax.c: Update copyright year.
541 * config/tc-vax.h: Likewise.
542
a49fcc17
JBG		 5432006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
544
545 * config/tc-vax.c (md_chars_to_number): Used only locally, so
546 make it static.
547 * config/tc-vax.h (md_chars_to_number): Remove obsolete declaration.
548
f5208ef2
PB		 5492006-03-17 Paul Brook <paul@codesourcery.com>
550
551 * config/tc-arm.c (insns): Add ldm and stm.
552
cb4c78d6
BE		 5532006-03-17 Ben Elliston <bje@au.ibm.com>
554
555 PR gas/2446
556 * doc/as.texinfo (Ident): Document this directive more thoroughly.
557
c16d2bf0
PB		 5582006-03-16 Paul Brook <paul@codesourcery.com>
559
560 * config/tc-arm.c (insns): Add "svc".
561
80ca4e2c
BW		 5622006-03-13 Bob Wilson <bob.wilson@acm.org>
563
564 * config/tc-xtensa.c (xg_translate_sysreg_op): Remove has_underbar
565 flag and avoid double underscore prefixes.
566
3a4a14e9
PB		 5672006-03-10 Paul Brook <paul@codesourcery.com>
568
569 * config/tc-arm.c (md_begin): Handle EABIv5.
570 (arm_eabis): Add EF_ARM_EABI_VER5.
571 * doc/c-arm.texi: Document -meabi=5.
572
518051dc
BE		 5732006-03-10 Ben Elliston <bje@au.ibm.com>
574
575 * app.c (do_scrub_chars): Simplify string handling.
576
00a97672
RS		 5772006-03-07 Richard Sandiford <richard@codesourcery.com>
578 Daniel Jacobowitz <dan@codesourcery.com>
579 Zack Weinberg <zack@codesourcery.com>
580 Nathan Sidwell <nathan@codesourcery.com>
581 Paul Brook <paul@codesourcery.com>
582 Ricardo Anguiano <anguiano@codesourcery.com>
583 Phil Edwards <phil@codesourcery.com>
584
585 * config/tc-arm.c (md_apply_fix): Install a value of zero into a
586 BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
587 R_ARM_ABS12 reloc.
588 (tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
589 relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12
590 relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
591
b29757dc
BW		 5922006-03-06 Bob Wilson <bob.wilson@acm.org>
593
594 * config/tc-xtensa.c (xtensa_post_relax_hook): Generate literal tables
595 even when using the text-section-literals option.
596
0b2e31dc
NS		 5972006-03-06 Nathan Sidwell <nathan@codesourcery.com>
598
599 * config/tc-m68k.c (m68k_extensions): Allow 'float' on both m68k
600 and cf.
601 (m68k_ip): <case 'J'> Check we have some control regs.
602 (md_parse_option): Allow raw arch switch.
603 (m68k_init_arch): Better detection of arch/cpu mismatch. Detect
604 whether 68881 or cfloat was meant by -mfloat.
605 (md_show_usage): Adjust extension display.
606 (m68k_elf_final_processing): Adjust.
607
df406460
NC		 6082006-03-03 Bjoern Haase <bjoern.m.haase@web.de>
609
610 * config/tc-avr.c (avr_mod_hash_value): New function.
611 (md_apply_fix, exp_mod): Use BFD_RELOC_HH8_LDI and
612 BFD_RELOC_MS8_LDI for hlo8() and hhi8()
613 (md_begin): Set linkrelax variable to 1, use avr_mod_hash_value
614 instead of int avr_ldi_expression: use avr_mod_hash_value instead
615 of (int).
616 (tc_gen_reloc): Handle substractions of symbols, if possible do
617 fixups, abort otherwise.
618 * config/tc-avr.h (TC_LINKRELAX_FIXUP, TC_VALIDATE_FIX,
619 tc_fix_adjustable): Define.
620
53022e4a
JW		 6212006-03-02 James E Wilson <wilson@specifix.com>
622
623 * config/tc-ia64.c (emit_one_bundle): For IA64_OPCODE_LAST, if we
624 change the template, then clear md.slot[curr].end_of_insn_group.
625
9f6f925e
JB		 6262006-02-28 Jan Beulich <jbeulich@novell.com>
627
628 * macro.c (get_any_string): Don't insert quotes for <>-quoted input.
629
0e31b3e1
JB		 6302006-02-28 Jan Beulich <jbeulich@novell.com>
631
632 PR/1070
633 * macro.c (getstring): Don't treat parentheses special anymore.
634 (get_any_string): Don't consider '(' and ')' as quoting anymore.
635 Special-case '(', ')', '[', and ']' when dealing with non-quoting
636 characters.
637
10cd14b4
AM		 6382006-02-28 Mat <mat@csail.mit.edu>
639
640 * dwarf2dbg.c (get_filenum): Don't inadvertently decrease files_in_use.
641
63752a75
JJ		 6422006-02-27 Jakub Jelinek <jakub@redhat.com>
643
644 * dw2gencfi.c (struct fde_entry, struct cie_entry): Add signal_frame
645 field.
646 (CFI_signal_frame): Define.
647 (cfi_pseudo_table): Add .cfi_signal_frame.
648 (dot_cfi): Handle CFI_signal_frame.
649 (output_cie): Handle cie->signal_frame.
650 (select_cie_for_fde): Don't share CIE if signal_frame flag is
651 different. Copy signal_frame from FDE to newly created CIE.
652 * doc/as.texinfo: Document .cfi_signal_frame.
653
f7d9e5c3
CD		 6542006-02-27 Carlos O'Donell <carlos@codesourcery.com>
655
656 * doc/Makefile.am: Add html target.
657 * doc/Makefile.in: Regenerate.
658 * po/Make-in: Add html target.
659
331d2d0d
L		 6602006-02-27 H.J. Lu <hongjiu.lu@intel.com>
661
8502d882 662 * config/tc-i386.c (output_insn): Support Intel Merom New
331d2d0d
L		 663 Instructions.
664
8502d882 665 * config/tc-i386.h (CpuMNI): New.
331d2d0d
L		 666 (CpuUnknownFlags): Add CpuMNI.
667
10156f83
DM		 6682006-02-24 David S. Miller <davem@sunset.davemloft.net>
669
670 * config/tc-sparc.c (priv_reg_table): Add entry for "gl".
671 (hpriv_reg_table): New table for hyperprivileged registers.
672 (sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged
673 register encoding.
674
6772dd07
DD		 6752006-02-24 DJ Delorie <dj@redhat.com>
676
677 * config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
678 (tc_gen_reloc): Don't define.
679 * config/tc-m32c.c (rl_for, relaxable): New convenience macros.
680 (OPTION_LINKRELAX): New.
681 (md_longopts): Add it.
682 (m32c_relax): New.
683 (md_parse_options): Set it.
684 (md_assemble): Emit relaxation relocs as needed.
685 (md_convert_frag): Emit relaxation relocs as needed.
686 (md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
687 (m32c_apply_fix): New.
688 (tc_gen_reloc): New.
689 (m32c_force_relocation): Force out jump relocs when relaxing.
690 (m32c_fix_adjustable): Return false if relaxing.
691
62b3e311
PB		 6922006-02-24 Paul Brook <paul@codesourcery.com>
693
694 * config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
695 arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
696 (struct asm_barrier_opt): Define.
697 (arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
698 (parse_psr): Accept V7M psr names.
699 (parse_barrier): New function.
700 (enum operand_parse_code): Add OP_oBARRIER.
701 (parse_operands): Implement OP_oBARRIER.
702 (do_barrier): New function.
703 (do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
704 (do_t_cpsi): Add V7M restrictions.
705 (do_t_mrs, do_t_msr): Validate V7M variants.
706 (md_assemble): Check for NULL variants.
707 (v7m_psrs, barrier_opt_names): New tables.
708 (insns): Add V7 instructions. Mark V6 instructions absent from V7M.
709 (md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
710 (arm_cpu_option_table): Add Cortex-M3, R4 and A8.
711 (arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
712 (struct cpu_arch_ver_table): Define.
713 (cpu_arch_ver): New.
714 (aeabi_set_public_attributes): Use cpu_arch_ver. Set
715 Tag_CPU_arch_profile.
716 * doc/c-arm.texi: Document new cpu and arch options.
717
59cf82fe
L		 7182006-02-23 H.J. Lu <hongjiu.lu@intel.com>
719
720 * config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
721
19a7219f
L		 7222006-02-23 H.J. Lu <hongjiu.lu@intel.com>
723
724 * config/tc-ia64.c: Update copyright years.
725
7f3dfb9c
L		 7262006-02-22 H.J. Lu <hongjiu.lu@intel.com>
727
728 * config/tc-ia64.c (specify_resource): Add the rule 17 from
729 SDM 2.2.
730
f40d1643
PB		 7312005-02-22 Paul Brook <paul@codesourcery.com>
732
733 * config/tc-arm.c (do_pld): Remove incorrect write to
734 inst.instruction.
735 (encode_thumb32_addr_mode): Use correct operand.
736
216d22bc
PB		 7372006-02-21 Paul Brook <paul@codesourcery.com>
738
739 * config/tc-arm.c (md_apply_fix): Fix off-by-one errors.
740
d70c5fc7
NC		 7412006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
742 Anil Paranjape <anilp1@kpitcummins.com>
743 Shilin Shakti <shilins@kpitcummins.com>
744
745 * Makefile.am: Add xc16x related entry.
746 * Makefile.in: Regenerate.
747 * configure.in: Added xc16x related entry.
748 * configure: Regenerate.
749 * config/tc-xc16x.h: New file
750 * config/tc-xc16x.c: New file
751 * doc/c-xc16x.texi: New file for xc16x
752 * doc/all.texi: Entry for xc16x
753 * doc/Makefile.texi: Added c-xc16x.texi
754 * NEWS: Announce the support for the new target.
755
aaa2ab3d
NH		 7562006-02-16 Nick Hudson <nick.hudson@dsl.pipex.com>
757
758 * configure.tgt: set emulation for mips-*-netbsd*
759
82de001f
JJ		 7602006-02-14 Jakub Jelinek <jakub@redhat.com>
761
762 * config.in: Rebuilt.
763
431ad2d0
BW		 7642006-02-13 Bob Wilson <bob.wilson@acm.org>
765
766 * config/tc-xtensa.c (xg_add_opcode_fix): Number operands starting
767 from 1, not 0, in error messages.
768 (md_assemble): Simplify special-case check for ENTRY instructions.
769 (tinsn_has_invalid_symbolic_operands): Do not include opcode and
770 operand in error message.
771
94089a50
JM		 7722006-02-13 Joseph S. Myers <joseph@codesourcery.com>
773
774 * configure.tgt (arm-*-linux-gnueabi*): Change to
775 arm-*-linux-*eabi*.
776
52de4c06
NC		 7772006-02-10 Nick Clifton <nickc@redhat.com>
778
70e45ad9
NC		 779 * config/tc-crx.c (check_range): Ensure that the sign bit of a
780 32-bit value is propagated into the upper bits of a 64-bit long.
781
52de4c06
NC		 782 * config/tc-arc.c (init_opcode_tables): Fix cast.
783 (arc_extoper, md_operand): Likewise.
784
21af2bbd
BW		 7852006-02-09 David Heine <dlheine@tensilica.com>
786
787 * config/tc-xtensa.c (xg_assembly_relax): Increment steps_taken for
788 each relaxation step.
789
75a706fc
L		 7902006-02-09 Eric Botcazou <ebotcazou@libertysurf.fr>
791
792 * configure.in (CHECK_DECLS): Add vsnprintf.
793 * configure: Regenerate.
794 * messages.c (errno.h, stdarg.h, varargs.h, va_list): Do not
795 include/declare here, but...
796 * as.h: Move code detecting VARARGS idiom to the top.
797 (errno.h, stdarg.h, varargs.h, va_list): ...here.
798 (vsnprintf): Declare if not already declared.
799
0d474464
L		 8002006-02-08 H.J. Lu <hongjiu.lu@intel.com>
801
802 * as.c (close_output_file): New.
803 (main): Register close_output_file with xatexit before
804 dump_statistics. Don't call output_file_close.
805
266abb8f
NS		 8062006-02-07 Nathan Sidwell <nathan@codesourcery.com>
807
808 * config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs,
809 mcf5329_control_regs): New.
810 (not_current_architecture, selected_arch, selected_cpu): New.
811 (m68k_archs, m68k_extensions): New.
812 (archs): Renamed to ...
813 (m68k_cpus): ... here. Adjust.
814 (n_arches): Remove.
815 (md_pseudo_table): Add arch and cpu directives.
816 (find_cf_chip, m68k_ip): Adjust table scanning.
817 (no_68851, no_68881): Remove.
818 (md_assemble): Lazily initialize.
819 (select_control_regs): Adjust cpu names. Add 5208, 5213, 5329.
820 (md_init_after_args): Move functionality to m68k_init_arch.
821 (mri_chip): Adjust table scanning.
822 (md_parse_option): Reimplement 'm' processing to add -march & -mcpu
823 options with saner parsing.
824 (m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension,
825 m68k_init_arch): New.
826 (s_m68k_cpu, s_m68k_arch): New.
827 (md_show_usage): Adjust.
828 (m68k_elf_final_processing): Set CF EF flags.
829 * config/tc-m68k.h (m68k_init_after_args): Remove.
830 (tc_init_after_args): Remove.
831 * doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options.
832 (M68k-Directives): Document .arch and .cpu directives.
833
134dcee5
AM		 8342006-02-05 Arnold Metselaar <arnold.metselaar@planet.nl>
835
836 * config/tc-z80.c (z80_start_line_hook): allow .equ and .defl as
837 synonyms for equ and defl.
838 (z80_cons_fix_new): New function.
839 (emit_byte): Disallow relative jumps to absolute locations.
840 (emit_data): Only handle defb, prototype changed, because defb is
841 now handled as pseudo-op rather than an instruction.
842 (instab): Entries for defb,defw,db,dw moved from here...
843 (md_pseudo_table): ... to here, use generic cons() for defw,dw.
844 Add entries for def24,def32,d24,d32.
845 (md_assemble): Improved error handling.
846 (md_apply_fix): New case BFD_RELOC_24, set fixP->fx_no_overflow to one.
847 * config/tc-z80.h (TC_CONS_FIX_NEW): Define.
848 (z80_cons_fix_new): Declare.
849 * doc/c-z80.texi (defb, db): Mention warning on overflow.
850 (def24,d24,def32,d32): New pseudo-ops.
851
a9931606
PB		 8522006-02-02 Paul Brook <paul@codesourcery.com>
853
854 * config/tc-arm.c (do_shift): Remove Thumb-1 constraint.
855
ef8d22e6
PB		 8562005-02-02 Paul Brook <paul@codesourcery.com>
857
858 * config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND,
859 T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR,
860 T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB,
861 T2_OPCODE_RSB): Define.
862 (thumb32_negate_data_op): New function.
863 (md_apply_fix): Use it.
864
e7da6241
BW		 8652006-01-31 Bob Wilson <bob.wilson@acm.org>
866
867 * config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbol
868 fields.
869 * config/tc-xtensa.h (xtensa_frag_type): Remove slot_sub_symbols field.
870 * config/tc-xtensa.c (md_apply_fix): Check for unexpected uses of
871 subtracted symbols.
872 (relaxation_requirements): Add pfinish_frag argument and use it to
873 replace setting tinsn->record_fix fields.
874 (xg_assemble_vliw_tokens): Adjust calls to relaxation_requirements
875 and vinsn_to_insnbuf. Remove references to record_fix and
876 slot_sub_symbols fields.
877 (xtensa_mark_narrow_branches): Delete unused code.
878 (is_narrow_branch_guaranteed_in_range): Handle expr that is not just
879 a symbol.
880 (convert_frag_immed): Adjust vinsn_to_insnbuf call and do not set
881 record_fix fields.
882 (tinsn_immed_from_frag): Remove code for handling slot_sub_symbols.
883 (vinsn_to_insnbuf): Change use of record_fixup argument, replacing use
884 of the record_fix field. Simplify error messages for unexpected
885 symbolic operands.
886 (set_expr_symbol_offset_diff): Delete.
887
79134647
PB		 8882006-01-31 Paul Brook <paul@codesourcery.com>
889
890 * config/tc-arm.c (arm_reg_parse): Check if reg is non-NULL.
891
e74cfd16
PB		 8922006-01-31 Paul Brook <paul@codesourcery.com>
893 Richard Earnshaw <rearnsha@arm.com>
894
895 * config/tc-arm.c: Use arm_feature_set.
896 (arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
897 arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
898 fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
899 New variables.
900 (insns): Use them.
901 (md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
902 md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
903 arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
904 s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
905 feature flags.
906 (arm_legacy_option_table, arm_option_cpu_value_table): New types.
907 (arm_opts): Move old cpu/arch options from here...
908 (arm_legacy_opts): ... to here.
909 (md_parse_option): Search arm_legacy_opts.
910 (arm_cpus, arm_archs, arm_extensions, arm_fpus)
911 (arm_float_abis, arm_eabis): Make const.
912
d47d412e
BW		 9132006-01-25 Bob Wilson <bob.wilson@acm.org>
914
915 * config/tc-xtensa.c (md_apply_fix): Set value to zero for PLT relocs.
916
b14273fe
JZ		 9172006-01-21 Jie Zhang <jie.zhang@analog.com>
918
919 * config/bfin-parse.y (asm_1): Check value range for 16 bit immediate
920 in load immediate intruction.
921
39cd1c76
JZ		 9222006-01-21 Jie Zhang <jie.zhang@analog.com>
923
924 * config/bfin-parse.y (value_match): Use correct conversion
925 specifications in template string for __FILE__ and __LINE__.
926 (binary): Ditto.
927 (unary): Ditto.
928
67a4f2b7
AO		 9292006-01-18 Alexandre Oliva <aoliva@redhat.com>
930
931 Introduce TLS descriptors for i386 and x86_64.
932 * config/tc-i386.c (tc_i386_fix_adjustable): Handle
933 BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC_CALL,
934 BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL.
935 (optimize_disp): Emit fix up for BFD_RELOC_386_TLS_DESC_CALL and
936 BFD_RELOC_X86_64_TLSDESC_CALL immediately, and clear the
937 displacement bits.
938 (build_modrm_byte): Set up zero modrm for TLS desc calls.
939 (lex_got): Handle @tlsdesc and @tlscall.
940 (md_apply_fix, tc_gen_reloc): Handle the new relocations.
941
8ad7c533
NC		 9422006-01-11 Nick Clifton <nickc@redhat.com>
943
944 Fixes for building on 64-bit hosts:
945 * config/tc-avr.c (mod_index): New union to allow conversion
946 between pointers and integers.
947 (md_begin, avr_ldi_expression): Use it.
948 * config/tc-i370.c (md_assemble): Add cast for argument to print
949 statement.
950 * config/tc-tic54x.c (subsym_substitute): Likewise.
951 * config/tc-mn10200.c (md_assemble): Use a union to convert the
952 opindex field of fr_cgen structure into a pointer so that it can
953 be stored in a frag.
954 * config/tc-mn10300.c (md_assemble): Likewise.
955 * config/tc-frv.c (frv_debug_tomcat): Use %p to print pointer
956 types.
957 * config/tc-v850.c: Replace uses of (int) casts with correct
958 types.
959
4dcb3903
L		 9602006-01-09 H.J. Lu <hongjiu.lu@intel.com>
961
962 PR gas/2117
963 * symbols.c (snapshot_symbol): Don't change a defined symbol.
964
e0f6ea40
HPN		 9652006-01-03 Hans-Peter Nilsson <hp@bitrange.com>
966
967 PR gas/2101
968 * config/tc-mmix.c (mmix_handle_mmixal): Don't treat #[0-9][FB] as
969 a local-label reference.
970
e88d958a 971For older changes see ChangeLog-2005
08d56133
NC		 972\f
973Local Variables:
974mode: change-log
975left-margin: 8
976fill-column: 74
977version-control: never
978End:
GDB Binutils - Deliverables
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