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Handle EV5 (21164/66/68) PALcode support.
[deliverable/binutils-gdb.git] / gas / config / alpha-opcode.h
CommitLineData
5749c497
KR		 1/*
2 * Mach Operating System
3 * Copyright (c) 1993 Carnegie Mellon University
4 * All Rights Reserved.
5 *
6 * Permission to use, copy, modify and distribute this software and its
7 * documentation is hereby granted, provided that both the copyright
8 * notice and this permission notice appear in all copies of the
9 * software, derivative works or modified versions, and any portions
10 * thereof, and that both notices appear in supporting documentation.
11 *
12 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
13 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
14 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
15 *
16 * Carnegie Mellon requests users of this software to return to
17 *
18 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
19 * School of Computer Science
20 * Carnegie Mellon University
21 * Pittsburgh PA 15213-3890
22 *
23 * any improvements or extensions that they make and grant Carnegie the
24 * rights to redistribute these changes.
25 */
26/*
27 * HISTORY
28 * 5-Oct-93 Alessandro Forin (af) at Carnegie-Mellon University
29 * First checkin.
30 *
5749c497
KR		 31 * Author: Alessandro Forin, Carnegie Mellon University
32 * Date: Jan 1993
33 */
34
35/* Table of opcodes for the alpha.
36 Copyright (C) 1989 Free Software Foundation, Inc.
37
38This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
39
40GAS/GDB is free software; you can redistribute it and/or modify
41it under the terms of the GNU General Public License as published by
42the Free Software Foundation; either version 1, or (at your option)
43any later version.
44
45GAS/GDB is distributed in the hope that it will be useful,
46but WITHOUT ANY WARRANTY; without even the implied warranty of
47MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
48GNU General Public License for more details.
49
50You should have received a copy of the GNU General Public License
51along with GAS or GDB; see the file COPYING. If not, write to
52the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
53
54#if !defined(__STDC__) && !defined(const)
55#define const
56#endif
57
58/*
59 * Structure of an opcode table entry.
60 */
61struct alpha_opcode
62{
63 const char *name;
64 const unsigned int match; /* fixed encoding part of instruction */
65 const int isa_float;
66 const char *args;
67};
68
69/*
70 All alpha opcodes are 32 bits, except for the `set' instruction (really
71 a macro), which is 64 bits. It is handled as a special case.
72
73 The match component is a mask saying which bits must match a
74 particular opcode in order for an instruction to be an instance
75 of that opcode.
76
77 The args component is a string containing one character
78 for each operand of the instruction.
79
80Kinds of operands:
81 1 ra register
82 2 rb register
83 3 rc register
84 r same register for ra and rc
85 R same register for ra and rb
86 e fa floating point register.
87 f fb floating point register.
88 g fc floating point register.
0952861c 89 I 26 bit immediate (PALcode function #)
5749c497
KR		 90 l 16 low bits of immediate
91 h 16 high(er) bits of immediate [Never used. KR]
92 L 22 bit PC relative immediate.
93 i 14 bit immediate jmp/jsr/ret operand -- PC-rel or not,
94 dependent on opcode
95 b 8 bit literal, shifted left 13 bits (literal in `operate' fmt)
96 G Base-register GET at address, needs macro-expansion
97 P Base-register PUT at address, needs macro-expansion
98 Bn builtin macro
99 t twelve bit displacement
100 8 eight bit index
101
102Syntactic elements
103 (
104 ) base register in "offset(base)" addressing
105 , separator
106
107Builtin functions (look like macros to the programmer)
108 %br the current base register
109 la %r,A load the (64bit) address in register %r
110 li %r,N load the constant N in register %r
111#if 0
112 lo(A) low 16 bits of Address (relocatable)
113 uml(A) med-low 16 bits, unchanged
114 umh(A) med-high 16 bits, unchanged
115 uhi(A) high 16 bits, unchanged
116 ml(A) med-low, adjusted viz sign of lo(A)
117 mh(A) med-high, adjusted viz sign of ml(A)
118 hi(A) high, adjusted viz sign of mh(A)
119#endif
120
121*/
122
123/* The order of the opcodes in this table is significant:
124
125 * The assembler requires that all instances of the same mnemonic must be
126 consecutive. If they aren't, the assembler will bomb at runtime.
127
128 * The disassembler should not care about the order of the opcodes. */
129
130static const struct alpha_opcode alpha_opcodes[] =
131{
132
133{ "ldgp", 0x00000000, 0, "3,l(1)Ba" }, /* builtin */
134{ "setgp", 0x00000000, 0, "0(1)Bb" }, /* builtin */
135
136{ "reml", 0x00000000, 0, "1,2,3B0" }, /* builtin */
137{ "divl", 0x00000000, 0, "1,2,3B1" }, /* builtin */
138{ "remq", 0x00000000, 0, "1,2,3B2" }, /* builtin */
139{ "divq", 0x00000000, 0, "1,2,3B3" }, /* builtin */
140{ "remlu", 0x00000000, 0, "1,2,3B4" }, /* builtin */
141{ "divlu", 0x00000000, 0, "1,2,3B5" }, /* builtin */
142{ "remqu", 0x00000000, 0, "1,2,3B6" }, /* builtin */
143{ "divqu", 0x00000000, 0, "1,2,3B7" }, /* builtin */
144
145{ "lda", 0x20000000, 0, "1,l(2)" }, /* 6o+5a+5b+16d */
146{ "lda", 0x20000000, 0, "1,G" }, /* regbase macro */
147{ "ldi", 0x201F0000, 0, "1,l"}, /* ldi ra,lit == lda ra,lit(r31) */
148{ "ldah", 0x24000000, 0, "1,l(2)" },
149{ "ldah", 0x24000000, 0, "1,G" }, /* regbase macro */
150{ "lui", 0x241F0000, 0, "1,l"}, /* lui ra,lit == ldah ra,lit(r31) */
151{ "ldil", 0x20000000, 0, "1,G" }, /* macro */
152{ "ldiq", 0x20000000, 0, "1,G" }, /* (broken) macro */
153
154{ "ldl", 0xa0000000, 0, "1,l(2)" },
155{ "ldl", 0xa0000000, 0, "1,G" }, /* regbase macro */
156{ "ldl_l", 0xa8000000, 0, "1,l(2)" },
157{ "ldl_l", 0xa8000000, 0, "1,G" }, /* regbase macro */
158{ "ldq", 0xa4000000, 0, "1,l(2)" },
159{ "ldq", 0xa4000000, 0, "1,G" }, /* regbase macro */
160{ "ldq_u", 0x2c000000, 0, "1,l(2)" },
161{ "ldq_u", 0x2c000000, 0, "1,G" }, /* regbase macro */
162{ "ldq_l", 0xac000000, 0, "1,l(2)" },
163{ "ldq_l", 0xac000000, 0, "1,G" }, /* regbase macro */
164
165{ "stl", 0xb0000000, 0, "1,l(2)" },
166{ "stl", 0xb0000000, 0, "1,P" }, /* regbase macro */
167{ "stl_c", 0xb8000000, 0, "1,l(2)" },
168{ "stl_c", 0xb8000000, 0, "1,P" }, /* regbase macro */
169{ "stq", 0xb4000000, 0, "1,l(2)" },
170{ "stq", 0xb4000000, 0, "1,P" }, /* regbase macro */
171{ "stq_u", 0x3c000000, 0, "1,l(2)" },
172{ "stq_u", 0x3c000000, 0, "1,P" }, /* regbase macro */
173{ "stq_c", 0xbc000000, 0, "1,l(2)" },
174{ "stq_c", 0xbc000000, 0, "1,P" }, /* regbase macro */
175
0952861c
KR		 176{ "ldb", 0, 0, "1,l(2)Bd" },
177{ "ldb", 0, 0, "1,PBd" },
178{ "ldbu", 0, 0, "1,l(2)Bd" },
179{ "ldbu", 0, 0, "1,PBd" },
180{ "ldw", 0, 0, "1,l(2)Bd" },
181{ "ldw", 0, 0, "1,PBd" },
182{ "ldwu", 0, 0, "1,l(2)Bd" },
183{ "ldwu", 0, 0, "1,PBd" },
184{ "stb", 0, 0, "1,l(2)Bd" },
185{ "stb", 0, 0, "1,PBd" },
186{ "stw", 0, 0, "1,l(2)Bd" },
187{ "stw", 0, 0, "1,PBd" },
188{ "ustw", 0, 0, "1,l(2)Bd" },
189{ "ustw", 0, 0, "1,PBd" },
190{ "ustl", 0, 0, "1,l(2)Bd" },
191{ "ustl", 0, 0, "1,PBd" },
192{ "ustq", 0, 0, "1,l(2)Bd" },
193{ "ustq", 0, 0, "1,PBd" },
194{ "uldw", 0, 0, "1,l(2)Bd" },
195{ "uldw", 0, 0, "1,PBd" },
196{ "uldwu", 0, 0, "1,l(2)Bd" },
197{ "uldwu", 0, 0, "1,PBd" },
198{ "uldl", 0, 0, "1,l(2)Bd" },
199{ "uldl", 0, 0, "1,PBd" },
200{ "uldq", 0, 0, "1,l(2)Bd" },
201{ "uldq", 0, 0, "1,PBd" },
202
5749c497
KR		 203{ "beq", 0xe4000000, 0, "1,L" }, /* 6o+5a+21d */
204{ "bne", 0xf4000000, 0, "1,L" },
205{ "blt", 0xe8000000, 0, "1,L" },
206{ "ble", 0xec000000, 0, "1,L" },
207{ "bgt", 0xfc000000, 0, "1,L" },
208{ "bge", 0xf8000000, 0, "1,L" },
209{ "blbc", 0xe0000000, 0, "1,L" },
210{ "blbs", 0xf0000000, 0, "1,L" },
211
212{ "br", 0xc0000000, 0, "1,L" },
213{ "br", 0xc3e00000, 0, "L" }, /* macro: br zero,disp */
214{ "bsr", 0xd0000000, 0, "1,L" },
215{ "bsr", 0xd3500000, 0, "L" }, /* macro: bsr $ra,L */
216
217{ "jmp", 0x68000000, 0, "1,(2),i" }, /* 6o+5a+5b+2A+14d */
218{ "jmp", 0x68000000, 0, "1,(2)" },
219{ "jsr", 0x68004000, 0, "1,(2),i" },
220{ "jsr", 0x68004000, 0, "1,(2)" },
221{ "jsr", 0x68004000, 0, "1,Bc" }, /* macro: lda $pv,L;jsr .. */
222{ "ret", 0x68008000, 0, "1,(2),i" },
223{ "ret", 0x68008000, 0, "1,(2)" },
224{ "ret", 0x6b5a8000, 0, "" }, /* macro: ret ra,(ra) */
225{ "ret", 0x6be08000, 0, "(2)" }, /* macro: ret zero,(2) */
226{ "ret", 0x681a8000, 0, "1" }, /* macro: ret 1,(ra) */
227{ "jcr", 0x6800c000, 0, "1,(2)" },
228{ "jsr_coroutine", 0x6800c000, 0, "1,(2)" },
229
230{ "addl", 0x40000000, 0, "1,2,3" }, /* 6o+5a+5b+4z+7f+5c */
231{ "addl", 0x40001000, 0, "1,b,3" }, /* 6o+5a+8n+1+7f+5c */
232{ "addl/v", 0x40000800, 0, "1,2,3" },
233{ "addl/v", 0x40001800, 0, "1,b,3" },
234{ "s4addl", 0x40000040, 0, "1,2,3" },
235{ "s4addl", 0x40001040, 0, "1,b,3" },
236{ "s8addl", 0x40000240, 0, "1,2,3" },
237{ "s8addl", 0x40001240, 0, "1,b,3" },
238{ "addq", 0x40000400, 0, "1,2,3" },
239{ "addq", 0x40001400, 0, "1,b,3" },
240{ "addq/v", 0x40000c00, 0, "1,2,3" },
241
242{ "addq/v", 0x40001c00, 0, "1,b,3" },
243{ "s4addq", 0x40000440, 0, "1,2,3" },
244{ "s4addq", 0x40001440, 0, "1,b,3" },
245{ "s8addq", 0x40000640, 0, "1,2,3" },
246{ "s8addq", 0x40001640, 0, "1,b,3" },
247{ "cmpeq", 0x400005a0, 0, "1,2,3" },
248{ "cmpeq", 0x400015a0, 0, "1,b,3" },
249{ "cmplt", 0x400009a0, 0, "1,2,3" },
250{ "cmplt", 0x400019a0, 0, "1,b,3" },
251{ "cmple", 0x40000da0, 0, "1,2,3" },
252{ "cmple", 0x40001da0, 0, "1,b,3" },
253{ "cmpult", 0x400003a0, 0, "1,2,3" },
254{ "cmpult", 0x400013a0, 0, "1,b,3" },
255{ "cmpule", 0x400007a0, 0, "1,2,3" },
256{ "cmpule", 0x400017a0, 0, "1,b,3" },
257{ "subl", 0x40000120, 0, "1,2,3" },
258{ "subl", 0x40001120, 0, "1,b,3" },
259{ "subl/v", 0x40000920, 0, "1,2,3" },
260{ "subl/v", 0x40001920, 0, "1,b,3" },
261{ "s4subl", 0x40000160, 0, "1,2,3" },
262{ "s4subl", 0x40001160, 0, "1,b,3" },
263{ "s8subl", 0x40000360, 0, "1,2,3" },
264{ "s8subl", 0x40001360, 0, "1,b,3" },
265{ "subq", 0x40000520, 0, "1,2,3" },
266{ "subq", 0x40001520, 0, "1,b,3" },
267{ "subq/v", 0x40000d20, 0, "1,2,3" },
268{ "subq/v", 0x40001d20, 0, "1,b,3" },
269{ "s4subq", 0x40000560, 0, "1,2,3" },
270{ "s4subq", 0x40001560, 0, "1,b,3" },
271{ "s8subq", 0x40000760, 0, "1,2,3" },
272{ "s8subq", 0x40001760, 0, "1,b,3" },
273{ "cmpbge", 0x400001e0, 0, "1,2,3" },
274{ "cmpbge", 0x400011e0, 0, "1,b,3" },
275
276{ "mull", 0x4c000000, 0, "1,2,3" },
277{ "mull", 0x4c001000, 0, "1,b,3" },
278{ "mull/v", 0x4c000800, 0, "1,2,3" },
279{ "mull/v", 0x4c001800, 0, "1,b,3" },
280{ "mulq", 0x4c000400, 0, "1,2,3" },
281{ "mulq", 0x4c001400, 0, "1,b,3" },
282{ "mulq/v", 0x4c000c00, 0, "1,2,3" },
283{ "mulq/v", 0x4c001c00, 0, "1,b,3" },
284{ "umulh", 0x4c000600, 0, "1,2,3" },
285{ "umulh", 0x4c001600, 0, "1,b,3" },
286
287{ "clr", 0x47ff0400, 0, "3" }, /* macro: or zero,zero,rc */
288{ "negl", 0x43e00120, 0, "2,3" }, /* macro: subl zero,rb,rc */
289{ "negl_v", 0x43e00920, 0, "2,3" }, /* macro: subl_v zero,rb,rc */
290{ "negq", 0x43e00520, 0, "2,3" }, /* macro: subq zero,rb,rc */
291{ "negq_v", 0x43e00d20, 0, "2,3" }, /* macro: subq_v zero,rb,rc */
292{ "sextl", 0x43e00000, 0, "2,3" }, /* macro: addl zero,rb,rc */
293
294{ "and", 0x44000000, 0, "1,2,3" },
295{ "and", 0x44001000, 0, "1,b,3" },
296{ "and", 0x44000000, 0, "r,2" }, /* macro: and ra,rb,ra */
297{ "and", 0x44001000, 0, "r,b" }, /* macro: and ra,#,ra */
298{ "or", 0x44000400, 0, "1,2,3" },
299{ "or", 0x44001400, 0, "1,b,3" },
300{ "or", 0x44000400, 0, "r,2" }, /* macro: or ra,rb,ra */
301{ "or", 0x44001400, 0, "r,b" }, /* macro: or ra,#,ra */
302{ "bis", 0x44000400, 0, "1,2,3" },
303{ "bis", 0x44001400, 0, "1,b,3" },
304{ "bis", 0x44000400, 0, "r,2" }, /* macro: or ra,rb,ra */
305{ "bis", 0x44001400, 0, "r,b" }, /* macro: or ra,#,ra */
306{ "movi", 0x47E01400, 0, "b,3"}, /* movi lit,rc == bis r31,lit,rc */
307{ "xor", 0x44000800, 0, "1,2,3" },
308{ "xor", 0x44001800, 0, "1,b,3" },
309{ "xor", 0x44000800, 0, "r,2" }, /* macro: ra,rb,ra */
310{ "xor", 0x44001800, 0, "r,b" }, /* macro: ra,#,ra */
311{ "andnot", 0x44000100, 0, "1,2,3" },
312{ "andnot", 0x44001100, 0, "1,b,3" },
313{ "andnot", 0x44000100, 0, "r,2" }, /* macro: ra,#,ra */
314{ "andnot", 0x44001100, 0, "r,b" }, /* macro: ra,#,ra */
315{ "bic", 0x44000100, 0, "1,2,3" },
316{ "bic", 0x44001100, 0, "1,b,3" },
317{ "bic", 0x44000100, 0, "r,2" }, /* macro: ra,#,ra */
318{ "bic", 0x44001100, 0, "r,b" }, /* macro: ra,#,ra */
319{ "ornot", 0x44000500, 0, "1,2,3" },
320{ "ornot", 0x44001500, 0, "1,b,3" },
321{ "ornot", 0x44000500, 0, "r,2" }, /* macro: ra,#,ra */
322{ "ornot", 0x44001500, 0, "r,b" }, /* macro: ra,#,ra */
323{ "not", 0x47e00500, 0, "2,3" }, /* macro: ornot zero,.. */
324{ "not", 0x47e01500, 0, "b,3" },
325{ "xornot", 0x44000900, 0, "1,2,3" },
326{ "xornot", 0x44001900, 0, "1,b,3" },
327{ "xornot", 0x44000900, 0, "r,2" }, /* macro: ra,#,ra */
328{ "xornot", 0x44001900, 0, "r,b" }, /* macro: ra,#,ra */
329{ "eqv", 0x44000900, 0, "1,2,3" },
330{ "eqv", 0x44001900, 0, "1,b,3" },
331{ "eqv", 0x44000900, 0, "r,2" }, /* macro: ra,#,ra */
332{ "eqv", 0x44001900, 0, "r,b" }, /* macro: ra,#,ra */
333
334{ "cmoveq", 0x44000480, 0, "1,2,3" },
335{ "cmoveq", 0x44001480, 0, "1,b,3" },
336{ "cmovne", 0x440004c0, 0, "1,2,3" },
337{ "cmovne", 0x440014c0, 0, "1,b,3" },
338{ "cmovlt", 0x44000880, 0, "1,2,3" },
339{ "cmovlt", 0x44001880, 0, "1,b,3" },
340{ "cmovle", 0x44000c80, 0, "1,2,3" },
341{ "cmovle", 0x44001c80, 0, "1,b,3" },
342{ "cmovgt", 0x44000cc0, 0, "1,2,3" },
343{ "cmovgt", 0x44001cc0, 0, "1,b,3" },
344{ "cmovge", 0x440008c0, 0, "1,2,3" },
345{ "cmovge", 0x440018c0, 0, "1,b,3" },
346{ "cmovlbc", 0x440002c0, 0, "1,2,3" },
347{ "cmovlbc", 0x440012c0, 0, "1,b,3" },
348{ "cmovlbs", 0x44000280, 0, "1,2,3" },
349{ "cmovlbs", 0x44001280, 0, "1,b,3" },
350
351{ "sll", 0x48000720, 0, "1,2,3" },
352{ "sll", 0x48001720, 0, "1,b,3" },
353{ "srl", 0x48000680, 0, "1,2,3" },
354{ "srl", 0x48001680, 0, "1,b,3" },
355{ "sra", 0x48000780, 0, "1,2,3" },
356{ "sra", 0x48001780, 0, "1,b,3" },
357
358{ "extbl", 0x480000c0, 0, "1,2,3" },
359{ "extbl", 0x480010c0, 0, "1,b,3" },
360{ "extwl", 0x480002c0, 0, "1,2,3" },
361{ "extwl", 0x480012c0, 0, "1,b,3" },
362{ "extll", 0x480004c0, 0, "1,2,3" },
363{ "extll", 0x480014c0, 0, "1,b,3" },
364{ "extql", 0x480006c0, 0, "1,2,3" },
365{ "extql", 0x480016c0, 0, "1,b,3" },
366{ "extwh", 0x48000b40, 0, "1,2,3" },
367{ "extwh", 0x48001b40, 0, "1,b,3" },
368{ "extlh", 0x48000d40, 0, "1,2,3" },
369{ "extlh", 0x48001d40, 0, "1,b,3" },
370{ "extqh", 0x48000f40, 0, "1,2,3" },
371{ "extqh", 0x48001f40, 0, "1,b,3" },
372{ "insbl", 0x48000160, 0, "1,2,3" },
373{ "insbl", 0x48001160, 0, "1,b,3" },
374{ "inswl", 0x48000360, 0, "1,2,3" },
375{ "inswl", 0x48001360, 0, "1,b,3" },
376{ "insll", 0x48000560, 0, "1,2,3" },
377{ "insll", 0x48001560, 0, "1,b,3" },
378{ "insql", 0x48000760, 0, "1,2,3" },
379{ "insql", 0x48001760, 0, "1,b,3" },
380{ "inswh", 0x48000ae0, 0, "1,2,3" },
381{ "inswh", 0x48001ae0, 0, "1,b,3" },
382{ "inslh", 0x48000ce0, 0, "1,2,3" },
383{ "inslh", 0x48001ce0, 0, "1,b,3" },
384{ "insqh", 0x48000ee0, 0, "1,2,3" },
385{ "insqh", 0x48001ee0, 0, "1,b,3" },
386{ "mskbl", 0x48000040, 0, "1,2,3" },
387{ "mskbl", 0x48001040, 0, "1,b,3" },
388{ "mskwl", 0x48000240, 0, "1,2,3" },
389{ "mskwl", 0x48001240, 0, "1,b,3" },
390{ "mskll", 0x48000440, 0, "1,2,3" },
391{ "mskll", 0x48001440, 0, "1,b,3" },
392{ "mskql", 0x48000640, 0, "1,2,3" },
393{ "mskql", 0x48001640, 0, "1,b,3" },
394{ "mskwh", 0x48000a40, 0, "1,2,3" },
395{ "mskwh", 0x48001a40, 0, "1,b,3" },
396{ "msklh", 0x48000c40, 0, "1,2,3" },
397{ "msklh", 0x48001c40, 0, "1,b,3" },
398{ "mskqh", 0x48000e40, 0, "1,2,3" },
399{ "mskqh", 0x48001e40, 0, "1,b,3" },
400{ "zap", 0x48000600, 0, "1,2,3" },
401{ "zap", 0x48001600, 0, "1,b,3" },
402{ "zapnot", 0x48000620, 0, "1,2,3" },
403{ "zapnot", 0x48001620, 0, "1,b,3" },
404
405/*
406 * Floating point instructions
407 */
408{ "ldf", 0x80000000, 1, "e,l(2)" }, /* 6o+5a+5b+16d */
409{ "ldf", 0x80000000, 1, "e,G" }, /* regbase macro */
410{ "ldg", 0x84000000, 1, "e,l(2)" },
411{ "ldg", 0x84000000, 1, "e,G" }, /* regbase macro */
412{ "lds", 0x88000000, 1, "e,l(2)" },
413{ "lds", 0x88000000, 1, "e,G" }, /* regbase macro */
414{ "ldt", 0x8c000000, 1, "e,l(2)" },
415{ "ldt", 0x8c000000, 1, "e,G" }, /* regbase macro */
416{ "stf", 0x90000000, 1, "e,l(2)" },
417{ "stf", 0x90000000, 1, "e,P" }, /* regbase macro */
418{ "stg", 0x94000000, 1, "e,l(2)" },
419{ "stg", 0x94000000, 1, "e,P" }, /* regbase macro */
420{ "sts", 0x98000000, 1, "e,l(2)" },
421{ "sts", 0x98000000, 1, "e,P" }, /* regbase macro */
422{ "stt", 0x9c000000, 1, "e,l(2)" },
423{ "stt", 0x9c000000, 1, "e,P" }, /* regbase macro */
40cd35ff
KR		 424{ "ldif", 0x80000000, 1, "e,F" },
425{ "ldig", 0x84000000, 1, "e,F" },
426{ "ldis", 0x88000000, 1, "e,F" },
427{ "ldit", 0x8c000000, 1, "e,F" },
5749c497
KR		 428
429{ "fbeq", 0xc4000000, 1, "e,L" }, /* 6o+5a+21d */
430{ "fbne", 0xd4000000, 1, "e,L" },
431{ "fblt", 0xc8000000, 1, "e,L" },
432{ "fble", 0xcc000000, 1, "e,L" },
433{ "fbgt", 0xdc000000, 1, "e,L" },
434{ "fbge", 0xd8000000, 1, "e,L" },
435
436/* All subsets (opcode 0x17) */
437{ "cpys", 0x5c000400, 1, "e,f,g" }, /* 6o+5a+5b+11f+5c */
438{ "cpysn", 0x5c000420, 1, "e,f,g" },
439{ "cpyse", 0x5c000440, 1, "e,f,g" },
440
441{ "cvtlq", 0x5fe00200, 1, "f,g" },
442{ "cvtql", 0x5fe00600, 1, "f,g" },
443{ "cvtql/v", 0x5fe02600, 1, "f,g" },
444{ "cvtql/sv", 0x5fe06600, 1, "f,g" },
445
446{ "fcmoveq", 0x5c000540, 1, "e,f,g" },
447{ "fcmovne", 0x5c000560, 1, "e,f,g" },
448{ "fcmovlt", 0x5c000580, 1, "e,f,g" },
449{ "fcmovle", 0x5c0005c0, 1, "e,f,g" },
450{ "fcmovgt", 0x5c0005e0, 1, "e,f,g" },
451{ "fcmovge", 0x5c0005a0, 1, "e,f,g" },
452
453{ "mf_fpcr", 0x5c0004a0, 1, "E" },
454{ "mt_fpcr", 0x5c000480, 1, "E" },
455
456/* Vax subset (opcode 0x15) */
457{ "addf", 0x54001000, 1, "e,f,g" },
458{ "addf/c", 0x54000000, 1, "e,f,g" },
459{ "addf/u", 0x54003000, 1, "e,f,g" },
460{ "addf/uc", 0x54002000, 1, "e,f,g" },
461{ "addf/s", 0x54009000, 1, "e,f,g" },
462{ "addf/sc", 0x54008000, 1, "e,f,g" },
463{ "addf/su", 0x5400b000, 1, "e,f,g" },
464{ "addf/suc", 0x5400a000, 1, "e,f,g" },
465{ "addg", 0x54001400, 1, "e,f,g" },
466{ "addg/c", 0x54000400, 1, "e,f,g" },
467{ "addg/u", 0x54003400, 1, "e,f,g" },
468{ "addg/uc", 0x54002400, 1, "e,f,g" },
469{ "addg/s", 0x54009400, 1, "e,f,g" },
470{ "addg/sc", 0x54008400, 1, "e,f,g" },
471{ "addg/su", 0x5400b400, 1, "e,f,g" },
472{ "addg/suc", 0x5400a400, 1, "e,f,g" },
473{ "subf", 0x54001020, 1, "e,f,g" },
474{ "subf/c", 0x54000020, 1, "e,f,g" },
475{ "subf/u", 0x54003020, 1, "e,f,g" },
476{ "subf/uc", 0x54002020, 1, "e,f,g" },
477{ "subf/s", 0x54009020, 1, "e,f,g" },
478{ "subf/sc", 0x54008020, 1, "e,f,g" },
479{ "subf/su", 0x5400b020, 1, "e,f,g" },
480{ "subf/suc", 0x5400a020, 1, "e,f,g" },
481{ "subg", 0x54001420, 1, "e,f,g" },
482{ "subg/c", 0x54000420, 1, "e,f,g" },
483{ "subg/u", 0x54003420, 1, "e,f,g" },
484{ "subg/uc", 0x54002420, 1, "e,f,g" },
485{ "subg/s", 0x54009420, 1, "e,f,g" },
486{ "subg/sc", 0x54008420, 1, "e,f,g" },
487{ "subg/su", 0x5400b420, 1, "e,f,g" },
488{ "subg/suc", 0x5400a420, 1, "e,f,g" },
489
490{ "cmpgeq", 0x540014a0, 1, "e,f,g" },
491{ "cmpgeq/s", 0x540094a0, 1, "e,f,g" },
492{ "cmpglt", 0x540014c0, 1, "e,f,g" },
493{ "cmpglt/s", 0x540094c0, 1, "e,f,g" },
494{ "cmpgle", 0x540014e0, 1, "e,f,g" },
495{ "cmpgle/s", 0x540094e0, 1, "e,f,g" },
496
497{ "cvtgq", 0x57e015e0, 1, "f,g" },
498{ "cvtgq/c", 0x57e005e0, 1, "f,g" },
499{ "cvtgq/v", 0x57e035e0, 1, "f,g" },
500{ "cvtgq/vc", 0x57e025e0, 1, "f,g" },
501{ "cvtgq/s", 0x57e095e0, 1, "f,g" },
502{ "cvtgq/sc", 0x57e085e0, 1, "f,g" },
503{ "cvtgq/sv", 0x57e0b5e0, 1, "f,g" },
504{ "cvtgq/svc", 0x57e0a5e0, 1, "f,g" },
505{ "cvtqf", 0x57e01780, 1, "f,g" },
506{ "cvtqf/c", 0x57e00780, 1, "f,g" },
507{ "cvtqf/s", 0x57e09780, 1, "f,g" },
508{ "cvtqf/sc", 0x57e08780, 1, "f,g" },
509{ "cvtqg", 0x57e017c0, 1, "f,g" },
510{ "cvtqg/c", 0x57e007c0, 1, "f,g" },
511{ "cvtqg/s", 0x57e097c0, 1, "f,g" },
512{ "cvtqg/sc", 0x57e087c0, 1, "f,g" },
513{ "cvtdg", 0x57e013c0, 1, "f,g" },
514{ "cvtdg/c", 0x57e003c0, 1, "f,g" },
515{ "cvtdg/u", 0x57e033c0, 1, "f,g" },
516{ "cvtdg/uc", 0x57e023c0, 1, "f,g" },
517{ "cvtdg/s", 0x57e093c0, 1, "f,g" },
518{ "cvtdg/sc", 0x57e083c0, 1, "f,g" },
519{ "cvtdg/su", 0x57e0b3c0, 1, "f,g" },
520{ "cvtdg/suc", 0x57e0a3c0, 1, "f,g" },
521{ "cvtgd", 0x57e015a0, 1, "f,g" },
522{ "cvtgd/c", 0x57e005a0, 1, "f,g" },
523{ "cvtgd/u", 0x57e035a0, 1, "f,g" },
524{ "cvtgd/uc", 0x57e025a0, 1, "f,g" },
525{ "cvtgd/s", 0x57e095a0, 1, "f,g" },
526{ "cvtgd/sc", 0x57e085a0, 1, "f,g" },
527{ "cvtgd/su", 0x57e0b5a0, 1, "f,g" },
528{ "cvtgd/suc", 0x57e0a5a0, 1, "f,g" },
529{ "cvtgf", 0x57e01580, 1, "f,g" },
530{ "cvtgf/c", 0x57e00580, 1, "f,g" },
531{ "cvtgf/u", 0x57e03580, 1, "f,g" },
532{ "cvtgf/uc", 0x57e02580, 1, "f,g" },
533{ "cvtgf/s", 0x57e09580, 1, "f,g" },
534{ "cvtgf/sc", 0x57e08580, 1, "f,g" },
535{ "cvtgf/su", 0x57e0b580, 1, "f,g" },
536{ "cvtgf/suc", 0x57e0a580, 1, "f,g" },
537
538{ "divf", 0x54001060, 1, "e,f,g" },
539{ "divf/c", 0x54000060, 1, "e,f,g" },
540{ "divf/u", 0x54003060, 1, "e,f,g" },
541{ "divf/uc", 0x54002060, 1, "e,f,g" },
542{ "divf/s", 0x54009060, 1, "e,f,g" },
543{ "divf/sc", 0x54008060, 1, "e,f,g" },
544{ "divf/su", 0x5400b060, 1, "e,f,g" },
545{ "divf/suc", 0x5400a060, 1, "e,f,g" },
546{ "divg", 0x54001460, 1, "e,f,g" },
547{ "divg/c", 0x54000460, 1, "e,f,g" },
548{ "divg/u", 0x54003460, 1, "e,f,g" },
549{ "divg/uc", 0x54002460, 1, "e,f,g" },
550{ "divg/s", 0x54009460, 1, "e,f,g" },
551{ "divg/sc", 0x54008460, 1, "e,f,g" },
552{ "divg/su", 0x5400b460, 1, "e,f,g" },
553{ "divg/suc", 0x5400a460, 1, "e,f,g" },
554{ "mulf", 0x54001040, 1, "e,f,g" },
555{ "mulf/c", 0x54000040, 1, "e,f,g" },
556{ "mulf/u", 0x54003040, 1, "e,f,g" },
557{ "mulf/uc", 0x54002040, 1, "e,f,g" },
558{ "mulf/s", 0x54009040, 1, "e,f,g" },
559{ "mulf/sc", 0x54008040, 1, "e,f,g" },
560{ "mulf/su", 0x5400b040, 1, "e,f,g" },
561{ "mulf/suc", 0x5400a040, 1, "e,f,g" },
562{ "mulg", 0x54001440, 1, "e,f,g" },
563{ "mulg/c", 0x54000440, 1, "e,f,g" },
564{ "mulg/u", 0x54003440, 1, "e,f,g" },
565{ "mulg/uc", 0x54002440, 1, "e,f,g" },
566{ "mulg/s", 0x54009440, 1, "e,f,g" },
567{ "mulg/sc", 0x54008440, 1, "e,f,g" },
568{ "mulg/su", 0x5400b440, 1, "e,f,g" },
569{ "mulg/suc", 0x5400a440, 1, "e,f,g" },
570
571/* IEEE subset (opcode 0x16) */
572{ "adds", 0x58001000, 1, "e,f,g" },
573{ "adds/c", 0x58000000, 1, "e,f,g" },
574{ "adds/m", 0x58000800, 1, "e,f,g" },
575{ "adds/d", 0x58001800, 1, "e,f,g" },
576{ "adds/u", 0x58003000, 1, "e,f,g" },
577{ "adds/uc", 0x58002000, 1, "e,f,g" },
578{ "adds/um", 0x58002800, 1, "e,f,g" },
579{ "adds/ud", 0x58003800, 1, "e,f,g" },
580{ "adds/su", 0x5800b000, 1, "e,f,g" },
581{ "adds/suc", 0x5800a000, 1, "e,f,g" },
582{ "adds/sum", 0x5800a800, 1, "e,f,g" },
583{ "adds/sud", 0x5800b800, 1, "e,f,g" },
584{ "adds/sui", 0x5800f000, 1, "e,f,g" },
585{ "adds/suic", 0x5800e000, 1, "e,f,g" },
586{ "adds/suim", 0x5800e800, 1, "e,f,g" },
587{ "adds/suid", 0x5800f800, 1, "e,f,g" },
588{ "addt", 0x58001400, 1, "e,f,g" },
589{ "addt/c", 0x58000400, 1, "e,f,g" },
590{ "addt/m", 0x58000c00, 1, "e,f,g" },
591{ "addt/d", 0x58001c00, 1, "e,f,g" },
592{ "addt/u", 0x58003400, 1, "e,f,g" },
593{ "addt/uc", 0x58002400, 1, "e,f,g" },
594{ "addt/um", 0x58002c00, 1, "e,f,g" },
595{ "addt/ud", 0x58003c00, 1, "e,f,g" },
596{ "addt/su", 0x5800b400, 1, "e,f,g" },
597{ "addt/suc", 0x5800a400, 1, "e,f,g" },
598{ "addt/sum", 0x5800ac00, 1, "e,f,g" },
599{ "addt/sud", 0x5800bc00, 1, "e,f,g" },
600{ "addt/sui", 0x5800f400, 1, "e,f,g" },
601{ "addt/suic", 0x5800e400, 1, "e,f,g" },
602{ "addt/suim", 0x5800ec00, 1, "e,f,g" },
603{ "addt/suid", 0x5800fc00, 1, "e,f,g" },
604{ "subs", 0x58001020, 1, "e,f,g" },
605{ "subs/c", 0x58000020, 1, "e,f,g" },
606{ "subs/m", 0x58000820, 1, "e,f,g" },
607{ "subs/d", 0x58001820, 1, "e,f,g" },
608{ "subs/u", 0x58003020, 1, "e,f,g" },
609{ "subs/uc", 0x58002020, 1, "e,f,g" },
610{ "subs/um", 0x58002820, 1, "e,f,g" },
611{ "subs/ud", 0x58003820, 1, "e,f,g" },
612{ "subs/su", 0x5800b020, 1, "e,f,g" },
613{ "subs/suc", 0x5800a020, 1, "e,f,g" },
614{ "subs/sum", 0x5800a820, 1, "e,f,g" },
615{ "subs/sud", 0x5800b820, 1, "e,f,g" },
616{ "subs/sui", 0x5800f020, 1, "e,f,g" },
617{ "subs/suic", 0x5800e020, 1, "e,f,g" },
618{ "subs/suim", 0x5800e820, 1, "e,f,g" },
619{ "subs/suid", 0x5800f820, 1, "e,f,g" },
620{ "subt", 0x58001420, 1, "e,f,g" },
621{ "subt/c", 0x58000420, 1, "e,f,g" },
622{ "subt/m", 0x58000c20, 1, "e,f,g" },
623{ "subt/d", 0x58001c20, 1, "e,f,g" },
624{ "subt/u", 0x58003420, 1, "e,f,g" },
625{ "subt/uc", 0x58002420, 1, "e,f,g" },
626{ "subt/um", 0x58002c20, 1, "e,f,g" },
627{ "subt/ud", 0x58003c20, 1, "e,f,g" },
628{ "subt/su", 0x5800b420, 1, "e,f,g" },
629{ "subt/suc", 0x5800a420, 1, "e,f,g" },
630{ "subt/sum", 0x5800ac20, 1, "e,f,g" },
631{ "subt/sud", 0x5800bc20, 1, "e,f,g" },
632{ "subt/sui", 0x5800f420, 1, "e,f,g" },
633{ "subt/suic", 0x5800e420, 1, "e,f,g" },
634{ "subt/suim", 0x5800ec20, 1, "e,f,g" },
635{ "subt/suid", 0x5800fc20, 1, "e,f,g" },
636
637{ "cmpteq", 0x580014a0, 1, "e,f,g" },
638{ "cmpteq/su", 0x5800b4a0, 1, "e,f,g" },
639{ "cmptlt", 0x580014c0, 1, "e,f,g" },
640{ "cmptlt/su", 0x5800b4c0, 1, "e,f,g" },
641{ "cmptle", 0x580014e0, 1, "e,f,g" },
642{ "cmptle/su", 0x5800b4e0, 1, "e,f,g" },
643{ "cmptun", 0x58001480, 1, "e,f,g" },
644{ "cmptun/su", 0x5800b480, 1, "e,f,g" },
645
646{ "cvttq", 0x5be015e0, 1, "f,g" },
647{ "cvttq/c", 0x5be005e0, 1, "f,g" },
648{ "cvttq/v", 0x5be035e0, 1, "f,g" },
649{ "cvttq/vc", 0x5be025e0, 1, "f,g" },
650{ "cvttq/sv", 0x5be0b5e0, 1, "f,g" },
651{ "cvttq/svc", 0x5be0a5e0, 1, "f,g" },
652{ "cvttq/svi", 0x5be0f5e0, 1, "f,g" },
653{ "cvttq/svic", 0x5be0e5e0, 1, "f,g" },
654{ "cvtqs", 0x5be01780, 1, "f,g" },
655{ "cvtqs/c", 0x5be00780, 1, "f,g" },
656{ "cvtqs/m", 0x5be00f80, 1, "f,g" },
657{ "cvtqs/d", 0x5be01f80, 1, "f,g" },
658{ "cvtqs/sui", 0x5be0f780, 1, "f,g" },
659{ "cvtqs/suic", 0x5be0e780, 1, "f,g" },
660{ "cvtqs/suim", 0x5be0ef80, 1, "f,g" },
661{ "cvtqs/suid", 0x5be0ff80, 1, "f,g" },
662{ "cvtqt", 0x5be017c0, 1, "f,g" },
663{ "cvtqt/c", 0x5be007c0, 1, "f,g" },
664{ "cvtqt/m", 0x5be00fc0, 1, "f,g" },
665{ "cvtqt/d", 0x5be01fc0, 1, "f,g" },
666{ "cvtqt/sui", 0x5be0f7c0, 1, "f,g" },
667{ "cvtqt/suic", 0x5be0e7c0, 1, "f,g" },
668{ "cvtqt/suim", 0x5be0efc0, 1, "f,g" },
669{ "cvtqt/suid", 0x5be0ffc0, 1, "f,g" },
670{ "cvtts", 0x5be01580, 1, "f,g" },
671{ "cvtts/c", 0x5be00580, 1, "f,g" },
672{ "cvtts/m", 0x5be00d80, 1, "f,g" },
673{ "cvtts/d", 0x5be01d80, 1, "f,g" },
674{ "cvtts/u", 0x5be03580, 1, "f,g" },
675{ "cvtts/uc", 0x5be02580, 1, "f,g" },
676{ "cvtts/um", 0x5be02d80, 1, "f,g" },
677{ "cvtts/ud", 0x5be03d80, 1, "f,g" },
678{ "cvtts/su", 0x5be0b580, 1, "f,g" },
679{ "cvtts/suc", 0x5be0a580, 1, "f,g" },
680{ "cvtts/sum", 0x5be0ad80, 1, "f,g" },
681{ "cvtts/sud", 0x5be0bd80, 1, "f,g" },
682{ "cvtts/sui", 0x5be0f580, 1, "f,g" },
683{ "cvtts/suic", 0x5be0e580, 1, "f,g" },
684{ "cvtts/suim", 0x5be0ed80, 1, "f,g" },
685{ "cvtts/suid", 0x5be0fd80, 1, "f,g" },
686
687{ "divs", 0x58001060, 1, "e,f,g" },
688{ "divs/c", 0x58000060, 1, "e,f,g" },
689{ "divs/m", 0x58000860, 1, "e,f,g" },
690{ "divs/d", 0x58001860, 1, "e,f,g" },
691{ "divs/u", 0x58003060, 1, "e,f,g" },
692{ "divs/uc", 0x58002060, 1, "e,f,g" },
693{ "divs/um", 0x58002860, 1, "e,f,g" },
694{ "divs/ud", 0x58003860, 1, "e,f,g" },
695{ "divs/su", 0x5800b060, 1, "e,f,g" },
696{ "divs/suc", 0x5800a060, 1, "e,f,g" },
697{ "divs/sum", 0x5800a860, 1, "e,f,g" },
698{ "divs/sud", 0x5800b860, 1, "e,f,g" },
699{ "divs/sui", 0x5800f060, 1, "e,f,g" },
700{ "divs/suic", 0x5800e060, 1, "e,f,g" },
701{ "divs/suim", 0x5800e860, 1, "e,f,g" },
702{ "divs/suid", 0x5800f860, 1, "e,f,g" },
703{ "divt", 0x58001460, 1, "e,f,g" },
704{ "divt/c", 0x58000460, 1, "e,f,g" },
705{ "divt/m", 0x58000c60, 1, "e,f,g" },
706{ "divt/d", 0x58001c60, 1, "e,f,g" },
707{ "divt/u", 0x58003460, 1, "e,f,g" },
708{ "divt/uc", 0x58002460, 1, "e,f,g" },
709{ "divt/um", 0x58002c60, 1, "e,f,g" },
710{ "divt/ud", 0x58003c60, 1, "e,f,g" },
711{ "divt/su", 0x5800b460, 1, "e,f,g" },
712{ "divt/suc", 0x5800a460, 1, "e,f,g" },
713{ "divt/sum", 0x5800ac60, 1, "e,f,g" },
714{ "divt/sud", 0x5800bc60, 1, "e,f,g" },
715{ "divt/sui", 0x5800f460, 1, "e,f,g" },
716{ "divt/suic", 0x5800e460, 1, "e,f,g" },
717{ "divt/suim", 0x5800ec60, 1, "e,f,g" },
718{ "divt/suid", 0x5800fc60, 1, "e,f,g" },
719{ "muls", 0x58001040, 1, "e,f,g" },
720{ "muls/c", 0x58000040, 1, "e,f,g" },
721{ "muls/m", 0x58000840, 1, "e,f,g" },
722{ "muls/d", 0x58001840, 1, "e,f,g" },
723{ "muls/u", 0x58003040, 1, "e,f,g" },
724{ "muls/uc", 0x58002040, 1, "e,f,g" },
725{ "muls/um", 0x58002840, 1, "e,f,g" },
726{ "muls/ud", 0x58003840, 1, "e,f,g" },
727{ "muls/su", 0x5800b040, 1, "e,f,g" },
728{ "muls/suc", 0x5800a040, 1, "e,f,g" },
729{ "muls/sum", 0x5800a840, 1, "e,f,g" },
730{ "muls/sud", 0x5800b840, 1, "e,f,g" },
731{ "muls/sui", 0x5800f040, 1, "e,f,g" },
732{ "muls/suic", 0x5800e040, 1, "e,f,g" },
733{ "muls/suim", 0x5800e840, 1, "e,f,g" },
734{ "muls/suid", 0x5800f840, 1, "e,f,g" },
735{ "mult", 0x58001440, 1, "e,f,g" },
736{ "mult/c", 0x58000440, 1, "e,f,g" },
737{ "mult/m", 0x58000c40, 1, "e,f,g" },
738{ "mult/d", 0x58001c40, 1, "e,f,g" },
739{ "mult/u", 0x58003440, 1, "e,f,g" },
740{ "mult/uc", 0x58002440, 1, "e,f,g" },
741{ "mult/um", 0x58002c40, 1, "e,f,g" },
742{ "mult/ud", 0x58003c40, 1, "e,f,g" },
743{ "mult/su", 0x5800b440, 1, "e,f,g" },
744{ "mult/suc", 0x5800a440, 1, "e,f,g" },
745{ "mult/sum", 0x5800ac40, 1, "e,f,g" },
746{ "mult/sud", 0x5800bc40, 1, "e,f,g" },
747{ "mult/sui", 0x5800f440, 1, "e,f,g" },
748{ "mult/suic", 0x5800e440, 1, "e,f,g" },
749{ "mult/suim", 0x5800ec40, 1, "e,f,g" },
750{ "mult/suid", 0x5800fc40, 1, "e,f,g" },
751
752/*
0952861c 753 * Miscellaneous, including standard PAL instructions.
5749c497
KR		 754 */
755{ "pal", 0x00000000, 0, "I" }, /* 6o+26f */
756{ "call_pal", 0x00000000, 0, "I" }, /* alias */
757{ "bpt", 0x00000080, 0, "" },
758{ "chmk", 0x00000083, 0, "" },
759{ "imb", 0x00000086, 0, "" },
760
761{ "draint", 0x60000000, 0, "" }, /* 6o+5a+5b+16d */
762{ "trapb", 0x60000000, 0, "" }, /* 6o+5a+5b+16d */
763{ "fetch", 0x60008000, 0, "0(2)" },
764{ "fetch_m", 0x6000a000, 0, "0(2)" },
765{ "mb", 0x60004000, 0, "" },
766{ "rpcc", 0x6000c000, 0, "1" },
767{ "rc", 0x6000e000, 0, "1" },
768{ "rs", 0x6000f000, 0, "1" },
769
770/*
0952861c
KR		 771 * More macros
772 */
773{ "nop", 0x47ff041f, 0, "" }, /* or zero,zero,zero */
774{ "mov", 0x47e00400, 0, "2,3" }, /* or zero,r2,r3 */
775};
776
777#define NUMOPCODES ((sizeof alpha_opcodes)/(sizeof alpha_opcodes[0]))
778
779/*
780 * PAL instructions for 21064 (and 21066/68)
5749c497 781 */
0952861c
KR		 782static const struct alpha_opcode alpha_pal21064_opcodes[] =
783{
5749c497
KR		 784{ "hw_ld", 0x6c000000, 0, "1,t(2)" },
785{ "hw_ld/p", 0x6c008000, 0, "1,t(2)" },
786{ "hw_ld/a", 0x6c004000, 0, "1,t(2)" },
787{ "hw_ld/r", 0x6c002000, 0, "1,t(2)" },
788{ "hw_ld/q", 0x6c001000, 0, "1,t(2)" },
789{ "hw_ld/pa", 0x6c00C000, 0, "1,t(2)" },
790{ "hw_ld/pr", 0x6c00A000, 0, "1,t(2)" },
791{ "hw_ld/pq", 0x6c009000, 0, "1,t(2)" },
792{ "hw_ld/ar", 0x6c006000, 0, "1,t(2)" },
793{ "hw_ld/aq", 0x6c005000, 0, "1,t(2)" },
794{ "hw_ld/rq", 0x6c003000, 0, "1,t(2)" },
795{ "hw_ld/par", 0x6c00e000, 0, "1,t(2)" },
796{ "hw_ld/paq", 0x6c00d000, 0, "1,t(2)" },
797{ "hw_ld/prq", 0x6c00b000, 0, "1,t(2)" },
798{ "hw_ld/arq", 0x6c007000, 0, "1,t(2)" },
799{ "hw_ld/parq", 0x6c00f000, 0, "1,t(2)" },
800
801{ "hw_ldq", 0x6c001000, 0, "1,t(2)" }, /* ldq/ldl variants for Eric */
802{ "hw_ldq/p", 0x6c009000, 0, "1,t(2)" },
803{ "hw_ldq/a", 0x6c005000, 0, "1,t(2)" },
804{ "hw_ldq/r", 0x6c003000, 0, "1,t(2)" },
805{ "hw_ldq/pa", 0x6c00d000, 0, "1,t(2)" },
806{ "hw_ldq/pr", 0x6c00b000, 0, "1,t(2)" },
807{ "hw_ldq/ar", 0x6c007000, 0, "1,t(2)" },
808{ "hw_ldq/par", 0x6c00f000, 0, "1,t(2)" },
809{ "hw_ldl", 0x6c000000, 0, "1,t(2)" },
810{ "hw_ldl/p", 0x6c008000, 0, "1,t(2)" },
811{ "hw_ldl/a", 0x6c004000, 0, "1,t(2)" },
812{ "hw_ldl/r", 0x6c002000, 0, "1,t(2)" },
813{ "hw_ldl/pa", 0x6c00C000, 0, "1,t(2)" },
814{ "hw_ldl/pr", 0x6c00A000, 0, "1,t(2)" },
815{ "hw_ldl/ar", 0x6c006000, 0, "1,t(2)" },
816{ "hw_ldl/par", 0x6c00e000, 0, "1,t(2)" },
817
818{ "hw_st/paq", 0x7c00c000, 0, "1,t(2)" },
819{ "hw_st/pa", 0x7c00b000, 0, "1,t(2)" },
820{ "hw_st/pq", 0x7c009000, 0, "1,t(2)" },
821{ "hw_st/aq", 0x7c005000, 0, "1,t(2)" },
822{ "hw_st/p", 0x7c008000, 0, "1,t(2)" },
823{ "hw_st/a", 0x7c004000, 0, "1,t(2)" },
824{ "hw_st/q", 0x7c001000, 0, "1,t(2)" },
825{ "hw_st", 0x7c000000, 0, "1,t(2)" },
826
827{ "hw_stq/pa", 0x7c00c000, 0, "1,t(2)" }, /* stq/stl variants for Eric */
828{ "hw_stq/p", 0x7c009000, 0, "1,t(2)" },
829{ "hw_stq", 0x7c001000, 0, "1,t(2)" },
830{ "hw_stq/a", 0x7c005000, 0, "1,t(2)" },
831{ "hw_stl/pa", 0x7c00b000, 0, "1,t(2)" },
832{ "hw_stl/p", 0x7c008000, 0, "1,t(2)" },
833{ "hw_stl/a", 0x7c004000, 0, "1,t(2)" },
834{ "hw_stl", 0x7c000000, 0, "1,t(2)" },
835
836{ "hw_mfpr/p", 0x64000080, 0, "R,3" },
837{ "hw_mfpr/a", 0x64000040, 0, "R,3" },
838{ "hw_mfpr/i", 0x64000020, 0, "R,3" },
839{ "hw_mfpr/pa", 0x640000c0, 0, "R,3" },
840{ "hw_mfpr/pi", 0x640000a0, 0, "R,3" },
841{ "hw_mfpr/ai", 0x64000060, 0, "R,3" },
842{ "hw_mfpr/pai",0x640000e0, 0, "R,3" },
843{ "hw_mfpr", 0x64000000, 0, "R,8" },
844
845{ "hw_mtpr/p", 0x74000080, 0, "R,3" },
846{ "hw_mtpr/a", 0x74000040, 0, "R,3" },
847{ "hw_mtpr/i", 0x74000020, 0, "R,3" },
848{ "hw_mtpr/pa", 0x740000c0, 0, "R,3" },
849{ "hw_mtpr/pi", 0x740000a0, 0, "R,3" },
850{ "hw_mtpr/ai", 0x74000060, 0, "R,3" },
851{ "hw_mtpr/pai",0x740000e0, 0, "R,3" },
852{ "hw_mtpr", 0x74000000, 0, "R,8" },
853
854{ "hw_rei", 0x7bff8000, 0, "" },
0952861c
KR		 855};
856
857#define NUM21064OPCODES ((sizeof alpha_pal21064_opcodes)/(sizeof alpha_pal21064_opcodes[0]))
858
5749c497 859/*
0952861c 860 * 21164 (and 21166/68) specific PAL instructions.
5749c497 861 */
0952861c
KR		 862static const struct alpha_opcode alpha_pal21164_opcodes[] =
863{
864{ "hw_ld", 0x6c000000, 0, "1,l(2)" }, /* RA, 16 bit displacement (RB) */
865{ "hw_st", 0x7c000000, 0, "1,l(2)" }, /* RA, 16 bit displacement (RB) */
866
867{ "hw_ldl/a", 0x6c004000, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
868{ "hw_ldq/a", 0x6c005000, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
869{ "hw_stl/a", 0x7c004000, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
870{ "hw_stq/a", 0x7c005000, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
871
872{ "hw_ldl/p", 0x6c008000, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
873{ "hw_ldq/p", 0x6c009000, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
874{ "hw_stl/p", 0x7c008000, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
875{ "hw_stq/p", 0x7c009000, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
876
877{ "hw_ldq/v", 0x6c001800, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
878
879{ "hw_ldl/l", 0x6c000400, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
880{ "hw_ldq/l", 0x6c001400, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
881
882{ "hw_stl/c", 0x7c000400, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
883{ "hw_stq/c", 0x7c001400, 0, "1,t(2)" }, /* RA, 12 bit displacement (RB) */
884
885{ "hw_mfpr", 0x64000000, 0, "R,l" }, /* RA,RB,16 bits displacement */
886{ "hw_mtpr", 0x74000000, 0, "R,l" }, /* RA,RB,16 bits displacement */
887
888{ "hw_rei", 0x7bff8000, 0, "" },
889
890{ "hw_rei_stall", 0x7bffc000, 0, "" },
5749c497
KR		 891};
892
0952861c 893#define NUM21164OPCODES ((sizeof alpha_pal21164_opcodes)/(sizeof alpha_pal21164_opcodes[0]))
GDB Binutils - Deliverables
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