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[deliverable/binutils-gdb.git] / gas / config / tc-aarch64.c
CommitLineData
a06ea964
NC		 1/* tc-aarch64.c -- Assemble for the AArch64 ISA
2
a3251895
YZ		 3 Copyright 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
a06ea964
NC		 5 Contributed by ARM Ltd.
6
7 This file is part of GAS.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the license, or
12 (at your option) any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
22
23#include "as.h"
24#include <limits.h>
25#include <stdarg.h>
26#include "bfd_stdint.h"
27#define NO_RELOC 0
28#include "safe-ctype.h"
29#include "subsegs.h"
30#include "obstack.h"
31
32#ifdef OBJ_ELF
33#include "elf/aarch64.h"
34#include "dw2gencfi.h"
35#endif
36
37#include "dwarf2dbg.h"
38
39/* Types of processor to assemble for. */
40#ifndef CPU_DEFAULT
41#define CPU_DEFAULT AARCH64_ARCH_V8
42#endif
43
44#define streq(a, b) (strcmp (a, b) == 0)
45
46static aarch64_feature_set cpu_variant;
47
48/* Variables that we set while parsing command-line options. Once all
49 options have been read we re-process these values to set the real
50 assembly flags. */
51static const aarch64_feature_set *mcpu_cpu_opt = NULL;
52static const aarch64_feature_set *march_cpu_opt = NULL;
53
54/* Constants for known architecture features. */
55static const aarch64_feature_set cpu_default = CPU_DEFAULT;
56
57static const aarch64_feature_set aarch64_arch_any = AARCH64_ANY;
58static const aarch64_feature_set aarch64_arch_none = AARCH64_ARCH_NONE;
59
60#ifdef OBJ_ELF
61/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
62static symbolS *GOT_symbol;
cec5225b
YZ		 63
64/* When non-zero, program to a 32-bit model, in which the C data types
65 int, long and all pointer types are 32-bit objects (ILP32); or to a
66 64-bit model, in which the C int type is 32-bits but the C long type
67 and all pointer types are 64-bit objects (LP64). */
68static int ilp32_p = 0;
a06ea964
NC		 69#endif
70
71enum neon_el_type
72{
73 NT_invtype = -1,
74 NT_b,
75 NT_h,
76 NT_s,
77 NT_d,
78 NT_q
79};
80
81/* Bits for DEFINED field in neon_type_el. */
82#define NTA_HASTYPE 1
83#define NTA_HASINDEX 2
84
85struct neon_type_el
86{
87 enum neon_el_type type;
88 unsigned char defined;
89 unsigned width;
90 int64_t index;
91};
92
93#define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
94
95struct reloc
96{
97 bfd_reloc_code_real_type type;
98 expressionS exp;
99 int pc_rel;
100 enum aarch64_opnd opnd;
101 uint32_t flags;
102 unsigned need_libopcodes_p : 1;
103};
104
105struct aarch64_instruction
106{
107 /* libopcodes structure for instruction intermediate representation. */
108 aarch64_inst base;
109 /* Record assembly errors found during the parsing. */
110 struct
111 {
112 enum aarch64_operand_error_kind kind;
113 const char *error;
114 } parsing_error;
115 /* The condition that appears in the assembly line. */
116 int cond;
117 /* Relocation information (including the GAS internal fixup). */
118 struct reloc reloc;
119 /* Need to generate an immediate in the literal pool. */
120 unsigned gen_lit_pool : 1;
121};
122
123typedef struct aarch64_instruction aarch64_instruction;
124
125static aarch64_instruction inst;
126
127static bfd_boolean parse_operands (char *, const aarch64_opcode *);
128static bfd_boolean programmer_friendly_fixup (aarch64_instruction *);
129
130/* Diagnostics inline function utilites.
131
132 These are lightweight utlities which should only be called by parse_operands
133 and other parsers. GAS processes each assembly line by parsing it against
134 instruction template(s), in the case of multiple templates (for the same
135 mnemonic name), those templates are tried one by one until one succeeds or
136 all fail. An assembly line may fail a few templates before being
137 successfully parsed; an error saved here in most cases is not a user error
138 but an error indicating the current template is not the right template.
139 Therefore it is very important that errors can be saved at a low cost during
140 the parsing; we don't want to slow down the whole parsing by recording
141 non-user errors in detail.
142
143 Remember that the objective is to help GAS pick up the most approapriate
144 error message in the case of multiple templates, e.g. FMOV which has 8
145 templates. */
146
147static inline void
148clear_error (void)
149{
150 inst.parsing_error.kind = AARCH64_OPDE_NIL;
151 inst.parsing_error.error = NULL;
152}
153
154static inline bfd_boolean
155error_p (void)
156{
157 return inst.parsing_error.kind != AARCH64_OPDE_NIL;
158}
159
160static inline const char *
161get_error_message (void)
162{
163 return inst.parsing_error.error;
164}
165
166static inline void
167set_error_message (const char *error)
168{
169 inst.parsing_error.error = error;
170}
171
172static inline enum aarch64_operand_error_kind
173get_error_kind (void)
174{
175 return inst.parsing_error.kind;
176}
177
178static inline void
179set_error_kind (enum aarch64_operand_error_kind kind)
180{
181 inst.parsing_error.kind = kind;
182}
183
184static inline void
185set_error (enum aarch64_operand_error_kind kind, const char *error)
186{
187 inst.parsing_error.kind = kind;
188 inst.parsing_error.error = error;
189}
190
191static inline void
192set_recoverable_error (const char *error)
193{
194 set_error (AARCH64_OPDE_RECOVERABLE, error);
195}
196
197/* Use the DESC field of the corresponding aarch64_operand entry to compose
198 the error message. */
199static inline void
200set_default_error (void)
201{
202 set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
203}
204
205static inline void
206set_syntax_error (const char *error)
207{
208 set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
209}
210
211static inline void
212set_first_syntax_error (const char *error)
213{
214 if (! error_p ())
215 set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
216}
217
218static inline void
219set_fatal_syntax_error (const char *error)
220{
221 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR, error);
222}
223\f
224/* Number of littlenums required to hold an extended precision number. */
225#define MAX_LITTLENUMS 6
226
227/* Return value for certain parsers when the parsing fails; those parsers
228 return the information of the parsed result, e.g. register number, on
229 success. */
230#define PARSE_FAIL -1
231
232/* This is an invalid condition code that means no conditional field is
233 present. */
234#define COND_ALWAYS 0x10
235
236typedef struct
237{
238 const char *template;
239 unsigned long value;
240} asm_barrier_opt;
241
242typedef struct
243{
244 const char *template;
245 uint32_t value;
246} asm_nzcv;
247
248struct reloc_entry
249{
250 char *name;
251 bfd_reloc_code_real_type reloc;
252};
253
254/* Structure for a hash table entry for a register. */
255typedef struct
256{
257 const char *name;
258 unsigned char number;
259 unsigned char type;
260 unsigned char builtin;
261} reg_entry;
262
263/* Macros to define the register types and masks for the purpose
264 of parsing. */
265
266#undef AARCH64_REG_TYPES
267#define AARCH64_REG_TYPES \
268 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
269 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
270 BASIC_REG_TYPE(SP_32) /* wsp */ \
271 BASIC_REG_TYPE(SP_64) /* sp */ \
272 BASIC_REG_TYPE(Z_32) /* wzr */ \
273 BASIC_REG_TYPE(Z_64) /* xzr */ \
274 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
275 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
276 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
277 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
278 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
279 BASIC_REG_TYPE(CN) /* c[0-7] */ \
280 BASIC_REG_TYPE(VN) /* v[0-31] */ \
281 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
282 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
283 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
284 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
285 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
286 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
287 /* Typecheck: any [BHSDQ]P FP. */ \
288 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
289 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
290 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
291 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
292 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
293 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
294 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
295 /* Any integer register; used for error messages only. */ \
296 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
297 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
298 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
299 /* Pseudo type to mark the end of the enumerator sequence. */ \
300 BASIC_REG_TYPE(MAX)
301
302#undef BASIC_REG_TYPE
303#define BASIC_REG_TYPE(T) REG_TYPE_##T,
304#undef MULTI_REG_TYPE
305#define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
306
307/* Register type enumerators. */
308typedef enum
309{
310 /* A list of REG_TYPE_*. */
311 AARCH64_REG_TYPES
312} aarch64_reg_type;
313
314#undef BASIC_REG_TYPE
315#define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
316#undef REG_TYPE
317#define REG_TYPE(T) (1 << REG_TYPE_##T)
318#undef MULTI_REG_TYPE
319#define MULTI_REG_TYPE(T,V) V,
320
321/* Values indexed by aarch64_reg_type to assist the type checking. */
322static const unsigned reg_type_masks[] =
323{
324 AARCH64_REG_TYPES
325};
326
327#undef BASIC_REG_TYPE
328#undef REG_TYPE
329#undef MULTI_REG_TYPE
330#undef AARCH64_REG_TYPES
331
332/* Diagnostics used when we don't get a register of the expected type.
333 Note: this has to synchronized with aarch64_reg_type definitions
334 above. */
335static const char *
336get_reg_expected_msg (aarch64_reg_type reg_type)
337{
338 const char *msg;
339
340 switch (reg_type)
341 {
342 case REG_TYPE_R_32:
343 msg = N_("integer 32-bit register expected");
344 break;
345 case REG_TYPE_R_64:
346 msg = N_("integer 64-bit register expected");
347 break;
348 case REG_TYPE_R_N:
349 msg = N_("integer register expected");
350 break;
351 case REG_TYPE_R_Z_SP:
352 msg = N_("integer, zero or SP register expected");
353 break;
354 case REG_TYPE_FP_B:
355 msg = N_("8-bit SIMD scalar register expected");
356 break;
357 case REG_TYPE_FP_H:
358 msg = N_("16-bit SIMD scalar or floating-point half precision "
359 "register expected");
360 break;
361 case REG_TYPE_FP_S:
362 msg = N_("32-bit SIMD scalar or floating-point single precision "
363 "register expected");
364 break;
365 case REG_TYPE_FP_D:
366 msg = N_("64-bit SIMD scalar or floating-point double precision "
367 "register expected");
368 break;
369 case REG_TYPE_FP_Q:
370 msg = N_("128-bit SIMD scalar or floating-point quad precision "
371 "register expected");
372 break;
373 case REG_TYPE_CN:
374 msg = N_("C0 - C15 expected");
375 break;
376 case REG_TYPE_R_Z_BHSDQ_V:
377 msg = N_("register expected");
378 break;
379 case REG_TYPE_BHSDQ: /* any [BHSDQ]P FP */
380 msg = N_("SIMD scalar or floating-point register expected");
381 break;
382 case REG_TYPE_VN: /* any V reg */
383 msg = N_("vector register expected");
384 break;
385 default:
386 as_fatal (_("invalid register type %d"), reg_type);
387 }
388 return msg;
389}
390
391/* Some well known registers that we refer to directly elsewhere. */
392#define REG_SP 31
393
394/* Instructions take 4 bytes in the object file. */
395#define INSN_SIZE 4
396
397/* Define some common error messages. */
398#define BAD_SP _("SP not allowed here")
399
400static struct hash_control *aarch64_ops_hsh;
401static struct hash_control *aarch64_cond_hsh;
402static struct hash_control *aarch64_shift_hsh;
403static struct hash_control *aarch64_sys_regs_hsh;
404static struct hash_control *aarch64_pstatefield_hsh;
405static struct hash_control *aarch64_sys_regs_ic_hsh;
406static struct hash_control *aarch64_sys_regs_dc_hsh;
407static struct hash_control *aarch64_sys_regs_at_hsh;
408static struct hash_control *aarch64_sys_regs_tlbi_hsh;
409static struct hash_control *aarch64_reg_hsh;
410static struct hash_control *aarch64_barrier_opt_hsh;
411static struct hash_control *aarch64_nzcv_hsh;
412static struct hash_control *aarch64_pldop_hsh;
413
414/* Stuff needed to resolve the label ambiguity
415 As:
416 ...
417 label: <insn>
418 may differ from:
419 ...
420 label:
421 <insn> */
422
423static symbolS *last_label_seen;
424
425/* Literal pool structure. Held on a per-section
426 and per-sub-section basis. */
427
428#define MAX_LITERAL_POOL_SIZE 1024
429typedef struct literal_pool
430{
431 expressionS literals[MAX_LITERAL_POOL_SIZE];
432 unsigned int next_free_entry;
433 unsigned int id;
434 symbolS *symbol;
435 segT section;
436 subsegT sub_section;
437 int size;
438 struct literal_pool *next;
439} literal_pool;
440
441/* Pointer to a linked list of literal pools. */
442static literal_pool *list_of_pools = NULL;
443\f
444/* Pure syntax. */
445
446/* This array holds the chars that always start a comment. If the
447 pre-processor is disabled, these aren't very useful. */
448const char comment_chars[] = "";
449
450/* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output. */
453/* Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output. */
456/* Also note that comments like this one will always work. */
457const char line_comment_chars[] = "#";
458
459const char line_separator_chars[] = ";";
460
461/* Chars that can be used to separate mant
462 from exp in floating point numbers. */
463const char EXP_CHARS[] = "eE";
464
465/* Chars that mean this number is a floating point constant. */
466/* As in 0f12.456 */
467/* or 0d1.2345e12 */
468
469const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
470
471/* Prefix character that indicates the start of an immediate value. */
472#define is_immediate_prefix(C) ((C) == '#')
473
474/* Separator character handling. */
475
476#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
477
478static inline bfd_boolean
479skip_past_char (char **str, char c)
480{
481 if (**str == c)
482 {
483 (*str)++;
484 return TRUE;
485 }
486 else
487 return FALSE;
488}
489
490#define skip_past_comma(str) skip_past_char (str, ',')
491
492/* Arithmetic expressions (possibly involving symbols). */
493
a06ea964
NC		 494static bfd_boolean in_my_get_expression_p = FALSE;
495
496/* Third argument to my_get_expression. */
497#define GE_NO_PREFIX 0
498#define GE_OPT_PREFIX 1
499
500/* Return TRUE if the string pointed by *STR is successfully parsed
501 as an valid expression; *EP will be filled with the information of
502 such an expression. Otherwise return FALSE. */
503
504static bfd_boolean
505my_get_expression (expressionS * ep, char **str, int prefix_mode,
506 int reject_absent)
507{
508 char *save_in;
509 segT seg;
510 int prefix_present_p = 0;
511
512 switch (prefix_mode)
513 {
514 case GE_NO_PREFIX:
515 break;
516 case GE_OPT_PREFIX:
517 if (is_immediate_prefix (**str))
518 {
519 (*str)++;
520 prefix_present_p = 1;
521 }
522 break;
523 default:
524 abort ();
525 }
526
527 memset (ep, 0, sizeof (expressionS));
528
529 save_in = input_line_pointer;
530 input_line_pointer = *str;
531 in_my_get_expression_p = TRUE;
532 seg = expression (ep);
533 in_my_get_expression_p = FALSE;
534
535 if (ep->X_op == O_illegal || (reject_absent && ep->X_op == O_absent))
536 {
537 /* We found a bad expression in md_operand(). */
538 *str = input_line_pointer;
539 input_line_pointer = save_in;
540 if (prefix_present_p && ! error_p ())
541 set_fatal_syntax_error (_("bad expression"));
542 else
543 set_first_syntax_error (_("bad expression"));
544 return FALSE;
545 }
546
547#ifdef OBJ_AOUT
548 if (seg != absolute_section
549 && seg != text_section
550 && seg != data_section
551 && seg != bss_section && seg != undefined_section)
552 {
553 set_syntax_error (_("bad segment"));
554 *str = input_line_pointer;
555 input_line_pointer = save_in;
556 return FALSE;
557 }
558#else
559 (void) seg;
560#endif
561
a06ea964
NC		 562 *str = input_line_pointer;
563 input_line_pointer = save_in;
564 return TRUE;
565}
566
567/* Turn a string in input_line_pointer into a floating point constant
568 of type TYPE, and store the appropriate bytes in *LITP. The number
569 of LITTLENUMS emitted is stored in *SIZEP. An error message is
570 returned, or NULL on OK. */
571
572char *
573md_atof (int type, char *litP, int *sizeP)
574{
575 return ieee_md_atof (type, litP, sizeP, target_big_endian);
576}
577
578/* We handle all bad expressions here, so that we can report the faulty
579 instruction in the error message. */
580void
581md_operand (expressionS * exp)
582{
583 if (in_my_get_expression_p)
584 exp->X_op = O_illegal;
585}
586
587/* Immediate values. */
588
589/* Errors may be set multiple times during parsing or bit encoding
590 (particularly in the Neon bits), but usually the earliest error which is set
591 will be the most meaningful. Avoid overwriting it with later (cascading)
592 errors by calling this function. */
593
594static void
595first_error (const char *error)
596{
597 if (! error_p ())
598 set_syntax_error (error);
599}
600
601/* Similiar to first_error, but this function accepts formatted error
602 message. */
603static void
604first_error_fmt (const char *format, ...)
605{
606 va_list args;
607 enum
608 { size = 100 };
609 /* N.B. this single buffer will not cause error messages for different
610 instructions to pollute each other; this is because at the end of
611 processing of each assembly line, error message if any will be
612 collected by as_bad. */
613 static char buffer[size];
614
615 if (! error_p ())
616 {
3e0baa28 617 int ret ATTRIBUTE_UNUSED;
a06ea964
NC		 618 va_start (args, format);
619 ret = vsnprintf (buffer, size, format, args);
620 know (ret <= size - 1 && ret >= 0);
621 va_end (args);
622 set_syntax_error (buffer);
623 }
624}
625
626/* Register parsing. */
627
628/* Generic register parser which is called by other specialized
629 register parsers.
630 CCP points to what should be the beginning of a register name.
631 If it is indeed a valid register name, advance CCP over it and
632 return the reg_entry structure; otherwise return NULL.
633 It does not issue diagnostics. */
634
635static reg_entry *
636parse_reg (char **ccp)
637{
638 char *start = *ccp;
639 char *p;
640 reg_entry *reg;
641
642#ifdef REGISTER_PREFIX
643 if (*start != REGISTER_PREFIX)
644 return NULL;
645 start++;
646#endif
647
648 p = start;
649 if (!ISALPHA (*p) || !is_name_beginner (*p))
650 return NULL;
651
652 do
653 p++;
654 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
655
656 reg = (reg_entry *) hash_find_n (aarch64_reg_hsh, start, p - start);
657
658 if (!reg)
659 return NULL;
660
661 *ccp = p;
662 return reg;
663}
664
665/* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
666 return FALSE. */
667static bfd_boolean
668aarch64_check_reg_type (const reg_entry *reg, aarch64_reg_type type)
669{
670 if (reg->type == type)
671 return TRUE;
672
673 switch (type)
674 {
675 case REG_TYPE_R64_SP: /* 64-bit integer reg (inc SP exc XZR). */
676 case REG_TYPE_R_Z_SP: /* Integer reg (inc {X}SP inc [WX]ZR). */
677 case REG_TYPE_R_Z_BHSDQ_V: /* Any register apart from Cn. */
678 case REG_TYPE_BHSDQ: /* Any [BHSDQ]P FP or SIMD scalar register. */
679 case REG_TYPE_VN: /* Vector register. */
680 gas_assert (reg->type < REG_TYPE_MAX && type < REG_TYPE_MAX);
681 return ((reg_type_masks[reg->type] & reg_type_masks[type])
682 == reg_type_masks[reg->type]);
683 default:
684 as_fatal ("unhandled type %d", type);
685 abort ();
686 }
687}
688
689/* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
690 Return the register number otherwise. *ISREG32 is set to one if the
691 register is 32-bit wide; *ISREGZERO is set to one if the register is
692 of type Z_32 or Z_64.
693 Note that this function does not issue any diagnostics. */
694
695static int
696aarch64_reg_parse_32_64 (char **ccp, int reject_sp, int reject_rz,
697 int *isreg32, int *isregzero)
698{
699 char *str = *ccp;
700 const reg_entry *reg = parse_reg (&str);
701
702 if (reg == NULL)
703 return PARSE_FAIL;
704
705 if (! aarch64_check_reg_type (reg, REG_TYPE_R_Z_SP))
706 return PARSE_FAIL;
707
708 switch (reg->type)
709 {
710 case REG_TYPE_SP_32:
711 case REG_TYPE_SP_64:
712 if (reject_sp)
713 return PARSE_FAIL;
714 *isreg32 = reg->type == REG_TYPE_SP_32;
715 *isregzero = 0;
716 break;
717 case REG_TYPE_R_32:
718 case REG_TYPE_R_64:
719 *isreg32 = reg->type == REG_TYPE_R_32;
720 *isregzero = 0;
721 break;
722 case REG_TYPE_Z_32:
723 case REG_TYPE_Z_64:
724 if (reject_rz)
725 return PARSE_FAIL;
726 *isreg32 = reg->type == REG_TYPE_Z_32;
727 *isregzero = 1;
728 break;
729 default:
730 return PARSE_FAIL;
731 }
732
733 *ccp = str;
734
735 return reg->number;
736}
737
738/* Parse the qualifier of a SIMD vector register or a SIMD vector element.
739 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
740 otherwise return FALSE.
741
742 Accept only one occurrence of:
743 8b 16b 4h 8h 2s 4s 1d 2d
744 b h s d q */
745static bfd_boolean
746parse_neon_type_for_operand (struct neon_type_el *parsed_type, char **str)
747{
748 char *ptr = *str;
749 unsigned width;
750 unsigned element_size;
751 enum neon_el_type type;
752
753 /* skip '.' */
754 ptr++;
755
756 if (!ISDIGIT (*ptr))
757 {
758 width = 0;
759 goto elt_size;
760 }
761 width = strtoul (ptr, &ptr, 10);
762 if (width != 1 && width != 2 && width != 4 && width != 8 && width != 16)
763 {
764 first_error_fmt (_("bad size %d in vector width specifier"), width);
765 return FALSE;
766 }
767
768elt_size:
769 switch (TOLOWER (*ptr))
770 {
771 case 'b':
772 type = NT_b;
773 element_size = 8;
774 break;
775 case 'h':
776 type = NT_h;
777 element_size = 16;
778 break;
779 case 's':
780 type = NT_s;
781 element_size = 32;
782 break;
783 case 'd':
784 type = NT_d;
785 element_size = 64;
786 break;
787 case 'q':
788 if (width == 1)
789 {
790 type = NT_q;
791 element_size = 128;
792 break;
793 }
794 /* fall through. */
795 default:
796 if (*ptr != '\0')
797 first_error_fmt (_("unexpected character `%c' in element size"), *ptr);
798 else
799 first_error (_("missing element size"));
800 return FALSE;
801 }
802 if (width != 0 && width * element_size != 64 && width * element_size != 128)
803 {
804 first_error_fmt (_
805 ("invalid element size %d and vector size combination %c"),
806 width, *ptr);
807 return FALSE;
808 }
809 ptr++;
810
811 parsed_type->type = type;
812 parsed_type->width = width;
813
814 *str = ptr;
815
816 return TRUE;
817}
818
819/* Parse a single type, e.g. ".8b", leading period included.
820 Only applicable to Vn registers.
821
822 Return TRUE on success; otherwise return FALSE. */
823static bfd_boolean
824parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
825{
826 char *str = *ccp;
827
828 if (*str == '.')
829 {
830 if (! parse_neon_type_for_operand (vectype, &str))
831 {
832 first_error (_("vector type expected"));
833 return FALSE;
834 }
835 }
836 else
837 return FALSE;
838
839 *ccp = str;
840
841 return TRUE;
842}
843
844/* Parse a register of the type TYPE.
845
846 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
847 name or the parsed register is not of TYPE.
848
849 Otherwise return the register number, and optionally fill in the actual
850 type of the register in *RTYPE when multiple alternatives were given, and
851 return the register shape and element index information in *TYPEINFO.
852
853 IN_REG_LIST should be set with TRUE if the caller is parsing a register
854 list. */
855
856static int
857parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
858 struct neon_type_el *typeinfo, bfd_boolean in_reg_list)
859{
860 char *str = *ccp;
861 const reg_entry *reg = parse_reg (&str);
862 struct neon_type_el atype;
863 struct neon_type_el parsetype;
864 bfd_boolean is_typed_vecreg = FALSE;
865
866 atype.defined = 0;
867 atype.type = NT_invtype;
868 atype.width = -1;
869 atype.index = 0;
870
871 if (reg == NULL)
872 {
873 if (typeinfo)
874 *typeinfo = atype;
875 set_default_error ();
876 return PARSE_FAIL;
877 }
878
879 if (! aarch64_check_reg_type (reg, type))
880 {
881 DEBUG_TRACE ("reg type check failed");
882 set_default_error ();
883 return PARSE_FAIL;
884 }
885 type = reg->type;
886
887 if (type == REG_TYPE_VN
888 && parse_neon_operand_type (&parsetype, &str))
889 {
890 /* Register if of the form Vn.[bhsdq]. */
891 is_typed_vecreg = TRUE;
892
893 if (parsetype.width == 0)
894 /* Expect index. In the new scheme we cannot have
895 Vn.[bhsdq] represent a scalar. Therefore any
896 Vn.[bhsdq] should have an index following it.
897 Except in reglists ofcourse. */
898 atype.defined |= NTA_HASINDEX;
899 else
900 atype.defined |= NTA_HASTYPE;
901
902 atype.type = parsetype.type;
903 atype.width = parsetype.width;
904 }
905
906 if (skip_past_char (&str, '['))
907 {
908 expressionS exp;
909
910 /* Reject Sn[index] syntax. */
911 if (!is_typed_vecreg)
912 {
913 first_error (_("this type of register can't be indexed"));
914 return PARSE_FAIL;
915 }
916
917 if (in_reg_list == TRUE)
918 {
919 first_error (_("index not allowed inside register list"));
920 return PARSE_FAIL;
921 }
922
923 atype.defined |= NTA_HASINDEX;
924
925 my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
926
927 if (exp.X_op != O_constant)
928 {
929 first_error (_("constant expression required"));
930 return PARSE_FAIL;
931 }
932
933 if (! skip_past_char (&str, ']'))
934 return PARSE_FAIL;
935
936 atype.index = exp.X_add_number;
937 }
938 else if (!in_reg_list && (atype.defined & NTA_HASINDEX) != 0)
939 {
940 /* Indexed vector register expected. */
941 first_error (_("indexed vector register expected"));
942 return PARSE_FAIL;
943 }
944
945 /* A vector reg Vn should be typed or indexed. */
946 if (type == REG_TYPE_VN && atype.defined == 0)
947 {
948 first_error (_("invalid use of vector register"));
949 }
950
951 if (typeinfo)
952 *typeinfo = atype;
953
954 if (rtype)
955 *rtype = type;
956
957 *ccp = str;
958
959 return reg->number;
960}
961
962/* Parse register.
963
964 Return the register number on success; return PARSE_FAIL otherwise.
965
966 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
967 the register (e.g. NEON double or quad reg when either has been requested).
968
969 If this is a NEON vector register with additional type information, fill
970 in the struct pointed to by VECTYPE (if non-NULL).
971
972 This parser does not handle register list. */
973
974static int
975aarch64_reg_parse (char **ccp, aarch64_reg_type type,
976 aarch64_reg_type *rtype, struct neon_type_el *vectype)
977{
978 struct neon_type_el atype;
979 char *str = *ccp;
980 int reg = parse_typed_reg (&str, type, rtype, &atype,
981 /*in_reg_list= */ FALSE);
982
983 if (reg == PARSE_FAIL)
984 return PARSE_FAIL;
985
986 if (vectype)
987 *vectype = atype;
988
989 *ccp = str;
990
991 return reg;
992}
993
994static inline bfd_boolean
995eq_neon_type_el (struct neon_type_el e1, struct neon_type_el e2)
996{
997 return
998 e1.type == e2.type
999 && e1.defined == e2.defined
1000 && e1.width == e2.width && e1.index == e2.index;
1001}
1002
1003/* This function parses the NEON register list. On success, it returns
1004 the parsed register list information in the following encoded format:
1005
1006 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1007 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1008
1009 The information of the register shape and/or index is returned in
1010 *VECTYPE.
1011
1012 It returns PARSE_FAIL if the register list is invalid.
1013
1014 The list contains one to four registers.
1015 Each register can be one of:
1016 <Vt>.<T>[<index>]
1017 <Vt>.<T>
1018 All <T> should be identical.
1019 All <index> should be identical.
1020 There are restrictions on <Vt> numbers which are checked later
1021 (by reg_list_valid_p). */
1022
1023static int
1024parse_neon_reg_list (char **ccp, struct neon_type_el *vectype)
1025{
1026 char *str = *ccp;
1027 int nb_regs;
1028 struct neon_type_el typeinfo, typeinfo_first;
1029 int val, val_range;
1030 int in_range;
1031 int ret_val;
1032 int i;
1033 bfd_boolean error = FALSE;
1034 bfd_boolean expect_index = FALSE;
1035
1036 if (*str != '{')
1037 {
1038 set_syntax_error (_("expecting {"));
1039 return PARSE_FAIL;
1040 }
1041 str++;
1042
1043 nb_regs = 0;
1044 typeinfo_first.defined = 0;
1045 typeinfo_first.type = NT_invtype;
1046 typeinfo_first.width = -1;
1047 typeinfo_first.index = 0;
1048 ret_val = 0;
1049 val = -1;
1050 val_range = -1;
1051 in_range = 0;
1052 do
1053 {
1054 if (in_range)
1055 {
1056 str++; /* skip over '-' */
1057 val_range = val;
1058 }
1059 val = parse_typed_reg (&str, REG_TYPE_VN, NULL, &typeinfo,
1060 /*in_reg_list= */ TRUE);
1061 if (val == PARSE_FAIL)
1062 {
1063 set_first_syntax_error (_("invalid vector register in list"));
1064 error = TRUE;
1065 continue;
1066 }
1067 /* reject [bhsd]n */
1068 if (typeinfo.defined == 0)
1069 {
1070 set_first_syntax_error (_("invalid scalar register in list"));
1071 error = TRUE;
1072 continue;
1073 }
1074
1075 if (typeinfo.defined & NTA_HASINDEX)
1076 expect_index = TRUE;
1077
1078 if (in_range)
1079 {
1080 if (val < val_range)
1081 {
1082 set_first_syntax_error
1083 (_("invalid range in vector register list"));
1084 error = TRUE;
1085 }
1086 val_range++;
1087 }
1088 else
1089 {
1090 val_range = val;
1091 if (nb_regs == 0)
1092 typeinfo_first = typeinfo;
1093 else if (! eq_neon_type_el (typeinfo_first, typeinfo))
1094 {
1095 set_first_syntax_error
1096 (_("type mismatch in vector register list"));
1097 error = TRUE;
1098 }
1099 }
1100 if (! error)
1101 for (i = val_range; i <= val; i++)
1102 {
1103 ret_val |= i << (5 * nb_regs);
1104 nb_regs++;
1105 }
1106 in_range = 0;
1107 }
1108 while (skip_past_comma (&str) || (in_range = 1, *str == '-'));
1109
1110 skip_whitespace (str);
1111 if (*str != '}')
1112 {
1113 set_first_syntax_error (_("end of vector register list not found"));
1114 error = TRUE;
1115 }
1116 str++;
1117
1118 skip_whitespace (str);
1119
1120 if (expect_index)
1121 {
1122 if (skip_past_char (&str, '['))
1123 {
1124 expressionS exp;
1125
1126 my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
1127 if (exp.X_op != O_constant)
1128 {
1129 set_first_syntax_error (_("constant expression required."));
1130 error = TRUE;
1131 }
1132 if (! skip_past_char (&str, ']'))
1133 error = TRUE;
1134 else
1135 typeinfo_first.index = exp.X_add_number;
1136 }
1137 else
1138 {
1139 set_first_syntax_error (_("expected index"));
1140 error = TRUE;
1141 }
1142 }
1143
1144 if (nb_regs > 4)
1145 {
1146 set_first_syntax_error (_("too many registers in vector register list"));
1147 error = TRUE;
1148 }
1149 else if (nb_regs == 0)
1150 {
1151 set_first_syntax_error (_("empty vector register list"));
1152 error = TRUE;
1153 }
1154
1155 *ccp = str;
1156 if (! error)
1157 *vectype = typeinfo_first;
1158
1159 return error ? PARSE_FAIL : (ret_val << 2) | (nb_regs - 1);
1160}
1161
1162/* Directives: register aliases. */
1163
1164static reg_entry *
1165insert_reg_alias (char *str, int number, aarch64_reg_type type)
1166{
1167 reg_entry *new;
1168 const char *name;
1169
1170 if ((new = hash_find (aarch64_reg_hsh, str)) != 0)
1171 {
1172 if (new->builtin)
1173 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1174 str);
1175
1176 /* Only warn about a redefinition if it's not defined as the
1177 same register. */
1178 else if (new->number != number || new->type != type)
1179 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1180
1181 return NULL;
1182 }
1183
1184 name = xstrdup (str);
1185 new = xmalloc (sizeof (reg_entry));
1186
1187 new->name = name;
1188 new->number = number;
1189 new->type = type;
1190 new->builtin = FALSE;
1191
1192 if (hash_insert (aarch64_reg_hsh, name, (void *) new))
1193 abort ();
1194
1195 return new;
1196}
1197
1198/* Look for the .req directive. This is of the form:
1199
1200 new_register_name .req existing_register_name
1201
1202 If we find one, or if it looks sufficiently like one that we want to
1203 handle any error here, return TRUE. Otherwise return FALSE. */
1204
1205static bfd_boolean
1206create_register_alias (char *newname, char *p)
1207{
1208 const reg_entry *old;
1209 char *oldname, *nbuf;
1210 size_t nlen;
1211
1212 /* The input scrubber ensures that whitespace after the mnemonic is
1213 collapsed to single spaces. */
1214 oldname = p;
1215 if (strncmp (oldname, " .req ", 6) != 0)
1216 return FALSE;
1217
1218 oldname += 6;
1219 if (*oldname == '\0')
1220 return FALSE;
1221
1222 old = hash_find (aarch64_reg_hsh, oldname);
1223 if (!old)
1224 {
1225 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
1226 return TRUE;
1227 }
1228
1229 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1230 the desired alias name, and p points to its end. If not, then
1231 the desired alias name is in the global original_case_string. */
1232#ifdef TC_CASE_SENSITIVE
1233 nlen = p - newname;
1234#else
1235 newname = original_case_string;
1236 nlen = strlen (newname);
1237#endif
1238
1239 nbuf = alloca (nlen + 1);
1240 memcpy (nbuf, newname, nlen);
1241 nbuf[nlen] = '\0';
1242
1243 /* Create aliases under the new name as stated; an all-lowercase
1244 version of the new name; and an all-uppercase version of the new
1245 name. */
1246 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
1247 {
1248 for (p = nbuf; *p; p++)
1249 *p = TOUPPER (*p);
1250
1251 if (strncmp (nbuf, newname, nlen))
1252 {
1253 /* If this attempt to create an additional alias fails, do not bother
1254 trying to create the all-lower case alias. We will fail and issue
1255 a second, duplicate error message. This situation arises when the
1256 programmer does something like:
1257 foo .req r0
1258 Foo .req r1
1259 The second .req creates the "Foo" alias but then fails to create
1260 the artificial FOO alias because it has already been created by the
1261 first .req. */
1262 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
1263 return TRUE;
1264 }
1265
1266 for (p = nbuf; *p; p++)
1267 *p = TOLOWER (*p);
1268
1269 if (strncmp (nbuf, newname, nlen))
1270 insert_reg_alias (nbuf, old->number, old->type);
1271 }
1272
1273 return TRUE;
1274}
1275
1276/* Should never be called, as .req goes between the alias and the
1277 register name, not at the beginning of the line. */
1278static void
1279s_req (int a ATTRIBUTE_UNUSED)
1280{
1281 as_bad (_("invalid syntax for .req directive"));
1282}
1283
1284/* The .unreq directive deletes an alias which was previously defined
1285 by .req. For example:
1286
1287 my_alias .req r11
1288 .unreq my_alias */
1289
1290static void
1291s_unreq (int a ATTRIBUTE_UNUSED)
1292{
1293 char *name;
1294 char saved_char;
1295
1296 name = input_line_pointer;
1297
1298 while (*input_line_pointer != 0
1299 && *input_line_pointer != ' ' && *input_line_pointer != '\n')
1300 ++input_line_pointer;
1301
1302 saved_char = *input_line_pointer;
1303 *input_line_pointer = 0;
1304
1305 if (!*name)
1306 as_bad (_("invalid syntax for .unreq directive"));
1307 else
1308 {
1309 reg_entry *reg = hash_find (aarch64_reg_hsh, name);
1310
1311 if (!reg)
1312 as_bad (_("unknown register alias '%s'"), name);
1313 else if (reg->builtin)
1314 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1315 name);
1316 else
1317 {
1318 char *p;
1319 char *nbuf;
1320
1321 hash_delete (aarch64_reg_hsh, name, FALSE);
1322 free ((char *) reg->name);
1323 free (reg);
1324
1325 /* Also locate the all upper case and all lower case versions.
1326 Do not complain if we cannot find one or the other as it
1327 was probably deleted above. */
1328
1329 nbuf = strdup (name);
1330 for (p = nbuf; *p; p++)
1331 *p = TOUPPER (*p);
1332 reg = hash_find (aarch64_reg_hsh, nbuf);
1333 if (reg)
1334 {
1335 hash_delete (aarch64_reg_hsh, nbuf, FALSE);
1336 free ((char *) reg->name);
1337 free (reg);
1338 }
1339
1340 for (p = nbuf; *p; p++)
1341 *p = TOLOWER (*p);
1342 reg = hash_find (aarch64_reg_hsh, nbuf);
1343 if (reg)
1344 {
1345 hash_delete (aarch64_reg_hsh, nbuf, FALSE);
1346 free ((char *) reg->name);
1347 free (reg);
1348 }
1349
1350 free (nbuf);
1351 }
1352 }
1353
1354 *input_line_pointer = saved_char;
1355 demand_empty_rest_of_line ();
1356}
1357
1358/* Directives: Instruction set selection. */
1359
1360#ifdef OBJ_ELF
1361/* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1362 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1363 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1364 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1365
1366/* Create a new mapping symbol for the transition to STATE. */
1367
1368static void
1369make_mapping_symbol (enum mstate state, valueT value, fragS * frag)
1370{
1371 symbolS *symbolP;
1372 const char *symname;
1373 int type;
1374
1375 switch (state)
1376 {
1377 case MAP_DATA:
1378 symname = "$d";
1379 type = BSF_NO_FLAGS;
1380 break;
1381 case MAP_INSN:
1382 symname = "$x";
1383 type = BSF_NO_FLAGS;
1384 break;
1385 default:
1386 abort ();
1387 }
1388
1389 symbolP = symbol_new (symname, now_seg, value, frag);
1390 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
1391
1392 /* Save the mapping symbols for future reference. Also check that
1393 we do not place two mapping symbols at the same offset within a
1394 frag. We'll handle overlap between frags in
1395 check_mapping_symbols.
1396
1397 If .fill or other data filling directive generates zero sized data,
1398 the mapping symbol for the following code will have the same value
1399 as the one generated for the data filling directive. In this case,
1400 we replace the old symbol with the new one at the same address. */
1401 if (value == 0)
1402 {
1403 if (frag->tc_frag_data.first_map != NULL)
1404 {
1405 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
1406 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP,
1407 &symbol_lastP);
1408 }
1409 frag->tc_frag_data.first_map = symbolP;
1410 }
1411 if (frag->tc_frag_data.last_map != NULL)
1412 {
1413 know (S_GET_VALUE (frag->tc_frag_data.last_map) <=
1414 S_GET_VALUE (symbolP));
1415 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
1416 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP,
1417 &symbol_lastP);
1418 }
1419 frag->tc_frag_data.last_map = symbolP;
1420}
1421
1422/* We must sometimes convert a region marked as code to data during
1423 code alignment, if an odd number of bytes have to be padded. The
1424 code mapping symbol is pushed to an aligned address. */
1425
1426static void
1427insert_data_mapping_symbol (enum mstate state,
1428 valueT value, fragS * frag, offsetT bytes)
1429{
1430 /* If there was already a mapping symbol, remove it. */
1431 if (frag->tc_frag_data.last_map != NULL
1432 && S_GET_VALUE (frag->tc_frag_data.last_map) ==
1433 frag->fr_address + value)
1434 {
1435 symbolS *symp = frag->tc_frag_data.last_map;
1436
1437 if (value == 0)
1438 {
1439 know (frag->tc_frag_data.first_map == symp);
1440 frag->tc_frag_data.first_map = NULL;
1441 }
1442 frag->tc_frag_data.last_map = NULL;
1443 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
1444 }
1445
1446 make_mapping_symbol (MAP_DATA, value, frag);
1447 make_mapping_symbol (state, value + bytes, frag);
1448}
1449
1450static void mapping_state_2 (enum mstate state, int max_chars);
1451
1452/* Set the mapping state to STATE. Only call this when about to
1453 emit some STATE bytes to the file. */
1454
1455void
1456mapping_state (enum mstate state)
1457{
1458 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1459
1460#define TRANSITION(from, to) (mapstate == (from) && state == (to))
1461
1462 if (mapstate == state)
1463 /* The mapping symbol has already been emitted.
1464 There is nothing else to do. */
1465 return;
1466 else if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
1467 /* This case will be evaluated later in the next else. */
1468 return;
1469 else if (TRANSITION (MAP_UNDEFINED, MAP_INSN))
1470 {
1471 /* Only add the symbol if the offset is > 0:
1472 if we're at the first frag, check it's size > 0;
1473 if we're not at the first frag, then for sure
1474 the offset is > 0. */
1475 struct frag *const frag_first = seg_info (now_seg)->frchainP->frch_root;
1476 const int add_symbol = (frag_now != frag_first)
1477 || (frag_now_fix () > 0);
1478
1479 if (add_symbol)
1480 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
1481 }
1482
1483 mapping_state_2 (state, 0);
1484#undef TRANSITION
1485}
1486
1487/* Same as mapping_state, but MAX_CHARS bytes have already been
1488 allocated. Put the mapping symbol that far back. */
1489
1490static void
1491mapping_state_2 (enum mstate state, int max_chars)
1492{
1493 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1494
1495 if (!SEG_NORMAL (now_seg))
1496 return;
1497
1498 if (mapstate == state)
1499 /* The mapping symbol has already been emitted.
1500 There is nothing else to do. */
1501 return;
1502
1503 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
1504 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
1505}
1506#else
1507#define mapping_state(x) /* nothing */
1508#define mapping_state_2(x, y) /* nothing */
1509#endif
1510
1511/* Directives: sectioning and alignment. */
1512
1513static void
1514s_bss (int ignore ATTRIBUTE_UNUSED)
1515{
1516 /* We don't support putting frags in the BSS segment, we fake it by
1517 marking in_bss, then looking at s_skip for clues. */
1518 subseg_set (bss_section, 0);
1519 demand_empty_rest_of_line ();
1520 mapping_state (MAP_DATA);
1521}
1522
1523static void
1524s_even (int ignore ATTRIBUTE_UNUSED)
1525{
1526 /* Never make frag if expect extra pass. */
1527 if (!need_pass_2)
1528 frag_align (1, 0, 0);
1529
1530 record_alignment (now_seg, 1);
1531
1532 demand_empty_rest_of_line ();
1533}
1534
1535/* Directives: Literal pools. */
1536
1537static literal_pool *
1538find_literal_pool (int size)
1539{
1540 literal_pool *pool;
1541
1542 for (pool = list_of_pools; pool != NULL; pool = pool->next)
1543 {
1544 if (pool->section == now_seg
1545 && pool->sub_section == now_subseg && pool->size == size)
1546 break;
1547 }
1548
1549 return pool;
1550}
1551
1552static literal_pool *
1553find_or_make_literal_pool (int size)
1554{
1555 /* Next literal pool ID number. */
1556 static unsigned int latest_pool_num = 1;
1557 literal_pool *pool;
1558
1559 pool = find_literal_pool (size);
1560
1561 if (pool == NULL)
1562 {
1563 /* Create a new pool. */
1564 pool = xmalloc (sizeof (*pool));
1565 if (!pool)
1566 return NULL;
1567
1568 /* Currently we always put the literal pool in the current text
1569 section. If we were generating "small" model code where we
1570 knew that all code and initialised data was within 1MB then
1571 we could output literals to mergeable, read-only data
1572 sections. */
1573
1574 pool->next_free_entry = 0;
1575 pool->section = now_seg;
1576 pool->sub_section = now_subseg;
1577 pool->size = size;
1578 pool->next = list_of_pools;
1579 pool->symbol = NULL;
1580
1581 /* Add it to the list. */
1582 list_of_pools = pool;
1583 }
1584
1585 /* New pools, and emptied pools, will have a NULL symbol. */
1586 if (pool->symbol == NULL)
1587 {
1588 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
1589 (valueT) 0, &zero_address_frag);
1590 pool->id = latest_pool_num++;
1591 }
1592
1593 /* Done. */
1594 return pool;
1595}
1596
1597/* Add the literal of size SIZE in *EXP to the relevant literal pool.
1598 Return TRUE on success, otherwise return FALSE. */
1599static bfd_boolean
1600add_to_lit_pool (expressionS *exp, int size)
1601{
1602 literal_pool *pool;
1603 unsigned int entry;
1604
1605 pool = find_or_make_literal_pool (size);
1606
1607 /* Check if this literal value is already in the pool. */
1608 for (entry = 0; entry < pool->next_free_entry; entry++)
1609 {
1610 if ((pool->literals[entry].X_op == exp->X_op)
1611 && (exp->X_op == O_constant)
1612 && (pool->literals[entry].X_add_number == exp->X_add_number)
1613 && (pool->literals[entry].X_unsigned == exp->X_unsigned))
1614 break;
1615
1616 if ((pool->literals[entry].X_op == exp->X_op)
1617 && (exp->X_op == O_symbol)
1618 && (pool->literals[entry].X_add_number == exp->X_add_number)
1619 && (pool->literals[entry].X_add_symbol == exp->X_add_symbol)
1620 && (pool->literals[entry].X_op_symbol == exp->X_op_symbol))
1621 break;
1622 }
1623
1624 /* Do we need to create a new entry? */
1625 if (entry == pool->next_free_entry)
1626 {
1627 if (entry >= MAX_LITERAL_POOL_SIZE)
1628 {
1629 set_syntax_error (_("literal pool overflow"));
1630 return FALSE;
1631 }
1632
1633 pool->literals[entry] = *exp;
1634 pool->next_free_entry += 1;
1635 }
1636
1637 exp->X_op = O_symbol;
1638 exp->X_add_number = ((int) entry) * size;
1639 exp->X_add_symbol = pool->symbol;
1640
1641 return TRUE;
1642}
1643
1644/* Can't use symbol_new here, so have to create a symbol and then at
1645 a later date assign it a value. Thats what these functions do. */
1646
1647static void
1648symbol_locate (symbolS * symbolP,
1649 const char *name,/* It is copied, the caller can modify. */
1650 segT segment, /* Segment identifier (SEG_<something>). */
1651 valueT valu, /* Symbol value. */
1652 fragS * frag) /* Associated fragment. */
1653{
1654 unsigned int name_length;
1655 char *preserved_copy_of_name;
1656
1657 name_length = strlen (name) + 1; /* +1 for \0. */
1658 obstack_grow (&notes, name, name_length);
1659 preserved_copy_of_name = obstack_finish (&notes);
1660
1661#ifdef tc_canonicalize_symbol_name
1662 preserved_copy_of_name =
1663 tc_canonicalize_symbol_name (preserved_copy_of_name);
1664#endif
1665
1666 S_SET_NAME (symbolP, preserved_copy_of_name);
1667
1668 S_SET_SEGMENT (symbolP, segment);
1669 S_SET_VALUE (symbolP, valu);
1670 symbol_clear_list_pointers (symbolP);
1671
1672 symbol_set_frag (symbolP, frag);
1673
1674 /* Link to end of symbol chain. */
1675 {
1676 extern int symbol_table_frozen;
1677
1678 if (symbol_table_frozen)
1679 abort ();
1680 }
1681
1682 symbol_append (symbolP, symbol_lastP, &symbol_rootP, &symbol_lastP);
1683
1684 obj_symbol_new_hook (symbolP);
1685
1686#ifdef tc_symbol_new_hook
1687 tc_symbol_new_hook (symbolP);
1688#endif
1689
1690#ifdef DEBUG_SYMS
1691 verify_symbol_chain (symbol_rootP, symbol_lastP);
1692#endif /* DEBUG_SYMS */
1693}
1694
1695
1696static void
1697s_ltorg (int ignored ATTRIBUTE_UNUSED)
1698{
1699 unsigned int entry;
1700 literal_pool *pool;
1701 char sym_name[20];
1702 int align;
1703
67a32447 1704 for (align = 2; align <= 4; align++)
a06ea964
NC		 1705 {
1706 int size = 1 << align;
1707
1708 pool = find_literal_pool (size);
1709 if (pool == NULL || pool->symbol == NULL || pool->next_free_entry == 0)
1710 continue;
1711
1712 mapping_state (MAP_DATA);
1713
1714 /* Align pool as you have word accesses.
1715 Only make a frag if we have to. */
1716 if (!need_pass_2)
1717 frag_align (align, 0, 0);
1718
1719 record_alignment (now_seg, align);
1720
1721 sprintf (sym_name, "$$lit_\002%x", pool->id);
1722
1723 symbol_locate (pool->symbol, sym_name, now_seg,
1724 (valueT) frag_now_fix (), frag_now);
1725 symbol_table_insert (pool->symbol);
1726
1727 for (entry = 0; entry < pool->next_free_entry; entry++)
1728 /* First output the expression in the instruction to the pool. */
1729 emit_expr (&(pool->literals[entry]), size); /* .word|.xword */
1730
1731 /* Mark the pool as empty. */
1732 pool->next_free_entry = 0;
1733 pool->symbol = NULL;
1734 }
1735}
1736
1737#ifdef OBJ_ELF
1738/* Forward declarations for functions below, in the MD interface
1739 section. */
1740static fixS *fix_new_aarch64 (fragS *, int, short, expressionS *, int, int);
1741static struct reloc_table_entry * find_reloc_table_entry (char **);
1742
1743/* Directives: Data. */
1744/* N.B. the support for relocation suffix in this directive needs to be
1745 implemented properly. */
1746
1747static void
1748s_aarch64_elf_cons (int nbytes)
1749{
1750 expressionS exp;
1751
1752#ifdef md_flush_pending_output
1753 md_flush_pending_output ();
1754#endif
1755
1756 if (is_it_end_of_statement ())
1757 {
1758 demand_empty_rest_of_line ();
1759 return;
1760 }
1761
1762#ifdef md_cons_align
1763 md_cons_align (nbytes);
1764#endif
1765
1766 mapping_state (MAP_DATA);
1767 do
1768 {
1769 struct reloc_table_entry *reloc;
1770
1771 expression (&exp);
1772
1773 if (exp.X_op != O_symbol)
1774 emit_expr (&exp, (unsigned int) nbytes);
1775 else
1776 {
1777 skip_past_char (&input_line_pointer, '#');
1778 if (skip_past_char (&input_line_pointer, ':'))
1779 {
1780 reloc = find_reloc_table_entry (&input_line_pointer);
1781 if (reloc == NULL)
1782 as_bad (_("unrecognized relocation suffix"));
1783 else
1784 as_bad (_("unimplemented relocation suffix"));
1785 ignore_rest_of_line ();
1786 return;
1787 }
1788 else
1789 emit_expr (&exp, (unsigned int) nbytes);
1790 }
1791 }
1792 while (*input_line_pointer++ == ',');
1793
1794 /* Put terminator back into stream. */
1795 input_line_pointer--;
1796 demand_empty_rest_of_line ();
1797}
1798
1799#endif /* OBJ_ELF */
1800
1801/* Output a 32-bit word, but mark as an instruction. */
1802
1803static void
1804s_aarch64_inst (int ignored ATTRIBUTE_UNUSED)
1805{
1806 expressionS exp;
1807
1808#ifdef md_flush_pending_output
1809 md_flush_pending_output ();
1810#endif
1811
1812 if (is_it_end_of_statement ())
1813 {
1814 demand_empty_rest_of_line ();
1815 return;
1816 }
1817
1818 if (!need_pass_2)
1819 frag_align_code (2, 0);
1820#ifdef OBJ_ELF
1821 mapping_state (MAP_INSN);
1822#endif
1823
1824 do
1825 {
1826 expression (&exp);
1827 if (exp.X_op != O_constant)
1828 {
1829 as_bad (_("constant expression required"));
1830 ignore_rest_of_line ();
1831 return;
1832 }
1833
1834 if (target_big_endian)
1835 {
1836 unsigned int val = exp.X_add_number;
1837 exp.X_add_number = SWAP_32 (val);
1838 }
1839 emit_expr (&exp, 4);
1840 }
1841 while (*input_line_pointer++ == ',');
1842
1843 /* Put terminator back into stream. */
1844 input_line_pointer--;
1845 demand_empty_rest_of_line ();
1846}
1847
1848#ifdef OBJ_ELF
1849/* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1850
1851static void
1852s_tlsdesccall (int ignored ATTRIBUTE_UNUSED)
1853{
1854 expressionS exp;
1855
1856 /* Since we're just labelling the code, there's no need to define a
1857 mapping symbol. */
1858 expression (&exp);
1859 /* Make sure there is enough room in this frag for the following
1860 blr. This trick only works if the blr follows immediately after
1861 the .tlsdesc directive. */
1862 frag_grow (4);
1863 fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
1864 BFD_RELOC_AARCH64_TLSDESC_CALL);
1865
1866 demand_empty_rest_of_line ();
1867}
1868#endif /* OBJ_ELF */
1869
1870static void s_aarch64_arch (int);
1871static void s_aarch64_cpu (int);
1872
1873/* This table describes all the machine specific pseudo-ops the assembler
1874 has to support. The fields are:
1875 pseudo-op name without dot
1876 function to call to execute this pseudo-op
1877 Integer arg to pass to the function. */
1878
1879const pseudo_typeS md_pseudo_table[] = {
1880 /* Never called because '.req' does not start a line. */
1881 {"req", s_req, 0},
1882 {"unreq", s_unreq, 0},
1883 {"bss", s_bss, 0},
1884 {"even", s_even, 0},
1885 {"ltorg", s_ltorg, 0},
1886 {"pool", s_ltorg, 0},
1887 {"cpu", s_aarch64_cpu, 0},
1888 {"arch", s_aarch64_arch, 0},
1889 {"inst", s_aarch64_inst, 0},
1890#ifdef OBJ_ELF
1891 {"tlsdesccall", s_tlsdesccall, 0},
1892 {"word", s_aarch64_elf_cons, 4},
1893 {"long", s_aarch64_elf_cons, 4},
1894 {"xword", s_aarch64_elf_cons, 8},
1895 {"dword", s_aarch64_elf_cons, 8},
1896#endif
1897 {0, 0, 0}
1898};
1899\f
1900
1901/* Check whether STR points to a register name followed by a comma or the
1902 end of line; REG_TYPE indicates which register types are checked
1903 against. Return TRUE if STR is such a register name; otherwise return
1904 FALSE. The function does not intend to produce any diagnostics, but since
1905 the register parser aarch64_reg_parse, which is called by this function,
1906 does produce diagnostics, we call clear_error to clear any diagnostics
1907 that may be generated by aarch64_reg_parse.
1908 Also, the function returns FALSE directly if there is any user error
1909 present at the function entry. This prevents the existing diagnostics
1910 state from being spoiled.
1911 The function currently serves parse_constant_immediate and
1912 parse_big_immediate only. */
1913static bfd_boolean
1914reg_name_p (char *str, aarch64_reg_type reg_type)
1915{
1916 int reg;
1917
1918 /* Prevent the diagnostics state from being spoiled. */
1919 if (error_p ())
1920 return FALSE;
1921
1922 reg = aarch64_reg_parse (&str, reg_type, NULL, NULL);
1923
1924 /* Clear the parsing error that may be set by the reg parser. */
1925 clear_error ();
1926
1927 if (reg == PARSE_FAIL)
1928 return FALSE;
1929
1930 skip_whitespace (str);
1931 if (*str == ',' || is_end_of_line[(unsigned int) *str])
1932 return TRUE;
1933
1934 return FALSE;
1935}
1936
1937/* Parser functions used exclusively in instruction operands. */
1938
1939/* Parse an immediate expression which may not be constant.
1940
1941 To prevent the expression parser from pushing a register name
1942 into the symbol table as an undefined symbol, firstly a check is
1943 done to find out whether STR is a valid register name followed
1944 by a comma or the end of line. Return FALSE if STR is such a
1945 string. */
1946
1947static bfd_boolean
1948parse_immediate_expression (char **str, expressionS *exp)
1949{
1950 if (reg_name_p (*str, REG_TYPE_R_Z_BHSDQ_V))
1951 {
1952 set_recoverable_error (_("immediate operand required"));
1953 return FALSE;
1954 }
1955
1956 my_get_expression (exp, str, GE_OPT_PREFIX, 1);
1957
1958 if (exp->X_op == O_absent)
1959 {
1960 set_fatal_syntax_error (_("missing immediate expression"));
1961 return FALSE;
1962 }
1963
1964 return TRUE;
1965}
1966
1967/* Constant immediate-value read function for use in insn parsing.
1968 STR points to the beginning of the immediate (with the optional
1969 leading #); *VAL receives the value.
1970
1971 Return TRUE on success; otherwise return FALSE. */
1972
1973static bfd_boolean
1974parse_constant_immediate (char **str, int64_t * val)
1975{
1976 expressionS exp;
1977
1978 if (! parse_immediate_expression (str, &exp))
1979 return FALSE;
1980
1981 if (exp.X_op != O_constant)
1982 {
1983 set_syntax_error (_("constant expression required"));
1984 return FALSE;
1985 }
1986
1987 *val = exp.X_add_number;
1988 return TRUE;
1989}
1990
1991static uint32_t
1992encode_imm_float_bits (uint32_t imm)
1993{
1994 return ((imm >> 19) & 0x7f) /* b[25:19] -> b[6:0] */
1995 | ((imm >> (31 - 7)) & 0x80); /* b[31] -> b[7] */
1996}
1997
62b0d0d5
YZ		 1998/* Return TRUE if the single-precision floating-point value encoded in IMM
1999 can be expressed in the AArch64 8-bit signed floating-point format with
2000 3-bit exponent and normalized 4 bits of precision; in other words, the
2001 floating-point value must be expressable as
2002 (+/-) n / 16 * power (2, r)
2003 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2004
a06ea964
NC		 2005static bfd_boolean
2006aarch64_imm_float_p (uint32_t imm)
2007{
62b0d0d5
YZ		 2008 /* If a single-precision floating-point value has the following bit
2009 pattern, it can be expressed in the AArch64 8-bit floating-point
2010 format:
2011
2012 3 32222222 2221111111111
a06ea964 2013 1 09876543 21098765432109876543210
62b0d0d5
YZ		 2014 n Eeeeeexx xxxx0000000000000000000
2015
2016 where n, e and each x are either 0 or 1 independently, with
2017 E == ~ e. */
a06ea964 2018
62b0d0d5
YZ		 2019 uint32_t pattern;
2020
2021 /* Prepare the pattern for 'Eeeeee'. */
2022 if (((imm >> 30) & 0x1) == 0)
2023 pattern = 0x3e000000;
a06ea964 2024 else
62b0d0d5
YZ		 2025 pattern = 0x40000000;
2026
2027 return (imm & 0x7ffff) == 0 /* lower 19 bits are 0. */
2028 && ((imm & 0x7e000000) == pattern); /* bits 25 - 29 == ~ bit 30. */
a06ea964
NC		 2029}
2030
62b0d0d5
YZ		 2031/* Like aarch64_imm_float_p but for a double-precision floating-point value.
2032
2033 Return TRUE if the value encoded in IMM can be expressed in the AArch64
2034 8-bit signed floating-point format with 3-bit exponent and normalized 4
2035 bits of precision (i.e. can be used in an FMOV instruction); return the
2036 equivalent single-precision encoding in *FPWORD.
2037
2038 Otherwise return FALSE. */
2039
a06ea964 2040static bfd_boolean
62b0d0d5
YZ		 2041aarch64_double_precision_fmovable (uint64_t imm, uint32_t *fpword)
2042{
2043 /* If a double-precision floating-point value has the following bit
2044 pattern, it can be expressed in the AArch64 8-bit floating-point
2045 format:
2046
2047 6 66655555555 554444444...21111111111
2048 3 21098765432 109876543...098765432109876543210
2049 n Eeeeeeeeexx xxxx00000...000000000000000000000
2050
2051 where n, e and each x are either 0 or 1 independently, with
2052 E == ~ e. */
2053
2054 uint32_t pattern;
2055 uint32_t high32 = imm >> 32;
2056
2057 /* Lower 32 bits need to be 0s. */
2058 if ((imm & 0xffffffff) != 0)
2059 return FALSE;
2060
2061 /* Prepare the pattern for 'Eeeeeeeee'. */
2062 if (((high32 >> 30) & 0x1) == 0)
2063 pattern = 0x3fc00000;
2064 else
2065 pattern = 0x40000000;
2066
2067 if ((high32 & 0xffff) == 0 /* bits 32 - 47 are 0. */
2068 && (high32 & 0x7fc00000) == pattern) /* bits 54 - 61 == ~ bit 62. */
2069 {
2070 /* Convert to the single-precision encoding.
2071 i.e. convert
2072 n Eeeeeeeeexx xxxx00000...000000000000000000000
2073 to
2074 n Eeeeeexx xxxx0000000000000000000. */
2075 *fpword = ((high32 & 0xfe000000) /* nEeeeee. */
2076 | (((high32 >> 16) & 0x3f) << 19)); /* xxxxxx. */
2077 return TRUE;
2078 }
2079 else
2080 return FALSE;
2081}
2082
2083/* Parse a floating-point immediate. Return TRUE on success and return the
2084 value in *IMMED in the format of IEEE754 single-precision encoding.
2085 *CCP points to the start of the string; DP_P is TRUE when the immediate
2086 is expected to be in double-precision (N.B. this only matters when
2087 hexadecimal representation is involved).
2088
2089 N.B. 0.0 is accepted by this function. */
2090
2091static bfd_boolean
2092parse_aarch64_imm_float (char **ccp, int *immed, bfd_boolean dp_p)
a06ea964
NC		 2093{
2094 char *str = *ccp;
2095 char *fpnum;
2096 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2097 int found_fpchar = 0;
62b0d0d5
YZ		 2098 int64_t val = 0;
2099 unsigned fpword = 0;
2100 bfd_boolean hex_p = FALSE;
a06ea964
NC		 2101
2102 skip_past_char (&str, '#');
2103
a06ea964
NC		 2104 fpnum = str;
2105 skip_whitespace (fpnum);
2106
2107 if (strncmp (fpnum, "0x", 2) == 0)
62b0d0d5
YZ		 2108 {
2109 /* Support the hexadecimal representation of the IEEE754 encoding.
2110 Double-precision is expected when DP_P is TRUE, otherwise the
2111 representation should be in single-precision. */
2112 if (! parse_constant_immediate (&str, &val))
2113 goto invalid_fp;
2114
2115 if (dp_p)
2116 {
2117 if (! aarch64_double_precision_fmovable (val, &fpword))
2118 goto invalid_fp;
2119 }
2120 else if ((uint64_t) val > 0xffffffff)
2121 goto invalid_fp;
2122 else
2123 fpword = val;
2124
2125 hex_p = TRUE;
2126 }
a06ea964
NC		 2127 else
2128 {
62b0d0d5
YZ		 2129 /* We must not accidentally parse an integer as a floating-point number.
2130 Make sure that the value we parse is not an integer by checking for
2131 special characters '.' or 'e'. */
a06ea964
NC		 2132 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
2133 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
2134 {
2135 found_fpchar = 1;
2136 break;
2137 }
2138
2139 if (!found_fpchar)
2140 return FALSE;
2141 }
2142
62b0d0d5 2143 if (! hex_p)
a06ea964 2144 {
a06ea964
NC		 2145 int i;
2146
62b0d0d5
YZ		 2147 if ((str = atof_ieee (str, 's', words)) == NULL)
2148 goto invalid_fp;
2149
a06ea964
NC		 2150 /* Our FP word must be 32 bits (single-precision FP). */
2151 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
2152 {
2153 fpword <<= LITTLENUM_NUMBER_OF_BITS;
2154 fpword |= words[i];
2155 }
62b0d0d5 2156 }
a06ea964 2157
62b0d0d5
YZ		 2158 if (aarch64_imm_float_p (fpword) || (fpword & 0x7fffffff) == 0)
2159 {
2160 *immed = fpword;
a06ea964 2161 *ccp = str;
a06ea964
NC		 2162 return TRUE;
2163 }
2164
2165invalid_fp:
2166 set_fatal_syntax_error (_("invalid floating-point constant"));
2167 return FALSE;
2168}
2169
2170/* Less-generic immediate-value read function with the possibility of loading
2171 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2172 instructions.
2173
2174 To prevent the expression parser from pushing a register name into the
2175 symbol table as an undefined symbol, a check is firstly done to find
2176 out whether STR is a valid register name followed by a comma or the end
2177 of line. Return FALSE if STR is such a register. */
2178
2179static bfd_boolean
2180parse_big_immediate (char **str, int64_t *imm)
2181{
2182 char *ptr = *str;
2183
2184 if (reg_name_p (ptr, REG_TYPE_R_Z_BHSDQ_V))
2185 {
2186 set_syntax_error (_("immediate operand required"));
2187 return FALSE;
2188 }
2189
2190 my_get_expression (&inst.reloc.exp, &ptr, GE_OPT_PREFIX, 1);
2191
2192 if (inst.reloc.exp.X_op == O_constant)
2193 *imm = inst.reloc.exp.X_add_number;
2194
2195 *str = ptr;
2196
2197 return TRUE;
2198}
2199
2200/* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2201 if NEED_LIBOPCODES is non-zero, the fixup will need
2202 assistance from the libopcodes. */
2203
2204static inline void
2205aarch64_set_gas_internal_fixup (struct reloc *reloc,
2206 const aarch64_opnd_info *operand,
2207 int need_libopcodes_p)
2208{
2209 reloc->type = BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
2210 reloc->opnd = operand->type;
2211 if (need_libopcodes_p)
2212 reloc->need_libopcodes_p = 1;
2213};
2214
2215/* Return TRUE if the instruction needs to be fixed up later internally by
2216 the GAS; otherwise return FALSE. */
2217
2218static inline bfd_boolean
2219aarch64_gas_internal_fixup_p (void)
2220{
2221 return inst.reloc.type == BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
2222}
2223
2224/* Assign the immediate value to the relavant field in *OPERAND if
2225 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2226 needs an internal fixup in a later stage.
2227 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2228 IMM.VALUE that may get assigned with the constant. */
2229static inline void
2230assign_imm_if_const_or_fixup_later (struct reloc *reloc,
2231 aarch64_opnd_info *operand,
2232 int addr_off_p,
2233 int need_libopcodes_p,
2234 int skip_p)
2235{
2236 if (reloc->exp.X_op == O_constant)
2237 {
2238 if (addr_off_p)
2239 operand->addr.offset.imm = reloc->exp.X_add_number;
2240 else
2241 operand->imm.value = reloc->exp.X_add_number;
2242 reloc->type = BFD_RELOC_UNUSED;
2243 }
2244 else
2245 {
2246 aarch64_set_gas_internal_fixup (reloc, operand, need_libopcodes_p);
2247 /* Tell libopcodes to ignore this operand or not. This is helpful
2248 when one of the operands needs to be fixed up later but we need
2249 libopcodes to check the other operands. */
2250 operand->skip = skip_p;
2251 }
2252}
2253
2254/* Relocation modifiers. Each entry in the table contains the textual
2255 name for the relocation which may be placed before a symbol used as
2256 a load/store offset, or add immediate. It must be surrounded by a
2257 leading and trailing colon, for example:
2258
2259 ldr x0, [x1, #:rello:varsym]
2260 add x0, x1, #:rello:varsym */
2261
2262struct reloc_table_entry
2263{
2264 const char *name;
2265 int pc_rel;
2266 bfd_reloc_code_real_type adrp_type;
2267 bfd_reloc_code_real_type movw_type;
2268 bfd_reloc_code_real_type add_type;
2269 bfd_reloc_code_real_type ldst_type;
2270};
2271
2272static struct reloc_table_entry reloc_table[] = {
2273 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2274 {"lo12", 0,
2275 0,
2276 0,
2277 BFD_RELOC_AARCH64_ADD_LO12,
2278 BFD_RELOC_AARCH64_LDST_LO12},
2279
2280 /* Higher 21 bits of pc-relative page offset: ADRP */
2281 {"pg_hi21", 1,
2282 BFD_RELOC_AARCH64_ADR_HI21_PCREL,
2283 0,
2284 0,
2285 0},
2286
2287 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2288 {"pg_hi21_nc", 1,
2289 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL,
2290 0,
2291 0,
2292 0},
2293
2294 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2295 {"abs_g0", 0,
2296 0,
2297 BFD_RELOC_AARCH64_MOVW_G0,
2298 0,
2299 0},
2300
2301 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2302 {"abs_g0_s", 0,
2303 0,
2304 BFD_RELOC_AARCH64_MOVW_G0_S,
2305 0,
2306 0},
2307
2308 /* Less significant bits 0-15 of address/value: MOVK, no check */
2309 {"abs_g0_nc", 0,
2310 0,
2311 BFD_RELOC_AARCH64_MOVW_G0_NC,
2312 0,
2313 0},
2314
2315 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2316 {"abs_g1", 0,
2317 0,
2318 BFD_RELOC_AARCH64_MOVW_G1,
2319 0,
2320 0},
2321
2322 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2323 {"abs_g1_s", 0,
2324 0,
2325 BFD_RELOC_AARCH64_MOVW_G1_S,
2326 0,
2327 0},
2328
2329 /* Less significant bits 16-31 of address/value: MOVK, no check */
2330 {"abs_g1_nc", 0,
2331 0,
2332 BFD_RELOC_AARCH64_MOVW_G1_NC,
2333 0,
2334 0},
2335
2336 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2337 {"abs_g2", 0,
2338 0,
2339 BFD_RELOC_AARCH64_MOVW_G2,
2340 0,
2341 0},
2342
2343 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2344 {"abs_g2_s", 0,
2345 0,
2346 BFD_RELOC_AARCH64_MOVW_G2_S,
2347 0,
2348 0},
2349
2350 /* Less significant bits 32-47 of address/value: MOVK, no check */
2351 {"abs_g2_nc", 0,
2352 0,
2353 BFD_RELOC_AARCH64_MOVW_G2_NC,
2354 0,
2355 0},
2356
2357 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2358 {"abs_g3", 0,
2359 0,
2360 BFD_RELOC_AARCH64_MOVW_G3,
2361 0,
2362 0},
4aa2c5e2 2363
a06ea964
NC		 2364 /* Get to the page containing GOT entry for a symbol. */
2365 {"got", 1,
2366 BFD_RELOC_AARCH64_ADR_GOT_PAGE,
2367 0,
2368 0,
4aa2c5e2
MS		 2369 BFD_RELOC_AARCH64_GOT_LD_PREL19},
2370
a06ea964
NC		 2371 /* 12 bit offset into the page containing GOT entry for that symbol. */
2372 {"got_lo12", 0,
2373 0,
2374 0,
2375 0,
a6bb11b2 2376 BFD_RELOC_AARCH64_LD_GOT_LO12_NC},
a06ea964
NC		 2377
2378 /* Get to the page containing GOT TLS entry for a symbol */
2379 {"tlsgd", 0,
2380 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21,
2381 0,
2382 0,
2383 0},
2384
2385 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2386 {"tlsgd_lo12", 0,
2387 0,
2388 0,
2389 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC,
2390 0},
2391
2392 /* Get to the page containing GOT TLS entry for a symbol */
2393 {"tlsdesc", 0,
418009c2 2394 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21,
a06ea964
NC		 2395 0,
2396 0,
2397 0},
2398
2399 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2400 {"tlsdesc_lo12", 0,
2401 0,
2402 0,
2403 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC,
a6bb11b2 2404 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC},
a06ea964
NC		 2405
2406 /* Get to the page containing GOT TLS entry for a symbol */
2407 {"gottprel", 0,
2408 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21,
2409 0,
2410 0,
2411 0},
2412
2413 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2414 {"gottprel_lo12", 0,
2415 0,
2416 0,
2417 0,
a6bb11b2 2418 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC},
a06ea964
NC		 2419
2420 /* Get tp offset for a symbol. */
2421 {"tprel", 0,
2422 0,
2423 0,
2424 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
2425 0},
2426
2427 /* Get tp offset for a symbol. */
2428 {"tprel_lo12", 0,
2429 0,
2430 0,
2431 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
2432 0},
2433
2434 /* Get tp offset for a symbol. */
2435 {"tprel_hi12", 0,
2436 0,
2437 0,
2438 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12,
2439 0},
2440
2441 /* Get tp offset for a symbol. */
2442 {"tprel_lo12_nc", 0,
2443 0,
2444 0,
2445 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
2446 0},
2447
2448 /* Most significant bits 32-47 of address/value: MOVZ. */
2449 {"tprel_g2", 0,
2450 0,
2451 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2,
2452 0,
2453 0},
2454
2455 /* Most significant bits 16-31 of address/value: MOVZ. */
2456 {"tprel_g1", 0,
2457 0,
2458 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1,
2459 0,
2460 0},
2461
2462 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2463 {"tprel_g1_nc", 0,
2464 0,
2465 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC,
2466 0,
2467 0},
2468
2469 /* Most significant bits 0-15 of address/value: MOVZ. */
2470 {"tprel_g0", 0,
2471 0,
2472 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0,
2473 0,
2474 0},
2475
2476 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2477 {"tprel_g0_nc", 0,
2478 0,
2479 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC,
2480 0,
2481 0},
2482};
2483
2484/* Given the address of a pointer pointing to the textual name of a
2485 relocation as may appear in assembler source, attempt to find its
2486 details in reloc_table. The pointer will be updated to the character
2487 after the trailing colon. On failure, NULL will be returned;
2488 otherwise return the reloc_table_entry. */
2489
2490static struct reloc_table_entry *
2491find_reloc_table_entry (char **str)
2492{
2493 unsigned int i;
2494 for (i = 0; i < ARRAY_SIZE (reloc_table); i++)
2495 {
2496 int length = strlen (reloc_table[i].name);
2497
2498 if (strncasecmp (reloc_table[i].name, *str, length) == 0
2499 && (*str)[length] == ':')
2500 {
2501 *str += (length + 1);
2502 return &reloc_table[i];
2503 }
2504 }
2505
2506 return NULL;
2507}
2508
2509/* Mode argument to parse_shift and parser_shifter_operand. */
2510enum parse_shift_mode
2511{
2512 SHIFTED_ARITH_IMM, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2513 "#imm{,lsl #n}" */
2514 SHIFTED_LOGIC_IMM, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2515 "#imm" */
2516 SHIFTED_LSL, /* bare "lsl #n" */
2517 SHIFTED_LSL_MSL, /* "lsl|msl #n" */
2518 SHIFTED_REG_OFFSET /* [su]xtw|sxtx {#n} or lsl #n */
2519};
2520
2521/* Parse a <shift> operator on an AArch64 data processing instruction.
2522 Return TRUE on success; otherwise return FALSE. */
2523static bfd_boolean
2524parse_shift (char **str, aarch64_opnd_info *operand, enum parse_shift_mode mode)
2525{
2526 const struct aarch64_name_value_pair *shift_op;
2527 enum aarch64_modifier_kind kind;
2528 expressionS exp;
2529 int exp_has_prefix;
2530 char *s = *str;
2531 char *p = s;
2532
2533 for (p = *str; ISALPHA (*p); p++)
2534 ;
2535
2536 if (p == *str)
2537 {
2538 set_syntax_error (_("shift expression expected"));
2539 return FALSE;
2540 }
2541
2542 shift_op = hash_find_n (aarch64_shift_hsh, *str, p - *str);
2543
2544 if (shift_op == NULL)
2545 {
2546 set_syntax_error (_("shift operator expected"));
2547 return FALSE;
2548 }
2549
2550 kind = aarch64_get_operand_modifier (shift_op);
2551
2552 if (kind == AARCH64_MOD_MSL && mode != SHIFTED_LSL_MSL)
2553 {
2554 set_syntax_error (_("invalid use of 'MSL'"));
2555 return FALSE;
2556 }
2557
2558 switch (mode)
2559 {
2560 case SHIFTED_LOGIC_IMM:
2561 if (aarch64_extend_operator_p (kind) == TRUE)
2562 {
2563 set_syntax_error (_("extending shift is not permitted"));
2564 return FALSE;
2565 }
2566 break;
2567
2568 case SHIFTED_ARITH_IMM:
2569 if (kind == AARCH64_MOD_ROR)
2570 {
2571 set_syntax_error (_("'ROR' shift is not permitted"));
2572 return FALSE;
2573 }
2574 break;
2575
2576 case SHIFTED_LSL:
2577 if (kind != AARCH64_MOD_LSL)
2578 {
2579 set_syntax_error (_("only 'LSL' shift is permitted"));
2580 return FALSE;
2581 }
2582 break;
2583
2584 case SHIFTED_REG_OFFSET:
2585 if (kind != AARCH64_MOD_UXTW && kind != AARCH64_MOD_LSL
2586 && kind != AARCH64_MOD_SXTW && kind != AARCH64_MOD_SXTX)
2587 {
2588 set_fatal_syntax_error
2589 (_("invalid shift for the register offset addressing mode"));
2590 return FALSE;
2591 }
2592 break;
2593
2594 case SHIFTED_LSL_MSL:
2595 if (kind != AARCH64_MOD_LSL && kind != AARCH64_MOD_MSL)
2596 {
2597 set_syntax_error (_("invalid shift operator"));
2598 return FALSE;
2599 }
2600 break;
2601
2602 default:
2603 abort ();
2604 }
2605
2606 /* Whitespace can appear here if the next thing is a bare digit. */
2607 skip_whitespace (p);
2608
2609 /* Parse shift amount. */
2610 exp_has_prefix = 0;
2611 if (mode == SHIFTED_REG_OFFSET && *p == ']')
2612 exp.X_op = O_absent;
2613 else
2614 {
2615 if (is_immediate_prefix (*p))
2616 {
2617 p++;
2618 exp_has_prefix = 1;
2619 }
2620 my_get_expression (&exp, &p, GE_NO_PREFIX, 0);
2621 }
2622 if (exp.X_op == O_absent)
2623 {
2624 if (aarch64_extend_operator_p (kind) == FALSE || exp_has_prefix)
2625 {
2626 set_syntax_error (_("missing shift amount"));
2627 return FALSE;
2628 }
2629 operand->shifter.amount = 0;
2630 }
2631 else if (exp.X_op != O_constant)
2632 {
2633 set_syntax_error (_("constant shift amount required"));
2634 return FALSE;
2635 }
2636 else if (exp.X_add_number < 0 || exp.X_add_number > 63)
2637 {
2638 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2639 return FALSE;
2640 }
2641 else
2642 {
2643 operand->shifter.amount = exp.X_add_number;
2644 operand->shifter.amount_present = 1;
2645 }
2646
2647 operand->shifter.operator_present = 1;
2648 operand->shifter.kind = kind;
2649
2650 *str = p;
2651 return TRUE;
2652}
2653
2654/* Parse a <shifter_operand> for a data processing instruction:
2655
2656 #<immediate>
2657 #<immediate>, LSL #imm
2658
2659 Validation of immediate operands is deferred to md_apply_fix.
2660
2661 Return TRUE on success; otherwise return FALSE. */
2662
2663static bfd_boolean
2664parse_shifter_operand_imm (char **str, aarch64_opnd_info *operand,
2665 enum parse_shift_mode mode)
2666{
2667 char *p;
2668
2669 if (mode != SHIFTED_ARITH_IMM && mode != SHIFTED_LOGIC_IMM)
2670 return FALSE;
2671
2672 p = *str;
2673
2674 /* Accept an immediate expression. */
2675 if (! my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX, 1))
2676 return FALSE;
2677
2678 /* Accept optional LSL for arithmetic immediate values. */
2679 if (mode == SHIFTED_ARITH_IMM && skip_past_comma (&p))
2680 if (! parse_shift (&p, operand, SHIFTED_LSL))
2681 return FALSE;
2682
2683 /* Not accept any shifter for logical immediate values. */
2684 if (mode == SHIFTED_LOGIC_IMM && skip_past_comma (&p)
2685 && parse_shift (&p, operand, mode))
2686 {
2687 set_syntax_error (_("unexpected shift operator"));
2688 return FALSE;
2689 }
2690
2691 *str = p;
2692 return TRUE;
2693}
2694
2695/* Parse a <shifter_operand> for a data processing instruction:
2696
2697 <Rm>
2698 <Rm>, <shift>
2699 #<immediate>
2700 #<immediate>, LSL #imm
2701
2702 where <shift> is handled by parse_shift above, and the last two
2703 cases are handled by the function above.
2704
2705 Validation of immediate operands is deferred to md_apply_fix.
2706
2707 Return TRUE on success; otherwise return FALSE. */
2708
2709static bfd_boolean
2710parse_shifter_operand (char **str, aarch64_opnd_info *operand,
2711 enum parse_shift_mode mode)
2712{
2713 int reg;
2714 int isreg32, isregzero;
2715 enum aarch64_operand_class opd_class
2716 = aarch64_get_operand_class (operand->type);
2717
2718 if ((reg =
2719 aarch64_reg_parse_32_64 (str, 0, 0, &isreg32, &isregzero)) != PARSE_FAIL)
2720 {
2721 if (opd_class == AARCH64_OPND_CLASS_IMMEDIATE)
2722 {
2723 set_syntax_error (_("unexpected register in the immediate operand"));
2724 return FALSE;
2725 }
2726
2727 if (!isregzero && reg == REG_SP)
2728 {
2729 set_syntax_error (BAD_SP);
2730 return FALSE;
2731 }
2732
2733 operand->reg.regno = reg;
2734 operand->qualifier = isreg32 ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X;
2735
2736 /* Accept optional shift operation on register. */
2737 if (! skip_past_comma (str))
2738 return TRUE;
2739
2740 if (! parse_shift (str, operand, mode))
2741 return FALSE;
2742
2743 return TRUE;
2744 }
2745 else if (opd_class == AARCH64_OPND_CLASS_MODIFIED_REG)
2746 {
2747 set_syntax_error
2748 (_("integer register expected in the extended/shifted operand "
2749 "register"));
2750 return FALSE;
2751 }
2752
2753 /* We have a shifted immediate variable. */
2754 return parse_shifter_operand_imm (str, operand, mode);
2755}
2756
2757/* Return TRUE on success; return FALSE otherwise. */
2758
2759static bfd_boolean
2760parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
2761 enum parse_shift_mode mode)
2762{
2763 char *p = *str;
2764
2765 /* Determine if we have the sequence of characters #: or just :
2766 coming next. If we do, then we check for a :rello: relocation
2767 modifier. If we don't, punt the whole lot to
2768 parse_shifter_operand. */
2769
2770 if ((p[0] == '#' && p[1] == ':') || p[0] == ':')
2771 {
2772 struct reloc_table_entry *entry;
2773
2774 if (p[0] == '#')
2775 p += 2;
2776 else
2777 p++;
2778 *str = p;
2779
2780 /* Try to parse a relocation. Anything else is an error. */
2781 if (!(entry = find_reloc_table_entry (str)))
2782 {
2783 set_syntax_error (_("unknown relocation modifier"));
2784 return FALSE;
2785 }
2786
2787 if (entry->add_type == 0)
2788 {
2789 set_syntax_error
2790 (_("this relocation modifier is not allowed on this instruction"));
2791 return FALSE;
2792 }
2793
2794 /* Save str before we decompose it. */
2795 p = *str;
2796
2797 /* Next, we parse the expression. */
2798 if (! my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX, 1))
2799 return FALSE;
2800
2801 /* Record the relocation type (use the ADD variant here). */
2802 inst.reloc.type = entry->add_type;
2803 inst.reloc.pc_rel = entry->pc_rel;
2804
2805 /* If str is empty, we've reached the end, stop here. */
2806 if (**str == '\0')
2807 return TRUE;
2808
2809 /* Otherwise, we have a shifted reloc modifier, so rewind to
2810 recover the variable name and continue parsing for the shifter. */
2811 *str = p;
2812 return parse_shifter_operand_imm (str, operand, mode);
2813 }
2814
2815 return parse_shifter_operand (str, operand, mode);
2816}
2817
2818/* Parse all forms of an address expression. Information is written
2819 to *OPERAND and/or inst.reloc.
2820
2821 The A64 instruction set has the following addressing modes:
2822
2823 Offset
2824 [base] // in SIMD ld/st structure
2825 [base{,#0}] // in ld/st exclusive
2826 [base{,#imm}]
2827 [base,Xm{,LSL #imm}]
2828 [base,Xm,SXTX {#imm}]
2829 [base,Wm,(S|U)XTW {#imm}]
2830 Pre-indexed
2831 [base,#imm]!
2832 Post-indexed
2833 [base],#imm
2834 [base],Xm // in SIMD ld/st structure
2835 PC-relative (literal)
2836 label
2837 =immediate
2838
2839 (As a convenience, the notation "=immediate" is permitted in conjunction
2840 with the pc-relative literal load instructions to automatically place an
2841 immediate value or symbolic address in a nearby literal pool and generate
2842 a hidden label which references it.)
2843
2844 Upon a successful parsing, the address structure in *OPERAND will be
2845 filled in the following way:
2846
2847 .base_regno = <base>
2848 .offset.is_reg // 1 if the offset is a register
2849 .offset.imm = <imm>
2850 .offset.regno = <Rm>
2851
2852 For different addressing modes defined in the A64 ISA:
2853
2854 Offset
2855 .pcrel=0; .preind=1; .postind=0; .writeback=0
2856 Pre-indexed
2857 .pcrel=0; .preind=1; .postind=0; .writeback=1
2858 Post-indexed
2859 .pcrel=0; .preind=0; .postind=1; .writeback=1
2860 PC-relative (literal)
2861 .pcrel=1; .preind=1; .postind=0; .writeback=0
2862
2863 The shift/extension information, if any, will be stored in .shifter.
2864
2865 It is the caller's responsibility to check for addressing modes not
2866 supported by the instruction, and to set inst.reloc.type. */
2867
2868static bfd_boolean
2869parse_address_main (char **str, aarch64_opnd_info *operand, int reloc,
2870 int accept_reg_post_index)
2871{
2872 char *p = *str;
2873 int reg;
2874 int isreg32, isregzero;
2875 expressionS *exp = &inst.reloc.exp;
2876
2877 if (! skip_past_char (&p, '['))
2878 {
2879 /* =immediate or label. */
2880 operand->addr.pcrel = 1;
2881 operand->addr.preind = 1;
2882
f41aef5f
RE		 2883 /* #:<reloc_op>:<symbol> */
2884 skip_past_char (&p, '#');
2885 if (reloc && skip_past_char (&p, ':'))
2886 {
2887 struct reloc_table_entry *entry;
2888
2889 /* Try to parse a relocation modifier. Anything else is
2890 an error. */
2891 entry = find_reloc_table_entry (&p);
2892 if (! entry)
2893 {
2894 set_syntax_error (_("unknown relocation modifier"));
2895 return FALSE;
2896 }
2897
2898 if (entry->ldst_type == 0)
2899 {
2900 set_syntax_error
2901 (_("this relocation modifier is not allowed on this "
2902 "instruction"));
2903 return FALSE;
2904 }
2905
2906 /* #:<reloc_op>: */
2907 if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
2908 {
2909 set_syntax_error (_("invalid relocation expression"));
2910 return FALSE;
2911 }
a06ea964 2912
f41aef5f
RE		 2913 /* #:<reloc_op>:<expr> */
2914 /* Record the load/store relocation type. */
2915 inst.reloc.type = entry->ldst_type;
2916 inst.reloc.pc_rel = entry->pc_rel;
2917 }
2918 else
a06ea964 2919 {
f41aef5f
RE		 2920
2921 if (skip_past_char (&p, '='))
2922 /* =immediate; need to generate the literal in the literal pool. */
2923 inst.gen_lit_pool = 1;
2924
2925 if (!my_get_expression (exp, &p, GE_NO_PREFIX, 1))
2926 {
2927 set_syntax_error (_("invalid address"));
2928 return FALSE;
2929 }
a06ea964
NC		 2930 }
2931
2932 *str = p;
2933 return TRUE;
2934 }
2935
2936 /* [ */
2937
2938 /* Accept SP and reject ZR */
2939 reg = aarch64_reg_parse_32_64 (&p, 0, 1, &isreg32, &isregzero);
2940 if (reg == PARSE_FAIL || isreg32)
2941 {
2942 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64)));
2943 return FALSE;
2944 }
2945 operand->addr.base_regno = reg;
2946
2947 /* [Xn */
2948 if (skip_past_comma (&p))
2949 {
2950 /* [Xn, */
2951 operand->addr.preind = 1;
2952
2953 /* Reject SP and accept ZR */
2954 reg = aarch64_reg_parse_32_64 (&p, 1, 0, &isreg32, &isregzero);
2955 if (reg != PARSE_FAIL)
2956 {
2957 /* [Xn,Rm */
2958 operand->addr.offset.regno = reg;
2959 operand->addr.offset.is_reg = 1;
2960 /* Shifted index. */
2961 if (skip_past_comma (&p))
2962 {
2963 /* [Xn,Rm, */
2964 if (! parse_shift (&p, operand, SHIFTED_REG_OFFSET))
2965 /* Use the diagnostics set in parse_shift, so not set new
2966 error message here. */
2967 return FALSE;
2968 }
2969 /* We only accept:
2970 [base,Xm{,LSL #imm}]
2971 [base,Xm,SXTX {#imm}]
2972 [base,Wm,(S|U)XTW {#imm}] */
2973 if (operand->shifter.kind == AARCH64_MOD_NONE
2974 || operand->shifter.kind == AARCH64_MOD_LSL
2975 || operand->shifter.kind == AARCH64_MOD_SXTX)
2976 {
2977 if (isreg32)
2978 {
2979 set_syntax_error (_("invalid use of 32-bit register offset"));
2980 return FALSE;
2981 }
2982 }
2983 else if (!isreg32)
2984 {
2985 set_syntax_error (_("invalid use of 64-bit register offset"));
2986 return FALSE;
2987 }
2988 }
2989 else
2990 {
2991 /* [Xn,#:<reloc_op>:<symbol> */
2992 skip_past_char (&p, '#');
2993 if (reloc && skip_past_char (&p, ':'))
2994 {
2995 struct reloc_table_entry *entry;
2996
2997 /* Try to parse a relocation modifier. Anything else is
2998 an error. */
2999 if (!(entry = find_reloc_table_entry (&p)))
3000 {
3001 set_syntax_error (_("unknown relocation modifier"));
3002 return FALSE;
3003 }
3004
3005 if (entry->ldst_type == 0)
3006 {
3007 set_syntax_error
3008 (_("this relocation modifier is not allowed on this "
3009 "instruction"));
3010 return FALSE;
3011 }
3012
3013 /* [Xn,#:<reloc_op>: */
3014 /* We now have the group relocation table entry corresponding to
3015 the name in the assembler source. Next, we parse the
3016 expression. */
3017 if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
3018 {
3019 set_syntax_error (_("invalid relocation expression"));
3020 return FALSE;
3021 }
3022
3023 /* [Xn,#:<reloc_op>:<expr> */
3024 /* Record the load/store relocation type. */
3025 inst.reloc.type = entry->ldst_type;
3026 inst.reloc.pc_rel = entry->pc_rel;
3027 }
3028 else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
3029 {
3030 set_syntax_error (_("invalid expression in the address"));
3031 return FALSE;
3032 }
3033 /* [Xn,<expr> */
3034 }
3035 }
3036
3037 if (! skip_past_char (&p, ']'))
3038 {
3039 set_syntax_error (_("']' expected"));
3040 return FALSE;
3041 }
3042
3043 if (skip_past_char (&p, '!'))
3044 {
3045 if (operand->addr.preind && operand->addr.offset.is_reg)
3046 {
3047 set_syntax_error (_("register offset not allowed in pre-indexed "
3048 "addressing mode"));
3049 return FALSE;
3050 }
3051 /* [Xn]! */
3052 operand->addr.writeback = 1;
3053 }
3054 else if (skip_past_comma (&p))
3055 {
3056 /* [Xn], */
3057 operand->addr.postind = 1;
3058 operand->addr.writeback = 1;
3059
3060 if (operand->addr.preind)
3061 {
3062 set_syntax_error (_("cannot combine pre- and post-indexing"));
3063 return FALSE;
3064 }
3065
3066 if (accept_reg_post_index
3067 && (reg = aarch64_reg_parse_32_64 (&p, 1, 1, &isreg32,
3068 &isregzero)) != PARSE_FAIL)
3069 {
3070 /* [Xn],Xm */
3071 if (isreg32)
3072 {
3073 set_syntax_error (_("invalid 32-bit register offset"));
3074 return FALSE;
3075 }
3076 operand->addr.offset.regno = reg;
3077 operand->addr.offset.is_reg = 1;
3078 }
3079 else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
3080 {
3081 /* [Xn],#expr */
3082 set_syntax_error (_("invalid expression in the address"));
3083 return FALSE;
3084 }
3085 }
3086
3087 /* If at this point neither .preind nor .postind is set, we have a
3088 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3089 if (operand->addr.preind == 0 && operand->addr.postind == 0)
3090 {
3091 if (operand->addr.writeback)
3092 {
3093 /* Reject [Rn]! */
3094 set_syntax_error (_("missing offset in the pre-indexed address"));
3095 return FALSE;
3096 }
3097 operand->addr.preind = 1;
3098 inst.reloc.exp.X_op = O_constant;
3099 inst.reloc.exp.X_add_number = 0;
3100 }
3101
3102 *str = p;
3103 return TRUE;
3104}
3105
3106/* Return TRUE on success; otherwise return FALSE. */
3107static bfd_boolean
3108parse_address (char **str, aarch64_opnd_info *operand,
3109 int accept_reg_post_index)
3110{
3111 return parse_address_main (str, operand, 0, accept_reg_post_index);
3112}
3113
3114/* Return TRUE on success; otherwise return FALSE. */
3115static bfd_boolean
3116parse_address_reloc (char **str, aarch64_opnd_info *operand)
3117{
3118 return parse_address_main (str, operand, 1, 0);
3119}
3120
3121/* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3122 Return TRUE on success; otherwise return FALSE. */
3123static bfd_boolean
3124parse_half (char **str, int *internal_fixup_p)
3125{
3126 char *p, *saved;
3127 int dummy;
3128
3129 p = *str;
3130 skip_past_char (&p, '#');
3131
3132 gas_assert (internal_fixup_p);
3133 *internal_fixup_p = 0;
3134
3135 if (*p == ':')
3136 {
3137 struct reloc_table_entry *entry;
3138
3139 /* Try to parse a relocation. Anything else is an error. */
3140 ++p;
3141 if (!(entry = find_reloc_table_entry (&p)))
3142 {
3143 set_syntax_error (_("unknown relocation modifier"));
3144 return FALSE;
3145 }
3146
3147 if (entry->movw_type == 0)
3148 {
3149 set_syntax_error
3150 (_("this relocation modifier is not allowed on this instruction"));
3151 return FALSE;
3152 }
3153
3154 inst.reloc.type = entry->movw_type;
3155 }
3156 else
3157 *internal_fixup_p = 1;
3158
3159 /* Avoid parsing a register as a general symbol. */
3160 saved = p;
3161 if (aarch64_reg_parse_32_64 (&p, 0, 0, &dummy, &dummy) != PARSE_FAIL)
3162 return FALSE;
3163 p = saved;
3164
3165 if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
3166 return FALSE;
3167
3168 *str = p;
3169 return TRUE;
3170}
3171
3172/* Parse an operand for an ADRP instruction:
3173 ADRP <Xd>, <label>
3174 Return TRUE on success; otherwise return FALSE. */
3175
3176static bfd_boolean
3177parse_adrp (char **str)
3178{
3179 char *p;
3180
3181 p = *str;
3182 if (*p == ':')
3183 {
3184 struct reloc_table_entry *entry;
3185
3186 /* Try to parse a relocation. Anything else is an error. */
3187 ++p;
3188 if (!(entry = find_reloc_table_entry (&p)))
3189 {
3190 set_syntax_error (_("unknown relocation modifier"));
3191 return FALSE;
3192 }
3193
3194 if (entry->adrp_type == 0)
3195 {
3196 set_syntax_error
3197 (_("this relocation modifier is not allowed on this instruction"));
3198 return FALSE;
3199 }
3200
3201 inst.reloc.type = entry->adrp_type;
3202 }
3203 else
3204 inst.reloc.type = BFD_RELOC_AARCH64_ADR_HI21_PCREL;
3205
3206 inst.reloc.pc_rel = 1;
3207
3208 if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
3209 return FALSE;
3210
3211 *str = p;
3212 return TRUE;
3213}
3214
3215/* Miscellaneous. */
3216
3217/* Parse an option for a preload instruction. Returns the encoding for the
3218 option, or PARSE_FAIL. */
3219
3220static int
3221parse_pldop (char **str)
3222{
3223 char *p, *q;
3224 const struct aarch64_name_value_pair *o;
3225
3226 p = q = *str;
3227 while (ISALNUM (*q))
3228 q++;
3229
3230 o = hash_find_n (aarch64_pldop_hsh, p, q - p);
3231 if (!o)
3232 return PARSE_FAIL;
3233
3234 *str = q;
3235 return o->value;
3236}
3237
3238/* Parse an option for a barrier instruction. Returns the encoding for the
3239 option, or PARSE_FAIL. */
3240
3241static int
3242parse_barrier (char **str)
3243{
3244 char *p, *q;
3245 const asm_barrier_opt *o;
3246
3247 p = q = *str;
3248 while (ISALPHA (*q))
3249 q++;
3250
3251 o = hash_find_n (aarch64_barrier_opt_hsh, p, q - p);
3252 if (!o)
3253 return PARSE_FAIL;
3254
3255 *str = q;
3256 return o->value;
3257}
3258
3259/* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3260 Returns the encoding for the option, or PARSE_FAIL.
3261
3262 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3263 implementation defined system register name S3_<op1>_<Cn>_<Cm>_<op2>. */
3264
3265static int
3266parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
3267{
3268 char *p, *q;
3269 char buf[32];
3270 const struct aarch64_name_value_pair *o;
3271 int value;
3272
3273 p = buf;
3274 for (q = *str; ISALNUM (*q) || *q == '_'; q++)
3275 if (p < buf + 31)
3276 *p++ = TOLOWER (*q);
3277 *p = '\0';
3278 /* Assert that BUF be large enough. */
3279 gas_assert (p - buf == q - *str);
3280
3281 o = hash_find (sys_regs, buf);
3282 if (!o)
3283 {
3284 if (!imple_defined_p)
3285 return PARSE_FAIL;
3286 else
3287 {
3288 /* Parse S3_<op1>_<Cn>_<Cm>_<op2>, the implementation defined
3289 registers. */
3290 unsigned int op0, op1, cn, cm, op2;
3291 if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2) != 5)
3292 return PARSE_FAIL;
aeebdd9b
YZ		 3293 /* The architecture specifies the encoding space for implementation
3294 defined registers as:
a06ea964 3295 op0 op1 CRn CRm op2
aeebdd9b
YZ		 3296 11 xxx 1x11 xxxx xxx
3297 For convenience GAS accepts a wider encoding space, as follows:
3298 op0 op1 CRn CRm op2
3299 11 xxx xxxx xxxx xxx */
3300 if (op0 != 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
a06ea964
NC		 3301 return PARSE_FAIL;
3302 value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;
3303 }
3304 }
3305 else
3306 value = o->value;
3307
3308 *str = q;
3309 return value;
3310}
3311
3312/* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3313 for the option, or NULL. */
3314
3315static const aarch64_sys_ins_reg *
3316parse_sys_ins_reg (char **str, struct hash_control *sys_ins_regs)
3317{
3318 char *p, *q;
3319 char buf[32];
3320 const aarch64_sys_ins_reg *o;
3321
3322 p = buf;
3323 for (q = *str; ISALNUM (*q) || *q == '_'; q++)
3324 if (p < buf + 31)
3325 *p++ = TOLOWER (*q);
3326 *p = '\0';
3327
3328 o = hash_find (sys_ins_regs, buf);
3329 if (!o)
3330 return NULL;
3331
3332 *str = q;
3333 return o;
3334}
3335\f
3336#define po_char_or_fail(chr) do { \
3337 if (! skip_past_char (&str, chr)) \
3338 goto failure; \
3339} while (0)
3340
3341#define po_reg_or_fail(regtype) do { \
3342 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3343 if (val == PARSE_FAIL) \
3344 { \
3345 set_default_error (); \
3346 goto failure; \
3347 } \
3348 } while (0)
3349
3350#define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3351 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3352 &isreg32, &isregzero); \
3353 if (val == PARSE_FAIL) \
3354 { \
3355 set_default_error (); \
3356 goto failure; \
3357 } \
3358 info->reg.regno = val; \
3359 if (isreg32) \
3360 info->qualifier = AARCH64_OPND_QLF_W; \
3361 else \
3362 info->qualifier = AARCH64_OPND_QLF_X; \
3363 } while (0)
3364
3365#define po_imm_nc_or_fail() do { \
3366 if (! parse_constant_immediate (&str, &val)) \
3367 goto failure; \
3368 } while (0)
3369
3370#define po_imm_or_fail(min, max) do { \
3371 if (! parse_constant_immediate (&str, &val)) \
3372 goto failure; \
3373 if (val < min || val > max) \
3374 { \
3375 set_fatal_syntax_error (_("immediate value out of range "\
3376#min " to "#max)); \
3377 goto failure; \
3378 } \
3379 } while (0)
3380
3381#define po_misc_or_fail(expr) do { \
3382 if (!expr) \
3383 goto failure; \
3384 } while (0)
3385\f
3386/* encode the 12-bit imm field of Add/sub immediate */
3387static inline uint32_t
3388encode_addsub_imm (uint32_t imm)
3389{
3390 return imm << 10;
3391}
3392
3393/* encode the shift amount field of Add/sub immediate */
3394static inline uint32_t
3395encode_addsub_imm_shift_amount (uint32_t cnt)
3396{
3397 return cnt << 22;
3398}
3399
3400
3401/* encode the imm field of Adr instruction */
3402static inline uint32_t
3403encode_adr_imm (uint32_t imm)
3404{
3405 return (((imm & 0x3) << 29) /* [1:0] -> [30:29] */
3406 | ((imm & (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3407}
3408
3409/* encode the immediate field of Move wide immediate */
3410static inline uint32_t
3411encode_movw_imm (uint32_t imm)
3412{
3413 return imm << 5;
3414}
3415
3416/* encode the 26-bit offset of unconditional branch */
3417static inline uint32_t
3418encode_branch_ofs_26 (uint32_t ofs)
3419{
3420 return ofs & ((1 << 26) - 1);
3421}
3422
3423/* encode the 19-bit offset of conditional branch and compare & branch */
3424static inline uint32_t
3425encode_cond_branch_ofs_19 (uint32_t ofs)
3426{
3427 return (ofs & ((1 << 19) - 1)) << 5;
3428}
3429
3430/* encode the 19-bit offset of ld literal */
3431static inline uint32_t
3432encode_ld_lit_ofs_19 (uint32_t ofs)
3433{
3434 return (ofs & ((1 << 19) - 1)) << 5;
3435}
3436
3437/* Encode the 14-bit offset of test & branch. */
3438static inline uint32_t
3439encode_tst_branch_ofs_14 (uint32_t ofs)
3440{
3441 return (ofs & ((1 << 14) - 1)) << 5;
3442}
3443
3444/* Encode the 16-bit imm field of svc/hvc/smc. */
3445static inline uint32_t
3446encode_svc_imm (uint32_t imm)
3447{
3448 return imm << 5;
3449}
3450
3451/* Reencode add(s) to sub(s), or sub(s) to add(s). */
3452static inline uint32_t
3453reencode_addsub_switch_add_sub (uint32_t opcode)
3454{
3455 return opcode ^ (1 << 30);
3456}
3457
3458static inline uint32_t
3459reencode_movzn_to_movz (uint32_t opcode)
3460{
3461 return opcode | (1 << 30);
3462}
3463
3464static inline uint32_t
3465reencode_movzn_to_movn (uint32_t opcode)
3466{
3467 return opcode & ~(1 << 30);
3468}
3469
3470/* Overall per-instruction processing. */
3471
3472/* We need to be able to fix up arbitrary expressions in some statements.
3473 This is so that we can handle symbols that are an arbitrary distance from
3474 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3475 which returns part of an address in a form which will be valid for
3476 a data instruction. We do this by pushing the expression into a symbol
3477 in the expr_section, and creating a fix for that. */
3478
3479static fixS *
3480fix_new_aarch64 (fragS * frag,
3481 int where,
3482 short int size, expressionS * exp, int pc_rel, int reloc)
3483{
3484 fixS *new_fix;
3485
3486 switch (exp->X_op)
3487 {
3488 case O_constant:
3489 case O_symbol:
3490 case O_add:
3491 case O_subtract:
3492 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
3493 break;
3494
3495 default:
3496 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
3497 pc_rel, reloc);
3498 break;
3499 }
3500 return new_fix;
3501}
3502\f
3503/* Diagnostics on operands errors. */
3504
3505/* By default, output one-line error message only.
3506 Enable the verbose error message by -merror-verbose. */
3507static int verbose_error_p = 0;
3508
3509#ifdef DEBUG_AARCH64
3510/* N.B. this is only for the purpose of debugging. */
3511const char* operand_mismatch_kind_names[] =
3512{
3513 "AARCH64_OPDE_NIL",
3514 "AARCH64_OPDE_RECOVERABLE",
3515 "AARCH64_OPDE_SYNTAX_ERROR",
3516 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3517 "AARCH64_OPDE_INVALID_VARIANT",
3518 "AARCH64_OPDE_OUT_OF_RANGE",
3519 "AARCH64_OPDE_UNALIGNED",
3520 "AARCH64_OPDE_REG_LIST",
3521 "AARCH64_OPDE_OTHER_ERROR",
3522};
3523#endif /* DEBUG_AARCH64 */
3524
3525/* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3526
3527 When multiple errors of different kinds are found in the same assembly
3528 line, only the error of the highest severity will be picked up for
3529 issuing the diagnostics. */
3530
3531static inline bfd_boolean
3532operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs,
3533 enum aarch64_operand_error_kind rhs)
3534{
3535 gas_assert (AARCH64_OPDE_RECOVERABLE > AARCH64_OPDE_NIL);
3536 gas_assert (AARCH64_OPDE_SYNTAX_ERROR > AARCH64_OPDE_RECOVERABLE);
3537 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR > AARCH64_OPDE_SYNTAX_ERROR);
3538 gas_assert (AARCH64_OPDE_INVALID_VARIANT > AARCH64_OPDE_FATAL_SYNTAX_ERROR);
3539 gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_INVALID_VARIANT);
3540 gas_assert (AARCH64_OPDE_UNALIGNED > AARCH64_OPDE_OUT_OF_RANGE);
3541 gas_assert (AARCH64_OPDE_REG_LIST > AARCH64_OPDE_UNALIGNED);
3542 gas_assert (AARCH64_OPDE_OTHER_ERROR > AARCH64_OPDE_REG_LIST);
3543 return lhs > rhs;
3544}
3545
3546/* Helper routine to get the mnemonic name from the assembly instruction
3547 line; should only be called for the diagnosis purpose, as there is
3548 string copy operation involved, which may affect the runtime
3549 performance if used in elsewhere. */
3550
3551static const char*
3552get_mnemonic_name (const char *str)
3553{
3554 static char mnemonic[32];
3555 char *ptr;
3556
3557 /* Get the first 15 bytes and assume that the full name is included. */
3558 strncpy (mnemonic, str, 31);
3559 mnemonic[31] = '\0';
3560
3561 /* Scan up to the end of the mnemonic, which must end in white space,
3562 '.', or end of string. */
3563 for (ptr = mnemonic; is_part_of_name(*ptr); ++ptr)
3564 ;
3565
3566 *ptr = '\0';
3567
3568 /* Append '...' to the truncated long name. */
3569 if (ptr - mnemonic == 31)
3570 mnemonic[28] = mnemonic[29] = mnemonic[30] = '.';
3571
3572 return mnemonic;
3573}
3574
3575static void
3576reset_aarch64_instruction (aarch64_instruction *instruction)
3577{
3578 memset (instruction, '\0', sizeof (aarch64_instruction));
3579 instruction->reloc.type = BFD_RELOC_UNUSED;
3580}
3581
3582/* Data strutures storing one user error in the assembly code related to
3583 operands. */
3584
3585struct operand_error_record
3586{
3587 const aarch64_opcode *opcode;
3588 aarch64_operand_error detail;
3589 struct operand_error_record *next;
3590};
3591
3592typedef struct operand_error_record operand_error_record;
3593
3594struct operand_errors
3595{
3596 operand_error_record *head;
3597 operand_error_record *tail;
3598};
3599
3600typedef struct operand_errors operand_errors;
3601
3602/* Top-level data structure reporting user errors for the current line of
3603 the assembly code.
3604 The way md_assemble works is that all opcodes sharing the same mnemonic
3605 name are iterated to find a match to the assembly line. In this data
3606 structure, each of the such opcodes will have one operand_error_record
3607 allocated and inserted. In other words, excessive errors related with
3608 a single opcode are disregarded. */
3609operand_errors operand_error_report;
3610
3611/* Free record nodes. */
3612static operand_error_record *free_opnd_error_record_nodes = NULL;
3613
3614/* Initialize the data structure that stores the operand mismatch
3615 information on assembling one line of the assembly code. */
3616static void
3617init_operand_error_report (void)
3618{
3619 if (operand_error_report.head != NULL)
3620 {
3621 gas_assert (operand_error_report.tail != NULL);
3622 operand_error_report.tail->next = free_opnd_error_record_nodes;
3623 free_opnd_error_record_nodes = operand_error_report.head;
3624 operand_error_report.head = NULL;
3625 operand_error_report.tail = NULL;
3626 return;
3627 }
3628 gas_assert (operand_error_report.tail == NULL);
3629}
3630
3631/* Return TRUE if some operand error has been recorded during the
3632 parsing of the current assembly line using the opcode *OPCODE;
3633 otherwise return FALSE. */
3634static inline bfd_boolean
3635opcode_has_operand_error_p (const aarch64_opcode *opcode)
3636{
3637 operand_error_record *record = operand_error_report.head;
3638 return record && record->opcode == opcode;
3639}
3640
3641/* Add the error record *NEW_RECORD to operand_error_report. The record's
3642 OPCODE field is initialized with OPCODE.
3643 N.B. only one record for each opcode, i.e. the maximum of one error is
3644 recorded for each instruction template. */
3645
3646static void
3647add_operand_error_record (const operand_error_record* new_record)
3648{
3649 const aarch64_opcode *opcode = new_record->opcode;
3650 operand_error_record* record = operand_error_report.head;
3651
3652 /* The record may have been created for this opcode. If not, we need
3653 to prepare one. */
3654 if (! opcode_has_operand_error_p (opcode))
3655 {
3656 /* Get one empty record. */
3657 if (free_opnd_error_record_nodes == NULL)
3658 {
3659 record = xmalloc (sizeof (operand_error_record));
3660 if (record == NULL)
3661 abort ();
3662 }
3663 else
3664 {
3665 record = free_opnd_error_record_nodes;
3666 free_opnd_error_record_nodes = record->next;
3667 }
3668 record->opcode = opcode;
3669 /* Insert at the head. */
3670 record->next = operand_error_report.head;
3671 operand_error_report.head = record;
3672 if (operand_error_report.tail == NULL)
3673 operand_error_report.tail = record;
3674 }
3675 else if (record->detail.kind != AARCH64_OPDE_NIL
3676 && record->detail.index <= new_record->detail.index
3677 && operand_error_higher_severity_p (record->detail.kind,
3678 new_record->detail.kind))
3679 {
3680 /* In the case of multiple errors found on operands related with a
3681 single opcode, only record the error of the leftmost operand and
3682 only if the error is of higher severity. */
3683 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
3684 " the existing error %s on operand %d",
3685 operand_mismatch_kind_names[new_record->detail.kind],
3686 new_record->detail.index,
3687 operand_mismatch_kind_names[record->detail.kind],
3688 record->detail.index);
3689 return;
3690 }
3691
3692 record->detail = new_record->detail;
3693}
3694
3695static inline void
3696record_operand_error_info (const aarch64_opcode *opcode,
3697 aarch64_operand_error *error_info)
3698{
3699 operand_error_record record;
3700 record.opcode = opcode;
3701 record.detail = *error_info;
3702 add_operand_error_record (&record);
3703}
3704
3705/* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
3706 error message *ERROR, for operand IDX (count from 0). */
3707
3708static void
3709record_operand_error (const aarch64_opcode *opcode, int idx,
3710 enum aarch64_operand_error_kind kind,
3711 const char* error)
3712{
3713 aarch64_operand_error info;
3714 memset(&info, 0, sizeof (info));
3715 info.index = idx;
3716 info.kind = kind;
3717 info.error = error;
3718 record_operand_error_info (opcode, &info);
3719}
3720
3721static void
3722record_operand_error_with_data (const aarch64_opcode *opcode, int idx,
3723 enum aarch64_operand_error_kind kind,
3724 const char* error, const int *extra_data)
3725{
3726 aarch64_operand_error info;
3727 info.index = idx;
3728 info.kind = kind;
3729 info.error = error;
3730 info.data[0] = extra_data[0];
3731 info.data[1] = extra_data[1];
3732 info.data[2] = extra_data[2];
3733 record_operand_error_info (opcode, &info);
3734}
3735
3736static void
3737record_operand_out_of_range_error (const aarch64_opcode *opcode, int idx,
3738 const char* error, int lower_bound,
3739 int upper_bound)
3740{
3741 int data[3] = {lower_bound, upper_bound, 0};
3742 record_operand_error_with_data (opcode, idx, AARCH64_OPDE_OUT_OF_RANGE,
3743 error, data);
3744}
3745
3746/* Remove the operand error record for *OPCODE. */
3747static void ATTRIBUTE_UNUSED
3748remove_operand_error_record (const aarch64_opcode *opcode)
3749{
3750 if (opcode_has_operand_error_p (opcode))
3751 {
3752 operand_error_record* record = operand_error_report.head;
3753 gas_assert (record != NULL && operand_error_report.tail != NULL);
3754 operand_error_report.head = record->next;
3755 record->next = free_opnd_error_record_nodes;
3756 free_opnd_error_record_nodes = record;
3757 if (operand_error_report.head == NULL)
3758 {
3759 gas_assert (operand_error_report.tail == record);
3760 operand_error_report.tail = NULL;
3761 }
3762 }
3763}
3764
3765/* Given the instruction in *INSTR, return the index of the best matched
3766 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
3767
3768 Return -1 if there is no qualifier sequence; return the first match
3769 if there is multiple matches found. */
3770
3771static int
3772find_best_match (const aarch64_inst *instr,
3773 const aarch64_opnd_qualifier_seq_t *qualifiers_list)
3774{
3775 int i, num_opnds, max_num_matched, idx;
3776
3777 num_opnds = aarch64_num_of_operands (instr->opcode);
3778 if (num_opnds == 0)
3779 {
3780 DEBUG_TRACE ("no operand");
3781 return -1;
3782 }
3783
3784 max_num_matched = 0;
3785 idx = -1;
3786
3787 /* For each pattern. */
3788 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
3789 {
3790 int j, num_matched;
3791 const aarch64_opnd_qualifier_t *qualifiers = *qualifiers_list;
3792
3793 /* Most opcodes has much fewer patterns in the list. */
3794 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
3795 {
3796 DEBUG_TRACE_IF (i == 0, "empty list of qualifier sequence");
3797 if (i != 0 && idx == -1)
3798 /* If nothing has been matched, return the 1st sequence. */
3799 idx = 0;
3800 break;
3801 }
3802
3803 for (j = 0, num_matched = 0; j < num_opnds; ++j, ++qualifiers)
3804 if (*qualifiers == instr->operands[j].qualifier)
3805 ++num_matched;
3806
3807 if (num_matched > max_num_matched)
3808 {
3809 max_num_matched = num_matched;
3810 idx = i;
3811 }
3812 }
3813
3814 DEBUG_TRACE ("return with %d", idx);
3815 return idx;
3816}
3817
3818/* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
3819 corresponding operands in *INSTR. */
3820
3821static inline void
3822assign_qualifier_sequence (aarch64_inst *instr,
3823 const aarch64_opnd_qualifier_t *qualifiers)
3824{
3825 int i = 0;
3826 int num_opnds = aarch64_num_of_operands (instr->opcode);
3827 gas_assert (num_opnds);
3828 for (i = 0; i < num_opnds; ++i, ++qualifiers)
3829 instr->operands[i].qualifier = *qualifiers;
3830}
3831
3832/* Print operands for the diagnosis purpose. */
3833
3834static void
3835print_operands (char *buf, const aarch64_opcode *opcode,
3836 const aarch64_opnd_info *opnds)
3837{
3838 int i;
3839
3840 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
3841 {
3842 const size_t size = 128;
3843 char str[size];
3844
3845 /* We regard the opcode operand info more, however we also look into
3846 the inst->operands to support the disassembling of the optional
3847 operand.
3848 The two operand code should be the same in all cases, apart from
3849 when the operand can be optional. */
3850 if (opcode->operands[i] == AARCH64_OPND_NIL
3851 || opnds[i].type == AARCH64_OPND_NIL)
3852 break;
3853
3854 /* Generate the operand string in STR. */
3855 aarch64_print_operand (str, size, 0, opcode, opnds, i, NULL, NULL);
3856
3857 /* Delimiter. */
3858 if (str[0] != '\0')
3859 strcat (buf, i == 0 ? " " : ",");
3860
3861 /* Append the operand string. */
3862 strcat (buf, str);
3863 }
3864}
3865
3866/* Send to stderr a string as information. */
3867
3868static void
3869output_info (const char *format, ...)
3870{
3871 char *file;
3872 unsigned int line;
3873 va_list args;
3874
3875 as_where (&file, &line);
3876 if (file)
3877 {
3878 if (line != 0)
3879 fprintf (stderr, "%s:%u: ", file, line);
3880 else
3881 fprintf (stderr, "%s: ", file);
3882 }
3883 fprintf (stderr, _("Info: "));
3884 va_start (args, format);
3885 vfprintf (stderr, format, args);
3886 va_end (args);
3887 (void) putc ('\n', stderr);
3888}
3889
3890/* Output one operand error record. */
3891
3892static void
3893output_operand_error_record (const operand_error_record *record, char *str)
3894{
3895 int idx = record->detail.index;
3896 const aarch64_opcode *opcode = record->opcode;
3897 enum aarch64_opnd opd_code = (idx != -1 ? opcode->operands[idx]
3898 : AARCH64_OPND_NIL);
3899 const aarch64_operand_error *detail = &record->detail;
3900
3901 switch (detail->kind)
3902 {
3903 case AARCH64_OPDE_NIL:
3904 gas_assert (0);
3905 break;
3906
3907 case AARCH64_OPDE_SYNTAX_ERROR:
3908 case AARCH64_OPDE_RECOVERABLE:
3909 case AARCH64_OPDE_FATAL_SYNTAX_ERROR:
3910 case AARCH64_OPDE_OTHER_ERROR:
3911 gas_assert (idx >= 0);
3912 /* Use the prepared error message if there is, otherwise use the
3913 operand description string to describe the error. */
3914 if (detail->error != NULL)
3915 {
3916 if (detail->index == -1)
3917 as_bad (_("%s -- `%s'"), detail->error, str);
3918 else
3919 as_bad (_("%s at operand %d -- `%s'"),
3920 detail->error, detail->index + 1, str);
3921 }
3922 else
3923 as_bad (_("operand %d should be %s -- `%s'"), idx + 1,
3924 aarch64_get_operand_desc (opd_code), str);
3925 break;
3926
3927 case AARCH64_OPDE_INVALID_VARIANT:
3928 as_bad (_("operand mismatch -- `%s'"), str);
3929 if (verbose_error_p)
3930 {
3931 /* We will try to correct the erroneous instruction and also provide
3932 more information e.g. all other valid variants.
3933
3934 The string representation of the corrected instruction and other
3935 valid variants are generated by
3936
3937 1) obtaining the intermediate representation of the erroneous
3938 instruction;
3939 2) manipulating the IR, e.g. replacing the operand qualifier;
3940 3) printing out the instruction by calling the printer functions
3941 shared with the disassembler.
3942
3943 The limitation of this method is that the exact input assembly
3944 line cannot be accurately reproduced in some cases, for example an
3945 optional operand present in the actual assembly line will be
3946 omitted in the output; likewise for the optional syntax rules,
3947 e.g. the # before the immediate. Another limitation is that the
3948 assembly symbols and relocation operations in the assembly line
3949 currently cannot be printed out in the error report. Last but not
3950 least, when there is other error(s) co-exist with this error, the
3951 'corrected' instruction may be still incorrect, e.g. given
3952 'ldnp h0,h1,[x0,#6]!'
3953 this diagnosis will provide the version:
3954 'ldnp s0,s1,[x0,#6]!'
3955 which is still not right. */
3956 size_t len = strlen (get_mnemonic_name (str));
3957 int i, qlf_idx;
3958 bfd_boolean result;
3959 const size_t size = 2048;
3960 char buf[size];
3961 aarch64_inst *inst_base = &inst.base;
3962 const aarch64_opnd_qualifier_seq_t *qualifiers_list;
3963
3964 /* Init inst. */
3965 reset_aarch64_instruction (&inst);
3966 inst_base->opcode = opcode;
3967
3968 /* Reset the error report so that there is no side effect on the
3969 following operand parsing. */
3970 init_operand_error_report ();
3971
3972 /* Fill inst. */
3973 result = parse_operands (str + len, opcode)
3974 && programmer_friendly_fixup (&inst);
3975 gas_assert (result);
3976 result = aarch64_opcode_encode (opcode, inst_base, &inst_base->value,
3977 NULL, NULL);
3978 gas_assert (!result);
3979
3980 /* Find the most matched qualifier sequence. */
3981 qlf_idx = find_best_match (inst_base, opcode->qualifiers_list);
3982 gas_assert (qlf_idx > -1);
3983
3984 /* Assign the qualifiers. */
3985 assign_qualifier_sequence (inst_base,
3986 opcode->qualifiers_list[qlf_idx]);
3987
3988 /* Print the hint. */
3989 output_info (_(" did you mean this?"));
3990 snprintf (buf, size, "\t%s", get_mnemonic_name (str));
3991 print_operands (buf, opcode, inst_base->operands);
3992 output_info (_(" %s"), buf);
3993
3994 /* Print out other variant(s) if there is any. */
3995 if (qlf_idx != 0 ||
3996 !empty_qualifier_sequence_p (opcode->qualifiers_list[1]))
3997 output_info (_(" other valid variant(s):"));
3998
3999 /* For each pattern. */
4000 qualifiers_list = opcode->qualifiers_list;
4001 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
4002 {
4003 /* Most opcodes has much fewer patterns in the list.
4004 First NIL qualifier indicates the end in the list. */
4005 if (empty_qualifier_sequence_p (*qualifiers_list) == TRUE)
4006 break;
4007
4008 if (i != qlf_idx)
4009 {
4010 /* Mnemonics name. */
4011 snprintf (buf, size, "\t%s", get_mnemonic_name (str));
4012
4013 /* Assign the qualifiers. */
4014 assign_qualifier_sequence (inst_base, *qualifiers_list);
4015
4016 /* Print instruction. */
4017 print_operands (buf, opcode, inst_base->operands);
4018
4019 output_info (_(" %s"), buf);
4020 }
4021 }
4022 }
4023 break;
4024
4025 case AARCH64_OPDE_OUT_OF_RANGE:
f5555712
YZ		 4026 if (detail->data[0] != detail->data[1])
4027 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4028 detail->error ? detail->error : _("immediate value"),
4029 detail->data[0], detail->data[1], detail->index + 1, str);
4030 else
4031 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4032 detail->error ? detail->error : _("immediate value"),
4033 detail->data[0], detail->index + 1, str);
a06ea964
NC		 4034 break;
4035
4036 case AARCH64_OPDE_REG_LIST:
4037 if (detail->data[0] == 1)
4038 as_bad (_("invalid number of registers in the list; "
4039 "only 1 register is expected at operand %d -- `%s'"),
4040 detail->index + 1, str);
4041 else
4042 as_bad (_("invalid number of registers in the list; "
4043 "%d registers are expected at operand %d -- `%s'"),
4044 detail->data[0], detail->index + 1, str);
4045 break;
4046
4047 case AARCH64_OPDE_UNALIGNED:
4048 as_bad (_("immediate value should be a multiple of "
4049 "%d at operand %d -- `%s'"),
4050 detail->data[0], detail->index + 1, str);
4051 break;
4052
4053 default:
4054 gas_assert (0);
4055 break;
4056 }
4057}
4058
4059/* Process and output the error message about the operand mismatching.
4060
4061 When this function is called, the operand error information had
4062 been collected for an assembly line and there will be multiple
4063 errors in the case of mulitple instruction templates; output the
4064 error message that most closely describes the problem. */
4065
4066static void
4067output_operand_error_report (char *str)
4068{
4069 int largest_error_pos;
4070 const char *msg = NULL;
4071 enum aarch64_operand_error_kind kind;
4072 operand_error_record *curr;
4073 operand_error_record *head = operand_error_report.head;
4074 operand_error_record *record = NULL;
4075
4076 /* No error to report. */
4077 if (head == NULL)
4078 return;
4079
4080 gas_assert (head != NULL && operand_error_report.tail != NULL);
4081
4082 /* Only one error. */
4083 if (head == operand_error_report.tail)
4084 {
4085 DEBUG_TRACE ("single opcode entry with error kind: %s",
4086 operand_mismatch_kind_names[head->detail.kind]);
4087 output_operand_error_record (head, str);
4088 return;
4089 }
4090
4091 /* Find the error kind of the highest severity. */
4092 DEBUG_TRACE ("multiple opcode entres with error kind");
4093 kind = AARCH64_OPDE_NIL;
4094 for (curr = head; curr != NULL; curr = curr->next)
4095 {
4096 gas_assert (curr->detail.kind != AARCH64_OPDE_NIL);
4097 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
4098 if (operand_error_higher_severity_p (curr->detail.kind, kind))
4099 kind = curr->detail.kind;
4100 }
4101 gas_assert (kind != AARCH64_OPDE_NIL);
4102
4103 /* Pick up one of errors of KIND to report. */
4104 largest_error_pos = -2; /* Index can be -1 which means unknown index. */
4105 for (curr = head; curr != NULL; curr = curr->next)
4106 {
4107 if (curr->detail.kind != kind)
4108 continue;
4109 /* If there are multiple errors, pick up the one with the highest
4110 mismatching operand index. In the case of multiple errors with
4111 the equally highest operand index, pick up the first one or the
4112 first one with non-NULL error message. */
4113 if (curr->detail.index > largest_error_pos
4114 || (curr->detail.index == largest_error_pos && msg == NULL
4115 && curr->detail.error != NULL))
4116 {
4117 largest_error_pos = curr->detail.index;
4118 record = curr;
4119 msg = record->detail.error;
4120 }
4121 }
4122
4123 gas_assert (largest_error_pos != -2 && record != NULL);
4124 DEBUG_TRACE ("Pick up error kind %s to report",
4125 operand_mismatch_kind_names[record->detail.kind]);
4126
4127 /* Output. */
4128 output_operand_error_record (record, str);
4129}
4130\f
4131/* Write an AARCH64 instruction to buf - always little-endian. */
4132static void
4133put_aarch64_insn (char *buf, uint32_t insn)
4134{
4135 unsigned char *where = (unsigned char *) buf;
4136 where[0] = insn;
4137 where[1] = insn >> 8;
4138 where[2] = insn >> 16;
4139 where[3] = insn >> 24;
4140}
4141
4142static uint32_t
4143get_aarch64_insn (char *buf)
4144{
4145 unsigned char *where = (unsigned char *) buf;
4146 uint32_t result;
4147 result = (where[0] | (where[1] << 8) | (where[2] << 16) | (where[3] << 24));
4148 return result;
4149}
4150
4151static void
4152output_inst (struct aarch64_inst *new_inst)
4153{
4154 char *to = NULL;
4155
4156 to = frag_more (INSN_SIZE);
4157
4158 frag_now->tc_frag_data.recorded = 1;
4159
4160 put_aarch64_insn (to, inst.base.value);
4161
4162 if (inst.reloc.type != BFD_RELOC_UNUSED)
4163 {
4164 fixS *fixp = fix_new_aarch64 (frag_now, to - frag_now->fr_literal,
4165 INSN_SIZE, &inst.reloc.exp,
4166 inst.reloc.pc_rel,
4167 inst.reloc.type);
4168 DEBUG_TRACE ("Prepared relocation fix up");
4169 /* Don't check the addend value against the instruction size,
4170 that's the job of our code in md_apply_fix(). */
4171 fixp->fx_no_overflow = 1;
4172 if (new_inst != NULL)
4173 fixp->tc_fix_data.inst = new_inst;
4174 if (aarch64_gas_internal_fixup_p ())
4175 {
4176 gas_assert (inst.reloc.opnd != AARCH64_OPND_NIL);
4177 fixp->tc_fix_data.opnd = inst.reloc.opnd;
4178 fixp->fx_addnumber = inst.reloc.flags;
4179 }
4180 }
4181
4182 dwarf2_emit_insn (INSN_SIZE);
4183}
4184
4185/* Link together opcodes of the same name. */
4186
4187struct templates
4188{
4189 aarch64_opcode *opcode;
4190 struct templates *next;
4191};
4192
4193typedef struct templates templates;
4194
4195static templates *
4196lookup_mnemonic (const char *start, int len)
4197{
4198 templates *templ = NULL;
4199
4200 templ = hash_find_n (aarch64_ops_hsh, start, len);
4201 return templ;
4202}
4203
4204/* Subroutine of md_assemble, responsible for looking up the primary
4205 opcode from the mnemonic the user wrote. STR points to the
4206 beginning of the mnemonic. */
4207
4208static templates *
4209opcode_lookup (char **str)
4210{
4211 char *end, *base;
4212 const aarch64_cond *cond;
4213 char condname[16];
4214 int len;
4215
4216 /* Scan up to the end of the mnemonic, which must end in white space,
4217 '.', or end of string. */
4218 for (base = end = *str; is_part_of_name(*end); end++)
4219 if (*end == '.')
4220 break;
4221
4222 if (end == base)
4223 return 0;
4224
4225 inst.cond = COND_ALWAYS;
4226
4227 /* Handle a possible condition. */
4228 if (end[0] == '.')
4229 {
4230 cond = hash_find_n (aarch64_cond_hsh, end + 1, 2);
4231 if (cond)
4232 {
4233 inst.cond = cond->value;
4234 *str = end + 3;
4235 }
4236 else
4237 {
4238 *str = end;
4239 return 0;
4240 }
4241 }
4242 else
4243 *str = end;
4244
4245 len = end - base;
4246
4247 if (inst.cond == COND_ALWAYS)
4248 {
4249 /* Look for unaffixed mnemonic. */
4250 return lookup_mnemonic (base, len);
4251 }
4252 else if (len <= 13)
4253 {
4254 /* append ".c" to mnemonic if conditional */
4255 memcpy (condname, base, len);
4256 memcpy (condname + len, ".c", 2);
4257 base = condname;
4258 len += 2;
4259 return lookup_mnemonic (base, len);
4260 }
4261
4262 return NULL;
4263}
4264
4265/* Internal helper routine converting a vector neon_type_el structure
4266 *VECTYPE to a corresponding operand qualifier. */
4267
4268static inline aarch64_opnd_qualifier_t
4269vectype_to_qualifier (const struct neon_type_el *vectype)
4270{
4271 /* Element size in bytes indexed by neon_el_type. */
4272 const unsigned char ele_size[5]
4273 = {1, 2, 4, 8, 16};
4274
4275 if (!vectype->defined || vectype->type == NT_invtype)
4276 goto vectype_conversion_fail;
4277
4278 gas_assert (vectype->type >= NT_b && vectype->type <= NT_q);
4279
4280 if (vectype->defined & NTA_HASINDEX)
4281 /* Vector element register. */
4282 return AARCH64_OPND_QLF_S_B + vectype->type;
4283 else
4284 {
4285 /* Vector register. */
4286 int reg_size = ele_size[vectype->type] * vectype->width;
4287 unsigned offset;
4288 if (reg_size != 16 && reg_size != 8)
4289 goto vectype_conversion_fail;
4290 /* The conversion is calculated based on the relation of the order of
4291 qualifiers to the vector element size and vector register size. */
4292 offset = (vectype->type == NT_q)
4293 ? 8 : (vectype->type << 1) + (reg_size >> 4);
4294 gas_assert (offset <= 8);
4295 return AARCH64_OPND_QLF_V_8B + offset;
4296 }
4297
4298vectype_conversion_fail:
4299 first_error (_("bad vector arrangement type"));
4300 return AARCH64_OPND_QLF_NIL;
4301}
4302
4303/* Process an optional operand that is found omitted from the assembly line.
4304 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4305 instruction's opcode entry while IDX is the index of this omitted operand.
4306 */
4307
4308static void
4309process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
4310 int idx, aarch64_opnd_info *operand)
4311{
4312 aarch64_insn default_value = get_optional_operand_default_value (opcode);
4313 gas_assert (optional_operand_p (opcode, idx));
4314 gas_assert (!operand->present);
4315
4316 switch (type)
4317 {
4318 case AARCH64_OPND_Rd:
4319 case AARCH64_OPND_Rn:
4320 case AARCH64_OPND_Rm:
4321 case AARCH64_OPND_Rt:
4322 case AARCH64_OPND_Rt2:
4323 case AARCH64_OPND_Rs:
4324 case AARCH64_OPND_Ra:
4325 case AARCH64_OPND_Rt_SYS:
4326 case AARCH64_OPND_Rd_SP:
4327 case AARCH64_OPND_Rn_SP:
4328 case AARCH64_OPND_Fd:
4329 case AARCH64_OPND_Fn:
4330 case AARCH64_OPND_Fm:
4331 case AARCH64_OPND_Fa:
4332 case AARCH64_OPND_Ft:
4333 case AARCH64_OPND_Ft2:
4334 case AARCH64_OPND_Sd:
4335 case AARCH64_OPND_Sn:
4336 case AARCH64_OPND_Sm:
4337 case AARCH64_OPND_Vd:
4338 case AARCH64_OPND_Vn:
4339 case AARCH64_OPND_Vm:
4340 case AARCH64_OPND_VdD1:
4341 case AARCH64_OPND_VnD1:
4342 operand->reg.regno = default_value;
4343 break;
4344
4345 case AARCH64_OPND_Ed:
4346 case AARCH64_OPND_En:
4347 case AARCH64_OPND_Em:
4348 operand->reglane.regno = default_value;
4349 break;
4350
4351 case AARCH64_OPND_IDX:
4352 case AARCH64_OPND_BIT_NUM:
4353 case AARCH64_OPND_IMMR:
4354 case AARCH64_OPND_IMMS:
4355 case AARCH64_OPND_SHLL_IMM:
4356 case AARCH64_OPND_IMM_VLSL:
4357 case AARCH64_OPND_IMM_VLSR:
4358 case AARCH64_OPND_CCMP_IMM:
4359 case AARCH64_OPND_FBITS:
4360 case AARCH64_OPND_UIMM4:
4361 case AARCH64_OPND_UIMM3_OP1:
4362 case AARCH64_OPND_UIMM3_OP2:
4363 case AARCH64_OPND_IMM:
4364 case AARCH64_OPND_WIDTH:
4365 case AARCH64_OPND_UIMM7:
4366 case AARCH64_OPND_NZCV:
4367 operand->imm.value = default_value;
4368 break;
4369
4370 case AARCH64_OPND_EXCEPTION:
4371 inst.reloc.type = BFD_RELOC_UNUSED;
4372 break;
4373
4374 case AARCH64_OPND_BARRIER_ISB:
4375 operand->barrier = aarch64_barrier_options + default_value;
4376
4377 default:
4378 break;
4379 }
4380}
4381
4382/* Process the relocation type for move wide instructions.
4383 Return TRUE on success; otherwise return FALSE. */
4384
4385static bfd_boolean
4386process_movw_reloc_info (void)
4387{
4388 int is32;
4389 unsigned shift;
4390
4391 is32 = inst.base.operands[0].qualifier == AARCH64_OPND_QLF_W ? 1 : 0;
4392
4393 if (inst.base.opcode->op == OP_MOVK)
4394 switch (inst.reloc.type)
4395 {
4396 case BFD_RELOC_AARCH64_MOVW_G0_S:
4397 case BFD_RELOC_AARCH64_MOVW_G1_S:
4398 case BFD_RELOC_AARCH64_MOVW_G2_S:
4399 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
4400 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
4401 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
4402 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
4403 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
4404 set_syntax_error
4405 (_("the specified relocation type is not allowed for MOVK"));
4406 return FALSE;
4407 default:
4408 break;
4409 }
4410
4411 switch (inst.reloc.type)
4412 {
4413 case BFD_RELOC_AARCH64_MOVW_G0:
4414 case BFD_RELOC_AARCH64_MOVW_G0_S:
4415 case BFD_RELOC_AARCH64_MOVW_G0_NC:
4416 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
4417 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
4418 shift = 0;
4419 break;
4420 case BFD_RELOC_AARCH64_MOVW_G1:
4421 case BFD_RELOC_AARCH64_MOVW_G1_S:
4422 case BFD_RELOC_AARCH64_MOVW_G1_NC:
4423 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
4424 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
4425 shift = 16;
4426 break;
4427 case BFD_RELOC_AARCH64_MOVW_G2:
4428 case BFD_RELOC_AARCH64_MOVW_G2_S:
4429 case BFD_RELOC_AARCH64_MOVW_G2_NC:
4430 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
4431 if (is32)
4432 {
4433 set_fatal_syntax_error
4434 (_("the specified relocation type is not allowed for 32-bit "
4435 "register"));
4436 return FALSE;
4437 }
4438 shift = 32;
4439 break;
4440 case BFD_RELOC_AARCH64_MOVW_G3:
4441 if (is32)
4442 {
4443 set_fatal_syntax_error
4444 (_("the specified relocation type is not allowed for 32-bit "
4445 "register"));
4446 return FALSE;
4447 }
4448 shift = 48;
4449 break;
4450 default:
4451 /* More cases should be added when more MOVW-related relocation types
4452 are supported in GAS. */
4453 gas_assert (aarch64_gas_internal_fixup_p ());
4454 /* The shift amount should have already been set by the parser. */
4455 return TRUE;
4456 }
4457 inst.base.operands[1].shifter.amount = shift;
4458 return TRUE;
4459}
4460
4461/* A primitive log caculator. */
4462
4463static inline unsigned int
4464get_logsz (unsigned int size)
4465{
4466 const unsigned char ls[16] =
4467 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4468 if (size > 16)
4469 {
4470 gas_assert (0);
4471 return -1;
4472 }
4473 gas_assert (ls[size - 1] != (unsigned char)-1);
4474 return ls[size - 1];
4475}
4476
4477/* Determine and return the real reloc type code for an instruction
4478 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4479
4480static inline bfd_reloc_code_real_type
4481ldst_lo12_determine_real_reloc_type (void)
4482{
4483 int logsz;
4484 enum aarch64_opnd_qualifier opd0_qlf = inst.base.operands[0].qualifier;
4485 enum aarch64_opnd_qualifier opd1_qlf = inst.base.operands[1].qualifier;
4486
4487 const bfd_reloc_code_real_type reloc_ldst_lo12[5] = {
4488 BFD_RELOC_AARCH64_LDST8_LO12, BFD_RELOC_AARCH64_LDST16_LO12,
4489 BFD_RELOC_AARCH64_LDST32_LO12, BFD_RELOC_AARCH64_LDST64_LO12,
4490 BFD_RELOC_AARCH64_LDST128_LO12
4491 };
4492
4493 gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12);
4494 gas_assert (inst.base.opcode->operands[1] == AARCH64_OPND_ADDR_UIMM12);
4495
4496 if (opd1_qlf == AARCH64_OPND_QLF_NIL)
4497 opd1_qlf =
4498 aarch64_get_expected_qualifier (inst.base.opcode->qualifiers_list,
4499 1, opd0_qlf, 0);
4500 gas_assert (opd1_qlf != AARCH64_OPND_QLF_NIL);
4501
4502 logsz = get_logsz (aarch64_get_qualifier_esize (opd1_qlf));
4503 gas_assert (logsz >= 0 && logsz <= 4);
4504
4505 return reloc_ldst_lo12[logsz];
4506}
4507
4508/* Check whether a register list REGINFO is valid. The registers must be
4509 numbered in increasing order (modulo 32), in increments of one or two.
4510
4511 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4512 increments of two.
4513
4514 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4515
4516static bfd_boolean
4517reg_list_valid_p (uint32_t reginfo, int accept_alternate)
4518{
4519 uint32_t i, nb_regs, prev_regno, incr;
4520
4521 nb_regs = 1 + (reginfo & 0x3);
4522 reginfo >>= 2;
4523 prev_regno = reginfo & 0x1f;
4524 incr = accept_alternate ? 2 : 1;
4525
4526 for (i = 1; i < nb_regs; ++i)
4527 {
4528 uint32_t curr_regno;
4529 reginfo >>= 5;
4530 curr_regno = reginfo & 0x1f;
4531 if (curr_regno != ((prev_regno + incr) & 0x1f))
4532 return FALSE;
4533 prev_regno = curr_regno;
4534 }
4535
4536 return TRUE;
4537}
4538
4539/* Generic instruction operand parser. This does no encoding and no
4540 semantic validation; it merely squirrels values away in the inst
4541 structure. Returns TRUE or FALSE depending on whether the
4542 specified grammar matched. */
4543
4544static bfd_boolean
4545parse_operands (char *str, const aarch64_opcode *opcode)
4546{
4547 int i;
4548 char *backtrack_pos = 0;
4549 const enum aarch64_opnd *operands = opcode->operands;
4550
4551 clear_error ();
4552 skip_whitespace (str);
4553
4554 for (i = 0; operands[i] != AARCH64_OPND_NIL; i++)
4555 {
4556 int64_t val;
4557 int isreg32, isregzero;
4558 int comma_skipped_p = 0;
4559 aarch64_reg_type rtype;
4560 struct neon_type_el vectype;
4561 aarch64_opnd_info *info = &inst.base.operands[i];
4562
4563 DEBUG_TRACE ("parse operand %d", i);
4564
4565 /* Assign the operand code. */
4566 info->type = operands[i];
4567
4568 if (optional_operand_p (opcode, i))
4569 {
4570 /* Remember where we are in case we need to backtrack. */
4571 gas_assert (!backtrack_pos);
4572 backtrack_pos = str;
4573 }
4574
4575 /* Expect comma between operands; the backtrack mechanizm will take
4576 care of cases of omitted optional operand. */
4577 if (i > 0 && ! skip_past_char (&str, ','))
4578 {
4579 set_syntax_error (_("comma expected between operands"));
4580 goto failure;
4581 }
4582 else
4583 comma_skipped_p = 1;
4584
4585 switch (operands[i])
4586 {
4587 case AARCH64_OPND_Rd:
4588 case AARCH64_OPND_Rn:
4589 case AARCH64_OPND_Rm:
4590 case AARCH64_OPND_Rt:
4591 case AARCH64_OPND_Rt2:
4592 case AARCH64_OPND_Rs:
4593 case AARCH64_OPND_Ra:
4594 case AARCH64_OPND_Rt_SYS:
4595 po_int_reg_or_fail (1, 0);
4596 break;
4597
4598 case AARCH64_OPND_Rd_SP:
4599 case AARCH64_OPND_Rn_SP:
4600 po_int_reg_or_fail (0, 1);
4601 break;
4602
4603 case AARCH64_OPND_Rm_EXT:
4604 case AARCH64_OPND_Rm_SFT:
4605 po_misc_or_fail (parse_shifter_operand
4606 (&str, info, (operands[i] == AARCH64_OPND_Rm_EXT
4607 ? SHIFTED_ARITH_IMM
4608 : SHIFTED_LOGIC_IMM)));
4609 if (!info->shifter.operator_present)
4610 {
4611 /* Default to LSL if not present. Libopcodes prefers shifter
4612 kind to be explicit. */
4613 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
4614 info->shifter.kind = AARCH64_MOD_LSL;
4615 /* For Rm_EXT, libopcodes will carry out further check on whether
4616 or not stack pointer is used in the instruction (Recall that
4617 "the extend operator is not optional unless at least one of
4618 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
4619 }
4620 break;
4621
4622 case AARCH64_OPND_Fd:
4623 case AARCH64_OPND_Fn:
4624 case AARCH64_OPND_Fm:
4625 case AARCH64_OPND_Fa:
4626 case AARCH64_OPND_Ft:
4627 case AARCH64_OPND_Ft2:
4628 case AARCH64_OPND_Sd:
4629 case AARCH64_OPND_Sn:
4630 case AARCH64_OPND_Sm:
4631 val = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, &rtype, NULL);
4632 if (val == PARSE_FAIL)
4633 {
4634 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ)));
4635 goto failure;
4636 }
4637 gas_assert (rtype >= REG_TYPE_FP_B && rtype <= REG_TYPE_FP_Q);
4638
4639 info->reg.regno = val;
4640 info->qualifier = AARCH64_OPND_QLF_S_B + (rtype - REG_TYPE_FP_B);
4641 break;
4642
4643 case AARCH64_OPND_Vd:
4644 case AARCH64_OPND_Vn:
4645 case AARCH64_OPND_Vm:
4646 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
4647 if (val == PARSE_FAIL)
4648 {
4649 first_error (_(get_reg_expected_msg (REG_TYPE_VN)));
4650 goto failure;
4651 }
4652 if (vectype.defined & NTA_HASINDEX)
4653 goto failure;
4654
4655 info->reg.regno = val;
4656 info->qualifier = vectype_to_qualifier (&vectype);
4657 if (info->qualifier == AARCH64_OPND_QLF_NIL)
4658 goto failure;
4659 break;
4660
4661 case AARCH64_OPND_VdD1:
4662 case AARCH64_OPND_VnD1:
4663 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
4664 if (val == PARSE_FAIL)
4665 {
4666 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN)));
4667 goto failure;
4668 }
4669 if (vectype.type != NT_d || vectype.index != 1)
4670 {
4671 set_fatal_syntax_error
4672 (_("the top half of a 128-bit FP/SIMD register is expected"));
4673 goto failure;
4674 }
4675 info->reg.regno = val;
4676 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
4677 here; it is correct for the purpose of encoding/decoding since
4678 only the register number is explicitly encoded in the related
4679 instructions, although this appears a bit hacky. */
4680 info->qualifier = AARCH64_OPND_QLF_S_D;
4681 break;
4682
4683 case AARCH64_OPND_Ed:
4684 case AARCH64_OPND_En:
4685 case AARCH64_OPND_Em:
4686 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
4687 if (val == PARSE_FAIL)
4688 {
4689 first_error (_(get_reg_expected_msg (REG_TYPE_VN)));
4690 goto failure;
4691 }
4692 if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX))
4693 goto failure;
4694
4695 info->reglane.regno = val;
4696 info->reglane.index = vectype.index;
4697 info->qualifier = vectype_to_qualifier (&vectype);
4698 if (info->qualifier == AARCH64_OPND_QLF_NIL)
4699 goto failure;
4700 break;
4701
4702 case AARCH64_OPND_LVn:
4703 case AARCH64_OPND_LVt:
4704 case AARCH64_OPND_LVt_AL:
4705 case AARCH64_OPND_LEt:
4706 if ((val = parse_neon_reg_list (&str, &vectype)) == PARSE_FAIL)
4707 goto failure;
4708 if (! reg_list_valid_p (val, /* accept_alternate */ 0))
4709 {
4710 set_fatal_syntax_error (_("invalid register list"));
4711 goto failure;
4712 }
4713 info->reglist.first_regno = (val >> 2) & 0x1f;
4714 info->reglist.num_regs = (val & 0x3) + 1;
4715 if (operands[i] == AARCH64_OPND_LEt)
4716 {
4717 if (!(vectype.defined & NTA_HASINDEX))
4718 goto failure;
4719 info->reglist.has_index = 1;
4720 info->reglist.index = vectype.index;
4721 }
4722 else if (!(vectype.defined & NTA_HASTYPE))
4723 goto failure;
4724 info->qualifier = vectype_to_qualifier (&vectype);
4725 if (info->qualifier == AARCH64_OPND_QLF_NIL)
4726 goto failure;
4727 break;
4728
4729 case AARCH64_OPND_Cn:
4730 case AARCH64_OPND_Cm:
4731 po_reg_or_fail (REG_TYPE_CN);
4732 if (val > 15)
4733 {
4734 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN)));
4735 goto failure;
4736 }
4737 inst.base.operands[i].reg.regno = val;
4738 break;
4739
4740 case AARCH64_OPND_SHLL_IMM:
4741 case AARCH64_OPND_IMM_VLSR:
4742 po_imm_or_fail (1, 64);
4743 info->imm.value = val;
4744 break;
4745
4746 case AARCH64_OPND_CCMP_IMM:
4747 case AARCH64_OPND_FBITS:
4748 case AARCH64_OPND_UIMM4:
4749 case AARCH64_OPND_UIMM3_OP1:
4750 case AARCH64_OPND_UIMM3_OP2:
4751 case AARCH64_OPND_IMM_VLSL:
4752 case AARCH64_OPND_IMM:
4753 case AARCH64_OPND_WIDTH:
4754 po_imm_nc_or_fail ();
4755 info->imm.value = val;
4756 break;
4757
4758 case AARCH64_OPND_UIMM7:
4759 po_imm_or_fail (0, 127);
4760 info->imm.value = val;
4761 break;
4762
4763 case AARCH64_OPND_IDX:
4764 case AARCH64_OPND_BIT_NUM:
4765 case AARCH64_OPND_IMMR:
4766 case AARCH64_OPND_IMMS:
4767 po_imm_or_fail (0, 63);
4768 info->imm.value = val;
4769 break;
4770
4771 case AARCH64_OPND_IMM0:
4772 po_imm_nc_or_fail ();
4773 if (val != 0)
4774 {
4775 set_fatal_syntax_error (_("immediate zero expected"));
4776 goto failure;
4777 }
4778 info->imm.value = 0;
4779 break;
4780
4781 case AARCH64_OPND_FPIMM0:
4782 {
4783 int qfloat;
4784 bfd_boolean res1 = FALSE, res2 = FALSE;
4785 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
4786 it is probably not worth the effort to support it. */
62b0d0d5 4787 if (!(res1 = parse_aarch64_imm_float (&str, &qfloat, FALSE))
a06ea964
NC		 4788 && !(res2 = parse_constant_immediate (&str, &val)))
4789 goto failure;
4790 if ((res1 && qfloat == 0) || (res2 && val == 0))
4791 {
4792 info->imm.value = 0;
4793 info->imm.is_fp = 1;
4794 break;
4795 }
4796 set_fatal_syntax_error (_("immediate zero expected"));
4797 goto failure;
4798 }
4799
4800 case AARCH64_OPND_IMM_MOV:
4801 {
4802 char *saved = str;
4803 if (reg_name_p (str, REG_TYPE_R_Z_SP))
4804 goto failure;
4805 str = saved;
4806 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
4807 GE_OPT_PREFIX, 1));
4808 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
4809 later. fix_mov_imm_insn will try to determine a machine
4810 instruction (MOVZ, MOVN or ORR) for it and will issue an error
4811 message if the immediate cannot be moved by a single
4812 instruction. */
4813 aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
4814 inst.base.operands[i].skip = 1;
4815 }
4816 break;
4817
4818 case AARCH64_OPND_SIMD_IMM:
4819 case AARCH64_OPND_SIMD_IMM_SFT:
4820 if (! parse_big_immediate (&str, &val))
4821 goto failure;
4822 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
4823 /* addr_off_p */ 0,
4824 /* need_libopcodes_p */ 1,
4825 /* skip_p */ 1);
4826 /* Parse shift.
4827 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
4828 shift, we don't check it here; we leave the checking to
4829 the libopcodes (operand_general_constraint_met_p). By
4830 doing this, we achieve better diagnostics. */
4831 if (skip_past_comma (&str)
4832 && ! parse_shift (&str, info, SHIFTED_LSL_MSL))
4833 goto failure;
4834 if (!info->shifter.operator_present
4835 && info->type == AARCH64_OPND_SIMD_IMM_SFT)
4836 {
4837 /* Default to LSL if not present. Libopcodes prefers shifter
4838 kind to be explicit. */
4839 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
4840 info->shifter.kind = AARCH64_MOD_LSL;
4841 }
4842 break;
4843
4844 case AARCH64_OPND_FPIMM:
4845 case AARCH64_OPND_SIMD_FPIMM:
4846 {
4847 int qfloat;
62b0d0d5
YZ		 4848 bfd_boolean dp_p
4849 = (aarch64_get_qualifier_esize (inst.base.operands[0].qualifier)
4850 == 8);
4851 if (! parse_aarch64_imm_float (&str, &qfloat, dp_p))
a06ea964
NC		 4852 goto failure;
4853 if (qfloat == 0)
4854 {
4855 set_fatal_syntax_error (_("invalid floating-point constant"));
4856 goto failure;
4857 }
4858 inst.base.operands[i].imm.value = encode_imm_float_bits (qfloat);
4859 inst.base.operands[i].imm.is_fp = 1;
4860 }
4861 break;
4862
4863 case AARCH64_OPND_LIMM:
4864 po_misc_or_fail (parse_shifter_operand (&str, info,
4865 SHIFTED_LOGIC_IMM));
4866 if (info->shifter.operator_present)
4867 {
4868 set_fatal_syntax_error
4869 (_("shift not allowed for bitmask immediate"));
4870 goto failure;
4871 }
4872 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
4873 /* addr_off_p */ 0,
4874 /* need_libopcodes_p */ 1,
4875 /* skip_p */ 1);
4876 break;
4877
4878 case AARCH64_OPND_AIMM:
4879 if (opcode->op == OP_ADD)
4880 /* ADD may have relocation types. */
4881 po_misc_or_fail (parse_shifter_operand_reloc (&str, info,
4882 SHIFTED_ARITH_IMM));
4883 else
4884 po_misc_or_fail (parse_shifter_operand (&str, info,
4885 SHIFTED_ARITH_IMM));
4886 switch (inst.reloc.type)
4887 {
4888 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
4889 info->shifter.amount = 12;
4890 break;
4891 case BFD_RELOC_UNUSED:
4892 aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
4893 if (info->shifter.kind != AARCH64_MOD_NONE)
4894 inst.reloc.flags = FIXUP_F_HAS_EXPLICIT_SHIFT;
4895 inst.reloc.pc_rel = 0;
4896 break;
4897 default:
4898 break;
4899 }
4900 info->imm.value = 0;
4901 if (!info->shifter.operator_present)
4902 {
4903 /* Default to LSL if not present. Libopcodes prefers shifter
4904 kind to be explicit. */
4905 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
4906 info->shifter.kind = AARCH64_MOD_LSL;
4907 }
4908 break;
4909
4910 case AARCH64_OPND_HALF:
4911 {
4912 /* #<imm16> or relocation. */
4913 int internal_fixup_p;
4914 po_misc_or_fail (parse_half (&str, &internal_fixup_p));
4915 if (internal_fixup_p)
4916 aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
4917 skip_whitespace (str);
4918 if (skip_past_comma (&str))
4919 {
4920 /* {, LSL #<shift>} */
4921 if (! aarch64_gas_internal_fixup_p ())
4922 {
4923 set_fatal_syntax_error (_("can't mix relocation modifier "
4924 "with explicit shift"));
4925 goto failure;
4926 }
4927 po_misc_or_fail (parse_shift (&str, info, SHIFTED_LSL));
4928 }
4929 else
4930 inst.base.operands[i].shifter.amount = 0;
4931 inst.base.operands[i].shifter.kind = AARCH64_MOD_LSL;
4932 inst.base.operands[i].imm.value = 0;
4933 if (! process_movw_reloc_info ())
4934 goto failure;
4935 }
4936 break;
4937
4938 case AARCH64_OPND_EXCEPTION:
4939 po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp));
4940 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
4941 /* addr_off_p */ 0,
4942 /* need_libopcodes_p */ 0,
4943 /* skip_p */ 1);
4944 break;
4945
4946 case AARCH64_OPND_NZCV:
4947 {
4948 const asm_nzcv *nzcv = hash_find_n (aarch64_nzcv_hsh, str, 4);
4949 if (nzcv != NULL)
4950 {
4951 str += 4;
4952 info->imm.value = nzcv->value;
4953 break;
4954 }
4955 po_imm_or_fail (0, 15);
4956 info->imm.value = val;
4957 }
4958 break;
4959
4960 case AARCH64_OPND_COND:
4961 info->cond = hash_find_n (aarch64_cond_hsh, str, 2);
4962 str += 2;
4963 if (info->cond == NULL)
4964 {
4965 set_syntax_error (_("invalid condition"));
4966 goto failure;
4967 }
4968 break;
4969
4970 case AARCH64_OPND_ADDR_ADRP:
4971 po_misc_or_fail (parse_adrp (&str));
4972 /* Clear the value as operand needs to be relocated. */
4973 info->imm.value = 0;
4974 break;
4975
4976 case AARCH64_OPND_ADDR_PCREL14:
4977 case AARCH64_OPND_ADDR_PCREL19:
4978 case AARCH64_OPND_ADDR_PCREL21:
4979 case AARCH64_OPND_ADDR_PCREL26:
4980 po_misc_or_fail (parse_address_reloc (&str, info));
4981 if (!info->addr.pcrel)
4982 {
4983 set_syntax_error (_("invalid pc-relative address"));
4984 goto failure;
4985 }
4986 if (inst.gen_lit_pool
4987 && (opcode->iclass != loadlit || opcode->op == OP_PRFM_LIT))
4988 {
4989 /* Only permit "=value" in the literal load instructions.
4990 The literal will be generated by programmer_friendly_fixup. */
4991 set_syntax_error (_("invalid use of \"=immediate\""));
4992 goto failure;
4993 }
4994 if (inst.reloc.exp.X_op == O_symbol && find_reloc_table_entry (&str))
4995 {
4996 set_syntax_error (_("unrecognized relocation suffix"));
4997 goto failure;
4998 }
4999 if (inst.reloc.exp.X_op == O_constant && !inst.gen_lit_pool)
5000 {
5001 info->imm.value = inst.reloc.exp.X_add_number;
5002 inst.reloc.type = BFD_RELOC_UNUSED;
5003 }
5004 else
5005 {
5006 info->imm.value = 0;
f41aef5f
RE		 5007 if (inst.reloc.type == BFD_RELOC_UNUSED)
5008 switch (opcode->iclass)
5009 {
5010 case compbranch:
5011 case condbranch:
5012 /* e.g. CBZ or B.COND */
5013 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
5014 inst.reloc.type = BFD_RELOC_AARCH64_BRANCH19;
5015 break;
5016 case testbranch:
5017 /* e.g. TBZ */
5018 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL14);
5019 inst.reloc.type = BFD_RELOC_AARCH64_TSTBR14;
5020 break;
5021 case branch_imm:
5022 /* e.g. B or BL */
5023 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL26);
5024 inst.reloc.type =
5025 (opcode->op == OP_BL) ? BFD_RELOC_AARCH64_CALL26
5026 : BFD_RELOC_AARCH64_JUMP26;
5027 break;
5028 case loadlit:
5029 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
5030 inst.reloc.type = BFD_RELOC_AARCH64_LD_LO19_PCREL;
5031 break;
5032 case pcreladdr:
5033 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL21);
5034 inst.reloc.type = BFD_RELOC_AARCH64_ADR_LO21_PCREL;
5035 break;
5036 default:
5037 gas_assert (0);
5038 abort ();
5039 }
a06ea964
NC		 5040 inst.reloc.pc_rel = 1;
5041 }
5042 break;
5043
5044 case AARCH64_OPND_ADDR_SIMPLE:
5045 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
5046 /* [<Xn|SP>{, #<simm>}] */
5047 po_char_or_fail ('[');
5048 po_reg_or_fail (REG_TYPE_R64_SP);
5049 /* Accept optional ", #0". */
5050 if (operands[i] == AARCH64_OPND_ADDR_SIMPLE
5051 && skip_past_char (&str, ','))
5052 {
5053 skip_past_char (&str, '#');
5054 if (! skip_past_char (&str, '0'))
5055 {
5056 set_fatal_syntax_error
5057 (_("the optional immediate offset can only be 0"));
5058 goto failure;
5059 }
5060 }
5061 po_char_or_fail (']');
5062 info->addr.base_regno = val;
5063 break;
5064
5065 case AARCH64_OPND_ADDR_REGOFF:
5066 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5067 po_misc_or_fail (parse_address (&str, info, 0));
5068 if (info->addr.pcrel || !info->addr.offset.is_reg
5069 || !info->addr.preind || info->addr.postind
5070 || info->addr.writeback)
5071 {
5072 set_syntax_error (_("invalid addressing mode"));
5073 goto failure;
5074 }
5075 if (!info->shifter.operator_present)
5076 {
5077 /* Default to LSL if not present. Libopcodes prefers shifter
5078 kind to be explicit. */
5079 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5080 info->shifter.kind = AARCH64_MOD_LSL;
5081 }
5082 /* Qualifier to be deduced by libopcodes. */
5083 break;
5084
5085 case AARCH64_OPND_ADDR_SIMM7:
5086 po_misc_or_fail (parse_address (&str, info, 0));
5087 if (info->addr.pcrel || info->addr.offset.is_reg
5088 || (!info->addr.preind && !info->addr.postind))
5089 {
5090 set_syntax_error (_("invalid addressing mode"));
5091 goto failure;
5092 }
5093 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5094 /* addr_off_p */ 1,
5095 /* need_libopcodes_p */ 1,
5096 /* skip_p */ 0);
5097 break;
5098
5099 case AARCH64_OPND_ADDR_SIMM9:
5100 case AARCH64_OPND_ADDR_SIMM9_2:
5101 po_misc_or_fail (parse_address_reloc (&str, info));
5102 if (info->addr.pcrel || info->addr.offset.is_reg
5103 || (!info->addr.preind && !info->addr.postind)
5104 || (operands[i] == AARCH64_OPND_ADDR_SIMM9_2
5105 && info->addr.writeback))
5106 {
5107 set_syntax_error (_("invalid addressing mode"));
5108 goto failure;
5109 }
5110 if (inst.reloc.type != BFD_RELOC_UNUSED)
5111 {
5112 set_syntax_error (_("relocation not allowed"));
5113 goto failure;
5114 }
5115 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5116 /* addr_off_p */ 1,
5117 /* need_libopcodes_p */ 1,
5118 /* skip_p */ 0);
5119 break;
5120
5121 case AARCH64_OPND_ADDR_UIMM12:
5122 po_misc_or_fail (parse_address_reloc (&str, info));
5123 if (info->addr.pcrel || info->addr.offset.is_reg
5124 || !info->addr.preind || info->addr.writeback)
5125 {
5126 set_syntax_error (_("invalid addressing mode"));
5127 goto failure;
5128 }
5129 if (inst.reloc.type == BFD_RELOC_UNUSED)
5130 aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
5131 else if (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12)
5132 inst.reloc.type = ldst_lo12_determine_real_reloc_type ();
5133 /* Leave qualifier to be determined by libopcodes. */
5134 break;
5135
5136 case AARCH64_OPND_SIMD_ADDR_POST:
5137 /* [<Xn|SP>], <Xm|#<amount>> */
5138 po_misc_or_fail (parse_address (&str, info, 1));
5139 if (!info->addr.postind || !info->addr.writeback)
5140 {
5141 set_syntax_error (_("invalid addressing mode"));
5142 goto failure;
5143 }
5144 if (!info->addr.offset.is_reg)
5145 {
5146 if (inst.reloc.exp.X_op == O_constant)
5147 info->addr.offset.imm = inst.reloc.exp.X_add_number;
5148 else
5149 {
5150 set_fatal_syntax_error
5151 (_("writeback value should be an immediate constant"));
5152 goto failure;
5153 }
5154 }
5155 /* No qualifier. */
5156 break;
5157
5158 case AARCH64_OPND_SYSREG:
a3251895
YZ		 5159 if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1))
5160 == PARSE_FAIL)
a06ea964
NC		 5161 {
5162 set_syntax_error (_("unknown or missing system register name"));
5163 goto failure;
5164 }
5165 inst.base.operands[i].sysreg = val;
5166 break;
5167
5168 case AARCH64_OPND_PSTATEFIELD:
a3251895
YZ		 5169 if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0))
5170 == PARSE_FAIL)
a06ea964
NC		 5171 {
5172 set_syntax_error (_("unknown or missing PSTATE field name"));
5173 goto failure;
5174 }
5175 inst.base.operands[i].pstatefield = val;
5176 break;
5177
5178 case AARCH64_OPND_SYSREG_IC:
5179 inst.base.operands[i].sysins_op =
5180 parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh);
5181 goto sys_reg_ins;
5182 case AARCH64_OPND_SYSREG_DC:
5183 inst.base.operands[i].sysins_op =
5184 parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh);
5185 goto sys_reg_ins;
5186 case AARCH64_OPND_SYSREG_AT:
5187 inst.base.operands[i].sysins_op =
5188 parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh);
5189 goto sys_reg_ins;
5190 case AARCH64_OPND_SYSREG_TLBI:
5191 inst.base.operands[i].sysins_op =
5192 parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh);
5193sys_reg_ins:
5194 if (inst.base.operands[i].sysins_op == NULL)
5195 {
5196 set_fatal_syntax_error ( _("unknown or missing operation name"));
5197 goto failure;
5198 }
5199 break;
5200
5201 case AARCH64_OPND_BARRIER:
5202 case AARCH64_OPND_BARRIER_ISB:
5203 val = parse_barrier (&str);
5204 if (val != PARSE_FAIL
5205 && operands[i] == AARCH64_OPND_BARRIER_ISB && val != 0xf)
5206 {
5207 /* ISB only accepts options name 'sy'. */
5208 set_syntax_error
5209 (_("the specified option is not accepted in ISB"));
5210 /* Turn off backtrack as this optional operand is present. */
5211 backtrack_pos = 0;
5212 goto failure;
5213 }
5214 /* This is an extension to accept a 0..15 immediate. */
5215 if (val == PARSE_FAIL)
5216 po_imm_or_fail (0, 15);
5217 info->barrier = aarch64_barrier_options + val;
5218 break;
5219
5220 case AARCH64_OPND_PRFOP:
5221 val = parse_pldop (&str);
5222 /* This is an extension to accept a 0..31 immediate. */
5223 if (val == PARSE_FAIL)
5224 po_imm_or_fail (0, 31);
5225 inst.base.operands[i].prfop = aarch64_prfops + val;
5226 break;
5227
5228 default:
5229 as_fatal (_("unhandled operand code %d"), operands[i]);
5230 }
5231
5232 /* If we get here, this operand was successfully parsed. */
5233 inst.base.operands[i].present = 1;
5234 continue;
5235
5236failure:
5237 /* The parse routine should already have set the error, but in case
5238 not, set a default one here. */
5239 if (! error_p ())
5240 set_default_error ();
5241
5242 if (! backtrack_pos)
5243 goto parse_operands_return;
5244
5245 /* Reaching here means we are dealing with an optional operand that is
5246 omitted from the assembly line. */
5247 gas_assert (optional_operand_p (opcode, i));
5248 info->present = 0;
5249 process_omitted_operand (operands[i], opcode, i, info);
5250
5251 /* Try again, skipping the optional operand at backtrack_pos. */
5252 str = backtrack_pos;
5253 backtrack_pos = 0;
5254
5255 /* If this is the last operand that is optional and omitted, but without
5256 the presence of a comma. */
5257 if (i && comma_skipped_p && i == aarch64_num_of_operands (opcode) - 1)
5258 {
5259 set_fatal_syntax_error
5260 (_("unexpected comma before the omitted optional operand"));
5261 goto parse_operands_return;
5262 }
5263
5264 /* Clear any error record after the omitted optional operand has been
5265 successfully handled. */
5266 clear_error ();
5267 }
5268
5269 /* Check if we have parsed all the operands. */
5270 if (*str != '\0' && ! error_p ())
5271 {
5272 /* Set I to the index of the last present operand; this is
5273 for the purpose of diagnostics. */
5274 for (i -= 1; i >= 0 && !inst.base.operands[i].present; --i)
5275 ;
5276 set_fatal_syntax_error
5277 (_("unexpected characters following instruction"));
5278 }
5279
5280parse_operands_return:
5281
5282 if (error_p ())
5283 {
5284 DEBUG_TRACE ("parsing FAIL: %s - %s",
5285 operand_mismatch_kind_names[get_error_kind ()],
5286 get_error_message ());
5287 /* Record the operand error properly; this is useful when there
5288 are multiple instruction templates for a mnemonic name, so that
5289 later on, we can select the error that most closely describes
5290 the problem. */
5291 record_operand_error (opcode, i, get_error_kind (),
5292 get_error_message ());
5293 return FALSE;
5294 }
5295 else
5296 {
5297 DEBUG_TRACE ("parsing SUCCESS");
5298 return TRUE;
5299 }
5300}
5301
5302/* It does some fix-up to provide some programmer friendly feature while
5303 keeping the libopcodes happy, i.e. libopcodes only accepts
5304 the preferred architectural syntax.
5305 Return FALSE if there is any failure; otherwise return TRUE. */
5306
5307static bfd_boolean
5308programmer_friendly_fixup (aarch64_instruction *instr)
5309{
5310 aarch64_inst *base = &instr->base;
5311 const aarch64_opcode *opcode = base->opcode;
5312 enum aarch64_op op = opcode->op;
5313 aarch64_opnd_info *operands = base->operands;
5314
5315 DEBUG_TRACE ("enter");
5316
5317 switch (opcode->iclass)
5318 {
5319 case testbranch:
5320 /* TBNZ Xn|Wn, #uimm6, label
5321 Test and Branch Not Zero: conditionally jumps to label if bit number
5322 uimm6 in register Xn is not zero. The bit number implies the width of
5323 the register, which may be written and should be disassembled as Wn if
5324 uimm is less than 32. */
5325 if (operands[0].qualifier == AARCH64_OPND_QLF_W)
5326 {
5327 if (operands[1].imm.value >= 32)
5328 {
5329 record_operand_out_of_range_error (opcode, 1, _("immediate value"),
5330 0, 31);
5331 return FALSE;
5332 }
5333 operands[0].qualifier = AARCH64_OPND_QLF_X;
5334 }
5335 break;
5336 case loadlit:
5337 /* LDR Wt, label | =value
5338 As a convenience assemblers will typically permit the notation
5339 "=value" in conjunction with the pc-relative literal load instructions
5340 to automatically place an immediate value or symbolic address in a
5341 nearby literal pool and generate a hidden label which references it.
5342 ISREG has been set to 0 in the case of =value. */
5343 if (instr->gen_lit_pool
5344 && (op == OP_LDR_LIT || op == OP_LDRV_LIT || op == OP_LDRSW_LIT))
5345 {
5346 int size = aarch64_get_qualifier_esize (operands[0].qualifier);
5347 if (op == OP_LDRSW_LIT)
5348 size = 4;
5349 if (instr->reloc.exp.X_op != O_constant
67a32447 5350 && instr->reloc.exp.X_op != O_big
a06ea964
NC		 5351 && instr->reloc.exp.X_op != O_symbol)
5352 {
5353 record_operand_error (opcode, 1,
5354 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
5355 _("constant expression expected"));
5356 return FALSE;
5357 }
5358 if (! add_to_lit_pool (&instr->reloc.exp, size))
5359 {
5360 record_operand_error (opcode, 1,
5361 AARCH64_OPDE_OTHER_ERROR,
5362 _("literal pool insertion failed"));
5363 return FALSE;
5364 }
5365 }
5366 break;
a06ea964
NC		 5367 case log_shift:
5368 case bitfield:
5369 /* UXT[BHW] Wd, Wn
5370 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5371 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5372 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5373 A programmer-friendly assembler should accept a destination Xd in
5374 place of Wd, however that is not the preferred form for disassembly.
5375 */
5376 if ((op == OP_UXTB || op == OP_UXTH || op == OP_UXTW)
5377 && operands[1].qualifier == AARCH64_OPND_QLF_W
5378 && operands[0].qualifier == AARCH64_OPND_QLF_X)
5379 operands[0].qualifier = AARCH64_OPND_QLF_W;
5380 break;
5381
5382 case addsub_ext:
5383 {
5384 /* In the 64-bit form, the final register operand is written as Wm
5385 for all but the (possibly omitted) UXTX/LSL and SXTX
5386 operators.
5387 As a programmer-friendly assembler, we accept e.g.
5388 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5389 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5390 int idx = aarch64_operand_index (opcode->operands,
5391 AARCH64_OPND_Rm_EXT);
5392 gas_assert (idx == 1 || idx == 2);
5393 if (operands[0].qualifier == AARCH64_OPND_QLF_X
5394 && operands[idx].qualifier == AARCH64_OPND_QLF_X
5395 && operands[idx].shifter.kind != AARCH64_MOD_LSL
5396 && operands[idx].shifter.kind != AARCH64_MOD_UXTX
5397 && operands[idx].shifter.kind != AARCH64_MOD_SXTX)
5398 operands[idx].qualifier = AARCH64_OPND_QLF_W;
5399 }
5400 break;
5401
5402 default:
5403 break;
5404 }
5405
5406 DEBUG_TRACE ("exit with SUCCESS");
5407 return TRUE;
5408}
5409
5410/* A wrapper function to interface with libopcodes on encoding and
5411 record the error message if there is any.
5412
5413 Return TRUE on success; otherwise return FALSE. */
5414
5415static bfd_boolean
5416do_encode (const aarch64_opcode *opcode, aarch64_inst *instr,
5417 aarch64_insn *code)
5418{
5419 aarch64_operand_error error_info;
5420 error_info.kind = AARCH64_OPDE_NIL;
5421 if (aarch64_opcode_encode (opcode, instr, code, NULL, &error_info))
5422 return TRUE;
5423 else
5424 {
5425 gas_assert (error_info.kind != AARCH64_OPDE_NIL);
5426 record_operand_error_info (opcode, &error_info);
5427 return FALSE;
5428 }
5429}
5430
5431#ifdef DEBUG_AARCH64
5432static inline void
5433dump_opcode_operands (const aarch64_opcode *opcode)
5434{
5435 int i = 0;
5436 while (opcode->operands[i] != AARCH64_OPND_NIL)
5437 {
5438 aarch64_verbose ("\t\t opnd%d: %s", i,
5439 aarch64_get_operand_name (opcode->operands[i])[0] != '\0'
5440 ? aarch64_get_operand_name (opcode->operands[i])
5441 : aarch64_get_operand_desc (opcode->operands[i]));
5442 ++i;
5443 }
5444}
5445#endif /* DEBUG_AARCH64 */
5446
5447/* This is the guts of the machine-dependent assembler. STR points to a
5448 machine dependent instruction. This function is supposed to emit
5449 the frags/bytes it assembles to. */
5450
5451void
5452md_assemble (char *str)
5453{
5454 char *p = str;
5455 templates *template;
5456 aarch64_opcode *opcode;
5457 aarch64_inst *inst_base;
5458 unsigned saved_cond;
5459
5460 /* Align the previous label if needed. */
5461 if (last_label_seen != NULL)
5462 {
5463 symbol_set_frag (last_label_seen, frag_now);
5464 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
5465 S_SET_SEGMENT (last_label_seen, now_seg);
5466 }
5467
5468 inst.reloc.type = BFD_RELOC_UNUSED;
5469
5470 DEBUG_TRACE ("\n\n");
5471 DEBUG_TRACE ("==============================");
5472 DEBUG_TRACE ("Enter md_assemble with %s", str);
5473
5474 template = opcode_lookup (&p);
5475 if (!template)
5476 {
5477 /* It wasn't an instruction, but it might be a register alias of
5478 the form alias .req reg directive. */
5479 if (!create_register_alias (str, p))
5480 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str),
5481 str);
5482 return;
5483 }
5484
5485 skip_whitespace (p);
5486 if (*p == ',')
5487 {
5488 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
5489 get_mnemonic_name (str), str);
5490 return;
5491 }
5492
5493 init_operand_error_report ();
5494
5495 saved_cond = inst.cond;
5496 reset_aarch64_instruction (&inst);
5497 inst.cond = saved_cond;
5498
5499 /* Iterate through all opcode entries with the same mnemonic name. */
5500 do
5501 {
5502 opcode = template->opcode;
5503
5504 DEBUG_TRACE ("opcode %s found", opcode->name);
5505#ifdef DEBUG_AARCH64
5506 if (debug_dump)
5507 dump_opcode_operands (opcode);
5508#endif /* DEBUG_AARCH64 */
5509
5510 /* Check that this instruction is supported for this CPU. */
5511 if (!opcode->avariant
5512 || !AARCH64_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))
5513 {
5514 as_bad (_("selected processor does not support `%s'"), str);
5515 return;
5516 }
5517
5518 mapping_state (MAP_INSN);
5519
5520 inst_base = &inst.base;
5521 inst_base->opcode = opcode;
5522
5523 /* Truly conditionally executed instructions, e.g. b.cond. */
5524 if (opcode->flags & F_COND)
5525 {
5526 gas_assert (inst.cond != COND_ALWAYS);
5527 inst_base->cond = get_cond_from_value (inst.cond);
5528 DEBUG_TRACE ("condition found %s", inst_base->cond->names[0]);
5529 }
5530 else if (inst.cond != COND_ALWAYS)
5531 {
5532 /* It shouldn't arrive here, where the assembly looks like a
5533 conditional instruction but the found opcode is unconditional. */
5534 gas_assert (0);
5535 continue;
5536 }
5537
5538 if (parse_operands (p, opcode)
5539 && programmer_friendly_fixup (&inst)
5540 && do_encode (inst_base->opcode, &inst.base, &inst_base->value))
5541 {
5542 if (inst.reloc.type == BFD_RELOC_UNUSED
5543 || !inst.reloc.need_libopcodes_p)
5544 output_inst (NULL);
5545 else
5546 {
5547 /* If there is relocation generated for the instruction,
5548 store the instruction information for the future fix-up. */
5549 struct aarch64_inst *copy;
5550 gas_assert (inst.reloc.type != BFD_RELOC_UNUSED);
5551 if ((copy = xmalloc (sizeof (struct aarch64_inst))) == NULL)
5552 abort ();
5553 memcpy (copy, &inst.base, sizeof (struct aarch64_inst));
5554 output_inst (copy);
5555 }
5556 return;
5557 }
5558
5559 template = template->next;
5560 if (template != NULL)
5561 {
5562 reset_aarch64_instruction (&inst);
5563 inst.cond = saved_cond;
5564 }
5565 }
5566 while (template != NULL);
5567
5568 /* Issue the error messages if any. */
5569 output_operand_error_report (str);
5570}
5571
5572/* Various frobbings of labels and their addresses. */
5573
5574void
5575aarch64_start_line_hook (void)
5576{
5577 last_label_seen = NULL;
5578}
5579
5580void
5581aarch64_frob_label (symbolS * sym)
5582{
5583 last_label_seen = sym;
5584
5585 dwarf2_emit_label (sym);
5586}
5587
5588int
5589aarch64_data_in_code (void)
5590{
5591 if (!strncmp (input_line_pointer + 1, "data:", 5))
5592 {
5593 *input_line_pointer = '/';
5594 input_line_pointer += 5;
5595 *input_line_pointer = 0;
5596 return 1;
5597 }
5598
5599 return 0;
5600}
5601
5602char *
5603aarch64_canonicalize_symbol_name (char *name)
5604{
5605 int len;
5606
5607 if ((len = strlen (name)) > 5 && streq (name + len - 5, "/data"))
5608 *(name + len - 5) = 0;
5609
5610 return name;
5611}
5612\f
5613/* Table of all register names defined by default. The user can
5614 define additional names with .req. Note that all register names
5615 should appear in both upper and lowercase variants. Some registers
5616 also have mixed-case names. */
5617
5618#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
5619#define REGNUM(p,n,t) REGDEF(p##n, n, t)
5620#define REGSET31(p,t) \
5621 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
5622 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
5623 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
5624 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
5625 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
5626 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
5627 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
5628 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
5629#define REGSET(p,t) \
5630 REGSET31(p,t), REGNUM(p,31,t)
5631
5632/* These go into aarch64_reg_hsh hash-table. */
5633static const reg_entry reg_names[] = {
5634 /* Integer registers. */
5635 REGSET31 (x, R_64), REGSET31 (X, R_64),
5636 REGSET31 (w, R_32), REGSET31 (W, R_32),
5637
5638 REGDEF (wsp, 31, SP_32), REGDEF (WSP, 31, SP_32),
5639 REGDEF (sp, 31, SP_64), REGDEF (SP, 31, SP_64),
5640
5641 REGDEF (wzr, 31, Z_32), REGDEF (WZR, 31, Z_32),
5642 REGDEF (xzr, 31, Z_64), REGDEF (XZR, 31, Z_64),
5643
5644 /* Coprocessor register numbers. */
5645 REGSET (c, CN), REGSET (C, CN),
5646
5647 /* Floating-point single precision registers. */
5648 REGSET (s, FP_S), REGSET (S, FP_S),
5649
5650 /* Floating-point double precision registers. */
5651 REGSET (d, FP_D), REGSET (D, FP_D),
5652
5653 /* Floating-point half precision registers. */
5654 REGSET (h, FP_H), REGSET (H, FP_H),
5655
5656 /* Floating-point byte precision registers. */
5657 REGSET (b, FP_B), REGSET (B, FP_B),
5658
5659 /* Floating-point quad precision registers. */
5660 REGSET (q, FP_Q), REGSET (Q, FP_Q),
5661
5662 /* FP/SIMD registers. */
5663 REGSET (v, VN), REGSET (V, VN),
5664};
5665
5666#undef REGDEF
5667#undef REGNUM
5668#undef REGSET
5669
5670#define N 1
5671#define n 0
5672#define Z 1
5673#define z 0
5674#define C 1
5675#define c 0
5676#define V 1
5677#define v 0
5678#define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
5679static const asm_nzcv nzcv_names[] = {
5680 {"nzcv", B (n, z, c, v)},
5681 {"nzcV", B (n, z, c, V)},
5682 {"nzCv", B (n, z, C, v)},
5683 {"nzCV", B (n, z, C, V)},
5684 {"nZcv", B (n, Z, c, v)},
5685 {"nZcV", B (n, Z, c, V)},
5686 {"nZCv", B (n, Z, C, v)},
5687 {"nZCV", B (n, Z, C, V)},
5688 {"Nzcv", B (N, z, c, v)},
5689 {"NzcV", B (N, z, c, V)},
5690 {"NzCv", B (N, z, C, v)},
5691 {"NzCV", B (N, z, C, V)},
5692 {"NZcv", B (N, Z, c, v)},
5693 {"NZcV", B (N, Z, c, V)},
5694 {"NZCv", B (N, Z, C, v)},
5695 {"NZCV", B (N, Z, C, V)}
5696};
5697
5698#undef N
5699#undef n
5700#undef Z
5701#undef z
5702#undef C
5703#undef c
5704#undef V
5705#undef v
5706#undef B
5707\f
5708/* MD interface: bits in the object file. */
5709
5710/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5711 for use in the a.out file, and stores them in the array pointed to by buf.
5712 This knows about the endian-ness of the target machine and does
5713 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5714 2 (short) and 4 (long) Floating numbers are put out as a series of
5715 LITTLENUMS (shorts, here at least). */
5716
5717void
5718md_number_to_chars (char *buf, valueT val, int n)
5719{
5720 if (target_big_endian)
5721 number_to_chars_bigendian (buf, val, n);
5722 else
5723 number_to_chars_littleendian (buf, val, n);
5724}
5725
5726/* MD interface: Sections. */
5727
5728/* Estimate the size of a frag before relaxing. Assume everything fits in
5729 4 bytes. */
5730
5731int
5732md_estimate_size_before_relax (fragS * fragp, segT segtype ATTRIBUTE_UNUSED)
5733{
5734 fragp->fr_var = 4;
5735 return 4;
5736}
5737
5738/* Round up a section size to the appropriate boundary. */
5739
5740valueT
5741md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
5742{
5743 return size;
5744}
5745
5746/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
5747 of an rs_align_code fragment. */
5748
5749void
5750aarch64_handle_align (fragS * fragP)
5751{
5752 /* NOP = d503201f */
5753 /* AArch64 instructions are always little-endian. */
5754 static char const aarch64_noop[4] = { 0x1f, 0x20, 0x03, 0xd5 };
5755
5756 int bytes, fix, noop_size;
5757 char *p;
5758 const char *noop;
5759
5760 if (fragP->fr_type != rs_align_code)
5761 return;
5762
5763 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
5764 p = fragP->fr_literal + fragP->fr_fix;
5765 fix = 0;
5766
5767 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
5768 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
5769
5770#ifdef OBJ_ELF
5771 gas_assert (fragP->tc_frag_data.recorded);
5772#endif
5773
5774 noop = aarch64_noop;
5775 noop_size = sizeof (aarch64_noop);
5776 fragP->fr_var = noop_size;
5777
5778 if (bytes & (noop_size - 1))
5779 {
5780 fix = bytes & (noop_size - 1);
5781#ifdef OBJ_ELF
5782 insert_data_mapping_symbol (MAP_INSN, fragP->fr_fix, fragP, fix);
5783#endif
5784 memset (p, 0, fix);
5785 p += fix;
5786 bytes -= fix;
5787 }
5788
5789 while (bytes >= noop_size)
5790 {
5791 memcpy (p, noop, noop_size);
5792 p += noop_size;
5793 bytes -= noop_size;
5794 fix += noop_size;
5795 }
5796
5797 fragP->fr_fix += fix;
5798}
5799
5800/* Called from md_do_align. Used to create an alignment
5801 frag in a code section. */
5802
5803void
5804aarch64_frag_align_code (int n, int max)
5805{
5806 char *p;
5807
5808 /* We assume that there will never be a requirement
5809 to support alignments greater than x bytes. */
5810 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
5811 as_fatal (_
5812 ("alignments greater than %d bytes not supported in .text sections"),
5813 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
5814
5815 p = frag_var (rs_align_code,
5816 MAX_MEM_FOR_RS_ALIGN_CODE,
5817 1,
5818 (relax_substateT) max,
5819 (symbolS *) NULL, (offsetT) n, (char *) NULL);
5820 *p = 0;
5821}
5822
5823/* Perform target specific initialisation of a frag.
5824 Note - despite the name this initialisation is not done when the frag
5825 is created, but only when its type is assigned. A frag can be created
5826 and used a long time before its type is set, so beware of assuming that
5827 this initialisationis performed first. */
5828
5829#ifndef OBJ_ELF
5830void
5831aarch64_init_frag (fragS * fragP ATTRIBUTE_UNUSED,
5832 int max_chars ATTRIBUTE_UNUSED)
5833{
5834}
5835
5836#else /* OBJ_ELF is defined. */
5837void
5838aarch64_init_frag (fragS * fragP, int max_chars)
5839{
5840 /* Record a mapping symbol for alignment frags. We will delete this
5841 later if the alignment ends up empty. */
5842 if (!fragP->tc_frag_data.recorded)
5843 {
5844 fragP->tc_frag_data.recorded = 1;
5845 switch (fragP->fr_type)
5846 {
5847 case rs_align:
5848 case rs_align_test:
5849 case rs_fill:
5850 mapping_state_2 (MAP_DATA, max_chars);
5851 break;
5852 case rs_align_code:
5853 mapping_state_2 (MAP_INSN, max_chars);
5854 break;
5855 default:
5856 break;
5857 }
5858 }
5859}
5860\f
5861/* Initialize the DWARF-2 unwind information for this procedure. */
5862
5863void
5864tc_aarch64_frame_initial_instructions (void)
5865{
5866 cfi_add_CFA_def_cfa (REG_SP, 0);
5867}
5868#endif /* OBJ_ELF */
5869
5870/* Convert REGNAME to a DWARF-2 register number. */
5871
5872int
5873tc_aarch64_regname_to_dw2regnum (char *regname)
5874{
5875 const reg_entry *reg = parse_reg (&regname);
5876 if (reg == NULL)
5877 return -1;
5878
5879 switch (reg->type)
5880 {
5881 case REG_TYPE_SP_32:
5882 case REG_TYPE_SP_64:
5883 case REG_TYPE_R_32:
5884 case REG_TYPE_R_64:
5885 case REG_TYPE_FP_B:
5886 case REG_TYPE_FP_H:
5887 case REG_TYPE_FP_S:
5888 case REG_TYPE_FP_D:
5889 case REG_TYPE_FP_Q:
5890 return reg->number;
5891 default:
5892 break;
5893 }
5894 return -1;
5895}
5896
cec5225b
YZ		 5897/* Implement DWARF2_ADDR_SIZE. */
5898
5899int
5900aarch64_dwarf2_addr_size (void)
5901{
5902#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5903 if (ilp32_p)
5904 return 4;
5905#endif
5906 return bfd_arch_bits_per_address (stdoutput) / 8;
5907}
5908
a06ea964
NC		 5909/* MD interface: Symbol and relocation handling. */
5910
5911/* Return the address within the segment that a PC-relative fixup is
5912 relative to. For AArch64 PC-relative fixups applied to instructions
5913 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
5914
5915long
5916md_pcrel_from_section (fixS * fixP, segT seg)
5917{
5918 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
5919
5920 /* If this is pc-relative and we are going to emit a relocation
5921 then we just want to put out any pipeline compensation that the linker
5922 will need. Otherwise we want to use the calculated base. */
5923 if (fixP->fx_pcrel
5924 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
5925 || aarch64_force_relocation (fixP)))
5926 base = 0;
5927
5928 /* AArch64 should be consistent for all pc-relative relocations. */
5929 return base + AARCH64_PCREL_OFFSET;
5930}
5931
5932/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
5933 Otherwise we have no need to default values of symbols. */
5934
5935symbolS *
5936md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
5937{
5938#ifdef OBJ_ELF
5939 if (name[0] == '_' && name[1] == 'G'
5940 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
5941 {
5942 if (!GOT_symbol)
5943 {
5944 if (symbol_find (name))
5945 as_bad (_("GOT already in the symbol table"));
5946
5947 GOT_symbol = symbol_new (name, undefined_section,
5948 (valueT) 0, &zero_address_frag);
5949 }
5950
5951 return GOT_symbol;
5952 }
5953#endif
5954
5955 return 0;
5956}
5957
5958/* Return non-zero if the indicated VALUE has overflowed the maximum
5959 range expressible by a unsigned number with the indicated number of
5960 BITS. */
5961
5962static bfd_boolean
5963unsigned_overflow (valueT value, unsigned bits)
5964{
5965 valueT lim;
5966 if (bits >= sizeof (valueT) * 8)
5967 return FALSE;
5968 lim = (valueT) 1 << bits;
5969 return (value >= lim);
5970}
5971
5972
5973/* Return non-zero if the indicated VALUE has overflowed the maximum
5974 range expressible by an signed number with the indicated number of
5975 BITS. */
5976
5977static bfd_boolean
5978signed_overflow (offsetT value, unsigned bits)
5979{
5980 offsetT lim;
5981 if (bits >= sizeof (offsetT) * 8)
5982 return FALSE;
5983 lim = (offsetT) 1 << (bits - 1);
5984 return (value < -lim || value >= lim);
5985}
5986
5987/* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
5988 unsigned immediate offset load/store instruction, try to encode it as
5989 an unscaled, 9-bit, signed immediate offset load/store instruction.
5990 Return TRUE if it is successful; otherwise return FALSE.
5991
5992 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
5993 in response to the standard LDR/STR mnemonics when the immediate offset is
5994 unambiguous, i.e. when it is negative or unaligned. */
5995
5996static bfd_boolean
5997try_to_encode_as_unscaled_ldst (aarch64_inst *instr)
5998{
5999 int idx;
6000 enum aarch64_op new_op;
6001 const aarch64_opcode *new_opcode;
6002
6003 gas_assert (instr->opcode->iclass == ldst_pos);
6004
6005 switch (instr->opcode->op)
6006 {
6007 case OP_LDRB_POS:new_op = OP_LDURB; break;
6008 case OP_STRB_POS: new_op = OP_STURB; break;
6009 case OP_LDRSB_POS: new_op = OP_LDURSB; break;
6010 case OP_LDRH_POS: new_op = OP_LDURH; break;
6011 case OP_STRH_POS: new_op = OP_STURH; break;
6012 case OP_LDRSH_POS: new_op = OP_LDURSH; break;
6013 case OP_LDR_POS: new_op = OP_LDUR; break;
6014 case OP_STR_POS: new_op = OP_STUR; break;
6015 case OP_LDRF_POS: new_op = OP_LDURV; break;
6016 case OP_STRF_POS: new_op = OP_STURV; break;
6017 case OP_LDRSW_POS: new_op = OP_LDURSW; break;
6018 case OP_PRFM_POS: new_op = OP_PRFUM; break;
6019 default: new_op = OP_NIL; break;
6020 }
6021
6022 if (new_op == OP_NIL)
6023 return FALSE;
6024
6025 new_opcode = aarch64_get_opcode (new_op);
6026 gas_assert (new_opcode != NULL);
6027
6028 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6029 instr->opcode->op, new_opcode->op);
6030
6031 aarch64_replace_opcode (instr, new_opcode);
6032
6033 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6034 qualifier matching may fail because the out-of-date qualifier will
6035 prevent the operand being updated with a new and correct qualifier. */
6036 idx = aarch64_operand_index (instr->opcode->operands,
6037 AARCH64_OPND_ADDR_SIMM9);
6038 gas_assert (idx == 1);
6039 instr->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
6040
6041 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6042
6043 if (!aarch64_opcode_encode (instr->opcode, instr, &instr->value, NULL, NULL))
6044 return FALSE;
6045
6046 return TRUE;
6047}
6048
6049/* Called by fix_insn to fix a MOV immediate alias instruction.
6050
6051 Operand for a generic move immediate instruction, which is an alias
6052 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6053 a 32-bit/64-bit immediate value into general register. An assembler error
6054 shall result if the immediate cannot be created by a single one of these
6055 instructions. If there is a choice, then to ensure reversability an
6056 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6057
6058static void
6059fix_mov_imm_insn (fixS *fixP, char *buf, aarch64_inst *instr, offsetT value)
6060{
6061 const aarch64_opcode *opcode;
6062
6063 /* Need to check if the destination is SP/ZR. The check has to be done
6064 before any aarch64_replace_opcode. */
6065 int try_mov_wide_p = !aarch64_stack_pointer_p (&instr->operands[0]);
6066 int try_mov_bitmask_p = !aarch64_zero_register_p (&instr->operands[0]);
6067
6068 instr->operands[1].imm.value = value;
6069 instr->operands[1].skip = 0;
6070
6071 if (try_mov_wide_p)
6072 {
6073 /* Try the MOVZ alias. */
6074 opcode = aarch64_get_opcode (OP_MOV_IMM_WIDE);
6075 aarch64_replace_opcode (instr, opcode);
6076 if (aarch64_opcode_encode (instr->opcode, instr,
6077 &instr->value, NULL, NULL))
6078 {
6079 put_aarch64_insn (buf, instr->value);
6080 return;
6081 }
6082 /* Try the MOVK alias. */
6083 opcode = aarch64_get_opcode (OP_MOV_IMM_WIDEN);
6084 aarch64_replace_opcode (instr, opcode);
6085 if (aarch64_opcode_encode (instr->opcode, instr,
6086 &instr->value, NULL, NULL))
6087 {
6088 put_aarch64_insn (buf, instr->value);
6089 return;
6090 }
6091 }
6092
6093 if (try_mov_bitmask_p)
6094 {
6095 /* Try the ORR alias. */
6096 opcode = aarch64_get_opcode (OP_MOV_IMM_LOG);
6097 aarch64_replace_opcode (instr, opcode);
6098 if (aarch64_opcode_encode (instr->opcode, instr,
6099 &instr->value, NULL, NULL))
6100 {
6101 put_aarch64_insn (buf, instr->value);
6102 return;
6103 }
6104 }
6105
6106 as_bad_where (fixP->fx_file, fixP->fx_line,
6107 _("immediate cannot be moved by a single instruction"));
6108}
6109
6110/* An instruction operand which is immediate related may have symbol used
6111 in the assembly, e.g.
6112
6113 mov w0, u32
6114 .set u32, 0x00ffff00
6115
6116 At the time when the assembly instruction is parsed, a referenced symbol,
6117 like 'u32' in the above example may not have been seen; a fixS is created
6118 in such a case and is handled here after symbols have been resolved.
6119 Instruction is fixed up with VALUE using the information in *FIXP plus
6120 extra information in FLAGS.
6121
6122 This function is called by md_apply_fix to fix up instructions that need
6123 a fix-up described above but does not involve any linker-time relocation. */
6124
6125static void
6126fix_insn (fixS *fixP, uint32_t flags, offsetT value)
6127{
6128 int idx;
6129 uint32_t insn;
6130 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
6131 enum aarch64_opnd opnd = fixP->tc_fix_data.opnd;
6132 aarch64_inst *new_inst = fixP->tc_fix_data.inst;
6133
6134 if (new_inst)
6135 {
6136 /* Now the instruction is about to be fixed-up, so the operand that
6137 was previously marked as 'ignored' needs to be unmarked in order
6138 to get the encoding done properly. */
6139 idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
6140 new_inst->operands[idx].skip = 0;
6141 }
6142
6143 gas_assert (opnd != AARCH64_OPND_NIL);
6144
6145 switch (opnd)
6146 {
6147 case AARCH64_OPND_EXCEPTION:
6148 if (unsigned_overflow (value, 16))
6149 as_bad_where (fixP->fx_file, fixP->fx_line,
6150 _("immediate out of range"));
6151 insn = get_aarch64_insn (buf);
6152 insn |= encode_svc_imm (value);
6153 put_aarch64_insn (buf, insn);
6154 break;
6155
6156 case AARCH64_OPND_AIMM:
6157 /* ADD or SUB with immediate.
6158 NOTE this assumes we come here with a add/sub shifted reg encoding
6159 3 322|2222|2 2 2 21111 111111
6160 1 098|7654|3 2 1 09876 543210 98765 43210
6161 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6162 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6163 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6164 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6165 ->
6166 3 322|2222|2 2 221111111111
6167 1 098|7654|3 2 109876543210 98765 43210
6168 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6169 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6170 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6171 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6172 Fields sf Rn Rd are already set. */
6173 insn = get_aarch64_insn (buf);
6174 if (value < 0)
6175 {
6176 /* Add <-> sub. */
6177 insn = reencode_addsub_switch_add_sub (insn);
6178 value = -value;
6179 }
6180
6181 if ((flags & FIXUP_F_HAS_EXPLICIT_SHIFT) == 0
6182 && unsigned_overflow (value, 12))
6183 {
6184 /* Try to shift the value by 12 to make it fit. */
6185 if (((value >> 12) << 12) == value
6186 && ! unsigned_overflow (value, 12 + 12))
6187 {
6188 value >>= 12;
6189 insn |= encode_addsub_imm_shift_amount (1);
6190 }
6191 }
6192
6193 if (unsigned_overflow (value, 12))
6194 as_bad_where (fixP->fx_file, fixP->fx_line,
6195 _("immediate out of range"));
6196
6197 insn |= encode_addsub_imm (value);
6198
6199 put_aarch64_insn (buf, insn);
6200 break;
6201
6202 case AARCH64_OPND_SIMD_IMM:
6203 case AARCH64_OPND_SIMD_IMM_SFT:
6204 case AARCH64_OPND_LIMM:
6205 /* Bit mask immediate. */
6206 gas_assert (new_inst != NULL);
6207 idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
6208 new_inst->operands[idx].imm.value = value;
6209 if (aarch64_opcode_encode (new_inst->opcode, new_inst,
6210 &new_inst->value, NULL, NULL))
6211 put_aarch64_insn (buf, new_inst->value);
6212 else
6213 as_bad_where (fixP->fx_file, fixP->fx_line,
6214 _("invalid immediate"));
6215 break;
6216
6217 case AARCH64_OPND_HALF:
6218 /* 16-bit unsigned immediate. */
6219 if (unsigned_overflow (value, 16))
6220 as_bad_where (fixP->fx_file, fixP->fx_line,
6221 _("immediate out of range"));
6222 insn = get_aarch64_insn (buf);
6223 insn |= encode_movw_imm (value & 0xffff);
6224 put_aarch64_insn (buf, insn);
6225 break;
6226
6227 case AARCH64_OPND_IMM_MOV:
6228 /* Operand for a generic move immediate instruction, which is
6229 an alias instruction that generates a single MOVZ, MOVN or ORR
6230 instruction to loads a 32-bit/64-bit immediate value into general
6231 register. An assembler error shall result if the immediate cannot be
6232 created by a single one of these instructions. If there is a choice,
6233 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6234 and MOVZ or MOVN to ORR. */
6235 gas_assert (new_inst != NULL);
6236 fix_mov_imm_insn (fixP, buf, new_inst, value);
6237 break;
6238
6239 case AARCH64_OPND_ADDR_SIMM7:
6240 case AARCH64_OPND_ADDR_SIMM9:
6241 case AARCH64_OPND_ADDR_SIMM9_2:
6242 case AARCH64_OPND_ADDR_UIMM12:
6243 /* Immediate offset in an address. */
6244 insn = get_aarch64_insn (buf);
6245
6246 gas_assert (new_inst != NULL && new_inst->value == insn);
6247 gas_assert (new_inst->opcode->operands[1] == opnd
6248 || new_inst->opcode->operands[2] == opnd);
6249
6250 /* Get the index of the address operand. */
6251 if (new_inst->opcode->operands[1] == opnd)
6252 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6253 idx = 1;
6254 else
6255 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6256 idx = 2;
6257
6258 /* Update the resolved offset value. */
6259 new_inst->operands[idx].addr.offset.imm = value;
6260
6261 /* Encode/fix-up. */
6262 if (aarch64_opcode_encode (new_inst->opcode, new_inst,
6263 &new_inst->value, NULL, NULL))
6264 {
6265 put_aarch64_insn (buf, new_inst->value);
6266 break;
6267 }
6268 else if (new_inst->opcode->iclass == ldst_pos
6269 && try_to_encode_as_unscaled_ldst (new_inst))
6270 {
6271 put_aarch64_insn (buf, new_inst->value);
6272 break;
6273 }
6274
6275 as_bad_where (fixP->fx_file, fixP->fx_line,
6276 _("immediate offset out of range"));
6277 break;
6278
6279 default:
6280 gas_assert (0);
6281 as_fatal (_("unhandled operand code %d"), opnd);
6282 }
6283}
6284
6285/* Apply a fixup (fixP) to segment data, once it has been determined
6286 by our caller that we have all the info we need to fix it up.
6287
6288 Parameter valP is the pointer to the value of the bits. */
6289
6290void
6291md_apply_fix (fixS * fixP, valueT * valP, segT seg)
6292{
6293 offsetT value = *valP;
6294 uint32_t insn;
6295 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
6296 int scale;
6297 unsigned flags = fixP->fx_addnumber;
6298
6299 DEBUG_TRACE ("\n\n");
6300 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6301 DEBUG_TRACE ("Enter md_apply_fix");
6302
6303 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
6304
6305 /* Note whether this will delete the relocation. */
6306
6307 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
6308 fixP->fx_done = 1;
6309
6310 /* Process the relocations. */
6311 switch (fixP->fx_r_type)
6312 {
6313 case BFD_RELOC_NONE:
6314 /* This will need to go in the object file. */
6315 fixP->fx_done = 0;
6316 break;
6317
6318 case BFD_RELOC_8:
6319 case BFD_RELOC_8_PCREL:
6320 if (fixP->fx_done || !seg->use_rela_p)
6321 md_number_to_chars (buf, value, 1);
6322 break;
6323
6324 case BFD_RELOC_16:
6325 case BFD_RELOC_16_PCREL:
6326 if (fixP->fx_done || !seg->use_rela_p)
6327 md_number_to_chars (buf, value, 2);
6328 break;
6329
6330 case BFD_RELOC_32:
6331 case BFD_RELOC_32_PCREL:
6332 if (fixP->fx_done || !seg->use_rela_p)
6333 md_number_to_chars (buf, value, 4);
6334 break;
6335
6336 case BFD_RELOC_64:
6337 case BFD_RELOC_64_PCREL:
6338 if (fixP->fx_done || !seg->use_rela_p)
6339 md_number_to_chars (buf, value, 8);
6340 break;
6341
6342 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
6343 /* We claim that these fixups have been processed here, even if
6344 in fact we generate an error because we do not have a reloc
6345 for them, so tc_gen_reloc() will reject them. */
6346 fixP->fx_done = 1;
6347 if (fixP->fx_addsy && !S_IS_DEFINED (fixP->fx_addsy))
6348 {
6349 as_bad_where (fixP->fx_file, fixP->fx_line,
6350 _("undefined symbol %s used as an immediate value"),
6351 S_GET_NAME (fixP->fx_addsy));
6352 goto apply_fix_return;
6353 }
6354 fix_insn (fixP, flags, value);
6355 break;
6356
6357 case BFD_RELOC_AARCH64_LD_LO19_PCREL:
a06ea964
NC		 6358 if (fixP->fx_done || !seg->use_rela_p)
6359 {
89d2a2a3
MS		 6360 if (value & 3)
6361 as_bad_where (fixP->fx_file, fixP->fx_line,
6362 _("pc-relative load offset not word aligned"));
6363 if (signed_overflow (value, 21))
6364 as_bad_where (fixP->fx_file, fixP->fx_line,
6365 _("pc-relative load offset out of range"));
a06ea964
NC		 6366 insn = get_aarch64_insn (buf);
6367 insn |= encode_ld_lit_ofs_19 (value >> 2);
6368 put_aarch64_insn (buf, insn);
6369 }
6370 break;
6371
6372 case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
a06ea964
NC		 6373 if (fixP->fx_done || !seg->use_rela_p)
6374 {
89d2a2a3
MS		 6375 if (signed_overflow (value, 21))
6376 as_bad_where (fixP->fx_file, fixP->fx_line,
6377 _("pc-relative address offset out of range"));
a06ea964
NC		 6378 insn = get_aarch64_insn (buf);
6379 insn |= encode_adr_imm (value);
6380 put_aarch64_insn (buf, insn);
6381 }
6382 break;
6383
6384 case BFD_RELOC_AARCH64_BRANCH19:
a06ea964
NC		 6385 if (fixP->fx_done || !seg->use_rela_p)
6386 {
89d2a2a3
MS		 6387 if (value & 3)
6388 as_bad_where (fixP->fx_file, fixP->fx_line,
6389 _("conditional branch target not word aligned"));
6390 if (signed_overflow (value, 21))
6391 as_bad_where (fixP->fx_file, fixP->fx_line,
6392 _("conditional branch out of range"));
a06ea964
NC		 6393 insn = get_aarch64_insn (buf);
6394 insn |= encode_cond_branch_ofs_19 (value >> 2);
6395 put_aarch64_insn (buf, insn);
6396 }
6397 break;
6398
6399 case BFD_RELOC_AARCH64_TSTBR14:
a06ea964
NC		 6400 if (fixP->fx_done || !seg->use_rela_p)
6401 {
89d2a2a3
MS		 6402 if (value & 3)
6403 as_bad_where (fixP->fx_file, fixP->fx_line,
6404 _("conditional branch target not word aligned"));
6405 if (signed_overflow (value, 16))
6406 as_bad_where (fixP->fx_file, fixP->fx_line,
6407 _("conditional branch out of range"));
a06ea964
NC		 6408 insn = get_aarch64_insn (buf);
6409 insn |= encode_tst_branch_ofs_14 (value >> 2);
6410 put_aarch64_insn (buf, insn);
6411 }
6412 break;
6413
6414 case BFD_RELOC_AARCH64_JUMP26:
6415 case BFD_RELOC_AARCH64_CALL26:
a06ea964
NC		 6416 if (fixP->fx_done || !seg->use_rela_p)
6417 {
89d2a2a3
MS		 6418 if (value & 3)
6419 as_bad_where (fixP->fx_file, fixP->fx_line,
6420 _("branch target not word aligned"));
6421 if (signed_overflow (value, 28))
6422 as_bad_where (fixP->fx_file, fixP->fx_line,
6423 _("branch out of range"));
a06ea964
NC		 6424 insn = get_aarch64_insn (buf);
6425 insn |= encode_branch_ofs_26 (value >> 2);
6426 put_aarch64_insn (buf, insn);
6427 }
6428 break;
6429
6430 case BFD_RELOC_AARCH64_MOVW_G0:
6431 case BFD_RELOC_AARCH64_MOVW_G0_S:
6432 case BFD_RELOC_AARCH64_MOVW_G0_NC:
6433 scale = 0;
6434 goto movw_common;
6435 case BFD_RELOC_AARCH64_MOVW_G1:
6436 case BFD_RELOC_AARCH64_MOVW_G1_S:
6437 case BFD_RELOC_AARCH64_MOVW_G1_NC:
6438 scale = 16;
6439 goto movw_common;
6440 case BFD_RELOC_AARCH64_MOVW_G2:
6441 case BFD_RELOC_AARCH64_MOVW_G2_S:
6442 case BFD_RELOC_AARCH64_MOVW_G2_NC:
6443 scale = 32;
6444 goto movw_common;
6445 case BFD_RELOC_AARCH64_MOVW_G3:
6446 scale = 48;
6447 movw_common:
6448 if (fixP->fx_done || !seg->use_rela_p)
6449 {
6450 insn = get_aarch64_insn (buf);
6451
6452 if (!fixP->fx_done)
6453 {
6454 /* REL signed addend must fit in 16 bits */
6455 if (signed_overflow (value, 16))
6456 as_bad_where (fixP->fx_file, fixP->fx_line,
6457 _("offset out of range"));
6458 }
6459 else
6460 {
6461 /* Check for overflow and scale. */
6462 switch (fixP->fx_r_type)
6463 {
6464 case BFD_RELOC_AARCH64_MOVW_G0:
6465 case BFD_RELOC_AARCH64_MOVW_G1:
6466 case BFD_RELOC_AARCH64_MOVW_G2:
6467 case BFD_RELOC_AARCH64_MOVW_G3:
6468 if (unsigned_overflow (value, scale + 16))
6469 as_bad_where (fixP->fx_file, fixP->fx_line,
6470 _("unsigned value out of range"));
6471 break;
6472 case BFD_RELOC_AARCH64_MOVW_G0_S:
6473 case BFD_RELOC_AARCH64_MOVW_G1_S:
6474 case BFD_RELOC_AARCH64_MOVW_G2_S:
6475 /* NOTE: We can only come here with movz or movn. */
6476 if (signed_overflow (value, scale + 16))
6477 as_bad_where (fixP->fx_file, fixP->fx_line,
6478 _("signed value out of range"));
6479 if (value < 0)
6480 {
6481 /* Force use of MOVN. */
6482 value = ~value;
6483 insn = reencode_movzn_to_movn (insn);
6484 }
6485 else
6486 {
6487 /* Force use of MOVZ. */
6488 insn = reencode_movzn_to_movz (insn);
6489 }
6490 break;
6491 default:
6492 /* Unchecked relocations. */
6493 break;
6494 }
6495 value >>= scale;
6496 }
6497
6498 /* Insert value into MOVN/MOVZ/MOVK instruction. */
6499 insn |= encode_movw_imm (value & 0xffff);
6500
6501 put_aarch64_insn (buf, insn);
6502 }
6503 break;
6504
a6bb11b2
YZ		 6505 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC:
6506 fixP->fx_r_type = (ilp32_p
6507 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
6508 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC);
6509 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6510 /* Should always be exported to object file, see
6511 aarch64_force_relocation(). */
6512 gas_assert (!fixP->fx_done);
6513 gas_assert (seg->use_rela_p);
6514 break;
6515
6516 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC:
6517 fixP->fx_r_type = (ilp32_p
6518 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
6519 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC);
6520 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6521 /* Should always be exported to object file, see
6522 aarch64_force_relocation(). */
6523 gas_assert (!fixP->fx_done);
6524 gas_assert (seg->use_rela_p);
6525 break;
6526
2c0a3565
MS		 6527 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
6528 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
6529 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
6530 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
a06ea964 6531 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
2c0a3565 6532 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
a06ea964 6533 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
a6bb11b2 6534 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
2c0a3565 6535 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
a06ea964 6536 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
2c0a3565 6537 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
a06ea964 6538 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
a06ea964
NC		 6539 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
6540 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
2c0a3565
MS		 6541 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
6542 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
6543 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
a06ea964
NC		 6544 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6545 /* Should always be exported to object file, see
6546 aarch64_force_relocation(). */
6547 gas_assert (!fixP->fx_done);
6548 gas_assert (seg->use_rela_p);
6549 break;
6550
a6bb11b2
YZ		 6551 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC:
6552 /* Should always be exported to object file, see
6553 aarch64_force_relocation(). */
6554 fixP->fx_r_type = (ilp32_p
6555 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
6556 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC);
6557 gas_assert (!fixP->fx_done);
6558 gas_assert (seg->use_rela_p);
6559 break;
6560
a06ea964
NC		 6561 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
6562 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
6563 case BFD_RELOC_AARCH64_ADD_LO12:
6564 case BFD_RELOC_AARCH64_LDST8_LO12:
6565 case BFD_RELOC_AARCH64_LDST16_LO12:
6566 case BFD_RELOC_AARCH64_LDST32_LO12:
6567 case BFD_RELOC_AARCH64_LDST64_LO12:
6568 case BFD_RELOC_AARCH64_LDST128_LO12:
f41aef5f 6569 case BFD_RELOC_AARCH64_GOT_LD_PREL19:
a06ea964
NC		 6570 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
6571 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
a6bb11b2 6572 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
a06ea964
NC		 6573 /* Should always be exported to object file, see
6574 aarch64_force_relocation(). */
6575 gas_assert (!fixP->fx_done);
6576 gas_assert (seg->use_rela_p);
6577 break;
6578
6579 case BFD_RELOC_AARCH64_TLSDESC_ADD:
6580 case BFD_RELOC_AARCH64_TLSDESC_LDR:
6581 case BFD_RELOC_AARCH64_TLSDESC_CALL:
6582 break;
6583
6584 default:
6585 as_bad_where (fixP->fx_file, fixP->fx_line,
6586 _("unexpected %s fixup"),
6587 bfd_get_reloc_code_name (fixP->fx_r_type));
6588 break;
6589 }
6590
6591apply_fix_return:
6592 /* Free the allocated the struct aarch64_inst.
6593 N.B. currently there are very limited number of fix-up types actually use
6594 this field, so the impact on the performance should be minimal . */
6595 if (fixP->tc_fix_data.inst != NULL)
6596 free (fixP->tc_fix_data.inst);
6597
6598 return;
6599}
6600
6601/* Translate internal representation of relocation info to BFD target
6602 format. */
6603
6604arelent *
6605tc_gen_reloc (asection * section, fixS * fixp)
6606{
6607 arelent *reloc;
6608 bfd_reloc_code_real_type code;
6609
6610 reloc = xmalloc (sizeof (arelent));
6611
6612 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
6613 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6614 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
6615
6616 if (fixp->fx_pcrel)
6617 {
6618 if (section->use_rela_p)
6619 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
6620 else
6621 fixp->fx_offset = reloc->address;
6622 }
6623 reloc->addend = fixp->fx_offset;
6624
6625 code = fixp->fx_r_type;
6626 switch (code)
6627 {
6628 case BFD_RELOC_16:
6629 if (fixp->fx_pcrel)
6630 code = BFD_RELOC_16_PCREL;
6631 break;
6632
6633 case BFD_RELOC_32:
6634 if (fixp->fx_pcrel)
6635 code = BFD_RELOC_32_PCREL;
6636 break;
6637
6638 case BFD_RELOC_64:
6639 if (fixp->fx_pcrel)
6640 code = BFD_RELOC_64_PCREL;
6641 break;
6642
6643 default:
6644 break;
6645 }
6646
6647 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6648 if (reloc->howto == NULL)
6649 {
6650 as_bad_where (fixp->fx_file, fixp->fx_line,
6651 _
6652 ("cannot represent %s relocation in this object file format"),
6653 bfd_get_reloc_code_name (code));
6654 return NULL;
6655 }
6656
6657 return reloc;
6658}
6659
6660/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6661
6662void
6663cons_fix_new_aarch64 (fragS * frag, int where, int size, expressionS * exp)
6664{
6665 bfd_reloc_code_real_type type;
6666 int pcrel = 0;
6667
6668 /* Pick a reloc.
6669 FIXME: @@ Should look at CPU word size. */
6670 switch (size)
6671 {
6672 case 1:
6673 type = BFD_RELOC_8;
6674 break;
6675 case 2:
6676 type = BFD_RELOC_16;
6677 break;
6678 case 4:
6679 type = BFD_RELOC_32;
6680 break;
6681 case 8:
6682 type = BFD_RELOC_64;
6683 break;
6684 default:
6685 as_bad (_("cannot do %u-byte relocation"), size);
6686 type = BFD_RELOC_UNUSED;
6687 break;
6688 }
6689
6690 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
6691}
6692
6693int
6694aarch64_force_relocation (struct fix *fixp)
6695{
6696 switch (fixp->fx_r_type)
6697 {
6698 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
6699 /* Perform these "immediate" internal relocations
6700 even if the symbol is extern or weak. */
6701 return 0;
6702
a6bb11b2
YZ		 6703 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC:
6704 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC:
6705 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC:
6706 /* Pseudo relocs that need to be fixed up according to
6707 ilp32_p. */
6708 return 0;
6709
2c0a3565
MS		 6710 case BFD_RELOC_AARCH64_ADD_LO12:
6711 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
6712 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
6713 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
6714 case BFD_RELOC_AARCH64_GOT_LD_PREL19:
6715 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
6716 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
6717 case BFD_RELOC_AARCH64_LDST128_LO12:
6718 case BFD_RELOC_AARCH64_LDST16_LO12:
6719 case BFD_RELOC_AARCH64_LDST32_LO12:
6720 case BFD_RELOC_AARCH64_LDST64_LO12:
6721 case BFD_RELOC_AARCH64_LDST8_LO12:
6722 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
6723 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
6724 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
6725 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
a06ea964 6726 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
2c0a3565 6727 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
a06ea964 6728 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
a6bb11b2 6729 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
2c0a3565 6730 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
a06ea964 6731 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
2c0a3565 6732 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
a06ea964 6733 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
a06ea964
NC		 6734 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
6735 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
2c0a3565
MS		 6736 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
6737 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
6738 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
a06ea964
NC		 6739 /* Always leave these relocations for the linker. */
6740 return 1;
6741
6742 default:
6743 break;
6744 }
6745
6746 return generic_force_reloc (fixp);
6747}
6748
6749#ifdef OBJ_ELF
6750
6751const char *
6752elf64_aarch64_target_format (void)
6753{
6754 if (target_big_endian)
cec5225b 6755 return ilp32_p ? "elf32-bigaarch64" : "elf64-bigaarch64";
a06ea964 6756 else
cec5225b 6757 return ilp32_p ? "elf32-littleaarch64" : "elf64-littleaarch64";
a06ea964
NC		 6758}
6759
6760void
6761aarch64elf_frob_symbol (symbolS * symp, int *puntp)
6762{
6763 elf_frob_symbol (symp, puntp);
6764}
6765#endif
6766
6767/* MD interface: Finalization. */
6768
6769/* A good place to do this, although this was probably not intended
6770 for this kind of use. We need to dump the literal pool before
6771 references are made to a null symbol pointer. */
6772
6773void
6774aarch64_cleanup (void)
6775{
6776 literal_pool *pool;
6777
6778 for (pool = list_of_pools; pool; pool = pool->next)
6779 {
6780 /* Put it at the end of the relevant section. */
6781 subseg_set (pool->section, pool->sub_section);
6782 s_ltorg (0);
6783 }
6784}
6785
6786#ifdef OBJ_ELF
6787/* Remove any excess mapping symbols generated for alignment frags in
6788 SEC. We may have created a mapping symbol before a zero byte
6789 alignment; remove it if there's a mapping symbol after the
6790 alignment. */
6791static void
6792check_mapping_symbols (bfd * abfd ATTRIBUTE_UNUSED, asection * sec,
6793 void *dummy ATTRIBUTE_UNUSED)
6794{
6795 segment_info_type *seginfo = seg_info (sec);
6796 fragS *fragp;
6797
6798 if (seginfo == NULL || seginfo->frchainP == NULL)
6799 return;
6800
6801 for (fragp = seginfo->frchainP->frch_root;
6802 fragp != NULL; fragp = fragp->fr_next)
6803 {
6804 symbolS *sym = fragp->tc_frag_data.last_map;
6805 fragS *next = fragp->fr_next;
6806
6807 /* Variable-sized frags have been converted to fixed size by
6808 this point. But if this was variable-sized to start with,
6809 there will be a fixed-size frag after it. So don't handle
6810 next == NULL. */
6811 if (sym == NULL || next == NULL)
6812 continue;
6813
6814 if (S_GET_VALUE (sym) < next->fr_address)
6815 /* Not at the end of this frag. */
6816 continue;
6817 know (S_GET_VALUE (sym) == next->fr_address);
6818
6819 do
6820 {
6821 if (next->tc_frag_data.first_map != NULL)
6822 {
6823 /* Next frag starts with a mapping symbol. Discard this
6824 one. */
6825 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
6826 break;
6827 }
6828
6829 if (next->fr_next == NULL)
6830 {
6831 /* This mapping symbol is at the end of the section. Discard
6832 it. */
6833 know (next->fr_fix == 0 && next->fr_var == 0);
6834 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
6835 break;
6836 }
6837
6838 /* As long as we have empty frags without any mapping symbols,
6839 keep looking. */
6840 /* If the next frag is non-empty and does not start with a
6841 mapping symbol, then this mapping symbol is required. */
6842 if (next->fr_address != next->fr_next->fr_address)
6843 break;
6844
6845 next = next->fr_next;
6846 }
6847 while (next != NULL);
6848 }
6849}
6850#endif
6851
6852/* Adjust the symbol table. */
6853
6854void
6855aarch64_adjust_symtab (void)
6856{
6857#ifdef OBJ_ELF
6858 /* Remove any overlapping mapping symbols generated by alignment frags. */
6859 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
6860 /* Now do generic ELF adjustments. */
6861 elf_adjust_symtab ();
6862#endif
6863}
6864
6865static void
6866checked_hash_insert (struct hash_control *table, const char *key, void *value)
6867{
6868 const char *hash_err;
6869
6870 hash_err = hash_insert (table, key, value);
6871 if (hash_err)
6872 printf ("Internal Error: Can't hash %s\n", key);
6873}
6874
6875static void
6876fill_instruction_hash_table (void)
6877{
6878 aarch64_opcode *opcode = aarch64_opcode_table;
6879
6880 while (opcode->name != NULL)
6881 {
6882 templates *templ, *new_templ;
6883 templ = hash_find (aarch64_ops_hsh, opcode->name);
6884
6885 new_templ = (templates *) xmalloc (sizeof (templates));
6886 new_templ->opcode = opcode;
6887 new_templ->next = NULL;
6888
6889 if (!templ)
6890 checked_hash_insert (aarch64_ops_hsh, opcode->name, (void *) new_templ);
6891 else
6892 {
6893 new_templ->next = templ->next;
6894 templ->next = new_templ;
6895 }
6896 ++opcode;
6897 }
6898}
6899
6900static inline void
6901convert_to_upper (char *dst, const char *src, size_t num)
6902{
6903 unsigned int i;
6904 for (i = 0; i < num && *src != '\0'; ++i, ++dst, ++src)
6905 *dst = TOUPPER (*src);
6906 *dst = '\0';
6907}
6908
6909/* Assume STR point to a lower-case string, allocate, convert and return
6910 the corresponding upper-case string. */
6911static inline const char*
6912get_upper_str (const char *str)
6913{
6914 char *ret;
6915 size_t len = strlen (str);
6916 if ((ret = xmalloc (len + 1)) == NULL)
6917 abort ();
6918 convert_to_upper (ret, str, len);
6919 return ret;
6920}
6921
6922/* MD interface: Initialization. */
6923
6924void
6925md_begin (void)
6926{
6927 unsigned mach;
6928 unsigned int i;
6929
6930 if ((aarch64_ops_hsh = hash_new ()) == NULL
6931 || (aarch64_cond_hsh = hash_new ()) == NULL
6932 || (aarch64_shift_hsh = hash_new ()) == NULL
6933 || (aarch64_sys_regs_hsh = hash_new ()) == NULL
6934 || (aarch64_pstatefield_hsh = hash_new ()) == NULL
6935 || (aarch64_sys_regs_ic_hsh = hash_new ()) == NULL
6936 || (aarch64_sys_regs_dc_hsh = hash_new ()) == NULL
6937 || (aarch64_sys_regs_at_hsh = hash_new ()) == NULL
6938 || (aarch64_sys_regs_tlbi_hsh = hash_new ()) == NULL
6939 || (aarch64_reg_hsh = hash_new ()) == NULL
6940 || (aarch64_barrier_opt_hsh = hash_new ()) == NULL
6941 || (aarch64_nzcv_hsh = hash_new ()) == NULL
6942 || (aarch64_pldop_hsh = hash_new ()) == NULL)
6943 as_fatal (_("virtual memory exhausted"));
6944
6945 fill_instruction_hash_table ();
6946
6947 for (i = 0; aarch64_sys_regs[i].name != NULL; ++i)
6948 checked_hash_insert (aarch64_sys_regs_hsh, aarch64_sys_regs[i].name,
6949 (void *) (aarch64_sys_regs + i));
6950
6951 for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
6952 checked_hash_insert (aarch64_pstatefield_hsh,
6953 aarch64_pstatefields[i].name,
6954 (void *) (aarch64_pstatefields + i));
6955
6956 for (i = 0; aarch64_sys_regs_ic[i].template != NULL; i++)
6957 checked_hash_insert (aarch64_sys_regs_ic_hsh,
6958 aarch64_sys_regs_ic[i].template,
6959 (void *) (aarch64_sys_regs_ic + i));
6960
6961 for (i = 0; aarch64_sys_regs_dc[i].template != NULL; i++)
6962 checked_hash_insert (aarch64_sys_regs_dc_hsh,
6963 aarch64_sys_regs_dc[i].template,
6964 (void *) (aarch64_sys_regs_dc + i));
6965
6966 for (i = 0; aarch64_sys_regs_at[i].template != NULL; i++)
6967 checked_hash_insert (aarch64_sys_regs_at_hsh,
6968 aarch64_sys_regs_at[i].template,
6969 (void *) (aarch64_sys_regs_at + i));
6970
6971 for (i = 0; aarch64_sys_regs_tlbi[i].template != NULL; i++)
6972 checked_hash_insert (aarch64_sys_regs_tlbi_hsh,
6973 aarch64_sys_regs_tlbi[i].template,
6974 (void *) (aarch64_sys_regs_tlbi + i));
6975
6976 for (i = 0; i < ARRAY_SIZE (reg_names); i++)
6977 checked_hash_insert (aarch64_reg_hsh, reg_names[i].name,
6978 (void *) (reg_names + i));
6979
6980 for (i = 0; i < ARRAY_SIZE (nzcv_names); i++)
6981 checked_hash_insert (aarch64_nzcv_hsh, nzcv_names[i].template,
6982 (void *) (nzcv_names + i));
6983
6984 for (i = 0; aarch64_operand_modifiers[i].name != NULL; i++)
6985 {
6986 const char *name = aarch64_operand_modifiers[i].name;
6987 checked_hash_insert (aarch64_shift_hsh, name,
6988 (void *) (aarch64_operand_modifiers + i));
6989 /* Also hash the name in the upper case. */
6990 checked_hash_insert (aarch64_shift_hsh, get_upper_str (name),
6991 (void *) (aarch64_operand_modifiers + i));
6992 }
6993
6994 for (i = 0; i < ARRAY_SIZE (aarch64_conds); i++)
6995 {
6996 unsigned int j;
6997 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
6998 the same condition code. */
6999 for (j = 0; j < ARRAY_SIZE (aarch64_conds[i].names); ++j)
7000 {
7001 const char *name = aarch64_conds[i].names[j];
7002 if (name == NULL)
7003 break;
7004 checked_hash_insert (aarch64_cond_hsh, name,
7005 (void *) (aarch64_conds + i));
7006 /* Also hash the name in the upper case. */
7007 checked_hash_insert (aarch64_cond_hsh, get_upper_str (name),
7008 (void *) (aarch64_conds + i));
7009 }
7010 }
7011
7012 for (i = 0; i < ARRAY_SIZE (aarch64_barrier_options); i++)
7013 {
7014 const char *name = aarch64_barrier_options[i].name;
7015 /* Skip xx00 - the unallocated values of option. */
7016 if ((i & 0x3) == 0)
7017 continue;
7018 checked_hash_insert (aarch64_barrier_opt_hsh, name,
7019 (void *) (aarch64_barrier_options + i));
7020 /* Also hash the name in the upper case. */
7021 checked_hash_insert (aarch64_barrier_opt_hsh, get_upper_str (name),
7022 (void *) (aarch64_barrier_options + i));
7023 }
7024
7025 for (i = 0; i < ARRAY_SIZE (aarch64_prfops); i++)
7026 {
7027 const char* name = aarch64_prfops[i].name;
a1ccaec9
YZ		 7028 /* Skip the unallocated hint encodings. */
7029 if (name == NULL)
a06ea964
NC		 7030 continue;
7031 checked_hash_insert (aarch64_pldop_hsh, name,
7032 (void *) (aarch64_prfops + i));
7033 /* Also hash the name in the upper case. */
7034 checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name),
7035 (void *) (aarch64_prfops + i));
7036 }
7037
7038 /* Set the cpu variant based on the command-line options. */
7039 if (!mcpu_cpu_opt)
7040 mcpu_cpu_opt = march_cpu_opt;
7041
7042 if (!mcpu_cpu_opt)
7043 mcpu_cpu_opt = &cpu_default;
7044
7045 cpu_variant = *mcpu_cpu_opt;
7046
7047 /* Record the CPU type. */
cec5225b 7048 mach = ilp32_p ? bfd_mach_aarch64_ilp32 : bfd_mach_aarch64;
a06ea964
NC		 7049
7050 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
7051}
7052
7053/* Command line processing. */
7054
7055const char *md_shortopts = "m:";
7056
7057#ifdef AARCH64_BI_ENDIAN
7058#define OPTION_EB (OPTION_MD_BASE + 0)
7059#define OPTION_EL (OPTION_MD_BASE + 1)
7060#else
7061#if TARGET_BYTES_BIG_ENDIAN
7062#define OPTION_EB (OPTION_MD_BASE + 0)
7063#else
7064#define OPTION_EL (OPTION_MD_BASE + 1)
7065#endif
7066#endif
7067
7068struct option md_longopts[] = {
7069#ifdef OPTION_EB
7070 {"EB", no_argument, NULL, OPTION_EB},
7071#endif
7072#ifdef OPTION_EL
7073 {"EL", no_argument, NULL, OPTION_EL},
7074#endif
7075 {NULL, no_argument, NULL, 0}
7076};
7077
7078size_t md_longopts_size = sizeof (md_longopts);
7079
7080struct aarch64_option_table
7081{
7082 char *option; /* Option name to match. */
7083 char *help; /* Help information. */
7084 int *var; /* Variable to change. */
7085 int value; /* What to change it to. */
7086 char *deprecated; /* If non-null, print this message. */
7087};
7088
7089static struct aarch64_option_table aarch64_opts[] = {
7090 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
7091 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
7092 NULL},
cec5225b
YZ		 7093#ifdef OBJ_ELF
7094 {"mlp64", N_("select the LP64 model"), &ilp32_p, 0, NULL},
7095 {"milp32", N_("select the ILP32 model"), &ilp32_p, 1, NULL},
7096#endif /* OBJ_ELF */
a06ea964
NC		 7097#ifdef DEBUG_AARCH64
7098 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump, 1, NULL},
7099#endif /* DEBUG_AARCH64 */
7100 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p, 1,
7101 NULL},
7102 {NULL, NULL, NULL, 0, NULL}
7103};
7104
7105struct aarch64_cpu_option_table
7106{
7107 char *name;
7108 const aarch64_feature_set value;
7109 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7110 case. */
7111 const char *canonical_name;
7112};
7113
7114/* This list should, at a minimum, contain all the cpu names
7115 recognized by GCC. */
7116static const struct aarch64_cpu_option_table aarch64_cpus[] = {
7117 {"all", AARCH64_ANY, NULL},
95830fd1
YZ		 7118 {"cortex-a53", AARCH64_ARCH_V8, "Cortex-A53"},
7119 {"cortex-a57", AARCH64_ARCH_V8, "Cortex-A57"},
a06ea964
NC		 7120 {"generic", AARCH64_ARCH_V8, NULL},
7121
7122 /* These two are example CPUs supported in GCC, once we have real
7123 CPUs they will be removed. */
7124 {"example-1", AARCH64_ARCH_V8, NULL},
7125 {"example-2", AARCH64_ARCH_V8, NULL},
7126
7127 {NULL, AARCH64_ARCH_NONE, NULL}
7128};
7129
7130struct aarch64_arch_option_table
7131{
7132 char *name;
7133 const aarch64_feature_set value;
7134};
7135
7136/* This list should, at a minimum, contain all the architecture names
7137 recognized by GCC. */
7138static const struct aarch64_arch_option_table aarch64_archs[] = {
7139 {"all", AARCH64_ANY},
5a1ad39d 7140 {"armv8-a", AARCH64_ARCH_V8},
a06ea964
NC		 7141 {NULL, AARCH64_ARCH_NONE}
7142};
7143
7144/* ISA extensions. */
7145struct aarch64_option_cpu_value_table
7146{
7147 char *name;
7148 const aarch64_feature_set value;
7149};
7150
7151static const struct aarch64_option_cpu_value_table aarch64_features[] = {
e60bb1dd 7152 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0)},
a06ea964
NC		 7153 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0)},
7154 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
7155 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
7156 {NULL, AARCH64_ARCH_NONE}
7157};
7158
7159struct aarch64_long_option_table
7160{
7161 char *option; /* Substring to match. */
7162 char *help; /* Help information. */
7163 int (*func) (char *subopt); /* Function to decode sub-option. */
7164 char *deprecated; /* If non-null, print this message. */
7165};
7166
7167static int
7168aarch64_parse_features (char *str, const aarch64_feature_set **opt_p)
7169{
7170 /* We insist on extensions being added before being removed. We achieve
7171 this by using the ADDING_VALUE variable to indicate whether we are
7172 adding an extension (1) or removing it (0) and only allowing it to
7173 change in the order -1 -> 1 -> 0. */
7174 int adding_value = -1;
7175 aarch64_feature_set *ext_set = xmalloc (sizeof (aarch64_feature_set));
7176
7177 /* Copy the feature set, so that we can modify it. */
7178 *ext_set = **opt_p;
7179 *opt_p = ext_set;
7180
7181 while (str != NULL && *str != 0)
7182 {
7183 const struct aarch64_option_cpu_value_table *opt;
7184 char *ext;
7185 int optlen;
7186
7187 if (*str != '+')
7188 {
7189 as_bad (_("invalid architectural extension"));
7190 return 0;
7191 }
7192
7193 str++;
7194 ext = strchr (str, '+');
7195
7196 if (ext != NULL)
7197 optlen = ext - str;
7198 else
7199 optlen = strlen (str);
7200
7201 if (optlen >= 2 && strncmp (str, "no", 2) == 0)
7202 {
7203 if (adding_value != 0)
7204 adding_value = 0;
7205 optlen -= 2;
7206 str += 2;
7207 }
7208 else if (optlen > 0)
7209 {
7210 if (adding_value == -1)
7211 adding_value = 1;
7212 else if (adding_value != 1)
7213 {
7214 as_bad (_("must specify extensions to add before specifying "
7215 "those to remove"));
7216 return FALSE;
7217 }
7218 }
7219
7220 if (optlen == 0)
7221 {
7222 as_bad (_("missing architectural extension"));
7223 return 0;
7224 }
7225
7226 gas_assert (adding_value != -1);
7227
7228 for (opt = aarch64_features; opt->name != NULL; opt++)
7229 if (strncmp (opt->name, str, optlen) == 0)
7230 {
7231 /* Add or remove the extension. */
7232 if (adding_value)
7233 AARCH64_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
7234 else
7235 AARCH64_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
7236 break;
7237 }
7238
7239 if (opt->name == NULL)
7240 {
7241 as_bad (_("unknown architectural extension `%s'"), str);
7242 return 0;
7243 }
7244
7245 str = ext;
7246 };
7247
7248 return 1;
7249}
7250
7251static int
7252aarch64_parse_cpu (char *str)
7253{
7254 const struct aarch64_cpu_option_table *opt;
7255 char *ext = strchr (str, '+');
7256 size_t optlen;
7257
7258 if (ext != NULL)
7259 optlen = ext - str;
7260 else
7261 optlen = strlen (str);
7262
7263 if (optlen == 0)
7264 {
7265 as_bad (_("missing cpu name `%s'"), str);
7266 return 0;
7267 }
7268
7269 for (opt = aarch64_cpus; opt->name != NULL; opt++)
7270 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
7271 {
7272 mcpu_cpu_opt = &opt->value;
7273 if (ext != NULL)
7274 return aarch64_parse_features (ext, &mcpu_cpu_opt);
7275
7276 return 1;
7277 }
7278
7279 as_bad (_("unknown cpu `%s'"), str);
7280 return 0;
7281}
7282
7283static int
7284aarch64_parse_arch (char *str)
7285{
7286 const struct aarch64_arch_option_table *opt;
7287 char *ext = strchr (str, '+');
7288 size_t optlen;
7289
7290 if (ext != NULL)
7291 optlen = ext - str;
7292 else
7293 optlen = strlen (str);
7294
7295 if (optlen == 0)
7296 {
7297 as_bad (_("missing architecture name `%s'"), str);
7298 return 0;
7299 }
7300
7301 for (opt = aarch64_archs; opt->name != NULL; opt++)
7302 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
7303 {
7304 march_cpu_opt = &opt->value;
7305 if (ext != NULL)
7306 return aarch64_parse_features (ext, &march_cpu_opt);
7307
7308 return 1;
7309 }
7310
7311 as_bad (_("unknown architecture `%s'\n"), str);
7312 return 0;
7313}
7314
7315static struct aarch64_long_option_table aarch64_long_opts[] = {
7316 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
7317 aarch64_parse_cpu, NULL},
7318 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
7319 aarch64_parse_arch, NULL},
7320 {NULL, NULL, 0, NULL}
7321};
7322
7323int
7324md_parse_option (int c, char *arg)
7325{
7326 struct aarch64_option_table *opt;
7327 struct aarch64_long_option_table *lopt;
7328
7329 switch (c)
7330 {
7331#ifdef OPTION_EB
7332 case OPTION_EB:
7333 target_big_endian = 1;
7334 break;
7335#endif
7336
7337#ifdef OPTION_EL
7338 case OPTION_EL:
7339 target_big_endian = 0;
7340 break;
7341#endif
7342
7343 case 'a':
7344 /* Listing option. Just ignore these, we don't support additional
7345 ones. */
7346 return 0;
7347
7348 default:
7349 for (opt = aarch64_opts; opt->option != NULL; opt++)
7350 {
7351 if (c == opt->option[0]
7352 && ((arg == NULL && opt->option[1] == 0)
7353 || streq (arg, opt->option + 1)))
7354 {
7355 /* If the option is deprecated, tell the user. */
7356 if (opt->deprecated != NULL)
7357 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
7358 arg ? arg : "", _(opt->deprecated));
7359
7360 if (opt->var != NULL)
7361 *opt->var = opt->value;
7362
7363 return 1;
7364 }
7365 }
7366
7367 for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
7368 {
7369 /* These options are expected to have an argument. */
7370 if (c == lopt->option[0]
7371 && arg != NULL
7372 && strncmp (arg, lopt->option + 1,
7373 strlen (lopt->option + 1)) == 0)
7374 {
7375 /* If the option is deprecated, tell the user. */
7376 if (lopt->deprecated != NULL)
7377 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
7378 _(lopt->deprecated));
7379
7380 /* Call the sup-option parser. */
7381 return lopt->func (arg + strlen (lopt->option) - 1);
7382 }
7383 }
7384
7385 return 0;
7386 }
7387
7388 return 1;
7389}
7390
7391void
7392md_show_usage (FILE * fp)
7393{
7394 struct aarch64_option_table *opt;
7395 struct aarch64_long_option_table *lopt;
7396
7397 fprintf (fp, _(" AArch64-specific assembler options:\n"));
7398
7399 for (opt = aarch64_opts; opt->option != NULL; opt++)
7400 if (opt->help != NULL)
7401 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
7402
7403 for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
7404 if (lopt->help != NULL)
7405 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
7406
7407#ifdef OPTION_EB
7408 fprintf (fp, _("\
7409 -EB assemble code for a big-endian cpu\n"));
7410#endif
7411
7412#ifdef OPTION_EL
7413 fprintf (fp, _("\
7414 -EL assemble code for a little-endian cpu\n"));
7415#endif
7416}
7417
7418/* Parse a .cpu directive. */
7419
7420static void
7421s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED)
7422{
7423 const struct aarch64_cpu_option_table *opt;
7424 char saved_char;
7425 char *name;
7426 char *ext;
7427 size_t optlen;
7428
7429 name = input_line_pointer;
7430 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
7431 input_line_pointer++;
7432 saved_char = *input_line_pointer;
7433 *input_line_pointer = 0;
7434
7435 ext = strchr (name, '+');
7436
7437 if (ext != NULL)
7438 optlen = ext - name;
7439 else
7440 optlen = strlen (name);
7441
7442 /* Skip the first "all" entry. */
7443 for (opt = aarch64_cpus + 1; opt->name != NULL; opt++)
7444 if (strlen (opt->name) == optlen
7445 && strncmp (name, opt->name, optlen) == 0)
7446 {
7447 mcpu_cpu_opt = &opt->value;
7448 if (ext != NULL)
7449 if (!aarch64_parse_features (ext, &mcpu_cpu_opt))
7450 return;
7451
7452 cpu_variant = *mcpu_cpu_opt;
7453
7454 *input_line_pointer = saved_char;
7455 demand_empty_rest_of_line ();
7456 return;
7457 }
7458 as_bad (_("unknown cpu `%s'"), name);
7459 *input_line_pointer = saved_char;
7460 ignore_rest_of_line ();
7461}
7462
7463
7464/* Parse a .arch directive. */
7465
7466static void
7467s_aarch64_arch (int ignored ATTRIBUTE_UNUSED)
7468{
7469 const struct aarch64_arch_option_table *opt;
7470 char saved_char;
7471 char *name;
7472 char *ext;
7473 size_t optlen;
7474
7475 name = input_line_pointer;
7476 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
7477 input_line_pointer++;
7478 saved_char = *input_line_pointer;
7479 *input_line_pointer = 0;
7480
7481 ext = strchr (name, '+');
7482
7483 if (ext != NULL)
7484 optlen = ext - name;
7485 else
7486 optlen = strlen (name);
7487
7488 /* Skip the first "all" entry. */
7489 for (opt = aarch64_archs + 1; opt->name != NULL; opt++)
7490 if (strlen (opt->name) == optlen
7491 && strncmp (name, opt->name, optlen) == 0)
7492 {
7493 mcpu_cpu_opt = &opt->value;
7494 if (ext != NULL)
7495 if (!aarch64_parse_features (ext, &mcpu_cpu_opt))
7496 return;
7497
7498 cpu_variant = *mcpu_cpu_opt;
7499
7500 *input_line_pointer = saved_char;
7501 demand_empty_rest_of_line ();
7502 return;
7503 }
7504
7505 as_bad (_("unknown architecture `%s'\n"), name);
7506 *input_line_pointer = saved_char;
7507 ignore_rest_of_line ();
7508}
7509
7510/* Copy symbol information. */
7511
7512void
7513aarch64_copy_symbol_attributes (symbolS * dest, symbolS * src)
7514{
7515 AARCH64_GET_FLAG (dest) = AARCH64_GET_FLAG (src);
7516}
GDB Binutils - Deliverables
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