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a06ea964 NC |
1 | /* tc-aarch64.c -- Assemble for the AArch64 ISA |
2 | ||
6f2750fe | 3 | Copyright (C) 2009-2016 Free Software Foundation, Inc. |
a06ea964 NC |
4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GAS. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the license, or | |
11 | (at your option) any later version. | |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; see the file COPYING3. If not, | |
20 | see <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #include "as.h" | |
23 | #include <limits.h> | |
24 | #include <stdarg.h> | |
25 | #include "bfd_stdint.h" | |
26 | #define NO_RELOC 0 | |
27 | #include "safe-ctype.h" | |
28 | #include "subsegs.h" | |
29 | #include "obstack.h" | |
30 | ||
31 | #ifdef OBJ_ELF | |
32 | #include "elf/aarch64.h" | |
33 | #include "dw2gencfi.h" | |
34 | #endif | |
35 | ||
36 | #include "dwarf2dbg.h" | |
37 | ||
38 | /* Types of processor to assemble for. */ | |
39 | #ifndef CPU_DEFAULT | |
40 | #define CPU_DEFAULT AARCH64_ARCH_V8 | |
41 | #endif | |
42 | ||
43 | #define streq(a, b) (strcmp (a, b) == 0) | |
44 | ||
f4c51f60 JW |
45 | #define END_OF_INSN '\0' |
46 | ||
a06ea964 NC |
47 | static aarch64_feature_set cpu_variant; |
48 | ||
49 | /* Variables that we set while parsing command-line options. Once all | |
50 | options have been read we re-process these values to set the real | |
51 | assembly flags. */ | |
52 | static const aarch64_feature_set *mcpu_cpu_opt = NULL; | |
53 | static const aarch64_feature_set *march_cpu_opt = NULL; | |
54 | ||
55 | /* Constants for known architecture features. */ | |
56 | static const aarch64_feature_set cpu_default = CPU_DEFAULT; | |
57 | ||
a06ea964 NC |
58 | #ifdef OBJ_ELF |
59 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ | |
60 | static symbolS *GOT_symbol; | |
cec5225b | 61 | |
69091a2c YZ |
62 | /* Which ABI to use. */ |
63 | enum aarch64_abi_type | |
64 | { | |
65 | AARCH64_ABI_LP64 = 0, | |
66 | AARCH64_ABI_ILP32 = 1 | |
67 | }; | |
68 | ||
69 | /* AArch64 ABI for the output file. */ | |
70 | static enum aarch64_abi_type aarch64_abi = AARCH64_ABI_LP64; | |
71 | ||
cec5225b YZ |
72 | /* When non-zero, program to a 32-bit model, in which the C data types |
73 | int, long and all pointer types are 32-bit objects (ILP32); or to a | |
74 | 64-bit model, in which the C int type is 32-bits but the C long type | |
75 | and all pointer types are 64-bit objects (LP64). */ | |
69091a2c | 76 | #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32) |
a06ea964 NC |
77 | #endif |
78 | ||
79 | enum neon_el_type | |
80 | { | |
81 | NT_invtype = -1, | |
82 | NT_b, | |
83 | NT_h, | |
84 | NT_s, | |
85 | NT_d, | |
86 | NT_q | |
87 | }; | |
88 | ||
89 | /* Bits for DEFINED field in neon_type_el. */ | |
90 | #define NTA_HASTYPE 1 | |
91 | #define NTA_HASINDEX 2 | |
92 | ||
93 | struct neon_type_el | |
94 | { | |
95 | enum neon_el_type type; | |
96 | unsigned char defined; | |
97 | unsigned width; | |
98 | int64_t index; | |
99 | }; | |
100 | ||
101 | #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001 | |
102 | ||
103 | struct reloc | |
104 | { | |
105 | bfd_reloc_code_real_type type; | |
106 | expressionS exp; | |
107 | int pc_rel; | |
108 | enum aarch64_opnd opnd; | |
109 | uint32_t flags; | |
110 | unsigned need_libopcodes_p : 1; | |
111 | }; | |
112 | ||
113 | struct aarch64_instruction | |
114 | { | |
115 | /* libopcodes structure for instruction intermediate representation. */ | |
116 | aarch64_inst base; | |
117 | /* Record assembly errors found during the parsing. */ | |
118 | struct | |
119 | { | |
120 | enum aarch64_operand_error_kind kind; | |
121 | const char *error; | |
122 | } parsing_error; | |
123 | /* The condition that appears in the assembly line. */ | |
124 | int cond; | |
125 | /* Relocation information (including the GAS internal fixup). */ | |
126 | struct reloc reloc; | |
127 | /* Need to generate an immediate in the literal pool. */ | |
128 | unsigned gen_lit_pool : 1; | |
129 | }; | |
130 | ||
131 | typedef struct aarch64_instruction aarch64_instruction; | |
132 | ||
133 | static aarch64_instruction inst; | |
134 | ||
135 | static bfd_boolean parse_operands (char *, const aarch64_opcode *); | |
136 | static bfd_boolean programmer_friendly_fixup (aarch64_instruction *); | |
137 | ||
138 | /* Diagnostics inline function utilites. | |
139 | ||
140 | These are lightweight utlities which should only be called by parse_operands | |
141 | and other parsers. GAS processes each assembly line by parsing it against | |
142 | instruction template(s), in the case of multiple templates (for the same | |
143 | mnemonic name), those templates are tried one by one until one succeeds or | |
144 | all fail. An assembly line may fail a few templates before being | |
145 | successfully parsed; an error saved here in most cases is not a user error | |
146 | but an error indicating the current template is not the right template. | |
147 | Therefore it is very important that errors can be saved at a low cost during | |
148 | the parsing; we don't want to slow down the whole parsing by recording | |
149 | non-user errors in detail. | |
150 | ||
151 | Remember that the objective is to help GAS pick up the most approapriate | |
152 | error message in the case of multiple templates, e.g. FMOV which has 8 | |
153 | templates. */ | |
154 | ||
155 | static inline void | |
156 | clear_error (void) | |
157 | { | |
158 | inst.parsing_error.kind = AARCH64_OPDE_NIL; | |
159 | inst.parsing_error.error = NULL; | |
160 | } | |
161 | ||
162 | static inline bfd_boolean | |
163 | error_p (void) | |
164 | { | |
165 | return inst.parsing_error.kind != AARCH64_OPDE_NIL; | |
166 | } | |
167 | ||
168 | static inline const char * | |
169 | get_error_message (void) | |
170 | { | |
171 | return inst.parsing_error.error; | |
172 | } | |
173 | ||
a06ea964 NC |
174 | static inline enum aarch64_operand_error_kind |
175 | get_error_kind (void) | |
176 | { | |
177 | return inst.parsing_error.kind; | |
178 | } | |
179 | ||
a06ea964 NC |
180 | static inline void |
181 | set_error (enum aarch64_operand_error_kind kind, const char *error) | |
182 | { | |
183 | inst.parsing_error.kind = kind; | |
184 | inst.parsing_error.error = error; | |
185 | } | |
186 | ||
187 | static inline void | |
188 | set_recoverable_error (const char *error) | |
189 | { | |
190 | set_error (AARCH64_OPDE_RECOVERABLE, error); | |
191 | } | |
192 | ||
193 | /* Use the DESC field of the corresponding aarch64_operand entry to compose | |
194 | the error message. */ | |
195 | static inline void | |
196 | set_default_error (void) | |
197 | { | |
198 | set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL); | |
199 | } | |
200 | ||
201 | static inline void | |
202 | set_syntax_error (const char *error) | |
203 | { | |
204 | set_error (AARCH64_OPDE_SYNTAX_ERROR, error); | |
205 | } | |
206 | ||
207 | static inline void | |
208 | set_first_syntax_error (const char *error) | |
209 | { | |
210 | if (! error_p ()) | |
211 | set_error (AARCH64_OPDE_SYNTAX_ERROR, error); | |
212 | } | |
213 | ||
214 | static inline void | |
215 | set_fatal_syntax_error (const char *error) | |
216 | { | |
217 | set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR, error); | |
218 | } | |
219 | \f | |
220 | /* Number of littlenums required to hold an extended precision number. */ | |
221 | #define MAX_LITTLENUMS 6 | |
222 | ||
223 | /* Return value for certain parsers when the parsing fails; those parsers | |
224 | return the information of the parsed result, e.g. register number, on | |
225 | success. */ | |
226 | #define PARSE_FAIL -1 | |
227 | ||
228 | /* This is an invalid condition code that means no conditional field is | |
229 | present. */ | |
230 | #define COND_ALWAYS 0x10 | |
231 | ||
232 | typedef struct | |
233 | { | |
234 | const char *template; | |
235 | unsigned long value; | |
236 | } asm_barrier_opt; | |
237 | ||
238 | typedef struct | |
239 | { | |
240 | const char *template; | |
241 | uint32_t value; | |
242 | } asm_nzcv; | |
243 | ||
244 | struct reloc_entry | |
245 | { | |
246 | char *name; | |
247 | bfd_reloc_code_real_type reloc; | |
248 | }; | |
249 | ||
a06ea964 NC |
250 | /* Macros to define the register types and masks for the purpose |
251 | of parsing. */ | |
252 | ||
253 | #undef AARCH64_REG_TYPES | |
254 | #define AARCH64_REG_TYPES \ | |
255 | BASIC_REG_TYPE(R_32) /* w[0-30] */ \ | |
256 | BASIC_REG_TYPE(R_64) /* x[0-30] */ \ | |
257 | BASIC_REG_TYPE(SP_32) /* wsp */ \ | |
258 | BASIC_REG_TYPE(SP_64) /* sp */ \ | |
259 | BASIC_REG_TYPE(Z_32) /* wzr */ \ | |
260 | BASIC_REG_TYPE(Z_64) /* xzr */ \ | |
261 | BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\ | |
262 | BASIC_REG_TYPE(FP_H) /* h[0-31] */ \ | |
263 | BASIC_REG_TYPE(FP_S) /* s[0-31] */ \ | |
264 | BASIC_REG_TYPE(FP_D) /* d[0-31] */ \ | |
265 | BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \ | |
266 | BASIC_REG_TYPE(CN) /* c[0-7] */ \ | |
267 | BASIC_REG_TYPE(VN) /* v[0-31] */ \ | |
268 | /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \ | |
269 | MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \ | |
270 | /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \ | |
271 | MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \ | |
272 | | REG_TYPE(SP_32) | REG_TYPE(SP_64) \ | |
273 | | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \ | |
274 | /* Typecheck: any [BHSDQ]P FP. */ \ | |
275 | MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \ | |
276 | | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \ | |
277 | /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \ | |
278 | MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \ | |
279 | | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \ | |
280 | | REG_TYPE(FP_B) | REG_TYPE(FP_H) \ | |
281 | | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \ | |
282 | /* Any integer register; used for error messages only. */ \ | |
283 | MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \ | |
284 | | REG_TYPE(SP_32) | REG_TYPE(SP_64) \ | |
285 | | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \ | |
286 | /* Pseudo type to mark the end of the enumerator sequence. */ \ | |
287 | BASIC_REG_TYPE(MAX) | |
288 | ||
289 | #undef BASIC_REG_TYPE | |
290 | #define BASIC_REG_TYPE(T) REG_TYPE_##T, | |
291 | #undef MULTI_REG_TYPE | |
292 | #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T) | |
293 | ||
294 | /* Register type enumerators. */ | |
8a0b252a | 295 | typedef enum aarch64_reg_type_ |
a06ea964 NC |
296 | { |
297 | /* A list of REG_TYPE_*. */ | |
298 | AARCH64_REG_TYPES | |
299 | } aarch64_reg_type; | |
300 | ||
301 | #undef BASIC_REG_TYPE | |
302 | #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T, | |
303 | #undef REG_TYPE | |
304 | #define REG_TYPE(T) (1 << REG_TYPE_##T) | |
305 | #undef MULTI_REG_TYPE | |
306 | #define MULTI_REG_TYPE(T,V) V, | |
307 | ||
8a0b252a TS |
308 | /* Structure for a hash table entry for a register. */ |
309 | typedef struct | |
310 | { | |
311 | const char *name; | |
312 | unsigned char number; | |
313 | ENUM_BITFIELD (aarch64_reg_type_) type : 8; | |
314 | unsigned char builtin; | |
315 | } reg_entry; | |
316 | ||
a06ea964 NC |
317 | /* Values indexed by aarch64_reg_type to assist the type checking. */ |
318 | static const unsigned reg_type_masks[] = | |
319 | { | |
320 | AARCH64_REG_TYPES | |
321 | }; | |
322 | ||
323 | #undef BASIC_REG_TYPE | |
324 | #undef REG_TYPE | |
325 | #undef MULTI_REG_TYPE | |
326 | #undef AARCH64_REG_TYPES | |
327 | ||
328 | /* Diagnostics used when we don't get a register of the expected type. | |
329 | Note: this has to synchronized with aarch64_reg_type definitions | |
330 | above. */ | |
331 | static const char * | |
332 | get_reg_expected_msg (aarch64_reg_type reg_type) | |
333 | { | |
334 | const char *msg; | |
335 | ||
336 | switch (reg_type) | |
337 | { | |
338 | case REG_TYPE_R_32: | |
339 | msg = N_("integer 32-bit register expected"); | |
340 | break; | |
341 | case REG_TYPE_R_64: | |
342 | msg = N_("integer 64-bit register expected"); | |
343 | break; | |
344 | case REG_TYPE_R_N: | |
345 | msg = N_("integer register expected"); | |
346 | break; | |
347 | case REG_TYPE_R_Z_SP: | |
348 | msg = N_("integer, zero or SP register expected"); | |
349 | break; | |
350 | case REG_TYPE_FP_B: | |
351 | msg = N_("8-bit SIMD scalar register expected"); | |
352 | break; | |
353 | case REG_TYPE_FP_H: | |
354 | msg = N_("16-bit SIMD scalar or floating-point half precision " | |
355 | "register expected"); | |
356 | break; | |
357 | case REG_TYPE_FP_S: | |
358 | msg = N_("32-bit SIMD scalar or floating-point single precision " | |
359 | "register expected"); | |
360 | break; | |
361 | case REG_TYPE_FP_D: | |
362 | msg = N_("64-bit SIMD scalar or floating-point double precision " | |
363 | "register expected"); | |
364 | break; | |
365 | case REG_TYPE_FP_Q: | |
366 | msg = N_("128-bit SIMD scalar or floating-point quad precision " | |
367 | "register expected"); | |
368 | break; | |
369 | case REG_TYPE_CN: | |
370 | msg = N_("C0 - C15 expected"); | |
371 | break; | |
372 | case REG_TYPE_R_Z_BHSDQ_V: | |
373 | msg = N_("register expected"); | |
374 | break; | |
375 | case REG_TYPE_BHSDQ: /* any [BHSDQ]P FP */ | |
376 | msg = N_("SIMD scalar or floating-point register expected"); | |
377 | break; | |
378 | case REG_TYPE_VN: /* any V reg */ | |
379 | msg = N_("vector register expected"); | |
380 | break; | |
381 | default: | |
382 | as_fatal (_("invalid register type %d"), reg_type); | |
383 | } | |
384 | return msg; | |
385 | } | |
386 | ||
387 | /* Some well known registers that we refer to directly elsewhere. */ | |
388 | #define REG_SP 31 | |
389 | ||
390 | /* Instructions take 4 bytes in the object file. */ | |
391 | #define INSN_SIZE 4 | |
392 | ||
393 | /* Define some common error messages. */ | |
394 | #define BAD_SP _("SP not allowed here") | |
395 | ||
396 | static struct hash_control *aarch64_ops_hsh; | |
397 | static struct hash_control *aarch64_cond_hsh; | |
398 | static struct hash_control *aarch64_shift_hsh; | |
399 | static struct hash_control *aarch64_sys_regs_hsh; | |
400 | static struct hash_control *aarch64_pstatefield_hsh; | |
401 | static struct hash_control *aarch64_sys_regs_ic_hsh; | |
402 | static struct hash_control *aarch64_sys_regs_dc_hsh; | |
403 | static struct hash_control *aarch64_sys_regs_at_hsh; | |
404 | static struct hash_control *aarch64_sys_regs_tlbi_hsh; | |
405 | static struct hash_control *aarch64_reg_hsh; | |
406 | static struct hash_control *aarch64_barrier_opt_hsh; | |
407 | static struct hash_control *aarch64_nzcv_hsh; | |
408 | static struct hash_control *aarch64_pldop_hsh; | |
1e6f4800 | 409 | static struct hash_control *aarch64_hint_opt_hsh; |
a06ea964 NC |
410 | |
411 | /* Stuff needed to resolve the label ambiguity | |
412 | As: | |
413 | ... | |
414 | label: <insn> | |
415 | may differ from: | |
416 | ... | |
417 | label: | |
418 | <insn> */ | |
419 | ||
420 | static symbolS *last_label_seen; | |
421 | ||
422 | /* Literal pool structure. Held on a per-section | |
423 | and per-sub-section basis. */ | |
424 | ||
425 | #define MAX_LITERAL_POOL_SIZE 1024 | |
55d9b4c1 NC |
426 | typedef struct literal_expression |
427 | { | |
428 | expressionS exp; | |
429 | /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */ | |
430 | LITTLENUM_TYPE * bignum; | |
431 | } literal_expression; | |
432 | ||
a06ea964 NC |
433 | typedef struct literal_pool |
434 | { | |
55d9b4c1 | 435 | literal_expression literals[MAX_LITERAL_POOL_SIZE]; |
a06ea964 NC |
436 | unsigned int next_free_entry; |
437 | unsigned int id; | |
438 | symbolS *symbol; | |
439 | segT section; | |
440 | subsegT sub_section; | |
441 | int size; | |
442 | struct literal_pool *next; | |
443 | } literal_pool; | |
444 | ||
445 | /* Pointer to a linked list of literal pools. */ | |
446 | static literal_pool *list_of_pools = NULL; | |
447 | \f | |
448 | /* Pure syntax. */ | |
449 | ||
450 | /* This array holds the chars that always start a comment. If the | |
451 | pre-processor is disabled, these aren't very useful. */ | |
452 | const char comment_chars[] = ""; | |
453 | ||
454 | /* This array holds the chars that only start a comment at the beginning of | |
455 | a line. If the line seems to have the form '# 123 filename' | |
456 | .line and .file directives will appear in the pre-processed output. */ | |
457 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
458 | first line of the input file. This is because the compiler outputs | |
459 | #NO_APP at the beginning of its output. */ | |
460 | /* Also note that comments like this one will always work. */ | |
461 | const char line_comment_chars[] = "#"; | |
462 | ||
463 | const char line_separator_chars[] = ";"; | |
464 | ||
465 | /* Chars that can be used to separate mant | |
466 | from exp in floating point numbers. */ | |
467 | const char EXP_CHARS[] = "eE"; | |
468 | ||
469 | /* Chars that mean this number is a floating point constant. */ | |
470 | /* As in 0f12.456 */ | |
471 | /* or 0d1.2345e12 */ | |
472 | ||
473 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; | |
474 | ||
475 | /* Prefix character that indicates the start of an immediate value. */ | |
476 | #define is_immediate_prefix(C) ((C) == '#') | |
477 | ||
478 | /* Separator character handling. */ | |
479 | ||
480 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
481 | ||
482 | static inline bfd_boolean | |
483 | skip_past_char (char **str, char c) | |
484 | { | |
485 | if (**str == c) | |
486 | { | |
487 | (*str)++; | |
488 | return TRUE; | |
489 | } | |
490 | else | |
491 | return FALSE; | |
492 | } | |
493 | ||
494 | #define skip_past_comma(str) skip_past_char (str, ',') | |
495 | ||
496 | /* Arithmetic expressions (possibly involving symbols). */ | |
497 | ||
a06ea964 NC |
498 | static bfd_boolean in_my_get_expression_p = FALSE; |
499 | ||
500 | /* Third argument to my_get_expression. */ | |
501 | #define GE_NO_PREFIX 0 | |
502 | #define GE_OPT_PREFIX 1 | |
503 | ||
504 | /* Return TRUE if the string pointed by *STR is successfully parsed | |
505 | as an valid expression; *EP will be filled with the information of | |
506 | such an expression. Otherwise return FALSE. */ | |
507 | ||
508 | static bfd_boolean | |
509 | my_get_expression (expressionS * ep, char **str, int prefix_mode, | |
510 | int reject_absent) | |
511 | { | |
512 | char *save_in; | |
513 | segT seg; | |
514 | int prefix_present_p = 0; | |
515 | ||
516 | switch (prefix_mode) | |
517 | { | |
518 | case GE_NO_PREFIX: | |
519 | break; | |
520 | case GE_OPT_PREFIX: | |
521 | if (is_immediate_prefix (**str)) | |
522 | { | |
523 | (*str)++; | |
524 | prefix_present_p = 1; | |
525 | } | |
526 | break; | |
527 | default: | |
528 | abort (); | |
529 | } | |
530 | ||
531 | memset (ep, 0, sizeof (expressionS)); | |
532 | ||
533 | save_in = input_line_pointer; | |
534 | input_line_pointer = *str; | |
535 | in_my_get_expression_p = TRUE; | |
536 | seg = expression (ep); | |
537 | in_my_get_expression_p = FALSE; | |
538 | ||
539 | if (ep->X_op == O_illegal || (reject_absent && ep->X_op == O_absent)) | |
540 | { | |
541 | /* We found a bad expression in md_operand(). */ | |
542 | *str = input_line_pointer; | |
543 | input_line_pointer = save_in; | |
544 | if (prefix_present_p && ! error_p ()) | |
545 | set_fatal_syntax_error (_("bad expression")); | |
546 | else | |
547 | set_first_syntax_error (_("bad expression")); | |
548 | return FALSE; | |
549 | } | |
550 | ||
551 | #ifdef OBJ_AOUT | |
552 | if (seg != absolute_section | |
553 | && seg != text_section | |
554 | && seg != data_section | |
555 | && seg != bss_section && seg != undefined_section) | |
556 | { | |
557 | set_syntax_error (_("bad segment")); | |
558 | *str = input_line_pointer; | |
559 | input_line_pointer = save_in; | |
560 | return FALSE; | |
561 | } | |
562 | #else | |
563 | (void) seg; | |
564 | #endif | |
565 | ||
a06ea964 NC |
566 | *str = input_line_pointer; |
567 | input_line_pointer = save_in; | |
568 | return TRUE; | |
569 | } | |
570 | ||
571 | /* Turn a string in input_line_pointer into a floating point constant | |
572 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
573 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
574 | returned, or NULL on OK. */ | |
575 | ||
6d4af3c2 | 576 | const char * |
a06ea964 NC |
577 | md_atof (int type, char *litP, int *sizeP) |
578 | { | |
579 | return ieee_md_atof (type, litP, sizeP, target_big_endian); | |
580 | } | |
581 | ||
582 | /* We handle all bad expressions here, so that we can report the faulty | |
583 | instruction in the error message. */ | |
584 | void | |
585 | md_operand (expressionS * exp) | |
586 | { | |
587 | if (in_my_get_expression_p) | |
588 | exp->X_op = O_illegal; | |
589 | } | |
590 | ||
591 | /* Immediate values. */ | |
592 | ||
593 | /* Errors may be set multiple times during parsing or bit encoding | |
594 | (particularly in the Neon bits), but usually the earliest error which is set | |
595 | will be the most meaningful. Avoid overwriting it with later (cascading) | |
596 | errors by calling this function. */ | |
597 | ||
598 | static void | |
599 | first_error (const char *error) | |
600 | { | |
601 | if (! error_p ()) | |
602 | set_syntax_error (error); | |
603 | } | |
604 | ||
605 | /* Similiar to first_error, but this function accepts formatted error | |
606 | message. */ | |
607 | static void | |
608 | first_error_fmt (const char *format, ...) | |
609 | { | |
610 | va_list args; | |
611 | enum | |
612 | { size = 100 }; | |
613 | /* N.B. this single buffer will not cause error messages for different | |
614 | instructions to pollute each other; this is because at the end of | |
615 | processing of each assembly line, error message if any will be | |
616 | collected by as_bad. */ | |
617 | static char buffer[size]; | |
618 | ||
619 | if (! error_p ()) | |
620 | { | |
3e0baa28 | 621 | int ret ATTRIBUTE_UNUSED; |
a06ea964 NC |
622 | va_start (args, format); |
623 | ret = vsnprintf (buffer, size, format, args); | |
624 | know (ret <= size - 1 && ret >= 0); | |
625 | va_end (args); | |
626 | set_syntax_error (buffer); | |
627 | } | |
628 | } | |
629 | ||
630 | /* Register parsing. */ | |
631 | ||
632 | /* Generic register parser which is called by other specialized | |
633 | register parsers. | |
634 | CCP points to what should be the beginning of a register name. | |
635 | If it is indeed a valid register name, advance CCP over it and | |
636 | return the reg_entry structure; otherwise return NULL. | |
637 | It does not issue diagnostics. */ | |
638 | ||
639 | static reg_entry * | |
640 | parse_reg (char **ccp) | |
641 | { | |
642 | char *start = *ccp; | |
643 | char *p; | |
644 | reg_entry *reg; | |
645 | ||
646 | #ifdef REGISTER_PREFIX | |
647 | if (*start != REGISTER_PREFIX) | |
648 | return NULL; | |
649 | start++; | |
650 | #endif | |
651 | ||
652 | p = start; | |
653 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
654 | return NULL; | |
655 | ||
656 | do | |
657 | p++; | |
658 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
659 | ||
660 | reg = (reg_entry *) hash_find_n (aarch64_reg_hsh, start, p - start); | |
661 | ||
662 | if (!reg) | |
663 | return NULL; | |
664 | ||
665 | *ccp = p; | |
666 | return reg; | |
667 | } | |
668 | ||
669 | /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise | |
670 | return FALSE. */ | |
671 | static bfd_boolean | |
672 | aarch64_check_reg_type (const reg_entry *reg, aarch64_reg_type type) | |
673 | { | |
674 | if (reg->type == type) | |
675 | return TRUE; | |
676 | ||
677 | switch (type) | |
678 | { | |
679 | case REG_TYPE_R64_SP: /* 64-bit integer reg (inc SP exc XZR). */ | |
680 | case REG_TYPE_R_Z_SP: /* Integer reg (inc {X}SP inc [WX]ZR). */ | |
681 | case REG_TYPE_R_Z_BHSDQ_V: /* Any register apart from Cn. */ | |
682 | case REG_TYPE_BHSDQ: /* Any [BHSDQ]P FP or SIMD scalar register. */ | |
683 | case REG_TYPE_VN: /* Vector register. */ | |
684 | gas_assert (reg->type < REG_TYPE_MAX && type < REG_TYPE_MAX); | |
685 | return ((reg_type_masks[reg->type] & reg_type_masks[type]) | |
686 | == reg_type_masks[reg->type]); | |
687 | default: | |
688 | as_fatal ("unhandled type %d", type); | |
689 | abort (); | |
690 | } | |
691 | } | |
692 | ||
693 | /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP. | |
694 | Return the register number otherwise. *ISREG32 is set to one if the | |
695 | register is 32-bit wide; *ISREGZERO is set to one if the register is | |
696 | of type Z_32 or Z_64. | |
697 | Note that this function does not issue any diagnostics. */ | |
698 | ||
699 | static int | |
700 | aarch64_reg_parse_32_64 (char **ccp, int reject_sp, int reject_rz, | |
701 | int *isreg32, int *isregzero) | |
702 | { | |
703 | char *str = *ccp; | |
704 | const reg_entry *reg = parse_reg (&str); | |
705 | ||
706 | if (reg == NULL) | |
707 | return PARSE_FAIL; | |
708 | ||
709 | if (! aarch64_check_reg_type (reg, REG_TYPE_R_Z_SP)) | |
710 | return PARSE_FAIL; | |
711 | ||
712 | switch (reg->type) | |
713 | { | |
714 | case REG_TYPE_SP_32: | |
715 | case REG_TYPE_SP_64: | |
716 | if (reject_sp) | |
717 | return PARSE_FAIL; | |
718 | *isreg32 = reg->type == REG_TYPE_SP_32; | |
719 | *isregzero = 0; | |
720 | break; | |
721 | case REG_TYPE_R_32: | |
722 | case REG_TYPE_R_64: | |
723 | *isreg32 = reg->type == REG_TYPE_R_32; | |
724 | *isregzero = 0; | |
725 | break; | |
726 | case REG_TYPE_Z_32: | |
727 | case REG_TYPE_Z_64: | |
728 | if (reject_rz) | |
729 | return PARSE_FAIL; | |
730 | *isreg32 = reg->type == REG_TYPE_Z_32; | |
731 | *isregzero = 1; | |
732 | break; | |
733 | default: | |
734 | return PARSE_FAIL; | |
735 | } | |
736 | ||
737 | *ccp = str; | |
738 | ||
739 | return reg->number; | |
740 | } | |
741 | ||
742 | /* Parse the qualifier of a SIMD vector register or a SIMD vector element. | |
743 | Fill in *PARSED_TYPE and return TRUE if the parsing succeeds; | |
744 | otherwise return FALSE. | |
745 | ||
746 | Accept only one occurrence of: | |
3067d3b9 | 747 | 8b 16b 2h 4h 8h 2s 4s 1d 2d |
a06ea964 NC |
748 | b h s d q */ |
749 | static bfd_boolean | |
750 | parse_neon_type_for_operand (struct neon_type_el *parsed_type, char **str) | |
751 | { | |
752 | char *ptr = *str; | |
753 | unsigned width; | |
754 | unsigned element_size; | |
755 | enum neon_el_type type; | |
756 | ||
757 | /* skip '.' */ | |
758 | ptr++; | |
759 | ||
760 | if (!ISDIGIT (*ptr)) | |
761 | { | |
762 | width = 0; | |
763 | goto elt_size; | |
764 | } | |
765 | width = strtoul (ptr, &ptr, 10); | |
766 | if (width != 1 && width != 2 && width != 4 && width != 8 && width != 16) | |
767 | { | |
768 | first_error_fmt (_("bad size %d in vector width specifier"), width); | |
769 | return FALSE; | |
770 | } | |
771 | ||
772 | elt_size: | |
773 | switch (TOLOWER (*ptr)) | |
774 | { | |
775 | case 'b': | |
776 | type = NT_b; | |
777 | element_size = 8; | |
778 | break; | |
779 | case 'h': | |
780 | type = NT_h; | |
781 | element_size = 16; | |
782 | break; | |
783 | case 's': | |
784 | type = NT_s; | |
785 | element_size = 32; | |
786 | break; | |
787 | case 'd': | |
788 | type = NT_d; | |
789 | element_size = 64; | |
790 | break; | |
791 | case 'q': | |
792 | if (width == 1) | |
793 | { | |
794 | type = NT_q; | |
795 | element_size = 128; | |
796 | break; | |
797 | } | |
798 | /* fall through. */ | |
799 | default: | |
800 | if (*ptr != '\0') | |
801 | first_error_fmt (_("unexpected character `%c' in element size"), *ptr); | |
802 | else | |
803 | first_error (_("missing element size")); | |
804 | return FALSE; | |
805 | } | |
3067d3b9 MW |
806 | if (width != 0 && width * element_size != 64 && width * element_size != 128 |
807 | && !(width == 2 && element_size == 16)) | |
a06ea964 NC |
808 | { |
809 | first_error_fmt (_ | |
810 | ("invalid element size %d and vector size combination %c"), | |
811 | width, *ptr); | |
812 | return FALSE; | |
813 | } | |
814 | ptr++; | |
815 | ||
816 | parsed_type->type = type; | |
817 | parsed_type->width = width; | |
818 | ||
819 | *str = ptr; | |
820 | ||
821 | return TRUE; | |
822 | } | |
823 | ||
a06ea964 NC |
824 | /* Parse a register of the type TYPE. |
825 | ||
826 | Return PARSE_FAIL if the string pointed by *CCP is not a valid register | |
827 | name or the parsed register is not of TYPE. | |
828 | ||
829 | Otherwise return the register number, and optionally fill in the actual | |
830 | type of the register in *RTYPE when multiple alternatives were given, and | |
831 | return the register shape and element index information in *TYPEINFO. | |
832 | ||
833 | IN_REG_LIST should be set with TRUE if the caller is parsing a register | |
834 | list. */ | |
835 | ||
836 | static int | |
837 | parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype, | |
838 | struct neon_type_el *typeinfo, bfd_boolean in_reg_list) | |
839 | { | |
840 | char *str = *ccp; | |
841 | const reg_entry *reg = parse_reg (&str); | |
842 | struct neon_type_el atype; | |
843 | struct neon_type_el parsetype; | |
844 | bfd_boolean is_typed_vecreg = FALSE; | |
845 | ||
846 | atype.defined = 0; | |
847 | atype.type = NT_invtype; | |
848 | atype.width = -1; | |
849 | atype.index = 0; | |
850 | ||
851 | if (reg == NULL) | |
852 | { | |
853 | if (typeinfo) | |
854 | *typeinfo = atype; | |
855 | set_default_error (); | |
856 | return PARSE_FAIL; | |
857 | } | |
858 | ||
859 | if (! aarch64_check_reg_type (reg, type)) | |
860 | { | |
861 | DEBUG_TRACE ("reg type check failed"); | |
862 | set_default_error (); | |
863 | return PARSE_FAIL; | |
864 | } | |
865 | type = reg->type; | |
866 | ||
a235d3ae | 867 | if (type == REG_TYPE_VN && *str == '.') |
a06ea964 | 868 | { |
a235d3ae RS |
869 | if (!parse_neon_type_for_operand (&parsetype, &str)) |
870 | return PARSE_FAIL; | |
871 | ||
a06ea964 NC |
872 | /* Register if of the form Vn.[bhsdq]. */ |
873 | is_typed_vecreg = TRUE; | |
874 | ||
875 | if (parsetype.width == 0) | |
876 | /* Expect index. In the new scheme we cannot have | |
877 | Vn.[bhsdq] represent a scalar. Therefore any | |
878 | Vn.[bhsdq] should have an index following it. | |
879 | Except in reglists ofcourse. */ | |
880 | atype.defined |= NTA_HASINDEX; | |
881 | else | |
882 | atype.defined |= NTA_HASTYPE; | |
883 | ||
884 | atype.type = parsetype.type; | |
885 | atype.width = parsetype.width; | |
886 | } | |
887 | ||
888 | if (skip_past_char (&str, '[')) | |
889 | { | |
890 | expressionS exp; | |
891 | ||
892 | /* Reject Sn[index] syntax. */ | |
893 | if (!is_typed_vecreg) | |
894 | { | |
895 | first_error (_("this type of register can't be indexed")); | |
896 | return PARSE_FAIL; | |
897 | } | |
898 | ||
899 | if (in_reg_list == TRUE) | |
900 | { | |
901 | first_error (_("index not allowed inside register list")); | |
902 | return PARSE_FAIL; | |
903 | } | |
904 | ||
905 | atype.defined |= NTA_HASINDEX; | |
906 | ||
907 | my_get_expression (&exp, &str, GE_NO_PREFIX, 1); | |
908 | ||
909 | if (exp.X_op != O_constant) | |
910 | { | |
911 | first_error (_("constant expression required")); | |
912 | return PARSE_FAIL; | |
913 | } | |
914 | ||
915 | if (! skip_past_char (&str, ']')) | |
916 | return PARSE_FAIL; | |
917 | ||
918 | atype.index = exp.X_add_number; | |
919 | } | |
920 | else if (!in_reg_list && (atype.defined & NTA_HASINDEX) != 0) | |
921 | { | |
922 | /* Indexed vector register expected. */ | |
923 | first_error (_("indexed vector register expected")); | |
924 | return PARSE_FAIL; | |
925 | } | |
926 | ||
927 | /* A vector reg Vn should be typed or indexed. */ | |
928 | if (type == REG_TYPE_VN && atype.defined == 0) | |
929 | { | |
930 | first_error (_("invalid use of vector register")); | |
931 | } | |
932 | ||
933 | if (typeinfo) | |
934 | *typeinfo = atype; | |
935 | ||
936 | if (rtype) | |
937 | *rtype = type; | |
938 | ||
939 | *ccp = str; | |
940 | ||
941 | return reg->number; | |
942 | } | |
943 | ||
944 | /* Parse register. | |
945 | ||
946 | Return the register number on success; return PARSE_FAIL otherwise. | |
947 | ||
948 | If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of | |
949 | the register (e.g. NEON double or quad reg when either has been requested). | |
950 | ||
951 | If this is a NEON vector register with additional type information, fill | |
952 | in the struct pointed to by VECTYPE (if non-NULL). | |
953 | ||
954 | This parser does not handle register list. */ | |
955 | ||
956 | static int | |
957 | aarch64_reg_parse (char **ccp, aarch64_reg_type type, | |
958 | aarch64_reg_type *rtype, struct neon_type_el *vectype) | |
959 | { | |
960 | struct neon_type_el atype; | |
961 | char *str = *ccp; | |
962 | int reg = parse_typed_reg (&str, type, rtype, &atype, | |
963 | /*in_reg_list= */ FALSE); | |
964 | ||
965 | if (reg == PARSE_FAIL) | |
966 | return PARSE_FAIL; | |
967 | ||
968 | if (vectype) | |
969 | *vectype = atype; | |
970 | ||
971 | *ccp = str; | |
972 | ||
973 | return reg; | |
974 | } | |
975 | ||
976 | static inline bfd_boolean | |
977 | eq_neon_type_el (struct neon_type_el e1, struct neon_type_el e2) | |
978 | { | |
979 | return | |
980 | e1.type == e2.type | |
981 | && e1.defined == e2.defined | |
982 | && e1.width == e2.width && e1.index == e2.index; | |
983 | } | |
984 | ||
985 | /* This function parses the NEON register list. On success, it returns | |
986 | the parsed register list information in the following encoded format: | |
987 | ||
988 | bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1 | |
989 | 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg | |
990 | ||
991 | The information of the register shape and/or index is returned in | |
992 | *VECTYPE. | |
993 | ||
994 | It returns PARSE_FAIL if the register list is invalid. | |
995 | ||
996 | The list contains one to four registers. | |
997 | Each register can be one of: | |
998 | <Vt>.<T>[<index>] | |
999 | <Vt>.<T> | |
1000 | All <T> should be identical. | |
1001 | All <index> should be identical. | |
1002 | There are restrictions on <Vt> numbers which are checked later | |
1003 | (by reg_list_valid_p). */ | |
1004 | ||
1005 | static int | |
1006 | parse_neon_reg_list (char **ccp, struct neon_type_el *vectype) | |
1007 | { | |
1008 | char *str = *ccp; | |
1009 | int nb_regs; | |
1010 | struct neon_type_el typeinfo, typeinfo_first; | |
1011 | int val, val_range; | |
1012 | int in_range; | |
1013 | int ret_val; | |
1014 | int i; | |
1015 | bfd_boolean error = FALSE; | |
1016 | bfd_boolean expect_index = FALSE; | |
1017 | ||
1018 | if (*str != '{') | |
1019 | { | |
1020 | set_syntax_error (_("expecting {")); | |
1021 | return PARSE_FAIL; | |
1022 | } | |
1023 | str++; | |
1024 | ||
1025 | nb_regs = 0; | |
1026 | typeinfo_first.defined = 0; | |
1027 | typeinfo_first.type = NT_invtype; | |
1028 | typeinfo_first.width = -1; | |
1029 | typeinfo_first.index = 0; | |
1030 | ret_val = 0; | |
1031 | val = -1; | |
1032 | val_range = -1; | |
1033 | in_range = 0; | |
1034 | do | |
1035 | { | |
1036 | if (in_range) | |
1037 | { | |
1038 | str++; /* skip over '-' */ | |
1039 | val_range = val; | |
1040 | } | |
1041 | val = parse_typed_reg (&str, REG_TYPE_VN, NULL, &typeinfo, | |
1042 | /*in_reg_list= */ TRUE); | |
1043 | if (val == PARSE_FAIL) | |
1044 | { | |
1045 | set_first_syntax_error (_("invalid vector register in list")); | |
1046 | error = TRUE; | |
1047 | continue; | |
1048 | } | |
1049 | /* reject [bhsd]n */ | |
1050 | if (typeinfo.defined == 0) | |
1051 | { | |
1052 | set_first_syntax_error (_("invalid scalar register in list")); | |
1053 | error = TRUE; | |
1054 | continue; | |
1055 | } | |
1056 | ||
1057 | if (typeinfo.defined & NTA_HASINDEX) | |
1058 | expect_index = TRUE; | |
1059 | ||
1060 | if (in_range) | |
1061 | { | |
1062 | if (val < val_range) | |
1063 | { | |
1064 | set_first_syntax_error | |
1065 | (_("invalid range in vector register list")); | |
1066 | error = TRUE; | |
1067 | } | |
1068 | val_range++; | |
1069 | } | |
1070 | else | |
1071 | { | |
1072 | val_range = val; | |
1073 | if (nb_regs == 0) | |
1074 | typeinfo_first = typeinfo; | |
1075 | else if (! eq_neon_type_el (typeinfo_first, typeinfo)) | |
1076 | { | |
1077 | set_first_syntax_error | |
1078 | (_("type mismatch in vector register list")); | |
1079 | error = TRUE; | |
1080 | } | |
1081 | } | |
1082 | if (! error) | |
1083 | for (i = val_range; i <= val; i++) | |
1084 | { | |
1085 | ret_val |= i << (5 * nb_regs); | |
1086 | nb_regs++; | |
1087 | } | |
1088 | in_range = 0; | |
1089 | } | |
1090 | while (skip_past_comma (&str) || (in_range = 1, *str == '-')); | |
1091 | ||
1092 | skip_whitespace (str); | |
1093 | if (*str != '}') | |
1094 | { | |
1095 | set_first_syntax_error (_("end of vector register list not found")); | |
1096 | error = TRUE; | |
1097 | } | |
1098 | str++; | |
1099 | ||
1100 | skip_whitespace (str); | |
1101 | ||
1102 | if (expect_index) | |
1103 | { | |
1104 | if (skip_past_char (&str, '[')) | |
1105 | { | |
1106 | expressionS exp; | |
1107 | ||
1108 | my_get_expression (&exp, &str, GE_NO_PREFIX, 1); | |
1109 | if (exp.X_op != O_constant) | |
1110 | { | |
1111 | set_first_syntax_error (_("constant expression required.")); | |
1112 | error = TRUE; | |
1113 | } | |
1114 | if (! skip_past_char (&str, ']')) | |
1115 | error = TRUE; | |
1116 | else | |
1117 | typeinfo_first.index = exp.X_add_number; | |
1118 | } | |
1119 | else | |
1120 | { | |
1121 | set_first_syntax_error (_("expected index")); | |
1122 | error = TRUE; | |
1123 | } | |
1124 | } | |
1125 | ||
1126 | if (nb_regs > 4) | |
1127 | { | |
1128 | set_first_syntax_error (_("too many registers in vector register list")); | |
1129 | error = TRUE; | |
1130 | } | |
1131 | else if (nb_regs == 0) | |
1132 | { | |
1133 | set_first_syntax_error (_("empty vector register list")); | |
1134 | error = TRUE; | |
1135 | } | |
1136 | ||
1137 | *ccp = str; | |
1138 | if (! error) | |
1139 | *vectype = typeinfo_first; | |
1140 | ||
1141 | return error ? PARSE_FAIL : (ret_val << 2) | (nb_regs - 1); | |
1142 | } | |
1143 | ||
1144 | /* Directives: register aliases. */ | |
1145 | ||
1146 | static reg_entry * | |
1147 | insert_reg_alias (char *str, int number, aarch64_reg_type type) | |
1148 | { | |
1149 | reg_entry *new; | |
1150 | const char *name; | |
1151 | ||
1152 | if ((new = hash_find (aarch64_reg_hsh, str)) != 0) | |
1153 | { | |
1154 | if (new->builtin) | |
1155 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), | |
1156 | str); | |
1157 | ||
1158 | /* Only warn about a redefinition if it's not defined as the | |
1159 | same register. */ | |
1160 | else if (new->number != number || new->type != type) | |
1161 | as_warn (_("ignoring redefinition of register alias '%s'"), str); | |
1162 | ||
1163 | return NULL; | |
1164 | } | |
1165 | ||
1166 | name = xstrdup (str); | |
add39d23 | 1167 | new = XNEW (reg_entry); |
a06ea964 NC |
1168 | |
1169 | new->name = name; | |
1170 | new->number = number; | |
1171 | new->type = type; | |
1172 | new->builtin = FALSE; | |
1173 | ||
1174 | if (hash_insert (aarch64_reg_hsh, name, (void *) new)) | |
1175 | abort (); | |
1176 | ||
1177 | return new; | |
1178 | } | |
1179 | ||
1180 | /* Look for the .req directive. This is of the form: | |
1181 | ||
1182 | new_register_name .req existing_register_name | |
1183 | ||
1184 | If we find one, or if it looks sufficiently like one that we want to | |
1185 | handle any error here, return TRUE. Otherwise return FALSE. */ | |
1186 | ||
1187 | static bfd_boolean | |
1188 | create_register_alias (char *newname, char *p) | |
1189 | { | |
1190 | const reg_entry *old; | |
1191 | char *oldname, *nbuf; | |
1192 | size_t nlen; | |
1193 | ||
1194 | /* The input scrubber ensures that whitespace after the mnemonic is | |
1195 | collapsed to single spaces. */ | |
1196 | oldname = p; | |
1197 | if (strncmp (oldname, " .req ", 6) != 0) | |
1198 | return FALSE; | |
1199 | ||
1200 | oldname += 6; | |
1201 | if (*oldname == '\0') | |
1202 | return FALSE; | |
1203 | ||
1204 | old = hash_find (aarch64_reg_hsh, oldname); | |
1205 | if (!old) | |
1206 | { | |
1207 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); | |
1208 | return TRUE; | |
1209 | } | |
1210 | ||
1211 | /* If TC_CASE_SENSITIVE is defined, then newname already points to | |
1212 | the desired alias name, and p points to its end. If not, then | |
1213 | the desired alias name is in the global original_case_string. */ | |
1214 | #ifdef TC_CASE_SENSITIVE | |
1215 | nlen = p - newname; | |
1216 | #else | |
1217 | newname = original_case_string; | |
1218 | nlen = strlen (newname); | |
1219 | #endif | |
1220 | ||
29a2809e | 1221 | nbuf = xmemdup0 (newname, nlen); |
a06ea964 NC |
1222 | |
1223 | /* Create aliases under the new name as stated; an all-lowercase | |
1224 | version of the new name; and an all-uppercase version of the new | |
1225 | name. */ | |
1226 | if (insert_reg_alias (nbuf, old->number, old->type) != NULL) | |
1227 | { | |
1228 | for (p = nbuf; *p; p++) | |
1229 | *p = TOUPPER (*p); | |
1230 | ||
1231 | if (strncmp (nbuf, newname, nlen)) | |
1232 | { | |
1233 | /* If this attempt to create an additional alias fails, do not bother | |
1234 | trying to create the all-lower case alias. We will fail and issue | |
1235 | a second, duplicate error message. This situation arises when the | |
1236 | programmer does something like: | |
1237 | foo .req r0 | |
1238 | Foo .req r1 | |
1239 | The second .req creates the "Foo" alias but then fails to create | |
1240 | the artificial FOO alias because it has already been created by the | |
1241 | first .req. */ | |
1242 | if (insert_reg_alias (nbuf, old->number, old->type) == NULL) | |
e1fa0163 NC |
1243 | { |
1244 | free (nbuf); | |
1245 | return TRUE; | |
1246 | } | |
a06ea964 NC |
1247 | } |
1248 | ||
1249 | for (p = nbuf; *p; p++) | |
1250 | *p = TOLOWER (*p); | |
1251 | ||
1252 | if (strncmp (nbuf, newname, nlen)) | |
1253 | insert_reg_alias (nbuf, old->number, old->type); | |
1254 | } | |
1255 | ||
e1fa0163 | 1256 | free (nbuf); |
a06ea964 NC |
1257 | return TRUE; |
1258 | } | |
1259 | ||
1260 | /* Should never be called, as .req goes between the alias and the | |
1261 | register name, not at the beginning of the line. */ | |
1262 | static void | |
1263 | s_req (int a ATTRIBUTE_UNUSED) | |
1264 | { | |
1265 | as_bad (_("invalid syntax for .req directive")); | |
1266 | } | |
1267 | ||
1268 | /* The .unreq directive deletes an alias which was previously defined | |
1269 | by .req. For example: | |
1270 | ||
1271 | my_alias .req r11 | |
1272 | .unreq my_alias */ | |
1273 | ||
1274 | static void | |
1275 | s_unreq (int a ATTRIBUTE_UNUSED) | |
1276 | { | |
1277 | char *name; | |
1278 | char saved_char; | |
1279 | ||
1280 | name = input_line_pointer; | |
1281 | ||
1282 | while (*input_line_pointer != 0 | |
1283 | && *input_line_pointer != ' ' && *input_line_pointer != '\n') | |
1284 | ++input_line_pointer; | |
1285 | ||
1286 | saved_char = *input_line_pointer; | |
1287 | *input_line_pointer = 0; | |
1288 | ||
1289 | if (!*name) | |
1290 | as_bad (_("invalid syntax for .unreq directive")); | |
1291 | else | |
1292 | { | |
1293 | reg_entry *reg = hash_find (aarch64_reg_hsh, name); | |
1294 | ||
1295 | if (!reg) | |
1296 | as_bad (_("unknown register alias '%s'"), name); | |
1297 | else if (reg->builtin) | |
1298 | as_warn (_("ignoring attempt to undefine built-in register '%s'"), | |
1299 | name); | |
1300 | else | |
1301 | { | |
1302 | char *p; | |
1303 | char *nbuf; | |
1304 | ||
1305 | hash_delete (aarch64_reg_hsh, name, FALSE); | |
1306 | free ((char *) reg->name); | |
1307 | free (reg); | |
1308 | ||
1309 | /* Also locate the all upper case and all lower case versions. | |
1310 | Do not complain if we cannot find one or the other as it | |
1311 | was probably deleted above. */ | |
1312 | ||
1313 | nbuf = strdup (name); | |
1314 | for (p = nbuf; *p; p++) | |
1315 | *p = TOUPPER (*p); | |
1316 | reg = hash_find (aarch64_reg_hsh, nbuf); | |
1317 | if (reg) | |
1318 | { | |
1319 | hash_delete (aarch64_reg_hsh, nbuf, FALSE); | |
1320 | free ((char *) reg->name); | |
1321 | free (reg); | |
1322 | } | |
1323 | ||
1324 | for (p = nbuf; *p; p++) | |
1325 | *p = TOLOWER (*p); | |
1326 | reg = hash_find (aarch64_reg_hsh, nbuf); | |
1327 | if (reg) | |
1328 | { | |
1329 | hash_delete (aarch64_reg_hsh, nbuf, FALSE); | |
1330 | free ((char *) reg->name); | |
1331 | free (reg); | |
1332 | } | |
1333 | ||
1334 | free (nbuf); | |
1335 | } | |
1336 | } | |
1337 | ||
1338 | *input_line_pointer = saved_char; | |
1339 | demand_empty_rest_of_line (); | |
1340 | } | |
1341 | ||
1342 | /* Directives: Instruction set selection. */ | |
1343 | ||
1344 | #ifdef OBJ_ELF | |
1345 | /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF | |
1346 | spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05). | |
1347 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
1348 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
1349 | ||
1350 | /* Create a new mapping symbol for the transition to STATE. */ | |
1351 | ||
1352 | static void | |
1353 | make_mapping_symbol (enum mstate state, valueT value, fragS * frag) | |
1354 | { | |
1355 | symbolS *symbolP; | |
1356 | const char *symname; | |
1357 | int type; | |
1358 | ||
1359 | switch (state) | |
1360 | { | |
1361 | case MAP_DATA: | |
1362 | symname = "$d"; | |
1363 | type = BSF_NO_FLAGS; | |
1364 | break; | |
1365 | case MAP_INSN: | |
1366 | symname = "$x"; | |
1367 | type = BSF_NO_FLAGS; | |
1368 | break; | |
1369 | default: | |
1370 | abort (); | |
1371 | } | |
1372 | ||
1373 | symbolP = symbol_new (symname, now_seg, value, frag); | |
1374 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; | |
1375 | ||
1376 | /* Save the mapping symbols for future reference. Also check that | |
1377 | we do not place two mapping symbols at the same offset within a | |
1378 | frag. We'll handle overlap between frags in | |
1379 | check_mapping_symbols. | |
1380 | ||
1381 | If .fill or other data filling directive generates zero sized data, | |
1382 | the mapping symbol for the following code will have the same value | |
1383 | as the one generated for the data filling directive. In this case, | |
1384 | we replace the old symbol with the new one at the same address. */ | |
1385 | if (value == 0) | |
1386 | { | |
1387 | if (frag->tc_frag_data.first_map != NULL) | |
1388 | { | |
1389 | know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0); | |
1390 | symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, | |
1391 | &symbol_lastP); | |
1392 | } | |
1393 | frag->tc_frag_data.first_map = symbolP; | |
1394 | } | |
1395 | if (frag->tc_frag_data.last_map != NULL) | |
1396 | { | |
1397 | know (S_GET_VALUE (frag->tc_frag_data.last_map) <= | |
1398 | S_GET_VALUE (symbolP)); | |
1399 | if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP)) | |
1400 | symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, | |
1401 | &symbol_lastP); | |
1402 | } | |
1403 | frag->tc_frag_data.last_map = symbolP; | |
1404 | } | |
1405 | ||
1406 | /* We must sometimes convert a region marked as code to data during | |
1407 | code alignment, if an odd number of bytes have to be padded. The | |
1408 | code mapping symbol is pushed to an aligned address. */ | |
1409 | ||
1410 | static void | |
1411 | insert_data_mapping_symbol (enum mstate state, | |
1412 | valueT value, fragS * frag, offsetT bytes) | |
1413 | { | |
1414 | /* If there was already a mapping symbol, remove it. */ | |
1415 | if (frag->tc_frag_data.last_map != NULL | |
1416 | && S_GET_VALUE (frag->tc_frag_data.last_map) == | |
1417 | frag->fr_address + value) | |
1418 | { | |
1419 | symbolS *symp = frag->tc_frag_data.last_map; | |
1420 | ||
1421 | if (value == 0) | |
1422 | { | |
1423 | know (frag->tc_frag_data.first_map == symp); | |
1424 | frag->tc_frag_data.first_map = NULL; | |
1425 | } | |
1426 | frag->tc_frag_data.last_map = NULL; | |
1427 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
1428 | } | |
1429 | ||
1430 | make_mapping_symbol (MAP_DATA, value, frag); | |
1431 | make_mapping_symbol (state, value + bytes, frag); | |
1432 | } | |
1433 | ||
1434 | static void mapping_state_2 (enum mstate state, int max_chars); | |
1435 | ||
1436 | /* Set the mapping state to STATE. Only call this when about to | |
1437 | emit some STATE bytes to the file. */ | |
1438 | ||
1439 | void | |
1440 | mapping_state (enum mstate state) | |
1441 | { | |
1442 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; | |
1443 | ||
a578ef7e JW |
1444 | if (state == MAP_INSN) |
1445 | /* AArch64 instructions require 4-byte alignment. When emitting | |
1446 | instructions into any section, record the appropriate section | |
1447 | alignment. */ | |
1448 | record_alignment (now_seg, 2); | |
1449 | ||
448eb63d RL |
1450 | if (mapstate == state) |
1451 | /* The mapping symbol has already been emitted. | |
1452 | There is nothing else to do. */ | |
1453 | return; | |
1454 | ||
c1baaddf | 1455 | #define TRANSITION(from, to) (mapstate == (from) && state == (to)) |
a97902de RL |
1456 | if (TRANSITION (MAP_UNDEFINED, MAP_DATA) && !subseg_text_p (now_seg)) |
1457 | /* Emit MAP_DATA within executable section in order. Otherwise, it will be | |
c1baaddf | 1458 | evaluated later in the next else. */ |
a06ea964 | 1459 | return; |
c1baaddf RL |
1460 | else if (TRANSITION (MAP_UNDEFINED, MAP_INSN)) |
1461 | { | |
1462 | /* Only add the symbol if the offset is > 0: | |
1463 | if we're at the first frag, check it's size > 0; | |
1464 | if we're not at the first frag, then for sure | |
1465 | the offset is > 0. */ | |
1466 | struct frag *const frag_first = seg_info (now_seg)->frchainP->frch_root; | |
1467 | const int add_symbol = (frag_now != frag_first) | |
1468 | || (frag_now_fix () > 0); | |
1469 | ||
1470 | if (add_symbol) | |
1471 | make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); | |
1472 | } | |
1473 | #undef TRANSITION | |
a06ea964 NC |
1474 | |
1475 | mapping_state_2 (state, 0); | |
a06ea964 NC |
1476 | } |
1477 | ||
1478 | /* Same as mapping_state, but MAX_CHARS bytes have already been | |
1479 | allocated. Put the mapping symbol that far back. */ | |
1480 | ||
1481 | static void | |
1482 | mapping_state_2 (enum mstate state, int max_chars) | |
1483 | { | |
1484 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; | |
1485 | ||
1486 | if (!SEG_NORMAL (now_seg)) | |
1487 | return; | |
1488 | ||
1489 | if (mapstate == state) | |
1490 | /* The mapping symbol has already been emitted. | |
1491 | There is nothing else to do. */ | |
1492 | return; | |
1493 | ||
1494 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; | |
1495 | make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); | |
1496 | } | |
1497 | #else | |
1498 | #define mapping_state(x) /* nothing */ | |
1499 | #define mapping_state_2(x, y) /* nothing */ | |
1500 | #endif | |
1501 | ||
1502 | /* Directives: sectioning and alignment. */ | |
1503 | ||
1504 | static void | |
1505 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
1506 | { | |
1507 | /* We don't support putting frags in the BSS segment, we fake it by | |
1508 | marking in_bss, then looking at s_skip for clues. */ | |
1509 | subseg_set (bss_section, 0); | |
1510 | demand_empty_rest_of_line (); | |
1511 | mapping_state (MAP_DATA); | |
1512 | } | |
1513 | ||
1514 | static void | |
1515 | s_even (int ignore ATTRIBUTE_UNUSED) | |
1516 | { | |
1517 | /* Never make frag if expect extra pass. */ | |
1518 | if (!need_pass_2) | |
1519 | frag_align (1, 0, 0); | |
1520 | ||
1521 | record_alignment (now_seg, 1); | |
1522 | ||
1523 | demand_empty_rest_of_line (); | |
1524 | } | |
1525 | ||
1526 | /* Directives: Literal pools. */ | |
1527 | ||
1528 | static literal_pool * | |
1529 | find_literal_pool (int size) | |
1530 | { | |
1531 | literal_pool *pool; | |
1532 | ||
1533 | for (pool = list_of_pools; pool != NULL; pool = pool->next) | |
1534 | { | |
1535 | if (pool->section == now_seg | |
1536 | && pool->sub_section == now_subseg && pool->size == size) | |
1537 | break; | |
1538 | } | |
1539 | ||
1540 | return pool; | |
1541 | } | |
1542 | ||
1543 | static literal_pool * | |
1544 | find_or_make_literal_pool (int size) | |
1545 | { | |
1546 | /* Next literal pool ID number. */ | |
1547 | static unsigned int latest_pool_num = 1; | |
1548 | literal_pool *pool; | |
1549 | ||
1550 | pool = find_literal_pool (size); | |
1551 | ||
1552 | if (pool == NULL) | |
1553 | { | |
1554 | /* Create a new pool. */ | |
add39d23 | 1555 | pool = XNEW (literal_pool); |
a06ea964 NC |
1556 | if (!pool) |
1557 | return NULL; | |
1558 | ||
1559 | /* Currently we always put the literal pool in the current text | |
1560 | section. If we were generating "small" model code where we | |
1561 | knew that all code and initialised data was within 1MB then | |
1562 | we could output literals to mergeable, read-only data | |
1563 | sections. */ | |
1564 | ||
1565 | pool->next_free_entry = 0; | |
1566 | pool->section = now_seg; | |
1567 | pool->sub_section = now_subseg; | |
1568 | pool->size = size; | |
1569 | pool->next = list_of_pools; | |
1570 | pool->symbol = NULL; | |
1571 | ||
1572 | /* Add it to the list. */ | |
1573 | list_of_pools = pool; | |
1574 | } | |
1575 | ||
1576 | /* New pools, and emptied pools, will have a NULL symbol. */ | |
1577 | if (pool->symbol == NULL) | |
1578 | { | |
1579 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, | |
1580 | (valueT) 0, &zero_address_frag); | |
1581 | pool->id = latest_pool_num++; | |
1582 | } | |
1583 | ||
1584 | /* Done. */ | |
1585 | return pool; | |
1586 | } | |
1587 | ||
1588 | /* Add the literal of size SIZE in *EXP to the relevant literal pool. | |
1589 | Return TRUE on success, otherwise return FALSE. */ | |
1590 | static bfd_boolean | |
1591 | add_to_lit_pool (expressionS *exp, int size) | |
1592 | { | |
1593 | literal_pool *pool; | |
1594 | unsigned int entry; | |
1595 | ||
1596 | pool = find_or_make_literal_pool (size); | |
1597 | ||
1598 | /* Check if this literal value is already in the pool. */ | |
1599 | for (entry = 0; entry < pool->next_free_entry; entry++) | |
1600 | { | |
55d9b4c1 NC |
1601 | expressionS * litexp = & pool->literals[entry].exp; |
1602 | ||
1603 | if ((litexp->X_op == exp->X_op) | |
a06ea964 | 1604 | && (exp->X_op == O_constant) |
55d9b4c1 NC |
1605 | && (litexp->X_add_number == exp->X_add_number) |
1606 | && (litexp->X_unsigned == exp->X_unsigned)) | |
a06ea964 NC |
1607 | break; |
1608 | ||
55d9b4c1 | 1609 | if ((litexp->X_op == exp->X_op) |
a06ea964 | 1610 | && (exp->X_op == O_symbol) |
55d9b4c1 NC |
1611 | && (litexp->X_add_number == exp->X_add_number) |
1612 | && (litexp->X_add_symbol == exp->X_add_symbol) | |
1613 | && (litexp->X_op_symbol == exp->X_op_symbol)) | |
a06ea964 NC |
1614 | break; |
1615 | } | |
1616 | ||
1617 | /* Do we need to create a new entry? */ | |
1618 | if (entry == pool->next_free_entry) | |
1619 | { | |
1620 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
1621 | { | |
1622 | set_syntax_error (_("literal pool overflow")); | |
1623 | return FALSE; | |
1624 | } | |
1625 | ||
55d9b4c1 | 1626 | pool->literals[entry].exp = *exp; |
a06ea964 | 1627 | pool->next_free_entry += 1; |
55d9b4c1 NC |
1628 | if (exp->X_op == O_big) |
1629 | { | |
1630 | /* PR 16688: Bignums are held in a single global array. We must | |
1631 | copy and preserve that value now, before it is overwritten. */ | |
add39d23 TS |
1632 | pool->literals[entry].bignum = XNEWVEC (LITTLENUM_TYPE, |
1633 | exp->X_add_number); | |
55d9b4c1 NC |
1634 | memcpy (pool->literals[entry].bignum, generic_bignum, |
1635 | CHARS_PER_LITTLENUM * exp->X_add_number); | |
1636 | } | |
1637 | else | |
1638 | pool->literals[entry].bignum = NULL; | |
a06ea964 NC |
1639 | } |
1640 | ||
1641 | exp->X_op = O_symbol; | |
1642 | exp->X_add_number = ((int) entry) * size; | |
1643 | exp->X_add_symbol = pool->symbol; | |
1644 | ||
1645 | return TRUE; | |
1646 | } | |
1647 | ||
1648 | /* Can't use symbol_new here, so have to create a symbol and then at | |
1649 | a later date assign it a value. Thats what these functions do. */ | |
1650 | ||
1651 | static void | |
1652 | symbol_locate (symbolS * symbolP, | |
1653 | const char *name,/* It is copied, the caller can modify. */ | |
1654 | segT segment, /* Segment identifier (SEG_<something>). */ | |
1655 | valueT valu, /* Symbol value. */ | |
1656 | fragS * frag) /* Associated fragment. */ | |
1657 | { | |
e57e6ddc | 1658 | size_t name_length; |
a06ea964 NC |
1659 | char *preserved_copy_of_name; |
1660 | ||
1661 | name_length = strlen (name) + 1; /* +1 for \0. */ | |
1662 | obstack_grow (¬es, name, name_length); | |
1663 | preserved_copy_of_name = obstack_finish (¬es); | |
1664 | ||
1665 | #ifdef tc_canonicalize_symbol_name | |
1666 | preserved_copy_of_name = | |
1667 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
1668 | #endif | |
1669 | ||
1670 | S_SET_NAME (symbolP, preserved_copy_of_name); | |
1671 | ||
1672 | S_SET_SEGMENT (symbolP, segment); | |
1673 | S_SET_VALUE (symbolP, valu); | |
1674 | symbol_clear_list_pointers (symbolP); | |
1675 | ||
1676 | symbol_set_frag (symbolP, frag); | |
1677 | ||
1678 | /* Link to end of symbol chain. */ | |
1679 | { | |
1680 | extern int symbol_table_frozen; | |
1681 | ||
1682 | if (symbol_table_frozen) | |
1683 | abort (); | |
1684 | } | |
1685 | ||
1686 | symbol_append (symbolP, symbol_lastP, &symbol_rootP, &symbol_lastP); | |
1687 | ||
1688 | obj_symbol_new_hook (symbolP); | |
1689 | ||
1690 | #ifdef tc_symbol_new_hook | |
1691 | tc_symbol_new_hook (symbolP); | |
1692 | #endif | |
1693 | ||
1694 | #ifdef DEBUG_SYMS | |
1695 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
1696 | #endif /* DEBUG_SYMS */ | |
1697 | } | |
1698 | ||
1699 | ||
1700 | static void | |
1701 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
1702 | { | |
1703 | unsigned int entry; | |
1704 | literal_pool *pool; | |
1705 | char sym_name[20]; | |
1706 | int align; | |
1707 | ||
67a32447 | 1708 | for (align = 2; align <= 4; align++) |
a06ea964 NC |
1709 | { |
1710 | int size = 1 << align; | |
1711 | ||
1712 | pool = find_literal_pool (size); | |
1713 | if (pool == NULL || pool->symbol == NULL || pool->next_free_entry == 0) | |
1714 | continue; | |
1715 | ||
a06ea964 NC |
1716 | /* Align pool as you have word accesses. |
1717 | Only make a frag if we have to. */ | |
1718 | if (!need_pass_2) | |
1719 | frag_align (align, 0, 0); | |
1720 | ||
7ea12e5c NC |
1721 | mapping_state (MAP_DATA); |
1722 | ||
a06ea964 NC |
1723 | record_alignment (now_seg, align); |
1724 | ||
1725 | sprintf (sym_name, "$$lit_\002%x", pool->id); | |
1726 | ||
1727 | symbol_locate (pool->symbol, sym_name, now_seg, | |
1728 | (valueT) frag_now_fix (), frag_now); | |
1729 | symbol_table_insert (pool->symbol); | |
1730 | ||
1731 | for (entry = 0; entry < pool->next_free_entry; entry++) | |
55d9b4c1 NC |
1732 | { |
1733 | expressionS * exp = & pool->literals[entry].exp; | |
1734 | ||
1735 | if (exp->X_op == O_big) | |
1736 | { | |
1737 | /* PR 16688: Restore the global bignum value. */ | |
1738 | gas_assert (pool->literals[entry].bignum != NULL); | |
1739 | memcpy (generic_bignum, pool->literals[entry].bignum, | |
1740 | CHARS_PER_LITTLENUM * exp->X_add_number); | |
1741 | } | |
1742 | ||
1743 | /* First output the expression in the instruction to the pool. */ | |
1744 | emit_expr (exp, size); /* .word|.xword */ | |
1745 | ||
1746 | if (exp->X_op == O_big) | |
1747 | { | |
1748 | free (pool->literals[entry].bignum); | |
1749 | pool->literals[entry].bignum = NULL; | |
1750 | } | |
1751 | } | |
a06ea964 NC |
1752 | |
1753 | /* Mark the pool as empty. */ | |
1754 | pool->next_free_entry = 0; | |
1755 | pool->symbol = NULL; | |
1756 | } | |
1757 | } | |
1758 | ||
1759 | #ifdef OBJ_ELF | |
1760 | /* Forward declarations for functions below, in the MD interface | |
1761 | section. */ | |
1762 | static fixS *fix_new_aarch64 (fragS *, int, short, expressionS *, int, int); | |
1763 | static struct reloc_table_entry * find_reloc_table_entry (char **); | |
1764 | ||
1765 | /* Directives: Data. */ | |
1766 | /* N.B. the support for relocation suffix in this directive needs to be | |
1767 | implemented properly. */ | |
1768 | ||
1769 | static void | |
1770 | s_aarch64_elf_cons (int nbytes) | |
1771 | { | |
1772 | expressionS exp; | |
1773 | ||
1774 | #ifdef md_flush_pending_output | |
1775 | md_flush_pending_output (); | |
1776 | #endif | |
1777 | ||
1778 | if (is_it_end_of_statement ()) | |
1779 | { | |
1780 | demand_empty_rest_of_line (); | |
1781 | return; | |
1782 | } | |
1783 | ||
1784 | #ifdef md_cons_align | |
1785 | md_cons_align (nbytes); | |
1786 | #endif | |
1787 | ||
1788 | mapping_state (MAP_DATA); | |
1789 | do | |
1790 | { | |
1791 | struct reloc_table_entry *reloc; | |
1792 | ||
1793 | expression (&exp); | |
1794 | ||
1795 | if (exp.X_op != O_symbol) | |
1796 | emit_expr (&exp, (unsigned int) nbytes); | |
1797 | else | |
1798 | { | |
1799 | skip_past_char (&input_line_pointer, '#'); | |
1800 | if (skip_past_char (&input_line_pointer, ':')) | |
1801 | { | |
1802 | reloc = find_reloc_table_entry (&input_line_pointer); | |
1803 | if (reloc == NULL) | |
1804 | as_bad (_("unrecognized relocation suffix")); | |
1805 | else | |
1806 | as_bad (_("unimplemented relocation suffix")); | |
1807 | ignore_rest_of_line (); | |
1808 | return; | |
1809 | } | |
1810 | else | |
1811 | emit_expr (&exp, (unsigned int) nbytes); | |
1812 | } | |
1813 | } | |
1814 | while (*input_line_pointer++ == ','); | |
1815 | ||
1816 | /* Put terminator back into stream. */ | |
1817 | input_line_pointer--; | |
1818 | demand_empty_rest_of_line (); | |
1819 | } | |
1820 | ||
1821 | #endif /* OBJ_ELF */ | |
1822 | ||
1823 | /* Output a 32-bit word, but mark as an instruction. */ | |
1824 | ||
1825 | static void | |
1826 | s_aarch64_inst (int ignored ATTRIBUTE_UNUSED) | |
1827 | { | |
1828 | expressionS exp; | |
1829 | ||
1830 | #ifdef md_flush_pending_output | |
1831 | md_flush_pending_output (); | |
1832 | #endif | |
1833 | ||
1834 | if (is_it_end_of_statement ()) | |
1835 | { | |
1836 | demand_empty_rest_of_line (); | |
1837 | return; | |
1838 | } | |
1839 | ||
a97902de | 1840 | /* Sections are assumed to start aligned. In executable section, there is no |
c1baaddf RL |
1841 | MAP_DATA symbol pending. So we only align the address during |
1842 | MAP_DATA --> MAP_INSN transition. | |
eb9d6cc9 | 1843 | For other sections, this is not guaranteed. */ |
c1baaddf | 1844 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
eb9d6cc9 | 1845 | if (!need_pass_2 && subseg_text_p (now_seg) && mapstate == MAP_DATA) |
a06ea964 | 1846 | frag_align_code (2, 0); |
c1baaddf | 1847 | |
a06ea964 NC |
1848 | #ifdef OBJ_ELF |
1849 | mapping_state (MAP_INSN); | |
1850 | #endif | |
1851 | ||
1852 | do | |
1853 | { | |
1854 | expression (&exp); | |
1855 | if (exp.X_op != O_constant) | |
1856 | { | |
1857 | as_bad (_("constant expression required")); | |
1858 | ignore_rest_of_line (); | |
1859 | return; | |
1860 | } | |
1861 | ||
1862 | if (target_big_endian) | |
1863 | { | |
1864 | unsigned int val = exp.X_add_number; | |
1865 | exp.X_add_number = SWAP_32 (val); | |
1866 | } | |
1867 | emit_expr (&exp, 4); | |
1868 | } | |
1869 | while (*input_line_pointer++ == ','); | |
1870 | ||
1871 | /* Put terminator back into stream. */ | |
1872 | input_line_pointer--; | |
1873 | demand_empty_rest_of_line (); | |
1874 | } | |
1875 | ||
1876 | #ifdef OBJ_ELF | |
43a357f9 RL |
1877 | /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */ |
1878 | ||
1879 | static void | |
1880 | s_tlsdescadd (int ignored ATTRIBUTE_UNUSED) | |
1881 | { | |
1882 | expressionS exp; | |
1883 | ||
1884 | expression (&exp); | |
1885 | frag_grow (4); | |
1886 | fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0, | |
1887 | BFD_RELOC_AARCH64_TLSDESC_ADD); | |
1888 | ||
1889 | demand_empty_rest_of_line (); | |
1890 | } | |
1891 | ||
a06ea964 NC |
1892 | /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */ |
1893 | ||
1894 | static void | |
1895 | s_tlsdesccall (int ignored ATTRIBUTE_UNUSED) | |
1896 | { | |
1897 | expressionS exp; | |
1898 | ||
1899 | /* Since we're just labelling the code, there's no need to define a | |
1900 | mapping symbol. */ | |
1901 | expression (&exp); | |
1902 | /* Make sure there is enough room in this frag for the following | |
1903 | blr. This trick only works if the blr follows immediately after | |
1904 | the .tlsdesc directive. */ | |
1905 | frag_grow (4); | |
1906 | fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0, | |
1907 | BFD_RELOC_AARCH64_TLSDESC_CALL); | |
1908 | ||
1909 | demand_empty_rest_of_line (); | |
1910 | } | |
43a357f9 RL |
1911 | |
1912 | /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */ | |
1913 | ||
1914 | static void | |
1915 | s_tlsdescldr (int ignored ATTRIBUTE_UNUSED) | |
1916 | { | |
1917 | expressionS exp; | |
1918 | ||
1919 | expression (&exp); | |
1920 | frag_grow (4); | |
1921 | fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0, | |
1922 | BFD_RELOC_AARCH64_TLSDESC_LDR); | |
1923 | ||
1924 | demand_empty_rest_of_line (); | |
1925 | } | |
a06ea964 NC |
1926 | #endif /* OBJ_ELF */ |
1927 | ||
1928 | static void s_aarch64_arch (int); | |
1929 | static void s_aarch64_cpu (int); | |
ae527cd8 | 1930 | static void s_aarch64_arch_extension (int); |
a06ea964 NC |
1931 | |
1932 | /* This table describes all the machine specific pseudo-ops the assembler | |
1933 | has to support. The fields are: | |
1934 | pseudo-op name without dot | |
1935 | function to call to execute this pseudo-op | |
1936 | Integer arg to pass to the function. */ | |
1937 | ||
1938 | const pseudo_typeS md_pseudo_table[] = { | |
1939 | /* Never called because '.req' does not start a line. */ | |
1940 | {"req", s_req, 0}, | |
1941 | {"unreq", s_unreq, 0}, | |
1942 | {"bss", s_bss, 0}, | |
1943 | {"even", s_even, 0}, | |
1944 | {"ltorg", s_ltorg, 0}, | |
1945 | {"pool", s_ltorg, 0}, | |
1946 | {"cpu", s_aarch64_cpu, 0}, | |
1947 | {"arch", s_aarch64_arch, 0}, | |
ae527cd8 | 1948 | {"arch_extension", s_aarch64_arch_extension, 0}, |
a06ea964 NC |
1949 | {"inst", s_aarch64_inst, 0}, |
1950 | #ifdef OBJ_ELF | |
43a357f9 | 1951 | {"tlsdescadd", s_tlsdescadd, 0}, |
a06ea964 | 1952 | {"tlsdesccall", s_tlsdesccall, 0}, |
43a357f9 | 1953 | {"tlsdescldr", s_tlsdescldr, 0}, |
a06ea964 NC |
1954 | {"word", s_aarch64_elf_cons, 4}, |
1955 | {"long", s_aarch64_elf_cons, 4}, | |
1956 | {"xword", s_aarch64_elf_cons, 8}, | |
1957 | {"dword", s_aarch64_elf_cons, 8}, | |
1958 | #endif | |
1959 | {0, 0, 0} | |
1960 | }; | |
1961 | \f | |
1962 | ||
1963 | /* Check whether STR points to a register name followed by a comma or the | |
1964 | end of line; REG_TYPE indicates which register types are checked | |
1965 | against. Return TRUE if STR is such a register name; otherwise return | |
1966 | FALSE. The function does not intend to produce any diagnostics, but since | |
1967 | the register parser aarch64_reg_parse, which is called by this function, | |
1968 | does produce diagnostics, we call clear_error to clear any diagnostics | |
1969 | that may be generated by aarch64_reg_parse. | |
1970 | Also, the function returns FALSE directly if there is any user error | |
1971 | present at the function entry. This prevents the existing diagnostics | |
1972 | state from being spoiled. | |
1973 | The function currently serves parse_constant_immediate and | |
1974 | parse_big_immediate only. */ | |
1975 | static bfd_boolean | |
1976 | reg_name_p (char *str, aarch64_reg_type reg_type) | |
1977 | { | |
1978 | int reg; | |
1979 | ||
1980 | /* Prevent the diagnostics state from being spoiled. */ | |
1981 | if (error_p ()) | |
1982 | return FALSE; | |
1983 | ||
1984 | reg = aarch64_reg_parse (&str, reg_type, NULL, NULL); | |
1985 | ||
1986 | /* Clear the parsing error that may be set by the reg parser. */ | |
1987 | clear_error (); | |
1988 | ||
1989 | if (reg == PARSE_FAIL) | |
1990 | return FALSE; | |
1991 | ||
1992 | skip_whitespace (str); | |
1993 | if (*str == ',' || is_end_of_line[(unsigned int) *str]) | |
1994 | return TRUE; | |
1995 | ||
1996 | return FALSE; | |
1997 | } | |
1998 | ||
1999 | /* Parser functions used exclusively in instruction operands. */ | |
2000 | ||
2001 | /* Parse an immediate expression which may not be constant. | |
2002 | ||
2003 | To prevent the expression parser from pushing a register name | |
2004 | into the symbol table as an undefined symbol, firstly a check is | |
2005 | done to find out whether STR is a valid register name followed | |
2006 | by a comma or the end of line. Return FALSE if STR is such a | |
2007 | string. */ | |
2008 | ||
2009 | static bfd_boolean | |
2010 | parse_immediate_expression (char **str, expressionS *exp) | |
2011 | { | |
2012 | if (reg_name_p (*str, REG_TYPE_R_Z_BHSDQ_V)) | |
2013 | { | |
2014 | set_recoverable_error (_("immediate operand required")); | |
2015 | return FALSE; | |
2016 | } | |
2017 | ||
2018 | my_get_expression (exp, str, GE_OPT_PREFIX, 1); | |
2019 | ||
2020 | if (exp->X_op == O_absent) | |
2021 | { | |
2022 | set_fatal_syntax_error (_("missing immediate expression")); | |
2023 | return FALSE; | |
2024 | } | |
2025 | ||
2026 | return TRUE; | |
2027 | } | |
2028 | ||
2029 | /* Constant immediate-value read function for use in insn parsing. | |
2030 | STR points to the beginning of the immediate (with the optional | |
2031 | leading #); *VAL receives the value. | |
2032 | ||
2033 | Return TRUE on success; otherwise return FALSE. */ | |
2034 | ||
2035 | static bfd_boolean | |
2036 | parse_constant_immediate (char **str, int64_t * val) | |
2037 | { | |
2038 | expressionS exp; | |
2039 | ||
2040 | if (! parse_immediate_expression (str, &exp)) | |
2041 | return FALSE; | |
2042 | ||
2043 | if (exp.X_op != O_constant) | |
2044 | { | |
2045 | set_syntax_error (_("constant expression required")); | |
2046 | return FALSE; | |
2047 | } | |
2048 | ||
2049 | *val = exp.X_add_number; | |
2050 | return TRUE; | |
2051 | } | |
2052 | ||
2053 | static uint32_t | |
2054 | encode_imm_float_bits (uint32_t imm) | |
2055 | { | |
2056 | return ((imm >> 19) & 0x7f) /* b[25:19] -> b[6:0] */ | |
2057 | | ((imm >> (31 - 7)) & 0x80); /* b[31] -> b[7] */ | |
2058 | } | |
2059 | ||
62b0d0d5 YZ |
2060 | /* Return TRUE if the single-precision floating-point value encoded in IMM |
2061 | can be expressed in the AArch64 8-bit signed floating-point format with | |
2062 | 3-bit exponent and normalized 4 bits of precision; in other words, the | |
2063 | floating-point value must be expressable as | |
2064 | (+/-) n / 16 * power (2, r) | |
2065 | where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */ | |
2066 | ||
a06ea964 NC |
2067 | static bfd_boolean |
2068 | aarch64_imm_float_p (uint32_t imm) | |
2069 | { | |
62b0d0d5 YZ |
2070 | /* If a single-precision floating-point value has the following bit |
2071 | pattern, it can be expressed in the AArch64 8-bit floating-point | |
2072 | format: | |
2073 | ||
2074 | 3 32222222 2221111111111 | |
a06ea964 | 2075 | 1 09876543 21098765432109876543210 |
62b0d0d5 YZ |
2076 | n Eeeeeexx xxxx0000000000000000000 |
2077 | ||
2078 | where n, e and each x are either 0 or 1 independently, with | |
2079 | E == ~ e. */ | |
a06ea964 | 2080 | |
62b0d0d5 YZ |
2081 | uint32_t pattern; |
2082 | ||
2083 | /* Prepare the pattern for 'Eeeeee'. */ | |
2084 | if (((imm >> 30) & 0x1) == 0) | |
2085 | pattern = 0x3e000000; | |
a06ea964 | 2086 | else |
62b0d0d5 YZ |
2087 | pattern = 0x40000000; |
2088 | ||
2089 | return (imm & 0x7ffff) == 0 /* lower 19 bits are 0. */ | |
2090 | && ((imm & 0x7e000000) == pattern); /* bits 25 - 29 == ~ bit 30. */ | |
a06ea964 NC |
2091 | } |
2092 | ||
62b0d0d5 YZ |
2093 | /* Like aarch64_imm_float_p but for a double-precision floating-point value. |
2094 | ||
2095 | Return TRUE if the value encoded in IMM can be expressed in the AArch64 | |
2096 | 8-bit signed floating-point format with 3-bit exponent and normalized 4 | |
2097 | bits of precision (i.e. can be used in an FMOV instruction); return the | |
2098 | equivalent single-precision encoding in *FPWORD. | |
2099 | ||
2100 | Otherwise return FALSE. */ | |
2101 | ||
a06ea964 | 2102 | static bfd_boolean |
62b0d0d5 YZ |
2103 | aarch64_double_precision_fmovable (uint64_t imm, uint32_t *fpword) |
2104 | { | |
2105 | /* If a double-precision floating-point value has the following bit | |
2106 | pattern, it can be expressed in the AArch64 8-bit floating-point | |
2107 | format: | |
2108 | ||
2109 | 6 66655555555 554444444...21111111111 | |
2110 | 3 21098765432 109876543...098765432109876543210 | |
2111 | n Eeeeeeeeexx xxxx00000...000000000000000000000 | |
2112 | ||
2113 | where n, e and each x are either 0 or 1 independently, with | |
2114 | E == ~ e. */ | |
2115 | ||
2116 | uint32_t pattern; | |
2117 | uint32_t high32 = imm >> 32; | |
2118 | ||
2119 | /* Lower 32 bits need to be 0s. */ | |
2120 | if ((imm & 0xffffffff) != 0) | |
2121 | return FALSE; | |
2122 | ||
2123 | /* Prepare the pattern for 'Eeeeeeeee'. */ | |
2124 | if (((high32 >> 30) & 0x1) == 0) | |
2125 | pattern = 0x3fc00000; | |
2126 | else | |
2127 | pattern = 0x40000000; | |
2128 | ||
2129 | if ((high32 & 0xffff) == 0 /* bits 32 - 47 are 0. */ | |
2130 | && (high32 & 0x7fc00000) == pattern) /* bits 54 - 61 == ~ bit 62. */ | |
2131 | { | |
2132 | /* Convert to the single-precision encoding. | |
2133 | i.e. convert | |
2134 | n Eeeeeeeeexx xxxx00000...000000000000000000000 | |
2135 | to | |
2136 | n Eeeeeexx xxxx0000000000000000000. */ | |
2137 | *fpword = ((high32 & 0xfe000000) /* nEeeeee. */ | |
2138 | | (((high32 >> 16) & 0x3f) << 19)); /* xxxxxx. */ | |
2139 | return TRUE; | |
2140 | } | |
2141 | else | |
2142 | return FALSE; | |
2143 | } | |
2144 | ||
2145 | /* Parse a floating-point immediate. Return TRUE on success and return the | |
2146 | value in *IMMED in the format of IEEE754 single-precision encoding. | |
2147 | *CCP points to the start of the string; DP_P is TRUE when the immediate | |
2148 | is expected to be in double-precision (N.B. this only matters when | |
2149 | hexadecimal representation is involved). | |
2150 | ||
2151 | N.B. 0.0 is accepted by this function. */ | |
2152 | ||
2153 | static bfd_boolean | |
2154 | parse_aarch64_imm_float (char **ccp, int *immed, bfd_boolean dp_p) | |
a06ea964 NC |
2155 | { |
2156 | char *str = *ccp; | |
2157 | char *fpnum; | |
2158 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
2159 | int found_fpchar = 0; | |
62b0d0d5 YZ |
2160 | int64_t val = 0; |
2161 | unsigned fpword = 0; | |
2162 | bfd_boolean hex_p = FALSE; | |
a06ea964 NC |
2163 | |
2164 | skip_past_char (&str, '#'); | |
2165 | ||
a06ea964 NC |
2166 | fpnum = str; |
2167 | skip_whitespace (fpnum); | |
2168 | ||
2169 | if (strncmp (fpnum, "0x", 2) == 0) | |
62b0d0d5 YZ |
2170 | { |
2171 | /* Support the hexadecimal representation of the IEEE754 encoding. | |
2172 | Double-precision is expected when DP_P is TRUE, otherwise the | |
2173 | representation should be in single-precision. */ | |
2174 | if (! parse_constant_immediate (&str, &val)) | |
2175 | goto invalid_fp; | |
2176 | ||
2177 | if (dp_p) | |
2178 | { | |
2179 | if (! aarch64_double_precision_fmovable (val, &fpword)) | |
2180 | goto invalid_fp; | |
2181 | } | |
2182 | else if ((uint64_t) val > 0xffffffff) | |
2183 | goto invalid_fp; | |
2184 | else | |
2185 | fpword = val; | |
2186 | ||
2187 | hex_p = TRUE; | |
2188 | } | |
a06ea964 NC |
2189 | else |
2190 | { | |
62b0d0d5 YZ |
2191 | /* We must not accidentally parse an integer as a floating-point number. |
2192 | Make sure that the value we parse is not an integer by checking for | |
2193 | special characters '.' or 'e'. */ | |
a06ea964 NC |
2194 | for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) |
2195 | if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') | |
2196 | { | |
2197 | found_fpchar = 1; | |
2198 | break; | |
2199 | } | |
2200 | ||
2201 | if (!found_fpchar) | |
2202 | return FALSE; | |
2203 | } | |
2204 | ||
62b0d0d5 | 2205 | if (! hex_p) |
a06ea964 | 2206 | { |
a06ea964 NC |
2207 | int i; |
2208 | ||
62b0d0d5 YZ |
2209 | if ((str = atof_ieee (str, 's', words)) == NULL) |
2210 | goto invalid_fp; | |
2211 | ||
a06ea964 NC |
2212 | /* Our FP word must be 32 bits (single-precision FP). */ |
2213 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) | |
2214 | { | |
2215 | fpword <<= LITTLENUM_NUMBER_OF_BITS; | |
2216 | fpword |= words[i]; | |
2217 | } | |
62b0d0d5 | 2218 | } |
a06ea964 | 2219 | |
dbd8770c | 2220 | if (aarch64_imm_float_p (fpword) || fpword == 0) |
62b0d0d5 YZ |
2221 | { |
2222 | *immed = fpword; | |
a06ea964 | 2223 | *ccp = str; |
a06ea964 NC |
2224 | return TRUE; |
2225 | } | |
2226 | ||
2227 | invalid_fp: | |
2228 | set_fatal_syntax_error (_("invalid floating-point constant")); | |
2229 | return FALSE; | |
2230 | } | |
2231 | ||
2232 | /* Less-generic immediate-value read function with the possibility of loading | |
2233 | a big (64-bit) immediate, as required by AdvSIMD Modified immediate | |
2234 | instructions. | |
2235 | ||
2236 | To prevent the expression parser from pushing a register name into the | |
2237 | symbol table as an undefined symbol, a check is firstly done to find | |
2238 | out whether STR is a valid register name followed by a comma or the end | |
2239 | of line. Return FALSE if STR is such a register. */ | |
2240 | ||
2241 | static bfd_boolean | |
2242 | parse_big_immediate (char **str, int64_t *imm) | |
2243 | { | |
2244 | char *ptr = *str; | |
2245 | ||
2246 | if (reg_name_p (ptr, REG_TYPE_R_Z_BHSDQ_V)) | |
2247 | { | |
2248 | set_syntax_error (_("immediate operand required")); | |
2249 | return FALSE; | |
2250 | } | |
2251 | ||
2252 | my_get_expression (&inst.reloc.exp, &ptr, GE_OPT_PREFIX, 1); | |
2253 | ||
2254 | if (inst.reloc.exp.X_op == O_constant) | |
2255 | *imm = inst.reloc.exp.X_add_number; | |
2256 | ||
2257 | *str = ptr; | |
2258 | ||
2259 | return TRUE; | |
2260 | } | |
2261 | ||
2262 | /* Set operand IDX of the *INSTR that needs a GAS internal fixup. | |
2263 | if NEED_LIBOPCODES is non-zero, the fixup will need | |
2264 | assistance from the libopcodes. */ | |
2265 | ||
2266 | static inline void | |
2267 | aarch64_set_gas_internal_fixup (struct reloc *reloc, | |
2268 | const aarch64_opnd_info *operand, | |
2269 | int need_libopcodes_p) | |
2270 | { | |
2271 | reloc->type = BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP; | |
2272 | reloc->opnd = operand->type; | |
2273 | if (need_libopcodes_p) | |
2274 | reloc->need_libopcodes_p = 1; | |
2275 | }; | |
2276 | ||
2277 | /* Return TRUE if the instruction needs to be fixed up later internally by | |
2278 | the GAS; otherwise return FALSE. */ | |
2279 | ||
2280 | static inline bfd_boolean | |
2281 | aarch64_gas_internal_fixup_p (void) | |
2282 | { | |
2283 | return inst.reloc.type == BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP; | |
2284 | } | |
2285 | ||
2286 | /* Assign the immediate value to the relavant field in *OPERAND if | |
2287 | RELOC->EXP is a constant expression; otherwise, flag that *OPERAND | |
2288 | needs an internal fixup in a later stage. | |
2289 | ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or | |
2290 | IMM.VALUE that may get assigned with the constant. */ | |
2291 | static inline void | |
2292 | assign_imm_if_const_or_fixup_later (struct reloc *reloc, | |
2293 | aarch64_opnd_info *operand, | |
2294 | int addr_off_p, | |
2295 | int need_libopcodes_p, | |
2296 | int skip_p) | |
2297 | { | |
2298 | if (reloc->exp.X_op == O_constant) | |
2299 | { | |
2300 | if (addr_off_p) | |
2301 | operand->addr.offset.imm = reloc->exp.X_add_number; | |
2302 | else | |
2303 | operand->imm.value = reloc->exp.X_add_number; | |
2304 | reloc->type = BFD_RELOC_UNUSED; | |
2305 | } | |
2306 | else | |
2307 | { | |
2308 | aarch64_set_gas_internal_fixup (reloc, operand, need_libopcodes_p); | |
2309 | /* Tell libopcodes to ignore this operand or not. This is helpful | |
2310 | when one of the operands needs to be fixed up later but we need | |
2311 | libopcodes to check the other operands. */ | |
2312 | operand->skip = skip_p; | |
2313 | } | |
2314 | } | |
2315 | ||
2316 | /* Relocation modifiers. Each entry in the table contains the textual | |
2317 | name for the relocation which may be placed before a symbol used as | |
2318 | a load/store offset, or add immediate. It must be surrounded by a | |
2319 | leading and trailing colon, for example: | |
2320 | ||
2321 | ldr x0, [x1, #:rello:varsym] | |
2322 | add x0, x1, #:rello:varsym */ | |
2323 | ||
2324 | struct reloc_table_entry | |
2325 | { | |
2326 | const char *name; | |
2327 | int pc_rel; | |
6f4a313b | 2328 | bfd_reloc_code_real_type adr_type; |
a06ea964 NC |
2329 | bfd_reloc_code_real_type adrp_type; |
2330 | bfd_reloc_code_real_type movw_type; | |
2331 | bfd_reloc_code_real_type add_type; | |
2332 | bfd_reloc_code_real_type ldst_type; | |
74ad790c | 2333 | bfd_reloc_code_real_type ld_literal_type; |
a06ea964 NC |
2334 | }; |
2335 | ||
2336 | static struct reloc_table_entry reloc_table[] = { | |
2337 | /* Low 12 bits of absolute address: ADD/i and LDR/STR */ | |
2338 | {"lo12", 0, | |
6f4a313b | 2339 | 0, /* adr_type */ |
a06ea964 NC |
2340 | 0, |
2341 | 0, | |
2342 | BFD_RELOC_AARCH64_ADD_LO12, | |
74ad790c MS |
2343 | BFD_RELOC_AARCH64_LDST_LO12, |
2344 | 0}, | |
a06ea964 NC |
2345 | |
2346 | /* Higher 21 bits of pc-relative page offset: ADRP */ | |
2347 | {"pg_hi21", 1, | |
6f4a313b | 2348 | 0, /* adr_type */ |
a06ea964 NC |
2349 | BFD_RELOC_AARCH64_ADR_HI21_PCREL, |
2350 | 0, | |
2351 | 0, | |
74ad790c | 2352 | 0, |
a06ea964 NC |
2353 | 0}, |
2354 | ||
2355 | /* Higher 21 bits of pc-relative page offset: ADRP, no check */ | |
2356 | {"pg_hi21_nc", 1, | |
6f4a313b | 2357 | 0, /* adr_type */ |
a06ea964 NC |
2358 | BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL, |
2359 | 0, | |
2360 | 0, | |
74ad790c | 2361 | 0, |
a06ea964 NC |
2362 | 0}, |
2363 | ||
2364 | /* Most significant bits 0-15 of unsigned address/value: MOVZ */ | |
2365 | {"abs_g0", 0, | |
6f4a313b | 2366 | 0, /* adr_type */ |
a06ea964 NC |
2367 | 0, |
2368 | BFD_RELOC_AARCH64_MOVW_G0, | |
2369 | 0, | |
74ad790c | 2370 | 0, |
a06ea964 NC |
2371 | 0}, |
2372 | ||
2373 | /* Most significant bits 0-15 of signed address/value: MOVN/Z */ | |
2374 | {"abs_g0_s", 0, | |
6f4a313b | 2375 | 0, /* adr_type */ |
a06ea964 NC |
2376 | 0, |
2377 | BFD_RELOC_AARCH64_MOVW_G0_S, | |
2378 | 0, | |
74ad790c | 2379 | 0, |
a06ea964 NC |
2380 | 0}, |
2381 | ||
2382 | /* Less significant bits 0-15 of address/value: MOVK, no check */ | |
2383 | {"abs_g0_nc", 0, | |
6f4a313b | 2384 | 0, /* adr_type */ |
a06ea964 NC |
2385 | 0, |
2386 | BFD_RELOC_AARCH64_MOVW_G0_NC, | |
2387 | 0, | |
74ad790c | 2388 | 0, |
a06ea964 NC |
2389 | 0}, |
2390 | ||
2391 | /* Most significant bits 16-31 of unsigned address/value: MOVZ */ | |
2392 | {"abs_g1", 0, | |
6f4a313b | 2393 | 0, /* adr_type */ |
a06ea964 NC |
2394 | 0, |
2395 | BFD_RELOC_AARCH64_MOVW_G1, | |
2396 | 0, | |
74ad790c | 2397 | 0, |
a06ea964 NC |
2398 | 0}, |
2399 | ||
2400 | /* Most significant bits 16-31 of signed address/value: MOVN/Z */ | |
2401 | {"abs_g1_s", 0, | |
6f4a313b | 2402 | 0, /* adr_type */ |
a06ea964 NC |
2403 | 0, |
2404 | BFD_RELOC_AARCH64_MOVW_G1_S, | |
2405 | 0, | |
74ad790c | 2406 | 0, |
a06ea964 NC |
2407 | 0}, |
2408 | ||
2409 | /* Less significant bits 16-31 of address/value: MOVK, no check */ | |
2410 | {"abs_g1_nc", 0, | |
6f4a313b | 2411 | 0, /* adr_type */ |
a06ea964 NC |
2412 | 0, |
2413 | BFD_RELOC_AARCH64_MOVW_G1_NC, | |
2414 | 0, | |
74ad790c | 2415 | 0, |
a06ea964 NC |
2416 | 0}, |
2417 | ||
2418 | /* Most significant bits 32-47 of unsigned address/value: MOVZ */ | |
2419 | {"abs_g2", 0, | |
6f4a313b | 2420 | 0, /* adr_type */ |
a06ea964 NC |
2421 | 0, |
2422 | BFD_RELOC_AARCH64_MOVW_G2, | |
2423 | 0, | |
74ad790c | 2424 | 0, |
a06ea964 NC |
2425 | 0}, |
2426 | ||
2427 | /* Most significant bits 32-47 of signed address/value: MOVN/Z */ | |
2428 | {"abs_g2_s", 0, | |
6f4a313b | 2429 | 0, /* adr_type */ |
a06ea964 NC |
2430 | 0, |
2431 | BFD_RELOC_AARCH64_MOVW_G2_S, | |
2432 | 0, | |
74ad790c | 2433 | 0, |
a06ea964 NC |
2434 | 0}, |
2435 | ||
2436 | /* Less significant bits 32-47 of address/value: MOVK, no check */ | |
2437 | {"abs_g2_nc", 0, | |
6f4a313b | 2438 | 0, /* adr_type */ |
a06ea964 NC |
2439 | 0, |
2440 | BFD_RELOC_AARCH64_MOVW_G2_NC, | |
2441 | 0, | |
74ad790c | 2442 | 0, |
a06ea964 NC |
2443 | 0}, |
2444 | ||
2445 | /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */ | |
2446 | {"abs_g3", 0, | |
6f4a313b | 2447 | 0, /* adr_type */ |
a06ea964 NC |
2448 | 0, |
2449 | BFD_RELOC_AARCH64_MOVW_G3, | |
2450 | 0, | |
74ad790c | 2451 | 0, |
a06ea964 | 2452 | 0}, |
4aa2c5e2 | 2453 | |
a06ea964 NC |
2454 | /* Get to the page containing GOT entry for a symbol. */ |
2455 | {"got", 1, | |
6f4a313b | 2456 | 0, /* adr_type */ |
a06ea964 NC |
2457 | BFD_RELOC_AARCH64_ADR_GOT_PAGE, |
2458 | 0, | |
2459 | 0, | |
74ad790c | 2460 | 0, |
4aa2c5e2 MS |
2461 | BFD_RELOC_AARCH64_GOT_LD_PREL19}, |
2462 | ||
a06ea964 NC |
2463 | /* 12 bit offset into the page containing GOT entry for that symbol. */ |
2464 | {"got_lo12", 0, | |
6f4a313b | 2465 | 0, /* adr_type */ |
a06ea964 NC |
2466 | 0, |
2467 | 0, | |
2468 | 0, | |
74ad790c MS |
2469 | BFD_RELOC_AARCH64_LD_GOT_LO12_NC, |
2470 | 0}, | |
a06ea964 | 2471 | |
ca632371 RL |
2472 | /* 0-15 bits of address/value: MOVk, no check. */ |
2473 | {"gotoff_g0_nc", 0, | |
2474 | 0, /* adr_type */ | |
2475 | 0, | |
2476 | BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC, | |
2477 | 0, | |
2478 | 0, | |
2479 | 0}, | |
2480 | ||
654248e7 RL |
2481 | /* Most significant bits 16-31 of address/value: MOVZ. */ |
2482 | {"gotoff_g1", 0, | |
2483 | 0, /* adr_type */ | |
2484 | 0, | |
2485 | BFD_RELOC_AARCH64_MOVW_GOTOFF_G1, | |
2486 | 0, | |
2487 | 0, | |
2488 | 0}, | |
2489 | ||
87f5fbcc RL |
2490 | /* 15 bit offset into the page containing GOT entry for that symbol. */ |
2491 | {"gotoff_lo15", 0, | |
2492 | 0, /* adr_type */ | |
2493 | 0, | |
2494 | 0, | |
2495 | 0, | |
2496 | BFD_RELOC_AARCH64_LD64_GOTOFF_LO15, | |
2497 | 0}, | |
2498 | ||
3b957e5b RL |
2499 | /* Get to the page containing GOT TLS entry for a symbol */ |
2500 | {"gottprel_g0_nc", 0, | |
2501 | 0, /* adr_type */ | |
2502 | 0, | |
2503 | BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC, | |
2504 | 0, | |
2505 | 0, | |
2506 | 0}, | |
2507 | ||
2508 | /* Get to the page containing GOT TLS entry for a symbol */ | |
2509 | {"gottprel_g1", 0, | |
2510 | 0, /* adr_type */ | |
2511 | 0, | |
2512 | BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1, | |
2513 | 0, | |
2514 | 0, | |
2515 | 0}, | |
2516 | ||
a06ea964 NC |
2517 | /* Get to the page containing GOT TLS entry for a symbol */ |
2518 | {"tlsgd", 0, | |
3c12b054 | 2519 | BFD_RELOC_AARCH64_TLSGD_ADR_PREL21, /* adr_type */ |
a06ea964 NC |
2520 | BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21, |
2521 | 0, | |
2522 | 0, | |
74ad790c | 2523 | 0, |
a06ea964 NC |
2524 | 0}, |
2525 | ||
2526 | /* 12 bit offset into the page containing GOT TLS entry for a symbol */ | |
2527 | {"tlsgd_lo12", 0, | |
6f4a313b | 2528 | 0, /* adr_type */ |
a06ea964 NC |
2529 | 0, |
2530 | 0, | |
2531 | BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC, | |
74ad790c | 2532 | 0, |
a06ea964 NC |
2533 | 0}, |
2534 | ||
3e8286c0 RL |
2535 | /* Lower 16 bits address/value: MOVk. */ |
2536 | {"tlsgd_g0_nc", 0, | |
2537 | 0, /* adr_type */ | |
2538 | 0, | |
2539 | BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC, | |
2540 | 0, | |
2541 | 0, | |
2542 | 0}, | |
2543 | ||
1aa66fb1 RL |
2544 | /* Most significant bits 16-31 of address/value: MOVZ. */ |
2545 | {"tlsgd_g1", 0, | |
2546 | 0, /* adr_type */ | |
2547 | 0, | |
2548 | BFD_RELOC_AARCH64_TLSGD_MOVW_G1, | |
2549 | 0, | |
2550 | 0, | |
2551 | 0}, | |
2552 | ||
a06ea964 NC |
2553 | /* Get to the page containing GOT TLS entry for a symbol */ |
2554 | {"tlsdesc", 0, | |
389b8029 | 2555 | BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21, /* adr_type */ |
418009c2 | 2556 | BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21, |
a06ea964 NC |
2557 | 0, |
2558 | 0, | |
74ad790c | 2559 | 0, |
1ada945d | 2560 | BFD_RELOC_AARCH64_TLSDESC_LD_PREL19}, |
a06ea964 NC |
2561 | |
2562 | /* 12 bit offset into the page containing GOT TLS entry for a symbol */ | |
2563 | {"tlsdesc_lo12", 0, | |
6f4a313b | 2564 | 0, /* adr_type */ |
a06ea964 NC |
2565 | 0, |
2566 | 0, | |
2567 | BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC, | |
74ad790c MS |
2568 | BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC, |
2569 | 0}, | |
a06ea964 | 2570 | |
6c37fedc JW |
2571 | /* Get to the page containing GOT TLS entry for a symbol. |
2572 | The same as GD, we allocate two consecutive GOT slots | |
2573 | for module index and module offset, the only difference | |
2574 | with GD is the module offset should be intialized to | |
2575 | zero without any outstanding runtime relocation. */ | |
2576 | {"tlsldm", 0, | |
2577 | BFD_RELOC_AARCH64_TLSLD_ADR_PREL21, /* adr_type */ | |
1107e076 | 2578 | BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21, |
6c37fedc JW |
2579 | 0, |
2580 | 0, | |
2581 | 0, | |
2582 | 0}, | |
2583 | ||
a12fad50 JW |
2584 | /* 12 bit offset into the page containing GOT TLS entry for a symbol */ |
2585 | {"tlsldm_lo12_nc", 0, | |
2586 | 0, /* adr_type */ | |
2587 | 0, | |
2588 | 0, | |
2589 | BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC, | |
2590 | 0, | |
2591 | 0}, | |
2592 | ||
70151fb5 JW |
2593 | /* 12 bit offset into the module TLS base address. */ |
2594 | {"dtprel_lo12", 0, | |
2595 | 0, /* adr_type */ | |
2596 | 0, | |
2597 | 0, | |
2598 | BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12, | |
4c562523 | 2599 | BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, |
70151fb5 JW |
2600 | 0}, |
2601 | ||
13289c10 JW |
2602 | /* Same as dtprel_lo12, no overflow check. */ |
2603 | {"dtprel_lo12_nc", 0, | |
2604 | 0, /* adr_type */ | |
2605 | 0, | |
2606 | 0, | |
2607 | BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC, | |
4c562523 | 2608 | BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC, |
13289c10 JW |
2609 | 0}, |
2610 | ||
49df5539 JW |
2611 | /* bits[23:12] of offset to the module TLS base address. */ |
2612 | {"dtprel_hi12", 0, | |
2613 | 0, /* adr_type */ | |
2614 | 0, | |
2615 | 0, | |
2616 | BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12, | |
2617 | 0, | |
2618 | 0}, | |
2619 | ||
2620 | /* bits[15:0] of offset to the module TLS base address. */ | |
2621 | {"dtprel_g0", 0, | |
2622 | 0, /* adr_type */ | |
2623 | 0, | |
2624 | BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0, | |
2625 | 0, | |
2626 | 0, | |
2627 | 0}, | |
2628 | ||
2629 | /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */ | |
2630 | {"dtprel_g0_nc", 0, | |
2631 | 0, /* adr_type */ | |
2632 | 0, | |
2633 | BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC, | |
2634 | 0, | |
2635 | 0, | |
2636 | 0}, | |
2637 | ||
2638 | /* bits[31:16] of offset to the module TLS base address. */ | |
2639 | {"dtprel_g1", 0, | |
2640 | 0, /* adr_type */ | |
2641 | 0, | |
2642 | BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1, | |
2643 | 0, | |
2644 | 0, | |
2645 | 0}, | |
2646 | ||
2647 | /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */ | |
2648 | {"dtprel_g1_nc", 0, | |
2649 | 0, /* adr_type */ | |
2650 | 0, | |
2651 | BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC, | |
2652 | 0, | |
2653 | 0, | |
2654 | 0}, | |
2655 | ||
2656 | /* bits[47:32] of offset to the module TLS base address. */ | |
2657 | {"dtprel_g2", 0, | |
2658 | 0, /* adr_type */ | |
2659 | 0, | |
2660 | BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2, | |
2661 | 0, | |
2662 | 0, | |
2663 | 0}, | |
2664 | ||
43a357f9 RL |
2665 | /* Lower 16 bit offset into GOT entry for a symbol */ |
2666 | {"tlsdesc_off_g0_nc", 0, | |
2667 | 0, /* adr_type */ | |
2668 | 0, | |
2669 | BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC, | |
2670 | 0, | |
2671 | 0, | |
2672 | 0}, | |
2673 | ||
2674 | /* Higher 16 bit offset into GOT entry for a symbol */ | |
2675 | {"tlsdesc_off_g1", 0, | |
2676 | 0, /* adr_type */ | |
2677 | 0, | |
2678 | BFD_RELOC_AARCH64_TLSDESC_OFF_G1, | |
2679 | 0, | |
2680 | 0, | |
2681 | 0}, | |
2682 | ||
a06ea964 NC |
2683 | /* Get to the page containing GOT TLS entry for a symbol */ |
2684 | {"gottprel", 0, | |
6f4a313b | 2685 | 0, /* adr_type */ |
a06ea964 NC |
2686 | BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, |
2687 | 0, | |
2688 | 0, | |
74ad790c | 2689 | 0, |
043bf05a | 2690 | BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19}, |
a06ea964 NC |
2691 | |
2692 | /* 12 bit offset into the page containing GOT TLS entry for a symbol */ | |
2693 | {"gottprel_lo12", 0, | |
6f4a313b | 2694 | 0, /* adr_type */ |
a06ea964 NC |
2695 | 0, |
2696 | 0, | |
2697 | 0, | |
74ad790c MS |
2698 | BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC, |
2699 | 0}, | |
a06ea964 NC |
2700 | |
2701 | /* Get tp offset for a symbol. */ | |
2702 | {"tprel", 0, | |
6f4a313b | 2703 | 0, /* adr_type */ |
a06ea964 NC |
2704 | 0, |
2705 | 0, | |
2706 | BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12, | |
74ad790c | 2707 | 0, |
a06ea964 NC |
2708 | 0}, |
2709 | ||
2710 | /* Get tp offset for a symbol. */ | |
2711 | {"tprel_lo12", 0, | |
6f4a313b | 2712 | 0, /* adr_type */ |
a06ea964 NC |
2713 | 0, |
2714 | 0, | |
2715 | BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12, | |
74ad790c | 2716 | 0, |
a06ea964 NC |
2717 | 0}, |
2718 | ||
2719 | /* Get tp offset for a symbol. */ | |
2720 | {"tprel_hi12", 0, | |
6f4a313b | 2721 | 0, /* adr_type */ |
a06ea964 NC |
2722 | 0, |
2723 | 0, | |
2724 | BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12, | |
74ad790c | 2725 | 0, |
a06ea964 NC |
2726 | 0}, |
2727 | ||
2728 | /* Get tp offset for a symbol. */ | |
2729 | {"tprel_lo12_nc", 0, | |
6f4a313b | 2730 | 0, /* adr_type */ |
a06ea964 NC |
2731 | 0, |
2732 | 0, | |
2733 | BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC, | |
74ad790c | 2734 | 0, |
a06ea964 NC |
2735 | 0}, |
2736 | ||
2737 | /* Most significant bits 32-47 of address/value: MOVZ. */ | |
2738 | {"tprel_g2", 0, | |
6f4a313b | 2739 | 0, /* adr_type */ |
a06ea964 NC |
2740 | 0, |
2741 | BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2, | |
2742 | 0, | |
74ad790c | 2743 | 0, |
a06ea964 NC |
2744 | 0}, |
2745 | ||
2746 | /* Most significant bits 16-31 of address/value: MOVZ. */ | |
2747 | {"tprel_g1", 0, | |
6f4a313b | 2748 | 0, /* adr_type */ |
a06ea964 NC |
2749 | 0, |
2750 | BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1, | |
2751 | 0, | |
74ad790c | 2752 | 0, |
a06ea964 NC |
2753 | 0}, |
2754 | ||
2755 | /* Most significant bits 16-31 of address/value: MOVZ, no check. */ | |
2756 | {"tprel_g1_nc", 0, | |
6f4a313b | 2757 | 0, /* adr_type */ |
a06ea964 NC |
2758 | 0, |
2759 | BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC, | |
2760 | 0, | |
74ad790c | 2761 | 0, |
a06ea964 NC |
2762 | 0}, |
2763 | ||
2764 | /* Most significant bits 0-15 of address/value: MOVZ. */ | |
2765 | {"tprel_g0", 0, | |
6f4a313b | 2766 | 0, /* adr_type */ |
a06ea964 NC |
2767 | 0, |
2768 | BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0, | |
2769 | 0, | |
74ad790c | 2770 | 0, |
a06ea964 NC |
2771 | 0}, |
2772 | ||
2773 | /* Most significant bits 0-15 of address/value: MOVZ, no check. */ | |
2774 | {"tprel_g0_nc", 0, | |
6f4a313b | 2775 | 0, /* adr_type */ |
a06ea964 NC |
2776 | 0, |
2777 | BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC, | |
2778 | 0, | |
74ad790c | 2779 | 0, |
a06ea964 | 2780 | 0}, |
a921b5bd JW |
2781 | |
2782 | /* 15bit offset from got entry to base address of GOT table. */ | |
2783 | {"gotpage_lo15", 0, | |
2784 | 0, | |
2785 | 0, | |
2786 | 0, | |
2787 | 0, | |
2788 | BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15, | |
2789 | 0}, | |
3d715ce4 JW |
2790 | |
2791 | /* 14bit offset from got entry to base address of GOT table. */ | |
2792 | {"gotpage_lo14", 0, | |
2793 | 0, | |
2794 | 0, | |
2795 | 0, | |
2796 | 0, | |
2797 | BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14, | |
2798 | 0}, | |
a06ea964 NC |
2799 | }; |
2800 | ||
2801 | /* Given the address of a pointer pointing to the textual name of a | |
2802 | relocation as may appear in assembler source, attempt to find its | |
2803 | details in reloc_table. The pointer will be updated to the character | |
2804 | after the trailing colon. On failure, NULL will be returned; | |
2805 | otherwise return the reloc_table_entry. */ | |
2806 | ||
2807 | static struct reloc_table_entry * | |
2808 | find_reloc_table_entry (char **str) | |
2809 | { | |
2810 | unsigned int i; | |
2811 | for (i = 0; i < ARRAY_SIZE (reloc_table); i++) | |
2812 | { | |
2813 | int length = strlen (reloc_table[i].name); | |
2814 | ||
2815 | if (strncasecmp (reloc_table[i].name, *str, length) == 0 | |
2816 | && (*str)[length] == ':') | |
2817 | { | |
2818 | *str += (length + 1); | |
2819 | return &reloc_table[i]; | |
2820 | } | |
2821 | } | |
2822 | ||
2823 | return NULL; | |
2824 | } | |
2825 | ||
2826 | /* Mode argument to parse_shift and parser_shifter_operand. */ | |
2827 | enum parse_shift_mode | |
2828 | { | |
2829 | SHIFTED_ARITH_IMM, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or | |
2830 | "#imm{,lsl #n}" */ | |
2831 | SHIFTED_LOGIC_IMM, /* "rn{,lsl|lsr|asl|asr|ror #n}" or | |
2832 | "#imm" */ | |
2833 | SHIFTED_LSL, /* bare "lsl #n" */ | |
2834 | SHIFTED_LSL_MSL, /* "lsl|msl #n" */ | |
2835 | SHIFTED_REG_OFFSET /* [su]xtw|sxtx {#n} or lsl #n */ | |
2836 | }; | |
2837 | ||
2838 | /* Parse a <shift> operator on an AArch64 data processing instruction. | |
2839 | Return TRUE on success; otherwise return FALSE. */ | |
2840 | static bfd_boolean | |
2841 | parse_shift (char **str, aarch64_opnd_info *operand, enum parse_shift_mode mode) | |
2842 | { | |
2843 | const struct aarch64_name_value_pair *shift_op; | |
2844 | enum aarch64_modifier_kind kind; | |
2845 | expressionS exp; | |
2846 | int exp_has_prefix; | |
2847 | char *s = *str; | |
2848 | char *p = s; | |
2849 | ||
2850 | for (p = *str; ISALPHA (*p); p++) | |
2851 | ; | |
2852 | ||
2853 | if (p == *str) | |
2854 | { | |
2855 | set_syntax_error (_("shift expression expected")); | |
2856 | return FALSE; | |
2857 | } | |
2858 | ||
2859 | shift_op = hash_find_n (aarch64_shift_hsh, *str, p - *str); | |
2860 | ||
2861 | if (shift_op == NULL) | |
2862 | { | |
2863 | set_syntax_error (_("shift operator expected")); | |
2864 | return FALSE; | |
2865 | } | |
2866 | ||
2867 | kind = aarch64_get_operand_modifier (shift_op); | |
2868 | ||
2869 | if (kind == AARCH64_MOD_MSL && mode != SHIFTED_LSL_MSL) | |
2870 | { | |
2871 | set_syntax_error (_("invalid use of 'MSL'")); | |
2872 | return FALSE; | |
2873 | } | |
2874 | ||
2875 | switch (mode) | |
2876 | { | |
2877 | case SHIFTED_LOGIC_IMM: | |
2878 | if (aarch64_extend_operator_p (kind) == TRUE) | |
2879 | { | |
2880 | set_syntax_error (_("extending shift is not permitted")); | |
2881 | return FALSE; | |
2882 | } | |
2883 | break; | |
2884 | ||
2885 | case SHIFTED_ARITH_IMM: | |
2886 | if (kind == AARCH64_MOD_ROR) | |
2887 | { | |
2888 | set_syntax_error (_("'ROR' shift is not permitted")); | |
2889 | return FALSE; | |
2890 | } | |
2891 | break; | |
2892 | ||
2893 | case SHIFTED_LSL: | |
2894 | if (kind != AARCH64_MOD_LSL) | |
2895 | { | |
2896 | set_syntax_error (_("only 'LSL' shift is permitted")); | |
2897 | return FALSE; | |
2898 | } | |
2899 | break; | |
2900 | ||
2901 | case SHIFTED_REG_OFFSET: | |
2902 | if (kind != AARCH64_MOD_UXTW && kind != AARCH64_MOD_LSL | |
2903 | && kind != AARCH64_MOD_SXTW && kind != AARCH64_MOD_SXTX) | |
2904 | { | |
2905 | set_fatal_syntax_error | |
2906 | (_("invalid shift for the register offset addressing mode")); | |
2907 | return FALSE; | |
2908 | } | |
2909 | break; | |
2910 | ||
2911 | case SHIFTED_LSL_MSL: | |
2912 | if (kind != AARCH64_MOD_LSL && kind != AARCH64_MOD_MSL) | |
2913 | { | |
2914 | set_syntax_error (_("invalid shift operator")); | |
2915 | return FALSE; | |
2916 | } | |
2917 | break; | |
2918 | ||
2919 | default: | |
2920 | abort (); | |
2921 | } | |
2922 | ||
2923 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
2924 | skip_whitespace (p); | |
2925 | ||
2926 | /* Parse shift amount. */ | |
2927 | exp_has_prefix = 0; | |
2928 | if (mode == SHIFTED_REG_OFFSET && *p == ']') | |
2929 | exp.X_op = O_absent; | |
2930 | else | |
2931 | { | |
2932 | if (is_immediate_prefix (*p)) | |
2933 | { | |
2934 | p++; | |
2935 | exp_has_prefix = 1; | |
2936 | } | |
2937 | my_get_expression (&exp, &p, GE_NO_PREFIX, 0); | |
2938 | } | |
2939 | if (exp.X_op == O_absent) | |
2940 | { | |
2941 | if (aarch64_extend_operator_p (kind) == FALSE || exp_has_prefix) | |
2942 | { | |
2943 | set_syntax_error (_("missing shift amount")); | |
2944 | return FALSE; | |
2945 | } | |
2946 | operand->shifter.amount = 0; | |
2947 | } | |
2948 | else if (exp.X_op != O_constant) | |
2949 | { | |
2950 | set_syntax_error (_("constant shift amount required")); | |
2951 | return FALSE; | |
2952 | } | |
2953 | else if (exp.X_add_number < 0 || exp.X_add_number > 63) | |
2954 | { | |
2955 | set_fatal_syntax_error (_("shift amount out of range 0 to 63")); | |
2956 | return FALSE; | |
2957 | } | |
2958 | else | |
2959 | { | |
2960 | operand->shifter.amount = exp.X_add_number; | |
2961 | operand->shifter.amount_present = 1; | |
2962 | } | |
2963 | ||
2964 | operand->shifter.operator_present = 1; | |
2965 | operand->shifter.kind = kind; | |
2966 | ||
2967 | *str = p; | |
2968 | return TRUE; | |
2969 | } | |
2970 | ||
2971 | /* Parse a <shifter_operand> for a data processing instruction: | |
2972 | ||
2973 | #<immediate> | |
2974 | #<immediate>, LSL #imm | |
2975 | ||
2976 | Validation of immediate operands is deferred to md_apply_fix. | |
2977 | ||
2978 | Return TRUE on success; otherwise return FALSE. */ | |
2979 | ||
2980 | static bfd_boolean | |
2981 | parse_shifter_operand_imm (char **str, aarch64_opnd_info *operand, | |
2982 | enum parse_shift_mode mode) | |
2983 | { | |
2984 | char *p; | |
2985 | ||
2986 | if (mode != SHIFTED_ARITH_IMM && mode != SHIFTED_LOGIC_IMM) | |
2987 | return FALSE; | |
2988 | ||
2989 | p = *str; | |
2990 | ||
2991 | /* Accept an immediate expression. */ | |
2992 | if (! my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX, 1)) | |
2993 | return FALSE; | |
2994 | ||
2995 | /* Accept optional LSL for arithmetic immediate values. */ | |
2996 | if (mode == SHIFTED_ARITH_IMM && skip_past_comma (&p)) | |
2997 | if (! parse_shift (&p, operand, SHIFTED_LSL)) | |
2998 | return FALSE; | |
2999 | ||
3000 | /* Not accept any shifter for logical immediate values. */ | |
3001 | if (mode == SHIFTED_LOGIC_IMM && skip_past_comma (&p) | |
3002 | && parse_shift (&p, operand, mode)) | |
3003 | { | |
3004 | set_syntax_error (_("unexpected shift operator")); | |
3005 | return FALSE; | |
3006 | } | |
3007 | ||
3008 | *str = p; | |
3009 | return TRUE; | |
3010 | } | |
3011 | ||
3012 | /* Parse a <shifter_operand> for a data processing instruction: | |
3013 | ||
3014 | <Rm> | |
3015 | <Rm>, <shift> | |
3016 | #<immediate> | |
3017 | #<immediate>, LSL #imm | |
3018 | ||
3019 | where <shift> is handled by parse_shift above, and the last two | |
3020 | cases are handled by the function above. | |
3021 | ||
3022 | Validation of immediate operands is deferred to md_apply_fix. | |
3023 | ||
3024 | Return TRUE on success; otherwise return FALSE. */ | |
3025 | ||
3026 | static bfd_boolean | |
3027 | parse_shifter_operand (char **str, aarch64_opnd_info *operand, | |
3028 | enum parse_shift_mode mode) | |
3029 | { | |
3030 | int reg; | |
3031 | int isreg32, isregzero; | |
3032 | enum aarch64_operand_class opd_class | |
3033 | = aarch64_get_operand_class (operand->type); | |
3034 | ||
3035 | if ((reg = | |
3036 | aarch64_reg_parse_32_64 (str, 0, 0, &isreg32, &isregzero)) != PARSE_FAIL) | |
3037 | { | |
3038 | if (opd_class == AARCH64_OPND_CLASS_IMMEDIATE) | |
3039 | { | |
3040 | set_syntax_error (_("unexpected register in the immediate operand")); | |
3041 | return FALSE; | |
3042 | } | |
3043 | ||
3044 | if (!isregzero && reg == REG_SP) | |
3045 | { | |
3046 | set_syntax_error (BAD_SP); | |
3047 | return FALSE; | |
3048 | } | |
3049 | ||
3050 | operand->reg.regno = reg; | |
3051 | operand->qualifier = isreg32 ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X; | |
3052 | ||
3053 | /* Accept optional shift operation on register. */ | |
3054 | if (! skip_past_comma (str)) | |
3055 | return TRUE; | |
3056 | ||
3057 | if (! parse_shift (str, operand, mode)) | |
3058 | return FALSE; | |
3059 | ||
3060 | return TRUE; | |
3061 | } | |
3062 | else if (opd_class == AARCH64_OPND_CLASS_MODIFIED_REG) | |
3063 | { | |
3064 | set_syntax_error | |
3065 | (_("integer register expected in the extended/shifted operand " | |
3066 | "register")); | |
3067 | return FALSE; | |
3068 | } | |
3069 | ||
3070 | /* We have a shifted immediate variable. */ | |
3071 | return parse_shifter_operand_imm (str, operand, mode); | |
3072 | } | |
3073 | ||
3074 | /* Return TRUE on success; return FALSE otherwise. */ | |
3075 | ||
3076 | static bfd_boolean | |
3077 | parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand, | |
3078 | enum parse_shift_mode mode) | |
3079 | { | |
3080 | char *p = *str; | |
3081 | ||
3082 | /* Determine if we have the sequence of characters #: or just : | |
3083 | coming next. If we do, then we check for a :rello: relocation | |
3084 | modifier. If we don't, punt the whole lot to | |
3085 | parse_shifter_operand. */ | |
3086 | ||
3087 | if ((p[0] == '#' && p[1] == ':') || p[0] == ':') | |
3088 | { | |
3089 | struct reloc_table_entry *entry; | |
3090 | ||
3091 | if (p[0] == '#') | |
3092 | p += 2; | |
3093 | else | |
3094 | p++; | |
3095 | *str = p; | |
3096 | ||
3097 | /* Try to parse a relocation. Anything else is an error. */ | |
3098 | if (!(entry = find_reloc_table_entry (str))) | |
3099 | { | |
3100 | set_syntax_error (_("unknown relocation modifier")); | |
3101 | return FALSE; | |
3102 | } | |
3103 | ||
3104 | if (entry->add_type == 0) | |
3105 | { | |
3106 | set_syntax_error | |
3107 | (_("this relocation modifier is not allowed on this instruction")); | |
3108 | return FALSE; | |
3109 | } | |
3110 | ||
3111 | /* Save str before we decompose it. */ | |
3112 | p = *str; | |
3113 | ||
3114 | /* Next, we parse the expression. */ | |
3115 | if (! my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX, 1)) | |
3116 | return FALSE; | |
3117 | ||
3118 | /* Record the relocation type (use the ADD variant here). */ | |
3119 | inst.reloc.type = entry->add_type; | |
3120 | inst.reloc.pc_rel = entry->pc_rel; | |
3121 | ||
3122 | /* If str is empty, we've reached the end, stop here. */ | |
3123 | if (**str == '\0') | |
3124 | return TRUE; | |
3125 | ||
55d9b4c1 | 3126 | /* Otherwise, we have a shifted reloc modifier, so rewind to |
a06ea964 NC |
3127 | recover the variable name and continue parsing for the shifter. */ |
3128 | *str = p; | |
3129 | return parse_shifter_operand_imm (str, operand, mode); | |
3130 | } | |
3131 | ||
3132 | return parse_shifter_operand (str, operand, mode); | |
3133 | } | |
3134 | ||
3135 | /* Parse all forms of an address expression. Information is written | |
3136 | to *OPERAND and/or inst.reloc. | |
3137 | ||
3138 | The A64 instruction set has the following addressing modes: | |
3139 | ||
3140 | Offset | |
3141 | [base] // in SIMD ld/st structure | |
3142 | [base{,#0}] // in ld/st exclusive | |
3143 | [base{,#imm}] | |
3144 | [base,Xm{,LSL #imm}] | |
3145 | [base,Xm,SXTX {#imm}] | |
3146 | [base,Wm,(S|U)XTW {#imm}] | |
3147 | Pre-indexed | |
3148 | [base,#imm]! | |
3149 | Post-indexed | |
3150 | [base],#imm | |
3151 | [base],Xm // in SIMD ld/st structure | |
3152 | PC-relative (literal) | |
3153 | label | |
3154 | =immediate | |
3155 | ||
3156 | (As a convenience, the notation "=immediate" is permitted in conjunction | |
3157 | with the pc-relative literal load instructions to automatically place an | |
3158 | immediate value or symbolic address in a nearby literal pool and generate | |
3159 | a hidden label which references it.) | |
3160 | ||
3161 | Upon a successful parsing, the address structure in *OPERAND will be | |
3162 | filled in the following way: | |
3163 | ||
3164 | .base_regno = <base> | |
3165 | .offset.is_reg // 1 if the offset is a register | |
3166 | .offset.imm = <imm> | |
3167 | .offset.regno = <Rm> | |
3168 | ||
3169 | For different addressing modes defined in the A64 ISA: | |
3170 | ||
3171 | Offset | |
3172 | .pcrel=0; .preind=1; .postind=0; .writeback=0 | |
3173 | Pre-indexed | |
3174 | .pcrel=0; .preind=1; .postind=0; .writeback=1 | |
3175 | Post-indexed | |
3176 | .pcrel=0; .preind=0; .postind=1; .writeback=1 | |
3177 | PC-relative (literal) | |
3178 | .pcrel=1; .preind=1; .postind=0; .writeback=0 | |
3179 | ||
3180 | The shift/extension information, if any, will be stored in .shifter. | |
3181 | ||
3182 | It is the caller's responsibility to check for addressing modes not | |
3183 | supported by the instruction, and to set inst.reloc.type. */ | |
3184 | ||
3185 | static bfd_boolean | |
3186 | parse_address_main (char **str, aarch64_opnd_info *operand, int reloc, | |
3187 | int accept_reg_post_index) | |
3188 | { | |
3189 | char *p = *str; | |
3190 | int reg; | |
3191 | int isreg32, isregzero; | |
3192 | expressionS *exp = &inst.reloc.exp; | |
3193 | ||
3194 | if (! skip_past_char (&p, '[')) | |
3195 | { | |
3196 | /* =immediate or label. */ | |
3197 | operand->addr.pcrel = 1; | |
3198 | operand->addr.preind = 1; | |
3199 | ||
f41aef5f RE |
3200 | /* #:<reloc_op>:<symbol> */ |
3201 | skip_past_char (&p, '#'); | |
3202 | if (reloc && skip_past_char (&p, ':')) | |
3203 | { | |
6f4a313b | 3204 | bfd_reloc_code_real_type ty; |
f41aef5f RE |
3205 | struct reloc_table_entry *entry; |
3206 | ||
3207 | /* Try to parse a relocation modifier. Anything else is | |
3208 | an error. */ | |
3209 | entry = find_reloc_table_entry (&p); | |
3210 | if (! entry) | |
3211 | { | |
3212 | set_syntax_error (_("unknown relocation modifier")); | |
3213 | return FALSE; | |
3214 | } | |
3215 | ||
6f4a313b MS |
3216 | switch (operand->type) |
3217 | { | |
3218 | case AARCH64_OPND_ADDR_PCREL21: | |
3219 | /* adr */ | |
3220 | ty = entry->adr_type; | |
3221 | break; | |
3222 | ||
3223 | default: | |
74ad790c | 3224 | ty = entry->ld_literal_type; |
6f4a313b MS |
3225 | break; |
3226 | } | |
3227 | ||
3228 | if (ty == 0) | |
f41aef5f RE |
3229 | { |
3230 | set_syntax_error | |
3231 | (_("this relocation modifier is not allowed on this " | |
3232 | "instruction")); | |
3233 | return FALSE; | |
3234 | } | |
3235 | ||
3236 | /* #:<reloc_op>: */ | |
3237 | if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1)) | |
3238 | { | |
3239 | set_syntax_error (_("invalid relocation expression")); | |
3240 | return FALSE; | |
3241 | } | |
a06ea964 | 3242 | |
f41aef5f | 3243 | /* #:<reloc_op>:<expr> */ |
6f4a313b MS |
3244 | /* Record the relocation type. */ |
3245 | inst.reloc.type = ty; | |
f41aef5f RE |
3246 | inst.reloc.pc_rel = entry->pc_rel; |
3247 | } | |
3248 | else | |
a06ea964 | 3249 | { |
f41aef5f RE |
3250 | |
3251 | if (skip_past_char (&p, '=')) | |
3252 | /* =immediate; need to generate the literal in the literal pool. */ | |
3253 | inst.gen_lit_pool = 1; | |
3254 | ||
3255 | if (!my_get_expression (exp, &p, GE_NO_PREFIX, 1)) | |
3256 | { | |
3257 | set_syntax_error (_("invalid address")); | |
3258 | return FALSE; | |
3259 | } | |
a06ea964 NC |
3260 | } |
3261 | ||
3262 | *str = p; | |
3263 | return TRUE; | |
3264 | } | |
3265 | ||
3266 | /* [ */ | |
3267 | ||
3268 | /* Accept SP and reject ZR */ | |
3269 | reg = aarch64_reg_parse_32_64 (&p, 0, 1, &isreg32, &isregzero); | |
3270 | if (reg == PARSE_FAIL || isreg32) | |
3271 | { | |
3272 | set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64))); | |
3273 | return FALSE; | |
3274 | } | |
3275 | operand->addr.base_regno = reg; | |
3276 | ||
3277 | /* [Xn */ | |
3278 | if (skip_past_comma (&p)) | |
3279 | { | |
3280 | /* [Xn, */ | |
3281 | operand->addr.preind = 1; | |
3282 | ||
3283 | /* Reject SP and accept ZR */ | |
3284 | reg = aarch64_reg_parse_32_64 (&p, 1, 0, &isreg32, &isregzero); | |
3285 | if (reg != PARSE_FAIL) | |
3286 | { | |
3287 | /* [Xn,Rm */ | |
3288 | operand->addr.offset.regno = reg; | |
3289 | operand->addr.offset.is_reg = 1; | |
3290 | /* Shifted index. */ | |
3291 | if (skip_past_comma (&p)) | |
3292 | { | |
3293 | /* [Xn,Rm, */ | |
3294 | if (! parse_shift (&p, operand, SHIFTED_REG_OFFSET)) | |
3295 | /* Use the diagnostics set in parse_shift, so not set new | |
3296 | error message here. */ | |
3297 | return FALSE; | |
3298 | } | |
3299 | /* We only accept: | |
3300 | [base,Xm{,LSL #imm}] | |
3301 | [base,Xm,SXTX {#imm}] | |
3302 | [base,Wm,(S|U)XTW {#imm}] */ | |
3303 | if (operand->shifter.kind == AARCH64_MOD_NONE | |
3304 | || operand->shifter.kind == AARCH64_MOD_LSL | |
3305 | || operand->shifter.kind == AARCH64_MOD_SXTX) | |
3306 | { | |
3307 | if (isreg32) | |
3308 | { | |
3309 | set_syntax_error (_("invalid use of 32-bit register offset")); | |
3310 | return FALSE; | |
3311 | } | |
3312 | } | |
3313 | else if (!isreg32) | |
3314 | { | |
3315 | set_syntax_error (_("invalid use of 64-bit register offset")); | |
3316 | return FALSE; | |
3317 | } | |
3318 | } | |
3319 | else | |
3320 | { | |
3321 | /* [Xn,#:<reloc_op>:<symbol> */ | |
3322 | skip_past_char (&p, '#'); | |
3323 | if (reloc && skip_past_char (&p, ':')) | |
3324 | { | |
3325 | struct reloc_table_entry *entry; | |
3326 | ||
3327 | /* Try to parse a relocation modifier. Anything else is | |
3328 | an error. */ | |
3329 | if (!(entry = find_reloc_table_entry (&p))) | |
3330 | { | |
3331 | set_syntax_error (_("unknown relocation modifier")); | |
3332 | return FALSE; | |
3333 | } | |
3334 | ||
3335 | if (entry->ldst_type == 0) | |
3336 | { | |
3337 | set_syntax_error | |
3338 | (_("this relocation modifier is not allowed on this " | |
3339 | "instruction")); | |
3340 | return FALSE; | |
3341 | } | |
3342 | ||
3343 | /* [Xn,#:<reloc_op>: */ | |
3344 | /* We now have the group relocation table entry corresponding to | |
3345 | the name in the assembler source. Next, we parse the | |
3346 | expression. */ | |
3347 | if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1)) | |
3348 | { | |
3349 | set_syntax_error (_("invalid relocation expression")); | |
3350 | return FALSE; | |
3351 | } | |
3352 | ||
3353 | /* [Xn,#:<reloc_op>:<expr> */ | |
3354 | /* Record the load/store relocation type. */ | |
3355 | inst.reloc.type = entry->ldst_type; | |
3356 | inst.reloc.pc_rel = entry->pc_rel; | |
3357 | } | |
3358 | else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1)) | |
3359 | { | |
3360 | set_syntax_error (_("invalid expression in the address")); | |
3361 | return FALSE; | |
3362 | } | |
3363 | /* [Xn,<expr> */ | |
3364 | } | |
3365 | } | |
3366 | ||
3367 | if (! skip_past_char (&p, ']')) | |
3368 | { | |
3369 | set_syntax_error (_("']' expected")); | |
3370 | return FALSE; | |
3371 | } | |
3372 | ||
3373 | if (skip_past_char (&p, '!')) | |
3374 | { | |
3375 | if (operand->addr.preind && operand->addr.offset.is_reg) | |
3376 | { | |
3377 | set_syntax_error (_("register offset not allowed in pre-indexed " | |
3378 | "addressing mode")); | |
3379 | return FALSE; | |
3380 | } | |
3381 | /* [Xn]! */ | |
3382 | operand->addr.writeback = 1; | |
3383 | } | |
3384 | else if (skip_past_comma (&p)) | |
3385 | { | |
3386 | /* [Xn], */ | |
3387 | operand->addr.postind = 1; | |
3388 | operand->addr.writeback = 1; | |
3389 | ||
3390 | if (operand->addr.preind) | |
3391 | { | |
3392 | set_syntax_error (_("cannot combine pre- and post-indexing")); | |
3393 | return FALSE; | |
3394 | } | |
3395 | ||
3396 | if (accept_reg_post_index | |
3397 | && (reg = aarch64_reg_parse_32_64 (&p, 1, 1, &isreg32, | |
3398 | &isregzero)) != PARSE_FAIL) | |
3399 | { | |
3400 | /* [Xn],Xm */ | |
3401 | if (isreg32) | |
3402 | { | |
3403 | set_syntax_error (_("invalid 32-bit register offset")); | |
3404 | return FALSE; | |
3405 | } | |
3406 | operand->addr.offset.regno = reg; | |
3407 | operand->addr.offset.is_reg = 1; | |
3408 | } | |
3409 | else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1)) | |
3410 | { | |
3411 | /* [Xn],#expr */ | |
3412 | set_syntax_error (_("invalid expression in the address")); | |
3413 | return FALSE; | |
3414 | } | |
3415 | } | |
3416 | ||
3417 | /* If at this point neither .preind nor .postind is set, we have a | |
3418 | bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */ | |
3419 | if (operand->addr.preind == 0 && operand->addr.postind == 0) | |
3420 | { | |
3421 | if (operand->addr.writeback) | |
3422 | { | |
3423 | /* Reject [Rn]! */ | |
3424 | set_syntax_error (_("missing offset in the pre-indexed address")); | |
3425 | return FALSE; | |
3426 | } | |
3427 | operand->addr.preind = 1; | |
3428 | inst.reloc.exp.X_op = O_constant; | |
3429 | inst.reloc.exp.X_add_number = 0; | |
3430 | } | |
3431 | ||
3432 | *str = p; | |
3433 | return TRUE; | |
3434 | } | |
3435 | ||
3436 | /* Return TRUE on success; otherwise return FALSE. */ | |
3437 | static bfd_boolean | |
3438 | parse_address (char **str, aarch64_opnd_info *operand, | |
3439 | int accept_reg_post_index) | |
3440 | { | |
3441 | return parse_address_main (str, operand, 0, accept_reg_post_index); | |
3442 | } | |
3443 | ||
3444 | /* Return TRUE on success; otherwise return FALSE. */ | |
3445 | static bfd_boolean | |
3446 | parse_address_reloc (char **str, aarch64_opnd_info *operand) | |
3447 | { | |
3448 | return parse_address_main (str, operand, 1, 0); | |
3449 | } | |
3450 | ||
3451 | /* Parse an operand for a MOVZ, MOVN or MOVK instruction. | |
3452 | Return TRUE on success; otherwise return FALSE. */ | |
3453 | static bfd_boolean | |
3454 | parse_half (char **str, int *internal_fixup_p) | |
3455 | { | |
671eeb28 | 3456 | char *p = *str; |
a06ea964 | 3457 | |
a06ea964 NC |
3458 | skip_past_char (&p, '#'); |
3459 | ||
3460 | gas_assert (internal_fixup_p); | |
3461 | *internal_fixup_p = 0; | |
3462 | ||
3463 | if (*p == ':') | |
3464 | { | |
3465 | struct reloc_table_entry *entry; | |
3466 | ||
3467 | /* Try to parse a relocation. Anything else is an error. */ | |
3468 | ++p; | |
3469 | if (!(entry = find_reloc_table_entry (&p))) | |
3470 | { | |
3471 | set_syntax_error (_("unknown relocation modifier")); | |
3472 | return FALSE; | |
3473 | } | |
3474 | ||
3475 | if (entry->movw_type == 0) | |
3476 | { | |
3477 | set_syntax_error | |
3478 | (_("this relocation modifier is not allowed on this instruction")); | |
3479 | return FALSE; | |
3480 | } | |
3481 | ||
3482 | inst.reloc.type = entry->movw_type; | |
3483 | } | |
3484 | else | |
3485 | *internal_fixup_p = 1; | |
3486 | ||
a06ea964 NC |
3487 | if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1)) |
3488 | return FALSE; | |
3489 | ||
3490 | *str = p; | |
3491 | return TRUE; | |
3492 | } | |
3493 | ||
3494 | /* Parse an operand for an ADRP instruction: | |
3495 | ADRP <Xd>, <label> | |
3496 | Return TRUE on success; otherwise return FALSE. */ | |
3497 | ||
3498 | static bfd_boolean | |
3499 | parse_adrp (char **str) | |
3500 | { | |
3501 | char *p; | |
3502 | ||
3503 | p = *str; | |
3504 | if (*p == ':') | |
3505 | { | |
3506 | struct reloc_table_entry *entry; | |
3507 | ||
3508 | /* Try to parse a relocation. Anything else is an error. */ | |
3509 | ++p; | |
3510 | if (!(entry = find_reloc_table_entry (&p))) | |
3511 | { | |
3512 | set_syntax_error (_("unknown relocation modifier")); | |
3513 | return FALSE; | |
3514 | } | |
3515 | ||
3516 | if (entry->adrp_type == 0) | |
3517 | { | |
3518 | set_syntax_error | |
3519 | (_("this relocation modifier is not allowed on this instruction")); | |
3520 | return FALSE; | |
3521 | } | |
3522 | ||
3523 | inst.reloc.type = entry->adrp_type; | |
3524 | } | |
3525 | else | |
3526 | inst.reloc.type = BFD_RELOC_AARCH64_ADR_HI21_PCREL; | |
3527 | ||
3528 | inst.reloc.pc_rel = 1; | |
3529 | ||
3530 | if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1)) | |
3531 | return FALSE; | |
3532 | ||
3533 | *str = p; | |
3534 | return TRUE; | |
3535 | } | |
3536 | ||
3537 | /* Miscellaneous. */ | |
3538 | ||
3539 | /* Parse an option for a preload instruction. Returns the encoding for the | |
3540 | option, or PARSE_FAIL. */ | |
3541 | ||
3542 | static int | |
3543 | parse_pldop (char **str) | |
3544 | { | |
3545 | char *p, *q; | |
3546 | const struct aarch64_name_value_pair *o; | |
3547 | ||
3548 | p = q = *str; | |
3549 | while (ISALNUM (*q)) | |
3550 | q++; | |
3551 | ||
3552 | o = hash_find_n (aarch64_pldop_hsh, p, q - p); | |
3553 | if (!o) | |
3554 | return PARSE_FAIL; | |
3555 | ||
3556 | *str = q; | |
3557 | return o->value; | |
3558 | } | |
3559 | ||
3560 | /* Parse an option for a barrier instruction. Returns the encoding for the | |
3561 | option, or PARSE_FAIL. */ | |
3562 | ||
3563 | static int | |
3564 | parse_barrier (char **str) | |
3565 | { | |
3566 | char *p, *q; | |
3567 | const asm_barrier_opt *o; | |
3568 | ||
3569 | p = q = *str; | |
3570 | while (ISALPHA (*q)) | |
3571 | q++; | |
3572 | ||
3573 | o = hash_find_n (aarch64_barrier_opt_hsh, p, q - p); | |
3574 | if (!o) | |
3575 | return PARSE_FAIL; | |
3576 | ||
3577 | *str = q; | |
3578 | return o->value; | |
3579 | } | |
3580 | ||
1e6f4800 MW |
3581 | /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record |
3582 | return 0 if successful. Otherwise return PARSE_FAIL. */ | |
3583 | ||
3584 | static int | |
3585 | parse_barrier_psb (char **str, | |
3586 | const struct aarch64_name_value_pair ** hint_opt) | |
3587 | { | |
3588 | char *p, *q; | |
3589 | const struct aarch64_name_value_pair *o; | |
3590 | ||
3591 | p = q = *str; | |
3592 | while (ISALPHA (*q)) | |
3593 | q++; | |
3594 | ||
3595 | o = hash_find_n (aarch64_hint_opt_hsh, p, q - p); | |
3596 | if (!o) | |
3597 | { | |
3598 | set_fatal_syntax_error | |
3599 | ( _("unknown or missing option to PSB")); | |
3600 | return PARSE_FAIL; | |
3601 | } | |
3602 | ||
3603 | if (o->value != 0x11) | |
3604 | { | |
3605 | /* PSB only accepts option name 'CSYNC'. */ | |
3606 | set_syntax_error | |
3607 | (_("the specified option is not accepted for PSB")); | |
3608 | return PARSE_FAIL; | |
3609 | } | |
3610 | ||
3611 | *str = q; | |
3612 | *hint_opt = o; | |
3613 | return 0; | |
3614 | } | |
3615 | ||
a06ea964 | 3616 | /* Parse a system register or a PSTATE field name for an MSR/MRS instruction. |
a203d9b7 | 3617 | Returns the encoding for the option, or PARSE_FAIL. |
a06ea964 NC |
3618 | |
3619 | If IMPLE_DEFINED_P is non-zero, the function will also try to parse the | |
72ca8fad MW |
3620 | implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>. |
3621 | ||
3622 | If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE | |
3623 | field, otherwise as a system register. | |
3624 | */ | |
a06ea964 NC |
3625 | |
3626 | static int | |
72ca8fad MW |
3627 | parse_sys_reg (char **str, struct hash_control *sys_regs, |
3628 | int imple_defined_p, int pstatefield_p) | |
a06ea964 NC |
3629 | { |
3630 | char *p, *q; | |
3631 | char buf[32]; | |
49eec193 | 3632 | const aarch64_sys_reg *o; |
a06ea964 NC |
3633 | int value; |
3634 | ||
3635 | p = buf; | |
3636 | for (q = *str; ISALNUM (*q) || *q == '_'; q++) | |
3637 | if (p < buf + 31) | |
3638 | *p++ = TOLOWER (*q); | |
3639 | *p = '\0'; | |
3640 | /* Assert that BUF be large enough. */ | |
3641 | gas_assert (p - buf == q - *str); | |
3642 | ||
3643 | o = hash_find (sys_regs, buf); | |
3644 | if (!o) | |
3645 | { | |
3646 | if (!imple_defined_p) | |
3647 | return PARSE_FAIL; | |
3648 | else | |
3649 | { | |
df7b4545 | 3650 | /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */ |
a06ea964 | 3651 | unsigned int op0, op1, cn, cm, op2; |
df7b4545 JW |
3652 | |
3653 | if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2) | |
3654 | != 5) | |
a06ea964 | 3655 | return PARSE_FAIL; |
df7b4545 | 3656 | if (op0 > 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7) |
a06ea964 NC |
3657 | return PARSE_FAIL; |
3658 | value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2; | |
3659 | } | |
3660 | } | |
3661 | else | |
49eec193 | 3662 | { |
72ca8fad MW |
3663 | if (pstatefield_p && !aarch64_pstatefield_supported_p (cpu_variant, o)) |
3664 | as_bad (_("selected processor does not support PSTATE field " | |
3665 | "name '%s'"), buf); | |
3666 | if (!pstatefield_p && !aarch64_sys_reg_supported_p (cpu_variant, o)) | |
3667 | as_bad (_("selected processor does not support system register " | |
3668 | "name '%s'"), buf); | |
9a73e520 | 3669 | if (aarch64_sys_reg_deprecated_p (o)) |
49eec193 | 3670 | as_warn (_("system register name '%s' is deprecated and may be " |
72ca8fad | 3671 | "removed in a future release"), buf); |
49eec193 YZ |
3672 | value = o->value; |
3673 | } | |
a06ea964 NC |
3674 | |
3675 | *str = q; | |
3676 | return value; | |
3677 | } | |
3678 | ||
3679 | /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry | |
3680 | for the option, or NULL. */ | |
3681 | ||
3682 | static const aarch64_sys_ins_reg * | |
3683 | parse_sys_ins_reg (char **str, struct hash_control *sys_ins_regs) | |
3684 | { | |
3685 | char *p, *q; | |
3686 | char buf[32]; | |
3687 | const aarch64_sys_ins_reg *o; | |
3688 | ||
3689 | p = buf; | |
3690 | for (q = *str; ISALNUM (*q) || *q == '_'; q++) | |
3691 | if (p < buf + 31) | |
3692 | *p++ = TOLOWER (*q); | |
3693 | *p = '\0'; | |
3694 | ||
3695 | o = hash_find (sys_ins_regs, buf); | |
3696 | if (!o) | |
3697 | return NULL; | |
3698 | ||
d6bf7ce6 MW |
3699 | if (!aarch64_sys_ins_reg_supported_p (cpu_variant, o)) |
3700 | as_bad (_("selected processor does not support system register " | |
3701 | "name '%s'"), buf); | |
3702 | ||
a06ea964 NC |
3703 | *str = q; |
3704 | return o; | |
3705 | } | |
3706 | \f | |
3707 | #define po_char_or_fail(chr) do { \ | |
3708 | if (! skip_past_char (&str, chr)) \ | |
3709 | goto failure; \ | |
3710 | } while (0) | |
3711 | ||
3712 | #define po_reg_or_fail(regtype) do { \ | |
3713 | val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \ | |
3714 | if (val == PARSE_FAIL) \ | |
3715 | { \ | |
3716 | set_default_error (); \ | |
3717 | goto failure; \ | |
3718 | } \ | |
3719 | } while (0) | |
3720 | ||
3721 | #define po_int_reg_or_fail(reject_sp, reject_rz) do { \ | |
3722 | val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \ | |
3723 | &isreg32, &isregzero); \ | |
3724 | if (val == PARSE_FAIL) \ | |
3725 | { \ | |
3726 | set_default_error (); \ | |
3727 | goto failure; \ | |
3728 | } \ | |
3729 | info->reg.regno = val; \ | |
3730 | if (isreg32) \ | |
3731 | info->qualifier = AARCH64_OPND_QLF_W; \ | |
3732 | else \ | |
3733 | info->qualifier = AARCH64_OPND_QLF_X; \ | |
3734 | } while (0) | |
3735 | ||
3736 | #define po_imm_nc_or_fail() do { \ | |
3737 | if (! parse_constant_immediate (&str, &val)) \ | |
3738 | goto failure; \ | |
3739 | } while (0) | |
3740 | ||
3741 | #define po_imm_or_fail(min, max) do { \ | |
3742 | if (! parse_constant_immediate (&str, &val)) \ | |
3743 | goto failure; \ | |
3744 | if (val < min || val > max) \ | |
3745 | { \ | |
3746 | set_fatal_syntax_error (_("immediate value out of range "\ | |
3747 | #min " to "#max)); \ | |
3748 | goto failure; \ | |
3749 | } \ | |
3750 | } while (0) | |
3751 | ||
3752 | #define po_misc_or_fail(expr) do { \ | |
3753 | if (!expr) \ | |
3754 | goto failure; \ | |
3755 | } while (0) | |
3756 | \f | |
3757 | /* encode the 12-bit imm field of Add/sub immediate */ | |
3758 | static inline uint32_t | |
3759 | encode_addsub_imm (uint32_t imm) | |
3760 | { | |
3761 | return imm << 10; | |
3762 | } | |
3763 | ||
3764 | /* encode the shift amount field of Add/sub immediate */ | |
3765 | static inline uint32_t | |
3766 | encode_addsub_imm_shift_amount (uint32_t cnt) | |
3767 | { | |
3768 | return cnt << 22; | |
3769 | } | |
3770 | ||
3771 | ||
3772 | /* encode the imm field of Adr instruction */ | |
3773 | static inline uint32_t | |
3774 | encode_adr_imm (uint32_t imm) | |
3775 | { | |
3776 | return (((imm & 0x3) << 29) /* [1:0] -> [30:29] */ | |
3777 | | ((imm & (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */ | |
3778 | } | |
3779 | ||
3780 | /* encode the immediate field of Move wide immediate */ | |
3781 | static inline uint32_t | |
3782 | encode_movw_imm (uint32_t imm) | |
3783 | { | |
3784 | return imm << 5; | |
3785 | } | |
3786 | ||
3787 | /* encode the 26-bit offset of unconditional branch */ | |
3788 | static inline uint32_t | |
3789 | encode_branch_ofs_26 (uint32_t ofs) | |
3790 | { | |
3791 | return ofs & ((1 << 26) - 1); | |
3792 | } | |
3793 | ||
3794 | /* encode the 19-bit offset of conditional branch and compare & branch */ | |
3795 | static inline uint32_t | |
3796 | encode_cond_branch_ofs_19 (uint32_t ofs) | |
3797 | { | |
3798 | return (ofs & ((1 << 19) - 1)) << 5; | |
3799 | } | |
3800 | ||
3801 | /* encode the 19-bit offset of ld literal */ | |
3802 | static inline uint32_t | |
3803 | encode_ld_lit_ofs_19 (uint32_t ofs) | |
3804 | { | |
3805 | return (ofs & ((1 << 19) - 1)) << 5; | |
3806 | } | |
3807 | ||
3808 | /* Encode the 14-bit offset of test & branch. */ | |
3809 | static inline uint32_t | |
3810 | encode_tst_branch_ofs_14 (uint32_t ofs) | |
3811 | { | |
3812 | return (ofs & ((1 << 14) - 1)) << 5; | |
3813 | } | |
3814 | ||
3815 | /* Encode the 16-bit imm field of svc/hvc/smc. */ | |
3816 | static inline uint32_t | |
3817 | encode_svc_imm (uint32_t imm) | |
3818 | { | |
3819 | return imm << 5; | |
3820 | } | |
3821 | ||
3822 | /* Reencode add(s) to sub(s), or sub(s) to add(s). */ | |
3823 | static inline uint32_t | |
3824 | reencode_addsub_switch_add_sub (uint32_t opcode) | |
3825 | { | |
3826 | return opcode ^ (1 << 30); | |
3827 | } | |
3828 | ||
3829 | static inline uint32_t | |
3830 | reencode_movzn_to_movz (uint32_t opcode) | |
3831 | { | |
3832 | return opcode | (1 << 30); | |
3833 | } | |
3834 | ||
3835 | static inline uint32_t | |
3836 | reencode_movzn_to_movn (uint32_t opcode) | |
3837 | { | |
3838 | return opcode & ~(1 << 30); | |
3839 | } | |
3840 | ||
3841 | /* Overall per-instruction processing. */ | |
3842 | ||
3843 | /* We need to be able to fix up arbitrary expressions in some statements. | |
3844 | This is so that we can handle symbols that are an arbitrary distance from | |
3845 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
3846 | which returns part of an address in a form which will be valid for | |
3847 | a data instruction. We do this by pushing the expression into a symbol | |
3848 | in the expr_section, and creating a fix for that. */ | |
3849 | ||
3850 | static fixS * | |
3851 | fix_new_aarch64 (fragS * frag, | |
3852 | int where, | |
3853 | short int size, expressionS * exp, int pc_rel, int reloc) | |
3854 | { | |
3855 | fixS *new_fix; | |
3856 | ||
3857 | switch (exp->X_op) | |
3858 | { | |
3859 | case O_constant: | |
3860 | case O_symbol: | |
3861 | case O_add: | |
3862 | case O_subtract: | |
3863 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc); | |
3864 | break; | |
3865 | ||
3866 | default: | |
3867 | new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0, | |
3868 | pc_rel, reloc); | |
3869 | break; | |
3870 | } | |
3871 | return new_fix; | |
3872 | } | |
3873 | \f | |
3874 | /* Diagnostics on operands errors. */ | |
3875 | ||
a52e6fd3 YZ |
3876 | /* By default, output verbose error message. |
3877 | Disable the verbose error message by -mno-verbose-error. */ | |
3878 | static int verbose_error_p = 1; | |
a06ea964 NC |
3879 | |
3880 | #ifdef DEBUG_AARCH64 | |
3881 | /* N.B. this is only for the purpose of debugging. */ | |
3882 | const char* operand_mismatch_kind_names[] = | |
3883 | { | |
3884 | "AARCH64_OPDE_NIL", | |
3885 | "AARCH64_OPDE_RECOVERABLE", | |
3886 | "AARCH64_OPDE_SYNTAX_ERROR", | |
3887 | "AARCH64_OPDE_FATAL_SYNTAX_ERROR", | |
3888 | "AARCH64_OPDE_INVALID_VARIANT", | |
3889 | "AARCH64_OPDE_OUT_OF_RANGE", | |
3890 | "AARCH64_OPDE_UNALIGNED", | |
3891 | "AARCH64_OPDE_REG_LIST", | |
3892 | "AARCH64_OPDE_OTHER_ERROR", | |
3893 | }; | |
3894 | #endif /* DEBUG_AARCH64 */ | |
3895 | ||
3896 | /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE. | |
3897 | ||
3898 | When multiple errors of different kinds are found in the same assembly | |
3899 | line, only the error of the highest severity will be picked up for | |
3900 | issuing the diagnostics. */ | |
3901 | ||
3902 | static inline bfd_boolean | |
3903 | operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs, | |
3904 | enum aarch64_operand_error_kind rhs) | |
3905 | { | |
3906 | gas_assert (AARCH64_OPDE_RECOVERABLE > AARCH64_OPDE_NIL); | |
3907 | gas_assert (AARCH64_OPDE_SYNTAX_ERROR > AARCH64_OPDE_RECOVERABLE); | |
3908 | gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR > AARCH64_OPDE_SYNTAX_ERROR); | |
3909 | gas_assert (AARCH64_OPDE_INVALID_VARIANT > AARCH64_OPDE_FATAL_SYNTAX_ERROR); | |
3910 | gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_INVALID_VARIANT); | |
3911 | gas_assert (AARCH64_OPDE_UNALIGNED > AARCH64_OPDE_OUT_OF_RANGE); | |
3912 | gas_assert (AARCH64_OPDE_REG_LIST > AARCH64_OPDE_UNALIGNED); | |
3913 | gas_assert (AARCH64_OPDE_OTHER_ERROR > AARCH64_OPDE_REG_LIST); | |
3914 | return lhs > rhs; | |
3915 | } | |
3916 | ||
3917 | /* Helper routine to get the mnemonic name from the assembly instruction | |
3918 | line; should only be called for the diagnosis purpose, as there is | |
3919 | string copy operation involved, which may affect the runtime | |
3920 | performance if used in elsewhere. */ | |
3921 | ||
3922 | static const char* | |
3923 | get_mnemonic_name (const char *str) | |
3924 | { | |
3925 | static char mnemonic[32]; | |
3926 | char *ptr; | |
3927 | ||
3928 | /* Get the first 15 bytes and assume that the full name is included. */ | |
3929 | strncpy (mnemonic, str, 31); | |
3930 | mnemonic[31] = '\0'; | |
3931 | ||
3932 | /* Scan up to the end of the mnemonic, which must end in white space, | |
3933 | '.', or end of string. */ | |
3934 | for (ptr = mnemonic; is_part_of_name(*ptr); ++ptr) | |
3935 | ; | |
3936 | ||
3937 | *ptr = '\0'; | |
3938 | ||
3939 | /* Append '...' to the truncated long name. */ | |
3940 | if (ptr - mnemonic == 31) | |
3941 | mnemonic[28] = mnemonic[29] = mnemonic[30] = '.'; | |
3942 | ||
3943 | return mnemonic; | |
3944 | } | |
3945 | ||
3946 | static void | |
3947 | reset_aarch64_instruction (aarch64_instruction *instruction) | |
3948 | { | |
3949 | memset (instruction, '\0', sizeof (aarch64_instruction)); | |
3950 | instruction->reloc.type = BFD_RELOC_UNUSED; | |
3951 | } | |
3952 | ||
3953 | /* Data strutures storing one user error in the assembly code related to | |
3954 | operands. */ | |
3955 | ||
3956 | struct operand_error_record | |
3957 | { | |
3958 | const aarch64_opcode *opcode; | |
3959 | aarch64_operand_error detail; | |
3960 | struct operand_error_record *next; | |
3961 | }; | |
3962 | ||
3963 | typedef struct operand_error_record operand_error_record; | |
3964 | ||
3965 | struct operand_errors | |
3966 | { | |
3967 | operand_error_record *head; | |
3968 | operand_error_record *tail; | |
3969 | }; | |
3970 | ||
3971 | typedef struct operand_errors operand_errors; | |
3972 | ||
3973 | /* Top-level data structure reporting user errors for the current line of | |
3974 | the assembly code. | |
3975 | The way md_assemble works is that all opcodes sharing the same mnemonic | |
3976 | name are iterated to find a match to the assembly line. In this data | |
3977 | structure, each of the such opcodes will have one operand_error_record | |
3978 | allocated and inserted. In other words, excessive errors related with | |
3979 | a single opcode are disregarded. */ | |
3980 | operand_errors operand_error_report; | |
3981 | ||
3982 | /* Free record nodes. */ | |
3983 | static operand_error_record *free_opnd_error_record_nodes = NULL; | |
3984 | ||
3985 | /* Initialize the data structure that stores the operand mismatch | |
3986 | information on assembling one line of the assembly code. */ | |
3987 | static void | |
3988 | init_operand_error_report (void) | |
3989 | { | |
3990 | if (operand_error_report.head != NULL) | |
3991 | { | |
3992 | gas_assert (operand_error_report.tail != NULL); | |
3993 | operand_error_report.tail->next = free_opnd_error_record_nodes; | |
3994 | free_opnd_error_record_nodes = operand_error_report.head; | |
3995 | operand_error_report.head = NULL; | |
3996 | operand_error_report.tail = NULL; | |
3997 | return; | |
3998 | } | |
3999 | gas_assert (operand_error_report.tail == NULL); | |
4000 | } | |
4001 | ||
4002 | /* Return TRUE if some operand error has been recorded during the | |
4003 | parsing of the current assembly line using the opcode *OPCODE; | |
4004 | otherwise return FALSE. */ | |
4005 | static inline bfd_boolean | |
4006 | opcode_has_operand_error_p (const aarch64_opcode *opcode) | |
4007 | { | |
4008 | operand_error_record *record = operand_error_report.head; | |
4009 | return record && record->opcode == opcode; | |
4010 | } | |
4011 | ||
4012 | /* Add the error record *NEW_RECORD to operand_error_report. The record's | |
4013 | OPCODE field is initialized with OPCODE. | |
4014 | N.B. only one record for each opcode, i.e. the maximum of one error is | |
4015 | recorded for each instruction template. */ | |
4016 | ||
4017 | static void | |
4018 | add_operand_error_record (const operand_error_record* new_record) | |
4019 | { | |
4020 | const aarch64_opcode *opcode = new_record->opcode; | |
4021 | operand_error_record* record = operand_error_report.head; | |
4022 | ||
4023 | /* The record may have been created for this opcode. If not, we need | |
4024 | to prepare one. */ | |
4025 | if (! opcode_has_operand_error_p (opcode)) | |
4026 | { | |
4027 | /* Get one empty record. */ | |
4028 | if (free_opnd_error_record_nodes == NULL) | |
4029 | { | |
325801bd | 4030 | record = XNEW (operand_error_record); |
a06ea964 NC |
4031 | } |
4032 | else | |
4033 | { | |
4034 | record = free_opnd_error_record_nodes; | |
4035 | free_opnd_error_record_nodes = record->next; | |
4036 | } | |
4037 | record->opcode = opcode; | |
4038 | /* Insert at the head. */ | |
4039 | record->next = operand_error_report.head; | |
4040 | operand_error_report.head = record; | |
4041 | if (operand_error_report.tail == NULL) | |
4042 | operand_error_report.tail = record; | |
4043 | } | |
4044 | else if (record->detail.kind != AARCH64_OPDE_NIL | |
4045 | && record->detail.index <= new_record->detail.index | |
4046 | && operand_error_higher_severity_p (record->detail.kind, | |
4047 | new_record->detail.kind)) | |
4048 | { | |
4049 | /* In the case of multiple errors found on operands related with a | |
4050 | single opcode, only record the error of the leftmost operand and | |
4051 | only if the error is of higher severity. */ | |
4052 | DEBUG_TRACE ("error %s on operand %d not added to the report due to" | |
4053 | " the existing error %s on operand %d", | |
4054 | operand_mismatch_kind_names[new_record->detail.kind], | |
4055 | new_record->detail.index, | |
4056 | operand_mismatch_kind_names[record->detail.kind], | |
4057 | record->detail.index); | |
4058 | return; | |
4059 | } | |
4060 | ||
4061 | record->detail = new_record->detail; | |
4062 | } | |
4063 | ||
4064 | static inline void | |
4065 | record_operand_error_info (const aarch64_opcode *opcode, | |
4066 | aarch64_operand_error *error_info) | |
4067 | { | |
4068 | operand_error_record record; | |
4069 | record.opcode = opcode; | |
4070 | record.detail = *error_info; | |
4071 | add_operand_error_record (&record); | |
4072 | } | |
4073 | ||
4074 | /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed | |
4075 | error message *ERROR, for operand IDX (count from 0). */ | |
4076 | ||
4077 | static void | |
4078 | record_operand_error (const aarch64_opcode *opcode, int idx, | |
4079 | enum aarch64_operand_error_kind kind, | |
4080 | const char* error) | |
4081 | { | |
4082 | aarch64_operand_error info; | |
4083 | memset(&info, 0, sizeof (info)); | |
4084 | info.index = idx; | |
4085 | info.kind = kind; | |
4086 | info.error = error; | |
4087 | record_operand_error_info (opcode, &info); | |
4088 | } | |
4089 | ||
4090 | static void | |
4091 | record_operand_error_with_data (const aarch64_opcode *opcode, int idx, | |
4092 | enum aarch64_operand_error_kind kind, | |
4093 | const char* error, const int *extra_data) | |
4094 | { | |
4095 | aarch64_operand_error info; | |
4096 | info.index = idx; | |
4097 | info.kind = kind; | |
4098 | info.error = error; | |
4099 | info.data[0] = extra_data[0]; | |
4100 | info.data[1] = extra_data[1]; | |
4101 | info.data[2] = extra_data[2]; | |
4102 | record_operand_error_info (opcode, &info); | |
4103 | } | |
4104 | ||
4105 | static void | |
4106 | record_operand_out_of_range_error (const aarch64_opcode *opcode, int idx, | |
4107 | const char* error, int lower_bound, | |
4108 | int upper_bound) | |
4109 | { | |
4110 | int data[3] = {lower_bound, upper_bound, 0}; | |
4111 | record_operand_error_with_data (opcode, idx, AARCH64_OPDE_OUT_OF_RANGE, | |
4112 | error, data); | |
4113 | } | |
4114 | ||
4115 | /* Remove the operand error record for *OPCODE. */ | |
4116 | static void ATTRIBUTE_UNUSED | |
4117 | remove_operand_error_record (const aarch64_opcode *opcode) | |
4118 | { | |
4119 | if (opcode_has_operand_error_p (opcode)) | |
4120 | { | |
4121 | operand_error_record* record = operand_error_report.head; | |
4122 | gas_assert (record != NULL && operand_error_report.tail != NULL); | |
4123 | operand_error_report.head = record->next; | |
4124 | record->next = free_opnd_error_record_nodes; | |
4125 | free_opnd_error_record_nodes = record; | |
4126 | if (operand_error_report.head == NULL) | |
4127 | { | |
4128 | gas_assert (operand_error_report.tail == record); | |
4129 | operand_error_report.tail = NULL; | |
4130 | } | |
4131 | } | |
4132 | } | |
4133 | ||
4134 | /* Given the instruction in *INSTR, return the index of the best matched | |
4135 | qualifier sequence in the list (an array) headed by QUALIFIERS_LIST. | |
4136 | ||
4137 | Return -1 if there is no qualifier sequence; return the first match | |
4138 | if there is multiple matches found. */ | |
4139 | ||
4140 | static int | |
4141 | find_best_match (const aarch64_inst *instr, | |
4142 | const aarch64_opnd_qualifier_seq_t *qualifiers_list) | |
4143 | { | |
4144 | int i, num_opnds, max_num_matched, idx; | |
4145 | ||
4146 | num_opnds = aarch64_num_of_operands (instr->opcode); | |
4147 | if (num_opnds == 0) | |
4148 | { | |
4149 | DEBUG_TRACE ("no operand"); | |
4150 | return -1; | |
4151 | } | |
4152 | ||
4153 | max_num_matched = 0; | |
4154 | idx = -1; | |
4155 | ||
4156 | /* For each pattern. */ | |
4157 | for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list) | |
4158 | { | |
4159 | int j, num_matched; | |
4160 | const aarch64_opnd_qualifier_t *qualifiers = *qualifiers_list; | |
4161 | ||
4162 | /* Most opcodes has much fewer patterns in the list. */ | |
4163 | if (empty_qualifier_sequence_p (qualifiers) == TRUE) | |
4164 | { | |
4165 | DEBUG_TRACE_IF (i == 0, "empty list of qualifier sequence"); | |
4166 | if (i != 0 && idx == -1) | |
4167 | /* If nothing has been matched, return the 1st sequence. */ | |
4168 | idx = 0; | |
4169 | break; | |
4170 | } | |
4171 | ||
4172 | for (j = 0, num_matched = 0; j < num_opnds; ++j, ++qualifiers) | |
4173 | if (*qualifiers == instr->operands[j].qualifier) | |
4174 | ++num_matched; | |
4175 | ||
4176 | if (num_matched > max_num_matched) | |
4177 | { | |
4178 | max_num_matched = num_matched; | |
4179 | idx = i; | |
4180 | } | |
4181 | } | |
4182 | ||
4183 | DEBUG_TRACE ("return with %d", idx); | |
4184 | return idx; | |
4185 | } | |
4186 | ||
4187 | /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the | |
4188 | corresponding operands in *INSTR. */ | |
4189 | ||
4190 | static inline void | |
4191 | assign_qualifier_sequence (aarch64_inst *instr, | |
4192 | const aarch64_opnd_qualifier_t *qualifiers) | |
4193 | { | |
4194 | int i = 0; | |
4195 | int num_opnds = aarch64_num_of_operands (instr->opcode); | |
4196 | gas_assert (num_opnds); | |
4197 | for (i = 0; i < num_opnds; ++i, ++qualifiers) | |
4198 | instr->operands[i].qualifier = *qualifiers; | |
4199 | } | |
4200 | ||
4201 | /* Print operands for the diagnosis purpose. */ | |
4202 | ||
4203 | static void | |
4204 | print_operands (char *buf, const aarch64_opcode *opcode, | |
4205 | const aarch64_opnd_info *opnds) | |
4206 | { | |
4207 | int i; | |
4208 | ||
4209 | for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) | |
4210 | { | |
08d3b0cc | 4211 | char str[128]; |
a06ea964 NC |
4212 | |
4213 | /* We regard the opcode operand info more, however we also look into | |
4214 | the inst->operands to support the disassembling of the optional | |
4215 | operand. | |
4216 | The two operand code should be the same in all cases, apart from | |
4217 | when the operand can be optional. */ | |
4218 | if (opcode->operands[i] == AARCH64_OPND_NIL | |
4219 | || opnds[i].type == AARCH64_OPND_NIL) | |
4220 | break; | |
4221 | ||
4222 | /* Generate the operand string in STR. */ | |
08d3b0cc | 4223 | aarch64_print_operand (str, sizeof (str), 0, opcode, opnds, i, NULL, NULL); |
a06ea964 NC |
4224 | |
4225 | /* Delimiter. */ | |
4226 | if (str[0] != '\0') | |
4227 | strcat (buf, i == 0 ? " " : ","); | |
4228 | ||
4229 | /* Append the operand string. */ | |
4230 | strcat (buf, str); | |
4231 | } | |
4232 | } | |
4233 | ||
4234 | /* Send to stderr a string as information. */ | |
4235 | ||
4236 | static void | |
4237 | output_info (const char *format, ...) | |
4238 | { | |
3b4dbbbf | 4239 | const char *file; |
a06ea964 NC |
4240 | unsigned int line; |
4241 | va_list args; | |
4242 | ||
3b4dbbbf | 4243 | file = as_where (&line); |
a06ea964 NC |
4244 | if (file) |
4245 | { | |
4246 | if (line != 0) | |
4247 | fprintf (stderr, "%s:%u: ", file, line); | |
4248 | else | |
4249 | fprintf (stderr, "%s: ", file); | |
4250 | } | |
4251 | fprintf (stderr, _("Info: ")); | |
4252 | va_start (args, format); | |
4253 | vfprintf (stderr, format, args); | |
4254 | va_end (args); | |
4255 | (void) putc ('\n', stderr); | |
4256 | } | |
4257 | ||
4258 | /* Output one operand error record. */ | |
4259 | ||
4260 | static void | |
4261 | output_operand_error_record (const operand_error_record *record, char *str) | |
4262 | { | |
28f013d5 JB |
4263 | const aarch64_operand_error *detail = &record->detail; |
4264 | int idx = detail->index; | |
a06ea964 | 4265 | const aarch64_opcode *opcode = record->opcode; |
28f013d5 | 4266 | enum aarch64_opnd opd_code = (idx >= 0 ? opcode->operands[idx] |
a06ea964 | 4267 | : AARCH64_OPND_NIL); |
a06ea964 NC |
4268 | |
4269 | switch (detail->kind) | |
4270 | { | |
4271 | case AARCH64_OPDE_NIL: | |
4272 | gas_assert (0); | |
4273 | break; | |
4274 | ||
4275 | case AARCH64_OPDE_SYNTAX_ERROR: | |
4276 | case AARCH64_OPDE_RECOVERABLE: | |
4277 | case AARCH64_OPDE_FATAL_SYNTAX_ERROR: | |
4278 | case AARCH64_OPDE_OTHER_ERROR: | |
a06ea964 NC |
4279 | /* Use the prepared error message if there is, otherwise use the |
4280 | operand description string to describe the error. */ | |
4281 | if (detail->error != NULL) | |
4282 | { | |
28f013d5 | 4283 | if (idx < 0) |
a06ea964 NC |
4284 | as_bad (_("%s -- `%s'"), detail->error, str); |
4285 | else | |
4286 | as_bad (_("%s at operand %d -- `%s'"), | |
28f013d5 | 4287 | detail->error, idx + 1, str); |
a06ea964 NC |
4288 | } |
4289 | else | |
28f013d5 JB |
4290 | { |
4291 | gas_assert (idx >= 0); | |
4292 | as_bad (_("operand %d should be %s -- `%s'"), idx + 1, | |
a06ea964 | 4293 | aarch64_get_operand_desc (opd_code), str); |
28f013d5 | 4294 | } |
a06ea964 NC |
4295 | break; |
4296 | ||
4297 | case AARCH64_OPDE_INVALID_VARIANT: | |
4298 | as_bad (_("operand mismatch -- `%s'"), str); | |
4299 | if (verbose_error_p) | |
4300 | { | |
4301 | /* We will try to correct the erroneous instruction and also provide | |
4302 | more information e.g. all other valid variants. | |
4303 | ||
4304 | The string representation of the corrected instruction and other | |
4305 | valid variants are generated by | |
4306 | ||
4307 | 1) obtaining the intermediate representation of the erroneous | |
4308 | instruction; | |
4309 | 2) manipulating the IR, e.g. replacing the operand qualifier; | |
4310 | 3) printing out the instruction by calling the printer functions | |
4311 | shared with the disassembler. | |
4312 | ||
4313 | The limitation of this method is that the exact input assembly | |
4314 | line cannot be accurately reproduced in some cases, for example an | |
4315 | optional operand present in the actual assembly line will be | |
4316 | omitted in the output; likewise for the optional syntax rules, | |
4317 | e.g. the # before the immediate. Another limitation is that the | |
4318 | assembly symbols and relocation operations in the assembly line | |
4319 | currently cannot be printed out in the error report. Last but not | |
4320 | least, when there is other error(s) co-exist with this error, the | |
4321 | 'corrected' instruction may be still incorrect, e.g. given | |
4322 | 'ldnp h0,h1,[x0,#6]!' | |
4323 | this diagnosis will provide the version: | |
4324 | 'ldnp s0,s1,[x0,#6]!' | |
4325 | which is still not right. */ | |
4326 | size_t len = strlen (get_mnemonic_name (str)); | |
4327 | int i, qlf_idx; | |
4328 | bfd_boolean result; | |
08d3b0cc | 4329 | char buf[2048]; |
a06ea964 NC |
4330 | aarch64_inst *inst_base = &inst.base; |
4331 | const aarch64_opnd_qualifier_seq_t *qualifiers_list; | |
4332 | ||
4333 | /* Init inst. */ | |
4334 | reset_aarch64_instruction (&inst); | |
4335 | inst_base->opcode = opcode; | |
4336 | ||
4337 | /* Reset the error report so that there is no side effect on the | |
4338 | following operand parsing. */ | |
4339 | init_operand_error_report (); | |
4340 | ||
4341 | /* Fill inst. */ | |
4342 | result = parse_operands (str + len, opcode) | |
4343 | && programmer_friendly_fixup (&inst); | |
4344 | gas_assert (result); | |
4345 | result = aarch64_opcode_encode (opcode, inst_base, &inst_base->value, | |
4346 | NULL, NULL); | |
4347 | gas_assert (!result); | |
4348 | ||
4349 | /* Find the most matched qualifier sequence. */ | |
4350 | qlf_idx = find_best_match (inst_base, opcode->qualifiers_list); | |
4351 | gas_assert (qlf_idx > -1); | |
4352 | ||
4353 | /* Assign the qualifiers. */ | |
4354 | assign_qualifier_sequence (inst_base, | |
4355 | opcode->qualifiers_list[qlf_idx]); | |
4356 | ||
4357 | /* Print the hint. */ | |
4358 | output_info (_(" did you mean this?")); | |
08d3b0cc | 4359 | snprintf (buf, sizeof (buf), "\t%s", get_mnemonic_name (str)); |
a06ea964 NC |
4360 | print_operands (buf, opcode, inst_base->operands); |
4361 | output_info (_(" %s"), buf); | |
4362 | ||
4363 | /* Print out other variant(s) if there is any. */ | |
4364 | if (qlf_idx != 0 || | |
4365 | !empty_qualifier_sequence_p (opcode->qualifiers_list[1])) | |
4366 | output_info (_(" other valid variant(s):")); | |
4367 | ||
4368 | /* For each pattern. */ | |
4369 | qualifiers_list = opcode->qualifiers_list; | |
4370 | for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list) | |
4371 | { | |
4372 | /* Most opcodes has much fewer patterns in the list. | |
4373 | First NIL qualifier indicates the end in the list. */ | |
4374 | if (empty_qualifier_sequence_p (*qualifiers_list) == TRUE) | |
4375 | break; | |
4376 | ||
4377 | if (i != qlf_idx) | |
4378 | { | |
4379 | /* Mnemonics name. */ | |
08d3b0cc | 4380 | snprintf (buf, sizeof (buf), "\t%s", get_mnemonic_name (str)); |
a06ea964 NC |
4381 | |
4382 | /* Assign the qualifiers. */ | |
4383 | assign_qualifier_sequence (inst_base, *qualifiers_list); | |
4384 | ||
4385 | /* Print instruction. */ | |
4386 | print_operands (buf, opcode, inst_base->operands); | |
4387 | ||
4388 | output_info (_(" %s"), buf); | |
4389 | } | |
4390 | } | |
4391 | } | |
4392 | break; | |
4393 | ||
4394 | case AARCH64_OPDE_OUT_OF_RANGE: | |
f5555712 YZ |
4395 | if (detail->data[0] != detail->data[1]) |
4396 | as_bad (_("%s out of range %d to %d at operand %d -- `%s'"), | |
4397 | detail->error ? detail->error : _("immediate value"), | |
28f013d5 | 4398 | detail->data[0], detail->data[1], idx + 1, str); |
f5555712 YZ |
4399 | else |
4400 | as_bad (_("%s expected to be %d at operand %d -- `%s'"), | |
4401 | detail->error ? detail->error : _("immediate value"), | |
28f013d5 | 4402 | detail->data[0], idx + 1, str); |
a06ea964 NC |
4403 | break; |
4404 | ||
4405 | case AARCH64_OPDE_REG_LIST: | |
4406 | if (detail->data[0] == 1) | |
4407 | as_bad (_("invalid number of registers in the list; " | |
4408 | "only 1 register is expected at operand %d -- `%s'"), | |
28f013d5 | 4409 | idx + 1, str); |
a06ea964 NC |
4410 | else |
4411 | as_bad (_("invalid number of registers in the list; " | |
4412 | "%d registers are expected at operand %d -- `%s'"), | |
28f013d5 | 4413 | detail->data[0], idx + 1, str); |
a06ea964 NC |
4414 | break; |
4415 | ||
4416 | case AARCH64_OPDE_UNALIGNED: | |
4417 | as_bad (_("immediate value should be a multiple of " | |
4418 | "%d at operand %d -- `%s'"), | |
28f013d5 | 4419 | detail->data[0], idx + 1, str); |
a06ea964 NC |
4420 | break; |
4421 | ||
4422 | default: | |
4423 | gas_assert (0); | |
4424 | break; | |
4425 | } | |
4426 | } | |
4427 | ||
4428 | /* Process and output the error message about the operand mismatching. | |
4429 | ||
4430 | When this function is called, the operand error information had | |
4431 | been collected for an assembly line and there will be multiple | |
4432 | errors in the case of mulitple instruction templates; output the | |
4433 | error message that most closely describes the problem. */ | |
4434 | ||
4435 | static void | |
4436 | output_operand_error_report (char *str) | |
4437 | { | |
4438 | int largest_error_pos; | |
4439 | const char *msg = NULL; | |
4440 | enum aarch64_operand_error_kind kind; | |
4441 | operand_error_record *curr; | |
4442 | operand_error_record *head = operand_error_report.head; | |
4443 | operand_error_record *record = NULL; | |
4444 | ||
4445 | /* No error to report. */ | |
4446 | if (head == NULL) | |
4447 | return; | |
4448 | ||
4449 | gas_assert (head != NULL && operand_error_report.tail != NULL); | |
4450 | ||
4451 | /* Only one error. */ | |
4452 | if (head == operand_error_report.tail) | |
4453 | { | |
4454 | DEBUG_TRACE ("single opcode entry with error kind: %s", | |
4455 | operand_mismatch_kind_names[head->detail.kind]); | |
4456 | output_operand_error_record (head, str); | |
4457 | return; | |
4458 | } | |
4459 | ||
4460 | /* Find the error kind of the highest severity. */ | |
4461 | DEBUG_TRACE ("multiple opcode entres with error kind"); | |
4462 | kind = AARCH64_OPDE_NIL; | |
4463 | for (curr = head; curr != NULL; curr = curr->next) | |
4464 | { | |
4465 | gas_assert (curr->detail.kind != AARCH64_OPDE_NIL); | |
4466 | DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]); | |
4467 | if (operand_error_higher_severity_p (curr->detail.kind, kind)) | |
4468 | kind = curr->detail.kind; | |
4469 | } | |
4470 | gas_assert (kind != AARCH64_OPDE_NIL); | |
4471 | ||
4472 | /* Pick up one of errors of KIND to report. */ | |
4473 | largest_error_pos = -2; /* Index can be -1 which means unknown index. */ | |
4474 | for (curr = head; curr != NULL; curr = curr->next) | |
4475 | { | |
4476 | if (curr->detail.kind != kind) | |
4477 | continue; | |
4478 | /* If there are multiple errors, pick up the one with the highest | |
4479 | mismatching operand index. In the case of multiple errors with | |
4480 | the equally highest operand index, pick up the first one or the | |
4481 | first one with non-NULL error message. */ | |
4482 | if (curr->detail.index > largest_error_pos | |
4483 | || (curr->detail.index == largest_error_pos && msg == NULL | |
4484 | && curr->detail.error != NULL)) | |
4485 | { | |
4486 | largest_error_pos = curr->detail.index; | |
4487 | record = curr; | |
4488 | msg = record->detail.error; | |
4489 | } | |
4490 | } | |
4491 | ||
4492 | gas_assert (largest_error_pos != -2 && record != NULL); | |
4493 | DEBUG_TRACE ("Pick up error kind %s to report", | |
4494 | operand_mismatch_kind_names[record->detail.kind]); | |
4495 | ||
4496 | /* Output. */ | |
4497 | output_operand_error_record (record, str); | |
4498 | } | |
4499 | \f | |
4500 | /* Write an AARCH64 instruction to buf - always little-endian. */ | |
4501 | static void | |
4502 | put_aarch64_insn (char *buf, uint32_t insn) | |
4503 | { | |
4504 | unsigned char *where = (unsigned char *) buf; | |
4505 | where[0] = insn; | |
4506 | where[1] = insn >> 8; | |
4507 | where[2] = insn >> 16; | |
4508 | where[3] = insn >> 24; | |
4509 | } | |
4510 | ||
4511 | static uint32_t | |
4512 | get_aarch64_insn (char *buf) | |
4513 | { | |
4514 | unsigned char *where = (unsigned char *) buf; | |
4515 | uint32_t result; | |
4516 | result = (where[0] | (where[1] << 8) | (where[2] << 16) | (where[3] << 24)); | |
4517 | return result; | |
4518 | } | |
4519 | ||
4520 | static void | |
4521 | output_inst (struct aarch64_inst *new_inst) | |
4522 | { | |
4523 | char *to = NULL; | |
4524 | ||
4525 | to = frag_more (INSN_SIZE); | |
4526 | ||
4527 | frag_now->tc_frag_data.recorded = 1; | |
4528 | ||
4529 | put_aarch64_insn (to, inst.base.value); | |
4530 | ||
4531 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
4532 | { | |
4533 | fixS *fixp = fix_new_aarch64 (frag_now, to - frag_now->fr_literal, | |
4534 | INSN_SIZE, &inst.reloc.exp, | |
4535 | inst.reloc.pc_rel, | |
4536 | inst.reloc.type); | |
4537 | DEBUG_TRACE ("Prepared relocation fix up"); | |
4538 | /* Don't check the addend value against the instruction size, | |
4539 | that's the job of our code in md_apply_fix(). */ | |
4540 | fixp->fx_no_overflow = 1; | |
4541 | if (new_inst != NULL) | |
4542 | fixp->tc_fix_data.inst = new_inst; | |
4543 | if (aarch64_gas_internal_fixup_p ()) | |
4544 | { | |
4545 | gas_assert (inst.reloc.opnd != AARCH64_OPND_NIL); | |
4546 | fixp->tc_fix_data.opnd = inst.reloc.opnd; | |
4547 | fixp->fx_addnumber = inst.reloc.flags; | |
4548 | } | |
4549 | } | |
4550 | ||
4551 | dwarf2_emit_insn (INSN_SIZE); | |
4552 | } | |
4553 | ||
4554 | /* Link together opcodes of the same name. */ | |
4555 | ||
4556 | struct templates | |
4557 | { | |
4558 | aarch64_opcode *opcode; | |
4559 | struct templates *next; | |
4560 | }; | |
4561 | ||
4562 | typedef struct templates templates; | |
4563 | ||
4564 | static templates * | |
4565 | lookup_mnemonic (const char *start, int len) | |
4566 | { | |
4567 | templates *templ = NULL; | |
4568 | ||
4569 | templ = hash_find_n (aarch64_ops_hsh, start, len); | |
4570 | return templ; | |
4571 | } | |
4572 | ||
4573 | /* Subroutine of md_assemble, responsible for looking up the primary | |
4574 | opcode from the mnemonic the user wrote. STR points to the | |
4575 | beginning of the mnemonic. */ | |
4576 | ||
4577 | static templates * | |
4578 | opcode_lookup (char **str) | |
4579 | { | |
4580 | char *end, *base; | |
4581 | const aarch64_cond *cond; | |
4582 | char condname[16]; | |
4583 | int len; | |
4584 | ||
4585 | /* Scan up to the end of the mnemonic, which must end in white space, | |
4586 | '.', or end of string. */ | |
4587 | for (base = end = *str; is_part_of_name(*end); end++) | |
4588 | if (*end == '.') | |
4589 | break; | |
4590 | ||
4591 | if (end == base) | |
4592 | return 0; | |
4593 | ||
4594 | inst.cond = COND_ALWAYS; | |
4595 | ||
4596 | /* Handle a possible condition. */ | |
4597 | if (end[0] == '.') | |
4598 | { | |
4599 | cond = hash_find_n (aarch64_cond_hsh, end + 1, 2); | |
4600 | if (cond) | |
4601 | { | |
4602 | inst.cond = cond->value; | |
4603 | *str = end + 3; | |
4604 | } | |
4605 | else | |
4606 | { | |
4607 | *str = end; | |
4608 | return 0; | |
4609 | } | |
4610 | } | |
4611 | else | |
4612 | *str = end; | |
4613 | ||
4614 | len = end - base; | |
4615 | ||
4616 | if (inst.cond == COND_ALWAYS) | |
4617 | { | |
4618 | /* Look for unaffixed mnemonic. */ | |
4619 | return lookup_mnemonic (base, len); | |
4620 | } | |
4621 | else if (len <= 13) | |
4622 | { | |
4623 | /* append ".c" to mnemonic if conditional */ | |
4624 | memcpy (condname, base, len); | |
4625 | memcpy (condname + len, ".c", 2); | |
4626 | base = condname; | |
4627 | len += 2; | |
4628 | return lookup_mnemonic (base, len); | |
4629 | } | |
4630 | ||
4631 | return NULL; | |
4632 | } | |
4633 | ||
4634 | /* Internal helper routine converting a vector neon_type_el structure | |
4635 | *VECTYPE to a corresponding operand qualifier. */ | |
4636 | ||
4637 | static inline aarch64_opnd_qualifier_t | |
4638 | vectype_to_qualifier (const struct neon_type_el *vectype) | |
4639 | { | |
4640 | /* Element size in bytes indexed by neon_el_type. */ | |
4641 | const unsigned char ele_size[5] | |
4642 | = {1, 2, 4, 8, 16}; | |
65f2205d MW |
4643 | const unsigned int ele_base [5] = |
4644 | { | |
4645 | AARCH64_OPND_QLF_V_8B, | |
3067d3b9 | 4646 | AARCH64_OPND_QLF_V_2H, |
65f2205d MW |
4647 | AARCH64_OPND_QLF_V_2S, |
4648 | AARCH64_OPND_QLF_V_1D, | |
4649 | AARCH64_OPND_QLF_V_1Q | |
4650 | }; | |
a06ea964 NC |
4651 | |
4652 | if (!vectype->defined || vectype->type == NT_invtype) | |
4653 | goto vectype_conversion_fail; | |
4654 | ||
4655 | gas_assert (vectype->type >= NT_b && vectype->type <= NT_q); | |
4656 | ||
4657 | if (vectype->defined & NTA_HASINDEX) | |
4658 | /* Vector element register. */ | |
4659 | return AARCH64_OPND_QLF_S_B + vectype->type; | |
4660 | else | |
4661 | { | |
4662 | /* Vector register. */ | |
4663 | int reg_size = ele_size[vectype->type] * vectype->width; | |
4664 | unsigned offset; | |
65f2205d | 4665 | unsigned shift; |
3067d3b9 | 4666 | if (reg_size != 16 && reg_size != 8 && reg_size != 4) |
a06ea964 | 4667 | goto vectype_conversion_fail; |
65f2205d MW |
4668 | |
4669 | /* The conversion is by calculating the offset from the base operand | |
4670 | qualifier for the vector type. The operand qualifiers are regular | |
4671 | enough that the offset can established by shifting the vector width by | |
4672 | a vector-type dependent amount. */ | |
4673 | shift = 0; | |
4674 | if (vectype->type == NT_b) | |
4675 | shift = 4; | |
3067d3b9 | 4676 | else if (vectype->type == NT_h || vectype->type == NT_s) |
65f2205d MW |
4677 | shift = 2; |
4678 | else if (vectype->type >= NT_d) | |
4679 | shift = 1; | |
4680 | else | |
4681 | gas_assert (0); | |
4682 | ||
4683 | offset = ele_base [vectype->type] + (vectype->width >> shift); | |
4684 | gas_assert (AARCH64_OPND_QLF_V_8B <= offset | |
4685 | && offset <= AARCH64_OPND_QLF_V_1Q); | |
4686 | return offset; | |
a06ea964 NC |
4687 | } |
4688 | ||
4689 | vectype_conversion_fail: | |
4690 | first_error (_("bad vector arrangement type")); | |
4691 | return AARCH64_OPND_QLF_NIL; | |
4692 | } | |
4693 | ||
4694 | /* Process an optional operand that is found omitted from the assembly line. | |
4695 | Fill *OPERAND for such an operand of type TYPE. OPCODE points to the | |
4696 | instruction's opcode entry while IDX is the index of this omitted operand. | |
4697 | */ | |
4698 | ||
4699 | static void | |
4700 | process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode, | |
4701 | int idx, aarch64_opnd_info *operand) | |
4702 | { | |
4703 | aarch64_insn default_value = get_optional_operand_default_value (opcode); | |
4704 | gas_assert (optional_operand_p (opcode, idx)); | |
4705 | gas_assert (!operand->present); | |
4706 | ||
4707 | switch (type) | |
4708 | { | |
4709 | case AARCH64_OPND_Rd: | |
4710 | case AARCH64_OPND_Rn: | |
4711 | case AARCH64_OPND_Rm: | |
4712 | case AARCH64_OPND_Rt: | |
4713 | case AARCH64_OPND_Rt2: | |
4714 | case AARCH64_OPND_Rs: | |
4715 | case AARCH64_OPND_Ra: | |
4716 | case AARCH64_OPND_Rt_SYS: | |
4717 | case AARCH64_OPND_Rd_SP: | |
4718 | case AARCH64_OPND_Rn_SP: | |
4719 | case AARCH64_OPND_Fd: | |
4720 | case AARCH64_OPND_Fn: | |
4721 | case AARCH64_OPND_Fm: | |
4722 | case AARCH64_OPND_Fa: | |
4723 | case AARCH64_OPND_Ft: | |
4724 | case AARCH64_OPND_Ft2: | |
4725 | case AARCH64_OPND_Sd: | |
4726 | case AARCH64_OPND_Sn: | |
4727 | case AARCH64_OPND_Sm: | |
4728 | case AARCH64_OPND_Vd: | |
4729 | case AARCH64_OPND_Vn: | |
4730 | case AARCH64_OPND_Vm: | |
4731 | case AARCH64_OPND_VdD1: | |
4732 | case AARCH64_OPND_VnD1: | |
4733 | operand->reg.regno = default_value; | |
4734 | break; | |
4735 | ||
4736 | case AARCH64_OPND_Ed: | |
4737 | case AARCH64_OPND_En: | |
4738 | case AARCH64_OPND_Em: | |
4739 | operand->reglane.regno = default_value; | |
4740 | break; | |
4741 | ||
4742 | case AARCH64_OPND_IDX: | |
4743 | case AARCH64_OPND_BIT_NUM: | |
4744 | case AARCH64_OPND_IMMR: | |
4745 | case AARCH64_OPND_IMMS: | |
4746 | case AARCH64_OPND_SHLL_IMM: | |
4747 | case AARCH64_OPND_IMM_VLSL: | |
4748 | case AARCH64_OPND_IMM_VLSR: | |
4749 | case AARCH64_OPND_CCMP_IMM: | |
4750 | case AARCH64_OPND_FBITS: | |
4751 | case AARCH64_OPND_UIMM4: | |
4752 | case AARCH64_OPND_UIMM3_OP1: | |
4753 | case AARCH64_OPND_UIMM3_OP2: | |
4754 | case AARCH64_OPND_IMM: | |
4755 | case AARCH64_OPND_WIDTH: | |
4756 | case AARCH64_OPND_UIMM7: | |
4757 | case AARCH64_OPND_NZCV: | |
4758 | operand->imm.value = default_value; | |
4759 | break; | |
4760 | ||
4761 | case AARCH64_OPND_EXCEPTION: | |
4762 | inst.reloc.type = BFD_RELOC_UNUSED; | |
4763 | break; | |
4764 | ||
4765 | case AARCH64_OPND_BARRIER_ISB: | |
4766 | operand->barrier = aarch64_barrier_options + default_value; | |
4767 | ||
4768 | default: | |
4769 | break; | |
4770 | } | |
4771 | } | |
4772 | ||
4773 | /* Process the relocation type for move wide instructions. | |
4774 | Return TRUE on success; otherwise return FALSE. */ | |
4775 | ||
4776 | static bfd_boolean | |
4777 | process_movw_reloc_info (void) | |
4778 | { | |
4779 | int is32; | |
4780 | unsigned shift; | |
4781 | ||
4782 | is32 = inst.base.operands[0].qualifier == AARCH64_OPND_QLF_W ? 1 : 0; | |
4783 | ||
4784 | if (inst.base.opcode->op == OP_MOVK) | |
4785 | switch (inst.reloc.type) | |
4786 | { | |
4787 | case BFD_RELOC_AARCH64_MOVW_G0_S: | |
4788 | case BFD_RELOC_AARCH64_MOVW_G1_S: | |
4789 | case BFD_RELOC_AARCH64_MOVW_G2_S: | |
1aa66fb1 | 4790 | case BFD_RELOC_AARCH64_TLSGD_MOVW_G1: |
a06ea964 | 4791 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0: |
a06ea964 | 4792 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1: |
a06ea964 NC |
4793 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2: |
4794 | set_syntax_error | |
4795 | (_("the specified relocation type is not allowed for MOVK")); | |
4796 | return FALSE; | |
4797 | default: | |
4798 | break; | |
4799 | } | |
4800 | ||
4801 | switch (inst.reloc.type) | |
4802 | { | |
4803 | case BFD_RELOC_AARCH64_MOVW_G0: | |
a06ea964 | 4804 | case BFD_RELOC_AARCH64_MOVW_G0_NC: |
f09c556a | 4805 | case BFD_RELOC_AARCH64_MOVW_G0_S: |
ca632371 | 4806 | case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC: |
43a357f9 | 4807 | case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC: |
3e8286c0 | 4808 | case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC: |
3b957e5b | 4809 | case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC: |
49df5539 JW |
4810 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0: |
4811 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC: | |
a06ea964 NC |
4812 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0: |
4813 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC: | |
4814 | shift = 0; | |
4815 | break; | |
4816 | case BFD_RELOC_AARCH64_MOVW_G1: | |
a06ea964 | 4817 | case BFD_RELOC_AARCH64_MOVW_G1_NC: |
f09c556a | 4818 | case BFD_RELOC_AARCH64_MOVW_G1_S: |
654248e7 | 4819 | case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1: |
43a357f9 | 4820 | case BFD_RELOC_AARCH64_TLSDESC_OFF_G1: |
1aa66fb1 | 4821 | case BFD_RELOC_AARCH64_TLSGD_MOVW_G1: |
3b957e5b | 4822 | case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1: |
49df5539 JW |
4823 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1: |
4824 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC: | |
a06ea964 NC |
4825 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1: |
4826 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC: | |
4827 | shift = 16; | |
4828 | break; | |
4829 | case BFD_RELOC_AARCH64_MOVW_G2: | |
a06ea964 | 4830 | case BFD_RELOC_AARCH64_MOVW_G2_NC: |
f09c556a | 4831 | case BFD_RELOC_AARCH64_MOVW_G2_S: |
49df5539 | 4832 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2: |
a06ea964 NC |
4833 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2: |
4834 | if (is32) | |
4835 | { | |
4836 | set_fatal_syntax_error | |
4837 | (_("the specified relocation type is not allowed for 32-bit " | |
4838 | "register")); | |
4839 | return FALSE; | |
4840 | } | |
4841 | shift = 32; | |
4842 | break; | |
4843 | case BFD_RELOC_AARCH64_MOVW_G3: | |
4844 | if (is32) | |
4845 | { | |
4846 | set_fatal_syntax_error | |
4847 | (_("the specified relocation type is not allowed for 32-bit " | |
4848 | "register")); | |
4849 | return FALSE; | |
4850 | } | |
4851 | shift = 48; | |
4852 | break; | |
4853 | default: | |
4854 | /* More cases should be added when more MOVW-related relocation types | |
4855 | are supported in GAS. */ | |
4856 | gas_assert (aarch64_gas_internal_fixup_p ()); | |
4857 | /* The shift amount should have already been set by the parser. */ | |
4858 | return TRUE; | |
4859 | } | |
4860 | inst.base.operands[1].shifter.amount = shift; | |
4861 | return TRUE; | |
4862 | } | |
4863 | ||
4864 | /* A primitive log caculator. */ | |
4865 | ||
4866 | static inline unsigned int | |
4867 | get_logsz (unsigned int size) | |
4868 | { | |
4869 | const unsigned char ls[16] = | |
4870 | {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4}; | |
4871 | if (size > 16) | |
4872 | { | |
4873 | gas_assert (0); | |
4874 | return -1; | |
4875 | } | |
4876 | gas_assert (ls[size - 1] != (unsigned char)-1); | |
4877 | return ls[size - 1]; | |
4878 | } | |
4879 | ||
4880 | /* Determine and return the real reloc type code for an instruction | |
4881 | with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */ | |
4882 | ||
4883 | static inline bfd_reloc_code_real_type | |
4884 | ldst_lo12_determine_real_reloc_type (void) | |
4885 | { | |
4c562523 | 4886 | unsigned logsz; |
a06ea964 NC |
4887 | enum aarch64_opnd_qualifier opd0_qlf = inst.base.operands[0].qualifier; |
4888 | enum aarch64_opnd_qualifier opd1_qlf = inst.base.operands[1].qualifier; | |
4889 | ||
4c562523 JW |
4890 | const bfd_reloc_code_real_type reloc_ldst_lo12[3][5] = { |
4891 | { | |
4892 | BFD_RELOC_AARCH64_LDST8_LO12, | |
4893 | BFD_RELOC_AARCH64_LDST16_LO12, | |
4894 | BFD_RELOC_AARCH64_LDST32_LO12, | |
4895 | BFD_RELOC_AARCH64_LDST64_LO12, | |
a06ea964 | 4896 | BFD_RELOC_AARCH64_LDST128_LO12 |
4c562523 JW |
4897 | }, |
4898 | { | |
4899 | BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, | |
4900 | BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, | |
4901 | BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, | |
4902 | BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, | |
4903 | BFD_RELOC_AARCH64_NONE | |
4904 | }, | |
4905 | { | |
4906 | BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC, | |
4907 | BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC, | |
4908 | BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC, | |
4909 | BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC, | |
4910 | BFD_RELOC_AARCH64_NONE | |
4911 | } | |
a06ea964 NC |
4912 | }; |
4913 | ||
4c562523 JW |
4914 | gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12 |
4915 | || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12 | |
4916 | || (inst.reloc.type | |
4917 | == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC)); | |
a06ea964 NC |
4918 | gas_assert (inst.base.opcode->operands[1] == AARCH64_OPND_ADDR_UIMM12); |
4919 | ||
4920 | if (opd1_qlf == AARCH64_OPND_QLF_NIL) | |
4921 | opd1_qlf = | |
4922 | aarch64_get_expected_qualifier (inst.base.opcode->qualifiers_list, | |
4923 | 1, opd0_qlf, 0); | |
4924 | gas_assert (opd1_qlf != AARCH64_OPND_QLF_NIL); | |
4925 | ||
4926 | logsz = get_logsz (aarch64_get_qualifier_esize (opd1_qlf)); | |
4c562523 JW |
4927 | if (inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12 |
4928 | || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC) | |
4929 | gas_assert (logsz <= 3); | |
4930 | else | |
4931 | gas_assert (logsz <= 4); | |
a06ea964 | 4932 | |
4c562523 JW |
4933 | /* In reloc.c, these pseudo relocation types should be defined in similar |
4934 | order as above reloc_ldst_lo12 array. Because the array index calcuation | |
4935 | below relies on this. */ | |
4936 | return reloc_ldst_lo12[inst.reloc.type - BFD_RELOC_AARCH64_LDST_LO12][logsz]; | |
a06ea964 NC |
4937 | } |
4938 | ||
4939 | /* Check whether a register list REGINFO is valid. The registers must be | |
4940 | numbered in increasing order (modulo 32), in increments of one or two. | |
4941 | ||
4942 | If ACCEPT_ALTERNATE is non-zero, the register numbers should be in | |
4943 | increments of two. | |
4944 | ||
4945 | Return FALSE if such a register list is invalid, otherwise return TRUE. */ | |
4946 | ||
4947 | static bfd_boolean | |
4948 | reg_list_valid_p (uint32_t reginfo, int accept_alternate) | |
4949 | { | |
4950 | uint32_t i, nb_regs, prev_regno, incr; | |
4951 | ||
4952 | nb_regs = 1 + (reginfo & 0x3); | |
4953 | reginfo >>= 2; | |
4954 | prev_regno = reginfo & 0x1f; | |
4955 | incr = accept_alternate ? 2 : 1; | |
4956 | ||
4957 | for (i = 1; i < nb_regs; ++i) | |
4958 | { | |
4959 | uint32_t curr_regno; | |
4960 | reginfo >>= 5; | |
4961 | curr_regno = reginfo & 0x1f; | |
4962 | if (curr_regno != ((prev_regno + incr) & 0x1f)) | |
4963 | return FALSE; | |
4964 | prev_regno = curr_regno; | |
4965 | } | |
4966 | ||
4967 | return TRUE; | |
4968 | } | |
4969 | ||
4970 | /* Generic instruction operand parser. This does no encoding and no | |
4971 | semantic validation; it merely squirrels values away in the inst | |
4972 | structure. Returns TRUE or FALSE depending on whether the | |
4973 | specified grammar matched. */ | |
4974 | ||
4975 | static bfd_boolean | |
4976 | parse_operands (char *str, const aarch64_opcode *opcode) | |
4977 | { | |
4978 | int i; | |
4979 | char *backtrack_pos = 0; | |
4980 | const enum aarch64_opnd *operands = opcode->operands; | |
4981 | ||
4982 | clear_error (); | |
4983 | skip_whitespace (str); | |
4984 | ||
4985 | for (i = 0; operands[i] != AARCH64_OPND_NIL; i++) | |
4986 | { | |
4987 | int64_t val; | |
4988 | int isreg32, isregzero; | |
4989 | int comma_skipped_p = 0; | |
4990 | aarch64_reg_type rtype; | |
4991 | struct neon_type_el vectype; | |
4992 | aarch64_opnd_info *info = &inst.base.operands[i]; | |
4993 | ||
4994 | DEBUG_TRACE ("parse operand %d", i); | |
4995 | ||
4996 | /* Assign the operand code. */ | |
4997 | info->type = operands[i]; | |
4998 | ||
4999 | if (optional_operand_p (opcode, i)) | |
5000 | { | |
5001 | /* Remember where we are in case we need to backtrack. */ | |
5002 | gas_assert (!backtrack_pos); | |
5003 | backtrack_pos = str; | |
5004 | } | |
5005 | ||
5006 | /* Expect comma between operands; the backtrack mechanizm will take | |
5007 | care of cases of omitted optional operand. */ | |
5008 | if (i > 0 && ! skip_past_char (&str, ',')) | |
5009 | { | |
5010 | set_syntax_error (_("comma expected between operands")); | |
5011 | goto failure; | |
5012 | } | |
5013 | else | |
5014 | comma_skipped_p = 1; | |
5015 | ||
5016 | switch (operands[i]) | |
5017 | { | |
5018 | case AARCH64_OPND_Rd: | |
5019 | case AARCH64_OPND_Rn: | |
5020 | case AARCH64_OPND_Rm: | |
5021 | case AARCH64_OPND_Rt: | |
5022 | case AARCH64_OPND_Rt2: | |
5023 | case AARCH64_OPND_Rs: | |
5024 | case AARCH64_OPND_Ra: | |
5025 | case AARCH64_OPND_Rt_SYS: | |
ee804238 | 5026 | case AARCH64_OPND_PAIRREG: |
a06ea964 NC |
5027 | po_int_reg_or_fail (1, 0); |
5028 | break; | |
5029 | ||
5030 | case AARCH64_OPND_Rd_SP: | |
5031 | case AARCH64_OPND_Rn_SP: | |
5032 | po_int_reg_or_fail (0, 1); | |
5033 | break; | |
5034 | ||
5035 | case AARCH64_OPND_Rm_EXT: | |
5036 | case AARCH64_OPND_Rm_SFT: | |
5037 | po_misc_or_fail (parse_shifter_operand | |
5038 | (&str, info, (operands[i] == AARCH64_OPND_Rm_EXT | |
5039 | ? SHIFTED_ARITH_IMM | |
5040 | : SHIFTED_LOGIC_IMM))); | |
5041 | if (!info->shifter.operator_present) | |
5042 | { | |
5043 | /* Default to LSL if not present. Libopcodes prefers shifter | |
5044 | kind to be explicit. */ | |
5045 | gas_assert (info->shifter.kind == AARCH64_MOD_NONE); | |
5046 | info->shifter.kind = AARCH64_MOD_LSL; | |
5047 | /* For Rm_EXT, libopcodes will carry out further check on whether | |
5048 | or not stack pointer is used in the instruction (Recall that | |
5049 | "the extend operator is not optional unless at least one of | |
5050 | "Rd" or "Rn" is '11111' (i.e. WSP)"). */ | |
5051 | } | |
5052 | break; | |
5053 | ||
5054 | case AARCH64_OPND_Fd: | |
5055 | case AARCH64_OPND_Fn: | |
5056 | case AARCH64_OPND_Fm: | |
5057 | case AARCH64_OPND_Fa: | |
5058 | case AARCH64_OPND_Ft: | |
5059 | case AARCH64_OPND_Ft2: | |
5060 | case AARCH64_OPND_Sd: | |
5061 | case AARCH64_OPND_Sn: | |
5062 | case AARCH64_OPND_Sm: | |
5063 | val = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, &rtype, NULL); | |
5064 | if (val == PARSE_FAIL) | |
5065 | { | |
5066 | first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ))); | |
5067 | goto failure; | |
5068 | } | |
5069 | gas_assert (rtype >= REG_TYPE_FP_B && rtype <= REG_TYPE_FP_Q); | |
5070 | ||
5071 | info->reg.regno = val; | |
5072 | info->qualifier = AARCH64_OPND_QLF_S_B + (rtype - REG_TYPE_FP_B); | |
5073 | break; | |
5074 | ||
5075 | case AARCH64_OPND_Vd: | |
5076 | case AARCH64_OPND_Vn: | |
5077 | case AARCH64_OPND_Vm: | |
5078 | val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype); | |
5079 | if (val == PARSE_FAIL) | |
5080 | { | |
5081 | first_error (_(get_reg_expected_msg (REG_TYPE_VN))); | |
5082 | goto failure; | |
5083 | } | |
5084 | if (vectype.defined & NTA_HASINDEX) | |
5085 | goto failure; | |
5086 | ||
5087 | info->reg.regno = val; | |
5088 | info->qualifier = vectype_to_qualifier (&vectype); | |
5089 | if (info->qualifier == AARCH64_OPND_QLF_NIL) | |
5090 | goto failure; | |
5091 | break; | |
5092 | ||
5093 | case AARCH64_OPND_VdD1: | |
5094 | case AARCH64_OPND_VnD1: | |
5095 | val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype); | |
5096 | if (val == PARSE_FAIL) | |
5097 | { | |
5098 | set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN))); | |
5099 | goto failure; | |
5100 | } | |
5101 | if (vectype.type != NT_d || vectype.index != 1) | |
5102 | { | |
5103 | set_fatal_syntax_error | |
5104 | (_("the top half of a 128-bit FP/SIMD register is expected")); | |
5105 | goto failure; | |
5106 | } | |
5107 | info->reg.regno = val; | |
5108 | /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register | |
5109 | here; it is correct for the purpose of encoding/decoding since | |
5110 | only the register number is explicitly encoded in the related | |
5111 | instructions, although this appears a bit hacky. */ | |
5112 | info->qualifier = AARCH64_OPND_QLF_S_D; | |
5113 | break; | |
5114 | ||
5115 | case AARCH64_OPND_Ed: | |
5116 | case AARCH64_OPND_En: | |
5117 | case AARCH64_OPND_Em: | |
5118 | val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype); | |
5119 | if (val == PARSE_FAIL) | |
5120 | { | |
5121 | first_error (_(get_reg_expected_msg (REG_TYPE_VN))); | |
5122 | goto failure; | |
5123 | } | |
5124 | if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX)) | |
5125 | goto failure; | |
5126 | ||
5127 | info->reglane.regno = val; | |
5128 | info->reglane.index = vectype.index; | |
5129 | info->qualifier = vectype_to_qualifier (&vectype); | |
5130 | if (info->qualifier == AARCH64_OPND_QLF_NIL) | |
5131 | goto failure; | |
5132 | break; | |
5133 | ||
5134 | case AARCH64_OPND_LVn: | |
5135 | case AARCH64_OPND_LVt: | |
5136 | case AARCH64_OPND_LVt_AL: | |
5137 | case AARCH64_OPND_LEt: | |
5138 | if ((val = parse_neon_reg_list (&str, &vectype)) == PARSE_FAIL) | |
5139 | goto failure; | |
5140 | if (! reg_list_valid_p (val, /* accept_alternate */ 0)) | |
5141 | { | |
5142 | set_fatal_syntax_error (_("invalid register list")); | |
5143 | goto failure; | |
5144 | } | |
5145 | info->reglist.first_regno = (val >> 2) & 0x1f; | |
5146 | info->reglist.num_regs = (val & 0x3) + 1; | |
5147 | if (operands[i] == AARCH64_OPND_LEt) | |
5148 | { | |
5149 | if (!(vectype.defined & NTA_HASINDEX)) | |
5150 | goto failure; | |
5151 | info->reglist.has_index = 1; | |
5152 | info->reglist.index = vectype.index; | |
5153 | } | |
5154 | else if (!(vectype.defined & NTA_HASTYPE)) | |
5155 | goto failure; | |
5156 | info->qualifier = vectype_to_qualifier (&vectype); | |
5157 | if (info->qualifier == AARCH64_OPND_QLF_NIL) | |
5158 | goto failure; | |
5159 | break; | |
5160 | ||
5161 | case AARCH64_OPND_Cn: | |
5162 | case AARCH64_OPND_Cm: | |
5163 | po_reg_or_fail (REG_TYPE_CN); | |
5164 | if (val > 15) | |
5165 | { | |
5166 | set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN))); | |
5167 | goto failure; | |
5168 | } | |
5169 | inst.base.operands[i].reg.regno = val; | |
5170 | break; | |
5171 | ||
5172 | case AARCH64_OPND_SHLL_IMM: | |
5173 | case AARCH64_OPND_IMM_VLSR: | |
5174 | po_imm_or_fail (1, 64); | |
5175 | info->imm.value = val; | |
5176 | break; | |
5177 | ||
5178 | case AARCH64_OPND_CCMP_IMM: | |
5179 | case AARCH64_OPND_FBITS: | |
5180 | case AARCH64_OPND_UIMM4: | |
5181 | case AARCH64_OPND_UIMM3_OP1: | |
5182 | case AARCH64_OPND_UIMM3_OP2: | |
5183 | case AARCH64_OPND_IMM_VLSL: | |
5184 | case AARCH64_OPND_IMM: | |
5185 | case AARCH64_OPND_WIDTH: | |
5186 | po_imm_nc_or_fail (); | |
5187 | info->imm.value = val; | |
5188 | break; | |
5189 | ||
5190 | case AARCH64_OPND_UIMM7: | |
5191 | po_imm_or_fail (0, 127); | |
5192 | info->imm.value = val; | |
5193 | break; | |
5194 | ||
5195 | case AARCH64_OPND_IDX: | |
5196 | case AARCH64_OPND_BIT_NUM: | |
5197 | case AARCH64_OPND_IMMR: | |
5198 | case AARCH64_OPND_IMMS: | |
5199 | po_imm_or_fail (0, 63); | |
5200 | info->imm.value = val; | |
5201 | break; | |
5202 | ||
5203 | case AARCH64_OPND_IMM0: | |
5204 | po_imm_nc_or_fail (); | |
5205 | if (val != 0) | |
5206 | { | |
5207 | set_fatal_syntax_error (_("immediate zero expected")); | |
5208 | goto failure; | |
5209 | } | |
5210 | info->imm.value = 0; | |
5211 | break; | |
5212 | ||
5213 | case AARCH64_OPND_FPIMM0: | |
5214 | { | |
5215 | int qfloat; | |
5216 | bfd_boolean res1 = FALSE, res2 = FALSE; | |
5217 | /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected, | |
5218 | it is probably not worth the effort to support it. */ | |
62b0d0d5 | 5219 | if (!(res1 = parse_aarch64_imm_float (&str, &qfloat, FALSE)) |
a06ea964 NC |
5220 | && !(res2 = parse_constant_immediate (&str, &val))) |
5221 | goto failure; | |
5222 | if ((res1 && qfloat == 0) || (res2 && val == 0)) | |
5223 | { | |
5224 | info->imm.value = 0; | |
5225 | info->imm.is_fp = 1; | |
5226 | break; | |
5227 | } | |
5228 | set_fatal_syntax_error (_("immediate zero expected")); | |
5229 | goto failure; | |
5230 | } | |
5231 | ||
5232 | case AARCH64_OPND_IMM_MOV: | |
5233 | { | |
5234 | char *saved = str; | |
8db49cc2 WN |
5235 | if (reg_name_p (str, REG_TYPE_R_Z_SP) || |
5236 | reg_name_p (str, REG_TYPE_VN)) | |
a06ea964 NC |
5237 | goto failure; |
5238 | str = saved; | |
5239 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
5240 | GE_OPT_PREFIX, 1)); | |
5241 | /* The MOV immediate alias will be fixed up by fix_mov_imm_insn | |
5242 | later. fix_mov_imm_insn will try to determine a machine | |
5243 | instruction (MOVZ, MOVN or ORR) for it and will issue an error | |
5244 | message if the immediate cannot be moved by a single | |
5245 | instruction. */ | |
5246 | aarch64_set_gas_internal_fixup (&inst.reloc, info, 1); | |
5247 | inst.base.operands[i].skip = 1; | |
5248 | } | |
5249 | break; | |
5250 | ||
5251 | case AARCH64_OPND_SIMD_IMM: | |
5252 | case AARCH64_OPND_SIMD_IMM_SFT: | |
5253 | if (! parse_big_immediate (&str, &val)) | |
5254 | goto failure; | |
5255 | assign_imm_if_const_or_fixup_later (&inst.reloc, info, | |
5256 | /* addr_off_p */ 0, | |
5257 | /* need_libopcodes_p */ 1, | |
5258 | /* skip_p */ 1); | |
5259 | /* Parse shift. | |
5260 | N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any | |
5261 | shift, we don't check it here; we leave the checking to | |
5262 | the libopcodes (operand_general_constraint_met_p). By | |
5263 | doing this, we achieve better diagnostics. */ | |
5264 | if (skip_past_comma (&str) | |
5265 | && ! parse_shift (&str, info, SHIFTED_LSL_MSL)) | |
5266 | goto failure; | |
5267 | if (!info->shifter.operator_present | |
5268 | && info->type == AARCH64_OPND_SIMD_IMM_SFT) | |
5269 | { | |
5270 | /* Default to LSL if not present. Libopcodes prefers shifter | |
5271 | kind to be explicit. */ | |
5272 | gas_assert (info->shifter.kind == AARCH64_MOD_NONE); | |
5273 | info->shifter.kind = AARCH64_MOD_LSL; | |
5274 | } | |
5275 | break; | |
5276 | ||
5277 | case AARCH64_OPND_FPIMM: | |
5278 | case AARCH64_OPND_SIMD_FPIMM: | |
5279 | { | |
5280 | int qfloat; | |
62b0d0d5 YZ |
5281 | bfd_boolean dp_p |
5282 | = (aarch64_get_qualifier_esize (inst.base.operands[0].qualifier) | |
5283 | == 8); | |
5284 | if (! parse_aarch64_imm_float (&str, &qfloat, dp_p)) | |
a06ea964 NC |
5285 | goto failure; |
5286 | if (qfloat == 0) | |
5287 | { | |
5288 | set_fatal_syntax_error (_("invalid floating-point constant")); | |
5289 | goto failure; | |
5290 | } | |
5291 | inst.base.operands[i].imm.value = encode_imm_float_bits (qfloat); | |
5292 | inst.base.operands[i].imm.is_fp = 1; | |
5293 | } | |
5294 | break; | |
5295 | ||
5296 | case AARCH64_OPND_LIMM: | |
5297 | po_misc_or_fail (parse_shifter_operand (&str, info, | |
5298 | SHIFTED_LOGIC_IMM)); | |
5299 | if (info->shifter.operator_present) | |
5300 | { | |
5301 | set_fatal_syntax_error | |
5302 | (_("shift not allowed for bitmask immediate")); | |
5303 | goto failure; | |
5304 | } | |
5305 | assign_imm_if_const_or_fixup_later (&inst.reloc, info, | |
5306 | /* addr_off_p */ 0, | |
5307 | /* need_libopcodes_p */ 1, | |
5308 | /* skip_p */ 1); | |
5309 | break; | |
5310 | ||
5311 | case AARCH64_OPND_AIMM: | |
5312 | if (opcode->op == OP_ADD) | |
5313 | /* ADD may have relocation types. */ | |
5314 | po_misc_or_fail (parse_shifter_operand_reloc (&str, info, | |
5315 | SHIFTED_ARITH_IMM)); | |
5316 | else | |
5317 | po_misc_or_fail (parse_shifter_operand (&str, info, | |
5318 | SHIFTED_ARITH_IMM)); | |
5319 | switch (inst.reloc.type) | |
5320 | { | |
5321 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12: | |
5322 | info->shifter.amount = 12; | |
5323 | break; | |
5324 | case BFD_RELOC_UNUSED: | |
5325 | aarch64_set_gas_internal_fixup (&inst.reloc, info, 0); | |
5326 | if (info->shifter.kind != AARCH64_MOD_NONE) | |
5327 | inst.reloc.flags = FIXUP_F_HAS_EXPLICIT_SHIFT; | |
5328 | inst.reloc.pc_rel = 0; | |
5329 | break; | |
5330 | default: | |
5331 | break; | |
5332 | } | |
5333 | info->imm.value = 0; | |
5334 | if (!info->shifter.operator_present) | |
5335 | { | |
5336 | /* Default to LSL if not present. Libopcodes prefers shifter | |
5337 | kind to be explicit. */ | |
5338 | gas_assert (info->shifter.kind == AARCH64_MOD_NONE); | |
5339 | info->shifter.kind = AARCH64_MOD_LSL; | |
5340 | } | |
5341 | break; | |
5342 | ||
5343 | case AARCH64_OPND_HALF: | |
5344 | { | |
5345 | /* #<imm16> or relocation. */ | |
5346 | int internal_fixup_p; | |
5347 | po_misc_or_fail (parse_half (&str, &internal_fixup_p)); | |
5348 | if (internal_fixup_p) | |
5349 | aarch64_set_gas_internal_fixup (&inst.reloc, info, 0); | |
5350 | skip_whitespace (str); | |
5351 | if (skip_past_comma (&str)) | |
5352 | { | |
5353 | /* {, LSL #<shift>} */ | |
5354 | if (! aarch64_gas_internal_fixup_p ()) | |
5355 | { | |
5356 | set_fatal_syntax_error (_("can't mix relocation modifier " | |
5357 | "with explicit shift")); | |
5358 | goto failure; | |
5359 | } | |
5360 | po_misc_or_fail (parse_shift (&str, info, SHIFTED_LSL)); | |
5361 | } | |
5362 | else | |
5363 | inst.base.operands[i].shifter.amount = 0; | |
5364 | inst.base.operands[i].shifter.kind = AARCH64_MOD_LSL; | |
5365 | inst.base.operands[i].imm.value = 0; | |
5366 | if (! process_movw_reloc_info ()) | |
5367 | goto failure; | |
5368 | } | |
5369 | break; | |
5370 | ||
5371 | case AARCH64_OPND_EXCEPTION: | |
5372 | po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp)); | |
5373 | assign_imm_if_const_or_fixup_later (&inst.reloc, info, | |
5374 | /* addr_off_p */ 0, | |
5375 | /* need_libopcodes_p */ 0, | |
5376 | /* skip_p */ 1); | |
5377 | break; | |
5378 | ||
5379 | case AARCH64_OPND_NZCV: | |
5380 | { | |
5381 | const asm_nzcv *nzcv = hash_find_n (aarch64_nzcv_hsh, str, 4); | |
5382 | if (nzcv != NULL) | |
5383 | { | |
5384 | str += 4; | |
5385 | info->imm.value = nzcv->value; | |
5386 | break; | |
5387 | } | |
5388 | po_imm_or_fail (0, 15); | |
5389 | info->imm.value = val; | |
5390 | } | |
5391 | break; | |
5392 | ||
5393 | case AARCH64_OPND_COND: | |
68a64283 | 5394 | case AARCH64_OPND_COND1: |
a06ea964 NC |
5395 | info->cond = hash_find_n (aarch64_cond_hsh, str, 2); |
5396 | str += 2; | |
5397 | if (info->cond == NULL) | |
5398 | { | |
5399 | set_syntax_error (_("invalid condition")); | |
5400 | goto failure; | |
5401 | } | |
68a64283 YZ |
5402 | else if (operands[i] == AARCH64_OPND_COND1 |
5403 | && (info->cond->value & 0xe) == 0xe) | |
5404 | { | |
5405 | /* Not allow AL or NV. */ | |
5406 | set_default_error (); | |
5407 | goto failure; | |
5408 | } | |
a06ea964 NC |
5409 | break; |
5410 | ||
5411 | case AARCH64_OPND_ADDR_ADRP: | |
5412 | po_misc_or_fail (parse_adrp (&str)); | |
5413 | /* Clear the value as operand needs to be relocated. */ | |
5414 | info->imm.value = 0; | |
5415 | break; | |
5416 | ||
5417 | case AARCH64_OPND_ADDR_PCREL14: | |
5418 | case AARCH64_OPND_ADDR_PCREL19: | |
5419 | case AARCH64_OPND_ADDR_PCREL21: | |
5420 | case AARCH64_OPND_ADDR_PCREL26: | |
5421 | po_misc_or_fail (parse_address_reloc (&str, info)); | |
5422 | if (!info->addr.pcrel) | |
5423 | { | |
5424 | set_syntax_error (_("invalid pc-relative address")); | |
5425 | goto failure; | |
5426 | } | |
5427 | if (inst.gen_lit_pool | |
5428 | && (opcode->iclass != loadlit || opcode->op == OP_PRFM_LIT)) | |
5429 | { | |
5430 | /* Only permit "=value" in the literal load instructions. | |
5431 | The literal will be generated by programmer_friendly_fixup. */ | |
5432 | set_syntax_error (_("invalid use of \"=immediate\"")); | |
5433 | goto failure; | |
5434 | } | |
5435 | if (inst.reloc.exp.X_op == O_symbol && find_reloc_table_entry (&str)) | |
5436 | { | |
5437 | set_syntax_error (_("unrecognized relocation suffix")); | |
5438 | goto failure; | |
5439 | } | |
5440 | if (inst.reloc.exp.X_op == O_constant && !inst.gen_lit_pool) | |
5441 | { | |
5442 | info->imm.value = inst.reloc.exp.X_add_number; | |
5443 | inst.reloc.type = BFD_RELOC_UNUSED; | |
5444 | } | |
5445 | else | |
5446 | { | |
5447 | info->imm.value = 0; | |
f41aef5f RE |
5448 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
5449 | switch (opcode->iclass) | |
5450 | { | |
5451 | case compbranch: | |
5452 | case condbranch: | |
5453 | /* e.g. CBZ or B.COND */ | |
5454 | gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19); | |
5455 | inst.reloc.type = BFD_RELOC_AARCH64_BRANCH19; | |
5456 | break; | |
5457 | case testbranch: | |
5458 | /* e.g. TBZ */ | |
5459 | gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL14); | |
5460 | inst.reloc.type = BFD_RELOC_AARCH64_TSTBR14; | |
5461 | break; | |
5462 | case branch_imm: | |
5463 | /* e.g. B or BL */ | |
5464 | gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL26); | |
5465 | inst.reloc.type = | |
5466 | (opcode->op == OP_BL) ? BFD_RELOC_AARCH64_CALL26 | |
5467 | : BFD_RELOC_AARCH64_JUMP26; | |
5468 | break; | |
5469 | case loadlit: | |
5470 | gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19); | |
5471 | inst.reloc.type = BFD_RELOC_AARCH64_LD_LO19_PCREL; | |
5472 | break; | |
5473 | case pcreladdr: | |
5474 | gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL21); | |
5475 | inst.reloc.type = BFD_RELOC_AARCH64_ADR_LO21_PCREL; | |
5476 | break; | |
5477 | default: | |
5478 | gas_assert (0); | |
5479 | abort (); | |
5480 | } | |
a06ea964 NC |
5481 | inst.reloc.pc_rel = 1; |
5482 | } | |
5483 | break; | |
5484 | ||
5485 | case AARCH64_OPND_ADDR_SIMPLE: | |
5486 | case AARCH64_OPND_SIMD_ADDR_SIMPLE: | |
5487 | /* [<Xn|SP>{, #<simm>}] */ | |
5488 | po_char_or_fail ('['); | |
5489 | po_reg_or_fail (REG_TYPE_R64_SP); | |
5490 | /* Accept optional ", #0". */ | |
5491 | if (operands[i] == AARCH64_OPND_ADDR_SIMPLE | |
5492 | && skip_past_char (&str, ',')) | |
5493 | { | |
5494 | skip_past_char (&str, '#'); | |
5495 | if (! skip_past_char (&str, '0')) | |
5496 | { | |
5497 | set_fatal_syntax_error | |
5498 | (_("the optional immediate offset can only be 0")); | |
5499 | goto failure; | |
5500 | } | |
5501 | } | |
5502 | po_char_or_fail (']'); | |
5503 | info->addr.base_regno = val; | |
5504 | break; | |
5505 | ||
5506 | case AARCH64_OPND_ADDR_REGOFF: | |
5507 | /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */ | |
5508 | po_misc_or_fail (parse_address (&str, info, 0)); | |
5509 | if (info->addr.pcrel || !info->addr.offset.is_reg | |
5510 | || !info->addr.preind || info->addr.postind | |
5511 | || info->addr.writeback) | |
5512 | { | |
5513 | set_syntax_error (_("invalid addressing mode")); | |
5514 | goto failure; | |
5515 | } | |
5516 | if (!info->shifter.operator_present) | |
5517 | { | |
5518 | /* Default to LSL if not present. Libopcodes prefers shifter | |
5519 | kind to be explicit. */ | |
5520 | gas_assert (info->shifter.kind == AARCH64_MOD_NONE); | |
5521 | info->shifter.kind = AARCH64_MOD_LSL; | |
5522 | } | |
5523 | /* Qualifier to be deduced by libopcodes. */ | |
5524 | break; | |
5525 | ||
5526 | case AARCH64_OPND_ADDR_SIMM7: | |
5527 | po_misc_or_fail (parse_address (&str, info, 0)); | |
5528 | if (info->addr.pcrel || info->addr.offset.is_reg | |
5529 | || (!info->addr.preind && !info->addr.postind)) | |
5530 | { | |
5531 | set_syntax_error (_("invalid addressing mode")); | |
5532 | goto failure; | |
5533 | } | |
5534 | assign_imm_if_const_or_fixup_later (&inst.reloc, info, | |
5535 | /* addr_off_p */ 1, | |
5536 | /* need_libopcodes_p */ 1, | |
5537 | /* skip_p */ 0); | |
5538 | break; | |
5539 | ||
5540 | case AARCH64_OPND_ADDR_SIMM9: | |
5541 | case AARCH64_OPND_ADDR_SIMM9_2: | |
5542 | po_misc_or_fail (parse_address_reloc (&str, info)); | |
5543 | if (info->addr.pcrel || info->addr.offset.is_reg | |
5544 | || (!info->addr.preind && !info->addr.postind) | |
5545 | || (operands[i] == AARCH64_OPND_ADDR_SIMM9_2 | |
5546 | && info->addr.writeback)) | |
5547 | { | |
5548 | set_syntax_error (_("invalid addressing mode")); | |
5549 | goto failure; | |
5550 | } | |
5551 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
5552 | { | |
5553 | set_syntax_error (_("relocation not allowed")); | |
5554 | goto failure; | |
5555 | } | |
5556 | assign_imm_if_const_or_fixup_later (&inst.reloc, info, | |
5557 | /* addr_off_p */ 1, | |
5558 | /* need_libopcodes_p */ 1, | |
5559 | /* skip_p */ 0); | |
5560 | break; | |
5561 | ||
5562 | case AARCH64_OPND_ADDR_UIMM12: | |
5563 | po_misc_or_fail (parse_address_reloc (&str, info)); | |
5564 | if (info->addr.pcrel || info->addr.offset.is_reg | |
5565 | || !info->addr.preind || info->addr.writeback) | |
5566 | { | |
5567 | set_syntax_error (_("invalid addressing mode")); | |
5568 | goto failure; | |
5569 | } | |
5570 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
5571 | aarch64_set_gas_internal_fixup (&inst.reloc, info, 1); | |
4c562523 JW |
5572 | else if (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12 |
5573 | || (inst.reloc.type | |
5574 | == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12) | |
5575 | || (inst.reloc.type | |
5576 | == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC)) | |
a06ea964 NC |
5577 | inst.reloc.type = ldst_lo12_determine_real_reloc_type (); |
5578 | /* Leave qualifier to be determined by libopcodes. */ | |
5579 | break; | |
5580 | ||
5581 | case AARCH64_OPND_SIMD_ADDR_POST: | |
5582 | /* [<Xn|SP>], <Xm|#<amount>> */ | |
5583 | po_misc_or_fail (parse_address (&str, info, 1)); | |
5584 | if (!info->addr.postind || !info->addr.writeback) | |
5585 | { | |
5586 | set_syntax_error (_("invalid addressing mode")); | |
5587 | goto failure; | |
5588 | } | |
5589 | if (!info->addr.offset.is_reg) | |
5590 | { | |
5591 | if (inst.reloc.exp.X_op == O_constant) | |
5592 | info->addr.offset.imm = inst.reloc.exp.X_add_number; | |
5593 | else | |
5594 | { | |
5595 | set_fatal_syntax_error | |
5596 | (_("writeback value should be an immediate constant")); | |
5597 | goto failure; | |
5598 | } | |
5599 | } | |
5600 | /* No qualifier. */ | |
5601 | break; | |
5602 | ||
5603 | case AARCH64_OPND_SYSREG: | |
72ca8fad | 5604 | if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1, 0)) |
a203d9b7 | 5605 | == PARSE_FAIL) |
a06ea964 | 5606 | { |
a203d9b7 YZ |
5607 | set_syntax_error (_("unknown or missing system register name")); |
5608 | goto failure; | |
a06ea964 | 5609 | } |
a203d9b7 | 5610 | inst.base.operands[i].sysreg = val; |
a06ea964 NC |
5611 | break; |
5612 | ||
5613 | case AARCH64_OPND_PSTATEFIELD: | |
72ca8fad | 5614 | if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1)) |
a3251895 | 5615 | == PARSE_FAIL) |
a06ea964 NC |
5616 | { |
5617 | set_syntax_error (_("unknown or missing PSTATE field name")); | |
5618 | goto failure; | |
5619 | } | |
5620 | inst.base.operands[i].pstatefield = val; | |
5621 | break; | |
5622 | ||
5623 | case AARCH64_OPND_SYSREG_IC: | |
5624 | inst.base.operands[i].sysins_op = | |
5625 | parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh); | |
5626 | goto sys_reg_ins; | |
5627 | case AARCH64_OPND_SYSREG_DC: | |
5628 | inst.base.operands[i].sysins_op = | |
5629 | parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh); | |
5630 | goto sys_reg_ins; | |
5631 | case AARCH64_OPND_SYSREG_AT: | |
5632 | inst.base.operands[i].sysins_op = | |
5633 | parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh); | |
5634 | goto sys_reg_ins; | |
5635 | case AARCH64_OPND_SYSREG_TLBI: | |
5636 | inst.base.operands[i].sysins_op = | |
5637 | parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh); | |
5638 | sys_reg_ins: | |
5639 | if (inst.base.operands[i].sysins_op == NULL) | |
5640 | { | |
5641 | set_fatal_syntax_error ( _("unknown or missing operation name")); | |
5642 | goto failure; | |
5643 | } | |
5644 | break; | |
5645 | ||
5646 | case AARCH64_OPND_BARRIER: | |
5647 | case AARCH64_OPND_BARRIER_ISB: | |
5648 | val = parse_barrier (&str); | |
5649 | if (val != PARSE_FAIL | |
5650 | && operands[i] == AARCH64_OPND_BARRIER_ISB && val != 0xf) | |
5651 | { | |
5652 | /* ISB only accepts options name 'sy'. */ | |
5653 | set_syntax_error | |
5654 | (_("the specified option is not accepted in ISB")); | |
5655 | /* Turn off backtrack as this optional operand is present. */ | |
5656 | backtrack_pos = 0; | |
5657 | goto failure; | |
5658 | } | |
5659 | /* This is an extension to accept a 0..15 immediate. */ | |
5660 | if (val == PARSE_FAIL) | |
5661 | po_imm_or_fail (0, 15); | |
5662 | info->barrier = aarch64_barrier_options + val; | |
5663 | break; | |
5664 | ||
5665 | case AARCH64_OPND_PRFOP: | |
5666 | val = parse_pldop (&str); | |
5667 | /* This is an extension to accept a 0..31 immediate. */ | |
5668 | if (val == PARSE_FAIL) | |
5669 | po_imm_or_fail (0, 31); | |
5670 | inst.base.operands[i].prfop = aarch64_prfops + val; | |
5671 | break; | |
5672 | ||
1e6f4800 MW |
5673 | case AARCH64_OPND_BARRIER_PSB: |
5674 | val = parse_barrier_psb (&str, &(info->hint_option)); | |
5675 | if (val == PARSE_FAIL) | |
5676 | goto failure; | |
5677 | break; | |
5678 | ||
a06ea964 NC |
5679 | default: |
5680 | as_fatal (_("unhandled operand code %d"), operands[i]); | |
5681 | } | |
5682 | ||
5683 | /* If we get here, this operand was successfully parsed. */ | |
5684 | inst.base.operands[i].present = 1; | |
5685 | continue; | |
5686 | ||
5687 | failure: | |
5688 | /* The parse routine should already have set the error, but in case | |
5689 | not, set a default one here. */ | |
5690 | if (! error_p ()) | |
5691 | set_default_error (); | |
5692 | ||
5693 | if (! backtrack_pos) | |
5694 | goto parse_operands_return; | |
5695 | ||
f4c51f60 JW |
5696 | { |
5697 | /* We reach here because this operand is marked as optional, and | |
5698 | either no operand was supplied or the operand was supplied but it | |
5699 | was syntactically incorrect. In the latter case we report an | |
5700 | error. In the former case we perform a few more checks before | |
5701 | dropping through to the code to insert the default operand. */ | |
5702 | ||
5703 | char *tmp = backtrack_pos; | |
5704 | char endchar = END_OF_INSN; | |
5705 | ||
5706 | if (i != (aarch64_num_of_operands (opcode) - 1)) | |
5707 | endchar = ','; | |
5708 | skip_past_char (&tmp, ','); | |
5709 | ||
5710 | if (*tmp != endchar) | |
5711 | /* The user has supplied an operand in the wrong format. */ | |
5712 | goto parse_operands_return; | |
5713 | ||
5714 | /* Make sure there is not a comma before the optional operand. | |
5715 | For example the fifth operand of 'sys' is optional: | |
5716 | ||
5717 | sys #0,c0,c0,#0, <--- wrong | |
5718 | sys #0,c0,c0,#0 <--- correct. */ | |
5719 | if (comma_skipped_p && i && endchar == END_OF_INSN) | |
5720 | { | |
5721 | set_fatal_syntax_error | |
5722 | (_("unexpected comma before the omitted optional operand")); | |
5723 | goto parse_operands_return; | |
5724 | } | |
5725 | } | |
5726 | ||
a06ea964 NC |
5727 | /* Reaching here means we are dealing with an optional operand that is |
5728 | omitted from the assembly line. */ | |
5729 | gas_assert (optional_operand_p (opcode, i)); | |
5730 | info->present = 0; | |
5731 | process_omitted_operand (operands[i], opcode, i, info); | |
5732 | ||
5733 | /* Try again, skipping the optional operand at backtrack_pos. */ | |
5734 | str = backtrack_pos; | |
5735 | backtrack_pos = 0; | |
5736 | ||
a06ea964 NC |
5737 | /* Clear any error record after the omitted optional operand has been |
5738 | successfully handled. */ | |
5739 | clear_error (); | |
5740 | } | |
5741 | ||
5742 | /* Check if we have parsed all the operands. */ | |
5743 | if (*str != '\0' && ! error_p ()) | |
5744 | { | |
5745 | /* Set I to the index of the last present operand; this is | |
5746 | for the purpose of diagnostics. */ | |
5747 | for (i -= 1; i >= 0 && !inst.base.operands[i].present; --i) | |
5748 | ; | |
5749 | set_fatal_syntax_error | |
5750 | (_("unexpected characters following instruction")); | |
5751 | } | |
5752 | ||
5753 | parse_operands_return: | |
5754 | ||
5755 | if (error_p ()) | |
5756 | { | |
5757 | DEBUG_TRACE ("parsing FAIL: %s - %s", | |
5758 | operand_mismatch_kind_names[get_error_kind ()], | |
5759 | get_error_message ()); | |
5760 | /* Record the operand error properly; this is useful when there | |
5761 | are multiple instruction templates for a mnemonic name, so that | |
5762 | later on, we can select the error that most closely describes | |
5763 | the problem. */ | |
5764 | record_operand_error (opcode, i, get_error_kind (), | |
5765 | get_error_message ()); | |
5766 | return FALSE; | |
5767 | } | |
5768 | else | |
5769 | { | |
5770 | DEBUG_TRACE ("parsing SUCCESS"); | |
5771 | return TRUE; | |
5772 | } | |
5773 | } | |
5774 | ||
5775 | /* It does some fix-up to provide some programmer friendly feature while | |
5776 | keeping the libopcodes happy, i.e. libopcodes only accepts | |
5777 | the preferred architectural syntax. | |
5778 | Return FALSE if there is any failure; otherwise return TRUE. */ | |
5779 | ||
5780 | static bfd_boolean | |
5781 | programmer_friendly_fixup (aarch64_instruction *instr) | |
5782 | { | |
5783 | aarch64_inst *base = &instr->base; | |
5784 | const aarch64_opcode *opcode = base->opcode; | |
5785 | enum aarch64_op op = opcode->op; | |
5786 | aarch64_opnd_info *operands = base->operands; | |
5787 | ||
5788 | DEBUG_TRACE ("enter"); | |
5789 | ||
5790 | switch (opcode->iclass) | |
5791 | { | |
5792 | case testbranch: | |
5793 | /* TBNZ Xn|Wn, #uimm6, label | |
5794 | Test and Branch Not Zero: conditionally jumps to label if bit number | |
5795 | uimm6 in register Xn is not zero. The bit number implies the width of | |
5796 | the register, which may be written and should be disassembled as Wn if | |
5797 | uimm is less than 32. */ | |
5798 | if (operands[0].qualifier == AARCH64_OPND_QLF_W) | |
5799 | { | |
5800 | if (operands[1].imm.value >= 32) | |
5801 | { | |
5802 | record_operand_out_of_range_error (opcode, 1, _("immediate value"), | |
5803 | 0, 31); | |
5804 | return FALSE; | |
5805 | } | |
5806 | operands[0].qualifier = AARCH64_OPND_QLF_X; | |
5807 | } | |
5808 | break; | |
5809 | case loadlit: | |
5810 | /* LDR Wt, label | =value | |
5811 | As a convenience assemblers will typically permit the notation | |
5812 | "=value" in conjunction with the pc-relative literal load instructions | |
5813 | to automatically place an immediate value or symbolic address in a | |
5814 | nearby literal pool and generate a hidden label which references it. | |
5815 | ISREG has been set to 0 in the case of =value. */ | |
5816 | if (instr->gen_lit_pool | |
5817 | && (op == OP_LDR_LIT || op == OP_LDRV_LIT || op == OP_LDRSW_LIT)) | |
5818 | { | |
5819 | int size = aarch64_get_qualifier_esize (operands[0].qualifier); | |
5820 | if (op == OP_LDRSW_LIT) | |
5821 | size = 4; | |
5822 | if (instr->reloc.exp.X_op != O_constant | |
67a32447 | 5823 | && instr->reloc.exp.X_op != O_big |
a06ea964 NC |
5824 | && instr->reloc.exp.X_op != O_symbol) |
5825 | { | |
5826 | record_operand_error (opcode, 1, | |
5827 | AARCH64_OPDE_FATAL_SYNTAX_ERROR, | |
5828 | _("constant expression expected")); | |
5829 | return FALSE; | |
5830 | } | |
5831 | if (! add_to_lit_pool (&instr->reloc.exp, size)) | |
5832 | { | |
5833 | record_operand_error (opcode, 1, | |
5834 | AARCH64_OPDE_OTHER_ERROR, | |
5835 | _("literal pool insertion failed")); | |
5836 | return FALSE; | |
5837 | } | |
5838 | } | |
5839 | break; | |
a06ea964 NC |
5840 | case log_shift: |
5841 | case bitfield: | |
5842 | /* UXT[BHW] Wd, Wn | |
5843 | Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias | |
5844 | for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is | |
5845 | encoded using ORR Wd, WZR, Wn (MOV Wd,Wn). | |
5846 | A programmer-friendly assembler should accept a destination Xd in | |
5847 | place of Wd, however that is not the preferred form for disassembly. | |
5848 | */ | |
5849 | if ((op == OP_UXTB || op == OP_UXTH || op == OP_UXTW) | |
5850 | && operands[1].qualifier == AARCH64_OPND_QLF_W | |
5851 | && operands[0].qualifier == AARCH64_OPND_QLF_X) | |
5852 | operands[0].qualifier = AARCH64_OPND_QLF_W; | |
5853 | break; | |
5854 | ||
5855 | case addsub_ext: | |
5856 | { | |
5857 | /* In the 64-bit form, the final register operand is written as Wm | |
5858 | for all but the (possibly omitted) UXTX/LSL and SXTX | |
5859 | operators. | |
5860 | As a programmer-friendly assembler, we accept e.g. | |
5861 | ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to | |
5862 | ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */ | |
5863 | int idx = aarch64_operand_index (opcode->operands, | |
5864 | AARCH64_OPND_Rm_EXT); | |
5865 | gas_assert (idx == 1 || idx == 2); | |
5866 | if (operands[0].qualifier == AARCH64_OPND_QLF_X | |
5867 | && operands[idx].qualifier == AARCH64_OPND_QLF_X | |
5868 | && operands[idx].shifter.kind != AARCH64_MOD_LSL | |
5869 | && operands[idx].shifter.kind != AARCH64_MOD_UXTX | |
5870 | && operands[idx].shifter.kind != AARCH64_MOD_SXTX) | |
5871 | operands[idx].qualifier = AARCH64_OPND_QLF_W; | |
5872 | } | |
5873 | break; | |
5874 | ||
5875 | default: | |
5876 | break; | |
5877 | } | |
5878 | ||
5879 | DEBUG_TRACE ("exit with SUCCESS"); | |
5880 | return TRUE; | |
5881 | } | |
5882 | ||
5c47e525 | 5883 | /* Check for loads and stores that will cause unpredictable behavior. */ |
54a28c4c JW |
5884 | |
5885 | static void | |
5886 | warn_unpredictable_ldst (aarch64_instruction *instr, char *str) | |
5887 | { | |
5888 | aarch64_inst *base = &instr->base; | |
5889 | const aarch64_opcode *opcode = base->opcode; | |
5890 | const aarch64_opnd_info *opnds = base->operands; | |
5891 | switch (opcode->iclass) | |
5892 | { | |
5893 | case ldst_pos: | |
5894 | case ldst_imm9: | |
5895 | case ldst_unscaled: | |
5896 | case ldst_unpriv: | |
5c47e525 RE |
5897 | /* Loading/storing the base register is unpredictable if writeback. */ |
5898 | if ((aarch64_get_operand_class (opnds[0].type) | |
5899 | == AARCH64_OPND_CLASS_INT_REG) | |
5900 | && opnds[0].reg.regno == opnds[1].addr.base_regno | |
4bf8c6e8 | 5901 | && opnds[1].addr.base_regno != REG_SP |
54a28c4c | 5902 | && opnds[1].addr.writeback) |
5c47e525 | 5903 | as_warn (_("unpredictable transfer with writeback -- `%s'"), str); |
54a28c4c JW |
5904 | break; |
5905 | case ldstpair_off: | |
5906 | case ldstnapair_offs: | |
5907 | case ldstpair_indexed: | |
5c47e525 RE |
5908 | /* Loading/storing the base register is unpredictable if writeback. */ |
5909 | if ((aarch64_get_operand_class (opnds[0].type) | |
5910 | == AARCH64_OPND_CLASS_INT_REG) | |
5911 | && (opnds[0].reg.regno == opnds[2].addr.base_regno | |
5912 | || opnds[1].reg.regno == opnds[2].addr.base_regno) | |
4bf8c6e8 | 5913 | && opnds[2].addr.base_regno != REG_SP |
54a28c4c | 5914 | && opnds[2].addr.writeback) |
5c47e525 RE |
5915 | as_warn (_("unpredictable transfer with writeback -- `%s'"), str); |
5916 | /* Load operations must load different registers. */ | |
54a28c4c JW |
5917 | if ((opcode->opcode & (1 << 22)) |
5918 | && opnds[0].reg.regno == opnds[1].reg.regno) | |
5919 | as_warn (_("unpredictable load of register pair -- `%s'"), str); | |
5920 | break; | |
5921 | default: | |
5922 | break; | |
5923 | } | |
5924 | } | |
5925 | ||
a06ea964 NC |
5926 | /* A wrapper function to interface with libopcodes on encoding and |
5927 | record the error message if there is any. | |
5928 | ||
5929 | Return TRUE on success; otherwise return FALSE. */ | |
5930 | ||
5931 | static bfd_boolean | |
5932 | do_encode (const aarch64_opcode *opcode, aarch64_inst *instr, | |
5933 | aarch64_insn *code) | |
5934 | { | |
5935 | aarch64_operand_error error_info; | |
5936 | error_info.kind = AARCH64_OPDE_NIL; | |
5937 | if (aarch64_opcode_encode (opcode, instr, code, NULL, &error_info)) | |
5938 | return TRUE; | |
5939 | else | |
5940 | { | |
5941 | gas_assert (error_info.kind != AARCH64_OPDE_NIL); | |
5942 | record_operand_error_info (opcode, &error_info); | |
5943 | return FALSE; | |
5944 | } | |
5945 | } | |
5946 | ||
5947 | #ifdef DEBUG_AARCH64 | |
5948 | static inline void | |
5949 | dump_opcode_operands (const aarch64_opcode *opcode) | |
5950 | { | |
5951 | int i = 0; | |
5952 | while (opcode->operands[i] != AARCH64_OPND_NIL) | |
5953 | { | |
5954 | aarch64_verbose ("\t\t opnd%d: %s", i, | |
5955 | aarch64_get_operand_name (opcode->operands[i])[0] != '\0' | |
5956 | ? aarch64_get_operand_name (opcode->operands[i]) | |
5957 | : aarch64_get_operand_desc (opcode->operands[i])); | |
5958 | ++i; | |
5959 | } | |
5960 | } | |
5961 | #endif /* DEBUG_AARCH64 */ | |
5962 | ||
5963 | /* This is the guts of the machine-dependent assembler. STR points to a | |
5964 | machine dependent instruction. This function is supposed to emit | |
5965 | the frags/bytes it assembles to. */ | |
5966 | ||
5967 | void | |
5968 | md_assemble (char *str) | |
5969 | { | |
5970 | char *p = str; | |
5971 | templates *template; | |
5972 | aarch64_opcode *opcode; | |
5973 | aarch64_inst *inst_base; | |
5974 | unsigned saved_cond; | |
5975 | ||
5976 | /* Align the previous label if needed. */ | |
5977 | if (last_label_seen != NULL) | |
5978 | { | |
5979 | symbol_set_frag (last_label_seen, frag_now); | |
5980 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
5981 | S_SET_SEGMENT (last_label_seen, now_seg); | |
5982 | } | |
5983 | ||
5984 | inst.reloc.type = BFD_RELOC_UNUSED; | |
5985 | ||
5986 | DEBUG_TRACE ("\n\n"); | |
5987 | DEBUG_TRACE ("=============================="); | |
5988 | DEBUG_TRACE ("Enter md_assemble with %s", str); | |
5989 | ||
5990 | template = opcode_lookup (&p); | |
5991 | if (!template) | |
5992 | { | |
5993 | /* It wasn't an instruction, but it might be a register alias of | |
5994 | the form alias .req reg directive. */ | |
5995 | if (!create_register_alias (str, p)) | |
5996 | as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str), | |
5997 | str); | |
5998 | return; | |
5999 | } | |
6000 | ||
6001 | skip_whitespace (p); | |
6002 | if (*p == ',') | |
6003 | { | |
6004 | as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"), | |
6005 | get_mnemonic_name (str), str); | |
6006 | return; | |
6007 | } | |
6008 | ||
6009 | init_operand_error_report (); | |
6010 | ||
eb9d6cc9 RL |
6011 | /* Sections are assumed to start aligned. In executable section, there is no |
6012 | MAP_DATA symbol pending. So we only align the address during | |
6013 | MAP_DATA --> MAP_INSN transition. | |
6014 | For other sections, this is not guaranteed. */ | |
6015 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; | |
6016 | if (!need_pass_2 && subseg_text_p (now_seg) && mapstate == MAP_DATA) | |
6017 | frag_align_code (2, 0); | |
6018 | ||
a06ea964 NC |
6019 | saved_cond = inst.cond; |
6020 | reset_aarch64_instruction (&inst); | |
6021 | inst.cond = saved_cond; | |
6022 | ||
6023 | /* Iterate through all opcode entries with the same mnemonic name. */ | |
6024 | do | |
6025 | { | |
6026 | opcode = template->opcode; | |
6027 | ||
6028 | DEBUG_TRACE ("opcode %s found", opcode->name); | |
6029 | #ifdef DEBUG_AARCH64 | |
6030 | if (debug_dump) | |
6031 | dump_opcode_operands (opcode); | |
6032 | #endif /* DEBUG_AARCH64 */ | |
6033 | ||
a06ea964 NC |
6034 | mapping_state (MAP_INSN); |
6035 | ||
6036 | inst_base = &inst.base; | |
6037 | inst_base->opcode = opcode; | |
6038 | ||
6039 | /* Truly conditionally executed instructions, e.g. b.cond. */ | |
6040 | if (opcode->flags & F_COND) | |
6041 | { | |
6042 | gas_assert (inst.cond != COND_ALWAYS); | |
6043 | inst_base->cond = get_cond_from_value (inst.cond); | |
6044 | DEBUG_TRACE ("condition found %s", inst_base->cond->names[0]); | |
6045 | } | |
6046 | else if (inst.cond != COND_ALWAYS) | |
6047 | { | |
6048 | /* It shouldn't arrive here, where the assembly looks like a | |
6049 | conditional instruction but the found opcode is unconditional. */ | |
6050 | gas_assert (0); | |
6051 | continue; | |
6052 | } | |
6053 | ||
6054 | if (parse_operands (p, opcode) | |
6055 | && programmer_friendly_fixup (&inst) | |
6056 | && do_encode (inst_base->opcode, &inst.base, &inst_base->value)) | |
6057 | { | |
3f06bfce YZ |
6058 | /* Check that this instruction is supported for this CPU. */ |
6059 | if (!opcode->avariant | |
93d8990c | 6060 | || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, *opcode->avariant)) |
3f06bfce YZ |
6061 | { |
6062 | as_bad (_("selected processor does not support `%s'"), str); | |
6063 | return; | |
6064 | } | |
6065 | ||
54a28c4c JW |
6066 | warn_unpredictable_ldst (&inst, str); |
6067 | ||
a06ea964 NC |
6068 | if (inst.reloc.type == BFD_RELOC_UNUSED |
6069 | || !inst.reloc.need_libopcodes_p) | |
6070 | output_inst (NULL); | |
6071 | else | |
6072 | { | |
6073 | /* If there is relocation generated for the instruction, | |
6074 | store the instruction information for the future fix-up. */ | |
6075 | struct aarch64_inst *copy; | |
6076 | gas_assert (inst.reloc.type != BFD_RELOC_UNUSED); | |
325801bd | 6077 | copy = XNEW (struct aarch64_inst); |
a06ea964 NC |
6078 | memcpy (copy, &inst.base, sizeof (struct aarch64_inst)); |
6079 | output_inst (copy); | |
6080 | } | |
6081 | return; | |
6082 | } | |
6083 | ||
6084 | template = template->next; | |
6085 | if (template != NULL) | |
6086 | { | |
6087 | reset_aarch64_instruction (&inst); | |
6088 | inst.cond = saved_cond; | |
6089 | } | |
6090 | } | |
6091 | while (template != NULL); | |
6092 | ||
6093 | /* Issue the error messages if any. */ | |
6094 | output_operand_error_report (str); | |
6095 | } | |
6096 | ||
6097 | /* Various frobbings of labels and their addresses. */ | |
6098 | ||
6099 | void | |
6100 | aarch64_start_line_hook (void) | |
6101 | { | |
6102 | last_label_seen = NULL; | |
6103 | } | |
6104 | ||
6105 | void | |
6106 | aarch64_frob_label (symbolS * sym) | |
6107 | { | |
6108 | last_label_seen = sym; | |
6109 | ||
6110 | dwarf2_emit_label (sym); | |
6111 | } | |
6112 | ||
6113 | int | |
6114 | aarch64_data_in_code (void) | |
6115 | { | |
6116 | if (!strncmp (input_line_pointer + 1, "data:", 5)) | |
6117 | { | |
6118 | *input_line_pointer = '/'; | |
6119 | input_line_pointer += 5; | |
6120 | *input_line_pointer = 0; | |
6121 | return 1; | |
6122 | } | |
6123 | ||
6124 | return 0; | |
6125 | } | |
6126 | ||
6127 | char * | |
6128 | aarch64_canonicalize_symbol_name (char *name) | |
6129 | { | |
6130 | int len; | |
6131 | ||
6132 | if ((len = strlen (name)) > 5 && streq (name + len - 5, "/data")) | |
6133 | *(name + len - 5) = 0; | |
6134 | ||
6135 | return name; | |
6136 | } | |
6137 | \f | |
6138 | /* Table of all register names defined by default. The user can | |
6139 | define additional names with .req. Note that all register names | |
6140 | should appear in both upper and lowercase variants. Some registers | |
6141 | also have mixed-case names. */ | |
6142 | ||
6143 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE } | |
6144 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) | |
6145 | #define REGSET31(p,t) \ | |
6146 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
6147 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
6148 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
6149 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \ | |
6150 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ | |
6151 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ | |
6152 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ | |
6153 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t) | |
6154 | #define REGSET(p,t) \ | |
6155 | REGSET31(p,t), REGNUM(p,31,t) | |
6156 | ||
6157 | /* These go into aarch64_reg_hsh hash-table. */ | |
6158 | static const reg_entry reg_names[] = { | |
6159 | /* Integer registers. */ | |
6160 | REGSET31 (x, R_64), REGSET31 (X, R_64), | |
6161 | REGSET31 (w, R_32), REGSET31 (W, R_32), | |
6162 | ||
6163 | REGDEF (wsp, 31, SP_32), REGDEF (WSP, 31, SP_32), | |
6164 | REGDEF (sp, 31, SP_64), REGDEF (SP, 31, SP_64), | |
6165 | ||
6166 | REGDEF (wzr, 31, Z_32), REGDEF (WZR, 31, Z_32), | |
6167 | REGDEF (xzr, 31, Z_64), REGDEF (XZR, 31, Z_64), | |
6168 | ||
6169 | /* Coprocessor register numbers. */ | |
6170 | REGSET (c, CN), REGSET (C, CN), | |
6171 | ||
6172 | /* Floating-point single precision registers. */ | |
6173 | REGSET (s, FP_S), REGSET (S, FP_S), | |
6174 | ||
6175 | /* Floating-point double precision registers. */ | |
6176 | REGSET (d, FP_D), REGSET (D, FP_D), | |
6177 | ||
6178 | /* Floating-point half precision registers. */ | |
6179 | REGSET (h, FP_H), REGSET (H, FP_H), | |
6180 | ||
6181 | /* Floating-point byte precision registers. */ | |
6182 | REGSET (b, FP_B), REGSET (B, FP_B), | |
6183 | ||
6184 | /* Floating-point quad precision registers. */ | |
6185 | REGSET (q, FP_Q), REGSET (Q, FP_Q), | |
6186 | ||
6187 | /* FP/SIMD registers. */ | |
6188 | REGSET (v, VN), REGSET (V, VN), | |
6189 | }; | |
6190 | ||
6191 | #undef REGDEF | |
6192 | #undef REGNUM | |
6193 | #undef REGSET | |
6194 | ||
6195 | #define N 1 | |
6196 | #define n 0 | |
6197 | #define Z 1 | |
6198 | #define z 0 | |
6199 | #define C 1 | |
6200 | #define c 0 | |
6201 | #define V 1 | |
6202 | #define v 0 | |
6203 | #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d)) | |
6204 | static const asm_nzcv nzcv_names[] = { | |
6205 | {"nzcv", B (n, z, c, v)}, | |
6206 | {"nzcV", B (n, z, c, V)}, | |
6207 | {"nzCv", B (n, z, C, v)}, | |
6208 | {"nzCV", B (n, z, C, V)}, | |
6209 | {"nZcv", B (n, Z, c, v)}, | |
6210 | {"nZcV", B (n, Z, c, V)}, | |
6211 | {"nZCv", B (n, Z, C, v)}, | |
6212 | {"nZCV", B (n, Z, C, V)}, | |
6213 | {"Nzcv", B (N, z, c, v)}, | |
6214 | {"NzcV", B (N, z, c, V)}, | |
6215 | {"NzCv", B (N, z, C, v)}, | |
6216 | {"NzCV", B (N, z, C, V)}, | |
6217 | {"NZcv", B (N, Z, c, v)}, | |
6218 | {"NZcV", B (N, Z, c, V)}, | |
6219 | {"NZCv", B (N, Z, C, v)}, | |
6220 | {"NZCV", B (N, Z, C, V)} | |
6221 | }; | |
6222 | ||
6223 | #undef N | |
6224 | #undef n | |
6225 | #undef Z | |
6226 | #undef z | |
6227 | #undef C | |
6228 | #undef c | |
6229 | #undef V | |
6230 | #undef v | |
6231 | #undef B | |
6232 | \f | |
6233 | /* MD interface: bits in the object file. */ | |
6234 | ||
6235 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate | |
6236 | for use in the a.out file, and stores them in the array pointed to by buf. | |
6237 | This knows about the endian-ness of the target machine and does | |
6238 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
6239 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
6240 | LITTLENUMS (shorts, here at least). */ | |
6241 | ||
6242 | void | |
6243 | md_number_to_chars (char *buf, valueT val, int n) | |
6244 | { | |
6245 | if (target_big_endian) | |
6246 | number_to_chars_bigendian (buf, val, n); | |
6247 | else | |
6248 | number_to_chars_littleendian (buf, val, n); | |
6249 | } | |
6250 | ||
6251 | /* MD interface: Sections. */ | |
6252 | ||
6253 | /* Estimate the size of a frag before relaxing. Assume everything fits in | |
6254 | 4 bytes. */ | |
6255 | ||
6256 | int | |
6257 | md_estimate_size_before_relax (fragS * fragp, segT segtype ATTRIBUTE_UNUSED) | |
6258 | { | |
6259 | fragp->fr_var = 4; | |
6260 | return 4; | |
6261 | } | |
6262 | ||
6263 | /* Round up a section size to the appropriate boundary. */ | |
6264 | ||
6265 | valueT | |
6266 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) | |
6267 | { | |
6268 | return size; | |
6269 | } | |
6270 | ||
6271 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents | |
f803aa8e DPT |
6272 | of an rs_align_code fragment. |
6273 | ||
6274 | Here we fill the frag with the appropriate info for padding the | |
6275 | output stream. The resulting frag will consist of a fixed (fr_fix) | |
6276 | and of a repeating (fr_var) part. | |
6277 | ||
6278 | The fixed content is always emitted before the repeating content and | |
6279 | these two parts are used as follows in constructing the output: | |
6280 | - the fixed part will be used to align to a valid instruction word | |
6281 | boundary, in case that we start at a misaligned address; as no | |
6282 | executable instruction can live at the misaligned location, we | |
6283 | simply fill with zeros; | |
6284 | - the variable part will be used to cover the remaining padding and | |
6285 | we fill using the AArch64 NOP instruction. | |
6286 | ||
6287 | Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide | |
6288 | enough storage space for up to 3 bytes for padding the back to a valid | |
6289 | instruction alignment and exactly 4 bytes to store the NOP pattern. */ | |
a06ea964 NC |
6290 | |
6291 | void | |
6292 | aarch64_handle_align (fragS * fragP) | |
6293 | { | |
6294 | /* NOP = d503201f */ | |
6295 | /* AArch64 instructions are always little-endian. */ | |
d9235011 | 6296 | static unsigned char const aarch64_noop[4] = { 0x1f, 0x20, 0x03, 0xd5 }; |
a06ea964 NC |
6297 | |
6298 | int bytes, fix, noop_size; | |
6299 | char *p; | |
a06ea964 NC |
6300 | |
6301 | if (fragP->fr_type != rs_align_code) | |
6302 | return; | |
6303 | ||
6304 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
6305 | p = fragP->fr_literal + fragP->fr_fix; | |
a06ea964 NC |
6306 | |
6307 | #ifdef OBJ_ELF | |
6308 | gas_assert (fragP->tc_frag_data.recorded); | |
6309 | #endif | |
6310 | ||
a06ea964 | 6311 | noop_size = sizeof (aarch64_noop); |
a06ea964 | 6312 | |
f803aa8e DPT |
6313 | fix = bytes & (noop_size - 1); |
6314 | if (fix) | |
a06ea964 | 6315 | { |
a06ea964 NC |
6316 | #ifdef OBJ_ELF |
6317 | insert_data_mapping_symbol (MAP_INSN, fragP->fr_fix, fragP, fix); | |
6318 | #endif | |
6319 | memset (p, 0, fix); | |
6320 | p += fix; | |
f803aa8e | 6321 | fragP->fr_fix += fix; |
a06ea964 NC |
6322 | } |
6323 | ||
f803aa8e DPT |
6324 | if (noop_size) |
6325 | memcpy (p, aarch64_noop, noop_size); | |
6326 | fragP->fr_var = noop_size; | |
a06ea964 NC |
6327 | } |
6328 | ||
6329 | /* Perform target specific initialisation of a frag. | |
6330 | Note - despite the name this initialisation is not done when the frag | |
6331 | is created, but only when its type is assigned. A frag can be created | |
6332 | and used a long time before its type is set, so beware of assuming that | |
6333 | this initialisationis performed first. */ | |
6334 | ||
6335 | #ifndef OBJ_ELF | |
6336 | void | |
6337 | aarch64_init_frag (fragS * fragP ATTRIBUTE_UNUSED, | |
6338 | int max_chars ATTRIBUTE_UNUSED) | |
6339 | { | |
6340 | } | |
6341 | ||
6342 | #else /* OBJ_ELF is defined. */ | |
6343 | void | |
6344 | aarch64_init_frag (fragS * fragP, int max_chars) | |
6345 | { | |
6346 | /* Record a mapping symbol for alignment frags. We will delete this | |
6347 | later if the alignment ends up empty. */ | |
6348 | if (!fragP->tc_frag_data.recorded) | |
c7ad08e6 RL |
6349 | fragP->tc_frag_data.recorded = 1; |
6350 | ||
6351 | switch (fragP->fr_type) | |
a06ea964 | 6352 | { |
c7ad08e6 RL |
6353 | case rs_align_test: |
6354 | case rs_fill: | |
6355 | mapping_state_2 (MAP_DATA, max_chars); | |
6356 | break; | |
7ea12e5c NC |
6357 | case rs_align: |
6358 | /* PR 20364: We can get alignment frags in code sections, | |
6359 | so do not just assume that we should use the MAP_DATA state. */ | |
6360 | mapping_state_2 (subseg_text_p (now_seg) ? MAP_INSN : MAP_DATA, max_chars); | |
6361 | break; | |
c7ad08e6 RL |
6362 | case rs_align_code: |
6363 | mapping_state_2 (MAP_INSN, max_chars); | |
6364 | break; | |
6365 | default: | |
6366 | break; | |
a06ea964 NC |
6367 | } |
6368 | } | |
6369 | \f | |
6370 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
6371 | ||
6372 | void | |
6373 | tc_aarch64_frame_initial_instructions (void) | |
6374 | { | |
6375 | cfi_add_CFA_def_cfa (REG_SP, 0); | |
6376 | } | |
6377 | #endif /* OBJ_ELF */ | |
6378 | ||
6379 | /* Convert REGNAME to a DWARF-2 register number. */ | |
6380 | ||
6381 | int | |
6382 | tc_aarch64_regname_to_dw2regnum (char *regname) | |
6383 | { | |
6384 | const reg_entry *reg = parse_reg (®name); | |
6385 | if (reg == NULL) | |
6386 | return -1; | |
6387 | ||
6388 | switch (reg->type) | |
6389 | { | |
6390 | case REG_TYPE_SP_32: | |
6391 | case REG_TYPE_SP_64: | |
6392 | case REG_TYPE_R_32: | |
6393 | case REG_TYPE_R_64: | |
a2cac51c RH |
6394 | return reg->number; |
6395 | ||
a06ea964 NC |
6396 | case REG_TYPE_FP_B: |
6397 | case REG_TYPE_FP_H: | |
6398 | case REG_TYPE_FP_S: | |
6399 | case REG_TYPE_FP_D: | |
6400 | case REG_TYPE_FP_Q: | |
a2cac51c RH |
6401 | return reg->number + 64; |
6402 | ||
a06ea964 NC |
6403 | default: |
6404 | break; | |
6405 | } | |
6406 | return -1; | |
6407 | } | |
6408 | ||
cec5225b YZ |
6409 | /* Implement DWARF2_ADDR_SIZE. */ |
6410 | ||
6411 | int | |
6412 | aarch64_dwarf2_addr_size (void) | |
6413 | { | |
6414 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
6415 | if (ilp32_p) | |
6416 | return 4; | |
6417 | #endif | |
6418 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
6419 | } | |
6420 | ||
a06ea964 NC |
6421 | /* MD interface: Symbol and relocation handling. */ |
6422 | ||
6423 | /* Return the address within the segment that a PC-relative fixup is | |
6424 | relative to. For AArch64 PC-relative fixups applied to instructions | |
6425 | are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */ | |
6426 | ||
6427 | long | |
6428 | md_pcrel_from_section (fixS * fixP, segT seg) | |
6429 | { | |
6430 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; | |
6431 | ||
6432 | /* If this is pc-relative and we are going to emit a relocation | |
6433 | then we just want to put out any pipeline compensation that the linker | |
6434 | will need. Otherwise we want to use the calculated base. */ | |
6435 | if (fixP->fx_pcrel | |
6436 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
6437 | || aarch64_force_relocation (fixP))) | |
6438 | base = 0; | |
6439 | ||
6440 | /* AArch64 should be consistent for all pc-relative relocations. */ | |
6441 | return base + AARCH64_PCREL_OFFSET; | |
6442 | } | |
6443 | ||
6444 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. | |
6445 | Otherwise we have no need to default values of symbols. */ | |
6446 | ||
6447 | symbolS * | |
6448 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) | |
6449 | { | |
6450 | #ifdef OBJ_ELF | |
6451 | if (name[0] == '_' && name[1] == 'G' | |
6452 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
6453 | { | |
6454 | if (!GOT_symbol) | |
6455 | { | |
6456 | if (symbol_find (name)) | |
6457 | as_bad (_("GOT already in the symbol table")); | |
6458 | ||
6459 | GOT_symbol = symbol_new (name, undefined_section, | |
6460 | (valueT) 0, &zero_address_frag); | |
6461 | } | |
6462 | ||
6463 | return GOT_symbol; | |
6464 | } | |
6465 | #endif | |
6466 | ||
6467 | return 0; | |
6468 | } | |
6469 | ||
6470 | /* Return non-zero if the indicated VALUE has overflowed the maximum | |
6471 | range expressible by a unsigned number with the indicated number of | |
6472 | BITS. */ | |
6473 | ||
6474 | static bfd_boolean | |
6475 | unsigned_overflow (valueT value, unsigned bits) | |
6476 | { | |
6477 | valueT lim; | |
6478 | if (bits >= sizeof (valueT) * 8) | |
6479 | return FALSE; | |
6480 | lim = (valueT) 1 << bits; | |
6481 | return (value >= lim); | |
6482 | } | |
6483 | ||
6484 | ||
6485 | /* Return non-zero if the indicated VALUE has overflowed the maximum | |
6486 | range expressible by an signed number with the indicated number of | |
6487 | BITS. */ | |
6488 | ||
6489 | static bfd_boolean | |
6490 | signed_overflow (offsetT value, unsigned bits) | |
6491 | { | |
6492 | offsetT lim; | |
6493 | if (bits >= sizeof (offsetT) * 8) | |
6494 | return FALSE; | |
6495 | lim = (offsetT) 1 << (bits - 1); | |
6496 | return (value < -lim || value >= lim); | |
6497 | } | |
6498 | ||
6499 | /* Given an instruction in *INST, which is expected to be a scaled, 12-bit, | |
6500 | unsigned immediate offset load/store instruction, try to encode it as | |
6501 | an unscaled, 9-bit, signed immediate offset load/store instruction. | |
6502 | Return TRUE if it is successful; otherwise return FALSE. | |
6503 | ||
6504 | As a programmer-friendly assembler, LDUR/STUR instructions can be generated | |
6505 | in response to the standard LDR/STR mnemonics when the immediate offset is | |
6506 | unambiguous, i.e. when it is negative or unaligned. */ | |
6507 | ||
6508 | static bfd_boolean | |
6509 | try_to_encode_as_unscaled_ldst (aarch64_inst *instr) | |
6510 | { | |
6511 | int idx; | |
6512 | enum aarch64_op new_op; | |
6513 | const aarch64_opcode *new_opcode; | |
6514 | ||
6515 | gas_assert (instr->opcode->iclass == ldst_pos); | |
6516 | ||
6517 | switch (instr->opcode->op) | |
6518 | { | |
6519 | case OP_LDRB_POS:new_op = OP_LDURB; break; | |
6520 | case OP_STRB_POS: new_op = OP_STURB; break; | |
6521 | case OP_LDRSB_POS: new_op = OP_LDURSB; break; | |
6522 | case OP_LDRH_POS: new_op = OP_LDURH; break; | |
6523 | case OP_STRH_POS: new_op = OP_STURH; break; | |
6524 | case OP_LDRSH_POS: new_op = OP_LDURSH; break; | |
6525 | case OP_LDR_POS: new_op = OP_LDUR; break; | |
6526 | case OP_STR_POS: new_op = OP_STUR; break; | |
6527 | case OP_LDRF_POS: new_op = OP_LDURV; break; | |
6528 | case OP_STRF_POS: new_op = OP_STURV; break; | |
6529 | case OP_LDRSW_POS: new_op = OP_LDURSW; break; | |
6530 | case OP_PRFM_POS: new_op = OP_PRFUM; break; | |
6531 | default: new_op = OP_NIL; break; | |
6532 | } | |
6533 | ||
6534 | if (new_op == OP_NIL) | |
6535 | return FALSE; | |
6536 | ||
6537 | new_opcode = aarch64_get_opcode (new_op); | |
6538 | gas_assert (new_opcode != NULL); | |
6539 | ||
6540 | DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d", | |
6541 | instr->opcode->op, new_opcode->op); | |
6542 | ||
6543 | aarch64_replace_opcode (instr, new_opcode); | |
6544 | ||
6545 | /* Clear up the ADDR_SIMM9's qualifier; otherwise the | |
6546 | qualifier matching may fail because the out-of-date qualifier will | |
6547 | prevent the operand being updated with a new and correct qualifier. */ | |
6548 | idx = aarch64_operand_index (instr->opcode->operands, | |
6549 | AARCH64_OPND_ADDR_SIMM9); | |
6550 | gas_assert (idx == 1); | |
6551 | instr->operands[idx].qualifier = AARCH64_OPND_QLF_NIL; | |
6552 | ||
6553 | DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB"); | |
6554 | ||
6555 | if (!aarch64_opcode_encode (instr->opcode, instr, &instr->value, NULL, NULL)) | |
6556 | return FALSE; | |
6557 | ||
6558 | return TRUE; | |
6559 | } | |
6560 | ||
6561 | /* Called by fix_insn to fix a MOV immediate alias instruction. | |
6562 | ||
6563 | Operand for a generic move immediate instruction, which is an alias | |
6564 | instruction that generates a single MOVZ, MOVN or ORR instruction to loads | |
6565 | a 32-bit/64-bit immediate value into general register. An assembler error | |
6566 | shall result if the immediate cannot be created by a single one of these | |
6567 | instructions. If there is a choice, then to ensure reversability an | |
6568 | assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */ | |
6569 | ||
6570 | static void | |
6571 | fix_mov_imm_insn (fixS *fixP, char *buf, aarch64_inst *instr, offsetT value) | |
6572 | { | |
6573 | const aarch64_opcode *opcode; | |
6574 | ||
6575 | /* Need to check if the destination is SP/ZR. The check has to be done | |
6576 | before any aarch64_replace_opcode. */ | |
6577 | int try_mov_wide_p = !aarch64_stack_pointer_p (&instr->operands[0]); | |
6578 | int try_mov_bitmask_p = !aarch64_zero_register_p (&instr->operands[0]); | |
6579 | ||
6580 | instr->operands[1].imm.value = value; | |
6581 | instr->operands[1].skip = 0; | |
6582 | ||
6583 | if (try_mov_wide_p) | |
6584 | { | |
6585 | /* Try the MOVZ alias. */ | |
6586 | opcode = aarch64_get_opcode (OP_MOV_IMM_WIDE); | |
6587 | aarch64_replace_opcode (instr, opcode); | |
6588 | if (aarch64_opcode_encode (instr->opcode, instr, | |
6589 | &instr->value, NULL, NULL)) | |
6590 | { | |
6591 | put_aarch64_insn (buf, instr->value); | |
6592 | return; | |
6593 | } | |
6594 | /* Try the MOVK alias. */ | |
6595 | opcode = aarch64_get_opcode (OP_MOV_IMM_WIDEN); | |
6596 | aarch64_replace_opcode (instr, opcode); | |
6597 | if (aarch64_opcode_encode (instr->opcode, instr, | |
6598 | &instr->value, NULL, NULL)) | |
6599 | { | |
6600 | put_aarch64_insn (buf, instr->value); | |
6601 | return; | |
6602 | } | |
6603 | } | |
6604 | ||
6605 | if (try_mov_bitmask_p) | |
6606 | { | |
6607 | /* Try the ORR alias. */ | |
6608 | opcode = aarch64_get_opcode (OP_MOV_IMM_LOG); | |
6609 | aarch64_replace_opcode (instr, opcode); | |
6610 | if (aarch64_opcode_encode (instr->opcode, instr, | |
6611 | &instr->value, NULL, NULL)) | |
6612 | { | |
6613 | put_aarch64_insn (buf, instr->value); | |
6614 | return; | |
6615 | } | |
6616 | } | |
6617 | ||
6618 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6619 | _("immediate cannot be moved by a single instruction")); | |
6620 | } | |
6621 | ||
6622 | /* An instruction operand which is immediate related may have symbol used | |
6623 | in the assembly, e.g. | |
6624 | ||
6625 | mov w0, u32 | |
6626 | .set u32, 0x00ffff00 | |
6627 | ||
6628 | At the time when the assembly instruction is parsed, a referenced symbol, | |
6629 | like 'u32' in the above example may not have been seen; a fixS is created | |
6630 | in such a case and is handled here after symbols have been resolved. | |
6631 | Instruction is fixed up with VALUE using the information in *FIXP plus | |
6632 | extra information in FLAGS. | |
6633 | ||
6634 | This function is called by md_apply_fix to fix up instructions that need | |
6635 | a fix-up described above but does not involve any linker-time relocation. */ | |
6636 | ||
6637 | static void | |
6638 | fix_insn (fixS *fixP, uint32_t flags, offsetT value) | |
6639 | { | |
6640 | int idx; | |
6641 | uint32_t insn; | |
6642 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
6643 | enum aarch64_opnd opnd = fixP->tc_fix_data.opnd; | |
6644 | aarch64_inst *new_inst = fixP->tc_fix_data.inst; | |
6645 | ||
6646 | if (new_inst) | |
6647 | { | |
6648 | /* Now the instruction is about to be fixed-up, so the operand that | |
6649 | was previously marked as 'ignored' needs to be unmarked in order | |
6650 | to get the encoding done properly. */ | |
6651 | idx = aarch64_operand_index (new_inst->opcode->operands, opnd); | |
6652 | new_inst->operands[idx].skip = 0; | |
6653 | } | |
6654 | ||
6655 | gas_assert (opnd != AARCH64_OPND_NIL); | |
6656 | ||
6657 | switch (opnd) | |
6658 | { | |
6659 | case AARCH64_OPND_EXCEPTION: | |
6660 | if (unsigned_overflow (value, 16)) | |
6661 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6662 | _("immediate out of range")); | |
6663 | insn = get_aarch64_insn (buf); | |
6664 | insn |= encode_svc_imm (value); | |
6665 | put_aarch64_insn (buf, insn); | |
6666 | break; | |
6667 | ||
6668 | case AARCH64_OPND_AIMM: | |
6669 | /* ADD or SUB with immediate. | |
6670 | NOTE this assumes we come here with a add/sub shifted reg encoding | |
6671 | 3 322|2222|2 2 2 21111 111111 | |
6672 | 1 098|7654|3 2 1 09876 543210 98765 43210 | |
6673 | 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD | |
6674 | 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS | |
6675 | 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB | |
6676 | 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS | |
6677 | -> | |
6678 | 3 322|2222|2 2 221111111111 | |
6679 | 1 098|7654|3 2 109876543210 98765 43210 | |
6680 | 11000000 sf 001|0001|shift imm12 Rn Rd ADD | |
6681 | 31000000 sf 011|0001|shift imm12 Rn Rd ADDS | |
6682 | 51000000 sf 101|0001|shift imm12 Rn Rd SUB | |
6683 | 71000000 sf 111|0001|shift imm12 Rn Rd SUBS | |
6684 | Fields sf Rn Rd are already set. */ | |
6685 | insn = get_aarch64_insn (buf); | |
6686 | if (value < 0) | |
6687 | { | |
6688 | /* Add <-> sub. */ | |
6689 | insn = reencode_addsub_switch_add_sub (insn); | |
6690 | value = -value; | |
6691 | } | |
6692 | ||
6693 | if ((flags & FIXUP_F_HAS_EXPLICIT_SHIFT) == 0 | |
6694 | && unsigned_overflow (value, 12)) | |
6695 | { | |
6696 | /* Try to shift the value by 12 to make it fit. */ | |
6697 | if (((value >> 12) << 12) == value | |
6698 | && ! unsigned_overflow (value, 12 + 12)) | |
6699 | { | |
6700 | value >>= 12; | |
6701 | insn |= encode_addsub_imm_shift_amount (1); | |
6702 | } | |
6703 | } | |
6704 | ||
6705 | if (unsigned_overflow (value, 12)) | |
6706 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6707 | _("immediate out of range")); | |
6708 | ||
6709 | insn |= encode_addsub_imm (value); | |
6710 | ||
6711 | put_aarch64_insn (buf, insn); | |
6712 | break; | |
6713 | ||
6714 | case AARCH64_OPND_SIMD_IMM: | |
6715 | case AARCH64_OPND_SIMD_IMM_SFT: | |
6716 | case AARCH64_OPND_LIMM: | |
6717 | /* Bit mask immediate. */ | |
6718 | gas_assert (new_inst != NULL); | |
6719 | idx = aarch64_operand_index (new_inst->opcode->operands, opnd); | |
6720 | new_inst->operands[idx].imm.value = value; | |
6721 | if (aarch64_opcode_encode (new_inst->opcode, new_inst, | |
6722 | &new_inst->value, NULL, NULL)) | |
6723 | put_aarch64_insn (buf, new_inst->value); | |
6724 | else | |
6725 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6726 | _("invalid immediate")); | |
6727 | break; | |
6728 | ||
6729 | case AARCH64_OPND_HALF: | |
6730 | /* 16-bit unsigned immediate. */ | |
6731 | if (unsigned_overflow (value, 16)) | |
6732 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6733 | _("immediate out of range")); | |
6734 | insn = get_aarch64_insn (buf); | |
6735 | insn |= encode_movw_imm (value & 0xffff); | |
6736 | put_aarch64_insn (buf, insn); | |
6737 | break; | |
6738 | ||
6739 | case AARCH64_OPND_IMM_MOV: | |
6740 | /* Operand for a generic move immediate instruction, which is | |
6741 | an alias instruction that generates a single MOVZ, MOVN or ORR | |
6742 | instruction to loads a 32-bit/64-bit immediate value into general | |
6743 | register. An assembler error shall result if the immediate cannot be | |
6744 | created by a single one of these instructions. If there is a choice, | |
6745 | then to ensure reversability an assembler must prefer a MOVZ to MOVN, | |
6746 | and MOVZ or MOVN to ORR. */ | |
6747 | gas_assert (new_inst != NULL); | |
6748 | fix_mov_imm_insn (fixP, buf, new_inst, value); | |
6749 | break; | |
6750 | ||
6751 | case AARCH64_OPND_ADDR_SIMM7: | |
6752 | case AARCH64_OPND_ADDR_SIMM9: | |
6753 | case AARCH64_OPND_ADDR_SIMM9_2: | |
6754 | case AARCH64_OPND_ADDR_UIMM12: | |
6755 | /* Immediate offset in an address. */ | |
6756 | insn = get_aarch64_insn (buf); | |
6757 | ||
6758 | gas_assert (new_inst != NULL && new_inst->value == insn); | |
6759 | gas_assert (new_inst->opcode->operands[1] == opnd | |
6760 | || new_inst->opcode->operands[2] == opnd); | |
6761 | ||
6762 | /* Get the index of the address operand. */ | |
6763 | if (new_inst->opcode->operands[1] == opnd) | |
6764 | /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
6765 | idx = 1; | |
6766 | else | |
6767 | /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */ | |
6768 | idx = 2; | |
6769 | ||
6770 | /* Update the resolved offset value. */ | |
6771 | new_inst->operands[idx].addr.offset.imm = value; | |
6772 | ||
6773 | /* Encode/fix-up. */ | |
6774 | if (aarch64_opcode_encode (new_inst->opcode, new_inst, | |
6775 | &new_inst->value, NULL, NULL)) | |
6776 | { | |
6777 | put_aarch64_insn (buf, new_inst->value); | |
6778 | break; | |
6779 | } | |
6780 | else if (new_inst->opcode->iclass == ldst_pos | |
6781 | && try_to_encode_as_unscaled_ldst (new_inst)) | |
6782 | { | |
6783 | put_aarch64_insn (buf, new_inst->value); | |
6784 | break; | |
6785 | } | |
6786 | ||
6787 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6788 | _("immediate offset out of range")); | |
6789 | break; | |
6790 | ||
6791 | default: | |
6792 | gas_assert (0); | |
6793 | as_fatal (_("unhandled operand code %d"), opnd); | |
6794 | } | |
6795 | } | |
6796 | ||
6797 | /* Apply a fixup (fixP) to segment data, once it has been determined | |
6798 | by our caller that we have all the info we need to fix it up. | |
6799 | ||
6800 | Parameter valP is the pointer to the value of the bits. */ | |
6801 | ||
6802 | void | |
6803 | md_apply_fix (fixS * fixP, valueT * valP, segT seg) | |
6804 | { | |
6805 | offsetT value = *valP; | |
6806 | uint32_t insn; | |
6807 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
6808 | int scale; | |
6809 | unsigned flags = fixP->fx_addnumber; | |
6810 | ||
6811 | DEBUG_TRACE ("\n\n"); | |
6812 | DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~"); | |
6813 | DEBUG_TRACE ("Enter md_apply_fix"); | |
6814 | ||
6815 | gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); | |
6816 | ||
6817 | /* Note whether this will delete the relocation. */ | |
6818 | ||
6819 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
6820 | fixP->fx_done = 1; | |
6821 | ||
6822 | /* Process the relocations. */ | |
6823 | switch (fixP->fx_r_type) | |
6824 | { | |
6825 | case BFD_RELOC_NONE: | |
6826 | /* This will need to go in the object file. */ | |
6827 | fixP->fx_done = 0; | |
6828 | break; | |
6829 | ||
6830 | case BFD_RELOC_8: | |
6831 | case BFD_RELOC_8_PCREL: | |
6832 | if (fixP->fx_done || !seg->use_rela_p) | |
6833 | md_number_to_chars (buf, value, 1); | |
6834 | break; | |
6835 | ||
6836 | case BFD_RELOC_16: | |
6837 | case BFD_RELOC_16_PCREL: | |
6838 | if (fixP->fx_done || !seg->use_rela_p) | |
6839 | md_number_to_chars (buf, value, 2); | |
6840 | break; | |
6841 | ||
6842 | case BFD_RELOC_32: | |
6843 | case BFD_RELOC_32_PCREL: | |
6844 | if (fixP->fx_done || !seg->use_rela_p) | |
6845 | md_number_to_chars (buf, value, 4); | |
6846 | break; | |
6847 | ||
6848 | case BFD_RELOC_64: | |
6849 | case BFD_RELOC_64_PCREL: | |
6850 | if (fixP->fx_done || !seg->use_rela_p) | |
6851 | md_number_to_chars (buf, value, 8); | |
6852 | break; | |
6853 | ||
6854 | case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP: | |
6855 | /* We claim that these fixups have been processed here, even if | |
6856 | in fact we generate an error because we do not have a reloc | |
6857 | for them, so tc_gen_reloc() will reject them. */ | |
6858 | fixP->fx_done = 1; | |
6859 | if (fixP->fx_addsy && !S_IS_DEFINED (fixP->fx_addsy)) | |
6860 | { | |
6861 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6862 | _("undefined symbol %s used as an immediate value"), | |
6863 | S_GET_NAME (fixP->fx_addsy)); | |
6864 | goto apply_fix_return; | |
6865 | } | |
6866 | fix_insn (fixP, flags, value); | |
6867 | break; | |
6868 | ||
6869 | case BFD_RELOC_AARCH64_LD_LO19_PCREL: | |
a06ea964 NC |
6870 | if (fixP->fx_done || !seg->use_rela_p) |
6871 | { | |
89d2a2a3 MS |
6872 | if (value & 3) |
6873 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6874 | _("pc-relative load offset not word aligned")); | |
6875 | if (signed_overflow (value, 21)) | |
6876 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6877 | _("pc-relative load offset out of range")); | |
a06ea964 NC |
6878 | insn = get_aarch64_insn (buf); |
6879 | insn |= encode_ld_lit_ofs_19 (value >> 2); | |
6880 | put_aarch64_insn (buf, insn); | |
6881 | } | |
6882 | break; | |
6883 | ||
6884 | case BFD_RELOC_AARCH64_ADR_LO21_PCREL: | |
a06ea964 NC |
6885 | if (fixP->fx_done || !seg->use_rela_p) |
6886 | { | |
89d2a2a3 MS |
6887 | if (signed_overflow (value, 21)) |
6888 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6889 | _("pc-relative address offset out of range")); | |
a06ea964 NC |
6890 | insn = get_aarch64_insn (buf); |
6891 | insn |= encode_adr_imm (value); | |
6892 | put_aarch64_insn (buf, insn); | |
6893 | } | |
6894 | break; | |
6895 | ||
6896 | case BFD_RELOC_AARCH64_BRANCH19: | |
a06ea964 NC |
6897 | if (fixP->fx_done || !seg->use_rela_p) |
6898 | { | |
89d2a2a3 MS |
6899 | if (value & 3) |
6900 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6901 | _("conditional branch target not word aligned")); | |
6902 | if (signed_overflow (value, 21)) | |
6903 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6904 | _("conditional branch out of range")); | |
a06ea964 NC |
6905 | insn = get_aarch64_insn (buf); |
6906 | insn |= encode_cond_branch_ofs_19 (value >> 2); | |
6907 | put_aarch64_insn (buf, insn); | |
6908 | } | |
6909 | break; | |
6910 | ||
6911 | case BFD_RELOC_AARCH64_TSTBR14: | |
a06ea964 NC |
6912 | if (fixP->fx_done || !seg->use_rela_p) |
6913 | { | |
89d2a2a3 MS |
6914 | if (value & 3) |
6915 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6916 | _("conditional branch target not word aligned")); | |
6917 | if (signed_overflow (value, 16)) | |
6918 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6919 | _("conditional branch out of range")); | |
a06ea964 NC |
6920 | insn = get_aarch64_insn (buf); |
6921 | insn |= encode_tst_branch_ofs_14 (value >> 2); | |
6922 | put_aarch64_insn (buf, insn); | |
6923 | } | |
6924 | break; | |
6925 | ||
a06ea964 | 6926 | case BFD_RELOC_AARCH64_CALL26: |
f09c556a | 6927 | case BFD_RELOC_AARCH64_JUMP26: |
a06ea964 NC |
6928 | if (fixP->fx_done || !seg->use_rela_p) |
6929 | { | |
89d2a2a3 MS |
6930 | if (value & 3) |
6931 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6932 | _("branch target not word aligned")); | |
6933 | if (signed_overflow (value, 28)) | |
6934 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6935 | _("branch out of range")); | |
a06ea964 NC |
6936 | insn = get_aarch64_insn (buf); |
6937 | insn |= encode_branch_ofs_26 (value >> 2); | |
6938 | put_aarch64_insn (buf, insn); | |
6939 | } | |
6940 | break; | |
6941 | ||
6942 | case BFD_RELOC_AARCH64_MOVW_G0: | |
a06ea964 | 6943 | case BFD_RELOC_AARCH64_MOVW_G0_NC: |
f09c556a | 6944 | case BFD_RELOC_AARCH64_MOVW_G0_S: |
ca632371 | 6945 | case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC: |
a06ea964 NC |
6946 | scale = 0; |
6947 | goto movw_common; | |
6948 | case BFD_RELOC_AARCH64_MOVW_G1: | |
a06ea964 | 6949 | case BFD_RELOC_AARCH64_MOVW_G1_NC: |
f09c556a | 6950 | case BFD_RELOC_AARCH64_MOVW_G1_S: |
654248e7 | 6951 | case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1: |
a06ea964 NC |
6952 | scale = 16; |
6953 | goto movw_common; | |
43a357f9 RL |
6954 | case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC: |
6955 | scale = 0; | |
6956 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
6957 | /* Should always be exported to object file, see | |
6958 | aarch64_force_relocation(). */ | |
6959 | gas_assert (!fixP->fx_done); | |
6960 | gas_assert (seg->use_rela_p); | |
6961 | goto movw_common; | |
6962 | case BFD_RELOC_AARCH64_TLSDESC_OFF_G1: | |
6963 | scale = 16; | |
6964 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
6965 | /* Should always be exported to object file, see | |
6966 | aarch64_force_relocation(). */ | |
6967 | gas_assert (!fixP->fx_done); | |
6968 | gas_assert (seg->use_rela_p); | |
6969 | goto movw_common; | |
a06ea964 | 6970 | case BFD_RELOC_AARCH64_MOVW_G2: |
a06ea964 | 6971 | case BFD_RELOC_AARCH64_MOVW_G2_NC: |
f09c556a | 6972 | case BFD_RELOC_AARCH64_MOVW_G2_S: |
a06ea964 NC |
6973 | scale = 32; |
6974 | goto movw_common; | |
6975 | case BFD_RELOC_AARCH64_MOVW_G3: | |
6976 | scale = 48; | |
6977 | movw_common: | |
6978 | if (fixP->fx_done || !seg->use_rela_p) | |
6979 | { | |
6980 | insn = get_aarch64_insn (buf); | |
6981 | ||
6982 | if (!fixP->fx_done) | |
6983 | { | |
6984 | /* REL signed addend must fit in 16 bits */ | |
6985 | if (signed_overflow (value, 16)) | |
6986 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6987 | _("offset out of range")); | |
6988 | } | |
6989 | else | |
6990 | { | |
6991 | /* Check for overflow and scale. */ | |
6992 | switch (fixP->fx_r_type) | |
6993 | { | |
6994 | case BFD_RELOC_AARCH64_MOVW_G0: | |
6995 | case BFD_RELOC_AARCH64_MOVW_G1: | |
6996 | case BFD_RELOC_AARCH64_MOVW_G2: | |
6997 | case BFD_RELOC_AARCH64_MOVW_G3: | |
654248e7 | 6998 | case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1: |
43a357f9 | 6999 | case BFD_RELOC_AARCH64_TLSDESC_OFF_G1: |
a06ea964 NC |
7000 | if (unsigned_overflow (value, scale + 16)) |
7001 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7002 | _("unsigned value out of range")); | |
7003 | break; | |
7004 | case BFD_RELOC_AARCH64_MOVW_G0_S: | |
7005 | case BFD_RELOC_AARCH64_MOVW_G1_S: | |
7006 | case BFD_RELOC_AARCH64_MOVW_G2_S: | |
7007 | /* NOTE: We can only come here with movz or movn. */ | |
7008 | if (signed_overflow (value, scale + 16)) | |
7009 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7010 | _("signed value out of range")); | |
7011 | if (value < 0) | |
7012 | { | |
7013 | /* Force use of MOVN. */ | |
7014 | value = ~value; | |
7015 | insn = reencode_movzn_to_movn (insn); | |
7016 | } | |
7017 | else | |
7018 | { | |
7019 | /* Force use of MOVZ. */ | |
7020 | insn = reencode_movzn_to_movz (insn); | |
7021 | } | |
7022 | break; | |
7023 | default: | |
7024 | /* Unchecked relocations. */ | |
7025 | break; | |
7026 | } | |
7027 | value >>= scale; | |
7028 | } | |
7029 | ||
7030 | /* Insert value into MOVN/MOVZ/MOVK instruction. */ | |
7031 | insn |= encode_movw_imm (value & 0xffff); | |
7032 | ||
7033 | put_aarch64_insn (buf, insn); | |
7034 | } | |
7035 | break; | |
7036 | ||
a6bb11b2 YZ |
7037 | case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC: |
7038 | fixP->fx_r_type = (ilp32_p | |
7039 | ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC | |
7040 | : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC); | |
7041 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
7042 | /* Should always be exported to object file, see | |
7043 | aarch64_force_relocation(). */ | |
7044 | gas_assert (!fixP->fx_done); | |
7045 | gas_assert (seg->use_rela_p); | |
7046 | break; | |
7047 | ||
7048 | case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC: | |
7049 | fixP->fx_r_type = (ilp32_p | |
7050 | ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC | |
7051 | : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC); | |
7052 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
7053 | /* Should always be exported to object file, see | |
7054 | aarch64_force_relocation(). */ | |
7055 | gas_assert (!fixP->fx_done); | |
7056 | gas_assert (seg->use_rela_p); | |
7057 | break; | |
7058 | ||
2c0a3565 MS |
7059 | case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC: |
7060 | case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21: | |
389b8029 | 7061 | case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21: |
2c0a3565 MS |
7062 | case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC: |
7063 | case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC: | |
1ada945d | 7064 | case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19: |
a06ea964 | 7065 | case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC: |
2c0a3565 | 7066 | case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21: |
3c12b054 | 7067 | case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21: |
3e8286c0 | 7068 | case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC: |
1aa66fb1 | 7069 | case BFD_RELOC_AARCH64_TLSGD_MOVW_G1: |
a06ea964 | 7070 | case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: |
a6bb11b2 | 7071 | case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC: |
2c0a3565 | 7072 | case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: |
043bf05a | 7073 | case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19: |
3b957e5b RL |
7074 | case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC: |
7075 | case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1: | |
49df5539 | 7076 | case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12: |
70151fb5 | 7077 | case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12: |
13289c10 | 7078 | case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC: |
a12fad50 | 7079 | case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC: |
1107e076 | 7080 | case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21: |
6c37fedc | 7081 | case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21: |
4c562523 JW |
7082 | case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12: |
7083 | case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC: | |
7084 | case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12: | |
7085 | case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC: | |
7086 | case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12: | |
7087 | case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC: | |
7088 | case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12: | |
7089 | case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC: | |
49df5539 JW |
7090 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0: |
7091 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC: | |
7092 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1: | |
7093 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC: | |
7094 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2: | |
a06ea964 | 7095 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12: |
2c0a3565 | 7096 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12: |
a06ea964 | 7097 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC: |
a06ea964 NC |
7098 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0: |
7099 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC: | |
2c0a3565 MS |
7100 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1: |
7101 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC: | |
7102 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2: | |
a06ea964 NC |
7103 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
7104 | /* Should always be exported to object file, see | |
7105 | aarch64_force_relocation(). */ | |
7106 | gas_assert (!fixP->fx_done); | |
7107 | gas_assert (seg->use_rela_p); | |
7108 | break; | |
7109 | ||
a6bb11b2 YZ |
7110 | case BFD_RELOC_AARCH64_LD_GOT_LO12_NC: |
7111 | /* Should always be exported to object file, see | |
7112 | aarch64_force_relocation(). */ | |
7113 | fixP->fx_r_type = (ilp32_p | |
7114 | ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC | |
7115 | : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC); | |
7116 | gas_assert (!fixP->fx_done); | |
7117 | gas_assert (seg->use_rela_p); | |
7118 | break; | |
7119 | ||
a06ea964 | 7120 | case BFD_RELOC_AARCH64_ADD_LO12: |
f09c556a JW |
7121 | case BFD_RELOC_AARCH64_ADR_GOT_PAGE: |
7122 | case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL: | |
7123 | case BFD_RELOC_AARCH64_ADR_HI21_PCREL: | |
7124 | case BFD_RELOC_AARCH64_GOT_LD_PREL19: | |
7125 | case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC: | |
3d715ce4 | 7126 | case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14: |
87f5fbcc | 7127 | case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15: |
a921b5bd | 7128 | case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15: |
f09c556a JW |
7129 | case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC: |
7130 | case BFD_RELOC_AARCH64_LDST128_LO12: | |
a06ea964 NC |
7131 | case BFD_RELOC_AARCH64_LDST16_LO12: |
7132 | case BFD_RELOC_AARCH64_LDST32_LO12: | |
7133 | case BFD_RELOC_AARCH64_LDST64_LO12: | |
f09c556a | 7134 | case BFD_RELOC_AARCH64_LDST8_LO12: |
a06ea964 NC |
7135 | /* Should always be exported to object file, see |
7136 | aarch64_force_relocation(). */ | |
7137 | gas_assert (!fixP->fx_done); | |
7138 | gas_assert (seg->use_rela_p); | |
7139 | break; | |
7140 | ||
7141 | case BFD_RELOC_AARCH64_TLSDESC_ADD: | |
a06ea964 | 7142 | case BFD_RELOC_AARCH64_TLSDESC_CALL: |
f09c556a | 7143 | case BFD_RELOC_AARCH64_TLSDESC_LDR: |
a06ea964 NC |
7144 | break; |
7145 | ||
b97e87cc NC |
7146 | case BFD_RELOC_UNUSED: |
7147 | /* An error will already have been reported. */ | |
7148 | break; | |
7149 | ||
a06ea964 NC |
7150 | default: |
7151 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7152 | _("unexpected %s fixup"), | |
7153 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
7154 | break; | |
7155 | } | |
7156 | ||
7157 | apply_fix_return: | |
7158 | /* Free the allocated the struct aarch64_inst. | |
7159 | N.B. currently there are very limited number of fix-up types actually use | |
7160 | this field, so the impact on the performance should be minimal . */ | |
7161 | if (fixP->tc_fix_data.inst != NULL) | |
7162 | free (fixP->tc_fix_data.inst); | |
7163 | ||
7164 | return; | |
7165 | } | |
7166 | ||
7167 | /* Translate internal representation of relocation info to BFD target | |
7168 | format. */ | |
7169 | ||
7170 | arelent * | |
7171 | tc_gen_reloc (asection * section, fixS * fixp) | |
7172 | { | |
7173 | arelent *reloc; | |
7174 | bfd_reloc_code_real_type code; | |
7175 | ||
325801bd | 7176 | reloc = XNEW (arelent); |
a06ea964 | 7177 | |
325801bd | 7178 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
a06ea964 NC |
7179 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
7180 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
7181 | ||
7182 | if (fixp->fx_pcrel) | |
7183 | { | |
7184 | if (section->use_rela_p) | |
7185 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
7186 | else | |
7187 | fixp->fx_offset = reloc->address; | |
7188 | } | |
7189 | reloc->addend = fixp->fx_offset; | |
7190 | ||
7191 | code = fixp->fx_r_type; | |
7192 | switch (code) | |
7193 | { | |
7194 | case BFD_RELOC_16: | |
7195 | if (fixp->fx_pcrel) | |
7196 | code = BFD_RELOC_16_PCREL; | |
7197 | break; | |
7198 | ||
7199 | case BFD_RELOC_32: | |
7200 | if (fixp->fx_pcrel) | |
7201 | code = BFD_RELOC_32_PCREL; | |
7202 | break; | |
7203 | ||
7204 | case BFD_RELOC_64: | |
7205 | if (fixp->fx_pcrel) | |
7206 | code = BFD_RELOC_64_PCREL; | |
7207 | break; | |
7208 | ||
7209 | default: | |
7210 | break; | |
7211 | } | |
7212 | ||
7213 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
7214 | if (reloc->howto == NULL) | |
7215 | { | |
7216 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
7217 | _ | |
7218 | ("cannot represent %s relocation in this object file format"), | |
7219 | bfd_get_reloc_code_name (code)); | |
7220 | return NULL; | |
7221 | } | |
7222 | ||
7223 | return reloc; | |
7224 | } | |
7225 | ||
7226 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ | |
7227 | ||
7228 | void | |
7229 | cons_fix_new_aarch64 (fragS * frag, int where, int size, expressionS * exp) | |
7230 | { | |
7231 | bfd_reloc_code_real_type type; | |
7232 | int pcrel = 0; | |
7233 | ||
7234 | /* Pick a reloc. | |
7235 | FIXME: @@ Should look at CPU word size. */ | |
7236 | switch (size) | |
7237 | { | |
7238 | case 1: | |
7239 | type = BFD_RELOC_8; | |
7240 | break; | |
7241 | case 2: | |
7242 | type = BFD_RELOC_16; | |
7243 | break; | |
7244 | case 4: | |
7245 | type = BFD_RELOC_32; | |
7246 | break; | |
7247 | case 8: | |
7248 | type = BFD_RELOC_64; | |
7249 | break; | |
7250 | default: | |
7251 | as_bad (_("cannot do %u-byte relocation"), size); | |
7252 | type = BFD_RELOC_UNUSED; | |
7253 | break; | |
7254 | } | |
7255 | ||
7256 | fix_new_exp (frag, where, (int) size, exp, pcrel, type); | |
7257 | } | |
7258 | ||
7259 | int | |
7260 | aarch64_force_relocation (struct fix *fixp) | |
7261 | { | |
7262 | switch (fixp->fx_r_type) | |
7263 | { | |
7264 | case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP: | |
7265 | /* Perform these "immediate" internal relocations | |
7266 | even if the symbol is extern or weak. */ | |
7267 | return 0; | |
7268 | ||
a6bb11b2 | 7269 | case BFD_RELOC_AARCH64_LD_GOT_LO12_NC: |
f09c556a JW |
7270 | case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC: |
7271 | case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC: | |
a6bb11b2 YZ |
7272 | /* Pseudo relocs that need to be fixed up according to |
7273 | ilp32_p. */ | |
7274 | return 0; | |
7275 | ||
2c0a3565 MS |
7276 | case BFD_RELOC_AARCH64_ADD_LO12: |
7277 | case BFD_RELOC_AARCH64_ADR_GOT_PAGE: | |
7278 | case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL: | |
7279 | case BFD_RELOC_AARCH64_ADR_HI21_PCREL: | |
7280 | case BFD_RELOC_AARCH64_GOT_LD_PREL19: | |
7281 | case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC: | |
3d715ce4 | 7282 | case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14: |
87f5fbcc | 7283 | case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15: |
a921b5bd | 7284 | case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15: |
2c0a3565 MS |
7285 | case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC: |
7286 | case BFD_RELOC_AARCH64_LDST128_LO12: | |
7287 | case BFD_RELOC_AARCH64_LDST16_LO12: | |
7288 | case BFD_RELOC_AARCH64_LDST32_LO12: | |
7289 | case BFD_RELOC_AARCH64_LDST64_LO12: | |
7290 | case BFD_RELOC_AARCH64_LDST8_LO12: | |
7291 | case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC: | |
7292 | case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21: | |
389b8029 | 7293 | case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21: |
2c0a3565 MS |
7294 | case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC: |
7295 | case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC: | |
1ada945d | 7296 | case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19: |
43a357f9 RL |
7297 | case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC: |
7298 | case BFD_RELOC_AARCH64_TLSDESC_OFF_G1: | |
a06ea964 | 7299 | case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC: |
2c0a3565 | 7300 | case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21: |
3c12b054 | 7301 | case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21: |
3e8286c0 | 7302 | case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC: |
1aa66fb1 | 7303 | case BFD_RELOC_AARCH64_TLSGD_MOVW_G1: |
a06ea964 | 7304 | case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: |
a6bb11b2 | 7305 | case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC: |
2c0a3565 | 7306 | case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: |
043bf05a | 7307 | case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19: |
3b957e5b RL |
7308 | case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC: |
7309 | case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1: | |
7310 | case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12: | |
70151fb5 | 7311 | case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12: |
13289c10 | 7312 | case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC: |
a12fad50 | 7313 | case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC: |
1107e076 | 7314 | case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21: |
6c37fedc | 7315 | case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21: |
4c562523 JW |
7316 | case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12: |
7317 | case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC: | |
7318 | case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12: | |
7319 | case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC: | |
7320 | case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12: | |
7321 | case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC: | |
7322 | case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12: | |
7323 | case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC: | |
49df5539 JW |
7324 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0: |
7325 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC: | |
7326 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1: | |
7327 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC: | |
7328 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2: | |
a06ea964 | 7329 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12: |
2c0a3565 | 7330 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12: |
a06ea964 | 7331 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC: |
a06ea964 NC |
7332 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0: |
7333 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC: | |
2c0a3565 MS |
7334 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1: |
7335 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC: | |
7336 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2: | |
a06ea964 NC |
7337 | /* Always leave these relocations for the linker. */ |
7338 | return 1; | |
7339 | ||
7340 | default: | |
7341 | break; | |
7342 | } | |
7343 | ||
7344 | return generic_force_reloc (fixp); | |
7345 | } | |
7346 | ||
7347 | #ifdef OBJ_ELF | |
7348 | ||
7349 | const char * | |
7350 | elf64_aarch64_target_format (void) | |
7351 | { | |
a75cf613 ES |
7352 | if (strcmp (TARGET_OS, "cloudabi") == 0) |
7353 | { | |
7354 | /* FIXME: What to do for ilp32_p ? */ | |
7355 | return target_big_endian ? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi"; | |
7356 | } | |
a06ea964 | 7357 | if (target_big_endian) |
cec5225b | 7358 | return ilp32_p ? "elf32-bigaarch64" : "elf64-bigaarch64"; |
a06ea964 | 7359 | else |
cec5225b | 7360 | return ilp32_p ? "elf32-littleaarch64" : "elf64-littleaarch64"; |
a06ea964 NC |
7361 | } |
7362 | ||
7363 | void | |
7364 | aarch64elf_frob_symbol (symbolS * symp, int *puntp) | |
7365 | { | |
7366 | elf_frob_symbol (symp, puntp); | |
7367 | } | |
7368 | #endif | |
7369 | ||
7370 | /* MD interface: Finalization. */ | |
7371 | ||
7372 | /* A good place to do this, although this was probably not intended | |
7373 | for this kind of use. We need to dump the literal pool before | |
7374 | references are made to a null symbol pointer. */ | |
7375 | ||
7376 | void | |
7377 | aarch64_cleanup (void) | |
7378 | { | |
7379 | literal_pool *pool; | |
7380 | ||
7381 | for (pool = list_of_pools; pool; pool = pool->next) | |
7382 | { | |
7383 | /* Put it at the end of the relevant section. */ | |
7384 | subseg_set (pool->section, pool->sub_section); | |
7385 | s_ltorg (0); | |
7386 | } | |
7387 | } | |
7388 | ||
7389 | #ifdef OBJ_ELF | |
7390 | /* Remove any excess mapping symbols generated for alignment frags in | |
7391 | SEC. We may have created a mapping symbol before a zero byte | |
7392 | alignment; remove it if there's a mapping symbol after the | |
7393 | alignment. */ | |
7394 | static void | |
7395 | check_mapping_symbols (bfd * abfd ATTRIBUTE_UNUSED, asection * sec, | |
7396 | void *dummy ATTRIBUTE_UNUSED) | |
7397 | { | |
7398 | segment_info_type *seginfo = seg_info (sec); | |
7399 | fragS *fragp; | |
7400 | ||
7401 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
7402 | return; | |
7403 | ||
7404 | for (fragp = seginfo->frchainP->frch_root; | |
7405 | fragp != NULL; fragp = fragp->fr_next) | |
7406 | { | |
7407 | symbolS *sym = fragp->tc_frag_data.last_map; | |
7408 | fragS *next = fragp->fr_next; | |
7409 | ||
7410 | /* Variable-sized frags have been converted to fixed size by | |
7411 | this point. But if this was variable-sized to start with, | |
7412 | there will be a fixed-size frag after it. So don't handle | |
7413 | next == NULL. */ | |
7414 | if (sym == NULL || next == NULL) | |
7415 | continue; | |
7416 | ||
7417 | if (S_GET_VALUE (sym) < next->fr_address) | |
7418 | /* Not at the end of this frag. */ | |
7419 | continue; | |
7420 | know (S_GET_VALUE (sym) == next->fr_address); | |
7421 | ||
7422 | do | |
7423 | { | |
7424 | if (next->tc_frag_data.first_map != NULL) | |
7425 | { | |
7426 | /* Next frag starts with a mapping symbol. Discard this | |
7427 | one. */ | |
7428 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
7429 | break; | |
7430 | } | |
7431 | ||
7432 | if (next->fr_next == NULL) | |
7433 | { | |
7434 | /* This mapping symbol is at the end of the section. Discard | |
7435 | it. */ | |
7436 | know (next->fr_fix == 0 && next->fr_var == 0); | |
7437 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
7438 | break; | |
7439 | } | |
7440 | ||
7441 | /* As long as we have empty frags without any mapping symbols, | |
7442 | keep looking. */ | |
7443 | /* If the next frag is non-empty and does not start with a | |
7444 | mapping symbol, then this mapping symbol is required. */ | |
7445 | if (next->fr_address != next->fr_next->fr_address) | |
7446 | break; | |
7447 | ||
7448 | next = next->fr_next; | |
7449 | } | |
7450 | while (next != NULL); | |
7451 | } | |
7452 | } | |
7453 | #endif | |
7454 | ||
7455 | /* Adjust the symbol table. */ | |
7456 | ||
7457 | void | |
7458 | aarch64_adjust_symtab (void) | |
7459 | { | |
7460 | #ifdef OBJ_ELF | |
7461 | /* Remove any overlapping mapping symbols generated by alignment frags. */ | |
7462 | bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); | |
7463 | /* Now do generic ELF adjustments. */ | |
7464 | elf_adjust_symtab (); | |
7465 | #endif | |
7466 | } | |
7467 | ||
7468 | static void | |
7469 | checked_hash_insert (struct hash_control *table, const char *key, void *value) | |
7470 | { | |
7471 | const char *hash_err; | |
7472 | ||
7473 | hash_err = hash_insert (table, key, value); | |
7474 | if (hash_err) | |
7475 | printf ("Internal Error: Can't hash %s\n", key); | |
7476 | } | |
7477 | ||
7478 | static void | |
7479 | fill_instruction_hash_table (void) | |
7480 | { | |
7481 | aarch64_opcode *opcode = aarch64_opcode_table; | |
7482 | ||
7483 | while (opcode->name != NULL) | |
7484 | { | |
7485 | templates *templ, *new_templ; | |
7486 | templ = hash_find (aarch64_ops_hsh, opcode->name); | |
7487 | ||
add39d23 | 7488 | new_templ = XNEW (templates); |
a06ea964 NC |
7489 | new_templ->opcode = opcode; |
7490 | new_templ->next = NULL; | |
7491 | ||
7492 | if (!templ) | |
7493 | checked_hash_insert (aarch64_ops_hsh, opcode->name, (void *) new_templ); | |
7494 | else | |
7495 | { | |
7496 | new_templ->next = templ->next; | |
7497 | templ->next = new_templ; | |
7498 | } | |
7499 | ++opcode; | |
7500 | } | |
7501 | } | |
7502 | ||
7503 | static inline void | |
7504 | convert_to_upper (char *dst, const char *src, size_t num) | |
7505 | { | |
7506 | unsigned int i; | |
7507 | for (i = 0; i < num && *src != '\0'; ++i, ++dst, ++src) | |
7508 | *dst = TOUPPER (*src); | |
7509 | *dst = '\0'; | |
7510 | } | |
7511 | ||
7512 | /* Assume STR point to a lower-case string, allocate, convert and return | |
7513 | the corresponding upper-case string. */ | |
7514 | static inline const char* | |
7515 | get_upper_str (const char *str) | |
7516 | { | |
7517 | char *ret; | |
7518 | size_t len = strlen (str); | |
325801bd | 7519 | ret = XNEWVEC (char, len + 1); |
a06ea964 NC |
7520 | convert_to_upper (ret, str, len); |
7521 | return ret; | |
7522 | } | |
7523 | ||
7524 | /* MD interface: Initialization. */ | |
7525 | ||
7526 | void | |
7527 | md_begin (void) | |
7528 | { | |
7529 | unsigned mach; | |
7530 | unsigned int i; | |
7531 | ||
7532 | if ((aarch64_ops_hsh = hash_new ()) == NULL | |
7533 | || (aarch64_cond_hsh = hash_new ()) == NULL | |
7534 | || (aarch64_shift_hsh = hash_new ()) == NULL | |
7535 | || (aarch64_sys_regs_hsh = hash_new ()) == NULL | |
7536 | || (aarch64_pstatefield_hsh = hash_new ()) == NULL | |
7537 | || (aarch64_sys_regs_ic_hsh = hash_new ()) == NULL | |
7538 | || (aarch64_sys_regs_dc_hsh = hash_new ()) == NULL | |
7539 | || (aarch64_sys_regs_at_hsh = hash_new ()) == NULL | |
7540 | || (aarch64_sys_regs_tlbi_hsh = hash_new ()) == NULL | |
7541 | || (aarch64_reg_hsh = hash_new ()) == NULL | |
7542 | || (aarch64_barrier_opt_hsh = hash_new ()) == NULL | |
7543 | || (aarch64_nzcv_hsh = hash_new ()) == NULL | |
1e6f4800 MW |
7544 | || (aarch64_pldop_hsh = hash_new ()) == NULL |
7545 | || (aarch64_hint_opt_hsh = hash_new ()) == NULL) | |
a06ea964 NC |
7546 | as_fatal (_("virtual memory exhausted")); |
7547 | ||
7548 | fill_instruction_hash_table (); | |
7549 | ||
7550 | for (i = 0; aarch64_sys_regs[i].name != NULL; ++i) | |
7551 | checked_hash_insert (aarch64_sys_regs_hsh, aarch64_sys_regs[i].name, | |
7552 | (void *) (aarch64_sys_regs + i)); | |
7553 | ||
7554 | for (i = 0; aarch64_pstatefields[i].name != NULL; ++i) | |
7555 | checked_hash_insert (aarch64_pstatefield_hsh, | |
7556 | aarch64_pstatefields[i].name, | |
7557 | (void *) (aarch64_pstatefields + i)); | |
7558 | ||
875880c6 | 7559 | for (i = 0; aarch64_sys_regs_ic[i].name != NULL; i++) |
a06ea964 | 7560 | checked_hash_insert (aarch64_sys_regs_ic_hsh, |
875880c6 | 7561 | aarch64_sys_regs_ic[i].name, |
a06ea964 NC |
7562 | (void *) (aarch64_sys_regs_ic + i)); |
7563 | ||
875880c6 | 7564 | for (i = 0; aarch64_sys_regs_dc[i].name != NULL; i++) |
a06ea964 | 7565 | checked_hash_insert (aarch64_sys_regs_dc_hsh, |
875880c6 | 7566 | aarch64_sys_regs_dc[i].name, |
a06ea964 NC |
7567 | (void *) (aarch64_sys_regs_dc + i)); |
7568 | ||
875880c6 | 7569 | for (i = 0; aarch64_sys_regs_at[i].name != NULL; i++) |
a06ea964 | 7570 | checked_hash_insert (aarch64_sys_regs_at_hsh, |
875880c6 | 7571 | aarch64_sys_regs_at[i].name, |
a06ea964 NC |
7572 | (void *) (aarch64_sys_regs_at + i)); |
7573 | ||
875880c6 | 7574 | for (i = 0; aarch64_sys_regs_tlbi[i].name != NULL; i++) |
a06ea964 | 7575 | checked_hash_insert (aarch64_sys_regs_tlbi_hsh, |
875880c6 | 7576 | aarch64_sys_regs_tlbi[i].name, |
a06ea964 NC |
7577 | (void *) (aarch64_sys_regs_tlbi + i)); |
7578 | ||
7579 | for (i = 0; i < ARRAY_SIZE (reg_names); i++) | |
7580 | checked_hash_insert (aarch64_reg_hsh, reg_names[i].name, | |
7581 | (void *) (reg_names + i)); | |
7582 | ||
7583 | for (i = 0; i < ARRAY_SIZE (nzcv_names); i++) | |
7584 | checked_hash_insert (aarch64_nzcv_hsh, nzcv_names[i].template, | |
7585 | (void *) (nzcv_names + i)); | |
7586 | ||
7587 | for (i = 0; aarch64_operand_modifiers[i].name != NULL; i++) | |
7588 | { | |
7589 | const char *name = aarch64_operand_modifiers[i].name; | |
7590 | checked_hash_insert (aarch64_shift_hsh, name, | |
7591 | (void *) (aarch64_operand_modifiers + i)); | |
7592 | /* Also hash the name in the upper case. */ | |
7593 | checked_hash_insert (aarch64_shift_hsh, get_upper_str (name), | |
7594 | (void *) (aarch64_operand_modifiers + i)); | |
7595 | } | |
7596 | ||
7597 | for (i = 0; i < ARRAY_SIZE (aarch64_conds); i++) | |
7598 | { | |
7599 | unsigned int j; | |
7600 | /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are | |
7601 | the same condition code. */ | |
7602 | for (j = 0; j < ARRAY_SIZE (aarch64_conds[i].names); ++j) | |
7603 | { | |
7604 | const char *name = aarch64_conds[i].names[j]; | |
7605 | if (name == NULL) | |
7606 | break; | |
7607 | checked_hash_insert (aarch64_cond_hsh, name, | |
7608 | (void *) (aarch64_conds + i)); | |
7609 | /* Also hash the name in the upper case. */ | |
7610 | checked_hash_insert (aarch64_cond_hsh, get_upper_str (name), | |
7611 | (void *) (aarch64_conds + i)); | |
7612 | } | |
7613 | } | |
7614 | ||
7615 | for (i = 0; i < ARRAY_SIZE (aarch64_barrier_options); i++) | |
7616 | { | |
7617 | const char *name = aarch64_barrier_options[i].name; | |
7618 | /* Skip xx00 - the unallocated values of option. */ | |
7619 | if ((i & 0x3) == 0) | |
7620 | continue; | |
7621 | checked_hash_insert (aarch64_barrier_opt_hsh, name, | |
7622 | (void *) (aarch64_barrier_options + i)); | |
7623 | /* Also hash the name in the upper case. */ | |
7624 | checked_hash_insert (aarch64_barrier_opt_hsh, get_upper_str (name), | |
7625 | (void *) (aarch64_barrier_options + i)); | |
7626 | } | |
7627 | ||
7628 | for (i = 0; i < ARRAY_SIZE (aarch64_prfops); i++) | |
7629 | { | |
7630 | const char* name = aarch64_prfops[i].name; | |
a1ccaec9 YZ |
7631 | /* Skip the unallocated hint encodings. */ |
7632 | if (name == NULL) | |
a06ea964 NC |
7633 | continue; |
7634 | checked_hash_insert (aarch64_pldop_hsh, name, | |
7635 | (void *) (aarch64_prfops + i)); | |
7636 | /* Also hash the name in the upper case. */ | |
7637 | checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name), | |
7638 | (void *) (aarch64_prfops + i)); | |
7639 | } | |
7640 | ||
1e6f4800 MW |
7641 | for (i = 0; aarch64_hint_options[i].name != NULL; i++) |
7642 | { | |
7643 | const char* name = aarch64_hint_options[i].name; | |
7644 | ||
7645 | checked_hash_insert (aarch64_hint_opt_hsh, name, | |
7646 | (void *) (aarch64_hint_options + i)); | |
7647 | /* Also hash the name in the upper case. */ | |
7648 | checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name), | |
7649 | (void *) (aarch64_hint_options + i)); | |
7650 | } | |
7651 | ||
a06ea964 NC |
7652 | /* Set the cpu variant based on the command-line options. */ |
7653 | if (!mcpu_cpu_opt) | |
7654 | mcpu_cpu_opt = march_cpu_opt; | |
7655 | ||
7656 | if (!mcpu_cpu_opt) | |
7657 | mcpu_cpu_opt = &cpu_default; | |
7658 | ||
7659 | cpu_variant = *mcpu_cpu_opt; | |
7660 | ||
7661 | /* Record the CPU type. */ | |
cec5225b | 7662 | mach = ilp32_p ? bfd_mach_aarch64_ilp32 : bfd_mach_aarch64; |
a06ea964 NC |
7663 | |
7664 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
7665 | } | |
7666 | ||
7667 | /* Command line processing. */ | |
7668 | ||
7669 | const char *md_shortopts = "m:"; | |
7670 | ||
7671 | #ifdef AARCH64_BI_ENDIAN | |
7672 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
7673 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
7674 | #else | |
7675 | #if TARGET_BYTES_BIG_ENDIAN | |
7676 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
7677 | #else | |
7678 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
7679 | #endif | |
7680 | #endif | |
7681 | ||
7682 | struct option md_longopts[] = { | |
7683 | #ifdef OPTION_EB | |
7684 | {"EB", no_argument, NULL, OPTION_EB}, | |
7685 | #endif | |
7686 | #ifdef OPTION_EL | |
7687 | {"EL", no_argument, NULL, OPTION_EL}, | |
7688 | #endif | |
7689 | {NULL, no_argument, NULL, 0} | |
7690 | }; | |
7691 | ||
7692 | size_t md_longopts_size = sizeof (md_longopts); | |
7693 | ||
7694 | struct aarch64_option_table | |
7695 | { | |
e0471c16 TS |
7696 | const char *option; /* Option name to match. */ |
7697 | const char *help; /* Help information. */ | |
a06ea964 NC |
7698 | int *var; /* Variable to change. */ |
7699 | int value; /* What to change it to. */ | |
7700 | char *deprecated; /* If non-null, print this message. */ | |
7701 | }; | |
7702 | ||
7703 | static struct aarch64_option_table aarch64_opts[] = { | |
7704 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
7705 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
7706 | NULL}, | |
7707 | #ifdef DEBUG_AARCH64 | |
7708 | {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump, 1, NULL}, | |
7709 | #endif /* DEBUG_AARCH64 */ | |
7710 | {"mverbose-error", N_("output verbose error messages"), &verbose_error_p, 1, | |
7711 | NULL}, | |
a52e6fd3 YZ |
7712 | {"mno-verbose-error", N_("do not output verbose error messages"), |
7713 | &verbose_error_p, 0, NULL}, | |
a06ea964 NC |
7714 | {NULL, NULL, NULL, 0, NULL} |
7715 | }; | |
7716 | ||
7717 | struct aarch64_cpu_option_table | |
7718 | { | |
e0471c16 | 7719 | const char *name; |
a06ea964 NC |
7720 | const aarch64_feature_set value; |
7721 | /* The canonical name of the CPU, or NULL to use NAME converted to upper | |
7722 | case. */ | |
7723 | const char *canonical_name; | |
7724 | }; | |
7725 | ||
7726 | /* This list should, at a minimum, contain all the cpu names | |
7727 | recognized by GCC. */ | |
7728 | static const struct aarch64_cpu_option_table aarch64_cpus[] = { | |
7729 | {"all", AARCH64_ANY, NULL}, | |
9c352f1c JG |
7730 | {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8, |
7731 | AARCH64_FEATURE_CRC), "Cortex-A35"}, | |
aa31c464 JW |
7732 | {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8, |
7733 | AARCH64_FEATURE_CRC), "Cortex-A53"}, | |
7734 | {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8, | |
7735 | AARCH64_FEATURE_CRC), "Cortex-A57"}, | |
2abdd192 JW |
7736 | {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8, |
7737 | AARCH64_FEATURE_CRC), "Cortex-A72"}, | |
1aa70332 KT |
7738 | {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8, |
7739 | AARCH64_FEATURE_CRC), "Cortex-A73"}, | |
2412d878 EM |
7740 | {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8, |
7741 | AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO), | |
7742 | "Samsung Exynos M1"}, | |
6b21c2bf JW |
7743 | {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8, |
7744 | AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO), | |
7745 | "Qualcomm QDF24XX"}, | |
faade851 JW |
7746 | {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8, |
7747 | AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO), | |
7748 | "Cavium ThunderX"}, | |
9f99c22e VP |
7749 | {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1, |
7750 | AARCH64_FEATURE_CRYPTO), | |
0a8be2fe | 7751 | "Broadcom Vulcan"}, |
070cb956 PT |
7752 | /* The 'xgene-1' name is an older name for 'xgene1', which was used |
7753 | in earlier releases and is superseded by 'xgene1' in all | |
7754 | tools. */ | |
9877c63c | 7755 | {"xgene-1", AARCH64_ARCH_V8, "APM X-Gene 1"}, |
070cb956 | 7756 | {"xgene1", AARCH64_ARCH_V8, "APM X-Gene 1"}, |
aa31c464 JW |
7757 | {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8, |
7758 | AARCH64_FEATURE_CRC), "APM X-Gene 2"}, | |
a06ea964 NC |
7759 | {"generic", AARCH64_ARCH_V8, NULL}, |
7760 | ||
a06ea964 NC |
7761 | {NULL, AARCH64_ARCH_NONE, NULL} |
7762 | }; | |
7763 | ||
7764 | struct aarch64_arch_option_table | |
7765 | { | |
e0471c16 | 7766 | const char *name; |
a06ea964 NC |
7767 | const aarch64_feature_set value; |
7768 | }; | |
7769 | ||
7770 | /* This list should, at a minimum, contain all the architecture names | |
7771 | recognized by GCC. */ | |
7772 | static const struct aarch64_arch_option_table aarch64_archs[] = { | |
7773 | {"all", AARCH64_ANY}, | |
5a1ad39d | 7774 | {"armv8-a", AARCH64_ARCH_V8}, |
88f0ea34 | 7775 | {"armv8.1-a", AARCH64_ARCH_V8_1}, |
acb787b0 | 7776 | {"armv8.2-a", AARCH64_ARCH_V8_2}, |
a06ea964 NC |
7777 | {NULL, AARCH64_ARCH_NONE} |
7778 | }; | |
7779 | ||
7780 | /* ISA extensions. */ | |
7781 | struct aarch64_option_cpu_value_table | |
7782 | { | |
e0471c16 | 7783 | const char *name; |
a06ea964 | 7784 | const aarch64_feature_set value; |
93d8990c | 7785 | const aarch64_feature_set require; /* Feature dependencies. */ |
a06ea964 NC |
7786 | }; |
7787 | ||
7788 | static const struct aarch64_option_cpu_value_table aarch64_features[] = { | |
93d8990c SN |
7789 | {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0), |
7790 | AARCH64_ARCH_NONE}, | |
7791 | {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0), | |
7792 | AARCH64_ARCH_NONE}, | |
7793 | {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0), | |
7794 | AARCH64_ARCH_NONE}, | |
7795 | {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0), | |
7796 | AARCH64_ARCH_NONE}, | |
7797 | {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0), | |
7798 | AARCH64_ARCH_NONE}, | |
7799 | {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN, 0), | |
7800 | AARCH64_ARCH_NONE}, | |
7801 | {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0), | |
7802 | AARCH64_ARCH_NONE}, | |
7803 | {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0), | |
7804 | AARCH64_ARCH_NONE}, | |
7805 | {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0), | |
7806 | AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)}, | |
7807 | {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16, 0), | |
7808 | AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)}, | |
7809 | {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0), | |
7810 | AARCH64_ARCH_NONE}, | |
7811 | {NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE}, | |
a06ea964 NC |
7812 | }; |
7813 | ||
7814 | struct aarch64_long_option_table | |
7815 | { | |
e0471c16 TS |
7816 | const char *option; /* Substring to match. */ |
7817 | const char *help; /* Help information. */ | |
17b9d67d | 7818 | int (*func) (const char *subopt); /* Function to decode sub-option. */ |
a06ea964 NC |
7819 | char *deprecated; /* If non-null, print this message. */ |
7820 | }; | |
7821 | ||
93d8990c SN |
7822 | /* Transitive closure of features depending on set. */ |
7823 | static aarch64_feature_set | |
7824 | aarch64_feature_disable_set (aarch64_feature_set set) | |
7825 | { | |
7826 | const struct aarch64_option_cpu_value_table *opt; | |
7827 | aarch64_feature_set prev = 0; | |
7828 | ||
7829 | while (prev != set) { | |
7830 | prev = set; | |
7831 | for (opt = aarch64_features; opt->name != NULL; opt++) | |
7832 | if (AARCH64_CPU_HAS_ANY_FEATURES (opt->require, set)) | |
7833 | AARCH64_MERGE_FEATURE_SETS (set, set, opt->value); | |
7834 | } | |
7835 | return set; | |
7836 | } | |
7837 | ||
7838 | /* Transitive closure of dependencies of set. */ | |
7839 | static aarch64_feature_set | |
7840 | aarch64_feature_enable_set (aarch64_feature_set set) | |
7841 | { | |
7842 | const struct aarch64_option_cpu_value_table *opt; | |
7843 | aarch64_feature_set prev = 0; | |
7844 | ||
7845 | while (prev != set) { | |
7846 | prev = set; | |
7847 | for (opt = aarch64_features; opt->name != NULL; opt++) | |
7848 | if (AARCH64_CPU_HAS_FEATURE (set, opt->value)) | |
7849 | AARCH64_MERGE_FEATURE_SETS (set, set, opt->require); | |
7850 | } | |
7851 | return set; | |
7852 | } | |
7853 | ||
a06ea964 | 7854 | static int |
82b8a785 | 7855 | aarch64_parse_features (const char *str, const aarch64_feature_set **opt_p, |
ae527cd8 | 7856 | bfd_boolean ext_only) |
a06ea964 NC |
7857 | { |
7858 | /* We insist on extensions being added before being removed. We achieve | |
7859 | this by using the ADDING_VALUE variable to indicate whether we are | |
7860 | adding an extension (1) or removing it (0) and only allowing it to | |
7861 | change in the order -1 -> 1 -> 0. */ | |
7862 | int adding_value = -1; | |
325801bd | 7863 | aarch64_feature_set *ext_set = XNEW (aarch64_feature_set); |
a06ea964 NC |
7864 | |
7865 | /* Copy the feature set, so that we can modify it. */ | |
7866 | *ext_set = **opt_p; | |
7867 | *opt_p = ext_set; | |
7868 | ||
7869 | while (str != NULL && *str != 0) | |
7870 | { | |
7871 | const struct aarch64_option_cpu_value_table *opt; | |
82b8a785 | 7872 | const char *ext = NULL; |
a06ea964 NC |
7873 | int optlen; |
7874 | ||
ae527cd8 | 7875 | if (!ext_only) |
a06ea964 | 7876 | { |
ae527cd8 JB |
7877 | if (*str != '+') |
7878 | { | |
7879 | as_bad (_("invalid architectural extension")); | |
7880 | return 0; | |
7881 | } | |
a06ea964 | 7882 | |
ae527cd8 JB |
7883 | ext = strchr (++str, '+'); |
7884 | } | |
a06ea964 NC |
7885 | |
7886 | if (ext != NULL) | |
7887 | optlen = ext - str; | |
7888 | else | |
7889 | optlen = strlen (str); | |
7890 | ||
7891 | if (optlen >= 2 && strncmp (str, "no", 2) == 0) | |
7892 | { | |
7893 | if (adding_value != 0) | |
7894 | adding_value = 0; | |
7895 | optlen -= 2; | |
7896 | str += 2; | |
7897 | } | |
7898 | else if (optlen > 0) | |
7899 | { | |
7900 | if (adding_value == -1) | |
7901 | adding_value = 1; | |
7902 | else if (adding_value != 1) | |
7903 | { | |
7904 | as_bad (_("must specify extensions to add before specifying " | |
7905 | "those to remove")); | |
7906 | return FALSE; | |
7907 | } | |
7908 | } | |
7909 | ||
7910 | if (optlen == 0) | |
7911 | { | |
7912 | as_bad (_("missing architectural extension")); | |
7913 | return 0; | |
7914 | } | |
7915 | ||
7916 | gas_assert (adding_value != -1); | |
7917 | ||
7918 | for (opt = aarch64_features; opt->name != NULL; opt++) | |
7919 | if (strncmp (opt->name, str, optlen) == 0) | |
7920 | { | |
93d8990c SN |
7921 | aarch64_feature_set set; |
7922 | ||
a06ea964 NC |
7923 | /* Add or remove the extension. */ |
7924 | if (adding_value) | |
93d8990c SN |
7925 | { |
7926 | set = aarch64_feature_enable_set (opt->value); | |
7927 | AARCH64_MERGE_FEATURE_SETS (*ext_set, *ext_set, set); | |
7928 | } | |
a06ea964 | 7929 | else |
93d8990c SN |
7930 | { |
7931 | set = aarch64_feature_disable_set (opt->value); | |
7932 | AARCH64_CLEAR_FEATURE (*ext_set, *ext_set, set); | |
7933 | } | |
a06ea964 NC |
7934 | break; |
7935 | } | |
7936 | ||
7937 | if (opt->name == NULL) | |
7938 | { | |
7939 | as_bad (_("unknown architectural extension `%s'"), str); | |
7940 | return 0; | |
7941 | } | |
7942 | ||
7943 | str = ext; | |
7944 | }; | |
7945 | ||
7946 | return 1; | |
7947 | } | |
7948 | ||
7949 | static int | |
17b9d67d | 7950 | aarch64_parse_cpu (const char *str) |
a06ea964 NC |
7951 | { |
7952 | const struct aarch64_cpu_option_table *opt; | |
82b8a785 | 7953 | const char *ext = strchr (str, '+'); |
a06ea964 NC |
7954 | size_t optlen; |
7955 | ||
7956 | if (ext != NULL) | |
7957 | optlen = ext - str; | |
7958 | else | |
7959 | optlen = strlen (str); | |
7960 | ||
7961 | if (optlen == 0) | |
7962 | { | |
7963 | as_bad (_("missing cpu name `%s'"), str); | |
7964 | return 0; | |
7965 | } | |
7966 | ||
7967 | for (opt = aarch64_cpus; opt->name != NULL; opt++) | |
7968 | if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0) | |
7969 | { | |
7970 | mcpu_cpu_opt = &opt->value; | |
7971 | if (ext != NULL) | |
ae527cd8 | 7972 | return aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE); |
a06ea964 NC |
7973 | |
7974 | return 1; | |
7975 | } | |
7976 | ||
7977 | as_bad (_("unknown cpu `%s'"), str); | |
7978 | return 0; | |
7979 | } | |
7980 | ||
7981 | static int | |
17b9d67d | 7982 | aarch64_parse_arch (const char *str) |
a06ea964 NC |
7983 | { |
7984 | const struct aarch64_arch_option_table *opt; | |
82b8a785 | 7985 | const char *ext = strchr (str, '+'); |
a06ea964 NC |
7986 | size_t optlen; |
7987 | ||
7988 | if (ext != NULL) | |
7989 | optlen = ext - str; | |
7990 | else | |
7991 | optlen = strlen (str); | |
7992 | ||
7993 | if (optlen == 0) | |
7994 | { | |
7995 | as_bad (_("missing architecture name `%s'"), str); | |
7996 | return 0; | |
7997 | } | |
7998 | ||
7999 | for (opt = aarch64_archs; opt->name != NULL; opt++) | |
8000 | if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0) | |
8001 | { | |
8002 | march_cpu_opt = &opt->value; | |
8003 | if (ext != NULL) | |
ae527cd8 | 8004 | return aarch64_parse_features (ext, &march_cpu_opt, FALSE); |
a06ea964 NC |
8005 | |
8006 | return 1; | |
8007 | } | |
8008 | ||
8009 | as_bad (_("unknown architecture `%s'\n"), str); | |
8010 | return 0; | |
8011 | } | |
8012 | ||
69091a2c YZ |
8013 | /* ABIs. */ |
8014 | struct aarch64_option_abi_value_table | |
8015 | { | |
e0471c16 | 8016 | const char *name; |
69091a2c YZ |
8017 | enum aarch64_abi_type value; |
8018 | }; | |
8019 | ||
8020 | static const struct aarch64_option_abi_value_table aarch64_abis[] = { | |
8021 | {"ilp32", AARCH64_ABI_ILP32}, | |
8022 | {"lp64", AARCH64_ABI_LP64}, | |
69091a2c YZ |
8023 | }; |
8024 | ||
8025 | static int | |
17b9d67d | 8026 | aarch64_parse_abi (const char *str) |
69091a2c | 8027 | { |
5703197e | 8028 | unsigned int i; |
69091a2c | 8029 | |
5703197e | 8030 | if (str[0] == '\0') |
69091a2c YZ |
8031 | { |
8032 | as_bad (_("missing abi name `%s'"), str); | |
8033 | return 0; | |
8034 | } | |
8035 | ||
5703197e TS |
8036 | for (i = 0; i < ARRAY_SIZE (aarch64_abis); i++) |
8037 | if (strcmp (str, aarch64_abis[i].name) == 0) | |
69091a2c | 8038 | { |
5703197e | 8039 | aarch64_abi = aarch64_abis[i].value; |
69091a2c YZ |
8040 | return 1; |
8041 | } | |
8042 | ||
8043 | as_bad (_("unknown abi `%s'\n"), str); | |
8044 | return 0; | |
8045 | } | |
8046 | ||
a06ea964 | 8047 | static struct aarch64_long_option_table aarch64_long_opts[] = { |
69091a2c YZ |
8048 | #ifdef OBJ_ELF |
8049 | {"mabi=", N_("<abi name>\t specify for ABI <abi name>"), | |
8050 | aarch64_parse_abi, NULL}, | |
8051 | #endif /* OBJ_ELF */ | |
a06ea964 NC |
8052 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), |
8053 | aarch64_parse_cpu, NULL}, | |
8054 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
8055 | aarch64_parse_arch, NULL}, | |
8056 | {NULL, NULL, 0, NULL} | |
8057 | }; | |
8058 | ||
8059 | int | |
17b9d67d | 8060 | md_parse_option (int c, const char *arg) |
a06ea964 NC |
8061 | { |
8062 | struct aarch64_option_table *opt; | |
8063 | struct aarch64_long_option_table *lopt; | |
8064 | ||
8065 | switch (c) | |
8066 | { | |
8067 | #ifdef OPTION_EB | |
8068 | case OPTION_EB: | |
8069 | target_big_endian = 1; | |
8070 | break; | |
8071 | #endif | |
8072 | ||
8073 | #ifdef OPTION_EL | |
8074 | case OPTION_EL: | |
8075 | target_big_endian = 0; | |
8076 | break; | |
8077 | #endif | |
8078 | ||
8079 | case 'a': | |
8080 | /* Listing option. Just ignore these, we don't support additional | |
8081 | ones. */ | |
8082 | return 0; | |
8083 | ||
8084 | default: | |
8085 | for (opt = aarch64_opts; opt->option != NULL; opt++) | |
8086 | { | |
8087 | if (c == opt->option[0] | |
8088 | && ((arg == NULL && opt->option[1] == 0) | |
8089 | || streq (arg, opt->option + 1))) | |
8090 | { | |
8091 | /* If the option is deprecated, tell the user. */ | |
8092 | if (opt->deprecated != NULL) | |
8093 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, | |
8094 | arg ? arg : "", _(opt->deprecated)); | |
8095 | ||
8096 | if (opt->var != NULL) | |
8097 | *opt->var = opt->value; | |
8098 | ||
8099 | return 1; | |
8100 | } | |
8101 | } | |
8102 | ||
8103 | for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++) | |
8104 | { | |
8105 | /* These options are expected to have an argument. */ | |
8106 | if (c == lopt->option[0] | |
8107 | && arg != NULL | |
8108 | && strncmp (arg, lopt->option + 1, | |
8109 | strlen (lopt->option + 1)) == 0) | |
8110 | { | |
8111 | /* If the option is deprecated, tell the user. */ | |
8112 | if (lopt->deprecated != NULL) | |
8113 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, | |
8114 | _(lopt->deprecated)); | |
8115 | ||
8116 | /* Call the sup-option parser. */ | |
8117 | return lopt->func (arg + strlen (lopt->option) - 1); | |
8118 | } | |
8119 | } | |
8120 | ||
8121 | return 0; | |
8122 | } | |
8123 | ||
8124 | return 1; | |
8125 | } | |
8126 | ||
8127 | void | |
8128 | md_show_usage (FILE * fp) | |
8129 | { | |
8130 | struct aarch64_option_table *opt; | |
8131 | struct aarch64_long_option_table *lopt; | |
8132 | ||
8133 | fprintf (fp, _(" AArch64-specific assembler options:\n")); | |
8134 | ||
8135 | for (opt = aarch64_opts; opt->option != NULL; opt++) | |
8136 | if (opt->help != NULL) | |
8137 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
8138 | ||
8139 | for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++) | |
8140 | if (lopt->help != NULL) | |
8141 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
8142 | ||
8143 | #ifdef OPTION_EB | |
8144 | fprintf (fp, _("\ | |
8145 | -EB assemble code for a big-endian cpu\n")); | |
8146 | #endif | |
8147 | ||
8148 | #ifdef OPTION_EL | |
8149 | fprintf (fp, _("\ | |
8150 | -EL assemble code for a little-endian cpu\n")); | |
8151 | #endif | |
8152 | } | |
8153 | ||
8154 | /* Parse a .cpu directive. */ | |
8155 | ||
8156 | static void | |
8157 | s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED) | |
8158 | { | |
8159 | const struct aarch64_cpu_option_table *opt; | |
8160 | char saved_char; | |
8161 | char *name; | |
8162 | char *ext; | |
8163 | size_t optlen; | |
8164 | ||
8165 | name = input_line_pointer; | |
8166 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) | |
8167 | input_line_pointer++; | |
8168 | saved_char = *input_line_pointer; | |
8169 | *input_line_pointer = 0; | |
8170 | ||
8171 | ext = strchr (name, '+'); | |
8172 | ||
8173 | if (ext != NULL) | |
8174 | optlen = ext - name; | |
8175 | else | |
8176 | optlen = strlen (name); | |
8177 | ||
8178 | /* Skip the first "all" entry. */ | |
8179 | for (opt = aarch64_cpus + 1; opt->name != NULL; opt++) | |
8180 | if (strlen (opt->name) == optlen | |
8181 | && strncmp (name, opt->name, optlen) == 0) | |
8182 | { | |
8183 | mcpu_cpu_opt = &opt->value; | |
8184 | if (ext != NULL) | |
ae527cd8 | 8185 | if (!aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE)) |
a06ea964 NC |
8186 | return; |
8187 | ||
8188 | cpu_variant = *mcpu_cpu_opt; | |
8189 | ||
8190 | *input_line_pointer = saved_char; | |
8191 | demand_empty_rest_of_line (); | |
8192 | return; | |
8193 | } | |
8194 | as_bad (_("unknown cpu `%s'"), name); | |
8195 | *input_line_pointer = saved_char; | |
8196 | ignore_rest_of_line (); | |
8197 | } | |
8198 | ||
8199 | ||
8200 | /* Parse a .arch directive. */ | |
8201 | ||
8202 | static void | |
8203 | s_aarch64_arch (int ignored ATTRIBUTE_UNUSED) | |
8204 | { | |
8205 | const struct aarch64_arch_option_table *opt; | |
8206 | char saved_char; | |
8207 | char *name; | |
8208 | char *ext; | |
8209 | size_t optlen; | |
8210 | ||
8211 | name = input_line_pointer; | |
8212 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) | |
8213 | input_line_pointer++; | |
8214 | saved_char = *input_line_pointer; | |
8215 | *input_line_pointer = 0; | |
8216 | ||
8217 | ext = strchr (name, '+'); | |
8218 | ||
8219 | if (ext != NULL) | |
8220 | optlen = ext - name; | |
8221 | else | |
8222 | optlen = strlen (name); | |
8223 | ||
8224 | /* Skip the first "all" entry. */ | |
8225 | for (opt = aarch64_archs + 1; opt->name != NULL; opt++) | |
8226 | if (strlen (opt->name) == optlen | |
8227 | && strncmp (name, opt->name, optlen) == 0) | |
8228 | { | |
8229 | mcpu_cpu_opt = &opt->value; | |
8230 | if (ext != NULL) | |
ae527cd8 | 8231 | if (!aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE)) |
a06ea964 NC |
8232 | return; |
8233 | ||
8234 | cpu_variant = *mcpu_cpu_opt; | |
8235 | ||
8236 | *input_line_pointer = saved_char; | |
8237 | demand_empty_rest_of_line (); | |
8238 | return; | |
8239 | } | |
8240 | ||
8241 | as_bad (_("unknown architecture `%s'\n"), name); | |
8242 | *input_line_pointer = saved_char; | |
8243 | ignore_rest_of_line (); | |
8244 | } | |
8245 | ||
ae527cd8 JB |
8246 | /* Parse a .arch_extension directive. */ |
8247 | ||
8248 | static void | |
8249 | s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED) | |
8250 | { | |
8251 | char saved_char; | |
8252 | char *ext = input_line_pointer;; | |
8253 | ||
8254 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) | |
8255 | input_line_pointer++; | |
8256 | saved_char = *input_line_pointer; | |
8257 | *input_line_pointer = 0; | |
8258 | ||
8259 | if (!aarch64_parse_features (ext, &mcpu_cpu_opt, TRUE)) | |
8260 | return; | |
8261 | ||
8262 | cpu_variant = *mcpu_cpu_opt; | |
8263 | ||
8264 | *input_line_pointer = saved_char; | |
8265 | demand_empty_rest_of_line (); | |
8266 | } | |
8267 | ||
a06ea964 NC |
8268 | /* Copy symbol information. */ |
8269 | ||
8270 | void | |
8271 | aarch64_copy_symbol_attributes (symbolS * dest, symbolS * src) | |
8272 | { | |
8273 | AARCH64_GET_FLAG (dest) = AARCH64_GET_FLAG (src); | |
8274 | } |