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Remove Kaz Kojima as SH maintainer.
[deliverable/binutils-gdb.git] / gas / config / tc-arc.c
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252b5132 1/* tc-arc.c -- Assembler for the ARC
2571583a 2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19203624 19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
252b5132 23#include "as.h"
886a2506 24#include "subsegs.h"
a161fe53 25#include "struc-symbol.h"
886a2506 26#include "dwarf2dbg.h"
726c18e1 27#include "dw2gencfi.h"
3882b010 28#include "safe-ctype.h"
886a2506 29
252b5132
RH		 30#include "opcode/arc.h"
31#include "elf/arc.h"
b99747ae 32#include "../opcodes/arc-ext.h"
252b5132 33
886a2506 34/* Defines section. */
0d2bcfaf 35
886a2506
NC		 36#define MAX_INSN_FIXUPS 2
37#define MAX_CONSTR_STR 20
4670103e 38#define FRAG_MAX_GROWTH 8
0d2bcfaf 39
886a2506
NC		 40#ifdef DEBUG
41# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
42#else
43# define pr_debug(fmt, args...)
44#endif
45
46#define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47#define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
db18dbab
GM		 48#define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
49 && (SUB_OPCODE (x) == 0x28))
886a2506
NC		 50
51/* Equal to MAX_PRECISION in atof-ieee.c. */
52#define MAX_LITTLENUMS 6
53
9004b6bd
AB		 54#ifndef TARGET_WITH_CPU
55#define TARGET_WITH_CPU "arc700"
56#endif /* TARGET_WITH_CPU */
57
4670103e
CZ		 58/* Enum used to enumerate the relaxable ins operands. */
59enum rlx_operand_type
60{
61 EMPTY = 0,
62 REGISTER,
63 REGISTER_S, /* Register for short instruction(s). */
64 REGISTER_NO_GP, /* Is a register but not gp register specifically. */
65 REGISTER_DUP, /* Duplication of previous operand of type register. */
66 IMMEDIATE,
67 BRACKET
68};
69
70enum arc_rlx_types
71{
72 ARC_RLX_NONE = 0,
73 ARC_RLX_BL_S,
74 ARC_RLX_BL,
75 ARC_RLX_B_S,
76 ARC_RLX_B,
77 ARC_RLX_ADD_U3,
78 ARC_RLX_ADD_U6,
79 ARC_RLX_ADD_LIMM,
80 ARC_RLX_LD_U7,
81 ARC_RLX_LD_S9,
82 ARC_RLX_LD_LIMM,
83 ARC_RLX_MOV_U8,
84 ARC_RLX_MOV_S12,
85 ARC_RLX_MOV_LIMM,
86 ARC_RLX_SUB_U3,
87 ARC_RLX_SUB_U6,
88 ARC_RLX_SUB_LIMM,
89 ARC_RLX_MPY_U6,
90 ARC_RLX_MPY_LIMM,
91 ARC_RLX_MOV_RU6,
92 ARC_RLX_MOV_RLIMM,
93 ARC_RLX_ADD_RRU6,
94 ARC_RLX_ADD_RRLIMM,
95};
96
886a2506
NC		 97/* Macros section. */
98
99#define regno(x) ((x) & 0x3F)
100#define is_ir_num(x) (((x) & ~0x3F) == 0)
8ddf6b2a
CZ		 101#define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
102#define is_spfp_p(op) (((sc) == SPX))
103#define is_dpfp_p(op) (((sc) == DPX))
104#define is_fpuda_p(op) (((sc) == DPA))
db18dbab
GM		 105#define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
106 || (op)->insn_class == JUMP))
c810e0b8 107#define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
bdd582db 108#define is_nps400_p(op) (((sc) == NPS400))
0d2bcfaf 109
886a2506
NC		 110/* Generic assembler global variables which must be defined by all
111 targets. */
0d2bcfaf 112
886a2506 113/* Characters which always start a comment. */
252b5132
RH		 114const char comment_chars[] = "#;";
115
886a2506 116/* Characters which start a comment at the beginning of a line. */
252b5132
RH		 117const char line_comment_chars[] = "#";
118
886a2506
NC		 119/* Characters which may be used to separate multiple commands on a
120 single line. */
121const char line_separator_chars[] = "`";
252b5132 122
886a2506
NC		 123/* Characters which are used to indicate an exponent in a floating
124 point number. */
252b5132
RH		 125const char EXP_CHARS[] = "eE";
126
bcee8eb8
AM		 127/* Chars that mean this number is a floating point constant
128 As in 0f12.456 or 0d1.2345e12. */
252b5132
RH		 129const char FLT_CHARS[] = "rRsSfFdD";
130
131/* Byte order. */
132extern int target_big_endian;
133const char *arc_target_format = DEFAULT_TARGET_FORMAT;
134static int byte_order = DEFAULT_BYTE_ORDER;
135
b99747ae
CZ		 136/* Arc extension section. */
137static segT arcext_section;
138
4670103e
CZ		 139/* By default relaxation is disabled. */
140static int relaxation_state = 0;
141
886a2506 142extern int arc_get_mach (char *);
0d2bcfaf 143
4670103e 144/* Forward declarations. */
886a2506
NC		 145static void arc_lcomm (int);
146static void arc_option (int);
147static void arc_extra_reloc (int);
b99747ae 148static void arc_extinsn (int);
f36e33da 149static void arc_extcorereg (int);
4670103e 150
886a2506 151const pseudo_typeS md_pseudo_table[] =
6f4b1afc
CM		 152{
153 /* Make sure that .word is 32 bits. */
154 { "word", cons, 4 },
886a2506 155
6f4b1afc
CM		 156 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
157 { "lcomm", arc_lcomm, 0 },
158 { "lcommon", arc_lcomm, 0 },
159 { "cpu", arc_option, 0 },
252b5132 160
f36e33da
CZ		 161 { "extinstruction", arc_extinsn, 0 },
162 { "extcoreregister", arc_extcorereg, EXT_CORE_REGISTER },
163 { "extauxregister", arc_extcorereg, EXT_AUX_REGISTER },
164 { "extcondcode", arc_extcorereg, EXT_COND_CODE },
b99747ae 165
6f4b1afc
CM		 166 { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
167 { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
886a2506 168
6f4b1afc
CM		 169 { NULL, NULL, 0 }
170};
252b5132 171
252b5132 172const char *md_shortopts = "";
ea1562b3
NC		 173
174enum options
6f4b1afc
CM		 175{
176 OPTION_EB = OPTION_MD_BASE,
177 OPTION_EL,
178
179 OPTION_ARC600,
180 OPTION_ARC601,
181 OPTION_ARC700,
182 OPTION_ARCEM,
183 OPTION_ARCHS,
184
185 OPTION_MCPU,
186 OPTION_CD,
4670103e 187 OPTION_RELAX,
bdd582db 188 OPTION_NPS400,
6f4b1afc 189
ce440d63
GM		 190 OPTION_SPFP,
191 OPTION_DPFP,
192 OPTION_FPUDA,
193
6f4b1afc
CM		 194 /* The following options are deprecated and provided here only for
195 compatibility reasons. */
196 OPTION_USER_MODE,
197 OPTION_LD_EXT_MASK,
198 OPTION_SWAP,
199 OPTION_NORM,
200 OPTION_BARREL_SHIFT,
201 OPTION_MIN_MAX,
202 OPTION_NO_MPY,
203 OPTION_EA,
204 OPTION_MUL64,
205 OPTION_SIMD,
6f4b1afc
CM		 206 OPTION_XMAC_D16,
207 OPTION_XMAC_24,
208 OPTION_DSP_PACKA,
209 OPTION_CRC,
210 OPTION_DVBF,
211 OPTION_TELEPHONY,
212 OPTION_XYMEMORY,
213 OPTION_LOCK,
214 OPTION_SWAPE,
ce440d63 215 OPTION_RTSC
6f4b1afc 216};
ea1562b3
NC		 217
218struct option md_longopts[] =
6f4b1afc
CM		 219{
220 { "EB", no_argument, NULL, OPTION_EB },
221 { "EL", no_argument, NULL, OPTION_EL },
222 { "mcpu", required_argument, NULL, OPTION_MCPU },
223 { "mA6", no_argument, NULL, OPTION_ARC600 },
24b368f8
CZ		 224 { "mARC600", no_argument, NULL, OPTION_ARC600 },
225 { "mARC601", no_argument, NULL, OPTION_ARC601 },
226 { "mARC700", no_argument, NULL, OPTION_ARC700 },
6f4b1afc
CM		 227 { "mA7", no_argument, NULL, OPTION_ARC700 },
228 { "mEM", no_argument, NULL, OPTION_ARCEM },
229 { "mHS", no_argument, NULL, OPTION_ARCHS },
230 { "mcode-density", no_argument, NULL, OPTION_CD },
4670103e 231 { "mrelax", no_argument, NULL, OPTION_RELAX },
bdd582db 232 { "mnps400", no_argument, NULL, OPTION_NPS400 },
6f4b1afc 233
ce440d63
GM		 234 /* Floating point options */
235 { "mspfp", no_argument, NULL, OPTION_SPFP},
236 { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
237 { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
238 { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
239 { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
240 { "mdpfp", no_argument, NULL, OPTION_DPFP},
241 { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
242 { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
243 { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
244 { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
245 { "mfpuda", no_argument, NULL, OPTION_FPUDA},
246
6f4b1afc
CM		 247 /* The following options are deprecated and provided here only for
248 compatibility reasons. */
249 { "mav2em", no_argument, NULL, OPTION_ARCEM },
250 { "mav2hs", no_argument, NULL, OPTION_ARCHS },
251 { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE },
252 { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK },
253 { "mswap", no_argument, NULL, OPTION_SWAP },
254 { "mnorm", no_argument, NULL, OPTION_NORM },
255 { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
256 { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
257 { "mmin-max", no_argument, NULL, OPTION_MIN_MAX },
258 { "mmin_max", no_argument, NULL, OPTION_MIN_MAX },
259 { "mno-mpy", no_argument, NULL, OPTION_NO_MPY },
260 { "mea", no_argument, NULL, OPTION_EA },
261 { "mEA", no_argument, NULL, OPTION_EA },
262 { "mmul64", no_argument, NULL, OPTION_MUL64 },
263 { "msimd", no_argument, NULL, OPTION_SIMD},
6f4b1afc
CM		 264 { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
265 { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
266 { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
267 { "mmac_24", no_argument, NULL, OPTION_XMAC_24},
268 { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA},
269 { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA},
270 { "mcrc", no_argument, NULL, OPTION_CRC},
271 { "mdvbf", no_argument, NULL, OPTION_DVBF},
272 { "mtelephony", no_argument, NULL, OPTION_TELEPHONY},
273 { "mxy", no_argument, NULL, OPTION_XYMEMORY},
274 { "mlock", no_argument, NULL, OPTION_LOCK},
275 { "mswape", no_argument, NULL, OPTION_SWAPE},
276 { "mrtsc", no_argument, NULL, OPTION_RTSC},
6f4b1afc
CM		 277
278 { NULL, no_argument, NULL, 0 }
279};
252b5132 280
886a2506 281size_t md_longopts_size = sizeof (md_longopts);
0d2bcfaf 282
886a2506 283/* Local data and data types. */
252b5132 284
886a2506
NC		 285/* Used since new relocation types are introduced in this
286 file (DUMMY_RELOC_LITUSE_*). */
287typedef int extended_bfd_reloc_code_real_type;
252b5132 288
886a2506 289struct arc_fixup
252b5132 290{
886a2506 291 expressionS exp;
252b5132 292
886a2506 293 extended_bfd_reloc_code_real_type reloc;
252b5132 294
886a2506
NC		 295 /* index into arc_operands. */
296 unsigned int opindex;
252b5132 297
886a2506
NC		 298 /* PC-relative, used by internals fixups. */
299 unsigned char pcrel;
252b5132 300
886a2506
NC		 301 /* TRUE if this fixup is for LIMM operand. */
302 bfd_boolean islong;
303};
252b5132 304
886a2506
NC		 305struct arc_insn
306{
bdfe53e3 307 unsigned long long int insn;
886a2506
NC		 308 int nfixups;
309 struct arc_fixup fixups[MAX_INSN_FIXUPS];
310 long limm;
91fdca6f 311 unsigned int len; /* Length of instruction in bytes. */
886a2506
NC		 312 bfd_boolean has_limm; /* Boolean value: TRUE if limm field is
313 valid. */
4670103e
CZ		 314 bfd_boolean relax; /* Boolean value: TRUE if needs
315 relaxation. */
886a2506 316};
ea1562b3 317
886a2506
NC		 318/* Structure to hold any last two instructions. */
319static struct arc_last_insn
252b5132 320{
886a2506
NC		 321 /* Saved instruction opcode. */
322 const struct arc_opcode *opcode;
252b5132 323
886a2506
NC		 324 /* Boolean value: TRUE if current insn is short. */
325 bfd_boolean has_limm;
252b5132 326
886a2506
NC		 327 /* Boolean value: TRUE if current insn has delay slot. */
328 bfd_boolean has_delay_slot;
329} arc_last_insns[2];
252b5132 330
b99747ae
CZ		 331/* Extension instruction suffix classes. */
332typedef struct
333{
334 const char *name;
335 int len;
c810e0b8 336 int attr_class;
b99747ae
CZ		 337} attributes_t;
338
339static const attributes_t suffixclass[] =
340{
341 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG },
342 { "SUFFIX_COND", 11, ARC_SUFFIX_COND },
343 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE }
344};
345
346/* Extension instruction syntax classes. */
347static const attributes_t syntaxclass[] =
348{
349 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP },
945e0f82
CZ		 350 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP },
351 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP },
352 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP }
b99747ae
CZ		 353};
354
355/* Extension instruction syntax classes modifiers. */
356static const attributes_t syntaxclassmod[] =
357{
358 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED },
359 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM }
360};
361
f36e33da
CZ		 362/* Extension register type. */
363typedef struct
364{
365 char *name;
366 int number;
367 int imode;
368} extRegister_t;
369
370/* A structure to hold the additional conditional codes. */
371static struct
372{
373 struct arc_flag_operand *arc_ext_condcode;
374 int size;
375} ext_condcode = { NULL, 0 };
376
da5be039
AB		 377/* Structure to hold an entry in ARC_OPCODE_HASH. */
378struct arc_opcode_hash_entry
379{
380 /* The number of pointers in the OPCODE list. */
381 size_t count;
382
383 /* Points to a list of opcode pointers. */
384 const struct arc_opcode **opcode;
385};
386
1328504b
AB		 387/* Structure used for iterating through an arc_opcode_hash_entry. */
388struct arc_opcode_hash_entry_iterator
389{
390 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
391 size_t index;
392
393 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
394 returned by this iterator. */
395 const struct arc_opcode *opcode;
396};
397
4670103e
CZ		 398/* Forward declaration. */
399static void assemble_insn
400 (const struct arc_opcode *, const expressionS *, int,
401 const struct arc_flags *, int, struct arc_insn *);
402
bb65a718
AB		 403/* The selection of the machine type can come from different sources. This
404 enum is used to track how the selection was made in order to perform
405 error checks. */
406enum mach_selection_type
407 {
408 MACH_SELECTION_NONE,
409 MACH_SELECTION_FROM_DEFAULT,
410 MACH_SELECTION_FROM_CPU_DIRECTIVE,
411 MACH_SELECTION_FROM_COMMAND_LINE
412 };
413
414/* How the current machine type was selected. */
415static enum mach_selection_type mach_selection_mode = MACH_SELECTION_NONE;
0d2bcfaf 416
886a2506
NC		 417/* The hash table of instruction opcodes. */
418static struct hash_control *arc_opcode_hash;
0d2bcfaf 419
886a2506
NC		 420/* The hash table of register symbols. */
421static struct hash_control *arc_reg_hash;
252b5132 422
f36e33da
CZ		 423/* The hash table of aux register symbols. */
424static struct hash_control *arc_aux_hash;
425
db18dbab
GM		 426/* The hash table of address types. */
427static struct hash_control *arc_addrtype_hash;
428
a9752fdf
CZ		 429#define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
430 { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
431 E_ARC_MACH_ARC600, EXTRA}
432#define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
433 { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
434 E_ARC_MACH_ARC700, EXTRA}
435#define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
436 { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
437 EF_ARC_CPU_ARCV2EM, EXTRA}
438#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
439 { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
440 EF_ARC_CPU_ARCV2HS, EXTRA}
441
886a2506
NC		 442/* A table of CPU names and opcode sets. */
443static const struct cpu_type
444{
445 const char *name;
446 unsigned flags;
447 int mach;
448 unsigned eflags;
449 unsigned features;
252b5132 450}
886a2506 451 cpu_types[] =
252b5132 452{
a9752fdf
CZ		 453 ARC_CPU_TYPE_A7xx (arc700, 0x00),
454 ARC_CPU_TYPE_A7xx (nps400, ARC_NPS400),
455
456 ARC_CPU_TYPE_AV2EM (arcem, 0x00),
457 ARC_CPU_TYPE_AV2EM (em, 0x00),
458 ARC_CPU_TYPE_AV2EM (em4, ARC_CD),
459 ARC_CPU_TYPE_AV2EM (em4_dmips, ARC_CD),
460 ARC_CPU_TYPE_AV2EM (em4_fpus, ARC_CD),
461 ARC_CPU_TYPE_AV2EM (em4_fpuda, ARC_CD | ARC_FPUDA),
462 ARC_CPU_TYPE_AV2EM (quarkse_em, ARC_CD | ARC_SPFP | ARC_DPFP),
463
464 ARC_CPU_TYPE_AV2HS (archs, ARC_CD),
465 ARC_CPU_TYPE_AV2HS (hs, ARC_CD),
466 ARC_CPU_TYPE_AV2HS (hs34, ARC_CD),
467 ARC_CPU_TYPE_AV2HS (hs38, ARC_CD),
468 ARC_CPU_TYPE_AV2HS (hs38_linux, ARC_CD),
469
470 ARC_CPU_TYPE_A6xx (arc600, 0x00),
471 ARC_CPU_TYPE_A6xx (arc600_norm, 0x00),
472 ARC_CPU_TYPE_A6xx (arc600_mul64, 0x00),
473 ARC_CPU_TYPE_A6xx (arc600_mul32x16, 0x00),
474 ARC_CPU_TYPE_A6xx (arc601, 0x00),
475 ARC_CPU_TYPE_A6xx (arc601_norm, 0x00),
476 ARC_CPU_TYPE_A6xx (arc601_mul64, 0x00),
477 ARC_CPU_TYPE_A6xx (arc601_mul32x16, 0x00),
886a2506
NC		 478 { 0, 0, 0, 0, 0 }
479};
252b5132 480
bb65a718 481/* Information about the cpu/variant we're assembling for. */
bb050a69
CZ		 482static struct cpu_type selected_cpu = { 0, 0, 0, 0, 0 };
483
484/* A table with options. */
485static const struct feature_type
486{
487 unsigned feature;
488 unsigned cpus;
489 const char *name;
490}
491 feature_list[] =
492{
493 { ARC_CD, ARC_OPCODE_ARCV2, "code-density" },
494 { ARC_NPS400, ARC_OPCODE_ARC700, "nps400" },
495 { ARC_SPFP, ARC_OPCODE_ARCFPX, "single-precision FPX" },
496 { ARC_DPFP, ARC_OPCODE_ARCFPX, "double-precision FPX" },
497 { ARC_FPUDA, ARC_OPCODE_ARCv2EM, "double assist FP" }
498};
bb65a718 499
a9752fdf
CZ		 500/* Command line given features. */
501static unsigned cl_features = 0;
502
886a2506
NC		 503/* Used by the arc_reloc_op table. Order is important. */
504#define O_gotoff O_md1 /* @gotoff relocation. */
505#define O_gotpc O_md2 /* @gotpc relocation. */
506#define O_plt O_md3 /* @plt relocation. */
507#define O_sda O_md4 /* @sda relocation. */
508#define O_pcl O_md5 /* @pcl relocation. */
509#define O_tlsgd O_md6 /* @tlsgd relocation. */
510#define O_tlsie O_md7 /* @tlsie relocation. */
511#define O_tpoff9 O_md8 /* @tpoff9 relocation. */
512#define O_tpoff O_md9 /* @tpoff relocation. */
513#define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
514#define O_dtpoff O_md11 /* @dtpoff relocation. */
515#define O_last O_dtpoff
516
517/* Used to define a bracket as operand in tokens. */
518#define O_bracket O_md32
519
db18dbab
GM		 520/* Used to define a colon as an operand in tokens. */
521#define O_colon O_md31
522
523/* Used to define address types in nps400. */
524#define O_addrtype O_md30
525
886a2506
NC		 526/* Dummy relocation, to be sorted out. */
527#define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
528
529#define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
530
531/* A table to map the spelling of a relocation operand into an appropriate
532 bfd_reloc_code_real_type type. The table is assumed to be ordered such
533 that op-O_literal indexes into it. */
534#define ARC_RELOC_TABLE(op) \
535 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
536 ? (abort (), 0) \
537 : (int) (op) - (int) O_gotoff) ])
538
539#define DEF(NAME, RELOC, REQ) \
540 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
541
542static const struct arc_reloc_op_tag
543{
544 /* String to lookup. */
545 const char *name;
546 /* Size of the string. */
547 size_t length;
548 /* Which operator to use. */
549 operatorT op;
550 extended_bfd_reloc_code_real_type reloc;
551 /* Allows complex relocation expression like identifier@reloc +
552 const. */
553 unsigned int complex_expr : 1;
554}
555 arc_reloc_op[] =
6f4b1afc
CM		 556{
557 DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1),
558 DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0),
559 DEF (plt, BFD_RELOC_ARC_PLT32, 0),
560 DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1),
561 DEF (pcl, BFD_RELOC_ARC_PC32, 1),
562 DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0),
563 DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0),
564 DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0),
b125bd17 565 DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1),
6f4b1afc 566 DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
05bbf016 567 DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 1),
6f4b1afc 568};
252b5132 569
886a2506
NC		 570static const int arc_num_reloc_op
571= sizeof (arc_reloc_op) / sizeof (*arc_reloc_op);
572
4670103e
CZ		 573/* Structure for relaxable instruction that have to be swapped with a
574 smaller alternative instruction. */
575struct arc_relaxable_ins
576{
577 /* Mnemonic that should be checked. */
578 const char *mnemonic_r;
579
580 /* Operands that should be checked.
581 Indexes of operands from operand array. */
582 enum rlx_operand_type operands[6];
583
584 /* Flags that should be checked. */
585 unsigned flag_classes[5];
586
587 /* Mnemonic (smaller) alternative to be used later for relaxation. */
588 const char *mnemonic_alt;
589
590 /* Index of operand that generic relaxation has to check. */
591 unsigned opcheckidx;
592
593 /* Base subtype index used. */
594 enum arc_rlx_types subtype;
595};
596
597#define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
598 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
599 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
600 (SIZE), \
601 (NEXT) } \
602
603#define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
604 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
605 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
606 (SIZE), \
607 (NEXT) } \
608
609
610/* ARC relaxation table. */
611const relax_typeS md_relax_table[] =
612{
613 /* Fake entry. */
614 {0, 0, 0, 0},
615
616 /* BL_S s13 ->
617 BL s25. */
db18dbab
GM		 618 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL),
619 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 620
621 /* B_S s10 ->
622 B s25. */
db18dbab
GM		 623 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B),
624 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 625
626 /* ADD_S c,b, u3 ->
627 ADD<.f> a,b,u6 ->
628 ADD<.f> a,b,limm. */
db18dbab
GM		 629 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6),
630 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM),
631 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 632
633 /* LD_S a, [b, u7] ->
634 LD<zz><.x><.aa><.di> a, [b, s9] ->
635 LD<zz><.x><.aa><.di> a, [b, limm] */
db18dbab
GM		 636 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9),
637 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM),
638 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE),
4670103e
CZ		 639
640 /* MOV_S b, u8 ->
641 MOV<.f> b, s12 ->
642 MOV<.f> b, limm. */
db18dbab
GM		 643 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12),
644 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM),
645 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 646
647 /* SUB_S c, b, u3 ->
648 SUB<.f> a, b, u6 ->
649 SUB<.f> a, b, limm. */
db18dbab
GM		 650 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6),
651 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM),
652 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 653
654 /* MPY<.f> a, b, u6 ->
655 MPY<.f> a, b, limm. */
db18dbab
GM		 656 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM),
657 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 658
659 /* MOV<.f><.cc> b, u6 ->
660 MOV<.f><.cc> b, limm. */
db18dbab
GM		 661 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM),
662 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 663
664 /* ADD<.f><.cc> b, b, u6 ->
665 ADD<.f><.cc> b, b, limm. */
db18dbab
GM		 666 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM),
667 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 668};
669
670/* Order of this table's entries matters! */
671const struct arc_relaxable_ins arc_relaxable_insns[] =
672{
673 { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S },
674 { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S },
675 { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add",
676 2, ARC_RLX_ADD_RRU6},
677 { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2,
678 ARC_RLX_ADD_U3 },
679 { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2,
680 ARC_RLX_ADD_U6 },
681 { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET },
682 { 0 }, "ld_s", 3, ARC_RLX_LD_U7 },
683 { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET },
684 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 },
685 { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 },
686 { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 },
687 { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 },
688 { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2,
689 ARC_RLX_SUB_U3 },
690 { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2,
691 ARC_RLX_SUB_U6 },
692 { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2,
693 ARC_RLX_MPY_U6 },
694};
695
696const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
697
886a2506 698/* Flags to set in the elf header. */
bb65a718 699static const flagword arc_initial_eflag = 0x00;
886a2506
NC		 700
701/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
702symbolS * GOT_symbol = 0;
703
704/* Set to TRUE when we assemble instructions. */
705static bfd_boolean assembling_insn = FALSE;
706
886a2506
NC		 707/* Functions implementation. */
708
b9b47ab7
AB		 709/* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
710 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
711 are no matching entries in ARC_OPCODE_HASH. */
da5be039 712
b9b47ab7 713static const struct arc_opcode_hash_entry *
da5be039
AB		 714arc_find_opcode (const char *name)
715{
716 const struct arc_opcode_hash_entry *entry;
da5be039
AB		 717
718 entry = hash_find (arc_opcode_hash, name);
b9b47ab7 719 return entry;
da5be039
AB		 720}
721
1328504b
AB		 722/* Initialise the iterator ITER. */
723
724static void
725arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator *iter)
726{
727 iter->index = 0;
728 iter->opcode = NULL;
729}
730
731/* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
732 calls to this function. Return NULL when all ARC_OPCODE entries have
733 been returned. */
734
735static const struct arc_opcode *
736arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry,
737 struct arc_opcode_hash_entry_iterator *iter)
738{
739 if (iter->opcode == NULL && iter->index == 0)
740 {
741 gas_assert (entry->count > 0);
742 iter->opcode = entry->opcode[iter->index];
743 }
744 else if (iter->opcode != NULL)
745 {
746 const char *old_name = iter->opcode->name;
747
748 iter->opcode++;
fe779266
AB		 749 if (iter->opcode->name == NULL
750 || strcmp (old_name, iter->opcode->name) != 0)
1328504b
AB		 751 {
752 iter->index++;
753 if (iter->index == entry->count)
754 iter->opcode = NULL;
755 else
756 iter->opcode = entry->opcode[iter->index];
757 }
758 }
759
760 return iter->opcode;
761}
762
b99747ae
CZ		 763/* Insert an opcode into opcode hash structure. */
764
765static void
766arc_insert_opcode (const struct arc_opcode *opcode)
767{
768 const char *name, *retval;
769 struct arc_opcode_hash_entry *entry;
770 name = opcode->name;
771
772 entry = hash_find (arc_opcode_hash, name);
773 if (entry == NULL)
774 {
add39d23 775 entry = XNEW (struct arc_opcode_hash_entry);
b99747ae
CZ		 776 entry->count = 0;
777 entry->opcode = NULL;
778
779 retval = hash_insert (arc_opcode_hash, name, (void *) entry);
780 if (retval)
781 as_fatal (_("internal error: can't hash opcode '%s': %s"),
782 name, retval);
783 }
784
add39d23
TS		 785 entry->opcode = XRESIZEVEC (const struct arc_opcode *, entry->opcode,
786 entry->count + 1);
b99747ae
CZ		 787
788 if (entry->opcode == NULL)
789 as_fatal (_("Virtual memory exhausted"));
790
791 entry->opcode[entry->count] = opcode;
792 entry->count++;
793}
794
795
bdfe53e3
AB		 796/* Like md_number_to_chars but for middle-endian values. The 4-byte limm
797 value, is encoded as 'middle-endian' for a little-endian target. This
798 function is used for regular 4, 6, and 8 byte instructions as well. */
886a2506
NC		 799
800static void
bdfe53e3 801md_number_to_chars_midend (char *buf, unsigned long long val, int n)
886a2506 802{
bdfe53e3 803 switch (n)
886a2506 804 {
bdfe53e3
AB		 805 case 2:
806 md_number_to_chars (buf, val, n);
807 break;
808 case 6:
809 md_number_to_chars (buf, (val & 0xffff00000000) >> 32, 2);
810 md_number_to_chars_midend (buf + 2, (val & 0xffffffff), 4);
811 break;
812 case 4:
886a2506
NC		 813 md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
814 md_number_to_chars (buf + 2, (val & 0xffff), 2);
bdfe53e3
AB		 815 break;
816 case 8:
817 md_number_to_chars_midend (buf, (val & 0xffffffff00000000) >> 32, 4);
818 md_number_to_chars_midend (buf + 4, (val & 0xffffffff), 4);
819 break;
820 default:
821 abort ();
886a2506 822 }
252b5132
RH		 823}
824
bb050a69
CZ		 825/* Check if a feature is allowed for a specific CPU. */
826
827static void
828arc_check_feature (void)
829{
830 unsigned i;
831
832 if (!selected_cpu.features
833 || !selected_cpu.name)
834 return;
835 for (i = 0; (i < ARRAY_SIZE (feature_list)); i++)
836 {
837 if ((selected_cpu.features & feature_list[i].feature)
838 && !(selected_cpu.flags & feature_list[i].cpus))
839 {
840 as_bad (_("invalid %s option for %s cpu"), feature_list[i].name,
841 selected_cpu.name);
842 }
843 }
844}
845
24740d83 846/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
bb65a718
AB		 847 the relevant static global variables. Parameter SEL describes where
848 this selection originated from. */
24740d83
AB		 849
850static void
bb65a718 851arc_select_cpu (const char *arg, enum mach_selection_type sel)
24740d83 852{
a9522a21 853 int cpu_flags = 0;
24740d83
AB		 854 int i;
855
bb65a718
AB		 856 /* We should only set a default if we've not made a selection from some
857 other source. */
858 gas_assert (sel != MACH_SELECTION_FROM_DEFAULT
859 || mach_selection_mode == MACH_SELECTION_NONE);
860
bb050a69
CZ		 861 if ((mach_selection_mode == MACH_SELECTION_FROM_CPU_DIRECTIVE)
862 && (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE))
863 as_bad (_("Multiple .cpu directives found"));
864
bb65a718 865 /* Look for a matching entry in CPU_TYPES array. */
24740d83
AB		 866 for (i = 0; cpu_types[i].name; ++i)
867 {
868 if (!strcasecmp (cpu_types[i].name, arg))
869 {
bb65a718
AB		 870 /* If a previous selection was made on the command line, then we
871 allow later selections on the command line to override earlier
872 ones. However, a selection from a '.cpu NAME' directive must
873 match the command line selection, or we give a warning. */
874 if (mach_selection_mode == MACH_SELECTION_FROM_COMMAND_LINE)
875 {
876 gas_assert (sel == MACH_SELECTION_FROM_COMMAND_LINE
877 || sel == MACH_SELECTION_FROM_CPU_DIRECTIVE);
878 if (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE
879 && selected_cpu.mach != cpu_types[i].mach)
880 {
881 as_warn (_("Command-line value overrides \".cpu\" directive"));
bb65a718 882 }
bb050a69 883 return;
bb65a718
AB		 884 }
885
bb050a69
CZ		 886 /* Initialise static global data about selected machine type. */
887 selected_cpu.flags = cpu_types[i].flags;
888 selected_cpu.name = cpu_types[i].name;
a9752fdf 889 selected_cpu.features = cpu_types[i].features | cl_features;
bb050a69
CZ		 890 selected_cpu.mach = cpu_types[i].mach;
891 cpu_flags = cpu_types[i].eflags;
24740d83
AB		 892 break;
893 }
894 }
895
896 if (!cpu_types[i].name)
897 as_fatal (_("unknown architecture: %s\n"), arg);
bb050a69
CZ		 898
899 /* Check if set features are compatible with the chosen CPU. */
900 arc_check_feature ();
a9522a21 901 gas_assert (cpu_flags != 0);
bb65a718
AB		 902 selected_cpu.eflags = (arc_initial_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
903 mach_selection_mode = sel;
24740d83
AB		 904}
905
886a2506
NC		 906/* Here ends all the ARCompact extension instruction assembling
907 stuff. */
252b5132 908
886a2506
NC		 909static void
910arc_extra_reloc (int r_type)
ea1562b3 911{
886a2506
NC		 912 char *sym_name, c;
913 symbolS *sym, *lab = NULL;
914
915 if (*input_line_pointer == '@')
916 input_line_pointer++;
917 c = get_symbol_name (&sym_name);
918 sym = symbol_find_or_make (sym_name);
919 restore_line_pointer (c);
920 if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD)
921 {
922 ++input_line_pointer;
923 char *lab_name;
924 c = get_symbol_name (&lab_name);
925 lab = symbol_find_or_make (lab_name);
926 restore_line_pointer (c);
927 }
841fdfcd
CZ		 928
929 /* These relocations exist as a mechanism for the compiler to tell the
930 linker how to patch the code if the tls model is optimised. However,
931 the relocation itself does not require any space within the assembler
932 fragment, and so we pass a size of 0.
933
934 The lines that generate these relocations look like this:
935
936 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
937
938 The '.tls_gd_ld @.tdata' is processed first and generates the
939 additional relocation, while the 'bl __tls_get_addr@plt' is processed
940 second and generates the additional branch.
941
942 It is possible that the additional relocation generated by the
943 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
944 while the 'bl __tls_get_addr@plt' will be generated as the first thing
945 in the next fragment. This will be fine; both relocations will still
946 appear to be at the same address in the generated object file.
947 However, this only works as the additional relocation is generated
948 with size of 0 bytes. */
886a2506
NC		 949 fixS *fixP
950 = fix_new (frag_now, /* Which frag? */
951 frag_now_fix (), /* Where in that frag? */
841fdfcd 952 0, /* size: 1, 2, or 4 usually. */
886a2506
NC		 953 sym, /* X_add_symbol. */
954 0, /* X_add_number. */
955 FALSE, /* TRUE if PC-relative relocation. */
956 r_type /* Relocation type. */);
957 fixP->fx_subsy = lab;
958}
252b5132 959
886a2506
NC		 960static symbolS *
961arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED,
962 symbolS *symbolP, addressT size)
963{
964 addressT align = 0;
965 SKIP_WHITESPACE ();
252b5132 966
886a2506
NC		 967 if (*input_line_pointer == ',')
968 {
969 align = parse_align (1);
252b5132 970
886a2506
NC		 971 if (align == (addressT) -1)
972 return NULL;
973 }
974 else
975 {
976 if (size >= 8)
977 align = 3;
978 else if (size >= 4)
979 align = 2;
980 else if (size >= 2)
981 align = 1;
982 else
983 align = 0;
984 }
252b5132 985
886a2506
NC		 986 bss_alloc (symbolP, size, align);
987 S_CLEAR_EXTERNAL (symbolP);
ea1562b3 988
886a2506
NC		 989 return symbolP;
990}
ea1562b3 991
886a2506
NC		 992static void
993arc_lcomm (int ignore)
994{
995 symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal);
ea1562b3 996
886a2506
NC		 997 if (symbolP)
998 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
999}
ea1562b3 1000
886a2506 1001/* Select the cpu we're assembling for. */
ea1562b3 1002
886a2506
NC		 1003static void
1004arc_option (int ignore ATTRIBUTE_UNUSED)
252b5132 1005{
886a2506
NC		 1006 char c;
1007 char *cpu;
bb65a718 1008 const char *cpu_name;
252b5132 1009
886a2506 1010 c = get_symbol_name (&cpu);
252b5132 1011
a9752fdf 1012 cpu_name = cpu;
bb65a718
AB		 1013 if ((!strcmp ("ARC600", cpu))
1014 || (!strcmp ("ARC601", cpu))
1015 || (!strcmp ("A6", cpu)))
1016 cpu_name = "arc600";
1017 else if ((!strcmp ("ARC700", cpu))
1018 || (!strcmp ("A7", cpu)))
1019 cpu_name = "arc700";
1020 else if (!strcmp ("EM", cpu))
1021 cpu_name = "arcem";
1022 else if (!strcmp ("HS", cpu))
1023 cpu_name = "archs";
1024 else if (!strcmp ("NPS400", cpu))
1025 cpu_name = "nps400";
886a2506 1026
a9752fdf 1027 arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE);
24b368f8 1028
bb65a718
AB		 1029 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
1030 as_fatal (_("could not set architecture and machine"));
1adc8a9a 1031
bb65a718
AB		 1032 /* Set elf header flags. */
1033 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
886a2506 1034
24b368f8 1035 restore_line_pointer (c);
886a2506 1036 demand_empty_rest_of_line ();
ea1562b3 1037}
252b5132 1038
886a2506
NC		 1039/* Smartly print an expression. */
1040
ea1562b3 1041static void
886a2506 1042debug_exp (expressionS *t)
ea1562b3 1043{
886a2506
NC		 1044 const char *name ATTRIBUTE_UNUSED;
1045 const char *namemd ATTRIBUTE_UNUSED;
252b5132 1046
886a2506 1047 pr_debug ("debug_exp: ");
252b5132 1048
886a2506 1049 switch (t->X_op)
252b5132 1050 {
886a2506
NC		 1051 default: name = "unknown"; break;
1052 case O_illegal: name = "O_illegal"; break;
1053 case O_absent: name = "O_absent"; break;
1054 case O_constant: name = "O_constant"; break;
1055 case O_symbol: name = "O_symbol"; break;
1056 case O_symbol_rva: name = "O_symbol_rva"; break;
1057 case O_register: name = "O_register"; break;
1058 case O_big: name = "O_big"; break;
1059 case O_uminus: name = "O_uminus"; break;
1060 case O_bit_not: name = "O_bit_not"; break;
1061 case O_logical_not: name = "O_logical_not"; break;
1062 case O_multiply: name = "O_multiply"; break;
1063 case O_divide: name = "O_divide"; break;
1064 case O_modulus: name = "O_modulus"; break;
1065 case O_left_shift: name = "O_left_shift"; break;
1066 case O_right_shift: name = "O_right_shift"; break;
1067 case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break;
1068 case O_bit_or_not: name = "O_bit_or_not"; break;
1069 case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break;
1070 case O_bit_and: name = "O_bit_and"; break;
1071 case O_add: name = "O_add"; break;
1072 case O_subtract: name = "O_subtract"; break;
1073 case O_eq: name = "O_eq"; break;
1074 case O_ne: name = "O_ne"; break;
1075 case O_lt: name = "O_lt"; break;
1076 case O_le: name = "O_le"; break;
1077 case O_ge: name = "O_ge"; break;
1078 case O_gt: name = "O_gt"; break;
1079 case O_logical_and: name = "O_logical_and"; break;
1080 case O_logical_or: name = "O_logical_or"; break;
1081 case O_index: name = "O_index"; break;
1082 case O_bracket: name = "O_bracket"; break;
db18dbab
GM		 1083 case O_colon: name = "O_colon"; break;
1084 case O_addrtype: name = "O_addrtype"; break;
ea1562b3 1085 }
252b5132 1086
886a2506 1087 switch (t->X_md)
ea1562b3 1088 {
886a2506
NC		 1089 default: namemd = "unknown"; break;
1090 case O_gotoff: namemd = "O_gotoff"; break;
1091 case O_gotpc: namemd = "O_gotpc"; break;
1092 case O_plt: namemd = "O_plt"; break;
1093 case O_sda: namemd = "O_sda"; break;
1094 case O_pcl: namemd = "O_pcl"; break;
1095 case O_tlsgd: namemd = "O_tlsgd"; break;
1096 case O_tlsie: namemd = "O_tlsie"; break;
1097 case O_tpoff9: namemd = "O_tpoff9"; break;
1098 case O_tpoff: namemd = "O_tpoff"; break;
1099 case O_dtpoff9: namemd = "O_dtpoff9"; break;
1100 case O_dtpoff: namemd = "O_dtpoff"; break;
ea1562b3 1101 }
252b5132 1102
886a2506
NC		 1103 pr_debug ("%s (%s, %s, %d, %s)", name,
1104 (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
1105 (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
1106 (int) t->X_add_number,
1107 (t->X_md) ? namemd : "--");
1108 pr_debug ("\n");
1109 fflush (stderr);
1110}
252b5132 1111
886a2506
NC		 1112/* Parse the arguments to an opcode. */
1113
1114static int
1115tokenize_arguments (char *str,
1116 expressionS *tok,
1117 int ntok)
1118{
1119 char *old_input_line_pointer;
1120 bfd_boolean saw_comma = FALSE;
1121 bfd_boolean saw_arg = FALSE;
1122 int brk_lvl = 0;
1123 int num_args = 0;
886a2506
NC		 1124 int i;
1125 size_t len;
1126 const struct arc_reloc_op_tag *r;
1127 expressionS tmpE;
6f4b1afc 1128 char *reloc_name, c;
886a2506
NC		 1129
1130 memset (tok, 0, sizeof (*tok) * ntok);
1131
1132 /* Save and restore input_line_pointer around this function. */
1133 old_input_line_pointer = input_line_pointer;
1134 input_line_pointer = str;
ea1562b3 1135
886a2506 1136 while (*input_line_pointer)
ea1562b3
NC		 1137 {
1138 SKIP_WHITESPACE ();
886a2506 1139 switch (*input_line_pointer)
252b5132 1140 {
886a2506
NC		 1141 case '\0':
1142 goto fini;
1143
1144 case ',':
1145 input_line_pointer++;
1146 if (saw_comma || !saw_arg)
1147 goto err;
1148 saw_comma = TRUE;
1149 break;
252b5132 1150
886a2506
NC		 1151 case '}':
1152 case ']':
1153 ++input_line_pointer;
1154 --brk_lvl;
3b889a78 1155 if (!saw_arg || num_args == ntok)
886a2506
NC		 1156 goto err;
1157 tok->X_op = O_bracket;
1158 ++tok;
1159 ++num_args;
1160 break;
ea1562b3 1161
886a2506
NC		 1162 case '{':
1163 case '[':
1164 input_line_pointer++;
3b889a78 1165 if (brk_lvl || num_args == ntok)
886a2506
NC		 1166 goto err;
1167 ++brk_lvl;
1168 tok->X_op = O_bracket;
1169 ++tok;
1170 ++num_args;
1171 break;
1172
db18dbab
GM		 1173 case ':':
1174 input_line_pointer++;
1175 if (!saw_arg || num_args == ntok)
1176 goto err;
1177 tok->X_op = O_colon;
1178 saw_arg = FALSE;
1179 ++tok;
1180 ++num_args;
1181 break;
1182
886a2506
NC		 1183 case '@':
1184 /* We have labels, function names and relocations, all
1185 starting with @ symbol. Sort them out. */
3b889a78 1186 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506
NC		 1187 goto err;
1188
1189 /* Parse @label. */
1190 tok->X_op = O_symbol;
1191 tok->X_md = O_absent;
1192 expression (tok);
1193 if (*input_line_pointer != '@')
1194 goto normalsymbol; /* This is not a relocation. */
1195
6f4b1afc
CM		 1196 relocationsym:
1197
33eaf5de 1198 /* A relocation operand has the following form
886a2506
NC		 1199 @identifier@relocation_type. The identifier is already
1200 in tok! */
1201 if (tok->X_op != O_symbol)
ea1562b3 1202 {
886a2506
NC		 1203 as_bad (_("No valid label relocation operand"));
1204 goto err;
252b5132 1205 }
886a2506
NC		 1206
1207 /* Parse @relocation_type. */
6f4b1afc
CM		 1208 input_line_pointer++;
1209 c = get_symbol_name (&reloc_name);
1210 len = input_line_pointer - reloc_name;
1211 if (len == 0)
252b5132 1212 {
886a2506
NC		 1213 as_bad (_("No relocation operand"));
1214 goto err;
252b5132 1215 }
252b5132 1216
886a2506
NC		 1217 /* Go through known relocation and try to find a match. */
1218 r = &arc_reloc_op[0];
1219 for (i = arc_num_reloc_op - 1; i >= 0; i--, r++)
6f4b1afc
CM		 1220 if (len == r->length
1221 && memcmp (reloc_name, r->name, len) == 0)
886a2506 1222 break;
886a2506 1223 if (i < 0)
252b5132 1224 {
6f4b1afc 1225 as_bad (_("Unknown relocation operand: @%s"), reloc_name);
886a2506
NC		 1226 goto err;
1227 }
1228
6f4b1afc
CM		 1229 *input_line_pointer = c;
1230 SKIP_WHITESPACE_AFTER_NAME ();
886a2506
NC		 1231 /* Extra check for TLS: base. */
1232 if (*input_line_pointer == '@')
1233 {
1234 symbolS *base;
1235 if (tok->X_op_symbol != NULL
1236 || tok->X_op != O_symbol)
252b5132 1237 {
6f4b1afc
CM		 1238 as_bad (_("Unable to parse TLS base: %s"),
1239 input_line_pointer);
886a2506 1240 goto err;
252b5132 1241 }
886a2506
NC		 1242 input_line_pointer++;
1243 char *sym_name;
6f4b1afc 1244 c = get_symbol_name (&sym_name);
886a2506
NC		 1245 base = symbol_find_or_make (sym_name);
1246 tok->X_op = O_subtract;
1247 tok->X_op_symbol = base;
1248 restore_line_pointer (c);
6f4b1afc
CM		 1249 tmpE.X_add_number = 0;
1250 }
32348c58 1251 if ((*input_line_pointer != '+')
6f4b1afc
CM		 1252 && (*input_line_pointer != '-'))
1253 {
1254 tmpE.X_add_number = 0;
ea1562b3 1255 }
6f4b1afc
CM		 1256 else
1257 {
1258 /* Parse the constant of a complex relocation expression
1259 like @identifier@reloc +/- const. */
1260 if (! r->complex_expr)
1261 {
1262 as_bad (_("@%s is not a complex relocation."), r->name);
1263 goto err;
1264 }
1265 expression (&tmpE);
1266 if (tmpE.X_op != O_constant)
1267 {
1268 as_bad (_("Bad expression: @%s + %s."),
1269 r->name, input_line_pointer);
1270 goto err;
1271 }
1272 }
1273
1274 tok->X_md = r->op;
1275 tok->X_add_number = tmpE.X_add_number;
1e07b820 1276
886a2506 1277 debug_exp (tok);
ea1562b3 1278
886a2506
NC		 1279 saw_comma = FALSE;
1280 saw_arg = TRUE;
1281 tok++;
1282 num_args++;
1283 break;
252b5132 1284
886a2506
NC		 1285 case '%':
1286 /* Can be a register. */
1287 ++input_line_pointer;
1288 /* Fall through. */
1289 default:
252b5132 1290
3b889a78 1291 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506 1292 goto err;
252b5132 1293
886a2506 1294 tok->X_op = O_absent;
6f4b1afc 1295 tok->X_md = O_absent;
886a2506 1296 expression (tok);
252b5132 1297
6f4b1afc
CM		 1298 /* Legacy: There are cases when we have
1299 identifier@relocation_type, if it is the case parse the
1300 relocation type as well. */
1301 if (*input_line_pointer == '@')
1302 goto relocationsym;
1303
886a2506
NC		 1304 normalsymbol:
1305 debug_exp (tok);
252b5132 1306
3b889a78
AB		 1307 if (tok->X_op == O_illegal
1308 || tok->X_op == O_absent
1309 || num_args == ntok)
886a2506 1310 goto err;
252b5132 1311
886a2506
NC		 1312 saw_comma = FALSE;
1313 saw_arg = TRUE;
1314 tok++;
1315 num_args++;
1316 break;
1317 }
ea1562b3 1318 }
252b5132 1319
886a2506
NC		 1320 fini:
1321 if (saw_comma || brk_lvl)
1322 goto err;
1323 input_line_pointer = old_input_line_pointer;
252b5132 1324
886a2506 1325 return num_args;
252b5132 1326
886a2506
NC		 1327 err:
1328 if (brk_lvl)
1329 as_bad (_("Brackets in operand field incorrect"));
1330 else if (saw_comma)
1331 as_bad (_("extra comma"));
1332 else if (!saw_arg)
1333 as_bad (_("missing argument"));
1334 else
1335 as_bad (_("missing comma or colon"));
1336 input_line_pointer = old_input_line_pointer;
1337 return -1;
252b5132 1338}
ea1562b3 1339
886a2506
NC		 1340/* Parse the flags to a structure. */
1341
1342static int
1343tokenize_flags (const char *str,
1344 struct arc_flags flags[],
1345 int nflg)
252b5132 1346{
886a2506
NC		 1347 char *old_input_line_pointer;
1348 bfd_boolean saw_flg = FALSE;
1349 bfd_boolean saw_dot = FALSE;
1350 int num_flags = 0;
1351 size_t flgnamelen;
252b5132 1352
886a2506 1353 memset (flags, 0, sizeof (*flags) * nflg);
0d2bcfaf 1354
886a2506
NC		 1355 /* Save and restore input_line_pointer around this function. */
1356 old_input_line_pointer = input_line_pointer;
1357 input_line_pointer = (char *) str;
0d2bcfaf 1358
886a2506
NC		 1359 while (*input_line_pointer)
1360 {
1361 switch (*input_line_pointer)
1362 {
1363 case ' ':
1364 case '\0':
1365 goto fini;
1366
1367 case '.':
1368 input_line_pointer++;
1369 if (saw_dot)
1370 goto err;
1371 saw_dot = TRUE;
1372 saw_flg = FALSE;
1373 break;
ea1562b3 1374
886a2506
NC		 1375 default:
1376 if (saw_flg && !saw_dot)
1377 goto err;
0d2bcfaf 1378
886a2506
NC		 1379 if (num_flags >= nflg)
1380 goto err;
0d2bcfaf 1381
692166c2
AB		 1382 flgnamelen = strspn (input_line_pointer,
1383 "abcdefghijklmnopqrstuvwxyz0123456789");
83cda17b 1384 if (flgnamelen > MAX_FLAG_NAME_LENGTH)
886a2506 1385 goto err;
0d2bcfaf 1386
886a2506 1387 memcpy (flags->name, input_line_pointer, flgnamelen);
0d2bcfaf 1388
886a2506
NC		 1389 input_line_pointer += flgnamelen;
1390 flags++;
1391 saw_dot = FALSE;
1392 saw_flg = TRUE;
1393 num_flags++;
1394 break;
1e07b820 1395 }
0d2bcfaf
NC		 1396 }
1397
886a2506
NC		 1398 fini:
1399 input_line_pointer = old_input_line_pointer;
1400 return num_flags;
0d2bcfaf 1401
886a2506
NC		 1402 err:
1403 if (saw_dot)
1404 as_bad (_("extra dot"));
1405 else if (!saw_flg)
1406 as_bad (_("unrecognized flag"));
1407 else
1408 as_bad (_("failed to parse flags"));
1409 input_line_pointer = old_input_line_pointer;
1410 return -1;
1411}
0d2bcfaf 1412
4670103e 1413/* Apply the fixups in order. */
0d2bcfaf 1414
4670103e
CZ		 1415static void
1416apply_fixups (struct arc_insn *insn, fragS *fragP, int fix)
886a2506 1417{
4670103e 1418 int i;
0d2bcfaf 1419
4670103e 1420 for (i = 0; i < insn->nfixups; i++)
252b5132 1421 {
4670103e
CZ		 1422 struct arc_fixup *fixup = &insn->fixups[i];
1423 int size, pcrel, offset = 0;
0d2bcfaf 1424
4670103e
CZ		 1425 /* FIXME! the reloc size is wrong in the BFD file.
1426 When it is fixed please delete me. */
91fdca6f 1427 size = ((insn->len == 2) && !fixup->islong) ? 2 : 4;
0d2bcfaf 1428
4670103e 1429 if (fixup->islong)
91fdca6f 1430 offset = insn->len;
252b5132 1431
4670103e
CZ		 1432 /* Some fixups are only used internally, thus no howto. */
1433 if ((int) fixup->reloc == 0)
1434 as_fatal (_("Unhandled reloc type"));
886a2506 1435
4670103e
CZ		 1436 if ((int) fixup->reloc < 0)
1437 {
1438 /* FIXME! the reloc size is wrong in the BFD file.
1439 When it is fixed please enable me.
91fdca6f 1440 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
4670103e
CZ		 1441 pcrel = fixup->pcrel;
1442 }
1443 else
1444 {
1445 reloc_howto_type *reloc_howto =
1446 bfd_reloc_type_lookup (stdoutput,
1447 (bfd_reloc_code_real_type) fixup->reloc);
1448 gas_assert (reloc_howto);
0d2bcfaf 1449
4670103e
CZ		 1450 /* FIXME! the reloc size is wrong in the BFD file.
1451 When it is fixed please enable me.
1452 size = bfd_get_reloc_size (reloc_howto); */
1453 pcrel = reloc_howto->pc_relative;
1454 }
0d2bcfaf 1455
4670103e
CZ		 1456 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1457offset %d + %d\n",
1458 fragP->fr_file, fragP->fr_line,
1459 (fixup->reloc < 0) ? "Internal" :
1460 bfd_get_reloc_code_name (fixup->reloc),
1461 pcrel ? "Y" : "N",
1462 size, fix, offset);
1463 fix_new_exp (fragP, fix + offset,
1464 size, &fixup->exp, pcrel, fixup->reloc);
0d2bcfaf 1465
4670103e
CZ		 1466 /* Check for ZOLs, and update symbol info if any. */
1467 if (LP_INSN (insn->insn))
886a2506 1468 {
4670103e
CZ		 1469 gas_assert (fixup->exp.X_add_symbol);
1470 ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL);
886a2506
NC		 1471 }
1472 }
252b5132
RH		 1473}
1474
4670103e 1475/* Actually output an instruction with its fixup. */
886a2506 1476
4670103e
CZ		 1477static void
1478emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax)
252b5132 1479{
4670103e 1480 char *f = where;
91fdca6f 1481 size_t total_len;
252b5132 1482
bdfe53e3
AB		 1483 pr_debug ("Emit insn : 0x%llx\n", insn->insn);
1484 pr_debug ("\tLength : 0x%d\n", insn->len);
4670103e 1485 pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
0d2bcfaf 1486
4670103e 1487 /* Write out the instruction. */
91fdca6f
GM		 1488 total_len = insn->len + (insn->has_limm ? 4 : 0);
1489 if (!relax)
1490 f = frag_more (total_len);
1491
1492 md_number_to_chars_midend(f, insn->insn, insn->len);
1493
1494 if (insn->has_limm)
1495 md_number_to_chars_midend (f + insn->len, insn->limm, 4);
1496 dwarf2_emit_insn (total_len);
252b5132 1497
4670103e
CZ		 1498 if (!relax)
1499 apply_fixups (insn, frag_now, (f - frag_now->fr_literal));
1500}
252b5132 1501
4670103e
CZ		 1502static void
1503emit_insn1 (struct arc_insn *insn)
1504{
1505 /* How frag_var's args are currently configured:
1506 - rs_machine_dependent, to dictate it's a relaxation frag.
1507 - FRAG_MAX_GROWTH, maximum size of instruction
1508 - 0, variable size that might grow...unused by generic relaxation.
1509 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1510 - s, opand expression.
1511 - 0, offset but it's unused.
1512 - 0, opcode but it's unused. */
1513 symbolS *s = make_expr_symbol (&insn->fixups[0].exp);
1514 frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel;
1515
1516 if (frag_room () < FRAG_MAX_GROWTH)
1517 {
1518 /* Handle differently when frag literal memory is exhausted.
1519 This is used because when there's not enough memory left in
1520 the current frag, a new frag is created and the information
1521 we put into frag_now->tc_frag_data is disregarded. */
252b5132 1522
4670103e
CZ		 1523 struct arc_relax_type relax_info_copy;
1524 relax_substateT subtype = frag_now->fr_subtype;
252b5132 1525
4670103e
CZ		 1526 memcpy (&relax_info_copy, &frag_now->tc_frag_data,
1527 sizeof (struct arc_relax_type));
0d2bcfaf 1528
4670103e
CZ		 1529 frag_wane (frag_now);
1530 frag_grow (FRAG_MAX_GROWTH);
0d2bcfaf 1531
4670103e
CZ		 1532 memcpy (&frag_now->tc_frag_data, &relax_info_copy,
1533 sizeof (struct arc_relax_type));
252b5132 1534
4670103e
CZ		 1535 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1536 subtype, s, 0, 0);
1537 }
1538 else
1539 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1540 frag_now->fr_subtype, s, 0, 0);
1541}
252b5132 1542
4670103e
CZ		 1543static void
1544emit_insn (struct arc_insn *insn)
252b5132 1545{
4670103e
CZ		 1546 if (insn->relax)
1547 emit_insn1 (insn);
252b5132 1548 else
4670103e 1549 emit_insn0 (insn, NULL, FALSE);
252b5132
RH		 1550}
1551
4670103e 1552/* Check whether a symbol involves a register. */
252b5132 1553
4670103e
CZ		 1554static bfd_boolean
1555contains_register (symbolS *sym)
252b5132 1556{
4670103e
CZ		 1557 if (sym)
1558 {
1559 expressionS *ex = symbol_get_value_expression (sym);
252b5132 1560
4670103e
CZ		 1561 return ((O_register == ex->X_op)
1562 && !contains_register (ex->X_add_symbol)
1563 && !contains_register (ex->X_op_symbol));
1564 }
1565
1566 return FALSE;
252b5132
RH		 1567}
1568
4670103e 1569/* Returns the register number within a symbol. */
252b5132 1570
4670103e
CZ		 1571static int
1572get_register (symbolS *sym)
252b5132 1573{
4670103e
CZ		 1574 if (!contains_register (sym))
1575 return -1;
0d2bcfaf 1576
4670103e
CZ		 1577 expressionS *ex = symbol_get_value_expression (sym);
1578 return regno (ex->X_add_number);
1579}
252b5132 1580
4670103e
CZ		 1581/* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1582 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
f17c130b 1583
4670103e
CZ		 1584static bfd_boolean
1585generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
1586{
1587 if (!reloc)
1588 return FALSE;
886a2506 1589
4670103e
CZ		 1590 switch (reloc)
1591 {
1592 case BFD_RELOC_ARC_SDA_LDST:
1593 case BFD_RELOC_ARC_SDA_LDST1:
1594 case BFD_RELOC_ARC_SDA_LDST2:
1595 case BFD_RELOC_ARC_SDA16_LD:
1596 case BFD_RELOC_ARC_SDA16_LD1:
1597 case BFD_RELOC_ARC_SDA16_LD2:
1598 case BFD_RELOC_ARC_SDA16_ST2:
1599 case BFD_RELOC_ARC_SDA32_ME:
1600 return FALSE;
1601 default:
1602 return TRUE;
f17c130b 1603 }
252b5132
RH		 1604}
1605
4670103e 1606/* Allocates a tok entry. */
252b5132 1607
4670103e
CZ		 1608static int
1609allocate_tok (expressionS *tok, int ntok, int cidx)
252b5132 1610{
4670103e
CZ		 1611 if (ntok > MAX_INSN_ARGS - 2)
1612 return 0; /* No space left. */
252b5132 1613
4670103e 1614 if (cidx > ntok)
33eaf5de 1615 return 0; /* Incorrect args. */
252b5132 1616
4670103e 1617 memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
252b5132 1618
4670103e
CZ		 1619 if (cidx == ntok)
1620 return 1; /* Success. */
1621 return allocate_tok (tok, ntok - 1, cidx);
1622}
886a2506 1623
8ddf6b2a
CZ		 1624/* Check if an particular ARC feature is enabled. */
1625
1626static bfd_boolean
1627check_cpu_feature (insn_subclass_t sc)
1628{
bb65a718 1629 if (is_code_density_p (sc) && !(selected_cpu.features & ARC_CD))
8ddf6b2a
CZ		 1630 return FALSE;
1631
bb65a718 1632 if (is_spfp_p (sc) && !(selected_cpu.features & ARC_SPFP))
8ddf6b2a
CZ		 1633 return FALSE;
1634
bb65a718 1635 if (is_dpfp_p (sc) && !(selected_cpu.features & ARC_DPFP))
8ddf6b2a
CZ		 1636 return FALSE;
1637
bb65a718 1638 if (is_fpuda_p (sc) && !(selected_cpu.features & ARC_FPUDA))
bdd582db
GM		 1639 return FALSE;
1640
bb65a718 1641 if (is_nps400_p (sc) && !(selected_cpu.features & ARC_NPS400))
8ddf6b2a
CZ		 1642 return FALSE;
1643
1644 return TRUE;
1645}
1646
4eb6f892
AB		 1647/* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1648 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1649 array and returns TRUE if the flag operands all match, otherwise,
1650 returns FALSE, in which case the FIRST_PFLAG array may have been
1651 modified. */
1652
1653static bfd_boolean
1654parse_opcode_flags (const struct arc_opcode *opcode,
1655 int nflgs,
1656 struct arc_flags *first_pflag)
1657{
1658 int lnflg, i;
1659 const unsigned char *flgidx;
1660
1661 lnflg = nflgs;
1662 for (i = 0; i < nflgs; i++)
1663 first_pflag[i].flgp = NULL;
1664
1665 /* Check the flags. Iterate over the valid flag classes. */
1666 for (flgidx = opcode->flags; *flgidx; ++flgidx)
1667 {
1668 /* Get a valid flag class. */
1669 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
1670 const unsigned *flgopridx;
1671 int cl_matches = 0;
1672 struct arc_flags *pflag = NULL;
1673
6ec7c1ae
CZ		 1674 /* Check if opcode has implicit flag classes. */
1675 if (cl_flags->flag_class & F_CLASS_IMPLICIT)
1676 continue;
1677
4eb6f892
AB		 1678 /* Check for extension conditional codes. */
1679 if (ext_condcode.arc_ext_condcode
1680 && cl_flags->flag_class & F_CLASS_EXTEND)
1681 {
1682 struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode;
1683 while (pf->name)
1684 {
1685 pflag = first_pflag;
1686 for (i = 0; i < nflgs; i++, pflag++)
1687 {
1688 if (!strcmp (pf->name, pflag->name))
1689 {
1690 if (pflag->flgp != NULL)
1691 return FALSE;
1692 /* Found it. */
1693 cl_matches++;
1694 pflag->flgp = pf;
1695 lnflg--;
1696 break;
1697 }
1698 }
1699 pf++;
1700 }
1701 }
1702
1703 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
1704 {
1705 const struct arc_flag_operand *flg_operand;
1706
1707 pflag = first_pflag;
1708 flg_operand = &arc_flag_operands[*flgopridx];
1709 for (i = 0; i < nflgs; i++, pflag++)
1710 {
1711 /* Match against the parsed flags. */
1712 if (!strcmp (flg_operand->name, pflag->name))
1713 {
1714 if (pflag->flgp != NULL)
1715 return FALSE;
1716 cl_matches++;
1717 pflag->flgp = flg_operand;
1718 lnflg--;
1719 break; /* goto next flag class and parsed flag. */
1720 }
1721 }
1722 }
1723
1724 if ((cl_flags->flag_class & F_CLASS_REQUIRED) && cl_matches == 0)
1725 return FALSE;
1726 if ((cl_flags->flag_class & F_CLASS_OPTIONAL) && cl_matches > 1)
1727 return FALSE;
1728 }
1729
1730 /* Did I check all the parsed flags? */
1731 return lnflg ? FALSE : TRUE;
1732}
1733
1734
4670103e
CZ		 1735/* Search forward through all variants of an opcode looking for a
1736 syntax match. */
886a2506 1737
4670103e 1738static const struct arc_opcode *
b9b47ab7 1739find_opcode_match (const struct arc_opcode_hash_entry *entry,
4670103e
CZ		 1740 expressionS *tok,
1741 int *pntok,
1742 struct arc_flags *first_pflag,
1743 int nflgs,
abe7c33b
CZ		 1744 int *pcpumatch,
1745 const char **errmsg)
4670103e 1746{
1328504b
AB		 1747 const struct arc_opcode *opcode;
1748 struct arc_opcode_hash_entry_iterator iter;
4670103e
CZ		 1749 int ntok = *pntok;
1750 int got_cpu_match = 0;
1751 expressionS bktok[MAX_INSN_ARGS];
1752 int bkntok;
1753 expressionS emptyE;
886a2506 1754
1328504b 1755 arc_opcode_hash_entry_iterator_init (&iter);
4670103e
CZ		 1756 memset (&emptyE, 0, sizeof (emptyE));
1757 memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
1758 bkntok = ntok;
a161fe53 1759
1328504b
AB		 1760 for (opcode = arc_opcode_hash_entry_iterator_next (entry, &iter);
1761 opcode != NULL;
1762 opcode = arc_opcode_hash_entry_iterator_next (entry, &iter))
252b5132 1763 {
4670103e 1764 const unsigned char *opidx;
4eb6f892 1765 int tokidx = 0;
4670103e 1766 const expressionS *t = &emptyE;
252b5132 1767
bdfe53e3 1768 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
4670103e 1769 frag_now->fr_file, frag_now->fr_line, opcode->opcode);
886a2506 1770
4670103e
CZ		 1771 /* Don't match opcodes that don't exist on this
1772 architecture. */
bb65a718 1773 if (!(opcode->cpu & selected_cpu.flags))
4670103e 1774 goto match_failed;
886a2506 1775
8ddf6b2a 1776 if (!check_cpu_feature (opcode->subclass))
4670103e 1777 goto match_failed;
886a2506 1778
4670103e
CZ		 1779 got_cpu_match = 1;
1780 pr_debug ("cpu ");
886a2506 1781
4670103e
CZ		 1782 /* Check the operands. */
1783 for (opidx = opcode->operands; *opidx; ++opidx)
252b5132 1784 {
4670103e 1785 const struct arc_operand *operand = &arc_operands[*opidx];
252b5132 1786
4670103e 1787 /* Only take input from real operands. */
db18dbab 1788 if (ARC_OPERAND_IS_FAKE (operand))
4670103e 1789 continue;
252b5132 1790
4670103e
CZ		 1791 /* When we expect input, make sure we have it. */
1792 if (tokidx >= ntok)
1793 goto match_failed;
6f4b1afc 1794
4670103e
CZ		 1795 /* Match operand type with expression type. */
1796 switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
1797 {
db18dbab 1798 case ARC_OPERAND_ADDRTYPE:
b437d035 1799 {
abe7c33b 1800 *errmsg = NULL;
b437d035
AB		 1801
1802 /* Check to be an address type. */
1803 if (tok[tokidx].X_op != O_addrtype)
1804 goto match_failed;
1805
1806 /* All address type operands need to have an insert
1807 method in order to check that we have the correct
1808 address type. */
1809 gas_assert (operand->insert != NULL);
1810 (*operand->insert) (0, tok[tokidx].X_add_number,
abe7c33b
CZ		 1811 errmsg);
1812 if (*errmsg != NULL)
b437d035
AB		 1813 goto match_failed;
1814 }
db18dbab
GM		 1815 break;
1816
4670103e
CZ		 1817 case ARC_OPERAND_IR:
1818 /* Check to be a register. */
1819 if ((tok[tokidx].X_op != O_register
1820 || !is_ir_num (tok[tokidx].X_add_number))
1821 && !(operand->flags & ARC_OPERAND_IGNORE))
1822 goto match_failed;
1823
1824 /* If expect duplicate, make sure it is duplicate. */
1825 if (operand->flags & ARC_OPERAND_DUPLICATE)
1826 {
1827 /* Check for duplicate. */
1828 if (t->X_op != O_register
1829 || !is_ir_num (t->X_add_number)
1830 || (regno (t->X_add_number) !=
1831 regno (tok[tokidx].X_add_number)))
1832 goto match_failed;
1833 }
1834
1835 /* Special handling? */
1836 if (operand->insert)
1837 {
abe7c33b 1838 *errmsg = NULL;
4670103e
CZ		 1839 (*operand->insert)(0,
1840 regno (tok[tokidx].X_add_number),
abe7c33b
CZ		 1841 errmsg);
1842 if (*errmsg)
4670103e
CZ		 1843 {
1844 if (operand->flags & ARC_OPERAND_IGNORE)
1845 {
1846 /* Missing argument, create one. */
1847 if (!allocate_tok (tok, ntok - 1, tokidx))
1848 goto match_failed;
1849
1850 tok[tokidx].X_op = O_absent;
1851 ++ntok;
1852 }
1853 else
1854 goto match_failed;
1855 }
1856 }
1857
1858 t = &tok[tokidx];
1859 break;
1860
1861 case ARC_OPERAND_BRAKET:
1862 /* Check if bracket is also in opcode table as
1863 operand. */
1864 if (tok[tokidx].X_op != O_bracket)
1865 goto match_failed;
1866 break;
1867
db18dbab
GM		 1868 case ARC_OPERAND_COLON:
1869 /* Check if colon is also in opcode table as operand. */
1870 if (tok[tokidx].X_op != O_colon)
1871 goto match_failed;
1872 break;
1873
4670103e
CZ		 1874 case ARC_OPERAND_LIMM:
1875 case ARC_OPERAND_SIGNED:
1876 case ARC_OPERAND_UNSIGNED:
1877 switch (tok[tokidx].X_op)
1878 {
1879 case O_illegal:
1880 case O_absent:
1881 case O_register:
1882 goto match_failed;
1883
1884 case O_bracket:
1885 /* Got an (too) early bracket, check if it is an
1886 ignored operand. N.B. This procedure works only
1887 when bracket is the last operand! */
1888 if (!(operand->flags & ARC_OPERAND_IGNORE))
1889 goto match_failed;
1890 /* Insert the missing operand. */
1891 if (!allocate_tok (tok, ntok - 1, tokidx))
1892 goto match_failed;
1893
1894 tok[tokidx].X_op = O_absent;
1895 ++ntok;
1896 break;
1897
22b92fc4
AB		 1898 case O_symbol:
1899 {
1900 const char *p;
22b92fc4 1901 const struct arc_aux_reg *auxr;
22b92fc4 1902
c810e0b8 1903 if (opcode->insn_class != AUXREG)
22b92fc4
AB		 1904 goto de_fault;
1905 p = S_GET_NAME (tok[tokidx].X_add_symbol);
f36e33da
CZ		 1906
1907 auxr = hash_find (arc_aux_hash, p);
1908 if (auxr)
1909 {
1910 /* We modify the token array here, safe in the
1911 knowledge, that if this was the wrong
1912 choice then the original contents will be
1913 restored from BKTOK. */
1914 tok[tokidx].X_op = O_constant;
1915 tok[tokidx].X_add_number = auxr->address;
1916 ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX);
1917 }
22b92fc4
AB		 1918
1919 if (tok[tokidx].X_op != O_constant)
1920 goto de_fault;
1921 }
1a0670f3 1922 /* Fall through. */
4670103e
CZ		 1923 case O_constant:
1924 /* Check the range. */
1925 if (operand->bits != 32
1926 && !(operand->flags & ARC_OPERAND_NCHK))
1927 {
1928 offsetT min, max, val;
1929 val = tok[tokidx].X_add_number;
1930
1931 if (operand->flags & ARC_OPERAND_SIGNED)
1932 {
1933 max = (1 << (operand->bits - 1)) - 1;
1934 min = -(1 << (operand->bits - 1));
1935 }
1936 else
1937 {
1938 max = (1 << operand->bits) - 1;
1939 min = 0;
1940 }
1941
1942 if (val < min || val > max)
1943 goto match_failed;
1944
33eaf5de 1945 /* Check alignments. */
4670103e
CZ		 1946 if ((operand->flags & ARC_OPERAND_ALIGNED32)
1947 && (val & 0x03))
1948 goto match_failed;
1949
1950 if ((operand->flags & ARC_OPERAND_ALIGNED16)
1951 && (val & 0x01))
1952 goto match_failed;
1953 }
1954 else if (operand->flags & ARC_OPERAND_NCHK)
1955 {
1956 if (operand->insert)
1957 {
abe7c33b 1958 *errmsg = NULL;
4670103e
CZ		 1959 (*operand->insert)(0,
1960 tok[tokidx].X_add_number,
abe7c33b
CZ		 1961 errmsg);
1962 if (*errmsg)
4670103e
CZ		 1963 goto match_failed;
1964 }
4eb6f892 1965 else if (!(operand->flags & ARC_OPERAND_IGNORE))
4670103e
CZ		 1966 goto match_failed;
1967 }
1968 break;
1969
1970 case O_subtract:
1971 /* Check if it is register range. */
1972 if ((tok[tokidx].X_add_number == 0)
1973 && contains_register (tok[tokidx].X_add_symbol)
1974 && contains_register (tok[tokidx].X_op_symbol))
1975 {
1976 int regs;
1977
1978 regs = get_register (tok[tokidx].X_add_symbol);
1979 regs <<= 16;
1980 regs |= get_register (tok[tokidx].X_op_symbol);
1981 if (operand->insert)
1982 {
abe7c33b 1983 *errmsg = NULL;
4670103e
CZ		 1984 (*operand->insert)(0,
1985 regs,
abe7c33b
CZ		 1986 errmsg);
1987 if (*errmsg)
4670103e
CZ		 1988 goto match_failed;
1989 }
1990 else
1991 goto match_failed;
1992 break;
1993 }
1a0670f3 1994 /* Fall through. */
4670103e 1995 default:
22b92fc4 1996 de_fault:
4670103e
CZ		 1997 if (operand->default_reloc == 0)
1998 goto match_failed; /* The operand needs relocation. */
1999
2000 /* Relocs requiring long immediate. FIXME! make it
2001 generic and move it to a function. */
2002 switch (tok[tokidx].X_md)
2003 {
2004 case O_gotoff:
2005 case O_gotpc:
2006 case O_pcl:
2007 case O_tpoff:
2008 case O_dtpoff:
2009 case O_tlsgd:
2010 case O_tlsie:
2011 if (!(operand->flags & ARC_OPERAND_LIMM))
2012 goto match_failed;
1a0670f3 2013 /* Fall through. */
4670103e
CZ		 2014 case O_absent:
2015 if (!generic_reloc_p (operand->default_reloc))
2016 goto match_failed;
2b804145 2017 break;
4670103e
CZ		 2018 default:
2019 break;
2020 }
2021 break;
2022 }
2023 /* If expect duplicate, make sure it is duplicate. */
2024 if (operand->flags & ARC_OPERAND_DUPLICATE)
2025 {
2026 if (t->X_op == O_illegal
2027 || t->X_op == O_absent
2028 || t->X_op == O_register
2029 || (t->X_add_number != tok[tokidx].X_add_number))
2030 goto match_failed;
2031 }
2032 t = &tok[tokidx];
2033 break;
2034
2035 default:
2036 /* Everything else should have been fake. */
2037 abort ();
2038 }
2039
2040 ++tokidx;
2041 }
2042 pr_debug ("opr ");
2043
1ae8ab47 2044 /* Setup ready for flag parsing. */
4eb6f892 2045 if (!parse_opcode_flags (opcode, nflgs, first_pflag))
4670103e
CZ		 2046 goto match_failed;
2047
2048 pr_debug ("flg");
2049 /* Possible match -- did we use all of our input? */
2050 if (tokidx == ntok)
2051 {
2052 *pntok = ntok;
2053 pr_debug ("\n");
2054 return opcode;
2055 }
2056
2057 match_failed:;
2058 pr_debug ("\n");
2059 /* Restore the original parameters. */
2060 memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
2061 ntok = bkntok;
2062 }
4670103e
CZ		 2063
2064 if (*pcpumatch)
2065 *pcpumatch = got_cpu_match;
2066
2067 return NULL;
2068}
2069
2070/* Swap operand tokens. */
2071
2072static void
2073swap_operand (expressionS *operand_array,
2074 unsigned source,
2075 unsigned destination)
2076{
2077 expressionS cpy_operand;
2078 expressionS *src_operand;
2079 expressionS *dst_operand;
2080 size_t size;
2081
2082 if (source == destination)
2083 return;
2084
2085 src_operand = &operand_array[source];
2086 dst_operand = &operand_array[destination];
2087 size = sizeof (expressionS);
2088
2089 /* Make copy of operand to swap with and swap. */
2090 memcpy (&cpy_operand, dst_operand, size);
2091 memcpy (dst_operand, src_operand, size);
2092 memcpy (src_operand, &cpy_operand, size);
2093}
2094
2095/* Check if *op matches *tok type.
2096 Returns FALSE if they don't match, TRUE if they match. */
2097
2098static bfd_boolean
2099pseudo_operand_match (const expressionS *tok,
2100 const struct arc_operand_operation *op)
2101{
2102 offsetT min, max, val;
2103 bfd_boolean ret;
2104 const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
2105
2106 ret = FALSE;
2107 switch (tok->X_op)
2108 {
2109 case O_constant:
2110 if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM))
2111 ret = 1;
2112 else if (!(operand_real->flags & ARC_OPERAND_IR))
2113 {
2114 val = tok->X_add_number + op->count;
2115 if (operand_real->flags & ARC_OPERAND_SIGNED)
2116 {
2117 max = (1 << (operand_real->bits - 1)) - 1;
2118 min = -(1 << (operand_real->bits - 1));
2119 }
2120 else
2121 {
2122 max = (1 << operand_real->bits) - 1;
2123 min = 0;
2124 }
2125 if (min <= val && val <= max)
2126 ret = TRUE;
2127 }
6f4b1afc
CM		 2128 break;
2129
4670103e
CZ		 2130 case O_symbol:
2131 /* Handle all symbols as long immediates or signed 9. */
db18dbab
GM		 2132 if (operand_real->flags & ARC_OPERAND_LIMM
2133 || ((operand_real->flags & ARC_OPERAND_SIGNED)
2134 && operand_real->bits == 9))
4670103e 2135 ret = TRUE;
6f4b1afc
CM		 2136 break;
2137
4670103e
CZ		 2138 case O_register:
2139 if (operand_real->flags & ARC_OPERAND_IR)
2140 ret = TRUE;
2141 break;
2142
2143 case O_bracket:
2144 if (operand_real->flags & ARC_OPERAND_BRAKET)
2145 ret = TRUE;
6f4b1afc
CM		 2146 break;
2147
2148 default:
4670103e 2149 /* Unknown. */
6f4b1afc
CM		 2150 break;
2151 }
4670103e
CZ		 2152 return ret;
2153}
6f4b1afc 2154
4670103e
CZ		 2155/* Find pseudo instruction in array. */
2156
2157static const struct arc_pseudo_insn *
2158find_pseudo_insn (const char *opname,
2159 int ntok,
2160 const expressionS *tok)
2161{
2162 const struct arc_pseudo_insn *pseudo_insn = NULL;
2163 const struct arc_operand_operation *op;
2164 unsigned int i;
2165 int j;
2166
2167 for (i = 0; i < arc_num_pseudo_insn; ++i)
6f4b1afc 2168 {
4670103e
CZ		 2169 pseudo_insn = &arc_pseudo_insns[i];
2170 if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
2171 {
2172 op = pseudo_insn->operand;
2173 for (j = 0; j < ntok; ++j)
2174 if (!pseudo_operand_match (&tok[j], &op[j]))
2175 break;
2176
2177 /* Found the right instruction. */
2178 if (j == ntok)
2179 return pseudo_insn;
2180 }
6f4b1afc 2181 }
4670103e
CZ		 2182 return NULL;
2183}
252b5132 2184
4670103e 2185/* Assumes the expressionS *tok is of sufficient size. */
252b5132 2186
b9b47ab7 2187static const struct arc_opcode_hash_entry *
4670103e
CZ		 2188find_special_case_pseudo (const char *opname,
2189 int *ntok,
2190 expressionS *tok,
2191 int *nflgs,
2192 struct arc_flags *pflags)
2193{
2194 const struct arc_pseudo_insn *pseudo_insn = NULL;
2195 const struct arc_operand_operation *operand_pseudo;
2196 const struct arc_operand *operand_real;
2197 unsigned i;
2198 char construct_operand[MAX_CONSTR_STR];
886a2506 2199
4670103e
CZ		 2200 /* Find whether opname is in pseudo instruction array. */
2201 pseudo_insn = find_pseudo_insn (opname, *ntok, tok);
2202
2203 if (pseudo_insn == NULL)
2204 return NULL;
2205
2206 /* Handle flag, Limited to one flag at the moment. */
2207 if (pseudo_insn->flag_r != NULL)
2208 *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs],
2209 MAX_INSN_FLGS - *nflgs);
2210
2211 /* Handle operand operations. */
2212 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
252b5132 2213 {
4670103e
CZ		 2214 operand_pseudo = &pseudo_insn->operand[i];
2215 operand_real = &arc_operands[operand_pseudo->operand_idx];
886a2506 2216
db18dbab
GM		 2217 if (operand_real->flags & ARC_OPERAND_BRAKET
2218 && !operand_pseudo->needs_insert)
4670103e 2219 continue;
b125bd17 2220
4670103e
CZ		 2221 /* Has to be inserted (i.e. this token does not exist yet). */
2222 if (operand_pseudo->needs_insert)
2223 {
2224 if (operand_real->flags & ARC_OPERAND_BRAKET)
2225 {
2226 tok[i].X_op = O_bracket;
2227 ++(*ntok);
2228 continue;
2229 }
b125bd17 2230
4670103e
CZ		 2231 /* Check if operand is a register or constant and handle it
2232 by type. */
2233 if (operand_real->flags & ARC_OPERAND_IR)
2234 snprintf (construct_operand, MAX_CONSTR_STR, "r%d",
2235 operand_pseudo->count);
2236 else
2237 snprintf (construct_operand, MAX_CONSTR_STR, "%d",
2238 operand_pseudo->count);
886a2506 2239
4670103e
CZ		 2240 tokenize_arguments (construct_operand, &tok[i], 1);
2241 ++(*ntok);
2242 }
2243
2244 else if (operand_pseudo->count)
2245 {
2246 /* Operand number has to be adjusted accordingly (by operand
2247 type). */
2248 switch (tok[i].X_op)
2249 {
2250 case O_constant:
2251 tok[i].X_add_number += operand_pseudo->count;
2252 break;
2253
2254 case O_symbol:
2255 break;
2256
2257 default:
2258 /* Ignored. */
2259 break;
2260 }
2261 }
2262 }
2263
2264 /* Swap operands if necessary. Only supports one swap at the
2265 moment. */
2266 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
2267 {
2268 operand_pseudo = &pseudo_insn->operand[i];
2269
2270 if (operand_pseudo->swap_operand_idx == i)
2271 continue;
2272
2273 swap_operand (tok, i, operand_pseudo->swap_operand_idx);
2274
2275 /* Prevent a swap back later by breaking out. */
2276 break;
2277 }
2278
da5be039 2279 return arc_find_opcode (pseudo_insn->mnemonic_r);
4670103e
CZ		 2280}
2281
b9b47ab7 2282static const struct arc_opcode_hash_entry *
4670103e
CZ		 2283find_special_case_flag (const char *opname,
2284 int *nflgs,
2285 struct arc_flags *pflags)
2286{
2287 unsigned int i;
2288 const char *flagnm;
2289 unsigned flag_idx, flag_arr_idx;
2290 size_t flaglen, oplen;
2291 const struct arc_flag_special *arc_flag_special_opcode;
b9b47ab7 2292 const struct arc_opcode_hash_entry *entry;
4670103e
CZ		 2293
2294 /* Search for special case instruction. */
2295 for (i = 0; i < arc_num_flag_special; i++)
2296 {
2297 arc_flag_special_opcode = &arc_flag_special_cases[i];
2298 oplen = strlen (arc_flag_special_opcode->name);
2299
2300 if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0)
2301 continue;
2302
2303 /* Found a potential special case instruction, now test for
2304 flags. */
2305 for (flag_arr_idx = 0;; ++flag_arr_idx)
2306 {
2307 flag_idx = arc_flag_special_opcode->flags[flag_arr_idx];
2308 if (flag_idx == 0)
2309 break; /* End of array, nothing found. */
886a2506 2310
4670103e
CZ		 2311 flagnm = arc_flag_operands[flag_idx].name;
2312 flaglen = strlen (flagnm);
2313 if (strcmp (opname + oplen, flagnm) == 0)
2314 {
b9b47ab7 2315 entry = arc_find_opcode (arc_flag_special_opcode->name);
886a2506 2316
4670103e
CZ		 2317 if (*nflgs + 1 > MAX_INSN_FLGS)
2318 break;
2319 memcpy (pflags[*nflgs].name, flagnm, flaglen);
2320 pflags[*nflgs].name[flaglen] = '\0';
2321 (*nflgs)++;
b9b47ab7 2322 return entry;
4670103e
CZ		 2323 }
2324 }
2325 }
2326 return NULL;
2327}
886a2506 2328
4670103e 2329/* Used to find special case opcode. */
886a2506 2330
b9b47ab7 2331static const struct arc_opcode_hash_entry *
4670103e
CZ		 2332find_special_case (const char *opname,
2333 int *nflgs,
2334 struct arc_flags *pflags,
2335 expressionS *tok,
2336 int *ntok)
2337{
b9b47ab7 2338 const struct arc_opcode_hash_entry *entry;
886a2506 2339
b9b47ab7 2340 entry = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
886a2506 2341
b9b47ab7
AB		 2342 if (entry == NULL)
2343 entry = find_special_case_flag (opname, nflgs, pflags);
886a2506 2344
b9b47ab7 2345 return entry;
4670103e 2346}
886a2506 2347
33eaf5de 2348/* Given an opcode name, pre-tokenized set of arguments and the
4670103e 2349 opcode flags, take it all the way through emission. */
886a2506 2350
4670103e
CZ		 2351static void
2352assemble_tokens (const char *opname,
2353 expressionS *tok,
2354 int ntok,
2355 struct arc_flags *pflags,
2356 int nflgs)
2357{
2358 bfd_boolean found_something = FALSE;
b9b47ab7 2359 const struct arc_opcode_hash_entry *entry;
4670103e 2360 int cpumatch = 1;
abe7c33b 2361 const char *errmsg = NULL;
886a2506 2362
4670103e 2363 /* Search opcodes. */
b9b47ab7 2364 entry = arc_find_opcode (opname);
886a2506 2365
4670103e 2366 /* Couldn't find opcode conventional way, try special cases. */
b9b47ab7
AB		 2367 if (entry == NULL)
2368 entry = find_special_case (opname, &nflgs, pflags, tok, &ntok);
886a2506 2369
b9b47ab7 2370 if (entry != NULL)
4670103e 2371 {
b9b47ab7
AB		 2372 const struct arc_opcode *opcode;
2373
1328504b
AB		 2374 pr_debug ("%s:%d: assemble_tokens: %s\n",
2375 frag_now->fr_file, frag_now->fr_line, opname);
4670103e 2376 found_something = TRUE;
b9b47ab7 2377 opcode = find_opcode_match (entry, tok, &ntok, pflags,
abe7c33b 2378 nflgs, &cpumatch, &errmsg);
b9b47ab7 2379 if (opcode != NULL)
4670103e
CZ		 2380 {
2381 struct arc_insn insn;
b9b47ab7 2382
4670103e
CZ		 2383 assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
2384 emit_insn (&insn);
2385 return;
2386 }
2387 }
886a2506 2388
4670103e
CZ		 2389 if (found_something)
2390 {
2391 if (cpumatch)
abe7c33b
CZ		 2392 if (errmsg)
2393 as_bad (_("%s for instruction '%s'"), errmsg, opname);
2394 else
2395 as_bad (_("inappropriate arguments for opcode '%s'"), opname);
4670103e
CZ		 2396 else
2397 as_bad (_("opcode '%s' not supported for target %s"), opname,
bb65a718 2398 selected_cpu.name);
4670103e
CZ		 2399 }
2400 else
2401 as_bad (_("unknown opcode '%s'"), opname);
886a2506
NC		 2402}
2403
4670103e 2404/* The public interface to the instruction assembler. */
886a2506 2405
4670103e
CZ		 2406void
2407md_assemble (char *str)
886a2506 2408{
4670103e
CZ		 2409 char *opname;
2410 expressionS tok[MAX_INSN_ARGS];
2411 int ntok, nflg;
2412 size_t opnamelen;
2413 struct arc_flags flags[MAX_INSN_FLGS];
886a2506 2414
4670103e
CZ		 2415 /* Split off the opcode. */
2416 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468");
29a2809e 2417 opname = xmemdup0 (str, opnamelen);
886a2506 2418
33eaf5de 2419 /* Signalize we are assembling the instructions. */
4670103e 2420 assembling_insn = TRUE;
886a2506 2421
4670103e
CZ		 2422 /* Tokenize the flags. */
2423 if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
2424 {
2425 as_bad (_("syntax error"));
2426 return;
2427 }
886a2506 2428
4670103e
CZ		 2429 /* Scan up to the end of the mnemonic which must end in space or end
2430 of string. */
2431 str += opnamelen;
2432 for (; *str != '\0'; str++)
2433 if (*str == ' ')
2434 break;
886a2506 2435
4670103e
CZ		 2436 /* Tokenize the rest of the line. */
2437 if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0)
886a2506 2438 {
4670103e
CZ		 2439 as_bad (_("syntax error"));
2440 return;
252b5132
RH		 2441 }
2442
4670103e
CZ		 2443 /* Finish it off. */
2444 assemble_tokens (opname, tok, ntok, flags, nflg);
2445 assembling_insn = FALSE;
2446}
2447
2448/* Callback to insert a register into the hash table. */
2449
2450static void
f86f5863 2451declare_register (const char *name, int number)
4670103e
CZ		 2452{
2453 const char *err;
2454 symbolS *regS = symbol_create (name, reg_section,
2455 number, &zero_address_frag);
2456
2457 err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS);
2458 if (err)
e6ba1cba 2459 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
4670103e
CZ		 2460 name, err);
2461}
252b5132 2462
4670103e 2463/* Construct symbols for each of the general registers. */
252b5132 2464
4670103e
CZ		 2465static void
2466declare_register_set (void)
2467{
2468 int i;
2469 for (i = 0; i < 64; ++i)
886a2506 2470 {
4670103e
CZ		 2471 char name[7];
2472
2473 sprintf (name, "r%d", i);
2474 declare_register (name, i);
2475 if ((i & 0x01) == 0)
886a2506 2476 {
4670103e
CZ		 2477 sprintf (name, "r%dr%d", i, i+1);
2478 declare_register (name, i);
886a2506
NC		 2479 }
2480 }
252b5132 2481}
ea1562b3 2482
db18dbab
GM		 2483/* Construct a symbol for an address type. */
2484
2485static void
2486declare_addrtype (const char *name, int number)
2487{
2488 const char *err;
2489 symbolS *addrtypeS = symbol_create (name, undefined_section,
2490 number, &zero_address_frag);
2491
2492 err = hash_insert (arc_addrtype_hash, S_GET_NAME (addrtypeS),
2493 (void *) addrtypeS);
2494 if (err)
2495 as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
2496 name, err);
2497}
2498
4670103e
CZ		 2499/* Port-specific assembler initialization. This function is called
2500 once, at assembler startup time. */
ea1562b3
NC		 2501
2502void
4670103e 2503md_begin (void)
ea1562b3 2504{
b99747ae 2505 const struct arc_opcode *opcode = arc_opcodes;
886a2506 2506
bb65a718
AB		 2507 if (mach_selection_mode == MACH_SELECTION_NONE)
2508 arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT);
24740d83 2509
4670103e
CZ		 2510 /* The endianness can be chosen "at the factory". */
2511 target_big_endian = byte_order == BIG_ENDIAN;
886a2506 2512
bb65a718 2513 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
4670103e
CZ		 2514 as_warn (_("could not set architecture and machine"));
2515
2516 /* Set elf header flags. */
bb65a718 2517 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
4670103e
CZ		 2518
2519 /* Set up a hash table for the instructions. */
2520 arc_opcode_hash = hash_new ();
2521 if (arc_opcode_hash == NULL)
2522 as_fatal (_("Virtual memory exhausted"));
2523
2524 /* Initialize the hash table with the insns. */
b99747ae 2525 do
ea1562b3 2526 {
b99747ae 2527 const char *name = opcode->name;
da5be039 2528
b99747ae 2529 arc_insert_opcode (opcode);
4670103e 2530
b99747ae
CZ		 2531 while (++opcode && opcode->name
2532 && (opcode->name == name
2533 || !strcmp (opcode->name, name)))
4670103e 2534 continue;
b99747ae 2535 }while (opcode->name);
4670103e
CZ		 2536
2537 /* Register declaration. */
2538 arc_reg_hash = hash_new ();
2539 if (arc_reg_hash == NULL)
2540 as_fatal (_("Virtual memory exhausted"));
2541
2542 declare_register_set ();
2543 declare_register ("gp", 26);
2544 declare_register ("fp", 27);
2545 declare_register ("sp", 28);
2546 declare_register ("ilink", 29);
2547 declare_register ("ilink1", 29);
2548 declare_register ("ilink2", 30);
2549 declare_register ("blink", 31);
2550
87789e08
CZ		 2551 /* XY memory registers. */
2552 declare_register ("x0_u0", 32);
2553 declare_register ("x0_u1", 33);
2554 declare_register ("x1_u0", 34);
2555 declare_register ("x1_u1", 35);
2556 declare_register ("x2_u0", 36);
2557 declare_register ("x2_u1", 37);
2558 declare_register ("x3_u0", 38);
2559 declare_register ("x3_u1", 39);
2560 declare_register ("y0_u0", 40);
2561 declare_register ("y0_u1", 41);
2562 declare_register ("y1_u0", 42);
2563 declare_register ("y1_u1", 43);
2564 declare_register ("y2_u0", 44);
2565 declare_register ("y2_u1", 45);
2566 declare_register ("y3_u0", 46);
2567 declare_register ("y3_u1", 47);
2568 declare_register ("x0_nu", 48);
2569 declare_register ("x1_nu", 49);
2570 declare_register ("x2_nu", 50);
2571 declare_register ("x3_nu", 51);
2572 declare_register ("y0_nu", 52);
2573 declare_register ("y1_nu", 53);
2574 declare_register ("y2_nu", 54);
2575 declare_register ("y3_nu", 55);
2576
4670103e
CZ		 2577 declare_register ("mlo", 57);
2578 declare_register ("mmid", 58);
2579 declare_register ("mhi", 59);
2580
2581 declare_register ("acc1", 56);
2582 declare_register ("acc2", 57);
2583
2584 declare_register ("lp_count", 60);
2585 declare_register ("pcl", 63);
2586
2587 /* Initialize the last instructions. */
2588 memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
f36e33da
CZ		 2589
2590 /* Aux register declaration. */
2591 arc_aux_hash = hash_new ();
2592 if (arc_aux_hash == NULL)
2593 as_fatal (_("Virtual memory exhausted"));
2594
2595 const struct arc_aux_reg *auxr = &arc_aux_regs[0];
2596 unsigned int i;
2597 for (i = 0; i < arc_num_aux_regs; i++, auxr++)
2598 {
2599 const char *retval;
2600
bb65a718 2601 if (!(auxr->cpu & selected_cpu.flags))
f36e33da
CZ		 2602 continue;
2603
2604 if ((auxr->subclass != NONE)
2605 && !check_cpu_feature (auxr->subclass))
2606 continue;
2607
2608 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
2609 if (retval)
2610 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2611 auxr->name, retval);
2612 }
db18dbab
GM		 2613
2614 /* Address type declaration. */
2615 arc_addrtype_hash = hash_new ();
2616 if (arc_addrtype_hash == NULL)
2617 as_fatal (_("Virtual memory exhausted"));
2618
2619 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD);
2620 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID);
2621 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD);
2622 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD);
2623 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD);
2624 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM);
2625 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA);
2626 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD);
2627 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD);
2628 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD);
2629 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID);
2630 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD);
2631 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM);
2632 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD);
2633 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA);
2634 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD);
886a2506 2635}
ea1562b3 2636
4670103e
CZ		 2637/* Write a value out to the object file, using the appropriate
2638 endianness. */
ea1562b3 2639
4670103e
CZ		 2640void
2641md_number_to_chars (char *buf,
2642 valueT val,
2643 int n)
886a2506 2644{
4670103e
CZ		 2645 if (target_big_endian)
2646 number_to_chars_bigendian (buf, val, n);
2647 else
2648 number_to_chars_littleendian (buf, val, n);
886a2506 2649}
ea1562b3 2650
4670103e 2651/* Round up a section size to the appropriate boundary. */
ea1562b3 2652
4670103e
CZ		 2653valueT
2654md_section_align (segT segment,
2655 valueT size)
886a2506 2656{
4670103e
CZ		 2657 int align = bfd_get_section_alignment (stdoutput, segment);
2658
2659 return ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
886a2506 2660}
ea1562b3 2661
4670103e
CZ		 2662/* The location from which a PC relative jump should be calculated,
2663 given a PC relative reloc. */
ea1562b3 2664
4670103e
CZ		 2665long
2666md_pcrel_from_section (fixS *fixP,
2667 segT sec)
886a2506 2668{
4670103e 2669 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
ea1562b3 2670
4670103e 2671 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset);
ea1562b3 2672
4670103e
CZ		 2673 if (fixP->fx_addsy != (symbolS *) NULL
2674 && (!S_IS_DEFINED (fixP->fx_addsy)
2675 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
2676 {
2677 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy));
ea1562b3 2678
4670103e
CZ		 2679 /* The symbol is undefined (or is defined but not in this section).
2680 Let the linker figure it out. */
2681 return 0;
2682 }
2683
2684 if ((int) fixP->fx_r_type < 0)
886a2506 2685 {
4670103e
CZ		 2686 /* These are the "internal" relocations. Align them to
2687 32 bit boundary (PCL), for the moment. */
2688 base &= ~3;
886a2506 2689 }
4670103e
CZ		 2690 else
2691 {
2692 switch (fixP->fx_r_type)
2693 {
2694 case BFD_RELOC_ARC_PC32:
2695 /* The hardware calculates relative to the start of the
2696 insn, but this relocation is relative to location of the
2697 LIMM, compensate. The base always needs to be
2b0f3761 2698 subtracted by 4 as we do not support this type of PCrel
4670103e
CZ		 2699 relocation for short instructions. */
2700 base -= 4;
2701 /* Fall through. */
2702 case BFD_RELOC_ARC_PLT32:
2703 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2704 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2705 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2706 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2707
2708 case BFD_RELOC_ARC_S21H_PCREL:
2709 case BFD_RELOC_ARC_S25H_PCREL:
2710 case BFD_RELOC_ARC_S13_PCREL:
2711 case BFD_RELOC_ARC_S21W_PCREL:
2712 case BFD_RELOC_ARC_S25W_PCREL:
2713 base &= ~3;
2714 break;
2715 default:
2716 as_bad_where (fixP->fx_file, fixP->fx_line,
2717 _("unhandled reloc %s in md_pcrel_from_section"),
2718 bfd_get_reloc_code_name (fixP->fx_r_type));
2719 break;
2720 }
2721 }
2722
9e32d9ae
AB		 2723 pr_debug ("pcrel from %"BFD_VMA_FMT"x + %lx = %"BFD_VMA_FMT"x, "
2724 "symbol: %s (%"BFD_VMA_FMT"x)\n",
4670103e
CZ		 2725 fixP->fx_frag->fr_address, fixP->fx_where, base,
2726 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
2727 fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0);
2728
2729 return base;
886a2506 2730}
ea1562b3 2731
33eaf5de 2732/* Given a BFD relocation find the corresponding operand. */
ea1562b3 2733
4670103e
CZ		 2734static const struct arc_operand *
2735find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
2736{
2737 unsigned i;
ea1562b3 2738
4670103e
CZ		 2739 for (i = 0; i < arc_num_operands; i++)
2740 if (arc_operands[i].default_reloc == reloc)
2741 return &arc_operands[i];
2742 return NULL;
2743}
ea1562b3 2744
4670103e 2745/* Insert an operand value into an instruction. */
ea1562b3 2746
bdfe53e3
AB		 2747static unsigned long long
2748insert_operand (unsigned long long insn,
4670103e 2749 const struct arc_operand *operand,
bdfe53e3 2750 long long val,
3b4dbbbf 2751 const char *file,
4670103e 2752 unsigned line)
886a2506 2753{
4670103e 2754 offsetT min = 0, max = 0;
ea1562b3 2755
4670103e
CZ		 2756 if (operand->bits != 32
2757 && !(operand->flags & ARC_OPERAND_NCHK)
2758 && !(operand->flags & ARC_OPERAND_FAKE))
886a2506 2759 {
4670103e
CZ		 2760 if (operand->flags & ARC_OPERAND_SIGNED)
2761 {
2762 max = (1 << (operand->bits - 1)) - 1;
2763 min = -(1 << (operand->bits - 1));
2764 }
2765 else
2766 {
2767 max = (1 << operand->bits) - 1;
2768 min = 0;
2769 }
886a2506 2770
4670103e
CZ		 2771 if (val < min || val > max)
2772 as_bad_value_out_of_range (_("operand"),
2773 val, min, max, file, line);
2774 }
ea1562b3 2775
cc07cda6 2776 pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n",
4670103e 2777 min, val, max, insn);
ea1562b3 2778
4670103e
CZ		 2779 if ((operand->flags & ARC_OPERAND_ALIGNED32)
2780 && (val & 0x03))
2781 as_bad_where (file, line,
2782 _("Unaligned operand. Needs to be 32bit aligned"));
ea1562b3 2783
4670103e
CZ		 2784 if ((operand->flags & ARC_OPERAND_ALIGNED16)
2785 && (val & 0x01))
2786 as_bad_where (file, line,
2787 _("Unaligned operand. Needs to be 16bit aligned"));
ea1562b3 2788
4670103e
CZ		 2789 if (operand->insert)
2790 {
2791 const char *errmsg = NULL;
ea1562b3 2792
4670103e
CZ		 2793 insn = (*operand->insert) (insn, val, &errmsg);
2794 if (errmsg)
2795 as_warn_where (file, line, "%s", errmsg);
2796 }
2797 else
2798 {
2799 if (operand->flags & ARC_OPERAND_TRUNCATE)
2800 {
2801 if (operand->flags & ARC_OPERAND_ALIGNED32)
2802 val >>= 2;
2803 if (operand->flags & ARC_OPERAND_ALIGNED16)
2804 val >>= 1;
886a2506 2805 }
4670103e
CZ		 2806 insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
2807 }
2808 return insn;
2809}
ea1562b3 2810
4670103e
CZ		 2811/* Apply a fixup to the object code. At this point all symbol values
2812 should be fully resolved, and we attempt to completely resolve the
2813 reloc. If we can not do that, we determine the correct reloc code
2814 and put it back in the fixup. To indicate that a fixup has been
2815 eliminated, set fixP->fx_done. */
ea1562b3 2816
4670103e
CZ		 2817void
2818md_apply_fix (fixS *fixP,
2819 valueT *valP,
2820 segT seg)
2821{
2822 char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
2823 valueT value = *valP;
2824 unsigned insn = 0;
2825 symbolS *fx_addsy, *fx_subsy;
2826 offsetT fx_offset;
2827 segT add_symbol_segment = absolute_section;
2828 segT sub_symbol_segment = absolute_section;
2829 const struct arc_operand *operand = NULL;
2830 extended_bfd_reloc_code_real_type reloc;
886a2506 2831
4670103e
CZ		 2832 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2833 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2834 ((int) fixP->fx_r_type < 0) ? "Internal":
2835 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2836 fixP->fx_offset);
886a2506 2837
4670103e
CZ		 2838 fx_addsy = fixP->fx_addsy;
2839 fx_subsy = fixP->fx_subsy;
2840 fx_offset = 0;
886a2506 2841
4670103e
CZ		 2842 if (fx_addsy)
2843 {
2844 add_symbol_segment = S_GET_SEGMENT (fx_addsy);
886a2506
NC		 2845 }
2846
4670103e
CZ		 2847 if (fx_subsy
2848 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
2849 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
2850 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
2851 {
2852 resolve_symbol_value (fx_subsy);
2853 sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
886a2506 2854
4670103e
CZ		 2855 if (sub_symbol_segment == absolute_section)
2856 {
2857 /* The symbol is really a constant. */
2858 fx_offset -= S_GET_VALUE (fx_subsy);
2859 fx_subsy = NULL;
2860 }
2861 else
2862 {
2863 as_bad_where (fixP->fx_file, fixP->fx_line,
2864 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2865 fx_addsy ? S_GET_NAME (fx_addsy) : "0",
2866 segment_name (add_symbol_segment),
2867 S_GET_NAME (fx_subsy),
2868 segment_name (sub_symbol_segment));
2869 return;
2870 }
2871 }
886a2506 2872
4670103e
CZ		 2873 if (fx_addsy
2874 && !S_IS_WEAK (fx_addsy))
2875 {
2876 if (add_symbol_segment == seg
2877 && fixP->fx_pcrel)
2878 {
2879 value += S_GET_VALUE (fx_addsy);
2880 value -= md_pcrel_from_section (fixP, seg);
2881 fx_addsy = NULL;
2882 fixP->fx_pcrel = FALSE;
2883 }
2884 else if (add_symbol_segment == absolute_section)
2885 {
2886 value = fixP->fx_offset;
2887 fx_offset += S_GET_VALUE (fixP->fx_addsy);
2888 fx_addsy = NULL;
2889 fixP->fx_pcrel = FALSE;
2890 }
2891 }
886a2506 2892
4670103e
CZ		 2893 if (!fx_addsy)
2894 fixP->fx_done = TRUE;
886a2506 2895
4670103e 2896 if (fixP->fx_pcrel)
886a2506 2897 {
4670103e
CZ		 2898 if (fx_addsy
2899 && ((S_IS_DEFINED (fx_addsy)
2900 && S_GET_SEGMENT (fx_addsy) != seg)
2901 || S_IS_WEAK (fx_addsy)))
2902 value += md_pcrel_from_section (fixP, seg);
886a2506 2903
4670103e
CZ		 2904 switch (fixP->fx_r_type)
2905 {
2906 case BFD_RELOC_ARC_32_ME:
2907 /* This is a pc-relative value in a LIMM. Adjust it to the
2908 address of the instruction not to the address of the
33eaf5de 2909 LIMM. Note: it is not any longer valid this affirmation as
4670103e
CZ		 2910 the linker consider ARC_PC32 a fixup to entire 64 bit
2911 insn. */
2912 fixP->fx_offset += fixP->fx_frag->fr_address;
2913 /* Fall through. */
2914 case BFD_RELOC_32:
2915 fixP->fx_r_type = BFD_RELOC_ARC_PC32;
2916 /* Fall through. */
2917 case BFD_RELOC_ARC_PC32:
2918 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
886a2506
NC		 2919 break;
2920 default:
4670103e
CZ		 2921 if ((int) fixP->fx_r_type < 0)
2922 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2923 fixP->fx_r_type);
886a2506 2924 break;
ea1562b3
NC		 2925 }
2926 }
2927
4670103e
CZ		 2928 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2929 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2930 ((int) fixP->fx_r_type < 0) ? "Internal":
2931 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2932 fixP->fx_offset);
886a2506 2933
886a2506 2934
4670103e
CZ		 2935 /* Now check for TLS relocations. */
2936 reloc = fixP->fx_r_type;
2937 switch (reloc)
886a2506 2938 {
4670103e
CZ		 2939 case BFD_RELOC_ARC_TLS_DTPOFF:
2940 case BFD_RELOC_ARC_TLS_LE_32:
2941 if (fixP->fx_done)
2942 break;
2943 /* Fall through. */
2944 case BFD_RELOC_ARC_TLS_GD_GOT:
2945 case BFD_RELOC_ARC_TLS_IE_GOT:
2946 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2947 break;
886a2506 2948
4670103e
CZ		 2949 case BFD_RELOC_ARC_TLS_GD_LD:
2950 gas_assert (!fixP->fx_offset);
2951 if (fixP->fx_subsy)
2952 fixP->fx_offset
2953 = (S_GET_VALUE (fixP->fx_subsy)
2954 - fixP->fx_frag->fr_address- fixP->fx_where);
2955 fixP->fx_subsy = NULL;
2956 /* Fall through. */
2957 case BFD_RELOC_ARC_TLS_GD_CALL:
2958 /* These two relocs are there just to allow ld to change the tls
2959 model for this symbol, by patching the code. The offset -
2960 and scale, if any - will be installed by the linker. */
2961 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2962 break;
886a2506 2963
4670103e
CZ		 2964 case BFD_RELOC_ARC_TLS_LE_S9:
2965 case BFD_RELOC_ARC_TLS_DTPOFF_S9:
2966 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2967 break;
2968
2969 default:
2970 break;
886a2506
NC		 2971 }
2972
4670103e 2973 if (!fixP->fx_done)
886a2506 2974 {
4670103e 2975 return;
886a2506 2976 }
886a2506 2977
33eaf5de 2978 /* Adjust the value if we have a constant. */
4670103e 2979 value += fx_offset;
886a2506 2980
4670103e
CZ		 2981 /* For hosts with longs bigger than 32-bits make sure that the top
2982 bits of a 32-bit negative value read in by the parser are set,
2983 so that the correct comparisons are made. */
2984 if (value & 0x80000000)
69c9e028 2985 value |= (-1UL << 31);
886a2506 2986
4670103e
CZ		 2987 reloc = fixP->fx_r_type;
2988 switch (reloc)
2989 {
2990 case BFD_RELOC_8:
2991 case BFD_RELOC_16:
2992 case BFD_RELOC_24:
2993 case BFD_RELOC_32:
2994 case BFD_RELOC_64:
2995 case BFD_RELOC_ARC_32_PCREL:
2996 md_number_to_chars (fixpos, value, fixP->fx_size);
2997 return;
886a2506 2998
4670103e
CZ		 2999 case BFD_RELOC_ARC_GOTPC32:
3000 /* I cannot fix an GOTPC relocation because I need to relax it
3001 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3002 as_bad (_("Unsupported operation on reloc"));
3003 return;
886a2506 3004
4670103e
CZ		 3005 case BFD_RELOC_ARC_TLS_DTPOFF:
3006 case BFD_RELOC_ARC_TLS_LE_32:
3007 gas_assert (!fixP->fx_addsy);
3008 gas_assert (!fixP->fx_subsy);
1a0670f3 3009 /* Fall through. */
886a2506 3010
4670103e
CZ		 3011 case BFD_RELOC_ARC_GOTOFF:
3012 case BFD_RELOC_ARC_32_ME:
3013 case BFD_RELOC_ARC_PC32:
3014 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3015 return;
886a2506 3016
4670103e
CZ		 3017 case BFD_RELOC_ARC_PLT32:
3018 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3019 return;
886a2506 3020
4670103e
CZ		 3021 case BFD_RELOC_ARC_S25H_PCREL_PLT:
3022 reloc = BFD_RELOC_ARC_S25W_PCREL;
3023 goto solve_plt;
886a2506 3024
4670103e
CZ		 3025 case BFD_RELOC_ARC_S21H_PCREL_PLT:
3026 reloc = BFD_RELOC_ARC_S21H_PCREL;
3027 goto solve_plt;
886a2506 3028
4670103e
CZ		 3029 case BFD_RELOC_ARC_S25W_PCREL_PLT:
3030 reloc = BFD_RELOC_ARC_S25W_PCREL;
3031 goto solve_plt;
886a2506 3032
4670103e
CZ		 3033 case BFD_RELOC_ARC_S21W_PCREL_PLT:
3034 reloc = BFD_RELOC_ARC_S21W_PCREL;
1a0670f3 3035 /* Fall through. */
886a2506 3036
4670103e
CZ		 3037 case BFD_RELOC_ARC_S25W_PCREL:
3038 case BFD_RELOC_ARC_S21W_PCREL:
3039 case BFD_RELOC_ARC_S21H_PCREL:
3040 case BFD_RELOC_ARC_S25H_PCREL:
3041 case BFD_RELOC_ARC_S13_PCREL:
3042 solve_plt:
3043 operand = find_operand_for_reloc (reloc);
3044 gas_assert (operand);
886a2506
NC		 3045 break;
3046
3047 default:
4670103e
CZ		 3048 {
3049 if ((int) fixP->fx_r_type >= 0)
3050 as_fatal (_("unhandled relocation type %s"),
3051 bfd_get_reloc_code_name (fixP->fx_r_type));
886a2506 3052
4670103e
CZ		 3053 /* The rest of these fixups needs to be completely resolved as
3054 constants. */
3055 if (fixP->fx_addsy != 0
3056 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
3057 as_bad_where (fixP->fx_file, fixP->fx_line,
3058 _("non-absolute expression in constant field"));
886a2506 3059
4670103e
CZ		 3060 gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands);
3061 operand = &arc_operands[-(int) fixP->fx_r_type];
3062 break;
3063 }
3064 }
886a2506 3065
4670103e 3066 if (target_big_endian)
886a2506 3067 {
4670103e 3068 switch (fixP->fx_size)
886a2506 3069 {
4670103e
CZ		 3070 case 4:
3071 insn = bfd_getb32 (fixpos);
3072 break;
3073 case 2:
3074 insn = bfd_getb16 (fixpos);
3075 break;
3076 default:
3077 as_bad_where (fixP->fx_file, fixP->fx_line,
3078 _("unknown fixup size"));
3079 }
3080 }
3081 else
3082 {
3083 insn = 0;
3084 switch (fixP->fx_size)
3085 {
3086 case 4:
3087 insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2);
3088 break;
3089 case 2:
3090 insn = bfd_getl16 (fixpos);
3091 break;
3092 default:
3093 as_bad_where (fixP->fx_file, fixP->fx_line,
3094 _("unknown fixup size"));
886a2506
NC		 3095 }
3096 }
886a2506 3097
4670103e
CZ		 3098 insn = insert_operand (insn, operand, (offsetT) value,
3099 fixP->fx_file, fixP->fx_line);
886a2506 3100
4670103e
CZ		 3101 md_number_to_chars_midend (fixpos, insn, fixP->fx_size);
3102}
886a2506 3103
4670103e 3104/* Prepare machine-dependent frags for relaxation.
886a2506 3105
4670103e
CZ		 3106 Called just before relaxation starts. Any symbol that is now undefined
3107 will not become defined.
886a2506 3108
4670103e 3109 Return the correct fr_subtype in the frag.
886a2506 3110
4670103e
CZ		 3111 Return the initial "guess for fr_var" to caller. The guess for fr_var
3112 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3113 or fr_var contributes to our returned value.
886a2506 3114
4670103e
CZ		 3115 Although it may not be explicit in the frag, pretend
3116 fr_var starts with a value. */
886a2506 3117
4670103e
CZ		 3118int
3119md_estimate_size_before_relax (fragS *fragP,
3120 segT segment)
3121{
3122 int growth;
3123
3124 /* If the symbol is not located within the same section AND it's not
3125 an absolute section, use the maximum. OR if the symbol is a
3126 constant AND the insn is by nature not pc-rel, use the maximum.
3127 OR if the symbol is being equated against another symbol, use the
3128 maximum. OR if the symbol is weak use the maximum. */
3129 if ((S_GET_SEGMENT (fragP->fr_symbol) != segment
3130 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
3131 || (symbol_constant_p (fragP->fr_symbol)
3132 && !fragP->tc_frag_data.pcrel)
3133 || symbol_equated_p (fragP->fr_symbol)
3134 || S_IS_WEAK (fragP->fr_symbol))
3135 {
3136 while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE)
3137 ++fragP->fr_subtype;
3138 }
886a2506 3139
4670103e
CZ		 3140 growth = md_relax_table[fragP->fr_subtype].rlx_length;
3141 fragP->fr_var = growth;
886a2506 3142
4670103e
CZ		 3143 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3144 fragP->fr_file, fragP->fr_line, growth);
886a2506 3145
4670103e
CZ		 3146 return growth;
3147}
886a2506 3148
4670103e
CZ		 3149/* Translate internal representation of relocation info to BFD target
3150 format. */
886a2506 3151
4670103e
CZ		 3152arelent *
3153tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
3154 fixS *fixP)
3155{
3156 arelent *reloc;
3157 bfd_reloc_code_real_type code;
886a2506 3158
add39d23
TS		 3159 reloc = XNEW (arelent);
3160 reloc->sym_ptr_ptr = XNEW (asymbol *);
4670103e
CZ		 3161 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
3162 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
886a2506 3163
4670103e
CZ		 3164 /* Make sure none of our internal relocations make it this far.
3165 They'd better have been fully resolved by this point. */
3166 gas_assert ((int) fixP->fx_r_type > 0);
886a2506 3167
4670103e 3168 code = fixP->fx_r_type;
886a2506 3169
4670103e
CZ		 3170 /* if we have something like add gp, pcl,
3171 _GLOBAL_OFFSET_TABLE_@gotpc. */
3172 if (code == BFD_RELOC_ARC_GOTPC32
3173 && GOT_symbol
3174 && fixP->fx_addsy == GOT_symbol)
3175 code = BFD_RELOC_ARC_GOTPC;
886a2506 3176
4670103e
CZ		 3177 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3178 if (reloc->howto == NULL)
886a2506 3179 {
4670103e
CZ		 3180 as_bad_where (fixP->fx_file, fixP->fx_line,
3181 _("cannot represent `%s' relocation in object file"),
3182 bfd_get_reloc_code_name (code));
3183 return NULL;
3184 }
886a2506 3185
4670103e
CZ		 3186 if (!fixP->fx_pcrel != !reloc->howto->pc_relative)
3187 as_fatal (_("internal error? cannot generate `%s' relocation"),
3188 bfd_get_reloc_code_name (code));
886a2506 3189
4670103e 3190 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
886a2506 3191
05bbf016 3192 reloc->addend = fixP->fx_offset;
4670103e
CZ		 3193
3194 return reloc;
886a2506
NC		 3195}
3196
4670103e
CZ		 3197/* Perform post-processing of machine-dependent frags after relaxation.
3198 Called after relaxation is finished.
3199 In: Address of frag.
3200 fr_type == rs_machine_dependent.
3201 fr_subtype is what the address relaxed to.
886a2506 3202
4670103e
CZ		 3203 Out: Any fixS:s and constants are set up. */
3204
3205void
3206md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
3207 segT segment ATTRIBUTE_UNUSED,
3208 fragS *fragP)
886a2506 3209{
4670103e
CZ		 3210 const relax_typeS *table_entry;
3211 char *dest;
3212 const struct arc_opcode *opcode;
3213 struct arc_insn insn;
3214 int size, fix;
3215 struct arc_relax_type *relax_arg = &fragP->tc_frag_data;
886a2506 3216
4670103e
CZ		 3217 fix = (fragP->fr_fix < 0 ? 0 : fragP->fr_fix);
3218 dest = fragP->fr_literal + fix;
3219 table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
886a2506 3220
9e32d9ae
AB		 3221 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3222 "var: %"BFD_VMA_FMT"d\n",
4670103e
CZ		 3223 fragP->fr_file, fragP->fr_line,
3224 fragP->fr_subtype, fix, fragP->fr_var);
886a2506 3225
4670103e
CZ		 3226 if (fragP->fr_subtype <= 0
3227 && fragP->fr_subtype >= arc_num_relax_opcodes)
3228 as_fatal (_("no relaxation found for this instruction."));
886a2506 3229
4670103e 3230 opcode = &arc_relax_opcodes[fragP->fr_subtype];
886a2506 3231
4670103e
CZ		 3232 assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags,
3233 relax_arg->nflg, &insn);
886a2506 3234
4670103e 3235 apply_fixups (&insn, fragP, fix);
886a2506 3236
91fdca6f 3237 size = insn.len + (insn.has_limm ? 4 : 0);
4670103e
CZ		 3238 gas_assert (table_entry->rlx_length == size);
3239 emit_insn0 (&insn, dest, TRUE);
886a2506 3240
4670103e
CZ		 3241 fragP->fr_fix += table_entry->rlx_length;
3242 fragP->fr_var = 0;
886a2506
NC		 3243}
3244
4670103e
CZ		 3245/* We have no need to default values of symbols. We could catch
3246 register names here, but that is handled by inserting them all in
3247 the symbol table to begin with. */
886a2506 3248
4670103e
CZ		 3249symbolS *
3250md_undefined_symbol (char *name)
886a2506 3251{
4670103e
CZ		 3252 /* The arc abi demands that a GOT[0] should be referencible as
3253 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3254 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3255 if (((*name == '_')
3256 && (*(name+1) == 'G')
3257 && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0))
3258 || ((*name == '_')
3259 && (*(name+1) == 'D')
3260 && (strcmp (name, DYNAMIC_STRUCT_NAME) == 0)))
886a2506 3261 {
4670103e
CZ		 3262 if (!GOT_symbol)
3263 {
3264 if (symbol_find (name))
3265 as_bad ("GOT already in symbol table");
3266
3267 GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section,
3268 (valueT) 0, &zero_address_frag);
3269 };
3270 return GOT_symbol;
886a2506 3271 }
4670103e 3272 return NULL;
886a2506
NC		 3273}
3274
4670103e
CZ		 3275/* Turn a string in input_line_pointer into a floating point constant
3276 of type type, and store the appropriate bytes in *litP. The number
3277 of LITTLENUMS emitted is stored in *sizeP. An error message is
3278 returned, or NULL on OK. */
886a2506 3279
6d4af3c2 3280const char *
4670103e 3281md_atof (int type, char *litP, int *sizeP)
886a2506 3282{
4670103e
CZ		 3283 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3284}
886a2506 3285
4670103e
CZ		 3286/* Called for any expression that can not be recognized. When the
3287 function is called, `input_line_pointer' will point to the start of
3288 the expression. */
886a2506 3289
4670103e
CZ		 3290void
3291md_operand (expressionS *expressionP ATTRIBUTE_UNUSED)
3292{
3293 char *p = input_line_pointer;
3294 if (*p == '@')
886a2506 3295 {
4670103e
CZ		 3296 input_line_pointer++;
3297 expressionP->X_op = O_symbol;
3298 expression (expressionP);
3299 }
3300}
886a2506 3301
4670103e
CZ		 3302/* This function is called from the function 'expression', it attempts
3303 to parse special names (in our case register names). It fills in
3304 the expression with the identified register. It returns TRUE if
3305 it is a register and FALSE otherwise. */
886a2506 3306
4670103e
CZ		 3307bfd_boolean
3308arc_parse_name (const char *name,
3309 struct expressionS *e)
3310{
3311 struct symbol *sym;
886a2506 3312
4670103e
CZ		 3313 if (!assembling_insn)
3314 return FALSE;
886a2506 3315
08ec958f 3316 if (e->X_op == O_symbol)
4670103e 3317 return FALSE;
886a2506 3318
4670103e
CZ		 3319 sym = hash_find (arc_reg_hash, name);
3320 if (sym)
3321 {
3322 e->X_op = O_register;
3323 e->X_add_number = S_GET_VALUE (sym);
3324 return TRUE;
3325 }
db18dbab
GM		 3326
3327 sym = hash_find (arc_addrtype_hash, name);
3328 if (sym)
3329 {
3330 e->X_op = O_addrtype;
3331 e->X_add_number = S_GET_VALUE (sym);
3332 return TRUE;
3333 }
3334
4670103e
CZ		 3335 return FALSE;
3336}
886a2506 3337
4670103e
CZ		 3338/* md_parse_option
3339 Invocation line includes a switch not recognized by the base assembler.
3340 See if it's a processor-specific option.
886a2506 3341
4670103e 3342 New options (supported) are:
886a2506 3343
4670103e
CZ		 3344 -mcpu=<cpu name> Assemble for selected processor
3345 -EB/-mbig-endian Big-endian
3346 -EL/-mlittle-endian Little-endian
3347 -mrelax Enable relaxation
886a2506 3348
4670103e 3349 The following CPU names are recognized:
ce440d63 3350 arc600, arc700, arcem, archs, nps400. */
886a2506 3351
4670103e 3352int
17b9d67d 3353md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
4670103e 3354{
4670103e
CZ		 3355 switch (c)
3356 {
3357 case OPTION_ARC600:
3358 case OPTION_ARC601:
3359 return md_parse_option (OPTION_MCPU, "arc600");
886a2506 3360
4670103e
CZ		 3361 case OPTION_ARC700:
3362 return md_parse_option (OPTION_MCPU, "arc700");
886a2506 3363
4670103e
CZ		 3364 case OPTION_ARCEM:
3365 return md_parse_option (OPTION_MCPU, "arcem");
886a2506 3366
4670103e
CZ		 3367 case OPTION_ARCHS:
3368 return md_parse_option (OPTION_MCPU, "archs");
886a2506 3369
4670103e
CZ		 3370 case OPTION_MCPU:
3371 {
bb65a718 3372 arc_select_cpu (arg, MACH_SELECTION_FROM_COMMAND_LINE);
4670103e
CZ		 3373 break;
3374 }
886a2506 3375
4670103e
CZ		 3376 case OPTION_EB:
3377 arc_target_format = "elf32-bigarc";
3378 byte_order = BIG_ENDIAN;
3379 break;
886a2506 3380
4670103e
CZ		 3381 case OPTION_EL:
3382 arc_target_format = "elf32-littlearc";
3383 byte_order = LITTLE_ENDIAN;
3384 break;
886a2506 3385
4670103e 3386 case OPTION_CD:
bb050a69 3387 selected_cpu.features |= ARC_CD;
a9752fdf 3388 cl_features |= ARC_CD;
bb050a69 3389 arc_check_feature ();
4670103e 3390 break;
886a2506 3391
4670103e
CZ		 3392 case OPTION_RELAX:
3393 relaxation_state = 1;
3394 break;
886a2506 3395
bdd582db 3396 case OPTION_NPS400:
bb65a718 3397 selected_cpu.features |= ARC_NPS400;
a9752fdf 3398 cl_features |= ARC_NPS400;
bb050a69 3399 arc_check_feature ();
ce440d63 3400 break;
bdd582db 3401
ce440d63 3402 case OPTION_SPFP:
bb65a718 3403 selected_cpu.features |= ARC_SPFP;
a9752fdf 3404 cl_features |= ARC_SPFP;
bb050a69 3405 arc_check_feature ();
ce440d63
GM		 3406 break;
3407
3408 case OPTION_DPFP:
bb65a718 3409 selected_cpu.features |= ARC_DPFP;
a9752fdf 3410 cl_features |= ARC_DPFP;
bb050a69 3411 arc_check_feature ();
ce440d63
GM		 3412 break;
3413
3414 case OPTION_FPUDA:
bb050a69 3415 selected_cpu.features |= ARC_FPUDA;
a9752fdf 3416 cl_features |= ARC_FPUDA;
bb050a69 3417 arc_check_feature ();
ce440d63
GM		 3418 break;
3419
3420 /* Dummy options are accepted but have no effect. */
4670103e
CZ		 3421 case OPTION_USER_MODE:
3422 case OPTION_LD_EXT_MASK:
3423 case OPTION_SWAP:
3424 case OPTION_NORM:
3425 case OPTION_BARREL_SHIFT:
3426 case OPTION_MIN_MAX:
3427 case OPTION_NO_MPY:
3428 case OPTION_EA:
3429 case OPTION_MUL64:
3430 case OPTION_SIMD:
4670103e
CZ		 3431 case OPTION_XMAC_D16:
3432 case OPTION_XMAC_24:
3433 case OPTION_DSP_PACKA:
3434 case OPTION_CRC:
3435 case OPTION_DVBF:
3436 case OPTION_TELEPHONY:
3437 case OPTION_XYMEMORY:
3438 case OPTION_LOCK:
3439 case OPTION_SWAPE:
3440 case OPTION_RTSC:
8ddf6b2a
CZ		 3441 break;
3442
4670103e
CZ		 3443 default:
3444 return 0;
3445 }
886a2506 3446
4670103e
CZ		 3447 return 1;
3448}
886a2506 3449
a9752fdf
CZ		 3450/* Display the list of cpu names for use in the help text. */
3451
3452static void
3453arc_show_cpu_list (FILE *stream)
3454{
3455 int i, offset;
731f7c4e 3456 static const char *space_buf = " ";
a9752fdf 3457
731f7c4e
MR		 3458 fprintf (stream, "%s", space_buf);
3459 offset = strlen (space_buf);
a9752fdf
CZ		 3460 for (i = 0; cpu_types[i].name != NULL; ++i)
3461 {
3462 bfd_boolean last = (cpu_types[i + 1].name == NULL);
3463
3464 /* If displaying the new cpu name string, and the ', ' (for all
3465 but the last one) will take us past a target width of 80
3466 characters, then it's time for a new line. */
3467 if (offset + strlen (cpu_types[i].name) + (last ? 0 : 2) > 80)
3468 {
731f7c4e
MR		 3469 fprintf (stream, "\n%s", space_buf);
3470 offset = strlen (space_buf);
a9752fdf
CZ		 3471 }
3472
3473 fprintf (stream, "%s%s", cpu_types[i].name, (last ? "\n" : ", "));
3474 offset += strlen (cpu_types [i].name) + (last ? 0 : 2);
3475 }
3476}
3477
4670103e
CZ		 3478void
3479md_show_usage (FILE *stream)
3480{
3481 fprintf (stream, _("ARC-specific assembler options:\n"));
886a2506 3482
a9752fdf
CZ		 3483 fprintf (stream, " -mcpu=<cpu name>\t (default: %s), assemble for"
3484 " CPU <cpu name>, one of:\n", TARGET_WITH_CPU);
3485 arc_show_cpu_list (stream);
3486 fprintf (stream, "\n");
bdd582db
GM		 3487 fprintf (stream, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3488 fprintf (stream, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3489 fprintf (stream, " -mEM\t\t\t same as -mcpu=arcem\n");
3490 fprintf (stream, " -mHS\t\t\t same as -mcpu=archs\n");
3491
3492 fprintf (stream, " -mnps400\t\t enable NPS-400 extended instructions\n");
a9752fdf
CZ		 3493 fprintf (stream, " -mspfp\t\t enable single-precision floating point"
3494 " instructions\n");
3495 fprintf (stream, " -mdpfp\t\t enable double-precision floating point"
3496 " instructions\n");
bdd582db
GM		 3497 fprintf (stream, " -mfpuda\t\t enable double-precision assist floating "
3498 "point\n\t\t\t instructions for ARC EM\n");
3499
4670103e
CZ		 3500 fprintf (stream,
3501 " -mcode-density\t enable code density option for ARC EM\n");
3502
3503 fprintf (stream, _("\
3504 -EB assemble code for a big-endian cpu\n"));
3505 fprintf (stream, _("\
3506 -EL assemble code for a little-endian cpu\n"));
3507 fprintf (stream, _("\
bdd582db
GM		 3508 -mrelax enable relaxation\n"));
3509
3510 fprintf (stream, _("The following ARC-specific assembler options are "
3511 "deprecated and are accepted\nfor compatibility only:\n"));
3512
3513 fprintf (stream, _(" -mEA\n"
3514 " -mbarrel-shifter\n"
3515 " -mbarrel_shifter\n"
3516 " -mcrc\n"
3517 " -mdsp-packa\n"
3518 " -mdsp_packa\n"
3519 " -mdvbf\n"
3520 " -mld-extension-reg-mask\n"
3521 " -mlock\n"
3522 " -mmac-24\n"
3523 " -mmac-d16\n"
3524 " -mmac_24\n"
3525 " -mmac_d16\n"
3526 " -mmin-max\n"
3527 " -mmin_max\n"
3528 " -mmul64\n"
3529 " -mno-mpy\n"
3530 " -mnorm\n"
3531 " -mrtsc\n"
3532 " -msimd\n"
3533 " -mswap\n"
3534 " -mswape\n"
3535 " -mtelephony\n"
3536 " -muser-mode-only\n"
3537 " -mxy\n"));
886a2506
NC		 3538}
3539
3540/* Find the proper relocation for the given opcode. */
3541
3542static extended_bfd_reloc_code_real_type
3543find_reloc (const char *name,
3544 const char *opcodename,
3545 const struct arc_flags *pflags,
3546 int nflg,
3547 extended_bfd_reloc_code_real_type reloc)
3548{
3549 unsigned int i;
3550 int j;
24b368f8 3551 bfd_boolean found_flag, tmp;
886a2506
NC		 3552 extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
3553
3554 for (i = 0; i < arc_num_equiv_tab; i++)
3555 {
3556 const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i];
3557
3558 /* Find the entry. */
3559 if (strcmp (name, r->name))
3560 continue;
3561 if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
3562 continue;
24b368f8 3563 if (r->flags[0])
886a2506
NC		 3564 {
3565 if (!nflg)
3566 continue;
3567 found_flag = FALSE;
24b368f8
CZ		 3568 unsigned * psflg = (unsigned *)r->flags;
3569 do
3570 {
3571 tmp = FALSE;
3572 for (j = 0; j < nflg; j++)
3573 if (!strcmp (pflags[j].name,
3574 arc_flag_operands[*psflg].name))
3575 {
3576 tmp = TRUE;
3577 break;
3578 }
3579 if (!tmp)
3580 {
3581 found_flag = FALSE;
3582 break;
3583 }
3584 else
3585 {
3586 found_flag = TRUE;
3587 }
3588 ++ psflg;
3589 } while (*psflg);
3590
886a2506
NC		 3591 if (!found_flag)
3592 continue;
3593 }
3594
3595 if (reloc != r->oldreloc)
3596 continue;
3597 /* Found it. */
3598 ret = r->newreloc;
3599 break;
3600 }
3601
3602 if (ret == BFD_RELOC_UNUSED)
3603 as_bad (_("Unable to find %s relocation for instruction %s"),
3604 name, opcodename);
3605 return ret;
3606}
3607
4670103e
CZ		 3608/* All the symbol types that are allowed to be used for
3609 relaxation. */
3610
3611static bfd_boolean
3612may_relax_expr (expressionS tok)
3613{
3614 /* Check if we have unrelaxable relocs. */
3615 switch (tok.X_md)
3616 {
3617 default:
3618 break;
3619 case O_plt:
3620 return FALSE;
3621 }
3622
3623 switch (tok.X_op)
3624 {
3625 case O_symbol:
3626 case O_multiply:
3627 case O_divide:
3628 case O_modulus:
3629 case O_add:
3630 case O_subtract:
3631 break;
3632
3633 default:
3634 return FALSE;
3635 }
3636 return TRUE;
3637}
3638
3639/* Checks if flags are in line with relaxable insn. */
3640
3641static bfd_boolean
3642relaxable_flag (const struct arc_relaxable_ins *ins,
3643 const struct arc_flags *pflags,
3644 int nflgs)
3645{
3646 unsigned flag_class,
3647 flag,
3648 flag_class_idx = 0,
3649 flag_idx = 0;
3650
3651 const struct arc_flag_operand *flag_opand;
3652 int i, counttrue = 0;
3653
3654 /* Iterate through flags classes. */
3655 while ((flag_class = ins->flag_classes[flag_class_idx]) != 0)
3656 {
3657 /* Iterate through flags in flag class. */
3658 while ((flag = arc_flag_classes[flag_class].flags[flag_idx])
3659 != 0)
3660 {
3661 flag_opand = &arc_flag_operands[flag];
3662 /* Iterate through flags in ins to compare. */
3663 for (i = 0; i < nflgs; ++i)
3664 {
3665 if (strcmp (flag_opand->name, pflags[i].name) == 0)
3666 ++counttrue;
3667 }
3668
3669 ++flag_idx;
3670 }
3671
3672 ++flag_class_idx;
3673 flag_idx = 0;
3674 }
3675
3676 /* If counttrue == nflgs, then all flags have been found. */
3677 return (counttrue == nflgs ? TRUE : FALSE);
3678}
3679
3680/* Checks if operands are in line with relaxable insn. */
3681
3682static bfd_boolean
3683relaxable_operand (const struct arc_relaxable_ins *ins,
3684 const expressionS *tok,
3685 int ntok)
3686{
3687 const enum rlx_operand_type *operand = &ins->operands[0];
3688 int i = 0;
3689
3690 while (*operand != EMPTY)
3691 {
3692 const expressionS *epr = &tok[i];
3693
3694 if (i != 0 && i >= ntok)
3695 return FALSE;
3696
3697 switch (*operand)
3698 {
3699 case IMMEDIATE:
3700 if (!(epr->X_op == O_multiply
3701 || epr->X_op == O_divide
3702 || epr->X_op == O_modulus
3703 || epr->X_op == O_add
3704 || epr->X_op == O_subtract
3705 || epr->X_op == O_symbol))
3706 return FALSE;
3707 break;
3708
3709 case REGISTER_DUP:
3710 if ((i <= 0)
3711 || (epr->X_add_number != tok[i - 1].X_add_number))
3712 return FALSE;
3713 /* Fall through. */
3714 case REGISTER:
3715 if (epr->X_op != O_register)
3716 return FALSE;
3717 break;
3718
3719 case REGISTER_S:
3720 if (epr->X_op != O_register)
3721 return FALSE;
3722
3723 switch (epr->X_add_number)
3724 {
3725 case 0: case 1: case 2: case 3:
3726 case 12: case 13: case 14: case 15:
3727 break;
3728 default:
3729 return FALSE;
3730 }
3731 break;
3732
3733 case REGISTER_NO_GP:
3734 if ((epr->X_op != O_register)
3735 || (epr->X_add_number == 26)) /* 26 is the gp register. */
3736 return FALSE;
3737 break;
3738
3739 case BRACKET:
3740 if (epr->X_op != O_bracket)
3741 return FALSE;
3742 break;
3743
3744 default:
3745 /* Don't understand, bail out. */
3746 return FALSE;
3747 break;
3748 }
3749
3750 ++i;
3751 operand = &ins->operands[i];
3752 }
3753
3754 return (i == ntok ? TRUE : FALSE);
3755}
3756
3757/* Return TRUE if this OPDCODE is a candidate for relaxation. */
3758
3759static bfd_boolean
3760relax_insn_p (const struct arc_opcode *opcode,
3761 const expressionS *tok,
3762 int ntok,
3763 const struct arc_flags *pflags,
3764 int nflg)
3765{
3766 unsigned i;
3767 bfd_boolean rv = FALSE;
3768
3769 /* Check the relaxation table. */
3770 for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i)
3771 {
3772 const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i];
3773
3774 if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0)
3775 && may_relax_expr (tok[arc_rlx_ins->opcheckidx])
3776 && relaxable_operand (arc_rlx_ins, tok, ntok)
3777 && relaxable_flag (arc_rlx_ins, pflags, nflg))
3778 {
3779 rv = TRUE;
3780 frag_now->fr_subtype = arc_relaxable_insns[i].subtype;
3781 memcpy (&frag_now->tc_frag_data.tok, tok,
3782 sizeof (expressionS) * ntok);
3783 memcpy (&frag_now->tc_frag_data.pflags, pflags,
3784 sizeof (struct arc_flags) * nflg);
3785 frag_now->tc_frag_data.nflg = nflg;
3786 frag_now->tc_frag_data.ntok = ntok;
3787 break;
3788 }
3789 }
3790
3791 return rv;
3792}
3793
886a2506
NC		 3794/* Turn an opcode description and a set of arguments into
3795 an instruction and a fixup. */
3796
3797static void
3798assemble_insn (const struct arc_opcode *opcode,
3799 const expressionS *tok,
3800 int ntok,
3801 const struct arc_flags *pflags,
3802 int nflg,
3803 struct arc_insn *insn)
3804{
3805 const expressionS *reloc_exp = NULL;
bdfe53e3 3806 unsigned long long image;
886a2506
NC		 3807 const unsigned char *argidx;
3808 int i;
3809 int tokidx = 0;
3810 unsigned char pcrel = 0;
3811 bfd_boolean needGOTSymbol;
3812 bfd_boolean has_delay_slot = FALSE;
3813 extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
3814
3815 memset (insn, 0, sizeof (*insn));
3816 image = opcode->opcode;
3817
bdfe53e3 3818 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
886a2506
NC		 3819 frag_now->fr_file, frag_now->fr_line, opcode->name,
3820 opcode->opcode);
3821
3822 /* Handle operands. */
3823 for (argidx = opcode->operands; *argidx; ++argidx)
3824 {
3825 const struct arc_operand *operand = &arc_operands[*argidx];
3826 const expressionS *t = (const expressionS *) 0;
3827
db18dbab 3828 if (ARC_OPERAND_IS_FAKE (operand))
886a2506
NC		 3829 continue;
3830
3831 if (operand->flags & ARC_OPERAND_DUPLICATE)
3832 {
3833 /* Duplicate operand, already inserted. */
3834 tokidx ++;
3835 continue;
3836 }
3837
3838 if (tokidx >= ntok)
3839 {
3840 abort ();
3841 }
3842 else
3843 t = &tok[tokidx++];
3844
3845 /* Regardless if we have a reloc or not mark the instruction
3846 limm if it is the case. */
3847 if (operand->flags & ARC_OPERAND_LIMM)
3848 insn->has_limm = TRUE;
3849
3850 switch (t->X_op)
3851 {
3852 case O_register:
3853 image = insert_operand (image, operand, regno (t->X_add_number),
3854 NULL, 0);
3855 break;
3856
3857 case O_constant:
3858 image = insert_operand (image, operand, t->X_add_number, NULL, 0);
3859 reloc_exp = t;
3860 if (operand->flags & ARC_OPERAND_LIMM)
3861 insn->limm = t->X_add_number;
3862 break;
3863
3864 case O_bracket:
db18dbab
GM		 3865 case O_colon:
3866 case O_addrtype:
3867 /* Ignore brackets, colons, and address types. */
886a2506
NC		 3868 break;
3869
3870 case O_absent:
3871 gas_assert (operand->flags & ARC_OPERAND_IGNORE);
3872 break;
3873
3874 case O_subtract:
3875 /* Maybe register range. */
3876 if ((t->X_add_number == 0)
3877 && contains_register (t->X_add_symbol)
3878 && contains_register (t->X_op_symbol))
3879 {
3880 int regs;
3881
3882 regs = get_register (t->X_add_symbol);
3883 regs <<= 16;
3884 regs |= get_register (t->X_op_symbol);
3885 image = insert_operand (image, operand, regs, NULL, 0);
3886 break;
3887 }
1a0670f3 3888 /* Fall through. */
886a2506
NC		 3889
3890 default:
3891 /* This operand needs a relocation. */
3892 needGOTSymbol = FALSE;
3893
3894 switch (t->X_md)
3895 {
3896 case O_plt:
c810e0b8 3897 if (opcode->insn_class == JUMP)
6ec1f282 3898 as_bad_where (frag_now->fr_file, frag_now->fr_line,
33eaf5de 3899 _("Unable to use @plt relocation for insn %s"),
6ec1f282 3900 opcode->name);
886a2506
NC		 3901 needGOTSymbol = TRUE;
3902 reloc = find_reloc ("plt", opcode->name,
3903 pflags, nflg,
3904 operand->default_reloc);
3905 break;
3906
3907 case O_gotoff:
3908 case O_gotpc:
3909 needGOTSymbol = TRUE;
3910 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3911 break;
3912 case O_pcl:
cc07cda6
CZ		 3913 if (operand->flags & ARC_OPERAND_LIMM)
3914 {
3915 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3916 if (arc_opcode_len (opcode) == 2
3917 || opcode->insn_class == JUMP)
3918 as_bad_where (frag_now->fr_file, frag_now->fr_line,
3919 _("Unable to use @pcl relocation for insn %s"),
3920 opcode->name);
3921 }
3922 else
3923 {
3924 /* This is a relaxed operand which initially was
3925 limm, choose whatever we have defined in the
3926 opcode as reloc. */
3927 reloc = operand->default_reloc;
3928 }
886a2506
NC		 3929 break;
3930 case O_sda:
3931 reloc = find_reloc ("sda", opcode->name,
3932 pflags, nflg,
3933 operand->default_reloc);
3934 break;
3935 case O_tlsgd:
3936 case O_tlsie:
3937 needGOTSymbol = TRUE;
3938 /* Fall-through. */
3939
3940 case O_tpoff:
3941 case O_dtpoff:
3942 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3943 break;
3944
3945 case O_tpoff9: /*FIXME! Check for the conditionality of
3946 the insn. */
3947 case O_dtpoff9: /*FIXME! Check for the conditionality of
3948 the insn. */
3949 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3950 break;
3951
3952 default:
3953 /* Just consider the default relocation. */
3954 reloc = operand->default_reloc;
3955 break;
3956 }
3957
3958 if (needGOTSymbol && (GOT_symbol == NULL))
3959 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3960
3961 reloc_exp = t;
3962
3963#if 0
3964 if (reloc > 0)
3965 {
3966 /* sanity checks. */
3967 reloc_howto_type *reloc_howto
3968 = bfd_reloc_type_lookup (stdoutput,
3969 (bfd_reloc_code_real_type) reloc);
3970 unsigned reloc_bitsize = reloc_howto->bitsize;
3971 if (reloc_howto->rightshift)
3972 reloc_bitsize -= reloc_howto->rightshift;
3973 if (reloc_bitsize != operand->bits)
3974 {
3975 as_bad (_("invalid relocation %s for field"),
3976 bfd_get_reloc_code_name (reloc));
3977 return;
3978 }
3979 }
3980#endif
3981 if (insn->nfixups >= MAX_INSN_FIXUPS)
3982 as_fatal (_("too many fixups"));
3983
3984 struct arc_fixup *fixup;
3985 fixup = &insn->fixups[insn->nfixups++];
3986 fixup->exp = *t;
3987 fixup->reloc = reloc;
cc07cda6
CZ		 3988 if ((int) reloc < 0)
3989 pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0;
3990 else
3991 {
3992 reloc_howto_type *reloc_howto =
3993 bfd_reloc_type_lookup (stdoutput,
3994 (bfd_reloc_code_real_type) fixup->reloc);
3995 pcrel = reloc_howto->pc_relative;
3996 }
886a2506
NC		 3997 fixup->pcrel = pcrel;
3998 fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ?
3999 TRUE : FALSE;
4000 break;
4001 }
4002 }
4003
4004 /* Handle flags. */
4005 for (i = 0; i < nflg; i++)
4006 {
f36e33da 4007 const struct arc_flag_operand *flg_operand = pflags[i].flgp;
886a2506
NC		 4008
4009 /* Check if the instruction has a delay slot. */
4010 if (!strcmp (flg_operand->name, "d"))
4011 has_delay_slot = TRUE;
4012
2c52e2e8
RZ		 4013 /* There is an exceptional case when we cannot insert a flag just as
4014 it is. On ARCv2 the '.t' and '.nt' flags must be handled in
4015 relation with the relative address. Unfortunately, some of the
4016 ARC700 extensions (NPS400) also have a '.nt' flag that should be
4017 handled in the normal way.
4018
4019 Flag operands don't have an architecture field, so we can't
4020 directly validate that FLAG_OPERAND is valid for the current
4021 architecture, what we do instead is just validate that we're
4022 assembling for an ARCv2 architecture. */
4023 if ((selected_cpu.flags & ARC_OPCODE_ARCV2)
4024 && (!strcmp (flg_operand->name, "t")
4025 || !strcmp (flg_operand->name, "nt")))
886a2506
NC		 4026 {
4027 unsigned bitYoperand = 0;
4028 /* FIXME! move selection bbit/brcc in arc-opc.c. */
4029 if (!strcmp (flg_operand->name, "t"))
4030 if (!strcmp (opcode->name, "bbit0")
4031 || !strcmp (opcode->name, "bbit1"))
4032 bitYoperand = arc_NToperand;
4033 else
4034 bitYoperand = arc_Toperand;
4035 else
4036 if (!strcmp (opcode->name, "bbit0")
4037 || !strcmp (opcode->name, "bbit1"))
4038 bitYoperand = arc_Toperand;
4039 else
4040 bitYoperand = arc_NToperand;
4041
4042 gas_assert (reloc_exp != NULL);
4043 if (reloc_exp->X_op == O_constant)
4044 {
4045 /* Check if we have a constant and solved it
4046 immediately. */
4047 offsetT val = reloc_exp->X_add_number;
4048 image |= insert_operand (image, &arc_operands[bitYoperand],
4049 val, NULL, 0);
4050 }
4051 else
4052 {
4053 struct arc_fixup *fixup;
4054
4055 if (insn->nfixups >= MAX_INSN_FIXUPS)
4056 as_fatal (_("too many fixups"));
4057
4058 fixup = &insn->fixups[insn->nfixups++];
4059 fixup->exp = *reloc_exp;
4060 fixup->reloc = -bitYoperand;
4061 fixup->pcrel = pcrel;
4062 fixup->islong = FALSE;
4063 }
4064 }
4065 else
4066 image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
4067 << flg_operand->shift;
4068 }
4069
4670103e
CZ		 4070 insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
4071
91fdca6f 4072 /* Instruction length. */
06fe285f 4073 insn->len = arc_opcode_len (opcode);
886a2506
NC		 4074
4075 insn->insn = image;
4076
4077 /* Update last insn status. */
4078 arc_last_insns[1] = arc_last_insns[0];
4079 arc_last_insns[0].opcode = opcode;
4080 arc_last_insns[0].has_limm = insn->has_limm;
4081 arc_last_insns[0].has_delay_slot = has_delay_slot;
4082
4083 /* Check if the current instruction is legally used. */
4084 if (arc_last_insns[1].has_delay_slot
4085 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
4086 as_bad_where (frag_now->fr_file, frag_now->fr_line,
4087 _("A jump/branch instruction in delay slot."));
4088}
4089
886a2506
NC		 4090void
4091arc_handle_align (fragS* fragP)
4092{
4093 if ((fragP)->fr_type == rs_align_code)
4094 {
4095 char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
4096 valueT count = ((fragP)->fr_next->fr_address
4097 - (fragP)->fr_address - (fragP)->fr_fix);
4098
4099 (fragP)->fr_var = 2;
4100
4101 if (count & 1)/* Padding in the gap till the next 2-byte
4102 boundary with 0s. */
4103 {
4104 (fragP)->fr_fix++;
4105 *dest++ = 0;
4106 }
4107 /* Writing nop_s. */
4108 md_number_to_chars (dest, NOP_OPCODE_S, 2);
4109 }
4110}
4111
4112/* Here we decide which fixups can be adjusted to make them relative
4113 to the beginning of the section instead of the symbol. Basically
4114 we need to make sure that the dynamic relocations are done
4115 correctly, so in some cases we force the original symbol to be
4116 used. */
4117
4118int
4119tc_arc_fix_adjustable (fixS *fixP)
4120{
4121
4122 /* Prevent all adjustments to global symbols. */
4123 if (S_IS_EXTERNAL (fixP->fx_addsy))
4124 return 0;
4125 if (S_IS_WEAK (fixP->fx_addsy))
4126 return 0;
4127
4128 /* Adjust_reloc_syms doesn't know about the GOT. */
4129 switch (fixP->fx_r_type)
4130 {
4131 case BFD_RELOC_ARC_GOTPC32:
4132 case BFD_RELOC_ARC_PLT32:
4133 case BFD_RELOC_ARC_S25H_PCREL_PLT:
4134 case BFD_RELOC_ARC_S21H_PCREL_PLT:
4135 case BFD_RELOC_ARC_S25W_PCREL_PLT:
4136 case BFD_RELOC_ARC_S21W_PCREL_PLT:
4137 return 0;
4138
4139 default:
4140 break;
4141 }
4142
841fdfcd 4143 return 1;
886a2506
NC		 4144}
4145
4146/* Compute the reloc type of an expression EXP. */
4147
4148static void
4149arc_check_reloc (expressionS *exp,
4150 bfd_reloc_code_real_type *r_type_p)
4151{
4152 if (*r_type_p == BFD_RELOC_32
4153 && exp->X_op == O_subtract
4154 && exp->X_op_symbol != NULL
4155 && exp->X_op_symbol->bsym->section == now_seg)
6f4b1afc 4156 *r_type_p = BFD_RELOC_ARC_32_PCREL;
886a2506
NC		 4157}
4158
4159
4160/* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4161
4162void
4163arc_cons_fix_new (fragS *frag,
4164 int off,
4165 int size,
4166 expressionS *exp,
4167 bfd_reloc_code_real_type r_type)
4168{
4169 r_type = BFD_RELOC_UNUSED;
4170
4171 switch (size)
4172 {
4173 case 1:
4174 r_type = BFD_RELOC_8;
4175 break;
4176
4177 case 2:
4178 r_type = BFD_RELOC_16;
4179 break;
4180
4181 case 3:
4182 r_type = BFD_RELOC_24;
4183 break;
4184
4185 case 4:
4186 r_type = BFD_RELOC_32;
4187 arc_check_reloc (exp, &r_type);
4188 break;
4189
4190 case 8:
4191 r_type = BFD_RELOC_64;
4192 break;
4193
4194 default:
4195 as_bad (_("unsupported BFD relocation size %u"), size);
4196 r_type = BFD_RELOC_UNUSED;
4197 }
4198
4199 fix_new_exp (frag, off, size, exp, 0, r_type);
4200}
4201
4202/* The actual routine that checks the ZOL conditions. */
4203
4204static void
4205check_zol (symbolS *s)
4206{
bb65a718 4207 switch (selected_cpu.mach)
886a2506
NC		 4208 {
4209 case bfd_mach_arc_arcv2:
bb65a718 4210 if (selected_cpu.flags & ARC_OPCODE_ARCv2EM)
886a2506
NC		 4211 return;
4212
4213 if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
4214 || arc_last_insns[1].has_delay_slot)
4215 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4216 S_GET_NAME (s));
4217
4218 break;
4219 case bfd_mach_arc_arc600:
4220
4221 if (is_kernel_insn_p (arc_last_insns[0].opcode))
4222 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4223 S_GET_NAME (s));
4224
4225 if (arc_last_insns[0].has_limm
4226 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
4227 as_bad (_("A jump instruction with long immediate detected at the \
4228end of the ZOL label @%s"), S_GET_NAME (s));
4229
4230 /* Fall through. */
4231 case bfd_mach_arc_arc700:
4232 if (arc_last_insns[0].has_delay_slot)
4233 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4234 S_GET_NAME (s));
4235
4236 break;
4237 default:
4238 break;
4239 }
4240}
4241
4242/* If ZOL end check the last two instruction for illegals. */
4243void
4244arc_frob_label (symbolS * sym)
4245{
4246 if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL)
4247 check_zol (sym);
4248
4249 dwarf2_emit_label (sym);
ea1562b3 4250}
4670103e
CZ		 4251
4252/* Used because generic relaxation assumes a pc-rel value whilst we
4253 also relax instructions that use an absolute value resolved out of
4254 relative values (if that makes any sense). An example: 'add r1,
4255 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4256 but if they're in the same section we can subtract the section
4257 offset relocation which ends up in a resolved value. So if @.L2 is
4258 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4259 .text + 0x40 = 0x10. */
4260int
4261arc_pcrel_adjust (fragS *fragP)
4262{
cc07cda6
CZ		 4263 pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n",
4264 fragP->fr_address, fragP->fr_fix,
4265 fragP->tc_frag_data.pcrel ? "Y" : "N");
4266
4670103e
CZ		 4267 if (!fragP->tc_frag_data.pcrel)
4268 return fragP->fr_address + fragP->fr_fix;
4269
cc07cda6
CZ		 4270 /* Take into account the PCL rounding. */
4271 return (fragP->fr_address + fragP->fr_fix) & 0x03;
4670103e 4272}
726c18e1
CZ		 4273
4274/* Initialize the DWARF-2 unwind information for this procedure. */
4275
4276void
4277tc_arc_frame_initial_instructions (void)
4278{
4279 /* Stack pointer is register 28. */
45a54ee5 4280 cfi_add_CFA_def_cfa (28, 0);
726c18e1
CZ		 4281}
4282
4283int
4284tc_arc_regname_to_dw2regnum (char *regname)
4285{
4286 struct symbol *sym;
4287
4288 sym = hash_find (arc_reg_hash, regname);
4289 if (sym)
4290 return S_GET_VALUE (sym);
4291
4292 return -1;
4293}
37ab9779
CZ		 4294
4295/* Adjust the symbol table. Delete found AUX register symbols. */
4296
4297void
4298arc_adjust_symtab (void)
4299{
4300 symbolS * sym;
4301
4302 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4303 {
4304 /* I've created a symbol during parsing process. Now, remove
4305 the symbol as it is found to be an AUX register. */
4306 if (ARC_GET_FLAG (sym) & ARC_FLAG_AUX)
4307 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
4308 }
4309
4310 /* Now do generic ELF adjustments. */
4311 elf_adjust_symtab ();
4312}
b99747ae
CZ		 4313
4314static void
4315tokenize_extinsn (extInstruction_t *einsn)
4316{
4317 char *p, c;
4318 char *insn_name;
4319 unsigned char major_opcode;
4320 unsigned char sub_opcode;
4321 unsigned char syntax_class = 0;
4322 unsigned char syntax_class_modifiers = 0;
4323 unsigned char suffix_class = 0;
4324 unsigned int i;
4325
4326 SKIP_WHITESPACE ();
4327
4328 /* 1st: get instruction name. */
4329 p = input_line_pointer;
4330 c = get_symbol_name (&p);
4331
4332 insn_name = xstrdup (p);
4333 restore_line_pointer (c);
4334
4335 /* 2nd: get major opcode. */
4336 if (*input_line_pointer != ',')
4337 {
4338 as_bad (_("expected comma after instruction name"));
4339 ignore_rest_of_line ();
4340 return;
4341 }
4342 input_line_pointer++;
4343 major_opcode = get_absolute_expression ();
4344
4345 /* 3rd: get sub-opcode. */
4346 SKIP_WHITESPACE ();
4347
4348 if (*input_line_pointer != ',')
4349 {
4350 as_bad (_("expected comma after major opcode"));
4351 ignore_rest_of_line ();
4352 return;
4353 }
4354 input_line_pointer++;
4355 sub_opcode = get_absolute_expression ();
4356
4357 /* 4th: get suffix class. */
4358 SKIP_WHITESPACE ();
4359
4360 if (*input_line_pointer != ',')
4361 {
4362 as_bad ("expected comma after sub opcode");
4363 ignore_rest_of_line ();
4364 return;
4365 }
4366 input_line_pointer++;
4367
4368 while (1)
4369 {
4370 SKIP_WHITESPACE ();
4371
4372 for (i = 0; i < ARRAY_SIZE (suffixclass); i++)
4373 {
4374 if (!strncmp (suffixclass[i].name, input_line_pointer,
4375 suffixclass[i].len))
4376 {
c810e0b8 4377 suffix_class |= suffixclass[i].attr_class;
b99747ae
CZ		 4378 input_line_pointer += suffixclass[i].len;
4379 break;
4380 }
4381 }
4382
4383 if (i == ARRAY_SIZE (suffixclass))
4384 {
4385 as_bad ("invalid suffix class");
4386 ignore_rest_of_line ();
4387 return;
4388 }
4389
4390 SKIP_WHITESPACE ();
4391
4392 if (*input_line_pointer == '|')
4393 input_line_pointer++;
4394 else
4395 break;
4396 }
4397
4398 /* 5th: get syntax class and syntax class modifiers. */
4399 if (*input_line_pointer != ',')
4400 {
4401 as_bad ("expected comma after suffix class");
4402 ignore_rest_of_line ();
4403 return;
4404 }
4405 input_line_pointer++;
4406
4407 while (1)
4408 {
4409 SKIP_WHITESPACE ();
4410
4411 for (i = 0; i < ARRAY_SIZE (syntaxclassmod); i++)
4412 {
4413 if (!strncmp (syntaxclassmod[i].name,
4414 input_line_pointer,
4415 syntaxclassmod[i].len))
4416 {
c810e0b8 4417 syntax_class_modifiers |= syntaxclassmod[i].attr_class;
b99747ae
CZ		 4418 input_line_pointer += syntaxclassmod[i].len;
4419 break;
4420 }
4421 }
4422
4423 if (i == ARRAY_SIZE (syntaxclassmod))
4424 {
4425 for (i = 0; i < ARRAY_SIZE (syntaxclass); i++)
4426 {
4427 if (!strncmp (syntaxclass[i].name,
4428 input_line_pointer,
4429 syntaxclass[i].len))
4430 {
c810e0b8 4431 syntax_class |= syntaxclass[i].attr_class;
b99747ae
CZ		 4432 input_line_pointer += syntaxclass[i].len;
4433 break;
4434 }
4435 }
4436
4437 if (i == ARRAY_SIZE (syntaxclass))
4438 {
4439 as_bad ("missing syntax class");
4440 ignore_rest_of_line ();
4441 return;
4442 }
4443 }
4444
4445 SKIP_WHITESPACE ();
4446
4447 if (*input_line_pointer == '|')
4448 input_line_pointer++;
4449 else
4450 break;
4451 }
4452
4453 demand_empty_rest_of_line ();
4454
4455 einsn->name = insn_name;
4456 einsn->major = major_opcode;
4457 einsn->minor = sub_opcode;
4458 einsn->syntax = syntax_class;
4459 einsn->modsyn = syntax_class_modifiers;
4460 einsn->suffix = suffix_class;
4461 einsn->flags = syntax_class
4462 | (syntax_class_modifiers & ARC_OP1_IMM_IMPLIED ? 0x10 : 0);
4463}
4464
4465/* Generate an extension section. */
4466
4467static int
4468arc_set_ext_seg (void)
4469{
4470 if (!arcext_section)
4471 {
4472 arcext_section = subseg_new (".arcextmap", 0);
4473 bfd_set_section_flags (stdoutput, arcext_section,
4474 SEC_READONLY | SEC_HAS_CONTENTS);
4475 }
4476 else
4477 subseg_set (arcext_section, 0);
4478 return 1;
4479}
4480
4481/* Create an extension instruction description in the arc extension
4482 section of the output file.
4483 The structure for an instruction is like this:
4484 [0]: Length of the record.
4485 [1]: Type of the record.
4486
4487 [2]: Major opcode.
4488 [3]: Sub-opcode.
4489 [4]: Syntax (flags).
4490 [5]+ Name instruction.
4491
4492 The sequence is terminated by an empty entry. */
4493
4494static void
4495create_extinst_section (extInstruction_t *einsn)
4496{
4497
4498 segT old_sec = now_seg;
4499 int old_subsec = now_subseg;
4500 char *p;
4501 int name_len = strlen (einsn->name);
4502
4503 arc_set_ext_seg ();
4504
4505 p = frag_more (1);
4506 *p = 5 + name_len + 1;
4507 p = frag_more (1);
4508 *p = EXT_INSTRUCTION;
4509 p = frag_more (1);
4510 *p = einsn->major;
4511 p = frag_more (1);
4512 *p = einsn->minor;
4513 p = frag_more (1);
4514 *p = einsn->flags;
4515 p = frag_more (name_len + 1);
4516 strcpy (p, einsn->name);
4517
4518 subseg_set (old_sec, old_subsec);
4519}
4520
4521/* Handler .extinstruction pseudo-op. */
4522
4523static void
4524arc_extinsn (int ignore ATTRIBUTE_UNUSED)
4525{
4526 extInstruction_t einsn;
4527 struct arc_opcode *arc_ext_opcodes;
4528 const char *errmsg = NULL;
4529 unsigned char moplow, mophigh;
4530
4531 memset (&einsn, 0, sizeof (einsn));
4532 tokenize_extinsn (&einsn);
4533
4534 /* Check if the name is already used. */
4535 if (arc_find_opcode (einsn.name))
4536 as_warn (_("Pseudocode already used %s"), einsn.name);
4537
4538 /* Check the opcode ranges. */
4539 moplow = 0x05;
bb65a718
AB		 4540 mophigh = (selected_cpu.flags & (ARC_OPCODE_ARCv2EM
4541 | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a;
b99747ae
CZ		 4542
4543 if ((einsn.major > mophigh) || (einsn.major < moplow))
4544 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, mophigh);
4545
4546 if ((einsn.minor > 0x3f) && (einsn.major != 0x0a)
4547 && (einsn.major != 5) && (einsn.major != 9))
4548 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4549
945e0f82 4550 switch (einsn.syntax & ARC_SYNTAX_MASK)
b99747ae
CZ		 4551 {
4552 case ARC_SYNTAX_3OP:
4553 if (einsn.modsyn & ARC_OP1_IMM_IMPLIED)
4554 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4555 break;
4556 case ARC_SYNTAX_2OP:
945e0f82
CZ		 4557 case ARC_SYNTAX_1OP:
4558 case ARC_SYNTAX_NOP:
b99747ae
CZ		 4559 if (einsn.modsyn & ARC_OP1_MUST_BE_IMM)
4560 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4561 break;
4562 default:
4563 break;
4564 }
4565
bb65a718 4566 arc_ext_opcodes = arcExtMap_genOpcode (&einsn, selected_cpu.flags, &errmsg);
b99747ae
CZ		 4567 if (arc_ext_opcodes == NULL)
4568 {
4569 if (errmsg)
4570 as_fatal ("%s", errmsg);
4571 else
4572 as_fatal (_("Couldn't generate extension instruction opcodes"));
4573 }
4574 else if (errmsg)
4575 as_warn ("%s", errmsg);
4576
4577 /* Insert the extension instruction. */
4578 arc_insert_opcode ((const struct arc_opcode *) arc_ext_opcodes);
4579
4580 create_extinst_section (&einsn);
4581}
4582
06911889 4583static bfd_boolean
f36e33da
CZ		 4584tokenize_extregister (extRegister_t *ereg, int opertype)
4585{
4586 char *name;
4587 char *mode;
4588 char c;
4589 char *p;
4590 int number, imode = 0;
4591 bfd_boolean isCore_p = (opertype == EXT_CORE_REGISTER) ? TRUE : FALSE;
4592 bfd_boolean isReg_p = (opertype == EXT_CORE_REGISTER
4593 || opertype == EXT_AUX_REGISTER) ? TRUE : FALSE;
4594
4595 /* 1st: get register name. */
4596 SKIP_WHITESPACE ();
4597 p = input_line_pointer;
4598 c = get_symbol_name (&p);
4599
4600 name = xstrdup (p);
4601 restore_line_pointer (c);
4602
4603 /* 2nd: get register number. */
4604 SKIP_WHITESPACE ();
4605
4606 if (*input_line_pointer != ',')
4607 {
06911889 4608 as_bad (_("expected comma after name"));
f36e33da
CZ		 4609 ignore_rest_of_line ();
4610 free (name);
06911889 4611 return FALSE;
f36e33da
CZ		 4612 }
4613 input_line_pointer++;
4614 number = get_absolute_expression ();
4615
06911889
CZ		 4616 if ((number < 0)
4617 && (opertype != EXT_AUX_REGISTER))
f36e33da 4618 {
06911889
CZ		 4619 as_bad (_("%s second argument cannot be a negative number %d"),
4620 isCore_p ? "extCoreRegister's" : "extCondCode's",
4621 number);
f36e33da
CZ		 4622 ignore_rest_of_line ();
4623 free (name);
06911889 4624 return FALSE;
f36e33da
CZ		 4625 }
4626
4627 if (isReg_p)
4628 {
4629 /* 3rd: get register mode. */
4630 SKIP_WHITESPACE ();
4631
4632 if (*input_line_pointer != ',')
4633 {
4634 as_bad (_("expected comma after register number"));
4635 ignore_rest_of_line ();
4636 free (name);
06911889 4637 return FALSE;
f36e33da
CZ		 4638 }
4639
4640 input_line_pointer++;
4641 mode = input_line_pointer;
4642
4643 if (!strncmp (mode, "r|w", 3))
4644 {
4645 imode = 0;
4646 input_line_pointer += 3;
4647 }
4648 else if (!strncmp (mode, "r", 1))
4649 {
4650 imode = ARC_REGISTER_READONLY;
4651 input_line_pointer += 1;
4652 }
4653 else if (strncmp (mode, "w", 1))
4654 {
4655 as_bad (_("invalid mode"));
4656 ignore_rest_of_line ();
4657 free (name);
06911889 4658 return FALSE;
f36e33da
CZ		 4659 }
4660 else
4661 {
4662 imode = ARC_REGISTER_WRITEONLY;
4663 input_line_pointer += 1;
4664 }
4665 }
4666
4667 if (isCore_p)
4668 {
4669 /* 4th: get core register shortcut. */
4670 SKIP_WHITESPACE ();
4671 if (*input_line_pointer != ',')
4672 {
4673 as_bad (_("expected comma after register mode"));
4674 ignore_rest_of_line ();
4675 free (name);
06911889 4676 return FALSE;
f36e33da
CZ		 4677 }
4678
4679 input_line_pointer++;
4680
4681 if (!strncmp (input_line_pointer, "cannot_shortcut", 15))
4682 {
4683 imode |= ARC_REGISTER_NOSHORT_CUT;
4684 input_line_pointer += 15;
4685 }
4686 else if (strncmp (input_line_pointer, "can_shortcut", 12))
4687 {
4688 as_bad (_("shortcut designator invalid"));
4689 ignore_rest_of_line ();
4690 free (name);
06911889 4691 return FALSE;
f36e33da
CZ		 4692 }
4693 else
4694 {
4695 input_line_pointer += 12;
4696 }
4697 }
4698 demand_empty_rest_of_line ();
4699
4700 ereg->name = name;
4701 ereg->number = number;
4702 ereg->imode = imode;
06911889 4703 return TRUE;
f36e33da
CZ		 4704}
4705
4706/* Create an extension register/condition description in the arc
4707 extension section of the output file.
4708
4709 The structure for an instruction is like this:
4710 [0]: Length of the record.
4711 [1]: Type of the record.
4712
4713 For core regs and condition codes:
4714 [2]: Value.
4715 [3]+ Name.
4716
33eaf5de 4717 For auxiliary registers:
f36e33da
CZ		 4718 [2..5]: Value.
4719 [6]+ Name
4720
4721 The sequence is terminated by an empty entry. */
4722
4723static void
4724create_extcore_section (extRegister_t *ereg, int opertype)
4725{
4726 segT old_sec = now_seg;
4727 int old_subsec = now_subseg;
4728 char *p;
4729 int name_len = strlen (ereg->name);
4730
4731 arc_set_ext_seg ();
4732
4733 switch (opertype)
4734 {
4735 case EXT_COND_CODE:
4736 case EXT_CORE_REGISTER:
4737 p = frag_more (1);
4738 *p = 3 + name_len + 1;
4739 p = frag_more (1);
4740 *p = opertype;
4741 p = frag_more (1);
4742 *p = ereg->number;
4743 break;
4744 case EXT_AUX_REGISTER:
4745 p = frag_more (1);
4746 *p = 6 + name_len + 1;
4747 p = frag_more (1);
4748 *p = EXT_AUX_REGISTER;
4749 p = frag_more (1);
4750 *p = (ereg->number >> 24) & 0xff;
4751 p = frag_more (1);
4752 *p = (ereg->number >> 16) & 0xff;
4753 p = frag_more (1);
4754 *p = (ereg->number >> 8) & 0xff;
4755 p = frag_more (1);
4756 *p = (ereg->number) & 0xff;
4757 break;
4758 default:
4759 break;
4760 }
4761
4762 p = frag_more (name_len + 1);
4763 strcpy (p, ereg->name);
4764
4765 subseg_set (old_sec, old_subsec);
4766}
4767
4768/* Handler .extCoreRegister pseudo-op. */
4769
4770static void
4771arc_extcorereg (int opertype)
4772{
4773 extRegister_t ereg;
4774 struct arc_aux_reg *auxr;
4775 const char *retval;
4776 struct arc_flag_operand *ccode;
4777
4778 memset (&ereg, 0, sizeof (ereg));
06911889
CZ		 4779 if (!tokenize_extregister (&ereg, opertype))
4780 return;
f36e33da
CZ		 4781
4782 switch (opertype)
4783 {
4784 case EXT_CORE_REGISTER:
4785 /* Core register. */
4786 if (ereg.number > 60)
4787 as_bad (_("core register %s value (%d) too large"), ereg.name,
4788 ereg.number);
4789 declare_register (ereg.name, ereg.number);
4790 break;
4791 case EXT_AUX_REGISTER:
4792 /* Auxiliary register. */
add39d23 4793 auxr = XNEW (struct arc_aux_reg);
f36e33da 4794 auxr->name = ereg.name;
bb65a718 4795 auxr->cpu = selected_cpu.flags;
f36e33da
CZ		 4796 auxr->subclass = NONE;
4797 auxr->address = ereg.number;
4798 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
4799 if (retval)
4800 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4801 auxr->name, retval);
4802 break;
4803 case EXT_COND_CODE:
4804 /* Condition code. */
4805 if (ereg.number > 31)
4806 as_bad (_("condition code %s value (%d) too large"), ereg.name,
4807 ereg.number);
4808 ext_condcode.size ++;
4809 ext_condcode.arc_ext_condcode =
add39d23
TS		 4810 XRESIZEVEC (struct arc_flag_operand, ext_condcode.arc_ext_condcode,
4811 ext_condcode.size + 1);
f36e33da
CZ		 4812 if (ext_condcode.arc_ext_condcode == NULL)
4813 as_fatal (_("Virtual memory exhausted"));
4814
4815 ccode = ext_condcode.arc_ext_condcode + ext_condcode.size - 1;
4816 ccode->name = ereg.name;
4817 ccode->code = ereg.number;
4818 ccode->bits = 5;
4819 ccode->shift = 0;
4820 ccode->favail = 0; /* not used. */
4821 ccode++;
4822 memset (ccode, 0, sizeof (struct arc_flag_operand));
4823 break;
4824 default:
4825 as_bad (_("Unknown extension"));
4826 break;
4827 }
4828 create_extcore_section (&ereg, opertype);
4829}
4830
b99747ae
CZ		 4831/* Local variables:
4832 eval: (c-set-style "gnu")
4833 indent-tabs-mode: t
4834 End: */
GDB Binutils - Deliverables
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