Commit | Line | Data |
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252b5132 | 1 | /* tc-arc.c -- Assembler for the ARC |
6f2750fe | 2 | Copyright (C) 1994-2016 Free Software Foundation, Inc. |
886a2506 NC |
3 | |
4 | Contributor: Claudiu Zissulescu <claziss@synopsys.com> | |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19203624 | 19 | along with GAS; see the file COPYING. If not, write to the Free |
4b4da160 NC |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
252b5132 | 22 | |
252b5132 | 23 | #include "as.h" |
886a2506 | 24 | #include "subsegs.h" |
a161fe53 | 25 | #include "struc-symbol.h" |
886a2506 | 26 | #include "dwarf2dbg.h" |
726c18e1 | 27 | #include "dw2gencfi.h" |
3882b010 | 28 | #include "safe-ctype.h" |
886a2506 | 29 | |
252b5132 RH |
30 | #include "opcode/arc.h" |
31 | #include "elf/arc.h" | |
b99747ae | 32 | #include "../opcodes/arc-ext.h" |
252b5132 | 33 | |
886a2506 | 34 | /* Defines section. */ |
0d2bcfaf | 35 | |
886a2506 NC |
36 | #define MAX_INSN_FIXUPS 2 |
37 | #define MAX_CONSTR_STR 20 | |
4670103e | 38 | #define FRAG_MAX_GROWTH 8 |
0d2bcfaf | 39 | |
886a2506 NC |
40 | #ifdef DEBUG |
41 | # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args) | |
42 | #else | |
43 | # define pr_debug(fmt, args...) | |
44 | #endif | |
45 | ||
46 | #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27) | |
47 | #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16) | |
db18dbab GM |
48 | #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \ |
49 | && (SUB_OPCODE (x) == 0x28)) | |
886a2506 NC |
50 | |
51 | /* Equal to MAX_PRECISION in atof-ieee.c. */ | |
52 | #define MAX_LITTLENUMS 6 | |
53 | ||
9004b6bd AB |
54 | #ifndef TARGET_WITH_CPU |
55 | #define TARGET_WITH_CPU "arc700" | |
56 | #endif /* TARGET_WITH_CPU */ | |
57 | ||
4670103e CZ |
58 | /* Enum used to enumerate the relaxable ins operands. */ |
59 | enum rlx_operand_type | |
60 | { | |
61 | EMPTY = 0, | |
62 | REGISTER, | |
63 | REGISTER_S, /* Register for short instruction(s). */ | |
64 | REGISTER_NO_GP, /* Is a register but not gp register specifically. */ | |
65 | REGISTER_DUP, /* Duplication of previous operand of type register. */ | |
66 | IMMEDIATE, | |
67 | BRACKET | |
68 | }; | |
69 | ||
70 | enum arc_rlx_types | |
71 | { | |
72 | ARC_RLX_NONE = 0, | |
73 | ARC_RLX_BL_S, | |
74 | ARC_RLX_BL, | |
75 | ARC_RLX_B_S, | |
76 | ARC_RLX_B, | |
77 | ARC_RLX_ADD_U3, | |
78 | ARC_RLX_ADD_U6, | |
79 | ARC_RLX_ADD_LIMM, | |
80 | ARC_RLX_LD_U7, | |
81 | ARC_RLX_LD_S9, | |
82 | ARC_RLX_LD_LIMM, | |
83 | ARC_RLX_MOV_U8, | |
84 | ARC_RLX_MOV_S12, | |
85 | ARC_RLX_MOV_LIMM, | |
86 | ARC_RLX_SUB_U3, | |
87 | ARC_RLX_SUB_U6, | |
88 | ARC_RLX_SUB_LIMM, | |
89 | ARC_RLX_MPY_U6, | |
90 | ARC_RLX_MPY_LIMM, | |
91 | ARC_RLX_MOV_RU6, | |
92 | ARC_RLX_MOV_RLIMM, | |
93 | ARC_RLX_ADD_RRU6, | |
94 | ARC_RLX_ADD_RRLIMM, | |
95 | }; | |
96 | ||
886a2506 NC |
97 | /* Macros section. */ |
98 | ||
99 | #define regno(x) ((x) & 0x3F) | |
100 | #define is_ir_num(x) (((x) & ~0x3F) == 0) | |
8ddf6b2a CZ |
101 | #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2)) |
102 | #define is_spfp_p(op) (((sc) == SPX)) | |
103 | #define is_dpfp_p(op) (((sc) == DPX)) | |
104 | #define is_fpuda_p(op) (((sc) == DPA)) | |
db18dbab GM |
105 | #define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \ |
106 | || (op)->insn_class == JUMP)) | |
c810e0b8 | 107 | #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL)) |
bdd582db | 108 | #define is_nps400_p(op) (((sc) == NPS400)) |
0d2bcfaf | 109 | |
886a2506 NC |
110 | /* Generic assembler global variables which must be defined by all |
111 | targets. */ | |
0d2bcfaf | 112 | |
886a2506 | 113 | /* Characters which always start a comment. */ |
252b5132 RH |
114 | const char comment_chars[] = "#;"; |
115 | ||
886a2506 | 116 | /* Characters which start a comment at the beginning of a line. */ |
252b5132 RH |
117 | const char line_comment_chars[] = "#"; |
118 | ||
886a2506 NC |
119 | /* Characters which may be used to separate multiple commands on a |
120 | single line. */ | |
121 | const char line_separator_chars[] = "`"; | |
252b5132 | 122 | |
886a2506 NC |
123 | /* Characters which are used to indicate an exponent in a floating |
124 | point number. */ | |
252b5132 RH |
125 | const char EXP_CHARS[] = "eE"; |
126 | ||
bcee8eb8 AM |
127 | /* Chars that mean this number is a floating point constant |
128 | As in 0f12.456 or 0d1.2345e12. */ | |
252b5132 RH |
129 | const char FLT_CHARS[] = "rRsSfFdD"; |
130 | ||
131 | /* Byte order. */ | |
132 | extern int target_big_endian; | |
133 | const char *arc_target_format = DEFAULT_TARGET_FORMAT; | |
134 | static int byte_order = DEFAULT_BYTE_ORDER; | |
135 | ||
b99747ae CZ |
136 | /* Arc extension section. */ |
137 | static segT arcext_section; | |
138 | ||
4670103e CZ |
139 | /* By default relaxation is disabled. */ |
140 | static int relaxation_state = 0; | |
141 | ||
886a2506 | 142 | extern int arc_get_mach (char *); |
0d2bcfaf | 143 | |
4670103e | 144 | /* Forward declarations. */ |
886a2506 NC |
145 | static void arc_lcomm (int); |
146 | static void arc_option (int); | |
147 | static void arc_extra_reloc (int); | |
b99747ae | 148 | static void arc_extinsn (int); |
f36e33da | 149 | static void arc_extcorereg (int); |
4670103e | 150 | |
886a2506 | 151 | const pseudo_typeS md_pseudo_table[] = |
6f4b1afc CM |
152 | { |
153 | /* Make sure that .word is 32 bits. */ | |
154 | { "word", cons, 4 }, | |
886a2506 | 155 | |
6f4b1afc CM |
156 | { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ |
157 | { "lcomm", arc_lcomm, 0 }, | |
158 | { "lcommon", arc_lcomm, 0 }, | |
159 | { "cpu", arc_option, 0 }, | |
252b5132 | 160 | |
f36e33da CZ |
161 | { "extinstruction", arc_extinsn, 0 }, |
162 | { "extcoreregister", arc_extcorereg, EXT_CORE_REGISTER }, | |
163 | { "extauxregister", arc_extcorereg, EXT_AUX_REGISTER }, | |
164 | { "extcondcode", arc_extcorereg, EXT_COND_CODE }, | |
b99747ae | 165 | |
6f4b1afc CM |
166 | { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD }, |
167 | { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL }, | |
886a2506 | 168 | |
6f4b1afc CM |
169 | { NULL, NULL, 0 } |
170 | }; | |
252b5132 | 171 | |
252b5132 | 172 | const char *md_shortopts = ""; |
ea1562b3 NC |
173 | |
174 | enum options | |
6f4b1afc CM |
175 | { |
176 | OPTION_EB = OPTION_MD_BASE, | |
177 | OPTION_EL, | |
178 | ||
179 | OPTION_ARC600, | |
180 | OPTION_ARC601, | |
181 | OPTION_ARC700, | |
182 | OPTION_ARCEM, | |
183 | OPTION_ARCHS, | |
184 | ||
185 | OPTION_MCPU, | |
186 | OPTION_CD, | |
4670103e | 187 | OPTION_RELAX, |
bdd582db | 188 | OPTION_NPS400, |
6f4b1afc | 189 | |
ce440d63 GM |
190 | OPTION_SPFP, |
191 | OPTION_DPFP, | |
192 | OPTION_FPUDA, | |
193 | ||
6f4b1afc CM |
194 | /* The following options are deprecated and provided here only for |
195 | compatibility reasons. */ | |
196 | OPTION_USER_MODE, | |
197 | OPTION_LD_EXT_MASK, | |
198 | OPTION_SWAP, | |
199 | OPTION_NORM, | |
200 | OPTION_BARREL_SHIFT, | |
201 | OPTION_MIN_MAX, | |
202 | OPTION_NO_MPY, | |
203 | OPTION_EA, | |
204 | OPTION_MUL64, | |
205 | OPTION_SIMD, | |
6f4b1afc CM |
206 | OPTION_XMAC_D16, |
207 | OPTION_XMAC_24, | |
208 | OPTION_DSP_PACKA, | |
209 | OPTION_CRC, | |
210 | OPTION_DVBF, | |
211 | OPTION_TELEPHONY, | |
212 | OPTION_XYMEMORY, | |
213 | OPTION_LOCK, | |
214 | OPTION_SWAPE, | |
ce440d63 | 215 | OPTION_RTSC |
6f4b1afc | 216 | }; |
ea1562b3 NC |
217 | |
218 | struct option md_longopts[] = | |
6f4b1afc CM |
219 | { |
220 | { "EB", no_argument, NULL, OPTION_EB }, | |
221 | { "EL", no_argument, NULL, OPTION_EL }, | |
222 | { "mcpu", required_argument, NULL, OPTION_MCPU }, | |
223 | { "mA6", no_argument, NULL, OPTION_ARC600 }, | |
24b368f8 CZ |
224 | { "mARC600", no_argument, NULL, OPTION_ARC600 }, |
225 | { "mARC601", no_argument, NULL, OPTION_ARC601 }, | |
226 | { "mARC700", no_argument, NULL, OPTION_ARC700 }, | |
6f4b1afc CM |
227 | { "mA7", no_argument, NULL, OPTION_ARC700 }, |
228 | { "mEM", no_argument, NULL, OPTION_ARCEM }, | |
229 | { "mHS", no_argument, NULL, OPTION_ARCHS }, | |
230 | { "mcode-density", no_argument, NULL, OPTION_CD }, | |
4670103e | 231 | { "mrelax", no_argument, NULL, OPTION_RELAX }, |
bdd582db | 232 | { "mnps400", no_argument, NULL, OPTION_NPS400 }, |
6f4b1afc | 233 | |
ce440d63 GM |
234 | /* Floating point options */ |
235 | { "mspfp", no_argument, NULL, OPTION_SPFP}, | |
236 | { "mspfp-compact", no_argument, NULL, OPTION_SPFP}, | |
237 | { "mspfp_compact", no_argument, NULL, OPTION_SPFP}, | |
238 | { "mspfp-fast", no_argument, NULL, OPTION_SPFP}, | |
239 | { "mspfp_fast", no_argument, NULL, OPTION_SPFP}, | |
240 | { "mdpfp", no_argument, NULL, OPTION_DPFP}, | |
241 | { "mdpfp-compact", no_argument, NULL, OPTION_DPFP}, | |
242 | { "mdpfp_compact", no_argument, NULL, OPTION_DPFP}, | |
243 | { "mdpfp-fast", no_argument, NULL, OPTION_DPFP}, | |
244 | { "mdpfp_fast", no_argument, NULL, OPTION_DPFP}, | |
245 | { "mfpuda", no_argument, NULL, OPTION_FPUDA}, | |
246 | ||
6f4b1afc CM |
247 | /* The following options are deprecated and provided here only for |
248 | compatibility reasons. */ | |
249 | { "mav2em", no_argument, NULL, OPTION_ARCEM }, | |
250 | { "mav2hs", no_argument, NULL, OPTION_ARCHS }, | |
251 | { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE }, | |
252 | { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK }, | |
253 | { "mswap", no_argument, NULL, OPTION_SWAP }, | |
254 | { "mnorm", no_argument, NULL, OPTION_NORM }, | |
255 | { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT }, | |
256 | { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT }, | |
257 | { "mmin-max", no_argument, NULL, OPTION_MIN_MAX }, | |
258 | { "mmin_max", no_argument, NULL, OPTION_MIN_MAX }, | |
259 | { "mno-mpy", no_argument, NULL, OPTION_NO_MPY }, | |
260 | { "mea", no_argument, NULL, OPTION_EA }, | |
261 | { "mEA", no_argument, NULL, OPTION_EA }, | |
262 | { "mmul64", no_argument, NULL, OPTION_MUL64 }, | |
263 | { "msimd", no_argument, NULL, OPTION_SIMD}, | |
6f4b1afc CM |
264 | { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16}, |
265 | { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16}, | |
266 | { "mmac-24", no_argument, NULL, OPTION_XMAC_24}, | |
267 | { "mmac_24", no_argument, NULL, OPTION_XMAC_24}, | |
268 | { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA}, | |
269 | { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA}, | |
270 | { "mcrc", no_argument, NULL, OPTION_CRC}, | |
271 | { "mdvbf", no_argument, NULL, OPTION_DVBF}, | |
272 | { "mtelephony", no_argument, NULL, OPTION_TELEPHONY}, | |
273 | { "mxy", no_argument, NULL, OPTION_XYMEMORY}, | |
274 | { "mlock", no_argument, NULL, OPTION_LOCK}, | |
275 | { "mswape", no_argument, NULL, OPTION_SWAPE}, | |
276 | { "mrtsc", no_argument, NULL, OPTION_RTSC}, | |
6f4b1afc CM |
277 | |
278 | { NULL, no_argument, NULL, 0 } | |
279 | }; | |
252b5132 | 280 | |
886a2506 | 281 | size_t md_longopts_size = sizeof (md_longopts); |
0d2bcfaf | 282 | |
886a2506 | 283 | /* Local data and data types. */ |
252b5132 | 284 | |
886a2506 NC |
285 | /* Used since new relocation types are introduced in this |
286 | file (DUMMY_RELOC_LITUSE_*). */ | |
287 | typedef int extended_bfd_reloc_code_real_type; | |
252b5132 | 288 | |
886a2506 | 289 | struct arc_fixup |
252b5132 | 290 | { |
886a2506 | 291 | expressionS exp; |
252b5132 | 292 | |
886a2506 | 293 | extended_bfd_reloc_code_real_type reloc; |
252b5132 | 294 | |
886a2506 NC |
295 | /* index into arc_operands. */ |
296 | unsigned int opindex; | |
252b5132 | 297 | |
886a2506 NC |
298 | /* PC-relative, used by internals fixups. */ |
299 | unsigned char pcrel; | |
252b5132 | 300 | |
886a2506 NC |
301 | /* TRUE if this fixup is for LIMM operand. */ |
302 | bfd_boolean islong; | |
303 | }; | |
252b5132 | 304 | |
886a2506 NC |
305 | struct arc_insn |
306 | { | |
bdfe53e3 | 307 | unsigned long long int insn; |
886a2506 NC |
308 | int nfixups; |
309 | struct arc_fixup fixups[MAX_INSN_FIXUPS]; | |
310 | long limm; | |
91fdca6f | 311 | unsigned int len; /* Length of instruction in bytes. */ |
886a2506 NC |
312 | bfd_boolean has_limm; /* Boolean value: TRUE if limm field is |
313 | valid. */ | |
4670103e CZ |
314 | bfd_boolean relax; /* Boolean value: TRUE if needs |
315 | relaxation. */ | |
886a2506 | 316 | }; |
ea1562b3 | 317 | |
886a2506 NC |
318 | /* Structure to hold any last two instructions. */ |
319 | static struct arc_last_insn | |
252b5132 | 320 | { |
886a2506 NC |
321 | /* Saved instruction opcode. */ |
322 | const struct arc_opcode *opcode; | |
252b5132 | 323 | |
886a2506 NC |
324 | /* Boolean value: TRUE if current insn is short. */ |
325 | bfd_boolean has_limm; | |
252b5132 | 326 | |
886a2506 NC |
327 | /* Boolean value: TRUE if current insn has delay slot. */ |
328 | bfd_boolean has_delay_slot; | |
329 | } arc_last_insns[2]; | |
252b5132 | 330 | |
b99747ae CZ |
331 | /* Extension instruction suffix classes. */ |
332 | typedef struct | |
333 | { | |
334 | const char *name; | |
335 | int len; | |
c810e0b8 | 336 | int attr_class; |
b99747ae CZ |
337 | } attributes_t; |
338 | ||
339 | static const attributes_t suffixclass[] = | |
340 | { | |
341 | { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG }, | |
342 | { "SUFFIX_COND", 11, ARC_SUFFIX_COND }, | |
343 | { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE } | |
344 | }; | |
345 | ||
346 | /* Extension instruction syntax classes. */ | |
347 | static const attributes_t syntaxclass[] = | |
348 | { | |
349 | { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP }, | |
945e0f82 CZ |
350 | { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP }, |
351 | { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP }, | |
352 | { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP } | |
b99747ae CZ |
353 | }; |
354 | ||
355 | /* Extension instruction syntax classes modifiers. */ | |
356 | static const attributes_t syntaxclassmod[] = | |
357 | { | |
358 | { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED }, | |
359 | { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM } | |
360 | }; | |
361 | ||
f36e33da CZ |
362 | /* Extension register type. */ |
363 | typedef struct | |
364 | { | |
365 | char *name; | |
366 | int number; | |
367 | int imode; | |
368 | } extRegister_t; | |
369 | ||
370 | /* A structure to hold the additional conditional codes. */ | |
371 | static struct | |
372 | { | |
373 | struct arc_flag_operand *arc_ext_condcode; | |
374 | int size; | |
375 | } ext_condcode = { NULL, 0 }; | |
376 | ||
da5be039 AB |
377 | /* Structure to hold an entry in ARC_OPCODE_HASH. */ |
378 | struct arc_opcode_hash_entry | |
379 | { | |
380 | /* The number of pointers in the OPCODE list. */ | |
381 | size_t count; | |
382 | ||
383 | /* Points to a list of opcode pointers. */ | |
384 | const struct arc_opcode **opcode; | |
385 | }; | |
386 | ||
1328504b AB |
387 | /* Structure used for iterating through an arc_opcode_hash_entry. */ |
388 | struct arc_opcode_hash_entry_iterator | |
389 | { | |
390 | /* Index into the OPCODE element of the arc_opcode_hash_entry. */ | |
391 | size_t index; | |
392 | ||
393 | /* The specific ARC_OPCODE from the ARC_OPCODES table that was last | |
394 | returned by this iterator. */ | |
395 | const struct arc_opcode *opcode; | |
396 | }; | |
397 | ||
4670103e CZ |
398 | /* Forward declaration. */ |
399 | static void assemble_insn | |
400 | (const struct arc_opcode *, const expressionS *, int, | |
401 | const struct arc_flags *, int, struct arc_insn *); | |
402 | ||
bb65a718 AB |
403 | /* The selection of the machine type can come from different sources. This |
404 | enum is used to track how the selection was made in order to perform | |
405 | error checks. */ | |
406 | enum mach_selection_type | |
407 | { | |
408 | MACH_SELECTION_NONE, | |
409 | MACH_SELECTION_FROM_DEFAULT, | |
410 | MACH_SELECTION_FROM_CPU_DIRECTIVE, | |
411 | MACH_SELECTION_FROM_COMMAND_LINE | |
412 | }; | |
413 | ||
414 | /* How the current machine type was selected. */ | |
415 | static enum mach_selection_type mach_selection_mode = MACH_SELECTION_NONE; | |
0d2bcfaf | 416 | |
886a2506 NC |
417 | /* The hash table of instruction opcodes. */ |
418 | static struct hash_control *arc_opcode_hash; | |
0d2bcfaf | 419 | |
886a2506 NC |
420 | /* The hash table of register symbols. */ |
421 | static struct hash_control *arc_reg_hash; | |
252b5132 | 422 | |
f36e33da CZ |
423 | /* The hash table of aux register symbols. */ |
424 | static struct hash_control *arc_aux_hash; | |
425 | ||
db18dbab GM |
426 | /* The hash table of address types. */ |
427 | static struct hash_control *arc_addrtype_hash; | |
428 | ||
886a2506 NC |
429 | /* A table of CPU names and opcode sets. */ |
430 | static const struct cpu_type | |
431 | { | |
432 | const char *name; | |
433 | unsigned flags; | |
434 | int mach; | |
435 | unsigned eflags; | |
436 | unsigned features; | |
252b5132 | 437 | } |
886a2506 | 438 | cpu_types[] = |
252b5132 | 439 | { |
886a2506 NC |
440 | { "arc600", ARC_OPCODE_ARC600, bfd_mach_arc_arc600, |
441 | E_ARC_MACH_ARC600, 0x00}, | |
442 | { "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700, | |
443 | E_ARC_MACH_ARC700, 0x00}, | |
bdd582db GM |
444 | { "nps400", ARC_OPCODE_ARC700 , bfd_mach_arc_arc700, |
445 | E_ARC_MACH_ARC700, ARC_NPS400}, | |
886a2506 | 446 | { "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, |
87789e08 | 447 | EF_ARC_CPU_ARCV2EM, 0x00}, |
886a2506 NC |
448 | { "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, |
449 | EF_ARC_CPU_ARCV2HS, ARC_CD}, | |
886a2506 NC |
450 | { 0, 0, 0, 0, 0 } |
451 | }; | |
252b5132 | 452 | |
bb65a718 | 453 | /* Information about the cpu/variant we're assembling for. */ |
bb050a69 CZ |
454 | static struct cpu_type selected_cpu = { 0, 0, 0, 0, 0 }; |
455 | ||
456 | /* A table with options. */ | |
457 | static const struct feature_type | |
458 | { | |
459 | unsigned feature; | |
460 | unsigned cpus; | |
461 | const char *name; | |
462 | } | |
463 | feature_list[] = | |
464 | { | |
465 | { ARC_CD, ARC_OPCODE_ARCV2, "code-density" }, | |
466 | { ARC_NPS400, ARC_OPCODE_ARC700, "nps400" }, | |
467 | { ARC_SPFP, ARC_OPCODE_ARCFPX, "single-precision FPX" }, | |
468 | { ARC_DPFP, ARC_OPCODE_ARCFPX, "double-precision FPX" }, | |
469 | { ARC_FPUDA, ARC_OPCODE_ARCv2EM, "double assist FP" } | |
470 | }; | |
bb65a718 | 471 | |
886a2506 NC |
472 | /* Used by the arc_reloc_op table. Order is important. */ |
473 | #define O_gotoff O_md1 /* @gotoff relocation. */ | |
474 | #define O_gotpc O_md2 /* @gotpc relocation. */ | |
475 | #define O_plt O_md3 /* @plt relocation. */ | |
476 | #define O_sda O_md4 /* @sda relocation. */ | |
477 | #define O_pcl O_md5 /* @pcl relocation. */ | |
478 | #define O_tlsgd O_md6 /* @tlsgd relocation. */ | |
479 | #define O_tlsie O_md7 /* @tlsie relocation. */ | |
480 | #define O_tpoff9 O_md8 /* @tpoff9 relocation. */ | |
481 | #define O_tpoff O_md9 /* @tpoff relocation. */ | |
482 | #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */ | |
483 | #define O_dtpoff O_md11 /* @dtpoff relocation. */ | |
484 | #define O_last O_dtpoff | |
485 | ||
486 | /* Used to define a bracket as operand in tokens. */ | |
487 | #define O_bracket O_md32 | |
488 | ||
db18dbab GM |
489 | /* Used to define a colon as an operand in tokens. */ |
490 | #define O_colon O_md31 | |
491 | ||
492 | /* Used to define address types in nps400. */ | |
493 | #define O_addrtype O_md30 | |
494 | ||
886a2506 NC |
495 | /* Dummy relocation, to be sorted out. */ |
496 | #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1) | |
497 | ||
498 | #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last) | |
499 | ||
500 | /* A table to map the spelling of a relocation operand into an appropriate | |
501 | bfd_reloc_code_real_type type. The table is assumed to be ordered such | |
502 | that op-O_literal indexes into it. */ | |
503 | #define ARC_RELOC_TABLE(op) \ | |
504 | (&arc_reloc_op[ ((!USER_RELOC_P (op)) \ | |
505 | ? (abort (), 0) \ | |
506 | : (int) (op) - (int) O_gotoff) ]) | |
507 | ||
508 | #define DEF(NAME, RELOC, REQ) \ | |
509 | { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ} | |
510 | ||
511 | static const struct arc_reloc_op_tag | |
512 | { | |
513 | /* String to lookup. */ | |
514 | const char *name; | |
515 | /* Size of the string. */ | |
516 | size_t length; | |
517 | /* Which operator to use. */ | |
518 | operatorT op; | |
519 | extended_bfd_reloc_code_real_type reloc; | |
520 | /* Allows complex relocation expression like identifier@reloc + | |
521 | const. */ | |
522 | unsigned int complex_expr : 1; | |
523 | } | |
524 | arc_reloc_op[] = | |
6f4b1afc CM |
525 | { |
526 | DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1), | |
527 | DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0), | |
528 | DEF (plt, BFD_RELOC_ARC_PLT32, 0), | |
529 | DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1), | |
530 | DEF (pcl, BFD_RELOC_ARC_PC32, 1), | |
531 | DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0), | |
532 | DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0), | |
533 | DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0), | |
b125bd17 | 534 | DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1), |
6f4b1afc | 535 | DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0), |
05bbf016 | 536 | DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 1), |
6f4b1afc | 537 | }; |
252b5132 | 538 | |
886a2506 NC |
539 | static const int arc_num_reloc_op |
540 | = sizeof (arc_reloc_op) / sizeof (*arc_reloc_op); | |
541 | ||
4670103e CZ |
542 | /* Structure for relaxable instruction that have to be swapped with a |
543 | smaller alternative instruction. */ | |
544 | struct arc_relaxable_ins | |
545 | { | |
546 | /* Mnemonic that should be checked. */ | |
547 | const char *mnemonic_r; | |
548 | ||
549 | /* Operands that should be checked. | |
550 | Indexes of operands from operand array. */ | |
551 | enum rlx_operand_type operands[6]; | |
552 | ||
553 | /* Flags that should be checked. */ | |
554 | unsigned flag_classes[5]; | |
555 | ||
556 | /* Mnemonic (smaller) alternative to be used later for relaxation. */ | |
557 | const char *mnemonic_alt; | |
558 | ||
559 | /* Index of operand that generic relaxation has to check. */ | |
560 | unsigned opcheckidx; | |
561 | ||
562 | /* Base subtype index used. */ | |
563 | enum arc_rlx_types subtype; | |
564 | }; | |
565 | ||
566 | #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \ | |
567 | { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \ | |
568 | (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \ | |
569 | (SIZE), \ | |
570 | (NEXT) } \ | |
571 | ||
572 | #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \ | |
573 | { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \ | |
574 | (ISSIGNED) ? -(0x7FFFFFFF) : 0, \ | |
575 | (SIZE), \ | |
576 | (NEXT) } \ | |
577 | ||
578 | ||
579 | /* ARC relaxation table. */ | |
580 | const relax_typeS md_relax_table[] = | |
581 | { | |
582 | /* Fake entry. */ | |
583 | {0, 0, 0, 0}, | |
584 | ||
585 | /* BL_S s13 -> | |
586 | BL s25. */ | |
db18dbab GM |
587 | RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL), |
588 | RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE), | |
4670103e CZ |
589 | |
590 | /* B_S s10 -> | |
591 | B s25. */ | |
db18dbab GM |
592 | RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B), |
593 | RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE), | |
4670103e CZ |
594 | |
595 | /* ADD_S c,b, u3 -> | |
596 | ADD<.f> a,b,u6 -> | |
597 | ADD<.f> a,b,limm. */ | |
db18dbab GM |
598 | RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6), |
599 | RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM), | |
600 | RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE), | |
4670103e CZ |
601 | |
602 | /* LD_S a, [b, u7] -> | |
603 | LD<zz><.x><.aa><.di> a, [b, s9] -> | |
604 | LD<zz><.x><.aa><.di> a, [b, limm] */ | |
db18dbab GM |
605 | RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9), |
606 | RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM), | |
607 | RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE), | |
4670103e CZ |
608 | |
609 | /* MOV_S b, u8 -> | |
610 | MOV<.f> b, s12 -> | |
611 | MOV<.f> b, limm. */ | |
db18dbab GM |
612 | RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12), |
613 | RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM), | |
614 | RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE), | |
4670103e CZ |
615 | |
616 | /* SUB_S c, b, u3 -> | |
617 | SUB<.f> a, b, u6 -> | |
618 | SUB<.f> a, b, limm. */ | |
db18dbab GM |
619 | RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6), |
620 | RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM), | |
621 | RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE), | |
4670103e CZ |
622 | |
623 | /* MPY<.f> a, b, u6 -> | |
624 | MPY<.f> a, b, limm. */ | |
db18dbab GM |
625 | RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM), |
626 | RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE), | |
4670103e CZ |
627 | |
628 | /* MOV<.f><.cc> b, u6 -> | |
629 | MOV<.f><.cc> b, limm. */ | |
db18dbab GM |
630 | RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM), |
631 | RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE), | |
4670103e CZ |
632 | |
633 | /* ADD<.f><.cc> b, b, u6 -> | |
634 | ADD<.f><.cc> b, b, limm. */ | |
db18dbab GM |
635 | RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM), |
636 | RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE), | |
4670103e CZ |
637 | }; |
638 | ||
639 | /* Order of this table's entries matters! */ | |
640 | const struct arc_relaxable_ins arc_relaxable_insns[] = | |
641 | { | |
642 | { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S }, | |
643 | { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S }, | |
644 | { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add", | |
645 | 2, ARC_RLX_ADD_RRU6}, | |
646 | { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2, | |
647 | ARC_RLX_ADD_U3 }, | |
648 | { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2, | |
649 | ARC_RLX_ADD_U6 }, | |
650 | { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET }, | |
651 | { 0 }, "ld_s", 3, ARC_RLX_LD_U7 }, | |
652 | { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET }, | |
653 | { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 }, | |
654 | { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 }, | |
655 | { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 }, | |
656 | { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 }, | |
657 | { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2, | |
658 | ARC_RLX_SUB_U3 }, | |
659 | { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2, | |
660 | ARC_RLX_SUB_U6 }, | |
661 | { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2, | |
662 | ARC_RLX_MPY_U6 }, | |
663 | }; | |
664 | ||
665 | const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns); | |
666 | ||
886a2506 | 667 | /* Flags to set in the elf header. */ |
bb65a718 | 668 | static const flagword arc_initial_eflag = 0x00; |
886a2506 NC |
669 | |
670 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ | |
671 | symbolS * GOT_symbol = 0; | |
672 | ||
673 | /* Set to TRUE when we assemble instructions. */ | |
674 | static bfd_boolean assembling_insn = FALSE; | |
675 | ||
886a2506 NC |
676 | /* Functions implementation. */ |
677 | ||
b9b47ab7 AB |
678 | /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all |
679 | ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there | |
680 | are no matching entries in ARC_OPCODE_HASH. */ | |
da5be039 | 681 | |
b9b47ab7 | 682 | static const struct arc_opcode_hash_entry * |
da5be039 AB |
683 | arc_find_opcode (const char *name) |
684 | { | |
685 | const struct arc_opcode_hash_entry *entry; | |
da5be039 AB |
686 | |
687 | entry = hash_find (arc_opcode_hash, name); | |
b9b47ab7 | 688 | return entry; |
da5be039 AB |
689 | } |
690 | ||
1328504b AB |
691 | /* Initialise the iterator ITER. */ |
692 | ||
693 | static void | |
694 | arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator *iter) | |
695 | { | |
696 | iter->index = 0; | |
697 | iter->opcode = NULL; | |
698 | } | |
699 | ||
700 | /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between | |
701 | calls to this function. Return NULL when all ARC_OPCODE entries have | |
702 | been returned. */ | |
703 | ||
704 | static const struct arc_opcode * | |
705 | arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry, | |
706 | struct arc_opcode_hash_entry_iterator *iter) | |
707 | { | |
708 | if (iter->opcode == NULL && iter->index == 0) | |
709 | { | |
710 | gas_assert (entry->count > 0); | |
711 | iter->opcode = entry->opcode[iter->index]; | |
712 | } | |
713 | else if (iter->opcode != NULL) | |
714 | { | |
715 | const char *old_name = iter->opcode->name; | |
716 | ||
717 | iter->opcode++; | |
fe779266 AB |
718 | if (iter->opcode->name == NULL |
719 | || strcmp (old_name, iter->opcode->name) != 0) | |
1328504b AB |
720 | { |
721 | iter->index++; | |
722 | if (iter->index == entry->count) | |
723 | iter->opcode = NULL; | |
724 | else | |
725 | iter->opcode = entry->opcode[iter->index]; | |
726 | } | |
727 | } | |
728 | ||
729 | return iter->opcode; | |
730 | } | |
731 | ||
b99747ae CZ |
732 | /* Insert an opcode into opcode hash structure. */ |
733 | ||
734 | static void | |
735 | arc_insert_opcode (const struct arc_opcode *opcode) | |
736 | { | |
737 | const char *name, *retval; | |
738 | struct arc_opcode_hash_entry *entry; | |
739 | name = opcode->name; | |
740 | ||
741 | entry = hash_find (arc_opcode_hash, name); | |
742 | if (entry == NULL) | |
743 | { | |
add39d23 | 744 | entry = XNEW (struct arc_opcode_hash_entry); |
b99747ae CZ |
745 | entry->count = 0; |
746 | entry->opcode = NULL; | |
747 | ||
748 | retval = hash_insert (arc_opcode_hash, name, (void *) entry); | |
749 | if (retval) | |
750 | as_fatal (_("internal error: can't hash opcode '%s': %s"), | |
751 | name, retval); | |
752 | } | |
753 | ||
add39d23 TS |
754 | entry->opcode = XRESIZEVEC (const struct arc_opcode *, entry->opcode, |
755 | entry->count + 1); | |
b99747ae CZ |
756 | |
757 | if (entry->opcode == NULL) | |
758 | as_fatal (_("Virtual memory exhausted")); | |
759 | ||
760 | entry->opcode[entry->count] = opcode; | |
761 | entry->count++; | |
762 | } | |
763 | ||
764 | ||
bdfe53e3 AB |
765 | /* Like md_number_to_chars but for middle-endian values. The 4-byte limm |
766 | value, is encoded as 'middle-endian' for a little-endian target. This | |
767 | function is used for regular 4, 6, and 8 byte instructions as well. */ | |
886a2506 NC |
768 | |
769 | static void | |
bdfe53e3 | 770 | md_number_to_chars_midend (char *buf, unsigned long long val, int n) |
886a2506 | 771 | { |
bdfe53e3 | 772 | switch (n) |
886a2506 | 773 | { |
bdfe53e3 AB |
774 | case 2: |
775 | md_number_to_chars (buf, val, n); | |
776 | break; | |
777 | case 6: | |
778 | md_number_to_chars (buf, (val & 0xffff00000000) >> 32, 2); | |
779 | md_number_to_chars_midend (buf + 2, (val & 0xffffffff), 4); | |
780 | break; | |
781 | case 4: | |
886a2506 NC |
782 | md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2); |
783 | md_number_to_chars (buf + 2, (val & 0xffff), 2); | |
bdfe53e3 AB |
784 | break; |
785 | case 8: | |
786 | md_number_to_chars_midend (buf, (val & 0xffffffff00000000) >> 32, 4); | |
787 | md_number_to_chars_midend (buf + 4, (val & 0xffffffff), 4); | |
788 | break; | |
789 | default: | |
790 | abort (); | |
886a2506 | 791 | } |
252b5132 RH |
792 | } |
793 | ||
bb050a69 CZ |
794 | /* Check if a feature is allowed for a specific CPU. */ |
795 | ||
796 | static void | |
797 | arc_check_feature (void) | |
798 | { | |
799 | unsigned i; | |
800 | ||
801 | if (!selected_cpu.features | |
802 | || !selected_cpu.name) | |
803 | return; | |
804 | for (i = 0; (i < ARRAY_SIZE (feature_list)); i++) | |
805 | { | |
806 | if ((selected_cpu.features & feature_list[i].feature) | |
807 | && !(selected_cpu.flags & feature_list[i].cpus)) | |
808 | { | |
809 | as_bad (_("invalid %s option for %s cpu"), feature_list[i].name, | |
810 | selected_cpu.name); | |
811 | } | |
812 | } | |
813 | } | |
814 | ||
24740d83 | 815 | /* Select an appropriate entry from CPU_TYPES based on ARG and initialise |
bb65a718 AB |
816 | the relevant static global variables. Parameter SEL describes where |
817 | this selection originated from. */ | |
24740d83 AB |
818 | |
819 | static void | |
bb65a718 | 820 | arc_select_cpu (const char *arg, enum mach_selection_type sel) |
24740d83 | 821 | { |
a9522a21 | 822 | int cpu_flags = 0; |
24740d83 AB |
823 | int i; |
824 | ||
bb65a718 AB |
825 | /* We should only set a default if we've not made a selection from some |
826 | other source. */ | |
827 | gas_assert (sel != MACH_SELECTION_FROM_DEFAULT | |
828 | || mach_selection_mode == MACH_SELECTION_NONE); | |
829 | ||
bb050a69 CZ |
830 | if ((mach_selection_mode == MACH_SELECTION_FROM_CPU_DIRECTIVE) |
831 | && (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE)) | |
832 | as_bad (_("Multiple .cpu directives found")); | |
833 | ||
bb65a718 | 834 | /* Look for a matching entry in CPU_TYPES array. */ |
24740d83 AB |
835 | for (i = 0; cpu_types[i].name; ++i) |
836 | { | |
837 | if (!strcasecmp (cpu_types[i].name, arg)) | |
838 | { | |
bb65a718 AB |
839 | /* If a previous selection was made on the command line, then we |
840 | allow later selections on the command line to override earlier | |
841 | ones. However, a selection from a '.cpu NAME' directive must | |
842 | match the command line selection, or we give a warning. */ | |
843 | if (mach_selection_mode == MACH_SELECTION_FROM_COMMAND_LINE) | |
844 | { | |
845 | gas_assert (sel == MACH_SELECTION_FROM_COMMAND_LINE | |
846 | || sel == MACH_SELECTION_FROM_CPU_DIRECTIVE); | |
847 | if (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE | |
848 | && selected_cpu.mach != cpu_types[i].mach) | |
849 | { | |
850 | as_warn (_("Command-line value overrides \".cpu\" directive")); | |
bb65a718 | 851 | } |
bb050a69 | 852 | return; |
bb65a718 AB |
853 | } |
854 | ||
bb050a69 CZ |
855 | /* Initialise static global data about selected machine type. */ |
856 | selected_cpu.flags = cpu_types[i].flags; | |
857 | selected_cpu.name = cpu_types[i].name; | |
858 | selected_cpu.features |= cpu_types[i].features; | |
859 | selected_cpu.mach = cpu_types[i].mach; | |
860 | cpu_flags = cpu_types[i].eflags; | |
24740d83 AB |
861 | break; |
862 | } | |
863 | } | |
864 | ||
865 | if (!cpu_types[i].name) | |
866 | as_fatal (_("unknown architecture: %s\n"), arg); | |
bb050a69 CZ |
867 | |
868 | /* Check if set features are compatible with the chosen CPU. */ | |
869 | arc_check_feature (); | |
a9522a21 | 870 | gas_assert (cpu_flags != 0); |
bb65a718 AB |
871 | selected_cpu.eflags = (arc_initial_eflag & ~EF_ARC_MACH_MSK) | cpu_flags; |
872 | mach_selection_mode = sel; | |
24740d83 AB |
873 | } |
874 | ||
886a2506 NC |
875 | /* Here ends all the ARCompact extension instruction assembling |
876 | stuff. */ | |
252b5132 | 877 | |
886a2506 NC |
878 | static void |
879 | arc_extra_reloc (int r_type) | |
ea1562b3 | 880 | { |
886a2506 NC |
881 | char *sym_name, c; |
882 | symbolS *sym, *lab = NULL; | |
883 | ||
884 | if (*input_line_pointer == '@') | |
885 | input_line_pointer++; | |
886 | c = get_symbol_name (&sym_name); | |
887 | sym = symbol_find_or_make (sym_name); | |
888 | restore_line_pointer (c); | |
889 | if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD) | |
890 | { | |
891 | ++input_line_pointer; | |
892 | char *lab_name; | |
893 | c = get_symbol_name (&lab_name); | |
894 | lab = symbol_find_or_make (lab_name); | |
895 | restore_line_pointer (c); | |
896 | } | |
841fdfcd CZ |
897 | |
898 | /* These relocations exist as a mechanism for the compiler to tell the | |
899 | linker how to patch the code if the tls model is optimised. However, | |
900 | the relocation itself does not require any space within the assembler | |
901 | fragment, and so we pass a size of 0. | |
902 | ||
903 | The lines that generate these relocations look like this: | |
904 | ||
905 | .tls_gd_ld @.tdata`bl __tls_get_addr@plt | |
906 | ||
907 | The '.tls_gd_ld @.tdata' is processed first and generates the | |
908 | additional relocation, while the 'bl __tls_get_addr@plt' is processed | |
909 | second and generates the additional branch. | |
910 | ||
911 | It is possible that the additional relocation generated by the | |
912 | '.tls_gd_ld @.tdata' will be attached at the very end of one fragment, | |
913 | while the 'bl __tls_get_addr@plt' will be generated as the first thing | |
914 | in the next fragment. This will be fine; both relocations will still | |
915 | appear to be at the same address in the generated object file. | |
916 | However, this only works as the additional relocation is generated | |
917 | with size of 0 bytes. */ | |
886a2506 NC |
918 | fixS *fixP |
919 | = fix_new (frag_now, /* Which frag? */ | |
920 | frag_now_fix (), /* Where in that frag? */ | |
841fdfcd | 921 | 0, /* size: 1, 2, or 4 usually. */ |
886a2506 NC |
922 | sym, /* X_add_symbol. */ |
923 | 0, /* X_add_number. */ | |
924 | FALSE, /* TRUE if PC-relative relocation. */ | |
925 | r_type /* Relocation type. */); | |
926 | fixP->fx_subsy = lab; | |
927 | } | |
252b5132 | 928 | |
886a2506 NC |
929 | static symbolS * |
930 | arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED, | |
931 | symbolS *symbolP, addressT size) | |
932 | { | |
933 | addressT align = 0; | |
934 | SKIP_WHITESPACE (); | |
252b5132 | 935 | |
886a2506 NC |
936 | if (*input_line_pointer == ',') |
937 | { | |
938 | align = parse_align (1); | |
252b5132 | 939 | |
886a2506 NC |
940 | if (align == (addressT) -1) |
941 | return NULL; | |
942 | } | |
943 | else | |
944 | { | |
945 | if (size >= 8) | |
946 | align = 3; | |
947 | else if (size >= 4) | |
948 | align = 2; | |
949 | else if (size >= 2) | |
950 | align = 1; | |
951 | else | |
952 | align = 0; | |
953 | } | |
252b5132 | 954 | |
886a2506 NC |
955 | bss_alloc (symbolP, size, align); |
956 | S_CLEAR_EXTERNAL (symbolP); | |
ea1562b3 | 957 | |
886a2506 NC |
958 | return symbolP; |
959 | } | |
ea1562b3 | 960 | |
886a2506 NC |
961 | static void |
962 | arc_lcomm (int ignore) | |
963 | { | |
964 | symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal); | |
ea1562b3 | 965 | |
886a2506 NC |
966 | if (symbolP) |
967 | symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; | |
968 | } | |
ea1562b3 | 969 | |
886a2506 | 970 | /* Select the cpu we're assembling for. */ |
ea1562b3 | 971 | |
886a2506 NC |
972 | static void |
973 | arc_option (int ignore ATTRIBUTE_UNUSED) | |
252b5132 | 974 | { |
886a2506 NC |
975 | char c; |
976 | char *cpu; | |
bb65a718 | 977 | const char *cpu_name; |
252b5132 | 978 | |
886a2506 | 979 | c = get_symbol_name (&cpu); |
252b5132 | 980 | |
bb65a718 AB |
981 | if ((!strcmp ("ARC600", cpu)) |
982 | || (!strcmp ("ARC601", cpu)) | |
983 | || (!strcmp ("A6", cpu))) | |
984 | cpu_name = "arc600"; | |
985 | else if ((!strcmp ("ARC700", cpu)) | |
986 | || (!strcmp ("A7", cpu))) | |
987 | cpu_name = "arc700"; | |
988 | else if (!strcmp ("EM", cpu)) | |
989 | cpu_name = "arcem"; | |
990 | else if (!strcmp ("HS", cpu)) | |
991 | cpu_name = "archs"; | |
992 | else if (!strcmp ("NPS400", cpu)) | |
993 | cpu_name = "nps400"; | |
994 | else | |
995 | cpu_name = NULL; | |
886a2506 | 996 | |
bb65a718 AB |
997 | if (cpu_name != NULL) |
998 | arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE); | |
999 | else | |
1000 | as_fatal (_("invalid architecture `%s' in .cpu directive"), cpu); | |
24b368f8 | 1001 | |
bb65a718 AB |
1002 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach)) |
1003 | as_fatal (_("could not set architecture and machine")); | |
1adc8a9a | 1004 | |
bb65a718 AB |
1005 | /* Set elf header flags. */ |
1006 | bfd_set_private_flags (stdoutput, selected_cpu.eflags); | |
886a2506 | 1007 | |
24b368f8 | 1008 | restore_line_pointer (c); |
886a2506 | 1009 | demand_empty_rest_of_line (); |
ea1562b3 | 1010 | } |
252b5132 | 1011 | |
886a2506 NC |
1012 | /* Smartly print an expression. */ |
1013 | ||
ea1562b3 | 1014 | static void |
886a2506 | 1015 | debug_exp (expressionS *t) |
ea1562b3 | 1016 | { |
886a2506 NC |
1017 | const char *name ATTRIBUTE_UNUSED; |
1018 | const char *namemd ATTRIBUTE_UNUSED; | |
252b5132 | 1019 | |
886a2506 | 1020 | pr_debug ("debug_exp: "); |
252b5132 | 1021 | |
886a2506 | 1022 | switch (t->X_op) |
252b5132 | 1023 | { |
886a2506 NC |
1024 | default: name = "unknown"; break; |
1025 | case O_illegal: name = "O_illegal"; break; | |
1026 | case O_absent: name = "O_absent"; break; | |
1027 | case O_constant: name = "O_constant"; break; | |
1028 | case O_symbol: name = "O_symbol"; break; | |
1029 | case O_symbol_rva: name = "O_symbol_rva"; break; | |
1030 | case O_register: name = "O_register"; break; | |
1031 | case O_big: name = "O_big"; break; | |
1032 | case O_uminus: name = "O_uminus"; break; | |
1033 | case O_bit_not: name = "O_bit_not"; break; | |
1034 | case O_logical_not: name = "O_logical_not"; break; | |
1035 | case O_multiply: name = "O_multiply"; break; | |
1036 | case O_divide: name = "O_divide"; break; | |
1037 | case O_modulus: name = "O_modulus"; break; | |
1038 | case O_left_shift: name = "O_left_shift"; break; | |
1039 | case O_right_shift: name = "O_right_shift"; break; | |
1040 | case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break; | |
1041 | case O_bit_or_not: name = "O_bit_or_not"; break; | |
1042 | case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break; | |
1043 | case O_bit_and: name = "O_bit_and"; break; | |
1044 | case O_add: name = "O_add"; break; | |
1045 | case O_subtract: name = "O_subtract"; break; | |
1046 | case O_eq: name = "O_eq"; break; | |
1047 | case O_ne: name = "O_ne"; break; | |
1048 | case O_lt: name = "O_lt"; break; | |
1049 | case O_le: name = "O_le"; break; | |
1050 | case O_ge: name = "O_ge"; break; | |
1051 | case O_gt: name = "O_gt"; break; | |
1052 | case O_logical_and: name = "O_logical_and"; break; | |
1053 | case O_logical_or: name = "O_logical_or"; break; | |
1054 | case O_index: name = "O_index"; break; | |
1055 | case O_bracket: name = "O_bracket"; break; | |
db18dbab GM |
1056 | case O_colon: name = "O_colon"; break; |
1057 | case O_addrtype: name = "O_addrtype"; break; | |
ea1562b3 | 1058 | } |
252b5132 | 1059 | |
886a2506 | 1060 | switch (t->X_md) |
ea1562b3 | 1061 | { |
886a2506 NC |
1062 | default: namemd = "unknown"; break; |
1063 | case O_gotoff: namemd = "O_gotoff"; break; | |
1064 | case O_gotpc: namemd = "O_gotpc"; break; | |
1065 | case O_plt: namemd = "O_plt"; break; | |
1066 | case O_sda: namemd = "O_sda"; break; | |
1067 | case O_pcl: namemd = "O_pcl"; break; | |
1068 | case O_tlsgd: namemd = "O_tlsgd"; break; | |
1069 | case O_tlsie: namemd = "O_tlsie"; break; | |
1070 | case O_tpoff9: namemd = "O_tpoff9"; break; | |
1071 | case O_tpoff: namemd = "O_tpoff"; break; | |
1072 | case O_dtpoff9: namemd = "O_dtpoff9"; break; | |
1073 | case O_dtpoff: namemd = "O_dtpoff"; break; | |
ea1562b3 | 1074 | } |
252b5132 | 1075 | |
886a2506 NC |
1076 | pr_debug ("%s (%s, %s, %d, %s)", name, |
1077 | (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--", | |
1078 | (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--", | |
1079 | (int) t->X_add_number, | |
1080 | (t->X_md) ? namemd : "--"); | |
1081 | pr_debug ("\n"); | |
1082 | fflush (stderr); | |
1083 | } | |
252b5132 | 1084 | |
886a2506 NC |
1085 | /* Parse the arguments to an opcode. */ |
1086 | ||
1087 | static int | |
1088 | tokenize_arguments (char *str, | |
1089 | expressionS *tok, | |
1090 | int ntok) | |
1091 | { | |
1092 | char *old_input_line_pointer; | |
1093 | bfd_boolean saw_comma = FALSE; | |
1094 | bfd_boolean saw_arg = FALSE; | |
1095 | int brk_lvl = 0; | |
1096 | int num_args = 0; | |
886a2506 NC |
1097 | int i; |
1098 | size_t len; | |
1099 | const struct arc_reloc_op_tag *r; | |
1100 | expressionS tmpE; | |
6f4b1afc | 1101 | char *reloc_name, c; |
886a2506 NC |
1102 | |
1103 | memset (tok, 0, sizeof (*tok) * ntok); | |
1104 | ||
1105 | /* Save and restore input_line_pointer around this function. */ | |
1106 | old_input_line_pointer = input_line_pointer; | |
1107 | input_line_pointer = str; | |
ea1562b3 | 1108 | |
886a2506 | 1109 | while (*input_line_pointer) |
ea1562b3 NC |
1110 | { |
1111 | SKIP_WHITESPACE (); | |
886a2506 | 1112 | switch (*input_line_pointer) |
252b5132 | 1113 | { |
886a2506 NC |
1114 | case '\0': |
1115 | goto fini; | |
1116 | ||
1117 | case ',': | |
1118 | input_line_pointer++; | |
1119 | if (saw_comma || !saw_arg) | |
1120 | goto err; | |
1121 | saw_comma = TRUE; | |
1122 | break; | |
252b5132 | 1123 | |
886a2506 NC |
1124 | case '}': |
1125 | case ']': | |
1126 | ++input_line_pointer; | |
1127 | --brk_lvl; | |
3b889a78 | 1128 | if (!saw_arg || num_args == ntok) |
886a2506 NC |
1129 | goto err; |
1130 | tok->X_op = O_bracket; | |
1131 | ++tok; | |
1132 | ++num_args; | |
1133 | break; | |
ea1562b3 | 1134 | |
886a2506 NC |
1135 | case '{': |
1136 | case '[': | |
1137 | input_line_pointer++; | |
3b889a78 | 1138 | if (brk_lvl || num_args == ntok) |
886a2506 NC |
1139 | goto err; |
1140 | ++brk_lvl; | |
1141 | tok->X_op = O_bracket; | |
1142 | ++tok; | |
1143 | ++num_args; | |
1144 | break; | |
1145 | ||
db18dbab GM |
1146 | case ':': |
1147 | input_line_pointer++; | |
1148 | if (!saw_arg || num_args == ntok) | |
1149 | goto err; | |
1150 | tok->X_op = O_colon; | |
1151 | saw_arg = FALSE; | |
1152 | ++tok; | |
1153 | ++num_args; | |
1154 | break; | |
1155 | ||
886a2506 NC |
1156 | case '@': |
1157 | /* We have labels, function names and relocations, all | |
1158 | starting with @ symbol. Sort them out. */ | |
3b889a78 | 1159 | if ((saw_arg && !saw_comma) || num_args == ntok) |
886a2506 NC |
1160 | goto err; |
1161 | ||
1162 | /* Parse @label. */ | |
1163 | tok->X_op = O_symbol; | |
1164 | tok->X_md = O_absent; | |
1165 | expression (tok); | |
1166 | if (*input_line_pointer != '@') | |
1167 | goto normalsymbol; /* This is not a relocation. */ | |
1168 | ||
6f4b1afc CM |
1169 | relocationsym: |
1170 | ||
886a2506 NC |
1171 | /* A relocation opernad has the following form |
1172 | @identifier@relocation_type. The identifier is already | |
1173 | in tok! */ | |
1174 | if (tok->X_op != O_symbol) | |
ea1562b3 | 1175 | { |
886a2506 NC |
1176 | as_bad (_("No valid label relocation operand")); |
1177 | goto err; | |
252b5132 | 1178 | } |
886a2506 NC |
1179 | |
1180 | /* Parse @relocation_type. */ | |
6f4b1afc CM |
1181 | input_line_pointer++; |
1182 | c = get_symbol_name (&reloc_name); | |
1183 | len = input_line_pointer - reloc_name; | |
1184 | if (len == 0) | |
252b5132 | 1185 | { |
886a2506 NC |
1186 | as_bad (_("No relocation operand")); |
1187 | goto err; | |
252b5132 | 1188 | } |
252b5132 | 1189 | |
886a2506 NC |
1190 | /* Go through known relocation and try to find a match. */ |
1191 | r = &arc_reloc_op[0]; | |
1192 | for (i = arc_num_reloc_op - 1; i >= 0; i--, r++) | |
6f4b1afc CM |
1193 | if (len == r->length |
1194 | && memcmp (reloc_name, r->name, len) == 0) | |
886a2506 | 1195 | break; |
886a2506 | 1196 | if (i < 0) |
252b5132 | 1197 | { |
6f4b1afc | 1198 | as_bad (_("Unknown relocation operand: @%s"), reloc_name); |
886a2506 NC |
1199 | goto err; |
1200 | } | |
1201 | ||
6f4b1afc CM |
1202 | *input_line_pointer = c; |
1203 | SKIP_WHITESPACE_AFTER_NAME (); | |
886a2506 NC |
1204 | /* Extra check for TLS: base. */ |
1205 | if (*input_line_pointer == '@') | |
1206 | { | |
1207 | symbolS *base; | |
1208 | if (tok->X_op_symbol != NULL | |
1209 | || tok->X_op != O_symbol) | |
252b5132 | 1210 | { |
6f4b1afc CM |
1211 | as_bad (_("Unable to parse TLS base: %s"), |
1212 | input_line_pointer); | |
886a2506 | 1213 | goto err; |
252b5132 | 1214 | } |
886a2506 NC |
1215 | input_line_pointer++; |
1216 | char *sym_name; | |
6f4b1afc | 1217 | c = get_symbol_name (&sym_name); |
886a2506 NC |
1218 | base = symbol_find_or_make (sym_name); |
1219 | tok->X_op = O_subtract; | |
1220 | tok->X_op_symbol = base; | |
1221 | restore_line_pointer (c); | |
6f4b1afc CM |
1222 | tmpE.X_add_number = 0; |
1223 | } | |
32348c58 | 1224 | if ((*input_line_pointer != '+') |
6f4b1afc CM |
1225 | && (*input_line_pointer != '-')) |
1226 | { | |
1227 | tmpE.X_add_number = 0; | |
ea1562b3 | 1228 | } |
6f4b1afc CM |
1229 | else |
1230 | { | |
1231 | /* Parse the constant of a complex relocation expression | |
1232 | like @identifier@reloc +/- const. */ | |
1233 | if (! r->complex_expr) | |
1234 | { | |
1235 | as_bad (_("@%s is not a complex relocation."), r->name); | |
1236 | goto err; | |
1237 | } | |
1238 | expression (&tmpE); | |
1239 | if (tmpE.X_op != O_constant) | |
1240 | { | |
1241 | as_bad (_("Bad expression: @%s + %s."), | |
1242 | r->name, input_line_pointer); | |
1243 | goto err; | |
1244 | } | |
1245 | } | |
1246 | ||
1247 | tok->X_md = r->op; | |
1248 | tok->X_add_number = tmpE.X_add_number; | |
1e07b820 | 1249 | |
886a2506 | 1250 | debug_exp (tok); |
ea1562b3 | 1251 | |
886a2506 NC |
1252 | saw_comma = FALSE; |
1253 | saw_arg = TRUE; | |
1254 | tok++; | |
1255 | num_args++; | |
1256 | break; | |
252b5132 | 1257 | |
886a2506 NC |
1258 | case '%': |
1259 | /* Can be a register. */ | |
1260 | ++input_line_pointer; | |
1261 | /* Fall through. */ | |
1262 | default: | |
252b5132 | 1263 | |
3b889a78 | 1264 | if ((saw_arg && !saw_comma) || num_args == ntok) |
886a2506 | 1265 | goto err; |
252b5132 | 1266 | |
886a2506 | 1267 | tok->X_op = O_absent; |
6f4b1afc | 1268 | tok->X_md = O_absent; |
886a2506 | 1269 | expression (tok); |
252b5132 | 1270 | |
6f4b1afc CM |
1271 | /* Legacy: There are cases when we have |
1272 | identifier@relocation_type, if it is the case parse the | |
1273 | relocation type as well. */ | |
1274 | if (*input_line_pointer == '@') | |
1275 | goto relocationsym; | |
1276 | ||
886a2506 NC |
1277 | normalsymbol: |
1278 | debug_exp (tok); | |
252b5132 | 1279 | |
3b889a78 AB |
1280 | if (tok->X_op == O_illegal |
1281 | || tok->X_op == O_absent | |
1282 | || num_args == ntok) | |
886a2506 | 1283 | goto err; |
252b5132 | 1284 | |
886a2506 NC |
1285 | saw_comma = FALSE; |
1286 | saw_arg = TRUE; | |
1287 | tok++; | |
1288 | num_args++; | |
1289 | break; | |
1290 | } | |
ea1562b3 | 1291 | } |
252b5132 | 1292 | |
886a2506 NC |
1293 | fini: |
1294 | if (saw_comma || brk_lvl) | |
1295 | goto err; | |
1296 | input_line_pointer = old_input_line_pointer; | |
252b5132 | 1297 | |
886a2506 | 1298 | return num_args; |
252b5132 | 1299 | |
886a2506 NC |
1300 | err: |
1301 | if (brk_lvl) | |
1302 | as_bad (_("Brackets in operand field incorrect")); | |
1303 | else if (saw_comma) | |
1304 | as_bad (_("extra comma")); | |
1305 | else if (!saw_arg) | |
1306 | as_bad (_("missing argument")); | |
1307 | else | |
1308 | as_bad (_("missing comma or colon")); | |
1309 | input_line_pointer = old_input_line_pointer; | |
1310 | return -1; | |
252b5132 | 1311 | } |
ea1562b3 | 1312 | |
886a2506 NC |
1313 | /* Parse the flags to a structure. */ |
1314 | ||
1315 | static int | |
1316 | tokenize_flags (const char *str, | |
1317 | struct arc_flags flags[], | |
1318 | int nflg) | |
252b5132 | 1319 | { |
886a2506 NC |
1320 | char *old_input_line_pointer; |
1321 | bfd_boolean saw_flg = FALSE; | |
1322 | bfd_boolean saw_dot = FALSE; | |
1323 | int num_flags = 0; | |
1324 | size_t flgnamelen; | |
252b5132 | 1325 | |
886a2506 | 1326 | memset (flags, 0, sizeof (*flags) * nflg); |
0d2bcfaf | 1327 | |
886a2506 NC |
1328 | /* Save and restore input_line_pointer around this function. */ |
1329 | old_input_line_pointer = input_line_pointer; | |
1330 | input_line_pointer = (char *) str; | |
0d2bcfaf | 1331 | |
886a2506 NC |
1332 | while (*input_line_pointer) |
1333 | { | |
1334 | switch (*input_line_pointer) | |
1335 | { | |
1336 | case ' ': | |
1337 | case '\0': | |
1338 | goto fini; | |
1339 | ||
1340 | case '.': | |
1341 | input_line_pointer++; | |
1342 | if (saw_dot) | |
1343 | goto err; | |
1344 | saw_dot = TRUE; | |
1345 | saw_flg = FALSE; | |
1346 | break; | |
ea1562b3 | 1347 | |
886a2506 NC |
1348 | default: |
1349 | if (saw_flg && !saw_dot) | |
1350 | goto err; | |
0d2bcfaf | 1351 | |
886a2506 NC |
1352 | if (num_flags >= nflg) |
1353 | goto err; | |
0d2bcfaf | 1354 | |
692166c2 AB |
1355 | flgnamelen = strspn (input_line_pointer, |
1356 | "abcdefghijklmnopqrstuvwxyz0123456789"); | |
83cda17b | 1357 | if (flgnamelen > MAX_FLAG_NAME_LENGTH) |
886a2506 | 1358 | goto err; |
0d2bcfaf | 1359 | |
886a2506 | 1360 | memcpy (flags->name, input_line_pointer, flgnamelen); |
0d2bcfaf | 1361 | |
886a2506 NC |
1362 | input_line_pointer += flgnamelen; |
1363 | flags++; | |
1364 | saw_dot = FALSE; | |
1365 | saw_flg = TRUE; | |
1366 | num_flags++; | |
1367 | break; | |
1e07b820 | 1368 | } |
0d2bcfaf NC |
1369 | } |
1370 | ||
886a2506 NC |
1371 | fini: |
1372 | input_line_pointer = old_input_line_pointer; | |
1373 | return num_flags; | |
0d2bcfaf | 1374 | |
886a2506 NC |
1375 | err: |
1376 | if (saw_dot) | |
1377 | as_bad (_("extra dot")); | |
1378 | else if (!saw_flg) | |
1379 | as_bad (_("unrecognized flag")); | |
1380 | else | |
1381 | as_bad (_("failed to parse flags")); | |
1382 | input_line_pointer = old_input_line_pointer; | |
1383 | return -1; | |
1384 | } | |
0d2bcfaf | 1385 | |
4670103e | 1386 | /* Apply the fixups in order. */ |
0d2bcfaf | 1387 | |
4670103e CZ |
1388 | static void |
1389 | apply_fixups (struct arc_insn *insn, fragS *fragP, int fix) | |
886a2506 | 1390 | { |
4670103e | 1391 | int i; |
0d2bcfaf | 1392 | |
4670103e | 1393 | for (i = 0; i < insn->nfixups; i++) |
252b5132 | 1394 | { |
4670103e CZ |
1395 | struct arc_fixup *fixup = &insn->fixups[i]; |
1396 | int size, pcrel, offset = 0; | |
0d2bcfaf | 1397 | |
4670103e CZ |
1398 | /* FIXME! the reloc size is wrong in the BFD file. |
1399 | When it is fixed please delete me. */ | |
91fdca6f | 1400 | size = ((insn->len == 2) && !fixup->islong) ? 2 : 4; |
0d2bcfaf | 1401 | |
4670103e | 1402 | if (fixup->islong) |
91fdca6f | 1403 | offset = insn->len; |
252b5132 | 1404 | |
4670103e CZ |
1405 | /* Some fixups are only used internally, thus no howto. */ |
1406 | if ((int) fixup->reloc == 0) | |
1407 | as_fatal (_("Unhandled reloc type")); | |
886a2506 | 1408 | |
4670103e CZ |
1409 | if ((int) fixup->reloc < 0) |
1410 | { | |
1411 | /* FIXME! the reloc size is wrong in the BFD file. | |
1412 | When it is fixed please enable me. | |
91fdca6f | 1413 | size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */ |
4670103e CZ |
1414 | pcrel = fixup->pcrel; |
1415 | } | |
1416 | else | |
1417 | { | |
1418 | reloc_howto_type *reloc_howto = | |
1419 | bfd_reloc_type_lookup (stdoutput, | |
1420 | (bfd_reloc_code_real_type) fixup->reloc); | |
1421 | gas_assert (reloc_howto); | |
0d2bcfaf | 1422 | |
4670103e CZ |
1423 | /* FIXME! the reloc size is wrong in the BFD file. |
1424 | When it is fixed please enable me. | |
1425 | size = bfd_get_reloc_size (reloc_howto); */ | |
1426 | pcrel = reloc_howto->pc_relative; | |
1427 | } | |
0d2bcfaf | 1428 | |
4670103e CZ |
1429 | pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \ |
1430 | offset %d + %d\n", | |
1431 | fragP->fr_file, fragP->fr_line, | |
1432 | (fixup->reloc < 0) ? "Internal" : | |
1433 | bfd_get_reloc_code_name (fixup->reloc), | |
1434 | pcrel ? "Y" : "N", | |
1435 | size, fix, offset); | |
1436 | fix_new_exp (fragP, fix + offset, | |
1437 | size, &fixup->exp, pcrel, fixup->reloc); | |
0d2bcfaf | 1438 | |
4670103e CZ |
1439 | /* Check for ZOLs, and update symbol info if any. */ |
1440 | if (LP_INSN (insn->insn)) | |
886a2506 | 1441 | { |
4670103e CZ |
1442 | gas_assert (fixup->exp.X_add_symbol); |
1443 | ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL); | |
886a2506 NC |
1444 | } |
1445 | } | |
252b5132 RH |
1446 | } |
1447 | ||
4670103e | 1448 | /* Actually output an instruction with its fixup. */ |
886a2506 | 1449 | |
4670103e CZ |
1450 | static void |
1451 | emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax) | |
252b5132 | 1452 | { |
4670103e | 1453 | char *f = where; |
91fdca6f | 1454 | size_t total_len; |
252b5132 | 1455 | |
bdfe53e3 AB |
1456 | pr_debug ("Emit insn : 0x%llx\n", insn->insn); |
1457 | pr_debug ("\tLength : 0x%d\n", insn->len); | |
4670103e | 1458 | pr_debug ("\tLong imm: 0x%lx\n", insn->limm); |
0d2bcfaf | 1459 | |
4670103e | 1460 | /* Write out the instruction. */ |
91fdca6f GM |
1461 | total_len = insn->len + (insn->has_limm ? 4 : 0); |
1462 | if (!relax) | |
1463 | f = frag_more (total_len); | |
1464 | ||
1465 | md_number_to_chars_midend(f, insn->insn, insn->len); | |
1466 | ||
1467 | if (insn->has_limm) | |
1468 | md_number_to_chars_midend (f + insn->len, insn->limm, 4); | |
1469 | dwarf2_emit_insn (total_len); | |
252b5132 | 1470 | |
4670103e CZ |
1471 | if (!relax) |
1472 | apply_fixups (insn, frag_now, (f - frag_now->fr_literal)); | |
1473 | } | |
252b5132 | 1474 | |
4670103e CZ |
1475 | static void |
1476 | emit_insn1 (struct arc_insn *insn) | |
1477 | { | |
1478 | /* How frag_var's args are currently configured: | |
1479 | - rs_machine_dependent, to dictate it's a relaxation frag. | |
1480 | - FRAG_MAX_GROWTH, maximum size of instruction | |
1481 | - 0, variable size that might grow...unused by generic relaxation. | |
1482 | - frag_now->fr_subtype, fr_subtype starting value, set previously. | |
1483 | - s, opand expression. | |
1484 | - 0, offset but it's unused. | |
1485 | - 0, opcode but it's unused. */ | |
1486 | symbolS *s = make_expr_symbol (&insn->fixups[0].exp); | |
1487 | frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel; | |
1488 | ||
1489 | if (frag_room () < FRAG_MAX_GROWTH) | |
1490 | { | |
1491 | /* Handle differently when frag literal memory is exhausted. | |
1492 | This is used because when there's not enough memory left in | |
1493 | the current frag, a new frag is created and the information | |
1494 | we put into frag_now->tc_frag_data is disregarded. */ | |
252b5132 | 1495 | |
4670103e CZ |
1496 | struct arc_relax_type relax_info_copy; |
1497 | relax_substateT subtype = frag_now->fr_subtype; | |
252b5132 | 1498 | |
4670103e CZ |
1499 | memcpy (&relax_info_copy, &frag_now->tc_frag_data, |
1500 | sizeof (struct arc_relax_type)); | |
0d2bcfaf | 1501 | |
4670103e CZ |
1502 | frag_wane (frag_now); |
1503 | frag_grow (FRAG_MAX_GROWTH); | |
0d2bcfaf | 1504 | |
4670103e CZ |
1505 | memcpy (&frag_now->tc_frag_data, &relax_info_copy, |
1506 | sizeof (struct arc_relax_type)); | |
252b5132 | 1507 | |
4670103e CZ |
1508 | frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0, |
1509 | subtype, s, 0, 0); | |
1510 | } | |
1511 | else | |
1512 | frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0, | |
1513 | frag_now->fr_subtype, s, 0, 0); | |
1514 | } | |
252b5132 | 1515 | |
4670103e CZ |
1516 | static void |
1517 | emit_insn (struct arc_insn *insn) | |
252b5132 | 1518 | { |
4670103e CZ |
1519 | if (insn->relax) |
1520 | emit_insn1 (insn); | |
252b5132 | 1521 | else |
4670103e | 1522 | emit_insn0 (insn, NULL, FALSE); |
252b5132 RH |
1523 | } |
1524 | ||
4670103e | 1525 | /* Check whether a symbol involves a register. */ |
252b5132 | 1526 | |
4670103e CZ |
1527 | static bfd_boolean |
1528 | contains_register (symbolS *sym) | |
252b5132 | 1529 | { |
4670103e CZ |
1530 | if (sym) |
1531 | { | |
1532 | expressionS *ex = symbol_get_value_expression (sym); | |
252b5132 | 1533 | |
4670103e CZ |
1534 | return ((O_register == ex->X_op) |
1535 | && !contains_register (ex->X_add_symbol) | |
1536 | && !contains_register (ex->X_op_symbol)); | |
1537 | } | |
1538 | ||
1539 | return FALSE; | |
252b5132 RH |
1540 | } |
1541 | ||
4670103e | 1542 | /* Returns the register number within a symbol. */ |
252b5132 | 1543 | |
4670103e CZ |
1544 | static int |
1545 | get_register (symbolS *sym) | |
252b5132 | 1546 | { |
4670103e CZ |
1547 | if (!contains_register (sym)) |
1548 | return -1; | |
0d2bcfaf | 1549 | |
4670103e CZ |
1550 | expressionS *ex = symbol_get_value_expression (sym); |
1551 | return regno (ex->X_add_number); | |
1552 | } | |
252b5132 | 1553 | |
4670103e CZ |
1554 | /* Return true if a RELOC is generic. A generic reloc is PC-rel of a |
1555 | simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */ | |
f17c130b | 1556 | |
4670103e CZ |
1557 | static bfd_boolean |
1558 | generic_reloc_p (extended_bfd_reloc_code_real_type reloc) | |
1559 | { | |
1560 | if (!reloc) | |
1561 | return FALSE; | |
886a2506 | 1562 | |
4670103e CZ |
1563 | switch (reloc) |
1564 | { | |
1565 | case BFD_RELOC_ARC_SDA_LDST: | |
1566 | case BFD_RELOC_ARC_SDA_LDST1: | |
1567 | case BFD_RELOC_ARC_SDA_LDST2: | |
1568 | case BFD_RELOC_ARC_SDA16_LD: | |
1569 | case BFD_RELOC_ARC_SDA16_LD1: | |
1570 | case BFD_RELOC_ARC_SDA16_LD2: | |
1571 | case BFD_RELOC_ARC_SDA16_ST2: | |
1572 | case BFD_RELOC_ARC_SDA32_ME: | |
1573 | return FALSE; | |
1574 | default: | |
1575 | return TRUE; | |
f17c130b | 1576 | } |
252b5132 RH |
1577 | } |
1578 | ||
4670103e | 1579 | /* Allocates a tok entry. */ |
252b5132 | 1580 | |
4670103e CZ |
1581 | static int |
1582 | allocate_tok (expressionS *tok, int ntok, int cidx) | |
252b5132 | 1583 | { |
4670103e CZ |
1584 | if (ntok > MAX_INSN_ARGS - 2) |
1585 | return 0; /* No space left. */ | |
252b5132 | 1586 | |
4670103e CZ |
1587 | if (cidx > ntok) |
1588 | return 0; /* Incorect args. */ | |
252b5132 | 1589 | |
4670103e | 1590 | memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok)); |
252b5132 | 1591 | |
4670103e CZ |
1592 | if (cidx == ntok) |
1593 | return 1; /* Success. */ | |
1594 | return allocate_tok (tok, ntok - 1, cidx); | |
1595 | } | |
886a2506 | 1596 | |
8ddf6b2a CZ |
1597 | /* Check if an particular ARC feature is enabled. */ |
1598 | ||
1599 | static bfd_boolean | |
1600 | check_cpu_feature (insn_subclass_t sc) | |
1601 | { | |
bb65a718 | 1602 | if (is_code_density_p (sc) && !(selected_cpu.features & ARC_CD)) |
8ddf6b2a CZ |
1603 | return FALSE; |
1604 | ||
bb65a718 | 1605 | if (is_spfp_p (sc) && !(selected_cpu.features & ARC_SPFP)) |
8ddf6b2a CZ |
1606 | return FALSE; |
1607 | ||
bb65a718 | 1608 | if (is_dpfp_p (sc) && !(selected_cpu.features & ARC_DPFP)) |
8ddf6b2a CZ |
1609 | return FALSE; |
1610 | ||
bb65a718 | 1611 | if (is_fpuda_p (sc) && !(selected_cpu.features & ARC_FPUDA)) |
bdd582db GM |
1612 | return FALSE; |
1613 | ||
bb65a718 | 1614 | if (is_nps400_p (sc) && !(selected_cpu.features & ARC_NPS400)) |
8ddf6b2a CZ |
1615 | return FALSE; |
1616 | ||
1617 | return TRUE; | |
1618 | } | |
1619 | ||
4eb6f892 AB |
1620 | /* Parse the flags described by FIRST_PFLAG and NFLGS against the flag |
1621 | operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG | |
1622 | array and returns TRUE if the flag operands all match, otherwise, | |
1623 | returns FALSE, in which case the FIRST_PFLAG array may have been | |
1624 | modified. */ | |
1625 | ||
1626 | static bfd_boolean | |
1627 | parse_opcode_flags (const struct arc_opcode *opcode, | |
1628 | int nflgs, | |
1629 | struct arc_flags *first_pflag) | |
1630 | { | |
1631 | int lnflg, i; | |
1632 | const unsigned char *flgidx; | |
1633 | ||
1634 | lnflg = nflgs; | |
1635 | for (i = 0; i < nflgs; i++) | |
1636 | first_pflag[i].flgp = NULL; | |
1637 | ||
1638 | /* Check the flags. Iterate over the valid flag classes. */ | |
1639 | for (flgidx = opcode->flags; *flgidx; ++flgidx) | |
1640 | { | |
1641 | /* Get a valid flag class. */ | |
1642 | const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx]; | |
1643 | const unsigned *flgopridx; | |
1644 | int cl_matches = 0; | |
1645 | struct arc_flags *pflag = NULL; | |
1646 | ||
1647 | /* Check for extension conditional codes. */ | |
1648 | if (ext_condcode.arc_ext_condcode | |
1649 | && cl_flags->flag_class & F_CLASS_EXTEND) | |
1650 | { | |
1651 | struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode; | |
1652 | while (pf->name) | |
1653 | { | |
1654 | pflag = first_pflag; | |
1655 | for (i = 0; i < nflgs; i++, pflag++) | |
1656 | { | |
1657 | if (!strcmp (pf->name, pflag->name)) | |
1658 | { | |
1659 | if (pflag->flgp != NULL) | |
1660 | return FALSE; | |
1661 | /* Found it. */ | |
1662 | cl_matches++; | |
1663 | pflag->flgp = pf; | |
1664 | lnflg--; | |
1665 | break; | |
1666 | } | |
1667 | } | |
1668 | pf++; | |
1669 | } | |
1670 | } | |
1671 | ||
1672 | for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx) | |
1673 | { | |
1674 | const struct arc_flag_operand *flg_operand; | |
1675 | ||
1676 | pflag = first_pflag; | |
1677 | flg_operand = &arc_flag_operands[*flgopridx]; | |
1678 | for (i = 0; i < nflgs; i++, pflag++) | |
1679 | { | |
1680 | /* Match against the parsed flags. */ | |
1681 | if (!strcmp (flg_operand->name, pflag->name)) | |
1682 | { | |
1683 | if (pflag->flgp != NULL) | |
1684 | return FALSE; | |
1685 | cl_matches++; | |
1686 | pflag->flgp = flg_operand; | |
1687 | lnflg--; | |
1688 | break; /* goto next flag class and parsed flag. */ | |
1689 | } | |
1690 | } | |
1691 | } | |
1692 | ||
1693 | if ((cl_flags->flag_class & F_CLASS_REQUIRED) && cl_matches == 0) | |
1694 | return FALSE; | |
1695 | if ((cl_flags->flag_class & F_CLASS_OPTIONAL) && cl_matches > 1) | |
1696 | return FALSE; | |
1697 | } | |
1698 | ||
1699 | /* Did I check all the parsed flags? */ | |
1700 | return lnflg ? FALSE : TRUE; | |
1701 | } | |
1702 | ||
1703 | ||
4670103e CZ |
1704 | /* Search forward through all variants of an opcode looking for a |
1705 | syntax match. */ | |
886a2506 | 1706 | |
4670103e | 1707 | static const struct arc_opcode * |
b9b47ab7 | 1708 | find_opcode_match (const struct arc_opcode_hash_entry *entry, |
4670103e CZ |
1709 | expressionS *tok, |
1710 | int *pntok, | |
1711 | struct arc_flags *first_pflag, | |
1712 | int nflgs, | |
abe7c33b CZ |
1713 | int *pcpumatch, |
1714 | const char **errmsg) | |
4670103e | 1715 | { |
1328504b AB |
1716 | const struct arc_opcode *opcode; |
1717 | struct arc_opcode_hash_entry_iterator iter; | |
4670103e CZ |
1718 | int ntok = *pntok; |
1719 | int got_cpu_match = 0; | |
1720 | expressionS bktok[MAX_INSN_ARGS]; | |
1721 | int bkntok; | |
1722 | expressionS emptyE; | |
886a2506 | 1723 | |
1328504b | 1724 | arc_opcode_hash_entry_iterator_init (&iter); |
4670103e CZ |
1725 | memset (&emptyE, 0, sizeof (emptyE)); |
1726 | memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok)); | |
1727 | bkntok = ntok; | |
a161fe53 | 1728 | |
1328504b AB |
1729 | for (opcode = arc_opcode_hash_entry_iterator_next (entry, &iter); |
1730 | opcode != NULL; | |
1731 | opcode = arc_opcode_hash_entry_iterator_next (entry, &iter)) | |
252b5132 | 1732 | { |
4670103e | 1733 | const unsigned char *opidx; |
4eb6f892 | 1734 | int tokidx = 0; |
4670103e | 1735 | const expressionS *t = &emptyE; |
252b5132 | 1736 | |
bdfe53e3 | 1737 | pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ", |
4670103e | 1738 | frag_now->fr_file, frag_now->fr_line, opcode->opcode); |
886a2506 | 1739 | |
4670103e CZ |
1740 | /* Don't match opcodes that don't exist on this |
1741 | architecture. */ | |
bb65a718 | 1742 | if (!(opcode->cpu & selected_cpu.flags)) |
4670103e | 1743 | goto match_failed; |
886a2506 | 1744 | |
8ddf6b2a | 1745 | if (!check_cpu_feature (opcode->subclass)) |
4670103e | 1746 | goto match_failed; |
886a2506 | 1747 | |
4670103e CZ |
1748 | got_cpu_match = 1; |
1749 | pr_debug ("cpu "); | |
886a2506 | 1750 | |
4670103e CZ |
1751 | /* Check the operands. */ |
1752 | for (opidx = opcode->operands; *opidx; ++opidx) | |
252b5132 | 1753 | { |
4670103e | 1754 | const struct arc_operand *operand = &arc_operands[*opidx]; |
252b5132 | 1755 | |
4670103e | 1756 | /* Only take input from real operands. */ |
db18dbab | 1757 | if (ARC_OPERAND_IS_FAKE (operand)) |
4670103e | 1758 | continue; |
252b5132 | 1759 | |
4670103e CZ |
1760 | /* When we expect input, make sure we have it. */ |
1761 | if (tokidx >= ntok) | |
1762 | goto match_failed; | |
6f4b1afc | 1763 | |
4670103e CZ |
1764 | /* Match operand type with expression type. */ |
1765 | switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK) | |
1766 | { | |
db18dbab | 1767 | case ARC_OPERAND_ADDRTYPE: |
b437d035 | 1768 | { |
abe7c33b | 1769 | *errmsg = NULL; |
b437d035 AB |
1770 | |
1771 | /* Check to be an address type. */ | |
1772 | if (tok[tokidx].X_op != O_addrtype) | |
1773 | goto match_failed; | |
1774 | ||
1775 | /* All address type operands need to have an insert | |
1776 | method in order to check that we have the correct | |
1777 | address type. */ | |
1778 | gas_assert (operand->insert != NULL); | |
1779 | (*operand->insert) (0, tok[tokidx].X_add_number, | |
abe7c33b CZ |
1780 | errmsg); |
1781 | if (*errmsg != NULL) | |
b437d035 AB |
1782 | goto match_failed; |
1783 | } | |
db18dbab GM |
1784 | break; |
1785 | ||
4670103e CZ |
1786 | case ARC_OPERAND_IR: |
1787 | /* Check to be a register. */ | |
1788 | if ((tok[tokidx].X_op != O_register | |
1789 | || !is_ir_num (tok[tokidx].X_add_number)) | |
1790 | && !(operand->flags & ARC_OPERAND_IGNORE)) | |
1791 | goto match_failed; | |
1792 | ||
1793 | /* If expect duplicate, make sure it is duplicate. */ | |
1794 | if (operand->flags & ARC_OPERAND_DUPLICATE) | |
1795 | { | |
1796 | /* Check for duplicate. */ | |
1797 | if (t->X_op != O_register | |
1798 | || !is_ir_num (t->X_add_number) | |
1799 | || (regno (t->X_add_number) != | |
1800 | regno (tok[tokidx].X_add_number))) | |
1801 | goto match_failed; | |
1802 | } | |
1803 | ||
1804 | /* Special handling? */ | |
1805 | if (operand->insert) | |
1806 | { | |
abe7c33b | 1807 | *errmsg = NULL; |
4670103e CZ |
1808 | (*operand->insert)(0, |
1809 | regno (tok[tokidx].X_add_number), | |
abe7c33b CZ |
1810 | errmsg); |
1811 | if (*errmsg) | |
4670103e CZ |
1812 | { |
1813 | if (operand->flags & ARC_OPERAND_IGNORE) | |
1814 | { | |
1815 | /* Missing argument, create one. */ | |
1816 | if (!allocate_tok (tok, ntok - 1, tokidx)) | |
1817 | goto match_failed; | |
1818 | ||
1819 | tok[tokidx].X_op = O_absent; | |
1820 | ++ntok; | |
1821 | } | |
1822 | else | |
1823 | goto match_failed; | |
1824 | } | |
1825 | } | |
1826 | ||
1827 | t = &tok[tokidx]; | |
1828 | break; | |
1829 | ||
1830 | case ARC_OPERAND_BRAKET: | |
1831 | /* Check if bracket is also in opcode table as | |
1832 | operand. */ | |
1833 | if (tok[tokidx].X_op != O_bracket) | |
1834 | goto match_failed; | |
1835 | break; | |
1836 | ||
db18dbab GM |
1837 | case ARC_OPERAND_COLON: |
1838 | /* Check if colon is also in opcode table as operand. */ | |
1839 | if (tok[tokidx].X_op != O_colon) | |
1840 | goto match_failed; | |
1841 | break; | |
1842 | ||
4670103e CZ |
1843 | case ARC_OPERAND_LIMM: |
1844 | case ARC_OPERAND_SIGNED: | |
1845 | case ARC_OPERAND_UNSIGNED: | |
1846 | switch (tok[tokidx].X_op) | |
1847 | { | |
1848 | case O_illegal: | |
1849 | case O_absent: | |
1850 | case O_register: | |
1851 | goto match_failed; | |
1852 | ||
1853 | case O_bracket: | |
1854 | /* Got an (too) early bracket, check if it is an | |
1855 | ignored operand. N.B. This procedure works only | |
1856 | when bracket is the last operand! */ | |
1857 | if (!(operand->flags & ARC_OPERAND_IGNORE)) | |
1858 | goto match_failed; | |
1859 | /* Insert the missing operand. */ | |
1860 | if (!allocate_tok (tok, ntok - 1, tokidx)) | |
1861 | goto match_failed; | |
1862 | ||
1863 | tok[tokidx].X_op = O_absent; | |
1864 | ++ntok; | |
1865 | break; | |
1866 | ||
22b92fc4 AB |
1867 | case O_symbol: |
1868 | { | |
1869 | const char *p; | |
22b92fc4 | 1870 | const struct arc_aux_reg *auxr; |
22b92fc4 | 1871 | |
c810e0b8 | 1872 | if (opcode->insn_class != AUXREG) |
22b92fc4 AB |
1873 | goto de_fault; |
1874 | p = S_GET_NAME (tok[tokidx].X_add_symbol); | |
f36e33da CZ |
1875 | |
1876 | auxr = hash_find (arc_aux_hash, p); | |
1877 | if (auxr) | |
1878 | { | |
1879 | /* We modify the token array here, safe in the | |
1880 | knowledge, that if this was the wrong | |
1881 | choice then the original contents will be | |
1882 | restored from BKTOK. */ | |
1883 | tok[tokidx].X_op = O_constant; | |
1884 | tok[tokidx].X_add_number = auxr->address; | |
1885 | ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX); | |
1886 | } | |
22b92fc4 AB |
1887 | |
1888 | if (tok[tokidx].X_op != O_constant) | |
1889 | goto de_fault; | |
1890 | } | |
1a0670f3 | 1891 | /* Fall through. */ |
4670103e CZ |
1892 | case O_constant: |
1893 | /* Check the range. */ | |
1894 | if (operand->bits != 32 | |
1895 | && !(operand->flags & ARC_OPERAND_NCHK)) | |
1896 | { | |
1897 | offsetT min, max, val; | |
1898 | val = tok[tokidx].X_add_number; | |
1899 | ||
1900 | if (operand->flags & ARC_OPERAND_SIGNED) | |
1901 | { | |
1902 | max = (1 << (operand->bits - 1)) - 1; | |
1903 | min = -(1 << (operand->bits - 1)); | |
1904 | } | |
1905 | else | |
1906 | { | |
1907 | max = (1 << operand->bits) - 1; | |
1908 | min = 0; | |
1909 | } | |
1910 | ||
1911 | if (val < min || val > max) | |
1912 | goto match_failed; | |
1913 | ||
1914 | /* Check alignmets. */ | |
1915 | if ((operand->flags & ARC_OPERAND_ALIGNED32) | |
1916 | && (val & 0x03)) | |
1917 | goto match_failed; | |
1918 | ||
1919 | if ((operand->flags & ARC_OPERAND_ALIGNED16) | |
1920 | && (val & 0x01)) | |
1921 | goto match_failed; | |
1922 | } | |
1923 | else if (operand->flags & ARC_OPERAND_NCHK) | |
1924 | { | |
1925 | if (operand->insert) | |
1926 | { | |
abe7c33b | 1927 | *errmsg = NULL; |
4670103e CZ |
1928 | (*operand->insert)(0, |
1929 | tok[tokidx].X_add_number, | |
abe7c33b CZ |
1930 | errmsg); |
1931 | if (*errmsg) | |
4670103e CZ |
1932 | goto match_failed; |
1933 | } | |
4eb6f892 | 1934 | else if (!(operand->flags & ARC_OPERAND_IGNORE)) |
4670103e CZ |
1935 | goto match_failed; |
1936 | } | |
1937 | break; | |
1938 | ||
1939 | case O_subtract: | |
1940 | /* Check if it is register range. */ | |
1941 | if ((tok[tokidx].X_add_number == 0) | |
1942 | && contains_register (tok[tokidx].X_add_symbol) | |
1943 | && contains_register (tok[tokidx].X_op_symbol)) | |
1944 | { | |
1945 | int regs; | |
1946 | ||
1947 | regs = get_register (tok[tokidx].X_add_symbol); | |
1948 | regs <<= 16; | |
1949 | regs |= get_register (tok[tokidx].X_op_symbol); | |
1950 | if (operand->insert) | |
1951 | { | |
abe7c33b | 1952 | *errmsg = NULL; |
4670103e CZ |
1953 | (*operand->insert)(0, |
1954 | regs, | |
abe7c33b CZ |
1955 | errmsg); |
1956 | if (*errmsg) | |
4670103e CZ |
1957 | goto match_failed; |
1958 | } | |
1959 | else | |
1960 | goto match_failed; | |
1961 | break; | |
1962 | } | |
1a0670f3 | 1963 | /* Fall through. */ |
4670103e | 1964 | default: |
22b92fc4 | 1965 | de_fault: |
4670103e CZ |
1966 | if (operand->default_reloc == 0) |
1967 | goto match_failed; /* The operand needs relocation. */ | |
1968 | ||
1969 | /* Relocs requiring long immediate. FIXME! make it | |
1970 | generic and move it to a function. */ | |
1971 | switch (tok[tokidx].X_md) | |
1972 | { | |
1973 | case O_gotoff: | |
1974 | case O_gotpc: | |
1975 | case O_pcl: | |
1976 | case O_tpoff: | |
1977 | case O_dtpoff: | |
1978 | case O_tlsgd: | |
1979 | case O_tlsie: | |
1980 | if (!(operand->flags & ARC_OPERAND_LIMM)) | |
1981 | goto match_failed; | |
1a0670f3 | 1982 | /* Fall through. */ |
4670103e CZ |
1983 | case O_absent: |
1984 | if (!generic_reloc_p (operand->default_reloc)) | |
1985 | goto match_failed; | |
2b804145 | 1986 | break; |
4670103e CZ |
1987 | default: |
1988 | break; | |
1989 | } | |
1990 | break; | |
1991 | } | |
1992 | /* If expect duplicate, make sure it is duplicate. */ | |
1993 | if (operand->flags & ARC_OPERAND_DUPLICATE) | |
1994 | { | |
1995 | if (t->X_op == O_illegal | |
1996 | || t->X_op == O_absent | |
1997 | || t->X_op == O_register | |
1998 | || (t->X_add_number != tok[tokidx].X_add_number)) | |
1999 | goto match_failed; | |
2000 | } | |
2001 | t = &tok[tokidx]; | |
2002 | break; | |
2003 | ||
2004 | default: | |
2005 | /* Everything else should have been fake. */ | |
2006 | abort (); | |
2007 | } | |
2008 | ||
2009 | ++tokidx; | |
2010 | } | |
2011 | pr_debug ("opr "); | |
2012 | ||
1ae8ab47 | 2013 | /* Setup ready for flag parsing. */ |
4eb6f892 | 2014 | if (!parse_opcode_flags (opcode, nflgs, first_pflag)) |
4670103e CZ |
2015 | goto match_failed; |
2016 | ||
2017 | pr_debug ("flg"); | |
2018 | /* Possible match -- did we use all of our input? */ | |
2019 | if (tokidx == ntok) | |
2020 | { | |
2021 | *pntok = ntok; | |
2022 | pr_debug ("\n"); | |
2023 | return opcode; | |
2024 | } | |
2025 | ||
2026 | match_failed:; | |
2027 | pr_debug ("\n"); | |
2028 | /* Restore the original parameters. */ | |
2029 | memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok)); | |
2030 | ntok = bkntok; | |
2031 | } | |
4670103e CZ |
2032 | |
2033 | if (*pcpumatch) | |
2034 | *pcpumatch = got_cpu_match; | |
2035 | ||
2036 | return NULL; | |
2037 | } | |
2038 | ||
2039 | /* Swap operand tokens. */ | |
2040 | ||
2041 | static void | |
2042 | swap_operand (expressionS *operand_array, | |
2043 | unsigned source, | |
2044 | unsigned destination) | |
2045 | { | |
2046 | expressionS cpy_operand; | |
2047 | expressionS *src_operand; | |
2048 | expressionS *dst_operand; | |
2049 | size_t size; | |
2050 | ||
2051 | if (source == destination) | |
2052 | return; | |
2053 | ||
2054 | src_operand = &operand_array[source]; | |
2055 | dst_operand = &operand_array[destination]; | |
2056 | size = sizeof (expressionS); | |
2057 | ||
2058 | /* Make copy of operand to swap with and swap. */ | |
2059 | memcpy (&cpy_operand, dst_operand, size); | |
2060 | memcpy (dst_operand, src_operand, size); | |
2061 | memcpy (src_operand, &cpy_operand, size); | |
2062 | } | |
2063 | ||
2064 | /* Check if *op matches *tok type. | |
2065 | Returns FALSE if they don't match, TRUE if they match. */ | |
2066 | ||
2067 | static bfd_boolean | |
2068 | pseudo_operand_match (const expressionS *tok, | |
2069 | const struct arc_operand_operation *op) | |
2070 | { | |
2071 | offsetT min, max, val; | |
2072 | bfd_boolean ret; | |
2073 | const struct arc_operand *operand_real = &arc_operands[op->operand_idx]; | |
2074 | ||
2075 | ret = FALSE; | |
2076 | switch (tok->X_op) | |
2077 | { | |
2078 | case O_constant: | |
2079 | if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM)) | |
2080 | ret = 1; | |
2081 | else if (!(operand_real->flags & ARC_OPERAND_IR)) | |
2082 | { | |
2083 | val = tok->X_add_number + op->count; | |
2084 | if (operand_real->flags & ARC_OPERAND_SIGNED) | |
2085 | { | |
2086 | max = (1 << (operand_real->bits - 1)) - 1; | |
2087 | min = -(1 << (operand_real->bits - 1)); | |
2088 | } | |
2089 | else | |
2090 | { | |
2091 | max = (1 << operand_real->bits) - 1; | |
2092 | min = 0; | |
2093 | } | |
2094 | if (min <= val && val <= max) | |
2095 | ret = TRUE; | |
2096 | } | |
6f4b1afc CM |
2097 | break; |
2098 | ||
4670103e CZ |
2099 | case O_symbol: |
2100 | /* Handle all symbols as long immediates or signed 9. */ | |
db18dbab GM |
2101 | if (operand_real->flags & ARC_OPERAND_LIMM |
2102 | || ((operand_real->flags & ARC_OPERAND_SIGNED) | |
2103 | && operand_real->bits == 9)) | |
4670103e | 2104 | ret = TRUE; |
6f4b1afc CM |
2105 | break; |
2106 | ||
4670103e CZ |
2107 | case O_register: |
2108 | if (operand_real->flags & ARC_OPERAND_IR) | |
2109 | ret = TRUE; | |
2110 | break; | |
2111 | ||
2112 | case O_bracket: | |
2113 | if (operand_real->flags & ARC_OPERAND_BRAKET) | |
2114 | ret = TRUE; | |
6f4b1afc CM |
2115 | break; |
2116 | ||
2117 | default: | |
4670103e | 2118 | /* Unknown. */ |
6f4b1afc CM |
2119 | break; |
2120 | } | |
4670103e CZ |
2121 | return ret; |
2122 | } | |
6f4b1afc | 2123 | |
4670103e CZ |
2124 | /* Find pseudo instruction in array. */ |
2125 | ||
2126 | static const struct arc_pseudo_insn * | |
2127 | find_pseudo_insn (const char *opname, | |
2128 | int ntok, | |
2129 | const expressionS *tok) | |
2130 | { | |
2131 | const struct arc_pseudo_insn *pseudo_insn = NULL; | |
2132 | const struct arc_operand_operation *op; | |
2133 | unsigned int i; | |
2134 | int j; | |
2135 | ||
2136 | for (i = 0; i < arc_num_pseudo_insn; ++i) | |
6f4b1afc | 2137 | { |
4670103e CZ |
2138 | pseudo_insn = &arc_pseudo_insns[i]; |
2139 | if (strcmp (pseudo_insn->mnemonic_p, opname) == 0) | |
2140 | { | |
2141 | op = pseudo_insn->operand; | |
2142 | for (j = 0; j < ntok; ++j) | |
2143 | if (!pseudo_operand_match (&tok[j], &op[j])) | |
2144 | break; | |
2145 | ||
2146 | /* Found the right instruction. */ | |
2147 | if (j == ntok) | |
2148 | return pseudo_insn; | |
2149 | } | |
6f4b1afc | 2150 | } |
4670103e CZ |
2151 | return NULL; |
2152 | } | |
252b5132 | 2153 | |
4670103e | 2154 | /* Assumes the expressionS *tok is of sufficient size. */ |
252b5132 | 2155 | |
b9b47ab7 | 2156 | static const struct arc_opcode_hash_entry * |
4670103e CZ |
2157 | find_special_case_pseudo (const char *opname, |
2158 | int *ntok, | |
2159 | expressionS *tok, | |
2160 | int *nflgs, | |
2161 | struct arc_flags *pflags) | |
2162 | { | |
2163 | const struct arc_pseudo_insn *pseudo_insn = NULL; | |
2164 | const struct arc_operand_operation *operand_pseudo; | |
2165 | const struct arc_operand *operand_real; | |
2166 | unsigned i; | |
2167 | char construct_operand[MAX_CONSTR_STR]; | |
886a2506 | 2168 | |
4670103e CZ |
2169 | /* Find whether opname is in pseudo instruction array. */ |
2170 | pseudo_insn = find_pseudo_insn (opname, *ntok, tok); | |
2171 | ||
2172 | if (pseudo_insn == NULL) | |
2173 | return NULL; | |
2174 | ||
2175 | /* Handle flag, Limited to one flag at the moment. */ | |
2176 | if (pseudo_insn->flag_r != NULL) | |
2177 | *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs], | |
2178 | MAX_INSN_FLGS - *nflgs); | |
2179 | ||
2180 | /* Handle operand operations. */ | |
2181 | for (i = 0; i < pseudo_insn->operand_cnt; ++i) | |
252b5132 | 2182 | { |
4670103e CZ |
2183 | operand_pseudo = &pseudo_insn->operand[i]; |
2184 | operand_real = &arc_operands[operand_pseudo->operand_idx]; | |
886a2506 | 2185 | |
db18dbab GM |
2186 | if (operand_real->flags & ARC_OPERAND_BRAKET |
2187 | && !operand_pseudo->needs_insert) | |
4670103e | 2188 | continue; |
b125bd17 | 2189 | |
4670103e CZ |
2190 | /* Has to be inserted (i.e. this token does not exist yet). */ |
2191 | if (operand_pseudo->needs_insert) | |
2192 | { | |
2193 | if (operand_real->flags & ARC_OPERAND_BRAKET) | |
2194 | { | |
2195 | tok[i].X_op = O_bracket; | |
2196 | ++(*ntok); | |
2197 | continue; | |
2198 | } | |
b125bd17 | 2199 | |
4670103e CZ |
2200 | /* Check if operand is a register or constant and handle it |
2201 | by type. */ | |
2202 | if (operand_real->flags & ARC_OPERAND_IR) | |
2203 | snprintf (construct_operand, MAX_CONSTR_STR, "r%d", | |
2204 | operand_pseudo->count); | |
2205 | else | |
2206 | snprintf (construct_operand, MAX_CONSTR_STR, "%d", | |
2207 | operand_pseudo->count); | |
886a2506 | 2208 | |
4670103e CZ |
2209 | tokenize_arguments (construct_operand, &tok[i], 1); |
2210 | ++(*ntok); | |
2211 | } | |
2212 | ||
2213 | else if (operand_pseudo->count) | |
2214 | { | |
2215 | /* Operand number has to be adjusted accordingly (by operand | |
2216 | type). */ | |
2217 | switch (tok[i].X_op) | |
2218 | { | |
2219 | case O_constant: | |
2220 | tok[i].X_add_number += operand_pseudo->count; | |
2221 | break; | |
2222 | ||
2223 | case O_symbol: | |
2224 | break; | |
2225 | ||
2226 | default: | |
2227 | /* Ignored. */ | |
2228 | break; | |
2229 | } | |
2230 | } | |
2231 | } | |
2232 | ||
2233 | /* Swap operands if necessary. Only supports one swap at the | |
2234 | moment. */ | |
2235 | for (i = 0; i < pseudo_insn->operand_cnt; ++i) | |
2236 | { | |
2237 | operand_pseudo = &pseudo_insn->operand[i]; | |
2238 | ||
2239 | if (operand_pseudo->swap_operand_idx == i) | |
2240 | continue; | |
2241 | ||
2242 | swap_operand (tok, i, operand_pseudo->swap_operand_idx); | |
2243 | ||
2244 | /* Prevent a swap back later by breaking out. */ | |
2245 | break; | |
2246 | } | |
2247 | ||
da5be039 | 2248 | return arc_find_opcode (pseudo_insn->mnemonic_r); |
4670103e CZ |
2249 | } |
2250 | ||
b9b47ab7 | 2251 | static const struct arc_opcode_hash_entry * |
4670103e CZ |
2252 | find_special_case_flag (const char *opname, |
2253 | int *nflgs, | |
2254 | struct arc_flags *pflags) | |
2255 | { | |
2256 | unsigned int i; | |
2257 | const char *flagnm; | |
2258 | unsigned flag_idx, flag_arr_idx; | |
2259 | size_t flaglen, oplen; | |
2260 | const struct arc_flag_special *arc_flag_special_opcode; | |
b9b47ab7 | 2261 | const struct arc_opcode_hash_entry *entry; |
4670103e CZ |
2262 | |
2263 | /* Search for special case instruction. */ | |
2264 | for (i = 0; i < arc_num_flag_special; i++) | |
2265 | { | |
2266 | arc_flag_special_opcode = &arc_flag_special_cases[i]; | |
2267 | oplen = strlen (arc_flag_special_opcode->name); | |
2268 | ||
2269 | if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0) | |
2270 | continue; | |
2271 | ||
2272 | /* Found a potential special case instruction, now test for | |
2273 | flags. */ | |
2274 | for (flag_arr_idx = 0;; ++flag_arr_idx) | |
2275 | { | |
2276 | flag_idx = arc_flag_special_opcode->flags[flag_arr_idx]; | |
2277 | if (flag_idx == 0) | |
2278 | break; /* End of array, nothing found. */ | |
886a2506 | 2279 | |
4670103e CZ |
2280 | flagnm = arc_flag_operands[flag_idx].name; |
2281 | flaglen = strlen (flagnm); | |
2282 | if (strcmp (opname + oplen, flagnm) == 0) | |
2283 | { | |
b9b47ab7 | 2284 | entry = arc_find_opcode (arc_flag_special_opcode->name); |
886a2506 | 2285 | |
4670103e CZ |
2286 | if (*nflgs + 1 > MAX_INSN_FLGS) |
2287 | break; | |
2288 | memcpy (pflags[*nflgs].name, flagnm, flaglen); | |
2289 | pflags[*nflgs].name[flaglen] = '\0'; | |
2290 | (*nflgs)++; | |
b9b47ab7 | 2291 | return entry; |
4670103e CZ |
2292 | } |
2293 | } | |
2294 | } | |
2295 | return NULL; | |
2296 | } | |
886a2506 | 2297 | |
4670103e | 2298 | /* Used to find special case opcode. */ |
886a2506 | 2299 | |
b9b47ab7 | 2300 | static const struct arc_opcode_hash_entry * |
4670103e CZ |
2301 | find_special_case (const char *opname, |
2302 | int *nflgs, | |
2303 | struct arc_flags *pflags, | |
2304 | expressionS *tok, | |
2305 | int *ntok) | |
2306 | { | |
b9b47ab7 | 2307 | const struct arc_opcode_hash_entry *entry; |
886a2506 | 2308 | |
b9b47ab7 | 2309 | entry = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags); |
886a2506 | 2310 | |
b9b47ab7 AB |
2311 | if (entry == NULL) |
2312 | entry = find_special_case_flag (opname, nflgs, pflags); | |
886a2506 | 2313 | |
b9b47ab7 | 2314 | return entry; |
4670103e | 2315 | } |
886a2506 | 2316 | |
4670103e CZ |
2317 | /* Given an opcode name, pre-tockenized set of argumenst and the |
2318 | opcode flags, take it all the way through emission. */ | |
886a2506 | 2319 | |
4670103e CZ |
2320 | static void |
2321 | assemble_tokens (const char *opname, | |
2322 | expressionS *tok, | |
2323 | int ntok, | |
2324 | struct arc_flags *pflags, | |
2325 | int nflgs) | |
2326 | { | |
2327 | bfd_boolean found_something = FALSE; | |
b9b47ab7 | 2328 | const struct arc_opcode_hash_entry *entry; |
4670103e | 2329 | int cpumatch = 1; |
abe7c33b | 2330 | const char *errmsg = NULL; |
886a2506 | 2331 | |
4670103e | 2332 | /* Search opcodes. */ |
b9b47ab7 | 2333 | entry = arc_find_opcode (opname); |
886a2506 | 2334 | |
4670103e | 2335 | /* Couldn't find opcode conventional way, try special cases. */ |
b9b47ab7 AB |
2336 | if (entry == NULL) |
2337 | entry = find_special_case (opname, &nflgs, pflags, tok, &ntok); | |
886a2506 | 2338 | |
b9b47ab7 | 2339 | if (entry != NULL) |
4670103e | 2340 | { |
b9b47ab7 AB |
2341 | const struct arc_opcode *opcode; |
2342 | ||
1328504b AB |
2343 | pr_debug ("%s:%d: assemble_tokens: %s\n", |
2344 | frag_now->fr_file, frag_now->fr_line, opname); | |
4670103e | 2345 | found_something = TRUE; |
b9b47ab7 | 2346 | opcode = find_opcode_match (entry, tok, &ntok, pflags, |
abe7c33b | 2347 | nflgs, &cpumatch, &errmsg); |
b9b47ab7 | 2348 | if (opcode != NULL) |
4670103e CZ |
2349 | { |
2350 | struct arc_insn insn; | |
b9b47ab7 | 2351 | |
4670103e CZ |
2352 | assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn); |
2353 | emit_insn (&insn); | |
2354 | return; | |
2355 | } | |
2356 | } | |
886a2506 | 2357 | |
4670103e CZ |
2358 | if (found_something) |
2359 | { | |
2360 | if (cpumatch) | |
abe7c33b CZ |
2361 | if (errmsg) |
2362 | as_bad (_("%s for instruction '%s'"), errmsg, opname); | |
2363 | else | |
2364 | as_bad (_("inappropriate arguments for opcode '%s'"), opname); | |
4670103e CZ |
2365 | else |
2366 | as_bad (_("opcode '%s' not supported for target %s"), opname, | |
bb65a718 | 2367 | selected_cpu.name); |
4670103e CZ |
2368 | } |
2369 | else | |
2370 | as_bad (_("unknown opcode '%s'"), opname); | |
886a2506 NC |
2371 | } |
2372 | ||
4670103e | 2373 | /* The public interface to the instruction assembler. */ |
886a2506 | 2374 | |
4670103e CZ |
2375 | void |
2376 | md_assemble (char *str) | |
886a2506 | 2377 | { |
4670103e CZ |
2378 | char *opname; |
2379 | expressionS tok[MAX_INSN_ARGS]; | |
2380 | int ntok, nflg; | |
2381 | size_t opnamelen; | |
2382 | struct arc_flags flags[MAX_INSN_FLGS]; | |
886a2506 | 2383 | |
4670103e CZ |
2384 | /* Split off the opcode. */ |
2385 | opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468"); | |
29a2809e | 2386 | opname = xmemdup0 (str, opnamelen); |
886a2506 | 2387 | |
4670103e CZ |
2388 | /* Signalize we are assmbling the instructions. */ |
2389 | assembling_insn = TRUE; | |
886a2506 | 2390 | |
4670103e CZ |
2391 | /* Tokenize the flags. */ |
2392 | if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1) | |
2393 | { | |
2394 | as_bad (_("syntax error")); | |
2395 | return; | |
2396 | } | |
886a2506 | 2397 | |
4670103e CZ |
2398 | /* Scan up to the end of the mnemonic which must end in space or end |
2399 | of string. */ | |
2400 | str += opnamelen; | |
2401 | for (; *str != '\0'; str++) | |
2402 | if (*str == ' ') | |
2403 | break; | |
886a2506 | 2404 | |
4670103e CZ |
2405 | /* Tokenize the rest of the line. */ |
2406 | if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0) | |
886a2506 | 2407 | { |
4670103e CZ |
2408 | as_bad (_("syntax error")); |
2409 | return; | |
252b5132 RH |
2410 | } |
2411 | ||
4670103e CZ |
2412 | /* Finish it off. */ |
2413 | assemble_tokens (opname, tok, ntok, flags, nflg); | |
2414 | assembling_insn = FALSE; | |
2415 | } | |
2416 | ||
2417 | /* Callback to insert a register into the hash table. */ | |
2418 | ||
2419 | static void | |
f86f5863 | 2420 | declare_register (const char *name, int number) |
4670103e CZ |
2421 | { |
2422 | const char *err; | |
2423 | symbolS *regS = symbol_create (name, reg_section, | |
2424 | number, &zero_address_frag); | |
2425 | ||
2426 | err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS); | |
2427 | if (err) | |
e6ba1cba | 2428 | as_fatal (_("Inserting \"%s\" into register table failed: %s"), |
4670103e CZ |
2429 | name, err); |
2430 | } | |
252b5132 | 2431 | |
4670103e | 2432 | /* Construct symbols for each of the general registers. */ |
252b5132 | 2433 | |
4670103e CZ |
2434 | static void |
2435 | declare_register_set (void) | |
2436 | { | |
2437 | int i; | |
2438 | for (i = 0; i < 64; ++i) | |
886a2506 | 2439 | { |
4670103e CZ |
2440 | char name[7]; |
2441 | ||
2442 | sprintf (name, "r%d", i); | |
2443 | declare_register (name, i); | |
2444 | if ((i & 0x01) == 0) | |
886a2506 | 2445 | { |
4670103e CZ |
2446 | sprintf (name, "r%dr%d", i, i+1); |
2447 | declare_register (name, i); | |
886a2506 NC |
2448 | } |
2449 | } | |
252b5132 | 2450 | } |
ea1562b3 | 2451 | |
db18dbab GM |
2452 | /* Construct a symbol for an address type. */ |
2453 | ||
2454 | static void | |
2455 | declare_addrtype (const char *name, int number) | |
2456 | { | |
2457 | const char *err; | |
2458 | symbolS *addrtypeS = symbol_create (name, undefined_section, | |
2459 | number, &zero_address_frag); | |
2460 | ||
2461 | err = hash_insert (arc_addrtype_hash, S_GET_NAME (addrtypeS), | |
2462 | (void *) addrtypeS); | |
2463 | if (err) | |
2464 | as_fatal (_("Inserting \"%s\" into address type table failed: %s"), | |
2465 | name, err); | |
2466 | } | |
2467 | ||
4670103e CZ |
2468 | /* Port-specific assembler initialization. This function is called |
2469 | once, at assembler startup time. */ | |
ea1562b3 NC |
2470 | |
2471 | void | |
4670103e | 2472 | md_begin (void) |
ea1562b3 | 2473 | { |
b99747ae | 2474 | const struct arc_opcode *opcode = arc_opcodes; |
886a2506 | 2475 | |
bb65a718 AB |
2476 | if (mach_selection_mode == MACH_SELECTION_NONE) |
2477 | arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT); | |
24740d83 | 2478 | |
4670103e CZ |
2479 | /* The endianness can be chosen "at the factory". */ |
2480 | target_big_endian = byte_order == BIG_ENDIAN; | |
886a2506 | 2481 | |
bb65a718 | 2482 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach)) |
4670103e CZ |
2483 | as_warn (_("could not set architecture and machine")); |
2484 | ||
2485 | /* Set elf header flags. */ | |
bb65a718 | 2486 | bfd_set_private_flags (stdoutput, selected_cpu.eflags); |
4670103e CZ |
2487 | |
2488 | /* Set up a hash table for the instructions. */ | |
2489 | arc_opcode_hash = hash_new (); | |
2490 | if (arc_opcode_hash == NULL) | |
2491 | as_fatal (_("Virtual memory exhausted")); | |
2492 | ||
2493 | /* Initialize the hash table with the insns. */ | |
b99747ae | 2494 | do |
ea1562b3 | 2495 | { |
b99747ae | 2496 | const char *name = opcode->name; |
da5be039 | 2497 | |
b99747ae | 2498 | arc_insert_opcode (opcode); |
4670103e | 2499 | |
b99747ae CZ |
2500 | while (++opcode && opcode->name |
2501 | && (opcode->name == name | |
2502 | || !strcmp (opcode->name, name))) | |
4670103e | 2503 | continue; |
b99747ae | 2504 | }while (opcode->name); |
4670103e CZ |
2505 | |
2506 | /* Register declaration. */ | |
2507 | arc_reg_hash = hash_new (); | |
2508 | if (arc_reg_hash == NULL) | |
2509 | as_fatal (_("Virtual memory exhausted")); | |
2510 | ||
2511 | declare_register_set (); | |
2512 | declare_register ("gp", 26); | |
2513 | declare_register ("fp", 27); | |
2514 | declare_register ("sp", 28); | |
2515 | declare_register ("ilink", 29); | |
2516 | declare_register ("ilink1", 29); | |
2517 | declare_register ("ilink2", 30); | |
2518 | declare_register ("blink", 31); | |
2519 | ||
87789e08 CZ |
2520 | /* XY memory registers. */ |
2521 | declare_register ("x0_u0", 32); | |
2522 | declare_register ("x0_u1", 33); | |
2523 | declare_register ("x1_u0", 34); | |
2524 | declare_register ("x1_u1", 35); | |
2525 | declare_register ("x2_u0", 36); | |
2526 | declare_register ("x2_u1", 37); | |
2527 | declare_register ("x3_u0", 38); | |
2528 | declare_register ("x3_u1", 39); | |
2529 | declare_register ("y0_u0", 40); | |
2530 | declare_register ("y0_u1", 41); | |
2531 | declare_register ("y1_u0", 42); | |
2532 | declare_register ("y1_u1", 43); | |
2533 | declare_register ("y2_u0", 44); | |
2534 | declare_register ("y2_u1", 45); | |
2535 | declare_register ("y3_u0", 46); | |
2536 | declare_register ("y3_u1", 47); | |
2537 | declare_register ("x0_nu", 48); | |
2538 | declare_register ("x1_nu", 49); | |
2539 | declare_register ("x2_nu", 50); | |
2540 | declare_register ("x3_nu", 51); | |
2541 | declare_register ("y0_nu", 52); | |
2542 | declare_register ("y1_nu", 53); | |
2543 | declare_register ("y2_nu", 54); | |
2544 | declare_register ("y3_nu", 55); | |
2545 | ||
4670103e CZ |
2546 | declare_register ("mlo", 57); |
2547 | declare_register ("mmid", 58); | |
2548 | declare_register ("mhi", 59); | |
2549 | ||
2550 | declare_register ("acc1", 56); | |
2551 | declare_register ("acc2", 57); | |
2552 | ||
2553 | declare_register ("lp_count", 60); | |
2554 | declare_register ("pcl", 63); | |
2555 | ||
2556 | /* Initialize the last instructions. */ | |
2557 | memset (&arc_last_insns[0], 0, sizeof (arc_last_insns)); | |
f36e33da CZ |
2558 | |
2559 | /* Aux register declaration. */ | |
2560 | arc_aux_hash = hash_new (); | |
2561 | if (arc_aux_hash == NULL) | |
2562 | as_fatal (_("Virtual memory exhausted")); | |
2563 | ||
2564 | const struct arc_aux_reg *auxr = &arc_aux_regs[0]; | |
2565 | unsigned int i; | |
2566 | for (i = 0; i < arc_num_aux_regs; i++, auxr++) | |
2567 | { | |
2568 | const char *retval; | |
2569 | ||
bb65a718 | 2570 | if (!(auxr->cpu & selected_cpu.flags)) |
f36e33da CZ |
2571 | continue; |
2572 | ||
2573 | if ((auxr->subclass != NONE) | |
2574 | && !check_cpu_feature (auxr->subclass)) | |
2575 | continue; | |
2576 | ||
2577 | retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr); | |
2578 | if (retval) | |
2579 | as_fatal (_("internal error: can't hash aux register '%s': %s"), | |
2580 | auxr->name, retval); | |
2581 | } | |
db18dbab GM |
2582 | |
2583 | /* Address type declaration. */ | |
2584 | arc_addrtype_hash = hash_new (); | |
2585 | if (arc_addrtype_hash == NULL) | |
2586 | as_fatal (_("Virtual memory exhausted")); | |
2587 | ||
2588 | declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD); | |
2589 | declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID); | |
2590 | declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD); | |
2591 | declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD); | |
2592 | declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD); | |
2593 | declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM); | |
2594 | declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA); | |
2595 | declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD); | |
2596 | declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD); | |
2597 | declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD); | |
2598 | declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID); | |
2599 | declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD); | |
2600 | declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM); | |
2601 | declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD); | |
2602 | declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA); | |
2603 | declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD); | |
886a2506 | 2604 | } |
ea1562b3 | 2605 | |
4670103e CZ |
2606 | /* Write a value out to the object file, using the appropriate |
2607 | endianness. */ | |
ea1562b3 | 2608 | |
4670103e CZ |
2609 | void |
2610 | md_number_to_chars (char *buf, | |
2611 | valueT val, | |
2612 | int n) | |
886a2506 | 2613 | { |
4670103e CZ |
2614 | if (target_big_endian) |
2615 | number_to_chars_bigendian (buf, val, n); | |
2616 | else | |
2617 | number_to_chars_littleendian (buf, val, n); | |
886a2506 | 2618 | } |
ea1562b3 | 2619 | |
4670103e | 2620 | /* Round up a section size to the appropriate boundary. */ |
ea1562b3 | 2621 | |
4670103e CZ |
2622 | valueT |
2623 | md_section_align (segT segment, | |
2624 | valueT size) | |
886a2506 | 2625 | { |
4670103e CZ |
2626 | int align = bfd_get_section_alignment (stdoutput, segment); |
2627 | ||
2628 | return ((size + (1 << align) - 1) & (-((valueT) 1 << align))); | |
886a2506 | 2629 | } |
ea1562b3 | 2630 | |
4670103e CZ |
2631 | /* The location from which a PC relative jump should be calculated, |
2632 | given a PC relative reloc. */ | |
ea1562b3 | 2633 | |
4670103e CZ |
2634 | long |
2635 | md_pcrel_from_section (fixS *fixP, | |
2636 | segT sec) | |
886a2506 | 2637 | { |
4670103e | 2638 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
ea1562b3 | 2639 | |
4670103e | 2640 | pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset); |
ea1562b3 | 2641 | |
4670103e CZ |
2642 | if (fixP->fx_addsy != (symbolS *) NULL |
2643 | && (!S_IS_DEFINED (fixP->fx_addsy) | |
2644 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) | |
2645 | { | |
2646 | pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy)); | |
ea1562b3 | 2647 | |
4670103e CZ |
2648 | /* The symbol is undefined (or is defined but not in this section). |
2649 | Let the linker figure it out. */ | |
2650 | return 0; | |
2651 | } | |
2652 | ||
2653 | if ((int) fixP->fx_r_type < 0) | |
886a2506 | 2654 | { |
4670103e CZ |
2655 | /* These are the "internal" relocations. Align them to |
2656 | 32 bit boundary (PCL), for the moment. */ | |
2657 | base &= ~3; | |
886a2506 | 2658 | } |
4670103e CZ |
2659 | else |
2660 | { | |
2661 | switch (fixP->fx_r_type) | |
2662 | { | |
2663 | case BFD_RELOC_ARC_PC32: | |
2664 | /* The hardware calculates relative to the start of the | |
2665 | insn, but this relocation is relative to location of the | |
2666 | LIMM, compensate. The base always needs to be | |
2b0f3761 | 2667 | subtracted by 4 as we do not support this type of PCrel |
4670103e CZ |
2668 | relocation for short instructions. */ |
2669 | base -= 4; | |
2670 | /* Fall through. */ | |
2671 | case BFD_RELOC_ARC_PLT32: | |
2672 | case BFD_RELOC_ARC_S25H_PCREL_PLT: | |
2673 | case BFD_RELOC_ARC_S21H_PCREL_PLT: | |
2674 | case BFD_RELOC_ARC_S25W_PCREL_PLT: | |
2675 | case BFD_RELOC_ARC_S21W_PCREL_PLT: | |
2676 | ||
2677 | case BFD_RELOC_ARC_S21H_PCREL: | |
2678 | case BFD_RELOC_ARC_S25H_PCREL: | |
2679 | case BFD_RELOC_ARC_S13_PCREL: | |
2680 | case BFD_RELOC_ARC_S21W_PCREL: | |
2681 | case BFD_RELOC_ARC_S25W_PCREL: | |
2682 | base &= ~3; | |
2683 | break; | |
2684 | default: | |
2685 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2686 | _("unhandled reloc %s in md_pcrel_from_section"), | |
2687 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
2688 | break; | |
2689 | } | |
2690 | } | |
2691 | ||
9e32d9ae AB |
2692 | pr_debug ("pcrel from %"BFD_VMA_FMT"x + %lx = %"BFD_VMA_FMT"x, " |
2693 | "symbol: %s (%"BFD_VMA_FMT"x)\n", | |
4670103e CZ |
2694 | fixP->fx_frag->fr_address, fixP->fx_where, base, |
2695 | fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)", | |
2696 | fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0); | |
2697 | ||
2698 | return base; | |
886a2506 | 2699 | } |
ea1562b3 | 2700 | |
4670103e | 2701 | /* Given a BFD relocation find the coresponding operand. */ |
ea1562b3 | 2702 | |
4670103e CZ |
2703 | static const struct arc_operand * |
2704 | find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc) | |
2705 | { | |
2706 | unsigned i; | |
ea1562b3 | 2707 | |
4670103e CZ |
2708 | for (i = 0; i < arc_num_operands; i++) |
2709 | if (arc_operands[i].default_reloc == reloc) | |
2710 | return &arc_operands[i]; | |
2711 | return NULL; | |
2712 | } | |
ea1562b3 | 2713 | |
4670103e | 2714 | /* Insert an operand value into an instruction. */ |
ea1562b3 | 2715 | |
bdfe53e3 AB |
2716 | static unsigned long long |
2717 | insert_operand (unsigned long long insn, | |
4670103e | 2718 | const struct arc_operand *operand, |
bdfe53e3 | 2719 | long long val, |
3b4dbbbf | 2720 | const char *file, |
4670103e | 2721 | unsigned line) |
886a2506 | 2722 | { |
4670103e | 2723 | offsetT min = 0, max = 0; |
ea1562b3 | 2724 | |
4670103e CZ |
2725 | if (operand->bits != 32 |
2726 | && !(operand->flags & ARC_OPERAND_NCHK) | |
2727 | && !(operand->flags & ARC_OPERAND_FAKE)) | |
886a2506 | 2728 | { |
4670103e CZ |
2729 | if (operand->flags & ARC_OPERAND_SIGNED) |
2730 | { | |
2731 | max = (1 << (operand->bits - 1)) - 1; | |
2732 | min = -(1 << (operand->bits - 1)); | |
2733 | } | |
2734 | else | |
2735 | { | |
2736 | max = (1 << operand->bits) - 1; | |
2737 | min = 0; | |
2738 | } | |
886a2506 | 2739 | |
4670103e CZ |
2740 | if (val < min || val > max) |
2741 | as_bad_value_out_of_range (_("operand"), | |
2742 | val, min, max, file, line); | |
2743 | } | |
ea1562b3 | 2744 | |
bdfe53e3 | 2745 | pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08llx\n", |
4670103e | 2746 | min, val, max, insn); |
ea1562b3 | 2747 | |
4670103e CZ |
2748 | if ((operand->flags & ARC_OPERAND_ALIGNED32) |
2749 | && (val & 0x03)) | |
2750 | as_bad_where (file, line, | |
2751 | _("Unaligned operand. Needs to be 32bit aligned")); | |
ea1562b3 | 2752 | |
4670103e CZ |
2753 | if ((operand->flags & ARC_OPERAND_ALIGNED16) |
2754 | && (val & 0x01)) | |
2755 | as_bad_where (file, line, | |
2756 | _("Unaligned operand. Needs to be 16bit aligned")); | |
ea1562b3 | 2757 | |
4670103e CZ |
2758 | if (operand->insert) |
2759 | { | |
2760 | const char *errmsg = NULL; | |
ea1562b3 | 2761 | |
4670103e CZ |
2762 | insn = (*operand->insert) (insn, val, &errmsg); |
2763 | if (errmsg) | |
2764 | as_warn_where (file, line, "%s", errmsg); | |
2765 | } | |
2766 | else | |
2767 | { | |
2768 | if (operand->flags & ARC_OPERAND_TRUNCATE) | |
2769 | { | |
2770 | if (operand->flags & ARC_OPERAND_ALIGNED32) | |
2771 | val >>= 2; | |
2772 | if (operand->flags & ARC_OPERAND_ALIGNED16) | |
2773 | val >>= 1; | |
886a2506 | 2774 | } |
4670103e CZ |
2775 | insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift); |
2776 | } | |
2777 | return insn; | |
2778 | } | |
ea1562b3 | 2779 | |
4670103e CZ |
2780 | /* Apply a fixup to the object code. At this point all symbol values |
2781 | should be fully resolved, and we attempt to completely resolve the | |
2782 | reloc. If we can not do that, we determine the correct reloc code | |
2783 | and put it back in the fixup. To indicate that a fixup has been | |
2784 | eliminated, set fixP->fx_done. */ | |
ea1562b3 | 2785 | |
4670103e CZ |
2786 | void |
2787 | md_apply_fix (fixS *fixP, | |
2788 | valueT *valP, | |
2789 | segT seg) | |
2790 | { | |
2791 | char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; | |
2792 | valueT value = *valP; | |
2793 | unsigned insn = 0; | |
2794 | symbolS *fx_addsy, *fx_subsy; | |
2795 | offsetT fx_offset; | |
2796 | segT add_symbol_segment = absolute_section; | |
2797 | segT sub_symbol_segment = absolute_section; | |
2798 | const struct arc_operand *operand = NULL; | |
2799 | extended_bfd_reloc_code_real_type reloc; | |
886a2506 | 2800 | |
4670103e CZ |
2801 | pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n", |
2802 | fixP->fx_file, fixP->fx_line, fixP->fx_r_type, | |
2803 | ((int) fixP->fx_r_type < 0) ? "Internal": | |
2804 | bfd_get_reloc_code_name (fixP->fx_r_type), value, | |
2805 | fixP->fx_offset); | |
886a2506 | 2806 | |
4670103e CZ |
2807 | fx_addsy = fixP->fx_addsy; |
2808 | fx_subsy = fixP->fx_subsy; | |
2809 | fx_offset = 0; | |
886a2506 | 2810 | |
4670103e CZ |
2811 | if (fx_addsy) |
2812 | { | |
2813 | add_symbol_segment = S_GET_SEGMENT (fx_addsy); | |
886a2506 NC |
2814 | } |
2815 | ||
4670103e CZ |
2816 | if (fx_subsy |
2817 | && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF | |
2818 | && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9 | |
2819 | && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD) | |
2820 | { | |
2821 | resolve_symbol_value (fx_subsy); | |
2822 | sub_symbol_segment = S_GET_SEGMENT (fx_subsy); | |
886a2506 | 2823 | |
4670103e CZ |
2824 | if (sub_symbol_segment == absolute_section) |
2825 | { | |
2826 | /* The symbol is really a constant. */ | |
2827 | fx_offset -= S_GET_VALUE (fx_subsy); | |
2828 | fx_subsy = NULL; | |
2829 | } | |
2830 | else | |
2831 | { | |
2832 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2833 | _("can't resolve `%s' {%s section} - `%s' {%s section}"), | |
2834 | fx_addsy ? S_GET_NAME (fx_addsy) : "0", | |
2835 | segment_name (add_symbol_segment), | |
2836 | S_GET_NAME (fx_subsy), | |
2837 | segment_name (sub_symbol_segment)); | |
2838 | return; | |
2839 | } | |
2840 | } | |
886a2506 | 2841 | |
4670103e CZ |
2842 | if (fx_addsy |
2843 | && !S_IS_WEAK (fx_addsy)) | |
2844 | { | |
2845 | if (add_symbol_segment == seg | |
2846 | && fixP->fx_pcrel) | |
2847 | { | |
2848 | value += S_GET_VALUE (fx_addsy); | |
2849 | value -= md_pcrel_from_section (fixP, seg); | |
2850 | fx_addsy = NULL; | |
2851 | fixP->fx_pcrel = FALSE; | |
2852 | } | |
2853 | else if (add_symbol_segment == absolute_section) | |
2854 | { | |
2855 | value = fixP->fx_offset; | |
2856 | fx_offset += S_GET_VALUE (fixP->fx_addsy); | |
2857 | fx_addsy = NULL; | |
2858 | fixP->fx_pcrel = FALSE; | |
2859 | } | |
2860 | } | |
886a2506 | 2861 | |
4670103e CZ |
2862 | if (!fx_addsy) |
2863 | fixP->fx_done = TRUE; | |
886a2506 | 2864 | |
4670103e | 2865 | if (fixP->fx_pcrel) |
886a2506 | 2866 | { |
4670103e CZ |
2867 | if (fx_addsy |
2868 | && ((S_IS_DEFINED (fx_addsy) | |
2869 | && S_GET_SEGMENT (fx_addsy) != seg) | |
2870 | || S_IS_WEAK (fx_addsy))) | |
2871 | value += md_pcrel_from_section (fixP, seg); | |
886a2506 | 2872 | |
4670103e CZ |
2873 | switch (fixP->fx_r_type) |
2874 | { | |
2875 | case BFD_RELOC_ARC_32_ME: | |
2876 | /* This is a pc-relative value in a LIMM. Adjust it to the | |
2877 | address of the instruction not to the address of the | |
2878 | LIMM. Note: it is not anylonger valid this afirmation as | |
2879 | the linker consider ARC_PC32 a fixup to entire 64 bit | |
2880 | insn. */ | |
2881 | fixP->fx_offset += fixP->fx_frag->fr_address; | |
2882 | /* Fall through. */ | |
2883 | case BFD_RELOC_32: | |
2884 | fixP->fx_r_type = BFD_RELOC_ARC_PC32; | |
2885 | /* Fall through. */ | |
2886 | case BFD_RELOC_ARC_PC32: | |
2887 | /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */ | |
886a2506 NC |
2888 | break; |
2889 | default: | |
4670103e CZ |
2890 | if ((int) fixP->fx_r_type < 0) |
2891 | as_fatal (_("PC relative relocation not allowed for (internal) type %d"), | |
2892 | fixP->fx_r_type); | |
886a2506 | 2893 | break; |
ea1562b3 NC |
2894 | } |
2895 | } | |
2896 | ||
4670103e CZ |
2897 | pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n", |
2898 | fixP->fx_file, fixP->fx_line, fixP->fx_r_type, | |
2899 | ((int) fixP->fx_r_type < 0) ? "Internal": | |
2900 | bfd_get_reloc_code_name (fixP->fx_r_type), value, | |
2901 | fixP->fx_offset); | |
886a2506 | 2902 | |
886a2506 | 2903 | |
4670103e CZ |
2904 | /* Now check for TLS relocations. */ |
2905 | reloc = fixP->fx_r_type; | |
2906 | switch (reloc) | |
886a2506 | 2907 | { |
4670103e CZ |
2908 | case BFD_RELOC_ARC_TLS_DTPOFF: |
2909 | case BFD_RELOC_ARC_TLS_LE_32: | |
2910 | if (fixP->fx_done) | |
2911 | break; | |
2912 | /* Fall through. */ | |
2913 | case BFD_RELOC_ARC_TLS_GD_GOT: | |
2914 | case BFD_RELOC_ARC_TLS_IE_GOT: | |
2915 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
2916 | break; | |
886a2506 | 2917 | |
4670103e CZ |
2918 | case BFD_RELOC_ARC_TLS_GD_LD: |
2919 | gas_assert (!fixP->fx_offset); | |
2920 | if (fixP->fx_subsy) | |
2921 | fixP->fx_offset | |
2922 | = (S_GET_VALUE (fixP->fx_subsy) | |
2923 | - fixP->fx_frag->fr_address- fixP->fx_where); | |
2924 | fixP->fx_subsy = NULL; | |
2925 | /* Fall through. */ | |
2926 | case BFD_RELOC_ARC_TLS_GD_CALL: | |
2927 | /* These two relocs are there just to allow ld to change the tls | |
2928 | model for this symbol, by patching the code. The offset - | |
2929 | and scale, if any - will be installed by the linker. */ | |
2930 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
2931 | break; | |
886a2506 | 2932 | |
4670103e CZ |
2933 | case BFD_RELOC_ARC_TLS_LE_S9: |
2934 | case BFD_RELOC_ARC_TLS_DTPOFF_S9: | |
2935 | as_bad (_("TLS_*_S9 relocs are not supported yet")); | |
2936 | break; | |
2937 | ||
2938 | default: | |
2939 | break; | |
886a2506 NC |
2940 | } |
2941 | ||
4670103e | 2942 | if (!fixP->fx_done) |
886a2506 | 2943 | { |
4670103e | 2944 | return; |
886a2506 | 2945 | } |
886a2506 | 2946 | |
4670103e CZ |
2947 | /* Addjust the value if we have a constant. */ |
2948 | value += fx_offset; | |
886a2506 | 2949 | |
4670103e CZ |
2950 | /* For hosts with longs bigger than 32-bits make sure that the top |
2951 | bits of a 32-bit negative value read in by the parser are set, | |
2952 | so that the correct comparisons are made. */ | |
2953 | if (value & 0x80000000) | |
69c9e028 | 2954 | value |= (-1UL << 31); |
886a2506 | 2955 | |
4670103e CZ |
2956 | reloc = fixP->fx_r_type; |
2957 | switch (reloc) | |
2958 | { | |
2959 | case BFD_RELOC_8: | |
2960 | case BFD_RELOC_16: | |
2961 | case BFD_RELOC_24: | |
2962 | case BFD_RELOC_32: | |
2963 | case BFD_RELOC_64: | |
2964 | case BFD_RELOC_ARC_32_PCREL: | |
2965 | md_number_to_chars (fixpos, value, fixP->fx_size); | |
2966 | return; | |
886a2506 | 2967 | |
4670103e CZ |
2968 | case BFD_RELOC_ARC_GOTPC32: |
2969 | /* I cannot fix an GOTPC relocation because I need to relax it | |
2970 | from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */ | |
2971 | as_bad (_("Unsupported operation on reloc")); | |
2972 | return; | |
886a2506 | 2973 | |
4670103e CZ |
2974 | case BFD_RELOC_ARC_TLS_DTPOFF: |
2975 | case BFD_RELOC_ARC_TLS_LE_32: | |
2976 | gas_assert (!fixP->fx_addsy); | |
2977 | gas_assert (!fixP->fx_subsy); | |
1a0670f3 | 2978 | /* Fall through. */ |
886a2506 | 2979 | |
4670103e CZ |
2980 | case BFD_RELOC_ARC_GOTOFF: |
2981 | case BFD_RELOC_ARC_32_ME: | |
2982 | case BFD_RELOC_ARC_PC32: | |
2983 | md_number_to_chars_midend (fixpos, value, fixP->fx_size); | |
2984 | return; | |
886a2506 | 2985 | |
4670103e CZ |
2986 | case BFD_RELOC_ARC_PLT32: |
2987 | md_number_to_chars_midend (fixpos, value, fixP->fx_size); | |
2988 | return; | |
886a2506 | 2989 | |
4670103e CZ |
2990 | case BFD_RELOC_ARC_S25H_PCREL_PLT: |
2991 | reloc = BFD_RELOC_ARC_S25W_PCREL; | |
2992 | goto solve_plt; | |
886a2506 | 2993 | |
4670103e CZ |
2994 | case BFD_RELOC_ARC_S21H_PCREL_PLT: |
2995 | reloc = BFD_RELOC_ARC_S21H_PCREL; | |
2996 | goto solve_plt; | |
886a2506 | 2997 | |
4670103e CZ |
2998 | case BFD_RELOC_ARC_S25W_PCREL_PLT: |
2999 | reloc = BFD_RELOC_ARC_S25W_PCREL; | |
3000 | goto solve_plt; | |
886a2506 | 3001 | |
4670103e CZ |
3002 | case BFD_RELOC_ARC_S21W_PCREL_PLT: |
3003 | reloc = BFD_RELOC_ARC_S21W_PCREL; | |
1a0670f3 | 3004 | /* Fall through. */ |
886a2506 | 3005 | |
4670103e CZ |
3006 | case BFD_RELOC_ARC_S25W_PCREL: |
3007 | case BFD_RELOC_ARC_S21W_PCREL: | |
3008 | case BFD_RELOC_ARC_S21H_PCREL: | |
3009 | case BFD_RELOC_ARC_S25H_PCREL: | |
3010 | case BFD_RELOC_ARC_S13_PCREL: | |
3011 | solve_plt: | |
3012 | operand = find_operand_for_reloc (reloc); | |
3013 | gas_assert (operand); | |
886a2506 NC |
3014 | break; |
3015 | ||
3016 | default: | |
4670103e CZ |
3017 | { |
3018 | if ((int) fixP->fx_r_type >= 0) | |
3019 | as_fatal (_("unhandled relocation type %s"), | |
3020 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
886a2506 | 3021 | |
4670103e CZ |
3022 | /* The rest of these fixups needs to be completely resolved as |
3023 | constants. */ | |
3024 | if (fixP->fx_addsy != 0 | |
3025 | && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section) | |
3026 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3027 | _("non-absolute expression in constant field")); | |
886a2506 | 3028 | |
4670103e CZ |
3029 | gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands); |
3030 | operand = &arc_operands[-(int) fixP->fx_r_type]; | |
3031 | break; | |
3032 | } | |
3033 | } | |
886a2506 | 3034 | |
4670103e | 3035 | if (target_big_endian) |
886a2506 | 3036 | { |
4670103e | 3037 | switch (fixP->fx_size) |
886a2506 | 3038 | { |
4670103e CZ |
3039 | case 4: |
3040 | insn = bfd_getb32 (fixpos); | |
3041 | break; | |
3042 | case 2: | |
3043 | insn = bfd_getb16 (fixpos); | |
3044 | break; | |
3045 | default: | |
3046 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3047 | _("unknown fixup size")); | |
3048 | } | |
3049 | } | |
3050 | else | |
3051 | { | |
3052 | insn = 0; | |
3053 | switch (fixP->fx_size) | |
3054 | { | |
3055 | case 4: | |
3056 | insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2); | |
3057 | break; | |
3058 | case 2: | |
3059 | insn = bfd_getl16 (fixpos); | |
3060 | break; | |
3061 | default: | |
3062 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3063 | _("unknown fixup size")); | |
886a2506 NC |
3064 | } |
3065 | } | |
886a2506 | 3066 | |
4670103e CZ |
3067 | insn = insert_operand (insn, operand, (offsetT) value, |
3068 | fixP->fx_file, fixP->fx_line); | |
886a2506 | 3069 | |
4670103e CZ |
3070 | md_number_to_chars_midend (fixpos, insn, fixP->fx_size); |
3071 | } | |
886a2506 | 3072 | |
4670103e | 3073 | /* Prepare machine-dependent frags for relaxation. |
886a2506 | 3074 | |
4670103e CZ |
3075 | Called just before relaxation starts. Any symbol that is now undefined |
3076 | will not become defined. | |
886a2506 | 3077 | |
4670103e | 3078 | Return the correct fr_subtype in the frag. |
886a2506 | 3079 | |
4670103e CZ |
3080 | Return the initial "guess for fr_var" to caller. The guess for fr_var |
3081 | is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix | |
3082 | or fr_var contributes to our returned value. | |
886a2506 | 3083 | |
4670103e CZ |
3084 | Although it may not be explicit in the frag, pretend |
3085 | fr_var starts with a value. */ | |
886a2506 | 3086 | |
4670103e CZ |
3087 | int |
3088 | md_estimate_size_before_relax (fragS *fragP, | |
3089 | segT segment) | |
3090 | { | |
3091 | int growth; | |
3092 | ||
3093 | /* If the symbol is not located within the same section AND it's not | |
3094 | an absolute section, use the maximum. OR if the symbol is a | |
3095 | constant AND the insn is by nature not pc-rel, use the maximum. | |
3096 | OR if the symbol is being equated against another symbol, use the | |
3097 | maximum. OR if the symbol is weak use the maximum. */ | |
3098 | if ((S_GET_SEGMENT (fragP->fr_symbol) != segment | |
3099 | && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) | |
3100 | || (symbol_constant_p (fragP->fr_symbol) | |
3101 | && !fragP->tc_frag_data.pcrel) | |
3102 | || symbol_equated_p (fragP->fr_symbol) | |
3103 | || S_IS_WEAK (fragP->fr_symbol)) | |
3104 | { | |
3105 | while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE) | |
3106 | ++fragP->fr_subtype; | |
3107 | } | |
886a2506 | 3108 | |
4670103e CZ |
3109 | growth = md_relax_table[fragP->fr_subtype].rlx_length; |
3110 | fragP->fr_var = growth; | |
886a2506 | 3111 | |
4670103e CZ |
3112 | pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n", |
3113 | fragP->fr_file, fragP->fr_line, growth); | |
886a2506 | 3114 | |
4670103e CZ |
3115 | return growth; |
3116 | } | |
886a2506 | 3117 | |
4670103e CZ |
3118 | /* Translate internal representation of relocation info to BFD target |
3119 | format. */ | |
886a2506 | 3120 | |
4670103e CZ |
3121 | arelent * |
3122 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, | |
3123 | fixS *fixP) | |
3124 | { | |
3125 | arelent *reloc; | |
3126 | bfd_reloc_code_real_type code; | |
886a2506 | 3127 | |
add39d23 TS |
3128 | reloc = XNEW (arelent); |
3129 | reloc->sym_ptr_ptr = XNEW (asymbol *); | |
4670103e CZ |
3130 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); |
3131 | reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; | |
886a2506 | 3132 | |
4670103e CZ |
3133 | /* Make sure none of our internal relocations make it this far. |
3134 | They'd better have been fully resolved by this point. */ | |
3135 | gas_assert ((int) fixP->fx_r_type > 0); | |
886a2506 | 3136 | |
4670103e | 3137 | code = fixP->fx_r_type; |
886a2506 | 3138 | |
4670103e CZ |
3139 | /* if we have something like add gp, pcl, |
3140 | _GLOBAL_OFFSET_TABLE_@gotpc. */ | |
3141 | if (code == BFD_RELOC_ARC_GOTPC32 | |
3142 | && GOT_symbol | |
3143 | && fixP->fx_addsy == GOT_symbol) | |
3144 | code = BFD_RELOC_ARC_GOTPC; | |
886a2506 | 3145 | |
4670103e CZ |
3146 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
3147 | if (reloc->howto == NULL) | |
886a2506 | 3148 | { |
4670103e CZ |
3149 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3150 | _("cannot represent `%s' relocation in object file"), | |
3151 | bfd_get_reloc_code_name (code)); | |
3152 | return NULL; | |
3153 | } | |
886a2506 | 3154 | |
4670103e CZ |
3155 | if (!fixP->fx_pcrel != !reloc->howto->pc_relative) |
3156 | as_fatal (_("internal error? cannot generate `%s' relocation"), | |
3157 | bfd_get_reloc_code_name (code)); | |
886a2506 | 3158 | |
4670103e | 3159 | gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative); |
886a2506 | 3160 | |
05bbf016 | 3161 | reloc->addend = fixP->fx_offset; |
4670103e CZ |
3162 | |
3163 | return reloc; | |
886a2506 NC |
3164 | } |
3165 | ||
4670103e CZ |
3166 | /* Perform post-processing of machine-dependent frags after relaxation. |
3167 | Called after relaxation is finished. | |
3168 | In: Address of frag. | |
3169 | fr_type == rs_machine_dependent. | |
3170 | fr_subtype is what the address relaxed to. | |
886a2506 | 3171 | |
4670103e CZ |
3172 | Out: Any fixS:s and constants are set up. */ |
3173 | ||
3174 | void | |
3175 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, | |
3176 | segT segment ATTRIBUTE_UNUSED, | |
3177 | fragS *fragP) | |
886a2506 | 3178 | { |
4670103e CZ |
3179 | const relax_typeS *table_entry; |
3180 | char *dest; | |
3181 | const struct arc_opcode *opcode; | |
3182 | struct arc_insn insn; | |
3183 | int size, fix; | |
3184 | struct arc_relax_type *relax_arg = &fragP->tc_frag_data; | |
886a2506 | 3185 | |
4670103e CZ |
3186 | fix = (fragP->fr_fix < 0 ? 0 : fragP->fr_fix); |
3187 | dest = fragP->fr_literal + fix; | |
3188 | table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype; | |
886a2506 | 3189 | |
9e32d9ae AB |
3190 | pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, " |
3191 | "var: %"BFD_VMA_FMT"d\n", | |
4670103e CZ |
3192 | fragP->fr_file, fragP->fr_line, |
3193 | fragP->fr_subtype, fix, fragP->fr_var); | |
886a2506 | 3194 | |
4670103e CZ |
3195 | if (fragP->fr_subtype <= 0 |
3196 | && fragP->fr_subtype >= arc_num_relax_opcodes) | |
3197 | as_fatal (_("no relaxation found for this instruction.")); | |
886a2506 | 3198 | |
4670103e | 3199 | opcode = &arc_relax_opcodes[fragP->fr_subtype]; |
886a2506 | 3200 | |
4670103e CZ |
3201 | assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags, |
3202 | relax_arg->nflg, &insn); | |
886a2506 | 3203 | |
4670103e | 3204 | apply_fixups (&insn, fragP, fix); |
886a2506 | 3205 | |
91fdca6f | 3206 | size = insn.len + (insn.has_limm ? 4 : 0); |
4670103e CZ |
3207 | gas_assert (table_entry->rlx_length == size); |
3208 | emit_insn0 (&insn, dest, TRUE); | |
886a2506 | 3209 | |
4670103e CZ |
3210 | fragP->fr_fix += table_entry->rlx_length; |
3211 | fragP->fr_var = 0; | |
886a2506 NC |
3212 | } |
3213 | ||
4670103e CZ |
3214 | /* We have no need to default values of symbols. We could catch |
3215 | register names here, but that is handled by inserting them all in | |
3216 | the symbol table to begin with. */ | |
886a2506 | 3217 | |
4670103e CZ |
3218 | symbolS * |
3219 | md_undefined_symbol (char *name) | |
886a2506 | 3220 | { |
4670103e CZ |
3221 | /* The arc abi demands that a GOT[0] should be referencible as |
3222 | [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a | |
3223 | GOTPC reference to _GLOBAL_OFFSET_TABLE_. */ | |
3224 | if (((*name == '_') | |
3225 | && (*(name+1) == 'G') | |
3226 | && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)) | |
3227 | || ((*name == '_') | |
3228 | && (*(name+1) == 'D') | |
3229 | && (strcmp (name, DYNAMIC_STRUCT_NAME) == 0))) | |
886a2506 | 3230 | { |
4670103e CZ |
3231 | if (!GOT_symbol) |
3232 | { | |
3233 | if (symbol_find (name)) | |
3234 | as_bad ("GOT already in symbol table"); | |
3235 | ||
3236 | GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section, | |
3237 | (valueT) 0, &zero_address_frag); | |
3238 | }; | |
3239 | return GOT_symbol; | |
886a2506 | 3240 | } |
4670103e | 3241 | return NULL; |
886a2506 NC |
3242 | } |
3243 | ||
4670103e CZ |
3244 | /* Turn a string in input_line_pointer into a floating point constant |
3245 | of type type, and store the appropriate bytes in *litP. The number | |
3246 | of LITTLENUMS emitted is stored in *sizeP. An error message is | |
3247 | returned, or NULL on OK. */ | |
886a2506 | 3248 | |
6d4af3c2 | 3249 | const char * |
4670103e | 3250 | md_atof (int type, char *litP, int *sizeP) |
886a2506 | 3251 | { |
4670103e CZ |
3252 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
3253 | } | |
886a2506 | 3254 | |
4670103e CZ |
3255 | /* Called for any expression that can not be recognized. When the |
3256 | function is called, `input_line_pointer' will point to the start of | |
3257 | the expression. */ | |
886a2506 | 3258 | |
4670103e CZ |
3259 | void |
3260 | md_operand (expressionS *expressionP ATTRIBUTE_UNUSED) | |
3261 | { | |
3262 | char *p = input_line_pointer; | |
3263 | if (*p == '@') | |
886a2506 | 3264 | { |
4670103e CZ |
3265 | input_line_pointer++; |
3266 | expressionP->X_op = O_symbol; | |
3267 | expression (expressionP); | |
3268 | } | |
3269 | } | |
886a2506 | 3270 | |
4670103e CZ |
3271 | /* This function is called from the function 'expression', it attempts |
3272 | to parse special names (in our case register names). It fills in | |
3273 | the expression with the identified register. It returns TRUE if | |
3274 | it is a register and FALSE otherwise. */ | |
886a2506 | 3275 | |
4670103e CZ |
3276 | bfd_boolean |
3277 | arc_parse_name (const char *name, | |
3278 | struct expressionS *e) | |
3279 | { | |
3280 | struct symbol *sym; | |
886a2506 | 3281 | |
4670103e CZ |
3282 | if (!assembling_insn) |
3283 | return FALSE; | |
886a2506 | 3284 | |
08ec958f | 3285 | if (e->X_op == O_symbol) |
4670103e | 3286 | return FALSE; |
886a2506 | 3287 | |
4670103e CZ |
3288 | sym = hash_find (arc_reg_hash, name); |
3289 | if (sym) | |
3290 | { | |
3291 | e->X_op = O_register; | |
3292 | e->X_add_number = S_GET_VALUE (sym); | |
3293 | return TRUE; | |
3294 | } | |
db18dbab GM |
3295 | |
3296 | sym = hash_find (arc_addrtype_hash, name); | |
3297 | if (sym) | |
3298 | { | |
3299 | e->X_op = O_addrtype; | |
3300 | e->X_add_number = S_GET_VALUE (sym); | |
3301 | return TRUE; | |
3302 | } | |
3303 | ||
4670103e CZ |
3304 | return FALSE; |
3305 | } | |
886a2506 | 3306 | |
4670103e CZ |
3307 | /* md_parse_option |
3308 | Invocation line includes a switch not recognized by the base assembler. | |
3309 | See if it's a processor-specific option. | |
886a2506 | 3310 | |
4670103e | 3311 | New options (supported) are: |
886a2506 | 3312 | |
4670103e CZ |
3313 | -mcpu=<cpu name> Assemble for selected processor |
3314 | -EB/-mbig-endian Big-endian | |
3315 | -EL/-mlittle-endian Little-endian | |
3316 | -mrelax Enable relaxation | |
886a2506 | 3317 | |
4670103e | 3318 | The following CPU names are recognized: |
ce440d63 | 3319 | arc600, arc700, arcem, archs, nps400. */ |
886a2506 | 3320 | |
4670103e | 3321 | int |
17b9d67d | 3322 | md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED) |
4670103e | 3323 | { |
4670103e CZ |
3324 | switch (c) |
3325 | { | |
3326 | case OPTION_ARC600: | |
3327 | case OPTION_ARC601: | |
3328 | return md_parse_option (OPTION_MCPU, "arc600"); | |
886a2506 | 3329 | |
4670103e CZ |
3330 | case OPTION_ARC700: |
3331 | return md_parse_option (OPTION_MCPU, "arc700"); | |
886a2506 | 3332 | |
4670103e CZ |
3333 | case OPTION_ARCEM: |
3334 | return md_parse_option (OPTION_MCPU, "arcem"); | |
886a2506 | 3335 | |
4670103e CZ |
3336 | case OPTION_ARCHS: |
3337 | return md_parse_option (OPTION_MCPU, "archs"); | |
886a2506 | 3338 | |
4670103e CZ |
3339 | case OPTION_MCPU: |
3340 | { | |
bb65a718 | 3341 | arc_select_cpu (arg, MACH_SELECTION_FROM_COMMAND_LINE); |
4670103e CZ |
3342 | break; |
3343 | } | |
886a2506 | 3344 | |
4670103e CZ |
3345 | case OPTION_EB: |
3346 | arc_target_format = "elf32-bigarc"; | |
3347 | byte_order = BIG_ENDIAN; | |
3348 | break; | |
886a2506 | 3349 | |
4670103e CZ |
3350 | case OPTION_EL: |
3351 | arc_target_format = "elf32-littlearc"; | |
3352 | byte_order = LITTLE_ENDIAN; | |
3353 | break; | |
886a2506 | 3354 | |
4670103e | 3355 | case OPTION_CD: |
bb050a69 CZ |
3356 | selected_cpu.features |= ARC_CD; |
3357 | arc_check_feature (); | |
4670103e | 3358 | break; |
886a2506 | 3359 | |
4670103e CZ |
3360 | case OPTION_RELAX: |
3361 | relaxation_state = 1; | |
3362 | break; | |
886a2506 | 3363 | |
bdd582db | 3364 | case OPTION_NPS400: |
bb65a718 | 3365 | selected_cpu.features |= ARC_NPS400; |
bb050a69 | 3366 | arc_check_feature (); |
ce440d63 | 3367 | break; |
bdd582db | 3368 | |
ce440d63 | 3369 | case OPTION_SPFP: |
bb65a718 | 3370 | selected_cpu.features |= ARC_SPFP; |
bb050a69 | 3371 | arc_check_feature (); |
ce440d63 GM |
3372 | break; |
3373 | ||
3374 | case OPTION_DPFP: | |
bb65a718 | 3375 | selected_cpu.features |= ARC_DPFP; |
bb050a69 | 3376 | arc_check_feature (); |
ce440d63 GM |
3377 | break; |
3378 | ||
3379 | case OPTION_FPUDA: | |
bb050a69 CZ |
3380 | selected_cpu.features |= ARC_FPUDA; |
3381 | arc_check_feature (); | |
ce440d63 GM |
3382 | break; |
3383 | ||
3384 | /* Dummy options are accepted but have no effect. */ | |
4670103e CZ |
3385 | case OPTION_USER_MODE: |
3386 | case OPTION_LD_EXT_MASK: | |
3387 | case OPTION_SWAP: | |
3388 | case OPTION_NORM: | |
3389 | case OPTION_BARREL_SHIFT: | |
3390 | case OPTION_MIN_MAX: | |
3391 | case OPTION_NO_MPY: | |
3392 | case OPTION_EA: | |
3393 | case OPTION_MUL64: | |
3394 | case OPTION_SIMD: | |
4670103e CZ |
3395 | case OPTION_XMAC_D16: |
3396 | case OPTION_XMAC_24: | |
3397 | case OPTION_DSP_PACKA: | |
3398 | case OPTION_CRC: | |
3399 | case OPTION_DVBF: | |
3400 | case OPTION_TELEPHONY: | |
3401 | case OPTION_XYMEMORY: | |
3402 | case OPTION_LOCK: | |
3403 | case OPTION_SWAPE: | |
3404 | case OPTION_RTSC: | |
8ddf6b2a CZ |
3405 | break; |
3406 | ||
4670103e CZ |
3407 | default: |
3408 | return 0; | |
3409 | } | |
886a2506 | 3410 | |
4670103e CZ |
3411 | return 1; |
3412 | } | |
886a2506 | 3413 | |
4670103e CZ |
3414 | void |
3415 | md_show_usage (FILE *stream) | |
3416 | { | |
3417 | fprintf (stream, _("ARC-specific assembler options:\n")); | |
886a2506 | 3418 | |
9004b6bd AB |
3419 | fprintf (stream, " -mcpu=<cpu name>\t assemble for CPU <cpu name> " |
3420 | "(default: %s)\n", TARGET_WITH_CPU); | |
bdd582db GM |
3421 | fprintf (stream, " -mcpu=nps400\t\t same as -mcpu=arc700 -mnps400\n"); |
3422 | fprintf (stream, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n"); | |
3423 | fprintf (stream, " -mA7/-mARC700\t\t same as -mcpu=arc700\n"); | |
3424 | fprintf (stream, " -mEM\t\t\t same as -mcpu=arcem\n"); | |
3425 | fprintf (stream, " -mHS\t\t\t same as -mcpu=archs\n"); | |
3426 | ||
3427 | fprintf (stream, " -mnps400\t\t enable NPS-400 extended instructions\n"); | |
3428 | fprintf (stream, " -mspfp\t\t enable single-precision floating point instructions\n"); | |
3429 | fprintf (stream, " -mdpfp\t\t enable double-precision floating point instructions\n"); | |
3430 | fprintf (stream, " -mfpuda\t\t enable double-precision assist floating " | |
3431 | "point\n\t\t\t instructions for ARC EM\n"); | |
3432 | ||
4670103e CZ |
3433 | fprintf (stream, |
3434 | " -mcode-density\t enable code density option for ARC EM\n"); | |
3435 | ||
3436 | fprintf (stream, _("\ | |
3437 | -EB assemble code for a big-endian cpu\n")); | |
3438 | fprintf (stream, _("\ | |
3439 | -EL assemble code for a little-endian cpu\n")); | |
3440 | fprintf (stream, _("\ | |
bdd582db GM |
3441 | -mrelax enable relaxation\n")); |
3442 | ||
3443 | fprintf (stream, _("The following ARC-specific assembler options are " | |
3444 | "deprecated and are accepted\nfor compatibility only:\n")); | |
3445 | ||
3446 | fprintf (stream, _(" -mEA\n" | |
3447 | " -mbarrel-shifter\n" | |
3448 | " -mbarrel_shifter\n" | |
3449 | " -mcrc\n" | |
3450 | " -mdsp-packa\n" | |
3451 | " -mdsp_packa\n" | |
3452 | " -mdvbf\n" | |
3453 | " -mld-extension-reg-mask\n" | |
3454 | " -mlock\n" | |
3455 | " -mmac-24\n" | |
3456 | " -mmac-d16\n" | |
3457 | " -mmac_24\n" | |
3458 | " -mmac_d16\n" | |
3459 | " -mmin-max\n" | |
3460 | " -mmin_max\n" | |
3461 | " -mmul64\n" | |
3462 | " -mno-mpy\n" | |
3463 | " -mnorm\n" | |
3464 | " -mrtsc\n" | |
3465 | " -msimd\n" | |
3466 | " -mswap\n" | |
3467 | " -mswape\n" | |
3468 | " -mtelephony\n" | |
3469 | " -muser-mode-only\n" | |
3470 | " -mxy\n")); | |
886a2506 NC |
3471 | } |
3472 | ||
3473 | /* Find the proper relocation for the given opcode. */ | |
3474 | ||
3475 | static extended_bfd_reloc_code_real_type | |
3476 | find_reloc (const char *name, | |
3477 | const char *opcodename, | |
3478 | const struct arc_flags *pflags, | |
3479 | int nflg, | |
3480 | extended_bfd_reloc_code_real_type reloc) | |
3481 | { | |
3482 | unsigned int i; | |
3483 | int j; | |
24b368f8 | 3484 | bfd_boolean found_flag, tmp; |
886a2506 NC |
3485 | extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED; |
3486 | ||
3487 | for (i = 0; i < arc_num_equiv_tab; i++) | |
3488 | { | |
3489 | const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i]; | |
3490 | ||
3491 | /* Find the entry. */ | |
3492 | if (strcmp (name, r->name)) | |
3493 | continue; | |
3494 | if (r->mnemonic && (strcmp (r->mnemonic, opcodename))) | |
3495 | continue; | |
24b368f8 | 3496 | if (r->flags[0]) |
886a2506 NC |
3497 | { |
3498 | if (!nflg) | |
3499 | continue; | |
3500 | found_flag = FALSE; | |
24b368f8 CZ |
3501 | unsigned * psflg = (unsigned *)r->flags; |
3502 | do | |
3503 | { | |
3504 | tmp = FALSE; | |
3505 | for (j = 0; j < nflg; j++) | |
3506 | if (!strcmp (pflags[j].name, | |
3507 | arc_flag_operands[*psflg].name)) | |
3508 | { | |
3509 | tmp = TRUE; | |
3510 | break; | |
3511 | } | |
3512 | if (!tmp) | |
3513 | { | |
3514 | found_flag = FALSE; | |
3515 | break; | |
3516 | } | |
3517 | else | |
3518 | { | |
3519 | found_flag = TRUE; | |
3520 | } | |
3521 | ++ psflg; | |
3522 | } while (*psflg); | |
3523 | ||
886a2506 NC |
3524 | if (!found_flag) |
3525 | continue; | |
3526 | } | |
3527 | ||
3528 | if (reloc != r->oldreloc) | |
3529 | continue; | |
3530 | /* Found it. */ | |
3531 | ret = r->newreloc; | |
3532 | break; | |
3533 | } | |
3534 | ||
3535 | if (ret == BFD_RELOC_UNUSED) | |
3536 | as_bad (_("Unable to find %s relocation for instruction %s"), | |
3537 | name, opcodename); | |
3538 | return ret; | |
3539 | } | |
3540 | ||
4670103e CZ |
3541 | /* All the symbol types that are allowed to be used for |
3542 | relaxation. */ | |
3543 | ||
3544 | static bfd_boolean | |
3545 | may_relax_expr (expressionS tok) | |
3546 | { | |
3547 | /* Check if we have unrelaxable relocs. */ | |
3548 | switch (tok.X_md) | |
3549 | { | |
3550 | default: | |
3551 | break; | |
3552 | case O_plt: | |
3553 | return FALSE; | |
3554 | } | |
3555 | ||
3556 | switch (tok.X_op) | |
3557 | { | |
3558 | case O_symbol: | |
3559 | case O_multiply: | |
3560 | case O_divide: | |
3561 | case O_modulus: | |
3562 | case O_add: | |
3563 | case O_subtract: | |
3564 | break; | |
3565 | ||
3566 | default: | |
3567 | return FALSE; | |
3568 | } | |
3569 | return TRUE; | |
3570 | } | |
3571 | ||
3572 | /* Checks if flags are in line with relaxable insn. */ | |
3573 | ||
3574 | static bfd_boolean | |
3575 | relaxable_flag (const struct arc_relaxable_ins *ins, | |
3576 | const struct arc_flags *pflags, | |
3577 | int nflgs) | |
3578 | { | |
3579 | unsigned flag_class, | |
3580 | flag, | |
3581 | flag_class_idx = 0, | |
3582 | flag_idx = 0; | |
3583 | ||
3584 | const struct arc_flag_operand *flag_opand; | |
3585 | int i, counttrue = 0; | |
3586 | ||
3587 | /* Iterate through flags classes. */ | |
3588 | while ((flag_class = ins->flag_classes[flag_class_idx]) != 0) | |
3589 | { | |
3590 | /* Iterate through flags in flag class. */ | |
3591 | while ((flag = arc_flag_classes[flag_class].flags[flag_idx]) | |
3592 | != 0) | |
3593 | { | |
3594 | flag_opand = &arc_flag_operands[flag]; | |
3595 | /* Iterate through flags in ins to compare. */ | |
3596 | for (i = 0; i < nflgs; ++i) | |
3597 | { | |
3598 | if (strcmp (flag_opand->name, pflags[i].name) == 0) | |
3599 | ++counttrue; | |
3600 | } | |
3601 | ||
3602 | ++flag_idx; | |
3603 | } | |
3604 | ||
3605 | ++flag_class_idx; | |
3606 | flag_idx = 0; | |
3607 | } | |
3608 | ||
3609 | /* If counttrue == nflgs, then all flags have been found. */ | |
3610 | return (counttrue == nflgs ? TRUE : FALSE); | |
3611 | } | |
3612 | ||
3613 | /* Checks if operands are in line with relaxable insn. */ | |
3614 | ||
3615 | static bfd_boolean | |
3616 | relaxable_operand (const struct arc_relaxable_ins *ins, | |
3617 | const expressionS *tok, | |
3618 | int ntok) | |
3619 | { | |
3620 | const enum rlx_operand_type *operand = &ins->operands[0]; | |
3621 | int i = 0; | |
3622 | ||
3623 | while (*operand != EMPTY) | |
3624 | { | |
3625 | const expressionS *epr = &tok[i]; | |
3626 | ||
3627 | if (i != 0 && i >= ntok) | |
3628 | return FALSE; | |
3629 | ||
3630 | switch (*operand) | |
3631 | { | |
3632 | case IMMEDIATE: | |
3633 | if (!(epr->X_op == O_multiply | |
3634 | || epr->X_op == O_divide | |
3635 | || epr->X_op == O_modulus | |
3636 | || epr->X_op == O_add | |
3637 | || epr->X_op == O_subtract | |
3638 | || epr->X_op == O_symbol)) | |
3639 | return FALSE; | |
3640 | break; | |
3641 | ||
3642 | case REGISTER_DUP: | |
3643 | if ((i <= 0) | |
3644 | || (epr->X_add_number != tok[i - 1].X_add_number)) | |
3645 | return FALSE; | |
3646 | /* Fall through. */ | |
3647 | case REGISTER: | |
3648 | if (epr->X_op != O_register) | |
3649 | return FALSE; | |
3650 | break; | |
3651 | ||
3652 | case REGISTER_S: | |
3653 | if (epr->X_op != O_register) | |
3654 | return FALSE; | |
3655 | ||
3656 | switch (epr->X_add_number) | |
3657 | { | |
3658 | case 0: case 1: case 2: case 3: | |
3659 | case 12: case 13: case 14: case 15: | |
3660 | break; | |
3661 | default: | |
3662 | return FALSE; | |
3663 | } | |
3664 | break; | |
3665 | ||
3666 | case REGISTER_NO_GP: | |
3667 | if ((epr->X_op != O_register) | |
3668 | || (epr->X_add_number == 26)) /* 26 is the gp register. */ | |
3669 | return FALSE; | |
3670 | break; | |
3671 | ||
3672 | case BRACKET: | |
3673 | if (epr->X_op != O_bracket) | |
3674 | return FALSE; | |
3675 | break; | |
3676 | ||
3677 | default: | |
3678 | /* Don't understand, bail out. */ | |
3679 | return FALSE; | |
3680 | break; | |
3681 | } | |
3682 | ||
3683 | ++i; | |
3684 | operand = &ins->operands[i]; | |
3685 | } | |
3686 | ||
3687 | return (i == ntok ? TRUE : FALSE); | |
3688 | } | |
3689 | ||
3690 | /* Return TRUE if this OPDCODE is a candidate for relaxation. */ | |
3691 | ||
3692 | static bfd_boolean | |
3693 | relax_insn_p (const struct arc_opcode *opcode, | |
3694 | const expressionS *tok, | |
3695 | int ntok, | |
3696 | const struct arc_flags *pflags, | |
3697 | int nflg) | |
3698 | { | |
3699 | unsigned i; | |
3700 | bfd_boolean rv = FALSE; | |
3701 | ||
3702 | /* Check the relaxation table. */ | |
3703 | for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i) | |
3704 | { | |
3705 | const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i]; | |
3706 | ||
3707 | if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0) | |
3708 | && may_relax_expr (tok[arc_rlx_ins->opcheckidx]) | |
3709 | && relaxable_operand (arc_rlx_ins, tok, ntok) | |
3710 | && relaxable_flag (arc_rlx_ins, pflags, nflg)) | |
3711 | { | |
3712 | rv = TRUE; | |
3713 | frag_now->fr_subtype = arc_relaxable_insns[i].subtype; | |
3714 | memcpy (&frag_now->tc_frag_data.tok, tok, | |
3715 | sizeof (expressionS) * ntok); | |
3716 | memcpy (&frag_now->tc_frag_data.pflags, pflags, | |
3717 | sizeof (struct arc_flags) * nflg); | |
3718 | frag_now->tc_frag_data.nflg = nflg; | |
3719 | frag_now->tc_frag_data.ntok = ntok; | |
3720 | break; | |
3721 | } | |
3722 | } | |
3723 | ||
3724 | return rv; | |
3725 | } | |
3726 | ||
886a2506 NC |
3727 | /* Turn an opcode description and a set of arguments into |
3728 | an instruction and a fixup. */ | |
3729 | ||
3730 | static void | |
3731 | assemble_insn (const struct arc_opcode *opcode, | |
3732 | const expressionS *tok, | |
3733 | int ntok, | |
3734 | const struct arc_flags *pflags, | |
3735 | int nflg, | |
3736 | struct arc_insn *insn) | |
3737 | { | |
3738 | const expressionS *reloc_exp = NULL; | |
bdfe53e3 | 3739 | unsigned long long image; |
886a2506 NC |
3740 | const unsigned char *argidx; |
3741 | int i; | |
3742 | int tokidx = 0; | |
3743 | unsigned char pcrel = 0; | |
3744 | bfd_boolean needGOTSymbol; | |
3745 | bfd_boolean has_delay_slot = FALSE; | |
3746 | extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; | |
3747 | ||
3748 | memset (insn, 0, sizeof (*insn)); | |
3749 | image = opcode->opcode; | |
3750 | ||
bdfe53e3 | 3751 | pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n", |
886a2506 NC |
3752 | frag_now->fr_file, frag_now->fr_line, opcode->name, |
3753 | opcode->opcode); | |
3754 | ||
3755 | /* Handle operands. */ | |
3756 | for (argidx = opcode->operands; *argidx; ++argidx) | |
3757 | { | |
3758 | const struct arc_operand *operand = &arc_operands[*argidx]; | |
3759 | const expressionS *t = (const expressionS *) 0; | |
3760 | ||
db18dbab | 3761 | if (ARC_OPERAND_IS_FAKE (operand)) |
886a2506 NC |
3762 | continue; |
3763 | ||
3764 | if (operand->flags & ARC_OPERAND_DUPLICATE) | |
3765 | { | |
3766 | /* Duplicate operand, already inserted. */ | |
3767 | tokidx ++; | |
3768 | continue; | |
3769 | } | |
3770 | ||
3771 | if (tokidx >= ntok) | |
3772 | { | |
3773 | abort (); | |
3774 | } | |
3775 | else | |
3776 | t = &tok[tokidx++]; | |
3777 | ||
3778 | /* Regardless if we have a reloc or not mark the instruction | |
3779 | limm if it is the case. */ | |
3780 | if (operand->flags & ARC_OPERAND_LIMM) | |
3781 | insn->has_limm = TRUE; | |
3782 | ||
3783 | switch (t->X_op) | |
3784 | { | |
3785 | case O_register: | |
3786 | image = insert_operand (image, operand, regno (t->X_add_number), | |
3787 | NULL, 0); | |
3788 | break; | |
3789 | ||
3790 | case O_constant: | |
3791 | image = insert_operand (image, operand, t->X_add_number, NULL, 0); | |
3792 | reloc_exp = t; | |
3793 | if (operand->flags & ARC_OPERAND_LIMM) | |
3794 | insn->limm = t->X_add_number; | |
3795 | break; | |
3796 | ||
3797 | case O_bracket: | |
db18dbab GM |
3798 | case O_colon: |
3799 | case O_addrtype: | |
3800 | /* Ignore brackets, colons, and address types. */ | |
886a2506 NC |
3801 | break; |
3802 | ||
3803 | case O_absent: | |
3804 | gas_assert (operand->flags & ARC_OPERAND_IGNORE); | |
3805 | break; | |
3806 | ||
3807 | case O_subtract: | |
3808 | /* Maybe register range. */ | |
3809 | if ((t->X_add_number == 0) | |
3810 | && contains_register (t->X_add_symbol) | |
3811 | && contains_register (t->X_op_symbol)) | |
3812 | { | |
3813 | int regs; | |
3814 | ||
3815 | regs = get_register (t->X_add_symbol); | |
3816 | regs <<= 16; | |
3817 | regs |= get_register (t->X_op_symbol); | |
3818 | image = insert_operand (image, operand, regs, NULL, 0); | |
3819 | break; | |
3820 | } | |
1a0670f3 | 3821 | /* Fall through. */ |
886a2506 NC |
3822 | |
3823 | default: | |
3824 | /* This operand needs a relocation. */ | |
3825 | needGOTSymbol = FALSE; | |
3826 | ||
3827 | switch (t->X_md) | |
3828 | { | |
3829 | case O_plt: | |
c810e0b8 | 3830 | if (opcode->insn_class == JUMP) |
6ec1f282 CZ |
3831 | as_bad_where (frag_now->fr_file, frag_now->fr_line, |
3832 | _("Unable to use @plt relocatio for insn %s"), | |
3833 | opcode->name); | |
886a2506 NC |
3834 | needGOTSymbol = TRUE; |
3835 | reloc = find_reloc ("plt", opcode->name, | |
3836 | pflags, nflg, | |
3837 | operand->default_reloc); | |
3838 | break; | |
3839 | ||
3840 | case O_gotoff: | |
3841 | case O_gotpc: | |
3842 | needGOTSymbol = TRUE; | |
3843 | reloc = ARC_RELOC_TABLE (t->X_md)->reloc; | |
3844 | break; | |
3845 | case O_pcl: | |
3846 | reloc = ARC_RELOC_TABLE (t->X_md)->reloc; | |
06fe285f GM |
3847 | if (arc_opcode_len (opcode) == 2 |
3848 | || opcode->insn_class == JUMP) | |
886a2506 NC |
3849 | as_bad_where (frag_now->fr_file, frag_now->fr_line, |
3850 | _("Unable to use @pcl relocation for insn %s"), | |
3851 | opcode->name); | |
3852 | break; | |
3853 | case O_sda: | |
3854 | reloc = find_reloc ("sda", opcode->name, | |
3855 | pflags, nflg, | |
3856 | operand->default_reloc); | |
3857 | break; | |
3858 | case O_tlsgd: | |
3859 | case O_tlsie: | |
3860 | needGOTSymbol = TRUE; | |
3861 | /* Fall-through. */ | |
3862 | ||
3863 | case O_tpoff: | |
3864 | case O_dtpoff: | |
3865 | reloc = ARC_RELOC_TABLE (t->X_md)->reloc; | |
3866 | break; | |
3867 | ||
3868 | case O_tpoff9: /*FIXME! Check for the conditionality of | |
3869 | the insn. */ | |
3870 | case O_dtpoff9: /*FIXME! Check for the conditionality of | |
3871 | the insn. */ | |
3872 | as_bad (_("TLS_*_S9 relocs are not supported yet")); | |
3873 | break; | |
3874 | ||
3875 | default: | |
3876 | /* Just consider the default relocation. */ | |
3877 | reloc = operand->default_reloc; | |
3878 | break; | |
3879 | } | |
3880 | ||
3881 | if (needGOTSymbol && (GOT_symbol == NULL)) | |
3882 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
3883 | ||
3884 | reloc_exp = t; | |
3885 | ||
3886 | #if 0 | |
3887 | if (reloc > 0) | |
3888 | { | |
3889 | /* sanity checks. */ | |
3890 | reloc_howto_type *reloc_howto | |
3891 | = bfd_reloc_type_lookup (stdoutput, | |
3892 | (bfd_reloc_code_real_type) reloc); | |
3893 | unsigned reloc_bitsize = reloc_howto->bitsize; | |
3894 | if (reloc_howto->rightshift) | |
3895 | reloc_bitsize -= reloc_howto->rightshift; | |
3896 | if (reloc_bitsize != operand->bits) | |
3897 | { | |
3898 | as_bad (_("invalid relocation %s for field"), | |
3899 | bfd_get_reloc_code_name (reloc)); | |
3900 | return; | |
3901 | } | |
3902 | } | |
3903 | #endif | |
3904 | if (insn->nfixups >= MAX_INSN_FIXUPS) | |
3905 | as_fatal (_("too many fixups")); | |
3906 | ||
3907 | struct arc_fixup *fixup; | |
3908 | fixup = &insn->fixups[insn->nfixups++]; | |
3909 | fixup->exp = *t; | |
3910 | fixup->reloc = reloc; | |
3911 | pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0; | |
3912 | fixup->pcrel = pcrel; | |
3913 | fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ? | |
3914 | TRUE : FALSE; | |
3915 | break; | |
3916 | } | |
3917 | } | |
3918 | ||
3919 | /* Handle flags. */ | |
3920 | for (i = 0; i < nflg; i++) | |
3921 | { | |
f36e33da | 3922 | const struct arc_flag_operand *flg_operand = pflags[i].flgp; |
886a2506 NC |
3923 | |
3924 | /* Check if the instruction has a delay slot. */ | |
3925 | if (!strcmp (flg_operand->name, "d")) | |
3926 | has_delay_slot = TRUE; | |
3927 | ||
3928 | /* There is an exceptional case when we cannot insert a flag | |
3929 | just as it is. The .T flag must be handled in relation with | |
3930 | the relative address. */ | |
3931 | if (!strcmp (flg_operand->name, "t") | |
3932 | || !strcmp (flg_operand->name, "nt")) | |
3933 | { | |
3934 | unsigned bitYoperand = 0; | |
3935 | /* FIXME! move selection bbit/brcc in arc-opc.c. */ | |
3936 | if (!strcmp (flg_operand->name, "t")) | |
3937 | if (!strcmp (opcode->name, "bbit0") | |
3938 | || !strcmp (opcode->name, "bbit1")) | |
3939 | bitYoperand = arc_NToperand; | |
3940 | else | |
3941 | bitYoperand = arc_Toperand; | |
3942 | else | |
3943 | if (!strcmp (opcode->name, "bbit0") | |
3944 | || !strcmp (opcode->name, "bbit1")) | |
3945 | bitYoperand = arc_Toperand; | |
3946 | else | |
3947 | bitYoperand = arc_NToperand; | |
3948 | ||
3949 | gas_assert (reloc_exp != NULL); | |
3950 | if (reloc_exp->X_op == O_constant) | |
3951 | { | |
3952 | /* Check if we have a constant and solved it | |
3953 | immediately. */ | |
3954 | offsetT val = reloc_exp->X_add_number; | |
3955 | image |= insert_operand (image, &arc_operands[bitYoperand], | |
3956 | val, NULL, 0); | |
3957 | } | |
3958 | else | |
3959 | { | |
3960 | struct arc_fixup *fixup; | |
3961 | ||
3962 | if (insn->nfixups >= MAX_INSN_FIXUPS) | |
3963 | as_fatal (_("too many fixups")); | |
3964 | ||
3965 | fixup = &insn->fixups[insn->nfixups++]; | |
3966 | fixup->exp = *reloc_exp; | |
3967 | fixup->reloc = -bitYoperand; | |
3968 | fixup->pcrel = pcrel; | |
3969 | fixup->islong = FALSE; | |
3970 | } | |
3971 | } | |
3972 | else | |
3973 | image |= (flg_operand->code & ((1 << flg_operand->bits) - 1)) | |
3974 | << flg_operand->shift; | |
3975 | } | |
3976 | ||
4670103e CZ |
3977 | insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg); |
3978 | ||
91fdca6f | 3979 | /* Instruction length. */ |
06fe285f | 3980 | insn->len = arc_opcode_len (opcode); |
886a2506 NC |
3981 | |
3982 | insn->insn = image; | |
3983 | ||
3984 | /* Update last insn status. */ | |
3985 | arc_last_insns[1] = arc_last_insns[0]; | |
3986 | arc_last_insns[0].opcode = opcode; | |
3987 | arc_last_insns[0].has_limm = insn->has_limm; | |
3988 | arc_last_insns[0].has_delay_slot = has_delay_slot; | |
3989 | ||
3990 | /* Check if the current instruction is legally used. */ | |
3991 | if (arc_last_insns[1].has_delay_slot | |
3992 | && is_br_jmp_insn_p (arc_last_insns[0].opcode)) | |
3993 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
3994 | _("A jump/branch instruction in delay slot.")); | |
3995 | } | |
3996 | ||
886a2506 NC |
3997 | void |
3998 | arc_handle_align (fragS* fragP) | |
3999 | { | |
4000 | if ((fragP)->fr_type == rs_align_code) | |
4001 | { | |
4002 | char *dest = (fragP)->fr_literal + (fragP)->fr_fix; | |
4003 | valueT count = ((fragP)->fr_next->fr_address | |
4004 | - (fragP)->fr_address - (fragP)->fr_fix); | |
4005 | ||
4006 | (fragP)->fr_var = 2; | |
4007 | ||
4008 | if (count & 1)/* Padding in the gap till the next 2-byte | |
4009 | boundary with 0s. */ | |
4010 | { | |
4011 | (fragP)->fr_fix++; | |
4012 | *dest++ = 0; | |
4013 | } | |
4014 | /* Writing nop_s. */ | |
4015 | md_number_to_chars (dest, NOP_OPCODE_S, 2); | |
4016 | } | |
4017 | } | |
4018 | ||
4019 | /* Here we decide which fixups can be adjusted to make them relative | |
4020 | to the beginning of the section instead of the symbol. Basically | |
4021 | we need to make sure that the dynamic relocations are done | |
4022 | correctly, so in some cases we force the original symbol to be | |
4023 | used. */ | |
4024 | ||
4025 | int | |
4026 | tc_arc_fix_adjustable (fixS *fixP) | |
4027 | { | |
4028 | ||
4029 | /* Prevent all adjustments to global symbols. */ | |
4030 | if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
4031 | return 0; | |
4032 | if (S_IS_WEAK (fixP->fx_addsy)) | |
4033 | return 0; | |
4034 | ||
4035 | /* Adjust_reloc_syms doesn't know about the GOT. */ | |
4036 | switch (fixP->fx_r_type) | |
4037 | { | |
4038 | case BFD_RELOC_ARC_GOTPC32: | |
4039 | case BFD_RELOC_ARC_PLT32: | |
4040 | case BFD_RELOC_ARC_S25H_PCREL_PLT: | |
4041 | case BFD_RELOC_ARC_S21H_PCREL_PLT: | |
4042 | case BFD_RELOC_ARC_S25W_PCREL_PLT: | |
4043 | case BFD_RELOC_ARC_S21W_PCREL_PLT: | |
4044 | return 0; | |
4045 | ||
4046 | default: | |
4047 | break; | |
4048 | } | |
4049 | ||
841fdfcd | 4050 | return 1; |
886a2506 NC |
4051 | } |
4052 | ||
4053 | /* Compute the reloc type of an expression EXP. */ | |
4054 | ||
4055 | static void | |
4056 | arc_check_reloc (expressionS *exp, | |
4057 | bfd_reloc_code_real_type *r_type_p) | |
4058 | { | |
4059 | if (*r_type_p == BFD_RELOC_32 | |
4060 | && exp->X_op == O_subtract | |
4061 | && exp->X_op_symbol != NULL | |
4062 | && exp->X_op_symbol->bsym->section == now_seg) | |
6f4b1afc | 4063 | *r_type_p = BFD_RELOC_ARC_32_PCREL; |
886a2506 NC |
4064 | } |
4065 | ||
4066 | ||
4067 | /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */ | |
4068 | ||
4069 | void | |
4070 | arc_cons_fix_new (fragS *frag, | |
4071 | int off, | |
4072 | int size, | |
4073 | expressionS *exp, | |
4074 | bfd_reloc_code_real_type r_type) | |
4075 | { | |
4076 | r_type = BFD_RELOC_UNUSED; | |
4077 | ||
4078 | switch (size) | |
4079 | { | |
4080 | case 1: | |
4081 | r_type = BFD_RELOC_8; | |
4082 | break; | |
4083 | ||
4084 | case 2: | |
4085 | r_type = BFD_RELOC_16; | |
4086 | break; | |
4087 | ||
4088 | case 3: | |
4089 | r_type = BFD_RELOC_24; | |
4090 | break; | |
4091 | ||
4092 | case 4: | |
4093 | r_type = BFD_RELOC_32; | |
4094 | arc_check_reloc (exp, &r_type); | |
4095 | break; | |
4096 | ||
4097 | case 8: | |
4098 | r_type = BFD_RELOC_64; | |
4099 | break; | |
4100 | ||
4101 | default: | |
4102 | as_bad (_("unsupported BFD relocation size %u"), size); | |
4103 | r_type = BFD_RELOC_UNUSED; | |
4104 | } | |
4105 | ||
4106 | fix_new_exp (frag, off, size, exp, 0, r_type); | |
4107 | } | |
4108 | ||
4109 | /* The actual routine that checks the ZOL conditions. */ | |
4110 | ||
4111 | static void | |
4112 | check_zol (symbolS *s) | |
4113 | { | |
bb65a718 | 4114 | switch (selected_cpu.mach) |
886a2506 NC |
4115 | { |
4116 | case bfd_mach_arc_arcv2: | |
bb65a718 | 4117 | if (selected_cpu.flags & ARC_OPCODE_ARCv2EM) |
886a2506 NC |
4118 | return; |
4119 | ||
4120 | if (is_br_jmp_insn_p (arc_last_insns[0].opcode) | |
4121 | || arc_last_insns[1].has_delay_slot) | |
4122 | as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"), | |
4123 | S_GET_NAME (s)); | |
4124 | ||
4125 | break; | |
4126 | case bfd_mach_arc_arc600: | |
4127 | ||
4128 | if (is_kernel_insn_p (arc_last_insns[0].opcode)) | |
4129 | as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"), | |
4130 | S_GET_NAME (s)); | |
4131 | ||
4132 | if (arc_last_insns[0].has_limm | |
4133 | && is_br_jmp_insn_p (arc_last_insns[0].opcode)) | |
4134 | as_bad (_("A jump instruction with long immediate detected at the \ | |
4135 | end of the ZOL label @%s"), S_GET_NAME (s)); | |
4136 | ||
4137 | /* Fall through. */ | |
4138 | case bfd_mach_arc_arc700: | |
4139 | if (arc_last_insns[0].has_delay_slot) | |
4140 | as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"), | |
4141 | S_GET_NAME (s)); | |
4142 | ||
4143 | break; | |
4144 | default: | |
4145 | break; | |
4146 | } | |
4147 | } | |
4148 | ||
4149 | /* If ZOL end check the last two instruction for illegals. */ | |
4150 | void | |
4151 | arc_frob_label (symbolS * sym) | |
4152 | { | |
4153 | if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL) | |
4154 | check_zol (sym); | |
4155 | ||
4156 | dwarf2_emit_label (sym); | |
ea1562b3 | 4157 | } |
4670103e CZ |
4158 | |
4159 | /* Used because generic relaxation assumes a pc-rel value whilst we | |
4160 | also relax instructions that use an absolute value resolved out of | |
4161 | relative values (if that makes any sense). An example: 'add r1, | |
4162 | r2, @.L2 - .' The symbols . and @.L2 are relative to the section | |
4163 | but if they're in the same section we can subtract the section | |
4164 | offset relocation which ends up in a resolved value. So if @.L2 is | |
4165 | .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 - | |
4166 | .text + 0x40 = 0x10. */ | |
4167 | int | |
4168 | arc_pcrel_adjust (fragS *fragP) | |
4169 | { | |
4170 | if (!fragP->tc_frag_data.pcrel) | |
4171 | return fragP->fr_address + fragP->fr_fix; | |
4172 | ||
4173 | return 0; | |
4174 | } | |
726c18e1 CZ |
4175 | |
4176 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
4177 | ||
4178 | void | |
4179 | tc_arc_frame_initial_instructions (void) | |
4180 | { | |
4181 | /* Stack pointer is register 28. */ | |
45a54ee5 | 4182 | cfi_add_CFA_def_cfa (28, 0); |
726c18e1 CZ |
4183 | } |
4184 | ||
4185 | int | |
4186 | tc_arc_regname_to_dw2regnum (char *regname) | |
4187 | { | |
4188 | struct symbol *sym; | |
4189 | ||
4190 | sym = hash_find (arc_reg_hash, regname); | |
4191 | if (sym) | |
4192 | return S_GET_VALUE (sym); | |
4193 | ||
4194 | return -1; | |
4195 | } | |
37ab9779 CZ |
4196 | |
4197 | /* Adjust the symbol table. Delete found AUX register symbols. */ | |
4198 | ||
4199 | void | |
4200 | arc_adjust_symtab (void) | |
4201 | { | |
4202 | symbolS * sym; | |
4203 | ||
4204 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) | |
4205 | { | |
4206 | /* I've created a symbol during parsing process. Now, remove | |
4207 | the symbol as it is found to be an AUX register. */ | |
4208 | if (ARC_GET_FLAG (sym) & ARC_FLAG_AUX) | |
4209 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
4210 | } | |
4211 | ||
4212 | /* Now do generic ELF adjustments. */ | |
4213 | elf_adjust_symtab (); | |
4214 | } | |
b99747ae CZ |
4215 | |
4216 | static void | |
4217 | tokenize_extinsn (extInstruction_t *einsn) | |
4218 | { | |
4219 | char *p, c; | |
4220 | char *insn_name; | |
4221 | unsigned char major_opcode; | |
4222 | unsigned char sub_opcode; | |
4223 | unsigned char syntax_class = 0; | |
4224 | unsigned char syntax_class_modifiers = 0; | |
4225 | unsigned char suffix_class = 0; | |
4226 | unsigned int i; | |
4227 | ||
4228 | SKIP_WHITESPACE (); | |
4229 | ||
4230 | /* 1st: get instruction name. */ | |
4231 | p = input_line_pointer; | |
4232 | c = get_symbol_name (&p); | |
4233 | ||
4234 | insn_name = xstrdup (p); | |
4235 | restore_line_pointer (c); | |
4236 | ||
4237 | /* 2nd: get major opcode. */ | |
4238 | if (*input_line_pointer != ',') | |
4239 | { | |
4240 | as_bad (_("expected comma after instruction name")); | |
4241 | ignore_rest_of_line (); | |
4242 | return; | |
4243 | } | |
4244 | input_line_pointer++; | |
4245 | major_opcode = get_absolute_expression (); | |
4246 | ||
4247 | /* 3rd: get sub-opcode. */ | |
4248 | SKIP_WHITESPACE (); | |
4249 | ||
4250 | if (*input_line_pointer != ',') | |
4251 | { | |
4252 | as_bad (_("expected comma after major opcode")); | |
4253 | ignore_rest_of_line (); | |
4254 | return; | |
4255 | } | |
4256 | input_line_pointer++; | |
4257 | sub_opcode = get_absolute_expression (); | |
4258 | ||
4259 | /* 4th: get suffix class. */ | |
4260 | SKIP_WHITESPACE (); | |
4261 | ||
4262 | if (*input_line_pointer != ',') | |
4263 | { | |
4264 | as_bad ("expected comma after sub opcode"); | |
4265 | ignore_rest_of_line (); | |
4266 | return; | |
4267 | } | |
4268 | input_line_pointer++; | |
4269 | ||
4270 | while (1) | |
4271 | { | |
4272 | SKIP_WHITESPACE (); | |
4273 | ||
4274 | for (i = 0; i < ARRAY_SIZE (suffixclass); i++) | |
4275 | { | |
4276 | if (!strncmp (suffixclass[i].name, input_line_pointer, | |
4277 | suffixclass[i].len)) | |
4278 | { | |
c810e0b8 | 4279 | suffix_class |= suffixclass[i].attr_class; |
b99747ae CZ |
4280 | input_line_pointer += suffixclass[i].len; |
4281 | break; | |
4282 | } | |
4283 | } | |
4284 | ||
4285 | if (i == ARRAY_SIZE (suffixclass)) | |
4286 | { | |
4287 | as_bad ("invalid suffix class"); | |
4288 | ignore_rest_of_line (); | |
4289 | return; | |
4290 | } | |
4291 | ||
4292 | SKIP_WHITESPACE (); | |
4293 | ||
4294 | if (*input_line_pointer == '|') | |
4295 | input_line_pointer++; | |
4296 | else | |
4297 | break; | |
4298 | } | |
4299 | ||
4300 | /* 5th: get syntax class and syntax class modifiers. */ | |
4301 | if (*input_line_pointer != ',') | |
4302 | { | |
4303 | as_bad ("expected comma after suffix class"); | |
4304 | ignore_rest_of_line (); | |
4305 | return; | |
4306 | } | |
4307 | input_line_pointer++; | |
4308 | ||
4309 | while (1) | |
4310 | { | |
4311 | SKIP_WHITESPACE (); | |
4312 | ||
4313 | for (i = 0; i < ARRAY_SIZE (syntaxclassmod); i++) | |
4314 | { | |
4315 | if (!strncmp (syntaxclassmod[i].name, | |
4316 | input_line_pointer, | |
4317 | syntaxclassmod[i].len)) | |
4318 | { | |
c810e0b8 | 4319 | syntax_class_modifiers |= syntaxclassmod[i].attr_class; |
b99747ae CZ |
4320 | input_line_pointer += syntaxclassmod[i].len; |
4321 | break; | |
4322 | } | |
4323 | } | |
4324 | ||
4325 | if (i == ARRAY_SIZE (syntaxclassmod)) | |
4326 | { | |
4327 | for (i = 0; i < ARRAY_SIZE (syntaxclass); i++) | |
4328 | { | |
4329 | if (!strncmp (syntaxclass[i].name, | |
4330 | input_line_pointer, | |
4331 | syntaxclass[i].len)) | |
4332 | { | |
c810e0b8 | 4333 | syntax_class |= syntaxclass[i].attr_class; |
b99747ae CZ |
4334 | input_line_pointer += syntaxclass[i].len; |
4335 | break; | |
4336 | } | |
4337 | } | |
4338 | ||
4339 | if (i == ARRAY_SIZE (syntaxclass)) | |
4340 | { | |
4341 | as_bad ("missing syntax class"); | |
4342 | ignore_rest_of_line (); | |
4343 | return; | |
4344 | } | |
4345 | } | |
4346 | ||
4347 | SKIP_WHITESPACE (); | |
4348 | ||
4349 | if (*input_line_pointer == '|') | |
4350 | input_line_pointer++; | |
4351 | else | |
4352 | break; | |
4353 | } | |
4354 | ||
4355 | demand_empty_rest_of_line (); | |
4356 | ||
4357 | einsn->name = insn_name; | |
4358 | einsn->major = major_opcode; | |
4359 | einsn->minor = sub_opcode; | |
4360 | einsn->syntax = syntax_class; | |
4361 | einsn->modsyn = syntax_class_modifiers; | |
4362 | einsn->suffix = suffix_class; | |
4363 | einsn->flags = syntax_class | |
4364 | | (syntax_class_modifiers & ARC_OP1_IMM_IMPLIED ? 0x10 : 0); | |
4365 | } | |
4366 | ||
4367 | /* Generate an extension section. */ | |
4368 | ||
4369 | static int | |
4370 | arc_set_ext_seg (void) | |
4371 | { | |
4372 | if (!arcext_section) | |
4373 | { | |
4374 | arcext_section = subseg_new (".arcextmap", 0); | |
4375 | bfd_set_section_flags (stdoutput, arcext_section, | |
4376 | SEC_READONLY | SEC_HAS_CONTENTS); | |
4377 | } | |
4378 | else | |
4379 | subseg_set (arcext_section, 0); | |
4380 | return 1; | |
4381 | } | |
4382 | ||
4383 | /* Create an extension instruction description in the arc extension | |
4384 | section of the output file. | |
4385 | The structure for an instruction is like this: | |
4386 | [0]: Length of the record. | |
4387 | [1]: Type of the record. | |
4388 | ||
4389 | [2]: Major opcode. | |
4390 | [3]: Sub-opcode. | |
4391 | [4]: Syntax (flags). | |
4392 | [5]+ Name instruction. | |
4393 | ||
4394 | The sequence is terminated by an empty entry. */ | |
4395 | ||
4396 | static void | |
4397 | create_extinst_section (extInstruction_t *einsn) | |
4398 | { | |
4399 | ||
4400 | segT old_sec = now_seg; | |
4401 | int old_subsec = now_subseg; | |
4402 | char *p; | |
4403 | int name_len = strlen (einsn->name); | |
4404 | ||
4405 | arc_set_ext_seg (); | |
4406 | ||
4407 | p = frag_more (1); | |
4408 | *p = 5 + name_len + 1; | |
4409 | p = frag_more (1); | |
4410 | *p = EXT_INSTRUCTION; | |
4411 | p = frag_more (1); | |
4412 | *p = einsn->major; | |
4413 | p = frag_more (1); | |
4414 | *p = einsn->minor; | |
4415 | p = frag_more (1); | |
4416 | *p = einsn->flags; | |
4417 | p = frag_more (name_len + 1); | |
4418 | strcpy (p, einsn->name); | |
4419 | ||
4420 | subseg_set (old_sec, old_subsec); | |
4421 | } | |
4422 | ||
4423 | /* Handler .extinstruction pseudo-op. */ | |
4424 | ||
4425 | static void | |
4426 | arc_extinsn (int ignore ATTRIBUTE_UNUSED) | |
4427 | { | |
4428 | extInstruction_t einsn; | |
4429 | struct arc_opcode *arc_ext_opcodes; | |
4430 | const char *errmsg = NULL; | |
4431 | unsigned char moplow, mophigh; | |
4432 | ||
4433 | memset (&einsn, 0, sizeof (einsn)); | |
4434 | tokenize_extinsn (&einsn); | |
4435 | ||
4436 | /* Check if the name is already used. */ | |
4437 | if (arc_find_opcode (einsn.name)) | |
4438 | as_warn (_("Pseudocode already used %s"), einsn.name); | |
4439 | ||
4440 | /* Check the opcode ranges. */ | |
4441 | moplow = 0x05; | |
bb65a718 AB |
4442 | mophigh = (selected_cpu.flags & (ARC_OPCODE_ARCv2EM |
4443 | | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a; | |
b99747ae CZ |
4444 | |
4445 | if ((einsn.major > mophigh) || (einsn.major < moplow)) | |
4446 | as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, mophigh); | |
4447 | ||
4448 | if ((einsn.minor > 0x3f) && (einsn.major != 0x0a) | |
4449 | && (einsn.major != 5) && (einsn.major != 9)) | |
4450 | as_fatal (_("minor opcode not in range [0x00 - 0x3f]")); | |
4451 | ||
945e0f82 | 4452 | switch (einsn.syntax & ARC_SYNTAX_MASK) |
b99747ae CZ |
4453 | { |
4454 | case ARC_SYNTAX_3OP: | |
4455 | if (einsn.modsyn & ARC_OP1_IMM_IMPLIED) | |
4456 | as_fatal (_("Improper use of OP1_IMM_IMPLIED")); | |
4457 | break; | |
4458 | case ARC_SYNTAX_2OP: | |
945e0f82 CZ |
4459 | case ARC_SYNTAX_1OP: |
4460 | case ARC_SYNTAX_NOP: | |
b99747ae CZ |
4461 | if (einsn.modsyn & ARC_OP1_MUST_BE_IMM) |
4462 | as_fatal (_("Improper use of OP1_MUST_BE_IMM")); | |
4463 | break; | |
4464 | default: | |
4465 | break; | |
4466 | } | |
4467 | ||
bb65a718 | 4468 | arc_ext_opcodes = arcExtMap_genOpcode (&einsn, selected_cpu.flags, &errmsg); |
b99747ae CZ |
4469 | if (arc_ext_opcodes == NULL) |
4470 | { | |
4471 | if (errmsg) | |
4472 | as_fatal ("%s", errmsg); | |
4473 | else | |
4474 | as_fatal (_("Couldn't generate extension instruction opcodes")); | |
4475 | } | |
4476 | else if (errmsg) | |
4477 | as_warn ("%s", errmsg); | |
4478 | ||
4479 | /* Insert the extension instruction. */ | |
4480 | arc_insert_opcode ((const struct arc_opcode *) arc_ext_opcodes); | |
4481 | ||
4482 | create_extinst_section (&einsn); | |
4483 | } | |
4484 | ||
f36e33da CZ |
4485 | static void |
4486 | tokenize_extregister (extRegister_t *ereg, int opertype) | |
4487 | { | |
4488 | char *name; | |
4489 | char *mode; | |
4490 | char c; | |
4491 | char *p; | |
4492 | int number, imode = 0; | |
4493 | bfd_boolean isCore_p = (opertype == EXT_CORE_REGISTER) ? TRUE : FALSE; | |
4494 | bfd_boolean isReg_p = (opertype == EXT_CORE_REGISTER | |
4495 | || opertype == EXT_AUX_REGISTER) ? TRUE : FALSE; | |
4496 | ||
4497 | /* 1st: get register name. */ | |
4498 | SKIP_WHITESPACE (); | |
4499 | p = input_line_pointer; | |
4500 | c = get_symbol_name (&p); | |
4501 | ||
4502 | name = xstrdup (p); | |
4503 | restore_line_pointer (c); | |
4504 | ||
4505 | /* 2nd: get register number. */ | |
4506 | SKIP_WHITESPACE (); | |
4507 | ||
4508 | if (*input_line_pointer != ',') | |
4509 | { | |
4510 | as_bad (_("expected comma after register name")); | |
4511 | ignore_rest_of_line (); | |
4512 | free (name); | |
4513 | return; | |
4514 | } | |
4515 | input_line_pointer++; | |
4516 | number = get_absolute_expression (); | |
4517 | ||
4518 | if (number < 0) | |
4519 | { | |
4520 | as_bad (_("negative operand number %d"), number); | |
4521 | ignore_rest_of_line (); | |
4522 | free (name); | |
4523 | return; | |
4524 | } | |
4525 | ||
4526 | if (isReg_p) | |
4527 | { | |
4528 | /* 3rd: get register mode. */ | |
4529 | SKIP_WHITESPACE (); | |
4530 | ||
4531 | if (*input_line_pointer != ',') | |
4532 | { | |
4533 | as_bad (_("expected comma after register number")); | |
4534 | ignore_rest_of_line (); | |
4535 | free (name); | |
4536 | return; | |
4537 | } | |
4538 | ||
4539 | input_line_pointer++; | |
4540 | mode = input_line_pointer; | |
4541 | ||
4542 | if (!strncmp (mode, "r|w", 3)) | |
4543 | { | |
4544 | imode = 0; | |
4545 | input_line_pointer += 3; | |
4546 | } | |
4547 | else if (!strncmp (mode, "r", 1)) | |
4548 | { | |
4549 | imode = ARC_REGISTER_READONLY; | |
4550 | input_line_pointer += 1; | |
4551 | } | |
4552 | else if (strncmp (mode, "w", 1)) | |
4553 | { | |
4554 | as_bad (_("invalid mode")); | |
4555 | ignore_rest_of_line (); | |
4556 | free (name); | |
4557 | return; | |
4558 | } | |
4559 | else | |
4560 | { | |
4561 | imode = ARC_REGISTER_WRITEONLY; | |
4562 | input_line_pointer += 1; | |
4563 | } | |
4564 | } | |
4565 | ||
4566 | if (isCore_p) | |
4567 | { | |
4568 | /* 4th: get core register shortcut. */ | |
4569 | SKIP_WHITESPACE (); | |
4570 | if (*input_line_pointer != ',') | |
4571 | { | |
4572 | as_bad (_("expected comma after register mode")); | |
4573 | ignore_rest_of_line (); | |
4574 | free (name); | |
4575 | return; | |
4576 | } | |
4577 | ||
4578 | input_line_pointer++; | |
4579 | ||
4580 | if (!strncmp (input_line_pointer, "cannot_shortcut", 15)) | |
4581 | { | |
4582 | imode |= ARC_REGISTER_NOSHORT_CUT; | |
4583 | input_line_pointer += 15; | |
4584 | } | |
4585 | else if (strncmp (input_line_pointer, "can_shortcut", 12)) | |
4586 | { | |
4587 | as_bad (_("shortcut designator invalid")); | |
4588 | ignore_rest_of_line (); | |
4589 | free (name); | |
4590 | return; | |
4591 | } | |
4592 | else | |
4593 | { | |
4594 | input_line_pointer += 12; | |
4595 | } | |
4596 | } | |
4597 | demand_empty_rest_of_line (); | |
4598 | ||
4599 | ereg->name = name; | |
4600 | ereg->number = number; | |
4601 | ereg->imode = imode; | |
4602 | } | |
4603 | ||
4604 | /* Create an extension register/condition description in the arc | |
4605 | extension section of the output file. | |
4606 | ||
4607 | The structure for an instruction is like this: | |
4608 | [0]: Length of the record. | |
4609 | [1]: Type of the record. | |
4610 | ||
4611 | For core regs and condition codes: | |
4612 | [2]: Value. | |
4613 | [3]+ Name. | |
4614 | ||
4615 | For auxilirary registers: | |
4616 | [2..5]: Value. | |
4617 | [6]+ Name | |
4618 | ||
4619 | The sequence is terminated by an empty entry. */ | |
4620 | ||
4621 | static void | |
4622 | create_extcore_section (extRegister_t *ereg, int opertype) | |
4623 | { | |
4624 | segT old_sec = now_seg; | |
4625 | int old_subsec = now_subseg; | |
4626 | char *p; | |
4627 | int name_len = strlen (ereg->name); | |
4628 | ||
4629 | arc_set_ext_seg (); | |
4630 | ||
4631 | switch (opertype) | |
4632 | { | |
4633 | case EXT_COND_CODE: | |
4634 | case EXT_CORE_REGISTER: | |
4635 | p = frag_more (1); | |
4636 | *p = 3 + name_len + 1; | |
4637 | p = frag_more (1); | |
4638 | *p = opertype; | |
4639 | p = frag_more (1); | |
4640 | *p = ereg->number; | |
4641 | break; | |
4642 | case EXT_AUX_REGISTER: | |
4643 | p = frag_more (1); | |
4644 | *p = 6 + name_len + 1; | |
4645 | p = frag_more (1); | |
4646 | *p = EXT_AUX_REGISTER; | |
4647 | p = frag_more (1); | |
4648 | *p = (ereg->number >> 24) & 0xff; | |
4649 | p = frag_more (1); | |
4650 | *p = (ereg->number >> 16) & 0xff; | |
4651 | p = frag_more (1); | |
4652 | *p = (ereg->number >> 8) & 0xff; | |
4653 | p = frag_more (1); | |
4654 | *p = (ereg->number) & 0xff; | |
4655 | break; | |
4656 | default: | |
4657 | break; | |
4658 | } | |
4659 | ||
4660 | p = frag_more (name_len + 1); | |
4661 | strcpy (p, ereg->name); | |
4662 | ||
4663 | subseg_set (old_sec, old_subsec); | |
4664 | } | |
4665 | ||
4666 | /* Handler .extCoreRegister pseudo-op. */ | |
4667 | ||
4668 | static void | |
4669 | arc_extcorereg (int opertype) | |
4670 | { | |
4671 | extRegister_t ereg; | |
4672 | struct arc_aux_reg *auxr; | |
4673 | const char *retval; | |
4674 | struct arc_flag_operand *ccode; | |
4675 | ||
4676 | memset (&ereg, 0, sizeof (ereg)); | |
4677 | tokenize_extregister (&ereg, opertype); | |
4678 | ||
4679 | switch (opertype) | |
4680 | { | |
4681 | case EXT_CORE_REGISTER: | |
4682 | /* Core register. */ | |
4683 | if (ereg.number > 60) | |
4684 | as_bad (_("core register %s value (%d) too large"), ereg.name, | |
4685 | ereg.number); | |
4686 | declare_register (ereg.name, ereg.number); | |
4687 | break; | |
4688 | case EXT_AUX_REGISTER: | |
4689 | /* Auxiliary register. */ | |
add39d23 | 4690 | auxr = XNEW (struct arc_aux_reg); |
f36e33da | 4691 | auxr->name = ereg.name; |
bb65a718 | 4692 | auxr->cpu = selected_cpu.flags; |
f36e33da CZ |
4693 | auxr->subclass = NONE; |
4694 | auxr->address = ereg.number; | |
4695 | retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr); | |
4696 | if (retval) | |
4697 | as_fatal (_("internal error: can't hash aux register '%s': %s"), | |
4698 | auxr->name, retval); | |
4699 | break; | |
4700 | case EXT_COND_CODE: | |
4701 | /* Condition code. */ | |
4702 | if (ereg.number > 31) | |
4703 | as_bad (_("condition code %s value (%d) too large"), ereg.name, | |
4704 | ereg.number); | |
4705 | ext_condcode.size ++; | |
4706 | ext_condcode.arc_ext_condcode = | |
add39d23 TS |
4707 | XRESIZEVEC (struct arc_flag_operand, ext_condcode.arc_ext_condcode, |
4708 | ext_condcode.size + 1); | |
f36e33da CZ |
4709 | if (ext_condcode.arc_ext_condcode == NULL) |
4710 | as_fatal (_("Virtual memory exhausted")); | |
4711 | ||
4712 | ccode = ext_condcode.arc_ext_condcode + ext_condcode.size - 1; | |
4713 | ccode->name = ereg.name; | |
4714 | ccode->code = ereg.number; | |
4715 | ccode->bits = 5; | |
4716 | ccode->shift = 0; | |
4717 | ccode->favail = 0; /* not used. */ | |
4718 | ccode++; | |
4719 | memset (ccode, 0, sizeof (struct arc_flag_operand)); | |
4720 | break; | |
4721 | default: | |
4722 | as_bad (_("Unknown extension")); | |
4723 | break; | |
4724 | } | |
4725 | create_extcore_section (&ereg, opertype); | |
4726 | } | |
4727 | ||
b99747ae CZ |
4728 | /* Local variables: |
4729 | eval: (c-set-style "gnu") | |
4730 | indent-tabs-mode: t | |
4731 | End: */ |