Commit | Line | Data |
---|---|---|
b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
f17c130b | 2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, |
f31fef98 | 3 | 2004, 2005, 2006, 2007, 2008, 2009 |
b99bd4ef NC |
4 | Free Software Foundation, Inc. |
5 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) | |
6 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 7 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
8 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
9 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
10 | |
11 | This file is part of GAS, the GNU Assembler. | |
12 | ||
13 | GAS is free software; you can redistribute it and/or modify | |
14 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 15 | the Free Software Foundation; either version 3, or (at your option) |
b99bd4ef NC |
16 | any later version. |
17 | ||
18 | GAS is distributed in the hope that it will be useful, | |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
21 | GNU General Public License for more details. |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
24 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
25 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
26 | 02110-1301, USA. */ | |
b99bd4ef | 27 | |
42a68e18 | 28 | #include "as.h" |
5287ad62 | 29 | #include <limits.h> |
037e8744 | 30 | #include <stdarg.h> |
c19d1205 | 31 | #define NO_RELOC 0 |
3882b010 | 32 | #include "safe-ctype.h" |
b99bd4ef NC |
33 | #include "subsegs.h" |
34 | #include "obstack.h" | |
b99bd4ef | 35 | |
f263249b RE |
36 | #include "opcode/arm.h" |
37 | ||
b99bd4ef NC |
38 | #ifdef OBJ_ELF |
39 | #include "elf/arm.h" | |
a394c00f | 40 | #include "dw2gencfi.h" |
b99bd4ef NC |
41 | #endif |
42 | ||
f0927246 NC |
43 | #include "dwarf2dbg.h" |
44 | ||
7ed4c4c5 NC |
45 | #ifdef OBJ_ELF |
46 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
47 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
48 | ||
49 | /* This structure holds the unwinding state. */ | |
50 | ||
51 | static struct | |
52 | { | |
c19d1205 ZW |
53 | symbolS * proc_start; |
54 | symbolS * table_entry; | |
55 | symbolS * personality_routine; | |
56 | int personality_index; | |
7ed4c4c5 | 57 | /* The segment containing the function. */ |
c19d1205 ZW |
58 | segT saved_seg; |
59 | subsegT saved_subseg; | |
7ed4c4c5 NC |
60 | /* Opcodes generated from this function. */ |
61 | unsigned char * opcodes; | |
c19d1205 ZW |
62 | int opcode_count; |
63 | int opcode_alloc; | |
7ed4c4c5 | 64 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 65 | offsetT frame_size; |
7ed4c4c5 NC |
66 | /* We don't add stack adjustment opcodes immediately so that we can merge |
67 | multiple adjustments. We can also omit the final adjustment | |
68 | when using a frame pointer. */ | |
c19d1205 | 69 | offsetT pending_offset; |
7ed4c4c5 | 70 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
71 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
72 | offsetT fp_offset; | |
73 | int fp_reg; | |
7ed4c4c5 | 74 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 75 | unsigned fp_used:1; |
7ed4c4c5 | 76 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 77 | unsigned sp_restored:1; |
7ed4c4c5 NC |
78 | } unwind; |
79 | ||
8b1ad454 NC |
80 | /* Bit N indicates that an R_ARM_NONE relocation has been output for |
81 | __aeabi_unwind_cpp_prN already if set. This enables dependencies to be | |
82 | emitted only once per section, to save unnecessary bloat. */ | |
83 | static unsigned int marked_pr_dependency = 0; | |
84 | ||
85 | #endif /* OBJ_ELF */ | |
86 | ||
4962c51a MS |
87 | /* Results from operand parsing worker functions. */ |
88 | ||
89 | typedef enum | |
90 | { | |
91 | PARSE_OPERAND_SUCCESS, | |
92 | PARSE_OPERAND_FAIL, | |
93 | PARSE_OPERAND_FAIL_NO_BACKTRACK | |
94 | } parse_operand_result; | |
95 | ||
33a392fb PB |
96 | enum arm_float_abi |
97 | { | |
98 | ARM_FLOAT_ABI_HARD, | |
99 | ARM_FLOAT_ABI_SOFTFP, | |
100 | ARM_FLOAT_ABI_SOFT | |
101 | }; | |
102 | ||
c19d1205 | 103 | /* Types of processor to assemble for. */ |
b99bd4ef NC |
104 | #ifndef CPU_DEFAULT |
105 | #if defined __XSCALE__ | |
e74cfd16 | 106 | #define CPU_DEFAULT ARM_ARCH_XSCALE |
b99bd4ef NC |
107 | #else |
108 | #if defined __thumb__ | |
e74cfd16 | 109 | #define CPU_DEFAULT ARM_ARCH_V5T |
b99bd4ef NC |
110 | #endif |
111 | #endif | |
112 | #endif | |
113 | ||
114 | #ifndef FPU_DEFAULT | |
c820d418 MM |
115 | # ifdef TE_LINUX |
116 | # define FPU_DEFAULT FPU_ARCH_FPA | |
117 | # elif defined (TE_NetBSD) | |
118 | # ifdef OBJ_ELF | |
119 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
120 | # else | |
121 | /* Legacy a.out format. */ | |
122 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
123 | # endif | |
4e7fd91e PB |
124 | # elif defined (TE_VXWORKS) |
125 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
126 | # else |
127 | /* For backwards compatibility, default to FPA. */ | |
128 | # define FPU_DEFAULT FPU_ARCH_FPA | |
129 | # endif | |
130 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 131 | |
c19d1205 | 132 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 133 | |
e74cfd16 PB |
134 | static arm_feature_set cpu_variant; |
135 | static arm_feature_set arm_arch_used; | |
136 | static arm_feature_set thumb_arch_used; | |
b99bd4ef | 137 | |
b99bd4ef | 138 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
139 | static int uses_apcs_26 = FALSE; |
140 | static int atpcs = FALSE; | |
b34976b6 AM |
141 | static int support_interwork = FALSE; |
142 | static int uses_apcs_float = FALSE; | |
c19d1205 | 143 | static int pic_code = FALSE; |
845b51d6 | 144 | static int fix_v4bx = FALSE; |
278df34e NS |
145 | /* Warn on using deprecated features. */ |
146 | static int warn_on_deprecated = TRUE; | |
147 | ||
03b1477f RE |
148 | |
149 | /* Variables that we set while parsing command-line options. Once all | |
150 | options have been read we re-process these values to set the real | |
151 | assembly flags. */ | |
e74cfd16 PB |
152 | static const arm_feature_set *legacy_cpu = NULL; |
153 | static const arm_feature_set *legacy_fpu = NULL; | |
154 | ||
155 | static const arm_feature_set *mcpu_cpu_opt = NULL; | |
156 | static const arm_feature_set *mcpu_fpu_opt = NULL; | |
157 | static const arm_feature_set *march_cpu_opt = NULL; | |
158 | static const arm_feature_set *march_fpu_opt = NULL; | |
159 | static const arm_feature_set *mfpu_opt = NULL; | |
7a1d4c38 | 160 | static const arm_feature_set *object_arch = NULL; |
e74cfd16 PB |
161 | |
162 | /* Constants for known architecture features. */ | |
163 | static const arm_feature_set fpu_default = FPU_DEFAULT; | |
164 | static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; | |
165 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; | |
5287ad62 JB |
166 | static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; |
167 | static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; | |
e74cfd16 PB |
168 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; |
169 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; | |
170 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; | |
171 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; | |
172 | ||
173 | #ifdef CPU_DEFAULT | |
174 | static const arm_feature_set cpu_default = CPU_DEFAULT; | |
175 | #endif | |
176 | ||
177 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); | |
178 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); | |
179 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); | |
180 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); | |
181 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); | |
182 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); | |
183 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); | |
184 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); | |
185 | static const arm_feature_set arm_ext_v4t_5 = | |
186 | ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); | |
187 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); | |
188 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); | |
189 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); | |
190 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); | |
191 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); | |
192 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); | |
193 | static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0); | |
194 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); | |
62b3e311 | 195 | static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); |
7e806470 PB |
196 | static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0); |
197 | static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0); | |
62b3e311 PB |
198 | static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); |
199 | static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); | |
200 | static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); | |
201 | static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); | |
7e806470 PB |
202 | static const arm_feature_set arm_ext_m = |
203 | ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_V7M, 0); | |
e74cfd16 PB |
204 | |
205 | static const arm_feature_set arm_arch_any = ARM_ANY; | |
206 | static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); | |
207 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; | |
208 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; | |
209 | ||
2d447fca JM |
210 | static const arm_feature_set arm_cext_iwmmxt2 = |
211 | ARM_FEATURE (0, ARM_CEXT_IWMMXT2); | |
e74cfd16 PB |
212 | static const arm_feature_set arm_cext_iwmmxt = |
213 | ARM_FEATURE (0, ARM_CEXT_IWMMXT); | |
214 | static const arm_feature_set arm_cext_xscale = | |
215 | ARM_FEATURE (0, ARM_CEXT_XSCALE); | |
216 | static const arm_feature_set arm_cext_maverick = | |
217 | ARM_FEATURE (0, ARM_CEXT_MAVERICK); | |
218 | static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); | |
219 | static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); | |
220 | static const arm_feature_set fpu_vfp_ext_v1xd = | |
221 | ARM_FEATURE (0, FPU_VFP_EXT_V1xD); | |
222 | static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); | |
223 | static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); | |
5287ad62 | 224 | static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); |
b1cc4aeb PB |
225 | static const arm_feature_set fpu_vfp_ext_d32 = |
226 | ARM_FEATURE (0, FPU_VFP_EXT_D32); | |
5287ad62 JB |
227 | static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); |
228 | static const arm_feature_set fpu_vfp_v3_or_neon_ext = | |
229 | ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); | |
8e79c3df | 230 | static const arm_feature_set fpu_neon_fp16 = ARM_FEATURE (0, FPU_NEON_FP16); |
e74cfd16 | 231 | |
33a392fb | 232 | static int mfloat_abi_opt = -1; |
e74cfd16 PB |
233 | /* Record user cpu selection for object attributes. */ |
234 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; | |
ee065d83 PB |
235 | /* Must be long enough to hold any of the names in arm_cpus. */ |
236 | static char selected_cpu_name[16]; | |
7cc69913 | 237 | #ifdef OBJ_ELF |
deeaaff8 DJ |
238 | # ifdef EABI_DEFAULT |
239 | static int meabi_flags = EABI_DEFAULT; | |
240 | # else | |
d507cf36 | 241 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 242 | # endif |
e1da3f5b | 243 | |
ee3c0378 AS |
244 | static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; |
245 | ||
e1da3f5b | 246 | bfd_boolean |
5f4273c7 | 247 | arm_is_eabi (void) |
e1da3f5b PB |
248 | { |
249 | return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); | |
250 | } | |
7cc69913 | 251 | #endif |
b99bd4ef | 252 | |
b99bd4ef | 253 | #ifdef OBJ_ELF |
c19d1205 | 254 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
255 | symbolS * GOT_symbol; |
256 | #endif | |
257 | ||
b99bd4ef NC |
258 | /* 0: assemble for ARM, |
259 | 1: assemble for Thumb, | |
260 | 2: assemble for Thumb even though target CPU does not support thumb | |
261 | instructions. */ | |
262 | static int thumb_mode = 0; | |
8dc2430f NC |
263 | /* A value distinct from the possible values for thumb_mode that we |
264 | can use to record whether thumb_mode has been copied into the | |
265 | tc_frag_data field of a frag. */ | |
266 | #define MODE_RECORDED (1 << 4) | |
b99bd4ef | 267 | |
e07e6e58 NC |
268 | /* Specifies the intrinsic IT insn behavior mode. */ |
269 | enum implicit_it_mode | |
270 | { | |
271 | IMPLICIT_IT_MODE_NEVER = 0x00, | |
272 | IMPLICIT_IT_MODE_ARM = 0x01, | |
273 | IMPLICIT_IT_MODE_THUMB = 0x02, | |
274 | IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB) | |
275 | }; | |
276 | static int implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
277 | ||
c19d1205 ZW |
278 | /* If unified_syntax is true, we are processing the new unified |
279 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
280 | ||
281 | - Immediate operands do not require a # prefix. | |
282 | - Conditional affixes always appear at the end of the | |
283 | instruction. (For backward compatibility, those instructions | |
284 | that formerly had them in the middle, continue to accept them | |
285 | there.) | |
286 | - The IT instruction may appear, and if it does is validated | |
287 | against subsequent conditional affixes. It does not generate | |
288 | machine code. | |
289 | ||
290 | Important differences from the old Thumb mode: | |
291 | ||
292 | - Immediate operands do not require a # prefix. | |
293 | - Most of the V6T2 instructions are only available in unified mode. | |
294 | - The .N and .W suffixes are recognized and honored (it is an error | |
295 | if they cannot be honored). | |
296 | - All instructions set the flags if and only if they have an 's' affix. | |
297 | - Conditional affixes may be used. They are validated against | |
298 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
299 | conditional affix except in the scope of an IT instruction. */ | |
300 | ||
301 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef | 302 | |
5287ad62 JB |
303 | enum neon_el_type |
304 | { | |
dcbf9037 | 305 | NT_invtype, |
5287ad62 JB |
306 | NT_untyped, |
307 | NT_integer, | |
308 | NT_float, | |
309 | NT_poly, | |
310 | NT_signed, | |
dcbf9037 | 311 | NT_unsigned |
5287ad62 JB |
312 | }; |
313 | ||
314 | struct neon_type_el | |
315 | { | |
316 | enum neon_el_type type; | |
317 | unsigned size; | |
318 | }; | |
319 | ||
320 | #define NEON_MAX_TYPE_ELS 4 | |
321 | ||
322 | struct neon_type | |
323 | { | |
324 | struct neon_type_el el[NEON_MAX_TYPE_ELS]; | |
325 | unsigned elems; | |
326 | }; | |
327 | ||
e07e6e58 NC |
328 | enum it_instruction_type |
329 | { | |
330 | OUTSIDE_IT_INSN, | |
331 | INSIDE_IT_INSN, | |
332 | INSIDE_IT_LAST_INSN, | |
333 | IF_INSIDE_IT_LAST_INSN, /* Either outside or inside; | |
334 | if inside, should be the last one. */ | |
335 | NEUTRAL_IT_INSN, /* This could be either inside or outside, | |
336 | i.e. BKPT and NOP. */ | |
337 | IT_INSN /* The IT insn has been parsed. */ | |
338 | }; | |
339 | ||
b99bd4ef NC |
340 | struct arm_it |
341 | { | |
c19d1205 | 342 | const char * error; |
b99bd4ef | 343 | unsigned long instruction; |
c19d1205 ZW |
344 | int size; |
345 | int size_req; | |
346 | int cond; | |
037e8744 JB |
347 | /* "uncond_value" is set to the value in place of the conditional field in |
348 | unconditional versions of the instruction, or -1 if nothing is | |
349 | appropriate. */ | |
350 | int uncond_value; | |
5287ad62 | 351 | struct neon_type vectype; |
0110f2b8 PB |
352 | /* Set to the opcode if the instruction needs relaxation. |
353 | Zero if the instruction is not relaxed. */ | |
354 | unsigned long relax; | |
b99bd4ef NC |
355 | struct |
356 | { | |
357 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
358 | expressionS exp; |
359 | int pc_rel; | |
b99bd4ef | 360 | } reloc; |
b99bd4ef | 361 | |
e07e6e58 NC |
362 | enum it_instruction_type it_insn_type; |
363 | ||
c19d1205 ZW |
364 | struct |
365 | { | |
366 | unsigned reg; | |
ca3f61f7 | 367 | signed int imm; |
dcbf9037 | 368 | struct neon_type_el vectype; |
ca3f61f7 NC |
369 | unsigned present : 1; /* Operand present. */ |
370 | unsigned isreg : 1; /* Operand was a register. */ | |
371 | unsigned immisreg : 1; /* .imm field is a second register. */ | |
5287ad62 JB |
372 | unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ |
373 | unsigned immisalign : 1; /* Immediate is an alignment specifier. */ | |
c96612cc | 374 | unsigned immisfloat : 1; /* Immediate was parsed as a float. */ |
5287ad62 JB |
375 | /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV |
376 | instructions. This allows us to disambiguate ARM <-> vector insns. */ | |
377 | unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ | |
037e8744 | 378 | unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ |
5287ad62 | 379 | unsigned isquad : 1; /* Operand is Neon quad-precision register. */ |
037e8744 | 380 | unsigned issingle : 1; /* Operand is VFP single-precision register. */ |
ca3f61f7 NC |
381 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ |
382 | unsigned writeback : 1; /* Operand has trailing ! */ | |
383 | unsigned preind : 1; /* Preindexed address. */ | |
384 | unsigned postind : 1; /* Postindexed address. */ | |
385 | unsigned negative : 1; /* Index register was negated. */ | |
386 | unsigned shifted : 1; /* Shift applied to operation. */ | |
387 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
c19d1205 | 388 | } operands[6]; |
b99bd4ef NC |
389 | }; |
390 | ||
c19d1205 | 391 | static struct arm_it inst; |
b99bd4ef NC |
392 | |
393 | #define NUM_FLOAT_VALS 8 | |
394 | ||
05d2d07e | 395 | const char * fp_const[] = |
b99bd4ef NC |
396 | { |
397 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
398 | }; | |
399 | ||
c19d1205 | 400 | /* Number of littlenums required to hold an extended precision number. */ |
b99bd4ef NC |
401 | #define MAX_LITTLENUMS 6 |
402 | ||
403 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
404 | ||
405 | #define FAIL (-1) | |
406 | #define SUCCESS (0) | |
407 | ||
408 | #define SUFF_S 1 | |
409 | #define SUFF_D 2 | |
410 | #define SUFF_E 3 | |
411 | #define SUFF_P 4 | |
412 | ||
c19d1205 ZW |
413 | #define CP_T_X 0x00008000 |
414 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 415 | |
c19d1205 ZW |
416 | #define CONDS_BIT 0x00100000 |
417 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
418 | |
419 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
420 | ||
421 | struct asm_cond | |
422 | { | |
c19d1205 | 423 | const char * template; |
b99bd4ef NC |
424 | unsigned long value; |
425 | }; | |
426 | ||
c19d1205 | 427 | #define COND_ALWAYS 0xE |
b99bd4ef | 428 | |
b99bd4ef NC |
429 | struct asm_psr |
430 | { | |
b34976b6 | 431 | const char *template; |
b99bd4ef NC |
432 | unsigned long field; |
433 | }; | |
434 | ||
62b3e311 PB |
435 | struct asm_barrier_opt |
436 | { | |
437 | const char *template; | |
438 | unsigned long value; | |
439 | }; | |
440 | ||
2d2255b5 | 441 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
442 | #define SPSR_BIT (1 << 22) |
443 | ||
c19d1205 ZW |
444 | /* The individual PSR flag bits. */ |
445 | #define PSR_c (1 << 16) | |
446 | #define PSR_x (1 << 17) | |
447 | #define PSR_s (1 << 18) | |
448 | #define PSR_f (1 << 19) | |
b99bd4ef | 449 | |
c19d1205 | 450 | struct reloc_entry |
bfae80f2 | 451 | { |
c19d1205 ZW |
452 | char *name; |
453 | bfd_reloc_code_real_type reloc; | |
bfae80f2 RE |
454 | }; |
455 | ||
5287ad62 | 456 | enum vfp_reg_pos |
bfae80f2 | 457 | { |
5287ad62 JB |
458 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, |
459 | VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn | |
bfae80f2 RE |
460 | }; |
461 | ||
462 | enum vfp_ldstm_type | |
463 | { | |
464 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
465 | }; | |
466 | ||
dcbf9037 JB |
467 | /* Bits for DEFINED field in neon_typed_alias. */ |
468 | #define NTA_HASTYPE 1 | |
469 | #define NTA_HASINDEX 2 | |
470 | ||
471 | struct neon_typed_alias | |
472 | { | |
473 | unsigned char defined; | |
474 | unsigned char index; | |
475 | struct neon_type_el eltype; | |
476 | }; | |
477 | ||
c19d1205 ZW |
478 | /* ARM register categories. This includes coprocessor numbers and various |
479 | architecture extensions' registers. */ | |
480 | enum arm_reg_type | |
bfae80f2 | 481 | { |
c19d1205 ZW |
482 | REG_TYPE_RN, |
483 | REG_TYPE_CP, | |
484 | REG_TYPE_CN, | |
485 | REG_TYPE_FN, | |
486 | REG_TYPE_VFS, | |
487 | REG_TYPE_VFD, | |
5287ad62 | 488 | REG_TYPE_NQ, |
037e8744 | 489 | REG_TYPE_VFSD, |
5287ad62 | 490 | REG_TYPE_NDQ, |
037e8744 | 491 | REG_TYPE_NSDQ, |
c19d1205 ZW |
492 | REG_TYPE_VFC, |
493 | REG_TYPE_MVF, | |
494 | REG_TYPE_MVD, | |
495 | REG_TYPE_MVFX, | |
496 | REG_TYPE_MVDX, | |
497 | REG_TYPE_MVAX, | |
498 | REG_TYPE_DSPSC, | |
499 | REG_TYPE_MMXWR, | |
500 | REG_TYPE_MMXWC, | |
501 | REG_TYPE_MMXWCG, | |
502 | REG_TYPE_XSCALE, | |
bfae80f2 RE |
503 | }; |
504 | ||
dcbf9037 JB |
505 | /* Structure for a hash table entry for a register. |
506 | If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra | |
507 | information which states whether a vector type or index is specified (for a | |
508 | register alias created with .dn or .qn). Otherwise NEON should be NULL. */ | |
6c43fab6 RE |
509 | struct reg_entry |
510 | { | |
dcbf9037 JB |
511 | const char *name; |
512 | unsigned char number; | |
513 | unsigned char type; | |
514 | unsigned char builtin; | |
515 | struct neon_typed_alias *neon; | |
6c43fab6 RE |
516 | }; |
517 | ||
c19d1205 ZW |
518 | /* Diagnostics used when we don't get a register of the expected type. */ |
519 | const char *const reg_expected_msgs[] = | |
520 | { | |
521 | N_("ARM register expected"), | |
522 | N_("bad or missing co-processor number"), | |
523 | N_("co-processor register expected"), | |
524 | N_("FPA register expected"), | |
525 | N_("VFP single precision register expected"), | |
5287ad62 JB |
526 | N_("VFP/Neon double precision register expected"), |
527 | N_("Neon quad precision register expected"), | |
037e8744 | 528 | N_("VFP single or double precision register expected"), |
5287ad62 | 529 | N_("Neon double or quad precision register expected"), |
037e8744 | 530 | N_("VFP single, double or Neon quad precision register expected"), |
c19d1205 ZW |
531 | N_("VFP system register expected"), |
532 | N_("Maverick MVF register expected"), | |
533 | N_("Maverick MVD register expected"), | |
534 | N_("Maverick MVFX register expected"), | |
535 | N_("Maverick MVDX register expected"), | |
536 | N_("Maverick MVAX register expected"), | |
537 | N_("Maverick DSPSC register expected"), | |
538 | N_("iWMMXt data register expected"), | |
539 | N_("iWMMXt control register expected"), | |
540 | N_("iWMMXt scalar register expected"), | |
541 | N_("XScale accumulator register expected"), | |
6c43fab6 RE |
542 | }; |
543 | ||
c19d1205 ZW |
544 | /* Some well known registers that we refer to directly elsewhere. */ |
545 | #define REG_SP 13 | |
546 | #define REG_LR 14 | |
547 | #define REG_PC 15 | |
404ff6b5 | 548 | |
b99bd4ef NC |
549 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
550 | take 2: */ | |
c19d1205 | 551 | #define INSN_SIZE 4 |
b99bd4ef NC |
552 | |
553 | struct asm_opcode | |
554 | { | |
555 | /* Basic string to match. */ | |
c19d1205 ZW |
556 | const char *template; |
557 | ||
558 | /* Parameters to instruction. */ | |
559 | unsigned char operands[8]; | |
560 | ||
561 | /* Conditional tag - see opcode_lookup. */ | |
562 | unsigned int tag : 4; | |
b99bd4ef NC |
563 | |
564 | /* Basic instruction code. */ | |
c19d1205 | 565 | unsigned int avalue : 28; |
b99bd4ef | 566 | |
c19d1205 ZW |
567 | /* Thumb-format instruction code. */ |
568 | unsigned int tvalue; | |
b99bd4ef | 569 | |
90e4755a | 570 | /* Which architecture variant provides this instruction. */ |
e74cfd16 PB |
571 | const arm_feature_set *avariant; |
572 | const arm_feature_set *tvariant; | |
c19d1205 ZW |
573 | |
574 | /* Function to call to encode instruction in ARM format. */ | |
575 | void (* aencode) (void); | |
b99bd4ef | 576 | |
c19d1205 ZW |
577 | /* Function to call to encode instruction in Thumb format. */ |
578 | void (* tencode) (void); | |
b99bd4ef NC |
579 | }; |
580 | ||
a737bd4d NC |
581 | /* Defines for various bits that we will want to toggle. */ |
582 | #define INST_IMMEDIATE 0x02000000 | |
583 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 584 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
585 | #define SHIFT_BY_REG 0x00000010 |
586 | #define PRE_INDEX 0x01000000 | |
587 | #define INDEX_UP 0x00800000 | |
588 | #define WRITE_BACK 0x00200000 | |
589 | #define LDM_TYPE_2_OR_3 0x00400000 | |
a028a6f5 | 590 | #define CPSI_MMOD 0x00020000 |
90e4755a | 591 | |
a737bd4d NC |
592 | #define LITERAL_MASK 0xf000f000 |
593 | #define OPCODE_MASK 0xfe1fffff | |
594 | #define V4_STR_BIT 0x00000020 | |
90e4755a | 595 | |
efd81785 PB |
596 | #define T2_SUBS_PC_LR 0xf3de8f00 |
597 | ||
a737bd4d | 598 | #define DATA_OP_SHIFT 21 |
90e4755a | 599 | |
ef8d22e6 PB |
600 | #define T2_OPCODE_MASK 0xfe1fffff |
601 | #define T2_DATA_OP_SHIFT 21 | |
602 | ||
a737bd4d NC |
603 | /* Codes to distinguish the arithmetic instructions. */ |
604 | #define OPCODE_AND 0 | |
605 | #define OPCODE_EOR 1 | |
606 | #define OPCODE_SUB 2 | |
607 | #define OPCODE_RSB 3 | |
608 | #define OPCODE_ADD 4 | |
609 | #define OPCODE_ADC 5 | |
610 | #define OPCODE_SBC 6 | |
611 | #define OPCODE_RSC 7 | |
612 | #define OPCODE_TST 8 | |
613 | #define OPCODE_TEQ 9 | |
614 | #define OPCODE_CMP 10 | |
615 | #define OPCODE_CMN 11 | |
616 | #define OPCODE_ORR 12 | |
617 | #define OPCODE_MOV 13 | |
618 | #define OPCODE_BIC 14 | |
619 | #define OPCODE_MVN 15 | |
90e4755a | 620 | |
ef8d22e6 PB |
621 | #define T2_OPCODE_AND 0 |
622 | #define T2_OPCODE_BIC 1 | |
623 | #define T2_OPCODE_ORR 2 | |
624 | #define T2_OPCODE_ORN 3 | |
625 | #define T2_OPCODE_EOR 4 | |
626 | #define T2_OPCODE_ADD 8 | |
627 | #define T2_OPCODE_ADC 10 | |
628 | #define T2_OPCODE_SBC 11 | |
629 | #define T2_OPCODE_SUB 13 | |
630 | #define T2_OPCODE_RSB 14 | |
631 | ||
a737bd4d NC |
632 | #define T_OPCODE_MUL 0x4340 |
633 | #define T_OPCODE_TST 0x4200 | |
634 | #define T_OPCODE_CMN 0x42c0 | |
635 | #define T_OPCODE_NEG 0x4240 | |
636 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 637 | |
a737bd4d NC |
638 | #define T_OPCODE_ADD_R3 0x1800 |
639 | #define T_OPCODE_SUB_R3 0x1a00 | |
640 | #define T_OPCODE_ADD_HI 0x4400 | |
641 | #define T_OPCODE_ADD_ST 0xb000 | |
642 | #define T_OPCODE_SUB_ST 0xb080 | |
643 | #define T_OPCODE_ADD_SP 0xa800 | |
644 | #define T_OPCODE_ADD_PC 0xa000 | |
645 | #define T_OPCODE_ADD_I8 0x3000 | |
646 | #define T_OPCODE_SUB_I8 0x3800 | |
647 | #define T_OPCODE_ADD_I3 0x1c00 | |
648 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 649 | |
a737bd4d NC |
650 | #define T_OPCODE_ASR_R 0x4100 |
651 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
652 | #define T_OPCODE_LSR_R 0x40c0 |
653 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
654 | #define T_OPCODE_ASR_I 0x1000 |
655 | #define T_OPCODE_LSL_I 0x0000 | |
656 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 657 | |
a737bd4d NC |
658 | #define T_OPCODE_MOV_I8 0x2000 |
659 | #define T_OPCODE_CMP_I8 0x2800 | |
660 | #define T_OPCODE_CMP_LR 0x4280 | |
661 | #define T_OPCODE_MOV_HR 0x4600 | |
662 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 663 | |
a737bd4d NC |
664 | #define T_OPCODE_LDR_PC 0x4800 |
665 | #define T_OPCODE_LDR_SP 0x9800 | |
666 | #define T_OPCODE_STR_SP 0x9000 | |
667 | #define T_OPCODE_LDR_IW 0x6800 | |
668 | #define T_OPCODE_STR_IW 0x6000 | |
669 | #define T_OPCODE_LDR_IH 0x8800 | |
670 | #define T_OPCODE_STR_IH 0x8000 | |
671 | #define T_OPCODE_LDR_IB 0x7800 | |
672 | #define T_OPCODE_STR_IB 0x7000 | |
673 | #define T_OPCODE_LDR_RW 0x5800 | |
674 | #define T_OPCODE_STR_RW 0x5000 | |
675 | #define T_OPCODE_LDR_RH 0x5a00 | |
676 | #define T_OPCODE_STR_RH 0x5200 | |
677 | #define T_OPCODE_LDR_RB 0x5c00 | |
678 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 679 | |
a737bd4d NC |
680 | #define T_OPCODE_PUSH 0xb400 |
681 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 682 | |
2fc8bdac | 683 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 684 | |
a737bd4d | 685 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 686 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 | 687 | #define THUMB_LOAD_BIT 0x0800 |
53365c0d | 688 | #define THUMB2_LOAD_BIT 0x00100000 |
c19d1205 ZW |
689 | |
690 | #define BAD_ARGS _("bad arguments to instruction") | |
fdfde340 | 691 | #define BAD_SP _("r13 not allowed here") |
c19d1205 ZW |
692 | #define BAD_PC _("r15 not allowed here") |
693 | #define BAD_COND _("instruction cannot be conditional") | |
694 | #define BAD_OVERLAP _("registers may not be the same") | |
695 | #define BAD_HIREG _("lo register required") | |
696 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
01cfc07f | 697 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); |
dfa9f0d5 PB |
698 | #define BAD_BRANCH _("branch must be last instruction in IT block") |
699 | #define BAD_NOT_IT _("instruction not allowed in IT block") | |
037e8744 | 700 | #define BAD_FPU _("selected FPU does not support instruction") |
e07e6e58 NC |
701 | #define BAD_OUT_IT _("thumb conditional instruction should be in IT block") |
702 | #define BAD_IT_COND _("incorrect condition in IT block") | |
703 | #define BAD_IT_IT _("IT falling in the range of a previous IT block") | |
c19d1205 ZW |
704 | |
705 | static struct hash_control *arm_ops_hsh; | |
706 | static struct hash_control *arm_cond_hsh; | |
707 | static struct hash_control *arm_shift_hsh; | |
708 | static struct hash_control *arm_psr_hsh; | |
62b3e311 | 709 | static struct hash_control *arm_v7m_psr_hsh; |
c19d1205 ZW |
710 | static struct hash_control *arm_reg_hsh; |
711 | static struct hash_control *arm_reloc_hsh; | |
62b3e311 | 712 | static struct hash_control *arm_barrier_opt_hsh; |
b99bd4ef | 713 | |
b99bd4ef NC |
714 | /* Stuff needed to resolve the label ambiguity |
715 | As: | |
716 | ... | |
717 | label: <insn> | |
718 | may differ from: | |
719 | ... | |
720 | label: | |
5f4273c7 | 721 | <insn> */ |
b99bd4ef NC |
722 | |
723 | symbolS * last_label_seen; | |
b34976b6 | 724 | static int label_is_thumb_function_name = FALSE; |
e07e6e58 | 725 | |
3d0c9500 NC |
726 | /* Literal pool structure. Held on a per-section |
727 | and per-sub-section basis. */ | |
a737bd4d | 728 | |
c19d1205 | 729 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 730 | typedef struct literal_pool |
b99bd4ef | 731 | { |
c19d1205 ZW |
732 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
733 | unsigned int next_free_entry; | |
734 | unsigned int id; | |
735 | symbolS * symbol; | |
736 | segT section; | |
737 | subsegT sub_section; | |
61b5f74b | 738 | struct literal_pool * next; |
3d0c9500 | 739 | } literal_pool; |
b99bd4ef | 740 | |
3d0c9500 NC |
741 | /* Pointer to a linked list of literal pools. */ |
742 | literal_pool * list_of_pools = NULL; | |
e27ec89e | 743 | |
e07e6e58 NC |
744 | #ifdef OBJ_ELF |
745 | # define now_it seg_info (now_seg)->tc_segment_info_data.current_it | |
746 | #else | |
747 | static struct current_it now_it; | |
748 | #endif | |
749 | ||
750 | static inline int | |
751 | now_it_compatible (int cond) | |
752 | { | |
753 | return (cond & ~1) == (now_it.cc & ~1); | |
754 | } | |
755 | ||
756 | static inline int | |
757 | conditional_insn (void) | |
758 | { | |
759 | return inst.cond != COND_ALWAYS; | |
760 | } | |
761 | ||
762 | static int in_it_block (void); | |
763 | ||
764 | static int handle_it_state (void); | |
765 | ||
766 | static void force_automatic_it_block_close (void); | |
767 | ||
768 | #define set_it_insn_type(type) \ | |
769 | do \ | |
770 | { \ | |
771 | inst.it_insn_type = type; \ | |
772 | if (handle_it_state () == FAIL) \ | |
773 | return; \ | |
774 | } \ | |
775 | while (0) | |
776 | ||
777 | #define set_it_insn_type_last() \ | |
778 | do \ | |
779 | { \ | |
780 | if (inst.cond == COND_ALWAYS) \ | |
781 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \ | |
782 | else \ | |
783 | set_it_insn_type (INSIDE_IT_LAST_INSN); \ | |
784 | } \ | |
785 | while (0) | |
786 | ||
c19d1205 | 787 | /* Pure syntax. */ |
b99bd4ef | 788 | |
c19d1205 ZW |
789 | /* This array holds the chars that always start a comment. If the |
790 | pre-processor is disabled, these aren't very useful. */ | |
791 | const char comment_chars[] = "@"; | |
3d0c9500 | 792 | |
c19d1205 ZW |
793 | /* This array holds the chars that only start a comment at the beginning of |
794 | a line. If the line seems to have the form '# 123 filename' | |
795 | .line and .file directives will appear in the pre-processed output. */ | |
796 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
797 | first line of the input file. This is because the compiler outputs | |
798 | #NO_APP at the beginning of its output. */ | |
799 | /* Also note that comments like this one will always work. */ | |
800 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 801 | |
c19d1205 | 802 | const char line_separator_chars[] = ";"; |
b99bd4ef | 803 | |
c19d1205 ZW |
804 | /* Chars that can be used to separate mant |
805 | from exp in floating point numbers. */ | |
806 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 807 | |
c19d1205 ZW |
808 | /* Chars that mean this number is a floating point constant. */ |
809 | /* As in 0f12.456 */ | |
810 | /* or 0d1.2345e12 */ | |
b99bd4ef | 811 | |
c19d1205 | 812 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 813 | |
c19d1205 ZW |
814 | /* Prefix characters that indicate the start of an immediate |
815 | value. */ | |
816 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 817 | |
c19d1205 ZW |
818 | /* Separator character handling. */ |
819 | ||
820 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
821 | ||
822 | static inline int | |
823 | skip_past_char (char ** str, char c) | |
824 | { | |
825 | if (**str == c) | |
826 | { | |
827 | (*str)++; | |
828 | return SUCCESS; | |
3d0c9500 | 829 | } |
c19d1205 ZW |
830 | else |
831 | return FAIL; | |
832 | } | |
833 | #define skip_past_comma(str) skip_past_char (str, ',') | |
3d0c9500 | 834 | |
c19d1205 ZW |
835 | /* Arithmetic expressions (possibly involving symbols). */ |
836 | ||
837 | /* Return TRUE if anything in the expression is a bignum. */ | |
838 | ||
839 | static int | |
840 | walk_no_bignums (symbolS * sp) | |
841 | { | |
842 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
843 | return 1; | |
844 | ||
845 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 846 | { |
c19d1205 ZW |
847 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
848 | || (symbol_get_value_expression (sp)->X_op_symbol | |
849 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
850 | } |
851 | ||
c19d1205 | 852 | return 0; |
3d0c9500 NC |
853 | } |
854 | ||
c19d1205 ZW |
855 | static int in_my_get_expression = 0; |
856 | ||
857 | /* Third argument to my_get_expression. */ | |
858 | #define GE_NO_PREFIX 0 | |
859 | #define GE_IMM_PREFIX 1 | |
860 | #define GE_OPT_PREFIX 2 | |
5287ad62 JB |
861 | /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) |
862 | immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ | |
863 | #define GE_OPT_PREFIX_BIG 3 | |
a737bd4d | 864 | |
b99bd4ef | 865 | static int |
c19d1205 | 866 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 867 | { |
c19d1205 ZW |
868 | char * save_in; |
869 | segT seg; | |
b99bd4ef | 870 | |
c19d1205 ZW |
871 | /* In unified syntax, all prefixes are optional. */ |
872 | if (unified_syntax) | |
5287ad62 JB |
873 | prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode |
874 | : GE_OPT_PREFIX; | |
b99bd4ef | 875 | |
c19d1205 | 876 | switch (prefix_mode) |
b99bd4ef | 877 | { |
c19d1205 ZW |
878 | case GE_NO_PREFIX: break; |
879 | case GE_IMM_PREFIX: | |
880 | if (!is_immediate_prefix (**str)) | |
881 | { | |
882 | inst.error = _("immediate expression requires a # prefix"); | |
883 | return FAIL; | |
884 | } | |
885 | (*str)++; | |
886 | break; | |
887 | case GE_OPT_PREFIX: | |
5287ad62 | 888 | case GE_OPT_PREFIX_BIG: |
c19d1205 ZW |
889 | if (is_immediate_prefix (**str)) |
890 | (*str)++; | |
891 | break; | |
892 | default: abort (); | |
893 | } | |
b99bd4ef | 894 | |
c19d1205 | 895 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 896 | |
c19d1205 ZW |
897 | save_in = input_line_pointer; |
898 | input_line_pointer = *str; | |
899 | in_my_get_expression = 1; | |
900 | seg = expression (ep); | |
901 | in_my_get_expression = 0; | |
902 | ||
903 | if (ep->X_op == O_illegal) | |
b99bd4ef | 904 | { |
c19d1205 ZW |
905 | /* We found a bad expression in md_operand(). */ |
906 | *str = input_line_pointer; | |
907 | input_line_pointer = save_in; | |
908 | if (inst.error == NULL) | |
909 | inst.error = _("bad expression"); | |
910 | return 1; | |
911 | } | |
b99bd4ef | 912 | |
c19d1205 ZW |
913 | #ifdef OBJ_AOUT |
914 | if (seg != absolute_section | |
915 | && seg != text_section | |
916 | && seg != data_section | |
917 | && seg != bss_section | |
918 | && seg != undefined_section) | |
919 | { | |
920 | inst.error = _("bad segment"); | |
921 | *str = input_line_pointer; | |
922 | input_line_pointer = save_in; | |
923 | return 1; | |
b99bd4ef | 924 | } |
c19d1205 | 925 | #endif |
b99bd4ef | 926 | |
c19d1205 ZW |
927 | /* Get rid of any bignums now, so that we don't generate an error for which |
928 | we can't establish a line number later on. Big numbers are never valid | |
929 | in instructions, which is where this routine is always called. */ | |
5287ad62 JB |
930 | if (prefix_mode != GE_OPT_PREFIX_BIG |
931 | && (ep->X_op == O_big | |
932 | || (ep->X_add_symbol | |
933 | && (walk_no_bignums (ep->X_add_symbol) | |
934 | || (ep->X_op_symbol | |
935 | && walk_no_bignums (ep->X_op_symbol)))))) | |
c19d1205 ZW |
936 | { |
937 | inst.error = _("invalid constant"); | |
938 | *str = input_line_pointer; | |
939 | input_line_pointer = save_in; | |
940 | return 1; | |
941 | } | |
b99bd4ef | 942 | |
c19d1205 ZW |
943 | *str = input_line_pointer; |
944 | input_line_pointer = save_in; | |
945 | return 0; | |
b99bd4ef NC |
946 | } |
947 | ||
c19d1205 ZW |
948 | /* Turn a string in input_line_pointer into a floating point constant |
949 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
950 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
951 | returned, or NULL on OK. | |
b99bd4ef | 952 | |
c19d1205 ZW |
953 | Note that fp constants aren't represent in the normal way on the ARM. |
954 | In big endian mode, things are as expected. However, in little endian | |
955 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
956 | within the words. For example, (double) 1.1 in big endian mode is | |
957 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
958 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 959 | |
c19d1205 | 960 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 961 | |
c19d1205 ZW |
962 | char * |
963 | md_atof (int type, char * litP, int * sizeP) | |
964 | { | |
965 | int prec; | |
966 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
967 | char *t; | |
968 | int i; | |
b99bd4ef | 969 | |
c19d1205 ZW |
970 | switch (type) |
971 | { | |
972 | case 'f': | |
973 | case 'F': | |
974 | case 's': | |
975 | case 'S': | |
976 | prec = 2; | |
977 | break; | |
b99bd4ef | 978 | |
c19d1205 ZW |
979 | case 'd': |
980 | case 'D': | |
981 | case 'r': | |
982 | case 'R': | |
983 | prec = 4; | |
984 | break; | |
b99bd4ef | 985 | |
c19d1205 ZW |
986 | case 'x': |
987 | case 'X': | |
499ac353 | 988 | prec = 5; |
c19d1205 | 989 | break; |
b99bd4ef | 990 | |
c19d1205 ZW |
991 | case 'p': |
992 | case 'P': | |
499ac353 | 993 | prec = 5; |
c19d1205 | 994 | break; |
a737bd4d | 995 | |
c19d1205 ZW |
996 | default: |
997 | *sizeP = 0; | |
499ac353 | 998 | return _("Unrecognized or unsupported floating point constant"); |
c19d1205 | 999 | } |
b99bd4ef | 1000 | |
c19d1205 ZW |
1001 | t = atof_ieee (input_line_pointer, type, words); |
1002 | if (t) | |
1003 | input_line_pointer = t; | |
499ac353 | 1004 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
b99bd4ef | 1005 | |
c19d1205 ZW |
1006 | if (target_big_endian) |
1007 | { | |
1008 | for (i = 0; i < prec; i++) | |
1009 | { | |
499ac353 NC |
1010 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1011 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1012 | } |
1013 | } | |
1014 | else | |
1015 | { | |
e74cfd16 | 1016 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
c19d1205 ZW |
1017 | for (i = prec - 1; i >= 0; i--) |
1018 | { | |
499ac353 NC |
1019 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1020 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1021 | } |
1022 | else | |
1023 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
1024 | For an 8 byte float the order is 1 0 3 2. */ | |
1025 | for (i = 0; i < prec; i += 2) | |
1026 | { | |
499ac353 NC |
1027 | md_number_to_chars (litP, (valueT) words[i + 1], |
1028 | sizeof (LITTLENUM_TYPE)); | |
1029 | md_number_to_chars (litP + sizeof (LITTLENUM_TYPE), | |
1030 | (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
1031 | litP += 2 * sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1032 | } |
1033 | } | |
b99bd4ef | 1034 | |
499ac353 | 1035 | return NULL; |
c19d1205 | 1036 | } |
b99bd4ef | 1037 | |
c19d1205 ZW |
1038 | /* We handle all bad expressions here, so that we can report the faulty |
1039 | instruction in the error message. */ | |
1040 | void | |
1041 | md_operand (expressionS * expr) | |
1042 | { | |
1043 | if (in_my_get_expression) | |
1044 | expr->X_op = O_illegal; | |
b99bd4ef NC |
1045 | } |
1046 | ||
c19d1205 | 1047 | /* Immediate values. */ |
b99bd4ef | 1048 | |
c19d1205 ZW |
1049 | /* Generic immediate-value read function for use in directives. |
1050 | Accepts anything that 'expression' can fold to a constant. | |
1051 | *val receives the number. */ | |
1052 | #ifdef OBJ_ELF | |
1053 | static int | |
1054 | immediate_for_directive (int *val) | |
b99bd4ef | 1055 | { |
c19d1205 ZW |
1056 | expressionS exp; |
1057 | exp.X_op = O_illegal; | |
b99bd4ef | 1058 | |
c19d1205 ZW |
1059 | if (is_immediate_prefix (*input_line_pointer)) |
1060 | { | |
1061 | input_line_pointer++; | |
1062 | expression (&exp); | |
1063 | } | |
b99bd4ef | 1064 | |
c19d1205 ZW |
1065 | if (exp.X_op != O_constant) |
1066 | { | |
1067 | as_bad (_("expected #constant")); | |
1068 | ignore_rest_of_line (); | |
1069 | return FAIL; | |
1070 | } | |
1071 | *val = exp.X_add_number; | |
1072 | return SUCCESS; | |
b99bd4ef | 1073 | } |
c19d1205 | 1074 | #endif |
b99bd4ef | 1075 | |
c19d1205 | 1076 | /* Register parsing. */ |
b99bd4ef | 1077 | |
c19d1205 ZW |
1078 | /* Generic register parser. CCP points to what should be the |
1079 | beginning of a register name. If it is indeed a valid register | |
1080 | name, advance CCP over it and return the reg_entry structure; | |
1081 | otherwise return NULL. Does not issue diagnostics. */ | |
1082 | ||
1083 | static struct reg_entry * | |
1084 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 1085 | { |
c19d1205 ZW |
1086 | char *start = *ccp; |
1087 | char *p; | |
1088 | struct reg_entry *reg; | |
b99bd4ef | 1089 | |
c19d1205 ZW |
1090 | #ifdef REGISTER_PREFIX |
1091 | if (*start != REGISTER_PREFIX) | |
01cfc07f | 1092 | return NULL; |
c19d1205 ZW |
1093 | start++; |
1094 | #endif | |
1095 | #ifdef OPTIONAL_REGISTER_PREFIX | |
1096 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
1097 | start++; | |
1098 | #endif | |
b99bd4ef | 1099 | |
c19d1205 ZW |
1100 | p = start; |
1101 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
1102 | return NULL; | |
b99bd4ef | 1103 | |
c19d1205 ZW |
1104 | do |
1105 | p++; | |
1106 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
1107 | ||
1108 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
1109 | ||
1110 | if (!reg) | |
1111 | return NULL; | |
1112 | ||
1113 | *ccp = p; | |
1114 | return reg; | |
b99bd4ef NC |
1115 | } |
1116 | ||
1117 | static int | |
dcbf9037 JB |
1118 | arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, |
1119 | enum arm_reg_type type) | |
b99bd4ef | 1120 | { |
c19d1205 ZW |
1121 | /* Alternative syntaxes are accepted for a few register classes. */ |
1122 | switch (type) | |
1123 | { | |
1124 | case REG_TYPE_MVF: | |
1125 | case REG_TYPE_MVD: | |
1126 | case REG_TYPE_MVFX: | |
1127 | case REG_TYPE_MVDX: | |
1128 | /* Generic coprocessor register names are allowed for these. */ | |
79134647 | 1129 | if (reg && reg->type == REG_TYPE_CN) |
c19d1205 ZW |
1130 | return reg->number; |
1131 | break; | |
69b97547 | 1132 | |
c19d1205 ZW |
1133 | case REG_TYPE_CP: |
1134 | /* For backward compatibility, a bare number is valid here. */ | |
1135 | { | |
1136 | unsigned long processor = strtoul (start, ccp, 10); | |
1137 | if (*ccp != start && processor <= 15) | |
1138 | return processor; | |
1139 | } | |
6057a28f | 1140 | |
c19d1205 ZW |
1141 | case REG_TYPE_MMXWC: |
1142 | /* WC includes WCG. ??? I'm not sure this is true for all | |
1143 | instructions that take WC registers. */ | |
79134647 | 1144 | if (reg && reg->type == REG_TYPE_MMXWCG) |
c19d1205 | 1145 | return reg->number; |
6057a28f | 1146 | break; |
c19d1205 | 1147 | |
6057a28f | 1148 | default: |
c19d1205 | 1149 | break; |
6057a28f NC |
1150 | } |
1151 | ||
dcbf9037 JB |
1152 | return FAIL; |
1153 | } | |
1154 | ||
1155 | /* As arm_reg_parse_multi, but the register must be of type TYPE, and the | |
1156 | return value is the register number or FAIL. */ | |
1157 | ||
1158 | static int | |
1159 | arm_reg_parse (char **ccp, enum arm_reg_type type) | |
1160 | { | |
1161 | char *start = *ccp; | |
1162 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
1163 | int ret; | |
1164 | ||
1165 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1166 | if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) | |
1167 | return FAIL; | |
1168 | ||
1169 | if (reg && reg->type == type) | |
1170 | return reg->number; | |
1171 | ||
1172 | if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) | |
1173 | return ret; | |
1174 | ||
c19d1205 ZW |
1175 | *ccp = start; |
1176 | return FAIL; | |
1177 | } | |
69b97547 | 1178 | |
dcbf9037 JB |
1179 | /* Parse a Neon type specifier. *STR should point at the leading '.' |
1180 | character. Does no verification at this stage that the type fits the opcode | |
1181 | properly. E.g., | |
1182 | ||
1183 | .i32.i32.s16 | |
1184 | .s32.f32 | |
1185 | .u16 | |
1186 | ||
1187 | Can all be legally parsed by this function. | |
1188 | ||
1189 | Fills in neon_type struct pointer with parsed information, and updates STR | |
1190 | to point after the parsed type specifier. Returns SUCCESS if this was a legal | |
1191 | type, FAIL if not. */ | |
1192 | ||
1193 | static int | |
1194 | parse_neon_type (struct neon_type *type, char **str) | |
1195 | { | |
1196 | char *ptr = *str; | |
1197 | ||
1198 | if (type) | |
1199 | type->elems = 0; | |
1200 | ||
1201 | while (type->elems < NEON_MAX_TYPE_ELS) | |
1202 | { | |
1203 | enum neon_el_type thistype = NT_untyped; | |
1204 | unsigned thissize = -1u; | |
1205 | ||
1206 | if (*ptr != '.') | |
1207 | break; | |
1208 | ||
1209 | ptr++; | |
1210 | ||
1211 | /* Just a size without an explicit type. */ | |
1212 | if (ISDIGIT (*ptr)) | |
1213 | goto parsesize; | |
1214 | ||
1215 | switch (TOLOWER (*ptr)) | |
1216 | { | |
1217 | case 'i': thistype = NT_integer; break; | |
1218 | case 'f': thistype = NT_float; break; | |
1219 | case 'p': thistype = NT_poly; break; | |
1220 | case 's': thistype = NT_signed; break; | |
1221 | case 'u': thistype = NT_unsigned; break; | |
037e8744 JB |
1222 | case 'd': |
1223 | thistype = NT_float; | |
1224 | thissize = 64; | |
1225 | ptr++; | |
1226 | goto done; | |
dcbf9037 JB |
1227 | default: |
1228 | as_bad (_("unexpected character `%c' in type specifier"), *ptr); | |
1229 | return FAIL; | |
1230 | } | |
1231 | ||
1232 | ptr++; | |
1233 | ||
1234 | /* .f is an abbreviation for .f32. */ | |
1235 | if (thistype == NT_float && !ISDIGIT (*ptr)) | |
1236 | thissize = 32; | |
1237 | else | |
1238 | { | |
1239 | parsesize: | |
1240 | thissize = strtoul (ptr, &ptr, 10); | |
1241 | ||
1242 | if (thissize != 8 && thissize != 16 && thissize != 32 | |
1243 | && thissize != 64) | |
1244 | { | |
1245 | as_bad (_("bad size %d in type specifier"), thissize); | |
1246 | return FAIL; | |
1247 | } | |
1248 | } | |
1249 | ||
037e8744 | 1250 | done: |
dcbf9037 JB |
1251 | if (type) |
1252 | { | |
1253 | type->el[type->elems].type = thistype; | |
1254 | type->el[type->elems].size = thissize; | |
1255 | type->elems++; | |
1256 | } | |
1257 | } | |
1258 | ||
1259 | /* Empty/missing type is not a successful parse. */ | |
1260 | if (type->elems == 0) | |
1261 | return FAIL; | |
1262 | ||
1263 | *str = ptr; | |
1264 | ||
1265 | return SUCCESS; | |
1266 | } | |
1267 | ||
1268 | /* Errors may be set multiple times during parsing or bit encoding | |
1269 | (particularly in the Neon bits), but usually the earliest error which is set | |
1270 | will be the most meaningful. Avoid overwriting it with later (cascading) | |
1271 | errors by calling this function. */ | |
1272 | ||
1273 | static void | |
1274 | first_error (const char *err) | |
1275 | { | |
1276 | if (!inst.error) | |
1277 | inst.error = err; | |
1278 | } | |
1279 | ||
1280 | /* Parse a single type, e.g. ".s32", leading period included. */ | |
1281 | static int | |
1282 | parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) | |
1283 | { | |
1284 | char *str = *ccp; | |
1285 | struct neon_type optype; | |
1286 | ||
1287 | if (*str == '.') | |
1288 | { | |
1289 | if (parse_neon_type (&optype, &str) == SUCCESS) | |
1290 | { | |
1291 | if (optype.elems == 1) | |
1292 | *vectype = optype.el[0]; | |
1293 | else | |
1294 | { | |
1295 | first_error (_("only one type should be specified for operand")); | |
1296 | return FAIL; | |
1297 | } | |
1298 | } | |
1299 | else | |
1300 | { | |
1301 | first_error (_("vector type expected")); | |
1302 | return FAIL; | |
1303 | } | |
1304 | } | |
1305 | else | |
1306 | return FAIL; | |
5f4273c7 | 1307 | |
dcbf9037 | 1308 | *ccp = str; |
5f4273c7 | 1309 | |
dcbf9037 JB |
1310 | return SUCCESS; |
1311 | } | |
1312 | ||
1313 | /* Special meanings for indices (which have a range of 0-7), which will fit into | |
1314 | a 4-bit integer. */ | |
1315 | ||
1316 | #define NEON_ALL_LANES 15 | |
1317 | #define NEON_INTERLEAVE_LANES 14 | |
1318 | ||
1319 | /* Parse either a register or a scalar, with an optional type. Return the | |
1320 | register number, and optionally fill in the actual type of the register | |
1321 | when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and | |
1322 | type/index information in *TYPEINFO. */ | |
1323 | ||
1324 | static int | |
1325 | parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, | |
1326 | enum arm_reg_type *rtype, | |
1327 | struct neon_typed_alias *typeinfo) | |
1328 | { | |
1329 | char *str = *ccp; | |
1330 | struct reg_entry *reg = arm_reg_parse_multi (&str); | |
1331 | struct neon_typed_alias atype; | |
1332 | struct neon_type_el parsetype; | |
1333 | ||
1334 | atype.defined = 0; | |
1335 | atype.index = -1; | |
1336 | atype.eltype.type = NT_invtype; | |
1337 | atype.eltype.size = -1; | |
1338 | ||
1339 | /* Try alternate syntax for some types of register. Note these are mutually | |
1340 | exclusive with the Neon syntax extensions. */ | |
1341 | if (reg == NULL) | |
1342 | { | |
1343 | int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); | |
1344 | if (altreg != FAIL) | |
1345 | *ccp = str; | |
1346 | if (typeinfo) | |
1347 | *typeinfo = atype; | |
1348 | return altreg; | |
1349 | } | |
1350 | ||
037e8744 JB |
1351 | /* Undo polymorphism when a set of register types may be accepted. */ |
1352 | if ((type == REG_TYPE_NDQ | |
1353 | && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) | |
1354 | || (type == REG_TYPE_VFSD | |
1355 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) | |
1356 | || (type == REG_TYPE_NSDQ | |
1357 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD | |
f512f76f NC |
1358 | || reg->type == REG_TYPE_NQ)) |
1359 | || (type == REG_TYPE_MMXWC | |
1360 | && (reg->type == REG_TYPE_MMXWCG))) | |
dcbf9037 JB |
1361 | type = reg->type; |
1362 | ||
1363 | if (type != reg->type) | |
1364 | return FAIL; | |
1365 | ||
1366 | if (reg->neon) | |
1367 | atype = *reg->neon; | |
5f4273c7 | 1368 | |
dcbf9037 JB |
1369 | if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) |
1370 | { | |
1371 | if ((atype.defined & NTA_HASTYPE) != 0) | |
1372 | { | |
1373 | first_error (_("can't redefine type for operand")); | |
1374 | return FAIL; | |
1375 | } | |
1376 | atype.defined |= NTA_HASTYPE; | |
1377 | atype.eltype = parsetype; | |
1378 | } | |
5f4273c7 | 1379 | |
dcbf9037 JB |
1380 | if (skip_past_char (&str, '[') == SUCCESS) |
1381 | { | |
1382 | if (type != REG_TYPE_VFD) | |
1383 | { | |
1384 | first_error (_("only D registers may be indexed")); | |
1385 | return FAIL; | |
1386 | } | |
5f4273c7 | 1387 | |
dcbf9037 JB |
1388 | if ((atype.defined & NTA_HASINDEX) != 0) |
1389 | { | |
1390 | first_error (_("can't change index for operand")); | |
1391 | return FAIL; | |
1392 | } | |
1393 | ||
1394 | atype.defined |= NTA_HASINDEX; | |
1395 | ||
1396 | if (skip_past_char (&str, ']') == SUCCESS) | |
1397 | atype.index = NEON_ALL_LANES; | |
1398 | else | |
1399 | { | |
1400 | expressionS exp; | |
1401 | ||
1402 | my_get_expression (&exp, &str, GE_NO_PREFIX); | |
1403 | ||
1404 | if (exp.X_op != O_constant) | |
1405 | { | |
1406 | first_error (_("constant expression required")); | |
1407 | return FAIL; | |
1408 | } | |
1409 | ||
1410 | if (skip_past_char (&str, ']') == FAIL) | |
1411 | return FAIL; | |
1412 | ||
1413 | atype.index = exp.X_add_number; | |
1414 | } | |
1415 | } | |
5f4273c7 | 1416 | |
dcbf9037 JB |
1417 | if (typeinfo) |
1418 | *typeinfo = atype; | |
5f4273c7 | 1419 | |
dcbf9037 JB |
1420 | if (rtype) |
1421 | *rtype = type; | |
5f4273c7 | 1422 | |
dcbf9037 | 1423 | *ccp = str; |
5f4273c7 | 1424 | |
dcbf9037 JB |
1425 | return reg->number; |
1426 | } | |
1427 | ||
1428 | /* Like arm_reg_parse, but allow allow the following extra features: | |
1429 | - If RTYPE is non-zero, return the (possibly restricted) type of the | |
1430 | register (e.g. Neon double or quad reg when either has been requested). | |
1431 | - If this is a Neon vector type with additional type information, fill | |
1432 | in the struct pointed to by VECTYPE (if non-NULL). | |
5f4273c7 | 1433 | This function will fault on encountering a scalar. */ |
dcbf9037 JB |
1434 | |
1435 | static int | |
1436 | arm_typed_reg_parse (char **ccp, enum arm_reg_type type, | |
1437 | enum arm_reg_type *rtype, struct neon_type_el *vectype) | |
1438 | { | |
1439 | struct neon_typed_alias atype; | |
1440 | char *str = *ccp; | |
1441 | int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); | |
1442 | ||
1443 | if (reg == FAIL) | |
1444 | return FAIL; | |
1445 | ||
1446 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1447 | if ((atype.defined & NTA_HASINDEX) != 0) | |
1448 | { | |
1449 | first_error (_("register operand expected, but got scalar")); | |
1450 | return FAIL; | |
1451 | } | |
1452 | ||
1453 | if (vectype) | |
1454 | *vectype = atype.eltype; | |
1455 | ||
1456 | *ccp = str; | |
1457 | ||
1458 | return reg; | |
1459 | } | |
1460 | ||
1461 | #define NEON_SCALAR_REG(X) ((X) >> 4) | |
1462 | #define NEON_SCALAR_INDEX(X) ((X) & 15) | |
1463 | ||
5287ad62 JB |
1464 | /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't |
1465 | have enough information to be able to do a good job bounds-checking. So, we | |
1466 | just do easy checks here, and do further checks later. */ | |
1467 | ||
1468 | static int | |
dcbf9037 | 1469 | parse_scalar (char **ccp, int elsize, struct neon_type_el *type) |
5287ad62 | 1470 | { |
dcbf9037 | 1471 | int reg; |
5287ad62 | 1472 | char *str = *ccp; |
dcbf9037 | 1473 | struct neon_typed_alias atype; |
5f4273c7 | 1474 | |
dcbf9037 | 1475 | reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); |
5f4273c7 | 1476 | |
dcbf9037 | 1477 | if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) |
5287ad62 | 1478 | return FAIL; |
5f4273c7 | 1479 | |
dcbf9037 | 1480 | if (atype.index == NEON_ALL_LANES) |
5287ad62 | 1481 | { |
dcbf9037 | 1482 | first_error (_("scalar must have an index")); |
5287ad62 JB |
1483 | return FAIL; |
1484 | } | |
dcbf9037 | 1485 | else if (atype.index >= 64 / elsize) |
5287ad62 | 1486 | { |
dcbf9037 | 1487 | first_error (_("scalar index out of range")); |
5287ad62 JB |
1488 | return FAIL; |
1489 | } | |
5f4273c7 | 1490 | |
dcbf9037 JB |
1491 | if (type) |
1492 | *type = atype.eltype; | |
5f4273c7 | 1493 | |
5287ad62 | 1494 | *ccp = str; |
5f4273c7 | 1495 | |
dcbf9037 | 1496 | return reg * 16 + atype.index; |
5287ad62 JB |
1497 | } |
1498 | ||
c19d1205 | 1499 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
e07e6e58 | 1500 | |
c19d1205 ZW |
1501 | static long |
1502 | parse_reg_list (char ** strp) | |
1503 | { | |
1504 | char * str = * strp; | |
1505 | long range = 0; | |
1506 | int another_range; | |
a737bd4d | 1507 | |
c19d1205 ZW |
1508 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
1509 | do | |
6057a28f | 1510 | { |
c19d1205 | 1511 | another_range = 0; |
a737bd4d | 1512 | |
c19d1205 ZW |
1513 | if (*str == '{') |
1514 | { | |
1515 | int in_range = 0; | |
1516 | int cur_reg = -1; | |
a737bd4d | 1517 | |
c19d1205 ZW |
1518 | str++; |
1519 | do | |
1520 | { | |
1521 | int reg; | |
6057a28f | 1522 | |
dcbf9037 | 1523 | if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) |
c19d1205 | 1524 | { |
dcbf9037 | 1525 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 ZW |
1526 | return FAIL; |
1527 | } | |
a737bd4d | 1528 | |
c19d1205 ZW |
1529 | if (in_range) |
1530 | { | |
1531 | int i; | |
a737bd4d | 1532 | |
c19d1205 ZW |
1533 | if (reg <= cur_reg) |
1534 | { | |
dcbf9037 | 1535 | first_error (_("bad range in register list")); |
c19d1205 ZW |
1536 | return FAIL; |
1537 | } | |
40a18ebd | 1538 | |
c19d1205 ZW |
1539 | for (i = cur_reg + 1; i < reg; i++) |
1540 | { | |
1541 | if (range & (1 << i)) | |
1542 | as_tsktsk | |
1543 | (_("Warning: duplicated register (r%d) in register list"), | |
1544 | i); | |
1545 | else | |
1546 | range |= 1 << i; | |
1547 | } | |
1548 | in_range = 0; | |
1549 | } | |
a737bd4d | 1550 | |
c19d1205 ZW |
1551 | if (range & (1 << reg)) |
1552 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
1553 | reg); | |
1554 | else if (reg <= cur_reg) | |
1555 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 1556 | |
c19d1205 ZW |
1557 | range |= 1 << reg; |
1558 | cur_reg = reg; | |
1559 | } | |
1560 | while (skip_past_comma (&str) != FAIL | |
1561 | || (in_range = 1, *str++ == '-')); | |
1562 | str--; | |
a737bd4d | 1563 | |
c19d1205 ZW |
1564 | if (*str++ != '}') |
1565 | { | |
dcbf9037 | 1566 | first_error (_("missing `}'")); |
c19d1205 ZW |
1567 | return FAIL; |
1568 | } | |
1569 | } | |
1570 | else | |
1571 | { | |
1572 | expressionS expr; | |
40a18ebd | 1573 | |
c19d1205 ZW |
1574 | if (my_get_expression (&expr, &str, GE_NO_PREFIX)) |
1575 | return FAIL; | |
40a18ebd | 1576 | |
c19d1205 ZW |
1577 | if (expr.X_op == O_constant) |
1578 | { | |
1579 | if (expr.X_add_number | |
1580 | != (expr.X_add_number & 0x0000ffff)) | |
1581 | { | |
1582 | inst.error = _("invalid register mask"); | |
1583 | return FAIL; | |
1584 | } | |
a737bd4d | 1585 | |
c19d1205 ZW |
1586 | if ((range & expr.X_add_number) != 0) |
1587 | { | |
1588 | int regno = range & expr.X_add_number; | |
a737bd4d | 1589 | |
c19d1205 ZW |
1590 | regno &= -regno; |
1591 | regno = (1 << regno) - 1; | |
1592 | as_tsktsk | |
1593 | (_("Warning: duplicated register (r%d) in register list"), | |
1594 | regno); | |
1595 | } | |
a737bd4d | 1596 | |
c19d1205 ZW |
1597 | range |= expr.X_add_number; |
1598 | } | |
1599 | else | |
1600 | { | |
1601 | if (inst.reloc.type != 0) | |
1602 | { | |
1603 | inst.error = _("expression too complex"); | |
1604 | return FAIL; | |
1605 | } | |
a737bd4d | 1606 | |
c19d1205 ZW |
1607 | memcpy (&inst.reloc.exp, &expr, sizeof (expressionS)); |
1608 | inst.reloc.type = BFD_RELOC_ARM_MULTI; | |
1609 | inst.reloc.pc_rel = 0; | |
1610 | } | |
1611 | } | |
a737bd4d | 1612 | |
c19d1205 ZW |
1613 | if (*str == '|' || *str == '+') |
1614 | { | |
1615 | str++; | |
1616 | another_range = 1; | |
1617 | } | |
a737bd4d | 1618 | } |
c19d1205 | 1619 | while (another_range); |
a737bd4d | 1620 | |
c19d1205 ZW |
1621 | *strp = str; |
1622 | return range; | |
a737bd4d NC |
1623 | } |
1624 | ||
5287ad62 JB |
1625 | /* Types of registers in a list. */ |
1626 | ||
1627 | enum reg_list_els | |
1628 | { | |
1629 | REGLIST_VFP_S, | |
1630 | REGLIST_VFP_D, | |
1631 | REGLIST_NEON_D | |
1632 | }; | |
1633 | ||
c19d1205 ZW |
1634 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1635 | Otherwise return the number of registers, and set PBASE to the first | |
5287ad62 JB |
1636 | register. Parses registers of type ETYPE. |
1637 | If REGLIST_NEON_D is used, several syntax enhancements are enabled: | |
1638 | - Q registers can be used to specify pairs of D registers | |
1639 | - { } can be omitted from around a singleton register list | |
1640 | FIXME: This is not implemented, as it would require backtracking in | |
1641 | some cases, e.g.: | |
1642 | vtbl.8 d3,d4,d5 | |
1643 | This could be done (the meaning isn't really ambiguous), but doesn't | |
1644 | fit in well with the current parsing framework. | |
dcbf9037 JB |
1645 | - 32 D registers may be used (also true for VFPv3). |
1646 | FIXME: Types are ignored in these register lists, which is probably a | |
1647 | bug. */ | |
6057a28f | 1648 | |
c19d1205 | 1649 | static int |
037e8744 | 1650 | parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) |
6057a28f | 1651 | { |
037e8744 | 1652 | char *str = *ccp; |
c19d1205 ZW |
1653 | int base_reg; |
1654 | int new_base; | |
5287ad62 JB |
1655 | enum arm_reg_type regtype = 0; |
1656 | int max_regs = 0; | |
c19d1205 ZW |
1657 | int count = 0; |
1658 | int warned = 0; | |
1659 | unsigned long mask = 0; | |
a737bd4d | 1660 | int i; |
6057a28f | 1661 | |
037e8744 | 1662 | if (*str != '{') |
5287ad62 JB |
1663 | { |
1664 | inst.error = _("expecting {"); | |
1665 | return FAIL; | |
1666 | } | |
6057a28f | 1667 | |
037e8744 | 1668 | str++; |
6057a28f | 1669 | |
5287ad62 | 1670 | switch (etype) |
c19d1205 | 1671 | { |
5287ad62 | 1672 | case REGLIST_VFP_S: |
c19d1205 ZW |
1673 | regtype = REG_TYPE_VFS; |
1674 | max_regs = 32; | |
5287ad62 | 1675 | break; |
5f4273c7 | 1676 | |
5287ad62 JB |
1677 | case REGLIST_VFP_D: |
1678 | regtype = REG_TYPE_VFD; | |
b7fc2769 | 1679 | break; |
5f4273c7 | 1680 | |
b7fc2769 JB |
1681 | case REGLIST_NEON_D: |
1682 | regtype = REG_TYPE_NDQ; | |
1683 | break; | |
1684 | } | |
1685 | ||
1686 | if (etype != REGLIST_VFP_S) | |
1687 | { | |
b1cc4aeb PB |
1688 | /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */ |
1689 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) | |
5287ad62 JB |
1690 | { |
1691 | max_regs = 32; | |
1692 | if (thumb_mode) | |
1693 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
b1cc4aeb | 1694 | fpu_vfp_ext_d32); |
5287ad62 JB |
1695 | else |
1696 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
b1cc4aeb | 1697 | fpu_vfp_ext_d32); |
5287ad62 JB |
1698 | } |
1699 | else | |
1700 | max_regs = 16; | |
c19d1205 | 1701 | } |
6057a28f | 1702 | |
c19d1205 | 1703 | base_reg = max_regs; |
a737bd4d | 1704 | |
c19d1205 ZW |
1705 | do |
1706 | { | |
5287ad62 | 1707 | int setmask = 1, addregs = 1; |
dcbf9037 | 1708 | |
037e8744 | 1709 | new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); |
dcbf9037 | 1710 | |
c19d1205 | 1711 | if (new_base == FAIL) |
a737bd4d | 1712 | { |
dcbf9037 | 1713 | first_error (_(reg_expected_msgs[regtype])); |
c19d1205 ZW |
1714 | return FAIL; |
1715 | } | |
5f4273c7 | 1716 | |
b7fc2769 JB |
1717 | if (new_base >= max_regs) |
1718 | { | |
1719 | first_error (_("register out of range in list")); | |
1720 | return FAIL; | |
1721 | } | |
5f4273c7 | 1722 | |
5287ad62 JB |
1723 | /* Note: a value of 2 * n is returned for the register Q<n>. */ |
1724 | if (regtype == REG_TYPE_NQ) | |
1725 | { | |
1726 | setmask = 3; | |
1727 | addregs = 2; | |
1728 | } | |
1729 | ||
c19d1205 ZW |
1730 | if (new_base < base_reg) |
1731 | base_reg = new_base; | |
a737bd4d | 1732 | |
5287ad62 | 1733 | if (mask & (setmask << new_base)) |
c19d1205 | 1734 | { |
dcbf9037 | 1735 | first_error (_("invalid register list")); |
c19d1205 | 1736 | return FAIL; |
a737bd4d | 1737 | } |
a737bd4d | 1738 | |
c19d1205 ZW |
1739 | if ((mask >> new_base) != 0 && ! warned) |
1740 | { | |
1741 | as_tsktsk (_("register list not in ascending order")); | |
1742 | warned = 1; | |
1743 | } | |
0bbf2aa4 | 1744 | |
5287ad62 JB |
1745 | mask |= setmask << new_base; |
1746 | count += addregs; | |
0bbf2aa4 | 1747 | |
037e8744 | 1748 | if (*str == '-') /* We have the start of a range expression */ |
c19d1205 ZW |
1749 | { |
1750 | int high_range; | |
0bbf2aa4 | 1751 | |
037e8744 | 1752 | str++; |
0bbf2aa4 | 1753 | |
037e8744 | 1754 | if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) |
dcbf9037 | 1755 | == FAIL) |
c19d1205 ZW |
1756 | { |
1757 | inst.error = gettext (reg_expected_msgs[regtype]); | |
1758 | return FAIL; | |
1759 | } | |
0bbf2aa4 | 1760 | |
b7fc2769 JB |
1761 | if (high_range >= max_regs) |
1762 | { | |
1763 | first_error (_("register out of range in list")); | |
1764 | return FAIL; | |
1765 | } | |
1766 | ||
5287ad62 JB |
1767 | if (regtype == REG_TYPE_NQ) |
1768 | high_range = high_range + 1; | |
1769 | ||
c19d1205 ZW |
1770 | if (high_range <= new_base) |
1771 | { | |
1772 | inst.error = _("register range not in ascending order"); | |
1773 | return FAIL; | |
1774 | } | |
0bbf2aa4 | 1775 | |
5287ad62 | 1776 | for (new_base += addregs; new_base <= high_range; new_base += addregs) |
0bbf2aa4 | 1777 | { |
5287ad62 | 1778 | if (mask & (setmask << new_base)) |
0bbf2aa4 | 1779 | { |
c19d1205 ZW |
1780 | inst.error = _("invalid register list"); |
1781 | return FAIL; | |
0bbf2aa4 | 1782 | } |
c19d1205 | 1783 | |
5287ad62 JB |
1784 | mask |= setmask << new_base; |
1785 | count += addregs; | |
0bbf2aa4 | 1786 | } |
0bbf2aa4 | 1787 | } |
0bbf2aa4 | 1788 | } |
037e8744 | 1789 | while (skip_past_comma (&str) != FAIL); |
0bbf2aa4 | 1790 | |
037e8744 | 1791 | str++; |
0bbf2aa4 | 1792 | |
c19d1205 ZW |
1793 | /* Sanity check -- should have raised a parse error above. */ |
1794 | if (count == 0 || count > max_regs) | |
1795 | abort (); | |
1796 | ||
1797 | *pbase = base_reg; | |
1798 | ||
1799 | /* Final test -- the registers must be consecutive. */ | |
1800 | mask >>= base_reg; | |
1801 | for (i = 0; i < count; i++) | |
1802 | { | |
1803 | if ((mask & (1u << i)) == 0) | |
1804 | { | |
1805 | inst.error = _("non-contiguous register range"); | |
1806 | return FAIL; | |
1807 | } | |
1808 | } | |
1809 | ||
037e8744 JB |
1810 | *ccp = str; |
1811 | ||
c19d1205 | 1812 | return count; |
b99bd4ef NC |
1813 | } |
1814 | ||
dcbf9037 JB |
1815 | /* True if two alias types are the same. */ |
1816 | ||
1817 | static int | |
1818 | neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) | |
1819 | { | |
1820 | if (!a && !b) | |
1821 | return 1; | |
5f4273c7 | 1822 | |
dcbf9037 JB |
1823 | if (!a || !b) |
1824 | return 0; | |
1825 | ||
1826 | if (a->defined != b->defined) | |
1827 | return 0; | |
5f4273c7 | 1828 | |
dcbf9037 JB |
1829 | if ((a->defined & NTA_HASTYPE) != 0 |
1830 | && (a->eltype.type != b->eltype.type | |
1831 | || a->eltype.size != b->eltype.size)) | |
1832 | return 0; | |
1833 | ||
1834 | if ((a->defined & NTA_HASINDEX) != 0 | |
1835 | && (a->index != b->index)) | |
1836 | return 0; | |
5f4273c7 | 1837 | |
dcbf9037 JB |
1838 | return 1; |
1839 | } | |
1840 | ||
5287ad62 JB |
1841 | /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. |
1842 | The base register is put in *PBASE. | |
dcbf9037 | 1843 | The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of |
5287ad62 JB |
1844 | the return value. |
1845 | The register stride (minus one) is put in bit 4 of the return value. | |
dcbf9037 JB |
1846 | Bits [6:5] encode the list length (minus one). |
1847 | The type of the list elements is put in *ELTYPE, if non-NULL. */ | |
5287ad62 | 1848 | |
5287ad62 | 1849 | #define NEON_LANE(X) ((X) & 0xf) |
dcbf9037 | 1850 | #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) |
5287ad62 JB |
1851 | #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) |
1852 | ||
1853 | static int | |
dcbf9037 JB |
1854 | parse_neon_el_struct_list (char **str, unsigned *pbase, |
1855 | struct neon_type_el *eltype) | |
5287ad62 JB |
1856 | { |
1857 | char *ptr = *str; | |
1858 | int base_reg = -1; | |
1859 | int reg_incr = -1; | |
1860 | int count = 0; | |
1861 | int lane = -1; | |
1862 | int leading_brace = 0; | |
1863 | enum arm_reg_type rtype = REG_TYPE_NDQ; | |
1864 | int addregs = 1; | |
1865 | const char *const incr_error = "register stride must be 1 or 2"; | |
1866 | const char *const type_error = "mismatched element/structure types in list"; | |
dcbf9037 | 1867 | struct neon_typed_alias firsttype; |
5f4273c7 | 1868 | |
5287ad62 JB |
1869 | if (skip_past_char (&ptr, '{') == SUCCESS) |
1870 | leading_brace = 1; | |
5f4273c7 | 1871 | |
5287ad62 JB |
1872 | do |
1873 | { | |
dcbf9037 JB |
1874 | struct neon_typed_alias atype; |
1875 | int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); | |
1876 | ||
5287ad62 JB |
1877 | if (getreg == FAIL) |
1878 | { | |
dcbf9037 | 1879 | first_error (_(reg_expected_msgs[rtype])); |
5287ad62 JB |
1880 | return FAIL; |
1881 | } | |
5f4273c7 | 1882 | |
5287ad62 JB |
1883 | if (base_reg == -1) |
1884 | { | |
1885 | base_reg = getreg; | |
1886 | if (rtype == REG_TYPE_NQ) | |
1887 | { | |
1888 | reg_incr = 1; | |
1889 | addregs = 2; | |
1890 | } | |
dcbf9037 | 1891 | firsttype = atype; |
5287ad62 JB |
1892 | } |
1893 | else if (reg_incr == -1) | |
1894 | { | |
1895 | reg_incr = getreg - base_reg; | |
1896 | if (reg_incr < 1 || reg_incr > 2) | |
1897 | { | |
dcbf9037 | 1898 | first_error (_(incr_error)); |
5287ad62 JB |
1899 | return FAIL; |
1900 | } | |
1901 | } | |
1902 | else if (getreg != base_reg + reg_incr * count) | |
1903 | { | |
dcbf9037 JB |
1904 | first_error (_(incr_error)); |
1905 | return FAIL; | |
1906 | } | |
1907 | ||
1908 | if (!neon_alias_types_same (&atype, &firsttype)) | |
1909 | { | |
1910 | first_error (_(type_error)); | |
5287ad62 JB |
1911 | return FAIL; |
1912 | } | |
5f4273c7 | 1913 | |
5287ad62 JB |
1914 | /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list |
1915 | modes. */ | |
1916 | if (ptr[0] == '-') | |
1917 | { | |
dcbf9037 | 1918 | struct neon_typed_alias htype; |
5287ad62 JB |
1919 | int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; |
1920 | if (lane == -1) | |
1921 | lane = NEON_INTERLEAVE_LANES; | |
1922 | else if (lane != NEON_INTERLEAVE_LANES) | |
1923 | { | |
dcbf9037 | 1924 | first_error (_(type_error)); |
5287ad62 JB |
1925 | return FAIL; |
1926 | } | |
1927 | if (reg_incr == -1) | |
1928 | reg_incr = 1; | |
1929 | else if (reg_incr != 1) | |
1930 | { | |
dcbf9037 | 1931 | first_error (_("don't use Rn-Rm syntax with non-unit stride")); |
5287ad62 JB |
1932 | return FAIL; |
1933 | } | |
1934 | ptr++; | |
dcbf9037 | 1935 | hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); |
5287ad62 JB |
1936 | if (hireg == FAIL) |
1937 | { | |
dcbf9037 JB |
1938 | first_error (_(reg_expected_msgs[rtype])); |
1939 | return FAIL; | |
1940 | } | |
1941 | if (!neon_alias_types_same (&htype, &firsttype)) | |
1942 | { | |
1943 | first_error (_(type_error)); | |
5287ad62 JB |
1944 | return FAIL; |
1945 | } | |
1946 | count += hireg + dregs - getreg; | |
1947 | continue; | |
1948 | } | |
5f4273c7 | 1949 | |
5287ad62 JB |
1950 | /* If we're using Q registers, we can't use [] or [n] syntax. */ |
1951 | if (rtype == REG_TYPE_NQ) | |
1952 | { | |
1953 | count += 2; | |
1954 | continue; | |
1955 | } | |
5f4273c7 | 1956 | |
dcbf9037 | 1957 | if ((atype.defined & NTA_HASINDEX) != 0) |
5287ad62 | 1958 | { |
dcbf9037 JB |
1959 | if (lane == -1) |
1960 | lane = atype.index; | |
1961 | else if (lane != atype.index) | |
5287ad62 | 1962 | { |
dcbf9037 JB |
1963 | first_error (_(type_error)); |
1964 | return FAIL; | |
5287ad62 JB |
1965 | } |
1966 | } | |
1967 | else if (lane == -1) | |
1968 | lane = NEON_INTERLEAVE_LANES; | |
1969 | else if (lane != NEON_INTERLEAVE_LANES) | |
1970 | { | |
dcbf9037 | 1971 | first_error (_(type_error)); |
5287ad62 JB |
1972 | return FAIL; |
1973 | } | |
1974 | count++; | |
1975 | } | |
1976 | while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); | |
5f4273c7 | 1977 | |
5287ad62 JB |
1978 | /* No lane set by [x]. We must be interleaving structures. */ |
1979 | if (lane == -1) | |
1980 | lane = NEON_INTERLEAVE_LANES; | |
5f4273c7 | 1981 | |
5287ad62 JB |
1982 | /* Sanity check. */ |
1983 | if (lane == -1 || base_reg == -1 || count < 1 || count > 4 | |
1984 | || (count > 1 && reg_incr == -1)) | |
1985 | { | |
dcbf9037 | 1986 | first_error (_("error parsing element/structure list")); |
5287ad62 JB |
1987 | return FAIL; |
1988 | } | |
1989 | ||
1990 | if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) | |
1991 | { | |
dcbf9037 | 1992 | first_error (_("expected }")); |
5287ad62 JB |
1993 | return FAIL; |
1994 | } | |
5f4273c7 | 1995 | |
5287ad62 JB |
1996 | if (reg_incr == -1) |
1997 | reg_incr = 1; | |
1998 | ||
dcbf9037 JB |
1999 | if (eltype) |
2000 | *eltype = firsttype.eltype; | |
2001 | ||
5287ad62 JB |
2002 | *pbase = base_reg; |
2003 | *str = ptr; | |
5f4273c7 | 2004 | |
5287ad62 JB |
2005 | return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); |
2006 | } | |
2007 | ||
c19d1205 ZW |
2008 | /* Parse an explicit relocation suffix on an expression. This is |
2009 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
2010 | arm_reloc_hsh contains no entries, so this function can only | |
2011 | succeed if there is no () after the word. Returns -1 on error, | |
2012 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
2013 | static int | |
2014 | parse_reloc (char **str) | |
b99bd4ef | 2015 | { |
c19d1205 ZW |
2016 | struct reloc_entry *r; |
2017 | char *p, *q; | |
b99bd4ef | 2018 | |
c19d1205 ZW |
2019 | if (**str != '(') |
2020 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 2021 | |
c19d1205 ZW |
2022 | p = *str + 1; |
2023 | q = p; | |
2024 | ||
2025 | while (*q && *q != ')' && *q != ',') | |
2026 | q++; | |
2027 | if (*q != ')') | |
2028 | return -1; | |
2029 | ||
2030 | if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
2031 | return -1; | |
2032 | ||
2033 | *str = q + 1; | |
2034 | return r->reloc; | |
b99bd4ef NC |
2035 | } |
2036 | ||
c19d1205 ZW |
2037 | /* Directives: register aliases. */ |
2038 | ||
dcbf9037 | 2039 | static struct reg_entry * |
c19d1205 | 2040 | insert_reg_alias (char *str, int number, int type) |
b99bd4ef | 2041 | { |
c19d1205 ZW |
2042 | struct reg_entry *new; |
2043 | const char *name; | |
b99bd4ef | 2044 | |
c19d1205 ZW |
2045 | if ((new = hash_find (arm_reg_hsh, str)) != 0) |
2046 | { | |
2047 | if (new->builtin) | |
2048 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); | |
b99bd4ef | 2049 | |
c19d1205 ZW |
2050 | /* Only warn about a redefinition if it's not defined as the |
2051 | same register. */ | |
2052 | else if (new->number != number || new->type != type) | |
2053 | as_warn (_("ignoring redefinition of register alias '%s'"), str); | |
69b97547 | 2054 | |
d929913e | 2055 | return NULL; |
c19d1205 | 2056 | } |
b99bd4ef | 2057 | |
c19d1205 ZW |
2058 | name = xstrdup (str); |
2059 | new = xmalloc (sizeof (struct reg_entry)); | |
b99bd4ef | 2060 | |
c19d1205 ZW |
2061 | new->name = name; |
2062 | new->number = number; | |
2063 | new->type = type; | |
2064 | new->builtin = FALSE; | |
dcbf9037 | 2065 | new->neon = NULL; |
b99bd4ef | 2066 | |
5a49b8ac | 2067 | if (hash_insert (arm_reg_hsh, name, (void *) new)) |
c19d1205 | 2068 | abort (); |
5f4273c7 | 2069 | |
dcbf9037 JB |
2070 | return new; |
2071 | } | |
2072 | ||
2073 | static void | |
2074 | insert_neon_reg_alias (char *str, int number, int type, | |
2075 | struct neon_typed_alias *atype) | |
2076 | { | |
2077 | struct reg_entry *reg = insert_reg_alias (str, number, type); | |
5f4273c7 | 2078 | |
dcbf9037 JB |
2079 | if (!reg) |
2080 | { | |
2081 | first_error (_("attempt to redefine typed alias")); | |
2082 | return; | |
2083 | } | |
5f4273c7 | 2084 | |
dcbf9037 JB |
2085 | if (atype) |
2086 | { | |
2087 | reg->neon = xmalloc (sizeof (struct neon_typed_alias)); | |
2088 | *reg->neon = *atype; | |
2089 | } | |
c19d1205 | 2090 | } |
b99bd4ef | 2091 | |
c19d1205 | 2092 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 2093 | |
c19d1205 | 2094 | new_register_name .req existing_register_name |
b99bd4ef | 2095 | |
c19d1205 | 2096 | If we find one, or if it looks sufficiently like one that we want to |
d929913e | 2097 | handle any error here, return TRUE. Otherwise return FALSE. */ |
b99bd4ef | 2098 | |
d929913e | 2099 | static bfd_boolean |
c19d1205 ZW |
2100 | create_register_alias (char * newname, char *p) |
2101 | { | |
2102 | struct reg_entry *old; | |
2103 | char *oldname, *nbuf; | |
2104 | size_t nlen; | |
b99bd4ef | 2105 | |
c19d1205 ZW |
2106 | /* The input scrubber ensures that whitespace after the mnemonic is |
2107 | collapsed to single spaces. */ | |
2108 | oldname = p; | |
2109 | if (strncmp (oldname, " .req ", 6) != 0) | |
d929913e | 2110 | return FALSE; |
b99bd4ef | 2111 | |
c19d1205 ZW |
2112 | oldname += 6; |
2113 | if (*oldname == '\0') | |
d929913e | 2114 | return FALSE; |
b99bd4ef | 2115 | |
c19d1205 ZW |
2116 | old = hash_find (arm_reg_hsh, oldname); |
2117 | if (!old) | |
b99bd4ef | 2118 | { |
c19d1205 | 2119 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
d929913e | 2120 | return TRUE; |
b99bd4ef NC |
2121 | } |
2122 | ||
c19d1205 ZW |
2123 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2124 | the desired alias name, and p points to its end. If not, then | |
2125 | the desired alias name is in the global original_case_string. */ | |
2126 | #ifdef TC_CASE_SENSITIVE | |
2127 | nlen = p - newname; | |
2128 | #else | |
2129 | newname = original_case_string; | |
2130 | nlen = strlen (newname); | |
2131 | #endif | |
b99bd4ef | 2132 | |
c19d1205 ZW |
2133 | nbuf = alloca (nlen + 1); |
2134 | memcpy (nbuf, newname, nlen); | |
2135 | nbuf[nlen] = '\0'; | |
b99bd4ef | 2136 | |
c19d1205 ZW |
2137 | /* Create aliases under the new name as stated; an all-lowercase |
2138 | version of the new name; and an all-uppercase version of the new | |
2139 | name. */ | |
d929913e NC |
2140 | if (insert_reg_alias (nbuf, old->number, old->type) != NULL) |
2141 | { | |
2142 | for (p = nbuf; *p; p++) | |
2143 | *p = TOUPPER (*p); | |
c19d1205 | 2144 | |
d929913e NC |
2145 | if (strncmp (nbuf, newname, nlen)) |
2146 | { | |
2147 | /* If this attempt to create an additional alias fails, do not bother | |
2148 | trying to create the all-lower case alias. We will fail and issue | |
2149 | a second, duplicate error message. This situation arises when the | |
2150 | programmer does something like: | |
2151 | foo .req r0 | |
2152 | Foo .req r1 | |
2153 | The second .req creates the "Foo" alias but then fails to create | |
5f4273c7 | 2154 | the artificial FOO alias because it has already been created by the |
d929913e NC |
2155 | first .req. */ |
2156 | if (insert_reg_alias (nbuf, old->number, old->type) == NULL) | |
2157 | return TRUE; | |
2158 | } | |
c19d1205 | 2159 | |
d929913e NC |
2160 | for (p = nbuf; *p; p++) |
2161 | *p = TOLOWER (*p); | |
c19d1205 | 2162 | |
d929913e NC |
2163 | if (strncmp (nbuf, newname, nlen)) |
2164 | insert_reg_alias (nbuf, old->number, old->type); | |
2165 | } | |
c19d1205 | 2166 | |
d929913e | 2167 | return TRUE; |
b99bd4ef NC |
2168 | } |
2169 | ||
dcbf9037 JB |
2170 | /* Create a Neon typed/indexed register alias using directives, e.g.: |
2171 | X .dn d5.s32[1] | |
2172 | Y .qn 6.s16 | |
2173 | Z .dn d7 | |
2174 | T .dn Z[0] | |
2175 | These typed registers can be used instead of the types specified after the | |
2176 | Neon mnemonic, so long as all operands given have types. Types can also be | |
2177 | specified directly, e.g.: | |
5f4273c7 | 2178 | vadd d0.s32, d1.s32, d2.s32 */ |
dcbf9037 JB |
2179 | |
2180 | static int | |
2181 | create_neon_reg_alias (char *newname, char *p) | |
2182 | { | |
2183 | enum arm_reg_type basetype; | |
2184 | struct reg_entry *basereg; | |
2185 | struct reg_entry mybasereg; | |
2186 | struct neon_type ntype; | |
2187 | struct neon_typed_alias typeinfo; | |
2188 | char *namebuf, *nameend; | |
2189 | int namelen; | |
5f4273c7 | 2190 | |
dcbf9037 JB |
2191 | typeinfo.defined = 0; |
2192 | typeinfo.eltype.type = NT_invtype; | |
2193 | typeinfo.eltype.size = -1; | |
2194 | typeinfo.index = -1; | |
5f4273c7 | 2195 | |
dcbf9037 | 2196 | nameend = p; |
5f4273c7 | 2197 | |
dcbf9037 JB |
2198 | if (strncmp (p, " .dn ", 5) == 0) |
2199 | basetype = REG_TYPE_VFD; | |
2200 | else if (strncmp (p, " .qn ", 5) == 0) | |
2201 | basetype = REG_TYPE_NQ; | |
2202 | else | |
2203 | return 0; | |
5f4273c7 | 2204 | |
dcbf9037 | 2205 | p += 5; |
5f4273c7 | 2206 | |
dcbf9037 JB |
2207 | if (*p == '\0') |
2208 | return 0; | |
5f4273c7 | 2209 | |
dcbf9037 JB |
2210 | basereg = arm_reg_parse_multi (&p); |
2211 | ||
2212 | if (basereg && basereg->type != basetype) | |
2213 | { | |
2214 | as_bad (_("bad type for register")); | |
2215 | return 0; | |
2216 | } | |
2217 | ||
2218 | if (basereg == NULL) | |
2219 | { | |
2220 | expressionS exp; | |
2221 | /* Try parsing as an integer. */ | |
2222 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
2223 | if (exp.X_op != O_constant) | |
2224 | { | |
2225 | as_bad (_("expression must be constant")); | |
2226 | return 0; | |
2227 | } | |
2228 | basereg = &mybasereg; | |
2229 | basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 | |
2230 | : exp.X_add_number; | |
2231 | basereg->neon = 0; | |
2232 | } | |
2233 | ||
2234 | if (basereg->neon) | |
2235 | typeinfo = *basereg->neon; | |
2236 | ||
2237 | if (parse_neon_type (&ntype, &p) == SUCCESS) | |
2238 | { | |
2239 | /* We got a type. */ | |
2240 | if (typeinfo.defined & NTA_HASTYPE) | |
2241 | { | |
2242 | as_bad (_("can't redefine the type of a register alias")); | |
2243 | return 0; | |
2244 | } | |
5f4273c7 | 2245 | |
dcbf9037 JB |
2246 | typeinfo.defined |= NTA_HASTYPE; |
2247 | if (ntype.elems != 1) | |
2248 | { | |
2249 | as_bad (_("you must specify a single type only")); | |
2250 | return 0; | |
2251 | } | |
2252 | typeinfo.eltype = ntype.el[0]; | |
2253 | } | |
5f4273c7 | 2254 | |
dcbf9037 JB |
2255 | if (skip_past_char (&p, '[') == SUCCESS) |
2256 | { | |
2257 | expressionS exp; | |
2258 | /* We got a scalar index. */ | |
5f4273c7 | 2259 | |
dcbf9037 JB |
2260 | if (typeinfo.defined & NTA_HASINDEX) |
2261 | { | |
2262 | as_bad (_("can't redefine the index of a scalar alias")); | |
2263 | return 0; | |
2264 | } | |
5f4273c7 | 2265 | |
dcbf9037 | 2266 | my_get_expression (&exp, &p, GE_NO_PREFIX); |
5f4273c7 | 2267 | |
dcbf9037 JB |
2268 | if (exp.X_op != O_constant) |
2269 | { | |
2270 | as_bad (_("scalar index must be constant")); | |
2271 | return 0; | |
2272 | } | |
5f4273c7 | 2273 | |
dcbf9037 JB |
2274 | typeinfo.defined |= NTA_HASINDEX; |
2275 | typeinfo.index = exp.X_add_number; | |
5f4273c7 | 2276 | |
dcbf9037 JB |
2277 | if (skip_past_char (&p, ']') == FAIL) |
2278 | { | |
2279 | as_bad (_("expecting ]")); | |
2280 | return 0; | |
2281 | } | |
2282 | } | |
2283 | ||
2284 | namelen = nameend - newname; | |
2285 | namebuf = alloca (namelen + 1); | |
2286 | strncpy (namebuf, newname, namelen); | |
2287 | namebuf[namelen] = '\0'; | |
5f4273c7 | 2288 | |
dcbf9037 JB |
2289 | insert_neon_reg_alias (namebuf, basereg->number, basetype, |
2290 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2291 | |
dcbf9037 JB |
2292 | /* Insert name in all uppercase. */ |
2293 | for (p = namebuf; *p; p++) | |
2294 | *p = TOUPPER (*p); | |
5f4273c7 | 2295 | |
dcbf9037 JB |
2296 | if (strncmp (namebuf, newname, namelen)) |
2297 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2298 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2299 | |
dcbf9037 JB |
2300 | /* Insert name in all lowercase. */ |
2301 | for (p = namebuf; *p; p++) | |
2302 | *p = TOLOWER (*p); | |
5f4273c7 | 2303 | |
dcbf9037 JB |
2304 | if (strncmp (namebuf, newname, namelen)) |
2305 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2306 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2307 | |
dcbf9037 JB |
2308 | return 1; |
2309 | } | |
2310 | ||
c19d1205 ZW |
2311 | /* Should never be called, as .req goes between the alias and the |
2312 | register name, not at the beginning of the line. */ | |
b99bd4ef | 2313 | static void |
c19d1205 | 2314 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2315 | { |
c19d1205 ZW |
2316 | as_bad (_("invalid syntax for .req directive")); |
2317 | } | |
b99bd4ef | 2318 | |
dcbf9037 JB |
2319 | static void |
2320 | s_dn (int a ATTRIBUTE_UNUSED) | |
2321 | { | |
2322 | as_bad (_("invalid syntax for .dn directive")); | |
2323 | } | |
2324 | ||
2325 | static void | |
2326 | s_qn (int a ATTRIBUTE_UNUSED) | |
2327 | { | |
2328 | as_bad (_("invalid syntax for .qn directive")); | |
2329 | } | |
2330 | ||
c19d1205 ZW |
2331 | /* The .unreq directive deletes an alias which was previously defined |
2332 | by .req. For example: | |
b99bd4ef | 2333 | |
c19d1205 ZW |
2334 | my_alias .req r11 |
2335 | .unreq my_alias */ | |
b99bd4ef NC |
2336 | |
2337 | static void | |
c19d1205 | 2338 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2339 | { |
c19d1205 ZW |
2340 | char * name; |
2341 | char saved_char; | |
b99bd4ef | 2342 | |
c19d1205 ZW |
2343 | name = input_line_pointer; |
2344 | ||
2345 | while (*input_line_pointer != 0 | |
2346 | && *input_line_pointer != ' ' | |
2347 | && *input_line_pointer != '\n') | |
2348 | ++input_line_pointer; | |
2349 | ||
2350 | saved_char = *input_line_pointer; | |
2351 | *input_line_pointer = 0; | |
2352 | ||
2353 | if (!*name) | |
2354 | as_bad (_("invalid syntax for .unreq directive")); | |
2355 | else | |
2356 | { | |
2357 | struct reg_entry *reg = hash_find (arm_reg_hsh, name); | |
2358 | ||
2359 | if (!reg) | |
2360 | as_bad (_("unknown register alias '%s'"), name); | |
2361 | else if (reg->builtin) | |
2362 | as_warn (_("ignoring attempt to undefine built-in register '%s'"), | |
2363 | name); | |
2364 | else | |
2365 | { | |
d929913e NC |
2366 | char * p; |
2367 | char * nbuf; | |
2368 | ||
db0bc284 | 2369 | hash_delete (arm_reg_hsh, name, FALSE); |
c19d1205 | 2370 | free ((char *) reg->name); |
dcbf9037 JB |
2371 | if (reg->neon) |
2372 | free (reg->neon); | |
c19d1205 | 2373 | free (reg); |
d929913e NC |
2374 | |
2375 | /* Also locate the all upper case and all lower case versions. | |
2376 | Do not complain if we cannot find one or the other as it | |
2377 | was probably deleted above. */ | |
5f4273c7 | 2378 | |
d929913e NC |
2379 | nbuf = strdup (name); |
2380 | for (p = nbuf; *p; p++) | |
2381 | *p = TOUPPER (*p); | |
2382 | reg = hash_find (arm_reg_hsh, nbuf); | |
2383 | if (reg) | |
2384 | { | |
db0bc284 | 2385 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2386 | free ((char *) reg->name); |
2387 | if (reg->neon) | |
2388 | free (reg->neon); | |
2389 | free (reg); | |
2390 | } | |
2391 | ||
2392 | for (p = nbuf; *p; p++) | |
2393 | *p = TOLOWER (*p); | |
2394 | reg = hash_find (arm_reg_hsh, nbuf); | |
2395 | if (reg) | |
2396 | { | |
db0bc284 | 2397 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2398 | free ((char *) reg->name); |
2399 | if (reg->neon) | |
2400 | free (reg->neon); | |
2401 | free (reg); | |
2402 | } | |
2403 | ||
2404 | free (nbuf); | |
c19d1205 ZW |
2405 | } |
2406 | } | |
b99bd4ef | 2407 | |
c19d1205 | 2408 | *input_line_pointer = saved_char; |
b99bd4ef NC |
2409 | demand_empty_rest_of_line (); |
2410 | } | |
2411 | ||
c19d1205 ZW |
2412 | /* Directives: Instruction set selection. */ |
2413 | ||
2414 | #ifdef OBJ_ELF | |
2415 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
2416 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
2417 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
2418 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
2419 | ||
2420 | static enum mstate mapstate = MAP_UNDEFINED; | |
b99bd4ef | 2421 | |
e821645d | 2422 | void |
c19d1205 | 2423 | mapping_state (enum mstate state) |
b99bd4ef | 2424 | { |
a737bd4d | 2425 | symbolS * symbolP; |
c19d1205 ZW |
2426 | const char * symname; |
2427 | int type; | |
b99bd4ef | 2428 | |
c19d1205 ZW |
2429 | if (mapstate == state) |
2430 | /* The mapping symbol has already been emitted. | |
2431 | There is nothing else to do. */ | |
2432 | return; | |
b99bd4ef | 2433 | |
c19d1205 | 2434 | mapstate = state; |
b99bd4ef | 2435 | |
c19d1205 | 2436 | switch (state) |
b99bd4ef | 2437 | { |
c19d1205 ZW |
2438 | case MAP_DATA: |
2439 | symname = "$d"; | |
2440 | type = BSF_NO_FLAGS; | |
2441 | break; | |
2442 | case MAP_ARM: | |
2443 | symname = "$a"; | |
2444 | type = BSF_NO_FLAGS; | |
2445 | break; | |
2446 | case MAP_THUMB: | |
2447 | symname = "$t"; | |
2448 | type = BSF_NO_FLAGS; | |
2449 | break; | |
2450 | case MAP_UNDEFINED: | |
2451 | return; | |
2452 | default: | |
2453 | abort (); | |
2454 | } | |
2455 | ||
2456 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; | |
2457 | ||
2458 | symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now); | |
2459 | symbol_table_insert (symbolP); | |
2460 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; | |
2461 | ||
2462 | switch (state) | |
2463 | { | |
2464 | case MAP_ARM: | |
2465 | THUMB_SET_FUNC (symbolP, 0); | |
2466 | ARM_SET_THUMB (symbolP, 0); | |
2467 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2468 | break; | |
2469 | ||
2470 | case MAP_THUMB: | |
2471 | THUMB_SET_FUNC (symbolP, 1); | |
2472 | ARM_SET_THUMB (symbolP, 1); | |
2473 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2474 | break; | |
2475 | ||
2476 | case MAP_DATA: | |
2477 | default: | |
2478 | return; | |
2479 | } | |
2480 | } | |
2481 | #else | |
2482 | #define mapping_state(x) /* nothing */ | |
2483 | #endif | |
2484 | ||
2485 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
2486 | ||
4343666d | 2487 | #ifdef OBJ_COFF |
c19d1205 ZW |
2488 | static symbolS * |
2489 | find_real_start (symbolS * symbolP) | |
2490 | { | |
2491 | char * real_start; | |
2492 | const char * name = S_GET_NAME (symbolP); | |
2493 | symbolS * new_target; | |
2494 | ||
2495 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
2496 | #define STUB_NAME ".real_start_of" | |
2497 | ||
2498 | if (name == NULL) | |
2499 | abort (); | |
2500 | ||
37f6032b ZW |
2501 | /* The compiler may generate BL instructions to local labels because |
2502 | it needs to perform a branch to a far away location. These labels | |
2503 | do not have a corresponding ".real_start_of" label. We check | |
2504 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
2505 | the ".real_start_of" convention for nonlocal branches. */ | |
2506 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
2507 | return symbolP; |
2508 | ||
37f6032b | 2509 | real_start = ACONCAT ((STUB_NAME, name, NULL)); |
c19d1205 ZW |
2510 | new_target = symbol_find (real_start); |
2511 | ||
2512 | if (new_target == NULL) | |
2513 | { | |
bd3ba5d1 | 2514 | as_warn (_("Failed to find real start of function: %s\n"), name); |
c19d1205 ZW |
2515 | new_target = symbolP; |
2516 | } | |
2517 | ||
c19d1205 ZW |
2518 | return new_target; |
2519 | } | |
4343666d | 2520 | #endif |
c19d1205 ZW |
2521 | |
2522 | static void | |
2523 | opcode_select (int width) | |
2524 | { | |
2525 | switch (width) | |
2526 | { | |
2527 | case 16: | |
2528 | if (! thumb_mode) | |
2529 | { | |
e74cfd16 | 2530 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
c19d1205 ZW |
2531 | as_bad (_("selected processor does not support THUMB opcodes")); |
2532 | ||
2533 | thumb_mode = 1; | |
2534 | /* No need to force the alignment, since we will have been | |
2535 | coming from ARM mode, which is word-aligned. */ | |
2536 | record_alignment (now_seg, 1); | |
2537 | } | |
2538 | mapping_state (MAP_THUMB); | |
2539 | break; | |
2540 | ||
2541 | case 32: | |
2542 | if (thumb_mode) | |
2543 | { | |
e74cfd16 | 2544 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 ZW |
2545 | as_bad (_("selected processor does not support ARM opcodes")); |
2546 | ||
2547 | thumb_mode = 0; | |
2548 | ||
2549 | if (!need_pass_2) | |
2550 | frag_align (2, 0, 0); | |
2551 | ||
2552 | record_alignment (now_seg, 1); | |
2553 | } | |
2554 | mapping_state (MAP_ARM); | |
2555 | break; | |
2556 | ||
2557 | default: | |
2558 | as_bad (_("invalid instruction size selected (%d)"), width); | |
2559 | } | |
2560 | } | |
2561 | ||
2562 | static void | |
2563 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
2564 | { | |
2565 | opcode_select (32); | |
2566 | demand_empty_rest_of_line (); | |
2567 | } | |
2568 | ||
2569 | static void | |
2570 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
2571 | { | |
2572 | opcode_select (16); | |
2573 | demand_empty_rest_of_line (); | |
2574 | } | |
2575 | ||
2576 | static void | |
2577 | s_code (int unused ATTRIBUTE_UNUSED) | |
2578 | { | |
2579 | int temp; | |
2580 | ||
2581 | temp = get_absolute_expression (); | |
2582 | switch (temp) | |
2583 | { | |
2584 | case 16: | |
2585 | case 32: | |
2586 | opcode_select (temp); | |
2587 | break; | |
2588 | ||
2589 | default: | |
2590 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
2591 | } | |
2592 | } | |
2593 | ||
2594 | static void | |
2595 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
2596 | { | |
2597 | /* If we are not already in thumb mode go into it, EVEN if | |
2598 | the target processor does not support thumb instructions. | |
2599 | This is used by gcc/config/arm/lib1funcs.asm for example | |
2600 | to compile interworking support functions even if the | |
2601 | target processor should not support interworking. */ | |
2602 | if (! thumb_mode) | |
2603 | { | |
2604 | thumb_mode = 2; | |
2605 | record_alignment (now_seg, 1); | |
2606 | } | |
2607 | ||
2608 | demand_empty_rest_of_line (); | |
2609 | } | |
2610 | ||
2611 | static void | |
2612 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
2613 | { | |
2614 | s_thumb (0); | |
2615 | ||
2616 | /* The following label is the name/address of the start of a Thumb function. | |
2617 | We need to know this for the interworking support. */ | |
2618 | label_is_thumb_function_name = TRUE; | |
2619 | } | |
2620 | ||
2621 | /* Perform a .set directive, but also mark the alias as | |
2622 | being a thumb function. */ | |
2623 | ||
2624 | static void | |
2625 | s_thumb_set (int equiv) | |
2626 | { | |
2627 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
2628 | We cannot just call that code as we need to get at the symbol that | |
2629 | is created. */ | |
2630 | char * name; | |
2631 | char delim; | |
2632 | char * end_name; | |
2633 | symbolS * symbolP; | |
2634 | ||
2635 | /* Especial apologies for the random logic: | |
2636 | This just grew, and could be parsed much more simply! | |
2637 | Dean - in haste. */ | |
2638 | name = input_line_pointer; | |
2639 | delim = get_symbol_end (); | |
2640 | end_name = input_line_pointer; | |
2641 | *end_name = delim; | |
2642 | ||
2643 | if (*input_line_pointer != ',') | |
2644 | { | |
2645 | *end_name = 0; | |
2646 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
2647 | *end_name = delim; |
2648 | ignore_rest_of_line (); | |
2649 | return; | |
2650 | } | |
2651 | ||
2652 | input_line_pointer++; | |
2653 | *end_name = 0; | |
2654 | ||
2655 | if (name[0] == '.' && name[1] == '\0') | |
2656 | { | |
2657 | /* XXX - this should not happen to .thumb_set. */ | |
2658 | abort (); | |
2659 | } | |
2660 | ||
2661 | if ((symbolP = symbol_find (name)) == NULL | |
2662 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
2663 | { | |
2664 | #ifndef NO_LISTING | |
2665 | /* When doing symbol listings, play games with dummy fragments living | |
2666 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 2667 | for this symbol. */ |
b99bd4ef NC |
2668 | if (listing & LISTING_SYMBOLS) |
2669 | { | |
2670 | extern struct list_info_struct * listing_tail; | |
a737bd4d | 2671 | fragS * dummy_frag = xmalloc (sizeof (fragS)); |
b99bd4ef NC |
2672 | |
2673 | memset (dummy_frag, 0, sizeof (fragS)); | |
2674 | dummy_frag->fr_type = rs_fill; | |
2675 | dummy_frag->line = listing_tail; | |
2676 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
2677 | dummy_frag->fr_symbol = symbolP; | |
2678 | } | |
2679 | else | |
2680 | #endif | |
2681 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
2682 | ||
2683 | #ifdef OBJ_COFF | |
2684 | /* "set" symbols are local unless otherwise specified. */ | |
2685 | SF_SET_LOCAL (symbolP); | |
2686 | #endif /* OBJ_COFF */ | |
2687 | } /* Make a new symbol. */ | |
2688 | ||
2689 | symbol_table_insert (symbolP); | |
2690 | ||
2691 | * end_name = delim; | |
2692 | ||
2693 | if (equiv | |
2694 | && S_IS_DEFINED (symbolP) | |
2695 | && S_GET_SEGMENT (symbolP) != reg_section) | |
2696 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
2697 | ||
2698 | pseudo_set (symbolP); | |
2699 | ||
2700 | demand_empty_rest_of_line (); | |
2701 | ||
c19d1205 | 2702 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
2703 | |
2704 | THUMB_SET_FUNC (symbolP, 1); | |
2705 | ARM_SET_THUMB (symbolP, 1); | |
2706 | #if defined OBJ_ELF || defined OBJ_COFF | |
2707 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2708 | #endif | |
2709 | } | |
2710 | ||
c19d1205 | 2711 | /* Directives: Mode selection. */ |
b99bd4ef | 2712 | |
c19d1205 ZW |
2713 | /* .syntax [unified|divided] - choose the new unified syntax |
2714 | (same for Arm and Thumb encoding, modulo slight differences in what | |
2715 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 2716 | static void |
c19d1205 | 2717 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2718 | { |
c19d1205 ZW |
2719 | char *name, delim; |
2720 | ||
2721 | name = input_line_pointer; | |
2722 | delim = get_symbol_end (); | |
2723 | ||
2724 | if (!strcasecmp (name, "unified")) | |
2725 | unified_syntax = TRUE; | |
2726 | else if (!strcasecmp (name, "divided")) | |
2727 | unified_syntax = FALSE; | |
2728 | else | |
2729 | { | |
2730 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
2731 | return; | |
2732 | } | |
2733 | *input_line_pointer = delim; | |
b99bd4ef NC |
2734 | demand_empty_rest_of_line (); |
2735 | } | |
2736 | ||
c19d1205 ZW |
2737 | /* Directives: sectioning and alignment. */ |
2738 | ||
2739 | /* Same as s_align_ptwo but align 0 => align 2. */ | |
2740 | ||
b99bd4ef | 2741 | static void |
c19d1205 | 2742 | s_align (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2743 | { |
a737bd4d | 2744 | int temp; |
dce323d1 | 2745 | bfd_boolean fill_p; |
c19d1205 ZW |
2746 | long temp_fill; |
2747 | long max_alignment = 15; | |
b99bd4ef NC |
2748 | |
2749 | temp = get_absolute_expression (); | |
c19d1205 ZW |
2750 | if (temp > max_alignment) |
2751 | as_bad (_("alignment too large: %d assumed"), temp = max_alignment); | |
2752 | else if (temp < 0) | |
b99bd4ef | 2753 | { |
c19d1205 ZW |
2754 | as_bad (_("alignment negative. 0 assumed.")); |
2755 | temp = 0; | |
2756 | } | |
b99bd4ef | 2757 | |
c19d1205 ZW |
2758 | if (*input_line_pointer == ',') |
2759 | { | |
2760 | input_line_pointer++; | |
2761 | temp_fill = get_absolute_expression (); | |
dce323d1 | 2762 | fill_p = TRUE; |
b99bd4ef | 2763 | } |
c19d1205 | 2764 | else |
dce323d1 PB |
2765 | { |
2766 | fill_p = FALSE; | |
2767 | temp_fill = 0; | |
2768 | } | |
b99bd4ef | 2769 | |
c19d1205 ZW |
2770 | if (!temp) |
2771 | temp = 2; | |
b99bd4ef | 2772 | |
c19d1205 ZW |
2773 | /* Only make a frag if we HAVE to. */ |
2774 | if (temp && !need_pass_2) | |
dce323d1 PB |
2775 | { |
2776 | if (!fill_p && subseg_text_p (now_seg)) | |
2777 | frag_align_code (temp, 0); | |
2778 | else | |
2779 | frag_align (temp, (int) temp_fill, 0); | |
2780 | } | |
c19d1205 ZW |
2781 | demand_empty_rest_of_line (); |
2782 | ||
2783 | record_alignment (now_seg, temp); | |
b99bd4ef NC |
2784 | } |
2785 | ||
c19d1205 ZW |
2786 | static void |
2787 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 2788 | { |
c19d1205 ZW |
2789 | /* We don't support putting frags in the BSS segment, we fake it by |
2790 | marking in_bss, then looking at s_skip for clues. */ | |
2791 | subseg_set (bss_section, 0); | |
2792 | demand_empty_rest_of_line (); | |
2793 | mapping_state (MAP_DATA); | |
2794 | } | |
b99bd4ef | 2795 | |
c19d1205 ZW |
2796 | static void |
2797 | s_even (int ignore ATTRIBUTE_UNUSED) | |
2798 | { | |
2799 | /* Never make frag if expect extra pass. */ | |
2800 | if (!need_pass_2) | |
2801 | frag_align (1, 0, 0); | |
b99bd4ef | 2802 | |
c19d1205 | 2803 | record_alignment (now_seg, 1); |
b99bd4ef | 2804 | |
c19d1205 | 2805 | demand_empty_rest_of_line (); |
b99bd4ef NC |
2806 | } |
2807 | ||
c19d1205 | 2808 | /* Directives: Literal pools. */ |
a737bd4d | 2809 | |
c19d1205 ZW |
2810 | static literal_pool * |
2811 | find_literal_pool (void) | |
a737bd4d | 2812 | { |
c19d1205 | 2813 | literal_pool * pool; |
a737bd4d | 2814 | |
c19d1205 | 2815 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 2816 | { |
c19d1205 ZW |
2817 | if (pool->section == now_seg |
2818 | && pool->sub_section == now_subseg) | |
2819 | break; | |
a737bd4d NC |
2820 | } |
2821 | ||
c19d1205 | 2822 | return pool; |
a737bd4d NC |
2823 | } |
2824 | ||
c19d1205 ZW |
2825 | static literal_pool * |
2826 | find_or_make_literal_pool (void) | |
a737bd4d | 2827 | { |
c19d1205 ZW |
2828 | /* Next literal pool ID number. */ |
2829 | static unsigned int latest_pool_num = 1; | |
2830 | literal_pool * pool; | |
a737bd4d | 2831 | |
c19d1205 | 2832 | pool = find_literal_pool (); |
a737bd4d | 2833 | |
c19d1205 | 2834 | if (pool == NULL) |
a737bd4d | 2835 | { |
c19d1205 ZW |
2836 | /* Create a new pool. */ |
2837 | pool = xmalloc (sizeof (* pool)); | |
2838 | if (! pool) | |
2839 | return NULL; | |
a737bd4d | 2840 | |
c19d1205 ZW |
2841 | pool->next_free_entry = 0; |
2842 | pool->section = now_seg; | |
2843 | pool->sub_section = now_subseg; | |
2844 | pool->next = list_of_pools; | |
2845 | pool->symbol = NULL; | |
2846 | ||
2847 | /* Add it to the list. */ | |
2848 | list_of_pools = pool; | |
a737bd4d | 2849 | } |
a737bd4d | 2850 | |
c19d1205 ZW |
2851 | /* New pools, and emptied pools, will have a NULL symbol. */ |
2852 | if (pool->symbol == NULL) | |
a737bd4d | 2853 | { |
c19d1205 ZW |
2854 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
2855 | (valueT) 0, &zero_address_frag); | |
2856 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
2857 | } |
2858 | ||
c19d1205 ZW |
2859 | /* Done. */ |
2860 | return pool; | |
a737bd4d NC |
2861 | } |
2862 | ||
c19d1205 | 2863 | /* Add the literal in the global 'inst' |
5f4273c7 | 2864 | structure to the relevant literal pool. */ |
b99bd4ef NC |
2865 | |
2866 | static int | |
c19d1205 | 2867 | add_to_lit_pool (void) |
b99bd4ef | 2868 | { |
c19d1205 ZW |
2869 | literal_pool * pool; |
2870 | unsigned int entry; | |
b99bd4ef | 2871 | |
c19d1205 ZW |
2872 | pool = find_or_make_literal_pool (); |
2873 | ||
2874 | /* Check if this literal value is already in the pool. */ | |
2875 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 2876 | { |
c19d1205 ZW |
2877 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) |
2878 | && (inst.reloc.exp.X_op == O_constant) | |
2879 | && (pool->literals[entry].X_add_number | |
2880 | == inst.reloc.exp.X_add_number) | |
2881 | && (pool->literals[entry].X_unsigned | |
2882 | == inst.reloc.exp.X_unsigned)) | |
2883 | break; | |
2884 | ||
2885 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
2886 | && (inst.reloc.exp.X_op == O_symbol) | |
2887 | && (pool->literals[entry].X_add_number | |
2888 | == inst.reloc.exp.X_add_number) | |
2889 | && (pool->literals[entry].X_add_symbol | |
2890 | == inst.reloc.exp.X_add_symbol) | |
2891 | && (pool->literals[entry].X_op_symbol | |
2892 | == inst.reloc.exp.X_op_symbol)) | |
2893 | break; | |
b99bd4ef NC |
2894 | } |
2895 | ||
c19d1205 ZW |
2896 | /* Do we need to create a new entry? */ |
2897 | if (entry == pool->next_free_entry) | |
2898 | { | |
2899 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
2900 | { | |
2901 | inst.error = _("literal pool overflow"); | |
2902 | return FAIL; | |
2903 | } | |
2904 | ||
2905 | pool->literals[entry] = inst.reloc.exp; | |
2906 | pool->next_free_entry += 1; | |
2907 | } | |
b99bd4ef | 2908 | |
c19d1205 ZW |
2909 | inst.reloc.exp.X_op = O_symbol; |
2910 | inst.reloc.exp.X_add_number = ((int) entry) * 4; | |
2911 | inst.reloc.exp.X_add_symbol = pool->symbol; | |
b99bd4ef | 2912 | |
c19d1205 | 2913 | return SUCCESS; |
b99bd4ef NC |
2914 | } |
2915 | ||
c19d1205 ZW |
2916 | /* Can't use symbol_new here, so have to create a symbol and then at |
2917 | a later date assign it a value. Thats what these functions do. */ | |
e16bb312 | 2918 | |
c19d1205 ZW |
2919 | static void |
2920 | symbol_locate (symbolS * symbolP, | |
2921 | const char * name, /* It is copied, the caller can modify. */ | |
2922 | segT segment, /* Segment identifier (SEG_<something>). */ | |
2923 | valueT valu, /* Symbol value. */ | |
2924 | fragS * frag) /* Associated fragment. */ | |
2925 | { | |
2926 | unsigned int name_length; | |
2927 | char * preserved_copy_of_name; | |
e16bb312 | 2928 | |
c19d1205 ZW |
2929 | name_length = strlen (name) + 1; /* +1 for \0. */ |
2930 | obstack_grow (¬es, name, name_length); | |
2931 | preserved_copy_of_name = obstack_finish (¬es); | |
e16bb312 | 2932 | |
c19d1205 ZW |
2933 | #ifdef tc_canonicalize_symbol_name |
2934 | preserved_copy_of_name = | |
2935 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
2936 | #endif | |
b99bd4ef | 2937 | |
c19d1205 | 2938 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 2939 | |
c19d1205 ZW |
2940 | S_SET_SEGMENT (symbolP, segment); |
2941 | S_SET_VALUE (symbolP, valu); | |
2942 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 2943 | |
c19d1205 | 2944 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 2945 | |
c19d1205 ZW |
2946 | /* Link to end of symbol chain. */ |
2947 | { | |
2948 | extern int symbol_table_frozen; | |
b99bd4ef | 2949 | |
c19d1205 ZW |
2950 | if (symbol_table_frozen) |
2951 | abort (); | |
2952 | } | |
b99bd4ef | 2953 | |
c19d1205 | 2954 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 2955 | |
c19d1205 | 2956 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 2957 | |
c19d1205 ZW |
2958 | #ifdef tc_symbol_new_hook |
2959 | tc_symbol_new_hook (symbolP); | |
2960 | #endif | |
2961 | ||
2962 | #ifdef DEBUG_SYMS | |
2963 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
2964 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
2965 | } |
2966 | ||
b99bd4ef | 2967 | |
c19d1205 ZW |
2968 | static void |
2969 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 2970 | { |
c19d1205 ZW |
2971 | unsigned int entry; |
2972 | literal_pool * pool; | |
2973 | char sym_name[20]; | |
b99bd4ef | 2974 | |
c19d1205 ZW |
2975 | pool = find_literal_pool (); |
2976 | if (pool == NULL | |
2977 | || pool->symbol == NULL | |
2978 | || pool->next_free_entry == 0) | |
2979 | return; | |
b99bd4ef | 2980 | |
c19d1205 | 2981 | mapping_state (MAP_DATA); |
b99bd4ef | 2982 | |
c19d1205 ZW |
2983 | /* Align pool as you have word accesses. |
2984 | Only make a frag if we have to. */ | |
2985 | if (!need_pass_2) | |
2986 | frag_align (2, 0, 0); | |
b99bd4ef | 2987 | |
c19d1205 | 2988 | record_alignment (now_seg, 2); |
b99bd4ef | 2989 | |
c19d1205 | 2990 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 2991 | |
c19d1205 ZW |
2992 | symbol_locate (pool->symbol, sym_name, now_seg, |
2993 | (valueT) frag_now_fix (), frag_now); | |
2994 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 2995 | |
c19d1205 | 2996 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 2997 | |
c19d1205 ZW |
2998 | #if defined OBJ_COFF || defined OBJ_ELF |
2999 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
3000 | #endif | |
6c43fab6 | 3001 | |
c19d1205 ZW |
3002 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
3003 | /* First output the expression in the instruction to the pool. */ | |
3004 | emit_expr (&(pool->literals[entry]), 4); /* .word */ | |
b99bd4ef | 3005 | |
c19d1205 ZW |
3006 | /* Mark the pool as empty. */ |
3007 | pool->next_free_entry = 0; | |
3008 | pool->symbol = NULL; | |
b99bd4ef NC |
3009 | } |
3010 | ||
c19d1205 ZW |
3011 | #ifdef OBJ_ELF |
3012 | /* Forward declarations for functions below, in the MD interface | |
3013 | section. */ | |
3014 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
3015 | static valueT create_unwind_entry (int); | |
3016 | static void start_unwind_section (const segT, int); | |
3017 | static void add_unwind_opcode (valueT, int); | |
3018 | static void flush_pending_unwind (void); | |
b99bd4ef | 3019 | |
c19d1205 | 3020 | /* Directives: Data. */ |
b99bd4ef | 3021 | |
c19d1205 ZW |
3022 | static void |
3023 | s_arm_elf_cons (int nbytes) | |
3024 | { | |
3025 | expressionS exp; | |
b99bd4ef | 3026 | |
c19d1205 ZW |
3027 | #ifdef md_flush_pending_output |
3028 | md_flush_pending_output (); | |
3029 | #endif | |
b99bd4ef | 3030 | |
c19d1205 | 3031 | if (is_it_end_of_statement ()) |
b99bd4ef | 3032 | { |
c19d1205 ZW |
3033 | demand_empty_rest_of_line (); |
3034 | return; | |
b99bd4ef NC |
3035 | } |
3036 | ||
c19d1205 ZW |
3037 | #ifdef md_cons_align |
3038 | md_cons_align (nbytes); | |
3039 | #endif | |
b99bd4ef | 3040 | |
c19d1205 ZW |
3041 | mapping_state (MAP_DATA); |
3042 | do | |
b99bd4ef | 3043 | { |
c19d1205 ZW |
3044 | int reloc; |
3045 | char *base = input_line_pointer; | |
b99bd4ef | 3046 | |
c19d1205 | 3047 | expression (& exp); |
b99bd4ef | 3048 | |
c19d1205 ZW |
3049 | if (exp.X_op != O_symbol) |
3050 | emit_expr (&exp, (unsigned int) nbytes); | |
3051 | else | |
3052 | { | |
3053 | char *before_reloc = input_line_pointer; | |
3054 | reloc = parse_reloc (&input_line_pointer); | |
3055 | if (reloc == -1) | |
3056 | { | |
3057 | as_bad (_("unrecognized relocation suffix")); | |
3058 | ignore_rest_of_line (); | |
3059 | return; | |
3060 | } | |
3061 | else if (reloc == BFD_RELOC_UNUSED) | |
3062 | emit_expr (&exp, (unsigned int) nbytes); | |
3063 | else | |
3064 | { | |
3065 | reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc); | |
3066 | int size = bfd_get_reloc_size (howto); | |
b99bd4ef | 3067 | |
2fc8bdac ZW |
3068 | if (reloc == BFD_RELOC_ARM_PLT32) |
3069 | { | |
3070 | as_bad (_("(plt) is only valid on branch targets")); | |
3071 | reloc = BFD_RELOC_UNUSED; | |
3072 | size = 0; | |
3073 | } | |
3074 | ||
c19d1205 | 3075 | if (size > nbytes) |
2fc8bdac | 3076 | as_bad (_("%s relocations do not fit in %d bytes"), |
c19d1205 ZW |
3077 | howto->name, nbytes); |
3078 | else | |
3079 | { | |
3080 | /* We've parsed an expression stopping at O_symbol. | |
3081 | But there may be more expression left now that we | |
3082 | have parsed the relocation marker. Parse it again. | |
3083 | XXX Surely there is a cleaner way to do this. */ | |
3084 | char *p = input_line_pointer; | |
3085 | int offset; | |
3086 | char *save_buf = alloca (input_line_pointer - base); | |
3087 | memcpy (save_buf, base, input_line_pointer - base); | |
3088 | memmove (base + (input_line_pointer - before_reloc), | |
3089 | base, before_reloc - base); | |
3090 | ||
3091 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
3092 | expression (&exp); | |
3093 | memcpy (base, save_buf, p - base); | |
3094 | ||
3095 | offset = nbytes - size; | |
3096 | p = frag_more ((int) nbytes); | |
3097 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, | |
3098 | size, &exp, 0, reloc); | |
3099 | } | |
3100 | } | |
3101 | } | |
b99bd4ef | 3102 | } |
c19d1205 | 3103 | while (*input_line_pointer++ == ','); |
b99bd4ef | 3104 | |
c19d1205 ZW |
3105 | /* Put terminator back into stream. */ |
3106 | input_line_pointer --; | |
3107 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
3108 | } |
3109 | ||
b99bd4ef | 3110 | |
c19d1205 | 3111 | /* Parse a .rel31 directive. */ |
b99bd4ef | 3112 | |
c19d1205 ZW |
3113 | static void |
3114 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
3115 | { | |
3116 | expressionS exp; | |
3117 | char *p; | |
3118 | valueT highbit; | |
b99bd4ef | 3119 | |
c19d1205 ZW |
3120 | highbit = 0; |
3121 | if (*input_line_pointer == '1') | |
3122 | highbit = 0x80000000; | |
3123 | else if (*input_line_pointer != '0') | |
3124 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 3125 | |
c19d1205 ZW |
3126 | input_line_pointer++; |
3127 | if (*input_line_pointer != ',') | |
3128 | as_bad (_("missing comma")); | |
3129 | input_line_pointer++; | |
b99bd4ef | 3130 | |
c19d1205 ZW |
3131 | #ifdef md_flush_pending_output |
3132 | md_flush_pending_output (); | |
3133 | #endif | |
b99bd4ef | 3134 | |
c19d1205 ZW |
3135 | #ifdef md_cons_align |
3136 | md_cons_align (4); | |
3137 | #endif | |
b99bd4ef | 3138 | |
c19d1205 | 3139 | mapping_state (MAP_DATA); |
b99bd4ef | 3140 | |
c19d1205 | 3141 | expression (&exp); |
b99bd4ef | 3142 | |
c19d1205 ZW |
3143 | p = frag_more (4); |
3144 | md_number_to_chars (p, highbit, 4); | |
3145 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
3146 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 3147 | |
c19d1205 | 3148 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3149 | } |
3150 | ||
c19d1205 | 3151 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 3152 | |
c19d1205 | 3153 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 3154 | |
c19d1205 ZW |
3155 | static void |
3156 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
3157 | { | |
3158 | demand_empty_rest_of_line (); | |
3159 | /* Mark the start of the function. */ | |
3160 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 3161 | |
c19d1205 ZW |
3162 | /* Reset the rest of the unwind info. */ |
3163 | unwind.opcode_count = 0; | |
3164 | unwind.table_entry = NULL; | |
3165 | unwind.personality_routine = NULL; | |
3166 | unwind.personality_index = -1; | |
3167 | unwind.frame_size = 0; | |
3168 | unwind.fp_offset = 0; | |
fdfde340 | 3169 | unwind.fp_reg = REG_SP; |
c19d1205 ZW |
3170 | unwind.fp_used = 0; |
3171 | unwind.sp_restored = 0; | |
3172 | } | |
b99bd4ef | 3173 | |
b99bd4ef | 3174 | |
c19d1205 ZW |
3175 | /* Parse a handlerdata directive. Creates the exception handling table entry |
3176 | for the function. */ | |
b99bd4ef | 3177 | |
c19d1205 ZW |
3178 | static void |
3179 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
3180 | { | |
3181 | demand_empty_rest_of_line (); | |
3182 | if (unwind.table_entry) | |
6decc662 | 3183 | as_bad (_("duplicate .handlerdata directive")); |
f02232aa | 3184 | |
c19d1205 ZW |
3185 | create_unwind_entry (1); |
3186 | } | |
a737bd4d | 3187 | |
c19d1205 | 3188 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 3189 | |
c19d1205 ZW |
3190 | static void |
3191 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
3192 | { | |
3193 | long where; | |
3194 | char *ptr; | |
3195 | valueT val; | |
f02232aa | 3196 | |
c19d1205 | 3197 | demand_empty_rest_of_line (); |
f02232aa | 3198 | |
c19d1205 ZW |
3199 | /* Add eh table entry. */ |
3200 | if (unwind.table_entry == NULL) | |
3201 | val = create_unwind_entry (0); | |
3202 | else | |
3203 | val = 0; | |
f02232aa | 3204 | |
c19d1205 ZW |
3205 | /* Add index table entry. This is two words. */ |
3206 | start_unwind_section (unwind.saved_seg, 1); | |
3207 | frag_align (2, 0, 0); | |
3208 | record_alignment (now_seg, 2); | |
b99bd4ef | 3209 | |
c19d1205 ZW |
3210 | ptr = frag_more (8); |
3211 | where = frag_now_fix () - 8; | |
f02232aa | 3212 | |
c19d1205 ZW |
3213 | /* Self relative offset of the function start. */ |
3214 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
3215 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3216 | |
c19d1205 ZW |
3217 | /* Indicate dependency on EHABI-defined personality routines to the |
3218 | linker, if it hasn't been done already. */ | |
3219 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 | |
3220 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
3221 | { | |
5f4273c7 NC |
3222 | static const char *const name[] = |
3223 | { | |
3224 | "__aeabi_unwind_cpp_pr0", | |
3225 | "__aeabi_unwind_cpp_pr1", | |
3226 | "__aeabi_unwind_cpp_pr2" | |
3227 | }; | |
c19d1205 ZW |
3228 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); |
3229 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
3230 | marked_pr_dependency |= 1 << unwind.personality_index; | |
3231 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency | |
3232 | = marked_pr_dependency; | |
3233 | } | |
f02232aa | 3234 | |
c19d1205 ZW |
3235 | if (val) |
3236 | /* Inline exception table entry. */ | |
3237 | md_number_to_chars (ptr + 4, val, 4); | |
3238 | else | |
3239 | /* Self relative offset of the table entry. */ | |
3240 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
3241 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3242 | |
c19d1205 ZW |
3243 | /* Restore the original section. */ |
3244 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
3245 | } | |
f02232aa | 3246 | |
f02232aa | 3247 | |
c19d1205 | 3248 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 3249 | |
c19d1205 ZW |
3250 | static void |
3251 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
3252 | { | |
3253 | demand_empty_rest_of_line (); | |
3254 | if (unwind.personality_routine || unwind.personality_index != -1) | |
3255 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 3256 | |
c19d1205 ZW |
3257 | unwind.personality_index = -2; |
3258 | } | |
b99bd4ef | 3259 | |
b99bd4ef | 3260 | |
c19d1205 | 3261 | /* Parse a personalityindex directive. */ |
b99bd4ef | 3262 | |
c19d1205 ZW |
3263 | static void |
3264 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
3265 | { | |
3266 | expressionS exp; | |
b99bd4ef | 3267 | |
c19d1205 ZW |
3268 | if (unwind.personality_routine || unwind.personality_index != -1) |
3269 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 3270 | |
c19d1205 | 3271 | expression (&exp); |
b99bd4ef | 3272 | |
c19d1205 ZW |
3273 | if (exp.X_op != O_constant |
3274 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 3275 | { |
c19d1205 ZW |
3276 | as_bad (_("bad personality routine number")); |
3277 | ignore_rest_of_line (); | |
3278 | return; | |
b99bd4ef NC |
3279 | } |
3280 | ||
c19d1205 | 3281 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 3282 | |
c19d1205 ZW |
3283 | demand_empty_rest_of_line (); |
3284 | } | |
e16bb312 | 3285 | |
e16bb312 | 3286 | |
c19d1205 | 3287 | /* Parse a personality directive. */ |
e16bb312 | 3288 | |
c19d1205 ZW |
3289 | static void |
3290 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
3291 | { | |
3292 | char *name, *p, c; | |
a737bd4d | 3293 | |
c19d1205 ZW |
3294 | if (unwind.personality_routine || unwind.personality_index != -1) |
3295 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 3296 | |
c19d1205 ZW |
3297 | name = input_line_pointer; |
3298 | c = get_symbol_end (); | |
3299 | p = input_line_pointer; | |
3300 | unwind.personality_routine = symbol_find_or_make (name); | |
3301 | *p = c; | |
3302 | demand_empty_rest_of_line (); | |
3303 | } | |
e16bb312 | 3304 | |
e16bb312 | 3305 | |
c19d1205 | 3306 | /* Parse a directive saving core registers. */ |
e16bb312 | 3307 | |
c19d1205 ZW |
3308 | static void |
3309 | s_arm_unwind_save_core (void) | |
e16bb312 | 3310 | { |
c19d1205 ZW |
3311 | valueT op; |
3312 | long range; | |
3313 | int n; | |
e16bb312 | 3314 | |
c19d1205 ZW |
3315 | range = parse_reg_list (&input_line_pointer); |
3316 | if (range == FAIL) | |
e16bb312 | 3317 | { |
c19d1205 ZW |
3318 | as_bad (_("expected register list")); |
3319 | ignore_rest_of_line (); | |
3320 | return; | |
3321 | } | |
e16bb312 | 3322 | |
c19d1205 | 3323 | demand_empty_rest_of_line (); |
e16bb312 | 3324 | |
c19d1205 ZW |
3325 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
3326 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
3327 | ip because it is clobbered by calls. */ | |
3328 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
3329 | && (range & 0x3000) == 0x1000) | |
3330 | { | |
3331 | unwind.opcode_count--; | |
3332 | unwind.sp_restored = 0; | |
3333 | range = (range | 0x2000) & ~0x1000; | |
3334 | unwind.pending_offset = 0; | |
3335 | } | |
e16bb312 | 3336 | |
01ae4198 DJ |
3337 | /* Pop r4-r15. */ |
3338 | if (range & 0xfff0) | |
c19d1205 | 3339 | { |
01ae4198 DJ |
3340 | /* See if we can use the short opcodes. These pop a block of up to 8 |
3341 | registers starting with r4, plus maybe r14. */ | |
3342 | for (n = 0; n < 8; n++) | |
3343 | { | |
3344 | /* Break at the first non-saved register. */ | |
3345 | if ((range & (1 << (n + 4))) == 0) | |
3346 | break; | |
3347 | } | |
3348 | /* See if there are any other bits set. */ | |
3349 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
3350 | { | |
3351 | /* Use the long form. */ | |
3352 | op = 0x8000 | ((range >> 4) & 0xfff); | |
3353 | add_unwind_opcode (op, 2); | |
3354 | } | |
0dd132b6 | 3355 | else |
01ae4198 DJ |
3356 | { |
3357 | /* Use the short form. */ | |
3358 | if (range & 0x4000) | |
3359 | op = 0xa8; /* Pop r14. */ | |
3360 | else | |
3361 | op = 0xa0; /* Do not pop r14. */ | |
3362 | op |= (n - 1); | |
3363 | add_unwind_opcode (op, 1); | |
3364 | } | |
c19d1205 | 3365 | } |
0dd132b6 | 3366 | |
c19d1205 ZW |
3367 | /* Pop r0-r3. */ |
3368 | if (range & 0xf) | |
3369 | { | |
3370 | op = 0xb100 | (range & 0xf); | |
3371 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
3372 | } |
3373 | ||
c19d1205 ZW |
3374 | /* Record the number of bytes pushed. */ |
3375 | for (n = 0; n < 16; n++) | |
3376 | { | |
3377 | if (range & (1 << n)) | |
3378 | unwind.frame_size += 4; | |
3379 | } | |
0dd132b6 NC |
3380 | } |
3381 | ||
c19d1205 ZW |
3382 | |
3383 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
3384 | |
3385 | static void | |
c19d1205 | 3386 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 3387 | { |
c19d1205 ZW |
3388 | expressionS exp; |
3389 | int num_regs; | |
3390 | valueT op; | |
b99bd4ef | 3391 | |
c19d1205 ZW |
3392 | /* Get Number of registers to transfer. */ |
3393 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
3394 | expression (&exp); | |
3395 | else | |
3396 | exp.X_op = O_illegal; | |
b99bd4ef | 3397 | |
c19d1205 | 3398 | if (exp.X_op != O_constant) |
b99bd4ef | 3399 | { |
c19d1205 ZW |
3400 | as_bad (_("expected , <constant>")); |
3401 | ignore_rest_of_line (); | |
b99bd4ef NC |
3402 | return; |
3403 | } | |
3404 | ||
c19d1205 ZW |
3405 | num_regs = exp.X_add_number; |
3406 | ||
3407 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 3408 | { |
c19d1205 ZW |
3409 | as_bad (_("number of registers must be in the range [1:4]")); |
3410 | ignore_rest_of_line (); | |
b99bd4ef NC |
3411 | return; |
3412 | } | |
3413 | ||
c19d1205 | 3414 | demand_empty_rest_of_line (); |
b99bd4ef | 3415 | |
c19d1205 ZW |
3416 | if (reg == 4) |
3417 | { | |
3418 | /* Short form. */ | |
3419 | op = 0xb4 | (num_regs - 1); | |
3420 | add_unwind_opcode (op, 1); | |
3421 | } | |
b99bd4ef NC |
3422 | else |
3423 | { | |
c19d1205 ZW |
3424 | /* Long form. */ |
3425 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
3426 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3427 | } |
c19d1205 | 3428 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
3429 | } |
3430 | ||
c19d1205 | 3431 | |
fa073d69 MS |
3432 | /* Parse a directive saving VFP registers for ARMv6 and above. */ |
3433 | ||
3434 | static void | |
3435 | s_arm_unwind_save_vfp_armv6 (void) | |
3436 | { | |
3437 | int count; | |
3438 | unsigned int start; | |
3439 | valueT op; | |
3440 | int num_vfpv3_regs = 0; | |
3441 | int num_regs_below_16; | |
3442 | ||
3443 | count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); | |
3444 | if (count == FAIL) | |
3445 | { | |
3446 | as_bad (_("expected register list")); | |
3447 | ignore_rest_of_line (); | |
3448 | return; | |
3449 | } | |
3450 | ||
3451 | demand_empty_rest_of_line (); | |
3452 | ||
3453 | /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather | |
3454 | than FSTMX/FLDMX-style ones). */ | |
3455 | ||
3456 | /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ | |
3457 | if (start >= 16) | |
3458 | num_vfpv3_regs = count; | |
3459 | else if (start + count > 16) | |
3460 | num_vfpv3_regs = start + count - 16; | |
3461 | ||
3462 | if (num_vfpv3_regs > 0) | |
3463 | { | |
3464 | int start_offset = start > 16 ? start - 16 : 0; | |
3465 | op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); | |
3466 | add_unwind_opcode (op, 2); | |
3467 | } | |
3468 | ||
3469 | /* Generate opcode for registers numbered in the range 0 .. 15. */ | |
3470 | num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; | |
3471 | assert (num_regs_below_16 + num_vfpv3_regs == count); | |
3472 | if (num_regs_below_16 > 0) | |
3473 | { | |
3474 | op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); | |
3475 | add_unwind_opcode (op, 2); | |
3476 | } | |
3477 | ||
3478 | unwind.frame_size += count * 8; | |
3479 | } | |
3480 | ||
3481 | ||
3482 | /* Parse a directive saving VFP registers for pre-ARMv6. */ | |
b99bd4ef NC |
3483 | |
3484 | static void | |
c19d1205 | 3485 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 3486 | { |
c19d1205 | 3487 | int count; |
ca3f61f7 | 3488 | unsigned int reg; |
c19d1205 | 3489 | valueT op; |
b99bd4ef | 3490 | |
5287ad62 | 3491 | count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); |
c19d1205 | 3492 | if (count == FAIL) |
b99bd4ef | 3493 | { |
c19d1205 ZW |
3494 | as_bad (_("expected register list")); |
3495 | ignore_rest_of_line (); | |
b99bd4ef NC |
3496 | return; |
3497 | } | |
3498 | ||
c19d1205 | 3499 | demand_empty_rest_of_line (); |
b99bd4ef | 3500 | |
c19d1205 | 3501 | if (reg == 8) |
b99bd4ef | 3502 | { |
c19d1205 ZW |
3503 | /* Short form. */ |
3504 | op = 0xb8 | (count - 1); | |
3505 | add_unwind_opcode (op, 1); | |
b99bd4ef | 3506 | } |
c19d1205 | 3507 | else |
b99bd4ef | 3508 | { |
c19d1205 ZW |
3509 | /* Long form. */ |
3510 | op = 0xb300 | (reg << 4) | (count - 1); | |
3511 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3512 | } |
c19d1205 ZW |
3513 | unwind.frame_size += count * 8 + 4; |
3514 | } | |
b99bd4ef | 3515 | |
b99bd4ef | 3516 | |
c19d1205 ZW |
3517 | /* Parse a directive saving iWMMXt data registers. */ |
3518 | ||
3519 | static void | |
3520 | s_arm_unwind_save_mmxwr (void) | |
3521 | { | |
3522 | int reg; | |
3523 | int hi_reg; | |
3524 | int i; | |
3525 | unsigned mask = 0; | |
3526 | valueT op; | |
b99bd4ef | 3527 | |
c19d1205 ZW |
3528 | if (*input_line_pointer == '{') |
3529 | input_line_pointer++; | |
b99bd4ef | 3530 | |
c19d1205 | 3531 | do |
b99bd4ef | 3532 | { |
dcbf9037 | 3533 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 3534 | |
c19d1205 | 3535 | if (reg == FAIL) |
b99bd4ef | 3536 | { |
9b7132d3 | 3537 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 | 3538 | goto error; |
b99bd4ef NC |
3539 | } |
3540 | ||
c19d1205 ZW |
3541 | if (mask >> reg) |
3542 | as_tsktsk (_("register list not in ascending order")); | |
3543 | mask |= 1 << reg; | |
b99bd4ef | 3544 | |
c19d1205 ZW |
3545 | if (*input_line_pointer == '-') |
3546 | { | |
3547 | input_line_pointer++; | |
dcbf9037 | 3548 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
c19d1205 ZW |
3549 | if (hi_reg == FAIL) |
3550 | { | |
9b7132d3 | 3551 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 ZW |
3552 | goto error; |
3553 | } | |
3554 | else if (reg >= hi_reg) | |
3555 | { | |
3556 | as_bad (_("bad register range")); | |
3557 | goto error; | |
3558 | } | |
3559 | for (; reg < hi_reg; reg++) | |
3560 | mask |= 1 << reg; | |
3561 | } | |
3562 | } | |
3563 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 3564 | |
c19d1205 ZW |
3565 | if (*input_line_pointer == '}') |
3566 | input_line_pointer++; | |
b99bd4ef | 3567 | |
c19d1205 | 3568 | demand_empty_rest_of_line (); |
b99bd4ef | 3569 | |
708587a4 | 3570 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
3571 | the list. */ |
3572 | flush_pending_unwind (); | |
b99bd4ef | 3573 | |
c19d1205 | 3574 | for (i = 0; i < 16; i++) |
b99bd4ef | 3575 | { |
c19d1205 ZW |
3576 | if (mask & (1 << i)) |
3577 | unwind.frame_size += 8; | |
b99bd4ef NC |
3578 | } |
3579 | ||
c19d1205 ZW |
3580 | /* Attempt to combine with a previous opcode. We do this because gcc |
3581 | likes to output separate unwind directives for a single block of | |
3582 | registers. */ | |
3583 | if (unwind.opcode_count > 0) | |
b99bd4ef | 3584 | { |
c19d1205 ZW |
3585 | i = unwind.opcodes[unwind.opcode_count - 1]; |
3586 | if ((i & 0xf8) == 0xc0) | |
3587 | { | |
3588 | i &= 7; | |
3589 | /* Only merge if the blocks are contiguous. */ | |
3590 | if (i < 6) | |
3591 | { | |
3592 | if ((mask & 0xfe00) == (1 << 9)) | |
3593 | { | |
3594 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
3595 | unwind.opcode_count--; | |
3596 | } | |
3597 | } | |
3598 | else if (i == 6 && unwind.opcode_count >= 2) | |
3599 | { | |
3600 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
3601 | reg = i >> 4; | |
3602 | i &= 0xf; | |
b99bd4ef | 3603 | |
c19d1205 ZW |
3604 | op = 0xffff << (reg - 1); |
3605 | if (reg > 0 | |
87a1fd79 | 3606 | && ((mask & op) == (1u << (reg - 1)))) |
c19d1205 ZW |
3607 | { |
3608 | op = (1 << (reg + i + 1)) - 1; | |
3609 | op &= ~((1 << reg) - 1); | |
3610 | mask |= op; | |
3611 | unwind.opcode_count -= 2; | |
3612 | } | |
3613 | } | |
3614 | } | |
b99bd4ef NC |
3615 | } |
3616 | ||
c19d1205 ZW |
3617 | hi_reg = 15; |
3618 | /* We want to generate opcodes in the order the registers have been | |
3619 | saved, ie. descending order. */ | |
3620 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 3621 | { |
c19d1205 ZW |
3622 | /* Save registers in blocks. */ |
3623 | if (reg < 0 | |
3624 | || !(mask & (1 << reg))) | |
3625 | { | |
3626 | /* We found an unsaved reg. Generate opcodes to save the | |
5f4273c7 | 3627 | preceding block. */ |
c19d1205 ZW |
3628 | if (reg != hi_reg) |
3629 | { | |
3630 | if (reg == 9) | |
3631 | { | |
3632 | /* Short form. */ | |
3633 | op = 0xc0 | (hi_reg - 10); | |
3634 | add_unwind_opcode (op, 1); | |
3635 | } | |
3636 | else | |
3637 | { | |
3638 | /* Long form. */ | |
3639 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
3640 | add_unwind_opcode (op, 2); | |
3641 | } | |
3642 | } | |
3643 | hi_reg = reg - 1; | |
3644 | } | |
b99bd4ef NC |
3645 | } |
3646 | ||
c19d1205 ZW |
3647 | return; |
3648 | error: | |
3649 | ignore_rest_of_line (); | |
b99bd4ef NC |
3650 | } |
3651 | ||
3652 | static void | |
c19d1205 | 3653 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 3654 | { |
c19d1205 ZW |
3655 | int reg; |
3656 | int hi_reg; | |
3657 | unsigned mask = 0; | |
3658 | valueT op; | |
b99bd4ef | 3659 | |
c19d1205 ZW |
3660 | if (*input_line_pointer == '{') |
3661 | input_line_pointer++; | |
b99bd4ef | 3662 | |
c19d1205 | 3663 | do |
b99bd4ef | 3664 | { |
dcbf9037 | 3665 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 3666 | |
c19d1205 ZW |
3667 | if (reg == FAIL) |
3668 | { | |
9b7132d3 | 3669 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
3670 | goto error; |
3671 | } | |
b99bd4ef | 3672 | |
c19d1205 ZW |
3673 | reg -= 8; |
3674 | if (mask >> reg) | |
3675 | as_tsktsk (_("register list not in ascending order")); | |
3676 | mask |= 1 << reg; | |
b99bd4ef | 3677 | |
c19d1205 ZW |
3678 | if (*input_line_pointer == '-') |
3679 | { | |
3680 | input_line_pointer++; | |
dcbf9037 | 3681 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
c19d1205 ZW |
3682 | if (hi_reg == FAIL) |
3683 | { | |
9b7132d3 | 3684 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
3685 | goto error; |
3686 | } | |
3687 | else if (reg >= hi_reg) | |
3688 | { | |
3689 | as_bad (_("bad register range")); | |
3690 | goto error; | |
3691 | } | |
3692 | for (; reg < hi_reg; reg++) | |
3693 | mask |= 1 << reg; | |
3694 | } | |
b99bd4ef | 3695 | } |
c19d1205 | 3696 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 3697 | |
c19d1205 ZW |
3698 | if (*input_line_pointer == '}') |
3699 | input_line_pointer++; | |
b99bd4ef | 3700 | |
c19d1205 ZW |
3701 | demand_empty_rest_of_line (); |
3702 | ||
708587a4 | 3703 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
3704 | the list. */ |
3705 | flush_pending_unwind (); | |
b99bd4ef | 3706 | |
c19d1205 | 3707 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 3708 | { |
c19d1205 ZW |
3709 | if (mask & (1 << reg)) |
3710 | unwind.frame_size += 4; | |
b99bd4ef | 3711 | } |
c19d1205 ZW |
3712 | op = 0xc700 | mask; |
3713 | add_unwind_opcode (op, 2); | |
3714 | return; | |
3715 | error: | |
3716 | ignore_rest_of_line (); | |
b99bd4ef NC |
3717 | } |
3718 | ||
c19d1205 | 3719 | |
fa073d69 MS |
3720 | /* Parse an unwind_save directive. |
3721 | If the argument is non-zero, this is a .vsave directive. */ | |
c19d1205 | 3722 | |
b99bd4ef | 3723 | static void |
fa073d69 | 3724 | s_arm_unwind_save (int arch_v6) |
b99bd4ef | 3725 | { |
c19d1205 ZW |
3726 | char *peek; |
3727 | struct reg_entry *reg; | |
3728 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 3729 | |
c19d1205 ZW |
3730 | /* Figure out what sort of save we have. */ |
3731 | peek = input_line_pointer; | |
b99bd4ef | 3732 | |
c19d1205 | 3733 | if (*peek == '{') |
b99bd4ef | 3734 | { |
c19d1205 ZW |
3735 | had_brace = TRUE; |
3736 | peek++; | |
b99bd4ef NC |
3737 | } |
3738 | ||
c19d1205 | 3739 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 3740 | |
c19d1205 | 3741 | if (!reg) |
b99bd4ef | 3742 | { |
c19d1205 ZW |
3743 | as_bad (_("register expected")); |
3744 | ignore_rest_of_line (); | |
b99bd4ef NC |
3745 | return; |
3746 | } | |
3747 | ||
c19d1205 | 3748 | switch (reg->type) |
b99bd4ef | 3749 | { |
c19d1205 ZW |
3750 | case REG_TYPE_FN: |
3751 | if (had_brace) | |
3752 | { | |
3753 | as_bad (_("FPA .unwind_save does not take a register list")); | |
3754 | ignore_rest_of_line (); | |
3755 | return; | |
3756 | } | |
93ac2687 | 3757 | input_line_pointer = peek; |
c19d1205 | 3758 | s_arm_unwind_save_fpa (reg->number); |
b99bd4ef | 3759 | return; |
c19d1205 ZW |
3760 | |
3761 | case REG_TYPE_RN: s_arm_unwind_save_core (); return; | |
fa073d69 MS |
3762 | case REG_TYPE_VFD: |
3763 | if (arch_v6) | |
3764 | s_arm_unwind_save_vfp_armv6 (); | |
3765 | else | |
3766 | s_arm_unwind_save_vfp (); | |
3767 | return; | |
c19d1205 ZW |
3768 | case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; |
3769 | case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; | |
3770 | ||
3771 | default: | |
3772 | as_bad (_(".unwind_save does not support this kind of register")); | |
3773 | ignore_rest_of_line (); | |
b99bd4ef | 3774 | } |
c19d1205 | 3775 | } |
b99bd4ef | 3776 | |
b99bd4ef | 3777 | |
c19d1205 ZW |
3778 | /* Parse an unwind_movsp directive. */ |
3779 | ||
3780 | static void | |
3781 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
3782 | { | |
3783 | int reg; | |
3784 | valueT op; | |
4fa3602b | 3785 | int offset; |
c19d1205 | 3786 | |
dcbf9037 | 3787 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 | 3788 | if (reg == FAIL) |
b99bd4ef | 3789 | { |
9b7132d3 | 3790 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 | 3791 | ignore_rest_of_line (); |
b99bd4ef NC |
3792 | return; |
3793 | } | |
4fa3602b PB |
3794 | |
3795 | /* Optional constant. */ | |
3796 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
3797 | { | |
3798 | if (immediate_for_directive (&offset) == FAIL) | |
3799 | return; | |
3800 | } | |
3801 | else | |
3802 | offset = 0; | |
3803 | ||
c19d1205 | 3804 | demand_empty_rest_of_line (); |
b99bd4ef | 3805 | |
c19d1205 | 3806 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 3807 | { |
c19d1205 | 3808 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
3809 | return; |
3810 | } | |
3811 | ||
c19d1205 ZW |
3812 | if (unwind.fp_reg != REG_SP) |
3813 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 3814 | |
c19d1205 ZW |
3815 | /* Generate opcode to restore the value. */ |
3816 | op = 0x90 | reg; | |
3817 | add_unwind_opcode (op, 1); | |
3818 | ||
3819 | /* Record the information for later. */ | |
3820 | unwind.fp_reg = reg; | |
4fa3602b | 3821 | unwind.fp_offset = unwind.frame_size - offset; |
c19d1205 | 3822 | unwind.sp_restored = 1; |
b05fe5cf ZW |
3823 | } |
3824 | ||
c19d1205 ZW |
3825 | /* Parse an unwind_pad directive. */ |
3826 | ||
b05fe5cf | 3827 | static void |
c19d1205 | 3828 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 3829 | { |
c19d1205 | 3830 | int offset; |
b05fe5cf | 3831 | |
c19d1205 ZW |
3832 | if (immediate_for_directive (&offset) == FAIL) |
3833 | return; | |
b99bd4ef | 3834 | |
c19d1205 ZW |
3835 | if (offset & 3) |
3836 | { | |
3837 | as_bad (_("stack increment must be multiple of 4")); | |
3838 | ignore_rest_of_line (); | |
3839 | return; | |
3840 | } | |
b99bd4ef | 3841 | |
c19d1205 ZW |
3842 | /* Don't generate any opcodes, just record the details for later. */ |
3843 | unwind.frame_size += offset; | |
3844 | unwind.pending_offset += offset; | |
3845 | ||
3846 | demand_empty_rest_of_line (); | |
3847 | } | |
3848 | ||
3849 | /* Parse an unwind_setfp directive. */ | |
3850 | ||
3851 | static void | |
3852 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 3853 | { |
c19d1205 ZW |
3854 | int sp_reg; |
3855 | int fp_reg; | |
3856 | int offset; | |
3857 | ||
dcbf9037 | 3858 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 ZW |
3859 | if (skip_past_comma (&input_line_pointer) == FAIL) |
3860 | sp_reg = FAIL; | |
3861 | else | |
dcbf9037 | 3862 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
b99bd4ef | 3863 | |
c19d1205 ZW |
3864 | if (fp_reg == FAIL || sp_reg == FAIL) |
3865 | { | |
3866 | as_bad (_("expected <reg>, <reg>")); | |
3867 | ignore_rest_of_line (); | |
3868 | return; | |
3869 | } | |
b99bd4ef | 3870 | |
c19d1205 ZW |
3871 | /* Optional constant. */ |
3872 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
3873 | { | |
3874 | if (immediate_for_directive (&offset) == FAIL) | |
3875 | return; | |
3876 | } | |
3877 | else | |
3878 | offset = 0; | |
a737bd4d | 3879 | |
c19d1205 | 3880 | demand_empty_rest_of_line (); |
a737bd4d | 3881 | |
fdfde340 | 3882 | if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) |
a737bd4d | 3883 | { |
c19d1205 ZW |
3884 | as_bad (_("register must be either sp or set by a previous" |
3885 | "unwind_movsp directive")); | |
3886 | return; | |
a737bd4d NC |
3887 | } |
3888 | ||
c19d1205 ZW |
3889 | /* Don't generate any opcodes, just record the information for later. */ |
3890 | unwind.fp_reg = fp_reg; | |
3891 | unwind.fp_used = 1; | |
fdfde340 | 3892 | if (sp_reg == REG_SP) |
c19d1205 ZW |
3893 | unwind.fp_offset = unwind.frame_size - offset; |
3894 | else | |
3895 | unwind.fp_offset -= offset; | |
a737bd4d NC |
3896 | } |
3897 | ||
c19d1205 ZW |
3898 | /* Parse an unwind_raw directive. */ |
3899 | ||
3900 | static void | |
3901 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 3902 | { |
c19d1205 | 3903 | expressionS exp; |
708587a4 | 3904 | /* This is an arbitrary limit. */ |
c19d1205 ZW |
3905 | unsigned char op[16]; |
3906 | int count; | |
a737bd4d | 3907 | |
c19d1205 ZW |
3908 | expression (&exp); |
3909 | if (exp.X_op == O_constant | |
3910 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 3911 | { |
c19d1205 ZW |
3912 | unwind.frame_size += exp.X_add_number; |
3913 | expression (&exp); | |
3914 | } | |
3915 | else | |
3916 | exp.X_op = O_illegal; | |
a737bd4d | 3917 | |
c19d1205 ZW |
3918 | if (exp.X_op != O_constant) |
3919 | { | |
3920 | as_bad (_("expected <offset>, <opcode>")); | |
3921 | ignore_rest_of_line (); | |
3922 | return; | |
3923 | } | |
a737bd4d | 3924 | |
c19d1205 | 3925 | count = 0; |
a737bd4d | 3926 | |
c19d1205 ZW |
3927 | /* Parse the opcode. */ |
3928 | for (;;) | |
3929 | { | |
3930 | if (count >= 16) | |
3931 | { | |
3932 | as_bad (_("unwind opcode too long")); | |
3933 | ignore_rest_of_line (); | |
a737bd4d | 3934 | } |
c19d1205 | 3935 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 3936 | { |
c19d1205 ZW |
3937 | as_bad (_("invalid unwind opcode")); |
3938 | ignore_rest_of_line (); | |
3939 | return; | |
a737bd4d | 3940 | } |
c19d1205 | 3941 | op[count++] = exp.X_add_number; |
a737bd4d | 3942 | |
c19d1205 ZW |
3943 | /* Parse the next byte. */ |
3944 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
3945 | break; | |
a737bd4d | 3946 | |
c19d1205 ZW |
3947 | expression (&exp); |
3948 | } | |
b99bd4ef | 3949 | |
c19d1205 ZW |
3950 | /* Add the opcode bytes in reverse order. */ |
3951 | while (count--) | |
3952 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 3953 | |
c19d1205 | 3954 | demand_empty_rest_of_line (); |
b99bd4ef | 3955 | } |
ee065d83 PB |
3956 | |
3957 | ||
3958 | /* Parse a .eabi_attribute directive. */ | |
3959 | ||
3960 | static void | |
3961 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) | |
3962 | { | |
ee3c0378 AS |
3963 | int tag = s_vendor_attribute (OBJ_ATTR_PROC); |
3964 | ||
3965 | if (tag < NUM_KNOWN_OBJ_ATTRIBUTES) | |
3966 | attributes_set_explicitly[tag] = 1; | |
ee065d83 | 3967 | } |
8463be01 | 3968 | #endif /* OBJ_ELF */ |
ee065d83 PB |
3969 | |
3970 | static void s_arm_arch (int); | |
7a1d4c38 | 3971 | static void s_arm_object_arch (int); |
ee065d83 PB |
3972 | static void s_arm_cpu (int); |
3973 | static void s_arm_fpu (int); | |
b99bd4ef | 3974 | |
f0927246 NC |
3975 | #ifdef TE_PE |
3976 | ||
3977 | static void | |
5f4273c7 | 3978 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
f0927246 NC |
3979 | { |
3980 | expressionS exp; | |
3981 | ||
3982 | do | |
3983 | { | |
3984 | expression (&exp); | |
3985 | if (exp.X_op == O_symbol) | |
3986 | exp.X_op = O_secrel; | |
3987 | ||
3988 | emit_expr (&exp, 4); | |
3989 | } | |
3990 | while (*input_line_pointer++ == ','); | |
3991 | ||
3992 | input_line_pointer--; | |
3993 | demand_empty_rest_of_line (); | |
3994 | } | |
3995 | #endif /* TE_PE */ | |
3996 | ||
c19d1205 ZW |
3997 | /* This table describes all the machine specific pseudo-ops the assembler |
3998 | has to support. The fields are: | |
3999 | pseudo-op name without dot | |
4000 | function to call to execute this pseudo-op | |
4001 | Integer arg to pass to the function. */ | |
b99bd4ef | 4002 | |
c19d1205 | 4003 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 4004 | { |
c19d1205 ZW |
4005 | /* Never called because '.req' does not start a line. */ |
4006 | { "req", s_req, 0 }, | |
dcbf9037 JB |
4007 | /* Following two are likewise never called. */ |
4008 | { "dn", s_dn, 0 }, | |
4009 | { "qn", s_qn, 0 }, | |
c19d1205 ZW |
4010 | { "unreq", s_unreq, 0 }, |
4011 | { "bss", s_bss, 0 }, | |
4012 | { "align", s_align, 0 }, | |
4013 | { "arm", s_arm, 0 }, | |
4014 | { "thumb", s_thumb, 0 }, | |
4015 | { "code", s_code, 0 }, | |
4016 | { "force_thumb", s_force_thumb, 0 }, | |
4017 | { "thumb_func", s_thumb_func, 0 }, | |
4018 | { "thumb_set", s_thumb_set, 0 }, | |
4019 | { "even", s_even, 0 }, | |
4020 | { "ltorg", s_ltorg, 0 }, | |
4021 | { "pool", s_ltorg, 0 }, | |
4022 | { "syntax", s_syntax, 0 }, | |
8463be01 PB |
4023 | { "cpu", s_arm_cpu, 0 }, |
4024 | { "arch", s_arm_arch, 0 }, | |
7a1d4c38 | 4025 | { "object_arch", s_arm_object_arch, 0 }, |
8463be01 | 4026 | { "fpu", s_arm_fpu, 0 }, |
c19d1205 ZW |
4027 | #ifdef OBJ_ELF |
4028 | { "word", s_arm_elf_cons, 4 }, | |
4029 | { "long", s_arm_elf_cons, 4 }, | |
4030 | { "rel31", s_arm_rel31, 0 }, | |
4031 | { "fnstart", s_arm_unwind_fnstart, 0 }, | |
4032 | { "fnend", s_arm_unwind_fnend, 0 }, | |
4033 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
4034 | { "personality", s_arm_unwind_personality, 0 }, | |
4035 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
4036 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
4037 | { "save", s_arm_unwind_save, 0 }, | |
fa073d69 | 4038 | { "vsave", s_arm_unwind_save, 1 }, |
c19d1205 ZW |
4039 | { "movsp", s_arm_unwind_movsp, 0 }, |
4040 | { "pad", s_arm_unwind_pad, 0 }, | |
4041 | { "setfp", s_arm_unwind_setfp, 0 }, | |
4042 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
ee065d83 | 4043 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, |
c19d1205 ZW |
4044 | #else |
4045 | { "word", cons, 4}, | |
f0927246 NC |
4046 | |
4047 | /* These are used for dwarf. */ | |
4048 | {"2byte", cons, 2}, | |
4049 | {"4byte", cons, 4}, | |
4050 | {"8byte", cons, 8}, | |
4051 | /* These are used for dwarf2. */ | |
4052 | { "file", (void (*) (int)) dwarf2_directive_file, 0 }, | |
4053 | { "loc", dwarf2_directive_loc, 0 }, | |
4054 | { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, | |
c19d1205 ZW |
4055 | #endif |
4056 | { "extend", float_cons, 'x' }, | |
4057 | { "ldouble", float_cons, 'x' }, | |
4058 | { "packed", float_cons, 'p' }, | |
f0927246 NC |
4059 | #ifdef TE_PE |
4060 | {"secrel32", pe_directive_secrel, 0}, | |
4061 | #endif | |
c19d1205 ZW |
4062 | { 0, 0, 0 } |
4063 | }; | |
4064 | \f | |
4065 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 4066 | |
c19d1205 ZW |
4067 | /* Generic immediate-value read function for use in insn parsing. |
4068 | STR points to the beginning of the immediate (the leading #); | |
4069 | VAL receives the value; if the value is outside [MIN, MAX] | |
4070 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
4071 | optional. */ | |
b99bd4ef | 4072 | |
c19d1205 ZW |
4073 | static int |
4074 | parse_immediate (char **str, int *val, int min, int max, | |
4075 | bfd_boolean prefix_opt) | |
4076 | { | |
4077 | expressionS exp; | |
4078 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); | |
4079 | if (exp.X_op != O_constant) | |
b99bd4ef | 4080 | { |
c19d1205 ZW |
4081 | inst.error = _("constant expression required"); |
4082 | return FAIL; | |
4083 | } | |
b99bd4ef | 4084 | |
c19d1205 ZW |
4085 | if (exp.X_add_number < min || exp.X_add_number > max) |
4086 | { | |
4087 | inst.error = _("immediate value out of range"); | |
4088 | return FAIL; | |
4089 | } | |
b99bd4ef | 4090 | |
c19d1205 ZW |
4091 | *val = exp.X_add_number; |
4092 | return SUCCESS; | |
4093 | } | |
b99bd4ef | 4094 | |
5287ad62 | 4095 | /* Less-generic immediate-value read function with the possibility of loading a |
036dc3f7 | 4096 | big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate |
5287ad62 JB |
4097 | instructions. Puts the result directly in inst.operands[i]. */ |
4098 | ||
4099 | static int | |
4100 | parse_big_immediate (char **str, int i) | |
4101 | { | |
4102 | expressionS exp; | |
4103 | char *ptr = *str; | |
4104 | ||
4105 | my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); | |
4106 | ||
4107 | if (exp.X_op == O_constant) | |
036dc3f7 PB |
4108 | { |
4109 | inst.operands[i].imm = exp.X_add_number & 0xffffffff; | |
4110 | /* If we're on a 64-bit host, then a 64-bit number can be returned using | |
4111 | O_constant. We have to be careful not to break compilation for | |
4112 | 32-bit X_add_number, though. */ | |
4113 | if ((exp.X_add_number & ~0xffffffffl) != 0) | |
4114 | { | |
4115 | /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */ | |
4116 | inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff; | |
4117 | inst.operands[i].regisimm = 1; | |
4118 | } | |
4119 | } | |
5287ad62 JB |
4120 | else if (exp.X_op == O_big |
4121 | && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32 | |
4122 | && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64) | |
4123 | { | |
4124 | unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; | |
4125 | /* Bignums have their least significant bits in | |
4126 | generic_bignum[0]. Make sure we put 32 bits in imm and | |
4127 | 32 bits in reg, in a (hopefully) portable way. */ | |
4128 | assert (parts != 0); | |
4129 | inst.operands[i].imm = 0; | |
4130 | for (j = 0; j < parts; j++, idx++) | |
4131 | inst.operands[i].imm |= generic_bignum[idx] | |
4132 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
4133 | inst.operands[i].reg = 0; | |
4134 | for (j = 0; j < parts; j++, idx++) | |
4135 | inst.operands[i].reg |= generic_bignum[idx] | |
4136 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
4137 | inst.operands[i].regisimm = 1; | |
4138 | } | |
4139 | else | |
4140 | return FAIL; | |
5f4273c7 | 4141 | |
5287ad62 JB |
4142 | *str = ptr; |
4143 | ||
4144 | return SUCCESS; | |
4145 | } | |
4146 | ||
c19d1205 ZW |
4147 | /* Returns the pseudo-register number of an FPA immediate constant, |
4148 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 4149 | |
c19d1205 ZW |
4150 | static int |
4151 | parse_fpa_immediate (char ** str) | |
4152 | { | |
4153 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4154 | char * save_in; | |
4155 | expressionS exp; | |
4156 | int i; | |
4157 | int j; | |
b99bd4ef | 4158 | |
c19d1205 ZW |
4159 | /* First try and match exact strings, this is to guarantee |
4160 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 4161 | |
c19d1205 ZW |
4162 | for (i = 0; fp_const[i]; i++) |
4163 | { | |
4164 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 4165 | { |
c19d1205 | 4166 | char *start = *str; |
b99bd4ef | 4167 | |
c19d1205 ZW |
4168 | *str += strlen (fp_const[i]); |
4169 | if (is_end_of_line[(unsigned char) **str]) | |
4170 | return i + 8; | |
4171 | *str = start; | |
4172 | } | |
4173 | } | |
b99bd4ef | 4174 | |
c19d1205 ZW |
4175 | /* Just because we didn't get a match doesn't mean that the constant |
4176 | isn't valid, just that it is in a format that we don't | |
4177 | automatically recognize. Try parsing it with the standard | |
4178 | expression routines. */ | |
b99bd4ef | 4179 | |
c19d1205 | 4180 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 4181 | |
c19d1205 ZW |
4182 | /* Look for a raw floating point number. */ |
4183 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
4184 | && is_end_of_line[(unsigned char) *save_in]) | |
4185 | { | |
4186 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4187 | { | |
4188 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 4189 | { |
c19d1205 ZW |
4190 | if (words[j] != fp_values[i][j]) |
4191 | break; | |
b99bd4ef NC |
4192 | } |
4193 | ||
c19d1205 | 4194 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 4195 | { |
c19d1205 ZW |
4196 | *str = save_in; |
4197 | return i + 8; | |
b99bd4ef NC |
4198 | } |
4199 | } | |
4200 | } | |
b99bd4ef | 4201 | |
c19d1205 ZW |
4202 | /* Try and parse a more complex expression, this will probably fail |
4203 | unless the code uses a floating point prefix (eg "0f"). */ | |
4204 | save_in = input_line_pointer; | |
4205 | input_line_pointer = *str; | |
4206 | if (expression (&exp) == absolute_section | |
4207 | && exp.X_op == O_big | |
4208 | && exp.X_add_number < 0) | |
4209 | { | |
4210 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
4211 | Ditto for 15. */ | |
4212 | if (gen_to_words (words, 5, (long) 15) == 0) | |
4213 | { | |
4214 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4215 | { | |
4216 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
4217 | { | |
4218 | if (words[j] != fp_values[i][j]) | |
4219 | break; | |
4220 | } | |
b99bd4ef | 4221 | |
c19d1205 ZW |
4222 | if (j == MAX_LITTLENUMS) |
4223 | { | |
4224 | *str = input_line_pointer; | |
4225 | input_line_pointer = save_in; | |
4226 | return i + 8; | |
4227 | } | |
4228 | } | |
4229 | } | |
b99bd4ef NC |
4230 | } |
4231 | ||
c19d1205 ZW |
4232 | *str = input_line_pointer; |
4233 | input_line_pointer = save_in; | |
4234 | inst.error = _("invalid FPA immediate expression"); | |
4235 | return FAIL; | |
b99bd4ef NC |
4236 | } |
4237 | ||
136da414 JB |
4238 | /* Returns 1 if a number has "quarter-precision" float format |
4239 | 0baBbbbbbc defgh000 00000000 00000000. */ | |
4240 | ||
4241 | static int | |
4242 | is_quarter_float (unsigned imm) | |
4243 | { | |
4244 | int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; | |
4245 | return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; | |
4246 | } | |
4247 | ||
4248 | /* Parse an 8-bit "quarter-precision" floating point number of the form: | |
4249 | 0baBbbbbbc defgh000 00000000 00000000. | |
c96612cc JB |
4250 | The zero and minus-zero cases need special handling, since they can't be |
4251 | encoded in the "quarter-precision" float format, but can nonetheless be | |
4252 | loaded as integer constants. */ | |
136da414 JB |
4253 | |
4254 | static unsigned | |
4255 | parse_qfloat_immediate (char **ccp, int *immed) | |
4256 | { | |
4257 | char *str = *ccp; | |
c96612cc | 4258 | char *fpnum; |
136da414 | 4259 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
c96612cc | 4260 | int found_fpchar = 0; |
5f4273c7 | 4261 | |
136da414 | 4262 | skip_past_char (&str, '#'); |
5f4273c7 | 4263 | |
c96612cc JB |
4264 | /* We must not accidentally parse an integer as a floating-point number. Make |
4265 | sure that the value we parse is not an integer by checking for special | |
4266 | characters '.' or 'e'. | |
4267 | FIXME: This is a horrible hack, but doing better is tricky because type | |
4268 | information isn't in a very usable state at parse time. */ | |
4269 | fpnum = str; | |
4270 | skip_whitespace (fpnum); | |
4271 | ||
4272 | if (strncmp (fpnum, "0x", 2) == 0) | |
4273 | return FAIL; | |
4274 | else | |
4275 | { | |
4276 | for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) | |
4277 | if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') | |
4278 | { | |
4279 | found_fpchar = 1; | |
4280 | break; | |
4281 | } | |
4282 | ||
4283 | if (!found_fpchar) | |
4284 | return FAIL; | |
4285 | } | |
5f4273c7 | 4286 | |
136da414 JB |
4287 | if ((str = atof_ieee (str, 's', words)) != NULL) |
4288 | { | |
4289 | unsigned fpword = 0; | |
4290 | int i; | |
5f4273c7 | 4291 | |
136da414 JB |
4292 | /* Our FP word must be 32 bits (single-precision FP). */ |
4293 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) | |
4294 | { | |
4295 | fpword <<= LITTLENUM_NUMBER_OF_BITS; | |
4296 | fpword |= words[i]; | |
4297 | } | |
5f4273c7 | 4298 | |
c96612cc | 4299 | if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) |
136da414 JB |
4300 | *immed = fpword; |
4301 | else | |
4302 | return FAIL; | |
4303 | ||
4304 | *ccp = str; | |
5f4273c7 | 4305 | |
136da414 JB |
4306 | return SUCCESS; |
4307 | } | |
5f4273c7 | 4308 | |
136da414 JB |
4309 | return FAIL; |
4310 | } | |
4311 | ||
c19d1205 ZW |
4312 | /* Shift operands. */ |
4313 | enum shift_kind | |
b99bd4ef | 4314 | { |
c19d1205 ZW |
4315 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX |
4316 | }; | |
b99bd4ef | 4317 | |
c19d1205 ZW |
4318 | struct asm_shift_name |
4319 | { | |
4320 | const char *name; | |
4321 | enum shift_kind kind; | |
4322 | }; | |
b99bd4ef | 4323 | |
c19d1205 ZW |
4324 | /* Third argument to parse_shift. */ |
4325 | enum parse_shift_mode | |
4326 | { | |
4327 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
4328 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
4329 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
4330 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
4331 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
4332 | }; | |
b99bd4ef | 4333 | |
c19d1205 ZW |
4334 | /* Parse a <shift> specifier on an ARM data processing instruction. |
4335 | This has three forms: | |
b99bd4ef | 4336 | |
c19d1205 ZW |
4337 | (LSL|LSR|ASL|ASR|ROR) Rs |
4338 | (LSL|LSR|ASL|ASR|ROR) #imm | |
4339 | RRX | |
b99bd4ef | 4340 | |
c19d1205 ZW |
4341 | Note that ASL is assimilated to LSL in the instruction encoding, and |
4342 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 4343 | |
c19d1205 ZW |
4344 | static int |
4345 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 4346 | { |
c19d1205 ZW |
4347 | const struct asm_shift_name *shift_name; |
4348 | enum shift_kind shift; | |
4349 | char *s = *str; | |
4350 | char *p = s; | |
4351 | int reg; | |
b99bd4ef | 4352 | |
c19d1205 ZW |
4353 | for (p = *str; ISALPHA (*p); p++) |
4354 | ; | |
b99bd4ef | 4355 | |
c19d1205 | 4356 | if (p == *str) |
b99bd4ef | 4357 | { |
c19d1205 ZW |
4358 | inst.error = _("shift expression expected"); |
4359 | return FAIL; | |
b99bd4ef NC |
4360 | } |
4361 | ||
c19d1205 ZW |
4362 | shift_name = hash_find_n (arm_shift_hsh, *str, p - *str); |
4363 | ||
4364 | if (shift_name == NULL) | |
b99bd4ef | 4365 | { |
c19d1205 ZW |
4366 | inst.error = _("shift expression expected"); |
4367 | return FAIL; | |
b99bd4ef NC |
4368 | } |
4369 | ||
c19d1205 | 4370 | shift = shift_name->kind; |
b99bd4ef | 4371 | |
c19d1205 ZW |
4372 | switch (mode) |
4373 | { | |
4374 | case NO_SHIFT_RESTRICT: | |
4375 | case SHIFT_IMMEDIATE: break; | |
b99bd4ef | 4376 | |
c19d1205 ZW |
4377 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
4378 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
4379 | { | |
4380 | inst.error = _("'LSL' or 'ASR' required"); | |
4381 | return FAIL; | |
4382 | } | |
4383 | break; | |
b99bd4ef | 4384 | |
c19d1205 ZW |
4385 | case SHIFT_LSL_IMMEDIATE: |
4386 | if (shift != SHIFT_LSL) | |
4387 | { | |
4388 | inst.error = _("'LSL' required"); | |
4389 | return FAIL; | |
4390 | } | |
4391 | break; | |
b99bd4ef | 4392 | |
c19d1205 ZW |
4393 | case SHIFT_ASR_IMMEDIATE: |
4394 | if (shift != SHIFT_ASR) | |
4395 | { | |
4396 | inst.error = _("'ASR' required"); | |
4397 | return FAIL; | |
4398 | } | |
4399 | break; | |
b99bd4ef | 4400 | |
c19d1205 ZW |
4401 | default: abort (); |
4402 | } | |
b99bd4ef | 4403 | |
c19d1205 ZW |
4404 | if (shift != SHIFT_RRX) |
4405 | { | |
4406 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
4407 | skip_whitespace (p); | |
b99bd4ef | 4408 | |
c19d1205 | 4409 | if (mode == NO_SHIFT_RESTRICT |
dcbf9037 | 4410 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4411 | { |
4412 | inst.operands[i].imm = reg; | |
4413 | inst.operands[i].immisreg = 1; | |
4414 | } | |
4415 | else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4416 | return FAIL; | |
4417 | } | |
4418 | inst.operands[i].shift_kind = shift; | |
4419 | inst.operands[i].shifted = 1; | |
4420 | *str = p; | |
4421 | return SUCCESS; | |
b99bd4ef NC |
4422 | } |
4423 | ||
c19d1205 | 4424 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 4425 | |
c19d1205 ZW |
4426 | #<immediate> |
4427 | #<immediate>, <rotate> | |
4428 | <Rm> | |
4429 | <Rm>, <shift> | |
b99bd4ef | 4430 | |
c19d1205 ZW |
4431 | where <shift> is defined by parse_shift above, and <rotate> is a |
4432 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 4433 | is deferred to md_apply_fix. */ |
b99bd4ef | 4434 | |
c19d1205 ZW |
4435 | static int |
4436 | parse_shifter_operand (char **str, int i) | |
4437 | { | |
4438 | int value; | |
4439 | expressionS expr; | |
b99bd4ef | 4440 | |
dcbf9037 | 4441 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4442 | { |
4443 | inst.operands[i].reg = value; | |
4444 | inst.operands[i].isreg = 1; | |
b99bd4ef | 4445 | |
c19d1205 ZW |
4446 | /* parse_shift will override this if appropriate */ |
4447 | inst.reloc.exp.X_op = O_constant; | |
4448 | inst.reloc.exp.X_add_number = 0; | |
b99bd4ef | 4449 | |
c19d1205 ZW |
4450 | if (skip_past_comma (str) == FAIL) |
4451 | return SUCCESS; | |
b99bd4ef | 4452 | |
c19d1205 ZW |
4453 | /* Shift operation on register. */ |
4454 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
4455 | } |
4456 | ||
c19d1205 ZW |
4457 | if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) |
4458 | return FAIL; | |
b99bd4ef | 4459 | |
c19d1205 | 4460 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 4461 | { |
c19d1205 ZW |
4462 | /* #x, y -- ie explicit rotation by Y. */ |
4463 | if (my_get_expression (&expr, str, GE_NO_PREFIX)) | |
4464 | return FAIL; | |
b99bd4ef | 4465 | |
c19d1205 ZW |
4466 | if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant) |
4467 | { | |
4468 | inst.error = _("constant expression expected"); | |
4469 | return FAIL; | |
4470 | } | |
b99bd4ef | 4471 | |
c19d1205 ZW |
4472 | value = expr.X_add_number; |
4473 | if (value < 0 || value > 30 || value % 2 != 0) | |
4474 | { | |
4475 | inst.error = _("invalid rotation"); | |
4476 | return FAIL; | |
4477 | } | |
4478 | if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) | |
4479 | { | |
4480 | inst.error = _("invalid constant"); | |
4481 | return FAIL; | |
4482 | } | |
09d92015 | 4483 | |
55cf6793 | 4484 | /* Convert to decoded value. md_apply_fix will put it back. */ |
c19d1205 ZW |
4485 | inst.reloc.exp.X_add_number |
4486 | = (((inst.reloc.exp.X_add_number << (32 - value)) | |
4487 | | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff); | |
09d92015 MM |
4488 | } |
4489 | ||
c19d1205 ZW |
4490 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; |
4491 | inst.reloc.pc_rel = 0; | |
4492 | return SUCCESS; | |
09d92015 MM |
4493 | } |
4494 | ||
4962c51a MS |
4495 | /* Group relocation information. Each entry in the table contains the |
4496 | textual name of the relocation as may appear in assembler source | |
4497 | and must end with a colon. | |
4498 | Along with this textual name are the relocation codes to be used if | |
4499 | the corresponding instruction is an ALU instruction (ADD or SUB only), | |
4500 | an LDR, an LDRS, or an LDC. */ | |
4501 | ||
4502 | struct group_reloc_table_entry | |
4503 | { | |
4504 | const char *name; | |
4505 | int alu_code; | |
4506 | int ldr_code; | |
4507 | int ldrs_code; | |
4508 | int ldc_code; | |
4509 | }; | |
4510 | ||
4511 | typedef enum | |
4512 | { | |
4513 | /* Varieties of non-ALU group relocation. */ | |
4514 | ||
4515 | GROUP_LDR, | |
4516 | GROUP_LDRS, | |
4517 | GROUP_LDC | |
4518 | } group_reloc_type; | |
4519 | ||
4520 | static struct group_reloc_table_entry group_reloc_table[] = | |
4521 | { /* Program counter relative: */ | |
4522 | { "pc_g0_nc", | |
4523 | BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ | |
4524 | 0, /* LDR */ | |
4525 | 0, /* LDRS */ | |
4526 | 0 }, /* LDC */ | |
4527 | { "pc_g0", | |
4528 | BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ | |
4529 | BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ | |
4530 | BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ | |
4531 | BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ | |
4532 | { "pc_g1_nc", | |
4533 | BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ | |
4534 | 0, /* LDR */ | |
4535 | 0, /* LDRS */ | |
4536 | 0 }, /* LDC */ | |
4537 | { "pc_g1", | |
4538 | BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ | |
4539 | BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ | |
4540 | BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ | |
4541 | BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ | |
4542 | { "pc_g2", | |
4543 | BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ | |
4544 | BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ | |
4545 | BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ | |
4546 | BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ | |
4547 | /* Section base relative */ | |
4548 | { "sb_g0_nc", | |
4549 | BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ | |
4550 | 0, /* LDR */ | |
4551 | 0, /* LDRS */ | |
4552 | 0 }, /* LDC */ | |
4553 | { "sb_g0", | |
4554 | BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ | |
4555 | BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ | |
4556 | BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ | |
4557 | BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ | |
4558 | { "sb_g1_nc", | |
4559 | BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ | |
4560 | 0, /* LDR */ | |
4561 | 0, /* LDRS */ | |
4562 | 0 }, /* LDC */ | |
4563 | { "sb_g1", | |
4564 | BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ | |
4565 | BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ | |
4566 | BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ | |
4567 | BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ | |
4568 | { "sb_g2", | |
4569 | BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ | |
4570 | BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ | |
4571 | BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ | |
4572 | BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ | |
4573 | ||
4574 | /* Given the address of a pointer pointing to the textual name of a group | |
4575 | relocation as may appear in assembler source, attempt to find its details | |
4576 | in group_reloc_table. The pointer will be updated to the character after | |
4577 | the trailing colon. On failure, FAIL will be returned; SUCCESS | |
4578 | otherwise. On success, *entry will be updated to point at the relevant | |
4579 | group_reloc_table entry. */ | |
4580 | ||
4581 | static int | |
4582 | find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) | |
4583 | { | |
4584 | unsigned int i; | |
4585 | for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) | |
4586 | { | |
4587 | int length = strlen (group_reloc_table[i].name); | |
4588 | ||
5f4273c7 NC |
4589 | if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 |
4590 | && (*str)[length] == ':') | |
4962c51a MS |
4591 | { |
4592 | *out = &group_reloc_table[i]; | |
4593 | *str += (length + 1); | |
4594 | return SUCCESS; | |
4595 | } | |
4596 | } | |
4597 | ||
4598 | return FAIL; | |
4599 | } | |
4600 | ||
4601 | /* Parse a <shifter_operand> for an ARM data processing instruction | |
4602 | (as for parse_shifter_operand) where group relocations are allowed: | |
4603 | ||
4604 | #<immediate> | |
4605 | #<immediate>, <rotate> | |
4606 | #:<group_reloc>:<expression> | |
4607 | <Rm> | |
4608 | <Rm>, <shift> | |
4609 | ||
4610 | where <group_reloc> is one of the strings defined in group_reloc_table. | |
4611 | The hashes are optional. | |
4612 | ||
4613 | Everything else is as for parse_shifter_operand. */ | |
4614 | ||
4615 | static parse_operand_result | |
4616 | parse_shifter_operand_group_reloc (char **str, int i) | |
4617 | { | |
4618 | /* Determine if we have the sequence of characters #: or just : | |
4619 | coming next. If we do, then we check for a group relocation. | |
4620 | If we don't, punt the whole lot to parse_shifter_operand. */ | |
4621 | ||
4622 | if (((*str)[0] == '#' && (*str)[1] == ':') | |
4623 | || (*str)[0] == ':') | |
4624 | { | |
4625 | struct group_reloc_table_entry *entry; | |
4626 | ||
4627 | if ((*str)[0] == '#') | |
4628 | (*str) += 2; | |
4629 | else | |
4630 | (*str)++; | |
4631 | ||
4632 | /* Try to parse a group relocation. Anything else is an error. */ | |
4633 | if (find_group_reloc_table_entry (str, &entry) == FAIL) | |
4634 | { | |
4635 | inst.error = _("unknown group relocation"); | |
4636 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
4637 | } | |
4638 | ||
4639 | /* We now have the group relocation table entry corresponding to | |
4640 | the name in the assembler source. Next, we parse the expression. */ | |
4641 | if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) | |
4642 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
4643 | ||
4644 | /* Record the relocation type (always the ALU variant here). */ | |
4645 | inst.reloc.type = entry->alu_code; | |
4646 | assert (inst.reloc.type != 0); | |
4647 | ||
4648 | return PARSE_OPERAND_SUCCESS; | |
4649 | } | |
4650 | else | |
4651 | return parse_shifter_operand (str, i) == SUCCESS | |
4652 | ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; | |
4653 | ||
4654 | /* Never reached. */ | |
4655 | } | |
4656 | ||
c19d1205 ZW |
4657 | /* Parse all forms of an ARM address expression. Information is written |
4658 | to inst.operands[i] and/or inst.reloc. | |
09d92015 | 4659 | |
c19d1205 | 4660 | Preindexed addressing (.preind=1): |
09d92015 | 4661 | |
c19d1205 ZW |
4662 | [Rn, #offset] .reg=Rn .reloc.exp=offset |
4663 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
4664 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
4665 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 4666 | |
c19d1205 | 4667 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 4668 | |
c19d1205 | 4669 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 4670 | |
c19d1205 ZW |
4671 | [Rn], #offset .reg=Rn .reloc.exp=offset |
4672 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
4673 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
4674 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 4675 | |
c19d1205 | 4676 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 4677 | |
c19d1205 | 4678 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 4679 | |
c19d1205 | 4680 | Other: |
09d92015 | 4681 | |
c19d1205 ZW |
4682 | [Rn]{!} shorthand for [Rn,#0]{!} |
4683 | =immediate .isreg=0 .reloc.exp=immediate | |
4684 | label .reg=PC .reloc.pc_rel=1 .reloc.exp=label | |
09d92015 | 4685 | |
c19d1205 ZW |
4686 | It is the caller's responsibility to check for addressing modes not |
4687 | supported by the instruction, and to set inst.reloc.type. */ | |
4688 | ||
4962c51a MS |
4689 | static parse_operand_result |
4690 | parse_address_main (char **str, int i, int group_relocations, | |
4691 | group_reloc_type group_type) | |
09d92015 | 4692 | { |
c19d1205 ZW |
4693 | char *p = *str; |
4694 | int reg; | |
09d92015 | 4695 | |
c19d1205 | 4696 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 4697 | { |
c19d1205 ZW |
4698 | if (skip_past_char (&p, '=') == FAIL) |
4699 | { | |
4700 | /* bare address - translate to PC-relative offset */ | |
4701 | inst.reloc.pc_rel = 1; | |
4702 | inst.operands[i].reg = REG_PC; | |
4703 | inst.operands[i].isreg = 1; | |
4704 | inst.operands[i].preind = 1; | |
4705 | } | |
4706 | /* else a load-constant pseudo op, no special treatment needed here */ | |
09d92015 | 4707 | |
c19d1205 | 4708 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) |
4962c51a | 4709 | return PARSE_OPERAND_FAIL; |
09d92015 | 4710 | |
c19d1205 | 4711 | *str = p; |
4962c51a | 4712 | return PARSE_OPERAND_SUCCESS; |
09d92015 MM |
4713 | } |
4714 | ||
dcbf9037 | 4715 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
09d92015 | 4716 | { |
c19d1205 | 4717 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
4962c51a | 4718 | return PARSE_OPERAND_FAIL; |
09d92015 | 4719 | } |
c19d1205 ZW |
4720 | inst.operands[i].reg = reg; |
4721 | inst.operands[i].isreg = 1; | |
09d92015 | 4722 | |
c19d1205 | 4723 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 4724 | { |
c19d1205 | 4725 | inst.operands[i].preind = 1; |
09d92015 | 4726 | |
c19d1205 ZW |
4727 | if (*p == '+') p++; |
4728 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
4729 | ||
dcbf9037 | 4730 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
09d92015 | 4731 | { |
c19d1205 ZW |
4732 | inst.operands[i].imm = reg; |
4733 | inst.operands[i].immisreg = 1; | |
4734 | ||
4735 | if (skip_past_comma (&p) == SUCCESS) | |
4736 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 4737 | return PARSE_OPERAND_FAIL; |
c19d1205 | 4738 | } |
5287ad62 JB |
4739 | else if (skip_past_char (&p, ':') == SUCCESS) |
4740 | { | |
4741 | /* FIXME: '@' should be used here, but it's filtered out by generic | |
4742 | code before we get to see it here. This may be subject to | |
4743 | change. */ | |
4744 | expressionS exp; | |
4745 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
4746 | if (exp.X_op != O_constant) | |
4747 | { | |
4748 | inst.error = _("alignment must be constant"); | |
4962c51a | 4749 | return PARSE_OPERAND_FAIL; |
5287ad62 JB |
4750 | } |
4751 | inst.operands[i].imm = exp.X_add_number << 8; | |
4752 | inst.operands[i].immisalign = 1; | |
4753 | /* Alignments are not pre-indexes. */ | |
4754 | inst.operands[i].preind = 0; | |
4755 | } | |
c19d1205 ZW |
4756 | else |
4757 | { | |
4758 | if (inst.operands[i].negative) | |
4759 | { | |
4760 | inst.operands[i].negative = 0; | |
4761 | p--; | |
4762 | } | |
4962c51a | 4763 | |
5f4273c7 NC |
4764 | if (group_relocations |
4765 | && ((*p == '#' && *(p + 1) == ':') || *p == ':')) | |
4962c51a MS |
4766 | { |
4767 | struct group_reloc_table_entry *entry; | |
4768 | ||
4769 | /* Skip over the #: or : sequence. */ | |
4770 | if (*p == '#') | |
4771 | p += 2; | |
4772 | else | |
4773 | p++; | |
4774 | ||
4775 | /* Try to parse a group relocation. Anything else is an | |
4776 | error. */ | |
4777 | if (find_group_reloc_table_entry (&p, &entry) == FAIL) | |
4778 | { | |
4779 | inst.error = _("unknown group relocation"); | |
4780 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
4781 | } | |
4782 | ||
4783 | /* We now have the group relocation table entry corresponding to | |
4784 | the name in the assembler source. Next, we parse the | |
4785 | expression. */ | |
4786 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
4787 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
4788 | ||
4789 | /* Record the relocation type. */ | |
4790 | switch (group_type) | |
4791 | { | |
4792 | case GROUP_LDR: | |
4793 | inst.reloc.type = entry->ldr_code; | |
4794 | break; | |
4795 | ||
4796 | case GROUP_LDRS: | |
4797 | inst.reloc.type = entry->ldrs_code; | |
4798 | break; | |
4799 | ||
4800 | case GROUP_LDC: | |
4801 | inst.reloc.type = entry->ldc_code; | |
4802 | break; | |
4803 | ||
4804 | default: | |
4805 | assert (0); | |
4806 | } | |
4807 | ||
4808 | if (inst.reloc.type == 0) | |
4809 | { | |
4810 | inst.error = _("this group relocation is not allowed on this instruction"); | |
4811 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
4812 | } | |
4813 | } | |
4814 | else | |
4815 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4816 | return PARSE_OPERAND_FAIL; | |
09d92015 MM |
4817 | } |
4818 | } | |
4819 | ||
c19d1205 | 4820 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 4821 | { |
c19d1205 | 4822 | inst.error = _("']' expected"); |
4962c51a | 4823 | return PARSE_OPERAND_FAIL; |
09d92015 MM |
4824 | } |
4825 | ||
c19d1205 ZW |
4826 | if (skip_past_char (&p, '!') == SUCCESS) |
4827 | inst.operands[i].writeback = 1; | |
09d92015 | 4828 | |
c19d1205 | 4829 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 4830 | { |
c19d1205 ZW |
4831 | if (skip_past_char (&p, '{') == SUCCESS) |
4832 | { | |
4833 | /* [Rn], {expr} - unindexed, with option */ | |
4834 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 4835 | 0, 255, TRUE) == FAIL) |
4962c51a | 4836 | return PARSE_OPERAND_FAIL; |
09d92015 | 4837 | |
c19d1205 ZW |
4838 | if (skip_past_char (&p, '}') == FAIL) |
4839 | { | |
4840 | inst.error = _("'}' expected at end of 'option' field"); | |
4962c51a | 4841 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
4842 | } |
4843 | if (inst.operands[i].preind) | |
4844 | { | |
4845 | inst.error = _("cannot combine index with option"); | |
4962c51a | 4846 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
4847 | } |
4848 | *str = p; | |
4962c51a | 4849 | return PARSE_OPERAND_SUCCESS; |
09d92015 | 4850 | } |
c19d1205 ZW |
4851 | else |
4852 | { | |
4853 | inst.operands[i].postind = 1; | |
4854 | inst.operands[i].writeback = 1; | |
09d92015 | 4855 | |
c19d1205 ZW |
4856 | if (inst.operands[i].preind) |
4857 | { | |
4858 | inst.error = _("cannot combine pre- and post-indexing"); | |
4962c51a | 4859 | return PARSE_OPERAND_FAIL; |
c19d1205 | 4860 | } |
09d92015 | 4861 | |
c19d1205 ZW |
4862 | if (*p == '+') p++; |
4863 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 4864 | |
dcbf9037 | 4865 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 | 4866 | { |
5287ad62 JB |
4867 | /* We might be using the immediate for alignment already. If we |
4868 | are, OR the register number into the low-order bits. */ | |
4869 | if (inst.operands[i].immisalign) | |
4870 | inst.operands[i].imm |= reg; | |
4871 | else | |
4872 | inst.operands[i].imm = reg; | |
c19d1205 | 4873 | inst.operands[i].immisreg = 1; |
a737bd4d | 4874 | |
c19d1205 ZW |
4875 | if (skip_past_comma (&p) == SUCCESS) |
4876 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 4877 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
4878 | } |
4879 | else | |
4880 | { | |
4881 | if (inst.operands[i].negative) | |
4882 | { | |
4883 | inst.operands[i].negative = 0; | |
4884 | p--; | |
4885 | } | |
4886 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4962c51a | 4887 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
4888 | } |
4889 | } | |
a737bd4d NC |
4890 | } |
4891 | ||
c19d1205 ZW |
4892 | /* If at this point neither .preind nor .postind is set, we have a |
4893 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
4894 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
4895 | { | |
4896 | inst.operands[i].preind = 1; | |
4897 | inst.reloc.exp.X_op = O_constant; | |
4898 | inst.reloc.exp.X_add_number = 0; | |
4899 | } | |
4900 | *str = p; | |
4962c51a MS |
4901 | return PARSE_OPERAND_SUCCESS; |
4902 | } | |
4903 | ||
4904 | static int | |
4905 | parse_address (char **str, int i) | |
4906 | { | |
4907 | return parse_address_main (str, i, 0, 0) == PARSE_OPERAND_SUCCESS | |
4908 | ? SUCCESS : FAIL; | |
4909 | } | |
4910 | ||
4911 | static parse_operand_result | |
4912 | parse_address_group_reloc (char **str, int i, group_reloc_type type) | |
4913 | { | |
4914 | return parse_address_main (str, i, 1, type); | |
a737bd4d NC |
4915 | } |
4916 | ||
b6895b4f PB |
4917 | /* Parse an operand for a MOVW or MOVT instruction. */ |
4918 | static int | |
4919 | parse_half (char **str) | |
4920 | { | |
4921 | char * p; | |
5f4273c7 | 4922 | |
b6895b4f PB |
4923 | p = *str; |
4924 | skip_past_char (&p, '#'); | |
5f4273c7 | 4925 | if (strncasecmp (p, ":lower16:", 9) == 0) |
b6895b4f PB |
4926 | inst.reloc.type = BFD_RELOC_ARM_MOVW; |
4927 | else if (strncasecmp (p, ":upper16:", 9) == 0) | |
4928 | inst.reloc.type = BFD_RELOC_ARM_MOVT; | |
4929 | ||
4930 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
4931 | { | |
4932 | p += 9; | |
5f4273c7 | 4933 | skip_whitespace (p); |
b6895b4f PB |
4934 | } |
4935 | ||
4936 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
4937 | return FAIL; | |
4938 | ||
4939 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
4940 | { | |
4941 | if (inst.reloc.exp.X_op != O_constant) | |
4942 | { | |
4943 | inst.error = _("constant expression expected"); | |
4944 | return FAIL; | |
4945 | } | |
4946 | if (inst.reloc.exp.X_add_number < 0 | |
4947 | || inst.reloc.exp.X_add_number > 0xffff) | |
4948 | { | |
4949 | inst.error = _("immediate value out of range"); | |
4950 | return FAIL; | |
4951 | } | |
4952 | } | |
4953 | *str = p; | |
4954 | return SUCCESS; | |
4955 | } | |
4956 | ||
c19d1205 | 4957 | /* Miscellaneous. */ |
a737bd4d | 4958 | |
c19d1205 ZW |
4959 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
4960 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
4961 | static int | |
4962 | parse_psr (char **str) | |
09d92015 | 4963 | { |
c19d1205 ZW |
4964 | char *p; |
4965 | unsigned long psr_field; | |
62b3e311 PB |
4966 | const struct asm_psr *psr; |
4967 | char *start; | |
09d92015 | 4968 | |
c19d1205 ZW |
4969 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
4970 | feature for ease of use and backwards compatibility. */ | |
4971 | p = *str; | |
62b3e311 | 4972 | if (strncasecmp (p, "SPSR", 4) == 0) |
c19d1205 | 4973 | psr_field = SPSR_BIT; |
62b3e311 | 4974 | else if (strncasecmp (p, "CPSR", 4) == 0) |
c19d1205 ZW |
4975 | psr_field = 0; |
4976 | else | |
62b3e311 PB |
4977 | { |
4978 | start = p; | |
4979 | do | |
4980 | p++; | |
4981 | while (ISALNUM (*p) || *p == '_'); | |
4982 | ||
4983 | psr = hash_find_n (arm_v7m_psr_hsh, start, p - start); | |
4984 | if (!psr) | |
4985 | return FAIL; | |
09d92015 | 4986 | |
62b3e311 PB |
4987 | *str = p; |
4988 | return psr->field; | |
4989 | } | |
09d92015 | 4990 | |
62b3e311 | 4991 | p += 4; |
c19d1205 ZW |
4992 | if (*p == '_') |
4993 | { | |
4994 | /* A suffix follows. */ | |
c19d1205 ZW |
4995 | p++; |
4996 | start = p; | |
a737bd4d | 4997 | |
c19d1205 ZW |
4998 | do |
4999 | p++; | |
5000 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 5001 | |
c19d1205 ZW |
5002 | psr = hash_find_n (arm_psr_hsh, start, p - start); |
5003 | if (!psr) | |
5004 | goto error; | |
a737bd4d | 5005 | |
c19d1205 | 5006 | psr_field |= psr->field; |
a737bd4d | 5007 | } |
c19d1205 | 5008 | else |
a737bd4d | 5009 | { |
c19d1205 ZW |
5010 | if (ISALNUM (*p)) |
5011 | goto error; /* Garbage after "[CS]PSR". */ | |
5012 | ||
5013 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 5014 | } |
c19d1205 ZW |
5015 | *str = p; |
5016 | return psr_field; | |
a737bd4d | 5017 | |
c19d1205 ZW |
5018 | error: |
5019 | inst.error = _("flag for {c}psr instruction expected"); | |
5020 | return FAIL; | |
a737bd4d NC |
5021 | } |
5022 | ||
c19d1205 ZW |
5023 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
5024 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 5025 | |
c19d1205 ZW |
5026 | static int |
5027 | parse_cps_flags (char **str) | |
a737bd4d | 5028 | { |
c19d1205 ZW |
5029 | int val = 0; |
5030 | int saw_a_flag = 0; | |
5031 | char *s = *str; | |
a737bd4d | 5032 | |
c19d1205 ZW |
5033 | for (;;) |
5034 | switch (*s++) | |
5035 | { | |
5036 | case '\0': case ',': | |
5037 | goto done; | |
a737bd4d | 5038 | |
c19d1205 ZW |
5039 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
5040 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
5041 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 5042 | |
c19d1205 ZW |
5043 | default: |
5044 | inst.error = _("unrecognized CPS flag"); | |
5045 | return FAIL; | |
5046 | } | |
a737bd4d | 5047 | |
c19d1205 ZW |
5048 | done: |
5049 | if (saw_a_flag == 0) | |
a737bd4d | 5050 | { |
c19d1205 ZW |
5051 | inst.error = _("missing CPS flags"); |
5052 | return FAIL; | |
a737bd4d | 5053 | } |
a737bd4d | 5054 | |
c19d1205 ZW |
5055 | *str = s - 1; |
5056 | return val; | |
a737bd4d NC |
5057 | } |
5058 | ||
c19d1205 ZW |
5059 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
5060 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
5061 | |
5062 | static int | |
c19d1205 | 5063 | parse_endian_specifier (char **str) |
a737bd4d | 5064 | { |
c19d1205 ZW |
5065 | int little_endian; |
5066 | char *s = *str; | |
a737bd4d | 5067 | |
c19d1205 ZW |
5068 | if (strncasecmp (s, "BE", 2)) |
5069 | little_endian = 0; | |
5070 | else if (strncasecmp (s, "LE", 2)) | |
5071 | little_endian = 1; | |
5072 | else | |
a737bd4d | 5073 | { |
c19d1205 | 5074 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5075 | return FAIL; |
5076 | } | |
5077 | ||
c19d1205 | 5078 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 5079 | { |
c19d1205 | 5080 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5081 | return FAIL; |
5082 | } | |
5083 | ||
c19d1205 ZW |
5084 | *str = s + 2; |
5085 | return little_endian; | |
5086 | } | |
a737bd4d | 5087 | |
c19d1205 ZW |
5088 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
5089 | value suitable for poking into the rotate field of an sxt or sxta | |
5090 | instruction, or FAIL on error. */ | |
5091 | ||
5092 | static int | |
5093 | parse_ror (char **str) | |
5094 | { | |
5095 | int rot; | |
5096 | char *s = *str; | |
5097 | ||
5098 | if (strncasecmp (s, "ROR", 3) == 0) | |
5099 | s += 3; | |
5100 | else | |
a737bd4d | 5101 | { |
c19d1205 | 5102 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
5103 | return FAIL; |
5104 | } | |
c19d1205 ZW |
5105 | |
5106 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
5107 | return FAIL; | |
5108 | ||
5109 | switch (rot) | |
a737bd4d | 5110 | { |
c19d1205 ZW |
5111 | case 0: *str = s; return 0x0; |
5112 | case 8: *str = s; return 0x1; | |
5113 | case 16: *str = s; return 0x2; | |
5114 | case 24: *str = s; return 0x3; | |
5115 | ||
5116 | default: | |
5117 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
5118 | return FAIL; |
5119 | } | |
c19d1205 | 5120 | } |
a737bd4d | 5121 | |
c19d1205 ZW |
5122 | /* Parse a conditional code (from conds[] below). The value returned is in the |
5123 | range 0 .. 14, or FAIL. */ | |
5124 | static int | |
5125 | parse_cond (char **str) | |
5126 | { | |
c462b453 | 5127 | char *q; |
c19d1205 | 5128 | const struct asm_cond *c; |
c462b453 PB |
5129 | int n; |
5130 | /* Condition codes are always 2 characters, so matching up to | |
5131 | 3 characters is sufficient. */ | |
5132 | char cond[3]; | |
a737bd4d | 5133 | |
c462b453 PB |
5134 | q = *str; |
5135 | n = 0; | |
5136 | while (ISALPHA (*q) && n < 3) | |
5137 | { | |
e07e6e58 | 5138 | cond[n] = TOLOWER (*q); |
c462b453 PB |
5139 | q++; |
5140 | n++; | |
5141 | } | |
a737bd4d | 5142 | |
c462b453 | 5143 | c = hash_find_n (arm_cond_hsh, cond, n); |
c19d1205 | 5144 | if (!c) |
a737bd4d | 5145 | { |
c19d1205 | 5146 | inst.error = _("condition required"); |
a737bd4d NC |
5147 | return FAIL; |
5148 | } | |
5149 | ||
c19d1205 ZW |
5150 | *str = q; |
5151 | return c->value; | |
5152 | } | |
5153 | ||
62b3e311 PB |
5154 | /* Parse an option for a barrier instruction. Returns the encoding for the |
5155 | option, or FAIL. */ | |
5156 | static int | |
5157 | parse_barrier (char **str) | |
5158 | { | |
5159 | char *p, *q; | |
5160 | const struct asm_barrier_opt *o; | |
5161 | ||
5162 | p = q = *str; | |
5163 | while (ISALPHA (*q)) | |
5164 | q++; | |
5165 | ||
5166 | o = hash_find_n (arm_barrier_opt_hsh, p, q - p); | |
5167 | if (!o) | |
5168 | return FAIL; | |
5169 | ||
5170 | *str = q; | |
5171 | return o->value; | |
5172 | } | |
5173 | ||
92e90b6e PB |
5174 | /* Parse the operands of a table branch instruction. Similar to a memory |
5175 | operand. */ | |
5176 | static int | |
5177 | parse_tb (char **str) | |
5178 | { | |
5179 | char * p = *str; | |
5180 | int reg; | |
5181 | ||
5182 | if (skip_past_char (&p, '[') == FAIL) | |
ab1eb5fe PB |
5183 | { |
5184 | inst.error = _("'[' expected"); | |
5185 | return FAIL; | |
5186 | } | |
92e90b6e | 5187 | |
dcbf9037 | 5188 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5189 | { |
5190 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5191 | return FAIL; | |
5192 | } | |
5193 | inst.operands[0].reg = reg; | |
5194 | ||
5195 | if (skip_past_comma (&p) == FAIL) | |
ab1eb5fe PB |
5196 | { |
5197 | inst.error = _("',' expected"); | |
5198 | return FAIL; | |
5199 | } | |
5f4273c7 | 5200 | |
dcbf9037 | 5201 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5202 | { |
5203 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5204 | return FAIL; | |
5205 | } | |
5206 | inst.operands[0].imm = reg; | |
5207 | ||
5208 | if (skip_past_comma (&p) == SUCCESS) | |
5209 | { | |
5210 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
5211 | return FAIL; | |
5212 | if (inst.reloc.exp.X_add_number != 1) | |
5213 | { | |
5214 | inst.error = _("invalid shift"); | |
5215 | return FAIL; | |
5216 | } | |
5217 | inst.operands[0].shifted = 1; | |
5218 | } | |
5219 | ||
5220 | if (skip_past_char (&p, ']') == FAIL) | |
5221 | { | |
5222 | inst.error = _("']' expected"); | |
5223 | return FAIL; | |
5224 | } | |
5225 | *str = p; | |
5226 | return SUCCESS; | |
5227 | } | |
5228 | ||
5287ad62 JB |
5229 | /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more |
5230 | information on the types the operands can take and how they are encoded. | |
037e8744 JB |
5231 | Up to four operands may be read; this function handles setting the |
5232 | ".present" field for each read operand itself. | |
5287ad62 JB |
5233 | Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, |
5234 | else returns FAIL. */ | |
5235 | ||
5236 | static int | |
5237 | parse_neon_mov (char **str, int *which_operand) | |
5238 | { | |
5239 | int i = *which_operand, val; | |
5240 | enum arm_reg_type rtype; | |
5241 | char *ptr = *str; | |
dcbf9037 | 5242 | struct neon_type_el optype; |
5f4273c7 | 5243 | |
dcbf9037 | 5244 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
5245 | { |
5246 | /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ | |
5247 | inst.operands[i].reg = val; | |
5248 | inst.operands[i].isscalar = 1; | |
dcbf9037 | 5249 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5250 | inst.operands[i++].present = 1; |
5251 | ||
5252 | if (skip_past_comma (&ptr) == FAIL) | |
5253 | goto wanted_comma; | |
5f4273c7 | 5254 | |
dcbf9037 | 5255 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
5287ad62 | 5256 | goto wanted_arm; |
5f4273c7 | 5257 | |
5287ad62 JB |
5258 | inst.operands[i].reg = val; |
5259 | inst.operands[i].isreg = 1; | |
5260 | inst.operands[i].present = 1; | |
5261 | } | |
037e8744 | 5262 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) |
dcbf9037 | 5263 | != FAIL) |
5287ad62 JB |
5264 | { |
5265 | /* Cases 0, 1, 2, 3, 5 (D only). */ | |
5266 | if (skip_past_comma (&ptr) == FAIL) | |
5267 | goto wanted_comma; | |
5f4273c7 | 5268 | |
5287ad62 JB |
5269 | inst.operands[i].reg = val; |
5270 | inst.operands[i].isreg = 1; | |
5271 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5272 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5273 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5274 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5275 | inst.operands[i++].present = 1; |
5276 | ||
dcbf9037 | 5277 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 | 5278 | { |
037e8744 JB |
5279 | /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. |
5280 | Case 13: VMOV <Sd>, <Rm> */ | |
5287ad62 JB |
5281 | inst.operands[i].reg = val; |
5282 | inst.operands[i].isreg = 1; | |
037e8744 | 5283 | inst.operands[i].present = 1; |
5287ad62 JB |
5284 | |
5285 | if (rtype == REG_TYPE_NQ) | |
5286 | { | |
dcbf9037 | 5287 | first_error (_("can't use Neon quad register here")); |
5287ad62 JB |
5288 | return FAIL; |
5289 | } | |
037e8744 JB |
5290 | else if (rtype != REG_TYPE_VFS) |
5291 | { | |
5292 | i++; | |
5293 | if (skip_past_comma (&ptr) == FAIL) | |
5294 | goto wanted_comma; | |
5295 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5296 | goto wanted_arm; | |
5297 | inst.operands[i].reg = val; | |
5298 | inst.operands[i].isreg = 1; | |
5299 | inst.operands[i].present = 1; | |
5300 | } | |
5287ad62 | 5301 | } |
037e8744 JB |
5302 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, |
5303 | &optype)) != FAIL) | |
5287ad62 JB |
5304 | { |
5305 | /* Case 0: VMOV<c><q> <Qd>, <Qm> | |
037e8744 JB |
5306 | Case 1: VMOV<c><q> <Dd>, <Dm> |
5307 | Case 8: VMOV.F32 <Sd>, <Sm> | |
5308 | Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ | |
5287ad62 JB |
5309 | |
5310 | inst.operands[i].reg = val; | |
5311 | inst.operands[i].isreg = 1; | |
5312 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5313 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5314 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5315 | inst.operands[i].vectype = optype; |
5287ad62 | 5316 | inst.operands[i].present = 1; |
5f4273c7 | 5317 | |
037e8744 JB |
5318 | if (skip_past_comma (&ptr) == SUCCESS) |
5319 | { | |
5320 | /* Case 15. */ | |
5321 | i++; | |
5322 | ||
5323 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5324 | goto wanted_arm; | |
5325 | ||
5326 | inst.operands[i].reg = val; | |
5327 | inst.operands[i].isreg = 1; | |
5328 | inst.operands[i++].present = 1; | |
5f4273c7 | 5329 | |
037e8744 JB |
5330 | if (skip_past_comma (&ptr) == FAIL) |
5331 | goto wanted_comma; | |
5f4273c7 | 5332 | |
037e8744 JB |
5333 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
5334 | goto wanted_arm; | |
5f4273c7 | 5335 | |
037e8744 JB |
5336 | inst.operands[i].reg = val; |
5337 | inst.operands[i].isreg = 1; | |
5338 | inst.operands[i++].present = 1; | |
5339 | } | |
5287ad62 | 5340 | } |
4641781c PB |
5341 | else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) |
5342 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> | |
5343 | Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> | |
5344 | Case 10: VMOV.F32 <Sd>, #<imm> | |
5345 | Case 11: VMOV.F64 <Dd>, #<imm> */ | |
5346 | inst.operands[i].immisfloat = 1; | |
5347 | else if (parse_big_immediate (&ptr, i) == SUCCESS) | |
5348 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> | |
5349 | Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ | |
5350 | ; | |
5287ad62 JB |
5351 | else |
5352 | { | |
dcbf9037 | 5353 | first_error (_("expected <Rm> or <Dm> or <Qm> operand")); |
5287ad62 JB |
5354 | return FAIL; |
5355 | } | |
5356 | } | |
dcbf9037 | 5357 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
5358 | { |
5359 | /* Cases 6, 7. */ | |
5360 | inst.operands[i].reg = val; | |
5361 | inst.operands[i].isreg = 1; | |
5362 | inst.operands[i++].present = 1; | |
5f4273c7 | 5363 | |
5287ad62 JB |
5364 | if (skip_past_comma (&ptr) == FAIL) |
5365 | goto wanted_comma; | |
5f4273c7 | 5366 | |
dcbf9037 | 5367 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
5368 | { |
5369 | /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ | |
5370 | inst.operands[i].reg = val; | |
5371 | inst.operands[i].isscalar = 1; | |
5372 | inst.operands[i].present = 1; | |
dcbf9037 | 5373 | inst.operands[i].vectype = optype; |
5287ad62 | 5374 | } |
dcbf9037 | 5375 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
5376 | { |
5377 | /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ | |
5378 | inst.operands[i].reg = val; | |
5379 | inst.operands[i].isreg = 1; | |
5380 | inst.operands[i++].present = 1; | |
5f4273c7 | 5381 | |
5287ad62 JB |
5382 | if (skip_past_comma (&ptr) == FAIL) |
5383 | goto wanted_comma; | |
5f4273c7 | 5384 | |
037e8744 | 5385 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) |
dcbf9037 | 5386 | == FAIL) |
5287ad62 | 5387 | { |
037e8744 | 5388 | first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); |
5287ad62 JB |
5389 | return FAIL; |
5390 | } | |
5391 | ||
5392 | inst.operands[i].reg = val; | |
5393 | inst.operands[i].isreg = 1; | |
037e8744 JB |
5394 | inst.operands[i].isvec = 1; |
5395 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
dcbf9037 | 5396 | inst.operands[i].vectype = optype; |
5287ad62 | 5397 | inst.operands[i].present = 1; |
5f4273c7 | 5398 | |
037e8744 JB |
5399 | if (rtype == REG_TYPE_VFS) |
5400 | { | |
5401 | /* Case 14. */ | |
5402 | i++; | |
5403 | if (skip_past_comma (&ptr) == FAIL) | |
5404 | goto wanted_comma; | |
5405 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, | |
5406 | &optype)) == FAIL) | |
5407 | { | |
5408 | first_error (_(reg_expected_msgs[REG_TYPE_VFS])); | |
5409 | return FAIL; | |
5410 | } | |
5411 | inst.operands[i].reg = val; | |
5412 | inst.operands[i].isreg = 1; | |
5413 | inst.operands[i].isvec = 1; | |
5414 | inst.operands[i].issingle = 1; | |
5415 | inst.operands[i].vectype = optype; | |
5416 | inst.operands[i].present = 1; | |
5417 | } | |
5418 | } | |
5419 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) | |
5420 | != FAIL) | |
5421 | { | |
5422 | /* Case 13. */ | |
5423 | inst.operands[i].reg = val; | |
5424 | inst.operands[i].isreg = 1; | |
5425 | inst.operands[i].isvec = 1; | |
5426 | inst.operands[i].issingle = 1; | |
5427 | inst.operands[i].vectype = optype; | |
5428 | inst.operands[i++].present = 1; | |
5287ad62 JB |
5429 | } |
5430 | } | |
5431 | else | |
5432 | { | |
dcbf9037 | 5433 | first_error (_("parse error")); |
5287ad62 JB |
5434 | return FAIL; |
5435 | } | |
5436 | ||
5437 | /* Successfully parsed the operands. Update args. */ | |
5438 | *which_operand = i; | |
5439 | *str = ptr; | |
5440 | return SUCCESS; | |
5441 | ||
5f4273c7 | 5442 | wanted_comma: |
dcbf9037 | 5443 | first_error (_("expected comma")); |
5287ad62 | 5444 | return FAIL; |
5f4273c7 NC |
5445 | |
5446 | wanted_arm: | |
dcbf9037 | 5447 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
5287ad62 | 5448 | return FAIL; |
5287ad62 JB |
5449 | } |
5450 | ||
c19d1205 ZW |
5451 | /* Matcher codes for parse_operands. */ |
5452 | enum operand_parse_code | |
5453 | { | |
5454 | OP_stop, /* end of line */ | |
5455 | ||
5456 | OP_RR, /* ARM register */ | |
5457 | OP_RRnpc, /* ARM register, not r15 */ | |
5458 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ | |
5459 | OP_RRw, /* ARM register, not r15, optional trailing ! */ | |
5460 | OP_RCP, /* Coprocessor number */ | |
5461 | OP_RCN, /* Coprocessor register */ | |
5462 | OP_RF, /* FPA register */ | |
5463 | OP_RVS, /* VFP single precision register */ | |
5287ad62 JB |
5464 | OP_RVD, /* VFP double precision register (0..15) */ |
5465 | OP_RND, /* Neon double precision register (0..31) */ | |
5466 | OP_RNQ, /* Neon quad precision register */ | |
037e8744 | 5467 | OP_RVSD, /* VFP single or double precision register */ |
5287ad62 | 5468 | OP_RNDQ, /* Neon double or quad precision register */ |
037e8744 | 5469 | OP_RNSDQ, /* Neon single, double or quad precision register */ |
5287ad62 | 5470 | OP_RNSC, /* Neon scalar D[X] */ |
c19d1205 ZW |
5471 | OP_RVC, /* VFP control register */ |
5472 | OP_RMF, /* Maverick F register */ | |
5473 | OP_RMD, /* Maverick D register */ | |
5474 | OP_RMFX, /* Maverick FX register */ | |
5475 | OP_RMDX, /* Maverick DX register */ | |
5476 | OP_RMAX, /* Maverick AX register */ | |
5477 | OP_RMDS, /* Maverick DSPSC register */ | |
5478 | OP_RIWR, /* iWMMXt wR register */ | |
5479 | OP_RIWC, /* iWMMXt wC register */ | |
5480 | OP_RIWG, /* iWMMXt wCG register */ | |
5481 | OP_RXA, /* XScale accumulator register */ | |
5482 | ||
5483 | OP_REGLST, /* ARM register list */ | |
5484 | OP_VRSLST, /* VFP single-precision register list */ | |
5485 | OP_VRDLST, /* VFP double-precision register list */ | |
037e8744 | 5486 | OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ |
5287ad62 JB |
5487 | OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ |
5488 | OP_NSTRLST, /* Neon element/structure list */ | |
5489 | ||
5490 | OP_NILO, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */ | |
5491 | OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ | |
037e8744 | 5492 | OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ |
5287ad62 | 5493 | OP_RR_RNSC, /* ARM reg or Neon scalar. */ |
037e8744 | 5494 | OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ |
5287ad62 JB |
5495 | OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ |
5496 | OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ | |
5497 | OP_VMOV, /* Neon VMOV operands. */ | |
5498 | OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN. */ | |
5499 | OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ | |
2d447fca | 5500 | OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ |
5287ad62 JB |
5501 | |
5502 | OP_I0, /* immediate zero */ | |
c19d1205 ZW |
5503 | OP_I7, /* immediate value 0 .. 7 */ |
5504 | OP_I15, /* 0 .. 15 */ | |
5505 | OP_I16, /* 1 .. 16 */ | |
5287ad62 | 5506 | OP_I16z, /* 0 .. 16 */ |
c19d1205 ZW |
5507 | OP_I31, /* 0 .. 31 */ |
5508 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
5509 | OP_I32, /* 1 .. 32 */ | |
5287ad62 JB |
5510 | OP_I32z, /* 0 .. 32 */ |
5511 | OP_I63, /* 0 .. 63 */ | |
c19d1205 | 5512 | OP_I63s, /* -64 .. 63 */ |
5287ad62 JB |
5513 | OP_I64, /* 1 .. 64 */ |
5514 | OP_I64z, /* 0 .. 64 */ | |
c19d1205 | 5515 | OP_I255, /* 0 .. 255 */ |
c19d1205 ZW |
5516 | |
5517 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
5518 | OP_I7b, /* 0 .. 7 */ | |
5519 | OP_I15b, /* 0 .. 15 */ | |
5520 | OP_I31b, /* 0 .. 31 */ | |
5521 | ||
5522 | OP_SH, /* shifter operand */ | |
4962c51a | 5523 | OP_SHG, /* shifter operand with possible group relocation */ |
c19d1205 | 5524 | OP_ADDR, /* Memory address expression (any mode) */ |
4962c51a MS |
5525 | OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ |
5526 | OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ | |
5527 | OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ | |
c19d1205 ZW |
5528 | OP_EXP, /* arbitrary expression */ |
5529 | OP_EXPi, /* same, with optional immediate prefix */ | |
5530 | OP_EXPr, /* same, with optional relocation suffix */ | |
b6895b4f | 5531 | OP_HALF, /* 0 .. 65535 or low/high reloc. */ |
c19d1205 ZW |
5532 | |
5533 | OP_CPSF, /* CPS flags */ | |
5534 | OP_ENDI, /* Endianness specifier */ | |
5535 | OP_PSR, /* CPSR/SPSR mask for msr */ | |
5536 | OP_COND, /* conditional code */ | |
92e90b6e | 5537 | OP_TB, /* Table branch. */ |
c19d1205 | 5538 | |
037e8744 JB |
5539 | OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */ |
5540 | OP_APSR_RR, /* ARM register or "APSR_nzcv". */ | |
5541 | ||
c19d1205 ZW |
5542 | OP_RRnpc_I0, /* ARM register or literal 0 */ |
5543 | OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ | |
5544 | OP_RR_EXi, /* ARM register or expression with imm prefix */ | |
5545 | OP_RF_IF, /* FPA register or immediate */ | |
5546 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
41adaa5c | 5547 | OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ |
c19d1205 ZW |
5548 | |
5549 | /* Optional operands. */ | |
5550 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
5551 | OP_oI31b, /* 0 .. 31 */ | |
5287ad62 | 5552 | OP_oI32b, /* 1 .. 32 */ |
c19d1205 ZW |
5553 | OP_oIffffb, /* 0 .. 65535 */ |
5554 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
5555 | ||
5556 | OP_oRR, /* ARM register */ | |
5557 | OP_oRRnpc, /* ARM register, not the PC */ | |
b6702015 | 5558 | OP_oRRw, /* ARM register, not r15, optional trailing ! */ |
5287ad62 JB |
5559 | OP_oRND, /* Optional Neon double precision register */ |
5560 | OP_oRNQ, /* Optional Neon quad precision register */ | |
5561 | OP_oRNDQ, /* Optional Neon double or quad precision register */ | |
037e8744 | 5562 | OP_oRNSDQ, /* Optional single, double or quad precision vector register */ |
c19d1205 ZW |
5563 | OP_oSHll, /* LSL immediate */ |
5564 | OP_oSHar, /* ASR immediate */ | |
5565 | OP_oSHllar, /* LSL or ASR immediate */ | |
5566 | OP_oROR, /* ROR 0/8/16/24 */ | |
62b3e311 | 5567 | OP_oBARRIER, /* Option argument for a barrier instruction. */ |
c19d1205 ZW |
5568 | |
5569 | OP_FIRST_OPTIONAL = OP_oI7b | |
5570 | }; | |
a737bd4d | 5571 | |
c19d1205 ZW |
5572 | /* Generic instruction operand parser. This does no encoding and no |
5573 | semantic validation; it merely squirrels values away in the inst | |
5574 | structure. Returns SUCCESS or FAIL depending on whether the | |
5575 | specified grammar matched. */ | |
5576 | static int | |
ca3f61f7 | 5577 | parse_operands (char *str, const unsigned char *pattern) |
c19d1205 ZW |
5578 | { |
5579 | unsigned const char *upat = pattern; | |
5580 | char *backtrack_pos = 0; | |
5581 | const char *backtrack_error = 0; | |
5582 | int i, val, backtrack_index = 0; | |
5287ad62 | 5583 | enum arm_reg_type rtype; |
4962c51a | 5584 | parse_operand_result result; |
c19d1205 | 5585 | |
e07e6e58 NC |
5586 | #define po_char_or_fail(chr) \ |
5587 | do \ | |
5588 | { \ | |
5589 | if (skip_past_char (&str, chr) == FAIL) \ | |
5590 | goto bad_args; \ | |
5591 | } \ | |
5592 | while (0) | |
c19d1205 | 5593 | |
e07e6e58 NC |
5594 | #define po_reg_or_fail(regtype) \ |
5595 | do \ | |
dcbf9037 | 5596 | { \ |
e07e6e58 NC |
5597 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ |
5598 | & inst.operands[i].vectype); \ | |
5599 | if (val == FAIL) \ | |
5600 | { \ | |
5601 | first_error (_(reg_expected_msgs[regtype])); \ | |
5602 | goto failure; \ | |
5603 | } \ | |
5604 | inst.operands[i].reg = val; \ | |
5605 | inst.operands[i].isreg = 1; \ | |
5606 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
5607 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
5608 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
5609 | || rtype == REG_TYPE_VFD \ | |
5610 | || rtype == REG_TYPE_NQ); \ | |
dcbf9037 | 5611 | } \ |
e07e6e58 NC |
5612 | while (0) |
5613 | ||
5614 | #define po_reg_or_goto(regtype, label) \ | |
5615 | do \ | |
5616 | { \ | |
5617 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ | |
5618 | & inst.operands[i].vectype); \ | |
5619 | if (val == FAIL) \ | |
5620 | goto label; \ | |
dcbf9037 | 5621 | \ |
e07e6e58 NC |
5622 | inst.operands[i].reg = val; \ |
5623 | inst.operands[i].isreg = 1; \ | |
5624 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
5625 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
5626 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
5627 | || rtype == REG_TYPE_VFD \ | |
5628 | || rtype == REG_TYPE_NQ); \ | |
5629 | } \ | |
5630 | while (0) | |
5631 | ||
5632 | #define po_imm_or_fail(min, max, popt) \ | |
5633 | do \ | |
5634 | { \ | |
5635 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
5636 | goto failure; \ | |
5637 | inst.operands[i].imm = val; \ | |
5638 | } \ | |
5639 | while (0) | |
5640 | ||
5641 | #define po_scalar_or_goto(elsz, label) \ | |
5642 | do \ | |
5643 | { \ | |
5644 | val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \ | |
5645 | if (val == FAIL) \ | |
5646 | goto label; \ | |
5647 | inst.operands[i].reg = val; \ | |
5648 | inst.operands[i].isscalar = 1; \ | |
5649 | } \ | |
5650 | while (0) | |
5651 | ||
5652 | #define po_misc_or_fail(expr) \ | |
5653 | do \ | |
5654 | { \ | |
5655 | if (expr) \ | |
5656 | goto failure; \ | |
5657 | } \ | |
5658 | while (0) | |
5659 | ||
5660 | #define po_misc_or_fail_no_backtrack(expr) \ | |
5661 | do \ | |
5662 | { \ | |
5663 | result = expr; \ | |
5664 | if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \ | |
5665 | backtrack_pos = 0; \ | |
5666 | if (result != PARSE_OPERAND_SUCCESS) \ | |
5667 | goto failure; \ | |
5668 | } \ | |
5669 | while (0) | |
4962c51a | 5670 | |
c19d1205 ZW |
5671 | skip_whitespace (str); |
5672 | ||
5673 | for (i = 0; upat[i] != OP_stop; i++) | |
5674 | { | |
5675 | if (upat[i] >= OP_FIRST_OPTIONAL) | |
5676 | { | |
5677 | /* Remember where we are in case we need to backtrack. */ | |
5678 | assert (!backtrack_pos); | |
5679 | backtrack_pos = str; | |
5680 | backtrack_error = inst.error; | |
5681 | backtrack_index = i; | |
5682 | } | |
5683 | ||
b6702015 | 5684 | if (i > 0 && (i > 1 || inst.operands[0].present)) |
c19d1205 ZW |
5685 | po_char_or_fail (','); |
5686 | ||
5687 | switch (upat[i]) | |
5688 | { | |
5689 | /* Registers */ | |
5690 | case OP_oRRnpc: | |
5691 | case OP_RRnpc: | |
5692 | case OP_oRR: | |
5693 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; | |
5694 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
5695 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
5696 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
5697 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
5698 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
5287ad62 JB |
5699 | case OP_oRND: |
5700 | case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; | |
cd2cf30b PB |
5701 | case OP_RVC: |
5702 | po_reg_or_goto (REG_TYPE_VFC, coproc_reg); | |
5703 | break; | |
5704 | /* Also accept generic coprocessor regs for unknown registers. */ | |
5705 | coproc_reg: | |
5706 | po_reg_or_fail (REG_TYPE_CN); | |
5707 | break; | |
c19d1205 ZW |
5708 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; |
5709 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
5710 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
5711 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
5712 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
5713 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
5714 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
5715 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
5716 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
5717 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
5287ad62 JB |
5718 | case OP_oRNQ: |
5719 | case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; | |
5720 | case OP_oRNDQ: | |
5721 | case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; | |
037e8744 JB |
5722 | case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; |
5723 | case OP_oRNSDQ: | |
5724 | case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; | |
5287ad62 JB |
5725 | |
5726 | /* Neon scalar. Using an element size of 8 means that some invalid | |
5727 | scalars are accepted here, so deal with those in later code. */ | |
5728 | case OP_RNSC: po_scalar_or_goto (8, failure); break; | |
5729 | ||
5730 | /* WARNING: We can expand to two operands here. This has the potential | |
5731 | to totally confuse the backtracking mechanism! It will be OK at | |
5732 | least as long as we don't try to use optional args as well, | |
5733 | though. */ | |
5734 | case OP_NILO: | |
5735 | { | |
5736 | po_reg_or_goto (REG_TYPE_NDQ, try_imm); | |
466bbf93 | 5737 | inst.operands[i].present = 1; |
5287ad62 JB |
5738 | i++; |
5739 | skip_past_comma (&str); | |
5740 | po_reg_or_goto (REG_TYPE_NDQ, one_reg_only); | |
5741 | break; | |
5742 | one_reg_only: | |
5743 | /* Optional register operand was omitted. Unfortunately, it's in | |
5744 | operands[i-1] and we need it to be in inst.operands[i]. Fix that | |
5745 | here (this is a bit grotty). */ | |
5746 | inst.operands[i] = inst.operands[i-1]; | |
5747 | inst.operands[i-1].present = 0; | |
5748 | break; | |
5749 | try_imm: | |
036dc3f7 PB |
5750 | /* There's a possibility of getting a 64-bit immediate here, so |
5751 | we need special handling. */ | |
5752 | if (parse_big_immediate (&str, i) == FAIL) | |
5753 | { | |
5754 | inst.error = _("immediate value is out of range"); | |
5755 | goto failure; | |
5756 | } | |
5287ad62 JB |
5757 | } |
5758 | break; | |
5759 | ||
5760 | case OP_RNDQ_I0: | |
5761 | { | |
5762 | po_reg_or_goto (REG_TYPE_NDQ, try_imm0); | |
5763 | break; | |
5764 | try_imm0: | |
5765 | po_imm_or_fail (0, 0, TRUE); | |
5766 | } | |
5767 | break; | |
5768 | ||
037e8744 JB |
5769 | case OP_RVSD_I0: |
5770 | po_reg_or_goto (REG_TYPE_VFSD, try_imm0); | |
5771 | break; | |
5772 | ||
5287ad62 JB |
5773 | case OP_RR_RNSC: |
5774 | { | |
5775 | po_scalar_or_goto (8, try_rr); | |
5776 | break; | |
5777 | try_rr: | |
5778 | po_reg_or_fail (REG_TYPE_RN); | |
5779 | } | |
5780 | break; | |
5781 | ||
037e8744 JB |
5782 | case OP_RNSDQ_RNSC: |
5783 | { | |
5784 | po_scalar_or_goto (8, try_nsdq); | |
5785 | break; | |
5786 | try_nsdq: | |
5787 | po_reg_or_fail (REG_TYPE_NSDQ); | |
5788 | } | |
5789 | break; | |
5790 | ||
5287ad62 JB |
5791 | case OP_RNDQ_RNSC: |
5792 | { | |
5793 | po_scalar_or_goto (8, try_ndq); | |
5794 | break; | |
5795 | try_ndq: | |
5796 | po_reg_or_fail (REG_TYPE_NDQ); | |
5797 | } | |
5798 | break; | |
5799 | ||
5800 | case OP_RND_RNSC: | |
5801 | { | |
5802 | po_scalar_or_goto (8, try_vfd); | |
5803 | break; | |
5804 | try_vfd: | |
5805 | po_reg_or_fail (REG_TYPE_VFD); | |
5806 | } | |
5807 | break; | |
5808 | ||
5809 | case OP_VMOV: | |
5810 | /* WARNING: parse_neon_mov can move the operand counter, i. If we're | |
5811 | not careful then bad things might happen. */ | |
5812 | po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); | |
5813 | break; | |
5814 | ||
5815 | case OP_RNDQ_IMVNb: | |
5816 | { | |
5817 | po_reg_or_goto (REG_TYPE_NDQ, try_mvnimm); | |
5818 | break; | |
5819 | try_mvnimm: | |
5820 | /* There's a possibility of getting a 64-bit immediate here, so | |
5821 | we need special handling. */ | |
5822 | if (parse_big_immediate (&str, i) == FAIL) | |
5823 | { | |
5824 | inst.error = _("immediate value is out of range"); | |
5825 | goto failure; | |
5826 | } | |
5827 | } | |
5828 | break; | |
5829 | ||
5830 | case OP_RNDQ_I63b: | |
5831 | { | |
5832 | po_reg_or_goto (REG_TYPE_NDQ, try_shimm); | |
5833 | break; | |
5834 | try_shimm: | |
5835 | po_imm_or_fail (0, 63, TRUE); | |
5836 | } | |
5837 | break; | |
c19d1205 ZW |
5838 | |
5839 | case OP_RRnpcb: | |
5840 | po_char_or_fail ('['); | |
5841 | po_reg_or_fail (REG_TYPE_RN); | |
5842 | po_char_or_fail (']'); | |
5843 | break; | |
a737bd4d | 5844 | |
c19d1205 | 5845 | case OP_RRw: |
b6702015 | 5846 | case OP_oRRw: |
c19d1205 ZW |
5847 | po_reg_or_fail (REG_TYPE_RN); |
5848 | if (skip_past_char (&str, '!') == SUCCESS) | |
5849 | inst.operands[i].writeback = 1; | |
5850 | break; | |
5851 | ||
5852 | /* Immediates */ | |
5853 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
5854 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
5855 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
5287ad62 | 5856 | case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; |
c19d1205 ZW |
5857 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; |
5858 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
5287ad62 | 5859 | case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; |
c19d1205 | 5860 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; |
5287ad62 JB |
5861 | case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; |
5862 | case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; | |
5863 | case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; | |
c19d1205 | 5864 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; |
c19d1205 ZW |
5865 | |
5866 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
5867 | case OP_oI7b: | |
5868 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
5869 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
5870 | case OP_oI31b: | |
5871 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
5287ad62 | 5872 | case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; |
c19d1205 ZW |
5873 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; |
5874 | ||
5875 | /* Immediate variants */ | |
5876 | case OP_oI255c: | |
5877 | po_char_or_fail ('{'); | |
5878 | po_imm_or_fail (0, 255, TRUE); | |
5879 | po_char_or_fail ('}'); | |
5880 | break; | |
5881 | ||
5882 | case OP_I31w: | |
5883 | /* The expression parser chokes on a trailing !, so we have | |
5884 | to find it first and zap it. */ | |
5885 | { | |
5886 | char *s = str; | |
5887 | while (*s && *s != ',') | |
5888 | s++; | |
5889 | if (s[-1] == '!') | |
5890 | { | |
5891 | s[-1] = '\0'; | |
5892 | inst.operands[i].writeback = 1; | |
5893 | } | |
5894 | po_imm_or_fail (0, 31, TRUE); | |
5895 | if (str == s - 1) | |
5896 | str = s; | |
5897 | } | |
5898 | break; | |
5899 | ||
5900 | /* Expressions */ | |
5901 | case OP_EXPi: EXPi: | |
5902 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
5903 | GE_OPT_PREFIX)); | |
5904 | break; | |
5905 | ||
5906 | case OP_EXP: | |
5907 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
5908 | GE_NO_PREFIX)); | |
5909 | break; | |
5910 | ||
5911 | case OP_EXPr: EXPr: | |
5912 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
5913 | GE_NO_PREFIX)); | |
5914 | if (inst.reloc.exp.X_op == O_symbol) | |
a737bd4d | 5915 | { |
c19d1205 ZW |
5916 | val = parse_reloc (&str); |
5917 | if (val == -1) | |
5918 | { | |
5919 | inst.error = _("unrecognized relocation suffix"); | |
5920 | goto failure; | |
5921 | } | |
5922 | else if (val != BFD_RELOC_UNUSED) | |
5923 | { | |
5924 | inst.operands[i].imm = val; | |
5925 | inst.operands[i].hasreloc = 1; | |
5926 | } | |
a737bd4d | 5927 | } |
c19d1205 | 5928 | break; |
a737bd4d | 5929 | |
b6895b4f PB |
5930 | /* Operand for MOVW or MOVT. */ |
5931 | case OP_HALF: | |
5932 | po_misc_or_fail (parse_half (&str)); | |
5933 | break; | |
5934 | ||
e07e6e58 | 5935 | /* Register or expression. */ |
c19d1205 ZW |
5936 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; |
5937 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 5938 | |
e07e6e58 | 5939 | /* Register or immediate. */ |
c19d1205 ZW |
5940 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; |
5941 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 5942 | |
c19d1205 ZW |
5943 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
5944 | IF: | |
5945 | if (!is_immediate_prefix (*str)) | |
5946 | goto bad_args; | |
5947 | str++; | |
5948 | val = parse_fpa_immediate (&str); | |
5949 | if (val == FAIL) | |
5950 | goto failure; | |
5951 | /* FPA immediates are encoded as registers 8-15. | |
5952 | parse_fpa_immediate has already applied the offset. */ | |
5953 | inst.operands[i].reg = val; | |
5954 | inst.operands[i].isreg = 1; | |
5955 | break; | |
09d92015 | 5956 | |
2d447fca JM |
5957 | case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; |
5958 | I32z: po_imm_or_fail (0, 32, FALSE); break; | |
5959 | ||
e07e6e58 | 5960 | /* Two kinds of register. */ |
c19d1205 ZW |
5961 | case OP_RIWR_RIWC: |
5962 | { | |
5963 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
97f87066 JM |
5964 | if (!rege |
5965 | || (rege->type != REG_TYPE_MMXWR | |
5966 | && rege->type != REG_TYPE_MMXWC | |
5967 | && rege->type != REG_TYPE_MMXWCG)) | |
c19d1205 ZW |
5968 | { |
5969 | inst.error = _("iWMMXt data or control register expected"); | |
5970 | goto failure; | |
5971 | } | |
5972 | inst.operands[i].reg = rege->number; | |
5973 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
5974 | } | |
5975 | break; | |
09d92015 | 5976 | |
41adaa5c JM |
5977 | case OP_RIWC_RIWG: |
5978 | { | |
5979 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
5980 | if (!rege | |
5981 | || (rege->type != REG_TYPE_MMXWC | |
5982 | && rege->type != REG_TYPE_MMXWCG)) | |
5983 | { | |
5984 | inst.error = _("iWMMXt control register expected"); | |
5985 | goto failure; | |
5986 | } | |
5987 | inst.operands[i].reg = rege->number; | |
5988 | inst.operands[i].isreg = 1; | |
5989 | } | |
5990 | break; | |
5991 | ||
c19d1205 ZW |
5992 | /* Misc */ |
5993 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
5994 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
5995 | case OP_oROR: val = parse_ror (&str); break; | |
5996 | case OP_PSR: val = parse_psr (&str); break; | |
5997 | case OP_COND: val = parse_cond (&str); break; | |
62b3e311 | 5998 | case OP_oBARRIER:val = parse_barrier (&str); break; |
c19d1205 | 5999 | |
037e8744 JB |
6000 | case OP_RVC_PSR: |
6001 | po_reg_or_goto (REG_TYPE_VFC, try_psr); | |
6002 | inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */ | |
6003 | break; | |
6004 | try_psr: | |
6005 | val = parse_psr (&str); | |
6006 | break; | |
6007 | ||
6008 | case OP_APSR_RR: | |
6009 | po_reg_or_goto (REG_TYPE_RN, try_apsr); | |
6010 | break; | |
6011 | try_apsr: | |
6012 | /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS | |
6013 | instruction). */ | |
6014 | if (strncasecmp (str, "APSR_", 5) == 0) | |
6015 | { | |
6016 | unsigned found = 0; | |
6017 | str += 5; | |
6018 | while (found < 15) | |
6019 | switch (*str++) | |
6020 | { | |
6021 | case 'c': found = (found & 1) ? 16 : found | 1; break; | |
6022 | case 'n': found = (found & 2) ? 16 : found | 2; break; | |
6023 | case 'z': found = (found & 4) ? 16 : found | 4; break; | |
6024 | case 'v': found = (found & 8) ? 16 : found | 8; break; | |
6025 | default: found = 16; | |
6026 | } | |
6027 | if (found != 15) | |
6028 | goto failure; | |
6029 | inst.operands[i].isvec = 1; | |
6030 | } | |
6031 | else | |
6032 | goto failure; | |
6033 | break; | |
6034 | ||
92e90b6e PB |
6035 | case OP_TB: |
6036 | po_misc_or_fail (parse_tb (&str)); | |
6037 | break; | |
6038 | ||
e07e6e58 | 6039 | /* Register lists. */ |
c19d1205 ZW |
6040 | case OP_REGLST: |
6041 | val = parse_reg_list (&str); | |
6042 | if (*str == '^') | |
6043 | { | |
6044 | inst.operands[1].writeback = 1; | |
6045 | str++; | |
6046 | } | |
6047 | break; | |
09d92015 | 6048 | |
c19d1205 | 6049 | case OP_VRSLST: |
5287ad62 | 6050 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); |
c19d1205 | 6051 | break; |
09d92015 | 6052 | |
c19d1205 | 6053 | case OP_VRDLST: |
5287ad62 | 6054 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); |
c19d1205 | 6055 | break; |
a737bd4d | 6056 | |
037e8744 JB |
6057 | case OP_VRSDLST: |
6058 | /* Allow Q registers too. */ | |
6059 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6060 | REGLIST_NEON_D); | |
6061 | if (val == FAIL) | |
6062 | { | |
6063 | inst.error = NULL; | |
6064 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6065 | REGLIST_VFP_S); | |
6066 | inst.operands[i].issingle = 1; | |
6067 | } | |
6068 | break; | |
6069 | ||
5287ad62 JB |
6070 | case OP_NRDLST: |
6071 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6072 | REGLIST_NEON_D); | |
6073 | break; | |
6074 | ||
6075 | case OP_NSTRLST: | |
dcbf9037 JB |
6076 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, |
6077 | &inst.operands[i].vectype); | |
5287ad62 JB |
6078 | break; |
6079 | ||
c19d1205 ZW |
6080 | /* Addressing modes */ |
6081 | case OP_ADDR: | |
6082 | po_misc_or_fail (parse_address (&str, i)); | |
6083 | break; | |
09d92015 | 6084 | |
4962c51a MS |
6085 | case OP_ADDRGLDR: |
6086 | po_misc_or_fail_no_backtrack ( | |
6087 | parse_address_group_reloc (&str, i, GROUP_LDR)); | |
6088 | break; | |
6089 | ||
6090 | case OP_ADDRGLDRS: | |
6091 | po_misc_or_fail_no_backtrack ( | |
6092 | parse_address_group_reloc (&str, i, GROUP_LDRS)); | |
6093 | break; | |
6094 | ||
6095 | case OP_ADDRGLDC: | |
6096 | po_misc_or_fail_no_backtrack ( | |
6097 | parse_address_group_reloc (&str, i, GROUP_LDC)); | |
6098 | break; | |
6099 | ||
c19d1205 ZW |
6100 | case OP_SH: |
6101 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
6102 | break; | |
09d92015 | 6103 | |
4962c51a MS |
6104 | case OP_SHG: |
6105 | po_misc_or_fail_no_backtrack ( | |
6106 | parse_shifter_operand_group_reloc (&str, i)); | |
6107 | break; | |
6108 | ||
c19d1205 ZW |
6109 | case OP_oSHll: |
6110 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
6111 | break; | |
09d92015 | 6112 | |
c19d1205 ZW |
6113 | case OP_oSHar: |
6114 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
6115 | break; | |
09d92015 | 6116 | |
c19d1205 ZW |
6117 | case OP_oSHllar: |
6118 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
6119 | break; | |
09d92015 | 6120 | |
c19d1205 | 6121 | default: |
bd3ba5d1 | 6122 | as_fatal (_("unhandled operand code %d"), upat[i]); |
c19d1205 | 6123 | } |
09d92015 | 6124 | |
c19d1205 ZW |
6125 | /* Various value-based sanity checks and shared operations. We |
6126 | do not signal immediate failures for the register constraints; | |
6127 | this allows a syntax error to take precedence. */ | |
6128 | switch (upat[i]) | |
6129 | { | |
6130 | case OP_oRRnpc: | |
6131 | case OP_RRnpc: | |
6132 | case OP_RRnpcb: | |
6133 | case OP_RRw: | |
b6702015 | 6134 | case OP_oRRw: |
c19d1205 ZW |
6135 | case OP_RRnpc_I0: |
6136 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
6137 | inst.error = BAD_PC; | |
6138 | break; | |
09d92015 | 6139 | |
c19d1205 ZW |
6140 | case OP_CPSF: |
6141 | case OP_ENDI: | |
6142 | case OP_oROR: | |
6143 | case OP_PSR: | |
037e8744 | 6144 | case OP_RVC_PSR: |
c19d1205 | 6145 | case OP_COND: |
62b3e311 | 6146 | case OP_oBARRIER: |
c19d1205 ZW |
6147 | case OP_REGLST: |
6148 | case OP_VRSLST: | |
6149 | case OP_VRDLST: | |
037e8744 | 6150 | case OP_VRSDLST: |
5287ad62 JB |
6151 | case OP_NRDLST: |
6152 | case OP_NSTRLST: | |
c19d1205 ZW |
6153 | if (val == FAIL) |
6154 | goto failure; | |
6155 | inst.operands[i].imm = val; | |
6156 | break; | |
a737bd4d | 6157 | |
c19d1205 ZW |
6158 | default: |
6159 | break; | |
6160 | } | |
09d92015 | 6161 | |
c19d1205 ZW |
6162 | /* If we get here, this operand was successfully parsed. */ |
6163 | inst.operands[i].present = 1; | |
6164 | continue; | |
09d92015 | 6165 | |
c19d1205 | 6166 | bad_args: |
09d92015 | 6167 | inst.error = BAD_ARGS; |
c19d1205 ZW |
6168 | |
6169 | failure: | |
6170 | if (!backtrack_pos) | |
d252fdde PB |
6171 | { |
6172 | /* The parse routine should already have set inst.error, but set a | |
5f4273c7 | 6173 | default here just in case. */ |
d252fdde PB |
6174 | if (!inst.error) |
6175 | inst.error = _("syntax error"); | |
6176 | return FAIL; | |
6177 | } | |
c19d1205 ZW |
6178 | |
6179 | /* Do not backtrack over a trailing optional argument that | |
6180 | absorbed some text. We will only fail again, with the | |
6181 | 'garbage following instruction' error message, which is | |
6182 | probably less helpful than the current one. */ | |
6183 | if (backtrack_index == i && backtrack_pos != str | |
6184 | && upat[i+1] == OP_stop) | |
d252fdde PB |
6185 | { |
6186 | if (!inst.error) | |
6187 | inst.error = _("syntax error"); | |
6188 | return FAIL; | |
6189 | } | |
c19d1205 ZW |
6190 | |
6191 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
6192 | str = backtrack_pos; | |
6193 | inst.error = backtrack_error; | |
6194 | inst.operands[backtrack_index].present = 0; | |
6195 | i = backtrack_index; | |
6196 | backtrack_pos = 0; | |
09d92015 | 6197 | } |
09d92015 | 6198 | |
c19d1205 ZW |
6199 | /* Check that we have parsed all the arguments. */ |
6200 | if (*str != '\0' && !inst.error) | |
6201 | inst.error = _("garbage following instruction"); | |
09d92015 | 6202 | |
c19d1205 | 6203 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
6204 | } |
6205 | ||
c19d1205 ZW |
6206 | #undef po_char_or_fail |
6207 | #undef po_reg_or_fail | |
6208 | #undef po_reg_or_goto | |
6209 | #undef po_imm_or_fail | |
5287ad62 | 6210 | #undef po_scalar_or_fail |
e07e6e58 | 6211 | |
c19d1205 | 6212 | /* Shorthand macro for instruction encoding functions issuing errors. */ |
e07e6e58 NC |
6213 | #define constraint(expr, err) \ |
6214 | do \ | |
c19d1205 | 6215 | { \ |
e07e6e58 NC |
6216 | if (expr) \ |
6217 | { \ | |
6218 | inst.error = err; \ | |
6219 | return; \ | |
6220 | } \ | |
c19d1205 | 6221 | } \ |
e07e6e58 | 6222 | while (0) |
c19d1205 | 6223 | |
fdfde340 JM |
6224 | /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 |
6225 | instructions are unpredictable if these registers are used. This | |
6226 | is the BadReg predicate in ARM's Thumb-2 documentation. */ | |
6227 | #define reject_bad_reg(reg) \ | |
6228 | do \ | |
6229 | if (reg == REG_SP || reg == REG_PC) \ | |
6230 | { \ | |
6231 | inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \ | |
6232 | return; \ | |
6233 | } \ | |
6234 | while (0) | |
6235 | ||
94206790 MM |
6236 | /* If REG is R13 (the stack pointer), warn that its use is |
6237 | deprecated. */ | |
6238 | #define warn_deprecated_sp(reg) \ | |
6239 | do \ | |
6240 | if (warn_on_deprecated && reg == REG_SP) \ | |
6241 | as_warn (_("use of r13 is deprecated")); \ | |
6242 | while (0) | |
6243 | ||
c19d1205 ZW |
6244 | /* Functions for operand encoding. ARM, then Thumb. */ |
6245 | ||
6246 | #define rotate_left(v, n) (v << n | v >> (32 - n)) | |
6247 | ||
6248 | /* If VAL can be encoded in the immediate field of an ARM instruction, | |
6249 | return the encoded form. Otherwise, return FAIL. */ | |
6250 | ||
6251 | static unsigned int | |
6252 | encode_arm_immediate (unsigned int val) | |
09d92015 | 6253 | { |
c19d1205 ZW |
6254 | unsigned int a, i; |
6255 | ||
6256 | for (i = 0; i < 32; i += 2) | |
6257 | if ((a = rotate_left (val, i)) <= 0xff) | |
6258 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
6259 | ||
6260 | return FAIL; | |
09d92015 MM |
6261 | } |
6262 | ||
c19d1205 ZW |
6263 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
6264 | return the encoded form. Otherwise, return FAIL. */ | |
6265 | static unsigned int | |
6266 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 6267 | { |
c19d1205 | 6268 | unsigned int a, i; |
09d92015 | 6269 | |
9c3c69f2 | 6270 | if (val <= 0xff) |
c19d1205 | 6271 | return val; |
a737bd4d | 6272 | |
9c3c69f2 | 6273 | for (i = 1; i <= 24; i++) |
09d92015 | 6274 | { |
9c3c69f2 PB |
6275 | a = val >> i; |
6276 | if ((val & ~(0xff << i)) == 0) | |
6277 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 6278 | } |
a737bd4d | 6279 | |
c19d1205 ZW |
6280 | a = val & 0xff; |
6281 | if (val == ((a << 16) | a)) | |
6282 | return 0x100 | a; | |
6283 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
6284 | return 0x300 | a; | |
09d92015 | 6285 | |
c19d1205 ZW |
6286 | a = val & 0xff00; |
6287 | if (val == ((a << 16) | a)) | |
6288 | return 0x200 | (a >> 8); | |
a737bd4d | 6289 | |
c19d1205 | 6290 | return FAIL; |
09d92015 | 6291 | } |
5287ad62 | 6292 | /* Encode a VFP SP or DP register number into inst.instruction. */ |
09d92015 MM |
6293 | |
6294 | static void | |
5287ad62 JB |
6295 | encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) |
6296 | { | |
6297 | if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) | |
6298 | && reg > 15) | |
6299 | { | |
b1cc4aeb | 6300 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) |
5287ad62 JB |
6301 | { |
6302 | if (thumb_mode) | |
6303 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
b1cc4aeb | 6304 | fpu_vfp_ext_d32); |
5287ad62 JB |
6305 | else |
6306 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
b1cc4aeb | 6307 | fpu_vfp_ext_d32); |
5287ad62 JB |
6308 | } |
6309 | else | |
6310 | { | |
dcbf9037 | 6311 | first_error (_("D register out of range for selected VFP version")); |
5287ad62 JB |
6312 | return; |
6313 | } | |
6314 | } | |
6315 | ||
c19d1205 | 6316 | switch (pos) |
09d92015 | 6317 | { |
c19d1205 ZW |
6318 | case VFP_REG_Sd: |
6319 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
6320 | break; | |
6321 | ||
6322 | case VFP_REG_Sn: | |
6323 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
6324 | break; | |
6325 | ||
6326 | case VFP_REG_Sm: | |
6327 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
6328 | break; | |
6329 | ||
5287ad62 JB |
6330 | case VFP_REG_Dd: |
6331 | inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); | |
6332 | break; | |
5f4273c7 | 6333 | |
5287ad62 JB |
6334 | case VFP_REG_Dn: |
6335 | inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); | |
6336 | break; | |
5f4273c7 | 6337 | |
5287ad62 JB |
6338 | case VFP_REG_Dm: |
6339 | inst.instruction |= (reg & 15) | ((reg >> 4) << 5); | |
6340 | break; | |
6341 | ||
c19d1205 ZW |
6342 | default: |
6343 | abort (); | |
09d92015 | 6344 | } |
09d92015 MM |
6345 | } |
6346 | ||
c19d1205 | 6347 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 6348 | if any, is handled by md_apply_fix. */ |
09d92015 | 6349 | static void |
c19d1205 | 6350 | encode_arm_shift (int i) |
09d92015 | 6351 | { |
c19d1205 ZW |
6352 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
6353 | inst.instruction |= SHIFT_ROR << 5; | |
6354 | else | |
09d92015 | 6355 | { |
c19d1205 ZW |
6356 | inst.instruction |= inst.operands[i].shift_kind << 5; |
6357 | if (inst.operands[i].immisreg) | |
6358 | { | |
6359 | inst.instruction |= SHIFT_BY_REG; | |
6360 | inst.instruction |= inst.operands[i].imm << 8; | |
6361 | } | |
6362 | else | |
6363 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
09d92015 | 6364 | } |
c19d1205 | 6365 | } |
09d92015 | 6366 | |
c19d1205 ZW |
6367 | static void |
6368 | encode_arm_shifter_operand (int i) | |
6369 | { | |
6370 | if (inst.operands[i].isreg) | |
09d92015 | 6371 | { |
c19d1205 ZW |
6372 | inst.instruction |= inst.operands[i].reg; |
6373 | encode_arm_shift (i); | |
09d92015 | 6374 | } |
c19d1205 ZW |
6375 | else |
6376 | inst.instruction |= INST_IMMEDIATE; | |
09d92015 MM |
6377 | } |
6378 | ||
c19d1205 | 6379 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 6380 | static void |
c19d1205 | 6381 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 6382 | { |
c19d1205 ZW |
6383 | assert (inst.operands[i].isreg); |
6384 | inst.instruction |= inst.operands[i].reg << 16; | |
a737bd4d | 6385 | |
c19d1205 | 6386 | if (inst.operands[i].preind) |
09d92015 | 6387 | { |
c19d1205 ZW |
6388 | if (is_t) |
6389 | { | |
6390 | inst.error = _("instruction does not accept preindexed addressing"); | |
6391 | return; | |
6392 | } | |
6393 | inst.instruction |= PRE_INDEX; | |
6394 | if (inst.operands[i].writeback) | |
6395 | inst.instruction |= WRITE_BACK; | |
09d92015 | 6396 | |
c19d1205 ZW |
6397 | } |
6398 | else if (inst.operands[i].postind) | |
6399 | { | |
6400 | assert (inst.operands[i].writeback); | |
6401 | if (is_t) | |
6402 | inst.instruction |= WRITE_BACK; | |
6403 | } | |
6404 | else /* unindexed - only for coprocessor */ | |
09d92015 | 6405 | { |
c19d1205 | 6406 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
6407 | return; |
6408 | } | |
6409 | ||
c19d1205 ZW |
6410 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
6411 | && (((inst.instruction & 0x000f0000) >> 16) | |
6412 | == ((inst.instruction & 0x0000f000) >> 12))) | |
6413 | as_warn ((inst.instruction & LOAD_BIT) | |
6414 | ? _("destination register same as write-back base") | |
6415 | : _("source register same as write-back base")); | |
09d92015 MM |
6416 | } |
6417 | ||
c19d1205 ZW |
6418 | /* inst.operands[i] was set up by parse_address. Encode it into an |
6419 | ARM-format mode 2 load or store instruction. If is_t is true, | |
6420 | reject forms that cannot be used with a T instruction (i.e. not | |
6421 | post-indexed). */ | |
a737bd4d | 6422 | static void |
c19d1205 | 6423 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 6424 | { |
c19d1205 | 6425 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 6426 | |
c19d1205 | 6427 | if (inst.operands[i].immisreg) |
09d92015 | 6428 | { |
c19d1205 ZW |
6429 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
6430 | inst.instruction |= inst.operands[i].imm; | |
6431 | if (!inst.operands[i].negative) | |
6432 | inst.instruction |= INDEX_UP; | |
6433 | if (inst.operands[i].shifted) | |
6434 | { | |
6435 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
6436 | inst.instruction |= SHIFT_ROR << 5; | |
6437 | else | |
6438 | { | |
6439 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
6440 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
6441 | } | |
6442 | } | |
09d92015 | 6443 | } |
c19d1205 | 6444 | else /* immediate offset in inst.reloc */ |
09d92015 | 6445 | { |
c19d1205 ZW |
6446 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
6447 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
09d92015 | 6448 | } |
09d92015 MM |
6449 | } |
6450 | ||
c19d1205 ZW |
6451 | /* inst.operands[i] was set up by parse_address. Encode it into an |
6452 | ARM-format mode 3 load or store instruction. Reject forms that | |
6453 | cannot be used with such instructions. If is_t is true, reject | |
6454 | forms that cannot be used with a T instruction (i.e. not | |
6455 | post-indexed). */ | |
6456 | static void | |
6457 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 6458 | { |
c19d1205 | 6459 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 6460 | { |
c19d1205 ZW |
6461 | inst.error = _("instruction does not accept scaled register index"); |
6462 | return; | |
09d92015 | 6463 | } |
a737bd4d | 6464 | |
c19d1205 | 6465 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 6466 | |
c19d1205 ZW |
6467 | if (inst.operands[i].immisreg) |
6468 | { | |
6469 | inst.instruction |= inst.operands[i].imm; | |
6470 | if (!inst.operands[i].negative) | |
6471 | inst.instruction |= INDEX_UP; | |
6472 | } | |
6473 | else /* immediate offset in inst.reloc */ | |
6474 | { | |
6475 | inst.instruction |= HWOFFSET_IMM; | |
6476 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
6477 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
c19d1205 | 6478 | } |
a737bd4d NC |
6479 | } |
6480 | ||
c19d1205 ZW |
6481 | /* inst.operands[i] was set up by parse_address. Encode it into an |
6482 | ARM-format instruction. Reject all forms which cannot be encoded | |
6483 | into a coprocessor load/store instruction. If wb_ok is false, | |
6484 | reject use of writeback; if unind_ok is false, reject use of | |
6485 | unindexed addressing. If reloc_override is not 0, use it instead | |
4962c51a MS |
6486 | of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one |
6487 | (in which case it is preserved). */ | |
09d92015 | 6488 | |
c19d1205 ZW |
6489 | static int |
6490 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
09d92015 | 6491 | { |
c19d1205 | 6492 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 6493 | |
c19d1205 | 6494 | assert (!(inst.operands[i].preind && inst.operands[i].postind)); |
09d92015 | 6495 | |
c19d1205 | 6496 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ |
09d92015 | 6497 | { |
c19d1205 ZW |
6498 | assert (!inst.operands[i].writeback); |
6499 | if (!unind_ok) | |
6500 | { | |
6501 | inst.error = _("instruction does not support unindexed addressing"); | |
6502 | return FAIL; | |
6503 | } | |
6504 | inst.instruction |= inst.operands[i].imm; | |
6505 | inst.instruction |= INDEX_UP; | |
6506 | return SUCCESS; | |
09d92015 | 6507 | } |
a737bd4d | 6508 | |
c19d1205 ZW |
6509 | if (inst.operands[i].preind) |
6510 | inst.instruction |= PRE_INDEX; | |
a737bd4d | 6511 | |
c19d1205 | 6512 | if (inst.operands[i].writeback) |
09d92015 | 6513 | { |
c19d1205 ZW |
6514 | if (inst.operands[i].reg == REG_PC) |
6515 | { | |
6516 | inst.error = _("pc may not be used with write-back"); | |
6517 | return FAIL; | |
6518 | } | |
6519 | if (!wb_ok) | |
6520 | { | |
6521 | inst.error = _("instruction does not support writeback"); | |
6522 | return FAIL; | |
6523 | } | |
6524 | inst.instruction |= WRITE_BACK; | |
09d92015 | 6525 | } |
a737bd4d | 6526 | |
c19d1205 ZW |
6527 | if (reloc_override) |
6528 | inst.reloc.type = reloc_override; | |
4962c51a MS |
6529 | else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC |
6530 | || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) | |
6531 | && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) | |
6532 | { | |
6533 | if (thumb_mode) | |
6534 | inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; | |
6535 | else | |
6536 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; | |
6537 | } | |
6538 | ||
c19d1205 ZW |
6539 | return SUCCESS; |
6540 | } | |
a737bd4d | 6541 | |
c19d1205 ZW |
6542 | /* inst.reloc.exp describes an "=expr" load pseudo-operation. |
6543 | Determine whether it can be performed with a move instruction; if | |
6544 | it can, convert inst.instruction to that move instruction and | |
6545 | return 1; if it can't, convert inst.instruction to a literal-pool | |
6546 | load and return 0. If this is not a valid thing to do in the | |
6547 | current context, set inst.error and return 1. | |
a737bd4d | 6548 | |
c19d1205 ZW |
6549 | inst.operands[i] describes the destination register. */ |
6550 | ||
6551 | static int | |
6552 | move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) | |
6553 | { | |
53365c0d PB |
6554 | unsigned long tbit; |
6555 | ||
6556 | if (thumb_p) | |
6557 | tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; | |
6558 | else | |
6559 | tbit = LOAD_BIT; | |
6560 | ||
6561 | if ((inst.instruction & tbit) == 0) | |
09d92015 | 6562 | { |
c19d1205 ZW |
6563 | inst.error = _("invalid pseudo operation"); |
6564 | return 1; | |
09d92015 | 6565 | } |
c19d1205 | 6566 | if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) |
09d92015 MM |
6567 | { |
6568 | inst.error = _("constant expression expected"); | |
c19d1205 | 6569 | return 1; |
09d92015 | 6570 | } |
c19d1205 | 6571 | if (inst.reloc.exp.X_op == O_constant) |
09d92015 | 6572 | { |
c19d1205 ZW |
6573 | if (thumb_p) |
6574 | { | |
53365c0d | 6575 | if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) |
c19d1205 ZW |
6576 | { |
6577 | /* This can be done with a mov(1) instruction. */ | |
6578 | inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); | |
6579 | inst.instruction |= inst.reloc.exp.X_add_number; | |
6580 | return 1; | |
6581 | } | |
6582 | } | |
6583 | else | |
6584 | { | |
6585 | int value = encode_arm_immediate (inst.reloc.exp.X_add_number); | |
6586 | if (value != FAIL) | |
6587 | { | |
6588 | /* This can be done with a mov instruction. */ | |
6589 | inst.instruction &= LITERAL_MASK; | |
6590 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
6591 | inst.instruction |= value & 0xfff; | |
6592 | return 1; | |
6593 | } | |
09d92015 | 6594 | |
c19d1205 ZW |
6595 | value = encode_arm_immediate (~inst.reloc.exp.X_add_number); |
6596 | if (value != FAIL) | |
6597 | { | |
6598 | /* This can be done with a mvn instruction. */ | |
6599 | inst.instruction &= LITERAL_MASK; | |
6600 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
6601 | inst.instruction |= value & 0xfff; | |
6602 | return 1; | |
6603 | } | |
6604 | } | |
09d92015 MM |
6605 | } |
6606 | ||
c19d1205 ZW |
6607 | if (add_to_lit_pool () == FAIL) |
6608 | { | |
6609 | inst.error = _("literal pool insertion failed"); | |
6610 | return 1; | |
6611 | } | |
6612 | inst.operands[1].reg = REG_PC; | |
6613 | inst.operands[1].isreg = 1; | |
6614 | inst.operands[1].preind = 1; | |
6615 | inst.reloc.pc_rel = 1; | |
6616 | inst.reloc.type = (thumb_p | |
6617 | ? BFD_RELOC_ARM_THUMB_OFFSET | |
6618 | : (mode_3 | |
6619 | ? BFD_RELOC_ARM_HWLITERAL | |
6620 | : BFD_RELOC_ARM_LITERAL)); | |
6621 | return 0; | |
09d92015 MM |
6622 | } |
6623 | ||
5f4273c7 | 6624 | /* Functions for instruction encoding, sorted by sub-architecture. |
c19d1205 ZW |
6625 | First some generics; their names are taken from the conventional |
6626 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 6627 | |
a737bd4d | 6628 | static void |
c19d1205 | 6629 | do_noargs (void) |
09d92015 | 6630 | { |
c19d1205 | 6631 | } |
a737bd4d | 6632 | |
c19d1205 ZW |
6633 | static void |
6634 | do_rd (void) | |
6635 | { | |
6636 | inst.instruction |= inst.operands[0].reg << 12; | |
6637 | } | |
a737bd4d | 6638 | |
c19d1205 ZW |
6639 | static void |
6640 | do_rd_rm (void) | |
6641 | { | |
6642 | inst.instruction |= inst.operands[0].reg << 12; | |
6643 | inst.instruction |= inst.operands[1].reg; | |
6644 | } | |
09d92015 | 6645 | |
c19d1205 ZW |
6646 | static void |
6647 | do_rd_rn (void) | |
6648 | { | |
6649 | inst.instruction |= inst.operands[0].reg << 12; | |
6650 | inst.instruction |= inst.operands[1].reg << 16; | |
6651 | } | |
a737bd4d | 6652 | |
c19d1205 ZW |
6653 | static void |
6654 | do_rn_rd (void) | |
6655 | { | |
6656 | inst.instruction |= inst.operands[0].reg << 16; | |
6657 | inst.instruction |= inst.operands[1].reg << 12; | |
6658 | } | |
09d92015 | 6659 | |
c19d1205 ZW |
6660 | static void |
6661 | do_rd_rm_rn (void) | |
6662 | { | |
9a64e435 | 6663 | unsigned Rn = inst.operands[2].reg; |
708587a4 | 6664 | /* Enforce restrictions on SWP instruction. */ |
9a64e435 PB |
6665 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) |
6666 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
6667 | _("Rn must not overlap other operands")); | |
c19d1205 ZW |
6668 | inst.instruction |= inst.operands[0].reg << 12; |
6669 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 6670 | inst.instruction |= Rn << 16; |
c19d1205 | 6671 | } |
09d92015 | 6672 | |
c19d1205 ZW |
6673 | static void |
6674 | do_rd_rn_rm (void) | |
6675 | { | |
6676 | inst.instruction |= inst.operands[0].reg << 12; | |
6677 | inst.instruction |= inst.operands[1].reg << 16; | |
6678 | inst.instruction |= inst.operands[2].reg; | |
6679 | } | |
a737bd4d | 6680 | |
c19d1205 ZW |
6681 | static void |
6682 | do_rm_rd_rn (void) | |
6683 | { | |
6684 | inst.instruction |= inst.operands[0].reg; | |
6685 | inst.instruction |= inst.operands[1].reg << 12; | |
6686 | inst.instruction |= inst.operands[2].reg << 16; | |
6687 | } | |
09d92015 | 6688 | |
c19d1205 ZW |
6689 | static void |
6690 | do_imm0 (void) | |
6691 | { | |
6692 | inst.instruction |= inst.operands[0].imm; | |
6693 | } | |
09d92015 | 6694 | |
c19d1205 ZW |
6695 | static void |
6696 | do_rd_cpaddr (void) | |
6697 | { | |
6698 | inst.instruction |= inst.operands[0].reg << 12; | |
6699 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 6700 | } |
a737bd4d | 6701 | |
c19d1205 ZW |
6702 | /* ARM instructions, in alphabetical order by function name (except |
6703 | that wrapper functions appear immediately after the function they | |
6704 | wrap). */ | |
09d92015 | 6705 | |
c19d1205 ZW |
6706 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
6707 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
6708 | |
6709 | static void | |
c19d1205 | 6710 | do_adr (void) |
09d92015 | 6711 | { |
c19d1205 | 6712 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 6713 | |
c19d1205 ZW |
6714 | /* Frag hacking will turn this into a sub instruction if the offset turns |
6715 | out to be negative. */ | |
6716 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
c19d1205 | 6717 | inst.reloc.pc_rel = 1; |
2fc8bdac | 6718 | inst.reloc.exp.X_add_number -= 8; |
c19d1205 | 6719 | } |
b99bd4ef | 6720 | |
c19d1205 ZW |
6721 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
6722 | into a relative address of the form: | |
6723 | add rd, pc, #low(label-.-8)" | |
6724 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 6725 | |
c19d1205 ZW |
6726 | static void |
6727 | do_adrl (void) | |
6728 | { | |
6729 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 6730 | |
c19d1205 ZW |
6731 | /* Frag hacking will turn this into a sub instruction if the offset turns |
6732 | out to be negative. */ | |
6733 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
c19d1205 ZW |
6734 | inst.reloc.pc_rel = 1; |
6735 | inst.size = INSN_SIZE * 2; | |
2fc8bdac | 6736 | inst.reloc.exp.X_add_number -= 8; |
b99bd4ef NC |
6737 | } |
6738 | ||
b99bd4ef | 6739 | static void |
c19d1205 | 6740 | do_arit (void) |
b99bd4ef | 6741 | { |
c19d1205 ZW |
6742 | if (!inst.operands[1].present) |
6743 | inst.operands[1].reg = inst.operands[0].reg; | |
6744 | inst.instruction |= inst.operands[0].reg << 12; | |
6745 | inst.instruction |= inst.operands[1].reg << 16; | |
6746 | encode_arm_shifter_operand (2); | |
6747 | } | |
b99bd4ef | 6748 | |
62b3e311 PB |
6749 | static void |
6750 | do_barrier (void) | |
6751 | { | |
6752 | if (inst.operands[0].present) | |
6753 | { | |
6754 | constraint ((inst.instruction & 0xf0) != 0x40 | |
6755 | && inst.operands[0].imm != 0xf, | |
bd3ba5d1 | 6756 | _("bad barrier type")); |
62b3e311 PB |
6757 | inst.instruction |= inst.operands[0].imm; |
6758 | } | |
6759 | else | |
6760 | inst.instruction |= 0xf; | |
6761 | } | |
6762 | ||
c19d1205 ZW |
6763 | static void |
6764 | do_bfc (void) | |
6765 | { | |
6766 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
6767 | constraint (msb > 32, _("bit-field extends past end of register")); | |
6768 | /* The instruction encoding stores the LSB and MSB, | |
6769 | not the LSB and width. */ | |
6770 | inst.instruction |= inst.operands[0].reg << 12; | |
6771 | inst.instruction |= inst.operands[1].imm << 7; | |
6772 | inst.instruction |= (msb - 1) << 16; | |
6773 | } | |
b99bd4ef | 6774 | |
c19d1205 ZW |
6775 | static void |
6776 | do_bfi (void) | |
6777 | { | |
6778 | unsigned int msb; | |
b99bd4ef | 6779 | |
c19d1205 ZW |
6780 | /* #0 in second position is alternative syntax for bfc, which is |
6781 | the same instruction but with REG_PC in the Rm field. */ | |
6782 | if (!inst.operands[1].isreg) | |
6783 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 6784 | |
c19d1205 ZW |
6785 | msb = inst.operands[2].imm + inst.operands[3].imm; |
6786 | constraint (msb > 32, _("bit-field extends past end of register")); | |
6787 | /* The instruction encoding stores the LSB and MSB, | |
6788 | not the LSB and width. */ | |
6789 | inst.instruction |= inst.operands[0].reg << 12; | |
6790 | inst.instruction |= inst.operands[1].reg; | |
6791 | inst.instruction |= inst.operands[2].imm << 7; | |
6792 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
6793 | } |
6794 | ||
b99bd4ef | 6795 | static void |
c19d1205 | 6796 | do_bfx (void) |
b99bd4ef | 6797 | { |
c19d1205 ZW |
6798 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
6799 | _("bit-field extends past end of register")); | |
6800 | inst.instruction |= inst.operands[0].reg << 12; | |
6801 | inst.instruction |= inst.operands[1].reg; | |
6802 | inst.instruction |= inst.operands[2].imm << 7; | |
6803 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
6804 | } | |
09d92015 | 6805 | |
c19d1205 ZW |
6806 | /* ARM V5 breakpoint instruction (argument parse) |
6807 | BKPT <16 bit unsigned immediate> | |
6808 | Instruction is not conditional. | |
6809 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
6810 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 6811 | |
c19d1205 ZW |
6812 | static void |
6813 | do_bkpt (void) | |
6814 | { | |
6815 | /* Top 12 of 16 bits to bits 19:8. */ | |
6816 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 6817 | |
c19d1205 ZW |
6818 | /* Bottom 4 of 16 bits to bits 3:0. */ |
6819 | inst.instruction |= inst.operands[0].imm & 0xf; | |
6820 | } | |
09d92015 | 6821 | |
c19d1205 ZW |
6822 | static void |
6823 | encode_branch (int default_reloc) | |
6824 | { | |
6825 | if (inst.operands[0].hasreloc) | |
6826 | { | |
6827 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32, | |
6828 | _("the only suffix valid here is '(plt)'")); | |
267bf995 | 6829 | inst.reloc.type = BFD_RELOC_ARM_PLT32; |
c19d1205 | 6830 | } |
b99bd4ef | 6831 | else |
c19d1205 ZW |
6832 | { |
6833 | inst.reloc.type = default_reloc; | |
c19d1205 | 6834 | } |
2fc8bdac | 6835 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
6836 | } |
6837 | ||
b99bd4ef | 6838 | static void |
c19d1205 | 6839 | do_branch (void) |
b99bd4ef | 6840 | { |
39b41c9c PB |
6841 | #ifdef OBJ_ELF |
6842 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
6843 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
6844 | else | |
6845 | #endif | |
6846 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
6847 | } | |
6848 | ||
6849 | static void | |
6850 | do_bl (void) | |
6851 | { | |
6852 | #ifdef OBJ_ELF | |
6853 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
6854 | { | |
6855 | if (inst.cond == COND_ALWAYS) | |
6856 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
6857 | else | |
6858 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
6859 | } | |
6860 | else | |
6861 | #endif | |
6862 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
c19d1205 | 6863 | } |
b99bd4ef | 6864 | |
c19d1205 ZW |
6865 | /* ARM V5 branch-link-exchange instruction (argument parse) |
6866 | BLX <target_addr> ie BLX(1) | |
6867 | BLX{<condition>} <Rm> ie BLX(2) | |
6868 | Unfortunately, there are two different opcodes for this mnemonic. | |
6869 | So, the insns[].value is not used, and the code here zaps values | |
6870 | into inst.instruction. | |
6871 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 6872 | |
c19d1205 ZW |
6873 | static void |
6874 | do_blx (void) | |
6875 | { | |
6876 | if (inst.operands[0].isreg) | |
b99bd4ef | 6877 | { |
c19d1205 ZW |
6878 | /* Arg is a register; the opcode provided by insns[] is correct. |
6879 | It is not illegal to do "blx pc", just useless. */ | |
6880 | if (inst.operands[0].reg == REG_PC) | |
6881 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 6882 | |
c19d1205 ZW |
6883 | inst.instruction |= inst.operands[0].reg; |
6884 | } | |
6885 | else | |
b99bd4ef | 6886 | { |
c19d1205 | 6887 | /* Arg is an address; this instruction cannot be executed |
267bf995 RR |
6888 | conditionally, and the opcode must be adjusted. |
6889 | We retain the BFD_RELOC_ARM_PCREL_BLX till the very end | |
6890 | where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */ | |
c19d1205 | 6891 | constraint (inst.cond != COND_ALWAYS, BAD_COND); |
2fc8bdac | 6892 | inst.instruction = 0xfa000000; |
267bf995 | 6893 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); |
b99bd4ef | 6894 | } |
c19d1205 ZW |
6895 | } |
6896 | ||
6897 | static void | |
6898 | do_bx (void) | |
6899 | { | |
845b51d6 PB |
6900 | bfd_boolean want_reloc; |
6901 | ||
c19d1205 ZW |
6902 | if (inst.operands[0].reg == REG_PC) |
6903 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 6904 | |
c19d1205 | 6905 | inst.instruction |= inst.operands[0].reg; |
845b51d6 PB |
6906 | /* Output R_ARM_V4BX relocations if is an EABI object that looks like |
6907 | it is for ARMv4t or earlier. */ | |
6908 | want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5); | |
6909 | if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5)) | |
6910 | want_reloc = TRUE; | |
6911 | ||
5ad34203 | 6912 | #ifdef OBJ_ELF |
845b51d6 | 6913 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
5ad34203 | 6914 | #endif |
584206db | 6915 | want_reloc = FALSE; |
845b51d6 PB |
6916 | |
6917 | if (want_reloc) | |
6918 | inst.reloc.type = BFD_RELOC_ARM_V4BX; | |
09d92015 MM |
6919 | } |
6920 | ||
c19d1205 ZW |
6921 | |
6922 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
6923 | |
6924 | static void | |
c19d1205 | 6925 | do_bxj (void) |
a737bd4d | 6926 | { |
c19d1205 ZW |
6927 | if (inst.operands[0].reg == REG_PC) |
6928 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
6929 | ||
6930 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
6931 | } |
6932 | ||
c19d1205 ZW |
6933 | /* Co-processor data operation: |
6934 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
6935 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
6936 | static void | |
6937 | do_cdp (void) | |
6938 | { | |
6939 | inst.instruction |= inst.operands[0].reg << 8; | |
6940 | inst.instruction |= inst.operands[1].imm << 20; | |
6941 | inst.instruction |= inst.operands[2].reg << 12; | |
6942 | inst.instruction |= inst.operands[3].reg << 16; | |
6943 | inst.instruction |= inst.operands[4].reg; | |
6944 | inst.instruction |= inst.operands[5].imm << 5; | |
6945 | } | |
a737bd4d NC |
6946 | |
6947 | static void | |
c19d1205 | 6948 | do_cmp (void) |
a737bd4d | 6949 | { |
c19d1205 ZW |
6950 | inst.instruction |= inst.operands[0].reg << 16; |
6951 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
6952 | } |
6953 | ||
c19d1205 ZW |
6954 | /* Transfer between coprocessor and ARM registers. |
6955 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
6956 | MRC2 | |
6957 | MCR{cond} | |
6958 | MCR2 | |
6959 | ||
6960 | No special properties. */ | |
09d92015 MM |
6961 | |
6962 | static void | |
c19d1205 | 6963 | do_co_reg (void) |
09d92015 | 6964 | { |
fdfde340 JM |
6965 | unsigned Rd; |
6966 | ||
6967 | Rd = inst.operands[2].reg; | |
6968 | if (thumb_mode) | |
6969 | { | |
6970 | if (inst.instruction == 0xee000010 | |
6971 | || inst.instruction == 0xfe000010) | |
6972 | /* MCR, MCR2 */ | |
6973 | reject_bad_reg (Rd); | |
6974 | else | |
6975 | /* MRC, MRC2 */ | |
6976 | constraint (Rd == REG_SP, BAD_SP); | |
6977 | } | |
6978 | else | |
6979 | { | |
6980 | /* MCR */ | |
6981 | if (inst.instruction == 0xe000010) | |
6982 | constraint (Rd == REG_PC, BAD_PC); | |
6983 | } | |
6984 | ||
6985 | ||
c19d1205 ZW |
6986 | inst.instruction |= inst.operands[0].reg << 8; |
6987 | inst.instruction |= inst.operands[1].imm << 21; | |
fdfde340 | 6988 | inst.instruction |= Rd << 12; |
c19d1205 ZW |
6989 | inst.instruction |= inst.operands[3].reg << 16; |
6990 | inst.instruction |= inst.operands[4].reg; | |
6991 | inst.instruction |= inst.operands[5].imm << 5; | |
6992 | } | |
09d92015 | 6993 | |
c19d1205 ZW |
6994 | /* Transfer between coprocessor register and pair of ARM registers. |
6995 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
6996 | MCRR2 | |
6997 | MRRC{cond} | |
6998 | MRRC2 | |
b99bd4ef | 6999 | |
c19d1205 | 7000 | Two XScale instructions are special cases of these: |
09d92015 | 7001 | |
c19d1205 ZW |
7002 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
7003 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 7004 | |
5f4273c7 | 7005 | Result unpredictable if Rd or Rn is R15. */ |
a737bd4d | 7006 | |
c19d1205 ZW |
7007 | static void |
7008 | do_co_reg2c (void) | |
7009 | { | |
fdfde340 JM |
7010 | unsigned Rd, Rn; |
7011 | ||
7012 | Rd = inst.operands[2].reg; | |
7013 | Rn = inst.operands[3].reg; | |
7014 | ||
7015 | if (thumb_mode) | |
7016 | { | |
7017 | reject_bad_reg (Rd); | |
7018 | reject_bad_reg (Rn); | |
7019 | } | |
7020 | else | |
7021 | { | |
7022 | constraint (Rd == REG_PC, BAD_PC); | |
7023 | constraint (Rn == REG_PC, BAD_PC); | |
7024 | } | |
7025 | ||
c19d1205 ZW |
7026 | inst.instruction |= inst.operands[0].reg << 8; |
7027 | inst.instruction |= inst.operands[1].imm << 4; | |
fdfde340 JM |
7028 | inst.instruction |= Rd << 12; |
7029 | inst.instruction |= Rn << 16; | |
c19d1205 | 7030 | inst.instruction |= inst.operands[4].reg; |
b99bd4ef NC |
7031 | } |
7032 | ||
c19d1205 ZW |
7033 | static void |
7034 | do_cpsi (void) | |
7035 | { | |
7036 | inst.instruction |= inst.operands[0].imm << 6; | |
a028a6f5 PB |
7037 | if (inst.operands[1].present) |
7038 | { | |
7039 | inst.instruction |= CPSI_MMOD; | |
7040 | inst.instruction |= inst.operands[1].imm; | |
7041 | } | |
c19d1205 | 7042 | } |
b99bd4ef | 7043 | |
62b3e311 PB |
7044 | static void |
7045 | do_dbg (void) | |
7046 | { | |
7047 | inst.instruction |= inst.operands[0].imm; | |
7048 | } | |
7049 | ||
b99bd4ef | 7050 | static void |
c19d1205 | 7051 | do_it (void) |
b99bd4ef | 7052 | { |
c19d1205 | 7053 | /* There is no IT instruction in ARM mode. We |
e07e6e58 NC |
7054 | process it to do the validation as if in |
7055 | thumb mode, just in case the code gets | |
7056 | assembled for thumb using the unified syntax. */ | |
7057 | ||
c19d1205 | 7058 | inst.size = 0; |
e07e6e58 NC |
7059 | if (unified_syntax) |
7060 | { | |
7061 | set_it_insn_type (IT_INSN); | |
7062 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
7063 | now_it.cc = inst.operands[0].imm; | |
7064 | } | |
09d92015 | 7065 | } |
b99bd4ef | 7066 | |
09d92015 | 7067 | static void |
c19d1205 | 7068 | do_ldmstm (void) |
ea6ef066 | 7069 | { |
c19d1205 ZW |
7070 | int base_reg = inst.operands[0].reg; |
7071 | int range = inst.operands[1].imm; | |
ea6ef066 | 7072 | |
c19d1205 ZW |
7073 | inst.instruction |= base_reg << 16; |
7074 | inst.instruction |= range; | |
ea6ef066 | 7075 | |
c19d1205 ZW |
7076 | if (inst.operands[1].writeback) |
7077 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 7078 | |
c19d1205 | 7079 | if (inst.operands[0].writeback) |
ea6ef066 | 7080 | { |
c19d1205 ZW |
7081 | inst.instruction |= WRITE_BACK; |
7082 | /* Check for unpredictable uses of writeback. */ | |
7083 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 7084 | { |
c19d1205 ZW |
7085 | /* Not allowed in LDM type 2. */ |
7086 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
7087 | && ((range & (1 << REG_PC)) == 0)) | |
7088 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
7089 | /* Only allowed if base reg not in list for other types. */ | |
7090 | else if (range & (1 << base_reg)) | |
7091 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
7092 | } | |
7093 | else /* STM. */ | |
7094 | { | |
7095 | /* Not allowed for type 2. */ | |
7096 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
7097 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
7098 | /* Only allowed if base reg not in list, or first in list. */ | |
7099 | else if ((range & (1 << base_reg)) | |
7100 | && (range & ((1 << base_reg) - 1))) | |
7101 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 7102 | } |
ea6ef066 | 7103 | } |
a737bd4d NC |
7104 | } |
7105 | ||
c19d1205 ZW |
7106 | /* ARMv5TE load-consecutive (argument parse) |
7107 | Mode is like LDRH. | |
7108 | ||
7109 | LDRccD R, mode | |
7110 | STRccD R, mode. */ | |
7111 | ||
a737bd4d | 7112 | static void |
c19d1205 | 7113 | do_ldrd (void) |
a737bd4d | 7114 | { |
c19d1205 ZW |
7115 | constraint (inst.operands[0].reg % 2 != 0, |
7116 | _("first destination register must be even")); | |
7117 | constraint (inst.operands[1].present | |
7118 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
7119 | _("can only load two consecutive registers")); | |
7120 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
7121 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 7122 | |
c19d1205 ZW |
7123 | if (!inst.operands[1].present) |
7124 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
5f4273c7 | 7125 | |
c19d1205 | 7126 | if (inst.instruction & LOAD_BIT) |
a737bd4d | 7127 | { |
c19d1205 ZW |
7128 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
7129 | register and the first register written; we have to diagnose | |
7130 | overlap between the base and the second register written here. */ | |
ea6ef066 | 7131 | |
c19d1205 ZW |
7132 | if (inst.operands[2].reg == inst.operands[1].reg |
7133 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
7134 | as_warn (_("base register written back, and overlaps " | |
7135 | "second destination register")); | |
b05fe5cf | 7136 | |
c19d1205 ZW |
7137 | /* For an index-register load, the index register must not overlap the |
7138 | destination (even if not write-back). */ | |
7139 | else if (inst.operands[2].immisreg | |
ca3f61f7 NC |
7140 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg |
7141 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
c19d1205 | 7142 | as_warn (_("index register overlaps destination register")); |
b05fe5cf | 7143 | } |
c19d1205 ZW |
7144 | |
7145 | inst.instruction |= inst.operands[0].reg << 12; | |
7146 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
7147 | } |
7148 | ||
7149 | static void | |
c19d1205 | 7150 | do_ldrex (void) |
b05fe5cf | 7151 | { |
c19d1205 ZW |
7152 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
7153 | || inst.operands[1].postind || inst.operands[1].writeback | |
7154 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
01cfc07f NC |
7155 | || inst.operands[1].negative |
7156 | /* This can arise if the programmer has written | |
7157 | strex rN, rM, foo | |
7158 | or if they have mistakenly used a register name as the last | |
7159 | operand, eg: | |
7160 | strex rN, rM, rX | |
7161 | It is very difficult to distinguish between these two cases | |
7162 | because "rX" might actually be a label. ie the register | |
7163 | name has been occluded by a symbol of the same name. So we | |
7164 | just generate a general 'bad addressing mode' type error | |
7165 | message and leave it up to the programmer to discover the | |
7166 | true cause and fix their mistake. */ | |
7167 | || (inst.operands[1].reg == REG_PC), | |
7168 | BAD_ADDR_MODE); | |
b05fe5cf | 7169 | |
c19d1205 ZW |
7170 | constraint (inst.reloc.exp.X_op != O_constant |
7171 | || inst.reloc.exp.X_add_number != 0, | |
7172 | _("offset must be zero in ARM encoding")); | |
b05fe5cf | 7173 | |
c19d1205 ZW |
7174 | inst.instruction |= inst.operands[0].reg << 12; |
7175 | inst.instruction |= inst.operands[1].reg << 16; | |
7176 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b05fe5cf ZW |
7177 | } |
7178 | ||
7179 | static void | |
c19d1205 | 7180 | do_ldrexd (void) |
b05fe5cf | 7181 | { |
c19d1205 ZW |
7182 | constraint (inst.operands[0].reg % 2 != 0, |
7183 | _("even register required")); | |
7184 | constraint (inst.operands[1].present | |
7185 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
7186 | _("can only load two consecutive registers")); | |
7187 | /* If op 1 were present and equal to PC, this function wouldn't | |
7188 | have been called in the first place. */ | |
7189 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 7190 | |
c19d1205 ZW |
7191 | inst.instruction |= inst.operands[0].reg << 12; |
7192 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
7193 | } |
7194 | ||
7195 | static void | |
c19d1205 | 7196 | do_ldst (void) |
b05fe5cf | 7197 | { |
c19d1205 ZW |
7198 | inst.instruction |= inst.operands[0].reg << 12; |
7199 | if (!inst.operands[1].isreg) | |
7200 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) | |
b05fe5cf | 7201 | return; |
c19d1205 | 7202 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
7203 | } |
7204 | ||
7205 | static void | |
c19d1205 | 7206 | do_ldstt (void) |
b05fe5cf | 7207 | { |
c19d1205 ZW |
7208 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
7209 | reject [Rn,...]. */ | |
7210 | if (inst.operands[1].preind) | |
b05fe5cf | 7211 | { |
bd3ba5d1 NC |
7212 | constraint (inst.reloc.exp.X_op != O_constant |
7213 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 7214 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 7215 | |
c19d1205 ZW |
7216 | inst.operands[1].preind = 0; |
7217 | inst.operands[1].postind = 1; | |
7218 | inst.operands[1].writeback = 1; | |
b05fe5cf | 7219 | } |
c19d1205 ZW |
7220 | inst.instruction |= inst.operands[0].reg << 12; |
7221 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
7222 | } | |
b05fe5cf | 7223 | |
c19d1205 | 7224 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 7225 | |
c19d1205 ZW |
7226 | static void |
7227 | do_ldstv4 (void) | |
7228 | { | |
7229 | inst.instruction |= inst.operands[0].reg << 12; | |
7230 | if (!inst.operands[1].isreg) | |
7231 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) | |
b05fe5cf | 7232 | return; |
c19d1205 | 7233 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
7234 | } |
7235 | ||
7236 | static void | |
c19d1205 | 7237 | do_ldsttv4 (void) |
b05fe5cf | 7238 | { |
c19d1205 ZW |
7239 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
7240 | reject [Rn,...]. */ | |
7241 | if (inst.operands[1].preind) | |
b05fe5cf | 7242 | { |
bd3ba5d1 NC |
7243 | constraint (inst.reloc.exp.X_op != O_constant |
7244 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 7245 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 7246 | |
c19d1205 ZW |
7247 | inst.operands[1].preind = 0; |
7248 | inst.operands[1].postind = 1; | |
7249 | inst.operands[1].writeback = 1; | |
b05fe5cf | 7250 | } |
c19d1205 ZW |
7251 | inst.instruction |= inst.operands[0].reg << 12; |
7252 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
7253 | } | |
b05fe5cf | 7254 | |
c19d1205 ZW |
7255 | /* Co-processor register load/store. |
7256 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
7257 | static void | |
7258 | do_lstc (void) | |
7259 | { | |
7260 | inst.instruction |= inst.operands[0].reg << 8; | |
7261 | inst.instruction |= inst.operands[1].reg << 12; | |
7262 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
7263 | } |
7264 | ||
b05fe5cf | 7265 | static void |
c19d1205 | 7266 | do_mlas (void) |
b05fe5cf | 7267 | { |
8fb9d7b9 | 7268 | /* This restriction does not apply to mls (nor to mla in v6 or later). */ |
c19d1205 | 7269 | if (inst.operands[0].reg == inst.operands[1].reg |
8fb9d7b9 | 7270 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) |
c19d1205 | 7271 | && !(inst.instruction & 0x00400000)) |
8fb9d7b9 | 7272 | as_tsktsk (_("Rd and Rm should be different in mla")); |
b05fe5cf | 7273 | |
c19d1205 ZW |
7274 | inst.instruction |= inst.operands[0].reg << 16; |
7275 | inst.instruction |= inst.operands[1].reg; | |
7276 | inst.instruction |= inst.operands[2].reg << 8; | |
7277 | inst.instruction |= inst.operands[3].reg << 12; | |
c19d1205 | 7278 | } |
b05fe5cf | 7279 | |
c19d1205 ZW |
7280 | static void |
7281 | do_mov (void) | |
7282 | { | |
7283 | inst.instruction |= inst.operands[0].reg << 12; | |
7284 | encode_arm_shifter_operand (1); | |
7285 | } | |
b05fe5cf | 7286 | |
c19d1205 ZW |
7287 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
7288 | static void | |
7289 | do_mov16 (void) | |
7290 | { | |
b6895b4f PB |
7291 | bfd_vma imm; |
7292 | bfd_boolean top; | |
7293 | ||
7294 | top = (inst.instruction & 0x00400000) != 0; | |
7295 | constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, | |
7296 | _(":lower16: not allowed this instruction")); | |
7297 | constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, | |
7298 | _(":upper16: not allowed instruction")); | |
c19d1205 | 7299 | inst.instruction |= inst.operands[0].reg << 12; |
b6895b4f PB |
7300 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
7301 | { | |
7302 | imm = inst.reloc.exp.X_add_number; | |
7303 | /* The value is in two pieces: 0:11, 16:19. */ | |
7304 | inst.instruction |= (imm & 0x00000fff); | |
7305 | inst.instruction |= (imm & 0x0000f000) << 4; | |
7306 | } | |
b05fe5cf | 7307 | } |
b99bd4ef | 7308 | |
037e8744 JB |
7309 | static void do_vfp_nsyn_opcode (const char *); |
7310 | ||
7311 | static int | |
7312 | do_vfp_nsyn_mrs (void) | |
7313 | { | |
7314 | if (inst.operands[0].isvec) | |
7315 | { | |
7316 | if (inst.operands[1].reg != 1) | |
7317 | first_error (_("operand 1 must be FPSCR")); | |
7318 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
7319 | memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); | |
7320 | do_vfp_nsyn_opcode ("fmstat"); | |
7321 | } | |
7322 | else if (inst.operands[1].isvec) | |
7323 | do_vfp_nsyn_opcode ("fmrx"); | |
7324 | else | |
7325 | return FAIL; | |
5f4273c7 | 7326 | |
037e8744 JB |
7327 | return SUCCESS; |
7328 | } | |
7329 | ||
7330 | static int | |
7331 | do_vfp_nsyn_msr (void) | |
7332 | { | |
7333 | if (inst.operands[0].isvec) | |
7334 | do_vfp_nsyn_opcode ("fmxr"); | |
7335 | else | |
7336 | return FAIL; | |
7337 | ||
7338 | return SUCCESS; | |
7339 | } | |
7340 | ||
b99bd4ef | 7341 | static void |
c19d1205 | 7342 | do_mrs (void) |
b99bd4ef | 7343 | { |
037e8744 JB |
7344 | if (do_vfp_nsyn_mrs () == SUCCESS) |
7345 | return; | |
7346 | ||
c19d1205 ZW |
7347 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ |
7348 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
7349 | != (PSR_c|PSR_f), | |
7350 | _("'CPSR' or 'SPSR' expected")); | |
7351 | inst.instruction |= inst.operands[0].reg << 12; | |
7352 | inst.instruction |= (inst.operands[1].imm & SPSR_BIT); | |
7353 | } | |
b99bd4ef | 7354 | |
c19d1205 ZW |
7355 | /* Two possible forms: |
7356 | "{C|S}PSR_<field>, Rm", | |
7357 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 7358 | |
c19d1205 ZW |
7359 | static void |
7360 | do_msr (void) | |
7361 | { | |
037e8744 JB |
7362 | if (do_vfp_nsyn_msr () == SUCCESS) |
7363 | return; | |
7364 | ||
c19d1205 ZW |
7365 | inst.instruction |= inst.operands[0].imm; |
7366 | if (inst.operands[1].isreg) | |
7367 | inst.instruction |= inst.operands[1].reg; | |
7368 | else | |
b99bd4ef | 7369 | { |
c19d1205 ZW |
7370 | inst.instruction |= INST_IMMEDIATE; |
7371 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
7372 | inst.reloc.pc_rel = 0; | |
b99bd4ef | 7373 | } |
b99bd4ef NC |
7374 | } |
7375 | ||
c19d1205 ZW |
7376 | static void |
7377 | do_mul (void) | |
a737bd4d | 7378 | { |
c19d1205 ZW |
7379 | if (!inst.operands[2].present) |
7380 | inst.operands[2].reg = inst.operands[0].reg; | |
7381 | inst.instruction |= inst.operands[0].reg << 16; | |
7382 | inst.instruction |= inst.operands[1].reg; | |
7383 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 7384 | |
8fb9d7b9 MS |
7385 | if (inst.operands[0].reg == inst.operands[1].reg |
7386 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
7387 | as_tsktsk (_("Rd and Rm should be different in mul")); | |
a737bd4d NC |
7388 | } |
7389 | ||
c19d1205 ZW |
7390 | /* Long Multiply Parser |
7391 | UMULL RdLo, RdHi, Rm, Rs | |
7392 | SMULL RdLo, RdHi, Rm, Rs | |
7393 | UMLAL RdLo, RdHi, Rm, Rs | |
7394 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
7395 | |
7396 | static void | |
c19d1205 | 7397 | do_mull (void) |
b99bd4ef | 7398 | { |
c19d1205 ZW |
7399 | inst.instruction |= inst.operands[0].reg << 12; |
7400 | inst.instruction |= inst.operands[1].reg << 16; | |
7401 | inst.instruction |= inst.operands[2].reg; | |
7402 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 7403 | |
682b27ad PB |
7404 | /* rdhi and rdlo must be different. */ |
7405 | if (inst.operands[0].reg == inst.operands[1].reg) | |
7406 | as_tsktsk (_("rdhi and rdlo must be different")); | |
7407 | ||
7408 | /* rdhi, rdlo and rm must all be different before armv6. */ | |
7409 | if ((inst.operands[0].reg == inst.operands[2].reg | |
c19d1205 | 7410 | || inst.operands[1].reg == inst.operands[2].reg) |
682b27ad | 7411 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) |
c19d1205 ZW |
7412 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); |
7413 | } | |
b99bd4ef | 7414 | |
c19d1205 ZW |
7415 | static void |
7416 | do_nop (void) | |
7417 | { | |
e7495e45 NS |
7418 | if (inst.operands[0].present |
7419 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k)) | |
c19d1205 ZW |
7420 | { |
7421 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
7422 | inst.instruction &= 0xf0000000; | |
e7495e45 NS |
7423 | inst.instruction |= 0x0320f000; |
7424 | if (inst.operands[0].present) | |
7425 | inst.instruction |= inst.operands[0].imm; | |
c19d1205 | 7426 | } |
b99bd4ef NC |
7427 | } |
7428 | ||
c19d1205 ZW |
7429 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
7430 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
7431 | Condition defaults to COND_ALWAYS. | |
7432 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
7433 | |
7434 | static void | |
c19d1205 | 7435 | do_pkhbt (void) |
b99bd4ef | 7436 | { |
c19d1205 ZW |
7437 | inst.instruction |= inst.operands[0].reg << 12; |
7438 | inst.instruction |= inst.operands[1].reg << 16; | |
7439 | inst.instruction |= inst.operands[2].reg; | |
7440 | if (inst.operands[3].present) | |
7441 | encode_arm_shift (3); | |
7442 | } | |
b99bd4ef | 7443 | |
c19d1205 | 7444 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 7445 | |
c19d1205 ZW |
7446 | static void |
7447 | do_pkhtb (void) | |
7448 | { | |
7449 | if (!inst.operands[3].present) | |
b99bd4ef | 7450 | { |
c19d1205 ZW |
7451 | /* If the shift specifier is omitted, turn the instruction |
7452 | into pkhbt rd, rm, rn. */ | |
7453 | inst.instruction &= 0xfff00010; | |
7454 | inst.instruction |= inst.operands[0].reg << 12; | |
7455 | inst.instruction |= inst.operands[1].reg; | |
7456 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
7457 | } |
7458 | else | |
7459 | { | |
c19d1205 ZW |
7460 | inst.instruction |= inst.operands[0].reg << 12; |
7461 | inst.instruction |= inst.operands[1].reg << 16; | |
7462 | inst.instruction |= inst.operands[2].reg; | |
7463 | encode_arm_shift (3); | |
b99bd4ef NC |
7464 | } |
7465 | } | |
7466 | ||
c19d1205 ZW |
7467 | /* ARMv5TE: Preload-Cache |
7468 | ||
7469 | PLD <addr_mode> | |
7470 | ||
7471 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
7472 | |
7473 | static void | |
c19d1205 | 7474 | do_pld (void) |
b99bd4ef | 7475 | { |
c19d1205 ZW |
7476 | constraint (!inst.operands[0].isreg, |
7477 | _("'[' expected after PLD mnemonic")); | |
7478 | constraint (inst.operands[0].postind, | |
7479 | _("post-indexed expression used in preload instruction")); | |
7480 | constraint (inst.operands[0].writeback, | |
7481 | _("writeback used in preload instruction")); | |
7482 | constraint (!inst.operands[0].preind, | |
7483 | _("unindexed addressing used in preload instruction")); | |
c19d1205 ZW |
7484 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
7485 | } | |
b99bd4ef | 7486 | |
62b3e311 PB |
7487 | /* ARMv7: PLI <addr_mode> */ |
7488 | static void | |
7489 | do_pli (void) | |
7490 | { | |
7491 | constraint (!inst.operands[0].isreg, | |
7492 | _("'[' expected after PLI mnemonic")); | |
7493 | constraint (inst.operands[0].postind, | |
7494 | _("post-indexed expression used in preload instruction")); | |
7495 | constraint (inst.operands[0].writeback, | |
7496 | _("writeback used in preload instruction")); | |
7497 | constraint (!inst.operands[0].preind, | |
7498 | _("unindexed addressing used in preload instruction")); | |
7499 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
7500 | inst.instruction &= ~PRE_INDEX; | |
7501 | } | |
7502 | ||
c19d1205 ZW |
7503 | static void |
7504 | do_push_pop (void) | |
7505 | { | |
7506 | inst.operands[1] = inst.operands[0]; | |
7507 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
7508 | inst.operands[0].isreg = 1; | |
7509 | inst.operands[0].writeback = 1; | |
7510 | inst.operands[0].reg = REG_SP; | |
7511 | do_ldmstm (); | |
7512 | } | |
b99bd4ef | 7513 | |
c19d1205 ZW |
7514 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
7515 | word at the specified address and the following word | |
7516 | respectively. | |
7517 | Unconditionally executed. | |
7518 | Error if Rn is R15. */ | |
b99bd4ef | 7519 | |
c19d1205 ZW |
7520 | static void |
7521 | do_rfe (void) | |
7522 | { | |
7523 | inst.instruction |= inst.operands[0].reg << 16; | |
7524 | if (inst.operands[0].writeback) | |
7525 | inst.instruction |= WRITE_BACK; | |
7526 | } | |
b99bd4ef | 7527 | |
c19d1205 | 7528 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 7529 | |
c19d1205 ZW |
7530 | static void |
7531 | do_ssat (void) | |
7532 | { | |
7533 | inst.instruction |= inst.operands[0].reg << 12; | |
7534 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
7535 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 7536 | |
c19d1205 ZW |
7537 | if (inst.operands[3].present) |
7538 | encode_arm_shift (3); | |
b99bd4ef NC |
7539 | } |
7540 | ||
c19d1205 | 7541 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
7542 | |
7543 | static void | |
c19d1205 | 7544 | do_usat (void) |
b99bd4ef | 7545 | { |
c19d1205 ZW |
7546 | inst.instruction |= inst.operands[0].reg << 12; |
7547 | inst.instruction |= inst.operands[1].imm << 16; | |
7548 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 7549 | |
c19d1205 ZW |
7550 | if (inst.operands[3].present) |
7551 | encode_arm_shift (3); | |
b99bd4ef NC |
7552 | } |
7553 | ||
c19d1205 | 7554 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
7555 | |
7556 | static void | |
c19d1205 | 7557 | do_ssat16 (void) |
09d92015 | 7558 | { |
c19d1205 ZW |
7559 | inst.instruction |= inst.operands[0].reg << 12; |
7560 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
7561 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
7562 | } |
7563 | ||
c19d1205 ZW |
7564 | static void |
7565 | do_usat16 (void) | |
a737bd4d | 7566 | { |
c19d1205 ZW |
7567 | inst.instruction |= inst.operands[0].reg << 12; |
7568 | inst.instruction |= inst.operands[1].imm << 16; | |
7569 | inst.instruction |= inst.operands[2].reg; | |
7570 | } | |
a737bd4d | 7571 | |
c19d1205 ZW |
7572 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
7573 | preserving the other bits. | |
a737bd4d | 7574 | |
c19d1205 ZW |
7575 | setend <endian_specifier>, where <endian_specifier> is either |
7576 | BE or LE. */ | |
a737bd4d | 7577 | |
c19d1205 ZW |
7578 | static void |
7579 | do_setend (void) | |
7580 | { | |
7581 | if (inst.operands[0].imm) | |
7582 | inst.instruction |= 0x200; | |
a737bd4d NC |
7583 | } |
7584 | ||
7585 | static void | |
c19d1205 | 7586 | do_shift (void) |
a737bd4d | 7587 | { |
c19d1205 ZW |
7588 | unsigned int Rm = (inst.operands[1].present |
7589 | ? inst.operands[1].reg | |
7590 | : inst.operands[0].reg); | |
a737bd4d | 7591 | |
c19d1205 ZW |
7592 | inst.instruction |= inst.operands[0].reg << 12; |
7593 | inst.instruction |= Rm; | |
7594 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 7595 | { |
c19d1205 ZW |
7596 | inst.instruction |= inst.operands[2].reg << 8; |
7597 | inst.instruction |= SHIFT_BY_REG; | |
a737bd4d NC |
7598 | } |
7599 | else | |
c19d1205 | 7600 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
7601 | } |
7602 | ||
09d92015 | 7603 | static void |
3eb17e6b | 7604 | do_smc (void) |
09d92015 | 7605 | { |
3eb17e6b | 7606 | inst.reloc.type = BFD_RELOC_ARM_SMC; |
c19d1205 | 7607 | inst.reloc.pc_rel = 0; |
09d92015 MM |
7608 | } |
7609 | ||
09d92015 | 7610 | static void |
c19d1205 | 7611 | do_swi (void) |
09d92015 | 7612 | { |
c19d1205 ZW |
7613 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
7614 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
7615 | } |
7616 | ||
c19d1205 ZW |
7617 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
7618 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
7619 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
7620 | Error if any register is R15. */ | |
e16bb312 | 7621 | |
c19d1205 ZW |
7622 | static void |
7623 | do_smla (void) | |
e16bb312 | 7624 | { |
c19d1205 ZW |
7625 | inst.instruction |= inst.operands[0].reg << 16; |
7626 | inst.instruction |= inst.operands[1].reg; | |
7627 | inst.instruction |= inst.operands[2].reg << 8; | |
7628 | inst.instruction |= inst.operands[3].reg << 12; | |
7629 | } | |
a737bd4d | 7630 | |
c19d1205 ZW |
7631 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
7632 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
7633 | Error if any register is R15. | |
7634 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 7635 | |
c19d1205 ZW |
7636 | static void |
7637 | do_smlal (void) | |
7638 | { | |
7639 | inst.instruction |= inst.operands[0].reg << 12; | |
7640 | inst.instruction |= inst.operands[1].reg << 16; | |
7641 | inst.instruction |= inst.operands[2].reg; | |
7642 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 7643 | |
c19d1205 ZW |
7644 | if (inst.operands[0].reg == inst.operands[1].reg) |
7645 | as_tsktsk (_("rdhi and rdlo must be different")); | |
7646 | } | |
a737bd4d | 7647 | |
c19d1205 ZW |
7648 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
7649 | SMULxy{cond} Rd,Rm,Rs | |
7650 | Error if any register is R15. */ | |
a737bd4d | 7651 | |
c19d1205 ZW |
7652 | static void |
7653 | do_smul (void) | |
7654 | { | |
7655 | inst.instruction |= inst.operands[0].reg << 16; | |
7656 | inst.instruction |= inst.operands[1].reg; | |
7657 | inst.instruction |= inst.operands[2].reg << 8; | |
7658 | } | |
a737bd4d | 7659 | |
b6702015 PB |
7660 | /* ARM V6 srs (argument parse). The variable fields in the encoding are |
7661 | the same for both ARM and Thumb-2. */ | |
a737bd4d | 7662 | |
c19d1205 ZW |
7663 | static void |
7664 | do_srs (void) | |
7665 | { | |
b6702015 PB |
7666 | int reg; |
7667 | ||
7668 | if (inst.operands[0].present) | |
7669 | { | |
7670 | reg = inst.operands[0].reg; | |
fdfde340 | 7671 | constraint (reg != REG_SP, _("SRS base register must be r13")); |
b6702015 PB |
7672 | } |
7673 | else | |
fdfde340 | 7674 | reg = REG_SP; |
b6702015 PB |
7675 | |
7676 | inst.instruction |= reg << 16; | |
7677 | inst.instruction |= inst.operands[1].imm; | |
7678 | if (inst.operands[0].writeback || inst.operands[1].writeback) | |
c19d1205 ZW |
7679 | inst.instruction |= WRITE_BACK; |
7680 | } | |
a737bd4d | 7681 | |
c19d1205 | 7682 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 7683 | |
c19d1205 ZW |
7684 | static void |
7685 | do_strex (void) | |
7686 | { | |
7687 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
7688 | || inst.operands[2].postind || inst.operands[2].writeback | |
7689 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
01cfc07f NC |
7690 | || inst.operands[2].negative |
7691 | /* See comment in do_ldrex(). */ | |
7692 | || (inst.operands[2].reg == REG_PC), | |
7693 | BAD_ADDR_MODE); | |
a737bd4d | 7694 | |
c19d1205 ZW |
7695 | constraint (inst.operands[0].reg == inst.operands[1].reg |
7696 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 7697 | |
c19d1205 ZW |
7698 | constraint (inst.reloc.exp.X_op != O_constant |
7699 | || inst.reloc.exp.X_add_number != 0, | |
7700 | _("offset must be zero in ARM encoding")); | |
a737bd4d | 7701 | |
c19d1205 ZW |
7702 | inst.instruction |= inst.operands[0].reg << 12; |
7703 | inst.instruction |= inst.operands[1].reg; | |
7704 | inst.instruction |= inst.operands[2].reg << 16; | |
7705 | inst.reloc.type = BFD_RELOC_UNUSED; | |
e16bb312 NC |
7706 | } |
7707 | ||
7708 | static void | |
c19d1205 | 7709 | do_strexd (void) |
e16bb312 | 7710 | { |
c19d1205 ZW |
7711 | constraint (inst.operands[1].reg % 2 != 0, |
7712 | _("even register required")); | |
7713 | constraint (inst.operands[2].present | |
7714 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
7715 | _("can only store two consecutive registers")); | |
7716 | /* If op 2 were present and equal to PC, this function wouldn't | |
7717 | have been called in the first place. */ | |
7718 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 7719 | |
c19d1205 ZW |
7720 | constraint (inst.operands[0].reg == inst.operands[1].reg |
7721 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
7722 | || inst.operands[0].reg == inst.operands[3].reg, | |
7723 | BAD_OVERLAP); | |
e16bb312 | 7724 | |
c19d1205 ZW |
7725 | inst.instruction |= inst.operands[0].reg << 12; |
7726 | inst.instruction |= inst.operands[1].reg; | |
7727 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
7728 | } |
7729 | ||
c19d1205 ZW |
7730 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
7731 | extends it to 32-bits, and adds the result to a value in another | |
7732 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
7733 | before extracting the 16-bit value. | |
7734 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
7735 | Condition defaults to COND_ALWAYS. | |
7736 | Error if any register uses R15. */ | |
7737 | ||
e16bb312 | 7738 | static void |
c19d1205 | 7739 | do_sxtah (void) |
e16bb312 | 7740 | { |
c19d1205 ZW |
7741 | inst.instruction |= inst.operands[0].reg << 12; |
7742 | inst.instruction |= inst.operands[1].reg << 16; | |
7743 | inst.instruction |= inst.operands[2].reg; | |
7744 | inst.instruction |= inst.operands[3].imm << 10; | |
7745 | } | |
e16bb312 | 7746 | |
c19d1205 | 7747 | /* ARM V6 SXTH. |
e16bb312 | 7748 | |
c19d1205 ZW |
7749 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
7750 | Condition defaults to COND_ALWAYS. | |
7751 | Error if any register uses R15. */ | |
e16bb312 NC |
7752 | |
7753 | static void | |
c19d1205 | 7754 | do_sxth (void) |
e16bb312 | 7755 | { |
c19d1205 ZW |
7756 | inst.instruction |= inst.operands[0].reg << 12; |
7757 | inst.instruction |= inst.operands[1].reg; | |
7758 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 7759 | } |
c19d1205 ZW |
7760 | \f |
7761 | /* VFP instructions. In a logical order: SP variant first, monad | |
7762 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
7763 | |
7764 | static void | |
c19d1205 | 7765 | do_vfp_sp_monadic (void) |
e16bb312 | 7766 | { |
5287ad62 JB |
7767 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
7768 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
7769 | } |
7770 | ||
7771 | static void | |
c19d1205 | 7772 | do_vfp_sp_dyadic (void) |
e16bb312 | 7773 | { |
5287ad62 JB |
7774 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
7775 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
7776 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
7777 | } |
7778 | ||
7779 | static void | |
c19d1205 | 7780 | do_vfp_sp_compare_z (void) |
e16bb312 | 7781 | { |
5287ad62 | 7782 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
7783 | } |
7784 | ||
7785 | static void | |
c19d1205 | 7786 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 7787 | { |
5287ad62 JB |
7788 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
7789 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
7790 | } |
7791 | ||
7792 | static void | |
c19d1205 | 7793 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 7794 | { |
5287ad62 JB |
7795 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
7796 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
e16bb312 NC |
7797 | } |
7798 | ||
7799 | static void | |
c19d1205 | 7800 | do_vfp_reg_from_sp (void) |
e16bb312 | 7801 | { |
c19d1205 | 7802 | inst.instruction |= inst.operands[0].reg << 12; |
5287ad62 | 7803 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); |
e16bb312 NC |
7804 | } |
7805 | ||
7806 | static void | |
c19d1205 | 7807 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 7808 | { |
c19d1205 ZW |
7809 | constraint (inst.operands[2].imm != 2, |
7810 | _("only two consecutive VFP SP registers allowed here")); | |
7811 | inst.instruction |= inst.operands[0].reg << 12; | |
7812 | inst.instruction |= inst.operands[1].reg << 16; | |
5287ad62 | 7813 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); |
e16bb312 NC |
7814 | } |
7815 | ||
7816 | static void | |
c19d1205 | 7817 | do_vfp_sp_from_reg (void) |
e16bb312 | 7818 | { |
5287ad62 | 7819 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); |
c19d1205 | 7820 | inst.instruction |= inst.operands[1].reg << 12; |
e16bb312 NC |
7821 | } |
7822 | ||
7823 | static void | |
c19d1205 | 7824 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 7825 | { |
c19d1205 ZW |
7826 | constraint (inst.operands[0].imm != 2, |
7827 | _("only two consecutive VFP SP registers allowed here")); | |
5287ad62 | 7828 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); |
c19d1205 ZW |
7829 | inst.instruction |= inst.operands[1].reg << 12; |
7830 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
7831 | } |
7832 | ||
7833 | static void | |
c19d1205 | 7834 | do_vfp_sp_ldst (void) |
e16bb312 | 7835 | { |
5287ad62 | 7836 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
c19d1205 | 7837 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
7838 | } |
7839 | ||
7840 | static void | |
c19d1205 | 7841 | do_vfp_dp_ldst (void) |
e16bb312 | 7842 | { |
5287ad62 | 7843 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
c19d1205 | 7844 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
7845 | } |
7846 | ||
c19d1205 | 7847 | |
e16bb312 | 7848 | static void |
c19d1205 | 7849 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 7850 | { |
c19d1205 ZW |
7851 | if (inst.operands[0].writeback) |
7852 | inst.instruction |= WRITE_BACK; | |
7853 | else | |
7854 | constraint (ldstm_type != VFP_LDSTMIA, | |
7855 | _("this addressing mode requires base-register writeback")); | |
7856 | inst.instruction |= inst.operands[0].reg << 16; | |
5287ad62 | 7857 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); |
c19d1205 | 7858 | inst.instruction |= inst.operands[1].imm; |
e16bb312 NC |
7859 | } |
7860 | ||
7861 | static void | |
c19d1205 | 7862 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 7863 | { |
c19d1205 | 7864 | int count; |
e16bb312 | 7865 | |
c19d1205 ZW |
7866 | if (inst.operands[0].writeback) |
7867 | inst.instruction |= WRITE_BACK; | |
7868 | else | |
7869 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
7870 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 7871 | |
c19d1205 | 7872 | inst.instruction |= inst.operands[0].reg << 16; |
5287ad62 | 7873 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
e16bb312 | 7874 | |
c19d1205 ZW |
7875 | count = inst.operands[1].imm << 1; |
7876 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
7877 | count += 1; | |
e16bb312 | 7878 | |
c19d1205 | 7879 | inst.instruction |= count; |
e16bb312 NC |
7880 | } |
7881 | ||
7882 | static void | |
c19d1205 | 7883 | do_vfp_sp_ldstmia (void) |
e16bb312 | 7884 | { |
c19d1205 | 7885 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
7886 | } |
7887 | ||
7888 | static void | |
c19d1205 | 7889 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 7890 | { |
c19d1205 | 7891 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
7892 | } |
7893 | ||
7894 | static void | |
c19d1205 | 7895 | do_vfp_dp_ldstmia (void) |
e16bb312 | 7896 | { |
c19d1205 | 7897 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
7898 | } |
7899 | ||
7900 | static void | |
c19d1205 | 7901 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 7902 | { |
c19d1205 | 7903 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
7904 | } |
7905 | ||
7906 | static void | |
c19d1205 | 7907 | do_vfp_xp_ldstmia (void) |
e16bb312 | 7908 | { |
c19d1205 ZW |
7909 | vfp_dp_ldstm (VFP_LDSTMIAX); |
7910 | } | |
e16bb312 | 7911 | |
c19d1205 ZW |
7912 | static void |
7913 | do_vfp_xp_ldstmdb (void) | |
7914 | { | |
7915 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 7916 | } |
5287ad62 JB |
7917 | |
7918 | static void | |
7919 | do_vfp_dp_rd_rm (void) | |
7920 | { | |
7921 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
7922 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
7923 | } | |
7924 | ||
7925 | static void | |
7926 | do_vfp_dp_rn_rd (void) | |
7927 | { | |
7928 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); | |
7929 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
7930 | } | |
7931 | ||
7932 | static void | |
7933 | do_vfp_dp_rd_rn (void) | |
7934 | { | |
7935 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
7936 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
7937 | } | |
7938 | ||
7939 | static void | |
7940 | do_vfp_dp_rd_rn_rm (void) | |
7941 | { | |
7942 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
7943 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
7944 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); | |
7945 | } | |
7946 | ||
7947 | static void | |
7948 | do_vfp_dp_rd (void) | |
7949 | { | |
7950 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
7951 | } | |
7952 | ||
7953 | static void | |
7954 | do_vfp_dp_rm_rd_rn (void) | |
7955 | { | |
7956 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); | |
7957 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
7958 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); | |
7959 | } | |
7960 | ||
7961 | /* VFPv3 instructions. */ | |
7962 | static void | |
7963 | do_vfp_sp_const (void) | |
7964 | { | |
7965 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
00249aaa PB |
7966 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
7967 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
7968 | } |
7969 | ||
7970 | static void | |
7971 | do_vfp_dp_const (void) | |
7972 | { | |
7973 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
00249aaa PB |
7974 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
7975 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
7976 | } |
7977 | ||
7978 | static void | |
7979 | vfp_conv (int srcsize) | |
7980 | { | |
7981 | unsigned immbits = srcsize - inst.operands[1].imm; | |
7982 | inst.instruction |= (immbits & 1) << 5; | |
7983 | inst.instruction |= (immbits >> 1); | |
7984 | } | |
7985 | ||
7986 | static void | |
7987 | do_vfp_sp_conv_16 (void) | |
7988 | { | |
7989 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
7990 | vfp_conv (16); | |
7991 | } | |
7992 | ||
7993 | static void | |
7994 | do_vfp_dp_conv_16 (void) | |
7995 | { | |
7996 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
7997 | vfp_conv (16); | |
7998 | } | |
7999 | ||
8000 | static void | |
8001 | do_vfp_sp_conv_32 (void) | |
8002 | { | |
8003 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
8004 | vfp_conv (32); | |
8005 | } | |
8006 | ||
8007 | static void | |
8008 | do_vfp_dp_conv_32 (void) | |
8009 | { | |
8010 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8011 | vfp_conv (32); | |
8012 | } | |
c19d1205 ZW |
8013 | \f |
8014 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 8015 | |
c19d1205 ZW |
8016 | static void |
8017 | do_fpa_cmp (void) | |
8018 | { | |
8019 | inst.instruction |= inst.operands[0].reg << 16; | |
8020 | inst.instruction |= inst.operands[1].reg; | |
8021 | } | |
b99bd4ef NC |
8022 | |
8023 | static void | |
c19d1205 | 8024 | do_fpa_ldmstm (void) |
b99bd4ef | 8025 | { |
c19d1205 ZW |
8026 | inst.instruction |= inst.operands[0].reg << 12; |
8027 | switch (inst.operands[1].imm) | |
8028 | { | |
8029 | case 1: inst.instruction |= CP_T_X; break; | |
8030 | case 2: inst.instruction |= CP_T_Y; break; | |
8031 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
8032 | case 4: break; | |
8033 | default: abort (); | |
8034 | } | |
b99bd4ef | 8035 | |
c19d1205 ZW |
8036 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
8037 | { | |
8038 | /* The instruction specified "ea" or "fd", so we can only accept | |
8039 | [Rn]{!}. The instruction does not really support stacking or | |
8040 | unstacking, so we have to emulate these by setting appropriate | |
8041 | bits and offsets. */ | |
8042 | constraint (inst.reloc.exp.X_op != O_constant | |
8043 | || inst.reloc.exp.X_add_number != 0, | |
8044 | _("this instruction does not support indexing")); | |
b99bd4ef | 8045 | |
c19d1205 ZW |
8046 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
8047 | inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; | |
b99bd4ef | 8048 | |
c19d1205 ZW |
8049 | if (!(inst.instruction & INDEX_UP)) |
8050 | inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; | |
b99bd4ef | 8051 | |
c19d1205 ZW |
8052 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
8053 | { | |
8054 | inst.operands[2].preind = 0; | |
8055 | inst.operands[2].postind = 1; | |
8056 | } | |
8057 | } | |
b99bd4ef | 8058 | |
c19d1205 | 8059 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 8060 | } |
c19d1205 ZW |
8061 | \f |
8062 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 8063 | |
c19d1205 ZW |
8064 | static void |
8065 | do_iwmmxt_tandorc (void) | |
8066 | { | |
8067 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
8068 | } | |
b99bd4ef | 8069 | |
c19d1205 ZW |
8070 | static void |
8071 | do_iwmmxt_textrc (void) | |
8072 | { | |
8073 | inst.instruction |= inst.operands[0].reg << 12; | |
8074 | inst.instruction |= inst.operands[1].imm; | |
8075 | } | |
b99bd4ef NC |
8076 | |
8077 | static void | |
c19d1205 | 8078 | do_iwmmxt_textrm (void) |
b99bd4ef | 8079 | { |
c19d1205 ZW |
8080 | inst.instruction |= inst.operands[0].reg << 12; |
8081 | inst.instruction |= inst.operands[1].reg << 16; | |
8082 | inst.instruction |= inst.operands[2].imm; | |
8083 | } | |
b99bd4ef | 8084 | |
c19d1205 ZW |
8085 | static void |
8086 | do_iwmmxt_tinsr (void) | |
8087 | { | |
8088 | inst.instruction |= inst.operands[0].reg << 16; | |
8089 | inst.instruction |= inst.operands[1].reg << 12; | |
8090 | inst.instruction |= inst.operands[2].imm; | |
8091 | } | |
b99bd4ef | 8092 | |
c19d1205 ZW |
8093 | static void |
8094 | do_iwmmxt_tmia (void) | |
8095 | { | |
8096 | inst.instruction |= inst.operands[0].reg << 5; | |
8097 | inst.instruction |= inst.operands[1].reg; | |
8098 | inst.instruction |= inst.operands[2].reg << 12; | |
8099 | } | |
b99bd4ef | 8100 | |
c19d1205 ZW |
8101 | static void |
8102 | do_iwmmxt_waligni (void) | |
8103 | { | |
8104 | inst.instruction |= inst.operands[0].reg << 12; | |
8105 | inst.instruction |= inst.operands[1].reg << 16; | |
8106 | inst.instruction |= inst.operands[2].reg; | |
8107 | inst.instruction |= inst.operands[3].imm << 20; | |
8108 | } | |
b99bd4ef | 8109 | |
2d447fca JM |
8110 | static void |
8111 | do_iwmmxt_wmerge (void) | |
8112 | { | |
8113 | inst.instruction |= inst.operands[0].reg << 12; | |
8114 | inst.instruction |= inst.operands[1].reg << 16; | |
8115 | inst.instruction |= inst.operands[2].reg; | |
8116 | inst.instruction |= inst.operands[3].imm << 21; | |
8117 | } | |
8118 | ||
c19d1205 ZW |
8119 | static void |
8120 | do_iwmmxt_wmov (void) | |
8121 | { | |
8122 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
8123 | inst.instruction |= inst.operands[0].reg << 12; | |
8124 | inst.instruction |= inst.operands[1].reg << 16; | |
8125 | inst.instruction |= inst.operands[1].reg; | |
8126 | } | |
b99bd4ef | 8127 | |
c19d1205 ZW |
8128 | static void |
8129 | do_iwmmxt_wldstbh (void) | |
8130 | { | |
8f06b2d8 | 8131 | int reloc; |
c19d1205 | 8132 | inst.instruction |= inst.operands[0].reg << 12; |
8f06b2d8 PB |
8133 | if (thumb_mode) |
8134 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
8135 | else | |
8136 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
8137 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
8138 | } |
8139 | ||
c19d1205 ZW |
8140 | static void |
8141 | do_iwmmxt_wldstw (void) | |
8142 | { | |
8143 | /* RIWR_RIWC clears .isreg for a control register. */ | |
8144 | if (!inst.operands[0].isreg) | |
8145 | { | |
8146 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
8147 | inst.instruction |= 0xf0000000; | |
8148 | } | |
b99bd4ef | 8149 | |
c19d1205 ZW |
8150 | inst.instruction |= inst.operands[0].reg << 12; |
8151 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
8152 | } | |
b99bd4ef NC |
8153 | |
8154 | static void | |
c19d1205 | 8155 | do_iwmmxt_wldstd (void) |
b99bd4ef | 8156 | { |
c19d1205 | 8157 | inst.instruction |= inst.operands[0].reg << 12; |
2d447fca JM |
8158 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) |
8159 | && inst.operands[1].immisreg) | |
8160 | { | |
8161 | inst.instruction &= ~0x1a000ff; | |
8162 | inst.instruction |= (0xf << 28); | |
8163 | if (inst.operands[1].preind) | |
8164 | inst.instruction |= PRE_INDEX; | |
8165 | if (!inst.operands[1].negative) | |
8166 | inst.instruction |= INDEX_UP; | |
8167 | if (inst.operands[1].writeback) | |
8168 | inst.instruction |= WRITE_BACK; | |
8169 | inst.instruction |= inst.operands[1].reg << 16; | |
8170 | inst.instruction |= inst.reloc.exp.X_add_number << 4; | |
8171 | inst.instruction |= inst.operands[1].imm; | |
8172 | } | |
8173 | else | |
8174 | encode_arm_cp_address (1, TRUE, FALSE, 0); | |
c19d1205 | 8175 | } |
b99bd4ef | 8176 | |
c19d1205 ZW |
8177 | static void |
8178 | do_iwmmxt_wshufh (void) | |
8179 | { | |
8180 | inst.instruction |= inst.operands[0].reg << 12; | |
8181 | inst.instruction |= inst.operands[1].reg << 16; | |
8182 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
8183 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
8184 | } | |
b99bd4ef | 8185 | |
c19d1205 ZW |
8186 | static void |
8187 | do_iwmmxt_wzero (void) | |
8188 | { | |
8189 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
8190 | inst.instruction |= inst.operands[0].reg; | |
8191 | inst.instruction |= inst.operands[0].reg << 12; | |
8192 | inst.instruction |= inst.operands[0].reg << 16; | |
8193 | } | |
2d447fca JM |
8194 | |
8195 | static void | |
8196 | do_iwmmxt_wrwrwr_or_imm5 (void) | |
8197 | { | |
8198 | if (inst.operands[2].isreg) | |
8199 | do_rd_rn_rm (); | |
8200 | else { | |
8201 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), | |
8202 | _("immediate operand requires iWMMXt2")); | |
8203 | do_rd_rn (); | |
8204 | if (inst.operands[2].imm == 0) | |
8205 | { | |
8206 | switch ((inst.instruction >> 20) & 0xf) | |
8207 | { | |
8208 | case 4: | |
8209 | case 5: | |
8210 | case 6: | |
5f4273c7 | 8211 | case 7: |
2d447fca JM |
8212 | /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ |
8213 | inst.operands[2].imm = 16; | |
8214 | inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); | |
8215 | break; | |
8216 | case 8: | |
8217 | case 9: | |
8218 | case 10: | |
8219 | case 11: | |
8220 | /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ | |
8221 | inst.operands[2].imm = 32; | |
8222 | inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); | |
8223 | break; | |
8224 | case 12: | |
8225 | case 13: | |
8226 | case 14: | |
8227 | case 15: | |
8228 | { | |
8229 | /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ | |
8230 | unsigned long wrn; | |
8231 | wrn = (inst.instruction >> 16) & 0xf; | |
8232 | inst.instruction &= 0xff0fff0f; | |
8233 | inst.instruction |= wrn; | |
8234 | /* Bail out here; the instruction is now assembled. */ | |
8235 | return; | |
8236 | } | |
8237 | } | |
8238 | } | |
8239 | /* Map 32 -> 0, etc. */ | |
8240 | inst.operands[2].imm &= 0x1f; | |
8241 | inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); | |
8242 | } | |
8243 | } | |
c19d1205 ZW |
8244 | \f |
8245 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
8246 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 8247 | |
c19d1205 | 8248 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 8249 | |
c19d1205 ZW |
8250 | static void |
8251 | do_mav_triple (void) | |
8252 | { | |
8253 | inst.instruction |= inst.operands[0].reg << 16; | |
8254 | inst.instruction |= inst.operands[1].reg; | |
8255 | inst.instruction |= inst.operands[2].reg << 12; | |
8256 | } | |
b99bd4ef | 8257 | |
c19d1205 ZW |
8258 | /* Insns like "foo W,X,Y,Z". |
8259 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 8260 | |
c19d1205 ZW |
8261 | static void |
8262 | do_mav_quad (void) | |
8263 | { | |
8264 | inst.instruction |= inst.operands[0].reg << 5; | |
8265 | inst.instruction |= inst.operands[1].reg << 12; | |
8266 | inst.instruction |= inst.operands[2].reg << 16; | |
8267 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
8268 | } |
8269 | ||
c19d1205 ZW |
8270 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
8271 | static void | |
8272 | do_mav_dspsc (void) | |
a737bd4d | 8273 | { |
c19d1205 ZW |
8274 | inst.instruction |= inst.operands[1].reg << 12; |
8275 | } | |
a737bd4d | 8276 | |
c19d1205 ZW |
8277 | /* Maverick shift immediate instructions. |
8278 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
8279 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 8280 | |
c19d1205 ZW |
8281 | static void |
8282 | do_mav_shift (void) | |
8283 | { | |
8284 | int imm = inst.operands[2].imm; | |
a737bd4d | 8285 | |
c19d1205 ZW |
8286 | inst.instruction |= inst.operands[0].reg << 12; |
8287 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 8288 | |
c19d1205 ZW |
8289 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
8290 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
8291 | Bit 4 should be 0. */ | |
8292 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 8293 | |
c19d1205 ZW |
8294 | inst.instruction |= imm; |
8295 | } | |
8296 | \f | |
8297 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 8298 | |
c19d1205 ZW |
8299 | /* Xscale multiply-accumulate (argument parse) |
8300 | MIAcc acc0,Rm,Rs | |
8301 | MIAPHcc acc0,Rm,Rs | |
8302 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 8303 | |
c19d1205 ZW |
8304 | static void |
8305 | do_xsc_mia (void) | |
8306 | { | |
8307 | inst.instruction |= inst.operands[1].reg; | |
8308 | inst.instruction |= inst.operands[2].reg << 12; | |
8309 | } | |
a737bd4d | 8310 | |
c19d1205 | 8311 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 8312 | |
c19d1205 | 8313 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 8314 | |
c19d1205 ZW |
8315 | static void |
8316 | do_xsc_mar (void) | |
8317 | { | |
8318 | inst.instruction |= inst.operands[1].reg << 12; | |
8319 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
8320 | } |
8321 | ||
c19d1205 | 8322 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 8323 | |
c19d1205 | 8324 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
8325 | |
8326 | static void | |
c19d1205 | 8327 | do_xsc_mra (void) |
b99bd4ef | 8328 | { |
c19d1205 ZW |
8329 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
8330 | inst.instruction |= inst.operands[0].reg << 12; | |
8331 | inst.instruction |= inst.operands[1].reg << 16; | |
8332 | } | |
8333 | \f | |
8334 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 8335 | |
c19d1205 ZW |
8336 | /* inst.operands[i] is a shifted-register operand; encode |
8337 | it into inst.instruction in the format used by Thumb32. */ | |
8338 | ||
8339 | static void | |
8340 | encode_thumb32_shifted_operand (int i) | |
8341 | { | |
8342 | unsigned int value = inst.reloc.exp.X_add_number; | |
8343 | unsigned int shift = inst.operands[i].shift_kind; | |
b99bd4ef | 8344 | |
9c3c69f2 PB |
8345 | constraint (inst.operands[i].immisreg, |
8346 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
8347 | inst.instruction |= inst.operands[i].reg; |
8348 | if (shift == SHIFT_RRX) | |
8349 | inst.instruction |= SHIFT_ROR << 4; | |
8350 | else | |
b99bd4ef | 8351 | { |
c19d1205 ZW |
8352 | constraint (inst.reloc.exp.X_op != O_constant, |
8353 | _("expression too complex")); | |
8354 | ||
8355 | constraint (value > 32 | |
8356 | || (value == 32 && (shift == SHIFT_LSL | |
8357 | || shift == SHIFT_ROR)), | |
8358 | _("shift expression is too large")); | |
8359 | ||
8360 | if (value == 0) | |
8361 | shift = SHIFT_LSL; | |
8362 | else if (value == 32) | |
8363 | value = 0; | |
8364 | ||
8365 | inst.instruction |= shift << 4; | |
8366 | inst.instruction |= (value & 0x1c) << 10; | |
8367 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 8368 | } |
c19d1205 | 8369 | } |
b99bd4ef | 8370 | |
b99bd4ef | 8371 | |
c19d1205 ZW |
8372 | /* inst.operands[i] was set up by parse_address. Encode it into a |
8373 | Thumb32 format load or store instruction. Reject forms that cannot | |
8374 | be used with such instructions. If is_t is true, reject forms that | |
8375 | cannot be used with a T instruction; if is_d is true, reject forms | |
8376 | that cannot be used with a D instruction. */ | |
b99bd4ef | 8377 | |
c19d1205 ZW |
8378 | static void |
8379 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
8380 | { | |
8381 | bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); | |
8382 | ||
8383 | constraint (!inst.operands[i].isreg, | |
53365c0d | 8384 | _("Instruction does not support =N addresses")); |
b99bd4ef | 8385 | |
c19d1205 ZW |
8386 | inst.instruction |= inst.operands[i].reg << 16; |
8387 | if (inst.operands[i].immisreg) | |
b99bd4ef | 8388 | { |
c19d1205 ZW |
8389 | constraint (is_pc, _("cannot use register index with PC-relative addressing")); |
8390 | constraint (is_t || is_d, _("cannot use register index with this instruction")); | |
8391 | constraint (inst.operands[i].negative, | |
8392 | _("Thumb does not support negative register indexing")); | |
8393 | constraint (inst.operands[i].postind, | |
8394 | _("Thumb does not support register post-indexing")); | |
8395 | constraint (inst.operands[i].writeback, | |
8396 | _("Thumb does not support register indexing with writeback")); | |
8397 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
8398 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 8399 | |
f40d1643 | 8400 | inst.instruction |= inst.operands[i].imm; |
c19d1205 | 8401 | if (inst.operands[i].shifted) |
b99bd4ef | 8402 | { |
c19d1205 ZW |
8403 | constraint (inst.reloc.exp.X_op != O_constant, |
8404 | _("expression too complex")); | |
9c3c69f2 PB |
8405 | constraint (inst.reloc.exp.X_add_number < 0 |
8406 | || inst.reloc.exp.X_add_number > 3, | |
c19d1205 | 8407 | _("shift out of range")); |
9c3c69f2 | 8408 | inst.instruction |= inst.reloc.exp.X_add_number << 4; |
c19d1205 ZW |
8409 | } |
8410 | inst.reloc.type = BFD_RELOC_UNUSED; | |
8411 | } | |
8412 | else if (inst.operands[i].preind) | |
8413 | { | |
8414 | constraint (is_pc && inst.operands[i].writeback, | |
8415 | _("cannot use writeback with PC-relative addressing")); | |
f40d1643 | 8416 | constraint (is_t && inst.operands[i].writeback, |
c19d1205 ZW |
8417 | _("cannot use writeback with this instruction")); |
8418 | ||
8419 | if (is_d) | |
8420 | { | |
8421 | inst.instruction |= 0x01000000; | |
8422 | if (inst.operands[i].writeback) | |
8423 | inst.instruction |= 0x00200000; | |
b99bd4ef | 8424 | } |
c19d1205 | 8425 | else |
b99bd4ef | 8426 | { |
c19d1205 ZW |
8427 | inst.instruction |= 0x00000c00; |
8428 | if (inst.operands[i].writeback) | |
8429 | inst.instruction |= 0x00000100; | |
b99bd4ef | 8430 | } |
c19d1205 | 8431 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 8432 | } |
c19d1205 | 8433 | else if (inst.operands[i].postind) |
b99bd4ef | 8434 | { |
c19d1205 ZW |
8435 | assert (inst.operands[i].writeback); |
8436 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); | |
8437 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
8438 | ||
8439 | if (is_d) | |
8440 | inst.instruction |= 0x00200000; | |
8441 | else | |
8442 | inst.instruction |= 0x00000900; | |
8443 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
8444 | } | |
8445 | else /* unindexed - only for coprocessor */ | |
8446 | inst.error = _("instruction does not accept unindexed addressing"); | |
8447 | } | |
8448 | ||
8449 | /* Table of Thumb instructions which exist in both 16- and 32-bit | |
8450 | encodings (the latter only in post-V6T2 cores). The index is the | |
8451 | value used in the insns table below. When there is more than one | |
8452 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
8453 | holds variant (1). |
8454 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 ZW |
8455 | #define T16_32_TAB \ |
8456 | X(adc, 4140, eb400000), \ | |
8457 | X(adcs, 4140, eb500000), \ | |
8458 | X(add, 1c00, eb000000), \ | |
8459 | X(adds, 1c00, eb100000), \ | |
0110f2b8 PB |
8460 | X(addi, 0000, f1000000), \ |
8461 | X(addis, 0000, f1100000), \ | |
8462 | X(add_pc,000f, f20f0000), \ | |
8463 | X(add_sp,000d, f10d0000), \ | |
e9f89963 | 8464 | X(adr, 000f, f20f0000), \ |
c19d1205 ZW |
8465 | X(and, 4000, ea000000), \ |
8466 | X(ands, 4000, ea100000), \ | |
8467 | X(asr, 1000, fa40f000), \ | |
8468 | X(asrs, 1000, fa50f000), \ | |
0110f2b8 PB |
8469 | X(b, e000, f000b000), \ |
8470 | X(bcond, d000, f0008000), \ | |
c19d1205 ZW |
8471 | X(bic, 4380, ea200000), \ |
8472 | X(bics, 4380, ea300000), \ | |
8473 | X(cmn, 42c0, eb100f00), \ | |
8474 | X(cmp, 2800, ebb00f00), \ | |
8475 | X(cpsie, b660, f3af8400), \ | |
8476 | X(cpsid, b670, f3af8600), \ | |
8477 | X(cpy, 4600, ea4f0000), \ | |
155257ea | 8478 | X(dec_sp,80dd, f1ad0d00), \ |
c19d1205 ZW |
8479 | X(eor, 4040, ea800000), \ |
8480 | X(eors, 4040, ea900000), \ | |
0110f2b8 | 8481 | X(inc_sp,00dd, f10d0d00), \ |
c19d1205 ZW |
8482 | X(ldmia, c800, e8900000), \ |
8483 | X(ldr, 6800, f8500000), \ | |
8484 | X(ldrb, 7800, f8100000), \ | |
8485 | X(ldrh, 8800, f8300000), \ | |
8486 | X(ldrsb, 5600, f9100000), \ | |
8487 | X(ldrsh, 5e00, f9300000), \ | |
0110f2b8 PB |
8488 | X(ldr_pc,4800, f85f0000), \ |
8489 | X(ldr_pc2,4800, f85f0000), \ | |
8490 | X(ldr_sp,9800, f85d0000), \ | |
c19d1205 ZW |
8491 | X(lsl, 0000, fa00f000), \ |
8492 | X(lsls, 0000, fa10f000), \ | |
8493 | X(lsr, 0800, fa20f000), \ | |
8494 | X(lsrs, 0800, fa30f000), \ | |
8495 | X(mov, 2000, ea4f0000), \ | |
8496 | X(movs, 2000, ea5f0000), \ | |
8497 | X(mul, 4340, fb00f000), \ | |
8498 | X(muls, 4340, ffffffff), /* no 32b muls */ \ | |
8499 | X(mvn, 43c0, ea6f0000), \ | |
8500 | X(mvns, 43c0, ea7f0000), \ | |
8501 | X(neg, 4240, f1c00000), /* rsb #0 */ \ | |
8502 | X(negs, 4240, f1d00000), /* rsbs #0 */ \ | |
8503 | X(orr, 4300, ea400000), \ | |
8504 | X(orrs, 4300, ea500000), \ | |
e9f89963 PB |
8505 | X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \ |
8506 | X(push, b400, e92d0000), /* stmdb sp!,... */ \ | |
c19d1205 ZW |
8507 | X(rev, ba00, fa90f080), \ |
8508 | X(rev16, ba40, fa90f090), \ | |
8509 | X(revsh, bac0, fa90f0b0), \ | |
8510 | X(ror, 41c0, fa60f000), \ | |
8511 | X(rors, 41c0, fa70f000), \ | |
8512 | X(sbc, 4180, eb600000), \ | |
8513 | X(sbcs, 4180, eb700000), \ | |
8514 | X(stmia, c000, e8800000), \ | |
8515 | X(str, 6000, f8400000), \ | |
8516 | X(strb, 7000, f8000000), \ | |
8517 | X(strh, 8000, f8200000), \ | |
0110f2b8 | 8518 | X(str_sp,9000, f84d0000), \ |
c19d1205 ZW |
8519 | X(sub, 1e00, eba00000), \ |
8520 | X(subs, 1e00, ebb00000), \ | |
0110f2b8 PB |
8521 | X(subi, 8000, f1a00000), \ |
8522 | X(subis, 8000, f1b00000), \ | |
c19d1205 ZW |
8523 | X(sxtb, b240, fa4ff080), \ |
8524 | X(sxth, b200, fa0ff080), \ | |
8525 | X(tst, 4200, ea100f00), \ | |
8526 | X(uxtb, b2c0, fa5ff080), \ | |
8527 | X(uxth, b280, fa1ff080), \ | |
8528 | X(nop, bf00, f3af8000), \ | |
8529 | X(yield, bf10, f3af8001), \ | |
8530 | X(wfe, bf20, f3af8002), \ | |
8531 | X(wfi, bf30, f3af8003), \ | |
fe2ceba1 | 8532 | X(sev, bf40, f3af8004), |
c19d1205 ZW |
8533 | |
8534 | /* To catch errors in encoding functions, the codes are all offset by | |
8535 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
8536 | as 16-bit instructions. */ | |
8537 | #define X(a,b,c) T_MNEM_##a | |
8538 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; | |
8539 | #undef X | |
8540 | ||
8541 | #define X(a,b,c) 0x##b | |
8542 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
8543 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
8544 | #undef X | |
8545 | ||
8546 | #define X(a,b,c) 0x##c | |
8547 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
8548 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) | |
8549 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
8550 | #undef X | |
8551 | #undef T16_32_TAB | |
8552 | ||
8553 | /* Thumb instruction encoders, in alphabetical order. */ | |
8554 | ||
92e90b6e PB |
8555 | /* ADDW or SUBW. */ |
8556 | static void | |
8557 | do_t_add_sub_w (void) | |
8558 | { | |
8559 | int Rd, Rn; | |
8560 | ||
8561 | Rd = inst.operands[0].reg; | |
8562 | Rn = inst.operands[1].reg; | |
8563 | ||
fdfde340 JM |
8564 | /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this is the |
8565 | SP-{plus,minute}-immediate form of the instruction. */ | |
8566 | reject_bad_reg (Rd); | |
8567 | ||
92e90b6e PB |
8568 | inst.instruction |= (Rn << 16) | (Rd << 8); |
8569 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
8570 | } | |
8571 | ||
c19d1205 ZW |
8572 | /* Parse an add or subtract instruction. We get here with inst.instruction |
8573 | equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ | |
8574 | ||
8575 | static void | |
8576 | do_t_add_sub (void) | |
8577 | { | |
8578 | int Rd, Rs, Rn; | |
8579 | ||
8580 | Rd = inst.operands[0].reg; | |
8581 | Rs = (inst.operands[1].present | |
8582 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
8583 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
8584 | ||
e07e6e58 NC |
8585 | if (Rd == REG_PC) |
8586 | set_it_insn_type_last (); | |
8587 | ||
c19d1205 ZW |
8588 | if (unified_syntax) |
8589 | { | |
0110f2b8 PB |
8590 | bfd_boolean flags; |
8591 | bfd_boolean narrow; | |
8592 | int opcode; | |
8593 | ||
8594 | flags = (inst.instruction == T_MNEM_adds | |
8595 | || inst.instruction == T_MNEM_subs); | |
8596 | if (flags) | |
e07e6e58 | 8597 | narrow = !in_it_block (); |
0110f2b8 | 8598 | else |
e07e6e58 | 8599 | narrow = in_it_block (); |
c19d1205 | 8600 | if (!inst.operands[2].isreg) |
b99bd4ef | 8601 | { |
16805f35 PB |
8602 | int add; |
8603 | ||
fdfde340 JM |
8604 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); |
8605 | ||
16805f35 PB |
8606 | add = (inst.instruction == T_MNEM_add |
8607 | || inst.instruction == T_MNEM_adds); | |
0110f2b8 PB |
8608 | opcode = 0; |
8609 | if (inst.size_req != 4) | |
8610 | { | |
0110f2b8 PB |
8611 | /* Attempt to use a narrow opcode, with relaxation if |
8612 | appropriate. */ | |
8613 | if (Rd == REG_SP && Rs == REG_SP && !flags) | |
8614 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
8615 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
8616 | opcode = T_MNEM_add_sp; | |
8617 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
8618 | opcode = T_MNEM_add_pc; | |
8619 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
8620 | { | |
8621 | if (flags) | |
8622 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
8623 | else | |
8624 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
8625 | } | |
8626 | if (opcode) | |
8627 | { | |
8628 | inst.instruction = THUMB_OP16(opcode); | |
8629 | inst.instruction |= (Rd << 4) | Rs; | |
8630 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
8631 | if (inst.size_req != 2) | |
8632 | inst.relax = opcode; | |
8633 | } | |
8634 | else | |
8635 | constraint (inst.size_req == 2, BAD_HIREG); | |
8636 | } | |
8637 | if (inst.size_req == 4 | |
8638 | || (inst.size_req != 2 && !opcode)) | |
8639 | { | |
efd81785 PB |
8640 | if (Rd == REG_PC) |
8641 | { | |
fdfde340 | 8642 | constraint (add, BAD_PC); |
efd81785 PB |
8643 | constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, |
8644 | _("only SUBS PC, LR, #const allowed")); | |
8645 | constraint (inst.reloc.exp.X_op != O_constant, | |
8646 | _("expression too complex")); | |
8647 | constraint (inst.reloc.exp.X_add_number < 0 | |
8648 | || inst.reloc.exp.X_add_number > 0xff, | |
8649 | _("immediate value out of range")); | |
8650 | inst.instruction = T2_SUBS_PC_LR | |
8651 | | inst.reloc.exp.X_add_number; | |
8652 | inst.reloc.type = BFD_RELOC_UNUSED; | |
8653 | return; | |
8654 | } | |
8655 | else if (Rs == REG_PC) | |
16805f35 PB |
8656 | { |
8657 | /* Always use addw/subw. */ | |
8658 | inst.instruction = add ? 0xf20f0000 : 0xf2af0000; | |
8659 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
8660 | } | |
8661 | else | |
8662 | { | |
8663 | inst.instruction = THUMB_OP32 (inst.instruction); | |
8664 | inst.instruction = (inst.instruction & 0xe1ffffff) | |
8665 | | 0x10000000; | |
8666 | if (flags) | |
8667 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
8668 | else | |
8669 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; | |
8670 | } | |
dc4503c6 PB |
8671 | inst.instruction |= Rd << 8; |
8672 | inst.instruction |= Rs << 16; | |
0110f2b8 | 8673 | } |
b99bd4ef | 8674 | } |
c19d1205 ZW |
8675 | else |
8676 | { | |
8677 | Rn = inst.operands[2].reg; | |
8678 | /* See if we can do this with a 16-bit instruction. */ | |
8679 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
8680 | { | |
e27ec89e PB |
8681 | if (Rd > 7 || Rs > 7 || Rn > 7) |
8682 | narrow = FALSE; | |
8683 | ||
8684 | if (narrow) | |
c19d1205 | 8685 | { |
e27ec89e PB |
8686 | inst.instruction = ((inst.instruction == T_MNEM_adds |
8687 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
8688 | ? T_OPCODE_ADD_R3 |
8689 | : T_OPCODE_SUB_R3); | |
8690 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
8691 | return; | |
8692 | } | |
b99bd4ef | 8693 | |
7e806470 | 8694 | if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) |
c19d1205 | 8695 | { |
7e806470 PB |
8696 | /* Thumb-1 cores (except v6-M) require at least one high |
8697 | register in a narrow non flag setting add. */ | |
8698 | if (Rd > 7 || Rn > 7 | |
8699 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2) | |
8700 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr)) | |
c19d1205 | 8701 | { |
7e806470 PB |
8702 | if (Rd == Rn) |
8703 | { | |
8704 | Rn = Rs; | |
8705 | Rs = Rd; | |
8706 | } | |
c19d1205 ZW |
8707 | inst.instruction = T_OPCODE_ADD_HI; |
8708 | inst.instruction |= (Rd & 8) << 4; | |
8709 | inst.instruction |= (Rd & 7); | |
8710 | inst.instruction |= Rn << 3; | |
8711 | return; | |
8712 | } | |
c19d1205 ZW |
8713 | } |
8714 | } | |
fdfde340 JM |
8715 | |
8716 | constraint (Rd == REG_PC, BAD_PC); | |
8717 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); | |
8718 | constraint (Rs == REG_PC, BAD_PC); | |
8719 | reject_bad_reg (Rn); | |
8720 | ||
c19d1205 ZW |
8721 | /* If we get here, it can't be done in 16 bits. */ |
8722 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
8723 | _("shift must be constant")); | |
8724 | inst.instruction = THUMB_OP32 (inst.instruction); | |
8725 | inst.instruction |= Rd << 8; | |
8726 | inst.instruction |= Rs << 16; | |
8727 | encode_thumb32_shifted_operand (2); | |
8728 | } | |
8729 | } | |
8730 | else | |
8731 | { | |
8732 | constraint (inst.instruction == T_MNEM_adds | |
8733 | || inst.instruction == T_MNEM_subs, | |
8734 | BAD_THUMB32); | |
b99bd4ef | 8735 | |
c19d1205 | 8736 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 8737 | { |
c19d1205 ZW |
8738 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
8739 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
8740 | BAD_HIREG); | |
8741 | ||
8742 | inst.instruction = (inst.instruction == T_MNEM_add | |
8743 | ? 0x0000 : 0x8000); | |
8744 | inst.instruction |= (Rd << 4) | Rs; | |
8745 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
b99bd4ef NC |
8746 | return; |
8747 | } | |
8748 | ||
c19d1205 ZW |
8749 | Rn = inst.operands[2].reg; |
8750 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 8751 | |
c19d1205 ZW |
8752 | /* We now have Rd, Rs, and Rn set to registers. */ |
8753 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 8754 | { |
c19d1205 ZW |
8755 | /* Can't do this for SUB. */ |
8756 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
8757 | inst.instruction = T_OPCODE_ADD_HI; | |
8758 | inst.instruction |= (Rd & 8) << 4; | |
8759 | inst.instruction |= (Rd & 7); | |
8760 | if (Rs == Rd) | |
8761 | inst.instruction |= Rn << 3; | |
8762 | else if (Rn == Rd) | |
8763 | inst.instruction |= Rs << 3; | |
8764 | else | |
8765 | constraint (1, _("dest must overlap one source register")); | |
8766 | } | |
8767 | else | |
8768 | { | |
8769 | inst.instruction = (inst.instruction == T_MNEM_add | |
8770 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
8771 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 8772 | } |
b99bd4ef | 8773 | } |
b99bd4ef NC |
8774 | } |
8775 | ||
c19d1205 ZW |
8776 | static void |
8777 | do_t_adr (void) | |
8778 | { | |
fdfde340 JM |
8779 | unsigned Rd; |
8780 | ||
8781 | Rd = inst.operands[0].reg; | |
8782 | reject_bad_reg (Rd); | |
8783 | ||
8784 | if (unified_syntax && inst.size_req == 0 && Rd <= 7) | |
0110f2b8 PB |
8785 | { |
8786 | /* Defer to section relaxation. */ | |
8787 | inst.relax = inst.instruction; | |
8788 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 | 8789 | inst.instruction |= Rd << 4; |
0110f2b8 PB |
8790 | } |
8791 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 8792 | { |
0110f2b8 | 8793 | /* Generate a 32-bit opcode. */ |
e9f89963 | 8794 | inst.instruction = THUMB_OP32 (inst.instruction); |
fdfde340 | 8795 | inst.instruction |= Rd << 8; |
e9f89963 PB |
8796 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; |
8797 | inst.reloc.pc_rel = 1; | |
8798 | } | |
8799 | else | |
8800 | { | |
0110f2b8 | 8801 | /* Generate a 16-bit opcode. */ |
e9f89963 PB |
8802 | inst.instruction = THUMB_OP16 (inst.instruction); |
8803 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
8804 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
8805 | inst.reloc.pc_rel = 1; | |
b99bd4ef | 8806 | |
fdfde340 | 8807 | inst.instruction |= Rd << 4; |
e9f89963 | 8808 | } |
c19d1205 | 8809 | } |
b99bd4ef | 8810 | |
c19d1205 ZW |
8811 | /* Arithmetic instructions for which there is just one 16-bit |
8812 | instruction encoding, and it allows only two low registers. | |
8813 | For maximal compatibility with ARM syntax, we allow three register | |
8814 | operands even when Thumb-32 instructions are not available, as long | |
8815 | as the first two are identical. For instance, both "sbc r0,r1" and | |
8816 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 8817 | static void |
c19d1205 | 8818 | do_t_arit3 (void) |
b99bd4ef | 8819 | { |
c19d1205 | 8820 | int Rd, Rs, Rn; |
b99bd4ef | 8821 | |
c19d1205 ZW |
8822 | Rd = inst.operands[0].reg; |
8823 | Rs = (inst.operands[1].present | |
8824 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
8825 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
8826 | Rn = inst.operands[2].reg; | |
b99bd4ef | 8827 | |
fdfde340 JM |
8828 | reject_bad_reg (Rd); |
8829 | reject_bad_reg (Rs); | |
8830 | if (inst.operands[2].isreg) | |
8831 | reject_bad_reg (Rn); | |
8832 | ||
c19d1205 | 8833 | if (unified_syntax) |
b99bd4ef | 8834 | { |
c19d1205 ZW |
8835 | if (!inst.operands[2].isreg) |
8836 | { | |
8837 | /* For an immediate, we always generate a 32-bit opcode; | |
8838 | section relaxation will shrink it later if possible. */ | |
8839 | inst.instruction = THUMB_OP32 (inst.instruction); | |
8840 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
8841 | inst.instruction |= Rd << 8; | |
8842 | inst.instruction |= Rs << 16; | |
8843 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
8844 | } | |
8845 | else | |
8846 | { | |
e27ec89e PB |
8847 | bfd_boolean narrow; |
8848 | ||
c19d1205 | 8849 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 8850 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 8851 | narrow = !in_it_block (); |
e27ec89e | 8852 | else |
e07e6e58 | 8853 | narrow = in_it_block (); |
e27ec89e PB |
8854 | |
8855 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
8856 | narrow = FALSE; | |
8857 | if (inst.operands[2].shifted) | |
8858 | narrow = FALSE; | |
8859 | if (inst.size_req == 4) | |
8860 | narrow = FALSE; | |
8861 | ||
8862 | if (narrow | |
c19d1205 ZW |
8863 | && Rd == Rs) |
8864 | { | |
8865 | inst.instruction = THUMB_OP16 (inst.instruction); | |
8866 | inst.instruction |= Rd; | |
8867 | inst.instruction |= Rn << 3; | |
8868 | return; | |
8869 | } | |
b99bd4ef | 8870 | |
c19d1205 ZW |
8871 | /* If we get here, it can't be done in 16 bits. */ |
8872 | constraint (inst.operands[2].shifted | |
8873 | && inst.operands[2].immisreg, | |
8874 | _("shift must be constant")); | |
8875 | inst.instruction = THUMB_OP32 (inst.instruction); | |
8876 | inst.instruction |= Rd << 8; | |
8877 | inst.instruction |= Rs << 16; | |
8878 | encode_thumb32_shifted_operand (2); | |
8879 | } | |
a737bd4d | 8880 | } |
c19d1205 | 8881 | else |
b99bd4ef | 8882 | { |
c19d1205 ZW |
8883 | /* On its face this is a lie - the instruction does set the |
8884 | flags. However, the only supported mnemonic in this mode | |
8885 | says it doesn't. */ | |
8886 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 8887 | |
c19d1205 ZW |
8888 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
8889 | _("unshifted register required")); | |
8890 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
8891 | constraint (Rd != Rs, | |
8892 | _("dest and source1 must be the same register")); | |
a737bd4d | 8893 | |
c19d1205 ZW |
8894 | inst.instruction = THUMB_OP16 (inst.instruction); |
8895 | inst.instruction |= Rd; | |
8896 | inst.instruction |= Rn << 3; | |
b99bd4ef | 8897 | } |
a737bd4d | 8898 | } |
b99bd4ef | 8899 | |
c19d1205 ZW |
8900 | /* Similarly, but for instructions where the arithmetic operation is |
8901 | commutative, so we can allow either of them to be different from | |
8902 | the destination operand in a 16-bit instruction. For instance, all | |
8903 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
8904 | accepted. */ | |
8905 | static void | |
8906 | do_t_arit3c (void) | |
a737bd4d | 8907 | { |
c19d1205 | 8908 | int Rd, Rs, Rn; |
b99bd4ef | 8909 | |
c19d1205 ZW |
8910 | Rd = inst.operands[0].reg; |
8911 | Rs = (inst.operands[1].present | |
8912 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
8913 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
8914 | Rn = inst.operands[2].reg; | |
fdfde340 JM |
8915 | |
8916 | reject_bad_reg (Rd); | |
8917 | reject_bad_reg (Rs); | |
8918 | if (inst.operands[2].isreg) | |
8919 | reject_bad_reg (Rn); | |
a737bd4d | 8920 | |
c19d1205 | 8921 | if (unified_syntax) |
a737bd4d | 8922 | { |
c19d1205 | 8923 | if (!inst.operands[2].isreg) |
b99bd4ef | 8924 | { |
c19d1205 ZW |
8925 | /* For an immediate, we always generate a 32-bit opcode; |
8926 | section relaxation will shrink it later if possible. */ | |
8927 | inst.instruction = THUMB_OP32 (inst.instruction); | |
8928 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
8929 | inst.instruction |= Rd << 8; | |
8930 | inst.instruction |= Rs << 16; | |
8931 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 8932 | } |
c19d1205 | 8933 | else |
a737bd4d | 8934 | { |
e27ec89e PB |
8935 | bfd_boolean narrow; |
8936 | ||
c19d1205 | 8937 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 8938 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 8939 | narrow = !in_it_block (); |
e27ec89e | 8940 | else |
e07e6e58 | 8941 | narrow = in_it_block (); |
e27ec89e PB |
8942 | |
8943 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
8944 | narrow = FALSE; | |
8945 | if (inst.operands[2].shifted) | |
8946 | narrow = FALSE; | |
8947 | if (inst.size_req == 4) | |
8948 | narrow = FALSE; | |
8949 | ||
8950 | if (narrow) | |
a737bd4d | 8951 | { |
c19d1205 | 8952 | if (Rd == Rs) |
a737bd4d | 8953 | { |
c19d1205 ZW |
8954 | inst.instruction = THUMB_OP16 (inst.instruction); |
8955 | inst.instruction |= Rd; | |
8956 | inst.instruction |= Rn << 3; | |
8957 | return; | |
a737bd4d | 8958 | } |
c19d1205 | 8959 | if (Rd == Rn) |
a737bd4d | 8960 | { |
c19d1205 ZW |
8961 | inst.instruction = THUMB_OP16 (inst.instruction); |
8962 | inst.instruction |= Rd; | |
8963 | inst.instruction |= Rs << 3; | |
8964 | return; | |
a737bd4d NC |
8965 | } |
8966 | } | |
c19d1205 ZW |
8967 | |
8968 | /* If we get here, it can't be done in 16 bits. */ | |
8969 | constraint (inst.operands[2].shifted | |
8970 | && inst.operands[2].immisreg, | |
8971 | _("shift must be constant")); | |
8972 | inst.instruction = THUMB_OP32 (inst.instruction); | |
8973 | inst.instruction |= Rd << 8; | |
8974 | inst.instruction |= Rs << 16; | |
8975 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 8976 | } |
b99bd4ef | 8977 | } |
c19d1205 ZW |
8978 | else |
8979 | { | |
8980 | /* On its face this is a lie - the instruction does set the | |
8981 | flags. However, the only supported mnemonic in this mode | |
8982 | says it doesn't. */ | |
8983 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 8984 | |
c19d1205 ZW |
8985 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
8986 | _("unshifted register required")); | |
8987 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
8988 | ||
8989 | inst.instruction = THUMB_OP16 (inst.instruction); | |
8990 | inst.instruction |= Rd; | |
8991 | ||
8992 | if (Rd == Rs) | |
8993 | inst.instruction |= Rn << 3; | |
8994 | else if (Rd == Rn) | |
8995 | inst.instruction |= Rs << 3; | |
8996 | else | |
8997 | constraint (1, _("dest must overlap one source register")); | |
8998 | } | |
a737bd4d NC |
8999 | } |
9000 | ||
62b3e311 PB |
9001 | static void |
9002 | do_t_barrier (void) | |
9003 | { | |
9004 | if (inst.operands[0].present) | |
9005 | { | |
9006 | constraint ((inst.instruction & 0xf0) != 0x40 | |
9007 | && inst.operands[0].imm != 0xf, | |
bd3ba5d1 | 9008 | _("bad barrier type")); |
62b3e311 PB |
9009 | inst.instruction |= inst.operands[0].imm; |
9010 | } | |
9011 | else | |
9012 | inst.instruction |= 0xf; | |
9013 | } | |
9014 | ||
c19d1205 ZW |
9015 | static void |
9016 | do_t_bfc (void) | |
a737bd4d | 9017 | { |
fdfde340 | 9018 | unsigned Rd; |
c19d1205 ZW |
9019 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
9020 | constraint (msb > 32, _("bit-field extends past end of register")); | |
9021 | /* The instruction encoding stores the LSB and MSB, | |
9022 | not the LSB and width. */ | |
fdfde340 JM |
9023 | Rd = inst.operands[0].reg; |
9024 | reject_bad_reg (Rd); | |
9025 | inst.instruction |= Rd << 8; | |
c19d1205 ZW |
9026 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; |
9027 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
9028 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
9029 | } |
9030 | ||
c19d1205 ZW |
9031 | static void |
9032 | do_t_bfi (void) | |
b99bd4ef | 9033 | { |
fdfde340 | 9034 | int Rd, Rn; |
c19d1205 | 9035 | unsigned int msb; |
b99bd4ef | 9036 | |
fdfde340 JM |
9037 | Rd = inst.operands[0].reg; |
9038 | reject_bad_reg (Rd); | |
9039 | ||
c19d1205 ZW |
9040 | /* #0 in second position is alternative syntax for bfc, which is |
9041 | the same instruction but with REG_PC in the Rm field. */ | |
9042 | if (!inst.operands[1].isreg) | |
fdfde340 JM |
9043 | Rn = REG_PC; |
9044 | else | |
9045 | { | |
9046 | Rn = inst.operands[1].reg; | |
9047 | reject_bad_reg (Rn); | |
9048 | } | |
b99bd4ef | 9049 | |
c19d1205 ZW |
9050 | msb = inst.operands[2].imm + inst.operands[3].imm; |
9051 | constraint (msb > 32, _("bit-field extends past end of register")); | |
9052 | /* The instruction encoding stores the LSB and MSB, | |
9053 | not the LSB and width. */ | |
fdfde340 JM |
9054 | inst.instruction |= Rd << 8; |
9055 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
9056 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
9057 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
9058 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
9059 | } |
9060 | ||
c19d1205 ZW |
9061 | static void |
9062 | do_t_bfx (void) | |
b99bd4ef | 9063 | { |
fdfde340 JM |
9064 | unsigned Rd, Rn; |
9065 | ||
9066 | Rd = inst.operands[0].reg; | |
9067 | Rn = inst.operands[1].reg; | |
9068 | ||
9069 | reject_bad_reg (Rd); | |
9070 | reject_bad_reg (Rn); | |
9071 | ||
c19d1205 ZW |
9072 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
9073 | _("bit-field extends past end of register")); | |
fdfde340 JM |
9074 | inst.instruction |= Rd << 8; |
9075 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
9076 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
9077 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
9078 | inst.instruction |= inst.operands[3].imm - 1; | |
9079 | } | |
b99bd4ef | 9080 | |
c19d1205 ZW |
9081 | /* ARM V5 Thumb BLX (argument parse) |
9082 | BLX <target_addr> which is BLX(1) | |
9083 | BLX <Rm> which is BLX(2) | |
9084 | Unfortunately, there are two different opcodes for this mnemonic. | |
9085 | So, the insns[].value is not used, and the code here zaps values | |
9086 | into inst.instruction. | |
b99bd4ef | 9087 | |
c19d1205 ZW |
9088 | ??? How to take advantage of the additional two bits of displacement |
9089 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 9090 | |
c19d1205 ZW |
9091 | static void |
9092 | do_t_blx (void) | |
9093 | { | |
e07e6e58 NC |
9094 | set_it_insn_type_last (); |
9095 | ||
c19d1205 | 9096 | if (inst.operands[0].isreg) |
fdfde340 JM |
9097 | { |
9098 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); | |
9099 | /* We have a register, so this is BLX(2). */ | |
9100 | inst.instruction |= inst.operands[0].reg << 3; | |
9101 | } | |
b99bd4ef NC |
9102 | else |
9103 | { | |
c19d1205 | 9104 | /* No register. This must be BLX(1). */ |
2fc8bdac | 9105 | inst.instruction = 0xf000e800; |
00adf2d4 | 9106 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; |
c19d1205 | 9107 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
9108 | } |
9109 | } | |
9110 | ||
c19d1205 ZW |
9111 | static void |
9112 | do_t_branch (void) | |
b99bd4ef | 9113 | { |
0110f2b8 | 9114 | int opcode; |
dfa9f0d5 PB |
9115 | int cond; |
9116 | ||
e07e6e58 NC |
9117 | cond = inst.cond; |
9118 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); | |
9119 | ||
9120 | if (in_it_block ()) | |
dfa9f0d5 PB |
9121 | { |
9122 | /* Conditional branches inside IT blocks are encoded as unconditional | |
9123 | branches. */ | |
9124 | cond = COND_ALWAYS; | |
dfa9f0d5 PB |
9125 | } |
9126 | else | |
9127 | cond = inst.cond; | |
9128 | ||
9129 | if (cond != COND_ALWAYS) | |
0110f2b8 PB |
9130 | opcode = T_MNEM_bcond; |
9131 | else | |
9132 | opcode = inst.instruction; | |
9133 | ||
9134 | if (unified_syntax && inst.size_req == 4) | |
c19d1205 | 9135 | { |
0110f2b8 | 9136 | inst.instruction = THUMB_OP32(opcode); |
dfa9f0d5 | 9137 | if (cond == COND_ALWAYS) |
0110f2b8 | 9138 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
9139 | else |
9140 | { | |
dfa9f0d5 PB |
9141 | assert (cond != 0xF); |
9142 | inst.instruction |= cond << 22; | |
c19d1205 ZW |
9143 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20; |
9144 | } | |
9145 | } | |
b99bd4ef NC |
9146 | else |
9147 | { | |
0110f2b8 | 9148 | inst.instruction = THUMB_OP16(opcode); |
dfa9f0d5 | 9149 | if (cond == COND_ALWAYS) |
c19d1205 ZW |
9150 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12; |
9151 | else | |
b99bd4ef | 9152 | { |
dfa9f0d5 | 9153 | inst.instruction |= cond << 8; |
c19d1205 | 9154 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 9155 | } |
0110f2b8 PB |
9156 | /* Allow section relaxation. */ |
9157 | if (unified_syntax && inst.size_req != 2) | |
9158 | inst.relax = opcode; | |
b99bd4ef | 9159 | } |
c19d1205 ZW |
9160 | |
9161 | inst.reloc.pc_rel = 1; | |
b99bd4ef NC |
9162 | } |
9163 | ||
9164 | static void | |
c19d1205 | 9165 | do_t_bkpt (void) |
b99bd4ef | 9166 | { |
dfa9f0d5 PB |
9167 | constraint (inst.cond != COND_ALWAYS, |
9168 | _("instruction is always unconditional")); | |
c19d1205 | 9169 | if (inst.operands[0].present) |
b99bd4ef | 9170 | { |
c19d1205 ZW |
9171 | constraint (inst.operands[0].imm > 255, |
9172 | _("immediate value out of range")); | |
9173 | inst.instruction |= inst.operands[0].imm; | |
e07e6e58 | 9174 | set_it_insn_type (NEUTRAL_IT_INSN); |
b99bd4ef | 9175 | } |
b99bd4ef NC |
9176 | } |
9177 | ||
9178 | static void | |
c19d1205 | 9179 | do_t_branch23 (void) |
b99bd4ef | 9180 | { |
e07e6e58 | 9181 | set_it_insn_type_last (); |
c19d1205 | 9182 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; |
90e4755a RE |
9183 | inst.reloc.pc_rel = 1; |
9184 | ||
4343666d | 9185 | #if defined(OBJ_COFF) |
c19d1205 ZW |
9186 | /* If the destination of the branch is a defined symbol which does not have |
9187 | the THUMB_FUNC attribute, then we must be calling a function which has | |
9188 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
9189 | function and change the branch to refer to that function instead. */ | |
9190 | if ( inst.reloc.exp.X_op == O_symbol | |
9191 | && inst.reloc.exp.X_add_symbol != NULL | |
9192 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
9193 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
9194 | inst.reloc.exp.X_add_symbol = | |
9195 | find_real_start (inst.reloc.exp.X_add_symbol); | |
4343666d | 9196 | #endif |
90e4755a RE |
9197 | } |
9198 | ||
9199 | static void | |
c19d1205 | 9200 | do_t_bx (void) |
90e4755a | 9201 | { |
e07e6e58 | 9202 | set_it_insn_type_last (); |
c19d1205 ZW |
9203 | inst.instruction |= inst.operands[0].reg << 3; |
9204 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
9205 | should cause the alignment to be checked once it is known. This is | |
9206 | because BX PC only works if the instruction is word aligned. */ | |
9207 | } | |
90e4755a | 9208 | |
c19d1205 ZW |
9209 | static void |
9210 | do_t_bxj (void) | |
9211 | { | |
fdfde340 | 9212 | int Rm; |
90e4755a | 9213 | |
e07e6e58 | 9214 | set_it_insn_type_last (); |
fdfde340 JM |
9215 | Rm = inst.operands[0].reg; |
9216 | reject_bad_reg (Rm); | |
9217 | inst.instruction |= Rm << 16; | |
90e4755a RE |
9218 | } |
9219 | ||
9220 | static void | |
c19d1205 | 9221 | do_t_clz (void) |
90e4755a | 9222 | { |
fdfde340 JM |
9223 | unsigned Rd; |
9224 | unsigned Rm; | |
9225 | ||
9226 | Rd = inst.operands[0].reg; | |
9227 | Rm = inst.operands[1].reg; | |
9228 | ||
9229 | reject_bad_reg (Rd); | |
9230 | reject_bad_reg (Rm); | |
9231 | ||
9232 | inst.instruction |= Rd << 8; | |
9233 | inst.instruction |= Rm << 16; | |
9234 | inst.instruction |= Rm; | |
c19d1205 | 9235 | } |
90e4755a | 9236 | |
dfa9f0d5 PB |
9237 | static void |
9238 | do_t_cps (void) | |
9239 | { | |
e07e6e58 | 9240 | set_it_insn_type (OUTSIDE_IT_INSN); |
dfa9f0d5 PB |
9241 | inst.instruction |= inst.operands[0].imm; |
9242 | } | |
9243 | ||
c19d1205 ZW |
9244 | static void |
9245 | do_t_cpsi (void) | |
9246 | { | |
e07e6e58 | 9247 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 | 9248 | if (unified_syntax |
62b3e311 PB |
9249 | && (inst.operands[1].present || inst.size_req == 4) |
9250 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) | |
90e4755a | 9251 | { |
c19d1205 ZW |
9252 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
9253 | inst.instruction = 0xf3af8000; | |
9254 | inst.instruction |= imod << 9; | |
9255 | inst.instruction |= inst.operands[0].imm << 5; | |
9256 | if (inst.operands[1].present) | |
9257 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 9258 | } |
c19d1205 | 9259 | else |
90e4755a | 9260 | { |
62b3e311 PB |
9261 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) |
9262 | && (inst.operands[0].imm & 4), | |
9263 | _("selected processor does not support 'A' form " | |
9264 | "of this instruction")); | |
9265 | constraint (inst.operands[1].present || inst.size_req == 4, | |
c19d1205 ZW |
9266 | _("Thumb does not support the 2-argument " |
9267 | "form of this instruction")); | |
9268 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 9269 | } |
90e4755a RE |
9270 | } |
9271 | ||
c19d1205 ZW |
9272 | /* THUMB CPY instruction (argument parse). */ |
9273 | ||
90e4755a | 9274 | static void |
c19d1205 | 9275 | do_t_cpy (void) |
90e4755a | 9276 | { |
c19d1205 | 9277 | if (inst.size_req == 4) |
90e4755a | 9278 | { |
c19d1205 ZW |
9279 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
9280 | inst.instruction |= inst.operands[0].reg << 8; | |
9281 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 9282 | } |
c19d1205 | 9283 | else |
90e4755a | 9284 | { |
c19d1205 ZW |
9285 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
9286 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
9287 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 9288 | } |
90e4755a RE |
9289 | } |
9290 | ||
90e4755a | 9291 | static void |
25fe350b | 9292 | do_t_cbz (void) |
90e4755a | 9293 | { |
e07e6e58 | 9294 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
9295 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
9296 | inst.instruction |= inst.operands[0].reg; | |
9297 | inst.reloc.pc_rel = 1; | |
9298 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
9299 | } | |
90e4755a | 9300 | |
62b3e311 PB |
9301 | static void |
9302 | do_t_dbg (void) | |
9303 | { | |
9304 | inst.instruction |= inst.operands[0].imm; | |
9305 | } | |
9306 | ||
9307 | static void | |
9308 | do_t_div (void) | |
9309 | { | |
fdfde340 JM |
9310 | unsigned Rd, Rn, Rm; |
9311 | ||
9312 | Rd = inst.operands[0].reg; | |
9313 | Rn = (inst.operands[1].present | |
9314 | ? inst.operands[1].reg : Rd); | |
9315 | Rm = inst.operands[2].reg; | |
9316 | ||
9317 | reject_bad_reg (Rd); | |
9318 | reject_bad_reg (Rn); | |
9319 | reject_bad_reg (Rm); | |
9320 | ||
9321 | inst.instruction |= Rd << 8; | |
9322 | inst.instruction |= Rn << 16; | |
9323 | inst.instruction |= Rm; | |
62b3e311 PB |
9324 | } |
9325 | ||
c19d1205 ZW |
9326 | static void |
9327 | do_t_hint (void) | |
9328 | { | |
9329 | if (unified_syntax && inst.size_req == 4) | |
9330 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9331 | else | |
9332 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9333 | } | |
90e4755a | 9334 | |
c19d1205 ZW |
9335 | static void |
9336 | do_t_it (void) | |
9337 | { | |
9338 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e | 9339 | |
e07e6e58 NC |
9340 | set_it_insn_type (IT_INSN); |
9341 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
9342 | now_it.cc = cond; | |
e27ec89e PB |
9343 | |
9344 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 9345 | if ((cond & 0x1) == 0x0) |
90e4755a | 9346 | { |
c19d1205 | 9347 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 9348 | |
c19d1205 ZW |
9349 | if ((mask & 0x7) == 0) |
9350 | /* no conversion needed */; | |
9351 | else if ((mask & 0x3) == 0) | |
e27ec89e PB |
9352 | mask ^= 0x8; |
9353 | else if ((mask & 0x1) == 0) | |
9354 | mask ^= 0xC; | |
c19d1205 | 9355 | else |
e27ec89e | 9356 | mask ^= 0xE; |
90e4755a | 9357 | |
e27ec89e PB |
9358 | inst.instruction &= 0xfff0; |
9359 | inst.instruction |= mask; | |
c19d1205 | 9360 | } |
90e4755a | 9361 | |
c19d1205 ZW |
9362 | inst.instruction |= cond << 4; |
9363 | } | |
90e4755a | 9364 | |
3c707909 PB |
9365 | /* Helper function used for both push/pop and ldm/stm. */ |
9366 | static void | |
9367 | encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) | |
9368 | { | |
9369 | bfd_boolean load; | |
9370 | ||
9371 | load = (inst.instruction & (1 << 20)) != 0; | |
9372 | ||
9373 | if (mask & (1 << 13)) | |
9374 | inst.error = _("SP not allowed in register list"); | |
9375 | if (load) | |
9376 | { | |
e07e6e58 NC |
9377 | if (mask & (1 << 15)) |
9378 | { | |
9379 | if (mask & (1 << 14)) | |
9380 | inst.error = _("LR and PC should not both be in register list"); | |
9381 | else | |
9382 | set_it_insn_type_last (); | |
9383 | } | |
3c707909 PB |
9384 | |
9385 | if ((mask & (1 << base)) != 0 | |
9386 | && writeback) | |
9387 | as_warn (_("base register should not be in register list " | |
9388 | "when written back")); | |
9389 | } | |
9390 | else | |
9391 | { | |
9392 | if (mask & (1 << 15)) | |
9393 | inst.error = _("PC not allowed in register list"); | |
9394 | ||
9395 | if (mask & (1 << base)) | |
9396 | as_warn (_("value stored for r%d is UNPREDICTABLE"), base); | |
9397 | } | |
9398 | ||
9399 | if ((mask & (mask - 1)) == 0) | |
9400 | { | |
9401 | /* Single register transfers implemented as str/ldr. */ | |
9402 | if (writeback) | |
9403 | { | |
9404 | if (inst.instruction & (1 << 23)) | |
9405 | inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ | |
9406 | else | |
9407 | inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ | |
9408 | } | |
9409 | else | |
9410 | { | |
9411 | if (inst.instruction & (1 << 23)) | |
9412 | inst.instruction = 0x00800000; /* ia -> [base] */ | |
9413 | else | |
9414 | inst.instruction = 0x00000c04; /* db -> [base, #-4] */ | |
9415 | } | |
9416 | ||
9417 | inst.instruction |= 0xf8400000; | |
9418 | if (load) | |
9419 | inst.instruction |= 0x00100000; | |
9420 | ||
5f4273c7 | 9421 | mask = ffs (mask) - 1; |
3c707909 PB |
9422 | mask <<= 12; |
9423 | } | |
9424 | else if (writeback) | |
9425 | inst.instruction |= WRITE_BACK; | |
9426 | ||
9427 | inst.instruction |= mask; | |
9428 | inst.instruction |= base << 16; | |
9429 | } | |
9430 | ||
c19d1205 ZW |
9431 | static void |
9432 | do_t_ldmstm (void) | |
9433 | { | |
9434 | /* This really doesn't seem worth it. */ | |
9435 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
9436 | _("expression too complex")); | |
9437 | constraint (inst.operands[1].writeback, | |
9438 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 9439 | |
c19d1205 ZW |
9440 | if (unified_syntax) |
9441 | { | |
3c707909 PB |
9442 | bfd_boolean narrow; |
9443 | unsigned mask; | |
9444 | ||
9445 | narrow = FALSE; | |
c19d1205 ZW |
9446 | /* See if we can use a 16-bit instruction. */ |
9447 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
9448 | && inst.size_req != 4 | |
3c707909 | 9449 | && !(inst.operands[1].imm & ~0xff)) |
90e4755a | 9450 | { |
3c707909 | 9451 | mask = 1 << inst.operands[0].reg; |
90e4755a | 9452 | |
3c707909 PB |
9453 | if (inst.operands[0].reg <= 7 |
9454 | && (inst.instruction == T_MNEM_stmia | |
9455 | ? inst.operands[0].writeback | |
9456 | : (inst.operands[0].writeback | |
9457 | == !(inst.operands[1].imm & mask)))) | |
90e4755a | 9458 | { |
3c707909 PB |
9459 | if (inst.instruction == T_MNEM_stmia |
9460 | && (inst.operands[1].imm & mask) | |
9461 | && (inst.operands[1].imm & (mask - 1))) | |
c19d1205 ZW |
9462 | as_warn (_("value stored for r%d is UNPREDICTABLE"), |
9463 | inst.operands[0].reg); | |
3c707909 PB |
9464 | |
9465 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9466 | inst.instruction |= inst.operands[0].reg << 8; | |
9467 | inst.instruction |= inst.operands[1].imm; | |
9468 | narrow = TRUE; | |
90e4755a | 9469 | } |
3c707909 PB |
9470 | else if (inst.operands[0] .reg == REG_SP |
9471 | && inst.operands[0].writeback) | |
90e4755a | 9472 | { |
3c707909 PB |
9473 | inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia |
9474 | ? T_MNEM_push : T_MNEM_pop); | |
9475 | inst.instruction |= inst.operands[1].imm; | |
9476 | narrow = TRUE; | |
90e4755a | 9477 | } |
3c707909 PB |
9478 | } |
9479 | ||
9480 | if (!narrow) | |
9481 | { | |
c19d1205 ZW |
9482 | if (inst.instruction < 0xffff) |
9483 | inst.instruction = THUMB_OP32 (inst.instruction); | |
3c707909 | 9484 | |
5f4273c7 NC |
9485 | encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm, |
9486 | inst.operands[0].writeback); | |
90e4755a RE |
9487 | } |
9488 | } | |
c19d1205 | 9489 | else |
90e4755a | 9490 | { |
c19d1205 ZW |
9491 | constraint (inst.operands[0].reg > 7 |
9492 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
1198ca51 PB |
9493 | constraint (inst.instruction != T_MNEM_ldmia |
9494 | && inst.instruction != T_MNEM_stmia, | |
9495 | _("Thumb-2 instruction only valid in unified syntax")); | |
c19d1205 | 9496 | if (inst.instruction == T_MNEM_stmia) |
f03698e6 | 9497 | { |
c19d1205 ZW |
9498 | if (!inst.operands[0].writeback) |
9499 | as_warn (_("this instruction will write back the base register")); | |
9500 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
9501 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
9502 | as_warn (_("value stored for r%d is UNPREDICTABLE"), | |
9503 | inst.operands[0].reg); | |
f03698e6 | 9504 | } |
c19d1205 | 9505 | else |
90e4755a | 9506 | { |
c19d1205 ZW |
9507 | if (!inst.operands[0].writeback |
9508 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
9509 | as_warn (_("this instruction will write back the base register")); | |
9510 | else if (inst.operands[0].writeback | |
9511 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
9512 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
9513 | } |
9514 | ||
c19d1205 ZW |
9515 | inst.instruction = THUMB_OP16 (inst.instruction); |
9516 | inst.instruction |= inst.operands[0].reg << 8; | |
9517 | inst.instruction |= inst.operands[1].imm; | |
9518 | } | |
9519 | } | |
e28cd48c | 9520 | |
c19d1205 ZW |
9521 | static void |
9522 | do_t_ldrex (void) | |
9523 | { | |
9524 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
9525 | || inst.operands[1].postind || inst.operands[1].writeback | |
9526 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
9527 | || inst.operands[1].negative, | |
01cfc07f | 9528 | BAD_ADDR_MODE); |
e28cd48c | 9529 | |
c19d1205 ZW |
9530 | inst.instruction |= inst.operands[0].reg << 12; |
9531 | inst.instruction |= inst.operands[1].reg << 16; | |
9532 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
9533 | } | |
e28cd48c | 9534 | |
c19d1205 ZW |
9535 | static void |
9536 | do_t_ldrexd (void) | |
9537 | { | |
9538 | if (!inst.operands[1].present) | |
1cac9012 | 9539 | { |
c19d1205 ZW |
9540 | constraint (inst.operands[0].reg == REG_LR, |
9541 | _("r14 not allowed as first register " | |
9542 | "when second register is omitted")); | |
9543 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 9544 | } |
c19d1205 ZW |
9545 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
9546 | BAD_OVERLAP); | |
b99bd4ef | 9547 | |
c19d1205 ZW |
9548 | inst.instruction |= inst.operands[0].reg << 12; |
9549 | inst.instruction |= inst.operands[1].reg << 8; | |
9550 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
9551 | } |
9552 | ||
9553 | static void | |
c19d1205 | 9554 | do_t_ldst (void) |
b99bd4ef | 9555 | { |
0110f2b8 PB |
9556 | unsigned long opcode; |
9557 | int Rn; | |
9558 | ||
e07e6e58 NC |
9559 | if (inst.operands[0].isreg |
9560 | && !inst.operands[0].preind | |
9561 | && inst.operands[0].reg == REG_PC) | |
9562 | set_it_insn_type_last (); | |
9563 | ||
0110f2b8 | 9564 | opcode = inst.instruction; |
c19d1205 | 9565 | if (unified_syntax) |
b99bd4ef | 9566 | { |
53365c0d PB |
9567 | if (!inst.operands[1].isreg) |
9568 | { | |
9569 | if (opcode <= 0xffff) | |
9570 | inst.instruction = THUMB_OP32 (opcode); | |
9571 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
9572 | return; | |
9573 | } | |
0110f2b8 PB |
9574 | if (inst.operands[1].isreg |
9575 | && !inst.operands[1].writeback | |
c19d1205 ZW |
9576 | && !inst.operands[1].shifted && !inst.operands[1].postind |
9577 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
9578 | && opcode <= 0xffff |
9579 | && inst.size_req != 4) | |
c19d1205 | 9580 | { |
0110f2b8 PB |
9581 | /* Insn may have a 16-bit form. */ |
9582 | Rn = inst.operands[1].reg; | |
9583 | if (inst.operands[1].immisreg) | |
9584 | { | |
9585 | inst.instruction = THUMB_OP16 (opcode); | |
5f4273c7 | 9586 | /* [Rn, Rik] */ |
0110f2b8 PB |
9587 | if (Rn <= 7 && inst.operands[1].imm <= 7) |
9588 | goto op16; | |
9589 | } | |
9590 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
9591 | && opcode != T_MNEM_ldrsb) | |
9592 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
9593 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
9594 | { | |
9595 | /* [Rn, #const] */ | |
9596 | if (Rn > 7) | |
9597 | { | |
9598 | if (Rn == REG_PC) | |
9599 | { | |
9600 | if (inst.reloc.pc_rel) | |
9601 | opcode = T_MNEM_ldr_pc2; | |
9602 | else | |
9603 | opcode = T_MNEM_ldr_pc; | |
9604 | } | |
9605 | else | |
9606 | { | |
9607 | if (opcode == T_MNEM_ldr) | |
9608 | opcode = T_MNEM_ldr_sp; | |
9609 | else | |
9610 | opcode = T_MNEM_str_sp; | |
9611 | } | |
9612 | inst.instruction = inst.operands[0].reg << 8; | |
9613 | } | |
9614 | else | |
9615 | { | |
9616 | inst.instruction = inst.operands[0].reg; | |
9617 | inst.instruction |= inst.operands[1].reg << 3; | |
9618 | } | |
9619 | inst.instruction |= THUMB_OP16 (opcode); | |
9620 | if (inst.size_req == 2) | |
9621 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
9622 | else | |
9623 | inst.relax = opcode; | |
9624 | return; | |
9625 | } | |
c19d1205 | 9626 | } |
0110f2b8 PB |
9627 | /* Definitely a 32-bit variant. */ |
9628 | inst.instruction = THUMB_OP32 (opcode); | |
c19d1205 ZW |
9629 | inst.instruction |= inst.operands[0].reg << 12; |
9630 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
b99bd4ef NC |
9631 | return; |
9632 | } | |
9633 | ||
c19d1205 ZW |
9634 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
9635 | ||
9636 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 9637 | { |
c19d1205 ZW |
9638 | /* Only [Rn,Rm] is acceptable. */ |
9639 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
9640 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
9641 | || inst.operands[1].postind || inst.operands[1].shifted | |
9642 | || inst.operands[1].negative, | |
9643 | _("Thumb does not support this addressing mode")); | |
9644 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9645 | goto op16; | |
b99bd4ef | 9646 | } |
5f4273c7 | 9647 | |
c19d1205 ZW |
9648 | inst.instruction = THUMB_OP16 (inst.instruction); |
9649 | if (!inst.operands[1].isreg) | |
9650 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
9651 | return; | |
b99bd4ef | 9652 | |
c19d1205 ZW |
9653 | constraint (!inst.operands[1].preind |
9654 | || inst.operands[1].shifted | |
9655 | || inst.operands[1].writeback, | |
9656 | _("Thumb does not support this addressing mode")); | |
9657 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 9658 | { |
c19d1205 ZW |
9659 | constraint (inst.instruction & 0x0600, |
9660 | _("byte or halfword not valid for base register")); | |
9661 | constraint (inst.operands[1].reg == REG_PC | |
9662 | && !(inst.instruction & THUMB_LOAD_BIT), | |
9663 | _("r15 based store not allowed")); | |
9664 | constraint (inst.operands[1].immisreg, | |
9665 | _("invalid base register for register offset")); | |
b99bd4ef | 9666 | |
c19d1205 ZW |
9667 | if (inst.operands[1].reg == REG_PC) |
9668 | inst.instruction = T_OPCODE_LDR_PC; | |
9669 | else if (inst.instruction & THUMB_LOAD_BIT) | |
9670 | inst.instruction = T_OPCODE_LDR_SP; | |
9671 | else | |
9672 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 9673 | |
c19d1205 ZW |
9674 | inst.instruction |= inst.operands[0].reg << 8; |
9675 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
9676 | return; | |
9677 | } | |
90e4755a | 9678 | |
c19d1205 ZW |
9679 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
9680 | if (!inst.operands[1].immisreg) | |
9681 | { | |
9682 | /* Immediate offset. */ | |
9683 | inst.instruction |= inst.operands[0].reg; | |
9684 | inst.instruction |= inst.operands[1].reg << 3; | |
9685 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
9686 | return; | |
9687 | } | |
90e4755a | 9688 | |
c19d1205 ZW |
9689 | /* Register offset. */ |
9690 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
9691 | constraint (inst.operands[1].negative, | |
9692 | _("Thumb does not support this addressing mode")); | |
90e4755a | 9693 | |
c19d1205 ZW |
9694 | op16: |
9695 | switch (inst.instruction) | |
9696 | { | |
9697 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
9698 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
9699 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
9700 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
9701 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
9702 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
9703 | case 0x5600 /* ldrsb */: | |
9704 | case 0x5e00 /* ldrsh */: break; | |
9705 | default: abort (); | |
9706 | } | |
90e4755a | 9707 | |
c19d1205 ZW |
9708 | inst.instruction |= inst.operands[0].reg; |
9709 | inst.instruction |= inst.operands[1].reg << 3; | |
9710 | inst.instruction |= inst.operands[1].imm << 6; | |
9711 | } | |
90e4755a | 9712 | |
c19d1205 ZW |
9713 | static void |
9714 | do_t_ldstd (void) | |
9715 | { | |
9716 | if (!inst.operands[1].present) | |
b99bd4ef | 9717 | { |
c19d1205 ZW |
9718 | inst.operands[1].reg = inst.operands[0].reg + 1; |
9719 | constraint (inst.operands[0].reg == REG_LR, | |
9720 | _("r14 not allowed here")); | |
b99bd4ef | 9721 | } |
c19d1205 ZW |
9722 | inst.instruction |= inst.operands[0].reg << 12; |
9723 | inst.instruction |= inst.operands[1].reg << 8; | |
9724 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
b99bd4ef NC |
9725 | } |
9726 | ||
c19d1205 ZW |
9727 | static void |
9728 | do_t_ldstt (void) | |
9729 | { | |
9730 | inst.instruction |= inst.operands[0].reg << 12; | |
9731 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
9732 | } | |
a737bd4d | 9733 | |
b99bd4ef | 9734 | static void |
c19d1205 | 9735 | do_t_mla (void) |
b99bd4ef | 9736 | { |
fdfde340 JM |
9737 | unsigned Rd, Rn, Rm, Ra; |
9738 | ||
9739 | Rd = inst.operands[0].reg; | |
9740 | Rn = inst.operands[1].reg; | |
9741 | Rm = inst.operands[2].reg; | |
9742 | Ra = inst.operands[3].reg; | |
9743 | ||
9744 | reject_bad_reg (Rd); | |
9745 | reject_bad_reg (Rn); | |
9746 | reject_bad_reg (Rm); | |
9747 | reject_bad_reg (Ra); | |
9748 | ||
9749 | inst.instruction |= Rd << 8; | |
9750 | inst.instruction |= Rn << 16; | |
9751 | inst.instruction |= Rm; | |
9752 | inst.instruction |= Ra << 12; | |
c19d1205 | 9753 | } |
b99bd4ef | 9754 | |
c19d1205 ZW |
9755 | static void |
9756 | do_t_mlal (void) | |
9757 | { | |
fdfde340 JM |
9758 | unsigned RdLo, RdHi, Rn, Rm; |
9759 | ||
9760 | RdLo = inst.operands[0].reg; | |
9761 | RdHi = inst.operands[1].reg; | |
9762 | Rn = inst.operands[2].reg; | |
9763 | Rm = inst.operands[3].reg; | |
9764 | ||
9765 | reject_bad_reg (RdLo); | |
9766 | reject_bad_reg (RdHi); | |
9767 | reject_bad_reg (Rn); | |
9768 | reject_bad_reg (Rm); | |
9769 | ||
9770 | inst.instruction |= RdLo << 12; | |
9771 | inst.instruction |= RdHi << 8; | |
9772 | inst.instruction |= Rn << 16; | |
9773 | inst.instruction |= Rm; | |
c19d1205 | 9774 | } |
b99bd4ef | 9775 | |
c19d1205 ZW |
9776 | static void |
9777 | do_t_mov_cmp (void) | |
9778 | { | |
fdfde340 JM |
9779 | unsigned Rn, Rm; |
9780 | ||
9781 | Rn = inst.operands[0].reg; | |
9782 | Rm = inst.operands[1].reg; | |
9783 | ||
e07e6e58 NC |
9784 | if (Rn == REG_PC) |
9785 | set_it_insn_type_last (); | |
9786 | ||
c19d1205 | 9787 | if (unified_syntax) |
b99bd4ef | 9788 | { |
c19d1205 ZW |
9789 | int r0off = (inst.instruction == T_MNEM_mov |
9790 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 9791 | unsigned long opcode; |
3d388997 PB |
9792 | bfd_boolean narrow; |
9793 | bfd_boolean low_regs; | |
9794 | ||
fdfde340 | 9795 | low_regs = (Rn <= 7 && Rm <= 7); |
0110f2b8 | 9796 | opcode = inst.instruction; |
e07e6e58 | 9797 | if (in_it_block ()) |
0110f2b8 | 9798 | narrow = opcode != T_MNEM_movs; |
3d388997 | 9799 | else |
0110f2b8 | 9800 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
9801 | if (inst.size_req == 4 |
9802 | || inst.operands[1].shifted) | |
9803 | narrow = FALSE; | |
9804 | ||
efd81785 PB |
9805 | /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ |
9806 | if (opcode == T_MNEM_movs && inst.operands[1].isreg | |
9807 | && !inst.operands[1].shifted | |
fdfde340 JM |
9808 | && Rn == REG_PC |
9809 | && Rm == REG_LR) | |
efd81785 PB |
9810 | { |
9811 | inst.instruction = T2_SUBS_PC_LR; | |
9812 | return; | |
9813 | } | |
9814 | ||
fdfde340 JM |
9815 | if (opcode == T_MNEM_cmp) |
9816 | { | |
9817 | constraint (Rn == REG_PC, BAD_PC); | |
94206790 MM |
9818 | if (narrow) |
9819 | { | |
9820 | /* In the Thumb-2 ISA, use of R13 as Rm is deprecated, | |
9821 | but valid. */ | |
9822 | warn_deprecated_sp (Rm); | |
9823 | /* R15 was documented as a valid choice for Rm in ARMv6, | |
9824 | but as UNPREDICTABLE in ARMv7. ARM's proprietary | |
9825 | tools reject R15, so we do too. */ | |
9826 | constraint (Rm == REG_PC, BAD_PC); | |
9827 | } | |
9828 | else | |
9829 | reject_bad_reg (Rm); | |
fdfde340 JM |
9830 | } |
9831 | else if (opcode == T_MNEM_mov | |
9832 | || opcode == T_MNEM_movs) | |
9833 | { | |
9834 | if (inst.operands[1].isreg) | |
9835 | { | |
9836 | if (opcode == T_MNEM_movs) | |
9837 | { | |
9838 | reject_bad_reg (Rn); | |
9839 | reject_bad_reg (Rm); | |
9840 | } | |
9841 | else if ((Rn == REG_SP || Rn == REG_PC) | |
9842 | && (Rm == REG_SP || Rm == REG_PC)) | |
9843 | reject_bad_reg (Rm); | |
9844 | } | |
9845 | else | |
9846 | reject_bad_reg (Rn); | |
9847 | } | |
9848 | ||
c19d1205 ZW |
9849 | if (!inst.operands[1].isreg) |
9850 | { | |
0110f2b8 | 9851 | /* Immediate operand. */ |
e07e6e58 | 9852 | if (!in_it_block () && opcode == T_MNEM_mov) |
0110f2b8 PB |
9853 | narrow = 0; |
9854 | if (low_regs && narrow) | |
9855 | { | |
9856 | inst.instruction = THUMB_OP16 (opcode); | |
fdfde340 | 9857 | inst.instruction |= Rn << 8; |
0110f2b8 PB |
9858 | if (inst.size_req == 2) |
9859 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
9860 | else | |
9861 | inst.relax = opcode; | |
9862 | } | |
9863 | else | |
9864 | { | |
9865 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9866 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 9867 | inst.instruction |= Rn << r0off; |
0110f2b8 PB |
9868 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
9869 | } | |
c19d1205 | 9870 | } |
728ca7c9 PB |
9871 | else if (inst.operands[1].shifted && inst.operands[1].immisreg |
9872 | && (inst.instruction == T_MNEM_mov | |
9873 | || inst.instruction == T_MNEM_movs)) | |
9874 | { | |
9875 | /* Register shifts are encoded as separate shift instructions. */ | |
9876 | bfd_boolean flags = (inst.instruction == T_MNEM_movs); | |
9877 | ||
e07e6e58 | 9878 | if (in_it_block ()) |
728ca7c9 PB |
9879 | narrow = !flags; |
9880 | else | |
9881 | narrow = flags; | |
9882 | ||
9883 | if (inst.size_req == 4) | |
9884 | narrow = FALSE; | |
9885 | ||
9886 | if (!low_regs || inst.operands[1].imm > 7) | |
9887 | narrow = FALSE; | |
9888 | ||
fdfde340 | 9889 | if (Rn != Rm) |
728ca7c9 PB |
9890 | narrow = FALSE; |
9891 | ||
9892 | switch (inst.operands[1].shift_kind) | |
9893 | { | |
9894 | case SHIFT_LSL: | |
9895 | opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); | |
9896 | break; | |
9897 | case SHIFT_ASR: | |
9898 | opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); | |
9899 | break; | |
9900 | case SHIFT_LSR: | |
9901 | opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); | |
9902 | break; | |
9903 | case SHIFT_ROR: | |
9904 | opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); | |
9905 | break; | |
9906 | default: | |
5f4273c7 | 9907 | abort (); |
728ca7c9 PB |
9908 | } |
9909 | ||
9910 | inst.instruction = opcode; | |
9911 | if (narrow) | |
9912 | { | |
fdfde340 | 9913 | inst.instruction |= Rn; |
728ca7c9 PB |
9914 | inst.instruction |= inst.operands[1].imm << 3; |
9915 | } | |
9916 | else | |
9917 | { | |
9918 | if (flags) | |
9919 | inst.instruction |= CONDS_BIT; | |
9920 | ||
fdfde340 JM |
9921 | inst.instruction |= Rn << 8; |
9922 | inst.instruction |= Rm << 16; | |
728ca7c9 PB |
9923 | inst.instruction |= inst.operands[1].imm; |
9924 | } | |
9925 | } | |
3d388997 | 9926 | else if (!narrow) |
c19d1205 | 9927 | { |
728ca7c9 PB |
9928 | /* Some mov with immediate shift have narrow variants. |
9929 | Register shifts are handled above. */ | |
9930 | if (low_regs && inst.operands[1].shifted | |
9931 | && (inst.instruction == T_MNEM_mov | |
9932 | || inst.instruction == T_MNEM_movs)) | |
9933 | { | |
e07e6e58 | 9934 | if (in_it_block ()) |
728ca7c9 PB |
9935 | narrow = (inst.instruction == T_MNEM_mov); |
9936 | else | |
9937 | narrow = (inst.instruction == T_MNEM_movs); | |
9938 | } | |
9939 | ||
9940 | if (narrow) | |
9941 | { | |
9942 | switch (inst.operands[1].shift_kind) | |
9943 | { | |
9944 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
9945 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
9946 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; | |
9947 | default: narrow = FALSE; break; | |
9948 | } | |
9949 | } | |
9950 | ||
9951 | if (narrow) | |
9952 | { | |
fdfde340 JM |
9953 | inst.instruction |= Rn; |
9954 | inst.instruction |= Rm << 3; | |
728ca7c9 PB |
9955 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
9956 | } | |
9957 | else | |
9958 | { | |
9959 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 9960 | inst.instruction |= Rn << r0off; |
728ca7c9 PB |
9961 | encode_thumb32_shifted_operand (1); |
9962 | } | |
c19d1205 ZW |
9963 | } |
9964 | else | |
9965 | switch (inst.instruction) | |
9966 | { | |
9967 | case T_MNEM_mov: | |
9968 | inst.instruction = T_OPCODE_MOV_HR; | |
fdfde340 JM |
9969 | inst.instruction |= (Rn & 0x8) << 4; |
9970 | inst.instruction |= (Rn & 0x7); | |
9971 | inst.instruction |= Rm << 3; | |
c19d1205 | 9972 | break; |
b99bd4ef | 9973 | |
c19d1205 ZW |
9974 | case T_MNEM_movs: |
9975 | /* We know we have low registers at this point. | |
9976 | Generate ADD Rd, Rs, #0. */ | |
9977 | inst.instruction = T_OPCODE_ADD_I3; | |
fdfde340 JM |
9978 | inst.instruction |= Rn; |
9979 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
9980 | break; |
9981 | ||
9982 | case T_MNEM_cmp: | |
3d388997 | 9983 | if (low_regs) |
c19d1205 ZW |
9984 | { |
9985 | inst.instruction = T_OPCODE_CMP_LR; | |
fdfde340 JM |
9986 | inst.instruction |= Rn; |
9987 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
9988 | } |
9989 | else | |
9990 | { | |
9991 | inst.instruction = T_OPCODE_CMP_HR; | |
fdfde340 JM |
9992 | inst.instruction |= (Rn & 0x8) << 4; |
9993 | inst.instruction |= (Rn & 0x7); | |
9994 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
9995 | } |
9996 | break; | |
9997 | } | |
b99bd4ef NC |
9998 | return; |
9999 | } | |
10000 | ||
c19d1205 ZW |
10001 | inst.instruction = THUMB_OP16 (inst.instruction); |
10002 | if (inst.operands[1].isreg) | |
b99bd4ef | 10003 | { |
fdfde340 | 10004 | if (Rn < 8 && Rm < 8) |
b99bd4ef | 10005 | { |
c19d1205 ZW |
10006 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
10007 | since a MOV instruction produces unpredictable results. */ | |
10008 | if (inst.instruction == T_OPCODE_MOV_I8) | |
10009 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 10010 | else |
c19d1205 | 10011 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 10012 | |
fdfde340 JM |
10013 | inst.instruction |= Rn; |
10014 | inst.instruction |= Rm << 3; | |
b99bd4ef NC |
10015 | } |
10016 | else | |
10017 | { | |
c19d1205 ZW |
10018 | if (inst.instruction == T_OPCODE_MOV_I8) |
10019 | inst.instruction = T_OPCODE_MOV_HR; | |
10020 | else | |
10021 | inst.instruction = T_OPCODE_CMP_HR; | |
10022 | do_t_cpy (); | |
b99bd4ef NC |
10023 | } |
10024 | } | |
c19d1205 | 10025 | else |
b99bd4ef | 10026 | { |
fdfde340 | 10027 | constraint (Rn > 7, |
c19d1205 | 10028 | _("only lo regs allowed with immediate")); |
fdfde340 | 10029 | inst.instruction |= Rn << 8; |
c19d1205 ZW |
10030 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; |
10031 | } | |
10032 | } | |
b99bd4ef | 10033 | |
c19d1205 ZW |
10034 | static void |
10035 | do_t_mov16 (void) | |
10036 | { | |
fdfde340 | 10037 | unsigned Rd; |
b6895b4f PB |
10038 | bfd_vma imm; |
10039 | bfd_boolean top; | |
10040 | ||
10041 | top = (inst.instruction & 0x00800000) != 0; | |
10042 | if (inst.reloc.type == BFD_RELOC_ARM_MOVW) | |
10043 | { | |
10044 | constraint (top, _(":lower16: not allowed this instruction")); | |
10045 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; | |
10046 | } | |
10047 | else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) | |
10048 | { | |
10049 | constraint (!top, _(":upper16: not allowed this instruction")); | |
10050 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; | |
10051 | } | |
10052 | ||
fdfde340 JM |
10053 | Rd = inst.operands[0].reg; |
10054 | reject_bad_reg (Rd); | |
10055 | ||
10056 | inst.instruction |= Rd << 8; | |
b6895b4f PB |
10057 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
10058 | { | |
10059 | imm = inst.reloc.exp.X_add_number; | |
10060 | inst.instruction |= (imm & 0xf000) << 4; | |
10061 | inst.instruction |= (imm & 0x0800) << 15; | |
10062 | inst.instruction |= (imm & 0x0700) << 4; | |
10063 | inst.instruction |= (imm & 0x00ff); | |
10064 | } | |
c19d1205 | 10065 | } |
b99bd4ef | 10066 | |
c19d1205 ZW |
10067 | static void |
10068 | do_t_mvn_tst (void) | |
10069 | { | |
fdfde340 JM |
10070 | unsigned Rn, Rm; |
10071 | ||
10072 | Rn = inst.operands[0].reg; | |
10073 | Rm = inst.operands[1].reg; | |
10074 | ||
10075 | if (inst.instruction == T_MNEM_cmp | |
10076 | || inst.instruction == T_MNEM_cmn) | |
10077 | constraint (Rn == REG_PC, BAD_PC); | |
10078 | else | |
10079 | reject_bad_reg (Rn); | |
10080 | reject_bad_reg (Rm); | |
10081 | ||
c19d1205 ZW |
10082 | if (unified_syntax) |
10083 | { | |
10084 | int r0off = (inst.instruction == T_MNEM_mvn | |
10085 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
10086 | bfd_boolean narrow; |
10087 | ||
10088 | if (inst.size_req == 4 | |
10089 | || inst.instruction > 0xffff | |
10090 | || inst.operands[1].shifted | |
fdfde340 | 10091 | || Rn > 7 || Rm > 7) |
3d388997 PB |
10092 | narrow = FALSE; |
10093 | else if (inst.instruction == T_MNEM_cmn) | |
10094 | narrow = TRUE; | |
10095 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 10096 | narrow = !in_it_block (); |
3d388997 | 10097 | else |
e07e6e58 | 10098 | narrow = in_it_block (); |
3d388997 | 10099 | |
c19d1205 | 10100 | if (!inst.operands[1].isreg) |
b99bd4ef | 10101 | { |
c19d1205 ZW |
10102 | /* For an immediate, we always generate a 32-bit opcode; |
10103 | section relaxation will shrink it later if possible. */ | |
10104 | if (inst.instruction < 0xffff) | |
10105 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10106 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 10107 | inst.instruction |= Rn << r0off; |
c19d1205 | 10108 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
b99bd4ef | 10109 | } |
c19d1205 | 10110 | else |
b99bd4ef | 10111 | { |
c19d1205 | 10112 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 10113 | if (narrow) |
b99bd4ef | 10114 | { |
c19d1205 | 10115 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
10116 | inst.instruction |= Rn; |
10117 | inst.instruction |= Rm << 3; | |
b99bd4ef | 10118 | } |
c19d1205 | 10119 | else |
b99bd4ef | 10120 | { |
c19d1205 ZW |
10121 | constraint (inst.operands[1].shifted |
10122 | && inst.operands[1].immisreg, | |
10123 | _("shift must be constant")); | |
10124 | if (inst.instruction < 0xffff) | |
10125 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 10126 | inst.instruction |= Rn << r0off; |
c19d1205 | 10127 | encode_thumb32_shifted_operand (1); |
b99bd4ef | 10128 | } |
b99bd4ef NC |
10129 | } |
10130 | } | |
10131 | else | |
10132 | { | |
c19d1205 ZW |
10133 | constraint (inst.instruction > 0xffff |
10134 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
10135 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
10136 | _("unshifted register required")); | |
fdfde340 | 10137 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 10138 | BAD_HIREG); |
b99bd4ef | 10139 | |
c19d1205 | 10140 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
10141 | inst.instruction |= Rn; |
10142 | inst.instruction |= Rm << 3; | |
b99bd4ef | 10143 | } |
b99bd4ef NC |
10144 | } |
10145 | ||
b05fe5cf | 10146 | static void |
c19d1205 | 10147 | do_t_mrs (void) |
b05fe5cf | 10148 | { |
fdfde340 | 10149 | unsigned Rd; |
62b3e311 | 10150 | int flags; |
037e8744 JB |
10151 | |
10152 | if (do_vfp_nsyn_mrs () == SUCCESS) | |
10153 | return; | |
10154 | ||
62b3e311 PB |
10155 | flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
10156 | if (flags == 0) | |
10157 | { | |
7e806470 | 10158 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m), |
62b3e311 PB |
10159 | _("selected processor does not support " |
10160 | "requested special purpose register")); | |
10161 | } | |
10162 | else | |
10163 | { | |
10164 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), | |
10165 | _("selected processor does not support " | |
44bf2362 | 10166 | "requested special purpose register")); |
62b3e311 PB |
10167 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ |
10168 | constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), | |
10169 | _("'CPSR' or 'SPSR' expected")); | |
10170 | } | |
5f4273c7 | 10171 | |
fdfde340 JM |
10172 | Rd = inst.operands[0].reg; |
10173 | reject_bad_reg (Rd); | |
10174 | ||
10175 | inst.instruction |= Rd << 8; | |
62b3e311 PB |
10176 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
10177 | inst.instruction |= inst.operands[1].imm & 0xff; | |
c19d1205 | 10178 | } |
b05fe5cf | 10179 | |
c19d1205 ZW |
10180 | static void |
10181 | do_t_msr (void) | |
10182 | { | |
62b3e311 | 10183 | int flags; |
fdfde340 | 10184 | unsigned Rn; |
62b3e311 | 10185 | |
037e8744 JB |
10186 | if (do_vfp_nsyn_msr () == SUCCESS) |
10187 | return; | |
10188 | ||
c19d1205 ZW |
10189 | constraint (!inst.operands[1].isreg, |
10190 | _("Thumb encoding does not support an immediate here")); | |
62b3e311 PB |
10191 | flags = inst.operands[0].imm; |
10192 | if (flags & ~0xff) | |
10193 | { | |
10194 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), | |
10195 | _("selected processor does not support " | |
10196 | "requested special purpose register")); | |
10197 | } | |
10198 | else | |
10199 | { | |
7e806470 | 10200 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m), |
62b3e311 PB |
10201 | _("selected processor does not support " |
10202 | "requested special purpose register")); | |
10203 | flags |= PSR_f; | |
10204 | } | |
fdfde340 JM |
10205 | |
10206 | Rn = inst.operands[1].reg; | |
10207 | reject_bad_reg (Rn); | |
10208 | ||
62b3e311 PB |
10209 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
10210 | inst.instruction |= (flags & ~SPSR_BIT) >> 8; | |
10211 | inst.instruction |= (flags & 0xff); | |
fdfde340 | 10212 | inst.instruction |= Rn << 16; |
c19d1205 | 10213 | } |
b05fe5cf | 10214 | |
c19d1205 ZW |
10215 | static void |
10216 | do_t_mul (void) | |
10217 | { | |
17828f45 | 10218 | bfd_boolean narrow; |
fdfde340 | 10219 | unsigned Rd, Rn, Rm; |
17828f45 | 10220 | |
c19d1205 ZW |
10221 | if (!inst.operands[2].present) |
10222 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 10223 | |
fdfde340 JM |
10224 | Rd = inst.operands[0].reg; |
10225 | Rn = inst.operands[1].reg; | |
10226 | Rm = inst.operands[2].reg; | |
10227 | ||
17828f45 | 10228 | if (unified_syntax) |
b05fe5cf | 10229 | { |
17828f45 | 10230 | if (inst.size_req == 4 |
fdfde340 JM |
10231 | || (Rd != Rn |
10232 | && Rd != Rm) | |
10233 | || Rn > 7 | |
10234 | || Rm > 7) | |
17828f45 JM |
10235 | narrow = FALSE; |
10236 | else if (inst.instruction == T_MNEM_muls) | |
e07e6e58 | 10237 | narrow = !in_it_block (); |
17828f45 | 10238 | else |
e07e6e58 | 10239 | narrow = in_it_block (); |
b05fe5cf | 10240 | } |
c19d1205 | 10241 | else |
b05fe5cf | 10242 | { |
17828f45 | 10243 | constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); |
fdfde340 | 10244 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 10245 | BAD_HIREG); |
17828f45 JM |
10246 | narrow = TRUE; |
10247 | } | |
b05fe5cf | 10248 | |
17828f45 JM |
10249 | if (narrow) |
10250 | { | |
10251 | /* 16-bit MULS/Conditional MUL. */ | |
c19d1205 | 10252 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 | 10253 | inst.instruction |= Rd; |
b05fe5cf | 10254 | |
fdfde340 JM |
10255 | if (Rd == Rn) |
10256 | inst.instruction |= Rm << 3; | |
10257 | else if (Rd == Rm) | |
10258 | inst.instruction |= Rn << 3; | |
c19d1205 ZW |
10259 | else |
10260 | constraint (1, _("dest must overlap one source register")); | |
10261 | } | |
17828f45 JM |
10262 | else |
10263 | { | |
e07e6e58 NC |
10264 | constraint (inst.instruction != T_MNEM_mul, |
10265 | _("Thumb-2 MUL must not set flags")); | |
17828f45 JM |
10266 | /* 32-bit MUL. */ |
10267 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
10268 | inst.instruction |= Rd << 8; |
10269 | inst.instruction |= Rn << 16; | |
10270 | inst.instruction |= Rm << 0; | |
10271 | ||
10272 | reject_bad_reg (Rd); | |
10273 | reject_bad_reg (Rn); | |
10274 | reject_bad_reg (Rm); | |
17828f45 | 10275 | } |
c19d1205 | 10276 | } |
b05fe5cf | 10277 | |
c19d1205 ZW |
10278 | static void |
10279 | do_t_mull (void) | |
10280 | { | |
fdfde340 | 10281 | unsigned RdLo, RdHi, Rn, Rm; |
b05fe5cf | 10282 | |
fdfde340 JM |
10283 | RdLo = inst.operands[0].reg; |
10284 | RdHi = inst.operands[1].reg; | |
10285 | Rn = inst.operands[2].reg; | |
10286 | Rm = inst.operands[3].reg; | |
10287 | ||
10288 | reject_bad_reg (RdLo); | |
10289 | reject_bad_reg (RdHi); | |
10290 | reject_bad_reg (Rn); | |
10291 | reject_bad_reg (Rm); | |
10292 | ||
10293 | inst.instruction |= RdLo << 12; | |
10294 | inst.instruction |= RdHi << 8; | |
10295 | inst.instruction |= Rn << 16; | |
10296 | inst.instruction |= Rm; | |
10297 | ||
10298 | if (RdLo == RdHi) | |
c19d1205 ZW |
10299 | as_tsktsk (_("rdhi and rdlo must be different")); |
10300 | } | |
b05fe5cf | 10301 | |
c19d1205 ZW |
10302 | static void |
10303 | do_t_nop (void) | |
10304 | { | |
e07e6e58 NC |
10305 | set_it_insn_type (NEUTRAL_IT_INSN); |
10306 | ||
c19d1205 ZW |
10307 | if (unified_syntax) |
10308 | { | |
10309 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 10310 | { |
c19d1205 ZW |
10311 | inst.instruction = THUMB_OP32 (inst.instruction); |
10312 | inst.instruction |= inst.operands[0].imm; | |
10313 | } | |
10314 | else | |
10315 | { | |
bc2d1808 NC |
10316 | /* PR9722: Check for Thumb2 availability before |
10317 | generating a thumb2 nop instruction. */ | |
10318 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)) | |
10319 | { | |
10320 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10321 | inst.instruction |= inst.operands[0].imm << 4; | |
10322 | } | |
10323 | else | |
10324 | inst.instruction = 0x46c0; | |
c19d1205 ZW |
10325 | } |
10326 | } | |
10327 | else | |
10328 | { | |
10329 | constraint (inst.operands[0].present, | |
10330 | _("Thumb does not support NOP with hints")); | |
10331 | inst.instruction = 0x46c0; | |
10332 | } | |
10333 | } | |
b05fe5cf | 10334 | |
c19d1205 ZW |
10335 | static void |
10336 | do_t_neg (void) | |
10337 | { | |
10338 | if (unified_syntax) | |
10339 | { | |
3d388997 PB |
10340 | bfd_boolean narrow; |
10341 | ||
10342 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 10343 | narrow = !in_it_block (); |
3d388997 | 10344 | else |
e07e6e58 | 10345 | narrow = in_it_block (); |
3d388997 PB |
10346 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
10347 | narrow = FALSE; | |
10348 | if (inst.size_req == 4) | |
10349 | narrow = FALSE; | |
10350 | ||
10351 | if (!narrow) | |
c19d1205 ZW |
10352 | { |
10353 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10354 | inst.instruction |= inst.operands[0].reg << 8; | |
10355 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
10356 | } |
10357 | else | |
10358 | { | |
c19d1205 ZW |
10359 | inst.instruction = THUMB_OP16 (inst.instruction); |
10360 | inst.instruction |= inst.operands[0].reg; | |
10361 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
10362 | } |
10363 | } | |
10364 | else | |
10365 | { | |
c19d1205 ZW |
10366 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
10367 | BAD_HIREG); | |
10368 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
10369 | ||
10370 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10371 | inst.instruction |= inst.operands[0].reg; | |
10372 | inst.instruction |= inst.operands[1].reg << 3; | |
10373 | } | |
10374 | } | |
10375 | ||
1c444d06 JM |
10376 | static void |
10377 | do_t_orn (void) | |
10378 | { | |
10379 | unsigned Rd, Rn; | |
10380 | ||
10381 | Rd = inst.operands[0].reg; | |
10382 | Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; | |
10383 | ||
fdfde340 JM |
10384 | reject_bad_reg (Rd); |
10385 | /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ | |
10386 | reject_bad_reg (Rn); | |
10387 | ||
1c444d06 JM |
10388 | inst.instruction |= Rd << 8; |
10389 | inst.instruction |= Rn << 16; | |
10390 | ||
10391 | if (!inst.operands[2].isreg) | |
10392 | { | |
10393 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
10394 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10395 | } | |
10396 | else | |
10397 | { | |
10398 | unsigned Rm; | |
10399 | ||
10400 | Rm = inst.operands[2].reg; | |
fdfde340 | 10401 | reject_bad_reg (Rm); |
1c444d06 JM |
10402 | |
10403 | constraint (inst.operands[2].shifted | |
10404 | && inst.operands[2].immisreg, | |
10405 | _("shift must be constant")); | |
10406 | encode_thumb32_shifted_operand (2); | |
10407 | } | |
10408 | } | |
10409 | ||
c19d1205 ZW |
10410 | static void |
10411 | do_t_pkhbt (void) | |
10412 | { | |
fdfde340 JM |
10413 | unsigned Rd, Rn, Rm; |
10414 | ||
10415 | Rd = inst.operands[0].reg; | |
10416 | Rn = inst.operands[1].reg; | |
10417 | Rm = inst.operands[2].reg; | |
10418 | ||
10419 | reject_bad_reg (Rd); | |
10420 | reject_bad_reg (Rn); | |
10421 | reject_bad_reg (Rm); | |
10422 | ||
10423 | inst.instruction |= Rd << 8; | |
10424 | inst.instruction |= Rn << 16; | |
10425 | inst.instruction |= Rm; | |
c19d1205 ZW |
10426 | if (inst.operands[3].present) |
10427 | { | |
10428 | unsigned int val = inst.reloc.exp.X_add_number; | |
10429 | constraint (inst.reloc.exp.X_op != O_constant, | |
10430 | _("expression too complex")); | |
10431 | inst.instruction |= (val & 0x1c) << 10; | |
10432 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 10433 | } |
c19d1205 | 10434 | } |
b05fe5cf | 10435 | |
c19d1205 ZW |
10436 | static void |
10437 | do_t_pkhtb (void) | |
10438 | { | |
10439 | if (!inst.operands[3].present) | |
10440 | inst.instruction &= ~0x00000020; | |
10441 | do_t_pkhbt (); | |
b05fe5cf ZW |
10442 | } |
10443 | ||
c19d1205 ZW |
10444 | static void |
10445 | do_t_pld (void) | |
10446 | { | |
fdfde340 JM |
10447 | if (inst.operands[0].immisreg) |
10448 | reject_bad_reg (inst.operands[0].imm); | |
10449 | ||
c19d1205 ZW |
10450 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); |
10451 | } | |
b05fe5cf | 10452 | |
c19d1205 ZW |
10453 | static void |
10454 | do_t_push_pop (void) | |
b99bd4ef | 10455 | { |
e9f89963 | 10456 | unsigned mask; |
5f4273c7 | 10457 | |
c19d1205 ZW |
10458 | constraint (inst.operands[0].writeback, |
10459 | _("push/pop do not support {reglist}^")); | |
10460 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
10461 | _("expression too complex")); | |
b99bd4ef | 10462 | |
e9f89963 PB |
10463 | mask = inst.operands[0].imm; |
10464 | if ((mask & ~0xff) == 0) | |
3c707909 | 10465 | inst.instruction = THUMB_OP16 (inst.instruction) | mask; |
c19d1205 | 10466 | else if ((inst.instruction == T_MNEM_push |
e9f89963 | 10467 | && (mask & ~0xff) == 1 << REG_LR) |
c19d1205 | 10468 | || (inst.instruction == T_MNEM_pop |
e9f89963 | 10469 | && (mask & ~0xff) == 1 << REG_PC)) |
b99bd4ef | 10470 | { |
c19d1205 ZW |
10471 | inst.instruction = THUMB_OP16 (inst.instruction); |
10472 | inst.instruction |= THUMB_PP_PC_LR; | |
3c707909 | 10473 | inst.instruction |= mask & 0xff; |
c19d1205 ZW |
10474 | } |
10475 | else if (unified_syntax) | |
10476 | { | |
3c707909 | 10477 | inst.instruction = THUMB_OP32 (inst.instruction); |
5f4273c7 | 10478 | encode_thumb2_ldmstm (13, mask, TRUE); |
c19d1205 ZW |
10479 | } |
10480 | else | |
10481 | { | |
10482 | inst.error = _("invalid register list to push/pop instruction"); | |
10483 | return; | |
10484 | } | |
c19d1205 | 10485 | } |
b99bd4ef | 10486 | |
c19d1205 ZW |
10487 | static void |
10488 | do_t_rbit (void) | |
10489 | { | |
fdfde340 JM |
10490 | unsigned Rd, Rm; |
10491 | ||
10492 | Rd = inst.operands[0].reg; | |
10493 | Rm = inst.operands[1].reg; | |
10494 | ||
10495 | reject_bad_reg (Rd); | |
10496 | reject_bad_reg (Rm); | |
10497 | ||
10498 | inst.instruction |= Rd << 8; | |
10499 | inst.instruction |= Rm << 16; | |
10500 | inst.instruction |= Rm; | |
c19d1205 | 10501 | } |
b99bd4ef | 10502 | |
c19d1205 ZW |
10503 | static void |
10504 | do_t_rev (void) | |
10505 | { | |
fdfde340 JM |
10506 | unsigned Rd, Rm; |
10507 | ||
10508 | Rd = inst.operands[0].reg; | |
10509 | Rm = inst.operands[1].reg; | |
10510 | ||
10511 | reject_bad_reg (Rd); | |
10512 | reject_bad_reg (Rm); | |
10513 | ||
10514 | if (Rd <= 7 && Rm <= 7 | |
c19d1205 ZW |
10515 | && inst.size_req != 4) |
10516 | { | |
10517 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 JM |
10518 | inst.instruction |= Rd; |
10519 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10520 | } |
10521 | else if (unified_syntax) | |
10522 | { | |
10523 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
10524 | inst.instruction |= Rd << 8; |
10525 | inst.instruction |= Rm << 16; | |
10526 | inst.instruction |= Rm; | |
c19d1205 ZW |
10527 | } |
10528 | else | |
10529 | inst.error = BAD_HIREG; | |
10530 | } | |
b99bd4ef | 10531 | |
1c444d06 JM |
10532 | static void |
10533 | do_t_rrx (void) | |
10534 | { | |
10535 | unsigned Rd, Rm; | |
10536 | ||
10537 | Rd = inst.operands[0].reg; | |
10538 | Rm = inst.operands[1].reg; | |
10539 | ||
fdfde340 JM |
10540 | reject_bad_reg (Rd); |
10541 | reject_bad_reg (Rm); | |
10542 | ||
1c444d06 JM |
10543 | inst.instruction |= Rd << 8; |
10544 | inst.instruction |= Rm; | |
10545 | } | |
10546 | ||
c19d1205 ZW |
10547 | static void |
10548 | do_t_rsb (void) | |
10549 | { | |
fdfde340 | 10550 | unsigned Rd, Rs; |
b99bd4ef | 10551 | |
c19d1205 ZW |
10552 | Rd = inst.operands[0].reg; |
10553 | Rs = (inst.operands[1].present | |
10554 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
10555 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 10556 | |
fdfde340 JM |
10557 | reject_bad_reg (Rd); |
10558 | reject_bad_reg (Rs); | |
10559 | if (inst.operands[2].isreg) | |
10560 | reject_bad_reg (inst.operands[2].reg); | |
10561 | ||
c19d1205 ZW |
10562 | inst.instruction |= Rd << 8; |
10563 | inst.instruction |= Rs << 16; | |
10564 | if (!inst.operands[2].isreg) | |
10565 | { | |
026d3abb PB |
10566 | bfd_boolean narrow; |
10567 | ||
10568 | if ((inst.instruction & 0x00100000) != 0) | |
e07e6e58 | 10569 | narrow = !in_it_block (); |
026d3abb | 10570 | else |
e07e6e58 | 10571 | narrow = in_it_block (); |
026d3abb PB |
10572 | |
10573 | if (Rd > 7 || Rs > 7) | |
10574 | narrow = FALSE; | |
10575 | ||
10576 | if (inst.size_req == 4 || !unified_syntax) | |
10577 | narrow = FALSE; | |
10578 | ||
10579 | if (inst.reloc.exp.X_op != O_constant | |
10580 | || inst.reloc.exp.X_add_number != 0) | |
10581 | narrow = FALSE; | |
10582 | ||
10583 | /* Turn rsb #0 into 16-bit neg. We should probably do this via | |
10584 | relaxation, but it doesn't seem worth the hassle. */ | |
10585 | if (narrow) | |
10586 | { | |
10587 | inst.reloc.type = BFD_RELOC_UNUSED; | |
10588 | inst.instruction = THUMB_OP16 (T_MNEM_negs); | |
10589 | inst.instruction |= Rs << 3; | |
10590 | inst.instruction |= Rd; | |
10591 | } | |
10592 | else | |
10593 | { | |
10594 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
10595 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10596 | } | |
c19d1205 ZW |
10597 | } |
10598 | else | |
10599 | encode_thumb32_shifted_operand (2); | |
10600 | } | |
b99bd4ef | 10601 | |
c19d1205 ZW |
10602 | static void |
10603 | do_t_setend (void) | |
10604 | { | |
e07e6e58 | 10605 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
10606 | if (inst.operands[0].imm) |
10607 | inst.instruction |= 0x8; | |
10608 | } | |
b99bd4ef | 10609 | |
c19d1205 ZW |
10610 | static void |
10611 | do_t_shift (void) | |
10612 | { | |
10613 | if (!inst.operands[1].present) | |
10614 | inst.operands[1].reg = inst.operands[0].reg; | |
10615 | ||
10616 | if (unified_syntax) | |
10617 | { | |
3d388997 PB |
10618 | bfd_boolean narrow; |
10619 | int shift_kind; | |
10620 | ||
10621 | switch (inst.instruction) | |
10622 | { | |
10623 | case T_MNEM_asr: | |
10624 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
10625 | case T_MNEM_lsl: | |
10626 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
10627 | case T_MNEM_lsr: | |
10628 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
10629 | case T_MNEM_ror: | |
10630 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
10631 | default: abort (); | |
10632 | } | |
10633 | ||
10634 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 10635 | narrow = !in_it_block (); |
3d388997 | 10636 | else |
e07e6e58 | 10637 | narrow = in_it_block (); |
3d388997 PB |
10638 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
10639 | narrow = FALSE; | |
10640 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
10641 | narrow = FALSE; | |
10642 | if (inst.operands[2].isreg | |
10643 | && (inst.operands[1].reg != inst.operands[0].reg | |
10644 | || inst.operands[2].reg > 7)) | |
10645 | narrow = FALSE; | |
10646 | if (inst.size_req == 4) | |
10647 | narrow = FALSE; | |
10648 | ||
fdfde340 JM |
10649 | reject_bad_reg (inst.operands[0].reg); |
10650 | reject_bad_reg (inst.operands[1].reg); | |
10651 | ||
3d388997 | 10652 | if (!narrow) |
c19d1205 ZW |
10653 | { |
10654 | if (inst.operands[2].isreg) | |
b99bd4ef | 10655 | { |
fdfde340 | 10656 | reject_bad_reg (inst.operands[2].reg); |
c19d1205 ZW |
10657 | inst.instruction = THUMB_OP32 (inst.instruction); |
10658 | inst.instruction |= inst.operands[0].reg << 8; | |
10659 | inst.instruction |= inst.operands[1].reg << 16; | |
10660 | inst.instruction |= inst.operands[2].reg; | |
10661 | } | |
10662 | else | |
10663 | { | |
10664 | inst.operands[1].shifted = 1; | |
3d388997 | 10665 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
10666 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
10667 | ? T_MNEM_movs : T_MNEM_mov); | |
10668 | inst.instruction |= inst.operands[0].reg << 8; | |
10669 | encode_thumb32_shifted_operand (1); | |
10670 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
10671 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef NC |
10672 | } |
10673 | } | |
10674 | else | |
10675 | { | |
c19d1205 | 10676 | if (inst.operands[2].isreg) |
b99bd4ef | 10677 | { |
3d388997 | 10678 | switch (shift_kind) |
b99bd4ef | 10679 | { |
3d388997 PB |
10680 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
10681 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
10682 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
10683 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 10684 | default: abort (); |
b99bd4ef | 10685 | } |
5f4273c7 | 10686 | |
c19d1205 ZW |
10687 | inst.instruction |= inst.operands[0].reg; |
10688 | inst.instruction |= inst.operands[2].reg << 3; | |
b99bd4ef NC |
10689 | } |
10690 | else | |
10691 | { | |
3d388997 | 10692 | switch (shift_kind) |
b99bd4ef | 10693 | { |
3d388997 PB |
10694 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
10695 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
10696 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 10697 | default: abort (); |
b99bd4ef | 10698 | } |
c19d1205 ZW |
10699 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
10700 | inst.instruction |= inst.operands[0].reg; | |
10701 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
10702 | } |
10703 | } | |
c19d1205 ZW |
10704 | } |
10705 | else | |
10706 | { | |
10707 | constraint (inst.operands[0].reg > 7 | |
10708 | || inst.operands[1].reg > 7, BAD_HIREG); | |
10709 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 10710 | |
c19d1205 ZW |
10711 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
10712 | { | |
10713 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
10714 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
10715 | _("source1 and dest must be same register")); | |
b99bd4ef | 10716 | |
c19d1205 ZW |
10717 | switch (inst.instruction) |
10718 | { | |
10719 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
10720 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
10721 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
10722 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
10723 | default: abort (); | |
10724 | } | |
5f4273c7 | 10725 | |
c19d1205 ZW |
10726 | inst.instruction |= inst.operands[0].reg; |
10727 | inst.instruction |= inst.operands[2].reg << 3; | |
10728 | } | |
10729 | else | |
b99bd4ef | 10730 | { |
c19d1205 ZW |
10731 | switch (inst.instruction) |
10732 | { | |
10733 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
10734 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
10735 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
10736 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
10737 | default: abort (); | |
10738 | } | |
10739 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
10740 | inst.instruction |= inst.operands[0].reg; | |
10741 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
10742 | } |
10743 | } | |
b99bd4ef NC |
10744 | } |
10745 | ||
10746 | static void | |
c19d1205 | 10747 | do_t_simd (void) |
b99bd4ef | 10748 | { |
fdfde340 JM |
10749 | unsigned Rd, Rn, Rm; |
10750 | ||
10751 | Rd = inst.operands[0].reg; | |
10752 | Rn = inst.operands[1].reg; | |
10753 | Rm = inst.operands[2].reg; | |
10754 | ||
10755 | reject_bad_reg (Rd); | |
10756 | reject_bad_reg (Rn); | |
10757 | reject_bad_reg (Rm); | |
10758 | ||
10759 | inst.instruction |= Rd << 8; | |
10760 | inst.instruction |= Rn << 16; | |
10761 | inst.instruction |= Rm; | |
c19d1205 | 10762 | } |
b99bd4ef | 10763 | |
c19d1205 | 10764 | static void |
3eb17e6b | 10765 | do_t_smc (void) |
c19d1205 ZW |
10766 | { |
10767 | unsigned int value = inst.reloc.exp.X_add_number; | |
10768 | constraint (inst.reloc.exp.X_op != O_constant, | |
10769 | _("expression too complex")); | |
10770 | inst.reloc.type = BFD_RELOC_UNUSED; | |
10771 | inst.instruction |= (value & 0xf000) >> 12; | |
10772 | inst.instruction |= (value & 0x0ff0); | |
10773 | inst.instruction |= (value & 0x000f) << 16; | |
10774 | } | |
b99bd4ef | 10775 | |
c19d1205 | 10776 | static void |
3a21c15a | 10777 | do_t_ssat_usat (int bias) |
c19d1205 | 10778 | { |
fdfde340 JM |
10779 | unsigned Rd, Rn; |
10780 | ||
10781 | Rd = inst.operands[0].reg; | |
10782 | Rn = inst.operands[2].reg; | |
10783 | ||
10784 | reject_bad_reg (Rd); | |
10785 | reject_bad_reg (Rn); | |
10786 | ||
10787 | inst.instruction |= Rd << 8; | |
3a21c15a | 10788 | inst.instruction |= inst.operands[1].imm - bias; |
fdfde340 | 10789 | inst.instruction |= Rn << 16; |
b99bd4ef | 10790 | |
c19d1205 | 10791 | if (inst.operands[3].present) |
b99bd4ef | 10792 | { |
3a21c15a NC |
10793 | offsetT shift_amount = inst.reloc.exp.X_add_number; |
10794 | ||
10795 | inst.reloc.type = BFD_RELOC_UNUSED; | |
10796 | ||
c19d1205 ZW |
10797 | constraint (inst.reloc.exp.X_op != O_constant, |
10798 | _("expression too complex")); | |
b99bd4ef | 10799 | |
3a21c15a | 10800 | if (shift_amount != 0) |
6189168b | 10801 | { |
3a21c15a NC |
10802 | constraint (shift_amount > 31, |
10803 | _("shift expression is too large")); | |
10804 | ||
c19d1205 | 10805 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
3a21c15a NC |
10806 | inst.instruction |= 0x00200000; /* sh bit. */ |
10807 | ||
10808 | inst.instruction |= (shift_amount & 0x1c) << 10; | |
10809 | inst.instruction |= (shift_amount & 0x03) << 6; | |
6189168b NC |
10810 | } |
10811 | } | |
b99bd4ef | 10812 | } |
3a21c15a NC |
10813 | |
10814 | static void | |
10815 | do_t_ssat (void) | |
10816 | { | |
10817 | do_t_ssat_usat (1); | |
10818 | } | |
b99bd4ef | 10819 | |
0dd132b6 | 10820 | static void |
c19d1205 | 10821 | do_t_ssat16 (void) |
0dd132b6 | 10822 | { |
fdfde340 JM |
10823 | unsigned Rd, Rn; |
10824 | ||
10825 | Rd = inst.operands[0].reg; | |
10826 | Rn = inst.operands[2].reg; | |
10827 | ||
10828 | reject_bad_reg (Rd); | |
10829 | reject_bad_reg (Rn); | |
10830 | ||
10831 | inst.instruction |= Rd << 8; | |
c19d1205 | 10832 | inst.instruction |= inst.operands[1].imm - 1; |
fdfde340 | 10833 | inst.instruction |= Rn << 16; |
c19d1205 | 10834 | } |
0dd132b6 | 10835 | |
c19d1205 ZW |
10836 | static void |
10837 | do_t_strex (void) | |
10838 | { | |
10839 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
10840 | || inst.operands[2].postind || inst.operands[2].writeback | |
10841 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
10842 | || inst.operands[2].negative, | |
01cfc07f | 10843 | BAD_ADDR_MODE); |
0dd132b6 | 10844 | |
c19d1205 ZW |
10845 | inst.instruction |= inst.operands[0].reg << 8; |
10846 | inst.instruction |= inst.operands[1].reg << 12; | |
10847 | inst.instruction |= inst.operands[2].reg << 16; | |
10848 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
0dd132b6 NC |
10849 | } |
10850 | ||
b99bd4ef | 10851 | static void |
c19d1205 | 10852 | do_t_strexd (void) |
b99bd4ef | 10853 | { |
c19d1205 ZW |
10854 | if (!inst.operands[2].present) |
10855 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 10856 | |
c19d1205 ZW |
10857 | constraint (inst.operands[0].reg == inst.operands[1].reg |
10858 | || inst.operands[0].reg == inst.operands[2].reg | |
10859 | || inst.operands[0].reg == inst.operands[3].reg | |
10860 | || inst.operands[1].reg == inst.operands[2].reg, | |
10861 | BAD_OVERLAP); | |
b99bd4ef | 10862 | |
c19d1205 ZW |
10863 | inst.instruction |= inst.operands[0].reg; |
10864 | inst.instruction |= inst.operands[1].reg << 12; | |
10865 | inst.instruction |= inst.operands[2].reg << 8; | |
10866 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
10867 | } |
10868 | ||
10869 | static void | |
c19d1205 | 10870 | do_t_sxtah (void) |
b99bd4ef | 10871 | { |
fdfde340 JM |
10872 | unsigned Rd, Rn, Rm; |
10873 | ||
10874 | Rd = inst.operands[0].reg; | |
10875 | Rn = inst.operands[1].reg; | |
10876 | Rm = inst.operands[2].reg; | |
10877 | ||
10878 | reject_bad_reg (Rd); | |
10879 | reject_bad_reg (Rn); | |
10880 | reject_bad_reg (Rm); | |
10881 | ||
10882 | inst.instruction |= Rd << 8; | |
10883 | inst.instruction |= Rn << 16; | |
10884 | inst.instruction |= Rm; | |
c19d1205 ZW |
10885 | inst.instruction |= inst.operands[3].imm << 4; |
10886 | } | |
b99bd4ef | 10887 | |
c19d1205 ZW |
10888 | static void |
10889 | do_t_sxth (void) | |
10890 | { | |
fdfde340 JM |
10891 | unsigned Rd, Rm; |
10892 | ||
10893 | Rd = inst.operands[0].reg; | |
10894 | Rm = inst.operands[1].reg; | |
10895 | ||
10896 | reject_bad_reg (Rd); | |
10897 | reject_bad_reg (Rm); | |
10898 | ||
c19d1205 | 10899 | if (inst.instruction <= 0xffff && inst.size_req != 4 |
fdfde340 | 10900 | && Rd <= 7 && Rm <= 7 |
c19d1205 | 10901 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) |
b99bd4ef | 10902 | { |
c19d1205 | 10903 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
10904 | inst.instruction |= Rd; |
10905 | inst.instruction |= Rm << 3; | |
b99bd4ef | 10906 | } |
c19d1205 | 10907 | else if (unified_syntax) |
b99bd4ef | 10908 | { |
c19d1205 ZW |
10909 | if (inst.instruction <= 0xffff) |
10910 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
10911 | inst.instruction |= Rd << 8; |
10912 | inst.instruction |= Rm; | |
c19d1205 | 10913 | inst.instruction |= inst.operands[2].imm << 4; |
b99bd4ef | 10914 | } |
c19d1205 | 10915 | else |
b99bd4ef | 10916 | { |
c19d1205 ZW |
10917 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
10918 | _("Thumb encoding does not support rotation")); | |
10919 | constraint (1, BAD_HIREG); | |
b99bd4ef | 10920 | } |
c19d1205 | 10921 | } |
b99bd4ef | 10922 | |
c19d1205 ZW |
10923 | static void |
10924 | do_t_swi (void) | |
10925 | { | |
10926 | inst.reloc.type = BFD_RELOC_ARM_SWI; | |
10927 | } | |
b99bd4ef | 10928 | |
92e90b6e PB |
10929 | static void |
10930 | do_t_tb (void) | |
10931 | { | |
fdfde340 | 10932 | unsigned Rn, Rm; |
92e90b6e PB |
10933 | int half; |
10934 | ||
10935 | half = (inst.instruction & 0x10) != 0; | |
e07e6e58 | 10936 | set_it_insn_type_last (); |
dfa9f0d5 PB |
10937 | constraint (inst.operands[0].immisreg, |
10938 | _("instruction requires register index")); | |
fdfde340 JM |
10939 | |
10940 | Rn = inst.operands[0].reg; | |
10941 | Rm = inst.operands[0].imm; | |
10942 | ||
10943 | constraint (Rn == REG_SP, BAD_SP); | |
10944 | reject_bad_reg (Rm); | |
10945 | ||
92e90b6e PB |
10946 | constraint (!half && inst.operands[0].shifted, |
10947 | _("instruction does not allow shifted index")); | |
fdfde340 | 10948 | inst.instruction |= (Rn << 16) | Rm; |
92e90b6e PB |
10949 | } |
10950 | ||
c19d1205 ZW |
10951 | static void |
10952 | do_t_usat (void) | |
10953 | { | |
3a21c15a | 10954 | do_t_ssat_usat (0); |
b99bd4ef NC |
10955 | } |
10956 | ||
10957 | static void | |
c19d1205 | 10958 | do_t_usat16 (void) |
b99bd4ef | 10959 | { |
fdfde340 JM |
10960 | unsigned Rd, Rn; |
10961 | ||
10962 | Rd = inst.operands[0].reg; | |
10963 | Rn = inst.operands[2].reg; | |
10964 | ||
10965 | reject_bad_reg (Rd); | |
10966 | reject_bad_reg (Rn); | |
10967 | ||
10968 | inst.instruction |= Rd << 8; | |
c19d1205 | 10969 | inst.instruction |= inst.operands[1].imm; |
fdfde340 | 10970 | inst.instruction |= Rn << 16; |
b99bd4ef | 10971 | } |
c19d1205 | 10972 | |
5287ad62 | 10973 | /* Neon instruction encoder helpers. */ |
5f4273c7 | 10974 | |
5287ad62 | 10975 | /* Encodings for the different types for various Neon opcodes. */ |
b99bd4ef | 10976 | |
5287ad62 JB |
10977 | /* An "invalid" code for the following tables. */ |
10978 | #define N_INV -1u | |
10979 | ||
10980 | struct neon_tab_entry | |
b99bd4ef | 10981 | { |
5287ad62 JB |
10982 | unsigned integer; |
10983 | unsigned float_or_poly; | |
10984 | unsigned scalar_or_imm; | |
10985 | }; | |
5f4273c7 | 10986 | |
5287ad62 JB |
10987 | /* Map overloaded Neon opcodes to their respective encodings. */ |
10988 | #define NEON_ENC_TAB \ | |
10989 | X(vabd, 0x0000700, 0x1200d00, N_INV), \ | |
10990 | X(vmax, 0x0000600, 0x0000f00, N_INV), \ | |
10991 | X(vmin, 0x0000610, 0x0200f00, N_INV), \ | |
10992 | X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ | |
10993 | X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ | |
10994 | X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ | |
10995 | X(vadd, 0x0000800, 0x0000d00, N_INV), \ | |
10996 | X(vsub, 0x1000800, 0x0200d00, N_INV), \ | |
10997 | X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ | |
10998 | X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ | |
10999 | X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ | |
11000 | /* Register variants of the following two instructions are encoded as | |
e07e6e58 | 11001 | vcge / vcgt with the operands reversed. */ \ |
92559b5b PB |
11002 | X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ |
11003 | X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ | |
5287ad62 JB |
11004 | X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ |
11005 | X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ | |
11006 | X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ | |
11007 | X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ | |
11008 | X(vmlal, 0x0800800, N_INV, 0x0800240), \ | |
11009 | X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ | |
11010 | X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ | |
11011 | X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ | |
11012 | X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ | |
11013 | X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ | |
11014 | X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ | |
11015 | X(vshl, 0x0000400, N_INV, 0x0800510), \ | |
11016 | X(vqshl, 0x0000410, N_INV, 0x0800710), \ | |
11017 | X(vand, 0x0000110, N_INV, 0x0800030), \ | |
11018 | X(vbic, 0x0100110, N_INV, 0x0800030), \ | |
11019 | X(veor, 0x1000110, N_INV, N_INV), \ | |
11020 | X(vorn, 0x0300110, N_INV, 0x0800010), \ | |
11021 | X(vorr, 0x0200110, N_INV, 0x0800010), \ | |
11022 | X(vmvn, 0x1b00580, N_INV, 0x0800030), \ | |
11023 | X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ | |
11024 | X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ | |
11025 | X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ | |
11026 | X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ | |
11027 | X(vst1, 0x0000000, 0x0800000, N_INV), \ | |
11028 | X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ | |
11029 | X(vst2, 0x0000100, 0x0800100, N_INV), \ | |
11030 | X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ | |
11031 | X(vst3, 0x0000200, 0x0800200, N_INV), \ | |
11032 | X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ | |
11033 | X(vst4, 0x0000300, 0x0800300, N_INV), \ | |
11034 | X(vmovn, 0x1b20200, N_INV, N_INV), \ | |
11035 | X(vtrn, 0x1b20080, N_INV, N_INV), \ | |
11036 | X(vqmovn, 0x1b20200, N_INV, N_INV), \ | |
037e8744 JB |
11037 | X(vqmovun, 0x1b20240, N_INV, N_INV), \ |
11038 | X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ | |
11039 | X(vnmla, 0xe000a40, 0xe000b40, N_INV), \ | |
11040 | X(vnmls, 0xe100a40, 0xe100b40, N_INV), \ | |
11041 | X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ | |
11042 | X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ | |
11043 | X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ | |
11044 | X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV) | |
5287ad62 JB |
11045 | |
11046 | enum neon_opc | |
11047 | { | |
11048 | #define X(OPC,I,F,S) N_MNEM_##OPC | |
11049 | NEON_ENC_TAB | |
11050 | #undef X | |
11051 | }; | |
b99bd4ef | 11052 | |
5287ad62 JB |
11053 | static const struct neon_tab_entry neon_enc_tab[] = |
11054 | { | |
11055 | #define X(OPC,I,F,S) { (I), (F), (S) } | |
11056 | NEON_ENC_TAB | |
11057 | #undef X | |
11058 | }; | |
b99bd4ef | 11059 | |
5287ad62 JB |
11060 | #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer) |
11061 | #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
11062 | #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
11063 | #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
11064 | #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
11065 | #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
11066 | #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
11067 | #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
11068 | #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
037e8744 JB |
11069 | #define NEON_ENC_SINGLE(X) \ |
11070 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) | |
11071 | #define NEON_ENC_DOUBLE(X) \ | |
11072 | ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) | |
5287ad62 | 11073 | |
037e8744 JB |
11074 | /* Define shapes for instruction operands. The following mnemonic characters |
11075 | are used in this table: | |
5287ad62 | 11076 | |
037e8744 | 11077 | F - VFP S<n> register |
5287ad62 JB |
11078 | D - Neon D<n> register |
11079 | Q - Neon Q<n> register | |
11080 | I - Immediate | |
11081 | S - Scalar | |
11082 | R - ARM register | |
11083 | L - D<n> register list | |
5f4273c7 | 11084 | |
037e8744 JB |
11085 | This table is used to generate various data: |
11086 | - enumerations of the form NS_DDR to be used as arguments to | |
11087 | neon_select_shape. | |
11088 | - a table classifying shapes into single, double, quad, mixed. | |
5f4273c7 | 11089 | - a table used to drive neon_select_shape. */ |
b99bd4ef | 11090 | |
037e8744 JB |
11091 | #define NEON_SHAPE_DEF \ |
11092 | X(3, (D, D, D), DOUBLE), \ | |
11093 | X(3, (Q, Q, Q), QUAD), \ | |
11094 | X(3, (D, D, I), DOUBLE), \ | |
11095 | X(3, (Q, Q, I), QUAD), \ | |
11096 | X(3, (D, D, S), DOUBLE), \ | |
11097 | X(3, (Q, Q, S), QUAD), \ | |
11098 | X(2, (D, D), DOUBLE), \ | |
11099 | X(2, (Q, Q), QUAD), \ | |
11100 | X(2, (D, S), DOUBLE), \ | |
11101 | X(2, (Q, S), QUAD), \ | |
11102 | X(2, (D, R), DOUBLE), \ | |
11103 | X(2, (Q, R), QUAD), \ | |
11104 | X(2, (D, I), DOUBLE), \ | |
11105 | X(2, (Q, I), QUAD), \ | |
11106 | X(3, (D, L, D), DOUBLE), \ | |
11107 | X(2, (D, Q), MIXED), \ | |
11108 | X(2, (Q, D), MIXED), \ | |
11109 | X(3, (D, Q, I), MIXED), \ | |
11110 | X(3, (Q, D, I), MIXED), \ | |
11111 | X(3, (Q, D, D), MIXED), \ | |
11112 | X(3, (D, Q, Q), MIXED), \ | |
11113 | X(3, (Q, Q, D), MIXED), \ | |
11114 | X(3, (Q, D, S), MIXED), \ | |
11115 | X(3, (D, Q, S), MIXED), \ | |
11116 | X(4, (D, D, D, I), DOUBLE), \ | |
11117 | X(4, (Q, Q, Q, I), QUAD), \ | |
11118 | X(2, (F, F), SINGLE), \ | |
11119 | X(3, (F, F, F), SINGLE), \ | |
11120 | X(2, (F, I), SINGLE), \ | |
11121 | X(2, (F, D), MIXED), \ | |
11122 | X(2, (D, F), MIXED), \ | |
11123 | X(3, (F, F, I), MIXED), \ | |
11124 | X(4, (R, R, F, F), SINGLE), \ | |
11125 | X(4, (F, F, R, R), SINGLE), \ | |
11126 | X(3, (D, R, R), DOUBLE), \ | |
11127 | X(3, (R, R, D), DOUBLE), \ | |
11128 | X(2, (S, R), SINGLE), \ | |
11129 | X(2, (R, S), SINGLE), \ | |
11130 | X(2, (F, R), SINGLE), \ | |
11131 | X(2, (R, F), SINGLE) | |
11132 | ||
11133 | #define S2(A,B) NS_##A##B | |
11134 | #define S3(A,B,C) NS_##A##B##C | |
11135 | #define S4(A,B,C,D) NS_##A##B##C##D | |
11136 | ||
11137 | #define X(N, L, C) S##N L | |
11138 | ||
5287ad62 JB |
11139 | enum neon_shape |
11140 | { | |
037e8744 JB |
11141 | NEON_SHAPE_DEF, |
11142 | NS_NULL | |
5287ad62 | 11143 | }; |
b99bd4ef | 11144 | |
037e8744 JB |
11145 | #undef X |
11146 | #undef S2 | |
11147 | #undef S3 | |
11148 | #undef S4 | |
11149 | ||
11150 | enum neon_shape_class | |
11151 | { | |
11152 | SC_SINGLE, | |
11153 | SC_DOUBLE, | |
11154 | SC_QUAD, | |
11155 | SC_MIXED | |
11156 | }; | |
11157 | ||
11158 | #define X(N, L, C) SC_##C | |
11159 | ||
11160 | static enum neon_shape_class neon_shape_class[] = | |
11161 | { | |
11162 | NEON_SHAPE_DEF | |
11163 | }; | |
11164 | ||
11165 | #undef X | |
11166 | ||
11167 | enum neon_shape_el | |
11168 | { | |
11169 | SE_F, | |
11170 | SE_D, | |
11171 | SE_Q, | |
11172 | SE_I, | |
11173 | SE_S, | |
11174 | SE_R, | |
11175 | SE_L | |
11176 | }; | |
11177 | ||
11178 | /* Register widths of above. */ | |
11179 | static unsigned neon_shape_el_size[] = | |
11180 | { | |
11181 | 32, | |
11182 | 64, | |
11183 | 128, | |
11184 | 0, | |
11185 | 32, | |
11186 | 32, | |
11187 | 0 | |
11188 | }; | |
11189 | ||
11190 | struct neon_shape_info | |
11191 | { | |
11192 | unsigned els; | |
11193 | enum neon_shape_el el[NEON_MAX_TYPE_ELS]; | |
11194 | }; | |
11195 | ||
11196 | #define S2(A,B) { SE_##A, SE_##B } | |
11197 | #define S3(A,B,C) { SE_##A, SE_##B, SE_##C } | |
11198 | #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } | |
11199 | ||
11200 | #define X(N, L, C) { N, S##N L } | |
11201 | ||
11202 | static struct neon_shape_info neon_shape_tab[] = | |
11203 | { | |
11204 | NEON_SHAPE_DEF | |
11205 | }; | |
11206 | ||
11207 | #undef X | |
11208 | #undef S2 | |
11209 | #undef S3 | |
11210 | #undef S4 | |
11211 | ||
5287ad62 JB |
11212 | /* Bit masks used in type checking given instructions. |
11213 | 'N_EQK' means the type must be the same as (or based on in some way) the key | |
11214 | type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is | |
11215 | set, various other bits can be set as well in order to modify the meaning of | |
11216 | the type constraint. */ | |
11217 | ||
11218 | enum neon_type_mask | |
11219 | { | |
8e79c3df CM |
11220 | N_S8 = 0x0000001, |
11221 | N_S16 = 0x0000002, | |
11222 | N_S32 = 0x0000004, | |
11223 | N_S64 = 0x0000008, | |
11224 | N_U8 = 0x0000010, | |
11225 | N_U16 = 0x0000020, | |
11226 | N_U32 = 0x0000040, | |
11227 | N_U64 = 0x0000080, | |
11228 | N_I8 = 0x0000100, | |
11229 | N_I16 = 0x0000200, | |
11230 | N_I32 = 0x0000400, | |
11231 | N_I64 = 0x0000800, | |
11232 | N_8 = 0x0001000, | |
11233 | N_16 = 0x0002000, | |
11234 | N_32 = 0x0004000, | |
11235 | N_64 = 0x0008000, | |
11236 | N_P8 = 0x0010000, | |
11237 | N_P16 = 0x0020000, | |
11238 | N_F16 = 0x0040000, | |
11239 | N_F32 = 0x0080000, | |
11240 | N_F64 = 0x0100000, | |
11241 | N_KEY = 0x1000000, /* key element (main type specifier). */ | |
11242 | N_EQK = 0x2000000, /* given operand has the same type & size as the key. */ | |
11243 | N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ | |
11244 | N_DBL = 0x0000001, /* if N_EQK, this operand is twice the size. */ | |
11245 | N_HLF = 0x0000002, /* if N_EQK, this operand is half the size. */ | |
11246 | N_SGN = 0x0000004, /* if N_EQK, this operand is forced to be signed. */ | |
11247 | N_UNS = 0x0000008, /* if N_EQK, this operand is forced to be unsigned. */ | |
11248 | N_INT = 0x0000010, /* if N_EQK, this operand is forced to be integer. */ | |
11249 | N_FLT = 0x0000020, /* if N_EQK, this operand is forced to be float. */ | |
11250 | N_SIZ = 0x0000040, /* if N_EQK, this operand is forced to be size-only. */ | |
5287ad62 | 11251 | N_UTYP = 0, |
037e8744 | 11252 | N_MAX_NONSPECIAL = N_F64 |
5287ad62 JB |
11253 | }; |
11254 | ||
dcbf9037 JB |
11255 | #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) |
11256 | ||
5287ad62 JB |
11257 | #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) |
11258 | #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) | |
11259 | #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) | |
11260 | #define N_SUF_32 (N_SU_32 | N_F32) | |
11261 | #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) | |
11262 | #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) | |
11263 | ||
11264 | /* Pass this as the first type argument to neon_check_type to ignore types | |
11265 | altogether. */ | |
11266 | #define N_IGNORE_TYPE (N_KEY | N_EQK) | |
11267 | ||
037e8744 JB |
11268 | /* Select a "shape" for the current instruction (describing register types or |
11269 | sizes) from a list of alternatives. Return NS_NULL if the current instruction | |
11270 | doesn't fit. For non-polymorphic shapes, checking is usually done as a | |
11271 | function of operand parsing, so this function doesn't need to be called. | |
11272 | Shapes should be listed in order of decreasing length. */ | |
5287ad62 JB |
11273 | |
11274 | static enum neon_shape | |
037e8744 | 11275 | neon_select_shape (enum neon_shape shape, ...) |
5287ad62 | 11276 | { |
037e8744 JB |
11277 | va_list ap; |
11278 | enum neon_shape first_shape = shape; | |
5287ad62 JB |
11279 | |
11280 | /* Fix missing optional operands. FIXME: we don't know at this point how | |
11281 | many arguments we should have, so this makes the assumption that we have | |
11282 | > 1. This is true of all current Neon opcodes, I think, but may not be | |
11283 | true in the future. */ | |
11284 | if (!inst.operands[1].present) | |
11285 | inst.operands[1] = inst.operands[0]; | |
11286 | ||
037e8744 | 11287 | va_start (ap, shape); |
5f4273c7 | 11288 | |
037e8744 JB |
11289 | for (; shape != NS_NULL; shape = va_arg (ap, int)) |
11290 | { | |
11291 | unsigned j; | |
11292 | int matches = 1; | |
11293 | ||
11294 | for (j = 0; j < neon_shape_tab[shape].els; j++) | |
11295 | { | |
11296 | if (!inst.operands[j].present) | |
11297 | { | |
11298 | matches = 0; | |
11299 | break; | |
11300 | } | |
11301 | ||
11302 | switch (neon_shape_tab[shape].el[j]) | |
11303 | { | |
11304 | case SE_F: | |
11305 | if (!(inst.operands[j].isreg | |
11306 | && inst.operands[j].isvec | |
11307 | && inst.operands[j].issingle | |
11308 | && !inst.operands[j].isquad)) | |
11309 | matches = 0; | |
11310 | break; | |
11311 | ||
11312 | case SE_D: | |
11313 | if (!(inst.operands[j].isreg | |
11314 | && inst.operands[j].isvec | |
11315 | && !inst.operands[j].isquad | |
11316 | && !inst.operands[j].issingle)) | |
11317 | matches = 0; | |
11318 | break; | |
11319 | ||
11320 | case SE_R: | |
11321 | if (!(inst.operands[j].isreg | |
11322 | && !inst.operands[j].isvec)) | |
11323 | matches = 0; | |
11324 | break; | |
11325 | ||
11326 | case SE_Q: | |
11327 | if (!(inst.operands[j].isreg | |
11328 | && inst.operands[j].isvec | |
11329 | && inst.operands[j].isquad | |
11330 | && !inst.operands[j].issingle)) | |
11331 | matches = 0; | |
11332 | break; | |
11333 | ||
11334 | case SE_I: | |
11335 | if (!(!inst.operands[j].isreg | |
11336 | && !inst.operands[j].isscalar)) | |
11337 | matches = 0; | |
11338 | break; | |
11339 | ||
11340 | case SE_S: | |
11341 | if (!(!inst.operands[j].isreg | |
11342 | && inst.operands[j].isscalar)) | |
11343 | matches = 0; | |
11344 | break; | |
11345 | ||
11346 | case SE_L: | |
11347 | break; | |
11348 | } | |
11349 | } | |
11350 | if (matches) | |
5287ad62 | 11351 | break; |
037e8744 | 11352 | } |
5f4273c7 | 11353 | |
037e8744 | 11354 | va_end (ap); |
5287ad62 | 11355 | |
037e8744 JB |
11356 | if (shape == NS_NULL && first_shape != NS_NULL) |
11357 | first_error (_("invalid instruction shape")); | |
5287ad62 | 11358 | |
037e8744 JB |
11359 | return shape; |
11360 | } | |
5287ad62 | 11361 | |
037e8744 JB |
11362 | /* True if SHAPE is predominantly a quadword operation (most of the time, this |
11363 | means the Q bit should be set). */ | |
11364 | ||
11365 | static int | |
11366 | neon_quad (enum neon_shape shape) | |
11367 | { | |
11368 | return neon_shape_class[shape] == SC_QUAD; | |
5287ad62 | 11369 | } |
037e8744 | 11370 | |
5287ad62 JB |
11371 | static void |
11372 | neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, | |
11373 | unsigned *g_size) | |
11374 | { | |
11375 | /* Allow modification to be made to types which are constrained to be | |
11376 | based on the key element, based on bits set alongside N_EQK. */ | |
11377 | if ((typebits & N_EQK) != 0) | |
11378 | { | |
11379 | if ((typebits & N_HLF) != 0) | |
11380 | *g_size /= 2; | |
11381 | else if ((typebits & N_DBL) != 0) | |
11382 | *g_size *= 2; | |
11383 | if ((typebits & N_SGN) != 0) | |
11384 | *g_type = NT_signed; | |
11385 | else if ((typebits & N_UNS) != 0) | |
11386 | *g_type = NT_unsigned; | |
11387 | else if ((typebits & N_INT) != 0) | |
11388 | *g_type = NT_integer; | |
11389 | else if ((typebits & N_FLT) != 0) | |
11390 | *g_type = NT_float; | |
dcbf9037 JB |
11391 | else if ((typebits & N_SIZ) != 0) |
11392 | *g_type = NT_untyped; | |
5287ad62 JB |
11393 | } |
11394 | } | |
5f4273c7 | 11395 | |
5287ad62 JB |
11396 | /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" |
11397 | operand type, i.e. the single type specified in a Neon instruction when it | |
11398 | is the only one given. */ | |
11399 | ||
11400 | static struct neon_type_el | |
11401 | neon_type_promote (struct neon_type_el *key, unsigned thisarg) | |
11402 | { | |
11403 | struct neon_type_el dest = *key; | |
5f4273c7 | 11404 | |
5287ad62 | 11405 | assert ((thisarg & N_EQK) != 0); |
5f4273c7 | 11406 | |
5287ad62 JB |
11407 | neon_modify_type_size (thisarg, &dest.type, &dest.size); |
11408 | ||
11409 | return dest; | |
11410 | } | |
11411 | ||
11412 | /* Convert Neon type and size into compact bitmask representation. */ | |
11413 | ||
11414 | static enum neon_type_mask | |
11415 | type_chk_of_el_type (enum neon_el_type type, unsigned size) | |
11416 | { | |
11417 | switch (type) | |
11418 | { | |
11419 | case NT_untyped: | |
11420 | switch (size) | |
11421 | { | |
11422 | case 8: return N_8; | |
11423 | case 16: return N_16; | |
11424 | case 32: return N_32; | |
11425 | case 64: return N_64; | |
11426 | default: ; | |
11427 | } | |
11428 | break; | |
11429 | ||
11430 | case NT_integer: | |
11431 | switch (size) | |
11432 | { | |
11433 | case 8: return N_I8; | |
11434 | case 16: return N_I16; | |
11435 | case 32: return N_I32; | |
11436 | case 64: return N_I64; | |
11437 | default: ; | |
11438 | } | |
11439 | break; | |
11440 | ||
11441 | case NT_float: | |
037e8744 JB |
11442 | switch (size) |
11443 | { | |
8e79c3df | 11444 | case 16: return N_F16; |
037e8744 JB |
11445 | case 32: return N_F32; |
11446 | case 64: return N_F64; | |
11447 | default: ; | |
11448 | } | |
5287ad62 JB |
11449 | break; |
11450 | ||
11451 | case NT_poly: | |
11452 | switch (size) | |
11453 | { | |
11454 | case 8: return N_P8; | |
11455 | case 16: return N_P16; | |
11456 | default: ; | |
11457 | } | |
11458 | break; | |
11459 | ||
11460 | case NT_signed: | |
11461 | switch (size) | |
11462 | { | |
11463 | case 8: return N_S8; | |
11464 | case 16: return N_S16; | |
11465 | case 32: return N_S32; | |
11466 | case 64: return N_S64; | |
11467 | default: ; | |
11468 | } | |
11469 | break; | |
11470 | ||
11471 | case NT_unsigned: | |
11472 | switch (size) | |
11473 | { | |
11474 | case 8: return N_U8; | |
11475 | case 16: return N_U16; | |
11476 | case 32: return N_U32; | |
11477 | case 64: return N_U64; | |
11478 | default: ; | |
11479 | } | |
11480 | break; | |
11481 | ||
11482 | default: ; | |
11483 | } | |
5f4273c7 | 11484 | |
5287ad62 JB |
11485 | return N_UTYP; |
11486 | } | |
11487 | ||
11488 | /* Convert compact Neon bitmask type representation to a type and size. Only | |
11489 | handles the case where a single bit is set in the mask. */ | |
11490 | ||
dcbf9037 | 11491 | static int |
5287ad62 JB |
11492 | el_type_of_type_chk (enum neon_el_type *type, unsigned *size, |
11493 | enum neon_type_mask mask) | |
11494 | { | |
dcbf9037 JB |
11495 | if ((mask & N_EQK) != 0) |
11496 | return FAIL; | |
11497 | ||
5287ad62 JB |
11498 | if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) |
11499 | *size = 8; | |
dcbf9037 | 11500 | else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0) |
5287ad62 | 11501 | *size = 16; |
dcbf9037 | 11502 | else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) |
5287ad62 | 11503 | *size = 32; |
037e8744 | 11504 | else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0) |
5287ad62 | 11505 | *size = 64; |
dcbf9037 JB |
11506 | else |
11507 | return FAIL; | |
11508 | ||
5287ad62 JB |
11509 | if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) |
11510 | *type = NT_signed; | |
dcbf9037 | 11511 | else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) |
5287ad62 | 11512 | *type = NT_unsigned; |
dcbf9037 | 11513 | else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) |
5287ad62 | 11514 | *type = NT_integer; |
dcbf9037 | 11515 | else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) |
5287ad62 | 11516 | *type = NT_untyped; |
dcbf9037 | 11517 | else if ((mask & (N_P8 | N_P16)) != 0) |
5287ad62 | 11518 | *type = NT_poly; |
037e8744 | 11519 | else if ((mask & (N_F32 | N_F64)) != 0) |
5287ad62 | 11520 | *type = NT_float; |
dcbf9037 JB |
11521 | else |
11522 | return FAIL; | |
5f4273c7 | 11523 | |
dcbf9037 | 11524 | return SUCCESS; |
5287ad62 JB |
11525 | } |
11526 | ||
11527 | /* Modify a bitmask of allowed types. This is only needed for type | |
11528 | relaxation. */ | |
11529 | ||
11530 | static unsigned | |
11531 | modify_types_allowed (unsigned allowed, unsigned mods) | |
11532 | { | |
11533 | unsigned size; | |
11534 | enum neon_el_type type; | |
11535 | unsigned destmask; | |
11536 | int i; | |
5f4273c7 | 11537 | |
5287ad62 | 11538 | destmask = 0; |
5f4273c7 | 11539 | |
5287ad62 JB |
11540 | for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) |
11541 | { | |
dcbf9037 JB |
11542 | if (el_type_of_type_chk (&type, &size, allowed & i) == SUCCESS) |
11543 | { | |
11544 | neon_modify_type_size (mods, &type, &size); | |
11545 | destmask |= type_chk_of_el_type (type, size); | |
11546 | } | |
5287ad62 | 11547 | } |
5f4273c7 | 11548 | |
5287ad62 JB |
11549 | return destmask; |
11550 | } | |
11551 | ||
11552 | /* Check type and return type classification. | |
11553 | The manual states (paraphrase): If one datatype is given, it indicates the | |
11554 | type given in: | |
11555 | - the second operand, if there is one | |
11556 | - the operand, if there is no second operand | |
11557 | - the result, if there are no operands. | |
11558 | This isn't quite good enough though, so we use a concept of a "key" datatype | |
11559 | which is set on a per-instruction basis, which is the one which matters when | |
11560 | only one data type is written. | |
11561 | Note: this function has side-effects (e.g. filling in missing operands). All | |
037e8744 | 11562 | Neon instructions should call it before performing bit encoding. */ |
5287ad62 JB |
11563 | |
11564 | static struct neon_type_el | |
11565 | neon_check_type (unsigned els, enum neon_shape ns, ...) | |
11566 | { | |
11567 | va_list ap; | |
11568 | unsigned i, pass, key_el = 0; | |
11569 | unsigned types[NEON_MAX_TYPE_ELS]; | |
11570 | enum neon_el_type k_type = NT_invtype; | |
11571 | unsigned k_size = -1u; | |
11572 | struct neon_type_el badtype = {NT_invtype, -1}; | |
11573 | unsigned key_allowed = 0; | |
11574 | ||
11575 | /* Optional registers in Neon instructions are always (not) in operand 1. | |
11576 | Fill in the missing operand here, if it was omitted. */ | |
11577 | if (els > 1 && !inst.operands[1].present) | |
11578 | inst.operands[1] = inst.operands[0]; | |
11579 | ||
11580 | /* Suck up all the varargs. */ | |
11581 | va_start (ap, ns); | |
11582 | for (i = 0; i < els; i++) | |
11583 | { | |
11584 | unsigned thisarg = va_arg (ap, unsigned); | |
11585 | if (thisarg == N_IGNORE_TYPE) | |
11586 | { | |
11587 | va_end (ap); | |
11588 | return badtype; | |
11589 | } | |
11590 | types[i] = thisarg; | |
11591 | if ((thisarg & N_KEY) != 0) | |
11592 | key_el = i; | |
11593 | } | |
11594 | va_end (ap); | |
11595 | ||
dcbf9037 JB |
11596 | if (inst.vectype.elems > 0) |
11597 | for (i = 0; i < els; i++) | |
11598 | if (inst.operands[i].vectype.type != NT_invtype) | |
11599 | { | |
11600 | first_error (_("types specified in both the mnemonic and operands")); | |
11601 | return badtype; | |
11602 | } | |
11603 | ||
5287ad62 JB |
11604 | /* Duplicate inst.vectype elements here as necessary. |
11605 | FIXME: No idea if this is exactly the same as the ARM assembler, | |
11606 | particularly when an insn takes one register and one non-register | |
11607 | operand. */ | |
11608 | if (inst.vectype.elems == 1 && els > 1) | |
11609 | { | |
11610 | unsigned j; | |
11611 | inst.vectype.elems = els; | |
11612 | inst.vectype.el[key_el] = inst.vectype.el[0]; | |
11613 | for (j = 0; j < els; j++) | |
dcbf9037 JB |
11614 | if (j != key_el) |
11615 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
11616 | types[j]); | |
11617 | } | |
11618 | else if (inst.vectype.elems == 0 && els > 0) | |
11619 | { | |
11620 | unsigned j; | |
11621 | /* No types were given after the mnemonic, so look for types specified | |
11622 | after each operand. We allow some flexibility here; as long as the | |
11623 | "key" operand has a type, we can infer the others. */ | |
11624 | for (j = 0; j < els; j++) | |
11625 | if (inst.operands[j].vectype.type != NT_invtype) | |
11626 | inst.vectype.el[j] = inst.operands[j].vectype; | |
11627 | ||
11628 | if (inst.operands[key_el].vectype.type != NT_invtype) | |
5287ad62 | 11629 | { |
dcbf9037 JB |
11630 | for (j = 0; j < els; j++) |
11631 | if (inst.operands[j].vectype.type == NT_invtype) | |
11632 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
11633 | types[j]); | |
11634 | } | |
11635 | else | |
11636 | { | |
11637 | first_error (_("operand types can't be inferred")); | |
11638 | return badtype; | |
5287ad62 JB |
11639 | } |
11640 | } | |
11641 | else if (inst.vectype.elems != els) | |
11642 | { | |
dcbf9037 | 11643 | first_error (_("type specifier has the wrong number of parts")); |
5287ad62 JB |
11644 | return badtype; |
11645 | } | |
11646 | ||
11647 | for (pass = 0; pass < 2; pass++) | |
11648 | { | |
11649 | for (i = 0; i < els; i++) | |
11650 | { | |
11651 | unsigned thisarg = types[i]; | |
11652 | unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) | |
11653 | ? modify_types_allowed (key_allowed, thisarg) : thisarg; | |
11654 | enum neon_el_type g_type = inst.vectype.el[i].type; | |
11655 | unsigned g_size = inst.vectype.el[i].size; | |
11656 | ||
11657 | /* Decay more-specific signed & unsigned types to sign-insensitive | |
11658 | integer types if sign-specific variants are unavailable. */ | |
11659 | if ((g_type == NT_signed || g_type == NT_unsigned) | |
11660 | && (types_allowed & N_SU_ALL) == 0) | |
11661 | g_type = NT_integer; | |
11662 | ||
11663 | /* If only untyped args are allowed, decay any more specific types to | |
11664 | them. Some instructions only care about signs for some element | |
11665 | sizes, so handle that properly. */ | |
11666 | if ((g_size == 8 && (types_allowed & N_8) != 0) | |
11667 | || (g_size == 16 && (types_allowed & N_16) != 0) | |
11668 | || (g_size == 32 && (types_allowed & N_32) != 0) | |
11669 | || (g_size == 64 && (types_allowed & N_64) != 0)) | |
11670 | g_type = NT_untyped; | |
11671 | ||
11672 | if (pass == 0) | |
11673 | { | |
11674 | if ((thisarg & N_KEY) != 0) | |
11675 | { | |
11676 | k_type = g_type; | |
11677 | k_size = g_size; | |
11678 | key_allowed = thisarg & ~N_KEY; | |
11679 | } | |
11680 | } | |
11681 | else | |
11682 | { | |
037e8744 JB |
11683 | if ((thisarg & N_VFP) != 0) |
11684 | { | |
11685 | enum neon_shape_el regshape = neon_shape_tab[ns].el[i]; | |
11686 | unsigned regwidth = neon_shape_el_size[regshape], match; | |
11687 | ||
11688 | /* In VFP mode, operands must match register widths. If we | |
11689 | have a key operand, use its width, else use the width of | |
11690 | the current operand. */ | |
11691 | if (k_size != -1u) | |
11692 | match = k_size; | |
11693 | else | |
11694 | match = g_size; | |
11695 | ||
11696 | if (regwidth != match) | |
11697 | { | |
11698 | first_error (_("operand size must match register width")); | |
11699 | return badtype; | |
11700 | } | |
11701 | } | |
5f4273c7 | 11702 | |
5287ad62 JB |
11703 | if ((thisarg & N_EQK) == 0) |
11704 | { | |
11705 | unsigned given_type = type_chk_of_el_type (g_type, g_size); | |
11706 | ||
11707 | if ((given_type & types_allowed) == 0) | |
11708 | { | |
dcbf9037 | 11709 | first_error (_("bad type in Neon instruction")); |
5287ad62 JB |
11710 | return badtype; |
11711 | } | |
11712 | } | |
11713 | else | |
11714 | { | |
11715 | enum neon_el_type mod_k_type = k_type; | |
11716 | unsigned mod_k_size = k_size; | |
11717 | neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); | |
11718 | if (g_type != mod_k_type || g_size != mod_k_size) | |
11719 | { | |
dcbf9037 | 11720 | first_error (_("inconsistent types in Neon instruction")); |
5287ad62 JB |
11721 | return badtype; |
11722 | } | |
11723 | } | |
11724 | } | |
11725 | } | |
11726 | } | |
11727 | ||
11728 | return inst.vectype.el[key_el]; | |
11729 | } | |
11730 | ||
037e8744 | 11731 | /* Neon-style VFP instruction forwarding. */ |
5287ad62 | 11732 | |
037e8744 JB |
11733 | /* Thumb VFP instructions have 0xE in the condition field. */ |
11734 | ||
11735 | static void | |
11736 | do_vfp_cond_or_thumb (void) | |
5287ad62 JB |
11737 | { |
11738 | if (thumb_mode) | |
037e8744 | 11739 | inst.instruction |= 0xe0000000; |
5287ad62 | 11740 | else |
037e8744 | 11741 | inst.instruction |= inst.cond << 28; |
5287ad62 JB |
11742 | } |
11743 | ||
037e8744 JB |
11744 | /* Look up and encode a simple mnemonic, for use as a helper function for the |
11745 | Neon-style VFP syntax. This avoids duplication of bits of the insns table, | |
11746 | etc. It is assumed that operand parsing has already been done, and that the | |
11747 | operands are in the form expected by the given opcode (this isn't necessarily | |
11748 | the same as the form in which they were parsed, hence some massaging must | |
11749 | take place before this function is called). | |
11750 | Checks current arch version against that in the looked-up opcode. */ | |
5287ad62 | 11751 | |
037e8744 JB |
11752 | static void |
11753 | do_vfp_nsyn_opcode (const char *opname) | |
5287ad62 | 11754 | { |
037e8744 | 11755 | const struct asm_opcode *opcode; |
5f4273c7 | 11756 | |
037e8744 | 11757 | opcode = hash_find (arm_ops_hsh, opname); |
5287ad62 | 11758 | |
037e8744 JB |
11759 | if (!opcode) |
11760 | abort (); | |
5287ad62 | 11761 | |
037e8744 JB |
11762 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, |
11763 | thumb_mode ? *opcode->tvariant : *opcode->avariant), | |
11764 | _(BAD_FPU)); | |
5287ad62 | 11765 | |
037e8744 JB |
11766 | if (thumb_mode) |
11767 | { | |
11768 | inst.instruction = opcode->tvalue; | |
11769 | opcode->tencode (); | |
11770 | } | |
11771 | else | |
11772 | { | |
11773 | inst.instruction = (inst.cond << 28) | opcode->avalue; | |
11774 | opcode->aencode (); | |
11775 | } | |
11776 | } | |
5287ad62 JB |
11777 | |
11778 | static void | |
037e8744 | 11779 | do_vfp_nsyn_add_sub (enum neon_shape rs) |
5287ad62 | 11780 | { |
037e8744 JB |
11781 | int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; |
11782 | ||
11783 | if (rs == NS_FFF) | |
11784 | { | |
11785 | if (is_add) | |
11786 | do_vfp_nsyn_opcode ("fadds"); | |
11787 | else | |
11788 | do_vfp_nsyn_opcode ("fsubs"); | |
11789 | } | |
11790 | else | |
11791 | { | |
11792 | if (is_add) | |
11793 | do_vfp_nsyn_opcode ("faddd"); | |
11794 | else | |
11795 | do_vfp_nsyn_opcode ("fsubd"); | |
11796 | } | |
11797 | } | |
11798 | ||
11799 | /* Check operand types to see if this is a VFP instruction, and if so call | |
11800 | PFN (). */ | |
11801 | ||
11802 | static int | |
11803 | try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) | |
11804 | { | |
11805 | enum neon_shape rs; | |
11806 | struct neon_type_el et; | |
11807 | ||
11808 | switch (args) | |
11809 | { | |
11810 | case 2: | |
11811 | rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
11812 | et = neon_check_type (2, rs, | |
11813 | N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
11814 | break; | |
5f4273c7 | 11815 | |
037e8744 JB |
11816 | case 3: |
11817 | rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
11818 | et = neon_check_type (3, rs, | |
11819 | N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
11820 | break; | |
11821 | ||
11822 | default: | |
11823 | abort (); | |
11824 | } | |
11825 | ||
11826 | if (et.type != NT_invtype) | |
11827 | { | |
11828 | pfn (rs); | |
11829 | return SUCCESS; | |
11830 | } | |
11831 | else | |
11832 | inst.error = NULL; | |
11833 | ||
11834 | return FAIL; | |
11835 | } | |
11836 | ||
11837 | static void | |
11838 | do_vfp_nsyn_mla_mls (enum neon_shape rs) | |
11839 | { | |
11840 | int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; | |
5f4273c7 | 11841 | |
037e8744 JB |
11842 | if (rs == NS_FFF) |
11843 | { | |
11844 | if (is_mla) | |
11845 | do_vfp_nsyn_opcode ("fmacs"); | |
11846 | else | |
11847 | do_vfp_nsyn_opcode ("fmscs"); | |
11848 | } | |
11849 | else | |
11850 | { | |
11851 | if (is_mla) | |
11852 | do_vfp_nsyn_opcode ("fmacd"); | |
11853 | else | |
11854 | do_vfp_nsyn_opcode ("fmscd"); | |
11855 | } | |
11856 | } | |
11857 | ||
11858 | static void | |
11859 | do_vfp_nsyn_mul (enum neon_shape rs) | |
11860 | { | |
11861 | if (rs == NS_FFF) | |
11862 | do_vfp_nsyn_opcode ("fmuls"); | |
11863 | else | |
11864 | do_vfp_nsyn_opcode ("fmuld"); | |
11865 | } | |
11866 | ||
11867 | static void | |
11868 | do_vfp_nsyn_abs_neg (enum neon_shape rs) | |
11869 | { | |
11870 | int is_neg = (inst.instruction & 0x80) != 0; | |
11871 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); | |
11872 | ||
11873 | if (rs == NS_FF) | |
11874 | { | |
11875 | if (is_neg) | |
11876 | do_vfp_nsyn_opcode ("fnegs"); | |
11877 | else | |
11878 | do_vfp_nsyn_opcode ("fabss"); | |
11879 | } | |
11880 | else | |
11881 | { | |
11882 | if (is_neg) | |
11883 | do_vfp_nsyn_opcode ("fnegd"); | |
11884 | else | |
11885 | do_vfp_nsyn_opcode ("fabsd"); | |
11886 | } | |
11887 | } | |
11888 | ||
11889 | /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision | |
11890 | insns belong to Neon, and are handled elsewhere. */ | |
11891 | ||
11892 | static void | |
11893 | do_vfp_nsyn_ldm_stm (int is_dbmode) | |
11894 | { | |
11895 | int is_ldm = (inst.instruction & (1 << 20)) != 0; | |
11896 | if (is_ldm) | |
11897 | { | |
11898 | if (is_dbmode) | |
11899 | do_vfp_nsyn_opcode ("fldmdbs"); | |
11900 | else | |
11901 | do_vfp_nsyn_opcode ("fldmias"); | |
11902 | } | |
11903 | else | |
11904 | { | |
11905 | if (is_dbmode) | |
11906 | do_vfp_nsyn_opcode ("fstmdbs"); | |
11907 | else | |
11908 | do_vfp_nsyn_opcode ("fstmias"); | |
11909 | } | |
11910 | } | |
11911 | ||
037e8744 JB |
11912 | static void |
11913 | do_vfp_nsyn_sqrt (void) | |
11914 | { | |
11915 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
11916 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 11917 | |
037e8744 JB |
11918 | if (rs == NS_FF) |
11919 | do_vfp_nsyn_opcode ("fsqrts"); | |
11920 | else | |
11921 | do_vfp_nsyn_opcode ("fsqrtd"); | |
11922 | } | |
11923 | ||
11924 | static void | |
11925 | do_vfp_nsyn_div (void) | |
11926 | { | |
11927 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
11928 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
11929 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 11930 | |
037e8744 JB |
11931 | if (rs == NS_FFF) |
11932 | do_vfp_nsyn_opcode ("fdivs"); | |
11933 | else | |
11934 | do_vfp_nsyn_opcode ("fdivd"); | |
11935 | } | |
11936 | ||
11937 | static void | |
11938 | do_vfp_nsyn_nmul (void) | |
11939 | { | |
11940 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
11941 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
11942 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 11943 | |
037e8744 JB |
11944 | if (rs == NS_FFF) |
11945 | { | |
11946 | inst.instruction = NEON_ENC_SINGLE (inst.instruction); | |
11947 | do_vfp_sp_dyadic (); | |
11948 | } | |
11949 | else | |
11950 | { | |
11951 | inst.instruction = NEON_ENC_DOUBLE (inst.instruction); | |
11952 | do_vfp_dp_rd_rn_rm (); | |
11953 | } | |
11954 | do_vfp_cond_or_thumb (); | |
11955 | } | |
11956 | ||
11957 | static void | |
11958 | do_vfp_nsyn_cmp (void) | |
11959 | { | |
11960 | if (inst.operands[1].isreg) | |
11961 | { | |
11962 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
11963 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 11964 | |
037e8744 JB |
11965 | if (rs == NS_FF) |
11966 | { | |
11967 | inst.instruction = NEON_ENC_SINGLE (inst.instruction); | |
11968 | do_vfp_sp_monadic (); | |
11969 | } | |
11970 | else | |
11971 | { | |
11972 | inst.instruction = NEON_ENC_DOUBLE (inst.instruction); | |
11973 | do_vfp_dp_rd_rm (); | |
11974 | } | |
11975 | } | |
11976 | else | |
11977 | { | |
11978 | enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); | |
11979 | neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); | |
11980 | ||
11981 | switch (inst.instruction & 0x0fffffff) | |
11982 | { | |
11983 | case N_MNEM_vcmp: | |
11984 | inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; | |
11985 | break; | |
11986 | case N_MNEM_vcmpe: | |
11987 | inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; | |
11988 | break; | |
11989 | default: | |
11990 | abort (); | |
11991 | } | |
5f4273c7 | 11992 | |
037e8744 JB |
11993 | if (rs == NS_FI) |
11994 | { | |
11995 | inst.instruction = NEON_ENC_SINGLE (inst.instruction); | |
11996 | do_vfp_sp_compare_z (); | |
11997 | } | |
11998 | else | |
11999 | { | |
12000 | inst.instruction = NEON_ENC_DOUBLE (inst.instruction); | |
12001 | do_vfp_dp_rd (); | |
12002 | } | |
12003 | } | |
12004 | do_vfp_cond_or_thumb (); | |
12005 | } | |
12006 | ||
12007 | static void | |
12008 | nsyn_insert_sp (void) | |
12009 | { | |
12010 | inst.operands[1] = inst.operands[0]; | |
12011 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
fdfde340 | 12012 | inst.operands[0].reg = REG_SP; |
037e8744 JB |
12013 | inst.operands[0].isreg = 1; |
12014 | inst.operands[0].writeback = 1; | |
12015 | inst.operands[0].present = 1; | |
12016 | } | |
12017 | ||
12018 | static void | |
12019 | do_vfp_nsyn_push (void) | |
12020 | { | |
12021 | nsyn_insert_sp (); | |
12022 | if (inst.operands[1].issingle) | |
12023 | do_vfp_nsyn_opcode ("fstmdbs"); | |
12024 | else | |
12025 | do_vfp_nsyn_opcode ("fstmdbd"); | |
12026 | } | |
12027 | ||
12028 | static void | |
12029 | do_vfp_nsyn_pop (void) | |
12030 | { | |
12031 | nsyn_insert_sp (); | |
12032 | if (inst.operands[1].issingle) | |
22b5b651 | 12033 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 | 12034 | else |
22b5b651 | 12035 | do_vfp_nsyn_opcode ("fldmiad"); |
037e8744 JB |
12036 | } |
12037 | ||
12038 | /* Fix up Neon data-processing instructions, ORing in the correct bits for | |
12039 | ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ | |
12040 | ||
12041 | static unsigned | |
12042 | neon_dp_fixup (unsigned i) | |
12043 | { | |
12044 | if (thumb_mode) | |
12045 | { | |
12046 | /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ | |
12047 | if (i & (1 << 24)) | |
12048 | i |= 1 << 28; | |
5f4273c7 | 12049 | |
037e8744 | 12050 | i &= ~(1 << 24); |
5f4273c7 | 12051 | |
037e8744 JB |
12052 | i |= 0xef000000; |
12053 | } | |
12054 | else | |
12055 | i |= 0xf2000000; | |
5f4273c7 | 12056 | |
037e8744 JB |
12057 | return i; |
12058 | } | |
12059 | ||
12060 | /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 | |
12061 | (0, 1, 2, 3). */ | |
12062 | ||
12063 | static unsigned | |
12064 | neon_logbits (unsigned x) | |
12065 | { | |
12066 | return ffs (x) - 4; | |
12067 | } | |
12068 | ||
12069 | #define LOW4(R) ((R) & 0xf) | |
12070 | #define HI1(R) (((R) >> 4) & 1) | |
12071 | ||
12072 | /* Encode insns with bit pattern: | |
12073 | ||
12074 | |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
12075 | | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | | |
5f4273c7 | 12076 | |
037e8744 JB |
12077 | SIZE is passed in bits. -1 means size field isn't changed, in case it has a |
12078 | different meaning for some instruction. */ | |
12079 | ||
12080 | static void | |
12081 | neon_three_same (int isquad, int ubit, int size) | |
12082 | { | |
12083 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12084 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12085 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
12086 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
12087 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
12088 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
12089 | inst.instruction |= (isquad != 0) << 6; | |
12090 | inst.instruction |= (ubit != 0) << 24; | |
12091 | if (size != -1) | |
12092 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 12093 | |
037e8744 JB |
12094 | inst.instruction = neon_dp_fixup (inst.instruction); |
12095 | } | |
12096 | ||
12097 | /* Encode instructions of the form: | |
12098 | ||
12099 | |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| | |
12100 | | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | | |
5287ad62 JB |
12101 | |
12102 | Don't write size if SIZE == -1. */ | |
12103 | ||
12104 | static void | |
12105 | neon_two_same (int qbit, int ubit, int size) | |
12106 | { | |
12107 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12108 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12109 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
12110 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
12111 | inst.instruction |= (qbit != 0) << 6; | |
12112 | inst.instruction |= (ubit != 0) << 24; | |
12113 | ||
12114 | if (size != -1) | |
12115 | inst.instruction |= neon_logbits (size) << 18; | |
12116 | ||
12117 | inst.instruction = neon_dp_fixup (inst.instruction); | |
12118 | } | |
12119 | ||
12120 | /* Neon instruction encoders, in approximate order of appearance. */ | |
12121 | ||
12122 | static void | |
12123 | do_neon_dyadic_i_su (void) | |
12124 | { | |
037e8744 | 12125 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12126 | struct neon_type_el et = neon_check_type (3, rs, |
12127 | N_EQK, N_EQK, N_SU_32 | N_KEY); | |
037e8744 | 12128 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
12129 | } |
12130 | ||
12131 | static void | |
12132 | do_neon_dyadic_i64_su (void) | |
12133 | { | |
037e8744 | 12134 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12135 | struct neon_type_el et = neon_check_type (3, rs, |
12136 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
037e8744 | 12137 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
12138 | } |
12139 | ||
12140 | static void | |
12141 | neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, | |
12142 | unsigned immbits) | |
12143 | { | |
12144 | unsigned size = et.size >> 3; | |
12145 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12146 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12147 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
12148 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
12149 | inst.instruction |= (isquad != 0) << 6; | |
12150 | inst.instruction |= immbits << 16; | |
12151 | inst.instruction |= (size >> 3) << 7; | |
12152 | inst.instruction |= (size & 0x7) << 19; | |
12153 | if (write_ubit) | |
12154 | inst.instruction |= (uval != 0) << 24; | |
12155 | ||
12156 | inst.instruction = neon_dp_fixup (inst.instruction); | |
12157 | } | |
12158 | ||
12159 | static void | |
12160 | do_neon_shl_imm (void) | |
12161 | { | |
12162 | if (!inst.operands[2].isreg) | |
12163 | { | |
037e8744 | 12164 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
12165 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); |
12166 | inst.instruction = NEON_ENC_IMMED (inst.instruction); | |
037e8744 | 12167 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm); |
5287ad62 JB |
12168 | } |
12169 | else | |
12170 | { | |
037e8744 | 12171 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12172 | struct neon_type_el et = neon_check_type (3, rs, |
12173 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
627907b7 JB |
12174 | unsigned int tmp; |
12175 | ||
12176 | /* VSHL/VQSHL 3-register variants have syntax such as: | |
12177 | vshl.xx Dd, Dm, Dn | |
12178 | whereas other 3-register operations encoded by neon_three_same have | |
12179 | syntax like: | |
12180 | vadd.xx Dd, Dn, Dm | |
12181 | (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg | |
12182 | here. */ | |
12183 | tmp = inst.operands[2].reg; | |
12184 | inst.operands[2].reg = inst.operands[1].reg; | |
12185 | inst.operands[1].reg = tmp; | |
5287ad62 | 12186 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); |
037e8744 | 12187 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
12188 | } |
12189 | } | |
12190 | ||
12191 | static void | |
12192 | do_neon_qshl_imm (void) | |
12193 | { | |
12194 | if (!inst.operands[2].isreg) | |
12195 | { | |
037e8744 | 12196 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 12197 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
627907b7 | 12198 | |
5287ad62 | 12199 | inst.instruction = NEON_ENC_IMMED (inst.instruction); |
037e8744 | 12200 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
12201 | inst.operands[2].imm); |
12202 | } | |
12203 | else | |
12204 | { | |
037e8744 | 12205 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12206 | struct neon_type_el et = neon_check_type (3, rs, |
12207 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
627907b7 JB |
12208 | unsigned int tmp; |
12209 | ||
12210 | /* See note in do_neon_shl_imm. */ | |
12211 | tmp = inst.operands[2].reg; | |
12212 | inst.operands[2].reg = inst.operands[1].reg; | |
12213 | inst.operands[1].reg = tmp; | |
5287ad62 | 12214 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); |
037e8744 | 12215 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
12216 | } |
12217 | } | |
12218 | ||
627907b7 JB |
12219 | static void |
12220 | do_neon_rshl (void) | |
12221 | { | |
12222 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
12223 | struct neon_type_el et = neon_check_type (3, rs, | |
12224 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
12225 | unsigned int tmp; | |
12226 | ||
12227 | tmp = inst.operands[2].reg; | |
12228 | inst.operands[2].reg = inst.operands[1].reg; | |
12229 | inst.operands[1].reg = tmp; | |
12230 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
12231 | } | |
12232 | ||
5287ad62 JB |
12233 | static int |
12234 | neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) | |
12235 | { | |
036dc3f7 PB |
12236 | /* Handle .I8 pseudo-instructions. */ |
12237 | if (size == 8) | |
5287ad62 | 12238 | { |
5287ad62 JB |
12239 | /* Unfortunately, this will make everything apart from zero out-of-range. |
12240 | FIXME is this the intended semantics? There doesn't seem much point in | |
12241 | accepting .I8 if so. */ | |
12242 | immediate |= immediate << 8; | |
12243 | size = 16; | |
036dc3f7 PB |
12244 | } |
12245 | ||
12246 | if (size >= 32) | |
12247 | { | |
12248 | if (immediate == (immediate & 0x000000ff)) | |
12249 | { | |
12250 | *immbits = immediate; | |
12251 | return 0x1; | |
12252 | } | |
12253 | else if (immediate == (immediate & 0x0000ff00)) | |
12254 | { | |
12255 | *immbits = immediate >> 8; | |
12256 | return 0x3; | |
12257 | } | |
12258 | else if (immediate == (immediate & 0x00ff0000)) | |
12259 | { | |
12260 | *immbits = immediate >> 16; | |
12261 | return 0x5; | |
12262 | } | |
12263 | else if (immediate == (immediate & 0xff000000)) | |
12264 | { | |
12265 | *immbits = immediate >> 24; | |
12266 | return 0x7; | |
12267 | } | |
12268 | if ((immediate & 0xffff) != (immediate >> 16)) | |
12269 | goto bad_immediate; | |
12270 | immediate &= 0xffff; | |
5287ad62 JB |
12271 | } |
12272 | ||
12273 | if (immediate == (immediate & 0x000000ff)) | |
12274 | { | |
12275 | *immbits = immediate; | |
036dc3f7 | 12276 | return 0x9; |
5287ad62 JB |
12277 | } |
12278 | else if (immediate == (immediate & 0x0000ff00)) | |
12279 | { | |
12280 | *immbits = immediate >> 8; | |
036dc3f7 | 12281 | return 0xb; |
5287ad62 JB |
12282 | } |
12283 | ||
12284 | bad_immediate: | |
dcbf9037 | 12285 | first_error (_("immediate value out of range")); |
5287ad62 JB |
12286 | return FAIL; |
12287 | } | |
12288 | ||
12289 | /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits | |
12290 | A, B, C, D. */ | |
12291 | ||
12292 | static int | |
12293 | neon_bits_same_in_bytes (unsigned imm) | |
12294 | { | |
12295 | return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) | |
12296 | && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) | |
12297 | && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) | |
12298 | && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); | |
12299 | } | |
12300 | ||
12301 | /* For immediate of above form, return 0bABCD. */ | |
12302 | ||
12303 | static unsigned | |
12304 | neon_squash_bits (unsigned imm) | |
12305 | { | |
12306 | return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) | |
12307 | | ((imm & 0x01000000) >> 21); | |
12308 | } | |
12309 | ||
136da414 | 12310 | /* Compress quarter-float representation to 0b...000 abcdefgh. */ |
5287ad62 JB |
12311 | |
12312 | static unsigned | |
12313 | neon_qfloat_bits (unsigned imm) | |
12314 | { | |
136da414 | 12315 | return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); |
5287ad62 JB |
12316 | } |
12317 | ||
12318 | /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into | |
12319 | the instruction. *OP is passed as the initial value of the op field, and | |
12320 | may be set to a different value depending on the constant (i.e. | |
12321 | "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not | |
5f4273c7 | 12322 | MVN). If the immediate looks like a repeated pattern then also |
036dc3f7 | 12323 | try smaller element sizes. */ |
5287ad62 JB |
12324 | |
12325 | static int | |
c96612cc JB |
12326 | neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, |
12327 | unsigned *immbits, int *op, int size, | |
12328 | enum neon_el_type type) | |
5287ad62 | 12329 | { |
c96612cc JB |
12330 | /* Only permit float immediates (including 0.0/-0.0) if the operand type is |
12331 | float. */ | |
12332 | if (type == NT_float && !float_p) | |
12333 | return FAIL; | |
12334 | ||
136da414 JB |
12335 | if (type == NT_float && is_quarter_float (immlo) && immhi == 0) |
12336 | { | |
12337 | if (size != 32 || *op == 1) | |
12338 | return FAIL; | |
12339 | *immbits = neon_qfloat_bits (immlo); | |
12340 | return 0xf; | |
12341 | } | |
036dc3f7 PB |
12342 | |
12343 | if (size == 64) | |
5287ad62 | 12344 | { |
036dc3f7 PB |
12345 | if (neon_bits_same_in_bytes (immhi) |
12346 | && neon_bits_same_in_bytes (immlo)) | |
12347 | { | |
12348 | if (*op == 1) | |
12349 | return FAIL; | |
12350 | *immbits = (neon_squash_bits (immhi) << 4) | |
12351 | | neon_squash_bits (immlo); | |
12352 | *op = 1; | |
12353 | return 0xe; | |
12354 | } | |
12355 | ||
12356 | if (immhi != immlo) | |
12357 | return FAIL; | |
5287ad62 | 12358 | } |
036dc3f7 PB |
12359 | |
12360 | if (size >= 32) | |
5287ad62 | 12361 | { |
036dc3f7 PB |
12362 | if (immlo == (immlo & 0x000000ff)) |
12363 | { | |
12364 | *immbits = immlo; | |
12365 | return 0x0; | |
12366 | } | |
12367 | else if (immlo == (immlo & 0x0000ff00)) | |
12368 | { | |
12369 | *immbits = immlo >> 8; | |
12370 | return 0x2; | |
12371 | } | |
12372 | else if (immlo == (immlo & 0x00ff0000)) | |
12373 | { | |
12374 | *immbits = immlo >> 16; | |
12375 | return 0x4; | |
12376 | } | |
12377 | else if (immlo == (immlo & 0xff000000)) | |
12378 | { | |
12379 | *immbits = immlo >> 24; | |
12380 | return 0x6; | |
12381 | } | |
12382 | else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) | |
12383 | { | |
12384 | *immbits = (immlo >> 8) & 0xff; | |
12385 | return 0xc; | |
12386 | } | |
12387 | else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) | |
12388 | { | |
12389 | *immbits = (immlo >> 16) & 0xff; | |
12390 | return 0xd; | |
12391 | } | |
12392 | ||
12393 | if ((immlo & 0xffff) != (immlo >> 16)) | |
12394 | return FAIL; | |
12395 | immlo &= 0xffff; | |
5287ad62 | 12396 | } |
036dc3f7 PB |
12397 | |
12398 | if (size >= 16) | |
5287ad62 | 12399 | { |
036dc3f7 PB |
12400 | if (immlo == (immlo & 0x000000ff)) |
12401 | { | |
12402 | *immbits = immlo; | |
12403 | return 0x8; | |
12404 | } | |
12405 | else if (immlo == (immlo & 0x0000ff00)) | |
12406 | { | |
12407 | *immbits = immlo >> 8; | |
12408 | return 0xa; | |
12409 | } | |
12410 | ||
12411 | if ((immlo & 0xff) != (immlo >> 8)) | |
12412 | return FAIL; | |
12413 | immlo &= 0xff; | |
5287ad62 | 12414 | } |
036dc3f7 PB |
12415 | |
12416 | if (immlo == (immlo & 0x000000ff)) | |
5287ad62 | 12417 | { |
036dc3f7 PB |
12418 | /* Don't allow MVN with 8-bit immediate. */ |
12419 | if (*op == 1) | |
12420 | return FAIL; | |
12421 | *immbits = immlo; | |
12422 | return 0xe; | |
5287ad62 | 12423 | } |
5287ad62 JB |
12424 | |
12425 | return FAIL; | |
12426 | } | |
12427 | ||
12428 | /* Write immediate bits [7:0] to the following locations: | |
12429 | ||
12430 | |28/24|23 19|18 16|15 4|3 0| | |
12431 | | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| | |
12432 | ||
12433 | This function is used by VMOV/VMVN/VORR/VBIC. */ | |
12434 | ||
12435 | static void | |
12436 | neon_write_immbits (unsigned immbits) | |
12437 | { | |
12438 | inst.instruction |= immbits & 0xf; | |
12439 | inst.instruction |= ((immbits >> 4) & 0x7) << 16; | |
12440 | inst.instruction |= ((immbits >> 7) & 0x1) << 24; | |
12441 | } | |
12442 | ||
12443 | /* Invert low-order SIZE bits of XHI:XLO. */ | |
12444 | ||
12445 | static void | |
12446 | neon_invert_size (unsigned *xlo, unsigned *xhi, int size) | |
12447 | { | |
12448 | unsigned immlo = xlo ? *xlo : 0; | |
12449 | unsigned immhi = xhi ? *xhi : 0; | |
12450 | ||
12451 | switch (size) | |
12452 | { | |
12453 | case 8: | |
12454 | immlo = (~immlo) & 0xff; | |
12455 | break; | |
12456 | ||
12457 | case 16: | |
12458 | immlo = (~immlo) & 0xffff; | |
12459 | break; | |
12460 | ||
12461 | case 64: | |
12462 | immhi = (~immhi) & 0xffffffff; | |
12463 | /* fall through. */ | |
12464 | ||
12465 | case 32: | |
12466 | immlo = (~immlo) & 0xffffffff; | |
12467 | break; | |
12468 | ||
12469 | default: | |
12470 | abort (); | |
12471 | } | |
12472 | ||
12473 | if (xlo) | |
12474 | *xlo = immlo; | |
12475 | ||
12476 | if (xhi) | |
12477 | *xhi = immhi; | |
12478 | } | |
12479 | ||
12480 | static void | |
12481 | do_neon_logic (void) | |
12482 | { | |
12483 | if (inst.operands[2].present && inst.operands[2].isreg) | |
12484 | { | |
037e8744 | 12485 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12486 | neon_check_type (3, rs, N_IGNORE_TYPE); |
12487 | /* U bit and size field were set as part of the bitmask. */ | |
12488 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
037e8744 | 12489 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
12490 | } |
12491 | else | |
12492 | { | |
037e8744 JB |
12493 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
12494 | struct neon_type_el et = neon_check_type (2, rs, | |
12495 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
5287ad62 JB |
12496 | enum neon_opc opcode = inst.instruction & 0x0fffffff; |
12497 | unsigned immbits; | |
12498 | int cmode; | |
5f4273c7 | 12499 | |
5287ad62 JB |
12500 | if (et.type == NT_invtype) |
12501 | return; | |
5f4273c7 | 12502 | |
5287ad62 JB |
12503 | inst.instruction = NEON_ENC_IMMED (inst.instruction); |
12504 | ||
036dc3f7 PB |
12505 | immbits = inst.operands[1].imm; |
12506 | if (et.size == 64) | |
12507 | { | |
12508 | /* .i64 is a pseudo-op, so the immediate must be a repeating | |
12509 | pattern. */ | |
12510 | if (immbits != (inst.operands[1].regisimm ? | |
12511 | inst.operands[1].reg : 0)) | |
12512 | { | |
12513 | /* Set immbits to an invalid constant. */ | |
12514 | immbits = 0xdeadbeef; | |
12515 | } | |
12516 | } | |
12517 | ||
5287ad62 JB |
12518 | switch (opcode) |
12519 | { | |
12520 | case N_MNEM_vbic: | |
036dc3f7 | 12521 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
5287ad62 | 12522 | break; |
5f4273c7 | 12523 | |
5287ad62 | 12524 | case N_MNEM_vorr: |
036dc3f7 | 12525 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
5287ad62 | 12526 | break; |
5f4273c7 | 12527 | |
5287ad62 JB |
12528 | case N_MNEM_vand: |
12529 | /* Pseudo-instruction for VBIC. */ | |
5287ad62 JB |
12530 | neon_invert_size (&immbits, 0, et.size); |
12531 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
12532 | break; | |
5f4273c7 | 12533 | |
5287ad62 JB |
12534 | case N_MNEM_vorn: |
12535 | /* Pseudo-instruction for VORR. */ | |
5287ad62 JB |
12536 | neon_invert_size (&immbits, 0, et.size); |
12537 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
12538 | break; | |
5f4273c7 | 12539 | |
5287ad62 JB |
12540 | default: |
12541 | abort (); | |
12542 | } | |
12543 | ||
12544 | if (cmode == FAIL) | |
12545 | return; | |
12546 | ||
037e8744 | 12547 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
12548 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
12549 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12550 | inst.instruction |= cmode << 8; | |
12551 | neon_write_immbits (immbits); | |
5f4273c7 | 12552 | |
5287ad62 JB |
12553 | inst.instruction = neon_dp_fixup (inst.instruction); |
12554 | } | |
12555 | } | |
12556 | ||
12557 | static void | |
12558 | do_neon_bitfield (void) | |
12559 | { | |
037e8744 | 12560 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 12561 | neon_check_type (3, rs, N_IGNORE_TYPE); |
037e8744 | 12562 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
12563 | } |
12564 | ||
12565 | static void | |
dcbf9037 JB |
12566 | neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, |
12567 | unsigned destbits) | |
5287ad62 | 12568 | { |
037e8744 | 12569 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 JB |
12570 | struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, |
12571 | types | N_KEY); | |
5287ad62 JB |
12572 | if (et.type == NT_float) |
12573 | { | |
12574 | inst.instruction = NEON_ENC_FLOAT (inst.instruction); | |
037e8744 | 12575 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
12576 | } |
12577 | else | |
12578 | { | |
12579 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
037e8744 | 12580 | neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); |
5287ad62 JB |
12581 | } |
12582 | } | |
12583 | ||
12584 | static void | |
12585 | do_neon_dyadic_if_su (void) | |
12586 | { | |
dcbf9037 | 12587 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
12588 | } |
12589 | ||
12590 | static void | |
12591 | do_neon_dyadic_if_su_d (void) | |
12592 | { | |
12593 | /* This version only allow D registers, but that constraint is enforced during | |
12594 | operand parsing so we don't need to do anything extra here. */ | |
dcbf9037 | 12595 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
12596 | } |
12597 | ||
5287ad62 JB |
12598 | static void |
12599 | do_neon_dyadic_if_i_d (void) | |
12600 | { | |
428e3f1f PB |
12601 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
12602 | affected if we specify unsigned args. */ | |
12603 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
5287ad62 JB |
12604 | } |
12605 | ||
037e8744 JB |
12606 | enum vfp_or_neon_is_neon_bits |
12607 | { | |
12608 | NEON_CHECK_CC = 1, | |
12609 | NEON_CHECK_ARCH = 2 | |
12610 | }; | |
12611 | ||
12612 | /* Call this function if an instruction which may have belonged to the VFP or | |
12613 | Neon instruction sets, but turned out to be a Neon instruction (due to the | |
12614 | operand types involved, etc.). We have to check and/or fix-up a couple of | |
12615 | things: | |
12616 | ||
12617 | - Make sure the user hasn't attempted to make a Neon instruction | |
12618 | conditional. | |
12619 | - Alter the value in the condition code field if necessary. | |
12620 | - Make sure that the arch supports Neon instructions. | |
12621 | ||
12622 | Which of these operations take place depends on bits from enum | |
12623 | vfp_or_neon_is_neon_bits. | |
12624 | ||
12625 | WARNING: This function has side effects! If NEON_CHECK_CC is used and the | |
12626 | current instruction's condition is COND_ALWAYS, the condition field is | |
12627 | changed to inst.uncond_value. This is necessary because instructions shared | |
12628 | between VFP and Neon may be conditional for the VFP variants only, and the | |
12629 | unconditional Neon version must have, e.g., 0xF in the condition field. */ | |
12630 | ||
12631 | static int | |
12632 | vfp_or_neon_is_neon (unsigned check) | |
12633 | { | |
12634 | /* Conditions are always legal in Thumb mode (IT blocks). */ | |
12635 | if (!thumb_mode && (check & NEON_CHECK_CC)) | |
12636 | { | |
12637 | if (inst.cond != COND_ALWAYS) | |
12638 | { | |
12639 | first_error (_(BAD_COND)); | |
12640 | return FAIL; | |
12641 | } | |
12642 | if (inst.uncond_value != -1) | |
12643 | inst.instruction |= inst.uncond_value << 28; | |
12644 | } | |
5f4273c7 | 12645 | |
037e8744 JB |
12646 | if ((check & NEON_CHECK_ARCH) |
12647 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) | |
12648 | { | |
12649 | first_error (_(BAD_FPU)); | |
12650 | return FAIL; | |
12651 | } | |
5f4273c7 | 12652 | |
037e8744 JB |
12653 | return SUCCESS; |
12654 | } | |
12655 | ||
5287ad62 JB |
12656 | static void |
12657 | do_neon_addsub_if_i (void) | |
12658 | { | |
037e8744 JB |
12659 | if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) |
12660 | return; | |
12661 | ||
12662 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
12663 | return; | |
12664 | ||
5287ad62 JB |
12665 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
12666 | affected if we specify unsigned args. */ | |
dcbf9037 | 12667 | neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); |
5287ad62 JB |
12668 | } |
12669 | ||
12670 | /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the | |
12671 | result to be: | |
12672 | V<op> A,B (A is operand 0, B is operand 2) | |
12673 | to mean: | |
12674 | V<op> A,B,A | |
12675 | not: | |
12676 | V<op> A,B,B | |
12677 | so handle that case specially. */ | |
12678 | ||
12679 | static void | |
12680 | neon_exchange_operands (void) | |
12681 | { | |
12682 | void *scratch = alloca (sizeof (inst.operands[0])); | |
12683 | if (inst.operands[1].present) | |
12684 | { | |
12685 | /* Swap operands[1] and operands[2]. */ | |
12686 | memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); | |
12687 | inst.operands[1] = inst.operands[2]; | |
12688 | memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); | |
12689 | } | |
12690 | else | |
12691 | { | |
12692 | inst.operands[1] = inst.operands[2]; | |
12693 | inst.operands[2] = inst.operands[0]; | |
12694 | } | |
12695 | } | |
12696 | ||
12697 | static void | |
12698 | neon_compare (unsigned regtypes, unsigned immtypes, int invert) | |
12699 | { | |
12700 | if (inst.operands[2].isreg) | |
12701 | { | |
12702 | if (invert) | |
12703 | neon_exchange_operands (); | |
dcbf9037 | 12704 | neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); |
5287ad62 JB |
12705 | } |
12706 | else | |
12707 | { | |
037e8744 | 12708 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
dcbf9037 JB |
12709 | struct neon_type_el et = neon_check_type (2, rs, |
12710 | N_EQK | N_SIZ, immtypes | N_KEY); | |
5287ad62 JB |
12711 | |
12712 | inst.instruction = NEON_ENC_IMMED (inst.instruction); | |
12713 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12714 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12715 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
12716 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 12717 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
12718 | inst.instruction |= (et.type == NT_float) << 10; |
12719 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 12720 | |
5287ad62 JB |
12721 | inst.instruction = neon_dp_fixup (inst.instruction); |
12722 | } | |
12723 | } | |
12724 | ||
12725 | static void | |
12726 | do_neon_cmp (void) | |
12727 | { | |
12728 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); | |
12729 | } | |
12730 | ||
12731 | static void | |
12732 | do_neon_cmp_inv (void) | |
12733 | { | |
12734 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); | |
12735 | } | |
12736 | ||
12737 | static void | |
12738 | do_neon_ceq (void) | |
12739 | { | |
12740 | neon_compare (N_IF_32, N_IF_32, FALSE); | |
12741 | } | |
12742 | ||
12743 | /* For multiply instructions, we have the possibility of 16-bit or 32-bit | |
12744 | scalars, which are encoded in 5 bits, M : Rm. | |
12745 | For 16-bit scalars, the register is encoded in Rm[2:0] and the index in | |
12746 | M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the | |
12747 | index in M. */ | |
12748 | ||
12749 | static unsigned | |
12750 | neon_scalar_for_mul (unsigned scalar, unsigned elsize) | |
12751 | { | |
dcbf9037 JB |
12752 | unsigned regno = NEON_SCALAR_REG (scalar); |
12753 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
5287ad62 JB |
12754 | |
12755 | switch (elsize) | |
12756 | { | |
12757 | case 16: | |
12758 | if (regno > 7 || elno > 3) | |
12759 | goto bad_scalar; | |
12760 | return regno | (elno << 3); | |
5f4273c7 | 12761 | |
5287ad62 JB |
12762 | case 32: |
12763 | if (regno > 15 || elno > 1) | |
12764 | goto bad_scalar; | |
12765 | return regno | (elno << 4); | |
12766 | ||
12767 | default: | |
12768 | bad_scalar: | |
dcbf9037 | 12769 | first_error (_("scalar out of range for multiply instruction")); |
5287ad62 JB |
12770 | } |
12771 | ||
12772 | return 0; | |
12773 | } | |
12774 | ||
12775 | /* Encode multiply / multiply-accumulate scalar instructions. */ | |
12776 | ||
12777 | static void | |
12778 | neon_mul_mac (struct neon_type_el et, int ubit) | |
12779 | { | |
dcbf9037 JB |
12780 | unsigned scalar; |
12781 | ||
12782 | /* Give a more helpful error message if we have an invalid type. */ | |
12783 | if (et.type == NT_invtype) | |
12784 | return; | |
5f4273c7 | 12785 | |
dcbf9037 | 12786 | scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); |
5287ad62 JB |
12787 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
12788 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12789 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
12790 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
12791 | inst.instruction |= LOW4 (scalar); | |
12792 | inst.instruction |= HI1 (scalar) << 5; | |
12793 | inst.instruction |= (et.type == NT_float) << 8; | |
12794 | inst.instruction |= neon_logbits (et.size) << 20; | |
12795 | inst.instruction |= (ubit != 0) << 24; | |
12796 | ||
12797 | inst.instruction = neon_dp_fixup (inst.instruction); | |
12798 | } | |
12799 | ||
12800 | static void | |
12801 | do_neon_mac_maybe_scalar (void) | |
12802 | { | |
037e8744 JB |
12803 | if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) |
12804 | return; | |
12805 | ||
12806 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
12807 | return; | |
12808 | ||
5287ad62 JB |
12809 | if (inst.operands[2].isscalar) |
12810 | { | |
037e8744 | 12811 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
12812 | struct neon_type_el et = neon_check_type (3, rs, |
12813 | N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); | |
12814 | inst.instruction = NEON_ENC_SCALAR (inst.instruction); | |
037e8744 | 12815 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
12816 | } |
12817 | else | |
428e3f1f PB |
12818 | { |
12819 | /* The "untyped" case can't happen. Do this to stop the "U" bit being | |
12820 | affected if we specify unsigned args. */ | |
12821 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
12822 | } | |
5287ad62 JB |
12823 | } |
12824 | ||
12825 | static void | |
12826 | do_neon_tst (void) | |
12827 | { | |
037e8744 | 12828 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12829 | struct neon_type_el et = neon_check_type (3, rs, |
12830 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
037e8744 | 12831 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
12832 | } |
12833 | ||
12834 | /* VMUL with 3 registers allows the P8 type. The scalar version supports the | |
12835 | same types as the MAC equivalents. The polynomial type for this instruction | |
12836 | is encoded the same as the integer type. */ | |
12837 | ||
12838 | static void | |
12839 | do_neon_mul (void) | |
12840 | { | |
037e8744 JB |
12841 | if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) |
12842 | return; | |
12843 | ||
12844 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
12845 | return; | |
12846 | ||
5287ad62 JB |
12847 | if (inst.operands[2].isscalar) |
12848 | do_neon_mac_maybe_scalar (); | |
12849 | else | |
dcbf9037 | 12850 | neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); |
5287ad62 JB |
12851 | } |
12852 | ||
12853 | static void | |
12854 | do_neon_qdmulh (void) | |
12855 | { | |
12856 | if (inst.operands[2].isscalar) | |
12857 | { | |
037e8744 | 12858 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
12859 | struct neon_type_el et = neon_check_type (3, rs, |
12860 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
12861 | inst.instruction = NEON_ENC_SCALAR (inst.instruction); | |
037e8744 | 12862 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
12863 | } |
12864 | else | |
12865 | { | |
037e8744 | 12866 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12867 | struct neon_type_el et = neon_check_type (3, rs, |
12868 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
12869 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
12870 | /* The U bit (rounding) comes from bit mask. */ | |
037e8744 | 12871 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
12872 | } |
12873 | } | |
12874 | ||
12875 | static void | |
12876 | do_neon_fcmp_absolute (void) | |
12877 | { | |
037e8744 | 12878 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12879 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
12880 | /* Size field comes from bit mask. */ | |
037e8744 | 12881 | neon_three_same (neon_quad (rs), 1, -1); |
5287ad62 JB |
12882 | } |
12883 | ||
12884 | static void | |
12885 | do_neon_fcmp_absolute_inv (void) | |
12886 | { | |
12887 | neon_exchange_operands (); | |
12888 | do_neon_fcmp_absolute (); | |
12889 | } | |
12890 | ||
12891 | static void | |
12892 | do_neon_step (void) | |
12893 | { | |
037e8744 | 12894 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 12895 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
037e8744 | 12896 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
12897 | } |
12898 | ||
12899 | static void | |
12900 | do_neon_abs_neg (void) | |
12901 | { | |
037e8744 JB |
12902 | enum neon_shape rs; |
12903 | struct neon_type_el et; | |
5f4273c7 | 12904 | |
037e8744 JB |
12905 | if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) |
12906 | return; | |
12907 | ||
12908 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
12909 | return; | |
12910 | ||
12911 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
12912 | et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); | |
5f4273c7 | 12913 | |
5287ad62 JB |
12914 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
12915 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12916 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
12917 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 12918 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
12919 | inst.instruction |= (et.type == NT_float) << 10; |
12920 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 12921 | |
5287ad62 JB |
12922 | inst.instruction = neon_dp_fixup (inst.instruction); |
12923 | } | |
12924 | ||
12925 | static void | |
12926 | do_neon_sli (void) | |
12927 | { | |
037e8744 | 12928 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
12929 | struct neon_type_el et = neon_check_type (2, rs, |
12930 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
12931 | int imm = inst.operands[2].imm; | |
12932 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
12933 | _("immediate out of range for insert")); | |
037e8744 | 12934 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
12935 | } |
12936 | ||
12937 | static void | |
12938 | do_neon_sri (void) | |
12939 | { | |
037e8744 | 12940 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
12941 | struct neon_type_el et = neon_check_type (2, rs, |
12942 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
12943 | int imm = inst.operands[2].imm; | |
12944 | constraint (imm < 1 || (unsigned)imm > et.size, | |
12945 | _("immediate out of range for insert")); | |
037e8744 | 12946 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); |
5287ad62 JB |
12947 | } |
12948 | ||
12949 | static void | |
12950 | do_neon_qshlu_imm (void) | |
12951 | { | |
037e8744 | 12952 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
12953 | struct neon_type_el et = neon_check_type (2, rs, |
12954 | N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); | |
12955 | int imm = inst.operands[2].imm; | |
12956 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
12957 | _("immediate out of range for shift")); | |
12958 | /* Only encodes the 'U present' variant of the instruction. | |
12959 | In this case, signed types have OP (bit 8) set to 0. | |
12960 | Unsigned types have OP set to 1. */ | |
12961 | inst.instruction |= (et.type == NT_unsigned) << 8; | |
12962 | /* The rest of the bits are the same as other immediate shifts. */ | |
037e8744 | 12963 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
12964 | } |
12965 | ||
12966 | static void | |
12967 | do_neon_qmovn (void) | |
12968 | { | |
12969 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
12970 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
12971 | /* Saturating move where operands can be signed or unsigned, and the | |
12972 | destination has the same signedness. */ | |
12973 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
12974 | if (et.type == NT_unsigned) | |
12975 | inst.instruction |= 0xc0; | |
12976 | else | |
12977 | inst.instruction |= 0x80; | |
12978 | neon_two_same (0, 1, et.size / 2); | |
12979 | } | |
12980 | ||
12981 | static void | |
12982 | do_neon_qmovun (void) | |
12983 | { | |
12984 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
12985 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
12986 | /* Saturating move with unsigned results. Operands must be signed. */ | |
12987 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
12988 | neon_two_same (0, 1, et.size / 2); | |
12989 | } | |
12990 | ||
12991 | static void | |
12992 | do_neon_rshift_sat_narrow (void) | |
12993 | { | |
12994 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
12995 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
12996 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
12997 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
12998 | int imm = inst.operands[2].imm; | |
12999 | /* This gets the bounds check, size encoding and immediate bits calculation | |
13000 | right. */ | |
13001 | et.size /= 2; | |
5f4273c7 | 13002 | |
5287ad62 JB |
13003 | /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for |
13004 | VQMOVN.I<size> <Dd>, <Qm>. */ | |
13005 | if (imm == 0) | |
13006 | { | |
13007 | inst.operands[2].present = 0; | |
13008 | inst.instruction = N_MNEM_vqmovn; | |
13009 | do_neon_qmovn (); | |
13010 | return; | |
13011 | } | |
5f4273c7 | 13012 | |
5287ad62 JB |
13013 | constraint (imm < 1 || (unsigned)imm > et.size, |
13014 | _("immediate out of range")); | |
13015 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); | |
13016 | } | |
13017 | ||
13018 | static void | |
13019 | do_neon_rshift_sat_narrow_u (void) | |
13020 | { | |
13021 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
13022 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
13023 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
13024 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
13025 | int imm = inst.operands[2].imm; | |
13026 | /* This gets the bounds check, size encoding and immediate bits calculation | |
13027 | right. */ | |
13028 | et.size /= 2; | |
13029 | ||
13030 | /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for | |
13031 | VQMOVUN.I<size> <Dd>, <Qm>. */ | |
13032 | if (imm == 0) | |
13033 | { | |
13034 | inst.operands[2].present = 0; | |
13035 | inst.instruction = N_MNEM_vqmovun; | |
13036 | do_neon_qmovun (); | |
13037 | return; | |
13038 | } | |
13039 | ||
13040 | constraint (imm < 1 || (unsigned)imm > et.size, | |
13041 | _("immediate out of range")); | |
13042 | /* FIXME: The manual is kind of unclear about what value U should have in | |
13043 | VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it | |
13044 | must be 1. */ | |
13045 | neon_imm_shift (TRUE, 1, 0, et, et.size - imm); | |
13046 | } | |
13047 | ||
13048 | static void | |
13049 | do_neon_movn (void) | |
13050 | { | |
13051 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
13052 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
13053 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
13054 | neon_two_same (0, 1, et.size / 2); | |
13055 | } | |
13056 | ||
13057 | static void | |
13058 | do_neon_rshift_narrow (void) | |
13059 | { | |
13060 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
13061 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
13062 | int imm = inst.operands[2].imm; | |
13063 | /* This gets the bounds check, size encoding and immediate bits calculation | |
13064 | right. */ | |
13065 | et.size /= 2; | |
5f4273c7 | 13066 | |
5287ad62 JB |
13067 | /* If immediate is zero then we are a pseudo-instruction for |
13068 | VMOVN.I<size> <Dd>, <Qm> */ | |
13069 | if (imm == 0) | |
13070 | { | |
13071 | inst.operands[2].present = 0; | |
13072 | inst.instruction = N_MNEM_vmovn; | |
13073 | do_neon_movn (); | |
13074 | return; | |
13075 | } | |
5f4273c7 | 13076 | |
5287ad62 JB |
13077 | constraint (imm < 1 || (unsigned)imm > et.size, |
13078 | _("immediate out of range for narrowing operation")); | |
13079 | neon_imm_shift (FALSE, 0, 0, et, et.size - imm); | |
13080 | } | |
13081 | ||
13082 | static void | |
13083 | do_neon_shll (void) | |
13084 | { | |
13085 | /* FIXME: Type checking when lengthening. */ | |
13086 | struct neon_type_el et = neon_check_type (2, NS_QDI, | |
13087 | N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); | |
13088 | unsigned imm = inst.operands[2].imm; | |
13089 | ||
13090 | if (imm == et.size) | |
13091 | { | |
13092 | /* Maximum shift variant. */ | |
13093 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
13094 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13095 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13096 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13097 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13098 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 13099 | |
5287ad62 JB |
13100 | inst.instruction = neon_dp_fixup (inst.instruction); |
13101 | } | |
13102 | else | |
13103 | { | |
13104 | /* A more-specific type check for non-max versions. */ | |
13105 | et = neon_check_type (2, NS_QDI, | |
13106 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
13107 | inst.instruction = NEON_ENC_IMMED (inst.instruction); | |
13108 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); | |
13109 | } | |
13110 | } | |
13111 | ||
037e8744 | 13112 | /* Check the various types for the VCVT instruction, and return which version |
5287ad62 JB |
13113 | the current instruction is. */ |
13114 | ||
13115 | static int | |
13116 | neon_cvt_flavour (enum neon_shape rs) | |
13117 | { | |
037e8744 JB |
13118 | #define CVT_VAR(C,X,Y) \ |
13119 | et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \ | |
13120 | if (et.type != NT_invtype) \ | |
13121 | { \ | |
13122 | inst.error = NULL; \ | |
13123 | return (C); \ | |
5287ad62 JB |
13124 | } |
13125 | struct neon_type_el et; | |
037e8744 JB |
13126 | unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF |
13127 | || rs == NS_FF) ? N_VFP : 0; | |
13128 | /* The instruction versions which take an immediate take one register | |
13129 | argument, which is extended to the width of the full register. Thus the | |
13130 | "source" and "destination" registers must have the same width. Hack that | |
13131 | here by making the size equal to the key (wider, in this case) operand. */ | |
13132 | unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; | |
5f4273c7 | 13133 | |
5287ad62 JB |
13134 | CVT_VAR (0, N_S32, N_F32); |
13135 | CVT_VAR (1, N_U32, N_F32); | |
13136 | CVT_VAR (2, N_F32, N_S32); | |
13137 | CVT_VAR (3, N_F32, N_U32); | |
8e79c3df CM |
13138 | /* Half-precision conversions. */ |
13139 | CVT_VAR (4, N_F32, N_F16); | |
13140 | CVT_VAR (5, N_F16, N_F32); | |
5f4273c7 | 13141 | |
037e8744 | 13142 | whole_reg = N_VFP; |
5f4273c7 | 13143 | |
037e8744 | 13144 | /* VFP instructions. */ |
8e79c3df CM |
13145 | CVT_VAR (6, N_F32, N_F64); |
13146 | CVT_VAR (7, N_F64, N_F32); | |
13147 | CVT_VAR (8, N_S32, N_F64 | key); | |
13148 | CVT_VAR (9, N_U32, N_F64 | key); | |
13149 | CVT_VAR (10, N_F64 | key, N_S32); | |
13150 | CVT_VAR (11, N_F64 | key, N_U32); | |
037e8744 | 13151 | /* VFP instructions with bitshift. */ |
8e79c3df CM |
13152 | CVT_VAR (12, N_F32 | key, N_S16); |
13153 | CVT_VAR (13, N_F32 | key, N_U16); | |
13154 | CVT_VAR (14, N_F64 | key, N_S16); | |
13155 | CVT_VAR (15, N_F64 | key, N_U16); | |
13156 | CVT_VAR (16, N_S16, N_F32 | key); | |
13157 | CVT_VAR (17, N_U16, N_F32 | key); | |
13158 | CVT_VAR (18, N_S16, N_F64 | key); | |
13159 | CVT_VAR (19, N_U16, N_F64 | key); | |
5f4273c7 | 13160 | |
5287ad62 JB |
13161 | return -1; |
13162 | #undef CVT_VAR | |
13163 | } | |
13164 | ||
037e8744 JB |
13165 | /* Neon-syntax VFP conversions. */ |
13166 | ||
5287ad62 | 13167 | static void |
037e8744 | 13168 | do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) |
5287ad62 | 13169 | { |
037e8744 | 13170 | const char *opname = 0; |
5f4273c7 | 13171 | |
037e8744 | 13172 | if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) |
5287ad62 | 13173 | { |
037e8744 JB |
13174 | /* Conversions with immediate bitshift. */ |
13175 | const char *enc[] = | |
13176 | { | |
13177 | "ftosls", | |
13178 | "ftouls", | |
13179 | "fsltos", | |
13180 | "fultos", | |
13181 | NULL, | |
13182 | NULL, | |
8e79c3df CM |
13183 | NULL, |
13184 | NULL, | |
037e8744 JB |
13185 | "ftosld", |
13186 | "ftould", | |
13187 | "fsltod", | |
13188 | "fultod", | |
13189 | "fshtos", | |
13190 | "fuhtos", | |
13191 | "fshtod", | |
13192 | "fuhtod", | |
13193 | "ftoshs", | |
13194 | "ftouhs", | |
13195 | "ftoshd", | |
13196 | "ftouhd" | |
13197 | }; | |
13198 | ||
13199 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
13200 | { | |
13201 | opname = enc[flavour]; | |
13202 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
13203 | _("operands 0 and 1 must be the same register")); | |
13204 | inst.operands[1] = inst.operands[2]; | |
13205 | memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); | |
13206 | } | |
5287ad62 JB |
13207 | } |
13208 | else | |
13209 | { | |
037e8744 JB |
13210 | /* Conversions without bitshift. */ |
13211 | const char *enc[] = | |
13212 | { | |
13213 | "ftosis", | |
13214 | "ftouis", | |
13215 | "fsitos", | |
13216 | "fuitos", | |
8e79c3df CM |
13217 | "NULL", |
13218 | "NULL", | |
037e8744 JB |
13219 | "fcvtsd", |
13220 | "fcvtds", | |
13221 | "ftosid", | |
13222 | "ftouid", | |
13223 | "fsitod", | |
13224 | "fuitod" | |
13225 | }; | |
13226 | ||
13227 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
13228 | opname = enc[flavour]; | |
13229 | } | |
13230 | ||
13231 | if (opname) | |
13232 | do_vfp_nsyn_opcode (opname); | |
13233 | } | |
13234 | ||
13235 | static void | |
13236 | do_vfp_nsyn_cvtz (void) | |
13237 | { | |
13238 | enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); | |
13239 | int flavour = neon_cvt_flavour (rs); | |
13240 | const char *enc[] = | |
13241 | { | |
13242 | "ftosizs", | |
13243 | "ftouizs", | |
13244 | NULL, | |
13245 | NULL, | |
13246 | NULL, | |
13247 | NULL, | |
8e79c3df CM |
13248 | NULL, |
13249 | NULL, | |
037e8744 JB |
13250 | "ftosizd", |
13251 | "ftouizd" | |
13252 | }; | |
13253 | ||
13254 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) | |
13255 | do_vfp_nsyn_opcode (enc[flavour]); | |
13256 | } | |
f31fef98 | 13257 | |
037e8744 JB |
13258 | static void |
13259 | do_neon_cvt (void) | |
13260 | { | |
13261 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, | |
8e79c3df | 13262 | NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL); |
037e8744 JB |
13263 | int flavour = neon_cvt_flavour (rs); |
13264 | ||
13265 | /* VFP rather than Neon conversions. */ | |
8e79c3df | 13266 | if (flavour >= 6) |
037e8744 JB |
13267 | { |
13268 | do_vfp_nsyn_cvt (rs, flavour); | |
13269 | return; | |
13270 | } | |
13271 | ||
13272 | switch (rs) | |
13273 | { | |
13274 | case NS_DDI: | |
13275 | case NS_QQI: | |
13276 | { | |
35997600 NC |
13277 | unsigned immbits; |
13278 | unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; | |
13279 | ||
037e8744 JB |
13280 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
13281 | return; | |
13282 | ||
13283 | /* Fixed-point conversion with #0 immediate is encoded as an | |
13284 | integer conversion. */ | |
13285 | if (inst.operands[2].present && inst.operands[2].imm == 0) | |
13286 | goto int_encode; | |
35997600 | 13287 | immbits = 32 - inst.operands[2].imm; |
037e8744 JB |
13288 | inst.instruction = NEON_ENC_IMMED (inst.instruction); |
13289 | if (flavour != -1) | |
13290 | inst.instruction |= enctab[flavour]; | |
13291 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13292 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13293 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13294 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13295 | inst.instruction |= neon_quad (rs) << 6; | |
13296 | inst.instruction |= 1 << 21; | |
13297 | inst.instruction |= immbits << 16; | |
13298 | ||
13299 | inst.instruction = neon_dp_fixup (inst.instruction); | |
13300 | } | |
13301 | break; | |
13302 | ||
13303 | case NS_DD: | |
13304 | case NS_QQ: | |
13305 | int_encode: | |
13306 | { | |
13307 | unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; | |
13308 | ||
13309 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
13310 | ||
13311 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13312 | return; | |
13313 | ||
13314 | if (flavour != -1) | |
13315 | inst.instruction |= enctab[flavour]; | |
13316 | ||
13317 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13318 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13319 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13320 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13321 | inst.instruction |= neon_quad (rs) << 6; | |
13322 | inst.instruction |= 2 << 18; | |
13323 | ||
13324 | inst.instruction = neon_dp_fixup (inst.instruction); | |
13325 | } | |
13326 | break; | |
13327 | ||
8e79c3df CM |
13328 | /* Half-precision conversions for Advanced SIMD -- neon. */ |
13329 | case NS_QD: | |
13330 | case NS_DQ: | |
13331 | ||
13332 | if ((rs == NS_DQ) | |
13333 | && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) | |
13334 | { | |
13335 | as_bad (_("operand size must match register width")); | |
13336 | break; | |
13337 | } | |
13338 | ||
13339 | if ((rs == NS_QD) | |
13340 | && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) | |
13341 | { | |
13342 | as_bad (_("operand size must match register width")); | |
13343 | break; | |
13344 | } | |
13345 | ||
13346 | if (rs == NS_DQ) | |
13347 | inst.instruction = 0x3b60600; | |
13348 | else | |
13349 | inst.instruction = 0x3b60700; | |
13350 | ||
13351 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13352 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13353 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13354 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13355 | inst.instruction = neon_dp_fixup (inst.instruction); | |
13356 | break; | |
13357 | ||
037e8744 JB |
13358 | default: |
13359 | /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ | |
13360 | do_vfp_nsyn_cvt (rs, flavour); | |
5287ad62 | 13361 | } |
5287ad62 JB |
13362 | } |
13363 | ||
8e79c3df CM |
13364 | static void |
13365 | do_neon_cvtb (void) | |
13366 | { | |
13367 | inst.instruction = 0xeb20a40; | |
13368 | ||
13369 | /* The sizes are attached to the mnemonic. */ | |
13370 | if (inst.vectype.el[0].type != NT_invtype | |
13371 | && inst.vectype.el[0].size == 16) | |
13372 | inst.instruction |= 0x00010000; | |
13373 | ||
13374 | /* Programmer's syntax: the sizes are attached to the operands. */ | |
13375 | else if (inst.operands[0].vectype.type != NT_invtype | |
13376 | && inst.operands[0].vectype.size == 16) | |
13377 | inst.instruction |= 0x00010000; | |
13378 | ||
13379 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
13380 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
13381 | do_vfp_cond_or_thumb (); | |
13382 | } | |
13383 | ||
13384 | ||
13385 | static void | |
13386 | do_neon_cvtt (void) | |
13387 | { | |
13388 | do_neon_cvtb (); | |
13389 | inst.instruction |= 0x80; | |
13390 | } | |
13391 | ||
5287ad62 JB |
13392 | static void |
13393 | neon_move_immediate (void) | |
13394 | { | |
037e8744 JB |
13395 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
13396 | struct neon_type_el et = neon_check_type (2, rs, | |
13397 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
5287ad62 | 13398 | unsigned immlo, immhi = 0, immbits; |
c96612cc | 13399 | int op, cmode, float_p; |
5287ad62 | 13400 | |
037e8744 JB |
13401 | constraint (et.type == NT_invtype, |
13402 | _("operand size must be specified for immediate VMOV")); | |
13403 | ||
5287ad62 JB |
13404 | /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ |
13405 | op = (inst.instruction & (1 << 5)) != 0; | |
13406 | ||
13407 | immlo = inst.operands[1].imm; | |
13408 | if (inst.operands[1].regisimm) | |
13409 | immhi = inst.operands[1].reg; | |
13410 | ||
13411 | constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, | |
13412 | _("immediate has bits set outside the operand size")); | |
13413 | ||
c96612cc JB |
13414 | float_p = inst.operands[1].immisfloat; |
13415 | ||
13416 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, | |
136da414 | 13417 | et.size, et.type)) == FAIL) |
5287ad62 JB |
13418 | { |
13419 | /* Invert relevant bits only. */ | |
13420 | neon_invert_size (&immlo, &immhi, et.size); | |
13421 | /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable | |
13422 | with one or the other; those cases are caught by | |
13423 | neon_cmode_for_move_imm. */ | |
13424 | op = !op; | |
c96612cc JB |
13425 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, |
13426 | &op, et.size, et.type)) == FAIL) | |
5287ad62 | 13427 | { |
dcbf9037 | 13428 | first_error (_("immediate out of range")); |
5287ad62 JB |
13429 | return; |
13430 | } | |
13431 | } | |
13432 | ||
13433 | inst.instruction &= ~(1 << 5); | |
13434 | inst.instruction |= op << 5; | |
13435 | ||
13436 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13437 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
037e8744 | 13438 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13439 | inst.instruction |= cmode << 8; |
13440 | ||
13441 | neon_write_immbits (immbits); | |
13442 | } | |
13443 | ||
13444 | static void | |
13445 | do_neon_mvn (void) | |
13446 | { | |
13447 | if (inst.operands[1].isreg) | |
13448 | { | |
037e8744 | 13449 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5f4273c7 | 13450 | |
5287ad62 JB |
13451 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); |
13452 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13453 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13454 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13455 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 13456 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13457 | } |
13458 | else | |
13459 | { | |
13460 | inst.instruction = NEON_ENC_IMMED (inst.instruction); | |
13461 | neon_move_immediate (); | |
13462 | } | |
13463 | ||
13464 | inst.instruction = neon_dp_fixup (inst.instruction); | |
13465 | } | |
13466 | ||
13467 | /* Encode instructions of form: | |
13468 | ||
13469 | |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
5f4273c7 | 13470 | | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */ |
5287ad62 JB |
13471 | |
13472 | static void | |
13473 | neon_mixed_length (struct neon_type_el et, unsigned size) | |
13474 | { | |
13475 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13476 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13477 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
13478 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
13479 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
13480 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
13481 | inst.instruction |= (et.type == NT_unsigned) << 24; | |
13482 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 13483 | |
5287ad62 JB |
13484 | inst.instruction = neon_dp_fixup (inst.instruction); |
13485 | } | |
13486 | ||
13487 | static void | |
13488 | do_neon_dyadic_long (void) | |
13489 | { | |
13490 | /* FIXME: Type checking for lengthening op. */ | |
13491 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
13492 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
13493 | neon_mixed_length (et, et.size); | |
13494 | } | |
13495 | ||
13496 | static void | |
13497 | do_neon_abal (void) | |
13498 | { | |
13499 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
13500 | N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
13501 | neon_mixed_length (et, et.size); | |
13502 | } | |
13503 | ||
13504 | static void | |
13505 | neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) | |
13506 | { | |
13507 | if (inst.operands[2].isscalar) | |
13508 | { | |
dcbf9037 JB |
13509 | struct neon_type_el et = neon_check_type (3, NS_QDS, |
13510 | N_EQK | N_DBL, N_EQK, regtypes | N_KEY); | |
5287ad62 JB |
13511 | inst.instruction = NEON_ENC_SCALAR (inst.instruction); |
13512 | neon_mul_mac (et, et.type == NT_unsigned); | |
13513 | } | |
13514 | else | |
13515 | { | |
13516 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
13517 | N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); | |
13518 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
13519 | neon_mixed_length (et, et.size); | |
13520 | } | |
13521 | } | |
13522 | ||
13523 | static void | |
13524 | do_neon_mac_maybe_scalar_long (void) | |
13525 | { | |
13526 | neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); | |
13527 | } | |
13528 | ||
13529 | static void | |
13530 | do_neon_dyadic_wide (void) | |
13531 | { | |
13532 | struct neon_type_el et = neon_check_type (3, NS_QQD, | |
13533 | N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); | |
13534 | neon_mixed_length (et, et.size); | |
13535 | } | |
13536 | ||
13537 | static void | |
13538 | do_neon_dyadic_narrow (void) | |
13539 | { | |
13540 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
13541 | N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); | |
428e3f1f PB |
13542 | /* Operand sign is unimportant, and the U bit is part of the opcode, |
13543 | so force the operand type to integer. */ | |
13544 | et.type = NT_integer; | |
5287ad62 JB |
13545 | neon_mixed_length (et, et.size / 2); |
13546 | } | |
13547 | ||
13548 | static void | |
13549 | do_neon_mul_sat_scalar_long (void) | |
13550 | { | |
13551 | neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); | |
13552 | } | |
13553 | ||
13554 | static void | |
13555 | do_neon_vmull (void) | |
13556 | { | |
13557 | if (inst.operands[2].isscalar) | |
13558 | do_neon_mac_maybe_scalar_long (); | |
13559 | else | |
13560 | { | |
13561 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
13562 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY); | |
13563 | if (et.type == NT_poly) | |
13564 | inst.instruction = NEON_ENC_POLY (inst.instruction); | |
13565 | else | |
13566 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
13567 | /* For polynomial encoding, size field must be 0b00 and the U bit must be | |
13568 | zero. Should be OK as-is. */ | |
13569 | neon_mixed_length (et, et.size); | |
13570 | } | |
13571 | } | |
13572 | ||
13573 | static void | |
13574 | do_neon_ext (void) | |
13575 | { | |
037e8744 | 13576 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
5287ad62 JB |
13577 | struct neon_type_el et = neon_check_type (3, rs, |
13578 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
13579 | unsigned imm = (inst.operands[3].imm * et.size) / 8; | |
35997600 NC |
13580 | |
13581 | constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), | |
13582 | _("shift out of range")); | |
5287ad62 JB |
13583 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13584 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13585 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
13586 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
13587 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
13588 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
037e8744 | 13589 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 | 13590 | inst.instruction |= imm << 8; |
5f4273c7 | 13591 | |
5287ad62 JB |
13592 | inst.instruction = neon_dp_fixup (inst.instruction); |
13593 | } | |
13594 | ||
13595 | static void | |
13596 | do_neon_rev (void) | |
13597 | { | |
037e8744 | 13598 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
13599 | struct neon_type_el et = neon_check_type (2, rs, |
13600 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
13601 | unsigned op = (inst.instruction >> 7) & 3; | |
13602 | /* N (width of reversed regions) is encoded as part of the bitmask. We | |
13603 | extract it here to check the elements to be reversed are smaller. | |
13604 | Otherwise we'd get a reserved instruction. */ | |
13605 | unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; | |
13606 | assert (elsize != 0); | |
13607 | constraint (et.size >= elsize, | |
13608 | _("elements must be smaller than reversal region")); | |
037e8744 | 13609 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
13610 | } |
13611 | ||
13612 | static void | |
13613 | do_neon_dup (void) | |
13614 | { | |
13615 | if (inst.operands[1].isscalar) | |
13616 | { | |
037e8744 | 13617 | enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); |
dcbf9037 JB |
13618 | struct neon_type_el et = neon_check_type (2, rs, |
13619 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
5287ad62 | 13620 | unsigned sizebits = et.size >> 3; |
dcbf9037 | 13621 | unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); |
5287ad62 | 13622 | int logsize = neon_logbits (et.size); |
dcbf9037 | 13623 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; |
037e8744 JB |
13624 | |
13625 | if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) | |
13626 | return; | |
13627 | ||
5287ad62 JB |
13628 | inst.instruction = NEON_ENC_SCALAR (inst.instruction); |
13629 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13630 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13631 | inst.instruction |= LOW4 (dm); | |
13632 | inst.instruction |= HI1 (dm) << 5; | |
037e8744 | 13633 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13634 | inst.instruction |= x << 17; |
13635 | inst.instruction |= sizebits << 16; | |
5f4273c7 | 13636 | |
5287ad62 JB |
13637 | inst.instruction = neon_dp_fixup (inst.instruction); |
13638 | } | |
13639 | else | |
13640 | { | |
037e8744 JB |
13641 | enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); |
13642 | struct neon_type_el et = neon_check_type (2, rs, | |
13643 | N_8 | N_16 | N_32 | N_KEY, N_EQK); | |
5287ad62 JB |
13644 | /* Duplicate ARM register to lanes of vector. */ |
13645 | inst.instruction = NEON_ENC_ARMREG (inst.instruction); | |
13646 | switch (et.size) | |
13647 | { | |
13648 | case 8: inst.instruction |= 0x400000; break; | |
13649 | case 16: inst.instruction |= 0x000020; break; | |
13650 | case 32: inst.instruction |= 0x000000; break; | |
13651 | default: break; | |
13652 | } | |
13653 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
13654 | inst.instruction |= LOW4 (inst.operands[0].reg) << 16; | |
13655 | inst.instruction |= HI1 (inst.operands[0].reg) << 7; | |
037e8744 | 13656 | inst.instruction |= neon_quad (rs) << 21; |
5287ad62 JB |
13657 | /* The encoding for this instruction is identical for the ARM and Thumb |
13658 | variants, except for the condition field. */ | |
037e8744 | 13659 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
13660 | } |
13661 | } | |
13662 | ||
13663 | /* VMOV has particularly many variations. It can be one of: | |
13664 | 0. VMOV<c><q> <Qd>, <Qm> | |
13665 | 1. VMOV<c><q> <Dd>, <Dm> | |
13666 | (Register operations, which are VORR with Rm = Rn.) | |
13667 | 2. VMOV<c><q>.<dt> <Qd>, #<imm> | |
13668 | 3. VMOV<c><q>.<dt> <Dd>, #<imm> | |
13669 | (Immediate loads.) | |
13670 | 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> | |
13671 | (ARM register to scalar.) | |
13672 | 5. VMOV<c><q> <Dm>, <Rd>, <Rn> | |
13673 | (Two ARM registers to vector.) | |
13674 | 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> | |
13675 | (Scalar to ARM register.) | |
13676 | 7. VMOV<c><q> <Rd>, <Rn>, <Dm> | |
13677 | (Vector to two ARM registers.) | |
037e8744 JB |
13678 | 8. VMOV.F32 <Sd>, <Sm> |
13679 | 9. VMOV.F64 <Dd>, <Dm> | |
13680 | (VFP register moves.) | |
13681 | 10. VMOV.F32 <Sd>, #imm | |
13682 | 11. VMOV.F64 <Dd>, #imm | |
13683 | (VFP float immediate load.) | |
13684 | 12. VMOV <Rd>, <Sm> | |
13685 | (VFP single to ARM reg.) | |
13686 | 13. VMOV <Sd>, <Rm> | |
13687 | (ARM reg to VFP single.) | |
13688 | 14. VMOV <Rd>, <Re>, <Sn>, <Sm> | |
13689 | (Two ARM regs to two VFP singles.) | |
13690 | 15. VMOV <Sd>, <Se>, <Rn>, <Rm> | |
13691 | (Two VFP singles to two ARM regs.) | |
5f4273c7 | 13692 | |
037e8744 JB |
13693 | These cases can be disambiguated using neon_select_shape, except cases 1/9 |
13694 | and 3/11 which depend on the operand type too. | |
5f4273c7 | 13695 | |
5287ad62 | 13696 | All the encoded bits are hardcoded by this function. |
5f4273c7 | 13697 | |
b7fc2769 JB |
13698 | Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). |
13699 | Cases 5, 7 may be used with VFPv2 and above. | |
5f4273c7 | 13700 | |
5287ad62 | 13701 | FIXME: Some of the checking may be a bit sloppy (in a couple of cases you |
5f4273c7 | 13702 | can specify a type where it doesn't make sense to, and is ignored). */ |
5287ad62 JB |
13703 | |
13704 | static void | |
13705 | do_neon_mov (void) | |
13706 | { | |
037e8744 JB |
13707 | enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, |
13708 | NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, | |
13709 | NS_NULL); | |
13710 | struct neon_type_el et; | |
13711 | const char *ldconst = 0; | |
5287ad62 | 13712 | |
037e8744 | 13713 | switch (rs) |
5287ad62 | 13714 | { |
037e8744 JB |
13715 | case NS_DD: /* case 1/9. */ |
13716 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
13717 | /* It is not an error here if no type is given. */ | |
13718 | inst.error = NULL; | |
13719 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 13720 | { |
037e8744 JB |
13721 | do_vfp_nsyn_opcode ("fcpyd"); |
13722 | break; | |
5287ad62 | 13723 | } |
037e8744 | 13724 | /* fall through. */ |
5287ad62 | 13725 | |
037e8744 JB |
13726 | case NS_QQ: /* case 0/1. */ |
13727 | { | |
13728 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13729 | return; | |
13730 | /* The architecture manual I have doesn't explicitly state which | |
13731 | value the U bit should have for register->register moves, but | |
13732 | the equivalent VORR instruction has U = 0, so do that. */ | |
13733 | inst.instruction = 0x0200110; | |
13734 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13735 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13736 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13737 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13738 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
13739 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
13740 | inst.instruction |= neon_quad (rs) << 6; | |
13741 | ||
13742 | inst.instruction = neon_dp_fixup (inst.instruction); | |
13743 | } | |
13744 | break; | |
5f4273c7 | 13745 | |
037e8744 JB |
13746 | case NS_DI: /* case 3/11. */ |
13747 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
13748 | inst.error = NULL; | |
13749 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 13750 | { |
037e8744 JB |
13751 | /* case 11 (fconstd). */ |
13752 | ldconst = "fconstd"; | |
13753 | goto encode_fconstd; | |
5287ad62 | 13754 | } |
037e8744 JB |
13755 | /* fall through. */ |
13756 | ||
13757 | case NS_QI: /* case 2/3. */ | |
13758 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13759 | return; | |
13760 | inst.instruction = 0x0800010; | |
13761 | neon_move_immediate (); | |
13762 | inst.instruction = neon_dp_fixup (inst.instruction); | |
5287ad62 | 13763 | break; |
5f4273c7 | 13764 | |
037e8744 JB |
13765 | case NS_SR: /* case 4. */ |
13766 | { | |
13767 | unsigned bcdebits = 0; | |
13768 | struct neon_type_el et = neon_check_type (2, NS_NULL, | |
13769 | N_8 | N_16 | N_32 | N_KEY, N_EQK); | |
13770 | int logsize = neon_logbits (et.size); | |
13771 | unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); | |
13772 | unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); | |
13773 | ||
13774 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), | |
13775 | _(BAD_FPU)); | |
13776 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
13777 | && et.size != 32, _(BAD_FPU)); | |
13778 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
13779 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
13780 | ||
13781 | switch (et.size) | |
13782 | { | |
13783 | case 8: bcdebits = 0x8; break; | |
13784 | case 16: bcdebits = 0x1; break; | |
13785 | case 32: bcdebits = 0x0; break; | |
13786 | default: ; | |
13787 | } | |
13788 | ||
13789 | bcdebits |= x << logsize; | |
13790 | ||
13791 | inst.instruction = 0xe000b10; | |
13792 | do_vfp_cond_or_thumb (); | |
13793 | inst.instruction |= LOW4 (dn) << 16; | |
13794 | inst.instruction |= HI1 (dn) << 7; | |
13795 | inst.instruction |= inst.operands[1].reg << 12; | |
13796 | inst.instruction |= (bcdebits & 3) << 5; | |
13797 | inst.instruction |= (bcdebits >> 2) << 21; | |
13798 | } | |
13799 | break; | |
5f4273c7 | 13800 | |
037e8744 | 13801 | case NS_DRR: /* case 5 (fmdrr). */ |
b7fc2769 | 13802 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), |
037e8744 | 13803 | _(BAD_FPU)); |
b7fc2769 | 13804 | |
037e8744 JB |
13805 | inst.instruction = 0xc400b10; |
13806 | do_vfp_cond_or_thumb (); | |
13807 | inst.instruction |= LOW4 (inst.operands[0].reg); | |
13808 | inst.instruction |= HI1 (inst.operands[0].reg) << 5; | |
13809 | inst.instruction |= inst.operands[1].reg << 12; | |
13810 | inst.instruction |= inst.operands[2].reg << 16; | |
13811 | break; | |
5f4273c7 | 13812 | |
037e8744 JB |
13813 | case NS_RS: /* case 6. */ |
13814 | { | |
13815 | struct neon_type_el et = neon_check_type (2, NS_NULL, | |
13816 | N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); | |
13817 | unsigned logsize = neon_logbits (et.size); | |
13818 | unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); | |
13819 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); | |
13820 | unsigned abcdebits = 0; | |
13821 | ||
13822 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), | |
13823 | _(BAD_FPU)); | |
13824 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
13825 | && et.size != 32, _(BAD_FPU)); | |
13826 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
13827 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
13828 | ||
13829 | switch (et.size) | |
13830 | { | |
13831 | case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; | |
13832 | case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; | |
13833 | case 32: abcdebits = 0x00; break; | |
13834 | default: ; | |
13835 | } | |
13836 | ||
13837 | abcdebits |= x << logsize; | |
13838 | inst.instruction = 0xe100b10; | |
13839 | do_vfp_cond_or_thumb (); | |
13840 | inst.instruction |= LOW4 (dn) << 16; | |
13841 | inst.instruction |= HI1 (dn) << 7; | |
13842 | inst.instruction |= inst.operands[0].reg << 12; | |
13843 | inst.instruction |= (abcdebits & 3) << 5; | |
13844 | inst.instruction |= (abcdebits >> 2) << 21; | |
13845 | } | |
13846 | break; | |
5f4273c7 | 13847 | |
037e8744 JB |
13848 | case NS_RRD: /* case 7 (fmrrd). */ |
13849 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), | |
13850 | _(BAD_FPU)); | |
13851 | ||
13852 | inst.instruction = 0xc500b10; | |
13853 | do_vfp_cond_or_thumb (); | |
13854 | inst.instruction |= inst.operands[0].reg << 12; | |
13855 | inst.instruction |= inst.operands[1].reg << 16; | |
13856 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
13857 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
13858 | break; | |
5f4273c7 | 13859 | |
037e8744 JB |
13860 | case NS_FF: /* case 8 (fcpys). */ |
13861 | do_vfp_nsyn_opcode ("fcpys"); | |
13862 | break; | |
5f4273c7 | 13863 | |
037e8744 JB |
13864 | case NS_FI: /* case 10 (fconsts). */ |
13865 | ldconst = "fconsts"; | |
13866 | encode_fconstd: | |
13867 | if (is_quarter_float (inst.operands[1].imm)) | |
5287ad62 | 13868 | { |
037e8744 JB |
13869 | inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); |
13870 | do_vfp_nsyn_opcode (ldconst); | |
5287ad62 JB |
13871 | } |
13872 | else | |
037e8744 JB |
13873 | first_error (_("immediate out of range")); |
13874 | break; | |
5f4273c7 | 13875 | |
037e8744 JB |
13876 | case NS_RF: /* case 12 (fmrs). */ |
13877 | do_vfp_nsyn_opcode ("fmrs"); | |
13878 | break; | |
5f4273c7 | 13879 | |
037e8744 JB |
13880 | case NS_FR: /* case 13 (fmsr). */ |
13881 | do_vfp_nsyn_opcode ("fmsr"); | |
13882 | break; | |
5f4273c7 | 13883 | |
037e8744 JB |
13884 | /* The encoders for the fmrrs and fmsrr instructions expect three operands |
13885 | (one of which is a list), but we have parsed four. Do some fiddling to | |
13886 | make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 | |
13887 | expect. */ | |
13888 | case NS_RRFF: /* case 14 (fmrrs). */ | |
13889 | constraint (inst.operands[3].reg != inst.operands[2].reg + 1, | |
13890 | _("VFP registers must be adjacent")); | |
13891 | inst.operands[2].imm = 2; | |
13892 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
13893 | do_vfp_nsyn_opcode ("fmrrs"); | |
13894 | break; | |
5f4273c7 | 13895 | |
037e8744 JB |
13896 | case NS_FFRR: /* case 15 (fmsrr). */ |
13897 | constraint (inst.operands[1].reg != inst.operands[0].reg + 1, | |
13898 | _("VFP registers must be adjacent")); | |
13899 | inst.operands[1] = inst.operands[2]; | |
13900 | inst.operands[2] = inst.operands[3]; | |
13901 | inst.operands[0].imm = 2; | |
13902 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
13903 | do_vfp_nsyn_opcode ("fmsrr"); | |
5287ad62 | 13904 | break; |
5f4273c7 | 13905 | |
5287ad62 JB |
13906 | default: |
13907 | abort (); | |
13908 | } | |
13909 | } | |
13910 | ||
13911 | static void | |
13912 | do_neon_rshift_round_imm (void) | |
13913 | { | |
037e8744 | 13914 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
13915 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
13916 | int imm = inst.operands[2].imm; | |
13917 | ||
13918 | /* imm == 0 case is encoded as VMOV for V{R}SHR. */ | |
13919 | if (imm == 0) | |
13920 | { | |
13921 | inst.operands[2].present = 0; | |
13922 | do_neon_mov (); | |
13923 | return; | |
13924 | } | |
13925 | ||
13926 | constraint (imm < 1 || (unsigned)imm > et.size, | |
13927 | _("immediate out of range for shift")); | |
037e8744 | 13928 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
13929 | et.size - imm); |
13930 | } | |
13931 | ||
13932 | static void | |
13933 | do_neon_movl (void) | |
13934 | { | |
13935 | struct neon_type_el et = neon_check_type (2, NS_QD, | |
13936 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
13937 | unsigned sizebits = et.size >> 3; | |
13938 | inst.instruction |= sizebits << 19; | |
13939 | neon_two_same (0, et.type == NT_unsigned, -1); | |
13940 | } | |
13941 | ||
13942 | static void | |
13943 | do_neon_trn (void) | |
13944 | { | |
037e8744 | 13945 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
13946 | struct neon_type_el et = neon_check_type (2, rs, |
13947 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
13948 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
037e8744 | 13949 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
13950 | } |
13951 | ||
13952 | static void | |
13953 | do_neon_zip_uzp (void) | |
13954 | { | |
037e8744 | 13955 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
13956 | struct neon_type_el et = neon_check_type (2, rs, |
13957 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
13958 | if (rs == NS_DD && et.size == 32) | |
13959 | { | |
13960 | /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ | |
13961 | inst.instruction = N_MNEM_vtrn; | |
13962 | do_neon_trn (); | |
13963 | return; | |
13964 | } | |
037e8744 | 13965 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
13966 | } |
13967 | ||
13968 | static void | |
13969 | do_neon_sat_abs_neg (void) | |
13970 | { | |
037e8744 | 13971 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
13972 | struct neon_type_el et = neon_check_type (2, rs, |
13973 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 13974 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
13975 | } |
13976 | ||
13977 | static void | |
13978 | do_neon_pair_long (void) | |
13979 | { | |
037e8744 | 13980 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
13981 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); |
13982 | /* Unsigned is encoded in OP field (bit 7) for these instruction. */ | |
13983 | inst.instruction |= (et.type == NT_unsigned) << 7; | |
037e8744 | 13984 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
13985 | } |
13986 | ||
13987 | static void | |
13988 | do_neon_recip_est (void) | |
13989 | { | |
037e8744 | 13990 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
13991 | struct neon_type_el et = neon_check_type (2, rs, |
13992 | N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); | |
13993 | inst.instruction |= (et.type == NT_float) << 8; | |
037e8744 | 13994 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
13995 | } |
13996 | ||
13997 | static void | |
13998 | do_neon_cls (void) | |
13999 | { | |
037e8744 | 14000 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14001 | struct neon_type_el et = neon_check_type (2, rs, |
14002 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 14003 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14004 | } |
14005 | ||
14006 | static void | |
14007 | do_neon_clz (void) | |
14008 | { | |
037e8744 | 14009 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14010 | struct neon_type_el et = neon_check_type (2, rs, |
14011 | N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); | |
037e8744 | 14012 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14013 | } |
14014 | ||
14015 | static void | |
14016 | do_neon_cnt (void) | |
14017 | { | |
037e8744 | 14018 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14019 | struct neon_type_el et = neon_check_type (2, rs, |
14020 | N_EQK | N_INT, N_8 | N_KEY); | |
037e8744 | 14021 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14022 | } |
14023 | ||
14024 | static void | |
14025 | do_neon_swp (void) | |
14026 | { | |
037e8744 JB |
14027 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
14028 | neon_two_same (neon_quad (rs), 1, -1); | |
5287ad62 JB |
14029 | } |
14030 | ||
14031 | static void | |
14032 | do_neon_tbl_tbx (void) | |
14033 | { | |
14034 | unsigned listlenbits; | |
dcbf9037 | 14035 | neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); |
5f4273c7 | 14036 | |
5287ad62 JB |
14037 | if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) |
14038 | { | |
dcbf9037 | 14039 | first_error (_("bad list length for table lookup")); |
5287ad62 JB |
14040 | return; |
14041 | } | |
5f4273c7 | 14042 | |
5287ad62 JB |
14043 | listlenbits = inst.operands[1].imm - 1; |
14044 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14045 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14046 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14047 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14048 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14049 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14050 | inst.instruction |= listlenbits << 8; | |
5f4273c7 | 14051 | |
5287ad62 JB |
14052 | inst.instruction = neon_dp_fixup (inst.instruction); |
14053 | } | |
14054 | ||
14055 | static void | |
14056 | do_neon_ldm_stm (void) | |
14057 | { | |
14058 | /* P, U and L bits are part of bitmask. */ | |
14059 | int is_dbmode = (inst.instruction & (1 << 24)) != 0; | |
14060 | unsigned offsetbits = inst.operands[1].imm * 2; | |
14061 | ||
037e8744 JB |
14062 | if (inst.operands[1].issingle) |
14063 | { | |
14064 | do_vfp_nsyn_ldm_stm (is_dbmode); | |
14065 | return; | |
14066 | } | |
14067 | ||
5287ad62 JB |
14068 | constraint (is_dbmode && !inst.operands[0].writeback, |
14069 | _("writeback (!) must be used for VLDMDB and VSTMDB")); | |
14070 | ||
14071 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
14072 | _("register list must contain at least 1 and at most 16 " | |
14073 | "registers")); | |
14074 | ||
14075 | inst.instruction |= inst.operands[0].reg << 16; | |
14076 | inst.instruction |= inst.operands[0].writeback << 21; | |
14077 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
14078 | inst.instruction |= HI1 (inst.operands[1].reg) << 22; | |
14079 | ||
14080 | inst.instruction |= offsetbits; | |
5f4273c7 | 14081 | |
037e8744 | 14082 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
14083 | } |
14084 | ||
14085 | static void | |
14086 | do_neon_ldr_str (void) | |
14087 | { | |
5287ad62 | 14088 | int is_ldr = (inst.instruction & (1 << 20)) != 0; |
5f4273c7 | 14089 | |
037e8744 JB |
14090 | if (inst.operands[0].issingle) |
14091 | { | |
cd2f129f JB |
14092 | if (is_ldr) |
14093 | do_vfp_nsyn_opcode ("flds"); | |
14094 | else | |
14095 | do_vfp_nsyn_opcode ("fsts"); | |
5287ad62 JB |
14096 | } |
14097 | else | |
5287ad62 | 14098 | { |
cd2f129f JB |
14099 | if (is_ldr) |
14100 | do_vfp_nsyn_opcode ("fldd"); | |
5287ad62 | 14101 | else |
cd2f129f | 14102 | do_vfp_nsyn_opcode ("fstd"); |
5287ad62 | 14103 | } |
5287ad62 JB |
14104 | } |
14105 | ||
14106 | /* "interleave" version also handles non-interleaving register VLD1/VST1 | |
14107 | instructions. */ | |
14108 | ||
14109 | static void | |
14110 | do_neon_ld_st_interleave (void) | |
14111 | { | |
037e8744 | 14112 | struct neon_type_el et = neon_check_type (1, NS_NULL, |
5287ad62 JB |
14113 | N_8 | N_16 | N_32 | N_64); |
14114 | unsigned alignbits = 0; | |
14115 | unsigned idx; | |
14116 | /* The bits in this table go: | |
14117 | 0: register stride of one (0) or two (1) | |
14118 | 1,2: register list length, minus one (1, 2, 3, 4). | |
14119 | 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). | |
14120 | We use -1 for invalid entries. */ | |
14121 | const int typetable[] = | |
14122 | { | |
14123 | 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ | |
14124 | -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ | |
14125 | -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ | |
14126 | -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ | |
14127 | }; | |
14128 | int typebits; | |
14129 | ||
dcbf9037 JB |
14130 | if (et.type == NT_invtype) |
14131 | return; | |
14132 | ||
5287ad62 JB |
14133 | if (inst.operands[1].immisalign) |
14134 | switch (inst.operands[1].imm >> 8) | |
14135 | { | |
14136 | case 64: alignbits = 1; break; | |
14137 | case 128: | |
14138 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3) | |
14139 | goto bad_alignment; | |
14140 | alignbits = 2; | |
14141 | break; | |
14142 | case 256: | |
14143 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3) | |
14144 | goto bad_alignment; | |
14145 | alignbits = 3; | |
14146 | break; | |
14147 | default: | |
14148 | bad_alignment: | |
dcbf9037 | 14149 | first_error (_("bad alignment")); |
5287ad62 JB |
14150 | return; |
14151 | } | |
14152 | ||
14153 | inst.instruction |= alignbits << 4; | |
14154 | inst.instruction |= neon_logbits (et.size) << 6; | |
14155 | ||
14156 | /* Bits [4:6] of the immediate in a list specifier encode register stride | |
14157 | (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of | |
14158 | VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look | |
14159 | up the right value for "type" in a table based on this value and the given | |
14160 | list style, then stick it back. */ | |
14161 | idx = ((inst.operands[0].imm >> 4) & 7) | |
14162 | | (((inst.instruction >> 8) & 3) << 3); | |
14163 | ||
14164 | typebits = typetable[idx]; | |
5f4273c7 | 14165 | |
5287ad62 JB |
14166 | constraint (typebits == -1, _("bad list type for instruction")); |
14167 | ||
14168 | inst.instruction &= ~0xf00; | |
14169 | inst.instruction |= typebits << 8; | |
14170 | } | |
14171 | ||
14172 | /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. | |
14173 | *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 | |
14174 | otherwise. The variable arguments are a list of pairs of legal (size, align) | |
14175 | values, terminated with -1. */ | |
14176 | ||
14177 | static int | |
14178 | neon_alignment_bit (int size, int align, int *do_align, ...) | |
14179 | { | |
14180 | va_list ap; | |
14181 | int result = FAIL, thissize, thisalign; | |
5f4273c7 | 14182 | |
5287ad62 JB |
14183 | if (!inst.operands[1].immisalign) |
14184 | { | |
14185 | *do_align = 0; | |
14186 | return SUCCESS; | |
14187 | } | |
5f4273c7 | 14188 | |
5287ad62 JB |
14189 | va_start (ap, do_align); |
14190 | ||
14191 | do | |
14192 | { | |
14193 | thissize = va_arg (ap, int); | |
14194 | if (thissize == -1) | |
14195 | break; | |
14196 | thisalign = va_arg (ap, int); | |
14197 | ||
14198 | if (size == thissize && align == thisalign) | |
14199 | result = SUCCESS; | |
14200 | } | |
14201 | while (result != SUCCESS); | |
14202 | ||
14203 | va_end (ap); | |
14204 | ||
14205 | if (result == SUCCESS) | |
14206 | *do_align = 1; | |
14207 | else | |
dcbf9037 | 14208 | first_error (_("unsupported alignment for instruction")); |
5f4273c7 | 14209 | |
5287ad62 JB |
14210 | return result; |
14211 | } | |
14212 | ||
14213 | static void | |
14214 | do_neon_ld_st_lane (void) | |
14215 | { | |
037e8744 | 14216 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
14217 | int align_good, do_align = 0; |
14218 | int logsize = neon_logbits (et.size); | |
14219 | int align = inst.operands[1].imm >> 8; | |
14220 | int n = (inst.instruction >> 8) & 3; | |
14221 | int max_el = 64 / et.size; | |
5f4273c7 | 14222 | |
dcbf9037 JB |
14223 | if (et.type == NT_invtype) |
14224 | return; | |
5f4273c7 | 14225 | |
5287ad62 JB |
14226 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, |
14227 | _("bad list length")); | |
14228 | constraint (NEON_LANE (inst.operands[0].imm) >= max_el, | |
14229 | _("scalar index out of range")); | |
14230 | constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 | |
14231 | && et.size == 8, | |
14232 | _("stride of 2 unavailable when element size is 8")); | |
5f4273c7 | 14233 | |
5287ad62 JB |
14234 | switch (n) |
14235 | { | |
14236 | case 0: /* VLD1 / VST1. */ | |
14237 | align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, | |
14238 | 32, 32, -1); | |
14239 | if (align_good == FAIL) | |
14240 | return; | |
14241 | if (do_align) | |
14242 | { | |
14243 | unsigned alignbits = 0; | |
14244 | switch (et.size) | |
14245 | { | |
14246 | case 16: alignbits = 0x1; break; | |
14247 | case 32: alignbits = 0x3; break; | |
14248 | default: ; | |
14249 | } | |
14250 | inst.instruction |= alignbits << 4; | |
14251 | } | |
14252 | break; | |
14253 | ||
14254 | case 1: /* VLD2 / VST2. */ | |
14255 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, | |
14256 | 32, 64, -1); | |
14257 | if (align_good == FAIL) | |
14258 | return; | |
14259 | if (do_align) | |
14260 | inst.instruction |= 1 << 4; | |
14261 | break; | |
14262 | ||
14263 | case 2: /* VLD3 / VST3. */ | |
14264 | constraint (inst.operands[1].immisalign, | |
14265 | _("can't use alignment with this instruction")); | |
14266 | break; | |
14267 | ||
14268 | case 3: /* VLD4 / VST4. */ | |
14269 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
14270 | 16, 64, 32, 64, 32, 128, -1); | |
14271 | if (align_good == FAIL) | |
14272 | return; | |
14273 | if (do_align) | |
14274 | { | |
14275 | unsigned alignbits = 0; | |
14276 | switch (et.size) | |
14277 | { | |
14278 | case 8: alignbits = 0x1; break; | |
14279 | case 16: alignbits = 0x1; break; | |
14280 | case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; | |
14281 | default: ; | |
14282 | } | |
14283 | inst.instruction |= alignbits << 4; | |
14284 | } | |
14285 | break; | |
14286 | ||
14287 | default: ; | |
14288 | } | |
14289 | ||
14290 | /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ | |
14291 | if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
14292 | inst.instruction |= 1 << (4 + logsize); | |
5f4273c7 | 14293 | |
5287ad62 JB |
14294 | inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); |
14295 | inst.instruction |= logsize << 10; | |
14296 | } | |
14297 | ||
14298 | /* Encode single n-element structure to all lanes VLD<n> instructions. */ | |
14299 | ||
14300 | static void | |
14301 | do_neon_ld_dup (void) | |
14302 | { | |
037e8744 | 14303 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
14304 | int align_good, do_align = 0; |
14305 | ||
dcbf9037 JB |
14306 | if (et.type == NT_invtype) |
14307 | return; | |
14308 | ||
5287ad62 JB |
14309 | switch ((inst.instruction >> 8) & 3) |
14310 | { | |
14311 | case 0: /* VLD1. */ | |
14312 | assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); | |
14313 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, | |
14314 | &do_align, 16, 16, 32, 32, -1); | |
14315 | if (align_good == FAIL) | |
14316 | return; | |
14317 | switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) | |
14318 | { | |
14319 | case 1: break; | |
14320 | case 2: inst.instruction |= 1 << 5; break; | |
dcbf9037 | 14321 | default: first_error (_("bad list length")); return; |
5287ad62 JB |
14322 | } |
14323 | inst.instruction |= neon_logbits (et.size) << 6; | |
14324 | break; | |
14325 | ||
14326 | case 1: /* VLD2. */ | |
14327 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, | |
14328 | &do_align, 8, 16, 16, 32, 32, 64, -1); | |
14329 | if (align_good == FAIL) | |
14330 | return; | |
14331 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, | |
14332 | _("bad list length")); | |
14333 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
14334 | inst.instruction |= 1 << 5; | |
14335 | inst.instruction |= neon_logbits (et.size) << 6; | |
14336 | break; | |
14337 | ||
14338 | case 2: /* VLD3. */ | |
14339 | constraint (inst.operands[1].immisalign, | |
14340 | _("can't use alignment with this instruction")); | |
14341 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, | |
14342 | _("bad list length")); | |
14343 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
14344 | inst.instruction |= 1 << 5; | |
14345 | inst.instruction |= neon_logbits (et.size) << 6; | |
14346 | break; | |
14347 | ||
14348 | case 3: /* VLD4. */ | |
14349 | { | |
14350 | int align = inst.operands[1].imm >> 8; | |
14351 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
14352 | 16, 64, 32, 64, 32, 128, -1); | |
14353 | if (align_good == FAIL) | |
14354 | return; | |
14355 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, | |
14356 | _("bad list length")); | |
14357 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
14358 | inst.instruction |= 1 << 5; | |
14359 | if (et.size == 32 && align == 128) | |
14360 | inst.instruction |= 0x3 << 6; | |
14361 | else | |
14362 | inst.instruction |= neon_logbits (et.size) << 6; | |
14363 | } | |
14364 | break; | |
14365 | ||
14366 | default: ; | |
14367 | } | |
14368 | ||
14369 | inst.instruction |= do_align << 4; | |
14370 | } | |
14371 | ||
14372 | /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those | |
14373 | apart from bits [11:4]. */ | |
14374 | ||
14375 | static void | |
14376 | do_neon_ldx_stx (void) | |
14377 | { | |
14378 | switch (NEON_LANE (inst.operands[0].imm)) | |
14379 | { | |
14380 | case NEON_INTERLEAVE_LANES: | |
14381 | inst.instruction = NEON_ENC_INTERLV (inst.instruction); | |
14382 | do_neon_ld_st_interleave (); | |
14383 | break; | |
5f4273c7 | 14384 | |
5287ad62 JB |
14385 | case NEON_ALL_LANES: |
14386 | inst.instruction = NEON_ENC_DUP (inst.instruction); | |
14387 | do_neon_ld_dup (); | |
14388 | break; | |
5f4273c7 | 14389 | |
5287ad62 JB |
14390 | default: |
14391 | inst.instruction = NEON_ENC_LANE (inst.instruction); | |
14392 | do_neon_ld_st_lane (); | |
14393 | } | |
14394 | ||
14395 | /* L bit comes from bit mask. */ | |
14396 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14397 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14398 | inst.instruction |= inst.operands[1].reg << 16; | |
5f4273c7 | 14399 | |
5287ad62 JB |
14400 | if (inst.operands[1].postind) |
14401 | { | |
14402 | int postreg = inst.operands[1].imm & 0xf; | |
14403 | constraint (!inst.operands[1].immisreg, | |
14404 | _("post-index must be a register")); | |
14405 | constraint (postreg == 0xd || postreg == 0xf, | |
14406 | _("bad register for post-index")); | |
14407 | inst.instruction |= postreg; | |
14408 | } | |
14409 | else if (inst.operands[1].writeback) | |
14410 | { | |
14411 | inst.instruction |= 0xd; | |
14412 | } | |
14413 | else | |
5f4273c7 NC |
14414 | inst.instruction |= 0xf; |
14415 | ||
5287ad62 JB |
14416 | if (thumb_mode) |
14417 | inst.instruction |= 0xf9000000; | |
14418 | else | |
14419 | inst.instruction |= 0xf4000000; | |
14420 | } | |
5287ad62 JB |
14421 | \f |
14422 | /* Overall per-instruction processing. */ | |
14423 | ||
14424 | /* We need to be able to fix up arbitrary expressions in some statements. | |
14425 | This is so that we can handle symbols that are an arbitrary distance from | |
14426 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
14427 | which returns part of an address in a form which will be valid for | |
14428 | a data instruction. We do this by pushing the expression into a symbol | |
14429 | in the expr_section, and creating a fix for that. */ | |
14430 | ||
14431 | static void | |
14432 | fix_new_arm (fragS * frag, | |
14433 | int where, | |
14434 | short int size, | |
14435 | expressionS * exp, | |
14436 | int pc_rel, | |
14437 | int reloc) | |
14438 | { | |
14439 | fixS * new_fix; | |
14440 | ||
14441 | switch (exp->X_op) | |
14442 | { | |
14443 | case O_constant: | |
14444 | case O_symbol: | |
14445 | case O_add: | |
14446 | case O_subtract: | |
14447 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc); | |
14448 | break; | |
14449 | ||
14450 | default: | |
14451 | new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0, | |
14452 | pc_rel, reloc); | |
14453 | break; | |
14454 | } | |
14455 | ||
14456 | /* Mark whether the fix is to a THUMB instruction, or an ARM | |
14457 | instruction. */ | |
14458 | new_fix->tc_fix_data = thumb_mode; | |
14459 | } | |
14460 | ||
14461 | /* Create a frg for an instruction requiring relaxation. */ | |
14462 | static void | |
14463 | output_relax_insn (void) | |
14464 | { | |
14465 | char * to; | |
14466 | symbolS *sym; | |
0110f2b8 PB |
14467 | int offset; |
14468 | ||
6e1cb1a6 PB |
14469 | /* The size of the instruction is unknown, so tie the debug info to the |
14470 | start of the instruction. */ | |
14471 | dwarf2_emit_insn (0); | |
6e1cb1a6 | 14472 | |
0110f2b8 PB |
14473 | switch (inst.reloc.exp.X_op) |
14474 | { | |
14475 | case O_symbol: | |
14476 | sym = inst.reloc.exp.X_add_symbol; | |
14477 | offset = inst.reloc.exp.X_add_number; | |
14478 | break; | |
14479 | case O_constant: | |
14480 | sym = NULL; | |
14481 | offset = inst.reloc.exp.X_add_number; | |
14482 | break; | |
14483 | default: | |
14484 | sym = make_expr_symbol (&inst.reloc.exp); | |
14485 | offset = 0; | |
14486 | break; | |
14487 | } | |
14488 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
14489 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
14490 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
0110f2b8 PB |
14491 | } |
14492 | ||
14493 | /* Write a 32-bit thumb instruction to buf. */ | |
14494 | static void | |
14495 | put_thumb32_insn (char * buf, unsigned long insn) | |
14496 | { | |
14497 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
14498 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
14499 | } | |
14500 | ||
b99bd4ef | 14501 | static void |
c19d1205 | 14502 | output_inst (const char * str) |
b99bd4ef | 14503 | { |
c19d1205 | 14504 | char * to = NULL; |
b99bd4ef | 14505 | |
c19d1205 | 14506 | if (inst.error) |
b99bd4ef | 14507 | { |
c19d1205 | 14508 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
14509 | return; |
14510 | } | |
5f4273c7 NC |
14511 | if (inst.relax) |
14512 | { | |
14513 | output_relax_insn (); | |
0110f2b8 | 14514 | return; |
5f4273c7 | 14515 | } |
c19d1205 ZW |
14516 | if (inst.size == 0) |
14517 | return; | |
b99bd4ef | 14518 | |
c19d1205 | 14519 | to = frag_more (inst.size); |
8dc2430f NC |
14520 | /* PR 9814: Record the thumb mode into the current frag so that we know |
14521 | what type of NOP padding to use, if necessary. We override any previous | |
14522 | setting so that if the mode has changed then the NOPS that we use will | |
14523 | match the encoding of the last instruction in the frag. */ | |
14524 | frag_now->tc_frag_data = thumb_mode | MODE_RECORDED; | |
c19d1205 ZW |
14525 | |
14526 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 14527 | { |
c19d1205 | 14528 | assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 14529 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 14530 | } |
c19d1205 | 14531 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 14532 | { |
c19d1205 ZW |
14533 | assert (inst.size == (2 * INSN_SIZE)); |
14534 | md_number_to_chars (to, inst.instruction, INSN_SIZE); | |
14535 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 14536 | } |
c19d1205 ZW |
14537 | else |
14538 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 14539 | |
c19d1205 ZW |
14540 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
14541 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
14542 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
14543 | inst.reloc.type); | |
b99bd4ef | 14544 | |
c19d1205 | 14545 | dwarf2_emit_insn (inst.size); |
c19d1205 | 14546 | } |
b99bd4ef | 14547 | |
e07e6e58 NC |
14548 | static char * |
14549 | output_it_inst (int cond, int mask, char * to) | |
14550 | { | |
14551 | unsigned long instruction = 0xbf00; | |
14552 | ||
14553 | mask &= 0xf; | |
14554 | instruction |= mask; | |
14555 | instruction |= cond << 4; | |
14556 | ||
14557 | if (to == NULL) | |
14558 | { | |
14559 | to = frag_more (2); | |
14560 | #ifdef OBJ_ELF | |
14561 | dwarf2_emit_insn (2); | |
14562 | #endif | |
14563 | } | |
14564 | ||
14565 | md_number_to_chars (to, instruction, 2); | |
14566 | ||
14567 | return to; | |
14568 | } | |
14569 | ||
c19d1205 ZW |
14570 | /* Tag values used in struct asm_opcode's tag field. */ |
14571 | enum opcode_tag | |
14572 | { | |
14573 | OT_unconditional, /* Instruction cannot be conditionalized. | |
14574 | The ARM condition field is still 0xE. */ | |
14575 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
14576 | and carries 0xF in its ARM condition field. */ | |
14577 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
037e8744 JB |
14578 | OT_csuffixF, /* Some forms of the instruction take a conditional |
14579 | suffix, others place 0xF where the condition field | |
14580 | would be. */ | |
c19d1205 ZW |
14581 | OT_cinfix3, /* Instruction takes a conditional infix, |
14582 | beginning at character index 3. (In | |
14583 | unified mode, it becomes a suffix.) */ | |
088fa78e KH |
14584 | OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for |
14585 | tsts, cmps, cmns, and teqs. */ | |
e3cb604e PB |
14586 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
14587 | character index 3, even in unified mode. Used for | |
14588 | legacy instructions where suffix and infix forms | |
14589 | may be ambiguous. */ | |
c19d1205 | 14590 | OT_csuf_or_in3, /* Instruction takes either a conditional |
e3cb604e | 14591 | suffix or an infix at character index 3. */ |
c19d1205 ZW |
14592 | OT_odd_infix_unc, /* This is the unconditional variant of an |
14593 | instruction that takes a conditional infix | |
14594 | at an unusual position. In unified mode, | |
14595 | this variant will accept a suffix. */ | |
14596 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
14597 | are the conditional variants of instructions that | |
14598 | take conditional infixes in unusual positions. | |
14599 | The infix appears at character index | |
14600 | (tag - OT_odd_infix_0). These are not accepted | |
14601 | in unified mode. */ | |
14602 | }; | |
b99bd4ef | 14603 | |
c19d1205 ZW |
14604 | /* Subroutine of md_assemble, responsible for looking up the primary |
14605 | opcode from the mnemonic the user wrote. STR points to the | |
14606 | beginning of the mnemonic. | |
14607 | ||
14608 | This is not simply a hash table lookup, because of conditional | |
14609 | variants. Most instructions have conditional variants, which are | |
14610 | expressed with a _conditional affix_ to the mnemonic. If we were | |
14611 | to encode each conditional variant as a literal string in the opcode | |
14612 | table, it would have approximately 20,000 entries. | |
14613 | ||
14614 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
14615 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
14616 | instructions take the affix as an infix, notably the s-variants of | |
14617 | the arithmetic instructions. Of those instructions, all but six | |
14618 | have the infix appear after the third character of the mnemonic. | |
14619 | ||
14620 | Accordingly, the algorithm for looking up primary opcodes given | |
14621 | an identifier is: | |
14622 | ||
14623 | 1. Look up the identifier in the opcode table. | |
14624 | If we find a match, go to step U. | |
14625 | ||
14626 | 2. Look up the last two characters of the identifier in the | |
14627 | conditions table. If we find a match, look up the first N-2 | |
14628 | characters of the identifier in the opcode table. If we | |
14629 | find a match, go to step CE. | |
14630 | ||
14631 | 3. Look up the fourth and fifth characters of the identifier in | |
14632 | the conditions table. If we find a match, extract those | |
14633 | characters from the identifier, and look up the remaining | |
14634 | characters in the opcode table. If we find a match, go | |
14635 | to step CM. | |
14636 | ||
14637 | 4. Fail. | |
14638 | ||
14639 | U. Examine the tag field of the opcode structure, in case this is | |
14640 | one of the six instructions with its conditional infix in an | |
14641 | unusual place. If it is, the tag tells us where to find the | |
14642 | infix; look it up in the conditions table and set inst.cond | |
14643 | accordingly. Otherwise, this is an unconditional instruction. | |
14644 | Again set inst.cond accordingly. Return the opcode structure. | |
14645 | ||
14646 | CE. Examine the tag field to make sure this is an instruction that | |
14647 | should receive a conditional suffix. If it is not, fail. | |
14648 | Otherwise, set inst.cond from the suffix we already looked up, | |
14649 | and return the opcode structure. | |
14650 | ||
14651 | CM. Examine the tag field to make sure this is an instruction that | |
14652 | should receive a conditional infix after the third character. | |
14653 | If it is not, fail. Otherwise, undo the edits to the current | |
14654 | line of input and proceed as for case CE. */ | |
14655 | ||
14656 | static const struct asm_opcode * | |
14657 | opcode_lookup (char **str) | |
14658 | { | |
14659 | char *end, *base; | |
14660 | char *affix; | |
14661 | const struct asm_opcode *opcode; | |
14662 | const struct asm_cond *cond; | |
e3cb604e | 14663 | char save[2]; |
267d2029 | 14664 | bfd_boolean neon_supported; |
5f4273c7 | 14665 | |
267d2029 | 14666 | neon_supported = ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1); |
c19d1205 ZW |
14667 | |
14668 | /* Scan up to the end of the mnemonic, which must end in white space, | |
267d2029 | 14669 | '.' (in unified mode, or for Neon instructions), or end of string. */ |
c19d1205 | 14670 | for (base = end = *str; *end != '\0'; end++) |
267d2029 | 14671 | if (*end == ' ' || ((unified_syntax || neon_supported) && *end == '.')) |
c19d1205 | 14672 | break; |
b99bd4ef | 14673 | |
c19d1205 ZW |
14674 | if (end == base) |
14675 | return 0; | |
b99bd4ef | 14676 | |
5287ad62 | 14677 | /* Handle a possible width suffix and/or Neon type suffix. */ |
c19d1205 | 14678 | if (end[0] == '.') |
b99bd4ef | 14679 | { |
5287ad62 | 14680 | int offset = 2; |
5f4273c7 | 14681 | |
267d2029 JB |
14682 | /* The .w and .n suffixes are only valid if the unified syntax is in |
14683 | use. */ | |
14684 | if (unified_syntax && end[1] == 'w') | |
c19d1205 | 14685 | inst.size_req = 4; |
267d2029 | 14686 | else if (unified_syntax && end[1] == 'n') |
c19d1205 ZW |
14687 | inst.size_req = 2; |
14688 | else | |
5287ad62 JB |
14689 | offset = 0; |
14690 | ||
14691 | inst.vectype.elems = 0; | |
14692 | ||
14693 | *str = end + offset; | |
b99bd4ef | 14694 | |
5f4273c7 | 14695 | if (end[offset] == '.') |
5287ad62 | 14696 | { |
267d2029 JB |
14697 | /* See if we have a Neon type suffix (possible in either unified or |
14698 | non-unified ARM syntax mode). */ | |
dcbf9037 | 14699 | if (parse_neon_type (&inst.vectype, str) == FAIL) |
5287ad62 JB |
14700 | return 0; |
14701 | } | |
14702 | else if (end[offset] != '\0' && end[offset] != ' ') | |
14703 | return 0; | |
b99bd4ef | 14704 | } |
c19d1205 ZW |
14705 | else |
14706 | *str = end; | |
b99bd4ef | 14707 | |
c19d1205 ZW |
14708 | /* Look for unaffixed or special-case affixed mnemonic. */ |
14709 | opcode = hash_find_n (arm_ops_hsh, base, end - base); | |
14710 | if (opcode) | |
b99bd4ef | 14711 | { |
c19d1205 ZW |
14712 | /* step U */ |
14713 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 14714 | { |
c19d1205 ZW |
14715 | inst.cond = COND_ALWAYS; |
14716 | return opcode; | |
b99bd4ef | 14717 | } |
b99bd4ef | 14718 | |
278df34e | 14719 | if (warn_on_deprecated && unified_syntax) |
c19d1205 ZW |
14720 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
14721 | affix = base + (opcode->tag - OT_odd_infix_0); | |
14722 | cond = hash_find_n (arm_cond_hsh, affix, 2); | |
14723 | assert (cond); | |
b99bd4ef | 14724 | |
c19d1205 ZW |
14725 | inst.cond = cond->value; |
14726 | return opcode; | |
14727 | } | |
b99bd4ef | 14728 | |
c19d1205 ZW |
14729 | /* Cannot have a conditional suffix on a mnemonic of less than two |
14730 | characters. */ | |
14731 | if (end - base < 3) | |
14732 | return 0; | |
b99bd4ef | 14733 | |
c19d1205 ZW |
14734 | /* Look for suffixed mnemonic. */ |
14735 | affix = end - 2; | |
14736 | cond = hash_find_n (arm_cond_hsh, affix, 2); | |
14737 | opcode = hash_find_n (arm_ops_hsh, base, affix - base); | |
14738 | if (opcode && cond) | |
14739 | { | |
14740 | /* step CE */ | |
14741 | switch (opcode->tag) | |
14742 | { | |
e3cb604e PB |
14743 | case OT_cinfix3_legacy: |
14744 | /* Ignore conditional suffixes matched on infix only mnemonics. */ | |
14745 | break; | |
14746 | ||
c19d1205 | 14747 | case OT_cinfix3: |
088fa78e | 14748 | case OT_cinfix3_deprecated: |
c19d1205 ZW |
14749 | case OT_odd_infix_unc: |
14750 | if (!unified_syntax) | |
e3cb604e | 14751 | return 0; |
c19d1205 ZW |
14752 | /* else fall through */ |
14753 | ||
14754 | case OT_csuffix: | |
037e8744 | 14755 | case OT_csuffixF: |
c19d1205 ZW |
14756 | case OT_csuf_or_in3: |
14757 | inst.cond = cond->value; | |
14758 | return opcode; | |
14759 | ||
14760 | case OT_unconditional: | |
14761 | case OT_unconditionalF: | |
dfa9f0d5 PB |
14762 | if (thumb_mode) |
14763 | { | |
14764 | inst.cond = cond->value; | |
14765 | } | |
14766 | else | |
14767 | { | |
14768 | /* delayed diagnostic */ | |
14769 | inst.error = BAD_COND; | |
14770 | inst.cond = COND_ALWAYS; | |
14771 | } | |
c19d1205 | 14772 | return opcode; |
b99bd4ef | 14773 | |
c19d1205 ZW |
14774 | default: |
14775 | return 0; | |
14776 | } | |
14777 | } | |
b99bd4ef | 14778 | |
c19d1205 ZW |
14779 | /* Cannot have a usual-position infix on a mnemonic of less than |
14780 | six characters (five would be a suffix). */ | |
14781 | if (end - base < 6) | |
14782 | return 0; | |
b99bd4ef | 14783 | |
c19d1205 ZW |
14784 | /* Look for infixed mnemonic in the usual position. */ |
14785 | affix = base + 3; | |
14786 | cond = hash_find_n (arm_cond_hsh, affix, 2); | |
e3cb604e PB |
14787 | if (!cond) |
14788 | return 0; | |
14789 | ||
14790 | memcpy (save, affix, 2); | |
14791 | memmove (affix, affix + 2, (end - affix) - 2); | |
14792 | opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2); | |
14793 | memmove (affix + 2, affix, (end - affix) - 2); | |
14794 | memcpy (affix, save, 2); | |
14795 | ||
088fa78e KH |
14796 | if (opcode |
14797 | && (opcode->tag == OT_cinfix3 | |
14798 | || opcode->tag == OT_cinfix3_deprecated | |
14799 | || opcode->tag == OT_csuf_or_in3 | |
14800 | || opcode->tag == OT_cinfix3_legacy)) | |
b99bd4ef | 14801 | { |
c19d1205 | 14802 | /* step CM */ |
278df34e | 14803 | if (warn_on_deprecated && unified_syntax |
088fa78e KH |
14804 | && (opcode->tag == OT_cinfix3 |
14805 | || opcode->tag == OT_cinfix3_deprecated)) | |
c19d1205 ZW |
14806 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
14807 | ||
14808 | inst.cond = cond->value; | |
14809 | return opcode; | |
b99bd4ef NC |
14810 | } |
14811 | ||
c19d1205 | 14812 | return 0; |
b99bd4ef NC |
14813 | } |
14814 | ||
e07e6e58 NC |
14815 | /* This function generates an initial IT instruction, leaving its block |
14816 | virtually open for the new instructions. Eventually, | |
14817 | the mask will be updated by now_it_add_mask () each time | |
14818 | a new instruction needs to be included in the IT block. | |
14819 | Finally, the block is closed with close_automatic_it_block (). | |
14820 | The block closure can be requested either from md_assemble (), | |
14821 | a tencode (), or due to a label hook. */ | |
14822 | ||
14823 | static void | |
14824 | new_automatic_it_block (int cond) | |
14825 | { | |
14826 | now_it.state = AUTOMATIC_IT_BLOCK; | |
14827 | now_it.mask = 0x18; | |
14828 | now_it.cc = cond; | |
14829 | now_it.block_length = 1; | |
14830 | now_it.insn = output_it_inst (cond, now_it.mask, NULL); | |
14831 | } | |
14832 | ||
14833 | /* Close an automatic IT block. | |
14834 | See comments in new_automatic_it_block (). */ | |
14835 | ||
14836 | static void | |
14837 | close_automatic_it_block (void) | |
14838 | { | |
14839 | now_it.mask = 0x10; | |
14840 | now_it.block_length = 0; | |
14841 | } | |
14842 | ||
14843 | /* Update the mask of the current automatically-generated IT | |
14844 | instruction. See comments in new_automatic_it_block (). */ | |
14845 | ||
14846 | static void | |
14847 | now_it_add_mask (int cond) | |
14848 | { | |
14849 | #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit))) | |
14850 | #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \ | |
14851 | | ((bitvalue) << (nbit))) | |
14852 | ||
14853 | const int resulting_bit = (cond & 1); | |
14854 | now_it.mask &= 0xf; | |
14855 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
14856 | resulting_bit, | |
14857 | (5 - now_it.block_length)); | |
14858 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
14859 | 1, | |
14860 | ((5 - now_it.block_length) - 1) ); | |
14861 | output_it_inst (now_it.cc, now_it.mask, now_it.insn); | |
14862 | ||
14863 | #undef CLEAR_BIT | |
14864 | #undef SET_BIT_VALUE | |
14865 | ||
14866 | } | |
14867 | ||
14868 | /* The IT blocks handling machinery is accessed through the these functions: | |
14869 | it_fsm_pre_encode () from md_assemble () | |
14870 | set_it_insn_type () optional, from the tencode functions | |
14871 | set_it_insn_type_last () ditto | |
14872 | in_it_block () ditto | |
14873 | it_fsm_post_encode () from md_assemble () | |
14874 | force_automatic_it_block_close () from label habdling functions | |
14875 | ||
14876 | Rationale: | |
14877 | 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), | |
14878 | initializing the IT insn type with a generic initial value depending | |
14879 | on the inst.condition. | |
14880 | 2) During the tencode function, two things may happen: | |
14881 | a) The tencode function overrides the IT insn type by | |
14882 | calling either set_it_insn_type (type) or set_it_insn_type_last (). | |
14883 | b) The tencode function queries the IT block state by | |
14884 | calling in_it_block () (i.e. to determine narrow/not narrow mode). | |
14885 | ||
14886 | Both set_it_insn_type and in_it_block run the internal FSM state | |
14887 | handling function (handle_it_state), because: a) setting the IT insn | |
14888 | type may incur in an invalid state (exiting the function), | |
14889 | and b) querying the state requires the FSM to be updated. | |
14890 | Specifically we want to avoid creating an IT block for conditional | |
14891 | branches, so it_fsm_pre_encode is actually a guess and we can't | |
14892 | determine whether an IT block is required until the tencode () routine | |
14893 | has decided what type of instruction this actually it. | |
14894 | Because of this, if set_it_insn_type and in_it_block have to be used, | |
14895 | set_it_insn_type has to be called first. | |
14896 | ||
14897 | set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that | |
14898 | determines the insn IT type depending on the inst.cond code. | |
14899 | When a tencode () routine encodes an instruction that can be | |
14900 | either outside an IT block, or, in the case of being inside, has to be | |
14901 | the last one, set_it_insn_type_last () will determine the proper | |
14902 | IT instruction type based on the inst.cond code. Otherwise, | |
14903 | set_it_insn_type can be called for overriding that logic or | |
14904 | for covering other cases. | |
14905 | ||
14906 | Calling handle_it_state () may not transition the IT block state to | |
14907 | OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be | |
14908 | still queried. Instead, if the FSM determines that the state should | |
14909 | be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed | |
14910 | after the tencode () function: that's what it_fsm_post_encode () does. | |
14911 | ||
14912 | Since in_it_block () calls the state handling function to get an | |
14913 | updated state, an error may occur (due to invalid insns combination). | |
14914 | In that case, inst.error is set. | |
14915 | Therefore, inst.error has to be checked after the execution of | |
14916 | the tencode () routine. | |
14917 | ||
14918 | 3) Back in md_assemble(), it_fsm_post_encode () is called to commit | |
14919 | any pending state change (if any) that didn't take place in | |
14920 | handle_it_state () as explained above. */ | |
14921 | ||
14922 | static void | |
14923 | it_fsm_pre_encode (void) | |
14924 | { | |
14925 | if (inst.cond != COND_ALWAYS) | |
14926 | inst.it_insn_type = INSIDE_IT_INSN; | |
14927 | else | |
14928 | inst.it_insn_type = OUTSIDE_IT_INSN; | |
14929 | ||
14930 | now_it.state_handled = 0; | |
14931 | } | |
14932 | ||
14933 | /* IT state FSM handling function. */ | |
14934 | ||
14935 | static int | |
14936 | handle_it_state (void) | |
14937 | { | |
14938 | now_it.state_handled = 1; | |
14939 | ||
14940 | switch (now_it.state) | |
14941 | { | |
14942 | case OUTSIDE_IT_BLOCK: | |
14943 | switch (inst.it_insn_type) | |
14944 | { | |
14945 | case OUTSIDE_IT_INSN: | |
14946 | break; | |
14947 | ||
14948 | case INSIDE_IT_INSN: | |
14949 | case INSIDE_IT_LAST_INSN: | |
14950 | if (thumb_mode == 0) | |
14951 | { | |
14952 | if (unified_syntax | |
14953 | && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM)) | |
14954 | as_tsktsk (_("Warning: conditional outside an IT block"\ | |
14955 | " for Thumb.")); | |
14956 | } | |
14957 | else | |
14958 | { | |
14959 | if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB) | |
14960 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)) | |
14961 | { | |
14962 | /* Automatically generate the IT instruction. */ | |
14963 | new_automatic_it_block (inst.cond); | |
14964 | if (inst.it_insn_type == INSIDE_IT_LAST_INSN) | |
14965 | close_automatic_it_block (); | |
14966 | } | |
14967 | else | |
14968 | { | |
14969 | inst.error = BAD_OUT_IT; | |
14970 | return FAIL; | |
14971 | } | |
14972 | } | |
14973 | break; | |
14974 | ||
14975 | case IF_INSIDE_IT_LAST_INSN: | |
14976 | case NEUTRAL_IT_INSN: | |
14977 | break; | |
14978 | ||
14979 | case IT_INSN: | |
14980 | now_it.state = MANUAL_IT_BLOCK; | |
14981 | now_it.block_length = 0; | |
14982 | break; | |
14983 | } | |
14984 | break; | |
14985 | ||
14986 | case AUTOMATIC_IT_BLOCK: | |
14987 | /* Three things may happen now: | |
14988 | a) We should increment current it block size; | |
14989 | b) We should close current it block (closing insn or 4 insns); | |
14990 | c) We should close current it block and start a new one (due | |
14991 | to incompatible conditions or | |
14992 | 4 insns-length block reached). */ | |
14993 | ||
14994 | switch (inst.it_insn_type) | |
14995 | { | |
14996 | case OUTSIDE_IT_INSN: | |
14997 | /* The closure of the block shall happen immediatelly, | |
14998 | so any in_it_block () call reports the block as closed. */ | |
14999 | force_automatic_it_block_close (); | |
15000 | break; | |
15001 | ||
15002 | case INSIDE_IT_INSN: | |
15003 | case INSIDE_IT_LAST_INSN: | |
15004 | case IF_INSIDE_IT_LAST_INSN: | |
15005 | now_it.block_length++; | |
15006 | ||
15007 | if (now_it.block_length > 4 | |
15008 | || !now_it_compatible (inst.cond)) | |
15009 | { | |
15010 | force_automatic_it_block_close (); | |
15011 | if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN) | |
15012 | new_automatic_it_block (inst.cond); | |
15013 | } | |
15014 | else | |
15015 | { | |
15016 | now_it_add_mask (inst.cond); | |
15017 | } | |
15018 | ||
15019 | if (now_it.state == AUTOMATIC_IT_BLOCK | |
15020 | && (inst.it_insn_type == INSIDE_IT_LAST_INSN | |
15021 | || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN)) | |
15022 | close_automatic_it_block (); | |
15023 | break; | |
15024 | ||
15025 | case NEUTRAL_IT_INSN: | |
15026 | now_it.block_length++; | |
15027 | ||
15028 | if (now_it.block_length > 4) | |
15029 | force_automatic_it_block_close (); | |
15030 | else | |
15031 | now_it_add_mask (now_it.cc & 1); | |
15032 | break; | |
15033 | ||
15034 | case IT_INSN: | |
15035 | close_automatic_it_block (); | |
15036 | now_it.state = MANUAL_IT_BLOCK; | |
15037 | break; | |
15038 | } | |
15039 | break; | |
15040 | ||
15041 | case MANUAL_IT_BLOCK: | |
15042 | { | |
15043 | /* Check conditional suffixes. */ | |
15044 | const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1; | |
15045 | int is_last; | |
15046 | now_it.mask <<= 1; | |
15047 | now_it.mask &= 0x1f; | |
15048 | is_last = (now_it.mask == 0x10); | |
15049 | ||
15050 | switch (inst.it_insn_type) | |
15051 | { | |
15052 | case OUTSIDE_IT_INSN: | |
15053 | inst.error = BAD_NOT_IT; | |
15054 | return FAIL; | |
15055 | ||
15056 | case INSIDE_IT_INSN: | |
15057 | if (cond != inst.cond) | |
15058 | { | |
15059 | inst.error = BAD_IT_COND; | |
15060 | return FAIL; | |
15061 | } | |
15062 | break; | |
15063 | ||
15064 | case INSIDE_IT_LAST_INSN: | |
15065 | case IF_INSIDE_IT_LAST_INSN: | |
15066 | if (cond != inst.cond) | |
15067 | { | |
15068 | inst.error = BAD_IT_COND; | |
15069 | return FAIL; | |
15070 | } | |
15071 | if (!is_last) | |
15072 | { | |
15073 | inst.error = BAD_BRANCH; | |
15074 | return FAIL; | |
15075 | } | |
15076 | break; | |
15077 | ||
15078 | case NEUTRAL_IT_INSN: | |
15079 | /* The BKPT instruction is unconditional even in an IT block. */ | |
15080 | break; | |
15081 | ||
15082 | case IT_INSN: | |
15083 | inst.error = BAD_IT_IT; | |
15084 | return FAIL; | |
15085 | } | |
15086 | } | |
15087 | break; | |
15088 | } | |
15089 | ||
15090 | return SUCCESS; | |
15091 | } | |
15092 | ||
15093 | static void | |
15094 | it_fsm_post_encode (void) | |
15095 | { | |
15096 | int is_last; | |
15097 | ||
15098 | if (!now_it.state_handled) | |
15099 | handle_it_state (); | |
15100 | ||
15101 | is_last = (now_it.mask == 0x10); | |
15102 | if (is_last) | |
15103 | { | |
15104 | now_it.state = OUTSIDE_IT_BLOCK; | |
15105 | now_it.mask = 0; | |
15106 | } | |
15107 | } | |
15108 | ||
15109 | static void | |
15110 | force_automatic_it_block_close (void) | |
15111 | { | |
15112 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
15113 | { | |
15114 | close_automatic_it_block (); | |
15115 | now_it.state = OUTSIDE_IT_BLOCK; | |
15116 | now_it.mask = 0; | |
15117 | } | |
15118 | } | |
15119 | ||
15120 | static int | |
15121 | in_it_block (void) | |
15122 | { | |
15123 | if (!now_it.state_handled) | |
15124 | handle_it_state (); | |
15125 | ||
15126 | return now_it.state != OUTSIDE_IT_BLOCK; | |
15127 | } | |
15128 | ||
c19d1205 ZW |
15129 | void |
15130 | md_assemble (char *str) | |
b99bd4ef | 15131 | { |
c19d1205 ZW |
15132 | char *p = str; |
15133 | const struct asm_opcode * opcode; | |
b99bd4ef | 15134 | |
c19d1205 ZW |
15135 | /* Align the previous label if needed. */ |
15136 | if (last_label_seen != NULL) | |
b99bd4ef | 15137 | { |
c19d1205 ZW |
15138 | symbol_set_frag (last_label_seen, frag_now); |
15139 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
15140 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
15141 | } |
15142 | ||
c19d1205 ZW |
15143 | memset (&inst, '\0', sizeof (inst)); |
15144 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 15145 | |
c19d1205 ZW |
15146 | opcode = opcode_lookup (&p); |
15147 | if (!opcode) | |
b99bd4ef | 15148 | { |
c19d1205 | 15149 | /* It wasn't an instruction, but it might be a register alias of |
dcbf9037 JB |
15150 | the form alias .req reg, or a Neon .dn/.qn directive. */ |
15151 | if (!create_register_alias (str, p) | |
15152 | && !create_neon_reg_alias (str, p)) | |
c19d1205 | 15153 | as_bad (_("bad instruction `%s'"), str); |
b99bd4ef | 15154 | |
b99bd4ef NC |
15155 | return; |
15156 | } | |
15157 | ||
278df34e | 15158 | if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated) |
088fa78e KH |
15159 | as_warn (_("s suffix on comparison instruction is deprecated")); |
15160 | ||
037e8744 JB |
15161 | /* The value which unconditional instructions should have in place of the |
15162 | condition field. */ | |
15163 | inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; | |
15164 | ||
c19d1205 | 15165 | if (thumb_mode) |
b99bd4ef | 15166 | { |
e74cfd16 | 15167 | arm_feature_set variant; |
8f06b2d8 PB |
15168 | |
15169 | variant = cpu_variant; | |
15170 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
e74cfd16 PB |
15171 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
15172 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); | |
c19d1205 | 15173 | /* Check that this instruction is supported for this CPU. */ |
62b3e311 PB |
15174 | if (!opcode->tvariant |
15175 | || (thumb_mode == 1 | |
15176 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) | |
b99bd4ef | 15177 | { |
c19d1205 | 15178 | as_bad (_("selected processor does not support `%s'"), str); |
b99bd4ef NC |
15179 | return; |
15180 | } | |
c19d1205 ZW |
15181 | if (inst.cond != COND_ALWAYS && !unified_syntax |
15182 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 15183 | { |
c19d1205 | 15184 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
15185 | return; |
15186 | } | |
15187 | ||
076d447c PB |
15188 | if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) && !inst.size_req) |
15189 | { | |
15190 | /* Implicit require narrow instructions on Thumb-1. This avoids | |
15191 | relaxation accidentally introducing Thumb-2 instructions. */ | |
7e806470 | 15192 | if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23 |
e07e6e58 NC |
15193 | && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) |
15194 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))) | |
076d447c PB |
15195 | inst.size_req = 2; |
15196 | } | |
15197 | ||
c19d1205 ZW |
15198 | mapping_state (MAP_THUMB); |
15199 | inst.instruction = opcode->tvalue; | |
15200 | ||
15201 | if (!parse_operands (p, opcode->operands)) | |
e07e6e58 NC |
15202 | { |
15203 | /* Prepare the it_insn_type for those encodings that don't set | |
15204 | it. */ | |
15205 | it_fsm_pre_encode (); | |
c19d1205 | 15206 | |
e07e6e58 NC |
15207 | opcode->tencode (); |
15208 | ||
15209 | it_fsm_post_encode (); | |
15210 | } | |
e27ec89e | 15211 | |
0110f2b8 | 15212 | if (!(inst.error || inst.relax)) |
b99bd4ef | 15213 | { |
c19d1205 ZW |
15214 | assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
15215 | inst.size = (inst.instruction > 0xffff ? 4 : 2); | |
15216 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 15217 | { |
c19d1205 | 15218 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
15219 | return; |
15220 | } | |
15221 | } | |
076d447c PB |
15222 | |
15223 | /* Something has gone badly wrong if we try to relax a fixed size | |
15224 | instruction. */ | |
15225 | assert (inst.size_req == 0 || !inst.relax); | |
15226 | ||
e74cfd16 PB |
15227 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
15228 | *opcode->tvariant); | |
ee065d83 | 15229 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
708587a4 | 15230 | set those bits when Thumb-2 32-bit instructions are seen. ie. |
7e806470 | 15231 | anything other than bl/blx and v6-M instructions. |
ee065d83 | 15232 | This is overly pessimistic for relaxable instructions. */ |
7e806470 PB |
15233 | if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) |
15234 | || inst.relax) | |
e07e6e58 NC |
15235 | && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) |
15236 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))) | |
e74cfd16 PB |
15237 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
15238 | arm_ext_v6t2); | |
c19d1205 | 15239 | } |
3e9e4fcf | 15240 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 | 15241 | { |
845b51d6 PB |
15242 | bfd_boolean is_bx; |
15243 | ||
15244 | /* bx is allowed on v5 cores, and sometimes on v4 cores. */ | |
15245 | is_bx = (opcode->aencode == do_bx); | |
15246 | ||
c19d1205 | 15247 | /* Check that this instruction is supported for this CPU. */ |
845b51d6 PB |
15248 | if (!(is_bx && fix_v4bx) |
15249 | && !(opcode->avariant && | |
15250 | ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))) | |
b99bd4ef | 15251 | { |
c19d1205 ZW |
15252 | as_bad (_("selected processor does not support `%s'"), str); |
15253 | return; | |
b99bd4ef | 15254 | } |
c19d1205 | 15255 | if (inst.size_req) |
b99bd4ef | 15256 | { |
c19d1205 ZW |
15257 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
15258 | return; | |
b99bd4ef NC |
15259 | } |
15260 | ||
c19d1205 ZW |
15261 | mapping_state (MAP_ARM); |
15262 | inst.instruction = opcode->avalue; | |
15263 | if (opcode->tag == OT_unconditionalF) | |
15264 | inst.instruction |= 0xF << 28; | |
15265 | else | |
15266 | inst.instruction |= inst.cond << 28; | |
15267 | inst.size = INSN_SIZE; | |
15268 | if (!parse_operands (p, opcode->operands)) | |
e07e6e58 NC |
15269 | { |
15270 | it_fsm_pre_encode (); | |
15271 | opcode->aencode (); | |
15272 | it_fsm_post_encode (); | |
15273 | } | |
ee065d83 PB |
15274 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
15275 | on a hypothetical non-thumb v5 core. */ | |
845b51d6 | 15276 | if (is_bx) |
e74cfd16 | 15277 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); |
ee065d83 | 15278 | else |
e74cfd16 PB |
15279 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
15280 | *opcode->avariant); | |
b99bd4ef | 15281 | } |
3e9e4fcf JB |
15282 | else |
15283 | { | |
15284 | as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " | |
15285 | "-- `%s'"), str); | |
15286 | return; | |
15287 | } | |
c19d1205 ZW |
15288 | output_inst (str); |
15289 | } | |
b99bd4ef | 15290 | |
e07e6e58 NC |
15291 | static void |
15292 | check_it_blocks_finished (void) | |
15293 | { | |
15294 | #ifdef OBJ_ELF | |
15295 | asection *sect; | |
15296 | ||
15297 | for (sect = stdoutput->sections; sect != NULL; sect = sect->next) | |
15298 | if (seg_info (sect)->tc_segment_info_data.current_it.state | |
15299 | == MANUAL_IT_BLOCK) | |
15300 | { | |
15301 | as_warn (_("section '%s' finished with an open IT block."), | |
15302 | sect->name); | |
15303 | } | |
15304 | #else | |
15305 | if (now_it.state == MANUAL_IT_BLOCK) | |
15306 | as_warn (_("file finished with an open IT block.")); | |
15307 | #endif | |
15308 | } | |
15309 | ||
c19d1205 ZW |
15310 | /* Various frobbings of labels and their addresses. */ |
15311 | ||
15312 | void | |
15313 | arm_start_line_hook (void) | |
15314 | { | |
15315 | last_label_seen = NULL; | |
b99bd4ef NC |
15316 | } |
15317 | ||
c19d1205 ZW |
15318 | void |
15319 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 15320 | { |
c19d1205 | 15321 | last_label_seen = sym; |
b99bd4ef | 15322 | |
c19d1205 | 15323 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 15324 | |
c19d1205 ZW |
15325 | #if defined OBJ_COFF || defined OBJ_ELF |
15326 | ARM_SET_INTERWORK (sym, support_interwork); | |
15327 | #endif | |
b99bd4ef | 15328 | |
e07e6e58 NC |
15329 | force_automatic_it_block_close (); |
15330 | ||
5f4273c7 | 15331 | /* Note - do not allow local symbols (.Lxxx) to be labelled |
c19d1205 ZW |
15332 | as Thumb functions. This is because these labels, whilst |
15333 | they exist inside Thumb code, are not the entry points for | |
15334 | possible ARM->Thumb calls. Also, these labels can be used | |
15335 | as part of a computed goto or switch statement. eg gcc | |
15336 | can generate code that looks like this: | |
b99bd4ef | 15337 | |
c19d1205 ZW |
15338 | ldr r2, [pc, .Laaa] |
15339 | lsl r3, r3, #2 | |
15340 | ldr r2, [r3, r2] | |
15341 | mov pc, r2 | |
b99bd4ef | 15342 | |
c19d1205 ZW |
15343 | .Lbbb: .word .Lxxx |
15344 | .Lccc: .word .Lyyy | |
15345 | ..etc... | |
15346 | .Laaa: .word Lbbb | |
b99bd4ef | 15347 | |
c19d1205 ZW |
15348 | The first instruction loads the address of the jump table. |
15349 | The second instruction converts a table index into a byte offset. | |
15350 | The third instruction gets the jump address out of the table. | |
15351 | The fourth instruction performs the jump. | |
b99bd4ef | 15352 | |
c19d1205 ZW |
15353 | If the address stored at .Laaa is that of a symbol which has the |
15354 | Thumb_Func bit set, then the linker will arrange for this address | |
15355 | to have the bottom bit set, which in turn would mean that the | |
15356 | address computation performed by the third instruction would end | |
15357 | up with the bottom bit set. Since the ARM is capable of unaligned | |
15358 | word loads, the instruction would then load the incorrect address | |
15359 | out of the jump table, and chaos would ensue. */ | |
15360 | if (label_is_thumb_function_name | |
15361 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
15362 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 15363 | { |
c19d1205 ZW |
15364 | /* When the address of a Thumb function is taken the bottom |
15365 | bit of that address should be set. This will allow | |
15366 | interworking between Arm and Thumb functions to work | |
15367 | correctly. */ | |
b99bd4ef | 15368 | |
c19d1205 | 15369 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 15370 | |
c19d1205 | 15371 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 15372 | } |
07a53e5c | 15373 | |
07a53e5c | 15374 | dwarf2_emit_label (sym); |
b99bd4ef NC |
15375 | } |
15376 | ||
c19d1205 ZW |
15377 | int |
15378 | arm_data_in_code (void) | |
b99bd4ef | 15379 | { |
c19d1205 | 15380 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 15381 | { |
c19d1205 ZW |
15382 | *input_line_pointer = '/'; |
15383 | input_line_pointer += 5; | |
15384 | *input_line_pointer = 0; | |
15385 | return 1; | |
b99bd4ef NC |
15386 | } |
15387 | ||
c19d1205 | 15388 | return 0; |
b99bd4ef NC |
15389 | } |
15390 | ||
c19d1205 ZW |
15391 | char * |
15392 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 15393 | { |
c19d1205 | 15394 | int len; |
b99bd4ef | 15395 | |
c19d1205 ZW |
15396 | if (thumb_mode && (len = strlen (name)) > 5 |
15397 | && streq (name + len - 5, "/data")) | |
15398 | *(name + len - 5) = 0; | |
b99bd4ef | 15399 | |
c19d1205 | 15400 | return name; |
b99bd4ef | 15401 | } |
c19d1205 ZW |
15402 | \f |
15403 | /* Table of all register names defined by default. The user can | |
15404 | define additional names with .req. Note that all register names | |
15405 | should appear in both upper and lowercase variants. Some registers | |
15406 | also have mixed-case names. */ | |
b99bd4ef | 15407 | |
dcbf9037 | 15408 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } |
c19d1205 | 15409 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) |
5287ad62 | 15410 | #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) |
c19d1205 ZW |
15411 | #define REGSET(p,t) \ |
15412 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
15413 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
15414 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
15415 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
5287ad62 JB |
15416 | #define REGSETH(p,t) \ |
15417 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ | |
15418 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ | |
15419 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ | |
15420 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) | |
15421 | #define REGSET2(p,t) \ | |
15422 | REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ | |
15423 | REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ | |
15424 | REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ | |
15425 | REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) | |
7ed4c4c5 | 15426 | |
c19d1205 | 15427 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 15428 | { |
c19d1205 ZW |
15429 | /* ARM integer registers. */ |
15430 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 15431 | |
c19d1205 ZW |
15432 | /* ATPCS synonyms. */ |
15433 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
15434 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
15435 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 15436 | |
c19d1205 ZW |
15437 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
15438 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
15439 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 15440 | |
c19d1205 ZW |
15441 | /* Well-known aliases. */ |
15442 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
15443 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
15444 | ||
15445 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
15446 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
15447 | ||
15448 | /* Coprocessor numbers. */ | |
15449 | REGSET(p, CP), REGSET(P, CP), | |
15450 | ||
15451 | /* Coprocessor register numbers. The "cr" variants are for backward | |
15452 | compatibility. */ | |
15453 | REGSET(c, CN), REGSET(C, CN), | |
15454 | REGSET(cr, CN), REGSET(CR, CN), | |
15455 | ||
15456 | /* FPA registers. */ | |
15457 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
15458 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
15459 | ||
15460 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
15461 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
15462 | ||
15463 | /* VFP SP registers. */ | |
5287ad62 JB |
15464 | REGSET(s,VFS), REGSET(S,VFS), |
15465 | REGSETH(s,VFS), REGSETH(S,VFS), | |
c19d1205 ZW |
15466 | |
15467 | /* VFP DP Registers. */ | |
5287ad62 JB |
15468 | REGSET(d,VFD), REGSET(D,VFD), |
15469 | /* Extra Neon DP registers. */ | |
15470 | REGSETH(d,VFD), REGSETH(D,VFD), | |
15471 | ||
15472 | /* Neon QP registers. */ | |
15473 | REGSET2(q,NQ), REGSET2(Q,NQ), | |
c19d1205 ZW |
15474 | |
15475 | /* VFP control registers. */ | |
15476 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
15477 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
cd2cf30b PB |
15478 | REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), |
15479 | REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), | |
15480 | REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), | |
15481 | REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), | |
c19d1205 ZW |
15482 | |
15483 | /* Maverick DSP coprocessor registers. */ | |
15484 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
15485 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
15486 | ||
15487 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
15488 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
15489 | REGDEF(dspsc,0,DSPSC), | |
15490 | ||
15491 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
15492 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
15493 | REGDEF(DSPSC,0,DSPSC), | |
15494 | ||
15495 | /* iWMMXt data registers - p0, c0-15. */ | |
15496 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
15497 | ||
15498 | /* iWMMXt control registers - p1, c0-3. */ | |
15499 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
15500 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
15501 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
15502 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
15503 | ||
15504 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
15505 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
15506 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
15507 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
15508 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
15509 | ||
15510 | /* XScale accumulator registers. */ | |
15511 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
15512 | }; | |
15513 | #undef REGDEF | |
15514 | #undef REGNUM | |
15515 | #undef REGSET | |
7ed4c4c5 | 15516 | |
c19d1205 ZW |
15517 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
15518 | within psr_required_here. */ | |
15519 | static const struct asm_psr psrs[] = | |
15520 | { | |
15521 | /* Backward compatibility notation. Note that "all" is no longer | |
15522 | truly all possible PSR bits. */ | |
15523 | {"all", PSR_c | PSR_f}, | |
15524 | {"flg", PSR_f}, | |
15525 | {"ctl", PSR_c}, | |
15526 | ||
15527 | /* Individual flags. */ | |
15528 | {"f", PSR_f}, | |
15529 | {"c", PSR_c}, | |
15530 | {"x", PSR_x}, | |
15531 | {"s", PSR_s}, | |
15532 | /* Combinations of flags. */ | |
15533 | {"fs", PSR_f | PSR_s}, | |
15534 | {"fx", PSR_f | PSR_x}, | |
15535 | {"fc", PSR_f | PSR_c}, | |
15536 | {"sf", PSR_s | PSR_f}, | |
15537 | {"sx", PSR_s | PSR_x}, | |
15538 | {"sc", PSR_s | PSR_c}, | |
15539 | {"xf", PSR_x | PSR_f}, | |
15540 | {"xs", PSR_x | PSR_s}, | |
15541 | {"xc", PSR_x | PSR_c}, | |
15542 | {"cf", PSR_c | PSR_f}, | |
15543 | {"cs", PSR_c | PSR_s}, | |
15544 | {"cx", PSR_c | PSR_x}, | |
15545 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
15546 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
15547 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
15548 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
15549 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
15550 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
15551 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
15552 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
15553 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
15554 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
15555 | {"scf", PSR_s | PSR_c | PSR_f}, | |
15556 | {"scx", PSR_s | PSR_c | PSR_x}, | |
15557 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
15558 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
15559 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
15560 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
15561 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
15562 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
15563 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
15564 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
15565 | {"csf", PSR_c | PSR_s | PSR_f}, | |
15566 | {"csx", PSR_c | PSR_s | PSR_x}, | |
15567 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
15568 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
15569 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
15570 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
15571 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
15572 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
15573 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
15574 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
15575 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
15576 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
15577 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
15578 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
15579 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
15580 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
15581 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
15582 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
15583 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
15584 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
15585 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
15586 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
15587 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
15588 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
15589 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
15590 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
15591 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
15592 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
15593 | }; | |
15594 | ||
62b3e311 PB |
15595 | /* Table of V7M psr names. */ |
15596 | static const struct asm_psr v7m_psrs[] = | |
15597 | { | |
2b744c99 PB |
15598 | {"apsr", 0 }, {"APSR", 0 }, |
15599 | {"iapsr", 1 }, {"IAPSR", 1 }, | |
15600 | {"eapsr", 2 }, {"EAPSR", 2 }, | |
15601 | {"psr", 3 }, {"PSR", 3 }, | |
15602 | {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, | |
15603 | {"ipsr", 5 }, {"IPSR", 5 }, | |
15604 | {"epsr", 6 }, {"EPSR", 6 }, | |
15605 | {"iepsr", 7 }, {"IEPSR", 7 }, | |
15606 | {"msp", 8 }, {"MSP", 8 }, | |
15607 | {"psp", 9 }, {"PSP", 9 }, | |
15608 | {"primask", 16}, {"PRIMASK", 16}, | |
15609 | {"basepri", 17}, {"BASEPRI", 17}, | |
15610 | {"basepri_max", 18}, {"BASEPRI_MAX", 18}, | |
15611 | {"faultmask", 19}, {"FAULTMASK", 19}, | |
15612 | {"control", 20}, {"CONTROL", 20} | |
62b3e311 PB |
15613 | }; |
15614 | ||
c19d1205 ZW |
15615 | /* Table of all shift-in-operand names. */ |
15616 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 15617 | { |
c19d1205 ZW |
15618 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
15619 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
15620 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
15621 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
15622 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
15623 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } | |
15624 | }; | |
b99bd4ef | 15625 | |
c19d1205 ZW |
15626 | /* Table of all explicit relocation names. */ |
15627 | #ifdef OBJ_ELF | |
15628 | static struct reloc_entry reloc_names[] = | |
15629 | { | |
15630 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
15631 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
15632 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
15633 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
15634 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
15635 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
15636 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
15637 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
15638 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
15639 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
15640 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32} | |
15641 | }; | |
15642 | #endif | |
b99bd4ef | 15643 | |
c19d1205 ZW |
15644 | /* Table of all conditional affixes. 0xF is not defined as a condition code. */ |
15645 | static const struct asm_cond conds[] = | |
15646 | { | |
15647 | {"eq", 0x0}, | |
15648 | {"ne", 0x1}, | |
15649 | {"cs", 0x2}, {"hs", 0x2}, | |
15650 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
15651 | {"mi", 0x4}, | |
15652 | {"pl", 0x5}, | |
15653 | {"vs", 0x6}, | |
15654 | {"vc", 0x7}, | |
15655 | {"hi", 0x8}, | |
15656 | {"ls", 0x9}, | |
15657 | {"ge", 0xa}, | |
15658 | {"lt", 0xb}, | |
15659 | {"gt", 0xc}, | |
15660 | {"le", 0xd}, | |
15661 | {"al", 0xe} | |
15662 | }; | |
bfae80f2 | 15663 | |
62b3e311 PB |
15664 | static struct asm_barrier_opt barrier_opt_names[] = |
15665 | { | |
15666 | { "sy", 0xf }, | |
15667 | { "un", 0x7 }, | |
15668 | { "st", 0xe }, | |
15669 | { "unst", 0x6 } | |
15670 | }; | |
15671 | ||
c19d1205 ZW |
15672 | /* Table of ARM-format instructions. */ |
15673 | ||
15674 | /* Macros for gluing together operand strings. N.B. In all cases | |
15675 | other than OPS0, the trailing OP_stop comes from default | |
15676 | zero-initialization of the unspecified elements of the array. */ | |
15677 | #define OPS0() { OP_stop, } | |
15678 | #define OPS1(a) { OP_##a, } | |
15679 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
15680 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
15681 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
15682 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
15683 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
15684 | ||
15685 | /* These macros abstract out the exact format of the mnemonic table and | |
15686 | save some repeated characters. */ | |
15687 | ||
15688 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
15689 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
15690 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ | |
1887dd22 | 15691 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
15692 | |
15693 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
15694 | a T_MNEM_xyz enumerator. */ | |
15695 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
e07e6e58 | 15696 | TxCE (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 15697 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 15698 | TxCE (mnem, aop, T_MNEM_##top, nops, ops, ae, te) |
c19d1205 ZW |
15699 | |
15700 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
15701 | infix after the third character. */ | |
15702 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
15703 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ | |
1887dd22 | 15704 | THUMB_VARIANT, do_##ae, do_##te } |
088fa78e KH |
15705 | #define TxC3w(mnem, op, top, nops, ops, ae, te) \ |
15706 | { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ | |
15707 | THUMB_VARIANT, do_##ae, do_##te } | |
c19d1205 | 15708 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 15709 | TxC3 (mnem, aop, 0x##top, nops, ops, ae, te) |
088fa78e | 15710 | #define TC3w(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 15711 | TxC3w (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 15712 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 15713 | TxC3 (mnem, aop, T_MNEM_##top, nops, ops, ae, te) |
088fa78e | 15714 | #define tC3w(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 15715 | TxC3w (mnem, aop, T_MNEM_##top, nops, ops, ae, te) |
c19d1205 ZW |
15716 | |
15717 | /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to | |
15718 | appear in the condition table. */ | |
15719 | #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ | |
e07e6e58 | 15720 | { #m1 #m2 #m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (#m1) - 1, \ |
1887dd22 | 15721 | 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
15722 | |
15723 | #define TxCM(m1, m2, op, top, nops, ops, ae, te) \ | |
e07e6e58 NC |
15724 | TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \ |
15725 | TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \ | |
15726 | TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \ | |
15727 | TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \ | |
15728 | TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \ | |
15729 | TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \ | |
15730 | TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \ | |
15731 | TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \ | |
15732 | TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \ | |
15733 | TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \ | |
15734 | TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \ | |
15735 | TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \ | |
15736 | TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \ | |
15737 | TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \ | |
15738 | TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \ | |
15739 | TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \ | |
15740 | TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \ | |
15741 | TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \ | |
15742 | TxCM_ (m1, al, m2, op, top, nops, ops, ae, te) | |
c19d1205 ZW |
15743 | |
15744 | #define TCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
e07e6e58 NC |
15745 | TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te) |
15746 | #define tCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
15747 | TxCM (m1,m2, aop, T_MNEM_##top, nops, ops, ae, te) | |
c19d1205 ZW |
15748 | |
15749 | /* Mnemonic that cannot be conditionalized. The ARM condition-code | |
dfa9f0d5 PB |
15750 | field is still 0xE. Many of the Thumb variants can be executed |
15751 | conditionally, so this is checked separately. */ | |
c19d1205 ZW |
15752 | #define TUE(mnem, op, top, nops, ops, ae, te) \ |
15753 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ | |
1887dd22 | 15754 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
15755 | |
15756 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM | |
15757 | condition code field. */ | |
15758 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
15759 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ | |
1887dd22 | 15760 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
15761 | |
15762 | /* ARM-only variants of all the above. */ | |
6a86118a NC |
15763 | #define CE(mnem, op, nops, ops, ae) \ |
15764 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
15765 | ||
15766 | #define C3(mnem, op, nops, ops, ae) \ | |
15767 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
15768 | ||
e3cb604e PB |
15769 | /* Legacy mnemonics that always have conditional infix after the third |
15770 | character. */ | |
15771 | #define CL(mnem, op, nops, ops, ae) \ | |
15772 | { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ | |
15773 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
15774 | ||
8f06b2d8 PB |
15775 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
15776 | #define cCE(mnem, op, nops, ops, ae) \ | |
15777 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } | |
15778 | ||
e3cb604e PB |
15779 | /* Legacy coprocessor instructions where conditional infix and conditional |
15780 | suffix are ambiguous. For consistency this includes all FPA instructions, | |
15781 | not just the potentially ambiguous ones. */ | |
15782 | #define cCL(mnem, op, nops, ops, ae) \ | |
15783 | { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ | |
15784 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } | |
15785 | ||
15786 | /* Coprocessor, takes either a suffix or a position-3 infix | |
15787 | (for an FPA corner case). */ | |
15788 | #define C3E(mnem, op, nops, ops, ae) \ | |
15789 | { #mnem, OPS##nops ops, OT_csuf_or_in3, \ | |
15790 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } | |
8f06b2d8 | 15791 | |
6a86118a NC |
15792 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
15793 | { #m1 #m2 #m3, OPS##nops ops, \ | |
e07e6e58 | 15794 | sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (#m1) - 1, \ |
6a86118a NC |
15795 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
15796 | ||
15797 | #define CM(m1, m2, op, nops, ops, ae) \ | |
e07e6e58 NC |
15798 | xCM_ (m1, , m2, op, nops, ops, ae), \ |
15799 | xCM_ (m1, eq, m2, op, nops, ops, ae), \ | |
15800 | xCM_ (m1, ne, m2, op, nops, ops, ae), \ | |
15801 | xCM_ (m1, cs, m2, op, nops, ops, ae), \ | |
15802 | xCM_ (m1, hs, m2, op, nops, ops, ae), \ | |
15803 | xCM_ (m1, cc, m2, op, nops, ops, ae), \ | |
15804 | xCM_ (m1, ul, m2, op, nops, ops, ae), \ | |
15805 | xCM_ (m1, lo, m2, op, nops, ops, ae), \ | |
15806 | xCM_ (m1, mi, m2, op, nops, ops, ae), \ | |
15807 | xCM_ (m1, pl, m2, op, nops, ops, ae), \ | |
15808 | xCM_ (m1, vs, m2, op, nops, ops, ae), \ | |
15809 | xCM_ (m1, vc, m2, op, nops, ops, ae), \ | |
15810 | xCM_ (m1, hi, m2, op, nops, ops, ae), \ | |
15811 | xCM_ (m1, ls, m2, op, nops, ops, ae), \ | |
15812 | xCM_ (m1, ge, m2, op, nops, ops, ae), \ | |
15813 | xCM_ (m1, lt, m2, op, nops, ops, ae), \ | |
15814 | xCM_ (m1, gt, m2, op, nops, ops, ae), \ | |
15815 | xCM_ (m1, le, m2, op, nops, ops, ae), \ | |
15816 | xCM_ (m1, al, m2, op, nops, ops, ae) | |
6a86118a NC |
15817 | |
15818 | #define UE(mnem, op, nops, ops, ae) \ | |
15819 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
15820 | ||
15821 | #define UF(mnem, op, nops, ops, ae) \ | |
15822 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
15823 | ||
5287ad62 JB |
15824 | /* Neon data-processing. ARM versions are unconditional with cond=0xf. |
15825 | The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we | |
15826 | use the same encoding function for each. */ | |
15827 | #define NUF(mnem, op, nops, ops, enc) \ | |
15828 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ | |
15829 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } | |
15830 | ||
15831 | /* Neon data processing, version which indirects through neon_enc_tab for | |
15832 | the various overloaded versions of opcodes. */ | |
15833 | #define nUF(mnem, op, nops, ops, enc) \ | |
15834 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \ | |
15835 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } | |
15836 | ||
15837 | /* Neon insn with conditional suffix for the ARM version, non-overloaded | |
15838 | version. */ | |
037e8744 JB |
15839 | #define NCE_tag(mnem, op, nops, ops, enc, tag) \ |
15840 | { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ | |
5287ad62 JB |
15841 | THUMB_VARIANT, do_##enc, do_##enc } |
15842 | ||
037e8744 | 15843 | #define NCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 15844 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
15845 | |
15846 | #define NCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 15847 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 15848 | |
5287ad62 | 15849 | /* Neon insn with conditional suffix for the ARM version, overloaded types. */ |
037e8744 JB |
15850 | #define nCE_tag(mnem, op, nops, ops, enc, tag) \ |
15851 | { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \ | |
5287ad62 JB |
15852 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
15853 | ||
037e8744 | 15854 | #define nCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 15855 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
15856 | |
15857 | #define nCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 15858 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 15859 | |
c19d1205 ZW |
15860 | #define do_0 0 |
15861 | ||
15862 | /* Thumb-only, unconditional. */ | |
e07e6e58 | 15863 | #define UT(mnem, op, nops, ops, te) TUE (mnem, 0, op, nops, ops, 0, te) |
c19d1205 | 15864 | |
c19d1205 | 15865 | static const struct asm_opcode insns[] = |
bfae80f2 | 15866 | { |
e74cfd16 PB |
15867 | #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ |
15868 | #define THUMB_VARIANT &arm_ext_v4t | |
c19d1205 ZW |
15869 | tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c), |
15870 | tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
15871 | tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
15872 | tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
15873 | tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
15874 | tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
4962c51a MS |
15875 | tCE(add, 0800000, add, 3, (RR, oRR, SHG), arit, t_add_sub), |
15876 | tC3(adds, 0900000, adds, 3, (RR, oRR, SHG), arit, t_add_sub), | |
c19d1205 ZW |
15877 | tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c), |
15878 | tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
15879 | tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
15880 | tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
15881 | tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
15882 | tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
15883 | tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3), | |
15884 | tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3), | |
15885 | ||
15886 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
15887 | for setting PSR flag bits. They are obsolete in V6 and do not | |
15888 | have Thumb equivalents. */ | |
15889 | tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), | |
088fa78e | 15890 | tC3w(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), |
e3cb604e | 15891 | CL(tstp, 110f000, 2, (RR, SH), cmp), |
c19d1205 | 15892 | tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), |
088fa78e | 15893 | tC3w(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), |
e3cb604e | 15894 | CL(cmpp, 150f000, 2, (RR, SH), cmp), |
c19d1205 | 15895 | tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), |
088fa78e | 15896 | tC3w(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), |
e3cb604e | 15897 | CL(cmnp, 170f000, 2, (RR, SH), cmp), |
c19d1205 ZW |
15898 | |
15899 | tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp), | |
15900 | tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp), | |
15901 | tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst), | |
15902 | tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst), | |
15903 | ||
4962c51a MS |
15904 | tCE(ldr, 4100000, ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), |
15905 | tC3(ldrb, 4500000, ldrb, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
15906 | tCE(str, 4000000, str, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
15907 | tC3(strb, 4400000, strb, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
c19d1205 | 15908 | |
f5208ef2 | 15909 | tCE(stm, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
c19d1205 ZW |
15910 | tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
15911 | tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
f5208ef2 | 15912 | tCE(ldm, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
c19d1205 ZW |
15913 | tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
15914 | tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
15915 | ||
15916 | TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi), | |
c16d2bf0 | 15917 | TCE(svc, f000000, df00, 1, (EXPi), swi, t_swi), |
0110f2b8 | 15918 | tCE(b, a000000, b, 1, (EXPr), branch, t_branch), |
39b41c9c | 15919 | TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23), |
bfae80f2 | 15920 | |
c19d1205 | 15921 | /* Pseudo ops. */ |
e9f89963 | 15922 | tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac ZW |
15923 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
15924 | tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop), | |
c19d1205 ZW |
15925 | |
15926 | /* Thumb-compatibility pseudo ops. */ | |
15927 | tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift), | |
15928 | tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift), | |
15929 | tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift), | |
15930 | tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
15931 | tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift), | |
2fc8bdac | 15932 | tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift), |
c19d1205 ZW |
15933 | tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift), |
15934 | tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift), | |
15935 | tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg), | |
15936 | tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg), | |
15937 | tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop), | |
15938 | tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop), | |
15939 | ||
16a4cf17 PB |
15940 | /* These may simplify to neg. */ |
15941 | TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), | |
15942 | TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
15943 | ||
c19d1205 | 15944 | #undef THUMB_VARIANT |
e74cfd16 | 15945 | #define THUMB_VARIANT &arm_ext_v6 |
2fc8bdac | 15946 | TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
15947 | |
15948 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
15949 | #undef THUMB_VARIANT | |
e74cfd16 | 15950 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 | 15951 | TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
088fa78e | 15952 | TC3w(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
e3cb604e | 15953 | CL(teqp, 130f000, 2, (RR, SH), cmp), |
c19d1205 ZW |
15954 | |
15955 | TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt), | |
3e94bf1a | 15956 | TC3(ldrbt, 4700000, f8100e00, 2, (RR, ADDR), ldstt, t_ldstt), |
c19d1205 | 15957 | TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt), |
3e94bf1a | 15958 | TC3(strbt, 4600000, f8000e00, 2, (RR, ADDR), ldstt, t_ldstt), |
c19d1205 | 15959 | |
9c3c69f2 PB |
15960 | TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
15961 | TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 15962 | |
9c3c69f2 PB |
15963 | TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
15964 | TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
15965 | |
15966 | /* V1 instructions with no Thumb analogue at all. */ | |
15967 | CE(rsc, 0e00000, 3, (RR, oRR, SH), arit), | |
15968 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), | |
15969 | ||
15970 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
15971 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
15972 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
15973 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
15974 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
15975 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
15976 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
15977 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
15978 | ||
15979 | #undef ARM_VARIANT | |
e74cfd16 | 15980 | #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */ |
c19d1205 | 15981 | #undef THUMB_VARIANT |
e74cfd16 | 15982 | #define THUMB_VARIANT &arm_ext_v4t |
c19d1205 ZW |
15983 | tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
15984 | tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
15985 | ||
15986 | #undef THUMB_VARIANT | |
e74cfd16 | 15987 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
15988 | TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
15989 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), | |
15990 | ||
15991 | /* Generic coprocessor instructions. */ | |
15992 | TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
4962c51a MS |
15993 | TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), |
15994 | TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
15995 | TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
15996 | TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
c19d1205 ZW |
15997 | TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), |
15998 | TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
15999 | ||
16000 | #undef ARM_VARIANT | |
e74cfd16 | 16001 | #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */ |
c19d1205 ZW |
16002 | CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
16003 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), | |
16004 | ||
16005 | #undef ARM_VARIANT | |
e74cfd16 | 16006 | #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */ |
7e806470 PB |
16007 | #undef THUMB_VARIANT |
16008 | #define THUMB_VARIANT &arm_ext_msr | |
037e8744 JB |
16009 | TCE(mrs, 10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs), |
16010 | TCE(msr, 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr), | |
c19d1205 ZW |
16011 | |
16012 | #undef ARM_VARIANT | |
e74cfd16 | 16013 | #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */ |
7e806470 PB |
16014 | #undef THUMB_VARIANT |
16015 | #define THUMB_VARIANT &arm_ext_v6t2 | |
c19d1205 ZW |
16016 | TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
16017 | CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
16018 | TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
16019 | CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
16020 | TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
16021 | CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
16022 | TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
16023 | CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
16024 | ||
16025 | #undef ARM_VARIANT | |
e74cfd16 | 16026 | #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */ |
c19d1205 | 16027 | #undef THUMB_VARIANT |
e74cfd16 | 16028 | #define THUMB_VARIANT &arm_ext_v4t |
4962c51a MS |
16029 | tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), |
16030 | tC3(strh, 00000b0, strh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), | |
16031 | tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), | |
16032 | tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), | |
16033 | tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), | |
16034 | tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), | |
c19d1205 ZW |
16035 | |
16036 | #undef ARM_VARIANT | |
e74cfd16 | 16037 | #define ARM_VARIANT &arm_ext_v4t_5 |
c19d1205 ZW |
16038 | /* ARM Architecture 4T. */ |
16039 | /* Note: bx (and blx) are required on V5, even if the processor does | |
16040 | not support Thumb. */ | |
16041 | TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx), | |
16042 | ||
16043 | #undef ARM_VARIANT | |
e74cfd16 | 16044 | #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */ |
c19d1205 | 16045 | #undef THUMB_VARIANT |
e74cfd16 | 16046 | #define THUMB_VARIANT &arm_ext_v5t |
c19d1205 ZW |
16047 | /* Note: blx has 2 variants; the .value coded here is for |
16048 | BLX(2). Only this variant has conditional execution. */ | |
16049 | TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx), | |
16050 | TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
16051 | ||
16052 | #undef THUMB_VARIANT | |
e74cfd16 | 16053 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 | 16054 | TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
4962c51a MS |
16055 | TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), |
16056 | TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16057 | TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16058 | TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
c19d1205 ZW |
16059 | TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), |
16060 | TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
16061 | TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
16062 | ||
16063 | #undef ARM_VARIANT | |
e74cfd16 | 16064 | #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */ |
c19d1205 ZW |
16065 | TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
16066 | TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
16067 | TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
16068 | TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
16069 | ||
16070 | TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
16071 | TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
16072 | ||
16073 | TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
16074 | TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
16075 | TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
16076 | TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
16077 | ||
16078 | TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16079 | TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16080 | TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16081 | TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16082 | ||
16083 | TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16084 | TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16085 | ||
087b80de JM |
16086 | TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd), |
16087 | TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd), | |
16088 | TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd), | |
16089 | TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd), | |
c19d1205 ZW |
16090 | |
16091 | #undef ARM_VARIANT | |
e74cfd16 | 16092 | #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */ |
c19d1205 | 16093 | TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld), |
79d49516 PB |
16094 | TC3(ldrd, 00000d0, e8500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), |
16095 | TC3(strd, 00000f0, e8400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), | |
c19d1205 ZW |
16096 | |
16097 | TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
16098 | TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
16099 | ||
16100 | #undef ARM_VARIANT | |
e74cfd16 | 16101 | #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */ |
c19d1205 ZW |
16102 | TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
16103 | ||
16104 | #undef ARM_VARIANT | |
e74cfd16 | 16105 | #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */ |
c19d1205 | 16106 | #undef THUMB_VARIANT |
e74cfd16 | 16107 | #define THUMB_VARIANT &arm_ext_v6 |
c19d1205 ZW |
16108 | TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
16109 | TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
16110 | tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
16111 | tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
16112 | tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
16113 | tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16114 | tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16115 | tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16116 | tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16117 | TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend), | |
16118 | ||
16119 | #undef THUMB_VARIANT | |
e74cfd16 | 16120 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 | 16121 | TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex), |
91568d08 | 16122 | TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex), |
c19d1205 ZW |
16123 | TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
16124 | TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
62b3e311 PB |
16125 | |
16126 | TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), | |
16127 | TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
16128 | ||
16129 | /* ARM V6 not included in V7M (eg. integer SIMD). */ | |
16130 | #undef THUMB_VARIANT | |
16131 | #define THUMB_VARIANT &arm_ext_v6_notm | |
dfa9f0d5 | 16132 | TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, t_cps), |
c19d1205 ZW |
16133 | TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), |
16134 | TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
16135 | TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16136 | TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e JM |
16137 | TCE(qasx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16138 | /* Old name for QASX. */ | |
c19d1205 | 16139 | TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e JM |
16140 | TCE(qsax, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16141 | /* Old name for QSAX. */ | |
16142 | TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
c19d1205 ZW |
16143 | TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16144 | TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
c19d1205 ZW |
16145 | TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16146 | TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e JM |
16147 | TCE(sasx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16148 | /* Old name for SASX. */ | |
c19d1205 ZW |
16149 | TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16150 | TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16151 | TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e JM |
16152 | TCE(shasx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16153 | /* Old name for SHASX. */ | |
c19d1205 | 16154 | TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e JM |
16155 | TCE(shsax, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16156 | /* Old name for SHSAX. */ | |
16157 | TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
c19d1205 ZW |
16158 | TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16159 | TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e JM |
16160 | TCE(ssax, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16161 | /* Old name for SSAX. */ | |
16162 | TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
c19d1205 ZW |
16163 | TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16164 | TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
c19d1205 ZW |
16165 | TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16166 | TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e JM |
16167 | TCE(uasx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16168 | /* Old name for UASX. */ | |
c19d1205 ZW |
16169 | TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16170 | TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16171 | TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e JM |
16172 | TCE(uhasx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16173 | /* Old name for UHASX. */ | |
c19d1205 | 16174 | TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e JM |
16175 | TCE(uhsax, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16176 | /* Old name for UHSAX. */ | |
16177 | TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
c19d1205 ZW |
16178 | TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16179 | TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
c19d1205 ZW |
16180 | TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16181 | TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e JM |
16182 | TCE(uqasx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16183 | /* Old name for UQASX. */ | |
c19d1205 | 16184 | TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e JM |
16185 | TCE(uqsax, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16186 | /* Old name for UQSAX. */ | |
16187 | TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
c19d1205 ZW |
16188 | TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16189 | TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
c19d1205 | 16190 | TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e JM |
16191 | TCE(usax, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16192 | /* Old name for USAX. */ | |
c19d1205 | 16193 | TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 16194 | TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
c19d1205 ZW |
16195 | TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe), |
16196 | UF(rfeib, 9900a00, 1, (RRw), rfe), | |
16197 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
16198 | TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
16199 | TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
16200 | UF(rfefa, 9900a00, 1, (RRw), rfe), | |
16201 | UF(rfeea, 8100a00, 1, (RRw), rfe), | |
16202 | TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
16203 | TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16204 | TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16205 | TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16206 | TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16207 | TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16208 | TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16209 | TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16210 | TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
f1022c90 | 16211 | TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
c19d1205 ZW |
16212 | TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), |
16213 | TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16214 | TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
16215 | TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
16216 | TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16217 | TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16218 | TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
16219 | TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
16220 | TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16221 | TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16222 | TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16223 | TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16224 | TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16225 | TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16226 | TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16227 | TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16228 | TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16229 | TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
b6702015 PB |
16230 | TUF(srsia, 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), |
16231 | UF(srsib, 9c00500, 2, (oRRw, I31w), srs), | |
16232 | UF(srsda, 8400500, 2, (oRRw, I31w), srs), | |
16233 | TUF(srsdb, 9400500, e800c000, 2, (oRRw, I31w), srs, srs), | |
c19d1205 | 16234 | TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), |
c19d1205 ZW |
16235 | TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), |
16236 | TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16237 | TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
c19d1205 ZW |
16238 | TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), |
16239 | ||
16240 | #undef ARM_VARIANT | |
e74cfd16 | 16241 | #define ARM_VARIANT &arm_ext_v6k |
c19d1205 | 16242 | #undef THUMB_VARIANT |
e74cfd16 | 16243 | #define THUMB_VARIANT &arm_ext_v6k |
c19d1205 ZW |
16244 | tCE(yield, 320f001, yield, 0, (), noargs, t_hint), |
16245 | tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint), | |
16246 | tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint), | |
16247 | tCE(sev, 320f004, sev, 0, (), noargs, t_hint), | |
16248 | ||
ebdca51a PB |
16249 | #undef THUMB_VARIANT |
16250 | #define THUMB_VARIANT &arm_ext_v6_notm | |
16251 | TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd), | |
16252 | TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd), | |
16253 | ||
c19d1205 | 16254 | #undef THUMB_VARIANT |
e74cfd16 | 16255 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
16256 | TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), |
16257 | TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
c19d1205 ZW |
16258 | TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), |
16259 | TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), | |
c19d1205 ZW |
16260 | TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs), |
16261 | ||
16262 | #undef ARM_VARIANT | |
e74cfd16 | 16263 | #define ARM_VARIANT &arm_ext_v6z |
3eb17e6b | 16264 | TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 ZW |
16265 | |
16266 | #undef ARM_VARIANT | |
e74cfd16 | 16267 | #define ARM_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
16268 | TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
16269 | TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
16270 | TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
16271 | TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
16272 | ||
16273 | TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), | |
b6895b4f PB |
16274 | TCE(movw, 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), |
16275 | TCE(movt, 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), | |
401a54cf | 16276 | TCE(rbit, 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), |
c19d1205 ZW |
16277 | |
16278 | TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
16279 | TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
16280 | TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
16281 | TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
16282 | ||
25fe350b MS |
16283 | UT(cbnz, b900, 2, (RR, EXP), t_cbz), |
16284 | UT(cbz, b100, 2, (RR, EXP), t_cbz), | |
e07e6e58 NC |
16285 | /* ARM does not really have an IT instruction, so always allow it. The opcode |
16286 | is copied from Thumb in order to allow warnings | |
16287 | in -mimplicit-it=[never | arm] modes. */ | |
f91e006c PB |
16288 | #undef ARM_VARIANT |
16289 | #define ARM_VARIANT &arm_ext_v1 | |
e07e6e58 NC |
16290 | TUE(it, bf08, bf08, 1, (COND), it, t_it), |
16291 | TUE(itt, bf0c, bf0c, 1, (COND), it, t_it), | |
16292 | TUE(ite, bf04, bf04, 1, (COND), it, t_it), | |
16293 | TUE(ittt, bf0e, bf0e, 1, (COND), it, t_it), | |
16294 | TUE(itet, bf06, bf06, 1, (COND), it, t_it), | |
16295 | TUE(itte, bf0a, bf0a, 1, (COND), it, t_it), | |
16296 | TUE(itee, bf02, bf02, 1, (COND), it, t_it), | |
16297 | TUE(itttt, bf0f, bf0f, 1, (COND), it, t_it), | |
16298 | TUE(itett, bf07, bf07, 1, (COND), it, t_it), | |
16299 | TUE(ittet, bf0b, bf0b, 1, (COND), it, t_it), | |
16300 | TUE(iteet, bf03, bf03, 1, (COND), it, t_it), | |
16301 | TUE(ittte, bf0d, bf0d, 1, (COND), it, t_it), | |
16302 | TUE(itete, bf05, bf05, 1, (COND), it, t_it), | |
16303 | TUE(ittee, bf09, bf09, 1, (COND), it, t_it), | |
16304 | TUE(iteee, bf01, bf01, 1, (COND), it, t_it), | |
1c444d06 JM |
16305 | /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */ |
16306 | TC3(rrx, 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx), | |
16307 | TC3(rrxs, 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx), | |
c19d1205 | 16308 | |
92e90b6e PB |
16309 | /* Thumb2 only instructions. */ |
16310 | #undef ARM_VARIANT | |
e74cfd16 | 16311 | #define ARM_VARIANT NULL |
92e90b6e PB |
16312 | |
16313 | TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
16314 | TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
1c444d06 JM |
16315 | TCE(orn, 0, ea600000, 3, (RR, oRR, SH), 0, t_orn), |
16316 | TCE(orns, 0, ea700000, 3, (RR, oRR, SH), 0, t_orn), | |
92e90b6e PB |
16317 | TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb), |
16318 | TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb), | |
16319 | ||
62b3e311 PB |
16320 | /* Thumb-2 hardware division instructions (R and M profiles only). */ |
16321 | #undef THUMB_VARIANT | |
16322 | #define THUMB_VARIANT &arm_ext_div | |
16323 | TCE(sdiv, 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div), | |
16324 | TCE(udiv, 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div), | |
16325 | ||
7e806470 PB |
16326 | /* ARM V6M/V7 instructions. */ |
16327 | #undef ARM_VARIANT | |
16328 | #define ARM_VARIANT &arm_ext_barrier | |
16329 | #undef THUMB_VARIANT | |
16330 | #define THUMB_VARIANT &arm_ext_barrier | |
16331 | TUF(dmb, 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier), | |
16332 | TUF(dsb, 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier), | |
16333 | TUF(isb, 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier), | |
16334 | ||
62b3e311 PB |
16335 | /* ARM V7 instructions. */ |
16336 | #undef ARM_VARIANT | |
16337 | #define ARM_VARIANT &arm_ext_v7 | |
16338 | #undef THUMB_VARIANT | |
16339 | #define THUMB_VARIANT &arm_ext_v7 | |
16340 | TUF(pli, 450f000, f910f000, 1, (ADDR), pli, t_pld), | |
16341 | TCE(dbg, 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), | |
62b3e311 | 16342 | |
c19d1205 | 16343 | #undef ARM_VARIANT |
e74cfd16 | 16344 | #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ |
8f06b2d8 PB |
16345 | cCE(wfs, e200110, 1, (RR), rd), |
16346 | cCE(rfs, e300110, 1, (RR), rd), | |
16347 | cCE(wfc, e400110, 1, (RR), rd), | |
16348 | cCE(rfc, e500110, 1, (RR), rd), | |
16349 | ||
4962c51a MS |
16350 | cCL(ldfs, c100100, 2, (RF, ADDRGLDC), rd_cpaddr), |
16351 | cCL(ldfd, c108100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
16352 | cCL(ldfe, c500100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
16353 | cCL(ldfp, c508100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
e3cb604e | 16354 | |
4962c51a MS |
16355 | cCL(stfs, c000100, 2, (RF, ADDRGLDC), rd_cpaddr), |
16356 | cCL(stfd, c008100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
16357 | cCL(stfe, c400100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
16358 | cCL(stfp, c408100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
e3cb604e PB |
16359 | |
16360 | cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm), | |
16361 | cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm), | |
16362 | cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm), | |
16363 | cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm), | |
16364 | cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm), | |
16365 | cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm), | |
16366 | cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm), | |
16367 | cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm), | |
16368 | cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm), | |
16369 | cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm), | |
16370 | cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm), | |
16371 | cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm), | |
16372 | ||
16373 | cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm), | |
16374 | cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm), | |
16375 | cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm), | |
16376 | cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm), | |
16377 | cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm), | |
16378 | cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm), | |
16379 | cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm), | |
16380 | cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm), | |
16381 | cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm), | |
16382 | cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm), | |
16383 | cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm), | |
16384 | cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm), | |
16385 | ||
16386 | cCL(abss, e208100, 2, (RF, RF_IF), rd_rm), | |
16387 | cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm), | |
16388 | cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm), | |
16389 | cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm), | |
16390 | cCL(absd, e208180, 2, (RF, RF_IF), rd_rm), | |
16391 | cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm), | |
16392 | cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm), | |
16393 | cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm), | |
16394 | cCL(abse, e288100, 2, (RF, RF_IF), rd_rm), | |
16395 | cCL(absep, e288120, 2, (RF, RF_IF), rd_rm), | |
16396 | cCL(absem, e288140, 2, (RF, RF_IF), rd_rm), | |
16397 | cCL(absez, e288160, 2, (RF, RF_IF), rd_rm), | |
16398 | ||
16399 | cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm), | |
16400 | cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm), | |
16401 | cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm), | |
16402 | cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm), | |
16403 | cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm), | |
16404 | cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm), | |
16405 | cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm), | |
16406 | cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm), | |
16407 | cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm), | |
16408 | cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm), | |
16409 | cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm), | |
16410 | cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm), | |
16411 | ||
16412 | cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm), | |
16413 | cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm), | |
16414 | cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm), | |
16415 | cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm), | |
16416 | cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm), | |
16417 | cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm), | |
16418 | cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm), | |
16419 | cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm), | |
16420 | cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm), | |
16421 | cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm), | |
16422 | cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm), | |
16423 | cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm), | |
16424 | ||
16425 | cCL(logs, e508100, 2, (RF, RF_IF), rd_rm), | |
16426 | cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm), | |
16427 | cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm), | |
16428 | cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm), | |
16429 | cCL(logd, e508180, 2, (RF, RF_IF), rd_rm), | |
16430 | cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm), | |
16431 | cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm), | |
16432 | cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm), | |
16433 | cCL(loge, e588100, 2, (RF, RF_IF), rd_rm), | |
16434 | cCL(logep, e588120, 2, (RF, RF_IF), rd_rm), | |
16435 | cCL(logem, e588140, 2, (RF, RF_IF), rd_rm), | |
16436 | cCL(logez, e588160, 2, (RF, RF_IF), rd_rm), | |
16437 | ||
16438 | cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm), | |
16439 | cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm), | |
16440 | cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm), | |
16441 | cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm), | |
16442 | cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm), | |
16443 | cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm), | |
16444 | cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm), | |
16445 | cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm), | |
16446 | cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm), | |
16447 | cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm), | |
16448 | cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm), | |
16449 | cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm), | |
16450 | ||
16451 | cCL(exps, e708100, 2, (RF, RF_IF), rd_rm), | |
16452 | cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm), | |
16453 | cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm), | |
16454 | cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm), | |
16455 | cCL(expd, e708180, 2, (RF, RF_IF), rd_rm), | |
16456 | cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm), | |
16457 | cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm), | |
16458 | cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm), | |
16459 | cCL(expe, e788100, 2, (RF, RF_IF), rd_rm), | |
16460 | cCL(expep, e788120, 2, (RF, RF_IF), rd_rm), | |
16461 | cCL(expem, e788140, 2, (RF, RF_IF), rd_rm), | |
16462 | cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm), | |
16463 | ||
16464 | cCL(sins, e808100, 2, (RF, RF_IF), rd_rm), | |
16465 | cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm), | |
16466 | cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm), | |
16467 | cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm), | |
16468 | cCL(sind, e808180, 2, (RF, RF_IF), rd_rm), | |
16469 | cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm), | |
16470 | cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm), | |
16471 | cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm), | |
16472 | cCL(sine, e888100, 2, (RF, RF_IF), rd_rm), | |
16473 | cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm), | |
16474 | cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm), | |
16475 | cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm), | |
16476 | ||
16477 | cCL(coss, e908100, 2, (RF, RF_IF), rd_rm), | |
16478 | cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm), | |
16479 | cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm), | |
16480 | cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm), | |
16481 | cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm), | |
16482 | cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm), | |
16483 | cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm), | |
16484 | cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm), | |
16485 | cCL(cose, e988100, 2, (RF, RF_IF), rd_rm), | |
16486 | cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm), | |
16487 | cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm), | |
16488 | cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm), | |
16489 | ||
16490 | cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm), | |
16491 | cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm), | |
16492 | cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm), | |
16493 | cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm), | |
16494 | cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm), | |
16495 | cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm), | |
16496 | cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm), | |
16497 | cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm), | |
16498 | cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm), | |
16499 | cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm), | |
16500 | cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm), | |
16501 | cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm), | |
16502 | ||
16503 | cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm), | |
16504 | cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm), | |
16505 | cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm), | |
16506 | cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm), | |
16507 | cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm), | |
16508 | cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm), | |
16509 | cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm), | |
16510 | cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm), | |
16511 | cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm), | |
16512 | cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm), | |
16513 | cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm), | |
16514 | cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm), | |
16515 | ||
16516 | cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm), | |
16517 | cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm), | |
16518 | cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm), | |
16519 | cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm), | |
16520 | cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm), | |
16521 | cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm), | |
16522 | cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm), | |
16523 | cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm), | |
16524 | cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm), | |
16525 | cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm), | |
16526 | cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm), | |
16527 | cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm), | |
16528 | ||
16529 | cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm), | |
16530 | cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm), | |
16531 | cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm), | |
16532 | cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm), | |
16533 | cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm), | |
16534 | cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm), | |
16535 | cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm), | |
16536 | cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm), | |
16537 | cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm), | |
16538 | cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm), | |
16539 | cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm), | |
16540 | cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm), | |
16541 | ||
16542 | cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm), | |
16543 | cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm), | |
16544 | cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm), | |
16545 | cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm), | |
16546 | cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm), | |
16547 | cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm), | |
16548 | cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm), | |
16549 | cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm), | |
16550 | cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm), | |
16551 | cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm), | |
16552 | cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm), | |
16553 | cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm), | |
16554 | ||
16555 | cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm), | |
16556 | cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm), | |
16557 | cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm), | |
16558 | cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm), | |
16559 | cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm), | |
16560 | cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm), | |
16561 | cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm), | |
16562 | cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm), | |
16563 | cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm), | |
16564 | cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm), | |
16565 | cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm), | |
16566 | cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm), | |
16567 | ||
16568 | cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16569 | cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16570 | cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16571 | cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16572 | cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16573 | cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16574 | cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16575 | cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16576 | cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16577 | cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16578 | cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16579 | cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16580 | ||
16581 | cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16582 | cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16583 | cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16584 | cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16585 | cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16586 | cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16587 | cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16588 | cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16589 | cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16590 | cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16591 | cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16592 | cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16593 | ||
16594 | cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16595 | cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16596 | cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16597 | cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16598 | cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16599 | cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16600 | cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16601 | cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16602 | cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16603 | cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16604 | cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16605 | cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16606 | ||
16607 | cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16608 | cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16609 | cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16610 | cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16611 | cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16612 | cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16613 | cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16614 | cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16615 | cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16616 | cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16617 | cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16618 | cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16619 | ||
16620 | cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16621 | cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16622 | cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16623 | cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16624 | cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16625 | cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16626 | cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16627 | cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16628 | cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16629 | cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16630 | cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16631 | cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16632 | ||
16633 | cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16634 | cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16635 | cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16636 | cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16637 | cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16638 | cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16639 | cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16640 | cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16641 | cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16642 | cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16643 | cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16644 | cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16645 | ||
16646 | cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16647 | cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16648 | cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16649 | cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16650 | cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16651 | cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16652 | cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16653 | cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16654 | cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16655 | cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16656 | cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16657 | cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16658 | ||
16659 | cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16660 | cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16661 | cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16662 | cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16663 | cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16664 | cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16665 | cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16666 | cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16667 | cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16668 | cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16669 | cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16670 | cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16671 | ||
16672 | cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16673 | cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16674 | cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16675 | cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16676 | cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16677 | cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16678 | cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16679 | cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16680 | cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16681 | cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16682 | cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16683 | cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16684 | ||
16685 | cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16686 | cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16687 | cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16688 | cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16689 | cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16690 | cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16691 | cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16692 | cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16693 | cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16694 | cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16695 | cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16696 | cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16697 | ||
16698 | cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16699 | cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16700 | cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16701 | cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16702 | cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16703 | cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16704 | cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16705 | cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16706 | cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16707 | cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16708 | cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16709 | cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16710 | ||
16711 | cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16712 | cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16713 | cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16714 | cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16715 | cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16716 | cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16717 | cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16718 | cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16719 | cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16720 | cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16721 | cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16722 | cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16723 | ||
16724 | cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16725 | cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16726 | cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16727 | cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16728 | cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16729 | cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16730 | cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16731 | cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16732 | cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16733 | cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16734 | cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
16735 | cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8f06b2d8 PB |
16736 | |
16737 | cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp), | |
c19d1205 | 16738 | C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp), |
8f06b2d8 | 16739 | cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp), |
c19d1205 ZW |
16740 | C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp), |
16741 | ||
e3cb604e PB |
16742 | cCL(flts, e000110, 2, (RF, RR), rn_rd), |
16743 | cCL(fltsp, e000130, 2, (RF, RR), rn_rd), | |
16744 | cCL(fltsm, e000150, 2, (RF, RR), rn_rd), | |
16745 | cCL(fltsz, e000170, 2, (RF, RR), rn_rd), | |
16746 | cCL(fltd, e000190, 2, (RF, RR), rn_rd), | |
16747 | cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd), | |
16748 | cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd), | |
16749 | cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd), | |
16750 | cCL(flte, e080110, 2, (RF, RR), rn_rd), | |
16751 | cCL(fltep, e080130, 2, (RF, RR), rn_rd), | |
16752 | cCL(fltem, e080150, 2, (RF, RR), rn_rd), | |
16753 | cCL(fltez, e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 16754 | |
c19d1205 ZW |
16755 | /* The implementation of the FIX instruction is broken on some |
16756 | assemblers, in that it accepts a precision specifier as well as a | |
16757 | rounding specifier, despite the fact that this is meaningless. | |
16758 | To be more compatible, we accept it as well, though of course it | |
16759 | does not set any bits. */ | |
8f06b2d8 | 16760 | cCE(fix, e100110, 2, (RR, RF), rd_rm), |
e3cb604e PB |
16761 | cCL(fixp, e100130, 2, (RR, RF), rd_rm), |
16762 | cCL(fixm, e100150, 2, (RR, RF), rd_rm), | |
16763 | cCL(fixz, e100170, 2, (RR, RF), rd_rm), | |
16764 | cCL(fixsp, e100130, 2, (RR, RF), rd_rm), | |
16765 | cCL(fixsm, e100150, 2, (RR, RF), rd_rm), | |
16766 | cCL(fixsz, e100170, 2, (RR, RF), rd_rm), | |
16767 | cCL(fixdp, e100130, 2, (RR, RF), rd_rm), | |
16768 | cCL(fixdm, e100150, 2, (RR, RF), rd_rm), | |
16769 | cCL(fixdz, e100170, 2, (RR, RF), rd_rm), | |
16770 | cCL(fixep, e100130, 2, (RR, RF), rd_rm), | |
16771 | cCL(fixem, e100150, 2, (RR, RF), rd_rm), | |
16772 | cCL(fixez, e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 16773 | |
c19d1205 ZW |
16774 | /* Instructions that were new with the real FPA, call them V2. */ |
16775 | #undef ARM_VARIANT | |
e74cfd16 | 16776 | #define ARM_VARIANT &fpu_fpa_ext_v2 |
8f06b2d8 | 16777 | cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
e3cb604e PB |
16778 | cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
16779 | cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
8f06b2d8 | 16780 | cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
e3cb604e PB |
16781 | cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
16782 | cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 ZW |
16783 | |
16784 | #undef ARM_VARIANT | |
e74cfd16 | 16785 | #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ |
c19d1205 | 16786 | /* Moves and type conversions. */ |
8f06b2d8 PB |
16787 | cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
16788 | cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
16789 | cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
16790 | cCE(fmstat, ef1fa10, 0, (), noargs), | |
16791 | cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
16792 | cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
16793 | cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
16794 | cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
16795 | cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
16796 | cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
16797 | cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn), | |
16798 | cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
16799 | |
16800 | /* Memory operations. */ | |
4962c51a MS |
16801 | cCE(flds, d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), |
16802 | cCE(fsts, d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), | |
8f06b2d8 PB |
16803 | cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), |
16804 | cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
16805 | cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
16806 | cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
16807 | cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
16808 | cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
16809 | cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
16810 | cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
16811 | cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
16812 | cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
16813 | cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
16814 | cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
16815 | cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
16816 | cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
16817 | cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
16818 | cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 16819 | |
c19d1205 | 16820 | /* Monadic operations. */ |
8f06b2d8 PB |
16821 | cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
16822 | cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
16823 | cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
16824 | |
16825 | /* Dyadic operations. */ | |
8f06b2d8 PB |
16826 | cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
16827 | cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
16828 | cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
16829 | cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
16830 | cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
16831 | cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
16832 | cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
16833 | cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
16834 | cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 16835 | |
c19d1205 | 16836 | /* Comparisons. */ |
8f06b2d8 PB |
16837 | cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
16838 | cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z), | |
16839 | cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
16840 | cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 16841 | |
c19d1205 | 16842 | #undef ARM_VARIANT |
e74cfd16 | 16843 | #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ |
c19d1205 | 16844 | /* Moves and type conversions. */ |
5287ad62 | 16845 | cCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
8f06b2d8 PB |
16846 | cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), |
16847 | cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
5287ad62 JB |
16848 | cCE(fmdhr, e200b10, 2, (RVD, RR), vfp_dp_rn_rd), |
16849 | cCE(fmdlr, e000b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
16850 | cCE(fmrdh, e300b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
16851 | cCE(fmrdl, e100b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
8f06b2d8 PB |
16852 | cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), |
16853 | cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
16854 | cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
16855 | cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
16856 | cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
16857 | cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 ZW |
16858 | |
16859 | /* Memory operations. */ | |
4962c51a MS |
16860 | cCE(fldd, d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), |
16861 | cCE(fstd, d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
8f06b2d8 PB |
16862 | cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), |
16863 | cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
16864 | cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
16865 | cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
16866 | cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
16867 | cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
16868 | cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
16869 | cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
b99bd4ef | 16870 | |
c19d1205 | 16871 | /* Monadic operations. */ |
5287ad62 JB |
16872 | cCE(fabsd, eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
16873 | cCE(fnegd, eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), | |
16874 | cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
c19d1205 ZW |
16875 | |
16876 | /* Dyadic operations. */ | |
5287ad62 JB |
16877 | cCE(faddd, e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
16878 | cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
16879 | cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
16880 | cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
16881 | cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
16882 | cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
16883 | cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
16884 | cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
16885 | cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
b99bd4ef | 16886 | |
c19d1205 | 16887 | /* Comparisons. */ |
5287ad62 JB |
16888 | cCE(fcmpd, eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
16889 | cCE(fcmpzd, eb50b40, 1, (RVD), vfp_dp_rd), | |
16890 | cCE(fcmped, eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
16891 | cCE(fcmpezd, eb50bc0, 1, (RVD), vfp_dp_rd), | |
c19d1205 ZW |
16892 | |
16893 | #undef ARM_VARIANT | |
e74cfd16 | 16894 | #define ARM_VARIANT &fpu_vfp_ext_v2 |
8f06b2d8 PB |
16895 | cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
16896 | cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
5287ad62 JB |
16897 | cCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), |
16898 | cCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), | |
16899 | ||
037e8744 JB |
16900 | /* Instructions which may belong to either the Neon or VFP instruction sets. |
16901 | Individual encoder functions perform additional architecture checks. */ | |
16902 | #undef ARM_VARIANT | |
16903 | #define ARM_VARIANT &fpu_vfp_ext_v1xd | |
16904 | #undef THUMB_VARIANT | |
16905 | #define THUMB_VARIANT &fpu_vfp_ext_v1xd | |
16906 | /* These mnemonics are unique to VFP. */ | |
16907 | NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), | |
16908 | NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), | |
16909 | nCE(vnmul, vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
16910 | nCE(vnmla, vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
16911 | nCE(vnmls, vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
16912 | nCE(vcmp, vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
16913 | nCE(vcmpe, vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
16914 | NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), | |
16915 | NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), | |
16916 | NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), | |
16917 | ||
16918 | /* Mnemonics shared by Neon and VFP. */ | |
16919 | nCEF(vmul, vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), | |
16920 | nCEF(vmla, vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
16921 | nCEF(vmls, vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
16922 | ||
16923 | nCEF(vadd, vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), | |
16924 | nCEF(vsub, vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), | |
16925 | ||
16926 | NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
16927 | NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
16928 | ||
16929 | NCE(vldm, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), | |
16930 | NCE(vldmia, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), | |
16931 | NCE(vldmdb, d100b00, 2, (RRw, VRSDLST), neon_ldm_stm), | |
16932 | NCE(vstm, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), | |
16933 | NCE(vstmia, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), | |
16934 | NCE(vstmdb, d000b00, 2, (RRw, VRSDLST), neon_ldm_stm), | |
4962c51a MS |
16935 | NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), |
16936 | NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), | |
037e8744 JB |
16937 | |
16938 | nCEF(vcvt, vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt), | |
8e79c3df CM |
16939 | nCEF(vcvtb, vcvt, 2, (RVS, RVS), neon_cvtb), |
16940 | nCEF(vcvtt, vcvt, 2, (RVS, RVS), neon_cvtt), | |
f31fef98 | 16941 | |
037e8744 JB |
16942 | |
16943 | /* NOTE: All VMOV encoding is special-cased! */ | |
16944 | NCE(vmov, 0, 1, (VMOV), neon_mov), | |
16945 | NCE(vmovq, 0, 1, (VMOV), neon_mov), | |
16946 | ||
5287ad62 JB |
16947 | #undef THUMB_VARIANT |
16948 | #define THUMB_VARIANT &fpu_neon_ext_v1 | |
16949 | #undef ARM_VARIANT | |
16950 | #define ARM_VARIANT &fpu_neon_ext_v1 | |
16951 | /* Data processing with three registers of the same length. */ | |
16952 | /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ | |
16953 | NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), | |
16954 | NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), | |
16955 | NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
16956 | NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
16957 | NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
16958 | NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
16959 | NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
16960 | NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
16961 | /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ | |
16962 | NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
16963 | NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
16964 | NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
16965 | NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
627907b7 JB |
16966 | NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), |
16967 | NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
16968 | NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), | |
16969 | NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
5287ad62 JB |
16970 | /* If not immediate, fall back to neon_dyadic_i64_su. |
16971 | shl_imm should accept I8 I16 I32 I64, | |
16972 | qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ | |
16973 | nUF(vshl, vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), | |
16974 | nUF(vshlq, vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), | |
16975 | nUF(vqshl, vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), | |
16976 | nUF(vqshlq, vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), | |
16977 | /* Logic ops, types optional & ignored. */ | |
16978 | nUF(vand, vand, 2, (RNDQ, NILO), neon_logic), | |
16979 | nUF(vandq, vand, 2, (RNQ, NILO), neon_logic), | |
16980 | nUF(vbic, vbic, 2, (RNDQ, NILO), neon_logic), | |
16981 | nUF(vbicq, vbic, 2, (RNQ, NILO), neon_logic), | |
16982 | nUF(vorr, vorr, 2, (RNDQ, NILO), neon_logic), | |
16983 | nUF(vorrq, vorr, 2, (RNQ, NILO), neon_logic), | |
16984 | nUF(vorn, vorn, 2, (RNDQ, NILO), neon_logic), | |
16985 | nUF(vornq, vorn, 2, (RNQ, NILO), neon_logic), | |
16986 | nUF(veor, veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), | |
16987 | nUF(veorq, veor, 3, (RNQ, oRNQ, RNQ), neon_logic), | |
16988 | /* Bitfield ops, untyped. */ | |
16989 | NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
16990 | NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
16991 | NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
16992 | NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
16993 | NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
16994 | NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
16995 | /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ | |
16996 | nUF(vabd, vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
16997 | nUF(vabdq, vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
16998 | nUF(vmax, vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
16999 | nUF(vmaxq, vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
17000 | nUF(vmin, vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
17001 | nUF(vminq, vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
17002 | /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall | |
17003 | back to neon_dyadic_if_su. */ | |
17004 | nUF(vcge, vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), | |
17005 | nUF(vcgeq, vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
17006 | nUF(vcgt, vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), | |
17007 | nUF(vcgtq, vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
17008 | nUF(vclt, vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
17009 | nUF(vcltq, vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
17010 | nUF(vcle, vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
17011 | nUF(vcleq, vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
428e3f1f | 17012 | /* Comparison. Type I8 I16 I32 F32. */ |
5287ad62 JB |
17013 | nUF(vceq, vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), |
17014 | nUF(vceqq, vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), | |
17015 | /* As above, D registers only. */ | |
17016 | nUF(vpmax, vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), | |
17017 | nUF(vpmin, vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), | |
17018 | /* Int and float variants, signedness unimportant. */ | |
5287ad62 | 17019 | nUF(vmlaq, vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
5287ad62 JB |
17020 | nUF(vmlsq, vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
17021 | nUF(vpadd, vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), | |
17022 | /* Add/sub take types I8 I16 I32 I64 F32. */ | |
5287ad62 | 17023 | nUF(vaddq, vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
5287ad62 JB |
17024 | nUF(vsubq, vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
17025 | /* vtst takes sizes 8, 16, 32. */ | |
17026 | NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), | |
17027 | NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), | |
17028 | /* VMUL takes I8 I16 I32 F32 P8. */ | |
037e8744 | 17029 | nUF(vmulq, vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), |
5287ad62 JB |
17030 | /* VQD{R}MULH takes S16 S32. */ |
17031 | nUF(vqdmulh, vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
17032 | nUF(vqdmulhq, vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
17033 | nUF(vqrdmulh, vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
17034 | nUF(vqrdmulhq, vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
17035 | NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), | |
17036 | NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
17037 | NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), | |
17038 | NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
92559b5b PB |
17039 | NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), |
17040 | NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
17041 | NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), | |
17042 | NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
5287ad62 JB |
17043 | NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), |
17044 | NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
17045 | NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), | |
17046 | NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
17047 | ||
17048 | /* Two address, int/float. Types S8 S16 S32 F32. */ | |
5287ad62 | 17049 | NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), |
5287ad62 JB |
17050 | NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), |
17051 | ||
17052 | /* Data processing with two registers and a shift amount. */ | |
17053 | /* Right shifts, and variants with rounding. | |
17054 | Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ | |
17055 | NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
17056 | NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
17057 | NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
17058 | NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
17059 | NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
17060 | NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
17061 | NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
17062 | NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
17063 | /* Shift and insert. Sizes accepted 8 16 32 64. */ | |
17064 | NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), | |
17065 | NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), | |
17066 | NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), | |
17067 | NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), | |
17068 | /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ | |
17069 | NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), | |
17070 | NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), | |
17071 | /* Right shift immediate, saturating & narrowing, with rounding variants. | |
17072 | Types accepted S16 S32 S64 U16 U32 U64. */ | |
17073 | NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
17074 | NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
17075 | /* As above, unsigned. Types accepted S16 S32 S64. */ | |
17076 | NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
17077 | NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
17078 | /* Right shift narrowing. Types accepted I16 I32 I64. */ | |
17079 | NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
17080 | NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
17081 | /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ | |
17082 | nUF(vshll, vshll, 3, (RNQ, RND, I32), neon_shll), | |
17083 | /* CVT with optional immediate for fixed-point variant. */ | |
037e8744 | 17084 | nUF(vcvtq, vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), |
b7fc2769 | 17085 | |
5287ad62 JB |
17086 | nUF(vmvn, vmvn, 2, (RNDQ, RNDQ_IMVNb), neon_mvn), |
17087 | nUF(vmvnq, vmvn, 2, (RNQ, RNDQ_IMVNb), neon_mvn), | |
17088 | ||
17089 | /* Data processing, three registers of different lengths. */ | |
17090 | /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ | |
17091 | NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), | |
17092 | NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), | |
17093 | NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), | |
17094 | NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), | |
17095 | /* If not scalar, fall back to neon_dyadic_long. | |
17096 | Vector types as above, scalar types S16 S32 U16 U32. */ | |
17097 | nUF(vmlal, vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), | |
17098 | nUF(vmlsl, vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), | |
17099 | /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ | |
17100 | NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
17101 | NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
17102 | /* Dyadic, narrowing insns. Types I16 I32 I64. */ | |
17103 | NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
17104 | NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
17105 | NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
17106 | NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
17107 | /* Saturating doubling multiplies. Types S16 S32. */ | |
17108 | nUF(vqdmlal, vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
17109 | nUF(vqdmlsl, vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
17110 | nUF(vqdmull, vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
17111 | /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types | |
17112 | S16 S32 U16 U32. */ | |
17113 | nUF(vmull, vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), | |
17114 | ||
17115 | /* Extract. Size 8. */ | |
3b8d421e PB |
17116 | NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), |
17117 | NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), | |
5287ad62 JB |
17118 | |
17119 | /* Two registers, miscellaneous. */ | |
17120 | /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ | |
17121 | NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), | |
17122 | NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), | |
17123 | NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), | |
17124 | NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), | |
17125 | NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), | |
17126 | NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), | |
17127 | /* Vector replicate. Sizes 8 16 32. */ | |
17128 | nCE(vdup, vdup, 2, (RNDQ, RR_RNSC), neon_dup), | |
17129 | nCE(vdupq, vdup, 2, (RNQ, RR_RNSC), neon_dup), | |
17130 | /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ | |
17131 | NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), | |
17132 | /* VMOVN. Types I16 I32 I64. */ | |
17133 | nUF(vmovn, vmovn, 2, (RND, RNQ), neon_movn), | |
17134 | /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ | |
17135 | nUF(vqmovn, vqmovn, 2, (RND, RNQ), neon_qmovn), | |
17136 | /* VQMOVUN. Types S16 S32 S64. */ | |
17137 | nUF(vqmovun, vqmovun, 2, (RND, RNQ), neon_qmovun), | |
17138 | /* VZIP / VUZP. Sizes 8 16 32. */ | |
17139 | NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
17140 | NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), | |
17141 | NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
17142 | NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), | |
17143 | /* VQABS / VQNEG. Types S8 S16 S32. */ | |
17144 | NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
17145 | NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
17146 | NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
17147 | NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
17148 | /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ | |
17149 | NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), | |
17150 | NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), | |
17151 | NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), | |
17152 | NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), | |
17153 | /* Reciprocal estimates. Types U32 F32. */ | |
17154 | NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), | |
17155 | NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), | |
17156 | NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), | |
17157 | NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), | |
17158 | /* VCLS. Types S8 S16 S32. */ | |
17159 | NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), | |
17160 | NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), | |
17161 | /* VCLZ. Types I8 I16 I32. */ | |
17162 | NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), | |
17163 | NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), | |
17164 | /* VCNT. Size 8. */ | |
17165 | NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), | |
17166 | NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), | |
17167 | /* Two address, untyped. */ | |
17168 | NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), | |
17169 | NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), | |
17170 | /* VTRN. Sizes 8 16 32. */ | |
17171 | nUF(vtrn, vtrn, 2, (RNDQ, RNDQ), neon_trn), | |
17172 | nUF(vtrnq, vtrn, 2, (RNQ, RNQ), neon_trn), | |
17173 | ||
17174 | /* Table lookup. Size 8. */ | |
17175 | NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
17176 | NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
17177 | ||
b7fc2769 JB |
17178 | #undef THUMB_VARIANT |
17179 | #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext | |
17180 | #undef ARM_VARIANT | |
17181 | #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext | |
5287ad62 JB |
17182 | /* Neon element/structure load/store. */ |
17183 | nUF(vld1, vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17184 | nUF(vst1, vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17185 | nUF(vld2, vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17186 | nUF(vst2, vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17187 | nUF(vld3, vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17188 | nUF(vst3, vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17189 | nUF(vld4, vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17190 | nUF(vst4, vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17191 | ||
17192 | #undef THUMB_VARIANT | |
17193 | #define THUMB_VARIANT &fpu_vfp_ext_v3 | |
17194 | #undef ARM_VARIANT | |
17195 | #define ARM_VARIANT &fpu_vfp_ext_v3 | |
5287ad62 JB |
17196 | cCE(fconsts, eb00a00, 2, (RVS, I255), vfp_sp_const), |
17197 | cCE(fconstd, eb00b00, 2, (RVD, I255), vfp_dp_const), | |
17198 | cCE(fshtos, eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
17199 | cCE(fshtod, eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), | |
17200 | cCE(fsltos, eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
17201 | cCE(fsltod, eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), | |
17202 | cCE(fuhtos, ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
17203 | cCE(fuhtod, ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), | |
17204 | cCE(fultos, ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
17205 | cCE(fultod, ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), | |
17206 | cCE(ftoshs, ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
17207 | cCE(ftoshd, ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), | |
17208 | cCE(ftosls, ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
17209 | cCE(ftosld, ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), | |
17210 | cCE(ftouhs, ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
17211 | cCE(ftouhd, ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), | |
17212 | cCE(ftouls, ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
17213 | cCE(ftould, ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), | |
c19d1205 | 17214 | |
5287ad62 | 17215 | #undef THUMB_VARIANT |
c19d1205 | 17216 | #undef ARM_VARIANT |
e74cfd16 | 17217 | #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */ |
8f06b2d8 PB |
17218 | cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
17219 | cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
17220 | cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
17221 | cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
17222 | cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
17223 | cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
17224 | cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
17225 | cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 ZW |
17226 | |
17227 | #undef ARM_VARIANT | |
e74cfd16 | 17228 | #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */ |
8f06b2d8 PB |
17229 | cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc), |
17230 | cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc), | |
17231 | cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc), | |
17232 | cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd), | |
17233 | cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd), | |
17234 | cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd), | |
17235 | cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc), | |
17236 | cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc), | |
17237 | cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc), | |
17238 | cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
17239 | cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
17240 | cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
17241 | cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
17242 | cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
17243 | cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
17244 | cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
17245 | cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
17246 | cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
41adaa5c | 17247 | cCE(tmcr, e000110, 2, (RIWC_RIWG, RR), rn_rd), |
8f06b2d8 PB |
17248 | cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn), |
17249 | cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
17250 | cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
17251 | cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
17252 | cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
17253 | cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
17254 | cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
17255 | cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn), | |
17256 | cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn), | |
17257 | cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn), | |
41adaa5c | 17258 | cCE(tmrc, e100110, 2, (RR, RIWC_RIWG), rd_rn), |
8f06b2d8 PB |
17259 | cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm), |
17260 | cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc), | |
17261 | cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc), | |
17262 | cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc), | |
17263 | cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn), | |
17264 | cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn), | |
17265 | cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn), | |
17266 | cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17267 | cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17268 | cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17269 | cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17270 | cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17271 | cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17272 | cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17273 | cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17274 | cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17275 | cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
17276 | cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17277 | cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17278 | cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17279 | cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17280 | cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17281 | cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17282 | cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17283 | cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17284 | cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17285 | cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17286 | cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17287 | cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17288 | cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17289 | cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17290 | cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17291 | cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17292 | cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17293 | cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17294 | cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17295 | cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
17296 | cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
17297 | cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
17298 | cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
17299 | cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17300 | cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17301 | cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17302 | cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17303 | cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17304 | cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17305 | cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17306 | cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17307 | cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17308 | cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17309 | cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17310 | cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17311 | cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17312 | cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17313 | cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17314 | cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17315 | cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17316 | cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17317 | cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
17318 | cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17319 | cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17320 | cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17321 | cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17322 | cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17323 | cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17324 | cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17325 | cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17326 | cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17327 | cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17328 | cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
2d447fca | 17329 | cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
8f06b2d8 | 17330 | cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
2d447fca | 17331 | cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
8f06b2d8 | 17332 | cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
2d447fca | 17333 | cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
8f06b2d8 PB |
17334 | cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
17335 | cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17336 | cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17337 | cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17338 | cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17339 | cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
2d447fca | 17340 | cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
8f06b2d8 | 17341 | cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
2d447fca | 17342 | cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
8f06b2d8 | 17343 | cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
2d447fca | 17344 | cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
8f06b2d8 | 17345 | cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
2d447fca | 17346 | cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
8f06b2d8 | 17347 | cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
2d447fca | 17348 | cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
8f06b2d8 | 17349 | cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
2d447fca | 17350 | cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
8f06b2d8 | 17351 | cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
2d447fca | 17352 | cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
8f06b2d8 | 17353 | cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
2d447fca | 17354 | cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
8f06b2d8 | 17355 | cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
2d447fca | 17356 | cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
8f06b2d8 PB |
17357 | cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
17358 | cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
17359 | cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
17360 | cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
17361 | cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
17362 | cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17363 | cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17364 | cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17365 | cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17366 | cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17367 | cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17368 | cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17369 | cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17370 | cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17371 | cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn), | |
17372 | cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn), | |
17373 | cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn), | |
17374 | cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn), | |
17375 | cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn), | |
17376 | cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn), | |
17377 | cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17378 | cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17379 | cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17380 | cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn), | |
17381 | cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn), | |
17382 | cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn), | |
17383 | cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn), | |
17384 | cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn), | |
17385 | cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn), | |
17386 | cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17387 | cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17388 | cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17389 | cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17390 | cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 | 17391 | |
2d447fca JM |
17392 | #undef ARM_VARIANT |
17393 | #define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ | |
17394 | cCE(torvscb, e13f190, 1, (RR), iwmmxt_tandorc), | |
17395 | cCE(torvsch, e53f190, 1, (RR), iwmmxt_tandorc), | |
17396 | cCE(torvscw, e93f190, 1, (RR), iwmmxt_tandorc), | |
17397 | cCE(wabsb, e2001c0, 2, (RIWR, RIWR), rd_rn), | |
17398 | cCE(wabsh, e6001c0, 2, (RIWR, RIWR), rd_rn), | |
17399 | cCE(wabsw, ea001c0, 2, (RIWR, RIWR), rd_rn), | |
17400 | cCE(wabsdiffb, e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17401 | cCE(wabsdiffh, e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17402 | cCE(wabsdiffw, e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17403 | cCE(waddbhusl, e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17404 | cCE(waddbhusm, e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17405 | cCE(waddhc, e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17406 | cCE(waddwc, ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17407 | cCE(waddsubhx, ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17408 | cCE(wavg4, e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17409 | cCE(wavg4r, e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17410 | cCE(wmaddsn, ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17411 | cCE(wmaddsx, eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17412 | cCE(wmaddun, ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17413 | cCE(wmaddux, e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17414 | cCE(wmerge, e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), | |
17415 | cCE(wmiabb, e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17416 | cCE(wmiabt, e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17417 | cCE(wmiatb, e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17418 | cCE(wmiatt, e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17419 | cCE(wmiabbn, e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17420 | cCE(wmiabtn, e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17421 | cCE(wmiatbn, e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17422 | cCE(wmiattn, e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17423 | cCE(wmiawbb, e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17424 | cCE(wmiawbt, e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17425 | cCE(wmiawtb, ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17426 | cCE(wmiawtt, eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17427 | cCE(wmiawbbn, ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17428 | cCE(wmiawbtn, ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17429 | cCE(wmiawtbn, ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17430 | cCE(wmiawttn, ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17431 | cCE(wmulsmr, ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17432 | cCE(wmulumr, ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17433 | cCE(wmulwumr, ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17434 | cCE(wmulwsmr, ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17435 | cCE(wmulwum, ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17436 | cCE(wmulwsm, ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17437 | cCE(wmulwl, eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17438 | cCE(wqmiabb, e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17439 | cCE(wqmiabt, e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17440 | cCE(wqmiatb, ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17441 | cCE(wqmiatt, eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17442 | cCE(wqmiabbn, ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17443 | cCE(wqmiabtn, ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17444 | cCE(wqmiatbn, ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17445 | cCE(wqmiattn, ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17446 | cCE(wqmulm, e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17447 | cCE(wqmulmr, e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17448 | cCE(wqmulwm, ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17449 | cCE(wqmulwmr, ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17450 | cCE(wsubaddhx, ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17451 | ||
c19d1205 | 17452 | #undef ARM_VARIANT |
e74cfd16 | 17453 | #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */ |
4962c51a MS |
17454 | cCE(cfldrs, c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), |
17455 | cCE(cfldrd, c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
17456 | cCE(cfldr32, c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
17457 | cCE(cfldr64, c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
17458 | cCE(cfstrs, c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), | |
17459 | cCE(cfstrd, c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
17460 | cCE(cfstr32, c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
17461 | cCE(cfstr64, c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
8f06b2d8 PB |
17462 | cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd), |
17463 | cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn), | |
17464 | cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd), | |
17465 | cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn), | |
17466 | cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd), | |
17467 | cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn), | |
17468 | cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd), | |
17469 | cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn), | |
17470 | cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd), | |
17471 | cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn), | |
17472 | cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn), | |
17473 | cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn), | |
17474 | cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn), | |
17475 | cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn), | |
17476 | cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn), | |
17477 | cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn), | |
17478 | cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn), | |
17479 | cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn), | |
17480 | cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn), | |
17481 | cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn), | |
17482 | cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc), | |
17483 | cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd), | |
17484 | cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn), | |
17485 | cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn), | |
17486 | cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn), | |
17487 | cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn), | |
17488 | cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn), | |
17489 | cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn), | |
17490 | cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn), | |
17491 | cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn), | |
17492 | cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn), | |
17493 | cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn), | |
17494 | cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn), | |
17495 | cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn), | |
17496 | cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple), | |
17497 | cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
17498 | cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift), | |
17499 | cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
17500 | cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
17501 | cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
17502 | cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
17503 | cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
17504 | cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn), | |
17505 | cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn), | |
17506 | cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn), | |
17507 | cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn), | |
17508 | cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
17509 | cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
17510 | cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
17511 | cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
17512 | cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
17513 | cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
17514 | cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn), | |
17515 | cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn), | |
17516 | cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn), | |
17517 | cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn), | |
17518 | cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
17519 | cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
17520 | cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
17521 | cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
17522 | cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
17523 | cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
17524 | cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
17525 | cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
17526 | cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
17527 | cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
17528 | cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
17529 | cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
c19d1205 ZW |
17530 | }; |
17531 | #undef ARM_VARIANT | |
17532 | #undef THUMB_VARIANT | |
17533 | #undef TCE | |
17534 | #undef TCM | |
17535 | #undef TUE | |
17536 | #undef TUF | |
17537 | #undef TCC | |
8f06b2d8 | 17538 | #undef cCE |
e3cb604e PB |
17539 | #undef cCL |
17540 | #undef C3E | |
c19d1205 ZW |
17541 | #undef CE |
17542 | #undef CM | |
17543 | #undef UE | |
17544 | #undef UF | |
17545 | #undef UT | |
5287ad62 JB |
17546 | #undef NUF |
17547 | #undef nUF | |
17548 | #undef NCE | |
17549 | #undef nCE | |
c19d1205 ZW |
17550 | #undef OPS0 |
17551 | #undef OPS1 | |
17552 | #undef OPS2 | |
17553 | #undef OPS3 | |
17554 | #undef OPS4 | |
17555 | #undef OPS5 | |
17556 | #undef OPS6 | |
17557 | #undef do_0 | |
17558 | \f | |
17559 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 17560 | |
c19d1205 ZW |
17561 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
17562 | for use in the a.out file, and stores them in the array pointed to by buf. | |
17563 | This knows about the endian-ness of the target machine and does | |
17564 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
17565 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
17566 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 17567 | |
c19d1205 ZW |
17568 | void |
17569 | md_number_to_chars (char * buf, valueT val, int n) | |
17570 | { | |
17571 | if (target_big_endian) | |
17572 | number_to_chars_bigendian (buf, val, n); | |
17573 | else | |
17574 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
17575 | } |
17576 | ||
c19d1205 ZW |
17577 | static valueT |
17578 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 17579 | { |
c19d1205 ZW |
17580 | valueT result = 0; |
17581 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 17582 | |
c19d1205 | 17583 | if (target_big_endian) |
b99bd4ef | 17584 | { |
c19d1205 ZW |
17585 | while (n--) |
17586 | { | |
17587 | result <<= 8; | |
17588 | result |= (*where++ & 255); | |
17589 | } | |
b99bd4ef | 17590 | } |
c19d1205 | 17591 | else |
b99bd4ef | 17592 | { |
c19d1205 ZW |
17593 | while (n--) |
17594 | { | |
17595 | result <<= 8; | |
17596 | result |= (where[n] & 255); | |
17597 | } | |
bfae80f2 | 17598 | } |
b99bd4ef | 17599 | |
c19d1205 | 17600 | return result; |
bfae80f2 | 17601 | } |
b99bd4ef | 17602 | |
c19d1205 | 17603 | /* MD interface: Sections. */ |
b99bd4ef | 17604 | |
0110f2b8 PB |
17605 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
17606 | 2 bytes. */ | |
17607 | ||
c19d1205 | 17608 | int |
0110f2b8 | 17609 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
17610 | segT segtype ATTRIBUTE_UNUSED) |
17611 | { | |
0110f2b8 PB |
17612 | fragp->fr_var = 2; |
17613 | return 2; | |
17614 | } | |
17615 | ||
17616 | /* Convert a machine dependent frag. */ | |
17617 | ||
17618 | void | |
17619 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
17620 | { | |
17621 | unsigned long insn; | |
17622 | unsigned long old_op; | |
17623 | char *buf; | |
17624 | expressionS exp; | |
17625 | fixS *fixp; | |
17626 | int reloc_type; | |
17627 | int pc_rel; | |
17628 | int opcode; | |
17629 | ||
17630 | buf = fragp->fr_literal + fragp->fr_fix; | |
17631 | ||
17632 | old_op = bfd_get_16(abfd, buf); | |
5f4273c7 NC |
17633 | if (fragp->fr_symbol) |
17634 | { | |
0110f2b8 PB |
17635 | exp.X_op = O_symbol; |
17636 | exp.X_add_symbol = fragp->fr_symbol; | |
5f4273c7 NC |
17637 | } |
17638 | else | |
17639 | { | |
0110f2b8 | 17640 | exp.X_op = O_constant; |
5f4273c7 | 17641 | } |
0110f2b8 PB |
17642 | exp.X_add_number = fragp->fr_offset; |
17643 | opcode = fragp->fr_subtype; | |
17644 | switch (opcode) | |
17645 | { | |
17646 | case T_MNEM_ldr_pc: | |
17647 | case T_MNEM_ldr_pc2: | |
17648 | case T_MNEM_ldr_sp: | |
17649 | case T_MNEM_str_sp: | |
17650 | case T_MNEM_ldr: | |
17651 | case T_MNEM_ldrb: | |
17652 | case T_MNEM_ldrh: | |
17653 | case T_MNEM_str: | |
17654 | case T_MNEM_strb: | |
17655 | case T_MNEM_strh: | |
17656 | if (fragp->fr_var == 4) | |
17657 | { | |
5f4273c7 | 17658 | insn = THUMB_OP32 (opcode); |
0110f2b8 PB |
17659 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) |
17660 | { | |
17661 | insn |= (old_op & 0x700) << 4; | |
17662 | } | |
17663 | else | |
17664 | { | |
17665 | insn |= (old_op & 7) << 12; | |
17666 | insn |= (old_op & 0x38) << 13; | |
17667 | } | |
17668 | insn |= 0x00000c00; | |
17669 | put_thumb32_insn (buf, insn); | |
17670 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
17671 | } | |
17672 | else | |
17673 | { | |
17674 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
17675 | } | |
17676 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
17677 | break; | |
17678 | case T_MNEM_adr: | |
17679 | if (fragp->fr_var == 4) | |
17680 | { | |
17681 | insn = THUMB_OP32 (opcode); | |
17682 | insn |= (old_op & 0xf0) << 4; | |
17683 | put_thumb32_insn (buf, insn); | |
17684 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
17685 | } | |
17686 | else | |
17687 | { | |
17688 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
17689 | exp.X_add_number -= 4; | |
17690 | } | |
17691 | pc_rel = 1; | |
17692 | break; | |
17693 | case T_MNEM_mov: | |
17694 | case T_MNEM_movs: | |
17695 | case T_MNEM_cmp: | |
17696 | case T_MNEM_cmn: | |
17697 | if (fragp->fr_var == 4) | |
17698 | { | |
17699 | int r0off = (opcode == T_MNEM_mov | |
17700 | || opcode == T_MNEM_movs) ? 0 : 8; | |
17701 | insn = THUMB_OP32 (opcode); | |
17702 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
17703 | insn |= (old_op & 0x700) << r0off; | |
17704 | put_thumb32_insn (buf, insn); | |
17705 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
17706 | } | |
17707 | else | |
17708 | { | |
17709 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
17710 | } | |
17711 | pc_rel = 0; | |
17712 | break; | |
17713 | case T_MNEM_b: | |
17714 | if (fragp->fr_var == 4) | |
17715 | { | |
17716 | insn = THUMB_OP32(opcode); | |
17717 | put_thumb32_insn (buf, insn); | |
17718 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
17719 | } | |
17720 | else | |
17721 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
17722 | pc_rel = 1; | |
17723 | break; | |
17724 | case T_MNEM_bcond: | |
17725 | if (fragp->fr_var == 4) | |
17726 | { | |
17727 | insn = THUMB_OP32(opcode); | |
17728 | insn |= (old_op & 0xf00) << 14; | |
17729 | put_thumb32_insn (buf, insn); | |
17730 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
17731 | } | |
17732 | else | |
17733 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
17734 | pc_rel = 1; | |
17735 | break; | |
17736 | case T_MNEM_add_sp: | |
17737 | case T_MNEM_add_pc: | |
17738 | case T_MNEM_inc_sp: | |
17739 | case T_MNEM_dec_sp: | |
17740 | if (fragp->fr_var == 4) | |
17741 | { | |
17742 | /* ??? Choose between add and addw. */ | |
17743 | insn = THUMB_OP32 (opcode); | |
17744 | insn |= (old_op & 0xf0) << 4; | |
17745 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
17746 | if (opcode == T_MNEM_add_pc) |
17747 | reloc_type = BFD_RELOC_ARM_T32_IMM12; | |
17748 | else | |
17749 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
0110f2b8 PB |
17750 | } |
17751 | else | |
17752 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
17753 | pc_rel = 0; | |
17754 | break; | |
17755 | ||
17756 | case T_MNEM_addi: | |
17757 | case T_MNEM_addis: | |
17758 | case T_MNEM_subi: | |
17759 | case T_MNEM_subis: | |
17760 | if (fragp->fr_var == 4) | |
17761 | { | |
17762 | insn = THUMB_OP32 (opcode); | |
17763 | insn |= (old_op & 0xf0) << 4; | |
17764 | insn |= (old_op & 0xf) << 16; | |
17765 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
17766 | if (insn & (1 << 20)) |
17767 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
17768 | else | |
17769 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
0110f2b8 PB |
17770 | } |
17771 | else | |
17772 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
17773 | pc_rel = 0; | |
17774 | break; | |
17775 | default: | |
5f4273c7 | 17776 | abort (); |
0110f2b8 PB |
17777 | } |
17778 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
17779 | reloc_type); | |
17780 | fixp->fx_file = fragp->fr_file; | |
17781 | fixp->fx_line = fragp->fr_line; | |
17782 | fragp->fr_fix += fragp->fr_var; | |
17783 | } | |
17784 | ||
17785 | /* Return the size of a relaxable immediate operand instruction. | |
17786 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
17787 | static int | |
17788 | relax_immediate (fragS *fragp, int size, int shift) | |
17789 | { | |
17790 | offsetT offset; | |
17791 | offsetT mask; | |
17792 | offsetT low; | |
17793 | ||
17794 | /* ??? Should be able to do better than this. */ | |
17795 | if (fragp->fr_symbol) | |
17796 | return 4; | |
17797 | ||
17798 | low = (1 << shift) - 1; | |
17799 | mask = (1 << (shift + size)) - (1 << shift); | |
17800 | offset = fragp->fr_offset; | |
17801 | /* Force misaligned offsets to 32-bit variant. */ | |
17802 | if (offset & low) | |
5e77afaa | 17803 | return 4; |
0110f2b8 PB |
17804 | if (offset & ~mask) |
17805 | return 4; | |
17806 | return 2; | |
17807 | } | |
17808 | ||
5e77afaa PB |
17809 | /* Get the address of a symbol during relaxation. */ |
17810 | static addressT | |
5f4273c7 | 17811 | relaxed_symbol_addr (fragS *fragp, long stretch) |
5e77afaa PB |
17812 | { |
17813 | fragS *sym_frag; | |
17814 | addressT addr; | |
17815 | symbolS *sym; | |
17816 | ||
17817 | sym = fragp->fr_symbol; | |
17818 | sym_frag = symbol_get_frag (sym); | |
17819 | know (S_GET_SEGMENT (sym) != absolute_section | |
17820 | || sym_frag == &zero_address_frag); | |
17821 | addr = S_GET_VALUE (sym) + fragp->fr_offset; | |
17822 | ||
17823 | /* If frag has yet to be reached on this pass, assume it will | |
17824 | move by STRETCH just as we did. If this is not so, it will | |
17825 | be because some frag between grows, and that will force | |
17826 | another pass. */ | |
17827 | ||
17828 | if (stretch != 0 | |
17829 | && sym_frag->relax_marker != fragp->relax_marker) | |
4396b686 PB |
17830 | { |
17831 | fragS *f; | |
17832 | ||
17833 | /* Adjust stretch for any alignment frag. Note that if have | |
17834 | been expanding the earlier code, the symbol may be | |
17835 | defined in what appears to be an earlier frag. FIXME: | |
17836 | This doesn't handle the fr_subtype field, which specifies | |
17837 | a maximum number of bytes to skip when doing an | |
17838 | alignment. */ | |
17839 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
17840 | { | |
17841 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17842 | { | |
17843 | if (stretch < 0) | |
17844 | stretch = - ((- stretch) | |
17845 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
17846 | else | |
17847 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
17848 | if (stretch == 0) | |
17849 | break; | |
17850 | } | |
17851 | } | |
17852 | if (f != NULL) | |
17853 | addr += stretch; | |
17854 | } | |
5e77afaa PB |
17855 | |
17856 | return addr; | |
17857 | } | |
17858 | ||
0110f2b8 PB |
17859 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative |
17860 | load. */ | |
17861 | static int | |
5e77afaa | 17862 | relax_adr (fragS *fragp, asection *sec, long stretch) |
0110f2b8 PB |
17863 | { |
17864 | addressT addr; | |
17865 | offsetT val; | |
17866 | ||
17867 | /* Assume worst case for symbols not known to be in the same section. */ | |
5f4273c7 | 17868 | if (!S_IS_DEFINED (fragp->fr_symbol) |
0110f2b8 PB |
17869 | || sec != S_GET_SEGMENT (fragp->fr_symbol)) |
17870 | return 4; | |
17871 | ||
5f4273c7 | 17872 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
17873 | addr = fragp->fr_address + fragp->fr_fix; |
17874 | addr = (addr + 4) & ~3; | |
5e77afaa | 17875 | /* Force misaligned targets to 32-bit variant. */ |
0110f2b8 | 17876 | if (val & 3) |
5e77afaa | 17877 | return 4; |
0110f2b8 PB |
17878 | val -= addr; |
17879 | if (val < 0 || val > 1020) | |
17880 | return 4; | |
17881 | return 2; | |
17882 | } | |
17883 | ||
17884 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
17885 | static int | |
17886 | relax_addsub (fragS *fragp, asection *sec) | |
17887 | { | |
17888 | char *buf; | |
17889 | int op; | |
17890 | ||
17891 | buf = fragp->fr_literal + fragp->fr_fix; | |
17892 | op = bfd_get_16(sec->owner, buf); | |
17893 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
17894 | return relax_immediate (fragp, 8, 0); | |
17895 | else | |
17896 | return relax_immediate (fragp, 3, 0); | |
17897 | } | |
17898 | ||
17899 | ||
17900 | /* Return the size of a relaxable branch instruction. BITS is the | |
17901 | size of the offset field in the narrow instruction. */ | |
17902 | ||
17903 | static int | |
5e77afaa | 17904 | relax_branch (fragS *fragp, asection *sec, int bits, long stretch) |
0110f2b8 PB |
17905 | { |
17906 | addressT addr; | |
17907 | offsetT val; | |
17908 | offsetT limit; | |
17909 | ||
17910 | /* Assume worst case for symbols not known to be in the same section. */ | |
5f4273c7 | 17911 | if (!S_IS_DEFINED (fragp->fr_symbol) |
0110f2b8 PB |
17912 | || sec != S_GET_SEGMENT (fragp->fr_symbol)) |
17913 | return 4; | |
17914 | ||
267bf995 RR |
17915 | #ifdef OBJ_ELF |
17916 | if (S_IS_DEFINED (fragp->fr_symbol) | |
17917 | && ARM_IS_FUNC (fragp->fr_symbol)) | |
17918 | return 4; | |
17919 | #endif | |
17920 | ||
5f4273c7 | 17921 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
17922 | addr = fragp->fr_address + fragp->fr_fix + 4; |
17923 | val -= addr; | |
17924 | ||
17925 | /* Offset is a signed value *2 */ | |
17926 | limit = 1 << bits; | |
17927 | if (val >= limit || val < -limit) | |
17928 | return 4; | |
17929 | return 2; | |
17930 | } | |
17931 | ||
17932 | ||
17933 | /* Relax a machine dependent frag. This returns the amount by which | |
17934 | the current size of the frag should change. */ | |
17935 | ||
17936 | int | |
5e77afaa | 17937 | arm_relax_frag (asection *sec, fragS *fragp, long stretch) |
0110f2b8 PB |
17938 | { |
17939 | int oldsize; | |
17940 | int newsize; | |
17941 | ||
17942 | oldsize = fragp->fr_var; | |
17943 | switch (fragp->fr_subtype) | |
17944 | { | |
17945 | case T_MNEM_ldr_pc2: | |
5f4273c7 | 17946 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
17947 | break; |
17948 | case T_MNEM_ldr_pc: | |
17949 | case T_MNEM_ldr_sp: | |
17950 | case T_MNEM_str_sp: | |
5f4273c7 | 17951 | newsize = relax_immediate (fragp, 8, 2); |
0110f2b8 PB |
17952 | break; |
17953 | case T_MNEM_ldr: | |
17954 | case T_MNEM_str: | |
5f4273c7 | 17955 | newsize = relax_immediate (fragp, 5, 2); |
0110f2b8 PB |
17956 | break; |
17957 | case T_MNEM_ldrh: | |
17958 | case T_MNEM_strh: | |
5f4273c7 | 17959 | newsize = relax_immediate (fragp, 5, 1); |
0110f2b8 PB |
17960 | break; |
17961 | case T_MNEM_ldrb: | |
17962 | case T_MNEM_strb: | |
5f4273c7 | 17963 | newsize = relax_immediate (fragp, 5, 0); |
0110f2b8 PB |
17964 | break; |
17965 | case T_MNEM_adr: | |
5f4273c7 | 17966 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
17967 | break; |
17968 | case T_MNEM_mov: | |
17969 | case T_MNEM_movs: | |
17970 | case T_MNEM_cmp: | |
17971 | case T_MNEM_cmn: | |
5f4273c7 | 17972 | newsize = relax_immediate (fragp, 8, 0); |
0110f2b8 PB |
17973 | break; |
17974 | case T_MNEM_b: | |
5f4273c7 | 17975 | newsize = relax_branch (fragp, sec, 11, stretch); |
0110f2b8 PB |
17976 | break; |
17977 | case T_MNEM_bcond: | |
5f4273c7 | 17978 | newsize = relax_branch (fragp, sec, 8, stretch); |
0110f2b8 PB |
17979 | break; |
17980 | case T_MNEM_add_sp: | |
17981 | case T_MNEM_add_pc: | |
17982 | newsize = relax_immediate (fragp, 8, 2); | |
17983 | break; | |
17984 | case T_MNEM_inc_sp: | |
17985 | case T_MNEM_dec_sp: | |
17986 | newsize = relax_immediate (fragp, 7, 2); | |
17987 | break; | |
17988 | case T_MNEM_addi: | |
17989 | case T_MNEM_addis: | |
17990 | case T_MNEM_subi: | |
17991 | case T_MNEM_subis: | |
17992 | newsize = relax_addsub (fragp, sec); | |
17993 | break; | |
17994 | default: | |
5f4273c7 | 17995 | abort (); |
0110f2b8 | 17996 | } |
5e77afaa PB |
17997 | |
17998 | fragp->fr_var = newsize; | |
17999 | /* Freeze wide instructions that are at or before the same location as | |
18000 | in the previous pass. This avoids infinite loops. | |
5f4273c7 NC |
18001 | Don't freeze them unconditionally because targets may be artificially |
18002 | misaligned by the expansion of preceding frags. */ | |
5e77afaa | 18003 | if (stretch <= 0 && newsize > 2) |
0110f2b8 | 18004 | { |
0110f2b8 | 18005 | md_convert_frag (sec->owner, sec, fragp); |
5f4273c7 | 18006 | frag_wane (fragp); |
0110f2b8 | 18007 | } |
5e77afaa | 18008 | |
0110f2b8 | 18009 | return newsize - oldsize; |
c19d1205 | 18010 | } |
b99bd4ef | 18011 | |
c19d1205 | 18012 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 18013 | |
c19d1205 ZW |
18014 | valueT |
18015 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
18016 | valueT size) | |
18017 | { | |
f0927246 NC |
18018 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
18019 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
18020 | { | |
18021 | /* For a.out, force the section size to be aligned. If we don't do | |
18022 | this, BFD will align it for us, but it will not write out the | |
18023 | final bytes of the section. This may be a bug in BFD, but it is | |
18024 | easier to fix it here since that is how the other a.out targets | |
18025 | work. */ | |
18026 | int align; | |
18027 | ||
18028 | align = bfd_get_section_alignment (stdoutput, segment); | |
18029 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
18030 | } | |
c19d1205 | 18031 | #endif |
f0927246 NC |
18032 | |
18033 | return size; | |
bfae80f2 | 18034 | } |
b99bd4ef | 18035 | |
c19d1205 ZW |
18036 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
18037 | of an rs_align_code fragment. */ | |
18038 | ||
18039 | void | |
18040 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 18041 | { |
e7495e45 NS |
18042 | static char const arm_noop[2][2][4] = |
18043 | { | |
18044 | { /* ARMv1 */ | |
18045 | {0x00, 0x00, 0xa0, 0xe1}, /* LE */ | |
18046 | {0xe1, 0xa0, 0x00, 0x00}, /* BE */ | |
18047 | }, | |
18048 | { /* ARMv6k */ | |
18049 | {0x00, 0xf0, 0x20, 0xe3}, /* LE */ | |
18050 | {0xe3, 0x20, 0xf0, 0x00}, /* BE */ | |
18051 | }, | |
18052 | }; | |
18053 | static char const thumb_noop[2][2][2] = | |
18054 | { | |
18055 | { /* Thumb-1 */ | |
18056 | {0xc0, 0x46}, /* LE */ | |
18057 | {0x46, 0xc0}, /* BE */ | |
18058 | }, | |
18059 | { /* Thumb-2 */ | |
18060 | {0x00, 0xbf}, /* LE */ | |
18061 | {0xbf, 0x00} /* BE */ | |
18062 | } | |
18063 | }; | |
18064 | static char const wide_thumb_noop[2][4] = | |
18065 | { /* Wide Thumb-2 */ | |
18066 | {0xaf, 0xf3, 0x00, 0x80}, /* LE */ | |
18067 | {0xf3, 0xaf, 0x80, 0x00}, /* BE */ | |
18068 | }; | |
18069 | ||
18070 | unsigned bytes, fix, noop_size; | |
c19d1205 ZW |
18071 | char * p; |
18072 | const char * noop; | |
e7495e45 | 18073 | const char *narrow_noop = NULL; |
bfae80f2 | 18074 | |
c19d1205 | 18075 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
18076 | return; |
18077 | ||
c19d1205 ZW |
18078 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
18079 | p = fragP->fr_literal + fragP->fr_fix; | |
18080 | fix = 0; | |
bfae80f2 | 18081 | |
c19d1205 ZW |
18082 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
18083 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 18084 | |
8dc2430f NC |
18085 | assert ((fragP->tc_frag_data & MODE_RECORDED) != 0); |
18086 | ||
18087 | if (fragP->tc_frag_data & (~ MODE_RECORDED)) | |
a737bd4d | 18088 | { |
e7495e45 NS |
18089 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
18090 | { | |
18091 | narrow_noop = thumb_noop[1][target_big_endian]; | |
18092 | noop = wide_thumb_noop[target_big_endian]; | |
18093 | } | |
c19d1205 | 18094 | else |
e7495e45 NS |
18095 | noop = thumb_noop[0][target_big_endian]; |
18096 | noop_size = 2; | |
7ed4c4c5 NC |
18097 | } |
18098 | else | |
18099 | { | |
e7495e45 NS |
18100 | noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0] |
18101 | [target_big_endian]; | |
18102 | noop_size = 4; | |
7ed4c4c5 | 18103 | } |
e7495e45 NS |
18104 | |
18105 | fragP->fr_var = noop_size; | |
18106 | ||
c19d1205 | 18107 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 18108 | { |
c19d1205 ZW |
18109 | fix = bytes & (noop_size - 1); |
18110 | memset (p, 0, fix); | |
18111 | p += fix; | |
18112 | bytes -= fix; | |
a737bd4d | 18113 | } |
a737bd4d | 18114 | |
e7495e45 NS |
18115 | if (narrow_noop) |
18116 | { | |
18117 | if (bytes & noop_size) | |
18118 | { | |
18119 | /* Insert a narrow noop. */ | |
18120 | memcpy (p, narrow_noop, noop_size); | |
18121 | p += noop_size; | |
18122 | bytes -= noop_size; | |
18123 | fix += noop_size; | |
18124 | } | |
18125 | ||
18126 | /* Use wide noops for the remainder */ | |
18127 | noop_size = 4; | |
18128 | } | |
18129 | ||
c19d1205 | 18130 | while (bytes >= noop_size) |
a737bd4d | 18131 | { |
c19d1205 ZW |
18132 | memcpy (p, noop, noop_size); |
18133 | p += noop_size; | |
18134 | bytes -= noop_size; | |
18135 | fix += noop_size; | |
a737bd4d NC |
18136 | } |
18137 | ||
c19d1205 | 18138 | fragP->fr_fix += fix; |
a737bd4d NC |
18139 | } |
18140 | ||
c19d1205 ZW |
18141 | /* Called from md_do_align. Used to create an alignment |
18142 | frag in a code section. */ | |
18143 | ||
18144 | void | |
18145 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 18146 | { |
c19d1205 | 18147 | char * p; |
7ed4c4c5 | 18148 | |
c19d1205 ZW |
18149 | /* We assume that there will never be a requirement |
18150 | to support alignments greater than 32 bytes. */ | |
18151 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) | |
18152 | as_fatal (_("alignments greater than 32 bytes not supported in .text sections.")); | |
bfae80f2 | 18153 | |
c19d1205 ZW |
18154 | p = frag_var (rs_align_code, |
18155 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
18156 | 1, | |
18157 | (relax_substateT) max, | |
18158 | (symbolS *) NULL, | |
18159 | (offsetT) n, | |
18160 | (char *) NULL); | |
18161 | *p = 0; | |
18162 | } | |
bfae80f2 | 18163 | |
8dc2430f NC |
18164 | /* Perform target specific initialisation of a frag. |
18165 | Note - despite the name this initialisation is not done when the frag | |
18166 | is created, but only when its type is assigned. A frag can be created | |
18167 | and used a long time before its type is set, so beware of assuming that | |
18168 | this initialisationis performed first. */ | |
bfae80f2 | 18169 | |
c19d1205 ZW |
18170 | void |
18171 | arm_init_frag (fragS * fragP) | |
18172 | { | |
8dc2430f NC |
18173 | /* If the current ARM vs THUMB mode has not already |
18174 | been recorded into this frag then do so now. */ | |
18175 | if ((fragP->tc_frag_data & MODE_RECORDED) == 0) | |
18176 | fragP->tc_frag_data = thumb_mode | MODE_RECORDED; | |
bfae80f2 RE |
18177 | } |
18178 | ||
c19d1205 ZW |
18179 | #ifdef OBJ_ELF |
18180 | /* When we change sections we need to issue a new mapping symbol. */ | |
18181 | ||
18182 | void | |
18183 | arm_elf_change_section (void) | |
bfae80f2 | 18184 | { |
c19d1205 ZW |
18185 | flagword flags; |
18186 | segment_info_type *seginfo; | |
bfae80f2 | 18187 | |
c19d1205 ZW |
18188 | /* Link an unlinked unwind index table section to the .text section. */ |
18189 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
18190 | && elf_linked_to_section (now_seg) == NULL) | |
18191 | elf_linked_to_section (now_seg) = text_section; | |
18192 | ||
18193 | if (!SEG_NORMAL (now_seg)) | |
bfae80f2 RE |
18194 | return; |
18195 | ||
c19d1205 ZW |
18196 | flags = bfd_get_section_flags (stdoutput, now_seg); |
18197 | ||
18198 | /* We can ignore sections that only contain debug info. */ | |
18199 | if ((flags & SEC_ALLOC) == 0) | |
18200 | return; | |
bfae80f2 | 18201 | |
c19d1205 ZW |
18202 | seginfo = seg_info (now_seg); |
18203 | mapstate = seginfo->tc_segment_info_data.mapstate; | |
18204 | marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency; | |
bfae80f2 RE |
18205 | } |
18206 | ||
c19d1205 ZW |
18207 | int |
18208 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 18209 | { |
c19d1205 ZW |
18210 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
18211 | return SHT_ARM_EXIDX; | |
e45d0630 | 18212 | |
c19d1205 ZW |
18213 | return -1; |
18214 | } | |
18215 | \f | |
18216 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 18217 | |
c19d1205 | 18218 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 18219 | |
5f4273c7 | 18220 | /* Generate any deferred unwind frame offset. */ |
e45d0630 | 18221 | |
bfae80f2 | 18222 | static void |
c19d1205 | 18223 | flush_pending_unwind (void) |
bfae80f2 | 18224 | { |
c19d1205 | 18225 | offsetT offset; |
bfae80f2 | 18226 | |
c19d1205 ZW |
18227 | offset = unwind.pending_offset; |
18228 | unwind.pending_offset = 0; | |
18229 | if (offset != 0) | |
18230 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
18231 | } |
18232 | ||
c19d1205 ZW |
18233 | /* Add an opcode to this list for this function. Two-byte opcodes should |
18234 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
18235 | order. */ | |
18236 | ||
bfae80f2 | 18237 | static void |
c19d1205 | 18238 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 18239 | { |
c19d1205 ZW |
18240 | /* Add any deferred stack adjustment. */ |
18241 | if (unwind.pending_offset) | |
18242 | flush_pending_unwind (); | |
bfae80f2 | 18243 | |
c19d1205 | 18244 | unwind.sp_restored = 0; |
bfae80f2 | 18245 | |
c19d1205 | 18246 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 18247 | { |
c19d1205 ZW |
18248 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
18249 | if (unwind.opcodes) | |
18250 | unwind.opcodes = xrealloc (unwind.opcodes, | |
18251 | unwind.opcode_alloc); | |
18252 | else | |
18253 | unwind.opcodes = xmalloc (unwind.opcode_alloc); | |
bfae80f2 | 18254 | } |
c19d1205 | 18255 | while (length > 0) |
bfae80f2 | 18256 | { |
c19d1205 ZW |
18257 | length--; |
18258 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
18259 | op >>= 8; | |
18260 | unwind.opcode_count++; | |
bfae80f2 | 18261 | } |
bfae80f2 RE |
18262 | } |
18263 | ||
c19d1205 ZW |
18264 | /* Add unwind opcodes to adjust the stack pointer. */ |
18265 | ||
bfae80f2 | 18266 | static void |
c19d1205 | 18267 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 18268 | { |
c19d1205 | 18269 | valueT op; |
bfae80f2 | 18270 | |
c19d1205 | 18271 | if (offset > 0x200) |
bfae80f2 | 18272 | { |
c19d1205 ZW |
18273 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
18274 | char bytes[5]; | |
18275 | int n; | |
18276 | valueT o; | |
bfae80f2 | 18277 | |
c19d1205 ZW |
18278 | /* Long form: 0xb2, uleb128. */ |
18279 | /* This might not fit in a word so add the individual bytes, | |
18280 | remembering the list is built in reverse order. */ | |
18281 | o = (valueT) ((offset - 0x204) >> 2); | |
18282 | if (o == 0) | |
18283 | add_unwind_opcode (0, 1); | |
bfae80f2 | 18284 | |
c19d1205 ZW |
18285 | /* Calculate the uleb128 encoding of the offset. */ |
18286 | n = 0; | |
18287 | while (o) | |
18288 | { | |
18289 | bytes[n] = o & 0x7f; | |
18290 | o >>= 7; | |
18291 | if (o) | |
18292 | bytes[n] |= 0x80; | |
18293 | n++; | |
18294 | } | |
18295 | /* Add the insn. */ | |
18296 | for (; n; n--) | |
18297 | add_unwind_opcode (bytes[n - 1], 1); | |
18298 | add_unwind_opcode (0xb2, 1); | |
18299 | } | |
18300 | else if (offset > 0x100) | |
bfae80f2 | 18301 | { |
c19d1205 ZW |
18302 | /* Two short opcodes. */ |
18303 | add_unwind_opcode (0x3f, 1); | |
18304 | op = (offset - 0x104) >> 2; | |
18305 | add_unwind_opcode (op, 1); | |
bfae80f2 | 18306 | } |
c19d1205 ZW |
18307 | else if (offset > 0) |
18308 | { | |
18309 | /* Short opcode. */ | |
18310 | op = (offset - 4) >> 2; | |
18311 | add_unwind_opcode (op, 1); | |
18312 | } | |
18313 | else if (offset < 0) | |
bfae80f2 | 18314 | { |
c19d1205 ZW |
18315 | offset = -offset; |
18316 | while (offset > 0x100) | |
bfae80f2 | 18317 | { |
c19d1205 ZW |
18318 | add_unwind_opcode (0x7f, 1); |
18319 | offset -= 0x100; | |
bfae80f2 | 18320 | } |
c19d1205 ZW |
18321 | op = ((offset - 4) >> 2) | 0x40; |
18322 | add_unwind_opcode (op, 1); | |
bfae80f2 | 18323 | } |
bfae80f2 RE |
18324 | } |
18325 | ||
c19d1205 ZW |
18326 | /* Finish the list of unwind opcodes for this function. */ |
18327 | static void | |
18328 | finish_unwind_opcodes (void) | |
bfae80f2 | 18329 | { |
c19d1205 | 18330 | valueT op; |
bfae80f2 | 18331 | |
c19d1205 | 18332 | if (unwind.fp_used) |
bfae80f2 | 18333 | { |
708587a4 | 18334 | /* Adjust sp as necessary. */ |
c19d1205 ZW |
18335 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; |
18336 | flush_pending_unwind (); | |
bfae80f2 | 18337 | |
c19d1205 ZW |
18338 | /* After restoring sp from the frame pointer. */ |
18339 | op = 0x90 | unwind.fp_reg; | |
18340 | add_unwind_opcode (op, 1); | |
18341 | } | |
18342 | else | |
18343 | flush_pending_unwind (); | |
bfae80f2 RE |
18344 | } |
18345 | ||
bfae80f2 | 18346 | |
c19d1205 ZW |
18347 | /* Start an exception table entry. If idx is nonzero this is an index table |
18348 | entry. */ | |
bfae80f2 RE |
18349 | |
18350 | static void | |
c19d1205 | 18351 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 18352 | { |
c19d1205 ZW |
18353 | const char * text_name; |
18354 | const char * prefix; | |
18355 | const char * prefix_once; | |
18356 | const char * group_name; | |
18357 | size_t prefix_len; | |
18358 | size_t text_len; | |
18359 | char * sec_name; | |
18360 | size_t sec_name_len; | |
18361 | int type; | |
18362 | int flags; | |
18363 | int linkonce; | |
bfae80f2 | 18364 | |
c19d1205 | 18365 | if (idx) |
bfae80f2 | 18366 | { |
c19d1205 ZW |
18367 | prefix = ELF_STRING_ARM_unwind; |
18368 | prefix_once = ELF_STRING_ARM_unwind_once; | |
18369 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 18370 | } |
c19d1205 | 18371 | else |
bfae80f2 | 18372 | { |
c19d1205 ZW |
18373 | prefix = ELF_STRING_ARM_unwind_info; |
18374 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
18375 | type = SHT_PROGBITS; | |
bfae80f2 RE |
18376 | } |
18377 | ||
c19d1205 ZW |
18378 | text_name = segment_name (text_seg); |
18379 | if (streq (text_name, ".text")) | |
18380 | text_name = ""; | |
18381 | ||
18382 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
18383 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 18384 | { |
c19d1205 ZW |
18385 | prefix = prefix_once; |
18386 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
18387 | } |
18388 | ||
c19d1205 ZW |
18389 | prefix_len = strlen (prefix); |
18390 | text_len = strlen (text_name); | |
18391 | sec_name_len = prefix_len + text_len; | |
18392 | sec_name = xmalloc (sec_name_len + 1); | |
18393 | memcpy (sec_name, prefix, prefix_len); | |
18394 | memcpy (sec_name + prefix_len, text_name, text_len); | |
18395 | sec_name[prefix_len + text_len] = '\0'; | |
bfae80f2 | 18396 | |
c19d1205 ZW |
18397 | flags = SHF_ALLOC; |
18398 | linkonce = 0; | |
18399 | group_name = 0; | |
bfae80f2 | 18400 | |
c19d1205 ZW |
18401 | /* Handle COMDAT group. */ |
18402 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 18403 | { |
c19d1205 ZW |
18404 | group_name = elf_group_name (text_seg); |
18405 | if (group_name == NULL) | |
18406 | { | |
bd3ba5d1 | 18407 | as_bad (_("Group section `%s' has no group signature"), |
c19d1205 ZW |
18408 | segment_name (text_seg)); |
18409 | ignore_rest_of_line (); | |
18410 | return; | |
18411 | } | |
18412 | flags |= SHF_GROUP; | |
18413 | linkonce = 1; | |
bfae80f2 RE |
18414 | } |
18415 | ||
c19d1205 | 18416 | obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); |
bfae80f2 | 18417 | |
5f4273c7 | 18418 | /* Set the section link for index tables. */ |
c19d1205 ZW |
18419 | if (idx) |
18420 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
18421 | } |
18422 | ||
bfae80f2 | 18423 | |
c19d1205 ZW |
18424 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
18425 | personality routine data. Returns zero, or the index table value for | |
18426 | and inline entry. */ | |
18427 | ||
18428 | static valueT | |
18429 | create_unwind_entry (int have_data) | |
bfae80f2 | 18430 | { |
c19d1205 ZW |
18431 | int size; |
18432 | addressT where; | |
18433 | char *ptr; | |
18434 | /* The current word of data. */ | |
18435 | valueT data; | |
18436 | /* The number of bytes left in this word. */ | |
18437 | int n; | |
bfae80f2 | 18438 | |
c19d1205 | 18439 | finish_unwind_opcodes (); |
bfae80f2 | 18440 | |
c19d1205 ZW |
18441 | /* Remember the current text section. */ |
18442 | unwind.saved_seg = now_seg; | |
18443 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 18444 | |
c19d1205 | 18445 | start_unwind_section (now_seg, 0); |
bfae80f2 | 18446 | |
c19d1205 | 18447 | if (unwind.personality_routine == NULL) |
bfae80f2 | 18448 | { |
c19d1205 ZW |
18449 | if (unwind.personality_index == -2) |
18450 | { | |
18451 | if (have_data) | |
5f4273c7 | 18452 | as_bad (_("handlerdata in cantunwind frame")); |
c19d1205 ZW |
18453 | return 1; /* EXIDX_CANTUNWIND. */ |
18454 | } | |
bfae80f2 | 18455 | |
c19d1205 ZW |
18456 | /* Use a default personality routine if none is specified. */ |
18457 | if (unwind.personality_index == -1) | |
18458 | { | |
18459 | if (unwind.opcode_count > 3) | |
18460 | unwind.personality_index = 1; | |
18461 | else | |
18462 | unwind.personality_index = 0; | |
18463 | } | |
bfae80f2 | 18464 | |
c19d1205 ZW |
18465 | /* Space for the personality routine entry. */ |
18466 | if (unwind.personality_index == 0) | |
18467 | { | |
18468 | if (unwind.opcode_count > 3) | |
18469 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 18470 | |
c19d1205 ZW |
18471 | if (!have_data) |
18472 | { | |
18473 | /* All the data is inline in the index table. */ | |
18474 | data = 0x80; | |
18475 | n = 3; | |
18476 | while (unwind.opcode_count > 0) | |
18477 | { | |
18478 | unwind.opcode_count--; | |
18479 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
18480 | n--; | |
18481 | } | |
bfae80f2 | 18482 | |
c19d1205 ZW |
18483 | /* Pad with "finish" opcodes. */ |
18484 | while (n--) | |
18485 | data = (data << 8) | 0xb0; | |
bfae80f2 | 18486 | |
c19d1205 ZW |
18487 | return data; |
18488 | } | |
18489 | size = 0; | |
18490 | } | |
18491 | else | |
18492 | /* We get two opcodes "free" in the first word. */ | |
18493 | size = unwind.opcode_count - 2; | |
18494 | } | |
18495 | else | |
18496 | /* An extra byte is required for the opcode count. */ | |
18497 | size = unwind.opcode_count + 1; | |
bfae80f2 | 18498 | |
c19d1205 ZW |
18499 | size = (size + 3) >> 2; |
18500 | if (size > 0xff) | |
18501 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 18502 | |
c19d1205 ZW |
18503 | frag_align (2, 0, 0); |
18504 | record_alignment (now_seg, 2); | |
18505 | unwind.table_entry = expr_build_dot (); | |
18506 | ||
18507 | /* Allocate the table entry. */ | |
18508 | ptr = frag_more ((size << 2) + 4); | |
18509 | where = frag_now_fix () - ((size << 2) + 4); | |
bfae80f2 | 18510 | |
c19d1205 | 18511 | switch (unwind.personality_index) |
bfae80f2 | 18512 | { |
c19d1205 ZW |
18513 | case -1: |
18514 | /* ??? Should this be a PLT generating relocation? */ | |
18515 | /* Custom personality routine. */ | |
18516 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
18517 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 18518 | |
c19d1205 ZW |
18519 | where += 4; |
18520 | ptr += 4; | |
bfae80f2 | 18521 | |
c19d1205 ZW |
18522 | /* Set the first byte to the number of additional words. */ |
18523 | data = size - 1; | |
18524 | n = 3; | |
18525 | break; | |
bfae80f2 | 18526 | |
c19d1205 ZW |
18527 | /* ABI defined personality routines. */ |
18528 | case 0: | |
18529 | /* Three opcodes bytes are packed into the first word. */ | |
18530 | data = 0x80; | |
18531 | n = 3; | |
18532 | break; | |
bfae80f2 | 18533 | |
c19d1205 ZW |
18534 | case 1: |
18535 | case 2: | |
18536 | /* The size and first two opcode bytes go in the first word. */ | |
18537 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
18538 | n = 2; | |
18539 | break; | |
bfae80f2 | 18540 | |
c19d1205 ZW |
18541 | default: |
18542 | /* Should never happen. */ | |
18543 | abort (); | |
18544 | } | |
bfae80f2 | 18545 | |
c19d1205 ZW |
18546 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
18547 | time. */ | |
18548 | while (unwind.opcode_count > 0) | |
18549 | { | |
18550 | if (n == 0) | |
18551 | { | |
18552 | md_number_to_chars (ptr, data, 4); | |
18553 | ptr += 4; | |
18554 | n = 4; | |
18555 | data = 0; | |
18556 | } | |
18557 | unwind.opcode_count--; | |
18558 | n--; | |
18559 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
18560 | } | |
18561 | ||
18562 | /* Finish off the last word. */ | |
18563 | if (n < 4) | |
18564 | { | |
18565 | /* Pad with "finish" opcodes. */ | |
18566 | while (n--) | |
18567 | data = (data << 8) | 0xb0; | |
18568 | ||
18569 | md_number_to_chars (ptr, data, 4); | |
18570 | } | |
18571 | ||
18572 | if (!have_data) | |
18573 | { | |
18574 | /* Add an empty descriptor if there is no user-specified data. */ | |
18575 | ptr = frag_more (4); | |
18576 | md_number_to_chars (ptr, 0, 4); | |
18577 | } | |
18578 | ||
18579 | return 0; | |
bfae80f2 RE |
18580 | } |
18581 | ||
f0927246 NC |
18582 | |
18583 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
18584 | ||
18585 | void | |
18586 | tc_arm_frame_initial_instructions (void) | |
18587 | { | |
18588 | cfi_add_CFA_def_cfa (REG_SP, 0); | |
18589 | } | |
18590 | #endif /* OBJ_ELF */ | |
18591 | ||
c19d1205 ZW |
18592 | /* Convert REGNAME to a DWARF-2 register number. */ |
18593 | ||
18594 | int | |
1df69f4f | 18595 | tc_arm_regname_to_dw2regnum (char *regname) |
bfae80f2 | 18596 | { |
1df69f4f | 18597 | int reg = arm_reg_parse (®name, REG_TYPE_RN); |
c19d1205 ZW |
18598 | |
18599 | if (reg == FAIL) | |
18600 | return -1; | |
18601 | ||
18602 | return reg; | |
bfae80f2 RE |
18603 | } |
18604 | ||
f0927246 | 18605 | #ifdef TE_PE |
c19d1205 | 18606 | void |
f0927246 | 18607 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
bfae80f2 | 18608 | { |
f0927246 | 18609 | expressionS expr; |
bfae80f2 | 18610 | |
f0927246 NC |
18611 | expr.X_op = O_secrel; |
18612 | expr.X_add_symbol = symbol; | |
18613 | expr.X_add_number = 0; | |
18614 | emit_expr (&expr, size); | |
18615 | } | |
18616 | #endif | |
bfae80f2 | 18617 | |
c19d1205 | 18618 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 18619 | |
2fc8bdac ZW |
18620 | /* Return the address within the segment that a PC-relative fixup is |
18621 | relative to. For ARM, PC-relative fixups applied to instructions | |
18622 | are generally relative to the location of the fixup plus 8 bytes. | |
18623 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
18624 | require special handling. */ | |
bfae80f2 | 18625 | |
c19d1205 | 18626 | long |
2fc8bdac | 18627 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 18628 | { |
2fc8bdac ZW |
18629 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
18630 | ||
18631 | /* If this is pc-relative and we are going to emit a relocation | |
18632 | then we just want to put out any pipeline compensation that the linker | |
53baae48 NC |
18633 | will need. Otherwise we want to use the calculated base. |
18634 | For WinCE we skip the bias for externals as well, since this | |
18635 | is how the MS ARM-CE assembler behaves and we want to be compatible. */ | |
5f4273c7 | 18636 | if (fixP->fx_pcrel |
2fc8bdac | 18637 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) |
53baae48 NC |
18638 | || (arm_force_relocation (fixP) |
18639 | #ifdef TE_WINCE | |
18640 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
18641 | #endif | |
18642 | ))) | |
2fc8bdac | 18643 | base = 0; |
bfae80f2 | 18644 | |
267bf995 | 18645 | |
c19d1205 | 18646 | switch (fixP->fx_r_type) |
bfae80f2 | 18647 | { |
2fc8bdac ZW |
18648 | /* PC relative addressing on the Thumb is slightly odd as the |
18649 | bottom two bits of the PC are forced to zero for the | |
18650 | calculation. This happens *after* application of the | |
18651 | pipeline offset. However, Thumb adrl already adjusts for | |
18652 | this, so we need not do it again. */ | |
c19d1205 | 18653 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 18654 | return base & ~3; |
c19d1205 ZW |
18655 | |
18656 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
18657 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 18658 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 18659 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 18660 | return (base + 4) & ~3; |
c19d1205 | 18661 | |
2fc8bdac ZW |
18662 | /* Thumb branches are simply offset by +4. */ |
18663 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
18664 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
18665 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
18666 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
2fc8bdac | 18667 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac | 18668 | return base + 4; |
bfae80f2 | 18669 | |
267bf995 RR |
18670 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
18671 | if (fixP->fx_addsy | |
18672 | && ARM_IS_FUNC (fixP->fx_addsy) | |
18673 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
18674 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
18675 | return base + 4; | |
18676 | ||
00adf2d4 JB |
18677 | /* BLX is like branches above, but forces the low two bits of PC to |
18678 | zero. */ | |
267bf995 RR |
18679 | case BFD_RELOC_THUMB_PCREL_BLX: |
18680 | if (fixP->fx_addsy | |
18681 | && THUMB_IS_FUNC (fixP->fx_addsy) | |
18682 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
18683 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
00adf2d4 JB |
18684 | return (base + 4) & ~3; |
18685 | ||
2fc8bdac ZW |
18686 | /* ARM mode branches are offset by +8. However, the Windows CE |
18687 | loader expects the relocation not to take this into account. */ | |
267bf995 RR |
18688 | case BFD_RELOC_ARM_PCREL_BLX: |
18689 | if (fixP->fx_addsy | |
18690 | && ARM_IS_FUNC (fixP->fx_addsy) | |
18691 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
18692 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
18693 | return base + 8; | |
18694 | ||
18695 | case BFD_RELOC_ARM_PCREL_CALL: | |
18696 | if (fixP->fx_addsy | |
18697 | && THUMB_IS_FUNC (fixP->fx_addsy) | |
18698 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
18699 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
18700 | return base + 8; | |
18701 | ||
2fc8bdac | 18702 | case BFD_RELOC_ARM_PCREL_BRANCH: |
39b41c9c | 18703 | case BFD_RELOC_ARM_PCREL_JUMP: |
2fc8bdac | 18704 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 18705 | #ifdef TE_WINCE |
5f4273c7 | 18706 | /* When handling fixups immediately, because we have already |
53baae48 NC |
18707 | discovered the value of a symbol, or the address of the frag involved |
18708 | we must account for the offset by +8, as the OS loader will never see the reloc. | |
18709 | see fixup_segment() in write.c | |
18710 | The S_IS_EXTERNAL test handles the case of global symbols. | |
18711 | Those need the calculated base, not just the pipe compensation the linker will need. */ | |
18712 | if (fixP->fx_pcrel | |
18713 | && fixP->fx_addsy != NULL | |
18714 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
18715 | && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) | |
18716 | return base + 8; | |
2fc8bdac | 18717 | return base; |
c19d1205 | 18718 | #else |
2fc8bdac | 18719 | return base + 8; |
c19d1205 | 18720 | #endif |
2fc8bdac | 18721 | |
267bf995 | 18722 | |
2fc8bdac ZW |
18723 | /* ARM mode loads relative to PC are also offset by +8. Unlike |
18724 | branches, the Windows CE loader *does* expect the relocation | |
18725 | to take this into account. */ | |
18726 | case BFD_RELOC_ARM_OFFSET_IMM: | |
18727 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
18728 | case BFD_RELOC_ARM_HWLITERAL: | |
18729 | case BFD_RELOC_ARM_LITERAL: | |
18730 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
18731 | return base + 8; | |
18732 | ||
18733 | ||
18734 | /* Other PC-relative relocations are un-offset. */ | |
18735 | default: | |
18736 | return base; | |
18737 | } | |
bfae80f2 RE |
18738 | } |
18739 | ||
c19d1205 ZW |
18740 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. |
18741 | Otherwise we have no need to default values of symbols. */ | |
18742 | ||
18743 | symbolS * | |
18744 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
bfae80f2 | 18745 | { |
c19d1205 ZW |
18746 | #ifdef OBJ_ELF |
18747 | if (name[0] == '_' && name[1] == 'G' | |
18748 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
18749 | { | |
18750 | if (!GOT_symbol) | |
18751 | { | |
18752 | if (symbol_find (name)) | |
bd3ba5d1 | 18753 | as_bad (_("GOT already in the symbol table")); |
bfae80f2 | 18754 | |
c19d1205 ZW |
18755 | GOT_symbol = symbol_new (name, undefined_section, |
18756 | (valueT) 0, & zero_address_frag); | |
18757 | } | |
bfae80f2 | 18758 | |
c19d1205 | 18759 | return GOT_symbol; |
bfae80f2 | 18760 | } |
c19d1205 | 18761 | #endif |
bfae80f2 | 18762 | |
c19d1205 | 18763 | return 0; |
bfae80f2 RE |
18764 | } |
18765 | ||
55cf6793 | 18766 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
18767 | computed as two separate immediate values, added together. We |
18768 | already know that this value cannot be computed by just one ARM | |
18769 | instruction. */ | |
18770 | ||
18771 | static unsigned int | |
18772 | validate_immediate_twopart (unsigned int val, | |
18773 | unsigned int * highpart) | |
bfae80f2 | 18774 | { |
c19d1205 ZW |
18775 | unsigned int a; |
18776 | unsigned int i; | |
bfae80f2 | 18777 | |
c19d1205 ZW |
18778 | for (i = 0; i < 32; i += 2) |
18779 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
18780 | { | |
18781 | if (a & 0xff00) | |
18782 | { | |
18783 | if (a & ~ 0xffff) | |
18784 | continue; | |
18785 | * highpart = (a >> 8) | ((i + 24) << 7); | |
18786 | } | |
18787 | else if (a & 0xff0000) | |
18788 | { | |
18789 | if (a & 0xff000000) | |
18790 | continue; | |
18791 | * highpart = (a >> 16) | ((i + 16) << 7); | |
18792 | } | |
18793 | else | |
18794 | { | |
18795 | assert (a & 0xff000000); | |
18796 | * highpart = (a >> 24) | ((i + 8) << 7); | |
18797 | } | |
bfae80f2 | 18798 | |
c19d1205 ZW |
18799 | return (a & 0xff) | (i << 7); |
18800 | } | |
bfae80f2 | 18801 | |
c19d1205 | 18802 | return FAIL; |
bfae80f2 RE |
18803 | } |
18804 | ||
c19d1205 ZW |
18805 | static int |
18806 | validate_offset_imm (unsigned int val, int hwse) | |
18807 | { | |
18808 | if ((hwse && val > 255) || val > 4095) | |
18809 | return FAIL; | |
18810 | return val; | |
18811 | } | |
bfae80f2 | 18812 | |
55cf6793 | 18813 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
18814 | negative immediate constant by altering the instruction. A bit of |
18815 | a hack really. | |
18816 | MOV <-> MVN | |
18817 | AND <-> BIC | |
18818 | ADC <-> SBC | |
18819 | by inverting the second operand, and | |
18820 | ADD <-> SUB | |
18821 | CMP <-> CMN | |
18822 | by negating the second operand. */ | |
bfae80f2 | 18823 | |
c19d1205 ZW |
18824 | static int |
18825 | negate_data_op (unsigned long * instruction, | |
18826 | unsigned long value) | |
bfae80f2 | 18827 | { |
c19d1205 ZW |
18828 | int op, new_inst; |
18829 | unsigned long negated, inverted; | |
bfae80f2 | 18830 | |
c19d1205 ZW |
18831 | negated = encode_arm_immediate (-value); |
18832 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 18833 | |
c19d1205 ZW |
18834 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
18835 | switch (op) | |
bfae80f2 | 18836 | { |
c19d1205 ZW |
18837 | /* First negates. */ |
18838 | case OPCODE_SUB: /* ADD <-> SUB */ | |
18839 | new_inst = OPCODE_ADD; | |
18840 | value = negated; | |
18841 | break; | |
bfae80f2 | 18842 | |
c19d1205 ZW |
18843 | case OPCODE_ADD: |
18844 | new_inst = OPCODE_SUB; | |
18845 | value = negated; | |
18846 | break; | |
bfae80f2 | 18847 | |
c19d1205 ZW |
18848 | case OPCODE_CMP: /* CMP <-> CMN */ |
18849 | new_inst = OPCODE_CMN; | |
18850 | value = negated; | |
18851 | break; | |
bfae80f2 | 18852 | |
c19d1205 ZW |
18853 | case OPCODE_CMN: |
18854 | new_inst = OPCODE_CMP; | |
18855 | value = negated; | |
18856 | break; | |
bfae80f2 | 18857 | |
c19d1205 ZW |
18858 | /* Now Inverted ops. */ |
18859 | case OPCODE_MOV: /* MOV <-> MVN */ | |
18860 | new_inst = OPCODE_MVN; | |
18861 | value = inverted; | |
18862 | break; | |
bfae80f2 | 18863 | |
c19d1205 ZW |
18864 | case OPCODE_MVN: |
18865 | new_inst = OPCODE_MOV; | |
18866 | value = inverted; | |
18867 | break; | |
bfae80f2 | 18868 | |
c19d1205 ZW |
18869 | case OPCODE_AND: /* AND <-> BIC */ |
18870 | new_inst = OPCODE_BIC; | |
18871 | value = inverted; | |
18872 | break; | |
bfae80f2 | 18873 | |
c19d1205 ZW |
18874 | case OPCODE_BIC: |
18875 | new_inst = OPCODE_AND; | |
18876 | value = inverted; | |
18877 | break; | |
bfae80f2 | 18878 | |
c19d1205 ZW |
18879 | case OPCODE_ADC: /* ADC <-> SBC */ |
18880 | new_inst = OPCODE_SBC; | |
18881 | value = inverted; | |
18882 | break; | |
bfae80f2 | 18883 | |
c19d1205 ZW |
18884 | case OPCODE_SBC: |
18885 | new_inst = OPCODE_ADC; | |
18886 | value = inverted; | |
18887 | break; | |
bfae80f2 | 18888 | |
c19d1205 ZW |
18889 | /* We cannot do anything. */ |
18890 | default: | |
18891 | return FAIL; | |
b99bd4ef NC |
18892 | } |
18893 | ||
c19d1205 ZW |
18894 | if (value == (unsigned) FAIL) |
18895 | return FAIL; | |
18896 | ||
18897 | *instruction &= OPCODE_MASK; | |
18898 | *instruction |= new_inst << DATA_OP_SHIFT; | |
18899 | return value; | |
b99bd4ef NC |
18900 | } |
18901 | ||
ef8d22e6 PB |
18902 | /* Like negate_data_op, but for Thumb-2. */ |
18903 | ||
18904 | static unsigned int | |
16dd5e42 | 18905 | thumb32_negate_data_op (offsetT *instruction, unsigned int value) |
ef8d22e6 PB |
18906 | { |
18907 | int op, new_inst; | |
18908 | int rd; | |
16dd5e42 | 18909 | unsigned int negated, inverted; |
ef8d22e6 PB |
18910 | |
18911 | negated = encode_thumb32_immediate (-value); | |
18912 | inverted = encode_thumb32_immediate (~value); | |
18913 | ||
18914 | rd = (*instruction >> 8) & 0xf; | |
18915 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; | |
18916 | switch (op) | |
18917 | { | |
18918 | /* ADD <-> SUB. Includes CMP <-> CMN. */ | |
18919 | case T2_OPCODE_SUB: | |
18920 | new_inst = T2_OPCODE_ADD; | |
18921 | value = negated; | |
18922 | break; | |
18923 | ||
18924 | case T2_OPCODE_ADD: | |
18925 | new_inst = T2_OPCODE_SUB; | |
18926 | value = negated; | |
18927 | break; | |
18928 | ||
18929 | /* ORR <-> ORN. Includes MOV <-> MVN. */ | |
18930 | case T2_OPCODE_ORR: | |
18931 | new_inst = T2_OPCODE_ORN; | |
18932 | value = inverted; | |
18933 | break; | |
18934 | ||
18935 | case T2_OPCODE_ORN: | |
18936 | new_inst = T2_OPCODE_ORR; | |
18937 | value = inverted; | |
18938 | break; | |
18939 | ||
18940 | /* AND <-> BIC. TST has no inverted equivalent. */ | |
18941 | case T2_OPCODE_AND: | |
18942 | new_inst = T2_OPCODE_BIC; | |
18943 | if (rd == 15) | |
18944 | value = FAIL; | |
18945 | else | |
18946 | value = inverted; | |
18947 | break; | |
18948 | ||
18949 | case T2_OPCODE_BIC: | |
18950 | new_inst = T2_OPCODE_AND; | |
18951 | value = inverted; | |
18952 | break; | |
18953 | ||
18954 | /* ADC <-> SBC */ | |
18955 | case T2_OPCODE_ADC: | |
18956 | new_inst = T2_OPCODE_SBC; | |
18957 | value = inverted; | |
18958 | break; | |
18959 | ||
18960 | case T2_OPCODE_SBC: | |
18961 | new_inst = T2_OPCODE_ADC; | |
18962 | value = inverted; | |
18963 | break; | |
18964 | ||
18965 | /* We cannot do anything. */ | |
18966 | default: | |
18967 | return FAIL; | |
18968 | } | |
18969 | ||
16dd5e42 | 18970 | if (value == (unsigned int)FAIL) |
ef8d22e6 PB |
18971 | return FAIL; |
18972 | ||
18973 | *instruction &= T2_OPCODE_MASK; | |
18974 | *instruction |= new_inst << T2_DATA_OP_SHIFT; | |
18975 | return value; | |
18976 | } | |
18977 | ||
8f06b2d8 PB |
18978 | /* Read a 32-bit thumb instruction from buf. */ |
18979 | static unsigned long | |
18980 | get_thumb32_insn (char * buf) | |
18981 | { | |
18982 | unsigned long insn; | |
18983 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
18984 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
18985 | ||
18986 | return insn; | |
18987 | } | |
18988 | ||
a8bc6c78 PB |
18989 | |
18990 | /* We usually want to set the low bit on the address of thumb function | |
18991 | symbols. In particular .word foo - . should have the low bit set. | |
18992 | Generic code tries to fold the difference of two symbols to | |
18993 | a constant. Prevent this and force a relocation when the first symbols | |
18994 | is a thumb function. */ | |
18995 | int | |
18996 | arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) | |
18997 | { | |
18998 | if (op == O_subtract | |
18999 | && l->X_op == O_symbol | |
19000 | && r->X_op == O_symbol | |
19001 | && THUMB_IS_FUNC (l->X_add_symbol)) | |
19002 | { | |
19003 | l->X_op = O_subtract; | |
19004 | l->X_op_symbol = r->X_add_symbol; | |
19005 | l->X_add_number -= r->X_add_number; | |
19006 | return 1; | |
19007 | } | |
19008 | /* Process as normal. */ | |
19009 | return 0; | |
19010 | } | |
19011 | ||
c19d1205 | 19012 | void |
55cf6793 | 19013 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
19014 | valueT * valP, |
19015 | segT seg) | |
19016 | { | |
19017 | offsetT value = * valP; | |
19018 | offsetT newval; | |
19019 | unsigned int newimm; | |
19020 | unsigned long temp; | |
19021 | int sign; | |
19022 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 19023 | |
c19d1205 | 19024 | assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 19025 | |
c19d1205 | 19026 | /* Note whether this will delete the relocation. */ |
4962c51a | 19027 | |
c19d1205 ZW |
19028 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) |
19029 | fixP->fx_done = 1; | |
b99bd4ef | 19030 | |
adbaf948 | 19031 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
5f4273c7 | 19032 | consistency with the behaviour on 32-bit hosts. Remember value |
adbaf948 ZW |
19033 | for emit_reloc. */ |
19034 | value &= 0xffffffff; | |
19035 | value ^= 0x80000000; | |
5f4273c7 | 19036 | value -= 0x80000000; |
adbaf948 ZW |
19037 | |
19038 | *valP = value; | |
c19d1205 | 19039 | fixP->fx_addnumber = value; |
b99bd4ef | 19040 | |
adbaf948 ZW |
19041 | /* Same treatment for fixP->fx_offset. */ |
19042 | fixP->fx_offset &= 0xffffffff; | |
19043 | fixP->fx_offset ^= 0x80000000; | |
19044 | fixP->fx_offset -= 0x80000000; | |
19045 | ||
c19d1205 | 19046 | switch (fixP->fx_r_type) |
b99bd4ef | 19047 | { |
c19d1205 ZW |
19048 | case BFD_RELOC_NONE: |
19049 | /* This will need to go in the object file. */ | |
19050 | fixP->fx_done = 0; | |
19051 | break; | |
b99bd4ef | 19052 | |
c19d1205 ZW |
19053 | case BFD_RELOC_ARM_IMMEDIATE: |
19054 | /* We claim that this fixup has been processed here, | |
19055 | even if in fact we generate an error because we do | |
19056 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
19057 | fixP->fx_done = 1; | |
b99bd4ef | 19058 | |
c19d1205 ZW |
19059 | if (fixP->fx_addsy |
19060 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
b99bd4ef | 19061 | { |
c19d1205 ZW |
19062 | as_bad_where (fixP->fx_file, fixP->fx_line, |
19063 | _("undefined symbol %s used as an immediate value"), | |
19064 | S_GET_NAME (fixP->fx_addsy)); | |
19065 | break; | |
b99bd4ef NC |
19066 | } |
19067 | ||
42e5fcbf AS |
19068 | if (fixP->fx_addsy |
19069 | && S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
19070 | { | |
19071 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19072 | _("symbol %s is in a different section"), | |
19073 | S_GET_NAME (fixP->fx_addsy)); | |
19074 | break; | |
19075 | } | |
19076 | ||
c19d1205 ZW |
19077 | newimm = encode_arm_immediate (value); |
19078 | temp = md_chars_to_number (buf, INSN_SIZE); | |
19079 | ||
19080 | /* If the instruction will fail, see if we can fix things up by | |
19081 | changing the opcode. */ | |
19082 | if (newimm == (unsigned int) FAIL | |
19083 | && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) | |
b99bd4ef | 19084 | { |
c19d1205 ZW |
19085 | as_bad_where (fixP->fx_file, fixP->fx_line, |
19086 | _("invalid constant (%lx) after fixup"), | |
19087 | (unsigned long) value); | |
19088 | break; | |
b99bd4ef | 19089 | } |
b99bd4ef | 19090 | |
c19d1205 ZW |
19091 | newimm |= (temp & 0xfffff000); |
19092 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
19093 | break; | |
b99bd4ef | 19094 | |
c19d1205 ZW |
19095 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
19096 | { | |
19097 | unsigned int highpart = 0; | |
19098 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 19099 | |
42e5fcbf AS |
19100 | if (fixP->fx_addsy |
19101 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
19102 | { | |
19103 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19104 | _("undefined symbol %s used as an immediate value"), | |
19105 | S_GET_NAME (fixP->fx_addsy)); | |
19106 | break; | |
19107 | } | |
19108 | ||
19109 | if (fixP->fx_addsy | |
19110 | && S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
19111 | { | |
19112 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19113 | _("symbol %s is in a different section"), | |
19114 | S_GET_NAME (fixP->fx_addsy)); | |
19115 | break; | |
19116 | } | |
19117 | ||
c19d1205 ZW |
19118 | newimm = encode_arm_immediate (value); |
19119 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 19120 | |
c19d1205 ZW |
19121 | /* If the instruction will fail, see if we can fix things up by |
19122 | changing the opcode. */ | |
19123 | if (newimm == (unsigned int) FAIL | |
19124 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
19125 | { | |
19126 | /* No ? OK - try using two ADD instructions to generate | |
19127 | the value. */ | |
19128 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 19129 | |
c19d1205 ZW |
19130 | /* Yes - then make sure that the second instruction is |
19131 | also an add. */ | |
19132 | if (newimm != (unsigned int) FAIL) | |
19133 | newinsn = temp; | |
19134 | /* Still No ? Try using a negated value. */ | |
19135 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
19136 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
19137 | /* Otherwise - give up. */ | |
19138 | else | |
19139 | { | |
19140 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19141 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
19142 | (long) value); | |
19143 | break; | |
19144 | } | |
b99bd4ef | 19145 | |
c19d1205 ZW |
19146 | /* Replace the first operand in the 2nd instruction (which |
19147 | is the PC) with the destination register. We have | |
19148 | already added in the PC in the first instruction and we | |
19149 | do not want to do it again. */ | |
19150 | newinsn &= ~ 0xf0000; | |
19151 | newinsn |= ((newinsn & 0x0f000) << 4); | |
19152 | } | |
b99bd4ef | 19153 | |
c19d1205 ZW |
19154 | newimm |= (temp & 0xfffff000); |
19155 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 19156 | |
c19d1205 ZW |
19157 | highpart |= (newinsn & 0xfffff000); |
19158 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
19159 | } | |
19160 | break; | |
b99bd4ef | 19161 | |
c19d1205 | 19162 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
19163 | if (!fixP->fx_done && seg->use_rela_p) |
19164 | value = 0; | |
19165 | ||
c19d1205 ZW |
19166 | case BFD_RELOC_ARM_LITERAL: |
19167 | sign = value >= 0; | |
b99bd4ef | 19168 | |
c19d1205 ZW |
19169 | if (value < 0) |
19170 | value = - value; | |
b99bd4ef | 19171 | |
c19d1205 | 19172 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 19173 | { |
c19d1205 ZW |
19174 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
19175 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19176 | _("invalid literal constant: pool needs to be closer")); | |
19177 | else | |
19178 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19179 | _("bad immediate value for offset (%ld)"), | |
19180 | (long) value); | |
19181 | break; | |
f03698e6 RE |
19182 | } |
19183 | ||
c19d1205 ZW |
19184 | newval = md_chars_to_number (buf, INSN_SIZE); |
19185 | newval &= 0xff7ff000; | |
19186 | newval |= value | (sign ? INDEX_UP : 0); | |
19187 | md_number_to_chars (buf, newval, INSN_SIZE); | |
19188 | break; | |
b99bd4ef | 19189 | |
c19d1205 ZW |
19190 | case BFD_RELOC_ARM_OFFSET_IMM8: |
19191 | case BFD_RELOC_ARM_HWLITERAL: | |
19192 | sign = value >= 0; | |
b99bd4ef | 19193 | |
c19d1205 ZW |
19194 | if (value < 0) |
19195 | value = - value; | |
b99bd4ef | 19196 | |
c19d1205 | 19197 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 19198 | { |
c19d1205 ZW |
19199 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
19200 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19201 | _("invalid literal constant: pool needs to be closer")); | |
19202 | else | |
f9d4405b | 19203 | as_bad (_("bad immediate value for 8-bit offset (%ld)"), |
c19d1205 ZW |
19204 | (long) value); |
19205 | break; | |
b99bd4ef NC |
19206 | } |
19207 | ||
c19d1205 ZW |
19208 | newval = md_chars_to_number (buf, INSN_SIZE); |
19209 | newval &= 0xff7ff0f0; | |
19210 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
19211 | md_number_to_chars (buf, newval, INSN_SIZE); | |
19212 | break; | |
b99bd4ef | 19213 | |
c19d1205 ZW |
19214 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
19215 | if (value < 0 || value > 1020 || value % 4 != 0) | |
19216 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19217 | _("bad immediate value for offset (%ld)"), (long) value); | |
19218 | value /= 4; | |
b99bd4ef | 19219 | |
c19d1205 | 19220 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
19221 | newval |= value; |
19222 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
19223 | break; | |
b99bd4ef | 19224 | |
c19d1205 ZW |
19225 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
19226 | /* This is a complicated relocation used for all varieties of Thumb32 | |
19227 | load/store instruction with immediate offset: | |
19228 | ||
19229 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
19230 | *4, optional writeback(W) | |
19231 | (doubleword load/store) | |
19232 | ||
19233 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
19234 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
19235 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
19236 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
19237 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
19238 | ||
19239 | Uppercase letters indicate bits that are already encoded at | |
19240 | this point. Lowercase letters are our problem. For the | |
19241 | second block of instructions, the secondary opcode nybble | |
19242 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
19243 | a PC-relative operation. */ | |
19244 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
19245 | newval <<= 16; | |
19246 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 19247 | |
c19d1205 | 19248 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 19249 | { |
c19d1205 ZW |
19250 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
19251 | if (value >= 0) | |
19252 | newval |= (1 << 23); | |
19253 | else | |
19254 | value = -value; | |
19255 | if (value % 4 != 0) | |
19256 | { | |
19257 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19258 | _("offset not a multiple of 4")); | |
19259 | break; | |
19260 | } | |
19261 | value /= 4; | |
216d22bc | 19262 | if (value > 0xff) |
c19d1205 ZW |
19263 | { |
19264 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19265 | _("offset out of range")); | |
19266 | break; | |
19267 | } | |
19268 | newval &= ~0xff; | |
b99bd4ef | 19269 | } |
c19d1205 | 19270 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 19271 | { |
c19d1205 ZW |
19272 | /* PC-relative, 12-bit offset. */ |
19273 | if (value >= 0) | |
19274 | newval |= (1 << 23); | |
19275 | else | |
19276 | value = -value; | |
216d22bc | 19277 | if (value > 0xfff) |
c19d1205 ZW |
19278 | { |
19279 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19280 | _("offset out of range")); | |
19281 | break; | |
19282 | } | |
19283 | newval &= ~0xfff; | |
b99bd4ef | 19284 | } |
c19d1205 | 19285 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 19286 | { |
c19d1205 ZW |
19287 | /* Writeback: 8-bit, +/- offset. */ |
19288 | if (value >= 0) | |
19289 | newval |= (1 << 9); | |
19290 | else | |
19291 | value = -value; | |
216d22bc | 19292 | if (value > 0xff) |
c19d1205 ZW |
19293 | { |
19294 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19295 | _("offset out of range")); | |
19296 | break; | |
19297 | } | |
19298 | newval &= ~0xff; | |
b99bd4ef | 19299 | } |
c19d1205 | 19300 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 19301 | { |
c19d1205 | 19302 | /* T-instruction: positive 8-bit offset. */ |
216d22bc | 19303 | if (value < 0 || value > 0xff) |
b99bd4ef | 19304 | { |
c19d1205 ZW |
19305 | as_bad_where (fixP->fx_file, fixP->fx_line, |
19306 | _("offset out of range")); | |
19307 | break; | |
b99bd4ef | 19308 | } |
c19d1205 ZW |
19309 | newval &= ~0xff; |
19310 | newval |= value; | |
b99bd4ef NC |
19311 | } |
19312 | else | |
b99bd4ef | 19313 | { |
c19d1205 ZW |
19314 | /* Positive 12-bit or negative 8-bit offset. */ |
19315 | int limit; | |
19316 | if (value >= 0) | |
b99bd4ef | 19317 | { |
c19d1205 ZW |
19318 | newval |= (1 << 23); |
19319 | limit = 0xfff; | |
19320 | } | |
19321 | else | |
19322 | { | |
19323 | value = -value; | |
19324 | limit = 0xff; | |
19325 | } | |
19326 | if (value > limit) | |
19327 | { | |
19328 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19329 | _("offset out of range")); | |
19330 | break; | |
b99bd4ef | 19331 | } |
c19d1205 | 19332 | newval &= ~limit; |
b99bd4ef | 19333 | } |
b99bd4ef | 19334 | |
c19d1205 ZW |
19335 | newval |= value; |
19336 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
19337 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
19338 | break; | |
404ff6b5 | 19339 | |
c19d1205 ZW |
19340 | case BFD_RELOC_ARM_SHIFT_IMM: |
19341 | newval = md_chars_to_number (buf, INSN_SIZE); | |
19342 | if (((unsigned long) value) > 32 | |
19343 | || (value == 32 | |
19344 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
19345 | { | |
19346 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19347 | _("shift expression is too large")); | |
19348 | break; | |
19349 | } | |
404ff6b5 | 19350 | |
c19d1205 ZW |
19351 | if (value == 0) |
19352 | /* Shifts of zero must be done as lsl. */ | |
19353 | newval &= ~0x60; | |
19354 | else if (value == 32) | |
19355 | value = 0; | |
19356 | newval &= 0xfffff07f; | |
19357 | newval |= (value & 0x1f) << 7; | |
19358 | md_number_to_chars (buf, newval, INSN_SIZE); | |
19359 | break; | |
404ff6b5 | 19360 | |
c19d1205 | 19361 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
16805f35 | 19362 | case BFD_RELOC_ARM_T32_ADD_IMM: |
92e90b6e | 19363 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 19364 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
19365 | /* We claim that this fixup has been processed here, |
19366 | even if in fact we generate an error because we do | |
19367 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
19368 | fixP->fx_done = 1; | |
404ff6b5 | 19369 | |
c19d1205 ZW |
19370 | if (fixP->fx_addsy |
19371 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
19372 | { | |
19373 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19374 | _("undefined symbol %s used as an immediate value"), | |
19375 | S_GET_NAME (fixP->fx_addsy)); | |
19376 | break; | |
19377 | } | |
404ff6b5 | 19378 | |
c19d1205 ZW |
19379 | newval = md_chars_to_number (buf, THUMB_SIZE); |
19380 | newval <<= 16; | |
19381 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 19382 | |
16805f35 PB |
19383 | newimm = FAIL; |
19384 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE | |
19385 | || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
ef8d22e6 PB |
19386 | { |
19387 | newimm = encode_thumb32_immediate (value); | |
19388 | if (newimm == (unsigned int) FAIL) | |
19389 | newimm = thumb32_negate_data_op (&newval, value); | |
19390 | } | |
16805f35 PB |
19391 | if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE |
19392 | && newimm == (unsigned int) FAIL) | |
92e90b6e | 19393 | { |
16805f35 PB |
19394 | /* Turn add/sum into addw/subw. */ |
19395 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
19396 | newval = (newval & 0xfeffffff) | 0x02000000; | |
19397 | ||
e9f89963 PB |
19398 | /* 12 bit immediate for addw/subw. */ |
19399 | if (value < 0) | |
19400 | { | |
19401 | value = -value; | |
19402 | newval ^= 0x00a00000; | |
19403 | } | |
92e90b6e PB |
19404 | if (value > 0xfff) |
19405 | newimm = (unsigned int) FAIL; | |
19406 | else | |
19407 | newimm = value; | |
19408 | } | |
cc8a6dd0 | 19409 | |
c19d1205 | 19410 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 19411 | { |
c19d1205 ZW |
19412 | as_bad_where (fixP->fx_file, fixP->fx_line, |
19413 | _("invalid constant (%lx) after fixup"), | |
19414 | (unsigned long) value); | |
19415 | break; | |
3631a3c8 NC |
19416 | } |
19417 | ||
c19d1205 ZW |
19418 | newval |= (newimm & 0x800) << 15; |
19419 | newval |= (newimm & 0x700) << 4; | |
19420 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 19421 | |
c19d1205 ZW |
19422 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
19423 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
19424 | break; | |
a737bd4d | 19425 | |
3eb17e6b | 19426 | case BFD_RELOC_ARM_SMC: |
c19d1205 ZW |
19427 | if (((unsigned long) value) > 0xffff) |
19428 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3eb17e6b | 19429 | _("invalid smc expression")); |
2fc8bdac | 19430 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
19431 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
19432 | md_number_to_chars (buf, newval, INSN_SIZE); | |
19433 | break; | |
a737bd4d | 19434 | |
c19d1205 | 19435 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 19436 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
19437 | { |
19438 | if (((unsigned long) value) > 0xff) | |
19439 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19440 | _("invalid swi expression")); | |
2fc8bdac | 19441 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
19442 | newval |= value; |
19443 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
19444 | } | |
19445 | else | |
19446 | { | |
19447 | if (((unsigned long) value) > 0x00ffffff) | |
19448 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19449 | _("invalid swi expression")); | |
2fc8bdac | 19450 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
19451 | newval |= value; |
19452 | md_number_to_chars (buf, newval, INSN_SIZE); | |
19453 | } | |
19454 | break; | |
a737bd4d | 19455 | |
c19d1205 ZW |
19456 | case BFD_RELOC_ARM_MULTI: |
19457 | if (((unsigned long) value) > 0xffff) | |
19458 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19459 | _("invalid expression in load/store multiple")); | |
19460 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
19461 | md_number_to_chars (buf, newval, INSN_SIZE); | |
19462 | break; | |
a737bd4d | 19463 | |
c19d1205 | 19464 | #ifdef OBJ_ELF |
39b41c9c | 19465 | case BFD_RELOC_ARM_PCREL_CALL: |
267bf995 RR |
19466 | |
19467 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
19468 | && fixP->fx_addsy | |
19469 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
19470 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19471 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
19472 | /* Flip the bl to blx. This is a simple flip | |
19473 | bit here because we generate PCREL_CALL for | |
19474 | unconditional bls. */ | |
19475 | { | |
19476 | newval = md_chars_to_number (buf, INSN_SIZE); | |
19477 | newval = newval | 0x10000000; | |
19478 | md_number_to_chars (buf, newval, INSN_SIZE); | |
19479 | temp = 1; | |
19480 | fixP->fx_done = 1; | |
19481 | } | |
39b41c9c PB |
19482 | else |
19483 | temp = 3; | |
19484 | goto arm_branch_common; | |
19485 | ||
19486 | case BFD_RELOC_ARM_PCREL_JUMP: | |
267bf995 RR |
19487 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
19488 | && fixP->fx_addsy | |
19489 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
19490 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19491 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
19492 | { | |
19493 | /* This would map to a bl<cond>, b<cond>, | |
19494 | b<always> to a Thumb function. We | |
19495 | need to force a relocation for this particular | |
19496 | case. */ | |
19497 | newval = md_chars_to_number (buf, INSN_SIZE); | |
19498 | fixP->fx_done = 0; | |
19499 | } | |
19500 | ||
2fc8bdac | 19501 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 19502 | #endif |
39b41c9c PB |
19503 | case BFD_RELOC_ARM_PCREL_BRANCH: |
19504 | temp = 3; | |
19505 | goto arm_branch_common; | |
a737bd4d | 19506 | |
39b41c9c | 19507 | case BFD_RELOC_ARM_PCREL_BLX: |
267bf995 | 19508 | |
39b41c9c | 19509 | temp = 1; |
267bf995 RR |
19510 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
19511 | && fixP->fx_addsy | |
19512 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
19513 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19514 | && ARM_IS_FUNC (fixP->fx_addsy)) | |
19515 | { | |
19516 | /* Flip the blx to a bl and warn. */ | |
19517 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
19518 | newval = 0xeb000000; | |
19519 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
19520 | _("blx to '%s' an ARM ISA state function changed to bl"), | |
19521 | name); | |
19522 | md_number_to_chars (buf, newval, INSN_SIZE); | |
19523 | temp = 3; | |
19524 | fixP->fx_done = 1; | |
19525 | } | |
19526 | ||
19527 | #ifdef OBJ_ELF | |
19528 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
19529 | fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL; | |
19530 | #endif | |
19531 | ||
39b41c9c | 19532 | arm_branch_common: |
c19d1205 | 19533 | /* We are going to store value (shifted right by two) in the |
39b41c9c PB |
19534 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
19535 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must | |
19536 | also be be clear. */ | |
19537 | if (value & temp) | |
c19d1205 | 19538 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
19539 | _("misaligned branch destination")); |
19540 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
19541 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
19542 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19543 | _("branch out of range")); | |
a737bd4d | 19544 | |
2fc8bdac | 19545 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 19546 | { |
2fc8bdac ZW |
19547 | newval = md_chars_to_number (buf, INSN_SIZE); |
19548 | newval |= (value >> 2) & 0x00ffffff; | |
7ae2971b PB |
19549 | /* Set the H bit on BLX instructions. */ |
19550 | if (temp == 1) | |
19551 | { | |
19552 | if (value & 2) | |
19553 | newval |= 0x01000000; | |
19554 | else | |
19555 | newval &= ~0x01000000; | |
19556 | } | |
2fc8bdac | 19557 | md_number_to_chars (buf, newval, INSN_SIZE); |
c19d1205 | 19558 | } |
c19d1205 | 19559 | break; |
a737bd4d | 19560 | |
25fe350b MS |
19561 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ |
19562 | /* CBZ can only branch forward. */ | |
a737bd4d | 19563 | |
738755b0 MS |
19564 | /* Attempts to use CBZ to branch to the next instruction |
19565 | (which, strictly speaking, are prohibited) will be turned into | |
19566 | no-ops. | |
19567 | ||
19568 | FIXME: It may be better to remove the instruction completely and | |
19569 | perform relaxation. */ | |
19570 | if (value == -2) | |
2fc8bdac ZW |
19571 | { |
19572 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
738755b0 | 19573 | newval = 0xbf00; /* NOP encoding T1 */ |
2fc8bdac ZW |
19574 | md_number_to_chars (buf, newval, THUMB_SIZE); |
19575 | } | |
738755b0 MS |
19576 | else |
19577 | { | |
19578 | if (value & ~0x7e) | |
19579 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19580 | _("branch out of range")); | |
19581 | ||
19582 | if (fixP->fx_done || !seg->use_rela_p) | |
19583 | { | |
19584 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
19585 | newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); | |
19586 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
19587 | } | |
19588 | } | |
c19d1205 | 19589 | break; |
a737bd4d | 19590 | |
c19d1205 | 19591 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac ZW |
19592 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
19593 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19594 | _("branch out of range")); | |
a737bd4d | 19595 | |
2fc8bdac ZW |
19596 | if (fixP->fx_done || !seg->use_rela_p) |
19597 | { | |
19598 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
19599 | newval |= (value & 0x1ff) >> 1; | |
19600 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
19601 | } | |
c19d1205 | 19602 | break; |
a737bd4d | 19603 | |
c19d1205 | 19604 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac ZW |
19605 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
19606 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19607 | _("branch out of range")); | |
a737bd4d | 19608 | |
2fc8bdac ZW |
19609 | if (fixP->fx_done || !seg->use_rela_p) |
19610 | { | |
19611 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
19612 | newval |= (value & 0xfff) >> 1; | |
19613 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
19614 | } | |
c19d1205 | 19615 | break; |
a737bd4d | 19616 | |
c19d1205 | 19617 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
267bf995 RR |
19618 | if (fixP->fx_addsy |
19619 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19620 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
19621 | && S_IS_DEFINED (fixP->fx_addsy) | |
19622 | && ARM_IS_FUNC (fixP->fx_addsy) | |
19623 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19624 | { | |
19625 | /* Force a relocation for a branch 20 bits wide. */ | |
19626 | fixP->fx_done = 0; | |
19627 | } | |
2fc8bdac ZW |
19628 | if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) |
19629 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19630 | _("conditional branch out of range")); | |
404ff6b5 | 19631 | |
2fc8bdac ZW |
19632 | if (fixP->fx_done || !seg->use_rela_p) |
19633 | { | |
19634 | offsetT newval2; | |
19635 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 19636 | |
2fc8bdac ZW |
19637 | S = (value & 0x00100000) >> 20; |
19638 | J2 = (value & 0x00080000) >> 19; | |
19639 | J1 = (value & 0x00040000) >> 18; | |
19640 | hi = (value & 0x0003f000) >> 12; | |
19641 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 19642 | |
2fc8bdac ZW |
19643 | newval = md_chars_to_number (buf, THUMB_SIZE); |
19644 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
19645 | newval |= (S << 10) | hi; | |
19646 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
19647 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
19648 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
19649 | } | |
c19d1205 | 19650 | break; |
6c43fab6 | 19651 | |
c19d1205 | 19652 | case BFD_RELOC_THUMB_PCREL_BLX: |
267bf995 RR |
19653 | |
19654 | /* If there is a blx from a thumb state function to | |
19655 | another thumb function flip this to a bl and warn | |
19656 | about it. */ | |
19657 | ||
19658 | if (fixP->fx_addsy | |
19659 | && S_IS_DEFINED (fixP->fx_addsy) | |
19660 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
19661 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19662 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
19663 | { | |
19664 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
19665 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
19666 | _("blx to Thumb func '%s' from Thumb ISA state changed to bl"), | |
19667 | name); | |
19668 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
19669 | newval = newval | 0x1000; | |
19670 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
19671 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
19672 | fixP->fx_done = 1; | |
19673 | } | |
19674 | ||
19675 | ||
19676 | goto thumb_bl_common; | |
19677 | ||
c19d1205 | 19678 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
267bf995 RR |
19679 | |
19680 | /* A bl from Thumb state ISA to an internal ARM state function | |
19681 | is converted to a blx. */ | |
19682 | if (fixP->fx_addsy | |
19683 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19684 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
19685 | && S_IS_DEFINED (fixP->fx_addsy) | |
19686 | && ARM_IS_FUNC (fixP->fx_addsy) | |
19687 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19688 | { | |
19689 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
19690 | newval = newval & ~0x1000; | |
19691 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
19692 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX; | |
19693 | fixP->fx_done = 1; | |
19694 | } | |
19695 | ||
19696 | thumb_bl_common: | |
19697 | ||
19698 | #ifdef OBJ_ELF | |
19699 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 && | |
19700 | fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) | |
19701 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
19702 | #endif | |
19703 | ||
2fc8bdac ZW |
19704 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
19705 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19706 | _("branch out of range")); | |
404ff6b5 | 19707 | |
2fc8bdac ZW |
19708 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
19709 | /* For a BLX instruction, make sure that the relocation is rounded up | |
19710 | to a word boundary. This follows the semantics of the instruction | |
19711 | which specifies that bit 1 of the target address will come from bit | |
19712 | 1 of the base address. */ | |
19713 | value = (value + 1) & ~ 1; | |
404ff6b5 | 19714 | |
2fc8bdac | 19715 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 19716 | { |
2fc8bdac ZW |
19717 | offsetT newval2; |
19718 | ||
19719 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
19720 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
19721 | newval |= (value & 0x7fffff) >> 12; | |
19722 | newval2 |= (value & 0xfff) >> 1; | |
19723 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
19724 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
c19d1205 | 19725 | } |
c19d1205 | 19726 | break; |
404ff6b5 | 19727 | |
c19d1205 | 19728 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac ZW |
19729 | if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) |
19730 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19731 | _("branch out of range")); | |
6c43fab6 | 19732 | |
2fc8bdac ZW |
19733 | if (fixP->fx_done || !seg->use_rela_p) |
19734 | { | |
19735 | offsetT newval2; | |
19736 | addressT S, I1, I2, lo, hi; | |
6c43fab6 | 19737 | |
2fc8bdac ZW |
19738 | S = (value & 0x01000000) >> 24; |
19739 | I1 = (value & 0x00800000) >> 23; | |
19740 | I2 = (value & 0x00400000) >> 22; | |
19741 | hi = (value & 0x003ff000) >> 12; | |
19742 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 19743 | |
2fc8bdac ZW |
19744 | I1 = !(I1 ^ S); |
19745 | I2 = !(I2 ^ S); | |
a737bd4d | 19746 | |
2fc8bdac ZW |
19747 | newval = md_chars_to_number (buf, THUMB_SIZE); |
19748 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
19749 | newval |= (S << 10) | hi; | |
19750 | newval2 |= (I1 << 13) | (I2 << 11) | lo; | |
19751 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
19752 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
19753 | } | |
19754 | break; | |
a737bd4d | 19755 | |
2fc8bdac ZW |
19756 | case BFD_RELOC_8: |
19757 | if (fixP->fx_done || !seg->use_rela_p) | |
19758 | md_number_to_chars (buf, value, 1); | |
c19d1205 | 19759 | break; |
a737bd4d | 19760 | |
c19d1205 | 19761 | case BFD_RELOC_16: |
2fc8bdac | 19762 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 19763 | md_number_to_chars (buf, value, 2); |
c19d1205 | 19764 | break; |
a737bd4d | 19765 | |
c19d1205 ZW |
19766 | #ifdef OBJ_ELF |
19767 | case BFD_RELOC_ARM_TLS_GD32: | |
19768 | case BFD_RELOC_ARM_TLS_LE32: | |
19769 | case BFD_RELOC_ARM_TLS_IE32: | |
19770 | case BFD_RELOC_ARM_TLS_LDM32: | |
19771 | case BFD_RELOC_ARM_TLS_LDO32: | |
19772 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
19773 | /* fall through */ | |
6c43fab6 | 19774 | |
c19d1205 ZW |
19775 | case BFD_RELOC_ARM_GOT32: |
19776 | case BFD_RELOC_ARM_GOTOFF: | |
19777 | case BFD_RELOC_ARM_TARGET2: | |
2fc8bdac ZW |
19778 | if (fixP->fx_done || !seg->use_rela_p) |
19779 | md_number_to_chars (buf, 0, 4); | |
c19d1205 ZW |
19780 | break; |
19781 | #endif | |
6c43fab6 | 19782 | |
c19d1205 ZW |
19783 | case BFD_RELOC_RVA: |
19784 | case BFD_RELOC_32: | |
19785 | case BFD_RELOC_ARM_TARGET1: | |
19786 | case BFD_RELOC_ARM_ROSEGREL32: | |
19787 | case BFD_RELOC_ARM_SBREL32: | |
19788 | case BFD_RELOC_32_PCREL: | |
f0927246 NC |
19789 | #ifdef TE_PE |
19790 | case BFD_RELOC_32_SECREL: | |
19791 | #endif | |
2fc8bdac | 19792 | if (fixP->fx_done || !seg->use_rela_p) |
53baae48 NC |
19793 | #ifdef TE_WINCE |
19794 | /* For WinCE we only do this for pcrel fixups. */ | |
19795 | if (fixP->fx_done || fixP->fx_pcrel) | |
19796 | #endif | |
19797 | md_number_to_chars (buf, value, 4); | |
c19d1205 | 19798 | break; |
6c43fab6 | 19799 | |
c19d1205 ZW |
19800 | #ifdef OBJ_ELF |
19801 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 19802 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
19803 | { |
19804 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
19805 | if ((value ^ (value >> 1)) & 0x40000000) | |
19806 | { | |
19807 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19808 | _("rel31 relocation overflow")); | |
19809 | } | |
19810 | newval |= value & 0x7fffffff; | |
19811 | md_number_to_chars (buf, newval, 4); | |
19812 | } | |
19813 | break; | |
c19d1205 | 19814 | #endif |
a737bd4d | 19815 | |
c19d1205 | 19816 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 19817 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
c19d1205 ZW |
19818 | if (value < -1023 || value > 1023 || (value & 3)) |
19819 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19820 | _("co-processor offset out of range")); | |
19821 | cp_off_common: | |
19822 | sign = value >= 0; | |
19823 | if (value < 0) | |
19824 | value = -value; | |
8f06b2d8 PB |
19825 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
19826 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
19827 | newval = md_chars_to_number (buf, INSN_SIZE); | |
19828 | else | |
19829 | newval = get_thumb32_insn (buf); | |
19830 | newval &= 0xff7fff00; | |
c19d1205 | 19831 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); |
8f06b2d8 PB |
19832 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
19833 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
19834 | md_number_to_chars (buf, newval, INSN_SIZE); | |
19835 | else | |
19836 | put_thumb32_insn (buf, newval); | |
c19d1205 | 19837 | break; |
a737bd4d | 19838 | |
c19d1205 | 19839 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 19840 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
19841 | if (value < -255 || value > 255) |
19842 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19843 | _("co-processor offset out of range")); | |
df7849c5 | 19844 | value *= 4; |
c19d1205 | 19845 | goto cp_off_common; |
6c43fab6 | 19846 | |
c19d1205 ZW |
19847 | case BFD_RELOC_ARM_THUMB_OFFSET: |
19848 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
19849 | /* Exactly what ranges, and where the offset is inserted depends | |
19850 | on the type of instruction, we can establish this from the | |
19851 | top 4 bits. */ | |
19852 | switch (newval >> 12) | |
19853 | { | |
19854 | case 4: /* PC load. */ | |
19855 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
19856 | forced to zero for these loads; md_pcrel_from has already | |
19857 | compensated for this. */ | |
19858 | if (value & 3) | |
19859 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19860 | _("invalid offset, target not word aligned (0x%08lX)"), | |
0359e808 NC |
19861 | (((unsigned long) fixP->fx_frag->fr_address |
19862 | + (unsigned long) fixP->fx_where) & ~3) | |
19863 | + (unsigned long) value); | |
a737bd4d | 19864 | |
c19d1205 ZW |
19865 | if (value & ~0x3fc) |
19866 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19867 | _("invalid offset, value too big (0x%08lX)"), | |
19868 | (long) value); | |
a737bd4d | 19869 | |
c19d1205 ZW |
19870 | newval |= value >> 2; |
19871 | break; | |
a737bd4d | 19872 | |
c19d1205 ZW |
19873 | case 9: /* SP load/store. */ |
19874 | if (value & ~0x3fc) | |
19875 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19876 | _("invalid offset, value too big (0x%08lX)"), | |
19877 | (long) value); | |
19878 | newval |= value >> 2; | |
19879 | break; | |
6c43fab6 | 19880 | |
c19d1205 ZW |
19881 | case 6: /* Word load/store. */ |
19882 | if (value & ~0x7c) | |
19883 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19884 | _("invalid offset, value too big (0x%08lX)"), | |
19885 | (long) value); | |
19886 | newval |= value << 4; /* 6 - 2. */ | |
19887 | break; | |
a737bd4d | 19888 | |
c19d1205 ZW |
19889 | case 7: /* Byte load/store. */ |
19890 | if (value & ~0x1f) | |
19891 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19892 | _("invalid offset, value too big (0x%08lX)"), | |
19893 | (long) value); | |
19894 | newval |= value << 6; | |
19895 | break; | |
a737bd4d | 19896 | |
c19d1205 ZW |
19897 | case 8: /* Halfword load/store. */ |
19898 | if (value & ~0x3e) | |
19899 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19900 | _("invalid offset, value too big (0x%08lX)"), | |
19901 | (long) value); | |
19902 | newval |= value << 5; /* 6 - 1. */ | |
19903 | break; | |
a737bd4d | 19904 | |
c19d1205 ZW |
19905 | default: |
19906 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19907 | "Unable to process relocation for thumb opcode: %lx", | |
19908 | (unsigned long) newval); | |
19909 | break; | |
19910 | } | |
19911 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
19912 | break; | |
a737bd4d | 19913 | |
c19d1205 ZW |
19914 | case BFD_RELOC_ARM_THUMB_ADD: |
19915 | /* This is a complicated relocation, since we use it for all of | |
19916 | the following immediate relocations: | |
a737bd4d | 19917 | |
c19d1205 ZW |
19918 | 3bit ADD/SUB |
19919 | 8bit ADD/SUB | |
19920 | 9bit ADD/SUB SP word-aligned | |
19921 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 19922 | |
c19d1205 ZW |
19923 | The type of instruction being processed is encoded in the |
19924 | instruction field: | |
a737bd4d | 19925 | |
c19d1205 ZW |
19926 | 0x8000 SUB |
19927 | 0x00F0 Rd | |
19928 | 0x000F Rs | |
19929 | */ | |
19930 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
19931 | { | |
19932 | int rd = (newval >> 4) & 0xf; | |
19933 | int rs = newval & 0xf; | |
19934 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 19935 | |
c19d1205 ZW |
19936 | /* Check for HI regs, only very restricted cases allowed: |
19937 | Adjusting SP, and using PC or SP to get an address. */ | |
19938 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
19939 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
19940 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19941 | _("invalid Hi register with immediate")); | |
a737bd4d | 19942 | |
c19d1205 ZW |
19943 | /* If value is negative, choose the opposite instruction. */ |
19944 | if (value < 0) | |
19945 | { | |
19946 | value = -value; | |
19947 | subtract = !subtract; | |
19948 | if (value < 0) | |
19949 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19950 | _("immediate value out of range")); | |
19951 | } | |
a737bd4d | 19952 | |
c19d1205 ZW |
19953 | if (rd == REG_SP) |
19954 | { | |
19955 | if (value & ~0x1fc) | |
19956 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19957 | _("invalid immediate for stack address calculation")); | |
19958 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
19959 | newval |= value >> 2; | |
19960 | } | |
19961 | else if (rs == REG_PC || rs == REG_SP) | |
19962 | { | |
19963 | if (subtract || value & ~0x3fc) | |
19964 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19965 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
19966 | (unsigned long) value); | |
19967 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); | |
19968 | newval |= rd << 8; | |
19969 | newval |= value >> 2; | |
19970 | } | |
19971 | else if (rs == rd) | |
19972 | { | |
19973 | if (value & ~0xff) | |
19974 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19975 | _("immediate value out of range")); | |
19976 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
19977 | newval |= (rd << 8) | value; | |
19978 | } | |
19979 | else | |
19980 | { | |
19981 | if (value & ~0x7) | |
19982 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19983 | _("immediate value out of range")); | |
19984 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
19985 | newval |= rd | (rs << 3) | (value << 6); | |
19986 | } | |
19987 | } | |
19988 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
19989 | break; | |
a737bd4d | 19990 | |
c19d1205 ZW |
19991 | case BFD_RELOC_ARM_THUMB_IMM: |
19992 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
19993 | if (value < 0 || value > 255) | |
19994 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
4e6e072b | 19995 | _("invalid immediate: %ld is out of range"), |
c19d1205 ZW |
19996 | (long) value); |
19997 | newval |= value; | |
19998 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
19999 | break; | |
a737bd4d | 20000 | |
c19d1205 ZW |
20001 | case BFD_RELOC_ARM_THUMB_SHIFT: |
20002 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
20003 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
20004 | temp = newval & 0xf800; | |
20005 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
20006 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20007 | _("invalid shift value: %ld"), (long) value); | |
20008 | /* Shifts of zero must be encoded as LSL. */ | |
20009 | if (value == 0) | |
20010 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
20011 | /* Shifts of 32 are encoded as zero. */ | |
20012 | else if (value == 32) | |
20013 | value = 0; | |
20014 | newval |= value << 6; | |
20015 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20016 | break; | |
a737bd4d | 20017 | |
c19d1205 ZW |
20018 | case BFD_RELOC_VTABLE_INHERIT: |
20019 | case BFD_RELOC_VTABLE_ENTRY: | |
20020 | fixP->fx_done = 0; | |
20021 | return; | |
6c43fab6 | 20022 | |
b6895b4f PB |
20023 | case BFD_RELOC_ARM_MOVW: |
20024 | case BFD_RELOC_ARM_MOVT: | |
20025 | case BFD_RELOC_ARM_THUMB_MOVW: | |
20026 | case BFD_RELOC_ARM_THUMB_MOVT: | |
20027 | if (fixP->fx_done || !seg->use_rela_p) | |
20028 | { | |
20029 | /* REL format relocations are limited to a 16-bit addend. */ | |
20030 | if (!fixP->fx_done) | |
20031 | { | |
39623e12 | 20032 | if (value < -0x8000 || value > 0x7fff) |
b6895b4f | 20033 | as_bad_where (fixP->fx_file, fixP->fx_line, |
ff5075ca | 20034 | _("offset out of range")); |
b6895b4f PB |
20035 | } |
20036 | else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
20037 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
20038 | { | |
20039 | value >>= 16; | |
20040 | } | |
20041 | ||
20042 | if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
20043 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
20044 | { | |
20045 | newval = get_thumb32_insn (buf); | |
20046 | newval &= 0xfbf08f00; | |
20047 | newval |= (value & 0xf000) << 4; | |
20048 | newval |= (value & 0x0800) << 15; | |
20049 | newval |= (value & 0x0700) << 4; | |
20050 | newval |= (value & 0x00ff); | |
20051 | put_thumb32_insn (buf, newval); | |
20052 | } | |
20053 | else | |
20054 | { | |
20055 | newval = md_chars_to_number (buf, 4); | |
20056 | newval &= 0xfff0f000; | |
20057 | newval |= value & 0x0fff; | |
20058 | newval |= (value & 0xf000) << 4; | |
20059 | md_number_to_chars (buf, newval, 4); | |
20060 | } | |
20061 | } | |
20062 | return; | |
20063 | ||
4962c51a MS |
20064 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
20065 | case BFD_RELOC_ARM_ALU_PC_G0: | |
20066 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
20067 | case BFD_RELOC_ARM_ALU_PC_G1: | |
20068 | case BFD_RELOC_ARM_ALU_PC_G2: | |
20069 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
20070 | case BFD_RELOC_ARM_ALU_SB_G0: | |
20071 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
20072 | case BFD_RELOC_ARM_ALU_SB_G1: | |
20073 | case BFD_RELOC_ARM_ALU_SB_G2: | |
20074 | assert (!fixP->fx_done); | |
20075 | if (!seg->use_rela_p) | |
20076 | { | |
20077 | bfd_vma insn; | |
20078 | bfd_vma encoded_addend; | |
20079 | bfd_vma addend_abs = abs (value); | |
20080 | ||
20081 | /* Check that the absolute value of the addend can be | |
20082 | expressed as an 8-bit constant plus a rotation. */ | |
20083 | encoded_addend = encode_arm_immediate (addend_abs); | |
20084 | if (encoded_addend == (unsigned int) FAIL) | |
20085 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20086 | _("the offset 0x%08lX is not representable"), | |
495bde8e | 20087 | (unsigned long) addend_abs); |
4962c51a MS |
20088 | |
20089 | /* Extract the instruction. */ | |
20090 | insn = md_chars_to_number (buf, INSN_SIZE); | |
20091 | ||
20092 | /* If the addend is positive, use an ADD instruction. | |
20093 | Otherwise use a SUB. Take care not to destroy the S bit. */ | |
20094 | insn &= 0xff1fffff; | |
20095 | if (value < 0) | |
20096 | insn |= 1 << 22; | |
20097 | else | |
20098 | insn |= 1 << 23; | |
20099 | ||
20100 | /* Place the encoded addend into the first 12 bits of the | |
20101 | instruction. */ | |
20102 | insn &= 0xfffff000; | |
20103 | insn |= encoded_addend; | |
5f4273c7 NC |
20104 | |
20105 | /* Update the instruction. */ | |
4962c51a MS |
20106 | md_number_to_chars (buf, insn, INSN_SIZE); |
20107 | } | |
20108 | break; | |
20109 | ||
20110 | case BFD_RELOC_ARM_LDR_PC_G0: | |
20111 | case BFD_RELOC_ARM_LDR_PC_G1: | |
20112 | case BFD_RELOC_ARM_LDR_PC_G2: | |
20113 | case BFD_RELOC_ARM_LDR_SB_G0: | |
20114 | case BFD_RELOC_ARM_LDR_SB_G1: | |
20115 | case BFD_RELOC_ARM_LDR_SB_G2: | |
20116 | assert (!fixP->fx_done); | |
20117 | if (!seg->use_rela_p) | |
20118 | { | |
20119 | bfd_vma insn; | |
20120 | bfd_vma addend_abs = abs (value); | |
20121 | ||
20122 | /* Check that the absolute value of the addend can be | |
20123 | encoded in 12 bits. */ | |
20124 | if (addend_abs >= 0x1000) | |
20125 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20126 | _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), | |
495bde8e | 20127 | (unsigned long) addend_abs); |
4962c51a MS |
20128 | |
20129 | /* Extract the instruction. */ | |
20130 | insn = md_chars_to_number (buf, INSN_SIZE); | |
20131 | ||
20132 | /* If the addend is negative, clear bit 23 of the instruction. | |
20133 | Otherwise set it. */ | |
20134 | if (value < 0) | |
20135 | insn &= ~(1 << 23); | |
20136 | else | |
20137 | insn |= 1 << 23; | |
20138 | ||
20139 | /* Place the absolute value of the addend into the first 12 bits | |
20140 | of the instruction. */ | |
20141 | insn &= 0xfffff000; | |
20142 | insn |= addend_abs; | |
5f4273c7 NC |
20143 | |
20144 | /* Update the instruction. */ | |
4962c51a MS |
20145 | md_number_to_chars (buf, insn, INSN_SIZE); |
20146 | } | |
20147 | break; | |
20148 | ||
20149 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
20150 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
20151 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
20152 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
20153 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
20154 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
20155 | assert (!fixP->fx_done); | |
20156 | if (!seg->use_rela_p) | |
20157 | { | |
20158 | bfd_vma insn; | |
20159 | bfd_vma addend_abs = abs (value); | |
20160 | ||
20161 | /* Check that the absolute value of the addend can be | |
20162 | encoded in 8 bits. */ | |
20163 | if (addend_abs >= 0x100) | |
20164 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20165 | _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), | |
495bde8e | 20166 | (unsigned long) addend_abs); |
4962c51a MS |
20167 | |
20168 | /* Extract the instruction. */ | |
20169 | insn = md_chars_to_number (buf, INSN_SIZE); | |
20170 | ||
20171 | /* If the addend is negative, clear bit 23 of the instruction. | |
20172 | Otherwise set it. */ | |
20173 | if (value < 0) | |
20174 | insn &= ~(1 << 23); | |
20175 | else | |
20176 | insn |= 1 << 23; | |
20177 | ||
20178 | /* Place the first four bits of the absolute value of the addend | |
20179 | into the first 4 bits of the instruction, and the remaining | |
20180 | four into bits 8 .. 11. */ | |
20181 | insn &= 0xfffff0f0; | |
20182 | insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); | |
5f4273c7 NC |
20183 | |
20184 | /* Update the instruction. */ | |
4962c51a MS |
20185 | md_number_to_chars (buf, insn, INSN_SIZE); |
20186 | } | |
20187 | break; | |
20188 | ||
20189 | case BFD_RELOC_ARM_LDC_PC_G0: | |
20190 | case BFD_RELOC_ARM_LDC_PC_G1: | |
20191 | case BFD_RELOC_ARM_LDC_PC_G2: | |
20192 | case BFD_RELOC_ARM_LDC_SB_G0: | |
20193 | case BFD_RELOC_ARM_LDC_SB_G1: | |
20194 | case BFD_RELOC_ARM_LDC_SB_G2: | |
20195 | assert (!fixP->fx_done); | |
20196 | if (!seg->use_rela_p) | |
20197 | { | |
20198 | bfd_vma insn; | |
20199 | bfd_vma addend_abs = abs (value); | |
20200 | ||
20201 | /* Check that the absolute value of the addend is a multiple of | |
20202 | four and, when divided by four, fits in 8 bits. */ | |
20203 | if (addend_abs & 0x3) | |
20204 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20205 | _("bad offset 0x%08lX (must be word-aligned)"), | |
495bde8e | 20206 | (unsigned long) addend_abs); |
4962c51a MS |
20207 | |
20208 | if ((addend_abs >> 2) > 0xff) | |
20209 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20210 | _("bad offset 0x%08lX (must be an 8-bit number of words)"), | |
495bde8e | 20211 | (unsigned long) addend_abs); |
4962c51a MS |
20212 | |
20213 | /* Extract the instruction. */ | |
20214 | insn = md_chars_to_number (buf, INSN_SIZE); | |
20215 | ||
20216 | /* If the addend is negative, clear bit 23 of the instruction. | |
20217 | Otherwise set it. */ | |
20218 | if (value < 0) | |
20219 | insn &= ~(1 << 23); | |
20220 | else | |
20221 | insn |= 1 << 23; | |
20222 | ||
20223 | /* Place the addend (divided by four) into the first eight | |
20224 | bits of the instruction. */ | |
20225 | insn &= 0xfffffff0; | |
20226 | insn |= addend_abs >> 2; | |
5f4273c7 NC |
20227 | |
20228 | /* Update the instruction. */ | |
4962c51a MS |
20229 | md_number_to_chars (buf, insn, INSN_SIZE); |
20230 | } | |
20231 | break; | |
20232 | ||
845b51d6 PB |
20233 | case BFD_RELOC_ARM_V4BX: |
20234 | /* This will need to go in the object file. */ | |
20235 | fixP->fx_done = 0; | |
20236 | break; | |
20237 | ||
c19d1205 ZW |
20238 | case BFD_RELOC_UNUSED: |
20239 | default: | |
20240 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20241 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
20242 | } | |
6c43fab6 RE |
20243 | } |
20244 | ||
c19d1205 ZW |
20245 | /* Translate internal representation of relocation info to BFD target |
20246 | format. */ | |
a737bd4d | 20247 | |
c19d1205 | 20248 | arelent * |
00a97672 | 20249 | tc_gen_reloc (asection *section, fixS *fixp) |
a737bd4d | 20250 | { |
c19d1205 ZW |
20251 | arelent * reloc; |
20252 | bfd_reloc_code_real_type code; | |
a737bd4d | 20253 | |
c19d1205 | 20254 | reloc = xmalloc (sizeof (arelent)); |
a737bd4d | 20255 | |
c19d1205 ZW |
20256 | reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); |
20257 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
20258 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 20259 | |
2fc8bdac | 20260 | if (fixp->fx_pcrel) |
00a97672 RS |
20261 | { |
20262 | if (section->use_rela_p) | |
20263 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
20264 | else | |
20265 | fixp->fx_offset = reloc->address; | |
20266 | } | |
c19d1205 | 20267 | reloc->addend = fixp->fx_offset; |
a737bd4d | 20268 | |
c19d1205 | 20269 | switch (fixp->fx_r_type) |
a737bd4d | 20270 | { |
c19d1205 ZW |
20271 | case BFD_RELOC_8: |
20272 | if (fixp->fx_pcrel) | |
20273 | { | |
20274 | code = BFD_RELOC_8_PCREL; | |
20275 | break; | |
20276 | } | |
a737bd4d | 20277 | |
c19d1205 ZW |
20278 | case BFD_RELOC_16: |
20279 | if (fixp->fx_pcrel) | |
20280 | { | |
20281 | code = BFD_RELOC_16_PCREL; | |
20282 | break; | |
20283 | } | |
6c43fab6 | 20284 | |
c19d1205 ZW |
20285 | case BFD_RELOC_32: |
20286 | if (fixp->fx_pcrel) | |
20287 | { | |
20288 | code = BFD_RELOC_32_PCREL; | |
20289 | break; | |
20290 | } | |
a737bd4d | 20291 | |
b6895b4f PB |
20292 | case BFD_RELOC_ARM_MOVW: |
20293 | if (fixp->fx_pcrel) | |
20294 | { | |
20295 | code = BFD_RELOC_ARM_MOVW_PCREL; | |
20296 | break; | |
20297 | } | |
20298 | ||
20299 | case BFD_RELOC_ARM_MOVT: | |
20300 | if (fixp->fx_pcrel) | |
20301 | { | |
20302 | code = BFD_RELOC_ARM_MOVT_PCREL; | |
20303 | break; | |
20304 | } | |
20305 | ||
20306 | case BFD_RELOC_ARM_THUMB_MOVW: | |
20307 | if (fixp->fx_pcrel) | |
20308 | { | |
20309 | code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; | |
20310 | break; | |
20311 | } | |
20312 | ||
20313 | case BFD_RELOC_ARM_THUMB_MOVT: | |
20314 | if (fixp->fx_pcrel) | |
20315 | { | |
20316 | code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; | |
20317 | break; | |
20318 | } | |
20319 | ||
c19d1205 ZW |
20320 | case BFD_RELOC_NONE: |
20321 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
20322 | case BFD_RELOC_ARM_PCREL_BLX: | |
20323 | case BFD_RELOC_RVA: | |
20324 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
20325 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
20326 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
20327 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
20328 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
20329 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
c19d1205 ZW |
20330 | case BFD_RELOC_VTABLE_ENTRY: |
20331 | case BFD_RELOC_VTABLE_INHERIT: | |
f0927246 NC |
20332 | #ifdef TE_PE |
20333 | case BFD_RELOC_32_SECREL: | |
20334 | #endif | |
c19d1205 ZW |
20335 | code = fixp->fx_r_type; |
20336 | break; | |
a737bd4d | 20337 | |
00adf2d4 JB |
20338 | case BFD_RELOC_THUMB_PCREL_BLX: |
20339 | #ifdef OBJ_ELF | |
20340 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
20341 | code = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
20342 | else | |
20343 | #endif | |
20344 | code = BFD_RELOC_THUMB_PCREL_BLX; | |
20345 | break; | |
20346 | ||
c19d1205 ZW |
20347 | case BFD_RELOC_ARM_LITERAL: |
20348 | case BFD_RELOC_ARM_HWLITERAL: | |
20349 | /* If this is called then the a literal has | |
20350 | been referenced across a section boundary. */ | |
20351 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
20352 | _("literal referenced across section boundary")); | |
20353 | return NULL; | |
a737bd4d | 20354 | |
c19d1205 ZW |
20355 | #ifdef OBJ_ELF |
20356 | case BFD_RELOC_ARM_GOT32: | |
20357 | case BFD_RELOC_ARM_GOTOFF: | |
20358 | case BFD_RELOC_ARM_PLT32: | |
20359 | case BFD_RELOC_ARM_TARGET1: | |
20360 | case BFD_RELOC_ARM_ROSEGREL32: | |
20361 | case BFD_RELOC_ARM_SBREL32: | |
20362 | case BFD_RELOC_ARM_PREL31: | |
20363 | case BFD_RELOC_ARM_TARGET2: | |
20364 | case BFD_RELOC_ARM_TLS_LE32: | |
20365 | case BFD_RELOC_ARM_TLS_LDO32: | |
39b41c9c PB |
20366 | case BFD_RELOC_ARM_PCREL_CALL: |
20367 | case BFD_RELOC_ARM_PCREL_JUMP: | |
4962c51a MS |
20368 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
20369 | case BFD_RELOC_ARM_ALU_PC_G0: | |
20370 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
20371 | case BFD_RELOC_ARM_ALU_PC_G1: | |
20372 | case BFD_RELOC_ARM_ALU_PC_G2: | |
20373 | case BFD_RELOC_ARM_LDR_PC_G0: | |
20374 | case BFD_RELOC_ARM_LDR_PC_G1: | |
20375 | case BFD_RELOC_ARM_LDR_PC_G2: | |
20376 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
20377 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
20378 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
20379 | case BFD_RELOC_ARM_LDC_PC_G0: | |
20380 | case BFD_RELOC_ARM_LDC_PC_G1: | |
20381 | case BFD_RELOC_ARM_LDC_PC_G2: | |
20382 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
20383 | case BFD_RELOC_ARM_ALU_SB_G0: | |
20384 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
20385 | case BFD_RELOC_ARM_ALU_SB_G1: | |
20386 | case BFD_RELOC_ARM_ALU_SB_G2: | |
20387 | case BFD_RELOC_ARM_LDR_SB_G0: | |
20388 | case BFD_RELOC_ARM_LDR_SB_G1: | |
20389 | case BFD_RELOC_ARM_LDR_SB_G2: | |
20390 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
20391 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
20392 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
20393 | case BFD_RELOC_ARM_LDC_SB_G0: | |
20394 | case BFD_RELOC_ARM_LDC_SB_G1: | |
20395 | case BFD_RELOC_ARM_LDC_SB_G2: | |
845b51d6 | 20396 | case BFD_RELOC_ARM_V4BX: |
c19d1205 ZW |
20397 | code = fixp->fx_r_type; |
20398 | break; | |
a737bd4d | 20399 | |
c19d1205 ZW |
20400 | case BFD_RELOC_ARM_TLS_GD32: |
20401 | case BFD_RELOC_ARM_TLS_IE32: | |
20402 | case BFD_RELOC_ARM_TLS_LDM32: | |
20403 | /* BFD will include the symbol's address in the addend. | |
20404 | But we don't want that, so subtract it out again here. */ | |
20405 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
20406 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
20407 | code = fixp->fx_r_type; | |
20408 | break; | |
20409 | #endif | |
a737bd4d | 20410 | |
c19d1205 ZW |
20411 | case BFD_RELOC_ARM_IMMEDIATE: |
20412 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
20413 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
20414 | return NULL; | |
a737bd4d | 20415 | |
c19d1205 ZW |
20416 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
20417 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
20418 | _("ADRL used for a symbol not defined in the same file")); | |
20419 | return NULL; | |
a737bd4d | 20420 | |
c19d1205 | 20421 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
20422 | if (section->use_rela_p) |
20423 | { | |
20424 | code = fixp->fx_r_type; | |
20425 | break; | |
20426 | } | |
20427 | ||
c19d1205 ZW |
20428 | if (fixp->fx_addsy != NULL |
20429 | && !S_IS_DEFINED (fixp->fx_addsy) | |
20430 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 20431 | { |
c19d1205 ZW |
20432 | as_bad_where (fixp->fx_file, fixp->fx_line, |
20433 | _("undefined local label `%s'"), | |
20434 | S_GET_NAME (fixp->fx_addsy)); | |
20435 | return NULL; | |
a737bd4d NC |
20436 | } |
20437 | ||
c19d1205 ZW |
20438 | as_bad_where (fixp->fx_file, fixp->fx_line, |
20439 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
20440 | return NULL; | |
a737bd4d | 20441 | |
c19d1205 ZW |
20442 | default: |
20443 | { | |
20444 | char * type; | |
6c43fab6 | 20445 | |
c19d1205 ZW |
20446 | switch (fixp->fx_r_type) |
20447 | { | |
20448 | case BFD_RELOC_NONE: type = "NONE"; break; | |
20449 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
20450 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 20451 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
20452 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
20453 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
20454 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
8f06b2d8 | 20455 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
20456 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
20457 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
20458 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
20459 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
20460 | default: type = _("<unknown>"); break; | |
20461 | } | |
20462 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
20463 | _("cannot represent %s relocation in this object file format"), | |
20464 | type); | |
20465 | return NULL; | |
20466 | } | |
a737bd4d | 20467 | } |
6c43fab6 | 20468 | |
c19d1205 ZW |
20469 | #ifdef OBJ_ELF |
20470 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
20471 | && GOT_symbol | |
20472 | && fixp->fx_addsy == GOT_symbol) | |
20473 | { | |
20474 | code = BFD_RELOC_ARM_GOTPC; | |
20475 | reloc->addend = fixp->fx_offset = reloc->address; | |
20476 | } | |
20477 | #endif | |
6c43fab6 | 20478 | |
c19d1205 | 20479 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 20480 | |
c19d1205 ZW |
20481 | if (reloc->howto == NULL) |
20482 | { | |
20483 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
20484 | _("cannot represent %s relocation in this object file format"), | |
20485 | bfd_get_reloc_code_name (code)); | |
20486 | return NULL; | |
20487 | } | |
6c43fab6 | 20488 | |
c19d1205 ZW |
20489 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
20490 | vtable entry to be used in the relocation's section offset. */ | |
20491 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
20492 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 20493 | |
c19d1205 | 20494 | return reloc; |
6c43fab6 RE |
20495 | } |
20496 | ||
c19d1205 | 20497 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 20498 | |
c19d1205 ZW |
20499 | void |
20500 | cons_fix_new_arm (fragS * frag, | |
20501 | int where, | |
20502 | int size, | |
20503 | expressionS * exp) | |
6c43fab6 | 20504 | { |
c19d1205 ZW |
20505 | bfd_reloc_code_real_type type; |
20506 | int pcrel = 0; | |
6c43fab6 | 20507 | |
c19d1205 ZW |
20508 | /* Pick a reloc. |
20509 | FIXME: @@ Should look at CPU word size. */ | |
20510 | switch (size) | |
20511 | { | |
20512 | case 1: | |
20513 | type = BFD_RELOC_8; | |
20514 | break; | |
20515 | case 2: | |
20516 | type = BFD_RELOC_16; | |
20517 | break; | |
20518 | case 4: | |
20519 | default: | |
20520 | type = BFD_RELOC_32; | |
20521 | break; | |
20522 | case 8: | |
20523 | type = BFD_RELOC_64; | |
20524 | break; | |
20525 | } | |
6c43fab6 | 20526 | |
f0927246 NC |
20527 | #ifdef TE_PE |
20528 | if (exp->X_op == O_secrel) | |
20529 | { | |
20530 | exp->X_op = O_symbol; | |
20531 | type = BFD_RELOC_32_SECREL; | |
20532 | } | |
20533 | #endif | |
20534 | ||
c19d1205 ZW |
20535 | fix_new_exp (frag, where, (int) size, exp, pcrel, type); |
20536 | } | |
6c43fab6 | 20537 | |
4343666d | 20538 | #if defined (OBJ_COFF) |
c19d1205 ZW |
20539 | void |
20540 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 20541 | { |
c19d1205 ZW |
20542 | /* If the destination of the branch is a defined symbol which does not have |
20543 | the THUMB_FUNC attribute, then we must be calling a function which has | |
20544 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
20545 | function and change the branch to refer to that function instead. */ | |
20546 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
20547 | && fixP->fx_addsy != NULL | |
20548 | && S_IS_DEFINED (fixP->fx_addsy) | |
20549 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 20550 | { |
c19d1205 | 20551 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 20552 | } |
c19d1205 ZW |
20553 | } |
20554 | #endif | |
6c43fab6 | 20555 | |
267bf995 | 20556 | |
c19d1205 ZW |
20557 | int |
20558 | arm_force_relocation (struct fix * fixp) | |
20559 | { | |
20560 | #if defined (OBJ_COFF) && defined (TE_PE) | |
20561 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
20562 | return 1; | |
20563 | #endif | |
6c43fab6 | 20564 | |
267bf995 RR |
20565 | /* In case we have a call or a branch to a function in ARM ISA mode from |
20566 | a thumb function or vice-versa force the relocation. These relocations | |
20567 | are cleared off for some cores that might have blx and simple transformations | |
20568 | are possible. */ | |
20569 | ||
20570 | #ifdef OBJ_ELF | |
20571 | switch (fixp->fx_r_type) | |
20572 | { | |
20573 | case BFD_RELOC_ARM_PCREL_JUMP: | |
20574 | case BFD_RELOC_ARM_PCREL_CALL: | |
20575 | case BFD_RELOC_THUMB_PCREL_BLX: | |
20576 | if (THUMB_IS_FUNC (fixp->fx_addsy)) | |
20577 | return 1; | |
20578 | break; | |
20579 | ||
20580 | case BFD_RELOC_ARM_PCREL_BLX: | |
20581 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
20582 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
20583 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
20584 | if (ARM_IS_FUNC (fixp->fx_addsy)) | |
20585 | return 1; | |
20586 | break; | |
20587 | ||
20588 | default: | |
20589 | break; | |
20590 | } | |
20591 | #endif | |
20592 | ||
c19d1205 ZW |
20593 | /* Resolve these relocations even if the symbol is extern or weak. */ |
20594 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE | |
20595 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
0110f2b8 | 20596 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
16805f35 | 20597 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM |
0110f2b8 PB |
20598 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
20599 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
20600 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12) | |
c19d1205 | 20601 | return 0; |
a737bd4d | 20602 | |
4962c51a MS |
20603 | /* Always leave these relocations for the linker. */ |
20604 | if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
20605 | && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
20606 | || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
20607 | return 1; | |
20608 | ||
f0291e4c PB |
20609 | /* Always generate relocations against function symbols. */ |
20610 | if (fixp->fx_r_type == BFD_RELOC_32 | |
20611 | && fixp->fx_addsy | |
20612 | && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) | |
20613 | return 1; | |
20614 | ||
c19d1205 | 20615 | return generic_force_reloc (fixp); |
404ff6b5 AH |
20616 | } |
20617 | ||
0ffdc86c | 20618 | #if defined (OBJ_ELF) || defined (OBJ_COFF) |
e28387c3 PB |
20619 | /* Relocations against function names must be left unadjusted, |
20620 | so that the linker can use this information to generate interworking | |
20621 | stubs. The MIPS version of this function | |
c19d1205 ZW |
20622 | also prevents relocations that are mips-16 specific, but I do not |
20623 | know why it does this. | |
404ff6b5 | 20624 | |
c19d1205 ZW |
20625 | FIXME: |
20626 | There is one other problem that ought to be addressed here, but | |
20627 | which currently is not: Taking the address of a label (rather | |
20628 | than a function) and then later jumping to that address. Such | |
20629 | addresses also ought to have their bottom bit set (assuming that | |
20630 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 20631 | |
c19d1205 ZW |
20632 | bfd_boolean |
20633 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 20634 | { |
c19d1205 ZW |
20635 | if (fixP->fx_addsy == NULL) |
20636 | return 1; | |
404ff6b5 | 20637 | |
e28387c3 PB |
20638 | /* Preserve relocations against symbols with function type. */ |
20639 | if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) | |
20640 | return 0; | |
20641 | ||
c19d1205 ZW |
20642 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
20643 | && fixP->fx_subsy == NULL) | |
20644 | return 0; | |
a737bd4d | 20645 | |
c19d1205 ZW |
20646 | /* We need the symbol name for the VTABLE entries. */ |
20647 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
20648 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
20649 | return 0; | |
404ff6b5 | 20650 | |
c19d1205 ZW |
20651 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
20652 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
20653 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
20654 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
20655 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
20656 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 | |
20657 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
20658 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 | |
20659 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 | |
20660 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) | |
20661 | return 0; | |
a737bd4d | 20662 | |
4962c51a MS |
20663 | /* Similarly for group relocations. */ |
20664 | if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
20665 | && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
20666 | || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
20667 | return 0; | |
20668 | ||
79947c54 CD |
20669 | /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */ |
20670 | if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW | |
20671 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
20672 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL | |
20673 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL | |
20674 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
20675 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT | |
20676 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL | |
20677 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL) | |
20678 | return 0; | |
20679 | ||
c19d1205 | 20680 | return 1; |
a737bd4d | 20681 | } |
0ffdc86c NC |
20682 | #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ |
20683 | ||
20684 | #ifdef OBJ_ELF | |
404ff6b5 | 20685 | |
c19d1205 ZW |
20686 | const char * |
20687 | elf32_arm_target_format (void) | |
404ff6b5 | 20688 | { |
c19d1205 ZW |
20689 | #ifdef TE_SYMBIAN |
20690 | return (target_big_endian | |
20691 | ? "elf32-bigarm-symbian" | |
20692 | : "elf32-littlearm-symbian"); | |
20693 | #elif defined (TE_VXWORKS) | |
20694 | return (target_big_endian | |
20695 | ? "elf32-bigarm-vxworks" | |
20696 | : "elf32-littlearm-vxworks"); | |
20697 | #else | |
20698 | if (target_big_endian) | |
20699 | return "elf32-bigarm"; | |
20700 | else | |
20701 | return "elf32-littlearm"; | |
20702 | #endif | |
404ff6b5 AH |
20703 | } |
20704 | ||
c19d1205 ZW |
20705 | void |
20706 | armelf_frob_symbol (symbolS * symp, | |
20707 | int * puntp) | |
404ff6b5 | 20708 | { |
c19d1205 ZW |
20709 | elf_frob_symbol (symp, puntp); |
20710 | } | |
20711 | #endif | |
404ff6b5 | 20712 | |
c19d1205 | 20713 | /* MD interface: Finalization. */ |
a737bd4d | 20714 | |
c19d1205 ZW |
20715 | void |
20716 | arm_cleanup (void) | |
20717 | { | |
20718 | literal_pool * pool; | |
a737bd4d | 20719 | |
e07e6e58 NC |
20720 | /* Ensure that all the IT blocks are properly closed. */ |
20721 | check_it_blocks_finished (); | |
20722 | ||
c19d1205 ZW |
20723 | for (pool = list_of_pools; pool; pool = pool->next) |
20724 | { | |
5f4273c7 | 20725 | /* Put it at the end of the relevant section. */ |
c19d1205 ZW |
20726 | subseg_set (pool->section, pool->sub_section); |
20727 | #ifdef OBJ_ELF | |
20728 | arm_elf_change_section (); | |
20729 | #endif | |
20730 | s_ltorg (0); | |
20731 | } | |
404ff6b5 AH |
20732 | } |
20733 | ||
c19d1205 ZW |
20734 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
20735 | ARM ones. */ | |
404ff6b5 | 20736 | |
c19d1205 ZW |
20737 | void |
20738 | arm_adjust_symtab (void) | |
404ff6b5 | 20739 | { |
c19d1205 ZW |
20740 | #ifdef OBJ_COFF |
20741 | symbolS * sym; | |
404ff6b5 | 20742 | |
c19d1205 ZW |
20743 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
20744 | { | |
20745 | if (ARM_IS_THUMB (sym)) | |
20746 | { | |
20747 | if (THUMB_IS_FUNC (sym)) | |
20748 | { | |
20749 | /* Mark the symbol as a Thumb function. */ | |
20750 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
20751 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
20752 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 20753 | |
c19d1205 ZW |
20754 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
20755 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
20756 | else | |
20757 | as_bad (_("%s: unexpected function type: %d"), | |
20758 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
20759 | } | |
20760 | else switch (S_GET_STORAGE_CLASS (sym)) | |
20761 | { | |
20762 | case C_EXT: | |
20763 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
20764 | break; | |
20765 | case C_STAT: | |
20766 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
20767 | break; | |
20768 | case C_LABEL: | |
20769 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
20770 | break; | |
20771 | default: | |
20772 | /* Do nothing. */ | |
20773 | break; | |
20774 | } | |
20775 | } | |
a737bd4d | 20776 | |
c19d1205 ZW |
20777 | if (ARM_IS_INTERWORK (sym)) |
20778 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 20779 | } |
c19d1205 ZW |
20780 | #endif |
20781 | #ifdef OBJ_ELF | |
20782 | symbolS * sym; | |
20783 | char bind; | |
404ff6b5 | 20784 | |
c19d1205 | 20785 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 20786 | { |
c19d1205 ZW |
20787 | if (ARM_IS_THUMB (sym)) |
20788 | { | |
20789 | elf_symbol_type * elf_sym; | |
404ff6b5 | 20790 | |
c19d1205 ZW |
20791 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
20792 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 20793 | |
b0796911 PB |
20794 | if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, |
20795 | BFD_ARM_SPECIAL_SYM_TYPE_ANY)) | |
c19d1205 ZW |
20796 | { |
20797 | /* If it's a .thumb_func, declare it as so, | |
20798 | otherwise tag label as .code 16. */ | |
20799 | if (THUMB_IS_FUNC (sym)) | |
20800 | elf_sym->internal_elf_sym.st_info = | |
20801 | ELF_ST_INFO (bind, STT_ARM_TFUNC); | |
3ba67470 | 20802 | else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
c19d1205 ZW |
20803 | elf_sym->internal_elf_sym.st_info = |
20804 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
20805 | } | |
20806 | } | |
20807 | } | |
20808 | #endif | |
404ff6b5 AH |
20809 | } |
20810 | ||
c19d1205 | 20811 | /* MD interface: Initialization. */ |
404ff6b5 | 20812 | |
a737bd4d | 20813 | static void |
c19d1205 | 20814 | set_constant_flonums (void) |
a737bd4d | 20815 | { |
c19d1205 | 20816 | int i; |
404ff6b5 | 20817 | |
c19d1205 ZW |
20818 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
20819 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
20820 | abort (); | |
a737bd4d | 20821 | } |
404ff6b5 | 20822 | |
3e9e4fcf JB |
20823 | /* Auto-select Thumb mode if it's the only available instruction set for the |
20824 | given architecture. */ | |
20825 | ||
20826 | static void | |
20827 | autoselect_thumb_from_cpu_variant (void) | |
20828 | { | |
20829 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) | |
20830 | opcode_select (16); | |
20831 | } | |
20832 | ||
c19d1205 ZW |
20833 | void |
20834 | md_begin (void) | |
a737bd4d | 20835 | { |
c19d1205 ZW |
20836 | unsigned mach; |
20837 | unsigned int i; | |
404ff6b5 | 20838 | |
c19d1205 ZW |
20839 | if ( (arm_ops_hsh = hash_new ()) == NULL |
20840 | || (arm_cond_hsh = hash_new ()) == NULL | |
20841 | || (arm_shift_hsh = hash_new ()) == NULL | |
20842 | || (arm_psr_hsh = hash_new ()) == NULL | |
62b3e311 | 20843 | || (arm_v7m_psr_hsh = hash_new ()) == NULL |
c19d1205 | 20844 | || (arm_reg_hsh = hash_new ()) == NULL |
62b3e311 PB |
20845 | || (arm_reloc_hsh = hash_new ()) == NULL |
20846 | || (arm_barrier_opt_hsh = hash_new ()) == NULL) | |
c19d1205 ZW |
20847 | as_fatal (_("virtual memory exhausted")); |
20848 | ||
20849 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
5a49b8ac | 20850 | hash_insert (arm_ops_hsh, insns[i].template, (void *) (insns + i)); |
c19d1205 | 20851 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) |
5a49b8ac | 20852 | hash_insert (arm_cond_hsh, conds[i].template, (void *) (conds + i)); |
c19d1205 | 20853 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) |
5a49b8ac | 20854 | hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i)); |
c19d1205 | 20855 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) |
5a49b8ac | 20856 | hash_insert (arm_psr_hsh, psrs[i].template, (void *) (psrs + i)); |
62b3e311 | 20857 | for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) |
5a49b8ac | 20858 | hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template, (void *) (v7m_psrs + i)); |
c19d1205 | 20859 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) |
5a49b8ac | 20860 | hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); |
62b3e311 PB |
20861 | for (i = 0; |
20862 | i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); | |
20863 | i++) | |
20864 | hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template, | |
5a49b8ac | 20865 | (void *) (barrier_opt_names + i)); |
c19d1205 ZW |
20866 | #ifdef OBJ_ELF |
20867 | for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++) | |
5a49b8ac | 20868 | hash_insert (arm_reloc_hsh, reloc_names[i].name, (void *) (reloc_names + i)); |
c19d1205 ZW |
20869 | #endif |
20870 | ||
20871 | set_constant_flonums (); | |
404ff6b5 | 20872 | |
c19d1205 ZW |
20873 | /* Set the cpu variant based on the command-line options. We prefer |
20874 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
20875 | -mfpu= over any other way of setting the floating point unit. | |
20876 | Use of legacy options with new options are faulted. */ | |
e74cfd16 | 20877 | if (legacy_cpu) |
404ff6b5 | 20878 | { |
e74cfd16 | 20879 | if (mcpu_cpu_opt || march_cpu_opt) |
c19d1205 ZW |
20880 | as_bad (_("use of old and new-style options to set CPU type")); |
20881 | ||
20882 | mcpu_cpu_opt = legacy_cpu; | |
404ff6b5 | 20883 | } |
e74cfd16 | 20884 | else if (!mcpu_cpu_opt) |
c19d1205 | 20885 | mcpu_cpu_opt = march_cpu_opt; |
404ff6b5 | 20886 | |
e74cfd16 | 20887 | if (legacy_fpu) |
c19d1205 | 20888 | { |
e74cfd16 | 20889 | if (mfpu_opt) |
c19d1205 | 20890 | as_bad (_("use of old and new-style options to set FPU type")); |
03b1477f RE |
20891 | |
20892 | mfpu_opt = legacy_fpu; | |
20893 | } | |
e74cfd16 | 20894 | else if (!mfpu_opt) |
03b1477f | 20895 | { |
45eb4c1b NS |
20896 | #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \ |
20897 | || defined (TE_NetBSD) || defined (TE_VXWORKS)) | |
39c2da32 RE |
20898 | /* Some environments specify a default FPU. If they don't, infer it |
20899 | from the processor. */ | |
e74cfd16 | 20900 | if (mcpu_fpu_opt) |
03b1477f RE |
20901 | mfpu_opt = mcpu_fpu_opt; |
20902 | else | |
20903 | mfpu_opt = march_fpu_opt; | |
39c2da32 | 20904 | #else |
e74cfd16 | 20905 | mfpu_opt = &fpu_default; |
39c2da32 | 20906 | #endif |
03b1477f RE |
20907 | } |
20908 | ||
e74cfd16 | 20909 | if (!mfpu_opt) |
03b1477f | 20910 | { |
493cb6ef | 20911 | if (mcpu_cpu_opt != NULL) |
e74cfd16 | 20912 | mfpu_opt = &fpu_default; |
493cb6ef | 20913 | else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) |
e74cfd16 | 20914 | mfpu_opt = &fpu_arch_vfp_v2; |
03b1477f | 20915 | else |
e74cfd16 | 20916 | mfpu_opt = &fpu_arch_fpa; |
03b1477f RE |
20917 | } |
20918 | ||
ee065d83 | 20919 | #ifdef CPU_DEFAULT |
e74cfd16 | 20920 | if (!mcpu_cpu_opt) |
ee065d83 | 20921 | { |
e74cfd16 PB |
20922 | mcpu_cpu_opt = &cpu_default; |
20923 | selected_cpu = cpu_default; | |
ee065d83 | 20924 | } |
e74cfd16 PB |
20925 | #else |
20926 | if (mcpu_cpu_opt) | |
20927 | selected_cpu = *mcpu_cpu_opt; | |
ee065d83 | 20928 | else |
e74cfd16 | 20929 | mcpu_cpu_opt = &arm_arch_any; |
ee065d83 | 20930 | #endif |
03b1477f | 20931 | |
e74cfd16 | 20932 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
03b1477f | 20933 | |
3e9e4fcf JB |
20934 | autoselect_thumb_from_cpu_variant (); |
20935 | ||
e74cfd16 | 20936 | arm_arch_used = thumb_arch_used = arm_arch_none; |
ee065d83 | 20937 | |
f17c130b | 20938 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 20939 | { |
7cc69913 NC |
20940 | unsigned int flags = 0; |
20941 | ||
20942 | #if defined OBJ_ELF | |
20943 | flags = meabi_flags; | |
d507cf36 PB |
20944 | |
20945 | switch (meabi_flags) | |
33a392fb | 20946 | { |
d507cf36 | 20947 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 20948 | #endif |
d507cf36 PB |
20949 | /* Set the flags in the private structure. */ |
20950 | if (uses_apcs_26) flags |= F_APCS26; | |
20951 | if (support_interwork) flags |= F_INTERWORK; | |
20952 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 20953 | if (pic_code) flags |= F_PIC; |
e74cfd16 | 20954 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
7cc69913 NC |
20955 | flags |= F_SOFT_FLOAT; |
20956 | ||
d507cf36 PB |
20957 | switch (mfloat_abi_opt) |
20958 | { | |
20959 | case ARM_FLOAT_ABI_SOFT: | |
20960 | case ARM_FLOAT_ABI_SOFTFP: | |
20961 | flags |= F_SOFT_FLOAT; | |
20962 | break; | |
33a392fb | 20963 | |
d507cf36 PB |
20964 | case ARM_FLOAT_ABI_HARD: |
20965 | if (flags & F_SOFT_FLOAT) | |
20966 | as_bad (_("hard-float conflicts with specified fpu")); | |
20967 | break; | |
20968 | } | |
03b1477f | 20969 | |
e74cfd16 PB |
20970 | /* Using pure-endian doubles (even if soft-float). */ |
20971 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
7cc69913 | 20972 | flags |= F_VFP_FLOAT; |
f17c130b | 20973 | |
fde78edd | 20974 | #if defined OBJ_ELF |
e74cfd16 | 20975 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
d507cf36 | 20976 | flags |= EF_ARM_MAVERICK_FLOAT; |
d507cf36 PB |
20977 | break; |
20978 | ||
8cb51566 | 20979 | case EF_ARM_EABI_VER4: |
3a4a14e9 | 20980 | case EF_ARM_EABI_VER5: |
c19d1205 | 20981 | /* No additional flags to set. */ |
d507cf36 PB |
20982 | break; |
20983 | ||
20984 | default: | |
20985 | abort (); | |
20986 | } | |
7cc69913 | 20987 | #endif |
b99bd4ef NC |
20988 | bfd_set_private_flags (stdoutput, flags); |
20989 | ||
20990 | /* We have run out flags in the COFF header to encode the | |
20991 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 20992 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
20993 | if (atpcs) |
20994 | { | |
20995 | asection * sec; | |
20996 | ||
20997 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
20998 | ||
20999 | if (sec != NULL) | |
21000 | { | |
21001 | bfd_set_section_flags | |
21002 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
21003 | bfd_set_section_size (stdoutput, sec, 0); | |
21004 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
21005 | } | |
21006 | } | |
7cc69913 | 21007 | } |
f17c130b | 21008 | #endif |
b99bd4ef NC |
21009 | |
21010 | /* Record the CPU type as well. */ | |
2d447fca JM |
21011 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) |
21012 | mach = bfd_mach_arm_iWMMXt2; | |
21013 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) | |
e16bb312 | 21014 | mach = bfd_mach_arm_iWMMXt; |
e74cfd16 | 21015 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
b99bd4ef | 21016 | mach = bfd_mach_arm_XScale; |
e74cfd16 | 21017 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
fde78edd | 21018 | mach = bfd_mach_arm_ep9312; |
e74cfd16 | 21019 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
b99bd4ef | 21020 | mach = bfd_mach_arm_5TE; |
e74cfd16 | 21021 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
b99bd4ef | 21022 | { |
e74cfd16 | 21023 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
21024 | mach = bfd_mach_arm_5T; |
21025 | else | |
21026 | mach = bfd_mach_arm_5; | |
21027 | } | |
e74cfd16 | 21028 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
b99bd4ef | 21029 | { |
e74cfd16 | 21030 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
21031 | mach = bfd_mach_arm_4T; |
21032 | else | |
21033 | mach = bfd_mach_arm_4; | |
21034 | } | |
e74cfd16 | 21035 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
b99bd4ef | 21036 | mach = bfd_mach_arm_3M; |
e74cfd16 PB |
21037 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
21038 | mach = bfd_mach_arm_3; | |
21039 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) | |
21040 | mach = bfd_mach_arm_2a; | |
21041 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) | |
21042 | mach = bfd_mach_arm_2; | |
21043 | else | |
21044 | mach = bfd_mach_arm_unknown; | |
b99bd4ef NC |
21045 | |
21046 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
21047 | } | |
21048 | ||
c19d1205 | 21049 | /* Command line processing. */ |
b99bd4ef | 21050 | |
c19d1205 ZW |
21051 | /* md_parse_option |
21052 | Invocation line includes a switch not recognized by the base assembler. | |
21053 | See if it's a processor-specific option. | |
b99bd4ef | 21054 | |
c19d1205 ZW |
21055 | This routine is somewhat complicated by the need for backwards |
21056 | compatibility (since older releases of gcc can't be changed). | |
21057 | The new options try to make the interface as compatible as | |
21058 | possible with GCC. | |
b99bd4ef | 21059 | |
c19d1205 | 21060 | New options (supported) are: |
b99bd4ef | 21061 | |
c19d1205 ZW |
21062 | -mcpu=<cpu name> Assemble for selected processor |
21063 | -march=<architecture name> Assemble for selected architecture | |
21064 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
21065 | -EB/-mbig-endian Big-endian | |
21066 | -EL/-mlittle-endian Little-endian | |
21067 | -k Generate PIC code | |
21068 | -mthumb Start in Thumb mode | |
21069 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 21070 | |
278df34e | 21071 | -m[no-]warn-deprecated Warn about deprecated features |
267bf995 | 21072 | |
c19d1205 | 21073 | For now we will also provide support for: |
b99bd4ef | 21074 | |
c19d1205 ZW |
21075 | -mapcs-32 32-bit Program counter |
21076 | -mapcs-26 26-bit Program counter | |
21077 | -macps-float Floats passed in FP registers | |
21078 | -mapcs-reentrant Reentrant code | |
21079 | -matpcs | |
21080 | (sometime these will probably be replaced with -mapcs=<list of options> | |
21081 | and -matpcs=<list of options>) | |
b99bd4ef | 21082 | |
c19d1205 ZW |
21083 | The remaining options are only supported for back-wards compatibility. |
21084 | Cpu variants, the arm part is optional: | |
21085 | -m[arm]1 Currently not supported. | |
21086 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
21087 | -m[arm]3 Arm 3 processor | |
21088 | -m[arm]6[xx], Arm 6 processors | |
21089 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
21090 | -m[arm]8[10] Arm 8 processors | |
21091 | -m[arm]9[20][tdmi] Arm 9 processors | |
21092 | -mstrongarm[110[0]] StrongARM processors | |
21093 | -mxscale XScale processors | |
21094 | -m[arm]v[2345[t[e]]] Arm architectures | |
21095 | -mall All (except the ARM1) | |
21096 | FP variants: | |
21097 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
21098 | -mfpe-old (No float load/store multiples) | |
21099 | -mvfpxd VFP Single precision | |
21100 | -mvfp All VFP | |
21101 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 21102 | |
c19d1205 ZW |
21103 | The following CPU names are recognized: |
21104 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
21105 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
21106 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
21107 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
21108 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
21109 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
21110 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 21111 | |
c19d1205 | 21112 | */ |
b99bd4ef | 21113 | |
c19d1205 | 21114 | const char * md_shortopts = "m:k"; |
b99bd4ef | 21115 | |
c19d1205 ZW |
21116 | #ifdef ARM_BI_ENDIAN |
21117 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
21118 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 21119 | #else |
c19d1205 ZW |
21120 | #if TARGET_BYTES_BIG_ENDIAN |
21121 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 21122 | #else |
c19d1205 ZW |
21123 | #define OPTION_EL (OPTION_MD_BASE + 1) |
21124 | #endif | |
b99bd4ef | 21125 | #endif |
845b51d6 | 21126 | #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2) |
b99bd4ef | 21127 | |
c19d1205 | 21128 | struct option md_longopts[] = |
b99bd4ef | 21129 | { |
c19d1205 ZW |
21130 | #ifdef OPTION_EB |
21131 | {"EB", no_argument, NULL, OPTION_EB}, | |
21132 | #endif | |
21133 | #ifdef OPTION_EL | |
21134 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 21135 | #endif |
845b51d6 | 21136 | {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, |
c19d1205 ZW |
21137 | {NULL, no_argument, NULL, 0} |
21138 | }; | |
b99bd4ef | 21139 | |
c19d1205 | 21140 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 21141 | |
c19d1205 | 21142 | struct arm_option_table |
b99bd4ef | 21143 | { |
c19d1205 ZW |
21144 | char *option; /* Option name to match. */ |
21145 | char *help; /* Help information. */ | |
21146 | int *var; /* Variable to change. */ | |
21147 | int value; /* What to change it to. */ | |
21148 | char *deprecated; /* If non-null, print this message. */ | |
21149 | }; | |
b99bd4ef | 21150 | |
c19d1205 ZW |
21151 | struct arm_option_table arm_opts[] = |
21152 | { | |
21153 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
21154 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
21155 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
21156 | &support_interwork, 1, NULL}, | |
21157 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
21158 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
21159 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
21160 | 1, NULL}, | |
21161 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
21162 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
21163 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
21164 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
21165 | NULL}, | |
b99bd4ef | 21166 | |
c19d1205 ZW |
21167 | /* These are recognized by the assembler, but have no affect on code. */ |
21168 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
21169 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
278df34e NS |
21170 | |
21171 | {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL}, | |
21172 | {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"), | |
21173 | &warn_on_deprecated, 0, NULL}, | |
e74cfd16 PB |
21174 | {NULL, NULL, NULL, 0, NULL} |
21175 | }; | |
21176 | ||
21177 | struct arm_legacy_option_table | |
21178 | { | |
21179 | char *option; /* Option name to match. */ | |
21180 | const arm_feature_set **var; /* Variable to change. */ | |
21181 | const arm_feature_set value; /* What to change it to. */ | |
21182 | char *deprecated; /* If non-null, print this message. */ | |
21183 | }; | |
b99bd4ef | 21184 | |
e74cfd16 PB |
21185 | const struct arm_legacy_option_table arm_legacy_opts[] = |
21186 | { | |
c19d1205 ZW |
21187 | /* DON'T add any new processors to this list -- we want the whole list |
21188 | to go away... Add them to the processors table instead. */ | |
e74cfd16 PB |
21189 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
21190 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
21191 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
21192 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
21193 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
21194 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
21195 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
21196 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
21197 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
21198 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
21199 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
21200 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
21201 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
21202 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
21203 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
21204 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
21205 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
21206 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
21207 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
21208 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
21209 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
21210 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
21211 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
21212 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
21213 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
21214 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
21215 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
21216 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
21217 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
21218 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
21219 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
21220 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
21221 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
21222 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
21223 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
21224 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
21225 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
21226 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
21227 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
21228 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
21229 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
21230 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
21231 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
21232 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
21233 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
21234 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
21235 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
21236 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
21237 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
21238 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
21239 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
21240 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
21241 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
21242 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
21243 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
21244 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
21245 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
21246 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
21247 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
21248 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
21249 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
21250 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
21251 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
21252 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
21253 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
21254 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
21255 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
21256 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
21257 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
21258 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, | |
c19d1205 | 21259 | N_("use -mcpu=strongarm110")}, |
e74cfd16 | 21260 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 21261 | N_("use -mcpu=strongarm1100")}, |
e74cfd16 | 21262 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 21263 | N_("use -mcpu=strongarm1110")}, |
e74cfd16 PB |
21264 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
21265 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
21266 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 21267 | |
c19d1205 | 21268 | /* Architecture variants -- don't add any more to this list either. */ |
e74cfd16 PB |
21269 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
21270 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
21271 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
21272 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
21273 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
21274 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
21275 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
21276 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
21277 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
21278 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
21279 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
21280 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
21281 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
21282 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
21283 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
21284 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
21285 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
21286 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 21287 | |
c19d1205 | 21288 | /* Floating point variants -- don't add any more to this list either. */ |
e74cfd16 PB |
21289 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
21290 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
21291 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
21292 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, | |
c19d1205 | 21293 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
7ed4c4c5 | 21294 | |
e74cfd16 | 21295 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
c19d1205 | 21296 | }; |
7ed4c4c5 | 21297 | |
c19d1205 | 21298 | struct arm_cpu_option_table |
7ed4c4c5 | 21299 | { |
c19d1205 | 21300 | char *name; |
e74cfd16 | 21301 | const arm_feature_set value; |
c19d1205 ZW |
21302 | /* For some CPUs we assume an FPU unless the user explicitly sets |
21303 | -mfpu=... */ | |
e74cfd16 | 21304 | const arm_feature_set default_fpu; |
ee065d83 PB |
21305 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
21306 | case. */ | |
21307 | const char *canonical_name; | |
c19d1205 | 21308 | }; |
7ed4c4c5 | 21309 | |
c19d1205 ZW |
21310 | /* This list should, at a minimum, contain all the cpu names |
21311 | recognized by GCC. */ | |
e74cfd16 | 21312 | static const struct arm_cpu_option_table arm_cpus[] = |
c19d1205 | 21313 | { |
ee065d83 PB |
21314 | {"all", ARM_ANY, FPU_ARCH_FPA, NULL}, |
21315 | {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL}, | |
21316 | {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL}, | |
21317 | {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, | |
21318 | {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, | |
21319 | {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
21320 | {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
21321 | {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
21322 | {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
21323 | {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
21324 | {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
21325 | {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
21326 | {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
21327 | {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
21328 | {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
21329 | {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
21330 | {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
21331 | {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
21332 | {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
21333 | {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
21334 | {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
21335 | {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
21336 | {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
21337 | {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
21338 | {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
21339 | {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
21340 | {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
21341 | {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
21342 | {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
21343 | {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
21344 | {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
21345 | {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
21346 | {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
21347 | {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
21348 | {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
21349 | {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
21350 | {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
21351 | {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
21352 | {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
21353 | {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"}, | |
21354 | {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
21355 | {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
21356 | {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
21357 | {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
7fac0536 NC |
21358 | {"fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, |
21359 | {"fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
c19d1205 ZW |
21360 | /* For V5 or later processors we default to using VFP; but the user |
21361 | should really set the FPU type explicitly. */ | |
ee065d83 PB |
21362 | {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, |
21363 | {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
21364 | {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, | |
21365 | {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, | |
21366 | {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, | |
21367 | {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, | |
21368 | {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"}, | |
21369 | {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
21370 | {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, | |
21371 | {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"}, | |
21372 | {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
21373 | {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
21374 | {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
21375 | {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
21376 | {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
21377 | {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"}, | |
21378 | {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
21379 | {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
21380 | {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
21381 | {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"}, | |
21382 | {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, | |
7fac0536 NC |
21383 | {"fa626te", ARM_ARCH_V5TE, FPU_NONE, NULL}, |
21384 | {"fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
ee065d83 PB |
21385 | {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"}, |
21386 | {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL}, | |
21387 | {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"}, | |
21388 | {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL}, | |
21389 | {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL}, | |
21390 | {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL}, | |
21391 | {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL}, | |
21392 | {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL}, | |
21393 | {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL}, | |
21394 | {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL}, | |
e07e6e58 | 21395 | {"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE (0, FPU_VFP_V3 |
5287ad62 | 21396 | | FPU_NEON_EXT_V1), |
15290f0a | 21397 | NULL}, |
e07e6e58 | 21398 | {"cortex-a9", ARM_ARCH_V7A, ARM_FEATURE (0, FPU_VFP_V3 |
15290f0a | 21399 | | FPU_NEON_EXT_V1), |
5287ad62 | 21400 | NULL}, |
62b3e311 PB |
21401 | {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL}, |
21402 | {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL}, | |
7e806470 | 21403 | {"cortex-m1", ARM_ARCH_V6M, FPU_NONE, NULL}, |
5b19eaba | 21404 | {"cortex-m0", ARM_ARCH_V6M, FPU_NONE, NULL}, |
c19d1205 | 21405 | /* ??? XSCALE is really an architecture. */ |
ee065d83 | 21406 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, |
c19d1205 | 21407 | /* ??? iwmmxt is not a processor. */ |
ee065d83 | 21408 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL}, |
2d447fca | 21409 | {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL}, |
ee065d83 | 21410 | {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, |
c19d1205 | 21411 | /* Maverick */ |
e07e6e58 | 21412 | {"ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"}, |
e74cfd16 | 21413 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL} |
c19d1205 | 21414 | }; |
7ed4c4c5 | 21415 | |
c19d1205 | 21416 | struct arm_arch_option_table |
7ed4c4c5 | 21417 | { |
c19d1205 | 21418 | char *name; |
e74cfd16 PB |
21419 | const arm_feature_set value; |
21420 | const arm_feature_set default_fpu; | |
c19d1205 | 21421 | }; |
7ed4c4c5 | 21422 | |
c19d1205 ZW |
21423 | /* This list should, at a minimum, contain all the architecture names |
21424 | recognized by GCC. */ | |
e74cfd16 | 21425 | static const struct arm_arch_option_table arm_archs[] = |
c19d1205 ZW |
21426 | { |
21427 | {"all", ARM_ANY, FPU_ARCH_FPA}, | |
21428 | {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA}, | |
21429 | {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA}, | |
21430 | {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
21431 | {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
21432 | {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
21433 | {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA}, | |
21434 | {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
21435 | {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA}, | |
21436 | {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
21437 | {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA}, | |
21438 | {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP}, | |
21439 | {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP}, | |
21440 | {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP}, | |
21441 | {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP}, | |
21442 | {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP}, | |
21443 | {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP}, | |
21444 | {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
21445 | {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
21446 | {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP}, | |
21447 | {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP}, | |
21448 | {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP}, | |
21449 | {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP}, | |
21450 | {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP}, | |
21451 | {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP}, | |
21452 | {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP}, | |
7e806470 | 21453 | {"armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP}, |
62b3e311 | 21454 | {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP}, |
c450d570 PB |
21455 | /* The official spelling of the ARMv7 profile variants is the dashed form. |
21456 | Accept the non-dashed form for compatibility with old toolchains. */ | |
62b3e311 PB |
21457 | {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP}, |
21458 | {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP}, | |
21459 | {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP}, | |
c450d570 PB |
21460 | {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP}, |
21461 | {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP}, | |
21462 | {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP}, | |
c19d1205 ZW |
21463 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP}, |
21464 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP}, | |
2d447fca | 21465 | {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP}, |
e74cfd16 | 21466 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} |
c19d1205 | 21467 | }; |
7ed4c4c5 | 21468 | |
c19d1205 | 21469 | /* ISA extensions in the co-processor space. */ |
e74cfd16 | 21470 | struct arm_option_cpu_value_table |
c19d1205 ZW |
21471 | { |
21472 | char *name; | |
e74cfd16 | 21473 | const arm_feature_set value; |
c19d1205 | 21474 | }; |
7ed4c4c5 | 21475 | |
e74cfd16 | 21476 | static const struct arm_option_cpu_value_table arm_extensions[] = |
c19d1205 | 21477 | { |
e74cfd16 PB |
21478 | {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)}, |
21479 | {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)}, | |
21480 | {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)}, | |
2d447fca | 21481 | {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2)}, |
e74cfd16 | 21482 | {NULL, ARM_ARCH_NONE} |
c19d1205 | 21483 | }; |
7ed4c4c5 | 21484 | |
c19d1205 ZW |
21485 | /* This list should, at a minimum, contain all the fpu names |
21486 | recognized by GCC. */ | |
e74cfd16 | 21487 | static const struct arm_option_cpu_value_table arm_fpus[] = |
c19d1205 ZW |
21488 | { |
21489 | {"softfpa", FPU_NONE}, | |
21490 | {"fpe", FPU_ARCH_FPE}, | |
21491 | {"fpe2", FPU_ARCH_FPE}, | |
21492 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
21493 | {"fpa", FPU_ARCH_FPA}, | |
21494 | {"fpa10", FPU_ARCH_FPA}, | |
21495 | {"fpa11", FPU_ARCH_FPA}, | |
21496 | {"arm7500fe", FPU_ARCH_FPA}, | |
21497 | {"softvfp", FPU_ARCH_VFP}, | |
21498 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
21499 | {"vfp", FPU_ARCH_VFP_V2}, | |
21500 | {"vfp9", FPU_ARCH_VFP_V2}, | |
b1cc4aeb | 21501 | {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */ |
c19d1205 ZW |
21502 | {"vfp10", FPU_ARCH_VFP_V2}, |
21503 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
21504 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
b1cc4aeb PB |
21505 | {"vfpv2", FPU_ARCH_VFP_V2}, |
21506 | {"vfpv3", FPU_ARCH_VFP_V3}, | |
21507 | {"vfpv3-d16", FPU_ARCH_VFP_V3D16}, | |
c19d1205 ZW |
21508 | {"arm1020t", FPU_ARCH_VFP_V1}, |
21509 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
21510 | {"arm1136jfs", FPU_ARCH_VFP_V2}, | |
21511 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, | |
21512 | {"maverick", FPU_ARCH_MAVERICK}, | |
5287ad62 | 21513 | {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
8e79c3df | 21514 | {"neon-fp16", FPU_ARCH_NEON_FP16}, |
e74cfd16 PB |
21515 | {NULL, ARM_ARCH_NONE} |
21516 | }; | |
21517 | ||
21518 | struct arm_option_value_table | |
21519 | { | |
21520 | char *name; | |
21521 | long value; | |
c19d1205 | 21522 | }; |
7ed4c4c5 | 21523 | |
e74cfd16 | 21524 | static const struct arm_option_value_table arm_float_abis[] = |
c19d1205 ZW |
21525 | { |
21526 | {"hard", ARM_FLOAT_ABI_HARD}, | |
21527 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
21528 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
e74cfd16 | 21529 | {NULL, 0} |
c19d1205 | 21530 | }; |
7ed4c4c5 | 21531 | |
c19d1205 | 21532 | #ifdef OBJ_ELF |
3a4a14e9 | 21533 | /* We only know how to output GNU and ver 4/5 (AAELF) formats. */ |
e74cfd16 | 21534 | static const struct arm_option_value_table arm_eabis[] = |
c19d1205 ZW |
21535 | { |
21536 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
21537 | {"4", EF_ARM_EABI_VER4}, | |
3a4a14e9 | 21538 | {"5", EF_ARM_EABI_VER5}, |
e74cfd16 | 21539 | {NULL, 0} |
c19d1205 ZW |
21540 | }; |
21541 | #endif | |
7ed4c4c5 | 21542 | |
c19d1205 ZW |
21543 | struct arm_long_option_table |
21544 | { | |
21545 | char * option; /* Substring to match. */ | |
21546 | char * help; /* Help information. */ | |
21547 | int (* func) (char * subopt); /* Function to decode sub-option. */ | |
21548 | char * deprecated; /* If non-null, print this message. */ | |
21549 | }; | |
7ed4c4c5 NC |
21550 | |
21551 | static int | |
e74cfd16 | 21552 | arm_parse_extension (char * str, const arm_feature_set **opt_p) |
7ed4c4c5 | 21553 | { |
e74cfd16 PB |
21554 | arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set)); |
21555 | ||
21556 | /* Copy the feature set, so that we can modify it. */ | |
21557 | *ext_set = **opt_p; | |
21558 | *opt_p = ext_set; | |
21559 | ||
c19d1205 | 21560 | while (str != NULL && *str != 0) |
7ed4c4c5 | 21561 | { |
e74cfd16 | 21562 | const struct arm_option_cpu_value_table * opt; |
c19d1205 ZW |
21563 | char * ext; |
21564 | int optlen; | |
7ed4c4c5 | 21565 | |
c19d1205 ZW |
21566 | if (*str != '+') |
21567 | { | |
21568 | as_bad (_("invalid architectural extension")); | |
21569 | return 0; | |
21570 | } | |
7ed4c4c5 | 21571 | |
c19d1205 ZW |
21572 | str++; |
21573 | ext = strchr (str, '+'); | |
7ed4c4c5 | 21574 | |
c19d1205 ZW |
21575 | if (ext != NULL) |
21576 | optlen = ext - str; | |
21577 | else | |
21578 | optlen = strlen (str); | |
7ed4c4c5 | 21579 | |
c19d1205 ZW |
21580 | if (optlen == 0) |
21581 | { | |
21582 | as_bad (_("missing architectural extension")); | |
21583 | return 0; | |
21584 | } | |
7ed4c4c5 | 21585 | |
c19d1205 ZW |
21586 | for (opt = arm_extensions; opt->name != NULL; opt++) |
21587 | if (strncmp (opt->name, str, optlen) == 0) | |
21588 | { | |
e74cfd16 | 21589 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); |
c19d1205 ZW |
21590 | break; |
21591 | } | |
7ed4c4c5 | 21592 | |
c19d1205 ZW |
21593 | if (opt->name == NULL) |
21594 | { | |
5f4273c7 | 21595 | as_bad (_("unknown architectural extension `%s'"), str); |
c19d1205 ZW |
21596 | return 0; |
21597 | } | |
7ed4c4c5 | 21598 | |
c19d1205 ZW |
21599 | str = ext; |
21600 | }; | |
7ed4c4c5 | 21601 | |
c19d1205 ZW |
21602 | return 1; |
21603 | } | |
7ed4c4c5 | 21604 | |
c19d1205 ZW |
21605 | static int |
21606 | arm_parse_cpu (char * str) | |
7ed4c4c5 | 21607 | { |
e74cfd16 | 21608 | const struct arm_cpu_option_table * opt; |
c19d1205 ZW |
21609 | char * ext = strchr (str, '+'); |
21610 | int optlen; | |
7ed4c4c5 | 21611 | |
c19d1205 ZW |
21612 | if (ext != NULL) |
21613 | optlen = ext - str; | |
7ed4c4c5 | 21614 | else |
c19d1205 | 21615 | optlen = strlen (str); |
7ed4c4c5 | 21616 | |
c19d1205 | 21617 | if (optlen == 0) |
7ed4c4c5 | 21618 | { |
c19d1205 ZW |
21619 | as_bad (_("missing cpu name `%s'"), str); |
21620 | return 0; | |
7ed4c4c5 NC |
21621 | } |
21622 | ||
c19d1205 ZW |
21623 | for (opt = arm_cpus; opt->name != NULL; opt++) |
21624 | if (strncmp (opt->name, str, optlen) == 0) | |
21625 | { | |
e74cfd16 PB |
21626 | mcpu_cpu_opt = &opt->value; |
21627 | mcpu_fpu_opt = &opt->default_fpu; | |
ee065d83 | 21628 | if (opt->canonical_name) |
5f4273c7 | 21629 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
21630 | else |
21631 | { | |
21632 | int i; | |
21633 | for (i = 0; i < optlen; i++) | |
21634 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
21635 | selected_cpu_name[i] = 0; | |
21636 | } | |
7ed4c4c5 | 21637 | |
c19d1205 ZW |
21638 | if (ext != NULL) |
21639 | return arm_parse_extension (ext, &mcpu_cpu_opt); | |
7ed4c4c5 | 21640 | |
c19d1205 ZW |
21641 | return 1; |
21642 | } | |
7ed4c4c5 | 21643 | |
c19d1205 ZW |
21644 | as_bad (_("unknown cpu `%s'"), str); |
21645 | return 0; | |
7ed4c4c5 NC |
21646 | } |
21647 | ||
c19d1205 ZW |
21648 | static int |
21649 | arm_parse_arch (char * str) | |
7ed4c4c5 | 21650 | { |
e74cfd16 | 21651 | const struct arm_arch_option_table *opt; |
c19d1205 ZW |
21652 | char *ext = strchr (str, '+'); |
21653 | int optlen; | |
7ed4c4c5 | 21654 | |
c19d1205 ZW |
21655 | if (ext != NULL) |
21656 | optlen = ext - str; | |
7ed4c4c5 | 21657 | else |
c19d1205 | 21658 | optlen = strlen (str); |
7ed4c4c5 | 21659 | |
c19d1205 | 21660 | if (optlen == 0) |
7ed4c4c5 | 21661 | { |
c19d1205 ZW |
21662 | as_bad (_("missing architecture name `%s'"), str); |
21663 | return 0; | |
7ed4c4c5 NC |
21664 | } |
21665 | ||
c19d1205 ZW |
21666 | for (opt = arm_archs; opt->name != NULL; opt++) |
21667 | if (streq (opt->name, str)) | |
21668 | { | |
e74cfd16 PB |
21669 | march_cpu_opt = &opt->value; |
21670 | march_fpu_opt = &opt->default_fpu; | |
5f4273c7 | 21671 | strcpy (selected_cpu_name, opt->name); |
7ed4c4c5 | 21672 | |
c19d1205 ZW |
21673 | if (ext != NULL) |
21674 | return arm_parse_extension (ext, &march_cpu_opt); | |
7ed4c4c5 | 21675 | |
c19d1205 ZW |
21676 | return 1; |
21677 | } | |
21678 | ||
21679 | as_bad (_("unknown architecture `%s'\n"), str); | |
21680 | return 0; | |
7ed4c4c5 | 21681 | } |
eb043451 | 21682 | |
c19d1205 ZW |
21683 | static int |
21684 | arm_parse_fpu (char * str) | |
21685 | { | |
e74cfd16 | 21686 | const struct arm_option_cpu_value_table * opt; |
b99bd4ef | 21687 | |
c19d1205 ZW |
21688 | for (opt = arm_fpus; opt->name != NULL; opt++) |
21689 | if (streq (opt->name, str)) | |
21690 | { | |
e74cfd16 | 21691 | mfpu_opt = &opt->value; |
c19d1205 ZW |
21692 | return 1; |
21693 | } | |
b99bd4ef | 21694 | |
c19d1205 ZW |
21695 | as_bad (_("unknown floating point format `%s'\n"), str); |
21696 | return 0; | |
21697 | } | |
21698 | ||
21699 | static int | |
21700 | arm_parse_float_abi (char * str) | |
b99bd4ef | 21701 | { |
e74cfd16 | 21702 | const struct arm_option_value_table * opt; |
b99bd4ef | 21703 | |
c19d1205 ZW |
21704 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
21705 | if (streq (opt->name, str)) | |
21706 | { | |
21707 | mfloat_abi_opt = opt->value; | |
21708 | return 1; | |
21709 | } | |
cc8a6dd0 | 21710 | |
c19d1205 ZW |
21711 | as_bad (_("unknown floating point abi `%s'\n"), str); |
21712 | return 0; | |
21713 | } | |
b99bd4ef | 21714 | |
c19d1205 ZW |
21715 | #ifdef OBJ_ELF |
21716 | static int | |
21717 | arm_parse_eabi (char * str) | |
21718 | { | |
e74cfd16 | 21719 | const struct arm_option_value_table *opt; |
cc8a6dd0 | 21720 | |
c19d1205 ZW |
21721 | for (opt = arm_eabis; opt->name != NULL; opt++) |
21722 | if (streq (opt->name, str)) | |
21723 | { | |
21724 | meabi_flags = opt->value; | |
21725 | return 1; | |
21726 | } | |
21727 | as_bad (_("unknown EABI `%s'\n"), str); | |
21728 | return 0; | |
21729 | } | |
21730 | #endif | |
cc8a6dd0 | 21731 | |
e07e6e58 NC |
21732 | static int |
21733 | arm_parse_it_mode (char * str) | |
21734 | { | |
21735 | int ret = 1; | |
21736 | ||
21737 | if (streq ("arm", str)) | |
21738 | implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
21739 | else if (streq ("thumb", str)) | |
21740 | implicit_it_mode = IMPLICIT_IT_MODE_THUMB; | |
21741 | else if (streq ("always", str)) | |
21742 | implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS; | |
21743 | else if (streq ("never", str)) | |
21744 | implicit_it_mode = IMPLICIT_IT_MODE_NEVER; | |
21745 | else | |
21746 | { | |
21747 | as_bad (_("unknown implicit IT mode `%s', should be "\ | |
21748 | "arm, thumb, always, or never."), str); | |
21749 | ret = 0; | |
21750 | } | |
21751 | ||
21752 | return ret; | |
21753 | } | |
21754 | ||
c19d1205 ZW |
21755 | struct arm_long_option_table arm_long_opts[] = |
21756 | { | |
21757 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
21758 | arm_parse_cpu, NULL}, | |
21759 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
21760 | arm_parse_arch, NULL}, | |
21761 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
21762 | arm_parse_fpu, NULL}, | |
21763 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
21764 | arm_parse_float_abi, NULL}, | |
21765 | #ifdef OBJ_ELF | |
7fac0536 | 21766 | {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"), |
c19d1205 ZW |
21767 | arm_parse_eabi, NULL}, |
21768 | #endif | |
e07e6e58 NC |
21769 | {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"), |
21770 | arm_parse_it_mode, NULL}, | |
c19d1205 ZW |
21771 | {NULL, NULL, 0, NULL} |
21772 | }; | |
cc8a6dd0 | 21773 | |
c19d1205 ZW |
21774 | int |
21775 | md_parse_option (int c, char * arg) | |
21776 | { | |
21777 | struct arm_option_table *opt; | |
e74cfd16 | 21778 | const struct arm_legacy_option_table *fopt; |
c19d1205 | 21779 | struct arm_long_option_table *lopt; |
b99bd4ef | 21780 | |
c19d1205 | 21781 | switch (c) |
b99bd4ef | 21782 | { |
c19d1205 ZW |
21783 | #ifdef OPTION_EB |
21784 | case OPTION_EB: | |
21785 | target_big_endian = 1; | |
21786 | break; | |
21787 | #endif | |
cc8a6dd0 | 21788 | |
c19d1205 ZW |
21789 | #ifdef OPTION_EL |
21790 | case OPTION_EL: | |
21791 | target_big_endian = 0; | |
21792 | break; | |
21793 | #endif | |
b99bd4ef | 21794 | |
845b51d6 PB |
21795 | case OPTION_FIX_V4BX: |
21796 | fix_v4bx = TRUE; | |
21797 | break; | |
21798 | ||
c19d1205 ZW |
21799 | case 'a': |
21800 | /* Listing option. Just ignore these, we don't support additional | |
21801 | ones. */ | |
21802 | return 0; | |
b99bd4ef | 21803 | |
c19d1205 ZW |
21804 | default: |
21805 | for (opt = arm_opts; opt->option != NULL; opt++) | |
21806 | { | |
21807 | if (c == opt->option[0] | |
21808 | && ((arg == NULL && opt->option[1] == 0) | |
21809 | || streq (arg, opt->option + 1))) | |
21810 | { | |
c19d1205 | 21811 | /* If the option is deprecated, tell the user. */ |
278df34e | 21812 | if (warn_on_deprecated && opt->deprecated != NULL) |
c19d1205 ZW |
21813 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
21814 | arg ? arg : "", _(opt->deprecated)); | |
b99bd4ef | 21815 | |
c19d1205 ZW |
21816 | if (opt->var != NULL) |
21817 | *opt->var = opt->value; | |
cc8a6dd0 | 21818 | |
c19d1205 ZW |
21819 | return 1; |
21820 | } | |
21821 | } | |
b99bd4ef | 21822 | |
e74cfd16 PB |
21823 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
21824 | { | |
21825 | if (c == fopt->option[0] | |
21826 | && ((arg == NULL && fopt->option[1] == 0) | |
21827 | || streq (arg, fopt->option + 1))) | |
21828 | { | |
e74cfd16 | 21829 | /* If the option is deprecated, tell the user. */ |
278df34e | 21830 | if (warn_on_deprecated && fopt->deprecated != NULL) |
e74cfd16 PB |
21831 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
21832 | arg ? arg : "", _(fopt->deprecated)); | |
e74cfd16 PB |
21833 | |
21834 | if (fopt->var != NULL) | |
21835 | *fopt->var = &fopt->value; | |
21836 | ||
21837 | return 1; | |
21838 | } | |
21839 | } | |
21840 | ||
c19d1205 ZW |
21841 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
21842 | { | |
21843 | /* These options are expected to have an argument. */ | |
21844 | if (c == lopt->option[0] | |
21845 | && arg != NULL | |
21846 | && strncmp (arg, lopt->option + 1, | |
21847 | strlen (lopt->option + 1)) == 0) | |
21848 | { | |
c19d1205 | 21849 | /* If the option is deprecated, tell the user. */ |
278df34e | 21850 | if (warn_on_deprecated && lopt->deprecated != NULL) |
c19d1205 ZW |
21851 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, |
21852 | _(lopt->deprecated)); | |
b99bd4ef | 21853 | |
c19d1205 ZW |
21854 | /* Call the sup-option parser. */ |
21855 | return lopt->func (arg + strlen (lopt->option) - 1); | |
21856 | } | |
21857 | } | |
a737bd4d | 21858 | |
c19d1205 ZW |
21859 | return 0; |
21860 | } | |
a394c00f | 21861 | |
c19d1205 ZW |
21862 | return 1; |
21863 | } | |
a394c00f | 21864 | |
c19d1205 ZW |
21865 | void |
21866 | md_show_usage (FILE * fp) | |
a394c00f | 21867 | { |
c19d1205 ZW |
21868 | struct arm_option_table *opt; |
21869 | struct arm_long_option_table *lopt; | |
a394c00f | 21870 | |
c19d1205 | 21871 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 21872 | |
c19d1205 ZW |
21873 | for (opt = arm_opts; opt->option != NULL; opt++) |
21874 | if (opt->help != NULL) | |
21875 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 21876 | |
c19d1205 ZW |
21877 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
21878 | if (lopt->help != NULL) | |
21879 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 21880 | |
c19d1205 ZW |
21881 | #ifdef OPTION_EB |
21882 | fprintf (fp, _("\ | |
21883 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
21884 | #endif |
21885 | ||
c19d1205 ZW |
21886 | #ifdef OPTION_EL |
21887 | fprintf (fp, _("\ | |
21888 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 21889 | #endif |
845b51d6 PB |
21890 | |
21891 | fprintf (fp, _("\ | |
21892 | --fix-v4bx Allow BX in ARMv4 code\n")); | |
c19d1205 | 21893 | } |
ee065d83 PB |
21894 | |
21895 | ||
21896 | #ifdef OBJ_ELF | |
62b3e311 PB |
21897 | typedef struct |
21898 | { | |
21899 | int val; | |
21900 | arm_feature_set flags; | |
21901 | } cpu_arch_ver_table; | |
21902 | ||
21903 | /* Mapping from CPU features to EABI CPU arch values. Table must be sorted | |
21904 | least features first. */ | |
21905 | static const cpu_arch_ver_table cpu_arch_ver[] = | |
21906 | { | |
21907 | {1, ARM_ARCH_V4}, | |
21908 | {2, ARM_ARCH_V4T}, | |
21909 | {3, ARM_ARCH_V5}, | |
ee3c0378 | 21910 | {3, ARM_ARCH_V5T}, |
62b3e311 PB |
21911 | {4, ARM_ARCH_V5TE}, |
21912 | {5, ARM_ARCH_V5TEJ}, | |
21913 | {6, ARM_ARCH_V6}, | |
21914 | {7, ARM_ARCH_V6Z}, | |
7e806470 | 21915 | {9, ARM_ARCH_V6K}, |
91e22acd | 21916 | {11, ARM_ARCH_V6M}, |
7e806470 | 21917 | {8, ARM_ARCH_V6T2}, |
62b3e311 PB |
21918 | {10, ARM_ARCH_V7A}, |
21919 | {10, ARM_ARCH_V7R}, | |
21920 | {10, ARM_ARCH_V7M}, | |
21921 | {0, ARM_ARCH_NONE} | |
21922 | }; | |
21923 | ||
ee3c0378 AS |
21924 | /* Set an attribute if it has not already been set by the user. */ |
21925 | static void | |
21926 | aeabi_set_attribute_int (int tag, int value) | |
21927 | { | |
21928 | if (tag < 1 | |
21929 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
21930 | || !attributes_set_explicitly[tag]) | |
21931 | bfd_elf_add_proc_attr_int (stdoutput, tag, value); | |
21932 | } | |
21933 | ||
21934 | static void | |
21935 | aeabi_set_attribute_string (int tag, const char *value) | |
21936 | { | |
21937 | if (tag < 1 | |
21938 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
21939 | || !attributes_set_explicitly[tag]) | |
21940 | bfd_elf_add_proc_attr_string (stdoutput, tag, value); | |
21941 | } | |
21942 | ||
ee065d83 PB |
21943 | /* Set the public EABI object attributes. */ |
21944 | static void | |
21945 | aeabi_set_public_attributes (void) | |
21946 | { | |
21947 | int arch; | |
e74cfd16 | 21948 | arm_feature_set flags; |
62b3e311 PB |
21949 | arm_feature_set tmp; |
21950 | const cpu_arch_ver_table *p; | |
ee065d83 PB |
21951 | |
21952 | /* Choose the architecture based on the capabilities of the requested cpu | |
21953 | (if any) and/or the instructions actually used. */ | |
e74cfd16 PB |
21954 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); |
21955 | ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); | |
21956 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); | |
7a1d4c38 PB |
21957 | /*Allow the user to override the reported architecture. */ |
21958 | if (object_arch) | |
21959 | { | |
21960 | ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); | |
21961 | ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); | |
21962 | } | |
21963 | ||
62b3e311 PB |
21964 | tmp = flags; |
21965 | arch = 0; | |
21966 | for (p = cpu_arch_ver; p->val; p++) | |
21967 | { | |
21968 | if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) | |
21969 | { | |
21970 | arch = p->val; | |
21971 | ARM_CLEAR_FEATURE (tmp, tmp, p->flags); | |
21972 | } | |
21973 | } | |
ee065d83 PB |
21974 | |
21975 | /* Tag_CPU_name. */ | |
21976 | if (selected_cpu_name[0]) | |
21977 | { | |
21978 | char *p; | |
21979 | ||
21980 | p = selected_cpu_name; | |
5f4273c7 | 21981 | if (strncmp (p, "armv", 4) == 0) |
ee065d83 PB |
21982 | { |
21983 | int i; | |
5f4273c7 | 21984 | |
ee065d83 PB |
21985 | p += 4; |
21986 | for (i = 0; p[i]; i++) | |
21987 | p[i] = TOUPPER (p[i]); | |
21988 | } | |
ee3c0378 | 21989 | aeabi_set_attribute_string (Tag_CPU_name, p); |
ee065d83 PB |
21990 | } |
21991 | /* Tag_CPU_arch. */ | |
ee3c0378 | 21992 | aeabi_set_attribute_int (Tag_CPU_arch, arch); |
62b3e311 PB |
21993 | /* Tag_CPU_arch_profile. */ |
21994 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) | |
ee3c0378 | 21995 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'A'); |
62b3e311 | 21996 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) |
ee3c0378 | 21997 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'R'); |
7e806470 | 21998 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m)) |
ee3c0378 | 21999 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'M'); |
ee065d83 | 22000 | /* Tag_ARM_ISA_use. */ |
ee3c0378 AS |
22001 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) |
22002 | || arch == 0) | |
22003 | aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); | |
ee065d83 | 22004 | /* Tag_THUMB_ISA_use. */ |
ee3c0378 AS |
22005 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) |
22006 | || arch == 0) | |
22007 | aeabi_set_attribute_int (Tag_THUMB_ISA_use, | |
22008 | ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1); | |
ee065d83 | 22009 | /* Tag_VFP_arch. */ |
ee3c0378 AS |
22010 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) |
22011 | aeabi_set_attribute_int (Tag_VFP_arch, 3); | |
22012 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3)) | |
22013 | aeabi_set_attribute_int (Tag_VFP_arch, 4); | |
22014 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) | |
22015 | aeabi_set_attribute_int (Tag_VFP_arch, 2); | |
22016 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) | |
22017 | || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)) | |
22018 | aeabi_set_attribute_int (Tag_VFP_arch, 1); | |
ee065d83 | 22019 | /* Tag_WMMX_arch. */ |
ee3c0378 AS |
22020 | if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2)) |
22021 | aeabi_set_attribute_int (Tag_WMMX_arch, 2); | |
22022 | else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt)) | |
22023 | aeabi_set_attribute_int (Tag_WMMX_arch, 1); | |
22024 | /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ | |
8e79c3df | 22025 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) |
ee3c0378 AS |
22026 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1); |
22027 | /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ | |
8e79c3df | 22028 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_fp16)) |
ee3c0378 | 22029 | aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); |
ee065d83 PB |
22030 | } |
22031 | ||
104d59d1 | 22032 | /* Add the default contents for the .ARM.attributes section. */ |
ee065d83 PB |
22033 | void |
22034 | arm_md_end (void) | |
22035 | { | |
ee065d83 PB |
22036 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
22037 | return; | |
22038 | ||
22039 | aeabi_set_public_attributes (); | |
ee065d83 | 22040 | } |
8463be01 | 22041 | #endif /* OBJ_ELF */ |
ee065d83 PB |
22042 | |
22043 | ||
22044 | /* Parse a .cpu directive. */ | |
22045 | ||
22046 | static void | |
22047 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) | |
22048 | { | |
e74cfd16 | 22049 | const struct arm_cpu_option_table *opt; |
ee065d83 PB |
22050 | char *name; |
22051 | char saved_char; | |
22052 | ||
22053 | name = input_line_pointer; | |
5f4273c7 | 22054 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
22055 | input_line_pointer++; |
22056 | saved_char = *input_line_pointer; | |
22057 | *input_line_pointer = 0; | |
22058 | ||
22059 | /* Skip the first "all" entry. */ | |
22060 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) | |
22061 | if (streq (opt->name, name)) | |
22062 | { | |
e74cfd16 PB |
22063 | mcpu_cpu_opt = &opt->value; |
22064 | selected_cpu = opt->value; | |
ee065d83 | 22065 | if (opt->canonical_name) |
5f4273c7 | 22066 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
22067 | else |
22068 | { | |
22069 | int i; | |
22070 | for (i = 0; opt->name[i]; i++) | |
22071 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
22072 | selected_cpu_name[i] = 0; | |
22073 | } | |
e74cfd16 | 22074 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
22075 | *input_line_pointer = saved_char; |
22076 | demand_empty_rest_of_line (); | |
22077 | return; | |
22078 | } | |
22079 | as_bad (_("unknown cpu `%s'"), name); | |
22080 | *input_line_pointer = saved_char; | |
22081 | ignore_rest_of_line (); | |
22082 | } | |
22083 | ||
22084 | ||
22085 | /* Parse a .arch directive. */ | |
22086 | ||
22087 | static void | |
22088 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) | |
22089 | { | |
e74cfd16 | 22090 | const struct arm_arch_option_table *opt; |
ee065d83 PB |
22091 | char saved_char; |
22092 | char *name; | |
22093 | ||
22094 | name = input_line_pointer; | |
5f4273c7 | 22095 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
22096 | input_line_pointer++; |
22097 | saved_char = *input_line_pointer; | |
22098 | *input_line_pointer = 0; | |
22099 | ||
22100 | /* Skip the first "all" entry. */ | |
22101 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
22102 | if (streq (opt->name, name)) | |
22103 | { | |
e74cfd16 PB |
22104 | mcpu_cpu_opt = &opt->value; |
22105 | selected_cpu = opt->value; | |
5f4273c7 | 22106 | strcpy (selected_cpu_name, opt->name); |
e74cfd16 | 22107 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
22108 | *input_line_pointer = saved_char; |
22109 | demand_empty_rest_of_line (); | |
22110 | return; | |
22111 | } | |
22112 | ||
22113 | as_bad (_("unknown architecture `%s'\n"), name); | |
22114 | *input_line_pointer = saved_char; | |
22115 | ignore_rest_of_line (); | |
22116 | } | |
22117 | ||
22118 | ||
7a1d4c38 PB |
22119 | /* Parse a .object_arch directive. */ |
22120 | ||
22121 | static void | |
22122 | s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) | |
22123 | { | |
22124 | const struct arm_arch_option_table *opt; | |
22125 | char saved_char; | |
22126 | char *name; | |
22127 | ||
22128 | name = input_line_pointer; | |
5f4273c7 | 22129 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
7a1d4c38 PB |
22130 | input_line_pointer++; |
22131 | saved_char = *input_line_pointer; | |
22132 | *input_line_pointer = 0; | |
22133 | ||
22134 | /* Skip the first "all" entry. */ | |
22135 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
22136 | if (streq (opt->name, name)) | |
22137 | { | |
22138 | object_arch = &opt->value; | |
22139 | *input_line_pointer = saved_char; | |
22140 | demand_empty_rest_of_line (); | |
22141 | return; | |
22142 | } | |
22143 | ||
22144 | as_bad (_("unknown architecture `%s'\n"), name); | |
22145 | *input_line_pointer = saved_char; | |
22146 | ignore_rest_of_line (); | |
22147 | } | |
22148 | ||
ee065d83 PB |
22149 | /* Parse a .fpu directive. */ |
22150 | ||
22151 | static void | |
22152 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) | |
22153 | { | |
e74cfd16 | 22154 | const struct arm_option_cpu_value_table *opt; |
ee065d83 PB |
22155 | char saved_char; |
22156 | char *name; | |
22157 | ||
22158 | name = input_line_pointer; | |
5f4273c7 | 22159 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
22160 | input_line_pointer++; |
22161 | saved_char = *input_line_pointer; | |
22162 | *input_line_pointer = 0; | |
5f4273c7 | 22163 | |
ee065d83 PB |
22164 | for (opt = arm_fpus; opt->name != NULL; opt++) |
22165 | if (streq (opt->name, name)) | |
22166 | { | |
e74cfd16 PB |
22167 | mfpu_opt = &opt->value; |
22168 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
ee065d83 PB |
22169 | *input_line_pointer = saved_char; |
22170 | demand_empty_rest_of_line (); | |
22171 | return; | |
22172 | } | |
22173 | ||
22174 | as_bad (_("unknown floating point format `%s'\n"), name); | |
22175 | *input_line_pointer = saved_char; | |
22176 | ignore_rest_of_line (); | |
22177 | } | |
ee065d83 | 22178 | |
794ba86a | 22179 | /* Copy symbol information. */ |
f31fef98 | 22180 | |
794ba86a DJ |
22181 | void |
22182 | arm_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
22183 | { | |
22184 | ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); | |
22185 | } | |
e04befd0 | 22186 | |
f31fef98 | 22187 | #ifdef OBJ_ELF |
e04befd0 AS |
22188 | /* Given a symbolic attribute NAME, return the proper integer value. |
22189 | Returns -1 if the attribute is not known. */ | |
f31fef98 | 22190 | |
e04befd0 AS |
22191 | int |
22192 | arm_convert_symbolic_attribute (const char *name) | |
22193 | { | |
f31fef98 NC |
22194 | static const struct |
22195 | { | |
22196 | const char * name; | |
22197 | const int tag; | |
22198 | } | |
22199 | attribute_table[] = | |
22200 | { | |
22201 | /* When you modify this table you should | |
22202 | also modify the list in doc/c-arm.texi. */ | |
e04befd0 | 22203 | #define T(tag) {#tag, tag} |
f31fef98 NC |
22204 | T (Tag_CPU_raw_name), |
22205 | T (Tag_CPU_name), | |
22206 | T (Tag_CPU_arch), | |
22207 | T (Tag_CPU_arch_profile), | |
22208 | T (Tag_ARM_ISA_use), | |
22209 | T (Tag_THUMB_ISA_use), | |
22210 | T (Tag_VFP_arch), | |
22211 | T (Tag_WMMX_arch), | |
22212 | T (Tag_Advanced_SIMD_arch), | |
22213 | T (Tag_PCS_config), | |
22214 | T (Tag_ABI_PCS_R9_use), | |
22215 | T (Tag_ABI_PCS_RW_data), | |
22216 | T (Tag_ABI_PCS_RO_data), | |
22217 | T (Tag_ABI_PCS_GOT_use), | |
22218 | T (Tag_ABI_PCS_wchar_t), | |
22219 | T (Tag_ABI_FP_rounding), | |
22220 | T (Tag_ABI_FP_denormal), | |
22221 | T (Tag_ABI_FP_exceptions), | |
22222 | T (Tag_ABI_FP_user_exceptions), | |
22223 | T (Tag_ABI_FP_number_model), | |
22224 | T (Tag_ABI_align8_needed), | |
22225 | T (Tag_ABI_align8_preserved), | |
22226 | T (Tag_ABI_enum_size), | |
22227 | T (Tag_ABI_HardFP_use), | |
22228 | T (Tag_ABI_VFP_args), | |
22229 | T (Tag_ABI_WMMX_args), | |
22230 | T (Tag_ABI_optimization_goals), | |
22231 | T (Tag_ABI_FP_optimization_goals), | |
22232 | T (Tag_compatibility), | |
22233 | T (Tag_CPU_unaligned_access), | |
22234 | T (Tag_VFP_HP_extension), | |
22235 | T (Tag_ABI_FP_16bit_format), | |
22236 | T (Tag_nodefaults), | |
22237 | T (Tag_also_compatible_with), | |
22238 | T (Tag_conformance), | |
22239 | T (Tag_T2EE_use), | |
22240 | T (Tag_Virtualization_use), | |
22241 | T (Tag_MPextension_use) | |
e04befd0 | 22242 | #undef T |
f31fef98 | 22243 | }; |
e04befd0 AS |
22244 | unsigned int i; |
22245 | ||
22246 | if (name == NULL) | |
22247 | return -1; | |
22248 | ||
f31fef98 | 22249 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
e04befd0 AS |
22250 | if (strcmp (name, attribute_table[i].name) == 0) |
22251 | return attribute_table[i].tag; | |
22252 | ||
22253 | return -1; | |
22254 | } | |
267bf995 RR |
22255 | |
22256 | ||
22257 | /* Apply sym value for relocations only in the case that | |
22258 | they are for local symbols and you have the respective | |
22259 | architectural feature for blx and simple switches. */ | |
22260 | int | |
22261 | arm_apply_sym_value (struct fix * fixP) | |
22262 | { | |
22263 | if (fixP->fx_addsy | |
22264 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
22265 | && !S_IS_EXTERNAL (fixP->fx_addsy)) | |
22266 | { | |
22267 | switch (fixP->fx_r_type) | |
22268 | { | |
22269 | case BFD_RELOC_ARM_PCREL_BLX: | |
22270 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
22271 | if (ARM_IS_FUNC (fixP->fx_addsy)) | |
22272 | return 1; | |
22273 | break; | |
22274 | ||
22275 | case BFD_RELOC_ARM_PCREL_CALL: | |
22276 | case BFD_RELOC_THUMB_PCREL_BLX: | |
22277 | if (THUMB_IS_FUNC (fixP->fx_addsy)) | |
22278 | return 1; | |
22279 | break; | |
22280 | ||
22281 | default: | |
22282 | break; | |
22283 | } | |
22284 | ||
22285 | } | |
22286 | return 0; | |
22287 | } | |
f31fef98 | 22288 | #endif /* OBJ_ELF */ |
267bf995 RR |
22289 | |
22290 |