* config/obj-evax.h (S_SET_OTHER, S_SET_TYPE, S_SET_DESC): Don't define.
[deliverable/binutils-gdb.git] / gas / config / tc-arm.c
CommitLineData
b99bd4ef 1/* tc-arm.c -- Assemble for the ARM
f17c130b 2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
b43420e6 3 2004, 2005, 2006, 2007, 2008, 2009, 2010
b99bd4ef
NC
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
22d9c8c5 7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
34920d91
NC
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
b99bd4ef
NC
10
11 This file is part of GAS, the GNU Assembler.
12
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
ec2655a6 15 the Free Software Foundation; either version 3, or (at your option)
b99bd4ef
NC
16 any later version.
17
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
c19d1205 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
b99bd4ef
NC
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
699d2810
NC
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
26 02110-1301, USA. */
b99bd4ef 27
42a68e18 28#include "as.h"
5287ad62 29#include <limits.h>
037e8744 30#include <stdarg.h>
c19d1205 31#define NO_RELOC 0
3882b010 32#include "safe-ctype.h"
b99bd4ef
NC
33#include "subsegs.h"
34#include "obstack.h"
b99bd4ef 35
f263249b
RE
36#include "opcode/arm.h"
37
b99bd4ef
NC
38#ifdef OBJ_ELF
39#include "elf/arm.h"
a394c00f 40#include "dw2gencfi.h"
b99bd4ef
NC
41#endif
42
f0927246
NC
43#include "dwarf2dbg.h"
44
7ed4c4c5
NC
45#ifdef OBJ_ELF
46/* Must be at least the size of the largest unwind opcode (currently two). */
47#define ARM_OPCODE_CHUNK_SIZE 8
48
49/* This structure holds the unwinding state. */
50
51static struct
52{
c19d1205
ZW
53 symbolS * proc_start;
54 symbolS * table_entry;
55 symbolS * personality_routine;
56 int personality_index;
7ed4c4c5 57 /* The segment containing the function. */
c19d1205
ZW
58 segT saved_seg;
59 subsegT saved_subseg;
7ed4c4c5
NC
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes;
c19d1205
ZW
62 int opcode_count;
63 int opcode_alloc;
7ed4c4c5 64 /* The number of bytes pushed to the stack. */
c19d1205 65 offsetT frame_size;
7ed4c4c5
NC
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
c19d1205 69 offsetT pending_offset;
7ed4c4c5 70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
c19d1205
ZW
71 hold the reg+offset to use when restoring sp from a frame pointer. */
72 offsetT fp_offset;
73 int fp_reg;
7ed4c4c5 74 /* Nonzero if an unwind_setfp directive has been seen. */
c19d1205 75 unsigned fp_used:1;
7ed4c4c5 76 /* Nonzero if the last opcode restores sp from fp_reg. */
c19d1205 77 unsigned sp_restored:1;
7ed4c4c5
NC
78} unwind;
79
8b1ad454
NC
80#endif /* OBJ_ELF */
81
4962c51a
MS
82/* Results from operand parsing worker functions. */
83
84typedef enum
85{
86 PARSE_OPERAND_SUCCESS,
87 PARSE_OPERAND_FAIL,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89} parse_operand_result;
90
33a392fb
PB
91enum arm_float_abi
92{
93 ARM_FLOAT_ABI_HARD,
94 ARM_FLOAT_ABI_SOFTFP,
95 ARM_FLOAT_ABI_SOFT
96};
97
c19d1205 98/* Types of processor to assemble for. */
b99bd4ef 99#ifndef CPU_DEFAULT
8a59fff3
MGD
100/* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
103
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
b99bd4ef
NC
106#endif
107
108#ifndef FPU_DEFAULT
c820d418
MM
109# ifdef TE_LINUX
110# define FPU_DEFAULT FPU_ARCH_FPA
111# elif defined (TE_NetBSD)
112# ifdef OBJ_ELF
113# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
114# else
115 /* Legacy a.out format. */
116# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
117# endif
4e7fd91e
PB
118# elif defined (TE_VXWORKS)
119# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
c820d418
MM
120# else
121 /* For backwards compatibility, default to FPA. */
122# define FPU_DEFAULT FPU_ARCH_FPA
123# endif
124#endif /* ifndef FPU_DEFAULT */
b99bd4ef 125
c19d1205 126#define streq(a, b) (strcmp (a, b) == 0)
b99bd4ef 127
e74cfd16
PB
128static arm_feature_set cpu_variant;
129static arm_feature_set arm_arch_used;
130static arm_feature_set thumb_arch_used;
b99bd4ef 131
b99bd4ef 132/* Flags stored in private area of BFD structure. */
c19d1205
ZW
133static int uses_apcs_26 = FALSE;
134static int atpcs = FALSE;
b34976b6
AM
135static int support_interwork = FALSE;
136static int uses_apcs_float = FALSE;
c19d1205 137static int pic_code = FALSE;
845b51d6 138static int fix_v4bx = FALSE;
278df34e
NS
139/* Warn on using deprecated features. */
140static int warn_on_deprecated = TRUE;
141
03b1477f
RE
142
143/* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
145 assembly flags. */
e74cfd16
PB
146static const arm_feature_set *legacy_cpu = NULL;
147static const arm_feature_set *legacy_fpu = NULL;
148
149static const arm_feature_set *mcpu_cpu_opt = NULL;
150static const arm_feature_set *mcpu_fpu_opt = NULL;
151static const arm_feature_set *march_cpu_opt = NULL;
152static const arm_feature_set *march_fpu_opt = NULL;
153static const arm_feature_set *mfpu_opt = NULL;
7a1d4c38 154static const arm_feature_set *object_arch = NULL;
e74cfd16
PB
155
156/* Constants for known architecture features. */
157static const arm_feature_set fpu_default = FPU_DEFAULT;
158static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
5287ad62
JB
160static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
e74cfd16
PB
162static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
166
167#ifdef CPU_DEFAULT
168static const arm_feature_set cpu_default = CPU_DEFAULT;
169#endif
170
171static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
172static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
173static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
174static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
175static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
176static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
177static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
178static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
179static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
181static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
182static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
183static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
184static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
185static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
186static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
187static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0);
188static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
62b3e311 189static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
9e3c6df6 190static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
7e806470
PB
191static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
192static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
62b3e311
PB
193static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
194static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
195static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
196static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
9e3c6df6 197static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
7e806470
PB
198static const arm_feature_set arm_ext_m =
199 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_V7M, 0);
e74cfd16
PB
200
201static const arm_feature_set arm_arch_any = ARM_ANY;
202static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
203static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
204static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
205
2d447fca
JM
206static const arm_feature_set arm_cext_iwmmxt2 =
207 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
e74cfd16
PB
208static const arm_feature_set arm_cext_iwmmxt =
209 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
210static const arm_feature_set arm_cext_xscale =
211 ARM_FEATURE (0, ARM_CEXT_XSCALE);
212static const arm_feature_set arm_cext_maverick =
213 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
214static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
215static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
216static const arm_feature_set fpu_vfp_ext_v1xd =
217 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
218static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
219static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
62f3b8c8 220static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
5287ad62 221static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
b1cc4aeb
PB
222static const arm_feature_set fpu_vfp_ext_d32 =
223 ARM_FEATURE (0, FPU_VFP_EXT_D32);
5287ad62
JB
224static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
225static const arm_feature_set fpu_vfp_v3_or_neon_ext =
226 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
62f3b8c8
PB
227static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
228static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
229static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
e74cfd16 230
33a392fb 231static int mfloat_abi_opt = -1;
e74cfd16
PB
232/* Record user cpu selection for object attributes. */
233static arm_feature_set selected_cpu = ARM_ARCH_NONE;
ee065d83
PB
234/* Must be long enough to hold any of the names in arm_cpus. */
235static char selected_cpu_name[16];
7cc69913 236#ifdef OBJ_ELF
deeaaff8
DJ
237# ifdef EABI_DEFAULT
238static int meabi_flags = EABI_DEFAULT;
239# else
d507cf36 240static int meabi_flags = EF_ARM_EABI_UNKNOWN;
deeaaff8 241# endif
e1da3f5b 242
ee3c0378
AS
243static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
244
e1da3f5b 245bfd_boolean
5f4273c7 246arm_is_eabi (void)
e1da3f5b
PB
247{
248 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
249}
7cc69913 250#endif
b99bd4ef 251
b99bd4ef 252#ifdef OBJ_ELF
c19d1205 253/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
b99bd4ef
NC
254symbolS * GOT_symbol;
255#endif
256
b99bd4ef
NC
257/* 0: assemble for ARM,
258 1: assemble for Thumb,
259 2: assemble for Thumb even though target CPU does not support thumb
260 instructions. */
261static int thumb_mode = 0;
8dc2430f
NC
262/* A value distinct from the possible values for thumb_mode that we
263 can use to record whether thumb_mode has been copied into the
264 tc_frag_data field of a frag. */
265#define MODE_RECORDED (1 << 4)
b99bd4ef 266
e07e6e58
NC
267/* Specifies the intrinsic IT insn behavior mode. */
268enum implicit_it_mode
269{
270 IMPLICIT_IT_MODE_NEVER = 0x00,
271 IMPLICIT_IT_MODE_ARM = 0x01,
272 IMPLICIT_IT_MODE_THUMB = 0x02,
273 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
274};
275static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
276
c19d1205
ZW
277/* If unified_syntax is true, we are processing the new unified
278 ARM/Thumb syntax. Important differences from the old ARM mode:
279
280 - Immediate operands do not require a # prefix.
281 - Conditional affixes always appear at the end of the
282 instruction. (For backward compatibility, those instructions
283 that formerly had them in the middle, continue to accept them
284 there.)
285 - The IT instruction may appear, and if it does is validated
286 against subsequent conditional affixes. It does not generate
287 machine code.
288
289 Important differences from the old Thumb mode:
290
291 - Immediate operands do not require a # prefix.
292 - Most of the V6T2 instructions are only available in unified mode.
293 - The .N and .W suffixes are recognized and honored (it is an error
294 if they cannot be honored).
295 - All instructions set the flags if and only if they have an 's' affix.
296 - Conditional affixes may be used. They are validated against
297 preceding IT instructions. Unlike ARM mode, you cannot use a
298 conditional affix except in the scope of an IT instruction. */
299
300static bfd_boolean unified_syntax = FALSE;
b99bd4ef 301
5287ad62
JB
302enum neon_el_type
303{
dcbf9037 304 NT_invtype,
5287ad62
JB
305 NT_untyped,
306 NT_integer,
307 NT_float,
308 NT_poly,
309 NT_signed,
dcbf9037 310 NT_unsigned
5287ad62
JB
311};
312
313struct neon_type_el
314{
315 enum neon_el_type type;
316 unsigned size;
317};
318
319#define NEON_MAX_TYPE_ELS 4
320
321struct neon_type
322{
323 struct neon_type_el el[NEON_MAX_TYPE_ELS];
324 unsigned elems;
325};
326
e07e6e58
NC
327enum it_instruction_type
328{
329 OUTSIDE_IT_INSN,
330 INSIDE_IT_INSN,
331 INSIDE_IT_LAST_INSN,
332 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
333 if inside, should be the last one. */
334 NEUTRAL_IT_INSN, /* This could be either inside or outside,
335 i.e. BKPT and NOP. */
336 IT_INSN /* The IT insn has been parsed. */
337};
338
b99bd4ef
NC
339struct arm_it
340{
c19d1205 341 const char * error;
b99bd4ef 342 unsigned long instruction;
c19d1205
ZW
343 int size;
344 int size_req;
345 int cond;
037e8744
JB
346 /* "uncond_value" is set to the value in place of the conditional field in
347 unconditional versions of the instruction, or -1 if nothing is
348 appropriate. */
349 int uncond_value;
5287ad62 350 struct neon_type vectype;
88714cb8
DG
351 /* This does not indicate an actual NEON instruction, only that
352 the mnemonic accepts neon-style type suffixes. */
353 int is_neon;
0110f2b8
PB
354 /* Set to the opcode if the instruction needs relaxation.
355 Zero if the instruction is not relaxed. */
356 unsigned long relax;
b99bd4ef
NC
357 struct
358 {
359 bfd_reloc_code_real_type type;
c19d1205
ZW
360 expressionS exp;
361 int pc_rel;
b99bd4ef 362 } reloc;
b99bd4ef 363
e07e6e58
NC
364 enum it_instruction_type it_insn_type;
365
c19d1205
ZW
366 struct
367 {
368 unsigned reg;
ca3f61f7 369 signed int imm;
dcbf9037 370 struct neon_type_el vectype;
ca3f61f7
NC
371 unsigned present : 1; /* Operand present. */
372 unsigned isreg : 1; /* Operand was a register. */
373 unsigned immisreg : 1; /* .imm field is a second register. */
5287ad62
JB
374 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
375 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
c96612cc 376 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
5287ad62
JB
377 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
378 instructions. This allows us to disambiguate ARM <-> vector insns. */
379 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
037e8744 380 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
5287ad62 381 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
037e8744 382 unsigned issingle : 1; /* Operand is VFP single-precision register. */
ca3f61f7
NC
383 unsigned hasreloc : 1; /* Operand has relocation suffix. */
384 unsigned writeback : 1; /* Operand has trailing ! */
385 unsigned preind : 1; /* Preindexed address. */
386 unsigned postind : 1; /* Postindexed address. */
387 unsigned negative : 1; /* Index register was negated. */
388 unsigned shifted : 1; /* Shift applied to operation. */
389 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
c19d1205 390 } operands[6];
b99bd4ef
NC
391};
392
c19d1205 393static struct arm_it inst;
b99bd4ef
NC
394
395#define NUM_FLOAT_VALS 8
396
05d2d07e 397const char * fp_const[] =
b99bd4ef
NC
398{
399 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
400};
401
c19d1205 402/* Number of littlenums required to hold an extended precision number. */
b99bd4ef
NC
403#define MAX_LITTLENUMS 6
404
405LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
406
407#define FAIL (-1)
408#define SUCCESS (0)
409
410#define SUFF_S 1
411#define SUFF_D 2
412#define SUFF_E 3
413#define SUFF_P 4
414
c19d1205
ZW
415#define CP_T_X 0x00008000
416#define CP_T_Y 0x00400000
b99bd4ef 417
c19d1205
ZW
418#define CONDS_BIT 0x00100000
419#define LOAD_BIT 0x00100000
b99bd4ef
NC
420
421#define DOUBLE_LOAD_FLAG 0x00000001
422
423struct asm_cond
424{
d3ce72d0 425 const char * template_name;
c921be7d 426 unsigned long value;
b99bd4ef
NC
427};
428
c19d1205 429#define COND_ALWAYS 0xE
b99bd4ef 430
b99bd4ef
NC
431struct asm_psr
432{
d3ce72d0 433 const char * template_name;
c921be7d 434 unsigned long field;
b99bd4ef
NC
435};
436
62b3e311
PB
437struct asm_barrier_opt
438{
d3ce72d0 439 const char * template_name;
c921be7d 440 unsigned long value;
62b3e311
PB
441};
442
2d2255b5 443/* The bit that distinguishes CPSR and SPSR. */
b99bd4ef
NC
444#define SPSR_BIT (1 << 22)
445
c19d1205
ZW
446/* The individual PSR flag bits. */
447#define PSR_c (1 << 16)
448#define PSR_x (1 << 17)
449#define PSR_s (1 << 18)
450#define PSR_f (1 << 19)
b99bd4ef 451
c19d1205 452struct reloc_entry
bfae80f2 453{
c921be7d
NC
454 char * name;
455 bfd_reloc_code_real_type reloc;
bfae80f2
RE
456};
457
5287ad62 458enum vfp_reg_pos
bfae80f2 459{
5287ad62
JB
460 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
461 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
bfae80f2
RE
462};
463
464enum vfp_ldstm_type
465{
466 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
467};
468
dcbf9037
JB
469/* Bits for DEFINED field in neon_typed_alias. */
470#define NTA_HASTYPE 1
471#define NTA_HASINDEX 2
472
473struct neon_typed_alias
474{
c921be7d
NC
475 unsigned char defined;
476 unsigned char index;
477 struct neon_type_el eltype;
dcbf9037
JB
478};
479
c19d1205
ZW
480/* ARM register categories. This includes coprocessor numbers and various
481 architecture extensions' registers. */
482enum arm_reg_type
bfae80f2 483{
c19d1205
ZW
484 REG_TYPE_RN,
485 REG_TYPE_CP,
486 REG_TYPE_CN,
487 REG_TYPE_FN,
488 REG_TYPE_VFS,
489 REG_TYPE_VFD,
5287ad62 490 REG_TYPE_NQ,
037e8744 491 REG_TYPE_VFSD,
5287ad62 492 REG_TYPE_NDQ,
037e8744 493 REG_TYPE_NSDQ,
c19d1205
ZW
494 REG_TYPE_VFC,
495 REG_TYPE_MVF,
496 REG_TYPE_MVD,
497 REG_TYPE_MVFX,
498 REG_TYPE_MVDX,
499 REG_TYPE_MVAX,
500 REG_TYPE_DSPSC,
501 REG_TYPE_MMXWR,
502 REG_TYPE_MMXWC,
503 REG_TYPE_MMXWCG,
504 REG_TYPE_XSCALE,
bfae80f2
RE
505};
506
dcbf9037
JB
507/* Structure for a hash table entry for a register.
508 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
509 information which states whether a vector type or index is specified (for a
510 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
6c43fab6
RE
511struct reg_entry
512{
c921be7d
NC
513 const char * name;
514 unsigned char number;
515 unsigned char type;
516 unsigned char builtin;
517 struct neon_typed_alias * neon;
6c43fab6
RE
518};
519
c19d1205 520/* Diagnostics used when we don't get a register of the expected type. */
c921be7d 521const char * const reg_expected_msgs[] =
c19d1205
ZW
522{
523 N_("ARM register expected"),
524 N_("bad or missing co-processor number"),
525 N_("co-processor register expected"),
526 N_("FPA register expected"),
527 N_("VFP single precision register expected"),
5287ad62
JB
528 N_("VFP/Neon double precision register expected"),
529 N_("Neon quad precision register expected"),
037e8744 530 N_("VFP single or double precision register expected"),
5287ad62 531 N_("Neon double or quad precision register expected"),
037e8744 532 N_("VFP single, double or Neon quad precision register expected"),
c19d1205
ZW
533 N_("VFP system register expected"),
534 N_("Maverick MVF register expected"),
535 N_("Maverick MVD register expected"),
536 N_("Maverick MVFX register expected"),
537 N_("Maverick MVDX register expected"),
538 N_("Maverick MVAX register expected"),
539 N_("Maverick DSPSC register expected"),
540 N_("iWMMXt data register expected"),
541 N_("iWMMXt control register expected"),
542 N_("iWMMXt scalar register expected"),
543 N_("XScale accumulator register expected"),
6c43fab6
RE
544};
545
c19d1205
ZW
546/* Some well known registers that we refer to directly elsewhere. */
547#define REG_SP 13
548#define REG_LR 14
549#define REG_PC 15
404ff6b5 550
b99bd4ef
NC
551/* ARM instructions take 4bytes in the object file, Thumb instructions
552 take 2: */
c19d1205 553#define INSN_SIZE 4
b99bd4ef
NC
554
555struct asm_opcode
556{
557 /* Basic string to match. */
d3ce72d0 558 const char * template_name;
c19d1205
ZW
559
560 /* Parameters to instruction. */
5be8be5d 561 unsigned int operands[8];
c19d1205
ZW
562
563 /* Conditional tag - see opcode_lookup. */
564 unsigned int tag : 4;
b99bd4ef
NC
565
566 /* Basic instruction code. */
c19d1205 567 unsigned int avalue : 28;
b99bd4ef 568
c19d1205
ZW
569 /* Thumb-format instruction code. */
570 unsigned int tvalue;
b99bd4ef 571
90e4755a 572 /* Which architecture variant provides this instruction. */
c921be7d
NC
573 const arm_feature_set * avariant;
574 const arm_feature_set * tvariant;
c19d1205
ZW
575
576 /* Function to call to encode instruction in ARM format. */
577 void (* aencode) (void);
b99bd4ef 578
c19d1205
ZW
579 /* Function to call to encode instruction in Thumb format. */
580 void (* tencode) (void);
b99bd4ef
NC
581};
582
a737bd4d
NC
583/* Defines for various bits that we will want to toggle. */
584#define INST_IMMEDIATE 0x02000000
585#define OFFSET_REG 0x02000000
c19d1205 586#define HWOFFSET_IMM 0x00400000
a737bd4d
NC
587#define SHIFT_BY_REG 0x00000010
588#define PRE_INDEX 0x01000000
589#define INDEX_UP 0x00800000
590#define WRITE_BACK 0x00200000
591#define LDM_TYPE_2_OR_3 0x00400000
a028a6f5 592#define CPSI_MMOD 0x00020000
90e4755a 593
a737bd4d
NC
594#define LITERAL_MASK 0xf000f000
595#define OPCODE_MASK 0xfe1fffff
596#define V4_STR_BIT 0x00000020
90e4755a 597
efd81785
PB
598#define T2_SUBS_PC_LR 0xf3de8f00
599
a737bd4d 600#define DATA_OP_SHIFT 21
90e4755a 601
ef8d22e6
PB
602#define T2_OPCODE_MASK 0xfe1fffff
603#define T2_DATA_OP_SHIFT 21
604
a737bd4d
NC
605/* Codes to distinguish the arithmetic instructions. */
606#define OPCODE_AND 0
607#define OPCODE_EOR 1
608#define OPCODE_SUB 2
609#define OPCODE_RSB 3
610#define OPCODE_ADD 4
611#define OPCODE_ADC 5
612#define OPCODE_SBC 6
613#define OPCODE_RSC 7
614#define OPCODE_TST 8
615#define OPCODE_TEQ 9
616#define OPCODE_CMP 10
617#define OPCODE_CMN 11
618#define OPCODE_ORR 12
619#define OPCODE_MOV 13
620#define OPCODE_BIC 14
621#define OPCODE_MVN 15
90e4755a 622
ef8d22e6
PB
623#define T2_OPCODE_AND 0
624#define T2_OPCODE_BIC 1
625#define T2_OPCODE_ORR 2
626#define T2_OPCODE_ORN 3
627#define T2_OPCODE_EOR 4
628#define T2_OPCODE_ADD 8
629#define T2_OPCODE_ADC 10
630#define T2_OPCODE_SBC 11
631#define T2_OPCODE_SUB 13
632#define T2_OPCODE_RSB 14
633
a737bd4d
NC
634#define T_OPCODE_MUL 0x4340
635#define T_OPCODE_TST 0x4200
636#define T_OPCODE_CMN 0x42c0
637#define T_OPCODE_NEG 0x4240
638#define T_OPCODE_MVN 0x43c0
90e4755a 639
a737bd4d
NC
640#define T_OPCODE_ADD_R3 0x1800
641#define T_OPCODE_SUB_R3 0x1a00
642#define T_OPCODE_ADD_HI 0x4400
643#define T_OPCODE_ADD_ST 0xb000
644#define T_OPCODE_SUB_ST 0xb080
645#define T_OPCODE_ADD_SP 0xa800
646#define T_OPCODE_ADD_PC 0xa000
647#define T_OPCODE_ADD_I8 0x3000
648#define T_OPCODE_SUB_I8 0x3800
649#define T_OPCODE_ADD_I3 0x1c00
650#define T_OPCODE_SUB_I3 0x1e00
b99bd4ef 651
a737bd4d
NC
652#define T_OPCODE_ASR_R 0x4100
653#define T_OPCODE_LSL_R 0x4080
c19d1205
ZW
654#define T_OPCODE_LSR_R 0x40c0
655#define T_OPCODE_ROR_R 0x41c0
a737bd4d
NC
656#define T_OPCODE_ASR_I 0x1000
657#define T_OPCODE_LSL_I 0x0000
658#define T_OPCODE_LSR_I 0x0800
b99bd4ef 659
a737bd4d
NC
660#define T_OPCODE_MOV_I8 0x2000
661#define T_OPCODE_CMP_I8 0x2800
662#define T_OPCODE_CMP_LR 0x4280
663#define T_OPCODE_MOV_HR 0x4600
664#define T_OPCODE_CMP_HR 0x4500
b99bd4ef 665
a737bd4d
NC
666#define T_OPCODE_LDR_PC 0x4800
667#define T_OPCODE_LDR_SP 0x9800
668#define T_OPCODE_STR_SP 0x9000
669#define T_OPCODE_LDR_IW 0x6800
670#define T_OPCODE_STR_IW 0x6000
671#define T_OPCODE_LDR_IH 0x8800
672#define T_OPCODE_STR_IH 0x8000
673#define T_OPCODE_LDR_IB 0x7800
674#define T_OPCODE_STR_IB 0x7000
675#define T_OPCODE_LDR_RW 0x5800
676#define T_OPCODE_STR_RW 0x5000
677#define T_OPCODE_LDR_RH 0x5a00
678#define T_OPCODE_STR_RH 0x5200
679#define T_OPCODE_LDR_RB 0x5c00
680#define T_OPCODE_STR_RB 0x5400
c9b604bd 681
a737bd4d
NC
682#define T_OPCODE_PUSH 0xb400
683#define T_OPCODE_POP 0xbc00
b99bd4ef 684
2fc8bdac 685#define T_OPCODE_BRANCH 0xe000
b99bd4ef 686
a737bd4d 687#define THUMB_SIZE 2 /* Size of thumb instruction. */
a737bd4d 688#define THUMB_PP_PC_LR 0x0100
c19d1205 689#define THUMB_LOAD_BIT 0x0800
53365c0d 690#define THUMB2_LOAD_BIT 0x00100000
c19d1205
ZW
691
692#define BAD_ARGS _("bad arguments to instruction")
fdfde340 693#define BAD_SP _("r13 not allowed here")
c19d1205
ZW
694#define BAD_PC _("r15 not allowed here")
695#define BAD_COND _("instruction cannot be conditional")
696#define BAD_OVERLAP _("registers may not be the same")
697#define BAD_HIREG _("lo register required")
698#define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
01cfc07f 699#define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
dfa9f0d5
PB
700#define BAD_BRANCH _("branch must be last instruction in IT block")
701#define BAD_NOT_IT _("instruction not allowed in IT block")
037e8744 702#define BAD_FPU _("selected FPU does not support instruction")
e07e6e58
NC
703#define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
704#define BAD_IT_COND _("incorrect condition in IT block")
705#define BAD_IT_IT _("IT falling in the range of a previous IT block")
921e5f0a 706#define MISSING_FNSTART _("missing .fnstart before unwinding directive")
5be8be5d
DG
707#define BAD_PC_ADDRESSING \
708 _("cannot use register index with PC-relative addressing")
709#define BAD_PC_WRITEBACK \
710 _("cannot use writeback with PC-relative addressing")
c19d1205 711
c921be7d
NC
712static struct hash_control * arm_ops_hsh;
713static struct hash_control * arm_cond_hsh;
714static struct hash_control * arm_shift_hsh;
715static struct hash_control * arm_psr_hsh;
716static struct hash_control * arm_v7m_psr_hsh;
717static struct hash_control * arm_reg_hsh;
718static struct hash_control * arm_reloc_hsh;
719static struct hash_control * arm_barrier_opt_hsh;
b99bd4ef 720
b99bd4ef
NC
721/* Stuff needed to resolve the label ambiguity
722 As:
723 ...
724 label: <insn>
725 may differ from:
726 ...
727 label:
5f4273c7 728 <insn> */
b99bd4ef
NC
729
730symbolS * last_label_seen;
b34976b6 731static int label_is_thumb_function_name = FALSE;
e07e6e58 732
3d0c9500
NC
733/* Literal pool structure. Held on a per-section
734 and per-sub-section basis. */
a737bd4d 735
c19d1205 736#define MAX_LITERAL_POOL_SIZE 1024
3d0c9500 737typedef struct literal_pool
b99bd4ef 738{
c921be7d
NC
739 expressionS literals [MAX_LITERAL_POOL_SIZE];
740 unsigned int next_free_entry;
741 unsigned int id;
742 symbolS * symbol;
743 segT section;
744 subsegT sub_section;
745 struct literal_pool * next;
3d0c9500 746} literal_pool;
b99bd4ef 747
3d0c9500
NC
748/* Pointer to a linked list of literal pools. */
749literal_pool * list_of_pools = NULL;
e27ec89e 750
e07e6e58
NC
751#ifdef OBJ_ELF
752# define now_it seg_info (now_seg)->tc_segment_info_data.current_it
753#else
754static struct current_it now_it;
755#endif
756
757static inline int
758now_it_compatible (int cond)
759{
760 return (cond & ~1) == (now_it.cc & ~1);
761}
762
763static inline int
764conditional_insn (void)
765{
766 return inst.cond != COND_ALWAYS;
767}
768
769static int in_it_block (void);
770
771static int handle_it_state (void);
772
773static void force_automatic_it_block_close (void);
774
c921be7d
NC
775static void it_fsm_post_encode (void);
776
e07e6e58
NC
777#define set_it_insn_type(type) \
778 do \
779 { \
780 inst.it_insn_type = type; \
781 if (handle_it_state () == FAIL) \
782 return; \
783 } \
784 while (0)
785
c921be7d
NC
786#define set_it_insn_type_nonvoid(type, failret) \
787 do \
788 { \
789 inst.it_insn_type = type; \
790 if (handle_it_state () == FAIL) \
791 return failret; \
792 } \
793 while(0)
794
e07e6e58
NC
795#define set_it_insn_type_last() \
796 do \
797 { \
798 if (inst.cond == COND_ALWAYS) \
799 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
800 else \
801 set_it_insn_type (INSIDE_IT_LAST_INSN); \
802 } \
803 while (0)
804
c19d1205 805/* Pure syntax. */
b99bd4ef 806
c19d1205
ZW
807/* This array holds the chars that always start a comment. If the
808 pre-processor is disabled, these aren't very useful. */
809const char comment_chars[] = "@";
3d0c9500 810
c19d1205
ZW
811/* This array holds the chars that only start a comment at the beginning of
812 a line. If the line seems to have the form '# 123 filename'
813 .line and .file directives will appear in the pre-processed output. */
814/* Note that input_file.c hand checks for '#' at the beginning of the
815 first line of the input file. This is because the compiler outputs
816 #NO_APP at the beginning of its output. */
817/* Also note that comments like this one will always work. */
818const char line_comment_chars[] = "#";
3d0c9500 819
c19d1205 820const char line_separator_chars[] = ";";
b99bd4ef 821
c19d1205
ZW
822/* Chars that can be used to separate mant
823 from exp in floating point numbers. */
824const char EXP_CHARS[] = "eE";
3d0c9500 825
c19d1205
ZW
826/* Chars that mean this number is a floating point constant. */
827/* As in 0f12.456 */
828/* or 0d1.2345e12 */
b99bd4ef 829
c19d1205 830const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
3d0c9500 831
c19d1205
ZW
832/* Prefix characters that indicate the start of an immediate
833 value. */
834#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
3d0c9500 835
c19d1205
ZW
836/* Separator character handling. */
837
838#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
839
840static inline int
841skip_past_char (char ** str, char c)
842{
843 if (**str == c)
844 {
845 (*str)++;
846 return SUCCESS;
3d0c9500 847 }
c19d1205
ZW
848 else
849 return FAIL;
850}
c921be7d 851
c19d1205 852#define skip_past_comma(str) skip_past_char (str, ',')
3d0c9500 853
c19d1205
ZW
854/* Arithmetic expressions (possibly involving symbols). */
855
856/* Return TRUE if anything in the expression is a bignum. */
857
858static int
859walk_no_bignums (symbolS * sp)
860{
861 if (symbol_get_value_expression (sp)->X_op == O_big)
862 return 1;
863
864 if (symbol_get_value_expression (sp)->X_add_symbol)
3d0c9500 865 {
c19d1205
ZW
866 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
867 || (symbol_get_value_expression (sp)->X_op_symbol
868 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
3d0c9500
NC
869 }
870
c19d1205 871 return 0;
3d0c9500
NC
872}
873
c19d1205
ZW
874static int in_my_get_expression = 0;
875
876/* Third argument to my_get_expression. */
877#define GE_NO_PREFIX 0
878#define GE_IMM_PREFIX 1
879#define GE_OPT_PREFIX 2
5287ad62
JB
880/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
881 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
882#define GE_OPT_PREFIX_BIG 3
a737bd4d 883
b99bd4ef 884static int
c19d1205 885my_get_expression (expressionS * ep, char ** str, int prefix_mode)
b99bd4ef 886{
c19d1205
ZW
887 char * save_in;
888 segT seg;
b99bd4ef 889
c19d1205
ZW
890 /* In unified syntax, all prefixes are optional. */
891 if (unified_syntax)
5287ad62
JB
892 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
893 : GE_OPT_PREFIX;
b99bd4ef 894
c19d1205 895 switch (prefix_mode)
b99bd4ef 896 {
c19d1205
ZW
897 case GE_NO_PREFIX: break;
898 case GE_IMM_PREFIX:
899 if (!is_immediate_prefix (**str))
900 {
901 inst.error = _("immediate expression requires a # prefix");
902 return FAIL;
903 }
904 (*str)++;
905 break;
906 case GE_OPT_PREFIX:
5287ad62 907 case GE_OPT_PREFIX_BIG:
c19d1205
ZW
908 if (is_immediate_prefix (**str))
909 (*str)++;
910 break;
911 default: abort ();
912 }
b99bd4ef 913
c19d1205 914 memset (ep, 0, sizeof (expressionS));
b99bd4ef 915
c19d1205
ZW
916 save_in = input_line_pointer;
917 input_line_pointer = *str;
918 in_my_get_expression = 1;
919 seg = expression (ep);
920 in_my_get_expression = 0;
921
f86adc07 922 if (ep->X_op == O_illegal || ep->X_op == O_absent)
b99bd4ef 923 {
f86adc07 924 /* We found a bad or missing expression in md_operand(). */
c19d1205
ZW
925 *str = input_line_pointer;
926 input_line_pointer = save_in;
927 if (inst.error == NULL)
f86adc07
NS
928 inst.error = (ep->X_op == O_absent
929 ? _("missing expression") :_("bad expression"));
c19d1205
ZW
930 return 1;
931 }
b99bd4ef 932
c19d1205
ZW
933#ifdef OBJ_AOUT
934 if (seg != absolute_section
935 && seg != text_section
936 && seg != data_section
937 && seg != bss_section
938 && seg != undefined_section)
939 {
940 inst.error = _("bad segment");
941 *str = input_line_pointer;
942 input_line_pointer = save_in;
943 return 1;
b99bd4ef 944 }
87975d2a
AM
945#else
946 (void) seg;
c19d1205 947#endif
b99bd4ef 948
c19d1205
ZW
949 /* Get rid of any bignums now, so that we don't generate an error for which
950 we can't establish a line number later on. Big numbers are never valid
951 in instructions, which is where this routine is always called. */
5287ad62
JB
952 if (prefix_mode != GE_OPT_PREFIX_BIG
953 && (ep->X_op == O_big
954 || (ep->X_add_symbol
955 && (walk_no_bignums (ep->X_add_symbol)
956 || (ep->X_op_symbol
957 && walk_no_bignums (ep->X_op_symbol))))))
c19d1205
ZW
958 {
959 inst.error = _("invalid constant");
960 *str = input_line_pointer;
961 input_line_pointer = save_in;
962 return 1;
963 }
b99bd4ef 964
c19d1205
ZW
965 *str = input_line_pointer;
966 input_line_pointer = save_in;
967 return 0;
b99bd4ef
NC
968}
969
c19d1205
ZW
970/* Turn a string in input_line_pointer into a floating point constant
971 of type TYPE, and store the appropriate bytes in *LITP. The number
972 of LITTLENUMS emitted is stored in *SIZEP. An error message is
973 returned, or NULL on OK.
b99bd4ef 974
c19d1205
ZW
975 Note that fp constants aren't represent in the normal way on the ARM.
976 In big endian mode, things are as expected. However, in little endian
977 mode fp constants are big-endian word-wise, and little-endian byte-wise
978 within the words. For example, (double) 1.1 in big endian mode is
979 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
980 the byte sequence 99 99 f1 3f 9a 99 99 99.
b99bd4ef 981
c19d1205 982 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
b99bd4ef 983
c19d1205
ZW
984char *
985md_atof (int type, char * litP, int * sizeP)
986{
987 int prec;
988 LITTLENUM_TYPE words[MAX_LITTLENUMS];
989 char *t;
990 int i;
b99bd4ef 991
c19d1205
ZW
992 switch (type)
993 {
994 case 'f':
995 case 'F':
996 case 's':
997 case 'S':
998 prec = 2;
999 break;
b99bd4ef 1000
c19d1205
ZW
1001 case 'd':
1002 case 'D':
1003 case 'r':
1004 case 'R':
1005 prec = 4;
1006 break;
b99bd4ef 1007
c19d1205
ZW
1008 case 'x':
1009 case 'X':
499ac353 1010 prec = 5;
c19d1205 1011 break;
b99bd4ef 1012
c19d1205
ZW
1013 case 'p':
1014 case 'P':
499ac353 1015 prec = 5;
c19d1205 1016 break;
a737bd4d 1017
c19d1205
ZW
1018 default:
1019 *sizeP = 0;
499ac353 1020 return _("Unrecognized or unsupported floating point constant");
c19d1205 1021 }
b99bd4ef 1022
c19d1205
ZW
1023 t = atof_ieee (input_line_pointer, type, words);
1024 if (t)
1025 input_line_pointer = t;
499ac353 1026 *sizeP = prec * sizeof (LITTLENUM_TYPE);
b99bd4ef 1027
c19d1205
ZW
1028 if (target_big_endian)
1029 {
1030 for (i = 0; i < prec; i++)
1031 {
499ac353
NC
1032 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1033 litP += sizeof (LITTLENUM_TYPE);
c19d1205
ZW
1034 }
1035 }
1036 else
1037 {
e74cfd16 1038 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
c19d1205
ZW
1039 for (i = prec - 1; i >= 0; i--)
1040 {
499ac353
NC
1041 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1042 litP += sizeof (LITTLENUM_TYPE);
c19d1205
ZW
1043 }
1044 else
1045 /* For a 4 byte float the order of elements in `words' is 1 0.
1046 For an 8 byte float the order is 1 0 3 2. */
1047 for (i = 0; i < prec; i += 2)
1048 {
499ac353
NC
1049 md_number_to_chars (litP, (valueT) words[i + 1],
1050 sizeof (LITTLENUM_TYPE));
1051 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1052 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1053 litP += 2 * sizeof (LITTLENUM_TYPE);
c19d1205
ZW
1054 }
1055 }
b99bd4ef 1056
499ac353 1057 return NULL;
c19d1205 1058}
b99bd4ef 1059
c19d1205
ZW
1060/* We handle all bad expressions here, so that we can report the faulty
1061 instruction in the error message. */
1062void
91d6fa6a 1063md_operand (expressionS * exp)
c19d1205
ZW
1064{
1065 if (in_my_get_expression)
91d6fa6a 1066 exp->X_op = O_illegal;
b99bd4ef
NC
1067}
1068
c19d1205 1069/* Immediate values. */
b99bd4ef 1070
c19d1205
ZW
1071/* Generic immediate-value read function for use in directives.
1072 Accepts anything that 'expression' can fold to a constant.
1073 *val receives the number. */
1074#ifdef OBJ_ELF
1075static int
1076immediate_for_directive (int *val)
b99bd4ef 1077{
c19d1205
ZW
1078 expressionS exp;
1079 exp.X_op = O_illegal;
b99bd4ef 1080
c19d1205
ZW
1081 if (is_immediate_prefix (*input_line_pointer))
1082 {
1083 input_line_pointer++;
1084 expression (&exp);
1085 }
b99bd4ef 1086
c19d1205
ZW
1087 if (exp.X_op != O_constant)
1088 {
1089 as_bad (_("expected #constant"));
1090 ignore_rest_of_line ();
1091 return FAIL;
1092 }
1093 *val = exp.X_add_number;
1094 return SUCCESS;
b99bd4ef 1095}
c19d1205 1096#endif
b99bd4ef 1097
c19d1205 1098/* Register parsing. */
b99bd4ef 1099
c19d1205
ZW
1100/* Generic register parser. CCP points to what should be the
1101 beginning of a register name. If it is indeed a valid register
1102 name, advance CCP over it and return the reg_entry structure;
1103 otherwise return NULL. Does not issue diagnostics. */
1104
1105static struct reg_entry *
1106arm_reg_parse_multi (char **ccp)
b99bd4ef 1107{
c19d1205
ZW
1108 char *start = *ccp;
1109 char *p;
1110 struct reg_entry *reg;
b99bd4ef 1111
c19d1205
ZW
1112#ifdef REGISTER_PREFIX
1113 if (*start != REGISTER_PREFIX)
01cfc07f 1114 return NULL;
c19d1205
ZW
1115 start++;
1116#endif
1117#ifdef OPTIONAL_REGISTER_PREFIX
1118 if (*start == OPTIONAL_REGISTER_PREFIX)
1119 start++;
1120#endif
b99bd4ef 1121
c19d1205
ZW
1122 p = start;
1123 if (!ISALPHA (*p) || !is_name_beginner (*p))
1124 return NULL;
b99bd4ef 1125
c19d1205
ZW
1126 do
1127 p++;
1128 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1129
1130 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1131
1132 if (!reg)
1133 return NULL;
1134
1135 *ccp = p;
1136 return reg;
b99bd4ef
NC
1137}
1138
1139static int
dcbf9037
JB
1140arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1141 enum arm_reg_type type)
b99bd4ef 1142{
c19d1205
ZW
1143 /* Alternative syntaxes are accepted for a few register classes. */
1144 switch (type)
1145 {
1146 case REG_TYPE_MVF:
1147 case REG_TYPE_MVD:
1148 case REG_TYPE_MVFX:
1149 case REG_TYPE_MVDX:
1150 /* Generic coprocessor register names are allowed for these. */
79134647 1151 if (reg && reg->type == REG_TYPE_CN)
c19d1205
ZW
1152 return reg->number;
1153 break;
69b97547 1154
c19d1205
ZW
1155 case REG_TYPE_CP:
1156 /* For backward compatibility, a bare number is valid here. */
1157 {
1158 unsigned long processor = strtoul (start, ccp, 10);
1159 if (*ccp != start && processor <= 15)
1160 return processor;
1161 }
6057a28f 1162
c19d1205
ZW
1163 case REG_TYPE_MMXWC:
1164 /* WC includes WCG. ??? I'm not sure this is true for all
1165 instructions that take WC registers. */
79134647 1166 if (reg && reg->type == REG_TYPE_MMXWCG)
c19d1205 1167 return reg->number;
6057a28f 1168 break;
c19d1205 1169
6057a28f 1170 default:
c19d1205 1171 break;
6057a28f
NC
1172 }
1173
dcbf9037
JB
1174 return FAIL;
1175}
1176
1177/* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1178 return value is the register number or FAIL. */
1179
1180static int
1181arm_reg_parse (char **ccp, enum arm_reg_type type)
1182{
1183 char *start = *ccp;
1184 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1185 int ret;
1186
1187 /* Do not allow a scalar (reg+index) to parse as a register. */
1188 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1189 return FAIL;
1190
1191 if (reg && reg->type == type)
1192 return reg->number;
1193
1194 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1195 return ret;
1196
c19d1205
ZW
1197 *ccp = start;
1198 return FAIL;
1199}
69b97547 1200
dcbf9037
JB
1201/* Parse a Neon type specifier. *STR should point at the leading '.'
1202 character. Does no verification at this stage that the type fits the opcode
1203 properly. E.g.,
1204
1205 .i32.i32.s16
1206 .s32.f32
1207 .u16
1208
1209 Can all be legally parsed by this function.
1210
1211 Fills in neon_type struct pointer with parsed information, and updates STR
1212 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1213 type, FAIL if not. */
1214
1215static int
1216parse_neon_type (struct neon_type *type, char **str)
1217{
1218 char *ptr = *str;
1219
1220 if (type)
1221 type->elems = 0;
1222
1223 while (type->elems < NEON_MAX_TYPE_ELS)
1224 {
1225 enum neon_el_type thistype = NT_untyped;
1226 unsigned thissize = -1u;
1227
1228 if (*ptr != '.')
1229 break;
1230
1231 ptr++;
1232
1233 /* Just a size without an explicit type. */
1234 if (ISDIGIT (*ptr))
1235 goto parsesize;
1236
1237 switch (TOLOWER (*ptr))
1238 {
1239 case 'i': thistype = NT_integer; break;
1240 case 'f': thistype = NT_float; break;
1241 case 'p': thistype = NT_poly; break;
1242 case 's': thistype = NT_signed; break;
1243 case 'u': thistype = NT_unsigned; break;
037e8744
JB
1244 case 'd':
1245 thistype = NT_float;
1246 thissize = 64;
1247 ptr++;
1248 goto done;
dcbf9037
JB
1249 default:
1250 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1251 return FAIL;
1252 }
1253
1254 ptr++;
1255
1256 /* .f is an abbreviation for .f32. */
1257 if (thistype == NT_float && !ISDIGIT (*ptr))
1258 thissize = 32;
1259 else
1260 {
1261 parsesize:
1262 thissize = strtoul (ptr, &ptr, 10);
1263
1264 if (thissize != 8 && thissize != 16 && thissize != 32
1265 && thissize != 64)
1266 {
1267 as_bad (_("bad size %d in type specifier"), thissize);
1268 return FAIL;
1269 }
1270 }
1271
037e8744 1272 done:
dcbf9037
JB
1273 if (type)
1274 {
1275 type->el[type->elems].type = thistype;
1276 type->el[type->elems].size = thissize;
1277 type->elems++;
1278 }
1279 }
1280
1281 /* Empty/missing type is not a successful parse. */
1282 if (type->elems == 0)
1283 return FAIL;
1284
1285 *str = ptr;
1286
1287 return SUCCESS;
1288}
1289
1290/* Errors may be set multiple times during parsing or bit encoding
1291 (particularly in the Neon bits), but usually the earliest error which is set
1292 will be the most meaningful. Avoid overwriting it with later (cascading)
1293 errors by calling this function. */
1294
1295static void
1296first_error (const char *err)
1297{
1298 if (!inst.error)
1299 inst.error = err;
1300}
1301
1302/* Parse a single type, e.g. ".s32", leading period included. */
1303static int
1304parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1305{
1306 char *str = *ccp;
1307 struct neon_type optype;
1308
1309 if (*str == '.')
1310 {
1311 if (parse_neon_type (&optype, &str) == SUCCESS)
1312 {
1313 if (optype.elems == 1)
1314 *vectype = optype.el[0];
1315 else
1316 {
1317 first_error (_("only one type should be specified for operand"));
1318 return FAIL;
1319 }
1320 }
1321 else
1322 {
1323 first_error (_("vector type expected"));
1324 return FAIL;
1325 }
1326 }
1327 else
1328 return FAIL;
5f4273c7 1329
dcbf9037 1330 *ccp = str;
5f4273c7 1331
dcbf9037
JB
1332 return SUCCESS;
1333}
1334
1335/* Special meanings for indices (which have a range of 0-7), which will fit into
1336 a 4-bit integer. */
1337
1338#define NEON_ALL_LANES 15
1339#define NEON_INTERLEAVE_LANES 14
1340
1341/* Parse either a register or a scalar, with an optional type. Return the
1342 register number, and optionally fill in the actual type of the register
1343 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1344 type/index information in *TYPEINFO. */
1345
1346static int
1347parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1348 enum arm_reg_type *rtype,
1349 struct neon_typed_alias *typeinfo)
1350{
1351 char *str = *ccp;
1352 struct reg_entry *reg = arm_reg_parse_multi (&str);
1353 struct neon_typed_alias atype;
1354 struct neon_type_el parsetype;
1355
1356 atype.defined = 0;
1357 atype.index = -1;
1358 atype.eltype.type = NT_invtype;
1359 atype.eltype.size = -1;
1360
1361 /* Try alternate syntax for some types of register. Note these are mutually
1362 exclusive with the Neon syntax extensions. */
1363 if (reg == NULL)
1364 {
1365 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1366 if (altreg != FAIL)
1367 *ccp = str;
1368 if (typeinfo)
1369 *typeinfo = atype;
1370 return altreg;
1371 }
1372
037e8744
JB
1373 /* Undo polymorphism when a set of register types may be accepted. */
1374 if ((type == REG_TYPE_NDQ
1375 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1376 || (type == REG_TYPE_VFSD
1377 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1378 || (type == REG_TYPE_NSDQ
1379 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
f512f76f
NC
1380 || reg->type == REG_TYPE_NQ))
1381 || (type == REG_TYPE_MMXWC
1382 && (reg->type == REG_TYPE_MMXWCG)))
21d799b5 1383 type = (enum arm_reg_type) reg->type;
dcbf9037
JB
1384
1385 if (type != reg->type)
1386 return FAIL;
1387
1388 if (reg->neon)
1389 atype = *reg->neon;
5f4273c7 1390
dcbf9037
JB
1391 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1392 {
1393 if ((atype.defined & NTA_HASTYPE) != 0)
1394 {
1395 first_error (_("can't redefine type for operand"));
1396 return FAIL;
1397 }
1398 atype.defined |= NTA_HASTYPE;
1399 atype.eltype = parsetype;
1400 }
5f4273c7 1401
dcbf9037
JB
1402 if (skip_past_char (&str, '[') == SUCCESS)
1403 {
1404 if (type != REG_TYPE_VFD)
1405 {
1406 first_error (_("only D registers may be indexed"));
1407 return FAIL;
1408 }
5f4273c7 1409
dcbf9037
JB
1410 if ((atype.defined & NTA_HASINDEX) != 0)
1411 {
1412 first_error (_("can't change index for operand"));
1413 return FAIL;
1414 }
1415
1416 atype.defined |= NTA_HASINDEX;
1417
1418 if (skip_past_char (&str, ']') == SUCCESS)
1419 atype.index = NEON_ALL_LANES;
1420 else
1421 {
1422 expressionS exp;
1423
1424 my_get_expression (&exp, &str, GE_NO_PREFIX);
1425
1426 if (exp.X_op != O_constant)
1427 {
1428 first_error (_("constant expression required"));
1429 return FAIL;
1430 }
1431
1432 if (skip_past_char (&str, ']') == FAIL)
1433 return FAIL;
1434
1435 atype.index = exp.X_add_number;
1436 }
1437 }
5f4273c7 1438
dcbf9037
JB
1439 if (typeinfo)
1440 *typeinfo = atype;
5f4273c7 1441
dcbf9037
JB
1442 if (rtype)
1443 *rtype = type;
5f4273c7 1444
dcbf9037 1445 *ccp = str;
5f4273c7 1446
dcbf9037
JB
1447 return reg->number;
1448}
1449
1450/* Like arm_reg_parse, but allow allow the following extra features:
1451 - If RTYPE is non-zero, return the (possibly restricted) type of the
1452 register (e.g. Neon double or quad reg when either has been requested).
1453 - If this is a Neon vector type with additional type information, fill
1454 in the struct pointed to by VECTYPE (if non-NULL).
5f4273c7 1455 This function will fault on encountering a scalar. */
dcbf9037
JB
1456
1457static int
1458arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1459 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1460{
1461 struct neon_typed_alias atype;
1462 char *str = *ccp;
1463 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1464
1465 if (reg == FAIL)
1466 return FAIL;
1467
1468 /* Do not allow a scalar (reg+index) to parse as a register. */
1469 if ((atype.defined & NTA_HASINDEX) != 0)
1470 {
1471 first_error (_("register operand expected, but got scalar"));
1472 return FAIL;
1473 }
1474
1475 if (vectype)
1476 *vectype = atype.eltype;
1477
1478 *ccp = str;
1479
1480 return reg;
1481}
1482
1483#define NEON_SCALAR_REG(X) ((X) >> 4)
1484#define NEON_SCALAR_INDEX(X) ((X) & 15)
1485
5287ad62
JB
1486/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1487 have enough information to be able to do a good job bounds-checking. So, we
1488 just do easy checks here, and do further checks later. */
1489
1490static int
dcbf9037 1491parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
5287ad62 1492{
dcbf9037 1493 int reg;
5287ad62 1494 char *str = *ccp;
dcbf9037 1495 struct neon_typed_alias atype;
5f4273c7 1496
dcbf9037 1497 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
5f4273c7 1498
dcbf9037 1499 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
5287ad62 1500 return FAIL;
5f4273c7 1501
dcbf9037 1502 if (atype.index == NEON_ALL_LANES)
5287ad62 1503 {
dcbf9037 1504 first_error (_("scalar must have an index"));
5287ad62
JB
1505 return FAIL;
1506 }
dcbf9037 1507 else if (atype.index >= 64 / elsize)
5287ad62 1508 {
dcbf9037 1509 first_error (_("scalar index out of range"));
5287ad62
JB
1510 return FAIL;
1511 }
5f4273c7 1512
dcbf9037
JB
1513 if (type)
1514 *type = atype.eltype;
5f4273c7 1515
5287ad62 1516 *ccp = str;
5f4273c7 1517
dcbf9037 1518 return reg * 16 + atype.index;
5287ad62
JB
1519}
1520
c19d1205 1521/* Parse an ARM register list. Returns the bitmask, or FAIL. */
e07e6e58 1522
c19d1205
ZW
1523static long
1524parse_reg_list (char ** strp)
1525{
1526 char * str = * strp;
1527 long range = 0;
1528 int another_range;
a737bd4d 1529
c19d1205
ZW
1530 /* We come back here if we get ranges concatenated by '+' or '|'. */
1531 do
6057a28f 1532 {
c19d1205 1533 another_range = 0;
a737bd4d 1534
c19d1205
ZW
1535 if (*str == '{')
1536 {
1537 int in_range = 0;
1538 int cur_reg = -1;
a737bd4d 1539
c19d1205
ZW
1540 str++;
1541 do
1542 {
1543 int reg;
6057a28f 1544
dcbf9037 1545 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
c19d1205 1546 {
dcbf9037 1547 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
c19d1205
ZW
1548 return FAIL;
1549 }
a737bd4d 1550
c19d1205
ZW
1551 if (in_range)
1552 {
1553 int i;
a737bd4d 1554
c19d1205
ZW
1555 if (reg <= cur_reg)
1556 {
dcbf9037 1557 first_error (_("bad range in register list"));
c19d1205
ZW
1558 return FAIL;
1559 }
40a18ebd 1560
c19d1205
ZW
1561 for (i = cur_reg + 1; i < reg; i++)
1562 {
1563 if (range & (1 << i))
1564 as_tsktsk
1565 (_("Warning: duplicated register (r%d) in register list"),
1566 i);
1567 else
1568 range |= 1 << i;
1569 }
1570 in_range = 0;
1571 }
a737bd4d 1572
c19d1205
ZW
1573 if (range & (1 << reg))
1574 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1575 reg);
1576 else if (reg <= cur_reg)
1577 as_tsktsk (_("Warning: register range not in ascending order"));
a737bd4d 1578
c19d1205
ZW
1579 range |= 1 << reg;
1580 cur_reg = reg;
1581 }
1582 while (skip_past_comma (&str) != FAIL
1583 || (in_range = 1, *str++ == '-'));
1584 str--;
a737bd4d 1585
c19d1205
ZW
1586 if (*str++ != '}')
1587 {
dcbf9037 1588 first_error (_("missing `}'"));
c19d1205
ZW
1589 return FAIL;
1590 }
1591 }
1592 else
1593 {
91d6fa6a 1594 expressionS exp;
40a18ebd 1595
91d6fa6a 1596 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
c19d1205 1597 return FAIL;
40a18ebd 1598
91d6fa6a 1599 if (exp.X_op == O_constant)
c19d1205 1600 {
91d6fa6a
NC
1601 if (exp.X_add_number
1602 != (exp.X_add_number & 0x0000ffff))
c19d1205
ZW
1603 {
1604 inst.error = _("invalid register mask");
1605 return FAIL;
1606 }
a737bd4d 1607
91d6fa6a 1608 if ((range & exp.X_add_number) != 0)
c19d1205 1609 {
91d6fa6a 1610 int regno = range & exp.X_add_number;
a737bd4d 1611
c19d1205
ZW
1612 regno &= -regno;
1613 regno = (1 << regno) - 1;
1614 as_tsktsk
1615 (_("Warning: duplicated register (r%d) in register list"),
1616 regno);
1617 }
a737bd4d 1618
91d6fa6a 1619 range |= exp.X_add_number;
c19d1205
ZW
1620 }
1621 else
1622 {
1623 if (inst.reloc.type != 0)
1624 {
1625 inst.error = _("expression too complex");
1626 return FAIL;
1627 }
a737bd4d 1628
91d6fa6a 1629 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
c19d1205
ZW
1630 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1631 inst.reloc.pc_rel = 0;
1632 }
1633 }
a737bd4d 1634
c19d1205
ZW
1635 if (*str == '|' || *str == '+')
1636 {
1637 str++;
1638 another_range = 1;
1639 }
a737bd4d 1640 }
c19d1205 1641 while (another_range);
a737bd4d 1642
c19d1205
ZW
1643 *strp = str;
1644 return range;
a737bd4d
NC
1645}
1646
5287ad62
JB
1647/* Types of registers in a list. */
1648
1649enum reg_list_els
1650{
1651 REGLIST_VFP_S,
1652 REGLIST_VFP_D,
1653 REGLIST_NEON_D
1654};
1655
c19d1205
ZW
1656/* Parse a VFP register list. If the string is invalid return FAIL.
1657 Otherwise return the number of registers, and set PBASE to the first
5287ad62
JB
1658 register. Parses registers of type ETYPE.
1659 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1660 - Q registers can be used to specify pairs of D registers
1661 - { } can be omitted from around a singleton register list
1662 FIXME: This is not implemented, as it would require backtracking in
1663 some cases, e.g.:
1664 vtbl.8 d3,d4,d5
1665 This could be done (the meaning isn't really ambiguous), but doesn't
1666 fit in well with the current parsing framework.
dcbf9037
JB
1667 - 32 D registers may be used (also true for VFPv3).
1668 FIXME: Types are ignored in these register lists, which is probably a
1669 bug. */
6057a28f 1670
c19d1205 1671static int
037e8744 1672parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
6057a28f 1673{
037e8744 1674 char *str = *ccp;
c19d1205
ZW
1675 int base_reg;
1676 int new_base;
21d799b5 1677 enum arm_reg_type regtype = (enum arm_reg_type) 0;
5287ad62 1678 int max_regs = 0;
c19d1205
ZW
1679 int count = 0;
1680 int warned = 0;
1681 unsigned long mask = 0;
a737bd4d 1682 int i;
6057a28f 1683
037e8744 1684 if (*str != '{')
5287ad62
JB
1685 {
1686 inst.error = _("expecting {");
1687 return FAIL;
1688 }
6057a28f 1689
037e8744 1690 str++;
6057a28f 1691
5287ad62 1692 switch (etype)
c19d1205 1693 {
5287ad62 1694 case REGLIST_VFP_S:
c19d1205
ZW
1695 regtype = REG_TYPE_VFS;
1696 max_regs = 32;
5287ad62 1697 break;
5f4273c7 1698
5287ad62
JB
1699 case REGLIST_VFP_D:
1700 regtype = REG_TYPE_VFD;
b7fc2769 1701 break;
5f4273c7 1702
b7fc2769
JB
1703 case REGLIST_NEON_D:
1704 regtype = REG_TYPE_NDQ;
1705 break;
1706 }
1707
1708 if (etype != REGLIST_VFP_S)
1709 {
b1cc4aeb
PB
1710 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1711 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
5287ad62
JB
1712 {
1713 max_regs = 32;
1714 if (thumb_mode)
1715 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
b1cc4aeb 1716 fpu_vfp_ext_d32);
5287ad62
JB
1717 else
1718 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
b1cc4aeb 1719 fpu_vfp_ext_d32);
5287ad62
JB
1720 }
1721 else
1722 max_regs = 16;
c19d1205 1723 }
6057a28f 1724
c19d1205 1725 base_reg = max_regs;
a737bd4d 1726
c19d1205
ZW
1727 do
1728 {
5287ad62 1729 int setmask = 1, addregs = 1;
dcbf9037 1730
037e8744 1731 new_base = arm_typed_reg_parse (&str, regtype, &regtype, NULL);
dcbf9037 1732
c19d1205 1733 if (new_base == FAIL)
a737bd4d 1734 {
dcbf9037 1735 first_error (_(reg_expected_msgs[regtype]));
c19d1205
ZW
1736 return FAIL;
1737 }
5f4273c7 1738
b7fc2769
JB
1739 if (new_base >= max_regs)
1740 {
1741 first_error (_("register out of range in list"));
1742 return FAIL;
1743 }
5f4273c7 1744
5287ad62
JB
1745 /* Note: a value of 2 * n is returned for the register Q<n>. */
1746 if (regtype == REG_TYPE_NQ)
1747 {
1748 setmask = 3;
1749 addregs = 2;
1750 }
1751
c19d1205
ZW
1752 if (new_base < base_reg)
1753 base_reg = new_base;
a737bd4d 1754
5287ad62 1755 if (mask & (setmask << new_base))
c19d1205 1756 {
dcbf9037 1757 first_error (_("invalid register list"));
c19d1205 1758 return FAIL;
a737bd4d 1759 }
a737bd4d 1760
c19d1205
ZW
1761 if ((mask >> new_base) != 0 && ! warned)
1762 {
1763 as_tsktsk (_("register list not in ascending order"));
1764 warned = 1;
1765 }
0bbf2aa4 1766
5287ad62
JB
1767 mask |= setmask << new_base;
1768 count += addregs;
0bbf2aa4 1769
037e8744 1770 if (*str == '-') /* We have the start of a range expression */
c19d1205
ZW
1771 {
1772 int high_range;
0bbf2aa4 1773
037e8744 1774 str++;
0bbf2aa4 1775
037e8744 1776 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
dcbf9037 1777 == FAIL)
c19d1205
ZW
1778 {
1779 inst.error = gettext (reg_expected_msgs[regtype]);
1780 return FAIL;
1781 }
0bbf2aa4 1782
b7fc2769
JB
1783 if (high_range >= max_regs)
1784 {
1785 first_error (_("register out of range in list"));
1786 return FAIL;
1787 }
1788
5287ad62
JB
1789 if (regtype == REG_TYPE_NQ)
1790 high_range = high_range + 1;
1791
c19d1205
ZW
1792 if (high_range <= new_base)
1793 {
1794 inst.error = _("register range not in ascending order");
1795 return FAIL;
1796 }
0bbf2aa4 1797
5287ad62 1798 for (new_base += addregs; new_base <= high_range; new_base += addregs)
0bbf2aa4 1799 {
5287ad62 1800 if (mask & (setmask << new_base))
0bbf2aa4 1801 {
c19d1205
ZW
1802 inst.error = _("invalid register list");
1803 return FAIL;
0bbf2aa4 1804 }
c19d1205 1805
5287ad62
JB
1806 mask |= setmask << new_base;
1807 count += addregs;
0bbf2aa4 1808 }
0bbf2aa4 1809 }
0bbf2aa4 1810 }
037e8744 1811 while (skip_past_comma (&str) != FAIL);
0bbf2aa4 1812
037e8744 1813 str++;
0bbf2aa4 1814
c19d1205
ZW
1815 /* Sanity check -- should have raised a parse error above. */
1816 if (count == 0 || count > max_regs)
1817 abort ();
1818
1819 *pbase = base_reg;
1820
1821 /* Final test -- the registers must be consecutive. */
1822 mask >>= base_reg;
1823 for (i = 0; i < count; i++)
1824 {
1825 if ((mask & (1u << i)) == 0)
1826 {
1827 inst.error = _("non-contiguous register range");
1828 return FAIL;
1829 }
1830 }
1831
037e8744
JB
1832 *ccp = str;
1833
c19d1205 1834 return count;
b99bd4ef
NC
1835}
1836
dcbf9037
JB
1837/* True if two alias types are the same. */
1838
c921be7d 1839static bfd_boolean
dcbf9037
JB
1840neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1841{
1842 if (!a && !b)
c921be7d 1843 return TRUE;
5f4273c7 1844
dcbf9037 1845 if (!a || !b)
c921be7d 1846 return FALSE;
dcbf9037
JB
1847
1848 if (a->defined != b->defined)
c921be7d 1849 return FALSE;
5f4273c7 1850
dcbf9037
JB
1851 if ((a->defined & NTA_HASTYPE) != 0
1852 && (a->eltype.type != b->eltype.type
1853 || a->eltype.size != b->eltype.size))
c921be7d 1854 return FALSE;
dcbf9037
JB
1855
1856 if ((a->defined & NTA_HASINDEX) != 0
1857 && (a->index != b->index))
c921be7d 1858 return FALSE;
5f4273c7 1859
c921be7d 1860 return TRUE;
dcbf9037
JB
1861}
1862
5287ad62
JB
1863/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1864 The base register is put in *PBASE.
dcbf9037 1865 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
5287ad62
JB
1866 the return value.
1867 The register stride (minus one) is put in bit 4 of the return value.
dcbf9037
JB
1868 Bits [6:5] encode the list length (minus one).
1869 The type of the list elements is put in *ELTYPE, if non-NULL. */
5287ad62 1870
5287ad62 1871#define NEON_LANE(X) ((X) & 0xf)
dcbf9037 1872#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
5287ad62
JB
1873#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1874
1875static int
dcbf9037
JB
1876parse_neon_el_struct_list (char **str, unsigned *pbase,
1877 struct neon_type_el *eltype)
5287ad62
JB
1878{
1879 char *ptr = *str;
1880 int base_reg = -1;
1881 int reg_incr = -1;
1882 int count = 0;
1883 int lane = -1;
1884 int leading_brace = 0;
1885 enum arm_reg_type rtype = REG_TYPE_NDQ;
20203fb9
NC
1886 const char *const incr_error = _("register stride must be 1 or 2");
1887 const char *const type_error = _("mismatched element/structure types in list");
dcbf9037 1888 struct neon_typed_alias firsttype;
5f4273c7 1889
5287ad62
JB
1890 if (skip_past_char (&ptr, '{') == SUCCESS)
1891 leading_brace = 1;
5f4273c7 1892
5287ad62
JB
1893 do
1894 {
dcbf9037
JB
1895 struct neon_typed_alias atype;
1896 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1897
5287ad62
JB
1898 if (getreg == FAIL)
1899 {
dcbf9037 1900 first_error (_(reg_expected_msgs[rtype]));
5287ad62
JB
1901 return FAIL;
1902 }
5f4273c7 1903
5287ad62
JB
1904 if (base_reg == -1)
1905 {
1906 base_reg = getreg;
1907 if (rtype == REG_TYPE_NQ)
1908 {
1909 reg_incr = 1;
5287ad62 1910 }
dcbf9037 1911 firsttype = atype;
5287ad62
JB
1912 }
1913 else if (reg_incr == -1)
1914 {
1915 reg_incr = getreg - base_reg;
1916 if (reg_incr < 1 || reg_incr > 2)
1917 {
dcbf9037 1918 first_error (_(incr_error));
5287ad62
JB
1919 return FAIL;
1920 }
1921 }
1922 else if (getreg != base_reg + reg_incr * count)
1923 {
dcbf9037
JB
1924 first_error (_(incr_error));
1925 return FAIL;
1926 }
1927
c921be7d 1928 if (! neon_alias_types_same (&atype, &firsttype))
dcbf9037
JB
1929 {
1930 first_error (_(type_error));
5287ad62
JB
1931 return FAIL;
1932 }
5f4273c7 1933
5287ad62
JB
1934 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1935 modes. */
1936 if (ptr[0] == '-')
1937 {
dcbf9037 1938 struct neon_typed_alias htype;
5287ad62
JB
1939 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1940 if (lane == -1)
1941 lane = NEON_INTERLEAVE_LANES;
1942 else if (lane != NEON_INTERLEAVE_LANES)
1943 {
dcbf9037 1944 first_error (_(type_error));
5287ad62
JB
1945 return FAIL;
1946 }
1947 if (reg_incr == -1)
1948 reg_incr = 1;
1949 else if (reg_incr != 1)
1950 {
dcbf9037 1951 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
5287ad62
JB
1952 return FAIL;
1953 }
1954 ptr++;
dcbf9037 1955 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
5287ad62
JB
1956 if (hireg == FAIL)
1957 {
dcbf9037
JB
1958 first_error (_(reg_expected_msgs[rtype]));
1959 return FAIL;
1960 }
c921be7d 1961 if (! neon_alias_types_same (&htype, &firsttype))
dcbf9037
JB
1962 {
1963 first_error (_(type_error));
5287ad62
JB
1964 return FAIL;
1965 }
1966 count += hireg + dregs - getreg;
1967 continue;
1968 }
5f4273c7 1969
5287ad62
JB
1970 /* If we're using Q registers, we can't use [] or [n] syntax. */
1971 if (rtype == REG_TYPE_NQ)
1972 {
1973 count += 2;
1974 continue;
1975 }
5f4273c7 1976
dcbf9037 1977 if ((atype.defined & NTA_HASINDEX) != 0)
5287ad62 1978 {
dcbf9037
JB
1979 if (lane == -1)
1980 lane = atype.index;
1981 else if (lane != atype.index)
5287ad62 1982 {
dcbf9037
JB
1983 first_error (_(type_error));
1984 return FAIL;
5287ad62
JB
1985 }
1986 }
1987 else if (lane == -1)
1988 lane = NEON_INTERLEAVE_LANES;
1989 else if (lane != NEON_INTERLEAVE_LANES)
1990 {
dcbf9037 1991 first_error (_(type_error));
5287ad62
JB
1992 return FAIL;
1993 }
1994 count++;
1995 }
1996 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
5f4273c7 1997
5287ad62
JB
1998 /* No lane set by [x]. We must be interleaving structures. */
1999 if (lane == -1)
2000 lane = NEON_INTERLEAVE_LANES;
5f4273c7 2001
5287ad62
JB
2002 /* Sanity check. */
2003 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2004 || (count > 1 && reg_incr == -1))
2005 {
dcbf9037 2006 first_error (_("error parsing element/structure list"));
5287ad62
JB
2007 return FAIL;
2008 }
2009
2010 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2011 {
dcbf9037 2012 first_error (_("expected }"));
5287ad62
JB
2013 return FAIL;
2014 }
5f4273c7 2015
5287ad62
JB
2016 if (reg_incr == -1)
2017 reg_incr = 1;
2018
dcbf9037
JB
2019 if (eltype)
2020 *eltype = firsttype.eltype;
2021
5287ad62
JB
2022 *pbase = base_reg;
2023 *str = ptr;
5f4273c7 2024
5287ad62
JB
2025 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2026}
2027
c19d1205
ZW
2028/* Parse an explicit relocation suffix on an expression. This is
2029 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2030 arm_reloc_hsh contains no entries, so this function can only
2031 succeed if there is no () after the word. Returns -1 on error,
2032 BFD_RELOC_UNUSED if there wasn't any suffix. */
2033static int
2034parse_reloc (char **str)
b99bd4ef 2035{
c19d1205
ZW
2036 struct reloc_entry *r;
2037 char *p, *q;
b99bd4ef 2038
c19d1205
ZW
2039 if (**str != '(')
2040 return BFD_RELOC_UNUSED;
b99bd4ef 2041
c19d1205
ZW
2042 p = *str + 1;
2043 q = p;
2044
2045 while (*q && *q != ')' && *q != ',')
2046 q++;
2047 if (*q != ')')
2048 return -1;
2049
21d799b5
NC
2050 if ((r = (struct reloc_entry *)
2051 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
c19d1205
ZW
2052 return -1;
2053
2054 *str = q + 1;
2055 return r->reloc;
b99bd4ef
NC
2056}
2057
c19d1205
ZW
2058/* Directives: register aliases. */
2059
dcbf9037 2060static struct reg_entry *
c19d1205 2061insert_reg_alias (char *str, int number, int type)
b99bd4ef 2062{
d3ce72d0 2063 struct reg_entry *new_reg;
c19d1205 2064 const char *name;
b99bd4ef 2065
d3ce72d0 2066 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
c19d1205 2067 {
d3ce72d0 2068 if (new_reg->builtin)
c19d1205 2069 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
b99bd4ef 2070
c19d1205
ZW
2071 /* Only warn about a redefinition if it's not defined as the
2072 same register. */
d3ce72d0 2073 else if (new_reg->number != number || new_reg->type != type)
c19d1205 2074 as_warn (_("ignoring redefinition of register alias '%s'"), str);
69b97547 2075
d929913e 2076 return NULL;
c19d1205 2077 }
b99bd4ef 2078
c19d1205 2079 name = xstrdup (str);
d3ce72d0 2080 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
b99bd4ef 2081
d3ce72d0
NC
2082 new_reg->name = name;
2083 new_reg->number = number;
2084 new_reg->type = type;
2085 new_reg->builtin = FALSE;
2086 new_reg->neon = NULL;
b99bd4ef 2087
d3ce72d0 2088 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
c19d1205 2089 abort ();
5f4273c7 2090
d3ce72d0 2091 return new_reg;
dcbf9037
JB
2092}
2093
2094static void
2095insert_neon_reg_alias (char *str, int number, int type,
2096 struct neon_typed_alias *atype)
2097{
2098 struct reg_entry *reg = insert_reg_alias (str, number, type);
5f4273c7 2099
dcbf9037
JB
2100 if (!reg)
2101 {
2102 first_error (_("attempt to redefine typed alias"));
2103 return;
2104 }
5f4273c7 2105
dcbf9037
JB
2106 if (atype)
2107 {
21d799b5
NC
2108 reg->neon = (struct neon_typed_alias *)
2109 xmalloc (sizeof (struct neon_typed_alias));
dcbf9037
JB
2110 *reg->neon = *atype;
2111 }
c19d1205 2112}
b99bd4ef 2113
c19d1205 2114/* Look for the .req directive. This is of the form:
b99bd4ef 2115
c19d1205 2116 new_register_name .req existing_register_name
b99bd4ef 2117
c19d1205 2118 If we find one, or if it looks sufficiently like one that we want to
d929913e 2119 handle any error here, return TRUE. Otherwise return FALSE. */
b99bd4ef 2120
d929913e 2121static bfd_boolean
c19d1205
ZW
2122create_register_alias (char * newname, char *p)
2123{
2124 struct reg_entry *old;
2125 char *oldname, *nbuf;
2126 size_t nlen;
b99bd4ef 2127
c19d1205
ZW
2128 /* The input scrubber ensures that whitespace after the mnemonic is
2129 collapsed to single spaces. */
2130 oldname = p;
2131 if (strncmp (oldname, " .req ", 6) != 0)
d929913e 2132 return FALSE;
b99bd4ef 2133
c19d1205
ZW
2134 oldname += 6;
2135 if (*oldname == '\0')
d929913e 2136 return FALSE;
b99bd4ef 2137
21d799b5 2138 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
c19d1205 2139 if (!old)
b99bd4ef 2140 {
c19d1205 2141 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
d929913e 2142 return TRUE;
b99bd4ef
NC
2143 }
2144
c19d1205
ZW
2145 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2146 the desired alias name, and p points to its end. If not, then
2147 the desired alias name is in the global original_case_string. */
2148#ifdef TC_CASE_SENSITIVE
2149 nlen = p - newname;
2150#else
2151 newname = original_case_string;
2152 nlen = strlen (newname);
2153#endif
b99bd4ef 2154
21d799b5 2155 nbuf = (char *) alloca (nlen + 1);
c19d1205
ZW
2156 memcpy (nbuf, newname, nlen);
2157 nbuf[nlen] = '\0';
b99bd4ef 2158
c19d1205
ZW
2159 /* Create aliases under the new name as stated; an all-lowercase
2160 version of the new name; and an all-uppercase version of the new
2161 name. */
d929913e
NC
2162 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2163 {
2164 for (p = nbuf; *p; p++)
2165 *p = TOUPPER (*p);
c19d1205 2166
d929913e
NC
2167 if (strncmp (nbuf, newname, nlen))
2168 {
2169 /* If this attempt to create an additional alias fails, do not bother
2170 trying to create the all-lower case alias. We will fail and issue
2171 a second, duplicate error message. This situation arises when the
2172 programmer does something like:
2173 foo .req r0
2174 Foo .req r1
2175 The second .req creates the "Foo" alias but then fails to create
5f4273c7 2176 the artificial FOO alias because it has already been created by the
d929913e
NC
2177 first .req. */
2178 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2179 return TRUE;
2180 }
c19d1205 2181
d929913e
NC
2182 for (p = nbuf; *p; p++)
2183 *p = TOLOWER (*p);
c19d1205 2184
d929913e
NC
2185 if (strncmp (nbuf, newname, nlen))
2186 insert_reg_alias (nbuf, old->number, old->type);
2187 }
c19d1205 2188
d929913e 2189 return TRUE;
b99bd4ef
NC
2190}
2191
dcbf9037
JB
2192/* Create a Neon typed/indexed register alias using directives, e.g.:
2193 X .dn d5.s32[1]
2194 Y .qn 6.s16
2195 Z .dn d7
2196 T .dn Z[0]
2197 These typed registers can be used instead of the types specified after the
2198 Neon mnemonic, so long as all operands given have types. Types can also be
2199 specified directly, e.g.:
5f4273c7 2200 vadd d0.s32, d1.s32, d2.s32 */
dcbf9037 2201
c921be7d 2202static bfd_boolean
dcbf9037
JB
2203create_neon_reg_alias (char *newname, char *p)
2204{
2205 enum arm_reg_type basetype;
2206 struct reg_entry *basereg;
2207 struct reg_entry mybasereg;
2208 struct neon_type ntype;
2209 struct neon_typed_alias typeinfo;
2210 char *namebuf, *nameend;
2211 int namelen;
5f4273c7 2212
dcbf9037
JB
2213 typeinfo.defined = 0;
2214 typeinfo.eltype.type = NT_invtype;
2215 typeinfo.eltype.size = -1;
2216 typeinfo.index = -1;
5f4273c7 2217
dcbf9037 2218 nameend = p;
5f4273c7 2219
dcbf9037
JB
2220 if (strncmp (p, " .dn ", 5) == 0)
2221 basetype = REG_TYPE_VFD;
2222 else if (strncmp (p, " .qn ", 5) == 0)
2223 basetype = REG_TYPE_NQ;
2224 else
c921be7d 2225 return FALSE;
5f4273c7 2226
dcbf9037 2227 p += 5;
5f4273c7 2228
dcbf9037 2229 if (*p == '\0')
c921be7d 2230 return FALSE;
5f4273c7 2231
dcbf9037
JB
2232 basereg = arm_reg_parse_multi (&p);
2233
2234 if (basereg && basereg->type != basetype)
2235 {
2236 as_bad (_("bad type for register"));
c921be7d 2237 return FALSE;
dcbf9037
JB
2238 }
2239
2240 if (basereg == NULL)
2241 {
2242 expressionS exp;
2243 /* Try parsing as an integer. */
2244 my_get_expression (&exp, &p, GE_NO_PREFIX);
2245 if (exp.X_op != O_constant)
2246 {
2247 as_bad (_("expression must be constant"));
c921be7d 2248 return FALSE;
dcbf9037
JB
2249 }
2250 basereg = &mybasereg;
2251 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2252 : exp.X_add_number;
2253 basereg->neon = 0;
2254 }
2255
2256 if (basereg->neon)
2257 typeinfo = *basereg->neon;
2258
2259 if (parse_neon_type (&ntype, &p) == SUCCESS)
2260 {
2261 /* We got a type. */
2262 if (typeinfo.defined & NTA_HASTYPE)
2263 {
2264 as_bad (_("can't redefine the type of a register alias"));
c921be7d 2265 return FALSE;
dcbf9037 2266 }
5f4273c7 2267
dcbf9037
JB
2268 typeinfo.defined |= NTA_HASTYPE;
2269 if (ntype.elems != 1)
2270 {
2271 as_bad (_("you must specify a single type only"));
c921be7d 2272 return FALSE;
dcbf9037
JB
2273 }
2274 typeinfo.eltype = ntype.el[0];
2275 }
5f4273c7 2276
dcbf9037
JB
2277 if (skip_past_char (&p, '[') == SUCCESS)
2278 {
2279 expressionS exp;
2280 /* We got a scalar index. */
5f4273c7 2281
dcbf9037
JB
2282 if (typeinfo.defined & NTA_HASINDEX)
2283 {
2284 as_bad (_("can't redefine the index of a scalar alias"));
c921be7d 2285 return FALSE;
dcbf9037 2286 }
5f4273c7 2287
dcbf9037 2288 my_get_expression (&exp, &p, GE_NO_PREFIX);
5f4273c7 2289
dcbf9037
JB
2290 if (exp.X_op != O_constant)
2291 {
2292 as_bad (_("scalar index must be constant"));
c921be7d 2293 return FALSE;
dcbf9037 2294 }
5f4273c7 2295
dcbf9037
JB
2296 typeinfo.defined |= NTA_HASINDEX;
2297 typeinfo.index = exp.X_add_number;
5f4273c7 2298
dcbf9037
JB
2299 if (skip_past_char (&p, ']') == FAIL)
2300 {
2301 as_bad (_("expecting ]"));
c921be7d 2302 return FALSE;
dcbf9037
JB
2303 }
2304 }
2305
2306 namelen = nameend - newname;
21d799b5 2307 namebuf = (char *) alloca (namelen + 1);
dcbf9037
JB
2308 strncpy (namebuf, newname, namelen);
2309 namebuf[namelen] = '\0';
5f4273c7 2310
dcbf9037
JB
2311 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2312 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2313
dcbf9037
JB
2314 /* Insert name in all uppercase. */
2315 for (p = namebuf; *p; p++)
2316 *p = TOUPPER (*p);
5f4273c7 2317
dcbf9037
JB
2318 if (strncmp (namebuf, newname, namelen))
2319 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2320 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2321
dcbf9037
JB
2322 /* Insert name in all lowercase. */
2323 for (p = namebuf; *p; p++)
2324 *p = TOLOWER (*p);
5f4273c7 2325
dcbf9037
JB
2326 if (strncmp (namebuf, newname, namelen))
2327 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2328 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2329
c921be7d 2330 return TRUE;
dcbf9037
JB
2331}
2332
c19d1205
ZW
2333/* Should never be called, as .req goes between the alias and the
2334 register name, not at the beginning of the line. */
c921be7d 2335
b99bd4ef 2336static void
c19d1205 2337s_req (int a ATTRIBUTE_UNUSED)
b99bd4ef 2338{
c19d1205
ZW
2339 as_bad (_("invalid syntax for .req directive"));
2340}
b99bd4ef 2341
dcbf9037
JB
2342static void
2343s_dn (int a ATTRIBUTE_UNUSED)
2344{
2345 as_bad (_("invalid syntax for .dn directive"));
2346}
2347
2348static void
2349s_qn (int a ATTRIBUTE_UNUSED)
2350{
2351 as_bad (_("invalid syntax for .qn directive"));
2352}
2353
c19d1205
ZW
2354/* The .unreq directive deletes an alias which was previously defined
2355 by .req. For example:
b99bd4ef 2356
c19d1205
ZW
2357 my_alias .req r11
2358 .unreq my_alias */
b99bd4ef
NC
2359
2360static void
c19d1205 2361s_unreq (int a ATTRIBUTE_UNUSED)
b99bd4ef 2362{
c19d1205
ZW
2363 char * name;
2364 char saved_char;
b99bd4ef 2365
c19d1205
ZW
2366 name = input_line_pointer;
2367
2368 while (*input_line_pointer != 0
2369 && *input_line_pointer != ' '
2370 && *input_line_pointer != '\n')
2371 ++input_line_pointer;
2372
2373 saved_char = *input_line_pointer;
2374 *input_line_pointer = 0;
2375
2376 if (!*name)
2377 as_bad (_("invalid syntax for .unreq directive"));
2378 else
2379 {
21d799b5
NC
2380 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2381 name);
c19d1205
ZW
2382
2383 if (!reg)
2384 as_bad (_("unknown register alias '%s'"), name);
2385 else if (reg->builtin)
2386 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2387 name);
2388 else
2389 {
d929913e
NC
2390 char * p;
2391 char * nbuf;
2392
db0bc284 2393 hash_delete (arm_reg_hsh, name, FALSE);
c19d1205 2394 free ((char *) reg->name);
dcbf9037
JB
2395 if (reg->neon)
2396 free (reg->neon);
c19d1205 2397 free (reg);
d929913e
NC
2398
2399 /* Also locate the all upper case and all lower case versions.
2400 Do not complain if we cannot find one or the other as it
2401 was probably deleted above. */
5f4273c7 2402
d929913e
NC
2403 nbuf = strdup (name);
2404 for (p = nbuf; *p; p++)
2405 *p = TOUPPER (*p);
21d799b5 2406 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
d929913e
NC
2407 if (reg)
2408 {
db0bc284 2409 hash_delete (arm_reg_hsh, nbuf, FALSE);
d929913e
NC
2410 free ((char *) reg->name);
2411 if (reg->neon)
2412 free (reg->neon);
2413 free (reg);
2414 }
2415
2416 for (p = nbuf; *p; p++)
2417 *p = TOLOWER (*p);
21d799b5 2418 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
d929913e
NC
2419 if (reg)
2420 {
db0bc284 2421 hash_delete (arm_reg_hsh, nbuf, FALSE);
d929913e
NC
2422 free ((char *) reg->name);
2423 if (reg->neon)
2424 free (reg->neon);
2425 free (reg);
2426 }
2427
2428 free (nbuf);
c19d1205
ZW
2429 }
2430 }
b99bd4ef 2431
c19d1205 2432 *input_line_pointer = saved_char;
b99bd4ef
NC
2433 demand_empty_rest_of_line ();
2434}
2435
c19d1205
ZW
2436/* Directives: Instruction set selection. */
2437
2438#ifdef OBJ_ELF
2439/* This code is to handle mapping symbols as defined in the ARM ELF spec.
2440 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2441 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2442 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2443
cd000bff
DJ
2444/* Create a new mapping symbol for the transition to STATE. */
2445
2446static void
2447make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
b99bd4ef 2448{
a737bd4d 2449 symbolS * symbolP;
c19d1205
ZW
2450 const char * symname;
2451 int type;
b99bd4ef 2452
c19d1205 2453 switch (state)
b99bd4ef 2454 {
c19d1205
ZW
2455 case MAP_DATA:
2456 symname = "$d";
2457 type = BSF_NO_FLAGS;
2458 break;
2459 case MAP_ARM:
2460 symname = "$a";
2461 type = BSF_NO_FLAGS;
2462 break;
2463 case MAP_THUMB:
2464 symname = "$t";
2465 type = BSF_NO_FLAGS;
2466 break;
c19d1205
ZW
2467 default:
2468 abort ();
2469 }
2470
cd000bff 2471 symbolP = symbol_new (symname, now_seg, value, frag);
c19d1205
ZW
2472 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2473
2474 switch (state)
2475 {
2476 case MAP_ARM:
2477 THUMB_SET_FUNC (symbolP, 0);
2478 ARM_SET_THUMB (symbolP, 0);
2479 ARM_SET_INTERWORK (symbolP, support_interwork);
2480 break;
2481
2482 case MAP_THUMB:
2483 THUMB_SET_FUNC (symbolP, 1);
2484 ARM_SET_THUMB (symbolP, 1);
2485 ARM_SET_INTERWORK (symbolP, support_interwork);
2486 break;
2487
2488 case MAP_DATA:
2489 default:
cd000bff
DJ
2490 break;
2491 }
2492
2493 /* Save the mapping symbols for future reference. Also check that
2494 we do not place two mapping symbols at the same offset within a
2495 frag. We'll handle overlap between frags in
2de7820f
JZ
2496 check_mapping_symbols.
2497
2498 If .fill or other data filling directive generates zero sized data,
2499 the mapping symbol for the following code will have the same value
2500 as the one generated for the data filling directive. In this case,
2501 we replace the old symbol with the new one at the same address. */
cd000bff
DJ
2502 if (value == 0)
2503 {
2de7820f
JZ
2504 if (frag->tc_frag_data.first_map != NULL)
2505 {
2506 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2507 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2508 }
cd000bff
DJ
2509 frag->tc_frag_data.first_map = symbolP;
2510 }
2511 if (frag->tc_frag_data.last_map != NULL)
0f020cef
JZ
2512 {
2513 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
0f020cef
JZ
2514 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2515 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2516 }
cd000bff
DJ
2517 frag->tc_frag_data.last_map = symbolP;
2518}
2519
2520/* We must sometimes convert a region marked as code to data during
2521 code alignment, if an odd number of bytes have to be padded. The
2522 code mapping symbol is pushed to an aligned address. */
2523
2524static void
2525insert_data_mapping_symbol (enum mstate state,
2526 valueT value, fragS *frag, offsetT bytes)
2527{
2528 /* If there was already a mapping symbol, remove it. */
2529 if (frag->tc_frag_data.last_map != NULL
2530 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2531 {
2532 symbolS *symp = frag->tc_frag_data.last_map;
2533
2534 if (value == 0)
2535 {
2536 know (frag->tc_frag_data.first_map == symp);
2537 frag->tc_frag_data.first_map = NULL;
2538 }
2539 frag->tc_frag_data.last_map = NULL;
2540 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
c19d1205 2541 }
cd000bff
DJ
2542
2543 make_mapping_symbol (MAP_DATA, value, frag);
2544 make_mapping_symbol (state, value + bytes, frag);
2545}
2546
2547static void mapping_state_2 (enum mstate state, int max_chars);
2548
2549/* Set the mapping state to STATE. Only call this when about to
2550 emit some STATE bytes to the file. */
2551
2552void
2553mapping_state (enum mstate state)
2554{
940b5ce0
DJ
2555 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2556
cd000bff
DJ
2557#define TRANSITION(from, to) (mapstate == (from) && state == (to))
2558
2559 if (mapstate == state)
2560 /* The mapping symbol has already been emitted.
2561 There is nothing else to do. */
2562 return;
2563 else if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2564 /* This case will be evaluated later in the next else. */
2565 return;
2566 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2567 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2568 {
2569 /* Only add the symbol if the offset is > 0:
2570 if we're at the first frag, check it's size > 0;
2571 if we're not at the first frag, then for sure
2572 the offset is > 0. */
2573 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2574 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2575
2576 if (add_symbol)
2577 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2578 }
2579
2580 mapping_state_2 (state, 0);
2581#undef TRANSITION
2582}
2583
2584/* Same as mapping_state, but MAX_CHARS bytes have already been
2585 allocated. Put the mapping symbol that far back. */
2586
2587static void
2588mapping_state_2 (enum mstate state, int max_chars)
2589{
940b5ce0
DJ
2590 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2591
2592 if (!SEG_NORMAL (now_seg))
2593 return;
2594
cd000bff
DJ
2595 if (mapstate == state)
2596 /* The mapping symbol has already been emitted.
2597 There is nothing else to do. */
2598 return;
2599
cd000bff
DJ
2600 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2601 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
c19d1205
ZW
2602}
2603#else
d3106081
NS
2604#define mapping_state(x) ((void)0)
2605#define mapping_state_2(x, y) ((void)0)
c19d1205
ZW
2606#endif
2607
2608/* Find the real, Thumb encoded start of a Thumb function. */
2609
4343666d 2610#ifdef OBJ_COFF
c19d1205
ZW
2611static symbolS *
2612find_real_start (symbolS * symbolP)
2613{
2614 char * real_start;
2615 const char * name = S_GET_NAME (symbolP);
2616 symbolS * new_target;
2617
2618 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2619#define STUB_NAME ".real_start_of"
2620
2621 if (name == NULL)
2622 abort ();
2623
37f6032b
ZW
2624 /* The compiler may generate BL instructions to local labels because
2625 it needs to perform a branch to a far away location. These labels
2626 do not have a corresponding ".real_start_of" label. We check
2627 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2628 the ".real_start_of" convention for nonlocal branches. */
2629 if (S_IS_LOCAL (symbolP) || name[0] == '.')
c19d1205
ZW
2630 return symbolP;
2631
37f6032b 2632 real_start = ACONCAT ((STUB_NAME, name, NULL));
c19d1205
ZW
2633 new_target = symbol_find (real_start);
2634
2635 if (new_target == NULL)
2636 {
bd3ba5d1 2637 as_warn (_("Failed to find real start of function: %s\n"), name);
c19d1205
ZW
2638 new_target = symbolP;
2639 }
2640
c19d1205
ZW
2641 return new_target;
2642}
4343666d 2643#endif
c19d1205
ZW
2644
2645static void
2646opcode_select (int width)
2647{
2648 switch (width)
2649 {
2650 case 16:
2651 if (! thumb_mode)
2652 {
e74cfd16 2653 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
c19d1205
ZW
2654 as_bad (_("selected processor does not support THUMB opcodes"));
2655
2656 thumb_mode = 1;
2657 /* No need to force the alignment, since we will have been
2658 coming from ARM mode, which is word-aligned. */
2659 record_alignment (now_seg, 1);
2660 }
c19d1205
ZW
2661 break;
2662
2663 case 32:
2664 if (thumb_mode)
2665 {
e74cfd16 2666 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
c19d1205
ZW
2667 as_bad (_("selected processor does not support ARM opcodes"));
2668
2669 thumb_mode = 0;
2670
2671 if (!need_pass_2)
2672 frag_align (2, 0, 0);
2673
2674 record_alignment (now_seg, 1);
2675 }
c19d1205
ZW
2676 break;
2677
2678 default:
2679 as_bad (_("invalid instruction size selected (%d)"), width);
2680 }
2681}
2682
2683static void
2684s_arm (int ignore ATTRIBUTE_UNUSED)
2685{
2686 opcode_select (32);
2687 demand_empty_rest_of_line ();
2688}
2689
2690static void
2691s_thumb (int ignore ATTRIBUTE_UNUSED)
2692{
2693 opcode_select (16);
2694 demand_empty_rest_of_line ();
2695}
2696
2697static void
2698s_code (int unused ATTRIBUTE_UNUSED)
2699{
2700 int temp;
2701
2702 temp = get_absolute_expression ();
2703 switch (temp)
2704 {
2705 case 16:
2706 case 32:
2707 opcode_select (temp);
2708 break;
2709
2710 default:
2711 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2712 }
2713}
2714
2715static void
2716s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2717{
2718 /* If we are not already in thumb mode go into it, EVEN if
2719 the target processor does not support thumb instructions.
2720 This is used by gcc/config/arm/lib1funcs.asm for example
2721 to compile interworking support functions even if the
2722 target processor should not support interworking. */
2723 if (! thumb_mode)
2724 {
2725 thumb_mode = 2;
2726 record_alignment (now_seg, 1);
2727 }
2728
2729 demand_empty_rest_of_line ();
2730}
2731
2732static void
2733s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2734{
2735 s_thumb (0);
2736
2737 /* The following label is the name/address of the start of a Thumb function.
2738 We need to know this for the interworking support. */
2739 label_is_thumb_function_name = TRUE;
2740}
2741
2742/* Perform a .set directive, but also mark the alias as
2743 being a thumb function. */
2744
2745static void
2746s_thumb_set (int equiv)
2747{
2748 /* XXX the following is a duplicate of the code for s_set() in read.c
2749 We cannot just call that code as we need to get at the symbol that
2750 is created. */
2751 char * name;
2752 char delim;
2753 char * end_name;
2754 symbolS * symbolP;
2755
2756 /* Especial apologies for the random logic:
2757 This just grew, and could be parsed much more simply!
2758 Dean - in haste. */
2759 name = input_line_pointer;
2760 delim = get_symbol_end ();
2761 end_name = input_line_pointer;
2762 *end_name = delim;
2763
2764 if (*input_line_pointer != ',')
2765 {
2766 *end_name = 0;
2767 as_bad (_("expected comma after name \"%s\""), name);
b99bd4ef
NC
2768 *end_name = delim;
2769 ignore_rest_of_line ();
2770 return;
2771 }
2772
2773 input_line_pointer++;
2774 *end_name = 0;
2775
2776 if (name[0] == '.' && name[1] == '\0')
2777 {
2778 /* XXX - this should not happen to .thumb_set. */
2779 abort ();
2780 }
2781
2782 if ((symbolP = symbol_find (name)) == NULL
2783 && (symbolP = md_undefined_symbol (name)) == NULL)
2784 {
2785#ifndef NO_LISTING
2786 /* When doing symbol listings, play games with dummy fragments living
2787 outside the normal fragment chain to record the file and line info
c19d1205 2788 for this symbol. */
b99bd4ef
NC
2789 if (listing & LISTING_SYMBOLS)
2790 {
2791 extern struct list_info_struct * listing_tail;
21d799b5 2792 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
b99bd4ef
NC
2793
2794 memset (dummy_frag, 0, sizeof (fragS));
2795 dummy_frag->fr_type = rs_fill;
2796 dummy_frag->line = listing_tail;
2797 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2798 dummy_frag->fr_symbol = symbolP;
2799 }
2800 else
2801#endif
2802 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2803
2804#ifdef OBJ_COFF
2805 /* "set" symbols are local unless otherwise specified. */
2806 SF_SET_LOCAL (symbolP);
2807#endif /* OBJ_COFF */
2808 } /* Make a new symbol. */
2809
2810 symbol_table_insert (symbolP);
2811
2812 * end_name = delim;
2813
2814 if (equiv
2815 && S_IS_DEFINED (symbolP)
2816 && S_GET_SEGMENT (symbolP) != reg_section)
2817 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2818
2819 pseudo_set (symbolP);
2820
2821 demand_empty_rest_of_line ();
2822
c19d1205 2823 /* XXX Now we come to the Thumb specific bit of code. */
b99bd4ef
NC
2824
2825 THUMB_SET_FUNC (symbolP, 1);
2826 ARM_SET_THUMB (symbolP, 1);
2827#if defined OBJ_ELF || defined OBJ_COFF
2828 ARM_SET_INTERWORK (symbolP, support_interwork);
2829#endif
2830}
2831
c19d1205 2832/* Directives: Mode selection. */
b99bd4ef 2833
c19d1205
ZW
2834/* .syntax [unified|divided] - choose the new unified syntax
2835 (same for Arm and Thumb encoding, modulo slight differences in what
2836 can be represented) or the old divergent syntax for each mode. */
b99bd4ef 2837static void
c19d1205 2838s_syntax (int unused ATTRIBUTE_UNUSED)
b99bd4ef 2839{
c19d1205
ZW
2840 char *name, delim;
2841
2842 name = input_line_pointer;
2843 delim = get_symbol_end ();
2844
2845 if (!strcasecmp (name, "unified"))
2846 unified_syntax = TRUE;
2847 else if (!strcasecmp (name, "divided"))
2848 unified_syntax = FALSE;
2849 else
2850 {
2851 as_bad (_("unrecognized syntax mode \"%s\""), name);
2852 return;
2853 }
2854 *input_line_pointer = delim;
b99bd4ef
NC
2855 demand_empty_rest_of_line ();
2856}
2857
c19d1205
ZW
2858/* Directives: sectioning and alignment. */
2859
2860/* Same as s_align_ptwo but align 0 => align 2. */
2861
b99bd4ef 2862static void
c19d1205 2863s_align (int unused ATTRIBUTE_UNUSED)
b99bd4ef 2864{
a737bd4d 2865 int temp;
dce323d1 2866 bfd_boolean fill_p;
c19d1205
ZW
2867 long temp_fill;
2868 long max_alignment = 15;
b99bd4ef
NC
2869
2870 temp = get_absolute_expression ();
c19d1205
ZW
2871 if (temp > max_alignment)
2872 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2873 else if (temp < 0)
b99bd4ef 2874 {
c19d1205
ZW
2875 as_bad (_("alignment negative. 0 assumed."));
2876 temp = 0;
2877 }
b99bd4ef 2878
c19d1205
ZW
2879 if (*input_line_pointer == ',')
2880 {
2881 input_line_pointer++;
2882 temp_fill = get_absolute_expression ();
dce323d1 2883 fill_p = TRUE;
b99bd4ef 2884 }
c19d1205 2885 else
dce323d1
PB
2886 {
2887 fill_p = FALSE;
2888 temp_fill = 0;
2889 }
b99bd4ef 2890
c19d1205
ZW
2891 if (!temp)
2892 temp = 2;
b99bd4ef 2893
c19d1205
ZW
2894 /* Only make a frag if we HAVE to. */
2895 if (temp && !need_pass_2)
dce323d1
PB
2896 {
2897 if (!fill_p && subseg_text_p (now_seg))
2898 frag_align_code (temp, 0);
2899 else
2900 frag_align (temp, (int) temp_fill, 0);
2901 }
c19d1205
ZW
2902 demand_empty_rest_of_line ();
2903
2904 record_alignment (now_seg, temp);
b99bd4ef
NC
2905}
2906
c19d1205
ZW
2907static void
2908s_bss (int ignore ATTRIBUTE_UNUSED)
b99bd4ef 2909{
c19d1205
ZW
2910 /* We don't support putting frags in the BSS segment, we fake it by
2911 marking in_bss, then looking at s_skip for clues. */
2912 subseg_set (bss_section, 0);
2913 demand_empty_rest_of_line ();
cd000bff
DJ
2914
2915#ifdef md_elf_section_change_hook
2916 md_elf_section_change_hook ();
2917#endif
c19d1205 2918}
b99bd4ef 2919
c19d1205
ZW
2920static void
2921s_even (int ignore ATTRIBUTE_UNUSED)
2922{
2923 /* Never make frag if expect extra pass. */
2924 if (!need_pass_2)
2925 frag_align (1, 0, 0);
b99bd4ef 2926
c19d1205 2927 record_alignment (now_seg, 1);
b99bd4ef 2928
c19d1205 2929 demand_empty_rest_of_line ();
b99bd4ef
NC
2930}
2931
c19d1205 2932/* Directives: Literal pools. */
a737bd4d 2933
c19d1205
ZW
2934static literal_pool *
2935find_literal_pool (void)
a737bd4d 2936{
c19d1205 2937 literal_pool * pool;
a737bd4d 2938
c19d1205 2939 for (pool = list_of_pools; pool != NULL; pool = pool->next)
a737bd4d 2940 {
c19d1205
ZW
2941 if (pool->section == now_seg
2942 && pool->sub_section == now_subseg)
2943 break;
a737bd4d
NC
2944 }
2945
c19d1205 2946 return pool;
a737bd4d
NC
2947}
2948
c19d1205
ZW
2949static literal_pool *
2950find_or_make_literal_pool (void)
a737bd4d 2951{
c19d1205
ZW
2952 /* Next literal pool ID number. */
2953 static unsigned int latest_pool_num = 1;
2954 literal_pool * pool;
a737bd4d 2955
c19d1205 2956 pool = find_literal_pool ();
a737bd4d 2957
c19d1205 2958 if (pool == NULL)
a737bd4d 2959 {
c19d1205 2960 /* Create a new pool. */
21d799b5 2961 pool = (literal_pool *) xmalloc (sizeof (* pool));
c19d1205
ZW
2962 if (! pool)
2963 return NULL;
a737bd4d 2964
c19d1205
ZW
2965 pool->next_free_entry = 0;
2966 pool->section = now_seg;
2967 pool->sub_section = now_subseg;
2968 pool->next = list_of_pools;
2969 pool->symbol = NULL;
2970
2971 /* Add it to the list. */
2972 list_of_pools = pool;
a737bd4d 2973 }
a737bd4d 2974
c19d1205
ZW
2975 /* New pools, and emptied pools, will have a NULL symbol. */
2976 if (pool->symbol == NULL)
a737bd4d 2977 {
c19d1205
ZW
2978 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
2979 (valueT) 0, &zero_address_frag);
2980 pool->id = latest_pool_num ++;
a737bd4d
NC
2981 }
2982
c19d1205
ZW
2983 /* Done. */
2984 return pool;
a737bd4d
NC
2985}
2986
c19d1205 2987/* Add the literal in the global 'inst'
5f4273c7 2988 structure to the relevant literal pool. */
b99bd4ef
NC
2989
2990static int
c19d1205 2991add_to_lit_pool (void)
b99bd4ef 2992{
c19d1205
ZW
2993 literal_pool * pool;
2994 unsigned int entry;
b99bd4ef 2995
c19d1205
ZW
2996 pool = find_or_make_literal_pool ();
2997
2998 /* Check if this literal value is already in the pool. */
2999 for (entry = 0; entry < pool->next_free_entry; entry ++)
b99bd4ef 3000 {
c19d1205
ZW
3001 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3002 && (inst.reloc.exp.X_op == O_constant)
3003 && (pool->literals[entry].X_add_number
3004 == inst.reloc.exp.X_add_number)
3005 && (pool->literals[entry].X_unsigned
3006 == inst.reloc.exp.X_unsigned))
3007 break;
3008
3009 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3010 && (inst.reloc.exp.X_op == O_symbol)
3011 && (pool->literals[entry].X_add_number
3012 == inst.reloc.exp.X_add_number)
3013 && (pool->literals[entry].X_add_symbol
3014 == inst.reloc.exp.X_add_symbol)
3015 && (pool->literals[entry].X_op_symbol
3016 == inst.reloc.exp.X_op_symbol))
3017 break;
b99bd4ef
NC
3018 }
3019
c19d1205
ZW
3020 /* Do we need to create a new entry? */
3021 if (entry == pool->next_free_entry)
3022 {
3023 if (entry >= MAX_LITERAL_POOL_SIZE)
3024 {
3025 inst.error = _("literal pool overflow");
3026 return FAIL;
3027 }
3028
3029 pool->literals[entry] = inst.reloc.exp;
3030 pool->next_free_entry += 1;
3031 }
b99bd4ef 3032
c19d1205
ZW
3033 inst.reloc.exp.X_op = O_symbol;
3034 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3035 inst.reloc.exp.X_add_symbol = pool->symbol;
b99bd4ef 3036
c19d1205 3037 return SUCCESS;
b99bd4ef
NC
3038}
3039
c19d1205
ZW
3040/* Can't use symbol_new here, so have to create a symbol and then at
3041 a later date assign it a value. Thats what these functions do. */
e16bb312 3042
c19d1205
ZW
3043static void
3044symbol_locate (symbolS * symbolP,
3045 const char * name, /* It is copied, the caller can modify. */
3046 segT segment, /* Segment identifier (SEG_<something>). */
3047 valueT valu, /* Symbol value. */
3048 fragS * frag) /* Associated fragment. */
3049{
3050 unsigned int name_length;
3051 char * preserved_copy_of_name;
e16bb312 3052
c19d1205
ZW
3053 name_length = strlen (name) + 1; /* +1 for \0. */
3054 obstack_grow (&notes, name, name_length);
21d799b5 3055 preserved_copy_of_name = (char *) obstack_finish (&notes);
e16bb312 3056
c19d1205
ZW
3057#ifdef tc_canonicalize_symbol_name
3058 preserved_copy_of_name =
3059 tc_canonicalize_symbol_name (preserved_copy_of_name);
3060#endif
b99bd4ef 3061
c19d1205 3062 S_SET_NAME (symbolP, preserved_copy_of_name);
b99bd4ef 3063
c19d1205
ZW
3064 S_SET_SEGMENT (symbolP, segment);
3065 S_SET_VALUE (symbolP, valu);
3066 symbol_clear_list_pointers (symbolP);
b99bd4ef 3067
c19d1205 3068 symbol_set_frag (symbolP, frag);
b99bd4ef 3069
c19d1205
ZW
3070 /* Link to end of symbol chain. */
3071 {
3072 extern int symbol_table_frozen;
b99bd4ef 3073
c19d1205
ZW
3074 if (symbol_table_frozen)
3075 abort ();
3076 }
b99bd4ef 3077
c19d1205 3078 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
b99bd4ef 3079
c19d1205 3080 obj_symbol_new_hook (symbolP);
b99bd4ef 3081
c19d1205
ZW
3082#ifdef tc_symbol_new_hook
3083 tc_symbol_new_hook (symbolP);
3084#endif
3085
3086#ifdef DEBUG_SYMS
3087 verify_symbol_chain (symbol_rootP, symbol_lastP);
3088#endif /* DEBUG_SYMS */
b99bd4ef
NC
3089}
3090
b99bd4ef 3091
c19d1205
ZW
3092static void
3093s_ltorg (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 3094{
c19d1205
ZW
3095 unsigned int entry;
3096 literal_pool * pool;
3097 char sym_name[20];
b99bd4ef 3098
c19d1205
ZW
3099 pool = find_literal_pool ();
3100 if (pool == NULL
3101 || pool->symbol == NULL
3102 || pool->next_free_entry == 0)
3103 return;
b99bd4ef 3104
c19d1205 3105 mapping_state (MAP_DATA);
b99bd4ef 3106
c19d1205
ZW
3107 /* Align pool as you have word accesses.
3108 Only make a frag if we have to. */
3109 if (!need_pass_2)
3110 frag_align (2, 0, 0);
b99bd4ef 3111
c19d1205 3112 record_alignment (now_seg, 2);
b99bd4ef 3113
c19d1205 3114 sprintf (sym_name, "$$lit_\002%x", pool->id);
b99bd4ef 3115
c19d1205
ZW
3116 symbol_locate (pool->symbol, sym_name, now_seg,
3117 (valueT) frag_now_fix (), frag_now);
3118 symbol_table_insert (pool->symbol);
b99bd4ef 3119
c19d1205 3120 ARM_SET_THUMB (pool->symbol, thumb_mode);
b99bd4ef 3121
c19d1205
ZW
3122#if defined OBJ_COFF || defined OBJ_ELF
3123 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3124#endif
6c43fab6 3125
c19d1205
ZW
3126 for (entry = 0; entry < pool->next_free_entry; entry ++)
3127 /* First output the expression in the instruction to the pool. */
3128 emit_expr (&(pool->literals[entry]), 4); /* .word */
b99bd4ef 3129
c19d1205
ZW
3130 /* Mark the pool as empty. */
3131 pool->next_free_entry = 0;
3132 pool->symbol = NULL;
b99bd4ef
NC
3133}
3134
c19d1205
ZW
3135#ifdef OBJ_ELF
3136/* Forward declarations for functions below, in the MD interface
3137 section. */
3138static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3139static valueT create_unwind_entry (int);
3140static void start_unwind_section (const segT, int);
3141static void add_unwind_opcode (valueT, int);
3142static void flush_pending_unwind (void);
b99bd4ef 3143
c19d1205 3144/* Directives: Data. */
b99bd4ef 3145
c19d1205
ZW
3146static void
3147s_arm_elf_cons (int nbytes)
3148{
3149 expressionS exp;
b99bd4ef 3150
c19d1205
ZW
3151#ifdef md_flush_pending_output
3152 md_flush_pending_output ();
3153#endif
b99bd4ef 3154
c19d1205 3155 if (is_it_end_of_statement ())
b99bd4ef 3156 {
c19d1205
ZW
3157 demand_empty_rest_of_line ();
3158 return;
b99bd4ef
NC
3159 }
3160
c19d1205
ZW
3161#ifdef md_cons_align
3162 md_cons_align (nbytes);
3163#endif
b99bd4ef 3164
c19d1205
ZW
3165 mapping_state (MAP_DATA);
3166 do
b99bd4ef 3167 {
c19d1205
ZW
3168 int reloc;
3169 char *base = input_line_pointer;
b99bd4ef 3170
c19d1205 3171 expression (& exp);
b99bd4ef 3172
c19d1205
ZW
3173 if (exp.X_op != O_symbol)
3174 emit_expr (&exp, (unsigned int) nbytes);
3175 else
3176 {
3177 char *before_reloc = input_line_pointer;
3178 reloc = parse_reloc (&input_line_pointer);
3179 if (reloc == -1)
3180 {
3181 as_bad (_("unrecognized relocation suffix"));
3182 ignore_rest_of_line ();
3183 return;
3184 }
3185 else if (reloc == BFD_RELOC_UNUSED)
3186 emit_expr (&exp, (unsigned int) nbytes);
3187 else
3188 {
21d799b5
NC
3189 reloc_howto_type *howto = (reloc_howto_type *)
3190 bfd_reloc_type_lookup (stdoutput,
3191 (bfd_reloc_code_real_type) reloc);
c19d1205 3192 int size = bfd_get_reloc_size (howto);
b99bd4ef 3193
2fc8bdac
ZW
3194 if (reloc == BFD_RELOC_ARM_PLT32)
3195 {
3196 as_bad (_("(plt) is only valid on branch targets"));
3197 reloc = BFD_RELOC_UNUSED;
3198 size = 0;
3199 }
3200
c19d1205 3201 if (size > nbytes)
2fc8bdac 3202 as_bad (_("%s relocations do not fit in %d bytes"),
c19d1205
ZW
3203 howto->name, nbytes);
3204 else
3205 {
3206 /* We've parsed an expression stopping at O_symbol.
3207 But there may be more expression left now that we
3208 have parsed the relocation marker. Parse it again.
3209 XXX Surely there is a cleaner way to do this. */
3210 char *p = input_line_pointer;
3211 int offset;
21d799b5 3212 char *save_buf = (char *) alloca (input_line_pointer - base);
c19d1205
ZW
3213 memcpy (save_buf, base, input_line_pointer - base);
3214 memmove (base + (input_line_pointer - before_reloc),
3215 base, before_reloc - base);
3216
3217 input_line_pointer = base + (input_line_pointer-before_reloc);
3218 expression (&exp);
3219 memcpy (base, save_buf, p - base);
3220
3221 offset = nbytes - size;
3222 p = frag_more ((int) nbytes);
3223 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
21d799b5 3224 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
c19d1205
ZW
3225 }
3226 }
3227 }
b99bd4ef 3228 }
c19d1205 3229 while (*input_line_pointer++ == ',');
b99bd4ef 3230
c19d1205
ZW
3231 /* Put terminator back into stream. */
3232 input_line_pointer --;
3233 demand_empty_rest_of_line ();
b99bd4ef
NC
3234}
3235
c921be7d
NC
3236/* Emit an expression containing a 32-bit thumb instruction.
3237 Implementation based on put_thumb32_insn. */
3238
3239static void
3240emit_thumb32_expr (expressionS * exp)
3241{
3242 expressionS exp_high = *exp;
3243
3244 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3245 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3246 exp->X_add_number &= 0xffff;
3247 emit_expr (exp, (unsigned int) THUMB_SIZE);
3248}
3249
3250/* Guess the instruction size based on the opcode. */
3251
3252static int
3253thumb_insn_size (int opcode)
3254{
3255 if ((unsigned int) opcode < 0xe800u)
3256 return 2;
3257 else if ((unsigned int) opcode >= 0xe8000000u)
3258 return 4;
3259 else
3260 return 0;
3261}
3262
3263static bfd_boolean
3264emit_insn (expressionS *exp, int nbytes)
3265{
3266 int size = 0;
3267
3268 if (exp->X_op == O_constant)
3269 {
3270 size = nbytes;
3271
3272 if (size == 0)
3273 size = thumb_insn_size (exp->X_add_number);
3274
3275 if (size != 0)
3276 {
3277 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3278 {
3279 as_bad (_(".inst.n operand too big. "\
3280 "Use .inst.w instead"));
3281 size = 0;
3282 }
3283 else
3284 {
3285 if (now_it.state == AUTOMATIC_IT_BLOCK)
3286 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3287 else
3288 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3289
3290 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3291 emit_thumb32_expr (exp);
3292 else
3293 emit_expr (exp, (unsigned int) size);
3294
3295 it_fsm_post_encode ();
3296 }
3297 }
3298 else
3299 as_bad (_("cannot determine Thumb instruction size. " \
3300 "Use .inst.n/.inst.w instead"));
3301 }
3302 else
3303 as_bad (_("constant expression required"));
3304
3305 return (size != 0);
3306}
3307
3308/* Like s_arm_elf_cons but do not use md_cons_align and
3309 set the mapping state to MAP_ARM/MAP_THUMB. */
3310
3311static void
3312s_arm_elf_inst (int nbytes)
3313{
3314 if (is_it_end_of_statement ())
3315 {
3316 demand_empty_rest_of_line ();
3317 return;
3318 }
3319
3320 /* Calling mapping_state () here will not change ARM/THUMB,
3321 but will ensure not to be in DATA state. */
3322
3323 if (thumb_mode)
3324 mapping_state (MAP_THUMB);
3325 else
3326 {
3327 if (nbytes != 0)
3328 {
3329 as_bad (_("width suffixes are invalid in ARM mode"));
3330 ignore_rest_of_line ();
3331 return;
3332 }
3333
3334 nbytes = 4;
3335
3336 mapping_state (MAP_ARM);
3337 }
3338
3339 do
3340 {
3341 expressionS exp;
3342
3343 expression (& exp);
3344
3345 if (! emit_insn (& exp, nbytes))
3346 {
3347 ignore_rest_of_line ();
3348 return;
3349 }
3350 }
3351 while (*input_line_pointer++ == ',');
3352
3353 /* Put terminator back into stream. */
3354 input_line_pointer --;
3355 demand_empty_rest_of_line ();
3356}
b99bd4ef 3357
c19d1205 3358/* Parse a .rel31 directive. */
b99bd4ef 3359
c19d1205
ZW
3360static void
3361s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3362{
3363 expressionS exp;
3364 char *p;
3365 valueT highbit;
b99bd4ef 3366
c19d1205
ZW
3367 highbit = 0;
3368 if (*input_line_pointer == '1')
3369 highbit = 0x80000000;
3370 else if (*input_line_pointer != '0')
3371 as_bad (_("expected 0 or 1"));
b99bd4ef 3372
c19d1205
ZW
3373 input_line_pointer++;
3374 if (*input_line_pointer != ',')
3375 as_bad (_("missing comma"));
3376 input_line_pointer++;
b99bd4ef 3377
c19d1205
ZW
3378#ifdef md_flush_pending_output
3379 md_flush_pending_output ();
3380#endif
b99bd4ef 3381
c19d1205
ZW
3382#ifdef md_cons_align
3383 md_cons_align (4);
3384#endif
b99bd4ef 3385
c19d1205 3386 mapping_state (MAP_DATA);
b99bd4ef 3387
c19d1205 3388 expression (&exp);
b99bd4ef 3389
c19d1205
ZW
3390 p = frag_more (4);
3391 md_number_to_chars (p, highbit, 4);
3392 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3393 BFD_RELOC_ARM_PREL31);
b99bd4ef 3394
c19d1205 3395 demand_empty_rest_of_line ();
b99bd4ef
NC
3396}
3397
c19d1205 3398/* Directives: AEABI stack-unwind tables. */
b99bd4ef 3399
c19d1205 3400/* Parse an unwind_fnstart directive. Simply records the current location. */
b99bd4ef 3401
c19d1205
ZW
3402static void
3403s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3404{
3405 demand_empty_rest_of_line ();
921e5f0a
PB
3406 if (unwind.proc_start)
3407 {
c921be7d 3408 as_bad (_("duplicate .fnstart directive"));
921e5f0a
PB
3409 return;
3410 }
3411
c19d1205
ZW
3412 /* Mark the start of the function. */
3413 unwind.proc_start = expr_build_dot ();
b99bd4ef 3414
c19d1205
ZW
3415 /* Reset the rest of the unwind info. */
3416 unwind.opcode_count = 0;
3417 unwind.table_entry = NULL;
3418 unwind.personality_routine = NULL;
3419 unwind.personality_index = -1;
3420 unwind.frame_size = 0;
3421 unwind.fp_offset = 0;
fdfde340 3422 unwind.fp_reg = REG_SP;
c19d1205
ZW
3423 unwind.fp_used = 0;
3424 unwind.sp_restored = 0;
3425}
b99bd4ef 3426
b99bd4ef 3427
c19d1205
ZW
3428/* Parse a handlerdata directive. Creates the exception handling table entry
3429 for the function. */
b99bd4ef 3430
c19d1205
ZW
3431static void
3432s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3433{
3434 demand_empty_rest_of_line ();
921e5f0a 3435 if (!unwind.proc_start)
c921be7d 3436 as_bad (MISSING_FNSTART);
921e5f0a 3437
c19d1205 3438 if (unwind.table_entry)
6decc662 3439 as_bad (_("duplicate .handlerdata directive"));
f02232aa 3440
c19d1205
ZW
3441 create_unwind_entry (1);
3442}
a737bd4d 3443
c19d1205 3444/* Parse an unwind_fnend directive. Generates the index table entry. */
b99bd4ef 3445
c19d1205
ZW
3446static void
3447s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3448{
3449 long where;
3450 char *ptr;
3451 valueT val;
940b5ce0 3452 unsigned int marked_pr_dependency;
f02232aa 3453
c19d1205 3454 demand_empty_rest_of_line ();
f02232aa 3455
921e5f0a
PB
3456 if (!unwind.proc_start)
3457 {
c921be7d 3458 as_bad (_(".fnend directive without .fnstart"));
921e5f0a
PB
3459 return;
3460 }
3461
c19d1205
ZW
3462 /* Add eh table entry. */
3463 if (unwind.table_entry == NULL)
3464 val = create_unwind_entry (0);
3465 else
3466 val = 0;
f02232aa 3467
c19d1205
ZW
3468 /* Add index table entry. This is two words. */
3469 start_unwind_section (unwind.saved_seg, 1);
3470 frag_align (2, 0, 0);
3471 record_alignment (now_seg, 2);
b99bd4ef 3472
c19d1205
ZW
3473 ptr = frag_more (8);
3474 where = frag_now_fix () - 8;
f02232aa 3475
c19d1205
ZW
3476 /* Self relative offset of the function start. */
3477 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3478 BFD_RELOC_ARM_PREL31);
f02232aa 3479
c19d1205
ZW
3480 /* Indicate dependency on EHABI-defined personality routines to the
3481 linker, if it hasn't been done already. */
940b5ce0
DJ
3482 marked_pr_dependency
3483 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
c19d1205
ZW
3484 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3485 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3486 {
5f4273c7
NC
3487 static const char *const name[] =
3488 {
3489 "__aeabi_unwind_cpp_pr0",
3490 "__aeabi_unwind_cpp_pr1",
3491 "__aeabi_unwind_cpp_pr2"
3492 };
c19d1205
ZW
3493 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3494 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
c19d1205 3495 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
940b5ce0 3496 |= 1 << unwind.personality_index;
c19d1205 3497 }
f02232aa 3498
c19d1205
ZW
3499 if (val)
3500 /* Inline exception table entry. */
3501 md_number_to_chars (ptr + 4, val, 4);
3502 else
3503 /* Self relative offset of the table entry. */
3504 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3505 BFD_RELOC_ARM_PREL31);
f02232aa 3506
c19d1205
ZW
3507 /* Restore the original section. */
3508 subseg_set (unwind.saved_seg, unwind.saved_subseg);
921e5f0a
PB
3509
3510 unwind.proc_start = NULL;
c19d1205 3511}
f02232aa 3512
f02232aa 3513
c19d1205 3514/* Parse an unwind_cantunwind directive. */
b99bd4ef 3515
c19d1205
ZW
3516static void
3517s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3518{
3519 demand_empty_rest_of_line ();
921e5f0a 3520 if (!unwind.proc_start)
c921be7d 3521 as_bad (MISSING_FNSTART);
921e5f0a 3522
c19d1205
ZW
3523 if (unwind.personality_routine || unwind.personality_index != -1)
3524 as_bad (_("personality routine specified for cantunwind frame"));
b99bd4ef 3525
c19d1205
ZW
3526 unwind.personality_index = -2;
3527}
b99bd4ef 3528
b99bd4ef 3529
c19d1205 3530/* Parse a personalityindex directive. */
b99bd4ef 3531
c19d1205
ZW
3532static void
3533s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3534{
3535 expressionS exp;
b99bd4ef 3536
921e5f0a 3537 if (!unwind.proc_start)
c921be7d 3538 as_bad (MISSING_FNSTART);
921e5f0a 3539
c19d1205
ZW
3540 if (unwind.personality_routine || unwind.personality_index != -1)
3541 as_bad (_("duplicate .personalityindex directive"));
b99bd4ef 3542
c19d1205 3543 expression (&exp);
b99bd4ef 3544
c19d1205
ZW
3545 if (exp.X_op != O_constant
3546 || exp.X_add_number < 0 || exp.X_add_number > 15)
b99bd4ef 3547 {
c19d1205
ZW
3548 as_bad (_("bad personality routine number"));
3549 ignore_rest_of_line ();
3550 return;
b99bd4ef
NC
3551 }
3552
c19d1205 3553 unwind.personality_index = exp.X_add_number;
b99bd4ef 3554
c19d1205
ZW
3555 demand_empty_rest_of_line ();
3556}
e16bb312 3557
e16bb312 3558
c19d1205 3559/* Parse a personality directive. */
e16bb312 3560
c19d1205
ZW
3561static void
3562s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3563{
3564 char *name, *p, c;
a737bd4d 3565
921e5f0a 3566 if (!unwind.proc_start)
c921be7d 3567 as_bad (MISSING_FNSTART);
921e5f0a 3568
c19d1205
ZW
3569 if (unwind.personality_routine || unwind.personality_index != -1)
3570 as_bad (_("duplicate .personality directive"));
a737bd4d 3571
c19d1205
ZW
3572 name = input_line_pointer;
3573 c = get_symbol_end ();
3574 p = input_line_pointer;
3575 unwind.personality_routine = symbol_find_or_make (name);
3576 *p = c;
3577 demand_empty_rest_of_line ();
3578}
e16bb312 3579
e16bb312 3580
c19d1205 3581/* Parse a directive saving core registers. */
e16bb312 3582
c19d1205
ZW
3583static void
3584s_arm_unwind_save_core (void)
e16bb312 3585{
c19d1205
ZW
3586 valueT op;
3587 long range;
3588 int n;
e16bb312 3589
c19d1205
ZW
3590 range = parse_reg_list (&input_line_pointer);
3591 if (range == FAIL)
e16bb312 3592 {
c19d1205
ZW
3593 as_bad (_("expected register list"));
3594 ignore_rest_of_line ();
3595 return;
3596 }
e16bb312 3597
c19d1205 3598 demand_empty_rest_of_line ();
e16bb312 3599
c19d1205
ZW
3600 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3601 into .unwind_save {..., sp...}. We aren't bothered about the value of
3602 ip because it is clobbered by calls. */
3603 if (unwind.sp_restored && unwind.fp_reg == 12
3604 && (range & 0x3000) == 0x1000)
3605 {
3606 unwind.opcode_count--;
3607 unwind.sp_restored = 0;
3608 range = (range | 0x2000) & ~0x1000;
3609 unwind.pending_offset = 0;
3610 }
e16bb312 3611
01ae4198
DJ
3612 /* Pop r4-r15. */
3613 if (range & 0xfff0)
c19d1205 3614 {
01ae4198
DJ
3615 /* See if we can use the short opcodes. These pop a block of up to 8
3616 registers starting with r4, plus maybe r14. */
3617 for (n = 0; n < 8; n++)
3618 {
3619 /* Break at the first non-saved register. */
3620 if ((range & (1 << (n + 4))) == 0)
3621 break;
3622 }
3623 /* See if there are any other bits set. */
3624 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3625 {
3626 /* Use the long form. */
3627 op = 0x8000 | ((range >> 4) & 0xfff);
3628 add_unwind_opcode (op, 2);
3629 }
0dd132b6 3630 else
01ae4198
DJ
3631 {
3632 /* Use the short form. */
3633 if (range & 0x4000)
3634 op = 0xa8; /* Pop r14. */
3635 else
3636 op = 0xa0; /* Do not pop r14. */
3637 op |= (n - 1);
3638 add_unwind_opcode (op, 1);
3639 }
c19d1205 3640 }
0dd132b6 3641
c19d1205
ZW
3642 /* Pop r0-r3. */
3643 if (range & 0xf)
3644 {
3645 op = 0xb100 | (range & 0xf);
3646 add_unwind_opcode (op, 2);
0dd132b6
NC
3647 }
3648
c19d1205
ZW
3649 /* Record the number of bytes pushed. */
3650 for (n = 0; n < 16; n++)
3651 {
3652 if (range & (1 << n))
3653 unwind.frame_size += 4;
3654 }
0dd132b6
NC
3655}
3656
c19d1205
ZW
3657
3658/* Parse a directive saving FPA registers. */
b99bd4ef
NC
3659
3660static void
c19d1205 3661s_arm_unwind_save_fpa (int reg)
b99bd4ef 3662{
c19d1205
ZW
3663 expressionS exp;
3664 int num_regs;
3665 valueT op;
b99bd4ef 3666
c19d1205
ZW
3667 /* Get Number of registers to transfer. */
3668 if (skip_past_comma (&input_line_pointer) != FAIL)
3669 expression (&exp);
3670 else
3671 exp.X_op = O_illegal;
b99bd4ef 3672
c19d1205 3673 if (exp.X_op != O_constant)
b99bd4ef 3674 {
c19d1205
ZW
3675 as_bad (_("expected , <constant>"));
3676 ignore_rest_of_line ();
b99bd4ef
NC
3677 return;
3678 }
3679
c19d1205
ZW
3680 num_regs = exp.X_add_number;
3681
3682 if (num_regs < 1 || num_regs > 4)
b99bd4ef 3683 {
c19d1205
ZW
3684 as_bad (_("number of registers must be in the range [1:4]"));
3685 ignore_rest_of_line ();
b99bd4ef
NC
3686 return;
3687 }
3688
c19d1205 3689 demand_empty_rest_of_line ();
b99bd4ef 3690
c19d1205
ZW
3691 if (reg == 4)
3692 {
3693 /* Short form. */
3694 op = 0xb4 | (num_regs - 1);
3695 add_unwind_opcode (op, 1);
3696 }
b99bd4ef
NC
3697 else
3698 {
c19d1205
ZW
3699 /* Long form. */
3700 op = 0xc800 | (reg << 4) | (num_regs - 1);
3701 add_unwind_opcode (op, 2);
b99bd4ef 3702 }
c19d1205 3703 unwind.frame_size += num_regs * 12;
b99bd4ef
NC
3704}
3705
c19d1205 3706
fa073d69
MS
3707/* Parse a directive saving VFP registers for ARMv6 and above. */
3708
3709static void
3710s_arm_unwind_save_vfp_armv6 (void)
3711{
3712 int count;
3713 unsigned int start;
3714 valueT op;
3715 int num_vfpv3_regs = 0;
3716 int num_regs_below_16;
3717
3718 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3719 if (count == FAIL)
3720 {
3721 as_bad (_("expected register list"));
3722 ignore_rest_of_line ();
3723 return;
3724 }
3725
3726 demand_empty_rest_of_line ();
3727
3728 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3729 than FSTMX/FLDMX-style ones). */
3730
3731 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3732 if (start >= 16)
3733 num_vfpv3_regs = count;
3734 else if (start + count > 16)
3735 num_vfpv3_regs = start + count - 16;
3736
3737 if (num_vfpv3_regs > 0)
3738 {
3739 int start_offset = start > 16 ? start - 16 : 0;
3740 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3741 add_unwind_opcode (op, 2);
3742 }
3743
3744 /* Generate opcode for registers numbered in the range 0 .. 15. */
3745 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
9c2799c2 3746 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
fa073d69
MS
3747 if (num_regs_below_16 > 0)
3748 {
3749 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3750 add_unwind_opcode (op, 2);
3751 }
3752
3753 unwind.frame_size += count * 8;
3754}
3755
3756
3757/* Parse a directive saving VFP registers for pre-ARMv6. */
b99bd4ef
NC
3758
3759static void
c19d1205 3760s_arm_unwind_save_vfp (void)
b99bd4ef 3761{
c19d1205 3762 int count;
ca3f61f7 3763 unsigned int reg;
c19d1205 3764 valueT op;
b99bd4ef 3765
5287ad62 3766 count = parse_vfp_reg_list (&input_line_pointer, &reg, REGLIST_VFP_D);
c19d1205 3767 if (count == FAIL)
b99bd4ef 3768 {
c19d1205
ZW
3769 as_bad (_("expected register list"));
3770 ignore_rest_of_line ();
b99bd4ef
NC
3771 return;
3772 }
3773
c19d1205 3774 demand_empty_rest_of_line ();
b99bd4ef 3775
c19d1205 3776 if (reg == 8)
b99bd4ef 3777 {
c19d1205
ZW
3778 /* Short form. */
3779 op = 0xb8 | (count - 1);
3780 add_unwind_opcode (op, 1);
b99bd4ef 3781 }
c19d1205 3782 else
b99bd4ef 3783 {
c19d1205
ZW
3784 /* Long form. */
3785 op = 0xb300 | (reg << 4) | (count - 1);
3786 add_unwind_opcode (op, 2);
b99bd4ef 3787 }
c19d1205
ZW
3788 unwind.frame_size += count * 8 + 4;
3789}
b99bd4ef 3790
b99bd4ef 3791
c19d1205
ZW
3792/* Parse a directive saving iWMMXt data registers. */
3793
3794static void
3795s_arm_unwind_save_mmxwr (void)
3796{
3797 int reg;
3798 int hi_reg;
3799 int i;
3800 unsigned mask = 0;
3801 valueT op;
b99bd4ef 3802
c19d1205
ZW
3803 if (*input_line_pointer == '{')
3804 input_line_pointer++;
b99bd4ef 3805
c19d1205 3806 do
b99bd4ef 3807 {
dcbf9037 3808 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
b99bd4ef 3809
c19d1205 3810 if (reg == FAIL)
b99bd4ef 3811 {
9b7132d3 3812 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
c19d1205 3813 goto error;
b99bd4ef
NC
3814 }
3815
c19d1205
ZW
3816 if (mask >> reg)
3817 as_tsktsk (_("register list not in ascending order"));
3818 mask |= 1 << reg;
b99bd4ef 3819
c19d1205
ZW
3820 if (*input_line_pointer == '-')
3821 {
3822 input_line_pointer++;
dcbf9037 3823 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
c19d1205
ZW
3824 if (hi_reg == FAIL)
3825 {
9b7132d3 3826 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
c19d1205
ZW
3827 goto error;
3828 }
3829 else if (reg >= hi_reg)
3830 {
3831 as_bad (_("bad register range"));
3832 goto error;
3833 }
3834 for (; reg < hi_reg; reg++)
3835 mask |= 1 << reg;
3836 }
3837 }
3838 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 3839
c19d1205
ZW
3840 if (*input_line_pointer == '}')
3841 input_line_pointer++;
b99bd4ef 3842
c19d1205 3843 demand_empty_rest_of_line ();
b99bd4ef 3844
708587a4 3845 /* Generate any deferred opcodes because we're going to be looking at
c19d1205
ZW
3846 the list. */
3847 flush_pending_unwind ();
b99bd4ef 3848
c19d1205 3849 for (i = 0; i < 16; i++)
b99bd4ef 3850 {
c19d1205
ZW
3851 if (mask & (1 << i))
3852 unwind.frame_size += 8;
b99bd4ef
NC
3853 }
3854
c19d1205
ZW
3855 /* Attempt to combine with a previous opcode. We do this because gcc
3856 likes to output separate unwind directives for a single block of
3857 registers. */
3858 if (unwind.opcode_count > 0)
b99bd4ef 3859 {
c19d1205
ZW
3860 i = unwind.opcodes[unwind.opcode_count - 1];
3861 if ((i & 0xf8) == 0xc0)
3862 {
3863 i &= 7;
3864 /* Only merge if the blocks are contiguous. */
3865 if (i < 6)
3866 {
3867 if ((mask & 0xfe00) == (1 << 9))
3868 {
3869 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3870 unwind.opcode_count--;
3871 }
3872 }
3873 else if (i == 6 && unwind.opcode_count >= 2)
3874 {
3875 i = unwind.opcodes[unwind.opcode_count - 2];
3876 reg = i >> 4;
3877 i &= 0xf;
b99bd4ef 3878
c19d1205
ZW
3879 op = 0xffff << (reg - 1);
3880 if (reg > 0
87a1fd79 3881 && ((mask & op) == (1u << (reg - 1))))
c19d1205
ZW
3882 {
3883 op = (1 << (reg + i + 1)) - 1;
3884 op &= ~((1 << reg) - 1);
3885 mask |= op;
3886 unwind.opcode_count -= 2;
3887 }
3888 }
3889 }
b99bd4ef
NC
3890 }
3891
c19d1205
ZW
3892 hi_reg = 15;
3893 /* We want to generate opcodes in the order the registers have been
3894 saved, ie. descending order. */
3895 for (reg = 15; reg >= -1; reg--)
b99bd4ef 3896 {
c19d1205
ZW
3897 /* Save registers in blocks. */
3898 if (reg < 0
3899 || !(mask & (1 << reg)))
3900 {
3901 /* We found an unsaved reg. Generate opcodes to save the
5f4273c7 3902 preceding block. */
c19d1205
ZW
3903 if (reg != hi_reg)
3904 {
3905 if (reg == 9)
3906 {
3907 /* Short form. */
3908 op = 0xc0 | (hi_reg - 10);
3909 add_unwind_opcode (op, 1);
3910 }
3911 else
3912 {
3913 /* Long form. */
3914 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
3915 add_unwind_opcode (op, 2);
3916 }
3917 }
3918 hi_reg = reg - 1;
3919 }
b99bd4ef
NC
3920 }
3921
c19d1205
ZW
3922 return;
3923error:
3924 ignore_rest_of_line ();
b99bd4ef
NC
3925}
3926
3927static void
c19d1205 3928s_arm_unwind_save_mmxwcg (void)
b99bd4ef 3929{
c19d1205
ZW
3930 int reg;
3931 int hi_reg;
3932 unsigned mask = 0;
3933 valueT op;
b99bd4ef 3934
c19d1205
ZW
3935 if (*input_line_pointer == '{')
3936 input_line_pointer++;
b99bd4ef 3937
c19d1205 3938 do
b99bd4ef 3939 {
dcbf9037 3940 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
b99bd4ef 3941
c19d1205
ZW
3942 if (reg == FAIL)
3943 {
9b7132d3 3944 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
c19d1205
ZW
3945 goto error;
3946 }
b99bd4ef 3947
c19d1205
ZW
3948 reg -= 8;
3949 if (mask >> reg)
3950 as_tsktsk (_("register list not in ascending order"));
3951 mask |= 1 << reg;
b99bd4ef 3952
c19d1205
ZW
3953 if (*input_line_pointer == '-')
3954 {
3955 input_line_pointer++;
dcbf9037 3956 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
c19d1205
ZW
3957 if (hi_reg == FAIL)
3958 {
9b7132d3 3959 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
c19d1205
ZW
3960 goto error;
3961 }
3962 else if (reg >= hi_reg)
3963 {
3964 as_bad (_("bad register range"));
3965 goto error;
3966 }
3967 for (; reg < hi_reg; reg++)
3968 mask |= 1 << reg;
3969 }
b99bd4ef 3970 }
c19d1205 3971 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 3972
c19d1205
ZW
3973 if (*input_line_pointer == '}')
3974 input_line_pointer++;
b99bd4ef 3975
c19d1205
ZW
3976 demand_empty_rest_of_line ();
3977
708587a4 3978 /* Generate any deferred opcodes because we're going to be looking at
c19d1205
ZW
3979 the list. */
3980 flush_pending_unwind ();
b99bd4ef 3981
c19d1205 3982 for (reg = 0; reg < 16; reg++)
b99bd4ef 3983 {
c19d1205
ZW
3984 if (mask & (1 << reg))
3985 unwind.frame_size += 4;
b99bd4ef 3986 }
c19d1205
ZW
3987 op = 0xc700 | mask;
3988 add_unwind_opcode (op, 2);
3989 return;
3990error:
3991 ignore_rest_of_line ();
b99bd4ef
NC
3992}
3993
c19d1205 3994
fa073d69
MS
3995/* Parse an unwind_save directive.
3996 If the argument is non-zero, this is a .vsave directive. */
c19d1205 3997
b99bd4ef 3998static void
fa073d69 3999s_arm_unwind_save (int arch_v6)
b99bd4ef 4000{
c19d1205
ZW
4001 char *peek;
4002 struct reg_entry *reg;
4003 bfd_boolean had_brace = FALSE;
b99bd4ef 4004
921e5f0a 4005 if (!unwind.proc_start)
c921be7d 4006 as_bad (MISSING_FNSTART);
921e5f0a 4007
c19d1205
ZW
4008 /* Figure out what sort of save we have. */
4009 peek = input_line_pointer;
b99bd4ef 4010
c19d1205 4011 if (*peek == '{')
b99bd4ef 4012 {
c19d1205
ZW
4013 had_brace = TRUE;
4014 peek++;
b99bd4ef
NC
4015 }
4016
c19d1205 4017 reg = arm_reg_parse_multi (&peek);
b99bd4ef 4018
c19d1205 4019 if (!reg)
b99bd4ef 4020 {
c19d1205
ZW
4021 as_bad (_("register expected"));
4022 ignore_rest_of_line ();
b99bd4ef
NC
4023 return;
4024 }
4025
c19d1205 4026 switch (reg->type)
b99bd4ef 4027 {
c19d1205
ZW
4028 case REG_TYPE_FN:
4029 if (had_brace)
4030 {
4031 as_bad (_("FPA .unwind_save does not take a register list"));
4032 ignore_rest_of_line ();
4033 return;
4034 }
93ac2687 4035 input_line_pointer = peek;
c19d1205 4036 s_arm_unwind_save_fpa (reg->number);
b99bd4ef 4037 return;
c19d1205
ZW
4038
4039 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
fa073d69
MS
4040 case REG_TYPE_VFD:
4041 if (arch_v6)
4042 s_arm_unwind_save_vfp_armv6 ();
4043 else
4044 s_arm_unwind_save_vfp ();
4045 return;
c19d1205
ZW
4046 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4047 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4048
4049 default:
4050 as_bad (_(".unwind_save does not support this kind of register"));
4051 ignore_rest_of_line ();
b99bd4ef 4052 }
c19d1205 4053}
b99bd4ef 4054
b99bd4ef 4055
c19d1205
ZW
4056/* Parse an unwind_movsp directive. */
4057
4058static void
4059s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4060{
4061 int reg;
4062 valueT op;
4fa3602b 4063 int offset;
c19d1205 4064
921e5f0a 4065 if (!unwind.proc_start)
c921be7d 4066 as_bad (MISSING_FNSTART);
921e5f0a 4067
dcbf9037 4068 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
c19d1205 4069 if (reg == FAIL)
b99bd4ef 4070 {
9b7132d3 4071 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
c19d1205 4072 ignore_rest_of_line ();
b99bd4ef
NC
4073 return;
4074 }
4fa3602b
PB
4075
4076 /* Optional constant. */
4077 if (skip_past_comma (&input_line_pointer) != FAIL)
4078 {
4079 if (immediate_for_directive (&offset) == FAIL)
4080 return;
4081 }
4082 else
4083 offset = 0;
4084
c19d1205 4085 demand_empty_rest_of_line ();
b99bd4ef 4086
c19d1205 4087 if (reg == REG_SP || reg == REG_PC)
b99bd4ef 4088 {
c19d1205 4089 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
b99bd4ef
NC
4090 return;
4091 }
4092
c19d1205
ZW
4093 if (unwind.fp_reg != REG_SP)
4094 as_bad (_("unexpected .unwind_movsp directive"));
b99bd4ef 4095
c19d1205
ZW
4096 /* Generate opcode to restore the value. */
4097 op = 0x90 | reg;
4098 add_unwind_opcode (op, 1);
4099
4100 /* Record the information for later. */
4101 unwind.fp_reg = reg;
4fa3602b 4102 unwind.fp_offset = unwind.frame_size - offset;
c19d1205 4103 unwind.sp_restored = 1;
b05fe5cf
ZW
4104}
4105
c19d1205
ZW
4106/* Parse an unwind_pad directive. */
4107
b05fe5cf 4108static void
c19d1205 4109s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
b05fe5cf 4110{
c19d1205 4111 int offset;
b05fe5cf 4112
921e5f0a 4113 if (!unwind.proc_start)
c921be7d 4114 as_bad (MISSING_FNSTART);
921e5f0a 4115
c19d1205
ZW
4116 if (immediate_for_directive (&offset) == FAIL)
4117 return;
b99bd4ef 4118
c19d1205
ZW
4119 if (offset & 3)
4120 {
4121 as_bad (_("stack increment must be multiple of 4"));
4122 ignore_rest_of_line ();
4123 return;
4124 }
b99bd4ef 4125
c19d1205
ZW
4126 /* Don't generate any opcodes, just record the details for later. */
4127 unwind.frame_size += offset;
4128 unwind.pending_offset += offset;
4129
4130 demand_empty_rest_of_line ();
4131}
4132
4133/* Parse an unwind_setfp directive. */
4134
4135static void
4136s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 4137{
c19d1205
ZW
4138 int sp_reg;
4139 int fp_reg;
4140 int offset;
4141
921e5f0a 4142 if (!unwind.proc_start)
c921be7d 4143 as_bad (MISSING_FNSTART);
921e5f0a 4144
dcbf9037 4145 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
c19d1205
ZW
4146 if (skip_past_comma (&input_line_pointer) == FAIL)
4147 sp_reg = FAIL;
4148 else
dcbf9037 4149 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
b99bd4ef 4150
c19d1205
ZW
4151 if (fp_reg == FAIL || sp_reg == FAIL)
4152 {
4153 as_bad (_("expected <reg>, <reg>"));
4154 ignore_rest_of_line ();
4155 return;
4156 }
b99bd4ef 4157
c19d1205
ZW
4158 /* Optional constant. */
4159 if (skip_past_comma (&input_line_pointer) != FAIL)
4160 {
4161 if (immediate_for_directive (&offset) == FAIL)
4162 return;
4163 }
4164 else
4165 offset = 0;
a737bd4d 4166
c19d1205 4167 demand_empty_rest_of_line ();
a737bd4d 4168
fdfde340 4169 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
a737bd4d 4170 {
c19d1205
ZW
4171 as_bad (_("register must be either sp or set by a previous"
4172 "unwind_movsp directive"));
4173 return;
a737bd4d
NC
4174 }
4175
c19d1205
ZW
4176 /* Don't generate any opcodes, just record the information for later. */
4177 unwind.fp_reg = fp_reg;
4178 unwind.fp_used = 1;
fdfde340 4179 if (sp_reg == REG_SP)
c19d1205
ZW
4180 unwind.fp_offset = unwind.frame_size - offset;
4181 else
4182 unwind.fp_offset -= offset;
a737bd4d
NC
4183}
4184
c19d1205
ZW
4185/* Parse an unwind_raw directive. */
4186
4187static void
4188s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
a737bd4d 4189{
c19d1205 4190 expressionS exp;
708587a4 4191 /* This is an arbitrary limit. */
c19d1205
ZW
4192 unsigned char op[16];
4193 int count;
a737bd4d 4194
921e5f0a 4195 if (!unwind.proc_start)
c921be7d 4196 as_bad (MISSING_FNSTART);
921e5f0a 4197
c19d1205
ZW
4198 expression (&exp);
4199 if (exp.X_op == O_constant
4200 && skip_past_comma (&input_line_pointer) != FAIL)
a737bd4d 4201 {
c19d1205
ZW
4202 unwind.frame_size += exp.X_add_number;
4203 expression (&exp);
4204 }
4205 else
4206 exp.X_op = O_illegal;
a737bd4d 4207
c19d1205
ZW
4208 if (exp.X_op != O_constant)
4209 {
4210 as_bad (_("expected <offset>, <opcode>"));
4211 ignore_rest_of_line ();
4212 return;
4213 }
a737bd4d 4214
c19d1205 4215 count = 0;
a737bd4d 4216
c19d1205
ZW
4217 /* Parse the opcode. */
4218 for (;;)
4219 {
4220 if (count >= 16)
4221 {
4222 as_bad (_("unwind opcode too long"));
4223 ignore_rest_of_line ();
a737bd4d 4224 }
c19d1205 4225 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
a737bd4d 4226 {
c19d1205
ZW
4227 as_bad (_("invalid unwind opcode"));
4228 ignore_rest_of_line ();
4229 return;
a737bd4d 4230 }
c19d1205 4231 op[count++] = exp.X_add_number;
a737bd4d 4232
c19d1205
ZW
4233 /* Parse the next byte. */
4234 if (skip_past_comma (&input_line_pointer) == FAIL)
4235 break;
a737bd4d 4236
c19d1205
ZW
4237 expression (&exp);
4238 }
b99bd4ef 4239
c19d1205
ZW
4240 /* Add the opcode bytes in reverse order. */
4241 while (count--)
4242 add_unwind_opcode (op[count], 1);
b99bd4ef 4243
c19d1205 4244 demand_empty_rest_of_line ();
b99bd4ef 4245}
ee065d83
PB
4246
4247
4248/* Parse a .eabi_attribute directive. */
4249
4250static void
4251s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4252{
ee3c0378
AS
4253 int tag = s_vendor_attribute (OBJ_ATTR_PROC);
4254
4255 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4256 attributes_set_explicitly[tag] = 1;
ee065d83 4257}
8463be01 4258#endif /* OBJ_ELF */
ee065d83
PB
4259
4260static void s_arm_arch (int);
7a1d4c38 4261static void s_arm_object_arch (int);
ee065d83
PB
4262static void s_arm_cpu (int);
4263static void s_arm_fpu (int);
b99bd4ef 4264
f0927246
NC
4265#ifdef TE_PE
4266
4267static void
5f4273c7 4268pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
f0927246
NC
4269{
4270 expressionS exp;
4271
4272 do
4273 {
4274 expression (&exp);
4275 if (exp.X_op == O_symbol)
4276 exp.X_op = O_secrel;
4277
4278 emit_expr (&exp, 4);
4279 }
4280 while (*input_line_pointer++ == ',');
4281
4282 input_line_pointer--;
4283 demand_empty_rest_of_line ();
4284}
4285#endif /* TE_PE */
4286
c19d1205
ZW
4287/* This table describes all the machine specific pseudo-ops the assembler
4288 has to support. The fields are:
4289 pseudo-op name without dot
4290 function to call to execute this pseudo-op
4291 Integer arg to pass to the function. */
b99bd4ef 4292
c19d1205 4293const pseudo_typeS md_pseudo_table[] =
b99bd4ef 4294{
c19d1205
ZW
4295 /* Never called because '.req' does not start a line. */
4296 { "req", s_req, 0 },
dcbf9037
JB
4297 /* Following two are likewise never called. */
4298 { "dn", s_dn, 0 },
4299 { "qn", s_qn, 0 },
c19d1205
ZW
4300 { "unreq", s_unreq, 0 },
4301 { "bss", s_bss, 0 },
4302 { "align", s_align, 0 },
4303 { "arm", s_arm, 0 },
4304 { "thumb", s_thumb, 0 },
4305 { "code", s_code, 0 },
4306 { "force_thumb", s_force_thumb, 0 },
4307 { "thumb_func", s_thumb_func, 0 },
4308 { "thumb_set", s_thumb_set, 0 },
4309 { "even", s_even, 0 },
4310 { "ltorg", s_ltorg, 0 },
4311 { "pool", s_ltorg, 0 },
4312 { "syntax", s_syntax, 0 },
8463be01
PB
4313 { "cpu", s_arm_cpu, 0 },
4314 { "arch", s_arm_arch, 0 },
7a1d4c38 4315 { "object_arch", s_arm_object_arch, 0 },
8463be01 4316 { "fpu", s_arm_fpu, 0 },
c19d1205 4317#ifdef OBJ_ELF
c921be7d
NC
4318 { "word", s_arm_elf_cons, 4 },
4319 { "long", s_arm_elf_cons, 4 },
4320 { "inst.n", s_arm_elf_inst, 2 },
4321 { "inst.w", s_arm_elf_inst, 4 },
4322 { "inst", s_arm_elf_inst, 0 },
4323 { "rel31", s_arm_rel31, 0 },
c19d1205
ZW
4324 { "fnstart", s_arm_unwind_fnstart, 0 },
4325 { "fnend", s_arm_unwind_fnend, 0 },
4326 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4327 { "personality", s_arm_unwind_personality, 0 },
4328 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4329 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4330 { "save", s_arm_unwind_save, 0 },
fa073d69 4331 { "vsave", s_arm_unwind_save, 1 },
c19d1205
ZW
4332 { "movsp", s_arm_unwind_movsp, 0 },
4333 { "pad", s_arm_unwind_pad, 0 },
4334 { "setfp", s_arm_unwind_setfp, 0 },
4335 { "unwind_raw", s_arm_unwind_raw, 0 },
ee065d83 4336 { "eabi_attribute", s_arm_eabi_attribute, 0 },
c19d1205
ZW
4337#else
4338 { "word", cons, 4},
f0927246
NC
4339
4340 /* These are used for dwarf. */
4341 {"2byte", cons, 2},
4342 {"4byte", cons, 4},
4343 {"8byte", cons, 8},
4344 /* These are used for dwarf2. */
4345 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4346 { "loc", dwarf2_directive_loc, 0 },
4347 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
c19d1205
ZW
4348#endif
4349 { "extend", float_cons, 'x' },
4350 { "ldouble", float_cons, 'x' },
4351 { "packed", float_cons, 'p' },
f0927246
NC
4352#ifdef TE_PE
4353 {"secrel32", pe_directive_secrel, 0},
4354#endif
c19d1205
ZW
4355 { 0, 0, 0 }
4356};
4357\f
4358/* Parser functions used exclusively in instruction operands. */
b99bd4ef 4359
c19d1205
ZW
4360/* Generic immediate-value read function for use in insn parsing.
4361 STR points to the beginning of the immediate (the leading #);
4362 VAL receives the value; if the value is outside [MIN, MAX]
4363 issue an error. PREFIX_OPT is true if the immediate prefix is
4364 optional. */
b99bd4ef 4365
c19d1205
ZW
4366static int
4367parse_immediate (char **str, int *val, int min, int max,
4368 bfd_boolean prefix_opt)
4369{
4370 expressionS exp;
4371 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4372 if (exp.X_op != O_constant)
b99bd4ef 4373 {
c19d1205
ZW
4374 inst.error = _("constant expression required");
4375 return FAIL;
4376 }
b99bd4ef 4377
c19d1205
ZW
4378 if (exp.X_add_number < min || exp.X_add_number > max)
4379 {
4380 inst.error = _("immediate value out of range");
4381 return FAIL;
4382 }
b99bd4ef 4383
c19d1205
ZW
4384 *val = exp.X_add_number;
4385 return SUCCESS;
4386}
b99bd4ef 4387
5287ad62 4388/* Less-generic immediate-value read function with the possibility of loading a
036dc3f7 4389 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5287ad62
JB
4390 instructions. Puts the result directly in inst.operands[i]. */
4391
4392static int
4393parse_big_immediate (char **str, int i)
4394{
4395 expressionS exp;
4396 char *ptr = *str;
4397
4398 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4399
4400 if (exp.X_op == O_constant)
036dc3f7
PB
4401 {
4402 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4403 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4404 O_constant. We have to be careful not to break compilation for
4405 32-bit X_add_number, though. */
4406 if ((exp.X_add_number & ~0xffffffffl) != 0)
4407 {
4408 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4409 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4410 inst.operands[i].regisimm = 1;
4411 }
4412 }
5287ad62
JB
4413 else if (exp.X_op == O_big
4414 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32
4415 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64)
4416 {
4417 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4418 /* Bignums have their least significant bits in
4419 generic_bignum[0]. Make sure we put 32 bits in imm and
4420 32 bits in reg, in a (hopefully) portable way. */
9c2799c2 4421 gas_assert (parts != 0);
5287ad62
JB
4422 inst.operands[i].imm = 0;
4423 for (j = 0; j < parts; j++, idx++)
4424 inst.operands[i].imm |= generic_bignum[idx]
4425 << (LITTLENUM_NUMBER_OF_BITS * j);
4426 inst.operands[i].reg = 0;
4427 for (j = 0; j < parts; j++, idx++)
4428 inst.operands[i].reg |= generic_bignum[idx]
4429 << (LITTLENUM_NUMBER_OF_BITS * j);
4430 inst.operands[i].regisimm = 1;
4431 }
4432 else
4433 return FAIL;
5f4273c7 4434
5287ad62
JB
4435 *str = ptr;
4436
4437 return SUCCESS;
4438}
4439
c19d1205
ZW
4440/* Returns the pseudo-register number of an FPA immediate constant,
4441 or FAIL if there isn't a valid constant here. */
b99bd4ef 4442
c19d1205
ZW
4443static int
4444parse_fpa_immediate (char ** str)
4445{
4446 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4447 char * save_in;
4448 expressionS exp;
4449 int i;
4450 int j;
b99bd4ef 4451
c19d1205
ZW
4452 /* First try and match exact strings, this is to guarantee
4453 that some formats will work even for cross assembly. */
b99bd4ef 4454
c19d1205
ZW
4455 for (i = 0; fp_const[i]; i++)
4456 {
4457 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
b99bd4ef 4458 {
c19d1205 4459 char *start = *str;
b99bd4ef 4460
c19d1205
ZW
4461 *str += strlen (fp_const[i]);
4462 if (is_end_of_line[(unsigned char) **str])
4463 return i + 8;
4464 *str = start;
4465 }
4466 }
b99bd4ef 4467
c19d1205
ZW
4468 /* Just because we didn't get a match doesn't mean that the constant
4469 isn't valid, just that it is in a format that we don't
4470 automatically recognize. Try parsing it with the standard
4471 expression routines. */
b99bd4ef 4472
c19d1205 4473 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
b99bd4ef 4474
c19d1205
ZW
4475 /* Look for a raw floating point number. */
4476 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4477 && is_end_of_line[(unsigned char) *save_in])
4478 {
4479 for (i = 0; i < NUM_FLOAT_VALS; i++)
4480 {
4481 for (j = 0; j < MAX_LITTLENUMS; j++)
b99bd4ef 4482 {
c19d1205
ZW
4483 if (words[j] != fp_values[i][j])
4484 break;
b99bd4ef
NC
4485 }
4486
c19d1205 4487 if (j == MAX_LITTLENUMS)
b99bd4ef 4488 {
c19d1205
ZW
4489 *str = save_in;
4490 return i + 8;
b99bd4ef
NC
4491 }
4492 }
4493 }
b99bd4ef 4494
c19d1205
ZW
4495 /* Try and parse a more complex expression, this will probably fail
4496 unless the code uses a floating point prefix (eg "0f"). */
4497 save_in = input_line_pointer;
4498 input_line_pointer = *str;
4499 if (expression (&exp) == absolute_section
4500 && exp.X_op == O_big
4501 && exp.X_add_number < 0)
4502 {
4503 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4504 Ditto for 15. */
4505 if (gen_to_words (words, 5, (long) 15) == 0)
4506 {
4507 for (i = 0; i < NUM_FLOAT_VALS; i++)
4508 {
4509 for (j = 0; j < MAX_LITTLENUMS; j++)
4510 {
4511 if (words[j] != fp_values[i][j])
4512 break;
4513 }
b99bd4ef 4514
c19d1205
ZW
4515 if (j == MAX_LITTLENUMS)
4516 {
4517 *str = input_line_pointer;
4518 input_line_pointer = save_in;
4519 return i + 8;
4520 }
4521 }
4522 }
b99bd4ef
NC
4523 }
4524
c19d1205
ZW
4525 *str = input_line_pointer;
4526 input_line_pointer = save_in;
4527 inst.error = _("invalid FPA immediate expression");
4528 return FAIL;
b99bd4ef
NC
4529}
4530
136da414
JB
4531/* Returns 1 if a number has "quarter-precision" float format
4532 0baBbbbbbc defgh000 00000000 00000000. */
4533
4534static int
4535is_quarter_float (unsigned imm)
4536{
4537 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4538 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4539}
4540
4541/* Parse an 8-bit "quarter-precision" floating point number of the form:
4542 0baBbbbbbc defgh000 00000000 00000000.
c96612cc
JB
4543 The zero and minus-zero cases need special handling, since they can't be
4544 encoded in the "quarter-precision" float format, but can nonetheless be
4545 loaded as integer constants. */
136da414
JB
4546
4547static unsigned
4548parse_qfloat_immediate (char **ccp, int *immed)
4549{
4550 char *str = *ccp;
c96612cc 4551 char *fpnum;
136da414 4552 LITTLENUM_TYPE words[MAX_LITTLENUMS];
c96612cc 4553 int found_fpchar = 0;
5f4273c7 4554
136da414 4555 skip_past_char (&str, '#');
5f4273c7 4556
c96612cc
JB
4557 /* We must not accidentally parse an integer as a floating-point number. Make
4558 sure that the value we parse is not an integer by checking for special
4559 characters '.' or 'e'.
4560 FIXME: This is a horrible hack, but doing better is tricky because type
4561 information isn't in a very usable state at parse time. */
4562 fpnum = str;
4563 skip_whitespace (fpnum);
4564
4565 if (strncmp (fpnum, "0x", 2) == 0)
4566 return FAIL;
4567 else
4568 {
4569 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4570 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4571 {
4572 found_fpchar = 1;
4573 break;
4574 }
4575
4576 if (!found_fpchar)
4577 return FAIL;
4578 }
5f4273c7 4579
136da414
JB
4580 if ((str = atof_ieee (str, 's', words)) != NULL)
4581 {
4582 unsigned fpword = 0;
4583 int i;
5f4273c7 4584
136da414
JB
4585 /* Our FP word must be 32 bits (single-precision FP). */
4586 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4587 {
4588 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4589 fpword |= words[i];
4590 }
5f4273c7 4591
c96612cc 4592 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
136da414
JB
4593 *immed = fpword;
4594 else
4595 return FAIL;
4596
4597 *ccp = str;
5f4273c7 4598
136da414
JB
4599 return SUCCESS;
4600 }
5f4273c7 4601
136da414
JB
4602 return FAIL;
4603}
4604
c19d1205
ZW
4605/* Shift operands. */
4606enum shift_kind
b99bd4ef 4607{
c19d1205
ZW
4608 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4609};
b99bd4ef 4610
c19d1205
ZW
4611struct asm_shift_name
4612{
4613 const char *name;
4614 enum shift_kind kind;
4615};
b99bd4ef 4616
c19d1205
ZW
4617/* Third argument to parse_shift. */
4618enum parse_shift_mode
4619{
4620 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4621 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4622 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4623 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4624 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4625};
b99bd4ef 4626
c19d1205
ZW
4627/* Parse a <shift> specifier on an ARM data processing instruction.
4628 This has three forms:
b99bd4ef 4629
c19d1205
ZW
4630 (LSL|LSR|ASL|ASR|ROR) Rs
4631 (LSL|LSR|ASL|ASR|ROR) #imm
4632 RRX
b99bd4ef 4633
c19d1205
ZW
4634 Note that ASL is assimilated to LSL in the instruction encoding, and
4635 RRX to ROR #0 (which cannot be written as such). */
b99bd4ef 4636
c19d1205
ZW
4637static int
4638parse_shift (char **str, int i, enum parse_shift_mode mode)
b99bd4ef 4639{
c19d1205
ZW
4640 const struct asm_shift_name *shift_name;
4641 enum shift_kind shift;
4642 char *s = *str;
4643 char *p = s;
4644 int reg;
b99bd4ef 4645
c19d1205
ZW
4646 for (p = *str; ISALPHA (*p); p++)
4647 ;
b99bd4ef 4648
c19d1205 4649 if (p == *str)
b99bd4ef 4650 {
c19d1205
ZW
4651 inst.error = _("shift expression expected");
4652 return FAIL;
b99bd4ef
NC
4653 }
4654
21d799b5
NC
4655 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4656 p - *str);
c19d1205
ZW
4657
4658 if (shift_name == NULL)
b99bd4ef 4659 {
c19d1205
ZW
4660 inst.error = _("shift expression expected");
4661 return FAIL;
b99bd4ef
NC
4662 }
4663
c19d1205 4664 shift = shift_name->kind;
b99bd4ef 4665
c19d1205
ZW
4666 switch (mode)
4667 {
4668 case NO_SHIFT_RESTRICT:
4669 case SHIFT_IMMEDIATE: break;
b99bd4ef 4670
c19d1205
ZW
4671 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4672 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4673 {
4674 inst.error = _("'LSL' or 'ASR' required");
4675 return FAIL;
4676 }
4677 break;
b99bd4ef 4678
c19d1205
ZW
4679 case SHIFT_LSL_IMMEDIATE:
4680 if (shift != SHIFT_LSL)
4681 {
4682 inst.error = _("'LSL' required");
4683 return FAIL;
4684 }
4685 break;
b99bd4ef 4686
c19d1205
ZW
4687 case SHIFT_ASR_IMMEDIATE:
4688 if (shift != SHIFT_ASR)
4689 {
4690 inst.error = _("'ASR' required");
4691 return FAIL;
4692 }
4693 break;
b99bd4ef 4694
c19d1205
ZW
4695 default: abort ();
4696 }
b99bd4ef 4697
c19d1205
ZW
4698 if (shift != SHIFT_RRX)
4699 {
4700 /* Whitespace can appear here if the next thing is a bare digit. */
4701 skip_whitespace (p);
b99bd4ef 4702
c19d1205 4703 if (mode == NO_SHIFT_RESTRICT
dcbf9037 4704 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
c19d1205
ZW
4705 {
4706 inst.operands[i].imm = reg;
4707 inst.operands[i].immisreg = 1;
4708 }
4709 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4710 return FAIL;
4711 }
4712 inst.operands[i].shift_kind = shift;
4713 inst.operands[i].shifted = 1;
4714 *str = p;
4715 return SUCCESS;
b99bd4ef
NC
4716}
4717
c19d1205 4718/* Parse a <shifter_operand> for an ARM data processing instruction:
b99bd4ef 4719
c19d1205
ZW
4720 #<immediate>
4721 #<immediate>, <rotate>
4722 <Rm>
4723 <Rm>, <shift>
b99bd4ef 4724
c19d1205
ZW
4725 where <shift> is defined by parse_shift above, and <rotate> is a
4726 multiple of 2 between 0 and 30. Validation of immediate operands
55cf6793 4727 is deferred to md_apply_fix. */
b99bd4ef 4728
c19d1205
ZW
4729static int
4730parse_shifter_operand (char **str, int i)
4731{
4732 int value;
91d6fa6a 4733 expressionS exp;
b99bd4ef 4734
dcbf9037 4735 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
c19d1205
ZW
4736 {
4737 inst.operands[i].reg = value;
4738 inst.operands[i].isreg = 1;
b99bd4ef 4739
c19d1205
ZW
4740 /* parse_shift will override this if appropriate */
4741 inst.reloc.exp.X_op = O_constant;
4742 inst.reloc.exp.X_add_number = 0;
b99bd4ef 4743
c19d1205
ZW
4744 if (skip_past_comma (str) == FAIL)
4745 return SUCCESS;
b99bd4ef 4746
c19d1205
ZW
4747 /* Shift operation on register. */
4748 return parse_shift (str, i, NO_SHIFT_RESTRICT);
b99bd4ef
NC
4749 }
4750
c19d1205
ZW
4751 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4752 return FAIL;
b99bd4ef 4753
c19d1205 4754 if (skip_past_comma (str) == SUCCESS)
b99bd4ef 4755 {
c19d1205 4756 /* #x, y -- ie explicit rotation by Y. */
91d6fa6a 4757 if (my_get_expression (&exp, str, GE_NO_PREFIX))
c19d1205 4758 return FAIL;
b99bd4ef 4759
91d6fa6a 4760 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
c19d1205
ZW
4761 {
4762 inst.error = _("constant expression expected");
4763 return FAIL;
4764 }
b99bd4ef 4765
91d6fa6a 4766 value = exp.X_add_number;
c19d1205
ZW
4767 if (value < 0 || value > 30 || value % 2 != 0)
4768 {
4769 inst.error = _("invalid rotation");
4770 return FAIL;
4771 }
4772 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4773 {
4774 inst.error = _("invalid constant");
4775 return FAIL;
4776 }
09d92015 4777
55cf6793 4778 /* Convert to decoded value. md_apply_fix will put it back. */
c19d1205
ZW
4779 inst.reloc.exp.X_add_number
4780 = (((inst.reloc.exp.X_add_number << (32 - value))
4781 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
09d92015
MM
4782 }
4783
c19d1205
ZW
4784 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4785 inst.reloc.pc_rel = 0;
4786 return SUCCESS;
09d92015
MM
4787}
4788
4962c51a
MS
4789/* Group relocation information. Each entry in the table contains the
4790 textual name of the relocation as may appear in assembler source
4791 and must end with a colon.
4792 Along with this textual name are the relocation codes to be used if
4793 the corresponding instruction is an ALU instruction (ADD or SUB only),
4794 an LDR, an LDRS, or an LDC. */
4795
4796struct group_reloc_table_entry
4797{
4798 const char *name;
4799 int alu_code;
4800 int ldr_code;
4801 int ldrs_code;
4802 int ldc_code;
4803};
4804
4805typedef enum
4806{
4807 /* Varieties of non-ALU group relocation. */
4808
4809 GROUP_LDR,
4810 GROUP_LDRS,
4811 GROUP_LDC
4812} group_reloc_type;
4813
4814static struct group_reloc_table_entry group_reloc_table[] =
4815 { /* Program counter relative: */
4816 { "pc_g0_nc",
4817 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4818 0, /* LDR */
4819 0, /* LDRS */
4820 0 }, /* LDC */
4821 { "pc_g0",
4822 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4823 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4824 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4825 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4826 { "pc_g1_nc",
4827 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4828 0, /* LDR */
4829 0, /* LDRS */
4830 0 }, /* LDC */
4831 { "pc_g1",
4832 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4833 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4834 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4835 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4836 { "pc_g2",
4837 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4838 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4839 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4840 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4841 /* Section base relative */
4842 { "sb_g0_nc",
4843 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4844 0, /* LDR */
4845 0, /* LDRS */
4846 0 }, /* LDC */
4847 { "sb_g0",
4848 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4849 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4850 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4851 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4852 { "sb_g1_nc",
4853 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4854 0, /* LDR */
4855 0, /* LDRS */
4856 0 }, /* LDC */
4857 { "sb_g1",
4858 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4859 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4860 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4861 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4862 { "sb_g2",
4863 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4864 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4865 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4866 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4867
4868/* Given the address of a pointer pointing to the textual name of a group
4869 relocation as may appear in assembler source, attempt to find its details
4870 in group_reloc_table. The pointer will be updated to the character after
4871 the trailing colon. On failure, FAIL will be returned; SUCCESS
4872 otherwise. On success, *entry will be updated to point at the relevant
4873 group_reloc_table entry. */
4874
4875static int
4876find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
4877{
4878 unsigned int i;
4879 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
4880 {
4881 int length = strlen (group_reloc_table[i].name);
4882
5f4273c7
NC
4883 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
4884 && (*str)[length] == ':')
4962c51a
MS
4885 {
4886 *out = &group_reloc_table[i];
4887 *str += (length + 1);
4888 return SUCCESS;
4889 }
4890 }
4891
4892 return FAIL;
4893}
4894
4895/* Parse a <shifter_operand> for an ARM data processing instruction
4896 (as for parse_shifter_operand) where group relocations are allowed:
4897
4898 #<immediate>
4899 #<immediate>, <rotate>
4900 #:<group_reloc>:<expression>
4901 <Rm>
4902 <Rm>, <shift>
4903
4904 where <group_reloc> is one of the strings defined in group_reloc_table.
4905 The hashes are optional.
4906
4907 Everything else is as for parse_shifter_operand. */
4908
4909static parse_operand_result
4910parse_shifter_operand_group_reloc (char **str, int i)
4911{
4912 /* Determine if we have the sequence of characters #: or just :
4913 coming next. If we do, then we check for a group relocation.
4914 If we don't, punt the whole lot to parse_shifter_operand. */
4915
4916 if (((*str)[0] == '#' && (*str)[1] == ':')
4917 || (*str)[0] == ':')
4918 {
4919 struct group_reloc_table_entry *entry;
4920
4921 if ((*str)[0] == '#')
4922 (*str) += 2;
4923 else
4924 (*str)++;
4925
4926 /* Try to parse a group relocation. Anything else is an error. */
4927 if (find_group_reloc_table_entry (str, &entry) == FAIL)
4928 {
4929 inst.error = _("unknown group relocation");
4930 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4931 }
4932
4933 /* We now have the group relocation table entry corresponding to
4934 the name in the assembler source. Next, we parse the expression. */
4935 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
4936 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4937
4938 /* Record the relocation type (always the ALU variant here). */
21d799b5 4939 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
9c2799c2 4940 gas_assert (inst.reloc.type != 0);
4962c51a
MS
4941
4942 return PARSE_OPERAND_SUCCESS;
4943 }
4944 else
4945 return parse_shifter_operand (str, i) == SUCCESS
4946 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
4947
4948 /* Never reached. */
4949}
4950
8e560766
MGD
4951/* Parse a Neon alignment expression. Information is written to
4952 inst.operands[i]. We assume the initial ':' has been skipped.
4953
4954 align .imm = align << 8, .immisalign=1, .preind=0 */
4955static parse_operand_result
4956parse_neon_alignment (char **str, int i)
4957{
4958 char *p = *str;
4959 expressionS exp;
4960
4961 my_get_expression (&exp, &p, GE_NO_PREFIX);
4962
4963 if (exp.X_op != O_constant)
4964 {
4965 inst.error = _("alignment must be constant");
4966 return PARSE_OPERAND_FAIL;
4967 }
4968
4969 inst.operands[i].imm = exp.X_add_number << 8;
4970 inst.operands[i].immisalign = 1;
4971 /* Alignments are not pre-indexes. */
4972 inst.operands[i].preind = 0;
4973
4974 *str = p;
4975 return PARSE_OPERAND_SUCCESS;
4976}
4977
c19d1205
ZW
4978/* Parse all forms of an ARM address expression. Information is written
4979 to inst.operands[i] and/or inst.reloc.
09d92015 4980
c19d1205 4981 Preindexed addressing (.preind=1):
09d92015 4982
c19d1205
ZW
4983 [Rn, #offset] .reg=Rn .reloc.exp=offset
4984 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4985 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4986 .shift_kind=shift .reloc.exp=shift_imm
09d92015 4987
c19d1205 4988 These three may have a trailing ! which causes .writeback to be set also.
09d92015 4989
c19d1205 4990 Postindexed addressing (.postind=1, .writeback=1):
09d92015 4991
c19d1205
ZW
4992 [Rn], #offset .reg=Rn .reloc.exp=offset
4993 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4994 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4995 .shift_kind=shift .reloc.exp=shift_imm
09d92015 4996
c19d1205 4997 Unindexed addressing (.preind=0, .postind=0):
09d92015 4998
c19d1205 4999 [Rn], {option} .reg=Rn .imm=option .immisreg=0
09d92015 5000
c19d1205 5001 Other:
09d92015 5002
c19d1205
ZW
5003 [Rn]{!} shorthand for [Rn,#0]{!}
5004 =immediate .isreg=0 .reloc.exp=immediate
5005 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
09d92015 5006
c19d1205
ZW
5007 It is the caller's responsibility to check for addressing modes not
5008 supported by the instruction, and to set inst.reloc.type. */
5009
4962c51a
MS
5010static parse_operand_result
5011parse_address_main (char **str, int i, int group_relocations,
5012 group_reloc_type group_type)
09d92015 5013{
c19d1205
ZW
5014 char *p = *str;
5015 int reg;
09d92015 5016
c19d1205 5017 if (skip_past_char (&p, '[') == FAIL)
09d92015 5018 {
c19d1205
ZW
5019 if (skip_past_char (&p, '=') == FAIL)
5020 {
974da60d 5021 /* Bare address - translate to PC-relative offset. */
c19d1205
ZW
5022 inst.reloc.pc_rel = 1;
5023 inst.operands[i].reg = REG_PC;
5024 inst.operands[i].isreg = 1;
5025 inst.operands[i].preind = 1;
5026 }
974da60d 5027 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
09d92015 5028
c19d1205 5029 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4962c51a 5030 return PARSE_OPERAND_FAIL;
09d92015 5031
c19d1205 5032 *str = p;
4962c51a 5033 return PARSE_OPERAND_SUCCESS;
09d92015
MM
5034 }
5035
dcbf9037 5036 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
09d92015 5037 {
c19d1205 5038 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
4962c51a 5039 return PARSE_OPERAND_FAIL;
09d92015 5040 }
c19d1205
ZW
5041 inst.operands[i].reg = reg;
5042 inst.operands[i].isreg = 1;
09d92015 5043
c19d1205 5044 if (skip_past_comma (&p) == SUCCESS)
09d92015 5045 {
c19d1205 5046 inst.operands[i].preind = 1;
09d92015 5047
c19d1205
ZW
5048 if (*p == '+') p++;
5049 else if (*p == '-') p++, inst.operands[i].negative = 1;
5050
dcbf9037 5051 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
09d92015 5052 {
c19d1205
ZW
5053 inst.operands[i].imm = reg;
5054 inst.operands[i].immisreg = 1;
5055
5056 if (skip_past_comma (&p) == SUCCESS)
5057 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4962c51a 5058 return PARSE_OPERAND_FAIL;
c19d1205 5059 }
5287ad62 5060 else if (skip_past_char (&p, ':') == SUCCESS)
8e560766
MGD
5061 {
5062 /* FIXME: '@' should be used here, but it's filtered out by generic
5063 code before we get to see it here. This may be subject to
5064 change. */
5065 parse_operand_result result = parse_neon_alignment (&p, i);
5066
5067 if (result != PARSE_OPERAND_SUCCESS)
5068 return result;
5069 }
c19d1205
ZW
5070 else
5071 {
5072 if (inst.operands[i].negative)
5073 {
5074 inst.operands[i].negative = 0;
5075 p--;
5076 }
4962c51a 5077
5f4273c7
NC
5078 if (group_relocations
5079 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
4962c51a
MS
5080 {
5081 struct group_reloc_table_entry *entry;
5082
5083 /* Skip over the #: or : sequence. */
5084 if (*p == '#')
5085 p += 2;
5086 else
5087 p++;
5088
5089 /* Try to parse a group relocation. Anything else is an
5090 error. */
5091 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5092 {
5093 inst.error = _("unknown group relocation");
5094 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5095 }
5096
5097 /* We now have the group relocation table entry corresponding to
5098 the name in the assembler source. Next, we parse the
5099 expression. */
5100 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5101 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5102
5103 /* Record the relocation type. */
5104 switch (group_type)
5105 {
5106 case GROUP_LDR:
21d799b5 5107 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
4962c51a
MS
5108 break;
5109
5110 case GROUP_LDRS:
21d799b5 5111 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
4962c51a
MS
5112 break;
5113
5114 case GROUP_LDC:
21d799b5 5115 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
4962c51a
MS
5116 break;
5117
5118 default:
9c2799c2 5119 gas_assert (0);
4962c51a
MS
5120 }
5121
5122 if (inst.reloc.type == 0)
5123 {
5124 inst.error = _("this group relocation is not allowed on this instruction");
5125 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5126 }
5127 }
5128 else
5129 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5130 return PARSE_OPERAND_FAIL;
09d92015
MM
5131 }
5132 }
8e560766
MGD
5133 else if (skip_past_char (&p, ':') == SUCCESS)
5134 {
5135 /* FIXME: '@' should be used here, but it's filtered out by generic code
5136 before we get to see it here. This may be subject to change. */
5137 parse_operand_result result = parse_neon_alignment (&p, i);
5138
5139 if (result != PARSE_OPERAND_SUCCESS)
5140 return result;
5141 }
09d92015 5142
c19d1205 5143 if (skip_past_char (&p, ']') == FAIL)
09d92015 5144 {
c19d1205 5145 inst.error = _("']' expected");
4962c51a 5146 return PARSE_OPERAND_FAIL;
09d92015
MM
5147 }
5148
c19d1205
ZW
5149 if (skip_past_char (&p, '!') == SUCCESS)
5150 inst.operands[i].writeback = 1;
09d92015 5151
c19d1205 5152 else if (skip_past_comma (&p) == SUCCESS)
09d92015 5153 {
c19d1205
ZW
5154 if (skip_past_char (&p, '{') == SUCCESS)
5155 {
5156 /* [Rn], {expr} - unindexed, with option */
5157 if (parse_immediate (&p, &inst.operands[i].imm,
ca3f61f7 5158 0, 255, TRUE) == FAIL)
4962c51a 5159 return PARSE_OPERAND_FAIL;
09d92015 5160
c19d1205
ZW
5161 if (skip_past_char (&p, '}') == FAIL)
5162 {
5163 inst.error = _("'}' expected at end of 'option' field");
4962c51a 5164 return PARSE_OPERAND_FAIL;
c19d1205
ZW
5165 }
5166 if (inst.operands[i].preind)
5167 {
5168 inst.error = _("cannot combine index with option");
4962c51a 5169 return PARSE_OPERAND_FAIL;
c19d1205
ZW
5170 }
5171 *str = p;
4962c51a 5172 return PARSE_OPERAND_SUCCESS;
09d92015 5173 }
c19d1205
ZW
5174 else
5175 {
5176 inst.operands[i].postind = 1;
5177 inst.operands[i].writeback = 1;
09d92015 5178
c19d1205
ZW
5179 if (inst.operands[i].preind)
5180 {
5181 inst.error = _("cannot combine pre- and post-indexing");
4962c51a 5182 return PARSE_OPERAND_FAIL;
c19d1205 5183 }
09d92015 5184
c19d1205
ZW
5185 if (*p == '+') p++;
5186 else if (*p == '-') p++, inst.operands[i].negative = 1;
a737bd4d 5187
dcbf9037 5188 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
c19d1205 5189 {
5287ad62
JB
5190 /* We might be using the immediate for alignment already. If we
5191 are, OR the register number into the low-order bits. */
5192 if (inst.operands[i].immisalign)
5193 inst.operands[i].imm |= reg;
5194 else
5195 inst.operands[i].imm = reg;
c19d1205 5196 inst.operands[i].immisreg = 1;
a737bd4d 5197
c19d1205
ZW
5198 if (skip_past_comma (&p) == SUCCESS)
5199 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4962c51a 5200 return PARSE_OPERAND_FAIL;
c19d1205
ZW
5201 }
5202 else
5203 {
5204 if (inst.operands[i].negative)
5205 {
5206 inst.operands[i].negative = 0;
5207 p--;
5208 }
5209 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4962c51a 5210 return PARSE_OPERAND_FAIL;
c19d1205
ZW
5211 }
5212 }
a737bd4d
NC
5213 }
5214
c19d1205
ZW
5215 /* If at this point neither .preind nor .postind is set, we have a
5216 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5217 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5218 {
5219 inst.operands[i].preind = 1;
5220 inst.reloc.exp.X_op = O_constant;
5221 inst.reloc.exp.X_add_number = 0;
5222 }
5223 *str = p;
4962c51a
MS
5224 return PARSE_OPERAND_SUCCESS;
5225}
5226
5227static int
5228parse_address (char **str, int i)
5229{
21d799b5 5230 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
4962c51a
MS
5231 ? SUCCESS : FAIL;
5232}
5233
5234static parse_operand_result
5235parse_address_group_reloc (char **str, int i, group_reloc_type type)
5236{
5237 return parse_address_main (str, i, 1, type);
a737bd4d
NC
5238}
5239
b6895b4f
PB
5240/* Parse an operand for a MOVW or MOVT instruction. */
5241static int
5242parse_half (char **str)
5243{
5244 char * p;
5f4273c7 5245
b6895b4f
PB
5246 p = *str;
5247 skip_past_char (&p, '#');
5f4273c7 5248 if (strncasecmp (p, ":lower16:", 9) == 0)
b6895b4f
PB
5249 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5250 else if (strncasecmp (p, ":upper16:", 9) == 0)
5251 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5252
5253 if (inst.reloc.type != BFD_RELOC_UNUSED)
5254 {
5255 p += 9;
5f4273c7 5256 skip_whitespace (p);
b6895b4f
PB
5257 }
5258
5259 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5260 return FAIL;
5261
5262 if (inst.reloc.type == BFD_RELOC_UNUSED)
5263 {
5264 if (inst.reloc.exp.X_op != O_constant)
5265 {
5266 inst.error = _("constant expression expected");
5267 return FAIL;
5268 }
5269 if (inst.reloc.exp.X_add_number < 0
5270 || inst.reloc.exp.X_add_number > 0xffff)
5271 {
5272 inst.error = _("immediate value out of range");
5273 return FAIL;
5274 }
5275 }
5276 *str = p;
5277 return SUCCESS;
5278}
5279
c19d1205 5280/* Miscellaneous. */
a737bd4d 5281
c19d1205
ZW
5282/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5283 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5284static int
5285parse_psr (char **str)
09d92015 5286{
c19d1205
ZW
5287 char *p;
5288 unsigned long psr_field;
62b3e311
PB
5289 const struct asm_psr *psr;
5290 char *start;
09d92015 5291
c19d1205
ZW
5292 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5293 feature for ease of use and backwards compatibility. */
5294 p = *str;
62b3e311 5295 if (strncasecmp (p, "SPSR", 4) == 0)
c19d1205 5296 psr_field = SPSR_BIT;
62b3e311 5297 else if (strncasecmp (p, "CPSR", 4) == 0)
c19d1205
ZW
5298 psr_field = 0;
5299 else
62b3e311
PB
5300 {
5301 start = p;
5302 do
5303 p++;
5304 while (ISALNUM (*p) || *p == '_');
5305
21d799b5
NC
5306 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5307 p - start);
62b3e311
PB
5308 if (!psr)
5309 return FAIL;
09d92015 5310
62b3e311
PB
5311 *str = p;
5312 return psr->field;
5313 }
09d92015 5314
62b3e311 5315 p += 4;
c19d1205
ZW
5316 if (*p == '_')
5317 {
5318 /* A suffix follows. */
c19d1205
ZW
5319 p++;
5320 start = p;
a737bd4d 5321
c19d1205
ZW
5322 do
5323 p++;
5324 while (ISALNUM (*p) || *p == '_');
a737bd4d 5325
21d799b5
NC
5326 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5327 p - start);
c19d1205
ZW
5328 if (!psr)
5329 goto error;
a737bd4d 5330
c19d1205 5331 psr_field |= psr->field;
a737bd4d 5332 }
c19d1205 5333 else
a737bd4d 5334 {
c19d1205
ZW
5335 if (ISALNUM (*p))
5336 goto error; /* Garbage after "[CS]PSR". */
5337
5338 psr_field |= (PSR_c | PSR_f);
a737bd4d 5339 }
c19d1205
ZW
5340 *str = p;
5341 return psr_field;
a737bd4d 5342
c19d1205
ZW
5343 error:
5344 inst.error = _("flag for {c}psr instruction expected");
5345 return FAIL;
a737bd4d
NC
5346}
5347
c19d1205
ZW
5348/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5349 value suitable for splatting into the AIF field of the instruction. */
a737bd4d 5350
c19d1205
ZW
5351static int
5352parse_cps_flags (char **str)
a737bd4d 5353{
c19d1205
ZW
5354 int val = 0;
5355 int saw_a_flag = 0;
5356 char *s = *str;
a737bd4d 5357
c19d1205
ZW
5358 for (;;)
5359 switch (*s++)
5360 {
5361 case '\0': case ',':
5362 goto done;
a737bd4d 5363
c19d1205
ZW
5364 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5365 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5366 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
a737bd4d 5367
c19d1205
ZW
5368 default:
5369 inst.error = _("unrecognized CPS flag");
5370 return FAIL;
5371 }
a737bd4d 5372
c19d1205
ZW
5373 done:
5374 if (saw_a_flag == 0)
a737bd4d 5375 {
c19d1205
ZW
5376 inst.error = _("missing CPS flags");
5377 return FAIL;
a737bd4d 5378 }
a737bd4d 5379
c19d1205
ZW
5380 *str = s - 1;
5381 return val;
a737bd4d
NC
5382}
5383
c19d1205
ZW
5384/* Parse an endian specifier ("BE" or "LE", case insensitive);
5385 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
a737bd4d
NC
5386
5387static int
c19d1205 5388parse_endian_specifier (char **str)
a737bd4d 5389{
c19d1205
ZW
5390 int little_endian;
5391 char *s = *str;
a737bd4d 5392
c19d1205
ZW
5393 if (strncasecmp (s, "BE", 2))
5394 little_endian = 0;
5395 else if (strncasecmp (s, "LE", 2))
5396 little_endian = 1;
5397 else
a737bd4d 5398 {
c19d1205 5399 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC
5400 return FAIL;
5401 }
5402
c19d1205 5403 if (ISALNUM (s[2]) || s[2] == '_')
a737bd4d 5404 {
c19d1205 5405 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC
5406 return FAIL;
5407 }
5408
c19d1205
ZW
5409 *str = s + 2;
5410 return little_endian;
5411}
a737bd4d 5412
c19d1205
ZW
5413/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5414 value suitable for poking into the rotate field of an sxt or sxta
5415 instruction, or FAIL on error. */
5416
5417static int
5418parse_ror (char **str)
5419{
5420 int rot;
5421 char *s = *str;
5422
5423 if (strncasecmp (s, "ROR", 3) == 0)
5424 s += 3;
5425 else
a737bd4d 5426 {
c19d1205 5427 inst.error = _("missing rotation field after comma");
a737bd4d
NC
5428 return FAIL;
5429 }
c19d1205
ZW
5430
5431 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5432 return FAIL;
5433
5434 switch (rot)
a737bd4d 5435 {
c19d1205
ZW
5436 case 0: *str = s; return 0x0;
5437 case 8: *str = s; return 0x1;
5438 case 16: *str = s; return 0x2;
5439 case 24: *str = s; return 0x3;
5440
5441 default:
5442 inst.error = _("rotation can only be 0, 8, 16, or 24");
a737bd4d
NC
5443 return FAIL;
5444 }
c19d1205 5445}
a737bd4d 5446
c19d1205
ZW
5447/* Parse a conditional code (from conds[] below). The value returned is in the
5448 range 0 .. 14, or FAIL. */
5449static int
5450parse_cond (char **str)
5451{
c462b453 5452 char *q;
c19d1205 5453 const struct asm_cond *c;
c462b453
PB
5454 int n;
5455 /* Condition codes are always 2 characters, so matching up to
5456 3 characters is sufficient. */
5457 char cond[3];
a737bd4d 5458
c462b453
PB
5459 q = *str;
5460 n = 0;
5461 while (ISALPHA (*q) && n < 3)
5462 {
e07e6e58 5463 cond[n] = TOLOWER (*q);
c462b453
PB
5464 q++;
5465 n++;
5466 }
a737bd4d 5467
21d799b5 5468 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
c19d1205 5469 if (!c)
a737bd4d 5470 {
c19d1205 5471 inst.error = _("condition required");
a737bd4d
NC
5472 return FAIL;
5473 }
5474
c19d1205
ZW
5475 *str = q;
5476 return c->value;
5477}
5478
62b3e311
PB
5479/* Parse an option for a barrier instruction. Returns the encoding for the
5480 option, or FAIL. */
5481static int
5482parse_barrier (char **str)
5483{
5484 char *p, *q;
5485 const struct asm_barrier_opt *o;
5486
5487 p = q = *str;
5488 while (ISALPHA (*q))
5489 q++;
5490
21d799b5
NC
5491 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5492 q - p);
62b3e311
PB
5493 if (!o)
5494 return FAIL;
5495
5496 *str = q;
5497 return o->value;
5498}
5499
92e90b6e
PB
5500/* Parse the operands of a table branch instruction. Similar to a memory
5501 operand. */
5502static int
5503parse_tb (char **str)
5504{
5505 char * p = *str;
5506 int reg;
5507
5508 if (skip_past_char (&p, '[') == FAIL)
ab1eb5fe
PB
5509 {
5510 inst.error = _("'[' expected");
5511 return FAIL;
5512 }
92e90b6e 5513
dcbf9037 5514 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
92e90b6e
PB
5515 {
5516 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5517 return FAIL;
5518 }
5519 inst.operands[0].reg = reg;
5520
5521 if (skip_past_comma (&p) == FAIL)
ab1eb5fe
PB
5522 {
5523 inst.error = _("',' expected");
5524 return FAIL;
5525 }
5f4273c7 5526
dcbf9037 5527 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
92e90b6e
PB
5528 {
5529 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5530 return FAIL;
5531 }
5532 inst.operands[0].imm = reg;
5533
5534 if (skip_past_comma (&p) == SUCCESS)
5535 {
5536 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5537 return FAIL;
5538 if (inst.reloc.exp.X_add_number != 1)
5539 {
5540 inst.error = _("invalid shift");
5541 return FAIL;
5542 }
5543 inst.operands[0].shifted = 1;
5544 }
5545
5546 if (skip_past_char (&p, ']') == FAIL)
5547 {
5548 inst.error = _("']' expected");
5549 return FAIL;
5550 }
5551 *str = p;
5552 return SUCCESS;
5553}
5554
5287ad62
JB
5555/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5556 information on the types the operands can take and how they are encoded.
037e8744
JB
5557 Up to four operands may be read; this function handles setting the
5558 ".present" field for each read operand itself.
5287ad62
JB
5559 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5560 else returns FAIL. */
5561
5562static int
5563parse_neon_mov (char **str, int *which_operand)
5564{
5565 int i = *which_operand, val;
5566 enum arm_reg_type rtype;
5567 char *ptr = *str;
dcbf9037 5568 struct neon_type_el optype;
5f4273c7 5569
dcbf9037 5570 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5287ad62
JB
5571 {
5572 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5573 inst.operands[i].reg = val;
5574 inst.operands[i].isscalar = 1;
dcbf9037 5575 inst.operands[i].vectype = optype;
5287ad62
JB
5576 inst.operands[i++].present = 1;
5577
5578 if (skip_past_comma (&ptr) == FAIL)
5579 goto wanted_comma;
5f4273c7 5580
dcbf9037 5581 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5287ad62 5582 goto wanted_arm;
5f4273c7 5583
5287ad62
JB
5584 inst.operands[i].reg = val;
5585 inst.operands[i].isreg = 1;
5586 inst.operands[i].present = 1;
5587 }
037e8744 5588 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
dcbf9037 5589 != FAIL)
5287ad62
JB
5590 {
5591 /* Cases 0, 1, 2, 3, 5 (D only). */
5592 if (skip_past_comma (&ptr) == FAIL)
5593 goto wanted_comma;
5f4273c7 5594
5287ad62
JB
5595 inst.operands[i].reg = val;
5596 inst.operands[i].isreg = 1;
5597 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
037e8744
JB
5598 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5599 inst.operands[i].isvec = 1;
dcbf9037 5600 inst.operands[i].vectype = optype;
5287ad62
JB
5601 inst.operands[i++].present = 1;
5602
dcbf9037 5603 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5287ad62 5604 {
037e8744
JB
5605 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5606 Case 13: VMOV <Sd>, <Rm> */
5287ad62
JB
5607 inst.operands[i].reg = val;
5608 inst.operands[i].isreg = 1;
037e8744 5609 inst.operands[i].present = 1;
5287ad62
JB
5610
5611 if (rtype == REG_TYPE_NQ)
5612 {
dcbf9037 5613 first_error (_("can't use Neon quad register here"));
5287ad62
JB
5614 return FAIL;
5615 }
037e8744
JB
5616 else if (rtype != REG_TYPE_VFS)
5617 {
5618 i++;
5619 if (skip_past_comma (&ptr) == FAIL)
5620 goto wanted_comma;
5621 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5622 goto wanted_arm;
5623 inst.operands[i].reg = val;
5624 inst.operands[i].isreg = 1;
5625 inst.operands[i].present = 1;
5626 }
5287ad62 5627 }
037e8744
JB
5628 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5629 &optype)) != FAIL)
5287ad62
JB
5630 {
5631 /* Case 0: VMOV<c><q> <Qd>, <Qm>
037e8744
JB
5632 Case 1: VMOV<c><q> <Dd>, <Dm>
5633 Case 8: VMOV.F32 <Sd>, <Sm>
5634 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5287ad62
JB
5635
5636 inst.operands[i].reg = val;
5637 inst.operands[i].isreg = 1;
5638 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
037e8744
JB
5639 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5640 inst.operands[i].isvec = 1;
dcbf9037 5641 inst.operands[i].vectype = optype;
5287ad62 5642 inst.operands[i].present = 1;
5f4273c7 5643
037e8744
JB
5644 if (skip_past_comma (&ptr) == SUCCESS)
5645 {
5646 /* Case 15. */
5647 i++;
5648
5649 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5650 goto wanted_arm;
5651
5652 inst.operands[i].reg = val;
5653 inst.operands[i].isreg = 1;
5654 inst.operands[i++].present = 1;
5f4273c7 5655
037e8744
JB
5656 if (skip_past_comma (&ptr) == FAIL)
5657 goto wanted_comma;
5f4273c7 5658
037e8744
JB
5659 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5660 goto wanted_arm;
5f4273c7 5661
037e8744
JB
5662 inst.operands[i].reg = val;
5663 inst.operands[i].isreg = 1;
5664 inst.operands[i++].present = 1;
5665 }
5287ad62 5666 }
4641781c
PB
5667 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5668 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5669 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5670 Case 10: VMOV.F32 <Sd>, #<imm>
5671 Case 11: VMOV.F64 <Dd>, #<imm> */
5672 inst.operands[i].immisfloat = 1;
5673 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5674 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5675 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5676 ;
5287ad62
JB
5677 else
5678 {
dcbf9037 5679 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5287ad62
JB
5680 return FAIL;
5681 }
5682 }
dcbf9037 5683 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5287ad62
JB
5684 {
5685 /* Cases 6, 7. */
5686 inst.operands[i].reg = val;
5687 inst.operands[i].isreg = 1;
5688 inst.operands[i++].present = 1;
5f4273c7 5689
5287ad62
JB
5690 if (skip_past_comma (&ptr) == FAIL)
5691 goto wanted_comma;
5f4273c7 5692
dcbf9037 5693 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5287ad62
JB
5694 {
5695 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5696 inst.operands[i].reg = val;
5697 inst.operands[i].isscalar = 1;
5698 inst.operands[i].present = 1;
dcbf9037 5699 inst.operands[i].vectype = optype;
5287ad62 5700 }
dcbf9037 5701 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5287ad62
JB
5702 {
5703 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5704 inst.operands[i].reg = val;
5705 inst.operands[i].isreg = 1;
5706 inst.operands[i++].present = 1;
5f4273c7 5707
5287ad62
JB
5708 if (skip_past_comma (&ptr) == FAIL)
5709 goto wanted_comma;
5f4273c7 5710
037e8744 5711 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
dcbf9037 5712 == FAIL)
5287ad62 5713 {
037e8744 5714 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
5287ad62
JB
5715 return FAIL;
5716 }
5717
5718 inst.operands[i].reg = val;
5719 inst.operands[i].isreg = 1;
037e8744
JB
5720 inst.operands[i].isvec = 1;
5721 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
dcbf9037 5722 inst.operands[i].vectype = optype;
5287ad62 5723 inst.operands[i].present = 1;
5f4273c7 5724
037e8744
JB
5725 if (rtype == REG_TYPE_VFS)
5726 {
5727 /* Case 14. */
5728 i++;
5729 if (skip_past_comma (&ptr) == FAIL)
5730 goto wanted_comma;
5731 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
5732 &optype)) == FAIL)
5733 {
5734 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
5735 return FAIL;
5736 }
5737 inst.operands[i].reg = val;
5738 inst.operands[i].isreg = 1;
5739 inst.operands[i].isvec = 1;
5740 inst.operands[i].issingle = 1;
5741 inst.operands[i].vectype = optype;
5742 inst.operands[i].present = 1;
5743 }
5744 }
5745 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
5746 != FAIL)
5747 {
5748 /* Case 13. */
5749 inst.operands[i].reg = val;
5750 inst.operands[i].isreg = 1;
5751 inst.operands[i].isvec = 1;
5752 inst.operands[i].issingle = 1;
5753 inst.operands[i].vectype = optype;
5754 inst.operands[i++].present = 1;
5287ad62
JB
5755 }
5756 }
5757 else
5758 {
dcbf9037 5759 first_error (_("parse error"));
5287ad62
JB
5760 return FAIL;
5761 }
5762
5763 /* Successfully parsed the operands. Update args. */
5764 *which_operand = i;
5765 *str = ptr;
5766 return SUCCESS;
5767
5f4273c7 5768 wanted_comma:
dcbf9037 5769 first_error (_("expected comma"));
5287ad62 5770 return FAIL;
5f4273c7
NC
5771
5772 wanted_arm:
dcbf9037 5773 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
5287ad62 5774 return FAIL;
5287ad62
JB
5775}
5776
5be8be5d
DG
5777/* Use this macro when the operand constraints are different
5778 for ARM and THUMB (e.g. ldrd). */
5779#define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
5780 ((arm_operand) | ((thumb_operand) << 16))
5781
c19d1205
ZW
5782/* Matcher codes for parse_operands. */
5783enum operand_parse_code
5784{
5785 OP_stop, /* end of line */
5786
5787 OP_RR, /* ARM register */
5788 OP_RRnpc, /* ARM register, not r15 */
5be8be5d 5789 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
c19d1205 5790 OP_RRnpcb, /* ARM register, not r15, in square brackets */
55881a11
MGD
5791 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
5792 optional trailing ! */
c19d1205
ZW
5793 OP_RRw, /* ARM register, not r15, optional trailing ! */
5794 OP_RCP, /* Coprocessor number */
5795 OP_RCN, /* Coprocessor register */
5796 OP_RF, /* FPA register */
5797 OP_RVS, /* VFP single precision register */
5287ad62
JB
5798 OP_RVD, /* VFP double precision register (0..15) */
5799 OP_RND, /* Neon double precision register (0..31) */
5800 OP_RNQ, /* Neon quad precision register */
037e8744 5801 OP_RVSD, /* VFP single or double precision register */
5287ad62 5802 OP_RNDQ, /* Neon double or quad precision register */
037e8744 5803 OP_RNSDQ, /* Neon single, double or quad precision register */
5287ad62 5804 OP_RNSC, /* Neon scalar D[X] */
c19d1205
ZW
5805 OP_RVC, /* VFP control register */
5806 OP_RMF, /* Maverick F register */
5807 OP_RMD, /* Maverick D register */
5808 OP_RMFX, /* Maverick FX register */
5809 OP_RMDX, /* Maverick DX register */
5810 OP_RMAX, /* Maverick AX register */
5811 OP_RMDS, /* Maverick DSPSC register */
5812 OP_RIWR, /* iWMMXt wR register */
5813 OP_RIWC, /* iWMMXt wC register */
5814 OP_RIWG, /* iWMMXt wCG register */
5815 OP_RXA, /* XScale accumulator register */
5816
5817 OP_REGLST, /* ARM register list */
5818 OP_VRSLST, /* VFP single-precision register list */
5819 OP_VRDLST, /* VFP double-precision register list */
037e8744 5820 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
5287ad62
JB
5821 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
5822 OP_NSTRLST, /* Neon element/structure list */
5823
5287ad62 5824 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
037e8744 5825 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
5287ad62 5826 OP_RR_RNSC, /* ARM reg or Neon scalar. */
037e8744 5827 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
5287ad62
JB
5828 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
5829 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
5830 OP_VMOV, /* Neon VMOV operands. */
4316f0d2 5831 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
5287ad62 5832 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
2d447fca 5833 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5287ad62
JB
5834
5835 OP_I0, /* immediate zero */
c19d1205
ZW
5836 OP_I7, /* immediate value 0 .. 7 */
5837 OP_I15, /* 0 .. 15 */
5838 OP_I16, /* 1 .. 16 */
5287ad62 5839 OP_I16z, /* 0 .. 16 */
c19d1205
ZW
5840 OP_I31, /* 0 .. 31 */
5841 OP_I31w, /* 0 .. 31, optional trailing ! */
5842 OP_I32, /* 1 .. 32 */
5287ad62
JB
5843 OP_I32z, /* 0 .. 32 */
5844 OP_I63, /* 0 .. 63 */
c19d1205 5845 OP_I63s, /* -64 .. 63 */
5287ad62
JB
5846 OP_I64, /* 1 .. 64 */
5847 OP_I64z, /* 0 .. 64 */
c19d1205 5848 OP_I255, /* 0 .. 255 */
c19d1205
ZW
5849
5850 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
5851 OP_I7b, /* 0 .. 7 */
5852 OP_I15b, /* 0 .. 15 */
5853 OP_I31b, /* 0 .. 31 */
5854
5855 OP_SH, /* shifter operand */
4962c51a 5856 OP_SHG, /* shifter operand with possible group relocation */
c19d1205 5857 OP_ADDR, /* Memory address expression (any mode) */
4962c51a
MS
5858 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
5859 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
5860 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
c19d1205
ZW
5861 OP_EXP, /* arbitrary expression */
5862 OP_EXPi, /* same, with optional immediate prefix */
5863 OP_EXPr, /* same, with optional relocation suffix */
b6895b4f 5864 OP_HALF, /* 0 .. 65535 or low/high reloc. */
c19d1205
ZW
5865
5866 OP_CPSF, /* CPS flags */
5867 OP_ENDI, /* Endianness specifier */
5868 OP_PSR, /* CPSR/SPSR mask for msr */
5869 OP_COND, /* conditional code */
92e90b6e 5870 OP_TB, /* Table branch. */
c19d1205 5871
037e8744
JB
5872 OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */
5873 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
5874
c19d1205
ZW
5875 OP_RRnpc_I0, /* ARM register or literal 0 */
5876 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
5877 OP_RR_EXi, /* ARM register or expression with imm prefix */
5878 OP_RF_IF, /* FPA register or immediate */
5879 OP_RIWR_RIWC, /* iWMMXt R or C reg */
41adaa5c 5880 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
c19d1205
ZW
5881
5882 /* Optional operands. */
5883 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
5884 OP_oI31b, /* 0 .. 31 */
5287ad62 5885 OP_oI32b, /* 1 .. 32 */
c19d1205
ZW
5886 OP_oIffffb, /* 0 .. 65535 */
5887 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
5888
5889 OP_oRR, /* ARM register */
5890 OP_oRRnpc, /* ARM register, not the PC */
5be8be5d 5891 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
b6702015 5892 OP_oRRw, /* ARM register, not r15, optional trailing ! */
5287ad62
JB
5893 OP_oRND, /* Optional Neon double precision register */
5894 OP_oRNQ, /* Optional Neon quad precision register */
5895 OP_oRNDQ, /* Optional Neon double or quad precision register */
037e8744 5896 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
c19d1205
ZW
5897 OP_oSHll, /* LSL immediate */
5898 OP_oSHar, /* ASR immediate */
5899 OP_oSHllar, /* LSL or ASR immediate */
5900 OP_oROR, /* ROR 0/8/16/24 */
62b3e311 5901 OP_oBARRIER, /* Option argument for a barrier instruction. */
c19d1205 5902
5be8be5d
DG
5903 /* Some pre-defined mixed (ARM/THUMB) operands. */
5904 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
5905 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
5906 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
5907
c19d1205
ZW
5908 OP_FIRST_OPTIONAL = OP_oI7b
5909};
a737bd4d 5910
c19d1205
ZW
5911/* Generic instruction operand parser. This does no encoding and no
5912 semantic validation; it merely squirrels values away in the inst
5913 structure. Returns SUCCESS or FAIL depending on whether the
5914 specified grammar matched. */
5915static int
5be8be5d 5916parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
c19d1205 5917{
5be8be5d 5918 unsigned const int *upat = pattern;
c19d1205
ZW
5919 char *backtrack_pos = 0;
5920 const char *backtrack_error = 0;
5921 int i, val, backtrack_index = 0;
5287ad62 5922 enum arm_reg_type rtype;
4962c51a 5923 parse_operand_result result;
5be8be5d 5924 unsigned int op_parse_code;
c19d1205 5925
e07e6e58
NC
5926#define po_char_or_fail(chr) \
5927 do \
5928 { \
5929 if (skip_past_char (&str, chr) == FAIL) \
5930 goto bad_args; \
5931 } \
5932 while (0)
c19d1205 5933
e07e6e58
NC
5934#define po_reg_or_fail(regtype) \
5935 do \
dcbf9037 5936 { \
e07e6e58
NC
5937 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5938 & inst.operands[i].vectype); \
5939 if (val == FAIL) \
5940 { \
5941 first_error (_(reg_expected_msgs[regtype])); \
5942 goto failure; \
5943 } \
5944 inst.operands[i].reg = val; \
5945 inst.operands[i].isreg = 1; \
5946 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5947 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5948 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5949 || rtype == REG_TYPE_VFD \
5950 || rtype == REG_TYPE_NQ); \
dcbf9037 5951 } \
e07e6e58
NC
5952 while (0)
5953
5954#define po_reg_or_goto(regtype, label) \
5955 do \
5956 { \
5957 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5958 & inst.operands[i].vectype); \
5959 if (val == FAIL) \
5960 goto label; \
dcbf9037 5961 \
e07e6e58
NC
5962 inst.operands[i].reg = val; \
5963 inst.operands[i].isreg = 1; \
5964 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5965 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5966 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5967 || rtype == REG_TYPE_VFD \
5968 || rtype == REG_TYPE_NQ); \
5969 } \
5970 while (0)
5971
5972#define po_imm_or_fail(min, max, popt) \
5973 do \
5974 { \
5975 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5976 goto failure; \
5977 inst.operands[i].imm = val; \
5978 } \
5979 while (0)
5980
5981#define po_scalar_or_goto(elsz, label) \
5982 do \
5983 { \
5984 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
5985 if (val == FAIL) \
5986 goto label; \
5987 inst.operands[i].reg = val; \
5988 inst.operands[i].isscalar = 1; \
5989 } \
5990 while (0)
5991
5992#define po_misc_or_fail(expr) \
5993 do \
5994 { \
5995 if (expr) \
5996 goto failure; \
5997 } \
5998 while (0)
5999
6000#define po_misc_or_fail_no_backtrack(expr) \
6001 do \
6002 { \
6003 result = expr; \
6004 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6005 backtrack_pos = 0; \
6006 if (result != PARSE_OPERAND_SUCCESS) \
6007 goto failure; \
6008 } \
6009 while (0)
4962c51a 6010
c19d1205
ZW
6011 skip_whitespace (str);
6012
6013 for (i = 0; upat[i] != OP_stop; i++)
6014 {
5be8be5d
DG
6015 op_parse_code = upat[i];
6016 if (op_parse_code >= 1<<16)
6017 op_parse_code = thumb ? (op_parse_code >> 16)
6018 : (op_parse_code & ((1<<16)-1));
6019
6020 if (op_parse_code >= OP_FIRST_OPTIONAL)
c19d1205
ZW
6021 {
6022 /* Remember where we are in case we need to backtrack. */
9c2799c2 6023 gas_assert (!backtrack_pos);
c19d1205
ZW
6024 backtrack_pos = str;
6025 backtrack_error = inst.error;
6026 backtrack_index = i;
6027 }
6028
b6702015 6029 if (i > 0 && (i > 1 || inst.operands[0].present))
c19d1205
ZW
6030 po_char_or_fail (',');
6031
5be8be5d 6032 switch (op_parse_code)
c19d1205
ZW
6033 {
6034 /* Registers */
6035 case OP_oRRnpc:
5be8be5d 6036 case OP_oRRnpcsp:
c19d1205 6037 case OP_RRnpc:
5be8be5d 6038 case OP_RRnpcsp:
c19d1205
ZW
6039 case OP_oRR:
6040 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6041 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6042 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6043 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6044 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6045 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
5287ad62
JB
6046 case OP_oRND:
6047 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
cd2cf30b
PB
6048 case OP_RVC:
6049 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6050 break;
6051 /* Also accept generic coprocessor regs for unknown registers. */
6052 coproc_reg:
6053 po_reg_or_fail (REG_TYPE_CN);
6054 break;
c19d1205
ZW
6055 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6056 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6057 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6058 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6059 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6060 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6061 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6062 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6063 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6064 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
5287ad62
JB
6065 case OP_oRNQ:
6066 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6067 case OP_oRNDQ:
6068 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
037e8744
JB
6069 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6070 case OP_oRNSDQ:
6071 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
5287ad62
JB
6072
6073 /* Neon scalar. Using an element size of 8 means that some invalid
6074 scalars are accepted here, so deal with those in later code. */
6075 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6076
5287ad62
JB
6077 case OP_RNDQ_I0:
6078 {
6079 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6080 break;
6081 try_imm0:
6082 po_imm_or_fail (0, 0, TRUE);
6083 }
6084 break;
6085
037e8744
JB
6086 case OP_RVSD_I0:
6087 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6088 break;
6089
5287ad62
JB
6090 case OP_RR_RNSC:
6091 {
6092 po_scalar_or_goto (8, try_rr);
6093 break;
6094 try_rr:
6095 po_reg_or_fail (REG_TYPE_RN);
6096 }
6097 break;
6098
037e8744
JB
6099 case OP_RNSDQ_RNSC:
6100 {
6101 po_scalar_or_goto (8, try_nsdq);
6102 break;
6103 try_nsdq:
6104 po_reg_or_fail (REG_TYPE_NSDQ);
6105 }
6106 break;
6107
5287ad62
JB
6108 case OP_RNDQ_RNSC:
6109 {
6110 po_scalar_or_goto (8, try_ndq);
6111 break;
6112 try_ndq:
6113 po_reg_or_fail (REG_TYPE_NDQ);
6114 }
6115 break;
6116
6117 case OP_RND_RNSC:
6118 {
6119 po_scalar_or_goto (8, try_vfd);
6120 break;
6121 try_vfd:
6122 po_reg_or_fail (REG_TYPE_VFD);
6123 }
6124 break;
6125
6126 case OP_VMOV:
6127 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6128 not careful then bad things might happen. */
6129 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6130 break;
6131
4316f0d2 6132 case OP_RNDQ_Ibig:
5287ad62 6133 {
4316f0d2 6134 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
5287ad62 6135 break;
4316f0d2 6136 try_immbig:
5287ad62
JB
6137 /* There's a possibility of getting a 64-bit immediate here, so
6138 we need special handling. */
6139 if (parse_big_immediate (&str, i) == FAIL)
6140 {
6141 inst.error = _("immediate value is out of range");
6142 goto failure;
6143 }
6144 }
6145 break;
6146
6147 case OP_RNDQ_I63b:
6148 {
6149 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6150 break;
6151 try_shimm:
6152 po_imm_or_fail (0, 63, TRUE);
6153 }
6154 break;
c19d1205
ZW
6155
6156 case OP_RRnpcb:
6157 po_char_or_fail ('[');
6158 po_reg_or_fail (REG_TYPE_RN);
6159 po_char_or_fail (']');
6160 break;
a737bd4d 6161
55881a11 6162 case OP_RRnpctw:
c19d1205 6163 case OP_RRw:
b6702015 6164 case OP_oRRw:
c19d1205
ZW
6165 po_reg_or_fail (REG_TYPE_RN);
6166 if (skip_past_char (&str, '!') == SUCCESS)
6167 inst.operands[i].writeback = 1;
6168 break;
6169
6170 /* Immediates */
6171 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6172 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6173 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
5287ad62 6174 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
c19d1205
ZW
6175 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6176 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
5287ad62 6177 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
c19d1205 6178 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
5287ad62
JB
6179 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6180 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6181 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
c19d1205 6182 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
c19d1205
ZW
6183
6184 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6185 case OP_oI7b:
6186 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6187 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6188 case OP_oI31b:
6189 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
5287ad62 6190 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
c19d1205
ZW
6191 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6192
6193 /* Immediate variants */
6194 case OP_oI255c:
6195 po_char_or_fail ('{');
6196 po_imm_or_fail (0, 255, TRUE);
6197 po_char_or_fail ('}');
6198 break;
6199
6200 case OP_I31w:
6201 /* The expression parser chokes on a trailing !, so we have
6202 to find it first and zap it. */
6203 {
6204 char *s = str;
6205 while (*s && *s != ',')
6206 s++;
6207 if (s[-1] == '!')
6208 {
6209 s[-1] = '\0';
6210 inst.operands[i].writeback = 1;
6211 }
6212 po_imm_or_fail (0, 31, TRUE);
6213 if (str == s - 1)
6214 str = s;
6215 }
6216 break;
6217
6218 /* Expressions */
6219 case OP_EXPi: EXPi:
6220 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6221 GE_OPT_PREFIX));
6222 break;
6223
6224 case OP_EXP:
6225 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6226 GE_NO_PREFIX));
6227 break;
6228
6229 case OP_EXPr: EXPr:
6230 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6231 GE_NO_PREFIX));
6232 if (inst.reloc.exp.X_op == O_symbol)
a737bd4d 6233 {
c19d1205
ZW
6234 val = parse_reloc (&str);
6235 if (val == -1)
6236 {
6237 inst.error = _("unrecognized relocation suffix");
6238 goto failure;
6239 }
6240 else if (val != BFD_RELOC_UNUSED)
6241 {
6242 inst.operands[i].imm = val;
6243 inst.operands[i].hasreloc = 1;
6244 }
a737bd4d 6245 }
c19d1205 6246 break;
a737bd4d 6247
b6895b4f
PB
6248 /* Operand for MOVW or MOVT. */
6249 case OP_HALF:
6250 po_misc_or_fail (parse_half (&str));
6251 break;
6252
e07e6e58 6253 /* Register or expression. */
c19d1205
ZW
6254 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6255 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
a737bd4d 6256
e07e6e58 6257 /* Register or immediate. */
c19d1205
ZW
6258 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6259 I0: po_imm_or_fail (0, 0, FALSE); break;
a737bd4d 6260
c19d1205
ZW
6261 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6262 IF:
6263 if (!is_immediate_prefix (*str))
6264 goto bad_args;
6265 str++;
6266 val = parse_fpa_immediate (&str);
6267 if (val == FAIL)
6268 goto failure;
6269 /* FPA immediates are encoded as registers 8-15.
6270 parse_fpa_immediate has already applied the offset. */
6271 inst.operands[i].reg = val;
6272 inst.operands[i].isreg = 1;
6273 break;
09d92015 6274
2d447fca
JM
6275 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6276 I32z: po_imm_or_fail (0, 32, FALSE); break;
6277
e07e6e58 6278 /* Two kinds of register. */
c19d1205
ZW
6279 case OP_RIWR_RIWC:
6280 {
6281 struct reg_entry *rege = arm_reg_parse_multi (&str);
97f87066
JM
6282 if (!rege
6283 || (rege->type != REG_TYPE_MMXWR
6284 && rege->type != REG_TYPE_MMXWC
6285 && rege->type != REG_TYPE_MMXWCG))
c19d1205
ZW
6286 {
6287 inst.error = _("iWMMXt data or control register expected");
6288 goto failure;
6289 }
6290 inst.operands[i].reg = rege->number;
6291 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6292 }
6293 break;
09d92015 6294
41adaa5c
JM
6295 case OP_RIWC_RIWG:
6296 {
6297 struct reg_entry *rege = arm_reg_parse_multi (&str);
6298 if (!rege
6299 || (rege->type != REG_TYPE_MMXWC
6300 && rege->type != REG_TYPE_MMXWCG))
6301 {
6302 inst.error = _("iWMMXt control register expected");
6303 goto failure;
6304 }
6305 inst.operands[i].reg = rege->number;
6306 inst.operands[i].isreg = 1;
6307 }
6308 break;
6309
c19d1205
ZW
6310 /* Misc */
6311 case OP_CPSF: val = parse_cps_flags (&str); break;
6312 case OP_ENDI: val = parse_endian_specifier (&str); break;
6313 case OP_oROR: val = parse_ror (&str); break;
6314 case OP_PSR: val = parse_psr (&str); break;
6315 case OP_COND: val = parse_cond (&str); break;
62b3e311 6316 case OP_oBARRIER:val = parse_barrier (&str); break;
c19d1205 6317
037e8744
JB
6318 case OP_RVC_PSR:
6319 po_reg_or_goto (REG_TYPE_VFC, try_psr);
6320 inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */
6321 break;
6322 try_psr:
6323 val = parse_psr (&str);
6324 break;
6325
6326 case OP_APSR_RR:
6327 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6328 break;
6329 try_apsr:
6330 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6331 instruction). */
6332 if (strncasecmp (str, "APSR_", 5) == 0)
6333 {
6334 unsigned found = 0;
6335 str += 5;
6336 while (found < 15)
6337 switch (*str++)
6338 {
6339 case 'c': found = (found & 1) ? 16 : found | 1; break;
6340 case 'n': found = (found & 2) ? 16 : found | 2; break;
6341 case 'z': found = (found & 4) ? 16 : found | 4; break;
6342 case 'v': found = (found & 8) ? 16 : found | 8; break;
6343 default: found = 16;
6344 }
6345 if (found != 15)
6346 goto failure;
6347 inst.operands[i].isvec = 1;
f7c21dc7
NC
6348 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6349 inst.operands[i].reg = REG_PC;
037e8744
JB
6350 }
6351 else
6352 goto failure;
6353 break;
6354
92e90b6e
PB
6355 case OP_TB:
6356 po_misc_or_fail (parse_tb (&str));
6357 break;
6358
e07e6e58 6359 /* Register lists. */
c19d1205
ZW
6360 case OP_REGLST:
6361 val = parse_reg_list (&str);
6362 if (*str == '^')
6363 {
6364 inst.operands[1].writeback = 1;
6365 str++;
6366 }
6367 break;
09d92015 6368
c19d1205 6369 case OP_VRSLST:
5287ad62 6370 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
c19d1205 6371 break;
09d92015 6372
c19d1205 6373 case OP_VRDLST:
5287ad62 6374 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
c19d1205 6375 break;
a737bd4d 6376
037e8744
JB
6377 case OP_VRSDLST:
6378 /* Allow Q registers too. */
6379 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6380 REGLIST_NEON_D);
6381 if (val == FAIL)
6382 {
6383 inst.error = NULL;
6384 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6385 REGLIST_VFP_S);
6386 inst.operands[i].issingle = 1;
6387 }
6388 break;
6389
5287ad62
JB
6390 case OP_NRDLST:
6391 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6392 REGLIST_NEON_D);
6393 break;
6394
6395 case OP_NSTRLST:
dcbf9037
JB
6396 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6397 &inst.operands[i].vectype);
5287ad62
JB
6398 break;
6399
c19d1205
ZW
6400 /* Addressing modes */
6401 case OP_ADDR:
6402 po_misc_or_fail (parse_address (&str, i));
6403 break;
09d92015 6404
4962c51a
MS
6405 case OP_ADDRGLDR:
6406 po_misc_or_fail_no_backtrack (
6407 parse_address_group_reloc (&str, i, GROUP_LDR));
6408 break;
6409
6410 case OP_ADDRGLDRS:
6411 po_misc_or_fail_no_backtrack (
6412 parse_address_group_reloc (&str, i, GROUP_LDRS));
6413 break;
6414
6415 case OP_ADDRGLDC:
6416 po_misc_or_fail_no_backtrack (
6417 parse_address_group_reloc (&str, i, GROUP_LDC));
6418 break;
6419
c19d1205
ZW
6420 case OP_SH:
6421 po_misc_or_fail (parse_shifter_operand (&str, i));
6422 break;
09d92015 6423
4962c51a
MS
6424 case OP_SHG:
6425 po_misc_or_fail_no_backtrack (
6426 parse_shifter_operand_group_reloc (&str, i));
6427 break;
6428
c19d1205
ZW
6429 case OP_oSHll:
6430 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6431 break;
09d92015 6432
c19d1205
ZW
6433 case OP_oSHar:
6434 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6435 break;
09d92015 6436
c19d1205
ZW
6437 case OP_oSHllar:
6438 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6439 break;
09d92015 6440
c19d1205 6441 default:
5be8be5d 6442 as_fatal (_("unhandled operand code %d"), op_parse_code);
c19d1205 6443 }
09d92015 6444
c19d1205
ZW
6445 /* Various value-based sanity checks and shared operations. We
6446 do not signal immediate failures for the register constraints;
6447 this allows a syntax error to take precedence. */
5be8be5d 6448 switch (op_parse_code)
c19d1205
ZW
6449 {
6450 case OP_oRRnpc:
6451 case OP_RRnpc:
6452 case OP_RRnpcb:
6453 case OP_RRw:
b6702015 6454 case OP_oRRw:
c19d1205
ZW
6455 case OP_RRnpc_I0:
6456 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6457 inst.error = BAD_PC;
6458 break;
09d92015 6459
5be8be5d
DG
6460 case OP_oRRnpcsp:
6461 case OP_RRnpcsp:
6462 if (inst.operands[i].isreg)
6463 {
6464 if (inst.operands[i].reg == REG_PC)
6465 inst.error = BAD_PC;
6466 else if (inst.operands[i].reg == REG_SP)
6467 inst.error = BAD_SP;
6468 }
6469 break;
6470
55881a11
MGD
6471 case OP_RRnpctw:
6472 if (inst.operands[i].isreg
6473 && inst.operands[i].reg == REG_PC
6474 && (inst.operands[i].writeback || thumb))
6475 inst.error = BAD_PC;
6476 break;
6477
c19d1205
ZW
6478 case OP_CPSF:
6479 case OP_ENDI:
6480 case OP_oROR:
6481 case OP_PSR:
037e8744 6482 case OP_RVC_PSR:
c19d1205 6483 case OP_COND:
62b3e311 6484 case OP_oBARRIER:
c19d1205
ZW
6485 case OP_REGLST:
6486 case OP_VRSLST:
6487 case OP_VRDLST:
037e8744 6488 case OP_VRSDLST:
5287ad62
JB
6489 case OP_NRDLST:
6490 case OP_NSTRLST:
c19d1205
ZW
6491 if (val == FAIL)
6492 goto failure;
6493 inst.operands[i].imm = val;
6494 break;
a737bd4d 6495
c19d1205
ZW
6496 default:
6497 break;
6498 }
09d92015 6499
c19d1205
ZW
6500 /* If we get here, this operand was successfully parsed. */
6501 inst.operands[i].present = 1;
6502 continue;
09d92015 6503
c19d1205 6504 bad_args:
09d92015 6505 inst.error = BAD_ARGS;
c19d1205
ZW
6506
6507 failure:
6508 if (!backtrack_pos)
d252fdde
PB
6509 {
6510 /* The parse routine should already have set inst.error, but set a
5f4273c7 6511 default here just in case. */
d252fdde
PB
6512 if (!inst.error)
6513 inst.error = _("syntax error");
6514 return FAIL;
6515 }
c19d1205
ZW
6516
6517 /* Do not backtrack over a trailing optional argument that
6518 absorbed some text. We will only fail again, with the
6519 'garbage following instruction' error message, which is
6520 probably less helpful than the current one. */
6521 if (backtrack_index == i && backtrack_pos != str
6522 && upat[i+1] == OP_stop)
d252fdde
PB
6523 {
6524 if (!inst.error)
6525 inst.error = _("syntax error");
6526 return FAIL;
6527 }
c19d1205
ZW
6528
6529 /* Try again, skipping the optional argument at backtrack_pos. */
6530 str = backtrack_pos;
6531 inst.error = backtrack_error;
6532 inst.operands[backtrack_index].present = 0;
6533 i = backtrack_index;
6534 backtrack_pos = 0;
09d92015 6535 }
09d92015 6536
c19d1205
ZW
6537 /* Check that we have parsed all the arguments. */
6538 if (*str != '\0' && !inst.error)
6539 inst.error = _("garbage following instruction");
09d92015 6540
c19d1205 6541 return inst.error ? FAIL : SUCCESS;
09d92015
MM
6542}
6543
c19d1205
ZW
6544#undef po_char_or_fail
6545#undef po_reg_or_fail
6546#undef po_reg_or_goto
6547#undef po_imm_or_fail
5287ad62 6548#undef po_scalar_or_fail
e07e6e58 6549
c19d1205 6550/* Shorthand macro for instruction encoding functions issuing errors. */
e07e6e58
NC
6551#define constraint(expr, err) \
6552 do \
c19d1205 6553 { \
e07e6e58
NC
6554 if (expr) \
6555 { \
6556 inst.error = err; \
6557 return; \
6558 } \
c19d1205 6559 } \
e07e6e58 6560 while (0)
c19d1205 6561
fdfde340
JM
6562/* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6563 instructions are unpredictable if these registers are used. This
6564 is the BadReg predicate in ARM's Thumb-2 documentation. */
6565#define reject_bad_reg(reg) \
6566 do \
6567 if (reg == REG_SP || reg == REG_PC) \
6568 { \
6569 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6570 return; \
6571 } \
6572 while (0)
6573
94206790
MM
6574/* If REG is R13 (the stack pointer), warn that its use is
6575 deprecated. */
6576#define warn_deprecated_sp(reg) \
6577 do \
6578 if (warn_on_deprecated && reg == REG_SP) \
6579 as_warn (_("use of r13 is deprecated")); \
6580 while (0)
6581
c19d1205
ZW
6582/* Functions for operand encoding. ARM, then Thumb. */
6583
6584#define rotate_left(v, n) (v << n | v >> (32 - n))
6585
6586/* If VAL can be encoded in the immediate field of an ARM instruction,
6587 return the encoded form. Otherwise, return FAIL. */
6588
6589static unsigned int
6590encode_arm_immediate (unsigned int val)
09d92015 6591{
c19d1205
ZW
6592 unsigned int a, i;
6593
6594 for (i = 0; i < 32; i += 2)
6595 if ((a = rotate_left (val, i)) <= 0xff)
6596 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6597
6598 return FAIL;
09d92015
MM
6599}
6600
c19d1205
ZW
6601/* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6602 return the encoded form. Otherwise, return FAIL. */
6603static unsigned int
6604encode_thumb32_immediate (unsigned int val)
09d92015 6605{
c19d1205 6606 unsigned int a, i;
09d92015 6607
9c3c69f2 6608 if (val <= 0xff)
c19d1205 6609 return val;
a737bd4d 6610
9c3c69f2 6611 for (i = 1; i <= 24; i++)
09d92015 6612 {
9c3c69f2
PB
6613 a = val >> i;
6614 if ((val & ~(0xff << i)) == 0)
6615 return ((val >> i) & 0x7f) | ((32 - i) << 7);
09d92015 6616 }
a737bd4d 6617
c19d1205
ZW
6618 a = val & 0xff;
6619 if (val == ((a << 16) | a))
6620 return 0x100 | a;
6621 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6622 return 0x300 | a;
09d92015 6623
c19d1205
ZW
6624 a = val & 0xff00;
6625 if (val == ((a << 16) | a))
6626 return 0x200 | (a >> 8);
a737bd4d 6627
c19d1205 6628 return FAIL;
09d92015 6629}
5287ad62 6630/* Encode a VFP SP or DP register number into inst.instruction. */
09d92015
MM
6631
6632static void
5287ad62
JB
6633encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6634{
6635 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6636 && reg > 15)
6637 {
b1cc4aeb 6638 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
5287ad62
JB
6639 {
6640 if (thumb_mode)
6641 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
b1cc4aeb 6642 fpu_vfp_ext_d32);
5287ad62
JB
6643 else
6644 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
b1cc4aeb 6645 fpu_vfp_ext_d32);
5287ad62
JB
6646 }
6647 else
6648 {
dcbf9037 6649 first_error (_("D register out of range for selected VFP version"));
5287ad62
JB
6650 return;
6651 }
6652 }
6653
c19d1205 6654 switch (pos)
09d92015 6655 {
c19d1205
ZW
6656 case VFP_REG_Sd:
6657 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6658 break;
6659
6660 case VFP_REG_Sn:
6661 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6662 break;
6663
6664 case VFP_REG_Sm:
6665 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6666 break;
6667
5287ad62
JB
6668 case VFP_REG_Dd:
6669 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
6670 break;
5f4273c7 6671
5287ad62
JB
6672 case VFP_REG_Dn:
6673 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
6674 break;
5f4273c7 6675
5287ad62
JB
6676 case VFP_REG_Dm:
6677 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
6678 break;
6679
c19d1205
ZW
6680 default:
6681 abort ();
09d92015 6682 }
09d92015
MM
6683}
6684
c19d1205 6685/* Encode a <shift> in an ARM-format instruction. The immediate,
55cf6793 6686 if any, is handled by md_apply_fix. */
09d92015 6687static void
c19d1205 6688encode_arm_shift (int i)
09d92015 6689{
c19d1205
ZW
6690 if (inst.operands[i].shift_kind == SHIFT_RRX)
6691 inst.instruction |= SHIFT_ROR << 5;
6692 else
09d92015 6693 {
c19d1205
ZW
6694 inst.instruction |= inst.operands[i].shift_kind << 5;
6695 if (inst.operands[i].immisreg)
6696 {
6697 inst.instruction |= SHIFT_BY_REG;
6698 inst.instruction |= inst.operands[i].imm << 8;
6699 }
6700 else
6701 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
09d92015 6702 }
c19d1205 6703}
09d92015 6704
c19d1205
ZW
6705static void
6706encode_arm_shifter_operand (int i)
6707{
6708 if (inst.operands[i].isreg)
09d92015 6709 {
c19d1205
ZW
6710 inst.instruction |= inst.operands[i].reg;
6711 encode_arm_shift (i);
09d92015 6712 }
c19d1205
ZW
6713 else
6714 inst.instruction |= INST_IMMEDIATE;
09d92015
MM
6715}
6716
c19d1205 6717/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
09d92015 6718static void
c19d1205 6719encode_arm_addr_mode_common (int i, bfd_boolean is_t)
09d92015 6720{
9c2799c2 6721 gas_assert (inst.operands[i].isreg);
c19d1205 6722 inst.instruction |= inst.operands[i].reg << 16;
a737bd4d 6723
c19d1205 6724 if (inst.operands[i].preind)
09d92015 6725 {
c19d1205
ZW
6726 if (is_t)
6727 {
6728 inst.error = _("instruction does not accept preindexed addressing");
6729 return;
6730 }
6731 inst.instruction |= PRE_INDEX;
6732 if (inst.operands[i].writeback)
6733 inst.instruction |= WRITE_BACK;
09d92015 6734
c19d1205
ZW
6735 }
6736 else if (inst.operands[i].postind)
6737 {
9c2799c2 6738 gas_assert (inst.operands[i].writeback);
c19d1205
ZW
6739 if (is_t)
6740 inst.instruction |= WRITE_BACK;
6741 }
6742 else /* unindexed - only for coprocessor */
09d92015 6743 {
c19d1205 6744 inst.error = _("instruction does not accept unindexed addressing");
09d92015
MM
6745 return;
6746 }
6747
c19d1205
ZW
6748 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
6749 && (((inst.instruction & 0x000f0000) >> 16)
6750 == ((inst.instruction & 0x0000f000) >> 12)))
6751 as_warn ((inst.instruction & LOAD_BIT)
6752 ? _("destination register same as write-back base")
6753 : _("source register same as write-back base"));
09d92015
MM
6754}
6755
c19d1205
ZW
6756/* inst.operands[i] was set up by parse_address. Encode it into an
6757 ARM-format mode 2 load or store instruction. If is_t is true,
6758 reject forms that cannot be used with a T instruction (i.e. not
6759 post-indexed). */
a737bd4d 6760static void
c19d1205 6761encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
09d92015 6762{
5be8be5d
DG
6763 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
6764
c19d1205 6765 encode_arm_addr_mode_common (i, is_t);
a737bd4d 6766
c19d1205 6767 if (inst.operands[i].immisreg)
09d92015 6768 {
5be8be5d
DG
6769 constraint ((inst.operands[i].imm == REG_PC
6770 || (is_pc && inst.operands[i].writeback)),
6771 BAD_PC_ADDRESSING);
c19d1205
ZW
6772 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
6773 inst.instruction |= inst.operands[i].imm;
6774 if (!inst.operands[i].negative)
6775 inst.instruction |= INDEX_UP;
6776 if (inst.operands[i].shifted)
6777 {
6778 if (inst.operands[i].shift_kind == SHIFT_RRX)
6779 inst.instruction |= SHIFT_ROR << 5;
6780 else
6781 {
6782 inst.instruction |= inst.operands[i].shift_kind << 5;
6783 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
6784 }
6785 }
09d92015 6786 }
c19d1205 6787 else /* immediate offset in inst.reloc */
09d92015 6788 {
5be8be5d
DG
6789 if (is_pc && !inst.reloc.pc_rel)
6790 {
6791 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
6792 /* BAD_PC_ADDRESSING Condition =
6793 is_load => is_t
6794 which becomes !is_load || is_t. */
6795 constraint ((!is_load || is_t),
6796 BAD_PC_ADDRESSING);
6797 }
6798
c19d1205
ZW
6799 if (inst.reloc.type == BFD_RELOC_UNUSED)
6800 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
09d92015 6801 }
09d92015
MM
6802}
6803
c19d1205
ZW
6804/* inst.operands[i] was set up by parse_address. Encode it into an
6805 ARM-format mode 3 load or store instruction. Reject forms that
6806 cannot be used with such instructions. If is_t is true, reject
6807 forms that cannot be used with a T instruction (i.e. not
6808 post-indexed). */
6809static void
6810encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
09d92015 6811{
c19d1205 6812 if (inst.operands[i].immisreg && inst.operands[i].shifted)
09d92015 6813 {
c19d1205
ZW
6814 inst.error = _("instruction does not accept scaled register index");
6815 return;
09d92015 6816 }
a737bd4d 6817
c19d1205 6818 encode_arm_addr_mode_common (i, is_t);
a737bd4d 6819
c19d1205
ZW
6820 if (inst.operands[i].immisreg)
6821 {
5be8be5d
DG
6822 constraint ((inst.operands[i].imm == REG_PC
6823 || inst.operands[i].reg == REG_PC),
6824 BAD_PC_ADDRESSING);
c19d1205
ZW
6825 inst.instruction |= inst.operands[i].imm;
6826 if (!inst.operands[i].negative)
6827 inst.instruction |= INDEX_UP;
6828 }
6829 else /* immediate offset in inst.reloc */
6830 {
5be8be5d
DG
6831 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
6832 && inst.operands[i].writeback),
6833 BAD_PC_WRITEBACK);
c19d1205
ZW
6834 inst.instruction |= HWOFFSET_IMM;
6835 if (inst.reloc.type == BFD_RELOC_UNUSED)
6836 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
c19d1205 6837 }
a737bd4d
NC
6838}
6839
c19d1205
ZW
6840/* inst.operands[i] was set up by parse_address. Encode it into an
6841 ARM-format instruction. Reject all forms which cannot be encoded
6842 into a coprocessor load/store instruction. If wb_ok is false,
6843 reject use of writeback; if unind_ok is false, reject use of
6844 unindexed addressing. If reloc_override is not 0, use it instead
4962c51a
MS
6845 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6846 (in which case it is preserved). */
09d92015 6847
c19d1205
ZW
6848static int
6849encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
09d92015 6850{
c19d1205 6851 inst.instruction |= inst.operands[i].reg << 16;
a737bd4d 6852
9c2799c2 6853 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
09d92015 6854
c19d1205 6855 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
09d92015 6856 {
9c2799c2 6857 gas_assert (!inst.operands[i].writeback);
c19d1205
ZW
6858 if (!unind_ok)
6859 {
6860 inst.error = _("instruction does not support unindexed addressing");
6861 return FAIL;
6862 }
6863 inst.instruction |= inst.operands[i].imm;
6864 inst.instruction |= INDEX_UP;
6865 return SUCCESS;
09d92015 6866 }
a737bd4d 6867
c19d1205
ZW
6868 if (inst.operands[i].preind)
6869 inst.instruction |= PRE_INDEX;
a737bd4d 6870
c19d1205 6871 if (inst.operands[i].writeback)
09d92015 6872 {
c19d1205
ZW
6873 if (inst.operands[i].reg == REG_PC)
6874 {
6875 inst.error = _("pc may not be used with write-back");
6876 return FAIL;
6877 }
6878 if (!wb_ok)
6879 {
6880 inst.error = _("instruction does not support writeback");
6881 return FAIL;
6882 }
6883 inst.instruction |= WRITE_BACK;
09d92015 6884 }
a737bd4d 6885
c19d1205 6886 if (reloc_override)
21d799b5 6887 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
4962c51a
MS
6888 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
6889 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
6890 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
6891 {
6892 if (thumb_mode)
6893 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
6894 else
6895 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
6896 }
6897
c19d1205
ZW
6898 return SUCCESS;
6899}
a737bd4d 6900
c19d1205
ZW
6901/* inst.reloc.exp describes an "=expr" load pseudo-operation.
6902 Determine whether it can be performed with a move instruction; if
6903 it can, convert inst.instruction to that move instruction and
c921be7d
NC
6904 return TRUE; if it can't, convert inst.instruction to a literal-pool
6905 load and return FALSE. If this is not a valid thing to do in the
6906 current context, set inst.error and return TRUE.
a737bd4d 6907
c19d1205
ZW
6908 inst.operands[i] describes the destination register. */
6909
c921be7d 6910static bfd_boolean
c19d1205
ZW
6911move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
6912{
53365c0d
PB
6913 unsigned long tbit;
6914
6915 if (thumb_p)
6916 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
6917 else
6918 tbit = LOAD_BIT;
6919
6920 if ((inst.instruction & tbit) == 0)
09d92015 6921 {
c19d1205 6922 inst.error = _("invalid pseudo operation");
c921be7d 6923 return TRUE;
09d92015 6924 }
c19d1205 6925 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
09d92015
MM
6926 {
6927 inst.error = _("constant expression expected");
c921be7d 6928 return TRUE;
09d92015 6929 }
c19d1205 6930 if (inst.reloc.exp.X_op == O_constant)
09d92015 6931 {
c19d1205
ZW
6932 if (thumb_p)
6933 {
53365c0d 6934 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
c19d1205
ZW
6935 {
6936 /* This can be done with a mov(1) instruction. */
6937 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
6938 inst.instruction |= inst.reloc.exp.X_add_number;
c921be7d 6939 return TRUE;
c19d1205
ZW
6940 }
6941 }
6942 else
6943 {
6944 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
6945 if (value != FAIL)
6946 {
6947 /* This can be done with a mov instruction. */
6948 inst.instruction &= LITERAL_MASK;
6949 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
6950 inst.instruction |= value & 0xfff;
c921be7d 6951 return TRUE;
c19d1205 6952 }
09d92015 6953
c19d1205
ZW
6954 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
6955 if (value != FAIL)
6956 {
6957 /* This can be done with a mvn instruction. */
6958 inst.instruction &= LITERAL_MASK;
6959 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
6960 inst.instruction |= value & 0xfff;
c921be7d 6961 return TRUE;
c19d1205
ZW
6962 }
6963 }
09d92015
MM
6964 }
6965
c19d1205
ZW
6966 if (add_to_lit_pool () == FAIL)
6967 {
6968 inst.error = _("literal pool insertion failed");
c921be7d 6969 return TRUE;
c19d1205
ZW
6970 }
6971 inst.operands[1].reg = REG_PC;
6972 inst.operands[1].isreg = 1;
6973 inst.operands[1].preind = 1;
6974 inst.reloc.pc_rel = 1;
6975 inst.reloc.type = (thumb_p
6976 ? BFD_RELOC_ARM_THUMB_OFFSET
6977 : (mode_3
6978 ? BFD_RELOC_ARM_HWLITERAL
6979 : BFD_RELOC_ARM_LITERAL));
c921be7d 6980 return FALSE;
09d92015
MM
6981}
6982
5f4273c7 6983/* Functions for instruction encoding, sorted by sub-architecture.
c19d1205
ZW
6984 First some generics; their names are taken from the conventional
6985 bit positions for register arguments in ARM format instructions. */
09d92015 6986
a737bd4d 6987static void
c19d1205 6988do_noargs (void)
09d92015 6989{
c19d1205 6990}
a737bd4d 6991
c19d1205
ZW
6992static void
6993do_rd (void)
6994{
6995 inst.instruction |= inst.operands[0].reg << 12;
6996}
a737bd4d 6997
c19d1205
ZW
6998static void
6999do_rd_rm (void)
7000{
7001 inst.instruction |= inst.operands[0].reg << 12;
7002 inst.instruction |= inst.operands[1].reg;
7003}
09d92015 7004
c19d1205
ZW
7005static void
7006do_rd_rn (void)
7007{
7008 inst.instruction |= inst.operands[0].reg << 12;
7009 inst.instruction |= inst.operands[1].reg << 16;
7010}
a737bd4d 7011
c19d1205
ZW
7012static void
7013do_rn_rd (void)
7014{
7015 inst.instruction |= inst.operands[0].reg << 16;
7016 inst.instruction |= inst.operands[1].reg << 12;
7017}
09d92015 7018
c19d1205
ZW
7019static void
7020do_rd_rm_rn (void)
7021{
9a64e435 7022 unsigned Rn = inst.operands[2].reg;
708587a4 7023 /* Enforce restrictions on SWP instruction. */
9a64e435 7024 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
56adecf4
DG
7025 {
7026 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7027 _("Rn must not overlap other operands"));
7028
7029 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7030 if (warn_on_deprecated
7031 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
7032 as_warn (_("swp{b} use is deprecated for this architecture"));
7033
7034 }
c19d1205
ZW
7035 inst.instruction |= inst.operands[0].reg << 12;
7036 inst.instruction |= inst.operands[1].reg;
9a64e435 7037 inst.instruction |= Rn << 16;
c19d1205 7038}
09d92015 7039
c19d1205
ZW
7040static void
7041do_rd_rn_rm (void)
7042{
7043 inst.instruction |= inst.operands[0].reg << 12;
7044 inst.instruction |= inst.operands[1].reg << 16;
7045 inst.instruction |= inst.operands[2].reg;
7046}
a737bd4d 7047
c19d1205
ZW
7048static void
7049do_rm_rd_rn (void)
7050{
5be8be5d
DG
7051 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7052 constraint (((inst.reloc.exp.X_op != O_constant
7053 && inst.reloc.exp.X_op != O_illegal)
7054 || inst.reloc.exp.X_add_number != 0),
7055 BAD_ADDR_MODE);
c19d1205
ZW
7056 inst.instruction |= inst.operands[0].reg;
7057 inst.instruction |= inst.operands[1].reg << 12;
7058 inst.instruction |= inst.operands[2].reg << 16;
7059}
09d92015 7060
c19d1205
ZW
7061static void
7062do_imm0 (void)
7063{
7064 inst.instruction |= inst.operands[0].imm;
7065}
09d92015 7066
c19d1205
ZW
7067static void
7068do_rd_cpaddr (void)
7069{
7070 inst.instruction |= inst.operands[0].reg << 12;
7071 encode_arm_cp_address (1, TRUE, TRUE, 0);
09d92015 7072}
a737bd4d 7073
c19d1205
ZW
7074/* ARM instructions, in alphabetical order by function name (except
7075 that wrapper functions appear immediately after the function they
7076 wrap). */
09d92015 7077
c19d1205
ZW
7078/* This is a pseudo-op of the form "adr rd, label" to be converted
7079 into a relative address of the form "add rd, pc, #label-.-8". */
09d92015
MM
7080
7081static void
c19d1205 7082do_adr (void)
09d92015 7083{
c19d1205 7084 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 7085
c19d1205
ZW
7086 /* Frag hacking will turn this into a sub instruction if the offset turns
7087 out to be negative. */
7088 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
c19d1205 7089 inst.reloc.pc_rel = 1;
2fc8bdac 7090 inst.reloc.exp.X_add_number -= 8;
c19d1205 7091}
b99bd4ef 7092
c19d1205
ZW
7093/* This is a pseudo-op of the form "adrl rd, label" to be converted
7094 into a relative address of the form:
7095 add rd, pc, #low(label-.-8)"
7096 add rd, rd, #high(label-.-8)" */
b99bd4ef 7097
c19d1205
ZW
7098static void
7099do_adrl (void)
7100{
7101 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 7102
c19d1205
ZW
7103 /* Frag hacking will turn this into a sub instruction if the offset turns
7104 out to be negative. */
7105 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
c19d1205
ZW
7106 inst.reloc.pc_rel = 1;
7107 inst.size = INSN_SIZE * 2;
2fc8bdac 7108 inst.reloc.exp.X_add_number -= 8;
b99bd4ef
NC
7109}
7110
b99bd4ef 7111static void
c19d1205 7112do_arit (void)
b99bd4ef 7113{
c19d1205
ZW
7114 if (!inst.operands[1].present)
7115 inst.operands[1].reg = inst.operands[0].reg;
7116 inst.instruction |= inst.operands[0].reg << 12;
7117 inst.instruction |= inst.operands[1].reg << 16;
7118 encode_arm_shifter_operand (2);
7119}
b99bd4ef 7120
62b3e311
PB
7121static void
7122do_barrier (void)
7123{
7124 if (inst.operands[0].present)
7125 {
7126 constraint ((inst.instruction & 0xf0) != 0x40
7127 && inst.operands[0].imm != 0xf,
bd3ba5d1 7128 _("bad barrier type"));
62b3e311
PB
7129 inst.instruction |= inst.operands[0].imm;
7130 }
7131 else
7132 inst.instruction |= 0xf;
7133}
7134
c19d1205
ZW
7135static void
7136do_bfc (void)
7137{
7138 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7139 constraint (msb > 32, _("bit-field extends past end of register"));
7140 /* The instruction encoding stores the LSB and MSB,
7141 not the LSB and width. */
7142 inst.instruction |= inst.operands[0].reg << 12;
7143 inst.instruction |= inst.operands[1].imm << 7;
7144 inst.instruction |= (msb - 1) << 16;
7145}
b99bd4ef 7146
c19d1205
ZW
7147static void
7148do_bfi (void)
7149{
7150 unsigned int msb;
b99bd4ef 7151
c19d1205
ZW
7152 /* #0 in second position is alternative syntax for bfc, which is
7153 the same instruction but with REG_PC in the Rm field. */
7154 if (!inst.operands[1].isreg)
7155 inst.operands[1].reg = REG_PC;
b99bd4ef 7156
c19d1205
ZW
7157 msb = inst.operands[2].imm + inst.operands[3].imm;
7158 constraint (msb > 32, _("bit-field extends past end of register"));
7159 /* The instruction encoding stores the LSB and MSB,
7160 not the LSB and width. */
7161 inst.instruction |= inst.operands[0].reg << 12;
7162 inst.instruction |= inst.operands[1].reg;
7163 inst.instruction |= inst.operands[2].imm << 7;
7164 inst.instruction |= (msb - 1) << 16;
b99bd4ef
NC
7165}
7166
b99bd4ef 7167static void
c19d1205 7168do_bfx (void)
b99bd4ef 7169{
c19d1205
ZW
7170 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7171 _("bit-field extends past end of register"));
7172 inst.instruction |= inst.operands[0].reg << 12;
7173 inst.instruction |= inst.operands[1].reg;
7174 inst.instruction |= inst.operands[2].imm << 7;
7175 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7176}
09d92015 7177
c19d1205
ZW
7178/* ARM V5 breakpoint instruction (argument parse)
7179 BKPT <16 bit unsigned immediate>
7180 Instruction is not conditional.
7181 The bit pattern given in insns[] has the COND_ALWAYS condition,
7182 and it is an error if the caller tried to override that. */
b99bd4ef 7183
c19d1205
ZW
7184static void
7185do_bkpt (void)
7186{
7187 /* Top 12 of 16 bits to bits 19:8. */
7188 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
09d92015 7189
c19d1205
ZW
7190 /* Bottom 4 of 16 bits to bits 3:0. */
7191 inst.instruction |= inst.operands[0].imm & 0xf;
7192}
09d92015 7193
c19d1205
ZW
7194static void
7195encode_branch (int default_reloc)
7196{
7197 if (inst.operands[0].hasreloc)
7198 {
7199 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
7200 _("the only suffix valid here is '(plt)'"));
267bf995 7201 inst.reloc.type = BFD_RELOC_ARM_PLT32;
c19d1205 7202 }
b99bd4ef 7203 else
c19d1205 7204 {
21d799b5 7205 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
c19d1205 7206 }
2fc8bdac 7207 inst.reloc.pc_rel = 1;
b99bd4ef
NC
7208}
7209
b99bd4ef 7210static void
c19d1205 7211do_branch (void)
b99bd4ef 7212{
39b41c9c
PB
7213#ifdef OBJ_ELF
7214 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7215 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7216 else
7217#endif
7218 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7219}
7220
7221static void
7222do_bl (void)
7223{
7224#ifdef OBJ_ELF
7225 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7226 {
7227 if (inst.cond == COND_ALWAYS)
7228 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7229 else
7230 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7231 }
7232 else
7233#endif
7234 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
c19d1205 7235}
b99bd4ef 7236
c19d1205
ZW
7237/* ARM V5 branch-link-exchange instruction (argument parse)
7238 BLX <target_addr> ie BLX(1)
7239 BLX{<condition>} <Rm> ie BLX(2)
7240 Unfortunately, there are two different opcodes for this mnemonic.
7241 So, the insns[].value is not used, and the code here zaps values
7242 into inst.instruction.
7243 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
b99bd4ef 7244
c19d1205
ZW
7245static void
7246do_blx (void)
7247{
7248 if (inst.operands[0].isreg)
b99bd4ef 7249 {
c19d1205
ZW
7250 /* Arg is a register; the opcode provided by insns[] is correct.
7251 It is not illegal to do "blx pc", just useless. */
7252 if (inst.operands[0].reg == REG_PC)
7253 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
b99bd4ef 7254
c19d1205
ZW
7255 inst.instruction |= inst.operands[0].reg;
7256 }
7257 else
b99bd4ef 7258 {
c19d1205 7259 /* Arg is an address; this instruction cannot be executed
267bf995
RR
7260 conditionally, and the opcode must be adjusted.
7261 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7262 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
c19d1205 7263 constraint (inst.cond != COND_ALWAYS, BAD_COND);
2fc8bdac 7264 inst.instruction = 0xfa000000;
267bf995 7265 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
b99bd4ef 7266 }
c19d1205
ZW
7267}
7268
7269static void
7270do_bx (void)
7271{
845b51d6
PB
7272 bfd_boolean want_reloc;
7273
c19d1205
ZW
7274 if (inst.operands[0].reg == REG_PC)
7275 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
b99bd4ef 7276
c19d1205 7277 inst.instruction |= inst.operands[0].reg;
845b51d6
PB
7278 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7279 it is for ARMv4t or earlier. */
7280 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7281 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7282 want_reloc = TRUE;
7283
5ad34203 7284#ifdef OBJ_ELF
845b51d6 7285 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
5ad34203 7286#endif
584206db 7287 want_reloc = FALSE;
845b51d6
PB
7288
7289 if (want_reloc)
7290 inst.reloc.type = BFD_RELOC_ARM_V4BX;
09d92015
MM
7291}
7292
c19d1205
ZW
7293
7294/* ARM v5TEJ. Jump to Jazelle code. */
a737bd4d
NC
7295
7296static void
c19d1205 7297do_bxj (void)
a737bd4d 7298{
c19d1205
ZW
7299 if (inst.operands[0].reg == REG_PC)
7300 as_tsktsk (_("use of r15 in bxj is not really useful"));
7301
7302 inst.instruction |= inst.operands[0].reg;
a737bd4d
NC
7303}
7304
c19d1205
ZW
7305/* Co-processor data operation:
7306 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7307 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7308static void
7309do_cdp (void)
7310{
7311 inst.instruction |= inst.operands[0].reg << 8;
7312 inst.instruction |= inst.operands[1].imm << 20;
7313 inst.instruction |= inst.operands[2].reg << 12;
7314 inst.instruction |= inst.operands[3].reg << 16;
7315 inst.instruction |= inst.operands[4].reg;
7316 inst.instruction |= inst.operands[5].imm << 5;
7317}
a737bd4d
NC
7318
7319static void
c19d1205 7320do_cmp (void)
a737bd4d 7321{
c19d1205
ZW
7322 inst.instruction |= inst.operands[0].reg << 16;
7323 encode_arm_shifter_operand (1);
a737bd4d
NC
7324}
7325
c19d1205
ZW
7326/* Transfer between coprocessor and ARM registers.
7327 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7328 MRC2
7329 MCR{cond}
7330 MCR2
7331
7332 No special properties. */
09d92015
MM
7333
7334static void
c19d1205 7335do_co_reg (void)
09d92015 7336{
fdfde340
JM
7337 unsigned Rd;
7338
7339 Rd = inst.operands[2].reg;
7340 if (thumb_mode)
7341 {
7342 if (inst.instruction == 0xee000010
7343 || inst.instruction == 0xfe000010)
7344 /* MCR, MCR2 */
7345 reject_bad_reg (Rd);
7346 else
7347 /* MRC, MRC2 */
7348 constraint (Rd == REG_SP, BAD_SP);
7349 }
7350 else
7351 {
7352 /* MCR */
7353 if (inst.instruction == 0xe000010)
7354 constraint (Rd == REG_PC, BAD_PC);
7355 }
7356
7357
c19d1205
ZW
7358 inst.instruction |= inst.operands[0].reg << 8;
7359 inst.instruction |= inst.operands[1].imm << 21;
fdfde340 7360 inst.instruction |= Rd << 12;
c19d1205
ZW
7361 inst.instruction |= inst.operands[3].reg << 16;
7362 inst.instruction |= inst.operands[4].reg;
7363 inst.instruction |= inst.operands[5].imm << 5;
7364}
09d92015 7365
c19d1205
ZW
7366/* Transfer between coprocessor register and pair of ARM registers.
7367 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7368 MCRR2
7369 MRRC{cond}
7370 MRRC2
b99bd4ef 7371
c19d1205 7372 Two XScale instructions are special cases of these:
09d92015 7373
c19d1205
ZW
7374 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7375 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
b99bd4ef 7376
5f4273c7 7377 Result unpredictable if Rd or Rn is R15. */
a737bd4d 7378
c19d1205
ZW
7379static void
7380do_co_reg2c (void)
7381{
fdfde340
JM
7382 unsigned Rd, Rn;
7383
7384 Rd = inst.operands[2].reg;
7385 Rn = inst.operands[3].reg;
7386
7387 if (thumb_mode)
7388 {
7389 reject_bad_reg (Rd);
7390 reject_bad_reg (Rn);
7391 }
7392 else
7393 {
7394 constraint (Rd == REG_PC, BAD_PC);
7395 constraint (Rn == REG_PC, BAD_PC);
7396 }
7397
c19d1205
ZW
7398 inst.instruction |= inst.operands[0].reg << 8;
7399 inst.instruction |= inst.operands[1].imm << 4;
fdfde340
JM
7400 inst.instruction |= Rd << 12;
7401 inst.instruction |= Rn << 16;
c19d1205 7402 inst.instruction |= inst.operands[4].reg;
b99bd4ef
NC
7403}
7404
c19d1205
ZW
7405static void
7406do_cpsi (void)
7407{
7408 inst.instruction |= inst.operands[0].imm << 6;
a028a6f5
PB
7409 if (inst.operands[1].present)
7410 {
7411 inst.instruction |= CPSI_MMOD;
7412 inst.instruction |= inst.operands[1].imm;
7413 }
c19d1205 7414}
b99bd4ef 7415
62b3e311
PB
7416static void
7417do_dbg (void)
7418{
7419 inst.instruction |= inst.operands[0].imm;
7420}
7421
b99bd4ef 7422static void
c19d1205 7423do_it (void)
b99bd4ef 7424{
c19d1205 7425 /* There is no IT instruction in ARM mode. We
e07e6e58
NC
7426 process it to do the validation as if in
7427 thumb mode, just in case the code gets
7428 assembled for thumb using the unified syntax. */
7429
c19d1205 7430 inst.size = 0;
e07e6e58
NC
7431 if (unified_syntax)
7432 {
7433 set_it_insn_type (IT_INSN);
7434 now_it.mask = (inst.instruction & 0xf) | 0x10;
7435 now_it.cc = inst.operands[0].imm;
7436 }
09d92015 7437}
b99bd4ef 7438
09d92015 7439static void
c19d1205 7440do_ldmstm (void)
ea6ef066 7441{
c19d1205
ZW
7442 int base_reg = inst.operands[0].reg;
7443 int range = inst.operands[1].imm;
ea6ef066 7444
c19d1205
ZW
7445 inst.instruction |= base_reg << 16;
7446 inst.instruction |= range;
ea6ef066 7447
c19d1205
ZW
7448 if (inst.operands[1].writeback)
7449 inst.instruction |= LDM_TYPE_2_OR_3;
09d92015 7450
c19d1205 7451 if (inst.operands[0].writeback)
ea6ef066 7452 {
c19d1205
ZW
7453 inst.instruction |= WRITE_BACK;
7454 /* Check for unpredictable uses of writeback. */
7455 if (inst.instruction & LOAD_BIT)
09d92015 7456 {
c19d1205
ZW
7457 /* Not allowed in LDM type 2. */
7458 if ((inst.instruction & LDM_TYPE_2_OR_3)
7459 && ((range & (1 << REG_PC)) == 0))
7460 as_warn (_("writeback of base register is UNPREDICTABLE"));
7461 /* Only allowed if base reg not in list for other types. */
7462 else if (range & (1 << base_reg))
7463 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7464 }
7465 else /* STM. */
7466 {
7467 /* Not allowed for type 2. */
7468 if (inst.instruction & LDM_TYPE_2_OR_3)
7469 as_warn (_("writeback of base register is UNPREDICTABLE"));
7470 /* Only allowed if base reg not in list, or first in list. */
7471 else if ((range & (1 << base_reg))
7472 && (range & ((1 << base_reg) - 1)))
7473 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
09d92015 7474 }
ea6ef066 7475 }
a737bd4d
NC
7476}
7477
c19d1205
ZW
7478/* ARMv5TE load-consecutive (argument parse)
7479 Mode is like LDRH.
7480
7481 LDRccD R, mode
7482 STRccD R, mode. */
7483
a737bd4d 7484static void
c19d1205 7485do_ldrd (void)
a737bd4d 7486{
c19d1205
ZW
7487 constraint (inst.operands[0].reg % 2 != 0,
7488 _("first destination register must be even"));
7489 constraint (inst.operands[1].present
7490 && inst.operands[1].reg != inst.operands[0].reg + 1,
7491 _("can only load two consecutive registers"));
7492 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7493 constraint (!inst.operands[2].isreg, _("'[' expected"));
a737bd4d 7494
c19d1205
ZW
7495 if (!inst.operands[1].present)
7496 inst.operands[1].reg = inst.operands[0].reg + 1;
5f4273c7 7497
c19d1205 7498 if (inst.instruction & LOAD_BIT)
a737bd4d 7499 {
c19d1205
ZW
7500 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7501 register and the first register written; we have to diagnose
7502 overlap between the base and the second register written here. */
ea6ef066 7503
c19d1205
ZW
7504 if (inst.operands[2].reg == inst.operands[1].reg
7505 && (inst.operands[2].writeback || inst.operands[2].postind))
7506 as_warn (_("base register written back, and overlaps "
7507 "second destination register"));
b05fe5cf 7508
c19d1205
ZW
7509 /* For an index-register load, the index register must not overlap the
7510 destination (even if not write-back). */
7511 else if (inst.operands[2].immisreg
ca3f61f7
NC
7512 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
7513 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
c19d1205 7514 as_warn (_("index register overlaps destination register"));
b05fe5cf 7515 }
c19d1205
ZW
7516
7517 inst.instruction |= inst.operands[0].reg << 12;
7518 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
b05fe5cf
ZW
7519}
7520
7521static void
c19d1205 7522do_ldrex (void)
b05fe5cf 7523{
c19d1205
ZW
7524 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
7525 || inst.operands[1].postind || inst.operands[1].writeback
7526 || inst.operands[1].immisreg || inst.operands[1].shifted
01cfc07f
NC
7527 || inst.operands[1].negative
7528 /* This can arise if the programmer has written
7529 strex rN, rM, foo
7530 or if they have mistakenly used a register name as the last
7531 operand, eg:
7532 strex rN, rM, rX
7533 It is very difficult to distinguish between these two cases
7534 because "rX" might actually be a label. ie the register
7535 name has been occluded by a symbol of the same name. So we
7536 just generate a general 'bad addressing mode' type error
7537 message and leave it up to the programmer to discover the
7538 true cause and fix their mistake. */
7539 || (inst.operands[1].reg == REG_PC),
7540 BAD_ADDR_MODE);
b05fe5cf 7541
c19d1205
ZW
7542 constraint (inst.reloc.exp.X_op != O_constant
7543 || inst.reloc.exp.X_add_number != 0,
7544 _("offset must be zero in ARM encoding"));
b05fe5cf 7545
5be8be5d
DG
7546 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
7547
c19d1205
ZW
7548 inst.instruction |= inst.operands[0].reg << 12;
7549 inst.instruction |= inst.operands[1].reg << 16;
7550 inst.reloc.type = BFD_RELOC_UNUSED;
b05fe5cf
ZW
7551}
7552
7553static void
c19d1205 7554do_ldrexd (void)
b05fe5cf 7555{
c19d1205
ZW
7556 constraint (inst.operands[0].reg % 2 != 0,
7557 _("even register required"));
7558 constraint (inst.operands[1].present
7559 && inst.operands[1].reg != inst.operands[0].reg + 1,
7560 _("can only load two consecutive registers"));
7561 /* If op 1 were present and equal to PC, this function wouldn't
7562 have been called in the first place. */
7563 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
b05fe5cf 7564
c19d1205
ZW
7565 inst.instruction |= inst.operands[0].reg << 12;
7566 inst.instruction |= inst.operands[2].reg << 16;
b05fe5cf
ZW
7567}
7568
7569static void
c19d1205 7570do_ldst (void)
b05fe5cf 7571{
c19d1205
ZW
7572 inst.instruction |= inst.operands[0].reg << 12;
7573 if (!inst.operands[1].isreg)
7574 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
b05fe5cf 7575 return;
c19d1205 7576 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
b05fe5cf
ZW
7577}
7578
7579static void
c19d1205 7580do_ldstt (void)
b05fe5cf 7581{
c19d1205
ZW
7582 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7583 reject [Rn,...]. */
7584 if (inst.operands[1].preind)
b05fe5cf 7585 {
bd3ba5d1
NC
7586 constraint (inst.reloc.exp.X_op != O_constant
7587 || inst.reloc.exp.X_add_number != 0,
c19d1205 7588 _("this instruction requires a post-indexed address"));
b05fe5cf 7589
c19d1205
ZW
7590 inst.operands[1].preind = 0;
7591 inst.operands[1].postind = 1;
7592 inst.operands[1].writeback = 1;
b05fe5cf 7593 }
c19d1205
ZW
7594 inst.instruction |= inst.operands[0].reg << 12;
7595 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
7596}
b05fe5cf 7597
c19d1205 7598/* Halfword and signed-byte load/store operations. */
b05fe5cf 7599
c19d1205
ZW
7600static void
7601do_ldstv4 (void)
7602{
ff4a8d2b 7603 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
c19d1205
ZW
7604 inst.instruction |= inst.operands[0].reg << 12;
7605 if (!inst.operands[1].isreg)
7606 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
b05fe5cf 7607 return;
c19d1205 7608 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
b05fe5cf
ZW
7609}
7610
7611static void
c19d1205 7612do_ldsttv4 (void)
b05fe5cf 7613{
c19d1205
ZW
7614 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7615 reject [Rn,...]. */
7616 if (inst.operands[1].preind)
b05fe5cf 7617 {
bd3ba5d1
NC
7618 constraint (inst.reloc.exp.X_op != O_constant
7619 || inst.reloc.exp.X_add_number != 0,
c19d1205 7620 _("this instruction requires a post-indexed address"));
b05fe5cf 7621
c19d1205
ZW
7622 inst.operands[1].preind = 0;
7623 inst.operands[1].postind = 1;
7624 inst.operands[1].writeback = 1;
b05fe5cf 7625 }
c19d1205
ZW
7626 inst.instruction |= inst.operands[0].reg << 12;
7627 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
7628}
b05fe5cf 7629
c19d1205
ZW
7630/* Co-processor register load/store.
7631 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7632static void
7633do_lstc (void)
7634{
7635 inst.instruction |= inst.operands[0].reg << 8;
7636 inst.instruction |= inst.operands[1].reg << 12;
7637 encode_arm_cp_address (2, TRUE, TRUE, 0);
b05fe5cf
ZW
7638}
7639
b05fe5cf 7640static void
c19d1205 7641do_mlas (void)
b05fe5cf 7642{
8fb9d7b9 7643 /* This restriction does not apply to mls (nor to mla in v6 or later). */
c19d1205 7644 if (inst.operands[0].reg == inst.operands[1].reg
8fb9d7b9 7645 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
c19d1205 7646 && !(inst.instruction & 0x00400000))
8fb9d7b9 7647 as_tsktsk (_("Rd and Rm should be different in mla"));
b05fe5cf 7648
c19d1205
ZW
7649 inst.instruction |= inst.operands[0].reg << 16;
7650 inst.instruction |= inst.operands[1].reg;
7651 inst.instruction |= inst.operands[2].reg << 8;
7652 inst.instruction |= inst.operands[3].reg << 12;
c19d1205 7653}
b05fe5cf 7654
c19d1205
ZW
7655static void
7656do_mov (void)
7657{
7658 inst.instruction |= inst.operands[0].reg << 12;
7659 encode_arm_shifter_operand (1);
7660}
b05fe5cf 7661
c19d1205
ZW
7662/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7663static void
7664do_mov16 (void)
7665{
b6895b4f
PB
7666 bfd_vma imm;
7667 bfd_boolean top;
7668
7669 top = (inst.instruction & 0x00400000) != 0;
7670 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
7671 _(":lower16: not allowed this instruction"));
7672 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
7673 _(":upper16: not allowed instruction"));
c19d1205 7674 inst.instruction |= inst.operands[0].reg << 12;
b6895b4f
PB
7675 if (inst.reloc.type == BFD_RELOC_UNUSED)
7676 {
7677 imm = inst.reloc.exp.X_add_number;
7678 /* The value is in two pieces: 0:11, 16:19. */
7679 inst.instruction |= (imm & 0x00000fff);
7680 inst.instruction |= (imm & 0x0000f000) << 4;
7681 }
b05fe5cf 7682}
b99bd4ef 7683
037e8744
JB
7684static void do_vfp_nsyn_opcode (const char *);
7685
7686static int
7687do_vfp_nsyn_mrs (void)
7688{
7689 if (inst.operands[0].isvec)
7690 {
7691 if (inst.operands[1].reg != 1)
7692 first_error (_("operand 1 must be FPSCR"));
7693 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
7694 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
7695 do_vfp_nsyn_opcode ("fmstat");
7696 }
7697 else if (inst.operands[1].isvec)
7698 do_vfp_nsyn_opcode ("fmrx");
7699 else
7700 return FAIL;
5f4273c7 7701
037e8744
JB
7702 return SUCCESS;
7703}
7704
7705static int
7706do_vfp_nsyn_msr (void)
7707{
7708 if (inst.operands[0].isvec)
7709 do_vfp_nsyn_opcode ("fmxr");
7710 else
7711 return FAIL;
7712
7713 return SUCCESS;
7714}
7715
f7c21dc7
NC
7716static void
7717do_vmrs (void)
7718{
7719 unsigned Rt = inst.operands[0].reg;
7720
7721 if (thumb_mode && inst.operands[0].reg == REG_SP)
7722 {
7723 inst.error = BAD_SP;
7724 return;
7725 }
7726
7727 /* APSR_ sets isvec. All other refs to PC are illegal. */
7728 if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
7729 {
7730 inst.error = BAD_PC;
7731 return;
7732 }
7733
7734 if (inst.operands[1].reg != 1)
7735 first_error (_("operand 1 must be FPSCR"));
7736
7737 inst.instruction |= (Rt << 12);
7738}
7739
7740static void
7741do_vmsr (void)
7742{
7743 unsigned Rt = inst.operands[1].reg;
7744
7745 if (thumb_mode)
7746 reject_bad_reg (Rt);
7747 else if (Rt == REG_PC)
7748 {
7749 inst.error = BAD_PC;
7750 return;
7751 }
7752
7753 if (inst.operands[0].reg != 1)
7754 first_error (_("operand 0 must be FPSCR"));
7755
7756 inst.instruction |= (Rt << 12);
7757}
7758
b99bd4ef 7759static void
c19d1205 7760do_mrs (void)
b99bd4ef 7761{
037e8744
JB
7762 if (do_vfp_nsyn_mrs () == SUCCESS)
7763 return;
7764
c19d1205
ZW
7765 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7766 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
7767 != (PSR_c|PSR_f),
7768 _("'CPSR' or 'SPSR' expected"));
ff4a8d2b 7769 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
c19d1205
ZW
7770 inst.instruction |= inst.operands[0].reg << 12;
7771 inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
7772}
b99bd4ef 7773
c19d1205
ZW
7774/* Two possible forms:
7775 "{C|S}PSR_<field>, Rm",
7776 "{C|S}PSR_f, #expression". */
b99bd4ef 7777
c19d1205
ZW
7778static void
7779do_msr (void)
7780{
037e8744
JB
7781 if (do_vfp_nsyn_msr () == SUCCESS)
7782 return;
7783
c19d1205
ZW
7784 inst.instruction |= inst.operands[0].imm;
7785 if (inst.operands[1].isreg)
7786 inst.instruction |= inst.operands[1].reg;
7787 else
b99bd4ef 7788 {
c19d1205
ZW
7789 inst.instruction |= INST_IMMEDIATE;
7790 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7791 inst.reloc.pc_rel = 0;
b99bd4ef 7792 }
b99bd4ef
NC
7793}
7794
c19d1205
ZW
7795static void
7796do_mul (void)
a737bd4d 7797{
ff4a8d2b
NC
7798 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
7799
c19d1205
ZW
7800 if (!inst.operands[2].present)
7801 inst.operands[2].reg = inst.operands[0].reg;
7802 inst.instruction |= inst.operands[0].reg << 16;
7803 inst.instruction |= inst.operands[1].reg;
7804 inst.instruction |= inst.operands[2].reg << 8;
a737bd4d 7805
8fb9d7b9
MS
7806 if (inst.operands[0].reg == inst.operands[1].reg
7807 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
7808 as_tsktsk (_("Rd and Rm should be different in mul"));
a737bd4d
NC
7809}
7810
c19d1205
ZW
7811/* Long Multiply Parser
7812 UMULL RdLo, RdHi, Rm, Rs
7813 SMULL RdLo, RdHi, Rm, Rs
7814 UMLAL RdLo, RdHi, Rm, Rs
7815 SMLAL RdLo, RdHi, Rm, Rs. */
b99bd4ef
NC
7816
7817static void
c19d1205 7818do_mull (void)
b99bd4ef 7819{
c19d1205
ZW
7820 inst.instruction |= inst.operands[0].reg << 12;
7821 inst.instruction |= inst.operands[1].reg << 16;
7822 inst.instruction |= inst.operands[2].reg;
7823 inst.instruction |= inst.operands[3].reg << 8;
b99bd4ef 7824
682b27ad
PB
7825 /* rdhi and rdlo must be different. */
7826 if (inst.operands[0].reg == inst.operands[1].reg)
7827 as_tsktsk (_("rdhi and rdlo must be different"));
7828
7829 /* rdhi, rdlo and rm must all be different before armv6. */
7830 if ((inst.operands[0].reg == inst.operands[2].reg
c19d1205 7831 || inst.operands[1].reg == inst.operands[2].reg)
682b27ad 7832 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
c19d1205
ZW
7833 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7834}
b99bd4ef 7835
c19d1205
ZW
7836static void
7837do_nop (void)
7838{
e7495e45
NS
7839 if (inst.operands[0].present
7840 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
c19d1205
ZW
7841 {
7842 /* Architectural NOP hints are CPSR sets with no bits selected. */
7843 inst.instruction &= 0xf0000000;
e7495e45
NS
7844 inst.instruction |= 0x0320f000;
7845 if (inst.operands[0].present)
7846 inst.instruction |= inst.operands[0].imm;
c19d1205 7847 }
b99bd4ef
NC
7848}
7849
c19d1205
ZW
7850/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7851 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7852 Condition defaults to COND_ALWAYS.
7853 Error if Rd, Rn or Rm are R15. */
b99bd4ef
NC
7854
7855static void
c19d1205 7856do_pkhbt (void)
b99bd4ef 7857{
c19d1205
ZW
7858 inst.instruction |= inst.operands[0].reg << 12;
7859 inst.instruction |= inst.operands[1].reg << 16;
7860 inst.instruction |= inst.operands[2].reg;
7861 if (inst.operands[3].present)
7862 encode_arm_shift (3);
7863}
b99bd4ef 7864
c19d1205 7865/* ARM V6 PKHTB (Argument Parse). */
b99bd4ef 7866
c19d1205
ZW
7867static void
7868do_pkhtb (void)
7869{
7870 if (!inst.operands[3].present)
b99bd4ef 7871 {
c19d1205
ZW
7872 /* If the shift specifier is omitted, turn the instruction
7873 into pkhbt rd, rm, rn. */
7874 inst.instruction &= 0xfff00010;
7875 inst.instruction |= inst.operands[0].reg << 12;
7876 inst.instruction |= inst.operands[1].reg;
7877 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC
7878 }
7879 else
7880 {
c19d1205
ZW
7881 inst.instruction |= inst.operands[0].reg << 12;
7882 inst.instruction |= inst.operands[1].reg << 16;
7883 inst.instruction |= inst.operands[2].reg;
7884 encode_arm_shift (3);
b99bd4ef
NC
7885 }
7886}
7887
c19d1205
ZW
7888/* ARMv5TE: Preload-Cache
7889
7890 PLD <addr_mode>
7891
7892 Syntactically, like LDR with B=1, W=0, L=1. */
b99bd4ef
NC
7893
7894static void
c19d1205 7895do_pld (void)
b99bd4ef 7896{
c19d1205
ZW
7897 constraint (!inst.operands[0].isreg,
7898 _("'[' expected after PLD mnemonic"));
7899 constraint (inst.operands[0].postind,
7900 _("post-indexed expression used in preload instruction"));
7901 constraint (inst.operands[0].writeback,
7902 _("writeback used in preload instruction"));
7903 constraint (!inst.operands[0].preind,
7904 _("unindexed addressing used in preload instruction"));
c19d1205
ZW
7905 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
7906}
b99bd4ef 7907
62b3e311
PB
7908/* ARMv7: PLI <addr_mode> */
7909static void
7910do_pli (void)
7911{
7912 constraint (!inst.operands[0].isreg,
7913 _("'[' expected after PLI mnemonic"));
7914 constraint (inst.operands[0].postind,
7915 _("post-indexed expression used in preload instruction"));
7916 constraint (inst.operands[0].writeback,
7917 _("writeback used in preload instruction"));
7918 constraint (!inst.operands[0].preind,
7919 _("unindexed addressing used in preload instruction"));
7920 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
7921 inst.instruction &= ~PRE_INDEX;
7922}
7923
c19d1205
ZW
7924static void
7925do_push_pop (void)
7926{
7927 inst.operands[1] = inst.operands[0];
7928 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
7929 inst.operands[0].isreg = 1;
7930 inst.operands[0].writeback = 1;
7931 inst.operands[0].reg = REG_SP;
7932 do_ldmstm ();
7933}
b99bd4ef 7934
c19d1205
ZW
7935/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7936 word at the specified address and the following word
7937 respectively.
7938 Unconditionally executed.
7939 Error if Rn is R15. */
b99bd4ef 7940
c19d1205
ZW
7941static void
7942do_rfe (void)
7943{
7944 inst.instruction |= inst.operands[0].reg << 16;
7945 if (inst.operands[0].writeback)
7946 inst.instruction |= WRITE_BACK;
7947}
b99bd4ef 7948
c19d1205 7949/* ARM V6 ssat (argument parse). */
b99bd4ef 7950
c19d1205
ZW
7951static void
7952do_ssat (void)
7953{
7954 inst.instruction |= inst.operands[0].reg << 12;
7955 inst.instruction |= (inst.operands[1].imm - 1) << 16;
7956 inst.instruction |= inst.operands[2].reg;
b99bd4ef 7957
c19d1205
ZW
7958 if (inst.operands[3].present)
7959 encode_arm_shift (3);
b99bd4ef
NC
7960}
7961
c19d1205 7962/* ARM V6 usat (argument parse). */
b99bd4ef
NC
7963
7964static void
c19d1205 7965do_usat (void)
b99bd4ef 7966{
c19d1205
ZW
7967 inst.instruction |= inst.operands[0].reg << 12;
7968 inst.instruction |= inst.operands[1].imm << 16;
7969 inst.instruction |= inst.operands[2].reg;
b99bd4ef 7970
c19d1205
ZW
7971 if (inst.operands[3].present)
7972 encode_arm_shift (3);
b99bd4ef
NC
7973}
7974
c19d1205 7975/* ARM V6 ssat16 (argument parse). */
09d92015
MM
7976
7977static void
c19d1205 7978do_ssat16 (void)
09d92015 7979{
c19d1205
ZW
7980 inst.instruction |= inst.operands[0].reg << 12;
7981 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
7982 inst.instruction |= inst.operands[2].reg;
09d92015
MM
7983}
7984
c19d1205
ZW
7985static void
7986do_usat16 (void)
a737bd4d 7987{
c19d1205
ZW
7988 inst.instruction |= inst.operands[0].reg << 12;
7989 inst.instruction |= inst.operands[1].imm << 16;
7990 inst.instruction |= inst.operands[2].reg;
7991}
a737bd4d 7992
c19d1205
ZW
7993/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7994 preserving the other bits.
a737bd4d 7995
c19d1205
ZW
7996 setend <endian_specifier>, where <endian_specifier> is either
7997 BE or LE. */
a737bd4d 7998
c19d1205
ZW
7999static void
8000do_setend (void)
8001{
8002 if (inst.operands[0].imm)
8003 inst.instruction |= 0x200;
a737bd4d
NC
8004}
8005
8006static void
c19d1205 8007do_shift (void)
a737bd4d 8008{
c19d1205
ZW
8009 unsigned int Rm = (inst.operands[1].present
8010 ? inst.operands[1].reg
8011 : inst.operands[0].reg);
a737bd4d 8012
c19d1205
ZW
8013 inst.instruction |= inst.operands[0].reg << 12;
8014 inst.instruction |= Rm;
8015 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
a737bd4d 8016 {
c19d1205
ZW
8017 inst.instruction |= inst.operands[2].reg << 8;
8018 inst.instruction |= SHIFT_BY_REG;
a737bd4d
NC
8019 }
8020 else
c19d1205 8021 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
a737bd4d
NC
8022}
8023
09d92015 8024static void
3eb17e6b 8025do_smc (void)
09d92015 8026{
3eb17e6b 8027 inst.reloc.type = BFD_RELOC_ARM_SMC;
c19d1205 8028 inst.reloc.pc_rel = 0;
09d92015
MM
8029}
8030
09d92015 8031static void
c19d1205 8032do_swi (void)
09d92015 8033{
c19d1205
ZW
8034 inst.reloc.type = BFD_RELOC_ARM_SWI;
8035 inst.reloc.pc_rel = 0;
09d92015
MM
8036}
8037
c19d1205
ZW
8038/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8039 SMLAxy{cond} Rd,Rm,Rs,Rn
8040 SMLAWy{cond} Rd,Rm,Rs,Rn
8041 Error if any register is R15. */
e16bb312 8042
c19d1205
ZW
8043static void
8044do_smla (void)
e16bb312 8045{
c19d1205
ZW
8046 inst.instruction |= inst.operands[0].reg << 16;
8047 inst.instruction |= inst.operands[1].reg;
8048 inst.instruction |= inst.operands[2].reg << 8;
8049 inst.instruction |= inst.operands[3].reg << 12;
8050}
a737bd4d 8051
c19d1205
ZW
8052/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8053 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8054 Error if any register is R15.
8055 Warning if Rdlo == Rdhi. */
a737bd4d 8056
c19d1205
ZW
8057static void
8058do_smlal (void)
8059{
8060 inst.instruction |= inst.operands[0].reg << 12;
8061 inst.instruction |= inst.operands[1].reg << 16;
8062 inst.instruction |= inst.operands[2].reg;
8063 inst.instruction |= inst.operands[3].reg << 8;
a737bd4d 8064
c19d1205
ZW
8065 if (inst.operands[0].reg == inst.operands[1].reg)
8066 as_tsktsk (_("rdhi and rdlo must be different"));
8067}
a737bd4d 8068
c19d1205
ZW
8069/* ARM V5E (El Segundo) signed-multiply (argument parse)
8070 SMULxy{cond} Rd,Rm,Rs
8071 Error if any register is R15. */
a737bd4d 8072
c19d1205
ZW
8073static void
8074do_smul (void)
8075{
8076 inst.instruction |= inst.operands[0].reg << 16;
8077 inst.instruction |= inst.operands[1].reg;
8078 inst.instruction |= inst.operands[2].reg << 8;
8079}
a737bd4d 8080
b6702015
PB
8081/* ARM V6 srs (argument parse). The variable fields in the encoding are
8082 the same for both ARM and Thumb-2. */
a737bd4d 8083
c19d1205
ZW
8084static void
8085do_srs (void)
8086{
b6702015
PB
8087 int reg;
8088
8089 if (inst.operands[0].present)
8090 {
8091 reg = inst.operands[0].reg;
fdfde340 8092 constraint (reg != REG_SP, _("SRS base register must be r13"));
b6702015
PB
8093 }
8094 else
fdfde340 8095 reg = REG_SP;
b6702015
PB
8096
8097 inst.instruction |= reg << 16;
8098 inst.instruction |= inst.operands[1].imm;
8099 if (inst.operands[0].writeback || inst.operands[1].writeback)
c19d1205
ZW
8100 inst.instruction |= WRITE_BACK;
8101}
a737bd4d 8102
c19d1205 8103/* ARM V6 strex (argument parse). */
a737bd4d 8104
c19d1205
ZW
8105static void
8106do_strex (void)
8107{
8108 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8109 || inst.operands[2].postind || inst.operands[2].writeback
8110 || inst.operands[2].immisreg || inst.operands[2].shifted
01cfc07f
NC
8111 || inst.operands[2].negative
8112 /* See comment in do_ldrex(). */
8113 || (inst.operands[2].reg == REG_PC),
8114 BAD_ADDR_MODE);
a737bd4d 8115
c19d1205
ZW
8116 constraint (inst.operands[0].reg == inst.operands[1].reg
8117 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
a737bd4d 8118
c19d1205
ZW
8119 constraint (inst.reloc.exp.X_op != O_constant
8120 || inst.reloc.exp.X_add_number != 0,
8121 _("offset must be zero in ARM encoding"));
a737bd4d 8122
c19d1205
ZW
8123 inst.instruction |= inst.operands[0].reg << 12;
8124 inst.instruction |= inst.operands[1].reg;
8125 inst.instruction |= inst.operands[2].reg << 16;
8126 inst.reloc.type = BFD_RELOC_UNUSED;
e16bb312
NC
8127}
8128
8129static void
c19d1205 8130do_strexd (void)
e16bb312 8131{
c19d1205
ZW
8132 constraint (inst.operands[1].reg % 2 != 0,
8133 _("even register required"));
8134 constraint (inst.operands[2].present
8135 && inst.operands[2].reg != inst.operands[1].reg + 1,
8136 _("can only store two consecutive registers"));
8137 /* If op 2 were present and equal to PC, this function wouldn't
8138 have been called in the first place. */
8139 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
e16bb312 8140
c19d1205
ZW
8141 constraint (inst.operands[0].reg == inst.operands[1].reg
8142 || inst.operands[0].reg == inst.operands[1].reg + 1
8143 || inst.operands[0].reg == inst.operands[3].reg,
8144 BAD_OVERLAP);
e16bb312 8145
c19d1205
ZW
8146 inst.instruction |= inst.operands[0].reg << 12;
8147 inst.instruction |= inst.operands[1].reg;
8148 inst.instruction |= inst.operands[3].reg << 16;
e16bb312
NC
8149}
8150
c19d1205
ZW
8151/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8152 extends it to 32-bits, and adds the result to a value in another
8153 register. You can specify a rotation by 0, 8, 16, or 24 bits
8154 before extracting the 16-bit value.
8155 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8156 Condition defaults to COND_ALWAYS.
8157 Error if any register uses R15. */
8158
e16bb312 8159static void
c19d1205 8160do_sxtah (void)
e16bb312 8161{
c19d1205
ZW
8162 inst.instruction |= inst.operands[0].reg << 12;
8163 inst.instruction |= inst.operands[1].reg << 16;
8164 inst.instruction |= inst.operands[2].reg;
8165 inst.instruction |= inst.operands[3].imm << 10;
8166}
e16bb312 8167
c19d1205 8168/* ARM V6 SXTH.
e16bb312 8169
c19d1205
ZW
8170 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8171 Condition defaults to COND_ALWAYS.
8172 Error if any register uses R15. */
e16bb312
NC
8173
8174static void
c19d1205 8175do_sxth (void)
e16bb312 8176{
c19d1205
ZW
8177 inst.instruction |= inst.operands[0].reg << 12;
8178 inst.instruction |= inst.operands[1].reg;
8179 inst.instruction |= inst.operands[2].imm << 10;
e16bb312 8180}
c19d1205
ZW
8181\f
8182/* VFP instructions. In a logical order: SP variant first, monad
8183 before dyad, arithmetic then move then load/store. */
e16bb312
NC
8184
8185static void
c19d1205 8186do_vfp_sp_monadic (void)
e16bb312 8187{
5287ad62
JB
8188 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8189 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC
8190}
8191
8192static void
c19d1205 8193do_vfp_sp_dyadic (void)
e16bb312 8194{
5287ad62
JB
8195 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8196 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8197 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC
8198}
8199
8200static void
c19d1205 8201do_vfp_sp_compare_z (void)
e16bb312 8202{
5287ad62 8203 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
e16bb312
NC
8204}
8205
8206static void
c19d1205 8207do_vfp_dp_sp_cvt (void)
e16bb312 8208{
5287ad62
JB
8209 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8210 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC
8211}
8212
8213static void
c19d1205 8214do_vfp_sp_dp_cvt (void)
e16bb312 8215{
5287ad62
JB
8216 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8217 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
e16bb312
NC
8218}
8219
8220static void
c19d1205 8221do_vfp_reg_from_sp (void)
e16bb312 8222{
c19d1205 8223 inst.instruction |= inst.operands[0].reg << 12;
5287ad62 8224 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
e16bb312
NC
8225}
8226
8227static void
c19d1205 8228do_vfp_reg2_from_sp2 (void)
e16bb312 8229{
c19d1205
ZW
8230 constraint (inst.operands[2].imm != 2,
8231 _("only two consecutive VFP SP registers allowed here"));
8232 inst.instruction |= inst.operands[0].reg << 12;
8233 inst.instruction |= inst.operands[1].reg << 16;
5287ad62 8234 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC
8235}
8236
8237static void
c19d1205 8238do_vfp_sp_from_reg (void)
e16bb312 8239{
5287ad62 8240 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
c19d1205 8241 inst.instruction |= inst.operands[1].reg << 12;
e16bb312
NC
8242}
8243
8244static void
c19d1205 8245do_vfp_sp2_from_reg2 (void)
e16bb312 8246{
c19d1205
ZW
8247 constraint (inst.operands[0].imm != 2,
8248 _("only two consecutive VFP SP registers allowed here"));
5287ad62 8249 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
c19d1205
ZW
8250 inst.instruction |= inst.operands[1].reg << 12;
8251 inst.instruction |= inst.operands[2].reg << 16;
e16bb312
NC
8252}
8253
8254static void
c19d1205 8255do_vfp_sp_ldst (void)
e16bb312 8256{
5287ad62 8257 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
c19d1205 8258 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC
8259}
8260
8261static void
c19d1205 8262do_vfp_dp_ldst (void)
e16bb312 8263{
5287ad62 8264 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
c19d1205 8265 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC
8266}
8267
c19d1205 8268
e16bb312 8269static void
c19d1205 8270vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 8271{
c19d1205
ZW
8272 if (inst.operands[0].writeback)
8273 inst.instruction |= WRITE_BACK;
8274 else
8275 constraint (ldstm_type != VFP_LDSTMIA,
8276 _("this addressing mode requires base-register writeback"));
8277 inst.instruction |= inst.operands[0].reg << 16;
5287ad62 8278 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
c19d1205 8279 inst.instruction |= inst.operands[1].imm;
e16bb312
NC
8280}
8281
8282static void
c19d1205 8283vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 8284{
c19d1205 8285 int count;
e16bb312 8286
c19d1205
ZW
8287 if (inst.operands[0].writeback)
8288 inst.instruction |= WRITE_BACK;
8289 else
8290 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8291 _("this addressing mode requires base-register writeback"));
e16bb312 8292
c19d1205 8293 inst.instruction |= inst.operands[0].reg << 16;
5287ad62 8294 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
e16bb312 8295
c19d1205
ZW
8296 count = inst.operands[1].imm << 1;
8297 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8298 count += 1;
e16bb312 8299
c19d1205 8300 inst.instruction |= count;
e16bb312
NC
8301}
8302
8303static void
c19d1205 8304do_vfp_sp_ldstmia (void)
e16bb312 8305{
c19d1205 8306 vfp_sp_ldstm (VFP_LDSTMIA);
e16bb312
NC
8307}
8308
8309static void
c19d1205 8310do_vfp_sp_ldstmdb (void)
e16bb312 8311{
c19d1205 8312 vfp_sp_ldstm (VFP_LDSTMDB);
e16bb312
NC
8313}
8314
8315static void
c19d1205 8316do_vfp_dp_ldstmia (void)
e16bb312 8317{
c19d1205 8318 vfp_dp_ldstm (VFP_LDSTMIA);
e16bb312
NC
8319}
8320
8321static void
c19d1205 8322do_vfp_dp_ldstmdb (void)
e16bb312 8323{
c19d1205 8324 vfp_dp_ldstm (VFP_LDSTMDB);
e16bb312
NC
8325}
8326
8327static void
c19d1205 8328do_vfp_xp_ldstmia (void)
e16bb312 8329{
c19d1205
ZW
8330 vfp_dp_ldstm (VFP_LDSTMIAX);
8331}
e16bb312 8332
c19d1205
ZW
8333static void
8334do_vfp_xp_ldstmdb (void)
8335{
8336 vfp_dp_ldstm (VFP_LDSTMDBX);
e16bb312 8337}
5287ad62
JB
8338
8339static void
8340do_vfp_dp_rd_rm (void)
8341{
8342 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8343 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8344}
8345
8346static void
8347do_vfp_dp_rn_rd (void)
8348{
8349 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8350 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8351}
8352
8353static void
8354do_vfp_dp_rd_rn (void)
8355{
8356 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8357 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8358}
8359
8360static void
8361do_vfp_dp_rd_rn_rm (void)
8362{
8363 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8364 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8365 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8366}
8367
8368static void
8369do_vfp_dp_rd (void)
8370{
8371 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8372}
8373
8374static void
8375do_vfp_dp_rm_rd_rn (void)
8376{
8377 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8378 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8379 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8380}
8381
8382/* VFPv3 instructions. */
8383static void
8384do_vfp_sp_const (void)
8385{
8386 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
00249aaa
PB
8387 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8388 inst.instruction |= (inst.operands[1].imm & 0x0f);
5287ad62
JB
8389}
8390
8391static void
8392do_vfp_dp_const (void)
8393{
8394 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
00249aaa
PB
8395 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8396 inst.instruction |= (inst.operands[1].imm & 0x0f);
5287ad62
JB
8397}
8398
8399static void
8400vfp_conv (int srcsize)
8401{
8402 unsigned immbits = srcsize - inst.operands[1].imm;
8403 inst.instruction |= (immbits & 1) << 5;
8404 inst.instruction |= (immbits >> 1);
8405}
8406
8407static void
8408do_vfp_sp_conv_16 (void)
8409{
8410 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8411 vfp_conv (16);
8412}
8413
8414static void
8415do_vfp_dp_conv_16 (void)
8416{
8417 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8418 vfp_conv (16);
8419}
8420
8421static void
8422do_vfp_sp_conv_32 (void)
8423{
8424 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8425 vfp_conv (32);
8426}
8427
8428static void
8429do_vfp_dp_conv_32 (void)
8430{
8431 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8432 vfp_conv (32);
8433}
c19d1205
ZW
8434\f
8435/* FPA instructions. Also in a logical order. */
e16bb312 8436
c19d1205
ZW
8437static void
8438do_fpa_cmp (void)
8439{
8440 inst.instruction |= inst.operands[0].reg << 16;
8441 inst.instruction |= inst.operands[1].reg;
8442}
b99bd4ef
NC
8443
8444static void
c19d1205 8445do_fpa_ldmstm (void)
b99bd4ef 8446{
c19d1205
ZW
8447 inst.instruction |= inst.operands[0].reg << 12;
8448 switch (inst.operands[1].imm)
8449 {
8450 case 1: inst.instruction |= CP_T_X; break;
8451 case 2: inst.instruction |= CP_T_Y; break;
8452 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
8453 case 4: break;
8454 default: abort ();
8455 }
b99bd4ef 8456
c19d1205
ZW
8457 if (inst.instruction & (PRE_INDEX | INDEX_UP))
8458 {
8459 /* The instruction specified "ea" or "fd", so we can only accept
8460 [Rn]{!}. The instruction does not really support stacking or
8461 unstacking, so we have to emulate these by setting appropriate
8462 bits and offsets. */
8463 constraint (inst.reloc.exp.X_op != O_constant
8464 || inst.reloc.exp.X_add_number != 0,
8465 _("this instruction does not support indexing"));
b99bd4ef 8466
c19d1205
ZW
8467 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
8468 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
b99bd4ef 8469
c19d1205
ZW
8470 if (!(inst.instruction & INDEX_UP))
8471 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
b99bd4ef 8472
c19d1205
ZW
8473 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
8474 {
8475 inst.operands[2].preind = 0;
8476 inst.operands[2].postind = 1;
8477 }
8478 }
b99bd4ef 8479
c19d1205 8480 encode_arm_cp_address (2, TRUE, TRUE, 0);
b99bd4ef 8481}
c19d1205
ZW
8482\f
8483/* iWMMXt instructions: strictly in alphabetical order. */
b99bd4ef 8484
c19d1205
ZW
8485static void
8486do_iwmmxt_tandorc (void)
8487{
8488 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
8489}
b99bd4ef 8490
c19d1205
ZW
8491static void
8492do_iwmmxt_textrc (void)
8493{
8494 inst.instruction |= inst.operands[0].reg << 12;
8495 inst.instruction |= inst.operands[1].imm;
8496}
b99bd4ef
NC
8497
8498static void
c19d1205 8499do_iwmmxt_textrm (void)
b99bd4ef 8500{
c19d1205
ZW
8501 inst.instruction |= inst.operands[0].reg << 12;
8502 inst.instruction |= inst.operands[1].reg << 16;
8503 inst.instruction |= inst.operands[2].imm;
8504}
b99bd4ef 8505
c19d1205
ZW
8506static void
8507do_iwmmxt_tinsr (void)
8508{
8509 inst.instruction |= inst.operands[0].reg << 16;
8510 inst.instruction |= inst.operands[1].reg << 12;
8511 inst.instruction |= inst.operands[2].imm;
8512}
b99bd4ef 8513
c19d1205
ZW
8514static void
8515do_iwmmxt_tmia (void)
8516{
8517 inst.instruction |= inst.operands[0].reg << 5;
8518 inst.instruction |= inst.operands[1].reg;
8519 inst.instruction |= inst.operands[2].reg << 12;
8520}
b99bd4ef 8521
c19d1205
ZW
8522static void
8523do_iwmmxt_waligni (void)
8524{
8525 inst.instruction |= inst.operands[0].reg << 12;
8526 inst.instruction |= inst.operands[1].reg << 16;
8527 inst.instruction |= inst.operands[2].reg;
8528 inst.instruction |= inst.operands[3].imm << 20;
8529}
b99bd4ef 8530
2d447fca
JM
8531static void
8532do_iwmmxt_wmerge (void)
8533{
8534 inst.instruction |= inst.operands[0].reg << 12;
8535 inst.instruction |= inst.operands[1].reg << 16;
8536 inst.instruction |= inst.operands[2].reg;
8537 inst.instruction |= inst.operands[3].imm << 21;
8538}
8539
c19d1205
ZW
8540static void
8541do_iwmmxt_wmov (void)
8542{
8543 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8544 inst.instruction |= inst.operands[0].reg << 12;
8545 inst.instruction |= inst.operands[1].reg << 16;
8546 inst.instruction |= inst.operands[1].reg;
8547}
b99bd4ef 8548
c19d1205
ZW
8549static void
8550do_iwmmxt_wldstbh (void)
8551{
8f06b2d8 8552 int reloc;
c19d1205 8553 inst.instruction |= inst.operands[0].reg << 12;
8f06b2d8
PB
8554 if (thumb_mode)
8555 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
8556 else
8557 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
8558 encode_arm_cp_address (1, TRUE, FALSE, reloc);
b99bd4ef
NC
8559}
8560
c19d1205
ZW
8561static void
8562do_iwmmxt_wldstw (void)
8563{
8564 /* RIWR_RIWC clears .isreg for a control register. */
8565 if (!inst.operands[0].isreg)
8566 {
8567 constraint (inst.cond != COND_ALWAYS, BAD_COND);
8568 inst.instruction |= 0xf0000000;
8569 }
b99bd4ef 8570
c19d1205
ZW
8571 inst.instruction |= inst.operands[0].reg << 12;
8572 encode_arm_cp_address (1, TRUE, TRUE, 0);
8573}
b99bd4ef
NC
8574
8575static void
c19d1205 8576do_iwmmxt_wldstd (void)
b99bd4ef 8577{
c19d1205 8578 inst.instruction |= inst.operands[0].reg << 12;
2d447fca
JM
8579 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
8580 && inst.operands[1].immisreg)
8581 {
8582 inst.instruction &= ~0x1a000ff;
8583 inst.instruction |= (0xf << 28);
8584 if (inst.operands[1].preind)
8585 inst.instruction |= PRE_INDEX;
8586 if (!inst.operands[1].negative)
8587 inst.instruction |= INDEX_UP;
8588 if (inst.operands[1].writeback)
8589 inst.instruction |= WRITE_BACK;
8590 inst.instruction |= inst.operands[1].reg << 16;
8591 inst.instruction |= inst.reloc.exp.X_add_number << 4;
8592 inst.instruction |= inst.operands[1].imm;
8593 }
8594 else
8595 encode_arm_cp_address (1, TRUE, FALSE, 0);
c19d1205 8596}
b99bd4ef 8597
c19d1205
ZW
8598static void
8599do_iwmmxt_wshufh (void)
8600{
8601 inst.instruction |= inst.operands[0].reg << 12;
8602 inst.instruction |= inst.operands[1].reg << 16;
8603 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
8604 inst.instruction |= (inst.operands[2].imm & 0x0f);
8605}
b99bd4ef 8606
c19d1205
ZW
8607static void
8608do_iwmmxt_wzero (void)
8609{
8610 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8611 inst.instruction |= inst.operands[0].reg;
8612 inst.instruction |= inst.operands[0].reg << 12;
8613 inst.instruction |= inst.operands[0].reg << 16;
8614}
2d447fca
JM
8615
8616static void
8617do_iwmmxt_wrwrwr_or_imm5 (void)
8618{
8619 if (inst.operands[2].isreg)
8620 do_rd_rn_rm ();
8621 else {
8622 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
8623 _("immediate operand requires iWMMXt2"));
8624 do_rd_rn ();
8625 if (inst.operands[2].imm == 0)
8626 {
8627 switch ((inst.instruction >> 20) & 0xf)
8628 {
8629 case 4:
8630 case 5:
8631 case 6:
5f4273c7 8632 case 7:
2d447fca
JM
8633 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8634 inst.operands[2].imm = 16;
8635 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
8636 break;
8637 case 8:
8638 case 9:
8639 case 10:
8640 case 11:
8641 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8642 inst.operands[2].imm = 32;
8643 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
8644 break;
8645 case 12:
8646 case 13:
8647 case 14:
8648 case 15:
8649 {
8650 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8651 unsigned long wrn;
8652 wrn = (inst.instruction >> 16) & 0xf;
8653 inst.instruction &= 0xff0fff0f;
8654 inst.instruction |= wrn;
8655 /* Bail out here; the instruction is now assembled. */
8656 return;
8657 }
8658 }
8659 }
8660 /* Map 32 -> 0, etc. */
8661 inst.operands[2].imm &= 0x1f;
8662 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
8663 }
8664}
c19d1205
ZW
8665\f
8666/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8667 operations first, then control, shift, and load/store. */
b99bd4ef 8668
c19d1205 8669/* Insns like "foo X,Y,Z". */
b99bd4ef 8670
c19d1205
ZW
8671static void
8672do_mav_triple (void)
8673{
8674 inst.instruction |= inst.operands[0].reg << 16;
8675 inst.instruction |= inst.operands[1].reg;
8676 inst.instruction |= inst.operands[2].reg << 12;
8677}
b99bd4ef 8678
c19d1205
ZW
8679/* Insns like "foo W,X,Y,Z".
8680 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
a737bd4d 8681
c19d1205
ZW
8682static void
8683do_mav_quad (void)
8684{
8685 inst.instruction |= inst.operands[0].reg << 5;
8686 inst.instruction |= inst.operands[1].reg << 12;
8687 inst.instruction |= inst.operands[2].reg << 16;
8688 inst.instruction |= inst.operands[3].reg;
a737bd4d
NC
8689}
8690
c19d1205
ZW
8691/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8692static void
8693do_mav_dspsc (void)
a737bd4d 8694{
c19d1205
ZW
8695 inst.instruction |= inst.operands[1].reg << 12;
8696}
a737bd4d 8697
c19d1205
ZW
8698/* Maverick shift immediate instructions.
8699 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8700 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
a737bd4d 8701
c19d1205
ZW
8702static void
8703do_mav_shift (void)
8704{
8705 int imm = inst.operands[2].imm;
a737bd4d 8706
c19d1205
ZW
8707 inst.instruction |= inst.operands[0].reg << 12;
8708 inst.instruction |= inst.operands[1].reg << 16;
a737bd4d 8709
c19d1205
ZW
8710 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8711 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8712 Bit 4 should be 0. */
8713 imm = (imm & 0xf) | ((imm & 0x70) << 1);
a737bd4d 8714
c19d1205
ZW
8715 inst.instruction |= imm;
8716}
8717\f
8718/* XScale instructions. Also sorted arithmetic before move. */
a737bd4d 8719
c19d1205
ZW
8720/* Xscale multiply-accumulate (argument parse)
8721 MIAcc acc0,Rm,Rs
8722 MIAPHcc acc0,Rm,Rs
8723 MIAxycc acc0,Rm,Rs. */
a737bd4d 8724
c19d1205
ZW
8725static void
8726do_xsc_mia (void)
8727{
8728 inst.instruction |= inst.operands[1].reg;
8729 inst.instruction |= inst.operands[2].reg << 12;
8730}
a737bd4d 8731
c19d1205 8732/* Xscale move-accumulator-register (argument parse)
a737bd4d 8733
c19d1205 8734 MARcc acc0,RdLo,RdHi. */
b99bd4ef 8735
c19d1205
ZW
8736static void
8737do_xsc_mar (void)
8738{
8739 inst.instruction |= inst.operands[1].reg << 12;
8740 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC
8741}
8742
c19d1205 8743/* Xscale move-register-accumulator (argument parse)
b99bd4ef 8744
c19d1205 8745 MRAcc RdLo,RdHi,acc0. */
b99bd4ef
NC
8746
8747static void
c19d1205 8748do_xsc_mra (void)
b99bd4ef 8749{
c19d1205
ZW
8750 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
8751 inst.instruction |= inst.operands[0].reg << 12;
8752 inst.instruction |= inst.operands[1].reg << 16;
8753}
8754\f
8755/* Encoding functions relevant only to Thumb. */
b99bd4ef 8756
c19d1205
ZW
8757/* inst.operands[i] is a shifted-register operand; encode
8758 it into inst.instruction in the format used by Thumb32. */
8759
8760static void
8761encode_thumb32_shifted_operand (int i)
8762{
8763 unsigned int value = inst.reloc.exp.X_add_number;
8764 unsigned int shift = inst.operands[i].shift_kind;
b99bd4ef 8765
9c3c69f2
PB
8766 constraint (inst.operands[i].immisreg,
8767 _("shift by register not allowed in thumb mode"));
c19d1205
ZW
8768 inst.instruction |= inst.operands[i].reg;
8769 if (shift == SHIFT_RRX)
8770 inst.instruction |= SHIFT_ROR << 4;
8771 else
b99bd4ef 8772 {
c19d1205
ZW
8773 constraint (inst.reloc.exp.X_op != O_constant,
8774 _("expression too complex"));
8775
8776 constraint (value > 32
8777 || (value == 32 && (shift == SHIFT_LSL
8778 || shift == SHIFT_ROR)),
8779 _("shift expression is too large"));
8780
8781 if (value == 0)
8782 shift = SHIFT_LSL;
8783 else if (value == 32)
8784 value = 0;
8785
8786 inst.instruction |= shift << 4;
8787 inst.instruction |= (value & 0x1c) << 10;
8788 inst.instruction |= (value & 0x03) << 6;
b99bd4ef 8789 }
c19d1205 8790}
b99bd4ef 8791
b99bd4ef 8792
c19d1205
ZW
8793/* inst.operands[i] was set up by parse_address. Encode it into a
8794 Thumb32 format load or store instruction. Reject forms that cannot
8795 be used with such instructions. If is_t is true, reject forms that
8796 cannot be used with a T instruction; if is_d is true, reject forms
5be8be5d
DG
8797 that cannot be used with a D instruction. If it is a store insn,
8798 reject PC in Rn. */
b99bd4ef 8799
c19d1205
ZW
8800static void
8801encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
8802{
5be8be5d 8803 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
c19d1205
ZW
8804
8805 constraint (!inst.operands[i].isreg,
53365c0d 8806 _("Instruction does not support =N addresses"));
b99bd4ef 8807
c19d1205
ZW
8808 inst.instruction |= inst.operands[i].reg << 16;
8809 if (inst.operands[i].immisreg)
b99bd4ef 8810 {
5be8be5d 8811 constraint (is_pc, BAD_PC_ADDRESSING);
c19d1205
ZW
8812 constraint (is_t || is_d, _("cannot use register index with this instruction"));
8813 constraint (inst.operands[i].negative,
8814 _("Thumb does not support negative register indexing"));
8815 constraint (inst.operands[i].postind,
8816 _("Thumb does not support register post-indexing"));
8817 constraint (inst.operands[i].writeback,
8818 _("Thumb does not support register indexing with writeback"));
8819 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
8820 _("Thumb supports only LSL in shifted register indexing"));
b99bd4ef 8821
f40d1643 8822 inst.instruction |= inst.operands[i].imm;
c19d1205 8823 if (inst.operands[i].shifted)
b99bd4ef 8824 {
c19d1205
ZW
8825 constraint (inst.reloc.exp.X_op != O_constant,
8826 _("expression too complex"));
9c3c69f2
PB
8827 constraint (inst.reloc.exp.X_add_number < 0
8828 || inst.reloc.exp.X_add_number > 3,
c19d1205 8829 _("shift out of range"));
9c3c69f2 8830 inst.instruction |= inst.reloc.exp.X_add_number << 4;
c19d1205
ZW
8831 }
8832 inst.reloc.type = BFD_RELOC_UNUSED;
8833 }
8834 else if (inst.operands[i].preind)
8835 {
5be8be5d 8836 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
f40d1643 8837 constraint (is_t && inst.operands[i].writeback,
c19d1205 8838 _("cannot use writeback with this instruction"));
5be8be5d
DG
8839 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0)
8840 && !inst.reloc.pc_rel, BAD_PC_ADDRESSING);
c19d1205
ZW
8841
8842 if (is_d)
8843 {
8844 inst.instruction |= 0x01000000;
8845 if (inst.operands[i].writeback)
8846 inst.instruction |= 0x00200000;
b99bd4ef 8847 }
c19d1205 8848 else
b99bd4ef 8849 {
c19d1205
ZW
8850 inst.instruction |= 0x00000c00;
8851 if (inst.operands[i].writeback)
8852 inst.instruction |= 0x00000100;
b99bd4ef 8853 }
c19d1205 8854 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
b99bd4ef 8855 }
c19d1205 8856 else if (inst.operands[i].postind)
b99bd4ef 8857 {
9c2799c2 8858 gas_assert (inst.operands[i].writeback);
c19d1205
ZW
8859 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
8860 constraint (is_t, _("cannot use post-indexing with this instruction"));
8861
8862 if (is_d)
8863 inst.instruction |= 0x00200000;
8864 else
8865 inst.instruction |= 0x00000900;
8866 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
8867 }
8868 else /* unindexed - only for coprocessor */
8869 inst.error = _("instruction does not accept unindexed addressing");
8870}
8871
8872/* Table of Thumb instructions which exist in both 16- and 32-bit
8873 encodings (the latter only in post-V6T2 cores). The index is the
8874 value used in the insns table below. When there is more than one
8875 possible 16-bit encoding for the instruction, this table always
0110f2b8
PB
8876 holds variant (1).
8877 Also contains several pseudo-instructions used during relaxation. */
c19d1205 8878#define T16_32_TAB \
21d799b5
NC
8879 X(_adc, 4140, eb400000), \
8880 X(_adcs, 4140, eb500000), \
8881 X(_add, 1c00, eb000000), \
8882 X(_adds, 1c00, eb100000), \
8883 X(_addi, 0000, f1000000), \
8884 X(_addis, 0000, f1100000), \
8885 X(_add_pc,000f, f20f0000), \
8886 X(_add_sp,000d, f10d0000), \
8887 X(_adr, 000f, f20f0000), \
8888 X(_and, 4000, ea000000), \
8889 X(_ands, 4000, ea100000), \
8890 X(_asr, 1000, fa40f000), \
8891 X(_asrs, 1000, fa50f000), \
8892 X(_b, e000, f000b000), \
8893 X(_bcond, d000, f0008000), \
8894 X(_bic, 4380, ea200000), \
8895 X(_bics, 4380, ea300000), \
8896 X(_cmn, 42c0, eb100f00), \
8897 X(_cmp, 2800, ebb00f00), \
8898 X(_cpsie, b660, f3af8400), \
8899 X(_cpsid, b670, f3af8600), \
8900 X(_cpy, 4600, ea4f0000), \
8901 X(_dec_sp,80dd, f1ad0d00), \
8902 X(_eor, 4040, ea800000), \
8903 X(_eors, 4040, ea900000), \
8904 X(_inc_sp,00dd, f10d0d00), \
8905 X(_ldmia, c800, e8900000), \
8906 X(_ldr, 6800, f8500000), \
8907 X(_ldrb, 7800, f8100000), \
8908 X(_ldrh, 8800, f8300000), \
8909 X(_ldrsb, 5600, f9100000), \
8910 X(_ldrsh, 5e00, f9300000), \
8911 X(_ldr_pc,4800, f85f0000), \
8912 X(_ldr_pc2,4800, f85f0000), \
8913 X(_ldr_sp,9800, f85d0000), \
8914 X(_lsl, 0000, fa00f000), \
8915 X(_lsls, 0000, fa10f000), \
8916 X(_lsr, 0800, fa20f000), \
8917 X(_lsrs, 0800, fa30f000), \
8918 X(_mov, 2000, ea4f0000), \
8919 X(_movs, 2000, ea5f0000), \
8920 X(_mul, 4340, fb00f000), \
8921 X(_muls, 4340, ffffffff), /* no 32b muls */ \
8922 X(_mvn, 43c0, ea6f0000), \
8923 X(_mvns, 43c0, ea7f0000), \
8924 X(_neg, 4240, f1c00000), /* rsb #0 */ \
8925 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
8926 X(_orr, 4300, ea400000), \
8927 X(_orrs, 4300, ea500000), \
8928 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8929 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
8930 X(_rev, ba00, fa90f080), \
8931 X(_rev16, ba40, fa90f090), \
8932 X(_revsh, bac0, fa90f0b0), \
8933 X(_ror, 41c0, fa60f000), \
8934 X(_rors, 41c0, fa70f000), \
8935 X(_sbc, 4180, eb600000), \
8936 X(_sbcs, 4180, eb700000), \
8937 X(_stmia, c000, e8800000), \
8938 X(_str, 6000, f8400000), \
8939 X(_strb, 7000, f8000000), \
8940 X(_strh, 8000, f8200000), \
8941 X(_str_sp,9000, f84d0000), \
8942 X(_sub, 1e00, eba00000), \
8943 X(_subs, 1e00, ebb00000), \
8944 X(_subi, 8000, f1a00000), \
8945 X(_subis, 8000, f1b00000), \
8946 X(_sxtb, b240, fa4ff080), \
8947 X(_sxth, b200, fa0ff080), \
8948 X(_tst, 4200, ea100f00), \
8949 X(_uxtb, b2c0, fa5ff080), \
8950 X(_uxth, b280, fa1ff080), \
8951 X(_nop, bf00, f3af8000), \
8952 X(_yield, bf10, f3af8001), \
8953 X(_wfe, bf20, f3af8002), \
8954 X(_wfi, bf30, f3af8003), \
8955 X(_sev, bf40, f3af8004),
c19d1205
ZW
8956
8957/* To catch errors in encoding functions, the codes are all offset by
8958 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8959 as 16-bit instructions. */
21d799b5 8960#define X(a,b,c) T_MNEM##a
c19d1205
ZW
8961enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
8962#undef X
8963
8964#define X(a,b,c) 0x##b
8965static const unsigned short thumb_op16[] = { T16_32_TAB };
8966#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8967#undef X
8968
8969#define X(a,b,c) 0x##c
8970static const unsigned int thumb_op32[] = { T16_32_TAB };
c921be7d
NC
8971#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8972#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
c19d1205
ZW
8973#undef X
8974#undef T16_32_TAB
8975
8976/* Thumb instruction encoders, in alphabetical order. */
8977
92e90b6e 8978/* ADDW or SUBW. */
c921be7d 8979
92e90b6e
PB
8980static void
8981do_t_add_sub_w (void)
8982{
8983 int Rd, Rn;
8984
8985 Rd = inst.operands[0].reg;
8986 Rn = inst.operands[1].reg;
8987
539d4391
NC
8988 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
8989 is the SP-{plus,minus}-immediate form of the instruction. */
8990 if (Rn == REG_SP)
8991 constraint (Rd == REG_PC, BAD_PC);
8992 else
8993 reject_bad_reg (Rd);
fdfde340 8994
92e90b6e
PB
8995 inst.instruction |= (Rn << 16) | (Rd << 8);
8996 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
8997}
8998
c19d1205
ZW
8999/* Parse an add or subtract instruction. We get here with inst.instruction
9000 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9001
9002static void
9003do_t_add_sub (void)
9004{
9005 int Rd, Rs, Rn;
9006
9007 Rd = inst.operands[0].reg;
9008 Rs = (inst.operands[1].present
9009 ? inst.operands[1].reg /* Rd, Rs, foo */
9010 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9011
e07e6e58
NC
9012 if (Rd == REG_PC)
9013 set_it_insn_type_last ();
9014
c19d1205
ZW
9015 if (unified_syntax)
9016 {
0110f2b8
PB
9017 bfd_boolean flags;
9018 bfd_boolean narrow;
9019 int opcode;
9020
9021 flags = (inst.instruction == T_MNEM_adds
9022 || inst.instruction == T_MNEM_subs);
9023 if (flags)
e07e6e58 9024 narrow = !in_it_block ();
0110f2b8 9025 else
e07e6e58 9026 narrow = in_it_block ();
c19d1205 9027 if (!inst.operands[2].isreg)
b99bd4ef 9028 {
16805f35
PB
9029 int add;
9030
fdfde340
JM
9031 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9032
16805f35
PB
9033 add = (inst.instruction == T_MNEM_add
9034 || inst.instruction == T_MNEM_adds);
0110f2b8
PB
9035 opcode = 0;
9036 if (inst.size_req != 4)
9037 {
0110f2b8
PB
9038 /* Attempt to use a narrow opcode, with relaxation if
9039 appropriate. */
9040 if (Rd == REG_SP && Rs == REG_SP && !flags)
9041 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9042 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9043 opcode = T_MNEM_add_sp;
9044 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9045 opcode = T_MNEM_add_pc;
9046 else if (Rd <= 7 && Rs <= 7 && narrow)
9047 {
9048 if (flags)
9049 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9050 else
9051 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9052 }
9053 if (opcode)
9054 {
9055 inst.instruction = THUMB_OP16(opcode);
9056 inst.instruction |= (Rd << 4) | Rs;
9057 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9058 if (inst.size_req != 2)
9059 inst.relax = opcode;
9060 }
9061 else
9062 constraint (inst.size_req == 2, BAD_HIREG);
9063 }
9064 if (inst.size_req == 4
9065 || (inst.size_req != 2 && !opcode))
9066 {
efd81785
PB
9067 if (Rd == REG_PC)
9068 {
fdfde340 9069 constraint (add, BAD_PC);
efd81785
PB
9070 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9071 _("only SUBS PC, LR, #const allowed"));
9072 constraint (inst.reloc.exp.X_op != O_constant,
9073 _("expression too complex"));
9074 constraint (inst.reloc.exp.X_add_number < 0
9075 || inst.reloc.exp.X_add_number > 0xff,
9076 _("immediate value out of range"));
9077 inst.instruction = T2_SUBS_PC_LR
9078 | inst.reloc.exp.X_add_number;
9079 inst.reloc.type = BFD_RELOC_UNUSED;
9080 return;
9081 }
9082 else if (Rs == REG_PC)
16805f35
PB
9083 {
9084 /* Always use addw/subw. */
9085 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9086 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9087 }
9088 else
9089 {
9090 inst.instruction = THUMB_OP32 (inst.instruction);
9091 inst.instruction = (inst.instruction & 0xe1ffffff)
9092 | 0x10000000;
9093 if (flags)
9094 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9095 else
9096 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9097 }
dc4503c6
PB
9098 inst.instruction |= Rd << 8;
9099 inst.instruction |= Rs << 16;
0110f2b8 9100 }
b99bd4ef 9101 }
c19d1205
ZW
9102 else
9103 {
9104 Rn = inst.operands[2].reg;
9105 /* See if we can do this with a 16-bit instruction. */
9106 if (!inst.operands[2].shifted && inst.size_req != 4)
9107 {
e27ec89e
PB
9108 if (Rd > 7 || Rs > 7 || Rn > 7)
9109 narrow = FALSE;
9110
9111 if (narrow)
c19d1205 9112 {
e27ec89e
PB
9113 inst.instruction = ((inst.instruction == T_MNEM_adds
9114 || inst.instruction == T_MNEM_add)
c19d1205
ZW
9115 ? T_OPCODE_ADD_R3
9116 : T_OPCODE_SUB_R3);
9117 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9118 return;
9119 }
b99bd4ef 9120
7e806470 9121 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
c19d1205 9122 {
7e806470
PB
9123 /* Thumb-1 cores (except v6-M) require at least one high
9124 register in a narrow non flag setting add. */
9125 if (Rd > 7 || Rn > 7
9126 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9127 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
c19d1205 9128 {
7e806470
PB
9129 if (Rd == Rn)
9130 {
9131 Rn = Rs;
9132 Rs = Rd;
9133 }
c19d1205
ZW
9134 inst.instruction = T_OPCODE_ADD_HI;
9135 inst.instruction |= (Rd & 8) << 4;
9136 inst.instruction |= (Rd & 7);
9137 inst.instruction |= Rn << 3;
9138 return;
9139 }
c19d1205
ZW
9140 }
9141 }
c921be7d 9142
fdfde340
JM
9143 constraint (Rd == REG_PC, BAD_PC);
9144 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9145 constraint (Rs == REG_PC, BAD_PC);
9146 reject_bad_reg (Rn);
9147
c19d1205
ZW
9148 /* If we get here, it can't be done in 16 bits. */
9149 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9150 _("shift must be constant"));
9151 inst.instruction = THUMB_OP32 (inst.instruction);
9152 inst.instruction |= Rd << 8;
9153 inst.instruction |= Rs << 16;
9154 encode_thumb32_shifted_operand (2);
9155 }
9156 }
9157 else
9158 {
9159 constraint (inst.instruction == T_MNEM_adds
9160 || inst.instruction == T_MNEM_subs,
9161 BAD_THUMB32);
b99bd4ef 9162
c19d1205 9163 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
b99bd4ef 9164 {
c19d1205
ZW
9165 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9166 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9167 BAD_HIREG);
9168
9169 inst.instruction = (inst.instruction == T_MNEM_add
9170 ? 0x0000 : 0x8000);
9171 inst.instruction |= (Rd << 4) | Rs;
9172 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
b99bd4ef
NC
9173 return;
9174 }
9175
c19d1205
ZW
9176 Rn = inst.operands[2].reg;
9177 constraint (inst.operands[2].shifted, _("unshifted register required"));
b99bd4ef 9178
c19d1205
ZW
9179 /* We now have Rd, Rs, and Rn set to registers. */
9180 if (Rd > 7 || Rs > 7 || Rn > 7)
b99bd4ef 9181 {
c19d1205
ZW
9182 /* Can't do this for SUB. */
9183 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9184 inst.instruction = T_OPCODE_ADD_HI;
9185 inst.instruction |= (Rd & 8) << 4;
9186 inst.instruction |= (Rd & 7);
9187 if (Rs == Rd)
9188 inst.instruction |= Rn << 3;
9189 else if (Rn == Rd)
9190 inst.instruction |= Rs << 3;
9191 else
9192 constraint (1, _("dest must overlap one source register"));
9193 }
9194 else
9195 {
9196 inst.instruction = (inst.instruction == T_MNEM_add
9197 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9198 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
b99bd4ef 9199 }
b99bd4ef 9200 }
b99bd4ef
NC
9201}
9202
c19d1205
ZW
9203static void
9204do_t_adr (void)
9205{
fdfde340
JM
9206 unsigned Rd;
9207
9208 Rd = inst.operands[0].reg;
9209 reject_bad_reg (Rd);
9210
9211 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
0110f2b8
PB
9212 {
9213 /* Defer to section relaxation. */
9214 inst.relax = inst.instruction;
9215 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340 9216 inst.instruction |= Rd << 4;
0110f2b8
PB
9217 }
9218 else if (unified_syntax && inst.size_req != 2)
e9f89963 9219 {
0110f2b8 9220 /* Generate a 32-bit opcode. */
e9f89963 9221 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 9222 inst.instruction |= Rd << 8;
e9f89963
PB
9223 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9224 inst.reloc.pc_rel = 1;
9225 }
9226 else
9227 {
0110f2b8 9228 /* Generate a 16-bit opcode. */
e9f89963
PB
9229 inst.instruction = THUMB_OP16 (inst.instruction);
9230 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9231 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9232 inst.reloc.pc_rel = 1;
b99bd4ef 9233
fdfde340 9234 inst.instruction |= Rd << 4;
e9f89963 9235 }
c19d1205 9236}
b99bd4ef 9237
c19d1205
ZW
9238/* Arithmetic instructions for which there is just one 16-bit
9239 instruction encoding, and it allows only two low registers.
9240 For maximal compatibility with ARM syntax, we allow three register
9241 operands even when Thumb-32 instructions are not available, as long
9242 as the first two are identical. For instance, both "sbc r0,r1" and
9243 "sbc r0,r0,r1" are allowed. */
b99bd4ef 9244static void
c19d1205 9245do_t_arit3 (void)
b99bd4ef 9246{
c19d1205 9247 int Rd, Rs, Rn;
b99bd4ef 9248
c19d1205
ZW
9249 Rd = inst.operands[0].reg;
9250 Rs = (inst.operands[1].present
9251 ? inst.operands[1].reg /* Rd, Rs, foo */
9252 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9253 Rn = inst.operands[2].reg;
b99bd4ef 9254
fdfde340
JM
9255 reject_bad_reg (Rd);
9256 reject_bad_reg (Rs);
9257 if (inst.operands[2].isreg)
9258 reject_bad_reg (Rn);
9259
c19d1205 9260 if (unified_syntax)
b99bd4ef 9261 {
c19d1205
ZW
9262 if (!inst.operands[2].isreg)
9263 {
9264 /* For an immediate, we always generate a 32-bit opcode;
9265 section relaxation will shrink it later if possible. */
9266 inst.instruction = THUMB_OP32 (inst.instruction);
9267 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9268 inst.instruction |= Rd << 8;
9269 inst.instruction |= Rs << 16;
9270 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9271 }
9272 else
9273 {
e27ec89e
PB
9274 bfd_boolean narrow;
9275
c19d1205 9276 /* See if we can do this with a 16-bit instruction. */
e27ec89e 9277 if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 9278 narrow = !in_it_block ();
e27ec89e 9279 else
e07e6e58 9280 narrow = in_it_block ();
e27ec89e
PB
9281
9282 if (Rd > 7 || Rn > 7 || Rs > 7)
9283 narrow = FALSE;
9284 if (inst.operands[2].shifted)
9285 narrow = FALSE;
9286 if (inst.size_req == 4)
9287 narrow = FALSE;
9288
9289 if (narrow
c19d1205
ZW
9290 && Rd == Rs)
9291 {
9292 inst.instruction = THUMB_OP16 (inst.instruction);
9293 inst.instruction |= Rd;
9294 inst.instruction |= Rn << 3;
9295 return;
9296 }
b99bd4ef 9297
c19d1205
ZW
9298 /* If we get here, it can't be done in 16 bits. */
9299 constraint (inst.operands[2].shifted
9300 && inst.operands[2].immisreg,
9301 _("shift must be constant"));
9302 inst.instruction = THUMB_OP32 (inst.instruction);
9303 inst.instruction |= Rd << 8;
9304 inst.instruction |= Rs << 16;
9305 encode_thumb32_shifted_operand (2);
9306 }
a737bd4d 9307 }
c19d1205 9308 else
b99bd4ef 9309 {
c19d1205
ZW
9310 /* On its face this is a lie - the instruction does set the
9311 flags. However, the only supported mnemonic in this mode
9312 says it doesn't. */
9313 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 9314
c19d1205
ZW
9315 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9316 _("unshifted register required"));
9317 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9318 constraint (Rd != Rs,
9319 _("dest and source1 must be the same register"));
a737bd4d 9320
c19d1205
ZW
9321 inst.instruction = THUMB_OP16 (inst.instruction);
9322 inst.instruction |= Rd;
9323 inst.instruction |= Rn << 3;
b99bd4ef 9324 }
a737bd4d 9325}
b99bd4ef 9326
c19d1205
ZW
9327/* Similarly, but for instructions where the arithmetic operation is
9328 commutative, so we can allow either of them to be different from
9329 the destination operand in a 16-bit instruction. For instance, all
9330 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9331 accepted. */
9332static void
9333do_t_arit3c (void)
a737bd4d 9334{
c19d1205 9335 int Rd, Rs, Rn;
b99bd4ef 9336
c19d1205
ZW
9337 Rd = inst.operands[0].reg;
9338 Rs = (inst.operands[1].present
9339 ? inst.operands[1].reg /* Rd, Rs, foo */
9340 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9341 Rn = inst.operands[2].reg;
c921be7d 9342
fdfde340
JM
9343 reject_bad_reg (Rd);
9344 reject_bad_reg (Rs);
9345 if (inst.operands[2].isreg)
9346 reject_bad_reg (Rn);
a737bd4d 9347
c19d1205 9348 if (unified_syntax)
a737bd4d 9349 {
c19d1205 9350 if (!inst.operands[2].isreg)
b99bd4ef 9351 {
c19d1205
ZW
9352 /* For an immediate, we always generate a 32-bit opcode;
9353 section relaxation will shrink it later if possible. */
9354 inst.instruction = THUMB_OP32 (inst.instruction);
9355 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9356 inst.instruction |= Rd << 8;
9357 inst.instruction |= Rs << 16;
9358 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 9359 }
c19d1205 9360 else
a737bd4d 9361 {
e27ec89e
PB
9362 bfd_boolean narrow;
9363
c19d1205 9364 /* See if we can do this with a 16-bit instruction. */
e27ec89e 9365 if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 9366 narrow = !in_it_block ();
e27ec89e 9367 else
e07e6e58 9368 narrow = in_it_block ();
e27ec89e
PB
9369
9370 if (Rd > 7 || Rn > 7 || Rs > 7)
9371 narrow = FALSE;
9372 if (inst.operands[2].shifted)
9373 narrow = FALSE;
9374 if (inst.size_req == 4)
9375 narrow = FALSE;
9376
9377 if (narrow)
a737bd4d 9378 {
c19d1205 9379 if (Rd == Rs)
a737bd4d 9380 {
c19d1205
ZW
9381 inst.instruction = THUMB_OP16 (inst.instruction);
9382 inst.instruction |= Rd;
9383 inst.instruction |= Rn << 3;
9384 return;
a737bd4d 9385 }
c19d1205 9386 if (Rd == Rn)
a737bd4d 9387 {
c19d1205
ZW
9388 inst.instruction = THUMB_OP16 (inst.instruction);
9389 inst.instruction |= Rd;
9390 inst.instruction |= Rs << 3;
9391 return;
a737bd4d
NC
9392 }
9393 }
c19d1205
ZW
9394
9395 /* If we get here, it can't be done in 16 bits. */
9396 constraint (inst.operands[2].shifted
9397 && inst.operands[2].immisreg,
9398 _("shift must be constant"));
9399 inst.instruction = THUMB_OP32 (inst.instruction);
9400 inst.instruction |= Rd << 8;
9401 inst.instruction |= Rs << 16;
9402 encode_thumb32_shifted_operand (2);
a737bd4d 9403 }
b99bd4ef 9404 }
c19d1205
ZW
9405 else
9406 {
9407 /* On its face this is a lie - the instruction does set the
9408 flags. However, the only supported mnemonic in this mode
9409 says it doesn't. */
9410 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 9411
c19d1205
ZW
9412 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9413 _("unshifted register required"));
9414 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9415
9416 inst.instruction = THUMB_OP16 (inst.instruction);
9417 inst.instruction |= Rd;
9418
9419 if (Rd == Rs)
9420 inst.instruction |= Rn << 3;
9421 else if (Rd == Rn)
9422 inst.instruction |= Rs << 3;
9423 else
9424 constraint (1, _("dest must overlap one source register"));
9425 }
a737bd4d
NC
9426}
9427
62b3e311
PB
9428static void
9429do_t_barrier (void)
9430{
9431 if (inst.operands[0].present)
9432 {
9433 constraint ((inst.instruction & 0xf0) != 0x40
9434 && inst.operands[0].imm != 0xf,
bd3ba5d1 9435 _("bad barrier type"));
62b3e311
PB
9436 inst.instruction |= inst.operands[0].imm;
9437 }
9438 else
9439 inst.instruction |= 0xf;
9440}
9441
c19d1205
ZW
9442static void
9443do_t_bfc (void)
a737bd4d 9444{
fdfde340 9445 unsigned Rd;
c19d1205
ZW
9446 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9447 constraint (msb > 32, _("bit-field extends past end of register"));
9448 /* The instruction encoding stores the LSB and MSB,
9449 not the LSB and width. */
fdfde340
JM
9450 Rd = inst.operands[0].reg;
9451 reject_bad_reg (Rd);
9452 inst.instruction |= Rd << 8;
c19d1205
ZW
9453 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
9454 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
9455 inst.instruction |= msb - 1;
b99bd4ef
NC
9456}
9457
c19d1205
ZW
9458static void
9459do_t_bfi (void)
b99bd4ef 9460{
fdfde340 9461 int Rd, Rn;
c19d1205 9462 unsigned int msb;
b99bd4ef 9463
fdfde340
JM
9464 Rd = inst.operands[0].reg;
9465 reject_bad_reg (Rd);
9466
c19d1205
ZW
9467 /* #0 in second position is alternative syntax for bfc, which is
9468 the same instruction but with REG_PC in the Rm field. */
9469 if (!inst.operands[1].isreg)
fdfde340
JM
9470 Rn = REG_PC;
9471 else
9472 {
9473 Rn = inst.operands[1].reg;
9474 reject_bad_reg (Rn);
9475 }
b99bd4ef 9476
c19d1205
ZW
9477 msb = inst.operands[2].imm + inst.operands[3].imm;
9478 constraint (msb > 32, _("bit-field extends past end of register"));
9479 /* The instruction encoding stores the LSB and MSB,
9480 not the LSB and width. */
fdfde340
JM
9481 inst.instruction |= Rd << 8;
9482 inst.instruction |= Rn << 16;
c19d1205
ZW
9483 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9484 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9485 inst.instruction |= msb - 1;
b99bd4ef
NC
9486}
9487
c19d1205
ZW
9488static void
9489do_t_bfx (void)
b99bd4ef 9490{
fdfde340
JM
9491 unsigned Rd, Rn;
9492
9493 Rd = inst.operands[0].reg;
9494 Rn = inst.operands[1].reg;
9495
9496 reject_bad_reg (Rd);
9497 reject_bad_reg (Rn);
9498
c19d1205
ZW
9499 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9500 _("bit-field extends past end of register"));
fdfde340
JM
9501 inst.instruction |= Rd << 8;
9502 inst.instruction |= Rn << 16;
c19d1205
ZW
9503 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9504 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9505 inst.instruction |= inst.operands[3].imm - 1;
9506}
b99bd4ef 9507
c19d1205
ZW
9508/* ARM V5 Thumb BLX (argument parse)
9509 BLX <target_addr> which is BLX(1)
9510 BLX <Rm> which is BLX(2)
9511 Unfortunately, there are two different opcodes for this mnemonic.
9512 So, the insns[].value is not used, and the code here zaps values
9513 into inst.instruction.
b99bd4ef 9514
c19d1205
ZW
9515 ??? How to take advantage of the additional two bits of displacement
9516 available in Thumb32 mode? Need new relocation? */
b99bd4ef 9517
c19d1205
ZW
9518static void
9519do_t_blx (void)
9520{
e07e6e58
NC
9521 set_it_insn_type_last ();
9522
c19d1205 9523 if (inst.operands[0].isreg)
fdfde340
JM
9524 {
9525 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9526 /* We have a register, so this is BLX(2). */
9527 inst.instruction |= inst.operands[0].reg << 3;
9528 }
b99bd4ef
NC
9529 else
9530 {
c19d1205 9531 /* No register. This must be BLX(1). */
2fc8bdac 9532 inst.instruction = 0xf000e800;
00adf2d4 9533 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
c19d1205 9534 inst.reloc.pc_rel = 1;
b99bd4ef
NC
9535 }
9536}
9537
c19d1205
ZW
9538static void
9539do_t_branch (void)
b99bd4ef 9540{
0110f2b8 9541 int opcode;
dfa9f0d5
PB
9542 int cond;
9543
e07e6e58
NC
9544 cond = inst.cond;
9545 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
9546
9547 if (in_it_block ())
dfa9f0d5
PB
9548 {
9549 /* Conditional branches inside IT blocks are encoded as unconditional
9550 branches. */
9551 cond = COND_ALWAYS;
dfa9f0d5
PB
9552 }
9553 else
9554 cond = inst.cond;
9555
9556 if (cond != COND_ALWAYS)
0110f2b8
PB
9557 opcode = T_MNEM_bcond;
9558 else
9559 opcode = inst.instruction;
9560
9561 if (unified_syntax && inst.size_req == 4)
c19d1205 9562 {
0110f2b8 9563 inst.instruction = THUMB_OP32(opcode);
dfa9f0d5 9564 if (cond == COND_ALWAYS)
0110f2b8 9565 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
c19d1205
ZW
9566 else
9567 {
9c2799c2 9568 gas_assert (cond != 0xF);
dfa9f0d5 9569 inst.instruction |= cond << 22;
c19d1205
ZW
9570 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
9571 }
9572 }
b99bd4ef
NC
9573 else
9574 {
0110f2b8 9575 inst.instruction = THUMB_OP16(opcode);
dfa9f0d5 9576 if (cond == COND_ALWAYS)
c19d1205
ZW
9577 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
9578 else
b99bd4ef 9579 {
dfa9f0d5 9580 inst.instruction |= cond << 8;
c19d1205 9581 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
b99bd4ef 9582 }
0110f2b8
PB
9583 /* Allow section relaxation. */
9584 if (unified_syntax && inst.size_req != 2)
9585 inst.relax = opcode;
b99bd4ef 9586 }
c19d1205
ZW
9587
9588 inst.reloc.pc_rel = 1;
b99bd4ef
NC
9589}
9590
9591static void
c19d1205 9592do_t_bkpt (void)
b99bd4ef 9593{
dfa9f0d5
PB
9594 constraint (inst.cond != COND_ALWAYS,
9595 _("instruction is always unconditional"));
c19d1205 9596 if (inst.operands[0].present)
b99bd4ef 9597 {
c19d1205
ZW
9598 constraint (inst.operands[0].imm > 255,
9599 _("immediate value out of range"));
9600 inst.instruction |= inst.operands[0].imm;
e07e6e58 9601 set_it_insn_type (NEUTRAL_IT_INSN);
b99bd4ef 9602 }
b99bd4ef
NC
9603}
9604
9605static void
c19d1205 9606do_t_branch23 (void)
b99bd4ef 9607{
e07e6e58 9608 set_it_insn_type_last ();
c19d1205 9609 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
90e4755a
RE
9610 inst.reloc.pc_rel = 1;
9611
4343666d 9612#if defined(OBJ_COFF)
c19d1205
ZW
9613 /* If the destination of the branch is a defined symbol which does not have
9614 the THUMB_FUNC attribute, then we must be calling a function which has
9615 the (interfacearm) attribute. We look for the Thumb entry point to that
9616 function and change the branch to refer to that function instead. */
9617 if ( inst.reloc.exp.X_op == O_symbol
9618 && inst.reloc.exp.X_add_symbol != NULL
9619 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
9620 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
9621 inst.reloc.exp.X_add_symbol =
9622 find_real_start (inst.reloc.exp.X_add_symbol);
4343666d 9623#endif
90e4755a
RE
9624}
9625
9626static void
c19d1205 9627do_t_bx (void)
90e4755a 9628{
e07e6e58 9629 set_it_insn_type_last ();
c19d1205
ZW
9630 inst.instruction |= inst.operands[0].reg << 3;
9631 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9632 should cause the alignment to be checked once it is known. This is
9633 because BX PC only works if the instruction is word aligned. */
9634}
90e4755a 9635
c19d1205
ZW
9636static void
9637do_t_bxj (void)
9638{
fdfde340 9639 int Rm;
90e4755a 9640
e07e6e58 9641 set_it_insn_type_last ();
fdfde340
JM
9642 Rm = inst.operands[0].reg;
9643 reject_bad_reg (Rm);
9644 inst.instruction |= Rm << 16;
90e4755a
RE
9645}
9646
9647static void
c19d1205 9648do_t_clz (void)
90e4755a 9649{
fdfde340
JM
9650 unsigned Rd;
9651 unsigned Rm;
9652
9653 Rd = inst.operands[0].reg;
9654 Rm = inst.operands[1].reg;
9655
9656 reject_bad_reg (Rd);
9657 reject_bad_reg (Rm);
9658
9659 inst.instruction |= Rd << 8;
9660 inst.instruction |= Rm << 16;
9661 inst.instruction |= Rm;
c19d1205 9662}
90e4755a 9663
dfa9f0d5
PB
9664static void
9665do_t_cps (void)
9666{
e07e6e58 9667 set_it_insn_type (OUTSIDE_IT_INSN);
dfa9f0d5
PB
9668 inst.instruction |= inst.operands[0].imm;
9669}
9670
c19d1205
ZW
9671static void
9672do_t_cpsi (void)
9673{
e07e6e58 9674 set_it_insn_type (OUTSIDE_IT_INSN);
c19d1205 9675 if (unified_syntax
62b3e311
PB
9676 && (inst.operands[1].present || inst.size_req == 4)
9677 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
90e4755a 9678 {
c19d1205
ZW
9679 unsigned int imod = (inst.instruction & 0x0030) >> 4;
9680 inst.instruction = 0xf3af8000;
9681 inst.instruction |= imod << 9;
9682 inst.instruction |= inst.operands[0].imm << 5;
9683 if (inst.operands[1].present)
9684 inst.instruction |= 0x100 | inst.operands[1].imm;
90e4755a 9685 }
c19d1205 9686 else
90e4755a 9687 {
62b3e311
PB
9688 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
9689 && (inst.operands[0].imm & 4),
9690 _("selected processor does not support 'A' form "
9691 "of this instruction"));
9692 constraint (inst.operands[1].present || inst.size_req == 4,
c19d1205
ZW
9693 _("Thumb does not support the 2-argument "
9694 "form of this instruction"));
9695 inst.instruction |= inst.operands[0].imm;
90e4755a 9696 }
90e4755a
RE
9697}
9698
c19d1205
ZW
9699/* THUMB CPY instruction (argument parse). */
9700
90e4755a 9701static void
c19d1205 9702do_t_cpy (void)
90e4755a 9703{
c19d1205 9704 if (inst.size_req == 4)
90e4755a 9705 {
c19d1205
ZW
9706 inst.instruction = THUMB_OP32 (T_MNEM_mov);
9707 inst.instruction |= inst.operands[0].reg << 8;
9708 inst.instruction |= inst.operands[1].reg;
90e4755a 9709 }
c19d1205 9710 else
90e4755a 9711 {
c19d1205
ZW
9712 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9713 inst.instruction |= (inst.operands[0].reg & 0x7);
9714 inst.instruction |= inst.operands[1].reg << 3;
90e4755a 9715 }
90e4755a
RE
9716}
9717
90e4755a 9718static void
25fe350b 9719do_t_cbz (void)
90e4755a 9720{
e07e6e58 9721 set_it_insn_type (OUTSIDE_IT_INSN);
c19d1205
ZW
9722 constraint (inst.operands[0].reg > 7, BAD_HIREG);
9723 inst.instruction |= inst.operands[0].reg;
9724 inst.reloc.pc_rel = 1;
9725 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
9726}
90e4755a 9727
62b3e311
PB
9728static void
9729do_t_dbg (void)
9730{
9731 inst.instruction |= inst.operands[0].imm;
9732}
9733
9734static void
9735do_t_div (void)
9736{
fdfde340
JM
9737 unsigned Rd, Rn, Rm;
9738
9739 Rd = inst.operands[0].reg;
9740 Rn = (inst.operands[1].present
9741 ? inst.operands[1].reg : Rd);
9742 Rm = inst.operands[2].reg;
9743
9744 reject_bad_reg (Rd);
9745 reject_bad_reg (Rn);
9746 reject_bad_reg (Rm);
9747
9748 inst.instruction |= Rd << 8;
9749 inst.instruction |= Rn << 16;
9750 inst.instruction |= Rm;
62b3e311
PB
9751}
9752
c19d1205
ZW
9753static void
9754do_t_hint (void)
9755{
9756 if (unified_syntax && inst.size_req == 4)
9757 inst.instruction = THUMB_OP32 (inst.instruction);
9758 else
9759 inst.instruction = THUMB_OP16 (inst.instruction);
9760}
90e4755a 9761
c19d1205
ZW
9762static void
9763do_t_it (void)
9764{
9765 unsigned int cond = inst.operands[0].imm;
e27ec89e 9766
e07e6e58
NC
9767 set_it_insn_type (IT_INSN);
9768 now_it.mask = (inst.instruction & 0xf) | 0x10;
9769 now_it.cc = cond;
e27ec89e
PB
9770
9771 /* If the condition is a negative condition, invert the mask. */
c19d1205 9772 if ((cond & 0x1) == 0x0)
90e4755a 9773 {
c19d1205 9774 unsigned int mask = inst.instruction & 0x000f;
90e4755a 9775
c19d1205
ZW
9776 if ((mask & 0x7) == 0)
9777 /* no conversion needed */;
9778 else if ((mask & 0x3) == 0)
e27ec89e
PB
9779 mask ^= 0x8;
9780 else if ((mask & 0x1) == 0)
9781 mask ^= 0xC;
c19d1205 9782 else
e27ec89e 9783 mask ^= 0xE;
90e4755a 9784
e27ec89e
PB
9785 inst.instruction &= 0xfff0;
9786 inst.instruction |= mask;
c19d1205 9787 }
90e4755a 9788
c19d1205
ZW
9789 inst.instruction |= cond << 4;
9790}
90e4755a 9791
3c707909
PB
9792/* Helper function used for both push/pop and ldm/stm. */
9793static void
9794encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
9795{
9796 bfd_boolean load;
9797
9798 load = (inst.instruction & (1 << 20)) != 0;
9799
9800 if (mask & (1 << 13))
9801 inst.error = _("SP not allowed in register list");
1e5b0379
NC
9802
9803 if ((mask & (1 << base)) != 0
9804 && writeback)
9805 inst.error = _("having the base register in the register list when "
9806 "using write back is UNPREDICTABLE");
9807
3c707909
PB
9808 if (load)
9809 {
e07e6e58
NC
9810 if (mask & (1 << 15))
9811 {
9812 if (mask & (1 << 14))
9813 inst.error = _("LR and PC should not both be in register list");
9814 else
9815 set_it_insn_type_last ();
9816 }
3c707909
PB
9817 }
9818 else
9819 {
9820 if (mask & (1 << 15))
9821 inst.error = _("PC not allowed in register list");
3c707909
PB
9822 }
9823
9824 if ((mask & (mask - 1)) == 0)
9825 {
9826 /* Single register transfers implemented as str/ldr. */
9827 if (writeback)
9828 {
9829 if (inst.instruction & (1 << 23))
9830 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
9831 else
9832 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
9833 }
9834 else
9835 {
9836 if (inst.instruction & (1 << 23))
9837 inst.instruction = 0x00800000; /* ia -> [base] */
9838 else
9839 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
9840 }
9841
9842 inst.instruction |= 0xf8400000;
9843 if (load)
9844 inst.instruction |= 0x00100000;
9845
5f4273c7 9846 mask = ffs (mask) - 1;
3c707909
PB
9847 mask <<= 12;
9848 }
9849 else if (writeback)
9850 inst.instruction |= WRITE_BACK;
9851
9852 inst.instruction |= mask;
9853 inst.instruction |= base << 16;
9854}
9855
c19d1205
ZW
9856static void
9857do_t_ldmstm (void)
9858{
9859 /* This really doesn't seem worth it. */
9860 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
9861 _("expression too complex"));
9862 constraint (inst.operands[1].writeback,
9863 _("Thumb load/store multiple does not support {reglist}^"));
90e4755a 9864
c19d1205
ZW
9865 if (unified_syntax)
9866 {
3c707909
PB
9867 bfd_boolean narrow;
9868 unsigned mask;
9869
9870 narrow = FALSE;
c19d1205
ZW
9871 /* See if we can use a 16-bit instruction. */
9872 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
9873 && inst.size_req != 4
3c707909 9874 && !(inst.operands[1].imm & ~0xff))
90e4755a 9875 {
3c707909 9876 mask = 1 << inst.operands[0].reg;
90e4755a 9877
3c707909
PB
9878 if (inst.operands[0].reg <= 7
9879 && (inst.instruction == T_MNEM_stmia
9880 ? inst.operands[0].writeback
9881 : (inst.operands[0].writeback
9882 == !(inst.operands[1].imm & mask))))
90e4755a 9883 {
3c707909
PB
9884 if (inst.instruction == T_MNEM_stmia
9885 && (inst.operands[1].imm & mask)
9886 && (inst.operands[1].imm & (mask - 1)))
1e5b0379 9887 as_warn (_("value stored for r%d is UNKNOWN"),
c19d1205 9888 inst.operands[0].reg);
3c707909
PB
9889
9890 inst.instruction = THUMB_OP16 (inst.instruction);
9891 inst.instruction |= inst.operands[0].reg << 8;
9892 inst.instruction |= inst.operands[1].imm;
9893 narrow = TRUE;
90e4755a 9894 }
3c707909
PB
9895 else if (inst.operands[0] .reg == REG_SP
9896 && inst.operands[0].writeback)
90e4755a 9897 {
3c707909
PB
9898 inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia
9899 ? T_MNEM_push : T_MNEM_pop);
9900 inst.instruction |= inst.operands[1].imm;
9901 narrow = TRUE;
90e4755a 9902 }
3c707909
PB
9903 }
9904
9905 if (!narrow)
9906 {
c19d1205
ZW
9907 if (inst.instruction < 0xffff)
9908 inst.instruction = THUMB_OP32 (inst.instruction);
3c707909 9909
5f4273c7
NC
9910 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
9911 inst.operands[0].writeback);
90e4755a
RE
9912 }
9913 }
c19d1205 9914 else
90e4755a 9915 {
c19d1205
ZW
9916 constraint (inst.operands[0].reg > 7
9917 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
1198ca51
PB
9918 constraint (inst.instruction != T_MNEM_ldmia
9919 && inst.instruction != T_MNEM_stmia,
9920 _("Thumb-2 instruction only valid in unified syntax"));
c19d1205 9921 if (inst.instruction == T_MNEM_stmia)
f03698e6 9922 {
c19d1205
ZW
9923 if (!inst.operands[0].writeback)
9924 as_warn (_("this instruction will write back the base register"));
9925 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
9926 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
1e5b0379 9927 as_warn (_("value stored for r%d is UNKNOWN"),
c19d1205 9928 inst.operands[0].reg);
f03698e6 9929 }
c19d1205 9930 else
90e4755a 9931 {
c19d1205
ZW
9932 if (!inst.operands[0].writeback
9933 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
9934 as_warn (_("this instruction will write back the base register"));
9935 else if (inst.operands[0].writeback
9936 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
9937 as_warn (_("this instruction will not write back the base register"));
90e4755a
RE
9938 }
9939
c19d1205
ZW
9940 inst.instruction = THUMB_OP16 (inst.instruction);
9941 inst.instruction |= inst.operands[0].reg << 8;
9942 inst.instruction |= inst.operands[1].imm;
9943 }
9944}
e28cd48c 9945
c19d1205
ZW
9946static void
9947do_t_ldrex (void)
9948{
9949 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
9950 || inst.operands[1].postind || inst.operands[1].writeback
9951 || inst.operands[1].immisreg || inst.operands[1].shifted
9952 || inst.operands[1].negative,
01cfc07f 9953 BAD_ADDR_MODE);
e28cd48c 9954
5be8be5d
DG
9955 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
9956
c19d1205
ZW
9957 inst.instruction |= inst.operands[0].reg << 12;
9958 inst.instruction |= inst.operands[1].reg << 16;
9959 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
9960}
e28cd48c 9961
c19d1205
ZW
9962static void
9963do_t_ldrexd (void)
9964{
9965 if (!inst.operands[1].present)
1cac9012 9966 {
c19d1205
ZW
9967 constraint (inst.operands[0].reg == REG_LR,
9968 _("r14 not allowed as first register "
9969 "when second register is omitted"));
9970 inst.operands[1].reg = inst.operands[0].reg + 1;
b99bd4ef 9971 }
c19d1205
ZW
9972 constraint (inst.operands[0].reg == inst.operands[1].reg,
9973 BAD_OVERLAP);
b99bd4ef 9974
c19d1205
ZW
9975 inst.instruction |= inst.operands[0].reg << 12;
9976 inst.instruction |= inst.operands[1].reg << 8;
9977 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC
9978}
9979
9980static void
c19d1205 9981do_t_ldst (void)
b99bd4ef 9982{
0110f2b8
PB
9983 unsigned long opcode;
9984 int Rn;
9985
e07e6e58
NC
9986 if (inst.operands[0].isreg
9987 && !inst.operands[0].preind
9988 && inst.operands[0].reg == REG_PC)
9989 set_it_insn_type_last ();
9990
0110f2b8 9991 opcode = inst.instruction;
c19d1205 9992 if (unified_syntax)
b99bd4ef 9993 {
53365c0d
PB
9994 if (!inst.operands[1].isreg)
9995 {
9996 if (opcode <= 0xffff)
9997 inst.instruction = THUMB_OP32 (opcode);
9998 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
9999 return;
10000 }
0110f2b8
PB
10001 if (inst.operands[1].isreg
10002 && !inst.operands[1].writeback
c19d1205
ZW
10003 && !inst.operands[1].shifted && !inst.operands[1].postind
10004 && !inst.operands[1].negative && inst.operands[0].reg <= 7
0110f2b8
PB
10005 && opcode <= 0xffff
10006 && inst.size_req != 4)
c19d1205 10007 {
0110f2b8
PB
10008 /* Insn may have a 16-bit form. */
10009 Rn = inst.operands[1].reg;
10010 if (inst.operands[1].immisreg)
10011 {
10012 inst.instruction = THUMB_OP16 (opcode);
5f4273c7 10013 /* [Rn, Rik] */
0110f2b8
PB
10014 if (Rn <= 7 && inst.operands[1].imm <= 7)
10015 goto op16;
5be8be5d
DG
10016 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10017 reject_bad_reg (inst.operands[1].imm);
0110f2b8
PB
10018 }
10019 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10020 && opcode != T_MNEM_ldrsb)
10021 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10022 || (Rn == REG_SP && opcode == T_MNEM_str))
10023 {
10024 /* [Rn, #const] */
10025 if (Rn > 7)
10026 {
10027 if (Rn == REG_PC)
10028 {
10029 if (inst.reloc.pc_rel)
10030 opcode = T_MNEM_ldr_pc2;
10031 else
10032 opcode = T_MNEM_ldr_pc;
10033 }
10034 else
10035 {
10036 if (opcode == T_MNEM_ldr)
10037 opcode = T_MNEM_ldr_sp;
10038 else
10039 opcode = T_MNEM_str_sp;
10040 }
10041 inst.instruction = inst.operands[0].reg << 8;
10042 }
10043 else
10044 {
10045 inst.instruction = inst.operands[0].reg;
10046 inst.instruction |= inst.operands[1].reg << 3;
10047 }
10048 inst.instruction |= THUMB_OP16 (opcode);
10049 if (inst.size_req == 2)
10050 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10051 else
10052 inst.relax = opcode;
10053 return;
10054 }
c19d1205 10055 }
0110f2b8 10056 /* Definitely a 32-bit variant. */
5be8be5d
DG
10057
10058 /* Do some validations regarding addressing modes. */
10059 if (inst.operands[1].immisreg && opcode != T_MNEM_ldr
10060 && opcode != T_MNEM_str)
10061 reject_bad_reg (inst.operands[1].imm);
10062
0110f2b8 10063 inst.instruction = THUMB_OP32 (opcode);
c19d1205
ZW
10064 inst.instruction |= inst.operands[0].reg << 12;
10065 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
b99bd4ef
NC
10066 return;
10067 }
10068
c19d1205
ZW
10069 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10070
10071 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
b99bd4ef 10072 {
c19d1205
ZW
10073 /* Only [Rn,Rm] is acceptable. */
10074 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10075 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10076 || inst.operands[1].postind || inst.operands[1].shifted
10077 || inst.operands[1].negative,
10078 _("Thumb does not support this addressing mode"));
10079 inst.instruction = THUMB_OP16 (inst.instruction);
10080 goto op16;
b99bd4ef 10081 }
5f4273c7 10082
c19d1205
ZW
10083 inst.instruction = THUMB_OP16 (inst.instruction);
10084 if (!inst.operands[1].isreg)
10085 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10086 return;
b99bd4ef 10087
c19d1205
ZW
10088 constraint (!inst.operands[1].preind
10089 || inst.operands[1].shifted
10090 || inst.operands[1].writeback,
10091 _("Thumb does not support this addressing mode"));
10092 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
90e4755a 10093 {
c19d1205
ZW
10094 constraint (inst.instruction & 0x0600,
10095 _("byte or halfword not valid for base register"));
10096 constraint (inst.operands[1].reg == REG_PC
10097 && !(inst.instruction & THUMB_LOAD_BIT),
10098 _("r15 based store not allowed"));
10099 constraint (inst.operands[1].immisreg,
10100 _("invalid base register for register offset"));
b99bd4ef 10101
c19d1205
ZW
10102 if (inst.operands[1].reg == REG_PC)
10103 inst.instruction = T_OPCODE_LDR_PC;
10104 else if (inst.instruction & THUMB_LOAD_BIT)
10105 inst.instruction = T_OPCODE_LDR_SP;
10106 else
10107 inst.instruction = T_OPCODE_STR_SP;
b99bd4ef 10108
c19d1205
ZW
10109 inst.instruction |= inst.operands[0].reg << 8;
10110 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10111 return;
10112 }
90e4755a 10113
c19d1205
ZW
10114 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10115 if (!inst.operands[1].immisreg)
10116 {
10117 /* Immediate offset. */
10118 inst.instruction |= inst.operands[0].reg;
10119 inst.instruction |= inst.operands[1].reg << 3;
10120 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10121 return;
10122 }
90e4755a 10123
c19d1205
ZW
10124 /* Register offset. */
10125 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10126 constraint (inst.operands[1].negative,
10127 _("Thumb does not support this addressing mode"));
90e4755a 10128
c19d1205
ZW
10129 op16:
10130 switch (inst.instruction)
10131 {
10132 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10133 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10134 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10135 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10136 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10137 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10138 case 0x5600 /* ldrsb */:
10139 case 0x5e00 /* ldrsh */: break;
10140 default: abort ();
10141 }
90e4755a 10142
c19d1205
ZW
10143 inst.instruction |= inst.operands[0].reg;
10144 inst.instruction |= inst.operands[1].reg << 3;
10145 inst.instruction |= inst.operands[1].imm << 6;
10146}
90e4755a 10147
c19d1205
ZW
10148static void
10149do_t_ldstd (void)
10150{
10151 if (!inst.operands[1].present)
b99bd4ef 10152 {
c19d1205
ZW
10153 inst.operands[1].reg = inst.operands[0].reg + 1;
10154 constraint (inst.operands[0].reg == REG_LR,
10155 _("r14 not allowed here"));
b99bd4ef 10156 }
c19d1205
ZW
10157 inst.instruction |= inst.operands[0].reg << 12;
10158 inst.instruction |= inst.operands[1].reg << 8;
10159 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
b99bd4ef
NC
10160}
10161
c19d1205
ZW
10162static void
10163do_t_ldstt (void)
10164{
10165 inst.instruction |= inst.operands[0].reg << 12;
10166 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10167}
a737bd4d 10168
b99bd4ef 10169static void
c19d1205 10170do_t_mla (void)
b99bd4ef 10171{
fdfde340 10172 unsigned Rd, Rn, Rm, Ra;
c921be7d 10173
fdfde340
JM
10174 Rd = inst.operands[0].reg;
10175 Rn = inst.operands[1].reg;
10176 Rm = inst.operands[2].reg;
10177 Ra = inst.operands[3].reg;
10178
10179 reject_bad_reg (Rd);
10180 reject_bad_reg (Rn);
10181 reject_bad_reg (Rm);
10182 reject_bad_reg (Ra);
10183
10184 inst.instruction |= Rd << 8;
10185 inst.instruction |= Rn << 16;
10186 inst.instruction |= Rm;
10187 inst.instruction |= Ra << 12;
c19d1205 10188}
b99bd4ef 10189
c19d1205
ZW
10190static void
10191do_t_mlal (void)
10192{
fdfde340
JM
10193 unsigned RdLo, RdHi, Rn, Rm;
10194
10195 RdLo = inst.operands[0].reg;
10196 RdHi = inst.operands[1].reg;
10197 Rn = inst.operands[2].reg;
10198 Rm = inst.operands[3].reg;
10199
10200 reject_bad_reg (RdLo);
10201 reject_bad_reg (RdHi);
10202 reject_bad_reg (Rn);
10203 reject_bad_reg (Rm);
10204
10205 inst.instruction |= RdLo << 12;
10206 inst.instruction |= RdHi << 8;
10207 inst.instruction |= Rn << 16;
10208 inst.instruction |= Rm;
c19d1205 10209}
b99bd4ef 10210
c19d1205
ZW
10211static void
10212do_t_mov_cmp (void)
10213{
fdfde340
JM
10214 unsigned Rn, Rm;
10215
10216 Rn = inst.operands[0].reg;
10217 Rm = inst.operands[1].reg;
10218
e07e6e58
NC
10219 if (Rn == REG_PC)
10220 set_it_insn_type_last ();
10221
c19d1205 10222 if (unified_syntax)
b99bd4ef 10223 {
c19d1205
ZW
10224 int r0off = (inst.instruction == T_MNEM_mov
10225 || inst.instruction == T_MNEM_movs) ? 8 : 16;
0110f2b8 10226 unsigned long opcode;
3d388997
PB
10227 bfd_boolean narrow;
10228 bfd_boolean low_regs;
10229
fdfde340 10230 low_regs = (Rn <= 7 && Rm <= 7);
0110f2b8 10231 opcode = inst.instruction;
e07e6e58 10232 if (in_it_block ())
0110f2b8 10233 narrow = opcode != T_MNEM_movs;
3d388997 10234 else
0110f2b8 10235 narrow = opcode != T_MNEM_movs || low_regs;
3d388997
PB
10236 if (inst.size_req == 4
10237 || inst.operands[1].shifted)
10238 narrow = FALSE;
10239
efd81785
PB
10240 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10241 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10242 && !inst.operands[1].shifted
fdfde340
JM
10243 && Rn == REG_PC
10244 && Rm == REG_LR)
efd81785
PB
10245 {
10246 inst.instruction = T2_SUBS_PC_LR;
10247 return;
10248 }
10249
fdfde340
JM
10250 if (opcode == T_MNEM_cmp)
10251 {
10252 constraint (Rn == REG_PC, BAD_PC);
94206790
MM
10253 if (narrow)
10254 {
10255 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10256 but valid. */
10257 warn_deprecated_sp (Rm);
10258 /* R15 was documented as a valid choice for Rm in ARMv6,
10259 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10260 tools reject R15, so we do too. */
10261 constraint (Rm == REG_PC, BAD_PC);
10262 }
10263 else
10264 reject_bad_reg (Rm);
fdfde340
JM
10265 }
10266 else if (opcode == T_MNEM_mov
10267 || opcode == T_MNEM_movs)
10268 {
10269 if (inst.operands[1].isreg)
10270 {
10271 if (opcode == T_MNEM_movs)
10272 {
10273 reject_bad_reg (Rn);
10274 reject_bad_reg (Rm);
10275 }
10276 else if ((Rn == REG_SP || Rn == REG_PC)
10277 && (Rm == REG_SP || Rm == REG_PC))
10278 reject_bad_reg (Rm);
10279 }
10280 else
10281 reject_bad_reg (Rn);
10282 }
10283
c19d1205
ZW
10284 if (!inst.operands[1].isreg)
10285 {
0110f2b8 10286 /* Immediate operand. */
e07e6e58 10287 if (!in_it_block () && opcode == T_MNEM_mov)
0110f2b8
PB
10288 narrow = 0;
10289 if (low_regs && narrow)
10290 {
10291 inst.instruction = THUMB_OP16 (opcode);
fdfde340 10292 inst.instruction |= Rn << 8;
0110f2b8
PB
10293 if (inst.size_req == 2)
10294 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
10295 else
10296 inst.relax = opcode;
10297 }
10298 else
10299 {
10300 inst.instruction = THUMB_OP32 (inst.instruction);
10301 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
fdfde340 10302 inst.instruction |= Rn << r0off;
0110f2b8
PB
10303 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10304 }
c19d1205 10305 }
728ca7c9
PB
10306 else if (inst.operands[1].shifted && inst.operands[1].immisreg
10307 && (inst.instruction == T_MNEM_mov
10308 || inst.instruction == T_MNEM_movs))
10309 {
10310 /* Register shifts are encoded as separate shift instructions. */
10311 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
10312
e07e6e58 10313 if (in_it_block ())
728ca7c9
PB
10314 narrow = !flags;
10315 else
10316 narrow = flags;
10317
10318 if (inst.size_req == 4)
10319 narrow = FALSE;
10320
10321 if (!low_regs || inst.operands[1].imm > 7)
10322 narrow = FALSE;
10323
fdfde340 10324 if (Rn != Rm)
728ca7c9
PB
10325 narrow = FALSE;
10326
10327 switch (inst.operands[1].shift_kind)
10328 {
10329 case SHIFT_LSL:
10330 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
10331 break;
10332 case SHIFT_ASR:
10333 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
10334 break;
10335 case SHIFT_LSR:
10336 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
10337 break;
10338 case SHIFT_ROR:
10339 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
10340 break;
10341 default:
5f4273c7 10342 abort ();
728ca7c9
PB
10343 }
10344
10345 inst.instruction = opcode;
10346 if (narrow)
10347 {
fdfde340 10348 inst.instruction |= Rn;
728ca7c9
PB
10349 inst.instruction |= inst.operands[1].imm << 3;
10350 }
10351 else
10352 {
10353 if (flags)
10354 inst.instruction |= CONDS_BIT;
10355
fdfde340
JM
10356 inst.instruction |= Rn << 8;
10357 inst.instruction |= Rm << 16;
728ca7c9
PB
10358 inst.instruction |= inst.operands[1].imm;
10359 }
10360 }
3d388997 10361 else if (!narrow)
c19d1205 10362 {
728ca7c9
PB
10363 /* Some mov with immediate shift have narrow variants.
10364 Register shifts are handled above. */
10365 if (low_regs && inst.operands[1].shifted
10366 && (inst.instruction == T_MNEM_mov
10367 || inst.instruction == T_MNEM_movs))
10368 {
e07e6e58 10369 if (in_it_block ())
728ca7c9
PB
10370 narrow = (inst.instruction == T_MNEM_mov);
10371 else
10372 narrow = (inst.instruction == T_MNEM_movs);
10373 }
10374
10375 if (narrow)
10376 {
10377 switch (inst.operands[1].shift_kind)
10378 {
10379 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
10380 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
10381 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
10382 default: narrow = FALSE; break;
10383 }
10384 }
10385
10386 if (narrow)
10387 {
fdfde340
JM
10388 inst.instruction |= Rn;
10389 inst.instruction |= Rm << 3;
728ca7c9
PB
10390 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10391 }
10392 else
10393 {
10394 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 10395 inst.instruction |= Rn << r0off;
728ca7c9
PB
10396 encode_thumb32_shifted_operand (1);
10397 }
c19d1205
ZW
10398 }
10399 else
10400 switch (inst.instruction)
10401 {
10402 case T_MNEM_mov:
10403 inst.instruction = T_OPCODE_MOV_HR;
fdfde340
JM
10404 inst.instruction |= (Rn & 0x8) << 4;
10405 inst.instruction |= (Rn & 0x7);
10406 inst.instruction |= Rm << 3;
c19d1205 10407 break;
b99bd4ef 10408
c19d1205
ZW
10409 case T_MNEM_movs:
10410 /* We know we have low registers at this point.
941a8a52
MGD
10411 Generate LSLS Rd, Rs, #0. */
10412 inst.instruction = T_OPCODE_LSL_I;
fdfde340
JM
10413 inst.instruction |= Rn;
10414 inst.instruction |= Rm << 3;
c19d1205
ZW
10415 break;
10416
10417 case T_MNEM_cmp:
3d388997 10418 if (low_regs)
c19d1205
ZW
10419 {
10420 inst.instruction = T_OPCODE_CMP_LR;
fdfde340
JM
10421 inst.instruction |= Rn;
10422 inst.instruction |= Rm << 3;
c19d1205
ZW
10423 }
10424 else
10425 {
10426 inst.instruction = T_OPCODE_CMP_HR;
fdfde340
JM
10427 inst.instruction |= (Rn & 0x8) << 4;
10428 inst.instruction |= (Rn & 0x7);
10429 inst.instruction |= Rm << 3;
c19d1205
ZW
10430 }
10431 break;
10432 }
b99bd4ef
NC
10433 return;
10434 }
10435
c19d1205 10436 inst.instruction = THUMB_OP16 (inst.instruction);
539d4391
NC
10437
10438 /* PR 10443: Do not silently ignore shifted operands. */
10439 constraint (inst.operands[1].shifted,
10440 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10441
c19d1205 10442 if (inst.operands[1].isreg)
b99bd4ef 10443 {
fdfde340 10444 if (Rn < 8 && Rm < 8)
b99bd4ef 10445 {
c19d1205
ZW
10446 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10447 since a MOV instruction produces unpredictable results. */
10448 if (inst.instruction == T_OPCODE_MOV_I8)
10449 inst.instruction = T_OPCODE_ADD_I3;
b99bd4ef 10450 else
c19d1205 10451 inst.instruction = T_OPCODE_CMP_LR;
b99bd4ef 10452
fdfde340
JM
10453 inst.instruction |= Rn;
10454 inst.instruction |= Rm << 3;
b99bd4ef
NC
10455 }
10456 else
10457 {
c19d1205
ZW
10458 if (inst.instruction == T_OPCODE_MOV_I8)
10459 inst.instruction = T_OPCODE_MOV_HR;
10460 else
10461 inst.instruction = T_OPCODE_CMP_HR;
10462 do_t_cpy ();
b99bd4ef
NC
10463 }
10464 }
c19d1205 10465 else
b99bd4ef 10466 {
fdfde340 10467 constraint (Rn > 7,
c19d1205 10468 _("only lo regs allowed with immediate"));
fdfde340 10469 inst.instruction |= Rn << 8;
c19d1205
ZW
10470 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
10471 }
10472}
b99bd4ef 10473
c19d1205
ZW
10474static void
10475do_t_mov16 (void)
10476{
fdfde340 10477 unsigned Rd;
b6895b4f
PB
10478 bfd_vma imm;
10479 bfd_boolean top;
10480
10481 top = (inst.instruction & 0x00800000) != 0;
10482 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
10483 {
10484 constraint (top, _(":lower16: not allowed this instruction"));
10485 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
10486 }
10487 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
10488 {
10489 constraint (!top, _(":upper16: not allowed this instruction"));
10490 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
10491 }
10492
fdfde340
JM
10493 Rd = inst.operands[0].reg;
10494 reject_bad_reg (Rd);
10495
10496 inst.instruction |= Rd << 8;
b6895b4f
PB
10497 if (inst.reloc.type == BFD_RELOC_UNUSED)
10498 {
10499 imm = inst.reloc.exp.X_add_number;
10500 inst.instruction |= (imm & 0xf000) << 4;
10501 inst.instruction |= (imm & 0x0800) << 15;
10502 inst.instruction |= (imm & 0x0700) << 4;
10503 inst.instruction |= (imm & 0x00ff);
10504 }
c19d1205 10505}
b99bd4ef 10506
c19d1205
ZW
10507static void
10508do_t_mvn_tst (void)
10509{
fdfde340 10510 unsigned Rn, Rm;
c921be7d 10511
fdfde340
JM
10512 Rn = inst.operands[0].reg;
10513 Rm = inst.operands[1].reg;
10514
10515 if (inst.instruction == T_MNEM_cmp
10516 || inst.instruction == T_MNEM_cmn)
10517 constraint (Rn == REG_PC, BAD_PC);
10518 else
10519 reject_bad_reg (Rn);
10520 reject_bad_reg (Rm);
10521
c19d1205
ZW
10522 if (unified_syntax)
10523 {
10524 int r0off = (inst.instruction == T_MNEM_mvn
10525 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
3d388997
PB
10526 bfd_boolean narrow;
10527
10528 if (inst.size_req == 4
10529 || inst.instruction > 0xffff
10530 || inst.operands[1].shifted
fdfde340 10531 || Rn > 7 || Rm > 7)
3d388997
PB
10532 narrow = FALSE;
10533 else if (inst.instruction == T_MNEM_cmn)
10534 narrow = TRUE;
10535 else if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 10536 narrow = !in_it_block ();
3d388997 10537 else
e07e6e58 10538 narrow = in_it_block ();
3d388997 10539
c19d1205 10540 if (!inst.operands[1].isreg)
b99bd4ef 10541 {
c19d1205
ZW
10542 /* For an immediate, we always generate a 32-bit opcode;
10543 section relaxation will shrink it later if possible. */
10544 if (inst.instruction < 0xffff)
10545 inst.instruction = THUMB_OP32 (inst.instruction);
10546 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
fdfde340 10547 inst.instruction |= Rn << r0off;
c19d1205 10548 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 10549 }
c19d1205 10550 else
b99bd4ef 10551 {
c19d1205 10552 /* See if we can do this with a 16-bit instruction. */
3d388997 10553 if (narrow)
b99bd4ef 10554 {
c19d1205 10555 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM
10556 inst.instruction |= Rn;
10557 inst.instruction |= Rm << 3;
b99bd4ef 10558 }
c19d1205 10559 else
b99bd4ef 10560 {
c19d1205
ZW
10561 constraint (inst.operands[1].shifted
10562 && inst.operands[1].immisreg,
10563 _("shift must be constant"));
10564 if (inst.instruction < 0xffff)
10565 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 10566 inst.instruction |= Rn << r0off;
c19d1205 10567 encode_thumb32_shifted_operand (1);
b99bd4ef 10568 }
b99bd4ef
NC
10569 }
10570 }
10571 else
10572 {
c19d1205
ZW
10573 constraint (inst.instruction > 0xffff
10574 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
10575 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
10576 _("unshifted register required"));
fdfde340 10577 constraint (Rn > 7 || Rm > 7,
c19d1205 10578 BAD_HIREG);
b99bd4ef 10579
c19d1205 10580 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM
10581 inst.instruction |= Rn;
10582 inst.instruction |= Rm << 3;
b99bd4ef 10583 }
b99bd4ef
NC
10584}
10585
b05fe5cf 10586static void
c19d1205 10587do_t_mrs (void)
b05fe5cf 10588{
fdfde340 10589 unsigned Rd;
62b3e311 10590 int flags;
037e8744
JB
10591
10592 if (do_vfp_nsyn_mrs () == SUCCESS)
10593 return;
10594
62b3e311
PB
10595 flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
10596 if (flags == 0)
10597 {
7e806470 10598 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m),
62b3e311
PB
10599 _("selected processor does not support "
10600 "requested special purpose register"));
10601 }
10602 else
10603 {
10604 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
10605 _("selected processor does not support "
44bf2362 10606 "requested special purpose register"));
62b3e311
PB
10607 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10608 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
10609 _("'CPSR' or 'SPSR' expected"));
10610 }
5f4273c7 10611
fdfde340
JM
10612 Rd = inst.operands[0].reg;
10613 reject_bad_reg (Rd);
10614
10615 inst.instruction |= Rd << 8;
62b3e311
PB
10616 inst.instruction |= (flags & SPSR_BIT) >> 2;
10617 inst.instruction |= inst.operands[1].imm & 0xff;
c19d1205 10618}
b05fe5cf 10619
c19d1205
ZW
10620static void
10621do_t_msr (void)
10622{
62b3e311 10623 int flags;
fdfde340 10624 unsigned Rn;
62b3e311 10625
037e8744
JB
10626 if (do_vfp_nsyn_msr () == SUCCESS)
10627 return;
10628
c19d1205
ZW
10629 constraint (!inst.operands[1].isreg,
10630 _("Thumb encoding does not support an immediate here"));
62b3e311
PB
10631 flags = inst.operands[0].imm;
10632 if (flags & ~0xff)
10633 {
10634 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
10635 _("selected processor does not support "
10636 "requested special purpose register"));
10637 }
10638 else
10639 {
7e806470 10640 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m),
62b3e311
PB
10641 _("selected processor does not support "
10642 "requested special purpose register"));
10643 flags |= PSR_f;
10644 }
c921be7d 10645
fdfde340
JM
10646 Rn = inst.operands[1].reg;
10647 reject_bad_reg (Rn);
10648
62b3e311
PB
10649 inst.instruction |= (flags & SPSR_BIT) >> 2;
10650 inst.instruction |= (flags & ~SPSR_BIT) >> 8;
10651 inst.instruction |= (flags & 0xff);
fdfde340 10652 inst.instruction |= Rn << 16;
c19d1205 10653}
b05fe5cf 10654
c19d1205
ZW
10655static void
10656do_t_mul (void)
10657{
17828f45 10658 bfd_boolean narrow;
fdfde340 10659 unsigned Rd, Rn, Rm;
17828f45 10660
c19d1205
ZW
10661 if (!inst.operands[2].present)
10662 inst.operands[2].reg = inst.operands[0].reg;
b05fe5cf 10663
fdfde340
JM
10664 Rd = inst.operands[0].reg;
10665 Rn = inst.operands[1].reg;
10666 Rm = inst.operands[2].reg;
10667
17828f45 10668 if (unified_syntax)
b05fe5cf 10669 {
17828f45 10670 if (inst.size_req == 4
fdfde340
JM
10671 || (Rd != Rn
10672 && Rd != Rm)
10673 || Rn > 7
10674 || Rm > 7)
17828f45
JM
10675 narrow = FALSE;
10676 else if (inst.instruction == T_MNEM_muls)
e07e6e58 10677 narrow = !in_it_block ();
17828f45 10678 else
e07e6e58 10679 narrow = in_it_block ();
b05fe5cf 10680 }
c19d1205 10681 else
b05fe5cf 10682 {
17828f45 10683 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
fdfde340 10684 constraint (Rn > 7 || Rm > 7,
c19d1205 10685 BAD_HIREG);
17828f45
JM
10686 narrow = TRUE;
10687 }
b05fe5cf 10688
17828f45
JM
10689 if (narrow)
10690 {
10691 /* 16-bit MULS/Conditional MUL. */
c19d1205 10692 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340 10693 inst.instruction |= Rd;
b05fe5cf 10694
fdfde340
JM
10695 if (Rd == Rn)
10696 inst.instruction |= Rm << 3;
10697 else if (Rd == Rm)
10698 inst.instruction |= Rn << 3;
c19d1205
ZW
10699 else
10700 constraint (1, _("dest must overlap one source register"));
10701 }
17828f45
JM
10702 else
10703 {
e07e6e58
NC
10704 constraint (inst.instruction != T_MNEM_mul,
10705 _("Thumb-2 MUL must not set flags"));
17828f45
JM
10706 /* 32-bit MUL. */
10707 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM
10708 inst.instruction |= Rd << 8;
10709 inst.instruction |= Rn << 16;
10710 inst.instruction |= Rm << 0;
10711
10712 reject_bad_reg (Rd);
10713 reject_bad_reg (Rn);
10714 reject_bad_reg (Rm);
17828f45 10715 }
c19d1205 10716}
b05fe5cf 10717
c19d1205
ZW
10718static void
10719do_t_mull (void)
10720{
fdfde340 10721 unsigned RdLo, RdHi, Rn, Rm;
b05fe5cf 10722
fdfde340
JM
10723 RdLo = inst.operands[0].reg;
10724 RdHi = inst.operands[1].reg;
10725 Rn = inst.operands[2].reg;
10726 Rm = inst.operands[3].reg;
10727
10728 reject_bad_reg (RdLo);
10729 reject_bad_reg (RdHi);
10730 reject_bad_reg (Rn);
10731 reject_bad_reg (Rm);
10732
10733 inst.instruction |= RdLo << 12;
10734 inst.instruction |= RdHi << 8;
10735 inst.instruction |= Rn << 16;
10736 inst.instruction |= Rm;
10737
10738 if (RdLo == RdHi)
c19d1205
ZW
10739 as_tsktsk (_("rdhi and rdlo must be different"));
10740}
b05fe5cf 10741
c19d1205
ZW
10742static void
10743do_t_nop (void)
10744{
e07e6e58
NC
10745 set_it_insn_type (NEUTRAL_IT_INSN);
10746
c19d1205
ZW
10747 if (unified_syntax)
10748 {
10749 if (inst.size_req == 4 || inst.operands[0].imm > 15)
b05fe5cf 10750 {
c19d1205
ZW
10751 inst.instruction = THUMB_OP32 (inst.instruction);
10752 inst.instruction |= inst.operands[0].imm;
10753 }
10754 else
10755 {
bc2d1808
NC
10756 /* PR9722: Check for Thumb2 availability before
10757 generating a thumb2 nop instruction. */
afa62d5e 10758 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
bc2d1808
NC
10759 {
10760 inst.instruction = THUMB_OP16 (inst.instruction);
10761 inst.instruction |= inst.operands[0].imm << 4;
10762 }
10763 else
10764 inst.instruction = 0x46c0;
c19d1205
ZW
10765 }
10766 }
10767 else
10768 {
10769 constraint (inst.operands[0].present,
10770 _("Thumb does not support NOP with hints"));
10771 inst.instruction = 0x46c0;
10772 }
10773}
b05fe5cf 10774
c19d1205
ZW
10775static void
10776do_t_neg (void)
10777{
10778 if (unified_syntax)
10779 {
3d388997
PB
10780 bfd_boolean narrow;
10781
10782 if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 10783 narrow = !in_it_block ();
3d388997 10784 else
e07e6e58 10785 narrow = in_it_block ();
3d388997
PB
10786 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
10787 narrow = FALSE;
10788 if (inst.size_req == 4)
10789 narrow = FALSE;
10790
10791 if (!narrow)
c19d1205
ZW
10792 {
10793 inst.instruction = THUMB_OP32 (inst.instruction);
10794 inst.instruction |= inst.operands[0].reg << 8;
10795 inst.instruction |= inst.operands[1].reg << 16;
b05fe5cf
ZW
10796 }
10797 else
10798 {
c19d1205
ZW
10799 inst.instruction = THUMB_OP16 (inst.instruction);
10800 inst.instruction |= inst.operands[0].reg;
10801 inst.instruction |= inst.operands[1].reg << 3;
b05fe5cf
ZW
10802 }
10803 }
10804 else
10805 {
c19d1205
ZW
10806 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
10807 BAD_HIREG);
10808 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10809
10810 inst.instruction = THUMB_OP16 (inst.instruction);
10811 inst.instruction |= inst.operands[0].reg;
10812 inst.instruction |= inst.operands[1].reg << 3;
10813 }
10814}
10815
1c444d06
JM
10816static void
10817do_t_orn (void)
10818{
10819 unsigned Rd, Rn;
10820
10821 Rd = inst.operands[0].reg;
10822 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
10823
fdfde340
JM
10824 reject_bad_reg (Rd);
10825 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10826 reject_bad_reg (Rn);
10827
1c444d06
JM
10828 inst.instruction |= Rd << 8;
10829 inst.instruction |= Rn << 16;
10830
10831 if (!inst.operands[2].isreg)
10832 {
10833 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10834 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10835 }
10836 else
10837 {
10838 unsigned Rm;
10839
10840 Rm = inst.operands[2].reg;
fdfde340 10841 reject_bad_reg (Rm);
1c444d06
JM
10842
10843 constraint (inst.operands[2].shifted
10844 && inst.operands[2].immisreg,
10845 _("shift must be constant"));
10846 encode_thumb32_shifted_operand (2);
10847 }
10848}
10849
c19d1205
ZW
10850static void
10851do_t_pkhbt (void)
10852{
fdfde340
JM
10853 unsigned Rd, Rn, Rm;
10854
10855 Rd = inst.operands[0].reg;
10856 Rn = inst.operands[1].reg;
10857 Rm = inst.operands[2].reg;
10858
10859 reject_bad_reg (Rd);
10860 reject_bad_reg (Rn);
10861 reject_bad_reg (Rm);
10862
10863 inst.instruction |= Rd << 8;
10864 inst.instruction |= Rn << 16;
10865 inst.instruction |= Rm;
c19d1205
ZW
10866 if (inst.operands[3].present)
10867 {
10868 unsigned int val = inst.reloc.exp.X_add_number;
10869 constraint (inst.reloc.exp.X_op != O_constant,
10870 _("expression too complex"));
10871 inst.instruction |= (val & 0x1c) << 10;
10872 inst.instruction |= (val & 0x03) << 6;
b05fe5cf 10873 }
c19d1205 10874}
b05fe5cf 10875
c19d1205
ZW
10876static void
10877do_t_pkhtb (void)
10878{
10879 if (!inst.operands[3].present)
1ef52f49
NC
10880 {
10881 unsigned Rtmp;
10882
10883 inst.instruction &= ~0x00000020;
10884
10885 /* PR 10168. Swap the Rm and Rn registers. */
10886 Rtmp = inst.operands[1].reg;
10887 inst.operands[1].reg = inst.operands[2].reg;
10888 inst.operands[2].reg = Rtmp;
10889 }
c19d1205 10890 do_t_pkhbt ();
b05fe5cf
ZW
10891}
10892
c19d1205
ZW
10893static void
10894do_t_pld (void)
10895{
fdfde340
JM
10896 if (inst.operands[0].immisreg)
10897 reject_bad_reg (inst.operands[0].imm);
10898
c19d1205
ZW
10899 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
10900}
b05fe5cf 10901
c19d1205
ZW
10902static void
10903do_t_push_pop (void)
b99bd4ef 10904{
e9f89963 10905 unsigned mask;
5f4273c7 10906
c19d1205
ZW
10907 constraint (inst.operands[0].writeback,
10908 _("push/pop do not support {reglist}^"));
10909 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10910 _("expression too complex"));
b99bd4ef 10911
e9f89963
PB
10912 mask = inst.operands[0].imm;
10913 if ((mask & ~0xff) == 0)
3c707909 10914 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
c19d1205 10915 else if ((inst.instruction == T_MNEM_push
e9f89963 10916 && (mask & ~0xff) == 1 << REG_LR)
c19d1205 10917 || (inst.instruction == T_MNEM_pop
e9f89963 10918 && (mask & ~0xff) == 1 << REG_PC))
b99bd4ef 10919 {
c19d1205
ZW
10920 inst.instruction = THUMB_OP16 (inst.instruction);
10921 inst.instruction |= THUMB_PP_PC_LR;
3c707909 10922 inst.instruction |= mask & 0xff;
c19d1205
ZW
10923 }
10924 else if (unified_syntax)
10925 {
3c707909 10926 inst.instruction = THUMB_OP32 (inst.instruction);
5f4273c7 10927 encode_thumb2_ldmstm (13, mask, TRUE);
c19d1205
ZW
10928 }
10929 else
10930 {
10931 inst.error = _("invalid register list to push/pop instruction");
10932 return;
10933 }
c19d1205 10934}
b99bd4ef 10935
c19d1205
ZW
10936static void
10937do_t_rbit (void)
10938{
fdfde340
JM
10939 unsigned Rd, Rm;
10940
10941 Rd = inst.operands[0].reg;
10942 Rm = inst.operands[1].reg;
10943
10944 reject_bad_reg (Rd);
10945 reject_bad_reg (Rm);
10946
10947 inst.instruction |= Rd << 8;
10948 inst.instruction |= Rm << 16;
10949 inst.instruction |= Rm;
c19d1205 10950}
b99bd4ef 10951
c19d1205
ZW
10952static void
10953do_t_rev (void)
10954{
fdfde340
JM
10955 unsigned Rd, Rm;
10956
10957 Rd = inst.operands[0].reg;
10958 Rm = inst.operands[1].reg;
10959
10960 reject_bad_reg (Rd);
10961 reject_bad_reg (Rm);
10962
10963 if (Rd <= 7 && Rm <= 7
c19d1205
ZW
10964 && inst.size_req != 4)
10965 {
10966 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM
10967 inst.instruction |= Rd;
10968 inst.instruction |= Rm << 3;
c19d1205
ZW
10969 }
10970 else if (unified_syntax)
10971 {
10972 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM
10973 inst.instruction |= Rd << 8;
10974 inst.instruction |= Rm << 16;
10975 inst.instruction |= Rm;
c19d1205
ZW
10976 }
10977 else
10978 inst.error = BAD_HIREG;
10979}
b99bd4ef 10980
1c444d06
JM
10981static void
10982do_t_rrx (void)
10983{
10984 unsigned Rd, Rm;
10985
10986 Rd = inst.operands[0].reg;
10987 Rm = inst.operands[1].reg;
10988
fdfde340
JM
10989 reject_bad_reg (Rd);
10990 reject_bad_reg (Rm);
c921be7d 10991
1c444d06
JM
10992 inst.instruction |= Rd << 8;
10993 inst.instruction |= Rm;
10994}
10995
c19d1205
ZW
10996static void
10997do_t_rsb (void)
10998{
fdfde340 10999 unsigned Rd, Rs;
b99bd4ef 11000
c19d1205
ZW
11001 Rd = inst.operands[0].reg;
11002 Rs = (inst.operands[1].present
11003 ? inst.operands[1].reg /* Rd, Rs, foo */
11004 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
b99bd4ef 11005
fdfde340
JM
11006 reject_bad_reg (Rd);
11007 reject_bad_reg (Rs);
11008 if (inst.operands[2].isreg)
11009 reject_bad_reg (inst.operands[2].reg);
11010
c19d1205
ZW
11011 inst.instruction |= Rd << 8;
11012 inst.instruction |= Rs << 16;
11013 if (!inst.operands[2].isreg)
11014 {
026d3abb
PB
11015 bfd_boolean narrow;
11016
11017 if ((inst.instruction & 0x00100000) != 0)
e07e6e58 11018 narrow = !in_it_block ();
026d3abb 11019 else
e07e6e58 11020 narrow = in_it_block ();
026d3abb
PB
11021
11022 if (Rd > 7 || Rs > 7)
11023 narrow = FALSE;
11024
11025 if (inst.size_req == 4 || !unified_syntax)
11026 narrow = FALSE;
11027
11028 if (inst.reloc.exp.X_op != O_constant
11029 || inst.reloc.exp.X_add_number != 0)
11030 narrow = FALSE;
11031
11032 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11033 relaxation, but it doesn't seem worth the hassle. */
11034 if (narrow)
11035 {
11036 inst.reloc.type = BFD_RELOC_UNUSED;
11037 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11038 inst.instruction |= Rs << 3;
11039 inst.instruction |= Rd;
11040 }
11041 else
11042 {
11043 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11044 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11045 }
c19d1205
ZW
11046 }
11047 else
11048 encode_thumb32_shifted_operand (2);
11049}
b99bd4ef 11050
c19d1205
ZW
11051static void
11052do_t_setend (void)
11053{
e07e6e58 11054 set_it_insn_type (OUTSIDE_IT_INSN);
c19d1205
ZW
11055 if (inst.operands[0].imm)
11056 inst.instruction |= 0x8;
11057}
b99bd4ef 11058
c19d1205
ZW
11059static void
11060do_t_shift (void)
11061{
11062 if (!inst.operands[1].present)
11063 inst.operands[1].reg = inst.operands[0].reg;
11064
11065 if (unified_syntax)
11066 {
3d388997
PB
11067 bfd_boolean narrow;
11068 int shift_kind;
11069
11070 switch (inst.instruction)
11071 {
11072 case T_MNEM_asr:
11073 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11074 case T_MNEM_lsl:
11075 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11076 case T_MNEM_lsr:
11077 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11078 case T_MNEM_ror:
11079 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11080 default: abort ();
11081 }
11082
11083 if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 11084 narrow = !in_it_block ();
3d388997 11085 else
e07e6e58 11086 narrow = in_it_block ();
3d388997
PB
11087 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11088 narrow = FALSE;
11089 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11090 narrow = FALSE;
11091 if (inst.operands[2].isreg
11092 && (inst.operands[1].reg != inst.operands[0].reg
11093 || inst.operands[2].reg > 7))
11094 narrow = FALSE;
11095 if (inst.size_req == 4)
11096 narrow = FALSE;
11097
fdfde340
JM
11098 reject_bad_reg (inst.operands[0].reg);
11099 reject_bad_reg (inst.operands[1].reg);
c921be7d 11100
3d388997 11101 if (!narrow)
c19d1205
ZW
11102 {
11103 if (inst.operands[2].isreg)
b99bd4ef 11104 {
fdfde340 11105 reject_bad_reg (inst.operands[2].reg);
c19d1205
ZW
11106 inst.instruction = THUMB_OP32 (inst.instruction);
11107 inst.instruction |= inst.operands[0].reg << 8;
11108 inst.instruction |= inst.operands[1].reg << 16;
11109 inst.instruction |= inst.operands[2].reg;
11110 }
11111 else
11112 {
11113 inst.operands[1].shifted = 1;
3d388997 11114 inst.operands[1].shift_kind = shift_kind;
c19d1205
ZW
11115 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11116 ? T_MNEM_movs : T_MNEM_mov);
11117 inst.instruction |= inst.operands[0].reg << 8;
11118 encode_thumb32_shifted_operand (1);
11119 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11120 inst.reloc.type = BFD_RELOC_UNUSED;
b99bd4ef
NC
11121 }
11122 }
11123 else
11124 {
c19d1205 11125 if (inst.operands[2].isreg)
b99bd4ef 11126 {
3d388997 11127 switch (shift_kind)
b99bd4ef 11128 {
3d388997
PB
11129 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11130 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11131 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11132 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
c19d1205 11133 default: abort ();
b99bd4ef 11134 }
5f4273c7 11135
c19d1205
ZW
11136 inst.instruction |= inst.operands[0].reg;
11137 inst.instruction |= inst.operands[2].reg << 3;
b99bd4ef
NC
11138 }
11139 else
11140 {
3d388997 11141 switch (shift_kind)
b99bd4ef 11142 {
3d388997
PB
11143 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11144 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11145 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
c19d1205 11146 default: abort ();
b99bd4ef 11147 }
c19d1205
ZW
11148 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11149 inst.instruction |= inst.operands[0].reg;
11150 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC
11151 }
11152 }
c19d1205
ZW
11153 }
11154 else
11155 {
11156 constraint (inst.operands[0].reg > 7
11157 || inst.operands[1].reg > 7, BAD_HIREG);
11158 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
b99bd4ef 11159
c19d1205
ZW
11160 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11161 {
11162 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11163 constraint (inst.operands[0].reg != inst.operands[1].reg,
11164 _("source1 and dest must be same register"));
b99bd4ef 11165
c19d1205
ZW
11166 switch (inst.instruction)
11167 {
11168 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11169 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11170 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11171 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11172 default: abort ();
11173 }
5f4273c7 11174
c19d1205
ZW
11175 inst.instruction |= inst.operands[0].reg;
11176 inst.instruction |= inst.operands[2].reg << 3;
11177 }
11178 else
b99bd4ef 11179 {
c19d1205
ZW
11180 switch (inst.instruction)
11181 {
11182 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11183 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11184 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11185 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11186 default: abort ();
11187 }
11188 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11189 inst.instruction |= inst.operands[0].reg;
11190 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC
11191 }
11192 }
b99bd4ef
NC
11193}
11194
11195static void
c19d1205 11196do_t_simd (void)
b99bd4ef 11197{
fdfde340
JM
11198 unsigned Rd, Rn, Rm;
11199
11200 Rd = inst.operands[0].reg;
11201 Rn = inst.operands[1].reg;
11202 Rm = inst.operands[2].reg;
11203
11204 reject_bad_reg (Rd);
11205 reject_bad_reg (Rn);
11206 reject_bad_reg (Rm);
11207
11208 inst.instruction |= Rd << 8;
11209 inst.instruction |= Rn << 16;
11210 inst.instruction |= Rm;
c19d1205 11211}
b99bd4ef 11212
03ee1b7f
NC
11213static void
11214do_t_simd2 (void)
11215{
11216 unsigned Rd, Rn, Rm;
11217
11218 Rd = inst.operands[0].reg;
11219 Rm = inst.operands[1].reg;
11220 Rn = inst.operands[2].reg;
11221
11222 reject_bad_reg (Rd);
11223 reject_bad_reg (Rn);
11224 reject_bad_reg (Rm);
11225
11226 inst.instruction |= Rd << 8;
11227 inst.instruction |= Rn << 16;
11228 inst.instruction |= Rm;
11229}
11230
c19d1205 11231static void
3eb17e6b 11232do_t_smc (void)
c19d1205
ZW
11233{
11234 unsigned int value = inst.reloc.exp.X_add_number;
11235 constraint (inst.reloc.exp.X_op != O_constant,
11236 _("expression too complex"));
11237 inst.reloc.type = BFD_RELOC_UNUSED;
11238 inst.instruction |= (value & 0xf000) >> 12;
11239 inst.instruction |= (value & 0x0ff0);
11240 inst.instruction |= (value & 0x000f) << 16;
11241}
b99bd4ef 11242
c19d1205 11243static void
3a21c15a 11244do_t_ssat_usat (int bias)
c19d1205 11245{
fdfde340
JM
11246 unsigned Rd, Rn;
11247
11248 Rd = inst.operands[0].reg;
11249 Rn = inst.operands[2].reg;
11250
11251 reject_bad_reg (Rd);
11252 reject_bad_reg (Rn);
11253
11254 inst.instruction |= Rd << 8;
3a21c15a 11255 inst.instruction |= inst.operands[1].imm - bias;
fdfde340 11256 inst.instruction |= Rn << 16;
b99bd4ef 11257
c19d1205 11258 if (inst.operands[3].present)
b99bd4ef 11259 {
3a21c15a
NC
11260 offsetT shift_amount = inst.reloc.exp.X_add_number;
11261
11262 inst.reloc.type = BFD_RELOC_UNUSED;
11263
c19d1205
ZW
11264 constraint (inst.reloc.exp.X_op != O_constant,
11265 _("expression too complex"));
b99bd4ef 11266
3a21c15a 11267 if (shift_amount != 0)
6189168b 11268 {
3a21c15a
NC
11269 constraint (shift_amount > 31,
11270 _("shift expression is too large"));
11271
c19d1205 11272 if (inst.operands[3].shift_kind == SHIFT_ASR)
3a21c15a
NC
11273 inst.instruction |= 0x00200000; /* sh bit. */
11274
11275 inst.instruction |= (shift_amount & 0x1c) << 10;
11276 inst.instruction |= (shift_amount & 0x03) << 6;
6189168b
NC
11277 }
11278 }
b99bd4ef 11279}
c921be7d 11280
3a21c15a
NC
11281static void
11282do_t_ssat (void)
11283{
11284 do_t_ssat_usat (1);
11285}
b99bd4ef 11286
0dd132b6 11287static void
c19d1205 11288do_t_ssat16 (void)
0dd132b6 11289{
fdfde340
JM
11290 unsigned Rd, Rn;
11291
11292 Rd = inst.operands[0].reg;
11293 Rn = inst.operands[2].reg;
11294
11295 reject_bad_reg (Rd);
11296 reject_bad_reg (Rn);
11297
11298 inst.instruction |= Rd << 8;
c19d1205 11299 inst.instruction |= inst.operands[1].imm - 1;
fdfde340 11300 inst.instruction |= Rn << 16;
c19d1205 11301}
0dd132b6 11302
c19d1205
ZW
11303static void
11304do_t_strex (void)
11305{
11306 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
11307 || inst.operands[2].postind || inst.operands[2].writeback
11308 || inst.operands[2].immisreg || inst.operands[2].shifted
11309 || inst.operands[2].negative,
01cfc07f 11310 BAD_ADDR_MODE);
0dd132b6 11311
5be8be5d
DG
11312 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
11313
c19d1205
ZW
11314 inst.instruction |= inst.operands[0].reg << 8;
11315 inst.instruction |= inst.operands[1].reg << 12;
11316 inst.instruction |= inst.operands[2].reg << 16;
11317 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
0dd132b6
NC
11318}
11319
b99bd4ef 11320static void
c19d1205 11321do_t_strexd (void)
b99bd4ef 11322{
c19d1205
ZW
11323 if (!inst.operands[2].present)
11324 inst.operands[2].reg = inst.operands[1].reg + 1;
b99bd4ef 11325
c19d1205
ZW
11326 constraint (inst.operands[0].reg == inst.operands[1].reg
11327 || inst.operands[0].reg == inst.operands[2].reg
f8a8e9d6 11328 || inst.operands[0].reg == inst.operands[3].reg,
c19d1205 11329 BAD_OVERLAP);
b99bd4ef 11330
c19d1205
ZW
11331 inst.instruction |= inst.operands[0].reg;
11332 inst.instruction |= inst.operands[1].reg << 12;
11333 inst.instruction |= inst.operands[2].reg << 8;
11334 inst.instruction |= inst.operands[3].reg << 16;
b99bd4ef
NC
11335}
11336
11337static void
c19d1205 11338do_t_sxtah (void)
b99bd4ef 11339{
fdfde340
JM
11340 unsigned Rd, Rn, Rm;
11341
11342 Rd = inst.operands[0].reg;
11343 Rn = inst.operands[1].reg;
11344 Rm = inst.operands[2].reg;
11345
11346 reject_bad_reg (Rd);
11347 reject_bad_reg (Rn);
11348 reject_bad_reg (Rm);
11349
11350 inst.instruction |= Rd << 8;
11351 inst.instruction |= Rn << 16;
11352 inst.instruction |= Rm;
c19d1205
ZW
11353 inst.instruction |= inst.operands[3].imm << 4;
11354}
b99bd4ef 11355
c19d1205
ZW
11356static void
11357do_t_sxth (void)
11358{
fdfde340
JM
11359 unsigned Rd, Rm;
11360
11361 Rd = inst.operands[0].reg;
11362 Rm = inst.operands[1].reg;
11363
11364 reject_bad_reg (Rd);
11365 reject_bad_reg (Rm);
c921be7d
NC
11366
11367 if (inst.instruction <= 0xffff
11368 && inst.size_req != 4
fdfde340 11369 && Rd <= 7 && Rm <= 7
c19d1205 11370 && (!inst.operands[2].present || inst.operands[2].imm == 0))
b99bd4ef 11371 {
c19d1205 11372 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM
11373 inst.instruction |= Rd;
11374 inst.instruction |= Rm << 3;
b99bd4ef 11375 }
c19d1205 11376 else if (unified_syntax)
b99bd4ef 11377 {
c19d1205
ZW
11378 if (inst.instruction <= 0xffff)
11379 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM
11380 inst.instruction |= Rd << 8;
11381 inst.instruction |= Rm;
c19d1205 11382 inst.instruction |= inst.operands[2].imm << 4;
b99bd4ef 11383 }
c19d1205 11384 else
b99bd4ef 11385 {
c19d1205
ZW
11386 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
11387 _("Thumb encoding does not support rotation"));
11388 constraint (1, BAD_HIREG);
b99bd4ef 11389 }
c19d1205 11390}
b99bd4ef 11391
c19d1205
ZW
11392static void
11393do_t_swi (void)
11394{
11395 inst.reloc.type = BFD_RELOC_ARM_SWI;
11396}
b99bd4ef 11397
92e90b6e
PB
11398static void
11399do_t_tb (void)
11400{
fdfde340 11401 unsigned Rn, Rm;
92e90b6e
PB
11402 int half;
11403
11404 half = (inst.instruction & 0x10) != 0;
e07e6e58 11405 set_it_insn_type_last ();
dfa9f0d5
PB
11406 constraint (inst.operands[0].immisreg,
11407 _("instruction requires register index"));
fdfde340
JM
11408
11409 Rn = inst.operands[0].reg;
11410 Rm = inst.operands[0].imm;
c921be7d 11411
fdfde340
JM
11412 constraint (Rn == REG_SP, BAD_SP);
11413 reject_bad_reg (Rm);
11414
92e90b6e
PB
11415 constraint (!half && inst.operands[0].shifted,
11416 _("instruction does not allow shifted index"));
fdfde340 11417 inst.instruction |= (Rn << 16) | Rm;
92e90b6e
PB
11418}
11419
c19d1205
ZW
11420static void
11421do_t_usat (void)
11422{
3a21c15a 11423 do_t_ssat_usat (0);
b99bd4ef
NC
11424}
11425
11426static void
c19d1205 11427do_t_usat16 (void)
b99bd4ef 11428{
fdfde340
JM
11429 unsigned Rd, Rn;
11430
11431 Rd = inst.operands[0].reg;
11432 Rn = inst.operands[2].reg;
11433
11434 reject_bad_reg (Rd);
11435 reject_bad_reg (Rn);
11436
11437 inst.instruction |= Rd << 8;
c19d1205 11438 inst.instruction |= inst.operands[1].imm;
fdfde340 11439 inst.instruction |= Rn << 16;
b99bd4ef 11440}
c19d1205 11441
5287ad62 11442/* Neon instruction encoder helpers. */
5f4273c7 11443
5287ad62 11444/* Encodings for the different types for various Neon opcodes. */
b99bd4ef 11445
5287ad62
JB
11446/* An "invalid" code for the following tables. */
11447#define N_INV -1u
11448
11449struct neon_tab_entry
b99bd4ef 11450{
5287ad62
JB
11451 unsigned integer;
11452 unsigned float_or_poly;
11453 unsigned scalar_or_imm;
11454};
5f4273c7 11455
5287ad62
JB
11456/* Map overloaded Neon opcodes to their respective encodings. */
11457#define NEON_ENC_TAB \
11458 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11459 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11460 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11461 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11462 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11463 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11464 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11465 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11466 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11467 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11468 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11469 /* Register variants of the following two instructions are encoded as
e07e6e58 11470 vcge / vcgt with the operands reversed. */ \
92559b5b
PB
11471 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11472 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
62f3b8c8
PB
11473 X(vfma, N_INV, 0x0000c10, N_INV), \
11474 X(vfms, N_INV, 0x0200c10, N_INV), \
5287ad62
JB
11475 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11476 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11477 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11478 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11479 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11480 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11481 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11482 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11483 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11484 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11485 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11486 X(vshl, 0x0000400, N_INV, 0x0800510), \
11487 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11488 X(vand, 0x0000110, N_INV, 0x0800030), \
11489 X(vbic, 0x0100110, N_INV, 0x0800030), \
11490 X(veor, 0x1000110, N_INV, N_INV), \
11491 X(vorn, 0x0300110, N_INV, 0x0800010), \
11492 X(vorr, 0x0200110, N_INV, 0x0800010), \
11493 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11494 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11495 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11496 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11497 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11498 X(vst1, 0x0000000, 0x0800000, N_INV), \
11499 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11500 X(vst2, 0x0000100, 0x0800100, N_INV), \
11501 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11502 X(vst3, 0x0000200, 0x0800200, N_INV), \
11503 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11504 X(vst4, 0x0000300, 0x0800300, N_INV), \
11505 X(vmovn, 0x1b20200, N_INV, N_INV), \
11506 X(vtrn, 0x1b20080, N_INV, N_INV), \
11507 X(vqmovn, 0x1b20200, N_INV, N_INV), \
037e8744
JB
11508 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11509 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
e6655fda
PB
11510 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11511 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
62f3b8c8
PB
11512 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11513 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
037e8744
JB
11514 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11515 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11516 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11517 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
5287ad62
JB
11518
11519enum neon_opc
11520{
11521#define X(OPC,I,F,S) N_MNEM_##OPC
11522NEON_ENC_TAB
11523#undef X
11524};
b99bd4ef 11525
5287ad62
JB
11526static const struct neon_tab_entry neon_enc_tab[] =
11527{
11528#define X(OPC,I,F,S) { (I), (F), (S) }
11529NEON_ENC_TAB
11530#undef X
11531};
b99bd4ef 11532
88714cb8
DG
11533/* Do not use these macros; instead, use NEON_ENCODE defined below. */
11534#define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11535#define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11536#define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11537#define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11538#define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11539#define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11540#define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11541#define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11542#define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11543#define NEON_ENC_SINGLE_(X) \
037e8744 11544 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
88714cb8 11545#define NEON_ENC_DOUBLE_(X) \
037e8744 11546 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
5287ad62 11547
88714cb8
DG
11548#define NEON_ENCODE(type, inst) \
11549 do \
11550 { \
11551 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
11552 inst.is_neon = 1; \
11553 } \
11554 while (0)
11555
11556#define check_neon_suffixes \
11557 do \
11558 { \
11559 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
11560 { \
11561 as_bad (_("invalid neon suffix for non neon instruction")); \
11562 return; \
11563 } \
11564 } \
11565 while (0)
11566
037e8744
JB
11567/* Define shapes for instruction operands. The following mnemonic characters
11568 are used in this table:
5287ad62 11569
037e8744 11570 F - VFP S<n> register
5287ad62
JB
11571 D - Neon D<n> register
11572 Q - Neon Q<n> register
11573 I - Immediate
11574 S - Scalar
11575 R - ARM register
11576 L - D<n> register list
5f4273c7 11577
037e8744
JB
11578 This table is used to generate various data:
11579 - enumerations of the form NS_DDR to be used as arguments to
11580 neon_select_shape.
11581 - a table classifying shapes into single, double, quad, mixed.
5f4273c7 11582 - a table used to drive neon_select_shape. */
b99bd4ef 11583
037e8744
JB
11584#define NEON_SHAPE_DEF \
11585 X(3, (D, D, D), DOUBLE), \
11586 X(3, (Q, Q, Q), QUAD), \
11587 X(3, (D, D, I), DOUBLE), \
11588 X(3, (Q, Q, I), QUAD), \
11589 X(3, (D, D, S), DOUBLE), \
11590 X(3, (Q, Q, S), QUAD), \
11591 X(2, (D, D), DOUBLE), \
11592 X(2, (Q, Q), QUAD), \
11593 X(2, (D, S), DOUBLE), \
11594 X(2, (Q, S), QUAD), \
11595 X(2, (D, R), DOUBLE), \
11596 X(2, (Q, R), QUAD), \
11597 X(2, (D, I), DOUBLE), \
11598 X(2, (Q, I), QUAD), \
11599 X(3, (D, L, D), DOUBLE), \
11600 X(2, (D, Q), MIXED), \
11601 X(2, (Q, D), MIXED), \
11602 X(3, (D, Q, I), MIXED), \
11603 X(3, (Q, D, I), MIXED), \
11604 X(3, (Q, D, D), MIXED), \
11605 X(3, (D, Q, Q), MIXED), \
11606 X(3, (Q, Q, D), MIXED), \
11607 X(3, (Q, D, S), MIXED), \
11608 X(3, (D, Q, S), MIXED), \
11609 X(4, (D, D, D, I), DOUBLE), \
11610 X(4, (Q, Q, Q, I), QUAD), \
11611 X(2, (F, F), SINGLE), \
11612 X(3, (F, F, F), SINGLE), \
11613 X(2, (F, I), SINGLE), \
11614 X(2, (F, D), MIXED), \
11615 X(2, (D, F), MIXED), \
11616 X(3, (F, F, I), MIXED), \
11617 X(4, (R, R, F, F), SINGLE), \
11618 X(4, (F, F, R, R), SINGLE), \
11619 X(3, (D, R, R), DOUBLE), \
11620 X(3, (R, R, D), DOUBLE), \
11621 X(2, (S, R), SINGLE), \
11622 X(2, (R, S), SINGLE), \
11623 X(2, (F, R), SINGLE), \
11624 X(2, (R, F), SINGLE)
11625
11626#define S2(A,B) NS_##A##B
11627#define S3(A,B,C) NS_##A##B##C
11628#define S4(A,B,C,D) NS_##A##B##C##D
11629
11630#define X(N, L, C) S##N L
11631
5287ad62
JB
11632enum neon_shape
11633{
037e8744
JB
11634 NEON_SHAPE_DEF,
11635 NS_NULL
5287ad62 11636};
b99bd4ef 11637
037e8744
JB
11638#undef X
11639#undef S2
11640#undef S3
11641#undef S4
11642
11643enum neon_shape_class
11644{
11645 SC_SINGLE,
11646 SC_DOUBLE,
11647 SC_QUAD,
11648 SC_MIXED
11649};
11650
11651#define X(N, L, C) SC_##C
11652
11653static enum neon_shape_class neon_shape_class[] =
11654{
11655 NEON_SHAPE_DEF
11656};
11657
11658#undef X
11659
11660enum neon_shape_el
11661{
11662 SE_F,
11663 SE_D,
11664 SE_Q,
11665 SE_I,
11666 SE_S,
11667 SE_R,
11668 SE_L
11669};
11670
11671/* Register widths of above. */
11672static unsigned neon_shape_el_size[] =
11673{
11674 32,
11675 64,
11676 128,
11677 0,
11678 32,
11679 32,
11680 0
11681};
11682
11683struct neon_shape_info
11684{
11685 unsigned els;
11686 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
11687};
11688
11689#define S2(A,B) { SE_##A, SE_##B }
11690#define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11691#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11692
11693#define X(N, L, C) { N, S##N L }
11694
11695static struct neon_shape_info neon_shape_tab[] =
11696{
11697 NEON_SHAPE_DEF
11698};
11699
11700#undef X
11701#undef S2
11702#undef S3
11703#undef S4
11704
5287ad62
JB
11705/* Bit masks used in type checking given instructions.
11706 'N_EQK' means the type must be the same as (or based on in some way) the key
11707 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11708 set, various other bits can be set as well in order to modify the meaning of
11709 the type constraint. */
11710
11711enum neon_type_mask
11712{
8e79c3df
CM
11713 N_S8 = 0x0000001,
11714 N_S16 = 0x0000002,
11715 N_S32 = 0x0000004,
11716 N_S64 = 0x0000008,
11717 N_U8 = 0x0000010,
11718 N_U16 = 0x0000020,
11719 N_U32 = 0x0000040,
11720 N_U64 = 0x0000080,
11721 N_I8 = 0x0000100,
11722 N_I16 = 0x0000200,
11723 N_I32 = 0x0000400,
11724 N_I64 = 0x0000800,
11725 N_8 = 0x0001000,
11726 N_16 = 0x0002000,
11727 N_32 = 0x0004000,
11728 N_64 = 0x0008000,
11729 N_P8 = 0x0010000,
11730 N_P16 = 0x0020000,
11731 N_F16 = 0x0040000,
11732 N_F32 = 0x0080000,
11733 N_F64 = 0x0100000,
c921be7d
NC
11734 N_KEY = 0x1000000, /* Key element (main type specifier). */
11735 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
8e79c3df 11736 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
c921be7d
NC
11737 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
11738 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
11739 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11740 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11741 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11742 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
11743 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
5287ad62 11744 N_UTYP = 0,
037e8744 11745 N_MAX_NONSPECIAL = N_F64
5287ad62
JB
11746};
11747
dcbf9037
JB
11748#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11749
5287ad62
JB
11750#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11751#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11752#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11753#define N_SUF_32 (N_SU_32 | N_F32)
11754#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11755#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11756
11757/* Pass this as the first type argument to neon_check_type to ignore types
11758 altogether. */
11759#define N_IGNORE_TYPE (N_KEY | N_EQK)
11760
037e8744
JB
11761/* Select a "shape" for the current instruction (describing register types or
11762 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11763 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11764 function of operand parsing, so this function doesn't need to be called.
11765 Shapes should be listed in order of decreasing length. */
5287ad62
JB
11766
11767static enum neon_shape
037e8744 11768neon_select_shape (enum neon_shape shape, ...)
5287ad62 11769{
037e8744
JB
11770 va_list ap;
11771 enum neon_shape first_shape = shape;
5287ad62
JB
11772
11773 /* Fix missing optional operands. FIXME: we don't know at this point how
11774 many arguments we should have, so this makes the assumption that we have
11775 > 1. This is true of all current Neon opcodes, I think, but may not be
11776 true in the future. */
11777 if (!inst.operands[1].present)
11778 inst.operands[1] = inst.operands[0];
11779
037e8744 11780 va_start (ap, shape);
5f4273c7 11781
21d799b5 11782 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
037e8744
JB
11783 {
11784 unsigned j;
11785 int matches = 1;
11786
11787 for (j = 0; j < neon_shape_tab[shape].els; j++)
11788 {
11789 if (!inst.operands[j].present)
11790 {
11791 matches = 0;
11792 break;
11793 }
11794
11795 switch (neon_shape_tab[shape].el[j])
11796 {
11797 case SE_F:
11798 if (!(inst.operands[j].isreg
11799 && inst.operands[j].isvec
11800 && inst.operands[j].issingle
11801 && !inst.operands[j].isquad))
11802 matches = 0;
11803 break;
11804
11805 case SE_D:
11806 if (!(inst.operands[j].isreg
11807 && inst.operands[j].isvec
11808 && !inst.operands[j].isquad
11809 && !inst.operands[j].issingle))
11810 matches = 0;
11811 break;
11812
11813 case SE_R:
11814 if (!(inst.operands[j].isreg
11815 && !inst.operands[j].isvec))
11816 matches = 0;
11817 break;
11818
11819 case SE_Q:
11820 if (!(inst.operands[j].isreg
11821 && inst.operands[j].isvec
11822 && inst.operands[j].isquad
11823 && !inst.operands[j].issingle))
11824 matches = 0;
11825 break;
11826
11827 case SE_I:
11828 if (!(!inst.operands[j].isreg
11829 && !inst.operands[j].isscalar))
11830 matches = 0;
11831 break;
11832
11833 case SE_S:
11834 if (!(!inst.operands[j].isreg
11835 && inst.operands[j].isscalar))
11836 matches = 0;
11837 break;
11838
11839 case SE_L:
11840 break;
11841 }
3fde54a2
JZ
11842 if (!matches)
11843 break;
037e8744
JB
11844 }
11845 if (matches)
5287ad62 11846 break;
037e8744 11847 }
5f4273c7 11848
037e8744 11849 va_end (ap);
5287ad62 11850
037e8744
JB
11851 if (shape == NS_NULL && first_shape != NS_NULL)
11852 first_error (_("invalid instruction shape"));
5287ad62 11853
037e8744
JB
11854 return shape;
11855}
5287ad62 11856
037e8744
JB
11857/* True if SHAPE is predominantly a quadword operation (most of the time, this
11858 means the Q bit should be set). */
11859
11860static int
11861neon_quad (enum neon_shape shape)
11862{
11863 return neon_shape_class[shape] == SC_QUAD;
5287ad62 11864}
037e8744 11865
5287ad62
JB
11866static void
11867neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
11868 unsigned *g_size)
11869{
11870 /* Allow modification to be made to types which are constrained to be
11871 based on the key element, based on bits set alongside N_EQK. */
11872 if ((typebits & N_EQK) != 0)
11873 {
11874 if ((typebits & N_HLF) != 0)
11875 *g_size /= 2;
11876 else if ((typebits & N_DBL) != 0)
11877 *g_size *= 2;
11878 if ((typebits & N_SGN) != 0)
11879 *g_type = NT_signed;
11880 else if ((typebits & N_UNS) != 0)
11881 *g_type = NT_unsigned;
11882 else if ((typebits & N_INT) != 0)
11883 *g_type = NT_integer;
11884 else if ((typebits & N_FLT) != 0)
11885 *g_type = NT_float;
dcbf9037
JB
11886 else if ((typebits & N_SIZ) != 0)
11887 *g_type = NT_untyped;
5287ad62
JB
11888 }
11889}
5f4273c7 11890
5287ad62
JB
11891/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11892 operand type, i.e. the single type specified in a Neon instruction when it
11893 is the only one given. */
11894
11895static struct neon_type_el
11896neon_type_promote (struct neon_type_el *key, unsigned thisarg)
11897{
11898 struct neon_type_el dest = *key;
5f4273c7 11899
9c2799c2 11900 gas_assert ((thisarg & N_EQK) != 0);
5f4273c7 11901
5287ad62
JB
11902 neon_modify_type_size (thisarg, &dest.type, &dest.size);
11903
11904 return dest;
11905}
11906
11907/* Convert Neon type and size into compact bitmask representation. */
11908
11909static enum neon_type_mask
11910type_chk_of_el_type (enum neon_el_type type, unsigned size)
11911{
11912 switch (type)
11913 {
11914 case NT_untyped:
11915 switch (size)
11916 {
11917 case 8: return N_8;
11918 case 16: return N_16;
11919 case 32: return N_32;
11920 case 64: return N_64;
11921 default: ;
11922 }
11923 break;
11924
11925 case NT_integer:
11926 switch (size)
11927 {
11928 case 8: return N_I8;
11929 case 16: return N_I16;
11930 case 32: return N_I32;
11931 case 64: return N_I64;
11932 default: ;
11933 }
11934 break;
11935
11936 case NT_float:
037e8744
JB
11937 switch (size)
11938 {
8e79c3df 11939 case 16: return N_F16;
037e8744
JB
11940 case 32: return N_F32;
11941 case 64: return N_F64;
11942 default: ;
11943 }
5287ad62
JB
11944 break;
11945
11946 case NT_poly:
11947 switch (size)
11948 {
11949 case 8: return N_P8;
11950 case 16: return N_P16;
11951 default: ;
11952 }
11953 break;
11954
11955 case NT_signed:
11956 switch (size)
11957 {
11958 case 8: return N_S8;
11959 case 16: return N_S16;
11960 case 32: return N_S32;
11961 case 64: return N_S64;
11962 default: ;
11963 }
11964 break;
11965
11966 case NT_unsigned:
11967 switch (size)
11968 {
11969 case 8: return N_U8;
11970 case 16: return N_U16;
11971 case 32: return N_U32;
11972 case 64: return N_U64;
11973 default: ;
11974 }
11975 break;
11976
11977 default: ;
11978 }
5f4273c7 11979
5287ad62
JB
11980 return N_UTYP;
11981}
11982
11983/* Convert compact Neon bitmask type representation to a type and size. Only
11984 handles the case where a single bit is set in the mask. */
11985
dcbf9037 11986static int
5287ad62
JB
11987el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
11988 enum neon_type_mask mask)
11989{
dcbf9037
JB
11990 if ((mask & N_EQK) != 0)
11991 return FAIL;
11992
5287ad62
JB
11993 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
11994 *size = 8;
dcbf9037 11995 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
5287ad62 11996 *size = 16;
dcbf9037 11997 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
5287ad62 11998 *size = 32;
037e8744 11999 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
5287ad62 12000 *size = 64;
dcbf9037
JB
12001 else
12002 return FAIL;
12003
5287ad62
JB
12004 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12005 *type = NT_signed;
dcbf9037 12006 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
5287ad62 12007 *type = NT_unsigned;
dcbf9037 12008 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
5287ad62 12009 *type = NT_integer;
dcbf9037 12010 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
5287ad62 12011 *type = NT_untyped;
dcbf9037 12012 else if ((mask & (N_P8 | N_P16)) != 0)
5287ad62 12013 *type = NT_poly;
037e8744 12014 else if ((mask & (N_F32 | N_F64)) != 0)
5287ad62 12015 *type = NT_float;
dcbf9037
JB
12016 else
12017 return FAIL;
5f4273c7 12018
dcbf9037 12019 return SUCCESS;
5287ad62
JB
12020}
12021
12022/* Modify a bitmask of allowed types. This is only needed for type
12023 relaxation. */
12024
12025static unsigned
12026modify_types_allowed (unsigned allowed, unsigned mods)
12027{
12028 unsigned size;
12029 enum neon_el_type type;
12030 unsigned destmask;
12031 int i;
5f4273c7 12032
5287ad62 12033 destmask = 0;
5f4273c7 12034
5287ad62
JB
12035 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12036 {
21d799b5
NC
12037 if (el_type_of_type_chk (&type, &size,
12038 (enum neon_type_mask) (allowed & i)) == SUCCESS)
dcbf9037
JB
12039 {
12040 neon_modify_type_size (mods, &type, &size);
12041 destmask |= type_chk_of_el_type (type, size);
12042 }
5287ad62 12043 }
5f4273c7 12044
5287ad62
JB
12045 return destmask;
12046}
12047
12048/* Check type and return type classification.
12049 The manual states (paraphrase): If one datatype is given, it indicates the
12050 type given in:
12051 - the second operand, if there is one
12052 - the operand, if there is no second operand
12053 - the result, if there are no operands.
12054 This isn't quite good enough though, so we use a concept of a "key" datatype
12055 which is set on a per-instruction basis, which is the one which matters when
12056 only one data type is written.
12057 Note: this function has side-effects (e.g. filling in missing operands). All
037e8744 12058 Neon instructions should call it before performing bit encoding. */
5287ad62
JB
12059
12060static struct neon_type_el
12061neon_check_type (unsigned els, enum neon_shape ns, ...)
12062{
12063 va_list ap;
12064 unsigned i, pass, key_el = 0;
12065 unsigned types[NEON_MAX_TYPE_ELS];
12066 enum neon_el_type k_type = NT_invtype;
12067 unsigned k_size = -1u;
12068 struct neon_type_el badtype = {NT_invtype, -1};
12069 unsigned key_allowed = 0;
12070
12071 /* Optional registers in Neon instructions are always (not) in operand 1.
12072 Fill in the missing operand here, if it was omitted. */
12073 if (els > 1 && !inst.operands[1].present)
12074 inst.operands[1] = inst.operands[0];
12075
12076 /* Suck up all the varargs. */
12077 va_start (ap, ns);
12078 for (i = 0; i < els; i++)
12079 {
12080 unsigned thisarg = va_arg (ap, unsigned);
12081 if (thisarg == N_IGNORE_TYPE)
12082 {
12083 va_end (ap);
12084 return badtype;
12085 }
12086 types[i] = thisarg;
12087 if ((thisarg & N_KEY) != 0)
12088 key_el = i;
12089 }
12090 va_end (ap);
12091
dcbf9037
JB
12092 if (inst.vectype.elems > 0)
12093 for (i = 0; i < els; i++)
12094 if (inst.operands[i].vectype.type != NT_invtype)
12095 {
12096 first_error (_("types specified in both the mnemonic and operands"));
12097 return badtype;
12098 }
12099
5287ad62
JB
12100 /* Duplicate inst.vectype elements here as necessary.
12101 FIXME: No idea if this is exactly the same as the ARM assembler,
12102 particularly when an insn takes one register and one non-register
12103 operand. */
12104 if (inst.vectype.elems == 1 && els > 1)
12105 {
12106 unsigned j;
12107 inst.vectype.elems = els;
12108 inst.vectype.el[key_el] = inst.vectype.el[0];
12109 for (j = 0; j < els; j++)
dcbf9037
JB
12110 if (j != key_el)
12111 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12112 types[j]);
12113 }
12114 else if (inst.vectype.elems == 0 && els > 0)
12115 {
12116 unsigned j;
12117 /* No types were given after the mnemonic, so look for types specified
12118 after each operand. We allow some flexibility here; as long as the
12119 "key" operand has a type, we can infer the others. */
12120 for (j = 0; j < els; j++)
12121 if (inst.operands[j].vectype.type != NT_invtype)
12122 inst.vectype.el[j] = inst.operands[j].vectype;
12123
12124 if (inst.operands[key_el].vectype.type != NT_invtype)
5287ad62 12125 {
dcbf9037
JB
12126 for (j = 0; j < els; j++)
12127 if (inst.operands[j].vectype.type == NT_invtype)
12128 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12129 types[j]);
12130 }
12131 else
12132 {
12133 first_error (_("operand types can't be inferred"));
12134 return badtype;
5287ad62
JB
12135 }
12136 }
12137 else if (inst.vectype.elems != els)
12138 {
dcbf9037 12139 first_error (_("type specifier has the wrong number of parts"));
5287ad62
JB
12140 return badtype;
12141 }
12142
12143 for (pass = 0; pass < 2; pass++)
12144 {
12145 for (i = 0; i < els; i++)
12146 {
12147 unsigned thisarg = types[i];
12148 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12149 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12150 enum neon_el_type g_type = inst.vectype.el[i].type;
12151 unsigned g_size = inst.vectype.el[i].size;
12152
12153 /* Decay more-specific signed & unsigned types to sign-insensitive
12154 integer types if sign-specific variants are unavailable. */
12155 if ((g_type == NT_signed || g_type == NT_unsigned)
12156 && (types_allowed & N_SU_ALL) == 0)
12157 g_type = NT_integer;
12158
12159 /* If only untyped args are allowed, decay any more specific types to
12160 them. Some instructions only care about signs for some element
12161 sizes, so handle that properly. */
12162 if ((g_size == 8 && (types_allowed & N_8) != 0)
12163 || (g_size == 16 && (types_allowed & N_16) != 0)
12164 || (g_size == 32 && (types_allowed & N_32) != 0)
12165 || (g_size == 64 && (types_allowed & N_64) != 0))
12166 g_type = NT_untyped;
12167
12168 if (pass == 0)
12169 {
12170 if ((thisarg & N_KEY) != 0)
12171 {
12172 k_type = g_type;
12173 k_size = g_size;
12174 key_allowed = thisarg & ~N_KEY;
12175 }
12176 }
12177 else
12178 {
037e8744
JB
12179 if ((thisarg & N_VFP) != 0)
12180 {
99b253c5
NC
12181 enum neon_shape_el regshape;
12182 unsigned regwidth, match;
12183
12184 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12185 if (ns == NS_NULL)
12186 {
12187 first_error (_("invalid instruction shape"));
12188 return badtype;
12189 }
12190 regshape = neon_shape_tab[ns].el[i];
12191 regwidth = neon_shape_el_size[regshape];
037e8744
JB
12192
12193 /* In VFP mode, operands must match register widths. If we
12194 have a key operand, use its width, else use the width of
12195 the current operand. */
12196 if (k_size != -1u)
12197 match = k_size;
12198 else
12199 match = g_size;
12200
12201 if (regwidth != match)
12202 {
12203 first_error (_("operand size must match register width"));
12204 return badtype;
12205 }
12206 }
5f4273c7 12207
5287ad62
JB
12208 if ((thisarg & N_EQK) == 0)
12209 {
12210 unsigned given_type = type_chk_of_el_type (g_type, g_size);
12211
12212 if ((given_type & types_allowed) == 0)
12213 {
dcbf9037 12214 first_error (_("bad type in Neon instruction"));
5287ad62
JB
12215 return badtype;
12216 }
12217 }
12218 else
12219 {
12220 enum neon_el_type mod_k_type = k_type;
12221 unsigned mod_k_size = k_size;
12222 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
12223 if (g_type != mod_k_type || g_size != mod_k_size)
12224 {
dcbf9037 12225 first_error (_("inconsistent types in Neon instruction"));
5287ad62
JB
12226 return badtype;
12227 }
12228 }
12229 }
12230 }
12231 }
12232
12233 return inst.vectype.el[key_el];
12234}
12235
037e8744 12236/* Neon-style VFP instruction forwarding. */
5287ad62 12237
037e8744
JB
12238/* Thumb VFP instructions have 0xE in the condition field. */
12239
12240static void
12241do_vfp_cond_or_thumb (void)
5287ad62 12242{
88714cb8
DG
12243 inst.is_neon = 1;
12244
5287ad62 12245 if (thumb_mode)
037e8744 12246 inst.instruction |= 0xe0000000;
5287ad62 12247 else
037e8744 12248 inst.instruction |= inst.cond << 28;
5287ad62
JB
12249}
12250
037e8744
JB
12251/* Look up and encode a simple mnemonic, for use as a helper function for the
12252 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12253 etc. It is assumed that operand parsing has already been done, and that the
12254 operands are in the form expected by the given opcode (this isn't necessarily
12255 the same as the form in which they were parsed, hence some massaging must
12256 take place before this function is called).
12257 Checks current arch version against that in the looked-up opcode. */
5287ad62 12258
037e8744
JB
12259static void
12260do_vfp_nsyn_opcode (const char *opname)
5287ad62 12261{
037e8744 12262 const struct asm_opcode *opcode;
5f4273c7 12263
21d799b5 12264 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
5287ad62 12265
037e8744
JB
12266 if (!opcode)
12267 abort ();
5287ad62 12268
037e8744
JB
12269 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
12270 thumb_mode ? *opcode->tvariant : *opcode->avariant),
12271 _(BAD_FPU));
5287ad62 12272
88714cb8
DG
12273 inst.is_neon = 1;
12274
037e8744
JB
12275 if (thumb_mode)
12276 {
12277 inst.instruction = opcode->tvalue;
12278 opcode->tencode ();
12279 }
12280 else
12281 {
12282 inst.instruction = (inst.cond << 28) | opcode->avalue;
12283 opcode->aencode ();
12284 }
12285}
5287ad62
JB
12286
12287static void
037e8744 12288do_vfp_nsyn_add_sub (enum neon_shape rs)
5287ad62 12289{
037e8744
JB
12290 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
12291
12292 if (rs == NS_FFF)
12293 {
12294 if (is_add)
12295 do_vfp_nsyn_opcode ("fadds");
12296 else
12297 do_vfp_nsyn_opcode ("fsubs");
12298 }
12299 else
12300 {
12301 if (is_add)
12302 do_vfp_nsyn_opcode ("faddd");
12303 else
12304 do_vfp_nsyn_opcode ("fsubd");
12305 }
12306}
12307
12308/* Check operand types to see if this is a VFP instruction, and if so call
12309 PFN (). */
12310
12311static int
12312try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
12313{
12314 enum neon_shape rs;
12315 struct neon_type_el et;
12316
12317 switch (args)
12318 {
12319 case 2:
12320 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
12321 et = neon_check_type (2, rs,
12322 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12323 break;
5f4273c7 12324
037e8744
JB
12325 case 3:
12326 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
12327 et = neon_check_type (3, rs,
12328 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12329 break;
12330
12331 default:
12332 abort ();
12333 }
12334
12335 if (et.type != NT_invtype)
12336 {
12337 pfn (rs);
12338 return SUCCESS;
12339 }
037e8744 12340
99b253c5 12341 inst.error = NULL;
037e8744
JB
12342 return FAIL;
12343}
12344
12345static void
12346do_vfp_nsyn_mla_mls (enum neon_shape rs)
12347{
12348 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
5f4273c7 12349
037e8744
JB
12350 if (rs == NS_FFF)
12351 {
12352 if (is_mla)
12353 do_vfp_nsyn_opcode ("fmacs");
12354 else
1ee69515 12355 do_vfp_nsyn_opcode ("fnmacs");
037e8744
JB
12356 }
12357 else
12358 {
12359 if (is_mla)
12360 do_vfp_nsyn_opcode ("fmacd");
12361 else
1ee69515 12362 do_vfp_nsyn_opcode ("fnmacd");
037e8744
JB
12363 }
12364}
12365
62f3b8c8
PB
12366static void
12367do_vfp_nsyn_fma_fms (enum neon_shape rs)
12368{
12369 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
12370
12371 if (rs == NS_FFF)
12372 {
12373 if (is_fma)
12374 do_vfp_nsyn_opcode ("ffmas");
12375 else
12376 do_vfp_nsyn_opcode ("ffnmas");
12377 }
12378 else
12379 {
12380 if (is_fma)
12381 do_vfp_nsyn_opcode ("ffmad");
12382 else
12383 do_vfp_nsyn_opcode ("ffnmad");
12384 }
12385}
12386
037e8744
JB
12387static void
12388do_vfp_nsyn_mul (enum neon_shape rs)
12389{
12390 if (rs == NS_FFF)
12391 do_vfp_nsyn_opcode ("fmuls");
12392 else
12393 do_vfp_nsyn_opcode ("fmuld");
12394}
12395
12396static void
12397do_vfp_nsyn_abs_neg (enum neon_shape rs)
12398{
12399 int is_neg = (inst.instruction & 0x80) != 0;
12400 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
12401
12402 if (rs == NS_FF)
12403 {
12404 if (is_neg)
12405 do_vfp_nsyn_opcode ("fnegs");
12406 else
12407 do_vfp_nsyn_opcode ("fabss");
12408 }
12409 else
12410 {
12411 if (is_neg)
12412 do_vfp_nsyn_opcode ("fnegd");
12413 else
12414 do_vfp_nsyn_opcode ("fabsd");
12415 }
12416}
12417
12418/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12419 insns belong to Neon, and are handled elsewhere. */
12420
12421static void
12422do_vfp_nsyn_ldm_stm (int is_dbmode)
12423{
12424 int is_ldm = (inst.instruction & (1 << 20)) != 0;
12425 if (is_ldm)
12426 {
12427 if (is_dbmode)
12428 do_vfp_nsyn_opcode ("fldmdbs");
12429 else
12430 do_vfp_nsyn_opcode ("fldmias");
12431 }
12432 else
12433 {
12434 if (is_dbmode)
12435 do_vfp_nsyn_opcode ("fstmdbs");
12436 else
12437 do_vfp_nsyn_opcode ("fstmias");
12438 }
12439}
12440
037e8744
JB
12441static void
12442do_vfp_nsyn_sqrt (void)
12443{
12444 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
12445 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 12446
037e8744
JB
12447 if (rs == NS_FF)
12448 do_vfp_nsyn_opcode ("fsqrts");
12449 else
12450 do_vfp_nsyn_opcode ("fsqrtd");
12451}
12452
12453static void
12454do_vfp_nsyn_div (void)
12455{
12456 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
12457 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
12458 N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 12459
037e8744
JB
12460 if (rs == NS_FFF)
12461 do_vfp_nsyn_opcode ("fdivs");
12462 else
12463 do_vfp_nsyn_opcode ("fdivd");
12464}
12465
12466static void
12467do_vfp_nsyn_nmul (void)
12468{
12469 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
12470 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
12471 N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 12472
037e8744
JB
12473 if (rs == NS_FFF)
12474 {
88714cb8 12475 NEON_ENCODE (SINGLE, inst);
037e8744
JB
12476 do_vfp_sp_dyadic ();
12477 }
12478 else
12479 {
88714cb8 12480 NEON_ENCODE (DOUBLE, inst);
037e8744
JB
12481 do_vfp_dp_rd_rn_rm ();
12482 }
12483 do_vfp_cond_or_thumb ();
12484}
12485
12486static void
12487do_vfp_nsyn_cmp (void)
12488{
12489 if (inst.operands[1].isreg)
12490 {
12491 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
12492 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 12493
037e8744
JB
12494 if (rs == NS_FF)
12495 {
88714cb8 12496 NEON_ENCODE (SINGLE, inst);
037e8744
JB
12497 do_vfp_sp_monadic ();
12498 }
12499 else
12500 {
88714cb8 12501 NEON_ENCODE (DOUBLE, inst);
037e8744
JB
12502 do_vfp_dp_rd_rm ();
12503 }
12504 }
12505 else
12506 {
12507 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
12508 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
12509
12510 switch (inst.instruction & 0x0fffffff)
12511 {
12512 case N_MNEM_vcmp:
12513 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
12514 break;
12515 case N_MNEM_vcmpe:
12516 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
12517 break;
12518 default:
12519 abort ();
12520 }
5f4273c7 12521
037e8744
JB
12522 if (rs == NS_FI)
12523 {
88714cb8 12524 NEON_ENCODE (SINGLE, inst);
037e8744
JB
12525 do_vfp_sp_compare_z ();
12526 }
12527 else
12528 {
88714cb8 12529 NEON_ENCODE (DOUBLE, inst);
037e8744
JB
12530 do_vfp_dp_rd ();
12531 }
12532 }
12533 do_vfp_cond_or_thumb ();
12534}
12535
12536static void
12537nsyn_insert_sp (void)
12538{
12539 inst.operands[1] = inst.operands[0];
12540 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
fdfde340 12541 inst.operands[0].reg = REG_SP;
037e8744
JB
12542 inst.operands[0].isreg = 1;
12543 inst.operands[0].writeback = 1;
12544 inst.operands[0].present = 1;
12545}
12546
12547static void
12548do_vfp_nsyn_push (void)
12549{
12550 nsyn_insert_sp ();
12551 if (inst.operands[1].issingle)
12552 do_vfp_nsyn_opcode ("fstmdbs");
12553 else
12554 do_vfp_nsyn_opcode ("fstmdbd");
12555}
12556
12557static void
12558do_vfp_nsyn_pop (void)
12559{
12560 nsyn_insert_sp ();
12561 if (inst.operands[1].issingle)
22b5b651 12562 do_vfp_nsyn_opcode ("fldmias");
037e8744 12563 else
22b5b651 12564 do_vfp_nsyn_opcode ("fldmiad");
037e8744
JB
12565}
12566
12567/* Fix up Neon data-processing instructions, ORing in the correct bits for
12568 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12569
88714cb8
DG
12570static void
12571neon_dp_fixup (struct arm_it* insn)
037e8744 12572{
88714cb8
DG
12573 unsigned int i = insn->instruction;
12574 insn->is_neon = 1;
12575
037e8744
JB
12576 if (thumb_mode)
12577 {
12578 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12579 if (i & (1 << 24))
12580 i |= 1 << 28;
5f4273c7 12581
037e8744 12582 i &= ~(1 << 24);
5f4273c7 12583
037e8744
JB
12584 i |= 0xef000000;
12585 }
12586 else
12587 i |= 0xf2000000;
5f4273c7 12588
88714cb8 12589 insn->instruction = i;
037e8744
JB
12590}
12591
12592/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12593 (0, 1, 2, 3). */
12594
12595static unsigned
12596neon_logbits (unsigned x)
12597{
12598 return ffs (x) - 4;
12599}
12600
12601#define LOW4(R) ((R) & 0xf)
12602#define HI1(R) (((R) >> 4) & 1)
12603
12604/* Encode insns with bit pattern:
12605
12606 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12607 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
5f4273c7 12608
037e8744
JB
12609 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12610 different meaning for some instruction. */
12611
12612static void
12613neon_three_same (int isquad, int ubit, int size)
12614{
12615 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12616 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12617 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12618 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12619 inst.instruction |= LOW4 (inst.operands[2].reg);
12620 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
12621 inst.instruction |= (isquad != 0) << 6;
12622 inst.instruction |= (ubit != 0) << 24;
12623 if (size != -1)
12624 inst.instruction |= neon_logbits (size) << 20;
5f4273c7 12625
88714cb8 12626 neon_dp_fixup (&inst);
037e8744
JB
12627}
12628
12629/* Encode instructions of the form:
12630
12631 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12632 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
5287ad62
JB
12633
12634 Don't write size if SIZE == -1. */
12635
12636static void
12637neon_two_same (int qbit, int ubit, int size)
12638{
12639 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12640 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12641 inst.instruction |= LOW4 (inst.operands[1].reg);
12642 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12643 inst.instruction |= (qbit != 0) << 6;
12644 inst.instruction |= (ubit != 0) << 24;
12645
12646 if (size != -1)
12647 inst.instruction |= neon_logbits (size) << 18;
12648
88714cb8 12649 neon_dp_fixup (&inst);
5287ad62
JB
12650}
12651
12652/* Neon instruction encoders, in approximate order of appearance. */
12653
12654static void
12655do_neon_dyadic_i_su (void)
12656{
037e8744 12657 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB
12658 struct neon_type_el et = neon_check_type (3, rs,
12659 N_EQK, N_EQK, N_SU_32 | N_KEY);
037e8744 12660 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB
12661}
12662
12663static void
12664do_neon_dyadic_i64_su (void)
12665{
037e8744 12666 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB
12667 struct neon_type_el et = neon_check_type (3, rs,
12668 N_EQK, N_EQK, N_SU_ALL | N_KEY);
037e8744 12669 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB
12670}
12671
12672static void
12673neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
12674 unsigned immbits)
12675{
12676 unsigned size = et.size >> 3;
12677 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12678 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12679 inst.instruction |= LOW4 (inst.operands[1].reg);
12680 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12681 inst.instruction |= (isquad != 0) << 6;
12682 inst.instruction |= immbits << 16;
12683 inst.instruction |= (size >> 3) << 7;
12684 inst.instruction |= (size & 0x7) << 19;
12685 if (write_ubit)
12686 inst.instruction |= (uval != 0) << 24;
12687
88714cb8 12688 neon_dp_fixup (&inst);
5287ad62
JB
12689}
12690
12691static void
12692do_neon_shl_imm (void)
12693{
12694 if (!inst.operands[2].isreg)
12695 {
037e8744 12696 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62 12697 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
88714cb8 12698 NEON_ENCODE (IMMED, inst);
037e8744 12699 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
5287ad62
JB
12700 }
12701 else
12702 {
037e8744 12703 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB
12704 struct neon_type_el et = neon_check_type (3, rs,
12705 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
627907b7
JB
12706 unsigned int tmp;
12707
12708 /* VSHL/VQSHL 3-register variants have syntax such as:
12709 vshl.xx Dd, Dm, Dn
12710 whereas other 3-register operations encoded by neon_three_same have
12711 syntax like:
12712 vadd.xx Dd, Dn, Dm
12713 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12714 here. */
12715 tmp = inst.operands[2].reg;
12716 inst.operands[2].reg = inst.operands[1].reg;
12717 inst.operands[1].reg = tmp;
88714cb8 12718 NEON_ENCODE (INTEGER, inst);
037e8744 12719 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB
12720 }
12721}
12722
12723static void
12724do_neon_qshl_imm (void)
12725{
12726 if (!inst.operands[2].isreg)
12727 {
037e8744 12728 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62 12729 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
627907b7 12730
88714cb8 12731 NEON_ENCODE (IMMED, inst);
037e8744 12732 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
5287ad62
JB
12733 inst.operands[2].imm);
12734 }
12735 else
12736 {
037e8744 12737 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB
12738 struct neon_type_el et = neon_check_type (3, rs,
12739 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
627907b7
JB
12740 unsigned int tmp;
12741
12742 /* See note in do_neon_shl_imm. */
12743 tmp = inst.operands[2].reg;
12744 inst.operands[2].reg = inst.operands[1].reg;
12745 inst.operands[1].reg = tmp;
88714cb8 12746 NEON_ENCODE (INTEGER, inst);
037e8744 12747 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB
12748 }
12749}
12750
627907b7
JB
12751static void
12752do_neon_rshl (void)
12753{
12754 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12755 struct neon_type_el et = neon_check_type (3, rs,
12756 N_EQK, N_EQK, N_SU_ALL | N_KEY);
12757 unsigned int tmp;
12758
12759 tmp = inst.operands[2].reg;
12760 inst.operands[2].reg = inst.operands[1].reg;
12761 inst.operands[1].reg = tmp;
12762 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
12763}
12764
5287ad62
JB
12765static int
12766neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
12767{
036dc3f7
PB
12768 /* Handle .I8 pseudo-instructions. */
12769 if (size == 8)
5287ad62 12770 {
5287ad62
JB
12771 /* Unfortunately, this will make everything apart from zero out-of-range.
12772 FIXME is this the intended semantics? There doesn't seem much point in
12773 accepting .I8 if so. */
12774 immediate |= immediate << 8;
12775 size = 16;
036dc3f7
PB
12776 }
12777
12778 if (size >= 32)
12779 {
12780 if (immediate == (immediate & 0x000000ff))
12781 {
12782 *immbits = immediate;
12783 return 0x1;
12784 }
12785 else if (immediate == (immediate & 0x0000ff00))
12786 {
12787 *immbits = immediate >> 8;
12788 return 0x3;
12789 }
12790 else if (immediate == (immediate & 0x00ff0000))
12791 {
12792 *immbits = immediate >> 16;
12793 return 0x5;
12794 }
12795 else if (immediate == (immediate & 0xff000000))
12796 {
12797 *immbits = immediate >> 24;
12798 return 0x7;
12799 }
12800 if ((immediate & 0xffff) != (immediate >> 16))
12801 goto bad_immediate;
12802 immediate &= 0xffff;
5287ad62
JB
12803 }
12804
12805 if (immediate == (immediate & 0x000000ff))
12806 {
12807 *immbits = immediate;
036dc3f7 12808 return 0x9;
5287ad62
JB
12809 }
12810 else if (immediate == (immediate & 0x0000ff00))
12811 {
12812 *immbits = immediate >> 8;
036dc3f7 12813 return 0xb;
5287ad62
JB
12814 }
12815
12816 bad_immediate:
dcbf9037 12817 first_error (_("immediate value out of range"));
5287ad62
JB
12818 return FAIL;
12819}
12820
12821/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12822 A, B, C, D. */
12823
12824static int
12825neon_bits_same_in_bytes (unsigned imm)
12826{
12827 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
12828 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
12829 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
12830 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
12831}
12832
12833/* For immediate of above form, return 0bABCD. */
12834
12835static unsigned
12836neon_squash_bits (unsigned imm)
12837{
12838 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
12839 | ((imm & 0x01000000) >> 21);
12840}
12841
136da414 12842/* Compress quarter-float representation to 0b...000 abcdefgh. */
5287ad62
JB
12843
12844static unsigned
12845neon_qfloat_bits (unsigned imm)
12846{
136da414 12847 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
5287ad62
JB
12848}
12849
12850/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12851 the instruction. *OP is passed as the initial value of the op field, and
12852 may be set to a different value depending on the constant (i.e.
12853 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
5f4273c7 12854 MVN). If the immediate looks like a repeated pattern then also
036dc3f7 12855 try smaller element sizes. */
5287ad62
JB
12856
12857static int
c96612cc
JB
12858neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
12859 unsigned *immbits, int *op, int size,
12860 enum neon_el_type type)
5287ad62 12861{
c96612cc
JB
12862 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12863 float. */
12864 if (type == NT_float && !float_p)
12865 return FAIL;
12866
136da414
JB
12867 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
12868 {
12869 if (size != 32 || *op == 1)
12870 return FAIL;
12871 *immbits = neon_qfloat_bits (immlo);
12872 return 0xf;
12873 }
036dc3f7
PB
12874
12875 if (size == 64)
5287ad62 12876 {
036dc3f7
PB
12877 if (neon_bits_same_in_bytes (immhi)
12878 && neon_bits_same_in_bytes (immlo))
12879 {
12880 if (*op == 1)
12881 return FAIL;
12882 *immbits = (neon_squash_bits (immhi) << 4)
12883 | neon_squash_bits (immlo);
12884 *op = 1;
12885 return 0xe;
12886 }
12887
12888 if (immhi != immlo)
12889 return FAIL;
5287ad62 12890 }
036dc3f7
PB
12891
12892 if (size >= 32)
5287ad62 12893 {
036dc3f7
PB
12894 if (immlo == (immlo & 0x000000ff))
12895 {
12896 *immbits = immlo;
12897 return 0x0;
12898 }
12899 else if (immlo == (immlo & 0x0000ff00))
12900 {
12901 *immbits = immlo >> 8;
12902 return 0x2;
12903 }
12904 else if (immlo == (immlo & 0x00ff0000))
12905 {
12906 *immbits = immlo >> 16;
12907 return 0x4;
12908 }
12909 else if (immlo == (immlo & 0xff000000))
12910 {
12911 *immbits = immlo >> 24;
12912 return 0x6;
12913 }
12914 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
12915 {
12916 *immbits = (immlo >> 8) & 0xff;
12917 return 0xc;
12918 }
12919 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
12920 {
12921 *immbits = (immlo >> 16) & 0xff;
12922 return 0xd;
12923 }
12924
12925 if ((immlo & 0xffff) != (immlo >> 16))
12926 return FAIL;
12927 immlo &= 0xffff;
5287ad62 12928 }
036dc3f7
PB
12929
12930 if (size >= 16)
5287ad62 12931 {
036dc3f7
PB
12932 if (immlo == (immlo & 0x000000ff))
12933 {
12934 *immbits = immlo;
12935 return 0x8;
12936 }
12937 else if (immlo == (immlo & 0x0000ff00))
12938 {
12939 *immbits = immlo >> 8;
12940 return 0xa;
12941 }
12942
12943 if ((immlo & 0xff) != (immlo >> 8))
12944 return FAIL;
12945 immlo &= 0xff;
5287ad62 12946 }
036dc3f7
PB
12947
12948 if (immlo == (immlo & 0x000000ff))
5287ad62 12949 {
036dc3f7
PB
12950 /* Don't allow MVN with 8-bit immediate. */
12951 if (*op == 1)
12952 return FAIL;
12953 *immbits = immlo;
12954 return 0xe;
5287ad62 12955 }
5287ad62
JB
12956
12957 return FAIL;
12958}
12959
12960/* Write immediate bits [7:0] to the following locations:
12961
12962 |28/24|23 19|18 16|15 4|3 0|
12963 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
12964
12965 This function is used by VMOV/VMVN/VORR/VBIC. */
12966
12967static void
12968neon_write_immbits (unsigned immbits)
12969{
12970 inst.instruction |= immbits & 0xf;
12971 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
12972 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
12973}
12974
12975/* Invert low-order SIZE bits of XHI:XLO. */
12976
12977static void
12978neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
12979{
12980 unsigned immlo = xlo ? *xlo : 0;
12981 unsigned immhi = xhi ? *xhi : 0;
12982
12983 switch (size)
12984 {
12985 case 8:
12986 immlo = (~immlo) & 0xff;
12987 break;
12988
12989 case 16:
12990 immlo = (~immlo) & 0xffff;
12991 break;
12992
12993 case 64:
12994 immhi = (~immhi) & 0xffffffff;
12995 /* fall through. */
12996
12997 case 32:
12998 immlo = (~immlo) & 0xffffffff;
12999 break;
13000
13001 default:
13002 abort ();
13003 }
13004
13005 if (xlo)
13006 *xlo = immlo;
13007
13008 if (xhi)
13009 *xhi = immhi;
13010}
13011
13012static void
13013do_neon_logic (void)
13014{
13015 if (inst.operands[2].present && inst.operands[2].isreg)
13016 {
037e8744 13017 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB
13018 neon_check_type (3, rs, N_IGNORE_TYPE);
13019 /* U bit and size field were set as part of the bitmask. */
88714cb8 13020 NEON_ENCODE (INTEGER, inst);
037e8744 13021 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB
13022 }
13023 else
13024 {
4316f0d2
DG
13025 const int three_ops_form = (inst.operands[2].present
13026 && !inst.operands[2].isreg);
13027 const int immoperand = (three_ops_form ? 2 : 1);
13028 enum neon_shape rs = (three_ops_form
13029 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13030 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
037e8744
JB
13031 struct neon_type_el et = neon_check_type (2, rs,
13032 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
21d799b5 13033 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
5287ad62
JB
13034 unsigned immbits;
13035 int cmode;
5f4273c7 13036
5287ad62
JB
13037 if (et.type == NT_invtype)
13038 return;
5f4273c7 13039
4316f0d2
DG
13040 if (three_ops_form)
13041 constraint (inst.operands[0].reg != inst.operands[1].reg,
13042 _("first and second operands shall be the same register"));
13043
88714cb8 13044 NEON_ENCODE (IMMED, inst);
5287ad62 13045
4316f0d2 13046 immbits = inst.operands[immoperand].imm;
036dc3f7
PB
13047 if (et.size == 64)
13048 {
13049 /* .i64 is a pseudo-op, so the immediate must be a repeating
13050 pattern. */
4316f0d2
DG
13051 if (immbits != (inst.operands[immoperand].regisimm ?
13052 inst.operands[immoperand].reg : 0))
036dc3f7
PB
13053 {
13054 /* Set immbits to an invalid constant. */
13055 immbits = 0xdeadbeef;
13056 }
13057 }
13058
5287ad62
JB
13059 switch (opcode)
13060 {
13061 case N_MNEM_vbic:
036dc3f7 13062 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
5287ad62 13063 break;
5f4273c7 13064
5287ad62 13065 case N_MNEM_vorr:
036dc3f7 13066 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
5287ad62 13067 break;
5f4273c7 13068
5287ad62
JB
13069 case N_MNEM_vand:
13070 /* Pseudo-instruction for VBIC. */
5287ad62
JB
13071 neon_invert_size (&immbits, 0, et.size);
13072 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13073 break;
5f4273c7 13074
5287ad62
JB
13075 case N_MNEM_vorn:
13076 /* Pseudo-instruction for VORR. */
5287ad62
JB
13077 neon_invert_size (&immbits, 0, et.size);
13078 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13079 break;
5f4273c7 13080
5287ad62
JB
13081 default:
13082 abort ();
13083 }
13084
13085 if (cmode == FAIL)
13086 return;
13087
037e8744 13088 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB
13089 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13090 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13091 inst.instruction |= cmode << 8;
13092 neon_write_immbits (immbits);
5f4273c7 13093
88714cb8 13094 neon_dp_fixup (&inst);
5287ad62
JB
13095 }
13096}
13097
13098static void
13099do_neon_bitfield (void)
13100{
037e8744 13101 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
dcbf9037 13102 neon_check_type (3, rs, N_IGNORE_TYPE);
037e8744 13103 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB
13104}
13105
13106static void
dcbf9037
JB
13107neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13108 unsigned destbits)
5287ad62 13109{
037e8744 13110 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
dcbf9037
JB
13111 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13112 types | N_KEY);
5287ad62
JB
13113 if (et.type == NT_float)
13114 {
88714cb8 13115 NEON_ENCODE (FLOAT, inst);
037e8744 13116 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB
13117 }
13118 else
13119 {
88714cb8 13120 NEON_ENCODE (INTEGER, inst);
037e8744 13121 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
5287ad62
JB
13122 }
13123}
13124
13125static void
13126do_neon_dyadic_if_su (void)
13127{
dcbf9037 13128 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
5287ad62
JB
13129}
13130
13131static void
13132do_neon_dyadic_if_su_d (void)
13133{
13134 /* This version only allow D registers, but that constraint is enforced during
13135 operand parsing so we don't need to do anything extra here. */
dcbf9037 13136 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
5287ad62
JB
13137}
13138
5287ad62
JB
13139static void
13140do_neon_dyadic_if_i_d (void)
13141{
428e3f1f
PB
13142 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13143 affected if we specify unsigned args. */
13144 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
5287ad62
JB
13145}
13146
037e8744
JB
13147enum vfp_or_neon_is_neon_bits
13148{
13149 NEON_CHECK_CC = 1,
13150 NEON_CHECK_ARCH = 2
13151};
13152
13153/* Call this function if an instruction which may have belonged to the VFP or
13154 Neon instruction sets, but turned out to be a Neon instruction (due to the
13155 operand types involved, etc.). We have to check and/or fix-up a couple of
13156 things:
13157
13158 - Make sure the user hasn't attempted to make a Neon instruction
13159 conditional.
13160 - Alter the value in the condition code field if necessary.
13161 - Make sure that the arch supports Neon instructions.
13162
13163 Which of these operations take place depends on bits from enum
13164 vfp_or_neon_is_neon_bits.
13165
13166 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13167 current instruction's condition is COND_ALWAYS, the condition field is
13168 changed to inst.uncond_value. This is necessary because instructions shared
13169 between VFP and Neon may be conditional for the VFP variants only, and the
13170 unconditional Neon version must have, e.g., 0xF in the condition field. */
13171
13172static int
13173vfp_or_neon_is_neon (unsigned check)
13174{
13175 /* Conditions are always legal in Thumb mode (IT blocks). */
13176 if (!thumb_mode && (check & NEON_CHECK_CC))
13177 {
13178 if (inst.cond != COND_ALWAYS)
13179 {
13180 first_error (_(BAD_COND));
13181 return FAIL;
13182 }
13183 if (inst.uncond_value != -1)
13184 inst.instruction |= inst.uncond_value << 28;
13185 }
5f4273c7 13186
037e8744
JB
13187 if ((check & NEON_CHECK_ARCH)
13188 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
13189 {
13190 first_error (_(BAD_FPU));
13191 return FAIL;
13192 }
5f4273c7 13193
037e8744
JB
13194 return SUCCESS;
13195}
13196
5287ad62
JB
13197static void
13198do_neon_addsub_if_i (void)
13199{
037e8744
JB
13200 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
13201 return;
13202
13203 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13204 return;
13205
5287ad62
JB
13206 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13207 affected if we specify unsigned args. */
dcbf9037 13208 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
5287ad62
JB
13209}
13210
13211/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13212 result to be:
13213 V<op> A,B (A is operand 0, B is operand 2)
13214 to mean:
13215 V<op> A,B,A
13216 not:
13217 V<op> A,B,B
13218 so handle that case specially. */
13219
13220static void
13221neon_exchange_operands (void)
13222{
13223 void *scratch = alloca (sizeof (inst.operands[0]));
13224 if (inst.operands[1].present)
13225 {
13226 /* Swap operands[1] and operands[2]. */
13227 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
13228 inst.operands[1] = inst.operands[2];
13229 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
13230 }
13231 else
13232 {
13233 inst.operands[1] = inst.operands[2];
13234 inst.operands[2] = inst.operands[0];
13235 }
13236}
13237
13238static void
13239neon_compare (unsigned regtypes, unsigned immtypes, int invert)
13240{
13241 if (inst.operands[2].isreg)
13242 {
13243 if (invert)
13244 neon_exchange_operands ();
dcbf9037 13245 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
5287ad62
JB
13246 }
13247 else
13248 {
037e8744 13249 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
dcbf9037
JB
13250 struct neon_type_el et = neon_check_type (2, rs,
13251 N_EQK | N_SIZ, immtypes | N_KEY);
5287ad62 13252
88714cb8 13253 NEON_ENCODE (IMMED, inst);
5287ad62
JB
13254 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13255 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13256 inst.instruction |= LOW4 (inst.operands[1].reg);
13257 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 13258 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB
13259 inst.instruction |= (et.type == NT_float) << 10;
13260 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 13261
88714cb8 13262 neon_dp_fixup (&inst);
5287ad62
JB
13263 }
13264}
13265
13266static void
13267do_neon_cmp (void)
13268{
13269 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
13270}
13271
13272static void
13273do_neon_cmp_inv (void)
13274{
13275 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
13276}
13277
13278static void
13279do_neon_ceq (void)
13280{
13281 neon_compare (N_IF_32, N_IF_32, FALSE);
13282}
13283
13284/* For multiply instructions, we have the possibility of 16-bit or 32-bit
13285 scalars, which are encoded in 5 bits, M : Rm.
13286 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13287 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13288 index in M. */
13289
13290static unsigned
13291neon_scalar_for_mul (unsigned scalar, unsigned elsize)
13292{
dcbf9037
JB
13293 unsigned regno = NEON_SCALAR_REG (scalar);
13294 unsigned elno = NEON_SCALAR_INDEX (scalar);
5287ad62
JB
13295
13296 switch (elsize)
13297 {
13298 case 16:
13299 if (regno > 7 || elno > 3)
13300 goto bad_scalar;
13301 return regno | (elno << 3);
5f4273c7 13302
5287ad62
JB
13303 case 32:
13304 if (regno > 15 || elno > 1)
13305 goto bad_scalar;
13306 return regno | (elno << 4);
13307
13308 default:
13309 bad_scalar:
dcbf9037 13310 first_error (_("scalar out of range for multiply instruction"));
5287ad62
JB
13311 }
13312
13313 return 0;
13314}
13315
13316/* Encode multiply / multiply-accumulate scalar instructions. */
13317
13318static void
13319neon_mul_mac (struct neon_type_el et, int ubit)
13320{
dcbf9037
JB
13321 unsigned scalar;
13322
13323 /* Give a more helpful error message if we have an invalid type. */
13324 if (et.type == NT_invtype)
13325 return;
5f4273c7 13326
dcbf9037 13327 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
5287ad62
JB
13328 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13329 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13330 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13331 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13332 inst.instruction |= LOW4 (scalar);
13333 inst.instruction |= HI1 (scalar) << 5;
13334 inst.instruction |= (et.type == NT_float) << 8;
13335 inst.instruction |= neon_logbits (et.size) << 20;
13336 inst.instruction |= (ubit != 0) << 24;
13337
88714cb8 13338 neon_dp_fixup (&inst);
5287ad62
JB
13339}
13340
13341static void
13342do_neon_mac_maybe_scalar (void)
13343{
037e8744
JB
13344 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
13345 return;
13346
13347 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13348 return;
13349
5287ad62
JB
13350 if (inst.operands[2].isscalar)
13351 {
037e8744 13352 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
5287ad62
JB
13353 struct neon_type_el et = neon_check_type (3, rs,
13354 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
88714cb8 13355 NEON_ENCODE (SCALAR, inst);
037e8744 13356 neon_mul_mac (et, neon_quad (rs));
5287ad62
JB
13357 }
13358 else
428e3f1f
PB
13359 {
13360 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13361 affected if we specify unsigned args. */
13362 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13363 }
5287ad62
JB
13364}
13365
62f3b8c8
PB
13366static void
13367do_neon_fmac (void)
13368{
13369 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
13370 return;
13371
13372 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13373 return;
13374
13375 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13376}
13377
5287ad62
JB
13378static void
13379do_neon_tst (void)
13380{
037e8744 13381 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB
13382 struct neon_type_el et = neon_check_type (3, rs,
13383 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
037e8744 13384 neon_three_same (neon_quad (rs), 0, et.size);
5287ad62
JB
13385}
13386
13387/* VMUL with 3 registers allows the P8 type. The scalar version supports the
13388 same types as the MAC equivalents. The polynomial type for this instruction
13389 is encoded the same as the integer type. */
13390
13391static void
13392do_neon_mul (void)
13393{
037e8744
JB
13394 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
13395 return;
13396
13397 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13398 return;
13399
5287ad62
JB
13400 if (inst.operands[2].isscalar)
13401 do_neon_mac_maybe_scalar ();
13402 else
dcbf9037 13403 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
5287ad62
JB
13404}
13405
13406static void
13407do_neon_qdmulh (void)
13408{
13409 if (inst.operands[2].isscalar)
13410 {
037e8744 13411 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
5287ad62
JB
13412 struct neon_type_el et = neon_check_type (3, rs,
13413 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
88714cb8 13414 NEON_ENCODE (SCALAR, inst);
037e8744 13415 neon_mul_mac (et, neon_quad (rs));
5287ad62
JB
13416 }
13417 else
13418 {
037e8744 13419 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB
13420 struct neon_type_el et = neon_check_type (3, rs,
13421 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
88714cb8 13422 NEON_ENCODE (INTEGER, inst);
5287ad62 13423 /* The U bit (rounding) comes from bit mask. */
037e8744 13424 neon_three_same (neon_quad (rs), 0, et.size);
5287ad62
JB
13425 }
13426}
13427
13428static void
13429do_neon_fcmp_absolute (void)
13430{
037e8744 13431 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB
13432 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
13433 /* Size field comes from bit mask. */
037e8744 13434 neon_three_same (neon_quad (rs), 1, -1);
5287ad62
JB
13435}
13436
13437static void
13438do_neon_fcmp_absolute_inv (void)
13439{
13440 neon_exchange_operands ();
13441 do_neon_fcmp_absolute ();
13442}
13443
13444static void
13445do_neon_step (void)
13446{
037e8744 13447 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62 13448 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
037e8744 13449 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB
13450}
13451
13452static void
13453do_neon_abs_neg (void)
13454{
037e8744
JB
13455 enum neon_shape rs;
13456 struct neon_type_el et;
5f4273c7 13457
037e8744
JB
13458 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
13459 return;
13460
13461 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13462 return;
13463
13464 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13465 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
5f4273c7 13466
5287ad62
JB
13467 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13468 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13469 inst.instruction |= LOW4 (inst.operands[1].reg);
13470 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 13471 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB
13472 inst.instruction |= (et.type == NT_float) << 10;
13473 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 13474
88714cb8 13475 neon_dp_fixup (&inst);
5287ad62
JB
13476}
13477
13478static void
13479do_neon_sli (void)
13480{
037e8744 13481 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB
13482 struct neon_type_el et = neon_check_type (2, rs,
13483 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
13484 int imm = inst.operands[2].imm;
13485 constraint (imm < 0 || (unsigned)imm >= et.size,
13486 _("immediate out of range for insert"));
037e8744 13487 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB
13488}
13489
13490static void
13491do_neon_sri (void)
13492{
037e8744 13493 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB
13494 struct neon_type_el et = neon_check_type (2, rs,
13495 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
13496 int imm = inst.operands[2].imm;
13497 constraint (imm < 1 || (unsigned)imm > et.size,
13498 _("immediate out of range for insert"));
037e8744 13499 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
5287ad62
JB
13500}
13501
13502static void
13503do_neon_qshlu_imm (void)
13504{
037e8744 13505 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB
13506 struct neon_type_el et = neon_check_type (2, rs,
13507 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
13508 int imm = inst.operands[2].imm;
13509 constraint (imm < 0 || (unsigned)imm >= et.size,
13510 _("immediate out of range for shift"));
13511 /* Only encodes the 'U present' variant of the instruction.
13512 In this case, signed types have OP (bit 8) set to 0.
13513 Unsigned types have OP set to 1. */
13514 inst.instruction |= (et.type == NT_unsigned) << 8;
13515 /* The rest of the bits are the same as other immediate shifts. */
037e8744 13516 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB
13517}
13518
13519static void
13520do_neon_qmovn (void)
13521{
13522 struct neon_type_el et = neon_check_type (2, NS_DQ,
13523 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
13524 /* Saturating move where operands can be signed or unsigned, and the
13525 destination has the same signedness. */
88714cb8 13526 NEON_ENCODE (INTEGER, inst);
5287ad62
JB
13527 if (et.type == NT_unsigned)
13528 inst.instruction |= 0xc0;
13529 else
13530 inst.instruction |= 0x80;
13531 neon_two_same (0, 1, et.size / 2);
13532}
13533
13534static void
13535do_neon_qmovun (void)
13536{
13537 struct neon_type_el et = neon_check_type (2, NS_DQ,
13538 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
13539 /* Saturating move with unsigned results. Operands must be signed. */
88714cb8 13540 NEON_ENCODE (INTEGER, inst);
5287ad62
JB
13541 neon_two_same (0, 1, et.size / 2);
13542}
13543
13544static void
13545do_neon_rshift_sat_narrow (void)
13546{
13547 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13548 or unsigned. If operands are unsigned, results must also be unsigned. */
13549 struct neon_type_el et = neon_check_type (2, NS_DQI,
13550 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
13551 int imm = inst.operands[2].imm;
13552 /* This gets the bounds check, size encoding and immediate bits calculation
13553 right. */
13554 et.size /= 2;
5f4273c7 13555
5287ad62
JB
13556 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13557 VQMOVN.I<size> <Dd>, <Qm>. */
13558 if (imm == 0)
13559 {
13560 inst.operands[2].present = 0;
13561 inst.instruction = N_MNEM_vqmovn;
13562 do_neon_qmovn ();
13563 return;
13564 }
5f4273c7 13565
5287ad62
JB
13566 constraint (imm < 1 || (unsigned)imm > et.size,
13567 _("immediate out of range"));
13568 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
13569}
13570
13571static void
13572do_neon_rshift_sat_narrow_u (void)
13573{
13574 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13575 or unsigned. If operands are unsigned, results must also be unsigned. */
13576 struct neon_type_el et = neon_check_type (2, NS_DQI,
13577 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
13578 int imm = inst.operands[2].imm;
13579 /* This gets the bounds check, size encoding and immediate bits calculation
13580 right. */
13581 et.size /= 2;
13582
13583 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13584 VQMOVUN.I<size> <Dd>, <Qm>. */
13585 if (imm == 0)
13586 {
13587 inst.operands[2].present = 0;
13588 inst.instruction = N_MNEM_vqmovun;
13589 do_neon_qmovun ();
13590 return;
13591 }
13592
13593 constraint (imm < 1 || (unsigned)imm > et.size,
13594 _("immediate out of range"));
13595 /* FIXME: The manual is kind of unclear about what value U should have in
13596 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13597 must be 1. */
13598 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
13599}
13600
13601static void
13602do_neon_movn (void)
13603{
13604 struct neon_type_el et = neon_check_type (2, NS_DQ,
13605 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
88714cb8 13606 NEON_ENCODE (INTEGER, inst);
5287ad62
JB
13607 neon_two_same (0, 1, et.size / 2);
13608}
13609
13610static void
13611do_neon_rshift_narrow (void)
13612{
13613 struct neon_type_el et = neon_check_type (2, NS_DQI,
13614 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
13615 int imm = inst.operands[2].imm;
13616 /* This gets the bounds check, size encoding and immediate bits calculation
13617 right. */
13618 et.size /= 2;
5f4273c7 13619
5287ad62
JB
13620 /* If immediate is zero then we are a pseudo-instruction for
13621 VMOVN.I<size> <Dd>, <Qm> */
13622 if (imm == 0)
13623 {
13624 inst.operands[2].present = 0;
13625 inst.instruction = N_MNEM_vmovn;
13626 do_neon_movn ();
13627 return;
13628 }
5f4273c7 13629
5287ad62
JB
13630 constraint (imm < 1 || (unsigned)imm > et.size,
13631 _("immediate out of range for narrowing operation"));
13632 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
13633}
13634
13635static void
13636do_neon_shll (void)
13637{
13638 /* FIXME: Type checking when lengthening. */
13639 struct neon_type_el et = neon_check_type (2, NS_QDI,
13640 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
13641 unsigned imm = inst.operands[2].imm;
13642
13643 if (imm == et.size)
13644 {
13645 /* Maximum shift variant. */
88714cb8 13646 NEON_ENCODE (INTEGER, inst);
5287ad62
JB
13647 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13648 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13649 inst.instruction |= LOW4 (inst.operands[1].reg);
13650 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13651 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 13652
88714cb8 13653 neon_dp_fixup (&inst);
5287ad62
JB
13654 }
13655 else
13656 {
13657 /* A more-specific type check for non-max versions. */
13658 et = neon_check_type (2, NS_QDI,
13659 N_EQK | N_DBL, N_SU_32 | N_KEY);
88714cb8 13660 NEON_ENCODE (IMMED, inst);
5287ad62
JB
13661 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
13662 }
13663}
13664
037e8744 13665/* Check the various types for the VCVT instruction, and return which version
5287ad62
JB
13666 the current instruction is. */
13667
13668static int
13669neon_cvt_flavour (enum neon_shape rs)
13670{
037e8744
JB
13671#define CVT_VAR(C,X,Y) \
13672 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13673 if (et.type != NT_invtype) \
13674 { \
13675 inst.error = NULL; \
13676 return (C); \
5287ad62
JB
13677 }
13678 struct neon_type_el et;
037e8744
JB
13679 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
13680 || rs == NS_FF) ? N_VFP : 0;
13681 /* The instruction versions which take an immediate take one register
13682 argument, which is extended to the width of the full register. Thus the
13683 "source" and "destination" registers must have the same width. Hack that
13684 here by making the size equal to the key (wider, in this case) operand. */
13685 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
5f4273c7 13686
5287ad62
JB
13687 CVT_VAR (0, N_S32, N_F32);
13688 CVT_VAR (1, N_U32, N_F32);
13689 CVT_VAR (2, N_F32, N_S32);
13690 CVT_VAR (3, N_F32, N_U32);
8e79c3df
CM
13691 /* Half-precision conversions. */
13692 CVT_VAR (4, N_F32, N_F16);
13693 CVT_VAR (5, N_F16, N_F32);
5f4273c7 13694
037e8744 13695 whole_reg = N_VFP;
5f4273c7 13696
037e8744 13697 /* VFP instructions. */
8e79c3df
CM
13698 CVT_VAR (6, N_F32, N_F64);
13699 CVT_VAR (7, N_F64, N_F32);
13700 CVT_VAR (8, N_S32, N_F64 | key);
13701 CVT_VAR (9, N_U32, N_F64 | key);
13702 CVT_VAR (10, N_F64 | key, N_S32);
13703 CVT_VAR (11, N_F64 | key, N_U32);
037e8744 13704 /* VFP instructions with bitshift. */
8e79c3df
CM
13705 CVT_VAR (12, N_F32 | key, N_S16);
13706 CVT_VAR (13, N_F32 | key, N_U16);
13707 CVT_VAR (14, N_F64 | key, N_S16);
13708 CVT_VAR (15, N_F64 | key, N_U16);
13709 CVT_VAR (16, N_S16, N_F32 | key);
13710 CVT_VAR (17, N_U16, N_F32 | key);
13711 CVT_VAR (18, N_S16, N_F64 | key);
13712 CVT_VAR (19, N_U16, N_F64 | key);
5f4273c7 13713
5287ad62
JB
13714 return -1;
13715#undef CVT_VAR
13716}
13717
037e8744
JB
13718/* Neon-syntax VFP conversions. */
13719
5287ad62 13720static void
037e8744 13721do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
5287ad62 13722{
037e8744 13723 const char *opname = 0;
5f4273c7 13724
037e8744 13725 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
5287ad62 13726 {
037e8744
JB
13727 /* Conversions with immediate bitshift. */
13728 const char *enc[] =
13729 {
13730 "ftosls",
13731 "ftouls",
13732 "fsltos",
13733 "fultos",
13734 NULL,
13735 NULL,
8e79c3df
CM
13736 NULL,
13737 NULL,
037e8744
JB
13738 "ftosld",
13739 "ftould",
13740 "fsltod",
13741 "fultod",
13742 "fshtos",
13743 "fuhtos",
13744 "fshtod",
13745 "fuhtod",
13746 "ftoshs",
13747 "ftouhs",
13748 "ftoshd",
13749 "ftouhd"
13750 };
13751
13752 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
13753 {
13754 opname = enc[flavour];
13755 constraint (inst.operands[0].reg != inst.operands[1].reg,
13756 _("operands 0 and 1 must be the same register"));
13757 inst.operands[1] = inst.operands[2];
13758 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
13759 }
5287ad62
JB
13760 }
13761 else
13762 {
037e8744
JB
13763 /* Conversions without bitshift. */
13764 const char *enc[] =
13765 {
13766 "ftosis",
13767 "ftouis",
13768 "fsitos",
13769 "fuitos",
8e79c3df
CM
13770 "NULL",
13771 "NULL",
037e8744
JB
13772 "fcvtsd",
13773 "fcvtds",
13774 "ftosid",
13775 "ftouid",
13776 "fsitod",
13777 "fuitod"
13778 };
13779
13780 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
13781 opname = enc[flavour];
13782 }
13783
13784 if (opname)
13785 do_vfp_nsyn_opcode (opname);
13786}
13787
13788static void
13789do_vfp_nsyn_cvtz (void)
13790{
13791 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
13792 int flavour = neon_cvt_flavour (rs);
13793 const char *enc[] =
13794 {
13795 "ftosizs",
13796 "ftouizs",
13797 NULL,
13798 NULL,
13799 NULL,
13800 NULL,
8e79c3df
CM
13801 NULL,
13802 NULL,
037e8744
JB
13803 "ftosizd",
13804 "ftouizd"
13805 };
13806
13807 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
13808 do_vfp_nsyn_opcode (enc[flavour]);
13809}
f31fef98 13810
037e8744 13811static void
e3e535bc 13812do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
037e8744
JB
13813{
13814 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
8e79c3df 13815 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
037e8744
JB
13816 int flavour = neon_cvt_flavour (rs);
13817
e3e535bc
NC
13818 /* PR11109: Handle round-to-zero for VCVT conversions. */
13819 if (round_to_zero
13820 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
13821 && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9)
13822 && (rs == NS_FD || rs == NS_FF))
13823 {
13824 do_vfp_nsyn_cvtz ();
13825 return;
13826 }
13827
037e8744 13828 /* VFP rather than Neon conversions. */
8e79c3df 13829 if (flavour >= 6)
037e8744
JB
13830 {
13831 do_vfp_nsyn_cvt (rs, flavour);
13832 return;
13833 }
13834
13835 switch (rs)
13836 {
13837 case NS_DDI:
13838 case NS_QQI:
13839 {
35997600
NC
13840 unsigned immbits;
13841 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13842
037e8744
JB
13843 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13844 return;
13845
13846 /* Fixed-point conversion with #0 immediate is encoded as an
13847 integer conversion. */
13848 if (inst.operands[2].present && inst.operands[2].imm == 0)
13849 goto int_encode;
35997600 13850 immbits = 32 - inst.operands[2].imm;
88714cb8 13851 NEON_ENCODE (IMMED, inst);
037e8744
JB
13852 if (flavour != -1)
13853 inst.instruction |= enctab[flavour];
13854 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13855 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13856 inst.instruction |= LOW4 (inst.operands[1].reg);
13857 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13858 inst.instruction |= neon_quad (rs) << 6;
13859 inst.instruction |= 1 << 21;
13860 inst.instruction |= immbits << 16;
13861
88714cb8 13862 neon_dp_fixup (&inst);
037e8744
JB
13863 }
13864 break;
13865
13866 case NS_DD:
13867 case NS_QQ:
13868 int_encode:
13869 {
13870 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
13871
88714cb8 13872 NEON_ENCODE (INTEGER, inst);
037e8744
JB
13873
13874 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13875 return;
13876
13877 if (flavour != -1)
13878 inst.instruction |= enctab[flavour];
13879
13880 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13881 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13882 inst.instruction |= LOW4 (inst.operands[1].reg);
13883 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13884 inst.instruction |= neon_quad (rs) << 6;
13885 inst.instruction |= 2 << 18;
13886
88714cb8 13887 neon_dp_fixup (&inst);
037e8744
JB
13888 }
13889 break;
13890
8e79c3df
CM
13891 /* Half-precision conversions for Advanced SIMD -- neon. */
13892 case NS_QD:
13893 case NS_DQ:
13894
13895 if ((rs == NS_DQ)
13896 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
13897 {
13898 as_bad (_("operand size must match register width"));
13899 break;
13900 }
13901
13902 if ((rs == NS_QD)
13903 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
13904 {
13905 as_bad (_("operand size must match register width"));
13906 break;
13907 }
13908
13909 if (rs == NS_DQ)
13910 inst.instruction = 0x3b60600;
13911 else
13912 inst.instruction = 0x3b60700;
13913
13914 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13915 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13916 inst.instruction |= LOW4 (inst.operands[1].reg);
13917 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
88714cb8 13918 neon_dp_fixup (&inst);
8e79c3df
CM
13919 break;
13920
037e8744
JB
13921 default:
13922 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
13923 do_vfp_nsyn_cvt (rs, flavour);
5287ad62 13924 }
5287ad62
JB
13925}
13926
e3e535bc
NC
13927static void
13928do_neon_cvtr (void)
13929{
13930 do_neon_cvt_1 (FALSE);
13931}
13932
13933static void
13934do_neon_cvt (void)
13935{
13936 do_neon_cvt_1 (TRUE);
13937}
13938
8e79c3df
CM
13939static void
13940do_neon_cvtb (void)
13941{
13942 inst.instruction = 0xeb20a40;
13943
13944 /* The sizes are attached to the mnemonic. */
13945 if (inst.vectype.el[0].type != NT_invtype
13946 && inst.vectype.el[0].size == 16)
13947 inst.instruction |= 0x00010000;
13948
13949 /* Programmer's syntax: the sizes are attached to the operands. */
13950 else if (inst.operands[0].vectype.type != NT_invtype
13951 && inst.operands[0].vectype.size == 16)
13952 inst.instruction |= 0x00010000;
13953
13954 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
13955 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
13956 do_vfp_cond_or_thumb ();
13957}
13958
13959
13960static void
13961do_neon_cvtt (void)
13962{
13963 do_neon_cvtb ();
13964 inst.instruction |= 0x80;
13965}
13966
5287ad62
JB
13967static void
13968neon_move_immediate (void)
13969{
037e8744
JB
13970 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
13971 struct neon_type_el et = neon_check_type (2, rs,
13972 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
5287ad62 13973 unsigned immlo, immhi = 0, immbits;
c96612cc 13974 int op, cmode, float_p;
5287ad62 13975
037e8744
JB
13976 constraint (et.type == NT_invtype,
13977 _("operand size must be specified for immediate VMOV"));
13978
5287ad62
JB
13979 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
13980 op = (inst.instruction & (1 << 5)) != 0;
13981
13982 immlo = inst.operands[1].imm;
13983 if (inst.operands[1].regisimm)
13984 immhi = inst.operands[1].reg;
13985
13986 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
13987 _("immediate has bits set outside the operand size"));
13988
c96612cc
JB
13989 float_p = inst.operands[1].immisfloat;
13990
13991 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
136da414 13992 et.size, et.type)) == FAIL)
5287ad62
JB
13993 {
13994 /* Invert relevant bits only. */
13995 neon_invert_size (&immlo, &immhi, et.size);
13996 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
13997 with one or the other; those cases are caught by
13998 neon_cmode_for_move_imm. */
13999 op = !op;
c96612cc
JB
14000 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14001 &op, et.size, et.type)) == FAIL)
5287ad62 14002 {
dcbf9037 14003 first_error (_("immediate out of range"));
5287ad62
JB
14004 return;
14005 }
14006 }
14007
14008 inst.instruction &= ~(1 << 5);
14009 inst.instruction |= op << 5;
14010
14011 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14012 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
037e8744 14013 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB
14014 inst.instruction |= cmode << 8;
14015
14016 neon_write_immbits (immbits);
14017}
14018
14019static void
14020do_neon_mvn (void)
14021{
14022 if (inst.operands[1].isreg)
14023 {
037e8744 14024 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5f4273c7 14025
88714cb8 14026 NEON_ENCODE (INTEGER, inst);
5287ad62
JB
14027 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14028 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14029 inst.instruction |= LOW4 (inst.operands[1].reg);
14030 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 14031 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB
14032 }
14033 else
14034 {
88714cb8 14035 NEON_ENCODE (IMMED, inst);
5287ad62
JB
14036 neon_move_immediate ();
14037 }
14038
88714cb8 14039 neon_dp_fixup (&inst);
5287ad62
JB
14040}
14041
14042/* Encode instructions of form:
14043
14044 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
5f4273c7 14045 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
5287ad62
JB
14046
14047static void
14048neon_mixed_length (struct neon_type_el et, unsigned size)
14049{
14050 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14051 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14052 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14053 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14054 inst.instruction |= LOW4 (inst.operands[2].reg);
14055 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14056 inst.instruction |= (et.type == NT_unsigned) << 24;
14057 inst.instruction |= neon_logbits (size) << 20;
5f4273c7 14058
88714cb8 14059 neon_dp_fixup (&inst);
5287ad62
JB
14060}
14061
14062static void
14063do_neon_dyadic_long (void)
14064{
14065 /* FIXME: Type checking for lengthening op. */
14066 struct neon_type_el et = neon_check_type (3, NS_QDD,
14067 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
14068 neon_mixed_length (et, et.size);
14069}
14070
14071static void
14072do_neon_abal (void)
14073{
14074 struct neon_type_el et = neon_check_type (3, NS_QDD,
14075 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
14076 neon_mixed_length (et, et.size);
14077}
14078
14079static void
14080neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
14081{
14082 if (inst.operands[2].isscalar)
14083 {
dcbf9037
JB
14084 struct neon_type_el et = neon_check_type (3, NS_QDS,
14085 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
88714cb8 14086 NEON_ENCODE (SCALAR, inst);
5287ad62
JB
14087 neon_mul_mac (et, et.type == NT_unsigned);
14088 }
14089 else
14090 {
14091 struct neon_type_el et = neon_check_type (3, NS_QDD,
14092 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
88714cb8 14093 NEON_ENCODE (INTEGER, inst);
5287ad62
JB
14094 neon_mixed_length (et, et.size);
14095 }
14096}
14097
14098static void
14099do_neon_mac_maybe_scalar_long (void)
14100{
14101 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
14102}
14103
14104static void
14105do_neon_dyadic_wide (void)
14106{
14107 struct neon_type_el et = neon_check_type (3, NS_QQD,
14108 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
14109 neon_mixed_length (et, et.size);
14110}
14111
14112static void
14113do_neon_dyadic_narrow (void)
14114{
14115 struct neon_type_el et = neon_check_type (3, NS_QDD,
14116 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
428e3f1f
PB
14117 /* Operand sign is unimportant, and the U bit is part of the opcode,
14118 so force the operand type to integer. */
14119 et.type = NT_integer;
5287ad62
JB
14120 neon_mixed_length (et, et.size / 2);
14121}
14122
14123static void
14124do_neon_mul_sat_scalar_long (void)
14125{
14126 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
14127}
14128
14129static void
14130do_neon_vmull (void)
14131{
14132 if (inst.operands[2].isscalar)
14133 do_neon_mac_maybe_scalar_long ();
14134 else
14135 {
14136 struct neon_type_el et = neon_check_type (3, NS_QDD,
14137 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
14138 if (et.type == NT_poly)
88714cb8 14139 NEON_ENCODE (POLY, inst);
5287ad62 14140 else
88714cb8 14141 NEON_ENCODE (INTEGER, inst);
5287ad62
JB
14142 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14143 zero. Should be OK as-is. */
14144 neon_mixed_length (et, et.size);
14145 }
14146}
14147
14148static void
14149do_neon_ext (void)
14150{
037e8744 14151 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
5287ad62
JB
14152 struct neon_type_el et = neon_check_type (3, rs,
14153 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14154 unsigned imm = (inst.operands[3].imm * et.size) / 8;
35997600
NC
14155
14156 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
14157 _("shift out of range"));
5287ad62
JB
14158 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14159 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14160 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14161 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14162 inst.instruction |= LOW4 (inst.operands[2].reg);
14163 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
037e8744 14164 inst.instruction |= neon_quad (rs) << 6;
5287ad62 14165 inst.instruction |= imm << 8;
5f4273c7 14166
88714cb8 14167 neon_dp_fixup (&inst);
5287ad62
JB
14168}
14169
14170static void
14171do_neon_rev (void)
14172{
037e8744 14173 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
14174 struct neon_type_el et = neon_check_type (2, rs,
14175 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14176 unsigned op = (inst.instruction >> 7) & 3;
14177 /* N (width of reversed regions) is encoded as part of the bitmask. We
14178 extract it here to check the elements to be reversed are smaller.
14179 Otherwise we'd get a reserved instruction. */
14180 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
9c2799c2 14181 gas_assert (elsize != 0);
5287ad62
JB
14182 constraint (et.size >= elsize,
14183 _("elements must be smaller than reversal region"));
037e8744 14184 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
14185}
14186
14187static void
14188do_neon_dup (void)
14189{
14190 if (inst.operands[1].isscalar)
14191 {
037e8744 14192 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
dcbf9037
JB
14193 struct neon_type_el et = neon_check_type (2, rs,
14194 N_EQK, N_8 | N_16 | N_32 | N_KEY);
5287ad62 14195 unsigned sizebits = et.size >> 3;
dcbf9037 14196 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
5287ad62 14197 int logsize = neon_logbits (et.size);
dcbf9037 14198 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
037e8744
JB
14199
14200 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
14201 return;
14202
88714cb8 14203 NEON_ENCODE (SCALAR, inst);
5287ad62
JB
14204 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14205 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14206 inst.instruction |= LOW4 (dm);
14207 inst.instruction |= HI1 (dm) << 5;
037e8744 14208 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB
14209 inst.instruction |= x << 17;
14210 inst.instruction |= sizebits << 16;
5f4273c7 14211
88714cb8 14212 neon_dp_fixup (&inst);
5287ad62
JB
14213 }
14214 else
14215 {
037e8744
JB
14216 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
14217 struct neon_type_el et = neon_check_type (2, rs,
14218 N_8 | N_16 | N_32 | N_KEY, N_EQK);
5287ad62 14219 /* Duplicate ARM register to lanes of vector. */
88714cb8 14220 NEON_ENCODE (ARMREG, inst);
5287ad62
JB
14221 switch (et.size)
14222 {
14223 case 8: inst.instruction |= 0x400000; break;
14224 case 16: inst.instruction |= 0x000020; break;
14225 case 32: inst.instruction |= 0x000000; break;
14226 default: break;
14227 }
14228 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
14229 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
14230 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
037e8744 14231 inst.instruction |= neon_quad (rs) << 21;
5287ad62
JB
14232 /* The encoding for this instruction is identical for the ARM and Thumb
14233 variants, except for the condition field. */
037e8744 14234 do_vfp_cond_or_thumb ();
5287ad62
JB
14235 }
14236}
14237
14238/* VMOV has particularly many variations. It can be one of:
14239 0. VMOV<c><q> <Qd>, <Qm>
14240 1. VMOV<c><q> <Dd>, <Dm>
14241 (Register operations, which are VORR with Rm = Rn.)
14242 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14243 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14244 (Immediate loads.)
14245 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14246 (ARM register to scalar.)
14247 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14248 (Two ARM registers to vector.)
14249 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14250 (Scalar to ARM register.)
14251 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14252 (Vector to two ARM registers.)
037e8744
JB
14253 8. VMOV.F32 <Sd>, <Sm>
14254 9. VMOV.F64 <Dd>, <Dm>
14255 (VFP register moves.)
14256 10. VMOV.F32 <Sd>, #imm
14257 11. VMOV.F64 <Dd>, #imm
14258 (VFP float immediate load.)
14259 12. VMOV <Rd>, <Sm>
14260 (VFP single to ARM reg.)
14261 13. VMOV <Sd>, <Rm>
14262 (ARM reg to VFP single.)
14263 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14264 (Two ARM regs to two VFP singles.)
14265 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14266 (Two VFP singles to two ARM regs.)
5f4273c7 14267
037e8744
JB
14268 These cases can be disambiguated using neon_select_shape, except cases 1/9
14269 and 3/11 which depend on the operand type too.
5f4273c7 14270
5287ad62 14271 All the encoded bits are hardcoded by this function.
5f4273c7 14272
b7fc2769
JB
14273 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14274 Cases 5, 7 may be used with VFPv2 and above.
5f4273c7 14275
5287ad62 14276 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
5f4273c7 14277 can specify a type where it doesn't make sense to, and is ignored). */
5287ad62
JB
14278
14279static void
14280do_neon_mov (void)
14281{
037e8744
JB
14282 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
14283 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
14284 NS_NULL);
14285 struct neon_type_el et;
14286 const char *ldconst = 0;
5287ad62 14287
037e8744 14288 switch (rs)
5287ad62 14289 {
037e8744
JB
14290 case NS_DD: /* case 1/9. */
14291 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14292 /* It is not an error here if no type is given. */
14293 inst.error = NULL;
14294 if (et.type == NT_float && et.size == 64)
5287ad62 14295 {
037e8744
JB
14296 do_vfp_nsyn_opcode ("fcpyd");
14297 break;
5287ad62 14298 }
037e8744 14299 /* fall through. */
5287ad62 14300
037e8744
JB
14301 case NS_QQ: /* case 0/1. */
14302 {
14303 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14304 return;
14305 /* The architecture manual I have doesn't explicitly state which
14306 value the U bit should have for register->register moves, but
14307 the equivalent VORR instruction has U = 0, so do that. */
14308 inst.instruction = 0x0200110;
14309 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14310 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14311 inst.instruction |= LOW4 (inst.operands[1].reg);
14312 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14313 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14314 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14315 inst.instruction |= neon_quad (rs) << 6;
14316
88714cb8 14317 neon_dp_fixup (&inst);
037e8744
JB
14318 }
14319 break;
5f4273c7 14320
037e8744
JB
14321 case NS_DI: /* case 3/11. */
14322 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14323 inst.error = NULL;
14324 if (et.type == NT_float && et.size == 64)
5287ad62 14325 {
037e8744
JB
14326 /* case 11 (fconstd). */
14327 ldconst = "fconstd";
14328 goto encode_fconstd;
5287ad62 14329 }
037e8744
JB
14330 /* fall through. */
14331
14332 case NS_QI: /* case 2/3. */
14333 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14334 return;
14335 inst.instruction = 0x0800010;
14336 neon_move_immediate ();
88714cb8 14337 neon_dp_fixup (&inst);
5287ad62 14338 break;
5f4273c7 14339
037e8744
JB
14340 case NS_SR: /* case 4. */
14341 {
14342 unsigned bcdebits = 0;
91d6fa6a 14343 int logsize;
037e8744
JB
14344 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
14345 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
14346
91d6fa6a
NC
14347 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
14348 logsize = neon_logbits (et.size);
14349
037e8744
JB
14350 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
14351 _(BAD_FPU));
14352 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
14353 && et.size != 32, _(BAD_FPU));
14354 constraint (et.type == NT_invtype, _("bad type for scalar"));
14355 constraint (x >= 64 / et.size, _("scalar index out of range"));
14356
14357 switch (et.size)
14358 {
14359 case 8: bcdebits = 0x8; break;
14360 case 16: bcdebits = 0x1; break;
14361 case 32: bcdebits = 0x0; break;
14362 default: ;
14363 }
14364
14365 bcdebits |= x << logsize;
14366
14367 inst.instruction = 0xe000b10;
14368 do_vfp_cond_or_thumb ();
14369 inst.instruction |= LOW4 (dn) << 16;
14370 inst.instruction |= HI1 (dn) << 7;
14371 inst.instruction |= inst.operands[1].reg << 12;
14372 inst.instruction |= (bcdebits & 3) << 5;
14373 inst.instruction |= (bcdebits >> 2) << 21;
14374 }
14375 break;
5f4273c7 14376
037e8744 14377 case NS_DRR: /* case 5 (fmdrr). */
b7fc2769 14378 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
037e8744 14379 _(BAD_FPU));
b7fc2769 14380
037e8744
JB
14381 inst.instruction = 0xc400b10;
14382 do_vfp_cond_or_thumb ();
14383 inst.instruction |= LOW4 (inst.operands[0].reg);
14384 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
14385 inst.instruction |= inst.operands[1].reg << 12;
14386 inst.instruction |= inst.operands[2].reg << 16;
14387 break;
5f4273c7 14388
037e8744
JB
14389 case NS_RS: /* case 6. */
14390 {
91d6fa6a 14391 unsigned logsize;
037e8744
JB
14392 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
14393 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
14394 unsigned abcdebits = 0;
14395
91d6fa6a
NC
14396 et = neon_check_type (2, NS_NULL,
14397 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
14398 logsize = neon_logbits (et.size);
14399
037e8744
JB
14400 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
14401 _(BAD_FPU));
14402 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
14403 && et.size != 32, _(BAD_FPU));
14404 constraint (et.type == NT_invtype, _("bad type for scalar"));
14405 constraint (x >= 64 / et.size, _("scalar index out of range"));
14406
14407 switch (et.size)
14408 {
14409 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
14410 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
14411 case 32: abcdebits = 0x00; break;
14412 default: ;
14413 }
14414
14415 abcdebits |= x << logsize;
14416 inst.instruction = 0xe100b10;
14417 do_vfp_cond_or_thumb ();
14418 inst.instruction |= LOW4 (dn) << 16;
14419 inst.instruction |= HI1 (dn) << 7;
14420 inst.instruction |= inst.operands[0].reg << 12;
14421 inst.instruction |= (abcdebits & 3) << 5;
14422 inst.instruction |= (abcdebits >> 2) << 21;
14423 }
14424 break;
5f4273c7 14425
037e8744
JB
14426 case NS_RRD: /* case 7 (fmrrd). */
14427 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
14428 _(BAD_FPU));
14429
14430 inst.instruction = 0xc500b10;
14431 do_vfp_cond_or_thumb ();
14432 inst.instruction |= inst.operands[0].reg << 12;
14433 inst.instruction |= inst.operands[1].reg << 16;
14434 inst.instruction |= LOW4 (inst.operands[2].reg);
14435 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14436 break;
5f4273c7 14437
037e8744
JB
14438 case NS_FF: /* case 8 (fcpys). */
14439 do_vfp_nsyn_opcode ("fcpys");
14440 break;
5f4273c7 14441
037e8744
JB
14442 case NS_FI: /* case 10 (fconsts). */
14443 ldconst = "fconsts";
14444 encode_fconstd:
14445 if (is_quarter_float (inst.operands[1].imm))
5287ad62 14446 {
037e8744
JB
14447 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
14448 do_vfp_nsyn_opcode (ldconst);
5287ad62
JB
14449 }
14450 else
037e8744
JB
14451 first_error (_("immediate out of range"));
14452 break;
5f4273c7 14453
037e8744
JB
14454 case NS_RF: /* case 12 (fmrs). */
14455 do_vfp_nsyn_opcode ("fmrs");
14456 break;
5f4273c7 14457
037e8744
JB
14458 case NS_FR: /* case 13 (fmsr). */
14459 do_vfp_nsyn_opcode ("fmsr");
14460 break;
5f4273c7 14461
037e8744
JB
14462 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14463 (one of which is a list), but we have parsed four. Do some fiddling to
14464 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14465 expect. */
14466 case NS_RRFF: /* case 14 (fmrrs). */
14467 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
14468 _("VFP registers must be adjacent"));
14469 inst.operands[2].imm = 2;
14470 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
14471 do_vfp_nsyn_opcode ("fmrrs");
14472 break;
5f4273c7 14473
037e8744
JB
14474 case NS_FFRR: /* case 15 (fmsrr). */
14475 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
14476 _("VFP registers must be adjacent"));
14477 inst.operands[1] = inst.operands[2];
14478 inst.operands[2] = inst.operands[3];
14479 inst.operands[0].imm = 2;
14480 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
14481 do_vfp_nsyn_opcode ("fmsrr");
5287ad62 14482 break;
5f4273c7 14483
5287ad62
JB
14484 default:
14485 abort ();
14486 }
14487}
14488
14489static void
14490do_neon_rshift_round_imm (void)
14491{
037e8744 14492 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB
14493 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
14494 int imm = inst.operands[2].imm;
14495
14496 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14497 if (imm == 0)
14498 {
14499 inst.operands[2].present = 0;
14500 do_neon_mov ();
14501 return;
14502 }
14503
14504 constraint (imm < 1 || (unsigned)imm > et.size,
14505 _("immediate out of range for shift"));
037e8744 14506 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
5287ad62
JB
14507 et.size - imm);
14508}
14509
14510static void
14511do_neon_movl (void)
14512{
14513 struct neon_type_el et = neon_check_type (2, NS_QD,
14514 N_EQK | N_DBL, N_SU_32 | N_KEY);
14515 unsigned sizebits = et.size >> 3;
14516 inst.instruction |= sizebits << 19;
14517 neon_two_same (0, et.type == NT_unsigned, -1);
14518}
14519
14520static void
14521do_neon_trn (void)
14522{
037e8744 14523 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
14524 struct neon_type_el et = neon_check_type (2, rs,
14525 N_EQK, N_8 | N_16 | N_32 | N_KEY);
88714cb8 14526 NEON_ENCODE (INTEGER, inst);
037e8744 14527 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
14528}
14529
14530static void
14531do_neon_zip_uzp (void)
14532{
037e8744 14533 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
14534 struct neon_type_el et = neon_check_type (2, rs,
14535 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14536 if (rs == NS_DD && et.size == 32)
14537 {
14538 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14539 inst.instruction = N_MNEM_vtrn;
14540 do_neon_trn ();
14541 return;
14542 }
037e8744 14543 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
14544}
14545
14546static void
14547do_neon_sat_abs_neg (void)
14548{
037e8744 14549 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
14550 struct neon_type_el et = neon_check_type (2, rs,
14551 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
037e8744 14552 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
14553}
14554
14555static void
14556do_neon_pair_long (void)
14557{
037e8744 14558 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
14559 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
14560 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14561 inst.instruction |= (et.type == NT_unsigned) << 7;
037e8744 14562 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
14563}
14564
14565static void
14566do_neon_recip_est (void)
14567{
037e8744 14568 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
14569 struct neon_type_el et = neon_check_type (2, rs,
14570 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
14571 inst.instruction |= (et.type == NT_float) << 8;
037e8744 14572 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
14573}
14574
14575static void
14576do_neon_cls (void)
14577{
037e8744 14578 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
14579 struct neon_type_el et = neon_check_type (2, rs,
14580 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
037e8744 14581 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
14582}
14583
14584static void
14585do_neon_clz (void)
14586{
037e8744 14587 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
14588 struct neon_type_el et = neon_check_type (2, rs,
14589 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
037e8744 14590 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
14591}
14592
14593static void
14594do_neon_cnt (void)
14595{
037e8744 14596 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
14597 struct neon_type_el et = neon_check_type (2, rs,
14598 N_EQK | N_INT, N_8 | N_KEY);
037e8744 14599 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
14600}
14601
14602static void
14603do_neon_swp (void)
14604{
037e8744
JB
14605 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14606 neon_two_same (neon_quad (rs), 1, -1);
5287ad62
JB
14607}
14608
14609static void
14610do_neon_tbl_tbx (void)
14611{
14612 unsigned listlenbits;
dcbf9037 14613 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
5f4273c7 14614
5287ad62
JB
14615 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
14616 {
dcbf9037 14617 first_error (_("bad list length for table lookup"));
5287ad62
JB
14618 return;
14619 }
5f4273c7 14620
5287ad62
JB
14621 listlenbits = inst.operands[1].imm - 1;
14622 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14623 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14624 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14625 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14626 inst.instruction |= LOW4 (inst.operands[2].reg);
14627 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14628 inst.instruction |= listlenbits << 8;
5f4273c7 14629
88714cb8 14630 neon_dp_fixup (&inst);
5287ad62
JB
14631}
14632
14633static void
14634do_neon_ldm_stm (void)
14635{
14636 /* P, U and L bits are part of bitmask. */
14637 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
14638 unsigned offsetbits = inst.operands[1].imm * 2;
14639
037e8744
JB
14640 if (inst.operands[1].issingle)
14641 {
14642 do_vfp_nsyn_ldm_stm (is_dbmode);
14643 return;
14644 }
14645
5287ad62
JB
14646 constraint (is_dbmode && !inst.operands[0].writeback,
14647 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14648
14649 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
14650 _("register list must contain at least 1 and at most 16 "
14651 "registers"));
14652
14653 inst.instruction |= inst.operands[0].reg << 16;
14654 inst.instruction |= inst.operands[0].writeback << 21;
14655 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
14656 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
14657
14658 inst.instruction |= offsetbits;
5f4273c7 14659
037e8744 14660 do_vfp_cond_or_thumb ();
5287ad62
JB
14661}
14662
14663static void
14664do_neon_ldr_str (void)
14665{
5287ad62 14666 int is_ldr = (inst.instruction & (1 << 20)) != 0;
5f4273c7 14667
037e8744
JB
14668 if (inst.operands[0].issingle)
14669 {
cd2f129f
JB
14670 if (is_ldr)
14671 do_vfp_nsyn_opcode ("flds");
14672 else
14673 do_vfp_nsyn_opcode ("fsts");
5287ad62
JB
14674 }
14675 else
5287ad62 14676 {
cd2f129f
JB
14677 if (is_ldr)
14678 do_vfp_nsyn_opcode ("fldd");
5287ad62 14679 else
cd2f129f 14680 do_vfp_nsyn_opcode ("fstd");
5287ad62 14681 }
5287ad62
JB
14682}
14683
14684/* "interleave" version also handles non-interleaving register VLD1/VST1
14685 instructions. */
14686
14687static void
14688do_neon_ld_st_interleave (void)
14689{
037e8744 14690 struct neon_type_el et = neon_check_type (1, NS_NULL,
5287ad62
JB
14691 N_8 | N_16 | N_32 | N_64);
14692 unsigned alignbits = 0;
14693 unsigned idx;
14694 /* The bits in this table go:
14695 0: register stride of one (0) or two (1)
14696 1,2: register list length, minus one (1, 2, 3, 4).
14697 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14698 We use -1 for invalid entries. */
14699 const int typetable[] =
14700 {
14701 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14702 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14703 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14704 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14705 };
14706 int typebits;
14707
dcbf9037
JB
14708 if (et.type == NT_invtype)
14709 return;
14710
5287ad62
JB
14711 if (inst.operands[1].immisalign)
14712 switch (inst.operands[1].imm >> 8)
14713 {
14714 case 64: alignbits = 1; break;
14715 case 128:
e23c0ad8
JZ
14716 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
14717 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
5287ad62
JB
14718 goto bad_alignment;
14719 alignbits = 2;
14720 break;
14721 case 256:
e23c0ad8 14722 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
5287ad62
JB
14723 goto bad_alignment;
14724 alignbits = 3;
14725 break;
14726 default:
14727 bad_alignment:
dcbf9037 14728 first_error (_("bad alignment"));
5287ad62
JB
14729 return;
14730 }
14731
14732 inst.instruction |= alignbits << 4;
14733 inst.instruction |= neon_logbits (et.size) << 6;
14734
14735 /* Bits [4:6] of the immediate in a list specifier encode register stride
14736 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14737 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14738 up the right value for "type" in a table based on this value and the given
14739 list style, then stick it back. */
14740 idx = ((inst.operands[0].imm >> 4) & 7)
14741 | (((inst.instruction >> 8) & 3) << 3);
14742
14743 typebits = typetable[idx];
5f4273c7 14744
5287ad62
JB
14745 constraint (typebits == -1, _("bad list type for instruction"));
14746
14747 inst.instruction &= ~0xf00;
14748 inst.instruction |= typebits << 8;
14749}
14750
14751/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14752 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14753 otherwise. The variable arguments are a list of pairs of legal (size, align)
14754 values, terminated with -1. */
14755
14756static int
14757neon_alignment_bit (int size, int align, int *do_align, ...)
14758{
14759 va_list ap;
14760 int result = FAIL, thissize, thisalign;
5f4273c7 14761
5287ad62
JB
14762 if (!inst.operands[1].immisalign)
14763 {
14764 *do_align = 0;
14765 return SUCCESS;
14766 }
5f4273c7 14767
5287ad62
JB
14768 va_start (ap, do_align);
14769
14770 do
14771 {
14772 thissize = va_arg (ap, int);
14773 if (thissize == -1)
14774 break;
14775 thisalign = va_arg (ap, int);
14776
14777 if (size == thissize && align == thisalign)
14778 result = SUCCESS;
14779 }
14780 while (result != SUCCESS);
14781
14782 va_end (ap);
14783
14784 if (result == SUCCESS)
14785 *do_align = 1;
14786 else
dcbf9037 14787 first_error (_("unsupported alignment for instruction"));
5f4273c7 14788
5287ad62
JB
14789 return result;
14790}
14791
14792static void
14793do_neon_ld_st_lane (void)
14794{
037e8744 14795 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
5287ad62
JB
14796 int align_good, do_align = 0;
14797 int logsize = neon_logbits (et.size);
14798 int align = inst.operands[1].imm >> 8;
14799 int n = (inst.instruction >> 8) & 3;
14800 int max_el = 64 / et.size;
5f4273c7 14801
dcbf9037
JB
14802 if (et.type == NT_invtype)
14803 return;
5f4273c7 14804
5287ad62
JB
14805 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
14806 _("bad list length"));
14807 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
14808 _("scalar index out of range"));
14809 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
14810 && et.size == 8,
14811 _("stride of 2 unavailable when element size is 8"));
5f4273c7 14812
5287ad62
JB
14813 switch (n)
14814 {
14815 case 0: /* VLD1 / VST1. */
14816 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
14817 32, 32, -1);
14818 if (align_good == FAIL)
14819 return;
14820 if (do_align)
14821 {
14822 unsigned alignbits = 0;
14823 switch (et.size)
14824 {
14825 case 16: alignbits = 0x1; break;
14826 case 32: alignbits = 0x3; break;
14827 default: ;
14828 }
14829 inst.instruction |= alignbits << 4;
14830 }
14831 break;
14832
14833 case 1: /* VLD2 / VST2. */
14834 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
14835 32, 64, -1);
14836 if (align_good == FAIL)
14837 return;
14838 if (do_align)
14839 inst.instruction |= 1 << 4;
14840 break;
14841
14842 case 2: /* VLD3 / VST3. */
14843 constraint (inst.operands[1].immisalign,
14844 _("can't use alignment with this instruction"));
14845 break;
14846
14847 case 3: /* VLD4 / VST4. */
14848 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
14849 16, 64, 32, 64, 32, 128, -1);
14850 if (align_good == FAIL)
14851 return;
14852 if (do_align)
14853 {
14854 unsigned alignbits = 0;
14855 switch (et.size)
14856 {
14857 case 8: alignbits = 0x1; break;
14858 case 16: alignbits = 0x1; break;
14859 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
14860 default: ;
14861 }
14862 inst.instruction |= alignbits << 4;
14863 }
14864 break;
14865
14866 default: ;
14867 }
14868
14869 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14870 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
14871 inst.instruction |= 1 << (4 + logsize);
5f4273c7 14872
5287ad62
JB
14873 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
14874 inst.instruction |= logsize << 10;
14875}
14876
14877/* Encode single n-element structure to all lanes VLD<n> instructions. */
14878
14879static void
14880do_neon_ld_dup (void)
14881{
037e8744 14882 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
5287ad62
JB
14883 int align_good, do_align = 0;
14884
dcbf9037
JB
14885 if (et.type == NT_invtype)
14886 return;
14887
5287ad62
JB
14888 switch ((inst.instruction >> 8) & 3)
14889 {
14890 case 0: /* VLD1. */
9c2799c2 14891 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
5287ad62
JB
14892 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
14893 &do_align, 16, 16, 32, 32, -1);
14894 if (align_good == FAIL)
14895 return;
14896 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
14897 {
14898 case 1: break;
14899 case 2: inst.instruction |= 1 << 5; break;
dcbf9037 14900 default: first_error (_("bad list length")); return;
5287ad62
JB
14901 }
14902 inst.instruction |= neon_logbits (et.size) << 6;
14903 break;
14904
14905 case 1: /* VLD2. */
14906 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
14907 &do_align, 8, 16, 16, 32, 32, 64, -1);
14908 if (align_good == FAIL)
14909 return;
14910 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
14911 _("bad list length"));
14912 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
14913 inst.instruction |= 1 << 5;
14914 inst.instruction |= neon_logbits (et.size) << 6;
14915 break;
14916
14917 case 2: /* VLD3. */
14918 constraint (inst.operands[1].immisalign,
14919 _("can't use alignment with this instruction"));
14920 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
14921 _("bad list length"));
14922 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
14923 inst.instruction |= 1 << 5;
14924 inst.instruction |= neon_logbits (et.size) << 6;
14925 break;
14926
14927 case 3: /* VLD4. */
14928 {
14929 int align = inst.operands[1].imm >> 8;
14930 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
14931 16, 64, 32, 64, 32, 128, -1);
14932 if (align_good == FAIL)
14933 return;
14934 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
14935 _("bad list length"));
14936 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
14937 inst.instruction |= 1 << 5;
14938 if (et.size == 32 && align == 128)
14939 inst.instruction |= 0x3 << 6;
14940 else
14941 inst.instruction |= neon_logbits (et.size) << 6;
14942 }
14943 break;
14944
14945 default: ;
14946 }
14947
14948 inst.instruction |= do_align << 4;
14949}
14950
14951/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
14952 apart from bits [11:4]. */
14953
14954static void
14955do_neon_ldx_stx (void)
14956{
b1a769ed
DG
14957 if (inst.operands[1].isreg)
14958 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
14959
5287ad62
JB
14960 switch (NEON_LANE (inst.operands[0].imm))
14961 {
14962 case NEON_INTERLEAVE_LANES:
88714cb8 14963 NEON_ENCODE (INTERLV, inst);
5287ad62
JB
14964 do_neon_ld_st_interleave ();
14965 break;
5f4273c7 14966
5287ad62 14967 case NEON_ALL_LANES:
88714cb8 14968 NEON_ENCODE (DUP, inst);
5287ad62
JB
14969 do_neon_ld_dup ();
14970 break;
5f4273c7 14971
5287ad62 14972 default:
88714cb8 14973 NEON_ENCODE (LANE, inst);
5287ad62
JB
14974 do_neon_ld_st_lane ();
14975 }
14976
14977 /* L bit comes from bit mask. */
14978 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14979 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14980 inst.instruction |= inst.operands[1].reg << 16;
5f4273c7 14981
5287ad62
JB
14982 if (inst.operands[1].postind)
14983 {
14984 int postreg = inst.operands[1].imm & 0xf;
14985 constraint (!inst.operands[1].immisreg,
14986 _("post-index must be a register"));
14987 constraint (postreg == 0xd || postreg == 0xf,
14988 _("bad register for post-index"));
14989 inst.instruction |= postreg;
14990 }
14991 else if (inst.operands[1].writeback)
14992 {
14993 inst.instruction |= 0xd;
14994 }
14995 else
5f4273c7
NC
14996 inst.instruction |= 0xf;
14997
5287ad62
JB
14998 if (thumb_mode)
14999 inst.instruction |= 0xf9000000;
15000 else
15001 inst.instruction |= 0xf4000000;
15002}
5287ad62
JB
15003\f
15004/* Overall per-instruction processing. */
15005
15006/* We need to be able to fix up arbitrary expressions in some statements.
15007 This is so that we can handle symbols that are an arbitrary distance from
15008 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15009 which returns part of an address in a form which will be valid for
15010 a data instruction. We do this by pushing the expression into a symbol
15011 in the expr_section, and creating a fix for that. */
15012
15013static void
15014fix_new_arm (fragS * frag,
15015 int where,
15016 short int size,
15017 expressionS * exp,
15018 int pc_rel,
15019 int reloc)
15020{
15021 fixS * new_fix;
15022
15023 switch (exp->X_op)
15024 {
15025 case O_constant:
15026 case O_symbol:
15027 case O_add:
15028 case O_subtract:
21d799b5
NC
15029 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
15030 (enum bfd_reloc_code_real) reloc);
5287ad62
JB
15031 break;
15032
15033 default:
21d799b5
NC
15034 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
15035 pc_rel, (enum bfd_reloc_code_real) reloc);
5287ad62
JB
15036 break;
15037 }
15038
15039 /* Mark whether the fix is to a THUMB instruction, or an ARM
15040 instruction. */
15041 new_fix->tc_fix_data = thumb_mode;
15042}
15043
15044/* Create a frg for an instruction requiring relaxation. */
15045static void
15046output_relax_insn (void)
15047{
15048 char * to;
15049 symbolS *sym;
0110f2b8
PB
15050 int offset;
15051
6e1cb1a6
PB
15052 /* The size of the instruction is unknown, so tie the debug info to the
15053 start of the instruction. */
15054 dwarf2_emit_insn (0);
6e1cb1a6 15055
0110f2b8
PB
15056 switch (inst.reloc.exp.X_op)
15057 {
15058 case O_symbol:
15059 sym = inst.reloc.exp.X_add_symbol;
15060 offset = inst.reloc.exp.X_add_number;
15061 break;
15062 case O_constant:
15063 sym = NULL;
15064 offset = inst.reloc.exp.X_add_number;
15065 break;
15066 default:
15067 sym = make_expr_symbol (&inst.reloc.exp);
15068 offset = 0;
15069 break;
15070 }
15071 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
15072 inst.relax, sym, offset, NULL/*offset, opcode*/);
15073 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
0110f2b8
PB
15074}
15075
15076/* Write a 32-bit thumb instruction to buf. */
15077static void
15078put_thumb32_insn (char * buf, unsigned long insn)
15079{
15080 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
15081 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
15082}
15083
b99bd4ef 15084static void
c19d1205 15085output_inst (const char * str)
b99bd4ef 15086{
c19d1205 15087 char * to = NULL;
b99bd4ef 15088
c19d1205 15089 if (inst.error)
b99bd4ef 15090 {
c19d1205 15091 as_bad ("%s -- `%s'", inst.error, str);
b99bd4ef
NC
15092 return;
15093 }
5f4273c7
NC
15094 if (inst.relax)
15095 {
15096 output_relax_insn ();
0110f2b8 15097 return;
5f4273c7 15098 }
c19d1205
ZW
15099 if (inst.size == 0)
15100 return;
b99bd4ef 15101
c19d1205 15102 to = frag_more (inst.size);
8dc2430f
NC
15103 /* PR 9814: Record the thumb mode into the current frag so that we know
15104 what type of NOP padding to use, if necessary. We override any previous
15105 setting so that if the mode has changed then the NOPS that we use will
15106 match the encoding of the last instruction in the frag. */
cd000bff 15107 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
c19d1205
ZW
15108
15109 if (thumb_mode && (inst.size > THUMB_SIZE))
b99bd4ef 15110 {
9c2799c2 15111 gas_assert (inst.size == (2 * THUMB_SIZE));
0110f2b8 15112 put_thumb32_insn (to, inst.instruction);
b99bd4ef 15113 }
c19d1205 15114 else if (inst.size > INSN_SIZE)
b99bd4ef 15115 {
9c2799c2 15116 gas_assert (inst.size == (2 * INSN_SIZE));
c19d1205
ZW
15117 md_number_to_chars (to, inst.instruction, INSN_SIZE);
15118 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
b99bd4ef 15119 }
c19d1205
ZW
15120 else
15121 md_number_to_chars (to, inst.instruction, inst.size);
b99bd4ef 15122
c19d1205
ZW
15123 if (inst.reloc.type != BFD_RELOC_UNUSED)
15124 fix_new_arm (frag_now, to - frag_now->fr_literal,
15125 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
15126 inst.reloc.type);
b99bd4ef 15127
c19d1205 15128 dwarf2_emit_insn (inst.size);
c19d1205 15129}
b99bd4ef 15130
e07e6e58
NC
15131static char *
15132output_it_inst (int cond, int mask, char * to)
15133{
15134 unsigned long instruction = 0xbf00;
15135
15136 mask &= 0xf;
15137 instruction |= mask;
15138 instruction |= cond << 4;
15139
15140 if (to == NULL)
15141 {
15142 to = frag_more (2);
15143#ifdef OBJ_ELF
15144 dwarf2_emit_insn (2);
15145#endif
15146 }
15147
15148 md_number_to_chars (to, instruction, 2);
15149
15150 return to;
15151}
15152
c19d1205
ZW
15153/* Tag values used in struct asm_opcode's tag field. */
15154enum opcode_tag
15155{
15156 OT_unconditional, /* Instruction cannot be conditionalized.
15157 The ARM condition field is still 0xE. */
15158 OT_unconditionalF, /* Instruction cannot be conditionalized
15159 and carries 0xF in its ARM condition field. */
15160 OT_csuffix, /* Instruction takes a conditional suffix. */
037e8744
JB
15161 OT_csuffixF, /* Some forms of the instruction take a conditional
15162 suffix, others place 0xF where the condition field
15163 would be. */
c19d1205
ZW
15164 OT_cinfix3, /* Instruction takes a conditional infix,
15165 beginning at character index 3. (In
15166 unified mode, it becomes a suffix.) */
088fa78e
KH
15167 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
15168 tsts, cmps, cmns, and teqs. */
e3cb604e
PB
15169 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
15170 character index 3, even in unified mode. Used for
15171 legacy instructions where suffix and infix forms
15172 may be ambiguous. */
c19d1205 15173 OT_csuf_or_in3, /* Instruction takes either a conditional
e3cb604e 15174 suffix or an infix at character index 3. */
c19d1205
ZW
15175 OT_odd_infix_unc, /* This is the unconditional variant of an
15176 instruction that takes a conditional infix
15177 at an unusual position. In unified mode,
15178 this variant will accept a suffix. */
15179 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
15180 are the conditional variants of instructions that
15181 take conditional infixes in unusual positions.
15182 The infix appears at character index
15183 (tag - OT_odd_infix_0). These are not accepted
15184 in unified mode. */
15185};
b99bd4ef 15186
c19d1205
ZW
15187/* Subroutine of md_assemble, responsible for looking up the primary
15188 opcode from the mnemonic the user wrote. STR points to the
15189 beginning of the mnemonic.
15190
15191 This is not simply a hash table lookup, because of conditional
15192 variants. Most instructions have conditional variants, which are
15193 expressed with a _conditional affix_ to the mnemonic. If we were
15194 to encode each conditional variant as a literal string in the opcode
15195 table, it would have approximately 20,000 entries.
15196
15197 Most mnemonics take this affix as a suffix, and in unified syntax,
15198 'most' is upgraded to 'all'. However, in the divided syntax, some
15199 instructions take the affix as an infix, notably the s-variants of
15200 the arithmetic instructions. Of those instructions, all but six
15201 have the infix appear after the third character of the mnemonic.
15202
15203 Accordingly, the algorithm for looking up primary opcodes given
15204 an identifier is:
15205
15206 1. Look up the identifier in the opcode table.
15207 If we find a match, go to step U.
15208
15209 2. Look up the last two characters of the identifier in the
15210 conditions table. If we find a match, look up the first N-2
15211 characters of the identifier in the opcode table. If we
15212 find a match, go to step CE.
15213
15214 3. Look up the fourth and fifth characters of the identifier in
15215 the conditions table. If we find a match, extract those
15216 characters from the identifier, and look up the remaining
15217 characters in the opcode table. If we find a match, go
15218 to step CM.
15219
15220 4. Fail.
15221
15222 U. Examine the tag field of the opcode structure, in case this is
15223 one of the six instructions with its conditional infix in an
15224 unusual place. If it is, the tag tells us where to find the
15225 infix; look it up in the conditions table and set inst.cond
15226 accordingly. Otherwise, this is an unconditional instruction.
15227 Again set inst.cond accordingly. Return the opcode structure.
15228
15229 CE. Examine the tag field to make sure this is an instruction that
15230 should receive a conditional suffix. If it is not, fail.
15231 Otherwise, set inst.cond from the suffix we already looked up,
15232 and return the opcode structure.
15233
15234 CM. Examine the tag field to make sure this is an instruction that
15235 should receive a conditional infix after the third character.
15236 If it is not, fail. Otherwise, undo the edits to the current
15237 line of input and proceed as for case CE. */
15238
15239static const struct asm_opcode *
15240opcode_lookup (char **str)
15241{
15242 char *end, *base;
15243 char *affix;
15244 const struct asm_opcode *opcode;
15245 const struct asm_cond *cond;
e3cb604e 15246 char save[2];
c19d1205
ZW
15247
15248 /* Scan up to the end of the mnemonic, which must end in white space,
721a8186 15249 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
c19d1205 15250 for (base = end = *str; *end != '\0'; end++)
721a8186 15251 if (*end == ' ' || *end == '.')
c19d1205 15252 break;
b99bd4ef 15253
c19d1205 15254 if (end == base)
c921be7d 15255 return NULL;
b99bd4ef 15256
5287ad62 15257 /* Handle a possible width suffix and/or Neon type suffix. */
c19d1205 15258 if (end[0] == '.')
b99bd4ef 15259 {
5287ad62 15260 int offset = 2;
5f4273c7 15261
267d2029
JB
15262 /* The .w and .n suffixes are only valid if the unified syntax is in
15263 use. */
15264 if (unified_syntax && end[1] == 'w')
c19d1205 15265 inst.size_req = 4;
267d2029 15266 else if (unified_syntax && end[1] == 'n')
c19d1205
ZW
15267 inst.size_req = 2;
15268 else
5287ad62
JB
15269 offset = 0;
15270
15271 inst.vectype.elems = 0;
15272
15273 *str = end + offset;
b99bd4ef 15274
5f4273c7 15275 if (end[offset] == '.')
5287ad62 15276 {
267d2029
JB
15277 /* See if we have a Neon type suffix (possible in either unified or
15278 non-unified ARM syntax mode). */
dcbf9037 15279 if (parse_neon_type (&inst.vectype, str) == FAIL)
c921be7d 15280 return NULL;
5287ad62
JB
15281 }
15282 else if (end[offset] != '\0' && end[offset] != ' ')
c921be7d 15283 return NULL;
b99bd4ef 15284 }
c19d1205
ZW
15285 else
15286 *str = end;
b99bd4ef 15287
c19d1205 15288 /* Look for unaffixed or special-case affixed mnemonic. */
21d799b5
NC
15289 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15290 end - base);
c19d1205 15291 if (opcode)
b99bd4ef 15292 {
c19d1205
ZW
15293 /* step U */
15294 if (opcode->tag < OT_odd_infix_0)
b99bd4ef 15295 {
c19d1205
ZW
15296 inst.cond = COND_ALWAYS;
15297 return opcode;
b99bd4ef 15298 }
b99bd4ef 15299
278df34e 15300 if (warn_on_deprecated && unified_syntax)
c19d1205
ZW
15301 as_warn (_("conditional infixes are deprecated in unified syntax"));
15302 affix = base + (opcode->tag - OT_odd_infix_0);
21d799b5 15303 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
9c2799c2 15304 gas_assert (cond);
b99bd4ef 15305
c19d1205
ZW
15306 inst.cond = cond->value;
15307 return opcode;
15308 }
b99bd4ef 15309
c19d1205
ZW
15310 /* Cannot have a conditional suffix on a mnemonic of less than two
15311 characters. */
15312 if (end - base < 3)
c921be7d 15313 return NULL;
b99bd4ef 15314
c19d1205
ZW
15315 /* Look for suffixed mnemonic. */
15316 affix = end - 2;
21d799b5
NC
15317 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15318 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15319 affix - base);
c19d1205
ZW
15320 if (opcode && cond)
15321 {
15322 /* step CE */
15323 switch (opcode->tag)
15324 {
e3cb604e
PB
15325 case OT_cinfix3_legacy:
15326 /* Ignore conditional suffixes matched on infix only mnemonics. */
15327 break;
15328
c19d1205 15329 case OT_cinfix3:
088fa78e 15330 case OT_cinfix3_deprecated:
c19d1205
ZW
15331 case OT_odd_infix_unc:
15332 if (!unified_syntax)
e3cb604e 15333 return 0;
c19d1205
ZW
15334 /* else fall through */
15335
15336 case OT_csuffix:
037e8744 15337 case OT_csuffixF:
c19d1205
ZW
15338 case OT_csuf_or_in3:
15339 inst.cond = cond->value;
15340 return opcode;
15341
15342 case OT_unconditional:
15343 case OT_unconditionalF:
dfa9f0d5 15344 if (thumb_mode)
c921be7d 15345 inst.cond = cond->value;
dfa9f0d5
PB
15346 else
15347 {
c921be7d 15348 /* Delayed diagnostic. */
dfa9f0d5
PB
15349 inst.error = BAD_COND;
15350 inst.cond = COND_ALWAYS;
15351 }
c19d1205 15352 return opcode;
b99bd4ef 15353
c19d1205 15354 default:
c921be7d 15355 return NULL;
c19d1205
ZW
15356 }
15357 }
b99bd4ef 15358
c19d1205
ZW
15359 /* Cannot have a usual-position infix on a mnemonic of less than
15360 six characters (five would be a suffix). */
15361 if (end - base < 6)
c921be7d 15362 return NULL;
b99bd4ef 15363
c19d1205
ZW
15364 /* Look for infixed mnemonic in the usual position. */
15365 affix = base + 3;
21d799b5 15366 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
e3cb604e 15367 if (!cond)
c921be7d 15368 return NULL;
e3cb604e
PB
15369
15370 memcpy (save, affix, 2);
15371 memmove (affix, affix + 2, (end - affix) - 2);
21d799b5
NC
15372 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15373 (end - base) - 2);
e3cb604e
PB
15374 memmove (affix + 2, affix, (end - affix) - 2);
15375 memcpy (affix, save, 2);
15376
088fa78e
KH
15377 if (opcode
15378 && (opcode->tag == OT_cinfix3
15379 || opcode->tag == OT_cinfix3_deprecated
15380 || opcode->tag == OT_csuf_or_in3
15381 || opcode->tag == OT_cinfix3_legacy))
b99bd4ef 15382 {
c921be7d 15383 /* Step CM. */
278df34e 15384 if (warn_on_deprecated && unified_syntax
088fa78e
KH
15385 && (opcode->tag == OT_cinfix3
15386 || opcode->tag == OT_cinfix3_deprecated))
c19d1205
ZW
15387 as_warn (_("conditional infixes are deprecated in unified syntax"));
15388
15389 inst.cond = cond->value;
15390 return opcode;
b99bd4ef
NC
15391 }
15392
c921be7d 15393 return NULL;
b99bd4ef
NC
15394}
15395
e07e6e58
NC
15396/* This function generates an initial IT instruction, leaving its block
15397 virtually open for the new instructions. Eventually,
15398 the mask will be updated by now_it_add_mask () each time
15399 a new instruction needs to be included in the IT block.
15400 Finally, the block is closed with close_automatic_it_block ().
15401 The block closure can be requested either from md_assemble (),
15402 a tencode (), or due to a label hook. */
15403
15404static void
15405new_automatic_it_block (int cond)
15406{
15407 now_it.state = AUTOMATIC_IT_BLOCK;
15408 now_it.mask = 0x18;
15409 now_it.cc = cond;
15410 now_it.block_length = 1;
cd000bff 15411 mapping_state (MAP_THUMB);
e07e6e58
NC
15412 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
15413}
15414
15415/* Close an automatic IT block.
15416 See comments in new_automatic_it_block (). */
15417
15418static void
15419close_automatic_it_block (void)
15420{
15421 now_it.mask = 0x10;
15422 now_it.block_length = 0;
15423}
15424
15425/* Update the mask of the current automatically-generated IT
15426 instruction. See comments in new_automatic_it_block (). */
15427
15428static void
15429now_it_add_mask (int cond)
15430{
15431#define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15432#define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15433 | ((bitvalue) << (nbit)))
e07e6e58 15434 const int resulting_bit = (cond & 1);
c921be7d 15435
e07e6e58
NC
15436 now_it.mask &= 0xf;
15437 now_it.mask = SET_BIT_VALUE (now_it.mask,
15438 resulting_bit,
15439 (5 - now_it.block_length));
15440 now_it.mask = SET_BIT_VALUE (now_it.mask,
15441 1,
15442 ((5 - now_it.block_length) - 1) );
15443 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
15444
15445#undef CLEAR_BIT
15446#undef SET_BIT_VALUE
e07e6e58
NC
15447}
15448
15449/* The IT blocks handling machinery is accessed through the these functions:
15450 it_fsm_pre_encode () from md_assemble ()
15451 set_it_insn_type () optional, from the tencode functions
15452 set_it_insn_type_last () ditto
15453 in_it_block () ditto
15454 it_fsm_post_encode () from md_assemble ()
15455 force_automatic_it_block_close () from label habdling functions
15456
15457 Rationale:
15458 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15459 initializing the IT insn type with a generic initial value depending
15460 on the inst.condition.
15461 2) During the tencode function, two things may happen:
15462 a) The tencode function overrides the IT insn type by
15463 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15464 b) The tencode function queries the IT block state by
15465 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15466
15467 Both set_it_insn_type and in_it_block run the internal FSM state
15468 handling function (handle_it_state), because: a) setting the IT insn
15469 type may incur in an invalid state (exiting the function),
15470 and b) querying the state requires the FSM to be updated.
15471 Specifically we want to avoid creating an IT block for conditional
15472 branches, so it_fsm_pre_encode is actually a guess and we can't
15473 determine whether an IT block is required until the tencode () routine
15474 has decided what type of instruction this actually it.
15475 Because of this, if set_it_insn_type and in_it_block have to be used,
15476 set_it_insn_type has to be called first.
15477
15478 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15479 determines the insn IT type depending on the inst.cond code.
15480 When a tencode () routine encodes an instruction that can be
15481 either outside an IT block, or, in the case of being inside, has to be
15482 the last one, set_it_insn_type_last () will determine the proper
15483 IT instruction type based on the inst.cond code. Otherwise,
15484 set_it_insn_type can be called for overriding that logic or
15485 for covering other cases.
15486
15487 Calling handle_it_state () may not transition the IT block state to
15488 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15489 still queried. Instead, if the FSM determines that the state should
15490 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15491 after the tencode () function: that's what it_fsm_post_encode () does.
15492
15493 Since in_it_block () calls the state handling function to get an
15494 updated state, an error may occur (due to invalid insns combination).
15495 In that case, inst.error is set.
15496 Therefore, inst.error has to be checked after the execution of
15497 the tencode () routine.
15498
15499 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15500 any pending state change (if any) that didn't take place in
15501 handle_it_state () as explained above. */
15502
15503static void
15504it_fsm_pre_encode (void)
15505{
15506 if (inst.cond != COND_ALWAYS)
15507 inst.it_insn_type = INSIDE_IT_INSN;
15508 else
15509 inst.it_insn_type = OUTSIDE_IT_INSN;
15510
15511 now_it.state_handled = 0;
15512}
15513
15514/* IT state FSM handling function. */
15515
15516static int
15517handle_it_state (void)
15518{
15519 now_it.state_handled = 1;
15520
15521 switch (now_it.state)
15522 {
15523 case OUTSIDE_IT_BLOCK:
15524 switch (inst.it_insn_type)
15525 {
15526 case OUTSIDE_IT_INSN:
15527 break;
15528
15529 case INSIDE_IT_INSN:
15530 case INSIDE_IT_LAST_INSN:
15531 if (thumb_mode == 0)
15532 {
c921be7d 15533 if (unified_syntax
e07e6e58
NC
15534 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
15535 as_tsktsk (_("Warning: conditional outside an IT block"\
15536 " for Thumb."));
15537 }
15538 else
15539 {
15540 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
15541 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
15542 {
15543 /* Automatically generate the IT instruction. */
15544 new_automatic_it_block (inst.cond);
15545 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
15546 close_automatic_it_block ();
15547 }
15548 else
15549 {
15550 inst.error = BAD_OUT_IT;
15551 return FAIL;
15552 }
15553 }
15554 break;
15555
15556 case IF_INSIDE_IT_LAST_INSN:
15557 case NEUTRAL_IT_INSN:
15558 break;
15559
15560 case IT_INSN:
15561 now_it.state = MANUAL_IT_BLOCK;
15562 now_it.block_length = 0;
15563 break;
15564 }
15565 break;
15566
15567 case AUTOMATIC_IT_BLOCK:
15568 /* Three things may happen now:
15569 a) We should increment current it block size;
15570 b) We should close current it block (closing insn or 4 insns);
15571 c) We should close current it block and start a new one (due
15572 to incompatible conditions or
15573 4 insns-length block reached). */
15574
15575 switch (inst.it_insn_type)
15576 {
15577 case OUTSIDE_IT_INSN:
15578 /* The closure of the block shall happen immediatelly,
15579 so any in_it_block () call reports the block as closed. */
15580 force_automatic_it_block_close ();
15581 break;
15582
15583 case INSIDE_IT_INSN:
15584 case INSIDE_IT_LAST_INSN:
15585 case IF_INSIDE_IT_LAST_INSN:
15586 now_it.block_length++;
15587
15588 if (now_it.block_length > 4
15589 || !now_it_compatible (inst.cond))
15590 {
15591 force_automatic_it_block_close ();
15592 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
15593 new_automatic_it_block (inst.cond);
15594 }
15595 else
15596 {
15597 now_it_add_mask (inst.cond);
15598 }
15599
15600 if (now_it.state == AUTOMATIC_IT_BLOCK
15601 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
15602 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
15603 close_automatic_it_block ();
15604 break;
15605
15606 case NEUTRAL_IT_INSN:
15607 now_it.block_length++;
15608
15609 if (now_it.block_length > 4)
15610 force_automatic_it_block_close ();
15611 else
15612 now_it_add_mask (now_it.cc & 1);
15613 break;
15614
15615 case IT_INSN:
15616 close_automatic_it_block ();
15617 now_it.state = MANUAL_IT_BLOCK;
15618 break;
15619 }
15620 break;
15621
15622 case MANUAL_IT_BLOCK:
15623 {
15624 /* Check conditional suffixes. */
15625 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
15626 int is_last;
15627 now_it.mask <<= 1;
15628 now_it.mask &= 0x1f;
15629 is_last = (now_it.mask == 0x10);
15630
15631 switch (inst.it_insn_type)
15632 {
15633 case OUTSIDE_IT_INSN:
15634 inst.error = BAD_NOT_IT;
15635 return FAIL;
15636
15637 case INSIDE_IT_INSN:
15638 if (cond != inst.cond)
15639 {
15640 inst.error = BAD_IT_COND;
15641 return FAIL;
15642 }
15643 break;
15644
15645 case INSIDE_IT_LAST_INSN:
15646 case IF_INSIDE_IT_LAST_INSN:
15647 if (cond != inst.cond)
15648 {
15649 inst.error = BAD_IT_COND;
15650 return FAIL;
15651 }
15652 if (!is_last)
15653 {
15654 inst.error = BAD_BRANCH;
15655 return FAIL;
15656 }
15657 break;
15658
15659 case NEUTRAL_IT_INSN:
15660 /* The BKPT instruction is unconditional even in an IT block. */
15661 break;
15662
15663 case IT_INSN:
15664 inst.error = BAD_IT_IT;
15665 return FAIL;
15666 }
15667 }
15668 break;
15669 }
15670
15671 return SUCCESS;
15672}
15673
15674static void
15675it_fsm_post_encode (void)
15676{
15677 int is_last;
15678
15679 if (!now_it.state_handled)
15680 handle_it_state ();
15681
15682 is_last = (now_it.mask == 0x10);
15683 if (is_last)
15684 {
15685 now_it.state = OUTSIDE_IT_BLOCK;
15686 now_it.mask = 0;
15687 }
15688}
15689
15690static void
15691force_automatic_it_block_close (void)
15692{
15693 if (now_it.state == AUTOMATIC_IT_BLOCK)
15694 {
15695 close_automatic_it_block ();
15696 now_it.state = OUTSIDE_IT_BLOCK;
15697 now_it.mask = 0;
15698 }
15699}
15700
15701static int
15702in_it_block (void)
15703{
15704 if (!now_it.state_handled)
15705 handle_it_state ();
15706
15707 return now_it.state != OUTSIDE_IT_BLOCK;
15708}
15709
c19d1205
ZW
15710void
15711md_assemble (char *str)
b99bd4ef 15712{
c19d1205
ZW
15713 char *p = str;
15714 const struct asm_opcode * opcode;
b99bd4ef 15715
c19d1205
ZW
15716 /* Align the previous label if needed. */
15717 if (last_label_seen != NULL)
b99bd4ef 15718 {
c19d1205
ZW
15719 symbol_set_frag (last_label_seen, frag_now);
15720 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
15721 S_SET_SEGMENT (last_label_seen, now_seg);
b99bd4ef
NC
15722 }
15723
c19d1205
ZW
15724 memset (&inst, '\0', sizeof (inst));
15725 inst.reloc.type = BFD_RELOC_UNUSED;
b99bd4ef 15726
c19d1205
ZW
15727 opcode = opcode_lookup (&p);
15728 if (!opcode)
b99bd4ef 15729 {
c19d1205 15730 /* It wasn't an instruction, but it might be a register alias of
dcbf9037 15731 the form alias .req reg, or a Neon .dn/.qn directive. */
c921be7d
NC
15732 if (! create_register_alias (str, p)
15733 && ! create_neon_reg_alias (str, p))
c19d1205 15734 as_bad (_("bad instruction `%s'"), str);
b99bd4ef 15735
b99bd4ef
NC
15736 return;
15737 }
15738
278df34e 15739 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
088fa78e
KH
15740 as_warn (_("s suffix on comparison instruction is deprecated"));
15741
037e8744
JB
15742 /* The value which unconditional instructions should have in place of the
15743 condition field. */
15744 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
15745
c19d1205 15746 if (thumb_mode)
b99bd4ef 15747 {
e74cfd16 15748 arm_feature_set variant;
8f06b2d8
PB
15749
15750 variant = cpu_variant;
15751 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
e74cfd16
PB
15752 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
15753 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
c19d1205 15754 /* Check that this instruction is supported for this CPU. */
62b3e311
PB
15755 if (!opcode->tvariant
15756 || (thumb_mode == 1
15757 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
b99bd4ef 15758 {
bf3eeda7 15759 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
b99bd4ef
NC
15760 return;
15761 }
c19d1205
ZW
15762 if (inst.cond != COND_ALWAYS && !unified_syntax
15763 && opcode->tencode != do_t_branch)
b99bd4ef 15764 {
c19d1205 15765 as_bad (_("Thumb does not support conditional execution"));
b99bd4ef
NC
15766 return;
15767 }
15768
752d5da4 15769 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
076d447c 15770 {
7e806470 15771 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
752d5da4
NC
15772 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
15773 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
15774 {
15775 /* Two things are addressed here.
15776 1) Implicit require narrow instructions on Thumb-1.
15777 This avoids relaxation accidentally introducing Thumb-2
15778 instructions.
15779 2) Reject wide instructions in non Thumb-2 cores. */
15780 if (inst.size_req == 0)
15781 inst.size_req = 2;
15782 else if (inst.size_req == 4)
15783 {
bf3eeda7 15784 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
752d5da4
NC
15785 return;
15786 }
15787 }
076d447c
PB
15788 }
15789
c19d1205
ZW
15790 inst.instruction = opcode->tvalue;
15791
5be8be5d 15792 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
e07e6e58
NC
15793 {
15794 /* Prepare the it_insn_type for those encodings that don't set
15795 it. */
15796 it_fsm_pre_encode ();
c19d1205 15797
e07e6e58
NC
15798 opcode->tencode ();
15799
15800 it_fsm_post_encode ();
15801 }
e27ec89e 15802
0110f2b8 15803 if (!(inst.error || inst.relax))
b99bd4ef 15804 {
9c2799c2 15805 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
c19d1205
ZW
15806 inst.size = (inst.instruction > 0xffff ? 4 : 2);
15807 if (inst.size_req && inst.size_req != inst.size)
b99bd4ef 15808 {
c19d1205 15809 as_bad (_("cannot honor width suffix -- `%s'"), str);
b99bd4ef
NC
15810 return;
15811 }
15812 }
076d447c
PB
15813
15814 /* Something has gone badly wrong if we try to relax a fixed size
15815 instruction. */
9c2799c2 15816 gas_assert (inst.size_req == 0 || !inst.relax);
076d447c 15817
e74cfd16
PB
15818 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
15819 *opcode->tvariant);
ee065d83 15820 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
708587a4 15821 set those bits when Thumb-2 32-bit instructions are seen. ie.
7e806470 15822 anything other than bl/blx and v6-M instructions.
ee065d83 15823 This is overly pessimistic for relaxable instructions. */
7e806470
PB
15824 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
15825 || inst.relax)
e07e6e58
NC
15826 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
15827 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
e74cfd16
PB
15828 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
15829 arm_ext_v6t2);
cd000bff 15830
88714cb8
DG
15831 check_neon_suffixes;
15832
cd000bff 15833 if (!inst.error)
c877a2f2
NC
15834 {
15835 mapping_state (MAP_THUMB);
15836 }
c19d1205 15837 }
3e9e4fcf 15838 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
c19d1205 15839 {
845b51d6
PB
15840 bfd_boolean is_bx;
15841
15842 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15843 is_bx = (opcode->aencode == do_bx);
15844
c19d1205 15845 /* Check that this instruction is supported for this CPU. */
845b51d6
PB
15846 if (!(is_bx && fix_v4bx)
15847 && !(opcode->avariant &&
15848 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
b99bd4ef 15849 {
bf3eeda7 15850 as_bad (_("selected processor does not support ARM mode `%s'"), str);
c19d1205 15851 return;
b99bd4ef 15852 }
c19d1205 15853 if (inst.size_req)
b99bd4ef 15854 {
c19d1205
ZW
15855 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
15856 return;
b99bd4ef
NC
15857 }
15858
c19d1205
ZW
15859 inst.instruction = opcode->avalue;
15860 if (opcode->tag == OT_unconditionalF)
15861 inst.instruction |= 0xF << 28;
15862 else
15863 inst.instruction |= inst.cond << 28;
15864 inst.size = INSN_SIZE;
5be8be5d 15865 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
e07e6e58
NC
15866 {
15867 it_fsm_pre_encode ();
15868 opcode->aencode ();
15869 it_fsm_post_encode ();
15870 }
ee065d83
PB
15871 /* Arm mode bx is marked as both v4T and v5 because it's still required
15872 on a hypothetical non-thumb v5 core. */
845b51d6 15873 if (is_bx)
e74cfd16 15874 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
ee065d83 15875 else
e74cfd16
PB
15876 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
15877 *opcode->avariant);
88714cb8
DG
15878
15879 check_neon_suffixes;
15880
cd000bff 15881 if (!inst.error)
c877a2f2
NC
15882 {
15883 mapping_state (MAP_ARM);
15884 }
b99bd4ef 15885 }
3e9e4fcf
JB
15886 else
15887 {
15888 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
15889 "-- `%s'"), str);
15890 return;
15891 }
c19d1205
ZW
15892 output_inst (str);
15893}
b99bd4ef 15894
e07e6e58
NC
15895static void
15896check_it_blocks_finished (void)
15897{
15898#ifdef OBJ_ELF
15899 asection *sect;
15900
15901 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
15902 if (seg_info (sect)->tc_segment_info_data.current_it.state
15903 == MANUAL_IT_BLOCK)
15904 {
15905 as_warn (_("section '%s' finished with an open IT block."),
15906 sect->name);
15907 }
15908#else
15909 if (now_it.state == MANUAL_IT_BLOCK)
15910 as_warn (_("file finished with an open IT block."));
15911#endif
15912}
15913
c19d1205
ZW
15914/* Various frobbings of labels and their addresses. */
15915
15916void
15917arm_start_line_hook (void)
15918{
15919 last_label_seen = NULL;
b99bd4ef
NC
15920}
15921
c19d1205
ZW
15922void
15923arm_frob_label (symbolS * sym)
b99bd4ef 15924{
c19d1205 15925 last_label_seen = sym;
b99bd4ef 15926
c19d1205 15927 ARM_SET_THUMB (sym, thumb_mode);
b99bd4ef 15928
c19d1205
ZW
15929#if defined OBJ_COFF || defined OBJ_ELF
15930 ARM_SET_INTERWORK (sym, support_interwork);
15931#endif
b99bd4ef 15932
e07e6e58
NC
15933 force_automatic_it_block_close ();
15934
5f4273c7 15935 /* Note - do not allow local symbols (.Lxxx) to be labelled
c19d1205
ZW
15936 as Thumb functions. This is because these labels, whilst
15937 they exist inside Thumb code, are not the entry points for
15938 possible ARM->Thumb calls. Also, these labels can be used
15939 as part of a computed goto or switch statement. eg gcc
15940 can generate code that looks like this:
b99bd4ef 15941
c19d1205
ZW
15942 ldr r2, [pc, .Laaa]
15943 lsl r3, r3, #2
15944 ldr r2, [r3, r2]
15945 mov pc, r2
b99bd4ef 15946
c19d1205
ZW
15947 .Lbbb: .word .Lxxx
15948 .Lccc: .word .Lyyy
15949 ..etc...
15950 .Laaa: .word Lbbb
b99bd4ef 15951
c19d1205
ZW
15952 The first instruction loads the address of the jump table.
15953 The second instruction converts a table index into a byte offset.
15954 The third instruction gets the jump address out of the table.
15955 The fourth instruction performs the jump.
b99bd4ef 15956
c19d1205
ZW
15957 If the address stored at .Laaa is that of a symbol which has the
15958 Thumb_Func bit set, then the linker will arrange for this address
15959 to have the bottom bit set, which in turn would mean that the
15960 address computation performed by the third instruction would end
15961 up with the bottom bit set. Since the ARM is capable of unaligned
15962 word loads, the instruction would then load the incorrect address
15963 out of the jump table, and chaos would ensue. */
15964 if (label_is_thumb_function_name
15965 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
15966 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
b99bd4ef 15967 {
c19d1205
ZW
15968 /* When the address of a Thumb function is taken the bottom
15969 bit of that address should be set. This will allow
15970 interworking between Arm and Thumb functions to work
15971 correctly. */
b99bd4ef 15972
c19d1205 15973 THUMB_SET_FUNC (sym, 1);
b99bd4ef 15974
c19d1205 15975 label_is_thumb_function_name = FALSE;
b99bd4ef 15976 }
07a53e5c 15977
07a53e5c 15978 dwarf2_emit_label (sym);
b99bd4ef
NC
15979}
15980
c921be7d 15981bfd_boolean
c19d1205 15982arm_data_in_code (void)
b99bd4ef 15983{
c19d1205 15984 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
b99bd4ef 15985 {
c19d1205
ZW
15986 *input_line_pointer = '/';
15987 input_line_pointer += 5;
15988 *input_line_pointer = 0;
c921be7d 15989 return TRUE;
b99bd4ef
NC
15990 }
15991
c921be7d 15992 return FALSE;
b99bd4ef
NC
15993}
15994
c19d1205
ZW
15995char *
15996arm_canonicalize_symbol_name (char * name)
b99bd4ef 15997{
c19d1205 15998 int len;
b99bd4ef 15999
c19d1205
ZW
16000 if (thumb_mode && (len = strlen (name)) > 5
16001 && streq (name + len - 5, "/data"))
16002 *(name + len - 5) = 0;
b99bd4ef 16003
c19d1205 16004 return name;
b99bd4ef 16005}
c19d1205
ZW
16006\f
16007/* Table of all register names defined by default. The user can
16008 define additional names with .req. Note that all register names
16009 should appear in both upper and lowercase variants. Some registers
16010 also have mixed-case names. */
b99bd4ef 16011
dcbf9037 16012#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
c19d1205 16013#define REGNUM(p,n,t) REGDEF(p##n, n, t)
5287ad62 16014#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
c19d1205
ZW
16015#define REGSET(p,t) \
16016 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16017 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16018 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16019 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
5287ad62
JB
16020#define REGSETH(p,t) \
16021 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16022 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16023 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16024 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16025#define REGSET2(p,t) \
16026 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16027 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16028 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16029 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
7ed4c4c5 16030
c19d1205 16031static const struct reg_entry reg_names[] =
7ed4c4c5 16032{
c19d1205
ZW
16033 /* ARM integer registers. */
16034 REGSET(r, RN), REGSET(R, RN),
7ed4c4c5 16035
c19d1205
ZW
16036 /* ATPCS synonyms. */
16037 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
16038 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
16039 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
7ed4c4c5 16040
c19d1205
ZW
16041 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
16042 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
16043 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
7ed4c4c5 16044
c19d1205
ZW
16045 /* Well-known aliases. */
16046 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
16047 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
16048
16049 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
16050 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
16051
16052 /* Coprocessor numbers. */
16053 REGSET(p, CP), REGSET(P, CP),
16054
16055 /* Coprocessor register numbers. The "cr" variants are for backward
16056 compatibility. */
16057 REGSET(c, CN), REGSET(C, CN),
16058 REGSET(cr, CN), REGSET(CR, CN),
16059
16060 /* FPA registers. */
16061 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
16062 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
16063
16064 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
16065 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
16066
16067 /* VFP SP registers. */
5287ad62
JB
16068 REGSET(s,VFS), REGSET(S,VFS),
16069 REGSETH(s,VFS), REGSETH(S,VFS),
c19d1205
ZW
16070
16071 /* VFP DP Registers. */
5287ad62
JB
16072 REGSET(d,VFD), REGSET(D,VFD),
16073 /* Extra Neon DP registers. */
16074 REGSETH(d,VFD), REGSETH(D,VFD),
16075
16076 /* Neon QP registers. */
16077 REGSET2(q,NQ), REGSET2(Q,NQ),
c19d1205
ZW
16078
16079 /* VFP control registers. */
16080 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
16081 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
cd2cf30b
PB
16082 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
16083 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
16084 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
16085 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
c19d1205
ZW
16086
16087 /* Maverick DSP coprocessor registers. */
16088 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
16089 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
16090
16091 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
16092 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
16093 REGDEF(dspsc,0,DSPSC),
16094
16095 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
16096 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
16097 REGDEF(DSPSC,0,DSPSC),
16098
16099 /* iWMMXt data registers - p0, c0-15. */
16100 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
16101
16102 /* iWMMXt control registers - p1, c0-3. */
16103 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
16104 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
16105 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
16106 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
16107
16108 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16109 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
16110 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
16111 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
16112 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
16113
16114 /* XScale accumulator registers. */
16115 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
16116};
16117#undef REGDEF
16118#undef REGNUM
16119#undef REGSET
7ed4c4c5 16120
c19d1205
ZW
16121/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16122 within psr_required_here. */
16123static const struct asm_psr psrs[] =
16124{
16125 /* Backward compatibility notation. Note that "all" is no longer
16126 truly all possible PSR bits. */
16127 {"all", PSR_c | PSR_f},
16128 {"flg", PSR_f},
16129 {"ctl", PSR_c},
16130
16131 /* Individual flags. */
16132 {"f", PSR_f},
16133 {"c", PSR_c},
16134 {"x", PSR_x},
16135 {"s", PSR_s},
16136 /* Combinations of flags. */
16137 {"fs", PSR_f | PSR_s},
16138 {"fx", PSR_f | PSR_x},
16139 {"fc", PSR_f | PSR_c},
16140 {"sf", PSR_s | PSR_f},
16141 {"sx", PSR_s | PSR_x},
16142 {"sc", PSR_s | PSR_c},
16143 {"xf", PSR_x | PSR_f},
16144 {"xs", PSR_x | PSR_s},
16145 {"xc", PSR_x | PSR_c},
16146 {"cf", PSR_c | PSR_f},
16147 {"cs", PSR_c | PSR_s},
16148 {"cx", PSR_c | PSR_x},
16149 {"fsx", PSR_f | PSR_s | PSR_x},
16150 {"fsc", PSR_f | PSR_s | PSR_c},
16151 {"fxs", PSR_f | PSR_x | PSR_s},
16152 {"fxc", PSR_f | PSR_x | PSR_c},
16153 {"fcs", PSR_f | PSR_c | PSR_s},
16154 {"fcx", PSR_f | PSR_c | PSR_x},
16155 {"sfx", PSR_s | PSR_f | PSR_x},
16156 {"sfc", PSR_s | PSR_f | PSR_c},
16157 {"sxf", PSR_s | PSR_x | PSR_f},
16158 {"sxc", PSR_s | PSR_x | PSR_c},
16159 {"scf", PSR_s | PSR_c | PSR_f},
16160 {"scx", PSR_s | PSR_c | PSR_x},
16161 {"xfs", PSR_x | PSR_f | PSR_s},
16162 {"xfc", PSR_x | PSR_f | PSR_c},
16163 {"xsf", PSR_x | PSR_s | PSR_f},
16164 {"xsc", PSR_x | PSR_s | PSR_c},
16165 {"xcf", PSR_x | PSR_c | PSR_f},
16166 {"xcs", PSR_x | PSR_c | PSR_s},
16167 {"cfs", PSR_c | PSR_f | PSR_s},
16168 {"cfx", PSR_c | PSR_f | PSR_x},
16169 {"csf", PSR_c | PSR_s | PSR_f},
16170 {"csx", PSR_c | PSR_s | PSR_x},
16171 {"cxf", PSR_c | PSR_x | PSR_f},
16172 {"cxs", PSR_c | PSR_x | PSR_s},
16173 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
16174 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
16175 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
16176 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
16177 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
16178 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
16179 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
16180 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
16181 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
16182 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
16183 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
16184 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
16185 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
16186 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
16187 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
16188 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
16189 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
16190 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
16191 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
16192 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
16193 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
16194 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
16195 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
16196 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
16197};
16198
62b3e311
PB
16199/* Table of V7M psr names. */
16200static const struct asm_psr v7m_psrs[] =
16201{
2b744c99
PB
16202 {"apsr", 0 }, {"APSR", 0 },
16203 {"iapsr", 1 }, {"IAPSR", 1 },
16204 {"eapsr", 2 }, {"EAPSR", 2 },
16205 {"psr", 3 }, {"PSR", 3 },
16206 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16207 {"ipsr", 5 }, {"IPSR", 5 },
16208 {"epsr", 6 }, {"EPSR", 6 },
16209 {"iepsr", 7 }, {"IEPSR", 7 },
16210 {"msp", 8 }, {"MSP", 8 },
16211 {"psp", 9 }, {"PSP", 9 },
16212 {"primask", 16}, {"PRIMASK", 16},
16213 {"basepri", 17}, {"BASEPRI", 17},
16214 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16215 {"faultmask", 19}, {"FAULTMASK", 19},
16216 {"control", 20}, {"CONTROL", 20}
62b3e311
PB
16217};
16218
c19d1205
ZW
16219/* Table of all shift-in-operand names. */
16220static const struct asm_shift_name shift_names [] =
b99bd4ef 16221{
c19d1205
ZW
16222 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
16223 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
16224 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
16225 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
16226 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
16227 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
16228};
b99bd4ef 16229
c19d1205
ZW
16230/* Table of all explicit relocation names. */
16231#ifdef OBJ_ELF
16232static struct reloc_entry reloc_names[] =
16233{
16234 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
16235 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
16236 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
16237 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
16238 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
16239 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
16240 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
16241 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
16242 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
16243 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
b43420e6
NC
16244 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
16245 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL}
c19d1205
ZW
16246};
16247#endif
b99bd4ef 16248
c19d1205
ZW
16249/* Table of all conditional affixes. 0xF is not defined as a condition code. */
16250static const struct asm_cond conds[] =
16251{
16252 {"eq", 0x0},
16253 {"ne", 0x1},
16254 {"cs", 0x2}, {"hs", 0x2},
16255 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16256 {"mi", 0x4},
16257 {"pl", 0x5},
16258 {"vs", 0x6},
16259 {"vc", 0x7},
16260 {"hi", 0x8},
16261 {"ls", 0x9},
16262 {"ge", 0xa},
16263 {"lt", 0xb},
16264 {"gt", 0xc},
16265 {"le", 0xd},
16266 {"al", 0xe}
16267};
bfae80f2 16268
62b3e311
PB
16269static struct asm_barrier_opt barrier_opt_names[] =
16270{
16271 { "sy", 0xf },
16272 { "un", 0x7 },
16273 { "st", 0xe },
16274 { "unst", 0x6 }
16275};
16276
c19d1205
ZW
16277/* Table of ARM-format instructions. */
16278
16279/* Macros for gluing together operand strings. N.B. In all cases
16280 other than OPS0, the trailing OP_stop comes from default
16281 zero-initialization of the unspecified elements of the array. */
16282#define OPS0() { OP_stop, }
16283#define OPS1(a) { OP_##a, }
16284#define OPS2(a,b) { OP_##a,OP_##b, }
16285#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16286#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16287#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16288#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16289
5be8be5d
DG
16290/* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16291 This is useful when mixing operands for ARM and THUMB, i.e. using the
16292 MIX_ARM_THUMB_OPERANDS macro.
16293 In order to use these macros, prefix the number of operands with _
16294 e.g. _3. */
16295#define OPS_1(a) { a, }
16296#define OPS_2(a,b) { a,b, }
16297#define OPS_3(a,b,c) { a,b,c, }
16298#define OPS_4(a,b,c,d) { a,b,c,d, }
16299#define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16300#define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16301
c19d1205
ZW
16302/* These macros abstract out the exact format of the mnemonic table and
16303 save some repeated characters. */
16304
16305/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16306#define TxCE(mnem, op, top, nops, ops, ae, te) \
21d799b5 16307 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
1887dd22 16308 THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW
16309
16310/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16311 a T_MNEM_xyz enumerator. */
16312#define TCE(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 16313 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
c19d1205 16314#define tCE(mnem, aop, top, nops, ops, ae, te) \
21d799b5 16315 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
c19d1205
ZW
16316
16317/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16318 infix after the third character. */
16319#define TxC3(mnem, op, top, nops, ops, ae, te) \
21d799b5 16320 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
1887dd22 16321 THUMB_VARIANT, do_##ae, do_##te }
088fa78e 16322#define TxC3w(mnem, op, top, nops, ops, ae, te) \
21d799b5 16323 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
088fa78e 16324 THUMB_VARIANT, do_##ae, do_##te }
c19d1205 16325#define TC3(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 16326 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
088fa78e 16327#define TC3w(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 16328 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
c19d1205 16329#define tC3(mnem, aop, top, nops, ops, ae, te) \
21d799b5 16330 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
088fa78e 16331#define tC3w(mnem, aop, top, nops, ops, ae, te) \
21d799b5 16332 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
c19d1205
ZW
16333
16334/* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16335 appear in the condition table. */
16336#define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
21d799b5 16337 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
1887dd22 16338 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW
16339
16340#define TxCM(m1, m2, op, top, nops, ops, ae, te) \
e07e6e58
NC
16341 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16342 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16343 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16344 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16345 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16346 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16347 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16348 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16349 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16350 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16351 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16352 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16353 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16354 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16355 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16356 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16357 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16358 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16359 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
c19d1205
ZW
16360
16361#define TCM(m1,m2, aop, top, nops, ops, ae, te) \
e07e6e58
NC
16362 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16363#define tCM(m1,m2, aop, top, nops, ops, ae, te) \
21d799b5 16364 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
c19d1205
ZW
16365
16366/* Mnemonic that cannot be conditionalized. The ARM condition-code
dfa9f0d5
PB
16367 field is still 0xE. Many of the Thumb variants can be executed
16368 conditionally, so this is checked separately. */
c19d1205 16369#define TUE(mnem, op, top, nops, ops, ae, te) \
21d799b5 16370 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
1887dd22 16371 THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW
16372
16373/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16374 condition code field. */
16375#define TUF(mnem, op, top, nops, ops, ae, te) \
21d799b5 16376 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
1887dd22 16377 THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW
16378
16379/* ARM-only variants of all the above. */
6a86118a 16380#define CE(mnem, op, nops, ops, ae) \
21d799b5 16381 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
6a86118a
NC
16382
16383#define C3(mnem, op, nops, ops, ae) \
16384 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16385
e3cb604e
PB
16386/* Legacy mnemonics that always have conditional infix after the third
16387 character. */
16388#define CL(mnem, op, nops, ops, ae) \
21d799b5 16389 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
e3cb604e
PB
16390 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16391
8f06b2d8
PB
16392/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16393#define cCE(mnem, op, nops, ops, ae) \
21d799b5 16394 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8f06b2d8 16395
e3cb604e
PB
16396/* Legacy coprocessor instructions where conditional infix and conditional
16397 suffix are ambiguous. For consistency this includes all FPA instructions,
16398 not just the potentially ambiguous ones. */
16399#define cCL(mnem, op, nops, ops, ae) \
21d799b5 16400 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
e3cb604e
PB
16401 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16402
16403/* Coprocessor, takes either a suffix or a position-3 infix
16404 (for an FPA corner case). */
16405#define C3E(mnem, op, nops, ops, ae) \
21d799b5 16406 { mnem, OPS##nops ops, OT_csuf_or_in3, \
e3cb604e 16407 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8f06b2d8 16408
6a86118a 16409#define xCM_(m1, m2, m3, op, nops, ops, ae) \
21d799b5
NC
16410 { m1 #m2 m3, OPS##nops ops, \
16411 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
6a86118a
NC
16412 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16413
16414#define CM(m1, m2, op, nops, ops, ae) \
e07e6e58
NC
16415 xCM_ (m1, , m2, op, nops, ops, ae), \
16416 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16417 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16418 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16419 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16420 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16421 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16422 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16423 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16424 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16425 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16426 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16427 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16428 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16429 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16430 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16431 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16432 xCM_ (m1, le, m2, op, nops, ops, ae), \
16433 xCM_ (m1, al, m2, op, nops, ops, ae)
6a86118a
NC
16434
16435#define UE(mnem, op, nops, ops, ae) \
16436 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16437
16438#define UF(mnem, op, nops, ops, ae) \
16439 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16440
5287ad62
JB
16441/* Neon data-processing. ARM versions are unconditional with cond=0xf.
16442 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16443 use the same encoding function for each. */
16444#define NUF(mnem, op, nops, ops, enc) \
16445 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16446 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16447
16448/* Neon data processing, version which indirects through neon_enc_tab for
16449 the various overloaded versions of opcodes. */
16450#define nUF(mnem, op, nops, ops, enc) \
21d799b5 16451 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
5287ad62
JB
16452 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16453
16454/* Neon insn with conditional suffix for the ARM version, non-overloaded
16455 version. */
037e8744
JB
16456#define NCE_tag(mnem, op, nops, ops, enc, tag) \
16457 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
5287ad62
JB
16458 THUMB_VARIANT, do_##enc, do_##enc }
16459
037e8744 16460#define NCE(mnem, op, nops, ops, enc) \
e07e6e58 16461 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
037e8744
JB
16462
16463#define NCEF(mnem, op, nops, ops, enc) \
e07e6e58 16464 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
037e8744 16465
5287ad62 16466/* Neon insn with conditional suffix for the ARM version, overloaded types. */
037e8744 16467#define nCE_tag(mnem, op, nops, ops, enc, tag) \
21d799b5 16468 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
5287ad62
JB
16469 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16470
037e8744 16471#define nCE(mnem, op, nops, ops, enc) \
e07e6e58 16472 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
037e8744
JB
16473
16474#define nCEF(mnem, op, nops, ops, enc) \
e07e6e58 16475 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
037e8744 16476
c19d1205
ZW
16477#define do_0 0
16478
c19d1205 16479static const struct asm_opcode insns[] =
bfae80f2 16480{
e74cfd16
PB
16481#define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16482#define THUMB_VARIANT &arm_ext_v4t
21d799b5
NC
16483 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
16484 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
16485 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
16486 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
16487 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
16488 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
16489 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
16490 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
16491 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
16492 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
16493 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
16494 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
16495 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
16496 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
16497 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
16498 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
c19d1205
ZW
16499
16500 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16501 for setting PSR flag bits. They are obsolete in V6 and do not
16502 have Thumb equivalents. */
21d799b5
NC
16503 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
16504 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
16505 CL("tstp", 110f000, 2, (RR, SH), cmp),
16506 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
16507 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
16508 CL("cmpp", 150f000, 2, (RR, SH), cmp),
16509 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
16510 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
16511 CL("cmnp", 170f000, 2, (RR, SH), cmp),
16512
16513 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
16514 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
16515 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
16516 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
16517
16518 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
5be8be5d
DG
16519 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
16520 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
16521 OP_RRnpc),
16522 OP_ADDRGLDR),ldst, t_ldst),
16523 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
21d799b5
NC
16524
16525 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
16526 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
16527 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
16528 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
16529 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
16530 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
16531
16532 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
16533 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
16534 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
16535 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
bfae80f2 16536
c19d1205 16537 /* Pseudo ops. */
21d799b5 16538 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
2fc8bdac 16539 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
21d799b5 16540 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
c19d1205
ZW
16541
16542 /* Thumb-compatibility pseudo ops. */
21d799b5
NC
16543 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
16544 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
16545 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
16546 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
16547 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
16548 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
16549 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
16550 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
16551 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
16552 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
16553 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
16554 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
c19d1205 16555
16a4cf17 16556 /* These may simplify to neg. */
21d799b5
NC
16557 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
16558 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
16a4cf17 16559
c921be7d
NC
16560#undef THUMB_VARIANT
16561#define THUMB_VARIANT & arm_ext_v6
16562
21d799b5 16563 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
c19d1205
ZW
16564
16565 /* V1 instructions with no Thumb analogue prior to V6T2. */
c921be7d
NC
16566#undef THUMB_VARIANT
16567#define THUMB_VARIANT & arm_ext_v6t2
16568
21d799b5
NC
16569 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
16570 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
16571 CL("teqp", 130f000, 2, (RR, SH), cmp),
c19d1205 16572
5be8be5d
DG
16573 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
16574 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
16575 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
16576 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
c19d1205 16577
21d799b5
NC
16578 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
16579 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205 16580
21d799b5
NC
16581 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
16582 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205
ZW
16583
16584 /* V1 instructions with no Thumb analogue at all. */
21d799b5 16585 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
c19d1205
ZW
16586 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
16587
16588 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
16589 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
16590 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
16591 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
16592 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
16593 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
16594 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
16595 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
16596
c921be7d
NC
16597#undef ARM_VARIANT
16598#define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16599#undef THUMB_VARIANT
16600#define THUMB_VARIANT & arm_ext_v4t
16601
21d799b5
NC
16602 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
16603 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
c19d1205 16604
c921be7d
NC
16605#undef THUMB_VARIANT
16606#define THUMB_VARIANT & arm_ext_v6t2
16607
21d799b5 16608 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
c19d1205
ZW
16609 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
16610
16611 /* Generic coprocessor instructions. */
21d799b5
NC
16612 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
16613 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
16614 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
16615 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
16616 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
16617 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
16618 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
c19d1205 16619
c921be7d
NC
16620#undef ARM_VARIANT
16621#define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16622
21d799b5 16623 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
c19d1205
ZW
16624 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
16625
c921be7d
NC
16626#undef ARM_VARIANT
16627#define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16628#undef THUMB_VARIANT
16629#define THUMB_VARIANT & arm_ext_msr
16630
21d799b5
NC
16631 TCE("mrs", 10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs),
16632 TCE("msr", 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr),
c19d1205 16633
c921be7d
NC
16634#undef ARM_VARIANT
16635#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16636#undef THUMB_VARIANT
16637#define THUMB_VARIANT & arm_ext_v6t2
16638
21d799b5
NC
16639 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
16640 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
16641 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
16642 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
16643 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
16644 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
16645 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
16646 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
c19d1205 16647
c921be7d
NC
16648#undef ARM_VARIANT
16649#define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16650#undef THUMB_VARIANT
16651#define THUMB_VARIANT & arm_ext_v4t
16652
5be8be5d
DG
16653 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
16654 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
16655 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
16656 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
16657 tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
16658 tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
c19d1205 16659
c921be7d
NC
16660#undef ARM_VARIANT
16661#define ARM_VARIANT & arm_ext_v4t_5
16662
c19d1205
ZW
16663 /* ARM Architecture 4T. */
16664 /* Note: bx (and blx) are required on V5, even if the processor does
16665 not support Thumb. */
21d799b5 16666 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
c19d1205 16667
c921be7d
NC
16668#undef ARM_VARIANT
16669#define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16670#undef THUMB_VARIANT
16671#define THUMB_VARIANT & arm_ext_v5t
16672
c19d1205
ZW
16673 /* Note: blx has 2 variants; the .value coded here is for
16674 BLX(2). Only this variant has conditional execution. */
21d799b5
NC
16675 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
16676 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
c19d1205 16677
c921be7d
NC
16678#undef THUMB_VARIANT
16679#define THUMB_VARIANT & arm_ext_v6t2
16680
21d799b5
NC
16681 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
16682 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
16683 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
16684 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
16685 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
16686 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
16687 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
16688 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
c19d1205 16689
c921be7d
NC
16690#undef ARM_VARIANT
16691#define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
9e3c6df6
PB
16692#undef THUMB_VARIANT
16693#define THUMB_VARIANT &arm_ext_v5exp
c921be7d 16694
21d799b5
NC
16695 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
16696 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
16697 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
16698 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
c19d1205 16699
21d799b5
NC
16700 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
16701 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
c19d1205 16702
21d799b5
NC
16703 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
16704 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
16705 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
16706 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
c19d1205 16707
21d799b5
NC
16708 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
16709 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
16710 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
16711 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
c19d1205 16712
21d799b5
NC
16713 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
16714 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
c19d1205 16715
03ee1b7f
NC
16716 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
16717 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
16718 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
16719 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
c19d1205 16720
c921be7d
NC
16721#undef ARM_VARIANT
16722#define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
9e3c6df6
PB
16723#undef THUMB_VARIANT
16724#define THUMB_VARIANT &arm_ext_v6t2
c921be7d 16725
21d799b5 16726 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
5be8be5d
DG
16727 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
16728 ldrd, t_ldstd),
16729 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
16730 ADDRGLDRS), ldrd, t_ldstd),
c19d1205 16731
21d799b5
NC
16732 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
16733 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
c19d1205 16734
c921be7d
NC
16735#undef ARM_VARIANT
16736#define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16737
21d799b5 16738 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
c19d1205 16739
c921be7d
NC
16740#undef ARM_VARIANT
16741#define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16742#undef THUMB_VARIANT
16743#define THUMB_VARIANT & arm_ext_v6
16744
21d799b5
NC
16745 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
16746 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
16747 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
16748 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
16749 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
16750 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
16751 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
16752 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
16753 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
16754 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
c19d1205 16755
c921be7d
NC
16756#undef THUMB_VARIANT
16757#define THUMB_VARIANT & arm_ext_v6t2
16758
5be8be5d
DG
16759 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
16760 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
16761 strex, t_strex),
21d799b5
NC
16762 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
16763 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
62b3e311 16764
21d799b5
NC
16765 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
16766 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
62b3e311 16767
9e3c6df6 16768/* ARM V6 not included in V7M. */
c921be7d
NC
16769#undef THUMB_VARIANT
16770#define THUMB_VARIANT & arm_ext_v6_notm
9e3c6df6
PB
16771 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
16772 UF(rfeib, 9900a00, 1, (RRw), rfe),
16773 UF(rfeda, 8100a00, 1, (RRw), rfe),
16774 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
16775 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
16776 UF(rfefa, 9900a00, 1, (RRw), rfe),
16777 UF(rfeea, 8100a00, 1, (RRw), rfe),
16778 TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe),
16779 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
16780 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
16781 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
16782 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
c921be7d 16783
9e3c6df6
PB
16784/* ARM V6 not included in V7M (eg. integer SIMD). */
16785#undef THUMB_VARIANT
16786#define THUMB_VARIANT & arm_ext_v6_dsp
21d799b5
NC
16787 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
16788 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
16789 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
16790 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16791 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16792 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 16793 /* Old name for QASX. */
21d799b5
NC
16794 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16795 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 16796 /* Old name for QSAX. */
21d799b5
NC
16797 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16798 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16799 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16800 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16801 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16802 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 16803 /* Old name for SASX. */
21d799b5
NC
16804 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16805 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16806 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16807 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 16808 /* Old name for SHASX. */
21d799b5
NC
16809 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16810 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 16811 /* Old name for SHSAX. */
21d799b5
NC
16812 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16813 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16814 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16815 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 16816 /* Old name for SSAX. */
21d799b5
NC
16817 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16818 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16819 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16820 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16821 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16822 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 16823 /* Old name for UASX. */
21d799b5
NC
16824 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16825 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16826 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16827 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 16828 /* Old name for UHASX. */
21d799b5
NC
16829 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16830 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 16831 /* Old name for UHSAX. */
21d799b5
NC
16832 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16833 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16834 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16835 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16836 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16837 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 16838 /* Old name for UQASX. */
21d799b5
NC
16839 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16840 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 16841 /* Old name for UQSAX. */
21d799b5
NC
16842 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16843 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16844 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16845 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16846 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 16847 /* Old name for USAX. */
21d799b5
NC
16848 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16849 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC
16850 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
16851 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
16852 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
16853 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
16854 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
16855 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
16856 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
16857 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
16858 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
16859 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
16860 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
16861 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
16862 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
16863 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
16864 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
16865 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
16866 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
16867 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
16868 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
16869 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
16870 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
16871 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
16872 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
16873 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
16874 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
16875 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
16876 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
21d799b5
NC
16877 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
16878 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
16879 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
16880 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
16881 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
c19d1205 16882
c921be7d
NC
16883#undef ARM_VARIANT
16884#define ARM_VARIANT & arm_ext_v6k
16885#undef THUMB_VARIANT
16886#define THUMB_VARIANT & arm_ext_v6k
16887
21d799b5
NC
16888 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
16889 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
16890 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
16891 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
c19d1205 16892
c921be7d
NC
16893#undef THUMB_VARIANT
16894#define THUMB_VARIANT & arm_ext_v6_notm
5be8be5d
DG
16895 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
16896 ldrexd, t_ldrexd),
16897 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
16898 RRnpcb), strexd, t_strexd),
ebdca51a 16899
c921be7d
NC
16900#undef THUMB_VARIANT
16901#define THUMB_VARIANT & arm_ext_v6t2
5be8be5d
DG
16902 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
16903 rd_rn, rd_rn),
16904 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
16905 rd_rn, rd_rn),
16906 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
16907 strex, rm_rd_rn),
16908 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
16909 strex, rm_rd_rn),
21d799b5 16910 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
c19d1205 16911
c921be7d
NC
16912#undef ARM_VARIANT
16913#define ARM_VARIANT & arm_ext_v6z
16914
21d799b5 16915 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
c19d1205 16916
c921be7d
NC
16917#undef ARM_VARIANT
16918#define ARM_VARIANT & arm_ext_v6t2
16919
21d799b5
NC
16920 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
16921 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
16922 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
16923 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
c19d1205 16924
21d799b5
NC
16925 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
16926 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
16927 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
16928 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
c19d1205 16929
5be8be5d
DG
16930 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
16931 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
16932 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
16933 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
c19d1205 16934
bf3eeda7
NS
16935 /* Thumb-only instructions. */
16936#undef ARM_VARIANT
16937#define ARM_VARIANT NULL
16938 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
16939 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
c921be7d
NC
16940
16941 /* ARM does not really have an IT instruction, so always allow it.
16942 The opcode is copied from Thumb in order to allow warnings in
16943 -mimplicit-it=[never | arm] modes. */
16944#undef ARM_VARIANT
16945#define ARM_VARIANT & arm_ext_v1
16946
21d799b5
NC
16947 TUE("it", bf08, bf08, 1, (COND), it, t_it),
16948 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
16949 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
16950 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
16951 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
16952 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
16953 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
16954 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
16955 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
16956 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
16957 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
16958 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
16959 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
16960 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
16961 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
1c444d06 16962 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
21d799b5
NC
16963 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
16964 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
c19d1205 16965
92e90b6e 16966 /* Thumb2 only instructions. */
c921be7d
NC
16967#undef ARM_VARIANT
16968#define ARM_VARIANT NULL
92e90b6e 16969
21d799b5
NC
16970 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
16971 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
16972 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
16973 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
16974 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
16975 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
92e90b6e 16976
62b3e311 16977 /* Thumb-2 hardware division instructions (R and M profiles only). */
c921be7d
NC
16978#undef THUMB_VARIANT
16979#define THUMB_VARIANT & arm_ext_div
16980
21d799b5
NC
16981 TCE("sdiv", 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div),
16982 TCE("udiv", 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div),
62b3e311 16983
7e806470 16984 /* ARM V6M/V7 instructions. */
c921be7d
NC
16985#undef ARM_VARIANT
16986#define ARM_VARIANT & arm_ext_barrier
16987#undef THUMB_VARIANT
16988#define THUMB_VARIANT & arm_ext_barrier
16989
21d799b5
NC
16990 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier),
16991 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier),
16992 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier),
7e806470 16993
62b3e311 16994 /* ARM V7 instructions. */
c921be7d
NC
16995#undef ARM_VARIANT
16996#define ARM_VARIANT & arm_ext_v7
16997#undef THUMB_VARIANT
16998#define THUMB_VARIANT & arm_ext_v7
16999
21d799b5
NC
17000 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
17001 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
62b3e311 17002
c921be7d
NC
17003#undef ARM_VARIANT
17004#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17005
21d799b5
NC
17006 cCE("wfs", e200110, 1, (RR), rd),
17007 cCE("rfs", e300110, 1, (RR), rd),
17008 cCE("wfc", e400110, 1, (RR), rd),
17009 cCE("rfc", e500110, 1, (RR), rd),
17010
17011 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
17012 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
17013 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
17014 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
17015
17016 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
17017 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
17018 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
17019 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
17020
17021 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
17022 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
17023 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
17024 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
17025 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
17026 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
17027 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
17028 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
17029 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
17030 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
17031 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
17032 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
17033
17034 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
17035 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
17036 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
17037 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
17038 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
17039 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
17040 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
17041 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
17042 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
17043 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
17044 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
17045 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
17046
17047 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
17048 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
17049 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
17050 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
17051 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
17052 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
17053 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
17054 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
17055 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
17056 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
17057 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
17058 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
17059
17060 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
17061 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
17062 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
17063 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
17064 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
17065 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
17066 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
17067 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
17068 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
17069 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
17070 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
17071 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
17072
17073 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
17074 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
17075 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
17076 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
17077 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
17078 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
17079 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
17080 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
17081 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
17082 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
17083 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
17084 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
17085
17086 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
17087 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
17088 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
17089 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
17090 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
17091 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
17092 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
17093 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
17094 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
17095 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
17096 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
17097 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
17098
17099 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
17100 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
17101 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
17102 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
17103 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
17104 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
17105 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
17106 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
17107 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
17108 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
17109 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
17110 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
17111
17112 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
17113 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
17114 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
17115 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
17116 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
17117 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
17118 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
17119 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
17120 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
17121 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
17122 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
17123 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
17124
17125 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
17126 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
17127 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
17128 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
17129 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
17130 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
17131 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
17132 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
17133 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
17134 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
17135 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
17136 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
17137
17138 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
17139 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
17140 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
17141 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
17142 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
17143 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
17144 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
17145 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
17146 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
17147 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
17148 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
17149 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
17150
17151 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
17152 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
17153 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
17154 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
17155 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
17156 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
17157 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
17158 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
17159 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
17160 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
17161 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
17162 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
17163
17164 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
17165 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
17166 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
17167 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
17168 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
17169 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
17170 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
17171 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
17172 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
17173 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
17174 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
17175 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
17176
17177 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
17178 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
17179 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
17180 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
17181 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
17182 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
17183 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
17184 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
17185 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
17186 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
17187 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
17188 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
17189
17190 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
17191 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
17192 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
17193 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
17194 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
17195 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
17196 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
17197 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
17198 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
17199 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
17200 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
17201 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
17202
17203 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
17204 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
17205 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
17206 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
17207 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
17208 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
17209 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
17210 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
17211 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
17212 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
17213 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
17214 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
17215
17216 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
17217 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
17218 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
17219 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
17220 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
17221 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
17222 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
17223 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
17224 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
17225 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
17226 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
17227 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
17228
17229 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
17230 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
17231 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
17232 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
17233 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
17234 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17235 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17236 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17237 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
17238 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
17239 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
17240 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
17241
17242 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
17243 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
17244 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
17245 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
17246 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
17247 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17248 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17249 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17250 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
17251 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
17252 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
17253 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
17254
17255 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
17256 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
17257 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
17258 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
17259 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
17260 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17261 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17262 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17263 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
17264 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
17265 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
17266 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
17267
17268 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
17269 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
17270 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
17271 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
17272 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
17273 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17274 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17275 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17276 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
17277 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
17278 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
17279 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
17280
17281 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
17282 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
17283 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
17284 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
17285 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
17286 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17287 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17288 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17289 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
17290 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
17291 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
17292 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
17293
17294 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
17295 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
17296 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
17297 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
17298 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
17299 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17300 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17301 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17302 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
17303 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
17304 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
17305 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
17306
17307 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
17308 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
17309 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
17310 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
17311 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
17312 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17313 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17314 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17315 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
17316 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
17317 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
17318 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
17319
17320 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
17321 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
17322 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
17323 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
17324 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
17325 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17326 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17327 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17328 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
17329 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
17330 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
17331 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
17332
17333 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
17334 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
17335 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
17336 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
17337 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
17338 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17339 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17340 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17341 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
17342 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
17343 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
17344 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
17345
17346 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
17347 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
17348 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
17349 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
17350 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
17351 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17352 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17353 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17354 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
17355 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
17356 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
17357 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
17358
17359 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
17360 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
17361 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
17362 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
17363 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
17364 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17365 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17366 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17367 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
17368 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
17369 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
17370 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
17371
17372 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
17373 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
17374 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
17375 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
17376 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
17377 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17378 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17379 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17380 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
17381 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
17382 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
17383 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
17384
17385 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
17386 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
17387 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
17388 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
17389 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
17390 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17391 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17392 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17393 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
17394 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
17395 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
17396 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
17397
17398 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
17399 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
17400 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
17401 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
17402
17403 cCL("flts", e000110, 2, (RF, RR), rn_rd),
17404 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
17405 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
17406 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
17407 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
17408 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
17409 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
17410 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
17411 cCL("flte", e080110, 2, (RF, RR), rn_rd),
17412 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
17413 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
17414 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
b99bd4ef 17415
c19d1205
ZW
17416 /* The implementation of the FIX instruction is broken on some
17417 assemblers, in that it accepts a precision specifier as well as a
17418 rounding specifier, despite the fact that this is meaningless.
17419 To be more compatible, we accept it as well, though of course it
17420 does not set any bits. */
21d799b5
NC
17421 cCE("fix", e100110, 2, (RR, RF), rd_rm),
17422 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
17423 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
17424 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
17425 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
17426 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
17427 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
17428 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
17429 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
17430 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
17431 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
17432 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
17433 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
bfae80f2 17434
c19d1205 17435 /* Instructions that were new with the real FPA, call them V2. */
c921be7d
NC
17436#undef ARM_VARIANT
17437#define ARM_VARIANT & fpu_fpa_ext_v2
17438
21d799b5
NC
17439 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
17440 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
17441 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
17442 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
17443 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
17444 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
c19d1205 17445
c921be7d
NC
17446#undef ARM_VARIANT
17447#define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17448
c19d1205 17449 /* Moves and type conversions. */
21d799b5
NC
17450 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
17451 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
17452 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
17453 cCE("fmstat", ef1fa10, 0, (), noargs),
f7c21dc7
NC
17454 cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs),
17455 cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr),
21d799b5
NC
17456 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
17457 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
17458 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
17459 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
17460 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
17461 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
17462 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
17463 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
c19d1205
ZW
17464
17465 /* Memory operations. */
21d799b5
NC
17466 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
17467 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
55881a11
MGD
17468 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
17469 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
17470 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
17471 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
17472 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
17473 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
17474 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
17475 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
17476 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
17477 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
17478 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
17479 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
17480 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
17481 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
17482 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
17483 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
bfae80f2 17484
c19d1205 17485 /* Monadic operations. */
21d799b5
NC
17486 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
17487 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
17488 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
c19d1205
ZW
17489
17490 /* Dyadic operations. */
21d799b5
NC
17491 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
17492 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
17493 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
17494 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
17495 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
17496 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
17497 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
17498 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
17499 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
b99bd4ef 17500
c19d1205 17501 /* Comparisons. */
21d799b5
NC
17502 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
17503 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
17504 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
17505 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
b99bd4ef 17506
62f3b8c8
PB
17507 /* Double precision load/store are still present on single precision
17508 implementations. */
17509 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
17510 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
55881a11
MGD
17511 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
17512 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
17513 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
17514 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
17515 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
17516 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
17517 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
17518 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
62f3b8c8 17519
c921be7d
NC
17520#undef ARM_VARIANT
17521#define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17522
c19d1205 17523 /* Moves and type conversions. */
21d799b5
NC
17524 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
17525 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
17526 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
17527 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
17528 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
17529 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
17530 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
17531 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
17532 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
17533 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
17534 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
17535 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
17536 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
c19d1205 17537
c19d1205 17538 /* Monadic operations. */
21d799b5
NC
17539 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
17540 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
17541 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
c19d1205
ZW
17542
17543 /* Dyadic operations. */
21d799b5
NC
17544 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
17545 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
17546 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
17547 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
17548 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
17549 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
17550 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
17551 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
17552 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
b99bd4ef 17553
c19d1205 17554 /* Comparisons. */
21d799b5
NC
17555 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
17556 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
17557 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
17558 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
c19d1205 17559
c921be7d
NC
17560#undef ARM_VARIANT
17561#define ARM_VARIANT & fpu_vfp_ext_v2
17562
21d799b5
NC
17563 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
17564 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
17565 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
17566 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
5287ad62 17567
037e8744
JB
17568/* Instructions which may belong to either the Neon or VFP instruction sets.
17569 Individual encoder functions perform additional architecture checks. */
c921be7d
NC
17570#undef ARM_VARIANT
17571#define ARM_VARIANT & fpu_vfp_ext_v1xd
17572#undef THUMB_VARIANT
17573#define THUMB_VARIANT & fpu_vfp_ext_v1xd
17574
037e8744
JB
17575 /* These mnemonics are unique to VFP. */
17576 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
17577 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
21d799b5
NC
17578 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
17579 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
17580 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
17581 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
17582 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
037e8744
JB
17583 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
17584 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
17585 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
17586
17587 /* Mnemonics shared by Neon and VFP. */
21d799b5
NC
17588 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
17589 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
17590 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
037e8744 17591
21d799b5
NC
17592 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
17593 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
037e8744
JB
17594
17595 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
17596 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
17597
55881a11
MGD
17598 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
17599 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
17600 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
17601 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
17602 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
17603 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
4962c51a
MS
17604 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
17605 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
037e8744 17606
e3e535bc
NC
17607 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt),
17608 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
21d799b5
NC
17609 nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
17610 nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
f31fef98 17611
037e8744
JB
17612
17613 /* NOTE: All VMOV encoding is special-cased! */
17614 NCE(vmov, 0, 1, (VMOV), neon_mov),
17615 NCE(vmovq, 0, 1, (VMOV), neon_mov),
17616
c921be7d
NC
17617#undef THUMB_VARIANT
17618#define THUMB_VARIANT & fpu_neon_ext_v1
17619#undef ARM_VARIANT
17620#define ARM_VARIANT & fpu_neon_ext_v1
17621
5287ad62
JB
17622 /* Data processing with three registers of the same length. */
17623 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17624 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
17625 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
17626 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
17627 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
17628 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
17629 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
17630 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
17631 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
17632 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17633 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
17634 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
17635 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
17636 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
627907b7
JB
17637 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
17638 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
17639 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
17640 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
5287ad62
JB
17641 /* If not immediate, fall back to neon_dyadic_i64_su.
17642 shl_imm should accept I8 I16 I32 I64,
17643 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
21d799b5
NC
17644 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
17645 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
17646 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
17647 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
5287ad62 17648 /* Logic ops, types optional & ignored. */
4316f0d2
DG
17649 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
17650 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
17651 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
17652 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
17653 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
17654 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
17655 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
17656 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
17657 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
17658 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
5287ad62
JB
17659 /* Bitfield ops, untyped. */
17660 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
17661 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
17662 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
17663 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
17664 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
17665 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
17666 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
21d799b5
NC
17667 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
17668 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
17669 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
17670 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
17671 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
17672 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
5287ad62
JB
17673 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17674 back to neon_dyadic_if_su. */
21d799b5
NC
17675 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
17676 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
17677 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
17678 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
17679 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
17680 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
17681 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
17682 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
428e3f1f 17683 /* Comparison. Type I8 I16 I32 F32. */
21d799b5
NC
17684 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
17685 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
5287ad62 17686 /* As above, D registers only. */
21d799b5
NC
17687 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
17688 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
5287ad62 17689 /* Int and float variants, signedness unimportant. */
21d799b5
NC
17690 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
17691 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
17692 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
5287ad62 17693 /* Add/sub take types I8 I16 I32 I64 F32. */
21d799b5
NC
17694 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
17695 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
5287ad62
JB
17696 /* vtst takes sizes 8, 16, 32. */
17697 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
17698 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
17699 /* VMUL takes I8 I16 I32 F32 P8. */
21d799b5 17700 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
5287ad62 17701 /* VQD{R}MULH takes S16 S32. */
21d799b5
NC
17702 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
17703 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
17704 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
17705 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
5287ad62
JB
17706 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
17707 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
17708 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
17709 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
92559b5b
PB
17710 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
17711 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
17712 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
17713 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
5287ad62
JB
17714 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
17715 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
17716 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
17717 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
17718
17719 /* Two address, int/float. Types S8 S16 S32 F32. */
5287ad62 17720 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
5287ad62
JB
17721 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
17722
17723 /* Data processing with two registers and a shift amount. */
17724 /* Right shifts, and variants with rounding.
17725 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17726 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
17727 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
17728 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
17729 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
17730 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
17731 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
17732 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
17733 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
17734 /* Shift and insert. Sizes accepted 8 16 32 64. */
17735 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
17736 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
17737 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
17738 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
17739 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17740 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
17741 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
17742 /* Right shift immediate, saturating & narrowing, with rounding variants.
17743 Types accepted S16 S32 S64 U16 U32 U64. */
17744 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
17745 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
17746 /* As above, unsigned. Types accepted S16 S32 S64. */
17747 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
17748 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
17749 /* Right shift narrowing. Types accepted I16 I32 I64. */
17750 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
17751 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
17752 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
21d799b5 17753 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
5287ad62 17754 /* CVT with optional immediate for fixed-point variant. */
21d799b5 17755 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
b7fc2769 17756
4316f0d2
DG
17757 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
17758 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
5287ad62
JB
17759
17760 /* Data processing, three registers of different lengths. */
17761 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17762 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
17763 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
17764 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
17765 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
17766 /* If not scalar, fall back to neon_dyadic_long.
17767 Vector types as above, scalar types S16 S32 U16 U32. */
21d799b5
NC
17768 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
17769 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
5287ad62
JB
17770 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17771 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
17772 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
17773 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17774 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
17775 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
17776 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
17777 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
17778 /* Saturating doubling multiplies. Types S16 S32. */
21d799b5
NC
17779 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
17780 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
17781 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
5287ad62
JB
17782 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17783 S16 S32 U16 U32. */
21d799b5 17784 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
5287ad62
JB
17785
17786 /* Extract. Size 8. */
3b8d421e
PB
17787 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
17788 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
5287ad62
JB
17789
17790 /* Two registers, miscellaneous. */
17791 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17792 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
17793 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
17794 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
17795 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
17796 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
17797 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
17798 /* Vector replicate. Sizes 8 16 32. */
21d799b5
NC
17799 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
17800 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
5287ad62
JB
17801 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17802 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
17803 /* VMOVN. Types I16 I32 I64. */
21d799b5 17804 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
5287ad62 17805 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21d799b5 17806 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
5287ad62 17807 /* VQMOVUN. Types S16 S32 S64. */
21d799b5 17808 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
5287ad62
JB
17809 /* VZIP / VUZP. Sizes 8 16 32. */
17810 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
17811 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
17812 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
17813 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
17814 /* VQABS / VQNEG. Types S8 S16 S32. */
17815 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
17816 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
17817 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
17818 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
17819 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17820 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
17821 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
17822 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
17823 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
17824 /* Reciprocal estimates. Types U32 F32. */
17825 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
17826 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
17827 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
17828 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
17829 /* VCLS. Types S8 S16 S32. */
17830 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
17831 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
17832 /* VCLZ. Types I8 I16 I32. */
17833 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
17834 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
17835 /* VCNT. Size 8. */
17836 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
17837 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
17838 /* Two address, untyped. */
17839 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
17840 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
17841 /* VTRN. Sizes 8 16 32. */
21d799b5
NC
17842 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
17843 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
5287ad62
JB
17844
17845 /* Table lookup. Size 8. */
17846 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
17847 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
17848
c921be7d
NC
17849#undef THUMB_VARIANT
17850#define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
17851#undef ARM_VARIANT
17852#define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
17853
5287ad62 17854 /* Neon element/structure load/store. */
21d799b5
NC
17855 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
17856 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
17857 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
17858 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
17859 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
17860 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
17861 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
17862 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
5287ad62 17863
c921be7d 17864#undef THUMB_VARIANT
62f3b8c8
PB
17865#define THUMB_VARIANT &fpu_vfp_ext_v3xd
17866#undef ARM_VARIANT
17867#define ARM_VARIANT &fpu_vfp_ext_v3xd
17868 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
17869 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
17870 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
17871 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
17872 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
17873 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
17874 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
17875 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
17876 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
17877
17878#undef THUMB_VARIANT
c921be7d
NC
17879#define THUMB_VARIANT & fpu_vfp_ext_v3
17880#undef ARM_VARIANT
17881#define ARM_VARIANT & fpu_vfp_ext_v3
17882
21d799b5 17883 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
21d799b5 17884 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 17885 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 17886 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 17887 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 17888 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 17889 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 17890 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 17891 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
c19d1205 17892
62f3b8c8
PB
17893#undef ARM_VARIANT
17894#define ARM_VARIANT &fpu_vfp_ext_fma
17895#undef THUMB_VARIANT
17896#define THUMB_VARIANT &fpu_vfp_ext_fma
17897 /* Mnemonics shared by Neon and VFP. These are included in the
17898 VFP FMA variant; NEON and VFP FMA always includes the NEON
17899 FMA instructions. */
17900 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
17901 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
17902 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
17903 the v form should always be used. */
17904 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
17905 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
17906 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
17907 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
17908 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
17909 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
17910
5287ad62 17911#undef THUMB_VARIANT
c921be7d
NC
17912#undef ARM_VARIANT
17913#define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
17914
21d799b5
NC
17915 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
17916 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
17917 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
17918 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
17919 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
17920 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
17921 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
17922 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
c19d1205 17923
c921be7d
NC
17924#undef ARM_VARIANT
17925#define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
17926
21d799b5
NC
17927 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
17928 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
17929 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
17930 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
17931 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
17932 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
17933 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
17934 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
17935 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
17936 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
17937 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
17938 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
17939 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
17940 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
17941 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
17942 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
17943 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
17944 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
17945 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
17946 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
17947 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
17948 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
17949 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
17950 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
17951 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
17952 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
17953 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
17954 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
17955 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
17956 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
17957 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
17958 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
17959 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
17960 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
17961 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
17962 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
17963 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
17964 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17965 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17966 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17967 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17968 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17969 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17970 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17971 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17972 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17973 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
17974 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17975 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17976 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17977 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17978 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17979 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17980 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17981 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17982 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17983 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17984 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17985 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17986 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17987 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17988 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17989 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17990 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17991 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17992 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17993 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
17994 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
17995 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
17996 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
17997 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17998 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
17999 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18000 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18001 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18002 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18003 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18004 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18005 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18006 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18007 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18008 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18009 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18010 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18011 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18012 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18013 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18014 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18015 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
18016 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18017 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18018 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18019 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18020 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18021 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18022 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18023 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18024 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18025 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18026 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18027 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18028 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18029 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18030 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18031 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18032 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18033 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18034 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18035 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18036 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18037 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
18038 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18039 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18040 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18041 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18042 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18043 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18044 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18045 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18046 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18047 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18048 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18049 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18050 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18051 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18052 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18053 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18054 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18055 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18056 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18057 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18058 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18059 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18060 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18061 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18062 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18063 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18064 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18065 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18066 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18067 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18068 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18069 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
18070 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
18071 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
18072 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
18073 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
18074 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
18075 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18076 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18077 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18078 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
18079 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
18080 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
18081 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
18082 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
18083 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
18084 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18085 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18086 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18087 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18088 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
c19d1205 18089
c921be7d
NC
18090#undef ARM_VARIANT
18091#define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18092
21d799b5
NC
18093 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
18094 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
18095 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
18096 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
18097 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
18098 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
18099 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18100 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18101 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18102 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18103 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18104 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18105 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18106 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18107 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18108 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18109 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18110 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18111 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18112 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18113 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
18114 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18115 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18116 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18117 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18118 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18119 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18120 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18121 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18122 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18123 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18124 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18125 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18126 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18127 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18128 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18129 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18130 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18131 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18132 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18133 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18134 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18135 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18136 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18137 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18138 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18139 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18140 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18141 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18142 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18143 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18144 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18145 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18146 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18147 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18148 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18149 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
2d447fca 18150
c921be7d
NC
18151#undef ARM_VARIANT
18152#define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18153
21d799b5
NC
18154 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18155 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18156 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18157 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18158 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18159 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18160 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18161 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18162 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
18163 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
18164 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
18165 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
18166 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
18167 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
18168 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
18169 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
18170 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
18171 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
18172 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
18173 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
18174 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
18175 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
18176 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
18177 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
18178 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
18179 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
18180 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
18181 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
18182 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
18183 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
18184 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
18185 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
18186 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
18187 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
18188 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
18189 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
18190 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
18191 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
18192 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
18193 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
18194 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
18195 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
18196 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
18197 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
18198 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
18199 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
18200 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
18201 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
18202 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
18203 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
18204 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
18205 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
18206 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
18207 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
18208 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
18209 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
18210 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
18211 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
18212 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
18213 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
18214 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
18215 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
18216 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
18217 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
18218 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18219 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18220 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18221 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18222 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18223 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18224 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18225 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18226 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18227 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18228 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18229 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
c19d1205
ZW
18230};
18231#undef ARM_VARIANT
18232#undef THUMB_VARIANT
18233#undef TCE
18234#undef TCM
18235#undef TUE
18236#undef TUF
18237#undef TCC
8f06b2d8 18238#undef cCE
e3cb604e
PB
18239#undef cCL
18240#undef C3E
c19d1205
ZW
18241#undef CE
18242#undef CM
18243#undef UE
18244#undef UF
18245#undef UT
5287ad62
JB
18246#undef NUF
18247#undef nUF
18248#undef NCE
18249#undef nCE
c19d1205
ZW
18250#undef OPS0
18251#undef OPS1
18252#undef OPS2
18253#undef OPS3
18254#undef OPS4
18255#undef OPS5
18256#undef OPS6
18257#undef do_0
18258\f
18259/* MD interface: bits in the object file. */
bfae80f2 18260
c19d1205
ZW
18261/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18262 for use in the a.out file, and stores them in the array pointed to by buf.
18263 This knows about the endian-ness of the target machine and does
18264 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18265 2 (short) and 4 (long) Floating numbers are put out as a series of
18266 LITTLENUMS (shorts, here at least). */
b99bd4ef 18267
c19d1205
ZW
18268void
18269md_number_to_chars (char * buf, valueT val, int n)
18270{
18271 if (target_big_endian)
18272 number_to_chars_bigendian (buf, val, n);
18273 else
18274 number_to_chars_littleendian (buf, val, n);
bfae80f2
RE
18275}
18276
c19d1205
ZW
18277static valueT
18278md_chars_to_number (char * buf, int n)
bfae80f2 18279{
c19d1205
ZW
18280 valueT result = 0;
18281 unsigned char * where = (unsigned char *) buf;
bfae80f2 18282
c19d1205 18283 if (target_big_endian)
b99bd4ef 18284 {
c19d1205
ZW
18285 while (n--)
18286 {
18287 result <<= 8;
18288 result |= (*where++ & 255);
18289 }
b99bd4ef 18290 }
c19d1205 18291 else
b99bd4ef 18292 {
c19d1205
ZW
18293 while (n--)
18294 {
18295 result <<= 8;
18296 result |= (where[n] & 255);
18297 }
bfae80f2 18298 }
b99bd4ef 18299
c19d1205 18300 return result;
bfae80f2 18301}
b99bd4ef 18302
c19d1205 18303/* MD interface: Sections. */
b99bd4ef 18304
0110f2b8
PB
18305/* Estimate the size of a frag before relaxing. Assume everything fits in
18306 2 bytes. */
18307
c19d1205 18308int
0110f2b8 18309md_estimate_size_before_relax (fragS * fragp,
c19d1205
ZW
18310 segT segtype ATTRIBUTE_UNUSED)
18311{
0110f2b8
PB
18312 fragp->fr_var = 2;
18313 return 2;
18314}
18315
18316/* Convert a machine dependent frag. */
18317
18318void
18319md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
18320{
18321 unsigned long insn;
18322 unsigned long old_op;
18323 char *buf;
18324 expressionS exp;
18325 fixS *fixp;
18326 int reloc_type;
18327 int pc_rel;
18328 int opcode;
18329
18330 buf = fragp->fr_literal + fragp->fr_fix;
18331
18332 old_op = bfd_get_16(abfd, buf);
5f4273c7
NC
18333 if (fragp->fr_symbol)
18334 {
0110f2b8
PB
18335 exp.X_op = O_symbol;
18336 exp.X_add_symbol = fragp->fr_symbol;
5f4273c7
NC
18337 }
18338 else
18339 {
0110f2b8 18340 exp.X_op = O_constant;
5f4273c7 18341 }
0110f2b8
PB
18342 exp.X_add_number = fragp->fr_offset;
18343 opcode = fragp->fr_subtype;
18344 switch (opcode)
18345 {
18346 case T_MNEM_ldr_pc:
18347 case T_MNEM_ldr_pc2:
18348 case T_MNEM_ldr_sp:
18349 case T_MNEM_str_sp:
18350 case T_MNEM_ldr:
18351 case T_MNEM_ldrb:
18352 case T_MNEM_ldrh:
18353 case T_MNEM_str:
18354 case T_MNEM_strb:
18355 case T_MNEM_strh:
18356 if (fragp->fr_var == 4)
18357 {
5f4273c7 18358 insn = THUMB_OP32 (opcode);
0110f2b8
PB
18359 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
18360 {
18361 insn |= (old_op & 0x700) << 4;
18362 }
18363 else
18364 {
18365 insn |= (old_op & 7) << 12;
18366 insn |= (old_op & 0x38) << 13;
18367 }
18368 insn |= 0x00000c00;
18369 put_thumb32_insn (buf, insn);
18370 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
18371 }
18372 else
18373 {
18374 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
18375 }
18376 pc_rel = (opcode == T_MNEM_ldr_pc2);
18377 break;
18378 case T_MNEM_adr:
18379 if (fragp->fr_var == 4)
18380 {
18381 insn = THUMB_OP32 (opcode);
18382 insn |= (old_op & 0xf0) << 4;
18383 put_thumb32_insn (buf, insn);
18384 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
18385 }
18386 else
18387 {
18388 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
18389 exp.X_add_number -= 4;
18390 }
18391 pc_rel = 1;
18392 break;
18393 case T_MNEM_mov:
18394 case T_MNEM_movs:
18395 case T_MNEM_cmp:
18396 case T_MNEM_cmn:
18397 if (fragp->fr_var == 4)
18398 {
18399 int r0off = (opcode == T_MNEM_mov
18400 || opcode == T_MNEM_movs) ? 0 : 8;
18401 insn = THUMB_OP32 (opcode);
18402 insn = (insn & 0xe1ffffff) | 0x10000000;
18403 insn |= (old_op & 0x700) << r0off;
18404 put_thumb32_insn (buf, insn);
18405 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
18406 }
18407 else
18408 {
18409 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
18410 }
18411 pc_rel = 0;
18412 break;
18413 case T_MNEM_b:
18414 if (fragp->fr_var == 4)
18415 {
18416 insn = THUMB_OP32(opcode);
18417 put_thumb32_insn (buf, insn);
18418 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
18419 }
18420 else
18421 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
18422 pc_rel = 1;
18423 break;
18424 case T_MNEM_bcond:
18425 if (fragp->fr_var == 4)
18426 {
18427 insn = THUMB_OP32(opcode);
18428 insn |= (old_op & 0xf00) << 14;
18429 put_thumb32_insn (buf, insn);
18430 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
18431 }
18432 else
18433 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
18434 pc_rel = 1;
18435 break;
18436 case T_MNEM_add_sp:
18437 case T_MNEM_add_pc:
18438 case T_MNEM_inc_sp:
18439 case T_MNEM_dec_sp:
18440 if (fragp->fr_var == 4)
18441 {
18442 /* ??? Choose between add and addw. */
18443 insn = THUMB_OP32 (opcode);
18444 insn |= (old_op & 0xf0) << 4;
18445 put_thumb32_insn (buf, insn);
16805f35
PB
18446 if (opcode == T_MNEM_add_pc)
18447 reloc_type = BFD_RELOC_ARM_T32_IMM12;
18448 else
18449 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
0110f2b8
PB
18450 }
18451 else
18452 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
18453 pc_rel = 0;
18454 break;
18455
18456 case T_MNEM_addi:
18457 case T_MNEM_addis:
18458 case T_MNEM_subi:
18459 case T_MNEM_subis:
18460 if (fragp->fr_var == 4)
18461 {
18462 insn = THUMB_OP32 (opcode);
18463 insn |= (old_op & 0xf0) << 4;
18464 insn |= (old_op & 0xf) << 16;
18465 put_thumb32_insn (buf, insn);
16805f35
PB
18466 if (insn & (1 << 20))
18467 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
18468 else
18469 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
0110f2b8
PB
18470 }
18471 else
18472 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
18473 pc_rel = 0;
18474 break;
18475 default:
5f4273c7 18476 abort ();
0110f2b8
PB
18477 }
18478 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
21d799b5 18479 (enum bfd_reloc_code_real) reloc_type);
0110f2b8
PB
18480 fixp->fx_file = fragp->fr_file;
18481 fixp->fx_line = fragp->fr_line;
18482 fragp->fr_fix += fragp->fr_var;
18483}
18484
18485/* Return the size of a relaxable immediate operand instruction.
18486 SHIFT and SIZE specify the form of the allowable immediate. */
18487static int
18488relax_immediate (fragS *fragp, int size, int shift)
18489{
18490 offsetT offset;
18491 offsetT mask;
18492 offsetT low;
18493
18494 /* ??? Should be able to do better than this. */
18495 if (fragp->fr_symbol)
18496 return 4;
18497
18498 low = (1 << shift) - 1;
18499 mask = (1 << (shift + size)) - (1 << shift);
18500 offset = fragp->fr_offset;
18501 /* Force misaligned offsets to 32-bit variant. */
18502 if (offset & low)
5e77afaa 18503 return 4;
0110f2b8
PB
18504 if (offset & ~mask)
18505 return 4;
18506 return 2;
18507}
18508
5e77afaa
PB
18509/* Get the address of a symbol during relaxation. */
18510static addressT
5f4273c7 18511relaxed_symbol_addr (fragS *fragp, long stretch)
5e77afaa
PB
18512{
18513 fragS *sym_frag;
18514 addressT addr;
18515 symbolS *sym;
18516
18517 sym = fragp->fr_symbol;
18518 sym_frag = symbol_get_frag (sym);
18519 know (S_GET_SEGMENT (sym) != absolute_section
18520 || sym_frag == &zero_address_frag);
18521 addr = S_GET_VALUE (sym) + fragp->fr_offset;
18522
18523 /* If frag has yet to be reached on this pass, assume it will
18524 move by STRETCH just as we did. If this is not so, it will
18525 be because some frag between grows, and that will force
18526 another pass. */
18527
18528 if (stretch != 0
18529 && sym_frag->relax_marker != fragp->relax_marker)
4396b686
PB
18530 {
18531 fragS *f;
18532
18533 /* Adjust stretch for any alignment frag. Note that if have
18534 been expanding the earlier code, the symbol may be
18535 defined in what appears to be an earlier frag. FIXME:
18536 This doesn't handle the fr_subtype field, which specifies
18537 a maximum number of bytes to skip when doing an
18538 alignment. */
18539 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
18540 {
18541 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
18542 {
18543 if (stretch < 0)
18544 stretch = - ((- stretch)
18545 & ~ ((1 << (int) f->fr_offset) - 1));
18546 else
18547 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
18548 if (stretch == 0)
18549 break;
18550 }
18551 }
18552 if (f != NULL)
18553 addr += stretch;
18554 }
5e77afaa
PB
18555
18556 return addr;
18557}
18558
0110f2b8
PB
18559/* Return the size of a relaxable adr pseudo-instruction or PC-relative
18560 load. */
18561static int
5e77afaa 18562relax_adr (fragS *fragp, asection *sec, long stretch)
0110f2b8
PB
18563{
18564 addressT addr;
18565 offsetT val;
18566
18567 /* Assume worst case for symbols not known to be in the same section. */
974da60d
NC
18568 if (fragp->fr_symbol == NULL
18569 || !S_IS_DEFINED (fragp->fr_symbol)
77db8e2e
NC
18570 || sec != S_GET_SEGMENT (fragp->fr_symbol)
18571 || S_IS_WEAK (fragp->fr_symbol))
0110f2b8
PB
18572 return 4;
18573
5f4273c7 18574 val = relaxed_symbol_addr (fragp, stretch);
0110f2b8
PB
18575 addr = fragp->fr_address + fragp->fr_fix;
18576 addr = (addr + 4) & ~3;
5e77afaa 18577 /* Force misaligned targets to 32-bit variant. */
0110f2b8 18578 if (val & 3)
5e77afaa 18579 return 4;
0110f2b8
PB
18580 val -= addr;
18581 if (val < 0 || val > 1020)
18582 return 4;
18583 return 2;
18584}
18585
18586/* Return the size of a relaxable add/sub immediate instruction. */
18587static int
18588relax_addsub (fragS *fragp, asection *sec)
18589{
18590 char *buf;
18591 int op;
18592
18593 buf = fragp->fr_literal + fragp->fr_fix;
18594 op = bfd_get_16(sec->owner, buf);
18595 if ((op & 0xf) == ((op >> 4) & 0xf))
18596 return relax_immediate (fragp, 8, 0);
18597 else
18598 return relax_immediate (fragp, 3, 0);
18599}
18600
18601
18602/* Return the size of a relaxable branch instruction. BITS is the
18603 size of the offset field in the narrow instruction. */
18604
18605static int
5e77afaa 18606relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
0110f2b8
PB
18607{
18608 addressT addr;
18609 offsetT val;
18610 offsetT limit;
18611
18612 /* Assume worst case for symbols not known to be in the same section. */
5f4273c7 18613 if (!S_IS_DEFINED (fragp->fr_symbol)
77db8e2e
NC
18614 || sec != S_GET_SEGMENT (fragp->fr_symbol)
18615 || S_IS_WEAK (fragp->fr_symbol))
0110f2b8
PB
18616 return 4;
18617
267bf995
RR
18618#ifdef OBJ_ELF
18619 if (S_IS_DEFINED (fragp->fr_symbol)
18620 && ARM_IS_FUNC (fragp->fr_symbol))
18621 return 4;
18622#endif
18623
5f4273c7 18624 val = relaxed_symbol_addr (fragp, stretch);
0110f2b8
PB
18625 addr = fragp->fr_address + fragp->fr_fix + 4;
18626 val -= addr;
18627
18628 /* Offset is a signed value *2 */
18629 limit = 1 << bits;
18630 if (val >= limit || val < -limit)
18631 return 4;
18632 return 2;
18633}
18634
18635
18636/* Relax a machine dependent frag. This returns the amount by which
18637 the current size of the frag should change. */
18638
18639int
5e77afaa 18640arm_relax_frag (asection *sec, fragS *fragp, long stretch)
0110f2b8
PB
18641{
18642 int oldsize;
18643 int newsize;
18644
18645 oldsize = fragp->fr_var;
18646 switch (fragp->fr_subtype)
18647 {
18648 case T_MNEM_ldr_pc2:
5f4273c7 18649 newsize = relax_adr (fragp, sec, stretch);
0110f2b8
PB
18650 break;
18651 case T_MNEM_ldr_pc:
18652 case T_MNEM_ldr_sp:
18653 case T_MNEM_str_sp:
5f4273c7 18654 newsize = relax_immediate (fragp, 8, 2);
0110f2b8
PB
18655 break;
18656 case T_MNEM_ldr:
18657 case T_MNEM_str:
5f4273c7 18658 newsize = relax_immediate (fragp, 5, 2);
0110f2b8
PB
18659 break;
18660 case T_MNEM_ldrh:
18661 case T_MNEM_strh:
5f4273c7 18662 newsize = relax_immediate (fragp, 5, 1);
0110f2b8
PB
18663 break;
18664 case T_MNEM_ldrb:
18665 case T_MNEM_strb:
5f4273c7 18666 newsize = relax_immediate (fragp, 5, 0);
0110f2b8
PB
18667 break;
18668 case T_MNEM_adr:
5f4273c7 18669 newsize = relax_adr (fragp, sec, stretch);
0110f2b8
PB
18670 break;
18671 case T_MNEM_mov:
18672 case T_MNEM_movs:
18673 case T_MNEM_cmp:
18674 case T_MNEM_cmn:
5f4273c7 18675 newsize = relax_immediate (fragp, 8, 0);
0110f2b8
PB
18676 break;
18677 case T_MNEM_b:
5f4273c7 18678 newsize = relax_branch (fragp, sec, 11, stretch);
0110f2b8
PB
18679 break;
18680 case T_MNEM_bcond:
5f4273c7 18681 newsize = relax_branch (fragp, sec, 8, stretch);
0110f2b8
PB
18682 break;
18683 case T_MNEM_add_sp:
18684 case T_MNEM_add_pc:
18685 newsize = relax_immediate (fragp, 8, 2);
18686 break;
18687 case T_MNEM_inc_sp:
18688 case T_MNEM_dec_sp:
18689 newsize = relax_immediate (fragp, 7, 2);
18690 break;
18691 case T_MNEM_addi:
18692 case T_MNEM_addis:
18693 case T_MNEM_subi:
18694 case T_MNEM_subis:
18695 newsize = relax_addsub (fragp, sec);
18696 break;
18697 default:
5f4273c7 18698 abort ();
0110f2b8 18699 }
5e77afaa
PB
18700
18701 fragp->fr_var = newsize;
18702 /* Freeze wide instructions that are at or before the same location as
18703 in the previous pass. This avoids infinite loops.
5f4273c7
NC
18704 Don't freeze them unconditionally because targets may be artificially
18705 misaligned by the expansion of preceding frags. */
5e77afaa 18706 if (stretch <= 0 && newsize > 2)
0110f2b8 18707 {
0110f2b8 18708 md_convert_frag (sec->owner, sec, fragp);
5f4273c7 18709 frag_wane (fragp);
0110f2b8 18710 }
5e77afaa 18711
0110f2b8 18712 return newsize - oldsize;
c19d1205 18713}
b99bd4ef 18714
c19d1205 18715/* Round up a section size to the appropriate boundary. */
b99bd4ef 18716
c19d1205
ZW
18717valueT
18718md_section_align (segT segment ATTRIBUTE_UNUSED,
18719 valueT size)
18720{
f0927246
NC
18721#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18722 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
18723 {
18724 /* For a.out, force the section size to be aligned. If we don't do
18725 this, BFD will align it for us, but it will not write out the
18726 final bytes of the section. This may be a bug in BFD, but it is
18727 easier to fix it here since that is how the other a.out targets
18728 work. */
18729 int align;
18730
18731 align = bfd_get_section_alignment (stdoutput, segment);
18732 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
18733 }
c19d1205 18734#endif
f0927246
NC
18735
18736 return size;
bfae80f2 18737}
b99bd4ef 18738
c19d1205
ZW
18739/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18740 of an rs_align_code fragment. */
18741
18742void
18743arm_handle_align (fragS * fragP)
bfae80f2 18744{
e7495e45
NS
18745 static char const arm_noop[2][2][4] =
18746 {
18747 { /* ARMv1 */
18748 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18749 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18750 },
18751 { /* ARMv6k */
18752 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18753 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18754 },
18755 };
18756 static char const thumb_noop[2][2][2] =
18757 {
18758 { /* Thumb-1 */
18759 {0xc0, 0x46}, /* LE */
18760 {0x46, 0xc0}, /* BE */
18761 },
18762 { /* Thumb-2 */
18763 {0x00, 0xbf}, /* LE */
18764 {0xbf, 0x00} /* BE */
18765 }
18766 };
18767 static char const wide_thumb_noop[2][4] =
18768 { /* Wide Thumb-2 */
18769 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18770 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18771 };
c921be7d 18772
e7495e45 18773 unsigned bytes, fix, noop_size;
c19d1205
ZW
18774 char * p;
18775 const char * noop;
e7495e45 18776 const char *narrow_noop = NULL;
cd000bff
DJ
18777#ifdef OBJ_ELF
18778 enum mstate state;
18779#endif
bfae80f2 18780
c19d1205 18781 if (fragP->fr_type != rs_align_code)
bfae80f2
RE
18782 return;
18783
c19d1205
ZW
18784 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
18785 p = fragP->fr_literal + fragP->fr_fix;
18786 fix = 0;
bfae80f2 18787
c19d1205
ZW
18788 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
18789 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
bfae80f2 18790
cd000bff 18791 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
8dc2430f 18792
cd000bff 18793 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
a737bd4d 18794 {
e7495e45
NS
18795 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
18796 {
18797 narrow_noop = thumb_noop[1][target_big_endian];
18798 noop = wide_thumb_noop[target_big_endian];
18799 }
c19d1205 18800 else
e7495e45
NS
18801 noop = thumb_noop[0][target_big_endian];
18802 noop_size = 2;
cd000bff
DJ
18803#ifdef OBJ_ELF
18804 state = MAP_THUMB;
18805#endif
7ed4c4c5
NC
18806 }
18807 else
18808 {
e7495e45
NS
18809 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
18810 [target_big_endian];
18811 noop_size = 4;
cd000bff
DJ
18812#ifdef OBJ_ELF
18813 state = MAP_ARM;
18814#endif
7ed4c4c5 18815 }
c921be7d 18816
e7495e45 18817 fragP->fr_var = noop_size;
c921be7d 18818
c19d1205 18819 if (bytes & (noop_size - 1))
7ed4c4c5 18820 {
c19d1205 18821 fix = bytes & (noop_size - 1);
cd000bff
DJ
18822#ifdef OBJ_ELF
18823 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
18824#endif
c19d1205
ZW
18825 memset (p, 0, fix);
18826 p += fix;
18827 bytes -= fix;
a737bd4d 18828 }
a737bd4d 18829
e7495e45
NS
18830 if (narrow_noop)
18831 {
18832 if (bytes & noop_size)
18833 {
18834 /* Insert a narrow noop. */
18835 memcpy (p, narrow_noop, noop_size);
18836 p += noop_size;
18837 bytes -= noop_size;
18838 fix += noop_size;
18839 }
18840
18841 /* Use wide noops for the remainder */
18842 noop_size = 4;
18843 }
18844
c19d1205 18845 while (bytes >= noop_size)
a737bd4d 18846 {
c19d1205
ZW
18847 memcpy (p, noop, noop_size);
18848 p += noop_size;
18849 bytes -= noop_size;
18850 fix += noop_size;
a737bd4d
NC
18851 }
18852
c19d1205 18853 fragP->fr_fix += fix;
a737bd4d
NC
18854}
18855
c19d1205
ZW
18856/* Called from md_do_align. Used to create an alignment
18857 frag in a code section. */
18858
18859void
18860arm_frag_align_code (int n, int max)
bfae80f2 18861{
c19d1205 18862 char * p;
7ed4c4c5 18863
c19d1205 18864 /* We assume that there will never be a requirement
6ec8e702 18865 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
c19d1205 18866 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
6ec8e702
NC
18867 {
18868 char err_msg[128];
18869
18870 sprintf (err_msg,
18871 _("alignments greater than %d bytes not supported in .text sections."),
18872 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
20203fb9 18873 as_fatal ("%s", err_msg);
6ec8e702 18874 }
bfae80f2 18875
c19d1205
ZW
18876 p = frag_var (rs_align_code,
18877 MAX_MEM_FOR_RS_ALIGN_CODE,
18878 1,
18879 (relax_substateT) max,
18880 (symbolS *) NULL,
18881 (offsetT) n,
18882 (char *) NULL);
18883 *p = 0;
18884}
bfae80f2 18885
8dc2430f
NC
18886/* Perform target specific initialisation of a frag.
18887 Note - despite the name this initialisation is not done when the frag
18888 is created, but only when its type is assigned. A frag can be created
18889 and used a long time before its type is set, so beware of assuming that
18890 this initialisationis performed first. */
bfae80f2 18891
cd000bff
DJ
18892#ifndef OBJ_ELF
18893void
18894arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
18895{
18896 /* Record whether this frag is in an ARM or a THUMB area. */
2e98972e 18897 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
cd000bff
DJ
18898}
18899
18900#else /* OBJ_ELF is defined. */
c19d1205 18901void
cd000bff 18902arm_init_frag (fragS * fragP, int max_chars)
c19d1205 18903{
8dc2430f
NC
18904 /* If the current ARM vs THUMB mode has not already
18905 been recorded into this frag then do so now. */
cd000bff
DJ
18906 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
18907 {
18908 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
18909
18910 /* Record a mapping symbol for alignment frags. We will delete this
18911 later if the alignment ends up empty. */
18912 switch (fragP->fr_type)
18913 {
18914 case rs_align:
18915 case rs_align_test:
18916 case rs_fill:
18917 mapping_state_2 (MAP_DATA, max_chars);
18918 break;
18919 case rs_align_code:
18920 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
18921 break;
18922 default:
18923 break;
18924 }
18925 }
bfae80f2
RE
18926}
18927
c19d1205
ZW
18928/* When we change sections we need to issue a new mapping symbol. */
18929
18930void
18931arm_elf_change_section (void)
bfae80f2 18932{
c19d1205
ZW
18933 /* Link an unlinked unwind index table section to the .text section. */
18934 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
18935 && elf_linked_to_section (now_seg) == NULL)
18936 elf_linked_to_section (now_seg) = text_section;
bfae80f2
RE
18937}
18938
c19d1205
ZW
18939int
18940arm_elf_section_type (const char * str, size_t len)
e45d0630 18941{
c19d1205
ZW
18942 if (len == 5 && strncmp (str, "exidx", 5) == 0)
18943 return SHT_ARM_EXIDX;
e45d0630 18944
c19d1205
ZW
18945 return -1;
18946}
18947\f
18948/* Code to deal with unwinding tables. */
e45d0630 18949
c19d1205 18950static void add_unwind_adjustsp (offsetT);
e45d0630 18951
5f4273c7 18952/* Generate any deferred unwind frame offset. */
e45d0630 18953
bfae80f2 18954static void
c19d1205 18955flush_pending_unwind (void)
bfae80f2 18956{
c19d1205 18957 offsetT offset;
bfae80f2 18958
c19d1205
ZW
18959 offset = unwind.pending_offset;
18960 unwind.pending_offset = 0;
18961 if (offset != 0)
18962 add_unwind_adjustsp (offset);
bfae80f2
RE
18963}
18964
c19d1205
ZW
18965/* Add an opcode to this list for this function. Two-byte opcodes should
18966 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
18967 order. */
18968
bfae80f2 18969static void
c19d1205 18970add_unwind_opcode (valueT op, int length)
bfae80f2 18971{
c19d1205
ZW
18972 /* Add any deferred stack adjustment. */
18973 if (unwind.pending_offset)
18974 flush_pending_unwind ();
bfae80f2 18975
c19d1205 18976 unwind.sp_restored = 0;
bfae80f2 18977
c19d1205 18978 if (unwind.opcode_count + length > unwind.opcode_alloc)
bfae80f2 18979 {
c19d1205
ZW
18980 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
18981 if (unwind.opcodes)
21d799b5
NC
18982 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
18983 unwind.opcode_alloc);
c19d1205 18984 else
21d799b5 18985 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
bfae80f2 18986 }
c19d1205 18987 while (length > 0)
bfae80f2 18988 {
c19d1205
ZW
18989 length--;
18990 unwind.opcodes[unwind.opcode_count] = op & 0xff;
18991 op >>= 8;
18992 unwind.opcode_count++;
bfae80f2 18993 }
bfae80f2
RE
18994}
18995
c19d1205
ZW
18996/* Add unwind opcodes to adjust the stack pointer. */
18997
bfae80f2 18998static void
c19d1205 18999add_unwind_adjustsp (offsetT offset)
bfae80f2 19000{
c19d1205 19001 valueT op;
bfae80f2 19002
c19d1205 19003 if (offset > 0x200)
bfae80f2 19004 {
c19d1205
ZW
19005 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19006 char bytes[5];
19007 int n;
19008 valueT o;
bfae80f2 19009
c19d1205
ZW
19010 /* Long form: 0xb2, uleb128. */
19011 /* This might not fit in a word so add the individual bytes,
19012 remembering the list is built in reverse order. */
19013 o = (valueT) ((offset - 0x204) >> 2);
19014 if (o == 0)
19015 add_unwind_opcode (0, 1);
bfae80f2 19016
c19d1205
ZW
19017 /* Calculate the uleb128 encoding of the offset. */
19018 n = 0;
19019 while (o)
19020 {
19021 bytes[n] = o & 0x7f;
19022 o >>= 7;
19023 if (o)
19024 bytes[n] |= 0x80;
19025 n++;
19026 }
19027 /* Add the insn. */
19028 for (; n; n--)
19029 add_unwind_opcode (bytes[n - 1], 1);
19030 add_unwind_opcode (0xb2, 1);
19031 }
19032 else if (offset > 0x100)
bfae80f2 19033 {
c19d1205
ZW
19034 /* Two short opcodes. */
19035 add_unwind_opcode (0x3f, 1);
19036 op = (offset - 0x104) >> 2;
19037 add_unwind_opcode (op, 1);
bfae80f2 19038 }
c19d1205
ZW
19039 else if (offset > 0)
19040 {
19041 /* Short opcode. */
19042 op = (offset - 4) >> 2;
19043 add_unwind_opcode (op, 1);
19044 }
19045 else if (offset < 0)
bfae80f2 19046 {
c19d1205
ZW
19047 offset = -offset;
19048 while (offset > 0x100)
bfae80f2 19049 {
c19d1205
ZW
19050 add_unwind_opcode (0x7f, 1);
19051 offset -= 0x100;
bfae80f2 19052 }
c19d1205
ZW
19053 op = ((offset - 4) >> 2) | 0x40;
19054 add_unwind_opcode (op, 1);
bfae80f2 19055 }
bfae80f2
RE
19056}
19057
c19d1205
ZW
19058/* Finish the list of unwind opcodes for this function. */
19059static void
19060finish_unwind_opcodes (void)
bfae80f2 19061{
c19d1205 19062 valueT op;
bfae80f2 19063
c19d1205 19064 if (unwind.fp_used)
bfae80f2 19065 {
708587a4 19066 /* Adjust sp as necessary. */
c19d1205
ZW
19067 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
19068 flush_pending_unwind ();
bfae80f2 19069
c19d1205
ZW
19070 /* After restoring sp from the frame pointer. */
19071 op = 0x90 | unwind.fp_reg;
19072 add_unwind_opcode (op, 1);
19073 }
19074 else
19075 flush_pending_unwind ();
bfae80f2
RE
19076}
19077
bfae80f2 19078
c19d1205
ZW
19079/* Start an exception table entry. If idx is nonzero this is an index table
19080 entry. */
bfae80f2
RE
19081
19082static void
c19d1205 19083start_unwind_section (const segT text_seg, int idx)
bfae80f2 19084{
c19d1205
ZW
19085 const char * text_name;
19086 const char * prefix;
19087 const char * prefix_once;
19088 const char * group_name;
19089 size_t prefix_len;
19090 size_t text_len;
19091 char * sec_name;
19092 size_t sec_name_len;
19093 int type;
19094 int flags;
19095 int linkonce;
bfae80f2 19096
c19d1205 19097 if (idx)
bfae80f2 19098 {
c19d1205
ZW
19099 prefix = ELF_STRING_ARM_unwind;
19100 prefix_once = ELF_STRING_ARM_unwind_once;
19101 type = SHT_ARM_EXIDX;
bfae80f2 19102 }
c19d1205 19103 else
bfae80f2 19104 {
c19d1205
ZW
19105 prefix = ELF_STRING_ARM_unwind_info;
19106 prefix_once = ELF_STRING_ARM_unwind_info_once;
19107 type = SHT_PROGBITS;
bfae80f2
RE
19108 }
19109
c19d1205
ZW
19110 text_name = segment_name (text_seg);
19111 if (streq (text_name, ".text"))
19112 text_name = "";
19113
19114 if (strncmp (text_name, ".gnu.linkonce.t.",
19115 strlen (".gnu.linkonce.t.")) == 0)
bfae80f2 19116 {
c19d1205
ZW
19117 prefix = prefix_once;
19118 text_name += strlen (".gnu.linkonce.t.");
bfae80f2
RE
19119 }
19120
c19d1205
ZW
19121 prefix_len = strlen (prefix);
19122 text_len = strlen (text_name);
19123 sec_name_len = prefix_len + text_len;
21d799b5 19124 sec_name = (char *) xmalloc (sec_name_len + 1);
c19d1205
ZW
19125 memcpy (sec_name, prefix, prefix_len);
19126 memcpy (sec_name + prefix_len, text_name, text_len);
19127 sec_name[prefix_len + text_len] = '\0';
bfae80f2 19128
c19d1205
ZW
19129 flags = SHF_ALLOC;
19130 linkonce = 0;
19131 group_name = 0;
bfae80f2 19132
c19d1205
ZW
19133 /* Handle COMDAT group. */
19134 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
bfae80f2 19135 {
c19d1205
ZW
19136 group_name = elf_group_name (text_seg);
19137 if (group_name == NULL)
19138 {
bd3ba5d1 19139 as_bad (_("Group section `%s' has no group signature"),
c19d1205
ZW
19140 segment_name (text_seg));
19141 ignore_rest_of_line ();
19142 return;
19143 }
19144 flags |= SHF_GROUP;
19145 linkonce = 1;
bfae80f2
RE
19146 }
19147
c19d1205 19148 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
bfae80f2 19149
5f4273c7 19150 /* Set the section link for index tables. */
c19d1205
ZW
19151 if (idx)
19152 elf_linked_to_section (now_seg) = text_seg;
bfae80f2
RE
19153}
19154
bfae80f2 19155
c19d1205
ZW
19156/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19157 personality routine data. Returns zero, or the index table value for
19158 and inline entry. */
19159
19160static valueT
19161create_unwind_entry (int have_data)
bfae80f2 19162{
c19d1205
ZW
19163 int size;
19164 addressT where;
19165 char *ptr;
19166 /* The current word of data. */
19167 valueT data;
19168 /* The number of bytes left in this word. */
19169 int n;
bfae80f2 19170
c19d1205 19171 finish_unwind_opcodes ();
bfae80f2 19172
c19d1205
ZW
19173 /* Remember the current text section. */
19174 unwind.saved_seg = now_seg;
19175 unwind.saved_subseg = now_subseg;
bfae80f2 19176
c19d1205 19177 start_unwind_section (now_seg, 0);
bfae80f2 19178
c19d1205 19179 if (unwind.personality_routine == NULL)
bfae80f2 19180 {
c19d1205
ZW
19181 if (unwind.personality_index == -2)
19182 {
19183 if (have_data)
5f4273c7 19184 as_bad (_("handlerdata in cantunwind frame"));
c19d1205
ZW
19185 return 1; /* EXIDX_CANTUNWIND. */
19186 }
bfae80f2 19187
c19d1205
ZW
19188 /* Use a default personality routine if none is specified. */
19189 if (unwind.personality_index == -1)
19190 {
19191 if (unwind.opcode_count > 3)
19192 unwind.personality_index = 1;
19193 else
19194 unwind.personality_index = 0;
19195 }
bfae80f2 19196
c19d1205
ZW
19197 /* Space for the personality routine entry. */
19198 if (unwind.personality_index == 0)
19199 {
19200 if (unwind.opcode_count > 3)
19201 as_bad (_("too many unwind opcodes for personality routine 0"));
bfae80f2 19202
c19d1205
ZW
19203 if (!have_data)
19204 {
19205 /* All the data is inline in the index table. */
19206 data = 0x80;
19207 n = 3;
19208 while (unwind.opcode_count > 0)
19209 {
19210 unwind.opcode_count--;
19211 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
19212 n--;
19213 }
bfae80f2 19214
c19d1205
ZW
19215 /* Pad with "finish" opcodes. */
19216 while (n--)
19217 data = (data << 8) | 0xb0;
bfae80f2 19218
c19d1205
ZW
19219 return data;
19220 }
19221 size = 0;
19222 }
19223 else
19224 /* We get two opcodes "free" in the first word. */
19225 size = unwind.opcode_count - 2;
19226 }
19227 else
19228 /* An extra byte is required for the opcode count. */
19229 size = unwind.opcode_count + 1;
bfae80f2 19230
c19d1205
ZW
19231 size = (size + 3) >> 2;
19232 if (size > 0xff)
19233 as_bad (_("too many unwind opcodes"));
bfae80f2 19234
c19d1205
ZW
19235 frag_align (2, 0, 0);
19236 record_alignment (now_seg, 2);
19237 unwind.table_entry = expr_build_dot ();
19238
19239 /* Allocate the table entry. */
19240 ptr = frag_more ((size << 2) + 4);
19241 where = frag_now_fix () - ((size << 2) + 4);
bfae80f2 19242
c19d1205 19243 switch (unwind.personality_index)
bfae80f2 19244 {
c19d1205
ZW
19245 case -1:
19246 /* ??? Should this be a PLT generating relocation? */
19247 /* Custom personality routine. */
19248 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
19249 BFD_RELOC_ARM_PREL31);
bfae80f2 19250
c19d1205
ZW
19251 where += 4;
19252 ptr += 4;
bfae80f2 19253
c19d1205
ZW
19254 /* Set the first byte to the number of additional words. */
19255 data = size - 1;
19256 n = 3;
19257 break;
bfae80f2 19258
c19d1205
ZW
19259 /* ABI defined personality routines. */
19260 case 0:
19261 /* Three opcodes bytes are packed into the first word. */
19262 data = 0x80;
19263 n = 3;
19264 break;
bfae80f2 19265
c19d1205
ZW
19266 case 1:
19267 case 2:
19268 /* The size and first two opcode bytes go in the first word. */
19269 data = ((0x80 + unwind.personality_index) << 8) | size;
19270 n = 2;
19271 break;
bfae80f2 19272
c19d1205
ZW
19273 default:
19274 /* Should never happen. */
19275 abort ();
19276 }
bfae80f2 19277
c19d1205
ZW
19278 /* Pack the opcodes into words (MSB first), reversing the list at the same
19279 time. */
19280 while (unwind.opcode_count > 0)
19281 {
19282 if (n == 0)
19283 {
19284 md_number_to_chars (ptr, data, 4);
19285 ptr += 4;
19286 n = 4;
19287 data = 0;
19288 }
19289 unwind.opcode_count--;
19290 n--;
19291 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
19292 }
19293
19294 /* Finish off the last word. */
19295 if (n < 4)
19296 {
19297 /* Pad with "finish" opcodes. */
19298 while (n--)
19299 data = (data << 8) | 0xb0;
19300
19301 md_number_to_chars (ptr, data, 4);
19302 }
19303
19304 if (!have_data)
19305 {
19306 /* Add an empty descriptor if there is no user-specified data. */
19307 ptr = frag_more (4);
19308 md_number_to_chars (ptr, 0, 4);
19309 }
19310
19311 return 0;
bfae80f2
RE
19312}
19313
f0927246
NC
19314
19315/* Initialize the DWARF-2 unwind information for this procedure. */
19316
19317void
19318tc_arm_frame_initial_instructions (void)
19319{
19320 cfi_add_CFA_def_cfa (REG_SP, 0);
19321}
19322#endif /* OBJ_ELF */
19323
c19d1205
ZW
19324/* Convert REGNAME to a DWARF-2 register number. */
19325
19326int
1df69f4f 19327tc_arm_regname_to_dw2regnum (char *regname)
bfae80f2 19328{
1df69f4f 19329 int reg = arm_reg_parse (&regname, REG_TYPE_RN);
c19d1205
ZW
19330
19331 if (reg == FAIL)
19332 return -1;
19333
19334 return reg;
bfae80f2
RE
19335}
19336
f0927246 19337#ifdef TE_PE
c19d1205 19338void
f0927246 19339tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
bfae80f2 19340{
91d6fa6a 19341 expressionS exp;
bfae80f2 19342
91d6fa6a
NC
19343 exp.X_op = O_secrel;
19344 exp.X_add_symbol = symbol;
19345 exp.X_add_number = 0;
19346 emit_expr (&exp, size);
f0927246
NC
19347}
19348#endif
bfae80f2 19349
c19d1205 19350/* MD interface: Symbol and relocation handling. */
bfae80f2 19351
2fc8bdac
ZW
19352/* Return the address within the segment that a PC-relative fixup is
19353 relative to. For ARM, PC-relative fixups applied to instructions
19354 are generally relative to the location of the fixup plus 8 bytes.
19355 Thumb branches are offset by 4, and Thumb loads relative to PC
19356 require special handling. */
bfae80f2 19357
c19d1205 19358long
2fc8bdac 19359md_pcrel_from_section (fixS * fixP, segT seg)
bfae80f2 19360{
2fc8bdac
ZW
19361 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
19362
19363 /* If this is pc-relative and we are going to emit a relocation
19364 then we just want to put out any pipeline compensation that the linker
53baae48
NC
19365 will need. Otherwise we want to use the calculated base.
19366 For WinCE we skip the bias for externals as well, since this
19367 is how the MS ARM-CE assembler behaves and we want to be compatible. */
5f4273c7 19368 if (fixP->fx_pcrel
2fc8bdac 19369 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
53baae48
NC
19370 || (arm_force_relocation (fixP)
19371#ifdef TE_WINCE
19372 && !S_IS_EXTERNAL (fixP->fx_addsy)
19373#endif
19374 )))
2fc8bdac 19375 base = 0;
bfae80f2 19376
267bf995 19377
c19d1205 19378 switch (fixP->fx_r_type)
bfae80f2 19379 {
2fc8bdac
ZW
19380 /* PC relative addressing on the Thumb is slightly odd as the
19381 bottom two bits of the PC are forced to zero for the
19382 calculation. This happens *after* application of the
19383 pipeline offset. However, Thumb adrl already adjusts for
19384 this, so we need not do it again. */
c19d1205 19385 case BFD_RELOC_ARM_THUMB_ADD:
2fc8bdac 19386 return base & ~3;
c19d1205
ZW
19387
19388 case BFD_RELOC_ARM_THUMB_OFFSET:
19389 case BFD_RELOC_ARM_T32_OFFSET_IMM:
e9f89963 19390 case BFD_RELOC_ARM_T32_ADD_PC12:
8f06b2d8 19391 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
2fc8bdac 19392 return (base + 4) & ~3;
c19d1205 19393
2fc8bdac
ZW
19394 /* Thumb branches are simply offset by +4. */
19395 case BFD_RELOC_THUMB_PCREL_BRANCH7:
19396 case BFD_RELOC_THUMB_PCREL_BRANCH9:
19397 case BFD_RELOC_THUMB_PCREL_BRANCH12:
19398 case BFD_RELOC_THUMB_PCREL_BRANCH20:
2fc8bdac 19399 case BFD_RELOC_THUMB_PCREL_BRANCH25:
2fc8bdac 19400 return base + 4;
bfae80f2 19401
267bf995 19402 case BFD_RELOC_THUMB_PCREL_BRANCH23:
486499d0
CL
19403 if (fixP->fx_addsy
19404 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
19405 && (!S_IS_EXTERNAL (fixP->fx_addsy))
267bf995
RR
19406 && ARM_IS_FUNC (fixP->fx_addsy)
19407 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
19408 base = fixP->fx_where + fixP->fx_frag->fr_address;
19409 return base + 4;
19410
00adf2d4
JB
19411 /* BLX is like branches above, but forces the low two bits of PC to
19412 zero. */
486499d0
CL
19413 case BFD_RELOC_THUMB_PCREL_BLX:
19414 if (fixP->fx_addsy
19415 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
19416 && (!S_IS_EXTERNAL (fixP->fx_addsy))
267bf995
RR
19417 && THUMB_IS_FUNC (fixP->fx_addsy)
19418 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
19419 base = fixP->fx_where + fixP->fx_frag->fr_address;
00adf2d4
JB
19420 return (base + 4) & ~3;
19421
2fc8bdac
ZW
19422 /* ARM mode branches are offset by +8. However, the Windows CE
19423 loader expects the relocation not to take this into account. */
267bf995 19424 case BFD_RELOC_ARM_PCREL_BLX:
486499d0
CL
19425 if (fixP->fx_addsy
19426 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
19427 && (!S_IS_EXTERNAL (fixP->fx_addsy))
267bf995
RR
19428 && ARM_IS_FUNC (fixP->fx_addsy)
19429 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
19430 base = fixP->fx_where + fixP->fx_frag->fr_address;
486499d0 19431 return base + 8;
267bf995 19432
486499d0
CL
19433 case BFD_RELOC_ARM_PCREL_CALL:
19434 if (fixP->fx_addsy
19435 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
19436 && (!S_IS_EXTERNAL (fixP->fx_addsy))
267bf995
RR
19437 && THUMB_IS_FUNC (fixP->fx_addsy)
19438 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
19439 base = fixP->fx_where + fixP->fx_frag->fr_address;
486499d0 19440 return base + 8;
267bf995 19441
2fc8bdac 19442 case BFD_RELOC_ARM_PCREL_BRANCH:
39b41c9c 19443 case BFD_RELOC_ARM_PCREL_JUMP:
2fc8bdac 19444 case BFD_RELOC_ARM_PLT32:
c19d1205 19445#ifdef TE_WINCE
5f4273c7 19446 /* When handling fixups immediately, because we have already
53baae48
NC
19447 discovered the value of a symbol, or the address of the frag involved
19448 we must account for the offset by +8, as the OS loader will never see the reloc.
19449 see fixup_segment() in write.c
19450 The S_IS_EXTERNAL test handles the case of global symbols.
19451 Those need the calculated base, not just the pipe compensation the linker will need. */
19452 if (fixP->fx_pcrel
19453 && fixP->fx_addsy != NULL
19454 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
19455 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
19456 return base + 8;
2fc8bdac 19457 return base;
c19d1205 19458#else
2fc8bdac 19459 return base + 8;
c19d1205 19460#endif
2fc8bdac 19461
267bf995 19462
2fc8bdac
ZW
19463 /* ARM mode loads relative to PC are also offset by +8. Unlike
19464 branches, the Windows CE loader *does* expect the relocation
19465 to take this into account. */
19466 case BFD_RELOC_ARM_OFFSET_IMM:
19467 case BFD_RELOC_ARM_OFFSET_IMM8:
19468 case BFD_RELOC_ARM_HWLITERAL:
19469 case BFD_RELOC_ARM_LITERAL:
19470 case BFD_RELOC_ARM_CP_OFF_IMM:
19471 return base + 8;
19472
19473
19474 /* Other PC-relative relocations are un-offset. */
19475 default:
19476 return base;
19477 }
bfae80f2
RE
19478}
19479
c19d1205
ZW
19480/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19481 Otherwise we have no need to default values of symbols. */
19482
19483symbolS *
19484md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
bfae80f2 19485{
c19d1205
ZW
19486#ifdef OBJ_ELF
19487 if (name[0] == '_' && name[1] == 'G'
19488 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
19489 {
19490 if (!GOT_symbol)
19491 {
19492 if (symbol_find (name))
bd3ba5d1 19493 as_bad (_("GOT already in the symbol table"));
bfae80f2 19494
c19d1205
ZW
19495 GOT_symbol = symbol_new (name, undefined_section,
19496 (valueT) 0, & zero_address_frag);
19497 }
bfae80f2 19498
c19d1205 19499 return GOT_symbol;
bfae80f2 19500 }
c19d1205 19501#endif
bfae80f2 19502
c921be7d 19503 return NULL;
bfae80f2
RE
19504}
19505
55cf6793 19506/* Subroutine of md_apply_fix. Check to see if an immediate can be
c19d1205
ZW
19507 computed as two separate immediate values, added together. We
19508 already know that this value cannot be computed by just one ARM
19509 instruction. */
19510
19511static unsigned int
19512validate_immediate_twopart (unsigned int val,
19513 unsigned int * highpart)
bfae80f2 19514{
c19d1205
ZW
19515 unsigned int a;
19516 unsigned int i;
bfae80f2 19517
c19d1205
ZW
19518 for (i = 0; i < 32; i += 2)
19519 if (((a = rotate_left (val, i)) & 0xff) != 0)
19520 {
19521 if (a & 0xff00)
19522 {
19523 if (a & ~ 0xffff)
19524 continue;
19525 * highpart = (a >> 8) | ((i + 24) << 7);
19526 }
19527 else if (a & 0xff0000)
19528 {
19529 if (a & 0xff000000)
19530 continue;
19531 * highpart = (a >> 16) | ((i + 16) << 7);
19532 }
19533 else
19534 {
9c2799c2 19535 gas_assert (a & 0xff000000);
c19d1205
ZW
19536 * highpart = (a >> 24) | ((i + 8) << 7);
19537 }
bfae80f2 19538
c19d1205
ZW
19539 return (a & 0xff) | (i << 7);
19540 }
bfae80f2 19541
c19d1205 19542 return FAIL;
bfae80f2
RE
19543}
19544
c19d1205
ZW
19545static int
19546validate_offset_imm (unsigned int val, int hwse)
19547{
19548 if ((hwse && val > 255) || val > 4095)
19549 return FAIL;
19550 return val;
19551}
bfae80f2 19552
55cf6793 19553/* Subroutine of md_apply_fix. Do those data_ops which can take a
c19d1205
ZW
19554 negative immediate constant by altering the instruction. A bit of
19555 a hack really.
19556 MOV <-> MVN
19557 AND <-> BIC
19558 ADC <-> SBC
19559 by inverting the second operand, and
19560 ADD <-> SUB
19561 CMP <-> CMN
19562 by negating the second operand. */
bfae80f2 19563
c19d1205
ZW
19564static int
19565negate_data_op (unsigned long * instruction,
19566 unsigned long value)
bfae80f2 19567{
c19d1205
ZW
19568 int op, new_inst;
19569 unsigned long negated, inverted;
bfae80f2 19570
c19d1205
ZW
19571 negated = encode_arm_immediate (-value);
19572 inverted = encode_arm_immediate (~value);
bfae80f2 19573
c19d1205
ZW
19574 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
19575 switch (op)
bfae80f2 19576 {
c19d1205
ZW
19577 /* First negates. */
19578 case OPCODE_SUB: /* ADD <-> SUB */
19579 new_inst = OPCODE_ADD;
19580 value = negated;
19581 break;
bfae80f2 19582
c19d1205
ZW
19583 case OPCODE_ADD:
19584 new_inst = OPCODE_SUB;
19585 value = negated;
19586 break;
bfae80f2 19587
c19d1205
ZW
19588 case OPCODE_CMP: /* CMP <-> CMN */
19589 new_inst = OPCODE_CMN;
19590 value = negated;
19591 break;
bfae80f2 19592
c19d1205
ZW
19593 case OPCODE_CMN:
19594 new_inst = OPCODE_CMP;
19595 value = negated;
19596 break;
bfae80f2 19597
c19d1205
ZW
19598 /* Now Inverted ops. */
19599 case OPCODE_MOV: /* MOV <-> MVN */
19600 new_inst = OPCODE_MVN;
19601 value = inverted;
19602 break;
bfae80f2 19603
c19d1205
ZW
19604 case OPCODE_MVN:
19605 new_inst = OPCODE_MOV;
19606 value = inverted;
19607 break;
bfae80f2 19608
c19d1205
ZW
19609 case OPCODE_AND: /* AND <-> BIC */
19610 new_inst = OPCODE_BIC;
19611 value = inverted;
19612 break;
bfae80f2 19613
c19d1205
ZW
19614 case OPCODE_BIC:
19615 new_inst = OPCODE_AND;
19616 value = inverted;
19617 break;
bfae80f2 19618
c19d1205
ZW
19619 case OPCODE_ADC: /* ADC <-> SBC */
19620 new_inst = OPCODE_SBC;
19621 value = inverted;
19622 break;
bfae80f2 19623
c19d1205
ZW
19624 case OPCODE_SBC:
19625 new_inst = OPCODE_ADC;
19626 value = inverted;
19627 break;
bfae80f2 19628
c19d1205
ZW
19629 /* We cannot do anything. */
19630 default:
19631 return FAIL;
b99bd4ef
NC
19632 }
19633
c19d1205
ZW
19634 if (value == (unsigned) FAIL)
19635 return FAIL;
19636
19637 *instruction &= OPCODE_MASK;
19638 *instruction |= new_inst << DATA_OP_SHIFT;
19639 return value;
b99bd4ef
NC
19640}
19641
ef8d22e6
PB
19642/* Like negate_data_op, but for Thumb-2. */
19643
19644static unsigned int
16dd5e42 19645thumb32_negate_data_op (offsetT *instruction, unsigned int value)
ef8d22e6
PB
19646{
19647 int op, new_inst;
19648 int rd;
16dd5e42 19649 unsigned int negated, inverted;
ef8d22e6
PB
19650
19651 negated = encode_thumb32_immediate (-value);
19652 inverted = encode_thumb32_immediate (~value);
19653
19654 rd = (*instruction >> 8) & 0xf;
19655 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
19656 switch (op)
19657 {
19658 /* ADD <-> SUB. Includes CMP <-> CMN. */
19659 case T2_OPCODE_SUB:
19660 new_inst = T2_OPCODE_ADD;
19661 value = negated;
19662 break;
19663
19664 case T2_OPCODE_ADD:
19665 new_inst = T2_OPCODE_SUB;
19666 value = negated;
19667 break;
19668
19669 /* ORR <-> ORN. Includes MOV <-> MVN. */
19670 case T2_OPCODE_ORR:
19671 new_inst = T2_OPCODE_ORN;
19672 value = inverted;
19673 break;
19674
19675 case T2_OPCODE_ORN:
19676 new_inst = T2_OPCODE_ORR;
19677 value = inverted;
19678 break;
19679
19680 /* AND <-> BIC. TST has no inverted equivalent. */
19681 case T2_OPCODE_AND:
19682 new_inst = T2_OPCODE_BIC;
19683 if (rd == 15)
19684 value = FAIL;
19685 else
19686 value = inverted;
19687 break;
19688
19689 case T2_OPCODE_BIC:
19690 new_inst = T2_OPCODE_AND;
19691 value = inverted;
19692 break;
19693
19694 /* ADC <-> SBC */
19695 case T2_OPCODE_ADC:
19696 new_inst = T2_OPCODE_SBC;
19697 value = inverted;
19698 break;
19699
19700 case T2_OPCODE_SBC:
19701 new_inst = T2_OPCODE_ADC;
19702 value = inverted;
19703 break;
19704
19705 /* We cannot do anything. */
19706 default:
19707 return FAIL;
19708 }
19709
16dd5e42 19710 if (value == (unsigned int)FAIL)
ef8d22e6
PB
19711 return FAIL;
19712
19713 *instruction &= T2_OPCODE_MASK;
19714 *instruction |= new_inst << T2_DATA_OP_SHIFT;
19715 return value;
19716}
19717
8f06b2d8
PB
19718/* Read a 32-bit thumb instruction from buf. */
19719static unsigned long
19720get_thumb32_insn (char * buf)
19721{
19722 unsigned long insn;
19723 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
19724 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
19725
19726 return insn;
19727}
19728
a8bc6c78
PB
19729
19730/* We usually want to set the low bit on the address of thumb function
19731 symbols. In particular .word foo - . should have the low bit set.
19732 Generic code tries to fold the difference of two symbols to
19733 a constant. Prevent this and force a relocation when the first symbols
19734 is a thumb function. */
c921be7d
NC
19735
19736bfd_boolean
a8bc6c78
PB
19737arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
19738{
19739 if (op == O_subtract
19740 && l->X_op == O_symbol
19741 && r->X_op == O_symbol
19742 && THUMB_IS_FUNC (l->X_add_symbol))
19743 {
19744 l->X_op = O_subtract;
19745 l->X_op_symbol = r->X_add_symbol;
19746 l->X_add_number -= r->X_add_number;
c921be7d 19747 return TRUE;
a8bc6c78 19748 }
c921be7d 19749
a8bc6c78 19750 /* Process as normal. */
c921be7d 19751 return FALSE;
a8bc6c78
PB
19752}
19753
4a42ebbc
RR
19754/* Encode Thumb2 unconditional branches and calls. The encoding
19755 for the 2 are identical for the immediate values. */
19756
19757static void
19758encode_thumb2_b_bl_offset (char * buf, offsetT value)
19759{
19760#define T2I1I2MASK ((1 << 13) | (1 << 11))
19761 offsetT newval;
19762 offsetT newval2;
19763 addressT S, I1, I2, lo, hi;
19764
19765 S = (value >> 24) & 0x01;
19766 I1 = (value >> 23) & 0x01;
19767 I2 = (value >> 22) & 0x01;
19768 hi = (value >> 12) & 0x3ff;
19769 lo = (value >> 1) & 0x7ff;
19770 newval = md_chars_to_number (buf, THUMB_SIZE);
19771 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
19772 newval |= (S << 10) | hi;
19773 newval2 &= ~T2I1I2MASK;
19774 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
19775 md_number_to_chars (buf, newval, THUMB_SIZE);
19776 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
19777}
19778
c19d1205 19779void
55cf6793 19780md_apply_fix (fixS * fixP,
c19d1205
ZW
19781 valueT * valP,
19782 segT seg)
19783{
19784 offsetT value = * valP;
19785 offsetT newval;
19786 unsigned int newimm;
19787 unsigned long temp;
19788 int sign;
19789 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
b99bd4ef 19790
9c2799c2 19791 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
b99bd4ef 19792
c19d1205 19793 /* Note whether this will delete the relocation. */
4962c51a 19794
c19d1205
ZW
19795 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
19796 fixP->fx_done = 1;
b99bd4ef 19797
adbaf948 19798 /* On a 64-bit host, silently truncate 'value' to 32 bits for
5f4273c7 19799 consistency with the behaviour on 32-bit hosts. Remember value
adbaf948
ZW
19800 for emit_reloc. */
19801 value &= 0xffffffff;
19802 value ^= 0x80000000;
5f4273c7 19803 value -= 0x80000000;
adbaf948
ZW
19804
19805 *valP = value;
c19d1205 19806 fixP->fx_addnumber = value;
b99bd4ef 19807
adbaf948
ZW
19808 /* Same treatment for fixP->fx_offset. */
19809 fixP->fx_offset &= 0xffffffff;
19810 fixP->fx_offset ^= 0x80000000;
19811 fixP->fx_offset -= 0x80000000;
19812
c19d1205 19813 switch (fixP->fx_r_type)
b99bd4ef 19814 {
c19d1205
ZW
19815 case BFD_RELOC_NONE:
19816 /* This will need to go in the object file. */
19817 fixP->fx_done = 0;
19818 break;
b99bd4ef 19819
c19d1205
ZW
19820 case BFD_RELOC_ARM_IMMEDIATE:
19821 /* We claim that this fixup has been processed here,
19822 even if in fact we generate an error because we do
19823 not have a reloc for it, so tc_gen_reloc will reject it. */
19824 fixP->fx_done = 1;
b99bd4ef 19825
77db8e2e 19826 if (fixP->fx_addsy)
b99bd4ef 19827 {
77db8e2e 19828 const char *msg = 0;
b99bd4ef 19829
77db8e2e
NC
19830 if (! S_IS_DEFINED (fixP->fx_addsy))
19831 msg = _("undefined symbol %s used as an immediate value");
19832 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
19833 msg = _("symbol %s is in a different section");
19834 else if (S_IS_WEAK (fixP->fx_addsy))
19835 msg = _("symbol %s is weak and may be overridden later");
19836
19837 if (msg)
19838 {
19839 as_bad_where (fixP->fx_file, fixP->fx_line,
19840 msg, S_GET_NAME (fixP->fx_addsy));
19841 break;
19842 }
42e5fcbf
AS
19843 }
19844
c19d1205
ZW
19845 newimm = encode_arm_immediate (value);
19846 temp = md_chars_to_number (buf, INSN_SIZE);
19847
19848 /* If the instruction will fail, see if we can fix things up by
19849 changing the opcode. */
19850 if (newimm == (unsigned int) FAIL
19851 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
b99bd4ef 19852 {
c19d1205
ZW
19853 as_bad_where (fixP->fx_file, fixP->fx_line,
19854 _("invalid constant (%lx) after fixup"),
19855 (unsigned long) value);
19856 break;
b99bd4ef 19857 }
b99bd4ef 19858
c19d1205
ZW
19859 newimm |= (temp & 0xfffff000);
19860 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
19861 break;
b99bd4ef 19862
c19d1205
ZW
19863 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
19864 {
19865 unsigned int highpart = 0;
19866 unsigned int newinsn = 0xe1a00000; /* nop. */
b99bd4ef 19867
77db8e2e 19868 if (fixP->fx_addsy)
42e5fcbf 19869 {
77db8e2e 19870 const char *msg = 0;
42e5fcbf 19871
77db8e2e
NC
19872 if (! S_IS_DEFINED (fixP->fx_addsy))
19873 msg = _("undefined symbol %s used as an immediate value");
19874 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
19875 msg = _("symbol %s is in a different section");
19876 else if (S_IS_WEAK (fixP->fx_addsy))
19877 msg = _("symbol %s is weak and may be overridden later");
42e5fcbf 19878
77db8e2e
NC
19879 if (msg)
19880 {
19881 as_bad_where (fixP->fx_file, fixP->fx_line,
19882 msg, S_GET_NAME (fixP->fx_addsy));
19883 break;
19884 }
19885 }
19886
c19d1205
ZW
19887 newimm = encode_arm_immediate (value);
19888 temp = md_chars_to_number (buf, INSN_SIZE);
b99bd4ef 19889
c19d1205
ZW
19890 /* If the instruction will fail, see if we can fix things up by
19891 changing the opcode. */
19892 if (newimm == (unsigned int) FAIL
19893 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
19894 {
19895 /* No ? OK - try using two ADD instructions to generate
19896 the value. */
19897 newimm = validate_immediate_twopart (value, & highpart);
b99bd4ef 19898
c19d1205
ZW
19899 /* Yes - then make sure that the second instruction is
19900 also an add. */
19901 if (newimm != (unsigned int) FAIL)
19902 newinsn = temp;
19903 /* Still No ? Try using a negated value. */
19904 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
19905 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
19906 /* Otherwise - give up. */
19907 else
19908 {
19909 as_bad_where (fixP->fx_file, fixP->fx_line,
19910 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
19911 (long) value);
19912 break;
19913 }
b99bd4ef 19914
c19d1205
ZW
19915 /* Replace the first operand in the 2nd instruction (which
19916 is the PC) with the destination register. We have
19917 already added in the PC in the first instruction and we
19918 do not want to do it again. */
19919 newinsn &= ~ 0xf0000;
19920 newinsn |= ((newinsn & 0x0f000) << 4);
19921 }
b99bd4ef 19922
c19d1205
ZW
19923 newimm |= (temp & 0xfffff000);
19924 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
b99bd4ef 19925
c19d1205
ZW
19926 highpart |= (newinsn & 0xfffff000);
19927 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
19928 }
19929 break;
b99bd4ef 19930
c19d1205 19931 case BFD_RELOC_ARM_OFFSET_IMM:
00a97672
RS
19932 if (!fixP->fx_done && seg->use_rela_p)
19933 value = 0;
19934
c19d1205
ZW
19935 case BFD_RELOC_ARM_LITERAL:
19936 sign = value >= 0;
b99bd4ef 19937
c19d1205
ZW
19938 if (value < 0)
19939 value = - value;
b99bd4ef 19940
c19d1205 19941 if (validate_offset_imm (value, 0) == FAIL)
f03698e6 19942 {
c19d1205
ZW
19943 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
19944 as_bad_where (fixP->fx_file, fixP->fx_line,
19945 _("invalid literal constant: pool needs to be closer"));
19946 else
19947 as_bad_where (fixP->fx_file, fixP->fx_line,
19948 _("bad immediate value for offset (%ld)"),
19949 (long) value);
19950 break;
f03698e6
RE
19951 }
19952
c19d1205
ZW
19953 newval = md_chars_to_number (buf, INSN_SIZE);
19954 newval &= 0xff7ff000;
19955 newval |= value | (sign ? INDEX_UP : 0);
19956 md_number_to_chars (buf, newval, INSN_SIZE);
19957 break;
b99bd4ef 19958
c19d1205
ZW
19959 case BFD_RELOC_ARM_OFFSET_IMM8:
19960 case BFD_RELOC_ARM_HWLITERAL:
19961 sign = value >= 0;
b99bd4ef 19962
c19d1205
ZW
19963 if (value < 0)
19964 value = - value;
b99bd4ef 19965
c19d1205 19966 if (validate_offset_imm (value, 1) == FAIL)
b99bd4ef 19967 {
c19d1205
ZW
19968 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
19969 as_bad_where (fixP->fx_file, fixP->fx_line,
19970 _("invalid literal constant: pool needs to be closer"));
19971 else
f9d4405b 19972 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
c19d1205
ZW
19973 (long) value);
19974 break;
b99bd4ef
NC
19975 }
19976
c19d1205
ZW
19977 newval = md_chars_to_number (buf, INSN_SIZE);
19978 newval &= 0xff7ff0f0;
19979 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
19980 md_number_to_chars (buf, newval, INSN_SIZE);
19981 break;
b99bd4ef 19982
c19d1205
ZW
19983 case BFD_RELOC_ARM_T32_OFFSET_U8:
19984 if (value < 0 || value > 1020 || value % 4 != 0)
19985 as_bad_where (fixP->fx_file, fixP->fx_line,
19986 _("bad immediate value for offset (%ld)"), (long) value);
19987 value /= 4;
b99bd4ef 19988
c19d1205 19989 newval = md_chars_to_number (buf+2, THUMB_SIZE);
c19d1205
ZW
19990 newval |= value;
19991 md_number_to_chars (buf+2, newval, THUMB_SIZE);
19992 break;
b99bd4ef 19993
c19d1205
ZW
19994 case BFD_RELOC_ARM_T32_OFFSET_IMM:
19995 /* This is a complicated relocation used for all varieties of Thumb32
19996 load/store instruction with immediate offset:
19997
19998 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
19999 *4, optional writeback(W)
20000 (doubleword load/store)
20001
20002 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20003 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20004 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20005 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20006 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20007
20008 Uppercase letters indicate bits that are already encoded at
20009 this point. Lowercase letters are our problem. For the
20010 second block of instructions, the secondary opcode nybble
20011 (bits 8..11) is present, and bit 23 is zero, even if this is
20012 a PC-relative operation. */
20013 newval = md_chars_to_number (buf, THUMB_SIZE);
20014 newval <<= 16;
20015 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
b99bd4ef 20016
c19d1205 20017 if ((newval & 0xf0000000) == 0xe0000000)
b99bd4ef 20018 {
c19d1205
ZW
20019 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20020 if (value >= 0)
20021 newval |= (1 << 23);
20022 else
20023 value = -value;
20024 if (value % 4 != 0)
20025 {
20026 as_bad_where (fixP->fx_file, fixP->fx_line,
20027 _("offset not a multiple of 4"));
20028 break;
20029 }
20030 value /= 4;
216d22bc 20031 if (value > 0xff)
c19d1205
ZW
20032 {
20033 as_bad_where (fixP->fx_file, fixP->fx_line,
20034 _("offset out of range"));
20035 break;
20036 }
20037 newval &= ~0xff;
b99bd4ef 20038 }
c19d1205 20039 else if ((newval & 0x000f0000) == 0x000f0000)
b99bd4ef 20040 {
c19d1205
ZW
20041 /* PC-relative, 12-bit offset. */
20042 if (value >= 0)
20043 newval |= (1 << 23);
20044 else
20045 value = -value;
216d22bc 20046 if (value > 0xfff)
c19d1205
ZW
20047 {
20048 as_bad_where (fixP->fx_file, fixP->fx_line,
20049 _("offset out of range"));
20050 break;
20051 }
20052 newval &= ~0xfff;
b99bd4ef 20053 }
c19d1205 20054 else if ((newval & 0x00000100) == 0x00000100)
b99bd4ef 20055 {
c19d1205
ZW
20056 /* Writeback: 8-bit, +/- offset. */
20057 if (value >= 0)
20058 newval |= (1 << 9);
20059 else
20060 value = -value;
216d22bc 20061 if (value > 0xff)
c19d1205
ZW
20062 {
20063 as_bad_where (fixP->fx_file, fixP->fx_line,
20064 _("offset out of range"));
20065 break;
20066 }
20067 newval &= ~0xff;
b99bd4ef 20068 }
c19d1205 20069 else if ((newval & 0x00000f00) == 0x00000e00)
b99bd4ef 20070 {
c19d1205 20071 /* T-instruction: positive 8-bit offset. */
216d22bc 20072 if (value < 0 || value > 0xff)
b99bd4ef 20073 {
c19d1205
ZW
20074 as_bad_where (fixP->fx_file, fixP->fx_line,
20075 _("offset out of range"));
20076 break;
b99bd4ef 20077 }
c19d1205
ZW
20078 newval &= ~0xff;
20079 newval |= value;
b99bd4ef
NC
20080 }
20081 else
b99bd4ef 20082 {
c19d1205
ZW
20083 /* Positive 12-bit or negative 8-bit offset. */
20084 int limit;
20085 if (value >= 0)
b99bd4ef 20086 {
c19d1205
ZW
20087 newval |= (1 << 23);
20088 limit = 0xfff;
20089 }
20090 else
20091 {
20092 value = -value;
20093 limit = 0xff;
20094 }
20095 if (value > limit)
20096 {
20097 as_bad_where (fixP->fx_file, fixP->fx_line,
20098 _("offset out of range"));
20099 break;
b99bd4ef 20100 }
c19d1205 20101 newval &= ~limit;
b99bd4ef 20102 }
b99bd4ef 20103
c19d1205
ZW
20104 newval |= value;
20105 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
20106 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
20107 break;
404ff6b5 20108
c19d1205
ZW
20109 case BFD_RELOC_ARM_SHIFT_IMM:
20110 newval = md_chars_to_number (buf, INSN_SIZE);
20111 if (((unsigned long) value) > 32
20112 || (value == 32
20113 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
20114 {
20115 as_bad_where (fixP->fx_file, fixP->fx_line,
20116 _("shift expression is too large"));
20117 break;
20118 }
404ff6b5 20119
c19d1205
ZW
20120 if (value == 0)
20121 /* Shifts of zero must be done as lsl. */
20122 newval &= ~0x60;
20123 else if (value == 32)
20124 value = 0;
20125 newval &= 0xfffff07f;
20126 newval |= (value & 0x1f) << 7;
20127 md_number_to_chars (buf, newval, INSN_SIZE);
20128 break;
404ff6b5 20129
c19d1205 20130 case BFD_RELOC_ARM_T32_IMMEDIATE:
16805f35 20131 case BFD_RELOC_ARM_T32_ADD_IMM:
92e90b6e 20132 case BFD_RELOC_ARM_T32_IMM12:
e9f89963 20133 case BFD_RELOC_ARM_T32_ADD_PC12:
c19d1205
ZW
20134 /* We claim that this fixup has been processed here,
20135 even if in fact we generate an error because we do
20136 not have a reloc for it, so tc_gen_reloc will reject it. */
20137 fixP->fx_done = 1;
404ff6b5 20138
c19d1205
ZW
20139 if (fixP->fx_addsy
20140 && ! S_IS_DEFINED (fixP->fx_addsy))
20141 {
20142 as_bad_where (fixP->fx_file, fixP->fx_line,
20143 _("undefined symbol %s used as an immediate value"),
20144 S_GET_NAME (fixP->fx_addsy));
20145 break;
20146 }
404ff6b5 20147
c19d1205
ZW
20148 newval = md_chars_to_number (buf, THUMB_SIZE);
20149 newval <<= 16;
20150 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
404ff6b5 20151
16805f35
PB
20152 newimm = FAIL;
20153 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
20154 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
ef8d22e6
PB
20155 {
20156 newimm = encode_thumb32_immediate (value);
20157 if (newimm == (unsigned int) FAIL)
20158 newimm = thumb32_negate_data_op (&newval, value);
20159 }
16805f35
PB
20160 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
20161 && newimm == (unsigned int) FAIL)
92e90b6e 20162 {
16805f35
PB
20163 /* Turn add/sum into addw/subw. */
20164 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20165 newval = (newval & 0xfeffffff) | 0x02000000;
20166
e9f89963
PB
20167 /* 12 bit immediate for addw/subw. */
20168 if (value < 0)
20169 {
20170 value = -value;
20171 newval ^= 0x00a00000;
20172 }
92e90b6e
PB
20173 if (value > 0xfff)
20174 newimm = (unsigned int) FAIL;
20175 else
20176 newimm = value;
20177 }
cc8a6dd0 20178
c19d1205 20179 if (newimm == (unsigned int)FAIL)
3631a3c8 20180 {
c19d1205
ZW
20181 as_bad_where (fixP->fx_file, fixP->fx_line,
20182 _("invalid constant (%lx) after fixup"),
20183 (unsigned long) value);
20184 break;
3631a3c8
NC
20185 }
20186
c19d1205
ZW
20187 newval |= (newimm & 0x800) << 15;
20188 newval |= (newimm & 0x700) << 4;
20189 newval |= (newimm & 0x0ff);
cc8a6dd0 20190
c19d1205
ZW
20191 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
20192 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
20193 break;
a737bd4d 20194
3eb17e6b 20195 case BFD_RELOC_ARM_SMC:
c19d1205
ZW
20196 if (((unsigned long) value) > 0xffff)
20197 as_bad_where (fixP->fx_file, fixP->fx_line,
3eb17e6b 20198 _("invalid smc expression"));
2fc8bdac 20199 newval = md_chars_to_number (buf, INSN_SIZE);
c19d1205
ZW
20200 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
20201 md_number_to_chars (buf, newval, INSN_SIZE);
20202 break;
a737bd4d 20203
c19d1205 20204 case BFD_RELOC_ARM_SWI:
adbaf948 20205 if (fixP->tc_fix_data != 0)
c19d1205
ZW
20206 {
20207 if (((unsigned long) value) > 0xff)
20208 as_bad_where (fixP->fx_file, fixP->fx_line,
20209 _("invalid swi expression"));
2fc8bdac 20210 newval = md_chars_to_number (buf, THUMB_SIZE);
c19d1205
ZW
20211 newval |= value;
20212 md_number_to_chars (buf, newval, THUMB_SIZE);
20213 }
20214 else
20215 {
20216 if (((unsigned long) value) > 0x00ffffff)
20217 as_bad_where (fixP->fx_file, fixP->fx_line,
20218 _("invalid swi expression"));
2fc8bdac 20219 newval = md_chars_to_number (buf, INSN_SIZE);
c19d1205
ZW
20220 newval |= value;
20221 md_number_to_chars (buf, newval, INSN_SIZE);
20222 }
20223 break;
a737bd4d 20224
c19d1205
ZW
20225 case BFD_RELOC_ARM_MULTI:
20226 if (((unsigned long) value) > 0xffff)
20227 as_bad_where (fixP->fx_file, fixP->fx_line,
20228 _("invalid expression in load/store multiple"));
20229 newval = value | md_chars_to_number (buf, INSN_SIZE);
20230 md_number_to_chars (buf, newval, INSN_SIZE);
20231 break;
a737bd4d 20232
c19d1205 20233#ifdef OBJ_ELF
39b41c9c 20234 case BFD_RELOC_ARM_PCREL_CALL:
267bf995
RR
20235
20236 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20237 && fixP->fx_addsy
20238 && !S_IS_EXTERNAL (fixP->fx_addsy)
20239 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20240 && THUMB_IS_FUNC (fixP->fx_addsy))
20241 /* Flip the bl to blx. This is a simple flip
20242 bit here because we generate PCREL_CALL for
20243 unconditional bls. */
20244 {
20245 newval = md_chars_to_number (buf, INSN_SIZE);
20246 newval = newval | 0x10000000;
20247 md_number_to_chars (buf, newval, INSN_SIZE);
20248 temp = 1;
20249 fixP->fx_done = 1;
20250 }
39b41c9c
PB
20251 else
20252 temp = 3;
20253 goto arm_branch_common;
20254
20255 case BFD_RELOC_ARM_PCREL_JUMP:
267bf995
RR
20256 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20257 && fixP->fx_addsy
20258 && !S_IS_EXTERNAL (fixP->fx_addsy)
20259 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20260 && THUMB_IS_FUNC (fixP->fx_addsy))
20261 {
20262 /* This would map to a bl<cond>, b<cond>,
20263 b<always> to a Thumb function. We
20264 need to force a relocation for this particular
20265 case. */
20266 newval = md_chars_to_number (buf, INSN_SIZE);
20267 fixP->fx_done = 0;
20268 }
20269
2fc8bdac 20270 case BFD_RELOC_ARM_PLT32:
c19d1205 20271#endif
39b41c9c
PB
20272 case BFD_RELOC_ARM_PCREL_BRANCH:
20273 temp = 3;
20274 goto arm_branch_common;
a737bd4d 20275
39b41c9c 20276 case BFD_RELOC_ARM_PCREL_BLX:
267bf995 20277
39b41c9c 20278 temp = 1;
267bf995
RR
20279 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20280 && fixP->fx_addsy
20281 && !S_IS_EXTERNAL (fixP->fx_addsy)
20282 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20283 && ARM_IS_FUNC (fixP->fx_addsy))
20284 {
20285 /* Flip the blx to a bl and warn. */
20286 const char *name = S_GET_NAME (fixP->fx_addsy);
20287 newval = 0xeb000000;
20288 as_warn_where (fixP->fx_file, fixP->fx_line,
20289 _("blx to '%s' an ARM ISA state function changed to bl"),
20290 name);
20291 md_number_to_chars (buf, newval, INSN_SIZE);
20292 temp = 3;
20293 fixP->fx_done = 1;
20294 }
20295
20296#ifdef OBJ_ELF
20297 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
20298 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
20299#endif
20300
39b41c9c 20301 arm_branch_common:
c19d1205 20302 /* We are going to store value (shifted right by two) in the
39b41c9c
PB
20303 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20304 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20305 also be be clear. */
20306 if (value & temp)
c19d1205 20307 as_bad_where (fixP->fx_file, fixP->fx_line,
2fc8bdac
ZW
20308 _("misaligned branch destination"));
20309 if ((value & (offsetT)0xfe000000) != (offsetT)0
20310 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
20311 as_bad_where (fixP->fx_file, fixP->fx_line,
20312 _("branch out of range"));
a737bd4d 20313
2fc8bdac 20314 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 20315 {
2fc8bdac
ZW
20316 newval = md_chars_to_number (buf, INSN_SIZE);
20317 newval |= (value >> 2) & 0x00ffffff;
7ae2971b
PB
20318 /* Set the H bit on BLX instructions. */
20319 if (temp == 1)
20320 {
20321 if (value & 2)
20322 newval |= 0x01000000;
20323 else
20324 newval &= ~0x01000000;
20325 }
2fc8bdac 20326 md_number_to_chars (buf, newval, INSN_SIZE);
c19d1205 20327 }
c19d1205 20328 break;
a737bd4d 20329
25fe350b
MS
20330 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
20331 /* CBZ can only branch forward. */
a737bd4d 20332
738755b0
MS
20333 /* Attempts to use CBZ to branch to the next instruction
20334 (which, strictly speaking, are prohibited) will be turned into
20335 no-ops.
20336
20337 FIXME: It may be better to remove the instruction completely and
20338 perform relaxation. */
20339 if (value == -2)
2fc8bdac
ZW
20340 {
20341 newval = md_chars_to_number (buf, THUMB_SIZE);
738755b0 20342 newval = 0xbf00; /* NOP encoding T1 */
2fc8bdac
ZW
20343 md_number_to_chars (buf, newval, THUMB_SIZE);
20344 }
738755b0
MS
20345 else
20346 {
20347 if (value & ~0x7e)
20348 as_bad_where (fixP->fx_file, fixP->fx_line,
20349 _("branch out of range"));
20350
20351 if (fixP->fx_done || !seg->use_rela_p)
20352 {
20353 newval = md_chars_to_number (buf, THUMB_SIZE);
20354 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
20355 md_number_to_chars (buf, newval, THUMB_SIZE);
20356 }
20357 }
c19d1205 20358 break;
a737bd4d 20359
c19d1205 20360 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
2fc8bdac
ZW
20361 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
20362 as_bad_where (fixP->fx_file, fixP->fx_line,
20363 _("branch out of range"));
a737bd4d 20364
2fc8bdac
ZW
20365 if (fixP->fx_done || !seg->use_rela_p)
20366 {
20367 newval = md_chars_to_number (buf, THUMB_SIZE);
20368 newval |= (value & 0x1ff) >> 1;
20369 md_number_to_chars (buf, newval, THUMB_SIZE);
20370 }
c19d1205 20371 break;
a737bd4d 20372
c19d1205 20373 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
2fc8bdac
ZW
20374 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
20375 as_bad_where (fixP->fx_file, fixP->fx_line,
20376 _("branch out of range"));
a737bd4d 20377
2fc8bdac
ZW
20378 if (fixP->fx_done || !seg->use_rela_p)
20379 {
20380 newval = md_chars_to_number (buf, THUMB_SIZE);
20381 newval |= (value & 0xfff) >> 1;
20382 md_number_to_chars (buf, newval, THUMB_SIZE);
20383 }
c19d1205 20384 break;
a737bd4d 20385
c19d1205 20386 case BFD_RELOC_THUMB_PCREL_BRANCH20:
267bf995
RR
20387 if (fixP->fx_addsy
20388 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20389 && !S_IS_EXTERNAL (fixP->fx_addsy)
20390 && S_IS_DEFINED (fixP->fx_addsy)
20391 && ARM_IS_FUNC (fixP->fx_addsy)
20392 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20393 {
20394 /* Force a relocation for a branch 20 bits wide. */
20395 fixP->fx_done = 0;
20396 }
2fc8bdac
ZW
20397 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
20398 as_bad_where (fixP->fx_file, fixP->fx_line,
20399 _("conditional branch out of range"));
404ff6b5 20400
2fc8bdac
ZW
20401 if (fixP->fx_done || !seg->use_rela_p)
20402 {
20403 offsetT newval2;
20404 addressT S, J1, J2, lo, hi;
404ff6b5 20405
2fc8bdac
ZW
20406 S = (value & 0x00100000) >> 20;
20407 J2 = (value & 0x00080000) >> 19;
20408 J1 = (value & 0x00040000) >> 18;
20409 hi = (value & 0x0003f000) >> 12;
20410 lo = (value & 0x00000ffe) >> 1;
6c43fab6 20411
2fc8bdac
ZW
20412 newval = md_chars_to_number (buf, THUMB_SIZE);
20413 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20414 newval |= (S << 10) | hi;
20415 newval2 |= (J1 << 13) | (J2 << 11) | lo;
20416 md_number_to_chars (buf, newval, THUMB_SIZE);
20417 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
20418 }
c19d1205 20419 break;
6c43fab6 20420
c19d1205 20421 case BFD_RELOC_THUMB_PCREL_BLX:
267bf995
RR
20422
20423 /* If there is a blx from a thumb state function to
20424 another thumb function flip this to a bl and warn
20425 about it. */
20426
20427 if (fixP->fx_addsy
20428 && S_IS_DEFINED (fixP->fx_addsy)
20429 && !S_IS_EXTERNAL (fixP->fx_addsy)
20430 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20431 && THUMB_IS_FUNC (fixP->fx_addsy))
20432 {
20433 const char *name = S_GET_NAME (fixP->fx_addsy);
20434 as_warn_where (fixP->fx_file, fixP->fx_line,
20435 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20436 name);
20437 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20438 newval = newval | 0x1000;
20439 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
20440 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
20441 fixP->fx_done = 1;
20442 }
20443
20444
20445 goto thumb_bl_common;
20446
c19d1205 20447 case BFD_RELOC_THUMB_PCREL_BRANCH23:
267bf995
RR
20448
20449 /* A bl from Thumb state ISA to an internal ARM state function
20450 is converted to a blx. */
20451 if (fixP->fx_addsy
20452 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20453 && !S_IS_EXTERNAL (fixP->fx_addsy)
20454 && S_IS_DEFINED (fixP->fx_addsy)
20455 && ARM_IS_FUNC (fixP->fx_addsy)
20456 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20457 {
20458 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20459 newval = newval & ~0x1000;
20460 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
20461 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
20462 fixP->fx_done = 1;
20463 }
20464
20465 thumb_bl_common:
20466
20467#ifdef OBJ_ELF
20468 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 &&
20469 fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
20470 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
20471#endif
20472
2fc8bdac
ZW
20473 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
20474 /* For a BLX instruction, make sure that the relocation is rounded up
20475 to a word boundary. This follows the semantics of the instruction
20476 which specifies that bit 1 of the target address will come from bit
20477 1 of the base address. */
20478 value = (value + 1) & ~ 1;
404ff6b5 20479
2fc8bdac 20480
4a42ebbc
RR
20481 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
20482 {
20483 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
20484 {
20485 as_bad_where (fixP->fx_file, fixP->fx_line,
20486 _("branch out of range"));
20487 }
20488 else if ((value & ~0x1ffffff)
20489 && ((value & ~0x1ffffff) != ~0x1ffffff))
20490 {
20491 as_bad_where (fixP->fx_file, fixP->fx_line,
20492 _("Thumb2 branch out of range"));
20493 }
c19d1205 20494 }
4a42ebbc
RR
20495
20496 if (fixP->fx_done || !seg->use_rela_p)
20497 encode_thumb2_b_bl_offset (buf, value);
20498
c19d1205 20499 break;
404ff6b5 20500
c19d1205 20501 case BFD_RELOC_THUMB_PCREL_BRANCH25:
2fc8bdac
ZW
20502 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
20503 as_bad_where (fixP->fx_file, fixP->fx_line,
20504 _("branch out of range"));
6c43fab6 20505
2fc8bdac 20506 if (fixP->fx_done || !seg->use_rela_p)
4a42ebbc 20507 encode_thumb2_b_bl_offset (buf, value);
6c43fab6 20508
2fc8bdac 20509 break;
a737bd4d 20510
2fc8bdac
ZW
20511 case BFD_RELOC_8:
20512 if (fixP->fx_done || !seg->use_rela_p)
20513 md_number_to_chars (buf, value, 1);
c19d1205 20514 break;
a737bd4d 20515
c19d1205 20516 case BFD_RELOC_16:
2fc8bdac 20517 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 20518 md_number_to_chars (buf, value, 2);
c19d1205 20519 break;
a737bd4d 20520
c19d1205
ZW
20521#ifdef OBJ_ELF
20522 case BFD_RELOC_ARM_TLS_GD32:
20523 case BFD_RELOC_ARM_TLS_LE32:
20524 case BFD_RELOC_ARM_TLS_IE32:
20525 case BFD_RELOC_ARM_TLS_LDM32:
20526 case BFD_RELOC_ARM_TLS_LDO32:
20527 S_SET_THREAD_LOCAL (fixP->fx_addsy);
20528 /* fall through */
6c43fab6 20529
c19d1205
ZW
20530 case BFD_RELOC_ARM_GOT32:
20531 case BFD_RELOC_ARM_GOTOFF:
2fc8bdac
ZW
20532 if (fixP->fx_done || !seg->use_rela_p)
20533 md_number_to_chars (buf, 0, 4);
c19d1205 20534 break;
b43420e6
NC
20535
20536 case BFD_RELOC_ARM_GOT_PREL:
20537 if (fixP->fx_done || !seg->use_rela_p)
20538 md_number_to_chars (buf, value, 4);
20539 break;
20540
9a6f4e97
NS
20541 case BFD_RELOC_ARM_TARGET2:
20542 /* TARGET2 is not partial-inplace, so we need to write the
20543 addend here for REL targets, because it won't be written out
20544 during reloc processing later. */
20545 if (fixP->fx_done || !seg->use_rela_p)
20546 md_number_to_chars (buf, fixP->fx_offset, 4);
20547 break;
c19d1205 20548#endif
6c43fab6 20549
c19d1205
ZW
20550 case BFD_RELOC_RVA:
20551 case BFD_RELOC_32:
20552 case BFD_RELOC_ARM_TARGET1:
20553 case BFD_RELOC_ARM_ROSEGREL32:
20554 case BFD_RELOC_ARM_SBREL32:
20555 case BFD_RELOC_32_PCREL:
f0927246
NC
20556#ifdef TE_PE
20557 case BFD_RELOC_32_SECREL:
20558#endif
2fc8bdac 20559 if (fixP->fx_done || !seg->use_rela_p)
53baae48
NC
20560#ifdef TE_WINCE
20561 /* For WinCE we only do this for pcrel fixups. */
20562 if (fixP->fx_done || fixP->fx_pcrel)
20563#endif
20564 md_number_to_chars (buf, value, 4);
c19d1205 20565 break;
6c43fab6 20566
c19d1205
ZW
20567#ifdef OBJ_ELF
20568 case BFD_RELOC_ARM_PREL31:
2fc8bdac 20569 if (fixP->fx_done || !seg->use_rela_p)
c19d1205
ZW
20570 {
20571 newval = md_chars_to_number (buf, 4) & 0x80000000;
20572 if ((value ^ (value >> 1)) & 0x40000000)
20573 {
20574 as_bad_where (fixP->fx_file, fixP->fx_line,
20575 _("rel31 relocation overflow"));
20576 }
20577 newval |= value & 0x7fffffff;
20578 md_number_to_chars (buf, newval, 4);
20579 }
20580 break;
c19d1205 20581#endif
a737bd4d 20582
c19d1205 20583 case BFD_RELOC_ARM_CP_OFF_IMM:
8f06b2d8 20584 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
c19d1205
ZW
20585 if (value < -1023 || value > 1023 || (value & 3))
20586 as_bad_where (fixP->fx_file, fixP->fx_line,
20587 _("co-processor offset out of range"));
20588 cp_off_common:
20589 sign = value >= 0;
20590 if (value < 0)
20591 value = -value;
8f06b2d8
PB
20592 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
20593 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
20594 newval = md_chars_to_number (buf, INSN_SIZE);
20595 else
20596 newval = get_thumb32_insn (buf);
20597 newval &= 0xff7fff00;
c19d1205 20598 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
8f06b2d8
PB
20599 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
20600 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
20601 md_number_to_chars (buf, newval, INSN_SIZE);
20602 else
20603 put_thumb32_insn (buf, newval);
c19d1205 20604 break;
a737bd4d 20605
c19d1205 20606 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
8f06b2d8 20607 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
c19d1205
ZW
20608 if (value < -255 || value > 255)
20609 as_bad_where (fixP->fx_file, fixP->fx_line,
20610 _("co-processor offset out of range"));
df7849c5 20611 value *= 4;
c19d1205 20612 goto cp_off_common;
6c43fab6 20613
c19d1205
ZW
20614 case BFD_RELOC_ARM_THUMB_OFFSET:
20615 newval = md_chars_to_number (buf, THUMB_SIZE);
20616 /* Exactly what ranges, and where the offset is inserted depends
20617 on the type of instruction, we can establish this from the
20618 top 4 bits. */
20619 switch (newval >> 12)
20620 {
20621 case 4: /* PC load. */
20622 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20623 forced to zero for these loads; md_pcrel_from has already
20624 compensated for this. */
20625 if (value & 3)
20626 as_bad_where (fixP->fx_file, fixP->fx_line,
20627 _("invalid offset, target not word aligned (0x%08lX)"),
0359e808
NC
20628 (((unsigned long) fixP->fx_frag->fr_address
20629 + (unsigned long) fixP->fx_where) & ~3)
20630 + (unsigned long) value);
a737bd4d 20631
c19d1205
ZW
20632 if (value & ~0x3fc)
20633 as_bad_where (fixP->fx_file, fixP->fx_line,
20634 _("invalid offset, value too big (0x%08lX)"),
20635 (long) value);
a737bd4d 20636
c19d1205
ZW
20637 newval |= value >> 2;
20638 break;
a737bd4d 20639
c19d1205
ZW
20640 case 9: /* SP load/store. */
20641 if (value & ~0x3fc)
20642 as_bad_where (fixP->fx_file, fixP->fx_line,
20643 _("invalid offset, value too big (0x%08lX)"),
20644 (long) value);
20645 newval |= value >> 2;
20646 break;
6c43fab6 20647
c19d1205
ZW
20648 case 6: /* Word load/store. */
20649 if (value & ~0x7c)
20650 as_bad_where (fixP->fx_file, fixP->fx_line,
20651 _("invalid offset, value too big (0x%08lX)"),
20652 (long) value);
20653 newval |= value << 4; /* 6 - 2. */
20654 break;
a737bd4d 20655
c19d1205
ZW
20656 case 7: /* Byte load/store. */
20657 if (value & ~0x1f)
20658 as_bad_where (fixP->fx_file, fixP->fx_line,
20659 _("invalid offset, value too big (0x%08lX)"),
20660 (long) value);
20661 newval |= value << 6;
20662 break;
a737bd4d 20663
c19d1205
ZW
20664 case 8: /* Halfword load/store. */
20665 if (value & ~0x3e)
20666 as_bad_where (fixP->fx_file, fixP->fx_line,
20667 _("invalid offset, value too big (0x%08lX)"),
20668 (long) value);
20669 newval |= value << 5; /* 6 - 1. */
20670 break;
a737bd4d 20671
c19d1205
ZW
20672 default:
20673 as_bad_where (fixP->fx_file, fixP->fx_line,
20674 "Unable to process relocation for thumb opcode: %lx",
20675 (unsigned long) newval);
20676 break;
20677 }
20678 md_number_to_chars (buf, newval, THUMB_SIZE);
20679 break;
a737bd4d 20680
c19d1205
ZW
20681 case BFD_RELOC_ARM_THUMB_ADD:
20682 /* This is a complicated relocation, since we use it for all of
20683 the following immediate relocations:
a737bd4d 20684
c19d1205
ZW
20685 3bit ADD/SUB
20686 8bit ADD/SUB
20687 9bit ADD/SUB SP word-aligned
20688 10bit ADD PC/SP word-aligned
a737bd4d 20689
c19d1205
ZW
20690 The type of instruction being processed is encoded in the
20691 instruction field:
a737bd4d 20692
c19d1205
ZW
20693 0x8000 SUB
20694 0x00F0 Rd
20695 0x000F Rs
20696 */
20697 newval = md_chars_to_number (buf, THUMB_SIZE);
20698 {
20699 int rd = (newval >> 4) & 0xf;
20700 int rs = newval & 0xf;
20701 int subtract = !!(newval & 0x8000);
a737bd4d 20702
c19d1205
ZW
20703 /* Check for HI regs, only very restricted cases allowed:
20704 Adjusting SP, and using PC or SP to get an address. */
20705 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
20706 || (rs > 7 && rs != REG_SP && rs != REG_PC))
20707 as_bad_where (fixP->fx_file, fixP->fx_line,
20708 _("invalid Hi register with immediate"));
a737bd4d 20709
c19d1205
ZW
20710 /* If value is negative, choose the opposite instruction. */
20711 if (value < 0)
20712 {
20713 value = -value;
20714 subtract = !subtract;
20715 if (value < 0)
20716 as_bad_where (fixP->fx_file, fixP->fx_line,
20717 _("immediate value out of range"));
20718 }
a737bd4d 20719
c19d1205
ZW
20720 if (rd == REG_SP)
20721 {
20722 if (value & ~0x1fc)
20723 as_bad_where (fixP->fx_file, fixP->fx_line,
20724 _("invalid immediate for stack address calculation"));
20725 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
20726 newval |= value >> 2;
20727 }
20728 else if (rs == REG_PC || rs == REG_SP)
20729 {
20730 if (subtract || value & ~0x3fc)
20731 as_bad_where (fixP->fx_file, fixP->fx_line,
20732 _("invalid immediate for address calculation (value = 0x%08lX)"),
20733 (unsigned long) value);
20734 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
20735 newval |= rd << 8;
20736 newval |= value >> 2;
20737 }
20738 else if (rs == rd)
20739 {
20740 if (value & ~0xff)
20741 as_bad_where (fixP->fx_file, fixP->fx_line,
20742 _("immediate value out of range"));
20743 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
20744 newval |= (rd << 8) | value;
20745 }
20746 else
20747 {
20748 if (value & ~0x7)
20749 as_bad_where (fixP->fx_file, fixP->fx_line,
20750 _("immediate value out of range"));
20751 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
20752 newval |= rd | (rs << 3) | (value << 6);
20753 }
20754 }
20755 md_number_to_chars (buf, newval, THUMB_SIZE);
20756 break;
a737bd4d 20757
c19d1205
ZW
20758 case BFD_RELOC_ARM_THUMB_IMM:
20759 newval = md_chars_to_number (buf, THUMB_SIZE);
20760 if (value < 0 || value > 255)
20761 as_bad_where (fixP->fx_file, fixP->fx_line,
4e6e072b 20762 _("invalid immediate: %ld is out of range"),
c19d1205
ZW
20763 (long) value);
20764 newval |= value;
20765 md_number_to_chars (buf, newval, THUMB_SIZE);
20766 break;
a737bd4d 20767
c19d1205
ZW
20768 case BFD_RELOC_ARM_THUMB_SHIFT:
20769 /* 5bit shift value (0..32). LSL cannot take 32. */
20770 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
20771 temp = newval & 0xf800;
20772 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
20773 as_bad_where (fixP->fx_file, fixP->fx_line,
20774 _("invalid shift value: %ld"), (long) value);
20775 /* Shifts of zero must be encoded as LSL. */
20776 if (value == 0)
20777 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
20778 /* Shifts of 32 are encoded as zero. */
20779 else if (value == 32)
20780 value = 0;
20781 newval |= value << 6;
20782 md_number_to_chars (buf, newval, THUMB_SIZE);
20783 break;
a737bd4d 20784
c19d1205
ZW
20785 case BFD_RELOC_VTABLE_INHERIT:
20786 case BFD_RELOC_VTABLE_ENTRY:
20787 fixP->fx_done = 0;
20788 return;
6c43fab6 20789
b6895b4f
PB
20790 case BFD_RELOC_ARM_MOVW:
20791 case BFD_RELOC_ARM_MOVT:
20792 case BFD_RELOC_ARM_THUMB_MOVW:
20793 case BFD_RELOC_ARM_THUMB_MOVT:
20794 if (fixP->fx_done || !seg->use_rela_p)
20795 {
20796 /* REL format relocations are limited to a 16-bit addend. */
20797 if (!fixP->fx_done)
20798 {
39623e12 20799 if (value < -0x8000 || value > 0x7fff)
b6895b4f 20800 as_bad_where (fixP->fx_file, fixP->fx_line,
ff5075ca 20801 _("offset out of range"));
b6895b4f
PB
20802 }
20803 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
20804 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
20805 {
20806 value >>= 16;
20807 }
20808
20809 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
20810 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
20811 {
20812 newval = get_thumb32_insn (buf);
20813 newval &= 0xfbf08f00;
20814 newval |= (value & 0xf000) << 4;
20815 newval |= (value & 0x0800) << 15;
20816 newval |= (value & 0x0700) << 4;
20817 newval |= (value & 0x00ff);
20818 put_thumb32_insn (buf, newval);
20819 }
20820 else
20821 {
20822 newval = md_chars_to_number (buf, 4);
20823 newval &= 0xfff0f000;
20824 newval |= value & 0x0fff;
20825 newval |= (value & 0xf000) << 4;
20826 md_number_to_chars (buf, newval, 4);
20827 }
20828 }
20829 return;
20830
4962c51a
MS
20831 case BFD_RELOC_ARM_ALU_PC_G0_NC:
20832 case BFD_RELOC_ARM_ALU_PC_G0:
20833 case BFD_RELOC_ARM_ALU_PC_G1_NC:
20834 case BFD_RELOC_ARM_ALU_PC_G1:
20835 case BFD_RELOC_ARM_ALU_PC_G2:
20836 case BFD_RELOC_ARM_ALU_SB_G0_NC:
20837 case BFD_RELOC_ARM_ALU_SB_G0:
20838 case BFD_RELOC_ARM_ALU_SB_G1_NC:
20839 case BFD_RELOC_ARM_ALU_SB_G1:
20840 case BFD_RELOC_ARM_ALU_SB_G2:
9c2799c2 20841 gas_assert (!fixP->fx_done);
4962c51a
MS
20842 if (!seg->use_rela_p)
20843 {
20844 bfd_vma insn;
20845 bfd_vma encoded_addend;
20846 bfd_vma addend_abs = abs (value);
20847
20848 /* Check that the absolute value of the addend can be
20849 expressed as an 8-bit constant plus a rotation. */
20850 encoded_addend = encode_arm_immediate (addend_abs);
20851 if (encoded_addend == (unsigned int) FAIL)
20852 as_bad_where (fixP->fx_file, fixP->fx_line,
20853 _("the offset 0x%08lX is not representable"),
495bde8e 20854 (unsigned long) addend_abs);
4962c51a
MS
20855
20856 /* Extract the instruction. */
20857 insn = md_chars_to_number (buf, INSN_SIZE);
20858
20859 /* If the addend is positive, use an ADD instruction.
20860 Otherwise use a SUB. Take care not to destroy the S bit. */
20861 insn &= 0xff1fffff;
20862 if (value < 0)
20863 insn |= 1 << 22;
20864 else
20865 insn |= 1 << 23;
20866
20867 /* Place the encoded addend into the first 12 bits of the
20868 instruction. */
20869 insn &= 0xfffff000;
20870 insn |= encoded_addend;
5f4273c7
NC
20871
20872 /* Update the instruction. */
4962c51a
MS
20873 md_number_to_chars (buf, insn, INSN_SIZE);
20874 }
20875 break;
20876
20877 case BFD_RELOC_ARM_LDR_PC_G0:
20878 case BFD_RELOC_ARM_LDR_PC_G1:
20879 case BFD_RELOC_ARM_LDR_PC_G2:
20880 case BFD_RELOC_ARM_LDR_SB_G0:
20881 case BFD_RELOC_ARM_LDR_SB_G1:
20882 case BFD_RELOC_ARM_LDR_SB_G2:
9c2799c2 20883 gas_assert (!fixP->fx_done);
4962c51a
MS
20884 if (!seg->use_rela_p)
20885 {
20886 bfd_vma insn;
20887 bfd_vma addend_abs = abs (value);
20888
20889 /* Check that the absolute value of the addend can be
20890 encoded in 12 bits. */
20891 if (addend_abs >= 0x1000)
20892 as_bad_where (fixP->fx_file, fixP->fx_line,
20893 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
495bde8e 20894 (unsigned long) addend_abs);
4962c51a
MS
20895
20896 /* Extract the instruction. */
20897 insn = md_chars_to_number (buf, INSN_SIZE);
20898
20899 /* If the addend is negative, clear bit 23 of the instruction.
20900 Otherwise set it. */
20901 if (value < 0)
20902 insn &= ~(1 << 23);
20903 else
20904 insn |= 1 << 23;
20905
20906 /* Place the absolute value of the addend into the first 12 bits
20907 of the instruction. */
20908 insn &= 0xfffff000;
20909 insn |= addend_abs;
5f4273c7
NC
20910
20911 /* Update the instruction. */
4962c51a
MS
20912 md_number_to_chars (buf, insn, INSN_SIZE);
20913 }
20914 break;
20915
20916 case BFD_RELOC_ARM_LDRS_PC_G0:
20917 case BFD_RELOC_ARM_LDRS_PC_G1:
20918 case BFD_RELOC_ARM_LDRS_PC_G2:
20919 case BFD_RELOC_ARM_LDRS_SB_G0:
20920 case BFD_RELOC_ARM_LDRS_SB_G1:
20921 case BFD_RELOC_ARM_LDRS_SB_G2:
9c2799c2 20922 gas_assert (!fixP->fx_done);
4962c51a
MS
20923 if (!seg->use_rela_p)
20924 {
20925 bfd_vma insn;
20926 bfd_vma addend_abs = abs (value);
20927
20928 /* Check that the absolute value of the addend can be
20929 encoded in 8 bits. */
20930 if (addend_abs >= 0x100)
20931 as_bad_where (fixP->fx_file, fixP->fx_line,
20932 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
495bde8e 20933 (unsigned long) addend_abs);
4962c51a
MS
20934
20935 /* Extract the instruction. */
20936 insn = md_chars_to_number (buf, INSN_SIZE);
20937
20938 /* If the addend is negative, clear bit 23 of the instruction.
20939 Otherwise set it. */
20940 if (value < 0)
20941 insn &= ~(1 << 23);
20942 else
20943 insn |= 1 << 23;
20944
20945 /* Place the first four bits of the absolute value of the addend
20946 into the first 4 bits of the instruction, and the remaining
20947 four into bits 8 .. 11. */
20948 insn &= 0xfffff0f0;
20949 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
5f4273c7
NC
20950
20951 /* Update the instruction. */
4962c51a
MS
20952 md_number_to_chars (buf, insn, INSN_SIZE);
20953 }
20954 break;
20955
20956 case BFD_RELOC_ARM_LDC_PC_G0:
20957 case BFD_RELOC_ARM_LDC_PC_G1:
20958 case BFD_RELOC_ARM_LDC_PC_G2:
20959 case BFD_RELOC_ARM_LDC_SB_G0:
20960 case BFD_RELOC_ARM_LDC_SB_G1:
20961 case BFD_RELOC_ARM_LDC_SB_G2:
9c2799c2 20962 gas_assert (!fixP->fx_done);
4962c51a
MS
20963 if (!seg->use_rela_p)
20964 {
20965 bfd_vma insn;
20966 bfd_vma addend_abs = abs (value);
20967
20968 /* Check that the absolute value of the addend is a multiple of
20969 four and, when divided by four, fits in 8 bits. */
20970 if (addend_abs & 0x3)
20971 as_bad_where (fixP->fx_file, fixP->fx_line,
20972 _("bad offset 0x%08lX (must be word-aligned)"),
495bde8e 20973 (unsigned long) addend_abs);
4962c51a
MS
20974
20975 if ((addend_abs >> 2) > 0xff)
20976 as_bad_where (fixP->fx_file, fixP->fx_line,
20977 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
495bde8e 20978 (unsigned long) addend_abs);
4962c51a
MS
20979
20980 /* Extract the instruction. */
20981 insn = md_chars_to_number (buf, INSN_SIZE);
20982
20983 /* If the addend is negative, clear bit 23 of the instruction.
20984 Otherwise set it. */
20985 if (value < 0)
20986 insn &= ~(1 << 23);
20987 else
20988 insn |= 1 << 23;
20989
20990 /* Place the addend (divided by four) into the first eight
20991 bits of the instruction. */
20992 insn &= 0xfffffff0;
20993 insn |= addend_abs >> 2;
5f4273c7
NC
20994
20995 /* Update the instruction. */
4962c51a
MS
20996 md_number_to_chars (buf, insn, INSN_SIZE);
20997 }
20998 break;
20999
845b51d6
PB
21000 case BFD_RELOC_ARM_V4BX:
21001 /* This will need to go in the object file. */
21002 fixP->fx_done = 0;
21003 break;
21004
c19d1205
ZW
21005 case BFD_RELOC_UNUSED:
21006 default:
21007 as_bad_where (fixP->fx_file, fixP->fx_line,
21008 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
21009 }
6c43fab6
RE
21010}
21011
c19d1205
ZW
21012/* Translate internal representation of relocation info to BFD target
21013 format. */
a737bd4d 21014
c19d1205 21015arelent *
00a97672 21016tc_gen_reloc (asection *section, fixS *fixp)
a737bd4d 21017{
c19d1205
ZW
21018 arelent * reloc;
21019 bfd_reloc_code_real_type code;
a737bd4d 21020
21d799b5 21021 reloc = (arelent *) xmalloc (sizeof (arelent));
a737bd4d 21022
21d799b5 21023 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
c19d1205
ZW
21024 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
21025 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
a737bd4d 21026
2fc8bdac 21027 if (fixp->fx_pcrel)
00a97672
RS
21028 {
21029 if (section->use_rela_p)
21030 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
21031 else
21032 fixp->fx_offset = reloc->address;
21033 }
c19d1205 21034 reloc->addend = fixp->fx_offset;
a737bd4d 21035
c19d1205 21036 switch (fixp->fx_r_type)
a737bd4d 21037 {
c19d1205
ZW
21038 case BFD_RELOC_8:
21039 if (fixp->fx_pcrel)
21040 {
21041 code = BFD_RELOC_8_PCREL;
21042 break;
21043 }
a737bd4d 21044
c19d1205
ZW
21045 case BFD_RELOC_16:
21046 if (fixp->fx_pcrel)
21047 {
21048 code = BFD_RELOC_16_PCREL;
21049 break;
21050 }
6c43fab6 21051
c19d1205
ZW
21052 case BFD_RELOC_32:
21053 if (fixp->fx_pcrel)
21054 {
21055 code = BFD_RELOC_32_PCREL;
21056 break;
21057 }
a737bd4d 21058
b6895b4f
PB
21059 case BFD_RELOC_ARM_MOVW:
21060 if (fixp->fx_pcrel)
21061 {
21062 code = BFD_RELOC_ARM_MOVW_PCREL;
21063 break;
21064 }
21065
21066 case BFD_RELOC_ARM_MOVT:
21067 if (fixp->fx_pcrel)
21068 {
21069 code = BFD_RELOC_ARM_MOVT_PCREL;
21070 break;
21071 }
21072
21073 case BFD_RELOC_ARM_THUMB_MOVW:
21074 if (fixp->fx_pcrel)
21075 {
21076 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
21077 break;
21078 }
21079
21080 case BFD_RELOC_ARM_THUMB_MOVT:
21081 if (fixp->fx_pcrel)
21082 {
21083 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
21084 break;
21085 }
21086
c19d1205
ZW
21087 case BFD_RELOC_NONE:
21088 case BFD_RELOC_ARM_PCREL_BRANCH:
21089 case BFD_RELOC_ARM_PCREL_BLX:
21090 case BFD_RELOC_RVA:
21091 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21092 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21093 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21094 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21095 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21096 case BFD_RELOC_THUMB_PCREL_BRANCH25:
c19d1205
ZW
21097 case BFD_RELOC_VTABLE_ENTRY:
21098 case BFD_RELOC_VTABLE_INHERIT:
f0927246
NC
21099#ifdef TE_PE
21100 case BFD_RELOC_32_SECREL:
21101#endif
c19d1205
ZW
21102 code = fixp->fx_r_type;
21103 break;
a737bd4d 21104
00adf2d4
JB
21105 case BFD_RELOC_THUMB_PCREL_BLX:
21106#ifdef OBJ_ELF
21107 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21108 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
21109 else
21110#endif
21111 code = BFD_RELOC_THUMB_PCREL_BLX;
21112 break;
21113
c19d1205
ZW
21114 case BFD_RELOC_ARM_LITERAL:
21115 case BFD_RELOC_ARM_HWLITERAL:
21116 /* If this is called then the a literal has
21117 been referenced across a section boundary. */
21118 as_bad_where (fixp->fx_file, fixp->fx_line,
21119 _("literal referenced across section boundary"));
21120 return NULL;
a737bd4d 21121
c19d1205
ZW
21122#ifdef OBJ_ELF
21123 case BFD_RELOC_ARM_GOT32:
21124 case BFD_RELOC_ARM_GOTOFF:
b43420e6 21125 case BFD_RELOC_ARM_GOT_PREL:
c19d1205
ZW
21126 case BFD_RELOC_ARM_PLT32:
21127 case BFD_RELOC_ARM_TARGET1:
21128 case BFD_RELOC_ARM_ROSEGREL32:
21129 case BFD_RELOC_ARM_SBREL32:
21130 case BFD_RELOC_ARM_PREL31:
21131 case BFD_RELOC_ARM_TARGET2:
21132 case BFD_RELOC_ARM_TLS_LE32:
21133 case BFD_RELOC_ARM_TLS_LDO32:
39b41c9c
PB
21134 case BFD_RELOC_ARM_PCREL_CALL:
21135 case BFD_RELOC_ARM_PCREL_JUMP:
4962c51a
MS
21136 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21137 case BFD_RELOC_ARM_ALU_PC_G0:
21138 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21139 case BFD_RELOC_ARM_ALU_PC_G1:
21140 case BFD_RELOC_ARM_ALU_PC_G2:
21141 case BFD_RELOC_ARM_LDR_PC_G0:
21142 case BFD_RELOC_ARM_LDR_PC_G1:
21143 case BFD_RELOC_ARM_LDR_PC_G2:
21144 case BFD_RELOC_ARM_LDRS_PC_G0:
21145 case BFD_RELOC_ARM_LDRS_PC_G1:
21146 case BFD_RELOC_ARM_LDRS_PC_G2:
21147 case BFD_RELOC_ARM_LDC_PC_G0:
21148 case BFD_RELOC_ARM_LDC_PC_G1:
21149 case BFD_RELOC_ARM_LDC_PC_G2:
21150 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21151 case BFD_RELOC_ARM_ALU_SB_G0:
21152 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21153 case BFD_RELOC_ARM_ALU_SB_G1:
21154 case BFD_RELOC_ARM_ALU_SB_G2:
21155 case BFD_RELOC_ARM_LDR_SB_G0:
21156 case BFD_RELOC_ARM_LDR_SB_G1:
21157 case BFD_RELOC_ARM_LDR_SB_G2:
21158 case BFD_RELOC_ARM_LDRS_SB_G0:
21159 case BFD_RELOC_ARM_LDRS_SB_G1:
21160 case BFD_RELOC_ARM_LDRS_SB_G2:
21161 case BFD_RELOC_ARM_LDC_SB_G0:
21162 case BFD_RELOC_ARM_LDC_SB_G1:
21163 case BFD_RELOC_ARM_LDC_SB_G2:
845b51d6 21164 case BFD_RELOC_ARM_V4BX:
c19d1205
ZW
21165 code = fixp->fx_r_type;
21166 break;
a737bd4d 21167
c19d1205
ZW
21168 case BFD_RELOC_ARM_TLS_GD32:
21169 case BFD_RELOC_ARM_TLS_IE32:
21170 case BFD_RELOC_ARM_TLS_LDM32:
21171 /* BFD will include the symbol's address in the addend.
21172 But we don't want that, so subtract it out again here. */
21173 if (!S_IS_COMMON (fixp->fx_addsy))
21174 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
21175 code = fixp->fx_r_type;
21176 break;
21177#endif
a737bd4d 21178
c19d1205
ZW
21179 case BFD_RELOC_ARM_IMMEDIATE:
21180 as_bad_where (fixp->fx_file, fixp->fx_line,
21181 _("internal relocation (type: IMMEDIATE) not fixed up"));
21182 return NULL;
a737bd4d 21183
c19d1205
ZW
21184 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21185 as_bad_where (fixp->fx_file, fixp->fx_line,
21186 _("ADRL used for a symbol not defined in the same file"));
21187 return NULL;
a737bd4d 21188
c19d1205 21189 case BFD_RELOC_ARM_OFFSET_IMM:
00a97672
RS
21190 if (section->use_rela_p)
21191 {
21192 code = fixp->fx_r_type;
21193 break;
21194 }
21195
c19d1205
ZW
21196 if (fixp->fx_addsy != NULL
21197 && !S_IS_DEFINED (fixp->fx_addsy)
21198 && S_IS_LOCAL (fixp->fx_addsy))
a737bd4d 21199 {
c19d1205
ZW
21200 as_bad_where (fixp->fx_file, fixp->fx_line,
21201 _("undefined local label `%s'"),
21202 S_GET_NAME (fixp->fx_addsy));
21203 return NULL;
a737bd4d
NC
21204 }
21205
c19d1205
ZW
21206 as_bad_where (fixp->fx_file, fixp->fx_line,
21207 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21208 return NULL;
a737bd4d 21209
c19d1205
ZW
21210 default:
21211 {
21212 char * type;
6c43fab6 21213
c19d1205
ZW
21214 switch (fixp->fx_r_type)
21215 {
21216 case BFD_RELOC_NONE: type = "NONE"; break;
21217 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
21218 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
3eb17e6b 21219 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
c19d1205
ZW
21220 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
21221 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
21222 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
8f06b2d8 21223 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
c19d1205
ZW
21224 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
21225 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
21226 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
21227 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
21228 default: type = _("<unknown>"); break;
21229 }
21230 as_bad_where (fixp->fx_file, fixp->fx_line,
21231 _("cannot represent %s relocation in this object file format"),
21232 type);
21233 return NULL;
21234 }
a737bd4d 21235 }
6c43fab6 21236
c19d1205
ZW
21237#ifdef OBJ_ELF
21238 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
21239 && GOT_symbol
21240 && fixp->fx_addsy == GOT_symbol)
21241 {
21242 code = BFD_RELOC_ARM_GOTPC;
21243 reloc->addend = fixp->fx_offset = reloc->address;
21244 }
21245#endif
6c43fab6 21246
c19d1205 21247 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6c43fab6 21248
c19d1205
ZW
21249 if (reloc->howto == NULL)
21250 {
21251 as_bad_where (fixp->fx_file, fixp->fx_line,
21252 _("cannot represent %s relocation in this object file format"),
21253 bfd_get_reloc_code_name (code));
21254 return NULL;
21255 }
6c43fab6 21256
c19d1205
ZW
21257 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21258 vtable entry to be used in the relocation's section offset. */
21259 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
21260 reloc->address = fixp->fx_offset;
6c43fab6 21261
c19d1205 21262 return reloc;
6c43fab6
RE
21263}
21264
c19d1205 21265/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6c43fab6 21266
c19d1205
ZW
21267void
21268cons_fix_new_arm (fragS * frag,
21269 int where,
21270 int size,
21271 expressionS * exp)
6c43fab6 21272{
c19d1205
ZW
21273 bfd_reloc_code_real_type type;
21274 int pcrel = 0;
6c43fab6 21275
c19d1205
ZW
21276 /* Pick a reloc.
21277 FIXME: @@ Should look at CPU word size. */
21278 switch (size)
21279 {
21280 case 1:
21281 type = BFD_RELOC_8;
21282 break;
21283 case 2:
21284 type = BFD_RELOC_16;
21285 break;
21286 case 4:
21287 default:
21288 type = BFD_RELOC_32;
21289 break;
21290 case 8:
21291 type = BFD_RELOC_64;
21292 break;
21293 }
6c43fab6 21294
f0927246
NC
21295#ifdef TE_PE
21296 if (exp->X_op == O_secrel)
21297 {
21298 exp->X_op = O_symbol;
21299 type = BFD_RELOC_32_SECREL;
21300 }
21301#endif
21302
c19d1205
ZW
21303 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
21304}
6c43fab6 21305
4343666d 21306#if defined (OBJ_COFF)
c19d1205
ZW
21307void
21308arm_validate_fix (fixS * fixP)
6c43fab6 21309{
c19d1205
ZW
21310 /* If the destination of the branch is a defined symbol which does not have
21311 the THUMB_FUNC attribute, then we must be calling a function which has
21312 the (interfacearm) attribute. We look for the Thumb entry point to that
21313 function and change the branch to refer to that function instead. */
21314 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
21315 && fixP->fx_addsy != NULL
21316 && S_IS_DEFINED (fixP->fx_addsy)
21317 && ! THUMB_IS_FUNC (fixP->fx_addsy))
6c43fab6 21318 {
c19d1205 21319 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
6c43fab6 21320 }
c19d1205
ZW
21321}
21322#endif
6c43fab6 21323
267bf995 21324
c19d1205
ZW
21325int
21326arm_force_relocation (struct fix * fixp)
21327{
21328#if defined (OBJ_COFF) && defined (TE_PE)
21329 if (fixp->fx_r_type == BFD_RELOC_RVA)
21330 return 1;
21331#endif
6c43fab6 21332
267bf995
RR
21333 /* In case we have a call or a branch to a function in ARM ISA mode from
21334 a thumb function or vice-versa force the relocation. These relocations
21335 are cleared off for some cores that might have blx and simple transformations
21336 are possible. */
21337
21338#ifdef OBJ_ELF
21339 switch (fixp->fx_r_type)
21340 {
21341 case BFD_RELOC_ARM_PCREL_JUMP:
21342 case BFD_RELOC_ARM_PCREL_CALL:
21343 case BFD_RELOC_THUMB_PCREL_BLX:
21344 if (THUMB_IS_FUNC (fixp->fx_addsy))
21345 return 1;
21346 break;
21347
21348 case BFD_RELOC_ARM_PCREL_BLX:
21349 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21350 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21351 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21352 if (ARM_IS_FUNC (fixp->fx_addsy))
21353 return 1;
21354 break;
21355
21356 default:
21357 break;
21358 }
21359#endif
21360
c19d1205
ZW
21361 /* Resolve these relocations even if the symbol is extern or weak. */
21362 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
21363 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
0110f2b8 21364 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
16805f35 21365 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
0110f2b8
PB
21366 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
21367 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
21368 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12)
c19d1205 21369 return 0;
a737bd4d 21370
4962c51a
MS
21371 /* Always leave these relocations for the linker. */
21372 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
21373 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
21374 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
21375 return 1;
21376
f0291e4c
PB
21377 /* Always generate relocations against function symbols. */
21378 if (fixp->fx_r_type == BFD_RELOC_32
21379 && fixp->fx_addsy
21380 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
21381 return 1;
21382
c19d1205 21383 return generic_force_reloc (fixp);
404ff6b5
AH
21384}
21385
0ffdc86c 21386#if defined (OBJ_ELF) || defined (OBJ_COFF)
e28387c3
PB
21387/* Relocations against function names must be left unadjusted,
21388 so that the linker can use this information to generate interworking
21389 stubs. The MIPS version of this function
c19d1205
ZW
21390 also prevents relocations that are mips-16 specific, but I do not
21391 know why it does this.
404ff6b5 21392
c19d1205
ZW
21393 FIXME:
21394 There is one other problem that ought to be addressed here, but
21395 which currently is not: Taking the address of a label (rather
21396 than a function) and then later jumping to that address. Such
21397 addresses also ought to have their bottom bit set (assuming that
21398 they reside in Thumb code), but at the moment they will not. */
404ff6b5 21399
c19d1205
ZW
21400bfd_boolean
21401arm_fix_adjustable (fixS * fixP)
404ff6b5 21402{
c19d1205
ZW
21403 if (fixP->fx_addsy == NULL)
21404 return 1;
404ff6b5 21405
e28387c3
PB
21406 /* Preserve relocations against symbols with function type. */
21407 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
c921be7d 21408 return FALSE;
e28387c3 21409
c19d1205
ZW
21410 if (THUMB_IS_FUNC (fixP->fx_addsy)
21411 && fixP->fx_subsy == NULL)
c921be7d 21412 return FALSE;
a737bd4d 21413
c19d1205
ZW
21414 /* We need the symbol name for the VTABLE entries. */
21415 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
21416 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
c921be7d 21417 return FALSE;
404ff6b5 21418
c19d1205
ZW
21419 /* Don't allow symbols to be discarded on GOT related relocs. */
21420 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
21421 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
21422 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
21423 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
21424 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
21425 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
21426 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
21427 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
21428 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
c921be7d 21429 return FALSE;
a737bd4d 21430
4962c51a
MS
21431 /* Similarly for group relocations. */
21432 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
21433 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
21434 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
c921be7d 21435 return FALSE;
4962c51a 21436
79947c54
CD
21437 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21438 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
21439 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
21440 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
21441 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
21442 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
21443 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
21444 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
21445 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
c921be7d 21446 return FALSE;
79947c54 21447
c921be7d 21448 return TRUE;
a737bd4d 21449}
0ffdc86c
NC
21450#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21451
21452#ifdef OBJ_ELF
404ff6b5 21453
c19d1205
ZW
21454const char *
21455elf32_arm_target_format (void)
404ff6b5 21456{
c19d1205
ZW
21457#ifdef TE_SYMBIAN
21458 return (target_big_endian
21459 ? "elf32-bigarm-symbian"
21460 : "elf32-littlearm-symbian");
21461#elif defined (TE_VXWORKS)
21462 return (target_big_endian
21463 ? "elf32-bigarm-vxworks"
21464 : "elf32-littlearm-vxworks");
21465#else
21466 if (target_big_endian)
21467 return "elf32-bigarm";
21468 else
21469 return "elf32-littlearm";
21470#endif
404ff6b5
AH
21471}
21472
c19d1205
ZW
21473void
21474armelf_frob_symbol (symbolS * symp,
21475 int * puntp)
404ff6b5 21476{
c19d1205
ZW
21477 elf_frob_symbol (symp, puntp);
21478}
21479#endif
404ff6b5 21480
c19d1205 21481/* MD interface: Finalization. */
a737bd4d 21482
c19d1205
ZW
21483void
21484arm_cleanup (void)
21485{
21486 literal_pool * pool;
a737bd4d 21487
e07e6e58
NC
21488 /* Ensure that all the IT blocks are properly closed. */
21489 check_it_blocks_finished ();
21490
c19d1205
ZW
21491 for (pool = list_of_pools; pool; pool = pool->next)
21492 {
5f4273c7 21493 /* Put it at the end of the relevant section. */
c19d1205
ZW
21494 subseg_set (pool->section, pool->sub_section);
21495#ifdef OBJ_ELF
21496 arm_elf_change_section ();
21497#endif
21498 s_ltorg (0);
21499 }
404ff6b5
AH
21500}
21501
cd000bff
DJ
21502#ifdef OBJ_ELF
21503/* Remove any excess mapping symbols generated for alignment frags in
21504 SEC. We may have created a mapping symbol before a zero byte
21505 alignment; remove it if there's a mapping symbol after the
21506 alignment. */
21507static void
21508check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
21509 void *dummy ATTRIBUTE_UNUSED)
21510{
21511 segment_info_type *seginfo = seg_info (sec);
21512 fragS *fragp;
21513
21514 if (seginfo == NULL || seginfo->frchainP == NULL)
21515 return;
21516
21517 for (fragp = seginfo->frchainP->frch_root;
21518 fragp != NULL;
21519 fragp = fragp->fr_next)
21520 {
21521 symbolS *sym = fragp->tc_frag_data.last_map;
21522 fragS *next = fragp->fr_next;
21523
21524 /* Variable-sized frags have been converted to fixed size by
21525 this point. But if this was variable-sized to start with,
21526 there will be a fixed-size frag after it. So don't handle
21527 next == NULL. */
21528 if (sym == NULL || next == NULL)
21529 continue;
21530
21531 if (S_GET_VALUE (sym) < next->fr_address)
21532 /* Not at the end of this frag. */
21533 continue;
21534 know (S_GET_VALUE (sym) == next->fr_address);
21535
21536 do
21537 {
21538 if (next->tc_frag_data.first_map != NULL)
21539 {
21540 /* Next frag starts with a mapping symbol. Discard this
21541 one. */
21542 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
21543 break;
21544 }
21545
21546 if (next->fr_next == NULL)
21547 {
21548 /* This mapping symbol is at the end of the section. Discard
21549 it. */
21550 know (next->fr_fix == 0 && next->fr_var == 0);
21551 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
21552 break;
21553 }
21554
21555 /* As long as we have empty frags without any mapping symbols,
21556 keep looking. */
21557 /* If the next frag is non-empty and does not start with a
21558 mapping symbol, then this mapping symbol is required. */
21559 if (next->fr_address != next->fr_next->fr_address)
21560 break;
21561
21562 next = next->fr_next;
21563 }
21564 while (next != NULL);
21565 }
21566}
21567#endif
21568
c19d1205
ZW
21569/* Adjust the symbol table. This marks Thumb symbols as distinct from
21570 ARM ones. */
404ff6b5 21571
c19d1205
ZW
21572void
21573arm_adjust_symtab (void)
404ff6b5 21574{
c19d1205
ZW
21575#ifdef OBJ_COFF
21576 symbolS * sym;
404ff6b5 21577
c19d1205
ZW
21578 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
21579 {
21580 if (ARM_IS_THUMB (sym))
21581 {
21582 if (THUMB_IS_FUNC (sym))
21583 {
21584 /* Mark the symbol as a Thumb function. */
21585 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
21586 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
21587 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
404ff6b5 21588
c19d1205
ZW
21589 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
21590 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
21591 else
21592 as_bad (_("%s: unexpected function type: %d"),
21593 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
21594 }
21595 else switch (S_GET_STORAGE_CLASS (sym))
21596 {
21597 case C_EXT:
21598 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
21599 break;
21600 case C_STAT:
21601 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
21602 break;
21603 case C_LABEL:
21604 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
21605 break;
21606 default:
21607 /* Do nothing. */
21608 break;
21609 }
21610 }
a737bd4d 21611
c19d1205
ZW
21612 if (ARM_IS_INTERWORK (sym))
21613 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
404ff6b5 21614 }
c19d1205
ZW
21615#endif
21616#ifdef OBJ_ELF
21617 symbolS * sym;
21618 char bind;
404ff6b5 21619
c19d1205 21620 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
404ff6b5 21621 {
c19d1205
ZW
21622 if (ARM_IS_THUMB (sym))
21623 {
21624 elf_symbol_type * elf_sym;
404ff6b5 21625
c19d1205
ZW
21626 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
21627 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
404ff6b5 21628
b0796911
PB
21629 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
21630 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
c19d1205
ZW
21631 {
21632 /* If it's a .thumb_func, declare it as so,
21633 otherwise tag label as .code 16. */
21634 if (THUMB_IS_FUNC (sym))
21635 elf_sym->internal_elf_sym.st_info =
21636 ELF_ST_INFO (bind, STT_ARM_TFUNC);
3ba67470 21637 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
c19d1205
ZW
21638 elf_sym->internal_elf_sym.st_info =
21639 ELF_ST_INFO (bind, STT_ARM_16BIT);
21640 }
21641 }
21642 }
cd000bff
DJ
21643
21644 /* Remove any overlapping mapping symbols generated by alignment frags. */
21645 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
c19d1205 21646#endif
404ff6b5
AH
21647}
21648
c19d1205 21649/* MD interface: Initialization. */
404ff6b5 21650
a737bd4d 21651static void
c19d1205 21652set_constant_flonums (void)
a737bd4d 21653{
c19d1205 21654 int i;
404ff6b5 21655
c19d1205
ZW
21656 for (i = 0; i < NUM_FLOAT_VALS; i++)
21657 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
21658 abort ();
a737bd4d 21659}
404ff6b5 21660
3e9e4fcf
JB
21661/* Auto-select Thumb mode if it's the only available instruction set for the
21662 given architecture. */
21663
21664static void
21665autoselect_thumb_from_cpu_variant (void)
21666{
21667 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
21668 opcode_select (16);
21669}
21670
c19d1205
ZW
21671void
21672md_begin (void)
a737bd4d 21673{
c19d1205
ZW
21674 unsigned mach;
21675 unsigned int i;
404ff6b5 21676
c19d1205
ZW
21677 if ( (arm_ops_hsh = hash_new ()) == NULL
21678 || (arm_cond_hsh = hash_new ()) == NULL
21679 || (arm_shift_hsh = hash_new ()) == NULL
21680 || (arm_psr_hsh = hash_new ()) == NULL
62b3e311 21681 || (arm_v7m_psr_hsh = hash_new ()) == NULL
c19d1205 21682 || (arm_reg_hsh = hash_new ()) == NULL
62b3e311
PB
21683 || (arm_reloc_hsh = hash_new ()) == NULL
21684 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
c19d1205
ZW
21685 as_fatal (_("virtual memory exhausted"));
21686
21687 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
d3ce72d0 21688 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
c19d1205 21689 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
d3ce72d0 21690 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
c19d1205 21691 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
5a49b8ac 21692 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
c19d1205 21693 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
d3ce72d0 21694 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
62b3e311 21695 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
d3ce72d0
NC
21696 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
21697 (void *) (v7m_psrs + i));
c19d1205 21698 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
5a49b8ac 21699 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
62b3e311
PB
21700 for (i = 0;
21701 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
21702 i++)
d3ce72d0 21703 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
5a49b8ac 21704 (void *) (barrier_opt_names + i));
c19d1205
ZW
21705#ifdef OBJ_ELF
21706 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
5a49b8ac 21707 hash_insert (arm_reloc_hsh, reloc_names[i].name, (void *) (reloc_names + i));
c19d1205
ZW
21708#endif
21709
21710 set_constant_flonums ();
404ff6b5 21711
c19d1205
ZW
21712 /* Set the cpu variant based on the command-line options. We prefer
21713 -mcpu= over -march= if both are set (as for GCC); and we prefer
21714 -mfpu= over any other way of setting the floating point unit.
21715 Use of legacy options with new options are faulted. */
e74cfd16 21716 if (legacy_cpu)
404ff6b5 21717 {
e74cfd16 21718 if (mcpu_cpu_opt || march_cpu_opt)
c19d1205
ZW
21719 as_bad (_("use of old and new-style options to set CPU type"));
21720
21721 mcpu_cpu_opt = legacy_cpu;
404ff6b5 21722 }
e74cfd16 21723 else if (!mcpu_cpu_opt)
c19d1205 21724 mcpu_cpu_opt = march_cpu_opt;
404ff6b5 21725
e74cfd16 21726 if (legacy_fpu)
c19d1205 21727 {
e74cfd16 21728 if (mfpu_opt)
c19d1205 21729 as_bad (_("use of old and new-style options to set FPU type"));
03b1477f
RE
21730
21731 mfpu_opt = legacy_fpu;
21732 }
e74cfd16 21733 else if (!mfpu_opt)
03b1477f 21734 {
45eb4c1b
NS
21735#if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21736 || defined (TE_NetBSD) || defined (TE_VXWORKS))
39c2da32
RE
21737 /* Some environments specify a default FPU. If they don't, infer it
21738 from the processor. */
e74cfd16 21739 if (mcpu_fpu_opt)
03b1477f
RE
21740 mfpu_opt = mcpu_fpu_opt;
21741 else
21742 mfpu_opt = march_fpu_opt;
39c2da32 21743#else
e74cfd16 21744 mfpu_opt = &fpu_default;
39c2da32 21745#endif
03b1477f
RE
21746 }
21747
e74cfd16 21748 if (!mfpu_opt)
03b1477f 21749 {
493cb6ef 21750 if (mcpu_cpu_opt != NULL)
e74cfd16 21751 mfpu_opt = &fpu_default;
493cb6ef 21752 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
e74cfd16 21753 mfpu_opt = &fpu_arch_vfp_v2;
03b1477f 21754 else
e74cfd16 21755 mfpu_opt = &fpu_arch_fpa;
03b1477f
RE
21756 }
21757
ee065d83 21758#ifdef CPU_DEFAULT
e74cfd16 21759 if (!mcpu_cpu_opt)
ee065d83 21760 {
e74cfd16
PB
21761 mcpu_cpu_opt = &cpu_default;
21762 selected_cpu = cpu_default;
ee065d83 21763 }
e74cfd16
PB
21764#else
21765 if (mcpu_cpu_opt)
21766 selected_cpu = *mcpu_cpu_opt;
ee065d83 21767 else
e74cfd16 21768 mcpu_cpu_opt = &arm_arch_any;
ee065d83 21769#endif
03b1477f 21770
e74cfd16 21771 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
03b1477f 21772
3e9e4fcf
JB
21773 autoselect_thumb_from_cpu_variant ();
21774
e74cfd16 21775 arm_arch_used = thumb_arch_used = arm_arch_none;
ee065d83 21776
f17c130b 21777#if defined OBJ_COFF || defined OBJ_ELF
b99bd4ef 21778 {
7cc69913
NC
21779 unsigned int flags = 0;
21780
21781#if defined OBJ_ELF
21782 flags = meabi_flags;
d507cf36
PB
21783
21784 switch (meabi_flags)
33a392fb 21785 {
d507cf36 21786 case EF_ARM_EABI_UNKNOWN:
7cc69913 21787#endif
d507cf36
PB
21788 /* Set the flags in the private structure. */
21789 if (uses_apcs_26) flags |= F_APCS26;
21790 if (support_interwork) flags |= F_INTERWORK;
21791 if (uses_apcs_float) flags |= F_APCS_FLOAT;
c19d1205 21792 if (pic_code) flags |= F_PIC;
e74cfd16 21793 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
7cc69913
NC
21794 flags |= F_SOFT_FLOAT;
21795
d507cf36
PB
21796 switch (mfloat_abi_opt)
21797 {
21798 case ARM_FLOAT_ABI_SOFT:
21799 case ARM_FLOAT_ABI_SOFTFP:
21800 flags |= F_SOFT_FLOAT;
21801 break;
33a392fb 21802
d507cf36
PB
21803 case ARM_FLOAT_ABI_HARD:
21804 if (flags & F_SOFT_FLOAT)
21805 as_bad (_("hard-float conflicts with specified fpu"));
21806 break;
21807 }
03b1477f 21808
e74cfd16
PB
21809 /* Using pure-endian doubles (even if soft-float). */
21810 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
7cc69913 21811 flags |= F_VFP_FLOAT;
f17c130b 21812
fde78edd 21813#if defined OBJ_ELF
e74cfd16 21814 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
d507cf36 21815 flags |= EF_ARM_MAVERICK_FLOAT;
d507cf36
PB
21816 break;
21817
8cb51566 21818 case EF_ARM_EABI_VER4:
3a4a14e9 21819 case EF_ARM_EABI_VER5:
c19d1205 21820 /* No additional flags to set. */
d507cf36
PB
21821 break;
21822
21823 default:
21824 abort ();
21825 }
7cc69913 21826#endif
b99bd4ef
NC
21827 bfd_set_private_flags (stdoutput, flags);
21828
21829 /* We have run out flags in the COFF header to encode the
21830 status of ATPCS support, so instead we create a dummy,
c19d1205 21831 empty, debug section called .arm.atpcs. */
b99bd4ef
NC
21832 if (atpcs)
21833 {
21834 asection * sec;
21835
21836 sec = bfd_make_section (stdoutput, ".arm.atpcs");
21837
21838 if (sec != NULL)
21839 {
21840 bfd_set_section_flags
21841 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
21842 bfd_set_section_size (stdoutput, sec, 0);
21843 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
21844 }
21845 }
7cc69913 21846 }
f17c130b 21847#endif
b99bd4ef
NC
21848
21849 /* Record the CPU type as well. */
2d447fca
JM
21850 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
21851 mach = bfd_mach_arm_iWMMXt2;
21852 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
e16bb312 21853 mach = bfd_mach_arm_iWMMXt;
e74cfd16 21854 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
b99bd4ef 21855 mach = bfd_mach_arm_XScale;
e74cfd16 21856 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
fde78edd 21857 mach = bfd_mach_arm_ep9312;
e74cfd16 21858 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
b99bd4ef 21859 mach = bfd_mach_arm_5TE;
e74cfd16 21860 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
b99bd4ef 21861 {
e74cfd16 21862 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
b99bd4ef
NC
21863 mach = bfd_mach_arm_5T;
21864 else
21865 mach = bfd_mach_arm_5;
21866 }
e74cfd16 21867 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
b99bd4ef 21868 {
e74cfd16 21869 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
b99bd4ef
NC
21870 mach = bfd_mach_arm_4T;
21871 else
21872 mach = bfd_mach_arm_4;
21873 }
e74cfd16 21874 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
b99bd4ef 21875 mach = bfd_mach_arm_3M;
e74cfd16
PB
21876 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
21877 mach = bfd_mach_arm_3;
21878 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
21879 mach = bfd_mach_arm_2a;
21880 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
21881 mach = bfd_mach_arm_2;
21882 else
21883 mach = bfd_mach_arm_unknown;
b99bd4ef
NC
21884
21885 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
21886}
21887
c19d1205 21888/* Command line processing. */
b99bd4ef 21889
c19d1205
ZW
21890/* md_parse_option
21891 Invocation line includes a switch not recognized by the base assembler.
21892 See if it's a processor-specific option.
b99bd4ef 21893
c19d1205
ZW
21894 This routine is somewhat complicated by the need for backwards
21895 compatibility (since older releases of gcc can't be changed).
21896 The new options try to make the interface as compatible as
21897 possible with GCC.
b99bd4ef 21898
c19d1205 21899 New options (supported) are:
b99bd4ef 21900
c19d1205
ZW
21901 -mcpu=<cpu name> Assemble for selected processor
21902 -march=<architecture name> Assemble for selected architecture
21903 -mfpu=<fpu architecture> Assemble for selected FPU.
21904 -EB/-mbig-endian Big-endian
21905 -EL/-mlittle-endian Little-endian
21906 -k Generate PIC code
21907 -mthumb Start in Thumb mode
21908 -mthumb-interwork Code supports ARM/Thumb interworking
b99bd4ef 21909
278df34e 21910 -m[no-]warn-deprecated Warn about deprecated features
267bf995 21911
c19d1205 21912 For now we will also provide support for:
b99bd4ef 21913
c19d1205
ZW
21914 -mapcs-32 32-bit Program counter
21915 -mapcs-26 26-bit Program counter
21916 -macps-float Floats passed in FP registers
21917 -mapcs-reentrant Reentrant code
21918 -matpcs
21919 (sometime these will probably be replaced with -mapcs=<list of options>
21920 and -matpcs=<list of options>)
b99bd4ef 21921
c19d1205
ZW
21922 The remaining options are only supported for back-wards compatibility.
21923 Cpu variants, the arm part is optional:
21924 -m[arm]1 Currently not supported.
21925 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
21926 -m[arm]3 Arm 3 processor
21927 -m[arm]6[xx], Arm 6 processors
21928 -m[arm]7[xx][t][[d]m] Arm 7 processors
21929 -m[arm]8[10] Arm 8 processors
21930 -m[arm]9[20][tdmi] Arm 9 processors
21931 -mstrongarm[110[0]] StrongARM processors
21932 -mxscale XScale processors
21933 -m[arm]v[2345[t[e]]] Arm architectures
21934 -mall All (except the ARM1)
21935 FP variants:
21936 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
21937 -mfpe-old (No float load/store multiples)
21938 -mvfpxd VFP Single precision
21939 -mvfp All VFP
21940 -mno-fpu Disable all floating point instructions
b99bd4ef 21941
c19d1205
ZW
21942 The following CPU names are recognized:
21943 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
21944 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
21945 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
21946 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
21947 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
21948 arm10t arm10e, arm1020t, arm1020e, arm10200e,
21949 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
b99bd4ef 21950
c19d1205 21951 */
b99bd4ef 21952
c19d1205 21953const char * md_shortopts = "m:k";
b99bd4ef 21954
c19d1205
ZW
21955#ifdef ARM_BI_ENDIAN
21956#define OPTION_EB (OPTION_MD_BASE + 0)
21957#define OPTION_EL (OPTION_MD_BASE + 1)
b99bd4ef 21958#else
c19d1205
ZW
21959#if TARGET_BYTES_BIG_ENDIAN
21960#define OPTION_EB (OPTION_MD_BASE + 0)
b99bd4ef 21961#else
c19d1205
ZW
21962#define OPTION_EL (OPTION_MD_BASE + 1)
21963#endif
b99bd4ef 21964#endif
845b51d6 21965#define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
b99bd4ef 21966
c19d1205 21967struct option md_longopts[] =
b99bd4ef 21968{
c19d1205
ZW
21969#ifdef OPTION_EB
21970 {"EB", no_argument, NULL, OPTION_EB},
21971#endif
21972#ifdef OPTION_EL
21973 {"EL", no_argument, NULL, OPTION_EL},
b99bd4ef 21974#endif
845b51d6 21975 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
c19d1205
ZW
21976 {NULL, no_argument, NULL, 0}
21977};
b99bd4ef 21978
c19d1205 21979size_t md_longopts_size = sizeof (md_longopts);
b99bd4ef 21980
c19d1205 21981struct arm_option_table
b99bd4ef 21982{
c19d1205
ZW
21983 char *option; /* Option name to match. */
21984 char *help; /* Help information. */
21985 int *var; /* Variable to change. */
21986 int value; /* What to change it to. */
21987 char *deprecated; /* If non-null, print this message. */
21988};
b99bd4ef 21989
c19d1205
ZW
21990struct arm_option_table arm_opts[] =
21991{
21992 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
21993 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
21994 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
21995 &support_interwork, 1, NULL},
21996 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
21997 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
21998 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
21999 1, NULL},
22000 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
22001 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
22002 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
22003 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
22004 NULL},
b99bd4ef 22005
c19d1205
ZW
22006 /* These are recognized by the assembler, but have no affect on code. */
22007 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
22008 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
278df34e
NS
22009
22010 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
22011 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22012 &warn_on_deprecated, 0, NULL},
e74cfd16
PB
22013 {NULL, NULL, NULL, 0, NULL}
22014};
22015
22016struct arm_legacy_option_table
22017{
22018 char *option; /* Option name to match. */
22019 const arm_feature_set **var; /* Variable to change. */
22020 const arm_feature_set value; /* What to change it to. */
22021 char *deprecated; /* If non-null, print this message. */
22022};
b99bd4ef 22023
e74cfd16
PB
22024const struct arm_legacy_option_table arm_legacy_opts[] =
22025{
c19d1205
ZW
22026 /* DON'T add any new processors to this list -- we want the whole list
22027 to go away... Add them to the processors table instead. */
e74cfd16
PB
22028 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22029 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22030 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22031 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22032 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22033 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22034 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22035 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22036 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22037 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22038 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22039 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22040 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22041 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22042 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22043 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22044 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22045 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22046 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22047 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22048 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22049 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22050 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22051 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22052 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22053 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22054 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22055 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22056 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22057 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22058 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22059 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22060 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22061 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22062 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22063 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22064 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22065 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22066 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22067 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22068 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22069 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22070 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22071 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22072 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22073 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22074 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22075 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22076 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22077 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22078 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22079 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22080 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22081 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22082 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22083 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22084 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22085 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22086 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22087 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22088 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22089 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22090 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22091 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22092 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22093 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22094 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22095 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22096 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
22097 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
c19d1205 22098 N_("use -mcpu=strongarm110")},
e74cfd16 22099 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
c19d1205 22100 N_("use -mcpu=strongarm1100")},
e74cfd16 22101 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
c19d1205 22102 N_("use -mcpu=strongarm1110")},
e74cfd16
PB
22103 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
22104 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
22105 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
7ed4c4c5 22106
c19d1205 22107 /* Architecture variants -- don't add any more to this list either. */
e74cfd16
PB
22108 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22109 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22110 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22111 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22112 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22113 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22114 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22115 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22116 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22117 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22118 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22119 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22120 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22121 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22122 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22123 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22124 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22125 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
7ed4c4c5 22126
c19d1205 22127 /* Floating point variants -- don't add any more to this list either. */
e74cfd16
PB
22128 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
22129 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
22130 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
22131 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
c19d1205 22132 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
7ed4c4c5 22133
e74cfd16 22134 {NULL, NULL, ARM_ARCH_NONE, NULL}
c19d1205 22135};
7ed4c4c5 22136
c19d1205 22137struct arm_cpu_option_table
7ed4c4c5 22138{
c19d1205 22139 char *name;
e74cfd16 22140 const arm_feature_set value;
c19d1205
ZW
22141 /* For some CPUs we assume an FPU unless the user explicitly sets
22142 -mfpu=... */
e74cfd16 22143 const arm_feature_set default_fpu;
ee065d83
PB
22144 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22145 case. */
22146 const char *canonical_name;
c19d1205 22147};
7ed4c4c5 22148
c19d1205
ZW
22149/* This list should, at a minimum, contain all the cpu names
22150 recognized by GCC. */
e74cfd16 22151static const struct arm_cpu_option_table arm_cpus[] =
c19d1205 22152{
ee065d83
PB
22153 {"all", ARM_ANY, FPU_ARCH_FPA, NULL},
22154 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL},
22155 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL},
22156 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
22157 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
22158 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22159 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22160 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22161 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22162 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22163 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22164 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22165 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22166 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22167 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22168 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22169 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22170 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22171 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22172 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22173 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22174 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22175 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22176 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22177 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22178 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22179 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22180 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22181 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22182 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22183 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22184 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22185 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22186 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22187 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22188 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22189 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22190 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22191 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22192 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"},
22193 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22194 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22195 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22196 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
7fac0536
NC
22197 {"fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22198 {"fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
c19d1205
ZW
22199 /* For V5 or later processors we default to using VFP; but the user
22200 should really set the FPU type explicitly. */
ee065d83
PB
22201 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22202 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22203 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
22204 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
22205 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
22206 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22207 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"},
22208 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22209 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22210 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"},
22211 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22212 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22213 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22214 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22215 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22216 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"},
22217 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22218 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22219 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22220 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
22221 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
7fac0536
NC
22222 {"fa626te", ARM_ARCH_V5TE, FPU_NONE, NULL},
22223 {"fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
ee065d83
PB
22224 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"},
22225 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL},
22226 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"},
22227 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL},
22228 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL},
22229 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL},
22230 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL},
22231 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
22232 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
22233 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
b38f9f31 22234 {"cortex-a5", ARM_ARCH_V7A, FPU_NONE, NULL},
e07e6e58 22235 {"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE (0, FPU_VFP_V3
5287ad62 22236 | FPU_NEON_EXT_V1),
15290f0a 22237 NULL},
e07e6e58 22238 {"cortex-a9", ARM_ARCH_V7A, ARM_FEATURE (0, FPU_VFP_V3
15290f0a 22239 | FPU_NEON_EXT_V1),
5287ad62 22240 NULL},
62b3e311 22241 {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL},
307c948d 22242 {"cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16, NULL},
26b6f191 22243 {"cortex-m4", ARM_ARCH_V7EM, FPU_NONE, NULL},
62b3e311 22244 {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL},
7e806470 22245 {"cortex-m1", ARM_ARCH_V6M, FPU_NONE, NULL},
5b19eaba 22246 {"cortex-m0", ARM_ARCH_V6M, FPU_NONE, NULL},
c19d1205 22247 /* ??? XSCALE is really an architecture. */
ee065d83 22248 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
c19d1205 22249 /* ??? iwmmxt is not a processor. */
ee065d83 22250 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
2d447fca 22251 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL},
ee065d83 22252 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
c19d1205 22253 /* Maverick */
e07e6e58 22254 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
e74cfd16 22255 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL}
c19d1205 22256};
7ed4c4c5 22257
c19d1205 22258struct arm_arch_option_table
7ed4c4c5 22259{
c19d1205 22260 char *name;
e74cfd16
PB
22261 const arm_feature_set value;
22262 const arm_feature_set default_fpu;
c19d1205 22263};
7ed4c4c5 22264
c19d1205
ZW
22265/* This list should, at a minimum, contain all the architecture names
22266 recognized by GCC. */
e74cfd16 22267static const struct arm_arch_option_table arm_archs[] =
c19d1205
ZW
22268{
22269 {"all", ARM_ANY, FPU_ARCH_FPA},
22270 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
22271 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
22272 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
22273 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
22274 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
22275 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
22276 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
22277 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
22278 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
22279 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
22280 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
22281 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
22282 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
22283 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
22284 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
22285 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
22286 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
22287 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
22288 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
22289 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
22290 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
22291 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
22292 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
22293 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
22294 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
7e806470 22295 {"armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP},
62b3e311 22296 {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP},
c450d570
PB
22297 /* The official spelling of the ARMv7 profile variants is the dashed form.
22298 Accept the non-dashed form for compatibility with old toolchains. */
62b3e311
PB
22299 {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP},
22300 {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP},
22301 {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP},
c450d570
PB
22302 {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP},
22303 {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP},
22304 {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP},
9e3c6df6 22305 {"armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP},
c19d1205
ZW
22306 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
22307 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
2d447fca 22308 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP},
e74cfd16 22309 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
c19d1205 22310};
7ed4c4c5 22311
c19d1205 22312/* ISA extensions in the co-processor space. */
e74cfd16 22313struct arm_option_cpu_value_table
c19d1205
ZW
22314{
22315 char *name;
e74cfd16 22316 const arm_feature_set value;
c19d1205 22317};
7ed4c4c5 22318
e74cfd16 22319static const struct arm_option_cpu_value_table arm_extensions[] =
c19d1205 22320{
e74cfd16
PB
22321 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)},
22322 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)},
22323 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)},
2d447fca 22324 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2)},
e74cfd16 22325 {NULL, ARM_ARCH_NONE}
c19d1205 22326};
7ed4c4c5 22327
c19d1205
ZW
22328/* This list should, at a minimum, contain all the fpu names
22329 recognized by GCC. */
e74cfd16 22330static const struct arm_option_cpu_value_table arm_fpus[] =
c19d1205
ZW
22331{
22332 {"softfpa", FPU_NONE},
22333 {"fpe", FPU_ARCH_FPE},
22334 {"fpe2", FPU_ARCH_FPE},
22335 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
22336 {"fpa", FPU_ARCH_FPA},
22337 {"fpa10", FPU_ARCH_FPA},
22338 {"fpa11", FPU_ARCH_FPA},
22339 {"arm7500fe", FPU_ARCH_FPA},
22340 {"softvfp", FPU_ARCH_VFP},
22341 {"softvfp+vfp", FPU_ARCH_VFP_V2},
22342 {"vfp", FPU_ARCH_VFP_V2},
22343 {"vfp9", FPU_ARCH_VFP_V2},
b1cc4aeb 22344 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
c19d1205
ZW
22345 {"vfp10", FPU_ARCH_VFP_V2},
22346 {"vfp10-r0", FPU_ARCH_VFP_V1},
22347 {"vfpxd", FPU_ARCH_VFP_V1xD},
b1cc4aeb
PB
22348 {"vfpv2", FPU_ARCH_VFP_V2},
22349 {"vfpv3", FPU_ARCH_VFP_V3},
62f3b8c8 22350 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
b1cc4aeb 22351 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
62f3b8c8
PB
22352 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
22353 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
22354 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
c19d1205
ZW
22355 {"arm1020t", FPU_ARCH_VFP_V1},
22356 {"arm1020e", FPU_ARCH_VFP_V2},
22357 {"arm1136jfs", FPU_ARCH_VFP_V2},
22358 {"arm1136jf-s", FPU_ARCH_VFP_V2},
22359 {"maverick", FPU_ARCH_MAVERICK},
5287ad62 22360 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
8e79c3df 22361 {"neon-fp16", FPU_ARCH_NEON_FP16},
62f3b8c8
PB
22362 {"vfpv4", FPU_ARCH_VFP_V4},
22363 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
ada65aa3 22364 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
62f3b8c8 22365 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
e74cfd16
PB
22366 {NULL, ARM_ARCH_NONE}
22367};
22368
22369struct arm_option_value_table
22370{
22371 char *name;
22372 long value;
c19d1205 22373};
7ed4c4c5 22374
e74cfd16 22375static const struct arm_option_value_table arm_float_abis[] =
c19d1205
ZW
22376{
22377 {"hard", ARM_FLOAT_ABI_HARD},
22378 {"softfp", ARM_FLOAT_ABI_SOFTFP},
22379 {"soft", ARM_FLOAT_ABI_SOFT},
e74cfd16 22380 {NULL, 0}
c19d1205 22381};
7ed4c4c5 22382
c19d1205 22383#ifdef OBJ_ELF
3a4a14e9 22384/* We only know how to output GNU and ver 4/5 (AAELF) formats. */
e74cfd16 22385static const struct arm_option_value_table arm_eabis[] =
c19d1205
ZW
22386{
22387 {"gnu", EF_ARM_EABI_UNKNOWN},
22388 {"4", EF_ARM_EABI_VER4},
3a4a14e9 22389 {"5", EF_ARM_EABI_VER5},
e74cfd16 22390 {NULL, 0}
c19d1205
ZW
22391};
22392#endif
7ed4c4c5 22393
c19d1205
ZW
22394struct arm_long_option_table
22395{
22396 char * option; /* Substring to match. */
22397 char * help; /* Help information. */
22398 int (* func) (char * subopt); /* Function to decode sub-option. */
22399 char * deprecated; /* If non-null, print this message. */
22400};
7ed4c4c5 22401
c921be7d 22402static bfd_boolean
e74cfd16 22403arm_parse_extension (char * str, const arm_feature_set **opt_p)
7ed4c4c5 22404{
21d799b5
NC
22405 arm_feature_set *ext_set = (arm_feature_set *)
22406 xmalloc (sizeof (arm_feature_set));
e74cfd16
PB
22407
22408 /* Copy the feature set, so that we can modify it. */
22409 *ext_set = **opt_p;
22410 *opt_p = ext_set;
22411
c19d1205 22412 while (str != NULL && *str != 0)
7ed4c4c5 22413 {
e74cfd16 22414 const struct arm_option_cpu_value_table * opt;
c19d1205
ZW
22415 char * ext;
22416 int optlen;
7ed4c4c5 22417
c19d1205
ZW
22418 if (*str != '+')
22419 {
22420 as_bad (_("invalid architectural extension"));
c921be7d 22421 return FALSE;
c19d1205 22422 }
7ed4c4c5 22423
c19d1205
ZW
22424 str++;
22425 ext = strchr (str, '+');
7ed4c4c5 22426
c19d1205
ZW
22427 if (ext != NULL)
22428 optlen = ext - str;
22429 else
22430 optlen = strlen (str);
7ed4c4c5 22431
c19d1205
ZW
22432 if (optlen == 0)
22433 {
22434 as_bad (_("missing architectural extension"));
c921be7d 22435 return FALSE;
c19d1205 22436 }
7ed4c4c5 22437
c19d1205
ZW
22438 for (opt = arm_extensions; opt->name != NULL; opt++)
22439 if (strncmp (opt->name, str, optlen) == 0)
22440 {
e74cfd16 22441 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
c19d1205
ZW
22442 break;
22443 }
7ed4c4c5 22444
c19d1205
ZW
22445 if (opt->name == NULL)
22446 {
5f4273c7 22447 as_bad (_("unknown architectural extension `%s'"), str);
c921be7d 22448 return FALSE;
c19d1205 22449 }
7ed4c4c5 22450
c19d1205
ZW
22451 str = ext;
22452 };
7ed4c4c5 22453
c921be7d 22454 return TRUE;
c19d1205 22455}
7ed4c4c5 22456
c921be7d 22457static bfd_boolean
c19d1205 22458arm_parse_cpu (char * str)
7ed4c4c5 22459{
e74cfd16 22460 const struct arm_cpu_option_table * opt;
c19d1205
ZW
22461 char * ext = strchr (str, '+');
22462 int optlen;
7ed4c4c5 22463
c19d1205
ZW
22464 if (ext != NULL)
22465 optlen = ext - str;
7ed4c4c5 22466 else
c19d1205 22467 optlen = strlen (str);
7ed4c4c5 22468
c19d1205 22469 if (optlen == 0)
7ed4c4c5 22470 {
c19d1205 22471 as_bad (_("missing cpu name `%s'"), str);
c921be7d 22472 return FALSE;
7ed4c4c5
NC
22473 }
22474
c19d1205
ZW
22475 for (opt = arm_cpus; opt->name != NULL; opt++)
22476 if (strncmp (opt->name, str, optlen) == 0)
22477 {
e74cfd16
PB
22478 mcpu_cpu_opt = &opt->value;
22479 mcpu_fpu_opt = &opt->default_fpu;
ee065d83 22480 if (opt->canonical_name)
5f4273c7 22481 strcpy (selected_cpu_name, opt->canonical_name);
ee065d83
PB
22482 else
22483 {
22484 int i;
c921be7d 22485
ee065d83
PB
22486 for (i = 0; i < optlen; i++)
22487 selected_cpu_name[i] = TOUPPER (opt->name[i]);
22488 selected_cpu_name[i] = 0;
22489 }
7ed4c4c5 22490
c19d1205
ZW
22491 if (ext != NULL)
22492 return arm_parse_extension (ext, &mcpu_cpu_opt);
7ed4c4c5 22493
c921be7d 22494 return TRUE;
c19d1205 22495 }
7ed4c4c5 22496
c19d1205 22497 as_bad (_("unknown cpu `%s'"), str);
c921be7d 22498 return FALSE;
7ed4c4c5
NC
22499}
22500
c921be7d 22501static bfd_boolean
c19d1205 22502arm_parse_arch (char * str)
7ed4c4c5 22503{
e74cfd16 22504 const struct arm_arch_option_table *opt;
c19d1205
ZW
22505 char *ext = strchr (str, '+');
22506 int optlen;
7ed4c4c5 22507
c19d1205
ZW
22508 if (ext != NULL)
22509 optlen = ext - str;
7ed4c4c5 22510 else
c19d1205 22511 optlen = strlen (str);
7ed4c4c5 22512
c19d1205 22513 if (optlen == 0)
7ed4c4c5 22514 {
c19d1205 22515 as_bad (_("missing architecture name `%s'"), str);
c921be7d 22516 return FALSE;
7ed4c4c5
NC
22517 }
22518
c19d1205
ZW
22519 for (opt = arm_archs; opt->name != NULL; opt++)
22520 if (streq (opt->name, str))
22521 {
e74cfd16
PB
22522 march_cpu_opt = &opt->value;
22523 march_fpu_opt = &opt->default_fpu;
5f4273c7 22524 strcpy (selected_cpu_name, opt->name);
7ed4c4c5 22525
c19d1205
ZW
22526 if (ext != NULL)
22527 return arm_parse_extension (ext, &march_cpu_opt);
7ed4c4c5 22528
c921be7d 22529 return TRUE;
c19d1205
ZW
22530 }
22531
22532 as_bad (_("unknown architecture `%s'\n"), str);
c921be7d 22533 return FALSE;
7ed4c4c5 22534}
eb043451 22535
c921be7d 22536static bfd_boolean
c19d1205
ZW
22537arm_parse_fpu (char * str)
22538{
e74cfd16 22539 const struct arm_option_cpu_value_table * opt;
b99bd4ef 22540
c19d1205
ZW
22541 for (opt = arm_fpus; opt->name != NULL; opt++)
22542 if (streq (opt->name, str))
22543 {
e74cfd16 22544 mfpu_opt = &opt->value;
c921be7d 22545 return TRUE;
c19d1205 22546 }
b99bd4ef 22547
c19d1205 22548 as_bad (_("unknown floating point format `%s'\n"), str);
c921be7d 22549 return FALSE;
c19d1205
ZW
22550}
22551
c921be7d 22552static bfd_boolean
c19d1205 22553arm_parse_float_abi (char * str)
b99bd4ef 22554{
e74cfd16 22555 const struct arm_option_value_table * opt;
b99bd4ef 22556
c19d1205
ZW
22557 for (opt = arm_float_abis; opt->name != NULL; opt++)
22558 if (streq (opt->name, str))
22559 {
22560 mfloat_abi_opt = opt->value;
c921be7d 22561 return TRUE;
c19d1205 22562 }
cc8a6dd0 22563
c19d1205 22564 as_bad (_("unknown floating point abi `%s'\n"), str);
c921be7d 22565 return FALSE;
c19d1205 22566}
b99bd4ef 22567
c19d1205 22568#ifdef OBJ_ELF
c921be7d 22569static bfd_boolean
c19d1205
ZW
22570arm_parse_eabi (char * str)
22571{
e74cfd16 22572 const struct arm_option_value_table *opt;
cc8a6dd0 22573
c19d1205
ZW
22574 for (opt = arm_eabis; opt->name != NULL; opt++)
22575 if (streq (opt->name, str))
22576 {
22577 meabi_flags = opt->value;
c921be7d 22578 return TRUE;
c19d1205
ZW
22579 }
22580 as_bad (_("unknown EABI `%s'\n"), str);
c921be7d 22581 return FALSE;
c19d1205
ZW
22582}
22583#endif
cc8a6dd0 22584
c921be7d 22585static bfd_boolean
e07e6e58
NC
22586arm_parse_it_mode (char * str)
22587{
c921be7d 22588 bfd_boolean ret = TRUE;
e07e6e58
NC
22589
22590 if (streq ("arm", str))
22591 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
22592 else if (streq ("thumb", str))
22593 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
22594 else if (streq ("always", str))
22595 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
22596 else if (streq ("never", str))
22597 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
22598 else
22599 {
22600 as_bad (_("unknown implicit IT mode `%s', should be "\
22601 "arm, thumb, always, or never."), str);
c921be7d 22602 ret = FALSE;
e07e6e58
NC
22603 }
22604
22605 return ret;
22606}
22607
c19d1205
ZW
22608struct arm_long_option_table arm_long_opts[] =
22609{
22610 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22611 arm_parse_cpu, NULL},
22612 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22613 arm_parse_arch, NULL},
22614 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22615 arm_parse_fpu, NULL},
22616 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22617 arm_parse_float_abi, NULL},
22618#ifdef OBJ_ELF
7fac0536 22619 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
c19d1205
ZW
22620 arm_parse_eabi, NULL},
22621#endif
e07e6e58
NC
22622 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22623 arm_parse_it_mode, NULL},
c19d1205
ZW
22624 {NULL, NULL, 0, NULL}
22625};
cc8a6dd0 22626
c19d1205
ZW
22627int
22628md_parse_option (int c, char * arg)
22629{
22630 struct arm_option_table *opt;
e74cfd16 22631 const struct arm_legacy_option_table *fopt;
c19d1205 22632 struct arm_long_option_table *lopt;
b99bd4ef 22633
c19d1205 22634 switch (c)
b99bd4ef 22635 {
c19d1205
ZW
22636#ifdef OPTION_EB
22637 case OPTION_EB:
22638 target_big_endian = 1;
22639 break;
22640#endif
cc8a6dd0 22641
c19d1205
ZW
22642#ifdef OPTION_EL
22643 case OPTION_EL:
22644 target_big_endian = 0;
22645 break;
22646#endif
b99bd4ef 22647
845b51d6
PB
22648 case OPTION_FIX_V4BX:
22649 fix_v4bx = TRUE;
22650 break;
22651
c19d1205
ZW
22652 case 'a':
22653 /* Listing option. Just ignore these, we don't support additional
22654 ones. */
22655 return 0;
b99bd4ef 22656
c19d1205
ZW
22657 default:
22658 for (opt = arm_opts; opt->option != NULL; opt++)
22659 {
22660 if (c == opt->option[0]
22661 && ((arg == NULL && opt->option[1] == 0)
22662 || streq (arg, opt->option + 1)))
22663 {
c19d1205 22664 /* If the option is deprecated, tell the user. */
278df34e 22665 if (warn_on_deprecated && opt->deprecated != NULL)
c19d1205
ZW
22666 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
22667 arg ? arg : "", _(opt->deprecated));
b99bd4ef 22668
c19d1205
ZW
22669 if (opt->var != NULL)
22670 *opt->var = opt->value;
cc8a6dd0 22671
c19d1205
ZW
22672 return 1;
22673 }
22674 }
b99bd4ef 22675
e74cfd16
PB
22676 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
22677 {
22678 if (c == fopt->option[0]
22679 && ((arg == NULL && fopt->option[1] == 0)
22680 || streq (arg, fopt->option + 1)))
22681 {
e74cfd16 22682 /* If the option is deprecated, tell the user. */
278df34e 22683 if (warn_on_deprecated && fopt->deprecated != NULL)
e74cfd16
PB
22684 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
22685 arg ? arg : "", _(fopt->deprecated));
e74cfd16
PB
22686
22687 if (fopt->var != NULL)
22688 *fopt->var = &fopt->value;
22689
22690 return 1;
22691 }
22692 }
22693
c19d1205
ZW
22694 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
22695 {
22696 /* These options are expected to have an argument. */
22697 if (c == lopt->option[0]
22698 && arg != NULL
22699 && strncmp (arg, lopt->option + 1,
22700 strlen (lopt->option + 1)) == 0)
22701 {
c19d1205 22702 /* If the option is deprecated, tell the user. */
278df34e 22703 if (warn_on_deprecated && lopt->deprecated != NULL)
c19d1205
ZW
22704 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
22705 _(lopt->deprecated));
b99bd4ef 22706
c19d1205
ZW
22707 /* Call the sup-option parser. */
22708 return lopt->func (arg + strlen (lopt->option) - 1);
22709 }
22710 }
a737bd4d 22711
c19d1205
ZW
22712 return 0;
22713 }
a394c00f 22714
c19d1205
ZW
22715 return 1;
22716}
a394c00f 22717
c19d1205
ZW
22718void
22719md_show_usage (FILE * fp)
a394c00f 22720{
c19d1205
ZW
22721 struct arm_option_table *opt;
22722 struct arm_long_option_table *lopt;
a394c00f 22723
c19d1205 22724 fprintf (fp, _(" ARM-specific assembler options:\n"));
a394c00f 22725
c19d1205
ZW
22726 for (opt = arm_opts; opt->option != NULL; opt++)
22727 if (opt->help != NULL)
22728 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
a394c00f 22729
c19d1205
ZW
22730 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
22731 if (lopt->help != NULL)
22732 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
a394c00f 22733
c19d1205
ZW
22734#ifdef OPTION_EB
22735 fprintf (fp, _("\
22736 -EB assemble code for a big-endian cpu\n"));
a394c00f
NC
22737#endif
22738
c19d1205
ZW
22739#ifdef OPTION_EL
22740 fprintf (fp, _("\
22741 -EL assemble code for a little-endian cpu\n"));
a737bd4d 22742#endif
845b51d6
PB
22743
22744 fprintf (fp, _("\
22745 --fix-v4bx Allow BX in ARMv4 code\n"));
c19d1205 22746}
ee065d83
PB
22747
22748
22749#ifdef OBJ_ELF
62b3e311
PB
22750typedef struct
22751{
22752 int val;
22753 arm_feature_set flags;
22754} cpu_arch_ver_table;
22755
22756/* Mapping from CPU features to EABI CPU arch values. Table must be sorted
22757 least features first. */
22758static const cpu_arch_ver_table cpu_arch_ver[] =
22759{
22760 {1, ARM_ARCH_V4},
22761 {2, ARM_ARCH_V4T},
22762 {3, ARM_ARCH_V5},
ee3c0378 22763 {3, ARM_ARCH_V5T},
62b3e311
PB
22764 {4, ARM_ARCH_V5TE},
22765 {5, ARM_ARCH_V5TEJ},
22766 {6, ARM_ARCH_V6},
22767 {7, ARM_ARCH_V6Z},
7e806470 22768 {9, ARM_ARCH_V6K},
91e22acd 22769 {11, ARM_ARCH_V6M},
7e806470 22770 {8, ARM_ARCH_V6T2},
62b3e311
PB
22771 {10, ARM_ARCH_V7A},
22772 {10, ARM_ARCH_V7R},
22773 {10, ARM_ARCH_V7M},
22774 {0, ARM_ARCH_NONE}
22775};
22776
ee3c0378
AS
22777/* Set an attribute if it has not already been set by the user. */
22778static void
22779aeabi_set_attribute_int (int tag, int value)
22780{
22781 if (tag < 1
22782 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
22783 || !attributes_set_explicitly[tag])
22784 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
22785}
22786
22787static void
22788aeabi_set_attribute_string (int tag, const char *value)
22789{
22790 if (tag < 1
22791 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
22792 || !attributes_set_explicitly[tag])
22793 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
22794}
22795
ee065d83
PB
22796/* Set the public EABI object attributes. */
22797static void
22798aeabi_set_public_attributes (void)
22799{
22800 int arch;
e74cfd16 22801 arm_feature_set flags;
62b3e311
PB
22802 arm_feature_set tmp;
22803 const cpu_arch_ver_table *p;
ee065d83
PB
22804
22805 /* Choose the architecture based on the capabilities of the requested cpu
22806 (if any) and/or the instructions actually used. */
e74cfd16
PB
22807 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
22808 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
22809 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
7a1d4c38
PB
22810 /*Allow the user to override the reported architecture. */
22811 if (object_arch)
22812 {
22813 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
22814 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
22815 }
22816
62b3e311
PB
22817 tmp = flags;
22818 arch = 0;
22819 for (p = cpu_arch_ver; p->val; p++)
22820 {
22821 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
22822 {
22823 arch = p->val;
22824 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
22825 }
22826 }
ee065d83 22827
9e3c6df6
PB
22828 /* The table lookup above finds the last architecture to contribute
22829 a new feature. Unfortunately, Tag13 is a subset of the union of
22830 v6T2 and v7-M, so it is never seen as contributing a new feature.
22831 We can not search for the last entry which is entirely used,
22832 because if no CPU is specified we build up only those flags
22833 actually used. Perhaps we should separate out the specified
22834 and implicit cases. Avoid taking this path for -march=all by
22835 checking for contradictory v7-A / v7-M features. */
22836 if (arch == 10
22837 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
22838 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
22839 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
22840 arch = 13;
22841
ee065d83
PB
22842 /* Tag_CPU_name. */
22843 if (selected_cpu_name[0])
22844 {
91d6fa6a 22845 char *q;
ee065d83 22846
91d6fa6a
NC
22847 q = selected_cpu_name;
22848 if (strncmp (q, "armv", 4) == 0)
ee065d83
PB
22849 {
22850 int i;
5f4273c7 22851
91d6fa6a
NC
22852 q += 4;
22853 for (i = 0; q[i]; i++)
22854 q[i] = TOUPPER (q[i]);
ee065d83 22855 }
91d6fa6a 22856 aeabi_set_attribute_string (Tag_CPU_name, q);
ee065d83 22857 }
62f3b8c8 22858
ee065d83 22859 /* Tag_CPU_arch. */
ee3c0378 22860 aeabi_set_attribute_int (Tag_CPU_arch, arch);
62f3b8c8 22861
62b3e311
PB
22862 /* Tag_CPU_arch_profile. */
22863 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
ee3c0378 22864 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'A');
62b3e311 22865 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
ee3c0378 22866 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'R');
7e806470 22867 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
ee3c0378 22868 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'M');
62f3b8c8 22869
ee065d83 22870 /* Tag_ARM_ISA_use. */
ee3c0378
AS
22871 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
22872 || arch == 0)
22873 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
62f3b8c8 22874
ee065d83 22875 /* Tag_THUMB_ISA_use. */
ee3c0378
AS
22876 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
22877 || arch == 0)
22878 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
22879 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
62f3b8c8 22880
ee065d83 22881 /* Tag_VFP_arch. */
62f3b8c8
PB
22882 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
22883 aeabi_set_attribute_int (Tag_VFP_arch,
22884 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
22885 ? 5 : 6);
22886 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
ee3c0378 22887 aeabi_set_attribute_int (Tag_VFP_arch, 3);
ada65aa3 22888 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
ee3c0378
AS
22889 aeabi_set_attribute_int (Tag_VFP_arch, 4);
22890 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
22891 aeabi_set_attribute_int (Tag_VFP_arch, 2);
22892 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
22893 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
22894 aeabi_set_attribute_int (Tag_VFP_arch, 1);
62f3b8c8 22895
4547cb56
NC
22896 /* Tag_ABI_HardFP_use. */
22897 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
22898 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
22899 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
22900
ee065d83 22901 /* Tag_WMMX_arch. */
ee3c0378
AS
22902 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
22903 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
22904 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
22905 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
62f3b8c8 22906
ee3c0378 22907 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
8e79c3df 22908 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
62f3b8c8
PB
22909 aeabi_set_attribute_int
22910 (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)
22911 ? 2 : 1));
22912
ee3c0378 22913 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
62f3b8c8 22914 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16))
ee3c0378 22915 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
4547cb56
NC
22916
22917 /* Tag_DIV_use. */
22918 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div))
22919 aeabi_set_attribute_int (Tag_DIV_use, 0);
22920 /* Fill this in when gas supports v7a sdiv/udiv.
22921 else if (... v7a with div extension used ...)
22922 aeabi_set_attribute_int (Tag_DIV_use, 2); */
22923 else
22924 aeabi_set_attribute_int (Tag_DIV_use, 1);
ee065d83
PB
22925}
22926
104d59d1 22927/* Add the default contents for the .ARM.attributes section. */
ee065d83
PB
22928void
22929arm_md_end (void)
22930{
ee065d83
PB
22931 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
22932 return;
22933
22934 aeabi_set_public_attributes ();
ee065d83 22935}
8463be01 22936#endif /* OBJ_ELF */
ee065d83
PB
22937
22938
22939/* Parse a .cpu directive. */
22940
22941static void
22942s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
22943{
e74cfd16 22944 const struct arm_cpu_option_table *opt;
ee065d83
PB
22945 char *name;
22946 char saved_char;
22947
22948 name = input_line_pointer;
5f4273c7 22949 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB
22950 input_line_pointer++;
22951 saved_char = *input_line_pointer;
22952 *input_line_pointer = 0;
22953
22954 /* Skip the first "all" entry. */
22955 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
22956 if (streq (opt->name, name))
22957 {
e74cfd16
PB
22958 mcpu_cpu_opt = &opt->value;
22959 selected_cpu = opt->value;
ee065d83 22960 if (opt->canonical_name)
5f4273c7 22961 strcpy (selected_cpu_name, opt->canonical_name);
ee065d83
PB
22962 else
22963 {
22964 int i;
22965 for (i = 0; opt->name[i]; i++)
22966 selected_cpu_name[i] = TOUPPER (opt->name[i]);
22967 selected_cpu_name[i] = 0;
22968 }
e74cfd16 22969 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
ee065d83
PB
22970 *input_line_pointer = saved_char;
22971 demand_empty_rest_of_line ();
22972 return;
22973 }
22974 as_bad (_("unknown cpu `%s'"), name);
22975 *input_line_pointer = saved_char;
22976 ignore_rest_of_line ();
22977}
22978
22979
22980/* Parse a .arch directive. */
22981
22982static void
22983s_arm_arch (int ignored ATTRIBUTE_UNUSED)
22984{
e74cfd16 22985 const struct arm_arch_option_table *opt;
ee065d83
PB
22986 char saved_char;
22987 char *name;
22988
22989 name = input_line_pointer;
5f4273c7 22990 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB
22991 input_line_pointer++;
22992 saved_char = *input_line_pointer;
22993 *input_line_pointer = 0;
22994
22995 /* Skip the first "all" entry. */
22996 for (opt = arm_archs + 1; opt->name != NULL; opt++)
22997 if (streq (opt->name, name))
22998 {
e74cfd16
PB
22999 mcpu_cpu_opt = &opt->value;
23000 selected_cpu = opt->value;
5f4273c7 23001 strcpy (selected_cpu_name, opt->name);
e74cfd16 23002 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
ee065d83
PB
23003 *input_line_pointer = saved_char;
23004 demand_empty_rest_of_line ();
23005 return;
23006 }
23007
23008 as_bad (_("unknown architecture `%s'\n"), name);
23009 *input_line_pointer = saved_char;
23010 ignore_rest_of_line ();
23011}
23012
23013
7a1d4c38
PB
23014/* Parse a .object_arch directive. */
23015
23016static void
23017s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
23018{
23019 const struct arm_arch_option_table *opt;
23020 char saved_char;
23021 char *name;
23022
23023 name = input_line_pointer;
5f4273c7 23024 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
7a1d4c38
PB
23025 input_line_pointer++;
23026 saved_char = *input_line_pointer;
23027 *input_line_pointer = 0;
23028
23029 /* Skip the first "all" entry. */
23030 for (opt = arm_archs + 1; opt->name != NULL; opt++)
23031 if (streq (opt->name, name))
23032 {
23033 object_arch = &opt->value;
23034 *input_line_pointer = saved_char;
23035 demand_empty_rest_of_line ();
23036 return;
23037 }
23038
23039 as_bad (_("unknown architecture `%s'\n"), name);
23040 *input_line_pointer = saved_char;
23041 ignore_rest_of_line ();
23042}
23043
ee065d83
PB
23044/* Parse a .fpu directive. */
23045
23046static void
23047s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
23048{
e74cfd16 23049 const struct arm_option_cpu_value_table *opt;
ee065d83
PB
23050 char saved_char;
23051 char *name;
23052
23053 name = input_line_pointer;
5f4273c7 23054 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB
23055 input_line_pointer++;
23056 saved_char = *input_line_pointer;
23057 *input_line_pointer = 0;
5f4273c7 23058
ee065d83
PB
23059 for (opt = arm_fpus; opt->name != NULL; opt++)
23060 if (streq (opt->name, name))
23061 {
e74cfd16
PB
23062 mfpu_opt = &opt->value;
23063 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
ee065d83
PB
23064 *input_line_pointer = saved_char;
23065 demand_empty_rest_of_line ();
23066 return;
23067 }
23068
23069 as_bad (_("unknown floating point format `%s'\n"), name);
23070 *input_line_pointer = saved_char;
23071 ignore_rest_of_line ();
23072}
ee065d83 23073
794ba86a 23074/* Copy symbol information. */
f31fef98 23075
794ba86a
DJ
23076void
23077arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
23078{
23079 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
23080}
e04befd0 23081
f31fef98 23082#ifdef OBJ_ELF
e04befd0
AS
23083/* Given a symbolic attribute NAME, return the proper integer value.
23084 Returns -1 if the attribute is not known. */
f31fef98 23085
e04befd0
AS
23086int
23087arm_convert_symbolic_attribute (const char *name)
23088{
f31fef98
NC
23089 static const struct
23090 {
23091 const char * name;
23092 const int tag;
23093 }
23094 attribute_table[] =
23095 {
23096 /* When you modify this table you should
23097 also modify the list in doc/c-arm.texi. */
e04befd0 23098#define T(tag) {#tag, tag}
f31fef98
NC
23099 T (Tag_CPU_raw_name),
23100 T (Tag_CPU_name),
23101 T (Tag_CPU_arch),
23102 T (Tag_CPU_arch_profile),
23103 T (Tag_ARM_ISA_use),
23104 T (Tag_THUMB_ISA_use),
75375b3e 23105 T (Tag_FP_arch),
f31fef98
NC
23106 T (Tag_VFP_arch),
23107 T (Tag_WMMX_arch),
23108 T (Tag_Advanced_SIMD_arch),
23109 T (Tag_PCS_config),
23110 T (Tag_ABI_PCS_R9_use),
23111 T (Tag_ABI_PCS_RW_data),
23112 T (Tag_ABI_PCS_RO_data),
23113 T (Tag_ABI_PCS_GOT_use),
23114 T (Tag_ABI_PCS_wchar_t),
23115 T (Tag_ABI_FP_rounding),
23116 T (Tag_ABI_FP_denormal),
23117 T (Tag_ABI_FP_exceptions),
23118 T (Tag_ABI_FP_user_exceptions),
23119 T (Tag_ABI_FP_number_model),
75375b3e 23120 T (Tag_ABI_align_needed),
f31fef98 23121 T (Tag_ABI_align8_needed),
75375b3e 23122 T (Tag_ABI_align_preserved),
f31fef98
NC
23123 T (Tag_ABI_align8_preserved),
23124 T (Tag_ABI_enum_size),
23125 T (Tag_ABI_HardFP_use),
23126 T (Tag_ABI_VFP_args),
23127 T (Tag_ABI_WMMX_args),
23128 T (Tag_ABI_optimization_goals),
23129 T (Tag_ABI_FP_optimization_goals),
23130 T (Tag_compatibility),
23131 T (Tag_CPU_unaligned_access),
75375b3e 23132 T (Tag_FP_HP_extension),
f31fef98
NC
23133 T (Tag_VFP_HP_extension),
23134 T (Tag_ABI_FP_16bit_format),
cd21e546
MGD
23135 T (Tag_MPextension_use),
23136 T (Tag_DIV_use),
f31fef98
NC
23137 T (Tag_nodefaults),
23138 T (Tag_also_compatible_with),
23139 T (Tag_conformance),
23140 T (Tag_T2EE_use),
23141 T (Tag_Virtualization_use),
cd21e546 23142 /* We deliberately do not include Tag_MPextension_use_legacy. */
e04befd0 23143#undef T
f31fef98 23144 };
e04befd0
AS
23145 unsigned int i;
23146
23147 if (name == NULL)
23148 return -1;
23149
f31fef98 23150 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
c921be7d 23151 if (streq (name, attribute_table[i].name))
e04befd0
AS
23152 return attribute_table[i].tag;
23153
23154 return -1;
23155}
267bf995
RR
23156
23157
23158/* Apply sym value for relocations only in the case that
23159 they are for local symbols and you have the respective
23160 architectural feature for blx and simple switches. */
23161int
23162arm_apply_sym_value (struct fix * fixP)
23163{
23164 if (fixP->fx_addsy
23165 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
23166 && !S_IS_EXTERNAL (fixP->fx_addsy))
23167 {
23168 switch (fixP->fx_r_type)
23169 {
23170 case BFD_RELOC_ARM_PCREL_BLX:
23171 case BFD_RELOC_THUMB_PCREL_BRANCH23:
23172 if (ARM_IS_FUNC (fixP->fx_addsy))
23173 return 1;
23174 break;
23175
23176 case BFD_RELOC_ARM_PCREL_CALL:
23177 case BFD_RELOC_THUMB_PCREL_BLX:
23178 if (THUMB_IS_FUNC (fixP->fx_addsy))
23179 return 1;
23180 break;
23181
23182 default:
23183 break;
23184 }
23185
23186 }
23187 return 0;
23188}
f31fef98 23189#endif /* OBJ_ELF */
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