Commit | Line | Data |
---|---|---|
b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
f17c130b | 2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, |
b43420e6 | 3 | 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
b99bd4ef NC |
4 | Free Software Foundation, Inc. |
5 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) | |
6 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 7 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
8 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
9 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
10 | |
11 | This file is part of GAS, the GNU Assembler. | |
12 | ||
13 | GAS is free software; you can redistribute it and/or modify | |
14 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 15 | the Free Software Foundation; either version 3, or (at your option) |
b99bd4ef NC |
16 | any later version. |
17 | ||
18 | GAS is distributed in the hope that it will be useful, | |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
21 | GNU General Public License for more details. |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
24 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
25 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
26 | 02110-1301, USA. */ | |
b99bd4ef | 27 | |
42a68e18 | 28 | #include "as.h" |
5287ad62 | 29 | #include <limits.h> |
037e8744 | 30 | #include <stdarg.h> |
c19d1205 | 31 | #define NO_RELOC 0 |
3882b010 | 32 | #include "safe-ctype.h" |
b99bd4ef NC |
33 | #include "subsegs.h" |
34 | #include "obstack.h" | |
b99bd4ef | 35 | |
f263249b RE |
36 | #include "opcode/arm.h" |
37 | ||
b99bd4ef NC |
38 | #ifdef OBJ_ELF |
39 | #include "elf/arm.h" | |
a394c00f | 40 | #include "dw2gencfi.h" |
b99bd4ef NC |
41 | #endif |
42 | ||
f0927246 NC |
43 | #include "dwarf2dbg.h" |
44 | ||
7ed4c4c5 NC |
45 | #ifdef OBJ_ELF |
46 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
47 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
48 | ||
49 | /* This structure holds the unwinding state. */ | |
50 | ||
51 | static struct | |
52 | { | |
c19d1205 ZW |
53 | symbolS * proc_start; |
54 | symbolS * table_entry; | |
55 | symbolS * personality_routine; | |
56 | int personality_index; | |
7ed4c4c5 | 57 | /* The segment containing the function. */ |
c19d1205 ZW |
58 | segT saved_seg; |
59 | subsegT saved_subseg; | |
7ed4c4c5 NC |
60 | /* Opcodes generated from this function. */ |
61 | unsigned char * opcodes; | |
c19d1205 ZW |
62 | int opcode_count; |
63 | int opcode_alloc; | |
7ed4c4c5 | 64 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 65 | offsetT frame_size; |
7ed4c4c5 NC |
66 | /* We don't add stack adjustment opcodes immediately so that we can merge |
67 | multiple adjustments. We can also omit the final adjustment | |
68 | when using a frame pointer. */ | |
c19d1205 | 69 | offsetT pending_offset; |
7ed4c4c5 | 70 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
71 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
72 | offsetT fp_offset; | |
73 | int fp_reg; | |
7ed4c4c5 | 74 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 75 | unsigned fp_used:1; |
7ed4c4c5 | 76 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 77 | unsigned sp_restored:1; |
7ed4c4c5 NC |
78 | } unwind; |
79 | ||
8b1ad454 NC |
80 | #endif /* OBJ_ELF */ |
81 | ||
4962c51a MS |
82 | /* Results from operand parsing worker functions. */ |
83 | ||
84 | typedef enum | |
85 | { | |
86 | PARSE_OPERAND_SUCCESS, | |
87 | PARSE_OPERAND_FAIL, | |
88 | PARSE_OPERAND_FAIL_NO_BACKTRACK | |
89 | } parse_operand_result; | |
90 | ||
33a392fb PB |
91 | enum arm_float_abi |
92 | { | |
93 | ARM_FLOAT_ABI_HARD, | |
94 | ARM_FLOAT_ABI_SOFTFP, | |
95 | ARM_FLOAT_ABI_SOFT | |
96 | }; | |
97 | ||
c19d1205 | 98 | /* Types of processor to assemble for. */ |
b99bd4ef | 99 | #ifndef CPU_DEFAULT |
8a59fff3 MGD |
100 | /* The code that was here used to select a default CPU depending on compiler |
101 | pre-defines which were only present when doing native builds, thus | |
102 | changing gas' default behaviour depending upon the build host. | |
103 | ||
104 | If you have a target that requires a default CPU option then the you | |
105 | should define CPU_DEFAULT here. */ | |
b99bd4ef NC |
106 | #endif |
107 | ||
108 | #ifndef FPU_DEFAULT | |
c820d418 MM |
109 | # ifdef TE_LINUX |
110 | # define FPU_DEFAULT FPU_ARCH_FPA | |
111 | # elif defined (TE_NetBSD) | |
112 | # ifdef OBJ_ELF | |
113 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
114 | # else | |
115 | /* Legacy a.out format. */ | |
116 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
117 | # endif | |
4e7fd91e PB |
118 | # elif defined (TE_VXWORKS) |
119 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
120 | # else |
121 | /* For backwards compatibility, default to FPA. */ | |
122 | # define FPU_DEFAULT FPU_ARCH_FPA | |
123 | # endif | |
124 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 125 | |
c19d1205 | 126 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 127 | |
e74cfd16 PB |
128 | static arm_feature_set cpu_variant; |
129 | static arm_feature_set arm_arch_used; | |
130 | static arm_feature_set thumb_arch_used; | |
b99bd4ef | 131 | |
b99bd4ef | 132 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
133 | static int uses_apcs_26 = FALSE; |
134 | static int atpcs = FALSE; | |
b34976b6 AM |
135 | static int support_interwork = FALSE; |
136 | static int uses_apcs_float = FALSE; | |
c19d1205 | 137 | static int pic_code = FALSE; |
845b51d6 | 138 | static int fix_v4bx = FALSE; |
278df34e NS |
139 | /* Warn on using deprecated features. */ |
140 | static int warn_on_deprecated = TRUE; | |
141 | ||
03b1477f RE |
142 | |
143 | /* Variables that we set while parsing command-line options. Once all | |
144 | options have been read we re-process these values to set the real | |
145 | assembly flags. */ | |
e74cfd16 PB |
146 | static const arm_feature_set *legacy_cpu = NULL; |
147 | static const arm_feature_set *legacy_fpu = NULL; | |
148 | ||
149 | static const arm_feature_set *mcpu_cpu_opt = NULL; | |
150 | static const arm_feature_set *mcpu_fpu_opt = NULL; | |
151 | static const arm_feature_set *march_cpu_opt = NULL; | |
152 | static const arm_feature_set *march_fpu_opt = NULL; | |
153 | static const arm_feature_set *mfpu_opt = NULL; | |
7a1d4c38 | 154 | static const arm_feature_set *object_arch = NULL; |
e74cfd16 PB |
155 | |
156 | /* Constants for known architecture features. */ | |
157 | static const arm_feature_set fpu_default = FPU_DEFAULT; | |
158 | static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; | |
159 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; | |
5287ad62 JB |
160 | static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; |
161 | static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; | |
e74cfd16 PB |
162 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; |
163 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; | |
164 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; | |
165 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; | |
166 | ||
167 | #ifdef CPU_DEFAULT | |
168 | static const arm_feature_set cpu_default = CPU_DEFAULT; | |
169 | #endif | |
170 | ||
171 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); | |
172 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); | |
173 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); | |
174 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); | |
175 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); | |
176 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); | |
177 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); | |
178 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); | |
179 | static const arm_feature_set arm_ext_v4t_5 = | |
180 | ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); | |
181 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); | |
182 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); | |
183 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); | |
184 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); | |
185 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); | |
186 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); | |
187 | static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0); | |
188 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); | |
62b3e311 | 189 | static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); |
9e3c6df6 | 190 | static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0); |
7e806470 PB |
191 | static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0); |
192 | static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0); | |
62b3e311 PB |
193 | static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); |
194 | static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); | |
195 | static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); | |
196 | static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); | |
9e3c6df6 | 197 | static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); |
7e806470 PB |
198 | static const arm_feature_set arm_ext_m = |
199 | ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_V7M, 0); | |
e74cfd16 PB |
200 | |
201 | static const arm_feature_set arm_arch_any = ARM_ANY; | |
202 | static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); | |
203 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; | |
204 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; | |
205 | ||
2d447fca JM |
206 | static const arm_feature_set arm_cext_iwmmxt2 = |
207 | ARM_FEATURE (0, ARM_CEXT_IWMMXT2); | |
e74cfd16 PB |
208 | static const arm_feature_set arm_cext_iwmmxt = |
209 | ARM_FEATURE (0, ARM_CEXT_IWMMXT); | |
210 | static const arm_feature_set arm_cext_xscale = | |
211 | ARM_FEATURE (0, ARM_CEXT_XSCALE); | |
212 | static const arm_feature_set arm_cext_maverick = | |
213 | ARM_FEATURE (0, ARM_CEXT_MAVERICK); | |
214 | static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); | |
215 | static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); | |
216 | static const arm_feature_set fpu_vfp_ext_v1xd = | |
217 | ARM_FEATURE (0, FPU_VFP_EXT_V1xD); | |
218 | static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); | |
219 | static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); | |
62f3b8c8 | 220 | static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD); |
5287ad62 | 221 | static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); |
b1cc4aeb PB |
222 | static const arm_feature_set fpu_vfp_ext_d32 = |
223 | ARM_FEATURE (0, FPU_VFP_EXT_D32); | |
5287ad62 JB |
224 | static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); |
225 | static const arm_feature_set fpu_vfp_v3_or_neon_ext = | |
226 | ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); | |
62f3b8c8 PB |
227 | static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16); |
228 | static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA); | |
229 | static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA); | |
e74cfd16 | 230 | |
33a392fb | 231 | static int mfloat_abi_opt = -1; |
e74cfd16 PB |
232 | /* Record user cpu selection for object attributes. */ |
233 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; | |
ee065d83 PB |
234 | /* Must be long enough to hold any of the names in arm_cpus. */ |
235 | static char selected_cpu_name[16]; | |
7cc69913 | 236 | #ifdef OBJ_ELF |
deeaaff8 DJ |
237 | # ifdef EABI_DEFAULT |
238 | static int meabi_flags = EABI_DEFAULT; | |
239 | # else | |
d507cf36 | 240 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 241 | # endif |
e1da3f5b | 242 | |
ee3c0378 AS |
243 | static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; |
244 | ||
e1da3f5b | 245 | bfd_boolean |
5f4273c7 | 246 | arm_is_eabi (void) |
e1da3f5b PB |
247 | { |
248 | return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); | |
249 | } | |
7cc69913 | 250 | #endif |
b99bd4ef | 251 | |
b99bd4ef | 252 | #ifdef OBJ_ELF |
c19d1205 | 253 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
254 | symbolS * GOT_symbol; |
255 | #endif | |
256 | ||
b99bd4ef NC |
257 | /* 0: assemble for ARM, |
258 | 1: assemble for Thumb, | |
259 | 2: assemble for Thumb even though target CPU does not support thumb | |
260 | instructions. */ | |
261 | static int thumb_mode = 0; | |
8dc2430f NC |
262 | /* A value distinct from the possible values for thumb_mode that we |
263 | can use to record whether thumb_mode has been copied into the | |
264 | tc_frag_data field of a frag. */ | |
265 | #define MODE_RECORDED (1 << 4) | |
b99bd4ef | 266 | |
e07e6e58 NC |
267 | /* Specifies the intrinsic IT insn behavior mode. */ |
268 | enum implicit_it_mode | |
269 | { | |
270 | IMPLICIT_IT_MODE_NEVER = 0x00, | |
271 | IMPLICIT_IT_MODE_ARM = 0x01, | |
272 | IMPLICIT_IT_MODE_THUMB = 0x02, | |
273 | IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB) | |
274 | }; | |
275 | static int implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
276 | ||
c19d1205 ZW |
277 | /* If unified_syntax is true, we are processing the new unified |
278 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
279 | ||
280 | - Immediate operands do not require a # prefix. | |
281 | - Conditional affixes always appear at the end of the | |
282 | instruction. (For backward compatibility, those instructions | |
283 | that formerly had them in the middle, continue to accept them | |
284 | there.) | |
285 | - The IT instruction may appear, and if it does is validated | |
286 | against subsequent conditional affixes. It does not generate | |
287 | machine code. | |
288 | ||
289 | Important differences from the old Thumb mode: | |
290 | ||
291 | - Immediate operands do not require a # prefix. | |
292 | - Most of the V6T2 instructions are only available in unified mode. | |
293 | - The .N and .W suffixes are recognized and honored (it is an error | |
294 | if they cannot be honored). | |
295 | - All instructions set the flags if and only if they have an 's' affix. | |
296 | - Conditional affixes may be used. They are validated against | |
297 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
298 | conditional affix except in the scope of an IT instruction. */ | |
299 | ||
300 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef | 301 | |
5287ad62 JB |
302 | enum neon_el_type |
303 | { | |
dcbf9037 | 304 | NT_invtype, |
5287ad62 JB |
305 | NT_untyped, |
306 | NT_integer, | |
307 | NT_float, | |
308 | NT_poly, | |
309 | NT_signed, | |
dcbf9037 | 310 | NT_unsigned |
5287ad62 JB |
311 | }; |
312 | ||
313 | struct neon_type_el | |
314 | { | |
315 | enum neon_el_type type; | |
316 | unsigned size; | |
317 | }; | |
318 | ||
319 | #define NEON_MAX_TYPE_ELS 4 | |
320 | ||
321 | struct neon_type | |
322 | { | |
323 | struct neon_type_el el[NEON_MAX_TYPE_ELS]; | |
324 | unsigned elems; | |
325 | }; | |
326 | ||
e07e6e58 NC |
327 | enum it_instruction_type |
328 | { | |
329 | OUTSIDE_IT_INSN, | |
330 | INSIDE_IT_INSN, | |
331 | INSIDE_IT_LAST_INSN, | |
332 | IF_INSIDE_IT_LAST_INSN, /* Either outside or inside; | |
333 | if inside, should be the last one. */ | |
334 | NEUTRAL_IT_INSN, /* This could be either inside or outside, | |
335 | i.e. BKPT and NOP. */ | |
336 | IT_INSN /* The IT insn has been parsed. */ | |
337 | }; | |
338 | ||
b99bd4ef NC |
339 | struct arm_it |
340 | { | |
c19d1205 | 341 | const char * error; |
b99bd4ef | 342 | unsigned long instruction; |
c19d1205 ZW |
343 | int size; |
344 | int size_req; | |
345 | int cond; | |
037e8744 JB |
346 | /* "uncond_value" is set to the value in place of the conditional field in |
347 | unconditional versions of the instruction, or -1 if nothing is | |
348 | appropriate. */ | |
349 | int uncond_value; | |
5287ad62 | 350 | struct neon_type vectype; |
88714cb8 DG |
351 | /* This does not indicate an actual NEON instruction, only that |
352 | the mnemonic accepts neon-style type suffixes. */ | |
353 | int is_neon; | |
0110f2b8 PB |
354 | /* Set to the opcode if the instruction needs relaxation. |
355 | Zero if the instruction is not relaxed. */ | |
356 | unsigned long relax; | |
b99bd4ef NC |
357 | struct |
358 | { | |
359 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
360 | expressionS exp; |
361 | int pc_rel; | |
b99bd4ef | 362 | } reloc; |
b99bd4ef | 363 | |
e07e6e58 NC |
364 | enum it_instruction_type it_insn_type; |
365 | ||
c19d1205 ZW |
366 | struct |
367 | { | |
368 | unsigned reg; | |
ca3f61f7 | 369 | signed int imm; |
dcbf9037 | 370 | struct neon_type_el vectype; |
ca3f61f7 NC |
371 | unsigned present : 1; /* Operand present. */ |
372 | unsigned isreg : 1; /* Operand was a register. */ | |
373 | unsigned immisreg : 1; /* .imm field is a second register. */ | |
5287ad62 JB |
374 | unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ |
375 | unsigned immisalign : 1; /* Immediate is an alignment specifier. */ | |
c96612cc | 376 | unsigned immisfloat : 1; /* Immediate was parsed as a float. */ |
5287ad62 JB |
377 | /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV |
378 | instructions. This allows us to disambiguate ARM <-> vector insns. */ | |
379 | unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ | |
037e8744 | 380 | unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ |
5287ad62 | 381 | unsigned isquad : 1; /* Operand is Neon quad-precision register. */ |
037e8744 | 382 | unsigned issingle : 1; /* Operand is VFP single-precision register. */ |
ca3f61f7 NC |
383 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ |
384 | unsigned writeback : 1; /* Operand has trailing ! */ | |
385 | unsigned preind : 1; /* Preindexed address. */ | |
386 | unsigned postind : 1; /* Postindexed address. */ | |
387 | unsigned negative : 1; /* Index register was negated. */ | |
388 | unsigned shifted : 1; /* Shift applied to operation. */ | |
389 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
c19d1205 | 390 | } operands[6]; |
b99bd4ef NC |
391 | }; |
392 | ||
c19d1205 | 393 | static struct arm_it inst; |
b99bd4ef NC |
394 | |
395 | #define NUM_FLOAT_VALS 8 | |
396 | ||
05d2d07e | 397 | const char * fp_const[] = |
b99bd4ef NC |
398 | { |
399 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
400 | }; | |
401 | ||
c19d1205 | 402 | /* Number of littlenums required to hold an extended precision number. */ |
b99bd4ef NC |
403 | #define MAX_LITTLENUMS 6 |
404 | ||
405 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
406 | ||
407 | #define FAIL (-1) | |
408 | #define SUCCESS (0) | |
409 | ||
410 | #define SUFF_S 1 | |
411 | #define SUFF_D 2 | |
412 | #define SUFF_E 3 | |
413 | #define SUFF_P 4 | |
414 | ||
c19d1205 ZW |
415 | #define CP_T_X 0x00008000 |
416 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 417 | |
c19d1205 ZW |
418 | #define CONDS_BIT 0x00100000 |
419 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
420 | |
421 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
422 | ||
423 | struct asm_cond | |
424 | { | |
d3ce72d0 | 425 | const char * template_name; |
c921be7d | 426 | unsigned long value; |
b99bd4ef NC |
427 | }; |
428 | ||
c19d1205 | 429 | #define COND_ALWAYS 0xE |
b99bd4ef | 430 | |
b99bd4ef NC |
431 | struct asm_psr |
432 | { | |
d3ce72d0 | 433 | const char * template_name; |
c921be7d | 434 | unsigned long field; |
b99bd4ef NC |
435 | }; |
436 | ||
62b3e311 PB |
437 | struct asm_barrier_opt |
438 | { | |
d3ce72d0 | 439 | const char * template_name; |
c921be7d | 440 | unsigned long value; |
62b3e311 PB |
441 | }; |
442 | ||
2d2255b5 | 443 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
444 | #define SPSR_BIT (1 << 22) |
445 | ||
c19d1205 ZW |
446 | /* The individual PSR flag bits. */ |
447 | #define PSR_c (1 << 16) | |
448 | #define PSR_x (1 << 17) | |
449 | #define PSR_s (1 << 18) | |
450 | #define PSR_f (1 << 19) | |
b99bd4ef | 451 | |
c19d1205 | 452 | struct reloc_entry |
bfae80f2 | 453 | { |
c921be7d NC |
454 | char * name; |
455 | bfd_reloc_code_real_type reloc; | |
bfae80f2 RE |
456 | }; |
457 | ||
5287ad62 | 458 | enum vfp_reg_pos |
bfae80f2 | 459 | { |
5287ad62 JB |
460 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, |
461 | VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn | |
bfae80f2 RE |
462 | }; |
463 | ||
464 | enum vfp_ldstm_type | |
465 | { | |
466 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
467 | }; | |
468 | ||
dcbf9037 JB |
469 | /* Bits for DEFINED field in neon_typed_alias. */ |
470 | #define NTA_HASTYPE 1 | |
471 | #define NTA_HASINDEX 2 | |
472 | ||
473 | struct neon_typed_alias | |
474 | { | |
c921be7d NC |
475 | unsigned char defined; |
476 | unsigned char index; | |
477 | struct neon_type_el eltype; | |
dcbf9037 JB |
478 | }; |
479 | ||
c19d1205 ZW |
480 | /* ARM register categories. This includes coprocessor numbers and various |
481 | architecture extensions' registers. */ | |
482 | enum arm_reg_type | |
bfae80f2 | 483 | { |
c19d1205 ZW |
484 | REG_TYPE_RN, |
485 | REG_TYPE_CP, | |
486 | REG_TYPE_CN, | |
487 | REG_TYPE_FN, | |
488 | REG_TYPE_VFS, | |
489 | REG_TYPE_VFD, | |
5287ad62 | 490 | REG_TYPE_NQ, |
037e8744 | 491 | REG_TYPE_VFSD, |
5287ad62 | 492 | REG_TYPE_NDQ, |
037e8744 | 493 | REG_TYPE_NSDQ, |
c19d1205 ZW |
494 | REG_TYPE_VFC, |
495 | REG_TYPE_MVF, | |
496 | REG_TYPE_MVD, | |
497 | REG_TYPE_MVFX, | |
498 | REG_TYPE_MVDX, | |
499 | REG_TYPE_MVAX, | |
500 | REG_TYPE_DSPSC, | |
501 | REG_TYPE_MMXWR, | |
502 | REG_TYPE_MMXWC, | |
503 | REG_TYPE_MMXWCG, | |
504 | REG_TYPE_XSCALE, | |
bfae80f2 RE |
505 | }; |
506 | ||
dcbf9037 JB |
507 | /* Structure for a hash table entry for a register. |
508 | If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra | |
509 | information which states whether a vector type or index is specified (for a | |
510 | register alias created with .dn or .qn). Otherwise NEON should be NULL. */ | |
6c43fab6 RE |
511 | struct reg_entry |
512 | { | |
c921be7d NC |
513 | const char * name; |
514 | unsigned char number; | |
515 | unsigned char type; | |
516 | unsigned char builtin; | |
517 | struct neon_typed_alias * neon; | |
6c43fab6 RE |
518 | }; |
519 | ||
c19d1205 | 520 | /* Diagnostics used when we don't get a register of the expected type. */ |
c921be7d | 521 | const char * const reg_expected_msgs[] = |
c19d1205 ZW |
522 | { |
523 | N_("ARM register expected"), | |
524 | N_("bad or missing co-processor number"), | |
525 | N_("co-processor register expected"), | |
526 | N_("FPA register expected"), | |
527 | N_("VFP single precision register expected"), | |
5287ad62 JB |
528 | N_("VFP/Neon double precision register expected"), |
529 | N_("Neon quad precision register expected"), | |
037e8744 | 530 | N_("VFP single or double precision register expected"), |
5287ad62 | 531 | N_("Neon double or quad precision register expected"), |
037e8744 | 532 | N_("VFP single, double or Neon quad precision register expected"), |
c19d1205 ZW |
533 | N_("VFP system register expected"), |
534 | N_("Maverick MVF register expected"), | |
535 | N_("Maverick MVD register expected"), | |
536 | N_("Maverick MVFX register expected"), | |
537 | N_("Maverick MVDX register expected"), | |
538 | N_("Maverick MVAX register expected"), | |
539 | N_("Maverick DSPSC register expected"), | |
540 | N_("iWMMXt data register expected"), | |
541 | N_("iWMMXt control register expected"), | |
542 | N_("iWMMXt scalar register expected"), | |
543 | N_("XScale accumulator register expected"), | |
6c43fab6 RE |
544 | }; |
545 | ||
c19d1205 ZW |
546 | /* Some well known registers that we refer to directly elsewhere. */ |
547 | #define REG_SP 13 | |
548 | #define REG_LR 14 | |
549 | #define REG_PC 15 | |
404ff6b5 | 550 | |
b99bd4ef NC |
551 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
552 | take 2: */ | |
c19d1205 | 553 | #define INSN_SIZE 4 |
b99bd4ef NC |
554 | |
555 | struct asm_opcode | |
556 | { | |
557 | /* Basic string to match. */ | |
d3ce72d0 | 558 | const char * template_name; |
c19d1205 ZW |
559 | |
560 | /* Parameters to instruction. */ | |
5be8be5d | 561 | unsigned int operands[8]; |
c19d1205 ZW |
562 | |
563 | /* Conditional tag - see opcode_lookup. */ | |
564 | unsigned int tag : 4; | |
b99bd4ef NC |
565 | |
566 | /* Basic instruction code. */ | |
c19d1205 | 567 | unsigned int avalue : 28; |
b99bd4ef | 568 | |
c19d1205 ZW |
569 | /* Thumb-format instruction code. */ |
570 | unsigned int tvalue; | |
b99bd4ef | 571 | |
90e4755a | 572 | /* Which architecture variant provides this instruction. */ |
c921be7d NC |
573 | const arm_feature_set * avariant; |
574 | const arm_feature_set * tvariant; | |
c19d1205 ZW |
575 | |
576 | /* Function to call to encode instruction in ARM format. */ | |
577 | void (* aencode) (void); | |
b99bd4ef | 578 | |
c19d1205 ZW |
579 | /* Function to call to encode instruction in Thumb format. */ |
580 | void (* tencode) (void); | |
b99bd4ef NC |
581 | }; |
582 | ||
a737bd4d NC |
583 | /* Defines for various bits that we will want to toggle. */ |
584 | #define INST_IMMEDIATE 0x02000000 | |
585 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 586 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
587 | #define SHIFT_BY_REG 0x00000010 |
588 | #define PRE_INDEX 0x01000000 | |
589 | #define INDEX_UP 0x00800000 | |
590 | #define WRITE_BACK 0x00200000 | |
591 | #define LDM_TYPE_2_OR_3 0x00400000 | |
a028a6f5 | 592 | #define CPSI_MMOD 0x00020000 |
90e4755a | 593 | |
a737bd4d NC |
594 | #define LITERAL_MASK 0xf000f000 |
595 | #define OPCODE_MASK 0xfe1fffff | |
596 | #define V4_STR_BIT 0x00000020 | |
90e4755a | 597 | |
efd81785 PB |
598 | #define T2_SUBS_PC_LR 0xf3de8f00 |
599 | ||
a737bd4d | 600 | #define DATA_OP_SHIFT 21 |
90e4755a | 601 | |
ef8d22e6 PB |
602 | #define T2_OPCODE_MASK 0xfe1fffff |
603 | #define T2_DATA_OP_SHIFT 21 | |
604 | ||
a737bd4d NC |
605 | /* Codes to distinguish the arithmetic instructions. */ |
606 | #define OPCODE_AND 0 | |
607 | #define OPCODE_EOR 1 | |
608 | #define OPCODE_SUB 2 | |
609 | #define OPCODE_RSB 3 | |
610 | #define OPCODE_ADD 4 | |
611 | #define OPCODE_ADC 5 | |
612 | #define OPCODE_SBC 6 | |
613 | #define OPCODE_RSC 7 | |
614 | #define OPCODE_TST 8 | |
615 | #define OPCODE_TEQ 9 | |
616 | #define OPCODE_CMP 10 | |
617 | #define OPCODE_CMN 11 | |
618 | #define OPCODE_ORR 12 | |
619 | #define OPCODE_MOV 13 | |
620 | #define OPCODE_BIC 14 | |
621 | #define OPCODE_MVN 15 | |
90e4755a | 622 | |
ef8d22e6 PB |
623 | #define T2_OPCODE_AND 0 |
624 | #define T2_OPCODE_BIC 1 | |
625 | #define T2_OPCODE_ORR 2 | |
626 | #define T2_OPCODE_ORN 3 | |
627 | #define T2_OPCODE_EOR 4 | |
628 | #define T2_OPCODE_ADD 8 | |
629 | #define T2_OPCODE_ADC 10 | |
630 | #define T2_OPCODE_SBC 11 | |
631 | #define T2_OPCODE_SUB 13 | |
632 | #define T2_OPCODE_RSB 14 | |
633 | ||
a737bd4d NC |
634 | #define T_OPCODE_MUL 0x4340 |
635 | #define T_OPCODE_TST 0x4200 | |
636 | #define T_OPCODE_CMN 0x42c0 | |
637 | #define T_OPCODE_NEG 0x4240 | |
638 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 639 | |
a737bd4d NC |
640 | #define T_OPCODE_ADD_R3 0x1800 |
641 | #define T_OPCODE_SUB_R3 0x1a00 | |
642 | #define T_OPCODE_ADD_HI 0x4400 | |
643 | #define T_OPCODE_ADD_ST 0xb000 | |
644 | #define T_OPCODE_SUB_ST 0xb080 | |
645 | #define T_OPCODE_ADD_SP 0xa800 | |
646 | #define T_OPCODE_ADD_PC 0xa000 | |
647 | #define T_OPCODE_ADD_I8 0x3000 | |
648 | #define T_OPCODE_SUB_I8 0x3800 | |
649 | #define T_OPCODE_ADD_I3 0x1c00 | |
650 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 651 | |
a737bd4d NC |
652 | #define T_OPCODE_ASR_R 0x4100 |
653 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
654 | #define T_OPCODE_LSR_R 0x40c0 |
655 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
656 | #define T_OPCODE_ASR_I 0x1000 |
657 | #define T_OPCODE_LSL_I 0x0000 | |
658 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 659 | |
a737bd4d NC |
660 | #define T_OPCODE_MOV_I8 0x2000 |
661 | #define T_OPCODE_CMP_I8 0x2800 | |
662 | #define T_OPCODE_CMP_LR 0x4280 | |
663 | #define T_OPCODE_MOV_HR 0x4600 | |
664 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 665 | |
a737bd4d NC |
666 | #define T_OPCODE_LDR_PC 0x4800 |
667 | #define T_OPCODE_LDR_SP 0x9800 | |
668 | #define T_OPCODE_STR_SP 0x9000 | |
669 | #define T_OPCODE_LDR_IW 0x6800 | |
670 | #define T_OPCODE_STR_IW 0x6000 | |
671 | #define T_OPCODE_LDR_IH 0x8800 | |
672 | #define T_OPCODE_STR_IH 0x8000 | |
673 | #define T_OPCODE_LDR_IB 0x7800 | |
674 | #define T_OPCODE_STR_IB 0x7000 | |
675 | #define T_OPCODE_LDR_RW 0x5800 | |
676 | #define T_OPCODE_STR_RW 0x5000 | |
677 | #define T_OPCODE_LDR_RH 0x5a00 | |
678 | #define T_OPCODE_STR_RH 0x5200 | |
679 | #define T_OPCODE_LDR_RB 0x5c00 | |
680 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 681 | |
a737bd4d NC |
682 | #define T_OPCODE_PUSH 0xb400 |
683 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 684 | |
2fc8bdac | 685 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 686 | |
a737bd4d | 687 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 688 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 | 689 | #define THUMB_LOAD_BIT 0x0800 |
53365c0d | 690 | #define THUMB2_LOAD_BIT 0x00100000 |
c19d1205 ZW |
691 | |
692 | #define BAD_ARGS _("bad arguments to instruction") | |
fdfde340 | 693 | #define BAD_SP _("r13 not allowed here") |
c19d1205 ZW |
694 | #define BAD_PC _("r15 not allowed here") |
695 | #define BAD_COND _("instruction cannot be conditional") | |
696 | #define BAD_OVERLAP _("registers may not be the same") | |
697 | #define BAD_HIREG _("lo register required") | |
698 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
01cfc07f | 699 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); |
dfa9f0d5 PB |
700 | #define BAD_BRANCH _("branch must be last instruction in IT block") |
701 | #define BAD_NOT_IT _("instruction not allowed in IT block") | |
037e8744 | 702 | #define BAD_FPU _("selected FPU does not support instruction") |
e07e6e58 NC |
703 | #define BAD_OUT_IT _("thumb conditional instruction should be in IT block") |
704 | #define BAD_IT_COND _("incorrect condition in IT block") | |
705 | #define BAD_IT_IT _("IT falling in the range of a previous IT block") | |
921e5f0a | 706 | #define MISSING_FNSTART _("missing .fnstart before unwinding directive") |
5be8be5d DG |
707 | #define BAD_PC_ADDRESSING \ |
708 | _("cannot use register index with PC-relative addressing") | |
709 | #define BAD_PC_WRITEBACK \ | |
710 | _("cannot use writeback with PC-relative addressing") | |
c19d1205 | 711 | |
c921be7d NC |
712 | static struct hash_control * arm_ops_hsh; |
713 | static struct hash_control * arm_cond_hsh; | |
714 | static struct hash_control * arm_shift_hsh; | |
715 | static struct hash_control * arm_psr_hsh; | |
716 | static struct hash_control * arm_v7m_psr_hsh; | |
717 | static struct hash_control * arm_reg_hsh; | |
718 | static struct hash_control * arm_reloc_hsh; | |
719 | static struct hash_control * arm_barrier_opt_hsh; | |
b99bd4ef | 720 | |
b99bd4ef NC |
721 | /* Stuff needed to resolve the label ambiguity |
722 | As: | |
723 | ... | |
724 | label: <insn> | |
725 | may differ from: | |
726 | ... | |
727 | label: | |
5f4273c7 | 728 | <insn> */ |
b99bd4ef NC |
729 | |
730 | symbolS * last_label_seen; | |
b34976b6 | 731 | static int label_is_thumb_function_name = FALSE; |
e07e6e58 | 732 | |
3d0c9500 NC |
733 | /* Literal pool structure. Held on a per-section |
734 | and per-sub-section basis. */ | |
a737bd4d | 735 | |
c19d1205 | 736 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 737 | typedef struct literal_pool |
b99bd4ef | 738 | { |
c921be7d NC |
739 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
740 | unsigned int next_free_entry; | |
741 | unsigned int id; | |
742 | symbolS * symbol; | |
743 | segT section; | |
744 | subsegT sub_section; | |
745 | struct literal_pool * next; | |
3d0c9500 | 746 | } literal_pool; |
b99bd4ef | 747 | |
3d0c9500 NC |
748 | /* Pointer to a linked list of literal pools. */ |
749 | literal_pool * list_of_pools = NULL; | |
e27ec89e | 750 | |
e07e6e58 NC |
751 | #ifdef OBJ_ELF |
752 | # define now_it seg_info (now_seg)->tc_segment_info_data.current_it | |
753 | #else | |
754 | static struct current_it now_it; | |
755 | #endif | |
756 | ||
757 | static inline int | |
758 | now_it_compatible (int cond) | |
759 | { | |
760 | return (cond & ~1) == (now_it.cc & ~1); | |
761 | } | |
762 | ||
763 | static inline int | |
764 | conditional_insn (void) | |
765 | { | |
766 | return inst.cond != COND_ALWAYS; | |
767 | } | |
768 | ||
769 | static int in_it_block (void); | |
770 | ||
771 | static int handle_it_state (void); | |
772 | ||
773 | static void force_automatic_it_block_close (void); | |
774 | ||
c921be7d NC |
775 | static void it_fsm_post_encode (void); |
776 | ||
e07e6e58 NC |
777 | #define set_it_insn_type(type) \ |
778 | do \ | |
779 | { \ | |
780 | inst.it_insn_type = type; \ | |
781 | if (handle_it_state () == FAIL) \ | |
782 | return; \ | |
783 | } \ | |
784 | while (0) | |
785 | ||
c921be7d NC |
786 | #define set_it_insn_type_nonvoid(type, failret) \ |
787 | do \ | |
788 | { \ | |
789 | inst.it_insn_type = type; \ | |
790 | if (handle_it_state () == FAIL) \ | |
791 | return failret; \ | |
792 | } \ | |
793 | while(0) | |
794 | ||
e07e6e58 NC |
795 | #define set_it_insn_type_last() \ |
796 | do \ | |
797 | { \ | |
798 | if (inst.cond == COND_ALWAYS) \ | |
799 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \ | |
800 | else \ | |
801 | set_it_insn_type (INSIDE_IT_LAST_INSN); \ | |
802 | } \ | |
803 | while (0) | |
804 | ||
c19d1205 | 805 | /* Pure syntax. */ |
b99bd4ef | 806 | |
c19d1205 ZW |
807 | /* This array holds the chars that always start a comment. If the |
808 | pre-processor is disabled, these aren't very useful. */ | |
809 | const char comment_chars[] = "@"; | |
3d0c9500 | 810 | |
c19d1205 ZW |
811 | /* This array holds the chars that only start a comment at the beginning of |
812 | a line. If the line seems to have the form '# 123 filename' | |
813 | .line and .file directives will appear in the pre-processed output. */ | |
814 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
815 | first line of the input file. This is because the compiler outputs | |
816 | #NO_APP at the beginning of its output. */ | |
817 | /* Also note that comments like this one will always work. */ | |
818 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 819 | |
c19d1205 | 820 | const char line_separator_chars[] = ";"; |
b99bd4ef | 821 | |
c19d1205 ZW |
822 | /* Chars that can be used to separate mant |
823 | from exp in floating point numbers. */ | |
824 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 825 | |
c19d1205 ZW |
826 | /* Chars that mean this number is a floating point constant. */ |
827 | /* As in 0f12.456 */ | |
828 | /* or 0d1.2345e12 */ | |
b99bd4ef | 829 | |
c19d1205 | 830 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 831 | |
c19d1205 ZW |
832 | /* Prefix characters that indicate the start of an immediate |
833 | value. */ | |
834 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 835 | |
c19d1205 ZW |
836 | /* Separator character handling. */ |
837 | ||
838 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
839 | ||
840 | static inline int | |
841 | skip_past_char (char ** str, char c) | |
842 | { | |
843 | if (**str == c) | |
844 | { | |
845 | (*str)++; | |
846 | return SUCCESS; | |
3d0c9500 | 847 | } |
c19d1205 ZW |
848 | else |
849 | return FAIL; | |
850 | } | |
c921be7d | 851 | |
c19d1205 | 852 | #define skip_past_comma(str) skip_past_char (str, ',') |
3d0c9500 | 853 | |
c19d1205 ZW |
854 | /* Arithmetic expressions (possibly involving symbols). */ |
855 | ||
856 | /* Return TRUE if anything in the expression is a bignum. */ | |
857 | ||
858 | static int | |
859 | walk_no_bignums (symbolS * sp) | |
860 | { | |
861 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
862 | return 1; | |
863 | ||
864 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 865 | { |
c19d1205 ZW |
866 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
867 | || (symbol_get_value_expression (sp)->X_op_symbol | |
868 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
869 | } |
870 | ||
c19d1205 | 871 | return 0; |
3d0c9500 NC |
872 | } |
873 | ||
c19d1205 ZW |
874 | static int in_my_get_expression = 0; |
875 | ||
876 | /* Third argument to my_get_expression. */ | |
877 | #define GE_NO_PREFIX 0 | |
878 | #define GE_IMM_PREFIX 1 | |
879 | #define GE_OPT_PREFIX 2 | |
5287ad62 JB |
880 | /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) |
881 | immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ | |
882 | #define GE_OPT_PREFIX_BIG 3 | |
a737bd4d | 883 | |
b99bd4ef | 884 | static int |
c19d1205 | 885 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 886 | { |
c19d1205 ZW |
887 | char * save_in; |
888 | segT seg; | |
b99bd4ef | 889 | |
c19d1205 ZW |
890 | /* In unified syntax, all prefixes are optional. */ |
891 | if (unified_syntax) | |
5287ad62 JB |
892 | prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode |
893 | : GE_OPT_PREFIX; | |
b99bd4ef | 894 | |
c19d1205 | 895 | switch (prefix_mode) |
b99bd4ef | 896 | { |
c19d1205 ZW |
897 | case GE_NO_PREFIX: break; |
898 | case GE_IMM_PREFIX: | |
899 | if (!is_immediate_prefix (**str)) | |
900 | { | |
901 | inst.error = _("immediate expression requires a # prefix"); | |
902 | return FAIL; | |
903 | } | |
904 | (*str)++; | |
905 | break; | |
906 | case GE_OPT_PREFIX: | |
5287ad62 | 907 | case GE_OPT_PREFIX_BIG: |
c19d1205 ZW |
908 | if (is_immediate_prefix (**str)) |
909 | (*str)++; | |
910 | break; | |
911 | default: abort (); | |
912 | } | |
b99bd4ef | 913 | |
c19d1205 | 914 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 915 | |
c19d1205 ZW |
916 | save_in = input_line_pointer; |
917 | input_line_pointer = *str; | |
918 | in_my_get_expression = 1; | |
919 | seg = expression (ep); | |
920 | in_my_get_expression = 0; | |
921 | ||
f86adc07 | 922 | if (ep->X_op == O_illegal || ep->X_op == O_absent) |
b99bd4ef | 923 | { |
f86adc07 | 924 | /* We found a bad or missing expression in md_operand(). */ |
c19d1205 ZW |
925 | *str = input_line_pointer; |
926 | input_line_pointer = save_in; | |
927 | if (inst.error == NULL) | |
f86adc07 NS |
928 | inst.error = (ep->X_op == O_absent |
929 | ? _("missing expression") :_("bad expression")); | |
c19d1205 ZW |
930 | return 1; |
931 | } | |
b99bd4ef | 932 | |
c19d1205 ZW |
933 | #ifdef OBJ_AOUT |
934 | if (seg != absolute_section | |
935 | && seg != text_section | |
936 | && seg != data_section | |
937 | && seg != bss_section | |
938 | && seg != undefined_section) | |
939 | { | |
940 | inst.error = _("bad segment"); | |
941 | *str = input_line_pointer; | |
942 | input_line_pointer = save_in; | |
943 | return 1; | |
b99bd4ef | 944 | } |
87975d2a AM |
945 | #else |
946 | (void) seg; | |
c19d1205 | 947 | #endif |
b99bd4ef | 948 | |
c19d1205 ZW |
949 | /* Get rid of any bignums now, so that we don't generate an error for which |
950 | we can't establish a line number later on. Big numbers are never valid | |
951 | in instructions, which is where this routine is always called. */ | |
5287ad62 JB |
952 | if (prefix_mode != GE_OPT_PREFIX_BIG |
953 | && (ep->X_op == O_big | |
954 | || (ep->X_add_symbol | |
955 | && (walk_no_bignums (ep->X_add_symbol) | |
956 | || (ep->X_op_symbol | |
957 | && walk_no_bignums (ep->X_op_symbol)))))) | |
c19d1205 ZW |
958 | { |
959 | inst.error = _("invalid constant"); | |
960 | *str = input_line_pointer; | |
961 | input_line_pointer = save_in; | |
962 | return 1; | |
963 | } | |
b99bd4ef | 964 | |
c19d1205 ZW |
965 | *str = input_line_pointer; |
966 | input_line_pointer = save_in; | |
967 | return 0; | |
b99bd4ef NC |
968 | } |
969 | ||
c19d1205 ZW |
970 | /* Turn a string in input_line_pointer into a floating point constant |
971 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
972 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
973 | returned, or NULL on OK. | |
b99bd4ef | 974 | |
c19d1205 ZW |
975 | Note that fp constants aren't represent in the normal way on the ARM. |
976 | In big endian mode, things are as expected. However, in little endian | |
977 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
978 | within the words. For example, (double) 1.1 in big endian mode is | |
979 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
980 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 981 | |
c19d1205 | 982 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 983 | |
c19d1205 ZW |
984 | char * |
985 | md_atof (int type, char * litP, int * sizeP) | |
986 | { | |
987 | int prec; | |
988 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
989 | char *t; | |
990 | int i; | |
b99bd4ef | 991 | |
c19d1205 ZW |
992 | switch (type) |
993 | { | |
994 | case 'f': | |
995 | case 'F': | |
996 | case 's': | |
997 | case 'S': | |
998 | prec = 2; | |
999 | break; | |
b99bd4ef | 1000 | |
c19d1205 ZW |
1001 | case 'd': |
1002 | case 'D': | |
1003 | case 'r': | |
1004 | case 'R': | |
1005 | prec = 4; | |
1006 | break; | |
b99bd4ef | 1007 | |
c19d1205 ZW |
1008 | case 'x': |
1009 | case 'X': | |
499ac353 | 1010 | prec = 5; |
c19d1205 | 1011 | break; |
b99bd4ef | 1012 | |
c19d1205 ZW |
1013 | case 'p': |
1014 | case 'P': | |
499ac353 | 1015 | prec = 5; |
c19d1205 | 1016 | break; |
a737bd4d | 1017 | |
c19d1205 ZW |
1018 | default: |
1019 | *sizeP = 0; | |
499ac353 | 1020 | return _("Unrecognized or unsupported floating point constant"); |
c19d1205 | 1021 | } |
b99bd4ef | 1022 | |
c19d1205 ZW |
1023 | t = atof_ieee (input_line_pointer, type, words); |
1024 | if (t) | |
1025 | input_line_pointer = t; | |
499ac353 | 1026 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
b99bd4ef | 1027 | |
c19d1205 ZW |
1028 | if (target_big_endian) |
1029 | { | |
1030 | for (i = 0; i < prec; i++) | |
1031 | { | |
499ac353 NC |
1032 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1033 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1034 | } |
1035 | } | |
1036 | else | |
1037 | { | |
e74cfd16 | 1038 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
c19d1205 ZW |
1039 | for (i = prec - 1; i >= 0; i--) |
1040 | { | |
499ac353 NC |
1041 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1042 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1043 | } |
1044 | else | |
1045 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
1046 | For an 8 byte float the order is 1 0 3 2. */ | |
1047 | for (i = 0; i < prec; i += 2) | |
1048 | { | |
499ac353 NC |
1049 | md_number_to_chars (litP, (valueT) words[i + 1], |
1050 | sizeof (LITTLENUM_TYPE)); | |
1051 | md_number_to_chars (litP + sizeof (LITTLENUM_TYPE), | |
1052 | (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
1053 | litP += 2 * sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1054 | } |
1055 | } | |
b99bd4ef | 1056 | |
499ac353 | 1057 | return NULL; |
c19d1205 | 1058 | } |
b99bd4ef | 1059 | |
c19d1205 ZW |
1060 | /* We handle all bad expressions here, so that we can report the faulty |
1061 | instruction in the error message. */ | |
1062 | void | |
91d6fa6a | 1063 | md_operand (expressionS * exp) |
c19d1205 ZW |
1064 | { |
1065 | if (in_my_get_expression) | |
91d6fa6a | 1066 | exp->X_op = O_illegal; |
b99bd4ef NC |
1067 | } |
1068 | ||
c19d1205 | 1069 | /* Immediate values. */ |
b99bd4ef | 1070 | |
c19d1205 ZW |
1071 | /* Generic immediate-value read function for use in directives. |
1072 | Accepts anything that 'expression' can fold to a constant. | |
1073 | *val receives the number. */ | |
1074 | #ifdef OBJ_ELF | |
1075 | static int | |
1076 | immediate_for_directive (int *val) | |
b99bd4ef | 1077 | { |
c19d1205 ZW |
1078 | expressionS exp; |
1079 | exp.X_op = O_illegal; | |
b99bd4ef | 1080 | |
c19d1205 ZW |
1081 | if (is_immediate_prefix (*input_line_pointer)) |
1082 | { | |
1083 | input_line_pointer++; | |
1084 | expression (&exp); | |
1085 | } | |
b99bd4ef | 1086 | |
c19d1205 ZW |
1087 | if (exp.X_op != O_constant) |
1088 | { | |
1089 | as_bad (_("expected #constant")); | |
1090 | ignore_rest_of_line (); | |
1091 | return FAIL; | |
1092 | } | |
1093 | *val = exp.X_add_number; | |
1094 | return SUCCESS; | |
b99bd4ef | 1095 | } |
c19d1205 | 1096 | #endif |
b99bd4ef | 1097 | |
c19d1205 | 1098 | /* Register parsing. */ |
b99bd4ef | 1099 | |
c19d1205 ZW |
1100 | /* Generic register parser. CCP points to what should be the |
1101 | beginning of a register name. If it is indeed a valid register | |
1102 | name, advance CCP over it and return the reg_entry structure; | |
1103 | otherwise return NULL. Does not issue diagnostics. */ | |
1104 | ||
1105 | static struct reg_entry * | |
1106 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 1107 | { |
c19d1205 ZW |
1108 | char *start = *ccp; |
1109 | char *p; | |
1110 | struct reg_entry *reg; | |
b99bd4ef | 1111 | |
c19d1205 ZW |
1112 | #ifdef REGISTER_PREFIX |
1113 | if (*start != REGISTER_PREFIX) | |
01cfc07f | 1114 | return NULL; |
c19d1205 ZW |
1115 | start++; |
1116 | #endif | |
1117 | #ifdef OPTIONAL_REGISTER_PREFIX | |
1118 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
1119 | start++; | |
1120 | #endif | |
b99bd4ef | 1121 | |
c19d1205 ZW |
1122 | p = start; |
1123 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
1124 | return NULL; | |
b99bd4ef | 1125 | |
c19d1205 ZW |
1126 | do |
1127 | p++; | |
1128 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
1129 | ||
1130 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
1131 | ||
1132 | if (!reg) | |
1133 | return NULL; | |
1134 | ||
1135 | *ccp = p; | |
1136 | return reg; | |
b99bd4ef NC |
1137 | } |
1138 | ||
1139 | static int | |
dcbf9037 JB |
1140 | arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, |
1141 | enum arm_reg_type type) | |
b99bd4ef | 1142 | { |
c19d1205 ZW |
1143 | /* Alternative syntaxes are accepted for a few register classes. */ |
1144 | switch (type) | |
1145 | { | |
1146 | case REG_TYPE_MVF: | |
1147 | case REG_TYPE_MVD: | |
1148 | case REG_TYPE_MVFX: | |
1149 | case REG_TYPE_MVDX: | |
1150 | /* Generic coprocessor register names are allowed for these. */ | |
79134647 | 1151 | if (reg && reg->type == REG_TYPE_CN) |
c19d1205 ZW |
1152 | return reg->number; |
1153 | break; | |
69b97547 | 1154 | |
c19d1205 ZW |
1155 | case REG_TYPE_CP: |
1156 | /* For backward compatibility, a bare number is valid here. */ | |
1157 | { | |
1158 | unsigned long processor = strtoul (start, ccp, 10); | |
1159 | if (*ccp != start && processor <= 15) | |
1160 | return processor; | |
1161 | } | |
6057a28f | 1162 | |
c19d1205 ZW |
1163 | case REG_TYPE_MMXWC: |
1164 | /* WC includes WCG. ??? I'm not sure this is true for all | |
1165 | instructions that take WC registers. */ | |
79134647 | 1166 | if (reg && reg->type == REG_TYPE_MMXWCG) |
c19d1205 | 1167 | return reg->number; |
6057a28f | 1168 | break; |
c19d1205 | 1169 | |
6057a28f | 1170 | default: |
c19d1205 | 1171 | break; |
6057a28f NC |
1172 | } |
1173 | ||
dcbf9037 JB |
1174 | return FAIL; |
1175 | } | |
1176 | ||
1177 | /* As arm_reg_parse_multi, but the register must be of type TYPE, and the | |
1178 | return value is the register number or FAIL. */ | |
1179 | ||
1180 | static int | |
1181 | arm_reg_parse (char **ccp, enum arm_reg_type type) | |
1182 | { | |
1183 | char *start = *ccp; | |
1184 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
1185 | int ret; | |
1186 | ||
1187 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1188 | if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) | |
1189 | return FAIL; | |
1190 | ||
1191 | if (reg && reg->type == type) | |
1192 | return reg->number; | |
1193 | ||
1194 | if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) | |
1195 | return ret; | |
1196 | ||
c19d1205 ZW |
1197 | *ccp = start; |
1198 | return FAIL; | |
1199 | } | |
69b97547 | 1200 | |
dcbf9037 JB |
1201 | /* Parse a Neon type specifier. *STR should point at the leading '.' |
1202 | character. Does no verification at this stage that the type fits the opcode | |
1203 | properly. E.g., | |
1204 | ||
1205 | .i32.i32.s16 | |
1206 | .s32.f32 | |
1207 | .u16 | |
1208 | ||
1209 | Can all be legally parsed by this function. | |
1210 | ||
1211 | Fills in neon_type struct pointer with parsed information, and updates STR | |
1212 | to point after the parsed type specifier. Returns SUCCESS if this was a legal | |
1213 | type, FAIL if not. */ | |
1214 | ||
1215 | static int | |
1216 | parse_neon_type (struct neon_type *type, char **str) | |
1217 | { | |
1218 | char *ptr = *str; | |
1219 | ||
1220 | if (type) | |
1221 | type->elems = 0; | |
1222 | ||
1223 | while (type->elems < NEON_MAX_TYPE_ELS) | |
1224 | { | |
1225 | enum neon_el_type thistype = NT_untyped; | |
1226 | unsigned thissize = -1u; | |
1227 | ||
1228 | if (*ptr != '.') | |
1229 | break; | |
1230 | ||
1231 | ptr++; | |
1232 | ||
1233 | /* Just a size without an explicit type. */ | |
1234 | if (ISDIGIT (*ptr)) | |
1235 | goto parsesize; | |
1236 | ||
1237 | switch (TOLOWER (*ptr)) | |
1238 | { | |
1239 | case 'i': thistype = NT_integer; break; | |
1240 | case 'f': thistype = NT_float; break; | |
1241 | case 'p': thistype = NT_poly; break; | |
1242 | case 's': thistype = NT_signed; break; | |
1243 | case 'u': thistype = NT_unsigned; break; | |
037e8744 JB |
1244 | case 'd': |
1245 | thistype = NT_float; | |
1246 | thissize = 64; | |
1247 | ptr++; | |
1248 | goto done; | |
dcbf9037 JB |
1249 | default: |
1250 | as_bad (_("unexpected character `%c' in type specifier"), *ptr); | |
1251 | return FAIL; | |
1252 | } | |
1253 | ||
1254 | ptr++; | |
1255 | ||
1256 | /* .f is an abbreviation for .f32. */ | |
1257 | if (thistype == NT_float && !ISDIGIT (*ptr)) | |
1258 | thissize = 32; | |
1259 | else | |
1260 | { | |
1261 | parsesize: | |
1262 | thissize = strtoul (ptr, &ptr, 10); | |
1263 | ||
1264 | if (thissize != 8 && thissize != 16 && thissize != 32 | |
1265 | && thissize != 64) | |
1266 | { | |
1267 | as_bad (_("bad size %d in type specifier"), thissize); | |
1268 | return FAIL; | |
1269 | } | |
1270 | } | |
1271 | ||
037e8744 | 1272 | done: |
dcbf9037 JB |
1273 | if (type) |
1274 | { | |
1275 | type->el[type->elems].type = thistype; | |
1276 | type->el[type->elems].size = thissize; | |
1277 | type->elems++; | |
1278 | } | |
1279 | } | |
1280 | ||
1281 | /* Empty/missing type is not a successful parse. */ | |
1282 | if (type->elems == 0) | |
1283 | return FAIL; | |
1284 | ||
1285 | *str = ptr; | |
1286 | ||
1287 | return SUCCESS; | |
1288 | } | |
1289 | ||
1290 | /* Errors may be set multiple times during parsing or bit encoding | |
1291 | (particularly in the Neon bits), but usually the earliest error which is set | |
1292 | will be the most meaningful. Avoid overwriting it with later (cascading) | |
1293 | errors by calling this function. */ | |
1294 | ||
1295 | static void | |
1296 | first_error (const char *err) | |
1297 | { | |
1298 | if (!inst.error) | |
1299 | inst.error = err; | |
1300 | } | |
1301 | ||
1302 | /* Parse a single type, e.g. ".s32", leading period included. */ | |
1303 | static int | |
1304 | parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) | |
1305 | { | |
1306 | char *str = *ccp; | |
1307 | struct neon_type optype; | |
1308 | ||
1309 | if (*str == '.') | |
1310 | { | |
1311 | if (parse_neon_type (&optype, &str) == SUCCESS) | |
1312 | { | |
1313 | if (optype.elems == 1) | |
1314 | *vectype = optype.el[0]; | |
1315 | else | |
1316 | { | |
1317 | first_error (_("only one type should be specified for operand")); | |
1318 | return FAIL; | |
1319 | } | |
1320 | } | |
1321 | else | |
1322 | { | |
1323 | first_error (_("vector type expected")); | |
1324 | return FAIL; | |
1325 | } | |
1326 | } | |
1327 | else | |
1328 | return FAIL; | |
5f4273c7 | 1329 | |
dcbf9037 | 1330 | *ccp = str; |
5f4273c7 | 1331 | |
dcbf9037 JB |
1332 | return SUCCESS; |
1333 | } | |
1334 | ||
1335 | /* Special meanings for indices (which have a range of 0-7), which will fit into | |
1336 | a 4-bit integer. */ | |
1337 | ||
1338 | #define NEON_ALL_LANES 15 | |
1339 | #define NEON_INTERLEAVE_LANES 14 | |
1340 | ||
1341 | /* Parse either a register or a scalar, with an optional type. Return the | |
1342 | register number, and optionally fill in the actual type of the register | |
1343 | when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and | |
1344 | type/index information in *TYPEINFO. */ | |
1345 | ||
1346 | static int | |
1347 | parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, | |
1348 | enum arm_reg_type *rtype, | |
1349 | struct neon_typed_alias *typeinfo) | |
1350 | { | |
1351 | char *str = *ccp; | |
1352 | struct reg_entry *reg = arm_reg_parse_multi (&str); | |
1353 | struct neon_typed_alias atype; | |
1354 | struct neon_type_el parsetype; | |
1355 | ||
1356 | atype.defined = 0; | |
1357 | atype.index = -1; | |
1358 | atype.eltype.type = NT_invtype; | |
1359 | atype.eltype.size = -1; | |
1360 | ||
1361 | /* Try alternate syntax for some types of register. Note these are mutually | |
1362 | exclusive with the Neon syntax extensions. */ | |
1363 | if (reg == NULL) | |
1364 | { | |
1365 | int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); | |
1366 | if (altreg != FAIL) | |
1367 | *ccp = str; | |
1368 | if (typeinfo) | |
1369 | *typeinfo = atype; | |
1370 | return altreg; | |
1371 | } | |
1372 | ||
037e8744 JB |
1373 | /* Undo polymorphism when a set of register types may be accepted. */ |
1374 | if ((type == REG_TYPE_NDQ | |
1375 | && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) | |
1376 | || (type == REG_TYPE_VFSD | |
1377 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) | |
1378 | || (type == REG_TYPE_NSDQ | |
1379 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD | |
f512f76f NC |
1380 | || reg->type == REG_TYPE_NQ)) |
1381 | || (type == REG_TYPE_MMXWC | |
1382 | && (reg->type == REG_TYPE_MMXWCG))) | |
21d799b5 | 1383 | type = (enum arm_reg_type) reg->type; |
dcbf9037 JB |
1384 | |
1385 | if (type != reg->type) | |
1386 | return FAIL; | |
1387 | ||
1388 | if (reg->neon) | |
1389 | atype = *reg->neon; | |
5f4273c7 | 1390 | |
dcbf9037 JB |
1391 | if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) |
1392 | { | |
1393 | if ((atype.defined & NTA_HASTYPE) != 0) | |
1394 | { | |
1395 | first_error (_("can't redefine type for operand")); | |
1396 | return FAIL; | |
1397 | } | |
1398 | atype.defined |= NTA_HASTYPE; | |
1399 | atype.eltype = parsetype; | |
1400 | } | |
5f4273c7 | 1401 | |
dcbf9037 JB |
1402 | if (skip_past_char (&str, '[') == SUCCESS) |
1403 | { | |
1404 | if (type != REG_TYPE_VFD) | |
1405 | { | |
1406 | first_error (_("only D registers may be indexed")); | |
1407 | return FAIL; | |
1408 | } | |
5f4273c7 | 1409 | |
dcbf9037 JB |
1410 | if ((atype.defined & NTA_HASINDEX) != 0) |
1411 | { | |
1412 | first_error (_("can't change index for operand")); | |
1413 | return FAIL; | |
1414 | } | |
1415 | ||
1416 | atype.defined |= NTA_HASINDEX; | |
1417 | ||
1418 | if (skip_past_char (&str, ']') == SUCCESS) | |
1419 | atype.index = NEON_ALL_LANES; | |
1420 | else | |
1421 | { | |
1422 | expressionS exp; | |
1423 | ||
1424 | my_get_expression (&exp, &str, GE_NO_PREFIX); | |
1425 | ||
1426 | if (exp.X_op != O_constant) | |
1427 | { | |
1428 | first_error (_("constant expression required")); | |
1429 | return FAIL; | |
1430 | } | |
1431 | ||
1432 | if (skip_past_char (&str, ']') == FAIL) | |
1433 | return FAIL; | |
1434 | ||
1435 | atype.index = exp.X_add_number; | |
1436 | } | |
1437 | } | |
5f4273c7 | 1438 | |
dcbf9037 JB |
1439 | if (typeinfo) |
1440 | *typeinfo = atype; | |
5f4273c7 | 1441 | |
dcbf9037 JB |
1442 | if (rtype) |
1443 | *rtype = type; | |
5f4273c7 | 1444 | |
dcbf9037 | 1445 | *ccp = str; |
5f4273c7 | 1446 | |
dcbf9037 JB |
1447 | return reg->number; |
1448 | } | |
1449 | ||
1450 | /* Like arm_reg_parse, but allow allow the following extra features: | |
1451 | - If RTYPE is non-zero, return the (possibly restricted) type of the | |
1452 | register (e.g. Neon double or quad reg when either has been requested). | |
1453 | - If this is a Neon vector type with additional type information, fill | |
1454 | in the struct pointed to by VECTYPE (if non-NULL). | |
5f4273c7 | 1455 | This function will fault on encountering a scalar. */ |
dcbf9037 JB |
1456 | |
1457 | static int | |
1458 | arm_typed_reg_parse (char **ccp, enum arm_reg_type type, | |
1459 | enum arm_reg_type *rtype, struct neon_type_el *vectype) | |
1460 | { | |
1461 | struct neon_typed_alias atype; | |
1462 | char *str = *ccp; | |
1463 | int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); | |
1464 | ||
1465 | if (reg == FAIL) | |
1466 | return FAIL; | |
1467 | ||
1468 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1469 | if ((atype.defined & NTA_HASINDEX) != 0) | |
1470 | { | |
1471 | first_error (_("register operand expected, but got scalar")); | |
1472 | return FAIL; | |
1473 | } | |
1474 | ||
1475 | if (vectype) | |
1476 | *vectype = atype.eltype; | |
1477 | ||
1478 | *ccp = str; | |
1479 | ||
1480 | return reg; | |
1481 | } | |
1482 | ||
1483 | #define NEON_SCALAR_REG(X) ((X) >> 4) | |
1484 | #define NEON_SCALAR_INDEX(X) ((X) & 15) | |
1485 | ||
5287ad62 JB |
1486 | /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't |
1487 | have enough information to be able to do a good job bounds-checking. So, we | |
1488 | just do easy checks here, and do further checks later. */ | |
1489 | ||
1490 | static int | |
dcbf9037 | 1491 | parse_scalar (char **ccp, int elsize, struct neon_type_el *type) |
5287ad62 | 1492 | { |
dcbf9037 | 1493 | int reg; |
5287ad62 | 1494 | char *str = *ccp; |
dcbf9037 | 1495 | struct neon_typed_alias atype; |
5f4273c7 | 1496 | |
dcbf9037 | 1497 | reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); |
5f4273c7 | 1498 | |
dcbf9037 | 1499 | if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) |
5287ad62 | 1500 | return FAIL; |
5f4273c7 | 1501 | |
dcbf9037 | 1502 | if (atype.index == NEON_ALL_LANES) |
5287ad62 | 1503 | { |
dcbf9037 | 1504 | first_error (_("scalar must have an index")); |
5287ad62 JB |
1505 | return FAIL; |
1506 | } | |
dcbf9037 | 1507 | else if (atype.index >= 64 / elsize) |
5287ad62 | 1508 | { |
dcbf9037 | 1509 | first_error (_("scalar index out of range")); |
5287ad62 JB |
1510 | return FAIL; |
1511 | } | |
5f4273c7 | 1512 | |
dcbf9037 JB |
1513 | if (type) |
1514 | *type = atype.eltype; | |
5f4273c7 | 1515 | |
5287ad62 | 1516 | *ccp = str; |
5f4273c7 | 1517 | |
dcbf9037 | 1518 | return reg * 16 + atype.index; |
5287ad62 JB |
1519 | } |
1520 | ||
c19d1205 | 1521 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
e07e6e58 | 1522 | |
c19d1205 ZW |
1523 | static long |
1524 | parse_reg_list (char ** strp) | |
1525 | { | |
1526 | char * str = * strp; | |
1527 | long range = 0; | |
1528 | int another_range; | |
a737bd4d | 1529 | |
c19d1205 ZW |
1530 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
1531 | do | |
6057a28f | 1532 | { |
c19d1205 | 1533 | another_range = 0; |
a737bd4d | 1534 | |
c19d1205 ZW |
1535 | if (*str == '{') |
1536 | { | |
1537 | int in_range = 0; | |
1538 | int cur_reg = -1; | |
a737bd4d | 1539 | |
c19d1205 ZW |
1540 | str++; |
1541 | do | |
1542 | { | |
1543 | int reg; | |
6057a28f | 1544 | |
dcbf9037 | 1545 | if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) |
c19d1205 | 1546 | { |
dcbf9037 | 1547 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 ZW |
1548 | return FAIL; |
1549 | } | |
a737bd4d | 1550 | |
c19d1205 ZW |
1551 | if (in_range) |
1552 | { | |
1553 | int i; | |
a737bd4d | 1554 | |
c19d1205 ZW |
1555 | if (reg <= cur_reg) |
1556 | { | |
dcbf9037 | 1557 | first_error (_("bad range in register list")); |
c19d1205 ZW |
1558 | return FAIL; |
1559 | } | |
40a18ebd | 1560 | |
c19d1205 ZW |
1561 | for (i = cur_reg + 1; i < reg; i++) |
1562 | { | |
1563 | if (range & (1 << i)) | |
1564 | as_tsktsk | |
1565 | (_("Warning: duplicated register (r%d) in register list"), | |
1566 | i); | |
1567 | else | |
1568 | range |= 1 << i; | |
1569 | } | |
1570 | in_range = 0; | |
1571 | } | |
a737bd4d | 1572 | |
c19d1205 ZW |
1573 | if (range & (1 << reg)) |
1574 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
1575 | reg); | |
1576 | else if (reg <= cur_reg) | |
1577 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 1578 | |
c19d1205 ZW |
1579 | range |= 1 << reg; |
1580 | cur_reg = reg; | |
1581 | } | |
1582 | while (skip_past_comma (&str) != FAIL | |
1583 | || (in_range = 1, *str++ == '-')); | |
1584 | str--; | |
a737bd4d | 1585 | |
c19d1205 ZW |
1586 | if (*str++ != '}') |
1587 | { | |
dcbf9037 | 1588 | first_error (_("missing `}'")); |
c19d1205 ZW |
1589 | return FAIL; |
1590 | } | |
1591 | } | |
1592 | else | |
1593 | { | |
91d6fa6a | 1594 | expressionS exp; |
40a18ebd | 1595 | |
91d6fa6a | 1596 | if (my_get_expression (&exp, &str, GE_NO_PREFIX)) |
c19d1205 | 1597 | return FAIL; |
40a18ebd | 1598 | |
91d6fa6a | 1599 | if (exp.X_op == O_constant) |
c19d1205 | 1600 | { |
91d6fa6a NC |
1601 | if (exp.X_add_number |
1602 | != (exp.X_add_number & 0x0000ffff)) | |
c19d1205 ZW |
1603 | { |
1604 | inst.error = _("invalid register mask"); | |
1605 | return FAIL; | |
1606 | } | |
a737bd4d | 1607 | |
91d6fa6a | 1608 | if ((range & exp.X_add_number) != 0) |
c19d1205 | 1609 | { |
91d6fa6a | 1610 | int regno = range & exp.X_add_number; |
a737bd4d | 1611 | |
c19d1205 ZW |
1612 | regno &= -regno; |
1613 | regno = (1 << regno) - 1; | |
1614 | as_tsktsk | |
1615 | (_("Warning: duplicated register (r%d) in register list"), | |
1616 | regno); | |
1617 | } | |
a737bd4d | 1618 | |
91d6fa6a | 1619 | range |= exp.X_add_number; |
c19d1205 ZW |
1620 | } |
1621 | else | |
1622 | { | |
1623 | if (inst.reloc.type != 0) | |
1624 | { | |
1625 | inst.error = _("expression too complex"); | |
1626 | return FAIL; | |
1627 | } | |
a737bd4d | 1628 | |
91d6fa6a | 1629 | memcpy (&inst.reloc.exp, &exp, sizeof (expressionS)); |
c19d1205 ZW |
1630 | inst.reloc.type = BFD_RELOC_ARM_MULTI; |
1631 | inst.reloc.pc_rel = 0; | |
1632 | } | |
1633 | } | |
a737bd4d | 1634 | |
c19d1205 ZW |
1635 | if (*str == '|' || *str == '+') |
1636 | { | |
1637 | str++; | |
1638 | another_range = 1; | |
1639 | } | |
a737bd4d | 1640 | } |
c19d1205 | 1641 | while (another_range); |
a737bd4d | 1642 | |
c19d1205 ZW |
1643 | *strp = str; |
1644 | return range; | |
a737bd4d NC |
1645 | } |
1646 | ||
5287ad62 JB |
1647 | /* Types of registers in a list. */ |
1648 | ||
1649 | enum reg_list_els | |
1650 | { | |
1651 | REGLIST_VFP_S, | |
1652 | REGLIST_VFP_D, | |
1653 | REGLIST_NEON_D | |
1654 | }; | |
1655 | ||
c19d1205 ZW |
1656 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1657 | Otherwise return the number of registers, and set PBASE to the first | |
5287ad62 JB |
1658 | register. Parses registers of type ETYPE. |
1659 | If REGLIST_NEON_D is used, several syntax enhancements are enabled: | |
1660 | - Q registers can be used to specify pairs of D registers | |
1661 | - { } can be omitted from around a singleton register list | |
1662 | FIXME: This is not implemented, as it would require backtracking in | |
1663 | some cases, e.g.: | |
1664 | vtbl.8 d3,d4,d5 | |
1665 | This could be done (the meaning isn't really ambiguous), but doesn't | |
1666 | fit in well with the current parsing framework. | |
dcbf9037 JB |
1667 | - 32 D registers may be used (also true for VFPv3). |
1668 | FIXME: Types are ignored in these register lists, which is probably a | |
1669 | bug. */ | |
6057a28f | 1670 | |
c19d1205 | 1671 | static int |
037e8744 | 1672 | parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) |
6057a28f | 1673 | { |
037e8744 | 1674 | char *str = *ccp; |
c19d1205 ZW |
1675 | int base_reg; |
1676 | int new_base; | |
21d799b5 | 1677 | enum arm_reg_type regtype = (enum arm_reg_type) 0; |
5287ad62 | 1678 | int max_regs = 0; |
c19d1205 ZW |
1679 | int count = 0; |
1680 | int warned = 0; | |
1681 | unsigned long mask = 0; | |
a737bd4d | 1682 | int i; |
6057a28f | 1683 | |
037e8744 | 1684 | if (*str != '{') |
5287ad62 JB |
1685 | { |
1686 | inst.error = _("expecting {"); | |
1687 | return FAIL; | |
1688 | } | |
6057a28f | 1689 | |
037e8744 | 1690 | str++; |
6057a28f | 1691 | |
5287ad62 | 1692 | switch (etype) |
c19d1205 | 1693 | { |
5287ad62 | 1694 | case REGLIST_VFP_S: |
c19d1205 ZW |
1695 | regtype = REG_TYPE_VFS; |
1696 | max_regs = 32; | |
5287ad62 | 1697 | break; |
5f4273c7 | 1698 | |
5287ad62 JB |
1699 | case REGLIST_VFP_D: |
1700 | regtype = REG_TYPE_VFD; | |
b7fc2769 | 1701 | break; |
5f4273c7 | 1702 | |
b7fc2769 JB |
1703 | case REGLIST_NEON_D: |
1704 | regtype = REG_TYPE_NDQ; | |
1705 | break; | |
1706 | } | |
1707 | ||
1708 | if (etype != REGLIST_VFP_S) | |
1709 | { | |
b1cc4aeb PB |
1710 | /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */ |
1711 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) | |
5287ad62 JB |
1712 | { |
1713 | max_regs = 32; | |
1714 | if (thumb_mode) | |
1715 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
b1cc4aeb | 1716 | fpu_vfp_ext_d32); |
5287ad62 JB |
1717 | else |
1718 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
b1cc4aeb | 1719 | fpu_vfp_ext_d32); |
5287ad62 JB |
1720 | } |
1721 | else | |
1722 | max_regs = 16; | |
c19d1205 | 1723 | } |
6057a28f | 1724 | |
c19d1205 | 1725 | base_reg = max_regs; |
a737bd4d | 1726 | |
c19d1205 ZW |
1727 | do |
1728 | { | |
5287ad62 | 1729 | int setmask = 1, addregs = 1; |
dcbf9037 | 1730 | |
037e8744 | 1731 | new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); |
dcbf9037 | 1732 | |
c19d1205 | 1733 | if (new_base == FAIL) |
a737bd4d | 1734 | { |
dcbf9037 | 1735 | first_error (_(reg_expected_msgs[regtype])); |
c19d1205 ZW |
1736 | return FAIL; |
1737 | } | |
5f4273c7 | 1738 | |
b7fc2769 JB |
1739 | if (new_base >= max_regs) |
1740 | { | |
1741 | first_error (_("register out of range in list")); | |
1742 | return FAIL; | |
1743 | } | |
5f4273c7 | 1744 | |
5287ad62 JB |
1745 | /* Note: a value of 2 * n is returned for the register Q<n>. */ |
1746 | if (regtype == REG_TYPE_NQ) | |
1747 | { | |
1748 | setmask = 3; | |
1749 | addregs = 2; | |
1750 | } | |
1751 | ||
c19d1205 ZW |
1752 | if (new_base < base_reg) |
1753 | base_reg = new_base; | |
a737bd4d | 1754 | |
5287ad62 | 1755 | if (mask & (setmask << new_base)) |
c19d1205 | 1756 | { |
dcbf9037 | 1757 | first_error (_("invalid register list")); |
c19d1205 | 1758 | return FAIL; |
a737bd4d | 1759 | } |
a737bd4d | 1760 | |
c19d1205 ZW |
1761 | if ((mask >> new_base) != 0 && ! warned) |
1762 | { | |
1763 | as_tsktsk (_("register list not in ascending order")); | |
1764 | warned = 1; | |
1765 | } | |
0bbf2aa4 | 1766 | |
5287ad62 JB |
1767 | mask |= setmask << new_base; |
1768 | count += addregs; | |
0bbf2aa4 | 1769 | |
037e8744 | 1770 | if (*str == '-') /* We have the start of a range expression */ |
c19d1205 ZW |
1771 | { |
1772 | int high_range; | |
0bbf2aa4 | 1773 | |
037e8744 | 1774 | str++; |
0bbf2aa4 | 1775 | |
037e8744 | 1776 | if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) |
dcbf9037 | 1777 | == FAIL) |
c19d1205 ZW |
1778 | { |
1779 | inst.error = gettext (reg_expected_msgs[regtype]); | |
1780 | return FAIL; | |
1781 | } | |
0bbf2aa4 | 1782 | |
b7fc2769 JB |
1783 | if (high_range >= max_regs) |
1784 | { | |
1785 | first_error (_("register out of range in list")); | |
1786 | return FAIL; | |
1787 | } | |
1788 | ||
5287ad62 JB |
1789 | if (regtype == REG_TYPE_NQ) |
1790 | high_range = high_range + 1; | |
1791 | ||
c19d1205 ZW |
1792 | if (high_range <= new_base) |
1793 | { | |
1794 | inst.error = _("register range not in ascending order"); | |
1795 | return FAIL; | |
1796 | } | |
0bbf2aa4 | 1797 | |
5287ad62 | 1798 | for (new_base += addregs; new_base <= high_range; new_base += addregs) |
0bbf2aa4 | 1799 | { |
5287ad62 | 1800 | if (mask & (setmask << new_base)) |
0bbf2aa4 | 1801 | { |
c19d1205 ZW |
1802 | inst.error = _("invalid register list"); |
1803 | return FAIL; | |
0bbf2aa4 | 1804 | } |
c19d1205 | 1805 | |
5287ad62 JB |
1806 | mask |= setmask << new_base; |
1807 | count += addregs; | |
0bbf2aa4 | 1808 | } |
0bbf2aa4 | 1809 | } |
0bbf2aa4 | 1810 | } |
037e8744 | 1811 | while (skip_past_comma (&str) != FAIL); |
0bbf2aa4 | 1812 | |
037e8744 | 1813 | str++; |
0bbf2aa4 | 1814 | |
c19d1205 ZW |
1815 | /* Sanity check -- should have raised a parse error above. */ |
1816 | if (count == 0 || count > max_regs) | |
1817 | abort (); | |
1818 | ||
1819 | *pbase = base_reg; | |
1820 | ||
1821 | /* Final test -- the registers must be consecutive. */ | |
1822 | mask >>= base_reg; | |
1823 | for (i = 0; i < count; i++) | |
1824 | { | |
1825 | if ((mask & (1u << i)) == 0) | |
1826 | { | |
1827 | inst.error = _("non-contiguous register range"); | |
1828 | return FAIL; | |
1829 | } | |
1830 | } | |
1831 | ||
037e8744 JB |
1832 | *ccp = str; |
1833 | ||
c19d1205 | 1834 | return count; |
b99bd4ef NC |
1835 | } |
1836 | ||
dcbf9037 JB |
1837 | /* True if two alias types are the same. */ |
1838 | ||
c921be7d | 1839 | static bfd_boolean |
dcbf9037 JB |
1840 | neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) |
1841 | { | |
1842 | if (!a && !b) | |
c921be7d | 1843 | return TRUE; |
5f4273c7 | 1844 | |
dcbf9037 | 1845 | if (!a || !b) |
c921be7d | 1846 | return FALSE; |
dcbf9037 JB |
1847 | |
1848 | if (a->defined != b->defined) | |
c921be7d | 1849 | return FALSE; |
5f4273c7 | 1850 | |
dcbf9037 JB |
1851 | if ((a->defined & NTA_HASTYPE) != 0 |
1852 | && (a->eltype.type != b->eltype.type | |
1853 | || a->eltype.size != b->eltype.size)) | |
c921be7d | 1854 | return FALSE; |
dcbf9037 JB |
1855 | |
1856 | if ((a->defined & NTA_HASINDEX) != 0 | |
1857 | && (a->index != b->index)) | |
c921be7d | 1858 | return FALSE; |
5f4273c7 | 1859 | |
c921be7d | 1860 | return TRUE; |
dcbf9037 JB |
1861 | } |
1862 | ||
5287ad62 JB |
1863 | /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. |
1864 | The base register is put in *PBASE. | |
dcbf9037 | 1865 | The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of |
5287ad62 JB |
1866 | the return value. |
1867 | The register stride (minus one) is put in bit 4 of the return value. | |
dcbf9037 JB |
1868 | Bits [6:5] encode the list length (minus one). |
1869 | The type of the list elements is put in *ELTYPE, if non-NULL. */ | |
5287ad62 | 1870 | |
5287ad62 | 1871 | #define NEON_LANE(X) ((X) & 0xf) |
dcbf9037 | 1872 | #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) |
5287ad62 JB |
1873 | #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) |
1874 | ||
1875 | static int | |
dcbf9037 JB |
1876 | parse_neon_el_struct_list (char **str, unsigned *pbase, |
1877 | struct neon_type_el *eltype) | |
5287ad62 JB |
1878 | { |
1879 | char *ptr = *str; | |
1880 | int base_reg = -1; | |
1881 | int reg_incr = -1; | |
1882 | int count = 0; | |
1883 | int lane = -1; | |
1884 | int leading_brace = 0; | |
1885 | enum arm_reg_type rtype = REG_TYPE_NDQ; | |
20203fb9 NC |
1886 | const char *const incr_error = _("register stride must be 1 or 2"); |
1887 | const char *const type_error = _("mismatched element/structure types in list"); | |
dcbf9037 | 1888 | struct neon_typed_alias firsttype; |
5f4273c7 | 1889 | |
5287ad62 JB |
1890 | if (skip_past_char (&ptr, '{') == SUCCESS) |
1891 | leading_brace = 1; | |
5f4273c7 | 1892 | |
5287ad62 JB |
1893 | do |
1894 | { | |
dcbf9037 JB |
1895 | struct neon_typed_alias atype; |
1896 | int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); | |
1897 | ||
5287ad62 JB |
1898 | if (getreg == FAIL) |
1899 | { | |
dcbf9037 | 1900 | first_error (_(reg_expected_msgs[rtype])); |
5287ad62 JB |
1901 | return FAIL; |
1902 | } | |
5f4273c7 | 1903 | |
5287ad62 JB |
1904 | if (base_reg == -1) |
1905 | { | |
1906 | base_reg = getreg; | |
1907 | if (rtype == REG_TYPE_NQ) | |
1908 | { | |
1909 | reg_incr = 1; | |
5287ad62 | 1910 | } |
dcbf9037 | 1911 | firsttype = atype; |
5287ad62 JB |
1912 | } |
1913 | else if (reg_incr == -1) | |
1914 | { | |
1915 | reg_incr = getreg - base_reg; | |
1916 | if (reg_incr < 1 || reg_incr > 2) | |
1917 | { | |
dcbf9037 | 1918 | first_error (_(incr_error)); |
5287ad62 JB |
1919 | return FAIL; |
1920 | } | |
1921 | } | |
1922 | else if (getreg != base_reg + reg_incr * count) | |
1923 | { | |
dcbf9037 JB |
1924 | first_error (_(incr_error)); |
1925 | return FAIL; | |
1926 | } | |
1927 | ||
c921be7d | 1928 | if (! neon_alias_types_same (&atype, &firsttype)) |
dcbf9037 JB |
1929 | { |
1930 | first_error (_(type_error)); | |
5287ad62 JB |
1931 | return FAIL; |
1932 | } | |
5f4273c7 | 1933 | |
5287ad62 JB |
1934 | /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list |
1935 | modes. */ | |
1936 | if (ptr[0] == '-') | |
1937 | { | |
dcbf9037 | 1938 | struct neon_typed_alias htype; |
5287ad62 JB |
1939 | int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; |
1940 | if (lane == -1) | |
1941 | lane = NEON_INTERLEAVE_LANES; | |
1942 | else if (lane != NEON_INTERLEAVE_LANES) | |
1943 | { | |
dcbf9037 | 1944 | first_error (_(type_error)); |
5287ad62 JB |
1945 | return FAIL; |
1946 | } | |
1947 | if (reg_incr == -1) | |
1948 | reg_incr = 1; | |
1949 | else if (reg_incr != 1) | |
1950 | { | |
dcbf9037 | 1951 | first_error (_("don't use Rn-Rm syntax with non-unit stride")); |
5287ad62 JB |
1952 | return FAIL; |
1953 | } | |
1954 | ptr++; | |
dcbf9037 | 1955 | hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); |
5287ad62 JB |
1956 | if (hireg == FAIL) |
1957 | { | |
dcbf9037 JB |
1958 | first_error (_(reg_expected_msgs[rtype])); |
1959 | return FAIL; | |
1960 | } | |
c921be7d | 1961 | if (! neon_alias_types_same (&htype, &firsttype)) |
dcbf9037 JB |
1962 | { |
1963 | first_error (_(type_error)); | |
5287ad62 JB |
1964 | return FAIL; |
1965 | } | |
1966 | count += hireg + dregs - getreg; | |
1967 | continue; | |
1968 | } | |
5f4273c7 | 1969 | |
5287ad62 JB |
1970 | /* If we're using Q registers, we can't use [] or [n] syntax. */ |
1971 | if (rtype == REG_TYPE_NQ) | |
1972 | { | |
1973 | count += 2; | |
1974 | continue; | |
1975 | } | |
5f4273c7 | 1976 | |
dcbf9037 | 1977 | if ((atype.defined & NTA_HASINDEX) != 0) |
5287ad62 | 1978 | { |
dcbf9037 JB |
1979 | if (lane == -1) |
1980 | lane = atype.index; | |
1981 | else if (lane != atype.index) | |
5287ad62 | 1982 | { |
dcbf9037 JB |
1983 | first_error (_(type_error)); |
1984 | return FAIL; | |
5287ad62 JB |
1985 | } |
1986 | } | |
1987 | else if (lane == -1) | |
1988 | lane = NEON_INTERLEAVE_LANES; | |
1989 | else if (lane != NEON_INTERLEAVE_LANES) | |
1990 | { | |
dcbf9037 | 1991 | first_error (_(type_error)); |
5287ad62 JB |
1992 | return FAIL; |
1993 | } | |
1994 | count++; | |
1995 | } | |
1996 | while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); | |
5f4273c7 | 1997 | |
5287ad62 JB |
1998 | /* No lane set by [x]. We must be interleaving structures. */ |
1999 | if (lane == -1) | |
2000 | lane = NEON_INTERLEAVE_LANES; | |
5f4273c7 | 2001 | |
5287ad62 JB |
2002 | /* Sanity check. */ |
2003 | if (lane == -1 || base_reg == -1 || count < 1 || count > 4 | |
2004 | || (count > 1 && reg_incr == -1)) | |
2005 | { | |
dcbf9037 | 2006 | first_error (_("error parsing element/structure list")); |
5287ad62 JB |
2007 | return FAIL; |
2008 | } | |
2009 | ||
2010 | if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) | |
2011 | { | |
dcbf9037 | 2012 | first_error (_("expected }")); |
5287ad62 JB |
2013 | return FAIL; |
2014 | } | |
5f4273c7 | 2015 | |
5287ad62 JB |
2016 | if (reg_incr == -1) |
2017 | reg_incr = 1; | |
2018 | ||
dcbf9037 JB |
2019 | if (eltype) |
2020 | *eltype = firsttype.eltype; | |
2021 | ||
5287ad62 JB |
2022 | *pbase = base_reg; |
2023 | *str = ptr; | |
5f4273c7 | 2024 | |
5287ad62 JB |
2025 | return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); |
2026 | } | |
2027 | ||
c19d1205 ZW |
2028 | /* Parse an explicit relocation suffix on an expression. This is |
2029 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
2030 | arm_reloc_hsh contains no entries, so this function can only | |
2031 | succeed if there is no () after the word. Returns -1 on error, | |
2032 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
2033 | static int | |
2034 | parse_reloc (char **str) | |
b99bd4ef | 2035 | { |
c19d1205 ZW |
2036 | struct reloc_entry *r; |
2037 | char *p, *q; | |
b99bd4ef | 2038 | |
c19d1205 ZW |
2039 | if (**str != '(') |
2040 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 2041 | |
c19d1205 ZW |
2042 | p = *str + 1; |
2043 | q = p; | |
2044 | ||
2045 | while (*q && *q != ')' && *q != ',') | |
2046 | q++; | |
2047 | if (*q != ')') | |
2048 | return -1; | |
2049 | ||
21d799b5 NC |
2050 | if ((r = (struct reloc_entry *) |
2051 | hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
c19d1205 ZW |
2052 | return -1; |
2053 | ||
2054 | *str = q + 1; | |
2055 | return r->reloc; | |
b99bd4ef NC |
2056 | } |
2057 | ||
c19d1205 ZW |
2058 | /* Directives: register aliases. */ |
2059 | ||
dcbf9037 | 2060 | static struct reg_entry * |
c19d1205 | 2061 | insert_reg_alias (char *str, int number, int type) |
b99bd4ef | 2062 | { |
d3ce72d0 | 2063 | struct reg_entry *new_reg; |
c19d1205 | 2064 | const char *name; |
b99bd4ef | 2065 | |
d3ce72d0 | 2066 | if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0) |
c19d1205 | 2067 | { |
d3ce72d0 | 2068 | if (new_reg->builtin) |
c19d1205 | 2069 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); |
b99bd4ef | 2070 | |
c19d1205 ZW |
2071 | /* Only warn about a redefinition if it's not defined as the |
2072 | same register. */ | |
d3ce72d0 | 2073 | else if (new_reg->number != number || new_reg->type != type) |
c19d1205 | 2074 | as_warn (_("ignoring redefinition of register alias '%s'"), str); |
69b97547 | 2075 | |
d929913e | 2076 | return NULL; |
c19d1205 | 2077 | } |
b99bd4ef | 2078 | |
c19d1205 | 2079 | name = xstrdup (str); |
d3ce72d0 | 2080 | new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry)); |
b99bd4ef | 2081 | |
d3ce72d0 NC |
2082 | new_reg->name = name; |
2083 | new_reg->number = number; | |
2084 | new_reg->type = type; | |
2085 | new_reg->builtin = FALSE; | |
2086 | new_reg->neon = NULL; | |
b99bd4ef | 2087 | |
d3ce72d0 | 2088 | if (hash_insert (arm_reg_hsh, name, (void *) new_reg)) |
c19d1205 | 2089 | abort (); |
5f4273c7 | 2090 | |
d3ce72d0 | 2091 | return new_reg; |
dcbf9037 JB |
2092 | } |
2093 | ||
2094 | static void | |
2095 | insert_neon_reg_alias (char *str, int number, int type, | |
2096 | struct neon_typed_alias *atype) | |
2097 | { | |
2098 | struct reg_entry *reg = insert_reg_alias (str, number, type); | |
5f4273c7 | 2099 | |
dcbf9037 JB |
2100 | if (!reg) |
2101 | { | |
2102 | first_error (_("attempt to redefine typed alias")); | |
2103 | return; | |
2104 | } | |
5f4273c7 | 2105 | |
dcbf9037 JB |
2106 | if (atype) |
2107 | { | |
21d799b5 NC |
2108 | reg->neon = (struct neon_typed_alias *) |
2109 | xmalloc (sizeof (struct neon_typed_alias)); | |
dcbf9037 JB |
2110 | *reg->neon = *atype; |
2111 | } | |
c19d1205 | 2112 | } |
b99bd4ef | 2113 | |
c19d1205 | 2114 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 2115 | |
c19d1205 | 2116 | new_register_name .req existing_register_name |
b99bd4ef | 2117 | |
c19d1205 | 2118 | If we find one, or if it looks sufficiently like one that we want to |
d929913e | 2119 | handle any error here, return TRUE. Otherwise return FALSE. */ |
b99bd4ef | 2120 | |
d929913e | 2121 | static bfd_boolean |
c19d1205 ZW |
2122 | create_register_alias (char * newname, char *p) |
2123 | { | |
2124 | struct reg_entry *old; | |
2125 | char *oldname, *nbuf; | |
2126 | size_t nlen; | |
b99bd4ef | 2127 | |
c19d1205 ZW |
2128 | /* The input scrubber ensures that whitespace after the mnemonic is |
2129 | collapsed to single spaces. */ | |
2130 | oldname = p; | |
2131 | if (strncmp (oldname, " .req ", 6) != 0) | |
d929913e | 2132 | return FALSE; |
b99bd4ef | 2133 | |
c19d1205 ZW |
2134 | oldname += 6; |
2135 | if (*oldname == '\0') | |
d929913e | 2136 | return FALSE; |
b99bd4ef | 2137 | |
21d799b5 | 2138 | old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname); |
c19d1205 | 2139 | if (!old) |
b99bd4ef | 2140 | { |
c19d1205 | 2141 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
d929913e | 2142 | return TRUE; |
b99bd4ef NC |
2143 | } |
2144 | ||
c19d1205 ZW |
2145 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2146 | the desired alias name, and p points to its end. If not, then | |
2147 | the desired alias name is in the global original_case_string. */ | |
2148 | #ifdef TC_CASE_SENSITIVE | |
2149 | nlen = p - newname; | |
2150 | #else | |
2151 | newname = original_case_string; | |
2152 | nlen = strlen (newname); | |
2153 | #endif | |
b99bd4ef | 2154 | |
21d799b5 | 2155 | nbuf = (char *) alloca (nlen + 1); |
c19d1205 ZW |
2156 | memcpy (nbuf, newname, nlen); |
2157 | nbuf[nlen] = '\0'; | |
b99bd4ef | 2158 | |
c19d1205 ZW |
2159 | /* Create aliases under the new name as stated; an all-lowercase |
2160 | version of the new name; and an all-uppercase version of the new | |
2161 | name. */ | |
d929913e NC |
2162 | if (insert_reg_alias (nbuf, old->number, old->type) != NULL) |
2163 | { | |
2164 | for (p = nbuf; *p; p++) | |
2165 | *p = TOUPPER (*p); | |
c19d1205 | 2166 | |
d929913e NC |
2167 | if (strncmp (nbuf, newname, nlen)) |
2168 | { | |
2169 | /* If this attempt to create an additional alias fails, do not bother | |
2170 | trying to create the all-lower case alias. We will fail and issue | |
2171 | a second, duplicate error message. This situation arises when the | |
2172 | programmer does something like: | |
2173 | foo .req r0 | |
2174 | Foo .req r1 | |
2175 | The second .req creates the "Foo" alias but then fails to create | |
5f4273c7 | 2176 | the artificial FOO alias because it has already been created by the |
d929913e NC |
2177 | first .req. */ |
2178 | if (insert_reg_alias (nbuf, old->number, old->type) == NULL) | |
2179 | return TRUE; | |
2180 | } | |
c19d1205 | 2181 | |
d929913e NC |
2182 | for (p = nbuf; *p; p++) |
2183 | *p = TOLOWER (*p); | |
c19d1205 | 2184 | |
d929913e NC |
2185 | if (strncmp (nbuf, newname, nlen)) |
2186 | insert_reg_alias (nbuf, old->number, old->type); | |
2187 | } | |
c19d1205 | 2188 | |
d929913e | 2189 | return TRUE; |
b99bd4ef NC |
2190 | } |
2191 | ||
dcbf9037 JB |
2192 | /* Create a Neon typed/indexed register alias using directives, e.g.: |
2193 | X .dn d5.s32[1] | |
2194 | Y .qn 6.s16 | |
2195 | Z .dn d7 | |
2196 | T .dn Z[0] | |
2197 | These typed registers can be used instead of the types specified after the | |
2198 | Neon mnemonic, so long as all operands given have types. Types can also be | |
2199 | specified directly, e.g.: | |
5f4273c7 | 2200 | vadd d0.s32, d1.s32, d2.s32 */ |
dcbf9037 | 2201 | |
c921be7d | 2202 | static bfd_boolean |
dcbf9037 JB |
2203 | create_neon_reg_alias (char *newname, char *p) |
2204 | { | |
2205 | enum arm_reg_type basetype; | |
2206 | struct reg_entry *basereg; | |
2207 | struct reg_entry mybasereg; | |
2208 | struct neon_type ntype; | |
2209 | struct neon_typed_alias typeinfo; | |
2210 | char *namebuf, *nameend; | |
2211 | int namelen; | |
5f4273c7 | 2212 | |
dcbf9037 JB |
2213 | typeinfo.defined = 0; |
2214 | typeinfo.eltype.type = NT_invtype; | |
2215 | typeinfo.eltype.size = -1; | |
2216 | typeinfo.index = -1; | |
5f4273c7 | 2217 | |
dcbf9037 | 2218 | nameend = p; |
5f4273c7 | 2219 | |
dcbf9037 JB |
2220 | if (strncmp (p, " .dn ", 5) == 0) |
2221 | basetype = REG_TYPE_VFD; | |
2222 | else if (strncmp (p, " .qn ", 5) == 0) | |
2223 | basetype = REG_TYPE_NQ; | |
2224 | else | |
c921be7d | 2225 | return FALSE; |
5f4273c7 | 2226 | |
dcbf9037 | 2227 | p += 5; |
5f4273c7 | 2228 | |
dcbf9037 | 2229 | if (*p == '\0') |
c921be7d | 2230 | return FALSE; |
5f4273c7 | 2231 | |
dcbf9037 JB |
2232 | basereg = arm_reg_parse_multi (&p); |
2233 | ||
2234 | if (basereg && basereg->type != basetype) | |
2235 | { | |
2236 | as_bad (_("bad type for register")); | |
c921be7d | 2237 | return FALSE; |
dcbf9037 JB |
2238 | } |
2239 | ||
2240 | if (basereg == NULL) | |
2241 | { | |
2242 | expressionS exp; | |
2243 | /* Try parsing as an integer. */ | |
2244 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
2245 | if (exp.X_op != O_constant) | |
2246 | { | |
2247 | as_bad (_("expression must be constant")); | |
c921be7d | 2248 | return FALSE; |
dcbf9037 JB |
2249 | } |
2250 | basereg = &mybasereg; | |
2251 | basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 | |
2252 | : exp.X_add_number; | |
2253 | basereg->neon = 0; | |
2254 | } | |
2255 | ||
2256 | if (basereg->neon) | |
2257 | typeinfo = *basereg->neon; | |
2258 | ||
2259 | if (parse_neon_type (&ntype, &p) == SUCCESS) | |
2260 | { | |
2261 | /* We got a type. */ | |
2262 | if (typeinfo.defined & NTA_HASTYPE) | |
2263 | { | |
2264 | as_bad (_("can't redefine the type of a register alias")); | |
c921be7d | 2265 | return FALSE; |
dcbf9037 | 2266 | } |
5f4273c7 | 2267 | |
dcbf9037 JB |
2268 | typeinfo.defined |= NTA_HASTYPE; |
2269 | if (ntype.elems != 1) | |
2270 | { | |
2271 | as_bad (_("you must specify a single type only")); | |
c921be7d | 2272 | return FALSE; |
dcbf9037 JB |
2273 | } |
2274 | typeinfo.eltype = ntype.el[0]; | |
2275 | } | |
5f4273c7 | 2276 | |
dcbf9037 JB |
2277 | if (skip_past_char (&p, '[') == SUCCESS) |
2278 | { | |
2279 | expressionS exp; | |
2280 | /* We got a scalar index. */ | |
5f4273c7 | 2281 | |
dcbf9037 JB |
2282 | if (typeinfo.defined & NTA_HASINDEX) |
2283 | { | |
2284 | as_bad (_("can't redefine the index of a scalar alias")); | |
c921be7d | 2285 | return FALSE; |
dcbf9037 | 2286 | } |
5f4273c7 | 2287 | |
dcbf9037 | 2288 | my_get_expression (&exp, &p, GE_NO_PREFIX); |
5f4273c7 | 2289 | |
dcbf9037 JB |
2290 | if (exp.X_op != O_constant) |
2291 | { | |
2292 | as_bad (_("scalar index must be constant")); | |
c921be7d | 2293 | return FALSE; |
dcbf9037 | 2294 | } |
5f4273c7 | 2295 | |
dcbf9037 JB |
2296 | typeinfo.defined |= NTA_HASINDEX; |
2297 | typeinfo.index = exp.X_add_number; | |
5f4273c7 | 2298 | |
dcbf9037 JB |
2299 | if (skip_past_char (&p, ']') == FAIL) |
2300 | { | |
2301 | as_bad (_("expecting ]")); | |
c921be7d | 2302 | return FALSE; |
dcbf9037 JB |
2303 | } |
2304 | } | |
2305 | ||
15735687 NS |
2306 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2307 | the desired alias name, and p points to its end. If not, then | |
2308 | the desired alias name is in the global original_case_string. */ | |
2309 | #ifdef TC_CASE_SENSITIVE | |
dcbf9037 | 2310 | namelen = nameend - newname; |
15735687 NS |
2311 | #else |
2312 | newname = original_case_string; | |
2313 | namelen = strlen (newname); | |
2314 | #endif | |
2315 | ||
21d799b5 | 2316 | namebuf = (char *) alloca (namelen + 1); |
dcbf9037 JB |
2317 | strncpy (namebuf, newname, namelen); |
2318 | namebuf[namelen] = '\0'; | |
5f4273c7 | 2319 | |
dcbf9037 JB |
2320 | insert_neon_reg_alias (namebuf, basereg->number, basetype, |
2321 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2322 | |
dcbf9037 JB |
2323 | /* Insert name in all uppercase. */ |
2324 | for (p = namebuf; *p; p++) | |
2325 | *p = TOUPPER (*p); | |
5f4273c7 | 2326 | |
dcbf9037 JB |
2327 | if (strncmp (namebuf, newname, namelen)) |
2328 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2329 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2330 | |
dcbf9037 JB |
2331 | /* Insert name in all lowercase. */ |
2332 | for (p = namebuf; *p; p++) | |
2333 | *p = TOLOWER (*p); | |
5f4273c7 | 2334 | |
dcbf9037 JB |
2335 | if (strncmp (namebuf, newname, namelen)) |
2336 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2337 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2338 | |
c921be7d | 2339 | return TRUE; |
dcbf9037 JB |
2340 | } |
2341 | ||
c19d1205 ZW |
2342 | /* Should never be called, as .req goes between the alias and the |
2343 | register name, not at the beginning of the line. */ | |
c921be7d | 2344 | |
b99bd4ef | 2345 | static void |
c19d1205 | 2346 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2347 | { |
c19d1205 ZW |
2348 | as_bad (_("invalid syntax for .req directive")); |
2349 | } | |
b99bd4ef | 2350 | |
dcbf9037 JB |
2351 | static void |
2352 | s_dn (int a ATTRIBUTE_UNUSED) | |
2353 | { | |
2354 | as_bad (_("invalid syntax for .dn directive")); | |
2355 | } | |
2356 | ||
2357 | static void | |
2358 | s_qn (int a ATTRIBUTE_UNUSED) | |
2359 | { | |
2360 | as_bad (_("invalid syntax for .qn directive")); | |
2361 | } | |
2362 | ||
c19d1205 ZW |
2363 | /* The .unreq directive deletes an alias which was previously defined |
2364 | by .req. For example: | |
b99bd4ef | 2365 | |
c19d1205 ZW |
2366 | my_alias .req r11 |
2367 | .unreq my_alias */ | |
b99bd4ef NC |
2368 | |
2369 | static void | |
c19d1205 | 2370 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2371 | { |
c19d1205 ZW |
2372 | char * name; |
2373 | char saved_char; | |
b99bd4ef | 2374 | |
c19d1205 ZW |
2375 | name = input_line_pointer; |
2376 | ||
2377 | while (*input_line_pointer != 0 | |
2378 | && *input_line_pointer != ' ' | |
2379 | && *input_line_pointer != '\n') | |
2380 | ++input_line_pointer; | |
2381 | ||
2382 | saved_char = *input_line_pointer; | |
2383 | *input_line_pointer = 0; | |
2384 | ||
2385 | if (!*name) | |
2386 | as_bad (_("invalid syntax for .unreq directive")); | |
2387 | else | |
2388 | { | |
21d799b5 NC |
2389 | struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh, |
2390 | name); | |
c19d1205 ZW |
2391 | |
2392 | if (!reg) | |
2393 | as_bad (_("unknown register alias '%s'"), name); | |
2394 | else if (reg->builtin) | |
2395 | as_warn (_("ignoring attempt to undefine built-in register '%s'"), | |
2396 | name); | |
2397 | else | |
2398 | { | |
d929913e NC |
2399 | char * p; |
2400 | char * nbuf; | |
2401 | ||
db0bc284 | 2402 | hash_delete (arm_reg_hsh, name, FALSE); |
c19d1205 | 2403 | free ((char *) reg->name); |
dcbf9037 JB |
2404 | if (reg->neon) |
2405 | free (reg->neon); | |
c19d1205 | 2406 | free (reg); |
d929913e NC |
2407 | |
2408 | /* Also locate the all upper case and all lower case versions. | |
2409 | Do not complain if we cannot find one or the other as it | |
2410 | was probably deleted above. */ | |
5f4273c7 | 2411 | |
d929913e NC |
2412 | nbuf = strdup (name); |
2413 | for (p = nbuf; *p; p++) | |
2414 | *p = TOUPPER (*p); | |
21d799b5 | 2415 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2416 | if (reg) |
2417 | { | |
db0bc284 | 2418 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2419 | free ((char *) reg->name); |
2420 | if (reg->neon) | |
2421 | free (reg->neon); | |
2422 | free (reg); | |
2423 | } | |
2424 | ||
2425 | for (p = nbuf; *p; p++) | |
2426 | *p = TOLOWER (*p); | |
21d799b5 | 2427 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2428 | if (reg) |
2429 | { | |
db0bc284 | 2430 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2431 | free ((char *) reg->name); |
2432 | if (reg->neon) | |
2433 | free (reg->neon); | |
2434 | free (reg); | |
2435 | } | |
2436 | ||
2437 | free (nbuf); | |
c19d1205 ZW |
2438 | } |
2439 | } | |
b99bd4ef | 2440 | |
c19d1205 | 2441 | *input_line_pointer = saved_char; |
b99bd4ef NC |
2442 | demand_empty_rest_of_line (); |
2443 | } | |
2444 | ||
c19d1205 ZW |
2445 | /* Directives: Instruction set selection. */ |
2446 | ||
2447 | #ifdef OBJ_ELF | |
2448 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
2449 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
2450 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
2451 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
2452 | ||
cd000bff DJ |
2453 | /* Create a new mapping symbol for the transition to STATE. */ |
2454 | ||
2455 | static void | |
2456 | make_mapping_symbol (enum mstate state, valueT value, fragS *frag) | |
b99bd4ef | 2457 | { |
a737bd4d | 2458 | symbolS * symbolP; |
c19d1205 ZW |
2459 | const char * symname; |
2460 | int type; | |
b99bd4ef | 2461 | |
c19d1205 | 2462 | switch (state) |
b99bd4ef | 2463 | { |
c19d1205 ZW |
2464 | case MAP_DATA: |
2465 | symname = "$d"; | |
2466 | type = BSF_NO_FLAGS; | |
2467 | break; | |
2468 | case MAP_ARM: | |
2469 | symname = "$a"; | |
2470 | type = BSF_NO_FLAGS; | |
2471 | break; | |
2472 | case MAP_THUMB: | |
2473 | symname = "$t"; | |
2474 | type = BSF_NO_FLAGS; | |
2475 | break; | |
c19d1205 ZW |
2476 | default: |
2477 | abort (); | |
2478 | } | |
2479 | ||
cd000bff | 2480 | symbolP = symbol_new (symname, now_seg, value, frag); |
c19d1205 ZW |
2481 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; |
2482 | ||
2483 | switch (state) | |
2484 | { | |
2485 | case MAP_ARM: | |
2486 | THUMB_SET_FUNC (symbolP, 0); | |
2487 | ARM_SET_THUMB (symbolP, 0); | |
2488 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2489 | break; | |
2490 | ||
2491 | case MAP_THUMB: | |
2492 | THUMB_SET_FUNC (symbolP, 1); | |
2493 | ARM_SET_THUMB (symbolP, 1); | |
2494 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2495 | break; | |
2496 | ||
2497 | case MAP_DATA: | |
2498 | default: | |
cd000bff DJ |
2499 | break; |
2500 | } | |
2501 | ||
2502 | /* Save the mapping symbols for future reference. Also check that | |
2503 | we do not place two mapping symbols at the same offset within a | |
2504 | frag. We'll handle overlap between frags in | |
2de7820f JZ |
2505 | check_mapping_symbols. |
2506 | ||
2507 | If .fill or other data filling directive generates zero sized data, | |
2508 | the mapping symbol for the following code will have the same value | |
2509 | as the one generated for the data filling directive. In this case, | |
2510 | we replace the old symbol with the new one at the same address. */ | |
cd000bff DJ |
2511 | if (value == 0) |
2512 | { | |
2de7820f JZ |
2513 | if (frag->tc_frag_data.first_map != NULL) |
2514 | { | |
2515 | know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0); | |
2516 | symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP); | |
2517 | } | |
cd000bff DJ |
2518 | frag->tc_frag_data.first_map = symbolP; |
2519 | } | |
2520 | if (frag->tc_frag_data.last_map != NULL) | |
0f020cef JZ |
2521 | { |
2522 | know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP)); | |
0f020cef JZ |
2523 | if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP)) |
2524 | symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP); | |
2525 | } | |
cd000bff DJ |
2526 | frag->tc_frag_data.last_map = symbolP; |
2527 | } | |
2528 | ||
2529 | /* We must sometimes convert a region marked as code to data during | |
2530 | code alignment, if an odd number of bytes have to be padded. The | |
2531 | code mapping symbol is pushed to an aligned address. */ | |
2532 | ||
2533 | static void | |
2534 | insert_data_mapping_symbol (enum mstate state, | |
2535 | valueT value, fragS *frag, offsetT bytes) | |
2536 | { | |
2537 | /* If there was already a mapping symbol, remove it. */ | |
2538 | if (frag->tc_frag_data.last_map != NULL | |
2539 | && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value) | |
2540 | { | |
2541 | symbolS *symp = frag->tc_frag_data.last_map; | |
2542 | ||
2543 | if (value == 0) | |
2544 | { | |
2545 | know (frag->tc_frag_data.first_map == symp); | |
2546 | frag->tc_frag_data.first_map = NULL; | |
2547 | } | |
2548 | frag->tc_frag_data.last_map = NULL; | |
2549 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
c19d1205 | 2550 | } |
cd000bff DJ |
2551 | |
2552 | make_mapping_symbol (MAP_DATA, value, frag); | |
2553 | make_mapping_symbol (state, value + bytes, frag); | |
2554 | } | |
2555 | ||
2556 | static void mapping_state_2 (enum mstate state, int max_chars); | |
2557 | ||
2558 | /* Set the mapping state to STATE. Only call this when about to | |
2559 | emit some STATE bytes to the file. */ | |
2560 | ||
2561 | void | |
2562 | mapping_state (enum mstate state) | |
2563 | { | |
940b5ce0 DJ |
2564 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2565 | ||
cd000bff DJ |
2566 | #define TRANSITION(from, to) (mapstate == (from) && state == (to)) |
2567 | ||
2568 | if (mapstate == state) | |
2569 | /* The mapping symbol has already been emitted. | |
2570 | There is nothing else to do. */ | |
2571 | return; | |
2572 | else if (TRANSITION (MAP_UNDEFINED, MAP_DATA)) | |
2573 | /* This case will be evaluated later in the next else. */ | |
2574 | return; | |
2575 | else if (TRANSITION (MAP_UNDEFINED, MAP_ARM) | |
2576 | || TRANSITION (MAP_UNDEFINED, MAP_THUMB)) | |
2577 | { | |
2578 | /* Only add the symbol if the offset is > 0: | |
2579 | if we're at the first frag, check it's size > 0; | |
2580 | if we're not at the first frag, then for sure | |
2581 | the offset is > 0. */ | |
2582 | struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root; | |
2583 | const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0); | |
2584 | ||
2585 | if (add_symbol) | |
2586 | make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); | |
2587 | } | |
2588 | ||
2589 | mapping_state_2 (state, 0); | |
2590 | #undef TRANSITION | |
2591 | } | |
2592 | ||
2593 | /* Same as mapping_state, but MAX_CHARS bytes have already been | |
2594 | allocated. Put the mapping symbol that far back. */ | |
2595 | ||
2596 | static void | |
2597 | mapping_state_2 (enum mstate state, int max_chars) | |
2598 | { | |
940b5ce0 DJ |
2599 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2600 | ||
2601 | if (!SEG_NORMAL (now_seg)) | |
2602 | return; | |
2603 | ||
cd000bff DJ |
2604 | if (mapstate == state) |
2605 | /* The mapping symbol has already been emitted. | |
2606 | There is nothing else to do. */ | |
2607 | return; | |
2608 | ||
cd000bff DJ |
2609 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; |
2610 | make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); | |
c19d1205 ZW |
2611 | } |
2612 | #else | |
d3106081 NS |
2613 | #define mapping_state(x) ((void)0) |
2614 | #define mapping_state_2(x, y) ((void)0) | |
c19d1205 ZW |
2615 | #endif |
2616 | ||
2617 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
2618 | ||
4343666d | 2619 | #ifdef OBJ_COFF |
c19d1205 ZW |
2620 | static symbolS * |
2621 | find_real_start (symbolS * symbolP) | |
2622 | { | |
2623 | char * real_start; | |
2624 | const char * name = S_GET_NAME (symbolP); | |
2625 | symbolS * new_target; | |
2626 | ||
2627 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
2628 | #define STUB_NAME ".real_start_of" | |
2629 | ||
2630 | if (name == NULL) | |
2631 | abort (); | |
2632 | ||
37f6032b ZW |
2633 | /* The compiler may generate BL instructions to local labels because |
2634 | it needs to perform a branch to a far away location. These labels | |
2635 | do not have a corresponding ".real_start_of" label. We check | |
2636 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
2637 | the ".real_start_of" convention for nonlocal branches. */ | |
2638 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
2639 | return symbolP; |
2640 | ||
37f6032b | 2641 | real_start = ACONCAT ((STUB_NAME, name, NULL)); |
c19d1205 ZW |
2642 | new_target = symbol_find (real_start); |
2643 | ||
2644 | if (new_target == NULL) | |
2645 | { | |
bd3ba5d1 | 2646 | as_warn (_("Failed to find real start of function: %s\n"), name); |
c19d1205 ZW |
2647 | new_target = symbolP; |
2648 | } | |
2649 | ||
c19d1205 ZW |
2650 | return new_target; |
2651 | } | |
4343666d | 2652 | #endif |
c19d1205 ZW |
2653 | |
2654 | static void | |
2655 | opcode_select (int width) | |
2656 | { | |
2657 | switch (width) | |
2658 | { | |
2659 | case 16: | |
2660 | if (! thumb_mode) | |
2661 | { | |
e74cfd16 | 2662 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
c19d1205 ZW |
2663 | as_bad (_("selected processor does not support THUMB opcodes")); |
2664 | ||
2665 | thumb_mode = 1; | |
2666 | /* No need to force the alignment, since we will have been | |
2667 | coming from ARM mode, which is word-aligned. */ | |
2668 | record_alignment (now_seg, 1); | |
2669 | } | |
c19d1205 ZW |
2670 | break; |
2671 | ||
2672 | case 32: | |
2673 | if (thumb_mode) | |
2674 | { | |
e74cfd16 | 2675 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 ZW |
2676 | as_bad (_("selected processor does not support ARM opcodes")); |
2677 | ||
2678 | thumb_mode = 0; | |
2679 | ||
2680 | if (!need_pass_2) | |
2681 | frag_align (2, 0, 0); | |
2682 | ||
2683 | record_alignment (now_seg, 1); | |
2684 | } | |
c19d1205 ZW |
2685 | break; |
2686 | ||
2687 | default: | |
2688 | as_bad (_("invalid instruction size selected (%d)"), width); | |
2689 | } | |
2690 | } | |
2691 | ||
2692 | static void | |
2693 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
2694 | { | |
2695 | opcode_select (32); | |
2696 | demand_empty_rest_of_line (); | |
2697 | } | |
2698 | ||
2699 | static void | |
2700 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
2701 | { | |
2702 | opcode_select (16); | |
2703 | demand_empty_rest_of_line (); | |
2704 | } | |
2705 | ||
2706 | static void | |
2707 | s_code (int unused ATTRIBUTE_UNUSED) | |
2708 | { | |
2709 | int temp; | |
2710 | ||
2711 | temp = get_absolute_expression (); | |
2712 | switch (temp) | |
2713 | { | |
2714 | case 16: | |
2715 | case 32: | |
2716 | opcode_select (temp); | |
2717 | break; | |
2718 | ||
2719 | default: | |
2720 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
2721 | } | |
2722 | } | |
2723 | ||
2724 | static void | |
2725 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
2726 | { | |
2727 | /* If we are not already in thumb mode go into it, EVEN if | |
2728 | the target processor does not support thumb instructions. | |
2729 | This is used by gcc/config/arm/lib1funcs.asm for example | |
2730 | to compile interworking support functions even if the | |
2731 | target processor should not support interworking. */ | |
2732 | if (! thumb_mode) | |
2733 | { | |
2734 | thumb_mode = 2; | |
2735 | record_alignment (now_seg, 1); | |
2736 | } | |
2737 | ||
2738 | demand_empty_rest_of_line (); | |
2739 | } | |
2740 | ||
2741 | static void | |
2742 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
2743 | { | |
2744 | s_thumb (0); | |
2745 | ||
2746 | /* The following label is the name/address of the start of a Thumb function. | |
2747 | We need to know this for the interworking support. */ | |
2748 | label_is_thumb_function_name = TRUE; | |
2749 | } | |
2750 | ||
2751 | /* Perform a .set directive, but also mark the alias as | |
2752 | being a thumb function. */ | |
2753 | ||
2754 | static void | |
2755 | s_thumb_set (int equiv) | |
2756 | { | |
2757 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
2758 | We cannot just call that code as we need to get at the symbol that | |
2759 | is created. */ | |
2760 | char * name; | |
2761 | char delim; | |
2762 | char * end_name; | |
2763 | symbolS * symbolP; | |
2764 | ||
2765 | /* Especial apologies for the random logic: | |
2766 | This just grew, and could be parsed much more simply! | |
2767 | Dean - in haste. */ | |
2768 | name = input_line_pointer; | |
2769 | delim = get_symbol_end (); | |
2770 | end_name = input_line_pointer; | |
2771 | *end_name = delim; | |
2772 | ||
2773 | if (*input_line_pointer != ',') | |
2774 | { | |
2775 | *end_name = 0; | |
2776 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
2777 | *end_name = delim; |
2778 | ignore_rest_of_line (); | |
2779 | return; | |
2780 | } | |
2781 | ||
2782 | input_line_pointer++; | |
2783 | *end_name = 0; | |
2784 | ||
2785 | if (name[0] == '.' && name[1] == '\0') | |
2786 | { | |
2787 | /* XXX - this should not happen to .thumb_set. */ | |
2788 | abort (); | |
2789 | } | |
2790 | ||
2791 | if ((symbolP = symbol_find (name)) == NULL | |
2792 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
2793 | { | |
2794 | #ifndef NO_LISTING | |
2795 | /* When doing symbol listings, play games with dummy fragments living | |
2796 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 2797 | for this symbol. */ |
b99bd4ef NC |
2798 | if (listing & LISTING_SYMBOLS) |
2799 | { | |
2800 | extern struct list_info_struct * listing_tail; | |
21d799b5 | 2801 | fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS)); |
b99bd4ef NC |
2802 | |
2803 | memset (dummy_frag, 0, sizeof (fragS)); | |
2804 | dummy_frag->fr_type = rs_fill; | |
2805 | dummy_frag->line = listing_tail; | |
2806 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
2807 | dummy_frag->fr_symbol = symbolP; | |
2808 | } | |
2809 | else | |
2810 | #endif | |
2811 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
2812 | ||
2813 | #ifdef OBJ_COFF | |
2814 | /* "set" symbols are local unless otherwise specified. */ | |
2815 | SF_SET_LOCAL (symbolP); | |
2816 | #endif /* OBJ_COFF */ | |
2817 | } /* Make a new symbol. */ | |
2818 | ||
2819 | symbol_table_insert (symbolP); | |
2820 | ||
2821 | * end_name = delim; | |
2822 | ||
2823 | if (equiv | |
2824 | && S_IS_DEFINED (symbolP) | |
2825 | && S_GET_SEGMENT (symbolP) != reg_section) | |
2826 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
2827 | ||
2828 | pseudo_set (symbolP); | |
2829 | ||
2830 | demand_empty_rest_of_line (); | |
2831 | ||
c19d1205 | 2832 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
2833 | |
2834 | THUMB_SET_FUNC (symbolP, 1); | |
2835 | ARM_SET_THUMB (symbolP, 1); | |
2836 | #if defined OBJ_ELF || defined OBJ_COFF | |
2837 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2838 | #endif | |
2839 | } | |
2840 | ||
c19d1205 | 2841 | /* Directives: Mode selection. */ |
b99bd4ef | 2842 | |
c19d1205 ZW |
2843 | /* .syntax [unified|divided] - choose the new unified syntax |
2844 | (same for Arm and Thumb encoding, modulo slight differences in what | |
2845 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 2846 | static void |
c19d1205 | 2847 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2848 | { |
c19d1205 ZW |
2849 | char *name, delim; |
2850 | ||
2851 | name = input_line_pointer; | |
2852 | delim = get_symbol_end (); | |
2853 | ||
2854 | if (!strcasecmp (name, "unified")) | |
2855 | unified_syntax = TRUE; | |
2856 | else if (!strcasecmp (name, "divided")) | |
2857 | unified_syntax = FALSE; | |
2858 | else | |
2859 | { | |
2860 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
2861 | return; | |
2862 | } | |
2863 | *input_line_pointer = delim; | |
b99bd4ef NC |
2864 | demand_empty_rest_of_line (); |
2865 | } | |
2866 | ||
c19d1205 ZW |
2867 | /* Directives: sectioning and alignment. */ |
2868 | ||
2869 | /* Same as s_align_ptwo but align 0 => align 2. */ | |
2870 | ||
b99bd4ef | 2871 | static void |
c19d1205 | 2872 | s_align (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2873 | { |
a737bd4d | 2874 | int temp; |
dce323d1 | 2875 | bfd_boolean fill_p; |
c19d1205 ZW |
2876 | long temp_fill; |
2877 | long max_alignment = 15; | |
b99bd4ef NC |
2878 | |
2879 | temp = get_absolute_expression (); | |
c19d1205 ZW |
2880 | if (temp > max_alignment) |
2881 | as_bad (_("alignment too large: %d assumed"), temp = max_alignment); | |
2882 | else if (temp < 0) | |
b99bd4ef | 2883 | { |
c19d1205 ZW |
2884 | as_bad (_("alignment negative. 0 assumed.")); |
2885 | temp = 0; | |
2886 | } | |
b99bd4ef | 2887 | |
c19d1205 ZW |
2888 | if (*input_line_pointer == ',') |
2889 | { | |
2890 | input_line_pointer++; | |
2891 | temp_fill = get_absolute_expression (); | |
dce323d1 | 2892 | fill_p = TRUE; |
b99bd4ef | 2893 | } |
c19d1205 | 2894 | else |
dce323d1 PB |
2895 | { |
2896 | fill_p = FALSE; | |
2897 | temp_fill = 0; | |
2898 | } | |
b99bd4ef | 2899 | |
c19d1205 ZW |
2900 | if (!temp) |
2901 | temp = 2; | |
b99bd4ef | 2902 | |
c19d1205 ZW |
2903 | /* Only make a frag if we HAVE to. */ |
2904 | if (temp && !need_pass_2) | |
dce323d1 PB |
2905 | { |
2906 | if (!fill_p && subseg_text_p (now_seg)) | |
2907 | frag_align_code (temp, 0); | |
2908 | else | |
2909 | frag_align (temp, (int) temp_fill, 0); | |
2910 | } | |
c19d1205 ZW |
2911 | demand_empty_rest_of_line (); |
2912 | ||
2913 | record_alignment (now_seg, temp); | |
b99bd4ef NC |
2914 | } |
2915 | ||
c19d1205 ZW |
2916 | static void |
2917 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 2918 | { |
c19d1205 ZW |
2919 | /* We don't support putting frags in the BSS segment, we fake it by |
2920 | marking in_bss, then looking at s_skip for clues. */ | |
2921 | subseg_set (bss_section, 0); | |
2922 | demand_empty_rest_of_line (); | |
cd000bff DJ |
2923 | |
2924 | #ifdef md_elf_section_change_hook | |
2925 | md_elf_section_change_hook (); | |
2926 | #endif | |
c19d1205 | 2927 | } |
b99bd4ef | 2928 | |
c19d1205 ZW |
2929 | static void |
2930 | s_even (int ignore ATTRIBUTE_UNUSED) | |
2931 | { | |
2932 | /* Never make frag if expect extra pass. */ | |
2933 | if (!need_pass_2) | |
2934 | frag_align (1, 0, 0); | |
b99bd4ef | 2935 | |
c19d1205 | 2936 | record_alignment (now_seg, 1); |
b99bd4ef | 2937 | |
c19d1205 | 2938 | demand_empty_rest_of_line (); |
b99bd4ef NC |
2939 | } |
2940 | ||
c19d1205 | 2941 | /* Directives: Literal pools. */ |
a737bd4d | 2942 | |
c19d1205 ZW |
2943 | static literal_pool * |
2944 | find_literal_pool (void) | |
a737bd4d | 2945 | { |
c19d1205 | 2946 | literal_pool * pool; |
a737bd4d | 2947 | |
c19d1205 | 2948 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 2949 | { |
c19d1205 ZW |
2950 | if (pool->section == now_seg |
2951 | && pool->sub_section == now_subseg) | |
2952 | break; | |
a737bd4d NC |
2953 | } |
2954 | ||
c19d1205 | 2955 | return pool; |
a737bd4d NC |
2956 | } |
2957 | ||
c19d1205 ZW |
2958 | static literal_pool * |
2959 | find_or_make_literal_pool (void) | |
a737bd4d | 2960 | { |
c19d1205 ZW |
2961 | /* Next literal pool ID number. */ |
2962 | static unsigned int latest_pool_num = 1; | |
2963 | literal_pool * pool; | |
a737bd4d | 2964 | |
c19d1205 | 2965 | pool = find_literal_pool (); |
a737bd4d | 2966 | |
c19d1205 | 2967 | if (pool == NULL) |
a737bd4d | 2968 | { |
c19d1205 | 2969 | /* Create a new pool. */ |
21d799b5 | 2970 | pool = (literal_pool *) xmalloc (sizeof (* pool)); |
c19d1205 ZW |
2971 | if (! pool) |
2972 | return NULL; | |
a737bd4d | 2973 | |
c19d1205 ZW |
2974 | pool->next_free_entry = 0; |
2975 | pool->section = now_seg; | |
2976 | pool->sub_section = now_subseg; | |
2977 | pool->next = list_of_pools; | |
2978 | pool->symbol = NULL; | |
2979 | ||
2980 | /* Add it to the list. */ | |
2981 | list_of_pools = pool; | |
a737bd4d | 2982 | } |
a737bd4d | 2983 | |
c19d1205 ZW |
2984 | /* New pools, and emptied pools, will have a NULL symbol. */ |
2985 | if (pool->symbol == NULL) | |
a737bd4d | 2986 | { |
c19d1205 ZW |
2987 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
2988 | (valueT) 0, &zero_address_frag); | |
2989 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
2990 | } |
2991 | ||
c19d1205 ZW |
2992 | /* Done. */ |
2993 | return pool; | |
a737bd4d NC |
2994 | } |
2995 | ||
c19d1205 | 2996 | /* Add the literal in the global 'inst' |
5f4273c7 | 2997 | structure to the relevant literal pool. */ |
b99bd4ef NC |
2998 | |
2999 | static int | |
c19d1205 | 3000 | add_to_lit_pool (void) |
b99bd4ef | 3001 | { |
c19d1205 ZW |
3002 | literal_pool * pool; |
3003 | unsigned int entry; | |
b99bd4ef | 3004 | |
c19d1205 ZW |
3005 | pool = find_or_make_literal_pool (); |
3006 | ||
3007 | /* Check if this literal value is already in the pool. */ | |
3008 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 3009 | { |
c19d1205 ZW |
3010 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) |
3011 | && (inst.reloc.exp.X_op == O_constant) | |
3012 | && (pool->literals[entry].X_add_number | |
3013 | == inst.reloc.exp.X_add_number) | |
3014 | && (pool->literals[entry].X_unsigned | |
3015 | == inst.reloc.exp.X_unsigned)) | |
3016 | break; | |
3017 | ||
3018 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
3019 | && (inst.reloc.exp.X_op == O_symbol) | |
3020 | && (pool->literals[entry].X_add_number | |
3021 | == inst.reloc.exp.X_add_number) | |
3022 | && (pool->literals[entry].X_add_symbol | |
3023 | == inst.reloc.exp.X_add_symbol) | |
3024 | && (pool->literals[entry].X_op_symbol | |
3025 | == inst.reloc.exp.X_op_symbol)) | |
3026 | break; | |
b99bd4ef NC |
3027 | } |
3028 | ||
c19d1205 ZW |
3029 | /* Do we need to create a new entry? */ |
3030 | if (entry == pool->next_free_entry) | |
3031 | { | |
3032 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
3033 | { | |
3034 | inst.error = _("literal pool overflow"); | |
3035 | return FAIL; | |
3036 | } | |
3037 | ||
3038 | pool->literals[entry] = inst.reloc.exp; | |
3039 | pool->next_free_entry += 1; | |
3040 | } | |
b99bd4ef | 3041 | |
c19d1205 ZW |
3042 | inst.reloc.exp.X_op = O_symbol; |
3043 | inst.reloc.exp.X_add_number = ((int) entry) * 4; | |
3044 | inst.reloc.exp.X_add_symbol = pool->symbol; | |
b99bd4ef | 3045 | |
c19d1205 | 3046 | return SUCCESS; |
b99bd4ef NC |
3047 | } |
3048 | ||
c19d1205 ZW |
3049 | /* Can't use symbol_new here, so have to create a symbol and then at |
3050 | a later date assign it a value. Thats what these functions do. */ | |
e16bb312 | 3051 | |
c19d1205 ZW |
3052 | static void |
3053 | symbol_locate (symbolS * symbolP, | |
3054 | const char * name, /* It is copied, the caller can modify. */ | |
3055 | segT segment, /* Segment identifier (SEG_<something>). */ | |
3056 | valueT valu, /* Symbol value. */ | |
3057 | fragS * frag) /* Associated fragment. */ | |
3058 | { | |
3059 | unsigned int name_length; | |
3060 | char * preserved_copy_of_name; | |
e16bb312 | 3061 | |
c19d1205 ZW |
3062 | name_length = strlen (name) + 1; /* +1 for \0. */ |
3063 | obstack_grow (¬es, name, name_length); | |
21d799b5 | 3064 | preserved_copy_of_name = (char *) obstack_finish (¬es); |
e16bb312 | 3065 | |
c19d1205 ZW |
3066 | #ifdef tc_canonicalize_symbol_name |
3067 | preserved_copy_of_name = | |
3068 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
3069 | #endif | |
b99bd4ef | 3070 | |
c19d1205 | 3071 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 3072 | |
c19d1205 ZW |
3073 | S_SET_SEGMENT (symbolP, segment); |
3074 | S_SET_VALUE (symbolP, valu); | |
3075 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 3076 | |
c19d1205 | 3077 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 3078 | |
c19d1205 ZW |
3079 | /* Link to end of symbol chain. */ |
3080 | { | |
3081 | extern int symbol_table_frozen; | |
b99bd4ef | 3082 | |
c19d1205 ZW |
3083 | if (symbol_table_frozen) |
3084 | abort (); | |
3085 | } | |
b99bd4ef | 3086 | |
c19d1205 | 3087 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 3088 | |
c19d1205 | 3089 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 3090 | |
c19d1205 ZW |
3091 | #ifdef tc_symbol_new_hook |
3092 | tc_symbol_new_hook (symbolP); | |
3093 | #endif | |
3094 | ||
3095 | #ifdef DEBUG_SYMS | |
3096 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
3097 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
3098 | } |
3099 | ||
b99bd4ef | 3100 | |
c19d1205 ZW |
3101 | static void |
3102 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 3103 | { |
c19d1205 ZW |
3104 | unsigned int entry; |
3105 | literal_pool * pool; | |
3106 | char sym_name[20]; | |
b99bd4ef | 3107 | |
c19d1205 ZW |
3108 | pool = find_literal_pool (); |
3109 | if (pool == NULL | |
3110 | || pool->symbol == NULL | |
3111 | || pool->next_free_entry == 0) | |
3112 | return; | |
b99bd4ef | 3113 | |
c19d1205 | 3114 | mapping_state (MAP_DATA); |
b99bd4ef | 3115 | |
c19d1205 ZW |
3116 | /* Align pool as you have word accesses. |
3117 | Only make a frag if we have to. */ | |
3118 | if (!need_pass_2) | |
3119 | frag_align (2, 0, 0); | |
b99bd4ef | 3120 | |
c19d1205 | 3121 | record_alignment (now_seg, 2); |
b99bd4ef | 3122 | |
c19d1205 | 3123 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 3124 | |
c19d1205 ZW |
3125 | symbol_locate (pool->symbol, sym_name, now_seg, |
3126 | (valueT) frag_now_fix (), frag_now); | |
3127 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 3128 | |
c19d1205 | 3129 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 3130 | |
c19d1205 ZW |
3131 | #if defined OBJ_COFF || defined OBJ_ELF |
3132 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
3133 | #endif | |
6c43fab6 | 3134 | |
c19d1205 ZW |
3135 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
3136 | /* First output the expression in the instruction to the pool. */ | |
3137 | emit_expr (&(pool->literals[entry]), 4); /* .word */ | |
b99bd4ef | 3138 | |
c19d1205 ZW |
3139 | /* Mark the pool as empty. */ |
3140 | pool->next_free_entry = 0; | |
3141 | pool->symbol = NULL; | |
b99bd4ef NC |
3142 | } |
3143 | ||
c19d1205 ZW |
3144 | #ifdef OBJ_ELF |
3145 | /* Forward declarations for functions below, in the MD interface | |
3146 | section. */ | |
3147 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
3148 | static valueT create_unwind_entry (int); | |
3149 | static void start_unwind_section (const segT, int); | |
3150 | static void add_unwind_opcode (valueT, int); | |
3151 | static void flush_pending_unwind (void); | |
b99bd4ef | 3152 | |
c19d1205 | 3153 | /* Directives: Data. */ |
b99bd4ef | 3154 | |
c19d1205 ZW |
3155 | static void |
3156 | s_arm_elf_cons (int nbytes) | |
3157 | { | |
3158 | expressionS exp; | |
b99bd4ef | 3159 | |
c19d1205 ZW |
3160 | #ifdef md_flush_pending_output |
3161 | md_flush_pending_output (); | |
3162 | #endif | |
b99bd4ef | 3163 | |
c19d1205 | 3164 | if (is_it_end_of_statement ()) |
b99bd4ef | 3165 | { |
c19d1205 ZW |
3166 | demand_empty_rest_of_line (); |
3167 | return; | |
b99bd4ef NC |
3168 | } |
3169 | ||
c19d1205 ZW |
3170 | #ifdef md_cons_align |
3171 | md_cons_align (nbytes); | |
3172 | #endif | |
b99bd4ef | 3173 | |
c19d1205 ZW |
3174 | mapping_state (MAP_DATA); |
3175 | do | |
b99bd4ef | 3176 | { |
c19d1205 ZW |
3177 | int reloc; |
3178 | char *base = input_line_pointer; | |
b99bd4ef | 3179 | |
c19d1205 | 3180 | expression (& exp); |
b99bd4ef | 3181 | |
c19d1205 ZW |
3182 | if (exp.X_op != O_symbol) |
3183 | emit_expr (&exp, (unsigned int) nbytes); | |
3184 | else | |
3185 | { | |
3186 | char *before_reloc = input_line_pointer; | |
3187 | reloc = parse_reloc (&input_line_pointer); | |
3188 | if (reloc == -1) | |
3189 | { | |
3190 | as_bad (_("unrecognized relocation suffix")); | |
3191 | ignore_rest_of_line (); | |
3192 | return; | |
3193 | } | |
3194 | else if (reloc == BFD_RELOC_UNUSED) | |
3195 | emit_expr (&exp, (unsigned int) nbytes); | |
3196 | else | |
3197 | { | |
21d799b5 NC |
3198 | reloc_howto_type *howto = (reloc_howto_type *) |
3199 | bfd_reloc_type_lookup (stdoutput, | |
3200 | (bfd_reloc_code_real_type) reloc); | |
c19d1205 | 3201 | int size = bfd_get_reloc_size (howto); |
b99bd4ef | 3202 | |
2fc8bdac ZW |
3203 | if (reloc == BFD_RELOC_ARM_PLT32) |
3204 | { | |
3205 | as_bad (_("(plt) is only valid on branch targets")); | |
3206 | reloc = BFD_RELOC_UNUSED; | |
3207 | size = 0; | |
3208 | } | |
3209 | ||
c19d1205 | 3210 | if (size > nbytes) |
2fc8bdac | 3211 | as_bad (_("%s relocations do not fit in %d bytes"), |
c19d1205 ZW |
3212 | howto->name, nbytes); |
3213 | else | |
3214 | { | |
3215 | /* We've parsed an expression stopping at O_symbol. | |
3216 | But there may be more expression left now that we | |
3217 | have parsed the relocation marker. Parse it again. | |
3218 | XXX Surely there is a cleaner way to do this. */ | |
3219 | char *p = input_line_pointer; | |
3220 | int offset; | |
21d799b5 | 3221 | char *save_buf = (char *) alloca (input_line_pointer - base); |
c19d1205 ZW |
3222 | memcpy (save_buf, base, input_line_pointer - base); |
3223 | memmove (base + (input_line_pointer - before_reloc), | |
3224 | base, before_reloc - base); | |
3225 | ||
3226 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
3227 | expression (&exp); | |
3228 | memcpy (base, save_buf, p - base); | |
3229 | ||
3230 | offset = nbytes - size; | |
3231 | p = frag_more ((int) nbytes); | |
3232 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, | |
21d799b5 | 3233 | size, &exp, 0, (enum bfd_reloc_code_real) reloc); |
c19d1205 ZW |
3234 | } |
3235 | } | |
3236 | } | |
b99bd4ef | 3237 | } |
c19d1205 | 3238 | while (*input_line_pointer++ == ','); |
b99bd4ef | 3239 | |
c19d1205 ZW |
3240 | /* Put terminator back into stream. */ |
3241 | input_line_pointer --; | |
3242 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
3243 | } |
3244 | ||
c921be7d NC |
3245 | /* Emit an expression containing a 32-bit thumb instruction. |
3246 | Implementation based on put_thumb32_insn. */ | |
3247 | ||
3248 | static void | |
3249 | emit_thumb32_expr (expressionS * exp) | |
3250 | { | |
3251 | expressionS exp_high = *exp; | |
3252 | ||
3253 | exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16; | |
3254 | emit_expr (& exp_high, (unsigned int) THUMB_SIZE); | |
3255 | exp->X_add_number &= 0xffff; | |
3256 | emit_expr (exp, (unsigned int) THUMB_SIZE); | |
3257 | } | |
3258 | ||
3259 | /* Guess the instruction size based on the opcode. */ | |
3260 | ||
3261 | static int | |
3262 | thumb_insn_size (int opcode) | |
3263 | { | |
3264 | if ((unsigned int) opcode < 0xe800u) | |
3265 | return 2; | |
3266 | else if ((unsigned int) opcode >= 0xe8000000u) | |
3267 | return 4; | |
3268 | else | |
3269 | return 0; | |
3270 | } | |
3271 | ||
3272 | static bfd_boolean | |
3273 | emit_insn (expressionS *exp, int nbytes) | |
3274 | { | |
3275 | int size = 0; | |
3276 | ||
3277 | if (exp->X_op == O_constant) | |
3278 | { | |
3279 | size = nbytes; | |
3280 | ||
3281 | if (size == 0) | |
3282 | size = thumb_insn_size (exp->X_add_number); | |
3283 | ||
3284 | if (size != 0) | |
3285 | { | |
3286 | if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu) | |
3287 | { | |
3288 | as_bad (_(".inst.n operand too big. "\ | |
3289 | "Use .inst.w instead")); | |
3290 | size = 0; | |
3291 | } | |
3292 | else | |
3293 | { | |
3294 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
3295 | set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0); | |
3296 | else | |
3297 | set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0); | |
3298 | ||
3299 | if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian) | |
3300 | emit_thumb32_expr (exp); | |
3301 | else | |
3302 | emit_expr (exp, (unsigned int) size); | |
3303 | ||
3304 | it_fsm_post_encode (); | |
3305 | } | |
3306 | } | |
3307 | else | |
3308 | as_bad (_("cannot determine Thumb instruction size. " \ | |
3309 | "Use .inst.n/.inst.w instead")); | |
3310 | } | |
3311 | else | |
3312 | as_bad (_("constant expression required")); | |
3313 | ||
3314 | return (size != 0); | |
3315 | } | |
3316 | ||
3317 | /* Like s_arm_elf_cons but do not use md_cons_align and | |
3318 | set the mapping state to MAP_ARM/MAP_THUMB. */ | |
3319 | ||
3320 | static void | |
3321 | s_arm_elf_inst (int nbytes) | |
3322 | { | |
3323 | if (is_it_end_of_statement ()) | |
3324 | { | |
3325 | demand_empty_rest_of_line (); | |
3326 | return; | |
3327 | } | |
3328 | ||
3329 | /* Calling mapping_state () here will not change ARM/THUMB, | |
3330 | but will ensure not to be in DATA state. */ | |
3331 | ||
3332 | if (thumb_mode) | |
3333 | mapping_state (MAP_THUMB); | |
3334 | else | |
3335 | { | |
3336 | if (nbytes != 0) | |
3337 | { | |
3338 | as_bad (_("width suffixes are invalid in ARM mode")); | |
3339 | ignore_rest_of_line (); | |
3340 | return; | |
3341 | } | |
3342 | ||
3343 | nbytes = 4; | |
3344 | ||
3345 | mapping_state (MAP_ARM); | |
3346 | } | |
3347 | ||
3348 | do | |
3349 | { | |
3350 | expressionS exp; | |
3351 | ||
3352 | expression (& exp); | |
3353 | ||
3354 | if (! emit_insn (& exp, nbytes)) | |
3355 | { | |
3356 | ignore_rest_of_line (); | |
3357 | return; | |
3358 | } | |
3359 | } | |
3360 | while (*input_line_pointer++ == ','); | |
3361 | ||
3362 | /* Put terminator back into stream. */ | |
3363 | input_line_pointer --; | |
3364 | demand_empty_rest_of_line (); | |
3365 | } | |
b99bd4ef | 3366 | |
c19d1205 | 3367 | /* Parse a .rel31 directive. */ |
b99bd4ef | 3368 | |
c19d1205 ZW |
3369 | static void |
3370 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
3371 | { | |
3372 | expressionS exp; | |
3373 | char *p; | |
3374 | valueT highbit; | |
b99bd4ef | 3375 | |
c19d1205 ZW |
3376 | highbit = 0; |
3377 | if (*input_line_pointer == '1') | |
3378 | highbit = 0x80000000; | |
3379 | else if (*input_line_pointer != '0') | |
3380 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 3381 | |
c19d1205 ZW |
3382 | input_line_pointer++; |
3383 | if (*input_line_pointer != ',') | |
3384 | as_bad (_("missing comma")); | |
3385 | input_line_pointer++; | |
b99bd4ef | 3386 | |
c19d1205 ZW |
3387 | #ifdef md_flush_pending_output |
3388 | md_flush_pending_output (); | |
3389 | #endif | |
b99bd4ef | 3390 | |
c19d1205 ZW |
3391 | #ifdef md_cons_align |
3392 | md_cons_align (4); | |
3393 | #endif | |
b99bd4ef | 3394 | |
c19d1205 | 3395 | mapping_state (MAP_DATA); |
b99bd4ef | 3396 | |
c19d1205 | 3397 | expression (&exp); |
b99bd4ef | 3398 | |
c19d1205 ZW |
3399 | p = frag_more (4); |
3400 | md_number_to_chars (p, highbit, 4); | |
3401 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
3402 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 3403 | |
c19d1205 | 3404 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3405 | } |
3406 | ||
c19d1205 | 3407 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 3408 | |
c19d1205 | 3409 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 3410 | |
c19d1205 ZW |
3411 | static void |
3412 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
3413 | { | |
3414 | demand_empty_rest_of_line (); | |
921e5f0a PB |
3415 | if (unwind.proc_start) |
3416 | { | |
c921be7d | 3417 | as_bad (_("duplicate .fnstart directive")); |
921e5f0a PB |
3418 | return; |
3419 | } | |
3420 | ||
c19d1205 ZW |
3421 | /* Mark the start of the function. */ |
3422 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 3423 | |
c19d1205 ZW |
3424 | /* Reset the rest of the unwind info. */ |
3425 | unwind.opcode_count = 0; | |
3426 | unwind.table_entry = NULL; | |
3427 | unwind.personality_routine = NULL; | |
3428 | unwind.personality_index = -1; | |
3429 | unwind.frame_size = 0; | |
3430 | unwind.fp_offset = 0; | |
fdfde340 | 3431 | unwind.fp_reg = REG_SP; |
c19d1205 ZW |
3432 | unwind.fp_used = 0; |
3433 | unwind.sp_restored = 0; | |
3434 | } | |
b99bd4ef | 3435 | |
b99bd4ef | 3436 | |
c19d1205 ZW |
3437 | /* Parse a handlerdata directive. Creates the exception handling table entry |
3438 | for the function. */ | |
b99bd4ef | 3439 | |
c19d1205 ZW |
3440 | static void |
3441 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
3442 | { | |
3443 | demand_empty_rest_of_line (); | |
921e5f0a | 3444 | if (!unwind.proc_start) |
c921be7d | 3445 | as_bad (MISSING_FNSTART); |
921e5f0a | 3446 | |
c19d1205 | 3447 | if (unwind.table_entry) |
6decc662 | 3448 | as_bad (_("duplicate .handlerdata directive")); |
f02232aa | 3449 | |
c19d1205 ZW |
3450 | create_unwind_entry (1); |
3451 | } | |
a737bd4d | 3452 | |
c19d1205 | 3453 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 3454 | |
c19d1205 ZW |
3455 | static void |
3456 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
3457 | { | |
3458 | long where; | |
3459 | char *ptr; | |
3460 | valueT val; | |
940b5ce0 | 3461 | unsigned int marked_pr_dependency; |
f02232aa | 3462 | |
c19d1205 | 3463 | demand_empty_rest_of_line (); |
f02232aa | 3464 | |
921e5f0a PB |
3465 | if (!unwind.proc_start) |
3466 | { | |
c921be7d | 3467 | as_bad (_(".fnend directive without .fnstart")); |
921e5f0a PB |
3468 | return; |
3469 | } | |
3470 | ||
c19d1205 ZW |
3471 | /* Add eh table entry. */ |
3472 | if (unwind.table_entry == NULL) | |
3473 | val = create_unwind_entry (0); | |
3474 | else | |
3475 | val = 0; | |
f02232aa | 3476 | |
c19d1205 ZW |
3477 | /* Add index table entry. This is two words. */ |
3478 | start_unwind_section (unwind.saved_seg, 1); | |
3479 | frag_align (2, 0, 0); | |
3480 | record_alignment (now_seg, 2); | |
b99bd4ef | 3481 | |
c19d1205 ZW |
3482 | ptr = frag_more (8); |
3483 | where = frag_now_fix () - 8; | |
f02232aa | 3484 | |
c19d1205 ZW |
3485 | /* Self relative offset of the function start. */ |
3486 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
3487 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3488 | |
c19d1205 ZW |
3489 | /* Indicate dependency on EHABI-defined personality routines to the |
3490 | linker, if it hasn't been done already. */ | |
940b5ce0 DJ |
3491 | marked_pr_dependency |
3492 | = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency; | |
c19d1205 ZW |
3493 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 |
3494 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
3495 | { | |
5f4273c7 NC |
3496 | static const char *const name[] = |
3497 | { | |
3498 | "__aeabi_unwind_cpp_pr0", | |
3499 | "__aeabi_unwind_cpp_pr1", | |
3500 | "__aeabi_unwind_cpp_pr2" | |
3501 | }; | |
c19d1205 ZW |
3502 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); |
3503 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
c19d1205 | 3504 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency |
940b5ce0 | 3505 | |= 1 << unwind.personality_index; |
c19d1205 | 3506 | } |
f02232aa | 3507 | |
c19d1205 ZW |
3508 | if (val) |
3509 | /* Inline exception table entry. */ | |
3510 | md_number_to_chars (ptr + 4, val, 4); | |
3511 | else | |
3512 | /* Self relative offset of the table entry. */ | |
3513 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
3514 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3515 | |
c19d1205 ZW |
3516 | /* Restore the original section. */ |
3517 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
921e5f0a PB |
3518 | |
3519 | unwind.proc_start = NULL; | |
c19d1205 | 3520 | } |
f02232aa | 3521 | |
f02232aa | 3522 | |
c19d1205 | 3523 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 3524 | |
c19d1205 ZW |
3525 | static void |
3526 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
3527 | { | |
3528 | demand_empty_rest_of_line (); | |
921e5f0a | 3529 | if (!unwind.proc_start) |
c921be7d | 3530 | as_bad (MISSING_FNSTART); |
921e5f0a | 3531 | |
c19d1205 ZW |
3532 | if (unwind.personality_routine || unwind.personality_index != -1) |
3533 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 3534 | |
c19d1205 ZW |
3535 | unwind.personality_index = -2; |
3536 | } | |
b99bd4ef | 3537 | |
b99bd4ef | 3538 | |
c19d1205 | 3539 | /* Parse a personalityindex directive. */ |
b99bd4ef | 3540 | |
c19d1205 ZW |
3541 | static void |
3542 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
3543 | { | |
3544 | expressionS exp; | |
b99bd4ef | 3545 | |
921e5f0a | 3546 | if (!unwind.proc_start) |
c921be7d | 3547 | as_bad (MISSING_FNSTART); |
921e5f0a | 3548 | |
c19d1205 ZW |
3549 | if (unwind.personality_routine || unwind.personality_index != -1) |
3550 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 3551 | |
c19d1205 | 3552 | expression (&exp); |
b99bd4ef | 3553 | |
c19d1205 ZW |
3554 | if (exp.X_op != O_constant |
3555 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 3556 | { |
c19d1205 ZW |
3557 | as_bad (_("bad personality routine number")); |
3558 | ignore_rest_of_line (); | |
3559 | return; | |
b99bd4ef NC |
3560 | } |
3561 | ||
c19d1205 | 3562 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 3563 | |
c19d1205 ZW |
3564 | demand_empty_rest_of_line (); |
3565 | } | |
e16bb312 | 3566 | |
e16bb312 | 3567 | |
c19d1205 | 3568 | /* Parse a personality directive. */ |
e16bb312 | 3569 | |
c19d1205 ZW |
3570 | static void |
3571 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
3572 | { | |
3573 | char *name, *p, c; | |
a737bd4d | 3574 | |
921e5f0a | 3575 | if (!unwind.proc_start) |
c921be7d | 3576 | as_bad (MISSING_FNSTART); |
921e5f0a | 3577 | |
c19d1205 ZW |
3578 | if (unwind.personality_routine || unwind.personality_index != -1) |
3579 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 3580 | |
c19d1205 ZW |
3581 | name = input_line_pointer; |
3582 | c = get_symbol_end (); | |
3583 | p = input_line_pointer; | |
3584 | unwind.personality_routine = symbol_find_or_make (name); | |
3585 | *p = c; | |
3586 | demand_empty_rest_of_line (); | |
3587 | } | |
e16bb312 | 3588 | |
e16bb312 | 3589 | |
c19d1205 | 3590 | /* Parse a directive saving core registers. */ |
e16bb312 | 3591 | |
c19d1205 ZW |
3592 | static void |
3593 | s_arm_unwind_save_core (void) | |
e16bb312 | 3594 | { |
c19d1205 ZW |
3595 | valueT op; |
3596 | long range; | |
3597 | int n; | |
e16bb312 | 3598 | |
c19d1205 ZW |
3599 | range = parse_reg_list (&input_line_pointer); |
3600 | if (range == FAIL) | |
e16bb312 | 3601 | { |
c19d1205 ZW |
3602 | as_bad (_("expected register list")); |
3603 | ignore_rest_of_line (); | |
3604 | return; | |
3605 | } | |
e16bb312 | 3606 | |
c19d1205 | 3607 | demand_empty_rest_of_line (); |
e16bb312 | 3608 | |
c19d1205 ZW |
3609 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
3610 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
3611 | ip because it is clobbered by calls. */ | |
3612 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
3613 | && (range & 0x3000) == 0x1000) | |
3614 | { | |
3615 | unwind.opcode_count--; | |
3616 | unwind.sp_restored = 0; | |
3617 | range = (range | 0x2000) & ~0x1000; | |
3618 | unwind.pending_offset = 0; | |
3619 | } | |
e16bb312 | 3620 | |
01ae4198 DJ |
3621 | /* Pop r4-r15. */ |
3622 | if (range & 0xfff0) | |
c19d1205 | 3623 | { |
01ae4198 DJ |
3624 | /* See if we can use the short opcodes. These pop a block of up to 8 |
3625 | registers starting with r4, plus maybe r14. */ | |
3626 | for (n = 0; n < 8; n++) | |
3627 | { | |
3628 | /* Break at the first non-saved register. */ | |
3629 | if ((range & (1 << (n + 4))) == 0) | |
3630 | break; | |
3631 | } | |
3632 | /* See if there are any other bits set. */ | |
3633 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
3634 | { | |
3635 | /* Use the long form. */ | |
3636 | op = 0x8000 | ((range >> 4) & 0xfff); | |
3637 | add_unwind_opcode (op, 2); | |
3638 | } | |
0dd132b6 | 3639 | else |
01ae4198 DJ |
3640 | { |
3641 | /* Use the short form. */ | |
3642 | if (range & 0x4000) | |
3643 | op = 0xa8; /* Pop r14. */ | |
3644 | else | |
3645 | op = 0xa0; /* Do not pop r14. */ | |
3646 | op |= (n - 1); | |
3647 | add_unwind_opcode (op, 1); | |
3648 | } | |
c19d1205 | 3649 | } |
0dd132b6 | 3650 | |
c19d1205 ZW |
3651 | /* Pop r0-r3. */ |
3652 | if (range & 0xf) | |
3653 | { | |
3654 | op = 0xb100 | (range & 0xf); | |
3655 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
3656 | } |
3657 | ||
c19d1205 ZW |
3658 | /* Record the number of bytes pushed. */ |
3659 | for (n = 0; n < 16; n++) | |
3660 | { | |
3661 | if (range & (1 << n)) | |
3662 | unwind.frame_size += 4; | |
3663 | } | |
0dd132b6 NC |
3664 | } |
3665 | ||
c19d1205 ZW |
3666 | |
3667 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
3668 | |
3669 | static void | |
c19d1205 | 3670 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 3671 | { |
c19d1205 ZW |
3672 | expressionS exp; |
3673 | int num_regs; | |
3674 | valueT op; | |
b99bd4ef | 3675 | |
c19d1205 ZW |
3676 | /* Get Number of registers to transfer. */ |
3677 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
3678 | expression (&exp); | |
3679 | else | |
3680 | exp.X_op = O_illegal; | |
b99bd4ef | 3681 | |
c19d1205 | 3682 | if (exp.X_op != O_constant) |
b99bd4ef | 3683 | { |
c19d1205 ZW |
3684 | as_bad (_("expected , <constant>")); |
3685 | ignore_rest_of_line (); | |
b99bd4ef NC |
3686 | return; |
3687 | } | |
3688 | ||
c19d1205 ZW |
3689 | num_regs = exp.X_add_number; |
3690 | ||
3691 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 3692 | { |
c19d1205 ZW |
3693 | as_bad (_("number of registers must be in the range [1:4]")); |
3694 | ignore_rest_of_line (); | |
b99bd4ef NC |
3695 | return; |
3696 | } | |
3697 | ||
c19d1205 | 3698 | demand_empty_rest_of_line (); |
b99bd4ef | 3699 | |
c19d1205 ZW |
3700 | if (reg == 4) |
3701 | { | |
3702 | /* Short form. */ | |
3703 | op = 0xb4 | (num_regs - 1); | |
3704 | add_unwind_opcode (op, 1); | |
3705 | } | |
b99bd4ef NC |
3706 | else |
3707 | { | |
c19d1205 ZW |
3708 | /* Long form. */ |
3709 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
3710 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3711 | } |
c19d1205 | 3712 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
3713 | } |
3714 | ||
c19d1205 | 3715 | |
fa073d69 MS |
3716 | /* Parse a directive saving VFP registers for ARMv6 and above. */ |
3717 | ||
3718 | static void | |
3719 | s_arm_unwind_save_vfp_armv6 (void) | |
3720 | { | |
3721 | int count; | |
3722 | unsigned int start; | |
3723 | valueT op; | |
3724 | int num_vfpv3_regs = 0; | |
3725 | int num_regs_below_16; | |
3726 | ||
3727 | count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); | |
3728 | if (count == FAIL) | |
3729 | { | |
3730 | as_bad (_("expected register list")); | |
3731 | ignore_rest_of_line (); | |
3732 | return; | |
3733 | } | |
3734 | ||
3735 | demand_empty_rest_of_line (); | |
3736 | ||
3737 | /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather | |
3738 | than FSTMX/FLDMX-style ones). */ | |
3739 | ||
3740 | /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ | |
3741 | if (start >= 16) | |
3742 | num_vfpv3_regs = count; | |
3743 | else if (start + count > 16) | |
3744 | num_vfpv3_regs = start + count - 16; | |
3745 | ||
3746 | if (num_vfpv3_regs > 0) | |
3747 | { | |
3748 | int start_offset = start > 16 ? start - 16 : 0; | |
3749 | op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); | |
3750 | add_unwind_opcode (op, 2); | |
3751 | } | |
3752 | ||
3753 | /* Generate opcode for registers numbered in the range 0 .. 15. */ | |
3754 | num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; | |
9c2799c2 | 3755 | gas_assert (num_regs_below_16 + num_vfpv3_regs == count); |
fa073d69 MS |
3756 | if (num_regs_below_16 > 0) |
3757 | { | |
3758 | op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); | |
3759 | add_unwind_opcode (op, 2); | |
3760 | } | |
3761 | ||
3762 | unwind.frame_size += count * 8; | |
3763 | } | |
3764 | ||
3765 | ||
3766 | /* Parse a directive saving VFP registers for pre-ARMv6. */ | |
b99bd4ef NC |
3767 | |
3768 | static void | |
c19d1205 | 3769 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 3770 | { |
c19d1205 | 3771 | int count; |
ca3f61f7 | 3772 | unsigned int reg; |
c19d1205 | 3773 | valueT op; |
b99bd4ef | 3774 | |
5287ad62 | 3775 | count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); |
c19d1205 | 3776 | if (count == FAIL) |
b99bd4ef | 3777 | { |
c19d1205 ZW |
3778 | as_bad (_("expected register list")); |
3779 | ignore_rest_of_line (); | |
b99bd4ef NC |
3780 | return; |
3781 | } | |
3782 | ||
c19d1205 | 3783 | demand_empty_rest_of_line (); |
b99bd4ef | 3784 | |
c19d1205 | 3785 | if (reg == 8) |
b99bd4ef | 3786 | { |
c19d1205 ZW |
3787 | /* Short form. */ |
3788 | op = 0xb8 | (count - 1); | |
3789 | add_unwind_opcode (op, 1); | |
b99bd4ef | 3790 | } |
c19d1205 | 3791 | else |
b99bd4ef | 3792 | { |
c19d1205 ZW |
3793 | /* Long form. */ |
3794 | op = 0xb300 | (reg << 4) | (count - 1); | |
3795 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3796 | } |
c19d1205 ZW |
3797 | unwind.frame_size += count * 8 + 4; |
3798 | } | |
b99bd4ef | 3799 | |
b99bd4ef | 3800 | |
c19d1205 ZW |
3801 | /* Parse a directive saving iWMMXt data registers. */ |
3802 | ||
3803 | static void | |
3804 | s_arm_unwind_save_mmxwr (void) | |
3805 | { | |
3806 | int reg; | |
3807 | int hi_reg; | |
3808 | int i; | |
3809 | unsigned mask = 0; | |
3810 | valueT op; | |
b99bd4ef | 3811 | |
c19d1205 ZW |
3812 | if (*input_line_pointer == '{') |
3813 | input_line_pointer++; | |
b99bd4ef | 3814 | |
c19d1205 | 3815 | do |
b99bd4ef | 3816 | { |
dcbf9037 | 3817 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 3818 | |
c19d1205 | 3819 | if (reg == FAIL) |
b99bd4ef | 3820 | { |
9b7132d3 | 3821 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 | 3822 | goto error; |
b99bd4ef NC |
3823 | } |
3824 | ||
c19d1205 ZW |
3825 | if (mask >> reg) |
3826 | as_tsktsk (_("register list not in ascending order")); | |
3827 | mask |= 1 << reg; | |
b99bd4ef | 3828 | |
c19d1205 ZW |
3829 | if (*input_line_pointer == '-') |
3830 | { | |
3831 | input_line_pointer++; | |
dcbf9037 | 3832 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
c19d1205 ZW |
3833 | if (hi_reg == FAIL) |
3834 | { | |
9b7132d3 | 3835 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 ZW |
3836 | goto error; |
3837 | } | |
3838 | else if (reg >= hi_reg) | |
3839 | { | |
3840 | as_bad (_("bad register range")); | |
3841 | goto error; | |
3842 | } | |
3843 | for (; reg < hi_reg; reg++) | |
3844 | mask |= 1 << reg; | |
3845 | } | |
3846 | } | |
3847 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 3848 | |
c19d1205 ZW |
3849 | if (*input_line_pointer == '}') |
3850 | input_line_pointer++; | |
b99bd4ef | 3851 | |
c19d1205 | 3852 | demand_empty_rest_of_line (); |
b99bd4ef | 3853 | |
708587a4 | 3854 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
3855 | the list. */ |
3856 | flush_pending_unwind (); | |
b99bd4ef | 3857 | |
c19d1205 | 3858 | for (i = 0; i < 16; i++) |
b99bd4ef | 3859 | { |
c19d1205 ZW |
3860 | if (mask & (1 << i)) |
3861 | unwind.frame_size += 8; | |
b99bd4ef NC |
3862 | } |
3863 | ||
c19d1205 ZW |
3864 | /* Attempt to combine with a previous opcode. We do this because gcc |
3865 | likes to output separate unwind directives for a single block of | |
3866 | registers. */ | |
3867 | if (unwind.opcode_count > 0) | |
b99bd4ef | 3868 | { |
c19d1205 ZW |
3869 | i = unwind.opcodes[unwind.opcode_count - 1]; |
3870 | if ((i & 0xf8) == 0xc0) | |
3871 | { | |
3872 | i &= 7; | |
3873 | /* Only merge if the blocks are contiguous. */ | |
3874 | if (i < 6) | |
3875 | { | |
3876 | if ((mask & 0xfe00) == (1 << 9)) | |
3877 | { | |
3878 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
3879 | unwind.opcode_count--; | |
3880 | } | |
3881 | } | |
3882 | else if (i == 6 && unwind.opcode_count >= 2) | |
3883 | { | |
3884 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
3885 | reg = i >> 4; | |
3886 | i &= 0xf; | |
b99bd4ef | 3887 | |
c19d1205 ZW |
3888 | op = 0xffff << (reg - 1); |
3889 | if (reg > 0 | |
87a1fd79 | 3890 | && ((mask & op) == (1u << (reg - 1)))) |
c19d1205 ZW |
3891 | { |
3892 | op = (1 << (reg + i + 1)) - 1; | |
3893 | op &= ~((1 << reg) - 1); | |
3894 | mask |= op; | |
3895 | unwind.opcode_count -= 2; | |
3896 | } | |
3897 | } | |
3898 | } | |
b99bd4ef NC |
3899 | } |
3900 | ||
c19d1205 ZW |
3901 | hi_reg = 15; |
3902 | /* We want to generate opcodes in the order the registers have been | |
3903 | saved, ie. descending order. */ | |
3904 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 3905 | { |
c19d1205 ZW |
3906 | /* Save registers in blocks. */ |
3907 | if (reg < 0 | |
3908 | || !(mask & (1 << reg))) | |
3909 | { | |
3910 | /* We found an unsaved reg. Generate opcodes to save the | |
5f4273c7 | 3911 | preceding block. */ |
c19d1205 ZW |
3912 | if (reg != hi_reg) |
3913 | { | |
3914 | if (reg == 9) | |
3915 | { | |
3916 | /* Short form. */ | |
3917 | op = 0xc0 | (hi_reg - 10); | |
3918 | add_unwind_opcode (op, 1); | |
3919 | } | |
3920 | else | |
3921 | { | |
3922 | /* Long form. */ | |
3923 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
3924 | add_unwind_opcode (op, 2); | |
3925 | } | |
3926 | } | |
3927 | hi_reg = reg - 1; | |
3928 | } | |
b99bd4ef NC |
3929 | } |
3930 | ||
c19d1205 ZW |
3931 | return; |
3932 | error: | |
3933 | ignore_rest_of_line (); | |
b99bd4ef NC |
3934 | } |
3935 | ||
3936 | static void | |
c19d1205 | 3937 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 3938 | { |
c19d1205 ZW |
3939 | int reg; |
3940 | int hi_reg; | |
3941 | unsigned mask = 0; | |
3942 | valueT op; | |
b99bd4ef | 3943 | |
c19d1205 ZW |
3944 | if (*input_line_pointer == '{') |
3945 | input_line_pointer++; | |
b99bd4ef | 3946 | |
c19d1205 | 3947 | do |
b99bd4ef | 3948 | { |
dcbf9037 | 3949 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 3950 | |
c19d1205 ZW |
3951 | if (reg == FAIL) |
3952 | { | |
9b7132d3 | 3953 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
3954 | goto error; |
3955 | } | |
b99bd4ef | 3956 | |
c19d1205 ZW |
3957 | reg -= 8; |
3958 | if (mask >> reg) | |
3959 | as_tsktsk (_("register list not in ascending order")); | |
3960 | mask |= 1 << reg; | |
b99bd4ef | 3961 | |
c19d1205 ZW |
3962 | if (*input_line_pointer == '-') |
3963 | { | |
3964 | input_line_pointer++; | |
dcbf9037 | 3965 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
c19d1205 ZW |
3966 | if (hi_reg == FAIL) |
3967 | { | |
9b7132d3 | 3968 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
3969 | goto error; |
3970 | } | |
3971 | else if (reg >= hi_reg) | |
3972 | { | |
3973 | as_bad (_("bad register range")); | |
3974 | goto error; | |
3975 | } | |
3976 | for (; reg < hi_reg; reg++) | |
3977 | mask |= 1 << reg; | |
3978 | } | |
b99bd4ef | 3979 | } |
c19d1205 | 3980 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 3981 | |
c19d1205 ZW |
3982 | if (*input_line_pointer == '}') |
3983 | input_line_pointer++; | |
b99bd4ef | 3984 | |
c19d1205 ZW |
3985 | demand_empty_rest_of_line (); |
3986 | ||
708587a4 | 3987 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
3988 | the list. */ |
3989 | flush_pending_unwind (); | |
b99bd4ef | 3990 | |
c19d1205 | 3991 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 3992 | { |
c19d1205 ZW |
3993 | if (mask & (1 << reg)) |
3994 | unwind.frame_size += 4; | |
b99bd4ef | 3995 | } |
c19d1205 ZW |
3996 | op = 0xc700 | mask; |
3997 | add_unwind_opcode (op, 2); | |
3998 | return; | |
3999 | error: | |
4000 | ignore_rest_of_line (); | |
b99bd4ef NC |
4001 | } |
4002 | ||
c19d1205 | 4003 | |
fa073d69 MS |
4004 | /* Parse an unwind_save directive. |
4005 | If the argument is non-zero, this is a .vsave directive. */ | |
c19d1205 | 4006 | |
b99bd4ef | 4007 | static void |
fa073d69 | 4008 | s_arm_unwind_save (int arch_v6) |
b99bd4ef | 4009 | { |
c19d1205 ZW |
4010 | char *peek; |
4011 | struct reg_entry *reg; | |
4012 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 4013 | |
921e5f0a | 4014 | if (!unwind.proc_start) |
c921be7d | 4015 | as_bad (MISSING_FNSTART); |
921e5f0a | 4016 | |
c19d1205 ZW |
4017 | /* Figure out what sort of save we have. */ |
4018 | peek = input_line_pointer; | |
b99bd4ef | 4019 | |
c19d1205 | 4020 | if (*peek == '{') |
b99bd4ef | 4021 | { |
c19d1205 ZW |
4022 | had_brace = TRUE; |
4023 | peek++; | |
b99bd4ef NC |
4024 | } |
4025 | ||
c19d1205 | 4026 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 4027 | |
c19d1205 | 4028 | if (!reg) |
b99bd4ef | 4029 | { |
c19d1205 ZW |
4030 | as_bad (_("register expected")); |
4031 | ignore_rest_of_line (); | |
b99bd4ef NC |
4032 | return; |
4033 | } | |
4034 | ||
c19d1205 | 4035 | switch (reg->type) |
b99bd4ef | 4036 | { |
c19d1205 ZW |
4037 | case REG_TYPE_FN: |
4038 | if (had_brace) | |
4039 | { | |
4040 | as_bad (_("FPA .unwind_save does not take a register list")); | |
4041 | ignore_rest_of_line (); | |
4042 | return; | |
4043 | } | |
93ac2687 | 4044 | input_line_pointer = peek; |
c19d1205 | 4045 | s_arm_unwind_save_fpa (reg->number); |
b99bd4ef | 4046 | return; |
c19d1205 ZW |
4047 | |
4048 | case REG_TYPE_RN: s_arm_unwind_save_core (); return; | |
fa073d69 MS |
4049 | case REG_TYPE_VFD: |
4050 | if (arch_v6) | |
4051 | s_arm_unwind_save_vfp_armv6 (); | |
4052 | else | |
4053 | s_arm_unwind_save_vfp (); | |
4054 | return; | |
c19d1205 ZW |
4055 | case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; |
4056 | case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; | |
4057 | ||
4058 | default: | |
4059 | as_bad (_(".unwind_save does not support this kind of register")); | |
4060 | ignore_rest_of_line (); | |
b99bd4ef | 4061 | } |
c19d1205 | 4062 | } |
b99bd4ef | 4063 | |
b99bd4ef | 4064 | |
c19d1205 ZW |
4065 | /* Parse an unwind_movsp directive. */ |
4066 | ||
4067 | static void | |
4068 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
4069 | { | |
4070 | int reg; | |
4071 | valueT op; | |
4fa3602b | 4072 | int offset; |
c19d1205 | 4073 | |
921e5f0a | 4074 | if (!unwind.proc_start) |
c921be7d | 4075 | as_bad (MISSING_FNSTART); |
921e5f0a | 4076 | |
dcbf9037 | 4077 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 | 4078 | if (reg == FAIL) |
b99bd4ef | 4079 | { |
9b7132d3 | 4080 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 | 4081 | ignore_rest_of_line (); |
b99bd4ef NC |
4082 | return; |
4083 | } | |
4fa3602b PB |
4084 | |
4085 | /* Optional constant. */ | |
4086 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4087 | { | |
4088 | if (immediate_for_directive (&offset) == FAIL) | |
4089 | return; | |
4090 | } | |
4091 | else | |
4092 | offset = 0; | |
4093 | ||
c19d1205 | 4094 | demand_empty_rest_of_line (); |
b99bd4ef | 4095 | |
c19d1205 | 4096 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 4097 | { |
c19d1205 | 4098 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
4099 | return; |
4100 | } | |
4101 | ||
c19d1205 ZW |
4102 | if (unwind.fp_reg != REG_SP) |
4103 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 4104 | |
c19d1205 ZW |
4105 | /* Generate opcode to restore the value. */ |
4106 | op = 0x90 | reg; | |
4107 | add_unwind_opcode (op, 1); | |
4108 | ||
4109 | /* Record the information for later. */ | |
4110 | unwind.fp_reg = reg; | |
4fa3602b | 4111 | unwind.fp_offset = unwind.frame_size - offset; |
c19d1205 | 4112 | unwind.sp_restored = 1; |
b05fe5cf ZW |
4113 | } |
4114 | ||
c19d1205 ZW |
4115 | /* Parse an unwind_pad directive. */ |
4116 | ||
b05fe5cf | 4117 | static void |
c19d1205 | 4118 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 4119 | { |
c19d1205 | 4120 | int offset; |
b05fe5cf | 4121 | |
921e5f0a | 4122 | if (!unwind.proc_start) |
c921be7d | 4123 | as_bad (MISSING_FNSTART); |
921e5f0a | 4124 | |
c19d1205 ZW |
4125 | if (immediate_for_directive (&offset) == FAIL) |
4126 | return; | |
b99bd4ef | 4127 | |
c19d1205 ZW |
4128 | if (offset & 3) |
4129 | { | |
4130 | as_bad (_("stack increment must be multiple of 4")); | |
4131 | ignore_rest_of_line (); | |
4132 | return; | |
4133 | } | |
b99bd4ef | 4134 | |
c19d1205 ZW |
4135 | /* Don't generate any opcodes, just record the details for later. */ |
4136 | unwind.frame_size += offset; | |
4137 | unwind.pending_offset += offset; | |
4138 | ||
4139 | demand_empty_rest_of_line (); | |
4140 | } | |
4141 | ||
4142 | /* Parse an unwind_setfp directive. */ | |
4143 | ||
4144 | static void | |
4145 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 4146 | { |
c19d1205 ZW |
4147 | int sp_reg; |
4148 | int fp_reg; | |
4149 | int offset; | |
4150 | ||
921e5f0a | 4151 | if (!unwind.proc_start) |
c921be7d | 4152 | as_bad (MISSING_FNSTART); |
921e5f0a | 4153 | |
dcbf9037 | 4154 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 ZW |
4155 | if (skip_past_comma (&input_line_pointer) == FAIL) |
4156 | sp_reg = FAIL; | |
4157 | else | |
dcbf9037 | 4158 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
b99bd4ef | 4159 | |
c19d1205 ZW |
4160 | if (fp_reg == FAIL || sp_reg == FAIL) |
4161 | { | |
4162 | as_bad (_("expected <reg>, <reg>")); | |
4163 | ignore_rest_of_line (); | |
4164 | return; | |
4165 | } | |
b99bd4ef | 4166 | |
c19d1205 ZW |
4167 | /* Optional constant. */ |
4168 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4169 | { | |
4170 | if (immediate_for_directive (&offset) == FAIL) | |
4171 | return; | |
4172 | } | |
4173 | else | |
4174 | offset = 0; | |
a737bd4d | 4175 | |
c19d1205 | 4176 | demand_empty_rest_of_line (); |
a737bd4d | 4177 | |
fdfde340 | 4178 | if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) |
a737bd4d | 4179 | { |
c19d1205 ZW |
4180 | as_bad (_("register must be either sp or set by a previous" |
4181 | "unwind_movsp directive")); | |
4182 | return; | |
a737bd4d NC |
4183 | } |
4184 | ||
c19d1205 ZW |
4185 | /* Don't generate any opcodes, just record the information for later. */ |
4186 | unwind.fp_reg = fp_reg; | |
4187 | unwind.fp_used = 1; | |
fdfde340 | 4188 | if (sp_reg == REG_SP) |
c19d1205 ZW |
4189 | unwind.fp_offset = unwind.frame_size - offset; |
4190 | else | |
4191 | unwind.fp_offset -= offset; | |
a737bd4d NC |
4192 | } |
4193 | ||
c19d1205 ZW |
4194 | /* Parse an unwind_raw directive. */ |
4195 | ||
4196 | static void | |
4197 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 4198 | { |
c19d1205 | 4199 | expressionS exp; |
708587a4 | 4200 | /* This is an arbitrary limit. */ |
c19d1205 ZW |
4201 | unsigned char op[16]; |
4202 | int count; | |
a737bd4d | 4203 | |
921e5f0a | 4204 | if (!unwind.proc_start) |
c921be7d | 4205 | as_bad (MISSING_FNSTART); |
921e5f0a | 4206 | |
c19d1205 ZW |
4207 | expression (&exp); |
4208 | if (exp.X_op == O_constant | |
4209 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 4210 | { |
c19d1205 ZW |
4211 | unwind.frame_size += exp.X_add_number; |
4212 | expression (&exp); | |
4213 | } | |
4214 | else | |
4215 | exp.X_op = O_illegal; | |
a737bd4d | 4216 | |
c19d1205 ZW |
4217 | if (exp.X_op != O_constant) |
4218 | { | |
4219 | as_bad (_("expected <offset>, <opcode>")); | |
4220 | ignore_rest_of_line (); | |
4221 | return; | |
4222 | } | |
a737bd4d | 4223 | |
c19d1205 | 4224 | count = 0; |
a737bd4d | 4225 | |
c19d1205 ZW |
4226 | /* Parse the opcode. */ |
4227 | for (;;) | |
4228 | { | |
4229 | if (count >= 16) | |
4230 | { | |
4231 | as_bad (_("unwind opcode too long")); | |
4232 | ignore_rest_of_line (); | |
a737bd4d | 4233 | } |
c19d1205 | 4234 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 4235 | { |
c19d1205 ZW |
4236 | as_bad (_("invalid unwind opcode")); |
4237 | ignore_rest_of_line (); | |
4238 | return; | |
a737bd4d | 4239 | } |
c19d1205 | 4240 | op[count++] = exp.X_add_number; |
a737bd4d | 4241 | |
c19d1205 ZW |
4242 | /* Parse the next byte. */ |
4243 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
4244 | break; | |
a737bd4d | 4245 | |
c19d1205 ZW |
4246 | expression (&exp); |
4247 | } | |
b99bd4ef | 4248 | |
c19d1205 ZW |
4249 | /* Add the opcode bytes in reverse order. */ |
4250 | while (count--) | |
4251 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 4252 | |
c19d1205 | 4253 | demand_empty_rest_of_line (); |
b99bd4ef | 4254 | } |
ee065d83 PB |
4255 | |
4256 | ||
4257 | /* Parse a .eabi_attribute directive. */ | |
4258 | ||
4259 | static void | |
4260 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) | |
4261 | { | |
ee3c0378 AS |
4262 | int tag = s_vendor_attribute (OBJ_ATTR_PROC); |
4263 | ||
4264 | if (tag < NUM_KNOWN_OBJ_ATTRIBUTES) | |
4265 | attributes_set_explicitly[tag] = 1; | |
ee065d83 | 4266 | } |
8463be01 | 4267 | #endif /* OBJ_ELF */ |
ee065d83 PB |
4268 | |
4269 | static void s_arm_arch (int); | |
7a1d4c38 | 4270 | static void s_arm_object_arch (int); |
ee065d83 PB |
4271 | static void s_arm_cpu (int); |
4272 | static void s_arm_fpu (int); | |
b99bd4ef | 4273 | |
f0927246 NC |
4274 | #ifdef TE_PE |
4275 | ||
4276 | static void | |
5f4273c7 | 4277 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
f0927246 NC |
4278 | { |
4279 | expressionS exp; | |
4280 | ||
4281 | do | |
4282 | { | |
4283 | expression (&exp); | |
4284 | if (exp.X_op == O_symbol) | |
4285 | exp.X_op = O_secrel; | |
4286 | ||
4287 | emit_expr (&exp, 4); | |
4288 | } | |
4289 | while (*input_line_pointer++ == ','); | |
4290 | ||
4291 | input_line_pointer--; | |
4292 | demand_empty_rest_of_line (); | |
4293 | } | |
4294 | #endif /* TE_PE */ | |
4295 | ||
c19d1205 ZW |
4296 | /* This table describes all the machine specific pseudo-ops the assembler |
4297 | has to support. The fields are: | |
4298 | pseudo-op name without dot | |
4299 | function to call to execute this pseudo-op | |
4300 | Integer arg to pass to the function. */ | |
b99bd4ef | 4301 | |
c19d1205 | 4302 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 4303 | { |
c19d1205 ZW |
4304 | /* Never called because '.req' does not start a line. */ |
4305 | { "req", s_req, 0 }, | |
dcbf9037 JB |
4306 | /* Following two are likewise never called. */ |
4307 | { "dn", s_dn, 0 }, | |
4308 | { "qn", s_qn, 0 }, | |
c19d1205 ZW |
4309 | { "unreq", s_unreq, 0 }, |
4310 | { "bss", s_bss, 0 }, | |
4311 | { "align", s_align, 0 }, | |
4312 | { "arm", s_arm, 0 }, | |
4313 | { "thumb", s_thumb, 0 }, | |
4314 | { "code", s_code, 0 }, | |
4315 | { "force_thumb", s_force_thumb, 0 }, | |
4316 | { "thumb_func", s_thumb_func, 0 }, | |
4317 | { "thumb_set", s_thumb_set, 0 }, | |
4318 | { "even", s_even, 0 }, | |
4319 | { "ltorg", s_ltorg, 0 }, | |
4320 | { "pool", s_ltorg, 0 }, | |
4321 | { "syntax", s_syntax, 0 }, | |
8463be01 PB |
4322 | { "cpu", s_arm_cpu, 0 }, |
4323 | { "arch", s_arm_arch, 0 }, | |
7a1d4c38 | 4324 | { "object_arch", s_arm_object_arch, 0 }, |
8463be01 | 4325 | { "fpu", s_arm_fpu, 0 }, |
c19d1205 | 4326 | #ifdef OBJ_ELF |
c921be7d NC |
4327 | { "word", s_arm_elf_cons, 4 }, |
4328 | { "long", s_arm_elf_cons, 4 }, | |
4329 | { "inst.n", s_arm_elf_inst, 2 }, | |
4330 | { "inst.w", s_arm_elf_inst, 4 }, | |
4331 | { "inst", s_arm_elf_inst, 0 }, | |
4332 | { "rel31", s_arm_rel31, 0 }, | |
c19d1205 ZW |
4333 | { "fnstart", s_arm_unwind_fnstart, 0 }, |
4334 | { "fnend", s_arm_unwind_fnend, 0 }, | |
4335 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
4336 | { "personality", s_arm_unwind_personality, 0 }, | |
4337 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
4338 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
4339 | { "save", s_arm_unwind_save, 0 }, | |
fa073d69 | 4340 | { "vsave", s_arm_unwind_save, 1 }, |
c19d1205 ZW |
4341 | { "movsp", s_arm_unwind_movsp, 0 }, |
4342 | { "pad", s_arm_unwind_pad, 0 }, | |
4343 | { "setfp", s_arm_unwind_setfp, 0 }, | |
4344 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
ee065d83 | 4345 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, |
c19d1205 ZW |
4346 | #else |
4347 | { "word", cons, 4}, | |
f0927246 NC |
4348 | |
4349 | /* These are used for dwarf. */ | |
4350 | {"2byte", cons, 2}, | |
4351 | {"4byte", cons, 4}, | |
4352 | {"8byte", cons, 8}, | |
4353 | /* These are used for dwarf2. */ | |
4354 | { "file", (void (*) (int)) dwarf2_directive_file, 0 }, | |
4355 | { "loc", dwarf2_directive_loc, 0 }, | |
4356 | { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, | |
c19d1205 ZW |
4357 | #endif |
4358 | { "extend", float_cons, 'x' }, | |
4359 | { "ldouble", float_cons, 'x' }, | |
4360 | { "packed", float_cons, 'p' }, | |
f0927246 NC |
4361 | #ifdef TE_PE |
4362 | {"secrel32", pe_directive_secrel, 0}, | |
4363 | #endif | |
c19d1205 ZW |
4364 | { 0, 0, 0 } |
4365 | }; | |
4366 | \f | |
4367 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 4368 | |
c19d1205 ZW |
4369 | /* Generic immediate-value read function for use in insn parsing. |
4370 | STR points to the beginning of the immediate (the leading #); | |
4371 | VAL receives the value; if the value is outside [MIN, MAX] | |
4372 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
4373 | optional. */ | |
b99bd4ef | 4374 | |
c19d1205 ZW |
4375 | static int |
4376 | parse_immediate (char **str, int *val, int min, int max, | |
4377 | bfd_boolean prefix_opt) | |
4378 | { | |
4379 | expressionS exp; | |
4380 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); | |
4381 | if (exp.X_op != O_constant) | |
b99bd4ef | 4382 | { |
c19d1205 ZW |
4383 | inst.error = _("constant expression required"); |
4384 | return FAIL; | |
4385 | } | |
b99bd4ef | 4386 | |
c19d1205 ZW |
4387 | if (exp.X_add_number < min || exp.X_add_number > max) |
4388 | { | |
4389 | inst.error = _("immediate value out of range"); | |
4390 | return FAIL; | |
4391 | } | |
b99bd4ef | 4392 | |
c19d1205 ZW |
4393 | *val = exp.X_add_number; |
4394 | return SUCCESS; | |
4395 | } | |
b99bd4ef | 4396 | |
5287ad62 | 4397 | /* Less-generic immediate-value read function with the possibility of loading a |
036dc3f7 | 4398 | big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate |
5287ad62 JB |
4399 | instructions. Puts the result directly in inst.operands[i]. */ |
4400 | ||
4401 | static int | |
4402 | parse_big_immediate (char **str, int i) | |
4403 | { | |
4404 | expressionS exp; | |
4405 | char *ptr = *str; | |
4406 | ||
4407 | my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); | |
4408 | ||
4409 | if (exp.X_op == O_constant) | |
036dc3f7 PB |
4410 | { |
4411 | inst.operands[i].imm = exp.X_add_number & 0xffffffff; | |
4412 | /* If we're on a 64-bit host, then a 64-bit number can be returned using | |
4413 | O_constant. We have to be careful not to break compilation for | |
4414 | 32-bit X_add_number, though. */ | |
4415 | if ((exp.X_add_number & ~0xffffffffl) != 0) | |
4416 | { | |
4417 | /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */ | |
4418 | inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff; | |
4419 | inst.operands[i].regisimm = 1; | |
4420 | } | |
4421 | } | |
5287ad62 | 4422 | else if (exp.X_op == O_big |
95b75c01 | 4423 | && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32) |
5287ad62 JB |
4424 | { |
4425 | unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; | |
95b75c01 | 4426 | |
5287ad62 JB |
4427 | /* Bignums have their least significant bits in |
4428 | generic_bignum[0]. Make sure we put 32 bits in imm and | |
4429 | 32 bits in reg, in a (hopefully) portable way. */ | |
9c2799c2 | 4430 | gas_assert (parts != 0); |
95b75c01 NC |
4431 | |
4432 | /* Make sure that the number is not too big. | |
4433 | PR 11972: Bignums can now be sign-extended to the | |
4434 | size of a .octa so check that the out of range bits | |
4435 | are all zero or all one. */ | |
4436 | if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64) | |
4437 | { | |
4438 | LITTLENUM_TYPE m = -1; | |
4439 | ||
4440 | if (generic_bignum[parts * 2] != 0 | |
4441 | && generic_bignum[parts * 2] != m) | |
4442 | return FAIL; | |
4443 | ||
4444 | for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++) | |
4445 | if (generic_bignum[j] != generic_bignum[j-1]) | |
4446 | return FAIL; | |
4447 | } | |
4448 | ||
5287ad62 JB |
4449 | inst.operands[i].imm = 0; |
4450 | for (j = 0; j < parts; j++, idx++) | |
4451 | inst.operands[i].imm |= generic_bignum[idx] | |
4452 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
4453 | inst.operands[i].reg = 0; | |
4454 | for (j = 0; j < parts; j++, idx++) | |
4455 | inst.operands[i].reg |= generic_bignum[idx] | |
4456 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
4457 | inst.operands[i].regisimm = 1; | |
4458 | } | |
4459 | else | |
4460 | return FAIL; | |
5f4273c7 | 4461 | |
5287ad62 JB |
4462 | *str = ptr; |
4463 | ||
4464 | return SUCCESS; | |
4465 | } | |
4466 | ||
c19d1205 ZW |
4467 | /* Returns the pseudo-register number of an FPA immediate constant, |
4468 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 4469 | |
c19d1205 ZW |
4470 | static int |
4471 | parse_fpa_immediate (char ** str) | |
4472 | { | |
4473 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4474 | char * save_in; | |
4475 | expressionS exp; | |
4476 | int i; | |
4477 | int j; | |
b99bd4ef | 4478 | |
c19d1205 ZW |
4479 | /* First try and match exact strings, this is to guarantee |
4480 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 4481 | |
c19d1205 ZW |
4482 | for (i = 0; fp_const[i]; i++) |
4483 | { | |
4484 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 4485 | { |
c19d1205 | 4486 | char *start = *str; |
b99bd4ef | 4487 | |
c19d1205 ZW |
4488 | *str += strlen (fp_const[i]); |
4489 | if (is_end_of_line[(unsigned char) **str]) | |
4490 | return i + 8; | |
4491 | *str = start; | |
4492 | } | |
4493 | } | |
b99bd4ef | 4494 | |
c19d1205 ZW |
4495 | /* Just because we didn't get a match doesn't mean that the constant |
4496 | isn't valid, just that it is in a format that we don't | |
4497 | automatically recognize. Try parsing it with the standard | |
4498 | expression routines. */ | |
b99bd4ef | 4499 | |
c19d1205 | 4500 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 4501 | |
c19d1205 ZW |
4502 | /* Look for a raw floating point number. */ |
4503 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
4504 | && is_end_of_line[(unsigned char) *save_in]) | |
4505 | { | |
4506 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4507 | { | |
4508 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 4509 | { |
c19d1205 ZW |
4510 | if (words[j] != fp_values[i][j]) |
4511 | break; | |
b99bd4ef NC |
4512 | } |
4513 | ||
c19d1205 | 4514 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 4515 | { |
c19d1205 ZW |
4516 | *str = save_in; |
4517 | return i + 8; | |
b99bd4ef NC |
4518 | } |
4519 | } | |
4520 | } | |
b99bd4ef | 4521 | |
c19d1205 ZW |
4522 | /* Try and parse a more complex expression, this will probably fail |
4523 | unless the code uses a floating point prefix (eg "0f"). */ | |
4524 | save_in = input_line_pointer; | |
4525 | input_line_pointer = *str; | |
4526 | if (expression (&exp) == absolute_section | |
4527 | && exp.X_op == O_big | |
4528 | && exp.X_add_number < 0) | |
4529 | { | |
4530 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
4531 | Ditto for 15. */ | |
4532 | if (gen_to_words (words, 5, (long) 15) == 0) | |
4533 | { | |
4534 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4535 | { | |
4536 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
4537 | { | |
4538 | if (words[j] != fp_values[i][j]) | |
4539 | break; | |
4540 | } | |
b99bd4ef | 4541 | |
c19d1205 ZW |
4542 | if (j == MAX_LITTLENUMS) |
4543 | { | |
4544 | *str = input_line_pointer; | |
4545 | input_line_pointer = save_in; | |
4546 | return i + 8; | |
4547 | } | |
4548 | } | |
4549 | } | |
b99bd4ef NC |
4550 | } |
4551 | ||
c19d1205 ZW |
4552 | *str = input_line_pointer; |
4553 | input_line_pointer = save_in; | |
4554 | inst.error = _("invalid FPA immediate expression"); | |
4555 | return FAIL; | |
b99bd4ef NC |
4556 | } |
4557 | ||
136da414 JB |
4558 | /* Returns 1 if a number has "quarter-precision" float format |
4559 | 0baBbbbbbc defgh000 00000000 00000000. */ | |
4560 | ||
4561 | static int | |
4562 | is_quarter_float (unsigned imm) | |
4563 | { | |
4564 | int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; | |
4565 | return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; | |
4566 | } | |
4567 | ||
4568 | /* Parse an 8-bit "quarter-precision" floating point number of the form: | |
4569 | 0baBbbbbbc defgh000 00000000 00000000. | |
c96612cc JB |
4570 | The zero and minus-zero cases need special handling, since they can't be |
4571 | encoded in the "quarter-precision" float format, but can nonetheless be | |
4572 | loaded as integer constants. */ | |
136da414 JB |
4573 | |
4574 | static unsigned | |
4575 | parse_qfloat_immediate (char **ccp, int *immed) | |
4576 | { | |
4577 | char *str = *ccp; | |
c96612cc | 4578 | char *fpnum; |
136da414 | 4579 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
c96612cc | 4580 | int found_fpchar = 0; |
5f4273c7 | 4581 | |
136da414 | 4582 | skip_past_char (&str, '#'); |
5f4273c7 | 4583 | |
c96612cc JB |
4584 | /* We must not accidentally parse an integer as a floating-point number. Make |
4585 | sure that the value we parse is not an integer by checking for special | |
4586 | characters '.' or 'e'. | |
4587 | FIXME: This is a horrible hack, but doing better is tricky because type | |
4588 | information isn't in a very usable state at parse time. */ | |
4589 | fpnum = str; | |
4590 | skip_whitespace (fpnum); | |
4591 | ||
4592 | if (strncmp (fpnum, "0x", 2) == 0) | |
4593 | return FAIL; | |
4594 | else | |
4595 | { | |
4596 | for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) | |
4597 | if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') | |
4598 | { | |
4599 | found_fpchar = 1; | |
4600 | break; | |
4601 | } | |
4602 | ||
4603 | if (!found_fpchar) | |
4604 | return FAIL; | |
4605 | } | |
5f4273c7 | 4606 | |
136da414 JB |
4607 | if ((str = atof_ieee (str, 's', words)) != NULL) |
4608 | { | |
4609 | unsigned fpword = 0; | |
4610 | int i; | |
5f4273c7 | 4611 | |
136da414 JB |
4612 | /* Our FP word must be 32 bits (single-precision FP). */ |
4613 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) | |
4614 | { | |
4615 | fpword <<= LITTLENUM_NUMBER_OF_BITS; | |
4616 | fpword |= words[i]; | |
4617 | } | |
5f4273c7 | 4618 | |
c96612cc | 4619 | if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) |
136da414 JB |
4620 | *immed = fpword; |
4621 | else | |
4622 | return FAIL; | |
4623 | ||
4624 | *ccp = str; | |
5f4273c7 | 4625 | |
136da414 JB |
4626 | return SUCCESS; |
4627 | } | |
5f4273c7 | 4628 | |
136da414 JB |
4629 | return FAIL; |
4630 | } | |
4631 | ||
c19d1205 ZW |
4632 | /* Shift operands. */ |
4633 | enum shift_kind | |
b99bd4ef | 4634 | { |
c19d1205 ZW |
4635 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX |
4636 | }; | |
b99bd4ef | 4637 | |
c19d1205 ZW |
4638 | struct asm_shift_name |
4639 | { | |
4640 | const char *name; | |
4641 | enum shift_kind kind; | |
4642 | }; | |
b99bd4ef | 4643 | |
c19d1205 ZW |
4644 | /* Third argument to parse_shift. */ |
4645 | enum parse_shift_mode | |
4646 | { | |
4647 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
4648 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
4649 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
4650 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
4651 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
4652 | }; | |
b99bd4ef | 4653 | |
c19d1205 ZW |
4654 | /* Parse a <shift> specifier on an ARM data processing instruction. |
4655 | This has three forms: | |
b99bd4ef | 4656 | |
c19d1205 ZW |
4657 | (LSL|LSR|ASL|ASR|ROR) Rs |
4658 | (LSL|LSR|ASL|ASR|ROR) #imm | |
4659 | RRX | |
b99bd4ef | 4660 | |
c19d1205 ZW |
4661 | Note that ASL is assimilated to LSL in the instruction encoding, and |
4662 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 4663 | |
c19d1205 ZW |
4664 | static int |
4665 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 4666 | { |
c19d1205 ZW |
4667 | const struct asm_shift_name *shift_name; |
4668 | enum shift_kind shift; | |
4669 | char *s = *str; | |
4670 | char *p = s; | |
4671 | int reg; | |
b99bd4ef | 4672 | |
c19d1205 ZW |
4673 | for (p = *str; ISALPHA (*p); p++) |
4674 | ; | |
b99bd4ef | 4675 | |
c19d1205 | 4676 | if (p == *str) |
b99bd4ef | 4677 | { |
c19d1205 ZW |
4678 | inst.error = _("shift expression expected"); |
4679 | return FAIL; | |
b99bd4ef NC |
4680 | } |
4681 | ||
21d799b5 NC |
4682 | shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str, |
4683 | p - *str); | |
c19d1205 ZW |
4684 | |
4685 | if (shift_name == NULL) | |
b99bd4ef | 4686 | { |
c19d1205 ZW |
4687 | inst.error = _("shift expression expected"); |
4688 | return FAIL; | |
b99bd4ef NC |
4689 | } |
4690 | ||
c19d1205 | 4691 | shift = shift_name->kind; |
b99bd4ef | 4692 | |
c19d1205 ZW |
4693 | switch (mode) |
4694 | { | |
4695 | case NO_SHIFT_RESTRICT: | |
4696 | case SHIFT_IMMEDIATE: break; | |
b99bd4ef | 4697 | |
c19d1205 ZW |
4698 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
4699 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
4700 | { | |
4701 | inst.error = _("'LSL' or 'ASR' required"); | |
4702 | return FAIL; | |
4703 | } | |
4704 | break; | |
b99bd4ef | 4705 | |
c19d1205 ZW |
4706 | case SHIFT_LSL_IMMEDIATE: |
4707 | if (shift != SHIFT_LSL) | |
4708 | { | |
4709 | inst.error = _("'LSL' required"); | |
4710 | return FAIL; | |
4711 | } | |
4712 | break; | |
b99bd4ef | 4713 | |
c19d1205 ZW |
4714 | case SHIFT_ASR_IMMEDIATE: |
4715 | if (shift != SHIFT_ASR) | |
4716 | { | |
4717 | inst.error = _("'ASR' required"); | |
4718 | return FAIL; | |
4719 | } | |
4720 | break; | |
b99bd4ef | 4721 | |
c19d1205 ZW |
4722 | default: abort (); |
4723 | } | |
b99bd4ef | 4724 | |
c19d1205 ZW |
4725 | if (shift != SHIFT_RRX) |
4726 | { | |
4727 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
4728 | skip_whitespace (p); | |
b99bd4ef | 4729 | |
c19d1205 | 4730 | if (mode == NO_SHIFT_RESTRICT |
dcbf9037 | 4731 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4732 | { |
4733 | inst.operands[i].imm = reg; | |
4734 | inst.operands[i].immisreg = 1; | |
4735 | } | |
4736 | else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4737 | return FAIL; | |
4738 | } | |
4739 | inst.operands[i].shift_kind = shift; | |
4740 | inst.operands[i].shifted = 1; | |
4741 | *str = p; | |
4742 | return SUCCESS; | |
b99bd4ef NC |
4743 | } |
4744 | ||
c19d1205 | 4745 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 4746 | |
c19d1205 ZW |
4747 | #<immediate> |
4748 | #<immediate>, <rotate> | |
4749 | <Rm> | |
4750 | <Rm>, <shift> | |
b99bd4ef | 4751 | |
c19d1205 ZW |
4752 | where <shift> is defined by parse_shift above, and <rotate> is a |
4753 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 4754 | is deferred to md_apply_fix. */ |
b99bd4ef | 4755 | |
c19d1205 ZW |
4756 | static int |
4757 | parse_shifter_operand (char **str, int i) | |
4758 | { | |
4759 | int value; | |
91d6fa6a | 4760 | expressionS exp; |
b99bd4ef | 4761 | |
dcbf9037 | 4762 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4763 | { |
4764 | inst.operands[i].reg = value; | |
4765 | inst.operands[i].isreg = 1; | |
b99bd4ef | 4766 | |
c19d1205 ZW |
4767 | /* parse_shift will override this if appropriate */ |
4768 | inst.reloc.exp.X_op = O_constant; | |
4769 | inst.reloc.exp.X_add_number = 0; | |
b99bd4ef | 4770 | |
c19d1205 ZW |
4771 | if (skip_past_comma (str) == FAIL) |
4772 | return SUCCESS; | |
b99bd4ef | 4773 | |
c19d1205 ZW |
4774 | /* Shift operation on register. */ |
4775 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
4776 | } |
4777 | ||
c19d1205 ZW |
4778 | if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) |
4779 | return FAIL; | |
b99bd4ef | 4780 | |
c19d1205 | 4781 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 4782 | { |
c19d1205 | 4783 | /* #x, y -- ie explicit rotation by Y. */ |
91d6fa6a | 4784 | if (my_get_expression (&exp, str, GE_NO_PREFIX)) |
c19d1205 | 4785 | return FAIL; |
b99bd4ef | 4786 | |
91d6fa6a | 4787 | if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant) |
c19d1205 ZW |
4788 | { |
4789 | inst.error = _("constant expression expected"); | |
4790 | return FAIL; | |
4791 | } | |
b99bd4ef | 4792 | |
91d6fa6a | 4793 | value = exp.X_add_number; |
c19d1205 ZW |
4794 | if (value < 0 || value > 30 || value % 2 != 0) |
4795 | { | |
4796 | inst.error = _("invalid rotation"); | |
4797 | return FAIL; | |
4798 | } | |
4799 | if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) | |
4800 | { | |
4801 | inst.error = _("invalid constant"); | |
4802 | return FAIL; | |
4803 | } | |
09d92015 | 4804 | |
55cf6793 | 4805 | /* Convert to decoded value. md_apply_fix will put it back. */ |
c19d1205 ZW |
4806 | inst.reloc.exp.X_add_number |
4807 | = (((inst.reloc.exp.X_add_number << (32 - value)) | |
4808 | | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff); | |
09d92015 MM |
4809 | } |
4810 | ||
c19d1205 ZW |
4811 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; |
4812 | inst.reloc.pc_rel = 0; | |
4813 | return SUCCESS; | |
09d92015 MM |
4814 | } |
4815 | ||
4962c51a MS |
4816 | /* Group relocation information. Each entry in the table contains the |
4817 | textual name of the relocation as may appear in assembler source | |
4818 | and must end with a colon. | |
4819 | Along with this textual name are the relocation codes to be used if | |
4820 | the corresponding instruction is an ALU instruction (ADD or SUB only), | |
4821 | an LDR, an LDRS, or an LDC. */ | |
4822 | ||
4823 | struct group_reloc_table_entry | |
4824 | { | |
4825 | const char *name; | |
4826 | int alu_code; | |
4827 | int ldr_code; | |
4828 | int ldrs_code; | |
4829 | int ldc_code; | |
4830 | }; | |
4831 | ||
4832 | typedef enum | |
4833 | { | |
4834 | /* Varieties of non-ALU group relocation. */ | |
4835 | ||
4836 | GROUP_LDR, | |
4837 | GROUP_LDRS, | |
4838 | GROUP_LDC | |
4839 | } group_reloc_type; | |
4840 | ||
4841 | static struct group_reloc_table_entry group_reloc_table[] = | |
4842 | { /* Program counter relative: */ | |
4843 | { "pc_g0_nc", | |
4844 | BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ | |
4845 | 0, /* LDR */ | |
4846 | 0, /* LDRS */ | |
4847 | 0 }, /* LDC */ | |
4848 | { "pc_g0", | |
4849 | BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ | |
4850 | BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ | |
4851 | BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ | |
4852 | BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ | |
4853 | { "pc_g1_nc", | |
4854 | BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ | |
4855 | 0, /* LDR */ | |
4856 | 0, /* LDRS */ | |
4857 | 0 }, /* LDC */ | |
4858 | { "pc_g1", | |
4859 | BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ | |
4860 | BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ | |
4861 | BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ | |
4862 | BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ | |
4863 | { "pc_g2", | |
4864 | BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ | |
4865 | BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ | |
4866 | BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ | |
4867 | BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ | |
4868 | /* Section base relative */ | |
4869 | { "sb_g0_nc", | |
4870 | BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ | |
4871 | 0, /* LDR */ | |
4872 | 0, /* LDRS */ | |
4873 | 0 }, /* LDC */ | |
4874 | { "sb_g0", | |
4875 | BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ | |
4876 | BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ | |
4877 | BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ | |
4878 | BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ | |
4879 | { "sb_g1_nc", | |
4880 | BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ | |
4881 | 0, /* LDR */ | |
4882 | 0, /* LDRS */ | |
4883 | 0 }, /* LDC */ | |
4884 | { "sb_g1", | |
4885 | BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ | |
4886 | BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ | |
4887 | BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ | |
4888 | BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ | |
4889 | { "sb_g2", | |
4890 | BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ | |
4891 | BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ | |
4892 | BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ | |
4893 | BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ | |
4894 | ||
4895 | /* Given the address of a pointer pointing to the textual name of a group | |
4896 | relocation as may appear in assembler source, attempt to find its details | |
4897 | in group_reloc_table. The pointer will be updated to the character after | |
4898 | the trailing colon. On failure, FAIL will be returned; SUCCESS | |
4899 | otherwise. On success, *entry will be updated to point at the relevant | |
4900 | group_reloc_table entry. */ | |
4901 | ||
4902 | static int | |
4903 | find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) | |
4904 | { | |
4905 | unsigned int i; | |
4906 | for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) | |
4907 | { | |
4908 | int length = strlen (group_reloc_table[i].name); | |
4909 | ||
5f4273c7 NC |
4910 | if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 |
4911 | && (*str)[length] == ':') | |
4962c51a MS |
4912 | { |
4913 | *out = &group_reloc_table[i]; | |
4914 | *str += (length + 1); | |
4915 | return SUCCESS; | |
4916 | } | |
4917 | } | |
4918 | ||
4919 | return FAIL; | |
4920 | } | |
4921 | ||
4922 | /* Parse a <shifter_operand> for an ARM data processing instruction | |
4923 | (as for parse_shifter_operand) where group relocations are allowed: | |
4924 | ||
4925 | #<immediate> | |
4926 | #<immediate>, <rotate> | |
4927 | #:<group_reloc>:<expression> | |
4928 | <Rm> | |
4929 | <Rm>, <shift> | |
4930 | ||
4931 | where <group_reloc> is one of the strings defined in group_reloc_table. | |
4932 | The hashes are optional. | |
4933 | ||
4934 | Everything else is as for parse_shifter_operand. */ | |
4935 | ||
4936 | static parse_operand_result | |
4937 | parse_shifter_operand_group_reloc (char **str, int i) | |
4938 | { | |
4939 | /* Determine if we have the sequence of characters #: or just : | |
4940 | coming next. If we do, then we check for a group relocation. | |
4941 | If we don't, punt the whole lot to parse_shifter_operand. */ | |
4942 | ||
4943 | if (((*str)[0] == '#' && (*str)[1] == ':') | |
4944 | || (*str)[0] == ':') | |
4945 | { | |
4946 | struct group_reloc_table_entry *entry; | |
4947 | ||
4948 | if ((*str)[0] == '#') | |
4949 | (*str) += 2; | |
4950 | else | |
4951 | (*str)++; | |
4952 | ||
4953 | /* Try to parse a group relocation. Anything else is an error. */ | |
4954 | if (find_group_reloc_table_entry (str, &entry) == FAIL) | |
4955 | { | |
4956 | inst.error = _("unknown group relocation"); | |
4957 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
4958 | } | |
4959 | ||
4960 | /* We now have the group relocation table entry corresponding to | |
4961 | the name in the assembler source. Next, we parse the expression. */ | |
4962 | if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) | |
4963 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
4964 | ||
4965 | /* Record the relocation type (always the ALU variant here). */ | |
21d799b5 | 4966 | inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code; |
9c2799c2 | 4967 | gas_assert (inst.reloc.type != 0); |
4962c51a MS |
4968 | |
4969 | return PARSE_OPERAND_SUCCESS; | |
4970 | } | |
4971 | else | |
4972 | return parse_shifter_operand (str, i) == SUCCESS | |
4973 | ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; | |
4974 | ||
4975 | /* Never reached. */ | |
4976 | } | |
4977 | ||
8e560766 MGD |
4978 | /* Parse a Neon alignment expression. Information is written to |
4979 | inst.operands[i]. We assume the initial ':' has been skipped. | |
4980 | ||
4981 | align .imm = align << 8, .immisalign=1, .preind=0 */ | |
4982 | static parse_operand_result | |
4983 | parse_neon_alignment (char **str, int i) | |
4984 | { | |
4985 | char *p = *str; | |
4986 | expressionS exp; | |
4987 | ||
4988 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
4989 | ||
4990 | if (exp.X_op != O_constant) | |
4991 | { | |
4992 | inst.error = _("alignment must be constant"); | |
4993 | return PARSE_OPERAND_FAIL; | |
4994 | } | |
4995 | ||
4996 | inst.operands[i].imm = exp.X_add_number << 8; | |
4997 | inst.operands[i].immisalign = 1; | |
4998 | /* Alignments are not pre-indexes. */ | |
4999 | inst.operands[i].preind = 0; | |
5000 | ||
5001 | *str = p; | |
5002 | return PARSE_OPERAND_SUCCESS; | |
5003 | } | |
5004 | ||
c19d1205 ZW |
5005 | /* Parse all forms of an ARM address expression. Information is written |
5006 | to inst.operands[i] and/or inst.reloc. | |
09d92015 | 5007 | |
c19d1205 | 5008 | Preindexed addressing (.preind=1): |
09d92015 | 5009 | |
c19d1205 ZW |
5010 | [Rn, #offset] .reg=Rn .reloc.exp=offset |
5011 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5012 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5013 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5014 | |
c19d1205 | 5015 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 5016 | |
c19d1205 | 5017 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 5018 | |
c19d1205 ZW |
5019 | [Rn], #offset .reg=Rn .reloc.exp=offset |
5020 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5021 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5022 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5023 | |
c19d1205 | 5024 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 5025 | |
c19d1205 | 5026 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 5027 | |
c19d1205 | 5028 | Other: |
09d92015 | 5029 | |
c19d1205 ZW |
5030 | [Rn]{!} shorthand for [Rn,#0]{!} |
5031 | =immediate .isreg=0 .reloc.exp=immediate | |
5032 | label .reg=PC .reloc.pc_rel=1 .reloc.exp=label | |
09d92015 | 5033 | |
c19d1205 ZW |
5034 | It is the caller's responsibility to check for addressing modes not |
5035 | supported by the instruction, and to set inst.reloc.type. */ | |
5036 | ||
4962c51a MS |
5037 | static parse_operand_result |
5038 | parse_address_main (char **str, int i, int group_relocations, | |
5039 | group_reloc_type group_type) | |
09d92015 | 5040 | { |
c19d1205 ZW |
5041 | char *p = *str; |
5042 | int reg; | |
09d92015 | 5043 | |
c19d1205 | 5044 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 5045 | { |
c19d1205 ZW |
5046 | if (skip_past_char (&p, '=') == FAIL) |
5047 | { | |
974da60d | 5048 | /* Bare address - translate to PC-relative offset. */ |
c19d1205 ZW |
5049 | inst.reloc.pc_rel = 1; |
5050 | inst.operands[i].reg = REG_PC; | |
5051 | inst.operands[i].isreg = 1; | |
5052 | inst.operands[i].preind = 1; | |
5053 | } | |
974da60d | 5054 | /* Otherwise a load-constant pseudo op, no special treatment needed here. */ |
09d92015 | 5055 | |
c19d1205 | 5056 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) |
4962c51a | 5057 | return PARSE_OPERAND_FAIL; |
09d92015 | 5058 | |
c19d1205 | 5059 | *str = p; |
4962c51a | 5060 | return PARSE_OPERAND_SUCCESS; |
09d92015 MM |
5061 | } |
5062 | ||
dcbf9037 | 5063 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
09d92015 | 5064 | { |
c19d1205 | 5065 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
4962c51a | 5066 | return PARSE_OPERAND_FAIL; |
09d92015 | 5067 | } |
c19d1205 ZW |
5068 | inst.operands[i].reg = reg; |
5069 | inst.operands[i].isreg = 1; | |
09d92015 | 5070 | |
c19d1205 | 5071 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5072 | { |
c19d1205 | 5073 | inst.operands[i].preind = 1; |
09d92015 | 5074 | |
c19d1205 ZW |
5075 | if (*p == '+') p++; |
5076 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
5077 | ||
dcbf9037 | 5078 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
09d92015 | 5079 | { |
c19d1205 ZW |
5080 | inst.operands[i].imm = reg; |
5081 | inst.operands[i].immisreg = 1; | |
5082 | ||
5083 | if (skip_past_comma (&p) == SUCCESS) | |
5084 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5085 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5086 | } |
5287ad62 | 5087 | else if (skip_past_char (&p, ':') == SUCCESS) |
8e560766 MGD |
5088 | { |
5089 | /* FIXME: '@' should be used here, but it's filtered out by generic | |
5090 | code before we get to see it here. This may be subject to | |
5091 | change. */ | |
5092 | parse_operand_result result = parse_neon_alignment (&p, i); | |
5093 | ||
5094 | if (result != PARSE_OPERAND_SUCCESS) | |
5095 | return result; | |
5096 | } | |
c19d1205 ZW |
5097 | else |
5098 | { | |
5099 | if (inst.operands[i].negative) | |
5100 | { | |
5101 | inst.operands[i].negative = 0; | |
5102 | p--; | |
5103 | } | |
4962c51a | 5104 | |
5f4273c7 NC |
5105 | if (group_relocations |
5106 | && ((*p == '#' && *(p + 1) == ':') || *p == ':')) | |
4962c51a MS |
5107 | { |
5108 | struct group_reloc_table_entry *entry; | |
5109 | ||
5110 | /* Skip over the #: or : sequence. */ | |
5111 | if (*p == '#') | |
5112 | p += 2; | |
5113 | else | |
5114 | p++; | |
5115 | ||
5116 | /* Try to parse a group relocation. Anything else is an | |
5117 | error. */ | |
5118 | if (find_group_reloc_table_entry (&p, &entry) == FAIL) | |
5119 | { | |
5120 | inst.error = _("unknown group relocation"); | |
5121 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5122 | } | |
5123 | ||
5124 | /* We now have the group relocation table entry corresponding to | |
5125 | the name in the assembler source. Next, we parse the | |
5126 | expression. */ | |
5127 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5128 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5129 | ||
5130 | /* Record the relocation type. */ | |
5131 | switch (group_type) | |
5132 | { | |
5133 | case GROUP_LDR: | |
21d799b5 | 5134 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code; |
4962c51a MS |
5135 | break; |
5136 | ||
5137 | case GROUP_LDRS: | |
21d799b5 | 5138 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code; |
4962c51a MS |
5139 | break; |
5140 | ||
5141 | case GROUP_LDC: | |
21d799b5 | 5142 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code; |
4962c51a MS |
5143 | break; |
5144 | ||
5145 | default: | |
9c2799c2 | 5146 | gas_assert (0); |
4962c51a MS |
5147 | } |
5148 | ||
5149 | if (inst.reloc.type == 0) | |
5150 | { | |
5151 | inst.error = _("this group relocation is not allowed on this instruction"); | |
5152 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5153 | } | |
5154 | } | |
5155 | else | |
5156 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
5157 | return PARSE_OPERAND_FAIL; | |
09d92015 MM |
5158 | } |
5159 | } | |
8e560766 MGD |
5160 | else if (skip_past_char (&p, ':') == SUCCESS) |
5161 | { | |
5162 | /* FIXME: '@' should be used here, but it's filtered out by generic code | |
5163 | before we get to see it here. This may be subject to change. */ | |
5164 | parse_operand_result result = parse_neon_alignment (&p, i); | |
5165 | ||
5166 | if (result != PARSE_OPERAND_SUCCESS) | |
5167 | return result; | |
5168 | } | |
09d92015 | 5169 | |
c19d1205 | 5170 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 5171 | { |
c19d1205 | 5172 | inst.error = _("']' expected"); |
4962c51a | 5173 | return PARSE_OPERAND_FAIL; |
09d92015 MM |
5174 | } |
5175 | ||
c19d1205 ZW |
5176 | if (skip_past_char (&p, '!') == SUCCESS) |
5177 | inst.operands[i].writeback = 1; | |
09d92015 | 5178 | |
c19d1205 | 5179 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5180 | { |
c19d1205 ZW |
5181 | if (skip_past_char (&p, '{') == SUCCESS) |
5182 | { | |
5183 | /* [Rn], {expr} - unindexed, with option */ | |
5184 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 5185 | 0, 255, TRUE) == FAIL) |
4962c51a | 5186 | return PARSE_OPERAND_FAIL; |
09d92015 | 5187 | |
c19d1205 ZW |
5188 | if (skip_past_char (&p, '}') == FAIL) |
5189 | { | |
5190 | inst.error = _("'}' expected at end of 'option' field"); | |
4962c51a | 5191 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5192 | } |
5193 | if (inst.operands[i].preind) | |
5194 | { | |
5195 | inst.error = _("cannot combine index with option"); | |
4962c51a | 5196 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5197 | } |
5198 | *str = p; | |
4962c51a | 5199 | return PARSE_OPERAND_SUCCESS; |
09d92015 | 5200 | } |
c19d1205 ZW |
5201 | else |
5202 | { | |
5203 | inst.operands[i].postind = 1; | |
5204 | inst.operands[i].writeback = 1; | |
09d92015 | 5205 | |
c19d1205 ZW |
5206 | if (inst.operands[i].preind) |
5207 | { | |
5208 | inst.error = _("cannot combine pre- and post-indexing"); | |
4962c51a | 5209 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5210 | } |
09d92015 | 5211 | |
c19d1205 ZW |
5212 | if (*p == '+') p++; |
5213 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 5214 | |
dcbf9037 | 5215 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 | 5216 | { |
5287ad62 JB |
5217 | /* We might be using the immediate for alignment already. If we |
5218 | are, OR the register number into the low-order bits. */ | |
5219 | if (inst.operands[i].immisalign) | |
5220 | inst.operands[i].imm |= reg; | |
5221 | else | |
5222 | inst.operands[i].imm = reg; | |
c19d1205 | 5223 | inst.operands[i].immisreg = 1; |
a737bd4d | 5224 | |
c19d1205 ZW |
5225 | if (skip_past_comma (&p) == SUCCESS) |
5226 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5227 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5228 | } |
5229 | else | |
5230 | { | |
5231 | if (inst.operands[i].negative) | |
5232 | { | |
5233 | inst.operands[i].negative = 0; | |
5234 | p--; | |
5235 | } | |
5236 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4962c51a | 5237 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5238 | } |
5239 | } | |
a737bd4d NC |
5240 | } |
5241 | ||
c19d1205 ZW |
5242 | /* If at this point neither .preind nor .postind is set, we have a |
5243 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
5244 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
5245 | { | |
5246 | inst.operands[i].preind = 1; | |
5247 | inst.reloc.exp.X_op = O_constant; | |
5248 | inst.reloc.exp.X_add_number = 0; | |
5249 | } | |
5250 | *str = p; | |
4962c51a MS |
5251 | return PARSE_OPERAND_SUCCESS; |
5252 | } | |
5253 | ||
5254 | static int | |
5255 | parse_address (char **str, int i) | |
5256 | { | |
21d799b5 | 5257 | return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS |
4962c51a MS |
5258 | ? SUCCESS : FAIL; |
5259 | } | |
5260 | ||
5261 | static parse_operand_result | |
5262 | parse_address_group_reloc (char **str, int i, group_reloc_type type) | |
5263 | { | |
5264 | return parse_address_main (str, i, 1, type); | |
a737bd4d NC |
5265 | } |
5266 | ||
b6895b4f PB |
5267 | /* Parse an operand for a MOVW or MOVT instruction. */ |
5268 | static int | |
5269 | parse_half (char **str) | |
5270 | { | |
5271 | char * p; | |
5f4273c7 | 5272 | |
b6895b4f PB |
5273 | p = *str; |
5274 | skip_past_char (&p, '#'); | |
5f4273c7 | 5275 | if (strncasecmp (p, ":lower16:", 9) == 0) |
b6895b4f PB |
5276 | inst.reloc.type = BFD_RELOC_ARM_MOVW; |
5277 | else if (strncasecmp (p, ":upper16:", 9) == 0) | |
5278 | inst.reloc.type = BFD_RELOC_ARM_MOVT; | |
5279 | ||
5280 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
5281 | { | |
5282 | p += 9; | |
5f4273c7 | 5283 | skip_whitespace (p); |
b6895b4f PB |
5284 | } |
5285 | ||
5286 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5287 | return FAIL; | |
5288 | ||
5289 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
5290 | { | |
5291 | if (inst.reloc.exp.X_op != O_constant) | |
5292 | { | |
5293 | inst.error = _("constant expression expected"); | |
5294 | return FAIL; | |
5295 | } | |
5296 | if (inst.reloc.exp.X_add_number < 0 | |
5297 | || inst.reloc.exp.X_add_number > 0xffff) | |
5298 | { | |
5299 | inst.error = _("immediate value out of range"); | |
5300 | return FAIL; | |
5301 | } | |
5302 | } | |
5303 | *str = p; | |
5304 | return SUCCESS; | |
5305 | } | |
5306 | ||
c19d1205 | 5307 | /* Miscellaneous. */ |
a737bd4d | 5308 | |
c19d1205 ZW |
5309 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
5310 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
5311 | static int | |
5312 | parse_psr (char **str) | |
09d92015 | 5313 | { |
c19d1205 ZW |
5314 | char *p; |
5315 | unsigned long psr_field; | |
62b3e311 PB |
5316 | const struct asm_psr *psr; |
5317 | char *start; | |
09d92015 | 5318 | |
c19d1205 ZW |
5319 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
5320 | feature for ease of use and backwards compatibility. */ | |
5321 | p = *str; | |
62b3e311 | 5322 | if (strncasecmp (p, "SPSR", 4) == 0) |
c19d1205 | 5323 | psr_field = SPSR_BIT; |
62b3e311 | 5324 | else if (strncasecmp (p, "CPSR", 4) == 0) |
c19d1205 ZW |
5325 | psr_field = 0; |
5326 | else | |
62b3e311 PB |
5327 | { |
5328 | start = p; | |
5329 | do | |
5330 | p++; | |
5331 | while (ISALNUM (*p) || *p == '_'); | |
5332 | ||
21d799b5 NC |
5333 | psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start, |
5334 | p - start); | |
62b3e311 PB |
5335 | if (!psr) |
5336 | return FAIL; | |
09d92015 | 5337 | |
62b3e311 PB |
5338 | *str = p; |
5339 | return psr->field; | |
5340 | } | |
09d92015 | 5341 | |
62b3e311 | 5342 | p += 4; |
c19d1205 ZW |
5343 | if (*p == '_') |
5344 | { | |
5345 | /* A suffix follows. */ | |
c19d1205 ZW |
5346 | p++; |
5347 | start = p; | |
a737bd4d | 5348 | |
c19d1205 ZW |
5349 | do |
5350 | p++; | |
5351 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 5352 | |
21d799b5 NC |
5353 | psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start, |
5354 | p - start); | |
c19d1205 ZW |
5355 | if (!psr) |
5356 | goto error; | |
a737bd4d | 5357 | |
c19d1205 | 5358 | psr_field |= psr->field; |
a737bd4d | 5359 | } |
c19d1205 | 5360 | else |
a737bd4d | 5361 | { |
c19d1205 ZW |
5362 | if (ISALNUM (*p)) |
5363 | goto error; /* Garbage after "[CS]PSR". */ | |
5364 | ||
5365 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 5366 | } |
c19d1205 ZW |
5367 | *str = p; |
5368 | return psr_field; | |
a737bd4d | 5369 | |
c19d1205 ZW |
5370 | error: |
5371 | inst.error = _("flag for {c}psr instruction expected"); | |
5372 | return FAIL; | |
a737bd4d NC |
5373 | } |
5374 | ||
c19d1205 ZW |
5375 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
5376 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 5377 | |
c19d1205 ZW |
5378 | static int |
5379 | parse_cps_flags (char **str) | |
a737bd4d | 5380 | { |
c19d1205 ZW |
5381 | int val = 0; |
5382 | int saw_a_flag = 0; | |
5383 | char *s = *str; | |
a737bd4d | 5384 | |
c19d1205 ZW |
5385 | for (;;) |
5386 | switch (*s++) | |
5387 | { | |
5388 | case '\0': case ',': | |
5389 | goto done; | |
a737bd4d | 5390 | |
c19d1205 ZW |
5391 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
5392 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
5393 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 5394 | |
c19d1205 ZW |
5395 | default: |
5396 | inst.error = _("unrecognized CPS flag"); | |
5397 | return FAIL; | |
5398 | } | |
a737bd4d | 5399 | |
c19d1205 ZW |
5400 | done: |
5401 | if (saw_a_flag == 0) | |
a737bd4d | 5402 | { |
c19d1205 ZW |
5403 | inst.error = _("missing CPS flags"); |
5404 | return FAIL; | |
a737bd4d | 5405 | } |
a737bd4d | 5406 | |
c19d1205 ZW |
5407 | *str = s - 1; |
5408 | return val; | |
a737bd4d NC |
5409 | } |
5410 | ||
c19d1205 ZW |
5411 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
5412 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
5413 | |
5414 | static int | |
c19d1205 | 5415 | parse_endian_specifier (char **str) |
a737bd4d | 5416 | { |
c19d1205 ZW |
5417 | int little_endian; |
5418 | char *s = *str; | |
a737bd4d | 5419 | |
c19d1205 ZW |
5420 | if (strncasecmp (s, "BE", 2)) |
5421 | little_endian = 0; | |
5422 | else if (strncasecmp (s, "LE", 2)) | |
5423 | little_endian = 1; | |
5424 | else | |
a737bd4d | 5425 | { |
c19d1205 | 5426 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5427 | return FAIL; |
5428 | } | |
5429 | ||
c19d1205 | 5430 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 5431 | { |
c19d1205 | 5432 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5433 | return FAIL; |
5434 | } | |
5435 | ||
c19d1205 ZW |
5436 | *str = s + 2; |
5437 | return little_endian; | |
5438 | } | |
a737bd4d | 5439 | |
c19d1205 ZW |
5440 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
5441 | value suitable for poking into the rotate field of an sxt or sxta | |
5442 | instruction, or FAIL on error. */ | |
5443 | ||
5444 | static int | |
5445 | parse_ror (char **str) | |
5446 | { | |
5447 | int rot; | |
5448 | char *s = *str; | |
5449 | ||
5450 | if (strncasecmp (s, "ROR", 3) == 0) | |
5451 | s += 3; | |
5452 | else | |
a737bd4d | 5453 | { |
c19d1205 | 5454 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
5455 | return FAIL; |
5456 | } | |
c19d1205 ZW |
5457 | |
5458 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
5459 | return FAIL; | |
5460 | ||
5461 | switch (rot) | |
a737bd4d | 5462 | { |
c19d1205 ZW |
5463 | case 0: *str = s; return 0x0; |
5464 | case 8: *str = s; return 0x1; | |
5465 | case 16: *str = s; return 0x2; | |
5466 | case 24: *str = s; return 0x3; | |
5467 | ||
5468 | default: | |
5469 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
5470 | return FAIL; |
5471 | } | |
c19d1205 | 5472 | } |
a737bd4d | 5473 | |
c19d1205 ZW |
5474 | /* Parse a conditional code (from conds[] below). The value returned is in the |
5475 | range 0 .. 14, or FAIL. */ | |
5476 | static int | |
5477 | parse_cond (char **str) | |
5478 | { | |
c462b453 | 5479 | char *q; |
c19d1205 | 5480 | const struct asm_cond *c; |
c462b453 PB |
5481 | int n; |
5482 | /* Condition codes are always 2 characters, so matching up to | |
5483 | 3 characters is sufficient. */ | |
5484 | char cond[3]; | |
a737bd4d | 5485 | |
c462b453 PB |
5486 | q = *str; |
5487 | n = 0; | |
5488 | while (ISALPHA (*q) && n < 3) | |
5489 | { | |
e07e6e58 | 5490 | cond[n] = TOLOWER (*q); |
c462b453 PB |
5491 | q++; |
5492 | n++; | |
5493 | } | |
a737bd4d | 5494 | |
21d799b5 | 5495 | c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n); |
c19d1205 | 5496 | if (!c) |
a737bd4d | 5497 | { |
c19d1205 | 5498 | inst.error = _("condition required"); |
a737bd4d NC |
5499 | return FAIL; |
5500 | } | |
5501 | ||
c19d1205 ZW |
5502 | *str = q; |
5503 | return c->value; | |
5504 | } | |
5505 | ||
62b3e311 PB |
5506 | /* Parse an option for a barrier instruction. Returns the encoding for the |
5507 | option, or FAIL. */ | |
5508 | static int | |
5509 | parse_barrier (char **str) | |
5510 | { | |
5511 | char *p, *q; | |
5512 | const struct asm_barrier_opt *o; | |
5513 | ||
5514 | p = q = *str; | |
5515 | while (ISALPHA (*q)) | |
5516 | q++; | |
5517 | ||
21d799b5 NC |
5518 | o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p, |
5519 | q - p); | |
62b3e311 PB |
5520 | if (!o) |
5521 | return FAIL; | |
5522 | ||
5523 | *str = q; | |
5524 | return o->value; | |
5525 | } | |
5526 | ||
92e90b6e PB |
5527 | /* Parse the operands of a table branch instruction. Similar to a memory |
5528 | operand. */ | |
5529 | static int | |
5530 | parse_tb (char **str) | |
5531 | { | |
5532 | char * p = *str; | |
5533 | int reg; | |
5534 | ||
5535 | if (skip_past_char (&p, '[') == FAIL) | |
ab1eb5fe PB |
5536 | { |
5537 | inst.error = _("'[' expected"); | |
5538 | return FAIL; | |
5539 | } | |
92e90b6e | 5540 | |
dcbf9037 | 5541 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5542 | { |
5543 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5544 | return FAIL; | |
5545 | } | |
5546 | inst.operands[0].reg = reg; | |
5547 | ||
5548 | if (skip_past_comma (&p) == FAIL) | |
ab1eb5fe PB |
5549 | { |
5550 | inst.error = _("',' expected"); | |
5551 | return FAIL; | |
5552 | } | |
5f4273c7 | 5553 | |
dcbf9037 | 5554 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5555 | { |
5556 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5557 | return FAIL; | |
5558 | } | |
5559 | inst.operands[0].imm = reg; | |
5560 | ||
5561 | if (skip_past_comma (&p) == SUCCESS) | |
5562 | { | |
5563 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
5564 | return FAIL; | |
5565 | if (inst.reloc.exp.X_add_number != 1) | |
5566 | { | |
5567 | inst.error = _("invalid shift"); | |
5568 | return FAIL; | |
5569 | } | |
5570 | inst.operands[0].shifted = 1; | |
5571 | } | |
5572 | ||
5573 | if (skip_past_char (&p, ']') == FAIL) | |
5574 | { | |
5575 | inst.error = _("']' expected"); | |
5576 | return FAIL; | |
5577 | } | |
5578 | *str = p; | |
5579 | return SUCCESS; | |
5580 | } | |
5581 | ||
5287ad62 JB |
5582 | /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more |
5583 | information on the types the operands can take and how they are encoded. | |
037e8744 JB |
5584 | Up to four operands may be read; this function handles setting the |
5585 | ".present" field for each read operand itself. | |
5287ad62 JB |
5586 | Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, |
5587 | else returns FAIL. */ | |
5588 | ||
5589 | static int | |
5590 | parse_neon_mov (char **str, int *which_operand) | |
5591 | { | |
5592 | int i = *which_operand, val; | |
5593 | enum arm_reg_type rtype; | |
5594 | char *ptr = *str; | |
dcbf9037 | 5595 | struct neon_type_el optype; |
5f4273c7 | 5596 | |
dcbf9037 | 5597 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
5598 | { |
5599 | /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ | |
5600 | inst.operands[i].reg = val; | |
5601 | inst.operands[i].isscalar = 1; | |
dcbf9037 | 5602 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5603 | inst.operands[i++].present = 1; |
5604 | ||
5605 | if (skip_past_comma (&ptr) == FAIL) | |
5606 | goto wanted_comma; | |
5f4273c7 | 5607 | |
dcbf9037 | 5608 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
5287ad62 | 5609 | goto wanted_arm; |
5f4273c7 | 5610 | |
5287ad62 JB |
5611 | inst.operands[i].reg = val; |
5612 | inst.operands[i].isreg = 1; | |
5613 | inst.operands[i].present = 1; | |
5614 | } | |
037e8744 | 5615 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) |
dcbf9037 | 5616 | != FAIL) |
5287ad62 JB |
5617 | { |
5618 | /* Cases 0, 1, 2, 3, 5 (D only). */ | |
5619 | if (skip_past_comma (&ptr) == FAIL) | |
5620 | goto wanted_comma; | |
5f4273c7 | 5621 | |
5287ad62 JB |
5622 | inst.operands[i].reg = val; |
5623 | inst.operands[i].isreg = 1; | |
5624 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5625 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5626 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5627 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5628 | inst.operands[i++].present = 1; |
5629 | ||
dcbf9037 | 5630 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 | 5631 | { |
037e8744 JB |
5632 | /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. |
5633 | Case 13: VMOV <Sd>, <Rm> */ | |
5287ad62 JB |
5634 | inst.operands[i].reg = val; |
5635 | inst.operands[i].isreg = 1; | |
037e8744 | 5636 | inst.operands[i].present = 1; |
5287ad62 JB |
5637 | |
5638 | if (rtype == REG_TYPE_NQ) | |
5639 | { | |
dcbf9037 | 5640 | first_error (_("can't use Neon quad register here")); |
5287ad62 JB |
5641 | return FAIL; |
5642 | } | |
037e8744 JB |
5643 | else if (rtype != REG_TYPE_VFS) |
5644 | { | |
5645 | i++; | |
5646 | if (skip_past_comma (&ptr) == FAIL) | |
5647 | goto wanted_comma; | |
5648 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5649 | goto wanted_arm; | |
5650 | inst.operands[i].reg = val; | |
5651 | inst.operands[i].isreg = 1; | |
5652 | inst.operands[i].present = 1; | |
5653 | } | |
5287ad62 | 5654 | } |
037e8744 JB |
5655 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, |
5656 | &optype)) != FAIL) | |
5287ad62 JB |
5657 | { |
5658 | /* Case 0: VMOV<c><q> <Qd>, <Qm> | |
037e8744 JB |
5659 | Case 1: VMOV<c><q> <Dd>, <Dm> |
5660 | Case 8: VMOV.F32 <Sd>, <Sm> | |
5661 | Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ | |
5287ad62 JB |
5662 | |
5663 | inst.operands[i].reg = val; | |
5664 | inst.operands[i].isreg = 1; | |
5665 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5666 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5667 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5668 | inst.operands[i].vectype = optype; |
5287ad62 | 5669 | inst.operands[i].present = 1; |
5f4273c7 | 5670 | |
037e8744 JB |
5671 | if (skip_past_comma (&ptr) == SUCCESS) |
5672 | { | |
5673 | /* Case 15. */ | |
5674 | i++; | |
5675 | ||
5676 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5677 | goto wanted_arm; | |
5678 | ||
5679 | inst.operands[i].reg = val; | |
5680 | inst.operands[i].isreg = 1; | |
5681 | inst.operands[i++].present = 1; | |
5f4273c7 | 5682 | |
037e8744 JB |
5683 | if (skip_past_comma (&ptr) == FAIL) |
5684 | goto wanted_comma; | |
5f4273c7 | 5685 | |
037e8744 JB |
5686 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
5687 | goto wanted_arm; | |
5f4273c7 | 5688 | |
037e8744 JB |
5689 | inst.operands[i].reg = val; |
5690 | inst.operands[i].isreg = 1; | |
5691 | inst.operands[i++].present = 1; | |
5692 | } | |
5287ad62 | 5693 | } |
4641781c PB |
5694 | else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) |
5695 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> | |
5696 | Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> | |
5697 | Case 10: VMOV.F32 <Sd>, #<imm> | |
5698 | Case 11: VMOV.F64 <Dd>, #<imm> */ | |
5699 | inst.operands[i].immisfloat = 1; | |
5700 | else if (parse_big_immediate (&ptr, i) == SUCCESS) | |
5701 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> | |
5702 | Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ | |
5703 | ; | |
5287ad62 JB |
5704 | else |
5705 | { | |
dcbf9037 | 5706 | first_error (_("expected <Rm> or <Dm> or <Qm> operand")); |
5287ad62 JB |
5707 | return FAIL; |
5708 | } | |
5709 | } | |
dcbf9037 | 5710 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
5711 | { |
5712 | /* Cases 6, 7. */ | |
5713 | inst.operands[i].reg = val; | |
5714 | inst.operands[i].isreg = 1; | |
5715 | inst.operands[i++].present = 1; | |
5f4273c7 | 5716 | |
5287ad62 JB |
5717 | if (skip_past_comma (&ptr) == FAIL) |
5718 | goto wanted_comma; | |
5f4273c7 | 5719 | |
dcbf9037 | 5720 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
5721 | { |
5722 | /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ | |
5723 | inst.operands[i].reg = val; | |
5724 | inst.operands[i].isscalar = 1; | |
5725 | inst.operands[i].present = 1; | |
dcbf9037 | 5726 | inst.operands[i].vectype = optype; |
5287ad62 | 5727 | } |
dcbf9037 | 5728 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
5729 | { |
5730 | /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ | |
5731 | inst.operands[i].reg = val; | |
5732 | inst.operands[i].isreg = 1; | |
5733 | inst.operands[i++].present = 1; | |
5f4273c7 | 5734 | |
5287ad62 JB |
5735 | if (skip_past_comma (&ptr) == FAIL) |
5736 | goto wanted_comma; | |
5f4273c7 | 5737 | |
037e8744 | 5738 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) |
dcbf9037 | 5739 | == FAIL) |
5287ad62 | 5740 | { |
037e8744 | 5741 | first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); |
5287ad62 JB |
5742 | return FAIL; |
5743 | } | |
5744 | ||
5745 | inst.operands[i].reg = val; | |
5746 | inst.operands[i].isreg = 1; | |
037e8744 JB |
5747 | inst.operands[i].isvec = 1; |
5748 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
dcbf9037 | 5749 | inst.operands[i].vectype = optype; |
5287ad62 | 5750 | inst.operands[i].present = 1; |
5f4273c7 | 5751 | |
037e8744 JB |
5752 | if (rtype == REG_TYPE_VFS) |
5753 | { | |
5754 | /* Case 14. */ | |
5755 | i++; | |
5756 | if (skip_past_comma (&ptr) == FAIL) | |
5757 | goto wanted_comma; | |
5758 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, | |
5759 | &optype)) == FAIL) | |
5760 | { | |
5761 | first_error (_(reg_expected_msgs[REG_TYPE_VFS])); | |
5762 | return FAIL; | |
5763 | } | |
5764 | inst.operands[i].reg = val; | |
5765 | inst.operands[i].isreg = 1; | |
5766 | inst.operands[i].isvec = 1; | |
5767 | inst.operands[i].issingle = 1; | |
5768 | inst.operands[i].vectype = optype; | |
5769 | inst.operands[i].present = 1; | |
5770 | } | |
5771 | } | |
5772 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) | |
5773 | != FAIL) | |
5774 | { | |
5775 | /* Case 13. */ | |
5776 | inst.operands[i].reg = val; | |
5777 | inst.operands[i].isreg = 1; | |
5778 | inst.operands[i].isvec = 1; | |
5779 | inst.operands[i].issingle = 1; | |
5780 | inst.operands[i].vectype = optype; | |
5781 | inst.operands[i++].present = 1; | |
5287ad62 JB |
5782 | } |
5783 | } | |
5784 | else | |
5785 | { | |
dcbf9037 | 5786 | first_error (_("parse error")); |
5287ad62 JB |
5787 | return FAIL; |
5788 | } | |
5789 | ||
5790 | /* Successfully parsed the operands. Update args. */ | |
5791 | *which_operand = i; | |
5792 | *str = ptr; | |
5793 | return SUCCESS; | |
5794 | ||
5f4273c7 | 5795 | wanted_comma: |
dcbf9037 | 5796 | first_error (_("expected comma")); |
5287ad62 | 5797 | return FAIL; |
5f4273c7 NC |
5798 | |
5799 | wanted_arm: | |
dcbf9037 | 5800 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
5287ad62 | 5801 | return FAIL; |
5287ad62 JB |
5802 | } |
5803 | ||
5be8be5d DG |
5804 | /* Use this macro when the operand constraints are different |
5805 | for ARM and THUMB (e.g. ldrd). */ | |
5806 | #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \ | |
5807 | ((arm_operand) | ((thumb_operand) << 16)) | |
5808 | ||
c19d1205 ZW |
5809 | /* Matcher codes for parse_operands. */ |
5810 | enum operand_parse_code | |
5811 | { | |
5812 | OP_stop, /* end of line */ | |
5813 | ||
5814 | OP_RR, /* ARM register */ | |
5815 | OP_RRnpc, /* ARM register, not r15 */ | |
5be8be5d | 5816 | OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */ |
c19d1205 | 5817 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ |
55881a11 MGD |
5818 | OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback, |
5819 | optional trailing ! */ | |
c19d1205 ZW |
5820 | OP_RRw, /* ARM register, not r15, optional trailing ! */ |
5821 | OP_RCP, /* Coprocessor number */ | |
5822 | OP_RCN, /* Coprocessor register */ | |
5823 | OP_RF, /* FPA register */ | |
5824 | OP_RVS, /* VFP single precision register */ | |
5287ad62 JB |
5825 | OP_RVD, /* VFP double precision register (0..15) */ |
5826 | OP_RND, /* Neon double precision register (0..31) */ | |
5827 | OP_RNQ, /* Neon quad precision register */ | |
037e8744 | 5828 | OP_RVSD, /* VFP single or double precision register */ |
5287ad62 | 5829 | OP_RNDQ, /* Neon double or quad precision register */ |
037e8744 | 5830 | OP_RNSDQ, /* Neon single, double or quad precision register */ |
5287ad62 | 5831 | OP_RNSC, /* Neon scalar D[X] */ |
c19d1205 ZW |
5832 | OP_RVC, /* VFP control register */ |
5833 | OP_RMF, /* Maverick F register */ | |
5834 | OP_RMD, /* Maverick D register */ | |
5835 | OP_RMFX, /* Maverick FX register */ | |
5836 | OP_RMDX, /* Maverick DX register */ | |
5837 | OP_RMAX, /* Maverick AX register */ | |
5838 | OP_RMDS, /* Maverick DSPSC register */ | |
5839 | OP_RIWR, /* iWMMXt wR register */ | |
5840 | OP_RIWC, /* iWMMXt wC register */ | |
5841 | OP_RIWG, /* iWMMXt wCG register */ | |
5842 | OP_RXA, /* XScale accumulator register */ | |
5843 | ||
5844 | OP_REGLST, /* ARM register list */ | |
5845 | OP_VRSLST, /* VFP single-precision register list */ | |
5846 | OP_VRDLST, /* VFP double-precision register list */ | |
037e8744 | 5847 | OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ |
5287ad62 JB |
5848 | OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ |
5849 | OP_NSTRLST, /* Neon element/structure list */ | |
5850 | ||
5287ad62 | 5851 | OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ |
037e8744 | 5852 | OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ |
5287ad62 | 5853 | OP_RR_RNSC, /* ARM reg or Neon scalar. */ |
037e8744 | 5854 | OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ |
5287ad62 JB |
5855 | OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ |
5856 | OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ | |
5857 | OP_VMOV, /* Neon VMOV operands. */ | |
4316f0d2 | 5858 | OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */ |
5287ad62 | 5859 | OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ |
2d447fca | 5860 | OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ |
5287ad62 JB |
5861 | |
5862 | OP_I0, /* immediate zero */ | |
c19d1205 ZW |
5863 | OP_I7, /* immediate value 0 .. 7 */ |
5864 | OP_I15, /* 0 .. 15 */ | |
5865 | OP_I16, /* 1 .. 16 */ | |
5287ad62 | 5866 | OP_I16z, /* 0 .. 16 */ |
c19d1205 ZW |
5867 | OP_I31, /* 0 .. 31 */ |
5868 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
5869 | OP_I32, /* 1 .. 32 */ | |
5287ad62 JB |
5870 | OP_I32z, /* 0 .. 32 */ |
5871 | OP_I63, /* 0 .. 63 */ | |
c19d1205 | 5872 | OP_I63s, /* -64 .. 63 */ |
5287ad62 JB |
5873 | OP_I64, /* 1 .. 64 */ |
5874 | OP_I64z, /* 0 .. 64 */ | |
c19d1205 | 5875 | OP_I255, /* 0 .. 255 */ |
c19d1205 ZW |
5876 | |
5877 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
5878 | OP_I7b, /* 0 .. 7 */ | |
5879 | OP_I15b, /* 0 .. 15 */ | |
5880 | OP_I31b, /* 0 .. 31 */ | |
5881 | ||
5882 | OP_SH, /* shifter operand */ | |
4962c51a | 5883 | OP_SHG, /* shifter operand with possible group relocation */ |
c19d1205 | 5884 | OP_ADDR, /* Memory address expression (any mode) */ |
4962c51a MS |
5885 | OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ |
5886 | OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ | |
5887 | OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ | |
c19d1205 ZW |
5888 | OP_EXP, /* arbitrary expression */ |
5889 | OP_EXPi, /* same, with optional immediate prefix */ | |
5890 | OP_EXPr, /* same, with optional relocation suffix */ | |
b6895b4f | 5891 | OP_HALF, /* 0 .. 65535 or low/high reloc. */ |
c19d1205 ZW |
5892 | |
5893 | OP_CPSF, /* CPS flags */ | |
5894 | OP_ENDI, /* Endianness specifier */ | |
5895 | OP_PSR, /* CPSR/SPSR mask for msr */ | |
5896 | OP_COND, /* conditional code */ | |
92e90b6e | 5897 | OP_TB, /* Table branch. */ |
c19d1205 | 5898 | |
037e8744 JB |
5899 | OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */ |
5900 | OP_APSR_RR, /* ARM register or "APSR_nzcv". */ | |
5901 | ||
c19d1205 ZW |
5902 | OP_RRnpc_I0, /* ARM register or literal 0 */ |
5903 | OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ | |
5904 | OP_RR_EXi, /* ARM register or expression with imm prefix */ | |
5905 | OP_RF_IF, /* FPA register or immediate */ | |
5906 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
41adaa5c | 5907 | OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ |
c19d1205 ZW |
5908 | |
5909 | /* Optional operands. */ | |
5910 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
5911 | OP_oI31b, /* 0 .. 31 */ | |
5287ad62 | 5912 | OP_oI32b, /* 1 .. 32 */ |
c19d1205 ZW |
5913 | OP_oIffffb, /* 0 .. 65535 */ |
5914 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
5915 | ||
5916 | OP_oRR, /* ARM register */ | |
5917 | OP_oRRnpc, /* ARM register, not the PC */ | |
5be8be5d | 5918 | OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */ |
b6702015 | 5919 | OP_oRRw, /* ARM register, not r15, optional trailing ! */ |
5287ad62 JB |
5920 | OP_oRND, /* Optional Neon double precision register */ |
5921 | OP_oRNQ, /* Optional Neon quad precision register */ | |
5922 | OP_oRNDQ, /* Optional Neon double or quad precision register */ | |
037e8744 | 5923 | OP_oRNSDQ, /* Optional single, double or quad precision vector register */ |
c19d1205 ZW |
5924 | OP_oSHll, /* LSL immediate */ |
5925 | OP_oSHar, /* ASR immediate */ | |
5926 | OP_oSHllar, /* LSL or ASR immediate */ | |
5927 | OP_oROR, /* ROR 0/8/16/24 */ | |
52e7f43d | 5928 | OP_oBARRIER_I15, /* Option argument for a barrier instruction. */ |
c19d1205 | 5929 | |
5be8be5d DG |
5930 | /* Some pre-defined mixed (ARM/THUMB) operands. */ |
5931 | OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp), | |
5932 | OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp), | |
5933 | OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp), | |
5934 | ||
c19d1205 ZW |
5935 | OP_FIRST_OPTIONAL = OP_oI7b |
5936 | }; | |
a737bd4d | 5937 | |
c19d1205 ZW |
5938 | /* Generic instruction operand parser. This does no encoding and no |
5939 | semantic validation; it merely squirrels values away in the inst | |
5940 | structure. Returns SUCCESS or FAIL depending on whether the | |
5941 | specified grammar matched. */ | |
5942 | static int | |
5be8be5d | 5943 | parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) |
c19d1205 | 5944 | { |
5be8be5d | 5945 | unsigned const int *upat = pattern; |
c19d1205 ZW |
5946 | char *backtrack_pos = 0; |
5947 | const char *backtrack_error = 0; | |
5948 | int i, val, backtrack_index = 0; | |
5287ad62 | 5949 | enum arm_reg_type rtype; |
4962c51a | 5950 | parse_operand_result result; |
5be8be5d | 5951 | unsigned int op_parse_code; |
c19d1205 | 5952 | |
e07e6e58 NC |
5953 | #define po_char_or_fail(chr) \ |
5954 | do \ | |
5955 | { \ | |
5956 | if (skip_past_char (&str, chr) == FAIL) \ | |
5957 | goto bad_args; \ | |
5958 | } \ | |
5959 | while (0) | |
c19d1205 | 5960 | |
e07e6e58 NC |
5961 | #define po_reg_or_fail(regtype) \ |
5962 | do \ | |
dcbf9037 | 5963 | { \ |
e07e6e58 NC |
5964 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ |
5965 | & inst.operands[i].vectype); \ | |
5966 | if (val == FAIL) \ | |
5967 | { \ | |
5968 | first_error (_(reg_expected_msgs[regtype])); \ | |
5969 | goto failure; \ | |
5970 | } \ | |
5971 | inst.operands[i].reg = val; \ | |
5972 | inst.operands[i].isreg = 1; \ | |
5973 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
5974 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
5975 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
5976 | || rtype == REG_TYPE_VFD \ | |
5977 | || rtype == REG_TYPE_NQ); \ | |
dcbf9037 | 5978 | } \ |
e07e6e58 NC |
5979 | while (0) |
5980 | ||
5981 | #define po_reg_or_goto(regtype, label) \ | |
5982 | do \ | |
5983 | { \ | |
5984 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ | |
5985 | & inst.operands[i].vectype); \ | |
5986 | if (val == FAIL) \ | |
5987 | goto label; \ | |
dcbf9037 | 5988 | \ |
e07e6e58 NC |
5989 | inst.operands[i].reg = val; \ |
5990 | inst.operands[i].isreg = 1; \ | |
5991 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
5992 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
5993 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
5994 | || rtype == REG_TYPE_VFD \ | |
5995 | || rtype == REG_TYPE_NQ); \ | |
5996 | } \ | |
5997 | while (0) | |
5998 | ||
5999 | #define po_imm_or_fail(min, max, popt) \ | |
6000 | do \ | |
6001 | { \ | |
6002 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
6003 | goto failure; \ | |
6004 | inst.operands[i].imm = val; \ | |
6005 | } \ | |
6006 | while (0) | |
6007 | ||
6008 | #define po_scalar_or_goto(elsz, label) \ | |
6009 | do \ | |
6010 | { \ | |
6011 | val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \ | |
6012 | if (val == FAIL) \ | |
6013 | goto label; \ | |
6014 | inst.operands[i].reg = val; \ | |
6015 | inst.operands[i].isscalar = 1; \ | |
6016 | } \ | |
6017 | while (0) | |
6018 | ||
6019 | #define po_misc_or_fail(expr) \ | |
6020 | do \ | |
6021 | { \ | |
6022 | if (expr) \ | |
6023 | goto failure; \ | |
6024 | } \ | |
6025 | while (0) | |
6026 | ||
6027 | #define po_misc_or_fail_no_backtrack(expr) \ | |
6028 | do \ | |
6029 | { \ | |
6030 | result = expr; \ | |
6031 | if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \ | |
6032 | backtrack_pos = 0; \ | |
6033 | if (result != PARSE_OPERAND_SUCCESS) \ | |
6034 | goto failure; \ | |
6035 | } \ | |
6036 | while (0) | |
4962c51a | 6037 | |
52e7f43d RE |
6038 | #define po_barrier_or_imm(str) \ |
6039 | do \ | |
6040 | { \ | |
6041 | val = parse_barrier (&str); \ | |
6042 | if (val == FAIL) \ | |
6043 | { \ | |
6044 | if (ISALPHA (*str)) \ | |
6045 | goto failure; \ | |
6046 | else \ | |
6047 | goto immediate; \ | |
6048 | } \ | |
6049 | else \ | |
6050 | { \ | |
6051 | if ((inst.instruction & 0xf0) == 0x60 \ | |
6052 | && val != 0xf) \ | |
6053 | { \ | |
6054 | /* ISB can only take SY as an option. */ \ | |
6055 | inst.error = _("invalid barrier type"); \ | |
6056 | goto failure; \ | |
6057 | } \ | |
6058 | } \ | |
6059 | } \ | |
6060 | while (0) | |
6061 | ||
c19d1205 ZW |
6062 | skip_whitespace (str); |
6063 | ||
6064 | for (i = 0; upat[i] != OP_stop; i++) | |
6065 | { | |
5be8be5d DG |
6066 | op_parse_code = upat[i]; |
6067 | if (op_parse_code >= 1<<16) | |
6068 | op_parse_code = thumb ? (op_parse_code >> 16) | |
6069 | : (op_parse_code & ((1<<16)-1)); | |
6070 | ||
6071 | if (op_parse_code >= OP_FIRST_OPTIONAL) | |
c19d1205 ZW |
6072 | { |
6073 | /* Remember where we are in case we need to backtrack. */ | |
9c2799c2 | 6074 | gas_assert (!backtrack_pos); |
c19d1205 ZW |
6075 | backtrack_pos = str; |
6076 | backtrack_error = inst.error; | |
6077 | backtrack_index = i; | |
6078 | } | |
6079 | ||
b6702015 | 6080 | if (i > 0 && (i > 1 || inst.operands[0].present)) |
c19d1205 ZW |
6081 | po_char_or_fail (','); |
6082 | ||
5be8be5d | 6083 | switch (op_parse_code) |
c19d1205 ZW |
6084 | { |
6085 | /* Registers */ | |
6086 | case OP_oRRnpc: | |
5be8be5d | 6087 | case OP_oRRnpcsp: |
c19d1205 | 6088 | case OP_RRnpc: |
5be8be5d | 6089 | case OP_RRnpcsp: |
c19d1205 ZW |
6090 | case OP_oRR: |
6091 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; | |
6092 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
6093 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
6094 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
6095 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
6096 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
5287ad62 JB |
6097 | case OP_oRND: |
6098 | case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; | |
cd2cf30b PB |
6099 | case OP_RVC: |
6100 | po_reg_or_goto (REG_TYPE_VFC, coproc_reg); | |
6101 | break; | |
6102 | /* Also accept generic coprocessor regs for unknown registers. */ | |
6103 | coproc_reg: | |
6104 | po_reg_or_fail (REG_TYPE_CN); | |
6105 | break; | |
c19d1205 ZW |
6106 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; |
6107 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
6108 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
6109 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
6110 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
6111 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
6112 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
6113 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
6114 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
6115 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
5287ad62 JB |
6116 | case OP_oRNQ: |
6117 | case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; | |
6118 | case OP_oRNDQ: | |
6119 | case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; | |
037e8744 JB |
6120 | case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; |
6121 | case OP_oRNSDQ: | |
6122 | case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; | |
5287ad62 JB |
6123 | |
6124 | /* Neon scalar. Using an element size of 8 means that some invalid | |
6125 | scalars are accepted here, so deal with those in later code. */ | |
6126 | case OP_RNSC: po_scalar_or_goto (8, failure); break; | |
6127 | ||
5287ad62 JB |
6128 | case OP_RNDQ_I0: |
6129 | { | |
6130 | po_reg_or_goto (REG_TYPE_NDQ, try_imm0); | |
6131 | break; | |
6132 | try_imm0: | |
6133 | po_imm_or_fail (0, 0, TRUE); | |
6134 | } | |
6135 | break; | |
6136 | ||
037e8744 JB |
6137 | case OP_RVSD_I0: |
6138 | po_reg_or_goto (REG_TYPE_VFSD, try_imm0); | |
6139 | break; | |
6140 | ||
5287ad62 JB |
6141 | case OP_RR_RNSC: |
6142 | { | |
6143 | po_scalar_or_goto (8, try_rr); | |
6144 | break; | |
6145 | try_rr: | |
6146 | po_reg_or_fail (REG_TYPE_RN); | |
6147 | } | |
6148 | break; | |
6149 | ||
037e8744 JB |
6150 | case OP_RNSDQ_RNSC: |
6151 | { | |
6152 | po_scalar_or_goto (8, try_nsdq); | |
6153 | break; | |
6154 | try_nsdq: | |
6155 | po_reg_or_fail (REG_TYPE_NSDQ); | |
6156 | } | |
6157 | break; | |
6158 | ||
5287ad62 JB |
6159 | case OP_RNDQ_RNSC: |
6160 | { | |
6161 | po_scalar_or_goto (8, try_ndq); | |
6162 | break; | |
6163 | try_ndq: | |
6164 | po_reg_or_fail (REG_TYPE_NDQ); | |
6165 | } | |
6166 | break; | |
6167 | ||
6168 | case OP_RND_RNSC: | |
6169 | { | |
6170 | po_scalar_or_goto (8, try_vfd); | |
6171 | break; | |
6172 | try_vfd: | |
6173 | po_reg_or_fail (REG_TYPE_VFD); | |
6174 | } | |
6175 | break; | |
6176 | ||
6177 | case OP_VMOV: | |
6178 | /* WARNING: parse_neon_mov can move the operand counter, i. If we're | |
6179 | not careful then bad things might happen. */ | |
6180 | po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); | |
6181 | break; | |
6182 | ||
4316f0d2 | 6183 | case OP_RNDQ_Ibig: |
5287ad62 | 6184 | { |
4316f0d2 | 6185 | po_reg_or_goto (REG_TYPE_NDQ, try_immbig); |
5287ad62 | 6186 | break; |
4316f0d2 | 6187 | try_immbig: |
5287ad62 JB |
6188 | /* There's a possibility of getting a 64-bit immediate here, so |
6189 | we need special handling. */ | |
6190 | if (parse_big_immediate (&str, i) == FAIL) | |
6191 | { | |
6192 | inst.error = _("immediate value is out of range"); | |
6193 | goto failure; | |
6194 | } | |
6195 | } | |
6196 | break; | |
6197 | ||
6198 | case OP_RNDQ_I63b: | |
6199 | { | |
6200 | po_reg_or_goto (REG_TYPE_NDQ, try_shimm); | |
6201 | break; | |
6202 | try_shimm: | |
6203 | po_imm_or_fail (0, 63, TRUE); | |
6204 | } | |
6205 | break; | |
c19d1205 ZW |
6206 | |
6207 | case OP_RRnpcb: | |
6208 | po_char_or_fail ('['); | |
6209 | po_reg_or_fail (REG_TYPE_RN); | |
6210 | po_char_or_fail (']'); | |
6211 | break; | |
a737bd4d | 6212 | |
55881a11 | 6213 | case OP_RRnpctw: |
c19d1205 | 6214 | case OP_RRw: |
b6702015 | 6215 | case OP_oRRw: |
c19d1205 ZW |
6216 | po_reg_or_fail (REG_TYPE_RN); |
6217 | if (skip_past_char (&str, '!') == SUCCESS) | |
6218 | inst.operands[i].writeback = 1; | |
6219 | break; | |
6220 | ||
6221 | /* Immediates */ | |
6222 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
6223 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
6224 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
5287ad62 | 6225 | case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; |
c19d1205 ZW |
6226 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; |
6227 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
5287ad62 | 6228 | case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; |
c19d1205 | 6229 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; |
5287ad62 JB |
6230 | case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; |
6231 | case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; | |
6232 | case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; | |
c19d1205 | 6233 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; |
c19d1205 ZW |
6234 | |
6235 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
6236 | case OP_oI7b: | |
6237 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
6238 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
6239 | case OP_oI31b: | |
6240 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
5287ad62 | 6241 | case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; |
c19d1205 ZW |
6242 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; |
6243 | ||
6244 | /* Immediate variants */ | |
6245 | case OP_oI255c: | |
6246 | po_char_or_fail ('{'); | |
6247 | po_imm_or_fail (0, 255, TRUE); | |
6248 | po_char_or_fail ('}'); | |
6249 | break; | |
6250 | ||
6251 | case OP_I31w: | |
6252 | /* The expression parser chokes on a trailing !, so we have | |
6253 | to find it first and zap it. */ | |
6254 | { | |
6255 | char *s = str; | |
6256 | while (*s && *s != ',') | |
6257 | s++; | |
6258 | if (s[-1] == '!') | |
6259 | { | |
6260 | s[-1] = '\0'; | |
6261 | inst.operands[i].writeback = 1; | |
6262 | } | |
6263 | po_imm_or_fail (0, 31, TRUE); | |
6264 | if (str == s - 1) | |
6265 | str = s; | |
6266 | } | |
6267 | break; | |
6268 | ||
6269 | /* Expressions */ | |
6270 | case OP_EXPi: EXPi: | |
6271 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6272 | GE_OPT_PREFIX)); | |
6273 | break; | |
6274 | ||
6275 | case OP_EXP: | |
6276 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6277 | GE_NO_PREFIX)); | |
6278 | break; | |
6279 | ||
6280 | case OP_EXPr: EXPr: | |
6281 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6282 | GE_NO_PREFIX)); | |
6283 | if (inst.reloc.exp.X_op == O_symbol) | |
a737bd4d | 6284 | { |
c19d1205 ZW |
6285 | val = parse_reloc (&str); |
6286 | if (val == -1) | |
6287 | { | |
6288 | inst.error = _("unrecognized relocation suffix"); | |
6289 | goto failure; | |
6290 | } | |
6291 | else if (val != BFD_RELOC_UNUSED) | |
6292 | { | |
6293 | inst.operands[i].imm = val; | |
6294 | inst.operands[i].hasreloc = 1; | |
6295 | } | |
a737bd4d | 6296 | } |
c19d1205 | 6297 | break; |
a737bd4d | 6298 | |
b6895b4f PB |
6299 | /* Operand for MOVW or MOVT. */ |
6300 | case OP_HALF: | |
6301 | po_misc_or_fail (parse_half (&str)); | |
6302 | break; | |
6303 | ||
e07e6e58 | 6304 | /* Register or expression. */ |
c19d1205 ZW |
6305 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; |
6306 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 6307 | |
e07e6e58 | 6308 | /* Register or immediate. */ |
c19d1205 ZW |
6309 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; |
6310 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 6311 | |
c19d1205 ZW |
6312 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
6313 | IF: | |
6314 | if (!is_immediate_prefix (*str)) | |
6315 | goto bad_args; | |
6316 | str++; | |
6317 | val = parse_fpa_immediate (&str); | |
6318 | if (val == FAIL) | |
6319 | goto failure; | |
6320 | /* FPA immediates are encoded as registers 8-15. | |
6321 | parse_fpa_immediate has already applied the offset. */ | |
6322 | inst.operands[i].reg = val; | |
6323 | inst.operands[i].isreg = 1; | |
6324 | break; | |
09d92015 | 6325 | |
2d447fca JM |
6326 | case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; |
6327 | I32z: po_imm_or_fail (0, 32, FALSE); break; | |
6328 | ||
e07e6e58 | 6329 | /* Two kinds of register. */ |
c19d1205 ZW |
6330 | case OP_RIWR_RIWC: |
6331 | { | |
6332 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
97f87066 JM |
6333 | if (!rege |
6334 | || (rege->type != REG_TYPE_MMXWR | |
6335 | && rege->type != REG_TYPE_MMXWC | |
6336 | && rege->type != REG_TYPE_MMXWCG)) | |
c19d1205 ZW |
6337 | { |
6338 | inst.error = _("iWMMXt data or control register expected"); | |
6339 | goto failure; | |
6340 | } | |
6341 | inst.operands[i].reg = rege->number; | |
6342 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
6343 | } | |
6344 | break; | |
09d92015 | 6345 | |
41adaa5c JM |
6346 | case OP_RIWC_RIWG: |
6347 | { | |
6348 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
6349 | if (!rege | |
6350 | || (rege->type != REG_TYPE_MMXWC | |
6351 | && rege->type != REG_TYPE_MMXWCG)) | |
6352 | { | |
6353 | inst.error = _("iWMMXt control register expected"); | |
6354 | goto failure; | |
6355 | } | |
6356 | inst.operands[i].reg = rege->number; | |
6357 | inst.operands[i].isreg = 1; | |
6358 | } | |
6359 | break; | |
6360 | ||
c19d1205 ZW |
6361 | /* Misc */ |
6362 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
6363 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
6364 | case OP_oROR: val = parse_ror (&str); break; | |
6365 | case OP_PSR: val = parse_psr (&str); break; | |
6366 | case OP_COND: val = parse_cond (&str); break; | |
52e7f43d RE |
6367 | case OP_oBARRIER_I15: |
6368 | po_barrier_or_imm (str); break; | |
6369 | immediate: | |
6370 | if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL) | |
6371 | goto failure; | |
6372 | break; | |
c19d1205 | 6373 | |
037e8744 JB |
6374 | case OP_RVC_PSR: |
6375 | po_reg_or_goto (REG_TYPE_VFC, try_psr); | |
6376 | inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */ | |
6377 | break; | |
6378 | try_psr: | |
6379 | val = parse_psr (&str); | |
6380 | break; | |
6381 | ||
6382 | case OP_APSR_RR: | |
6383 | po_reg_or_goto (REG_TYPE_RN, try_apsr); | |
6384 | break; | |
6385 | try_apsr: | |
6386 | /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS | |
6387 | instruction). */ | |
6388 | if (strncasecmp (str, "APSR_", 5) == 0) | |
6389 | { | |
6390 | unsigned found = 0; | |
6391 | str += 5; | |
6392 | while (found < 15) | |
6393 | switch (*str++) | |
6394 | { | |
6395 | case 'c': found = (found & 1) ? 16 : found | 1; break; | |
6396 | case 'n': found = (found & 2) ? 16 : found | 2; break; | |
6397 | case 'z': found = (found & 4) ? 16 : found | 4; break; | |
6398 | case 'v': found = (found & 8) ? 16 : found | 8; break; | |
6399 | default: found = 16; | |
6400 | } | |
6401 | if (found != 15) | |
6402 | goto failure; | |
6403 | inst.operands[i].isvec = 1; | |
f7c21dc7 NC |
6404 | /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */ |
6405 | inst.operands[i].reg = REG_PC; | |
037e8744 JB |
6406 | } |
6407 | else | |
6408 | goto failure; | |
6409 | break; | |
6410 | ||
92e90b6e PB |
6411 | case OP_TB: |
6412 | po_misc_or_fail (parse_tb (&str)); | |
6413 | break; | |
6414 | ||
e07e6e58 | 6415 | /* Register lists. */ |
c19d1205 ZW |
6416 | case OP_REGLST: |
6417 | val = parse_reg_list (&str); | |
6418 | if (*str == '^') | |
6419 | { | |
6420 | inst.operands[1].writeback = 1; | |
6421 | str++; | |
6422 | } | |
6423 | break; | |
09d92015 | 6424 | |
c19d1205 | 6425 | case OP_VRSLST: |
5287ad62 | 6426 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); |
c19d1205 | 6427 | break; |
09d92015 | 6428 | |
c19d1205 | 6429 | case OP_VRDLST: |
5287ad62 | 6430 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); |
c19d1205 | 6431 | break; |
a737bd4d | 6432 | |
037e8744 JB |
6433 | case OP_VRSDLST: |
6434 | /* Allow Q registers too. */ | |
6435 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6436 | REGLIST_NEON_D); | |
6437 | if (val == FAIL) | |
6438 | { | |
6439 | inst.error = NULL; | |
6440 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6441 | REGLIST_VFP_S); | |
6442 | inst.operands[i].issingle = 1; | |
6443 | } | |
6444 | break; | |
6445 | ||
5287ad62 JB |
6446 | case OP_NRDLST: |
6447 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6448 | REGLIST_NEON_D); | |
6449 | break; | |
6450 | ||
6451 | case OP_NSTRLST: | |
dcbf9037 JB |
6452 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, |
6453 | &inst.operands[i].vectype); | |
5287ad62 JB |
6454 | break; |
6455 | ||
c19d1205 ZW |
6456 | /* Addressing modes */ |
6457 | case OP_ADDR: | |
6458 | po_misc_or_fail (parse_address (&str, i)); | |
6459 | break; | |
09d92015 | 6460 | |
4962c51a MS |
6461 | case OP_ADDRGLDR: |
6462 | po_misc_or_fail_no_backtrack ( | |
6463 | parse_address_group_reloc (&str, i, GROUP_LDR)); | |
6464 | break; | |
6465 | ||
6466 | case OP_ADDRGLDRS: | |
6467 | po_misc_or_fail_no_backtrack ( | |
6468 | parse_address_group_reloc (&str, i, GROUP_LDRS)); | |
6469 | break; | |
6470 | ||
6471 | case OP_ADDRGLDC: | |
6472 | po_misc_or_fail_no_backtrack ( | |
6473 | parse_address_group_reloc (&str, i, GROUP_LDC)); | |
6474 | break; | |
6475 | ||
c19d1205 ZW |
6476 | case OP_SH: |
6477 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
6478 | break; | |
09d92015 | 6479 | |
4962c51a MS |
6480 | case OP_SHG: |
6481 | po_misc_or_fail_no_backtrack ( | |
6482 | parse_shifter_operand_group_reloc (&str, i)); | |
6483 | break; | |
6484 | ||
c19d1205 ZW |
6485 | case OP_oSHll: |
6486 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
6487 | break; | |
09d92015 | 6488 | |
c19d1205 ZW |
6489 | case OP_oSHar: |
6490 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
6491 | break; | |
09d92015 | 6492 | |
c19d1205 ZW |
6493 | case OP_oSHllar: |
6494 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
6495 | break; | |
09d92015 | 6496 | |
c19d1205 | 6497 | default: |
5be8be5d | 6498 | as_fatal (_("unhandled operand code %d"), op_parse_code); |
c19d1205 | 6499 | } |
09d92015 | 6500 | |
c19d1205 ZW |
6501 | /* Various value-based sanity checks and shared operations. We |
6502 | do not signal immediate failures for the register constraints; | |
6503 | this allows a syntax error to take precedence. */ | |
5be8be5d | 6504 | switch (op_parse_code) |
c19d1205 ZW |
6505 | { |
6506 | case OP_oRRnpc: | |
6507 | case OP_RRnpc: | |
6508 | case OP_RRnpcb: | |
6509 | case OP_RRw: | |
b6702015 | 6510 | case OP_oRRw: |
c19d1205 ZW |
6511 | case OP_RRnpc_I0: |
6512 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
6513 | inst.error = BAD_PC; | |
6514 | break; | |
09d92015 | 6515 | |
5be8be5d DG |
6516 | case OP_oRRnpcsp: |
6517 | case OP_RRnpcsp: | |
6518 | if (inst.operands[i].isreg) | |
6519 | { | |
6520 | if (inst.operands[i].reg == REG_PC) | |
6521 | inst.error = BAD_PC; | |
6522 | else if (inst.operands[i].reg == REG_SP) | |
6523 | inst.error = BAD_SP; | |
6524 | } | |
6525 | break; | |
6526 | ||
55881a11 MGD |
6527 | case OP_RRnpctw: |
6528 | if (inst.operands[i].isreg | |
6529 | && inst.operands[i].reg == REG_PC | |
6530 | && (inst.operands[i].writeback || thumb)) | |
6531 | inst.error = BAD_PC; | |
6532 | break; | |
6533 | ||
c19d1205 ZW |
6534 | case OP_CPSF: |
6535 | case OP_ENDI: | |
6536 | case OP_oROR: | |
6537 | case OP_PSR: | |
037e8744 | 6538 | case OP_RVC_PSR: |
c19d1205 | 6539 | case OP_COND: |
52e7f43d | 6540 | case OP_oBARRIER_I15: |
c19d1205 ZW |
6541 | case OP_REGLST: |
6542 | case OP_VRSLST: | |
6543 | case OP_VRDLST: | |
037e8744 | 6544 | case OP_VRSDLST: |
5287ad62 JB |
6545 | case OP_NRDLST: |
6546 | case OP_NSTRLST: | |
c19d1205 ZW |
6547 | if (val == FAIL) |
6548 | goto failure; | |
6549 | inst.operands[i].imm = val; | |
6550 | break; | |
a737bd4d | 6551 | |
c19d1205 ZW |
6552 | default: |
6553 | break; | |
6554 | } | |
09d92015 | 6555 | |
c19d1205 ZW |
6556 | /* If we get here, this operand was successfully parsed. */ |
6557 | inst.operands[i].present = 1; | |
6558 | continue; | |
09d92015 | 6559 | |
c19d1205 | 6560 | bad_args: |
09d92015 | 6561 | inst.error = BAD_ARGS; |
c19d1205 ZW |
6562 | |
6563 | failure: | |
6564 | if (!backtrack_pos) | |
d252fdde PB |
6565 | { |
6566 | /* The parse routine should already have set inst.error, but set a | |
5f4273c7 | 6567 | default here just in case. */ |
d252fdde PB |
6568 | if (!inst.error) |
6569 | inst.error = _("syntax error"); | |
6570 | return FAIL; | |
6571 | } | |
c19d1205 ZW |
6572 | |
6573 | /* Do not backtrack over a trailing optional argument that | |
6574 | absorbed some text. We will only fail again, with the | |
6575 | 'garbage following instruction' error message, which is | |
6576 | probably less helpful than the current one. */ | |
6577 | if (backtrack_index == i && backtrack_pos != str | |
6578 | && upat[i+1] == OP_stop) | |
d252fdde PB |
6579 | { |
6580 | if (!inst.error) | |
6581 | inst.error = _("syntax error"); | |
6582 | return FAIL; | |
6583 | } | |
c19d1205 ZW |
6584 | |
6585 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
6586 | str = backtrack_pos; | |
6587 | inst.error = backtrack_error; | |
6588 | inst.operands[backtrack_index].present = 0; | |
6589 | i = backtrack_index; | |
6590 | backtrack_pos = 0; | |
09d92015 | 6591 | } |
09d92015 | 6592 | |
c19d1205 ZW |
6593 | /* Check that we have parsed all the arguments. */ |
6594 | if (*str != '\0' && !inst.error) | |
6595 | inst.error = _("garbage following instruction"); | |
09d92015 | 6596 | |
c19d1205 | 6597 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
6598 | } |
6599 | ||
c19d1205 ZW |
6600 | #undef po_char_or_fail |
6601 | #undef po_reg_or_fail | |
6602 | #undef po_reg_or_goto | |
6603 | #undef po_imm_or_fail | |
5287ad62 | 6604 | #undef po_scalar_or_fail |
52e7f43d | 6605 | #undef po_barrier_or_imm |
e07e6e58 | 6606 | |
c19d1205 | 6607 | /* Shorthand macro for instruction encoding functions issuing errors. */ |
e07e6e58 NC |
6608 | #define constraint(expr, err) \ |
6609 | do \ | |
c19d1205 | 6610 | { \ |
e07e6e58 NC |
6611 | if (expr) \ |
6612 | { \ | |
6613 | inst.error = err; \ | |
6614 | return; \ | |
6615 | } \ | |
c19d1205 | 6616 | } \ |
e07e6e58 | 6617 | while (0) |
c19d1205 | 6618 | |
fdfde340 JM |
6619 | /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 |
6620 | instructions are unpredictable if these registers are used. This | |
6621 | is the BadReg predicate in ARM's Thumb-2 documentation. */ | |
6622 | #define reject_bad_reg(reg) \ | |
6623 | do \ | |
6624 | if (reg == REG_SP || reg == REG_PC) \ | |
6625 | { \ | |
6626 | inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \ | |
6627 | return; \ | |
6628 | } \ | |
6629 | while (0) | |
6630 | ||
94206790 MM |
6631 | /* If REG is R13 (the stack pointer), warn that its use is |
6632 | deprecated. */ | |
6633 | #define warn_deprecated_sp(reg) \ | |
6634 | do \ | |
6635 | if (warn_on_deprecated && reg == REG_SP) \ | |
6636 | as_warn (_("use of r13 is deprecated")); \ | |
6637 | while (0) | |
6638 | ||
c19d1205 ZW |
6639 | /* Functions for operand encoding. ARM, then Thumb. */ |
6640 | ||
6641 | #define rotate_left(v, n) (v << n | v >> (32 - n)) | |
6642 | ||
6643 | /* If VAL can be encoded in the immediate field of an ARM instruction, | |
6644 | return the encoded form. Otherwise, return FAIL. */ | |
6645 | ||
6646 | static unsigned int | |
6647 | encode_arm_immediate (unsigned int val) | |
09d92015 | 6648 | { |
c19d1205 ZW |
6649 | unsigned int a, i; |
6650 | ||
6651 | for (i = 0; i < 32; i += 2) | |
6652 | if ((a = rotate_left (val, i)) <= 0xff) | |
6653 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
6654 | ||
6655 | return FAIL; | |
09d92015 MM |
6656 | } |
6657 | ||
c19d1205 ZW |
6658 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
6659 | return the encoded form. Otherwise, return FAIL. */ | |
6660 | static unsigned int | |
6661 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 6662 | { |
c19d1205 | 6663 | unsigned int a, i; |
09d92015 | 6664 | |
9c3c69f2 | 6665 | if (val <= 0xff) |
c19d1205 | 6666 | return val; |
a737bd4d | 6667 | |
9c3c69f2 | 6668 | for (i = 1; i <= 24; i++) |
09d92015 | 6669 | { |
9c3c69f2 PB |
6670 | a = val >> i; |
6671 | if ((val & ~(0xff << i)) == 0) | |
6672 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 6673 | } |
a737bd4d | 6674 | |
c19d1205 ZW |
6675 | a = val & 0xff; |
6676 | if (val == ((a << 16) | a)) | |
6677 | return 0x100 | a; | |
6678 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
6679 | return 0x300 | a; | |
09d92015 | 6680 | |
c19d1205 ZW |
6681 | a = val & 0xff00; |
6682 | if (val == ((a << 16) | a)) | |
6683 | return 0x200 | (a >> 8); | |
a737bd4d | 6684 | |
c19d1205 | 6685 | return FAIL; |
09d92015 | 6686 | } |
5287ad62 | 6687 | /* Encode a VFP SP or DP register number into inst.instruction. */ |
09d92015 MM |
6688 | |
6689 | static void | |
5287ad62 JB |
6690 | encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) |
6691 | { | |
6692 | if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) | |
6693 | && reg > 15) | |
6694 | { | |
b1cc4aeb | 6695 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) |
5287ad62 JB |
6696 | { |
6697 | if (thumb_mode) | |
6698 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
b1cc4aeb | 6699 | fpu_vfp_ext_d32); |
5287ad62 JB |
6700 | else |
6701 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
b1cc4aeb | 6702 | fpu_vfp_ext_d32); |
5287ad62 JB |
6703 | } |
6704 | else | |
6705 | { | |
dcbf9037 | 6706 | first_error (_("D register out of range for selected VFP version")); |
5287ad62 JB |
6707 | return; |
6708 | } | |
6709 | } | |
6710 | ||
c19d1205 | 6711 | switch (pos) |
09d92015 | 6712 | { |
c19d1205 ZW |
6713 | case VFP_REG_Sd: |
6714 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
6715 | break; | |
6716 | ||
6717 | case VFP_REG_Sn: | |
6718 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
6719 | break; | |
6720 | ||
6721 | case VFP_REG_Sm: | |
6722 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
6723 | break; | |
6724 | ||
5287ad62 JB |
6725 | case VFP_REG_Dd: |
6726 | inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); | |
6727 | break; | |
5f4273c7 | 6728 | |
5287ad62 JB |
6729 | case VFP_REG_Dn: |
6730 | inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); | |
6731 | break; | |
5f4273c7 | 6732 | |
5287ad62 JB |
6733 | case VFP_REG_Dm: |
6734 | inst.instruction |= (reg & 15) | ((reg >> 4) << 5); | |
6735 | break; | |
6736 | ||
c19d1205 ZW |
6737 | default: |
6738 | abort (); | |
09d92015 | 6739 | } |
09d92015 MM |
6740 | } |
6741 | ||
c19d1205 | 6742 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 6743 | if any, is handled by md_apply_fix. */ |
09d92015 | 6744 | static void |
c19d1205 | 6745 | encode_arm_shift (int i) |
09d92015 | 6746 | { |
c19d1205 ZW |
6747 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
6748 | inst.instruction |= SHIFT_ROR << 5; | |
6749 | else | |
09d92015 | 6750 | { |
c19d1205 ZW |
6751 | inst.instruction |= inst.operands[i].shift_kind << 5; |
6752 | if (inst.operands[i].immisreg) | |
6753 | { | |
6754 | inst.instruction |= SHIFT_BY_REG; | |
6755 | inst.instruction |= inst.operands[i].imm << 8; | |
6756 | } | |
6757 | else | |
6758 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
09d92015 | 6759 | } |
c19d1205 | 6760 | } |
09d92015 | 6761 | |
c19d1205 ZW |
6762 | static void |
6763 | encode_arm_shifter_operand (int i) | |
6764 | { | |
6765 | if (inst.operands[i].isreg) | |
09d92015 | 6766 | { |
c19d1205 ZW |
6767 | inst.instruction |= inst.operands[i].reg; |
6768 | encode_arm_shift (i); | |
09d92015 | 6769 | } |
c19d1205 ZW |
6770 | else |
6771 | inst.instruction |= INST_IMMEDIATE; | |
09d92015 MM |
6772 | } |
6773 | ||
c19d1205 | 6774 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 6775 | static void |
c19d1205 | 6776 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 6777 | { |
9c2799c2 | 6778 | gas_assert (inst.operands[i].isreg); |
c19d1205 | 6779 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 6780 | |
c19d1205 | 6781 | if (inst.operands[i].preind) |
09d92015 | 6782 | { |
c19d1205 ZW |
6783 | if (is_t) |
6784 | { | |
6785 | inst.error = _("instruction does not accept preindexed addressing"); | |
6786 | return; | |
6787 | } | |
6788 | inst.instruction |= PRE_INDEX; | |
6789 | if (inst.operands[i].writeback) | |
6790 | inst.instruction |= WRITE_BACK; | |
09d92015 | 6791 | |
c19d1205 ZW |
6792 | } |
6793 | else if (inst.operands[i].postind) | |
6794 | { | |
9c2799c2 | 6795 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
6796 | if (is_t) |
6797 | inst.instruction |= WRITE_BACK; | |
6798 | } | |
6799 | else /* unindexed - only for coprocessor */ | |
09d92015 | 6800 | { |
c19d1205 | 6801 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
6802 | return; |
6803 | } | |
6804 | ||
c19d1205 ZW |
6805 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
6806 | && (((inst.instruction & 0x000f0000) >> 16) | |
6807 | == ((inst.instruction & 0x0000f000) >> 12))) | |
6808 | as_warn ((inst.instruction & LOAD_BIT) | |
6809 | ? _("destination register same as write-back base") | |
6810 | : _("source register same as write-back base")); | |
09d92015 MM |
6811 | } |
6812 | ||
c19d1205 ZW |
6813 | /* inst.operands[i] was set up by parse_address. Encode it into an |
6814 | ARM-format mode 2 load or store instruction. If is_t is true, | |
6815 | reject forms that cannot be used with a T instruction (i.e. not | |
6816 | post-indexed). */ | |
a737bd4d | 6817 | static void |
c19d1205 | 6818 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 6819 | { |
5be8be5d DG |
6820 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
6821 | ||
c19d1205 | 6822 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 6823 | |
c19d1205 | 6824 | if (inst.operands[i].immisreg) |
09d92015 | 6825 | { |
5be8be5d DG |
6826 | constraint ((inst.operands[i].imm == REG_PC |
6827 | || (is_pc && inst.operands[i].writeback)), | |
6828 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
6829 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
6830 | inst.instruction |= inst.operands[i].imm; | |
6831 | if (!inst.operands[i].negative) | |
6832 | inst.instruction |= INDEX_UP; | |
6833 | if (inst.operands[i].shifted) | |
6834 | { | |
6835 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
6836 | inst.instruction |= SHIFT_ROR << 5; | |
6837 | else | |
6838 | { | |
6839 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
6840 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
6841 | } | |
6842 | } | |
09d92015 | 6843 | } |
c19d1205 | 6844 | else /* immediate offset in inst.reloc */ |
09d92015 | 6845 | { |
5be8be5d DG |
6846 | if (is_pc && !inst.reloc.pc_rel) |
6847 | { | |
6848 | const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0); | |
23a10334 JZ |
6849 | |
6850 | /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt | |
6851 | cannot use PC in addressing. | |
6852 | PC cannot be used in writeback addressing, either. */ | |
6853 | constraint ((is_t || inst.operands[i].writeback), | |
5be8be5d | 6854 | BAD_PC_ADDRESSING); |
23a10334 | 6855 | |
dc5ec521 | 6856 | /* Use of PC in str is deprecated for ARMv7. */ |
23a10334 JZ |
6857 | if (warn_on_deprecated |
6858 | && !is_load | |
6859 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) | |
6860 | as_warn (_("use of PC in this instruction is deprecated")); | |
5be8be5d DG |
6861 | } |
6862 | ||
c19d1205 ZW |
6863 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
6864 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
09d92015 | 6865 | } |
09d92015 MM |
6866 | } |
6867 | ||
c19d1205 ZW |
6868 | /* inst.operands[i] was set up by parse_address. Encode it into an |
6869 | ARM-format mode 3 load or store instruction. Reject forms that | |
6870 | cannot be used with such instructions. If is_t is true, reject | |
6871 | forms that cannot be used with a T instruction (i.e. not | |
6872 | post-indexed). */ | |
6873 | static void | |
6874 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 6875 | { |
c19d1205 | 6876 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 6877 | { |
c19d1205 ZW |
6878 | inst.error = _("instruction does not accept scaled register index"); |
6879 | return; | |
09d92015 | 6880 | } |
a737bd4d | 6881 | |
c19d1205 | 6882 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 6883 | |
c19d1205 ZW |
6884 | if (inst.operands[i].immisreg) |
6885 | { | |
5be8be5d DG |
6886 | constraint ((inst.operands[i].imm == REG_PC |
6887 | || inst.operands[i].reg == REG_PC), | |
6888 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
6889 | inst.instruction |= inst.operands[i].imm; |
6890 | if (!inst.operands[i].negative) | |
6891 | inst.instruction |= INDEX_UP; | |
6892 | } | |
6893 | else /* immediate offset in inst.reloc */ | |
6894 | { | |
5be8be5d DG |
6895 | constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel |
6896 | && inst.operands[i].writeback), | |
6897 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
6898 | inst.instruction |= HWOFFSET_IMM; |
6899 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
6900 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
c19d1205 | 6901 | } |
a737bd4d NC |
6902 | } |
6903 | ||
c19d1205 ZW |
6904 | /* inst.operands[i] was set up by parse_address. Encode it into an |
6905 | ARM-format instruction. Reject all forms which cannot be encoded | |
6906 | into a coprocessor load/store instruction. If wb_ok is false, | |
6907 | reject use of writeback; if unind_ok is false, reject use of | |
6908 | unindexed addressing. If reloc_override is not 0, use it instead | |
4962c51a MS |
6909 | of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one |
6910 | (in which case it is preserved). */ | |
09d92015 | 6911 | |
c19d1205 ZW |
6912 | static int |
6913 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
09d92015 | 6914 | { |
c19d1205 | 6915 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 6916 | |
9c2799c2 | 6917 | gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); |
09d92015 | 6918 | |
c19d1205 | 6919 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ |
09d92015 | 6920 | { |
9c2799c2 | 6921 | gas_assert (!inst.operands[i].writeback); |
c19d1205 ZW |
6922 | if (!unind_ok) |
6923 | { | |
6924 | inst.error = _("instruction does not support unindexed addressing"); | |
6925 | return FAIL; | |
6926 | } | |
6927 | inst.instruction |= inst.operands[i].imm; | |
6928 | inst.instruction |= INDEX_UP; | |
6929 | return SUCCESS; | |
09d92015 | 6930 | } |
a737bd4d | 6931 | |
c19d1205 ZW |
6932 | if (inst.operands[i].preind) |
6933 | inst.instruction |= PRE_INDEX; | |
a737bd4d | 6934 | |
c19d1205 | 6935 | if (inst.operands[i].writeback) |
09d92015 | 6936 | { |
c19d1205 ZW |
6937 | if (inst.operands[i].reg == REG_PC) |
6938 | { | |
6939 | inst.error = _("pc may not be used with write-back"); | |
6940 | return FAIL; | |
6941 | } | |
6942 | if (!wb_ok) | |
6943 | { | |
6944 | inst.error = _("instruction does not support writeback"); | |
6945 | return FAIL; | |
6946 | } | |
6947 | inst.instruction |= WRITE_BACK; | |
09d92015 | 6948 | } |
a737bd4d | 6949 | |
c19d1205 | 6950 | if (reloc_override) |
21d799b5 | 6951 | inst.reloc.type = (bfd_reloc_code_real_type) reloc_override; |
4962c51a MS |
6952 | else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC |
6953 | || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) | |
6954 | && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) | |
6955 | { | |
6956 | if (thumb_mode) | |
6957 | inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; | |
6958 | else | |
6959 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; | |
6960 | } | |
6961 | ||
c19d1205 ZW |
6962 | return SUCCESS; |
6963 | } | |
a737bd4d | 6964 | |
c19d1205 ZW |
6965 | /* inst.reloc.exp describes an "=expr" load pseudo-operation. |
6966 | Determine whether it can be performed with a move instruction; if | |
6967 | it can, convert inst.instruction to that move instruction and | |
c921be7d NC |
6968 | return TRUE; if it can't, convert inst.instruction to a literal-pool |
6969 | load and return FALSE. If this is not a valid thing to do in the | |
6970 | current context, set inst.error and return TRUE. | |
a737bd4d | 6971 | |
c19d1205 ZW |
6972 | inst.operands[i] describes the destination register. */ |
6973 | ||
c921be7d | 6974 | static bfd_boolean |
c19d1205 ZW |
6975 | move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) |
6976 | { | |
53365c0d PB |
6977 | unsigned long tbit; |
6978 | ||
6979 | if (thumb_p) | |
6980 | tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; | |
6981 | else | |
6982 | tbit = LOAD_BIT; | |
6983 | ||
6984 | if ((inst.instruction & tbit) == 0) | |
09d92015 | 6985 | { |
c19d1205 | 6986 | inst.error = _("invalid pseudo operation"); |
c921be7d | 6987 | return TRUE; |
09d92015 | 6988 | } |
c19d1205 | 6989 | if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) |
09d92015 MM |
6990 | { |
6991 | inst.error = _("constant expression expected"); | |
c921be7d | 6992 | return TRUE; |
09d92015 | 6993 | } |
c19d1205 | 6994 | if (inst.reloc.exp.X_op == O_constant) |
09d92015 | 6995 | { |
c19d1205 ZW |
6996 | if (thumb_p) |
6997 | { | |
53365c0d | 6998 | if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) |
c19d1205 ZW |
6999 | { |
7000 | /* This can be done with a mov(1) instruction. */ | |
7001 | inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); | |
7002 | inst.instruction |= inst.reloc.exp.X_add_number; | |
c921be7d | 7003 | return TRUE; |
c19d1205 ZW |
7004 | } |
7005 | } | |
7006 | else | |
7007 | { | |
7008 | int value = encode_arm_immediate (inst.reloc.exp.X_add_number); | |
7009 | if (value != FAIL) | |
7010 | { | |
7011 | /* This can be done with a mov instruction. */ | |
7012 | inst.instruction &= LITERAL_MASK; | |
7013 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
7014 | inst.instruction |= value & 0xfff; | |
c921be7d | 7015 | return TRUE; |
c19d1205 | 7016 | } |
09d92015 | 7017 | |
c19d1205 ZW |
7018 | value = encode_arm_immediate (~inst.reloc.exp.X_add_number); |
7019 | if (value != FAIL) | |
7020 | { | |
7021 | /* This can be done with a mvn instruction. */ | |
7022 | inst.instruction &= LITERAL_MASK; | |
7023 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
7024 | inst.instruction |= value & 0xfff; | |
c921be7d | 7025 | return TRUE; |
c19d1205 ZW |
7026 | } |
7027 | } | |
09d92015 MM |
7028 | } |
7029 | ||
c19d1205 ZW |
7030 | if (add_to_lit_pool () == FAIL) |
7031 | { | |
7032 | inst.error = _("literal pool insertion failed"); | |
c921be7d | 7033 | return TRUE; |
c19d1205 ZW |
7034 | } |
7035 | inst.operands[1].reg = REG_PC; | |
7036 | inst.operands[1].isreg = 1; | |
7037 | inst.operands[1].preind = 1; | |
7038 | inst.reloc.pc_rel = 1; | |
7039 | inst.reloc.type = (thumb_p | |
7040 | ? BFD_RELOC_ARM_THUMB_OFFSET | |
7041 | : (mode_3 | |
7042 | ? BFD_RELOC_ARM_HWLITERAL | |
7043 | : BFD_RELOC_ARM_LITERAL)); | |
c921be7d | 7044 | return FALSE; |
09d92015 MM |
7045 | } |
7046 | ||
5f4273c7 | 7047 | /* Functions for instruction encoding, sorted by sub-architecture. |
c19d1205 ZW |
7048 | First some generics; their names are taken from the conventional |
7049 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 7050 | |
a737bd4d | 7051 | static void |
c19d1205 | 7052 | do_noargs (void) |
09d92015 | 7053 | { |
c19d1205 | 7054 | } |
a737bd4d | 7055 | |
c19d1205 ZW |
7056 | static void |
7057 | do_rd (void) | |
7058 | { | |
7059 | inst.instruction |= inst.operands[0].reg << 12; | |
7060 | } | |
a737bd4d | 7061 | |
c19d1205 ZW |
7062 | static void |
7063 | do_rd_rm (void) | |
7064 | { | |
7065 | inst.instruction |= inst.operands[0].reg << 12; | |
7066 | inst.instruction |= inst.operands[1].reg; | |
7067 | } | |
09d92015 | 7068 | |
c19d1205 ZW |
7069 | static void |
7070 | do_rd_rn (void) | |
7071 | { | |
7072 | inst.instruction |= inst.operands[0].reg << 12; | |
7073 | inst.instruction |= inst.operands[1].reg << 16; | |
7074 | } | |
a737bd4d | 7075 | |
c19d1205 ZW |
7076 | static void |
7077 | do_rn_rd (void) | |
7078 | { | |
7079 | inst.instruction |= inst.operands[0].reg << 16; | |
7080 | inst.instruction |= inst.operands[1].reg << 12; | |
7081 | } | |
09d92015 | 7082 | |
c19d1205 ZW |
7083 | static void |
7084 | do_rd_rm_rn (void) | |
7085 | { | |
9a64e435 | 7086 | unsigned Rn = inst.operands[2].reg; |
708587a4 | 7087 | /* Enforce restrictions on SWP instruction. */ |
9a64e435 | 7088 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) |
56adecf4 DG |
7089 | { |
7090 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
7091 | _("Rn must not overlap other operands")); | |
7092 | ||
7093 | /* SWP{b} is deprecated for ARMv6* and ARMv7. */ | |
7094 | if (warn_on_deprecated | |
7095 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
7096 | as_warn (_("swp{b} use is deprecated for this architecture")); | |
7097 | ||
7098 | } | |
c19d1205 ZW |
7099 | inst.instruction |= inst.operands[0].reg << 12; |
7100 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 7101 | inst.instruction |= Rn << 16; |
c19d1205 | 7102 | } |
09d92015 | 7103 | |
c19d1205 ZW |
7104 | static void |
7105 | do_rd_rn_rm (void) | |
7106 | { | |
7107 | inst.instruction |= inst.operands[0].reg << 12; | |
7108 | inst.instruction |= inst.operands[1].reg << 16; | |
7109 | inst.instruction |= inst.operands[2].reg; | |
7110 | } | |
a737bd4d | 7111 | |
c19d1205 ZW |
7112 | static void |
7113 | do_rm_rd_rn (void) | |
7114 | { | |
5be8be5d DG |
7115 | constraint ((inst.operands[2].reg == REG_PC), BAD_PC); |
7116 | constraint (((inst.reloc.exp.X_op != O_constant | |
7117 | && inst.reloc.exp.X_op != O_illegal) | |
7118 | || inst.reloc.exp.X_add_number != 0), | |
7119 | BAD_ADDR_MODE); | |
c19d1205 ZW |
7120 | inst.instruction |= inst.operands[0].reg; |
7121 | inst.instruction |= inst.operands[1].reg << 12; | |
7122 | inst.instruction |= inst.operands[2].reg << 16; | |
7123 | } | |
09d92015 | 7124 | |
c19d1205 ZW |
7125 | static void |
7126 | do_imm0 (void) | |
7127 | { | |
7128 | inst.instruction |= inst.operands[0].imm; | |
7129 | } | |
09d92015 | 7130 | |
c19d1205 ZW |
7131 | static void |
7132 | do_rd_cpaddr (void) | |
7133 | { | |
7134 | inst.instruction |= inst.operands[0].reg << 12; | |
7135 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 7136 | } |
a737bd4d | 7137 | |
c19d1205 ZW |
7138 | /* ARM instructions, in alphabetical order by function name (except |
7139 | that wrapper functions appear immediately after the function they | |
7140 | wrap). */ | |
09d92015 | 7141 | |
c19d1205 ZW |
7142 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
7143 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
7144 | |
7145 | static void | |
c19d1205 | 7146 | do_adr (void) |
09d92015 | 7147 | { |
c19d1205 | 7148 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 7149 | |
c19d1205 ZW |
7150 | /* Frag hacking will turn this into a sub instruction if the offset turns |
7151 | out to be negative. */ | |
7152 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
c19d1205 | 7153 | inst.reloc.pc_rel = 1; |
2fc8bdac | 7154 | inst.reloc.exp.X_add_number -= 8; |
c19d1205 | 7155 | } |
b99bd4ef | 7156 | |
c19d1205 ZW |
7157 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
7158 | into a relative address of the form: | |
7159 | add rd, pc, #low(label-.-8)" | |
7160 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 7161 | |
c19d1205 ZW |
7162 | static void |
7163 | do_adrl (void) | |
7164 | { | |
7165 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 7166 | |
c19d1205 ZW |
7167 | /* Frag hacking will turn this into a sub instruction if the offset turns |
7168 | out to be negative. */ | |
7169 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
c19d1205 ZW |
7170 | inst.reloc.pc_rel = 1; |
7171 | inst.size = INSN_SIZE * 2; | |
2fc8bdac | 7172 | inst.reloc.exp.X_add_number -= 8; |
b99bd4ef NC |
7173 | } |
7174 | ||
b99bd4ef | 7175 | static void |
c19d1205 | 7176 | do_arit (void) |
b99bd4ef | 7177 | { |
c19d1205 ZW |
7178 | if (!inst.operands[1].present) |
7179 | inst.operands[1].reg = inst.operands[0].reg; | |
7180 | inst.instruction |= inst.operands[0].reg << 12; | |
7181 | inst.instruction |= inst.operands[1].reg << 16; | |
7182 | encode_arm_shifter_operand (2); | |
7183 | } | |
b99bd4ef | 7184 | |
62b3e311 PB |
7185 | static void |
7186 | do_barrier (void) | |
7187 | { | |
7188 | if (inst.operands[0].present) | |
7189 | { | |
7190 | constraint ((inst.instruction & 0xf0) != 0x40 | |
52e7f43d RE |
7191 | && inst.operands[0].imm > 0xf |
7192 | && inst.operands[0].imm < 0x0, | |
bd3ba5d1 | 7193 | _("bad barrier type")); |
62b3e311 PB |
7194 | inst.instruction |= inst.operands[0].imm; |
7195 | } | |
7196 | else | |
7197 | inst.instruction |= 0xf; | |
7198 | } | |
7199 | ||
c19d1205 ZW |
7200 | static void |
7201 | do_bfc (void) | |
7202 | { | |
7203 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
7204 | constraint (msb > 32, _("bit-field extends past end of register")); | |
7205 | /* The instruction encoding stores the LSB and MSB, | |
7206 | not the LSB and width. */ | |
7207 | inst.instruction |= inst.operands[0].reg << 12; | |
7208 | inst.instruction |= inst.operands[1].imm << 7; | |
7209 | inst.instruction |= (msb - 1) << 16; | |
7210 | } | |
b99bd4ef | 7211 | |
c19d1205 ZW |
7212 | static void |
7213 | do_bfi (void) | |
7214 | { | |
7215 | unsigned int msb; | |
b99bd4ef | 7216 | |
c19d1205 ZW |
7217 | /* #0 in second position is alternative syntax for bfc, which is |
7218 | the same instruction but with REG_PC in the Rm field. */ | |
7219 | if (!inst.operands[1].isreg) | |
7220 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 7221 | |
c19d1205 ZW |
7222 | msb = inst.operands[2].imm + inst.operands[3].imm; |
7223 | constraint (msb > 32, _("bit-field extends past end of register")); | |
7224 | /* The instruction encoding stores the LSB and MSB, | |
7225 | not the LSB and width. */ | |
7226 | inst.instruction |= inst.operands[0].reg << 12; | |
7227 | inst.instruction |= inst.operands[1].reg; | |
7228 | inst.instruction |= inst.operands[2].imm << 7; | |
7229 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
7230 | } |
7231 | ||
b99bd4ef | 7232 | static void |
c19d1205 | 7233 | do_bfx (void) |
b99bd4ef | 7234 | { |
c19d1205 ZW |
7235 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
7236 | _("bit-field extends past end of register")); | |
7237 | inst.instruction |= inst.operands[0].reg << 12; | |
7238 | inst.instruction |= inst.operands[1].reg; | |
7239 | inst.instruction |= inst.operands[2].imm << 7; | |
7240 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
7241 | } | |
09d92015 | 7242 | |
c19d1205 ZW |
7243 | /* ARM V5 breakpoint instruction (argument parse) |
7244 | BKPT <16 bit unsigned immediate> | |
7245 | Instruction is not conditional. | |
7246 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
7247 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 7248 | |
c19d1205 ZW |
7249 | static void |
7250 | do_bkpt (void) | |
7251 | { | |
7252 | /* Top 12 of 16 bits to bits 19:8. */ | |
7253 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 7254 | |
c19d1205 ZW |
7255 | /* Bottom 4 of 16 bits to bits 3:0. */ |
7256 | inst.instruction |= inst.operands[0].imm & 0xf; | |
7257 | } | |
09d92015 | 7258 | |
c19d1205 ZW |
7259 | static void |
7260 | encode_branch (int default_reloc) | |
7261 | { | |
7262 | if (inst.operands[0].hasreloc) | |
7263 | { | |
7264 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32, | |
7265 | _("the only suffix valid here is '(plt)'")); | |
267bf995 | 7266 | inst.reloc.type = BFD_RELOC_ARM_PLT32; |
c19d1205 | 7267 | } |
b99bd4ef | 7268 | else |
c19d1205 | 7269 | { |
21d799b5 | 7270 | inst.reloc.type = (bfd_reloc_code_real_type) default_reloc; |
c19d1205 | 7271 | } |
2fc8bdac | 7272 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
7273 | } |
7274 | ||
b99bd4ef | 7275 | static void |
c19d1205 | 7276 | do_branch (void) |
b99bd4ef | 7277 | { |
39b41c9c PB |
7278 | #ifdef OBJ_ELF |
7279 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
7280 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
7281 | else | |
7282 | #endif | |
7283 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
7284 | } | |
7285 | ||
7286 | static void | |
7287 | do_bl (void) | |
7288 | { | |
7289 | #ifdef OBJ_ELF | |
7290 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
7291 | { | |
7292 | if (inst.cond == COND_ALWAYS) | |
7293 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
7294 | else | |
7295 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
7296 | } | |
7297 | else | |
7298 | #endif | |
7299 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
c19d1205 | 7300 | } |
b99bd4ef | 7301 | |
c19d1205 ZW |
7302 | /* ARM V5 branch-link-exchange instruction (argument parse) |
7303 | BLX <target_addr> ie BLX(1) | |
7304 | BLX{<condition>} <Rm> ie BLX(2) | |
7305 | Unfortunately, there are two different opcodes for this mnemonic. | |
7306 | So, the insns[].value is not used, and the code here zaps values | |
7307 | into inst.instruction. | |
7308 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 7309 | |
c19d1205 ZW |
7310 | static void |
7311 | do_blx (void) | |
7312 | { | |
7313 | if (inst.operands[0].isreg) | |
b99bd4ef | 7314 | { |
c19d1205 ZW |
7315 | /* Arg is a register; the opcode provided by insns[] is correct. |
7316 | It is not illegal to do "blx pc", just useless. */ | |
7317 | if (inst.operands[0].reg == REG_PC) | |
7318 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 7319 | |
c19d1205 ZW |
7320 | inst.instruction |= inst.operands[0].reg; |
7321 | } | |
7322 | else | |
b99bd4ef | 7323 | { |
c19d1205 | 7324 | /* Arg is an address; this instruction cannot be executed |
267bf995 RR |
7325 | conditionally, and the opcode must be adjusted. |
7326 | We retain the BFD_RELOC_ARM_PCREL_BLX till the very end | |
7327 | where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */ | |
c19d1205 | 7328 | constraint (inst.cond != COND_ALWAYS, BAD_COND); |
2fc8bdac | 7329 | inst.instruction = 0xfa000000; |
267bf995 | 7330 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); |
b99bd4ef | 7331 | } |
c19d1205 ZW |
7332 | } |
7333 | ||
7334 | static void | |
7335 | do_bx (void) | |
7336 | { | |
845b51d6 PB |
7337 | bfd_boolean want_reloc; |
7338 | ||
c19d1205 ZW |
7339 | if (inst.operands[0].reg == REG_PC) |
7340 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 7341 | |
c19d1205 | 7342 | inst.instruction |= inst.operands[0].reg; |
845b51d6 PB |
7343 | /* Output R_ARM_V4BX relocations if is an EABI object that looks like |
7344 | it is for ARMv4t or earlier. */ | |
7345 | want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5); | |
7346 | if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5)) | |
7347 | want_reloc = TRUE; | |
7348 | ||
5ad34203 | 7349 | #ifdef OBJ_ELF |
845b51d6 | 7350 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
5ad34203 | 7351 | #endif |
584206db | 7352 | want_reloc = FALSE; |
845b51d6 PB |
7353 | |
7354 | if (want_reloc) | |
7355 | inst.reloc.type = BFD_RELOC_ARM_V4BX; | |
09d92015 MM |
7356 | } |
7357 | ||
c19d1205 ZW |
7358 | |
7359 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
7360 | |
7361 | static void | |
c19d1205 | 7362 | do_bxj (void) |
a737bd4d | 7363 | { |
c19d1205 ZW |
7364 | if (inst.operands[0].reg == REG_PC) |
7365 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
7366 | ||
7367 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
7368 | } |
7369 | ||
c19d1205 ZW |
7370 | /* Co-processor data operation: |
7371 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
7372 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
7373 | static void | |
7374 | do_cdp (void) | |
7375 | { | |
7376 | inst.instruction |= inst.operands[0].reg << 8; | |
7377 | inst.instruction |= inst.operands[1].imm << 20; | |
7378 | inst.instruction |= inst.operands[2].reg << 12; | |
7379 | inst.instruction |= inst.operands[3].reg << 16; | |
7380 | inst.instruction |= inst.operands[4].reg; | |
7381 | inst.instruction |= inst.operands[5].imm << 5; | |
7382 | } | |
a737bd4d NC |
7383 | |
7384 | static void | |
c19d1205 | 7385 | do_cmp (void) |
a737bd4d | 7386 | { |
c19d1205 ZW |
7387 | inst.instruction |= inst.operands[0].reg << 16; |
7388 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
7389 | } |
7390 | ||
c19d1205 ZW |
7391 | /* Transfer between coprocessor and ARM registers. |
7392 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
7393 | MRC2 | |
7394 | MCR{cond} | |
7395 | MCR2 | |
7396 | ||
7397 | No special properties. */ | |
09d92015 MM |
7398 | |
7399 | static void | |
c19d1205 | 7400 | do_co_reg (void) |
09d92015 | 7401 | { |
fdfde340 JM |
7402 | unsigned Rd; |
7403 | ||
7404 | Rd = inst.operands[2].reg; | |
7405 | if (thumb_mode) | |
7406 | { | |
7407 | if (inst.instruction == 0xee000010 | |
7408 | || inst.instruction == 0xfe000010) | |
7409 | /* MCR, MCR2 */ | |
7410 | reject_bad_reg (Rd); | |
7411 | else | |
7412 | /* MRC, MRC2 */ | |
7413 | constraint (Rd == REG_SP, BAD_SP); | |
7414 | } | |
7415 | else | |
7416 | { | |
7417 | /* MCR */ | |
7418 | if (inst.instruction == 0xe000010) | |
7419 | constraint (Rd == REG_PC, BAD_PC); | |
7420 | } | |
7421 | ||
7422 | ||
c19d1205 ZW |
7423 | inst.instruction |= inst.operands[0].reg << 8; |
7424 | inst.instruction |= inst.operands[1].imm << 21; | |
fdfde340 | 7425 | inst.instruction |= Rd << 12; |
c19d1205 ZW |
7426 | inst.instruction |= inst.operands[3].reg << 16; |
7427 | inst.instruction |= inst.operands[4].reg; | |
7428 | inst.instruction |= inst.operands[5].imm << 5; | |
7429 | } | |
09d92015 | 7430 | |
c19d1205 ZW |
7431 | /* Transfer between coprocessor register and pair of ARM registers. |
7432 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
7433 | MCRR2 | |
7434 | MRRC{cond} | |
7435 | MRRC2 | |
b99bd4ef | 7436 | |
c19d1205 | 7437 | Two XScale instructions are special cases of these: |
09d92015 | 7438 | |
c19d1205 ZW |
7439 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
7440 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 7441 | |
5f4273c7 | 7442 | Result unpredictable if Rd or Rn is R15. */ |
a737bd4d | 7443 | |
c19d1205 ZW |
7444 | static void |
7445 | do_co_reg2c (void) | |
7446 | { | |
fdfde340 JM |
7447 | unsigned Rd, Rn; |
7448 | ||
7449 | Rd = inst.operands[2].reg; | |
7450 | Rn = inst.operands[3].reg; | |
7451 | ||
7452 | if (thumb_mode) | |
7453 | { | |
7454 | reject_bad_reg (Rd); | |
7455 | reject_bad_reg (Rn); | |
7456 | } | |
7457 | else | |
7458 | { | |
7459 | constraint (Rd == REG_PC, BAD_PC); | |
7460 | constraint (Rn == REG_PC, BAD_PC); | |
7461 | } | |
7462 | ||
c19d1205 ZW |
7463 | inst.instruction |= inst.operands[0].reg << 8; |
7464 | inst.instruction |= inst.operands[1].imm << 4; | |
fdfde340 JM |
7465 | inst.instruction |= Rd << 12; |
7466 | inst.instruction |= Rn << 16; | |
c19d1205 | 7467 | inst.instruction |= inst.operands[4].reg; |
b99bd4ef NC |
7468 | } |
7469 | ||
c19d1205 ZW |
7470 | static void |
7471 | do_cpsi (void) | |
7472 | { | |
7473 | inst.instruction |= inst.operands[0].imm << 6; | |
a028a6f5 PB |
7474 | if (inst.operands[1].present) |
7475 | { | |
7476 | inst.instruction |= CPSI_MMOD; | |
7477 | inst.instruction |= inst.operands[1].imm; | |
7478 | } | |
c19d1205 | 7479 | } |
b99bd4ef | 7480 | |
62b3e311 PB |
7481 | static void |
7482 | do_dbg (void) | |
7483 | { | |
7484 | inst.instruction |= inst.operands[0].imm; | |
7485 | } | |
7486 | ||
b99bd4ef | 7487 | static void |
c19d1205 | 7488 | do_it (void) |
b99bd4ef | 7489 | { |
c19d1205 | 7490 | /* There is no IT instruction in ARM mode. We |
e07e6e58 NC |
7491 | process it to do the validation as if in |
7492 | thumb mode, just in case the code gets | |
7493 | assembled for thumb using the unified syntax. */ | |
7494 | ||
c19d1205 | 7495 | inst.size = 0; |
e07e6e58 NC |
7496 | if (unified_syntax) |
7497 | { | |
7498 | set_it_insn_type (IT_INSN); | |
7499 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
7500 | now_it.cc = inst.operands[0].imm; | |
7501 | } | |
09d92015 | 7502 | } |
b99bd4ef | 7503 | |
09d92015 | 7504 | static void |
c19d1205 | 7505 | do_ldmstm (void) |
ea6ef066 | 7506 | { |
c19d1205 ZW |
7507 | int base_reg = inst.operands[0].reg; |
7508 | int range = inst.operands[1].imm; | |
ea6ef066 | 7509 | |
c19d1205 ZW |
7510 | inst.instruction |= base_reg << 16; |
7511 | inst.instruction |= range; | |
ea6ef066 | 7512 | |
c19d1205 ZW |
7513 | if (inst.operands[1].writeback) |
7514 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 7515 | |
c19d1205 | 7516 | if (inst.operands[0].writeback) |
ea6ef066 | 7517 | { |
c19d1205 ZW |
7518 | inst.instruction |= WRITE_BACK; |
7519 | /* Check for unpredictable uses of writeback. */ | |
7520 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 7521 | { |
c19d1205 ZW |
7522 | /* Not allowed in LDM type 2. */ |
7523 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
7524 | && ((range & (1 << REG_PC)) == 0)) | |
7525 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
7526 | /* Only allowed if base reg not in list for other types. */ | |
7527 | else if (range & (1 << base_reg)) | |
7528 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
7529 | } | |
7530 | else /* STM. */ | |
7531 | { | |
7532 | /* Not allowed for type 2. */ | |
7533 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
7534 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
7535 | /* Only allowed if base reg not in list, or first in list. */ | |
7536 | else if ((range & (1 << base_reg)) | |
7537 | && (range & ((1 << base_reg) - 1))) | |
7538 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 7539 | } |
ea6ef066 | 7540 | } |
a737bd4d NC |
7541 | } |
7542 | ||
c19d1205 ZW |
7543 | /* ARMv5TE load-consecutive (argument parse) |
7544 | Mode is like LDRH. | |
7545 | ||
7546 | LDRccD R, mode | |
7547 | STRccD R, mode. */ | |
7548 | ||
a737bd4d | 7549 | static void |
c19d1205 | 7550 | do_ldrd (void) |
a737bd4d | 7551 | { |
c19d1205 ZW |
7552 | constraint (inst.operands[0].reg % 2 != 0, |
7553 | _("first destination register must be even")); | |
7554 | constraint (inst.operands[1].present | |
7555 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
7556 | _("can only load two consecutive registers")); | |
7557 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
7558 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 7559 | |
c19d1205 ZW |
7560 | if (!inst.operands[1].present) |
7561 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
5f4273c7 | 7562 | |
c19d1205 | 7563 | if (inst.instruction & LOAD_BIT) |
a737bd4d | 7564 | { |
c19d1205 ZW |
7565 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
7566 | register and the first register written; we have to diagnose | |
7567 | overlap between the base and the second register written here. */ | |
ea6ef066 | 7568 | |
c19d1205 ZW |
7569 | if (inst.operands[2].reg == inst.operands[1].reg |
7570 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
7571 | as_warn (_("base register written back, and overlaps " | |
7572 | "second destination register")); | |
b05fe5cf | 7573 | |
c19d1205 ZW |
7574 | /* For an index-register load, the index register must not overlap the |
7575 | destination (even if not write-back). */ | |
7576 | else if (inst.operands[2].immisreg | |
ca3f61f7 NC |
7577 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg |
7578 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
c19d1205 | 7579 | as_warn (_("index register overlaps destination register")); |
b05fe5cf | 7580 | } |
c19d1205 ZW |
7581 | |
7582 | inst.instruction |= inst.operands[0].reg << 12; | |
7583 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
7584 | } |
7585 | ||
7586 | static void | |
c19d1205 | 7587 | do_ldrex (void) |
b05fe5cf | 7588 | { |
c19d1205 ZW |
7589 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
7590 | || inst.operands[1].postind || inst.operands[1].writeback | |
7591 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
01cfc07f NC |
7592 | || inst.operands[1].negative |
7593 | /* This can arise if the programmer has written | |
7594 | strex rN, rM, foo | |
7595 | or if they have mistakenly used a register name as the last | |
7596 | operand, eg: | |
7597 | strex rN, rM, rX | |
7598 | It is very difficult to distinguish between these two cases | |
7599 | because "rX" might actually be a label. ie the register | |
7600 | name has been occluded by a symbol of the same name. So we | |
7601 | just generate a general 'bad addressing mode' type error | |
7602 | message and leave it up to the programmer to discover the | |
7603 | true cause and fix their mistake. */ | |
7604 | || (inst.operands[1].reg == REG_PC), | |
7605 | BAD_ADDR_MODE); | |
b05fe5cf | 7606 | |
c19d1205 ZW |
7607 | constraint (inst.reloc.exp.X_op != O_constant |
7608 | || inst.reloc.exp.X_add_number != 0, | |
7609 | _("offset must be zero in ARM encoding")); | |
b05fe5cf | 7610 | |
5be8be5d DG |
7611 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
7612 | ||
c19d1205 ZW |
7613 | inst.instruction |= inst.operands[0].reg << 12; |
7614 | inst.instruction |= inst.operands[1].reg << 16; | |
7615 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b05fe5cf ZW |
7616 | } |
7617 | ||
7618 | static void | |
c19d1205 | 7619 | do_ldrexd (void) |
b05fe5cf | 7620 | { |
c19d1205 ZW |
7621 | constraint (inst.operands[0].reg % 2 != 0, |
7622 | _("even register required")); | |
7623 | constraint (inst.operands[1].present | |
7624 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
7625 | _("can only load two consecutive registers")); | |
7626 | /* If op 1 were present and equal to PC, this function wouldn't | |
7627 | have been called in the first place. */ | |
7628 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 7629 | |
c19d1205 ZW |
7630 | inst.instruction |= inst.operands[0].reg << 12; |
7631 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
7632 | } |
7633 | ||
7634 | static void | |
c19d1205 | 7635 | do_ldst (void) |
b05fe5cf | 7636 | { |
c19d1205 ZW |
7637 | inst.instruction |= inst.operands[0].reg << 12; |
7638 | if (!inst.operands[1].isreg) | |
7639 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) | |
b05fe5cf | 7640 | return; |
c19d1205 | 7641 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
7642 | } |
7643 | ||
7644 | static void | |
c19d1205 | 7645 | do_ldstt (void) |
b05fe5cf | 7646 | { |
c19d1205 ZW |
7647 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
7648 | reject [Rn,...]. */ | |
7649 | if (inst.operands[1].preind) | |
b05fe5cf | 7650 | { |
bd3ba5d1 NC |
7651 | constraint (inst.reloc.exp.X_op != O_constant |
7652 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 7653 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 7654 | |
c19d1205 ZW |
7655 | inst.operands[1].preind = 0; |
7656 | inst.operands[1].postind = 1; | |
7657 | inst.operands[1].writeback = 1; | |
b05fe5cf | 7658 | } |
c19d1205 ZW |
7659 | inst.instruction |= inst.operands[0].reg << 12; |
7660 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
7661 | } | |
b05fe5cf | 7662 | |
c19d1205 | 7663 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 7664 | |
c19d1205 ZW |
7665 | static void |
7666 | do_ldstv4 (void) | |
7667 | { | |
ff4a8d2b | 7668 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 ZW |
7669 | inst.instruction |= inst.operands[0].reg << 12; |
7670 | if (!inst.operands[1].isreg) | |
7671 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) | |
b05fe5cf | 7672 | return; |
c19d1205 | 7673 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
7674 | } |
7675 | ||
7676 | static void | |
c19d1205 | 7677 | do_ldsttv4 (void) |
b05fe5cf | 7678 | { |
c19d1205 ZW |
7679 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
7680 | reject [Rn,...]. */ | |
7681 | if (inst.operands[1].preind) | |
b05fe5cf | 7682 | { |
bd3ba5d1 NC |
7683 | constraint (inst.reloc.exp.X_op != O_constant |
7684 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 7685 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 7686 | |
c19d1205 ZW |
7687 | inst.operands[1].preind = 0; |
7688 | inst.operands[1].postind = 1; | |
7689 | inst.operands[1].writeback = 1; | |
b05fe5cf | 7690 | } |
c19d1205 ZW |
7691 | inst.instruction |= inst.operands[0].reg << 12; |
7692 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
7693 | } | |
b05fe5cf | 7694 | |
c19d1205 ZW |
7695 | /* Co-processor register load/store. |
7696 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
7697 | static void | |
7698 | do_lstc (void) | |
7699 | { | |
7700 | inst.instruction |= inst.operands[0].reg << 8; | |
7701 | inst.instruction |= inst.operands[1].reg << 12; | |
7702 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
7703 | } |
7704 | ||
b05fe5cf | 7705 | static void |
c19d1205 | 7706 | do_mlas (void) |
b05fe5cf | 7707 | { |
8fb9d7b9 | 7708 | /* This restriction does not apply to mls (nor to mla in v6 or later). */ |
c19d1205 | 7709 | if (inst.operands[0].reg == inst.operands[1].reg |
8fb9d7b9 | 7710 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) |
c19d1205 | 7711 | && !(inst.instruction & 0x00400000)) |
8fb9d7b9 | 7712 | as_tsktsk (_("Rd and Rm should be different in mla")); |
b05fe5cf | 7713 | |
c19d1205 ZW |
7714 | inst.instruction |= inst.operands[0].reg << 16; |
7715 | inst.instruction |= inst.operands[1].reg; | |
7716 | inst.instruction |= inst.operands[2].reg << 8; | |
7717 | inst.instruction |= inst.operands[3].reg << 12; | |
c19d1205 | 7718 | } |
b05fe5cf | 7719 | |
c19d1205 ZW |
7720 | static void |
7721 | do_mov (void) | |
7722 | { | |
7723 | inst.instruction |= inst.operands[0].reg << 12; | |
7724 | encode_arm_shifter_operand (1); | |
7725 | } | |
b05fe5cf | 7726 | |
c19d1205 ZW |
7727 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
7728 | static void | |
7729 | do_mov16 (void) | |
7730 | { | |
b6895b4f PB |
7731 | bfd_vma imm; |
7732 | bfd_boolean top; | |
7733 | ||
7734 | top = (inst.instruction & 0x00400000) != 0; | |
7735 | constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, | |
7736 | _(":lower16: not allowed this instruction")); | |
7737 | constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, | |
7738 | _(":upper16: not allowed instruction")); | |
c19d1205 | 7739 | inst.instruction |= inst.operands[0].reg << 12; |
b6895b4f PB |
7740 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
7741 | { | |
7742 | imm = inst.reloc.exp.X_add_number; | |
7743 | /* The value is in two pieces: 0:11, 16:19. */ | |
7744 | inst.instruction |= (imm & 0x00000fff); | |
7745 | inst.instruction |= (imm & 0x0000f000) << 4; | |
7746 | } | |
b05fe5cf | 7747 | } |
b99bd4ef | 7748 | |
037e8744 JB |
7749 | static void do_vfp_nsyn_opcode (const char *); |
7750 | ||
7751 | static int | |
7752 | do_vfp_nsyn_mrs (void) | |
7753 | { | |
7754 | if (inst.operands[0].isvec) | |
7755 | { | |
7756 | if (inst.operands[1].reg != 1) | |
7757 | first_error (_("operand 1 must be FPSCR")); | |
7758 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
7759 | memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); | |
7760 | do_vfp_nsyn_opcode ("fmstat"); | |
7761 | } | |
7762 | else if (inst.operands[1].isvec) | |
7763 | do_vfp_nsyn_opcode ("fmrx"); | |
7764 | else | |
7765 | return FAIL; | |
5f4273c7 | 7766 | |
037e8744 JB |
7767 | return SUCCESS; |
7768 | } | |
7769 | ||
7770 | static int | |
7771 | do_vfp_nsyn_msr (void) | |
7772 | { | |
7773 | if (inst.operands[0].isvec) | |
7774 | do_vfp_nsyn_opcode ("fmxr"); | |
7775 | else | |
7776 | return FAIL; | |
7777 | ||
7778 | return SUCCESS; | |
7779 | } | |
7780 | ||
f7c21dc7 NC |
7781 | static void |
7782 | do_vmrs (void) | |
7783 | { | |
7784 | unsigned Rt = inst.operands[0].reg; | |
7785 | ||
7786 | if (thumb_mode && inst.operands[0].reg == REG_SP) | |
7787 | { | |
7788 | inst.error = BAD_SP; | |
7789 | return; | |
7790 | } | |
7791 | ||
7792 | /* APSR_ sets isvec. All other refs to PC are illegal. */ | |
7793 | if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC) | |
7794 | { | |
7795 | inst.error = BAD_PC; | |
7796 | return; | |
7797 | } | |
7798 | ||
7799 | if (inst.operands[1].reg != 1) | |
7800 | first_error (_("operand 1 must be FPSCR")); | |
7801 | ||
7802 | inst.instruction |= (Rt << 12); | |
7803 | } | |
7804 | ||
7805 | static void | |
7806 | do_vmsr (void) | |
7807 | { | |
7808 | unsigned Rt = inst.operands[1].reg; | |
7809 | ||
7810 | if (thumb_mode) | |
7811 | reject_bad_reg (Rt); | |
7812 | else if (Rt == REG_PC) | |
7813 | { | |
7814 | inst.error = BAD_PC; | |
7815 | return; | |
7816 | } | |
7817 | ||
7818 | if (inst.operands[0].reg != 1) | |
7819 | first_error (_("operand 0 must be FPSCR")); | |
7820 | ||
7821 | inst.instruction |= (Rt << 12); | |
7822 | } | |
7823 | ||
b99bd4ef | 7824 | static void |
c19d1205 | 7825 | do_mrs (void) |
b99bd4ef | 7826 | { |
037e8744 JB |
7827 | if (do_vfp_nsyn_mrs () == SUCCESS) |
7828 | return; | |
7829 | ||
c19d1205 ZW |
7830 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ |
7831 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
7832 | != (PSR_c|PSR_f), | |
7833 | _("'CPSR' or 'SPSR' expected")); | |
ff4a8d2b | 7834 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 ZW |
7835 | inst.instruction |= inst.operands[0].reg << 12; |
7836 | inst.instruction |= (inst.operands[1].imm & SPSR_BIT); | |
7837 | } | |
b99bd4ef | 7838 | |
c19d1205 ZW |
7839 | /* Two possible forms: |
7840 | "{C|S}PSR_<field>, Rm", | |
7841 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 7842 | |
c19d1205 ZW |
7843 | static void |
7844 | do_msr (void) | |
7845 | { | |
037e8744 JB |
7846 | if (do_vfp_nsyn_msr () == SUCCESS) |
7847 | return; | |
7848 | ||
c19d1205 ZW |
7849 | inst.instruction |= inst.operands[0].imm; |
7850 | if (inst.operands[1].isreg) | |
7851 | inst.instruction |= inst.operands[1].reg; | |
7852 | else | |
b99bd4ef | 7853 | { |
c19d1205 ZW |
7854 | inst.instruction |= INST_IMMEDIATE; |
7855 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
7856 | inst.reloc.pc_rel = 0; | |
b99bd4ef | 7857 | } |
b99bd4ef NC |
7858 | } |
7859 | ||
c19d1205 ZW |
7860 | static void |
7861 | do_mul (void) | |
a737bd4d | 7862 | { |
ff4a8d2b NC |
7863 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
7864 | ||
c19d1205 ZW |
7865 | if (!inst.operands[2].present) |
7866 | inst.operands[2].reg = inst.operands[0].reg; | |
7867 | inst.instruction |= inst.operands[0].reg << 16; | |
7868 | inst.instruction |= inst.operands[1].reg; | |
7869 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 7870 | |
8fb9d7b9 MS |
7871 | if (inst.operands[0].reg == inst.operands[1].reg |
7872 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
7873 | as_tsktsk (_("Rd and Rm should be different in mul")); | |
a737bd4d NC |
7874 | } |
7875 | ||
c19d1205 ZW |
7876 | /* Long Multiply Parser |
7877 | UMULL RdLo, RdHi, Rm, Rs | |
7878 | SMULL RdLo, RdHi, Rm, Rs | |
7879 | UMLAL RdLo, RdHi, Rm, Rs | |
7880 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
7881 | |
7882 | static void | |
c19d1205 | 7883 | do_mull (void) |
b99bd4ef | 7884 | { |
c19d1205 ZW |
7885 | inst.instruction |= inst.operands[0].reg << 12; |
7886 | inst.instruction |= inst.operands[1].reg << 16; | |
7887 | inst.instruction |= inst.operands[2].reg; | |
7888 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 7889 | |
682b27ad PB |
7890 | /* rdhi and rdlo must be different. */ |
7891 | if (inst.operands[0].reg == inst.operands[1].reg) | |
7892 | as_tsktsk (_("rdhi and rdlo must be different")); | |
7893 | ||
7894 | /* rdhi, rdlo and rm must all be different before armv6. */ | |
7895 | if ((inst.operands[0].reg == inst.operands[2].reg | |
c19d1205 | 7896 | || inst.operands[1].reg == inst.operands[2].reg) |
682b27ad | 7897 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) |
c19d1205 ZW |
7898 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); |
7899 | } | |
b99bd4ef | 7900 | |
c19d1205 ZW |
7901 | static void |
7902 | do_nop (void) | |
7903 | { | |
e7495e45 NS |
7904 | if (inst.operands[0].present |
7905 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k)) | |
c19d1205 ZW |
7906 | { |
7907 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
7908 | inst.instruction &= 0xf0000000; | |
e7495e45 NS |
7909 | inst.instruction |= 0x0320f000; |
7910 | if (inst.operands[0].present) | |
7911 | inst.instruction |= inst.operands[0].imm; | |
c19d1205 | 7912 | } |
b99bd4ef NC |
7913 | } |
7914 | ||
c19d1205 ZW |
7915 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
7916 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
7917 | Condition defaults to COND_ALWAYS. | |
7918 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
7919 | |
7920 | static void | |
c19d1205 | 7921 | do_pkhbt (void) |
b99bd4ef | 7922 | { |
c19d1205 ZW |
7923 | inst.instruction |= inst.operands[0].reg << 12; |
7924 | inst.instruction |= inst.operands[1].reg << 16; | |
7925 | inst.instruction |= inst.operands[2].reg; | |
7926 | if (inst.operands[3].present) | |
7927 | encode_arm_shift (3); | |
7928 | } | |
b99bd4ef | 7929 | |
c19d1205 | 7930 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 7931 | |
c19d1205 ZW |
7932 | static void |
7933 | do_pkhtb (void) | |
7934 | { | |
7935 | if (!inst.operands[3].present) | |
b99bd4ef | 7936 | { |
c19d1205 ZW |
7937 | /* If the shift specifier is omitted, turn the instruction |
7938 | into pkhbt rd, rm, rn. */ | |
7939 | inst.instruction &= 0xfff00010; | |
7940 | inst.instruction |= inst.operands[0].reg << 12; | |
7941 | inst.instruction |= inst.operands[1].reg; | |
7942 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
7943 | } |
7944 | else | |
7945 | { | |
c19d1205 ZW |
7946 | inst.instruction |= inst.operands[0].reg << 12; |
7947 | inst.instruction |= inst.operands[1].reg << 16; | |
7948 | inst.instruction |= inst.operands[2].reg; | |
7949 | encode_arm_shift (3); | |
b99bd4ef NC |
7950 | } |
7951 | } | |
7952 | ||
c19d1205 ZW |
7953 | /* ARMv5TE: Preload-Cache |
7954 | ||
7955 | PLD <addr_mode> | |
7956 | ||
7957 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
7958 | |
7959 | static void | |
c19d1205 | 7960 | do_pld (void) |
b99bd4ef | 7961 | { |
c19d1205 ZW |
7962 | constraint (!inst.operands[0].isreg, |
7963 | _("'[' expected after PLD mnemonic")); | |
7964 | constraint (inst.operands[0].postind, | |
7965 | _("post-indexed expression used in preload instruction")); | |
7966 | constraint (inst.operands[0].writeback, | |
7967 | _("writeback used in preload instruction")); | |
7968 | constraint (!inst.operands[0].preind, | |
7969 | _("unindexed addressing used in preload instruction")); | |
c19d1205 ZW |
7970 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
7971 | } | |
b99bd4ef | 7972 | |
62b3e311 PB |
7973 | /* ARMv7: PLI <addr_mode> */ |
7974 | static void | |
7975 | do_pli (void) | |
7976 | { | |
7977 | constraint (!inst.operands[0].isreg, | |
7978 | _("'[' expected after PLI mnemonic")); | |
7979 | constraint (inst.operands[0].postind, | |
7980 | _("post-indexed expression used in preload instruction")); | |
7981 | constraint (inst.operands[0].writeback, | |
7982 | _("writeback used in preload instruction")); | |
7983 | constraint (!inst.operands[0].preind, | |
7984 | _("unindexed addressing used in preload instruction")); | |
7985 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
7986 | inst.instruction &= ~PRE_INDEX; | |
7987 | } | |
7988 | ||
c19d1205 ZW |
7989 | static void |
7990 | do_push_pop (void) | |
7991 | { | |
7992 | inst.operands[1] = inst.operands[0]; | |
7993 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
7994 | inst.operands[0].isreg = 1; | |
7995 | inst.operands[0].writeback = 1; | |
7996 | inst.operands[0].reg = REG_SP; | |
7997 | do_ldmstm (); | |
7998 | } | |
b99bd4ef | 7999 | |
c19d1205 ZW |
8000 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
8001 | word at the specified address and the following word | |
8002 | respectively. | |
8003 | Unconditionally executed. | |
8004 | Error if Rn is R15. */ | |
b99bd4ef | 8005 | |
c19d1205 ZW |
8006 | static void |
8007 | do_rfe (void) | |
8008 | { | |
8009 | inst.instruction |= inst.operands[0].reg << 16; | |
8010 | if (inst.operands[0].writeback) | |
8011 | inst.instruction |= WRITE_BACK; | |
8012 | } | |
b99bd4ef | 8013 | |
c19d1205 | 8014 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 8015 | |
c19d1205 ZW |
8016 | static void |
8017 | do_ssat (void) | |
8018 | { | |
8019 | inst.instruction |= inst.operands[0].reg << 12; | |
8020 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
8021 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 8022 | |
c19d1205 ZW |
8023 | if (inst.operands[3].present) |
8024 | encode_arm_shift (3); | |
b99bd4ef NC |
8025 | } |
8026 | ||
c19d1205 | 8027 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
8028 | |
8029 | static void | |
c19d1205 | 8030 | do_usat (void) |
b99bd4ef | 8031 | { |
c19d1205 ZW |
8032 | inst.instruction |= inst.operands[0].reg << 12; |
8033 | inst.instruction |= inst.operands[1].imm << 16; | |
8034 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 8035 | |
c19d1205 ZW |
8036 | if (inst.operands[3].present) |
8037 | encode_arm_shift (3); | |
b99bd4ef NC |
8038 | } |
8039 | ||
c19d1205 | 8040 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
8041 | |
8042 | static void | |
c19d1205 | 8043 | do_ssat16 (void) |
09d92015 | 8044 | { |
c19d1205 ZW |
8045 | inst.instruction |= inst.operands[0].reg << 12; |
8046 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
8047 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
8048 | } |
8049 | ||
c19d1205 ZW |
8050 | static void |
8051 | do_usat16 (void) | |
a737bd4d | 8052 | { |
c19d1205 ZW |
8053 | inst.instruction |= inst.operands[0].reg << 12; |
8054 | inst.instruction |= inst.operands[1].imm << 16; | |
8055 | inst.instruction |= inst.operands[2].reg; | |
8056 | } | |
a737bd4d | 8057 | |
c19d1205 ZW |
8058 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
8059 | preserving the other bits. | |
a737bd4d | 8060 | |
c19d1205 ZW |
8061 | setend <endian_specifier>, where <endian_specifier> is either |
8062 | BE or LE. */ | |
a737bd4d | 8063 | |
c19d1205 ZW |
8064 | static void |
8065 | do_setend (void) | |
8066 | { | |
8067 | if (inst.operands[0].imm) | |
8068 | inst.instruction |= 0x200; | |
a737bd4d NC |
8069 | } |
8070 | ||
8071 | static void | |
c19d1205 | 8072 | do_shift (void) |
a737bd4d | 8073 | { |
c19d1205 ZW |
8074 | unsigned int Rm = (inst.operands[1].present |
8075 | ? inst.operands[1].reg | |
8076 | : inst.operands[0].reg); | |
a737bd4d | 8077 | |
c19d1205 ZW |
8078 | inst.instruction |= inst.operands[0].reg << 12; |
8079 | inst.instruction |= Rm; | |
8080 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 8081 | { |
c19d1205 ZW |
8082 | inst.instruction |= inst.operands[2].reg << 8; |
8083 | inst.instruction |= SHIFT_BY_REG; | |
a737bd4d NC |
8084 | } |
8085 | else | |
c19d1205 | 8086 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
8087 | } |
8088 | ||
09d92015 | 8089 | static void |
3eb17e6b | 8090 | do_smc (void) |
09d92015 | 8091 | { |
3eb17e6b | 8092 | inst.reloc.type = BFD_RELOC_ARM_SMC; |
c19d1205 | 8093 | inst.reloc.pc_rel = 0; |
09d92015 MM |
8094 | } |
8095 | ||
09d92015 | 8096 | static void |
c19d1205 | 8097 | do_swi (void) |
09d92015 | 8098 | { |
c19d1205 ZW |
8099 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
8100 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
8101 | } |
8102 | ||
c19d1205 ZW |
8103 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
8104 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
8105 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
8106 | Error if any register is R15. */ | |
e16bb312 | 8107 | |
c19d1205 ZW |
8108 | static void |
8109 | do_smla (void) | |
e16bb312 | 8110 | { |
c19d1205 ZW |
8111 | inst.instruction |= inst.operands[0].reg << 16; |
8112 | inst.instruction |= inst.operands[1].reg; | |
8113 | inst.instruction |= inst.operands[2].reg << 8; | |
8114 | inst.instruction |= inst.operands[3].reg << 12; | |
8115 | } | |
a737bd4d | 8116 | |
c19d1205 ZW |
8117 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
8118 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
8119 | Error if any register is R15. | |
8120 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 8121 | |
c19d1205 ZW |
8122 | static void |
8123 | do_smlal (void) | |
8124 | { | |
8125 | inst.instruction |= inst.operands[0].reg << 12; | |
8126 | inst.instruction |= inst.operands[1].reg << 16; | |
8127 | inst.instruction |= inst.operands[2].reg; | |
8128 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 8129 | |
c19d1205 ZW |
8130 | if (inst.operands[0].reg == inst.operands[1].reg) |
8131 | as_tsktsk (_("rdhi and rdlo must be different")); | |
8132 | } | |
a737bd4d | 8133 | |
c19d1205 ZW |
8134 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
8135 | SMULxy{cond} Rd,Rm,Rs | |
8136 | Error if any register is R15. */ | |
a737bd4d | 8137 | |
c19d1205 ZW |
8138 | static void |
8139 | do_smul (void) | |
8140 | { | |
8141 | inst.instruction |= inst.operands[0].reg << 16; | |
8142 | inst.instruction |= inst.operands[1].reg; | |
8143 | inst.instruction |= inst.operands[2].reg << 8; | |
8144 | } | |
a737bd4d | 8145 | |
b6702015 PB |
8146 | /* ARM V6 srs (argument parse). The variable fields in the encoding are |
8147 | the same for both ARM and Thumb-2. */ | |
a737bd4d | 8148 | |
c19d1205 ZW |
8149 | static void |
8150 | do_srs (void) | |
8151 | { | |
b6702015 PB |
8152 | int reg; |
8153 | ||
8154 | if (inst.operands[0].present) | |
8155 | { | |
8156 | reg = inst.operands[0].reg; | |
fdfde340 | 8157 | constraint (reg != REG_SP, _("SRS base register must be r13")); |
b6702015 PB |
8158 | } |
8159 | else | |
fdfde340 | 8160 | reg = REG_SP; |
b6702015 PB |
8161 | |
8162 | inst.instruction |= reg << 16; | |
8163 | inst.instruction |= inst.operands[1].imm; | |
8164 | if (inst.operands[0].writeback || inst.operands[1].writeback) | |
c19d1205 ZW |
8165 | inst.instruction |= WRITE_BACK; |
8166 | } | |
a737bd4d | 8167 | |
c19d1205 | 8168 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 8169 | |
c19d1205 ZW |
8170 | static void |
8171 | do_strex (void) | |
8172 | { | |
8173 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
8174 | || inst.operands[2].postind || inst.operands[2].writeback | |
8175 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
01cfc07f NC |
8176 | || inst.operands[2].negative |
8177 | /* See comment in do_ldrex(). */ | |
8178 | || (inst.operands[2].reg == REG_PC), | |
8179 | BAD_ADDR_MODE); | |
a737bd4d | 8180 | |
c19d1205 ZW |
8181 | constraint (inst.operands[0].reg == inst.operands[1].reg |
8182 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 8183 | |
c19d1205 ZW |
8184 | constraint (inst.reloc.exp.X_op != O_constant |
8185 | || inst.reloc.exp.X_add_number != 0, | |
8186 | _("offset must be zero in ARM encoding")); | |
a737bd4d | 8187 | |
c19d1205 ZW |
8188 | inst.instruction |= inst.operands[0].reg << 12; |
8189 | inst.instruction |= inst.operands[1].reg; | |
8190 | inst.instruction |= inst.operands[2].reg << 16; | |
8191 | inst.reloc.type = BFD_RELOC_UNUSED; | |
e16bb312 NC |
8192 | } |
8193 | ||
8194 | static void | |
c19d1205 | 8195 | do_strexd (void) |
e16bb312 | 8196 | { |
c19d1205 ZW |
8197 | constraint (inst.operands[1].reg % 2 != 0, |
8198 | _("even register required")); | |
8199 | constraint (inst.operands[2].present | |
8200 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
8201 | _("can only store two consecutive registers")); | |
8202 | /* If op 2 were present and equal to PC, this function wouldn't | |
8203 | have been called in the first place. */ | |
8204 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 8205 | |
c19d1205 ZW |
8206 | constraint (inst.operands[0].reg == inst.operands[1].reg |
8207 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
8208 | || inst.operands[0].reg == inst.operands[3].reg, | |
8209 | BAD_OVERLAP); | |
e16bb312 | 8210 | |
c19d1205 ZW |
8211 | inst.instruction |= inst.operands[0].reg << 12; |
8212 | inst.instruction |= inst.operands[1].reg; | |
8213 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
8214 | } |
8215 | ||
c19d1205 ZW |
8216 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
8217 | extends it to 32-bits, and adds the result to a value in another | |
8218 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
8219 | before extracting the 16-bit value. | |
8220 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
8221 | Condition defaults to COND_ALWAYS. | |
8222 | Error if any register uses R15. */ | |
8223 | ||
e16bb312 | 8224 | static void |
c19d1205 | 8225 | do_sxtah (void) |
e16bb312 | 8226 | { |
c19d1205 ZW |
8227 | inst.instruction |= inst.operands[0].reg << 12; |
8228 | inst.instruction |= inst.operands[1].reg << 16; | |
8229 | inst.instruction |= inst.operands[2].reg; | |
8230 | inst.instruction |= inst.operands[3].imm << 10; | |
8231 | } | |
e16bb312 | 8232 | |
c19d1205 | 8233 | /* ARM V6 SXTH. |
e16bb312 | 8234 | |
c19d1205 ZW |
8235 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
8236 | Condition defaults to COND_ALWAYS. | |
8237 | Error if any register uses R15. */ | |
e16bb312 NC |
8238 | |
8239 | static void | |
c19d1205 | 8240 | do_sxth (void) |
e16bb312 | 8241 | { |
c19d1205 ZW |
8242 | inst.instruction |= inst.operands[0].reg << 12; |
8243 | inst.instruction |= inst.operands[1].reg; | |
8244 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 8245 | } |
c19d1205 ZW |
8246 | \f |
8247 | /* VFP instructions. In a logical order: SP variant first, monad | |
8248 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
8249 | |
8250 | static void | |
c19d1205 | 8251 | do_vfp_sp_monadic (void) |
e16bb312 | 8252 | { |
5287ad62 JB |
8253 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8254 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
8255 | } |
8256 | ||
8257 | static void | |
c19d1205 | 8258 | do_vfp_sp_dyadic (void) |
e16bb312 | 8259 | { |
5287ad62 JB |
8260 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8261 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
8262 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
8263 | } |
8264 | ||
8265 | static void | |
c19d1205 | 8266 | do_vfp_sp_compare_z (void) |
e16bb312 | 8267 | { |
5287ad62 | 8268 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
8269 | } |
8270 | ||
8271 | static void | |
c19d1205 | 8272 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 8273 | { |
5287ad62 JB |
8274 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
8275 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
8276 | } |
8277 | ||
8278 | static void | |
c19d1205 | 8279 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 8280 | { |
5287ad62 JB |
8281 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8282 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
e16bb312 NC |
8283 | } |
8284 | ||
8285 | static void | |
c19d1205 | 8286 | do_vfp_reg_from_sp (void) |
e16bb312 | 8287 | { |
c19d1205 | 8288 | inst.instruction |= inst.operands[0].reg << 12; |
5287ad62 | 8289 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); |
e16bb312 NC |
8290 | } |
8291 | ||
8292 | static void | |
c19d1205 | 8293 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 8294 | { |
c19d1205 ZW |
8295 | constraint (inst.operands[2].imm != 2, |
8296 | _("only two consecutive VFP SP registers allowed here")); | |
8297 | inst.instruction |= inst.operands[0].reg << 12; | |
8298 | inst.instruction |= inst.operands[1].reg << 16; | |
5287ad62 | 8299 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); |
e16bb312 NC |
8300 | } |
8301 | ||
8302 | static void | |
c19d1205 | 8303 | do_vfp_sp_from_reg (void) |
e16bb312 | 8304 | { |
5287ad62 | 8305 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); |
c19d1205 | 8306 | inst.instruction |= inst.operands[1].reg << 12; |
e16bb312 NC |
8307 | } |
8308 | ||
8309 | static void | |
c19d1205 | 8310 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 8311 | { |
c19d1205 ZW |
8312 | constraint (inst.operands[0].imm != 2, |
8313 | _("only two consecutive VFP SP registers allowed here")); | |
5287ad62 | 8314 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); |
c19d1205 ZW |
8315 | inst.instruction |= inst.operands[1].reg << 12; |
8316 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
8317 | } |
8318 | ||
8319 | static void | |
c19d1205 | 8320 | do_vfp_sp_ldst (void) |
e16bb312 | 8321 | { |
5287ad62 | 8322 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
c19d1205 | 8323 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
8324 | } |
8325 | ||
8326 | static void | |
c19d1205 | 8327 | do_vfp_dp_ldst (void) |
e16bb312 | 8328 | { |
5287ad62 | 8329 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
c19d1205 | 8330 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
8331 | } |
8332 | ||
c19d1205 | 8333 | |
e16bb312 | 8334 | static void |
c19d1205 | 8335 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 8336 | { |
c19d1205 ZW |
8337 | if (inst.operands[0].writeback) |
8338 | inst.instruction |= WRITE_BACK; | |
8339 | else | |
8340 | constraint (ldstm_type != VFP_LDSTMIA, | |
8341 | _("this addressing mode requires base-register writeback")); | |
8342 | inst.instruction |= inst.operands[0].reg << 16; | |
5287ad62 | 8343 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); |
c19d1205 | 8344 | inst.instruction |= inst.operands[1].imm; |
e16bb312 NC |
8345 | } |
8346 | ||
8347 | static void | |
c19d1205 | 8348 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 8349 | { |
c19d1205 | 8350 | int count; |
e16bb312 | 8351 | |
c19d1205 ZW |
8352 | if (inst.operands[0].writeback) |
8353 | inst.instruction |= WRITE_BACK; | |
8354 | else | |
8355 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
8356 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 8357 | |
c19d1205 | 8358 | inst.instruction |= inst.operands[0].reg << 16; |
5287ad62 | 8359 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
e16bb312 | 8360 | |
c19d1205 ZW |
8361 | count = inst.operands[1].imm << 1; |
8362 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
8363 | count += 1; | |
e16bb312 | 8364 | |
c19d1205 | 8365 | inst.instruction |= count; |
e16bb312 NC |
8366 | } |
8367 | ||
8368 | static void | |
c19d1205 | 8369 | do_vfp_sp_ldstmia (void) |
e16bb312 | 8370 | { |
c19d1205 | 8371 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
8372 | } |
8373 | ||
8374 | static void | |
c19d1205 | 8375 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 8376 | { |
c19d1205 | 8377 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
8378 | } |
8379 | ||
8380 | static void | |
c19d1205 | 8381 | do_vfp_dp_ldstmia (void) |
e16bb312 | 8382 | { |
c19d1205 | 8383 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
8384 | } |
8385 | ||
8386 | static void | |
c19d1205 | 8387 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 8388 | { |
c19d1205 | 8389 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
8390 | } |
8391 | ||
8392 | static void | |
c19d1205 | 8393 | do_vfp_xp_ldstmia (void) |
e16bb312 | 8394 | { |
c19d1205 ZW |
8395 | vfp_dp_ldstm (VFP_LDSTMIAX); |
8396 | } | |
e16bb312 | 8397 | |
c19d1205 ZW |
8398 | static void |
8399 | do_vfp_xp_ldstmdb (void) | |
8400 | { | |
8401 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 8402 | } |
5287ad62 JB |
8403 | |
8404 | static void | |
8405 | do_vfp_dp_rd_rm (void) | |
8406 | { | |
8407 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8408 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
8409 | } | |
8410 | ||
8411 | static void | |
8412 | do_vfp_dp_rn_rd (void) | |
8413 | { | |
8414 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); | |
8415 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
8416 | } | |
8417 | ||
8418 | static void | |
8419 | do_vfp_dp_rd_rn (void) | |
8420 | { | |
8421 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8422 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
8423 | } | |
8424 | ||
8425 | static void | |
8426 | do_vfp_dp_rd_rn_rm (void) | |
8427 | { | |
8428 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8429 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
8430 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); | |
8431 | } | |
8432 | ||
8433 | static void | |
8434 | do_vfp_dp_rd (void) | |
8435 | { | |
8436 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8437 | } | |
8438 | ||
8439 | static void | |
8440 | do_vfp_dp_rm_rd_rn (void) | |
8441 | { | |
8442 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); | |
8443 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
8444 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); | |
8445 | } | |
8446 | ||
8447 | /* VFPv3 instructions. */ | |
8448 | static void | |
8449 | do_vfp_sp_const (void) | |
8450 | { | |
8451 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
00249aaa PB |
8452 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
8453 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
8454 | } |
8455 | ||
8456 | static void | |
8457 | do_vfp_dp_const (void) | |
8458 | { | |
8459 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
00249aaa PB |
8460 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
8461 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
8462 | } |
8463 | ||
8464 | static void | |
8465 | vfp_conv (int srcsize) | |
8466 | { | |
8467 | unsigned immbits = srcsize - inst.operands[1].imm; | |
8468 | inst.instruction |= (immbits & 1) << 5; | |
8469 | inst.instruction |= (immbits >> 1); | |
8470 | } | |
8471 | ||
8472 | static void | |
8473 | do_vfp_sp_conv_16 (void) | |
8474 | { | |
8475 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
8476 | vfp_conv (16); | |
8477 | } | |
8478 | ||
8479 | static void | |
8480 | do_vfp_dp_conv_16 (void) | |
8481 | { | |
8482 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8483 | vfp_conv (16); | |
8484 | } | |
8485 | ||
8486 | static void | |
8487 | do_vfp_sp_conv_32 (void) | |
8488 | { | |
8489 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
8490 | vfp_conv (32); | |
8491 | } | |
8492 | ||
8493 | static void | |
8494 | do_vfp_dp_conv_32 (void) | |
8495 | { | |
8496 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8497 | vfp_conv (32); | |
8498 | } | |
c19d1205 ZW |
8499 | \f |
8500 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 8501 | |
c19d1205 ZW |
8502 | static void |
8503 | do_fpa_cmp (void) | |
8504 | { | |
8505 | inst.instruction |= inst.operands[0].reg << 16; | |
8506 | inst.instruction |= inst.operands[1].reg; | |
8507 | } | |
b99bd4ef NC |
8508 | |
8509 | static void | |
c19d1205 | 8510 | do_fpa_ldmstm (void) |
b99bd4ef | 8511 | { |
c19d1205 ZW |
8512 | inst.instruction |= inst.operands[0].reg << 12; |
8513 | switch (inst.operands[1].imm) | |
8514 | { | |
8515 | case 1: inst.instruction |= CP_T_X; break; | |
8516 | case 2: inst.instruction |= CP_T_Y; break; | |
8517 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
8518 | case 4: break; | |
8519 | default: abort (); | |
8520 | } | |
b99bd4ef | 8521 | |
c19d1205 ZW |
8522 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
8523 | { | |
8524 | /* The instruction specified "ea" or "fd", so we can only accept | |
8525 | [Rn]{!}. The instruction does not really support stacking or | |
8526 | unstacking, so we have to emulate these by setting appropriate | |
8527 | bits and offsets. */ | |
8528 | constraint (inst.reloc.exp.X_op != O_constant | |
8529 | || inst.reloc.exp.X_add_number != 0, | |
8530 | _("this instruction does not support indexing")); | |
b99bd4ef | 8531 | |
c19d1205 ZW |
8532 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
8533 | inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; | |
b99bd4ef | 8534 | |
c19d1205 ZW |
8535 | if (!(inst.instruction & INDEX_UP)) |
8536 | inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; | |
b99bd4ef | 8537 | |
c19d1205 ZW |
8538 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
8539 | { | |
8540 | inst.operands[2].preind = 0; | |
8541 | inst.operands[2].postind = 1; | |
8542 | } | |
8543 | } | |
b99bd4ef | 8544 | |
c19d1205 | 8545 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 8546 | } |
c19d1205 ZW |
8547 | \f |
8548 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 8549 | |
c19d1205 ZW |
8550 | static void |
8551 | do_iwmmxt_tandorc (void) | |
8552 | { | |
8553 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
8554 | } | |
b99bd4ef | 8555 | |
c19d1205 ZW |
8556 | static void |
8557 | do_iwmmxt_textrc (void) | |
8558 | { | |
8559 | inst.instruction |= inst.operands[0].reg << 12; | |
8560 | inst.instruction |= inst.operands[1].imm; | |
8561 | } | |
b99bd4ef NC |
8562 | |
8563 | static void | |
c19d1205 | 8564 | do_iwmmxt_textrm (void) |
b99bd4ef | 8565 | { |
c19d1205 ZW |
8566 | inst.instruction |= inst.operands[0].reg << 12; |
8567 | inst.instruction |= inst.operands[1].reg << 16; | |
8568 | inst.instruction |= inst.operands[2].imm; | |
8569 | } | |
b99bd4ef | 8570 | |
c19d1205 ZW |
8571 | static void |
8572 | do_iwmmxt_tinsr (void) | |
8573 | { | |
8574 | inst.instruction |= inst.operands[0].reg << 16; | |
8575 | inst.instruction |= inst.operands[1].reg << 12; | |
8576 | inst.instruction |= inst.operands[2].imm; | |
8577 | } | |
b99bd4ef | 8578 | |
c19d1205 ZW |
8579 | static void |
8580 | do_iwmmxt_tmia (void) | |
8581 | { | |
8582 | inst.instruction |= inst.operands[0].reg << 5; | |
8583 | inst.instruction |= inst.operands[1].reg; | |
8584 | inst.instruction |= inst.operands[2].reg << 12; | |
8585 | } | |
b99bd4ef | 8586 | |
c19d1205 ZW |
8587 | static void |
8588 | do_iwmmxt_waligni (void) | |
8589 | { | |
8590 | inst.instruction |= inst.operands[0].reg << 12; | |
8591 | inst.instruction |= inst.operands[1].reg << 16; | |
8592 | inst.instruction |= inst.operands[2].reg; | |
8593 | inst.instruction |= inst.operands[3].imm << 20; | |
8594 | } | |
b99bd4ef | 8595 | |
2d447fca JM |
8596 | static void |
8597 | do_iwmmxt_wmerge (void) | |
8598 | { | |
8599 | inst.instruction |= inst.operands[0].reg << 12; | |
8600 | inst.instruction |= inst.operands[1].reg << 16; | |
8601 | inst.instruction |= inst.operands[2].reg; | |
8602 | inst.instruction |= inst.operands[3].imm << 21; | |
8603 | } | |
8604 | ||
c19d1205 ZW |
8605 | static void |
8606 | do_iwmmxt_wmov (void) | |
8607 | { | |
8608 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
8609 | inst.instruction |= inst.operands[0].reg << 12; | |
8610 | inst.instruction |= inst.operands[1].reg << 16; | |
8611 | inst.instruction |= inst.operands[1].reg; | |
8612 | } | |
b99bd4ef | 8613 | |
c19d1205 ZW |
8614 | static void |
8615 | do_iwmmxt_wldstbh (void) | |
8616 | { | |
8f06b2d8 | 8617 | int reloc; |
c19d1205 | 8618 | inst.instruction |= inst.operands[0].reg << 12; |
8f06b2d8 PB |
8619 | if (thumb_mode) |
8620 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
8621 | else | |
8622 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
8623 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
8624 | } |
8625 | ||
c19d1205 ZW |
8626 | static void |
8627 | do_iwmmxt_wldstw (void) | |
8628 | { | |
8629 | /* RIWR_RIWC clears .isreg for a control register. */ | |
8630 | if (!inst.operands[0].isreg) | |
8631 | { | |
8632 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
8633 | inst.instruction |= 0xf0000000; | |
8634 | } | |
b99bd4ef | 8635 | |
c19d1205 ZW |
8636 | inst.instruction |= inst.operands[0].reg << 12; |
8637 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
8638 | } | |
b99bd4ef NC |
8639 | |
8640 | static void | |
c19d1205 | 8641 | do_iwmmxt_wldstd (void) |
b99bd4ef | 8642 | { |
c19d1205 | 8643 | inst.instruction |= inst.operands[0].reg << 12; |
2d447fca JM |
8644 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) |
8645 | && inst.operands[1].immisreg) | |
8646 | { | |
8647 | inst.instruction &= ~0x1a000ff; | |
8648 | inst.instruction |= (0xf << 28); | |
8649 | if (inst.operands[1].preind) | |
8650 | inst.instruction |= PRE_INDEX; | |
8651 | if (!inst.operands[1].negative) | |
8652 | inst.instruction |= INDEX_UP; | |
8653 | if (inst.operands[1].writeback) | |
8654 | inst.instruction |= WRITE_BACK; | |
8655 | inst.instruction |= inst.operands[1].reg << 16; | |
8656 | inst.instruction |= inst.reloc.exp.X_add_number << 4; | |
8657 | inst.instruction |= inst.operands[1].imm; | |
8658 | } | |
8659 | else | |
8660 | encode_arm_cp_address (1, TRUE, FALSE, 0); | |
c19d1205 | 8661 | } |
b99bd4ef | 8662 | |
c19d1205 ZW |
8663 | static void |
8664 | do_iwmmxt_wshufh (void) | |
8665 | { | |
8666 | inst.instruction |= inst.operands[0].reg << 12; | |
8667 | inst.instruction |= inst.operands[1].reg << 16; | |
8668 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
8669 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
8670 | } | |
b99bd4ef | 8671 | |
c19d1205 ZW |
8672 | static void |
8673 | do_iwmmxt_wzero (void) | |
8674 | { | |
8675 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
8676 | inst.instruction |= inst.operands[0].reg; | |
8677 | inst.instruction |= inst.operands[0].reg << 12; | |
8678 | inst.instruction |= inst.operands[0].reg << 16; | |
8679 | } | |
2d447fca JM |
8680 | |
8681 | static void | |
8682 | do_iwmmxt_wrwrwr_or_imm5 (void) | |
8683 | { | |
8684 | if (inst.operands[2].isreg) | |
8685 | do_rd_rn_rm (); | |
8686 | else { | |
8687 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), | |
8688 | _("immediate operand requires iWMMXt2")); | |
8689 | do_rd_rn (); | |
8690 | if (inst.operands[2].imm == 0) | |
8691 | { | |
8692 | switch ((inst.instruction >> 20) & 0xf) | |
8693 | { | |
8694 | case 4: | |
8695 | case 5: | |
8696 | case 6: | |
5f4273c7 | 8697 | case 7: |
2d447fca JM |
8698 | /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ |
8699 | inst.operands[2].imm = 16; | |
8700 | inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); | |
8701 | break; | |
8702 | case 8: | |
8703 | case 9: | |
8704 | case 10: | |
8705 | case 11: | |
8706 | /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ | |
8707 | inst.operands[2].imm = 32; | |
8708 | inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); | |
8709 | break; | |
8710 | case 12: | |
8711 | case 13: | |
8712 | case 14: | |
8713 | case 15: | |
8714 | { | |
8715 | /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ | |
8716 | unsigned long wrn; | |
8717 | wrn = (inst.instruction >> 16) & 0xf; | |
8718 | inst.instruction &= 0xff0fff0f; | |
8719 | inst.instruction |= wrn; | |
8720 | /* Bail out here; the instruction is now assembled. */ | |
8721 | return; | |
8722 | } | |
8723 | } | |
8724 | } | |
8725 | /* Map 32 -> 0, etc. */ | |
8726 | inst.operands[2].imm &= 0x1f; | |
8727 | inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); | |
8728 | } | |
8729 | } | |
c19d1205 ZW |
8730 | \f |
8731 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
8732 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 8733 | |
c19d1205 | 8734 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 8735 | |
c19d1205 ZW |
8736 | static void |
8737 | do_mav_triple (void) | |
8738 | { | |
8739 | inst.instruction |= inst.operands[0].reg << 16; | |
8740 | inst.instruction |= inst.operands[1].reg; | |
8741 | inst.instruction |= inst.operands[2].reg << 12; | |
8742 | } | |
b99bd4ef | 8743 | |
c19d1205 ZW |
8744 | /* Insns like "foo W,X,Y,Z". |
8745 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 8746 | |
c19d1205 ZW |
8747 | static void |
8748 | do_mav_quad (void) | |
8749 | { | |
8750 | inst.instruction |= inst.operands[0].reg << 5; | |
8751 | inst.instruction |= inst.operands[1].reg << 12; | |
8752 | inst.instruction |= inst.operands[2].reg << 16; | |
8753 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
8754 | } |
8755 | ||
c19d1205 ZW |
8756 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
8757 | static void | |
8758 | do_mav_dspsc (void) | |
a737bd4d | 8759 | { |
c19d1205 ZW |
8760 | inst.instruction |= inst.operands[1].reg << 12; |
8761 | } | |
a737bd4d | 8762 | |
c19d1205 ZW |
8763 | /* Maverick shift immediate instructions. |
8764 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
8765 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 8766 | |
c19d1205 ZW |
8767 | static void |
8768 | do_mav_shift (void) | |
8769 | { | |
8770 | int imm = inst.operands[2].imm; | |
a737bd4d | 8771 | |
c19d1205 ZW |
8772 | inst.instruction |= inst.operands[0].reg << 12; |
8773 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 8774 | |
c19d1205 ZW |
8775 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
8776 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
8777 | Bit 4 should be 0. */ | |
8778 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 8779 | |
c19d1205 ZW |
8780 | inst.instruction |= imm; |
8781 | } | |
8782 | \f | |
8783 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 8784 | |
c19d1205 ZW |
8785 | /* Xscale multiply-accumulate (argument parse) |
8786 | MIAcc acc0,Rm,Rs | |
8787 | MIAPHcc acc0,Rm,Rs | |
8788 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 8789 | |
c19d1205 ZW |
8790 | static void |
8791 | do_xsc_mia (void) | |
8792 | { | |
8793 | inst.instruction |= inst.operands[1].reg; | |
8794 | inst.instruction |= inst.operands[2].reg << 12; | |
8795 | } | |
a737bd4d | 8796 | |
c19d1205 | 8797 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 8798 | |
c19d1205 | 8799 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 8800 | |
c19d1205 ZW |
8801 | static void |
8802 | do_xsc_mar (void) | |
8803 | { | |
8804 | inst.instruction |= inst.operands[1].reg << 12; | |
8805 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
8806 | } |
8807 | ||
c19d1205 | 8808 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 8809 | |
c19d1205 | 8810 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
8811 | |
8812 | static void | |
c19d1205 | 8813 | do_xsc_mra (void) |
b99bd4ef | 8814 | { |
c19d1205 ZW |
8815 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
8816 | inst.instruction |= inst.operands[0].reg << 12; | |
8817 | inst.instruction |= inst.operands[1].reg << 16; | |
8818 | } | |
8819 | \f | |
8820 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 8821 | |
c19d1205 ZW |
8822 | /* inst.operands[i] is a shifted-register operand; encode |
8823 | it into inst.instruction in the format used by Thumb32. */ | |
8824 | ||
8825 | static void | |
8826 | encode_thumb32_shifted_operand (int i) | |
8827 | { | |
8828 | unsigned int value = inst.reloc.exp.X_add_number; | |
8829 | unsigned int shift = inst.operands[i].shift_kind; | |
b99bd4ef | 8830 | |
9c3c69f2 PB |
8831 | constraint (inst.operands[i].immisreg, |
8832 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
8833 | inst.instruction |= inst.operands[i].reg; |
8834 | if (shift == SHIFT_RRX) | |
8835 | inst.instruction |= SHIFT_ROR << 4; | |
8836 | else | |
b99bd4ef | 8837 | { |
c19d1205 ZW |
8838 | constraint (inst.reloc.exp.X_op != O_constant, |
8839 | _("expression too complex")); | |
8840 | ||
8841 | constraint (value > 32 | |
8842 | || (value == 32 && (shift == SHIFT_LSL | |
8843 | || shift == SHIFT_ROR)), | |
8844 | _("shift expression is too large")); | |
8845 | ||
8846 | if (value == 0) | |
8847 | shift = SHIFT_LSL; | |
8848 | else if (value == 32) | |
8849 | value = 0; | |
8850 | ||
8851 | inst.instruction |= shift << 4; | |
8852 | inst.instruction |= (value & 0x1c) << 10; | |
8853 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 8854 | } |
c19d1205 | 8855 | } |
b99bd4ef | 8856 | |
b99bd4ef | 8857 | |
c19d1205 ZW |
8858 | /* inst.operands[i] was set up by parse_address. Encode it into a |
8859 | Thumb32 format load or store instruction. Reject forms that cannot | |
8860 | be used with such instructions. If is_t is true, reject forms that | |
8861 | cannot be used with a T instruction; if is_d is true, reject forms | |
5be8be5d DG |
8862 | that cannot be used with a D instruction. If it is a store insn, |
8863 | reject PC in Rn. */ | |
b99bd4ef | 8864 | |
c19d1205 ZW |
8865 | static void |
8866 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
8867 | { | |
5be8be5d | 8868 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
c19d1205 ZW |
8869 | |
8870 | constraint (!inst.operands[i].isreg, | |
53365c0d | 8871 | _("Instruction does not support =N addresses")); |
b99bd4ef | 8872 | |
c19d1205 ZW |
8873 | inst.instruction |= inst.operands[i].reg << 16; |
8874 | if (inst.operands[i].immisreg) | |
b99bd4ef | 8875 | { |
5be8be5d | 8876 | constraint (is_pc, BAD_PC_ADDRESSING); |
c19d1205 ZW |
8877 | constraint (is_t || is_d, _("cannot use register index with this instruction")); |
8878 | constraint (inst.operands[i].negative, | |
8879 | _("Thumb does not support negative register indexing")); | |
8880 | constraint (inst.operands[i].postind, | |
8881 | _("Thumb does not support register post-indexing")); | |
8882 | constraint (inst.operands[i].writeback, | |
8883 | _("Thumb does not support register indexing with writeback")); | |
8884 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
8885 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 8886 | |
f40d1643 | 8887 | inst.instruction |= inst.operands[i].imm; |
c19d1205 | 8888 | if (inst.operands[i].shifted) |
b99bd4ef | 8889 | { |
c19d1205 ZW |
8890 | constraint (inst.reloc.exp.X_op != O_constant, |
8891 | _("expression too complex")); | |
9c3c69f2 PB |
8892 | constraint (inst.reloc.exp.X_add_number < 0 |
8893 | || inst.reloc.exp.X_add_number > 3, | |
c19d1205 | 8894 | _("shift out of range")); |
9c3c69f2 | 8895 | inst.instruction |= inst.reloc.exp.X_add_number << 4; |
c19d1205 ZW |
8896 | } |
8897 | inst.reloc.type = BFD_RELOC_UNUSED; | |
8898 | } | |
8899 | else if (inst.operands[i].preind) | |
8900 | { | |
5be8be5d | 8901 | constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK); |
f40d1643 | 8902 | constraint (is_t && inst.operands[i].writeback, |
c19d1205 | 8903 | _("cannot use writeback with this instruction")); |
5be8be5d DG |
8904 | constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0) |
8905 | && !inst.reloc.pc_rel, BAD_PC_ADDRESSING); | |
c19d1205 ZW |
8906 | |
8907 | if (is_d) | |
8908 | { | |
8909 | inst.instruction |= 0x01000000; | |
8910 | if (inst.operands[i].writeback) | |
8911 | inst.instruction |= 0x00200000; | |
b99bd4ef | 8912 | } |
c19d1205 | 8913 | else |
b99bd4ef | 8914 | { |
c19d1205 ZW |
8915 | inst.instruction |= 0x00000c00; |
8916 | if (inst.operands[i].writeback) | |
8917 | inst.instruction |= 0x00000100; | |
b99bd4ef | 8918 | } |
c19d1205 | 8919 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 8920 | } |
c19d1205 | 8921 | else if (inst.operands[i].postind) |
b99bd4ef | 8922 | { |
9c2799c2 | 8923 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
8924 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); |
8925 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
8926 | ||
8927 | if (is_d) | |
8928 | inst.instruction |= 0x00200000; | |
8929 | else | |
8930 | inst.instruction |= 0x00000900; | |
8931 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
8932 | } | |
8933 | else /* unindexed - only for coprocessor */ | |
8934 | inst.error = _("instruction does not accept unindexed addressing"); | |
8935 | } | |
8936 | ||
8937 | /* Table of Thumb instructions which exist in both 16- and 32-bit | |
8938 | encodings (the latter only in post-V6T2 cores). The index is the | |
8939 | value used in the insns table below. When there is more than one | |
8940 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
8941 | holds variant (1). |
8942 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 | 8943 | #define T16_32_TAB \ |
21d799b5 NC |
8944 | X(_adc, 4140, eb400000), \ |
8945 | X(_adcs, 4140, eb500000), \ | |
8946 | X(_add, 1c00, eb000000), \ | |
8947 | X(_adds, 1c00, eb100000), \ | |
8948 | X(_addi, 0000, f1000000), \ | |
8949 | X(_addis, 0000, f1100000), \ | |
8950 | X(_add_pc,000f, f20f0000), \ | |
8951 | X(_add_sp,000d, f10d0000), \ | |
8952 | X(_adr, 000f, f20f0000), \ | |
8953 | X(_and, 4000, ea000000), \ | |
8954 | X(_ands, 4000, ea100000), \ | |
8955 | X(_asr, 1000, fa40f000), \ | |
8956 | X(_asrs, 1000, fa50f000), \ | |
8957 | X(_b, e000, f000b000), \ | |
8958 | X(_bcond, d000, f0008000), \ | |
8959 | X(_bic, 4380, ea200000), \ | |
8960 | X(_bics, 4380, ea300000), \ | |
8961 | X(_cmn, 42c0, eb100f00), \ | |
8962 | X(_cmp, 2800, ebb00f00), \ | |
8963 | X(_cpsie, b660, f3af8400), \ | |
8964 | X(_cpsid, b670, f3af8600), \ | |
8965 | X(_cpy, 4600, ea4f0000), \ | |
8966 | X(_dec_sp,80dd, f1ad0d00), \ | |
8967 | X(_eor, 4040, ea800000), \ | |
8968 | X(_eors, 4040, ea900000), \ | |
8969 | X(_inc_sp,00dd, f10d0d00), \ | |
8970 | X(_ldmia, c800, e8900000), \ | |
8971 | X(_ldr, 6800, f8500000), \ | |
8972 | X(_ldrb, 7800, f8100000), \ | |
8973 | X(_ldrh, 8800, f8300000), \ | |
8974 | X(_ldrsb, 5600, f9100000), \ | |
8975 | X(_ldrsh, 5e00, f9300000), \ | |
8976 | X(_ldr_pc,4800, f85f0000), \ | |
8977 | X(_ldr_pc2,4800, f85f0000), \ | |
8978 | X(_ldr_sp,9800, f85d0000), \ | |
8979 | X(_lsl, 0000, fa00f000), \ | |
8980 | X(_lsls, 0000, fa10f000), \ | |
8981 | X(_lsr, 0800, fa20f000), \ | |
8982 | X(_lsrs, 0800, fa30f000), \ | |
8983 | X(_mov, 2000, ea4f0000), \ | |
8984 | X(_movs, 2000, ea5f0000), \ | |
8985 | X(_mul, 4340, fb00f000), \ | |
8986 | X(_muls, 4340, ffffffff), /* no 32b muls */ \ | |
8987 | X(_mvn, 43c0, ea6f0000), \ | |
8988 | X(_mvns, 43c0, ea7f0000), \ | |
8989 | X(_neg, 4240, f1c00000), /* rsb #0 */ \ | |
8990 | X(_negs, 4240, f1d00000), /* rsbs #0 */ \ | |
8991 | X(_orr, 4300, ea400000), \ | |
8992 | X(_orrs, 4300, ea500000), \ | |
8993 | X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \ | |
8994 | X(_push, b400, e92d0000), /* stmdb sp!,... */ \ | |
8995 | X(_rev, ba00, fa90f080), \ | |
8996 | X(_rev16, ba40, fa90f090), \ | |
8997 | X(_revsh, bac0, fa90f0b0), \ | |
8998 | X(_ror, 41c0, fa60f000), \ | |
8999 | X(_rors, 41c0, fa70f000), \ | |
9000 | X(_sbc, 4180, eb600000), \ | |
9001 | X(_sbcs, 4180, eb700000), \ | |
9002 | X(_stmia, c000, e8800000), \ | |
9003 | X(_str, 6000, f8400000), \ | |
9004 | X(_strb, 7000, f8000000), \ | |
9005 | X(_strh, 8000, f8200000), \ | |
9006 | X(_str_sp,9000, f84d0000), \ | |
9007 | X(_sub, 1e00, eba00000), \ | |
9008 | X(_subs, 1e00, ebb00000), \ | |
9009 | X(_subi, 8000, f1a00000), \ | |
9010 | X(_subis, 8000, f1b00000), \ | |
9011 | X(_sxtb, b240, fa4ff080), \ | |
9012 | X(_sxth, b200, fa0ff080), \ | |
9013 | X(_tst, 4200, ea100f00), \ | |
9014 | X(_uxtb, b2c0, fa5ff080), \ | |
9015 | X(_uxth, b280, fa1ff080), \ | |
9016 | X(_nop, bf00, f3af8000), \ | |
9017 | X(_yield, bf10, f3af8001), \ | |
9018 | X(_wfe, bf20, f3af8002), \ | |
9019 | X(_wfi, bf30, f3af8003), \ | |
9020 | X(_sev, bf40, f3af8004), | |
c19d1205 ZW |
9021 | |
9022 | /* To catch errors in encoding functions, the codes are all offset by | |
9023 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
9024 | as 16-bit instructions. */ | |
21d799b5 | 9025 | #define X(a,b,c) T_MNEM##a |
c19d1205 ZW |
9026 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; |
9027 | #undef X | |
9028 | ||
9029 | #define X(a,b,c) 0x##b | |
9030 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
9031 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
9032 | #undef X | |
9033 | ||
9034 | #define X(a,b,c) 0x##c | |
9035 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
c921be7d NC |
9036 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) |
9037 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
c19d1205 ZW |
9038 | #undef X |
9039 | #undef T16_32_TAB | |
9040 | ||
9041 | /* Thumb instruction encoders, in alphabetical order. */ | |
9042 | ||
92e90b6e | 9043 | /* ADDW or SUBW. */ |
c921be7d | 9044 | |
92e90b6e PB |
9045 | static void |
9046 | do_t_add_sub_w (void) | |
9047 | { | |
9048 | int Rd, Rn; | |
9049 | ||
9050 | Rd = inst.operands[0].reg; | |
9051 | Rn = inst.operands[1].reg; | |
9052 | ||
539d4391 NC |
9053 | /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this |
9054 | is the SP-{plus,minus}-immediate form of the instruction. */ | |
9055 | if (Rn == REG_SP) | |
9056 | constraint (Rd == REG_PC, BAD_PC); | |
9057 | else | |
9058 | reject_bad_reg (Rd); | |
fdfde340 | 9059 | |
92e90b6e PB |
9060 | inst.instruction |= (Rn << 16) | (Rd << 8); |
9061 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
9062 | } | |
9063 | ||
c19d1205 ZW |
9064 | /* Parse an add or subtract instruction. We get here with inst.instruction |
9065 | equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ | |
9066 | ||
9067 | static void | |
9068 | do_t_add_sub (void) | |
9069 | { | |
9070 | int Rd, Rs, Rn; | |
9071 | ||
9072 | Rd = inst.operands[0].reg; | |
9073 | Rs = (inst.operands[1].present | |
9074 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9075 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9076 | ||
e07e6e58 NC |
9077 | if (Rd == REG_PC) |
9078 | set_it_insn_type_last (); | |
9079 | ||
c19d1205 ZW |
9080 | if (unified_syntax) |
9081 | { | |
0110f2b8 PB |
9082 | bfd_boolean flags; |
9083 | bfd_boolean narrow; | |
9084 | int opcode; | |
9085 | ||
9086 | flags = (inst.instruction == T_MNEM_adds | |
9087 | || inst.instruction == T_MNEM_subs); | |
9088 | if (flags) | |
e07e6e58 | 9089 | narrow = !in_it_block (); |
0110f2b8 | 9090 | else |
e07e6e58 | 9091 | narrow = in_it_block (); |
c19d1205 | 9092 | if (!inst.operands[2].isreg) |
b99bd4ef | 9093 | { |
16805f35 PB |
9094 | int add; |
9095 | ||
fdfde340 JM |
9096 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); |
9097 | ||
16805f35 PB |
9098 | add = (inst.instruction == T_MNEM_add |
9099 | || inst.instruction == T_MNEM_adds); | |
0110f2b8 PB |
9100 | opcode = 0; |
9101 | if (inst.size_req != 4) | |
9102 | { | |
0110f2b8 PB |
9103 | /* Attempt to use a narrow opcode, with relaxation if |
9104 | appropriate. */ | |
9105 | if (Rd == REG_SP && Rs == REG_SP && !flags) | |
9106 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
9107 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
9108 | opcode = T_MNEM_add_sp; | |
9109 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
9110 | opcode = T_MNEM_add_pc; | |
9111 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
9112 | { | |
9113 | if (flags) | |
9114 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
9115 | else | |
9116 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
9117 | } | |
9118 | if (opcode) | |
9119 | { | |
9120 | inst.instruction = THUMB_OP16(opcode); | |
9121 | inst.instruction |= (Rd << 4) | Rs; | |
9122 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
9123 | if (inst.size_req != 2) | |
9124 | inst.relax = opcode; | |
9125 | } | |
9126 | else | |
9127 | constraint (inst.size_req == 2, BAD_HIREG); | |
9128 | } | |
9129 | if (inst.size_req == 4 | |
9130 | || (inst.size_req != 2 && !opcode)) | |
9131 | { | |
efd81785 PB |
9132 | if (Rd == REG_PC) |
9133 | { | |
fdfde340 | 9134 | constraint (add, BAD_PC); |
efd81785 PB |
9135 | constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, |
9136 | _("only SUBS PC, LR, #const allowed")); | |
9137 | constraint (inst.reloc.exp.X_op != O_constant, | |
9138 | _("expression too complex")); | |
9139 | constraint (inst.reloc.exp.X_add_number < 0 | |
9140 | || inst.reloc.exp.X_add_number > 0xff, | |
9141 | _("immediate value out of range")); | |
9142 | inst.instruction = T2_SUBS_PC_LR | |
9143 | | inst.reloc.exp.X_add_number; | |
9144 | inst.reloc.type = BFD_RELOC_UNUSED; | |
9145 | return; | |
9146 | } | |
9147 | else if (Rs == REG_PC) | |
16805f35 PB |
9148 | { |
9149 | /* Always use addw/subw. */ | |
9150 | inst.instruction = add ? 0xf20f0000 : 0xf2af0000; | |
9151 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
9152 | } | |
9153 | else | |
9154 | { | |
9155 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9156 | inst.instruction = (inst.instruction & 0xe1ffffff) | |
9157 | | 0x10000000; | |
9158 | if (flags) | |
9159 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9160 | else | |
9161 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; | |
9162 | } | |
dc4503c6 PB |
9163 | inst.instruction |= Rd << 8; |
9164 | inst.instruction |= Rs << 16; | |
0110f2b8 | 9165 | } |
b99bd4ef | 9166 | } |
c19d1205 ZW |
9167 | else |
9168 | { | |
9169 | Rn = inst.operands[2].reg; | |
9170 | /* See if we can do this with a 16-bit instruction. */ | |
9171 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
9172 | { | |
e27ec89e PB |
9173 | if (Rd > 7 || Rs > 7 || Rn > 7) |
9174 | narrow = FALSE; | |
9175 | ||
9176 | if (narrow) | |
c19d1205 | 9177 | { |
e27ec89e PB |
9178 | inst.instruction = ((inst.instruction == T_MNEM_adds |
9179 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
9180 | ? T_OPCODE_ADD_R3 |
9181 | : T_OPCODE_SUB_R3); | |
9182 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
9183 | return; | |
9184 | } | |
b99bd4ef | 9185 | |
7e806470 | 9186 | if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) |
c19d1205 | 9187 | { |
7e806470 PB |
9188 | /* Thumb-1 cores (except v6-M) require at least one high |
9189 | register in a narrow non flag setting add. */ | |
9190 | if (Rd > 7 || Rn > 7 | |
9191 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2) | |
9192 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr)) | |
c19d1205 | 9193 | { |
7e806470 PB |
9194 | if (Rd == Rn) |
9195 | { | |
9196 | Rn = Rs; | |
9197 | Rs = Rd; | |
9198 | } | |
c19d1205 ZW |
9199 | inst.instruction = T_OPCODE_ADD_HI; |
9200 | inst.instruction |= (Rd & 8) << 4; | |
9201 | inst.instruction |= (Rd & 7); | |
9202 | inst.instruction |= Rn << 3; | |
9203 | return; | |
9204 | } | |
c19d1205 ZW |
9205 | } |
9206 | } | |
c921be7d | 9207 | |
fdfde340 JM |
9208 | constraint (Rd == REG_PC, BAD_PC); |
9209 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); | |
9210 | constraint (Rs == REG_PC, BAD_PC); | |
9211 | reject_bad_reg (Rn); | |
9212 | ||
c19d1205 ZW |
9213 | /* If we get here, it can't be done in 16 bits. */ |
9214 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
9215 | _("shift must be constant")); | |
9216 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9217 | inst.instruction |= Rd << 8; | |
9218 | inst.instruction |= Rs << 16; | |
9219 | encode_thumb32_shifted_operand (2); | |
9220 | } | |
9221 | } | |
9222 | else | |
9223 | { | |
9224 | constraint (inst.instruction == T_MNEM_adds | |
9225 | || inst.instruction == T_MNEM_subs, | |
9226 | BAD_THUMB32); | |
b99bd4ef | 9227 | |
c19d1205 | 9228 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 9229 | { |
c19d1205 ZW |
9230 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
9231 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
9232 | BAD_HIREG); | |
9233 | ||
9234 | inst.instruction = (inst.instruction == T_MNEM_add | |
9235 | ? 0x0000 : 0x8000); | |
9236 | inst.instruction |= (Rd << 4) | Rs; | |
9237 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
b99bd4ef NC |
9238 | return; |
9239 | } | |
9240 | ||
c19d1205 ZW |
9241 | Rn = inst.operands[2].reg; |
9242 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 9243 | |
c19d1205 ZW |
9244 | /* We now have Rd, Rs, and Rn set to registers. */ |
9245 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 9246 | { |
c19d1205 ZW |
9247 | /* Can't do this for SUB. */ |
9248 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
9249 | inst.instruction = T_OPCODE_ADD_HI; | |
9250 | inst.instruction |= (Rd & 8) << 4; | |
9251 | inst.instruction |= (Rd & 7); | |
9252 | if (Rs == Rd) | |
9253 | inst.instruction |= Rn << 3; | |
9254 | else if (Rn == Rd) | |
9255 | inst.instruction |= Rs << 3; | |
9256 | else | |
9257 | constraint (1, _("dest must overlap one source register")); | |
9258 | } | |
9259 | else | |
9260 | { | |
9261 | inst.instruction = (inst.instruction == T_MNEM_add | |
9262 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
9263 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 9264 | } |
b99bd4ef | 9265 | } |
b99bd4ef NC |
9266 | } |
9267 | ||
c19d1205 ZW |
9268 | static void |
9269 | do_t_adr (void) | |
9270 | { | |
fdfde340 JM |
9271 | unsigned Rd; |
9272 | ||
9273 | Rd = inst.operands[0].reg; | |
9274 | reject_bad_reg (Rd); | |
9275 | ||
9276 | if (unified_syntax && inst.size_req == 0 && Rd <= 7) | |
0110f2b8 PB |
9277 | { |
9278 | /* Defer to section relaxation. */ | |
9279 | inst.relax = inst.instruction; | |
9280 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 | 9281 | inst.instruction |= Rd << 4; |
0110f2b8 PB |
9282 | } |
9283 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 9284 | { |
0110f2b8 | 9285 | /* Generate a 32-bit opcode. */ |
e9f89963 | 9286 | inst.instruction = THUMB_OP32 (inst.instruction); |
fdfde340 | 9287 | inst.instruction |= Rd << 8; |
e9f89963 PB |
9288 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; |
9289 | inst.reloc.pc_rel = 1; | |
9290 | } | |
9291 | else | |
9292 | { | |
0110f2b8 | 9293 | /* Generate a 16-bit opcode. */ |
e9f89963 PB |
9294 | inst.instruction = THUMB_OP16 (inst.instruction); |
9295 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
9296 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
9297 | inst.reloc.pc_rel = 1; | |
b99bd4ef | 9298 | |
fdfde340 | 9299 | inst.instruction |= Rd << 4; |
e9f89963 | 9300 | } |
c19d1205 | 9301 | } |
b99bd4ef | 9302 | |
c19d1205 ZW |
9303 | /* Arithmetic instructions for which there is just one 16-bit |
9304 | instruction encoding, and it allows only two low registers. | |
9305 | For maximal compatibility with ARM syntax, we allow three register | |
9306 | operands even when Thumb-32 instructions are not available, as long | |
9307 | as the first two are identical. For instance, both "sbc r0,r1" and | |
9308 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 9309 | static void |
c19d1205 | 9310 | do_t_arit3 (void) |
b99bd4ef | 9311 | { |
c19d1205 | 9312 | int Rd, Rs, Rn; |
b99bd4ef | 9313 | |
c19d1205 ZW |
9314 | Rd = inst.operands[0].reg; |
9315 | Rs = (inst.operands[1].present | |
9316 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9317 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9318 | Rn = inst.operands[2].reg; | |
b99bd4ef | 9319 | |
fdfde340 JM |
9320 | reject_bad_reg (Rd); |
9321 | reject_bad_reg (Rs); | |
9322 | if (inst.operands[2].isreg) | |
9323 | reject_bad_reg (Rn); | |
9324 | ||
c19d1205 | 9325 | if (unified_syntax) |
b99bd4ef | 9326 | { |
c19d1205 ZW |
9327 | if (!inst.operands[2].isreg) |
9328 | { | |
9329 | /* For an immediate, we always generate a 32-bit opcode; | |
9330 | section relaxation will shrink it later if possible. */ | |
9331 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9332 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
9333 | inst.instruction |= Rd << 8; | |
9334 | inst.instruction |= Rs << 16; | |
9335 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9336 | } | |
9337 | else | |
9338 | { | |
e27ec89e PB |
9339 | bfd_boolean narrow; |
9340 | ||
c19d1205 | 9341 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 9342 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 9343 | narrow = !in_it_block (); |
e27ec89e | 9344 | else |
e07e6e58 | 9345 | narrow = in_it_block (); |
e27ec89e PB |
9346 | |
9347 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
9348 | narrow = FALSE; | |
9349 | if (inst.operands[2].shifted) | |
9350 | narrow = FALSE; | |
9351 | if (inst.size_req == 4) | |
9352 | narrow = FALSE; | |
9353 | ||
9354 | if (narrow | |
c19d1205 ZW |
9355 | && Rd == Rs) |
9356 | { | |
9357 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9358 | inst.instruction |= Rd; | |
9359 | inst.instruction |= Rn << 3; | |
9360 | return; | |
9361 | } | |
b99bd4ef | 9362 | |
c19d1205 ZW |
9363 | /* If we get here, it can't be done in 16 bits. */ |
9364 | constraint (inst.operands[2].shifted | |
9365 | && inst.operands[2].immisreg, | |
9366 | _("shift must be constant")); | |
9367 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9368 | inst.instruction |= Rd << 8; | |
9369 | inst.instruction |= Rs << 16; | |
9370 | encode_thumb32_shifted_operand (2); | |
9371 | } | |
a737bd4d | 9372 | } |
c19d1205 | 9373 | else |
b99bd4ef | 9374 | { |
c19d1205 ZW |
9375 | /* On its face this is a lie - the instruction does set the |
9376 | flags. However, the only supported mnemonic in this mode | |
9377 | says it doesn't. */ | |
9378 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 9379 | |
c19d1205 ZW |
9380 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
9381 | _("unshifted register required")); | |
9382 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
9383 | constraint (Rd != Rs, | |
9384 | _("dest and source1 must be the same register")); | |
a737bd4d | 9385 | |
c19d1205 ZW |
9386 | inst.instruction = THUMB_OP16 (inst.instruction); |
9387 | inst.instruction |= Rd; | |
9388 | inst.instruction |= Rn << 3; | |
b99bd4ef | 9389 | } |
a737bd4d | 9390 | } |
b99bd4ef | 9391 | |
c19d1205 ZW |
9392 | /* Similarly, but for instructions where the arithmetic operation is |
9393 | commutative, so we can allow either of them to be different from | |
9394 | the destination operand in a 16-bit instruction. For instance, all | |
9395 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
9396 | accepted. */ | |
9397 | static void | |
9398 | do_t_arit3c (void) | |
a737bd4d | 9399 | { |
c19d1205 | 9400 | int Rd, Rs, Rn; |
b99bd4ef | 9401 | |
c19d1205 ZW |
9402 | Rd = inst.operands[0].reg; |
9403 | Rs = (inst.operands[1].present | |
9404 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9405 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9406 | Rn = inst.operands[2].reg; | |
c921be7d | 9407 | |
fdfde340 JM |
9408 | reject_bad_reg (Rd); |
9409 | reject_bad_reg (Rs); | |
9410 | if (inst.operands[2].isreg) | |
9411 | reject_bad_reg (Rn); | |
a737bd4d | 9412 | |
c19d1205 | 9413 | if (unified_syntax) |
a737bd4d | 9414 | { |
c19d1205 | 9415 | if (!inst.operands[2].isreg) |
b99bd4ef | 9416 | { |
c19d1205 ZW |
9417 | /* For an immediate, we always generate a 32-bit opcode; |
9418 | section relaxation will shrink it later if possible. */ | |
9419 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9420 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
9421 | inst.instruction |= Rd << 8; | |
9422 | inst.instruction |= Rs << 16; | |
9423 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 9424 | } |
c19d1205 | 9425 | else |
a737bd4d | 9426 | { |
e27ec89e PB |
9427 | bfd_boolean narrow; |
9428 | ||
c19d1205 | 9429 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 9430 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 9431 | narrow = !in_it_block (); |
e27ec89e | 9432 | else |
e07e6e58 | 9433 | narrow = in_it_block (); |
e27ec89e PB |
9434 | |
9435 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
9436 | narrow = FALSE; | |
9437 | if (inst.operands[2].shifted) | |
9438 | narrow = FALSE; | |
9439 | if (inst.size_req == 4) | |
9440 | narrow = FALSE; | |
9441 | ||
9442 | if (narrow) | |
a737bd4d | 9443 | { |
c19d1205 | 9444 | if (Rd == Rs) |
a737bd4d | 9445 | { |
c19d1205 ZW |
9446 | inst.instruction = THUMB_OP16 (inst.instruction); |
9447 | inst.instruction |= Rd; | |
9448 | inst.instruction |= Rn << 3; | |
9449 | return; | |
a737bd4d | 9450 | } |
c19d1205 | 9451 | if (Rd == Rn) |
a737bd4d | 9452 | { |
c19d1205 ZW |
9453 | inst.instruction = THUMB_OP16 (inst.instruction); |
9454 | inst.instruction |= Rd; | |
9455 | inst.instruction |= Rs << 3; | |
9456 | return; | |
a737bd4d NC |
9457 | } |
9458 | } | |
c19d1205 ZW |
9459 | |
9460 | /* If we get here, it can't be done in 16 bits. */ | |
9461 | constraint (inst.operands[2].shifted | |
9462 | && inst.operands[2].immisreg, | |
9463 | _("shift must be constant")); | |
9464 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9465 | inst.instruction |= Rd << 8; | |
9466 | inst.instruction |= Rs << 16; | |
9467 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 9468 | } |
b99bd4ef | 9469 | } |
c19d1205 ZW |
9470 | else |
9471 | { | |
9472 | /* On its face this is a lie - the instruction does set the | |
9473 | flags. However, the only supported mnemonic in this mode | |
9474 | says it doesn't. */ | |
9475 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 9476 | |
c19d1205 ZW |
9477 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
9478 | _("unshifted register required")); | |
9479 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
9480 | ||
9481 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9482 | inst.instruction |= Rd; | |
9483 | ||
9484 | if (Rd == Rs) | |
9485 | inst.instruction |= Rn << 3; | |
9486 | else if (Rd == Rn) | |
9487 | inst.instruction |= Rs << 3; | |
9488 | else | |
9489 | constraint (1, _("dest must overlap one source register")); | |
9490 | } | |
a737bd4d NC |
9491 | } |
9492 | ||
62b3e311 PB |
9493 | static void |
9494 | do_t_barrier (void) | |
9495 | { | |
9496 | if (inst.operands[0].present) | |
9497 | { | |
9498 | constraint ((inst.instruction & 0xf0) != 0x40 | |
52e7f43d RE |
9499 | && inst.operands[0].imm > 0xf |
9500 | && inst.operands[0].imm < 0x0, | |
bd3ba5d1 | 9501 | _("bad barrier type")); |
62b3e311 PB |
9502 | inst.instruction |= inst.operands[0].imm; |
9503 | } | |
9504 | else | |
9505 | inst.instruction |= 0xf; | |
9506 | } | |
9507 | ||
c19d1205 ZW |
9508 | static void |
9509 | do_t_bfc (void) | |
a737bd4d | 9510 | { |
fdfde340 | 9511 | unsigned Rd; |
c19d1205 ZW |
9512 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
9513 | constraint (msb > 32, _("bit-field extends past end of register")); | |
9514 | /* The instruction encoding stores the LSB and MSB, | |
9515 | not the LSB and width. */ | |
fdfde340 JM |
9516 | Rd = inst.operands[0].reg; |
9517 | reject_bad_reg (Rd); | |
9518 | inst.instruction |= Rd << 8; | |
c19d1205 ZW |
9519 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; |
9520 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
9521 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
9522 | } |
9523 | ||
c19d1205 ZW |
9524 | static void |
9525 | do_t_bfi (void) | |
b99bd4ef | 9526 | { |
fdfde340 | 9527 | int Rd, Rn; |
c19d1205 | 9528 | unsigned int msb; |
b99bd4ef | 9529 | |
fdfde340 JM |
9530 | Rd = inst.operands[0].reg; |
9531 | reject_bad_reg (Rd); | |
9532 | ||
c19d1205 ZW |
9533 | /* #0 in second position is alternative syntax for bfc, which is |
9534 | the same instruction but with REG_PC in the Rm field. */ | |
9535 | if (!inst.operands[1].isreg) | |
fdfde340 JM |
9536 | Rn = REG_PC; |
9537 | else | |
9538 | { | |
9539 | Rn = inst.operands[1].reg; | |
9540 | reject_bad_reg (Rn); | |
9541 | } | |
b99bd4ef | 9542 | |
c19d1205 ZW |
9543 | msb = inst.operands[2].imm + inst.operands[3].imm; |
9544 | constraint (msb > 32, _("bit-field extends past end of register")); | |
9545 | /* The instruction encoding stores the LSB and MSB, | |
9546 | not the LSB and width. */ | |
fdfde340 JM |
9547 | inst.instruction |= Rd << 8; |
9548 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
9549 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
9550 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
9551 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
9552 | } |
9553 | ||
c19d1205 ZW |
9554 | static void |
9555 | do_t_bfx (void) | |
b99bd4ef | 9556 | { |
fdfde340 JM |
9557 | unsigned Rd, Rn; |
9558 | ||
9559 | Rd = inst.operands[0].reg; | |
9560 | Rn = inst.operands[1].reg; | |
9561 | ||
9562 | reject_bad_reg (Rd); | |
9563 | reject_bad_reg (Rn); | |
9564 | ||
c19d1205 ZW |
9565 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
9566 | _("bit-field extends past end of register")); | |
fdfde340 JM |
9567 | inst.instruction |= Rd << 8; |
9568 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
9569 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
9570 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
9571 | inst.instruction |= inst.operands[3].imm - 1; | |
9572 | } | |
b99bd4ef | 9573 | |
c19d1205 ZW |
9574 | /* ARM V5 Thumb BLX (argument parse) |
9575 | BLX <target_addr> which is BLX(1) | |
9576 | BLX <Rm> which is BLX(2) | |
9577 | Unfortunately, there are two different opcodes for this mnemonic. | |
9578 | So, the insns[].value is not used, and the code here zaps values | |
9579 | into inst.instruction. | |
b99bd4ef | 9580 | |
c19d1205 ZW |
9581 | ??? How to take advantage of the additional two bits of displacement |
9582 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 9583 | |
c19d1205 ZW |
9584 | static void |
9585 | do_t_blx (void) | |
9586 | { | |
e07e6e58 NC |
9587 | set_it_insn_type_last (); |
9588 | ||
c19d1205 | 9589 | if (inst.operands[0].isreg) |
fdfde340 JM |
9590 | { |
9591 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); | |
9592 | /* We have a register, so this is BLX(2). */ | |
9593 | inst.instruction |= inst.operands[0].reg << 3; | |
9594 | } | |
b99bd4ef NC |
9595 | else |
9596 | { | |
c19d1205 | 9597 | /* No register. This must be BLX(1). */ |
2fc8bdac | 9598 | inst.instruction = 0xf000e800; |
00adf2d4 | 9599 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; |
c19d1205 | 9600 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
9601 | } |
9602 | } | |
9603 | ||
c19d1205 ZW |
9604 | static void |
9605 | do_t_branch (void) | |
b99bd4ef | 9606 | { |
0110f2b8 | 9607 | int opcode; |
dfa9f0d5 PB |
9608 | int cond; |
9609 | ||
e07e6e58 NC |
9610 | cond = inst.cond; |
9611 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); | |
9612 | ||
9613 | if (in_it_block ()) | |
dfa9f0d5 PB |
9614 | { |
9615 | /* Conditional branches inside IT blocks are encoded as unconditional | |
9616 | branches. */ | |
9617 | cond = COND_ALWAYS; | |
dfa9f0d5 PB |
9618 | } |
9619 | else | |
9620 | cond = inst.cond; | |
9621 | ||
9622 | if (cond != COND_ALWAYS) | |
0110f2b8 PB |
9623 | opcode = T_MNEM_bcond; |
9624 | else | |
9625 | opcode = inst.instruction; | |
9626 | ||
9627 | if (unified_syntax && inst.size_req == 4) | |
c19d1205 | 9628 | { |
0110f2b8 | 9629 | inst.instruction = THUMB_OP32(opcode); |
dfa9f0d5 | 9630 | if (cond == COND_ALWAYS) |
0110f2b8 | 9631 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
9632 | else |
9633 | { | |
9c2799c2 | 9634 | gas_assert (cond != 0xF); |
dfa9f0d5 | 9635 | inst.instruction |= cond << 22; |
c19d1205 ZW |
9636 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20; |
9637 | } | |
9638 | } | |
b99bd4ef NC |
9639 | else |
9640 | { | |
0110f2b8 | 9641 | inst.instruction = THUMB_OP16(opcode); |
dfa9f0d5 | 9642 | if (cond == COND_ALWAYS) |
c19d1205 ZW |
9643 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12; |
9644 | else | |
b99bd4ef | 9645 | { |
dfa9f0d5 | 9646 | inst.instruction |= cond << 8; |
c19d1205 | 9647 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 9648 | } |
0110f2b8 PB |
9649 | /* Allow section relaxation. */ |
9650 | if (unified_syntax && inst.size_req != 2) | |
9651 | inst.relax = opcode; | |
b99bd4ef | 9652 | } |
c19d1205 ZW |
9653 | |
9654 | inst.reloc.pc_rel = 1; | |
b99bd4ef NC |
9655 | } |
9656 | ||
9657 | static void | |
c19d1205 | 9658 | do_t_bkpt (void) |
b99bd4ef | 9659 | { |
dfa9f0d5 PB |
9660 | constraint (inst.cond != COND_ALWAYS, |
9661 | _("instruction is always unconditional")); | |
c19d1205 | 9662 | if (inst.operands[0].present) |
b99bd4ef | 9663 | { |
c19d1205 ZW |
9664 | constraint (inst.operands[0].imm > 255, |
9665 | _("immediate value out of range")); | |
9666 | inst.instruction |= inst.operands[0].imm; | |
e07e6e58 | 9667 | set_it_insn_type (NEUTRAL_IT_INSN); |
b99bd4ef | 9668 | } |
b99bd4ef NC |
9669 | } |
9670 | ||
9671 | static void | |
c19d1205 | 9672 | do_t_branch23 (void) |
b99bd4ef | 9673 | { |
e07e6e58 | 9674 | set_it_insn_type_last (); |
c19d1205 | 9675 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; |
90e4755a RE |
9676 | inst.reloc.pc_rel = 1; |
9677 | ||
4343666d | 9678 | #if defined(OBJ_COFF) |
c19d1205 ZW |
9679 | /* If the destination of the branch is a defined symbol which does not have |
9680 | the THUMB_FUNC attribute, then we must be calling a function which has | |
9681 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
9682 | function and change the branch to refer to that function instead. */ | |
9683 | if ( inst.reloc.exp.X_op == O_symbol | |
9684 | && inst.reloc.exp.X_add_symbol != NULL | |
9685 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
9686 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
9687 | inst.reloc.exp.X_add_symbol = | |
9688 | find_real_start (inst.reloc.exp.X_add_symbol); | |
4343666d | 9689 | #endif |
90e4755a RE |
9690 | } |
9691 | ||
9692 | static void | |
c19d1205 | 9693 | do_t_bx (void) |
90e4755a | 9694 | { |
e07e6e58 | 9695 | set_it_insn_type_last (); |
c19d1205 ZW |
9696 | inst.instruction |= inst.operands[0].reg << 3; |
9697 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
9698 | should cause the alignment to be checked once it is known. This is | |
9699 | because BX PC only works if the instruction is word aligned. */ | |
9700 | } | |
90e4755a | 9701 | |
c19d1205 ZW |
9702 | static void |
9703 | do_t_bxj (void) | |
9704 | { | |
fdfde340 | 9705 | int Rm; |
90e4755a | 9706 | |
e07e6e58 | 9707 | set_it_insn_type_last (); |
fdfde340 JM |
9708 | Rm = inst.operands[0].reg; |
9709 | reject_bad_reg (Rm); | |
9710 | inst.instruction |= Rm << 16; | |
90e4755a RE |
9711 | } |
9712 | ||
9713 | static void | |
c19d1205 | 9714 | do_t_clz (void) |
90e4755a | 9715 | { |
fdfde340 JM |
9716 | unsigned Rd; |
9717 | unsigned Rm; | |
9718 | ||
9719 | Rd = inst.operands[0].reg; | |
9720 | Rm = inst.operands[1].reg; | |
9721 | ||
9722 | reject_bad_reg (Rd); | |
9723 | reject_bad_reg (Rm); | |
9724 | ||
9725 | inst.instruction |= Rd << 8; | |
9726 | inst.instruction |= Rm << 16; | |
9727 | inst.instruction |= Rm; | |
c19d1205 | 9728 | } |
90e4755a | 9729 | |
dfa9f0d5 PB |
9730 | static void |
9731 | do_t_cps (void) | |
9732 | { | |
e07e6e58 | 9733 | set_it_insn_type (OUTSIDE_IT_INSN); |
dfa9f0d5 PB |
9734 | inst.instruction |= inst.operands[0].imm; |
9735 | } | |
9736 | ||
c19d1205 ZW |
9737 | static void |
9738 | do_t_cpsi (void) | |
9739 | { | |
e07e6e58 | 9740 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 | 9741 | if (unified_syntax |
62b3e311 PB |
9742 | && (inst.operands[1].present || inst.size_req == 4) |
9743 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) | |
90e4755a | 9744 | { |
c19d1205 ZW |
9745 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
9746 | inst.instruction = 0xf3af8000; | |
9747 | inst.instruction |= imod << 9; | |
9748 | inst.instruction |= inst.operands[0].imm << 5; | |
9749 | if (inst.operands[1].present) | |
9750 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 9751 | } |
c19d1205 | 9752 | else |
90e4755a | 9753 | { |
62b3e311 PB |
9754 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) |
9755 | && (inst.operands[0].imm & 4), | |
9756 | _("selected processor does not support 'A' form " | |
9757 | "of this instruction")); | |
9758 | constraint (inst.operands[1].present || inst.size_req == 4, | |
c19d1205 ZW |
9759 | _("Thumb does not support the 2-argument " |
9760 | "form of this instruction")); | |
9761 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 9762 | } |
90e4755a RE |
9763 | } |
9764 | ||
c19d1205 ZW |
9765 | /* THUMB CPY instruction (argument parse). */ |
9766 | ||
90e4755a | 9767 | static void |
c19d1205 | 9768 | do_t_cpy (void) |
90e4755a | 9769 | { |
c19d1205 | 9770 | if (inst.size_req == 4) |
90e4755a | 9771 | { |
c19d1205 ZW |
9772 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
9773 | inst.instruction |= inst.operands[0].reg << 8; | |
9774 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 9775 | } |
c19d1205 | 9776 | else |
90e4755a | 9777 | { |
c19d1205 ZW |
9778 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
9779 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
9780 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 9781 | } |
90e4755a RE |
9782 | } |
9783 | ||
90e4755a | 9784 | static void |
25fe350b | 9785 | do_t_cbz (void) |
90e4755a | 9786 | { |
e07e6e58 | 9787 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
9788 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
9789 | inst.instruction |= inst.operands[0].reg; | |
9790 | inst.reloc.pc_rel = 1; | |
9791 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
9792 | } | |
90e4755a | 9793 | |
62b3e311 PB |
9794 | static void |
9795 | do_t_dbg (void) | |
9796 | { | |
9797 | inst.instruction |= inst.operands[0].imm; | |
9798 | } | |
9799 | ||
9800 | static void | |
9801 | do_t_div (void) | |
9802 | { | |
fdfde340 JM |
9803 | unsigned Rd, Rn, Rm; |
9804 | ||
9805 | Rd = inst.operands[0].reg; | |
9806 | Rn = (inst.operands[1].present | |
9807 | ? inst.operands[1].reg : Rd); | |
9808 | Rm = inst.operands[2].reg; | |
9809 | ||
9810 | reject_bad_reg (Rd); | |
9811 | reject_bad_reg (Rn); | |
9812 | reject_bad_reg (Rm); | |
9813 | ||
9814 | inst.instruction |= Rd << 8; | |
9815 | inst.instruction |= Rn << 16; | |
9816 | inst.instruction |= Rm; | |
62b3e311 PB |
9817 | } |
9818 | ||
c19d1205 ZW |
9819 | static void |
9820 | do_t_hint (void) | |
9821 | { | |
9822 | if (unified_syntax && inst.size_req == 4) | |
9823 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9824 | else | |
9825 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9826 | } | |
90e4755a | 9827 | |
c19d1205 ZW |
9828 | static void |
9829 | do_t_it (void) | |
9830 | { | |
9831 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e | 9832 | |
e07e6e58 NC |
9833 | set_it_insn_type (IT_INSN); |
9834 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
9835 | now_it.cc = cond; | |
e27ec89e PB |
9836 | |
9837 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 9838 | if ((cond & 0x1) == 0x0) |
90e4755a | 9839 | { |
c19d1205 | 9840 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 9841 | |
c19d1205 ZW |
9842 | if ((mask & 0x7) == 0) |
9843 | /* no conversion needed */; | |
9844 | else if ((mask & 0x3) == 0) | |
e27ec89e PB |
9845 | mask ^= 0x8; |
9846 | else if ((mask & 0x1) == 0) | |
9847 | mask ^= 0xC; | |
c19d1205 | 9848 | else |
e27ec89e | 9849 | mask ^= 0xE; |
90e4755a | 9850 | |
e27ec89e PB |
9851 | inst.instruction &= 0xfff0; |
9852 | inst.instruction |= mask; | |
c19d1205 | 9853 | } |
90e4755a | 9854 | |
c19d1205 ZW |
9855 | inst.instruction |= cond << 4; |
9856 | } | |
90e4755a | 9857 | |
3c707909 PB |
9858 | /* Helper function used for both push/pop and ldm/stm. */ |
9859 | static void | |
9860 | encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) | |
9861 | { | |
9862 | bfd_boolean load; | |
9863 | ||
9864 | load = (inst.instruction & (1 << 20)) != 0; | |
9865 | ||
9866 | if (mask & (1 << 13)) | |
9867 | inst.error = _("SP not allowed in register list"); | |
1e5b0379 NC |
9868 | |
9869 | if ((mask & (1 << base)) != 0 | |
9870 | && writeback) | |
9871 | inst.error = _("having the base register in the register list when " | |
9872 | "using write back is UNPREDICTABLE"); | |
9873 | ||
3c707909 PB |
9874 | if (load) |
9875 | { | |
e07e6e58 NC |
9876 | if (mask & (1 << 15)) |
9877 | { | |
9878 | if (mask & (1 << 14)) | |
9879 | inst.error = _("LR and PC should not both be in register list"); | |
9880 | else | |
9881 | set_it_insn_type_last (); | |
9882 | } | |
3c707909 PB |
9883 | } |
9884 | else | |
9885 | { | |
9886 | if (mask & (1 << 15)) | |
9887 | inst.error = _("PC not allowed in register list"); | |
3c707909 PB |
9888 | } |
9889 | ||
9890 | if ((mask & (mask - 1)) == 0) | |
9891 | { | |
9892 | /* Single register transfers implemented as str/ldr. */ | |
9893 | if (writeback) | |
9894 | { | |
9895 | if (inst.instruction & (1 << 23)) | |
9896 | inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ | |
9897 | else | |
9898 | inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ | |
9899 | } | |
9900 | else | |
9901 | { | |
9902 | if (inst.instruction & (1 << 23)) | |
9903 | inst.instruction = 0x00800000; /* ia -> [base] */ | |
9904 | else | |
9905 | inst.instruction = 0x00000c04; /* db -> [base, #-4] */ | |
9906 | } | |
9907 | ||
9908 | inst.instruction |= 0xf8400000; | |
9909 | if (load) | |
9910 | inst.instruction |= 0x00100000; | |
9911 | ||
5f4273c7 | 9912 | mask = ffs (mask) - 1; |
3c707909 PB |
9913 | mask <<= 12; |
9914 | } | |
9915 | else if (writeback) | |
9916 | inst.instruction |= WRITE_BACK; | |
9917 | ||
9918 | inst.instruction |= mask; | |
9919 | inst.instruction |= base << 16; | |
9920 | } | |
9921 | ||
c19d1205 ZW |
9922 | static void |
9923 | do_t_ldmstm (void) | |
9924 | { | |
9925 | /* This really doesn't seem worth it. */ | |
9926 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
9927 | _("expression too complex")); | |
9928 | constraint (inst.operands[1].writeback, | |
9929 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 9930 | |
c19d1205 ZW |
9931 | if (unified_syntax) |
9932 | { | |
3c707909 PB |
9933 | bfd_boolean narrow; |
9934 | unsigned mask; | |
9935 | ||
9936 | narrow = FALSE; | |
c19d1205 ZW |
9937 | /* See if we can use a 16-bit instruction. */ |
9938 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
9939 | && inst.size_req != 4 | |
3c707909 | 9940 | && !(inst.operands[1].imm & ~0xff)) |
90e4755a | 9941 | { |
3c707909 | 9942 | mask = 1 << inst.operands[0].reg; |
90e4755a | 9943 | |
3c707909 PB |
9944 | if (inst.operands[0].reg <= 7 |
9945 | && (inst.instruction == T_MNEM_stmia | |
9946 | ? inst.operands[0].writeback | |
9947 | : (inst.operands[0].writeback | |
9948 | == !(inst.operands[1].imm & mask)))) | |
90e4755a | 9949 | { |
3c707909 PB |
9950 | if (inst.instruction == T_MNEM_stmia |
9951 | && (inst.operands[1].imm & mask) | |
9952 | && (inst.operands[1].imm & (mask - 1))) | |
1e5b0379 | 9953 | as_warn (_("value stored for r%d is UNKNOWN"), |
c19d1205 | 9954 | inst.operands[0].reg); |
3c707909 PB |
9955 | |
9956 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9957 | inst.instruction |= inst.operands[0].reg << 8; | |
9958 | inst.instruction |= inst.operands[1].imm; | |
9959 | narrow = TRUE; | |
90e4755a | 9960 | } |
3c707909 PB |
9961 | else if (inst.operands[0] .reg == REG_SP |
9962 | && inst.operands[0].writeback) | |
90e4755a | 9963 | { |
3c707909 PB |
9964 | inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia |
9965 | ? T_MNEM_push : T_MNEM_pop); | |
9966 | inst.instruction |= inst.operands[1].imm; | |
9967 | narrow = TRUE; | |
90e4755a | 9968 | } |
3c707909 PB |
9969 | } |
9970 | ||
9971 | if (!narrow) | |
9972 | { | |
c19d1205 ZW |
9973 | if (inst.instruction < 0xffff) |
9974 | inst.instruction = THUMB_OP32 (inst.instruction); | |
3c707909 | 9975 | |
5f4273c7 NC |
9976 | encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm, |
9977 | inst.operands[0].writeback); | |
90e4755a RE |
9978 | } |
9979 | } | |
c19d1205 | 9980 | else |
90e4755a | 9981 | { |
c19d1205 ZW |
9982 | constraint (inst.operands[0].reg > 7 |
9983 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
1198ca51 PB |
9984 | constraint (inst.instruction != T_MNEM_ldmia |
9985 | && inst.instruction != T_MNEM_stmia, | |
9986 | _("Thumb-2 instruction only valid in unified syntax")); | |
c19d1205 | 9987 | if (inst.instruction == T_MNEM_stmia) |
f03698e6 | 9988 | { |
c19d1205 ZW |
9989 | if (!inst.operands[0].writeback) |
9990 | as_warn (_("this instruction will write back the base register")); | |
9991 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
9992 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
1e5b0379 | 9993 | as_warn (_("value stored for r%d is UNKNOWN"), |
c19d1205 | 9994 | inst.operands[0].reg); |
f03698e6 | 9995 | } |
c19d1205 | 9996 | else |
90e4755a | 9997 | { |
c19d1205 ZW |
9998 | if (!inst.operands[0].writeback |
9999 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
10000 | as_warn (_("this instruction will write back the base register")); | |
10001 | else if (inst.operands[0].writeback | |
10002 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
10003 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
10004 | } |
10005 | ||
c19d1205 ZW |
10006 | inst.instruction = THUMB_OP16 (inst.instruction); |
10007 | inst.instruction |= inst.operands[0].reg << 8; | |
10008 | inst.instruction |= inst.operands[1].imm; | |
10009 | } | |
10010 | } | |
e28cd48c | 10011 | |
c19d1205 ZW |
10012 | static void |
10013 | do_t_ldrex (void) | |
10014 | { | |
10015 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
10016 | || inst.operands[1].postind || inst.operands[1].writeback | |
10017 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
10018 | || inst.operands[1].negative, | |
01cfc07f | 10019 | BAD_ADDR_MODE); |
e28cd48c | 10020 | |
5be8be5d DG |
10021 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
10022 | ||
c19d1205 ZW |
10023 | inst.instruction |= inst.operands[0].reg << 12; |
10024 | inst.instruction |= inst.operands[1].reg << 16; | |
10025 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
10026 | } | |
e28cd48c | 10027 | |
c19d1205 ZW |
10028 | static void |
10029 | do_t_ldrexd (void) | |
10030 | { | |
10031 | if (!inst.operands[1].present) | |
1cac9012 | 10032 | { |
c19d1205 ZW |
10033 | constraint (inst.operands[0].reg == REG_LR, |
10034 | _("r14 not allowed as first register " | |
10035 | "when second register is omitted")); | |
10036 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 10037 | } |
c19d1205 ZW |
10038 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
10039 | BAD_OVERLAP); | |
b99bd4ef | 10040 | |
c19d1205 ZW |
10041 | inst.instruction |= inst.operands[0].reg << 12; |
10042 | inst.instruction |= inst.operands[1].reg << 8; | |
10043 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
10044 | } |
10045 | ||
10046 | static void | |
c19d1205 | 10047 | do_t_ldst (void) |
b99bd4ef | 10048 | { |
0110f2b8 PB |
10049 | unsigned long opcode; |
10050 | int Rn; | |
10051 | ||
e07e6e58 NC |
10052 | if (inst.operands[0].isreg |
10053 | && !inst.operands[0].preind | |
10054 | && inst.operands[0].reg == REG_PC) | |
10055 | set_it_insn_type_last (); | |
10056 | ||
0110f2b8 | 10057 | opcode = inst.instruction; |
c19d1205 | 10058 | if (unified_syntax) |
b99bd4ef | 10059 | { |
53365c0d PB |
10060 | if (!inst.operands[1].isreg) |
10061 | { | |
10062 | if (opcode <= 0xffff) | |
10063 | inst.instruction = THUMB_OP32 (opcode); | |
10064 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
10065 | return; | |
10066 | } | |
0110f2b8 PB |
10067 | if (inst.operands[1].isreg |
10068 | && !inst.operands[1].writeback | |
c19d1205 ZW |
10069 | && !inst.operands[1].shifted && !inst.operands[1].postind |
10070 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
10071 | && opcode <= 0xffff |
10072 | && inst.size_req != 4) | |
c19d1205 | 10073 | { |
0110f2b8 PB |
10074 | /* Insn may have a 16-bit form. */ |
10075 | Rn = inst.operands[1].reg; | |
10076 | if (inst.operands[1].immisreg) | |
10077 | { | |
10078 | inst.instruction = THUMB_OP16 (opcode); | |
5f4273c7 | 10079 | /* [Rn, Rik] */ |
0110f2b8 PB |
10080 | if (Rn <= 7 && inst.operands[1].imm <= 7) |
10081 | goto op16; | |
5be8be5d DG |
10082 | else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str) |
10083 | reject_bad_reg (inst.operands[1].imm); | |
0110f2b8 PB |
10084 | } |
10085 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
10086 | && opcode != T_MNEM_ldrsb) | |
10087 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
10088 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
10089 | { | |
10090 | /* [Rn, #const] */ | |
10091 | if (Rn > 7) | |
10092 | { | |
10093 | if (Rn == REG_PC) | |
10094 | { | |
10095 | if (inst.reloc.pc_rel) | |
10096 | opcode = T_MNEM_ldr_pc2; | |
10097 | else | |
10098 | opcode = T_MNEM_ldr_pc; | |
10099 | } | |
10100 | else | |
10101 | { | |
10102 | if (opcode == T_MNEM_ldr) | |
10103 | opcode = T_MNEM_ldr_sp; | |
10104 | else | |
10105 | opcode = T_MNEM_str_sp; | |
10106 | } | |
10107 | inst.instruction = inst.operands[0].reg << 8; | |
10108 | } | |
10109 | else | |
10110 | { | |
10111 | inst.instruction = inst.operands[0].reg; | |
10112 | inst.instruction |= inst.operands[1].reg << 3; | |
10113 | } | |
10114 | inst.instruction |= THUMB_OP16 (opcode); | |
10115 | if (inst.size_req == 2) | |
10116 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10117 | else | |
10118 | inst.relax = opcode; | |
10119 | return; | |
10120 | } | |
c19d1205 | 10121 | } |
0110f2b8 | 10122 | /* Definitely a 32-bit variant. */ |
5be8be5d DG |
10123 | |
10124 | /* Do some validations regarding addressing modes. */ | |
10125 | if (inst.operands[1].immisreg && opcode != T_MNEM_ldr | |
10126 | && opcode != T_MNEM_str) | |
10127 | reject_bad_reg (inst.operands[1].imm); | |
10128 | ||
0110f2b8 | 10129 | inst.instruction = THUMB_OP32 (opcode); |
c19d1205 ZW |
10130 | inst.instruction |= inst.operands[0].reg << 12; |
10131 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
b99bd4ef NC |
10132 | return; |
10133 | } | |
10134 | ||
c19d1205 ZW |
10135 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
10136 | ||
10137 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 10138 | { |
c19d1205 ZW |
10139 | /* Only [Rn,Rm] is acceptable. */ |
10140 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
10141 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
10142 | || inst.operands[1].postind || inst.operands[1].shifted | |
10143 | || inst.operands[1].negative, | |
10144 | _("Thumb does not support this addressing mode")); | |
10145 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10146 | goto op16; | |
b99bd4ef | 10147 | } |
5f4273c7 | 10148 | |
c19d1205 ZW |
10149 | inst.instruction = THUMB_OP16 (inst.instruction); |
10150 | if (!inst.operands[1].isreg) | |
10151 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
10152 | return; | |
b99bd4ef | 10153 | |
c19d1205 ZW |
10154 | constraint (!inst.operands[1].preind |
10155 | || inst.operands[1].shifted | |
10156 | || inst.operands[1].writeback, | |
10157 | _("Thumb does not support this addressing mode")); | |
10158 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 10159 | { |
c19d1205 ZW |
10160 | constraint (inst.instruction & 0x0600, |
10161 | _("byte or halfword not valid for base register")); | |
10162 | constraint (inst.operands[1].reg == REG_PC | |
10163 | && !(inst.instruction & THUMB_LOAD_BIT), | |
10164 | _("r15 based store not allowed")); | |
10165 | constraint (inst.operands[1].immisreg, | |
10166 | _("invalid base register for register offset")); | |
b99bd4ef | 10167 | |
c19d1205 ZW |
10168 | if (inst.operands[1].reg == REG_PC) |
10169 | inst.instruction = T_OPCODE_LDR_PC; | |
10170 | else if (inst.instruction & THUMB_LOAD_BIT) | |
10171 | inst.instruction = T_OPCODE_LDR_SP; | |
10172 | else | |
10173 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 10174 | |
c19d1205 ZW |
10175 | inst.instruction |= inst.operands[0].reg << 8; |
10176 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10177 | return; | |
10178 | } | |
90e4755a | 10179 | |
c19d1205 ZW |
10180 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
10181 | if (!inst.operands[1].immisreg) | |
10182 | { | |
10183 | /* Immediate offset. */ | |
10184 | inst.instruction |= inst.operands[0].reg; | |
10185 | inst.instruction |= inst.operands[1].reg << 3; | |
10186 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10187 | return; | |
10188 | } | |
90e4755a | 10189 | |
c19d1205 ZW |
10190 | /* Register offset. */ |
10191 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
10192 | constraint (inst.operands[1].negative, | |
10193 | _("Thumb does not support this addressing mode")); | |
90e4755a | 10194 | |
c19d1205 ZW |
10195 | op16: |
10196 | switch (inst.instruction) | |
10197 | { | |
10198 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
10199 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
10200 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
10201 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
10202 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
10203 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
10204 | case 0x5600 /* ldrsb */: | |
10205 | case 0x5e00 /* ldrsh */: break; | |
10206 | default: abort (); | |
10207 | } | |
90e4755a | 10208 | |
c19d1205 ZW |
10209 | inst.instruction |= inst.operands[0].reg; |
10210 | inst.instruction |= inst.operands[1].reg << 3; | |
10211 | inst.instruction |= inst.operands[1].imm << 6; | |
10212 | } | |
90e4755a | 10213 | |
c19d1205 ZW |
10214 | static void |
10215 | do_t_ldstd (void) | |
10216 | { | |
10217 | if (!inst.operands[1].present) | |
b99bd4ef | 10218 | { |
c19d1205 ZW |
10219 | inst.operands[1].reg = inst.operands[0].reg + 1; |
10220 | constraint (inst.operands[0].reg == REG_LR, | |
10221 | _("r14 not allowed here")); | |
b99bd4ef | 10222 | } |
c19d1205 ZW |
10223 | inst.instruction |= inst.operands[0].reg << 12; |
10224 | inst.instruction |= inst.operands[1].reg << 8; | |
10225 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
b99bd4ef NC |
10226 | } |
10227 | ||
c19d1205 ZW |
10228 | static void |
10229 | do_t_ldstt (void) | |
10230 | { | |
10231 | inst.instruction |= inst.operands[0].reg << 12; | |
10232 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
10233 | } | |
a737bd4d | 10234 | |
b99bd4ef | 10235 | static void |
c19d1205 | 10236 | do_t_mla (void) |
b99bd4ef | 10237 | { |
fdfde340 | 10238 | unsigned Rd, Rn, Rm, Ra; |
c921be7d | 10239 | |
fdfde340 JM |
10240 | Rd = inst.operands[0].reg; |
10241 | Rn = inst.operands[1].reg; | |
10242 | Rm = inst.operands[2].reg; | |
10243 | Ra = inst.operands[3].reg; | |
10244 | ||
10245 | reject_bad_reg (Rd); | |
10246 | reject_bad_reg (Rn); | |
10247 | reject_bad_reg (Rm); | |
10248 | reject_bad_reg (Ra); | |
10249 | ||
10250 | inst.instruction |= Rd << 8; | |
10251 | inst.instruction |= Rn << 16; | |
10252 | inst.instruction |= Rm; | |
10253 | inst.instruction |= Ra << 12; | |
c19d1205 | 10254 | } |
b99bd4ef | 10255 | |
c19d1205 ZW |
10256 | static void |
10257 | do_t_mlal (void) | |
10258 | { | |
fdfde340 JM |
10259 | unsigned RdLo, RdHi, Rn, Rm; |
10260 | ||
10261 | RdLo = inst.operands[0].reg; | |
10262 | RdHi = inst.operands[1].reg; | |
10263 | Rn = inst.operands[2].reg; | |
10264 | Rm = inst.operands[3].reg; | |
10265 | ||
10266 | reject_bad_reg (RdLo); | |
10267 | reject_bad_reg (RdHi); | |
10268 | reject_bad_reg (Rn); | |
10269 | reject_bad_reg (Rm); | |
10270 | ||
10271 | inst.instruction |= RdLo << 12; | |
10272 | inst.instruction |= RdHi << 8; | |
10273 | inst.instruction |= Rn << 16; | |
10274 | inst.instruction |= Rm; | |
c19d1205 | 10275 | } |
b99bd4ef | 10276 | |
c19d1205 ZW |
10277 | static void |
10278 | do_t_mov_cmp (void) | |
10279 | { | |
fdfde340 JM |
10280 | unsigned Rn, Rm; |
10281 | ||
10282 | Rn = inst.operands[0].reg; | |
10283 | Rm = inst.operands[1].reg; | |
10284 | ||
e07e6e58 NC |
10285 | if (Rn == REG_PC) |
10286 | set_it_insn_type_last (); | |
10287 | ||
c19d1205 | 10288 | if (unified_syntax) |
b99bd4ef | 10289 | { |
c19d1205 ZW |
10290 | int r0off = (inst.instruction == T_MNEM_mov |
10291 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 10292 | unsigned long opcode; |
3d388997 PB |
10293 | bfd_boolean narrow; |
10294 | bfd_boolean low_regs; | |
10295 | ||
fdfde340 | 10296 | low_regs = (Rn <= 7 && Rm <= 7); |
0110f2b8 | 10297 | opcode = inst.instruction; |
e07e6e58 | 10298 | if (in_it_block ()) |
0110f2b8 | 10299 | narrow = opcode != T_MNEM_movs; |
3d388997 | 10300 | else |
0110f2b8 | 10301 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
10302 | if (inst.size_req == 4 |
10303 | || inst.operands[1].shifted) | |
10304 | narrow = FALSE; | |
10305 | ||
efd81785 PB |
10306 | /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ |
10307 | if (opcode == T_MNEM_movs && inst.operands[1].isreg | |
10308 | && !inst.operands[1].shifted | |
fdfde340 JM |
10309 | && Rn == REG_PC |
10310 | && Rm == REG_LR) | |
efd81785 PB |
10311 | { |
10312 | inst.instruction = T2_SUBS_PC_LR; | |
10313 | return; | |
10314 | } | |
10315 | ||
fdfde340 JM |
10316 | if (opcode == T_MNEM_cmp) |
10317 | { | |
10318 | constraint (Rn == REG_PC, BAD_PC); | |
94206790 MM |
10319 | if (narrow) |
10320 | { | |
10321 | /* In the Thumb-2 ISA, use of R13 as Rm is deprecated, | |
10322 | but valid. */ | |
10323 | warn_deprecated_sp (Rm); | |
10324 | /* R15 was documented as a valid choice for Rm in ARMv6, | |
10325 | but as UNPREDICTABLE in ARMv7. ARM's proprietary | |
10326 | tools reject R15, so we do too. */ | |
10327 | constraint (Rm == REG_PC, BAD_PC); | |
10328 | } | |
10329 | else | |
10330 | reject_bad_reg (Rm); | |
fdfde340 JM |
10331 | } |
10332 | else if (opcode == T_MNEM_mov | |
10333 | || opcode == T_MNEM_movs) | |
10334 | { | |
10335 | if (inst.operands[1].isreg) | |
10336 | { | |
10337 | if (opcode == T_MNEM_movs) | |
10338 | { | |
10339 | reject_bad_reg (Rn); | |
10340 | reject_bad_reg (Rm); | |
10341 | } | |
76fa04a4 MGD |
10342 | else if (narrow) |
10343 | { | |
10344 | /* This is mov.n. */ | |
10345 | if ((Rn == REG_SP || Rn == REG_PC) | |
10346 | && (Rm == REG_SP || Rm == REG_PC)) | |
10347 | { | |
10348 | as_warn (_("Use of r%u as a source register is " | |
10349 | "deprecated when r%u is the destination " | |
10350 | "register."), Rm, Rn); | |
10351 | } | |
10352 | } | |
10353 | else | |
10354 | { | |
10355 | /* This is mov.w. */ | |
10356 | constraint (Rn == REG_PC, BAD_PC); | |
10357 | constraint (Rm == REG_PC, BAD_PC); | |
10358 | constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); | |
10359 | } | |
fdfde340 JM |
10360 | } |
10361 | else | |
10362 | reject_bad_reg (Rn); | |
10363 | } | |
10364 | ||
c19d1205 ZW |
10365 | if (!inst.operands[1].isreg) |
10366 | { | |
0110f2b8 | 10367 | /* Immediate operand. */ |
e07e6e58 | 10368 | if (!in_it_block () && opcode == T_MNEM_mov) |
0110f2b8 PB |
10369 | narrow = 0; |
10370 | if (low_regs && narrow) | |
10371 | { | |
10372 | inst.instruction = THUMB_OP16 (opcode); | |
fdfde340 | 10373 | inst.instruction |= Rn << 8; |
0110f2b8 PB |
10374 | if (inst.size_req == 2) |
10375 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
10376 | else | |
10377 | inst.relax = opcode; | |
10378 | } | |
10379 | else | |
10380 | { | |
10381 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10382 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 10383 | inst.instruction |= Rn << r0off; |
0110f2b8 PB |
10384 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
10385 | } | |
c19d1205 | 10386 | } |
728ca7c9 PB |
10387 | else if (inst.operands[1].shifted && inst.operands[1].immisreg |
10388 | && (inst.instruction == T_MNEM_mov | |
10389 | || inst.instruction == T_MNEM_movs)) | |
10390 | { | |
10391 | /* Register shifts are encoded as separate shift instructions. */ | |
10392 | bfd_boolean flags = (inst.instruction == T_MNEM_movs); | |
10393 | ||
e07e6e58 | 10394 | if (in_it_block ()) |
728ca7c9 PB |
10395 | narrow = !flags; |
10396 | else | |
10397 | narrow = flags; | |
10398 | ||
10399 | if (inst.size_req == 4) | |
10400 | narrow = FALSE; | |
10401 | ||
10402 | if (!low_regs || inst.operands[1].imm > 7) | |
10403 | narrow = FALSE; | |
10404 | ||
fdfde340 | 10405 | if (Rn != Rm) |
728ca7c9 PB |
10406 | narrow = FALSE; |
10407 | ||
10408 | switch (inst.operands[1].shift_kind) | |
10409 | { | |
10410 | case SHIFT_LSL: | |
10411 | opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); | |
10412 | break; | |
10413 | case SHIFT_ASR: | |
10414 | opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); | |
10415 | break; | |
10416 | case SHIFT_LSR: | |
10417 | opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); | |
10418 | break; | |
10419 | case SHIFT_ROR: | |
10420 | opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); | |
10421 | break; | |
10422 | default: | |
5f4273c7 | 10423 | abort (); |
728ca7c9 PB |
10424 | } |
10425 | ||
10426 | inst.instruction = opcode; | |
10427 | if (narrow) | |
10428 | { | |
fdfde340 | 10429 | inst.instruction |= Rn; |
728ca7c9 PB |
10430 | inst.instruction |= inst.operands[1].imm << 3; |
10431 | } | |
10432 | else | |
10433 | { | |
10434 | if (flags) | |
10435 | inst.instruction |= CONDS_BIT; | |
10436 | ||
fdfde340 JM |
10437 | inst.instruction |= Rn << 8; |
10438 | inst.instruction |= Rm << 16; | |
728ca7c9 PB |
10439 | inst.instruction |= inst.operands[1].imm; |
10440 | } | |
10441 | } | |
3d388997 | 10442 | else if (!narrow) |
c19d1205 | 10443 | { |
728ca7c9 PB |
10444 | /* Some mov with immediate shift have narrow variants. |
10445 | Register shifts are handled above. */ | |
10446 | if (low_regs && inst.operands[1].shifted | |
10447 | && (inst.instruction == T_MNEM_mov | |
10448 | || inst.instruction == T_MNEM_movs)) | |
10449 | { | |
e07e6e58 | 10450 | if (in_it_block ()) |
728ca7c9 PB |
10451 | narrow = (inst.instruction == T_MNEM_mov); |
10452 | else | |
10453 | narrow = (inst.instruction == T_MNEM_movs); | |
10454 | } | |
10455 | ||
10456 | if (narrow) | |
10457 | { | |
10458 | switch (inst.operands[1].shift_kind) | |
10459 | { | |
10460 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
10461 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
10462 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; | |
10463 | default: narrow = FALSE; break; | |
10464 | } | |
10465 | } | |
10466 | ||
10467 | if (narrow) | |
10468 | { | |
fdfde340 JM |
10469 | inst.instruction |= Rn; |
10470 | inst.instruction |= Rm << 3; | |
728ca7c9 PB |
10471 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
10472 | } | |
10473 | else | |
10474 | { | |
10475 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 10476 | inst.instruction |= Rn << r0off; |
728ca7c9 PB |
10477 | encode_thumb32_shifted_operand (1); |
10478 | } | |
c19d1205 ZW |
10479 | } |
10480 | else | |
10481 | switch (inst.instruction) | |
10482 | { | |
10483 | case T_MNEM_mov: | |
10484 | inst.instruction = T_OPCODE_MOV_HR; | |
fdfde340 JM |
10485 | inst.instruction |= (Rn & 0x8) << 4; |
10486 | inst.instruction |= (Rn & 0x7); | |
10487 | inst.instruction |= Rm << 3; | |
c19d1205 | 10488 | break; |
b99bd4ef | 10489 | |
c19d1205 ZW |
10490 | case T_MNEM_movs: |
10491 | /* We know we have low registers at this point. | |
941a8a52 MGD |
10492 | Generate LSLS Rd, Rs, #0. */ |
10493 | inst.instruction = T_OPCODE_LSL_I; | |
fdfde340 JM |
10494 | inst.instruction |= Rn; |
10495 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10496 | break; |
10497 | ||
10498 | case T_MNEM_cmp: | |
3d388997 | 10499 | if (low_regs) |
c19d1205 ZW |
10500 | { |
10501 | inst.instruction = T_OPCODE_CMP_LR; | |
fdfde340 JM |
10502 | inst.instruction |= Rn; |
10503 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10504 | } |
10505 | else | |
10506 | { | |
10507 | inst.instruction = T_OPCODE_CMP_HR; | |
fdfde340 JM |
10508 | inst.instruction |= (Rn & 0x8) << 4; |
10509 | inst.instruction |= (Rn & 0x7); | |
10510 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10511 | } |
10512 | break; | |
10513 | } | |
b99bd4ef NC |
10514 | return; |
10515 | } | |
10516 | ||
c19d1205 | 10517 | inst.instruction = THUMB_OP16 (inst.instruction); |
539d4391 NC |
10518 | |
10519 | /* PR 10443: Do not silently ignore shifted operands. */ | |
10520 | constraint (inst.operands[1].shifted, | |
10521 | _("shifts in CMP/MOV instructions are only supported in unified syntax")); | |
10522 | ||
c19d1205 | 10523 | if (inst.operands[1].isreg) |
b99bd4ef | 10524 | { |
fdfde340 | 10525 | if (Rn < 8 && Rm < 8) |
b99bd4ef | 10526 | { |
c19d1205 ZW |
10527 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
10528 | since a MOV instruction produces unpredictable results. */ | |
10529 | if (inst.instruction == T_OPCODE_MOV_I8) | |
10530 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 10531 | else |
c19d1205 | 10532 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 10533 | |
fdfde340 JM |
10534 | inst.instruction |= Rn; |
10535 | inst.instruction |= Rm << 3; | |
b99bd4ef NC |
10536 | } |
10537 | else | |
10538 | { | |
c19d1205 ZW |
10539 | if (inst.instruction == T_OPCODE_MOV_I8) |
10540 | inst.instruction = T_OPCODE_MOV_HR; | |
10541 | else | |
10542 | inst.instruction = T_OPCODE_CMP_HR; | |
10543 | do_t_cpy (); | |
b99bd4ef NC |
10544 | } |
10545 | } | |
c19d1205 | 10546 | else |
b99bd4ef | 10547 | { |
fdfde340 | 10548 | constraint (Rn > 7, |
c19d1205 | 10549 | _("only lo regs allowed with immediate")); |
fdfde340 | 10550 | inst.instruction |= Rn << 8; |
c19d1205 ZW |
10551 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; |
10552 | } | |
10553 | } | |
b99bd4ef | 10554 | |
c19d1205 ZW |
10555 | static void |
10556 | do_t_mov16 (void) | |
10557 | { | |
fdfde340 | 10558 | unsigned Rd; |
b6895b4f PB |
10559 | bfd_vma imm; |
10560 | bfd_boolean top; | |
10561 | ||
10562 | top = (inst.instruction & 0x00800000) != 0; | |
10563 | if (inst.reloc.type == BFD_RELOC_ARM_MOVW) | |
10564 | { | |
10565 | constraint (top, _(":lower16: not allowed this instruction")); | |
10566 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; | |
10567 | } | |
10568 | else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) | |
10569 | { | |
10570 | constraint (!top, _(":upper16: not allowed this instruction")); | |
10571 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; | |
10572 | } | |
10573 | ||
fdfde340 JM |
10574 | Rd = inst.operands[0].reg; |
10575 | reject_bad_reg (Rd); | |
10576 | ||
10577 | inst.instruction |= Rd << 8; | |
b6895b4f PB |
10578 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
10579 | { | |
10580 | imm = inst.reloc.exp.X_add_number; | |
10581 | inst.instruction |= (imm & 0xf000) << 4; | |
10582 | inst.instruction |= (imm & 0x0800) << 15; | |
10583 | inst.instruction |= (imm & 0x0700) << 4; | |
10584 | inst.instruction |= (imm & 0x00ff); | |
10585 | } | |
c19d1205 | 10586 | } |
b99bd4ef | 10587 | |
c19d1205 ZW |
10588 | static void |
10589 | do_t_mvn_tst (void) | |
10590 | { | |
fdfde340 | 10591 | unsigned Rn, Rm; |
c921be7d | 10592 | |
fdfde340 JM |
10593 | Rn = inst.operands[0].reg; |
10594 | Rm = inst.operands[1].reg; | |
10595 | ||
10596 | if (inst.instruction == T_MNEM_cmp | |
10597 | || inst.instruction == T_MNEM_cmn) | |
10598 | constraint (Rn == REG_PC, BAD_PC); | |
10599 | else | |
10600 | reject_bad_reg (Rn); | |
10601 | reject_bad_reg (Rm); | |
10602 | ||
c19d1205 ZW |
10603 | if (unified_syntax) |
10604 | { | |
10605 | int r0off = (inst.instruction == T_MNEM_mvn | |
10606 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
10607 | bfd_boolean narrow; |
10608 | ||
10609 | if (inst.size_req == 4 | |
10610 | || inst.instruction > 0xffff | |
10611 | || inst.operands[1].shifted | |
fdfde340 | 10612 | || Rn > 7 || Rm > 7) |
3d388997 PB |
10613 | narrow = FALSE; |
10614 | else if (inst.instruction == T_MNEM_cmn) | |
10615 | narrow = TRUE; | |
10616 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 10617 | narrow = !in_it_block (); |
3d388997 | 10618 | else |
e07e6e58 | 10619 | narrow = in_it_block (); |
3d388997 | 10620 | |
c19d1205 | 10621 | if (!inst.operands[1].isreg) |
b99bd4ef | 10622 | { |
c19d1205 ZW |
10623 | /* For an immediate, we always generate a 32-bit opcode; |
10624 | section relaxation will shrink it later if possible. */ | |
10625 | if (inst.instruction < 0xffff) | |
10626 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10627 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 10628 | inst.instruction |= Rn << r0off; |
c19d1205 | 10629 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
b99bd4ef | 10630 | } |
c19d1205 | 10631 | else |
b99bd4ef | 10632 | { |
c19d1205 | 10633 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 10634 | if (narrow) |
b99bd4ef | 10635 | { |
c19d1205 | 10636 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
10637 | inst.instruction |= Rn; |
10638 | inst.instruction |= Rm << 3; | |
b99bd4ef | 10639 | } |
c19d1205 | 10640 | else |
b99bd4ef | 10641 | { |
c19d1205 ZW |
10642 | constraint (inst.operands[1].shifted |
10643 | && inst.operands[1].immisreg, | |
10644 | _("shift must be constant")); | |
10645 | if (inst.instruction < 0xffff) | |
10646 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 10647 | inst.instruction |= Rn << r0off; |
c19d1205 | 10648 | encode_thumb32_shifted_operand (1); |
b99bd4ef | 10649 | } |
b99bd4ef NC |
10650 | } |
10651 | } | |
10652 | else | |
10653 | { | |
c19d1205 ZW |
10654 | constraint (inst.instruction > 0xffff |
10655 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
10656 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
10657 | _("unshifted register required")); | |
fdfde340 | 10658 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 10659 | BAD_HIREG); |
b99bd4ef | 10660 | |
c19d1205 | 10661 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
10662 | inst.instruction |= Rn; |
10663 | inst.instruction |= Rm << 3; | |
b99bd4ef | 10664 | } |
b99bd4ef NC |
10665 | } |
10666 | ||
b05fe5cf | 10667 | static void |
c19d1205 | 10668 | do_t_mrs (void) |
b05fe5cf | 10669 | { |
fdfde340 | 10670 | unsigned Rd; |
62b3e311 | 10671 | int flags; |
037e8744 JB |
10672 | |
10673 | if (do_vfp_nsyn_mrs () == SUCCESS) | |
10674 | return; | |
10675 | ||
62b3e311 PB |
10676 | flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
10677 | if (flags == 0) | |
10678 | { | |
7e806470 | 10679 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m), |
62b3e311 PB |
10680 | _("selected processor does not support " |
10681 | "requested special purpose register")); | |
10682 | } | |
10683 | else | |
10684 | { | |
10685 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), | |
10686 | _("selected processor does not support " | |
44bf2362 | 10687 | "requested special purpose register")); |
62b3e311 PB |
10688 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ |
10689 | constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), | |
10690 | _("'CPSR' or 'SPSR' expected")); | |
10691 | } | |
5f4273c7 | 10692 | |
fdfde340 JM |
10693 | Rd = inst.operands[0].reg; |
10694 | reject_bad_reg (Rd); | |
10695 | ||
10696 | inst.instruction |= Rd << 8; | |
62b3e311 PB |
10697 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
10698 | inst.instruction |= inst.operands[1].imm & 0xff; | |
c19d1205 | 10699 | } |
b05fe5cf | 10700 | |
c19d1205 ZW |
10701 | static void |
10702 | do_t_msr (void) | |
10703 | { | |
62b3e311 | 10704 | int flags; |
fdfde340 | 10705 | unsigned Rn; |
62b3e311 | 10706 | |
037e8744 JB |
10707 | if (do_vfp_nsyn_msr () == SUCCESS) |
10708 | return; | |
10709 | ||
c19d1205 ZW |
10710 | constraint (!inst.operands[1].isreg, |
10711 | _("Thumb encoding does not support an immediate here")); | |
62b3e311 PB |
10712 | flags = inst.operands[0].imm; |
10713 | if (flags & ~0xff) | |
10714 | { | |
10715 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), | |
10716 | _("selected processor does not support " | |
10717 | "requested special purpose register")); | |
10718 | } | |
10719 | else | |
10720 | { | |
7e806470 | 10721 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m), |
62b3e311 PB |
10722 | _("selected processor does not support " |
10723 | "requested special purpose register")); | |
10724 | flags |= PSR_f; | |
10725 | } | |
c921be7d | 10726 | |
fdfde340 JM |
10727 | Rn = inst.operands[1].reg; |
10728 | reject_bad_reg (Rn); | |
10729 | ||
62b3e311 PB |
10730 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
10731 | inst.instruction |= (flags & ~SPSR_BIT) >> 8; | |
10732 | inst.instruction |= (flags & 0xff); | |
fdfde340 | 10733 | inst.instruction |= Rn << 16; |
c19d1205 | 10734 | } |
b05fe5cf | 10735 | |
c19d1205 ZW |
10736 | static void |
10737 | do_t_mul (void) | |
10738 | { | |
17828f45 | 10739 | bfd_boolean narrow; |
fdfde340 | 10740 | unsigned Rd, Rn, Rm; |
17828f45 | 10741 | |
c19d1205 ZW |
10742 | if (!inst.operands[2].present) |
10743 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 10744 | |
fdfde340 JM |
10745 | Rd = inst.operands[0].reg; |
10746 | Rn = inst.operands[1].reg; | |
10747 | Rm = inst.operands[2].reg; | |
10748 | ||
17828f45 | 10749 | if (unified_syntax) |
b05fe5cf | 10750 | { |
17828f45 | 10751 | if (inst.size_req == 4 |
fdfde340 JM |
10752 | || (Rd != Rn |
10753 | && Rd != Rm) | |
10754 | || Rn > 7 | |
10755 | || Rm > 7) | |
17828f45 JM |
10756 | narrow = FALSE; |
10757 | else if (inst.instruction == T_MNEM_muls) | |
e07e6e58 | 10758 | narrow = !in_it_block (); |
17828f45 | 10759 | else |
e07e6e58 | 10760 | narrow = in_it_block (); |
b05fe5cf | 10761 | } |
c19d1205 | 10762 | else |
b05fe5cf | 10763 | { |
17828f45 | 10764 | constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); |
fdfde340 | 10765 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 10766 | BAD_HIREG); |
17828f45 JM |
10767 | narrow = TRUE; |
10768 | } | |
b05fe5cf | 10769 | |
17828f45 JM |
10770 | if (narrow) |
10771 | { | |
10772 | /* 16-bit MULS/Conditional MUL. */ | |
c19d1205 | 10773 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 | 10774 | inst.instruction |= Rd; |
b05fe5cf | 10775 | |
fdfde340 JM |
10776 | if (Rd == Rn) |
10777 | inst.instruction |= Rm << 3; | |
10778 | else if (Rd == Rm) | |
10779 | inst.instruction |= Rn << 3; | |
c19d1205 ZW |
10780 | else |
10781 | constraint (1, _("dest must overlap one source register")); | |
10782 | } | |
17828f45 JM |
10783 | else |
10784 | { | |
e07e6e58 NC |
10785 | constraint (inst.instruction != T_MNEM_mul, |
10786 | _("Thumb-2 MUL must not set flags")); | |
17828f45 JM |
10787 | /* 32-bit MUL. */ |
10788 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
10789 | inst.instruction |= Rd << 8; |
10790 | inst.instruction |= Rn << 16; | |
10791 | inst.instruction |= Rm << 0; | |
10792 | ||
10793 | reject_bad_reg (Rd); | |
10794 | reject_bad_reg (Rn); | |
10795 | reject_bad_reg (Rm); | |
17828f45 | 10796 | } |
c19d1205 | 10797 | } |
b05fe5cf | 10798 | |
c19d1205 ZW |
10799 | static void |
10800 | do_t_mull (void) | |
10801 | { | |
fdfde340 | 10802 | unsigned RdLo, RdHi, Rn, Rm; |
b05fe5cf | 10803 | |
fdfde340 JM |
10804 | RdLo = inst.operands[0].reg; |
10805 | RdHi = inst.operands[1].reg; | |
10806 | Rn = inst.operands[2].reg; | |
10807 | Rm = inst.operands[3].reg; | |
10808 | ||
10809 | reject_bad_reg (RdLo); | |
10810 | reject_bad_reg (RdHi); | |
10811 | reject_bad_reg (Rn); | |
10812 | reject_bad_reg (Rm); | |
10813 | ||
10814 | inst.instruction |= RdLo << 12; | |
10815 | inst.instruction |= RdHi << 8; | |
10816 | inst.instruction |= Rn << 16; | |
10817 | inst.instruction |= Rm; | |
10818 | ||
10819 | if (RdLo == RdHi) | |
c19d1205 ZW |
10820 | as_tsktsk (_("rdhi and rdlo must be different")); |
10821 | } | |
b05fe5cf | 10822 | |
c19d1205 ZW |
10823 | static void |
10824 | do_t_nop (void) | |
10825 | { | |
e07e6e58 NC |
10826 | set_it_insn_type (NEUTRAL_IT_INSN); |
10827 | ||
c19d1205 ZW |
10828 | if (unified_syntax) |
10829 | { | |
10830 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 10831 | { |
c19d1205 ZW |
10832 | inst.instruction = THUMB_OP32 (inst.instruction); |
10833 | inst.instruction |= inst.operands[0].imm; | |
10834 | } | |
10835 | else | |
10836 | { | |
bc2d1808 NC |
10837 | /* PR9722: Check for Thumb2 availability before |
10838 | generating a thumb2 nop instruction. */ | |
afa62d5e | 10839 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
bc2d1808 NC |
10840 | { |
10841 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10842 | inst.instruction |= inst.operands[0].imm << 4; | |
10843 | } | |
10844 | else | |
10845 | inst.instruction = 0x46c0; | |
c19d1205 ZW |
10846 | } |
10847 | } | |
10848 | else | |
10849 | { | |
10850 | constraint (inst.operands[0].present, | |
10851 | _("Thumb does not support NOP with hints")); | |
10852 | inst.instruction = 0x46c0; | |
10853 | } | |
10854 | } | |
b05fe5cf | 10855 | |
c19d1205 ZW |
10856 | static void |
10857 | do_t_neg (void) | |
10858 | { | |
10859 | if (unified_syntax) | |
10860 | { | |
3d388997 PB |
10861 | bfd_boolean narrow; |
10862 | ||
10863 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 10864 | narrow = !in_it_block (); |
3d388997 | 10865 | else |
e07e6e58 | 10866 | narrow = in_it_block (); |
3d388997 PB |
10867 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
10868 | narrow = FALSE; | |
10869 | if (inst.size_req == 4) | |
10870 | narrow = FALSE; | |
10871 | ||
10872 | if (!narrow) | |
c19d1205 ZW |
10873 | { |
10874 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10875 | inst.instruction |= inst.operands[0].reg << 8; | |
10876 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
10877 | } |
10878 | else | |
10879 | { | |
c19d1205 ZW |
10880 | inst.instruction = THUMB_OP16 (inst.instruction); |
10881 | inst.instruction |= inst.operands[0].reg; | |
10882 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
10883 | } |
10884 | } | |
10885 | else | |
10886 | { | |
c19d1205 ZW |
10887 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
10888 | BAD_HIREG); | |
10889 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
10890 | ||
10891 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10892 | inst.instruction |= inst.operands[0].reg; | |
10893 | inst.instruction |= inst.operands[1].reg << 3; | |
10894 | } | |
10895 | } | |
10896 | ||
1c444d06 JM |
10897 | static void |
10898 | do_t_orn (void) | |
10899 | { | |
10900 | unsigned Rd, Rn; | |
10901 | ||
10902 | Rd = inst.operands[0].reg; | |
10903 | Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; | |
10904 | ||
fdfde340 JM |
10905 | reject_bad_reg (Rd); |
10906 | /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ | |
10907 | reject_bad_reg (Rn); | |
10908 | ||
1c444d06 JM |
10909 | inst.instruction |= Rd << 8; |
10910 | inst.instruction |= Rn << 16; | |
10911 | ||
10912 | if (!inst.operands[2].isreg) | |
10913 | { | |
10914 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
10915 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10916 | } | |
10917 | else | |
10918 | { | |
10919 | unsigned Rm; | |
10920 | ||
10921 | Rm = inst.operands[2].reg; | |
fdfde340 | 10922 | reject_bad_reg (Rm); |
1c444d06 JM |
10923 | |
10924 | constraint (inst.operands[2].shifted | |
10925 | && inst.operands[2].immisreg, | |
10926 | _("shift must be constant")); | |
10927 | encode_thumb32_shifted_operand (2); | |
10928 | } | |
10929 | } | |
10930 | ||
c19d1205 ZW |
10931 | static void |
10932 | do_t_pkhbt (void) | |
10933 | { | |
fdfde340 JM |
10934 | unsigned Rd, Rn, Rm; |
10935 | ||
10936 | Rd = inst.operands[0].reg; | |
10937 | Rn = inst.operands[1].reg; | |
10938 | Rm = inst.operands[2].reg; | |
10939 | ||
10940 | reject_bad_reg (Rd); | |
10941 | reject_bad_reg (Rn); | |
10942 | reject_bad_reg (Rm); | |
10943 | ||
10944 | inst.instruction |= Rd << 8; | |
10945 | inst.instruction |= Rn << 16; | |
10946 | inst.instruction |= Rm; | |
c19d1205 ZW |
10947 | if (inst.operands[3].present) |
10948 | { | |
10949 | unsigned int val = inst.reloc.exp.X_add_number; | |
10950 | constraint (inst.reloc.exp.X_op != O_constant, | |
10951 | _("expression too complex")); | |
10952 | inst.instruction |= (val & 0x1c) << 10; | |
10953 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 10954 | } |
c19d1205 | 10955 | } |
b05fe5cf | 10956 | |
c19d1205 ZW |
10957 | static void |
10958 | do_t_pkhtb (void) | |
10959 | { | |
10960 | if (!inst.operands[3].present) | |
1ef52f49 NC |
10961 | { |
10962 | unsigned Rtmp; | |
10963 | ||
10964 | inst.instruction &= ~0x00000020; | |
10965 | ||
10966 | /* PR 10168. Swap the Rm and Rn registers. */ | |
10967 | Rtmp = inst.operands[1].reg; | |
10968 | inst.operands[1].reg = inst.operands[2].reg; | |
10969 | inst.operands[2].reg = Rtmp; | |
10970 | } | |
c19d1205 | 10971 | do_t_pkhbt (); |
b05fe5cf ZW |
10972 | } |
10973 | ||
c19d1205 ZW |
10974 | static void |
10975 | do_t_pld (void) | |
10976 | { | |
fdfde340 JM |
10977 | if (inst.operands[0].immisreg) |
10978 | reject_bad_reg (inst.operands[0].imm); | |
10979 | ||
c19d1205 ZW |
10980 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); |
10981 | } | |
b05fe5cf | 10982 | |
c19d1205 ZW |
10983 | static void |
10984 | do_t_push_pop (void) | |
b99bd4ef | 10985 | { |
e9f89963 | 10986 | unsigned mask; |
5f4273c7 | 10987 | |
c19d1205 ZW |
10988 | constraint (inst.operands[0].writeback, |
10989 | _("push/pop do not support {reglist}^")); | |
10990 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
10991 | _("expression too complex")); | |
b99bd4ef | 10992 | |
e9f89963 PB |
10993 | mask = inst.operands[0].imm; |
10994 | if ((mask & ~0xff) == 0) | |
3c707909 | 10995 | inst.instruction = THUMB_OP16 (inst.instruction) | mask; |
c19d1205 | 10996 | else if ((inst.instruction == T_MNEM_push |
e9f89963 | 10997 | && (mask & ~0xff) == 1 << REG_LR) |
c19d1205 | 10998 | || (inst.instruction == T_MNEM_pop |
e9f89963 | 10999 | && (mask & ~0xff) == 1 << REG_PC)) |
b99bd4ef | 11000 | { |
c19d1205 ZW |
11001 | inst.instruction = THUMB_OP16 (inst.instruction); |
11002 | inst.instruction |= THUMB_PP_PC_LR; | |
3c707909 | 11003 | inst.instruction |= mask & 0xff; |
c19d1205 ZW |
11004 | } |
11005 | else if (unified_syntax) | |
11006 | { | |
3c707909 | 11007 | inst.instruction = THUMB_OP32 (inst.instruction); |
5f4273c7 | 11008 | encode_thumb2_ldmstm (13, mask, TRUE); |
c19d1205 ZW |
11009 | } |
11010 | else | |
11011 | { | |
11012 | inst.error = _("invalid register list to push/pop instruction"); | |
11013 | return; | |
11014 | } | |
c19d1205 | 11015 | } |
b99bd4ef | 11016 | |
c19d1205 ZW |
11017 | static void |
11018 | do_t_rbit (void) | |
11019 | { | |
fdfde340 JM |
11020 | unsigned Rd, Rm; |
11021 | ||
11022 | Rd = inst.operands[0].reg; | |
11023 | Rm = inst.operands[1].reg; | |
11024 | ||
11025 | reject_bad_reg (Rd); | |
11026 | reject_bad_reg (Rm); | |
11027 | ||
11028 | inst.instruction |= Rd << 8; | |
11029 | inst.instruction |= Rm << 16; | |
11030 | inst.instruction |= Rm; | |
c19d1205 | 11031 | } |
b99bd4ef | 11032 | |
c19d1205 ZW |
11033 | static void |
11034 | do_t_rev (void) | |
11035 | { | |
fdfde340 JM |
11036 | unsigned Rd, Rm; |
11037 | ||
11038 | Rd = inst.operands[0].reg; | |
11039 | Rm = inst.operands[1].reg; | |
11040 | ||
11041 | reject_bad_reg (Rd); | |
11042 | reject_bad_reg (Rm); | |
11043 | ||
11044 | if (Rd <= 7 && Rm <= 7 | |
c19d1205 ZW |
11045 | && inst.size_req != 4) |
11046 | { | |
11047 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 JM |
11048 | inst.instruction |= Rd; |
11049 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11050 | } |
11051 | else if (unified_syntax) | |
11052 | { | |
11053 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
11054 | inst.instruction |= Rd << 8; |
11055 | inst.instruction |= Rm << 16; | |
11056 | inst.instruction |= Rm; | |
c19d1205 ZW |
11057 | } |
11058 | else | |
11059 | inst.error = BAD_HIREG; | |
11060 | } | |
b99bd4ef | 11061 | |
1c444d06 JM |
11062 | static void |
11063 | do_t_rrx (void) | |
11064 | { | |
11065 | unsigned Rd, Rm; | |
11066 | ||
11067 | Rd = inst.operands[0].reg; | |
11068 | Rm = inst.operands[1].reg; | |
11069 | ||
fdfde340 JM |
11070 | reject_bad_reg (Rd); |
11071 | reject_bad_reg (Rm); | |
c921be7d | 11072 | |
1c444d06 JM |
11073 | inst.instruction |= Rd << 8; |
11074 | inst.instruction |= Rm; | |
11075 | } | |
11076 | ||
c19d1205 ZW |
11077 | static void |
11078 | do_t_rsb (void) | |
11079 | { | |
fdfde340 | 11080 | unsigned Rd, Rs; |
b99bd4ef | 11081 | |
c19d1205 ZW |
11082 | Rd = inst.operands[0].reg; |
11083 | Rs = (inst.operands[1].present | |
11084 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
11085 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 11086 | |
fdfde340 JM |
11087 | reject_bad_reg (Rd); |
11088 | reject_bad_reg (Rs); | |
11089 | if (inst.operands[2].isreg) | |
11090 | reject_bad_reg (inst.operands[2].reg); | |
11091 | ||
c19d1205 ZW |
11092 | inst.instruction |= Rd << 8; |
11093 | inst.instruction |= Rs << 16; | |
11094 | if (!inst.operands[2].isreg) | |
11095 | { | |
026d3abb PB |
11096 | bfd_boolean narrow; |
11097 | ||
11098 | if ((inst.instruction & 0x00100000) != 0) | |
e07e6e58 | 11099 | narrow = !in_it_block (); |
026d3abb | 11100 | else |
e07e6e58 | 11101 | narrow = in_it_block (); |
026d3abb PB |
11102 | |
11103 | if (Rd > 7 || Rs > 7) | |
11104 | narrow = FALSE; | |
11105 | ||
11106 | if (inst.size_req == 4 || !unified_syntax) | |
11107 | narrow = FALSE; | |
11108 | ||
11109 | if (inst.reloc.exp.X_op != O_constant | |
11110 | || inst.reloc.exp.X_add_number != 0) | |
11111 | narrow = FALSE; | |
11112 | ||
11113 | /* Turn rsb #0 into 16-bit neg. We should probably do this via | |
11114 | relaxation, but it doesn't seem worth the hassle. */ | |
11115 | if (narrow) | |
11116 | { | |
11117 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11118 | inst.instruction = THUMB_OP16 (T_MNEM_negs); | |
11119 | inst.instruction |= Rs << 3; | |
11120 | inst.instruction |= Rd; | |
11121 | } | |
11122 | else | |
11123 | { | |
11124 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
11125 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
11126 | } | |
c19d1205 ZW |
11127 | } |
11128 | else | |
11129 | encode_thumb32_shifted_operand (2); | |
11130 | } | |
b99bd4ef | 11131 | |
c19d1205 ZW |
11132 | static void |
11133 | do_t_setend (void) | |
11134 | { | |
e07e6e58 | 11135 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
11136 | if (inst.operands[0].imm) |
11137 | inst.instruction |= 0x8; | |
11138 | } | |
b99bd4ef | 11139 | |
c19d1205 ZW |
11140 | static void |
11141 | do_t_shift (void) | |
11142 | { | |
11143 | if (!inst.operands[1].present) | |
11144 | inst.operands[1].reg = inst.operands[0].reg; | |
11145 | ||
11146 | if (unified_syntax) | |
11147 | { | |
3d388997 PB |
11148 | bfd_boolean narrow; |
11149 | int shift_kind; | |
11150 | ||
11151 | switch (inst.instruction) | |
11152 | { | |
11153 | case T_MNEM_asr: | |
11154 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
11155 | case T_MNEM_lsl: | |
11156 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
11157 | case T_MNEM_lsr: | |
11158 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
11159 | case T_MNEM_ror: | |
11160 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
11161 | default: abort (); | |
11162 | } | |
11163 | ||
11164 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 11165 | narrow = !in_it_block (); |
3d388997 | 11166 | else |
e07e6e58 | 11167 | narrow = in_it_block (); |
3d388997 PB |
11168 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
11169 | narrow = FALSE; | |
11170 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
11171 | narrow = FALSE; | |
11172 | if (inst.operands[2].isreg | |
11173 | && (inst.operands[1].reg != inst.operands[0].reg | |
11174 | || inst.operands[2].reg > 7)) | |
11175 | narrow = FALSE; | |
11176 | if (inst.size_req == 4) | |
11177 | narrow = FALSE; | |
11178 | ||
fdfde340 JM |
11179 | reject_bad_reg (inst.operands[0].reg); |
11180 | reject_bad_reg (inst.operands[1].reg); | |
c921be7d | 11181 | |
3d388997 | 11182 | if (!narrow) |
c19d1205 ZW |
11183 | { |
11184 | if (inst.operands[2].isreg) | |
b99bd4ef | 11185 | { |
fdfde340 | 11186 | reject_bad_reg (inst.operands[2].reg); |
c19d1205 ZW |
11187 | inst.instruction = THUMB_OP32 (inst.instruction); |
11188 | inst.instruction |= inst.operands[0].reg << 8; | |
11189 | inst.instruction |= inst.operands[1].reg << 16; | |
11190 | inst.instruction |= inst.operands[2].reg; | |
11191 | } | |
11192 | else | |
11193 | { | |
11194 | inst.operands[1].shifted = 1; | |
3d388997 | 11195 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
11196 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
11197 | ? T_MNEM_movs : T_MNEM_mov); | |
11198 | inst.instruction |= inst.operands[0].reg << 8; | |
11199 | encode_thumb32_shifted_operand (1); | |
11200 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
11201 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef NC |
11202 | } |
11203 | } | |
11204 | else | |
11205 | { | |
c19d1205 | 11206 | if (inst.operands[2].isreg) |
b99bd4ef | 11207 | { |
3d388997 | 11208 | switch (shift_kind) |
b99bd4ef | 11209 | { |
3d388997 PB |
11210 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
11211 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
11212 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
11213 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 11214 | default: abort (); |
b99bd4ef | 11215 | } |
5f4273c7 | 11216 | |
c19d1205 ZW |
11217 | inst.instruction |= inst.operands[0].reg; |
11218 | inst.instruction |= inst.operands[2].reg << 3; | |
b99bd4ef NC |
11219 | } |
11220 | else | |
11221 | { | |
3d388997 | 11222 | switch (shift_kind) |
b99bd4ef | 11223 | { |
3d388997 PB |
11224 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
11225 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
11226 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 11227 | default: abort (); |
b99bd4ef | 11228 | } |
c19d1205 ZW |
11229 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
11230 | inst.instruction |= inst.operands[0].reg; | |
11231 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
11232 | } |
11233 | } | |
c19d1205 ZW |
11234 | } |
11235 | else | |
11236 | { | |
11237 | constraint (inst.operands[0].reg > 7 | |
11238 | || inst.operands[1].reg > 7, BAD_HIREG); | |
11239 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 11240 | |
c19d1205 ZW |
11241 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
11242 | { | |
11243 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
11244 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
11245 | _("source1 and dest must be same register")); | |
b99bd4ef | 11246 | |
c19d1205 ZW |
11247 | switch (inst.instruction) |
11248 | { | |
11249 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
11250 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
11251 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
11252 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
11253 | default: abort (); | |
11254 | } | |
5f4273c7 | 11255 | |
c19d1205 ZW |
11256 | inst.instruction |= inst.operands[0].reg; |
11257 | inst.instruction |= inst.operands[2].reg << 3; | |
11258 | } | |
11259 | else | |
b99bd4ef | 11260 | { |
c19d1205 ZW |
11261 | switch (inst.instruction) |
11262 | { | |
11263 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
11264 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
11265 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
11266 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
11267 | default: abort (); | |
11268 | } | |
11269 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
11270 | inst.instruction |= inst.operands[0].reg; | |
11271 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
11272 | } |
11273 | } | |
b99bd4ef NC |
11274 | } |
11275 | ||
11276 | static void | |
c19d1205 | 11277 | do_t_simd (void) |
b99bd4ef | 11278 | { |
fdfde340 JM |
11279 | unsigned Rd, Rn, Rm; |
11280 | ||
11281 | Rd = inst.operands[0].reg; | |
11282 | Rn = inst.operands[1].reg; | |
11283 | Rm = inst.operands[2].reg; | |
11284 | ||
11285 | reject_bad_reg (Rd); | |
11286 | reject_bad_reg (Rn); | |
11287 | reject_bad_reg (Rm); | |
11288 | ||
11289 | inst.instruction |= Rd << 8; | |
11290 | inst.instruction |= Rn << 16; | |
11291 | inst.instruction |= Rm; | |
c19d1205 | 11292 | } |
b99bd4ef | 11293 | |
03ee1b7f NC |
11294 | static void |
11295 | do_t_simd2 (void) | |
11296 | { | |
11297 | unsigned Rd, Rn, Rm; | |
11298 | ||
11299 | Rd = inst.operands[0].reg; | |
11300 | Rm = inst.operands[1].reg; | |
11301 | Rn = inst.operands[2].reg; | |
11302 | ||
11303 | reject_bad_reg (Rd); | |
11304 | reject_bad_reg (Rn); | |
11305 | reject_bad_reg (Rm); | |
11306 | ||
11307 | inst.instruction |= Rd << 8; | |
11308 | inst.instruction |= Rn << 16; | |
11309 | inst.instruction |= Rm; | |
11310 | } | |
11311 | ||
c19d1205 | 11312 | static void |
3eb17e6b | 11313 | do_t_smc (void) |
c19d1205 ZW |
11314 | { |
11315 | unsigned int value = inst.reloc.exp.X_add_number; | |
11316 | constraint (inst.reloc.exp.X_op != O_constant, | |
11317 | _("expression too complex")); | |
11318 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11319 | inst.instruction |= (value & 0xf000) >> 12; | |
11320 | inst.instruction |= (value & 0x0ff0); | |
11321 | inst.instruction |= (value & 0x000f) << 16; | |
11322 | } | |
b99bd4ef | 11323 | |
c19d1205 | 11324 | static void |
3a21c15a | 11325 | do_t_ssat_usat (int bias) |
c19d1205 | 11326 | { |
fdfde340 JM |
11327 | unsigned Rd, Rn; |
11328 | ||
11329 | Rd = inst.operands[0].reg; | |
11330 | Rn = inst.operands[2].reg; | |
11331 | ||
11332 | reject_bad_reg (Rd); | |
11333 | reject_bad_reg (Rn); | |
11334 | ||
11335 | inst.instruction |= Rd << 8; | |
3a21c15a | 11336 | inst.instruction |= inst.operands[1].imm - bias; |
fdfde340 | 11337 | inst.instruction |= Rn << 16; |
b99bd4ef | 11338 | |
c19d1205 | 11339 | if (inst.operands[3].present) |
b99bd4ef | 11340 | { |
3a21c15a NC |
11341 | offsetT shift_amount = inst.reloc.exp.X_add_number; |
11342 | ||
11343 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11344 | ||
c19d1205 ZW |
11345 | constraint (inst.reloc.exp.X_op != O_constant, |
11346 | _("expression too complex")); | |
b99bd4ef | 11347 | |
3a21c15a | 11348 | if (shift_amount != 0) |
6189168b | 11349 | { |
3a21c15a NC |
11350 | constraint (shift_amount > 31, |
11351 | _("shift expression is too large")); | |
11352 | ||
c19d1205 | 11353 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
3a21c15a NC |
11354 | inst.instruction |= 0x00200000; /* sh bit. */ |
11355 | ||
11356 | inst.instruction |= (shift_amount & 0x1c) << 10; | |
11357 | inst.instruction |= (shift_amount & 0x03) << 6; | |
6189168b NC |
11358 | } |
11359 | } | |
b99bd4ef | 11360 | } |
c921be7d | 11361 | |
3a21c15a NC |
11362 | static void |
11363 | do_t_ssat (void) | |
11364 | { | |
11365 | do_t_ssat_usat (1); | |
11366 | } | |
b99bd4ef | 11367 | |
0dd132b6 | 11368 | static void |
c19d1205 | 11369 | do_t_ssat16 (void) |
0dd132b6 | 11370 | { |
fdfde340 JM |
11371 | unsigned Rd, Rn; |
11372 | ||
11373 | Rd = inst.operands[0].reg; | |
11374 | Rn = inst.operands[2].reg; | |
11375 | ||
11376 | reject_bad_reg (Rd); | |
11377 | reject_bad_reg (Rn); | |
11378 | ||
11379 | inst.instruction |= Rd << 8; | |
c19d1205 | 11380 | inst.instruction |= inst.operands[1].imm - 1; |
fdfde340 | 11381 | inst.instruction |= Rn << 16; |
c19d1205 | 11382 | } |
0dd132b6 | 11383 | |
c19d1205 ZW |
11384 | static void |
11385 | do_t_strex (void) | |
11386 | { | |
11387 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
11388 | || inst.operands[2].postind || inst.operands[2].writeback | |
11389 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
11390 | || inst.operands[2].negative, | |
01cfc07f | 11391 | BAD_ADDR_MODE); |
0dd132b6 | 11392 | |
5be8be5d DG |
11393 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
11394 | ||
c19d1205 ZW |
11395 | inst.instruction |= inst.operands[0].reg << 8; |
11396 | inst.instruction |= inst.operands[1].reg << 12; | |
11397 | inst.instruction |= inst.operands[2].reg << 16; | |
11398 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
0dd132b6 NC |
11399 | } |
11400 | ||
b99bd4ef | 11401 | static void |
c19d1205 | 11402 | do_t_strexd (void) |
b99bd4ef | 11403 | { |
c19d1205 ZW |
11404 | if (!inst.operands[2].present) |
11405 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 11406 | |
c19d1205 ZW |
11407 | constraint (inst.operands[0].reg == inst.operands[1].reg |
11408 | || inst.operands[0].reg == inst.operands[2].reg | |
f8a8e9d6 | 11409 | || inst.operands[0].reg == inst.operands[3].reg, |
c19d1205 | 11410 | BAD_OVERLAP); |
b99bd4ef | 11411 | |
c19d1205 ZW |
11412 | inst.instruction |= inst.operands[0].reg; |
11413 | inst.instruction |= inst.operands[1].reg << 12; | |
11414 | inst.instruction |= inst.operands[2].reg << 8; | |
11415 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
11416 | } |
11417 | ||
11418 | static void | |
c19d1205 | 11419 | do_t_sxtah (void) |
b99bd4ef | 11420 | { |
fdfde340 JM |
11421 | unsigned Rd, Rn, Rm; |
11422 | ||
11423 | Rd = inst.operands[0].reg; | |
11424 | Rn = inst.operands[1].reg; | |
11425 | Rm = inst.operands[2].reg; | |
11426 | ||
11427 | reject_bad_reg (Rd); | |
11428 | reject_bad_reg (Rn); | |
11429 | reject_bad_reg (Rm); | |
11430 | ||
11431 | inst.instruction |= Rd << 8; | |
11432 | inst.instruction |= Rn << 16; | |
11433 | inst.instruction |= Rm; | |
c19d1205 ZW |
11434 | inst.instruction |= inst.operands[3].imm << 4; |
11435 | } | |
b99bd4ef | 11436 | |
c19d1205 ZW |
11437 | static void |
11438 | do_t_sxth (void) | |
11439 | { | |
fdfde340 JM |
11440 | unsigned Rd, Rm; |
11441 | ||
11442 | Rd = inst.operands[0].reg; | |
11443 | Rm = inst.operands[1].reg; | |
11444 | ||
11445 | reject_bad_reg (Rd); | |
11446 | reject_bad_reg (Rm); | |
c921be7d NC |
11447 | |
11448 | if (inst.instruction <= 0xffff | |
11449 | && inst.size_req != 4 | |
fdfde340 | 11450 | && Rd <= 7 && Rm <= 7 |
c19d1205 | 11451 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) |
b99bd4ef | 11452 | { |
c19d1205 | 11453 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
11454 | inst.instruction |= Rd; |
11455 | inst.instruction |= Rm << 3; | |
b99bd4ef | 11456 | } |
c19d1205 | 11457 | else if (unified_syntax) |
b99bd4ef | 11458 | { |
c19d1205 ZW |
11459 | if (inst.instruction <= 0xffff) |
11460 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
11461 | inst.instruction |= Rd << 8; |
11462 | inst.instruction |= Rm; | |
c19d1205 | 11463 | inst.instruction |= inst.operands[2].imm << 4; |
b99bd4ef | 11464 | } |
c19d1205 | 11465 | else |
b99bd4ef | 11466 | { |
c19d1205 ZW |
11467 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
11468 | _("Thumb encoding does not support rotation")); | |
11469 | constraint (1, BAD_HIREG); | |
b99bd4ef | 11470 | } |
c19d1205 | 11471 | } |
b99bd4ef | 11472 | |
c19d1205 ZW |
11473 | static void |
11474 | do_t_swi (void) | |
11475 | { | |
11476 | inst.reloc.type = BFD_RELOC_ARM_SWI; | |
11477 | } | |
b99bd4ef | 11478 | |
92e90b6e PB |
11479 | static void |
11480 | do_t_tb (void) | |
11481 | { | |
fdfde340 | 11482 | unsigned Rn, Rm; |
92e90b6e PB |
11483 | int half; |
11484 | ||
11485 | half = (inst.instruction & 0x10) != 0; | |
e07e6e58 | 11486 | set_it_insn_type_last (); |
dfa9f0d5 PB |
11487 | constraint (inst.operands[0].immisreg, |
11488 | _("instruction requires register index")); | |
fdfde340 JM |
11489 | |
11490 | Rn = inst.operands[0].reg; | |
11491 | Rm = inst.operands[0].imm; | |
c921be7d | 11492 | |
fdfde340 JM |
11493 | constraint (Rn == REG_SP, BAD_SP); |
11494 | reject_bad_reg (Rm); | |
11495 | ||
92e90b6e PB |
11496 | constraint (!half && inst.operands[0].shifted, |
11497 | _("instruction does not allow shifted index")); | |
fdfde340 | 11498 | inst.instruction |= (Rn << 16) | Rm; |
92e90b6e PB |
11499 | } |
11500 | ||
c19d1205 ZW |
11501 | static void |
11502 | do_t_usat (void) | |
11503 | { | |
3a21c15a | 11504 | do_t_ssat_usat (0); |
b99bd4ef NC |
11505 | } |
11506 | ||
11507 | static void | |
c19d1205 | 11508 | do_t_usat16 (void) |
b99bd4ef | 11509 | { |
fdfde340 JM |
11510 | unsigned Rd, Rn; |
11511 | ||
11512 | Rd = inst.operands[0].reg; | |
11513 | Rn = inst.operands[2].reg; | |
11514 | ||
11515 | reject_bad_reg (Rd); | |
11516 | reject_bad_reg (Rn); | |
11517 | ||
11518 | inst.instruction |= Rd << 8; | |
c19d1205 | 11519 | inst.instruction |= inst.operands[1].imm; |
fdfde340 | 11520 | inst.instruction |= Rn << 16; |
b99bd4ef | 11521 | } |
c19d1205 | 11522 | |
5287ad62 | 11523 | /* Neon instruction encoder helpers. */ |
5f4273c7 | 11524 | |
5287ad62 | 11525 | /* Encodings for the different types for various Neon opcodes. */ |
b99bd4ef | 11526 | |
5287ad62 JB |
11527 | /* An "invalid" code for the following tables. */ |
11528 | #define N_INV -1u | |
11529 | ||
11530 | struct neon_tab_entry | |
b99bd4ef | 11531 | { |
5287ad62 JB |
11532 | unsigned integer; |
11533 | unsigned float_or_poly; | |
11534 | unsigned scalar_or_imm; | |
11535 | }; | |
5f4273c7 | 11536 | |
5287ad62 JB |
11537 | /* Map overloaded Neon opcodes to their respective encodings. */ |
11538 | #define NEON_ENC_TAB \ | |
11539 | X(vabd, 0x0000700, 0x1200d00, N_INV), \ | |
11540 | X(vmax, 0x0000600, 0x0000f00, N_INV), \ | |
11541 | X(vmin, 0x0000610, 0x0200f00, N_INV), \ | |
11542 | X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ | |
11543 | X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ | |
11544 | X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ | |
11545 | X(vadd, 0x0000800, 0x0000d00, N_INV), \ | |
11546 | X(vsub, 0x1000800, 0x0200d00, N_INV), \ | |
11547 | X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ | |
11548 | X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ | |
11549 | X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ | |
11550 | /* Register variants of the following two instructions are encoded as | |
e07e6e58 | 11551 | vcge / vcgt with the operands reversed. */ \ |
92559b5b PB |
11552 | X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ |
11553 | X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ | |
62f3b8c8 PB |
11554 | X(vfma, N_INV, 0x0000c10, N_INV), \ |
11555 | X(vfms, N_INV, 0x0200c10, N_INV), \ | |
5287ad62 JB |
11556 | X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ |
11557 | X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ | |
11558 | X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ | |
11559 | X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ | |
11560 | X(vmlal, 0x0800800, N_INV, 0x0800240), \ | |
11561 | X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ | |
11562 | X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ | |
11563 | X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ | |
11564 | X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ | |
11565 | X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ | |
11566 | X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ | |
11567 | X(vshl, 0x0000400, N_INV, 0x0800510), \ | |
11568 | X(vqshl, 0x0000410, N_INV, 0x0800710), \ | |
11569 | X(vand, 0x0000110, N_INV, 0x0800030), \ | |
11570 | X(vbic, 0x0100110, N_INV, 0x0800030), \ | |
11571 | X(veor, 0x1000110, N_INV, N_INV), \ | |
11572 | X(vorn, 0x0300110, N_INV, 0x0800010), \ | |
11573 | X(vorr, 0x0200110, N_INV, 0x0800010), \ | |
11574 | X(vmvn, 0x1b00580, N_INV, 0x0800030), \ | |
11575 | X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ | |
11576 | X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ | |
11577 | X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ | |
11578 | X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ | |
11579 | X(vst1, 0x0000000, 0x0800000, N_INV), \ | |
11580 | X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ | |
11581 | X(vst2, 0x0000100, 0x0800100, N_INV), \ | |
11582 | X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ | |
11583 | X(vst3, 0x0000200, 0x0800200, N_INV), \ | |
11584 | X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ | |
11585 | X(vst4, 0x0000300, 0x0800300, N_INV), \ | |
11586 | X(vmovn, 0x1b20200, N_INV, N_INV), \ | |
11587 | X(vtrn, 0x1b20080, N_INV, N_INV), \ | |
11588 | X(vqmovn, 0x1b20200, N_INV, N_INV), \ | |
037e8744 JB |
11589 | X(vqmovun, 0x1b20240, N_INV, N_INV), \ |
11590 | X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ | |
e6655fda PB |
11591 | X(vnmla, 0xe100a40, 0xe100b40, N_INV), \ |
11592 | X(vnmls, 0xe100a00, 0xe100b00, N_INV), \ | |
62f3b8c8 PB |
11593 | X(vfnma, 0xe900a40, 0xe900b40, N_INV), \ |
11594 | X(vfnms, 0xe900a00, 0xe900b00, N_INV), \ | |
037e8744 JB |
11595 | X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ |
11596 | X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ | |
11597 | X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ | |
11598 | X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV) | |
5287ad62 JB |
11599 | |
11600 | enum neon_opc | |
11601 | { | |
11602 | #define X(OPC,I,F,S) N_MNEM_##OPC | |
11603 | NEON_ENC_TAB | |
11604 | #undef X | |
11605 | }; | |
b99bd4ef | 11606 | |
5287ad62 JB |
11607 | static const struct neon_tab_entry neon_enc_tab[] = |
11608 | { | |
11609 | #define X(OPC,I,F,S) { (I), (F), (S) } | |
11610 | NEON_ENC_TAB | |
11611 | #undef X | |
11612 | }; | |
b99bd4ef | 11613 | |
88714cb8 DG |
11614 | /* Do not use these macros; instead, use NEON_ENCODE defined below. */ |
11615 | #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
11616 | #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
11617 | #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
11618 | #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
11619 | #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
11620 | #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
11621 | #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
11622 | #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
11623 | #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
11624 | #define NEON_ENC_SINGLE_(X) \ | |
037e8744 | 11625 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) |
88714cb8 | 11626 | #define NEON_ENC_DOUBLE_(X) \ |
037e8744 | 11627 | ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) |
5287ad62 | 11628 | |
88714cb8 DG |
11629 | #define NEON_ENCODE(type, inst) \ |
11630 | do \ | |
11631 | { \ | |
11632 | inst.instruction = NEON_ENC_##type##_ (inst.instruction); \ | |
11633 | inst.is_neon = 1; \ | |
11634 | } \ | |
11635 | while (0) | |
11636 | ||
11637 | #define check_neon_suffixes \ | |
11638 | do \ | |
11639 | { \ | |
11640 | if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \ | |
11641 | { \ | |
11642 | as_bad (_("invalid neon suffix for non neon instruction")); \ | |
11643 | return; \ | |
11644 | } \ | |
11645 | } \ | |
11646 | while (0) | |
11647 | ||
037e8744 JB |
11648 | /* Define shapes for instruction operands. The following mnemonic characters |
11649 | are used in this table: | |
5287ad62 | 11650 | |
037e8744 | 11651 | F - VFP S<n> register |
5287ad62 JB |
11652 | D - Neon D<n> register |
11653 | Q - Neon Q<n> register | |
11654 | I - Immediate | |
11655 | S - Scalar | |
11656 | R - ARM register | |
11657 | L - D<n> register list | |
5f4273c7 | 11658 | |
037e8744 JB |
11659 | This table is used to generate various data: |
11660 | - enumerations of the form NS_DDR to be used as arguments to | |
11661 | neon_select_shape. | |
11662 | - a table classifying shapes into single, double, quad, mixed. | |
5f4273c7 | 11663 | - a table used to drive neon_select_shape. */ |
b99bd4ef | 11664 | |
037e8744 JB |
11665 | #define NEON_SHAPE_DEF \ |
11666 | X(3, (D, D, D), DOUBLE), \ | |
11667 | X(3, (Q, Q, Q), QUAD), \ | |
11668 | X(3, (D, D, I), DOUBLE), \ | |
11669 | X(3, (Q, Q, I), QUAD), \ | |
11670 | X(3, (D, D, S), DOUBLE), \ | |
11671 | X(3, (Q, Q, S), QUAD), \ | |
11672 | X(2, (D, D), DOUBLE), \ | |
11673 | X(2, (Q, Q), QUAD), \ | |
11674 | X(2, (D, S), DOUBLE), \ | |
11675 | X(2, (Q, S), QUAD), \ | |
11676 | X(2, (D, R), DOUBLE), \ | |
11677 | X(2, (Q, R), QUAD), \ | |
11678 | X(2, (D, I), DOUBLE), \ | |
11679 | X(2, (Q, I), QUAD), \ | |
11680 | X(3, (D, L, D), DOUBLE), \ | |
11681 | X(2, (D, Q), MIXED), \ | |
11682 | X(2, (Q, D), MIXED), \ | |
11683 | X(3, (D, Q, I), MIXED), \ | |
11684 | X(3, (Q, D, I), MIXED), \ | |
11685 | X(3, (Q, D, D), MIXED), \ | |
11686 | X(3, (D, Q, Q), MIXED), \ | |
11687 | X(3, (Q, Q, D), MIXED), \ | |
11688 | X(3, (Q, D, S), MIXED), \ | |
11689 | X(3, (D, Q, S), MIXED), \ | |
11690 | X(4, (D, D, D, I), DOUBLE), \ | |
11691 | X(4, (Q, Q, Q, I), QUAD), \ | |
11692 | X(2, (F, F), SINGLE), \ | |
11693 | X(3, (F, F, F), SINGLE), \ | |
11694 | X(2, (F, I), SINGLE), \ | |
11695 | X(2, (F, D), MIXED), \ | |
11696 | X(2, (D, F), MIXED), \ | |
11697 | X(3, (F, F, I), MIXED), \ | |
11698 | X(4, (R, R, F, F), SINGLE), \ | |
11699 | X(4, (F, F, R, R), SINGLE), \ | |
11700 | X(3, (D, R, R), DOUBLE), \ | |
11701 | X(3, (R, R, D), DOUBLE), \ | |
11702 | X(2, (S, R), SINGLE), \ | |
11703 | X(2, (R, S), SINGLE), \ | |
11704 | X(2, (F, R), SINGLE), \ | |
11705 | X(2, (R, F), SINGLE) | |
11706 | ||
11707 | #define S2(A,B) NS_##A##B | |
11708 | #define S3(A,B,C) NS_##A##B##C | |
11709 | #define S4(A,B,C,D) NS_##A##B##C##D | |
11710 | ||
11711 | #define X(N, L, C) S##N L | |
11712 | ||
5287ad62 JB |
11713 | enum neon_shape |
11714 | { | |
037e8744 JB |
11715 | NEON_SHAPE_DEF, |
11716 | NS_NULL | |
5287ad62 | 11717 | }; |
b99bd4ef | 11718 | |
037e8744 JB |
11719 | #undef X |
11720 | #undef S2 | |
11721 | #undef S3 | |
11722 | #undef S4 | |
11723 | ||
11724 | enum neon_shape_class | |
11725 | { | |
11726 | SC_SINGLE, | |
11727 | SC_DOUBLE, | |
11728 | SC_QUAD, | |
11729 | SC_MIXED | |
11730 | }; | |
11731 | ||
11732 | #define X(N, L, C) SC_##C | |
11733 | ||
11734 | static enum neon_shape_class neon_shape_class[] = | |
11735 | { | |
11736 | NEON_SHAPE_DEF | |
11737 | }; | |
11738 | ||
11739 | #undef X | |
11740 | ||
11741 | enum neon_shape_el | |
11742 | { | |
11743 | SE_F, | |
11744 | SE_D, | |
11745 | SE_Q, | |
11746 | SE_I, | |
11747 | SE_S, | |
11748 | SE_R, | |
11749 | SE_L | |
11750 | }; | |
11751 | ||
11752 | /* Register widths of above. */ | |
11753 | static unsigned neon_shape_el_size[] = | |
11754 | { | |
11755 | 32, | |
11756 | 64, | |
11757 | 128, | |
11758 | 0, | |
11759 | 32, | |
11760 | 32, | |
11761 | 0 | |
11762 | }; | |
11763 | ||
11764 | struct neon_shape_info | |
11765 | { | |
11766 | unsigned els; | |
11767 | enum neon_shape_el el[NEON_MAX_TYPE_ELS]; | |
11768 | }; | |
11769 | ||
11770 | #define S2(A,B) { SE_##A, SE_##B } | |
11771 | #define S3(A,B,C) { SE_##A, SE_##B, SE_##C } | |
11772 | #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } | |
11773 | ||
11774 | #define X(N, L, C) { N, S##N L } | |
11775 | ||
11776 | static struct neon_shape_info neon_shape_tab[] = | |
11777 | { | |
11778 | NEON_SHAPE_DEF | |
11779 | }; | |
11780 | ||
11781 | #undef X | |
11782 | #undef S2 | |
11783 | #undef S3 | |
11784 | #undef S4 | |
11785 | ||
5287ad62 JB |
11786 | /* Bit masks used in type checking given instructions. |
11787 | 'N_EQK' means the type must be the same as (or based on in some way) the key | |
11788 | type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is | |
11789 | set, various other bits can be set as well in order to modify the meaning of | |
11790 | the type constraint. */ | |
11791 | ||
11792 | enum neon_type_mask | |
11793 | { | |
8e79c3df CM |
11794 | N_S8 = 0x0000001, |
11795 | N_S16 = 0x0000002, | |
11796 | N_S32 = 0x0000004, | |
11797 | N_S64 = 0x0000008, | |
11798 | N_U8 = 0x0000010, | |
11799 | N_U16 = 0x0000020, | |
11800 | N_U32 = 0x0000040, | |
11801 | N_U64 = 0x0000080, | |
11802 | N_I8 = 0x0000100, | |
11803 | N_I16 = 0x0000200, | |
11804 | N_I32 = 0x0000400, | |
11805 | N_I64 = 0x0000800, | |
11806 | N_8 = 0x0001000, | |
11807 | N_16 = 0x0002000, | |
11808 | N_32 = 0x0004000, | |
11809 | N_64 = 0x0008000, | |
11810 | N_P8 = 0x0010000, | |
11811 | N_P16 = 0x0020000, | |
11812 | N_F16 = 0x0040000, | |
11813 | N_F32 = 0x0080000, | |
11814 | N_F64 = 0x0100000, | |
c921be7d NC |
11815 | N_KEY = 0x1000000, /* Key element (main type specifier). */ |
11816 | N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */ | |
8e79c3df | 11817 | N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ |
c921be7d NC |
11818 | N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */ |
11819 | N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */ | |
11820 | N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */ | |
11821 | N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */ | |
11822 | N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */ | |
11823 | N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */ | |
11824 | N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */ | |
5287ad62 | 11825 | N_UTYP = 0, |
037e8744 | 11826 | N_MAX_NONSPECIAL = N_F64 |
5287ad62 JB |
11827 | }; |
11828 | ||
dcbf9037 JB |
11829 | #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) |
11830 | ||
5287ad62 JB |
11831 | #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) |
11832 | #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) | |
11833 | #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) | |
11834 | #define N_SUF_32 (N_SU_32 | N_F32) | |
11835 | #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) | |
11836 | #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) | |
11837 | ||
11838 | /* Pass this as the first type argument to neon_check_type to ignore types | |
11839 | altogether. */ | |
11840 | #define N_IGNORE_TYPE (N_KEY | N_EQK) | |
11841 | ||
037e8744 JB |
11842 | /* Select a "shape" for the current instruction (describing register types or |
11843 | sizes) from a list of alternatives. Return NS_NULL if the current instruction | |
11844 | doesn't fit. For non-polymorphic shapes, checking is usually done as a | |
11845 | function of operand parsing, so this function doesn't need to be called. | |
11846 | Shapes should be listed in order of decreasing length. */ | |
5287ad62 JB |
11847 | |
11848 | static enum neon_shape | |
037e8744 | 11849 | neon_select_shape (enum neon_shape shape, ...) |
5287ad62 | 11850 | { |
037e8744 JB |
11851 | va_list ap; |
11852 | enum neon_shape first_shape = shape; | |
5287ad62 JB |
11853 | |
11854 | /* Fix missing optional operands. FIXME: we don't know at this point how | |
11855 | many arguments we should have, so this makes the assumption that we have | |
11856 | > 1. This is true of all current Neon opcodes, I think, but may not be | |
11857 | true in the future. */ | |
11858 | if (!inst.operands[1].present) | |
11859 | inst.operands[1] = inst.operands[0]; | |
11860 | ||
037e8744 | 11861 | va_start (ap, shape); |
5f4273c7 | 11862 | |
21d799b5 | 11863 | for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int)) |
037e8744 JB |
11864 | { |
11865 | unsigned j; | |
11866 | int matches = 1; | |
11867 | ||
11868 | for (j = 0; j < neon_shape_tab[shape].els; j++) | |
11869 | { | |
11870 | if (!inst.operands[j].present) | |
11871 | { | |
11872 | matches = 0; | |
11873 | break; | |
11874 | } | |
11875 | ||
11876 | switch (neon_shape_tab[shape].el[j]) | |
11877 | { | |
11878 | case SE_F: | |
11879 | if (!(inst.operands[j].isreg | |
11880 | && inst.operands[j].isvec | |
11881 | && inst.operands[j].issingle | |
11882 | && !inst.operands[j].isquad)) | |
11883 | matches = 0; | |
11884 | break; | |
11885 | ||
11886 | case SE_D: | |
11887 | if (!(inst.operands[j].isreg | |
11888 | && inst.operands[j].isvec | |
11889 | && !inst.operands[j].isquad | |
11890 | && !inst.operands[j].issingle)) | |
11891 | matches = 0; | |
11892 | break; | |
11893 | ||
11894 | case SE_R: | |
11895 | if (!(inst.operands[j].isreg | |
11896 | && !inst.operands[j].isvec)) | |
11897 | matches = 0; | |
11898 | break; | |
11899 | ||
11900 | case SE_Q: | |
11901 | if (!(inst.operands[j].isreg | |
11902 | && inst.operands[j].isvec | |
11903 | && inst.operands[j].isquad | |
11904 | && !inst.operands[j].issingle)) | |
11905 | matches = 0; | |
11906 | break; | |
11907 | ||
11908 | case SE_I: | |
11909 | if (!(!inst.operands[j].isreg | |
11910 | && !inst.operands[j].isscalar)) | |
11911 | matches = 0; | |
11912 | break; | |
11913 | ||
11914 | case SE_S: | |
11915 | if (!(!inst.operands[j].isreg | |
11916 | && inst.operands[j].isscalar)) | |
11917 | matches = 0; | |
11918 | break; | |
11919 | ||
11920 | case SE_L: | |
11921 | break; | |
11922 | } | |
3fde54a2 JZ |
11923 | if (!matches) |
11924 | break; | |
037e8744 JB |
11925 | } |
11926 | if (matches) | |
5287ad62 | 11927 | break; |
037e8744 | 11928 | } |
5f4273c7 | 11929 | |
037e8744 | 11930 | va_end (ap); |
5287ad62 | 11931 | |
037e8744 JB |
11932 | if (shape == NS_NULL && first_shape != NS_NULL) |
11933 | first_error (_("invalid instruction shape")); | |
5287ad62 | 11934 | |
037e8744 JB |
11935 | return shape; |
11936 | } | |
5287ad62 | 11937 | |
037e8744 JB |
11938 | /* True if SHAPE is predominantly a quadword operation (most of the time, this |
11939 | means the Q bit should be set). */ | |
11940 | ||
11941 | static int | |
11942 | neon_quad (enum neon_shape shape) | |
11943 | { | |
11944 | return neon_shape_class[shape] == SC_QUAD; | |
5287ad62 | 11945 | } |
037e8744 | 11946 | |
5287ad62 JB |
11947 | static void |
11948 | neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, | |
11949 | unsigned *g_size) | |
11950 | { | |
11951 | /* Allow modification to be made to types which are constrained to be | |
11952 | based on the key element, based on bits set alongside N_EQK. */ | |
11953 | if ((typebits & N_EQK) != 0) | |
11954 | { | |
11955 | if ((typebits & N_HLF) != 0) | |
11956 | *g_size /= 2; | |
11957 | else if ((typebits & N_DBL) != 0) | |
11958 | *g_size *= 2; | |
11959 | if ((typebits & N_SGN) != 0) | |
11960 | *g_type = NT_signed; | |
11961 | else if ((typebits & N_UNS) != 0) | |
11962 | *g_type = NT_unsigned; | |
11963 | else if ((typebits & N_INT) != 0) | |
11964 | *g_type = NT_integer; | |
11965 | else if ((typebits & N_FLT) != 0) | |
11966 | *g_type = NT_float; | |
dcbf9037 JB |
11967 | else if ((typebits & N_SIZ) != 0) |
11968 | *g_type = NT_untyped; | |
5287ad62 JB |
11969 | } |
11970 | } | |
5f4273c7 | 11971 | |
5287ad62 JB |
11972 | /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" |
11973 | operand type, i.e. the single type specified in a Neon instruction when it | |
11974 | is the only one given. */ | |
11975 | ||
11976 | static struct neon_type_el | |
11977 | neon_type_promote (struct neon_type_el *key, unsigned thisarg) | |
11978 | { | |
11979 | struct neon_type_el dest = *key; | |
5f4273c7 | 11980 | |
9c2799c2 | 11981 | gas_assert ((thisarg & N_EQK) != 0); |
5f4273c7 | 11982 | |
5287ad62 JB |
11983 | neon_modify_type_size (thisarg, &dest.type, &dest.size); |
11984 | ||
11985 | return dest; | |
11986 | } | |
11987 | ||
11988 | /* Convert Neon type and size into compact bitmask representation. */ | |
11989 | ||
11990 | static enum neon_type_mask | |
11991 | type_chk_of_el_type (enum neon_el_type type, unsigned size) | |
11992 | { | |
11993 | switch (type) | |
11994 | { | |
11995 | case NT_untyped: | |
11996 | switch (size) | |
11997 | { | |
11998 | case 8: return N_8; | |
11999 | case 16: return N_16; | |
12000 | case 32: return N_32; | |
12001 | case 64: return N_64; | |
12002 | default: ; | |
12003 | } | |
12004 | break; | |
12005 | ||
12006 | case NT_integer: | |
12007 | switch (size) | |
12008 | { | |
12009 | case 8: return N_I8; | |
12010 | case 16: return N_I16; | |
12011 | case 32: return N_I32; | |
12012 | case 64: return N_I64; | |
12013 | default: ; | |
12014 | } | |
12015 | break; | |
12016 | ||
12017 | case NT_float: | |
037e8744 JB |
12018 | switch (size) |
12019 | { | |
8e79c3df | 12020 | case 16: return N_F16; |
037e8744 JB |
12021 | case 32: return N_F32; |
12022 | case 64: return N_F64; | |
12023 | default: ; | |
12024 | } | |
5287ad62 JB |
12025 | break; |
12026 | ||
12027 | case NT_poly: | |
12028 | switch (size) | |
12029 | { | |
12030 | case 8: return N_P8; | |
12031 | case 16: return N_P16; | |
12032 | default: ; | |
12033 | } | |
12034 | break; | |
12035 | ||
12036 | case NT_signed: | |
12037 | switch (size) | |
12038 | { | |
12039 | case 8: return N_S8; | |
12040 | case 16: return N_S16; | |
12041 | case 32: return N_S32; | |
12042 | case 64: return N_S64; | |
12043 | default: ; | |
12044 | } | |
12045 | break; | |
12046 | ||
12047 | case NT_unsigned: | |
12048 | switch (size) | |
12049 | { | |
12050 | case 8: return N_U8; | |
12051 | case 16: return N_U16; | |
12052 | case 32: return N_U32; | |
12053 | case 64: return N_U64; | |
12054 | default: ; | |
12055 | } | |
12056 | break; | |
12057 | ||
12058 | default: ; | |
12059 | } | |
5f4273c7 | 12060 | |
5287ad62 JB |
12061 | return N_UTYP; |
12062 | } | |
12063 | ||
12064 | /* Convert compact Neon bitmask type representation to a type and size. Only | |
12065 | handles the case where a single bit is set in the mask. */ | |
12066 | ||
dcbf9037 | 12067 | static int |
5287ad62 JB |
12068 | el_type_of_type_chk (enum neon_el_type *type, unsigned *size, |
12069 | enum neon_type_mask mask) | |
12070 | { | |
dcbf9037 JB |
12071 | if ((mask & N_EQK) != 0) |
12072 | return FAIL; | |
12073 | ||
5287ad62 JB |
12074 | if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) |
12075 | *size = 8; | |
dcbf9037 | 12076 | else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0) |
5287ad62 | 12077 | *size = 16; |
dcbf9037 | 12078 | else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) |
5287ad62 | 12079 | *size = 32; |
037e8744 | 12080 | else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0) |
5287ad62 | 12081 | *size = 64; |
dcbf9037 JB |
12082 | else |
12083 | return FAIL; | |
12084 | ||
5287ad62 JB |
12085 | if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) |
12086 | *type = NT_signed; | |
dcbf9037 | 12087 | else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) |
5287ad62 | 12088 | *type = NT_unsigned; |
dcbf9037 | 12089 | else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) |
5287ad62 | 12090 | *type = NT_integer; |
dcbf9037 | 12091 | else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) |
5287ad62 | 12092 | *type = NT_untyped; |
dcbf9037 | 12093 | else if ((mask & (N_P8 | N_P16)) != 0) |
5287ad62 | 12094 | *type = NT_poly; |
037e8744 | 12095 | else if ((mask & (N_F32 | N_F64)) != 0) |
5287ad62 | 12096 | *type = NT_float; |
dcbf9037 JB |
12097 | else |
12098 | return FAIL; | |
5f4273c7 | 12099 | |
dcbf9037 | 12100 | return SUCCESS; |
5287ad62 JB |
12101 | } |
12102 | ||
12103 | /* Modify a bitmask of allowed types. This is only needed for type | |
12104 | relaxation. */ | |
12105 | ||
12106 | static unsigned | |
12107 | modify_types_allowed (unsigned allowed, unsigned mods) | |
12108 | { | |
12109 | unsigned size; | |
12110 | enum neon_el_type type; | |
12111 | unsigned destmask; | |
12112 | int i; | |
5f4273c7 | 12113 | |
5287ad62 | 12114 | destmask = 0; |
5f4273c7 | 12115 | |
5287ad62 JB |
12116 | for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) |
12117 | { | |
21d799b5 NC |
12118 | if (el_type_of_type_chk (&type, &size, |
12119 | (enum neon_type_mask) (allowed & i)) == SUCCESS) | |
dcbf9037 JB |
12120 | { |
12121 | neon_modify_type_size (mods, &type, &size); | |
12122 | destmask |= type_chk_of_el_type (type, size); | |
12123 | } | |
5287ad62 | 12124 | } |
5f4273c7 | 12125 | |
5287ad62 JB |
12126 | return destmask; |
12127 | } | |
12128 | ||
12129 | /* Check type and return type classification. | |
12130 | The manual states (paraphrase): If one datatype is given, it indicates the | |
12131 | type given in: | |
12132 | - the second operand, if there is one | |
12133 | - the operand, if there is no second operand | |
12134 | - the result, if there are no operands. | |
12135 | This isn't quite good enough though, so we use a concept of a "key" datatype | |
12136 | which is set on a per-instruction basis, which is the one which matters when | |
12137 | only one data type is written. | |
12138 | Note: this function has side-effects (e.g. filling in missing operands). All | |
037e8744 | 12139 | Neon instructions should call it before performing bit encoding. */ |
5287ad62 JB |
12140 | |
12141 | static struct neon_type_el | |
12142 | neon_check_type (unsigned els, enum neon_shape ns, ...) | |
12143 | { | |
12144 | va_list ap; | |
12145 | unsigned i, pass, key_el = 0; | |
12146 | unsigned types[NEON_MAX_TYPE_ELS]; | |
12147 | enum neon_el_type k_type = NT_invtype; | |
12148 | unsigned k_size = -1u; | |
12149 | struct neon_type_el badtype = {NT_invtype, -1}; | |
12150 | unsigned key_allowed = 0; | |
12151 | ||
12152 | /* Optional registers in Neon instructions are always (not) in operand 1. | |
12153 | Fill in the missing operand here, if it was omitted. */ | |
12154 | if (els > 1 && !inst.operands[1].present) | |
12155 | inst.operands[1] = inst.operands[0]; | |
12156 | ||
12157 | /* Suck up all the varargs. */ | |
12158 | va_start (ap, ns); | |
12159 | for (i = 0; i < els; i++) | |
12160 | { | |
12161 | unsigned thisarg = va_arg (ap, unsigned); | |
12162 | if (thisarg == N_IGNORE_TYPE) | |
12163 | { | |
12164 | va_end (ap); | |
12165 | return badtype; | |
12166 | } | |
12167 | types[i] = thisarg; | |
12168 | if ((thisarg & N_KEY) != 0) | |
12169 | key_el = i; | |
12170 | } | |
12171 | va_end (ap); | |
12172 | ||
dcbf9037 JB |
12173 | if (inst.vectype.elems > 0) |
12174 | for (i = 0; i < els; i++) | |
12175 | if (inst.operands[i].vectype.type != NT_invtype) | |
12176 | { | |
12177 | first_error (_("types specified in both the mnemonic and operands")); | |
12178 | return badtype; | |
12179 | } | |
12180 | ||
5287ad62 JB |
12181 | /* Duplicate inst.vectype elements here as necessary. |
12182 | FIXME: No idea if this is exactly the same as the ARM assembler, | |
12183 | particularly when an insn takes one register and one non-register | |
12184 | operand. */ | |
12185 | if (inst.vectype.elems == 1 && els > 1) | |
12186 | { | |
12187 | unsigned j; | |
12188 | inst.vectype.elems = els; | |
12189 | inst.vectype.el[key_el] = inst.vectype.el[0]; | |
12190 | for (j = 0; j < els; j++) | |
dcbf9037 JB |
12191 | if (j != key_el) |
12192 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
12193 | types[j]); | |
12194 | } | |
12195 | else if (inst.vectype.elems == 0 && els > 0) | |
12196 | { | |
12197 | unsigned j; | |
12198 | /* No types were given after the mnemonic, so look for types specified | |
12199 | after each operand. We allow some flexibility here; as long as the | |
12200 | "key" operand has a type, we can infer the others. */ | |
12201 | for (j = 0; j < els; j++) | |
12202 | if (inst.operands[j].vectype.type != NT_invtype) | |
12203 | inst.vectype.el[j] = inst.operands[j].vectype; | |
12204 | ||
12205 | if (inst.operands[key_el].vectype.type != NT_invtype) | |
5287ad62 | 12206 | { |
dcbf9037 JB |
12207 | for (j = 0; j < els; j++) |
12208 | if (inst.operands[j].vectype.type == NT_invtype) | |
12209 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
12210 | types[j]); | |
12211 | } | |
12212 | else | |
12213 | { | |
12214 | first_error (_("operand types can't be inferred")); | |
12215 | return badtype; | |
5287ad62 JB |
12216 | } |
12217 | } | |
12218 | else if (inst.vectype.elems != els) | |
12219 | { | |
dcbf9037 | 12220 | first_error (_("type specifier has the wrong number of parts")); |
5287ad62 JB |
12221 | return badtype; |
12222 | } | |
12223 | ||
12224 | for (pass = 0; pass < 2; pass++) | |
12225 | { | |
12226 | for (i = 0; i < els; i++) | |
12227 | { | |
12228 | unsigned thisarg = types[i]; | |
12229 | unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) | |
12230 | ? modify_types_allowed (key_allowed, thisarg) : thisarg; | |
12231 | enum neon_el_type g_type = inst.vectype.el[i].type; | |
12232 | unsigned g_size = inst.vectype.el[i].size; | |
12233 | ||
12234 | /* Decay more-specific signed & unsigned types to sign-insensitive | |
12235 | integer types if sign-specific variants are unavailable. */ | |
12236 | if ((g_type == NT_signed || g_type == NT_unsigned) | |
12237 | && (types_allowed & N_SU_ALL) == 0) | |
12238 | g_type = NT_integer; | |
12239 | ||
12240 | /* If only untyped args are allowed, decay any more specific types to | |
12241 | them. Some instructions only care about signs for some element | |
12242 | sizes, so handle that properly. */ | |
12243 | if ((g_size == 8 && (types_allowed & N_8) != 0) | |
12244 | || (g_size == 16 && (types_allowed & N_16) != 0) | |
12245 | || (g_size == 32 && (types_allowed & N_32) != 0) | |
12246 | || (g_size == 64 && (types_allowed & N_64) != 0)) | |
12247 | g_type = NT_untyped; | |
12248 | ||
12249 | if (pass == 0) | |
12250 | { | |
12251 | if ((thisarg & N_KEY) != 0) | |
12252 | { | |
12253 | k_type = g_type; | |
12254 | k_size = g_size; | |
12255 | key_allowed = thisarg & ~N_KEY; | |
12256 | } | |
12257 | } | |
12258 | else | |
12259 | { | |
037e8744 JB |
12260 | if ((thisarg & N_VFP) != 0) |
12261 | { | |
99b253c5 NC |
12262 | enum neon_shape_el regshape; |
12263 | unsigned regwidth, match; | |
12264 | ||
12265 | /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */ | |
12266 | if (ns == NS_NULL) | |
12267 | { | |
12268 | first_error (_("invalid instruction shape")); | |
12269 | return badtype; | |
12270 | } | |
12271 | regshape = neon_shape_tab[ns].el[i]; | |
12272 | regwidth = neon_shape_el_size[regshape]; | |
037e8744 JB |
12273 | |
12274 | /* In VFP mode, operands must match register widths. If we | |
12275 | have a key operand, use its width, else use the width of | |
12276 | the current operand. */ | |
12277 | if (k_size != -1u) | |
12278 | match = k_size; | |
12279 | else | |
12280 | match = g_size; | |
12281 | ||
12282 | if (regwidth != match) | |
12283 | { | |
12284 | first_error (_("operand size must match register width")); | |
12285 | return badtype; | |
12286 | } | |
12287 | } | |
5f4273c7 | 12288 | |
5287ad62 JB |
12289 | if ((thisarg & N_EQK) == 0) |
12290 | { | |
12291 | unsigned given_type = type_chk_of_el_type (g_type, g_size); | |
12292 | ||
12293 | if ((given_type & types_allowed) == 0) | |
12294 | { | |
dcbf9037 | 12295 | first_error (_("bad type in Neon instruction")); |
5287ad62 JB |
12296 | return badtype; |
12297 | } | |
12298 | } | |
12299 | else | |
12300 | { | |
12301 | enum neon_el_type mod_k_type = k_type; | |
12302 | unsigned mod_k_size = k_size; | |
12303 | neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); | |
12304 | if (g_type != mod_k_type || g_size != mod_k_size) | |
12305 | { | |
dcbf9037 | 12306 | first_error (_("inconsistent types in Neon instruction")); |
5287ad62 JB |
12307 | return badtype; |
12308 | } | |
12309 | } | |
12310 | } | |
12311 | } | |
12312 | } | |
12313 | ||
12314 | return inst.vectype.el[key_el]; | |
12315 | } | |
12316 | ||
037e8744 | 12317 | /* Neon-style VFP instruction forwarding. */ |
5287ad62 | 12318 | |
037e8744 JB |
12319 | /* Thumb VFP instructions have 0xE in the condition field. */ |
12320 | ||
12321 | static void | |
12322 | do_vfp_cond_or_thumb (void) | |
5287ad62 | 12323 | { |
88714cb8 DG |
12324 | inst.is_neon = 1; |
12325 | ||
5287ad62 | 12326 | if (thumb_mode) |
037e8744 | 12327 | inst.instruction |= 0xe0000000; |
5287ad62 | 12328 | else |
037e8744 | 12329 | inst.instruction |= inst.cond << 28; |
5287ad62 JB |
12330 | } |
12331 | ||
037e8744 JB |
12332 | /* Look up and encode a simple mnemonic, for use as a helper function for the |
12333 | Neon-style VFP syntax. This avoids duplication of bits of the insns table, | |
12334 | etc. It is assumed that operand parsing has already been done, and that the | |
12335 | operands are in the form expected by the given opcode (this isn't necessarily | |
12336 | the same as the form in which they were parsed, hence some massaging must | |
12337 | take place before this function is called). | |
12338 | Checks current arch version against that in the looked-up opcode. */ | |
5287ad62 | 12339 | |
037e8744 JB |
12340 | static void |
12341 | do_vfp_nsyn_opcode (const char *opname) | |
5287ad62 | 12342 | { |
037e8744 | 12343 | const struct asm_opcode *opcode; |
5f4273c7 | 12344 | |
21d799b5 | 12345 | opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname); |
5287ad62 | 12346 | |
037e8744 JB |
12347 | if (!opcode) |
12348 | abort (); | |
5287ad62 | 12349 | |
037e8744 JB |
12350 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, |
12351 | thumb_mode ? *opcode->tvariant : *opcode->avariant), | |
12352 | _(BAD_FPU)); | |
5287ad62 | 12353 | |
88714cb8 DG |
12354 | inst.is_neon = 1; |
12355 | ||
037e8744 JB |
12356 | if (thumb_mode) |
12357 | { | |
12358 | inst.instruction = opcode->tvalue; | |
12359 | opcode->tencode (); | |
12360 | } | |
12361 | else | |
12362 | { | |
12363 | inst.instruction = (inst.cond << 28) | opcode->avalue; | |
12364 | opcode->aencode (); | |
12365 | } | |
12366 | } | |
5287ad62 JB |
12367 | |
12368 | static void | |
037e8744 | 12369 | do_vfp_nsyn_add_sub (enum neon_shape rs) |
5287ad62 | 12370 | { |
037e8744 JB |
12371 | int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; |
12372 | ||
12373 | if (rs == NS_FFF) | |
12374 | { | |
12375 | if (is_add) | |
12376 | do_vfp_nsyn_opcode ("fadds"); | |
12377 | else | |
12378 | do_vfp_nsyn_opcode ("fsubs"); | |
12379 | } | |
12380 | else | |
12381 | { | |
12382 | if (is_add) | |
12383 | do_vfp_nsyn_opcode ("faddd"); | |
12384 | else | |
12385 | do_vfp_nsyn_opcode ("fsubd"); | |
12386 | } | |
12387 | } | |
12388 | ||
12389 | /* Check operand types to see if this is a VFP instruction, and if so call | |
12390 | PFN (). */ | |
12391 | ||
12392 | static int | |
12393 | try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) | |
12394 | { | |
12395 | enum neon_shape rs; | |
12396 | struct neon_type_el et; | |
12397 | ||
12398 | switch (args) | |
12399 | { | |
12400 | case 2: | |
12401 | rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
12402 | et = neon_check_type (2, rs, | |
12403 | N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
12404 | break; | |
5f4273c7 | 12405 | |
037e8744 JB |
12406 | case 3: |
12407 | rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
12408 | et = neon_check_type (3, rs, | |
12409 | N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
12410 | break; | |
12411 | ||
12412 | default: | |
12413 | abort (); | |
12414 | } | |
12415 | ||
12416 | if (et.type != NT_invtype) | |
12417 | { | |
12418 | pfn (rs); | |
12419 | return SUCCESS; | |
12420 | } | |
037e8744 | 12421 | |
99b253c5 | 12422 | inst.error = NULL; |
037e8744 JB |
12423 | return FAIL; |
12424 | } | |
12425 | ||
12426 | static void | |
12427 | do_vfp_nsyn_mla_mls (enum neon_shape rs) | |
12428 | { | |
12429 | int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; | |
5f4273c7 | 12430 | |
037e8744 JB |
12431 | if (rs == NS_FFF) |
12432 | { | |
12433 | if (is_mla) | |
12434 | do_vfp_nsyn_opcode ("fmacs"); | |
12435 | else | |
1ee69515 | 12436 | do_vfp_nsyn_opcode ("fnmacs"); |
037e8744 JB |
12437 | } |
12438 | else | |
12439 | { | |
12440 | if (is_mla) | |
12441 | do_vfp_nsyn_opcode ("fmacd"); | |
12442 | else | |
1ee69515 | 12443 | do_vfp_nsyn_opcode ("fnmacd"); |
037e8744 JB |
12444 | } |
12445 | } | |
12446 | ||
62f3b8c8 PB |
12447 | static void |
12448 | do_vfp_nsyn_fma_fms (enum neon_shape rs) | |
12449 | { | |
12450 | int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma; | |
12451 | ||
12452 | if (rs == NS_FFF) | |
12453 | { | |
12454 | if (is_fma) | |
12455 | do_vfp_nsyn_opcode ("ffmas"); | |
12456 | else | |
12457 | do_vfp_nsyn_opcode ("ffnmas"); | |
12458 | } | |
12459 | else | |
12460 | { | |
12461 | if (is_fma) | |
12462 | do_vfp_nsyn_opcode ("ffmad"); | |
12463 | else | |
12464 | do_vfp_nsyn_opcode ("ffnmad"); | |
12465 | } | |
12466 | } | |
12467 | ||
037e8744 JB |
12468 | static void |
12469 | do_vfp_nsyn_mul (enum neon_shape rs) | |
12470 | { | |
12471 | if (rs == NS_FFF) | |
12472 | do_vfp_nsyn_opcode ("fmuls"); | |
12473 | else | |
12474 | do_vfp_nsyn_opcode ("fmuld"); | |
12475 | } | |
12476 | ||
12477 | static void | |
12478 | do_vfp_nsyn_abs_neg (enum neon_shape rs) | |
12479 | { | |
12480 | int is_neg = (inst.instruction & 0x80) != 0; | |
12481 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); | |
12482 | ||
12483 | if (rs == NS_FF) | |
12484 | { | |
12485 | if (is_neg) | |
12486 | do_vfp_nsyn_opcode ("fnegs"); | |
12487 | else | |
12488 | do_vfp_nsyn_opcode ("fabss"); | |
12489 | } | |
12490 | else | |
12491 | { | |
12492 | if (is_neg) | |
12493 | do_vfp_nsyn_opcode ("fnegd"); | |
12494 | else | |
12495 | do_vfp_nsyn_opcode ("fabsd"); | |
12496 | } | |
12497 | } | |
12498 | ||
12499 | /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision | |
12500 | insns belong to Neon, and are handled elsewhere. */ | |
12501 | ||
12502 | static void | |
12503 | do_vfp_nsyn_ldm_stm (int is_dbmode) | |
12504 | { | |
12505 | int is_ldm = (inst.instruction & (1 << 20)) != 0; | |
12506 | if (is_ldm) | |
12507 | { | |
12508 | if (is_dbmode) | |
12509 | do_vfp_nsyn_opcode ("fldmdbs"); | |
12510 | else | |
12511 | do_vfp_nsyn_opcode ("fldmias"); | |
12512 | } | |
12513 | else | |
12514 | { | |
12515 | if (is_dbmode) | |
12516 | do_vfp_nsyn_opcode ("fstmdbs"); | |
12517 | else | |
12518 | do_vfp_nsyn_opcode ("fstmias"); | |
12519 | } | |
12520 | } | |
12521 | ||
037e8744 JB |
12522 | static void |
12523 | do_vfp_nsyn_sqrt (void) | |
12524 | { | |
12525 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
12526 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12527 | |
037e8744 JB |
12528 | if (rs == NS_FF) |
12529 | do_vfp_nsyn_opcode ("fsqrts"); | |
12530 | else | |
12531 | do_vfp_nsyn_opcode ("fsqrtd"); | |
12532 | } | |
12533 | ||
12534 | static void | |
12535 | do_vfp_nsyn_div (void) | |
12536 | { | |
12537 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
12538 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
12539 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12540 | |
037e8744 JB |
12541 | if (rs == NS_FFF) |
12542 | do_vfp_nsyn_opcode ("fdivs"); | |
12543 | else | |
12544 | do_vfp_nsyn_opcode ("fdivd"); | |
12545 | } | |
12546 | ||
12547 | static void | |
12548 | do_vfp_nsyn_nmul (void) | |
12549 | { | |
12550 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
12551 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
12552 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12553 | |
037e8744 JB |
12554 | if (rs == NS_FFF) |
12555 | { | |
88714cb8 | 12556 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
12557 | do_vfp_sp_dyadic (); |
12558 | } | |
12559 | else | |
12560 | { | |
88714cb8 | 12561 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
12562 | do_vfp_dp_rd_rn_rm (); |
12563 | } | |
12564 | do_vfp_cond_or_thumb (); | |
12565 | } | |
12566 | ||
12567 | static void | |
12568 | do_vfp_nsyn_cmp (void) | |
12569 | { | |
12570 | if (inst.operands[1].isreg) | |
12571 | { | |
12572 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
12573 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12574 | |
037e8744 JB |
12575 | if (rs == NS_FF) |
12576 | { | |
88714cb8 | 12577 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
12578 | do_vfp_sp_monadic (); |
12579 | } | |
12580 | else | |
12581 | { | |
88714cb8 | 12582 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
12583 | do_vfp_dp_rd_rm (); |
12584 | } | |
12585 | } | |
12586 | else | |
12587 | { | |
12588 | enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); | |
12589 | neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); | |
12590 | ||
12591 | switch (inst.instruction & 0x0fffffff) | |
12592 | { | |
12593 | case N_MNEM_vcmp: | |
12594 | inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; | |
12595 | break; | |
12596 | case N_MNEM_vcmpe: | |
12597 | inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; | |
12598 | break; | |
12599 | default: | |
12600 | abort (); | |
12601 | } | |
5f4273c7 | 12602 | |
037e8744 JB |
12603 | if (rs == NS_FI) |
12604 | { | |
88714cb8 | 12605 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
12606 | do_vfp_sp_compare_z (); |
12607 | } | |
12608 | else | |
12609 | { | |
88714cb8 | 12610 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
12611 | do_vfp_dp_rd (); |
12612 | } | |
12613 | } | |
12614 | do_vfp_cond_or_thumb (); | |
12615 | } | |
12616 | ||
12617 | static void | |
12618 | nsyn_insert_sp (void) | |
12619 | { | |
12620 | inst.operands[1] = inst.operands[0]; | |
12621 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
fdfde340 | 12622 | inst.operands[0].reg = REG_SP; |
037e8744 JB |
12623 | inst.operands[0].isreg = 1; |
12624 | inst.operands[0].writeback = 1; | |
12625 | inst.operands[0].present = 1; | |
12626 | } | |
12627 | ||
12628 | static void | |
12629 | do_vfp_nsyn_push (void) | |
12630 | { | |
12631 | nsyn_insert_sp (); | |
12632 | if (inst.operands[1].issingle) | |
12633 | do_vfp_nsyn_opcode ("fstmdbs"); | |
12634 | else | |
12635 | do_vfp_nsyn_opcode ("fstmdbd"); | |
12636 | } | |
12637 | ||
12638 | static void | |
12639 | do_vfp_nsyn_pop (void) | |
12640 | { | |
12641 | nsyn_insert_sp (); | |
12642 | if (inst.operands[1].issingle) | |
22b5b651 | 12643 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 | 12644 | else |
22b5b651 | 12645 | do_vfp_nsyn_opcode ("fldmiad"); |
037e8744 JB |
12646 | } |
12647 | ||
12648 | /* Fix up Neon data-processing instructions, ORing in the correct bits for | |
12649 | ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ | |
12650 | ||
88714cb8 DG |
12651 | static void |
12652 | neon_dp_fixup (struct arm_it* insn) | |
037e8744 | 12653 | { |
88714cb8 DG |
12654 | unsigned int i = insn->instruction; |
12655 | insn->is_neon = 1; | |
12656 | ||
037e8744 JB |
12657 | if (thumb_mode) |
12658 | { | |
12659 | /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ | |
12660 | if (i & (1 << 24)) | |
12661 | i |= 1 << 28; | |
5f4273c7 | 12662 | |
037e8744 | 12663 | i &= ~(1 << 24); |
5f4273c7 | 12664 | |
037e8744 JB |
12665 | i |= 0xef000000; |
12666 | } | |
12667 | else | |
12668 | i |= 0xf2000000; | |
5f4273c7 | 12669 | |
88714cb8 | 12670 | insn->instruction = i; |
037e8744 JB |
12671 | } |
12672 | ||
12673 | /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 | |
12674 | (0, 1, 2, 3). */ | |
12675 | ||
12676 | static unsigned | |
12677 | neon_logbits (unsigned x) | |
12678 | { | |
12679 | return ffs (x) - 4; | |
12680 | } | |
12681 | ||
12682 | #define LOW4(R) ((R) & 0xf) | |
12683 | #define HI1(R) (((R) >> 4) & 1) | |
12684 | ||
12685 | /* Encode insns with bit pattern: | |
12686 | ||
12687 | |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
12688 | | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | | |
5f4273c7 | 12689 | |
037e8744 JB |
12690 | SIZE is passed in bits. -1 means size field isn't changed, in case it has a |
12691 | different meaning for some instruction. */ | |
12692 | ||
12693 | static void | |
12694 | neon_three_same (int isquad, int ubit, int size) | |
12695 | { | |
12696 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12697 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12698 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
12699 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
12700 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
12701 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
12702 | inst.instruction |= (isquad != 0) << 6; | |
12703 | inst.instruction |= (ubit != 0) << 24; | |
12704 | if (size != -1) | |
12705 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 12706 | |
88714cb8 | 12707 | neon_dp_fixup (&inst); |
037e8744 JB |
12708 | } |
12709 | ||
12710 | /* Encode instructions of the form: | |
12711 | ||
12712 | |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| | |
12713 | | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | | |
5287ad62 JB |
12714 | |
12715 | Don't write size if SIZE == -1. */ | |
12716 | ||
12717 | static void | |
12718 | neon_two_same (int qbit, int ubit, int size) | |
12719 | { | |
12720 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12721 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12722 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
12723 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
12724 | inst.instruction |= (qbit != 0) << 6; | |
12725 | inst.instruction |= (ubit != 0) << 24; | |
12726 | ||
12727 | if (size != -1) | |
12728 | inst.instruction |= neon_logbits (size) << 18; | |
12729 | ||
88714cb8 | 12730 | neon_dp_fixup (&inst); |
5287ad62 JB |
12731 | } |
12732 | ||
12733 | /* Neon instruction encoders, in approximate order of appearance. */ | |
12734 | ||
12735 | static void | |
12736 | do_neon_dyadic_i_su (void) | |
12737 | { | |
037e8744 | 12738 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12739 | struct neon_type_el et = neon_check_type (3, rs, |
12740 | N_EQK, N_EQK, N_SU_32 | N_KEY); | |
037e8744 | 12741 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
12742 | } |
12743 | ||
12744 | static void | |
12745 | do_neon_dyadic_i64_su (void) | |
12746 | { | |
037e8744 | 12747 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12748 | struct neon_type_el et = neon_check_type (3, rs, |
12749 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
037e8744 | 12750 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
12751 | } |
12752 | ||
12753 | static void | |
12754 | neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, | |
12755 | unsigned immbits) | |
12756 | { | |
12757 | unsigned size = et.size >> 3; | |
12758 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12759 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12760 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
12761 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
12762 | inst.instruction |= (isquad != 0) << 6; | |
12763 | inst.instruction |= immbits << 16; | |
12764 | inst.instruction |= (size >> 3) << 7; | |
12765 | inst.instruction |= (size & 0x7) << 19; | |
12766 | if (write_ubit) | |
12767 | inst.instruction |= (uval != 0) << 24; | |
12768 | ||
88714cb8 | 12769 | neon_dp_fixup (&inst); |
5287ad62 JB |
12770 | } |
12771 | ||
12772 | static void | |
12773 | do_neon_shl_imm (void) | |
12774 | { | |
12775 | if (!inst.operands[2].isreg) | |
12776 | { | |
037e8744 | 12777 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 12778 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); |
88714cb8 | 12779 | NEON_ENCODE (IMMED, inst); |
037e8744 | 12780 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm); |
5287ad62 JB |
12781 | } |
12782 | else | |
12783 | { | |
037e8744 | 12784 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12785 | struct neon_type_el et = neon_check_type (3, rs, |
12786 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
627907b7 JB |
12787 | unsigned int tmp; |
12788 | ||
12789 | /* VSHL/VQSHL 3-register variants have syntax such as: | |
12790 | vshl.xx Dd, Dm, Dn | |
12791 | whereas other 3-register operations encoded by neon_three_same have | |
12792 | syntax like: | |
12793 | vadd.xx Dd, Dn, Dm | |
12794 | (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg | |
12795 | here. */ | |
12796 | tmp = inst.operands[2].reg; | |
12797 | inst.operands[2].reg = inst.operands[1].reg; | |
12798 | inst.operands[1].reg = tmp; | |
88714cb8 | 12799 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 12800 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
12801 | } |
12802 | } | |
12803 | ||
12804 | static void | |
12805 | do_neon_qshl_imm (void) | |
12806 | { | |
12807 | if (!inst.operands[2].isreg) | |
12808 | { | |
037e8744 | 12809 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 12810 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
627907b7 | 12811 | |
88714cb8 | 12812 | NEON_ENCODE (IMMED, inst); |
037e8744 | 12813 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
12814 | inst.operands[2].imm); |
12815 | } | |
12816 | else | |
12817 | { | |
037e8744 | 12818 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12819 | struct neon_type_el et = neon_check_type (3, rs, |
12820 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
627907b7 JB |
12821 | unsigned int tmp; |
12822 | ||
12823 | /* See note in do_neon_shl_imm. */ | |
12824 | tmp = inst.operands[2].reg; | |
12825 | inst.operands[2].reg = inst.operands[1].reg; | |
12826 | inst.operands[1].reg = tmp; | |
88714cb8 | 12827 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 12828 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
12829 | } |
12830 | } | |
12831 | ||
627907b7 JB |
12832 | static void |
12833 | do_neon_rshl (void) | |
12834 | { | |
12835 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
12836 | struct neon_type_el et = neon_check_type (3, rs, | |
12837 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
12838 | unsigned int tmp; | |
12839 | ||
12840 | tmp = inst.operands[2].reg; | |
12841 | inst.operands[2].reg = inst.operands[1].reg; | |
12842 | inst.operands[1].reg = tmp; | |
12843 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
12844 | } | |
12845 | ||
5287ad62 JB |
12846 | static int |
12847 | neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) | |
12848 | { | |
036dc3f7 PB |
12849 | /* Handle .I8 pseudo-instructions. */ |
12850 | if (size == 8) | |
5287ad62 | 12851 | { |
5287ad62 JB |
12852 | /* Unfortunately, this will make everything apart from zero out-of-range. |
12853 | FIXME is this the intended semantics? There doesn't seem much point in | |
12854 | accepting .I8 if so. */ | |
12855 | immediate |= immediate << 8; | |
12856 | size = 16; | |
036dc3f7 PB |
12857 | } |
12858 | ||
12859 | if (size >= 32) | |
12860 | { | |
12861 | if (immediate == (immediate & 0x000000ff)) | |
12862 | { | |
12863 | *immbits = immediate; | |
12864 | return 0x1; | |
12865 | } | |
12866 | else if (immediate == (immediate & 0x0000ff00)) | |
12867 | { | |
12868 | *immbits = immediate >> 8; | |
12869 | return 0x3; | |
12870 | } | |
12871 | else if (immediate == (immediate & 0x00ff0000)) | |
12872 | { | |
12873 | *immbits = immediate >> 16; | |
12874 | return 0x5; | |
12875 | } | |
12876 | else if (immediate == (immediate & 0xff000000)) | |
12877 | { | |
12878 | *immbits = immediate >> 24; | |
12879 | return 0x7; | |
12880 | } | |
12881 | if ((immediate & 0xffff) != (immediate >> 16)) | |
12882 | goto bad_immediate; | |
12883 | immediate &= 0xffff; | |
5287ad62 JB |
12884 | } |
12885 | ||
12886 | if (immediate == (immediate & 0x000000ff)) | |
12887 | { | |
12888 | *immbits = immediate; | |
036dc3f7 | 12889 | return 0x9; |
5287ad62 JB |
12890 | } |
12891 | else if (immediate == (immediate & 0x0000ff00)) | |
12892 | { | |
12893 | *immbits = immediate >> 8; | |
036dc3f7 | 12894 | return 0xb; |
5287ad62 JB |
12895 | } |
12896 | ||
12897 | bad_immediate: | |
dcbf9037 | 12898 | first_error (_("immediate value out of range")); |
5287ad62 JB |
12899 | return FAIL; |
12900 | } | |
12901 | ||
12902 | /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits | |
12903 | A, B, C, D. */ | |
12904 | ||
12905 | static int | |
12906 | neon_bits_same_in_bytes (unsigned imm) | |
12907 | { | |
12908 | return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) | |
12909 | && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) | |
12910 | && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) | |
12911 | && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); | |
12912 | } | |
12913 | ||
12914 | /* For immediate of above form, return 0bABCD. */ | |
12915 | ||
12916 | static unsigned | |
12917 | neon_squash_bits (unsigned imm) | |
12918 | { | |
12919 | return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) | |
12920 | | ((imm & 0x01000000) >> 21); | |
12921 | } | |
12922 | ||
136da414 | 12923 | /* Compress quarter-float representation to 0b...000 abcdefgh. */ |
5287ad62 JB |
12924 | |
12925 | static unsigned | |
12926 | neon_qfloat_bits (unsigned imm) | |
12927 | { | |
136da414 | 12928 | return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); |
5287ad62 JB |
12929 | } |
12930 | ||
12931 | /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into | |
12932 | the instruction. *OP is passed as the initial value of the op field, and | |
12933 | may be set to a different value depending on the constant (i.e. | |
12934 | "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not | |
5f4273c7 | 12935 | MVN). If the immediate looks like a repeated pattern then also |
036dc3f7 | 12936 | try smaller element sizes. */ |
5287ad62 JB |
12937 | |
12938 | static int | |
c96612cc JB |
12939 | neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, |
12940 | unsigned *immbits, int *op, int size, | |
12941 | enum neon_el_type type) | |
5287ad62 | 12942 | { |
c96612cc JB |
12943 | /* Only permit float immediates (including 0.0/-0.0) if the operand type is |
12944 | float. */ | |
12945 | if (type == NT_float && !float_p) | |
12946 | return FAIL; | |
12947 | ||
136da414 JB |
12948 | if (type == NT_float && is_quarter_float (immlo) && immhi == 0) |
12949 | { | |
12950 | if (size != 32 || *op == 1) | |
12951 | return FAIL; | |
12952 | *immbits = neon_qfloat_bits (immlo); | |
12953 | return 0xf; | |
12954 | } | |
036dc3f7 PB |
12955 | |
12956 | if (size == 64) | |
5287ad62 | 12957 | { |
036dc3f7 PB |
12958 | if (neon_bits_same_in_bytes (immhi) |
12959 | && neon_bits_same_in_bytes (immlo)) | |
12960 | { | |
12961 | if (*op == 1) | |
12962 | return FAIL; | |
12963 | *immbits = (neon_squash_bits (immhi) << 4) | |
12964 | | neon_squash_bits (immlo); | |
12965 | *op = 1; | |
12966 | return 0xe; | |
12967 | } | |
12968 | ||
12969 | if (immhi != immlo) | |
12970 | return FAIL; | |
5287ad62 | 12971 | } |
036dc3f7 PB |
12972 | |
12973 | if (size >= 32) | |
5287ad62 | 12974 | { |
036dc3f7 PB |
12975 | if (immlo == (immlo & 0x000000ff)) |
12976 | { | |
12977 | *immbits = immlo; | |
12978 | return 0x0; | |
12979 | } | |
12980 | else if (immlo == (immlo & 0x0000ff00)) | |
12981 | { | |
12982 | *immbits = immlo >> 8; | |
12983 | return 0x2; | |
12984 | } | |
12985 | else if (immlo == (immlo & 0x00ff0000)) | |
12986 | { | |
12987 | *immbits = immlo >> 16; | |
12988 | return 0x4; | |
12989 | } | |
12990 | else if (immlo == (immlo & 0xff000000)) | |
12991 | { | |
12992 | *immbits = immlo >> 24; | |
12993 | return 0x6; | |
12994 | } | |
12995 | else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) | |
12996 | { | |
12997 | *immbits = (immlo >> 8) & 0xff; | |
12998 | return 0xc; | |
12999 | } | |
13000 | else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) | |
13001 | { | |
13002 | *immbits = (immlo >> 16) & 0xff; | |
13003 | return 0xd; | |
13004 | } | |
13005 | ||
13006 | if ((immlo & 0xffff) != (immlo >> 16)) | |
13007 | return FAIL; | |
13008 | immlo &= 0xffff; | |
5287ad62 | 13009 | } |
036dc3f7 PB |
13010 | |
13011 | if (size >= 16) | |
5287ad62 | 13012 | { |
036dc3f7 PB |
13013 | if (immlo == (immlo & 0x000000ff)) |
13014 | { | |
13015 | *immbits = immlo; | |
13016 | return 0x8; | |
13017 | } | |
13018 | else if (immlo == (immlo & 0x0000ff00)) | |
13019 | { | |
13020 | *immbits = immlo >> 8; | |
13021 | return 0xa; | |
13022 | } | |
13023 | ||
13024 | if ((immlo & 0xff) != (immlo >> 8)) | |
13025 | return FAIL; | |
13026 | immlo &= 0xff; | |
5287ad62 | 13027 | } |
036dc3f7 PB |
13028 | |
13029 | if (immlo == (immlo & 0x000000ff)) | |
5287ad62 | 13030 | { |
036dc3f7 PB |
13031 | /* Don't allow MVN with 8-bit immediate. */ |
13032 | if (*op == 1) | |
13033 | return FAIL; | |
13034 | *immbits = immlo; | |
13035 | return 0xe; | |
5287ad62 | 13036 | } |
5287ad62 JB |
13037 | |
13038 | return FAIL; | |
13039 | } | |
13040 | ||
13041 | /* Write immediate bits [7:0] to the following locations: | |
13042 | ||
13043 | |28/24|23 19|18 16|15 4|3 0| | |
13044 | | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| | |
13045 | ||
13046 | This function is used by VMOV/VMVN/VORR/VBIC. */ | |
13047 | ||
13048 | static void | |
13049 | neon_write_immbits (unsigned immbits) | |
13050 | { | |
13051 | inst.instruction |= immbits & 0xf; | |
13052 | inst.instruction |= ((immbits >> 4) & 0x7) << 16; | |
13053 | inst.instruction |= ((immbits >> 7) & 0x1) << 24; | |
13054 | } | |
13055 | ||
13056 | /* Invert low-order SIZE bits of XHI:XLO. */ | |
13057 | ||
13058 | static void | |
13059 | neon_invert_size (unsigned *xlo, unsigned *xhi, int size) | |
13060 | { | |
13061 | unsigned immlo = xlo ? *xlo : 0; | |
13062 | unsigned immhi = xhi ? *xhi : 0; | |
13063 | ||
13064 | switch (size) | |
13065 | { | |
13066 | case 8: | |
13067 | immlo = (~immlo) & 0xff; | |
13068 | break; | |
13069 | ||
13070 | case 16: | |
13071 | immlo = (~immlo) & 0xffff; | |
13072 | break; | |
13073 | ||
13074 | case 64: | |
13075 | immhi = (~immhi) & 0xffffffff; | |
13076 | /* fall through. */ | |
13077 | ||
13078 | case 32: | |
13079 | immlo = (~immlo) & 0xffffffff; | |
13080 | break; | |
13081 | ||
13082 | default: | |
13083 | abort (); | |
13084 | } | |
13085 | ||
13086 | if (xlo) | |
13087 | *xlo = immlo; | |
13088 | ||
13089 | if (xhi) | |
13090 | *xhi = immhi; | |
13091 | } | |
13092 | ||
13093 | static void | |
13094 | do_neon_logic (void) | |
13095 | { | |
13096 | if (inst.operands[2].present && inst.operands[2].isreg) | |
13097 | { | |
037e8744 | 13098 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13099 | neon_check_type (3, rs, N_IGNORE_TYPE); |
13100 | /* U bit and size field were set as part of the bitmask. */ | |
88714cb8 | 13101 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13102 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13103 | } |
13104 | else | |
13105 | { | |
4316f0d2 DG |
13106 | const int three_ops_form = (inst.operands[2].present |
13107 | && !inst.operands[2].isreg); | |
13108 | const int immoperand = (three_ops_form ? 2 : 1); | |
13109 | enum neon_shape rs = (three_ops_form | |
13110 | ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL) | |
13111 | : neon_select_shape (NS_DI, NS_QI, NS_NULL)); | |
037e8744 JB |
13112 | struct neon_type_el et = neon_check_type (2, rs, |
13113 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
21d799b5 | 13114 | enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff; |
5287ad62 JB |
13115 | unsigned immbits; |
13116 | int cmode; | |
5f4273c7 | 13117 | |
5287ad62 JB |
13118 | if (et.type == NT_invtype) |
13119 | return; | |
5f4273c7 | 13120 | |
4316f0d2 DG |
13121 | if (three_ops_form) |
13122 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
13123 | _("first and second operands shall be the same register")); | |
13124 | ||
88714cb8 | 13125 | NEON_ENCODE (IMMED, inst); |
5287ad62 | 13126 | |
4316f0d2 | 13127 | immbits = inst.operands[immoperand].imm; |
036dc3f7 PB |
13128 | if (et.size == 64) |
13129 | { | |
13130 | /* .i64 is a pseudo-op, so the immediate must be a repeating | |
13131 | pattern. */ | |
4316f0d2 DG |
13132 | if (immbits != (inst.operands[immoperand].regisimm ? |
13133 | inst.operands[immoperand].reg : 0)) | |
036dc3f7 PB |
13134 | { |
13135 | /* Set immbits to an invalid constant. */ | |
13136 | immbits = 0xdeadbeef; | |
13137 | } | |
13138 | } | |
13139 | ||
5287ad62 JB |
13140 | switch (opcode) |
13141 | { | |
13142 | case N_MNEM_vbic: | |
036dc3f7 | 13143 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
5287ad62 | 13144 | break; |
5f4273c7 | 13145 | |
5287ad62 | 13146 | case N_MNEM_vorr: |
036dc3f7 | 13147 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
5287ad62 | 13148 | break; |
5f4273c7 | 13149 | |
5287ad62 JB |
13150 | case N_MNEM_vand: |
13151 | /* Pseudo-instruction for VBIC. */ | |
5287ad62 JB |
13152 | neon_invert_size (&immbits, 0, et.size); |
13153 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
13154 | break; | |
5f4273c7 | 13155 | |
5287ad62 JB |
13156 | case N_MNEM_vorn: |
13157 | /* Pseudo-instruction for VORR. */ | |
5287ad62 JB |
13158 | neon_invert_size (&immbits, 0, et.size); |
13159 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
13160 | break; | |
5f4273c7 | 13161 | |
5287ad62 JB |
13162 | default: |
13163 | abort (); | |
13164 | } | |
13165 | ||
13166 | if (cmode == FAIL) | |
13167 | return; | |
13168 | ||
037e8744 | 13169 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13170 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13171 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13172 | inst.instruction |= cmode << 8; | |
13173 | neon_write_immbits (immbits); | |
5f4273c7 | 13174 | |
88714cb8 | 13175 | neon_dp_fixup (&inst); |
5287ad62 JB |
13176 | } |
13177 | } | |
13178 | ||
13179 | static void | |
13180 | do_neon_bitfield (void) | |
13181 | { | |
037e8744 | 13182 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 13183 | neon_check_type (3, rs, N_IGNORE_TYPE); |
037e8744 | 13184 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13185 | } |
13186 | ||
13187 | static void | |
dcbf9037 JB |
13188 | neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, |
13189 | unsigned destbits) | |
5287ad62 | 13190 | { |
037e8744 | 13191 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 JB |
13192 | struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, |
13193 | types | N_KEY); | |
5287ad62 JB |
13194 | if (et.type == NT_float) |
13195 | { | |
88714cb8 | 13196 | NEON_ENCODE (FLOAT, inst); |
037e8744 | 13197 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13198 | } |
13199 | else | |
13200 | { | |
88714cb8 | 13201 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13202 | neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); |
5287ad62 JB |
13203 | } |
13204 | } | |
13205 | ||
13206 | static void | |
13207 | do_neon_dyadic_if_su (void) | |
13208 | { | |
dcbf9037 | 13209 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
13210 | } |
13211 | ||
13212 | static void | |
13213 | do_neon_dyadic_if_su_d (void) | |
13214 | { | |
13215 | /* This version only allow D registers, but that constraint is enforced during | |
13216 | operand parsing so we don't need to do anything extra here. */ | |
dcbf9037 | 13217 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
13218 | } |
13219 | ||
5287ad62 JB |
13220 | static void |
13221 | do_neon_dyadic_if_i_d (void) | |
13222 | { | |
428e3f1f PB |
13223 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
13224 | affected if we specify unsigned args. */ | |
13225 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
5287ad62 JB |
13226 | } |
13227 | ||
037e8744 JB |
13228 | enum vfp_or_neon_is_neon_bits |
13229 | { | |
13230 | NEON_CHECK_CC = 1, | |
13231 | NEON_CHECK_ARCH = 2 | |
13232 | }; | |
13233 | ||
13234 | /* Call this function if an instruction which may have belonged to the VFP or | |
13235 | Neon instruction sets, but turned out to be a Neon instruction (due to the | |
13236 | operand types involved, etc.). We have to check and/or fix-up a couple of | |
13237 | things: | |
13238 | ||
13239 | - Make sure the user hasn't attempted to make a Neon instruction | |
13240 | conditional. | |
13241 | - Alter the value in the condition code field if necessary. | |
13242 | - Make sure that the arch supports Neon instructions. | |
13243 | ||
13244 | Which of these operations take place depends on bits from enum | |
13245 | vfp_or_neon_is_neon_bits. | |
13246 | ||
13247 | WARNING: This function has side effects! If NEON_CHECK_CC is used and the | |
13248 | current instruction's condition is COND_ALWAYS, the condition field is | |
13249 | changed to inst.uncond_value. This is necessary because instructions shared | |
13250 | between VFP and Neon may be conditional for the VFP variants only, and the | |
13251 | unconditional Neon version must have, e.g., 0xF in the condition field. */ | |
13252 | ||
13253 | static int | |
13254 | vfp_or_neon_is_neon (unsigned check) | |
13255 | { | |
13256 | /* Conditions are always legal in Thumb mode (IT blocks). */ | |
13257 | if (!thumb_mode && (check & NEON_CHECK_CC)) | |
13258 | { | |
13259 | if (inst.cond != COND_ALWAYS) | |
13260 | { | |
13261 | first_error (_(BAD_COND)); | |
13262 | return FAIL; | |
13263 | } | |
13264 | if (inst.uncond_value != -1) | |
13265 | inst.instruction |= inst.uncond_value << 28; | |
13266 | } | |
5f4273c7 | 13267 | |
037e8744 JB |
13268 | if ((check & NEON_CHECK_ARCH) |
13269 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) | |
13270 | { | |
13271 | first_error (_(BAD_FPU)); | |
13272 | return FAIL; | |
13273 | } | |
5f4273c7 | 13274 | |
037e8744 JB |
13275 | return SUCCESS; |
13276 | } | |
13277 | ||
5287ad62 JB |
13278 | static void |
13279 | do_neon_addsub_if_i (void) | |
13280 | { | |
037e8744 JB |
13281 | if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) |
13282 | return; | |
13283 | ||
13284 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13285 | return; | |
13286 | ||
5287ad62 JB |
13287 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
13288 | affected if we specify unsigned args. */ | |
dcbf9037 | 13289 | neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); |
5287ad62 JB |
13290 | } |
13291 | ||
13292 | /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the | |
13293 | result to be: | |
13294 | V<op> A,B (A is operand 0, B is operand 2) | |
13295 | to mean: | |
13296 | V<op> A,B,A | |
13297 | not: | |
13298 | V<op> A,B,B | |
13299 | so handle that case specially. */ | |
13300 | ||
13301 | static void | |
13302 | neon_exchange_operands (void) | |
13303 | { | |
13304 | void *scratch = alloca (sizeof (inst.operands[0])); | |
13305 | if (inst.operands[1].present) | |
13306 | { | |
13307 | /* Swap operands[1] and operands[2]. */ | |
13308 | memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); | |
13309 | inst.operands[1] = inst.operands[2]; | |
13310 | memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); | |
13311 | } | |
13312 | else | |
13313 | { | |
13314 | inst.operands[1] = inst.operands[2]; | |
13315 | inst.operands[2] = inst.operands[0]; | |
13316 | } | |
13317 | } | |
13318 | ||
13319 | static void | |
13320 | neon_compare (unsigned regtypes, unsigned immtypes, int invert) | |
13321 | { | |
13322 | if (inst.operands[2].isreg) | |
13323 | { | |
13324 | if (invert) | |
13325 | neon_exchange_operands (); | |
dcbf9037 | 13326 | neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); |
5287ad62 JB |
13327 | } |
13328 | else | |
13329 | { | |
037e8744 | 13330 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
dcbf9037 JB |
13331 | struct neon_type_el et = neon_check_type (2, rs, |
13332 | N_EQK | N_SIZ, immtypes | N_KEY); | |
5287ad62 | 13333 | |
88714cb8 | 13334 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
13335 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13336 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13337 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13338 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 13339 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13340 | inst.instruction |= (et.type == NT_float) << 10; |
13341 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 13342 | |
88714cb8 | 13343 | neon_dp_fixup (&inst); |
5287ad62 JB |
13344 | } |
13345 | } | |
13346 | ||
13347 | static void | |
13348 | do_neon_cmp (void) | |
13349 | { | |
13350 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); | |
13351 | } | |
13352 | ||
13353 | static void | |
13354 | do_neon_cmp_inv (void) | |
13355 | { | |
13356 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); | |
13357 | } | |
13358 | ||
13359 | static void | |
13360 | do_neon_ceq (void) | |
13361 | { | |
13362 | neon_compare (N_IF_32, N_IF_32, FALSE); | |
13363 | } | |
13364 | ||
13365 | /* For multiply instructions, we have the possibility of 16-bit or 32-bit | |
13366 | scalars, which are encoded in 5 bits, M : Rm. | |
13367 | For 16-bit scalars, the register is encoded in Rm[2:0] and the index in | |
13368 | M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the | |
13369 | index in M. */ | |
13370 | ||
13371 | static unsigned | |
13372 | neon_scalar_for_mul (unsigned scalar, unsigned elsize) | |
13373 | { | |
dcbf9037 JB |
13374 | unsigned regno = NEON_SCALAR_REG (scalar); |
13375 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
5287ad62 JB |
13376 | |
13377 | switch (elsize) | |
13378 | { | |
13379 | case 16: | |
13380 | if (regno > 7 || elno > 3) | |
13381 | goto bad_scalar; | |
13382 | return regno | (elno << 3); | |
5f4273c7 | 13383 | |
5287ad62 JB |
13384 | case 32: |
13385 | if (regno > 15 || elno > 1) | |
13386 | goto bad_scalar; | |
13387 | return regno | (elno << 4); | |
13388 | ||
13389 | default: | |
13390 | bad_scalar: | |
dcbf9037 | 13391 | first_error (_("scalar out of range for multiply instruction")); |
5287ad62 JB |
13392 | } |
13393 | ||
13394 | return 0; | |
13395 | } | |
13396 | ||
13397 | /* Encode multiply / multiply-accumulate scalar instructions. */ | |
13398 | ||
13399 | static void | |
13400 | neon_mul_mac (struct neon_type_el et, int ubit) | |
13401 | { | |
dcbf9037 JB |
13402 | unsigned scalar; |
13403 | ||
13404 | /* Give a more helpful error message if we have an invalid type. */ | |
13405 | if (et.type == NT_invtype) | |
13406 | return; | |
5f4273c7 | 13407 | |
dcbf9037 | 13408 | scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); |
5287ad62 JB |
13409 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13410 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13411 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
13412 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
13413 | inst.instruction |= LOW4 (scalar); | |
13414 | inst.instruction |= HI1 (scalar) << 5; | |
13415 | inst.instruction |= (et.type == NT_float) << 8; | |
13416 | inst.instruction |= neon_logbits (et.size) << 20; | |
13417 | inst.instruction |= (ubit != 0) << 24; | |
13418 | ||
88714cb8 | 13419 | neon_dp_fixup (&inst); |
5287ad62 JB |
13420 | } |
13421 | ||
13422 | static void | |
13423 | do_neon_mac_maybe_scalar (void) | |
13424 | { | |
037e8744 JB |
13425 | if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) |
13426 | return; | |
13427 | ||
13428 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13429 | return; | |
13430 | ||
5287ad62 JB |
13431 | if (inst.operands[2].isscalar) |
13432 | { | |
037e8744 | 13433 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
13434 | struct neon_type_el et = neon_check_type (3, rs, |
13435 | N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); | |
88714cb8 | 13436 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 13437 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
13438 | } |
13439 | else | |
428e3f1f PB |
13440 | { |
13441 | /* The "untyped" case can't happen. Do this to stop the "U" bit being | |
13442 | affected if we specify unsigned args. */ | |
13443 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
13444 | } | |
5287ad62 JB |
13445 | } |
13446 | ||
62f3b8c8 PB |
13447 | static void |
13448 | do_neon_fmac (void) | |
13449 | { | |
13450 | if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS) | |
13451 | return; | |
13452 | ||
13453 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13454 | return; | |
13455 | ||
13456 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
13457 | } | |
13458 | ||
5287ad62 JB |
13459 | static void |
13460 | do_neon_tst (void) | |
13461 | { | |
037e8744 | 13462 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13463 | struct neon_type_el et = neon_check_type (3, rs, |
13464 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
037e8744 | 13465 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
13466 | } |
13467 | ||
13468 | /* VMUL with 3 registers allows the P8 type. The scalar version supports the | |
13469 | same types as the MAC equivalents. The polynomial type for this instruction | |
13470 | is encoded the same as the integer type. */ | |
13471 | ||
13472 | static void | |
13473 | do_neon_mul (void) | |
13474 | { | |
037e8744 JB |
13475 | if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) |
13476 | return; | |
13477 | ||
13478 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13479 | return; | |
13480 | ||
5287ad62 JB |
13481 | if (inst.operands[2].isscalar) |
13482 | do_neon_mac_maybe_scalar (); | |
13483 | else | |
dcbf9037 | 13484 | neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); |
5287ad62 JB |
13485 | } |
13486 | ||
13487 | static void | |
13488 | do_neon_qdmulh (void) | |
13489 | { | |
13490 | if (inst.operands[2].isscalar) | |
13491 | { | |
037e8744 | 13492 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
13493 | struct neon_type_el et = neon_check_type (3, rs, |
13494 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
88714cb8 | 13495 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 13496 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
13497 | } |
13498 | else | |
13499 | { | |
037e8744 | 13500 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13501 | struct neon_type_el et = neon_check_type (3, rs, |
13502 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
88714cb8 | 13503 | NEON_ENCODE (INTEGER, inst); |
5287ad62 | 13504 | /* The U bit (rounding) comes from bit mask. */ |
037e8744 | 13505 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
13506 | } |
13507 | } | |
13508 | ||
13509 | static void | |
13510 | do_neon_fcmp_absolute (void) | |
13511 | { | |
037e8744 | 13512 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13513 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
13514 | /* Size field comes from bit mask. */ | |
037e8744 | 13515 | neon_three_same (neon_quad (rs), 1, -1); |
5287ad62 JB |
13516 | } |
13517 | ||
13518 | static void | |
13519 | do_neon_fcmp_absolute_inv (void) | |
13520 | { | |
13521 | neon_exchange_operands (); | |
13522 | do_neon_fcmp_absolute (); | |
13523 | } | |
13524 | ||
13525 | static void | |
13526 | do_neon_step (void) | |
13527 | { | |
037e8744 | 13528 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 13529 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
037e8744 | 13530 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13531 | } |
13532 | ||
13533 | static void | |
13534 | do_neon_abs_neg (void) | |
13535 | { | |
037e8744 JB |
13536 | enum neon_shape rs; |
13537 | struct neon_type_el et; | |
5f4273c7 | 13538 | |
037e8744 JB |
13539 | if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) |
13540 | return; | |
13541 | ||
13542 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13543 | return; | |
13544 | ||
13545 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
13546 | et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); | |
5f4273c7 | 13547 | |
5287ad62 JB |
13548 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13549 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13550 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13551 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 13552 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13553 | inst.instruction |= (et.type == NT_float) << 10; |
13554 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 13555 | |
88714cb8 | 13556 | neon_dp_fixup (&inst); |
5287ad62 JB |
13557 | } |
13558 | ||
13559 | static void | |
13560 | do_neon_sli (void) | |
13561 | { | |
037e8744 | 13562 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
13563 | struct neon_type_el et = neon_check_type (2, rs, |
13564 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
13565 | int imm = inst.operands[2].imm; | |
13566 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
13567 | _("immediate out of range for insert")); | |
037e8744 | 13568 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
13569 | } |
13570 | ||
13571 | static void | |
13572 | do_neon_sri (void) | |
13573 | { | |
037e8744 | 13574 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
13575 | struct neon_type_el et = neon_check_type (2, rs, |
13576 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
13577 | int imm = inst.operands[2].imm; | |
13578 | constraint (imm < 1 || (unsigned)imm > et.size, | |
13579 | _("immediate out of range for insert")); | |
037e8744 | 13580 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); |
5287ad62 JB |
13581 | } |
13582 | ||
13583 | static void | |
13584 | do_neon_qshlu_imm (void) | |
13585 | { | |
037e8744 | 13586 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
13587 | struct neon_type_el et = neon_check_type (2, rs, |
13588 | N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); | |
13589 | int imm = inst.operands[2].imm; | |
13590 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
13591 | _("immediate out of range for shift")); | |
13592 | /* Only encodes the 'U present' variant of the instruction. | |
13593 | In this case, signed types have OP (bit 8) set to 0. | |
13594 | Unsigned types have OP set to 1. */ | |
13595 | inst.instruction |= (et.type == NT_unsigned) << 8; | |
13596 | /* The rest of the bits are the same as other immediate shifts. */ | |
037e8744 | 13597 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
13598 | } |
13599 | ||
13600 | static void | |
13601 | do_neon_qmovn (void) | |
13602 | { | |
13603 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
13604 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
13605 | /* Saturating move where operands can be signed or unsigned, and the | |
13606 | destination has the same signedness. */ | |
88714cb8 | 13607 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
13608 | if (et.type == NT_unsigned) |
13609 | inst.instruction |= 0xc0; | |
13610 | else | |
13611 | inst.instruction |= 0x80; | |
13612 | neon_two_same (0, 1, et.size / 2); | |
13613 | } | |
13614 | ||
13615 | static void | |
13616 | do_neon_qmovun (void) | |
13617 | { | |
13618 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
13619 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
13620 | /* Saturating move with unsigned results. Operands must be signed. */ | |
88714cb8 | 13621 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
13622 | neon_two_same (0, 1, et.size / 2); |
13623 | } | |
13624 | ||
13625 | static void | |
13626 | do_neon_rshift_sat_narrow (void) | |
13627 | { | |
13628 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
13629 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
13630 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
13631 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
13632 | int imm = inst.operands[2].imm; | |
13633 | /* This gets the bounds check, size encoding and immediate bits calculation | |
13634 | right. */ | |
13635 | et.size /= 2; | |
5f4273c7 | 13636 | |
5287ad62 JB |
13637 | /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for |
13638 | VQMOVN.I<size> <Dd>, <Qm>. */ | |
13639 | if (imm == 0) | |
13640 | { | |
13641 | inst.operands[2].present = 0; | |
13642 | inst.instruction = N_MNEM_vqmovn; | |
13643 | do_neon_qmovn (); | |
13644 | return; | |
13645 | } | |
5f4273c7 | 13646 | |
5287ad62 JB |
13647 | constraint (imm < 1 || (unsigned)imm > et.size, |
13648 | _("immediate out of range")); | |
13649 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); | |
13650 | } | |
13651 | ||
13652 | static void | |
13653 | do_neon_rshift_sat_narrow_u (void) | |
13654 | { | |
13655 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
13656 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
13657 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
13658 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
13659 | int imm = inst.operands[2].imm; | |
13660 | /* This gets the bounds check, size encoding and immediate bits calculation | |
13661 | right. */ | |
13662 | et.size /= 2; | |
13663 | ||
13664 | /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for | |
13665 | VQMOVUN.I<size> <Dd>, <Qm>. */ | |
13666 | if (imm == 0) | |
13667 | { | |
13668 | inst.operands[2].present = 0; | |
13669 | inst.instruction = N_MNEM_vqmovun; | |
13670 | do_neon_qmovun (); | |
13671 | return; | |
13672 | } | |
13673 | ||
13674 | constraint (imm < 1 || (unsigned)imm > et.size, | |
13675 | _("immediate out of range")); | |
13676 | /* FIXME: The manual is kind of unclear about what value U should have in | |
13677 | VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it | |
13678 | must be 1. */ | |
13679 | neon_imm_shift (TRUE, 1, 0, et, et.size - imm); | |
13680 | } | |
13681 | ||
13682 | static void | |
13683 | do_neon_movn (void) | |
13684 | { | |
13685 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
13686 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
88714cb8 | 13687 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
13688 | neon_two_same (0, 1, et.size / 2); |
13689 | } | |
13690 | ||
13691 | static void | |
13692 | do_neon_rshift_narrow (void) | |
13693 | { | |
13694 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
13695 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
13696 | int imm = inst.operands[2].imm; | |
13697 | /* This gets the bounds check, size encoding and immediate bits calculation | |
13698 | right. */ | |
13699 | et.size /= 2; | |
5f4273c7 | 13700 | |
5287ad62 JB |
13701 | /* If immediate is zero then we are a pseudo-instruction for |
13702 | VMOVN.I<size> <Dd>, <Qm> */ | |
13703 | if (imm == 0) | |
13704 | { | |
13705 | inst.operands[2].present = 0; | |
13706 | inst.instruction = N_MNEM_vmovn; | |
13707 | do_neon_movn (); | |
13708 | return; | |
13709 | } | |
5f4273c7 | 13710 | |
5287ad62 JB |
13711 | constraint (imm < 1 || (unsigned)imm > et.size, |
13712 | _("immediate out of range for narrowing operation")); | |
13713 | neon_imm_shift (FALSE, 0, 0, et, et.size - imm); | |
13714 | } | |
13715 | ||
13716 | static void | |
13717 | do_neon_shll (void) | |
13718 | { | |
13719 | /* FIXME: Type checking when lengthening. */ | |
13720 | struct neon_type_el et = neon_check_type (2, NS_QDI, | |
13721 | N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); | |
13722 | unsigned imm = inst.operands[2].imm; | |
13723 | ||
13724 | if (imm == et.size) | |
13725 | { | |
13726 | /* Maximum shift variant. */ | |
88714cb8 | 13727 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
13728 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13729 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13730 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13731 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13732 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 13733 | |
88714cb8 | 13734 | neon_dp_fixup (&inst); |
5287ad62 JB |
13735 | } |
13736 | else | |
13737 | { | |
13738 | /* A more-specific type check for non-max versions. */ | |
13739 | et = neon_check_type (2, NS_QDI, | |
13740 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
88714cb8 | 13741 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
13742 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); |
13743 | } | |
13744 | } | |
13745 | ||
037e8744 | 13746 | /* Check the various types for the VCVT instruction, and return which version |
5287ad62 JB |
13747 | the current instruction is. */ |
13748 | ||
13749 | static int | |
13750 | neon_cvt_flavour (enum neon_shape rs) | |
13751 | { | |
037e8744 JB |
13752 | #define CVT_VAR(C,X,Y) \ |
13753 | et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \ | |
13754 | if (et.type != NT_invtype) \ | |
13755 | { \ | |
13756 | inst.error = NULL; \ | |
13757 | return (C); \ | |
5287ad62 JB |
13758 | } |
13759 | struct neon_type_el et; | |
037e8744 JB |
13760 | unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF |
13761 | || rs == NS_FF) ? N_VFP : 0; | |
13762 | /* The instruction versions which take an immediate take one register | |
13763 | argument, which is extended to the width of the full register. Thus the | |
13764 | "source" and "destination" registers must have the same width. Hack that | |
13765 | here by making the size equal to the key (wider, in this case) operand. */ | |
13766 | unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; | |
5f4273c7 | 13767 | |
5287ad62 JB |
13768 | CVT_VAR (0, N_S32, N_F32); |
13769 | CVT_VAR (1, N_U32, N_F32); | |
13770 | CVT_VAR (2, N_F32, N_S32); | |
13771 | CVT_VAR (3, N_F32, N_U32); | |
8e79c3df CM |
13772 | /* Half-precision conversions. */ |
13773 | CVT_VAR (4, N_F32, N_F16); | |
13774 | CVT_VAR (5, N_F16, N_F32); | |
5f4273c7 | 13775 | |
037e8744 | 13776 | whole_reg = N_VFP; |
5f4273c7 | 13777 | |
037e8744 | 13778 | /* VFP instructions. */ |
8e79c3df CM |
13779 | CVT_VAR (6, N_F32, N_F64); |
13780 | CVT_VAR (7, N_F64, N_F32); | |
13781 | CVT_VAR (8, N_S32, N_F64 | key); | |
13782 | CVT_VAR (9, N_U32, N_F64 | key); | |
13783 | CVT_VAR (10, N_F64 | key, N_S32); | |
13784 | CVT_VAR (11, N_F64 | key, N_U32); | |
037e8744 | 13785 | /* VFP instructions with bitshift. */ |
8e79c3df CM |
13786 | CVT_VAR (12, N_F32 | key, N_S16); |
13787 | CVT_VAR (13, N_F32 | key, N_U16); | |
13788 | CVT_VAR (14, N_F64 | key, N_S16); | |
13789 | CVT_VAR (15, N_F64 | key, N_U16); | |
13790 | CVT_VAR (16, N_S16, N_F32 | key); | |
13791 | CVT_VAR (17, N_U16, N_F32 | key); | |
13792 | CVT_VAR (18, N_S16, N_F64 | key); | |
13793 | CVT_VAR (19, N_U16, N_F64 | key); | |
5f4273c7 | 13794 | |
5287ad62 JB |
13795 | return -1; |
13796 | #undef CVT_VAR | |
13797 | } | |
13798 | ||
037e8744 JB |
13799 | /* Neon-syntax VFP conversions. */ |
13800 | ||
5287ad62 | 13801 | static void |
037e8744 | 13802 | do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) |
5287ad62 | 13803 | { |
037e8744 | 13804 | const char *opname = 0; |
5f4273c7 | 13805 | |
037e8744 | 13806 | if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) |
5287ad62 | 13807 | { |
037e8744 JB |
13808 | /* Conversions with immediate bitshift. */ |
13809 | const char *enc[] = | |
13810 | { | |
13811 | "ftosls", | |
13812 | "ftouls", | |
13813 | "fsltos", | |
13814 | "fultos", | |
13815 | NULL, | |
13816 | NULL, | |
8e79c3df CM |
13817 | NULL, |
13818 | NULL, | |
037e8744 JB |
13819 | "ftosld", |
13820 | "ftould", | |
13821 | "fsltod", | |
13822 | "fultod", | |
13823 | "fshtos", | |
13824 | "fuhtos", | |
13825 | "fshtod", | |
13826 | "fuhtod", | |
13827 | "ftoshs", | |
13828 | "ftouhs", | |
13829 | "ftoshd", | |
13830 | "ftouhd" | |
13831 | }; | |
13832 | ||
13833 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
13834 | { | |
13835 | opname = enc[flavour]; | |
13836 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
13837 | _("operands 0 and 1 must be the same register")); | |
13838 | inst.operands[1] = inst.operands[2]; | |
13839 | memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); | |
13840 | } | |
5287ad62 JB |
13841 | } |
13842 | else | |
13843 | { | |
037e8744 JB |
13844 | /* Conversions without bitshift. */ |
13845 | const char *enc[] = | |
13846 | { | |
13847 | "ftosis", | |
13848 | "ftouis", | |
13849 | "fsitos", | |
13850 | "fuitos", | |
8e79c3df CM |
13851 | "NULL", |
13852 | "NULL", | |
037e8744 JB |
13853 | "fcvtsd", |
13854 | "fcvtds", | |
13855 | "ftosid", | |
13856 | "ftouid", | |
13857 | "fsitod", | |
13858 | "fuitod" | |
13859 | }; | |
13860 | ||
13861 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
13862 | opname = enc[flavour]; | |
13863 | } | |
13864 | ||
13865 | if (opname) | |
13866 | do_vfp_nsyn_opcode (opname); | |
13867 | } | |
13868 | ||
13869 | static void | |
13870 | do_vfp_nsyn_cvtz (void) | |
13871 | { | |
13872 | enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); | |
13873 | int flavour = neon_cvt_flavour (rs); | |
13874 | const char *enc[] = | |
13875 | { | |
13876 | "ftosizs", | |
13877 | "ftouizs", | |
13878 | NULL, | |
13879 | NULL, | |
13880 | NULL, | |
13881 | NULL, | |
8e79c3df CM |
13882 | NULL, |
13883 | NULL, | |
037e8744 JB |
13884 | "ftosizd", |
13885 | "ftouizd" | |
13886 | }; | |
13887 | ||
13888 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) | |
13889 | do_vfp_nsyn_opcode (enc[flavour]); | |
13890 | } | |
f31fef98 | 13891 | |
037e8744 | 13892 | static void |
e3e535bc | 13893 | do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED) |
037e8744 JB |
13894 | { |
13895 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, | |
8e79c3df | 13896 | NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL); |
037e8744 JB |
13897 | int flavour = neon_cvt_flavour (rs); |
13898 | ||
e3e535bc NC |
13899 | /* PR11109: Handle round-to-zero for VCVT conversions. */ |
13900 | if (round_to_zero | |
13901 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2) | |
13902 | && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9) | |
13903 | && (rs == NS_FD || rs == NS_FF)) | |
13904 | { | |
13905 | do_vfp_nsyn_cvtz (); | |
13906 | return; | |
13907 | } | |
13908 | ||
037e8744 | 13909 | /* VFP rather than Neon conversions. */ |
8e79c3df | 13910 | if (flavour >= 6) |
037e8744 JB |
13911 | { |
13912 | do_vfp_nsyn_cvt (rs, flavour); | |
13913 | return; | |
13914 | } | |
13915 | ||
13916 | switch (rs) | |
13917 | { | |
13918 | case NS_DDI: | |
13919 | case NS_QQI: | |
13920 | { | |
35997600 NC |
13921 | unsigned immbits; |
13922 | unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; | |
13923 | ||
037e8744 JB |
13924 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
13925 | return; | |
13926 | ||
13927 | /* Fixed-point conversion with #0 immediate is encoded as an | |
13928 | integer conversion. */ | |
13929 | if (inst.operands[2].present && inst.operands[2].imm == 0) | |
13930 | goto int_encode; | |
35997600 | 13931 | immbits = 32 - inst.operands[2].imm; |
88714cb8 | 13932 | NEON_ENCODE (IMMED, inst); |
037e8744 JB |
13933 | if (flavour != -1) |
13934 | inst.instruction |= enctab[flavour]; | |
13935 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13936 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13937 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13938 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13939 | inst.instruction |= neon_quad (rs) << 6; | |
13940 | inst.instruction |= 1 << 21; | |
13941 | inst.instruction |= immbits << 16; | |
13942 | ||
88714cb8 | 13943 | neon_dp_fixup (&inst); |
037e8744 JB |
13944 | } |
13945 | break; | |
13946 | ||
13947 | case NS_DD: | |
13948 | case NS_QQ: | |
13949 | int_encode: | |
13950 | { | |
13951 | unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; | |
13952 | ||
88714cb8 | 13953 | NEON_ENCODE (INTEGER, inst); |
037e8744 JB |
13954 | |
13955 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13956 | return; | |
13957 | ||
13958 | if (flavour != -1) | |
13959 | inst.instruction |= enctab[flavour]; | |
13960 | ||
13961 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13962 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13963 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13964 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13965 | inst.instruction |= neon_quad (rs) << 6; | |
13966 | inst.instruction |= 2 << 18; | |
13967 | ||
88714cb8 | 13968 | neon_dp_fixup (&inst); |
037e8744 JB |
13969 | } |
13970 | break; | |
13971 | ||
8e79c3df CM |
13972 | /* Half-precision conversions for Advanced SIMD -- neon. */ |
13973 | case NS_QD: | |
13974 | case NS_DQ: | |
13975 | ||
13976 | if ((rs == NS_DQ) | |
13977 | && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) | |
13978 | { | |
13979 | as_bad (_("operand size must match register width")); | |
13980 | break; | |
13981 | } | |
13982 | ||
13983 | if ((rs == NS_QD) | |
13984 | && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) | |
13985 | { | |
13986 | as_bad (_("operand size must match register width")); | |
13987 | break; | |
13988 | } | |
13989 | ||
13990 | if (rs == NS_DQ) | |
13991 | inst.instruction = 0x3b60600; | |
13992 | else | |
13993 | inst.instruction = 0x3b60700; | |
13994 | ||
13995 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13996 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13997 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13998 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
88714cb8 | 13999 | neon_dp_fixup (&inst); |
8e79c3df CM |
14000 | break; |
14001 | ||
037e8744 JB |
14002 | default: |
14003 | /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ | |
14004 | do_vfp_nsyn_cvt (rs, flavour); | |
5287ad62 | 14005 | } |
5287ad62 JB |
14006 | } |
14007 | ||
e3e535bc NC |
14008 | static void |
14009 | do_neon_cvtr (void) | |
14010 | { | |
14011 | do_neon_cvt_1 (FALSE); | |
14012 | } | |
14013 | ||
14014 | static void | |
14015 | do_neon_cvt (void) | |
14016 | { | |
14017 | do_neon_cvt_1 (TRUE); | |
14018 | } | |
14019 | ||
8e79c3df CM |
14020 | static void |
14021 | do_neon_cvtb (void) | |
14022 | { | |
14023 | inst.instruction = 0xeb20a40; | |
14024 | ||
14025 | /* The sizes are attached to the mnemonic. */ | |
14026 | if (inst.vectype.el[0].type != NT_invtype | |
14027 | && inst.vectype.el[0].size == 16) | |
14028 | inst.instruction |= 0x00010000; | |
14029 | ||
14030 | /* Programmer's syntax: the sizes are attached to the operands. */ | |
14031 | else if (inst.operands[0].vectype.type != NT_invtype | |
14032 | && inst.operands[0].vectype.size == 16) | |
14033 | inst.instruction |= 0x00010000; | |
14034 | ||
14035 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
14036 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
14037 | do_vfp_cond_or_thumb (); | |
14038 | } | |
14039 | ||
14040 | ||
14041 | static void | |
14042 | do_neon_cvtt (void) | |
14043 | { | |
14044 | do_neon_cvtb (); | |
14045 | inst.instruction |= 0x80; | |
14046 | } | |
14047 | ||
5287ad62 JB |
14048 | static void |
14049 | neon_move_immediate (void) | |
14050 | { | |
037e8744 JB |
14051 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
14052 | struct neon_type_el et = neon_check_type (2, rs, | |
14053 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
5287ad62 | 14054 | unsigned immlo, immhi = 0, immbits; |
c96612cc | 14055 | int op, cmode, float_p; |
5287ad62 | 14056 | |
037e8744 JB |
14057 | constraint (et.type == NT_invtype, |
14058 | _("operand size must be specified for immediate VMOV")); | |
14059 | ||
5287ad62 JB |
14060 | /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ |
14061 | op = (inst.instruction & (1 << 5)) != 0; | |
14062 | ||
14063 | immlo = inst.operands[1].imm; | |
14064 | if (inst.operands[1].regisimm) | |
14065 | immhi = inst.operands[1].reg; | |
14066 | ||
14067 | constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, | |
14068 | _("immediate has bits set outside the operand size")); | |
14069 | ||
c96612cc JB |
14070 | float_p = inst.operands[1].immisfloat; |
14071 | ||
14072 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, | |
136da414 | 14073 | et.size, et.type)) == FAIL) |
5287ad62 JB |
14074 | { |
14075 | /* Invert relevant bits only. */ | |
14076 | neon_invert_size (&immlo, &immhi, et.size); | |
14077 | /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable | |
14078 | with one or the other; those cases are caught by | |
14079 | neon_cmode_for_move_imm. */ | |
14080 | op = !op; | |
c96612cc JB |
14081 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, |
14082 | &op, et.size, et.type)) == FAIL) | |
5287ad62 | 14083 | { |
dcbf9037 | 14084 | first_error (_("immediate out of range")); |
5287ad62 JB |
14085 | return; |
14086 | } | |
14087 | } | |
14088 | ||
14089 | inst.instruction &= ~(1 << 5); | |
14090 | inst.instruction |= op << 5; | |
14091 | ||
14092 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14093 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
037e8744 | 14094 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14095 | inst.instruction |= cmode << 8; |
14096 | ||
14097 | neon_write_immbits (immbits); | |
14098 | } | |
14099 | ||
14100 | static void | |
14101 | do_neon_mvn (void) | |
14102 | { | |
14103 | if (inst.operands[1].isreg) | |
14104 | { | |
037e8744 | 14105 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5f4273c7 | 14106 | |
88714cb8 | 14107 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14108 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14109 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14110 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14111 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14112 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14113 | } |
14114 | else | |
14115 | { | |
88714cb8 | 14116 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14117 | neon_move_immediate (); |
14118 | } | |
14119 | ||
88714cb8 | 14120 | neon_dp_fixup (&inst); |
5287ad62 JB |
14121 | } |
14122 | ||
14123 | /* Encode instructions of form: | |
14124 | ||
14125 | |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
5f4273c7 | 14126 | | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */ |
5287ad62 JB |
14127 | |
14128 | static void | |
14129 | neon_mixed_length (struct neon_type_el et, unsigned size) | |
14130 | { | |
14131 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14132 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14133 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14134 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14135 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14136 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14137 | inst.instruction |= (et.type == NT_unsigned) << 24; | |
14138 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 14139 | |
88714cb8 | 14140 | neon_dp_fixup (&inst); |
5287ad62 JB |
14141 | } |
14142 | ||
14143 | static void | |
14144 | do_neon_dyadic_long (void) | |
14145 | { | |
14146 | /* FIXME: Type checking for lengthening op. */ | |
14147 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14148 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
14149 | neon_mixed_length (et, et.size); | |
14150 | } | |
14151 | ||
14152 | static void | |
14153 | do_neon_abal (void) | |
14154 | { | |
14155 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14156 | N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
14157 | neon_mixed_length (et, et.size); | |
14158 | } | |
14159 | ||
14160 | static void | |
14161 | neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) | |
14162 | { | |
14163 | if (inst.operands[2].isscalar) | |
14164 | { | |
dcbf9037 JB |
14165 | struct neon_type_el et = neon_check_type (3, NS_QDS, |
14166 | N_EQK | N_DBL, N_EQK, regtypes | N_KEY); | |
88714cb8 | 14167 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
14168 | neon_mul_mac (et, et.type == NT_unsigned); |
14169 | } | |
14170 | else | |
14171 | { | |
14172 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14173 | N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); | |
88714cb8 | 14174 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14175 | neon_mixed_length (et, et.size); |
14176 | } | |
14177 | } | |
14178 | ||
14179 | static void | |
14180 | do_neon_mac_maybe_scalar_long (void) | |
14181 | { | |
14182 | neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); | |
14183 | } | |
14184 | ||
14185 | static void | |
14186 | do_neon_dyadic_wide (void) | |
14187 | { | |
14188 | struct neon_type_el et = neon_check_type (3, NS_QQD, | |
14189 | N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); | |
14190 | neon_mixed_length (et, et.size); | |
14191 | } | |
14192 | ||
14193 | static void | |
14194 | do_neon_dyadic_narrow (void) | |
14195 | { | |
14196 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14197 | N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); | |
428e3f1f PB |
14198 | /* Operand sign is unimportant, and the U bit is part of the opcode, |
14199 | so force the operand type to integer. */ | |
14200 | et.type = NT_integer; | |
5287ad62 JB |
14201 | neon_mixed_length (et, et.size / 2); |
14202 | } | |
14203 | ||
14204 | static void | |
14205 | do_neon_mul_sat_scalar_long (void) | |
14206 | { | |
14207 | neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); | |
14208 | } | |
14209 | ||
14210 | static void | |
14211 | do_neon_vmull (void) | |
14212 | { | |
14213 | if (inst.operands[2].isscalar) | |
14214 | do_neon_mac_maybe_scalar_long (); | |
14215 | else | |
14216 | { | |
14217 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14218 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY); | |
14219 | if (et.type == NT_poly) | |
88714cb8 | 14220 | NEON_ENCODE (POLY, inst); |
5287ad62 | 14221 | else |
88714cb8 | 14222 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14223 | /* For polynomial encoding, size field must be 0b00 and the U bit must be |
14224 | zero. Should be OK as-is. */ | |
14225 | neon_mixed_length (et, et.size); | |
14226 | } | |
14227 | } | |
14228 | ||
14229 | static void | |
14230 | do_neon_ext (void) | |
14231 | { | |
037e8744 | 14232 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
5287ad62 JB |
14233 | struct neon_type_el et = neon_check_type (3, rs, |
14234 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14235 | unsigned imm = (inst.operands[3].imm * et.size) / 8; | |
35997600 NC |
14236 | |
14237 | constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), | |
14238 | _("shift out of range")); | |
5287ad62 JB |
14239 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14240 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14241 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14242 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14243 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14244 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
037e8744 | 14245 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 | 14246 | inst.instruction |= imm << 8; |
5f4273c7 | 14247 | |
88714cb8 | 14248 | neon_dp_fixup (&inst); |
5287ad62 JB |
14249 | } |
14250 | ||
14251 | static void | |
14252 | do_neon_rev (void) | |
14253 | { | |
037e8744 | 14254 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14255 | struct neon_type_el et = neon_check_type (2, rs, |
14256 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
14257 | unsigned op = (inst.instruction >> 7) & 3; | |
14258 | /* N (width of reversed regions) is encoded as part of the bitmask. We | |
14259 | extract it here to check the elements to be reversed are smaller. | |
14260 | Otherwise we'd get a reserved instruction. */ | |
14261 | unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; | |
9c2799c2 | 14262 | gas_assert (elsize != 0); |
5287ad62 JB |
14263 | constraint (et.size >= elsize, |
14264 | _("elements must be smaller than reversal region")); | |
037e8744 | 14265 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14266 | } |
14267 | ||
14268 | static void | |
14269 | do_neon_dup (void) | |
14270 | { | |
14271 | if (inst.operands[1].isscalar) | |
14272 | { | |
037e8744 | 14273 | enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); |
dcbf9037 JB |
14274 | struct neon_type_el et = neon_check_type (2, rs, |
14275 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
5287ad62 | 14276 | unsigned sizebits = et.size >> 3; |
dcbf9037 | 14277 | unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); |
5287ad62 | 14278 | int logsize = neon_logbits (et.size); |
dcbf9037 | 14279 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; |
037e8744 JB |
14280 | |
14281 | if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) | |
14282 | return; | |
14283 | ||
88714cb8 | 14284 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
14285 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14286 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14287 | inst.instruction |= LOW4 (dm); | |
14288 | inst.instruction |= HI1 (dm) << 5; | |
037e8744 | 14289 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14290 | inst.instruction |= x << 17; |
14291 | inst.instruction |= sizebits << 16; | |
5f4273c7 | 14292 | |
88714cb8 | 14293 | neon_dp_fixup (&inst); |
5287ad62 JB |
14294 | } |
14295 | else | |
14296 | { | |
037e8744 JB |
14297 | enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); |
14298 | struct neon_type_el et = neon_check_type (2, rs, | |
14299 | N_8 | N_16 | N_32 | N_KEY, N_EQK); | |
5287ad62 | 14300 | /* Duplicate ARM register to lanes of vector. */ |
88714cb8 | 14301 | NEON_ENCODE (ARMREG, inst); |
5287ad62 JB |
14302 | switch (et.size) |
14303 | { | |
14304 | case 8: inst.instruction |= 0x400000; break; | |
14305 | case 16: inst.instruction |= 0x000020; break; | |
14306 | case 32: inst.instruction |= 0x000000; break; | |
14307 | default: break; | |
14308 | } | |
14309 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
14310 | inst.instruction |= LOW4 (inst.operands[0].reg) << 16; | |
14311 | inst.instruction |= HI1 (inst.operands[0].reg) << 7; | |
037e8744 | 14312 | inst.instruction |= neon_quad (rs) << 21; |
5287ad62 JB |
14313 | /* The encoding for this instruction is identical for the ARM and Thumb |
14314 | variants, except for the condition field. */ | |
037e8744 | 14315 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
14316 | } |
14317 | } | |
14318 | ||
14319 | /* VMOV has particularly many variations. It can be one of: | |
14320 | 0. VMOV<c><q> <Qd>, <Qm> | |
14321 | 1. VMOV<c><q> <Dd>, <Dm> | |
14322 | (Register operations, which are VORR with Rm = Rn.) | |
14323 | 2. VMOV<c><q>.<dt> <Qd>, #<imm> | |
14324 | 3. VMOV<c><q>.<dt> <Dd>, #<imm> | |
14325 | (Immediate loads.) | |
14326 | 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> | |
14327 | (ARM register to scalar.) | |
14328 | 5. VMOV<c><q> <Dm>, <Rd>, <Rn> | |
14329 | (Two ARM registers to vector.) | |
14330 | 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> | |
14331 | (Scalar to ARM register.) | |
14332 | 7. VMOV<c><q> <Rd>, <Rn>, <Dm> | |
14333 | (Vector to two ARM registers.) | |
037e8744 JB |
14334 | 8. VMOV.F32 <Sd>, <Sm> |
14335 | 9. VMOV.F64 <Dd>, <Dm> | |
14336 | (VFP register moves.) | |
14337 | 10. VMOV.F32 <Sd>, #imm | |
14338 | 11. VMOV.F64 <Dd>, #imm | |
14339 | (VFP float immediate load.) | |
14340 | 12. VMOV <Rd>, <Sm> | |
14341 | (VFP single to ARM reg.) | |
14342 | 13. VMOV <Sd>, <Rm> | |
14343 | (ARM reg to VFP single.) | |
14344 | 14. VMOV <Rd>, <Re>, <Sn>, <Sm> | |
14345 | (Two ARM regs to two VFP singles.) | |
14346 | 15. VMOV <Sd>, <Se>, <Rn>, <Rm> | |
14347 | (Two VFP singles to two ARM regs.) | |
5f4273c7 | 14348 | |
037e8744 JB |
14349 | These cases can be disambiguated using neon_select_shape, except cases 1/9 |
14350 | and 3/11 which depend on the operand type too. | |
5f4273c7 | 14351 | |
5287ad62 | 14352 | All the encoded bits are hardcoded by this function. |
5f4273c7 | 14353 | |
b7fc2769 JB |
14354 | Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). |
14355 | Cases 5, 7 may be used with VFPv2 and above. | |
5f4273c7 | 14356 | |
5287ad62 | 14357 | FIXME: Some of the checking may be a bit sloppy (in a couple of cases you |
5f4273c7 | 14358 | can specify a type where it doesn't make sense to, and is ignored). */ |
5287ad62 JB |
14359 | |
14360 | static void | |
14361 | do_neon_mov (void) | |
14362 | { | |
037e8744 JB |
14363 | enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, |
14364 | NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, | |
14365 | NS_NULL); | |
14366 | struct neon_type_el et; | |
14367 | const char *ldconst = 0; | |
5287ad62 | 14368 | |
037e8744 | 14369 | switch (rs) |
5287ad62 | 14370 | { |
037e8744 JB |
14371 | case NS_DD: /* case 1/9. */ |
14372 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
14373 | /* It is not an error here if no type is given. */ | |
14374 | inst.error = NULL; | |
14375 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 14376 | { |
037e8744 JB |
14377 | do_vfp_nsyn_opcode ("fcpyd"); |
14378 | break; | |
5287ad62 | 14379 | } |
037e8744 | 14380 | /* fall through. */ |
5287ad62 | 14381 | |
037e8744 JB |
14382 | case NS_QQ: /* case 0/1. */ |
14383 | { | |
14384 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14385 | return; | |
14386 | /* The architecture manual I have doesn't explicitly state which | |
14387 | value the U bit should have for register->register moves, but | |
14388 | the equivalent VORR instruction has U = 0, so do that. */ | |
14389 | inst.instruction = 0x0200110; | |
14390 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14391 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14392 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14393 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14394 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14395 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14396 | inst.instruction |= neon_quad (rs) << 6; | |
14397 | ||
88714cb8 | 14398 | neon_dp_fixup (&inst); |
037e8744 JB |
14399 | } |
14400 | break; | |
5f4273c7 | 14401 | |
037e8744 JB |
14402 | case NS_DI: /* case 3/11. */ |
14403 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
14404 | inst.error = NULL; | |
14405 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 14406 | { |
037e8744 JB |
14407 | /* case 11 (fconstd). */ |
14408 | ldconst = "fconstd"; | |
14409 | goto encode_fconstd; | |
5287ad62 | 14410 | } |
037e8744 JB |
14411 | /* fall through. */ |
14412 | ||
14413 | case NS_QI: /* case 2/3. */ | |
14414 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14415 | return; | |
14416 | inst.instruction = 0x0800010; | |
14417 | neon_move_immediate (); | |
88714cb8 | 14418 | neon_dp_fixup (&inst); |
5287ad62 | 14419 | break; |
5f4273c7 | 14420 | |
037e8744 JB |
14421 | case NS_SR: /* case 4. */ |
14422 | { | |
14423 | unsigned bcdebits = 0; | |
91d6fa6a | 14424 | int logsize; |
037e8744 JB |
14425 | unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); |
14426 | unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); | |
14427 | ||
91d6fa6a NC |
14428 | et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK); |
14429 | logsize = neon_logbits (et.size); | |
14430 | ||
037e8744 JB |
14431 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), |
14432 | _(BAD_FPU)); | |
14433 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
14434 | && et.size != 32, _(BAD_FPU)); | |
14435 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
14436 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
14437 | ||
14438 | switch (et.size) | |
14439 | { | |
14440 | case 8: bcdebits = 0x8; break; | |
14441 | case 16: bcdebits = 0x1; break; | |
14442 | case 32: bcdebits = 0x0; break; | |
14443 | default: ; | |
14444 | } | |
14445 | ||
14446 | bcdebits |= x << logsize; | |
14447 | ||
14448 | inst.instruction = 0xe000b10; | |
14449 | do_vfp_cond_or_thumb (); | |
14450 | inst.instruction |= LOW4 (dn) << 16; | |
14451 | inst.instruction |= HI1 (dn) << 7; | |
14452 | inst.instruction |= inst.operands[1].reg << 12; | |
14453 | inst.instruction |= (bcdebits & 3) << 5; | |
14454 | inst.instruction |= (bcdebits >> 2) << 21; | |
14455 | } | |
14456 | break; | |
5f4273c7 | 14457 | |
037e8744 | 14458 | case NS_DRR: /* case 5 (fmdrr). */ |
b7fc2769 | 14459 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), |
037e8744 | 14460 | _(BAD_FPU)); |
b7fc2769 | 14461 | |
037e8744 JB |
14462 | inst.instruction = 0xc400b10; |
14463 | do_vfp_cond_or_thumb (); | |
14464 | inst.instruction |= LOW4 (inst.operands[0].reg); | |
14465 | inst.instruction |= HI1 (inst.operands[0].reg) << 5; | |
14466 | inst.instruction |= inst.operands[1].reg << 12; | |
14467 | inst.instruction |= inst.operands[2].reg << 16; | |
14468 | break; | |
5f4273c7 | 14469 | |
037e8744 JB |
14470 | case NS_RS: /* case 6. */ |
14471 | { | |
91d6fa6a | 14472 | unsigned logsize; |
037e8744 JB |
14473 | unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); |
14474 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); | |
14475 | unsigned abcdebits = 0; | |
14476 | ||
91d6fa6a NC |
14477 | et = neon_check_type (2, NS_NULL, |
14478 | N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); | |
14479 | logsize = neon_logbits (et.size); | |
14480 | ||
037e8744 JB |
14481 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), |
14482 | _(BAD_FPU)); | |
14483 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
14484 | && et.size != 32, _(BAD_FPU)); | |
14485 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
14486 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
14487 | ||
14488 | switch (et.size) | |
14489 | { | |
14490 | case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; | |
14491 | case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; | |
14492 | case 32: abcdebits = 0x00; break; | |
14493 | default: ; | |
14494 | } | |
14495 | ||
14496 | abcdebits |= x << logsize; | |
14497 | inst.instruction = 0xe100b10; | |
14498 | do_vfp_cond_or_thumb (); | |
14499 | inst.instruction |= LOW4 (dn) << 16; | |
14500 | inst.instruction |= HI1 (dn) << 7; | |
14501 | inst.instruction |= inst.operands[0].reg << 12; | |
14502 | inst.instruction |= (abcdebits & 3) << 5; | |
14503 | inst.instruction |= (abcdebits >> 2) << 21; | |
14504 | } | |
14505 | break; | |
5f4273c7 | 14506 | |
037e8744 JB |
14507 | case NS_RRD: /* case 7 (fmrrd). */ |
14508 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), | |
14509 | _(BAD_FPU)); | |
14510 | ||
14511 | inst.instruction = 0xc500b10; | |
14512 | do_vfp_cond_or_thumb (); | |
14513 | inst.instruction |= inst.operands[0].reg << 12; | |
14514 | inst.instruction |= inst.operands[1].reg << 16; | |
14515 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14516 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14517 | break; | |
5f4273c7 | 14518 | |
037e8744 JB |
14519 | case NS_FF: /* case 8 (fcpys). */ |
14520 | do_vfp_nsyn_opcode ("fcpys"); | |
14521 | break; | |
5f4273c7 | 14522 | |
037e8744 JB |
14523 | case NS_FI: /* case 10 (fconsts). */ |
14524 | ldconst = "fconsts"; | |
14525 | encode_fconstd: | |
14526 | if (is_quarter_float (inst.operands[1].imm)) | |
5287ad62 | 14527 | { |
037e8744 JB |
14528 | inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); |
14529 | do_vfp_nsyn_opcode (ldconst); | |
5287ad62 JB |
14530 | } |
14531 | else | |
037e8744 JB |
14532 | first_error (_("immediate out of range")); |
14533 | break; | |
5f4273c7 | 14534 | |
037e8744 JB |
14535 | case NS_RF: /* case 12 (fmrs). */ |
14536 | do_vfp_nsyn_opcode ("fmrs"); | |
14537 | break; | |
5f4273c7 | 14538 | |
037e8744 JB |
14539 | case NS_FR: /* case 13 (fmsr). */ |
14540 | do_vfp_nsyn_opcode ("fmsr"); | |
14541 | break; | |
5f4273c7 | 14542 | |
037e8744 JB |
14543 | /* The encoders for the fmrrs and fmsrr instructions expect three operands |
14544 | (one of which is a list), but we have parsed four. Do some fiddling to | |
14545 | make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 | |
14546 | expect. */ | |
14547 | case NS_RRFF: /* case 14 (fmrrs). */ | |
14548 | constraint (inst.operands[3].reg != inst.operands[2].reg + 1, | |
14549 | _("VFP registers must be adjacent")); | |
14550 | inst.operands[2].imm = 2; | |
14551 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
14552 | do_vfp_nsyn_opcode ("fmrrs"); | |
14553 | break; | |
5f4273c7 | 14554 | |
037e8744 JB |
14555 | case NS_FFRR: /* case 15 (fmsrr). */ |
14556 | constraint (inst.operands[1].reg != inst.operands[0].reg + 1, | |
14557 | _("VFP registers must be adjacent")); | |
14558 | inst.operands[1] = inst.operands[2]; | |
14559 | inst.operands[2] = inst.operands[3]; | |
14560 | inst.operands[0].imm = 2; | |
14561 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
14562 | do_vfp_nsyn_opcode ("fmsrr"); | |
5287ad62 | 14563 | break; |
5f4273c7 | 14564 | |
5287ad62 JB |
14565 | default: |
14566 | abort (); | |
14567 | } | |
14568 | } | |
14569 | ||
14570 | static void | |
14571 | do_neon_rshift_round_imm (void) | |
14572 | { | |
037e8744 | 14573 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14574 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
14575 | int imm = inst.operands[2].imm; | |
14576 | ||
14577 | /* imm == 0 case is encoded as VMOV for V{R}SHR. */ | |
14578 | if (imm == 0) | |
14579 | { | |
14580 | inst.operands[2].present = 0; | |
14581 | do_neon_mov (); | |
14582 | return; | |
14583 | } | |
14584 | ||
14585 | constraint (imm < 1 || (unsigned)imm > et.size, | |
14586 | _("immediate out of range for shift")); | |
037e8744 | 14587 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
14588 | et.size - imm); |
14589 | } | |
14590 | ||
14591 | static void | |
14592 | do_neon_movl (void) | |
14593 | { | |
14594 | struct neon_type_el et = neon_check_type (2, NS_QD, | |
14595 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
14596 | unsigned sizebits = et.size >> 3; | |
14597 | inst.instruction |= sizebits << 19; | |
14598 | neon_two_same (0, et.type == NT_unsigned, -1); | |
14599 | } | |
14600 | ||
14601 | static void | |
14602 | do_neon_trn (void) | |
14603 | { | |
037e8744 | 14604 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14605 | struct neon_type_el et = neon_check_type (2, rs, |
14606 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
88714cb8 | 14607 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14608 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14609 | } |
14610 | ||
14611 | static void | |
14612 | do_neon_zip_uzp (void) | |
14613 | { | |
037e8744 | 14614 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14615 | struct neon_type_el et = neon_check_type (2, rs, |
14616 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
14617 | if (rs == NS_DD && et.size == 32) | |
14618 | { | |
14619 | /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ | |
14620 | inst.instruction = N_MNEM_vtrn; | |
14621 | do_neon_trn (); | |
14622 | return; | |
14623 | } | |
037e8744 | 14624 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14625 | } |
14626 | ||
14627 | static void | |
14628 | do_neon_sat_abs_neg (void) | |
14629 | { | |
037e8744 | 14630 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14631 | struct neon_type_el et = neon_check_type (2, rs, |
14632 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 14633 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14634 | } |
14635 | ||
14636 | static void | |
14637 | do_neon_pair_long (void) | |
14638 | { | |
037e8744 | 14639 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14640 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); |
14641 | /* Unsigned is encoded in OP field (bit 7) for these instruction. */ | |
14642 | inst.instruction |= (et.type == NT_unsigned) << 7; | |
037e8744 | 14643 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14644 | } |
14645 | ||
14646 | static void | |
14647 | do_neon_recip_est (void) | |
14648 | { | |
037e8744 | 14649 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14650 | struct neon_type_el et = neon_check_type (2, rs, |
14651 | N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); | |
14652 | inst.instruction |= (et.type == NT_float) << 8; | |
037e8744 | 14653 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14654 | } |
14655 | ||
14656 | static void | |
14657 | do_neon_cls (void) | |
14658 | { | |
037e8744 | 14659 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14660 | struct neon_type_el et = neon_check_type (2, rs, |
14661 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 14662 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14663 | } |
14664 | ||
14665 | static void | |
14666 | do_neon_clz (void) | |
14667 | { | |
037e8744 | 14668 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14669 | struct neon_type_el et = neon_check_type (2, rs, |
14670 | N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); | |
037e8744 | 14671 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14672 | } |
14673 | ||
14674 | static void | |
14675 | do_neon_cnt (void) | |
14676 | { | |
037e8744 | 14677 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14678 | struct neon_type_el et = neon_check_type (2, rs, |
14679 | N_EQK | N_INT, N_8 | N_KEY); | |
037e8744 | 14680 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14681 | } |
14682 | ||
14683 | static void | |
14684 | do_neon_swp (void) | |
14685 | { | |
037e8744 JB |
14686 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
14687 | neon_two_same (neon_quad (rs), 1, -1); | |
5287ad62 JB |
14688 | } |
14689 | ||
14690 | static void | |
14691 | do_neon_tbl_tbx (void) | |
14692 | { | |
14693 | unsigned listlenbits; | |
dcbf9037 | 14694 | neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); |
5f4273c7 | 14695 | |
5287ad62 JB |
14696 | if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) |
14697 | { | |
dcbf9037 | 14698 | first_error (_("bad list length for table lookup")); |
5287ad62 JB |
14699 | return; |
14700 | } | |
5f4273c7 | 14701 | |
5287ad62 JB |
14702 | listlenbits = inst.operands[1].imm - 1; |
14703 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14704 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14705 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14706 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14707 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14708 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14709 | inst.instruction |= listlenbits << 8; | |
5f4273c7 | 14710 | |
88714cb8 | 14711 | neon_dp_fixup (&inst); |
5287ad62 JB |
14712 | } |
14713 | ||
14714 | static void | |
14715 | do_neon_ldm_stm (void) | |
14716 | { | |
14717 | /* P, U and L bits are part of bitmask. */ | |
14718 | int is_dbmode = (inst.instruction & (1 << 24)) != 0; | |
14719 | unsigned offsetbits = inst.operands[1].imm * 2; | |
14720 | ||
037e8744 JB |
14721 | if (inst.operands[1].issingle) |
14722 | { | |
14723 | do_vfp_nsyn_ldm_stm (is_dbmode); | |
14724 | return; | |
14725 | } | |
14726 | ||
5287ad62 JB |
14727 | constraint (is_dbmode && !inst.operands[0].writeback, |
14728 | _("writeback (!) must be used for VLDMDB and VSTMDB")); | |
14729 | ||
14730 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
14731 | _("register list must contain at least 1 and at most 16 " | |
14732 | "registers")); | |
14733 | ||
14734 | inst.instruction |= inst.operands[0].reg << 16; | |
14735 | inst.instruction |= inst.operands[0].writeback << 21; | |
14736 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
14737 | inst.instruction |= HI1 (inst.operands[1].reg) << 22; | |
14738 | ||
14739 | inst.instruction |= offsetbits; | |
5f4273c7 | 14740 | |
037e8744 | 14741 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
14742 | } |
14743 | ||
14744 | static void | |
14745 | do_neon_ldr_str (void) | |
14746 | { | |
5287ad62 | 14747 | int is_ldr = (inst.instruction & (1 << 20)) != 0; |
5f4273c7 | 14748 | |
037e8744 JB |
14749 | if (inst.operands[0].issingle) |
14750 | { | |
cd2f129f JB |
14751 | if (is_ldr) |
14752 | do_vfp_nsyn_opcode ("flds"); | |
14753 | else | |
14754 | do_vfp_nsyn_opcode ("fsts"); | |
5287ad62 JB |
14755 | } |
14756 | else | |
5287ad62 | 14757 | { |
cd2f129f JB |
14758 | if (is_ldr) |
14759 | do_vfp_nsyn_opcode ("fldd"); | |
5287ad62 | 14760 | else |
cd2f129f | 14761 | do_vfp_nsyn_opcode ("fstd"); |
5287ad62 | 14762 | } |
5287ad62 JB |
14763 | } |
14764 | ||
14765 | /* "interleave" version also handles non-interleaving register VLD1/VST1 | |
14766 | instructions. */ | |
14767 | ||
14768 | static void | |
14769 | do_neon_ld_st_interleave (void) | |
14770 | { | |
037e8744 | 14771 | struct neon_type_el et = neon_check_type (1, NS_NULL, |
5287ad62 JB |
14772 | N_8 | N_16 | N_32 | N_64); |
14773 | unsigned alignbits = 0; | |
14774 | unsigned idx; | |
14775 | /* The bits in this table go: | |
14776 | 0: register stride of one (0) or two (1) | |
14777 | 1,2: register list length, minus one (1, 2, 3, 4). | |
14778 | 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). | |
14779 | We use -1 for invalid entries. */ | |
14780 | const int typetable[] = | |
14781 | { | |
14782 | 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ | |
14783 | -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ | |
14784 | -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ | |
14785 | -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ | |
14786 | }; | |
14787 | int typebits; | |
14788 | ||
dcbf9037 JB |
14789 | if (et.type == NT_invtype) |
14790 | return; | |
14791 | ||
5287ad62 JB |
14792 | if (inst.operands[1].immisalign) |
14793 | switch (inst.operands[1].imm >> 8) | |
14794 | { | |
14795 | case 64: alignbits = 1; break; | |
14796 | case 128: | |
e23c0ad8 JZ |
14797 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2 |
14798 | && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) | |
5287ad62 JB |
14799 | goto bad_alignment; |
14800 | alignbits = 2; | |
14801 | break; | |
14802 | case 256: | |
e23c0ad8 | 14803 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
5287ad62 JB |
14804 | goto bad_alignment; |
14805 | alignbits = 3; | |
14806 | break; | |
14807 | default: | |
14808 | bad_alignment: | |
dcbf9037 | 14809 | first_error (_("bad alignment")); |
5287ad62 JB |
14810 | return; |
14811 | } | |
14812 | ||
14813 | inst.instruction |= alignbits << 4; | |
14814 | inst.instruction |= neon_logbits (et.size) << 6; | |
14815 | ||
14816 | /* Bits [4:6] of the immediate in a list specifier encode register stride | |
14817 | (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of | |
14818 | VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look | |
14819 | up the right value for "type" in a table based on this value and the given | |
14820 | list style, then stick it back. */ | |
14821 | idx = ((inst.operands[0].imm >> 4) & 7) | |
14822 | | (((inst.instruction >> 8) & 3) << 3); | |
14823 | ||
14824 | typebits = typetable[idx]; | |
5f4273c7 | 14825 | |
5287ad62 JB |
14826 | constraint (typebits == -1, _("bad list type for instruction")); |
14827 | ||
14828 | inst.instruction &= ~0xf00; | |
14829 | inst.instruction |= typebits << 8; | |
14830 | } | |
14831 | ||
14832 | /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. | |
14833 | *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 | |
14834 | otherwise. The variable arguments are a list of pairs of legal (size, align) | |
14835 | values, terminated with -1. */ | |
14836 | ||
14837 | static int | |
14838 | neon_alignment_bit (int size, int align, int *do_align, ...) | |
14839 | { | |
14840 | va_list ap; | |
14841 | int result = FAIL, thissize, thisalign; | |
5f4273c7 | 14842 | |
5287ad62 JB |
14843 | if (!inst.operands[1].immisalign) |
14844 | { | |
14845 | *do_align = 0; | |
14846 | return SUCCESS; | |
14847 | } | |
5f4273c7 | 14848 | |
5287ad62 JB |
14849 | va_start (ap, do_align); |
14850 | ||
14851 | do | |
14852 | { | |
14853 | thissize = va_arg (ap, int); | |
14854 | if (thissize == -1) | |
14855 | break; | |
14856 | thisalign = va_arg (ap, int); | |
14857 | ||
14858 | if (size == thissize && align == thisalign) | |
14859 | result = SUCCESS; | |
14860 | } | |
14861 | while (result != SUCCESS); | |
14862 | ||
14863 | va_end (ap); | |
14864 | ||
14865 | if (result == SUCCESS) | |
14866 | *do_align = 1; | |
14867 | else | |
dcbf9037 | 14868 | first_error (_("unsupported alignment for instruction")); |
5f4273c7 | 14869 | |
5287ad62 JB |
14870 | return result; |
14871 | } | |
14872 | ||
14873 | static void | |
14874 | do_neon_ld_st_lane (void) | |
14875 | { | |
037e8744 | 14876 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
14877 | int align_good, do_align = 0; |
14878 | int logsize = neon_logbits (et.size); | |
14879 | int align = inst.operands[1].imm >> 8; | |
14880 | int n = (inst.instruction >> 8) & 3; | |
14881 | int max_el = 64 / et.size; | |
5f4273c7 | 14882 | |
dcbf9037 JB |
14883 | if (et.type == NT_invtype) |
14884 | return; | |
5f4273c7 | 14885 | |
5287ad62 JB |
14886 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, |
14887 | _("bad list length")); | |
14888 | constraint (NEON_LANE (inst.operands[0].imm) >= max_el, | |
14889 | _("scalar index out of range")); | |
14890 | constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 | |
14891 | && et.size == 8, | |
14892 | _("stride of 2 unavailable when element size is 8")); | |
5f4273c7 | 14893 | |
5287ad62 JB |
14894 | switch (n) |
14895 | { | |
14896 | case 0: /* VLD1 / VST1. */ | |
14897 | align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, | |
14898 | 32, 32, -1); | |
14899 | if (align_good == FAIL) | |
14900 | return; | |
14901 | if (do_align) | |
14902 | { | |
14903 | unsigned alignbits = 0; | |
14904 | switch (et.size) | |
14905 | { | |
14906 | case 16: alignbits = 0x1; break; | |
14907 | case 32: alignbits = 0x3; break; | |
14908 | default: ; | |
14909 | } | |
14910 | inst.instruction |= alignbits << 4; | |
14911 | } | |
14912 | break; | |
14913 | ||
14914 | case 1: /* VLD2 / VST2. */ | |
14915 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, | |
14916 | 32, 64, -1); | |
14917 | if (align_good == FAIL) | |
14918 | return; | |
14919 | if (do_align) | |
14920 | inst.instruction |= 1 << 4; | |
14921 | break; | |
14922 | ||
14923 | case 2: /* VLD3 / VST3. */ | |
14924 | constraint (inst.operands[1].immisalign, | |
14925 | _("can't use alignment with this instruction")); | |
14926 | break; | |
14927 | ||
14928 | case 3: /* VLD4 / VST4. */ | |
14929 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
14930 | 16, 64, 32, 64, 32, 128, -1); | |
14931 | if (align_good == FAIL) | |
14932 | return; | |
14933 | if (do_align) | |
14934 | { | |
14935 | unsigned alignbits = 0; | |
14936 | switch (et.size) | |
14937 | { | |
14938 | case 8: alignbits = 0x1; break; | |
14939 | case 16: alignbits = 0x1; break; | |
14940 | case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; | |
14941 | default: ; | |
14942 | } | |
14943 | inst.instruction |= alignbits << 4; | |
14944 | } | |
14945 | break; | |
14946 | ||
14947 | default: ; | |
14948 | } | |
14949 | ||
14950 | /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ | |
14951 | if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
14952 | inst.instruction |= 1 << (4 + logsize); | |
5f4273c7 | 14953 | |
5287ad62 JB |
14954 | inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); |
14955 | inst.instruction |= logsize << 10; | |
14956 | } | |
14957 | ||
14958 | /* Encode single n-element structure to all lanes VLD<n> instructions. */ | |
14959 | ||
14960 | static void | |
14961 | do_neon_ld_dup (void) | |
14962 | { | |
037e8744 | 14963 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
14964 | int align_good, do_align = 0; |
14965 | ||
dcbf9037 JB |
14966 | if (et.type == NT_invtype) |
14967 | return; | |
14968 | ||
5287ad62 JB |
14969 | switch ((inst.instruction >> 8) & 3) |
14970 | { | |
14971 | case 0: /* VLD1. */ | |
9c2799c2 | 14972 | gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); |
5287ad62 JB |
14973 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, |
14974 | &do_align, 16, 16, 32, 32, -1); | |
14975 | if (align_good == FAIL) | |
14976 | return; | |
14977 | switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) | |
14978 | { | |
14979 | case 1: break; | |
14980 | case 2: inst.instruction |= 1 << 5; break; | |
dcbf9037 | 14981 | default: first_error (_("bad list length")); return; |
5287ad62 JB |
14982 | } |
14983 | inst.instruction |= neon_logbits (et.size) << 6; | |
14984 | break; | |
14985 | ||
14986 | case 1: /* VLD2. */ | |
14987 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, | |
14988 | &do_align, 8, 16, 16, 32, 32, 64, -1); | |
14989 | if (align_good == FAIL) | |
14990 | return; | |
14991 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, | |
14992 | _("bad list length")); | |
14993 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
14994 | inst.instruction |= 1 << 5; | |
14995 | inst.instruction |= neon_logbits (et.size) << 6; | |
14996 | break; | |
14997 | ||
14998 | case 2: /* VLD3. */ | |
14999 | constraint (inst.operands[1].immisalign, | |
15000 | _("can't use alignment with this instruction")); | |
15001 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, | |
15002 | _("bad list length")); | |
15003 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15004 | inst.instruction |= 1 << 5; | |
15005 | inst.instruction |= neon_logbits (et.size) << 6; | |
15006 | break; | |
15007 | ||
15008 | case 3: /* VLD4. */ | |
15009 | { | |
15010 | int align = inst.operands[1].imm >> 8; | |
15011 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
15012 | 16, 64, 32, 64, 32, 128, -1); | |
15013 | if (align_good == FAIL) | |
15014 | return; | |
15015 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, | |
15016 | _("bad list length")); | |
15017 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15018 | inst.instruction |= 1 << 5; | |
15019 | if (et.size == 32 && align == 128) | |
15020 | inst.instruction |= 0x3 << 6; | |
15021 | else | |
15022 | inst.instruction |= neon_logbits (et.size) << 6; | |
15023 | } | |
15024 | break; | |
15025 | ||
15026 | default: ; | |
15027 | } | |
15028 | ||
15029 | inst.instruction |= do_align << 4; | |
15030 | } | |
15031 | ||
15032 | /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those | |
15033 | apart from bits [11:4]. */ | |
15034 | ||
15035 | static void | |
15036 | do_neon_ldx_stx (void) | |
15037 | { | |
b1a769ed DG |
15038 | if (inst.operands[1].isreg) |
15039 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); | |
15040 | ||
5287ad62 JB |
15041 | switch (NEON_LANE (inst.operands[0].imm)) |
15042 | { | |
15043 | case NEON_INTERLEAVE_LANES: | |
88714cb8 | 15044 | NEON_ENCODE (INTERLV, inst); |
5287ad62 JB |
15045 | do_neon_ld_st_interleave (); |
15046 | break; | |
5f4273c7 | 15047 | |
5287ad62 | 15048 | case NEON_ALL_LANES: |
88714cb8 | 15049 | NEON_ENCODE (DUP, inst); |
5287ad62 JB |
15050 | do_neon_ld_dup (); |
15051 | break; | |
5f4273c7 | 15052 | |
5287ad62 | 15053 | default: |
88714cb8 | 15054 | NEON_ENCODE (LANE, inst); |
5287ad62 JB |
15055 | do_neon_ld_st_lane (); |
15056 | } | |
15057 | ||
15058 | /* L bit comes from bit mask. */ | |
15059 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15060 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15061 | inst.instruction |= inst.operands[1].reg << 16; | |
5f4273c7 | 15062 | |
5287ad62 JB |
15063 | if (inst.operands[1].postind) |
15064 | { | |
15065 | int postreg = inst.operands[1].imm & 0xf; | |
15066 | constraint (!inst.operands[1].immisreg, | |
15067 | _("post-index must be a register")); | |
15068 | constraint (postreg == 0xd || postreg == 0xf, | |
15069 | _("bad register for post-index")); | |
15070 | inst.instruction |= postreg; | |
15071 | } | |
15072 | else if (inst.operands[1].writeback) | |
15073 | { | |
15074 | inst.instruction |= 0xd; | |
15075 | } | |
15076 | else | |
5f4273c7 NC |
15077 | inst.instruction |= 0xf; |
15078 | ||
5287ad62 JB |
15079 | if (thumb_mode) |
15080 | inst.instruction |= 0xf9000000; | |
15081 | else | |
15082 | inst.instruction |= 0xf4000000; | |
15083 | } | |
5287ad62 JB |
15084 | \f |
15085 | /* Overall per-instruction processing. */ | |
15086 | ||
15087 | /* We need to be able to fix up arbitrary expressions in some statements. | |
15088 | This is so that we can handle symbols that are an arbitrary distance from | |
15089 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
15090 | which returns part of an address in a form which will be valid for | |
15091 | a data instruction. We do this by pushing the expression into a symbol | |
15092 | in the expr_section, and creating a fix for that. */ | |
15093 | ||
15094 | static void | |
15095 | fix_new_arm (fragS * frag, | |
15096 | int where, | |
15097 | short int size, | |
15098 | expressionS * exp, | |
15099 | int pc_rel, | |
15100 | int reloc) | |
15101 | { | |
15102 | fixS * new_fix; | |
15103 | ||
15104 | switch (exp->X_op) | |
15105 | { | |
15106 | case O_constant: | |
15107 | case O_symbol: | |
15108 | case O_add: | |
15109 | case O_subtract: | |
21d799b5 NC |
15110 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, |
15111 | (enum bfd_reloc_code_real) reloc); | |
5287ad62 JB |
15112 | break; |
15113 | ||
15114 | default: | |
21d799b5 NC |
15115 | new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0, |
15116 | pc_rel, (enum bfd_reloc_code_real) reloc); | |
5287ad62 JB |
15117 | break; |
15118 | } | |
15119 | ||
15120 | /* Mark whether the fix is to a THUMB instruction, or an ARM | |
15121 | instruction. */ | |
15122 | new_fix->tc_fix_data = thumb_mode; | |
15123 | } | |
15124 | ||
15125 | /* Create a frg for an instruction requiring relaxation. */ | |
15126 | static void | |
15127 | output_relax_insn (void) | |
15128 | { | |
15129 | char * to; | |
15130 | symbolS *sym; | |
0110f2b8 PB |
15131 | int offset; |
15132 | ||
6e1cb1a6 PB |
15133 | /* The size of the instruction is unknown, so tie the debug info to the |
15134 | start of the instruction. */ | |
15135 | dwarf2_emit_insn (0); | |
6e1cb1a6 | 15136 | |
0110f2b8 PB |
15137 | switch (inst.reloc.exp.X_op) |
15138 | { | |
15139 | case O_symbol: | |
15140 | sym = inst.reloc.exp.X_add_symbol; | |
15141 | offset = inst.reloc.exp.X_add_number; | |
15142 | break; | |
15143 | case O_constant: | |
15144 | sym = NULL; | |
15145 | offset = inst.reloc.exp.X_add_number; | |
15146 | break; | |
15147 | default: | |
15148 | sym = make_expr_symbol (&inst.reloc.exp); | |
15149 | offset = 0; | |
15150 | break; | |
15151 | } | |
15152 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
15153 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
15154 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
0110f2b8 PB |
15155 | } |
15156 | ||
15157 | /* Write a 32-bit thumb instruction to buf. */ | |
15158 | static void | |
15159 | put_thumb32_insn (char * buf, unsigned long insn) | |
15160 | { | |
15161 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
15162 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
15163 | } | |
15164 | ||
b99bd4ef | 15165 | static void |
c19d1205 | 15166 | output_inst (const char * str) |
b99bd4ef | 15167 | { |
c19d1205 | 15168 | char * to = NULL; |
b99bd4ef | 15169 | |
c19d1205 | 15170 | if (inst.error) |
b99bd4ef | 15171 | { |
c19d1205 | 15172 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
15173 | return; |
15174 | } | |
5f4273c7 NC |
15175 | if (inst.relax) |
15176 | { | |
15177 | output_relax_insn (); | |
0110f2b8 | 15178 | return; |
5f4273c7 | 15179 | } |
c19d1205 ZW |
15180 | if (inst.size == 0) |
15181 | return; | |
b99bd4ef | 15182 | |
c19d1205 | 15183 | to = frag_more (inst.size); |
8dc2430f NC |
15184 | /* PR 9814: Record the thumb mode into the current frag so that we know |
15185 | what type of NOP padding to use, if necessary. We override any previous | |
15186 | setting so that if the mode has changed then the NOPS that we use will | |
15187 | match the encoding of the last instruction in the frag. */ | |
cd000bff | 15188 | frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
c19d1205 ZW |
15189 | |
15190 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 15191 | { |
9c2799c2 | 15192 | gas_assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 15193 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 15194 | } |
c19d1205 | 15195 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 15196 | { |
9c2799c2 | 15197 | gas_assert (inst.size == (2 * INSN_SIZE)); |
c19d1205 ZW |
15198 | md_number_to_chars (to, inst.instruction, INSN_SIZE); |
15199 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 15200 | } |
c19d1205 ZW |
15201 | else |
15202 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 15203 | |
c19d1205 ZW |
15204 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
15205 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
15206 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
15207 | inst.reloc.type); | |
b99bd4ef | 15208 | |
c19d1205 | 15209 | dwarf2_emit_insn (inst.size); |
c19d1205 | 15210 | } |
b99bd4ef | 15211 | |
e07e6e58 NC |
15212 | static char * |
15213 | output_it_inst (int cond, int mask, char * to) | |
15214 | { | |
15215 | unsigned long instruction = 0xbf00; | |
15216 | ||
15217 | mask &= 0xf; | |
15218 | instruction |= mask; | |
15219 | instruction |= cond << 4; | |
15220 | ||
15221 | if (to == NULL) | |
15222 | { | |
15223 | to = frag_more (2); | |
15224 | #ifdef OBJ_ELF | |
15225 | dwarf2_emit_insn (2); | |
15226 | #endif | |
15227 | } | |
15228 | ||
15229 | md_number_to_chars (to, instruction, 2); | |
15230 | ||
15231 | return to; | |
15232 | } | |
15233 | ||
c19d1205 ZW |
15234 | /* Tag values used in struct asm_opcode's tag field. */ |
15235 | enum opcode_tag | |
15236 | { | |
15237 | OT_unconditional, /* Instruction cannot be conditionalized. | |
15238 | The ARM condition field is still 0xE. */ | |
15239 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
15240 | and carries 0xF in its ARM condition field. */ | |
15241 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
037e8744 JB |
15242 | OT_csuffixF, /* Some forms of the instruction take a conditional |
15243 | suffix, others place 0xF where the condition field | |
15244 | would be. */ | |
c19d1205 ZW |
15245 | OT_cinfix3, /* Instruction takes a conditional infix, |
15246 | beginning at character index 3. (In | |
15247 | unified mode, it becomes a suffix.) */ | |
088fa78e KH |
15248 | OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for |
15249 | tsts, cmps, cmns, and teqs. */ | |
e3cb604e PB |
15250 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
15251 | character index 3, even in unified mode. Used for | |
15252 | legacy instructions where suffix and infix forms | |
15253 | may be ambiguous. */ | |
c19d1205 | 15254 | OT_csuf_or_in3, /* Instruction takes either a conditional |
e3cb604e | 15255 | suffix or an infix at character index 3. */ |
c19d1205 ZW |
15256 | OT_odd_infix_unc, /* This is the unconditional variant of an |
15257 | instruction that takes a conditional infix | |
15258 | at an unusual position. In unified mode, | |
15259 | this variant will accept a suffix. */ | |
15260 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
15261 | are the conditional variants of instructions that | |
15262 | take conditional infixes in unusual positions. | |
15263 | The infix appears at character index | |
15264 | (tag - OT_odd_infix_0). These are not accepted | |
15265 | in unified mode. */ | |
15266 | }; | |
b99bd4ef | 15267 | |
c19d1205 ZW |
15268 | /* Subroutine of md_assemble, responsible for looking up the primary |
15269 | opcode from the mnemonic the user wrote. STR points to the | |
15270 | beginning of the mnemonic. | |
15271 | ||
15272 | This is not simply a hash table lookup, because of conditional | |
15273 | variants. Most instructions have conditional variants, which are | |
15274 | expressed with a _conditional affix_ to the mnemonic. If we were | |
15275 | to encode each conditional variant as a literal string in the opcode | |
15276 | table, it would have approximately 20,000 entries. | |
15277 | ||
15278 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
15279 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
15280 | instructions take the affix as an infix, notably the s-variants of | |
15281 | the arithmetic instructions. Of those instructions, all but six | |
15282 | have the infix appear after the third character of the mnemonic. | |
15283 | ||
15284 | Accordingly, the algorithm for looking up primary opcodes given | |
15285 | an identifier is: | |
15286 | ||
15287 | 1. Look up the identifier in the opcode table. | |
15288 | If we find a match, go to step U. | |
15289 | ||
15290 | 2. Look up the last two characters of the identifier in the | |
15291 | conditions table. If we find a match, look up the first N-2 | |
15292 | characters of the identifier in the opcode table. If we | |
15293 | find a match, go to step CE. | |
15294 | ||
15295 | 3. Look up the fourth and fifth characters of the identifier in | |
15296 | the conditions table. If we find a match, extract those | |
15297 | characters from the identifier, and look up the remaining | |
15298 | characters in the opcode table. If we find a match, go | |
15299 | to step CM. | |
15300 | ||
15301 | 4. Fail. | |
15302 | ||
15303 | U. Examine the tag field of the opcode structure, in case this is | |
15304 | one of the six instructions with its conditional infix in an | |
15305 | unusual place. If it is, the tag tells us where to find the | |
15306 | infix; look it up in the conditions table and set inst.cond | |
15307 | accordingly. Otherwise, this is an unconditional instruction. | |
15308 | Again set inst.cond accordingly. Return the opcode structure. | |
15309 | ||
15310 | CE. Examine the tag field to make sure this is an instruction that | |
15311 | should receive a conditional suffix. If it is not, fail. | |
15312 | Otherwise, set inst.cond from the suffix we already looked up, | |
15313 | and return the opcode structure. | |
15314 | ||
15315 | CM. Examine the tag field to make sure this is an instruction that | |
15316 | should receive a conditional infix after the third character. | |
15317 | If it is not, fail. Otherwise, undo the edits to the current | |
15318 | line of input and proceed as for case CE. */ | |
15319 | ||
15320 | static const struct asm_opcode * | |
15321 | opcode_lookup (char **str) | |
15322 | { | |
15323 | char *end, *base; | |
15324 | char *affix; | |
15325 | const struct asm_opcode *opcode; | |
15326 | const struct asm_cond *cond; | |
e3cb604e | 15327 | char save[2]; |
c19d1205 ZW |
15328 | |
15329 | /* Scan up to the end of the mnemonic, which must end in white space, | |
721a8186 | 15330 | '.' (in unified mode, or for Neon/VFP instructions), or end of string. */ |
c19d1205 | 15331 | for (base = end = *str; *end != '\0'; end++) |
721a8186 | 15332 | if (*end == ' ' || *end == '.') |
c19d1205 | 15333 | break; |
b99bd4ef | 15334 | |
c19d1205 | 15335 | if (end == base) |
c921be7d | 15336 | return NULL; |
b99bd4ef | 15337 | |
5287ad62 | 15338 | /* Handle a possible width suffix and/or Neon type suffix. */ |
c19d1205 | 15339 | if (end[0] == '.') |
b99bd4ef | 15340 | { |
5287ad62 | 15341 | int offset = 2; |
5f4273c7 | 15342 | |
267d2029 JB |
15343 | /* The .w and .n suffixes are only valid if the unified syntax is in |
15344 | use. */ | |
15345 | if (unified_syntax && end[1] == 'w') | |
c19d1205 | 15346 | inst.size_req = 4; |
267d2029 | 15347 | else if (unified_syntax && end[1] == 'n') |
c19d1205 ZW |
15348 | inst.size_req = 2; |
15349 | else | |
5287ad62 JB |
15350 | offset = 0; |
15351 | ||
15352 | inst.vectype.elems = 0; | |
15353 | ||
15354 | *str = end + offset; | |
b99bd4ef | 15355 | |
5f4273c7 | 15356 | if (end[offset] == '.') |
5287ad62 | 15357 | { |
267d2029 JB |
15358 | /* See if we have a Neon type suffix (possible in either unified or |
15359 | non-unified ARM syntax mode). */ | |
dcbf9037 | 15360 | if (parse_neon_type (&inst.vectype, str) == FAIL) |
c921be7d | 15361 | return NULL; |
5287ad62 JB |
15362 | } |
15363 | else if (end[offset] != '\0' && end[offset] != ' ') | |
c921be7d | 15364 | return NULL; |
b99bd4ef | 15365 | } |
c19d1205 ZW |
15366 | else |
15367 | *str = end; | |
b99bd4ef | 15368 | |
c19d1205 | 15369 | /* Look for unaffixed or special-case affixed mnemonic. */ |
21d799b5 NC |
15370 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
15371 | end - base); | |
c19d1205 | 15372 | if (opcode) |
b99bd4ef | 15373 | { |
c19d1205 ZW |
15374 | /* step U */ |
15375 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 15376 | { |
c19d1205 ZW |
15377 | inst.cond = COND_ALWAYS; |
15378 | return opcode; | |
b99bd4ef | 15379 | } |
b99bd4ef | 15380 | |
278df34e | 15381 | if (warn_on_deprecated && unified_syntax) |
c19d1205 ZW |
15382 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
15383 | affix = base + (opcode->tag - OT_odd_infix_0); | |
21d799b5 | 15384 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
9c2799c2 | 15385 | gas_assert (cond); |
b99bd4ef | 15386 | |
c19d1205 ZW |
15387 | inst.cond = cond->value; |
15388 | return opcode; | |
15389 | } | |
b99bd4ef | 15390 | |
c19d1205 ZW |
15391 | /* Cannot have a conditional suffix on a mnemonic of less than two |
15392 | characters. */ | |
15393 | if (end - base < 3) | |
c921be7d | 15394 | return NULL; |
b99bd4ef | 15395 | |
c19d1205 ZW |
15396 | /* Look for suffixed mnemonic. */ |
15397 | affix = end - 2; | |
21d799b5 NC |
15398 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
15399 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, | |
15400 | affix - base); | |
c19d1205 ZW |
15401 | if (opcode && cond) |
15402 | { | |
15403 | /* step CE */ | |
15404 | switch (opcode->tag) | |
15405 | { | |
e3cb604e PB |
15406 | case OT_cinfix3_legacy: |
15407 | /* Ignore conditional suffixes matched on infix only mnemonics. */ | |
15408 | break; | |
15409 | ||
c19d1205 | 15410 | case OT_cinfix3: |
088fa78e | 15411 | case OT_cinfix3_deprecated: |
c19d1205 ZW |
15412 | case OT_odd_infix_unc: |
15413 | if (!unified_syntax) | |
e3cb604e | 15414 | return 0; |
c19d1205 ZW |
15415 | /* else fall through */ |
15416 | ||
15417 | case OT_csuffix: | |
037e8744 | 15418 | case OT_csuffixF: |
c19d1205 ZW |
15419 | case OT_csuf_or_in3: |
15420 | inst.cond = cond->value; | |
15421 | return opcode; | |
15422 | ||
15423 | case OT_unconditional: | |
15424 | case OT_unconditionalF: | |
dfa9f0d5 | 15425 | if (thumb_mode) |
c921be7d | 15426 | inst.cond = cond->value; |
dfa9f0d5 PB |
15427 | else |
15428 | { | |
c921be7d | 15429 | /* Delayed diagnostic. */ |
dfa9f0d5 PB |
15430 | inst.error = BAD_COND; |
15431 | inst.cond = COND_ALWAYS; | |
15432 | } | |
c19d1205 | 15433 | return opcode; |
b99bd4ef | 15434 | |
c19d1205 | 15435 | default: |
c921be7d | 15436 | return NULL; |
c19d1205 ZW |
15437 | } |
15438 | } | |
b99bd4ef | 15439 | |
c19d1205 ZW |
15440 | /* Cannot have a usual-position infix on a mnemonic of less than |
15441 | six characters (five would be a suffix). */ | |
15442 | if (end - base < 6) | |
c921be7d | 15443 | return NULL; |
b99bd4ef | 15444 | |
c19d1205 ZW |
15445 | /* Look for infixed mnemonic in the usual position. */ |
15446 | affix = base + 3; | |
21d799b5 | 15447 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
e3cb604e | 15448 | if (!cond) |
c921be7d | 15449 | return NULL; |
e3cb604e PB |
15450 | |
15451 | memcpy (save, affix, 2); | |
15452 | memmove (affix, affix + 2, (end - affix) - 2); | |
21d799b5 NC |
15453 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
15454 | (end - base) - 2); | |
e3cb604e PB |
15455 | memmove (affix + 2, affix, (end - affix) - 2); |
15456 | memcpy (affix, save, 2); | |
15457 | ||
088fa78e KH |
15458 | if (opcode |
15459 | && (opcode->tag == OT_cinfix3 | |
15460 | || opcode->tag == OT_cinfix3_deprecated | |
15461 | || opcode->tag == OT_csuf_or_in3 | |
15462 | || opcode->tag == OT_cinfix3_legacy)) | |
b99bd4ef | 15463 | { |
c921be7d | 15464 | /* Step CM. */ |
278df34e | 15465 | if (warn_on_deprecated && unified_syntax |
088fa78e KH |
15466 | && (opcode->tag == OT_cinfix3 |
15467 | || opcode->tag == OT_cinfix3_deprecated)) | |
c19d1205 ZW |
15468 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
15469 | ||
15470 | inst.cond = cond->value; | |
15471 | return opcode; | |
b99bd4ef NC |
15472 | } |
15473 | ||
c921be7d | 15474 | return NULL; |
b99bd4ef NC |
15475 | } |
15476 | ||
e07e6e58 NC |
15477 | /* This function generates an initial IT instruction, leaving its block |
15478 | virtually open for the new instructions. Eventually, | |
15479 | the mask will be updated by now_it_add_mask () each time | |
15480 | a new instruction needs to be included in the IT block. | |
15481 | Finally, the block is closed with close_automatic_it_block (). | |
15482 | The block closure can be requested either from md_assemble (), | |
15483 | a tencode (), or due to a label hook. */ | |
15484 | ||
15485 | static void | |
15486 | new_automatic_it_block (int cond) | |
15487 | { | |
15488 | now_it.state = AUTOMATIC_IT_BLOCK; | |
15489 | now_it.mask = 0x18; | |
15490 | now_it.cc = cond; | |
15491 | now_it.block_length = 1; | |
cd000bff | 15492 | mapping_state (MAP_THUMB); |
e07e6e58 NC |
15493 | now_it.insn = output_it_inst (cond, now_it.mask, NULL); |
15494 | } | |
15495 | ||
15496 | /* Close an automatic IT block. | |
15497 | See comments in new_automatic_it_block (). */ | |
15498 | ||
15499 | static void | |
15500 | close_automatic_it_block (void) | |
15501 | { | |
15502 | now_it.mask = 0x10; | |
15503 | now_it.block_length = 0; | |
15504 | } | |
15505 | ||
15506 | /* Update the mask of the current automatically-generated IT | |
15507 | instruction. See comments in new_automatic_it_block (). */ | |
15508 | ||
15509 | static void | |
15510 | now_it_add_mask (int cond) | |
15511 | { | |
15512 | #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit))) | |
15513 | #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \ | |
15514 | | ((bitvalue) << (nbit))) | |
e07e6e58 | 15515 | const int resulting_bit = (cond & 1); |
c921be7d | 15516 | |
e07e6e58 NC |
15517 | now_it.mask &= 0xf; |
15518 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
15519 | resulting_bit, | |
15520 | (5 - now_it.block_length)); | |
15521 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
15522 | 1, | |
15523 | ((5 - now_it.block_length) - 1) ); | |
15524 | output_it_inst (now_it.cc, now_it.mask, now_it.insn); | |
15525 | ||
15526 | #undef CLEAR_BIT | |
15527 | #undef SET_BIT_VALUE | |
e07e6e58 NC |
15528 | } |
15529 | ||
15530 | /* The IT blocks handling machinery is accessed through the these functions: | |
15531 | it_fsm_pre_encode () from md_assemble () | |
15532 | set_it_insn_type () optional, from the tencode functions | |
15533 | set_it_insn_type_last () ditto | |
15534 | in_it_block () ditto | |
15535 | it_fsm_post_encode () from md_assemble () | |
15536 | force_automatic_it_block_close () from label habdling functions | |
15537 | ||
15538 | Rationale: | |
15539 | 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), | |
15540 | initializing the IT insn type with a generic initial value depending | |
15541 | on the inst.condition. | |
15542 | 2) During the tencode function, two things may happen: | |
15543 | a) The tencode function overrides the IT insn type by | |
15544 | calling either set_it_insn_type (type) or set_it_insn_type_last (). | |
15545 | b) The tencode function queries the IT block state by | |
15546 | calling in_it_block () (i.e. to determine narrow/not narrow mode). | |
15547 | ||
15548 | Both set_it_insn_type and in_it_block run the internal FSM state | |
15549 | handling function (handle_it_state), because: a) setting the IT insn | |
15550 | type may incur in an invalid state (exiting the function), | |
15551 | and b) querying the state requires the FSM to be updated. | |
15552 | Specifically we want to avoid creating an IT block for conditional | |
15553 | branches, so it_fsm_pre_encode is actually a guess and we can't | |
15554 | determine whether an IT block is required until the tencode () routine | |
15555 | has decided what type of instruction this actually it. | |
15556 | Because of this, if set_it_insn_type and in_it_block have to be used, | |
15557 | set_it_insn_type has to be called first. | |
15558 | ||
15559 | set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that | |
15560 | determines the insn IT type depending on the inst.cond code. | |
15561 | When a tencode () routine encodes an instruction that can be | |
15562 | either outside an IT block, or, in the case of being inside, has to be | |
15563 | the last one, set_it_insn_type_last () will determine the proper | |
15564 | IT instruction type based on the inst.cond code. Otherwise, | |
15565 | set_it_insn_type can be called for overriding that logic or | |
15566 | for covering other cases. | |
15567 | ||
15568 | Calling handle_it_state () may not transition the IT block state to | |
15569 | OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be | |
15570 | still queried. Instead, if the FSM determines that the state should | |
15571 | be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed | |
15572 | after the tencode () function: that's what it_fsm_post_encode () does. | |
15573 | ||
15574 | Since in_it_block () calls the state handling function to get an | |
15575 | updated state, an error may occur (due to invalid insns combination). | |
15576 | In that case, inst.error is set. | |
15577 | Therefore, inst.error has to be checked after the execution of | |
15578 | the tencode () routine. | |
15579 | ||
15580 | 3) Back in md_assemble(), it_fsm_post_encode () is called to commit | |
15581 | any pending state change (if any) that didn't take place in | |
15582 | handle_it_state () as explained above. */ | |
15583 | ||
15584 | static void | |
15585 | it_fsm_pre_encode (void) | |
15586 | { | |
15587 | if (inst.cond != COND_ALWAYS) | |
15588 | inst.it_insn_type = INSIDE_IT_INSN; | |
15589 | else | |
15590 | inst.it_insn_type = OUTSIDE_IT_INSN; | |
15591 | ||
15592 | now_it.state_handled = 0; | |
15593 | } | |
15594 | ||
15595 | /* IT state FSM handling function. */ | |
15596 | ||
15597 | static int | |
15598 | handle_it_state (void) | |
15599 | { | |
15600 | now_it.state_handled = 1; | |
15601 | ||
15602 | switch (now_it.state) | |
15603 | { | |
15604 | case OUTSIDE_IT_BLOCK: | |
15605 | switch (inst.it_insn_type) | |
15606 | { | |
15607 | case OUTSIDE_IT_INSN: | |
15608 | break; | |
15609 | ||
15610 | case INSIDE_IT_INSN: | |
15611 | case INSIDE_IT_LAST_INSN: | |
15612 | if (thumb_mode == 0) | |
15613 | { | |
c921be7d | 15614 | if (unified_syntax |
e07e6e58 NC |
15615 | && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM)) |
15616 | as_tsktsk (_("Warning: conditional outside an IT block"\ | |
15617 | " for Thumb.")); | |
15618 | } | |
15619 | else | |
15620 | { | |
15621 | if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB) | |
15622 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)) | |
15623 | { | |
15624 | /* Automatically generate the IT instruction. */ | |
15625 | new_automatic_it_block (inst.cond); | |
15626 | if (inst.it_insn_type == INSIDE_IT_LAST_INSN) | |
15627 | close_automatic_it_block (); | |
15628 | } | |
15629 | else | |
15630 | { | |
15631 | inst.error = BAD_OUT_IT; | |
15632 | return FAIL; | |
15633 | } | |
15634 | } | |
15635 | break; | |
15636 | ||
15637 | case IF_INSIDE_IT_LAST_INSN: | |
15638 | case NEUTRAL_IT_INSN: | |
15639 | break; | |
15640 | ||
15641 | case IT_INSN: | |
15642 | now_it.state = MANUAL_IT_BLOCK; | |
15643 | now_it.block_length = 0; | |
15644 | break; | |
15645 | } | |
15646 | break; | |
15647 | ||
15648 | case AUTOMATIC_IT_BLOCK: | |
15649 | /* Three things may happen now: | |
15650 | a) We should increment current it block size; | |
15651 | b) We should close current it block (closing insn or 4 insns); | |
15652 | c) We should close current it block and start a new one (due | |
15653 | to incompatible conditions or | |
15654 | 4 insns-length block reached). */ | |
15655 | ||
15656 | switch (inst.it_insn_type) | |
15657 | { | |
15658 | case OUTSIDE_IT_INSN: | |
15659 | /* The closure of the block shall happen immediatelly, | |
15660 | so any in_it_block () call reports the block as closed. */ | |
15661 | force_automatic_it_block_close (); | |
15662 | break; | |
15663 | ||
15664 | case INSIDE_IT_INSN: | |
15665 | case INSIDE_IT_LAST_INSN: | |
15666 | case IF_INSIDE_IT_LAST_INSN: | |
15667 | now_it.block_length++; | |
15668 | ||
15669 | if (now_it.block_length > 4 | |
15670 | || !now_it_compatible (inst.cond)) | |
15671 | { | |
15672 | force_automatic_it_block_close (); | |
15673 | if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN) | |
15674 | new_automatic_it_block (inst.cond); | |
15675 | } | |
15676 | else | |
15677 | { | |
15678 | now_it_add_mask (inst.cond); | |
15679 | } | |
15680 | ||
15681 | if (now_it.state == AUTOMATIC_IT_BLOCK | |
15682 | && (inst.it_insn_type == INSIDE_IT_LAST_INSN | |
15683 | || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN)) | |
15684 | close_automatic_it_block (); | |
15685 | break; | |
15686 | ||
15687 | case NEUTRAL_IT_INSN: | |
15688 | now_it.block_length++; | |
15689 | ||
15690 | if (now_it.block_length > 4) | |
15691 | force_automatic_it_block_close (); | |
15692 | else | |
15693 | now_it_add_mask (now_it.cc & 1); | |
15694 | break; | |
15695 | ||
15696 | case IT_INSN: | |
15697 | close_automatic_it_block (); | |
15698 | now_it.state = MANUAL_IT_BLOCK; | |
15699 | break; | |
15700 | } | |
15701 | break; | |
15702 | ||
15703 | case MANUAL_IT_BLOCK: | |
15704 | { | |
15705 | /* Check conditional suffixes. */ | |
15706 | const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1; | |
15707 | int is_last; | |
15708 | now_it.mask <<= 1; | |
15709 | now_it.mask &= 0x1f; | |
15710 | is_last = (now_it.mask == 0x10); | |
15711 | ||
15712 | switch (inst.it_insn_type) | |
15713 | { | |
15714 | case OUTSIDE_IT_INSN: | |
15715 | inst.error = BAD_NOT_IT; | |
15716 | return FAIL; | |
15717 | ||
15718 | case INSIDE_IT_INSN: | |
15719 | if (cond != inst.cond) | |
15720 | { | |
15721 | inst.error = BAD_IT_COND; | |
15722 | return FAIL; | |
15723 | } | |
15724 | break; | |
15725 | ||
15726 | case INSIDE_IT_LAST_INSN: | |
15727 | case IF_INSIDE_IT_LAST_INSN: | |
15728 | if (cond != inst.cond) | |
15729 | { | |
15730 | inst.error = BAD_IT_COND; | |
15731 | return FAIL; | |
15732 | } | |
15733 | if (!is_last) | |
15734 | { | |
15735 | inst.error = BAD_BRANCH; | |
15736 | return FAIL; | |
15737 | } | |
15738 | break; | |
15739 | ||
15740 | case NEUTRAL_IT_INSN: | |
15741 | /* The BKPT instruction is unconditional even in an IT block. */ | |
15742 | break; | |
15743 | ||
15744 | case IT_INSN: | |
15745 | inst.error = BAD_IT_IT; | |
15746 | return FAIL; | |
15747 | } | |
15748 | } | |
15749 | break; | |
15750 | } | |
15751 | ||
15752 | return SUCCESS; | |
15753 | } | |
15754 | ||
15755 | static void | |
15756 | it_fsm_post_encode (void) | |
15757 | { | |
15758 | int is_last; | |
15759 | ||
15760 | if (!now_it.state_handled) | |
15761 | handle_it_state (); | |
15762 | ||
15763 | is_last = (now_it.mask == 0x10); | |
15764 | if (is_last) | |
15765 | { | |
15766 | now_it.state = OUTSIDE_IT_BLOCK; | |
15767 | now_it.mask = 0; | |
15768 | } | |
15769 | } | |
15770 | ||
15771 | static void | |
15772 | force_automatic_it_block_close (void) | |
15773 | { | |
15774 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
15775 | { | |
15776 | close_automatic_it_block (); | |
15777 | now_it.state = OUTSIDE_IT_BLOCK; | |
15778 | now_it.mask = 0; | |
15779 | } | |
15780 | } | |
15781 | ||
15782 | static int | |
15783 | in_it_block (void) | |
15784 | { | |
15785 | if (!now_it.state_handled) | |
15786 | handle_it_state (); | |
15787 | ||
15788 | return now_it.state != OUTSIDE_IT_BLOCK; | |
15789 | } | |
15790 | ||
c19d1205 ZW |
15791 | void |
15792 | md_assemble (char *str) | |
b99bd4ef | 15793 | { |
c19d1205 ZW |
15794 | char *p = str; |
15795 | const struct asm_opcode * opcode; | |
b99bd4ef | 15796 | |
c19d1205 ZW |
15797 | /* Align the previous label if needed. */ |
15798 | if (last_label_seen != NULL) | |
b99bd4ef | 15799 | { |
c19d1205 ZW |
15800 | symbol_set_frag (last_label_seen, frag_now); |
15801 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
15802 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
15803 | } |
15804 | ||
c19d1205 ZW |
15805 | memset (&inst, '\0', sizeof (inst)); |
15806 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 15807 | |
c19d1205 ZW |
15808 | opcode = opcode_lookup (&p); |
15809 | if (!opcode) | |
b99bd4ef | 15810 | { |
c19d1205 | 15811 | /* It wasn't an instruction, but it might be a register alias of |
dcbf9037 | 15812 | the form alias .req reg, or a Neon .dn/.qn directive. */ |
c921be7d NC |
15813 | if (! create_register_alias (str, p) |
15814 | && ! create_neon_reg_alias (str, p)) | |
c19d1205 | 15815 | as_bad (_("bad instruction `%s'"), str); |
b99bd4ef | 15816 | |
b99bd4ef NC |
15817 | return; |
15818 | } | |
15819 | ||
278df34e | 15820 | if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated) |
088fa78e KH |
15821 | as_warn (_("s suffix on comparison instruction is deprecated")); |
15822 | ||
037e8744 JB |
15823 | /* The value which unconditional instructions should have in place of the |
15824 | condition field. */ | |
15825 | inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; | |
15826 | ||
c19d1205 | 15827 | if (thumb_mode) |
b99bd4ef | 15828 | { |
e74cfd16 | 15829 | arm_feature_set variant; |
8f06b2d8 PB |
15830 | |
15831 | variant = cpu_variant; | |
15832 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
e74cfd16 PB |
15833 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
15834 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); | |
c19d1205 | 15835 | /* Check that this instruction is supported for this CPU. */ |
62b3e311 PB |
15836 | if (!opcode->tvariant |
15837 | || (thumb_mode == 1 | |
15838 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) | |
b99bd4ef | 15839 | { |
bf3eeda7 | 15840 | as_bad (_("selected processor does not support Thumb mode `%s'"), str); |
b99bd4ef NC |
15841 | return; |
15842 | } | |
c19d1205 ZW |
15843 | if (inst.cond != COND_ALWAYS && !unified_syntax |
15844 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 15845 | { |
c19d1205 | 15846 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
15847 | return; |
15848 | } | |
15849 | ||
752d5da4 | 15850 | if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)) |
076d447c | 15851 | { |
7e806470 | 15852 | if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23 |
752d5da4 NC |
15853 | && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr) |
15854 | || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier))) | |
15855 | { | |
15856 | /* Two things are addressed here. | |
15857 | 1) Implicit require narrow instructions on Thumb-1. | |
15858 | This avoids relaxation accidentally introducing Thumb-2 | |
15859 | instructions. | |
15860 | 2) Reject wide instructions in non Thumb-2 cores. */ | |
15861 | if (inst.size_req == 0) | |
15862 | inst.size_req = 2; | |
15863 | else if (inst.size_req == 4) | |
15864 | { | |
bf3eeda7 | 15865 | as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str); |
752d5da4 NC |
15866 | return; |
15867 | } | |
15868 | } | |
076d447c PB |
15869 | } |
15870 | ||
c19d1205 ZW |
15871 | inst.instruction = opcode->tvalue; |
15872 | ||
5be8be5d | 15873 | if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE)) |
e07e6e58 NC |
15874 | { |
15875 | /* Prepare the it_insn_type for those encodings that don't set | |
15876 | it. */ | |
15877 | it_fsm_pre_encode (); | |
c19d1205 | 15878 | |
e07e6e58 NC |
15879 | opcode->tencode (); |
15880 | ||
15881 | it_fsm_post_encode (); | |
15882 | } | |
e27ec89e | 15883 | |
0110f2b8 | 15884 | if (!(inst.error || inst.relax)) |
b99bd4ef | 15885 | { |
9c2799c2 | 15886 | gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
c19d1205 ZW |
15887 | inst.size = (inst.instruction > 0xffff ? 4 : 2); |
15888 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 15889 | { |
c19d1205 | 15890 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
15891 | return; |
15892 | } | |
15893 | } | |
076d447c PB |
15894 | |
15895 | /* Something has gone badly wrong if we try to relax a fixed size | |
15896 | instruction. */ | |
9c2799c2 | 15897 | gas_assert (inst.size_req == 0 || !inst.relax); |
076d447c | 15898 | |
e74cfd16 PB |
15899 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
15900 | *opcode->tvariant); | |
ee065d83 | 15901 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
708587a4 | 15902 | set those bits when Thumb-2 32-bit instructions are seen. ie. |
7e806470 | 15903 | anything other than bl/blx and v6-M instructions. |
ee065d83 | 15904 | This is overly pessimistic for relaxable instructions. */ |
7e806470 PB |
15905 | if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) |
15906 | || inst.relax) | |
e07e6e58 NC |
15907 | && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) |
15908 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))) | |
e74cfd16 PB |
15909 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
15910 | arm_ext_v6t2); | |
cd000bff | 15911 | |
88714cb8 DG |
15912 | check_neon_suffixes; |
15913 | ||
cd000bff | 15914 | if (!inst.error) |
c877a2f2 NC |
15915 | { |
15916 | mapping_state (MAP_THUMB); | |
15917 | } | |
c19d1205 | 15918 | } |
3e9e4fcf | 15919 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 | 15920 | { |
845b51d6 PB |
15921 | bfd_boolean is_bx; |
15922 | ||
15923 | /* bx is allowed on v5 cores, and sometimes on v4 cores. */ | |
15924 | is_bx = (opcode->aencode == do_bx); | |
15925 | ||
c19d1205 | 15926 | /* Check that this instruction is supported for this CPU. */ |
845b51d6 PB |
15927 | if (!(is_bx && fix_v4bx) |
15928 | && !(opcode->avariant && | |
15929 | ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))) | |
b99bd4ef | 15930 | { |
bf3eeda7 | 15931 | as_bad (_("selected processor does not support ARM mode `%s'"), str); |
c19d1205 | 15932 | return; |
b99bd4ef | 15933 | } |
c19d1205 | 15934 | if (inst.size_req) |
b99bd4ef | 15935 | { |
c19d1205 ZW |
15936 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
15937 | return; | |
b99bd4ef NC |
15938 | } |
15939 | ||
c19d1205 ZW |
15940 | inst.instruction = opcode->avalue; |
15941 | if (opcode->tag == OT_unconditionalF) | |
15942 | inst.instruction |= 0xF << 28; | |
15943 | else | |
15944 | inst.instruction |= inst.cond << 28; | |
15945 | inst.size = INSN_SIZE; | |
5be8be5d | 15946 | if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE)) |
e07e6e58 NC |
15947 | { |
15948 | it_fsm_pre_encode (); | |
15949 | opcode->aencode (); | |
15950 | it_fsm_post_encode (); | |
15951 | } | |
ee065d83 PB |
15952 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
15953 | on a hypothetical non-thumb v5 core. */ | |
845b51d6 | 15954 | if (is_bx) |
e74cfd16 | 15955 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); |
ee065d83 | 15956 | else |
e74cfd16 PB |
15957 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
15958 | *opcode->avariant); | |
88714cb8 DG |
15959 | |
15960 | check_neon_suffixes; | |
15961 | ||
cd000bff | 15962 | if (!inst.error) |
c877a2f2 NC |
15963 | { |
15964 | mapping_state (MAP_ARM); | |
15965 | } | |
b99bd4ef | 15966 | } |
3e9e4fcf JB |
15967 | else |
15968 | { | |
15969 | as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " | |
15970 | "-- `%s'"), str); | |
15971 | return; | |
15972 | } | |
c19d1205 ZW |
15973 | output_inst (str); |
15974 | } | |
b99bd4ef | 15975 | |
e07e6e58 NC |
15976 | static void |
15977 | check_it_blocks_finished (void) | |
15978 | { | |
15979 | #ifdef OBJ_ELF | |
15980 | asection *sect; | |
15981 | ||
15982 | for (sect = stdoutput->sections; sect != NULL; sect = sect->next) | |
15983 | if (seg_info (sect)->tc_segment_info_data.current_it.state | |
15984 | == MANUAL_IT_BLOCK) | |
15985 | { | |
15986 | as_warn (_("section '%s' finished with an open IT block."), | |
15987 | sect->name); | |
15988 | } | |
15989 | #else | |
15990 | if (now_it.state == MANUAL_IT_BLOCK) | |
15991 | as_warn (_("file finished with an open IT block.")); | |
15992 | #endif | |
15993 | } | |
15994 | ||
c19d1205 ZW |
15995 | /* Various frobbings of labels and their addresses. */ |
15996 | ||
15997 | void | |
15998 | arm_start_line_hook (void) | |
15999 | { | |
16000 | last_label_seen = NULL; | |
b99bd4ef NC |
16001 | } |
16002 | ||
c19d1205 ZW |
16003 | void |
16004 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 16005 | { |
c19d1205 | 16006 | last_label_seen = sym; |
b99bd4ef | 16007 | |
c19d1205 | 16008 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 16009 | |
c19d1205 ZW |
16010 | #if defined OBJ_COFF || defined OBJ_ELF |
16011 | ARM_SET_INTERWORK (sym, support_interwork); | |
16012 | #endif | |
b99bd4ef | 16013 | |
e07e6e58 NC |
16014 | force_automatic_it_block_close (); |
16015 | ||
5f4273c7 | 16016 | /* Note - do not allow local symbols (.Lxxx) to be labelled |
c19d1205 ZW |
16017 | as Thumb functions. This is because these labels, whilst |
16018 | they exist inside Thumb code, are not the entry points for | |
16019 | possible ARM->Thumb calls. Also, these labels can be used | |
16020 | as part of a computed goto or switch statement. eg gcc | |
16021 | can generate code that looks like this: | |
b99bd4ef | 16022 | |
c19d1205 ZW |
16023 | ldr r2, [pc, .Laaa] |
16024 | lsl r3, r3, #2 | |
16025 | ldr r2, [r3, r2] | |
16026 | mov pc, r2 | |
b99bd4ef | 16027 | |
c19d1205 ZW |
16028 | .Lbbb: .word .Lxxx |
16029 | .Lccc: .word .Lyyy | |
16030 | ..etc... | |
16031 | .Laaa: .word Lbbb | |
b99bd4ef | 16032 | |
c19d1205 ZW |
16033 | The first instruction loads the address of the jump table. |
16034 | The second instruction converts a table index into a byte offset. | |
16035 | The third instruction gets the jump address out of the table. | |
16036 | The fourth instruction performs the jump. | |
b99bd4ef | 16037 | |
c19d1205 ZW |
16038 | If the address stored at .Laaa is that of a symbol which has the |
16039 | Thumb_Func bit set, then the linker will arrange for this address | |
16040 | to have the bottom bit set, which in turn would mean that the | |
16041 | address computation performed by the third instruction would end | |
16042 | up with the bottom bit set. Since the ARM is capable of unaligned | |
16043 | word loads, the instruction would then load the incorrect address | |
16044 | out of the jump table, and chaos would ensue. */ | |
16045 | if (label_is_thumb_function_name | |
16046 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
16047 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 16048 | { |
c19d1205 ZW |
16049 | /* When the address of a Thumb function is taken the bottom |
16050 | bit of that address should be set. This will allow | |
16051 | interworking between Arm and Thumb functions to work | |
16052 | correctly. */ | |
b99bd4ef | 16053 | |
c19d1205 | 16054 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 16055 | |
c19d1205 | 16056 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 16057 | } |
07a53e5c | 16058 | |
07a53e5c | 16059 | dwarf2_emit_label (sym); |
b99bd4ef NC |
16060 | } |
16061 | ||
c921be7d | 16062 | bfd_boolean |
c19d1205 | 16063 | arm_data_in_code (void) |
b99bd4ef | 16064 | { |
c19d1205 | 16065 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 16066 | { |
c19d1205 ZW |
16067 | *input_line_pointer = '/'; |
16068 | input_line_pointer += 5; | |
16069 | *input_line_pointer = 0; | |
c921be7d | 16070 | return TRUE; |
b99bd4ef NC |
16071 | } |
16072 | ||
c921be7d | 16073 | return FALSE; |
b99bd4ef NC |
16074 | } |
16075 | ||
c19d1205 ZW |
16076 | char * |
16077 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 16078 | { |
c19d1205 | 16079 | int len; |
b99bd4ef | 16080 | |
c19d1205 ZW |
16081 | if (thumb_mode && (len = strlen (name)) > 5 |
16082 | && streq (name + len - 5, "/data")) | |
16083 | *(name + len - 5) = 0; | |
b99bd4ef | 16084 | |
c19d1205 | 16085 | return name; |
b99bd4ef | 16086 | } |
c19d1205 ZW |
16087 | \f |
16088 | /* Table of all register names defined by default. The user can | |
16089 | define additional names with .req. Note that all register names | |
16090 | should appear in both upper and lowercase variants. Some registers | |
16091 | also have mixed-case names. */ | |
b99bd4ef | 16092 | |
dcbf9037 | 16093 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } |
c19d1205 | 16094 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) |
5287ad62 | 16095 | #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) |
c19d1205 ZW |
16096 | #define REGSET(p,t) \ |
16097 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
16098 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
16099 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
16100 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
5287ad62 JB |
16101 | #define REGSETH(p,t) \ |
16102 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ | |
16103 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ | |
16104 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ | |
16105 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) | |
16106 | #define REGSET2(p,t) \ | |
16107 | REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ | |
16108 | REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ | |
16109 | REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ | |
16110 | REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) | |
7ed4c4c5 | 16111 | |
c19d1205 | 16112 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 16113 | { |
c19d1205 ZW |
16114 | /* ARM integer registers. */ |
16115 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 16116 | |
c19d1205 ZW |
16117 | /* ATPCS synonyms. */ |
16118 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
16119 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
16120 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 16121 | |
c19d1205 ZW |
16122 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
16123 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
16124 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 16125 | |
c19d1205 ZW |
16126 | /* Well-known aliases. */ |
16127 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
16128 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
16129 | ||
16130 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
16131 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
16132 | ||
16133 | /* Coprocessor numbers. */ | |
16134 | REGSET(p, CP), REGSET(P, CP), | |
16135 | ||
16136 | /* Coprocessor register numbers. The "cr" variants are for backward | |
16137 | compatibility. */ | |
16138 | REGSET(c, CN), REGSET(C, CN), | |
16139 | REGSET(cr, CN), REGSET(CR, CN), | |
16140 | ||
16141 | /* FPA registers. */ | |
16142 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
16143 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
16144 | ||
16145 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
16146 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
16147 | ||
16148 | /* VFP SP registers. */ | |
5287ad62 JB |
16149 | REGSET(s,VFS), REGSET(S,VFS), |
16150 | REGSETH(s,VFS), REGSETH(S,VFS), | |
c19d1205 ZW |
16151 | |
16152 | /* VFP DP Registers. */ | |
5287ad62 JB |
16153 | REGSET(d,VFD), REGSET(D,VFD), |
16154 | /* Extra Neon DP registers. */ | |
16155 | REGSETH(d,VFD), REGSETH(D,VFD), | |
16156 | ||
16157 | /* Neon QP registers. */ | |
16158 | REGSET2(q,NQ), REGSET2(Q,NQ), | |
c19d1205 ZW |
16159 | |
16160 | /* VFP control registers. */ | |
16161 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
16162 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
cd2cf30b PB |
16163 | REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), |
16164 | REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), | |
16165 | REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), | |
16166 | REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), | |
c19d1205 ZW |
16167 | |
16168 | /* Maverick DSP coprocessor registers. */ | |
16169 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
16170 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
16171 | ||
16172 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
16173 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
16174 | REGDEF(dspsc,0,DSPSC), | |
16175 | ||
16176 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
16177 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
16178 | REGDEF(DSPSC,0,DSPSC), | |
16179 | ||
16180 | /* iWMMXt data registers - p0, c0-15. */ | |
16181 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
16182 | ||
16183 | /* iWMMXt control registers - p1, c0-3. */ | |
16184 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
16185 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
16186 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
16187 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
16188 | ||
16189 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
16190 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
16191 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
16192 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
16193 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
16194 | ||
16195 | /* XScale accumulator registers. */ | |
16196 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
16197 | }; | |
16198 | #undef REGDEF | |
16199 | #undef REGNUM | |
16200 | #undef REGSET | |
7ed4c4c5 | 16201 | |
c19d1205 ZW |
16202 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
16203 | within psr_required_here. */ | |
16204 | static const struct asm_psr psrs[] = | |
16205 | { | |
16206 | /* Backward compatibility notation. Note that "all" is no longer | |
16207 | truly all possible PSR bits. */ | |
16208 | {"all", PSR_c | PSR_f}, | |
16209 | {"flg", PSR_f}, | |
16210 | {"ctl", PSR_c}, | |
16211 | ||
16212 | /* Individual flags. */ | |
16213 | {"f", PSR_f}, | |
16214 | {"c", PSR_c}, | |
16215 | {"x", PSR_x}, | |
16216 | {"s", PSR_s}, | |
16217 | /* Combinations of flags. */ | |
16218 | {"fs", PSR_f | PSR_s}, | |
16219 | {"fx", PSR_f | PSR_x}, | |
16220 | {"fc", PSR_f | PSR_c}, | |
16221 | {"sf", PSR_s | PSR_f}, | |
16222 | {"sx", PSR_s | PSR_x}, | |
16223 | {"sc", PSR_s | PSR_c}, | |
16224 | {"xf", PSR_x | PSR_f}, | |
16225 | {"xs", PSR_x | PSR_s}, | |
16226 | {"xc", PSR_x | PSR_c}, | |
16227 | {"cf", PSR_c | PSR_f}, | |
16228 | {"cs", PSR_c | PSR_s}, | |
16229 | {"cx", PSR_c | PSR_x}, | |
16230 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
16231 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
16232 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
16233 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
16234 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
16235 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
16236 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
16237 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
16238 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
16239 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
16240 | {"scf", PSR_s | PSR_c | PSR_f}, | |
16241 | {"scx", PSR_s | PSR_c | PSR_x}, | |
16242 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
16243 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
16244 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
16245 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
16246 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
16247 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
16248 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
16249 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
16250 | {"csf", PSR_c | PSR_s | PSR_f}, | |
16251 | {"csx", PSR_c | PSR_s | PSR_x}, | |
16252 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
16253 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
16254 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
16255 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
16256 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
16257 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
16258 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
16259 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
16260 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
16261 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
16262 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
16263 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
16264 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
16265 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
16266 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
16267 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
16268 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
16269 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
16270 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
16271 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
16272 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
16273 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
16274 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
16275 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
16276 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
16277 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
16278 | }; | |
16279 | ||
62b3e311 PB |
16280 | /* Table of V7M psr names. */ |
16281 | static const struct asm_psr v7m_psrs[] = | |
16282 | { | |
2b744c99 PB |
16283 | {"apsr", 0 }, {"APSR", 0 }, |
16284 | {"iapsr", 1 }, {"IAPSR", 1 }, | |
16285 | {"eapsr", 2 }, {"EAPSR", 2 }, | |
16286 | {"psr", 3 }, {"PSR", 3 }, | |
16287 | {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, | |
16288 | {"ipsr", 5 }, {"IPSR", 5 }, | |
16289 | {"epsr", 6 }, {"EPSR", 6 }, | |
16290 | {"iepsr", 7 }, {"IEPSR", 7 }, | |
16291 | {"msp", 8 }, {"MSP", 8 }, | |
16292 | {"psp", 9 }, {"PSP", 9 }, | |
16293 | {"primask", 16}, {"PRIMASK", 16}, | |
16294 | {"basepri", 17}, {"BASEPRI", 17}, | |
16295 | {"basepri_max", 18}, {"BASEPRI_MAX", 18}, | |
16296 | {"faultmask", 19}, {"FAULTMASK", 19}, | |
16297 | {"control", 20}, {"CONTROL", 20} | |
62b3e311 PB |
16298 | }; |
16299 | ||
c19d1205 ZW |
16300 | /* Table of all shift-in-operand names. */ |
16301 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 16302 | { |
c19d1205 ZW |
16303 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
16304 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
16305 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
16306 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
16307 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
16308 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } | |
16309 | }; | |
b99bd4ef | 16310 | |
c19d1205 ZW |
16311 | /* Table of all explicit relocation names. */ |
16312 | #ifdef OBJ_ELF | |
16313 | static struct reloc_entry reloc_names[] = | |
16314 | { | |
16315 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
16316 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
16317 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
16318 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
16319 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
16320 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
16321 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
16322 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
16323 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
16324 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
b43420e6 NC |
16325 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}, |
16326 | { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL} | |
c19d1205 ZW |
16327 | }; |
16328 | #endif | |
b99bd4ef | 16329 | |
c19d1205 ZW |
16330 | /* Table of all conditional affixes. 0xF is not defined as a condition code. */ |
16331 | static const struct asm_cond conds[] = | |
16332 | { | |
16333 | {"eq", 0x0}, | |
16334 | {"ne", 0x1}, | |
16335 | {"cs", 0x2}, {"hs", 0x2}, | |
16336 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
16337 | {"mi", 0x4}, | |
16338 | {"pl", 0x5}, | |
16339 | {"vs", 0x6}, | |
16340 | {"vc", 0x7}, | |
16341 | {"hi", 0x8}, | |
16342 | {"ls", 0x9}, | |
16343 | {"ge", 0xa}, | |
16344 | {"lt", 0xb}, | |
16345 | {"gt", 0xc}, | |
16346 | {"le", 0xd}, | |
16347 | {"al", 0xe} | |
16348 | }; | |
bfae80f2 | 16349 | |
62b3e311 PB |
16350 | static struct asm_barrier_opt barrier_opt_names[] = |
16351 | { | |
52e7f43d RE |
16352 | { "sy", 0xf }, { "SY", 0xf }, |
16353 | { "un", 0x7 }, { "UN", 0x7 }, | |
16354 | { "st", 0xe }, { "ST", 0xe }, | |
16355 | { "unst", 0x6 }, { "UNST", 0x6 }, | |
16356 | { "ish", 0xb }, { "ISH", 0xb }, | |
16357 | { "sh", 0xb }, { "SH", 0xb }, | |
16358 | { "ishst", 0xa }, { "ISHST", 0xa }, | |
16359 | { "shst", 0xa }, { "SHST", 0xa }, | |
16360 | { "nsh", 0x7 }, { "NSH", 0x7 }, | |
16361 | { "nshst", 0x6 }, { "NSHST", 0x6 }, | |
16362 | { "osh", 0x3 }, { "OSH", 0x3 }, | |
16363 | { "oshst", 0x2 }, { "OSHST", 0x2 } | |
62b3e311 PB |
16364 | }; |
16365 | ||
c19d1205 ZW |
16366 | /* Table of ARM-format instructions. */ |
16367 | ||
16368 | /* Macros for gluing together operand strings. N.B. In all cases | |
16369 | other than OPS0, the trailing OP_stop comes from default | |
16370 | zero-initialization of the unspecified elements of the array. */ | |
16371 | #define OPS0() { OP_stop, } | |
16372 | #define OPS1(a) { OP_##a, } | |
16373 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
16374 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
16375 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
16376 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
16377 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
16378 | ||
5be8be5d DG |
16379 | /* These macros are similar to the OPSn, but do not prepend the OP_ prefix. |
16380 | This is useful when mixing operands for ARM and THUMB, i.e. using the | |
16381 | MIX_ARM_THUMB_OPERANDS macro. | |
16382 | In order to use these macros, prefix the number of operands with _ | |
16383 | e.g. _3. */ | |
16384 | #define OPS_1(a) { a, } | |
16385 | #define OPS_2(a,b) { a,b, } | |
16386 | #define OPS_3(a,b,c) { a,b,c, } | |
16387 | #define OPS_4(a,b,c,d) { a,b,c,d, } | |
16388 | #define OPS_5(a,b,c,d,e) { a,b,c,d,e, } | |
16389 | #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, } | |
16390 | ||
c19d1205 ZW |
16391 | /* These macros abstract out the exact format of the mnemonic table and |
16392 | save some repeated characters. */ | |
16393 | ||
16394 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
16395 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16396 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 16397 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16398 | |
16399 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
16400 | a T_MNEM_xyz enumerator. */ | |
16401 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
e07e6e58 | 16402 | TxCE (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 16403 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 16404 | TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
16405 | |
16406 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
16407 | infix after the third character. */ | |
16408 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16409 | { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 16410 | THUMB_VARIANT, do_##ae, do_##te } |
088fa78e | 16411 | #define TxC3w(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 16412 | { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ |
088fa78e | 16413 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 | 16414 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 16415 | TxC3 (mnem, aop, 0x##top, nops, ops, ae, te) |
088fa78e | 16416 | #define TC3w(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 16417 | TxC3w (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 16418 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 16419 | TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
088fa78e | 16420 | #define tC3w(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 16421 | TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
16422 | |
16423 | /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to | |
16424 | appear in the condition table. */ | |
16425 | #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16426 | { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ |
1887dd22 | 16427 | 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16428 | |
16429 | #define TxCM(m1, m2, op, top, nops, ops, ae, te) \ | |
e07e6e58 NC |
16430 | TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \ |
16431 | TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \ | |
16432 | TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \ | |
16433 | TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \ | |
16434 | TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \ | |
16435 | TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \ | |
16436 | TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \ | |
16437 | TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \ | |
16438 | TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \ | |
16439 | TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \ | |
16440 | TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \ | |
16441 | TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \ | |
16442 | TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \ | |
16443 | TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \ | |
16444 | TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \ | |
16445 | TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \ | |
16446 | TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \ | |
16447 | TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \ | |
16448 | TxCM_ (m1, al, m2, op, top, nops, ops, ae, te) | |
c19d1205 ZW |
16449 | |
16450 | #define TCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
e07e6e58 NC |
16451 | TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te) |
16452 | #define tCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
21d799b5 | 16453 | TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
16454 | |
16455 | /* Mnemonic that cannot be conditionalized. The ARM condition-code | |
dfa9f0d5 PB |
16456 | field is still 0xE. Many of the Thumb variants can be executed |
16457 | conditionally, so this is checked separately. */ | |
c19d1205 | 16458 | #define TUE(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 16459 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 16460 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16461 | |
16462 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM | |
16463 | condition code field. */ | |
16464 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16465 | { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 16466 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16467 | |
16468 | /* ARM-only variants of all the above. */ | |
6a86118a | 16469 | #define CE(mnem, op, nops, ops, ae) \ |
21d799b5 | 16470 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
6a86118a NC |
16471 | |
16472 | #define C3(mnem, op, nops, ops, ae) \ | |
16473 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
16474 | ||
e3cb604e PB |
16475 | /* Legacy mnemonics that always have conditional infix after the third |
16476 | character. */ | |
16477 | #define CL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16478 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
16479 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
16480 | ||
8f06b2d8 PB |
16481 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
16482 | #define cCE(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16483 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 16484 | |
e3cb604e PB |
16485 | /* Legacy coprocessor instructions where conditional infix and conditional |
16486 | suffix are ambiguous. For consistency this includes all FPA instructions, | |
16487 | not just the potentially ambiguous ones. */ | |
16488 | #define cCL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16489 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
16490 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
16491 | ||
16492 | /* Coprocessor, takes either a suffix or a position-3 infix | |
16493 | (for an FPA corner case). */ | |
16494 | #define C3E(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16495 | { mnem, OPS##nops ops, OT_csuf_or_in3, \ |
e3cb604e | 16496 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 16497 | |
6a86118a | 16498 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
21d799b5 NC |
16499 | { m1 #m2 m3, OPS##nops ops, \ |
16500 | sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ | |
6a86118a NC |
16501 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
16502 | ||
16503 | #define CM(m1, m2, op, nops, ops, ae) \ | |
e07e6e58 NC |
16504 | xCM_ (m1, , m2, op, nops, ops, ae), \ |
16505 | xCM_ (m1, eq, m2, op, nops, ops, ae), \ | |
16506 | xCM_ (m1, ne, m2, op, nops, ops, ae), \ | |
16507 | xCM_ (m1, cs, m2, op, nops, ops, ae), \ | |
16508 | xCM_ (m1, hs, m2, op, nops, ops, ae), \ | |
16509 | xCM_ (m1, cc, m2, op, nops, ops, ae), \ | |
16510 | xCM_ (m1, ul, m2, op, nops, ops, ae), \ | |
16511 | xCM_ (m1, lo, m2, op, nops, ops, ae), \ | |
16512 | xCM_ (m1, mi, m2, op, nops, ops, ae), \ | |
16513 | xCM_ (m1, pl, m2, op, nops, ops, ae), \ | |
16514 | xCM_ (m1, vs, m2, op, nops, ops, ae), \ | |
16515 | xCM_ (m1, vc, m2, op, nops, ops, ae), \ | |
16516 | xCM_ (m1, hi, m2, op, nops, ops, ae), \ | |
16517 | xCM_ (m1, ls, m2, op, nops, ops, ae), \ | |
16518 | xCM_ (m1, ge, m2, op, nops, ops, ae), \ | |
16519 | xCM_ (m1, lt, m2, op, nops, ops, ae), \ | |
16520 | xCM_ (m1, gt, m2, op, nops, ops, ae), \ | |
16521 | xCM_ (m1, le, m2, op, nops, ops, ae), \ | |
16522 | xCM_ (m1, al, m2, op, nops, ops, ae) | |
6a86118a NC |
16523 | |
16524 | #define UE(mnem, op, nops, ops, ae) \ | |
16525 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
16526 | ||
16527 | #define UF(mnem, op, nops, ops, ae) \ | |
16528 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
16529 | ||
5287ad62 JB |
16530 | /* Neon data-processing. ARM versions are unconditional with cond=0xf. |
16531 | The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we | |
16532 | use the same encoding function for each. */ | |
16533 | #define NUF(mnem, op, nops, ops, enc) \ | |
16534 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ | |
16535 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } | |
16536 | ||
16537 | /* Neon data processing, version which indirects through neon_enc_tab for | |
16538 | the various overloaded versions of opcodes. */ | |
16539 | #define nUF(mnem, op, nops, ops, enc) \ | |
21d799b5 | 16540 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
16541 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
16542 | ||
16543 | /* Neon insn with conditional suffix for the ARM version, non-overloaded | |
16544 | version. */ | |
037e8744 JB |
16545 | #define NCE_tag(mnem, op, nops, ops, enc, tag) \ |
16546 | { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ | |
5287ad62 JB |
16547 | THUMB_VARIANT, do_##enc, do_##enc } |
16548 | ||
037e8744 | 16549 | #define NCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 16550 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
16551 | |
16552 | #define NCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 16553 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 16554 | |
5287ad62 | 16555 | /* Neon insn with conditional suffix for the ARM version, overloaded types. */ |
037e8744 | 16556 | #define nCE_tag(mnem, op, nops, ops, enc, tag) \ |
21d799b5 | 16557 | { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
16558 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
16559 | ||
037e8744 | 16560 | #define nCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 16561 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
16562 | |
16563 | #define nCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 16564 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 16565 | |
c19d1205 ZW |
16566 | #define do_0 0 |
16567 | ||
c19d1205 | 16568 | static const struct asm_opcode insns[] = |
bfae80f2 | 16569 | { |
e74cfd16 PB |
16570 | #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ |
16571 | #define THUMB_VARIANT &arm_ext_v4t | |
21d799b5 NC |
16572 | tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c), |
16573 | tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
16574 | tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
16575 | tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
16576 | tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
16577 | tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
16578 | tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub), | |
16579 | tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub), | |
16580 | tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c), | |
16581 | tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
16582 | tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
16583 | tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
16584 | tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
16585 | tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
16586 | tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3), | |
16587 | tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3), | |
c19d1205 ZW |
16588 | |
16589 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
16590 | for setting PSR flag bits. They are obsolete in V6 and do not | |
16591 | have Thumb equivalents. */ | |
21d799b5 NC |
16592 | tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), |
16593 | tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), | |
16594 | CL("tstp", 110f000, 2, (RR, SH), cmp), | |
16595 | tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
16596 | tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
16597 | CL("cmpp", 150f000, 2, (RR, SH), cmp), | |
16598 | tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
16599 | tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
16600 | CL("cmnp", 170f000, 2, (RR, SH), cmp), | |
16601 | ||
16602 | tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp), | |
16603 | tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp), | |
16604 | tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst), | |
16605 | tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst), | |
16606 | ||
16607 | tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
5be8be5d DG |
16608 | tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), |
16609 | tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR, | |
16610 | OP_RRnpc), | |
16611 | OP_ADDRGLDR),ldst, t_ldst), | |
16612 | tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), | |
21d799b5 NC |
16613 | |
16614 | tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16615 | tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16616 | tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16617 | tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16618 | tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16619 | tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16620 | ||
16621 | TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi), | |
16622 | TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi), | |
16623 | tCE("b", a000000, _b, 1, (EXPr), branch, t_branch), | |
16624 | TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23), | |
bfae80f2 | 16625 | |
c19d1205 | 16626 | /* Pseudo ops. */ |
21d799b5 | 16627 | tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac | 16628 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
21d799b5 | 16629 | tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop), |
c19d1205 ZW |
16630 | |
16631 | /* Thumb-compatibility pseudo ops. */ | |
21d799b5 NC |
16632 | tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift), |
16633 | tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift), | |
16634 | tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift), | |
16635 | tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
16636 | tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift), | |
16637 | tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift), | |
16638 | tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift), | |
16639 | tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift), | |
16640 | tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg), | |
16641 | tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg), | |
16642 | tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop), | |
16643 | tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop), | |
c19d1205 | 16644 | |
16a4cf17 | 16645 | /* These may simplify to neg. */ |
21d799b5 NC |
16646 | TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), |
16647 | TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
16a4cf17 | 16648 | |
c921be7d NC |
16649 | #undef THUMB_VARIANT |
16650 | #define THUMB_VARIANT & arm_ext_v6 | |
16651 | ||
21d799b5 | 16652 | TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
16653 | |
16654 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
c921be7d NC |
16655 | #undef THUMB_VARIANT |
16656 | #define THUMB_VARIANT & arm_ext_v6t2 | |
16657 | ||
21d799b5 NC |
16658 | TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
16659 | TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
16660 | CL("teqp", 130f000, 2, (RR, SH), cmp), | |
c19d1205 | 16661 | |
5be8be5d DG |
16662 | TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), |
16663 | TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
16664 | TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt), | |
16665 | TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
c19d1205 | 16666 | |
21d799b5 NC |
16667 | TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
16668 | TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 16669 | |
21d799b5 NC |
16670 | TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
16671 | TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
16672 | |
16673 | /* V1 instructions with no Thumb analogue at all. */ | |
21d799b5 | 16674 | CE("rsc", 0e00000, 3, (RR, oRR, SH), arit), |
c19d1205 ZW |
16675 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), |
16676 | ||
16677 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
16678 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
16679 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
16680 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
16681 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
16682 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
16683 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
16684 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
16685 | ||
c921be7d NC |
16686 | #undef ARM_VARIANT |
16687 | #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */ | |
16688 | #undef THUMB_VARIANT | |
16689 | #define THUMB_VARIANT & arm_ext_v4t | |
16690 | ||
21d799b5 NC |
16691 | tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
16692 | tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
c19d1205 | 16693 | |
c921be7d NC |
16694 | #undef THUMB_VARIANT |
16695 | #define THUMB_VARIANT & arm_ext_v6t2 | |
16696 | ||
21d799b5 | 16697 | TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
c19d1205 ZW |
16698 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), |
16699 | ||
16700 | /* Generic coprocessor instructions. */ | |
21d799b5 NC |
16701 | TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), |
16702 | TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16703 | TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16704 | TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16705 | TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16706 | TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
16707 | TCE("mrc", e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
c19d1205 | 16708 | |
c921be7d NC |
16709 | #undef ARM_VARIANT |
16710 | #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */ | |
16711 | ||
21d799b5 | 16712 | CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
c19d1205 ZW |
16713 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
16714 | ||
c921be7d NC |
16715 | #undef ARM_VARIANT |
16716 | #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */ | |
16717 | #undef THUMB_VARIANT | |
16718 | #define THUMB_VARIANT & arm_ext_msr | |
16719 | ||
21d799b5 NC |
16720 | TCE("mrs", 10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs), |
16721 | TCE("msr", 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr), | |
c19d1205 | 16722 | |
c921be7d NC |
16723 | #undef ARM_VARIANT |
16724 | #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */ | |
16725 | #undef THUMB_VARIANT | |
16726 | #define THUMB_VARIANT & arm_ext_v6t2 | |
16727 | ||
21d799b5 NC |
16728 | TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
16729 | CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
16730 | TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
16731 | CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
16732 | TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
16733 | CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
16734 | TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
16735 | CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
c19d1205 | 16736 | |
c921be7d NC |
16737 | #undef ARM_VARIANT |
16738 | #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */ | |
16739 | #undef THUMB_VARIANT | |
16740 | #define THUMB_VARIANT & arm_ext_v4t | |
16741 | ||
5be8be5d DG |
16742 | tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
16743 | tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
16744 | tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
16745 | tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
16746 | tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
16747 | tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
c19d1205 | 16748 | |
c921be7d NC |
16749 | #undef ARM_VARIANT |
16750 | #define ARM_VARIANT & arm_ext_v4t_5 | |
16751 | ||
c19d1205 ZW |
16752 | /* ARM Architecture 4T. */ |
16753 | /* Note: bx (and blx) are required on V5, even if the processor does | |
16754 | not support Thumb. */ | |
21d799b5 | 16755 | TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx), |
c19d1205 | 16756 | |
c921be7d NC |
16757 | #undef ARM_VARIANT |
16758 | #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */ | |
16759 | #undef THUMB_VARIANT | |
16760 | #define THUMB_VARIANT & arm_ext_v5t | |
16761 | ||
c19d1205 ZW |
16762 | /* Note: blx has 2 variants; the .value coded here is for |
16763 | BLX(2). Only this variant has conditional execution. */ | |
21d799b5 NC |
16764 | TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx), |
16765 | TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
c19d1205 | 16766 | |
c921be7d NC |
16767 | #undef THUMB_VARIANT |
16768 | #define THUMB_VARIANT & arm_ext_v6t2 | |
16769 | ||
21d799b5 NC |
16770 | TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
16771 | TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16772 | TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16773 | TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16774 | TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16775 | TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
16776 | TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
16777 | TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
c19d1205 | 16778 | |
c921be7d NC |
16779 | #undef ARM_VARIANT |
16780 | #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */ | |
9e3c6df6 PB |
16781 | #undef THUMB_VARIANT |
16782 | #define THUMB_VARIANT &arm_ext_v5exp | |
c921be7d | 16783 | |
21d799b5 NC |
16784 | TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
16785 | TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
16786 | TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
16787 | TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 16788 | |
21d799b5 NC |
16789 | TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
16790 | TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 16791 | |
21d799b5 NC |
16792 | TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), |
16793 | TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
16794 | TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
16795 | TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
c19d1205 | 16796 | |
21d799b5 NC |
16797 | TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
16798 | TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16799 | TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16800 | TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 16801 | |
21d799b5 NC |
16802 | TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
16803 | TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 16804 | |
03ee1b7f NC |
16805 | TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), |
16806 | TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
16807 | TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
16808 | TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
c19d1205 | 16809 | |
c921be7d NC |
16810 | #undef ARM_VARIANT |
16811 | #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */ | |
9e3c6df6 PB |
16812 | #undef THUMB_VARIANT |
16813 | #define THUMB_VARIANT &arm_ext_v6t2 | |
c921be7d | 16814 | |
21d799b5 | 16815 | TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld), |
5be8be5d DG |
16816 | TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS), |
16817 | ldrd, t_ldstd), | |
16818 | TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp, | |
16819 | ADDRGLDRS), ldrd, t_ldstd), | |
c19d1205 | 16820 | |
21d799b5 NC |
16821 | TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
16822 | TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
c19d1205 | 16823 | |
c921be7d NC |
16824 | #undef ARM_VARIANT |
16825 | #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */ | |
16826 | ||
21d799b5 | 16827 | TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
c19d1205 | 16828 | |
c921be7d NC |
16829 | #undef ARM_VARIANT |
16830 | #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */ | |
16831 | #undef THUMB_VARIANT | |
16832 | #define THUMB_VARIANT & arm_ext_v6 | |
16833 | ||
21d799b5 NC |
16834 | TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
16835 | TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
16836 | tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
16837 | tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
16838 | tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
16839 | tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16840 | tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16841 | tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16842 | tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16843 | TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend), | |
c19d1205 | 16844 | |
c921be7d NC |
16845 | #undef THUMB_VARIANT |
16846 | #define THUMB_VARIANT & arm_ext_v6t2 | |
16847 | ||
5be8be5d DG |
16848 | TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex), |
16849 | TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
16850 | strex, t_strex), | |
21d799b5 NC |
16851 | TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
16852 | TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
62b3e311 | 16853 | |
21d799b5 NC |
16854 | TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), |
16855 | TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
62b3e311 | 16856 | |
9e3c6df6 | 16857 | /* ARM V6 not included in V7M. */ |
c921be7d NC |
16858 | #undef THUMB_VARIANT |
16859 | #define THUMB_VARIANT & arm_ext_v6_notm | |
9e3c6df6 PB |
16860 | TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
16861 | UF(rfeib, 9900a00, 1, (RRw), rfe), | |
16862 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
16863 | TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
16864 | TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
16865 | UF(rfefa, 9900a00, 1, (RRw), rfe), | |
16866 | UF(rfeea, 8100a00, 1, (RRw), rfe), | |
16867 | TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
16868 | TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), | |
16869 | UF(srsib, 9c00500, 2, (oRRw, I31w), srs), | |
16870 | UF(srsda, 8400500, 2, (oRRw, I31w), srs), | |
16871 | TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), | |
c921be7d | 16872 | |
9e3c6df6 PB |
16873 | /* ARM V6 not included in V7M (eg. integer SIMD). */ |
16874 | #undef THUMB_VARIANT | |
16875 | #define THUMB_VARIANT & arm_ext_v6_dsp | |
21d799b5 NC |
16876 | TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps), |
16877 | TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), | |
16878 | TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
16879 | TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16880 | TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16881 | TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16882 | /* Old name for QASX. */ |
21d799b5 NC |
16883 | TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16884 | TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16885 | /* Old name for QSAX. */ |
21d799b5 NC |
16886 | TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16887 | TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16888 | TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16889 | TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16890 | TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16891 | TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16892 | /* Old name for SASX. */ |
21d799b5 NC |
16893 | TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16894 | TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16895 | TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16896 | TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16897 | /* Old name for SHASX. */ |
21d799b5 NC |
16898 | TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16899 | TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16900 | /* Old name for SHSAX. */ |
21d799b5 NC |
16901 | TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16902 | TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16903 | TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16904 | TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16905 | /* Old name for SSAX. */ |
21d799b5 NC |
16906 | TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16907 | TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16908 | TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16909 | TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16910 | TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16911 | TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16912 | /* Old name for UASX. */ |
21d799b5 NC |
16913 | TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16914 | TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16915 | TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16916 | TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16917 | /* Old name for UHASX. */ |
21d799b5 NC |
16918 | TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16919 | TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16920 | /* Old name for UHSAX. */ |
21d799b5 NC |
16921 | TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16922 | TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16923 | TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16924 | TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16925 | TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16926 | TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16927 | /* Old name for UQASX. */ |
21d799b5 NC |
16928 | TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16929 | TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16930 | /* Old name for UQSAX. */ |
21d799b5 NC |
16931 | TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16932 | TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16933 | TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16934 | TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16935 | TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16936 | /* Old name for USAX. */ |
21d799b5 NC |
16937 | TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16938 | TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
21d799b5 NC |
16939 | TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
16940 | TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16941 | TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16942 | TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16943 | TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16944 | TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16945 | TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16946 | TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16947 | TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16948 | TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16949 | TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16950 | TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
16951 | TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
16952 | TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16953 | TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16954 | TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
16955 | TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
16956 | TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16957 | TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16958 | TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16959 | TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16960 | TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16961 | TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16962 | TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16963 | TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16964 | TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16965 | TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
21d799b5 NC |
16966 | TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), |
16967 | TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
16968 | TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16969 | TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16970 | TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), | |
c19d1205 | 16971 | |
c921be7d NC |
16972 | #undef ARM_VARIANT |
16973 | #define ARM_VARIANT & arm_ext_v6k | |
16974 | #undef THUMB_VARIANT | |
16975 | #define THUMB_VARIANT & arm_ext_v6k | |
16976 | ||
21d799b5 NC |
16977 | tCE("yield", 320f001, _yield, 0, (), noargs, t_hint), |
16978 | tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint), | |
16979 | tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint), | |
16980 | tCE("sev", 320f004, _sev, 0, (), noargs, t_hint), | |
c19d1205 | 16981 | |
c921be7d NC |
16982 | #undef THUMB_VARIANT |
16983 | #define THUMB_VARIANT & arm_ext_v6_notm | |
5be8be5d DG |
16984 | TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb), |
16985 | ldrexd, t_ldrexd), | |
16986 | TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp, | |
16987 | RRnpcb), strexd, t_strexd), | |
ebdca51a | 16988 | |
c921be7d NC |
16989 | #undef THUMB_VARIANT |
16990 | #define THUMB_VARIANT & arm_ext_v6t2 | |
5be8be5d DG |
16991 | TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb), |
16992 | rd_rn, rd_rn), | |
16993 | TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb), | |
16994 | rd_rn, rd_rn), | |
16995 | TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
16996 | strex, rm_rd_rn), | |
16997 | TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
16998 | strex, rm_rd_rn), | |
21d799b5 | 16999 | TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs), |
c19d1205 | 17000 | |
c921be7d NC |
17001 | #undef ARM_VARIANT |
17002 | #define ARM_VARIANT & arm_ext_v6z | |
17003 | ||
21d799b5 | 17004 | TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 | 17005 | |
c921be7d NC |
17006 | #undef ARM_VARIANT |
17007 | #define ARM_VARIANT & arm_ext_v6t2 | |
17008 | ||
21d799b5 NC |
17009 | TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
17010 | TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
17011 | TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
17012 | TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
c19d1205 | 17013 | |
21d799b5 NC |
17014 | TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
17015 | TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), | |
17016 | TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), | |
17017 | TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), | |
c19d1205 | 17018 | |
5be8be5d DG |
17019 | TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), |
17020 | TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
17021 | TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
17022 | TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
c19d1205 | 17023 | |
bf3eeda7 NS |
17024 | /* Thumb-only instructions. */ |
17025 | #undef ARM_VARIANT | |
17026 | #define ARM_VARIANT NULL | |
17027 | TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz), | |
17028 | TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz), | |
c921be7d NC |
17029 | |
17030 | /* ARM does not really have an IT instruction, so always allow it. | |
17031 | The opcode is copied from Thumb in order to allow warnings in | |
17032 | -mimplicit-it=[never | arm] modes. */ | |
17033 | #undef ARM_VARIANT | |
17034 | #define ARM_VARIANT & arm_ext_v1 | |
17035 | ||
21d799b5 NC |
17036 | TUE("it", bf08, bf08, 1, (COND), it, t_it), |
17037 | TUE("itt", bf0c, bf0c, 1, (COND), it, t_it), | |
17038 | TUE("ite", bf04, bf04, 1, (COND), it, t_it), | |
17039 | TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it), | |
17040 | TUE("itet", bf06, bf06, 1, (COND), it, t_it), | |
17041 | TUE("itte", bf0a, bf0a, 1, (COND), it, t_it), | |
17042 | TUE("itee", bf02, bf02, 1, (COND), it, t_it), | |
17043 | TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it), | |
17044 | TUE("itett", bf07, bf07, 1, (COND), it, t_it), | |
17045 | TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it), | |
17046 | TUE("iteet", bf03, bf03, 1, (COND), it, t_it), | |
17047 | TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it), | |
17048 | TUE("itete", bf05, bf05, 1, (COND), it, t_it), | |
17049 | TUE("ittee", bf09, bf09, 1, (COND), it, t_it), | |
17050 | TUE("iteee", bf01, bf01, 1, (COND), it, t_it), | |
1c444d06 | 17051 | /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */ |
21d799b5 NC |
17052 | TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx), |
17053 | TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx), | |
c19d1205 | 17054 | |
92e90b6e | 17055 | /* Thumb2 only instructions. */ |
c921be7d NC |
17056 | #undef ARM_VARIANT |
17057 | #define ARM_VARIANT NULL | |
92e90b6e | 17058 | |
21d799b5 NC |
17059 | TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), |
17060 | TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
17061 | TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn), | |
17062 | TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn), | |
17063 | TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb), | |
17064 | TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb), | |
92e90b6e | 17065 | |
62b3e311 | 17066 | /* Thumb-2 hardware division instructions (R and M profiles only). */ |
c921be7d NC |
17067 | #undef THUMB_VARIANT |
17068 | #define THUMB_VARIANT & arm_ext_div | |
17069 | ||
21d799b5 NC |
17070 | TCE("sdiv", 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div), |
17071 | TCE("udiv", 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div), | |
62b3e311 | 17072 | |
7e806470 | 17073 | /* ARM V6M/V7 instructions. */ |
c921be7d NC |
17074 | #undef ARM_VARIANT |
17075 | #define ARM_VARIANT & arm_ext_barrier | |
17076 | #undef THUMB_VARIANT | |
17077 | #define THUMB_VARIANT & arm_ext_barrier | |
17078 | ||
52e7f43d RE |
17079 | TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier), |
17080 | TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier), | |
17081 | TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier), | |
7e806470 | 17082 | |
62b3e311 | 17083 | /* ARM V7 instructions. */ |
c921be7d NC |
17084 | #undef ARM_VARIANT |
17085 | #define ARM_VARIANT & arm_ext_v7 | |
17086 | #undef THUMB_VARIANT | |
17087 | #define THUMB_VARIANT & arm_ext_v7 | |
17088 | ||
21d799b5 NC |
17089 | TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld), |
17090 | TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), | |
62b3e311 | 17091 | |
c921be7d NC |
17092 | #undef ARM_VARIANT |
17093 | #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ | |
17094 | ||
21d799b5 NC |
17095 | cCE("wfs", e200110, 1, (RR), rd), |
17096 | cCE("rfs", e300110, 1, (RR), rd), | |
17097 | cCE("wfc", e400110, 1, (RR), rd), | |
17098 | cCE("rfc", e500110, 1, (RR), rd), | |
17099 | ||
17100 | cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17101 | cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17102 | cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17103 | cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17104 | ||
17105 | cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17106 | cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17107 | cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17108 | cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17109 | ||
17110 | cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm), | |
17111 | cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm), | |
17112 | cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm), | |
17113 | cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm), | |
17114 | cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm), | |
17115 | cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm), | |
17116 | cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm), | |
17117 | cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm), | |
17118 | cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm), | |
17119 | cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm), | |
17120 | cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm), | |
17121 | cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm), | |
17122 | ||
17123 | cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm), | |
17124 | cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm), | |
17125 | cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm), | |
17126 | cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm), | |
17127 | cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm), | |
17128 | cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm), | |
17129 | cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm), | |
17130 | cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm), | |
17131 | cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm), | |
17132 | cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm), | |
17133 | cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm), | |
17134 | cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm), | |
17135 | ||
17136 | cCL("abss", e208100, 2, (RF, RF_IF), rd_rm), | |
17137 | cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm), | |
17138 | cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm), | |
17139 | cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm), | |
17140 | cCL("absd", e208180, 2, (RF, RF_IF), rd_rm), | |
17141 | cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm), | |
17142 | cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm), | |
17143 | cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm), | |
17144 | cCL("abse", e288100, 2, (RF, RF_IF), rd_rm), | |
17145 | cCL("absep", e288120, 2, (RF, RF_IF), rd_rm), | |
17146 | cCL("absem", e288140, 2, (RF, RF_IF), rd_rm), | |
17147 | cCL("absez", e288160, 2, (RF, RF_IF), rd_rm), | |
17148 | ||
17149 | cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm), | |
17150 | cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm), | |
17151 | cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm), | |
17152 | cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm), | |
17153 | cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm), | |
17154 | cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm), | |
17155 | cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm), | |
17156 | cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm), | |
17157 | cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm), | |
17158 | cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm), | |
17159 | cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm), | |
17160 | cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm), | |
17161 | ||
17162 | cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm), | |
17163 | cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm), | |
17164 | cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm), | |
17165 | cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm), | |
17166 | cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm), | |
17167 | cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm), | |
17168 | cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm), | |
17169 | cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm), | |
17170 | cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm), | |
17171 | cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm), | |
17172 | cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm), | |
17173 | cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm), | |
17174 | ||
17175 | cCL("logs", e508100, 2, (RF, RF_IF), rd_rm), | |
17176 | cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm), | |
17177 | cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm), | |
17178 | cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm), | |
17179 | cCL("logd", e508180, 2, (RF, RF_IF), rd_rm), | |
17180 | cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm), | |
17181 | cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm), | |
17182 | cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm), | |
17183 | cCL("loge", e588100, 2, (RF, RF_IF), rd_rm), | |
17184 | cCL("logep", e588120, 2, (RF, RF_IF), rd_rm), | |
17185 | cCL("logem", e588140, 2, (RF, RF_IF), rd_rm), | |
17186 | cCL("logez", e588160, 2, (RF, RF_IF), rd_rm), | |
17187 | ||
17188 | cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm), | |
17189 | cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm), | |
17190 | cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm), | |
17191 | cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm), | |
17192 | cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm), | |
17193 | cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm), | |
17194 | cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm), | |
17195 | cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm), | |
17196 | cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm), | |
17197 | cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm), | |
17198 | cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm), | |
17199 | cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm), | |
17200 | ||
17201 | cCL("exps", e708100, 2, (RF, RF_IF), rd_rm), | |
17202 | cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm), | |
17203 | cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm), | |
17204 | cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm), | |
17205 | cCL("expd", e708180, 2, (RF, RF_IF), rd_rm), | |
17206 | cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm), | |
17207 | cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm), | |
17208 | cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm), | |
17209 | cCL("expe", e788100, 2, (RF, RF_IF), rd_rm), | |
17210 | cCL("expep", e788120, 2, (RF, RF_IF), rd_rm), | |
17211 | cCL("expem", e788140, 2, (RF, RF_IF), rd_rm), | |
17212 | cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm), | |
17213 | ||
17214 | cCL("sins", e808100, 2, (RF, RF_IF), rd_rm), | |
17215 | cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm), | |
17216 | cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm), | |
17217 | cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm), | |
17218 | cCL("sind", e808180, 2, (RF, RF_IF), rd_rm), | |
17219 | cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm), | |
17220 | cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm), | |
17221 | cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm), | |
17222 | cCL("sine", e888100, 2, (RF, RF_IF), rd_rm), | |
17223 | cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm), | |
17224 | cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm), | |
17225 | cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm), | |
17226 | ||
17227 | cCL("coss", e908100, 2, (RF, RF_IF), rd_rm), | |
17228 | cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm), | |
17229 | cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm), | |
17230 | cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm), | |
17231 | cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm), | |
17232 | cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm), | |
17233 | cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm), | |
17234 | cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm), | |
17235 | cCL("cose", e988100, 2, (RF, RF_IF), rd_rm), | |
17236 | cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm), | |
17237 | cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm), | |
17238 | cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm), | |
17239 | ||
17240 | cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm), | |
17241 | cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm), | |
17242 | cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm), | |
17243 | cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm), | |
17244 | cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm), | |
17245 | cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm), | |
17246 | cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm), | |
17247 | cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm), | |
17248 | cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm), | |
17249 | cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm), | |
17250 | cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm), | |
17251 | cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm), | |
17252 | ||
17253 | cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm), | |
17254 | cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm), | |
17255 | cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm), | |
17256 | cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm), | |
17257 | cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm), | |
17258 | cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm), | |
17259 | cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm), | |
17260 | cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm), | |
17261 | cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm), | |
17262 | cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm), | |
17263 | cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm), | |
17264 | cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm), | |
17265 | ||
17266 | cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm), | |
17267 | cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm), | |
17268 | cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm), | |
17269 | cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm), | |
17270 | cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm), | |
17271 | cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm), | |
17272 | cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm), | |
17273 | cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm), | |
17274 | cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm), | |
17275 | cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm), | |
17276 | cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm), | |
17277 | cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm), | |
17278 | ||
17279 | cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm), | |
17280 | cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm), | |
17281 | cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm), | |
17282 | cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm), | |
17283 | cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm), | |
17284 | cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm), | |
17285 | cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm), | |
17286 | cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm), | |
17287 | cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm), | |
17288 | cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm), | |
17289 | cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm), | |
17290 | cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm), | |
17291 | ||
17292 | cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm), | |
17293 | cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm), | |
17294 | cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm), | |
17295 | cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm), | |
17296 | cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm), | |
17297 | cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm), | |
17298 | cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm), | |
17299 | cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm), | |
17300 | cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm), | |
17301 | cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm), | |
17302 | cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm), | |
17303 | cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm), | |
17304 | ||
17305 | cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm), | |
17306 | cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm), | |
17307 | cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm), | |
17308 | cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm), | |
17309 | cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm), | |
17310 | cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm), | |
17311 | cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm), | |
17312 | cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm), | |
17313 | cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm), | |
17314 | cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm), | |
17315 | cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm), | |
17316 | cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm), | |
17317 | ||
17318 | cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17319 | cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17320 | cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17321 | cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17322 | cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17323 | cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17324 | cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17325 | cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17326 | cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17327 | cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17328 | cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17329 | cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17330 | ||
17331 | cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17332 | cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17333 | cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17334 | cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17335 | cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17336 | cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17337 | cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17338 | cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17339 | cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17340 | cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17341 | cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17342 | cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17343 | ||
17344 | cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17345 | cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17346 | cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17347 | cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17348 | cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17349 | cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17350 | cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17351 | cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17352 | cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17353 | cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17354 | cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17355 | cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17356 | ||
17357 | cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17358 | cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17359 | cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17360 | cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17361 | cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17362 | cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17363 | cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17364 | cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17365 | cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17366 | cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17367 | cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17368 | cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17369 | ||
17370 | cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17371 | cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17372 | cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17373 | cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17374 | cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17375 | cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17376 | cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17377 | cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17378 | cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17379 | cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17380 | cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17381 | cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17382 | ||
17383 | cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17384 | cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17385 | cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17386 | cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17387 | cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17388 | cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17389 | cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17390 | cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17391 | cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17392 | cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17393 | cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17394 | cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17395 | ||
17396 | cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17397 | cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17398 | cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17399 | cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17400 | cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17401 | cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17402 | cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17403 | cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17404 | cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17405 | cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17406 | cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17407 | cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17408 | ||
17409 | cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17410 | cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17411 | cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17412 | cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17413 | cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17414 | cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17415 | cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17416 | cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17417 | cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17418 | cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17419 | cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17420 | cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17421 | ||
17422 | cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17423 | cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17424 | cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17425 | cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17426 | cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17427 | cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17428 | cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17429 | cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17430 | cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17431 | cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17432 | cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17433 | cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17434 | ||
17435 | cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17436 | cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17437 | cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17438 | cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17439 | cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17440 | cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17441 | cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17442 | cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17443 | cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17444 | cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17445 | cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17446 | cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17447 | ||
17448 | cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17449 | cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17450 | cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17451 | cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17452 | cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17453 | cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17454 | cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17455 | cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17456 | cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17457 | cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17458 | cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17459 | cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17460 | ||
17461 | cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17462 | cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17463 | cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17464 | cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17465 | cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17466 | cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17467 | cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17468 | cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17469 | cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17470 | cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17471 | cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17472 | cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17473 | ||
17474 | cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17475 | cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17476 | cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17477 | cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17478 | cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17479 | cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17480 | cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17481 | cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17482 | cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17483 | cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17484 | cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17485 | cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17486 | ||
17487 | cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp), | |
17488 | C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp), | |
17489 | cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp), | |
17490 | C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp), | |
17491 | ||
17492 | cCL("flts", e000110, 2, (RF, RR), rn_rd), | |
17493 | cCL("fltsp", e000130, 2, (RF, RR), rn_rd), | |
17494 | cCL("fltsm", e000150, 2, (RF, RR), rn_rd), | |
17495 | cCL("fltsz", e000170, 2, (RF, RR), rn_rd), | |
17496 | cCL("fltd", e000190, 2, (RF, RR), rn_rd), | |
17497 | cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd), | |
17498 | cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd), | |
17499 | cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd), | |
17500 | cCL("flte", e080110, 2, (RF, RR), rn_rd), | |
17501 | cCL("fltep", e080130, 2, (RF, RR), rn_rd), | |
17502 | cCL("fltem", e080150, 2, (RF, RR), rn_rd), | |
17503 | cCL("fltez", e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 17504 | |
c19d1205 ZW |
17505 | /* The implementation of the FIX instruction is broken on some |
17506 | assemblers, in that it accepts a precision specifier as well as a | |
17507 | rounding specifier, despite the fact that this is meaningless. | |
17508 | To be more compatible, we accept it as well, though of course it | |
17509 | does not set any bits. */ | |
21d799b5 NC |
17510 | cCE("fix", e100110, 2, (RR, RF), rd_rm), |
17511 | cCL("fixp", e100130, 2, (RR, RF), rd_rm), | |
17512 | cCL("fixm", e100150, 2, (RR, RF), rd_rm), | |
17513 | cCL("fixz", e100170, 2, (RR, RF), rd_rm), | |
17514 | cCL("fixsp", e100130, 2, (RR, RF), rd_rm), | |
17515 | cCL("fixsm", e100150, 2, (RR, RF), rd_rm), | |
17516 | cCL("fixsz", e100170, 2, (RR, RF), rd_rm), | |
17517 | cCL("fixdp", e100130, 2, (RR, RF), rd_rm), | |
17518 | cCL("fixdm", e100150, 2, (RR, RF), rd_rm), | |
17519 | cCL("fixdz", e100170, 2, (RR, RF), rd_rm), | |
17520 | cCL("fixep", e100130, 2, (RR, RF), rd_rm), | |
17521 | cCL("fixem", e100150, 2, (RR, RF), rd_rm), | |
17522 | cCL("fixez", e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 17523 | |
c19d1205 | 17524 | /* Instructions that were new with the real FPA, call them V2. */ |
c921be7d NC |
17525 | #undef ARM_VARIANT |
17526 | #define ARM_VARIANT & fpu_fpa_ext_v2 | |
17527 | ||
21d799b5 NC |
17528 | cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
17529 | cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
17530 | cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
17531 | cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
17532 | cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
17533 | cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 | 17534 | |
c921be7d NC |
17535 | #undef ARM_VARIANT |
17536 | #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ | |
17537 | ||
c19d1205 | 17538 | /* Moves and type conversions. */ |
21d799b5 NC |
17539 | cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
17540 | cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
17541 | cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
17542 | cCE("fmstat", ef1fa10, 0, (), noargs), | |
f7c21dc7 NC |
17543 | cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs), |
17544 | cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr), | |
21d799b5 NC |
17545 | cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), |
17546 | cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
17547 | cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
17548 | cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
17549 | cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
17550 | cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
17551 | cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn), | |
17552 | cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
17553 | |
17554 | /* Memory operations. */ | |
21d799b5 NC |
17555 | cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), |
17556 | cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), | |
55881a11 MGD |
17557 | cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), |
17558 | cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
17559 | cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
17560 | cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
17561 | cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
17562 | cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
17563 | cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
17564 | cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
17565 | cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
17566 | cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
17567 | cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
17568 | cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
17569 | cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
17570 | cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
17571 | cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
17572 | cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 17573 | |
c19d1205 | 17574 | /* Monadic operations. */ |
21d799b5 NC |
17575 | cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
17576 | cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
17577 | cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
17578 | |
17579 | /* Dyadic operations. */ | |
21d799b5 NC |
17580 | cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
17581 | cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17582 | cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17583 | cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17584 | cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17585 | cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17586 | cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17587 | cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17588 | cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 17589 | |
c19d1205 | 17590 | /* Comparisons. */ |
21d799b5 NC |
17591 | cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
17592 | cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z), | |
17593 | cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
17594 | cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 17595 | |
62f3b8c8 PB |
17596 | /* Double precision load/store are still present on single precision |
17597 | implementations. */ | |
17598 | cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
17599 | cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
55881a11 MGD |
17600 | cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), |
17601 | cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
17602 | cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
17603 | cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
17604 | cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
17605 | cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
17606 | cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
17607 | cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
62f3b8c8 | 17608 | |
c921be7d NC |
17609 | #undef ARM_VARIANT |
17610 | #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ | |
17611 | ||
c19d1205 | 17612 | /* Moves and type conversions. */ |
21d799b5 NC |
17613 | cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
17614 | cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
17615 | cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
17616 | cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
17617 | cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
17618 | cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
17619 | cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
17620 | cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
17621 | cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
17622 | cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
17623 | cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
17624 | cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
17625 | cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 | 17626 | |
c19d1205 | 17627 | /* Monadic operations. */ |
21d799b5 NC |
17628 | cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
17629 | cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), | |
17630 | cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
c19d1205 ZW |
17631 | |
17632 | /* Dyadic operations. */ | |
21d799b5 NC |
17633 | cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
17634 | cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17635 | cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17636 | cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17637 | cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17638 | cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17639 | cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17640 | cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17641 | cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
b99bd4ef | 17642 | |
c19d1205 | 17643 | /* Comparisons. */ |
21d799b5 NC |
17644 | cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
17645 | cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd), | |
17646 | cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
17647 | cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd), | |
c19d1205 | 17648 | |
c921be7d NC |
17649 | #undef ARM_VARIANT |
17650 | #define ARM_VARIANT & fpu_vfp_ext_v2 | |
17651 | ||
21d799b5 NC |
17652 | cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
17653 | cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
17654 | cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), | |
17655 | cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), | |
5287ad62 | 17656 | |
037e8744 JB |
17657 | /* Instructions which may belong to either the Neon or VFP instruction sets. |
17658 | Individual encoder functions perform additional architecture checks. */ | |
c921be7d NC |
17659 | #undef ARM_VARIANT |
17660 | #define ARM_VARIANT & fpu_vfp_ext_v1xd | |
17661 | #undef THUMB_VARIANT | |
17662 | #define THUMB_VARIANT & fpu_vfp_ext_v1xd | |
17663 | ||
037e8744 JB |
17664 | /* These mnemonics are unique to VFP. */ |
17665 | NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), | |
17666 | NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), | |
21d799b5 NC |
17667 | nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
17668 | nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
17669 | nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
17670 | nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
17671 | nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
037e8744 JB |
17672 | NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), |
17673 | NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), | |
17674 | NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), | |
17675 | ||
17676 | /* Mnemonics shared by Neon and VFP. */ | |
21d799b5 NC |
17677 | nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), |
17678 | nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
17679 | nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
037e8744 | 17680 | |
21d799b5 NC |
17681 | nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), |
17682 | nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), | |
037e8744 JB |
17683 | |
17684 | NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
17685 | NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
17686 | ||
55881a11 MGD |
17687 | NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
17688 | NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
17689 | NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
17690 | NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
17691 | NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
17692 | NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
4962c51a MS |
17693 | NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), |
17694 | NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), | |
037e8744 | 17695 | |
e3e535bc NC |
17696 | nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt), |
17697 | nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr), | |
21d799b5 NC |
17698 | nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb), |
17699 | nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt), | |
f31fef98 | 17700 | |
037e8744 JB |
17701 | |
17702 | /* NOTE: All VMOV encoding is special-cased! */ | |
17703 | NCE(vmov, 0, 1, (VMOV), neon_mov), | |
17704 | NCE(vmovq, 0, 1, (VMOV), neon_mov), | |
17705 | ||
c921be7d NC |
17706 | #undef THUMB_VARIANT |
17707 | #define THUMB_VARIANT & fpu_neon_ext_v1 | |
17708 | #undef ARM_VARIANT | |
17709 | #define ARM_VARIANT & fpu_neon_ext_v1 | |
17710 | ||
5287ad62 JB |
17711 | /* Data processing with three registers of the same length. */ |
17712 | /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ | |
17713 | NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), | |
17714 | NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), | |
17715 | NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
17716 | NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
17717 | NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
17718 | NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
17719 | NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
17720 | NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
17721 | /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ | |
17722 | NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
17723 | NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
17724 | NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
17725 | NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
627907b7 JB |
17726 | NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), |
17727 | NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
17728 | NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), | |
17729 | NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
5287ad62 JB |
17730 | /* If not immediate, fall back to neon_dyadic_i64_su. |
17731 | shl_imm should accept I8 I16 I32 I64, | |
17732 | qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ | |
21d799b5 NC |
17733 | nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), |
17734 | nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), | |
17735 | nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), | |
17736 | nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), | |
5287ad62 | 17737 | /* Logic ops, types optional & ignored. */ |
4316f0d2 DG |
17738 | nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), |
17739 | nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
17740 | nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
17741 | nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
17742 | nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
17743 | nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
17744 | nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
17745 | nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
17746 | nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), | |
17747 | nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic), | |
5287ad62 JB |
17748 | /* Bitfield ops, untyped. */ |
17749 | NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
17750 | NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
17751 | NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
17752 | NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
17753 | NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
17754 | NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
17755 | /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ | |
21d799b5 NC |
17756 | nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), |
17757 | nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
17758 | nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
17759 | nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
17760 | nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
17761 | nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
5287ad62 JB |
17762 | /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall |
17763 | back to neon_dyadic_if_su. */ | |
21d799b5 NC |
17764 | nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), |
17765 | nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
17766 | nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), | |
17767 | nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
17768 | nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
17769 | nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
17770 | nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
17771 | nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
428e3f1f | 17772 | /* Comparison. Type I8 I16 I32 F32. */ |
21d799b5 NC |
17773 | nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), |
17774 | nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), | |
5287ad62 | 17775 | /* As above, D registers only. */ |
21d799b5 NC |
17776 | nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), |
17777 | nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), | |
5287ad62 | 17778 | /* Int and float variants, signedness unimportant. */ |
21d799b5 NC |
17779 | nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
17780 | nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), | |
17781 | nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), | |
5287ad62 | 17782 | /* Add/sub take types I8 I16 I32 I64 F32. */ |
21d799b5 NC |
17783 | nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
17784 | nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), | |
5287ad62 JB |
17785 | /* vtst takes sizes 8, 16, 32. */ |
17786 | NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), | |
17787 | NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), | |
17788 | /* VMUL takes I8 I16 I32 F32 P8. */ | |
21d799b5 | 17789 | nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), |
5287ad62 | 17790 | /* VQD{R}MULH takes S16 S32. */ |
21d799b5 NC |
17791 | nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), |
17792 | nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
17793 | nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
17794 | nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
5287ad62 JB |
17795 | NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), |
17796 | NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
17797 | NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), | |
17798 | NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
92559b5b PB |
17799 | NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), |
17800 | NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
17801 | NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), | |
17802 | NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
5287ad62 JB |
17803 | NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), |
17804 | NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
17805 | NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), | |
17806 | NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
17807 | ||
17808 | /* Two address, int/float. Types S8 S16 S32 F32. */ | |
5287ad62 | 17809 | NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), |
5287ad62 JB |
17810 | NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), |
17811 | ||
17812 | /* Data processing with two registers and a shift amount. */ | |
17813 | /* Right shifts, and variants with rounding. | |
17814 | Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ | |
17815 | NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
17816 | NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
17817 | NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
17818 | NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
17819 | NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
17820 | NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
17821 | NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
17822 | NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
17823 | /* Shift and insert. Sizes accepted 8 16 32 64. */ | |
17824 | NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), | |
17825 | NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), | |
17826 | NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), | |
17827 | NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), | |
17828 | /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ | |
17829 | NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), | |
17830 | NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), | |
17831 | /* Right shift immediate, saturating & narrowing, with rounding variants. | |
17832 | Types accepted S16 S32 S64 U16 U32 U64. */ | |
17833 | NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
17834 | NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
17835 | /* As above, unsigned. Types accepted S16 S32 S64. */ | |
17836 | NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
17837 | NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
17838 | /* Right shift narrowing. Types accepted I16 I32 I64. */ | |
17839 | NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
17840 | NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
17841 | /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ | |
21d799b5 | 17842 | nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll), |
5287ad62 | 17843 | /* CVT with optional immediate for fixed-point variant. */ |
21d799b5 | 17844 | nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), |
b7fc2769 | 17845 | |
4316f0d2 DG |
17846 | nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn), |
17847 | nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn), | |
5287ad62 JB |
17848 | |
17849 | /* Data processing, three registers of different lengths. */ | |
17850 | /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ | |
17851 | NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), | |
17852 | NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), | |
17853 | NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), | |
17854 | NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), | |
17855 | /* If not scalar, fall back to neon_dyadic_long. | |
17856 | Vector types as above, scalar types S16 S32 U16 U32. */ | |
21d799b5 NC |
17857 | nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), |
17858 | nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), | |
5287ad62 JB |
17859 | /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ |
17860 | NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
17861 | NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
17862 | /* Dyadic, narrowing insns. Types I16 I32 I64. */ | |
17863 | NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
17864 | NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
17865 | NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
17866 | NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
17867 | /* Saturating doubling multiplies. Types S16 S32. */ | |
21d799b5 NC |
17868 | nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), |
17869 | nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
17870 | nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
5287ad62 JB |
17871 | /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types |
17872 | S16 S32 U16 U32. */ | |
21d799b5 | 17873 | nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), |
5287ad62 JB |
17874 | |
17875 | /* Extract. Size 8. */ | |
3b8d421e PB |
17876 | NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), |
17877 | NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), | |
5287ad62 JB |
17878 | |
17879 | /* Two registers, miscellaneous. */ | |
17880 | /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ | |
17881 | NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), | |
17882 | NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), | |
17883 | NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), | |
17884 | NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), | |
17885 | NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), | |
17886 | NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), | |
17887 | /* Vector replicate. Sizes 8 16 32. */ | |
21d799b5 NC |
17888 | nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup), |
17889 | nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup), | |
5287ad62 JB |
17890 | /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ |
17891 | NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), | |
17892 | /* VMOVN. Types I16 I32 I64. */ | |
21d799b5 | 17893 | nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn), |
5287ad62 | 17894 | /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ |
21d799b5 | 17895 | nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn), |
5287ad62 | 17896 | /* VQMOVUN. Types S16 S32 S64. */ |
21d799b5 | 17897 | nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun), |
5287ad62 JB |
17898 | /* VZIP / VUZP. Sizes 8 16 32. */ |
17899 | NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
17900 | NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), | |
17901 | NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
17902 | NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), | |
17903 | /* VQABS / VQNEG. Types S8 S16 S32. */ | |
17904 | NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
17905 | NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
17906 | NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
17907 | NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
17908 | /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ | |
17909 | NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), | |
17910 | NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), | |
17911 | NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), | |
17912 | NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), | |
17913 | /* Reciprocal estimates. Types U32 F32. */ | |
17914 | NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), | |
17915 | NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), | |
17916 | NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), | |
17917 | NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), | |
17918 | /* VCLS. Types S8 S16 S32. */ | |
17919 | NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), | |
17920 | NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), | |
17921 | /* VCLZ. Types I8 I16 I32. */ | |
17922 | NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), | |
17923 | NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), | |
17924 | /* VCNT. Size 8. */ | |
17925 | NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), | |
17926 | NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), | |
17927 | /* Two address, untyped. */ | |
17928 | NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), | |
17929 | NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), | |
17930 | /* VTRN. Sizes 8 16 32. */ | |
21d799b5 NC |
17931 | nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn), |
17932 | nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn), | |
5287ad62 JB |
17933 | |
17934 | /* Table lookup. Size 8. */ | |
17935 | NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
17936 | NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
17937 | ||
c921be7d NC |
17938 | #undef THUMB_VARIANT |
17939 | #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext | |
17940 | #undef ARM_VARIANT | |
17941 | #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext | |
17942 | ||
5287ad62 | 17943 | /* Neon element/structure load/store. */ |
21d799b5 NC |
17944 | nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), |
17945 | nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17946 | nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17947 | nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17948 | nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17949 | nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17950 | nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17951 | nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
5287ad62 | 17952 | |
c921be7d | 17953 | #undef THUMB_VARIANT |
62f3b8c8 PB |
17954 | #define THUMB_VARIANT &fpu_vfp_ext_v3xd |
17955 | #undef ARM_VARIANT | |
17956 | #define ARM_VARIANT &fpu_vfp_ext_v3xd | |
17957 | cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const), | |
17958 | cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
17959 | cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
17960 | cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
17961 | cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
17962 | cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
17963 | cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
17964 | cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
17965 | cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
17966 | ||
17967 | #undef THUMB_VARIANT | |
c921be7d NC |
17968 | #define THUMB_VARIANT & fpu_vfp_ext_v3 |
17969 | #undef ARM_VARIANT | |
17970 | #define ARM_VARIANT & fpu_vfp_ext_v3 | |
17971 | ||
21d799b5 | 17972 | cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const), |
21d799b5 | 17973 | cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 17974 | cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 17975 | cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 17976 | cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 17977 | cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 17978 | cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 17979 | cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 17980 | cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
c19d1205 | 17981 | |
62f3b8c8 PB |
17982 | #undef ARM_VARIANT |
17983 | #define ARM_VARIANT &fpu_vfp_ext_fma | |
17984 | #undef THUMB_VARIANT | |
17985 | #define THUMB_VARIANT &fpu_vfp_ext_fma | |
17986 | /* Mnemonics shared by Neon and VFP. These are included in the | |
17987 | VFP FMA variant; NEON and VFP FMA always includes the NEON | |
17988 | FMA instructions. */ | |
17989 | nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
17990 | nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
17991 | /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas; | |
17992 | the v form should always be used. */ | |
17993 | cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17994 | cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17995 | cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17996 | cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17997 | nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
17998 | nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
17999 | ||
5287ad62 | 18000 | #undef THUMB_VARIANT |
c921be7d NC |
18001 | #undef ARM_VARIANT |
18002 | #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */ | |
18003 | ||
21d799b5 NC |
18004 | cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
18005 | cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18006 | cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18007 | cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18008 | cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18009 | cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18010 | cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
18011 | cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 | 18012 | |
c921be7d NC |
18013 | #undef ARM_VARIANT |
18014 | #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */ | |
18015 | ||
21d799b5 NC |
18016 | cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc), |
18017 | cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc), | |
18018 | cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc), | |
18019 | cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd), | |
18020 | cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd), | |
18021 | cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd), | |
18022 | cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc), | |
18023 | cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc), | |
18024 | cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc), | |
18025 | cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18026 | cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18027 | cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18028 | cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18029 | cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18030 | cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18031 | cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
18032 | cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
18033 | cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
18034 | cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd), | |
18035 | cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn), | |
18036 | cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18037 | cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18038 | cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18039 | cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18040 | cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18041 | cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18042 | cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn), | |
18043 | cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn), | |
18044 | cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn), | |
18045 | cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn), | |
18046 | cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm), | |
18047 | cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc), | |
18048 | cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc), | |
18049 | cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc), | |
18050 | cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn), | |
18051 | cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn), | |
18052 | cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn), | |
18053 | cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18054 | cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18055 | cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18056 | cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18057 | cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18058 | cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18059 | cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18060 | cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18061 | cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18062 | cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
18063 | cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18064 | cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18065 | cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18066 | cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18067 | cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18068 | cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18069 | cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18070 | cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18071 | cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18072 | cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18073 | cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18074 | cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18075 | cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18076 | cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18077 | cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18078 | cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18079 | cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18080 | cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18081 | cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18082 | cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18083 | cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18084 | cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
18085 | cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
18086 | cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18087 | cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18088 | cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18089 | cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18090 | cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18091 | cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18092 | cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18093 | cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18094 | cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18095 | cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18096 | cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18097 | cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18098 | cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18099 | cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18100 | cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18101 | cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18102 | cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18103 | cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18104 | cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
18105 | cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18106 | cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18107 | cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18108 | cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18109 | cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18110 | cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18111 | cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18112 | cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18113 | cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18114 | cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18115 | cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18116 | cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18117 | cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18118 | cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18119 | cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18120 | cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18121 | cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18122 | cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18123 | cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18124 | cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18125 | cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18126 | cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
18127 | cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18128 | cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18129 | cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18130 | cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18131 | cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18132 | cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18133 | cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18134 | cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18135 | cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18136 | cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18137 | cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18138 | cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18139 | cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18140 | cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18141 | cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18142 | cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18143 | cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18144 | cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18145 | cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18146 | cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18147 | cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
18148 | cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
18149 | cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18150 | cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18151 | cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18152 | cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18153 | cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18154 | cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18155 | cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18156 | cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18157 | cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18158 | cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn), | |
18159 | cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn), | |
18160 | cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn), | |
18161 | cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn), | |
18162 | cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn), | |
18163 | cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn), | |
18164 | cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18165 | cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18166 | cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18167 | cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn), | |
18168 | cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn), | |
18169 | cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn), | |
18170 | cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn), | |
18171 | cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn), | |
18172 | cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn), | |
18173 | cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18174 | cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18175 | cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18176 | cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18177 | cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 | 18178 | |
c921be7d NC |
18179 | #undef ARM_VARIANT |
18180 | #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ | |
18181 | ||
21d799b5 NC |
18182 | cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc), |
18183 | cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc), | |
18184 | cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc), | |
18185 | cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn), | |
18186 | cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn), | |
18187 | cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn), | |
18188 | cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18189 | cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18190 | cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18191 | cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18192 | cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18193 | cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18194 | cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18195 | cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18196 | cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18197 | cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18198 | cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18199 | cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18200 | cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18201 | cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18202 | cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), | |
18203 | cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18204 | cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18205 | cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18206 | cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18207 | cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18208 | cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18209 | cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18210 | cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18211 | cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18212 | cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18213 | cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18214 | cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18215 | cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18216 | cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18217 | cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18218 | cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18219 | cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18220 | cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18221 | cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18222 | cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18223 | cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18224 | cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18225 | cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18226 | cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18227 | cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18228 | cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18229 | cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18230 | cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18231 | cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18232 | cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18233 | cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18234 | cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18235 | cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18236 | cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18237 | cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18238 | cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
2d447fca | 18239 | |
c921be7d NC |
18240 | #undef ARM_VARIANT |
18241 | #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */ | |
18242 | ||
21d799b5 NC |
18243 | cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), |
18244 | cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
18245 | cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
18246 | cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
18247 | cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), | |
18248 | cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
18249 | cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
18250 | cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
18251 | cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd), | |
18252 | cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn), | |
18253 | cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd), | |
18254 | cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn), | |
18255 | cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd), | |
18256 | cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn), | |
18257 | cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd), | |
18258 | cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn), | |
18259 | cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd), | |
18260 | cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn), | |
18261 | cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn), | |
18262 | cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn), | |
18263 | cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn), | |
18264 | cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn), | |
18265 | cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn), | |
18266 | cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn), | |
18267 | cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn), | |
18268 | cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn), | |
18269 | cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn), | |
18270 | cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn), | |
18271 | cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc), | |
18272 | cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd), | |
18273 | cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn), | |
18274 | cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn), | |
18275 | cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn), | |
18276 | cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn), | |
18277 | cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn), | |
18278 | cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn), | |
18279 | cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn), | |
18280 | cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn), | |
18281 | cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn), | |
18282 | cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn), | |
18283 | cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn), | |
18284 | cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn), | |
18285 | cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple), | |
18286 | cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
18287 | cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift), | |
18288 | cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
18289 | cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
18290 | cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
18291 | cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
18292 | cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
18293 | cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn), | |
18294 | cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn), | |
18295 | cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn), | |
18296 | cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn), | |
18297 | cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
18298 | cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
18299 | cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
18300 | cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
18301 | cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
18302 | cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
18303 | cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn), | |
18304 | cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn), | |
18305 | cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn), | |
18306 | cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn), | |
18307 | cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18308 | cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
18309 | cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18310 | cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
18311 | cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18312 | cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
18313 | cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18314 | cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18315 | cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
18316 | cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
18317 | cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
18318 | cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
c19d1205 ZW |
18319 | }; |
18320 | #undef ARM_VARIANT | |
18321 | #undef THUMB_VARIANT | |
18322 | #undef TCE | |
18323 | #undef TCM | |
18324 | #undef TUE | |
18325 | #undef TUF | |
18326 | #undef TCC | |
8f06b2d8 | 18327 | #undef cCE |
e3cb604e PB |
18328 | #undef cCL |
18329 | #undef C3E | |
c19d1205 ZW |
18330 | #undef CE |
18331 | #undef CM | |
18332 | #undef UE | |
18333 | #undef UF | |
18334 | #undef UT | |
5287ad62 JB |
18335 | #undef NUF |
18336 | #undef nUF | |
18337 | #undef NCE | |
18338 | #undef nCE | |
c19d1205 ZW |
18339 | #undef OPS0 |
18340 | #undef OPS1 | |
18341 | #undef OPS2 | |
18342 | #undef OPS3 | |
18343 | #undef OPS4 | |
18344 | #undef OPS5 | |
18345 | #undef OPS6 | |
18346 | #undef do_0 | |
18347 | \f | |
18348 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 18349 | |
c19d1205 ZW |
18350 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
18351 | for use in the a.out file, and stores them in the array pointed to by buf. | |
18352 | This knows about the endian-ness of the target machine and does | |
18353 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
18354 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
18355 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 18356 | |
c19d1205 ZW |
18357 | void |
18358 | md_number_to_chars (char * buf, valueT val, int n) | |
18359 | { | |
18360 | if (target_big_endian) | |
18361 | number_to_chars_bigendian (buf, val, n); | |
18362 | else | |
18363 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
18364 | } |
18365 | ||
c19d1205 ZW |
18366 | static valueT |
18367 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 18368 | { |
c19d1205 ZW |
18369 | valueT result = 0; |
18370 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 18371 | |
c19d1205 | 18372 | if (target_big_endian) |
b99bd4ef | 18373 | { |
c19d1205 ZW |
18374 | while (n--) |
18375 | { | |
18376 | result <<= 8; | |
18377 | result |= (*where++ & 255); | |
18378 | } | |
b99bd4ef | 18379 | } |
c19d1205 | 18380 | else |
b99bd4ef | 18381 | { |
c19d1205 ZW |
18382 | while (n--) |
18383 | { | |
18384 | result <<= 8; | |
18385 | result |= (where[n] & 255); | |
18386 | } | |
bfae80f2 | 18387 | } |
b99bd4ef | 18388 | |
c19d1205 | 18389 | return result; |
bfae80f2 | 18390 | } |
b99bd4ef | 18391 | |
c19d1205 | 18392 | /* MD interface: Sections. */ |
b99bd4ef | 18393 | |
0110f2b8 PB |
18394 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
18395 | 2 bytes. */ | |
18396 | ||
c19d1205 | 18397 | int |
0110f2b8 | 18398 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
18399 | segT segtype ATTRIBUTE_UNUSED) |
18400 | { | |
0110f2b8 PB |
18401 | fragp->fr_var = 2; |
18402 | return 2; | |
18403 | } | |
18404 | ||
18405 | /* Convert a machine dependent frag. */ | |
18406 | ||
18407 | void | |
18408 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
18409 | { | |
18410 | unsigned long insn; | |
18411 | unsigned long old_op; | |
18412 | char *buf; | |
18413 | expressionS exp; | |
18414 | fixS *fixp; | |
18415 | int reloc_type; | |
18416 | int pc_rel; | |
18417 | int opcode; | |
18418 | ||
18419 | buf = fragp->fr_literal + fragp->fr_fix; | |
18420 | ||
18421 | old_op = bfd_get_16(abfd, buf); | |
5f4273c7 NC |
18422 | if (fragp->fr_symbol) |
18423 | { | |
0110f2b8 PB |
18424 | exp.X_op = O_symbol; |
18425 | exp.X_add_symbol = fragp->fr_symbol; | |
5f4273c7 NC |
18426 | } |
18427 | else | |
18428 | { | |
0110f2b8 | 18429 | exp.X_op = O_constant; |
5f4273c7 | 18430 | } |
0110f2b8 PB |
18431 | exp.X_add_number = fragp->fr_offset; |
18432 | opcode = fragp->fr_subtype; | |
18433 | switch (opcode) | |
18434 | { | |
18435 | case T_MNEM_ldr_pc: | |
18436 | case T_MNEM_ldr_pc2: | |
18437 | case T_MNEM_ldr_sp: | |
18438 | case T_MNEM_str_sp: | |
18439 | case T_MNEM_ldr: | |
18440 | case T_MNEM_ldrb: | |
18441 | case T_MNEM_ldrh: | |
18442 | case T_MNEM_str: | |
18443 | case T_MNEM_strb: | |
18444 | case T_MNEM_strh: | |
18445 | if (fragp->fr_var == 4) | |
18446 | { | |
5f4273c7 | 18447 | insn = THUMB_OP32 (opcode); |
0110f2b8 PB |
18448 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) |
18449 | { | |
18450 | insn |= (old_op & 0x700) << 4; | |
18451 | } | |
18452 | else | |
18453 | { | |
18454 | insn |= (old_op & 7) << 12; | |
18455 | insn |= (old_op & 0x38) << 13; | |
18456 | } | |
18457 | insn |= 0x00000c00; | |
18458 | put_thumb32_insn (buf, insn); | |
18459 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
18460 | } | |
18461 | else | |
18462 | { | |
18463 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
18464 | } | |
18465 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
18466 | break; | |
18467 | case T_MNEM_adr: | |
18468 | if (fragp->fr_var == 4) | |
18469 | { | |
18470 | insn = THUMB_OP32 (opcode); | |
18471 | insn |= (old_op & 0xf0) << 4; | |
18472 | put_thumb32_insn (buf, insn); | |
18473 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
18474 | } | |
18475 | else | |
18476 | { | |
18477 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
18478 | exp.X_add_number -= 4; | |
18479 | } | |
18480 | pc_rel = 1; | |
18481 | break; | |
18482 | case T_MNEM_mov: | |
18483 | case T_MNEM_movs: | |
18484 | case T_MNEM_cmp: | |
18485 | case T_MNEM_cmn: | |
18486 | if (fragp->fr_var == 4) | |
18487 | { | |
18488 | int r0off = (opcode == T_MNEM_mov | |
18489 | || opcode == T_MNEM_movs) ? 0 : 8; | |
18490 | insn = THUMB_OP32 (opcode); | |
18491 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
18492 | insn |= (old_op & 0x700) << r0off; | |
18493 | put_thumb32_insn (buf, insn); | |
18494 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
18495 | } | |
18496 | else | |
18497 | { | |
18498 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
18499 | } | |
18500 | pc_rel = 0; | |
18501 | break; | |
18502 | case T_MNEM_b: | |
18503 | if (fragp->fr_var == 4) | |
18504 | { | |
18505 | insn = THUMB_OP32(opcode); | |
18506 | put_thumb32_insn (buf, insn); | |
18507 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
18508 | } | |
18509 | else | |
18510 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
18511 | pc_rel = 1; | |
18512 | break; | |
18513 | case T_MNEM_bcond: | |
18514 | if (fragp->fr_var == 4) | |
18515 | { | |
18516 | insn = THUMB_OP32(opcode); | |
18517 | insn |= (old_op & 0xf00) << 14; | |
18518 | put_thumb32_insn (buf, insn); | |
18519 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
18520 | } | |
18521 | else | |
18522 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
18523 | pc_rel = 1; | |
18524 | break; | |
18525 | case T_MNEM_add_sp: | |
18526 | case T_MNEM_add_pc: | |
18527 | case T_MNEM_inc_sp: | |
18528 | case T_MNEM_dec_sp: | |
18529 | if (fragp->fr_var == 4) | |
18530 | { | |
18531 | /* ??? Choose between add and addw. */ | |
18532 | insn = THUMB_OP32 (opcode); | |
18533 | insn |= (old_op & 0xf0) << 4; | |
18534 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
18535 | if (opcode == T_MNEM_add_pc) |
18536 | reloc_type = BFD_RELOC_ARM_T32_IMM12; | |
18537 | else | |
18538 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
0110f2b8 PB |
18539 | } |
18540 | else | |
18541 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
18542 | pc_rel = 0; | |
18543 | break; | |
18544 | ||
18545 | case T_MNEM_addi: | |
18546 | case T_MNEM_addis: | |
18547 | case T_MNEM_subi: | |
18548 | case T_MNEM_subis: | |
18549 | if (fragp->fr_var == 4) | |
18550 | { | |
18551 | insn = THUMB_OP32 (opcode); | |
18552 | insn |= (old_op & 0xf0) << 4; | |
18553 | insn |= (old_op & 0xf) << 16; | |
18554 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
18555 | if (insn & (1 << 20)) |
18556 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
18557 | else | |
18558 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
0110f2b8 PB |
18559 | } |
18560 | else | |
18561 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
18562 | pc_rel = 0; | |
18563 | break; | |
18564 | default: | |
5f4273c7 | 18565 | abort (); |
0110f2b8 PB |
18566 | } |
18567 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
21d799b5 | 18568 | (enum bfd_reloc_code_real) reloc_type); |
0110f2b8 PB |
18569 | fixp->fx_file = fragp->fr_file; |
18570 | fixp->fx_line = fragp->fr_line; | |
18571 | fragp->fr_fix += fragp->fr_var; | |
18572 | } | |
18573 | ||
18574 | /* Return the size of a relaxable immediate operand instruction. | |
18575 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
18576 | static int | |
18577 | relax_immediate (fragS *fragp, int size, int shift) | |
18578 | { | |
18579 | offsetT offset; | |
18580 | offsetT mask; | |
18581 | offsetT low; | |
18582 | ||
18583 | /* ??? Should be able to do better than this. */ | |
18584 | if (fragp->fr_symbol) | |
18585 | return 4; | |
18586 | ||
18587 | low = (1 << shift) - 1; | |
18588 | mask = (1 << (shift + size)) - (1 << shift); | |
18589 | offset = fragp->fr_offset; | |
18590 | /* Force misaligned offsets to 32-bit variant. */ | |
18591 | if (offset & low) | |
5e77afaa | 18592 | return 4; |
0110f2b8 PB |
18593 | if (offset & ~mask) |
18594 | return 4; | |
18595 | return 2; | |
18596 | } | |
18597 | ||
5e77afaa PB |
18598 | /* Get the address of a symbol during relaxation. */ |
18599 | static addressT | |
5f4273c7 | 18600 | relaxed_symbol_addr (fragS *fragp, long stretch) |
5e77afaa PB |
18601 | { |
18602 | fragS *sym_frag; | |
18603 | addressT addr; | |
18604 | symbolS *sym; | |
18605 | ||
18606 | sym = fragp->fr_symbol; | |
18607 | sym_frag = symbol_get_frag (sym); | |
18608 | know (S_GET_SEGMENT (sym) != absolute_section | |
18609 | || sym_frag == &zero_address_frag); | |
18610 | addr = S_GET_VALUE (sym) + fragp->fr_offset; | |
18611 | ||
18612 | /* If frag has yet to be reached on this pass, assume it will | |
18613 | move by STRETCH just as we did. If this is not so, it will | |
18614 | be because some frag between grows, and that will force | |
18615 | another pass. */ | |
18616 | ||
18617 | if (stretch != 0 | |
18618 | && sym_frag->relax_marker != fragp->relax_marker) | |
4396b686 PB |
18619 | { |
18620 | fragS *f; | |
18621 | ||
18622 | /* Adjust stretch for any alignment frag. Note that if have | |
18623 | been expanding the earlier code, the symbol may be | |
18624 | defined in what appears to be an earlier frag. FIXME: | |
18625 | This doesn't handle the fr_subtype field, which specifies | |
18626 | a maximum number of bytes to skip when doing an | |
18627 | alignment. */ | |
18628 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
18629 | { | |
18630 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
18631 | { | |
18632 | if (stretch < 0) | |
18633 | stretch = - ((- stretch) | |
18634 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
18635 | else | |
18636 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
18637 | if (stretch == 0) | |
18638 | break; | |
18639 | } | |
18640 | } | |
18641 | if (f != NULL) | |
18642 | addr += stretch; | |
18643 | } | |
5e77afaa PB |
18644 | |
18645 | return addr; | |
18646 | } | |
18647 | ||
0110f2b8 PB |
18648 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative |
18649 | load. */ | |
18650 | static int | |
5e77afaa | 18651 | relax_adr (fragS *fragp, asection *sec, long stretch) |
0110f2b8 PB |
18652 | { |
18653 | addressT addr; | |
18654 | offsetT val; | |
18655 | ||
18656 | /* Assume worst case for symbols not known to be in the same section. */ | |
974da60d NC |
18657 | if (fragp->fr_symbol == NULL |
18658 | || !S_IS_DEFINED (fragp->fr_symbol) | |
77db8e2e NC |
18659 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
18660 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
18661 | return 4; |
18662 | ||
5f4273c7 | 18663 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
18664 | addr = fragp->fr_address + fragp->fr_fix; |
18665 | addr = (addr + 4) & ~3; | |
5e77afaa | 18666 | /* Force misaligned targets to 32-bit variant. */ |
0110f2b8 | 18667 | if (val & 3) |
5e77afaa | 18668 | return 4; |
0110f2b8 PB |
18669 | val -= addr; |
18670 | if (val < 0 || val > 1020) | |
18671 | return 4; | |
18672 | return 2; | |
18673 | } | |
18674 | ||
18675 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
18676 | static int | |
18677 | relax_addsub (fragS *fragp, asection *sec) | |
18678 | { | |
18679 | char *buf; | |
18680 | int op; | |
18681 | ||
18682 | buf = fragp->fr_literal + fragp->fr_fix; | |
18683 | op = bfd_get_16(sec->owner, buf); | |
18684 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
18685 | return relax_immediate (fragp, 8, 0); | |
18686 | else | |
18687 | return relax_immediate (fragp, 3, 0); | |
18688 | } | |
18689 | ||
18690 | ||
18691 | /* Return the size of a relaxable branch instruction. BITS is the | |
18692 | size of the offset field in the narrow instruction. */ | |
18693 | ||
18694 | static int | |
5e77afaa | 18695 | relax_branch (fragS *fragp, asection *sec, int bits, long stretch) |
0110f2b8 PB |
18696 | { |
18697 | addressT addr; | |
18698 | offsetT val; | |
18699 | offsetT limit; | |
18700 | ||
18701 | /* Assume worst case for symbols not known to be in the same section. */ | |
5f4273c7 | 18702 | if (!S_IS_DEFINED (fragp->fr_symbol) |
77db8e2e NC |
18703 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
18704 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
18705 | return 4; |
18706 | ||
267bf995 RR |
18707 | #ifdef OBJ_ELF |
18708 | if (S_IS_DEFINED (fragp->fr_symbol) | |
18709 | && ARM_IS_FUNC (fragp->fr_symbol)) | |
18710 | return 4; | |
18711 | #endif | |
18712 | ||
5f4273c7 | 18713 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
18714 | addr = fragp->fr_address + fragp->fr_fix + 4; |
18715 | val -= addr; | |
18716 | ||
18717 | /* Offset is a signed value *2 */ | |
18718 | limit = 1 << bits; | |
18719 | if (val >= limit || val < -limit) | |
18720 | return 4; | |
18721 | return 2; | |
18722 | } | |
18723 | ||
18724 | ||
18725 | /* Relax a machine dependent frag. This returns the amount by which | |
18726 | the current size of the frag should change. */ | |
18727 | ||
18728 | int | |
5e77afaa | 18729 | arm_relax_frag (asection *sec, fragS *fragp, long stretch) |
0110f2b8 PB |
18730 | { |
18731 | int oldsize; | |
18732 | int newsize; | |
18733 | ||
18734 | oldsize = fragp->fr_var; | |
18735 | switch (fragp->fr_subtype) | |
18736 | { | |
18737 | case T_MNEM_ldr_pc2: | |
5f4273c7 | 18738 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
18739 | break; |
18740 | case T_MNEM_ldr_pc: | |
18741 | case T_MNEM_ldr_sp: | |
18742 | case T_MNEM_str_sp: | |
5f4273c7 | 18743 | newsize = relax_immediate (fragp, 8, 2); |
0110f2b8 PB |
18744 | break; |
18745 | case T_MNEM_ldr: | |
18746 | case T_MNEM_str: | |
5f4273c7 | 18747 | newsize = relax_immediate (fragp, 5, 2); |
0110f2b8 PB |
18748 | break; |
18749 | case T_MNEM_ldrh: | |
18750 | case T_MNEM_strh: | |
5f4273c7 | 18751 | newsize = relax_immediate (fragp, 5, 1); |
0110f2b8 PB |
18752 | break; |
18753 | case T_MNEM_ldrb: | |
18754 | case T_MNEM_strb: | |
5f4273c7 | 18755 | newsize = relax_immediate (fragp, 5, 0); |
0110f2b8 PB |
18756 | break; |
18757 | case T_MNEM_adr: | |
5f4273c7 | 18758 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
18759 | break; |
18760 | case T_MNEM_mov: | |
18761 | case T_MNEM_movs: | |
18762 | case T_MNEM_cmp: | |
18763 | case T_MNEM_cmn: | |
5f4273c7 | 18764 | newsize = relax_immediate (fragp, 8, 0); |
0110f2b8 PB |
18765 | break; |
18766 | case T_MNEM_b: | |
5f4273c7 | 18767 | newsize = relax_branch (fragp, sec, 11, stretch); |
0110f2b8 PB |
18768 | break; |
18769 | case T_MNEM_bcond: | |
5f4273c7 | 18770 | newsize = relax_branch (fragp, sec, 8, stretch); |
0110f2b8 PB |
18771 | break; |
18772 | case T_MNEM_add_sp: | |
18773 | case T_MNEM_add_pc: | |
18774 | newsize = relax_immediate (fragp, 8, 2); | |
18775 | break; | |
18776 | case T_MNEM_inc_sp: | |
18777 | case T_MNEM_dec_sp: | |
18778 | newsize = relax_immediate (fragp, 7, 2); | |
18779 | break; | |
18780 | case T_MNEM_addi: | |
18781 | case T_MNEM_addis: | |
18782 | case T_MNEM_subi: | |
18783 | case T_MNEM_subis: | |
18784 | newsize = relax_addsub (fragp, sec); | |
18785 | break; | |
18786 | default: | |
5f4273c7 | 18787 | abort (); |
0110f2b8 | 18788 | } |
5e77afaa PB |
18789 | |
18790 | fragp->fr_var = newsize; | |
18791 | /* Freeze wide instructions that are at or before the same location as | |
18792 | in the previous pass. This avoids infinite loops. | |
5f4273c7 NC |
18793 | Don't freeze them unconditionally because targets may be artificially |
18794 | misaligned by the expansion of preceding frags. */ | |
5e77afaa | 18795 | if (stretch <= 0 && newsize > 2) |
0110f2b8 | 18796 | { |
0110f2b8 | 18797 | md_convert_frag (sec->owner, sec, fragp); |
5f4273c7 | 18798 | frag_wane (fragp); |
0110f2b8 | 18799 | } |
5e77afaa | 18800 | |
0110f2b8 | 18801 | return newsize - oldsize; |
c19d1205 | 18802 | } |
b99bd4ef | 18803 | |
c19d1205 | 18804 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 18805 | |
c19d1205 ZW |
18806 | valueT |
18807 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
18808 | valueT size) | |
18809 | { | |
f0927246 NC |
18810 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
18811 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
18812 | { | |
18813 | /* For a.out, force the section size to be aligned. If we don't do | |
18814 | this, BFD will align it for us, but it will not write out the | |
18815 | final bytes of the section. This may be a bug in BFD, but it is | |
18816 | easier to fix it here since that is how the other a.out targets | |
18817 | work. */ | |
18818 | int align; | |
18819 | ||
18820 | align = bfd_get_section_alignment (stdoutput, segment); | |
18821 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
18822 | } | |
c19d1205 | 18823 | #endif |
f0927246 NC |
18824 | |
18825 | return size; | |
bfae80f2 | 18826 | } |
b99bd4ef | 18827 | |
c19d1205 ZW |
18828 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
18829 | of an rs_align_code fragment. */ | |
18830 | ||
18831 | void | |
18832 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 18833 | { |
e7495e45 NS |
18834 | static char const arm_noop[2][2][4] = |
18835 | { | |
18836 | { /* ARMv1 */ | |
18837 | {0x00, 0x00, 0xa0, 0xe1}, /* LE */ | |
18838 | {0xe1, 0xa0, 0x00, 0x00}, /* BE */ | |
18839 | }, | |
18840 | { /* ARMv6k */ | |
18841 | {0x00, 0xf0, 0x20, 0xe3}, /* LE */ | |
18842 | {0xe3, 0x20, 0xf0, 0x00}, /* BE */ | |
18843 | }, | |
18844 | }; | |
18845 | static char const thumb_noop[2][2][2] = | |
18846 | { | |
18847 | { /* Thumb-1 */ | |
18848 | {0xc0, 0x46}, /* LE */ | |
18849 | {0x46, 0xc0}, /* BE */ | |
18850 | }, | |
18851 | { /* Thumb-2 */ | |
18852 | {0x00, 0xbf}, /* LE */ | |
18853 | {0xbf, 0x00} /* BE */ | |
18854 | } | |
18855 | }; | |
18856 | static char const wide_thumb_noop[2][4] = | |
18857 | { /* Wide Thumb-2 */ | |
18858 | {0xaf, 0xf3, 0x00, 0x80}, /* LE */ | |
18859 | {0xf3, 0xaf, 0x80, 0x00}, /* BE */ | |
18860 | }; | |
c921be7d | 18861 | |
e7495e45 | 18862 | unsigned bytes, fix, noop_size; |
c19d1205 ZW |
18863 | char * p; |
18864 | const char * noop; | |
e7495e45 | 18865 | const char *narrow_noop = NULL; |
cd000bff DJ |
18866 | #ifdef OBJ_ELF |
18867 | enum mstate state; | |
18868 | #endif | |
bfae80f2 | 18869 | |
c19d1205 | 18870 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
18871 | return; |
18872 | ||
c19d1205 ZW |
18873 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
18874 | p = fragP->fr_literal + fragP->fr_fix; | |
18875 | fix = 0; | |
bfae80f2 | 18876 | |
c19d1205 ZW |
18877 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
18878 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 18879 | |
cd000bff | 18880 | gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0); |
8dc2430f | 18881 | |
cd000bff | 18882 | if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED)) |
a737bd4d | 18883 | { |
e7495e45 NS |
18884 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
18885 | { | |
18886 | narrow_noop = thumb_noop[1][target_big_endian]; | |
18887 | noop = wide_thumb_noop[target_big_endian]; | |
18888 | } | |
c19d1205 | 18889 | else |
e7495e45 NS |
18890 | noop = thumb_noop[0][target_big_endian]; |
18891 | noop_size = 2; | |
cd000bff DJ |
18892 | #ifdef OBJ_ELF |
18893 | state = MAP_THUMB; | |
18894 | #endif | |
7ed4c4c5 NC |
18895 | } |
18896 | else | |
18897 | { | |
e7495e45 NS |
18898 | noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0] |
18899 | [target_big_endian]; | |
18900 | noop_size = 4; | |
cd000bff DJ |
18901 | #ifdef OBJ_ELF |
18902 | state = MAP_ARM; | |
18903 | #endif | |
7ed4c4c5 | 18904 | } |
c921be7d | 18905 | |
e7495e45 | 18906 | fragP->fr_var = noop_size; |
c921be7d | 18907 | |
c19d1205 | 18908 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 18909 | { |
c19d1205 | 18910 | fix = bytes & (noop_size - 1); |
cd000bff DJ |
18911 | #ifdef OBJ_ELF |
18912 | insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix); | |
18913 | #endif | |
c19d1205 ZW |
18914 | memset (p, 0, fix); |
18915 | p += fix; | |
18916 | bytes -= fix; | |
a737bd4d | 18917 | } |
a737bd4d | 18918 | |
e7495e45 NS |
18919 | if (narrow_noop) |
18920 | { | |
18921 | if (bytes & noop_size) | |
18922 | { | |
18923 | /* Insert a narrow noop. */ | |
18924 | memcpy (p, narrow_noop, noop_size); | |
18925 | p += noop_size; | |
18926 | bytes -= noop_size; | |
18927 | fix += noop_size; | |
18928 | } | |
18929 | ||
18930 | /* Use wide noops for the remainder */ | |
18931 | noop_size = 4; | |
18932 | } | |
18933 | ||
c19d1205 | 18934 | while (bytes >= noop_size) |
a737bd4d | 18935 | { |
c19d1205 ZW |
18936 | memcpy (p, noop, noop_size); |
18937 | p += noop_size; | |
18938 | bytes -= noop_size; | |
18939 | fix += noop_size; | |
a737bd4d NC |
18940 | } |
18941 | ||
c19d1205 | 18942 | fragP->fr_fix += fix; |
a737bd4d NC |
18943 | } |
18944 | ||
c19d1205 ZW |
18945 | /* Called from md_do_align. Used to create an alignment |
18946 | frag in a code section. */ | |
18947 | ||
18948 | void | |
18949 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 18950 | { |
c19d1205 | 18951 | char * p; |
7ed4c4c5 | 18952 | |
c19d1205 | 18953 | /* We assume that there will never be a requirement |
6ec8e702 | 18954 | to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */ |
c19d1205 | 18955 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) |
6ec8e702 NC |
18956 | { |
18957 | char err_msg[128]; | |
18958 | ||
18959 | sprintf (err_msg, | |
18960 | _("alignments greater than %d bytes not supported in .text sections."), | |
18961 | MAX_MEM_FOR_RS_ALIGN_CODE + 1); | |
20203fb9 | 18962 | as_fatal ("%s", err_msg); |
6ec8e702 | 18963 | } |
bfae80f2 | 18964 | |
c19d1205 ZW |
18965 | p = frag_var (rs_align_code, |
18966 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
18967 | 1, | |
18968 | (relax_substateT) max, | |
18969 | (symbolS *) NULL, | |
18970 | (offsetT) n, | |
18971 | (char *) NULL); | |
18972 | *p = 0; | |
18973 | } | |
bfae80f2 | 18974 | |
8dc2430f NC |
18975 | /* Perform target specific initialisation of a frag. |
18976 | Note - despite the name this initialisation is not done when the frag | |
18977 | is created, but only when its type is assigned. A frag can be created | |
18978 | and used a long time before its type is set, so beware of assuming that | |
18979 | this initialisationis performed first. */ | |
bfae80f2 | 18980 | |
cd000bff DJ |
18981 | #ifndef OBJ_ELF |
18982 | void | |
18983 | arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED) | |
18984 | { | |
18985 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
2e98972e | 18986 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
cd000bff DJ |
18987 | } |
18988 | ||
18989 | #else /* OBJ_ELF is defined. */ | |
c19d1205 | 18990 | void |
cd000bff | 18991 | arm_init_frag (fragS * fragP, int max_chars) |
c19d1205 | 18992 | { |
8dc2430f NC |
18993 | /* If the current ARM vs THUMB mode has not already |
18994 | been recorded into this frag then do so now. */ | |
cd000bff DJ |
18995 | if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0) |
18996 | { | |
18997 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; | |
18998 | ||
18999 | /* Record a mapping symbol for alignment frags. We will delete this | |
19000 | later if the alignment ends up empty. */ | |
19001 | switch (fragP->fr_type) | |
19002 | { | |
19003 | case rs_align: | |
19004 | case rs_align_test: | |
19005 | case rs_fill: | |
19006 | mapping_state_2 (MAP_DATA, max_chars); | |
19007 | break; | |
19008 | case rs_align_code: | |
19009 | mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars); | |
19010 | break; | |
19011 | default: | |
19012 | break; | |
19013 | } | |
19014 | } | |
bfae80f2 RE |
19015 | } |
19016 | ||
c19d1205 ZW |
19017 | /* When we change sections we need to issue a new mapping symbol. */ |
19018 | ||
19019 | void | |
19020 | arm_elf_change_section (void) | |
bfae80f2 | 19021 | { |
c19d1205 ZW |
19022 | /* Link an unlinked unwind index table section to the .text section. */ |
19023 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
19024 | && elf_linked_to_section (now_seg) == NULL) | |
19025 | elf_linked_to_section (now_seg) = text_section; | |
bfae80f2 RE |
19026 | } |
19027 | ||
c19d1205 ZW |
19028 | int |
19029 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 19030 | { |
c19d1205 ZW |
19031 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
19032 | return SHT_ARM_EXIDX; | |
e45d0630 | 19033 | |
c19d1205 ZW |
19034 | return -1; |
19035 | } | |
19036 | \f | |
19037 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 19038 | |
c19d1205 | 19039 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 19040 | |
5f4273c7 | 19041 | /* Generate any deferred unwind frame offset. */ |
e45d0630 | 19042 | |
bfae80f2 | 19043 | static void |
c19d1205 | 19044 | flush_pending_unwind (void) |
bfae80f2 | 19045 | { |
c19d1205 | 19046 | offsetT offset; |
bfae80f2 | 19047 | |
c19d1205 ZW |
19048 | offset = unwind.pending_offset; |
19049 | unwind.pending_offset = 0; | |
19050 | if (offset != 0) | |
19051 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
19052 | } |
19053 | ||
c19d1205 ZW |
19054 | /* Add an opcode to this list for this function. Two-byte opcodes should |
19055 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
19056 | order. */ | |
19057 | ||
bfae80f2 | 19058 | static void |
c19d1205 | 19059 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 19060 | { |
c19d1205 ZW |
19061 | /* Add any deferred stack adjustment. */ |
19062 | if (unwind.pending_offset) | |
19063 | flush_pending_unwind (); | |
bfae80f2 | 19064 | |
c19d1205 | 19065 | unwind.sp_restored = 0; |
bfae80f2 | 19066 | |
c19d1205 | 19067 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 19068 | { |
c19d1205 ZW |
19069 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
19070 | if (unwind.opcodes) | |
21d799b5 NC |
19071 | unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes, |
19072 | unwind.opcode_alloc); | |
c19d1205 | 19073 | else |
21d799b5 | 19074 | unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc); |
bfae80f2 | 19075 | } |
c19d1205 | 19076 | while (length > 0) |
bfae80f2 | 19077 | { |
c19d1205 ZW |
19078 | length--; |
19079 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
19080 | op >>= 8; | |
19081 | unwind.opcode_count++; | |
bfae80f2 | 19082 | } |
bfae80f2 RE |
19083 | } |
19084 | ||
c19d1205 ZW |
19085 | /* Add unwind opcodes to adjust the stack pointer. */ |
19086 | ||
bfae80f2 | 19087 | static void |
c19d1205 | 19088 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 19089 | { |
c19d1205 | 19090 | valueT op; |
bfae80f2 | 19091 | |
c19d1205 | 19092 | if (offset > 0x200) |
bfae80f2 | 19093 | { |
c19d1205 ZW |
19094 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
19095 | char bytes[5]; | |
19096 | int n; | |
19097 | valueT o; | |
bfae80f2 | 19098 | |
c19d1205 ZW |
19099 | /* Long form: 0xb2, uleb128. */ |
19100 | /* This might not fit in a word so add the individual bytes, | |
19101 | remembering the list is built in reverse order. */ | |
19102 | o = (valueT) ((offset - 0x204) >> 2); | |
19103 | if (o == 0) | |
19104 | add_unwind_opcode (0, 1); | |
bfae80f2 | 19105 | |
c19d1205 ZW |
19106 | /* Calculate the uleb128 encoding of the offset. */ |
19107 | n = 0; | |
19108 | while (o) | |
19109 | { | |
19110 | bytes[n] = o & 0x7f; | |
19111 | o >>= 7; | |
19112 | if (o) | |
19113 | bytes[n] |= 0x80; | |
19114 | n++; | |
19115 | } | |
19116 | /* Add the insn. */ | |
19117 | for (; n; n--) | |
19118 | add_unwind_opcode (bytes[n - 1], 1); | |
19119 | add_unwind_opcode (0xb2, 1); | |
19120 | } | |
19121 | else if (offset > 0x100) | |
bfae80f2 | 19122 | { |
c19d1205 ZW |
19123 | /* Two short opcodes. */ |
19124 | add_unwind_opcode (0x3f, 1); | |
19125 | op = (offset - 0x104) >> 2; | |
19126 | add_unwind_opcode (op, 1); | |
bfae80f2 | 19127 | } |
c19d1205 ZW |
19128 | else if (offset > 0) |
19129 | { | |
19130 | /* Short opcode. */ | |
19131 | op = (offset - 4) >> 2; | |
19132 | add_unwind_opcode (op, 1); | |
19133 | } | |
19134 | else if (offset < 0) | |
bfae80f2 | 19135 | { |
c19d1205 ZW |
19136 | offset = -offset; |
19137 | while (offset > 0x100) | |
bfae80f2 | 19138 | { |
c19d1205 ZW |
19139 | add_unwind_opcode (0x7f, 1); |
19140 | offset -= 0x100; | |
bfae80f2 | 19141 | } |
c19d1205 ZW |
19142 | op = ((offset - 4) >> 2) | 0x40; |
19143 | add_unwind_opcode (op, 1); | |
bfae80f2 | 19144 | } |
bfae80f2 RE |
19145 | } |
19146 | ||
c19d1205 ZW |
19147 | /* Finish the list of unwind opcodes for this function. */ |
19148 | static void | |
19149 | finish_unwind_opcodes (void) | |
bfae80f2 | 19150 | { |
c19d1205 | 19151 | valueT op; |
bfae80f2 | 19152 | |
c19d1205 | 19153 | if (unwind.fp_used) |
bfae80f2 | 19154 | { |
708587a4 | 19155 | /* Adjust sp as necessary. */ |
c19d1205 ZW |
19156 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; |
19157 | flush_pending_unwind (); | |
bfae80f2 | 19158 | |
c19d1205 ZW |
19159 | /* After restoring sp from the frame pointer. */ |
19160 | op = 0x90 | unwind.fp_reg; | |
19161 | add_unwind_opcode (op, 1); | |
19162 | } | |
19163 | else | |
19164 | flush_pending_unwind (); | |
bfae80f2 RE |
19165 | } |
19166 | ||
bfae80f2 | 19167 | |
c19d1205 ZW |
19168 | /* Start an exception table entry. If idx is nonzero this is an index table |
19169 | entry. */ | |
bfae80f2 RE |
19170 | |
19171 | static void | |
c19d1205 | 19172 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 19173 | { |
c19d1205 ZW |
19174 | const char * text_name; |
19175 | const char * prefix; | |
19176 | const char * prefix_once; | |
19177 | const char * group_name; | |
19178 | size_t prefix_len; | |
19179 | size_t text_len; | |
19180 | char * sec_name; | |
19181 | size_t sec_name_len; | |
19182 | int type; | |
19183 | int flags; | |
19184 | int linkonce; | |
bfae80f2 | 19185 | |
c19d1205 | 19186 | if (idx) |
bfae80f2 | 19187 | { |
c19d1205 ZW |
19188 | prefix = ELF_STRING_ARM_unwind; |
19189 | prefix_once = ELF_STRING_ARM_unwind_once; | |
19190 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 19191 | } |
c19d1205 | 19192 | else |
bfae80f2 | 19193 | { |
c19d1205 ZW |
19194 | prefix = ELF_STRING_ARM_unwind_info; |
19195 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
19196 | type = SHT_PROGBITS; | |
bfae80f2 RE |
19197 | } |
19198 | ||
c19d1205 ZW |
19199 | text_name = segment_name (text_seg); |
19200 | if (streq (text_name, ".text")) | |
19201 | text_name = ""; | |
19202 | ||
19203 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
19204 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 19205 | { |
c19d1205 ZW |
19206 | prefix = prefix_once; |
19207 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
19208 | } |
19209 | ||
c19d1205 ZW |
19210 | prefix_len = strlen (prefix); |
19211 | text_len = strlen (text_name); | |
19212 | sec_name_len = prefix_len + text_len; | |
21d799b5 | 19213 | sec_name = (char *) xmalloc (sec_name_len + 1); |
c19d1205 ZW |
19214 | memcpy (sec_name, prefix, prefix_len); |
19215 | memcpy (sec_name + prefix_len, text_name, text_len); | |
19216 | sec_name[prefix_len + text_len] = '\0'; | |
bfae80f2 | 19217 | |
c19d1205 ZW |
19218 | flags = SHF_ALLOC; |
19219 | linkonce = 0; | |
19220 | group_name = 0; | |
bfae80f2 | 19221 | |
c19d1205 ZW |
19222 | /* Handle COMDAT group. */ |
19223 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 19224 | { |
c19d1205 ZW |
19225 | group_name = elf_group_name (text_seg); |
19226 | if (group_name == NULL) | |
19227 | { | |
bd3ba5d1 | 19228 | as_bad (_("Group section `%s' has no group signature"), |
c19d1205 ZW |
19229 | segment_name (text_seg)); |
19230 | ignore_rest_of_line (); | |
19231 | return; | |
19232 | } | |
19233 | flags |= SHF_GROUP; | |
19234 | linkonce = 1; | |
bfae80f2 RE |
19235 | } |
19236 | ||
c19d1205 | 19237 | obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); |
bfae80f2 | 19238 | |
5f4273c7 | 19239 | /* Set the section link for index tables. */ |
c19d1205 ZW |
19240 | if (idx) |
19241 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
19242 | } |
19243 | ||
bfae80f2 | 19244 | |
c19d1205 ZW |
19245 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
19246 | personality routine data. Returns zero, or the index table value for | |
19247 | and inline entry. */ | |
19248 | ||
19249 | static valueT | |
19250 | create_unwind_entry (int have_data) | |
bfae80f2 | 19251 | { |
c19d1205 ZW |
19252 | int size; |
19253 | addressT where; | |
19254 | char *ptr; | |
19255 | /* The current word of data. */ | |
19256 | valueT data; | |
19257 | /* The number of bytes left in this word. */ | |
19258 | int n; | |
bfae80f2 | 19259 | |
c19d1205 | 19260 | finish_unwind_opcodes (); |
bfae80f2 | 19261 | |
c19d1205 ZW |
19262 | /* Remember the current text section. */ |
19263 | unwind.saved_seg = now_seg; | |
19264 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 19265 | |
c19d1205 | 19266 | start_unwind_section (now_seg, 0); |
bfae80f2 | 19267 | |
c19d1205 | 19268 | if (unwind.personality_routine == NULL) |
bfae80f2 | 19269 | { |
c19d1205 ZW |
19270 | if (unwind.personality_index == -2) |
19271 | { | |
19272 | if (have_data) | |
5f4273c7 | 19273 | as_bad (_("handlerdata in cantunwind frame")); |
c19d1205 ZW |
19274 | return 1; /* EXIDX_CANTUNWIND. */ |
19275 | } | |
bfae80f2 | 19276 | |
c19d1205 ZW |
19277 | /* Use a default personality routine if none is specified. */ |
19278 | if (unwind.personality_index == -1) | |
19279 | { | |
19280 | if (unwind.opcode_count > 3) | |
19281 | unwind.personality_index = 1; | |
19282 | else | |
19283 | unwind.personality_index = 0; | |
19284 | } | |
bfae80f2 | 19285 | |
c19d1205 ZW |
19286 | /* Space for the personality routine entry. */ |
19287 | if (unwind.personality_index == 0) | |
19288 | { | |
19289 | if (unwind.opcode_count > 3) | |
19290 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 19291 | |
c19d1205 ZW |
19292 | if (!have_data) |
19293 | { | |
19294 | /* All the data is inline in the index table. */ | |
19295 | data = 0x80; | |
19296 | n = 3; | |
19297 | while (unwind.opcode_count > 0) | |
19298 | { | |
19299 | unwind.opcode_count--; | |
19300 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
19301 | n--; | |
19302 | } | |
bfae80f2 | 19303 | |
c19d1205 ZW |
19304 | /* Pad with "finish" opcodes. */ |
19305 | while (n--) | |
19306 | data = (data << 8) | 0xb0; | |
bfae80f2 | 19307 | |
c19d1205 ZW |
19308 | return data; |
19309 | } | |
19310 | size = 0; | |
19311 | } | |
19312 | else | |
19313 | /* We get two opcodes "free" in the first word. */ | |
19314 | size = unwind.opcode_count - 2; | |
19315 | } | |
19316 | else | |
19317 | /* An extra byte is required for the opcode count. */ | |
19318 | size = unwind.opcode_count + 1; | |
bfae80f2 | 19319 | |
c19d1205 ZW |
19320 | size = (size + 3) >> 2; |
19321 | if (size > 0xff) | |
19322 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 19323 | |
c19d1205 ZW |
19324 | frag_align (2, 0, 0); |
19325 | record_alignment (now_seg, 2); | |
19326 | unwind.table_entry = expr_build_dot (); | |
19327 | ||
19328 | /* Allocate the table entry. */ | |
19329 | ptr = frag_more ((size << 2) + 4); | |
19330 | where = frag_now_fix () - ((size << 2) + 4); | |
bfae80f2 | 19331 | |
c19d1205 | 19332 | switch (unwind.personality_index) |
bfae80f2 | 19333 | { |
c19d1205 ZW |
19334 | case -1: |
19335 | /* ??? Should this be a PLT generating relocation? */ | |
19336 | /* Custom personality routine. */ | |
19337 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
19338 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 19339 | |
c19d1205 ZW |
19340 | where += 4; |
19341 | ptr += 4; | |
bfae80f2 | 19342 | |
c19d1205 ZW |
19343 | /* Set the first byte to the number of additional words. */ |
19344 | data = size - 1; | |
19345 | n = 3; | |
19346 | break; | |
bfae80f2 | 19347 | |
c19d1205 ZW |
19348 | /* ABI defined personality routines. */ |
19349 | case 0: | |
19350 | /* Three opcodes bytes are packed into the first word. */ | |
19351 | data = 0x80; | |
19352 | n = 3; | |
19353 | break; | |
bfae80f2 | 19354 | |
c19d1205 ZW |
19355 | case 1: |
19356 | case 2: | |
19357 | /* The size and first two opcode bytes go in the first word. */ | |
19358 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
19359 | n = 2; | |
19360 | break; | |
bfae80f2 | 19361 | |
c19d1205 ZW |
19362 | default: |
19363 | /* Should never happen. */ | |
19364 | abort (); | |
19365 | } | |
bfae80f2 | 19366 | |
c19d1205 ZW |
19367 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
19368 | time. */ | |
19369 | while (unwind.opcode_count > 0) | |
19370 | { | |
19371 | if (n == 0) | |
19372 | { | |
19373 | md_number_to_chars (ptr, data, 4); | |
19374 | ptr += 4; | |
19375 | n = 4; | |
19376 | data = 0; | |
19377 | } | |
19378 | unwind.opcode_count--; | |
19379 | n--; | |
19380 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
19381 | } | |
19382 | ||
19383 | /* Finish off the last word. */ | |
19384 | if (n < 4) | |
19385 | { | |
19386 | /* Pad with "finish" opcodes. */ | |
19387 | while (n--) | |
19388 | data = (data << 8) | 0xb0; | |
19389 | ||
19390 | md_number_to_chars (ptr, data, 4); | |
19391 | } | |
19392 | ||
19393 | if (!have_data) | |
19394 | { | |
19395 | /* Add an empty descriptor if there is no user-specified data. */ | |
19396 | ptr = frag_more (4); | |
19397 | md_number_to_chars (ptr, 0, 4); | |
19398 | } | |
19399 | ||
19400 | return 0; | |
bfae80f2 RE |
19401 | } |
19402 | ||
f0927246 NC |
19403 | |
19404 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
19405 | ||
19406 | void | |
19407 | tc_arm_frame_initial_instructions (void) | |
19408 | { | |
19409 | cfi_add_CFA_def_cfa (REG_SP, 0); | |
19410 | } | |
19411 | #endif /* OBJ_ELF */ | |
19412 | ||
c19d1205 ZW |
19413 | /* Convert REGNAME to a DWARF-2 register number. */ |
19414 | ||
19415 | int | |
1df69f4f | 19416 | tc_arm_regname_to_dw2regnum (char *regname) |
bfae80f2 | 19417 | { |
1df69f4f | 19418 | int reg = arm_reg_parse (®name, REG_TYPE_RN); |
c19d1205 ZW |
19419 | |
19420 | if (reg == FAIL) | |
19421 | return -1; | |
19422 | ||
19423 | return reg; | |
bfae80f2 RE |
19424 | } |
19425 | ||
f0927246 | 19426 | #ifdef TE_PE |
c19d1205 | 19427 | void |
f0927246 | 19428 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
bfae80f2 | 19429 | { |
91d6fa6a | 19430 | expressionS exp; |
bfae80f2 | 19431 | |
91d6fa6a NC |
19432 | exp.X_op = O_secrel; |
19433 | exp.X_add_symbol = symbol; | |
19434 | exp.X_add_number = 0; | |
19435 | emit_expr (&exp, size); | |
f0927246 NC |
19436 | } |
19437 | #endif | |
bfae80f2 | 19438 | |
c19d1205 | 19439 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 19440 | |
2fc8bdac ZW |
19441 | /* Return the address within the segment that a PC-relative fixup is |
19442 | relative to. For ARM, PC-relative fixups applied to instructions | |
19443 | are generally relative to the location of the fixup plus 8 bytes. | |
19444 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
19445 | require special handling. */ | |
bfae80f2 | 19446 | |
c19d1205 | 19447 | long |
2fc8bdac | 19448 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 19449 | { |
2fc8bdac ZW |
19450 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
19451 | ||
19452 | /* If this is pc-relative and we are going to emit a relocation | |
19453 | then we just want to put out any pipeline compensation that the linker | |
53baae48 NC |
19454 | will need. Otherwise we want to use the calculated base. |
19455 | For WinCE we skip the bias for externals as well, since this | |
19456 | is how the MS ARM-CE assembler behaves and we want to be compatible. */ | |
5f4273c7 | 19457 | if (fixP->fx_pcrel |
2fc8bdac | 19458 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) |
53baae48 NC |
19459 | || (arm_force_relocation (fixP) |
19460 | #ifdef TE_WINCE | |
19461 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
19462 | #endif | |
19463 | ))) | |
2fc8bdac | 19464 | base = 0; |
bfae80f2 | 19465 | |
267bf995 | 19466 | |
c19d1205 | 19467 | switch (fixP->fx_r_type) |
bfae80f2 | 19468 | { |
2fc8bdac ZW |
19469 | /* PC relative addressing on the Thumb is slightly odd as the |
19470 | bottom two bits of the PC are forced to zero for the | |
19471 | calculation. This happens *after* application of the | |
19472 | pipeline offset. However, Thumb adrl already adjusts for | |
19473 | this, so we need not do it again. */ | |
c19d1205 | 19474 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 19475 | return base & ~3; |
c19d1205 ZW |
19476 | |
19477 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
19478 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 19479 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 19480 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 19481 | return (base + 4) & ~3; |
c19d1205 | 19482 | |
2fc8bdac ZW |
19483 | /* Thumb branches are simply offset by +4. */ |
19484 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
19485 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
19486 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
19487 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
2fc8bdac | 19488 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac | 19489 | return base + 4; |
bfae80f2 | 19490 | |
267bf995 | 19491 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
486499d0 CL |
19492 | if (fixP->fx_addsy |
19493 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19494 | && (!S_IS_EXTERNAL (fixP->fx_addsy)) | |
267bf995 RR |
19495 | && ARM_IS_FUNC (fixP->fx_addsy) |
19496 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19497 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
19498 | return base + 4; | |
19499 | ||
00adf2d4 JB |
19500 | /* BLX is like branches above, but forces the low two bits of PC to |
19501 | zero. */ | |
486499d0 CL |
19502 | case BFD_RELOC_THUMB_PCREL_BLX: |
19503 | if (fixP->fx_addsy | |
19504 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19505 | && (!S_IS_EXTERNAL (fixP->fx_addsy)) | |
267bf995 RR |
19506 | && THUMB_IS_FUNC (fixP->fx_addsy) |
19507 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19508 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
00adf2d4 JB |
19509 | return (base + 4) & ~3; |
19510 | ||
2fc8bdac ZW |
19511 | /* ARM mode branches are offset by +8. However, the Windows CE |
19512 | loader expects the relocation not to take this into account. */ | |
267bf995 | 19513 | case BFD_RELOC_ARM_PCREL_BLX: |
486499d0 CL |
19514 | if (fixP->fx_addsy |
19515 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19516 | && (!S_IS_EXTERNAL (fixP->fx_addsy)) | |
267bf995 RR |
19517 | && ARM_IS_FUNC (fixP->fx_addsy) |
19518 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19519 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 19520 | return base + 8; |
267bf995 | 19521 | |
486499d0 CL |
19522 | case BFD_RELOC_ARM_PCREL_CALL: |
19523 | if (fixP->fx_addsy | |
19524 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19525 | && (!S_IS_EXTERNAL (fixP->fx_addsy)) | |
267bf995 RR |
19526 | && THUMB_IS_FUNC (fixP->fx_addsy) |
19527 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19528 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 19529 | return base + 8; |
267bf995 | 19530 | |
2fc8bdac | 19531 | case BFD_RELOC_ARM_PCREL_BRANCH: |
39b41c9c | 19532 | case BFD_RELOC_ARM_PCREL_JUMP: |
2fc8bdac | 19533 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 19534 | #ifdef TE_WINCE |
5f4273c7 | 19535 | /* When handling fixups immediately, because we have already |
53baae48 NC |
19536 | discovered the value of a symbol, or the address of the frag involved |
19537 | we must account for the offset by +8, as the OS loader will never see the reloc. | |
19538 | see fixup_segment() in write.c | |
19539 | The S_IS_EXTERNAL test handles the case of global symbols. | |
19540 | Those need the calculated base, not just the pipe compensation the linker will need. */ | |
19541 | if (fixP->fx_pcrel | |
19542 | && fixP->fx_addsy != NULL | |
19543 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19544 | && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) | |
19545 | return base + 8; | |
2fc8bdac | 19546 | return base; |
c19d1205 | 19547 | #else |
2fc8bdac | 19548 | return base + 8; |
c19d1205 | 19549 | #endif |
2fc8bdac | 19550 | |
267bf995 | 19551 | |
2fc8bdac ZW |
19552 | /* ARM mode loads relative to PC are also offset by +8. Unlike |
19553 | branches, the Windows CE loader *does* expect the relocation | |
19554 | to take this into account. */ | |
19555 | case BFD_RELOC_ARM_OFFSET_IMM: | |
19556 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
19557 | case BFD_RELOC_ARM_HWLITERAL: | |
19558 | case BFD_RELOC_ARM_LITERAL: | |
19559 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
19560 | return base + 8; | |
19561 | ||
19562 | ||
19563 | /* Other PC-relative relocations are un-offset. */ | |
19564 | default: | |
19565 | return base; | |
19566 | } | |
bfae80f2 RE |
19567 | } |
19568 | ||
c19d1205 ZW |
19569 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. |
19570 | Otherwise we have no need to default values of symbols. */ | |
19571 | ||
19572 | symbolS * | |
19573 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
bfae80f2 | 19574 | { |
c19d1205 ZW |
19575 | #ifdef OBJ_ELF |
19576 | if (name[0] == '_' && name[1] == 'G' | |
19577 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
19578 | { | |
19579 | if (!GOT_symbol) | |
19580 | { | |
19581 | if (symbol_find (name)) | |
bd3ba5d1 | 19582 | as_bad (_("GOT already in the symbol table")); |
bfae80f2 | 19583 | |
c19d1205 ZW |
19584 | GOT_symbol = symbol_new (name, undefined_section, |
19585 | (valueT) 0, & zero_address_frag); | |
19586 | } | |
bfae80f2 | 19587 | |
c19d1205 | 19588 | return GOT_symbol; |
bfae80f2 | 19589 | } |
c19d1205 | 19590 | #endif |
bfae80f2 | 19591 | |
c921be7d | 19592 | return NULL; |
bfae80f2 RE |
19593 | } |
19594 | ||
55cf6793 | 19595 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
19596 | computed as two separate immediate values, added together. We |
19597 | already know that this value cannot be computed by just one ARM | |
19598 | instruction. */ | |
19599 | ||
19600 | static unsigned int | |
19601 | validate_immediate_twopart (unsigned int val, | |
19602 | unsigned int * highpart) | |
bfae80f2 | 19603 | { |
c19d1205 ZW |
19604 | unsigned int a; |
19605 | unsigned int i; | |
bfae80f2 | 19606 | |
c19d1205 ZW |
19607 | for (i = 0; i < 32; i += 2) |
19608 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
19609 | { | |
19610 | if (a & 0xff00) | |
19611 | { | |
19612 | if (a & ~ 0xffff) | |
19613 | continue; | |
19614 | * highpart = (a >> 8) | ((i + 24) << 7); | |
19615 | } | |
19616 | else if (a & 0xff0000) | |
19617 | { | |
19618 | if (a & 0xff000000) | |
19619 | continue; | |
19620 | * highpart = (a >> 16) | ((i + 16) << 7); | |
19621 | } | |
19622 | else | |
19623 | { | |
9c2799c2 | 19624 | gas_assert (a & 0xff000000); |
c19d1205 ZW |
19625 | * highpart = (a >> 24) | ((i + 8) << 7); |
19626 | } | |
bfae80f2 | 19627 | |
c19d1205 ZW |
19628 | return (a & 0xff) | (i << 7); |
19629 | } | |
bfae80f2 | 19630 | |
c19d1205 | 19631 | return FAIL; |
bfae80f2 RE |
19632 | } |
19633 | ||
c19d1205 ZW |
19634 | static int |
19635 | validate_offset_imm (unsigned int val, int hwse) | |
19636 | { | |
19637 | if ((hwse && val > 255) || val > 4095) | |
19638 | return FAIL; | |
19639 | return val; | |
19640 | } | |
bfae80f2 | 19641 | |
55cf6793 | 19642 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
19643 | negative immediate constant by altering the instruction. A bit of |
19644 | a hack really. | |
19645 | MOV <-> MVN | |
19646 | AND <-> BIC | |
19647 | ADC <-> SBC | |
19648 | by inverting the second operand, and | |
19649 | ADD <-> SUB | |
19650 | CMP <-> CMN | |
19651 | by negating the second operand. */ | |
bfae80f2 | 19652 | |
c19d1205 ZW |
19653 | static int |
19654 | negate_data_op (unsigned long * instruction, | |
19655 | unsigned long value) | |
bfae80f2 | 19656 | { |
c19d1205 ZW |
19657 | int op, new_inst; |
19658 | unsigned long negated, inverted; | |
bfae80f2 | 19659 | |
c19d1205 ZW |
19660 | negated = encode_arm_immediate (-value); |
19661 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 19662 | |
c19d1205 ZW |
19663 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
19664 | switch (op) | |
bfae80f2 | 19665 | { |
c19d1205 ZW |
19666 | /* First negates. */ |
19667 | case OPCODE_SUB: /* ADD <-> SUB */ | |
19668 | new_inst = OPCODE_ADD; | |
19669 | value = negated; | |
19670 | break; | |
bfae80f2 | 19671 | |
c19d1205 ZW |
19672 | case OPCODE_ADD: |
19673 | new_inst = OPCODE_SUB; | |
19674 | value = negated; | |
19675 | break; | |
bfae80f2 | 19676 | |
c19d1205 ZW |
19677 | case OPCODE_CMP: /* CMP <-> CMN */ |
19678 | new_inst = OPCODE_CMN; | |
19679 | value = negated; | |
19680 | break; | |
bfae80f2 | 19681 | |
c19d1205 ZW |
19682 | case OPCODE_CMN: |
19683 | new_inst = OPCODE_CMP; | |
19684 | value = negated; | |
19685 | break; | |
bfae80f2 | 19686 | |
c19d1205 ZW |
19687 | /* Now Inverted ops. */ |
19688 | case OPCODE_MOV: /* MOV <-> MVN */ | |
19689 | new_inst = OPCODE_MVN; | |
19690 | value = inverted; | |
19691 | break; | |
bfae80f2 | 19692 | |
c19d1205 ZW |
19693 | case OPCODE_MVN: |
19694 | new_inst = OPCODE_MOV; | |
19695 | value = inverted; | |
19696 | break; | |
bfae80f2 | 19697 | |
c19d1205 ZW |
19698 | case OPCODE_AND: /* AND <-> BIC */ |
19699 | new_inst = OPCODE_BIC; | |
19700 | value = inverted; | |
19701 | break; | |
bfae80f2 | 19702 | |
c19d1205 ZW |
19703 | case OPCODE_BIC: |
19704 | new_inst = OPCODE_AND; | |
19705 | value = inverted; | |
19706 | break; | |
bfae80f2 | 19707 | |
c19d1205 ZW |
19708 | case OPCODE_ADC: /* ADC <-> SBC */ |
19709 | new_inst = OPCODE_SBC; | |
19710 | value = inverted; | |
19711 | break; | |
bfae80f2 | 19712 | |
c19d1205 ZW |
19713 | case OPCODE_SBC: |
19714 | new_inst = OPCODE_ADC; | |
19715 | value = inverted; | |
19716 | break; | |
bfae80f2 | 19717 | |
c19d1205 ZW |
19718 | /* We cannot do anything. */ |
19719 | default: | |
19720 | return FAIL; | |
b99bd4ef NC |
19721 | } |
19722 | ||
c19d1205 ZW |
19723 | if (value == (unsigned) FAIL) |
19724 | return FAIL; | |
19725 | ||
19726 | *instruction &= OPCODE_MASK; | |
19727 | *instruction |= new_inst << DATA_OP_SHIFT; | |
19728 | return value; | |
b99bd4ef NC |
19729 | } |
19730 | ||
ef8d22e6 PB |
19731 | /* Like negate_data_op, but for Thumb-2. */ |
19732 | ||
19733 | static unsigned int | |
16dd5e42 | 19734 | thumb32_negate_data_op (offsetT *instruction, unsigned int value) |
ef8d22e6 PB |
19735 | { |
19736 | int op, new_inst; | |
19737 | int rd; | |
16dd5e42 | 19738 | unsigned int negated, inverted; |
ef8d22e6 PB |
19739 | |
19740 | negated = encode_thumb32_immediate (-value); | |
19741 | inverted = encode_thumb32_immediate (~value); | |
19742 | ||
19743 | rd = (*instruction >> 8) & 0xf; | |
19744 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; | |
19745 | switch (op) | |
19746 | { | |
19747 | /* ADD <-> SUB. Includes CMP <-> CMN. */ | |
19748 | case T2_OPCODE_SUB: | |
19749 | new_inst = T2_OPCODE_ADD; | |
19750 | value = negated; | |
19751 | break; | |
19752 | ||
19753 | case T2_OPCODE_ADD: | |
19754 | new_inst = T2_OPCODE_SUB; | |
19755 | value = negated; | |
19756 | break; | |
19757 | ||
19758 | /* ORR <-> ORN. Includes MOV <-> MVN. */ | |
19759 | case T2_OPCODE_ORR: | |
19760 | new_inst = T2_OPCODE_ORN; | |
19761 | value = inverted; | |
19762 | break; | |
19763 | ||
19764 | case T2_OPCODE_ORN: | |
19765 | new_inst = T2_OPCODE_ORR; | |
19766 | value = inverted; | |
19767 | break; | |
19768 | ||
19769 | /* AND <-> BIC. TST has no inverted equivalent. */ | |
19770 | case T2_OPCODE_AND: | |
19771 | new_inst = T2_OPCODE_BIC; | |
19772 | if (rd == 15) | |
19773 | value = FAIL; | |
19774 | else | |
19775 | value = inverted; | |
19776 | break; | |
19777 | ||
19778 | case T2_OPCODE_BIC: | |
19779 | new_inst = T2_OPCODE_AND; | |
19780 | value = inverted; | |
19781 | break; | |
19782 | ||
19783 | /* ADC <-> SBC */ | |
19784 | case T2_OPCODE_ADC: | |
19785 | new_inst = T2_OPCODE_SBC; | |
19786 | value = inverted; | |
19787 | break; | |
19788 | ||
19789 | case T2_OPCODE_SBC: | |
19790 | new_inst = T2_OPCODE_ADC; | |
19791 | value = inverted; | |
19792 | break; | |
19793 | ||
19794 | /* We cannot do anything. */ | |
19795 | default: | |
19796 | return FAIL; | |
19797 | } | |
19798 | ||
16dd5e42 | 19799 | if (value == (unsigned int)FAIL) |
ef8d22e6 PB |
19800 | return FAIL; |
19801 | ||
19802 | *instruction &= T2_OPCODE_MASK; | |
19803 | *instruction |= new_inst << T2_DATA_OP_SHIFT; | |
19804 | return value; | |
19805 | } | |
19806 | ||
8f06b2d8 PB |
19807 | /* Read a 32-bit thumb instruction from buf. */ |
19808 | static unsigned long | |
19809 | get_thumb32_insn (char * buf) | |
19810 | { | |
19811 | unsigned long insn; | |
19812 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
19813 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
19814 | ||
19815 | return insn; | |
19816 | } | |
19817 | ||
a8bc6c78 PB |
19818 | |
19819 | /* We usually want to set the low bit on the address of thumb function | |
19820 | symbols. In particular .word foo - . should have the low bit set. | |
19821 | Generic code tries to fold the difference of two symbols to | |
19822 | a constant. Prevent this and force a relocation when the first symbols | |
19823 | is a thumb function. */ | |
c921be7d NC |
19824 | |
19825 | bfd_boolean | |
a8bc6c78 PB |
19826 | arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) |
19827 | { | |
19828 | if (op == O_subtract | |
19829 | && l->X_op == O_symbol | |
19830 | && r->X_op == O_symbol | |
19831 | && THUMB_IS_FUNC (l->X_add_symbol)) | |
19832 | { | |
19833 | l->X_op = O_subtract; | |
19834 | l->X_op_symbol = r->X_add_symbol; | |
19835 | l->X_add_number -= r->X_add_number; | |
c921be7d | 19836 | return TRUE; |
a8bc6c78 | 19837 | } |
c921be7d | 19838 | |
a8bc6c78 | 19839 | /* Process as normal. */ |
c921be7d | 19840 | return FALSE; |
a8bc6c78 PB |
19841 | } |
19842 | ||
4a42ebbc RR |
19843 | /* Encode Thumb2 unconditional branches and calls. The encoding |
19844 | for the 2 are identical for the immediate values. */ | |
19845 | ||
19846 | static void | |
19847 | encode_thumb2_b_bl_offset (char * buf, offsetT value) | |
19848 | { | |
19849 | #define T2I1I2MASK ((1 << 13) | (1 << 11)) | |
19850 | offsetT newval; | |
19851 | offsetT newval2; | |
19852 | addressT S, I1, I2, lo, hi; | |
19853 | ||
19854 | S = (value >> 24) & 0x01; | |
19855 | I1 = (value >> 23) & 0x01; | |
19856 | I2 = (value >> 22) & 0x01; | |
19857 | hi = (value >> 12) & 0x3ff; | |
19858 | lo = (value >> 1) & 0x7ff; | |
19859 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
19860 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
19861 | newval |= (S << 10) | hi; | |
19862 | newval2 &= ~T2I1I2MASK; | |
19863 | newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK; | |
19864 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
19865 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
19866 | } | |
19867 | ||
c19d1205 | 19868 | void |
55cf6793 | 19869 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
19870 | valueT * valP, |
19871 | segT seg) | |
19872 | { | |
19873 | offsetT value = * valP; | |
19874 | offsetT newval; | |
19875 | unsigned int newimm; | |
19876 | unsigned long temp; | |
19877 | int sign; | |
19878 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 19879 | |
9c2799c2 | 19880 | gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 19881 | |
c19d1205 | 19882 | /* Note whether this will delete the relocation. */ |
4962c51a | 19883 | |
c19d1205 ZW |
19884 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) |
19885 | fixP->fx_done = 1; | |
b99bd4ef | 19886 | |
adbaf948 | 19887 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
5f4273c7 | 19888 | consistency with the behaviour on 32-bit hosts. Remember value |
adbaf948 ZW |
19889 | for emit_reloc. */ |
19890 | value &= 0xffffffff; | |
19891 | value ^= 0x80000000; | |
5f4273c7 | 19892 | value -= 0x80000000; |
adbaf948 ZW |
19893 | |
19894 | *valP = value; | |
c19d1205 | 19895 | fixP->fx_addnumber = value; |
b99bd4ef | 19896 | |
adbaf948 ZW |
19897 | /* Same treatment for fixP->fx_offset. */ |
19898 | fixP->fx_offset &= 0xffffffff; | |
19899 | fixP->fx_offset ^= 0x80000000; | |
19900 | fixP->fx_offset -= 0x80000000; | |
19901 | ||
c19d1205 | 19902 | switch (fixP->fx_r_type) |
b99bd4ef | 19903 | { |
c19d1205 ZW |
19904 | case BFD_RELOC_NONE: |
19905 | /* This will need to go in the object file. */ | |
19906 | fixP->fx_done = 0; | |
19907 | break; | |
b99bd4ef | 19908 | |
c19d1205 ZW |
19909 | case BFD_RELOC_ARM_IMMEDIATE: |
19910 | /* We claim that this fixup has been processed here, | |
19911 | even if in fact we generate an error because we do | |
19912 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
19913 | fixP->fx_done = 1; | |
b99bd4ef | 19914 | |
77db8e2e | 19915 | if (fixP->fx_addsy) |
b99bd4ef | 19916 | { |
77db8e2e | 19917 | const char *msg = 0; |
b99bd4ef | 19918 | |
77db8e2e NC |
19919 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
19920 | msg = _("undefined symbol %s used as an immediate value"); | |
19921 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
19922 | msg = _("symbol %s is in a different section"); | |
19923 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
19924 | msg = _("symbol %s is weak and may be overridden later"); | |
19925 | ||
19926 | if (msg) | |
19927 | { | |
19928 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19929 | msg, S_GET_NAME (fixP->fx_addsy)); | |
19930 | break; | |
19931 | } | |
42e5fcbf AS |
19932 | } |
19933 | ||
c19d1205 ZW |
19934 | newimm = encode_arm_immediate (value); |
19935 | temp = md_chars_to_number (buf, INSN_SIZE); | |
19936 | ||
19937 | /* If the instruction will fail, see if we can fix things up by | |
19938 | changing the opcode. */ | |
19939 | if (newimm == (unsigned int) FAIL | |
19940 | && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) | |
b99bd4ef | 19941 | { |
c19d1205 ZW |
19942 | as_bad_where (fixP->fx_file, fixP->fx_line, |
19943 | _("invalid constant (%lx) after fixup"), | |
19944 | (unsigned long) value); | |
19945 | break; | |
b99bd4ef | 19946 | } |
b99bd4ef | 19947 | |
c19d1205 ZW |
19948 | newimm |= (temp & 0xfffff000); |
19949 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
19950 | break; | |
b99bd4ef | 19951 | |
c19d1205 ZW |
19952 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
19953 | { | |
19954 | unsigned int highpart = 0; | |
19955 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 19956 | |
77db8e2e | 19957 | if (fixP->fx_addsy) |
42e5fcbf | 19958 | { |
77db8e2e | 19959 | const char *msg = 0; |
42e5fcbf | 19960 | |
77db8e2e NC |
19961 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
19962 | msg = _("undefined symbol %s used as an immediate value"); | |
19963 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
19964 | msg = _("symbol %s is in a different section"); | |
19965 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
19966 | msg = _("symbol %s is weak and may be overridden later"); | |
42e5fcbf | 19967 | |
77db8e2e NC |
19968 | if (msg) |
19969 | { | |
19970 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19971 | msg, S_GET_NAME (fixP->fx_addsy)); | |
19972 | break; | |
19973 | } | |
19974 | } | |
19975 | ||
c19d1205 ZW |
19976 | newimm = encode_arm_immediate (value); |
19977 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 19978 | |
c19d1205 ZW |
19979 | /* If the instruction will fail, see if we can fix things up by |
19980 | changing the opcode. */ | |
19981 | if (newimm == (unsigned int) FAIL | |
19982 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
19983 | { | |
19984 | /* No ? OK - try using two ADD instructions to generate | |
19985 | the value. */ | |
19986 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 19987 | |
c19d1205 ZW |
19988 | /* Yes - then make sure that the second instruction is |
19989 | also an add. */ | |
19990 | if (newimm != (unsigned int) FAIL) | |
19991 | newinsn = temp; | |
19992 | /* Still No ? Try using a negated value. */ | |
19993 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
19994 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
19995 | /* Otherwise - give up. */ | |
19996 | else | |
19997 | { | |
19998 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19999 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
20000 | (long) value); | |
20001 | break; | |
20002 | } | |
b99bd4ef | 20003 | |
c19d1205 ZW |
20004 | /* Replace the first operand in the 2nd instruction (which |
20005 | is the PC) with the destination register. We have | |
20006 | already added in the PC in the first instruction and we | |
20007 | do not want to do it again. */ | |
20008 | newinsn &= ~ 0xf0000; | |
20009 | newinsn |= ((newinsn & 0x0f000) << 4); | |
20010 | } | |
b99bd4ef | 20011 | |
c19d1205 ZW |
20012 | newimm |= (temp & 0xfffff000); |
20013 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 20014 | |
c19d1205 ZW |
20015 | highpart |= (newinsn & 0xfffff000); |
20016 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
20017 | } | |
20018 | break; | |
b99bd4ef | 20019 | |
c19d1205 | 20020 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
20021 | if (!fixP->fx_done && seg->use_rela_p) |
20022 | value = 0; | |
20023 | ||
c19d1205 ZW |
20024 | case BFD_RELOC_ARM_LITERAL: |
20025 | sign = value >= 0; | |
b99bd4ef | 20026 | |
c19d1205 ZW |
20027 | if (value < 0) |
20028 | value = - value; | |
b99bd4ef | 20029 | |
c19d1205 | 20030 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 20031 | { |
c19d1205 ZW |
20032 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
20033 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20034 | _("invalid literal constant: pool needs to be closer")); | |
20035 | else | |
20036 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20037 | _("bad immediate value for offset (%ld)"), | |
20038 | (long) value); | |
20039 | break; | |
f03698e6 RE |
20040 | } |
20041 | ||
c19d1205 ZW |
20042 | newval = md_chars_to_number (buf, INSN_SIZE); |
20043 | newval &= 0xff7ff000; | |
20044 | newval |= value | (sign ? INDEX_UP : 0); | |
20045 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20046 | break; | |
b99bd4ef | 20047 | |
c19d1205 ZW |
20048 | case BFD_RELOC_ARM_OFFSET_IMM8: |
20049 | case BFD_RELOC_ARM_HWLITERAL: | |
20050 | sign = value >= 0; | |
b99bd4ef | 20051 | |
c19d1205 ZW |
20052 | if (value < 0) |
20053 | value = - value; | |
b99bd4ef | 20054 | |
c19d1205 | 20055 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 20056 | { |
c19d1205 ZW |
20057 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
20058 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20059 | _("invalid literal constant: pool needs to be closer")); | |
20060 | else | |
f9d4405b | 20061 | as_bad (_("bad immediate value for 8-bit offset (%ld)"), |
c19d1205 ZW |
20062 | (long) value); |
20063 | break; | |
b99bd4ef NC |
20064 | } |
20065 | ||
c19d1205 ZW |
20066 | newval = md_chars_to_number (buf, INSN_SIZE); |
20067 | newval &= 0xff7ff0f0; | |
20068 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
20069 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20070 | break; | |
b99bd4ef | 20071 | |
c19d1205 ZW |
20072 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
20073 | if (value < 0 || value > 1020 || value % 4 != 0) | |
20074 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20075 | _("bad immediate value for offset (%ld)"), (long) value); | |
20076 | value /= 4; | |
b99bd4ef | 20077 | |
c19d1205 | 20078 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
20079 | newval |= value; |
20080 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
20081 | break; | |
b99bd4ef | 20082 | |
c19d1205 ZW |
20083 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
20084 | /* This is a complicated relocation used for all varieties of Thumb32 | |
20085 | load/store instruction with immediate offset: | |
20086 | ||
20087 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
20088 | *4, optional writeback(W) | |
20089 | (doubleword load/store) | |
20090 | ||
20091 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
20092 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
20093 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
20094 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
20095 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
20096 | ||
20097 | Uppercase letters indicate bits that are already encoded at | |
20098 | this point. Lowercase letters are our problem. For the | |
20099 | second block of instructions, the secondary opcode nybble | |
20100 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
20101 | a PC-relative operation. */ | |
20102 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20103 | newval <<= 16; | |
20104 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 20105 | |
c19d1205 | 20106 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 20107 | { |
c19d1205 ZW |
20108 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
20109 | if (value >= 0) | |
20110 | newval |= (1 << 23); | |
20111 | else | |
20112 | value = -value; | |
20113 | if (value % 4 != 0) | |
20114 | { | |
20115 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20116 | _("offset not a multiple of 4")); | |
20117 | break; | |
20118 | } | |
20119 | value /= 4; | |
216d22bc | 20120 | if (value > 0xff) |
c19d1205 ZW |
20121 | { |
20122 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20123 | _("offset out of range")); | |
20124 | break; | |
20125 | } | |
20126 | newval &= ~0xff; | |
b99bd4ef | 20127 | } |
c19d1205 | 20128 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 20129 | { |
c19d1205 ZW |
20130 | /* PC-relative, 12-bit offset. */ |
20131 | if (value >= 0) | |
20132 | newval |= (1 << 23); | |
20133 | else | |
20134 | value = -value; | |
216d22bc | 20135 | if (value > 0xfff) |
c19d1205 ZW |
20136 | { |
20137 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20138 | _("offset out of range")); | |
20139 | break; | |
20140 | } | |
20141 | newval &= ~0xfff; | |
b99bd4ef | 20142 | } |
c19d1205 | 20143 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 20144 | { |
c19d1205 ZW |
20145 | /* Writeback: 8-bit, +/- offset. */ |
20146 | if (value >= 0) | |
20147 | newval |= (1 << 9); | |
20148 | else | |
20149 | value = -value; | |
216d22bc | 20150 | if (value > 0xff) |
c19d1205 ZW |
20151 | { |
20152 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20153 | _("offset out of range")); | |
20154 | break; | |
20155 | } | |
20156 | newval &= ~0xff; | |
b99bd4ef | 20157 | } |
c19d1205 | 20158 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 20159 | { |
c19d1205 | 20160 | /* T-instruction: positive 8-bit offset. */ |
216d22bc | 20161 | if (value < 0 || value > 0xff) |
b99bd4ef | 20162 | { |
c19d1205 ZW |
20163 | as_bad_where (fixP->fx_file, fixP->fx_line, |
20164 | _("offset out of range")); | |
20165 | break; | |
b99bd4ef | 20166 | } |
c19d1205 ZW |
20167 | newval &= ~0xff; |
20168 | newval |= value; | |
b99bd4ef NC |
20169 | } |
20170 | else | |
b99bd4ef | 20171 | { |
c19d1205 ZW |
20172 | /* Positive 12-bit or negative 8-bit offset. */ |
20173 | int limit; | |
20174 | if (value >= 0) | |
b99bd4ef | 20175 | { |
c19d1205 ZW |
20176 | newval |= (1 << 23); |
20177 | limit = 0xfff; | |
20178 | } | |
20179 | else | |
20180 | { | |
20181 | value = -value; | |
20182 | limit = 0xff; | |
20183 | } | |
20184 | if (value > limit) | |
20185 | { | |
20186 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20187 | _("offset out of range")); | |
20188 | break; | |
b99bd4ef | 20189 | } |
c19d1205 | 20190 | newval &= ~limit; |
b99bd4ef | 20191 | } |
b99bd4ef | 20192 | |
c19d1205 ZW |
20193 | newval |= value; |
20194 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
20195 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
20196 | break; | |
404ff6b5 | 20197 | |
c19d1205 ZW |
20198 | case BFD_RELOC_ARM_SHIFT_IMM: |
20199 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20200 | if (((unsigned long) value) > 32 | |
20201 | || (value == 32 | |
20202 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
20203 | { | |
20204 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20205 | _("shift expression is too large")); | |
20206 | break; | |
20207 | } | |
404ff6b5 | 20208 | |
c19d1205 ZW |
20209 | if (value == 0) |
20210 | /* Shifts of zero must be done as lsl. */ | |
20211 | newval &= ~0x60; | |
20212 | else if (value == 32) | |
20213 | value = 0; | |
20214 | newval &= 0xfffff07f; | |
20215 | newval |= (value & 0x1f) << 7; | |
20216 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20217 | break; | |
404ff6b5 | 20218 | |
c19d1205 | 20219 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
16805f35 | 20220 | case BFD_RELOC_ARM_T32_ADD_IMM: |
92e90b6e | 20221 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 20222 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
20223 | /* We claim that this fixup has been processed here, |
20224 | even if in fact we generate an error because we do | |
20225 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
20226 | fixP->fx_done = 1; | |
404ff6b5 | 20227 | |
c19d1205 ZW |
20228 | if (fixP->fx_addsy |
20229 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
20230 | { | |
20231 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20232 | _("undefined symbol %s used as an immediate value"), | |
20233 | S_GET_NAME (fixP->fx_addsy)); | |
20234 | break; | |
20235 | } | |
404ff6b5 | 20236 | |
c19d1205 ZW |
20237 | newval = md_chars_to_number (buf, THUMB_SIZE); |
20238 | newval <<= 16; | |
20239 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 20240 | |
16805f35 PB |
20241 | newimm = FAIL; |
20242 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE | |
20243 | || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
ef8d22e6 PB |
20244 | { |
20245 | newimm = encode_thumb32_immediate (value); | |
20246 | if (newimm == (unsigned int) FAIL) | |
20247 | newimm = thumb32_negate_data_op (&newval, value); | |
20248 | } | |
16805f35 PB |
20249 | if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE |
20250 | && newimm == (unsigned int) FAIL) | |
92e90b6e | 20251 | { |
16805f35 PB |
20252 | /* Turn add/sum into addw/subw. */ |
20253 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
20254 | newval = (newval & 0xfeffffff) | 0x02000000; | |
20255 | ||
e9f89963 PB |
20256 | /* 12 bit immediate for addw/subw. */ |
20257 | if (value < 0) | |
20258 | { | |
20259 | value = -value; | |
20260 | newval ^= 0x00a00000; | |
20261 | } | |
92e90b6e PB |
20262 | if (value > 0xfff) |
20263 | newimm = (unsigned int) FAIL; | |
20264 | else | |
20265 | newimm = value; | |
20266 | } | |
cc8a6dd0 | 20267 | |
c19d1205 | 20268 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 20269 | { |
c19d1205 ZW |
20270 | as_bad_where (fixP->fx_file, fixP->fx_line, |
20271 | _("invalid constant (%lx) after fixup"), | |
20272 | (unsigned long) value); | |
20273 | break; | |
3631a3c8 NC |
20274 | } |
20275 | ||
c19d1205 ZW |
20276 | newval |= (newimm & 0x800) << 15; |
20277 | newval |= (newimm & 0x700) << 4; | |
20278 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 20279 | |
c19d1205 ZW |
20280 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
20281 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
20282 | break; | |
a737bd4d | 20283 | |
3eb17e6b | 20284 | case BFD_RELOC_ARM_SMC: |
c19d1205 ZW |
20285 | if (((unsigned long) value) > 0xffff) |
20286 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3eb17e6b | 20287 | _("invalid smc expression")); |
2fc8bdac | 20288 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
20289 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
20290 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20291 | break; | |
a737bd4d | 20292 | |
c19d1205 | 20293 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 20294 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
20295 | { |
20296 | if (((unsigned long) value) > 0xff) | |
20297 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20298 | _("invalid swi expression")); | |
2fc8bdac | 20299 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
20300 | newval |= value; |
20301 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20302 | } | |
20303 | else | |
20304 | { | |
20305 | if (((unsigned long) value) > 0x00ffffff) | |
20306 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20307 | _("invalid swi expression")); | |
2fc8bdac | 20308 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
20309 | newval |= value; |
20310 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20311 | } | |
20312 | break; | |
a737bd4d | 20313 | |
c19d1205 ZW |
20314 | case BFD_RELOC_ARM_MULTI: |
20315 | if (((unsigned long) value) > 0xffff) | |
20316 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20317 | _("invalid expression in load/store multiple")); | |
20318 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
20319 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20320 | break; | |
a737bd4d | 20321 | |
c19d1205 | 20322 | #ifdef OBJ_ELF |
39b41c9c | 20323 | case BFD_RELOC_ARM_PCREL_CALL: |
267bf995 RR |
20324 | |
20325 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
20326 | && fixP->fx_addsy | |
20327 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20328 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20329 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
20330 | /* Flip the bl to blx. This is a simple flip | |
20331 | bit here because we generate PCREL_CALL for | |
20332 | unconditional bls. */ | |
20333 | { | |
20334 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20335 | newval = newval | 0x10000000; | |
20336 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20337 | temp = 1; | |
20338 | fixP->fx_done = 1; | |
20339 | } | |
39b41c9c PB |
20340 | else |
20341 | temp = 3; | |
20342 | goto arm_branch_common; | |
20343 | ||
20344 | case BFD_RELOC_ARM_PCREL_JUMP: | |
267bf995 RR |
20345 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
20346 | && fixP->fx_addsy | |
20347 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20348 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20349 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
20350 | { | |
20351 | /* This would map to a bl<cond>, b<cond>, | |
20352 | b<always> to a Thumb function. We | |
20353 | need to force a relocation for this particular | |
20354 | case. */ | |
20355 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20356 | fixP->fx_done = 0; | |
20357 | } | |
20358 | ||
2fc8bdac | 20359 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 20360 | #endif |
39b41c9c PB |
20361 | case BFD_RELOC_ARM_PCREL_BRANCH: |
20362 | temp = 3; | |
20363 | goto arm_branch_common; | |
a737bd4d | 20364 | |
39b41c9c | 20365 | case BFD_RELOC_ARM_PCREL_BLX: |
267bf995 | 20366 | |
39b41c9c | 20367 | temp = 1; |
267bf995 RR |
20368 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
20369 | && fixP->fx_addsy | |
20370 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20371 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20372 | && ARM_IS_FUNC (fixP->fx_addsy)) | |
20373 | { | |
20374 | /* Flip the blx to a bl and warn. */ | |
20375 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
20376 | newval = 0xeb000000; | |
20377 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
20378 | _("blx to '%s' an ARM ISA state function changed to bl"), | |
20379 | name); | |
20380 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20381 | temp = 3; | |
20382 | fixP->fx_done = 1; | |
20383 | } | |
20384 | ||
20385 | #ifdef OBJ_ELF | |
20386 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
20387 | fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL; | |
20388 | #endif | |
20389 | ||
39b41c9c | 20390 | arm_branch_common: |
c19d1205 | 20391 | /* We are going to store value (shifted right by two) in the |
39b41c9c PB |
20392 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
20393 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must | |
20394 | also be be clear. */ | |
20395 | if (value & temp) | |
c19d1205 | 20396 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
20397 | _("misaligned branch destination")); |
20398 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
20399 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
20400 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20401 | _("branch out of range")); | |
a737bd4d | 20402 | |
2fc8bdac | 20403 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 20404 | { |
2fc8bdac ZW |
20405 | newval = md_chars_to_number (buf, INSN_SIZE); |
20406 | newval |= (value >> 2) & 0x00ffffff; | |
7ae2971b PB |
20407 | /* Set the H bit on BLX instructions. */ |
20408 | if (temp == 1) | |
20409 | { | |
20410 | if (value & 2) | |
20411 | newval |= 0x01000000; | |
20412 | else | |
20413 | newval &= ~0x01000000; | |
20414 | } | |
2fc8bdac | 20415 | md_number_to_chars (buf, newval, INSN_SIZE); |
c19d1205 | 20416 | } |
c19d1205 | 20417 | break; |
a737bd4d | 20418 | |
25fe350b MS |
20419 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ |
20420 | /* CBZ can only branch forward. */ | |
a737bd4d | 20421 | |
738755b0 MS |
20422 | /* Attempts to use CBZ to branch to the next instruction |
20423 | (which, strictly speaking, are prohibited) will be turned into | |
20424 | no-ops. | |
20425 | ||
20426 | FIXME: It may be better to remove the instruction completely and | |
20427 | perform relaxation. */ | |
20428 | if (value == -2) | |
2fc8bdac ZW |
20429 | { |
20430 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
738755b0 | 20431 | newval = 0xbf00; /* NOP encoding T1 */ |
2fc8bdac ZW |
20432 | md_number_to_chars (buf, newval, THUMB_SIZE); |
20433 | } | |
738755b0 MS |
20434 | else |
20435 | { | |
20436 | if (value & ~0x7e) | |
20437 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20438 | _("branch out of range")); | |
20439 | ||
20440 | if (fixP->fx_done || !seg->use_rela_p) | |
20441 | { | |
20442 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20443 | newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); | |
20444 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20445 | } | |
20446 | } | |
c19d1205 | 20447 | break; |
a737bd4d | 20448 | |
c19d1205 | 20449 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac ZW |
20450 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
20451 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20452 | _("branch out of range")); | |
a737bd4d | 20453 | |
2fc8bdac ZW |
20454 | if (fixP->fx_done || !seg->use_rela_p) |
20455 | { | |
20456 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20457 | newval |= (value & 0x1ff) >> 1; | |
20458 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20459 | } | |
c19d1205 | 20460 | break; |
a737bd4d | 20461 | |
c19d1205 | 20462 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac ZW |
20463 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
20464 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20465 | _("branch out of range")); | |
a737bd4d | 20466 | |
2fc8bdac ZW |
20467 | if (fixP->fx_done || !seg->use_rela_p) |
20468 | { | |
20469 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20470 | newval |= (value & 0xfff) >> 1; | |
20471 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20472 | } | |
c19d1205 | 20473 | break; |
a737bd4d | 20474 | |
c19d1205 | 20475 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
267bf995 RR |
20476 | if (fixP->fx_addsy |
20477 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20478 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20479 | && S_IS_DEFINED (fixP->fx_addsy) | |
20480 | && ARM_IS_FUNC (fixP->fx_addsy) | |
20481 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20482 | { | |
20483 | /* Force a relocation for a branch 20 bits wide. */ | |
20484 | fixP->fx_done = 0; | |
20485 | } | |
2fc8bdac ZW |
20486 | if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) |
20487 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20488 | _("conditional branch out of range")); | |
404ff6b5 | 20489 | |
2fc8bdac ZW |
20490 | if (fixP->fx_done || !seg->use_rela_p) |
20491 | { | |
20492 | offsetT newval2; | |
20493 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 20494 | |
2fc8bdac ZW |
20495 | S = (value & 0x00100000) >> 20; |
20496 | J2 = (value & 0x00080000) >> 19; | |
20497 | J1 = (value & 0x00040000) >> 18; | |
20498 | hi = (value & 0x0003f000) >> 12; | |
20499 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 20500 | |
2fc8bdac ZW |
20501 | newval = md_chars_to_number (buf, THUMB_SIZE); |
20502 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20503 | newval |= (S << 10) | hi; | |
20504 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
20505 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20506 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
20507 | } | |
c19d1205 | 20508 | break; |
6c43fab6 | 20509 | |
c19d1205 | 20510 | case BFD_RELOC_THUMB_PCREL_BLX: |
267bf995 RR |
20511 | |
20512 | /* If there is a blx from a thumb state function to | |
20513 | another thumb function flip this to a bl and warn | |
20514 | about it. */ | |
20515 | ||
20516 | if (fixP->fx_addsy | |
20517 | && S_IS_DEFINED (fixP->fx_addsy) | |
20518 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20519 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20520 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
20521 | { | |
20522 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
20523 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
20524 | _("blx to Thumb func '%s' from Thumb ISA state changed to bl"), | |
20525 | name); | |
20526 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20527 | newval = newval | 0x1000; | |
20528 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
20529 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
20530 | fixP->fx_done = 1; | |
20531 | } | |
20532 | ||
20533 | ||
20534 | goto thumb_bl_common; | |
20535 | ||
c19d1205 | 20536 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
267bf995 RR |
20537 | |
20538 | /* A bl from Thumb state ISA to an internal ARM state function | |
20539 | is converted to a blx. */ | |
20540 | if (fixP->fx_addsy | |
20541 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20542 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20543 | && S_IS_DEFINED (fixP->fx_addsy) | |
20544 | && ARM_IS_FUNC (fixP->fx_addsy) | |
20545 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20546 | { | |
20547 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20548 | newval = newval & ~0x1000; | |
20549 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
20550 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX; | |
20551 | fixP->fx_done = 1; | |
20552 | } | |
20553 | ||
20554 | thumb_bl_common: | |
20555 | ||
20556 | #ifdef OBJ_ELF | |
20557 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 && | |
20558 | fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) | |
20559 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
20560 | #endif | |
20561 | ||
2fc8bdac ZW |
20562 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
20563 | /* For a BLX instruction, make sure that the relocation is rounded up | |
20564 | to a word boundary. This follows the semantics of the instruction | |
20565 | which specifies that bit 1 of the target address will come from bit | |
20566 | 1 of the base address. */ | |
20567 | value = (value + 1) & ~ 1; | |
404ff6b5 | 20568 | |
2fc8bdac | 20569 | |
4a42ebbc RR |
20570 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
20571 | { | |
20572 | if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))) | |
20573 | { | |
20574 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20575 | _("branch out of range")); | |
20576 | } | |
20577 | else if ((value & ~0x1ffffff) | |
20578 | && ((value & ~0x1ffffff) != ~0x1ffffff)) | |
20579 | { | |
20580 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20581 | _("Thumb2 branch out of range")); | |
20582 | } | |
c19d1205 | 20583 | } |
4a42ebbc RR |
20584 | |
20585 | if (fixP->fx_done || !seg->use_rela_p) | |
20586 | encode_thumb2_b_bl_offset (buf, value); | |
20587 | ||
c19d1205 | 20588 | break; |
404ff6b5 | 20589 | |
c19d1205 | 20590 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac ZW |
20591 | if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) |
20592 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20593 | _("branch out of range")); | |
6c43fab6 | 20594 | |
2fc8bdac | 20595 | if (fixP->fx_done || !seg->use_rela_p) |
4a42ebbc | 20596 | encode_thumb2_b_bl_offset (buf, value); |
6c43fab6 | 20597 | |
2fc8bdac | 20598 | break; |
a737bd4d | 20599 | |
2fc8bdac ZW |
20600 | case BFD_RELOC_8: |
20601 | if (fixP->fx_done || !seg->use_rela_p) | |
20602 | md_number_to_chars (buf, value, 1); | |
c19d1205 | 20603 | break; |
a737bd4d | 20604 | |
c19d1205 | 20605 | case BFD_RELOC_16: |
2fc8bdac | 20606 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 20607 | md_number_to_chars (buf, value, 2); |
c19d1205 | 20608 | break; |
a737bd4d | 20609 | |
c19d1205 ZW |
20610 | #ifdef OBJ_ELF |
20611 | case BFD_RELOC_ARM_TLS_GD32: | |
20612 | case BFD_RELOC_ARM_TLS_LE32: | |
20613 | case BFD_RELOC_ARM_TLS_IE32: | |
20614 | case BFD_RELOC_ARM_TLS_LDM32: | |
20615 | case BFD_RELOC_ARM_TLS_LDO32: | |
20616 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
20617 | /* fall through */ | |
6c43fab6 | 20618 | |
c19d1205 ZW |
20619 | case BFD_RELOC_ARM_GOT32: |
20620 | case BFD_RELOC_ARM_GOTOFF: | |
2fc8bdac ZW |
20621 | if (fixP->fx_done || !seg->use_rela_p) |
20622 | md_number_to_chars (buf, 0, 4); | |
c19d1205 | 20623 | break; |
b43420e6 NC |
20624 | |
20625 | case BFD_RELOC_ARM_GOT_PREL: | |
20626 | if (fixP->fx_done || !seg->use_rela_p) | |
20627 | md_number_to_chars (buf, value, 4); | |
20628 | break; | |
20629 | ||
9a6f4e97 NS |
20630 | case BFD_RELOC_ARM_TARGET2: |
20631 | /* TARGET2 is not partial-inplace, so we need to write the | |
20632 | addend here for REL targets, because it won't be written out | |
20633 | during reloc processing later. */ | |
20634 | if (fixP->fx_done || !seg->use_rela_p) | |
20635 | md_number_to_chars (buf, fixP->fx_offset, 4); | |
20636 | break; | |
c19d1205 | 20637 | #endif |
6c43fab6 | 20638 | |
c19d1205 ZW |
20639 | case BFD_RELOC_RVA: |
20640 | case BFD_RELOC_32: | |
20641 | case BFD_RELOC_ARM_TARGET1: | |
20642 | case BFD_RELOC_ARM_ROSEGREL32: | |
20643 | case BFD_RELOC_ARM_SBREL32: | |
20644 | case BFD_RELOC_32_PCREL: | |
f0927246 NC |
20645 | #ifdef TE_PE |
20646 | case BFD_RELOC_32_SECREL: | |
20647 | #endif | |
2fc8bdac | 20648 | if (fixP->fx_done || !seg->use_rela_p) |
53baae48 NC |
20649 | #ifdef TE_WINCE |
20650 | /* For WinCE we only do this for pcrel fixups. */ | |
20651 | if (fixP->fx_done || fixP->fx_pcrel) | |
20652 | #endif | |
20653 | md_number_to_chars (buf, value, 4); | |
c19d1205 | 20654 | break; |
6c43fab6 | 20655 | |
c19d1205 ZW |
20656 | #ifdef OBJ_ELF |
20657 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 20658 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
20659 | { |
20660 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
20661 | if ((value ^ (value >> 1)) & 0x40000000) | |
20662 | { | |
20663 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20664 | _("rel31 relocation overflow")); | |
20665 | } | |
20666 | newval |= value & 0x7fffffff; | |
20667 | md_number_to_chars (buf, newval, 4); | |
20668 | } | |
20669 | break; | |
c19d1205 | 20670 | #endif |
a737bd4d | 20671 | |
c19d1205 | 20672 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 20673 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
c19d1205 ZW |
20674 | if (value < -1023 || value > 1023 || (value & 3)) |
20675 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20676 | _("co-processor offset out of range")); | |
20677 | cp_off_common: | |
20678 | sign = value >= 0; | |
20679 | if (value < 0) | |
20680 | value = -value; | |
8f06b2d8 PB |
20681 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
20682 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
20683 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20684 | else | |
20685 | newval = get_thumb32_insn (buf); | |
20686 | newval &= 0xff7fff00; | |
c19d1205 | 20687 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); |
8f06b2d8 PB |
20688 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
20689 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
20690 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20691 | else | |
20692 | put_thumb32_insn (buf, newval); | |
c19d1205 | 20693 | break; |
a737bd4d | 20694 | |
c19d1205 | 20695 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 20696 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
20697 | if (value < -255 || value > 255) |
20698 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20699 | _("co-processor offset out of range")); | |
df7849c5 | 20700 | value *= 4; |
c19d1205 | 20701 | goto cp_off_common; |
6c43fab6 | 20702 | |
c19d1205 ZW |
20703 | case BFD_RELOC_ARM_THUMB_OFFSET: |
20704 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20705 | /* Exactly what ranges, and where the offset is inserted depends | |
20706 | on the type of instruction, we can establish this from the | |
20707 | top 4 bits. */ | |
20708 | switch (newval >> 12) | |
20709 | { | |
20710 | case 4: /* PC load. */ | |
20711 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
20712 | forced to zero for these loads; md_pcrel_from has already | |
20713 | compensated for this. */ | |
20714 | if (value & 3) | |
20715 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20716 | _("invalid offset, target not word aligned (0x%08lX)"), | |
0359e808 NC |
20717 | (((unsigned long) fixP->fx_frag->fr_address |
20718 | + (unsigned long) fixP->fx_where) & ~3) | |
20719 | + (unsigned long) value); | |
a737bd4d | 20720 | |
c19d1205 ZW |
20721 | if (value & ~0x3fc) |
20722 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20723 | _("invalid offset, value too big (0x%08lX)"), | |
20724 | (long) value); | |
a737bd4d | 20725 | |
c19d1205 ZW |
20726 | newval |= value >> 2; |
20727 | break; | |
a737bd4d | 20728 | |
c19d1205 ZW |
20729 | case 9: /* SP load/store. */ |
20730 | if (value & ~0x3fc) | |
20731 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20732 | _("invalid offset, value too big (0x%08lX)"), | |
20733 | (long) value); | |
20734 | newval |= value >> 2; | |
20735 | break; | |
6c43fab6 | 20736 | |
c19d1205 ZW |
20737 | case 6: /* Word load/store. */ |
20738 | if (value & ~0x7c) | |
20739 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20740 | _("invalid offset, value too big (0x%08lX)"), | |
20741 | (long) value); | |
20742 | newval |= value << 4; /* 6 - 2. */ | |
20743 | break; | |
a737bd4d | 20744 | |
c19d1205 ZW |
20745 | case 7: /* Byte load/store. */ |
20746 | if (value & ~0x1f) | |
20747 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20748 | _("invalid offset, value too big (0x%08lX)"), | |
20749 | (long) value); | |
20750 | newval |= value << 6; | |
20751 | break; | |
a737bd4d | 20752 | |
c19d1205 ZW |
20753 | case 8: /* Halfword load/store. */ |
20754 | if (value & ~0x3e) | |
20755 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20756 | _("invalid offset, value too big (0x%08lX)"), | |
20757 | (long) value); | |
20758 | newval |= value << 5; /* 6 - 1. */ | |
20759 | break; | |
a737bd4d | 20760 | |
c19d1205 ZW |
20761 | default: |
20762 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20763 | "Unable to process relocation for thumb opcode: %lx", | |
20764 | (unsigned long) newval); | |
20765 | break; | |
20766 | } | |
20767 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20768 | break; | |
a737bd4d | 20769 | |
c19d1205 ZW |
20770 | case BFD_RELOC_ARM_THUMB_ADD: |
20771 | /* This is a complicated relocation, since we use it for all of | |
20772 | the following immediate relocations: | |
a737bd4d | 20773 | |
c19d1205 ZW |
20774 | 3bit ADD/SUB |
20775 | 8bit ADD/SUB | |
20776 | 9bit ADD/SUB SP word-aligned | |
20777 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 20778 | |
c19d1205 ZW |
20779 | The type of instruction being processed is encoded in the |
20780 | instruction field: | |
a737bd4d | 20781 | |
c19d1205 ZW |
20782 | 0x8000 SUB |
20783 | 0x00F0 Rd | |
20784 | 0x000F Rs | |
20785 | */ | |
20786 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20787 | { | |
20788 | int rd = (newval >> 4) & 0xf; | |
20789 | int rs = newval & 0xf; | |
20790 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 20791 | |
c19d1205 ZW |
20792 | /* Check for HI regs, only very restricted cases allowed: |
20793 | Adjusting SP, and using PC or SP to get an address. */ | |
20794 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
20795 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
20796 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20797 | _("invalid Hi register with immediate")); | |
a737bd4d | 20798 | |
c19d1205 ZW |
20799 | /* If value is negative, choose the opposite instruction. */ |
20800 | if (value < 0) | |
20801 | { | |
20802 | value = -value; | |
20803 | subtract = !subtract; | |
20804 | if (value < 0) | |
20805 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20806 | _("immediate value out of range")); | |
20807 | } | |
a737bd4d | 20808 | |
c19d1205 ZW |
20809 | if (rd == REG_SP) |
20810 | { | |
20811 | if (value & ~0x1fc) | |
20812 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20813 | _("invalid immediate for stack address calculation")); | |
20814 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
20815 | newval |= value >> 2; | |
20816 | } | |
20817 | else if (rs == REG_PC || rs == REG_SP) | |
20818 | { | |
20819 | if (subtract || value & ~0x3fc) | |
20820 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20821 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
20822 | (unsigned long) value); | |
20823 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); | |
20824 | newval |= rd << 8; | |
20825 | newval |= value >> 2; | |
20826 | } | |
20827 | else if (rs == rd) | |
20828 | { | |
20829 | if (value & ~0xff) | |
20830 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20831 | _("immediate value out of range")); | |
20832 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
20833 | newval |= (rd << 8) | value; | |
20834 | } | |
20835 | else | |
20836 | { | |
20837 | if (value & ~0x7) | |
20838 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20839 | _("immediate value out of range")); | |
20840 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
20841 | newval |= rd | (rs << 3) | (value << 6); | |
20842 | } | |
20843 | } | |
20844 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20845 | break; | |
a737bd4d | 20846 | |
c19d1205 ZW |
20847 | case BFD_RELOC_ARM_THUMB_IMM: |
20848 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20849 | if (value < 0 || value > 255) | |
20850 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
4e6e072b | 20851 | _("invalid immediate: %ld is out of range"), |
c19d1205 ZW |
20852 | (long) value); |
20853 | newval |= value; | |
20854 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20855 | break; | |
a737bd4d | 20856 | |
c19d1205 ZW |
20857 | case BFD_RELOC_ARM_THUMB_SHIFT: |
20858 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
20859 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
20860 | temp = newval & 0xf800; | |
20861 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
20862 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20863 | _("invalid shift value: %ld"), (long) value); | |
20864 | /* Shifts of zero must be encoded as LSL. */ | |
20865 | if (value == 0) | |
20866 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
20867 | /* Shifts of 32 are encoded as zero. */ | |
20868 | else if (value == 32) | |
20869 | value = 0; | |
20870 | newval |= value << 6; | |
20871 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20872 | break; | |
a737bd4d | 20873 | |
c19d1205 ZW |
20874 | case BFD_RELOC_VTABLE_INHERIT: |
20875 | case BFD_RELOC_VTABLE_ENTRY: | |
20876 | fixP->fx_done = 0; | |
20877 | return; | |
6c43fab6 | 20878 | |
b6895b4f PB |
20879 | case BFD_RELOC_ARM_MOVW: |
20880 | case BFD_RELOC_ARM_MOVT: | |
20881 | case BFD_RELOC_ARM_THUMB_MOVW: | |
20882 | case BFD_RELOC_ARM_THUMB_MOVT: | |
20883 | if (fixP->fx_done || !seg->use_rela_p) | |
20884 | { | |
20885 | /* REL format relocations are limited to a 16-bit addend. */ | |
20886 | if (!fixP->fx_done) | |
20887 | { | |
39623e12 | 20888 | if (value < -0x8000 || value > 0x7fff) |
b6895b4f | 20889 | as_bad_where (fixP->fx_file, fixP->fx_line, |
ff5075ca | 20890 | _("offset out of range")); |
b6895b4f PB |
20891 | } |
20892 | else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
20893 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
20894 | { | |
20895 | value >>= 16; | |
20896 | } | |
20897 | ||
20898 | if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
20899 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
20900 | { | |
20901 | newval = get_thumb32_insn (buf); | |
20902 | newval &= 0xfbf08f00; | |
20903 | newval |= (value & 0xf000) << 4; | |
20904 | newval |= (value & 0x0800) << 15; | |
20905 | newval |= (value & 0x0700) << 4; | |
20906 | newval |= (value & 0x00ff); | |
20907 | put_thumb32_insn (buf, newval); | |
20908 | } | |
20909 | else | |
20910 | { | |
20911 | newval = md_chars_to_number (buf, 4); | |
20912 | newval &= 0xfff0f000; | |
20913 | newval |= value & 0x0fff; | |
20914 | newval |= (value & 0xf000) << 4; | |
20915 | md_number_to_chars (buf, newval, 4); | |
20916 | } | |
20917 | } | |
20918 | return; | |
20919 | ||
4962c51a MS |
20920 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
20921 | case BFD_RELOC_ARM_ALU_PC_G0: | |
20922 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
20923 | case BFD_RELOC_ARM_ALU_PC_G1: | |
20924 | case BFD_RELOC_ARM_ALU_PC_G2: | |
20925 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
20926 | case BFD_RELOC_ARM_ALU_SB_G0: | |
20927 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
20928 | case BFD_RELOC_ARM_ALU_SB_G1: | |
20929 | case BFD_RELOC_ARM_ALU_SB_G2: | |
9c2799c2 | 20930 | gas_assert (!fixP->fx_done); |
4962c51a MS |
20931 | if (!seg->use_rela_p) |
20932 | { | |
20933 | bfd_vma insn; | |
20934 | bfd_vma encoded_addend; | |
20935 | bfd_vma addend_abs = abs (value); | |
20936 | ||
20937 | /* Check that the absolute value of the addend can be | |
20938 | expressed as an 8-bit constant plus a rotation. */ | |
20939 | encoded_addend = encode_arm_immediate (addend_abs); | |
20940 | if (encoded_addend == (unsigned int) FAIL) | |
20941 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20942 | _("the offset 0x%08lX is not representable"), | |
495bde8e | 20943 | (unsigned long) addend_abs); |
4962c51a MS |
20944 | |
20945 | /* Extract the instruction. */ | |
20946 | insn = md_chars_to_number (buf, INSN_SIZE); | |
20947 | ||
20948 | /* If the addend is positive, use an ADD instruction. | |
20949 | Otherwise use a SUB. Take care not to destroy the S bit. */ | |
20950 | insn &= 0xff1fffff; | |
20951 | if (value < 0) | |
20952 | insn |= 1 << 22; | |
20953 | else | |
20954 | insn |= 1 << 23; | |
20955 | ||
20956 | /* Place the encoded addend into the first 12 bits of the | |
20957 | instruction. */ | |
20958 | insn &= 0xfffff000; | |
20959 | insn |= encoded_addend; | |
5f4273c7 NC |
20960 | |
20961 | /* Update the instruction. */ | |
4962c51a MS |
20962 | md_number_to_chars (buf, insn, INSN_SIZE); |
20963 | } | |
20964 | break; | |
20965 | ||
20966 | case BFD_RELOC_ARM_LDR_PC_G0: | |
20967 | case BFD_RELOC_ARM_LDR_PC_G1: | |
20968 | case BFD_RELOC_ARM_LDR_PC_G2: | |
20969 | case BFD_RELOC_ARM_LDR_SB_G0: | |
20970 | case BFD_RELOC_ARM_LDR_SB_G1: | |
20971 | case BFD_RELOC_ARM_LDR_SB_G2: | |
9c2799c2 | 20972 | gas_assert (!fixP->fx_done); |
4962c51a MS |
20973 | if (!seg->use_rela_p) |
20974 | { | |
20975 | bfd_vma insn; | |
20976 | bfd_vma addend_abs = abs (value); | |
20977 | ||
20978 | /* Check that the absolute value of the addend can be | |
20979 | encoded in 12 bits. */ | |
20980 | if (addend_abs >= 0x1000) | |
20981 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20982 | _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), | |
495bde8e | 20983 | (unsigned long) addend_abs); |
4962c51a MS |
20984 | |
20985 | /* Extract the instruction. */ | |
20986 | insn = md_chars_to_number (buf, INSN_SIZE); | |
20987 | ||
20988 | /* If the addend is negative, clear bit 23 of the instruction. | |
20989 | Otherwise set it. */ | |
20990 | if (value < 0) | |
20991 | insn &= ~(1 << 23); | |
20992 | else | |
20993 | insn |= 1 << 23; | |
20994 | ||
20995 | /* Place the absolute value of the addend into the first 12 bits | |
20996 | of the instruction. */ | |
20997 | insn &= 0xfffff000; | |
20998 | insn |= addend_abs; | |
5f4273c7 NC |
20999 | |
21000 | /* Update the instruction. */ | |
4962c51a MS |
21001 | md_number_to_chars (buf, insn, INSN_SIZE); |
21002 | } | |
21003 | break; | |
21004 | ||
21005 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
21006 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
21007 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
21008 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
21009 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
21010 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
9c2799c2 | 21011 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21012 | if (!seg->use_rela_p) |
21013 | { | |
21014 | bfd_vma insn; | |
21015 | bfd_vma addend_abs = abs (value); | |
21016 | ||
21017 | /* Check that the absolute value of the addend can be | |
21018 | encoded in 8 bits. */ | |
21019 | if (addend_abs >= 0x100) | |
21020 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21021 | _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), | |
495bde8e | 21022 | (unsigned long) addend_abs); |
4962c51a MS |
21023 | |
21024 | /* Extract the instruction. */ | |
21025 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21026 | ||
21027 | /* If the addend is negative, clear bit 23 of the instruction. | |
21028 | Otherwise set it. */ | |
21029 | if (value < 0) | |
21030 | insn &= ~(1 << 23); | |
21031 | else | |
21032 | insn |= 1 << 23; | |
21033 | ||
21034 | /* Place the first four bits of the absolute value of the addend | |
21035 | into the first 4 bits of the instruction, and the remaining | |
21036 | four into bits 8 .. 11. */ | |
21037 | insn &= 0xfffff0f0; | |
21038 | insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); | |
5f4273c7 NC |
21039 | |
21040 | /* Update the instruction. */ | |
4962c51a MS |
21041 | md_number_to_chars (buf, insn, INSN_SIZE); |
21042 | } | |
21043 | break; | |
21044 | ||
21045 | case BFD_RELOC_ARM_LDC_PC_G0: | |
21046 | case BFD_RELOC_ARM_LDC_PC_G1: | |
21047 | case BFD_RELOC_ARM_LDC_PC_G2: | |
21048 | case BFD_RELOC_ARM_LDC_SB_G0: | |
21049 | case BFD_RELOC_ARM_LDC_SB_G1: | |
21050 | case BFD_RELOC_ARM_LDC_SB_G2: | |
9c2799c2 | 21051 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21052 | if (!seg->use_rela_p) |
21053 | { | |
21054 | bfd_vma insn; | |
21055 | bfd_vma addend_abs = abs (value); | |
21056 | ||
21057 | /* Check that the absolute value of the addend is a multiple of | |
21058 | four and, when divided by four, fits in 8 bits. */ | |
21059 | if (addend_abs & 0x3) | |
21060 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21061 | _("bad offset 0x%08lX (must be word-aligned)"), | |
495bde8e | 21062 | (unsigned long) addend_abs); |
4962c51a MS |
21063 | |
21064 | if ((addend_abs >> 2) > 0xff) | |
21065 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21066 | _("bad offset 0x%08lX (must be an 8-bit number of words)"), | |
495bde8e | 21067 | (unsigned long) addend_abs); |
4962c51a MS |
21068 | |
21069 | /* Extract the instruction. */ | |
21070 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21071 | ||
21072 | /* If the addend is negative, clear bit 23 of the instruction. | |
21073 | Otherwise set it. */ | |
21074 | if (value < 0) | |
21075 | insn &= ~(1 << 23); | |
21076 | else | |
21077 | insn |= 1 << 23; | |
21078 | ||
21079 | /* Place the addend (divided by four) into the first eight | |
21080 | bits of the instruction. */ | |
21081 | insn &= 0xfffffff0; | |
21082 | insn |= addend_abs >> 2; | |
5f4273c7 NC |
21083 | |
21084 | /* Update the instruction. */ | |
4962c51a MS |
21085 | md_number_to_chars (buf, insn, INSN_SIZE); |
21086 | } | |
21087 | break; | |
21088 | ||
845b51d6 PB |
21089 | case BFD_RELOC_ARM_V4BX: |
21090 | /* This will need to go in the object file. */ | |
21091 | fixP->fx_done = 0; | |
21092 | break; | |
21093 | ||
c19d1205 ZW |
21094 | case BFD_RELOC_UNUSED: |
21095 | default: | |
21096 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21097 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
21098 | } | |
6c43fab6 RE |
21099 | } |
21100 | ||
c19d1205 ZW |
21101 | /* Translate internal representation of relocation info to BFD target |
21102 | format. */ | |
a737bd4d | 21103 | |
c19d1205 | 21104 | arelent * |
00a97672 | 21105 | tc_gen_reloc (asection *section, fixS *fixp) |
a737bd4d | 21106 | { |
c19d1205 ZW |
21107 | arelent * reloc; |
21108 | bfd_reloc_code_real_type code; | |
a737bd4d | 21109 | |
21d799b5 | 21110 | reloc = (arelent *) xmalloc (sizeof (arelent)); |
a737bd4d | 21111 | |
21d799b5 | 21112 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
c19d1205 ZW |
21113 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
21114 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 21115 | |
2fc8bdac | 21116 | if (fixp->fx_pcrel) |
00a97672 RS |
21117 | { |
21118 | if (section->use_rela_p) | |
21119 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
21120 | else | |
21121 | fixp->fx_offset = reloc->address; | |
21122 | } | |
c19d1205 | 21123 | reloc->addend = fixp->fx_offset; |
a737bd4d | 21124 | |
c19d1205 | 21125 | switch (fixp->fx_r_type) |
a737bd4d | 21126 | { |
c19d1205 ZW |
21127 | case BFD_RELOC_8: |
21128 | if (fixp->fx_pcrel) | |
21129 | { | |
21130 | code = BFD_RELOC_8_PCREL; | |
21131 | break; | |
21132 | } | |
a737bd4d | 21133 | |
c19d1205 ZW |
21134 | case BFD_RELOC_16: |
21135 | if (fixp->fx_pcrel) | |
21136 | { | |
21137 | code = BFD_RELOC_16_PCREL; | |
21138 | break; | |
21139 | } | |
6c43fab6 | 21140 | |
c19d1205 ZW |
21141 | case BFD_RELOC_32: |
21142 | if (fixp->fx_pcrel) | |
21143 | { | |
21144 | code = BFD_RELOC_32_PCREL; | |
21145 | break; | |
21146 | } | |
a737bd4d | 21147 | |
b6895b4f PB |
21148 | case BFD_RELOC_ARM_MOVW: |
21149 | if (fixp->fx_pcrel) | |
21150 | { | |
21151 | code = BFD_RELOC_ARM_MOVW_PCREL; | |
21152 | break; | |
21153 | } | |
21154 | ||
21155 | case BFD_RELOC_ARM_MOVT: | |
21156 | if (fixp->fx_pcrel) | |
21157 | { | |
21158 | code = BFD_RELOC_ARM_MOVT_PCREL; | |
21159 | break; | |
21160 | } | |
21161 | ||
21162 | case BFD_RELOC_ARM_THUMB_MOVW: | |
21163 | if (fixp->fx_pcrel) | |
21164 | { | |
21165 | code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; | |
21166 | break; | |
21167 | } | |
21168 | ||
21169 | case BFD_RELOC_ARM_THUMB_MOVT: | |
21170 | if (fixp->fx_pcrel) | |
21171 | { | |
21172 | code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; | |
21173 | break; | |
21174 | } | |
21175 | ||
c19d1205 ZW |
21176 | case BFD_RELOC_NONE: |
21177 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
21178 | case BFD_RELOC_ARM_PCREL_BLX: | |
21179 | case BFD_RELOC_RVA: | |
21180 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
21181 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
21182 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
21183 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
21184 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
21185 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
c19d1205 ZW |
21186 | case BFD_RELOC_VTABLE_ENTRY: |
21187 | case BFD_RELOC_VTABLE_INHERIT: | |
f0927246 NC |
21188 | #ifdef TE_PE |
21189 | case BFD_RELOC_32_SECREL: | |
21190 | #endif | |
c19d1205 ZW |
21191 | code = fixp->fx_r_type; |
21192 | break; | |
a737bd4d | 21193 | |
00adf2d4 JB |
21194 | case BFD_RELOC_THUMB_PCREL_BLX: |
21195 | #ifdef OBJ_ELF | |
21196 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
21197 | code = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
21198 | else | |
21199 | #endif | |
21200 | code = BFD_RELOC_THUMB_PCREL_BLX; | |
21201 | break; | |
21202 | ||
c19d1205 ZW |
21203 | case BFD_RELOC_ARM_LITERAL: |
21204 | case BFD_RELOC_ARM_HWLITERAL: | |
21205 | /* If this is called then the a literal has | |
21206 | been referenced across a section boundary. */ | |
21207 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21208 | _("literal referenced across section boundary")); | |
21209 | return NULL; | |
a737bd4d | 21210 | |
c19d1205 ZW |
21211 | #ifdef OBJ_ELF |
21212 | case BFD_RELOC_ARM_GOT32: | |
21213 | case BFD_RELOC_ARM_GOTOFF: | |
b43420e6 | 21214 | case BFD_RELOC_ARM_GOT_PREL: |
c19d1205 ZW |
21215 | case BFD_RELOC_ARM_PLT32: |
21216 | case BFD_RELOC_ARM_TARGET1: | |
21217 | case BFD_RELOC_ARM_ROSEGREL32: | |
21218 | case BFD_RELOC_ARM_SBREL32: | |
21219 | case BFD_RELOC_ARM_PREL31: | |
21220 | case BFD_RELOC_ARM_TARGET2: | |
21221 | case BFD_RELOC_ARM_TLS_LE32: | |
21222 | case BFD_RELOC_ARM_TLS_LDO32: | |
39b41c9c PB |
21223 | case BFD_RELOC_ARM_PCREL_CALL: |
21224 | case BFD_RELOC_ARM_PCREL_JUMP: | |
4962c51a MS |
21225 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
21226 | case BFD_RELOC_ARM_ALU_PC_G0: | |
21227 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
21228 | case BFD_RELOC_ARM_ALU_PC_G1: | |
21229 | case BFD_RELOC_ARM_ALU_PC_G2: | |
21230 | case BFD_RELOC_ARM_LDR_PC_G0: | |
21231 | case BFD_RELOC_ARM_LDR_PC_G1: | |
21232 | case BFD_RELOC_ARM_LDR_PC_G2: | |
21233 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
21234 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
21235 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
21236 | case BFD_RELOC_ARM_LDC_PC_G0: | |
21237 | case BFD_RELOC_ARM_LDC_PC_G1: | |
21238 | case BFD_RELOC_ARM_LDC_PC_G2: | |
21239 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
21240 | case BFD_RELOC_ARM_ALU_SB_G0: | |
21241 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
21242 | case BFD_RELOC_ARM_ALU_SB_G1: | |
21243 | case BFD_RELOC_ARM_ALU_SB_G2: | |
21244 | case BFD_RELOC_ARM_LDR_SB_G0: | |
21245 | case BFD_RELOC_ARM_LDR_SB_G1: | |
21246 | case BFD_RELOC_ARM_LDR_SB_G2: | |
21247 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
21248 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
21249 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
21250 | case BFD_RELOC_ARM_LDC_SB_G0: | |
21251 | case BFD_RELOC_ARM_LDC_SB_G1: | |
21252 | case BFD_RELOC_ARM_LDC_SB_G2: | |
845b51d6 | 21253 | case BFD_RELOC_ARM_V4BX: |
c19d1205 ZW |
21254 | code = fixp->fx_r_type; |
21255 | break; | |
a737bd4d | 21256 | |
c19d1205 ZW |
21257 | case BFD_RELOC_ARM_TLS_GD32: |
21258 | case BFD_RELOC_ARM_TLS_IE32: | |
21259 | case BFD_RELOC_ARM_TLS_LDM32: | |
21260 | /* BFD will include the symbol's address in the addend. | |
21261 | But we don't want that, so subtract it out again here. */ | |
21262 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
21263 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
21264 | code = fixp->fx_r_type; | |
21265 | break; | |
21266 | #endif | |
a737bd4d | 21267 | |
c19d1205 ZW |
21268 | case BFD_RELOC_ARM_IMMEDIATE: |
21269 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21270 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
21271 | return NULL; | |
a737bd4d | 21272 | |
c19d1205 ZW |
21273 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
21274 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21275 | _("ADRL used for a symbol not defined in the same file")); | |
21276 | return NULL; | |
a737bd4d | 21277 | |
c19d1205 | 21278 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
21279 | if (section->use_rela_p) |
21280 | { | |
21281 | code = fixp->fx_r_type; | |
21282 | break; | |
21283 | } | |
21284 | ||
c19d1205 ZW |
21285 | if (fixp->fx_addsy != NULL |
21286 | && !S_IS_DEFINED (fixp->fx_addsy) | |
21287 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 21288 | { |
c19d1205 ZW |
21289 | as_bad_where (fixp->fx_file, fixp->fx_line, |
21290 | _("undefined local label `%s'"), | |
21291 | S_GET_NAME (fixp->fx_addsy)); | |
21292 | return NULL; | |
a737bd4d NC |
21293 | } |
21294 | ||
c19d1205 ZW |
21295 | as_bad_where (fixp->fx_file, fixp->fx_line, |
21296 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
21297 | return NULL; | |
a737bd4d | 21298 | |
c19d1205 ZW |
21299 | default: |
21300 | { | |
21301 | char * type; | |
6c43fab6 | 21302 | |
c19d1205 ZW |
21303 | switch (fixp->fx_r_type) |
21304 | { | |
21305 | case BFD_RELOC_NONE: type = "NONE"; break; | |
21306 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
21307 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 21308 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
21309 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
21310 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
21311 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
db187cb9 | 21312 | case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break; |
8f06b2d8 | 21313 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
21314 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
21315 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
21316 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
21317 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
21318 | default: type = _("<unknown>"); break; | |
21319 | } | |
21320 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21321 | _("cannot represent %s relocation in this object file format"), | |
21322 | type); | |
21323 | return NULL; | |
21324 | } | |
a737bd4d | 21325 | } |
6c43fab6 | 21326 | |
c19d1205 ZW |
21327 | #ifdef OBJ_ELF |
21328 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
21329 | && GOT_symbol | |
21330 | && fixp->fx_addsy == GOT_symbol) | |
21331 | { | |
21332 | code = BFD_RELOC_ARM_GOTPC; | |
21333 | reloc->addend = fixp->fx_offset = reloc->address; | |
21334 | } | |
21335 | #endif | |
6c43fab6 | 21336 | |
c19d1205 | 21337 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 21338 | |
c19d1205 ZW |
21339 | if (reloc->howto == NULL) |
21340 | { | |
21341 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21342 | _("cannot represent %s relocation in this object file format"), | |
21343 | bfd_get_reloc_code_name (code)); | |
21344 | return NULL; | |
21345 | } | |
6c43fab6 | 21346 | |
c19d1205 ZW |
21347 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
21348 | vtable entry to be used in the relocation's section offset. */ | |
21349 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
21350 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 21351 | |
c19d1205 | 21352 | return reloc; |
6c43fab6 RE |
21353 | } |
21354 | ||
c19d1205 | 21355 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 21356 | |
c19d1205 ZW |
21357 | void |
21358 | cons_fix_new_arm (fragS * frag, | |
21359 | int where, | |
21360 | int size, | |
21361 | expressionS * exp) | |
6c43fab6 | 21362 | { |
c19d1205 ZW |
21363 | bfd_reloc_code_real_type type; |
21364 | int pcrel = 0; | |
6c43fab6 | 21365 | |
c19d1205 ZW |
21366 | /* Pick a reloc. |
21367 | FIXME: @@ Should look at CPU word size. */ | |
21368 | switch (size) | |
21369 | { | |
21370 | case 1: | |
21371 | type = BFD_RELOC_8; | |
21372 | break; | |
21373 | case 2: | |
21374 | type = BFD_RELOC_16; | |
21375 | break; | |
21376 | case 4: | |
21377 | default: | |
21378 | type = BFD_RELOC_32; | |
21379 | break; | |
21380 | case 8: | |
21381 | type = BFD_RELOC_64; | |
21382 | break; | |
21383 | } | |
6c43fab6 | 21384 | |
f0927246 NC |
21385 | #ifdef TE_PE |
21386 | if (exp->X_op == O_secrel) | |
21387 | { | |
21388 | exp->X_op = O_symbol; | |
21389 | type = BFD_RELOC_32_SECREL; | |
21390 | } | |
21391 | #endif | |
21392 | ||
c19d1205 ZW |
21393 | fix_new_exp (frag, where, (int) size, exp, pcrel, type); |
21394 | } | |
6c43fab6 | 21395 | |
4343666d | 21396 | #if defined (OBJ_COFF) |
c19d1205 ZW |
21397 | void |
21398 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 21399 | { |
c19d1205 ZW |
21400 | /* If the destination of the branch is a defined symbol which does not have |
21401 | the THUMB_FUNC attribute, then we must be calling a function which has | |
21402 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
21403 | function and change the branch to refer to that function instead. */ | |
21404 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
21405 | && fixP->fx_addsy != NULL | |
21406 | && S_IS_DEFINED (fixP->fx_addsy) | |
21407 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 21408 | { |
c19d1205 | 21409 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 21410 | } |
c19d1205 ZW |
21411 | } |
21412 | #endif | |
6c43fab6 | 21413 | |
267bf995 | 21414 | |
c19d1205 ZW |
21415 | int |
21416 | arm_force_relocation (struct fix * fixp) | |
21417 | { | |
21418 | #if defined (OBJ_COFF) && defined (TE_PE) | |
21419 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
21420 | return 1; | |
21421 | #endif | |
6c43fab6 | 21422 | |
267bf995 RR |
21423 | /* In case we have a call or a branch to a function in ARM ISA mode from |
21424 | a thumb function or vice-versa force the relocation. These relocations | |
21425 | are cleared off for some cores that might have blx and simple transformations | |
21426 | are possible. */ | |
21427 | ||
21428 | #ifdef OBJ_ELF | |
21429 | switch (fixp->fx_r_type) | |
21430 | { | |
21431 | case BFD_RELOC_ARM_PCREL_JUMP: | |
21432 | case BFD_RELOC_ARM_PCREL_CALL: | |
21433 | case BFD_RELOC_THUMB_PCREL_BLX: | |
21434 | if (THUMB_IS_FUNC (fixp->fx_addsy)) | |
21435 | return 1; | |
21436 | break; | |
21437 | ||
21438 | case BFD_RELOC_ARM_PCREL_BLX: | |
21439 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
21440 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
21441 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
21442 | if (ARM_IS_FUNC (fixp->fx_addsy)) | |
21443 | return 1; | |
21444 | break; | |
21445 | ||
21446 | default: | |
21447 | break; | |
21448 | } | |
21449 | #endif | |
21450 | ||
c19d1205 ZW |
21451 | /* Resolve these relocations even if the symbol is extern or weak. */ |
21452 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE | |
21453 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
0110f2b8 | 21454 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
16805f35 | 21455 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM |
0110f2b8 PB |
21456 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
21457 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
21458 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12) | |
c19d1205 | 21459 | return 0; |
a737bd4d | 21460 | |
4962c51a MS |
21461 | /* Always leave these relocations for the linker. */ |
21462 | if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
21463 | && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
21464 | || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
21465 | return 1; | |
21466 | ||
f0291e4c PB |
21467 | /* Always generate relocations against function symbols. */ |
21468 | if (fixp->fx_r_type == BFD_RELOC_32 | |
21469 | && fixp->fx_addsy | |
21470 | && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) | |
21471 | return 1; | |
21472 | ||
c19d1205 | 21473 | return generic_force_reloc (fixp); |
404ff6b5 AH |
21474 | } |
21475 | ||
0ffdc86c | 21476 | #if defined (OBJ_ELF) || defined (OBJ_COFF) |
e28387c3 PB |
21477 | /* Relocations against function names must be left unadjusted, |
21478 | so that the linker can use this information to generate interworking | |
21479 | stubs. The MIPS version of this function | |
c19d1205 ZW |
21480 | also prevents relocations that are mips-16 specific, but I do not |
21481 | know why it does this. | |
404ff6b5 | 21482 | |
c19d1205 ZW |
21483 | FIXME: |
21484 | There is one other problem that ought to be addressed here, but | |
21485 | which currently is not: Taking the address of a label (rather | |
21486 | than a function) and then later jumping to that address. Such | |
21487 | addresses also ought to have their bottom bit set (assuming that | |
21488 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 21489 | |
c19d1205 ZW |
21490 | bfd_boolean |
21491 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 21492 | { |
c19d1205 ZW |
21493 | if (fixP->fx_addsy == NULL) |
21494 | return 1; | |
404ff6b5 | 21495 | |
e28387c3 PB |
21496 | /* Preserve relocations against symbols with function type. */ |
21497 | if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) | |
c921be7d | 21498 | return FALSE; |
e28387c3 | 21499 | |
c19d1205 ZW |
21500 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
21501 | && fixP->fx_subsy == NULL) | |
c921be7d | 21502 | return FALSE; |
a737bd4d | 21503 | |
c19d1205 ZW |
21504 | /* We need the symbol name for the VTABLE entries. */ |
21505 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
21506 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
c921be7d | 21507 | return FALSE; |
404ff6b5 | 21508 | |
c19d1205 ZW |
21509 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
21510 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
21511 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
21512 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
21513 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
21514 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 | |
21515 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
21516 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 | |
21517 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 | |
21518 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) | |
c921be7d | 21519 | return FALSE; |
a737bd4d | 21520 | |
4962c51a MS |
21521 | /* Similarly for group relocations. */ |
21522 | if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
21523 | && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
21524 | || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
c921be7d | 21525 | return FALSE; |
4962c51a | 21526 | |
79947c54 CD |
21527 | /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */ |
21528 | if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW | |
21529 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
21530 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL | |
21531 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL | |
21532 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
21533 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT | |
21534 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL | |
21535 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL) | |
c921be7d | 21536 | return FALSE; |
79947c54 | 21537 | |
c921be7d | 21538 | return TRUE; |
a737bd4d | 21539 | } |
0ffdc86c NC |
21540 | #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ |
21541 | ||
21542 | #ifdef OBJ_ELF | |
404ff6b5 | 21543 | |
c19d1205 ZW |
21544 | const char * |
21545 | elf32_arm_target_format (void) | |
404ff6b5 | 21546 | { |
c19d1205 ZW |
21547 | #ifdef TE_SYMBIAN |
21548 | return (target_big_endian | |
21549 | ? "elf32-bigarm-symbian" | |
21550 | : "elf32-littlearm-symbian"); | |
21551 | #elif defined (TE_VXWORKS) | |
21552 | return (target_big_endian | |
21553 | ? "elf32-bigarm-vxworks" | |
21554 | : "elf32-littlearm-vxworks"); | |
21555 | #else | |
21556 | if (target_big_endian) | |
21557 | return "elf32-bigarm"; | |
21558 | else | |
21559 | return "elf32-littlearm"; | |
21560 | #endif | |
404ff6b5 AH |
21561 | } |
21562 | ||
c19d1205 ZW |
21563 | void |
21564 | armelf_frob_symbol (symbolS * symp, | |
21565 | int * puntp) | |
404ff6b5 | 21566 | { |
c19d1205 ZW |
21567 | elf_frob_symbol (symp, puntp); |
21568 | } | |
21569 | #endif | |
404ff6b5 | 21570 | |
c19d1205 | 21571 | /* MD interface: Finalization. */ |
a737bd4d | 21572 | |
c19d1205 ZW |
21573 | void |
21574 | arm_cleanup (void) | |
21575 | { | |
21576 | literal_pool * pool; | |
a737bd4d | 21577 | |
e07e6e58 NC |
21578 | /* Ensure that all the IT blocks are properly closed. */ |
21579 | check_it_blocks_finished (); | |
21580 | ||
c19d1205 ZW |
21581 | for (pool = list_of_pools; pool; pool = pool->next) |
21582 | { | |
5f4273c7 | 21583 | /* Put it at the end of the relevant section. */ |
c19d1205 ZW |
21584 | subseg_set (pool->section, pool->sub_section); |
21585 | #ifdef OBJ_ELF | |
21586 | arm_elf_change_section (); | |
21587 | #endif | |
21588 | s_ltorg (0); | |
21589 | } | |
404ff6b5 AH |
21590 | } |
21591 | ||
cd000bff DJ |
21592 | #ifdef OBJ_ELF |
21593 | /* Remove any excess mapping symbols generated for alignment frags in | |
21594 | SEC. We may have created a mapping symbol before a zero byte | |
21595 | alignment; remove it if there's a mapping symbol after the | |
21596 | alignment. */ | |
21597 | static void | |
21598 | check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, | |
21599 | void *dummy ATTRIBUTE_UNUSED) | |
21600 | { | |
21601 | segment_info_type *seginfo = seg_info (sec); | |
21602 | fragS *fragp; | |
21603 | ||
21604 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
21605 | return; | |
21606 | ||
21607 | for (fragp = seginfo->frchainP->frch_root; | |
21608 | fragp != NULL; | |
21609 | fragp = fragp->fr_next) | |
21610 | { | |
21611 | symbolS *sym = fragp->tc_frag_data.last_map; | |
21612 | fragS *next = fragp->fr_next; | |
21613 | ||
21614 | /* Variable-sized frags have been converted to fixed size by | |
21615 | this point. But if this was variable-sized to start with, | |
21616 | there will be a fixed-size frag after it. So don't handle | |
21617 | next == NULL. */ | |
21618 | if (sym == NULL || next == NULL) | |
21619 | continue; | |
21620 | ||
21621 | if (S_GET_VALUE (sym) < next->fr_address) | |
21622 | /* Not at the end of this frag. */ | |
21623 | continue; | |
21624 | know (S_GET_VALUE (sym) == next->fr_address); | |
21625 | ||
21626 | do | |
21627 | { | |
21628 | if (next->tc_frag_data.first_map != NULL) | |
21629 | { | |
21630 | /* Next frag starts with a mapping symbol. Discard this | |
21631 | one. */ | |
21632 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
21633 | break; | |
21634 | } | |
21635 | ||
21636 | if (next->fr_next == NULL) | |
21637 | { | |
21638 | /* This mapping symbol is at the end of the section. Discard | |
21639 | it. */ | |
21640 | know (next->fr_fix == 0 && next->fr_var == 0); | |
21641 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
21642 | break; | |
21643 | } | |
21644 | ||
21645 | /* As long as we have empty frags without any mapping symbols, | |
21646 | keep looking. */ | |
21647 | /* If the next frag is non-empty and does not start with a | |
21648 | mapping symbol, then this mapping symbol is required. */ | |
21649 | if (next->fr_address != next->fr_next->fr_address) | |
21650 | break; | |
21651 | ||
21652 | next = next->fr_next; | |
21653 | } | |
21654 | while (next != NULL); | |
21655 | } | |
21656 | } | |
21657 | #endif | |
21658 | ||
c19d1205 ZW |
21659 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
21660 | ARM ones. */ | |
404ff6b5 | 21661 | |
c19d1205 ZW |
21662 | void |
21663 | arm_adjust_symtab (void) | |
404ff6b5 | 21664 | { |
c19d1205 ZW |
21665 | #ifdef OBJ_COFF |
21666 | symbolS * sym; | |
404ff6b5 | 21667 | |
c19d1205 ZW |
21668 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
21669 | { | |
21670 | if (ARM_IS_THUMB (sym)) | |
21671 | { | |
21672 | if (THUMB_IS_FUNC (sym)) | |
21673 | { | |
21674 | /* Mark the symbol as a Thumb function. */ | |
21675 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
21676 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
21677 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 21678 | |
c19d1205 ZW |
21679 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
21680 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
21681 | else | |
21682 | as_bad (_("%s: unexpected function type: %d"), | |
21683 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
21684 | } | |
21685 | else switch (S_GET_STORAGE_CLASS (sym)) | |
21686 | { | |
21687 | case C_EXT: | |
21688 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
21689 | break; | |
21690 | case C_STAT: | |
21691 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
21692 | break; | |
21693 | case C_LABEL: | |
21694 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
21695 | break; | |
21696 | default: | |
21697 | /* Do nothing. */ | |
21698 | break; | |
21699 | } | |
21700 | } | |
a737bd4d | 21701 | |
c19d1205 ZW |
21702 | if (ARM_IS_INTERWORK (sym)) |
21703 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 21704 | } |
c19d1205 ZW |
21705 | #endif |
21706 | #ifdef OBJ_ELF | |
21707 | symbolS * sym; | |
21708 | char bind; | |
404ff6b5 | 21709 | |
c19d1205 | 21710 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 21711 | { |
c19d1205 ZW |
21712 | if (ARM_IS_THUMB (sym)) |
21713 | { | |
21714 | elf_symbol_type * elf_sym; | |
404ff6b5 | 21715 | |
c19d1205 ZW |
21716 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
21717 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 21718 | |
b0796911 PB |
21719 | if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, |
21720 | BFD_ARM_SPECIAL_SYM_TYPE_ANY)) | |
c19d1205 ZW |
21721 | { |
21722 | /* If it's a .thumb_func, declare it as so, | |
21723 | otherwise tag label as .code 16. */ | |
21724 | if (THUMB_IS_FUNC (sym)) | |
21725 | elf_sym->internal_elf_sym.st_info = | |
21726 | ELF_ST_INFO (bind, STT_ARM_TFUNC); | |
3ba67470 | 21727 | else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
c19d1205 ZW |
21728 | elf_sym->internal_elf_sym.st_info = |
21729 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
21730 | } | |
21731 | } | |
21732 | } | |
cd000bff DJ |
21733 | |
21734 | /* Remove any overlapping mapping symbols generated by alignment frags. */ | |
21735 | bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); | |
c19d1205 | 21736 | #endif |
404ff6b5 AH |
21737 | } |
21738 | ||
c19d1205 | 21739 | /* MD interface: Initialization. */ |
404ff6b5 | 21740 | |
a737bd4d | 21741 | static void |
c19d1205 | 21742 | set_constant_flonums (void) |
a737bd4d | 21743 | { |
c19d1205 | 21744 | int i; |
404ff6b5 | 21745 | |
c19d1205 ZW |
21746 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
21747 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
21748 | abort (); | |
a737bd4d | 21749 | } |
404ff6b5 | 21750 | |
3e9e4fcf JB |
21751 | /* Auto-select Thumb mode if it's the only available instruction set for the |
21752 | given architecture. */ | |
21753 | ||
21754 | static void | |
21755 | autoselect_thumb_from_cpu_variant (void) | |
21756 | { | |
21757 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) | |
21758 | opcode_select (16); | |
21759 | } | |
21760 | ||
c19d1205 ZW |
21761 | void |
21762 | md_begin (void) | |
a737bd4d | 21763 | { |
c19d1205 ZW |
21764 | unsigned mach; |
21765 | unsigned int i; | |
404ff6b5 | 21766 | |
c19d1205 ZW |
21767 | if ( (arm_ops_hsh = hash_new ()) == NULL |
21768 | || (arm_cond_hsh = hash_new ()) == NULL | |
21769 | || (arm_shift_hsh = hash_new ()) == NULL | |
21770 | || (arm_psr_hsh = hash_new ()) == NULL | |
62b3e311 | 21771 | || (arm_v7m_psr_hsh = hash_new ()) == NULL |
c19d1205 | 21772 | || (arm_reg_hsh = hash_new ()) == NULL |
62b3e311 PB |
21773 | || (arm_reloc_hsh = hash_new ()) == NULL |
21774 | || (arm_barrier_opt_hsh = hash_new ()) == NULL) | |
c19d1205 ZW |
21775 | as_fatal (_("virtual memory exhausted")); |
21776 | ||
21777 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
d3ce72d0 | 21778 | hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i)); |
c19d1205 | 21779 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) |
d3ce72d0 | 21780 | hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i)); |
c19d1205 | 21781 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) |
5a49b8ac | 21782 | hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i)); |
c19d1205 | 21783 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 21784 | hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i)); |
62b3e311 | 21785 | for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 NC |
21786 | hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name, |
21787 | (void *) (v7m_psrs + i)); | |
c19d1205 | 21788 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) |
5a49b8ac | 21789 | hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); |
62b3e311 PB |
21790 | for (i = 0; |
21791 | i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); | |
21792 | i++) | |
d3ce72d0 | 21793 | hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name, |
5a49b8ac | 21794 | (void *) (barrier_opt_names + i)); |
c19d1205 ZW |
21795 | #ifdef OBJ_ELF |
21796 | for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++) | |
5a49b8ac | 21797 | hash_insert (arm_reloc_hsh, reloc_names[i].name, (void *) (reloc_names + i)); |
c19d1205 ZW |
21798 | #endif |
21799 | ||
21800 | set_constant_flonums (); | |
404ff6b5 | 21801 | |
c19d1205 ZW |
21802 | /* Set the cpu variant based on the command-line options. We prefer |
21803 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
21804 | -mfpu= over any other way of setting the floating point unit. | |
21805 | Use of legacy options with new options are faulted. */ | |
e74cfd16 | 21806 | if (legacy_cpu) |
404ff6b5 | 21807 | { |
e74cfd16 | 21808 | if (mcpu_cpu_opt || march_cpu_opt) |
c19d1205 ZW |
21809 | as_bad (_("use of old and new-style options to set CPU type")); |
21810 | ||
21811 | mcpu_cpu_opt = legacy_cpu; | |
404ff6b5 | 21812 | } |
e74cfd16 | 21813 | else if (!mcpu_cpu_opt) |
c19d1205 | 21814 | mcpu_cpu_opt = march_cpu_opt; |
404ff6b5 | 21815 | |
e74cfd16 | 21816 | if (legacy_fpu) |
c19d1205 | 21817 | { |
e74cfd16 | 21818 | if (mfpu_opt) |
c19d1205 | 21819 | as_bad (_("use of old and new-style options to set FPU type")); |
03b1477f RE |
21820 | |
21821 | mfpu_opt = legacy_fpu; | |
21822 | } | |
e74cfd16 | 21823 | else if (!mfpu_opt) |
03b1477f | 21824 | { |
45eb4c1b NS |
21825 | #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \ |
21826 | || defined (TE_NetBSD) || defined (TE_VXWORKS)) | |
39c2da32 RE |
21827 | /* Some environments specify a default FPU. If they don't, infer it |
21828 | from the processor. */ | |
e74cfd16 | 21829 | if (mcpu_fpu_opt) |
03b1477f RE |
21830 | mfpu_opt = mcpu_fpu_opt; |
21831 | else | |
21832 | mfpu_opt = march_fpu_opt; | |
39c2da32 | 21833 | #else |
e74cfd16 | 21834 | mfpu_opt = &fpu_default; |
39c2da32 | 21835 | #endif |
03b1477f RE |
21836 | } |
21837 | ||
e74cfd16 | 21838 | if (!mfpu_opt) |
03b1477f | 21839 | { |
493cb6ef | 21840 | if (mcpu_cpu_opt != NULL) |
e74cfd16 | 21841 | mfpu_opt = &fpu_default; |
493cb6ef | 21842 | else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) |
e74cfd16 | 21843 | mfpu_opt = &fpu_arch_vfp_v2; |
03b1477f | 21844 | else |
e74cfd16 | 21845 | mfpu_opt = &fpu_arch_fpa; |
03b1477f RE |
21846 | } |
21847 | ||
ee065d83 | 21848 | #ifdef CPU_DEFAULT |
e74cfd16 | 21849 | if (!mcpu_cpu_opt) |
ee065d83 | 21850 | { |
e74cfd16 PB |
21851 | mcpu_cpu_opt = &cpu_default; |
21852 | selected_cpu = cpu_default; | |
ee065d83 | 21853 | } |
e74cfd16 PB |
21854 | #else |
21855 | if (mcpu_cpu_opt) | |
21856 | selected_cpu = *mcpu_cpu_opt; | |
ee065d83 | 21857 | else |
e74cfd16 | 21858 | mcpu_cpu_opt = &arm_arch_any; |
ee065d83 | 21859 | #endif |
03b1477f | 21860 | |
e74cfd16 | 21861 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
03b1477f | 21862 | |
3e9e4fcf JB |
21863 | autoselect_thumb_from_cpu_variant (); |
21864 | ||
e74cfd16 | 21865 | arm_arch_used = thumb_arch_used = arm_arch_none; |
ee065d83 | 21866 | |
f17c130b | 21867 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 21868 | { |
7cc69913 NC |
21869 | unsigned int flags = 0; |
21870 | ||
21871 | #if defined OBJ_ELF | |
21872 | flags = meabi_flags; | |
d507cf36 PB |
21873 | |
21874 | switch (meabi_flags) | |
33a392fb | 21875 | { |
d507cf36 | 21876 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 21877 | #endif |
d507cf36 PB |
21878 | /* Set the flags in the private structure. */ |
21879 | if (uses_apcs_26) flags |= F_APCS26; | |
21880 | if (support_interwork) flags |= F_INTERWORK; | |
21881 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 21882 | if (pic_code) flags |= F_PIC; |
e74cfd16 | 21883 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
7cc69913 NC |
21884 | flags |= F_SOFT_FLOAT; |
21885 | ||
d507cf36 PB |
21886 | switch (mfloat_abi_opt) |
21887 | { | |
21888 | case ARM_FLOAT_ABI_SOFT: | |
21889 | case ARM_FLOAT_ABI_SOFTFP: | |
21890 | flags |= F_SOFT_FLOAT; | |
21891 | break; | |
33a392fb | 21892 | |
d507cf36 PB |
21893 | case ARM_FLOAT_ABI_HARD: |
21894 | if (flags & F_SOFT_FLOAT) | |
21895 | as_bad (_("hard-float conflicts with specified fpu")); | |
21896 | break; | |
21897 | } | |
03b1477f | 21898 | |
e74cfd16 PB |
21899 | /* Using pure-endian doubles (even if soft-float). */ |
21900 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
7cc69913 | 21901 | flags |= F_VFP_FLOAT; |
f17c130b | 21902 | |
fde78edd | 21903 | #if defined OBJ_ELF |
e74cfd16 | 21904 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
d507cf36 | 21905 | flags |= EF_ARM_MAVERICK_FLOAT; |
d507cf36 PB |
21906 | break; |
21907 | ||
8cb51566 | 21908 | case EF_ARM_EABI_VER4: |
3a4a14e9 | 21909 | case EF_ARM_EABI_VER5: |
c19d1205 | 21910 | /* No additional flags to set. */ |
d507cf36 PB |
21911 | break; |
21912 | ||
21913 | default: | |
21914 | abort (); | |
21915 | } | |
7cc69913 | 21916 | #endif |
b99bd4ef NC |
21917 | bfd_set_private_flags (stdoutput, flags); |
21918 | ||
21919 | /* We have run out flags in the COFF header to encode the | |
21920 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 21921 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
21922 | if (atpcs) |
21923 | { | |
21924 | asection * sec; | |
21925 | ||
21926 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
21927 | ||
21928 | if (sec != NULL) | |
21929 | { | |
21930 | bfd_set_section_flags | |
21931 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
21932 | bfd_set_section_size (stdoutput, sec, 0); | |
21933 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
21934 | } | |
21935 | } | |
7cc69913 | 21936 | } |
f17c130b | 21937 | #endif |
b99bd4ef NC |
21938 | |
21939 | /* Record the CPU type as well. */ | |
2d447fca JM |
21940 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) |
21941 | mach = bfd_mach_arm_iWMMXt2; | |
21942 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) | |
e16bb312 | 21943 | mach = bfd_mach_arm_iWMMXt; |
e74cfd16 | 21944 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
b99bd4ef | 21945 | mach = bfd_mach_arm_XScale; |
e74cfd16 | 21946 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
fde78edd | 21947 | mach = bfd_mach_arm_ep9312; |
e74cfd16 | 21948 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
b99bd4ef | 21949 | mach = bfd_mach_arm_5TE; |
e74cfd16 | 21950 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
b99bd4ef | 21951 | { |
e74cfd16 | 21952 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
21953 | mach = bfd_mach_arm_5T; |
21954 | else | |
21955 | mach = bfd_mach_arm_5; | |
21956 | } | |
e74cfd16 | 21957 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
b99bd4ef | 21958 | { |
e74cfd16 | 21959 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
21960 | mach = bfd_mach_arm_4T; |
21961 | else | |
21962 | mach = bfd_mach_arm_4; | |
21963 | } | |
e74cfd16 | 21964 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
b99bd4ef | 21965 | mach = bfd_mach_arm_3M; |
e74cfd16 PB |
21966 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
21967 | mach = bfd_mach_arm_3; | |
21968 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) | |
21969 | mach = bfd_mach_arm_2a; | |
21970 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) | |
21971 | mach = bfd_mach_arm_2; | |
21972 | else | |
21973 | mach = bfd_mach_arm_unknown; | |
b99bd4ef NC |
21974 | |
21975 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
21976 | } | |
21977 | ||
c19d1205 | 21978 | /* Command line processing. */ |
b99bd4ef | 21979 | |
c19d1205 ZW |
21980 | /* md_parse_option |
21981 | Invocation line includes a switch not recognized by the base assembler. | |
21982 | See if it's a processor-specific option. | |
b99bd4ef | 21983 | |
c19d1205 ZW |
21984 | This routine is somewhat complicated by the need for backwards |
21985 | compatibility (since older releases of gcc can't be changed). | |
21986 | The new options try to make the interface as compatible as | |
21987 | possible with GCC. | |
b99bd4ef | 21988 | |
c19d1205 | 21989 | New options (supported) are: |
b99bd4ef | 21990 | |
c19d1205 ZW |
21991 | -mcpu=<cpu name> Assemble for selected processor |
21992 | -march=<architecture name> Assemble for selected architecture | |
21993 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
21994 | -EB/-mbig-endian Big-endian | |
21995 | -EL/-mlittle-endian Little-endian | |
21996 | -k Generate PIC code | |
21997 | -mthumb Start in Thumb mode | |
21998 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 21999 | |
278df34e | 22000 | -m[no-]warn-deprecated Warn about deprecated features |
267bf995 | 22001 | |
c19d1205 | 22002 | For now we will also provide support for: |
b99bd4ef | 22003 | |
c19d1205 ZW |
22004 | -mapcs-32 32-bit Program counter |
22005 | -mapcs-26 26-bit Program counter | |
22006 | -macps-float Floats passed in FP registers | |
22007 | -mapcs-reentrant Reentrant code | |
22008 | -matpcs | |
22009 | (sometime these will probably be replaced with -mapcs=<list of options> | |
22010 | and -matpcs=<list of options>) | |
b99bd4ef | 22011 | |
c19d1205 ZW |
22012 | The remaining options are only supported for back-wards compatibility. |
22013 | Cpu variants, the arm part is optional: | |
22014 | -m[arm]1 Currently not supported. | |
22015 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
22016 | -m[arm]3 Arm 3 processor | |
22017 | -m[arm]6[xx], Arm 6 processors | |
22018 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
22019 | -m[arm]8[10] Arm 8 processors | |
22020 | -m[arm]9[20][tdmi] Arm 9 processors | |
22021 | -mstrongarm[110[0]] StrongARM processors | |
22022 | -mxscale XScale processors | |
22023 | -m[arm]v[2345[t[e]]] Arm architectures | |
22024 | -mall All (except the ARM1) | |
22025 | FP variants: | |
22026 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
22027 | -mfpe-old (No float load/store multiples) | |
22028 | -mvfpxd VFP Single precision | |
22029 | -mvfp All VFP | |
22030 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 22031 | |
c19d1205 ZW |
22032 | The following CPU names are recognized: |
22033 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
22034 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
22035 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
22036 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
22037 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
22038 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
22039 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 22040 | |
c19d1205 | 22041 | */ |
b99bd4ef | 22042 | |
c19d1205 | 22043 | const char * md_shortopts = "m:k"; |
b99bd4ef | 22044 | |
c19d1205 ZW |
22045 | #ifdef ARM_BI_ENDIAN |
22046 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
22047 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 22048 | #else |
c19d1205 ZW |
22049 | #if TARGET_BYTES_BIG_ENDIAN |
22050 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 22051 | #else |
c19d1205 ZW |
22052 | #define OPTION_EL (OPTION_MD_BASE + 1) |
22053 | #endif | |
b99bd4ef | 22054 | #endif |
845b51d6 | 22055 | #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2) |
b99bd4ef | 22056 | |
c19d1205 | 22057 | struct option md_longopts[] = |
b99bd4ef | 22058 | { |
c19d1205 ZW |
22059 | #ifdef OPTION_EB |
22060 | {"EB", no_argument, NULL, OPTION_EB}, | |
22061 | #endif | |
22062 | #ifdef OPTION_EL | |
22063 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 22064 | #endif |
845b51d6 | 22065 | {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, |
c19d1205 ZW |
22066 | {NULL, no_argument, NULL, 0} |
22067 | }; | |
b99bd4ef | 22068 | |
c19d1205 | 22069 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 22070 | |
c19d1205 | 22071 | struct arm_option_table |
b99bd4ef | 22072 | { |
c19d1205 ZW |
22073 | char *option; /* Option name to match. */ |
22074 | char *help; /* Help information. */ | |
22075 | int *var; /* Variable to change. */ | |
22076 | int value; /* What to change it to. */ | |
22077 | char *deprecated; /* If non-null, print this message. */ | |
22078 | }; | |
b99bd4ef | 22079 | |
c19d1205 ZW |
22080 | struct arm_option_table arm_opts[] = |
22081 | { | |
22082 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
22083 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
22084 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
22085 | &support_interwork, 1, NULL}, | |
22086 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
22087 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
22088 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
22089 | 1, NULL}, | |
22090 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
22091 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
22092 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
22093 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
22094 | NULL}, | |
b99bd4ef | 22095 | |
c19d1205 ZW |
22096 | /* These are recognized by the assembler, but have no affect on code. */ |
22097 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
22098 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
278df34e NS |
22099 | |
22100 | {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL}, | |
22101 | {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"), | |
22102 | &warn_on_deprecated, 0, NULL}, | |
e74cfd16 PB |
22103 | {NULL, NULL, NULL, 0, NULL} |
22104 | }; | |
22105 | ||
22106 | struct arm_legacy_option_table | |
22107 | { | |
22108 | char *option; /* Option name to match. */ | |
22109 | const arm_feature_set **var; /* Variable to change. */ | |
22110 | const arm_feature_set value; /* What to change it to. */ | |
22111 | char *deprecated; /* If non-null, print this message. */ | |
22112 | }; | |
b99bd4ef | 22113 | |
e74cfd16 PB |
22114 | const struct arm_legacy_option_table arm_legacy_opts[] = |
22115 | { | |
c19d1205 ZW |
22116 | /* DON'T add any new processors to this list -- we want the whole list |
22117 | to go away... Add them to the processors table instead. */ | |
e74cfd16 PB |
22118 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
22119 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
22120 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
22121 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
22122 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
22123 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
22124 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
22125 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
22126 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
22127 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
22128 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
22129 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
22130 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
22131 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
22132 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
22133 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
22134 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
22135 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
22136 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
22137 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
22138 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
22139 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
22140 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
22141 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
22142 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
22143 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
22144 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
22145 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
22146 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
22147 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
22148 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
22149 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
22150 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
22151 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
22152 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
22153 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
22154 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
22155 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
22156 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
22157 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
22158 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
22159 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
22160 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
22161 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
22162 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
22163 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
22164 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22165 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22166 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22167 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22168 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
22169 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
22170 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
22171 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
22172 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
22173 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
22174 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
22175 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
22176 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
22177 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
22178 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
22179 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
22180 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
22181 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
22182 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
22183 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
22184 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
22185 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
22186 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
22187 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, | |
c19d1205 | 22188 | N_("use -mcpu=strongarm110")}, |
e74cfd16 | 22189 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 22190 | N_("use -mcpu=strongarm1100")}, |
e74cfd16 | 22191 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 22192 | N_("use -mcpu=strongarm1110")}, |
e74cfd16 PB |
22193 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
22194 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
22195 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 22196 | |
c19d1205 | 22197 | /* Architecture variants -- don't add any more to this list either. */ |
e74cfd16 PB |
22198 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
22199 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
22200 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
22201 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
22202 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
22203 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
22204 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
22205 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
22206 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
22207 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
22208 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
22209 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
22210 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
22211 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
22212 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
22213 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
22214 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
22215 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 22216 | |
c19d1205 | 22217 | /* Floating point variants -- don't add any more to this list either. */ |
e74cfd16 PB |
22218 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
22219 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
22220 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
22221 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, | |
c19d1205 | 22222 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
7ed4c4c5 | 22223 | |
e74cfd16 | 22224 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
c19d1205 | 22225 | }; |
7ed4c4c5 | 22226 | |
c19d1205 | 22227 | struct arm_cpu_option_table |
7ed4c4c5 | 22228 | { |
c19d1205 | 22229 | char *name; |
e74cfd16 | 22230 | const arm_feature_set value; |
c19d1205 ZW |
22231 | /* For some CPUs we assume an FPU unless the user explicitly sets |
22232 | -mfpu=... */ | |
e74cfd16 | 22233 | const arm_feature_set default_fpu; |
ee065d83 PB |
22234 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
22235 | case. */ | |
22236 | const char *canonical_name; | |
c19d1205 | 22237 | }; |
7ed4c4c5 | 22238 | |
c19d1205 ZW |
22239 | /* This list should, at a minimum, contain all the cpu names |
22240 | recognized by GCC. */ | |
e74cfd16 | 22241 | static const struct arm_cpu_option_table arm_cpus[] = |
c19d1205 | 22242 | { |
ee065d83 PB |
22243 | {"all", ARM_ANY, FPU_ARCH_FPA, NULL}, |
22244 | {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL}, | |
22245 | {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL}, | |
22246 | {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, | |
22247 | {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, | |
22248 | {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22249 | {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22250 | {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22251 | {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22252 | {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22253 | {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22254 | {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
22255 | {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22256 | {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
22257 | {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22258 | {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
22259 | {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22260 | {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22261 | {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22262 | {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22263 | {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22264 | {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22265 | {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22266 | {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22267 | {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22268 | {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22269 | {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22270 | {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22271 | {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22272 | {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22273 | {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22274 | {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22275 | {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22276 | {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22277 | {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22278 | {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22279 | {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22280 | {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22281 | {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22282 | {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"}, | |
22283 | {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22284 | {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22285 | {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22286 | {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
7fac0536 NC |
22287 | {"fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, |
22288 | {"fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
c19d1205 ZW |
22289 | /* For V5 or later processors we default to using VFP; but the user |
22290 | should really set the FPU type explicitly. */ | |
ee065d83 PB |
22291 | {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, |
22292 | {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22293 | {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, | |
22294 | {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, | |
22295 | {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, | |
22296 | {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, | |
22297 | {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"}, | |
22298 | {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22299 | {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, | |
22300 | {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"}, | |
22301 | {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22302 | {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22303 | {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
22304 | {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
22305 | {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22306 | {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"}, | |
22307 | {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
22308 | {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22309 | {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22310 | {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"}, | |
22311 | {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, | |
7fac0536 NC |
22312 | {"fa626te", ARM_ARCH_V5TE, FPU_NONE, NULL}, |
22313 | {"fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
ee065d83 PB |
22314 | {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"}, |
22315 | {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL}, | |
22316 | {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"}, | |
22317 | {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL}, | |
22318 | {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL}, | |
22319 | {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL}, | |
22320 | {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL}, | |
22321 | {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL}, | |
22322 | {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL}, | |
22323 | {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL}, | |
b38f9f31 | 22324 | {"cortex-a5", ARM_ARCH_V7A, FPU_NONE, NULL}, |
e07e6e58 | 22325 | {"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE (0, FPU_VFP_V3 |
5287ad62 | 22326 | | FPU_NEON_EXT_V1), |
15290f0a | 22327 | NULL}, |
e07e6e58 | 22328 | {"cortex-a9", ARM_ARCH_V7A, ARM_FEATURE (0, FPU_VFP_V3 |
15290f0a | 22329 | | FPU_NEON_EXT_V1), |
5287ad62 | 22330 | NULL}, |
62b3e311 | 22331 | {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL}, |
307c948d | 22332 | {"cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16, NULL}, |
26b6f191 | 22333 | {"cortex-m4", ARM_ARCH_V7EM, FPU_NONE, NULL}, |
62b3e311 | 22334 | {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL}, |
7e806470 | 22335 | {"cortex-m1", ARM_ARCH_V6M, FPU_NONE, NULL}, |
5b19eaba | 22336 | {"cortex-m0", ARM_ARCH_V6M, FPU_NONE, NULL}, |
c19d1205 | 22337 | /* ??? XSCALE is really an architecture. */ |
ee065d83 | 22338 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, |
c19d1205 | 22339 | /* ??? iwmmxt is not a processor. */ |
ee065d83 | 22340 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL}, |
2d447fca | 22341 | {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL}, |
ee065d83 | 22342 | {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, |
c19d1205 | 22343 | /* Maverick */ |
e07e6e58 | 22344 | {"ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"}, |
e74cfd16 | 22345 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL} |
c19d1205 | 22346 | }; |
7ed4c4c5 | 22347 | |
c19d1205 | 22348 | struct arm_arch_option_table |
7ed4c4c5 | 22349 | { |
c19d1205 | 22350 | char *name; |
e74cfd16 PB |
22351 | const arm_feature_set value; |
22352 | const arm_feature_set default_fpu; | |
c19d1205 | 22353 | }; |
7ed4c4c5 | 22354 | |
c19d1205 ZW |
22355 | /* This list should, at a minimum, contain all the architecture names |
22356 | recognized by GCC. */ | |
e74cfd16 | 22357 | static const struct arm_arch_option_table arm_archs[] = |
c19d1205 ZW |
22358 | { |
22359 | {"all", ARM_ANY, FPU_ARCH_FPA}, | |
22360 | {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA}, | |
22361 | {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA}, | |
22362 | {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
22363 | {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
22364 | {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
22365 | {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA}, | |
22366 | {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
22367 | {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA}, | |
22368 | {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
22369 | {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA}, | |
22370 | {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP}, | |
22371 | {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP}, | |
22372 | {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP}, | |
22373 | {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP}, | |
22374 | {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP}, | |
22375 | {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP}, | |
22376 | {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
22377 | {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
22378 | {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP}, | |
22379 | {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP}, | |
22380 | {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP}, | |
22381 | {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP}, | |
22382 | {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP}, | |
22383 | {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP}, | |
22384 | {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP}, | |
7e806470 | 22385 | {"armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP}, |
62b3e311 | 22386 | {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP}, |
c450d570 PB |
22387 | /* The official spelling of the ARMv7 profile variants is the dashed form. |
22388 | Accept the non-dashed form for compatibility with old toolchains. */ | |
62b3e311 PB |
22389 | {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP}, |
22390 | {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP}, | |
22391 | {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP}, | |
c450d570 PB |
22392 | {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP}, |
22393 | {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP}, | |
22394 | {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP}, | |
9e3c6df6 | 22395 | {"armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP}, |
c19d1205 ZW |
22396 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP}, |
22397 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP}, | |
2d447fca | 22398 | {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP}, |
e74cfd16 | 22399 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} |
c19d1205 | 22400 | }; |
7ed4c4c5 | 22401 | |
c19d1205 | 22402 | /* ISA extensions in the co-processor space. */ |
e74cfd16 | 22403 | struct arm_option_cpu_value_table |
c19d1205 ZW |
22404 | { |
22405 | char *name; | |
e74cfd16 | 22406 | const arm_feature_set value; |
c19d1205 | 22407 | }; |
7ed4c4c5 | 22408 | |
e74cfd16 | 22409 | static const struct arm_option_cpu_value_table arm_extensions[] = |
c19d1205 | 22410 | { |
e74cfd16 PB |
22411 | {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)}, |
22412 | {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)}, | |
22413 | {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)}, | |
2d447fca | 22414 | {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2)}, |
e74cfd16 | 22415 | {NULL, ARM_ARCH_NONE} |
c19d1205 | 22416 | }; |
7ed4c4c5 | 22417 | |
c19d1205 ZW |
22418 | /* This list should, at a minimum, contain all the fpu names |
22419 | recognized by GCC. */ | |
e74cfd16 | 22420 | static const struct arm_option_cpu_value_table arm_fpus[] = |
c19d1205 ZW |
22421 | { |
22422 | {"softfpa", FPU_NONE}, | |
22423 | {"fpe", FPU_ARCH_FPE}, | |
22424 | {"fpe2", FPU_ARCH_FPE}, | |
22425 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
22426 | {"fpa", FPU_ARCH_FPA}, | |
22427 | {"fpa10", FPU_ARCH_FPA}, | |
22428 | {"fpa11", FPU_ARCH_FPA}, | |
22429 | {"arm7500fe", FPU_ARCH_FPA}, | |
22430 | {"softvfp", FPU_ARCH_VFP}, | |
22431 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
22432 | {"vfp", FPU_ARCH_VFP_V2}, | |
22433 | {"vfp9", FPU_ARCH_VFP_V2}, | |
b1cc4aeb | 22434 | {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */ |
c19d1205 ZW |
22435 | {"vfp10", FPU_ARCH_VFP_V2}, |
22436 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
22437 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
b1cc4aeb PB |
22438 | {"vfpv2", FPU_ARCH_VFP_V2}, |
22439 | {"vfpv3", FPU_ARCH_VFP_V3}, | |
62f3b8c8 | 22440 | {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16}, |
b1cc4aeb | 22441 | {"vfpv3-d16", FPU_ARCH_VFP_V3D16}, |
62f3b8c8 PB |
22442 | {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16}, |
22443 | {"vfpv3xd", FPU_ARCH_VFP_V3xD}, | |
22444 | {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16}, | |
c19d1205 ZW |
22445 | {"arm1020t", FPU_ARCH_VFP_V1}, |
22446 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
22447 | {"arm1136jfs", FPU_ARCH_VFP_V2}, | |
22448 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, | |
22449 | {"maverick", FPU_ARCH_MAVERICK}, | |
5287ad62 | 22450 | {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
8e79c3df | 22451 | {"neon-fp16", FPU_ARCH_NEON_FP16}, |
62f3b8c8 PB |
22452 | {"vfpv4", FPU_ARCH_VFP_V4}, |
22453 | {"vfpv4-d16", FPU_ARCH_VFP_V4D16}, | |
ada65aa3 | 22454 | {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16}, |
62f3b8c8 | 22455 | {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4}, |
e74cfd16 PB |
22456 | {NULL, ARM_ARCH_NONE} |
22457 | }; | |
22458 | ||
22459 | struct arm_option_value_table | |
22460 | { | |
22461 | char *name; | |
22462 | long value; | |
c19d1205 | 22463 | }; |
7ed4c4c5 | 22464 | |
e74cfd16 | 22465 | static const struct arm_option_value_table arm_float_abis[] = |
c19d1205 ZW |
22466 | { |
22467 | {"hard", ARM_FLOAT_ABI_HARD}, | |
22468 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
22469 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
e74cfd16 | 22470 | {NULL, 0} |
c19d1205 | 22471 | }; |
7ed4c4c5 | 22472 | |
c19d1205 | 22473 | #ifdef OBJ_ELF |
3a4a14e9 | 22474 | /* We only know how to output GNU and ver 4/5 (AAELF) formats. */ |
e74cfd16 | 22475 | static const struct arm_option_value_table arm_eabis[] = |
c19d1205 ZW |
22476 | { |
22477 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
22478 | {"4", EF_ARM_EABI_VER4}, | |
3a4a14e9 | 22479 | {"5", EF_ARM_EABI_VER5}, |
e74cfd16 | 22480 | {NULL, 0} |
c19d1205 ZW |
22481 | }; |
22482 | #endif | |
7ed4c4c5 | 22483 | |
c19d1205 ZW |
22484 | struct arm_long_option_table |
22485 | { | |
22486 | char * option; /* Substring to match. */ | |
22487 | char * help; /* Help information. */ | |
22488 | int (* func) (char * subopt); /* Function to decode sub-option. */ | |
22489 | char * deprecated; /* If non-null, print this message. */ | |
22490 | }; | |
7ed4c4c5 | 22491 | |
c921be7d | 22492 | static bfd_boolean |
e74cfd16 | 22493 | arm_parse_extension (char * str, const arm_feature_set **opt_p) |
7ed4c4c5 | 22494 | { |
21d799b5 NC |
22495 | arm_feature_set *ext_set = (arm_feature_set *) |
22496 | xmalloc (sizeof (arm_feature_set)); | |
e74cfd16 PB |
22497 | |
22498 | /* Copy the feature set, so that we can modify it. */ | |
22499 | *ext_set = **opt_p; | |
22500 | *opt_p = ext_set; | |
22501 | ||
c19d1205 | 22502 | while (str != NULL && *str != 0) |
7ed4c4c5 | 22503 | { |
e74cfd16 | 22504 | const struct arm_option_cpu_value_table * opt; |
c19d1205 ZW |
22505 | char * ext; |
22506 | int optlen; | |
7ed4c4c5 | 22507 | |
c19d1205 ZW |
22508 | if (*str != '+') |
22509 | { | |
22510 | as_bad (_("invalid architectural extension")); | |
c921be7d | 22511 | return FALSE; |
c19d1205 | 22512 | } |
7ed4c4c5 | 22513 | |
c19d1205 ZW |
22514 | str++; |
22515 | ext = strchr (str, '+'); | |
7ed4c4c5 | 22516 | |
c19d1205 ZW |
22517 | if (ext != NULL) |
22518 | optlen = ext - str; | |
22519 | else | |
22520 | optlen = strlen (str); | |
7ed4c4c5 | 22521 | |
c19d1205 ZW |
22522 | if (optlen == 0) |
22523 | { | |
22524 | as_bad (_("missing architectural extension")); | |
c921be7d | 22525 | return FALSE; |
c19d1205 | 22526 | } |
7ed4c4c5 | 22527 | |
c19d1205 ZW |
22528 | for (opt = arm_extensions; opt->name != NULL; opt++) |
22529 | if (strncmp (opt->name, str, optlen) == 0) | |
22530 | { | |
e74cfd16 | 22531 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); |
c19d1205 ZW |
22532 | break; |
22533 | } | |
7ed4c4c5 | 22534 | |
c19d1205 ZW |
22535 | if (opt->name == NULL) |
22536 | { | |
5f4273c7 | 22537 | as_bad (_("unknown architectural extension `%s'"), str); |
c921be7d | 22538 | return FALSE; |
c19d1205 | 22539 | } |
7ed4c4c5 | 22540 | |
c19d1205 ZW |
22541 | str = ext; |
22542 | }; | |
7ed4c4c5 | 22543 | |
c921be7d | 22544 | return TRUE; |
c19d1205 | 22545 | } |
7ed4c4c5 | 22546 | |
c921be7d | 22547 | static bfd_boolean |
c19d1205 | 22548 | arm_parse_cpu (char * str) |
7ed4c4c5 | 22549 | { |
e74cfd16 | 22550 | const struct arm_cpu_option_table * opt; |
c19d1205 ZW |
22551 | char * ext = strchr (str, '+'); |
22552 | int optlen; | |
7ed4c4c5 | 22553 | |
c19d1205 ZW |
22554 | if (ext != NULL) |
22555 | optlen = ext - str; | |
7ed4c4c5 | 22556 | else |
c19d1205 | 22557 | optlen = strlen (str); |
7ed4c4c5 | 22558 | |
c19d1205 | 22559 | if (optlen == 0) |
7ed4c4c5 | 22560 | { |
c19d1205 | 22561 | as_bad (_("missing cpu name `%s'"), str); |
c921be7d | 22562 | return FALSE; |
7ed4c4c5 NC |
22563 | } |
22564 | ||
c19d1205 ZW |
22565 | for (opt = arm_cpus; opt->name != NULL; opt++) |
22566 | if (strncmp (opt->name, str, optlen) == 0) | |
22567 | { | |
e74cfd16 PB |
22568 | mcpu_cpu_opt = &opt->value; |
22569 | mcpu_fpu_opt = &opt->default_fpu; | |
ee065d83 | 22570 | if (opt->canonical_name) |
5f4273c7 | 22571 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
22572 | else |
22573 | { | |
22574 | int i; | |
c921be7d | 22575 | |
ee065d83 PB |
22576 | for (i = 0; i < optlen; i++) |
22577 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
22578 | selected_cpu_name[i] = 0; | |
22579 | } | |
7ed4c4c5 | 22580 | |
c19d1205 ZW |
22581 | if (ext != NULL) |
22582 | return arm_parse_extension (ext, &mcpu_cpu_opt); | |
7ed4c4c5 | 22583 | |
c921be7d | 22584 | return TRUE; |
c19d1205 | 22585 | } |
7ed4c4c5 | 22586 | |
c19d1205 | 22587 | as_bad (_("unknown cpu `%s'"), str); |
c921be7d | 22588 | return FALSE; |
7ed4c4c5 NC |
22589 | } |
22590 | ||
c921be7d | 22591 | static bfd_boolean |
c19d1205 | 22592 | arm_parse_arch (char * str) |
7ed4c4c5 | 22593 | { |
e74cfd16 | 22594 | const struct arm_arch_option_table *opt; |
c19d1205 ZW |
22595 | char *ext = strchr (str, '+'); |
22596 | int optlen; | |
7ed4c4c5 | 22597 | |
c19d1205 ZW |
22598 | if (ext != NULL) |
22599 | optlen = ext - str; | |
7ed4c4c5 | 22600 | else |
c19d1205 | 22601 | optlen = strlen (str); |
7ed4c4c5 | 22602 | |
c19d1205 | 22603 | if (optlen == 0) |
7ed4c4c5 | 22604 | { |
c19d1205 | 22605 | as_bad (_("missing architecture name `%s'"), str); |
c921be7d | 22606 | return FALSE; |
7ed4c4c5 NC |
22607 | } |
22608 | ||
c19d1205 ZW |
22609 | for (opt = arm_archs; opt->name != NULL; opt++) |
22610 | if (streq (opt->name, str)) | |
22611 | { | |
e74cfd16 PB |
22612 | march_cpu_opt = &opt->value; |
22613 | march_fpu_opt = &opt->default_fpu; | |
5f4273c7 | 22614 | strcpy (selected_cpu_name, opt->name); |
7ed4c4c5 | 22615 | |
c19d1205 ZW |
22616 | if (ext != NULL) |
22617 | return arm_parse_extension (ext, &march_cpu_opt); | |
7ed4c4c5 | 22618 | |
c921be7d | 22619 | return TRUE; |
c19d1205 ZW |
22620 | } |
22621 | ||
22622 | as_bad (_("unknown architecture `%s'\n"), str); | |
c921be7d | 22623 | return FALSE; |
7ed4c4c5 | 22624 | } |
eb043451 | 22625 | |
c921be7d | 22626 | static bfd_boolean |
c19d1205 ZW |
22627 | arm_parse_fpu (char * str) |
22628 | { | |
e74cfd16 | 22629 | const struct arm_option_cpu_value_table * opt; |
b99bd4ef | 22630 | |
c19d1205 ZW |
22631 | for (opt = arm_fpus; opt->name != NULL; opt++) |
22632 | if (streq (opt->name, str)) | |
22633 | { | |
e74cfd16 | 22634 | mfpu_opt = &opt->value; |
c921be7d | 22635 | return TRUE; |
c19d1205 | 22636 | } |
b99bd4ef | 22637 | |
c19d1205 | 22638 | as_bad (_("unknown floating point format `%s'\n"), str); |
c921be7d | 22639 | return FALSE; |
c19d1205 ZW |
22640 | } |
22641 | ||
c921be7d | 22642 | static bfd_boolean |
c19d1205 | 22643 | arm_parse_float_abi (char * str) |
b99bd4ef | 22644 | { |
e74cfd16 | 22645 | const struct arm_option_value_table * opt; |
b99bd4ef | 22646 | |
c19d1205 ZW |
22647 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
22648 | if (streq (opt->name, str)) | |
22649 | { | |
22650 | mfloat_abi_opt = opt->value; | |
c921be7d | 22651 | return TRUE; |
c19d1205 | 22652 | } |
cc8a6dd0 | 22653 | |
c19d1205 | 22654 | as_bad (_("unknown floating point abi `%s'\n"), str); |
c921be7d | 22655 | return FALSE; |
c19d1205 | 22656 | } |
b99bd4ef | 22657 | |
c19d1205 | 22658 | #ifdef OBJ_ELF |
c921be7d | 22659 | static bfd_boolean |
c19d1205 ZW |
22660 | arm_parse_eabi (char * str) |
22661 | { | |
e74cfd16 | 22662 | const struct arm_option_value_table *opt; |
cc8a6dd0 | 22663 | |
c19d1205 ZW |
22664 | for (opt = arm_eabis; opt->name != NULL; opt++) |
22665 | if (streq (opt->name, str)) | |
22666 | { | |
22667 | meabi_flags = opt->value; | |
c921be7d | 22668 | return TRUE; |
c19d1205 ZW |
22669 | } |
22670 | as_bad (_("unknown EABI `%s'\n"), str); | |
c921be7d | 22671 | return FALSE; |
c19d1205 ZW |
22672 | } |
22673 | #endif | |
cc8a6dd0 | 22674 | |
c921be7d | 22675 | static bfd_boolean |
e07e6e58 NC |
22676 | arm_parse_it_mode (char * str) |
22677 | { | |
c921be7d | 22678 | bfd_boolean ret = TRUE; |
e07e6e58 NC |
22679 | |
22680 | if (streq ("arm", str)) | |
22681 | implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
22682 | else if (streq ("thumb", str)) | |
22683 | implicit_it_mode = IMPLICIT_IT_MODE_THUMB; | |
22684 | else if (streq ("always", str)) | |
22685 | implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS; | |
22686 | else if (streq ("never", str)) | |
22687 | implicit_it_mode = IMPLICIT_IT_MODE_NEVER; | |
22688 | else | |
22689 | { | |
22690 | as_bad (_("unknown implicit IT mode `%s', should be "\ | |
22691 | "arm, thumb, always, or never."), str); | |
c921be7d | 22692 | ret = FALSE; |
e07e6e58 NC |
22693 | } |
22694 | ||
22695 | return ret; | |
22696 | } | |
22697 | ||
c19d1205 ZW |
22698 | struct arm_long_option_table arm_long_opts[] = |
22699 | { | |
22700 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
22701 | arm_parse_cpu, NULL}, | |
22702 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
22703 | arm_parse_arch, NULL}, | |
22704 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
22705 | arm_parse_fpu, NULL}, | |
22706 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
22707 | arm_parse_float_abi, NULL}, | |
22708 | #ifdef OBJ_ELF | |
7fac0536 | 22709 | {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"), |
c19d1205 ZW |
22710 | arm_parse_eabi, NULL}, |
22711 | #endif | |
e07e6e58 NC |
22712 | {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"), |
22713 | arm_parse_it_mode, NULL}, | |
c19d1205 ZW |
22714 | {NULL, NULL, 0, NULL} |
22715 | }; | |
cc8a6dd0 | 22716 | |
c19d1205 ZW |
22717 | int |
22718 | md_parse_option (int c, char * arg) | |
22719 | { | |
22720 | struct arm_option_table *opt; | |
e74cfd16 | 22721 | const struct arm_legacy_option_table *fopt; |
c19d1205 | 22722 | struct arm_long_option_table *lopt; |
b99bd4ef | 22723 | |
c19d1205 | 22724 | switch (c) |
b99bd4ef | 22725 | { |
c19d1205 ZW |
22726 | #ifdef OPTION_EB |
22727 | case OPTION_EB: | |
22728 | target_big_endian = 1; | |
22729 | break; | |
22730 | #endif | |
cc8a6dd0 | 22731 | |
c19d1205 ZW |
22732 | #ifdef OPTION_EL |
22733 | case OPTION_EL: | |
22734 | target_big_endian = 0; | |
22735 | break; | |
22736 | #endif | |
b99bd4ef | 22737 | |
845b51d6 PB |
22738 | case OPTION_FIX_V4BX: |
22739 | fix_v4bx = TRUE; | |
22740 | break; | |
22741 | ||
c19d1205 ZW |
22742 | case 'a': |
22743 | /* Listing option. Just ignore these, we don't support additional | |
22744 | ones. */ | |
22745 | return 0; | |
b99bd4ef | 22746 | |
c19d1205 ZW |
22747 | default: |
22748 | for (opt = arm_opts; opt->option != NULL; opt++) | |
22749 | { | |
22750 | if (c == opt->option[0] | |
22751 | && ((arg == NULL && opt->option[1] == 0) | |
22752 | || streq (arg, opt->option + 1))) | |
22753 | { | |
c19d1205 | 22754 | /* If the option is deprecated, tell the user. */ |
278df34e | 22755 | if (warn_on_deprecated && opt->deprecated != NULL) |
c19d1205 ZW |
22756 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
22757 | arg ? arg : "", _(opt->deprecated)); | |
b99bd4ef | 22758 | |
c19d1205 ZW |
22759 | if (opt->var != NULL) |
22760 | *opt->var = opt->value; | |
cc8a6dd0 | 22761 | |
c19d1205 ZW |
22762 | return 1; |
22763 | } | |
22764 | } | |
b99bd4ef | 22765 | |
e74cfd16 PB |
22766 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
22767 | { | |
22768 | if (c == fopt->option[0] | |
22769 | && ((arg == NULL && fopt->option[1] == 0) | |
22770 | || streq (arg, fopt->option + 1))) | |
22771 | { | |
e74cfd16 | 22772 | /* If the option is deprecated, tell the user. */ |
278df34e | 22773 | if (warn_on_deprecated && fopt->deprecated != NULL) |
e74cfd16 PB |
22774 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
22775 | arg ? arg : "", _(fopt->deprecated)); | |
e74cfd16 PB |
22776 | |
22777 | if (fopt->var != NULL) | |
22778 | *fopt->var = &fopt->value; | |
22779 | ||
22780 | return 1; | |
22781 | } | |
22782 | } | |
22783 | ||
c19d1205 ZW |
22784 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
22785 | { | |
22786 | /* These options are expected to have an argument. */ | |
22787 | if (c == lopt->option[0] | |
22788 | && arg != NULL | |
22789 | && strncmp (arg, lopt->option + 1, | |
22790 | strlen (lopt->option + 1)) == 0) | |
22791 | { | |
c19d1205 | 22792 | /* If the option is deprecated, tell the user. */ |
278df34e | 22793 | if (warn_on_deprecated && lopt->deprecated != NULL) |
c19d1205 ZW |
22794 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, |
22795 | _(lopt->deprecated)); | |
b99bd4ef | 22796 | |
c19d1205 ZW |
22797 | /* Call the sup-option parser. */ |
22798 | return lopt->func (arg + strlen (lopt->option) - 1); | |
22799 | } | |
22800 | } | |
a737bd4d | 22801 | |
c19d1205 ZW |
22802 | return 0; |
22803 | } | |
a394c00f | 22804 | |
c19d1205 ZW |
22805 | return 1; |
22806 | } | |
a394c00f | 22807 | |
c19d1205 ZW |
22808 | void |
22809 | md_show_usage (FILE * fp) | |
a394c00f | 22810 | { |
c19d1205 ZW |
22811 | struct arm_option_table *opt; |
22812 | struct arm_long_option_table *lopt; | |
a394c00f | 22813 | |
c19d1205 | 22814 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 22815 | |
c19d1205 ZW |
22816 | for (opt = arm_opts; opt->option != NULL; opt++) |
22817 | if (opt->help != NULL) | |
22818 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 22819 | |
c19d1205 ZW |
22820 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
22821 | if (lopt->help != NULL) | |
22822 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 22823 | |
c19d1205 ZW |
22824 | #ifdef OPTION_EB |
22825 | fprintf (fp, _("\ | |
22826 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
22827 | #endif |
22828 | ||
c19d1205 ZW |
22829 | #ifdef OPTION_EL |
22830 | fprintf (fp, _("\ | |
22831 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 22832 | #endif |
845b51d6 PB |
22833 | |
22834 | fprintf (fp, _("\ | |
22835 | --fix-v4bx Allow BX in ARMv4 code\n")); | |
c19d1205 | 22836 | } |
ee065d83 PB |
22837 | |
22838 | ||
22839 | #ifdef OBJ_ELF | |
62b3e311 PB |
22840 | typedef struct |
22841 | { | |
22842 | int val; | |
22843 | arm_feature_set flags; | |
22844 | } cpu_arch_ver_table; | |
22845 | ||
22846 | /* Mapping from CPU features to EABI CPU arch values. Table must be sorted | |
22847 | least features first. */ | |
22848 | static const cpu_arch_ver_table cpu_arch_ver[] = | |
22849 | { | |
22850 | {1, ARM_ARCH_V4}, | |
22851 | {2, ARM_ARCH_V4T}, | |
22852 | {3, ARM_ARCH_V5}, | |
ee3c0378 | 22853 | {3, ARM_ARCH_V5T}, |
62b3e311 PB |
22854 | {4, ARM_ARCH_V5TE}, |
22855 | {5, ARM_ARCH_V5TEJ}, | |
22856 | {6, ARM_ARCH_V6}, | |
22857 | {7, ARM_ARCH_V6Z}, | |
7e806470 | 22858 | {9, ARM_ARCH_V6K}, |
91e22acd | 22859 | {11, ARM_ARCH_V6M}, |
7e806470 | 22860 | {8, ARM_ARCH_V6T2}, |
62b3e311 PB |
22861 | {10, ARM_ARCH_V7A}, |
22862 | {10, ARM_ARCH_V7R}, | |
22863 | {10, ARM_ARCH_V7M}, | |
22864 | {0, ARM_ARCH_NONE} | |
22865 | }; | |
22866 | ||
ee3c0378 AS |
22867 | /* Set an attribute if it has not already been set by the user. */ |
22868 | static void | |
22869 | aeabi_set_attribute_int (int tag, int value) | |
22870 | { | |
22871 | if (tag < 1 | |
22872 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
22873 | || !attributes_set_explicitly[tag]) | |
22874 | bfd_elf_add_proc_attr_int (stdoutput, tag, value); | |
22875 | } | |
22876 | ||
22877 | static void | |
22878 | aeabi_set_attribute_string (int tag, const char *value) | |
22879 | { | |
22880 | if (tag < 1 | |
22881 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
22882 | || !attributes_set_explicitly[tag]) | |
22883 | bfd_elf_add_proc_attr_string (stdoutput, tag, value); | |
22884 | } | |
22885 | ||
ee065d83 PB |
22886 | /* Set the public EABI object attributes. */ |
22887 | static void | |
22888 | aeabi_set_public_attributes (void) | |
22889 | { | |
22890 | int arch; | |
e74cfd16 | 22891 | arm_feature_set flags; |
62b3e311 PB |
22892 | arm_feature_set tmp; |
22893 | const cpu_arch_ver_table *p; | |
ee065d83 PB |
22894 | |
22895 | /* Choose the architecture based on the capabilities of the requested cpu | |
22896 | (if any) and/or the instructions actually used. */ | |
e74cfd16 PB |
22897 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); |
22898 | ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); | |
22899 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); | |
7a1d4c38 PB |
22900 | /*Allow the user to override the reported architecture. */ |
22901 | if (object_arch) | |
22902 | { | |
22903 | ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); | |
22904 | ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); | |
22905 | } | |
22906 | ||
62b3e311 PB |
22907 | tmp = flags; |
22908 | arch = 0; | |
22909 | for (p = cpu_arch_ver; p->val; p++) | |
22910 | { | |
22911 | if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) | |
22912 | { | |
22913 | arch = p->val; | |
22914 | ARM_CLEAR_FEATURE (tmp, tmp, p->flags); | |
22915 | } | |
22916 | } | |
ee065d83 | 22917 | |
9e3c6df6 PB |
22918 | /* The table lookup above finds the last architecture to contribute |
22919 | a new feature. Unfortunately, Tag13 is a subset of the union of | |
22920 | v6T2 and v7-M, so it is never seen as contributing a new feature. | |
22921 | We can not search for the last entry which is entirely used, | |
22922 | because if no CPU is specified we build up only those flags | |
22923 | actually used. Perhaps we should separate out the specified | |
22924 | and implicit cases. Avoid taking this path for -march=all by | |
22925 | checking for contradictory v7-A / v7-M features. */ | |
22926 | if (arch == 10 | |
22927 | && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a) | |
22928 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m) | |
22929 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp)) | |
22930 | arch = 13; | |
22931 | ||
ee065d83 PB |
22932 | /* Tag_CPU_name. */ |
22933 | if (selected_cpu_name[0]) | |
22934 | { | |
91d6fa6a | 22935 | char *q; |
ee065d83 | 22936 | |
91d6fa6a NC |
22937 | q = selected_cpu_name; |
22938 | if (strncmp (q, "armv", 4) == 0) | |
ee065d83 PB |
22939 | { |
22940 | int i; | |
5f4273c7 | 22941 | |
91d6fa6a NC |
22942 | q += 4; |
22943 | for (i = 0; q[i]; i++) | |
22944 | q[i] = TOUPPER (q[i]); | |
ee065d83 | 22945 | } |
91d6fa6a | 22946 | aeabi_set_attribute_string (Tag_CPU_name, q); |
ee065d83 | 22947 | } |
62f3b8c8 | 22948 | |
ee065d83 | 22949 | /* Tag_CPU_arch. */ |
ee3c0378 | 22950 | aeabi_set_attribute_int (Tag_CPU_arch, arch); |
62f3b8c8 | 22951 | |
62b3e311 PB |
22952 | /* Tag_CPU_arch_profile. */ |
22953 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) | |
ee3c0378 | 22954 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'A'); |
62b3e311 | 22955 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) |
ee3c0378 | 22956 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'R'); |
7e806470 | 22957 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m)) |
ee3c0378 | 22958 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'M'); |
62f3b8c8 | 22959 | |
ee065d83 | 22960 | /* Tag_ARM_ISA_use. */ |
ee3c0378 AS |
22961 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) |
22962 | || arch == 0) | |
22963 | aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); | |
62f3b8c8 | 22964 | |
ee065d83 | 22965 | /* Tag_THUMB_ISA_use. */ |
ee3c0378 AS |
22966 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) |
22967 | || arch == 0) | |
22968 | aeabi_set_attribute_int (Tag_THUMB_ISA_use, | |
22969 | ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1); | |
62f3b8c8 | 22970 | |
ee065d83 | 22971 | /* Tag_VFP_arch. */ |
62f3b8c8 PB |
22972 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma)) |
22973 | aeabi_set_attribute_int (Tag_VFP_arch, | |
22974 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
22975 | ? 5 : 6); | |
22976 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) | |
ee3c0378 | 22977 | aeabi_set_attribute_int (Tag_VFP_arch, 3); |
ada65aa3 | 22978 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd)) |
ee3c0378 AS |
22979 | aeabi_set_attribute_int (Tag_VFP_arch, 4); |
22980 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) | |
22981 | aeabi_set_attribute_int (Tag_VFP_arch, 2); | |
22982 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) | |
22983 | || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)) | |
22984 | aeabi_set_attribute_int (Tag_VFP_arch, 1); | |
62f3b8c8 | 22985 | |
4547cb56 NC |
22986 | /* Tag_ABI_HardFP_use. */ |
22987 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd) | |
22988 | && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)) | |
22989 | aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1); | |
22990 | ||
ee065d83 | 22991 | /* Tag_WMMX_arch. */ |
ee3c0378 AS |
22992 | if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2)) |
22993 | aeabi_set_attribute_int (Tag_WMMX_arch, 2); | |
22994 | else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt)) | |
22995 | aeabi_set_attribute_int (Tag_WMMX_arch, 1); | |
62f3b8c8 | 22996 | |
ee3c0378 | 22997 | /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ |
8e79c3df | 22998 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) |
62f3b8c8 PB |
22999 | aeabi_set_attribute_int |
23000 | (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma) | |
23001 | ? 2 : 1)); | |
23002 | ||
ee3c0378 | 23003 | /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ |
62f3b8c8 | 23004 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16)) |
ee3c0378 | 23005 | aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); |
4547cb56 NC |
23006 | |
23007 | /* Tag_DIV_use. */ | |
23008 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div)) | |
23009 | aeabi_set_attribute_int (Tag_DIV_use, 0); | |
23010 | /* Fill this in when gas supports v7a sdiv/udiv. | |
23011 | else if (... v7a with div extension used ...) | |
23012 | aeabi_set_attribute_int (Tag_DIV_use, 2); */ | |
23013 | else | |
23014 | aeabi_set_attribute_int (Tag_DIV_use, 1); | |
ee065d83 PB |
23015 | } |
23016 | ||
104d59d1 | 23017 | /* Add the default contents for the .ARM.attributes section. */ |
ee065d83 PB |
23018 | void |
23019 | arm_md_end (void) | |
23020 | { | |
ee065d83 PB |
23021 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
23022 | return; | |
23023 | ||
23024 | aeabi_set_public_attributes (); | |
ee065d83 | 23025 | } |
8463be01 | 23026 | #endif /* OBJ_ELF */ |
ee065d83 PB |
23027 | |
23028 | ||
23029 | /* Parse a .cpu directive. */ | |
23030 | ||
23031 | static void | |
23032 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) | |
23033 | { | |
e74cfd16 | 23034 | const struct arm_cpu_option_table *opt; |
ee065d83 PB |
23035 | char *name; |
23036 | char saved_char; | |
23037 | ||
23038 | name = input_line_pointer; | |
5f4273c7 | 23039 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
23040 | input_line_pointer++; |
23041 | saved_char = *input_line_pointer; | |
23042 | *input_line_pointer = 0; | |
23043 | ||
23044 | /* Skip the first "all" entry. */ | |
23045 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) | |
23046 | if (streq (opt->name, name)) | |
23047 | { | |
e74cfd16 PB |
23048 | mcpu_cpu_opt = &opt->value; |
23049 | selected_cpu = opt->value; | |
ee065d83 | 23050 | if (opt->canonical_name) |
5f4273c7 | 23051 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
23052 | else |
23053 | { | |
23054 | int i; | |
23055 | for (i = 0; opt->name[i]; i++) | |
23056 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
23057 | selected_cpu_name[i] = 0; | |
23058 | } | |
e74cfd16 | 23059 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
23060 | *input_line_pointer = saved_char; |
23061 | demand_empty_rest_of_line (); | |
23062 | return; | |
23063 | } | |
23064 | as_bad (_("unknown cpu `%s'"), name); | |
23065 | *input_line_pointer = saved_char; | |
23066 | ignore_rest_of_line (); | |
23067 | } | |
23068 | ||
23069 | ||
23070 | /* Parse a .arch directive. */ | |
23071 | ||
23072 | static void | |
23073 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) | |
23074 | { | |
e74cfd16 | 23075 | const struct arm_arch_option_table *opt; |
ee065d83 PB |
23076 | char saved_char; |
23077 | char *name; | |
23078 | ||
23079 | name = input_line_pointer; | |
5f4273c7 | 23080 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
23081 | input_line_pointer++; |
23082 | saved_char = *input_line_pointer; | |
23083 | *input_line_pointer = 0; | |
23084 | ||
23085 | /* Skip the first "all" entry. */ | |
23086 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
23087 | if (streq (opt->name, name)) | |
23088 | { | |
e74cfd16 PB |
23089 | mcpu_cpu_opt = &opt->value; |
23090 | selected_cpu = opt->value; | |
5f4273c7 | 23091 | strcpy (selected_cpu_name, opt->name); |
e74cfd16 | 23092 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
23093 | *input_line_pointer = saved_char; |
23094 | demand_empty_rest_of_line (); | |
23095 | return; | |
23096 | } | |
23097 | ||
23098 | as_bad (_("unknown architecture `%s'\n"), name); | |
23099 | *input_line_pointer = saved_char; | |
23100 | ignore_rest_of_line (); | |
23101 | } | |
23102 | ||
23103 | ||
7a1d4c38 PB |
23104 | /* Parse a .object_arch directive. */ |
23105 | ||
23106 | static void | |
23107 | s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) | |
23108 | { | |
23109 | const struct arm_arch_option_table *opt; | |
23110 | char saved_char; | |
23111 | char *name; | |
23112 | ||
23113 | name = input_line_pointer; | |
5f4273c7 | 23114 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
7a1d4c38 PB |
23115 | input_line_pointer++; |
23116 | saved_char = *input_line_pointer; | |
23117 | *input_line_pointer = 0; | |
23118 | ||
23119 | /* Skip the first "all" entry. */ | |
23120 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
23121 | if (streq (opt->name, name)) | |
23122 | { | |
23123 | object_arch = &opt->value; | |
23124 | *input_line_pointer = saved_char; | |
23125 | demand_empty_rest_of_line (); | |
23126 | return; | |
23127 | } | |
23128 | ||
23129 | as_bad (_("unknown architecture `%s'\n"), name); | |
23130 | *input_line_pointer = saved_char; | |
23131 | ignore_rest_of_line (); | |
23132 | } | |
23133 | ||
ee065d83 PB |
23134 | /* Parse a .fpu directive. */ |
23135 | ||
23136 | static void | |
23137 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) | |
23138 | { | |
e74cfd16 | 23139 | const struct arm_option_cpu_value_table *opt; |
ee065d83 PB |
23140 | char saved_char; |
23141 | char *name; | |
23142 | ||
23143 | name = input_line_pointer; | |
5f4273c7 | 23144 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
23145 | input_line_pointer++; |
23146 | saved_char = *input_line_pointer; | |
23147 | *input_line_pointer = 0; | |
5f4273c7 | 23148 | |
ee065d83 PB |
23149 | for (opt = arm_fpus; opt->name != NULL; opt++) |
23150 | if (streq (opt->name, name)) | |
23151 | { | |
e74cfd16 PB |
23152 | mfpu_opt = &opt->value; |
23153 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
ee065d83 PB |
23154 | *input_line_pointer = saved_char; |
23155 | demand_empty_rest_of_line (); | |
23156 | return; | |
23157 | } | |
23158 | ||
23159 | as_bad (_("unknown floating point format `%s'\n"), name); | |
23160 | *input_line_pointer = saved_char; | |
23161 | ignore_rest_of_line (); | |
23162 | } | |
ee065d83 | 23163 | |
794ba86a | 23164 | /* Copy symbol information. */ |
f31fef98 | 23165 | |
794ba86a DJ |
23166 | void |
23167 | arm_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
23168 | { | |
23169 | ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); | |
23170 | } | |
e04befd0 | 23171 | |
f31fef98 | 23172 | #ifdef OBJ_ELF |
e04befd0 AS |
23173 | /* Given a symbolic attribute NAME, return the proper integer value. |
23174 | Returns -1 if the attribute is not known. */ | |
f31fef98 | 23175 | |
e04befd0 AS |
23176 | int |
23177 | arm_convert_symbolic_attribute (const char *name) | |
23178 | { | |
f31fef98 NC |
23179 | static const struct |
23180 | { | |
23181 | const char * name; | |
23182 | const int tag; | |
23183 | } | |
23184 | attribute_table[] = | |
23185 | { | |
23186 | /* When you modify this table you should | |
23187 | also modify the list in doc/c-arm.texi. */ | |
e04befd0 | 23188 | #define T(tag) {#tag, tag} |
f31fef98 NC |
23189 | T (Tag_CPU_raw_name), |
23190 | T (Tag_CPU_name), | |
23191 | T (Tag_CPU_arch), | |
23192 | T (Tag_CPU_arch_profile), | |
23193 | T (Tag_ARM_ISA_use), | |
23194 | T (Tag_THUMB_ISA_use), | |
75375b3e | 23195 | T (Tag_FP_arch), |
f31fef98 NC |
23196 | T (Tag_VFP_arch), |
23197 | T (Tag_WMMX_arch), | |
23198 | T (Tag_Advanced_SIMD_arch), | |
23199 | T (Tag_PCS_config), | |
23200 | T (Tag_ABI_PCS_R9_use), | |
23201 | T (Tag_ABI_PCS_RW_data), | |
23202 | T (Tag_ABI_PCS_RO_data), | |
23203 | T (Tag_ABI_PCS_GOT_use), | |
23204 | T (Tag_ABI_PCS_wchar_t), | |
23205 | T (Tag_ABI_FP_rounding), | |
23206 | T (Tag_ABI_FP_denormal), | |
23207 | T (Tag_ABI_FP_exceptions), | |
23208 | T (Tag_ABI_FP_user_exceptions), | |
23209 | T (Tag_ABI_FP_number_model), | |
75375b3e | 23210 | T (Tag_ABI_align_needed), |
f31fef98 | 23211 | T (Tag_ABI_align8_needed), |
75375b3e | 23212 | T (Tag_ABI_align_preserved), |
f31fef98 NC |
23213 | T (Tag_ABI_align8_preserved), |
23214 | T (Tag_ABI_enum_size), | |
23215 | T (Tag_ABI_HardFP_use), | |
23216 | T (Tag_ABI_VFP_args), | |
23217 | T (Tag_ABI_WMMX_args), | |
23218 | T (Tag_ABI_optimization_goals), | |
23219 | T (Tag_ABI_FP_optimization_goals), | |
23220 | T (Tag_compatibility), | |
23221 | T (Tag_CPU_unaligned_access), | |
75375b3e | 23222 | T (Tag_FP_HP_extension), |
f31fef98 NC |
23223 | T (Tag_VFP_HP_extension), |
23224 | T (Tag_ABI_FP_16bit_format), | |
cd21e546 MGD |
23225 | T (Tag_MPextension_use), |
23226 | T (Tag_DIV_use), | |
f31fef98 NC |
23227 | T (Tag_nodefaults), |
23228 | T (Tag_also_compatible_with), | |
23229 | T (Tag_conformance), | |
23230 | T (Tag_T2EE_use), | |
23231 | T (Tag_Virtualization_use), | |
cd21e546 | 23232 | /* We deliberately do not include Tag_MPextension_use_legacy. */ |
e04befd0 | 23233 | #undef T |
f31fef98 | 23234 | }; |
e04befd0 AS |
23235 | unsigned int i; |
23236 | ||
23237 | if (name == NULL) | |
23238 | return -1; | |
23239 | ||
f31fef98 | 23240 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
c921be7d | 23241 | if (streq (name, attribute_table[i].name)) |
e04befd0 AS |
23242 | return attribute_table[i].tag; |
23243 | ||
23244 | return -1; | |
23245 | } | |
267bf995 RR |
23246 | |
23247 | ||
23248 | /* Apply sym value for relocations only in the case that | |
23249 | they are for local symbols and you have the respective | |
23250 | architectural feature for blx and simple switches. */ | |
23251 | int | |
23252 | arm_apply_sym_value (struct fix * fixP) | |
23253 | { | |
23254 | if (fixP->fx_addsy | |
23255 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
23256 | && !S_IS_EXTERNAL (fixP->fx_addsy)) | |
23257 | { | |
23258 | switch (fixP->fx_r_type) | |
23259 | { | |
23260 | case BFD_RELOC_ARM_PCREL_BLX: | |
23261 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
23262 | if (ARM_IS_FUNC (fixP->fx_addsy)) | |
23263 | return 1; | |
23264 | break; | |
23265 | ||
23266 | case BFD_RELOC_ARM_PCREL_CALL: | |
23267 | case BFD_RELOC_THUMB_PCREL_BLX: | |
23268 | if (THUMB_IS_FUNC (fixP->fx_addsy)) | |
23269 | return 1; | |
23270 | break; | |
23271 | ||
23272 | default: | |
23273 | break; | |
23274 | } | |
23275 | ||
23276 | } | |
23277 | return 0; | |
23278 | } | |
f31fef98 | 23279 | #endif /* OBJ_ELF */ |