Commit | Line | Data |
---|---|---|
b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
f17c130b | 2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, |
ebd1c875 | 3 | 2004, 2005, 2006 |
b99bd4ef NC |
4 | Free Software Foundation, Inc. |
5 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) | |
6 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 7 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
8 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
9 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
10 | |
11 | This file is part of GAS, the GNU Assembler. | |
12 | ||
13 | GAS is free software; you can redistribute it and/or modify | |
14 | it under the terms of the GNU General Public License as published by | |
15 | the Free Software Foundation; either version 2, or (at your option) | |
16 | any later version. | |
17 | ||
18 | GAS is distributed in the hope that it will be useful, | |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
21 | GNU General Public License for more details. |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
24 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
25 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
26 | 02110-1301, USA. */ | |
b99bd4ef | 27 | |
5287ad62 | 28 | #include <limits.h> |
037e8744 | 29 | #include <stdarg.h> |
c19d1205 | 30 | #define NO_RELOC 0 |
b99bd4ef | 31 | #include "as.h" |
3882b010 | 32 | #include "safe-ctype.h" |
b99bd4ef NC |
33 | #include "subsegs.h" |
34 | #include "obstack.h" | |
b99bd4ef | 35 | |
f263249b RE |
36 | #include "opcode/arm.h" |
37 | ||
b99bd4ef NC |
38 | #ifdef OBJ_ELF |
39 | #include "elf/arm.h" | |
40 | #include "dwarf2dbg.h" | |
a394c00f | 41 | #include "dw2gencfi.h" |
b99bd4ef NC |
42 | #endif |
43 | ||
7ed4c4c5 | 44 | /* XXX Set this to 1 after the next binutils release. */ |
03b1477f RE |
45 | #define WARN_DEPRECATED 0 |
46 | ||
7ed4c4c5 NC |
47 | #ifdef OBJ_ELF |
48 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
49 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
50 | ||
51 | /* This structure holds the unwinding state. */ | |
52 | ||
53 | static struct | |
54 | { | |
c19d1205 ZW |
55 | symbolS * proc_start; |
56 | symbolS * table_entry; | |
57 | symbolS * personality_routine; | |
58 | int personality_index; | |
7ed4c4c5 | 59 | /* The segment containing the function. */ |
c19d1205 ZW |
60 | segT saved_seg; |
61 | subsegT saved_subseg; | |
7ed4c4c5 NC |
62 | /* Opcodes generated from this function. */ |
63 | unsigned char * opcodes; | |
c19d1205 ZW |
64 | int opcode_count; |
65 | int opcode_alloc; | |
7ed4c4c5 | 66 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 67 | offsetT frame_size; |
7ed4c4c5 NC |
68 | /* We don't add stack adjustment opcodes immediately so that we can merge |
69 | multiple adjustments. We can also omit the final adjustment | |
70 | when using a frame pointer. */ | |
c19d1205 | 71 | offsetT pending_offset; |
7ed4c4c5 | 72 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
73 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
74 | offsetT fp_offset; | |
75 | int fp_reg; | |
7ed4c4c5 | 76 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 77 | unsigned fp_used:1; |
7ed4c4c5 | 78 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 79 | unsigned sp_restored:1; |
7ed4c4c5 NC |
80 | } unwind; |
81 | ||
8b1ad454 NC |
82 | /* Bit N indicates that an R_ARM_NONE relocation has been output for |
83 | __aeabi_unwind_cpp_prN already if set. This enables dependencies to be | |
84 | emitted only once per section, to save unnecessary bloat. */ | |
85 | static unsigned int marked_pr_dependency = 0; | |
86 | ||
87 | #endif /* OBJ_ELF */ | |
88 | ||
4962c51a MS |
89 | /* Results from operand parsing worker functions. */ |
90 | ||
91 | typedef enum | |
92 | { | |
93 | PARSE_OPERAND_SUCCESS, | |
94 | PARSE_OPERAND_FAIL, | |
95 | PARSE_OPERAND_FAIL_NO_BACKTRACK | |
96 | } parse_operand_result; | |
97 | ||
33a392fb PB |
98 | enum arm_float_abi |
99 | { | |
100 | ARM_FLOAT_ABI_HARD, | |
101 | ARM_FLOAT_ABI_SOFTFP, | |
102 | ARM_FLOAT_ABI_SOFT | |
103 | }; | |
104 | ||
c19d1205 | 105 | /* Types of processor to assemble for. */ |
b99bd4ef NC |
106 | #ifndef CPU_DEFAULT |
107 | #if defined __XSCALE__ | |
e74cfd16 | 108 | #define CPU_DEFAULT ARM_ARCH_XSCALE |
b99bd4ef NC |
109 | #else |
110 | #if defined __thumb__ | |
e74cfd16 | 111 | #define CPU_DEFAULT ARM_ARCH_V5T |
b99bd4ef NC |
112 | #endif |
113 | #endif | |
114 | #endif | |
115 | ||
116 | #ifndef FPU_DEFAULT | |
c820d418 MM |
117 | # ifdef TE_LINUX |
118 | # define FPU_DEFAULT FPU_ARCH_FPA | |
119 | # elif defined (TE_NetBSD) | |
120 | # ifdef OBJ_ELF | |
121 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
122 | # else | |
123 | /* Legacy a.out format. */ | |
124 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
125 | # endif | |
4e7fd91e PB |
126 | # elif defined (TE_VXWORKS) |
127 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
128 | # else |
129 | /* For backwards compatibility, default to FPA. */ | |
130 | # define FPU_DEFAULT FPU_ARCH_FPA | |
131 | # endif | |
132 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 133 | |
c19d1205 | 134 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 135 | |
e74cfd16 PB |
136 | static arm_feature_set cpu_variant; |
137 | static arm_feature_set arm_arch_used; | |
138 | static arm_feature_set thumb_arch_used; | |
b99bd4ef | 139 | |
b99bd4ef | 140 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
141 | static int uses_apcs_26 = FALSE; |
142 | static int atpcs = FALSE; | |
b34976b6 AM |
143 | static int support_interwork = FALSE; |
144 | static int uses_apcs_float = FALSE; | |
c19d1205 | 145 | static int pic_code = FALSE; |
03b1477f RE |
146 | |
147 | /* Variables that we set while parsing command-line options. Once all | |
148 | options have been read we re-process these values to set the real | |
149 | assembly flags. */ | |
e74cfd16 PB |
150 | static const arm_feature_set *legacy_cpu = NULL; |
151 | static const arm_feature_set *legacy_fpu = NULL; | |
152 | ||
153 | static const arm_feature_set *mcpu_cpu_opt = NULL; | |
154 | static const arm_feature_set *mcpu_fpu_opt = NULL; | |
155 | static const arm_feature_set *march_cpu_opt = NULL; | |
156 | static const arm_feature_set *march_fpu_opt = NULL; | |
157 | static const arm_feature_set *mfpu_opt = NULL; | |
158 | ||
159 | /* Constants for known architecture features. */ | |
160 | static const arm_feature_set fpu_default = FPU_DEFAULT; | |
161 | static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; | |
162 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; | |
5287ad62 JB |
163 | static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; |
164 | static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; | |
e74cfd16 PB |
165 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; |
166 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; | |
167 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; | |
168 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; | |
169 | ||
170 | #ifdef CPU_DEFAULT | |
171 | static const arm_feature_set cpu_default = CPU_DEFAULT; | |
172 | #endif | |
173 | ||
174 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); | |
175 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); | |
176 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); | |
177 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); | |
178 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); | |
179 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); | |
180 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); | |
181 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); | |
182 | static const arm_feature_set arm_ext_v4t_5 = | |
183 | ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); | |
184 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); | |
185 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); | |
186 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); | |
187 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); | |
188 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); | |
189 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); | |
190 | static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0); | |
191 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); | |
62b3e311 PB |
192 | static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); |
193 | static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); | |
194 | static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); | |
195 | static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); | |
196 | static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); | |
197 | static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); | |
e74cfd16 PB |
198 | |
199 | static const arm_feature_set arm_arch_any = ARM_ANY; | |
200 | static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); | |
201 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; | |
202 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; | |
203 | ||
204 | static const arm_feature_set arm_cext_iwmmxt = | |
205 | ARM_FEATURE (0, ARM_CEXT_IWMMXT); | |
206 | static const arm_feature_set arm_cext_xscale = | |
207 | ARM_FEATURE (0, ARM_CEXT_XSCALE); | |
208 | static const arm_feature_set arm_cext_maverick = | |
209 | ARM_FEATURE (0, ARM_CEXT_MAVERICK); | |
210 | static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); | |
211 | static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); | |
212 | static const arm_feature_set fpu_vfp_ext_v1xd = | |
213 | ARM_FEATURE (0, FPU_VFP_EXT_V1xD); | |
214 | static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); | |
215 | static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); | |
5287ad62 JB |
216 | static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); |
217 | static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); | |
218 | static const arm_feature_set fpu_vfp_v3_or_neon_ext = | |
219 | ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); | |
e74cfd16 | 220 | |
33a392fb | 221 | static int mfloat_abi_opt = -1; |
e74cfd16 PB |
222 | /* Record user cpu selection for object attributes. */ |
223 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; | |
ee065d83 PB |
224 | /* Must be long enough to hold any of the names in arm_cpus. */ |
225 | static char selected_cpu_name[16]; | |
7cc69913 | 226 | #ifdef OBJ_ELF |
deeaaff8 DJ |
227 | # ifdef EABI_DEFAULT |
228 | static int meabi_flags = EABI_DEFAULT; | |
229 | # else | |
d507cf36 | 230 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 231 | # endif |
7cc69913 | 232 | #endif |
b99bd4ef | 233 | |
b99bd4ef | 234 | #ifdef OBJ_ELF |
c19d1205 | 235 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
236 | symbolS * GOT_symbol; |
237 | #endif | |
238 | ||
b99bd4ef NC |
239 | /* 0: assemble for ARM, |
240 | 1: assemble for Thumb, | |
241 | 2: assemble for Thumb even though target CPU does not support thumb | |
242 | instructions. */ | |
243 | static int thumb_mode = 0; | |
244 | ||
c19d1205 ZW |
245 | /* If unified_syntax is true, we are processing the new unified |
246 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
247 | ||
248 | - Immediate operands do not require a # prefix. | |
249 | - Conditional affixes always appear at the end of the | |
250 | instruction. (For backward compatibility, those instructions | |
251 | that formerly had them in the middle, continue to accept them | |
252 | there.) | |
253 | - The IT instruction may appear, and if it does is validated | |
254 | against subsequent conditional affixes. It does not generate | |
255 | machine code. | |
256 | ||
257 | Important differences from the old Thumb mode: | |
258 | ||
259 | - Immediate operands do not require a # prefix. | |
260 | - Most of the V6T2 instructions are only available in unified mode. | |
261 | - The .N and .W suffixes are recognized and honored (it is an error | |
262 | if they cannot be honored). | |
263 | - All instructions set the flags if and only if they have an 's' affix. | |
264 | - Conditional affixes may be used. They are validated against | |
265 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
266 | conditional affix except in the scope of an IT instruction. */ | |
267 | ||
268 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef | 269 | |
5287ad62 JB |
270 | enum neon_el_type |
271 | { | |
dcbf9037 | 272 | NT_invtype, |
5287ad62 JB |
273 | NT_untyped, |
274 | NT_integer, | |
275 | NT_float, | |
276 | NT_poly, | |
277 | NT_signed, | |
dcbf9037 | 278 | NT_unsigned |
5287ad62 JB |
279 | }; |
280 | ||
281 | struct neon_type_el | |
282 | { | |
283 | enum neon_el_type type; | |
284 | unsigned size; | |
285 | }; | |
286 | ||
287 | #define NEON_MAX_TYPE_ELS 4 | |
288 | ||
289 | struct neon_type | |
290 | { | |
291 | struct neon_type_el el[NEON_MAX_TYPE_ELS]; | |
292 | unsigned elems; | |
293 | }; | |
294 | ||
b99bd4ef NC |
295 | struct arm_it |
296 | { | |
c19d1205 | 297 | const char * error; |
b99bd4ef | 298 | unsigned long instruction; |
c19d1205 ZW |
299 | int size; |
300 | int size_req; | |
301 | int cond; | |
037e8744 JB |
302 | /* "uncond_value" is set to the value in place of the conditional field in |
303 | unconditional versions of the instruction, or -1 if nothing is | |
304 | appropriate. */ | |
305 | int uncond_value; | |
5287ad62 | 306 | struct neon_type vectype; |
0110f2b8 PB |
307 | /* Set to the opcode if the instruction needs relaxation. |
308 | Zero if the instruction is not relaxed. */ | |
309 | unsigned long relax; | |
b99bd4ef NC |
310 | struct |
311 | { | |
312 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
313 | expressionS exp; |
314 | int pc_rel; | |
b99bd4ef | 315 | } reloc; |
b99bd4ef | 316 | |
c19d1205 ZW |
317 | struct |
318 | { | |
319 | unsigned reg; | |
ca3f61f7 | 320 | signed int imm; |
dcbf9037 | 321 | struct neon_type_el vectype; |
ca3f61f7 NC |
322 | unsigned present : 1; /* Operand present. */ |
323 | unsigned isreg : 1; /* Operand was a register. */ | |
324 | unsigned immisreg : 1; /* .imm field is a second register. */ | |
5287ad62 JB |
325 | unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ |
326 | unsigned immisalign : 1; /* Immediate is an alignment specifier. */ | |
327 | /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV | |
328 | instructions. This allows us to disambiguate ARM <-> vector insns. */ | |
329 | unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ | |
037e8744 | 330 | unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ |
5287ad62 | 331 | unsigned isquad : 1; /* Operand is Neon quad-precision register. */ |
037e8744 | 332 | unsigned issingle : 1; /* Operand is VFP single-precision register. */ |
ca3f61f7 NC |
333 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ |
334 | unsigned writeback : 1; /* Operand has trailing ! */ | |
335 | unsigned preind : 1; /* Preindexed address. */ | |
336 | unsigned postind : 1; /* Postindexed address. */ | |
337 | unsigned negative : 1; /* Index register was negated. */ | |
338 | unsigned shifted : 1; /* Shift applied to operation. */ | |
339 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
c19d1205 | 340 | } operands[6]; |
b99bd4ef NC |
341 | }; |
342 | ||
c19d1205 | 343 | static struct arm_it inst; |
b99bd4ef NC |
344 | |
345 | #define NUM_FLOAT_VALS 8 | |
346 | ||
05d2d07e | 347 | const char * fp_const[] = |
b99bd4ef NC |
348 | { |
349 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
350 | }; | |
351 | ||
c19d1205 | 352 | /* Number of littlenums required to hold an extended precision number. */ |
b99bd4ef NC |
353 | #define MAX_LITTLENUMS 6 |
354 | ||
355 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
356 | ||
357 | #define FAIL (-1) | |
358 | #define SUCCESS (0) | |
359 | ||
360 | #define SUFF_S 1 | |
361 | #define SUFF_D 2 | |
362 | #define SUFF_E 3 | |
363 | #define SUFF_P 4 | |
364 | ||
c19d1205 ZW |
365 | #define CP_T_X 0x00008000 |
366 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 367 | |
c19d1205 ZW |
368 | #define CONDS_BIT 0x00100000 |
369 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
370 | |
371 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
372 | ||
373 | struct asm_cond | |
374 | { | |
c19d1205 | 375 | const char * template; |
b99bd4ef NC |
376 | unsigned long value; |
377 | }; | |
378 | ||
c19d1205 | 379 | #define COND_ALWAYS 0xE |
b99bd4ef | 380 | |
b99bd4ef NC |
381 | struct asm_psr |
382 | { | |
b34976b6 | 383 | const char *template; |
b99bd4ef NC |
384 | unsigned long field; |
385 | }; | |
386 | ||
62b3e311 PB |
387 | struct asm_barrier_opt |
388 | { | |
389 | const char *template; | |
390 | unsigned long value; | |
391 | }; | |
392 | ||
2d2255b5 | 393 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
394 | #define SPSR_BIT (1 << 22) |
395 | ||
c19d1205 ZW |
396 | /* The individual PSR flag bits. */ |
397 | #define PSR_c (1 << 16) | |
398 | #define PSR_x (1 << 17) | |
399 | #define PSR_s (1 << 18) | |
400 | #define PSR_f (1 << 19) | |
b99bd4ef | 401 | |
c19d1205 | 402 | struct reloc_entry |
bfae80f2 | 403 | { |
c19d1205 ZW |
404 | char *name; |
405 | bfd_reloc_code_real_type reloc; | |
bfae80f2 RE |
406 | }; |
407 | ||
5287ad62 | 408 | enum vfp_reg_pos |
bfae80f2 | 409 | { |
5287ad62 JB |
410 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, |
411 | VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn | |
bfae80f2 RE |
412 | }; |
413 | ||
414 | enum vfp_ldstm_type | |
415 | { | |
416 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
417 | }; | |
418 | ||
dcbf9037 JB |
419 | /* Bits for DEFINED field in neon_typed_alias. */ |
420 | #define NTA_HASTYPE 1 | |
421 | #define NTA_HASINDEX 2 | |
422 | ||
423 | struct neon_typed_alias | |
424 | { | |
425 | unsigned char defined; | |
426 | unsigned char index; | |
427 | struct neon_type_el eltype; | |
428 | }; | |
429 | ||
c19d1205 ZW |
430 | /* ARM register categories. This includes coprocessor numbers and various |
431 | architecture extensions' registers. */ | |
432 | enum arm_reg_type | |
bfae80f2 | 433 | { |
c19d1205 ZW |
434 | REG_TYPE_RN, |
435 | REG_TYPE_CP, | |
436 | REG_TYPE_CN, | |
437 | REG_TYPE_FN, | |
438 | REG_TYPE_VFS, | |
439 | REG_TYPE_VFD, | |
5287ad62 | 440 | REG_TYPE_NQ, |
037e8744 | 441 | REG_TYPE_VFSD, |
5287ad62 | 442 | REG_TYPE_NDQ, |
037e8744 | 443 | REG_TYPE_NSDQ, |
c19d1205 ZW |
444 | REG_TYPE_VFC, |
445 | REG_TYPE_MVF, | |
446 | REG_TYPE_MVD, | |
447 | REG_TYPE_MVFX, | |
448 | REG_TYPE_MVDX, | |
449 | REG_TYPE_MVAX, | |
450 | REG_TYPE_DSPSC, | |
451 | REG_TYPE_MMXWR, | |
452 | REG_TYPE_MMXWC, | |
453 | REG_TYPE_MMXWCG, | |
454 | REG_TYPE_XSCALE, | |
bfae80f2 RE |
455 | }; |
456 | ||
dcbf9037 JB |
457 | /* Structure for a hash table entry for a register. |
458 | If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra | |
459 | information which states whether a vector type or index is specified (for a | |
460 | register alias created with .dn or .qn). Otherwise NEON should be NULL. */ | |
6c43fab6 RE |
461 | struct reg_entry |
462 | { | |
dcbf9037 JB |
463 | const char *name; |
464 | unsigned char number; | |
465 | unsigned char type; | |
466 | unsigned char builtin; | |
467 | struct neon_typed_alias *neon; | |
6c43fab6 RE |
468 | }; |
469 | ||
c19d1205 ZW |
470 | /* Diagnostics used when we don't get a register of the expected type. */ |
471 | const char *const reg_expected_msgs[] = | |
472 | { | |
473 | N_("ARM register expected"), | |
474 | N_("bad or missing co-processor number"), | |
475 | N_("co-processor register expected"), | |
476 | N_("FPA register expected"), | |
477 | N_("VFP single precision register expected"), | |
5287ad62 JB |
478 | N_("VFP/Neon double precision register expected"), |
479 | N_("Neon quad precision register expected"), | |
037e8744 | 480 | N_("VFP single or double precision register expected"), |
5287ad62 | 481 | N_("Neon double or quad precision register expected"), |
037e8744 | 482 | N_("VFP single, double or Neon quad precision register expected"), |
c19d1205 ZW |
483 | N_("VFP system register expected"), |
484 | N_("Maverick MVF register expected"), | |
485 | N_("Maverick MVD register expected"), | |
486 | N_("Maverick MVFX register expected"), | |
487 | N_("Maverick MVDX register expected"), | |
488 | N_("Maverick MVAX register expected"), | |
489 | N_("Maverick DSPSC register expected"), | |
490 | N_("iWMMXt data register expected"), | |
491 | N_("iWMMXt control register expected"), | |
492 | N_("iWMMXt scalar register expected"), | |
493 | N_("XScale accumulator register expected"), | |
6c43fab6 RE |
494 | }; |
495 | ||
c19d1205 ZW |
496 | /* Some well known registers that we refer to directly elsewhere. */ |
497 | #define REG_SP 13 | |
498 | #define REG_LR 14 | |
499 | #define REG_PC 15 | |
404ff6b5 | 500 | |
b99bd4ef NC |
501 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
502 | take 2: */ | |
c19d1205 | 503 | #define INSN_SIZE 4 |
b99bd4ef NC |
504 | |
505 | struct asm_opcode | |
506 | { | |
507 | /* Basic string to match. */ | |
c19d1205 ZW |
508 | const char *template; |
509 | ||
510 | /* Parameters to instruction. */ | |
511 | unsigned char operands[8]; | |
512 | ||
513 | /* Conditional tag - see opcode_lookup. */ | |
514 | unsigned int tag : 4; | |
b99bd4ef NC |
515 | |
516 | /* Basic instruction code. */ | |
c19d1205 | 517 | unsigned int avalue : 28; |
b99bd4ef | 518 | |
c19d1205 ZW |
519 | /* Thumb-format instruction code. */ |
520 | unsigned int tvalue; | |
b99bd4ef | 521 | |
90e4755a | 522 | /* Which architecture variant provides this instruction. */ |
e74cfd16 PB |
523 | const arm_feature_set *avariant; |
524 | const arm_feature_set *tvariant; | |
c19d1205 ZW |
525 | |
526 | /* Function to call to encode instruction in ARM format. */ | |
527 | void (* aencode) (void); | |
b99bd4ef | 528 | |
c19d1205 ZW |
529 | /* Function to call to encode instruction in Thumb format. */ |
530 | void (* tencode) (void); | |
b99bd4ef NC |
531 | }; |
532 | ||
a737bd4d NC |
533 | /* Defines for various bits that we will want to toggle. */ |
534 | #define INST_IMMEDIATE 0x02000000 | |
535 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 536 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
537 | #define SHIFT_BY_REG 0x00000010 |
538 | #define PRE_INDEX 0x01000000 | |
539 | #define INDEX_UP 0x00800000 | |
540 | #define WRITE_BACK 0x00200000 | |
541 | #define LDM_TYPE_2_OR_3 0x00400000 | |
90e4755a | 542 | |
a737bd4d NC |
543 | #define LITERAL_MASK 0xf000f000 |
544 | #define OPCODE_MASK 0xfe1fffff | |
545 | #define V4_STR_BIT 0x00000020 | |
90e4755a | 546 | |
a737bd4d | 547 | #define DATA_OP_SHIFT 21 |
90e4755a | 548 | |
ef8d22e6 PB |
549 | #define T2_OPCODE_MASK 0xfe1fffff |
550 | #define T2_DATA_OP_SHIFT 21 | |
551 | ||
a737bd4d NC |
552 | /* Codes to distinguish the arithmetic instructions. */ |
553 | #define OPCODE_AND 0 | |
554 | #define OPCODE_EOR 1 | |
555 | #define OPCODE_SUB 2 | |
556 | #define OPCODE_RSB 3 | |
557 | #define OPCODE_ADD 4 | |
558 | #define OPCODE_ADC 5 | |
559 | #define OPCODE_SBC 6 | |
560 | #define OPCODE_RSC 7 | |
561 | #define OPCODE_TST 8 | |
562 | #define OPCODE_TEQ 9 | |
563 | #define OPCODE_CMP 10 | |
564 | #define OPCODE_CMN 11 | |
565 | #define OPCODE_ORR 12 | |
566 | #define OPCODE_MOV 13 | |
567 | #define OPCODE_BIC 14 | |
568 | #define OPCODE_MVN 15 | |
90e4755a | 569 | |
ef8d22e6 PB |
570 | #define T2_OPCODE_AND 0 |
571 | #define T2_OPCODE_BIC 1 | |
572 | #define T2_OPCODE_ORR 2 | |
573 | #define T2_OPCODE_ORN 3 | |
574 | #define T2_OPCODE_EOR 4 | |
575 | #define T2_OPCODE_ADD 8 | |
576 | #define T2_OPCODE_ADC 10 | |
577 | #define T2_OPCODE_SBC 11 | |
578 | #define T2_OPCODE_SUB 13 | |
579 | #define T2_OPCODE_RSB 14 | |
580 | ||
a737bd4d NC |
581 | #define T_OPCODE_MUL 0x4340 |
582 | #define T_OPCODE_TST 0x4200 | |
583 | #define T_OPCODE_CMN 0x42c0 | |
584 | #define T_OPCODE_NEG 0x4240 | |
585 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 586 | |
a737bd4d NC |
587 | #define T_OPCODE_ADD_R3 0x1800 |
588 | #define T_OPCODE_SUB_R3 0x1a00 | |
589 | #define T_OPCODE_ADD_HI 0x4400 | |
590 | #define T_OPCODE_ADD_ST 0xb000 | |
591 | #define T_OPCODE_SUB_ST 0xb080 | |
592 | #define T_OPCODE_ADD_SP 0xa800 | |
593 | #define T_OPCODE_ADD_PC 0xa000 | |
594 | #define T_OPCODE_ADD_I8 0x3000 | |
595 | #define T_OPCODE_SUB_I8 0x3800 | |
596 | #define T_OPCODE_ADD_I3 0x1c00 | |
597 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 598 | |
a737bd4d NC |
599 | #define T_OPCODE_ASR_R 0x4100 |
600 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
601 | #define T_OPCODE_LSR_R 0x40c0 |
602 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
603 | #define T_OPCODE_ASR_I 0x1000 |
604 | #define T_OPCODE_LSL_I 0x0000 | |
605 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 606 | |
a737bd4d NC |
607 | #define T_OPCODE_MOV_I8 0x2000 |
608 | #define T_OPCODE_CMP_I8 0x2800 | |
609 | #define T_OPCODE_CMP_LR 0x4280 | |
610 | #define T_OPCODE_MOV_HR 0x4600 | |
611 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 612 | |
a737bd4d NC |
613 | #define T_OPCODE_LDR_PC 0x4800 |
614 | #define T_OPCODE_LDR_SP 0x9800 | |
615 | #define T_OPCODE_STR_SP 0x9000 | |
616 | #define T_OPCODE_LDR_IW 0x6800 | |
617 | #define T_OPCODE_STR_IW 0x6000 | |
618 | #define T_OPCODE_LDR_IH 0x8800 | |
619 | #define T_OPCODE_STR_IH 0x8000 | |
620 | #define T_OPCODE_LDR_IB 0x7800 | |
621 | #define T_OPCODE_STR_IB 0x7000 | |
622 | #define T_OPCODE_LDR_RW 0x5800 | |
623 | #define T_OPCODE_STR_RW 0x5000 | |
624 | #define T_OPCODE_LDR_RH 0x5a00 | |
625 | #define T_OPCODE_STR_RH 0x5200 | |
626 | #define T_OPCODE_LDR_RB 0x5c00 | |
627 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 628 | |
a737bd4d NC |
629 | #define T_OPCODE_PUSH 0xb400 |
630 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 631 | |
2fc8bdac | 632 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 633 | |
a737bd4d | 634 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 635 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 | 636 | #define THUMB_LOAD_BIT 0x0800 |
53365c0d | 637 | #define THUMB2_LOAD_BIT 0x00100000 |
c19d1205 ZW |
638 | |
639 | #define BAD_ARGS _("bad arguments to instruction") | |
640 | #define BAD_PC _("r15 not allowed here") | |
641 | #define BAD_COND _("instruction cannot be conditional") | |
642 | #define BAD_OVERLAP _("registers may not be the same") | |
643 | #define BAD_HIREG _("lo register required") | |
644 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
01cfc07f | 645 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); |
dfa9f0d5 PB |
646 | #define BAD_BRANCH _("branch must be last instruction in IT block") |
647 | #define BAD_NOT_IT _("instruction not allowed in IT block") | |
037e8744 | 648 | #define BAD_FPU _("selected FPU does not support instruction") |
c19d1205 ZW |
649 | |
650 | static struct hash_control *arm_ops_hsh; | |
651 | static struct hash_control *arm_cond_hsh; | |
652 | static struct hash_control *arm_shift_hsh; | |
653 | static struct hash_control *arm_psr_hsh; | |
62b3e311 | 654 | static struct hash_control *arm_v7m_psr_hsh; |
c19d1205 ZW |
655 | static struct hash_control *arm_reg_hsh; |
656 | static struct hash_control *arm_reloc_hsh; | |
62b3e311 | 657 | static struct hash_control *arm_barrier_opt_hsh; |
b99bd4ef | 658 | |
b99bd4ef NC |
659 | /* Stuff needed to resolve the label ambiguity |
660 | As: | |
661 | ... | |
662 | label: <insn> | |
663 | may differ from: | |
664 | ... | |
665 | label: | |
c19d1205 | 666 | <insn> |
b99bd4ef NC |
667 | */ |
668 | ||
669 | symbolS * last_label_seen; | |
b34976b6 | 670 | static int label_is_thumb_function_name = FALSE; |
a737bd4d | 671 | \f |
3d0c9500 NC |
672 | /* Literal pool structure. Held on a per-section |
673 | and per-sub-section basis. */ | |
a737bd4d | 674 | |
c19d1205 | 675 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 676 | typedef struct literal_pool |
b99bd4ef | 677 | { |
c19d1205 ZW |
678 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
679 | unsigned int next_free_entry; | |
680 | unsigned int id; | |
681 | symbolS * symbol; | |
682 | segT section; | |
683 | subsegT sub_section; | |
61b5f74b | 684 | struct literal_pool * next; |
3d0c9500 | 685 | } literal_pool; |
b99bd4ef | 686 | |
3d0c9500 NC |
687 | /* Pointer to a linked list of literal pools. */ |
688 | literal_pool * list_of_pools = NULL; | |
e27ec89e PB |
689 | |
690 | /* State variables for IT block handling. */ | |
691 | static bfd_boolean current_it_mask = 0; | |
692 | static int current_cc; | |
693 | ||
c19d1205 ZW |
694 | \f |
695 | /* Pure syntax. */ | |
b99bd4ef | 696 | |
c19d1205 ZW |
697 | /* This array holds the chars that always start a comment. If the |
698 | pre-processor is disabled, these aren't very useful. */ | |
699 | const char comment_chars[] = "@"; | |
3d0c9500 | 700 | |
c19d1205 ZW |
701 | /* This array holds the chars that only start a comment at the beginning of |
702 | a line. If the line seems to have the form '# 123 filename' | |
703 | .line and .file directives will appear in the pre-processed output. */ | |
704 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
705 | first line of the input file. This is because the compiler outputs | |
706 | #NO_APP at the beginning of its output. */ | |
707 | /* Also note that comments like this one will always work. */ | |
708 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 709 | |
c19d1205 | 710 | const char line_separator_chars[] = ";"; |
b99bd4ef | 711 | |
c19d1205 ZW |
712 | /* Chars that can be used to separate mant |
713 | from exp in floating point numbers. */ | |
714 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 715 | |
c19d1205 ZW |
716 | /* Chars that mean this number is a floating point constant. */ |
717 | /* As in 0f12.456 */ | |
718 | /* or 0d1.2345e12 */ | |
b99bd4ef | 719 | |
c19d1205 | 720 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 721 | |
c19d1205 ZW |
722 | /* Prefix characters that indicate the start of an immediate |
723 | value. */ | |
724 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 725 | |
c19d1205 ZW |
726 | /* Separator character handling. */ |
727 | ||
728 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
729 | ||
730 | static inline int | |
731 | skip_past_char (char ** str, char c) | |
732 | { | |
733 | if (**str == c) | |
734 | { | |
735 | (*str)++; | |
736 | return SUCCESS; | |
3d0c9500 | 737 | } |
c19d1205 ZW |
738 | else |
739 | return FAIL; | |
740 | } | |
741 | #define skip_past_comma(str) skip_past_char (str, ',') | |
3d0c9500 | 742 | |
c19d1205 ZW |
743 | /* Arithmetic expressions (possibly involving symbols). */ |
744 | ||
745 | /* Return TRUE if anything in the expression is a bignum. */ | |
746 | ||
747 | static int | |
748 | walk_no_bignums (symbolS * sp) | |
749 | { | |
750 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
751 | return 1; | |
752 | ||
753 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 754 | { |
c19d1205 ZW |
755 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
756 | || (symbol_get_value_expression (sp)->X_op_symbol | |
757 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
758 | } |
759 | ||
c19d1205 | 760 | return 0; |
3d0c9500 NC |
761 | } |
762 | ||
c19d1205 ZW |
763 | static int in_my_get_expression = 0; |
764 | ||
765 | /* Third argument to my_get_expression. */ | |
766 | #define GE_NO_PREFIX 0 | |
767 | #define GE_IMM_PREFIX 1 | |
768 | #define GE_OPT_PREFIX 2 | |
5287ad62 JB |
769 | /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) |
770 | immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ | |
771 | #define GE_OPT_PREFIX_BIG 3 | |
a737bd4d | 772 | |
b99bd4ef | 773 | static int |
c19d1205 | 774 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 775 | { |
c19d1205 ZW |
776 | char * save_in; |
777 | segT seg; | |
b99bd4ef | 778 | |
c19d1205 ZW |
779 | /* In unified syntax, all prefixes are optional. */ |
780 | if (unified_syntax) | |
5287ad62 JB |
781 | prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode |
782 | : GE_OPT_PREFIX; | |
b99bd4ef | 783 | |
c19d1205 | 784 | switch (prefix_mode) |
b99bd4ef | 785 | { |
c19d1205 ZW |
786 | case GE_NO_PREFIX: break; |
787 | case GE_IMM_PREFIX: | |
788 | if (!is_immediate_prefix (**str)) | |
789 | { | |
790 | inst.error = _("immediate expression requires a # prefix"); | |
791 | return FAIL; | |
792 | } | |
793 | (*str)++; | |
794 | break; | |
795 | case GE_OPT_PREFIX: | |
5287ad62 | 796 | case GE_OPT_PREFIX_BIG: |
c19d1205 ZW |
797 | if (is_immediate_prefix (**str)) |
798 | (*str)++; | |
799 | break; | |
800 | default: abort (); | |
801 | } | |
b99bd4ef | 802 | |
c19d1205 | 803 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 804 | |
c19d1205 ZW |
805 | save_in = input_line_pointer; |
806 | input_line_pointer = *str; | |
807 | in_my_get_expression = 1; | |
808 | seg = expression (ep); | |
809 | in_my_get_expression = 0; | |
810 | ||
811 | if (ep->X_op == O_illegal) | |
b99bd4ef | 812 | { |
c19d1205 ZW |
813 | /* We found a bad expression in md_operand(). */ |
814 | *str = input_line_pointer; | |
815 | input_line_pointer = save_in; | |
816 | if (inst.error == NULL) | |
817 | inst.error = _("bad expression"); | |
818 | return 1; | |
819 | } | |
b99bd4ef | 820 | |
c19d1205 ZW |
821 | #ifdef OBJ_AOUT |
822 | if (seg != absolute_section | |
823 | && seg != text_section | |
824 | && seg != data_section | |
825 | && seg != bss_section | |
826 | && seg != undefined_section) | |
827 | { | |
828 | inst.error = _("bad segment"); | |
829 | *str = input_line_pointer; | |
830 | input_line_pointer = save_in; | |
831 | return 1; | |
b99bd4ef | 832 | } |
c19d1205 | 833 | #endif |
b99bd4ef | 834 | |
c19d1205 ZW |
835 | /* Get rid of any bignums now, so that we don't generate an error for which |
836 | we can't establish a line number later on. Big numbers are never valid | |
837 | in instructions, which is where this routine is always called. */ | |
5287ad62 JB |
838 | if (prefix_mode != GE_OPT_PREFIX_BIG |
839 | && (ep->X_op == O_big | |
840 | || (ep->X_add_symbol | |
841 | && (walk_no_bignums (ep->X_add_symbol) | |
842 | || (ep->X_op_symbol | |
843 | && walk_no_bignums (ep->X_op_symbol)))))) | |
c19d1205 ZW |
844 | { |
845 | inst.error = _("invalid constant"); | |
846 | *str = input_line_pointer; | |
847 | input_line_pointer = save_in; | |
848 | return 1; | |
849 | } | |
b99bd4ef | 850 | |
c19d1205 ZW |
851 | *str = input_line_pointer; |
852 | input_line_pointer = save_in; | |
853 | return 0; | |
b99bd4ef NC |
854 | } |
855 | ||
c19d1205 ZW |
856 | /* Turn a string in input_line_pointer into a floating point constant |
857 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
858 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
859 | returned, or NULL on OK. | |
b99bd4ef | 860 | |
c19d1205 ZW |
861 | Note that fp constants aren't represent in the normal way on the ARM. |
862 | In big endian mode, things are as expected. However, in little endian | |
863 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
864 | within the words. For example, (double) 1.1 in big endian mode is | |
865 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
866 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 867 | |
c19d1205 | 868 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 869 | |
c19d1205 ZW |
870 | char * |
871 | md_atof (int type, char * litP, int * sizeP) | |
872 | { | |
873 | int prec; | |
874 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
875 | char *t; | |
876 | int i; | |
b99bd4ef | 877 | |
c19d1205 ZW |
878 | switch (type) |
879 | { | |
880 | case 'f': | |
881 | case 'F': | |
882 | case 's': | |
883 | case 'S': | |
884 | prec = 2; | |
885 | break; | |
b99bd4ef | 886 | |
c19d1205 ZW |
887 | case 'd': |
888 | case 'D': | |
889 | case 'r': | |
890 | case 'R': | |
891 | prec = 4; | |
892 | break; | |
b99bd4ef | 893 | |
c19d1205 ZW |
894 | case 'x': |
895 | case 'X': | |
896 | prec = 6; | |
897 | break; | |
b99bd4ef | 898 | |
c19d1205 ZW |
899 | case 'p': |
900 | case 'P': | |
901 | prec = 6; | |
902 | break; | |
a737bd4d | 903 | |
c19d1205 ZW |
904 | default: |
905 | *sizeP = 0; | |
906 | return _("bad call to MD_ATOF()"); | |
907 | } | |
b99bd4ef | 908 | |
c19d1205 ZW |
909 | t = atof_ieee (input_line_pointer, type, words); |
910 | if (t) | |
911 | input_line_pointer = t; | |
912 | *sizeP = prec * 2; | |
b99bd4ef | 913 | |
c19d1205 ZW |
914 | if (target_big_endian) |
915 | { | |
916 | for (i = 0; i < prec; i++) | |
917 | { | |
918 | md_number_to_chars (litP, (valueT) words[i], 2); | |
919 | litP += 2; | |
920 | } | |
921 | } | |
922 | else | |
923 | { | |
e74cfd16 | 924 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
c19d1205 ZW |
925 | for (i = prec - 1; i >= 0; i--) |
926 | { | |
927 | md_number_to_chars (litP, (valueT) words[i], 2); | |
928 | litP += 2; | |
929 | } | |
930 | else | |
931 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
932 | For an 8 byte float the order is 1 0 3 2. */ | |
933 | for (i = 0; i < prec; i += 2) | |
934 | { | |
935 | md_number_to_chars (litP, (valueT) words[i + 1], 2); | |
936 | md_number_to_chars (litP + 2, (valueT) words[i], 2); | |
937 | litP += 4; | |
938 | } | |
939 | } | |
b99bd4ef | 940 | |
c19d1205 ZW |
941 | return 0; |
942 | } | |
b99bd4ef | 943 | |
c19d1205 ZW |
944 | /* We handle all bad expressions here, so that we can report the faulty |
945 | instruction in the error message. */ | |
946 | void | |
947 | md_operand (expressionS * expr) | |
948 | { | |
949 | if (in_my_get_expression) | |
950 | expr->X_op = O_illegal; | |
b99bd4ef NC |
951 | } |
952 | ||
c19d1205 | 953 | /* Immediate values. */ |
b99bd4ef | 954 | |
c19d1205 ZW |
955 | /* Generic immediate-value read function for use in directives. |
956 | Accepts anything that 'expression' can fold to a constant. | |
957 | *val receives the number. */ | |
958 | #ifdef OBJ_ELF | |
959 | static int | |
960 | immediate_for_directive (int *val) | |
b99bd4ef | 961 | { |
c19d1205 ZW |
962 | expressionS exp; |
963 | exp.X_op = O_illegal; | |
b99bd4ef | 964 | |
c19d1205 ZW |
965 | if (is_immediate_prefix (*input_line_pointer)) |
966 | { | |
967 | input_line_pointer++; | |
968 | expression (&exp); | |
969 | } | |
b99bd4ef | 970 | |
c19d1205 ZW |
971 | if (exp.X_op != O_constant) |
972 | { | |
973 | as_bad (_("expected #constant")); | |
974 | ignore_rest_of_line (); | |
975 | return FAIL; | |
976 | } | |
977 | *val = exp.X_add_number; | |
978 | return SUCCESS; | |
b99bd4ef | 979 | } |
c19d1205 | 980 | #endif |
b99bd4ef | 981 | |
c19d1205 | 982 | /* Register parsing. */ |
b99bd4ef | 983 | |
c19d1205 ZW |
984 | /* Generic register parser. CCP points to what should be the |
985 | beginning of a register name. If it is indeed a valid register | |
986 | name, advance CCP over it and return the reg_entry structure; | |
987 | otherwise return NULL. Does not issue diagnostics. */ | |
988 | ||
989 | static struct reg_entry * | |
990 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 991 | { |
c19d1205 ZW |
992 | char *start = *ccp; |
993 | char *p; | |
994 | struct reg_entry *reg; | |
b99bd4ef | 995 | |
c19d1205 ZW |
996 | #ifdef REGISTER_PREFIX |
997 | if (*start != REGISTER_PREFIX) | |
01cfc07f | 998 | return NULL; |
c19d1205 ZW |
999 | start++; |
1000 | #endif | |
1001 | #ifdef OPTIONAL_REGISTER_PREFIX | |
1002 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
1003 | start++; | |
1004 | #endif | |
b99bd4ef | 1005 | |
c19d1205 ZW |
1006 | p = start; |
1007 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
1008 | return NULL; | |
b99bd4ef | 1009 | |
c19d1205 ZW |
1010 | do |
1011 | p++; | |
1012 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
1013 | ||
1014 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
1015 | ||
1016 | if (!reg) | |
1017 | return NULL; | |
1018 | ||
1019 | *ccp = p; | |
1020 | return reg; | |
b99bd4ef NC |
1021 | } |
1022 | ||
1023 | static int | |
dcbf9037 JB |
1024 | arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, |
1025 | enum arm_reg_type type) | |
b99bd4ef | 1026 | { |
c19d1205 ZW |
1027 | /* Alternative syntaxes are accepted for a few register classes. */ |
1028 | switch (type) | |
1029 | { | |
1030 | case REG_TYPE_MVF: | |
1031 | case REG_TYPE_MVD: | |
1032 | case REG_TYPE_MVFX: | |
1033 | case REG_TYPE_MVDX: | |
1034 | /* Generic coprocessor register names are allowed for these. */ | |
79134647 | 1035 | if (reg && reg->type == REG_TYPE_CN) |
c19d1205 ZW |
1036 | return reg->number; |
1037 | break; | |
69b97547 | 1038 | |
c19d1205 ZW |
1039 | case REG_TYPE_CP: |
1040 | /* For backward compatibility, a bare number is valid here. */ | |
1041 | { | |
1042 | unsigned long processor = strtoul (start, ccp, 10); | |
1043 | if (*ccp != start && processor <= 15) | |
1044 | return processor; | |
1045 | } | |
6057a28f | 1046 | |
c19d1205 ZW |
1047 | case REG_TYPE_MMXWC: |
1048 | /* WC includes WCG. ??? I'm not sure this is true for all | |
1049 | instructions that take WC registers. */ | |
79134647 | 1050 | if (reg && reg->type == REG_TYPE_MMXWCG) |
c19d1205 | 1051 | return reg->number; |
6057a28f | 1052 | break; |
c19d1205 | 1053 | |
6057a28f | 1054 | default: |
c19d1205 | 1055 | break; |
6057a28f NC |
1056 | } |
1057 | ||
dcbf9037 JB |
1058 | return FAIL; |
1059 | } | |
1060 | ||
1061 | /* As arm_reg_parse_multi, but the register must be of type TYPE, and the | |
1062 | return value is the register number or FAIL. */ | |
1063 | ||
1064 | static int | |
1065 | arm_reg_parse (char **ccp, enum arm_reg_type type) | |
1066 | { | |
1067 | char *start = *ccp; | |
1068 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
1069 | int ret; | |
1070 | ||
1071 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1072 | if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) | |
1073 | return FAIL; | |
1074 | ||
1075 | if (reg && reg->type == type) | |
1076 | return reg->number; | |
1077 | ||
1078 | if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) | |
1079 | return ret; | |
1080 | ||
c19d1205 ZW |
1081 | *ccp = start; |
1082 | return FAIL; | |
1083 | } | |
69b97547 | 1084 | |
dcbf9037 JB |
1085 | /* Parse a Neon type specifier. *STR should point at the leading '.' |
1086 | character. Does no verification at this stage that the type fits the opcode | |
1087 | properly. E.g., | |
1088 | ||
1089 | .i32.i32.s16 | |
1090 | .s32.f32 | |
1091 | .u16 | |
1092 | ||
1093 | Can all be legally parsed by this function. | |
1094 | ||
1095 | Fills in neon_type struct pointer with parsed information, and updates STR | |
1096 | to point after the parsed type specifier. Returns SUCCESS if this was a legal | |
1097 | type, FAIL if not. */ | |
1098 | ||
1099 | static int | |
1100 | parse_neon_type (struct neon_type *type, char **str) | |
1101 | { | |
1102 | char *ptr = *str; | |
1103 | ||
1104 | if (type) | |
1105 | type->elems = 0; | |
1106 | ||
1107 | while (type->elems < NEON_MAX_TYPE_ELS) | |
1108 | { | |
1109 | enum neon_el_type thistype = NT_untyped; | |
1110 | unsigned thissize = -1u; | |
1111 | ||
1112 | if (*ptr != '.') | |
1113 | break; | |
1114 | ||
1115 | ptr++; | |
1116 | ||
1117 | /* Just a size without an explicit type. */ | |
1118 | if (ISDIGIT (*ptr)) | |
1119 | goto parsesize; | |
1120 | ||
1121 | switch (TOLOWER (*ptr)) | |
1122 | { | |
1123 | case 'i': thistype = NT_integer; break; | |
1124 | case 'f': thistype = NT_float; break; | |
1125 | case 'p': thistype = NT_poly; break; | |
1126 | case 's': thistype = NT_signed; break; | |
1127 | case 'u': thistype = NT_unsigned; break; | |
037e8744 JB |
1128 | case 'd': |
1129 | thistype = NT_float; | |
1130 | thissize = 64; | |
1131 | ptr++; | |
1132 | goto done; | |
dcbf9037 JB |
1133 | default: |
1134 | as_bad (_("unexpected character `%c' in type specifier"), *ptr); | |
1135 | return FAIL; | |
1136 | } | |
1137 | ||
1138 | ptr++; | |
1139 | ||
1140 | /* .f is an abbreviation for .f32. */ | |
1141 | if (thistype == NT_float && !ISDIGIT (*ptr)) | |
1142 | thissize = 32; | |
1143 | else | |
1144 | { | |
1145 | parsesize: | |
1146 | thissize = strtoul (ptr, &ptr, 10); | |
1147 | ||
1148 | if (thissize != 8 && thissize != 16 && thissize != 32 | |
1149 | && thissize != 64) | |
1150 | { | |
1151 | as_bad (_("bad size %d in type specifier"), thissize); | |
1152 | return FAIL; | |
1153 | } | |
1154 | } | |
1155 | ||
037e8744 | 1156 | done: |
dcbf9037 JB |
1157 | if (type) |
1158 | { | |
1159 | type->el[type->elems].type = thistype; | |
1160 | type->el[type->elems].size = thissize; | |
1161 | type->elems++; | |
1162 | } | |
1163 | } | |
1164 | ||
1165 | /* Empty/missing type is not a successful parse. */ | |
1166 | if (type->elems == 0) | |
1167 | return FAIL; | |
1168 | ||
1169 | *str = ptr; | |
1170 | ||
1171 | return SUCCESS; | |
1172 | } | |
1173 | ||
1174 | /* Errors may be set multiple times during parsing or bit encoding | |
1175 | (particularly in the Neon bits), but usually the earliest error which is set | |
1176 | will be the most meaningful. Avoid overwriting it with later (cascading) | |
1177 | errors by calling this function. */ | |
1178 | ||
1179 | static void | |
1180 | first_error (const char *err) | |
1181 | { | |
1182 | if (!inst.error) | |
1183 | inst.error = err; | |
1184 | } | |
1185 | ||
1186 | /* Parse a single type, e.g. ".s32", leading period included. */ | |
1187 | static int | |
1188 | parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) | |
1189 | { | |
1190 | char *str = *ccp; | |
1191 | struct neon_type optype; | |
1192 | ||
1193 | if (*str == '.') | |
1194 | { | |
1195 | if (parse_neon_type (&optype, &str) == SUCCESS) | |
1196 | { | |
1197 | if (optype.elems == 1) | |
1198 | *vectype = optype.el[0]; | |
1199 | else | |
1200 | { | |
1201 | first_error (_("only one type should be specified for operand")); | |
1202 | return FAIL; | |
1203 | } | |
1204 | } | |
1205 | else | |
1206 | { | |
1207 | first_error (_("vector type expected")); | |
1208 | return FAIL; | |
1209 | } | |
1210 | } | |
1211 | else | |
1212 | return FAIL; | |
1213 | ||
1214 | *ccp = str; | |
1215 | ||
1216 | return SUCCESS; | |
1217 | } | |
1218 | ||
1219 | /* Special meanings for indices (which have a range of 0-7), which will fit into | |
1220 | a 4-bit integer. */ | |
1221 | ||
1222 | #define NEON_ALL_LANES 15 | |
1223 | #define NEON_INTERLEAVE_LANES 14 | |
1224 | ||
1225 | /* Parse either a register or a scalar, with an optional type. Return the | |
1226 | register number, and optionally fill in the actual type of the register | |
1227 | when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and | |
1228 | type/index information in *TYPEINFO. */ | |
1229 | ||
1230 | static int | |
1231 | parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, | |
1232 | enum arm_reg_type *rtype, | |
1233 | struct neon_typed_alias *typeinfo) | |
1234 | { | |
1235 | char *str = *ccp; | |
1236 | struct reg_entry *reg = arm_reg_parse_multi (&str); | |
1237 | struct neon_typed_alias atype; | |
1238 | struct neon_type_el parsetype; | |
1239 | ||
1240 | atype.defined = 0; | |
1241 | atype.index = -1; | |
1242 | atype.eltype.type = NT_invtype; | |
1243 | atype.eltype.size = -1; | |
1244 | ||
1245 | /* Try alternate syntax for some types of register. Note these are mutually | |
1246 | exclusive with the Neon syntax extensions. */ | |
1247 | if (reg == NULL) | |
1248 | { | |
1249 | int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); | |
1250 | if (altreg != FAIL) | |
1251 | *ccp = str; | |
1252 | if (typeinfo) | |
1253 | *typeinfo = atype; | |
1254 | return altreg; | |
1255 | } | |
1256 | ||
037e8744 JB |
1257 | /* Undo polymorphism when a set of register types may be accepted. */ |
1258 | if ((type == REG_TYPE_NDQ | |
1259 | && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) | |
1260 | || (type == REG_TYPE_VFSD | |
1261 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) | |
1262 | || (type == REG_TYPE_NSDQ | |
1263 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD | |
1264 | || reg->type == REG_TYPE_NQ))) | |
dcbf9037 JB |
1265 | type = reg->type; |
1266 | ||
1267 | if (type != reg->type) | |
1268 | return FAIL; | |
1269 | ||
1270 | if (reg->neon) | |
1271 | atype = *reg->neon; | |
1272 | ||
1273 | if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) | |
1274 | { | |
1275 | if ((atype.defined & NTA_HASTYPE) != 0) | |
1276 | { | |
1277 | first_error (_("can't redefine type for operand")); | |
1278 | return FAIL; | |
1279 | } | |
1280 | atype.defined |= NTA_HASTYPE; | |
1281 | atype.eltype = parsetype; | |
1282 | } | |
1283 | ||
1284 | if (skip_past_char (&str, '[') == SUCCESS) | |
1285 | { | |
1286 | if (type != REG_TYPE_VFD) | |
1287 | { | |
1288 | first_error (_("only D registers may be indexed")); | |
1289 | return FAIL; | |
1290 | } | |
1291 | ||
1292 | if ((atype.defined & NTA_HASINDEX) != 0) | |
1293 | { | |
1294 | first_error (_("can't change index for operand")); | |
1295 | return FAIL; | |
1296 | } | |
1297 | ||
1298 | atype.defined |= NTA_HASINDEX; | |
1299 | ||
1300 | if (skip_past_char (&str, ']') == SUCCESS) | |
1301 | atype.index = NEON_ALL_LANES; | |
1302 | else | |
1303 | { | |
1304 | expressionS exp; | |
1305 | ||
1306 | my_get_expression (&exp, &str, GE_NO_PREFIX); | |
1307 | ||
1308 | if (exp.X_op != O_constant) | |
1309 | { | |
1310 | first_error (_("constant expression required")); | |
1311 | return FAIL; | |
1312 | } | |
1313 | ||
1314 | if (skip_past_char (&str, ']') == FAIL) | |
1315 | return FAIL; | |
1316 | ||
1317 | atype.index = exp.X_add_number; | |
1318 | } | |
1319 | } | |
1320 | ||
1321 | if (typeinfo) | |
1322 | *typeinfo = atype; | |
1323 | ||
1324 | if (rtype) | |
1325 | *rtype = type; | |
1326 | ||
1327 | *ccp = str; | |
1328 | ||
1329 | return reg->number; | |
1330 | } | |
1331 | ||
1332 | /* Like arm_reg_parse, but allow allow the following extra features: | |
1333 | - If RTYPE is non-zero, return the (possibly restricted) type of the | |
1334 | register (e.g. Neon double or quad reg when either has been requested). | |
1335 | - If this is a Neon vector type with additional type information, fill | |
1336 | in the struct pointed to by VECTYPE (if non-NULL). | |
1337 | This function will fault on encountering a scalar. | |
1338 | */ | |
1339 | ||
1340 | static int | |
1341 | arm_typed_reg_parse (char **ccp, enum arm_reg_type type, | |
1342 | enum arm_reg_type *rtype, struct neon_type_el *vectype) | |
1343 | { | |
1344 | struct neon_typed_alias atype; | |
1345 | char *str = *ccp; | |
1346 | int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); | |
1347 | ||
1348 | if (reg == FAIL) | |
1349 | return FAIL; | |
1350 | ||
1351 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1352 | if ((atype.defined & NTA_HASINDEX) != 0) | |
1353 | { | |
1354 | first_error (_("register operand expected, but got scalar")); | |
1355 | return FAIL; | |
1356 | } | |
1357 | ||
1358 | if (vectype) | |
1359 | *vectype = atype.eltype; | |
1360 | ||
1361 | *ccp = str; | |
1362 | ||
1363 | return reg; | |
1364 | } | |
1365 | ||
1366 | #define NEON_SCALAR_REG(X) ((X) >> 4) | |
1367 | #define NEON_SCALAR_INDEX(X) ((X) & 15) | |
1368 | ||
5287ad62 JB |
1369 | /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't |
1370 | have enough information to be able to do a good job bounds-checking. So, we | |
1371 | just do easy checks here, and do further checks later. */ | |
1372 | ||
1373 | static int | |
dcbf9037 | 1374 | parse_scalar (char **ccp, int elsize, struct neon_type_el *type) |
5287ad62 | 1375 | { |
dcbf9037 | 1376 | int reg; |
5287ad62 | 1377 | char *str = *ccp; |
dcbf9037 | 1378 | struct neon_typed_alias atype; |
5287ad62 | 1379 | |
dcbf9037 | 1380 | reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); |
5287ad62 | 1381 | |
dcbf9037 | 1382 | if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) |
5287ad62 JB |
1383 | return FAIL; |
1384 | ||
dcbf9037 | 1385 | if (atype.index == NEON_ALL_LANES) |
5287ad62 | 1386 | { |
dcbf9037 | 1387 | first_error (_("scalar must have an index")); |
5287ad62 JB |
1388 | return FAIL; |
1389 | } | |
dcbf9037 | 1390 | else if (atype.index >= 64 / elsize) |
5287ad62 | 1391 | { |
dcbf9037 | 1392 | first_error (_("scalar index out of range")); |
5287ad62 JB |
1393 | return FAIL; |
1394 | } | |
1395 | ||
dcbf9037 JB |
1396 | if (type) |
1397 | *type = atype.eltype; | |
5287ad62 | 1398 | |
5287ad62 JB |
1399 | *ccp = str; |
1400 | ||
dcbf9037 | 1401 | return reg * 16 + atype.index; |
5287ad62 JB |
1402 | } |
1403 | ||
c19d1205 ZW |
1404 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
1405 | static long | |
1406 | parse_reg_list (char ** strp) | |
1407 | { | |
1408 | char * str = * strp; | |
1409 | long range = 0; | |
1410 | int another_range; | |
a737bd4d | 1411 | |
c19d1205 ZW |
1412 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
1413 | do | |
6057a28f | 1414 | { |
c19d1205 | 1415 | another_range = 0; |
a737bd4d | 1416 | |
c19d1205 ZW |
1417 | if (*str == '{') |
1418 | { | |
1419 | int in_range = 0; | |
1420 | int cur_reg = -1; | |
a737bd4d | 1421 | |
c19d1205 ZW |
1422 | str++; |
1423 | do | |
1424 | { | |
1425 | int reg; | |
6057a28f | 1426 | |
dcbf9037 | 1427 | if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) |
c19d1205 | 1428 | { |
dcbf9037 | 1429 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 ZW |
1430 | return FAIL; |
1431 | } | |
a737bd4d | 1432 | |
c19d1205 ZW |
1433 | if (in_range) |
1434 | { | |
1435 | int i; | |
a737bd4d | 1436 | |
c19d1205 ZW |
1437 | if (reg <= cur_reg) |
1438 | { | |
dcbf9037 | 1439 | first_error (_("bad range in register list")); |
c19d1205 ZW |
1440 | return FAIL; |
1441 | } | |
40a18ebd | 1442 | |
c19d1205 ZW |
1443 | for (i = cur_reg + 1; i < reg; i++) |
1444 | { | |
1445 | if (range & (1 << i)) | |
1446 | as_tsktsk | |
1447 | (_("Warning: duplicated register (r%d) in register list"), | |
1448 | i); | |
1449 | else | |
1450 | range |= 1 << i; | |
1451 | } | |
1452 | in_range = 0; | |
1453 | } | |
a737bd4d | 1454 | |
c19d1205 ZW |
1455 | if (range & (1 << reg)) |
1456 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
1457 | reg); | |
1458 | else if (reg <= cur_reg) | |
1459 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 1460 | |
c19d1205 ZW |
1461 | range |= 1 << reg; |
1462 | cur_reg = reg; | |
1463 | } | |
1464 | while (skip_past_comma (&str) != FAIL | |
1465 | || (in_range = 1, *str++ == '-')); | |
1466 | str--; | |
a737bd4d | 1467 | |
c19d1205 ZW |
1468 | if (*str++ != '}') |
1469 | { | |
dcbf9037 | 1470 | first_error (_("missing `}'")); |
c19d1205 ZW |
1471 | return FAIL; |
1472 | } | |
1473 | } | |
1474 | else | |
1475 | { | |
1476 | expressionS expr; | |
40a18ebd | 1477 | |
c19d1205 ZW |
1478 | if (my_get_expression (&expr, &str, GE_NO_PREFIX)) |
1479 | return FAIL; | |
40a18ebd | 1480 | |
c19d1205 ZW |
1481 | if (expr.X_op == O_constant) |
1482 | { | |
1483 | if (expr.X_add_number | |
1484 | != (expr.X_add_number & 0x0000ffff)) | |
1485 | { | |
1486 | inst.error = _("invalid register mask"); | |
1487 | return FAIL; | |
1488 | } | |
a737bd4d | 1489 | |
c19d1205 ZW |
1490 | if ((range & expr.X_add_number) != 0) |
1491 | { | |
1492 | int regno = range & expr.X_add_number; | |
a737bd4d | 1493 | |
c19d1205 ZW |
1494 | regno &= -regno; |
1495 | regno = (1 << regno) - 1; | |
1496 | as_tsktsk | |
1497 | (_("Warning: duplicated register (r%d) in register list"), | |
1498 | regno); | |
1499 | } | |
a737bd4d | 1500 | |
c19d1205 ZW |
1501 | range |= expr.X_add_number; |
1502 | } | |
1503 | else | |
1504 | { | |
1505 | if (inst.reloc.type != 0) | |
1506 | { | |
1507 | inst.error = _("expression too complex"); | |
1508 | return FAIL; | |
1509 | } | |
a737bd4d | 1510 | |
c19d1205 ZW |
1511 | memcpy (&inst.reloc.exp, &expr, sizeof (expressionS)); |
1512 | inst.reloc.type = BFD_RELOC_ARM_MULTI; | |
1513 | inst.reloc.pc_rel = 0; | |
1514 | } | |
1515 | } | |
a737bd4d | 1516 | |
c19d1205 ZW |
1517 | if (*str == '|' || *str == '+') |
1518 | { | |
1519 | str++; | |
1520 | another_range = 1; | |
1521 | } | |
a737bd4d | 1522 | } |
c19d1205 | 1523 | while (another_range); |
a737bd4d | 1524 | |
c19d1205 ZW |
1525 | *strp = str; |
1526 | return range; | |
a737bd4d NC |
1527 | } |
1528 | ||
5287ad62 JB |
1529 | /* Types of registers in a list. */ |
1530 | ||
1531 | enum reg_list_els | |
1532 | { | |
1533 | REGLIST_VFP_S, | |
1534 | REGLIST_VFP_D, | |
1535 | REGLIST_NEON_D | |
1536 | }; | |
1537 | ||
c19d1205 ZW |
1538 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1539 | Otherwise return the number of registers, and set PBASE to the first | |
5287ad62 JB |
1540 | register. Parses registers of type ETYPE. |
1541 | If REGLIST_NEON_D is used, several syntax enhancements are enabled: | |
1542 | - Q registers can be used to specify pairs of D registers | |
1543 | - { } can be omitted from around a singleton register list | |
1544 | FIXME: This is not implemented, as it would require backtracking in | |
1545 | some cases, e.g.: | |
1546 | vtbl.8 d3,d4,d5 | |
1547 | This could be done (the meaning isn't really ambiguous), but doesn't | |
1548 | fit in well with the current parsing framework. | |
dcbf9037 JB |
1549 | - 32 D registers may be used (also true for VFPv3). |
1550 | FIXME: Types are ignored in these register lists, which is probably a | |
1551 | bug. */ | |
6057a28f | 1552 | |
c19d1205 | 1553 | static int |
037e8744 | 1554 | parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) |
6057a28f | 1555 | { |
037e8744 | 1556 | char *str = *ccp; |
c19d1205 ZW |
1557 | int base_reg; |
1558 | int new_base; | |
5287ad62 JB |
1559 | enum arm_reg_type regtype = 0; |
1560 | int max_regs = 0; | |
c19d1205 ZW |
1561 | int count = 0; |
1562 | int warned = 0; | |
1563 | unsigned long mask = 0; | |
a737bd4d | 1564 | int i; |
6057a28f | 1565 | |
037e8744 | 1566 | if (*str != '{') |
5287ad62 JB |
1567 | { |
1568 | inst.error = _("expecting {"); | |
1569 | return FAIL; | |
1570 | } | |
6057a28f | 1571 | |
037e8744 | 1572 | str++; |
6057a28f | 1573 | |
5287ad62 | 1574 | switch (etype) |
c19d1205 | 1575 | { |
5287ad62 | 1576 | case REGLIST_VFP_S: |
c19d1205 ZW |
1577 | regtype = REG_TYPE_VFS; |
1578 | max_regs = 32; | |
5287ad62 JB |
1579 | break; |
1580 | ||
1581 | case REGLIST_VFP_D: | |
1582 | regtype = REG_TYPE_VFD; | |
b7fc2769 JB |
1583 | break; |
1584 | ||
1585 | case REGLIST_NEON_D: | |
1586 | regtype = REG_TYPE_NDQ; | |
1587 | break; | |
1588 | } | |
1589 | ||
1590 | if (etype != REGLIST_VFP_S) | |
1591 | { | |
5287ad62 JB |
1592 | /* VFPv3 allows 32 D registers. */ |
1593 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) | |
1594 | { | |
1595 | max_regs = 32; | |
1596 | if (thumb_mode) | |
1597 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
1598 | fpu_vfp_ext_v3); | |
1599 | else | |
1600 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
1601 | fpu_vfp_ext_v3); | |
1602 | } | |
1603 | else | |
1604 | max_regs = 16; | |
c19d1205 | 1605 | } |
6057a28f | 1606 | |
c19d1205 | 1607 | base_reg = max_regs; |
a737bd4d | 1608 | |
c19d1205 ZW |
1609 | do |
1610 | { | |
5287ad62 | 1611 | int setmask = 1, addregs = 1; |
dcbf9037 | 1612 | |
037e8744 | 1613 | new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); |
dcbf9037 | 1614 | |
c19d1205 | 1615 | if (new_base == FAIL) |
a737bd4d | 1616 | { |
dcbf9037 | 1617 | first_error (_(reg_expected_msgs[regtype])); |
c19d1205 ZW |
1618 | return FAIL; |
1619 | } | |
dcbf9037 | 1620 | |
b7fc2769 JB |
1621 | if (new_base >= max_regs) |
1622 | { | |
1623 | first_error (_("register out of range in list")); | |
1624 | return FAIL; | |
1625 | } | |
1626 | ||
5287ad62 JB |
1627 | /* Note: a value of 2 * n is returned for the register Q<n>. */ |
1628 | if (regtype == REG_TYPE_NQ) | |
1629 | { | |
1630 | setmask = 3; | |
1631 | addregs = 2; | |
1632 | } | |
1633 | ||
c19d1205 ZW |
1634 | if (new_base < base_reg) |
1635 | base_reg = new_base; | |
a737bd4d | 1636 | |
5287ad62 | 1637 | if (mask & (setmask << new_base)) |
c19d1205 | 1638 | { |
dcbf9037 | 1639 | first_error (_("invalid register list")); |
c19d1205 | 1640 | return FAIL; |
a737bd4d | 1641 | } |
a737bd4d | 1642 | |
c19d1205 ZW |
1643 | if ((mask >> new_base) != 0 && ! warned) |
1644 | { | |
1645 | as_tsktsk (_("register list not in ascending order")); | |
1646 | warned = 1; | |
1647 | } | |
0bbf2aa4 | 1648 | |
5287ad62 JB |
1649 | mask |= setmask << new_base; |
1650 | count += addregs; | |
0bbf2aa4 | 1651 | |
037e8744 | 1652 | if (*str == '-') /* We have the start of a range expression */ |
c19d1205 ZW |
1653 | { |
1654 | int high_range; | |
0bbf2aa4 | 1655 | |
037e8744 | 1656 | str++; |
0bbf2aa4 | 1657 | |
037e8744 | 1658 | if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) |
dcbf9037 | 1659 | == FAIL) |
c19d1205 ZW |
1660 | { |
1661 | inst.error = gettext (reg_expected_msgs[regtype]); | |
1662 | return FAIL; | |
1663 | } | |
0bbf2aa4 | 1664 | |
b7fc2769 JB |
1665 | if (high_range >= max_regs) |
1666 | { | |
1667 | first_error (_("register out of range in list")); | |
1668 | return FAIL; | |
1669 | } | |
1670 | ||
5287ad62 JB |
1671 | if (regtype == REG_TYPE_NQ) |
1672 | high_range = high_range + 1; | |
1673 | ||
c19d1205 ZW |
1674 | if (high_range <= new_base) |
1675 | { | |
1676 | inst.error = _("register range not in ascending order"); | |
1677 | return FAIL; | |
1678 | } | |
0bbf2aa4 | 1679 | |
5287ad62 | 1680 | for (new_base += addregs; new_base <= high_range; new_base += addregs) |
0bbf2aa4 | 1681 | { |
5287ad62 | 1682 | if (mask & (setmask << new_base)) |
0bbf2aa4 | 1683 | { |
c19d1205 ZW |
1684 | inst.error = _("invalid register list"); |
1685 | return FAIL; | |
0bbf2aa4 | 1686 | } |
c19d1205 | 1687 | |
5287ad62 JB |
1688 | mask |= setmask << new_base; |
1689 | count += addregs; | |
0bbf2aa4 | 1690 | } |
0bbf2aa4 | 1691 | } |
0bbf2aa4 | 1692 | } |
037e8744 | 1693 | while (skip_past_comma (&str) != FAIL); |
0bbf2aa4 | 1694 | |
037e8744 | 1695 | str++; |
0bbf2aa4 | 1696 | |
c19d1205 ZW |
1697 | /* Sanity check -- should have raised a parse error above. */ |
1698 | if (count == 0 || count > max_regs) | |
1699 | abort (); | |
1700 | ||
1701 | *pbase = base_reg; | |
1702 | ||
1703 | /* Final test -- the registers must be consecutive. */ | |
1704 | mask >>= base_reg; | |
1705 | for (i = 0; i < count; i++) | |
1706 | { | |
1707 | if ((mask & (1u << i)) == 0) | |
1708 | { | |
1709 | inst.error = _("non-contiguous register range"); | |
1710 | return FAIL; | |
1711 | } | |
1712 | } | |
1713 | ||
037e8744 JB |
1714 | *ccp = str; |
1715 | ||
c19d1205 | 1716 | return count; |
b99bd4ef NC |
1717 | } |
1718 | ||
dcbf9037 JB |
1719 | /* True if two alias types are the same. */ |
1720 | ||
1721 | static int | |
1722 | neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) | |
1723 | { | |
1724 | if (!a && !b) | |
1725 | return 1; | |
1726 | ||
1727 | if (!a || !b) | |
1728 | return 0; | |
1729 | ||
1730 | if (a->defined != b->defined) | |
1731 | return 0; | |
1732 | ||
1733 | if ((a->defined & NTA_HASTYPE) != 0 | |
1734 | && (a->eltype.type != b->eltype.type | |
1735 | || a->eltype.size != b->eltype.size)) | |
1736 | return 0; | |
1737 | ||
1738 | if ((a->defined & NTA_HASINDEX) != 0 | |
1739 | && (a->index != b->index)) | |
1740 | return 0; | |
1741 | ||
1742 | return 1; | |
1743 | } | |
1744 | ||
5287ad62 JB |
1745 | /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. |
1746 | The base register is put in *PBASE. | |
dcbf9037 | 1747 | The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of |
5287ad62 JB |
1748 | the return value. |
1749 | The register stride (minus one) is put in bit 4 of the return value. | |
dcbf9037 JB |
1750 | Bits [6:5] encode the list length (minus one). |
1751 | The type of the list elements is put in *ELTYPE, if non-NULL. */ | |
5287ad62 | 1752 | |
5287ad62 | 1753 | #define NEON_LANE(X) ((X) & 0xf) |
dcbf9037 | 1754 | #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) |
5287ad62 JB |
1755 | #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) |
1756 | ||
1757 | static int | |
dcbf9037 JB |
1758 | parse_neon_el_struct_list (char **str, unsigned *pbase, |
1759 | struct neon_type_el *eltype) | |
5287ad62 JB |
1760 | { |
1761 | char *ptr = *str; | |
1762 | int base_reg = -1; | |
1763 | int reg_incr = -1; | |
1764 | int count = 0; | |
1765 | int lane = -1; | |
1766 | int leading_brace = 0; | |
1767 | enum arm_reg_type rtype = REG_TYPE_NDQ; | |
1768 | int addregs = 1; | |
1769 | const char *const incr_error = "register stride must be 1 or 2"; | |
1770 | const char *const type_error = "mismatched element/structure types in list"; | |
dcbf9037 | 1771 | struct neon_typed_alias firsttype; |
5287ad62 JB |
1772 | |
1773 | if (skip_past_char (&ptr, '{') == SUCCESS) | |
1774 | leading_brace = 1; | |
1775 | ||
1776 | do | |
1777 | { | |
dcbf9037 JB |
1778 | struct neon_typed_alias atype; |
1779 | int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); | |
1780 | ||
5287ad62 JB |
1781 | if (getreg == FAIL) |
1782 | { | |
dcbf9037 | 1783 | first_error (_(reg_expected_msgs[rtype])); |
5287ad62 JB |
1784 | return FAIL; |
1785 | } | |
1786 | ||
1787 | if (base_reg == -1) | |
1788 | { | |
1789 | base_reg = getreg; | |
1790 | if (rtype == REG_TYPE_NQ) | |
1791 | { | |
1792 | reg_incr = 1; | |
1793 | addregs = 2; | |
1794 | } | |
dcbf9037 | 1795 | firsttype = atype; |
5287ad62 JB |
1796 | } |
1797 | else if (reg_incr == -1) | |
1798 | { | |
1799 | reg_incr = getreg - base_reg; | |
1800 | if (reg_incr < 1 || reg_incr > 2) | |
1801 | { | |
dcbf9037 | 1802 | first_error (_(incr_error)); |
5287ad62 JB |
1803 | return FAIL; |
1804 | } | |
1805 | } | |
1806 | else if (getreg != base_reg + reg_incr * count) | |
1807 | { | |
dcbf9037 JB |
1808 | first_error (_(incr_error)); |
1809 | return FAIL; | |
1810 | } | |
1811 | ||
1812 | if (!neon_alias_types_same (&atype, &firsttype)) | |
1813 | { | |
1814 | first_error (_(type_error)); | |
5287ad62 JB |
1815 | return FAIL; |
1816 | } | |
1817 | ||
1818 | /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list | |
1819 | modes. */ | |
1820 | if (ptr[0] == '-') | |
1821 | { | |
dcbf9037 | 1822 | struct neon_typed_alias htype; |
5287ad62 JB |
1823 | int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; |
1824 | if (lane == -1) | |
1825 | lane = NEON_INTERLEAVE_LANES; | |
1826 | else if (lane != NEON_INTERLEAVE_LANES) | |
1827 | { | |
dcbf9037 | 1828 | first_error (_(type_error)); |
5287ad62 JB |
1829 | return FAIL; |
1830 | } | |
1831 | if (reg_incr == -1) | |
1832 | reg_incr = 1; | |
1833 | else if (reg_incr != 1) | |
1834 | { | |
dcbf9037 | 1835 | first_error (_("don't use Rn-Rm syntax with non-unit stride")); |
5287ad62 JB |
1836 | return FAIL; |
1837 | } | |
1838 | ptr++; | |
dcbf9037 | 1839 | hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); |
5287ad62 JB |
1840 | if (hireg == FAIL) |
1841 | { | |
dcbf9037 JB |
1842 | first_error (_(reg_expected_msgs[rtype])); |
1843 | return FAIL; | |
1844 | } | |
1845 | if (!neon_alias_types_same (&htype, &firsttype)) | |
1846 | { | |
1847 | first_error (_(type_error)); | |
5287ad62 JB |
1848 | return FAIL; |
1849 | } | |
1850 | count += hireg + dregs - getreg; | |
1851 | continue; | |
1852 | } | |
1853 | ||
1854 | /* If we're using Q registers, we can't use [] or [n] syntax. */ | |
1855 | if (rtype == REG_TYPE_NQ) | |
1856 | { | |
1857 | count += 2; | |
1858 | continue; | |
1859 | } | |
1860 | ||
dcbf9037 | 1861 | if ((atype.defined & NTA_HASINDEX) != 0) |
5287ad62 | 1862 | { |
dcbf9037 JB |
1863 | if (lane == -1) |
1864 | lane = atype.index; | |
1865 | else if (lane != atype.index) | |
5287ad62 | 1866 | { |
dcbf9037 JB |
1867 | first_error (_(type_error)); |
1868 | return FAIL; | |
5287ad62 JB |
1869 | } |
1870 | } | |
1871 | else if (lane == -1) | |
1872 | lane = NEON_INTERLEAVE_LANES; | |
1873 | else if (lane != NEON_INTERLEAVE_LANES) | |
1874 | { | |
dcbf9037 | 1875 | first_error (_(type_error)); |
5287ad62 JB |
1876 | return FAIL; |
1877 | } | |
1878 | count++; | |
1879 | } | |
1880 | while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); | |
1881 | ||
1882 | /* No lane set by [x]. We must be interleaving structures. */ | |
1883 | if (lane == -1) | |
1884 | lane = NEON_INTERLEAVE_LANES; | |
1885 | ||
1886 | /* Sanity check. */ | |
1887 | if (lane == -1 || base_reg == -1 || count < 1 || count > 4 | |
1888 | || (count > 1 && reg_incr == -1)) | |
1889 | { | |
dcbf9037 | 1890 | first_error (_("error parsing element/structure list")); |
5287ad62 JB |
1891 | return FAIL; |
1892 | } | |
1893 | ||
1894 | if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) | |
1895 | { | |
dcbf9037 | 1896 | first_error (_("expected }")); |
5287ad62 JB |
1897 | return FAIL; |
1898 | } | |
1899 | ||
1900 | if (reg_incr == -1) | |
1901 | reg_incr = 1; | |
1902 | ||
dcbf9037 JB |
1903 | if (eltype) |
1904 | *eltype = firsttype.eltype; | |
1905 | ||
5287ad62 JB |
1906 | *pbase = base_reg; |
1907 | *str = ptr; | |
1908 | ||
1909 | return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); | |
1910 | } | |
1911 | ||
c19d1205 ZW |
1912 | /* Parse an explicit relocation suffix on an expression. This is |
1913 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
1914 | arm_reloc_hsh contains no entries, so this function can only | |
1915 | succeed if there is no () after the word. Returns -1 on error, | |
1916 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
1917 | static int | |
1918 | parse_reloc (char **str) | |
b99bd4ef | 1919 | { |
c19d1205 ZW |
1920 | struct reloc_entry *r; |
1921 | char *p, *q; | |
b99bd4ef | 1922 | |
c19d1205 ZW |
1923 | if (**str != '(') |
1924 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 1925 | |
c19d1205 ZW |
1926 | p = *str + 1; |
1927 | q = p; | |
1928 | ||
1929 | while (*q && *q != ')' && *q != ',') | |
1930 | q++; | |
1931 | if (*q != ')') | |
1932 | return -1; | |
1933 | ||
1934 | if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
1935 | return -1; | |
1936 | ||
1937 | *str = q + 1; | |
1938 | return r->reloc; | |
b99bd4ef NC |
1939 | } |
1940 | ||
c19d1205 ZW |
1941 | /* Directives: register aliases. */ |
1942 | ||
dcbf9037 | 1943 | static struct reg_entry * |
c19d1205 | 1944 | insert_reg_alias (char *str, int number, int type) |
b99bd4ef | 1945 | { |
c19d1205 ZW |
1946 | struct reg_entry *new; |
1947 | const char *name; | |
b99bd4ef | 1948 | |
c19d1205 ZW |
1949 | if ((new = hash_find (arm_reg_hsh, str)) != 0) |
1950 | { | |
1951 | if (new->builtin) | |
1952 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); | |
b99bd4ef | 1953 | |
c19d1205 ZW |
1954 | /* Only warn about a redefinition if it's not defined as the |
1955 | same register. */ | |
1956 | else if (new->number != number || new->type != type) | |
1957 | as_warn (_("ignoring redefinition of register alias '%s'"), str); | |
69b97547 | 1958 | |
dcbf9037 | 1959 | return 0; |
c19d1205 | 1960 | } |
b99bd4ef | 1961 | |
c19d1205 ZW |
1962 | name = xstrdup (str); |
1963 | new = xmalloc (sizeof (struct reg_entry)); | |
b99bd4ef | 1964 | |
c19d1205 ZW |
1965 | new->name = name; |
1966 | new->number = number; | |
1967 | new->type = type; | |
1968 | new->builtin = FALSE; | |
dcbf9037 | 1969 | new->neon = NULL; |
b99bd4ef | 1970 | |
c19d1205 ZW |
1971 | if (hash_insert (arm_reg_hsh, name, (PTR) new)) |
1972 | abort (); | |
dcbf9037 JB |
1973 | |
1974 | return new; | |
1975 | } | |
1976 | ||
1977 | static void | |
1978 | insert_neon_reg_alias (char *str, int number, int type, | |
1979 | struct neon_typed_alias *atype) | |
1980 | { | |
1981 | struct reg_entry *reg = insert_reg_alias (str, number, type); | |
1982 | ||
1983 | if (!reg) | |
1984 | { | |
1985 | first_error (_("attempt to redefine typed alias")); | |
1986 | return; | |
1987 | } | |
1988 | ||
1989 | if (atype) | |
1990 | { | |
1991 | reg->neon = xmalloc (sizeof (struct neon_typed_alias)); | |
1992 | *reg->neon = *atype; | |
1993 | } | |
c19d1205 | 1994 | } |
b99bd4ef | 1995 | |
c19d1205 | 1996 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 1997 | |
c19d1205 | 1998 | new_register_name .req existing_register_name |
b99bd4ef | 1999 | |
c19d1205 ZW |
2000 | If we find one, or if it looks sufficiently like one that we want to |
2001 | handle any error here, return non-zero. Otherwise return zero. */ | |
b99bd4ef | 2002 | |
c19d1205 ZW |
2003 | static int |
2004 | create_register_alias (char * newname, char *p) | |
2005 | { | |
2006 | struct reg_entry *old; | |
2007 | char *oldname, *nbuf; | |
2008 | size_t nlen; | |
b99bd4ef | 2009 | |
c19d1205 ZW |
2010 | /* The input scrubber ensures that whitespace after the mnemonic is |
2011 | collapsed to single spaces. */ | |
2012 | oldname = p; | |
2013 | if (strncmp (oldname, " .req ", 6) != 0) | |
2014 | return 0; | |
b99bd4ef | 2015 | |
c19d1205 ZW |
2016 | oldname += 6; |
2017 | if (*oldname == '\0') | |
2018 | return 0; | |
b99bd4ef | 2019 | |
c19d1205 ZW |
2020 | old = hash_find (arm_reg_hsh, oldname); |
2021 | if (!old) | |
b99bd4ef | 2022 | { |
c19d1205 ZW |
2023 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
2024 | return 1; | |
b99bd4ef NC |
2025 | } |
2026 | ||
c19d1205 ZW |
2027 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2028 | the desired alias name, and p points to its end. If not, then | |
2029 | the desired alias name is in the global original_case_string. */ | |
2030 | #ifdef TC_CASE_SENSITIVE | |
2031 | nlen = p - newname; | |
2032 | #else | |
2033 | newname = original_case_string; | |
2034 | nlen = strlen (newname); | |
2035 | #endif | |
b99bd4ef | 2036 | |
c19d1205 ZW |
2037 | nbuf = alloca (nlen + 1); |
2038 | memcpy (nbuf, newname, nlen); | |
2039 | nbuf[nlen] = '\0'; | |
b99bd4ef | 2040 | |
c19d1205 ZW |
2041 | /* Create aliases under the new name as stated; an all-lowercase |
2042 | version of the new name; and an all-uppercase version of the new | |
2043 | name. */ | |
2044 | insert_reg_alias (nbuf, old->number, old->type); | |
b99bd4ef | 2045 | |
c19d1205 ZW |
2046 | for (p = nbuf; *p; p++) |
2047 | *p = TOUPPER (*p); | |
2048 | ||
2049 | if (strncmp (nbuf, newname, nlen)) | |
2050 | insert_reg_alias (nbuf, old->number, old->type); | |
2051 | ||
2052 | for (p = nbuf; *p; p++) | |
2053 | *p = TOLOWER (*p); | |
2054 | ||
2055 | if (strncmp (nbuf, newname, nlen)) | |
2056 | insert_reg_alias (nbuf, old->number, old->type); | |
2057 | ||
2058 | return 1; | |
b99bd4ef NC |
2059 | } |
2060 | ||
dcbf9037 JB |
2061 | /* Create a Neon typed/indexed register alias using directives, e.g.: |
2062 | X .dn d5.s32[1] | |
2063 | Y .qn 6.s16 | |
2064 | Z .dn d7 | |
2065 | T .dn Z[0] | |
2066 | These typed registers can be used instead of the types specified after the | |
2067 | Neon mnemonic, so long as all operands given have types. Types can also be | |
2068 | specified directly, e.g.: | |
2069 | vadd d0.s32, d1.s32, d2.s32 | |
2070 | */ | |
2071 | ||
2072 | static int | |
2073 | create_neon_reg_alias (char *newname, char *p) | |
2074 | { | |
2075 | enum arm_reg_type basetype; | |
2076 | struct reg_entry *basereg; | |
2077 | struct reg_entry mybasereg; | |
2078 | struct neon_type ntype; | |
2079 | struct neon_typed_alias typeinfo; | |
2080 | char *namebuf, *nameend; | |
2081 | int namelen; | |
2082 | ||
2083 | typeinfo.defined = 0; | |
2084 | typeinfo.eltype.type = NT_invtype; | |
2085 | typeinfo.eltype.size = -1; | |
2086 | typeinfo.index = -1; | |
2087 | ||
2088 | nameend = p; | |
2089 | ||
2090 | if (strncmp (p, " .dn ", 5) == 0) | |
2091 | basetype = REG_TYPE_VFD; | |
2092 | else if (strncmp (p, " .qn ", 5) == 0) | |
2093 | basetype = REG_TYPE_NQ; | |
2094 | else | |
2095 | return 0; | |
2096 | ||
2097 | p += 5; | |
2098 | ||
2099 | if (*p == '\0') | |
2100 | return 0; | |
2101 | ||
2102 | basereg = arm_reg_parse_multi (&p); | |
2103 | ||
2104 | if (basereg && basereg->type != basetype) | |
2105 | { | |
2106 | as_bad (_("bad type for register")); | |
2107 | return 0; | |
2108 | } | |
2109 | ||
2110 | if (basereg == NULL) | |
2111 | { | |
2112 | expressionS exp; | |
2113 | /* Try parsing as an integer. */ | |
2114 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
2115 | if (exp.X_op != O_constant) | |
2116 | { | |
2117 | as_bad (_("expression must be constant")); | |
2118 | return 0; | |
2119 | } | |
2120 | basereg = &mybasereg; | |
2121 | basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 | |
2122 | : exp.X_add_number; | |
2123 | basereg->neon = 0; | |
2124 | } | |
2125 | ||
2126 | if (basereg->neon) | |
2127 | typeinfo = *basereg->neon; | |
2128 | ||
2129 | if (parse_neon_type (&ntype, &p) == SUCCESS) | |
2130 | { | |
2131 | /* We got a type. */ | |
2132 | if (typeinfo.defined & NTA_HASTYPE) | |
2133 | { | |
2134 | as_bad (_("can't redefine the type of a register alias")); | |
2135 | return 0; | |
2136 | } | |
2137 | ||
2138 | typeinfo.defined |= NTA_HASTYPE; | |
2139 | if (ntype.elems != 1) | |
2140 | { | |
2141 | as_bad (_("you must specify a single type only")); | |
2142 | return 0; | |
2143 | } | |
2144 | typeinfo.eltype = ntype.el[0]; | |
2145 | } | |
2146 | ||
2147 | if (skip_past_char (&p, '[') == SUCCESS) | |
2148 | { | |
2149 | expressionS exp; | |
2150 | /* We got a scalar index. */ | |
2151 | ||
2152 | if (typeinfo.defined & NTA_HASINDEX) | |
2153 | { | |
2154 | as_bad (_("can't redefine the index of a scalar alias")); | |
2155 | return 0; | |
2156 | } | |
2157 | ||
2158 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
2159 | ||
2160 | if (exp.X_op != O_constant) | |
2161 | { | |
2162 | as_bad (_("scalar index must be constant")); | |
2163 | return 0; | |
2164 | } | |
2165 | ||
2166 | typeinfo.defined |= NTA_HASINDEX; | |
2167 | typeinfo.index = exp.X_add_number; | |
2168 | ||
2169 | if (skip_past_char (&p, ']') == FAIL) | |
2170 | { | |
2171 | as_bad (_("expecting ]")); | |
2172 | return 0; | |
2173 | } | |
2174 | } | |
2175 | ||
2176 | namelen = nameend - newname; | |
2177 | namebuf = alloca (namelen + 1); | |
2178 | strncpy (namebuf, newname, namelen); | |
2179 | namebuf[namelen] = '\0'; | |
2180 | ||
2181 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2182 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
2183 | ||
2184 | /* Insert name in all uppercase. */ | |
2185 | for (p = namebuf; *p; p++) | |
2186 | *p = TOUPPER (*p); | |
2187 | ||
2188 | if (strncmp (namebuf, newname, namelen)) | |
2189 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2190 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
2191 | ||
2192 | /* Insert name in all lowercase. */ | |
2193 | for (p = namebuf; *p; p++) | |
2194 | *p = TOLOWER (*p); | |
2195 | ||
2196 | if (strncmp (namebuf, newname, namelen)) | |
2197 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2198 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
2199 | ||
2200 | return 1; | |
2201 | } | |
2202 | ||
c19d1205 ZW |
2203 | /* Should never be called, as .req goes between the alias and the |
2204 | register name, not at the beginning of the line. */ | |
b99bd4ef | 2205 | static void |
c19d1205 | 2206 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2207 | { |
c19d1205 ZW |
2208 | as_bad (_("invalid syntax for .req directive")); |
2209 | } | |
b99bd4ef | 2210 | |
dcbf9037 JB |
2211 | static void |
2212 | s_dn (int a ATTRIBUTE_UNUSED) | |
2213 | { | |
2214 | as_bad (_("invalid syntax for .dn directive")); | |
2215 | } | |
2216 | ||
2217 | static void | |
2218 | s_qn (int a ATTRIBUTE_UNUSED) | |
2219 | { | |
2220 | as_bad (_("invalid syntax for .qn directive")); | |
2221 | } | |
2222 | ||
c19d1205 ZW |
2223 | /* The .unreq directive deletes an alias which was previously defined |
2224 | by .req. For example: | |
b99bd4ef | 2225 | |
c19d1205 ZW |
2226 | my_alias .req r11 |
2227 | .unreq my_alias */ | |
b99bd4ef NC |
2228 | |
2229 | static void | |
c19d1205 | 2230 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2231 | { |
c19d1205 ZW |
2232 | char * name; |
2233 | char saved_char; | |
b99bd4ef | 2234 | |
c19d1205 ZW |
2235 | name = input_line_pointer; |
2236 | ||
2237 | while (*input_line_pointer != 0 | |
2238 | && *input_line_pointer != ' ' | |
2239 | && *input_line_pointer != '\n') | |
2240 | ++input_line_pointer; | |
2241 | ||
2242 | saved_char = *input_line_pointer; | |
2243 | *input_line_pointer = 0; | |
2244 | ||
2245 | if (!*name) | |
2246 | as_bad (_("invalid syntax for .unreq directive")); | |
2247 | else | |
2248 | { | |
2249 | struct reg_entry *reg = hash_find (arm_reg_hsh, name); | |
2250 | ||
2251 | if (!reg) | |
2252 | as_bad (_("unknown register alias '%s'"), name); | |
2253 | else if (reg->builtin) | |
2254 | as_warn (_("ignoring attempt to undefine built-in register '%s'"), | |
2255 | name); | |
2256 | else | |
2257 | { | |
2258 | hash_delete (arm_reg_hsh, name); | |
2259 | free ((char *) reg->name); | |
dcbf9037 JB |
2260 | if (reg->neon) |
2261 | free (reg->neon); | |
c19d1205 ZW |
2262 | free (reg); |
2263 | } | |
2264 | } | |
b99bd4ef | 2265 | |
c19d1205 | 2266 | *input_line_pointer = saved_char; |
b99bd4ef NC |
2267 | demand_empty_rest_of_line (); |
2268 | } | |
2269 | ||
c19d1205 ZW |
2270 | /* Directives: Instruction set selection. */ |
2271 | ||
2272 | #ifdef OBJ_ELF | |
2273 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
2274 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
2275 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
2276 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
2277 | ||
2278 | static enum mstate mapstate = MAP_UNDEFINED; | |
b99bd4ef NC |
2279 | |
2280 | static void | |
c19d1205 | 2281 | mapping_state (enum mstate state) |
b99bd4ef | 2282 | { |
a737bd4d | 2283 | symbolS * symbolP; |
c19d1205 ZW |
2284 | const char * symname; |
2285 | int type; | |
b99bd4ef | 2286 | |
c19d1205 ZW |
2287 | if (mapstate == state) |
2288 | /* The mapping symbol has already been emitted. | |
2289 | There is nothing else to do. */ | |
2290 | return; | |
b99bd4ef | 2291 | |
c19d1205 | 2292 | mapstate = state; |
b99bd4ef | 2293 | |
c19d1205 | 2294 | switch (state) |
b99bd4ef | 2295 | { |
c19d1205 ZW |
2296 | case MAP_DATA: |
2297 | symname = "$d"; | |
2298 | type = BSF_NO_FLAGS; | |
2299 | break; | |
2300 | case MAP_ARM: | |
2301 | symname = "$a"; | |
2302 | type = BSF_NO_FLAGS; | |
2303 | break; | |
2304 | case MAP_THUMB: | |
2305 | symname = "$t"; | |
2306 | type = BSF_NO_FLAGS; | |
2307 | break; | |
2308 | case MAP_UNDEFINED: | |
2309 | return; | |
2310 | default: | |
2311 | abort (); | |
2312 | } | |
2313 | ||
2314 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; | |
2315 | ||
2316 | symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now); | |
2317 | symbol_table_insert (symbolP); | |
2318 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; | |
2319 | ||
2320 | switch (state) | |
2321 | { | |
2322 | case MAP_ARM: | |
2323 | THUMB_SET_FUNC (symbolP, 0); | |
2324 | ARM_SET_THUMB (symbolP, 0); | |
2325 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2326 | break; | |
2327 | ||
2328 | case MAP_THUMB: | |
2329 | THUMB_SET_FUNC (symbolP, 1); | |
2330 | ARM_SET_THUMB (symbolP, 1); | |
2331 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2332 | break; | |
2333 | ||
2334 | case MAP_DATA: | |
2335 | default: | |
2336 | return; | |
2337 | } | |
2338 | } | |
2339 | #else | |
2340 | #define mapping_state(x) /* nothing */ | |
2341 | #endif | |
2342 | ||
2343 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
2344 | ||
2345 | static symbolS * | |
2346 | find_real_start (symbolS * symbolP) | |
2347 | { | |
2348 | char * real_start; | |
2349 | const char * name = S_GET_NAME (symbolP); | |
2350 | symbolS * new_target; | |
2351 | ||
2352 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
2353 | #define STUB_NAME ".real_start_of" | |
2354 | ||
2355 | if (name == NULL) | |
2356 | abort (); | |
2357 | ||
37f6032b ZW |
2358 | /* The compiler may generate BL instructions to local labels because |
2359 | it needs to perform a branch to a far away location. These labels | |
2360 | do not have a corresponding ".real_start_of" label. We check | |
2361 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
2362 | the ".real_start_of" convention for nonlocal branches. */ | |
2363 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
2364 | return symbolP; |
2365 | ||
37f6032b | 2366 | real_start = ACONCAT ((STUB_NAME, name, NULL)); |
c19d1205 ZW |
2367 | new_target = symbol_find (real_start); |
2368 | ||
2369 | if (new_target == NULL) | |
2370 | { | |
2371 | as_warn ("Failed to find real start of function: %s\n", name); | |
2372 | new_target = symbolP; | |
2373 | } | |
2374 | ||
c19d1205 ZW |
2375 | return new_target; |
2376 | } | |
2377 | ||
2378 | static void | |
2379 | opcode_select (int width) | |
2380 | { | |
2381 | switch (width) | |
2382 | { | |
2383 | case 16: | |
2384 | if (! thumb_mode) | |
2385 | { | |
e74cfd16 | 2386 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
c19d1205 ZW |
2387 | as_bad (_("selected processor does not support THUMB opcodes")); |
2388 | ||
2389 | thumb_mode = 1; | |
2390 | /* No need to force the alignment, since we will have been | |
2391 | coming from ARM mode, which is word-aligned. */ | |
2392 | record_alignment (now_seg, 1); | |
2393 | } | |
2394 | mapping_state (MAP_THUMB); | |
2395 | break; | |
2396 | ||
2397 | case 32: | |
2398 | if (thumb_mode) | |
2399 | { | |
e74cfd16 | 2400 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 ZW |
2401 | as_bad (_("selected processor does not support ARM opcodes")); |
2402 | ||
2403 | thumb_mode = 0; | |
2404 | ||
2405 | if (!need_pass_2) | |
2406 | frag_align (2, 0, 0); | |
2407 | ||
2408 | record_alignment (now_seg, 1); | |
2409 | } | |
2410 | mapping_state (MAP_ARM); | |
2411 | break; | |
2412 | ||
2413 | default: | |
2414 | as_bad (_("invalid instruction size selected (%d)"), width); | |
2415 | } | |
2416 | } | |
2417 | ||
2418 | static void | |
2419 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
2420 | { | |
2421 | opcode_select (32); | |
2422 | demand_empty_rest_of_line (); | |
2423 | } | |
2424 | ||
2425 | static void | |
2426 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
2427 | { | |
2428 | opcode_select (16); | |
2429 | demand_empty_rest_of_line (); | |
2430 | } | |
2431 | ||
2432 | static void | |
2433 | s_code (int unused ATTRIBUTE_UNUSED) | |
2434 | { | |
2435 | int temp; | |
2436 | ||
2437 | temp = get_absolute_expression (); | |
2438 | switch (temp) | |
2439 | { | |
2440 | case 16: | |
2441 | case 32: | |
2442 | opcode_select (temp); | |
2443 | break; | |
2444 | ||
2445 | default: | |
2446 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
2447 | } | |
2448 | } | |
2449 | ||
2450 | static void | |
2451 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
2452 | { | |
2453 | /* If we are not already in thumb mode go into it, EVEN if | |
2454 | the target processor does not support thumb instructions. | |
2455 | This is used by gcc/config/arm/lib1funcs.asm for example | |
2456 | to compile interworking support functions even if the | |
2457 | target processor should not support interworking. */ | |
2458 | if (! thumb_mode) | |
2459 | { | |
2460 | thumb_mode = 2; | |
2461 | record_alignment (now_seg, 1); | |
2462 | } | |
2463 | ||
2464 | demand_empty_rest_of_line (); | |
2465 | } | |
2466 | ||
2467 | static void | |
2468 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
2469 | { | |
2470 | s_thumb (0); | |
2471 | ||
2472 | /* The following label is the name/address of the start of a Thumb function. | |
2473 | We need to know this for the interworking support. */ | |
2474 | label_is_thumb_function_name = TRUE; | |
2475 | } | |
2476 | ||
2477 | /* Perform a .set directive, but also mark the alias as | |
2478 | being a thumb function. */ | |
2479 | ||
2480 | static void | |
2481 | s_thumb_set (int equiv) | |
2482 | { | |
2483 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
2484 | We cannot just call that code as we need to get at the symbol that | |
2485 | is created. */ | |
2486 | char * name; | |
2487 | char delim; | |
2488 | char * end_name; | |
2489 | symbolS * symbolP; | |
2490 | ||
2491 | /* Especial apologies for the random logic: | |
2492 | This just grew, and could be parsed much more simply! | |
2493 | Dean - in haste. */ | |
2494 | name = input_line_pointer; | |
2495 | delim = get_symbol_end (); | |
2496 | end_name = input_line_pointer; | |
2497 | *end_name = delim; | |
2498 | ||
2499 | if (*input_line_pointer != ',') | |
2500 | { | |
2501 | *end_name = 0; | |
2502 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
2503 | *end_name = delim; |
2504 | ignore_rest_of_line (); | |
2505 | return; | |
2506 | } | |
2507 | ||
2508 | input_line_pointer++; | |
2509 | *end_name = 0; | |
2510 | ||
2511 | if (name[0] == '.' && name[1] == '\0') | |
2512 | { | |
2513 | /* XXX - this should not happen to .thumb_set. */ | |
2514 | abort (); | |
2515 | } | |
2516 | ||
2517 | if ((symbolP = symbol_find (name)) == NULL | |
2518 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
2519 | { | |
2520 | #ifndef NO_LISTING | |
2521 | /* When doing symbol listings, play games with dummy fragments living | |
2522 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 2523 | for this symbol. */ |
b99bd4ef NC |
2524 | if (listing & LISTING_SYMBOLS) |
2525 | { | |
2526 | extern struct list_info_struct * listing_tail; | |
a737bd4d | 2527 | fragS * dummy_frag = xmalloc (sizeof (fragS)); |
b99bd4ef NC |
2528 | |
2529 | memset (dummy_frag, 0, sizeof (fragS)); | |
2530 | dummy_frag->fr_type = rs_fill; | |
2531 | dummy_frag->line = listing_tail; | |
2532 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
2533 | dummy_frag->fr_symbol = symbolP; | |
2534 | } | |
2535 | else | |
2536 | #endif | |
2537 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
2538 | ||
2539 | #ifdef OBJ_COFF | |
2540 | /* "set" symbols are local unless otherwise specified. */ | |
2541 | SF_SET_LOCAL (symbolP); | |
2542 | #endif /* OBJ_COFF */ | |
2543 | } /* Make a new symbol. */ | |
2544 | ||
2545 | symbol_table_insert (symbolP); | |
2546 | ||
2547 | * end_name = delim; | |
2548 | ||
2549 | if (equiv | |
2550 | && S_IS_DEFINED (symbolP) | |
2551 | && S_GET_SEGMENT (symbolP) != reg_section) | |
2552 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
2553 | ||
2554 | pseudo_set (symbolP); | |
2555 | ||
2556 | demand_empty_rest_of_line (); | |
2557 | ||
c19d1205 | 2558 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
2559 | |
2560 | THUMB_SET_FUNC (symbolP, 1); | |
2561 | ARM_SET_THUMB (symbolP, 1); | |
2562 | #if defined OBJ_ELF || defined OBJ_COFF | |
2563 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2564 | #endif | |
2565 | } | |
2566 | ||
c19d1205 | 2567 | /* Directives: Mode selection. */ |
b99bd4ef | 2568 | |
c19d1205 ZW |
2569 | /* .syntax [unified|divided] - choose the new unified syntax |
2570 | (same for Arm and Thumb encoding, modulo slight differences in what | |
2571 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 2572 | static void |
c19d1205 | 2573 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2574 | { |
c19d1205 ZW |
2575 | char *name, delim; |
2576 | ||
2577 | name = input_line_pointer; | |
2578 | delim = get_symbol_end (); | |
2579 | ||
2580 | if (!strcasecmp (name, "unified")) | |
2581 | unified_syntax = TRUE; | |
2582 | else if (!strcasecmp (name, "divided")) | |
2583 | unified_syntax = FALSE; | |
2584 | else | |
2585 | { | |
2586 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
2587 | return; | |
2588 | } | |
2589 | *input_line_pointer = delim; | |
b99bd4ef NC |
2590 | demand_empty_rest_of_line (); |
2591 | } | |
2592 | ||
c19d1205 ZW |
2593 | /* Directives: sectioning and alignment. */ |
2594 | ||
2595 | /* Same as s_align_ptwo but align 0 => align 2. */ | |
2596 | ||
b99bd4ef | 2597 | static void |
c19d1205 | 2598 | s_align (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2599 | { |
a737bd4d | 2600 | int temp; |
c19d1205 ZW |
2601 | long temp_fill; |
2602 | long max_alignment = 15; | |
b99bd4ef NC |
2603 | |
2604 | temp = get_absolute_expression (); | |
c19d1205 ZW |
2605 | if (temp > max_alignment) |
2606 | as_bad (_("alignment too large: %d assumed"), temp = max_alignment); | |
2607 | else if (temp < 0) | |
b99bd4ef | 2608 | { |
c19d1205 ZW |
2609 | as_bad (_("alignment negative. 0 assumed.")); |
2610 | temp = 0; | |
2611 | } | |
b99bd4ef | 2612 | |
c19d1205 ZW |
2613 | if (*input_line_pointer == ',') |
2614 | { | |
2615 | input_line_pointer++; | |
2616 | temp_fill = get_absolute_expression (); | |
b99bd4ef | 2617 | } |
c19d1205 ZW |
2618 | else |
2619 | temp_fill = 0; | |
b99bd4ef | 2620 | |
c19d1205 ZW |
2621 | if (!temp) |
2622 | temp = 2; | |
b99bd4ef | 2623 | |
c19d1205 ZW |
2624 | /* Only make a frag if we HAVE to. */ |
2625 | if (temp && !need_pass_2) | |
2626 | frag_align (temp, (int) temp_fill, 0); | |
2627 | demand_empty_rest_of_line (); | |
2628 | ||
2629 | record_alignment (now_seg, temp); | |
b99bd4ef NC |
2630 | } |
2631 | ||
c19d1205 ZW |
2632 | static void |
2633 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 2634 | { |
c19d1205 ZW |
2635 | /* We don't support putting frags in the BSS segment, we fake it by |
2636 | marking in_bss, then looking at s_skip for clues. */ | |
2637 | subseg_set (bss_section, 0); | |
2638 | demand_empty_rest_of_line (); | |
2639 | mapping_state (MAP_DATA); | |
2640 | } | |
b99bd4ef | 2641 | |
c19d1205 ZW |
2642 | static void |
2643 | s_even (int ignore ATTRIBUTE_UNUSED) | |
2644 | { | |
2645 | /* Never make frag if expect extra pass. */ | |
2646 | if (!need_pass_2) | |
2647 | frag_align (1, 0, 0); | |
b99bd4ef | 2648 | |
c19d1205 | 2649 | record_alignment (now_seg, 1); |
b99bd4ef | 2650 | |
c19d1205 | 2651 | demand_empty_rest_of_line (); |
b99bd4ef NC |
2652 | } |
2653 | ||
c19d1205 | 2654 | /* Directives: Literal pools. */ |
a737bd4d | 2655 | |
c19d1205 ZW |
2656 | static literal_pool * |
2657 | find_literal_pool (void) | |
a737bd4d | 2658 | { |
c19d1205 | 2659 | literal_pool * pool; |
a737bd4d | 2660 | |
c19d1205 | 2661 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 2662 | { |
c19d1205 ZW |
2663 | if (pool->section == now_seg |
2664 | && pool->sub_section == now_subseg) | |
2665 | break; | |
a737bd4d NC |
2666 | } |
2667 | ||
c19d1205 | 2668 | return pool; |
a737bd4d NC |
2669 | } |
2670 | ||
c19d1205 ZW |
2671 | static literal_pool * |
2672 | find_or_make_literal_pool (void) | |
a737bd4d | 2673 | { |
c19d1205 ZW |
2674 | /* Next literal pool ID number. */ |
2675 | static unsigned int latest_pool_num = 1; | |
2676 | literal_pool * pool; | |
a737bd4d | 2677 | |
c19d1205 | 2678 | pool = find_literal_pool (); |
a737bd4d | 2679 | |
c19d1205 | 2680 | if (pool == NULL) |
a737bd4d | 2681 | { |
c19d1205 ZW |
2682 | /* Create a new pool. */ |
2683 | pool = xmalloc (sizeof (* pool)); | |
2684 | if (! pool) | |
2685 | return NULL; | |
a737bd4d | 2686 | |
c19d1205 ZW |
2687 | pool->next_free_entry = 0; |
2688 | pool->section = now_seg; | |
2689 | pool->sub_section = now_subseg; | |
2690 | pool->next = list_of_pools; | |
2691 | pool->symbol = NULL; | |
2692 | ||
2693 | /* Add it to the list. */ | |
2694 | list_of_pools = pool; | |
a737bd4d | 2695 | } |
a737bd4d | 2696 | |
c19d1205 ZW |
2697 | /* New pools, and emptied pools, will have a NULL symbol. */ |
2698 | if (pool->symbol == NULL) | |
a737bd4d | 2699 | { |
c19d1205 ZW |
2700 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
2701 | (valueT) 0, &zero_address_frag); | |
2702 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
2703 | } |
2704 | ||
c19d1205 ZW |
2705 | /* Done. */ |
2706 | return pool; | |
a737bd4d NC |
2707 | } |
2708 | ||
c19d1205 ZW |
2709 | /* Add the literal in the global 'inst' |
2710 | structure to the relevent literal pool. */ | |
b99bd4ef NC |
2711 | |
2712 | static int | |
c19d1205 | 2713 | add_to_lit_pool (void) |
b99bd4ef | 2714 | { |
c19d1205 ZW |
2715 | literal_pool * pool; |
2716 | unsigned int entry; | |
b99bd4ef | 2717 | |
c19d1205 ZW |
2718 | pool = find_or_make_literal_pool (); |
2719 | ||
2720 | /* Check if this literal value is already in the pool. */ | |
2721 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 2722 | { |
c19d1205 ZW |
2723 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) |
2724 | && (inst.reloc.exp.X_op == O_constant) | |
2725 | && (pool->literals[entry].X_add_number | |
2726 | == inst.reloc.exp.X_add_number) | |
2727 | && (pool->literals[entry].X_unsigned | |
2728 | == inst.reloc.exp.X_unsigned)) | |
2729 | break; | |
2730 | ||
2731 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
2732 | && (inst.reloc.exp.X_op == O_symbol) | |
2733 | && (pool->literals[entry].X_add_number | |
2734 | == inst.reloc.exp.X_add_number) | |
2735 | && (pool->literals[entry].X_add_symbol | |
2736 | == inst.reloc.exp.X_add_symbol) | |
2737 | && (pool->literals[entry].X_op_symbol | |
2738 | == inst.reloc.exp.X_op_symbol)) | |
2739 | break; | |
b99bd4ef NC |
2740 | } |
2741 | ||
c19d1205 ZW |
2742 | /* Do we need to create a new entry? */ |
2743 | if (entry == pool->next_free_entry) | |
2744 | { | |
2745 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
2746 | { | |
2747 | inst.error = _("literal pool overflow"); | |
2748 | return FAIL; | |
2749 | } | |
2750 | ||
2751 | pool->literals[entry] = inst.reloc.exp; | |
2752 | pool->next_free_entry += 1; | |
2753 | } | |
b99bd4ef | 2754 | |
c19d1205 ZW |
2755 | inst.reloc.exp.X_op = O_symbol; |
2756 | inst.reloc.exp.X_add_number = ((int) entry) * 4; | |
2757 | inst.reloc.exp.X_add_symbol = pool->symbol; | |
b99bd4ef | 2758 | |
c19d1205 | 2759 | return SUCCESS; |
b99bd4ef NC |
2760 | } |
2761 | ||
c19d1205 ZW |
2762 | /* Can't use symbol_new here, so have to create a symbol and then at |
2763 | a later date assign it a value. Thats what these functions do. */ | |
e16bb312 | 2764 | |
c19d1205 ZW |
2765 | static void |
2766 | symbol_locate (symbolS * symbolP, | |
2767 | const char * name, /* It is copied, the caller can modify. */ | |
2768 | segT segment, /* Segment identifier (SEG_<something>). */ | |
2769 | valueT valu, /* Symbol value. */ | |
2770 | fragS * frag) /* Associated fragment. */ | |
2771 | { | |
2772 | unsigned int name_length; | |
2773 | char * preserved_copy_of_name; | |
e16bb312 | 2774 | |
c19d1205 ZW |
2775 | name_length = strlen (name) + 1; /* +1 for \0. */ |
2776 | obstack_grow (¬es, name, name_length); | |
2777 | preserved_copy_of_name = obstack_finish (¬es); | |
e16bb312 | 2778 | |
c19d1205 ZW |
2779 | #ifdef tc_canonicalize_symbol_name |
2780 | preserved_copy_of_name = | |
2781 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
2782 | #endif | |
b99bd4ef | 2783 | |
c19d1205 | 2784 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 2785 | |
c19d1205 ZW |
2786 | S_SET_SEGMENT (symbolP, segment); |
2787 | S_SET_VALUE (symbolP, valu); | |
2788 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 2789 | |
c19d1205 | 2790 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 2791 | |
c19d1205 ZW |
2792 | /* Link to end of symbol chain. */ |
2793 | { | |
2794 | extern int symbol_table_frozen; | |
b99bd4ef | 2795 | |
c19d1205 ZW |
2796 | if (symbol_table_frozen) |
2797 | abort (); | |
2798 | } | |
b99bd4ef | 2799 | |
c19d1205 | 2800 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 2801 | |
c19d1205 | 2802 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 2803 | |
c19d1205 ZW |
2804 | #ifdef tc_symbol_new_hook |
2805 | tc_symbol_new_hook (symbolP); | |
2806 | #endif | |
2807 | ||
2808 | #ifdef DEBUG_SYMS | |
2809 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
2810 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
2811 | } |
2812 | ||
b99bd4ef | 2813 | |
c19d1205 ZW |
2814 | static void |
2815 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 2816 | { |
c19d1205 ZW |
2817 | unsigned int entry; |
2818 | literal_pool * pool; | |
2819 | char sym_name[20]; | |
b99bd4ef | 2820 | |
c19d1205 ZW |
2821 | pool = find_literal_pool (); |
2822 | if (pool == NULL | |
2823 | || pool->symbol == NULL | |
2824 | || pool->next_free_entry == 0) | |
2825 | return; | |
b99bd4ef | 2826 | |
c19d1205 | 2827 | mapping_state (MAP_DATA); |
b99bd4ef | 2828 | |
c19d1205 ZW |
2829 | /* Align pool as you have word accesses. |
2830 | Only make a frag if we have to. */ | |
2831 | if (!need_pass_2) | |
2832 | frag_align (2, 0, 0); | |
b99bd4ef | 2833 | |
c19d1205 | 2834 | record_alignment (now_seg, 2); |
b99bd4ef | 2835 | |
c19d1205 | 2836 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 2837 | |
c19d1205 ZW |
2838 | symbol_locate (pool->symbol, sym_name, now_seg, |
2839 | (valueT) frag_now_fix (), frag_now); | |
2840 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 2841 | |
c19d1205 | 2842 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 2843 | |
c19d1205 ZW |
2844 | #if defined OBJ_COFF || defined OBJ_ELF |
2845 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
2846 | #endif | |
6c43fab6 | 2847 | |
c19d1205 ZW |
2848 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
2849 | /* First output the expression in the instruction to the pool. */ | |
2850 | emit_expr (&(pool->literals[entry]), 4); /* .word */ | |
b99bd4ef | 2851 | |
c19d1205 ZW |
2852 | /* Mark the pool as empty. */ |
2853 | pool->next_free_entry = 0; | |
2854 | pool->symbol = NULL; | |
b99bd4ef NC |
2855 | } |
2856 | ||
c19d1205 ZW |
2857 | #ifdef OBJ_ELF |
2858 | /* Forward declarations for functions below, in the MD interface | |
2859 | section. */ | |
2860 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
2861 | static valueT create_unwind_entry (int); | |
2862 | static void start_unwind_section (const segT, int); | |
2863 | static void add_unwind_opcode (valueT, int); | |
2864 | static void flush_pending_unwind (void); | |
b99bd4ef | 2865 | |
c19d1205 | 2866 | /* Directives: Data. */ |
b99bd4ef | 2867 | |
c19d1205 ZW |
2868 | static void |
2869 | s_arm_elf_cons (int nbytes) | |
2870 | { | |
2871 | expressionS exp; | |
b99bd4ef | 2872 | |
c19d1205 ZW |
2873 | #ifdef md_flush_pending_output |
2874 | md_flush_pending_output (); | |
2875 | #endif | |
b99bd4ef | 2876 | |
c19d1205 | 2877 | if (is_it_end_of_statement ()) |
b99bd4ef | 2878 | { |
c19d1205 ZW |
2879 | demand_empty_rest_of_line (); |
2880 | return; | |
b99bd4ef NC |
2881 | } |
2882 | ||
c19d1205 ZW |
2883 | #ifdef md_cons_align |
2884 | md_cons_align (nbytes); | |
2885 | #endif | |
b99bd4ef | 2886 | |
c19d1205 ZW |
2887 | mapping_state (MAP_DATA); |
2888 | do | |
b99bd4ef | 2889 | { |
c19d1205 ZW |
2890 | int reloc; |
2891 | char *base = input_line_pointer; | |
b99bd4ef | 2892 | |
c19d1205 | 2893 | expression (& exp); |
b99bd4ef | 2894 | |
c19d1205 ZW |
2895 | if (exp.X_op != O_symbol) |
2896 | emit_expr (&exp, (unsigned int) nbytes); | |
2897 | else | |
2898 | { | |
2899 | char *before_reloc = input_line_pointer; | |
2900 | reloc = parse_reloc (&input_line_pointer); | |
2901 | if (reloc == -1) | |
2902 | { | |
2903 | as_bad (_("unrecognized relocation suffix")); | |
2904 | ignore_rest_of_line (); | |
2905 | return; | |
2906 | } | |
2907 | else if (reloc == BFD_RELOC_UNUSED) | |
2908 | emit_expr (&exp, (unsigned int) nbytes); | |
2909 | else | |
2910 | { | |
2911 | reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc); | |
2912 | int size = bfd_get_reloc_size (howto); | |
b99bd4ef | 2913 | |
2fc8bdac ZW |
2914 | if (reloc == BFD_RELOC_ARM_PLT32) |
2915 | { | |
2916 | as_bad (_("(plt) is only valid on branch targets")); | |
2917 | reloc = BFD_RELOC_UNUSED; | |
2918 | size = 0; | |
2919 | } | |
2920 | ||
c19d1205 | 2921 | if (size > nbytes) |
2fc8bdac | 2922 | as_bad (_("%s relocations do not fit in %d bytes"), |
c19d1205 ZW |
2923 | howto->name, nbytes); |
2924 | else | |
2925 | { | |
2926 | /* We've parsed an expression stopping at O_symbol. | |
2927 | But there may be more expression left now that we | |
2928 | have parsed the relocation marker. Parse it again. | |
2929 | XXX Surely there is a cleaner way to do this. */ | |
2930 | char *p = input_line_pointer; | |
2931 | int offset; | |
2932 | char *save_buf = alloca (input_line_pointer - base); | |
2933 | memcpy (save_buf, base, input_line_pointer - base); | |
2934 | memmove (base + (input_line_pointer - before_reloc), | |
2935 | base, before_reloc - base); | |
2936 | ||
2937 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
2938 | expression (&exp); | |
2939 | memcpy (base, save_buf, p - base); | |
2940 | ||
2941 | offset = nbytes - size; | |
2942 | p = frag_more ((int) nbytes); | |
2943 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, | |
2944 | size, &exp, 0, reloc); | |
2945 | } | |
2946 | } | |
2947 | } | |
b99bd4ef | 2948 | } |
c19d1205 | 2949 | while (*input_line_pointer++ == ','); |
b99bd4ef | 2950 | |
c19d1205 ZW |
2951 | /* Put terminator back into stream. */ |
2952 | input_line_pointer --; | |
2953 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
2954 | } |
2955 | ||
b99bd4ef | 2956 | |
c19d1205 | 2957 | /* Parse a .rel31 directive. */ |
b99bd4ef | 2958 | |
c19d1205 ZW |
2959 | static void |
2960 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
2961 | { | |
2962 | expressionS exp; | |
2963 | char *p; | |
2964 | valueT highbit; | |
b99bd4ef | 2965 | |
c19d1205 ZW |
2966 | highbit = 0; |
2967 | if (*input_line_pointer == '1') | |
2968 | highbit = 0x80000000; | |
2969 | else if (*input_line_pointer != '0') | |
2970 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 2971 | |
c19d1205 ZW |
2972 | input_line_pointer++; |
2973 | if (*input_line_pointer != ',') | |
2974 | as_bad (_("missing comma")); | |
2975 | input_line_pointer++; | |
b99bd4ef | 2976 | |
c19d1205 ZW |
2977 | #ifdef md_flush_pending_output |
2978 | md_flush_pending_output (); | |
2979 | #endif | |
b99bd4ef | 2980 | |
c19d1205 ZW |
2981 | #ifdef md_cons_align |
2982 | md_cons_align (4); | |
2983 | #endif | |
b99bd4ef | 2984 | |
c19d1205 | 2985 | mapping_state (MAP_DATA); |
b99bd4ef | 2986 | |
c19d1205 | 2987 | expression (&exp); |
b99bd4ef | 2988 | |
c19d1205 ZW |
2989 | p = frag_more (4); |
2990 | md_number_to_chars (p, highbit, 4); | |
2991 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
2992 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 2993 | |
c19d1205 | 2994 | demand_empty_rest_of_line (); |
b99bd4ef NC |
2995 | } |
2996 | ||
c19d1205 | 2997 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 2998 | |
c19d1205 | 2999 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 3000 | |
c19d1205 ZW |
3001 | static void |
3002 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
3003 | { | |
3004 | demand_empty_rest_of_line (); | |
3005 | /* Mark the start of the function. */ | |
3006 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 3007 | |
c19d1205 ZW |
3008 | /* Reset the rest of the unwind info. */ |
3009 | unwind.opcode_count = 0; | |
3010 | unwind.table_entry = NULL; | |
3011 | unwind.personality_routine = NULL; | |
3012 | unwind.personality_index = -1; | |
3013 | unwind.frame_size = 0; | |
3014 | unwind.fp_offset = 0; | |
3015 | unwind.fp_reg = 13; | |
3016 | unwind.fp_used = 0; | |
3017 | unwind.sp_restored = 0; | |
3018 | } | |
b99bd4ef | 3019 | |
b99bd4ef | 3020 | |
c19d1205 ZW |
3021 | /* Parse a handlerdata directive. Creates the exception handling table entry |
3022 | for the function. */ | |
b99bd4ef | 3023 | |
c19d1205 ZW |
3024 | static void |
3025 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
3026 | { | |
3027 | demand_empty_rest_of_line (); | |
3028 | if (unwind.table_entry) | |
3029 | as_bad (_("dupicate .handlerdata directive")); | |
f02232aa | 3030 | |
c19d1205 ZW |
3031 | create_unwind_entry (1); |
3032 | } | |
a737bd4d | 3033 | |
c19d1205 | 3034 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 3035 | |
c19d1205 ZW |
3036 | static void |
3037 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
3038 | { | |
3039 | long where; | |
3040 | char *ptr; | |
3041 | valueT val; | |
f02232aa | 3042 | |
c19d1205 | 3043 | demand_empty_rest_of_line (); |
f02232aa | 3044 | |
c19d1205 ZW |
3045 | /* Add eh table entry. */ |
3046 | if (unwind.table_entry == NULL) | |
3047 | val = create_unwind_entry (0); | |
3048 | else | |
3049 | val = 0; | |
f02232aa | 3050 | |
c19d1205 ZW |
3051 | /* Add index table entry. This is two words. */ |
3052 | start_unwind_section (unwind.saved_seg, 1); | |
3053 | frag_align (2, 0, 0); | |
3054 | record_alignment (now_seg, 2); | |
b99bd4ef | 3055 | |
c19d1205 ZW |
3056 | ptr = frag_more (8); |
3057 | where = frag_now_fix () - 8; | |
f02232aa | 3058 | |
c19d1205 ZW |
3059 | /* Self relative offset of the function start. */ |
3060 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
3061 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3062 | |
c19d1205 ZW |
3063 | /* Indicate dependency on EHABI-defined personality routines to the |
3064 | linker, if it hasn't been done already. */ | |
3065 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 | |
3066 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
3067 | { | |
3068 | static const char *const name[] = { | |
3069 | "__aeabi_unwind_cpp_pr0", | |
3070 | "__aeabi_unwind_cpp_pr1", | |
3071 | "__aeabi_unwind_cpp_pr2" | |
3072 | }; | |
3073 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); | |
3074 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
3075 | marked_pr_dependency |= 1 << unwind.personality_index; | |
3076 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency | |
3077 | = marked_pr_dependency; | |
3078 | } | |
f02232aa | 3079 | |
c19d1205 ZW |
3080 | if (val) |
3081 | /* Inline exception table entry. */ | |
3082 | md_number_to_chars (ptr + 4, val, 4); | |
3083 | else | |
3084 | /* Self relative offset of the table entry. */ | |
3085 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
3086 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3087 | |
c19d1205 ZW |
3088 | /* Restore the original section. */ |
3089 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
3090 | } | |
f02232aa | 3091 | |
f02232aa | 3092 | |
c19d1205 | 3093 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 3094 | |
c19d1205 ZW |
3095 | static void |
3096 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
3097 | { | |
3098 | demand_empty_rest_of_line (); | |
3099 | if (unwind.personality_routine || unwind.personality_index != -1) | |
3100 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 3101 | |
c19d1205 ZW |
3102 | unwind.personality_index = -2; |
3103 | } | |
b99bd4ef | 3104 | |
b99bd4ef | 3105 | |
c19d1205 | 3106 | /* Parse a personalityindex directive. */ |
b99bd4ef | 3107 | |
c19d1205 ZW |
3108 | static void |
3109 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
3110 | { | |
3111 | expressionS exp; | |
b99bd4ef | 3112 | |
c19d1205 ZW |
3113 | if (unwind.personality_routine || unwind.personality_index != -1) |
3114 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 3115 | |
c19d1205 | 3116 | expression (&exp); |
b99bd4ef | 3117 | |
c19d1205 ZW |
3118 | if (exp.X_op != O_constant |
3119 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 3120 | { |
c19d1205 ZW |
3121 | as_bad (_("bad personality routine number")); |
3122 | ignore_rest_of_line (); | |
3123 | return; | |
b99bd4ef NC |
3124 | } |
3125 | ||
c19d1205 | 3126 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 3127 | |
c19d1205 ZW |
3128 | demand_empty_rest_of_line (); |
3129 | } | |
e16bb312 | 3130 | |
e16bb312 | 3131 | |
c19d1205 | 3132 | /* Parse a personality directive. */ |
e16bb312 | 3133 | |
c19d1205 ZW |
3134 | static void |
3135 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
3136 | { | |
3137 | char *name, *p, c; | |
a737bd4d | 3138 | |
c19d1205 ZW |
3139 | if (unwind.personality_routine || unwind.personality_index != -1) |
3140 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 3141 | |
c19d1205 ZW |
3142 | name = input_line_pointer; |
3143 | c = get_symbol_end (); | |
3144 | p = input_line_pointer; | |
3145 | unwind.personality_routine = symbol_find_or_make (name); | |
3146 | *p = c; | |
3147 | demand_empty_rest_of_line (); | |
3148 | } | |
e16bb312 | 3149 | |
e16bb312 | 3150 | |
c19d1205 | 3151 | /* Parse a directive saving core registers. */ |
e16bb312 | 3152 | |
c19d1205 ZW |
3153 | static void |
3154 | s_arm_unwind_save_core (void) | |
e16bb312 | 3155 | { |
c19d1205 ZW |
3156 | valueT op; |
3157 | long range; | |
3158 | int n; | |
e16bb312 | 3159 | |
c19d1205 ZW |
3160 | range = parse_reg_list (&input_line_pointer); |
3161 | if (range == FAIL) | |
e16bb312 | 3162 | { |
c19d1205 ZW |
3163 | as_bad (_("expected register list")); |
3164 | ignore_rest_of_line (); | |
3165 | return; | |
3166 | } | |
e16bb312 | 3167 | |
c19d1205 | 3168 | demand_empty_rest_of_line (); |
e16bb312 | 3169 | |
c19d1205 ZW |
3170 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
3171 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
3172 | ip because it is clobbered by calls. */ | |
3173 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
3174 | && (range & 0x3000) == 0x1000) | |
3175 | { | |
3176 | unwind.opcode_count--; | |
3177 | unwind.sp_restored = 0; | |
3178 | range = (range | 0x2000) & ~0x1000; | |
3179 | unwind.pending_offset = 0; | |
3180 | } | |
e16bb312 | 3181 | |
01ae4198 DJ |
3182 | /* Pop r4-r15. */ |
3183 | if (range & 0xfff0) | |
c19d1205 | 3184 | { |
01ae4198 DJ |
3185 | /* See if we can use the short opcodes. These pop a block of up to 8 |
3186 | registers starting with r4, plus maybe r14. */ | |
3187 | for (n = 0; n < 8; n++) | |
3188 | { | |
3189 | /* Break at the first non-saved register. */ | |
3190 | if ((range & (1 << (n + 4))) == 0) | |
3191 | break; | |
3192 | } | |
3193 | /* See if there are any other bits set. */ | |
3194 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
3195 | { | |
3196 | /* Use the long form. */ | |
3197 | op = 0x8000 | ((range >> 4) & 0xfff); | |
3198 | add_unwind_opcode (op, 2); | |
3199 | } | |
0dd132b6 | 3200 | else |
01ae4198 DJ |
3201 | { |
3202 | /* Use the short form. */ | |
3203 | if (range & 0x4000) | |
3204 | op = 0xa8; /* Pop r14. */ | |
3205 | else | |
3206 | op = 0xa0; /* Do not pop r14. */ | |
3207 | op |= (n - 1); | |
3208 | add_unwind_opcode (op, 1); | |
3209 | } | |
c19d1205 | 3210 | } |
0dd132b6 | 3211 | |
c19d1205 ZW |
3212 | /* Pop r0-r3. */ |
3213 | if (range & 0xf) | |
3214 | { | |
3215 | op = 0xb100 | (range & 0xf); | |
3216 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
3217 | } |
3218 | ||
c19d1205 ZW |
3219 | /* Record the number of bytes pushed. */ |
3220 | for (n = 0; n < 16; n++) | |
3221 | { | |
3222 | if (range & (1 << n)) | |
3223 | unwind.frame_size += 4; | |
3224 | } | |
0dd132b6 NC |
3225 | } |
3226 | ||
c19d1205 ZW |
3227 | |
3228 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
3229 | |
3230 | static void | |
c19d1205 | 3231 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 3232 | { |
c19d1205 ZW |
3233 | expressionS exp; |
3234 | int num_regs; | |
3235 | valueT op; | |
b99bd4ef | 3236 | |
c19d1205 ZW |
3237 | /* Get Number of registers to transfer. */ |
3238 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
3239 | expression (&exp); | |
3240 | else | |
3241 | exp.X_op = O_illegal; | |
b99bd4ef | 3242 | |
c19d1205 | 3243 | if (exp.X_op != O_constant) |
b99bd4ef | 3244 | { |
c19d1205 ZW |
3245 | as_bad (_("expected , <constant>")); |
3246 | ignore_rest_of_line (); | |
b99bd4ef NC |
3247 | return; |
3248 | } | |
3249 | ||
c19d1205 ZW |
3250 | num_regs = exp.X_add_number; |
3251 | ||
3252 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 3253 | { |
c19d1205 ZW |
3254 | as_bad (_("number of registers must be in the range [1:4]")); |
3255 | ignore_rest_of_line (); | |
b99bd4ef NC |
3256 | return; |
3257 | } | |
3258 | ||
c19d1205 | 3259 | demand_empty_rest_of_line (); |
b99bd4ef | 3260 | |
c19d1205 ZW |
3261 | if (reg == 4) |
3262 | { | |
3263 | /* Short form. */ | |
3264 | op = 0xb4 | (num_regs - 1); | |
3265 | add_unwind_opcode (op, 1); | |
3266 | } | |
b99bd4ef NC |
3267 | else |
3268 | { | |
c19d1205 ZW |
3269 | /* Long form. */ |
3270 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
3271 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3272 | } |
c19d1205 | 3273 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
3274 | } |
3275 | ||
c19d1205 | 3276 | |
fa073d69 MS |
3277 | /* Parse a directive saving VFP registers for ARMv6 and above. */ |
3278 | ||
3279 | static void | |
3280 | s_arm_unwind_save_vfp_armv6 (void) | |
3281 | { | |
3282 | int count; | |
3283 | unsigned int start; | |
3284 | valueT op; | |
3285 | int num_vfpv3_regs = 0; | |
3286 | int num_regs_below_16; | |
3287 | ||
3288 | count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); | |
3289 | if (count == FAIL) | |
3290 | { | |
3291 | as_bad (_("expected register list")); | |
3292 | ignore_rest_of_line (); | |
3293 | return; | |
3294 | } | |
3295 | ||
3296 | demand_empty_rest_of_line (); | |
3297 | ||
3298 | /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather | |
3299 | than FSTMX/FLDMX-style ones). */ | |
3300 | ||
3301 | /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ | |
3302 | if (start >= 16) | |
3303 | num_vfpv3_regs = count; | |
3304 | else if (start + count > 16) | |
3305 | num_vfpv3_regs = start + count - 16; | |
3306 | ||
3307 | if (num_vfpv3_regs > 0) | |
3308 | { | |
3309 | int start_offset = start > 16 ? start - 16 : 0; | |
3310 | op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); | |
3311 | add_unwind_opcode (op, 2); | |
3312 | } | |
3313 | ||
3314 | /* Generate opcode for registers numbered in the range 0 .. 15. */ | |
3315 | num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; | |
3316 | assert (num_regs_below_16 + num_vfpv3_regs == count); | |
3317 | if (num_regs_below_16 > 0) | |
3318 | { | |
3319 | op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); | |
3320 | add_unwind_opcode (op, 2); | |
3321 | } | |
3322 | ||
3323 | unwind.frame_size += count * 8; | |
3324 | } | |
3325 | ||
3326 | ||
3327 | /* Parse a directive saving VFP registers for pre-ARMv6. */ | |
b99bd4ef NC |
3328 | |
3329 | static void | |
c19d1205 | 3330 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 3331 | { |
c19d1205 | 3332 | int count; |
ca3f61f7 | 3333 | unsigned int reg; |
c19d1205 | 3334 | valueT op; |
b99bd4ef | 3335 | |
5287ad62 | 3336 | count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); |
c19d1205 | 3337 | if (count == FAIL) |
b99bd4ef | 3338 | { |
c19d1205 ZW |
3339 | as_bad (_("expected register list")); |
3340 | ignore_rest_of_line (); | |
b99bd4ef NC |
3341 | return; |
3342 | } | |
3343 | ||
c19d1205 | 3344 | demand_empty_rest_of_line (); |
b99bd4ef | 3345 | |
c19d1205 | 3346 | if (reg == 8) |
b99bd4ef | 3347 | { |
c19d1205 ZW |
3348 | /* Short form. */ |
3349 | op = 0xb8 | (count - 1); | |
3350 | add_unwind_opcode (op, 1); | |
b99bd4ef | 3351 | } |
c19d1205 | 3352 | else |
b99bd4ef | 3353 | { |
c19d1205 ZW |
3354 | /* Long form. */ |
3355 | op = 0xb300 | (reg << 4) | (count - 1); | |
3356 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3357 | } |
c19d1205 ZW |
3358 | unwind.frame_size += count * 8 + 4; |
3359 | } | |
b99bd4ef | 3360 | |
b99bd4ef | 3361 | |
c19d1205 ZW |
3362 | /* Parse a directive saving iWMMXt data registers. */ |
3363 | ||
3364 | static void | |
3365 | s_arm_unwind_save_mmxwr (void) | |
3366 | { | |
3367 | int reg; | |
3368 | int hi_reg; | |
3369 | int i; | |
3370 | unsigned mask = 0; | |
3371 | valueT op; | |
b99bd4ef | 3372 | |
c19d1205 ZW |
3373 | if (*input_line_pointer == '{') |
3374 | input_line_pointer++; | |
b99bd4ef | 3375 | |
c19d1205 | 3376 | do |
b99bd4ef | 3377 | { |
dcbf9037 | 3378 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 3379 | |
c19d1205 | 3380 | if (reg == FAIL) |
b99bd4ef | 3381 | { |
c19d1205 ZW |
3382 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); |
3383 | goto error; | |
b99bd4ef NC |
3384 | } |
3385 | ||
c19d1205 ZW |
3386 | if (mask >> reg) |
3387 | as_tsktsk (_("register list not in ascending order")); | |
3388 | mask |= 1 << reg; | |
b99bd4ef | 3389 | |
c19d1205 ZW |
3390 | if (*input_line_pointer == '-') |
3391 | { | |
3392 | input_line_pointer++; | |
dcbf9037 | 3393 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
c19d1205 ZW |
3394 | if (hi_reg == FAIL) |
3395 | { | |
3396 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); | |
3397 | goto error; | |
3398 | } | |
3399 | else if (reg >= hi_reg) | |
3400 | { | |
3401 | as_bad (_("bad register range")); | |
3402 | goto error; | |
3403 | } | |
3404 | for (; reg < hi_reg; reg++) | |
3405 | mask |= 1 << reg; | |
3406 | } | |
3407 | } | |
3408 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 3409 | |
c19d1205 ZW |
3410 | if (*input_line_pointer == '}') |
3411 | input_line_pointer++; | |
b99bd4ef | 3412 | |
c19d1205 | 3413 | demand_empty_rest_of_line (); |
b99bd4ef | 3414 | |
708587a4 | 3415 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
3416 | the list. */ |
3417 | flush_pending_unwind (); | |
b99bd4ef | 3418 | |
c19d1205 | 3419 | for (i = 0; i < 16; i++) |
b99bd4ef | 3420 | { |
c19d1205 ZW |
3421 | if (mask & (1 << i)) |
3422 | unwind.frame_size += 8; | |
b99bd4ef NC |
3423 | } |
3424 | ||
c19d1205 ZW |
3425 | /* Attempt to combine with a previous opcode. We do this because gcc |
3426 | likes to output separate unwind directives for a single block of | |
3427 | registers. */ | |
3428 | if (unwind.opcode_count > 0) | |
b99bd4ef | 3429 | { |
c19d1205 ZW |
3430 | i = unwind.opcodes[unwind.opcode_count - 1]; |
3431 | if ((i & 0xf8) == 0xc0) | |
3432 | { | |
3433 | i &= 7; | |
3434 | /* Only merge if the blocks are contiguous. */ | |
3435 | if (i < 6) | |
3436 | { | |
3437 | if ((mask & 0xfe00) == (1 << 9)) | |
3438 | { | |
3439 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
3440 | unwind.opcode_count--; | |
3441 | } | |
3442 | } | |
3443 | else if (i == 6 && unwind.opcode_count >= 2) | |
3444 | { | |
3445 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
3446 | reg = i >> 4; | |
3447 | i &= 0xf; | |
b99bd4ef | 3448 | |
c19d1205 ZW |
3449 | op = 0xffff << (reg - 1); |
3450 | if (reg > 0 | |
3451 | || ((mask & op) == (1u << (reg - 1)))) | |
3452 | { | |
3453 | op = (1 << (reg + i + 1)) - 1; | |
3454 | op &= ~((1 << reg) - 1); | |
3455 | mask |= op; | |
3456 | unwind.opcode_count -= 2; | |
3457 | } | |
3458 | } | |
3459 | } | |
b99bd4ef NC |
3460 | } |
3461 | ||
c19d1205 ZW |
3462 | hi_reg = 15; |
3463 | /* We want to generate opcodes in the order the registers have been | |
3464 | saved, ie. descending order. */ | |
3465 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 3466 | { |
c19d1205 ZW |
3467 | /* Save registers in blocks. */ |
3468 | if (reg < 0 | |
3469 | || !(mask & (1 << reg))) | |
3470 | { | |
3471 | /* We found an unsaved reg. Generate opcodes to save the | |
3472 | preceeding block. */ | |
3473 | if (reg != hi_reg) | |
3474 | { | |
3475 | if (reg == 9) | |
3476 | { | |
3477 | /* Short form. */ | |
3478 | op = 0xc0 | (hi_reg - 10); | |
3479 | add_unwind_opcode (op, 1); | |
3480 | } | |
3481 | else | |
3482 | { | |
3483 | /* Long form. */ | |
3484 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
3485 | add_unwind_opcode (op, 2); | |
3486 | } | |
3487 | } | |
3488 | hi_reg = reg - 1; | |
3489 | } | |
b99bd4ef NC |
3490 | } |
3491 | ||
c19d1205 ZW |
3492 | return; |
3493 | error: | |
3494 | ignore_rest_of_line (); | |
b99bd4ef NC |
3495 | } |
3496 | ||
3497 | static void | |
c19d1205 | 3498 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 3499 | { |
c19d1205 ZW |
3500 | int reg; |
3501 | int hi_reg; | |
3502 | unsigned mask = 0; | |
3503 | valueT op; | |
b99bd4ef | 3504 | |
c19d1205 ZW |
3505 | if (*input_line_pointer == '{') |
3506 | input_line_pointer++; | |
b99bd4ef | 3507 | |
c19d1205 | 3508 | do |
b99bd4ef | 3509 | { |
dcbf9037 | 3510 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 3511 | |
c19d1205 ZW |
3512 | if (reg == FAIL) |
3513 | { | |
3514 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); | |
3515 | goto error; | |
3516 | } | |
b99bd4ef | 3517 | |
c19d1205 ZW |
3518 | reg -= 8; |
3519 | if (mask >> reg) | |
3520 | as_tsktsk (_("register list not in ascending order")); | |
3521 | mask |= 1 << reg; | |
b99bd4ef | 3522 | |
c19d1205 ZW |
3523 | if (*input_line_pointer == '-') |
3524 | { | |
3525 | input_line_pointer++; | |
dcbf9037 | 3526 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
c19d1205 ZW |
3527 | if (hi_reg == FAIL) |
3528 | { | |
3529 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); | |
3530 | goto error; | |
3531 | } | |
3532 | else if (reg >= hi_reg) | |
3533 | { | |
3534 | as_bad (_("bad register range")); | |
3535 | goto error; | |
3536 | } | |
3537 | for (; reg < hi_reg; reg++) | |
3538 | mask |= 1 << reg; | |
3539 | } | |
b99bd4ef | 3540 | } |
c19d1205 | 3541 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 3542 | |
c19d1205 ZW |
3543 | if (*input_line_pointer == '}') |
3544 | input_line_pointer++; | |
b99bd4ef | 3545 | |
c19d1205 ZW |
3546 | demand_empty_rest_of_line (); |
3547 | ||
708587a4 | 3548 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
3549 | the list. */ |
3550 | flush_pending_unwind (); | |
b99bd4ef | 3551 | |
c19d1205 | 3552 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 3553 | { |
c19d1205 ZW |
3554 | if (mask & (1 << reg)) |
3555 | unwind.frame_size += 4; | |
b99bd4ef | 3556 | } |
c19d1205 ZW |
3557 | op = 0xc700 | mask; |
3558 | add_unwind_opcode (op, 2); | |
3559 | return; | |
3560 | error: | |
3561 | ignore_rest_of_line (); | |
b99bd4ef NC |
3562 | } |
3563 | ||
c19d1205 | 3564 | |
fa073d69 MS |
3565 | /* Parse an unwind_save directive. |
3566 | If the argument is non-zero, this is a .vsave directive. */ | |
c19d1205 | 3567 | |
b99bd4ef | 3568 | static void |
fa073d69 | 3569 | s_arm_unwind_save (int arch_v6) |
b99bd4ef | 3570 | { |
c19d1205 ZW |
3571 | char *peek; |
3572 | struct reg_entry *reg; | |
3573 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 3574 | |
c19d1205 ZW |
3575 | /* Figure out what sort of save we have. */ |
3576 | peek = input_line_pointer; | |
b99bd4ef | 3577 | |
c19d1205 | 3578 | if (*peek == '{') |
b99bd4ef | 3579 | { |
c19d1205 ZW |
3580 | had_brace = TRUE; |
3581 | peek++; | |
b99bd4ef NC |
3582 | } |
3583 | ||
c19d1205 | 3584 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 3585 | |
c19d1205 | 3586 | if (!reg) |
b99bd4ef | 3587 | { |
c19d1205 ZW |
3588 | as_bad (_("register expected")); |
3589 | ignore_rest_of_line (); | |
b99bd4ef NC |
3590 | return; |
3591 | } | |
3592 | ||
c19d1205 | 3593 | switch (reg->type) |
b99bd4ef | 3594 | { |
c19d1205 ZW |
3595 | case REG_TYPE_FN: |
3596 | if (had_brace) | |
3597 | { | |
3598 | as_bad (_("FPA .unwind_save does not take a register list")); | |
3599 | ignore_rest_of_line (); | |
3600 | return; | |
3601 | } | |
3602 | s_arm_unwind_save_fpa (reg->number); | |
b99bd4ef | 3603 | return; |
c19d1205 ZW |
3604 | |
3605 | case REG_TYPE_RN: s_arm_unwind_save_core (); return; | |
fa073d69 MS |
3606 | case REG_TYPE_VFD: |
3607 | if (arch_v6) | |
3608 | s_arm_unwind_save_vfp_armv6 (); | |
3609 | else | |
3610 | s_arm_unwind_save_vfp (); | |
3611 | return; | |
c19d1205 ZW |
3612 | case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; |
3613 | case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; | |
3614 | ||
3615 | default: | |
3616 | as_bad (_(".unwind_save does not support this kind of register")); | |
3617 | ignore_rest_of_line (); | |
b99bd4ef | 3618 | } |
c19d1205 | 3619 | } |
b99bd4ef | 3620 | |
b99bd4ef | 3621 | |
c19d1205 ZW |
3622 | /* Parse an unwind_movsp directive. */ |
3623 | ||
3624 | static void | |
3625 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
3626 | { | |
3627 | int reg; | |
3628 | valueT op; | |
3629 | ||
dcbf9037 | 3630 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 | 3631 | if (reg == FAIL) |
b99bd4ef | 3632 | { |
c19d1205 ZW |
3633 | as_bad (_(reg_expected_msgs[REG_TYPE_RN])); |
3634 | ignore_rest_of_line (); | |
b99bd4ef NC |
3635 | return; |
3636 | } | |
c19d1205 | 3637 | demand_empty_rest_of_line (); |
b99bd4ef | 3638 | |
c19d1205 | 3639 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 3640 | { |
c19d1205 | 3641 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
3642 | return; |
3643 | } | |
3644 | ||
c19d1205 ZW |
3645 | if (unwind.fp_reg != REG_SP) |
3646 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 3647 | |
c19d1205 ZW |
3648 | /* Generate opcode to restore the value. */ |
3649 | op = 0x90 | reg; | |
3650 | add_unwind_opcode (op, 1); | |
3651 | ||
3652 | /* Record the information for later. */ | |
3653 | unwind.fp_reg = reg; | |
3654 | unwind.fp_offset = unwind.frame_size; | |
3655 | unwind.sp_restored = 1; | |
b05fe5cf ZW |
3656 | } |
3657 | ||
c19d1205 ZW |
3658 | /* Parse an unwind_pad directive. */ |
3659 | ||
b05fe5cf | 3660 | static void |
c19d1205 | 3661 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 3662 | { |
c19d1205 | 3663 | int offset; |
b05fe5cf | 3664 | |
c19d1205 ZW |
3665 | if (immediate_for_directive (&offset) == FAIL) |
3666 | return; | |
b99bd4ef | 3667 | |
c19d1205 ZW |
3668 | if (offset & 3) |
3669 | { | |
3670 | as_bad (_("stack increment must be multiple of 4")); | |
3671 | ignore_rest_of_line (); | |
3672 | return; | |
3673 | } | |
b99bd4ef | 3674 | |
c19d1205 ZW |
3675 | /* Don't generate any opcodes, just record the details for later. */ |
3676 | unwind.frame_size += offset; | |
3677 | unwind.pending_offset += offset; | |
3678 | ||
3679 | demand_empty_rest_of_line (); | |
3680 | } | |
3681 | ||
3682 | /* Parse an unwind_setfp directive. */ | |
3683 | ||
3684 | static void | |
3685 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 3686 | { |
c19d1205 ZW |
3687 | int sp_reg; |
3688 | int fp_reg; | |
3689 | int offset; | |
3690 | ||
dcbf9037 | 3691 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 ZW |
3692 | if (skip_past_comma (&input_line_pointer) == FAIL) |
3693 | sp_reg = FAIL; | |
3694 | else | |
dcbf9037 | 3695 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
b99bd4ef | 3696 | |
c19d1205 ZW |
3697 | if (fp_reg == FAIL || sp_reg == FAIL) |
3698 | { | |
3699 | as_bad (_("expected <reg>, <reg>")); | |
3700 | ignore_rest_of_line (); | |
3701 | return; | |
3702 | } | |
b99bd4ef | 3703 | |
c19d1205 ZW |
3704 | /* Optional constant. */ |
3705 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
3706 | { | |
3707 | if (immediate_for_directive (&offset) == FAIL) | |
3708 | return; | |
3709 | } | |
3710 | else | |
3711 | offset = 0; | |
a737bd4d | 3712 | |
c19d1205 | 3713 | demand_empty_rest_of_line (); |
a737bd4d | 3714 | |
c19d1205 | 3715 | if (sp_reg != 13 && sp_reg != unwind.fp_reg) |
a737bd4d | 3716 | { |
c19d1205 ZW |
3717 | as_bad (_("register must be either sp or set by a previous" |
3718 | "unwind_movsp directive")); | |
3719 | return; | |
a737bd4d NC |
3720 | } |
3721 | ||
c19d1205 ZW |
3722 | /* Don't generate any opcodes, just record the information for later. */ |
3723 | unwind.fp_reg = fp_reg; | |
3724 | unwind.fp_used = 1; | |
3725 | if (sp_reg == 13) | |
3726 | unwind.fp_offset = unwind.frame_size - offset; | |
3727 | else | |
3728 | unwind.fp_offset -= offset; | |
a737bd4d NC |
3729 | } |
3730 | ||
c19d1205 ZW |
3731 | /* Parse an unwind_raw directive. */ |
3732 | ||
3733 | static void | |
3734 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 3735 | { |
c19d1205 | 3736 | expressionS exp; |
708587a4 | 3737 | /* This is an arbitrary limit. */ |
c19d1205 ZW |
3738 | unsigned char op[16]; |
3739 | int count; | |
a737bd4d | 3740 | |
c19d1205 ZW |
3741 | expression (&exp); |
3742 | if (exp.X_op == O_constant | |
3743 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 3744 | { |
c19d1205 ZW |
3745 | unwind.frame_size += exp.X_add_number; |
3746 | expression (&exp); | |
3747 | } | |
3748 | else | |
3749 | exp.X_op = O_illegal; | |
a737bd4d | 3750 | |
c19d1205 ZW |
3751 | if (exp.X_op != O_constant) |
3752 | { | |
3753 | as_bad (_("expected <offset>, <opcode>")); | |
3754 | ignore_rest_of_line (); | |
3755 | return; | |
3756 | } | |
a737bd4d | 3757 | |
c19d1205 | 3758 | count = 0; |
a737bd4d | 3759 | |
c19d1205 ZW |
3760 | /* Parse the opcode. */ |
3761 | for (;;) | |
3762 | { | |
3763 | if (count >= 16) | |
3764 | { | |
3765 | as_bad (_("unwind opcode too long")); | |
3766 | ignore_rest_of_line (); | |
a737bd4d | 3767 | } |
c19d1205 | 3768 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 3769 | { |
c19d1205 ZW |
3770 | as_bad (_("invalid unwind opcode")); |
3771 | ignore_rest_of_line (); | |
3772 | return; | |
a737bd4d | 3773 | } |
c19d1205 | 3774 | op[count++] = exp.X_add_number; |
a737bd4d | 3775 | |
c19d1205 ZW |
3776 | /* Parse the next byte. */ |
3777 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
3778 | break; | |
a737bd4d | 3779 | |
c19d1205 ZW |
3780 | expression (&exp); |
3781 | } | |
b99bd4ef | 3782 | |
c19d1205 ZW |
3783 | /* Add the opcode bytes in reverse order. */ |
3784 | while (count--) | |
3785 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 3786 | |
c19d1205 | 3787 | demand_empty_rest_of_line (); |
b99bd4ef | 3788 | } |
ee065d83 PB |
3789 | |
3790 | ||
3791 | /* Parse a .eabi_attribute directive. */ | |
3792 | ||
3793 | static void | |
3794 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) | |
3795 | { | |
3796 | expressionS exp; | |
3797 | bfd_boolean is_string; | |
3798 | int tag; | |
3799 | unsigned int i = 0; | |
3800 | char *s = NULL; | |
3801 | char saved_char; | |
3802 | ||
3803 | expression (& exp); | |
3804 | if (exp.X_op != O_constant) | |
3805 | goto bad; | |
3806 | ||
3807 | tag = exp.X_add_number; | |
3808 | if (tag == 4 || tag == 5 || tag == 32 || (tag > 32 && (tag & 1) != 0)) | |
3809 | is_string = 1; | |
3810 | else | |
3811 | is_string = 0; | |
3812 | ||
3813 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
3814 | goto bad; | |
3815 | if (tag == 32 || !is_string) | |
3816 | { | |
3817 | expression (& exp); | |
3818 | if (exp.X_op != O_constant) | |
3819 | { | |
3820 | as_bad (_("expected numeric constant")); | |
3821 | ignore_rest_of_line (); | |
3822 | return; | |
3823 | } | |
3824 | i = exp.X_add_number; | |
3825 | } | |
3826 | if (tag == Tag_compatibility | |
3827 | && skip_past_comma (&input_line_pointer) == FAIL) | |
3828 | { | |
3829 | as_bad (_("expected comma")); | |
3830 | ignore_rest_of_line (); | |
3831 | return; | |
3832 | } | |
3833 | if (is_string) | |
3834 | { | |
3835 | skip_whitespace(input_line_pointer); | |
3836 | if (*input_line_pointer != '"') | |
3837 | goto bad_string; | |
3838 | input_line_pointer++; | |
3839 | s = input_line_pointer; | |
3840 | while (*input_line_pointer && *input_line_pointer != '"') | |
3841 | input_line_pointer++; | |
3842 | if (*input_line_pointer != '"') | |
3843 | goto bad_string; | |
3844 | saved_char = *input_line_pointer; | |
3845 | *input_line_pointer = 0; | |
3846 | } | |
3847 | else | |
3848 | { | |
3849 | s = NULL; | |
3850 | saved_char = 0; | |
3851 | } | |
3852 | ||
3853 | if (tag == Tag_compatibility) | |
3854 | elf32_arm_add_eabi_attr_compat (stdoutput, i, s); | |
3855 | else if (is_string) | |
3856 | elf32_arm_add_eabi_attr_string (stdoutput, tag, s); | |
3857 | else | |
3858 | elf32_arm_add_eabi_attr_int (stdoutput, tag, i); | |
3859 | ||
3860 | if (s) | |
3861 | { | |
3862 | *input_line_pointer = saved_char; | |
3863 | input_line_pointer++; | |
3864 | } | |
3865 | demand_empty_rest_of_line (); | |
3866 | return; | |
3867 | bad_string: | |
3868 | as_bad (_("bad string constant")); | |
3869 | ignore_rest_of_line (); | |
3870 | return; | |
3871 | bad: | |
3872 | as_bad (_("expected <tag> , <value>")); | |
3873 | ignore_rest_of_line (); | |
3874 | } | |
8463be01 | 3875 | #endif /* OBJ_ELF */ |
ee065d83 PB |
3876 | |
3877 | static void s_arm_arch (int); | |
3878 | static void s_arm_cpu (int); | |
3879 | static void s_arm_fpu (int); | |
b99bd4ef | 3880 | |
c19d1205 ZW |
3881 | /* This table describes all the machine specific pseudo-ops the assembler |
3882 | has to support. The fields are: | |
3883 | pseudo-op name without dot | |
3884 | function to call to execute this pseudo-op | |
3885 | Integer arg to pass to the function. */ | |
b99bd4ef | 3886 | |
c19d1205 | 3887 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 3888 | { |
c19d1205 ZW |
3889 | /* Never called because '.req' does not start a line. */ |
3890 | { "req", s_req, 0 }, | |
dcbf9037 JB |
3891 | /* Following two are likewise never called. */ |
3892 | { "dn", s_dn, 0 }, | |
3893 | { "qn", s_qn, 0 }, | |
c19d1205 ZW |
3894 | { "unreq", s_unreq, 0 }, |
3895 | { "bss", s_bss, 0 }, | |
3896 | { "align", s_align, 0 }, | |
3897 | { "arm", s_arm, 0 }, | |
3898 | { "thumb", s_thumb, 0 }, | |
3899 | { "code", s_code, 0 }, | |
3900 | { "force_thumb", s_force_thumb, 0 }, | |
3901 | { "thumb_func", s_thumb_func, 0 }, | |
3902 | { "thumb_set", s_thumb_set, 0 }, | |
3903 | { "even", s_even, 0 }, | |
3904 | { "ltorg", s_ltorg, 0 }, | |
3905 | { "pool", s_ltorg, 0 }, | |
3906 | { "syntax", s_syntax, 0 }, | |
8463be01 PB |
3907 | { "cpu", s_arm_cpu, 0 }, |
3908 | { "arch", s_arm_arch, 0 }, | |
3909 | { "fpu", s_arm_fpu, 0 }, | |
c19d1205 ZW |
3910 | #ifdef OBJ_ELF |
3911 | { "word", s_arm_elf_cons, 4 }, | |
3912 | { "long", s_arm_elf_cons, 4 }, | |
3913 | { "rel31", s_arm_rel31, 0 }, | |
3914 | { "fnstart", s_arm_unwind_fnstart, 0 }, | |
3915 | { "fnend", s_arm_unwind_fnend, 0 }, | |
3916 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
3917 | { "personality", s_arm_unwind_personality, 0 }, | |
3918 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
3919 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
3920 | { "save", s_arm_unwind_save, 0 }, | |
fa073d69 | 3921 | { "vsave", s_arm_unwind_save, 1 }, |
c19d1205 ZW |
3922 | { "movsp", s_arm_unwind_movsp, 0 }, |
3923 | { "pad", s_arm_unwind_pad, 0 }, | |
3924 | { "setfp", s_arm_unwind_setfp, 0 }, | |
3925 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
ee065d83 | 3926 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, |
c19d1205 ZW |
3927 | #else |
3928 | { "word", cons, 4}, | |
3929 | #endif | |
3930 | { "extend", float_cons, 'x' }, | |
3931 | { "ldouble", float_cons, 'x' }, | |
3932 | { "packed", float_cons, 'p' }, | |
3933 | { 0, 0, 0 } | |
3934 | }; | |
3935 | \f | |
3936 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 3937 | |
c19d1205 ZW |
3938 | /* Generic immediate-value read function for use in insn parsing. |
3939 | STR points to the beginning of the immediate (the leading #); | |
3940 | VAL receives the value; if the value is outside [MIN, MAX] | |
3941 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
3942 | optional. */ | |
b99bd4ef | 3943 | |
c19d1205 ZW |
3944 | static int |
3945 | parse_immediate (char **str, int *val, int min, int max, | |
3946 | bfd_boolean prefix_opt) | |
3947 | { | |
3948 | expressionS exp; | |
3949 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); | |
3950 | if (exp.X_op != O_constant) | |
b99bd4ef | 3951 | { |
c19d1205 ZW |
3952 | inst.error = _("constant expression required"); |
3953 | return FAIL; | |
3954 | } | |
b99bd4ef | 3955 | |
c19d1205 ZW |
3956 | if (exp.X_add_number < min || exp.X_add_number > max) |
3957 | { | |
3958 | inst.error = _("immediate value out of range"); | |
3959 | return FAIL; | |
3960 | } | |
b99bd4ef | 3961 | |
c19d1205 ZW |
3962 | *val = exp.X_add_number; |
3963 | return SUCCESS; | |
3964 | } | |
b99bd4ef | 3965 | |
5287ad62 JB |
3966 | /* Less-generic immediate-value read function with the possibility of loading a |
3967 | big (64-bit) immediate, as required by Neon VMOV and VMVN immediate | |
3968 | instructions. Puts the result directly in inst.operands[i]. */ | |
3969 | ||
3970 | static int | |
3971 | parse_big_immediate (char **str, int i) | |
3972 | { | |
3973 | expressionS exp; | |
3974 | char *ptr = *str; | |
3975 | ||
3976 | my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); | |
3977 | ||
3978 | if (exp.X_op == O_constant) | |
3979 | inst.operands[i].imm = exp.X_add_number; | |
3980 | else if (exp.X_op == O_big | |
3981 | && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32 | |
3982 | && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64) | |
3983 | { | |
3984 | unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; | |
3985 | /* Bignums have their least significant bits in | |
3986 | generic_bignum[0]. Make sure we put 32 bits in imm and | |
3987 | 32 bits in reg, in a (hopefully) portable way. */ | |
3988 | assert (parts != 0); | |
3989 | inst.operands[i].imm = 0; | |
3990 | for (j = 0; j < parts; j++, idx++) | |
3991 | inst.operands[i].imm |= generic_bignum[idx] | |
3992 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
3993 | inst.operands[i].reg = 0; | |
3994 | for (j = 0; j < parts; j++, idx++) | |
3995 | inst.operands[i].reg |= generic_bignum[idx] | |
3996 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
3997 | inst.operands[i].regisimm = 1; | |
3998 | } | |
3999 | else | |
4000 | return FAIL; | |
4001 | ||
4002 | *str = ptr; | |
4003 | ||
4004 | return SUCCESS; | |
4005 | } | |
4006 | ||
c19d1205 ZW |
4007 | /* Returns the pseudo-register number of an FPA immediate constant, |
4008 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 4009 | |
c19d1205 ZW |
4010 | static int |
4011 | parse_fpa_immediate (char ** str) | |
4012 | { | |
4013 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4014 | char * save_in; | |
4015 | expressionS exp; | |
4016 | int i; | |
4017 | int j; | |
b99bd4ef | 4018 | |
c19d1205 ZW |
4019 | /* First try and match exact strings, this is to guarantee |
4020 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 4021 | |
c19d1205 ZW |
4022 | for (i = 0; fp_const[i]; i++) |
4023 | { | |
4024 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 4025 | { |
c19d1205 | 4026 | char *start = *str; |
b99bd4ef | 4027 | |
c19d1205 ZW |
4028 | *str += strlen (fp_const[i]); |
4029 | if (is_end_of_line[(unsigned char) **str]) | |
4030 | return i + 8; | |
4031 | *str = start; | |
4032 | } | |
4033 | } | |
b99bd4ef | 4034 | |
c19d1205 ZW |
4035 | /* Just because we didn't get a match doesn't mean that the constant |
4036 | isn't valid, just that it is in a format that we don't | |
4037 | automatically recognize. Try parsing it with the standard | |
4038 | expression routines. */ | |
b99bd4ef | 4039 | |
c19d1205 | 4040 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 4041 | |
c19d1205 ZW |
4042 | /* Look for a raw floating point number. */ |
4043 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
4044 | && is_end_of_line[(unsigned char) *save_in]) | |
4045 | { | |
4046 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4047 | { | |
4048 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 4049 | { |
c19d1205 ZW |
4050 | if (words[j] != fp_values[i][j]) |
4051 | break; | |
b99bd4ef NC |
4052 | } |
4053 | ||
c19d1205 | 4054 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 4055 | { |
c19d1205 ZW |
4056 | *str = save_in; |
4057 | return i + 8; | |
b99bd4ef NC |
4058 | } |
4059 | } | |
4060 | } | |
b99bd4ef | 4061 | |
c19d1205 ZW |
4062 | /* Try and parse a more complex expression, this will probably fail |
4063 | unless the code uses a floating point prefix (eg "0f"). */ | |
4064 | save_in = input_line_pointer; | |
4065 | input_line_pointer = *str; | |
4066 | if (expression (&exp) == absolute_section | |
4067 | && exp.X_op == O_big | |
4068 | && exp.X_add_number < 0) | |
4069 | { | |
4070 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
4071 | Ditto for 15. */ | |
4072 | if (gen_to_words (words, 5, (long) 15) == 0) | |
4073 | { | |
4074 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4075 | { | |
4076 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
4077 | { | |
4078 | if (words[j] != fp_values[i][j]) | |
4079 | break; | |
4080 | } | |
b99bd4ef | 4081 | |
c19d1205 ZW |
4082 | if (j == MAX_LITTLENUMS) |
4083 | { | |
4084 | *str = input_line_pointer; | |
4085 | input_line_pointer = save_in; | |
4086 | return i + 8; | |
4087 | } | |
4088 | } | |
4089 | } | |
b99bd4ef NC |
4090 | } |
4091 | ||
c19d1205 ZW |
4092 | *str = input_line_pointer; |
4093 | input_line_pointer = save_in; | |
4094 | inst.error = _("invalid FPA immediate expression"); | |
4095 | return FAIL; | |
b99bd4ef NC |
4096 | } |
4097 | ||
136da414 JB |
4098 | /* Returns 1 if a number has "quarter-precision" float format |
4099 | 0baBbbbbbc defgh000 00000000 00000000. */ | |
4100 | ||
4101 | static int | |
4102 | is_quarter_float (unsigned imm) | |
4103 | { | |
4104 | int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; | |
4105 | return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; | |
4106 | } | |
4107 | ||
4108 | /* Parse an 8-bit "quarter-precision" floating point number of the form: | |
4109 | 0baBbbbbbc defgh000 00000000 00000000. | |
4110 | The minus-zero case needs special handling, since it can't be encoded in the | |
4111 | "quarter-precision" float format, but can nonetheless be loaded as an integer | |
4112 | constant. */ | |
4113 | ||
4114 | static unsigned | |
4115 | parse_qfloat_immediate (char **ccp, int *immed) | |
4116 | { | |
4117 | char *str = *ccp; | |
4118 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4119 | ||
4120 | skip_past_char (&str, '#'); | |
4121 | ||
4122 | if ((str = atof_ieee (str, 's', words)) != NULL) | |
4123 | { | |
4124 | unsigned fpword = 0; | |
4125 | int i; | |
4126 | ||
4127 | /* Our FP word must be 32 bits (single-precision FP). */ | |
4128 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) | |
4129 | { | |
4130 | fpword <<= LITTLENUM_NUMBER_OF_BITS; | |
4131 | fpword |= words[i]; | |
4132 | } | |
4133 | ||
4134 | if (is_quarter_float (fpword) || fpword == 0x80000000) | |
4135 | *immed = fpword; | |
4136 | else | |
4137 | return FAIL; | |
4138 | ||
4139 | *ccp = str; | |
4140 | ||
4141 | return SUCCESS; | |
4142 | } | |
4143 | ||
4144 | return FAIL; | |
4145 | } | |
4146 | ||
c19d1205 ZW |
4147 | /* Shift operands. */ |
4148 | enum shift_kind | |
b99bd4ef | 4149 | { |
c19d1205 ZW |
4150 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX |
4151 | }; | |
b99bd4ef | 4152 | |
c19d1205 ZW |
4153 | struct asm_shift_name |
4154 | { | |
4155 | const char *name; | |
4156 | enum shift_kind kind; | |
4157 | }; | |
b99bd4ef | 4158 | |
c19d1205 ZW |
4159 | /* Third argument to parse_shift. */ |
4160 | enum parse_shift_mode | |
4161 | { | |
4162 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
4163 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
4164 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
4165 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
4166 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
4167 | }; | |
b99bd4ef | 4168 | |
c19d1205 ZW |
4169 | /* Parse a <shift> specifier on an ARM data processing instruction. |
4170 | This has three forms: | |
b99bd4ef | 4171 | |
c19d1205 ZW |
4172 | (LSL|LSR|ASL|ASR|ROR) Rs |
4173 | (LSL|LSR|ASL|ASR|ROR) #imm | |
4174 | RRX | |
b99bd4ef | 4175 | |
c19d1205 ZW |
4176 | Note that ASL is assimilated to LSL in the instruction encoding, and |
4177 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 4178 | |
c19d1205 ZW |
4179 | static int |
4180 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 4181 | { |
c19d1205 ZW |
4182 | const struct asm_shift_name *shift_name; |
4183 | enum shift_kind shift; | |
4184 | char *s = *str; | |
4185 | char *p = s; | |
4186 | int reg; | |
b99bd4ef | 4187 | |
c19d1205 ZW |
4188 | for (p = *str; ISALPHA (*p); p++) |
4189 | ; | |
b99bd4ef | 4190 | |
c19d1205 | 4191 | if (p == *str) |
b99bd4ef | 4192 | { |
c19d1205 ZW |
4193 | inst.error = _("shift expression expected"); |
4194 | return FAIL; | |
b99bd4ef NC |
4195 | } |
4196 | ||
c19d1205 ZW |
4197 | shift_name = hash_find_n (arm_shift_hsh, *str, p - *str); |
4198 | ||
4199 | if (shift_name == NULL) | |
b99bd4ef | 4200 | { |
c19d1205 ZW |
4201 | inst.error = _("shift expression expected"); |
4202 | return FAIL; | |
b99bd4ef NC |
4203 | } |
4204 | ||
c19d1205 | 4205 | shift = shift_name->kind; |
b99bd4ef | 4206 | |
c19d1205 ZW |
4207 | switch (mode) |
4208 | { | |
4209 | case NO_SHIFT_RESTRICT: | |
4210 | case SHIFT_IMMEDIATE: break; | |
b99bd4ef | 4211 | |
c19d1205 ZW |
4212 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
4213 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
4214 | { | |
4215 | inst.error = _("'LSL' or 'ASR' required"); | |
4216 | return FAIL; | |
4217 | } | |
4218 | break; | |
b99bd4ef | 4219 | |
c19d1205 ZW |
4220 | case SHIFT_LSL_IMMEDIATE: |
4221 | if (shift != SHIFT_LSL) | |
4222 | { | |
4223 | inst.error = _("'LSL' required"); | |
4224 | return FAIL; | |
4225 | } | |
4226 | break; | |
b99bd4ef | 4227 | |
c19d1205 ZW |
4228 | case SHIFT_ASR_IMMEDIATE: |
4229 | if (shift != SHIFT_ASR) | |
4230 | { | |
4231 | inst.error = _("'ASR' required"); | |
4232 | return FAIL; | |
4233 | } | |
4234 | break; | |
b99bd4ef | 4235 | |
c19d1205 ZW |
4236 | default: abort (); |
4237 | } | |
b99bd4ef | 4238 | |
c19d1205 ZW |
4239 | if (shift != SHIFT_RRX) |
4240 | { | |
4241 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
4242 | skip_whitespace (p); | |
b99bd4ef | 4243 | |
c19d1205 | 4244 | if (mode == NO_SHIFT_RESTRICT |
dcbf9037 | 4245 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4246 | { |
4247 | inst.operands[i].imm = reg; | |
4248 | inst.operands[i].immisreg = 1; | |
4249 | } | |
4250 | else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4251 | return FAIL; | |
4252 | } | |
4253 | inst.operands[i].shift_kind = shift; | |
4254 | inst.operands[i].shifted = 1; | |
4255 | *str = p; | |
4256 | return SUCCESS; | |
b99bd4ef NC |
4257 | } |
4258 | ||
c19d1205 | 4259 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 4260 | |
c19d1205 ZW |
4261 | #<immediate> |
4262 | #<immediate>, <rotate> | |
4263 | <Rm> | |
4264 | <Rm>, <shift> | |
b99bd4ef | 4265 | |
c19d1205 ZW |
4266 | where <shift> is defined by parse_shift above, and <rotate> is a |
4267 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 4268 | is deferred to md_apply_fix. */ |
b99bd4ef | 4269 | |
c19d1205 ZW |
4270 | static int |
4271 | parse_shifter_operand (char **str, int i) | |
4272 | { | |
4273 | int value; | |
4274 | expressionS expr; | |
b99bd4ef | 4275 | |
dcbf9037 | 4276 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4277 | { |
4278 | inst.operands[i].reg = value; | |
4279 | inst.operands[i].isreg = 1; | |
b99bd4ef | 4280 | |
c19d1205 ZW |
4281 | /* parse_shift will override this if appropriate */ |
4282 | inst.reloc.exp.X_op = O_constant; | |
4283 | inst.reloc.exp.X_add_number = 0; | |
b99bd4ef | 4284 | |
c19d1205 ZW |
4285 | if (skip_past_comma (str) == FAIL) |
4286 | return SUCCESS; | |
b99bd4ef | 4287 | |
c19d1205 ZW |
4288 | /* Shift operation on register. */ |
4289 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
4290 | } |
4291 | ||
c19d1205 ZW |
4292 | if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) |
4293 | return FAIL; | |
b99bd4ef | 4294 | |
c19d1205 | 4295 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 4296 | { |
c19d1205 ZW |
4297 | /* #x, y -- ie explicit rotation by Y. */ |
4298 | if (my_get_expression (&expr, str, GE_NO_PREFIX)) | |
4299 | return FAIL; | |
b99bd4ef | 4300 | |
c19d1205 ZW |
4301 | if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant) |
4302 | { | |
4303 | inst.error = _("constant expression expected"); | |
4304 | return FAIL; | |
4305 | } | |
b99bd4ef | 4306 | |
c19d1205 ZW |
4307 | value = expr.X_add_number; |
4308 | if (value < 0 || value > 30 || value % 2 != 0) | |
4309 | { | |
4310 | inst.error = _("invalid rotation"); | |
4311 | return FAIL; | |
4312 | } | |
4313 | if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) | |
4314 | { | |
4315 | inst.error = _("invalid constant"); | |
4316 | return FAIL; | |
4317 | } | |
09d92015 | 4318 | |
55cf6793 | 4319 | /* Convert to decoded value. md_apply_fix will put it back. */ |
c19d1205 ZW |
4320 | inst.reloc.exp.X_add_number |
4321 | = (((inst.reloc.exp.X_add_number << (32 - value)) | |
4322 | | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff); | |
09d92015 MM |
4323 | } |
4324 | ||
c19d1205 ZW |
4325 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; |
4326 | inst.reloc.pc_rel = 0; | |
4327 | return SUCCESS; | |
09d92015 MM |
4328 | } |
4329 | ||
4962c51a MS |
4330 | /* Group relocation information. Each entry in the table contains the |
4331 | textual name of the relocation as may appear in assembler source | |
4332 | and must end with a colon. | |
4333 | Along with this textual name are the relocation codes to be used if | |
4334 | the corresponding instruction is an ALU instruction (ADD or SUB only), | |
4335 | an LDR, an LDRS, or an LDC. */ | |
4336 | ||
4337 | struct group_reloc_table_entry | |
4338 | { | |
4339 | const char *name; | |
4340 | int alu_code; | |
4341 | int ldr_code; | |
4342 | int ldrs_code; | |
4343 | int ldc_code; | |
4344 | }; | |
4345 | ||
4346 | typedef enum | |
4347 | { | |
4348 | /* Varieties of non-ALU group relocation. */ | |
4349 | ||
4350 | GROUP_LDR, | |
4351 | GROUP_LDRS, | |
4352 | GROUP_LDC | |
4353 | } group_reloc_type; | |
4354 | ||
4355 | static struct group_reloc_table_entry group_reloc_table[] = | |
4356 | { /* Program counter relative: */ | |
4357 | { "pc_g0_nc", | |
4358 | BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ | |
4359 | 0, /* LDR */ | |
4360 | 0, /* LDRS */ | |
4361 | 0 }, /* LDC */ | |
4362 | { "pc_g0", | |
4363 | BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ | |
4364 | BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ | |
4365 | BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ | |
4366 | BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ | |
4367 | { "pc_g1_nc", | |
4368 | BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ | |
4369 | 0, /* LDR */ | |
4370 | 0, /* LDRS */ | |
4371 | 0 }, /* LDC */ | |
4372 | { "pc_g1", | |
4373 | BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ | |
4374 | BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ | |
4375 | BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ | |
4376 | BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ | |
4377 | { "pc_g2", | |
4378 | BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ | |
4379 | BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ | |
4380 | BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ | |
4381 | BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ | |
4382 | /* Section base relative */ | |
4383 | { "sb_g0_nc", | |
4384 | BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ | |
4385 | 0, /* LDR */ | |
4386 | 0, /* LDRS */ | |
4387 | 0 }, /* LDC */ | |
4388 | { "sb_g0", | |
4389 | BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ | |
4390 | BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ | |
4391 | BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ | |
4392 | BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ | |
4393 | { "sb_g1_nc", | |
4394 | BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ | |
4395 | 0, /* LDR */ | |
4396 | 0, /* LDRS */ | |
4397 | 0 }, /* LDC */ | |
4398 | { "sb_g1", | |
4399 | BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ | |
4400 | BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ | |
4401 | BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ | |
4402 | BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ | |
4403 | { "sb_g2", | |
4404 | BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ | |
4405 | BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ | |
4406 | BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ | |
4407 | BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ | |
4408 | ||
4409 | /* Given the address of a pointer pointing to the textual name of a group | |
4410 | relocation as may appear in assembler source, attempt to find its details | |
4411 | in group_reloc_table. The pointer will be updated to the character after | |
4412 | the trailing colon. On failure, FAIL will be returned; SUCCESS | |
4413 | otherwise. On success, *entry will be updated to point at the relevant | |
4414 | group_reloc_table entry. */ | |
4415 | ||
4416 | static int | |
4417 | find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) | |
4418 | { | |
4419 | unsigned int i; | |
4420 | for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) | |
4421 | { | |
4422 | int length = strlen (group_reloc_table[i].name); | |
4423 | ||
4424 | if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 && | |
4425 | (*str)[length] == ':') | |
4426 | { | |
4427 | *out = &group_reloc_table[i]; | |
4428 | *str += (length + 1); | |
4429 | return SUCCESS; | |
4430 | } | |
4431 | } | |
4432 | ||
4433 | return FAIL; | |
4434 | } | |
4435 | ||
4436 | /* Parse a <shifter_operand> for an ARM data processing instruction | |
4437 | (as for parse_shifter_operand) where group relocations are allowed: | |
4438 | ||
4439 | #<immediate> | |
4440 | #<immediate>, <rotate> | |
4441 | #:<group_reloc>:<expression> | |
4442 | <Rm> | |
4443 | <Rm>, <shift> | |
4444 | ||
4445 | where <group_reloc> is one of the strings defined in group_reloc_table. | |
4446 | The hashes are optional. | |
4447 | ||
4448 | Everything else is as for parse_shifter_operand. */ | |
4449 | ||
4450 | static parse_operand_result | |
4451 | parse_shifter_operand_group_reloc (char **str, int i) | |
4452 | { | |
4453 | /* Determine if we have the sequence of characters #: or just : | |
4454 | coming next. If we do, then we check for a group relocation. | |
4455 | If we don't, punt the whole lot to parse_shifter_operand. */ | |
4456 | ||
4457 | if (((*str)[0] == '#' && (*str)[1] == ':') | |
4458 | || (*str)[0] == ':') | |
4459 | { | |
4460 | struct group_reloc_table_entry *entry; | |
4461 | ||
4462 | if ((*str)[0] == '#') | |
4463 | (*str) += 2; | |
4464 | else | |
4465 | (*str)++; | |
4466 | ||
4467 | /* Try to parse a group relocation. Anything else is an error. */ | |
4468 | if (find_group_reloc_table_entry (str, &entry) == FAIL) | |
4469 | { | |
4470 | inst.error = _("unknown group relocation"); | |
4471 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
4472 | } | |
4473 | ||
4474 | /* We now have the group relocation table entry corresponding to | |
4475 | the name in the assembler source. Next, we parse the expression. */ | |
4476 | if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) | |
4477 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
4478 | ||
4479 | /* Record the relocation type (always the ALU variant here). */ | |
4480 | inst.reloc.type = entry->alu_code; | |
4481 | assert (inst.reloc.type != 0); | |
4482 | ||
4483 | return PARSE_OPERAND_SUCCESS; | |
4484 | } | |
4485 | else | |
4486 | return parse_shifter_operand (str, i) == SUCCESS | |
4487 | ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; | |
4488 | ||
4489 | /* Never reached. */ | |
4490 | } | |
4491 | ||
c19d1205 ZW |
4492 | /* Parse all forms of an ARM address expression. Information is written |
4493 | to inst.operands[i] and/or inst.reloc. | |
09d92015 | 4494 | |
c19d1205 | 4495 | Preindexed addressing (.preind=1): |
09d92015 | 4496 | |
c19d1205 ZW |
4497 | [Rn, #offset] .reg=Rn .reloc.exp=offset |
4498 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
4499 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
4500 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 4501 | |
c19d1205 | 4502 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 4503 | |
c19d1205 | 4504 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 4505 | |
c19d1205 ZW |
4506 | [Rn], #offset .reg=Rn .reloc.exp=offset |
4507 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
4508 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
4509 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 4510 | |
c19d1205 | 4511 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 4512 | |
c19d1205 | 4513 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 4514 | |
c19d1205 | 4515 | Other: |
09d92015 | 4516 | |
c19d1205 ZW |
4517 | [Rn]{!} shorthand for [Rn,#0]{!} |
4518 | =immediate .isreg=0 .reloc.exp=immediate | |
4519 | label .reg=PC .reloc.pc_rel=1 .reloc.exp=label | |
09d92015 | 4520 | |
c19d1205 ZW |
4521 | It is the caller's responsibility to check for addressing modes not |
4522 | supported by the instruction, and to set inst.reloc.type. */ | |
4523 | ||
4962c51a MS |
4524 | static parse_operand_result |
4525 | parse_address_main (char **str, int i, int group_relocations, | |
4526 | group_reloc_type group_type) | |
09d92015 | 4527 | { |
c19d1205 ZW |
4528 | char *p = *str; |
4529 | int reg; | |
09d92015 | 4530 | |
c19d1205 | 4531 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 4532 | { |
c19d1205 ZW |
4533 | if (skip_past_char (&p, '=') == FAIL) |
4534 | { | |
4535 | /* bare address - translate to PC-relative offset */ | |
4536 | inst.reloc.pc_rel = 1; | |
4537 | inst.operands[i].reg = REG_PC; | |
4538 | inst.operands[i].isreg = 1; | |
4539 | inst.operands[i].preind = 1; | |
4540 | } | |
4541 | /* else a load-constant pseudo op, no special treatment needed here */ | |
09d92015 | 4542 | |
c19d1205 | 4543 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) |
4962c51a | 4544 | return PARSE_OPERAND_FAIL; |
09d92015 | 4545 | |
c19d1205 | 4546 | *str = p; |
4962c51a | 4547 | return PARSE_OPERAND_SUCCESS; |
09d92015 MM |
4548 | } |
4549 | ||
dcbf9037 | 4550 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
09d92015 | 4551 | { |
c19d1205 | 4552 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
4962c51a | 4553 | return PARSE_OPERAND_FAIL; |
09d92015 | 4554 | } |
c19d1205 ZW |
4555 | inst.operands[i].reg = reg; |
4556 | inst.operands[i].isreg = 1; | |
09d92015 | 4557 | |
c19d1205 | 4558 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 4559 | { |
c19d1205 | 4560 | inst.operands[i].preind = 1; |
09d92015 | 4561 | |
c19d1205 ZW |
4562 | if (*p == '+') p++; |
4563 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
4564 | ||
dcbf9037 | 4565 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
09d92015 | 4566 | { |
c19d1205 ZW |
4567 | inst.operands[i].imm = reg; |
4568 | inst.operands[i].immisreg = 1; | |
4569 | ||
4570 | if (skip_past_comma (&p) == SUCCESS) | |
4571 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 4572 | return PARSE_OPERAND_FAIL; |
c19d1205 | 4573 | } |
5287ad62 JB |
4574 | else if (skip_past_char (&p, ':') == SUCCESS) |
4575 | { | |
4576 | /* FIXME: '@' should be used here, but it's filtered out by generic | |
4577 | code before we get to see it here. This may be subject to | |
4578 | change. */ | |
4579 | expressionS exp; | |
4580 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
4581 | if (exp.X_op != O_constant) | |
4582 | { | |
4583 | inst.error = _("alignment must be constant"); | |
4962c51a | 4584 | return PARSE_OPERAND_FAIL; |
5287ad62 JB |
4585 | } |
4586 | inst.operands[i].imm = exp.X_add_number << 8; | |
4587 | inst.operands[i].immisalign = 1; | |
4588 | /* Alignments are not pre-indexes. */ | |
4589 | inst.operands[i].preind = 0; | |
4590 | } | |
c19d1205 ZW |
4591 | else |
4592 | { | |
4593 | if (inst.operands[i].negative) | |
4594 | { | |
4595 | inst.operands[i].negative = 0; | |
4596 | p--; | |
4597 | } | |
4962c51a MS |
4598 | |
4599 | if (group_relocations && | |
4600 | ((*p == '#' && *(p + 1) == ':') || *p == ':')) | |
4601 | ||
4602 | { | |
4603 | struct group_reloc_table_entry *entry; | |
4604 | ||
4605 | /* Skip over the #: or : sequence. */ | |
4606 | if (*p == '#') | |
4607 | p += 2; | |
4608 | else | |
4609 | p++; | |
4610 | ||
4611 | /* Try to parse a group relocation. Anything else is an | |
4612 | error. */ | |
4613 | if (find_group_reloc_table_entry (&p, &entry) == FAIL) | |
4614 | { | |
4615 | inst.error = _("unknown group relocation"); | |
4616 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
4617 | } | |
4618 | ||
4619 | /* We now have the group relocation table entry corresponding to | |
4620 | the name in the assembler source. Next, we parse the | |
4621 | expression. */ | |
4622 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
4623 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
4624 | ||
4625 | /* Record the relocation type. */ | |
4626 | switch (group_type) | |
4627 | { | |
4628 | case GROUP_LDR: | |
4629 | inst.reloc.type = entry->ldr_code; | |
4630 | break; | |
4631 | ||
4632 | case GROUP_LDRS: | |
4633 | inst.reloc.type = entry->ldrs_code; | |
4634 | break; | |
4635 | ||
4636 | case GROUP_LDC: | |
4637 | inst.reloc.type = entry->ldc_code; | |
4638 | break; | |
4639 | ||
4640 | default: | |
4641 | assert (0); | |
4642 | } | |
4643 | ||
4644 | if (inst.reloc.type == 0) | |
4645 | { | |
4646 | inst.error = _("this group relocation is not allowed on this instruction"); | |
4647 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
4648 | } | |
4649 | } | |
4650 | else | |
4651 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4652 | return PARSE_OPERAND_FAIL; | |
09d92015 MM |
4653 | } |
4654 | } | |
4655 | ||
c19d1205 | 4656 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 4657 | { |
c19d1205 | 4658 | inst.error = _("']' expected"); |
4962c51a | 4659 | return PARSE_OPERAND_FAIL; |
09d92015 MM |
4660 | } |
4661 | ||
c19d1205 ZW |
4662 | if (skip_past_char (&p, '!') == SUCCESS) |
4663 | inst.operands[i].writeback = 1; | |
09d92015 | 4664 | |
c19d1205 | 4665 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 4666 | { |
c19d1205 ZW |
4667 | if (skip_past_char (&p, '{') == SUCCESS) |
4668 | { | |
4669 | /* [Rn], {expr} - unindexed, with option */ | |
4670 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 4671 | 0, 255, TRUE) == FAIL) |
4962c51a | 4672 | return PARSE_OPERAND_FAIL; |
09d92015 | 4673 | |
c19d1205 ZW |
4674 | if (skip_past_char (&p, '}') == FAIL) |
4675 | { | |
4676 | inst.error = _("'}' expected at end of 'option' field"); | |
4962c51a | 4677 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
4678 | } |
4679 | if (inst.operands[i].preind) | |
4680 | { | |
4681 | inst.error = _("cannot combine index with option"); | |
4962c51a | 4682 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
4683 | } |
4684 | *str = p; | |
4962c51a | 4685 | return PARSE_OPERAND_SUCCESS; |
09d92015 | 4686 | } |
c19d1205 ZW |
4687 | else |
4688 | { | |
4689 | inst.operands[i].postind = 1; | |
4690 | inst.operands[i].writeback = 1; | |
09d92015 | 4691 | |
c19d1205 ZW |
4692 | if (inst.operands[i].preind) |
4693 | { | |
4694 | inst.error = _("cannot combine pre- and post-indexing"); | |
4962c51a | 4695 | return PARSE_OPERAND_FAIL; |
c19d1205 | 4696 | } |
09d92015 | 4697 | |
c19d1205 ZW |
4698 | if (*p == '+') p++; |
4699 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 4700 | |
dcbf9037 | 4701 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 | 4702 | { |
5287ad62 JB |
4703 | /* We might be using the immediate for alignment already. If we |
4704 | are, OR the register number into the low-order bits. */ | |
4705 | if (inst.operands[i].immisalign) | |
4706 | inst.operands[i].imm |= reg; | |
4707 | else | |
4708 | inst.operands[i].imm = reg; | |
c19d1205 | 4709 | inst.operands[i].immisreg = 1; |
a737bd4d | 4710 | |
c19d1205 ZW |
4711 | if (skip_past_comma (&p) == SUCCESS) |
4712 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 4713 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
4714 | } |
4715 | else | |
4716 | { | |
4717 | if (inst.operands[i].negative) | |
4718 | { | |
4719 | inst.operands[i].negative = 0; | |
4720 | p--; | |
4721 | } | |
4722 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4962c51a | 4723 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
4724 | } |
4725 | } | |
a737bd4d NC |
4726 | } |
4727 | ||
c19d1205 ZW |
4728 | /* If at this point neither .preind nor .postind is set, we have a |
4729 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
4730 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
4731 | { | |
4732 | inst.operands[i].preind = 1; | |
4733 | inst.reloc.exp.X_op = O_constant; | |
4734 | inst.reloc.exp.X_add_number = 0; | |
4735 | } | |
4736 | *str = p; | |
4962c51a MS |
4737 | return PARSE_OPERAND_SUCCESS; |
4738 | } | |
4739 | ||
4740 | static int | |
4741 | parse_address (char **str, int i) | |
4742 | { | |
4743 | return parse_address_main (str, i, 0, 0) == PARSE_OPERAND_SUCCESS | |
4744 | ? SUCCESS : FAIL; | |
4745 | } | |
4746 | ||
4747 | static parse_operand_result | |
4748 | parse_address_group_reloc (char **str, int i, group_reloc_type type) | |
4749 | { | |
4750 | return parse_address_main (str, i, 1, type); | |
a737bd4d NC |
4751 | } |
4752 | ||
b6895b4f PB |
4753 | /* Parse an operand for a MOVW or MOVT instruction. */ |
4754 | static int | |
4755 | parse_half (char **str) | |
4756 | { | |
4757 | char * p; | |
4758 | ||
4759 | p = *str; | |
4760 | skip_past_char (&p, '#'); | |
4761 | if (strncasecmp (p, ":lower16:", 9) == 0) | |
4762 | inst.reloc.type = BFD_RELOC_ARM_MOVW; | |
4763 | else if (strncasecmp (p, ":upper16:", 9) == 0) | |
4764 | inst.reloc.type = BFD_RELOC_ARM_MOVT; | |
4765 | ||
4766 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
4767 | { | |
4768 | p += 9; | |
4769 | skip_whitespace(p); | |
4770 | } | |
4771 | ||
4772 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
4773 | return FAIL; | |
4774 | ||
4775 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
4776 | { | |
4777 | if (inst.reloc.exp.X_op != O_constant) | |
4778 | { | |
4779 | inst.error = _("constant expression expected"); | |
4780 | return FAIL; | |
4781 | } | |
4782 | if (inst.reloc.exp.X_add_number < 0 | |
4783 | || inst.reloc.exp.X_add_number > 0xffff) | |
4784 | { | |
4785 | inst.error = _("immediate value out of range"); | |
4786 | return FAIL; | |
4787 | } | |
4788 | } | |
4789 | *str = p; | |
4790 | return SUCCESS; | |
4791 | } | |
4792 | ||
c19d1205 | 4793 | /* Miscellaneous. */ |
a737bd4d | 4794 | |
c19d1205 ZW |
4795 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
4796 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
4797 | static int | |
4798 | parse_psr (char **str) | |
09d92015 | 4799 | { |
c19d1205 ZW |
4800 | char *p; |
4801 | unsigned long psr_field; | |
62b3e311 PB |
4802 | const struct asm_psr *psr; |
4803 | char *start; | |
09d92015 | 4804 | |
c19d1205 ZW |
4805 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
4806 | feature for ease of use and backwards compatibility. */ | |
4807 | p = *str; | |
62b3e311 | 4808 | if (strncasecmp (p, "SPSR", 4) == 0) |
c19d1205 | 4809 | psr_field = SPSR_BIT; |
62b3e311 | 4810 | else if (strncasecmp (p, "CPSR", 4) == 0) |
c19d1205 ZW |
4811 | psr_field = 0; |
4812 | else | |
62b3e311 PB |
4813 | { |
4814 | start = p; | |
4815 | do | |
4816 | p++; | |
4817 | while (ISALNUM (*p) || *p == '_'); | |
4818 | ||
4819 | psr = hash_find_n (arm_v7m_psr_hsh, start, p - start); | |
4820 | if (!psr) | |
4821 | return FAIL; | |
09d92015 | 4822 | |
62b3e311 PB |
4823 | *str = p; |
4824 | return psr->field; | |
4825 | } | |
09d92015 | 4826 | |
62b3e311 | 4827 | p += 4; |
c19d1205 ZW |
4828 | if (*p == '_') |
4829 | { | |
4830 | /* A suffix follows. */ | |
c19d1205 ZW |
4831 | p++; |
4832 | start = p; | |
a737bd4d | 4833 | |
c19d1205 ZW |
4834 | do |
4835 | p++; | |
4836 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 4837 | |
c19d1205 ZW |
4838 | psr = hash_find_n (arm_psr_hsh, start, p - start); |
4839 | if (!psr) | |
4840 | goto error; | |
a737bd4d | 4841 | |
c19d1205 | 4842 | psr_field |= psr->field; |
a737bd4d | 4843 | } |
c19d1205 | 4844 | else |
a737bd4d | 4845 | { |
c19d1205 ZW |
4846 | if (ISALNUM (*p)) |
4847 | goto error; /* Garbage after "[CS]PSR". */ | |
4848 | ||
4849 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 4850 | } |
c19d1205 ZW |
4851 | *str = p; |
4852 | return psr_field; | |
a737bd4d | 4853 | |
c19d1205 ZW |
4854 | error: |
4855 | inst.error = _("flag for {c}psr instruction expected"); | |
4856 | return FAIL; | |
a737bd4d NC |
4857 | } |
4858 | ||
c19d1205 ZW |
4859 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
4860 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 4861 | |
c19d1205 ZW |
4862 | static int |
4863 | parse_cps_flags (char **str) | |
a737bd4d | 4864 | { |
c19d1205 ZW |
4865 | int val = 0; |
4866 | int saw_a_flag = 0; | |
4867 | char *s = *str; | |
a737bd4d | 4868 | |
c19d1205 ZW |
4869 | for (;;) |
4870 | switch (*s++) | |
4871 | { | |
4872 | case '\0': case ',': | |
4873 | goto done; | |
a737bd4d | 4874 | |
c19d1205 ZW |
4875 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
4876 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
4877 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 4878 | |
c19d1205 ZW |
4879 | default: |
4880 | inst.error = _("unrecognized CPS flag"); | |
4881 | return FAIL; | |
4882 | } | |
a737bd4d | 4883 | |
c19d1205 ZW |
4884 | done: |
4885 | if (saw_a_flag == 0) | |
a737bd4d | 4886 | { |
c19d1205 ZW |
4887 | inst.error = _("missing CPS flags"); |
4888 | return FAIL; | |
a737bd4d | 4889 | } |
a737bd4d | 4890 | |
c19d1205 ZW |
4891 | *str = s - 1; |
4892 | return val; | |
a737bd4d NC |
4893 | } |
4894 | ||
c19d1205 ZW |
4895 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
4896 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
4897 | |
4898 | static int | |
c19d1205 | 4899 | parse_endian_specifier (char **str) |
a737bd4d | 4900 | { |
c19d1205 ZW |
4901 | int little_endian; |
4902 | char *s = *str; | |
a737bd4d | 4903 | |
c19d1205 ZW |
4904 | if (strncasecmp (s, "BE", 2)) |
4905 | little_endian = 0; | |
4906 | else if (strncasecmp (s, "LE", 2)) | |
4907 | little_endian = 1; | |
4908 | else | |
a737bd4d | 4909 | { |
c19d1205 | 4910 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
4911 | return FAIL; |
4912 | } | |
4913 | ||
c19d1205 | 4914 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 4915 | { |
c19d1205 | 4916 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
4917 | return FAIL; |
4918 | } | |
4919 | ||
c19d1205 ZW |
4920 | *str = s + 2; |
4921 | return little_endian; | |
4922 | } | |
a737bd4d | 4923 | |
c19d1205 ZW |
4924 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
4925 | value suitable for poking into the rotate field of an sxt or sxta | |
4926 | instruction, or FAIL on error. */ | |
4927 | ||
4928 | static int | |
4929 | parse_ror (char **str) | |
4930 | { | |
4931 | int rot; | |
4932 | char *s = *str; | |
4933 | ||
4934 | if (strncasecmp (s, "ROR", 3) == 0) | |
4935 | s += 3; | |
4936 | else | |
a737bd4d | 4937 | { |
c19d1205 | 4938 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
4939 | return FAIL; |
4940 | } | |
c19d1205 ZW |
4941 | |
4942 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
4943 | return FAIL; | |
4944 | ||
4945 | switch (rot) | |
a737bd4d | 4946 | { |
c19d1205 ZW |
4947 | case 0: *str = s; return 0x0; |
4948 | case 8: *str = s; return 0x1; | |
4949 | case 16: *str = s; return 0x2; | |
4950 | case 24: *str = s; return 0x3; | |
4951 | ||
4952 | default: | |
4953 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
4954 | return FAIL; |
4955 | } | |
c19d1205 | 4956 | } |
a737bd4d | 4957 | |
c19d1205 ZW |
4958 | /* Parse a conditional code (from conds[] below). The value returned is in the |
4959 | range 0 .. 14, or FAIL. */ | |
4960 | static int | |
4961 | parse_cond (char **str) | |
4962 | { | |
4963 | char *p, *q; | |
4964 | const struct asm_cond *c; | |
a737bd4d | 4965 | |
c19d1205 ZW |
4966 | p = q = *str; |
4967 | while (ISALPHA (*q)) | |
4968 | q++; | |
a737bd4d | 4969 | |
c19d1205 ZW |
4970 | c = hash_find_n (arm_cond_hsh, p, q - p); |
4971 | if (!c) | |
a737bd4d | 4972 | { |
c19d1205 | 4973 | inst.error = _("condition required"); |
a737bd4d NC |
4974 | return FAIL; |
4975 | } | |
4976 | ||
c19d1205 ZW |
4977 | *str = q; |
4978 | return c->value; | |
4979 | } | |
4980 | ||
62b3e311 PB |
4981 | /* Parse an option for a barrier instruction. Returns the encoding for the |
4982 | option, or FAIL. */ | |
4983 | static int | |
4984 | parse_barrier (char **str) | |
4985 | { | |
4986 | char *p, *q; | |
4987 | const struct asm_barrier_opt *o; | |
4988 | ||
4989 | p = q = *str; | |
4990 | while (ISALPHA (*q)) | |
4991 | q++; | |
4992 | ||
4993 | o = hash_find_n (arm_barrier_opt_hsh, p, q - p); | |
4994 | if (!o) | |
4995 | return FAIL; | |
4996 | ||
4997 | *str = q; | |
4998 | return o->value; | |
4999 | } | |
5000 | ||
92e90b6e PB |
5001 | /* Parse the operands of a table branch instruction. Similar to a memory |
5002 | operand. */ | |
5003 | static int | |
5004 | parse_tb (char **str) | |
5005 | { | |
5006 | char * p = *str; | |
5007 | int reg; | |
5008 | ||
5009 | if (skip_past_char (&p, '[') == FAIL) | |
ab1eb5fe PB |
5010 | { |
5011 | inst.error = _("'[' expected"); | |
5012 | return FAIL; | |
5013 | } | |
92e90b6e | 5014 | |
dcbf9037 | 5015 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5016 | { |
5017 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5018 | return FAIL; | |
5019 | } | |
5020 | inst.operands[0].reg = reg; | |
5021 | ||
5022 | if (skip_past_comma (&p) == FAIL) | |
ab1eb5fe PB |
5023 | { |
5024 | inst.error = _("',' expected"); | |
5025 | return FAIL; | |
5026 | } | |
92e90b6e | 5027 | |
dcbf9037 | 5028 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5029 | { |
5030 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5031 | return FAIL; | |
5032 | } | |
5033 | inst.operands[0].imm = reg; | |
5034 | ||
5035 | if (skip_past_comma (&p) == SUCCESS) | |
5036 | { | |
5037 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
5038 | return FAIL; | |
5039 | if (inst.reloc.exp.X_add_number != 1) | |
5040 | { | |
5041 | inst.error = _("invalid shift"); | |
5042 | return FAIL; | |
5043 | } | |
5044 | inst.operands[0].shifted = 1; | |
5045 | } | |
5046 | ||
5047 | if (skip_past_char (&p, ']') == FAIL) | |
5048 | { | |
5049 | inst.error = _("']' expected"); | |
5050 | return FAIL; | |
5051 | } | |
5052 | *str = p; | |
5053 | return SUCCESS; | |
5054 | } | |
5055 | ||
5287ad62 JB |
5056 | /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more |
5057 | information on the types the operands can take and how they are encoded. | |
037e8744 JB |
5058 | Up to four operands may be read; this function handles setting the |
5059 | ".present" field for each read operand itself. | |
5287ad62 JB |
5060 | Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, |
5061 | else returns FAIL. */ | |
5062 | ||
5063 | static int | |
5064 | parse_neon_mov (char **str, int *which_operand) | |
5065 | { | |
5066 | int i = *which_operand, val; | |
5067 | enum arm_reg_type rtype; | |
5068 | char *ptr = *str; | |
dcbf9037 | 5069 | struct neon_type_el optype; |
5287ad62 | 5070 | |
dcbf9037 | 5071 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
5072 | { |
5073 | /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ | |
5074 | inst.operands[i].reg = val; | |
5075 | inst.operands[i].isscalar = 1; | |
dcbf9037 | 5076 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5077 | inst.operands[i++].present = 1; |
5078 | ||
5079 | if (skip_past_comma (&ptr) == FAIL) | |
5080 | goto wanted_comma; | |
5081 | ||
dcbf9037 | 5082 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
5287ad62 JB |
5083 | goto wanted_arm; |
5084 | ||
5085 | inst.operands[i].reg = val; | |
5086 | inst.operands[i].isreg = 1; | |
5087 | inst.operands[i].present = 1; | |
5088 | } | |
037e8744 | 5089 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) |
dcbf9037 | 5090 | != FAIL) |
5287ad62 JB |
5091 | { |
5092 | /* Cases 0, 1, 2, 3, 5 (D only). */ | |
5093 | if (skip_past_comma (&ptr) == FAIL) | |
5094 | goto wanted_comma; | |
5095 | ||
5096 | inst.operands[i].reg = val; | |
5097 | inst.operands[i].isreg = 1; | |
5098 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5099 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5100 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5101 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5102 | inst.operands[i++].present = 1; |
5103 | ||
dcbf9037 | 5104 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 | 5105 | { |
037e8744 JB |
5106 | /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. |
5107 | Case 13: VMOV <Sd>, <Rm> */ | |
5287ad62 JB |
5108 | inst.operands[i].reg = val; |
5109 | inst.operands[i].isreg = 1; | |
037e8744 | 5110 | inst.operands[i].present = 1; |
5287ad62 JB |
5111 | |
5112 | if (rtype == REG_TYPE_NQ) | |
5113 | { | |
dcbf9037 | 5114 | first_error (_("can't use Neon quad register here")); |
5287ad62 JB |
5115 | return FAIL; |
5116 | } | |
037e8744 JB |
5117 | else if (rtype != REG_TYPE_VFS) |
5118 | { | |
5119 | i++; | |
5120 | if (skip_past_comma (&ptr) == FAIL) | |
5121 | goto wanted_comma; | |
5122 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5123 | goto wanted_arm; | |
5124 | inst.operands[i].reg = val; | |
5125 | inst.operands[i].isreg = 1; | |
5126 | inst.operands[i].present = 1; | |
5127 | } | |
5287ad62 | 5128 | } |
136da414 | 5129 | else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) |
136da414 | 5130 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> |
037e8744 JB |
5131 | Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> |
5132 | Case 10: VMOV.F32 <Sd>, #<imm> | |
5133 | Case 11: VMOV.F64 <Dd>, #<imm> */ | |
5134 | ; | |
5287ad62 | 5135 | else if (parse_big_immediate (&ptr, i) == SUCCESS) |
5287ad62 JB |
5136 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> |
5137 | Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ | |
037e8744 JB |
5138 | ; |
5139 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, | |
5140 | &optype)) != FAIL) | |
5287ad62 JB |
5141 | { |
5142 | /* Case 0: VMOV<c><q> <Qd>, <Qm> | |
037e8744 JB |
5143 | Case 1: VMOV<c><q> <Dd>, <Dm> |
5144 | Case 8: VMOV.F32 <Sd>, <Sm> | |
5145 | Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ | |
5287ad62 JB |
5146 | |
5147 | inst.operands[i].reg = val; | |
5148 | inst.operands[i].isreg = 1; | |
5149 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5150 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5151 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5152 | inst.operands[i].vectype = optype; |
5287ad62 | 5153 | inst.operands[i].present = 1; |
037e8744 JB |
5154 | |
5155 | if (skip_past_comma (&ptr) == SUCCESS) | |
5156 | { | |
5157 | /* Case 15. */ | |
5158 | i++; | |
5159 | ||
5160 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5161 | goto wanted_arm; | |
5162 | ||
5163 | inst.operands[i].reg = val; | |
5164 | inst.operands[i].isreg = 1; | |
5165 | inst.operands[i++].present = 1; | |
5166 | ||
5167 | if (skip_past_comma (&ptr) == FAIL) | |
5168 | goto wanted_comma; | |
5169 | ||
5170 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5171 | goto wanted_arm; | |
5172 | ||
5173 | inst.operands[i].reg = val; | |
5174 | inst.operands[i].isreg = 1; | |
5175 | inst.operands[i++].present = 1; | |
5176 | } | |
5287ad62 JB |
5177 | } |
5178 | else | |
5179 | { | |
dcbf9037 | 5180 | first_error (_("expected <Rm> or <Dm> or <Qm> operand")); |
5287ad62 JB |
5181 | return FAIL; |
5182 | } | |
5183 | } | |
dcbf9037 | 5184 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
5185 | { |
5186 | /* Cases 6, 7. */ | |
5187 | inst.operands[i].reg = val; | |
5188 | inst.operands[i].isreg = 1; | |
5189 | inst.operands[i++].present = 1; | |
5190 | ||
5191 | if (skip_past_comma (&ptr) == FAIL) | |
5192 | goto wanted_comma; | |
5193 | ||
dcbf9037 | 5194 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
5195 | { |
5196 | /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ | |
5197 | inst.operands[i].reg = val; | |
5198 | inst.operands[i].isscalar = 1; | |
5199 | inst.operands[i].present = 1; | |
dcbf9037 | 5200 | inst.operands[i].vectype = optype; |
5287ad62 | 5201 | } |
dcbf9037 | 5202 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
5203 | { |
5204 | /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ | |
5205 | inst.operands[i].reg = val; | |
5206 | inst.operands[i].isreg = 1; | |
5207 | inst.operands[i++].present = 1; | |
5208 | ||
5209 | if (skip_past_comma (&ptr) == FAIL) | |
5210 | goto wanted_comma; | |
5211 | ||
037e8744 | 5212 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) |
dcbf9037 | 5213 | == FAIL) |
5287ad62 | 5214 | { |
037e8744 | 5215 | first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); |
5287ad62 JB |
5216 | return FAIL; |
5217 | } | |
5218 | ||
5219 | inst.operands[i].reg = val; | |
5220 | inst.operands[i].isreg = 1; | |
037e8744 JB |
5221 | inst.operands[i].isvec = 1; |
5222 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
dcbf9037 | 5223 | inst.operands[i].vectype = optype; |
5287ad62 | 5224 | inst.operands[i].present = 1; |
037e8744 JB |
5225 | |
5226 | if (rtype == REG_TYPE_VFS) | |
5227 | { | |
5228 | /* Case 14. */ | |
5229 | i++; | |
5230 | if (skip_past_comma (&ptr) == FAIL) | |
5231 | goto wanted_comma; | |
5232 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, | |
5233 | &optype)) == FAIL) | |
5234 | { | |
5235 | first_error (_(reg_expected_msgs[REG_TYPE_VFS])); | |
5236 | return FAIL; | |
5237 | } | |
5238 | inst.operands[i].reg = val; | |
5239 | inst.operands[i].isreg = 1; | |
5240 | inst.operands[i].isvec = 1; | |
5241 | inst.operands[i].issingle = 1; | |
5242 | inst.operands[i].vectype = optype; | |
5243 | inst.operands[i].present = 1; | |
5244 | } | |
5245 | } | |
5246 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) | |
5247 | != FAIL) | |
5248 | { | |
5249 | /* Case 13. */ | |
5250 | inst.operands[i].reg = val; | |
5251 | inst.operands[i].isreg = 1; | |
5252 | inst.operands[i].isvec = 1; | |
5253 | inst.operands[i].issingle = 1; | |
5254 | inst.operands[i].vectype = optype; | |
5255 | inst.operands[i++].present = 1; | |
5287ad62 JB |
5256 | } |
5257 | } | |
5258 | else | |
5259 | { | |
dcbf9037 | 5260 | first_error (_("parse error")); |
5287ad62 JB |
5261 | return FAIL; |
5262 | } | |
5263 | ||
5264 | /* Successfully parsed the operands. Update args. */ | |
5265 | *which_operand = i; | |
5266 | *str = ptr; | |
5267 | return SUCCESS; | |
5268 | ||
5269 | wanted_comma: | |
dcbf9037 | 5270 | first_error (_("expected comma")); |
5287ad62 JB |
5271 | return FAIL; |
5272 | ||
5273 | wanted_arm: | |
dcbf9037 | 5274 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
5287ad62 | 5275 | return FAIL; |
5287ad62 JB |
5276 | } |
5277 | ||
c19d1205 ZW |
5278 | /* Matcher codes for parse_operands. */ |
5279 | enum operand_parse_code | |
5280 | { | |
5281 | OP_stop, /* end of line */ | |
5282 | ||
5283 | OP_RR, /* ARM register */ | |
5284 | OP_RRnpc, /* ARM register, not r15 */ | |
5285 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ | |
5286 | OP_RRw, /* ARM register, not r15, optional trailing ! */ | |
5287 | OP_RCP, /* Coprocessor number */ | |
5288 | OP_RCN, /* Coprocessor register */ | |
5289 | OP_RF, /* FPA register */ | |
5290 | OP_RVS, /* VFP single precision register */ | |
5287ad62 JB |
5291 | OP_RVD, /* VFP double precision register (0..15) */ |
5292 | OP_RND, /* Neon double precision register (0..31) */ | |
5293 | OP_RNQ, /* Neon quad precision register */ | |
037e8744 | 5294 | OP_RVSD, /* VFP single or double precision register */ |
5287ad62 | 5295 | OP_RNDQ, /* Neon double or quad precision register */ |
037e8744 | 5296 | OP_RNSDQ, /* Neon single, double or quad precision register */ |
5287ad62 | 5297 | OP_RNSC, /* Neon scalar D[X] */ |
c19d1205 ZW |
5298 | OP_RVC, /* VFP control register */ |
5299 | OP_RMF, /* Maverick F register */ | |
5300 | OP_RMD, /* Maverick D register */ | |
5301 | OP_RMFX, /* Maverick FX register */ | |
5302 | OP_RMDX, /* Maverick DX register */ | |
5303 | OP_RMAX, /* Maverick AX register */ | |
5304 | OP_RMDS, /* Maverick DSPSC register */ | |
5305 | OP_RIWR, /* iWMMXt wR register */ | |
5306 | OP_RIWC, /* iWMMXt wC register */ | |
5307 | OP_RIWG, /* iWMMXt wCG register */ | |
5308 | OP_RXA, /* XScale accumulator register */ | |
5309 | ||
5310 | OP_REGLST, /* ARM register list */ | |
5311 | OP_VRSLST, /* VFP single-precision register list */ | |
5312 | OP_VRDLST, /* VFP double-precision register list */ | |
037e8744 | 5313 | OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ |
5287ad62 JB |
5314 | OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ |
5315 | OP_NSTRLST, /* Neon element/structure list */ | |
5316 | ||
5317 | OP_NILO, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */ | |
5318 | OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ | |
037e8744 | 5319 | OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ |
5287ad62 | 5320 | OP_RR_RNSC, /* ARM reg or Neon scalar. */ |
037e8744 | 5321 | OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ |
5287ad62 JB |
5322 | OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ |
5323 | OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ | |
5324 | OP_VMOV, /* Neon VMOV operands. */ | |
5325 | OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN. */ | |
5326 | OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ | |
5327 | ||
5328 | OP_I0, /* immediate zero */ | |
c19d1205 ZW |
5329 | OP_I7, /* immediate value 0 .. 7 */ |
5330 | OP_I15, /* 0 .. 15 */ | |
5331 | OP_I16, /* 1 .. 16 */ | |
5287ad62 | 5332 | OP_I16z, /* 0 .. 16 */ |
c19d1205 ZW |
5333 | OP_I31, /* 0 .. 31 */ |
5334 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
5335 | OP_I32, /* 1 .. 32 */ | |
5287ad62 JB |
5336 | OP_I32z, /* 0 .. 32 */ |
5337 | OP_I63, /* 0 .. 63 */ | |
c19d1205 | 5338 | OP_I63s, /* -64 .. 63 */ |
5287ad62 JB |
5339 | OP_I64, /* 1 .. 64 */ |
5340 | OP_I64z, /* 0 .. 64 */ | |
c19d1205 | 5341 | OP_I255, /* 0 .. 255 */ |
c19d1205 ZW |
5342 | |
5343 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
5344 | OP_I7b, /* 0 .. 7 */ | |
5345 | OP_I15b, /* 0 .. 15 */ | |
5346 | OP_I31b, /* 0 .. 31 */ | |
5347 | ||
5348 | OP_SH, /* shifter operand */ | |
4962c51a | 5349 | OP_SHG, /* shifter operand with possible group relocation */ |
c19d1205 | 5350 | OP_ADDR, /* Memory address expression (any mode) */ |
4962c51a MS |
5351 | OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ |
5352 | OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ | |
5353 | OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ | |
c19d1205 ZW |
5354 | OP_EXP, /* arbitrary expression */ |
5355 | OP_EXPi, /* same, with optional immediate prefix */ | |
5356 | OP_EXPr, /* same, with optional relocation suffix */ | |
b6895b4f | 5357 | OP_HALF, /* 0 .. 65535 or low/high reloc. */ |
c19d1205 ZW |
5358 | |
5359 | OP_CPSF, /* CPS flags */ | |
5360 | OP_ENDI, /* Endianness specifier */ | |
5361 | OP_PSR, /* CPSR/SPSR mask for msr */ | |
5362 | OP_COND, /* conditional code */ | |
92e90b6e | 5363 | OP_TB, /* Table branch. */ |
c19d1205 | 5364 | |
037e8744 JB |
5365 | OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */ |
5366 | OP_APSR_RR, /* ARM register or "APSR_nzcv". */ | |
5367 | ||
c19d1205 ZW |
5368 | OP_RRnpc_I0, /* ARM register or literal 0 */ |
5369 | OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ | |
5370 | OP_RR_EXi, /* ARM register or expression with imm prefix */ | |
5371 | OP_RF_IF, /* FPA register or immediate */ | |
5372 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
41adaa5c | 5373 | OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ |
c19d1205 ZW |
5374 | |
5375 | /* Optional operands. */ | |
5376 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
5377 | OP_oI31b, /* 0 .. 31 */ | |
5287ad62 | 5378 | OP_oI32b, /* 1 .. 32 */ |
c19d1205 ZW |
5379 | OP_oIffffb, /* 0 .. 65535 */ |
5380 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
5381 | ||
5382 | OP_oRR, /* ARM register */ | |
5383 | OP_oRRnpc, /* ARM register, not the PC */ | |
5287ad62 JB |
5384 | OP_oRND, /* Optional Neon double precision register */ |
5385 | OP_oRNQ, /* Optional Neon quad precision register */ | |
5386 | OP_oRNDQ, /* Optional Neon double or quad precision register */ | |
037e8744 | 5387 | OP_oRNSDQ, /* Optional single, double or quad precision vector register */ |
c19d1205 ZW |
5388 | OP_oSHll, /* LSL immediate */ |
5389 | OP_oSHar, /* ASR immediate */ | |
5390 | OP_oSHllar, /* LSL or ASR immediate */ | |
5391 | OP_oROR, /* ROR 0/8/16/24 */ | |
62b3e311 | 5392 | OP_oBARRIER, /* Option argument for a barrier instruction. */ |
c19d1205 ZW |
5393 | |
5394 | OP_FIRST_OPTIONAL = OP_oI7b | |
5395 | }; | |
a737bd4d | 5396 | |
c19d1205 ZW |
5397 | /* Generic instruction operand parser. This does no encoding and no |
5398 | semantic validation; it merely squirrels values away in the inst | |
5399 | structure. Returns SUCCESS or FAIL depending on whether the | |
5400 | specified grammar matched. */ | |
5401 | static int | |
ca3f61f7 | 5402 | parse_operands (char *str, const unsigned char *pattern) |
c19d1205 ZW |
5403 | { |
5404 | unsigned const char *upat = pattern; | |
5405 | char *backtrack_pos = 0; | |
5406 | const char *backtrack_error = 0; | |
5407 | int i, val, backtrack_index = 0; | |
5287ad62 | 5408 | enum arm_reg_type rtype; |
4962c51a | 5409 | parse_operand_result result; |
c19d1205 ZW |
5410 | |
5411 | #define po_char_or_fail(chr) do { \ | |
5412 | if (skip_past_char (&str, chr) == FAIL) \ | |
5413 | goto bad_args; \ | |
5414 | } while (0) | |
5415 | ||
dcbf9037 JB |
5416 | #define po_reg_or_fail(regtype) do { \ |
5417 | val = arm_typed_reg_parse (&str, regtype, &rtype, \ | |
5418 | &inst.operands[i].vectype); \ | |
5419 | if (val == FAIL) \ | |
5420 | { \ | |
5421 | first_error (_(reg_expected_msgs[regtype])); \ | |
5422 | goto failure; \ | |
5423 | } \ | |
5424 | inst.operands[i].reg = val; \ | |
5425 | inst.operands[i].isreg = 1; \ | |
5426 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
037e8744 JB |
5427 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ |
5428 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
5429 | || rtype == REG_TYPE_VFD \ | |
5430 | || rtype == REG_TYPE_NQ); \ | |
c19d1205 ZW |
5431 | } while (0) |
5432 | ||
dcbf9037 JB |
5433 | #define po_reg_or_goto(regtype, label) do { \ |
5434 | val = arm_typed_reg_parse (&str, regtype, &rtype, \ | |
5435 | &inst.operands[i].vectype); \ | |
5436 | if (val == FAIL) \ | |
5437 | goto label; \ | |
5438 | \ | |
5439 | inst.operands[i].reg = val; \ | |
5440 | inst.operands[i].isreg = 1; \ | |
5441 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
037e8744 JB |
5442 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ |
5443 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
5444 | || rtype == REG_TYPE_VFD \ | |
5445 | || rtype == REG_TYPE_NQ); \ | |
c19d1205 ZW |
5446 | } while (0) |
5447 | ||
5448 | #define po_imm_or_fail(min, max, popt) do { \ | |
5449 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
5450 | goto failure; \ | |
5451 | inst.operands[i].imm = val; \ | |
5452 | } while (0) | |
5453 | ||
dcbf9037 JB |
5454 | #define po_scalar_or_goto(elsz, label) do { \ |
5455 | val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \ | |
5456 | if (val == FAIL) \ | |
5457 | goto label; \ | |
5458 | inst.operands[i].reg = val; \ | |
5459 | inst.operands[i].isscalar = 1; \ | |
5287ad62 JB |
5460 | } while (0) |
5461 | ||
c19d1205 ZW |
5462 | #define po_misc_or_fail(expr) do { \ |
5463 | if (expr) \ | |
5464 | goto failure; \ | |
5465 | } while (0) | |
5466 | ||
4962c51a MS |
5467 | #define po_misc_or_fail_no_backtrack(expr) do { \ |
5468 | result = expr; \ | |
5469 | if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\ | |
5470 | backtrack_pos = 0; \ | |
5471 | if (result != PARSE_OPERAND_SUCCESS) \ | |
5472 | goto failure; \ | |
5473 | } while (0) | |
5474 | ||
c19d1205 ZW |
5475 | skip_whitespace (str); |
5476 | ||
5477 | for (i = 0; upat[i] != OP_stop; i++) | |
5478 | { | |
5479 | if (upat[i] >= OP_FIRST_OPTIONAL) | |
5480 | { | |
5481 | /* Remember where we are in case we need to backtrack. */ | |
5482 | assert (!backtrack_pos); | |
5483 | backtrack_pos = str; | |
5484 | backtrack_error = inst.error; | |
5485 | backtrack_index = i; | |
5486 | } | |
5487 | ||
5488 | if (i > 0) | |
5489 | po_char_or_fail (','); | |
5490 | ||
5491 | switch (upat[i]) | |
5492 | { | |
5493 | /* Registers */ | |
5494 | case OP_oRRnpc: | |
5495 | case OP_RRnpc: | |
5496 | case OP_oRR: | |
5497 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; | |
5498 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
5499 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
5500 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
5501 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
5502 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
5287ad62 JB |
5503 | case OP_oRND: |
5504 | case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; | |
c19d1205 ZW |
5505 | case OP_RVC: po_reg_or_fail (REG_TYPE_VFC); break; |
5506 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; | |
5507 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
5508 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
5509 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
5510 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
5511 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
5512 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
5513 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
5514 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
5515 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
5287ad62 JB |
5516 | case OP_oRNQ: |
5517 | case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; | |
5518 | case OP_oRNDQ: | |
5519 | case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; | |
037e8744 JB |
5520 | case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; |
5521 | case OP_oRNSDQ: | |
5522 | case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; | |
5287ad62 JB |
5523 | |
5524 | /* Neon scalar. Using an element size of 8 means that some invalid | |
5525 | scalars are accepted here, so deal with those in later code. */ | |
5526 | case OP_RNSC: po_scalar_or_goto (8, failure); break; | |
5527 | ||
5528 | /* WARNING: We can expand to two operands here. This has the potential | |
5529 | to totally confuse the backtracking mechanism! It will be OK at | |
5530 | least as long as we don't try to use optional args as well, | |
5531 | though. */ | |
5532 | case OP_NILO: | |
5533 | { | |
5534 | po_reg_or_goto (REG_TYPE_NDQ, try_imm); | |
5535 | i++; | |
5536 | skip_past_comma (&str); | |
5537 | po_reg_or_goto (REG_TYPE_NDQ, one_reg_only); | |
5538 | break; | |
5539 | one_reg_only: | |
5540 | /* Optional register operand was omitted. Unfortunately, it's in | |
5541 | operands[i-1] and we need it to be in inst.operands[i]. Fix that | |
5542 | here (this is a bit grotty). */ | |
5543 | inst.operands[i] = inst.operands[i-1]; | |
5544 | inst.operands[i-1].present = 0; | |
5545 | break; | |
5546 | try_imm: | |
5547 | /* Immediate gets verified properly later, so accept any now. */ | |
5548 | po_imm_or_fail (INT_MIN, INT_MAX, TRUE); | |
5549 | } | |
5550 | break; | |
5551 | ||
5552 | case OP_RNDQ_I0: | |
5553 | { | |
5554 | po_reg_or_goto (REG_TYPE_NDQ, try_imm0); | |
5555 | break; | |
5556 | try_imm0: | |
5557 | po_imm_or_fail (0, 0, TRUE); | |
5558 | } | |
5559 | break; | |
5560 | ||
037e8744 JB |
5561 | case OP_RVSD_I0: |
5562 | po_reg_or_goto (REG_TYPE_VFSD, try_imm0); | |
5563 | break; | |
5564 | ||
5287ad62 JB |
5565 | case OP_RR_RNSC: |
5566 | { | |
5567 | po_scalar_or_goto (8, try_rr); | |
5568 | break; | |
5569 | try_rr: | |
5570 | po_reg_or_fail (REG_TYPE_RN); | |
5571 | } | |
5572 | break; | |
5573 | ||
037e8744 JB |
5574 | case OP_RNSDQ_RNSC: |
5575 | { | |
5576 | po_scalar_or_goto (8, try_nsdq); | |
5577 | break; | |
5578 | try_nsdq: | |
5579 | po_reg_or_fail (REG_TYPE_NSDQ); | |
5580 | } | |
5581 | break; | |
5582 | ||
5287ad62 JB |
5583 | case OP_RNDQ_RNSC: |
5584 | { | |
5585 | po_scalar_or_goto (8, try_ndq); | |
5586 | break; | |
5587 | try_ndq: | |
5588 | po_reg_or_fail (REG_TYPE_NDQ); | |
5589 | } | |
5590 | break; | |
5591 | ||
5592 | case OP_RND_RNSC: | |
5593 | { | |
5594 | po_scalar_or_goto (8, try_vfd); | |
5595 | break; | |
5596 | try_vfd: | |
5597 | po_reg_or_fail (REG_TYPE_VFD); | |
5598 | } | |
5599 | break; | |
5600 | ||
5601 | case OP_VMOV: | |
5602 | /* WARNING: parse_neon_mov can move the operand counter, i. If we're | |
5603 | not careful then bad things might happen. */ | |
5604 | po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); | |
5605 | break; | |
5606 | ||
5607 | case OP_RNDQ_IMVNb: | |
5608 | { | |
5609 | po_reg_or_goto (REG_TYPE_NDQ, try_mvnimm); | |
5610 | break; | |
5611 | try_mvnimm: | |
5612 | /* There's a possibility of getting a 64-bit immediate here, so | |
5613 | we need special handling. */ | |
5614 | if (parse_big_immediate (&str, i) == FAIL) | |
5615 | { | |
5616 | inst.error = _("immediate value is out of range"); | |
5617 | goto failure; | |
5618 | } | |
5619 | } | |
5620 | break; | |
5621 | ||
5622 | case OP_RNDQ_I63b: | |
5623 | { | |
5624 | po_reg_or_goto (REG_TYPE_NDQ, try_shimm); | |
5625 | break; | |
5626 | try_shimm: | |
5627 | po_imm_or_fail (0, 63, TRUE); | |
5628 | } | |
5629 | break; | |
c19d1205 ZW |
5630 | |
5631 | case OP_RRnpcb: | |
5632 | po_char_or_fail ('['); | |
5633 | po_reg_or_fail (REG_TYPE_RN); | |
5634 | po_char_or_fail (']'); | |
5635 | break; | |
a737bd4d | 5636 | |
c19d1205 ZW |
5637 | case OP_RRw: |
5638 | po_reg_or_fail (REG_TYPE_RN); | |
5639 | if (skip_past_char (&str, '!') == SUCCESS) | |
5640 | inst.operands[i].writeback = 1; | |
5641 | break; | |
5642 | ||
5643 | /* Immediates */ | |
5644 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
5645 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
5646 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
5287ad62 | 5647 | case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; |
c19d1205 ZW |
5648 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; |
5649 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
5287ad62 | 5650 | case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; |
c19d1205 | 5651 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; |
5287ad62 JB |
5652 | case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; |
5653 | case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; | |
5654 | case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; | |
c19d1205 | 5655 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; |
c19d1205 ZW |
5656 | |
5657 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
5658 | case OP_oI7b: | |
5659 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
5660 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
5661 | case OP_oI31b: | |
5662 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
5287ad62 | 5663 | case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; |
c19d1205 ZW |
5664 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; |
5665 | ||
5666 | /* Immediate variants */ | |
5667 | case OP_oI255c: | |
5668 | po_char_or_fail ('{'); | |
5669 | po_imm_or_fail (0, 255, TRUE); | |
5670 | po_char_or_fail ('}'); | |
5671 | break; | |
5672 | ||
5673 | case OP_I31w: | |
5674 | /* The expression parser chokes on a trailing !, so we have | |
5675 | to find it first and zap it. */ | |
5676 | { | |
5677 | char *s = str; | |
5678 | while (*s && *s != ',') | |
5679 | s++; | |
5680 | if (s[-1] == '!') | |
5681 | { | |
5682 | s[-1] = '\0'; | |
5683 | inst.operands[i].writeback = 1; | |
5684 | } | |
5685 | po_imm_or_fail (0, 31, TRUE); | |
5686 | if (str == s - 1) | |
5687 | str = s; | |
5688 | } | |
5689 | break; | |
5690 | ||
5691 | /* Expressions */ | |
5692 | case OP_EXPi: EXPi: | |
5693 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
5694 | GE_OPT_PREFIX)); | |
5695 | break; | |
5696 | ||
5697 | case OP_EXP: | |
5698 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
5699 | GE_NO_PREFIX)); | |
5700 | break; | |
5701 | ||
5702 | case OP_EXPr: EXPr: | |
5703 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
5704 | GE_NO_PREFIX)); | |
5705 | if (inst.reloc.exp.X_op == O_symbol) | |
a737bd4d | 5706 | { |
c19d1205 ZW |
5707 | val = parse_reloc (&str); |
5708 | if (val == -1) | |
5709 | { | |
5710 | inst.error = _("unrecognized relocation suffix"); | |
5711 | goto failure; | |
5712 | } | |
5713 | else if (val != BFD_RELOC_UNUSED) | |
5714 | { | |
5715 | inst.operands[i].imm = val; | |
5716 | inst.operands[i].hasreloc = 1; | |
5717 | } | |
a737bd4d | 5718 | } |
c19d1205 | 5719 | break; |
a737bd4d | 5720 | |
b6895b4f PB |
5721 | /* Operand for MOVW or MOVT. */ |
5722 | case OP_HALF: | |
5723 | po_misc_or_fail (parse_half (&str)); | |
5724 | break; | |
5725 | ||
c19d1205 ZW |
5726 | /* Register or expression */ |
5727 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; | |
5728 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 5729 | |
c19d1205 ZW |
5730 | /* Register or immediate */ |
5731 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; | |
5732 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 5733 | |
c19d1205 ZW |
5734 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
5735 | IF: | |
5736 | if (!is_immediate_prefix (*str)) | |
5737 | goto bad_args; | |
5738 | str++; | |
5739 | val = parse_fpa_immediate (&str); | |
5740 | if (val == FAIL) | |
5741 | goto failure; | |
5742 | /* FPA immediates are encoded as registers 8-15. | |
5743 | parse_fpa_immediate has already applied the offset. */ | |
5744 | inst.operands[i].reg = val; | |
5745 | inst.operands[i].isreg = 1; | |
5746 | break; | |
09d92015 | 5747 | |
c19d1205 ZW |
5748 | /* Two kinds of register */ |
5749 | case OP_RIWR_RIWC: | |
5750 | { | |
5751 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
97f87066 JM |
5752 | if (!rege |
5753 | || (rege->type != REG_TYPE_MMXWR | |
5754 | && rege->type != REG_TYPE_MMXWC | |
5755 | && rege->type != REG_TYPE_MMXWCG)) | |
c19d1205 ZW |
5756 | { |
5757 | inst.error = _("iWMMXt data or control register expected"); | |
5758 | goto failure; | |
5759 | } | |
5760 | inst.operands[i].reg = rege->number; | |
5761 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
5762 | } | |
5763 | break; | |
09d92015 | 5764 | |
41adaa5c JM |
5765 | case OP_RIWC_RIWG: |
5766 | { | |
5767 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
5768 | if (!rege | |
5769 | || (rege->type != REG_TYPE_MMXWC | |
5770 | && rege->type != REG_TYPE_MMXWCG)) | |
5771 | { | |
5772 | inst.error = _("iWMMXt control register expected"); | |
5773 | goto failure; | |
5774 | } | |
5775 | inst.operands[i].reg = rege->number; | |
5776 | inst.operands[i].isreg = 1; | |
5777 | } | |
5778 | break; | |
5779 | ||
c19d1205 ZW |
5780 | /* Misc */ |
5781 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
5782 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
5783 | case OP_oROR: val = parse_ror (&str); break; | |
5784 | case OP_PSR: val = parse_psr (&str); break; | |
5785 | case OP_COND: val = parse_cond (&str); break; | |
62b3e311 | 5786 | case OP_oBARRIER:val = parse_barrier (&str); break; |
c19d1205 | 5787 | |
037e8744 JB |
5788 | case OP_RVC_PSR: |
5789 | po_reg_or_goto (REG_TYPE_VFC, try_psr); | |
5790 | inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */ | |
5791 | break; | |
5792 | try_psr: | |
5793 | val = parse_psr (&str); | |
5794 | break; | |
5795 | ||
5796 | case OP_APSR_RR: | |
5797 | po_reg_or_goto (REG_TYPE_RN, try_apsr); | |
5798 | break; | |
5799 | try_apsr: | |
5800 | /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS | |
5801 | instruction). */ | |
5802 | if (strncasecmp (str, "APSR_", 5) == 0) | |
5803 | { | |
5804 | unsigned found = 0; | |
5805 | str += 5; | |
5806 | while (found < 15) | |
5807 | switch (*str++) | |
5808 | { | |
5809 | case 'c': found = (found & 1) ? 16 : found | 1; break; | |
5810 | case 'n': found = (found & 2) ? 16 : found | 2; break; | |
5811 | case 'z': found = (found & 4) ? 16 : found | 4; break; | |
5812 | case 'v': found = (found & 8) ? 16 : found | 8; break; | |
5813 | default: found = 16; | |
5814 | } | |
5815 | if (found != 15) | |
5816 | goto failure; | |
5817 | inst.operands[i].isvec = 1; | |
5818 | } | |
5819 | else | |
5820 | goto failure; | |
5821 | break; | |
5822 | ||
92e90b6e PB |
5823 | case OP_TB: |
5824 | po_misc_or_fail (parse_tb (&str)); | |
5825 | break; | |
5826 | ||
c19d1205 ZW |
5827 | /* Register lists */ |
5828 | case OP_REGLST: | |
5829 | val = parse_reg_list (&str); | |
5830 | if (*str == '^') | |
5831 | { | |
5832 | inst.operands[1].writeback = 1; | |
5833 | str++; | |
5834 | } | |
5835 | break; | |
09d92015 | 5836 | |
c19d1205 | 5837 | case OP_VRSLST: |
5287ad62 | 5838 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); |
c19d1205 | 5839 | break; |
09d92015 | 5840 | |
c19d1205 | 5841 | case OP_VRDLST: |
5287ad62 | 5842 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); |
c19d1205 | 5843 | break; |
a737bd4d | 5844 | |
037e8744 JB |
5845 | case OP_VRSDLST: |
5846 | /* Allow Q registers too. */ | |
5847 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
5848 | REGLIST_NEON_D); | |
5849 | if (val == FAIL) | |
5850 | { | |
5851 | inst.error = NULL; | |
5852 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
5853 | REGLIST_VFP_S); | |
5854 | inst.operands[i].issingle = 1; | |
5855 | } | |
5856 | break; | |
5857 | ||
5287ad62 JB |
5858 | case OP_NRDLST: |
5859 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
5860 | REGLIST_NEON_D); | |
5861 | break; | |
5862 | ||
5863 | case OP_NSTRLST: | |
dcbf9037 JB |
5864 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, |
5865 | &inst.operands[i].vectype); | |
5287ad62 JB |
5866 | break; |
5867 | ||
c19d1205 ZW |
5868 | /* Addressing modes */ |
5869 | case OP_ADDR: | |
5870 | po_misc_or_fail (parse_address (&str, i)); | |
5871 | break; | |
09d92015 | 5872 | |
4962c51a MS |
5873 | case OP_ADDRGLDR: |
5874 | po_misc_or_fail_no_backtrack ( | |
5875 | parse_address_group_reloc (&str, i, GROUP_LDR)); | |
5876 | break; | |
5877 | ||
5878 | case OP_ADDRGLDRS: | |
5879 | po_misc_or_fail_no_backtrack ( | |
5880 | parse_address_group_reloc (&str, i, GROUP_LDRS)); | |
5881 | break; | |
5882 | ||
5883 | case OP_ADDRGLDC: | |
5884 | po_misc_or_fail_no_backtrack ( | |
5885 | parse_address_group_reloc (&str, i, GROUP_LDC)); | |
5886 | break; | |
5887 | ||
c19d1205 ZW |
5888 | case OP_SH: |
5889 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
5890 | break; | |
09d92015 | 5891 | |
4962c51a MS |
5892 | case OP_SHG: |
5893 | po_misc_or_fail_no_backtrack ( | |
5894 | parse_shifter_operand_group_reloc (&str, i)); | |
5895 | break; | |
5896 | ||
c19d1205 ZW |
5897 | case OP_oSHll: |
5898 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
5899 | break; | |
09d92015 | 5900 | |
c19d1205 ZW |
5901 | case OP_oSHar: |
5902 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
5903 | break; | |
09d92015 | 5904 | |
c19d1205 ZW |
5905 | case OP_oSHllar: |
5906 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
5907 | break; | |
09d92015 | 5908 | |
c19d1205 ZW |
5909 | default: |
5910 | as_fatal ("unhandled operand code %d", upat[i]); | |
5911 | } | |
09d92015 | 5912 | |
c19d1205 ZW |
5913 | /* Various value-based sanity checks and shared operations. We |
5914 | do not signal immediate failures for the register constraints; | |
5915 | this allows a syntax error to take precedence. */ | |
5916 | switch (upat[i]) | |
5917 | { | |
5918 | case OP_oRRnpc: | |
5919 | case OP_RRnpc: | |
5920 | case OP_RRnpcb: | |
5921 | case OP_RRw: | |
5922 | case OP_RRnpc_I0: | |
5923 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
5924 | inst.error = BAD_PC; | |
5925 | break; | |
09d92015 | 5926 | |
c19d1205 ZW |
5927 | case OP_CPSF: |
5928 | case OP_ENDI: | |
5929 | case OP_oROR: | |
5930 | case OP_PSR: | |
037e8744 | 5931 | case OP_RVC_PSR: |
c19d1205 | 5932 | case OP_COND: |
62b3e311 | 5933 | case OP_oBARRIER: |
c19d1205 ZW |
5934 | case OP_REGLST: |
5935 | case OP_VRSLST: | |
5936 | case OP_VRDLST: | |
037e8744 | 5937 | case OP_VRSDLST: |
5287ad62 JB |
5938 | case OP_NRDLST: |
5939 | case OP_NSTRLST: | |
c19d1205 ZW |
5940 | if (val == FAIL) |
5941 | goto failure; | |
5942 | inst.operands[i].imm = val; | |
5943 | break; | |
a737bd4d | 5944 | |
c19d1205 ZW |
5945 | default: |
5946 | break; | |
5947 | } | |
09d92015 | 5948 | |
c19d1205 ZW |
5949 | /* If we get here, this operand was successfully parsed. */ |
5950 | inst.operands[i].present = 1; | |
5951 | continue; | |
09d92015 | 5952 | |
c19d1205 | 5953 | bad_args: |
09d92015 | 5954 | inst.error = BAD_ARGS; |
c19d1205 ZW |
5955 | |
5956 | failure: | |
5957 | if (!backtrack_pos) | |
d252fdde PB |
5958 | { |
5959 | /* The parse routine should already have set inst.error, but set a | |
5960 | defaut here just in case. */ | |
5961 | if (!inst.error) | |
5962 | inst.error = _("syntax error"); | |
5963 | return FAIL; | |
5964 | } | |
c19d1205 ZW |
5965 | |
5966 | /* Do not backtrack over a trailing optional argument that | |
5967 | absorbed some text. We will only fail again, with the | |
5968 | 'garbage following instruction' error message, which is | |
5969 | probably less helpful than the current one. */ | |
5970 | if (backtrack_index == i && backtrack_pos != str | |
5971 | && upat[i+1] == OP_stop) | |
d252fdde PB |
5972 | { |
5973 | if (!inst.error) | |
5974 | inst.error = _("syntax error"); | |
5975 | return FAIL; | |
5976 | } | |
c19d1205 ZW |
5977 | |
5978 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
5979 | str = backtrack_pos; | |
5980 | inst.error = backtrack_error; | |
5981 | inst.operands[backtrack_index].present = 0; | |
5982 | i = backtrack_index; | |
5983 | backtrack_pos = 0; | |
09d92015 | 5984 | } |
09d92015 | 5985 | |
c19d1205 ZW |
5986 | /* Check that we have parsed all the arguments. */ |
5987 | if (*str != '\0' && !inst.error) | |
5988 | inst.error = _("garbage following instruction"); | |
09d92015 | 5989 | |
c19d1205 | 5990 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
5991 | } |
5992 | ||
c19d1205 ZW |
5993 | #undef po_char_or_fail |
5994 | #undef po_reg_or_fail | |
5995 | #undef po_reg_or_goto | |
5996 | #undef po_imm_or_fail | |
5287ad62 | 5997 | #undef po_scalar_or_fail |
c19d1205 ZW |
5998 | \f |
5999 | /* Shorthand macro for instruction encoding functions issuing errors. */ | |
6000 | #define constraint(expr, err) do { \ | |
6001 | if (expr) \ | |
6002 | { \ | |
6003 | inst.error = err; \ | |
6004 | return; \ | |
6005 | } \ | |
6006 | } while (0) | |
6007 | ||
6008 | /* Functions for operand encoding. ARM, then Thumb. */ | |
6009 | ||
6010 | #define rotate_left(v, n) (v << n | v >> (32 - n)) | |
6011 | ||
6012 | /* If VAL can be encoded in the immediate field of an ARM instruction, | |
6013 | return the encoded form. Otherwise, return FAIL. */ | |
6014 | ||
6015 | static unsigned int | |
6016 | encode_arm_immediate (unsigned int val) | |
09d92015 | 6017 | { |
c19d1205 ZW |
6018 | unsigned int a, i; |
6019 | ||
6020 | for (i = 0; i < 32; i += 2) | |
6021 | if ((a = rotate_left (val, i)) <= 0xff) | |
6022 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
6023 | ||
6024 | return FAIL; | |
09d92015 MM |
6025 | } |
6026 | ||
c19d1205 ZW |
6027 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
6028 | return the encoded form. Otherwise, return FAIL. */ | |
6029 | static unsigned int | |
6030 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 6031 | { |
c19d1205 | 6032 | unsigned int a, i; |
09d92015 | 6033 | |
9c3c69f2 | 6034 | if (val <= 0xff) |
c19d1205 | 6035 | return val; |
a737bd4d | 6036 | |
9c3c69f2 | 6037 | for (i = 1; i <= 24; i++) |
09d92015 | 6038 | { |
9c3c69f2 PB |
6039 | a = val >> i; |
6040 | if ((val & ~(0xff << i)) == 0) | |
6041 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 6042 | } |
a737bd4d | 6043 | |
c19d1205 ZW |
6044 | a = val & 0xff; |
6045 | if (val == ((a << 16) | a)) | |
6046 | return 0x100 | a; | |
6047 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
6048 | return 0x300 | a; | |
09d92015 | 6049 | |
c19d1205 ZW |
6050 | a = val & 0xff00; |
6051 | if (val == ((a << 16) | a)) | |
6052 | return 0x200 | (a >> 8); | |
a737bd4d | 6053 | |
c19d1205 | 6054 | return FAIL; |
09d92015 | 6055 | } |
5287ad62 | 6056 | /* Encode a VFP SP or DP register number into inst.instruction. */ |
09d92015 MM |
6057 | |
6058 | static void | |
5287ad62 JB |
6059 | encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) |
6060 | { | |
6061 | if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) | |
6062 | && reg > 15) | |
6063 | { | |
6064 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) | |
6065 | { | |
6066 | if (thumb_mode) | |
6067 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
6068 | fpu_vfp_ext_v3); | |
6069 | else | |
6070 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
6071 | fpu_vfp_ext_v3); | |
6072 | } | |
6073 | else | |
6074 | { | |
dcbf9037 | 6075 | first_error (_("D register out of range for selected VFP version")); |
5287ad62 JB |
6076 | return; |
6077 | } | |
6078 | } | |
6079 | ||
c19d1205 | 6080 | switch (pos) |
09d92015 | 6081 | { |
c19d1205 ZW |
6082 | case VFP_REG_Sd: |
6083 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
6084 | break; | |
6085 | ||
6086 | case VFP_REG_Sn: | |
6087 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
6088 | break; | |
6089 | ||
6090 | case VFP_REG_Sm: | |
6091 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
6092 | break; | |
6093 | ||
5287ad62 JB |
6094 | case VFP_REG_Dd: |
6095 | inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); | |
6096 | break; | |
6097 | ||
6098 | case VFP_REG_Dn: | |
6099 | inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); | |
6100 | break; | |
6101 | ||
6102 | case VFP_REG_Dm: | |
6103 | inst.instruction |= (reg & 15) | ((reg >> 4) << 5); | |
6104 | break; | |
6105 | ||
c19d1205 ZW |
6106 | default: |
6107 | abort (); | |
09d92015 | 6108 | } |
09d92015 MM |
6109 | } |
6110 | ||
c19d1205 | 6111 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 6112 | if any, is handled by md_apply_fix. */ |
09d92015 | 6113 | static void |
c19d1205 | 6114 | encode_arm_shift (int i) |
09d92015 | 6115 | { |
c19d1205 ZW |
6116 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
6117 | inst.instruction |= SHIFT_ROR << 5; | |
6118 | else | |
09d92015 | 6119 | { |
c19d1205 ZW |
6120 | inst.instruction |= inst.operands[i].shift_kind << 5; |
6121 | if (inst.operands[i].immisreg) | |
6122 | { | |
6123 | inst.instruction |= SHIFT_BY_REG; | |
6124 | inst.instruction |= inst.operands[i].imm << 8; | |
6125 | } | |
6126 | else | |
6127 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
09d92015 | 6128 | } |
c19d1205 | 6129 | } |
09d92015 | 6130 | |
c19d1205 ZW |
6131 | static void |
6132 | encode_arm_shifter_operand (int i) | |
6133 | { | |
6134 | if (inst.operands[i].isreg) | |
09d92015 | 6135 | { |
c19d1205 ZW |
6136 | inst.instruction |= inst.operands[i].reg; |
6137 | encode_arm_shift (i); | |
09d92015 | 6138 | } |
c19d1205 ZW |
6139 | else |
6140 | inst.instruction |= INST_IMMEDIATE; | |
09d92015 MM |
6141 | } |
6142 | ||
c19d1205 | 6143 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 6144 | static void |
c19d1205 | 6145 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 6146 | { |
c19d1205 ZW |
6147 | assert (inst.operands[i].isreg); |
6148 | inst.instruction |= inst.operands[i].reg << 16; | |
a737bd4d | 6149 | |
c19d1205 | 6150 | if (inst.operands[i].preind) |
09d92015 | 6151 | { |
c19d1205 ZW |
6152 | if (is_t) |
6153 | { | |
6154 | inst.error = _("instruction does not accept preindexed addressing"); | |
6155 | return; | |
6156 | } | |
6157 | inst.instruction |= PRE_INDEX; | |
6158 | if (inst.operands[i].writeback) | |
6159 | inst.instruction |= WRITE_BACK; | |
09d92015 | 6160 | |
c19d1205 ZW |
6161 | } |
6162 | else if (inst.operands[i].postind) | |
6163 | { | |
6164 | assert (inst.operands[i].writeback); | |
6165 | if (is_t) | |
6166 | inst.instruction |= WRITE_BACK; | |
6167 | } | |
6168 | else /* unindexed - only for coprocessor */ | |
09d92015 | 6169 | { |
c19d1205 | 6170 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
6171 | return; |
6172 | } | |
6173 | ||
c19d1205 ZW |
6174 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
6175 | && (((inst.instruction & 0x000f0000) >> 16) | |
6176 | == ((inst.instruction & 0x0000f000) >> 12))) | |
6177 | as_warn ((inst.instruction & LOAD_BIT) | |
6178 | ? _("destination register same as write-back base") | |
6179 | : _("source register same as write-back base")); | |
09d92015 MM |
6180 | } |
6181 | ||
c19d1205 ZW |
6182 | /* inst.operands[i] was set up by parse_address. Encode it into an |
6183 | ARM-format mode 2 load or store instruction. If is_t is true, | |
6184 | reject forms that cannot be used with a T instruction (i.e. not | |
6185 | post-indexed). */ | |
a737bd4d | 6186 | static void |
c19d1205 | 6187 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 6188 | { |
c19d1205 | 6189 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 6190 | |
c19d1205 | 6191 | if (inst.operands[i].immisreg) |
09d92015 | 6192 | { |
c19d1205 ZW |
6193 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
6194 | inst.instruction |= inst.operands[i].imm; | |
6195 | if (!inst.operands[i].negative) | |
6196 | inst.instruction |= INDEX_UP; | |
6197 | if (inst.operands[i].shifted) | |
6198 | { | |
6199 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
6200 | inst.instruction |= SHIFT_ROR << 5; | |
6201 | else | |
6202 | { | |
6203 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
6204 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
6205 | } | |
6206 | } | |
09d92015 | 6207 | } |
c19d1205 | 6208 | else /* immediate offset in inst.reloc */ |
09d92015 | 6209 | { |
c19d1205 ZW |
6210 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
6211 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
09d92015 | 6212 | } |
09d92015 MM |
6213 | } |
6214 | ||
c19d1205 ZW |
6215 | /* inst.operands[i] was set up by parse_address. Encode it into an |
6216 | ARM-format mode 3 load or store instruction. Reject forms that | |
6217 | cannot be used with such instructions. If is_t is true, reject | |
6218 | forms that cannot be used with a T instruction (i.e. not | |
6219 | post-indexed). */ | |
6220 | static void | |
6221 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 6222 | { |
c19d1205 | 6223 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 6224 | { |
c19d1205 ZW |
6225 | inst.error = _("instruction does not accept scaled register index"); |
6226 | return; | |
09d92015 | 6227 | } |
a737bd4d | 6228 | |
c19d1205 | 6229 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 6230 | |
c19d1205 ZW |
6231 | if (inst.operands[i].immisreg) |
6232 | { | |
6233 | inst.instruction |= inst.operands[i].imm; | |
6234 | if (!inst.operands[i].negative) | |
6235 | inst.instruction |= INDEX_UP; | |
6236 | } | |
6237 | else /* immediate offset in inst.reloc */ | |
6238 | { | |
6239 | inst.instruction |= HWOFFSET_IMM; | |
6240 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
6241 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
c19d1205 | 6242 | } |
a737bd4d NC |
6243 | } |
6244 | ||
c19d1205 ZW |
6245 | /* inst.operands[i] was set up by parse_address. Encode it into an |
6246 | ARM-format instruction. Reject all forms which cannot be encoded | |
6247 | into a coprocessor load/store instruction. If wb_ok is false, | |
6248 | reject use of writeback; if unind_ok is false, reject use of | |
6249 | unindexed addressing. If reloc_override is not 0, use it instead | |
4962c51a MS |
6250 | of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one |
6251 | (in which case it is preserved). */ | |
09d92015 | 6252 | |
c19d1205 ZW |
6253 | static int |
6254 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
09d92015 | 6255 | { |
c19d1205 | 6256 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 6257 | |
c19d1205 | 6258 | assert (!(inst.operands[i].preind && inst.operands[i].postind)); |
09d92015 | 6259 | |
c19d1205 | 6260 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ |
09d92015 | 6261 | { |
c19d1205 ZW |
6262 | assert (!inst.operands[i].writeback); |
6263 | if (!unind_ok) | |
6264 | { | |
6265 | inst.error = _("instruction does not support unindexed addressing"); | |
6266 | return FAIL; | |
6267 | } | |
6268 | inst.instruction |= inst.operands[i].imm; | |
6269 | inst.instruction |= INDEX_UP; | |
6270 | return SUCCESS; | |
09d92015 | 6271 | } |
a737bd4d | 6272 | |
c19d1205 ZW |
6273 | if (inst.operands[i].preind) |
6274 | inst.instruction |= PRE_INDEX; | |
a737bd4d | 6275 | |
c19d1205 | 6276 | if (inst.operands[i].writeback) |
09d92015 | 6277 | { |
c19d1205 ZW |
6278 | if (inst.operands[i].reg == REG_PC) |
6279 | { | |
6280 | inst.error = _("pc may not be used with write-back"); | |
6281 | return FAIL; | |
6282 | } | |
6283 | if (!wb_ok) | |
6284 | { | |
6285 | inst.error = _("instruction does not support writeback"); | |
6286 | return FAIL; | |
6287 | } | |
6288 | inst.instruction |= WRITE_BACK; | |
09d92015 | 6289 | } |
a737bd4d | 6290 | |
c19d1205 ZW |
6291 | if (reloc_override) |
6292 | inst.reloc.type = reloc_override; | |
4962c51a MS |
6293 | else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC |
6294 | || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) | |
6295 | && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) | |
6296 | { | |
6297 | if (thumb_mode) | |
6298 | inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; | |
6299 | else | |
6300 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; | |
6301 | } | |
6302 | ||
c19d1205 ZW |
6303 | return SUCCESS; |
6304 | } | |
a737bd4d | 6305 | |
c19d1205 ZW |
6306 | /* inst.reloc.exp describes an "=expr" load pseudo-operation. |
6307 | Determine whether it can be performed with a move instruction; if | |
6308 | it can, convert inst.instruction to that move instruction and | |
6309 | return 1; if it can't, convert inst.instruction to a literal-pool | |
6310 | load and return 0. If this is not a valid thing to do in the | |
6311 | current context, set inst.error and return 1. | |
a737bd4d | 6312 | |
c19d1205 ZW |
6313 | inst.operands[i] describes the destination register. */ |
6314 | ||
6315 | static int | |
6316 | move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) | |
6317 | { | |
53365c0d PB |
6318 | unsigned long tbit; |
6319 | ||
6320 | if (thumb_p) | |
6321 | tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; | |
6322 | else | |
6323 | tbit = LOAD_BIT; | |
6324 | ||
6325 | if ((inst.instruction & tbit) == 0) | |
09d92015 | 6326 | { |
c19d1205 ZW |
6327 | inst.error = _("invalid pseudo operation"); |
6328 | return 1; | |
09d92015 | 6329 | } |
c19d1205 | 6330 | if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) |
09d92015 MM |
6331 | { |
6332 | inst.error = _("constant expression expected"); | |
c19d1205 | 6333 | return 1; |
09d92015 | 6334 | } |
c19d1205 | 6335 | if (inst.reloc.exp.X_op == O_constant) |
09d92015 | 6336 | { |
c19d1205 ZW |
6337 | if (thumb_p) |
6338 | { | |
53365c0d | 6339 | if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) |
c19d1205 ZW |
6340 | { |
6341 | /* This can be done with a mov(1) instruction. */ | |
6342 | inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); | |
6343 | inst.instruction |= inst.reloc.exp.X_add_number; | |
6344 | return 1; | |
6345 | } | |
6346 | } | |
6347 | else | |
6348 | { | |
6349 | int value = encode_arm_immediate (inst.reloc.exp.X_add_number); | |
6350 | if (value != FAIL) | |
6351 | { | |
6352 | /* This can be done with a mov instruction. */ | |
6353 | inst.instruction &= LITERAL_MASK; | |
6354 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
6355 | inst.instruction |= value & 0xfff; | |
6356 | return 1; | |
6357 | } | |
09d92015 | 6358 | |
c19d1205 ZW |
6359 | value = encode_arm_immediate (~inst.reloc.exp.X_add_number); |
6360 | if (value != FAIL) | |
6361 | { | |
6362 | /* This can be done with a mvn instruction. */ | |
6363 | inst.instruction &= LITERAL_MASK; | |
6364 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
6365 | inst.instruction |= value & 0xfff; | |
6366 | return 1; | |
6367 | } | |
6368 | } | |
09d92015 MM |
6369 | } |
6370 | ||
c19d1205 ZW |
6371 | if (add_to_lit_pool () == FAIL) |
6372 | { | |
6373 | inst.error = _("literal pool insertion failed"); | |
6374 | return 1; | |
6375 | } | |
6376 | inst.operands[1].reg = REG_PC; | |
6377 | inst.operands[1].isreg = 1; | |
6378 | inst.operands[1].preind = 1; | |
6379 | inst.reloc.pc_rel = 1; | |
6380 | inst.reloc.type = (thumb_p | |
6381 | ? BFD_RELOC_ARM_THUMB_OFFSET | |
6382 | : (mode_3 | |
6383 | ? BFD_RELOC_ARM_HWLITERAL | |
6384 | : BFD_RELOC_ARM_LITERAL)); | |
6385 | return 0; | |
09d92015 MM |
6386 | } |
6387 | ||
c19d1205 ZW |
6388 | /* Functions for instruction encoding, sorted by subarchitecture. |
6389 | First some generics; their names are taken from the conventional | |
6390 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 6391 | |
a737bd4d | 6392 | static void |
c19d1205 | 6393 | do_noargs (void) |
09d92015 | 6394 | { |
c19d1205 | 6395 | } |
a737bd4d | 6396 | |
c19d1205 ZW |
6397 | static void |
6398 | do_rd (void) | |
6399 | { | |
6400 | inst.instruction |= inst.operands[0].reg << 12; | |
6401 | } | |
a737bd4d | 6402 | |
c19d1205 ZW |
6403 | static void |
6404 | do_rd_rm (void) | |
6405 | { | |
6406 | inst.instruction |= inst.operands[0].reg << 12; | |
6407 | inst.instruction |= inst.operands[1].reg; | |
6408 | } | |
09d92015 | 6409 | |
c19d1205 ZW |
6410 | static void |
6411 | do_rd_rn (void) | |
6412 | { | |
6413 | inst.instruction |= inst.operands[0].reg << 12; | |
6414 | inst.instruction |= inst.operands[1].reg << 16; | |
6415 | } | |
a737bd4d | 6416 | |
c19d1205 ZW |
6417 | static void |
6418 | do_rn_rd (void) | |
6419 | { | |
6420 | inst.instruction |= inst.operands[0].reg << 16; | |
6421 | inst.instruction |= inst.operands[1].reg << 12; | |
6422 | } | |
09d92015 | 6423 | |
c19d1205 ZW |
6424 | static void |
6425 | do_rd_rm_rn (void) | |
6426 | { | |
9a64e435 | 6427 | unsigned Rn = inst.operands[2].reg; |
708587a4 | 6428 | /* Enforce restrictions on SWP instruction. */ |
9a64e435 PB |
6429 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) |
6430 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
6431 | _("Rn must not overlap other operands")); | |
c19d1205 ZW |
6432 | inst.instruction |= inst.operands[0].reg << 12; |
6433 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 6434 | inst.instruction |= Rn << 16; |
c19d1205 | 6435 | } |
09d92015 | 6436 | |
c19d1205 ZW |
6437 | static void |
6438 | do_rd_rn_rm (void) | |
6439 | { | |
6440 | inst.instruction |= inst.operands[0].reg << 12; | |
6441 | inst.instruction |= inst.operands[1].reg << 16; | |
6442 | inst.instruction |= inst.operands[2].reg; | |
6443 | } | |
a737bd4d | 6444 | |
c19d1205 ZW |
6445 | static void |
6446 | do_rm_rd_rn (void) | |
6447 | { | |
6448 | inst.instruction |= inst.operands[0].reg; | |
6449 | inst.instruction |= inst.operands[1].reg << 12; | |
6450 | inst.instruction |= inst.operands[2].reg << 16; | |
6451 | } | |
09d92015 | 6452 | |
c19d1205 ZW |
6453 | static void |
6454 | do_imm0 (void) | |
6455 | { | |
6456 | inst.instruction |= inst.operands[0].imm; | |
6457 | } | |
09d92015 | 6458 | |
c19d1205 ZW |
6459 | static void |
6460 | do_rd_cpaddr (void) | |
6461 | { | |
6462 | inst.instruction |= inst.operands[0].reg << 12; | |
6463 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 6464 | } |
a737bd4d | 6465 | |
c19d1205 ZW |
6466 | /* ARM instructions, in alphabetical order by function name (except |
6467 | that wrapper functions appear immediately after the function they | |
6468 | wrap). */ | |
09d92015 | 6469 | |
c19d1205 ZW |
6470 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
6471 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
6472 | |
6473 | static void | |
c19d1205 | 6474 | do_adr (void) |
09d92015 | 6475 | { |
c19d1205 | 6476 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 6477 | |
c19d1205 ZW |
6478 | /* Frag hacking will turn this into a sub instruction if the offset turns |
6479 | out to be negative. */ | |
6480 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
c19d1205 | 6481 | inst.reloc.pc_rel = 1; |
2fc8bdac | 6482 | inst.reloc.exp.X_add_number -= 8; |
c19d1205 | 6483 | } |
b99bd4ef | 6484 | |
c19d1205 ZW |
6485 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
6486 | into a relative address of the form: | |
6487 | add rd, pc, #low(label-.-8)" | |
6488 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 6489 | |
c19d1205 ZW |
6490 | static void |
6491 | do_adrl (void) | |
6492 | { | |
6493 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 6494 | |
c19d1205 ZW |
6495 | /* Frag hacking will turn this into a sub instruction if the offset turns |
6496 | out to be negative. */ | |
6497 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
c19d1205 ZW |
6498 | inst.reloc.pc_rel = 1; |
6499 | inst.size = INSN_SIZE * 2; | |
2fc8bdac | 6500 | inst.reloc.exp.X_add_number -= 8; |
b99bd4ef NC |
6501 | } |
6502 | ||
b99bd4ef | 6503 | static void |
c19d1205 | 6504 | do_arit (void) |
b99bd4ef | 6505 | { |
c19d1205 ZW |
6506 | if (!inst.operands[1].present) |
6507 | inst.operands[1].reg = inst.operands[0].reg; | |
6508 | inst.instruction |= inst.operands[0].reg << 12; | |
6509 | inst.instruction |= inst.operands[1].reg << 16; | |
6510 | encode_arm_shifter_operand (2); | |
6511 | } | |
b99bd4ef | 6512 | |
62b3e311 PB |
6513 | static void |
6514 | do_barrier (void) | |
6515 | { | |
6516 | if (inst.operands[0].present) | |
6517 | { | |
6518 | constraint ((inst.instruction & 0xf0) != 0x40 | |
6519 | && inst.operands[0].imm != 0xf, | |
6520 | "bad barrier type"); | |
6521 | inst.instruction |= inst.operands[0].imm; | |
6522 | } | |
6523 | else | |
6524 | inst.instruction |= 0xf; | |
6525 | } | |
6526 | ||
c19d1205 ZW |
6527 | static void |
6528 | do_bfc (void) | |
6529 | { | |
6530 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
6531 | constraint (msb > 32, _("bit-field extends past end of register")); | |
6532 | /* The instruction encoding stores the LSB and MSB, | |
6533 | not the LSB and width. */ | |
6534 | inst.instruction |= inst.operands[0].reg << 12; | |
6535 | inst.instruction |= inst.operands[1].imm << 7; | |
6536 | inst.instruction |= (msb - 1) << 16; | |
6537 | } | |
b99bd4ef | 6538 | |
c19d1205 ZW |
6539 | static void |
6540 | do_bfi (void) | |
6541 | { | |
6542 | unsigned int msb; | |
b99bd4ef | 6543 | |
c19d1205 ZW |
6544 | /* #0 in second position is alternative syntax for bfc, which is |
6545 | the same instruction but with REG_PC in the Rm field. */ | |
6546 | if (!inst.operands[1].isreg) | |
6547 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 6548 | |
c19d1205 ZW |
6549 | msb = inst.operands[2].imm + inst.operands[3].imm; |
6550 | constraint (msb > 32, _("bit-field extends past end of register")); | |
6551 | /* The instruction encoding stores the LSB and MSB, | |
6552 | not the LSB and width. */ | |
6553 | inst.instruction |= inst.operands[0].reg << 12; | |
6554 | inst.instruction |= inst.operands[1].reg; | |
6555 | inst.instruction |= inst.operands[2].imm << 7; | |
6556 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
6557 | } |
6558 | ||
b99bd4ef | 6559 | static void |
c19d1205 | 6560 | do_bfx (void) |
b99bd4ef | 6561 | { |
c19d1205 ZW |
6562 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
6563 | _("bit-field extends past end of register")); | |
6564 | inst.instruction |= inst.operands[0].reg << 12; | |
6565 | inst.instruction |= inst.operands[1].reg; | |
6566 | inst.instruction |= inst.operands[2].imm << 7; | |
6567 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
6568 | } | |
09d92015 | 6569 | |
c19d1205 ZW |
6570 | /* ARM V5 breakpoint instruction (argument parse) |
6571 | BKPT <16 bit unsigned immediate> | |
6572 | Instruction is not conditional. | |
6573 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
6574 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 6575 | |
c19d1205 ZW |
6576 | static void |
6577 | do_bkpt (void) | |
6578 | { | |
6579 | /* Top 12 of 16 bits to bits 19:8. */ | |
6580 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 6581 | |
c19d1205 ZW |
6582 | /* Bottom 4 of 16 bits to bits 3:0. */ |
6583 | inst.instruction |= inst.operands[0].imm & 0xf; | |
6584 | } | |
09d92015 | 6585 | |
c19d1205 ZW |
6586 | static void |
6587 | encode_branch (int default_reloc) | |
6588 | { | |
6589 | if (inst.operands[0].hasreloc) | |
6590 | { | |
6591 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32, | |
6592 | _("the only suffix valid here is '(plt)'")); | |
6593 | inst.reloc.type = BFD_RELOC_ARM_PLT32; | |
c19d1205 | 6594 | } |
b99bd4ef | 6595 | else |
c19d1205 ZW |
6596 | { |
6597 | inst.reloc.type = default_reloc; | |
c19d1205 | 6598 | } |
2fc8bdac | 6599 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
6600 | } |
6601 | ||
b99bd4ef | 6602 | static void |
c19d1205 | 6603 | do_branch (void) |
b99bd4ef | 6604 | { |
39b41c9c PB |
6605 | #ifdef OBJ_ELF |
6606 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
6607 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
6608 | else | |
6609 | #endif | |
6610 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
6611 | } | |
6612 | ||
6613 | static void | |
6614 | do_bl (void) | |
6615 | { | |
6616 | #ifdef OBJ_ELF | |
6617 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
6618 | { | |
6619 | if (inst.cond == COND_ALWAYS) | |
6620 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
6621 | else | |
6622 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
6623 | } | |
6624 | else | |
6625 | #endif | |
6626 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
c19d1205 | 6627 | } |
b99bd4ef | 6628 | |
c19d1205 ZW |
6629 | /* ARM V5 branch-link-exchange instruction (argument parse) |
6630 | BLX <target_addr> ie BLX(1) | |
6631 | BLX{<condition>} <Rm> ie BLX(2) | |
6632 | Unfortunately, there are two different opcodes for this mnemonic. | |
6633 | So, the insns[].value is not used, and the code here zaps values | |
6634 | into inst.instruction. | |
6635 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 6636 | |
c19d1205 ZW |
6637 | static void |
6638 | do_blx (void) | |
6639 | { | |
6640 | if (inst.operands[0].isreg) | |
b99bd4ef | 6641 | { |
c19d1205 ZW |
6642 | /* Arg is a register; the opcode provided by insns[] is correct. |
6643 | It is not illegal to do "blx pc", just useless. */ | |
6644 | if (inst.operands[0].reg == REG_PC) | |
6645 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 6646 | |
c19d1205 ZW |
6647 | inst.instruction |= inst.operands[0].reg; |
6648 | } | |
6649 | else | |
b99bd4ef | 6650 | { |
c19d1205 ZW |
6651 | /* Arg is an address; this instruction cannot be executed |
6652 | conditionally, and the opcode must be adjusted. */ | |
6653 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
2fc8bdac | 6654 | inst.instruction = 0xfa000000; |
39b41c9c PB |
6655 | #ifdef OBJ_ELF |
6656 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
6657 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
6658 | else | |
6659 | #endif | |
6660 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); | |
b99bd4ef | 6661 | } |
c19d1205 ZW |
6662 | } |
6663 | ||
6664 | static void | |
6665 | do_bx (void) | |
6666 | { | |
6667 | if (inst.operands[0].reg == REG_PC) | |
6668 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 6669 | |
c19d1205 | 6670 | inst.instruction |= inst.operands[0].reg; |
09d92015 MM |
6671 | } |
6672 | ||
c19d1205 ZW |
6673 | |
6674 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
6675 | |
6676 | static void | |
c19d1205 | 6677 | do_bxj (void) |
a737bd4d | 6678 | { |
c19d1205 ZW |
6679 | if (inst.operands[0].reg == REG_PC) |
6680 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
6681 | ||
6682 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
6683 | } |
6684 | ||
c19d1205 ZW |
6685 | /* Co-processor data operation: |
6686 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
6687 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
6688 | static void | |
6689 | do_cdp (void) | |
6690 | { | |
6691 | inst.instruction |= inst.operands[0].reg << 8; | |
6692 | inst.instruction |= inst.operands[1].imm << 20; | |
6693 | inst.instruction |= inst.operands[2].reg << 12; | |
6694 | inst.instruction |= inst.operands[3].reg << 16; | |
6695 | inst.instruction |= inst.operands[4].reg; | |
6696 | inst.instruction |= inst.operands[5].imm << 5; | |
6697 | } | |
a737bd4d NC |
6698 | |
6699 | static void | |
c19d1205 | 6700 | do_cmp (void) |
a737bd4d | 6701 | { |
c19d1205 ZW |
6702 | inst.instruction |= inst.operands[0].reg << 16; |
6703 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
6704 | } |
6705 | ||
c19d1205 ZW |
6706 | /* Transfer between coprocessor and ARM registers. |
6707 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
6708 | MRC2 | |
6709 | MCR{cond} | |
6710 | MCR2 | |
6711 | ||
6712 | No special properties. */ | |
09d92015 MM |
6713 | |
6714 | static void | |
c19d1205 | 6715 | do_co_reg (void) |
09d92015 | 6716 | { |
c19d1205 ZW |
6717 | inst.instruction |= inst.operands[0].reg << 8; |
6718 | inst.instruction |= inst.operands[1].imm << 21; | |
6719 | inst.instruction |= inst.operands[2].reg << 12; | |
6720 | inst.instruction |= inst.operands[3].reg << 16; | |
6721 | inst.instruction |= inst.operands[4].reg; | |
6722 | inst.instruction |= inst.operands[5].imm << 5; | |
6723 | } | |
09d92015 | 6724 | |
c19d1205 ZW |
6725 | /* Transfer between coprocessor register and pair of ARM registers. |
6726 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
6727 | MCRR2 | |
6728 | MRRC{cond} | |
6729 | MRRC2 | |
b99bd4ef | 6730 | |
c19d1205 | 6731 | Two XScale instructions are special cases of these: |
09d92015 | 6732 | |
c19d1205 ZW |
6733 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
6734 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 6735 | |
c19d1205 | 6736 | Result unpredicatable if Rd or Rn is R15. */ |
a737bd4d | 6737 | |
c19d1205 ZW |
6738 | static void |
6739 | do_co_reg2c (void) | |
6740 | { | |
6741 | inst.instruction |= inst.operands[0].reg << 8; | |
6742 | inst.instruction |= inst.operands[1].imm << 4; | |
6743 | inst.instruction |= inst.operands[2].reg << 12; | |
6744 | inst.instruction |= inst.operands[3].reg << 16; | |
6745 | inst.instruction |= inst.operands[4].reg; | |
b99bd4ef NC |
6746 | } |
6747 | ||
c19d1205 ZW |
6748 | static void |
6749 | do_cpsi (void) | |
6750 | { | |
6751 | inst.instruction |= inst.operands[0].imm << 6; | |
6752 | inst.instruction |= inst.operands[1].imm; | |
6753 | } | |
b99bd4ef | 6754 | |
62b3e311 PB |
6755 | static void |
6756 | do_dbg (void) | |
6757 | { | |
6758 | inst.instruction |= inst.operands[0].imm; | |
6759 | } | |
6760 | ||
b99bd4ef | 6761 | static void |
c19d1205 | 6762 | do_it (void) |
b99bd4ef | 6763 | { |
c19d1205 ZW |
6764 | /* There is no IT instruction in ARM mode. We |
6765 | process it but do not generate code for it. */ | |
6766 | inst.size = 0; | |
09d92015 | 6767 | } |
b99bd4ef | 6768 | |
09d92015 | 6769 | static void |
c19d1205 | 6770 | do_ldmstm (void) |
ea6ef066 | 6771 | { |
c19d1205 ZW |
6772 | int base_reg = inst.operands[0].reg; |
6773 | int range = inst.operands[1].imm; | |
ea6ef066 | 6774 | |
c19d1205 ZW |
6775 | inst.instruction |= base_reg << 16; |
6776 | inst.instruction |= range; | |
ea6ef066 | 6777 | |
c19d1205 ZW |
6778 | if (inst.operands[1].writeback) |
6779 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 6780 | |
c19d1205 | 6781 | if (inst.operands[0].writeback) |
ea6ef066 | 6782 | { |
c19d1205 ZW |
6783 | inst.instruction |= WRITE_BACK; |
6784 | /* Check for unpredictable uses of writeback. */ | |
6785 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 6786 | { |
c19d1205 ZW |
6787 | /* Not allowed in LDM type 2. */ |
6788 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
6789 | && ((range & (1 << REG_PC)) == 0)) | |
6790 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
6791 | /* Only allowed if base reg not in list for other types. */ | |
6792 | else if (range & (1 << base_reg)) | |
6793 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
6794 | } | |
6795 | else /* STM. */ | |
6796 | { | |
6797 | /* Not allowed for type 2. */ | |
6798 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
6799 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
6800 | /* Only allowed if base reg not in list, or first in list. */ | |
6801 | else if ((range & (1 << base_reg)) | |
6802 | && (range & ((1 << base_reg) - 1))) | |
6803 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 6804 | } |
ea6ef066 | 6805 | } |
a737bd4d NC |
6806 | } |
6807 | ||
c19d1205 ZW |
6808 | /* ARMv5TE load-consecutive (argument parse) |
6809 | Mode is like LDRH. | |
6810 | ||
6811 | LDRccD R, mode | |
6812 | STRccD R, mode. */ | |
6813 | ||
a737bd4d | 6814 | static void |
c19d1205 | 6815 | do_ldrd (void) |
a737bd4d | 6816 | { |
c19d1205 ZW |
6817 | constraint (inst.operands[0].reg % 2 != 0, |
6818 | _("first destination register must be even")); | |
6819 | constraint (inst.operands[1].present | |
6820 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
6821 | _("can only load two consecutive registers")); | |
6822 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
6823 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 6824 | |
c19d1205 ZW |
6825 | if (!inst.operands[1].present) |
6826 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
6827 | ||
6828 | if (inst.instruction & LOAD_BIT) | |
a737bd4d | 6829 | { |
c19d1205 ZW |
6830 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
6831 | register and the first register written; we have to diagnose | |
6832 | overlap between the base and the second register written here. */ | |
ea6ef066 | 6833 | |
c19d1205 ZW |
6834 | if (inst.operands[2].reg == inst.operands[1].reg |
6835 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
6836 | as_warn (_("base register written back, and overlaps " | |
6837 | "second destination register")); | |
b05fe5cf | 6838 | |
c19d1205 ZW |
6839 | /* For an index-register load, the index register must not overlap the |
6840 | destination (even if not write-back). */ | |
6841 | else if (inst.operands[2].immisreg | |
ca3f61f7 NC |
6842 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg |
6843 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
c19d1205 | 6844 | as_warn (_("index register overlaps destination register")); |
b05fe5cf | 6845 | } |
c19d1205 ZW |
6846 | |
6847 | inst.instruction |= inst.operands[0].reg << 12; | |
6848 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
6849 | } |
6850 | ||
6851 | static void | |
c19d1205 | 6852 | do_ldrex (void) |
b05fe5cf | 6853 | { |
c19d1205 ZW |
6854 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
6855 | || inst.operands[1].postind || inst.operands[1].writeback | |
6856 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
01cfc07f NC |
6857 | || inst.operands[1].negative |
6858 | /* This can arise if the programmer has written | |
6859 | strex rN, rM, foo | |
6860 | or if they have mistakenly used a register name as the last | |
6861 | operand, eg: | |
6862 | strex rN, rM, rX | |
6863 | It is very difficult to distinguish between these two cases | |
6864 | because "rX" might actually be a label. ie the register | |
6865 | name has been occluded by a symbol of the same name. So we | |
6866 | just generate a general 'bad addressing mode' type error | |
6867 | message and leave it up to the programmer to discover the | |
6868 | true cause and fix their mistake. */ | |
6869 | || (inst.operands[1].reg == REG_PC), | |
6870 | BAD_ADDR_MODE); | |
b05fe5cf | 6871 | |
c19d1205 ZW |
6872 | constraint (inst.reloc.exp.X_op != O_constant |
6873 | || inst.reloc.exp.X_add_number != 0, | |
6874 | _("offset must be zero in ARM encoding")); | |
b05fe5cf | 6875 | |
c19d1205 ZW |
6876 | inst.instruction |= inst.operands[0].reg << 12; |
6877 | inst.instruction |= inst.operands[1].reg << 16; | |
6878 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b05fe5cf ZW |
6879 | } |
6880 | ||
6881 | static void | |
c19d1205 | 6882 | do_ldrexd (void) |
b05fe5cf | 6883 | { |
c19d1205 ZW |
6884 | constraint (inst.operands[0].reg % 2 != 0, |
6885 | _("even register required")); | |
6886 | constraint (inst.operands[1].present | |
6887 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
6888 | _("can only load two consecutive registers")); | |
6889 | /* If op 1 were present and equal to PC, this function wouldn't | |
6890 | have been called in the first place. */ | |
6891 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 6892 | |
c19d1205 ZW |
6893 | inst.instruction |= inst.operands[0].reg << 12; |
6894 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
6895 | } |
6896 | ||
6897 | static void | |
c19d1205 | 6898 | do_ldst (void) |
b05fe5cf | 6899 | { |
c19d1205 ZW |
6900 | inst.instruction |= inst.operands[0].reg << 12; |
6901 | if (!inst.operands[1].isreg) | |
6902 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) | |
b05fe5cf | 6903 | return; |
c19d1205 | 6904 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
6905 | } |
6906 | ||
6907 | static void | |
c19d1205 | 6908 | do_ldstt (void) |
b05fe5cf | 6909 | { |
c19d1205 ZW |
6910 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
6911 | reject [Rn,...]. */ | |
6912 | if (inst.operands[1].preind) | |
b05fe5cf | 6913 | { |
c19d1205 ZW |
6914 | constraint (inst.reloc.exp.X_op != O_constant || |
6915 | inst.reloc.exp.X_add_number != 0, | |
6916 | _("this instruction requires a post-indexed address")); | |
b05fe5cf | 6917 | |
c19d1205 ZW |
6918 | inst.operands[1].preind = 0; |
6919 | inst.operands[1].postind = 1; | |
6920 | inst.operands[1].writeback = 1; | |
b05fe5cf | 6921 | } |
c19d1205 ZW |
6922 | inst.instruction |= inst.operands[0].reg << 12; |
6923 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
6924 | } | |
b05fe5cf | 6925 | |
c19d1205 | 6926 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 6927 | |
c19d1205 ZW |
6928 | static void |
6929 | do_ldstv4 (void) | |
6930 | { | |
6931 | inst.instruction |= inst.operands[0].reg << 12; | |
6932 | if (!inst.operands[1].isreg) | |
6933 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) | |
b05fe5cf | 6934 | return; |
c19d1205 | 6935 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
6936 | } |
6937 | ||
6938 | static void | |
c19d1205 | 6939 | do_ldsttv4 (void) |
b05fe5cf | 6940 | { |
c19d1205 ZW |
6941 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
6942 | reject [Rn,...]. */ | |
6943 | if (inst.operands[1].preind) | |
b05fe5cf | 6944 | { |
c19d1205 ZW |
6945 | constraint (inst.reloc.exp.X_op != O_constant || |
6946 | inst.reloc.exp.X_add_number != 0, | |
6947 | _("this instruction requires a post-indexed address")); | |
b05fe5cf | 6948 | |
c19d1205 ZW |
6949 | inst.operands[1].preind = 0; |
6950 | inst.operands[1].postind = 1; | |
6951 | inst.operands[1].writeback = 1; | |
b05fe5cf | 6952 | } |
c19d1205 ZW |
6953 | inst.instruction |= inst.operands[0].reg << 12; |
6954 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
6955 | } | |
b05fe5cf | 6956 | |
c19d1205 ZW |
6957 | /* Co-processor register load/store. |
6958 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
6959 | static void | |
6960 | do_lstc (void) | |
6961 | { | |
6962 | inst.instruction |= inst.operands[0].reg << 8; | |
6963 | inst.instruction |= inst.operands[1].reg << 12; | |
6964 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
6965 | } |
6966 | ||
b05fe5cf | 6967 | static void |
c19d1205 | 6968 | do_mlas (void) |
b05fe5cf | 6969 | { |
c19d1205 ZW |
6970 | /* This restriction does not apply to mls (nor to mla in v6, but |
6971 | that's hard to detect at present). */ | |
6972 | if (inst.operands[0].reg == inst.operands[1].reg | |
6973 | && !(inst.instruction & 0x00400000)) | |
6974 | as_tsktsk (_("rd and rm should be different in mla")); | |
b05fe5cf | 6975 | |
c19d1205 ZW |
6976 | inst.instruction |= inst.operands[0].reg << 16; |
6977 | inst.instruction |= inst.operands[1].reg; | |
6978 | inst.instruction |= inst.operands[2].reg << 8; | |
6979 | inst.instruction |= inst.operands[3].reg << 12; | |
b05fe5cf | 6980 | |
c19d1205 | 6981 | } |
b05fe5cf | 6982 | |
c19d1205 ZW |
6983 | static void |
6984 | do_mov (void) | |
6985 | { | |
6986 | inst.instruction |= inst.operands[0].reg << 12; | |
6987 | encode_arm_shifter_operand (1); | |
6988 | } | |
b05fe5cf | 6989 | |
c19d1205 ZW |
6990 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
6991 | static void | |
6992 | do_mov16 (void) | |
6993 | { | |
b6895b4f PB |
6994 | bfd_vma imm; |
6995 | bfd_boolean top; | |
6996 | ||
6997 | top = (inst.instruction & 0x00400000) != 0; | |
6998 | constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, | |
6999 | _(":lower16: not allowed this instruction")); | |
7000 | constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, | |
7001 | _(":upper16: not allowed instruction")); | |
c19d1205 | 7002 | inst.instruction |= inst.operands[0].reg << 12; |
b6895b4f PB |
7003 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
7004 | { | |
7005 | imm = inst.reloc.exp.X_add_number; | |
7006 | /* The value is in two pieces: 0:11, 16:19. */ | |
7007 | inst.instruction |= (imm & 0x00000fff); | |
7008 | inst.instruction |= (imm & 0x0000f000) << 4; | |
7009 | } | |
b05fe5cf | 7010 | } |
b99bd4ef | 7011 | |
037e8744 JB |
7012 | static void do_vfp_nsyn_opcode (const char *); |
7013 | ||
7014 | static int | |
7015 | do_vfp_nsyn_mrs (void) | |
7016 | { | |
7017 | if (inst.operands[0].isvec) | |
7018 | { | |
7019 | if (inst.operands[1].reg != 1) | |
7020 | first_error (_("operand 1 must be FPSCR")); | |
7021 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
7022 | memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); | |
7023 | do_vfp_nsyn_opcode ("fmstat"); | |
7024 | } | |
7025 | else if (inst.operands[1].isvec) | |
7026 | do_vfp_nsyn_opcode ("fmrx"); | |
7027 | else | |
7028 | return FAIL; | |
7029 | ||
7030 | return SUCCESS; | |
7031 | } | |
7032 | ||
7033 | static int | |
7034 | do_vfp_nsyn_msr (void) | |
7035 | { | |
7036 | if (inst.operands[0].isvec) | |
7037 | do_vfp_nsyn_opcode ("fmxr"); | |
7038 | else | |
7039 | return FAIL; | |
7040 | ||
7041 | return SUCCESS; | |
7042 | } | |
7043 | ||
b99bd4ef | 7044 | static void |
c19d1205 | 7045 | do_mrs (void) |
b99bd4ef | 7046 | { |
037e8744 JB |
7047 | if (do_vfp_nsyn_mrs () == SUCCESS) |
7048 | return; | |
7049 | ||
c19d1205 ZW |
7050 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ |
7051 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
7052 | != (PSR_c|PSR_f), | |
7053 | _("'CPSR' or 'SPSR' expected")); | |
7054 | inst.instruction |= inst.operands[0].reg << 12; | |
7055 | inst.instruction |= (inst.operands[1].imm & SPSR_BIT); | |
7056 | } | |
b99bd4ef | 7057 | |
c19d1205 ZW |
7058 | /* Two possible forms: |
7059 | "{C|S}PSR_<field>, Rm", | |
7060 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 7061 | |
c19d1205 ZW |
7062 | static void |
7063 | do_msr (void) | |
7064 | { | |
037e8744 JB |
7065 | if (do_vfp_nsyn_msr () == SUCCESS) |
7066 | return; | |
7067 | ||
c19d1205 ZW |
7068 | inst.instruction |= inst.operands[0].imm; |
7069 | if (inst.operands[1].isreg) | |
7070 | inst.instruction |= inst.operands[1].reg; | |
7071 | else | |
b99bd4ef | 7072 | { |
c19d1205 ZW |
7073 | inst.instruction |= INST_IMMEDIATE; |
7074 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
7075 | inst.reloc.pc_rel = 0; | |
b99bd4ef | 7076 | } |
b99bd4ef NC |
7077 | } |
7078 | ||
c19d1205 ZW |
7079 | static void |
7080 | do_mul (void) | |
a737bd4d | 7081 | { |
c19d1205 ZW |
7082 | if (!inst.operands[2].present) |
7083 | inst.operands[2].reg = inst.operands[0].reg; | |
7084 | inst.instruction |= inst.operands[0].reg << 16; | |
7085 | inst.instruction |= inst.operands[1].reg; | |
7086 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 7087 | |
c19d1205 ZW |
7088 | if (inst.operands[0].reg == inst.operands[1].reg) |
7089 | as_tsktsk (_("rd and rm should be different in mul")); | |
a737bd4d NC |
7090 | } |
7091 | ||
c19d1205 ZW |
7092 | /* Long Multiply Parser |
7093 | UMULL RdLo, RdHi, Rm, Rs | |
7094 | SMULL RdLo, RdHi, Rm, Rs | |
7095 | UMLAL RdLo, RdHi, Rm, Rs | |
7096 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
7097 | |
7098 | static void | |
c19d1205 | 7099 | do_mull (void) |
b99bd4ef | 7100 | { |
c19d1205 ZW |
7101 | inst.instruction |= inst.operands[0].reg << 12; |
7102 | inst.instruction |= inst.operands[1].reg << 16; | |
7103 | inst.instruction |= inst.operands[2].reg; | |
7104 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 7105 | |
c19d1205 ZW |
7106 | /* rdhi, rdlo and rm must all be different. */ |
7107 | if (inst.operands[0].reg == inst.operands[1].reg | |
7108 | || inst.operands[0].reg == inst.operands[2].reg | |
7109 | || inst.operands[1].reg == inst.operands[2].reg) | |
7110 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); | |
7111 | } | |
b99bd4ef | 7112 | |
c19d1205 ZW |
7113 | static void |
7114 | do_nop (void) | |
7115 | { | |
7116 | if (inst.operands[0].present) | |
7117 | { | |
7118 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
7119 | inst.instruction &= 0xf0000000; | |
7120 | inst.instruction |= 0x0320f000 + inst.operands[0].imm; | |
7121 | } | |
b99bd4ef NC |
7122 | } |
7123 | ||
c19d1205 ZW |
7124 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
7125 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
7126 | Condition defaults to COND_ALWAYS. | |
7127 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
7128 | |
7129 | static void | |
c19d1205 | 7130 | do_pkhbt (void) |
b99bd4ef | 7131 | { |
c19d1205 ZW |
7132 | inst.instruction |= inst.operands[0].reg << 12; |
7133 | inst.instruction |= inst.operands[1].reg << 16; | |
7134 | inst.instruction |= inst.operands[2].reg; | |
7135 | if (inst.operands[3].present) | |
7136 | encode_arm_shift (3); | |
7137 | } | |
b99bd4ef | 7138 | |
c19d1205 | 7139 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 7140 | |
c19d1205 ZW |
7141 | static void |
7142 | do_pkhtb (void) | |
7143 | { | |
7144 | if (!inst.operands[3].present) | |
b99bd4ef | 7145 | { |
c19d1205 ZW |
7146 | /* If the shift specifier is omitted, turn the instruction |
7147 | into pkhbt rd, rm, rn. */ | |
7148 | inst.instruction &= 0xfff00010; | |
7149 | inst.instruction |= inst.operands[0].reg << 12; | |
7150 | inst.instruction |= inst.operands[1].reg; | |
7151 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
7152 | } |
7153 | else | |
7154 | { | |
c19d1205 ZW |
7155 | inst.instruction |= inst.operands[0].reg << 12; |
7156 | inst.instruction |= inst.operands[1].reg << 16; | |
7157 | inst.instruction |= inst.operands[2].reg; | |
7158 | encode_arm_shift (3); | |
b99bd4ef NC |
7159 | } |
7160 | } | |
7161 | ||
c19d1205 ZW |
7162 | /* ARMv5TE: Preload-Cache |
7163 | ||
7164 | PLD <addr_mode> | |
7165 | ||
7166 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
7167 | |
7168 | static void | |
c19d1205 | 7169 | do_pld (void) |
b99bd4ef | 7170 | { |
c19d1205 ZW |
7171 | constraint (!inst.operands[0].isreg, |
7172 | _("'[' expected after PLD mnemonic")); | |
7173 | constraint (inst.operands[0].postind, | |
7174 | _("post-indexed expression used in preload instruction")); | |
7175 | constraint (inst.operands[0].writeback, | |
7176 | _("writeback used in preload instruction")); | |
7177 | constraint (!inst.operands[0].preind, | |
7178 | _("unindexed addressing used in preload instruction")); | |
c19d1205 ZW |
7179 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
7180 | } | |
b99bd4ef | 7181 | |
62b3e311 PB |
7182 | /* ARMv7: PLI <addr_mode> */ |
7183 | static void | |
7184 | do_pli (void) | |
7185 | { | |
7186 | constraint (!inst.operands[0].isreg, | |
7187 | _("'[' expected after PLI mnemonic")); | |
7188 | constraint (inst.operands[0].postind, | |
7189 | _("post-indexed expression used in preload instruction")); | |
7190 | constraint (inst.operands[0].writeback, | |
7191 | _("writeback used in preload instruction")); | |
7192 | constraint (!inst.operands[0].preind, | |
7193 | _("unindexed addressing used in preload instruction")); | |
7194 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
7195 | inst.instruction &= ~PRE_INDEX; | |
7196 | } | |
7197 | ||
c19d1205 ZW |
7198 | static void |
7199 | do_push_pop (void) | |
7200 | { | |
7201 | inst.operands[1] = inst.operands[0]; | |
7202 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
7203 | inst.operands[0].isreg = 1; | |
7204 | inst.operands[0].writeback = 1; | |
7205 | inst.operands[0].reg = REG_SP; | |
7206 | do_ldmstm (); | |
7207 | } | |
b99bd4ef | 7208 | |
c19d1205 ZW |
7209 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
7210 | word at the specified address and the following word | |
7211 | respectively. | |
7212 | Unconditionally executed. | |
7213 | Error if Rn is R15. */ | |
b99bd4ef | 7214 | |
c19d1205 ZW |
7215 | static void |
7216 | do_rfe (void) | |
7217 | { | |
7218 | inst.instruction |= inst.operands[0].reg << 16; | |
7219 | if (inst.operands[0].writeback) | |
7220 | inst.instruction |= WRITE_BACK; | |
7221 | } | |
b99bd4ef | 7222 | |
c19d1205 | 7223 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 7224 | |
c19d1205 ZW |
7225 | static void |
7226 | do_ssat (void) | |
7227 | { | |
7228 | inst.instruction |= inst.operands[0].reg << 12; | |
7229 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
7230 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 7231 | |
c19d1205 ZW |
7232 | if (inst.operands[3].present) |
7233 | encode_arm_shift (3); | |
b99bd4ef NC |
7234 | } |
7235 | ||
c19d1205 | 7236 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
7237 | |
7238 | static void | |
c19d1205 | 7239 | do_usat (void) |
b99bd4ef | 7240 | { |
c19d1205 ZW |
7241 | inst.instruction |= inst.operands[0].reg << 12; |
7242 | inst.instruction |= inst.operands[1].imm << 16; | |
7243 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 7244 | |
c19d1205 ZW |
7245 | if (inst.operands[3].present) |
7246 | encode_arm_shift (3); | |
b99bd4ef NC |
7247 | } |
7248 | ||
c19d1205 | 7249 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
7250 | |
7251 | static void | |
c19d1205 | 7252 | do_ssat16 (void) |
09d92015 | 7253 | { |
c19d1205 ZW |
7254 | inst.instruction |= inst.operands[0].reg << 12; |
7255 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
7256 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
7257 | } |
7258 | ||
c19d1205 ZW |
7259 | static void |
7260 | do_usat16 (void) | |
a737bd4d | 7261 | { |
c19d1205 ZW |
7262 | inst.instruction |= inst.operands[0].reg << 12; |
7263 | inst.instruction |= inst.operands[1].imm << 16; | |
7264 | inst.instruction |= inst.operands[2].reg; | |
7265 | } | |
a737bd4d | 7266 | |
c19d1205 ZW |
7267 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
7268 | preserving the other bits. | |
a737bd4d | 7269 | |
c19d1205 ZW |
7270 | setend <endian_specifier>, where <endian_specifier> is either |
7271 | BE or LE. */ | |
a737bd4d | 7272 | |
c19d1205 ZW |
7273 | static void |
7274 | do_setend (void) | |
7275 | { | |
7276 | if (inst.operands[0].imm) | |
7277 | inst.instruction |= 0x200; | |
a737bd4d NC |
7278 | } |
7279 | ||
7280 | static void | |
c19d1205 | 7281 | do_shift (void) |
a737bd4d | 7282 | { |
c19d1205 ZW |
7283 | unsigned int Rm = (inst.operands[1].present |
7284 | ? inst.operands[1].reg | |
7285 | : inst.operands[0].reg); | |
a737bd4d | 7286 | |
c19d1205 ZW |
7287 | inst.instruction |= inst.operands[0].reg << 12; |
7288 | inst.instruction |= Rm; | |
7289 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 7290 | { |
c19d1205 ZW |
7291 | inst.instruction |= inst.operands[2].reg << 8; |
7292 | inst.instruction |= SHIFT_BY_REG; | |
a737bd4d NC |
7293 | } |
7294 | else | |
c19d1205 | 7295 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
7296 | } |
7297 | ||
09d92015 | 7298 | static void |
3eb17e6b | 7299 | do_smc (void) |
09d92015 | 7300 | { |
3eb17e6b | 7301 | inst.reloc.type = BFD_RELOC_ARM_SMC; |
c19d1205 | 7302 | inst.reloc.pc_rel = 0; |
09d92015 MM |
7303 | } |
7304 | ||
09d92015 | 7305 | static void |
c19d1205 | 7306 | do_swi (void) |
09d92015 | 7307 | { |
c19d1205 ZW |
7308 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
7309 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
7310 | } |
7311 | ||
c19d1205 ZW |
7312 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
7313 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
7314 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
7315 | Error if any register is R15. */ | |
e16bb312 | 7316 | |
c19d1205 ZW |
7317 | static void |
7318 | do_smla (void) | |
e16bb312 | 7319 | { |
c19d1205 ZW |
7320 | inst.instruction |= inst.operands[0].reg << 16; |
7321 | inst.instruction |= inst.operands[1].reg; | |
7322 | inst.instruction |= inst.operands[2].reg << 8; | |
7323 | inst.instruction |= inst.operands[3].reg << 12; | |
7324 | } | |
a737bd4d | 7325 | |
c19d1205 ZW |
7326 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
7327 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
7328 | Error if any register is R15. | |
7329 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 7330 | |
c19d1205 ZW |
7331 | static void |
7332 | do_smlal (void) | |
7333 | { | |
7334 | inst.instruction |= inst.operands[0].reg << 12; | |
7335 | inst.instruction |= inst.operands[1].reg << 16; | |
7336 | inst.instruction |= inst.operands[2].reg; | |
7337 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 7338 | |
c19d1205 ZW |
7339 | if (inst.operands[0].reg == inst.operands[1].reg) |
7340 | as_tsktsk (_("rdhi and rdlo must be different")); | |
7341 | } | |
a737bd4d | 7342 | |
c19d1205 ZW |
7343 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
7344 | SMULxy{cond} Rd,Rm,Rs | |
7345 | Error if any register is R15. */ | |
a737bd4d | 7346 | |
c19d1205 ZW |
7347 | static void |
7348 | do_smul (void) | |
7349 | { | |
7350 | inst.instruction |= inst.operands[0].reg << 16; | |
7351 | inst.instruction |= inst.operands[1].reg; | |
7352 | inst.instruction |= inst.operands[2].reg << 8; | |
7353 | } | |
a737bd4d | 7354 | |
c19d1205 | 7355 | /* ARM V6 srs (argument parse). */ |
a737bd4d | 7356 | |
c19d1205 ZW |
7357 | static void |
7358 | do_srs (void) | |
7359 | { | |
7360 | inst.instruction |= inst.operands[0].imm; | |
7361 | if (inst.operands[0].writeback) | |
7362 | inst.instruction |= WRITE_BACK; | |
7363 | } | |
a737bd4d | 7364 | |
c19d1205 | 7365 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 7366 | |
c19d1205 ZW |
7367 | static void |
7368 | do_strex (void) | |
7369 | { | |
7370 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
7371 | || inst.operands[2].postind || inst.operands[2].writeback | |
7372 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
01cfc07f NC |
7373 | || inst.operands[2].negative |
7374 | /* See comment in do_ldrex(). */ | |
7375 | || (inst.operands[2].reg == REG_PC), | |
7376 | BAD_ADDR_MODE); | |
a737bd4d | 7377 | |
c19d1205 ZW |
7378 | constraint (inst.operands[0].reg == inst.operands[1].reg |
7379 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 7380 | |
c19d1205 ZW |
7381 | constraint (inst.reloc.exp.X_op != O_constant |
7382 | || inst.reloc.exp.X_add_number != 0, | |
7383 | _("offset must be zero in ARM encoding")); | |
a737bd4d | 7384 | |
c19d1205 ZW |
7385 | inst.instruction |= inst.operands[0].reg << 12; |
7386 | inst.instruction |= inst.operands[1].reg; | |
7387 | inst.instruction |= inst.operands[2].reg << 16; | |
7388 | inst.reloc.type = BFD_RELOC_UNUSED; | |
e16bb312 NC |
7389 | } |
7390 | ||
7391 | static void | |
c19d1205 | 7392 | do_strexd (void) |
e16bb312 | 7393 | { |
c19d1205 ZW |
7394 | constraint (inst.operands[1].reg % 2 != 0, |
7395 | _("even register required")); | |
7396 | constraint (inst.operands[2].present | |
7397 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
7398 | _("can only store two consecutive registers")); | |
7399 | /* If op 2 were present and equal to PC, this function wouldn't | |
7400 | have been called in the first place. */ | |
7401 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 7402 | |
c19d1205 ZW |
7403 | constraint (inst.operands[0].reg == inst.operands[1].reg |
7404 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
7405 | || inst.operands[0].reg == inst.operands[3].reg, | |
7406 | BAD_OVERLAP); | |
e16bb312 | 7407 | |
c19d1205 ZW |
7408 | inst.instruction |= inst.operands[0].reg << 12; |
7409 | inst.instruction |= inst.operands[1].reg; | |
7410 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
7411 | } |
7412 | ||
c19d1205 ZW |
7413 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
7414 | extends it to 32-bits, and adds the result to a value in another | |
7415 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
7416 | before extracting the 16-bit value. | |
7417 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
7418 | Condition defaults to COND_ALWAYS. | |
7419 | Error if any register uses R15. */ | |
7420 | ||
e16bb312 | 7421 | static void |
c19d1205 | 7422 | do_sxtah (void) |
e16bb312 | 7423 | { |
c19d1205 ZW |
7424 | inst.instruction |= inst.operands[0].reg << 12; |
7425 | inst.instruction |= inst.operands[1].reg << 16; | |
7426 | inst.instruction |= inst.operands[2].reg; | |
7427 | inst.instruction |= inst.operands[3].imm << 10; | |
7428 | } | |
e16bb312 | 7429 | |
c19d1205 | 7430 | /* ARM V6 SXTH. |
e16bb312 | 7431 | |
c19d1205 ZW |
7432 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
7433 | Condition defaults to COND_ALWAYS. | |
7434 | Error if any register uses R15. */ | |
e16bb312 NC |
7435 | |
7436 | static void | |
c19d1205 | 7437 | do_sxth (void) |
e16bb312 | 7438 | { |
c19d1205 ZW |
7439 | inst.instruction |= inst.operands[0].reg << 12; |
7440 | inst.instruction |= inst.operands[1].reg; | |
7441 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 7442 | } |
c19d1205 ZW |
7443 | \f |
7444 | /* VFP instructions. In a logical order: SP variant first, monad | |
7445 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
7446 | |
7447 | static void | |
c19d1205 | 7448 | do_vfp_sp_monadic (void) |
e16bb312 | 7449 | { |
5287ad62 JB |
7450 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
7451 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
7452 | } |
7453 | ||
7454 | static void | |
c19d1205 | 7455 | do_vfp_sp_dyadic (void) |
e16bb312 | 7456 | { |
5287ad62 JB |
7457 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
7458 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
7459 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
7460 | } |
7461 | ||
7462 | static void | |
c19d1205 | 7463 | do_vfp_sp_compare_z (void) |
e16bb312 | 7464 | { |
5287ad62 | 7465 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
7466 | } |
7467 | ||
7468 | static void | |
c19d1205 | 7469 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 7470 | { |
5287ad62 JB |
7471 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
7472 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
7473 | } |
7474 | ||
7475 | static void | |
c19d1205 | 7476 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 7477 | { |
5287ad62 JB |
7478 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
7479 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
e16bb312 NC |
7480 | } |
7481 | ||
7482 | static void | |
c19d1205 | 7483 | do_vfp_reg_from_sp (void) |
e16bb312 | 7484 | { |
c19d1205 | 7485 | inst.instruction |= inst.operands[0].reg << 12; |
5287ad62 | 7486 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); |
e16bb312 NC |
7487 | } |
7488 | ||
7489 | static void | |
c19d1205 | 7490 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 7491 | { |
c19d1205 ZW |
7492 | constraint (inst.operands[2].imm != 2, |
7493 | _("only two consecutive VFP SP registers allowed here")); | |
7494 | inst.instruction |= inst.operands[0].reg << 12; | |
7495 | inst.instruction |= inst.operands[1].reg << 16; | |
5287ad62 | 7496 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); |
e16bb312 NC |
7497 | } |
7498 | ||
7499 | static void | |
c19d1205 | 7500 | do_vfp_sp_from_reg (void) |
e16bb312 | 7501 | { |
5287ad62 | 7502 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); |
c19d1205 | 7503 | inst.instruction |= inst.operands[1].reg << 12; |
e16bb312 NC |
7504 | } |
7505 | ||
7506 | static void | |
c19d1205 | 7507 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 7508 | { |
c19d1205 ZW |
7509 | constraint (inst.operands[0].imm != 2, |
7510 | _("only two consecutive VFP SP registers allowed here")); | |
5287ad62 | 7511 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); |
c19d1205 ZW |
7512 | inst.instruction |= inst.operands[1].reg << 12; |
7513 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
7514 | } |
7515 | ||
7516 | static void | |
c19d1205 | 7517 | do_vfp_sp_ldst (void) |
e16bb312 | 7518 | { |
5287ad62 | 7519 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
c19d1205 | 7520 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
7521 | } |
7522 | ||
7523 | static void | |
c19d1205 | 7524 | do_vfp_dp_ldst (void) |
e16bb312 | 7525 | { |
5287ad62 | 7526 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
c19d1205 | 7527 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
7528 | } |
7529 | ||
c19d1205 | 7530 | |
e16bb312 | 7531 | static void |
c19d1205 | 7532 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 7533 | { |
c19d1205 ZW |
7534 | if (inst.operands[0].writeback) |
7535 | inst.instruction |= WRITE_BACK; | |
7536 | else | |
7537 | constraint (ldstm_type != VFP_LDSTMIA, | |
7538 | _("this addressing mode requires base-register writeback")); | |
7539 | inst.instruction |= inst.operands[0].reg << 16; | |
5287ad62 | 7540 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); |
c19d1205 | 7541 | inst.instruction |= inst.operands[1].imm; |
e16bb312 NC |
7542 | } |
7543 | ||
7544 | static void | |
c19d1205 | 7545 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 7546 | { |
c19d1205 | 7547 | int count; |
e16bb312 | 7548 | |
c19d1205 ZW |
7549 | if (inst.operands[0].writeback) |
7550 | inst.instruction |= WRITE_BACK; | |
7551 | else | |
7552 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
7553 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 7554 | |
c19d1205 | 7555 | inst.instruction |= inst.operands[0].reg << 16; |
5287ad62 | 7556 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
e16bb312 | 7557 | |
c19d1205 ZW |
7558 | count = inst.operands[1].imm << 1; |
7559 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
7560 | count += 1; | |
e16bb312 | 7561 | |
c19d1205 | 7562 | inst.instruction |= count; |
e16bb312 NC |
7563 | } |
7564 | ||
7565 | static void | |
c19d1205 | 7566 | do_vfp_sp_ldstmia (void) |
e16bb312 | 7567 | { |
c19d1205 | 7568 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
7569 | } |
7570 | ||
7571 | static void | |
c19d1205 | 7572 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 7573 | { |
c19d1205 | 7574 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
7575 | } |
7576 | ||
7577 | static void | |
c19d1205 | 7578 | do_vfp_dp_ldstmia (void) |
e16bb312 | 7579 | { |
c19d1205 | 7580 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
7581 | } |
7582 | ||
7583 | static void | |
c19d1205 | 7584 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 7585 | { |
c19d1205 | 7586 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
7587 | } |
7588 | ||
7589 | static void | |
c19d1205 | 7590 | do_vfp_xp_ldstmia (void) |
e16bb312 | 7591 | { |
c19d1205 ZW |
7592 | vfp_dp_ldstm (VFP_LDSTMIAX); |
7593 | } | |
e16bb312 | 7594 | |
c19d1205 ZW |
7595 | static void |
7596 | do_vfp_xp_ldstmdb (void) | |
7597 | { | |
7598 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 7599 | } |
5287ad62 JB |
7600 | |
7601 | static void | |
7602 | do_vfp_dp_rd_rm (void) | |
7603 | { | |
7604 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
7605 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
7606 | } | |
7607 | ||
7608 | static void | |
7609 | do_vfp_dp_rn_rd (void) | |
7610 | { | |
7611 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); | |
7612 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
7613 | } | |
7614 | ||
7615 | static void | |
7616 | do_vfp_dp_rd_rn (void) | |
7617 | { | |
7618 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
7619 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
7620 | } | |
7621 | ||
7622 | static void | |
7623 | do_vfp_dp_rd_rn_rm (void) | |
7624 | { | |
7625 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
7626 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
7627 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); | |
7628 | } | |
7629 | ||
7630 | static void | |
7631 | do_vfp_dp_rd (void) | |
7632 | { | |
7633 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
7634 | } | |
7635 | ||
7636 | static void | |
7637 | do_vfp_dp_rm_rd_rn (void) | |
7638 | { | |
7639 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); | |
7640 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
7641 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); | |
7642 | } | |
7643 | ||
7644 | /* VFPv3 instructions. */ | |
7645 | static void | |
7646 | do_vfp_sp_const (void) | |
7647 | { | |
7648 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
7649 | inst.instruction |= (inst.operands[1].imm & 15) << 16; | |
7650 | inst.instruction |= (inst.operands[1].imm >> 4); | |
7651 | } | |
7652 | ||
7653 | static void | |
7654 | do_vfp_dp_const (void) | |
7655 | { | |
7656 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
7657 | inst.instruction |= (inst.operands[1].imm & 15) << 16; | |
7658 | inst.instruction |= (inst.operands[1].imm >> 4); | |
7659 | } | |
7660 | ||
7661 | static void | |
7662 | vfp_conv (int srcsize) | |
7663 | { | |
7664 | unsigned immbits = srcsize - inst.operands[1].imm; | |
7665 | inst.instruction |= (immbits & 1) << 5; | |
7666 | inst.instruction |= (immbits >> 1); | |
7667 | } | |
7668 | ||
7669 | static void | |
7670 | do_vfp_sp_conv_16 (void) | |
7671 | { | |
7672 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
7673 | vfp_conv (16); | |
7674 | } | |
7675 | ||
7676 | static void | |
7677 | do_vfp_dp_conv_16 (void) | |
7678 | { | |
7679 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
7680 | vfp_conv (16); | |
7681 | } | |
7682 | ||
7683 | static void | |
7684 | do_vfp_sp_conv_32 (void) | |
7685 | { | |
7686 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
7687 | vfp_conv (32); | |
7688 | } | |
7689 | ||
7690 | static void | |
7691 | do_vfp_dp_conv_32 (void) | |
7692 | { | |
7693 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
7694 | vfp_conv (32); | |
7695 | } | |
7696 | ||
c19d1205 ZW |
7697 | \f |
7698 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 7699 | |
c19d1205 ZW |
7700 | static void |
7701 | do_fpa_cmp (void) | |
7702 | { | |
7703 | inst.instruction |= inst.operands[0].reg << 16; | |
7704 | inst.instruction |= inst.operands[1].reg; | |
7705 | } | |
b99bd4ef NC |
7706 | |
7707 | static void | |
c19d1205 | 7708 | do_fpa_ldmstm (void) |
b99bd4ef | 7709 | { |
c19d1205 ZW |
7710 | inst.instruction |= inst.operands[0].reg << 12; |
7711 | switch (inst.operands[1].imm) | |
7712 | { | |
7713 | case 1: inst.instruction |= CP_T_X; break; | |
7714 | case 2: inst.instruction |= CP_T_Y; break; | |
7715 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
7716 | case 4: break; | |
7717 | default: abort (); | |
7718 | } | |
b99bd4ef | 7719 | |
c19d1205 ZW |
7720 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
7721 | { | |
7722 | /* The instruction specified "ea" or "fd", so we can only accept | |
7723 | [Rn]{!}. The instruction does not really support stacking or | |
7724 | unstacking, so we have to emulate these by setting appropriate | |
7725 | bits and offsets. */ | |
7726 | constraint (inst.reloc.exp.X_op != O_constant | |
7727 | || inst.reloc.exp.X_add_number != 0, | |
7728 | _("this instruction does not support indexing")); | |
b99bd4ef | 7729 | |
c19d1205 ZW |
7730 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
7731 | inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; | |
b99bd4ef | 7732 | |
c19d1205 ZW |
7733 | if (!(inst.instruction & INDEX_UP)) |
7734 | inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; | |
b99bd4ef | 7735 | |
c19d1205 ZW |
7736 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
7737 | { | |
7738 | inst.operands[2].preind = 0; | |
7739 | inst.operands[2].postind = 1; | |
7740 | } | |
7741 | } | |
b99bd4ef | 7742 | |
c19d1205 | 7743 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 7744 | } |
037e8744 | 7745 | |
c19d1205 ZW |
7746 | \f |
7747 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 7748 | |
c19d1205 ZW |
7749 | static void |
7750 | do_iwmmxt_tandorc (void) | |
7751 | { | |
7752 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
7753 | } | |
b99bd4ef | 7754 | |
c19d1205 ZW |
7755 | static void |
7756 | do_iwmmxt_textrc (void) | |
7757 | { | |
7758 | inst.instruction |= inst.operands[0].reg << 12; | |
7759 | inst.instruction |= inst.operands[1].imm; | |
7760 | } | |
b99bd4ef NC |
7761 | |
7762 | static void | |
c19d1205 | 7763 | do_iwmmxt_textrm (void) |
b99bd4ef | 7764 | { |
c19d1205 ZW |
7765 | inst.instruction |= inst.operands[0].reg << 12; |
7766 | inst.instruction |= inst.operands[1].reg << 16; | |
7767 | inst.instruction |= inst.operands[2].imm; | |
7768 | } | |
b99bd4ef | 7769 | |
c19d1205 ZW |
7770 | static void |
7771 | do_iwmmxt_tinsr (void) | |
7772 | { | |
7773 | inst.instruction |= inst.operands[0].reg << 16; | |
7774 | inst.instruction |= inst.operands[1].reg << 12; | |
7775 | inst.instruction |= inst.operands[2].imm; | |
7776 | } | |
b99bd4ef | 7777 | |
c19d1205 ZW |
7778 | static void |
7779 | do_iwmmxt_tmia (void) | |
7780 | { | |
7781 | inst.instruction |= inst.operands[0].reg << 5; | |
7782 | inst.instruction |= inst.operands[1].reg; | |
7783 | inst.instruction |= inst.operands[2].reg << 12; | |
7784 | } | |
b99bd4ef | 7785 | |
c19d1205 ZW |
7786 | static void |
7787 | do_iwmmxt_waligni (void) | |
7788 | { | |
7789 | inst.instruction |= inst.operands[0].reg << 12; | |
7790 | inst.instruction |= inst.operands[1].reg << 16; | |
7791 | inst.instruction |= inst.operands[2].reg; | |
7792 | inst.instruction |= inst.operands[3].imm << 20; | |
7793 | } | |
b99bd4ef | 7794 | |
c19d1205 ZW |
7795 | static void |
7796 | do_iwmmxt_wmov (void) | |
7797 | { | |
7798 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
7799 | inst.instruction |= inst.operands[0].reg << 12; | |
7800 | inst.instruction |= inst.operands[1].reg << 16; | |
7801 | inst.instruction |= inst.operands[1].reg; | |
7802 | } | |
b99bd4ef | 7803 | |
c19d1205 ZW |
7804 | static void |
7805 | do_iwmmxt_wldstbh (void) | |
7806 | { | |
8f06b2d8 | 7807 | int reloc; |
c19d1205 | 7808 | inst.instruction |= inst.operands[0].reg << 12; |
8f06b2d8 PB |
7809 | if (thumb_mode) |
7810 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
7811 | else | |
7812 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
7813 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
7814 | } |
7815 | ||
c19d1205 ZW |
7816 | static void |
7817 | do_iwmmxt_wldstw (void) | |
7818 | { | |
7819 | /* RIWR_RIWC clears .isreg for a control register. */ | |
7820 | if (!inst.operands[0].isreg) | |
7821 | { | |
7822 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
7823 | inst.instruction |= 0xf0000000; | |
7824 | } | |
b99bd4ef | 7825 | |
c19d1205 ZW |
7826 | inst.instruction |= inst.operands[0].reg << 12; |
7827 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
7828 | } | |
b99bd4ef NC |
7829 | |
7830 | static void | |
c19d1205 | 7831 | do_iwmmxt_wldstd (void) |
b99bd4ef | 7832 | { |
c19d1205 | 7833 | inst.instruction |= inst.operands[0].reg << 12; |
f2184508 | 7834 | encode_arm_cp_address (1, TRUE, FALSE, 0); |
c19d1205 | 7835 | } |
b99bd4ef | 7836 | |
c19d1205 ZW |
7837 | static void |
7838 | do_iwmmxt_wshufh (void) | |
7839 | { | |
7840 | inst.instruction |= inst.operands[0].reg << 12; | |
7841 | inst.instruction |= inst.operands[1].reg << 16; | |
7842 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
7843 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
7844 | } | |
b99bd4ef | 7845 | |
c19d1205 ZW |
7846 | static void |
7847 | do_iwmmxt_wzero (void) | |
7848 | { | |
7849 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
7850 | inst.instruction |= inst.operands[0].reg; | |
7851 | inst.instruction |= inst.operands[0].reg << 12; | |
7852 | inst.instruction |= inst.operands[0].reg << 16; | |
7853 | } | |
7854 | \f | |
7855 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
7856 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 7857 | |
c19d1205 | 7858 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 7859 | |
c19d1205 ZW |
7860 | static void |
7861 | do_mav_triple (void) | |
7862 | { | |
7863 | inst.instruction |= inst.operands[0].reg << 16; | |
7864 | inst.instruction |= inst.operands[1].reg; | |
7865 | inst.instruction |= inst.operands[2].reg << 12; | |
7866 | } | |
b99bd4ef | 7867 | |
c19d1205 ZW |
7868 | /* Insns like "foo W,X,Y,Z". |
7869 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 7870 | |
c19d1205 ZW |
7871 | static void |
7872 | do_mav_quad (void) | |
7873 | { | |
7874 | inst.instruction |= inst.operands[0].reg << 5; | |
7875 | inst.instruction |= inst.operands[1].reg << 12; | |
7876 | inst.instruction |= inst.operands[2].reg << 16; | |
7877 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
7878 | } |
7879 | ||
c19d1205 ZW |
7880 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
7881 | static void | |
7882 | do_mav_dspsc (void) | |
a737bd4d | 7883 | { |
c19d1205 ZW |
7884 | inst.instruction |= inst.operands[1].reg << 12; |
7885 | } | |
a737bd4d | 7886 | |
c19d1205 ZW |
7887 | /* Maverick shift immediate instructions. |
7888 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
7889 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 7890 | |
c19d1205 ZW |
7891 | static void |
7892 | do_mav_shift (void) | |
7893 | { | |
7894 | int imm = inst.operands[2].imm; | |
a737bd4d | 7895 | |
c19d1205 ZW |
7896 | inst.instruction |= inst.operands[0].reg << 12; |
7897 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 7898 | |
c19d1205 ZW |
7899 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
7900 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
7901 | Bit 4 should be 0. */ | |
7902 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 7903 | |
c19d1205 ZW |
7904 | inst.instruction |= imm; |
7905 | } | |
7906 | \f | |
7907 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 7908 | |
c19d1205 ZW |
7909 | /* Xscale multiply-accumulate (argument parse) |
7910 | MIAcc acc0,Rm,Rs | |
7911 | MIAPHcc acc0,Rm,Rs | |
7912 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 7913 | |
c19d1205 ZW |
7914 | static void |
7915 | do_xsc_mia (void) | |
7916 | { | |
7917 | inst.instruction |= inst.operands[1].reg; | |
7918 | inst.instruction |= inst.operands[2].reg << 12; | |
7919 | } | |
a737bd4d | 7920 | |
c19d1205 | 7921 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 7922 | |
c19d1205 | 7923 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 7924 | |
c19d1205 ZW |
7925 | static void |
7926 | do_xsc_mar (void) | |
7927 | { | |
7928 | inst.instruction |= inst.operands[1].reg << 12; | |
7929 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
7930 | } |
7931 | ||
c19d1205 | 7932 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 7933 | |
c19d1205 | 7934 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
7935 | |
7936 | static void | |
c19d1205 | 7937 | do_xsc_mra (void) |
b99bd4ef | 7938 | { |
c19d1205 ZW |
7939 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
7940 | inst.instruction |= inst.operands[0].reg << 12; | |
7941 | inst.instruction |= inst.operands[1].reg << 16; | |
7942 | } | |
7943 | \f | |
7944 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 7945 | |
c19d1205 ZW |
7946 | /* inst.operands[i] is a shifted-register operand; encode |
7947 | it into inst.instruction in the format used by Thumb32. */ | |
7948 | ||
7949 | static void | |
7950 | encode_thumb32_shifted_operand (int i) | |
7951 | { | |
7952 | unsigned int value = inst.reloc.exp.X_add_number; | |
7953 | unsigned int shift = inst.operands[i].shift_kind; | |
b99bd4ef | 7954 | |
9c3c69f2 PB |
7955 | constraint (inst.operands[i].immisreg, |
7956 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
7957 | inst.instruction |= inst.operands[i].reg; |
7958 | if (shift == SHIFT_RRX) | |
7959 | inst.instruction |= SHIFT_ROR << 4; | |
7960 | else | |
b99bd4ef | 7961 | { |
c19d1205 ZW |
7962 | constraint (inst.reloc.exp.X_op != O_constant, |
7963 | _("expression too complex")); | |
7964 | ||
7965 | constraint (value > 32 | |
7966 | || (value == 32 && (shift == SHIFT_LSL | |
7967 | || shift == SHIFT_ROR)), | |
7968 | _("shift expression is too large")); | |
7969 | ||
7970 | if (value == 0) | |
7971 | shift = SHIFT_LSL; | |
7972 | else if (value == 32) | |
7973 | value = 0; | |
7974 | ||
7975 | inst.instruction |= shift << 4; | |
7976 | inst.instruction |= (value & 0x1c) << 10; | |
7977 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 7978 | } |
c19d1205 | 7979 | } |
b99bd4ef | 7980 | |
b99bd4ef | 7981 | |
c19d1205 ZW |
7982 | /* inst.operands[i] was set up by parse_address. Encode it into a |
7983 | Thumb32 format load or store instruction. Reject forms that cannot | |
7984 | be used with such instructions. If is_t is true, reject forms that | |
7985 | cannot be used with a T instruction; if is_d is true, reject forms | |
7986 | that cannot be used with a D instruction. */ | |
b99bd4ef | 7987 | |
c19d1205 ZW |
7988 | static void |
7989 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
7990 | { | |
7991 | bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); | |
7992 | ||
7993 | constraint (!inst.operands[i].isreg, | |
53365c0d | 7994 | _("Instruction does not support =N addresses")); |
b99bd4ef | 7995 | |
c19d1205 ZW |
7996 | inst.instruction |= inst.operands[i].reg << 16; |
7997 | if (inst.operands[i].immisreg) | |
b99bd4ef | 7998 | { |
c19d1205 ZW |
7999 | constraint (is_pc, _("cannot use register index with PC-relative addressing")); |
8000 | constraint (is_t || is_d, _("cannot use register index with this instruction")); | |
8001 | constraint (inst.operands[i].negative, | |
8002 | _("Thumb does not support negative register indexing")); | |
8003 | constraint (inst.operands[i].postind, | |
8004 | _("Thumb does not support register post-indexing")); | |
8005 | constraint (inst.operands[i].writeback, | |
8006 | _("Thumb does not support register indexing with writeback")); | |
8007 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
8008 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 8009 | |
f40d1643 | 8010 | inst.instruction |= inst.operands[i].imm; |
c19d1205 | 8011 | if (inst.operands[i].shifted) |
b99bd4ef | 8012 | { |
c19d1205 ZW |
8013 | constraint (inst.reloc.exp.X_op != O_constant, |
8014 | _("expression too complex")); | |
9c3c69f2 PB |
8015 | constraint (inst.reloc.exp.X_add_number < 0 |
8016 | || inst.reloc.exp.X_add_number > 3, | |
c19d1205 | 8017 | _("shift out of range")); |
9c3c69f2 | 8018 | inst.instruction |= inst.reloc.exp.X_add_number << 4; |
c19d1205 ZW |
8019 | } |
8020 | inst.reloc.type = BFD_RELOC_UNUSED; | |
8021 | } | |
8022 | else if (inst.operands[i].preind) | |
8023 | { | |
8024 | constraint (is_pc && inst.operands[i].writeback, | |
8025 | _("cannot use writeback with PC-relative addressing")); | |
f40d1643 | 8026 | constraint (is_t && inst.operands[i].writeback, |
c19d1205 ZW |
8027 | _("cannot use writeback with this instruction")); |
8028 | ||
8029 | if (is_d) | |
8030 | { | |
8031 | inst.instruction |= 0x01000000; | |
8032 | if (inst.operands[i].writeback) | |
8033 | inst.instruction |= 0x00200000; | |
b99bd4ef | 8034 | } |
c19d1205 | 8035 | else |
b99bd4ef | 8036 | { |
c19d1205 ZW |
8037 | inst.instruction |= 0x00000c00; |
8038 | if (inst.operands[i].writeback) | |
8039 | inst.instruction |= 0x00000100; | |
b99bd4ef | 8040 | } |
c19d1205 | 8041 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 8042 | } |
c19d1205 | 8043 | else if (inst.operands[i].postind) |
b99bd4ef | 8044 | { |
c19d1205 ZW |
8045 | assert (inst.operands[i].writeback); |
8046 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); | |
8047 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
8048 | ||
8049 | if (is_d) | |
8050 | inst.instruction |= 0x00200000; | |
8051 | else | |
8052 | inst.instruction |= 0x00000900; | |
8053 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
8054 | } | |
8055 | else /* unindexed - only for coprocessor */ | |
8056 | inst.error = _("instruction does not accept unindexed addressing"); | |
8057 | } | |
8058 | ||
8059 | /* Table of Thumb instructions which exist in both 16- and 32-bit | |
8060 | encodings (the latter only in post-V6T2 cores). The index is the | |
8061 | value used in the insns table below. When there is more than one | |
8062 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
8063 | holds variant (1). |
8064 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 ZW |
8065 | #define T16_32_TAB \ |
8066 | X(adc, 4140, eb400000), \ | |
8067 | X(adcs, 4140, eb500000), \ | |
8068 | X(add, 1c00, eb000000), \ | |
8069 | X(adds, 1c00, eb100000), \ | |
0110f2b8 PB |
8070 | X(addi, 0000, f1000000), \ |
8071 | X(addis, 0000, f1100000), \ | |
8072 | X(add_pc,000f, f20f0000), \ | |
8073 | X(add_sp,000d, f10d0000), \ | |
e9f89963 | 8074 | X(adr, 000f, f20f0000), \ |
c19d1205 ZW |
8075 | X(and, 4000, ea000000), \ |
8076 | X(ands, 4000, ea100000), \ | |
8077 | X(asr, 1000, fa40f000), \ | |
8078 | X(asrs, 1000, fa50f000), \ | |
0110f2b8 PB |
8079 | X(b, e000, f000b000), \ |
8080 | X(bcond, d000, f0008000), \ | |
c19d1205 ZW |
8081 | X(bic, 4380, ea200000), \ |
8082 | X(bics, 4380, ea300000), \ | |
8083 | X(cmn, 42c0, eb100f00), \ | |
8084 | X(cmp, 2800, ebb00f00), \ | |
8085 | X(cpsie, b660, f3af8400), \ | |
8086 | X(cpsid, b670, f3af8600), \ | |
8087 | X(cpy, 4600, ea4f0000), \ | |
0110f2b8 | 8088 | X(dec_sp,80dd, f1bd0d00), \ |
c19d1205 ZW |
8089 | X(eor, 4040, ea800000), \ |
8090 | X(eors, 4040, ea900000), \ | |
0110f2b8 | 8091 | X(inc_sp,00dd, f10d0d00), \ |
c19d1205 ZW |
8092 | X(ldmia, c800, e8900000), \ |
8093 | X(ldr, 6800, f8500000), \ | |
8094 | X(ldrb, 7800, f8100000), \ | |
8095 | X(ldrh, 8800, f8300000), \ | |
8096 | X(ldrsb, 5600, f9100000), \ | |
8097 | X(ldrsh, 5e00, f9300000), \ | |
0110f2b8 PB |
8098 | X(ldr_pc,4800, f85f0000), \ |
8099 | X(ldr_pc2,4800, f85f0000), \ | |
8100 | X(ldr_sp,9800, f85d0000), \ | |
c19d1205 ZW |
8101 | X(lsl, 0000, fa00f000), \ |
8102 | X(lsls, 0000, fa10f000), \ | |
8103 | X(lsr, 0800, fa20f000), \ | |
8104 | X(lsrs, 0800, fa30f000), \ | |
8105 | X(mov, 2000, ea4f0000), \ | |
8106 | X(movs, 2000, ea5f0000), \ | |
8107 | X(mul, 4340, fb00f000), \ | |
8108 | X(muls, 4340, ffffffff), /* no 32b muls */ \ | |
8109 | X(mvn, 43c0, ea6f0000), \ | |
8110 | X(mvns, 43c0, ea7f0000), \ | |
8111 | X(neg, 4240, f1c00000), /* rsb #0 */ \ | |
8112 | X(negs, 4240, f1d00000), /* rsbs #0 */ \ | |
8113 | X(orr, 4300, ea400000), \ | |
8114 | X(orrs, 4300, ea500000), \ | |
e9f89963 PB |
8115 | X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \ |
8116 | X(push, b400, e92d0000), /* stmdb sp!,... */ \ | |
c19d1205 ZW |
8117 | X(rev, ba00, fa90f080), \ |
8118 | X(rev16, ba40, fa90f090), \ | |
8119 | X(revsh, bac0, fa90f0b0), \ | |
8120 | X(ror, 41c0, fa60f000), \ | |
8121 | X(rors, 41c0, fa70f000), \ | |
8122 | X(sbc, 4180, eb600000), \ | |
8123 | X(sbcs, 4180, eb700000), \ | |
8124 | X(stmia, c000, e8800000), \ | |
8125 | X(str, 6000, f8400000), \ | |
8126 | X(strb, 7000, f8000000), \ | |
8127 | X(strh, 8000, f8200000), \ | |
0110f2b8 | 8128 | X(str_sp,9000, f84d0000), \ |
c19d1205 ZW |
8129 | X(sub, 1e00, eba00000), \ |
8130 | X(subs, 1e00, ebb00000), \ | |
0110f2b8 PB |
8131 | X(subi, 8000, f1a00000), \ |
8132 | X(subis, 8000, f1b00000), \ | |
c19d1205 ZW |
8133 | X(sxtb, b240, fa4ff080), \ |
8134 | X(sxth, b200, fa0ff080), \ | |
8135 | X(tst, 4200, ea100f00), \ | |
8136 | X(uxtb, b2c0, fa5ff080), \ | |
8137 | X(uxth, b280, fa1ff080), \ | |
8138 | X(nop, bf00, f3af8000), \ | |
8139 | X(yield, bf10, f3af8001), \ | |
8140 | X(wfe, bf20, f3af8002), \ | |
8141 | X(wfi, bf30, f3af8003), \ | |
8142 | X(sev, bf40, f3af9004), /* typo, 8004? */ | |
8143 | ||
8144 | /* To catch errors in encoding functions, the codes are all offset by | |
8145 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
8146 | as 16-bit instructions. */ | |
8147 | #define X(a,b,c) T_MNEM_##a | |
8148 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; | |
8149 | #undef X | |
8150 | ||
8151 | #define X(a,b,c) 0x##b | |
8152 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
8153 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
8154 | #undef X | |
8155 | ||
8156 | #define X(a,b,c) 0x##c | |
8157 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
8158 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) | |
8159 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
8160 | #undef X | |
8161 | #undef T16_32_TAB | |
8162 | ||
8163 | /* Thumb instruction encoders, in alphabetical order. */ | |
8164 | ||
92e90b6e PB |
8165 | /* ADDW or SUBW. */ |
8166 | static void | |
8167 | do_t_add_sub_w (void) | |
8168 | { | |
8169 | int Rd, Rn; | |
8170 | ||
8171 | Rd = inst.operands[0].reg; | |
8172 | Rn = inst.operands[1].reg; | |
8173 | ||
8174 | constraint (Rd == 15, _("PC not allowed as destination")); | |
8175 | inst.instruction |= (Rn << 16) | (Rd << 8); | |
8176 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
8177 | } | |
8178 | ||
c19d1205 ZW |
8179 | /* Parse an add or subtract instruction. We get here with inst.instruction |
8180 | equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ | |
8181 | ||
8182 | static void | |
8183 | do_t_add_sub (void) | |
8184 | { | |
8185 | int Rd, Rs, Rn; | |
8186 | ||
8187 | Rd = inst.operands[0].reg; | |
8188 | Rs = (inst.operands[1].present | |
8189 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
8190 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
8191 | ||
8192 | if (unified_syntax) | |
8193 | { | |
0110f2b8 PB |
8194 | bfd_boolean flags; |
8195 | bfd_boolean narrow; | |
8196 | int opcode; | |
8197 | ||
8198 | flags = (inst.instruction == T_MNEM_adds | |
8199 | || inst.instruction == T_MNEM_subs); | |
8200 | if (flags) | |
8201 | narrow = (current_it_mask == 0); | |
8202 | else | |
8203 | narrow = (current_it_mask != 0); | |
c19d1205 | 8204 | if (!inst.operands[2].isreg) |
b99bd4ef | 8205 | { |
16805f35 PB |
8206 | int add; |
8207 | ||
8208 | add = (inst.instruction == T_MNEM_add | |
8209 | || inst.instruction == T_MNEM_adds); | |
0110f2b8 PB |
8210 | opcode = 0; |
8211 | if (inst.size_req != 4) | |
8212 | { | |
0110f2b8 PB |
8213 | /* Attempt to use a narrow opcode, with relaxation if |
8214 | appropriate. */ | |
8215 | if (Rd == REG_SP && Rs == REG_SP && !flags) | |
8216 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
8217 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
8218 | opcode = T_MNEM_add_sp; | |
8219 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
8220 | opcode = T_MNEM_add_pc; | |
8221 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
8222 | { | |
8223 | if (flags) | |
8224 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
8225 | else | |
8226 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
8227 | } | |
8228 | if (opcode) | |
8229 | { | |
8230 | inst.instruction = THUMB_OP16(opcode); | |
8231 | inst.instruction |= (Rd << 4) | Rs; | |
8232 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
8233 | if (inst.size_req != 2) | |
8234 | inst.relax = opcode; | |
8235 | } | |
8236 | else | |
8237 | constraint (inst.size_req == 2, BAD_HIREG); | |
8238 | } | |
8239 | if (inst.size_req == 4 | |
8240 | || (inst.size_req != 2 && !opcode)) | |
8241 | { | |
16805f35 PB |
8242 | if (Rs == REG_PC) |
8243 | { | |
8244 | /* Always use addw/subw. */ | |
8245 | inst.instruction = add ? 0xf20f0000 : 0xf2af0000; | |
8246 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
8247 | } | |
8248 | else | |
8249 | { | |
8250 | inst.instruction = THUMB_OP32 (inst.instruction); | |
8251 | inst.instruction = (inst.instruction & 0xe1ffffff) | |
8252 | | 0x10000000; | |
8253 | if (flags) | |
8254 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
8255 | else | |
8256 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; | |
8257 | } | |
0110f2b8 PB |
8258 | inst.instruction |= inst.operands[0].reg << 8; |
8259 | inst.instruction |= inst.operands[1].reg << 16; | |
0110f2b8 | 8260 | } |
b99bd4ef | 8261 | } |
c19d1205 ZW |
8262 | else |
8263 | { | |
8264 | Rn = inst.operands[2].reg; | |
8265 | /* See if we can do this with a 16-bit instruction. */ | |
8266 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
8267 | { | |
e27ec89e PB |
8268 | if (Rd > 7 || Rs > 7 || Rn > 7) |
8269 | narrow = FALSE; | |
8270 | ||
8271 | if (narrow) | |
c19d1205 | 8272 | { |
e27ec89e PB |
8273 | inst.instruction = ((inst.instruction == T_MNEM_adds |
8274 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
8275 | ? T_OPCODE_ADD_R3 |
8276 | : T_OPCODE_SUB_R3); | |
8277 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
8278 | return; | |
8279 | } | |
b99bd4ef | 8280 | |
c19d1205 ZW |
8281 | if (inst.instruction == T_MNEM_add) |
8282 | { | |
8283 | if (Rd == Rs) | |
8284 | { | |
8285 | inst.instruction = T_OPCODE_ADD_HI; | |
8286 | inst.instruction |= (Rd & 8) << 4; | |
8287 | inst.instruction |= (Rd & 7); | |
8288 | inst.instruction |= Rn << 3; | |
8289 | return; | |
8290 | } | |
8291 | /* ... because addition is commutative! */ | |
8292 | else if (Rd == Rn) | |
8293 | { | |
8294 | inst.instruction = T_OPCODE_ADD_HI; | |
8295 | inst.instruction |= (Rd & 8) << 4; | |
8296 | inst.instruction |= (Rd & 7); | |
8297 | inst.instruction |= Rs << 3; | |
8298 | return; | |
8299 | } | |
8300 | } | |
8301 | } | |
8302 | /* If we get here, it can't be done in 16 bits. */ | |
8303 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
8304 | _("shift must be constant")); | |
8305 | inst.instruction = THUMB_OP32 (inst.instruction); | |
8306 | inst.instruction |= Rd << 8; | |
8307 | inst.instruction |= Rs << 16; | |
8308 | encode_thumb32_shifted_operand (2); | |
8309 | } | |
8310 | } | |
8311 | else | |
8312 | { | |
8313 | constraint (inst.instruction == T_MNEM_adds | |
8314 | || inst.instruction == T_MNEM_subs, | |
8315 | BAD_THUMB32); | |
b99bd4ef | 8316 | |
c19d1205 | 8317 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 8318 | { |
c19d1205 ZW |
8319 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
8320 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
8321 | BAD_HIREG); | |
8322 | ||
8323 | inst.instruction = (inst.instruction == T_MNEM_add | |
8324 | ? 0x0000 : 0x8000); | |
8325 | inst.instruction |= (Rd << 4) | Rs; | |
8326 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
b99bd4ef NC |
8327 | return; |
8328 | } | |
8329 | ||
c19d1205 ZW |
8330 | Rn = inst.operands[2].reg; |
8331 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 8332 | |
c19d1205 ZW |
8333 | /* We now have Rd, Rs, and Rn set to registers. */ |
8334 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 8335 | { |
c19d1205 ZW |
8336 | /* Can't do this for SUB. */ |
8337 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
8338 | inst.instruction = T_OPCODE_ADD_HI; | |
8339 | inst.instruction |= (Rd & 8) << 4; | |
8340 | inst.instruction |= (Rd & 7); | |
8341 | if (Rs == Rd) | |
8342 | inst.instruction |= Rn << 3; | |
8343 | else if (Rn == Rd) | |
8344 | inst.instruction |= Rs << 3; | |
8345 | else | |
8346 | constraint (1, _("dest must overlap one source register")); | |
8347 | } | |
8348 | else | |
8349 | { | |
8350 | inst.instruction = (inst.instruction == T_MNEM_add | |
8351 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
8352 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 8353 | } |
b99bd4ef | 8354 | } |
b99bd4ef NC |
8355 | } |
8356 | ||
c19d1205 ZW |
8357 | static void |
8358 | do_t_adr (void) | |
8359 | { | |
0110f2b8 PB |
8360 | if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7) |
8361 | { | |
8362 | /* Defer to section relaxation. */ | |
8363 | inst.relax = inst.instruction; | |
8364 | inst.instruction = THUMB_OP16 (inst.instruction); | |
8365 | inst.instruction |= inst.operands[0].reg << 4; | |
8366 | } | |
8367 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 8368 | { |
0110f2b8 | 8369 | /* Generate a 32-bit opcode. */ |
e9f89963 PB |
8370 | inst.instruction = THUMB_OP32 (inst.instruction); |
8371 | inst.instruction |= inst.operands[0].reg << 8; | |
8372 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; | |
8373 | inst.reloc.pc_rel = 1; | |
8374 | } | |
8375 | else | |
8376 | { | |
0110f2b8 | 8377 | /* Generate a 16-bit opcode. */ |
e9f89963 PB |
8378 | inst.instruction = THUMB_OP16 (inst.instruction); |
8379 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
8380 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
8381 | inst.reloc.pc_rel = 1; | |
b99bd4ef | 8382 | |
e9f89963 PB |
8383 | inst.instruction |= inst.operands[0].reg << 4; |
8384 | } | |
c19d1205 | 8385 | } |
b99bd4ef | 8386 | |
c19d1205 ZW |
8387 | /* Arithmetic instructions for which there is just one 16-bit |
8388 | instruction encoding, and it allows only two low registers. | |
8389 | For maximal compatibility with ARM syntax, we allow three register | |
8390 | operands even when Thumb-32 instructions are not available, as long | |
8391 | as the first two are identical. For instance, both "sbc r0,r1" and | |
8392 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 8393 | static void |
c19d1205 | 8394 | do_t_arit3 (void) |
b99bd4ef | 8395 | { |
c19d1205 | 8396 | int Rd, Rs, Rn; |
b99bd4ef | 8397 | |
c19d1205 ZW |
8398 | Rd = inst.operands[0].reg; |
8399 | Rs = (inst.operands[1].present | |
8400 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
8401 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
8402 | Rn = inst.operands[2].reg; | |
b99bd4ef | 8403 | |
c19d1205 | 8404 | if (unified_syntax) |
b99bd4ef | 8405 | { |
c19d1205 ZW |
8406 | if (!inst.operands[2].isreg) |
8407 | { | |
8408 | /* For an immediate, we always generate a 32-bit opcode; | |
8409 | section relaxation will shrink it later if possible. */ | |
8410 | inst.instruction = THUMB_OP32 (inst.instruction); | |
8411 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
8412 | inst.instruction |= Rd << 8; | |
8413 | inst.instruction |= Rs << 16; | |
8414 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
8415 | } | |
8416 | else | |
8417 | { | |
e27ec89e PB |
8418 | bfd_boolean narrow; |
8419 | ||
c19d1205 | 8420 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e PB |
8421 | if (THUMB_SETS_FLAGS (inst.instruction)) |
8422 | narrow = current_it_mask == 0; | |
8423 | else | |
8424 | narrow = current_it_mask != 0; | |
8425 | ||
8426 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
8427 | narrow = FALSE; | |
8428 | if (inst.operands[2].shifted) | |
8429 | narrow = FALSE; | |
8430 | if (inst.size_req == 4) | |
8431 | narrow = FALSE; | |
8432 | ||
8433 | if (narrow | |
c19d1205 ZW |
8434 | && Rd == Rs) |
8435 | { | |
8436 | inst.instruction = THUMB_OP16 (inst.instruction); | |
8437 | inst.instruction |= Rd; | |
8438 | inst.instruction |= Rn << 3; | |
8439 | return; | |
8440 | } | |
b99bd4ef | 8441 | |
c19d1205 ZW |
8442 | /* If we get here, it can't be done in 16 bits. */ |
8443 | constraint (inst.operands[2].shifted | |
8444 | && inst.operands[2].immisreg, | |
8445 | _("shift must be constant")); | |
8446 | inst.instruction = THUMB_OP32 (inst.instruction); | |
8447 | inst.instruction |= Rd << 8; | |
8448 | inst.instruction |= Rs << 16; | |
8449 | encode_thumb32_shifted_operand (2); | |
8450 | } | |
a737bd4d | 8451 | } |
c19d1205 | 8452 | else |
b99bd4ef | 8453 | { |
c19d1205 ZW |
8454 | /* On its face this is a lie - the instruction does set the |
8455 | flags. However, the only supported mnemonic in this mode | |
8456 | says it doesn't. */ | |
8457 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 8458 | |
c19d1205 ZW |
8459 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
8460 | _("unshifted register required")); | |
8461 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
8462 | constraint (Rd != Rs, | |
8463 | _("dest and source1 must be the same register")); | |
a737bd4d | 8464 | |
c19d1205 ZW |
8465 | inst.instruction = THUMB_OP16 (inst.instruction); |
8466 | inst.instruction |= Rd; | |
8467 | inst.instruction |= Rn << 3; | |
b99bd4ef | 8468 | } |
a737bd4d | 8469 | } |
b99bd4ef | 8470 | |
c19d1205 ZW |
8471 | /* Similarly, but for instructions where the arithmetic operation is |
8472 | commutative, so we can allow either of them to be different from | |
8473 | the destination operand in a 16-bit instruction. For instance, all | |
8474 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
8475 | accepted. */ | |
8476 | static void | |
8477 | do_t_arit3c (void) | |
a737bd4d | 8478 | { |
c19d1205 | 8479 | int Rd, Rs, Rn; |
b99bd4ef | 8480 | |
c19d1205 ZW |
8481 | Rd = inst.operands[0].reg; |
8482 | Rs = (inst.operands[1].present | |
8483 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
8484 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
8485 | Rn = inst.operands[2].reg; | |
a737bd4d | 8486 | |
c19d1205 | 8487 | if (unified_syntax) |
a737bd4d | 8488 | { |
c19d1205 | 8489 | if (!inst.operands[2].isreg) |
b99bd4ef | 8490 | { |
c19d1205 ZW |
8491 | /* For an immediate, we always generate a 32-bit opcode; |
8492 | section relaxation will shrink it later if possible. */ | |
8493 | inst.instruction = THUMB_OP32 (inst.instruction); | |
8494 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
8495 | inst.instruction |= Rd << 8; | |
8496 | inst.instruction |= Rs << 16; | |
8497 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 8498 | } |
c19d1205 | 8499 | else |
a737bd4d | 8500 | { |
e27ec89e PB |
8501 | bfd_boolean narrow; |
8502 | ||
c19d1205 | 8503 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e PB |
8504 | if (THUMB_SETS_FLAGS (inst.instruction)) |
8505 | narrow = current_it_mask == 0; | |
8506 | else | |
8507 | narrow = current_it_mask != 0; | |
8508 | ||
8509 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
8510 | narrow = FALSE; | |
8511 | if (inst.operands[2].shifted) | |
8512 | narrow = FALSE; | |
8513 | if (inst.size_req == 4) | |
8514 | narrow = FALSE; | |
8515 | ||
8516 | if (narrow) | |
a737bd4d | 8517 | { |
c19d1205 | 8518 | if (Rd == Rs) |
a737bd4d | 8519 | { |
c19d1205 ZW |
8520 | inst.instruction = THUMB_OP16 (inst.instruction); |
8521 | inst.instruction |= Rd; | |
8522 | inst.instruction |= Rn << 3; | |
8523 | return; | |
a737bd4d | 8524 | } |
c19d1205 | 8525 | if (Rd == Rn) |
a737bd4d | 8526 | { |
c19d1205 ZW |
8527 | inst.instruction = THUMB_OP16 (inst.instruction); |
8528 | inst.instruction |= Rd; | |
8529 | inst.instruction |= Rs << 3; | |
8530 | return; | |
a737bd4d NC |
8531 | } |
8532 | } | |
c19d1205 ZW |
8533 | |
8534 | /* If we get here, it can't be done in 16 bits. */ | |
8535 | constraint (inst.operands[2].shifted | |
8536 | && inst.operands[2].immisreg, | |
8537 | _("shift must be constant")); | |
8538 | inst.instruction = THUMB_OP32 (inst.instruction); | |
8539 | inst.instruction |= Rd << 8; | |
8540 | inst.instruction |= Rs << 16; | |
8541 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 8542 | } |
b99bd4ef | 8543 | } |
c19d1205 ZW |
8544 | else |
8545 | { | |
8546 | /* On its face this is a lie - the instruction does set the | |
8547 | flags. However, the only supported mnemonic in this mode | |
8548 | says it doesn't. */ | |
8549 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 8550 | |
c19d1205 ZW |
8551 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
8552 | _("unshifted register required")); | |
8553 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
8554 | ||
8555 | inst.instruction = THUMB_OP16 (inst.instruction); | |
8556 | inst.instruction |= Rd; | |
8557 | ||
8558 | if (Rd == Rs) | |
8559 | inst.instruction |= Rn << 3; | |
8560 | else if (Rd == Rn) | |
8561 | inst.instruction |= Rs << 3; | |
8562 | else | |
8563 | constraint (1, _("dest must overlap one source register")); | |
8564 | } | |
a737bd4d NC |
8565 | } |
8566 | ||
62b3e311 PB |
8567 | static void |
8568 | do_t_barrier (void) | |
8569 | { | |
8570 | if (inst.operands[0].present) | |
8571 | { | |
8572 | constraint ((inst.instruction & 0xf0) != 0x40 | |
8573 | && inst.operands[0].imm != 0xf, | |
8574 | "bad barrier type"); | |
8575 | inst.instruction |= inst.operands[0].imm; | |
8576 | } | |
8577 | else | |
8578 | inst.instruction |= 0xf; | |
8579 | } | |
8580 | ||
c19d1205 ZW |
8581 | static void |
8582 | do_t_bfc (void) | |
a737bd4d | 8583 | { |
c19d1205 ZW |
8584 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
8585 | constraint (msb > 32, _("bit-field extends past end of register")); | |
8586 | /* The instruction encoding stores the LSB and MSB, | |
8587 | not the LSB and width. */ | |
8588 | inst.instruction |= inst.operands[0].reg << 8; | |
8589 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; | |
8590 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
8591 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
8592 | } |
8593 | ||
c19d1205 ZW |
8594 | static void |
8595 | do_t_bfi (void) | |
b99bd4ef | 8596 | { |
c19d1205 | 8597 | unsigned int msb; |
b99bd4ef | 8598 | |
c19d1205 ZW |
8599 | /* #0 in second position is alternative syntax for bfc, which is |
8600 | the same instruction but with REG_PC in the Rm field. */ | |
8601 | if (!inst.operands[1].isreg) | |
8602 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 8603 | |
c19d1205 ZW |
8604 | msb = inst.operands[2].imm + inst.operands[3].imm; |
8605 | constraint (msb > 32, _("bit-field extends past end of register")); | |
8606 | /* The instruction encoding stores the LSB and MSB, | |
8607 | not the LSB and width. */ | |
8608 | inst.instruction |= inst.operands[0].reg << 8; | |
8609 | inst.instruction |= inst.operands[1].reg << 16; | |
8610 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; | |
8611 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
8612 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
8613 | } |
8614 | ||
c19d1205 ZW |
8615 | static void |
8616 | do_t_bfx (void) | |
b99bd4ef | 8617 | { |
c19d1205 ZW |
8618 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
8619 | _("bit-field extends past end of register")); | |
8620 | inst.instruction |= inst.operands[0].reg << 8; | |
8621 | inst.instruction |= inst.operands[1].reg << 16; | |
8622 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; | |
8623 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
8624 | inst.instruction |= inst.operands[3].imm - 1; | |
8625 | } | |
b99bd4ef | 8626 | |
c19d1205 ZW |
8627 | /* ARM V5 Thumb BLX (argument parse) |
8628 | BLX <target_addr> which is BLX(1) | |
8629 | BLX <Rm> which is BLX(2) | |
8630 | Unfortunately, there are two different opcodes for this mnemonic. | |
8631 | So, the insns[].value is not used, and the code here zaps values | |
8632 | into inst.instruction. | |
b99bd4ef | 8633 | |
c19d1205 ZW |
8634 | ??? How to take advantage of the additional two bits of displacement |
8635 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 8636 | |
c19d1205 ZW |
8637 | static void |
8638 | do_t_blx (void) | |
8639 | { | |
dfa9f0d5 | 8640 | constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); |
c19d1205 ZW |
8641 | if (inst.operands[0].isreg) |
8642 | /* We have a register, so this is BLX(2). */ | |
8643 | inst.instruction |= inst.operands[0].reg << 3; | |
b99bd4ef NC |
8644 | else |
8645 | { | |
c19d1205 | 8646 | /* No register. This must be BLX(1). */ |
2fc8bdac | 8647 | inst.instruction = 0xf000e800; |
39b41c9c PB |
8648 | #ifdef OBJ_ELF |
8649 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
8650 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
8651 | else | |
8652 | #endif | |
8653 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; | |
c19d1205 | 8654 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
8655 | } |
8656 | } | |
8657 | ||
c19d1205 ZW |
8658 | static void |
8659 | do_t_branch (void) | |
b99bd4ef | 8660 | { |
0110f2b8 | 8661 | int opcode; |
dfa9f0d5 PB |
8662 | int cond; |
8663 | ||
8664 | if (current_it_mask) | |
8665 | { | |
8666 | /* Conditional branches inside IT blocks are encoded as unconditional | |
8667 | branches. */ | |
8668 | cond = COND_ALWAYS; | |
8669 | /* A branch must be the last instruction in an IT block. */ | |
8670 | constraint (current_it_mask != 0x10, BAD_BRANCH); | |
8671 | } | |
8672 | else | |
8673 | cond = inst.cond; | |
8674 | ||
8675 | if (cond != COND_ALWAYS) | |
0110f2b8 PB |
8676 | opcode = T_MNEM_bcond; |
8677 | else | |
8678 | opcode = inst.instruction; | |
8679 | ||
8680 | if (unified_syntax && inst.size_req == 4) | |
c19d1205 | 8681 | { |
0110f2b8 | 8682 | inst.instruction = THUMB_OP32(opcode); |
dfa9f0d5 | 8683 | if (cond == COND_ALWAYS) |
0110f2b8 | 8684 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
8685 | else |
8686 | { | |
dfa9f0d5 PB |
8687 | assert (cond != 0xF); |
8688 | inst.instruction |= cond << 22; | |
c19d1205 ZW |
8689 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20; |
8690 | } | |
8691 | } | |
b99bd4ef NC |
8692 | else |
8693 | { | |
0110f2b8 | 8694 | inst.instruction = THUMB_OP16(opcode); |
dfa9f0d5 | 8695 | if (cond == COND_ALWAYS) |
c19d1205 ZW |
8696 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12; |
8697 | else | |
b99bd4ef | 8698 | { |
dfa9f0d5 | 8699 | inst.instruction |= cond << 8; |
c19d1205 | 8700 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 8701 | } |
0110f2b8 PB |
8702 | /* Allow section relaxation. */ |
8703 | if (unified_syntax && inst.size_req != 2) | |
8704 | inst.relax = opcode; | |
b99bd4ef | 8705 | } |
c19d1205 ZW |
8706 | |
8707 | inst.reloc.pc_rel = 1; | |
b99bd4ef NC |
8708 | } |
8709 | ||
8710 | static void | |
c19d1205 | 8711 | do_t_bkpt (void) |
b99bd4ef | 8712 | { |
dfa9f0d5 PB |
8713 | constraint (inst.cond != COND_ALWAYS, |
8714 | _("instruction is always unconditional")); | |
c19d1205 | 8715 | if (inst.operands[0].present) |
b99bd4ef | 8716 | { |
c19d1205 ZW |
8717 | constraint (inst.operands[0].imm > 255, |
8718 | _("immediate value out of range")); | |
8719 | inst.instruction |= inst.operands[0].imm; | |
b99bd4ef | 8720 | } |
b99bd4ef NC |
8721 | } |
8722 | ||
8723 | static void | |
c19d1205 | 8724 | do_t_branch23 (void) |
b99bd4ef | 8725 | { |
dfa9f0d5 | 8726 | constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); |
c19d1205 | 8727 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; |
90e4755a RE |
8728 | inst.reloc.pc_rel = 1; |
8729 | ||
c19d1205 ZW |
8730 | /* If the destination of the branch is a defined symbol which does not have |
8731 | the THUMB_FUNC attribute, then we must be calling a function which has | |
8732 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
8733 | function and change the branch to refer to that function instead. */ | |
8734 | if ( inst.reloc.exp.X_op == O_symbol | |
8735 | && inst.reloc.exp.X_add_symbol != NULL | |
8736 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
8737 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
8738 | inst.reloc.exp.X_add_symbol = | |
8739 | find_real_start (inst.reloc.exp.X_add_symbol); | |
90e4755a RE |
8740 | } |
8741 | ||
8742 | static void | |
c19d1205 | 8743 | do_t_bx (void) |
90e4755a | 8744 | { |
dfa9f0d5 | 8745 | constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); |
c19d1205 ZW |
8746 | inst.instruction |= inst.operands[0].reg << 3; |
8747 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
8748 | should cause the alignment to be checked once it is known. This is | |
8749 | because BX PC only works if the instruction is word aligned. */ | |
8750 | } | |
90e4755a | 8751 | |
c19d1205 ZW |
8752 | static void |
8753 | do_t_bxj (void) | |
8754 | { | |
dfa9f0d5 | 8755 | constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); |
c19d1205 ZW |
8756 | if (inst.operands[0].reg == REG_PC) |
8757 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
90e4755a | 8758 | |
c19d1205 | 8759 | inst.instruction |= inst.operands[0].reg << 16; |
90e4755a RE |
8760 | } |
8761 | ||
8762 | static void | |
c19d1205 | 8763 | do_t_clz (void) |
90e4755a | 8764 | { |
c19d1205 ZW |
8765 | inst.instruction |= inst.operands[0].reg << 8; |
8766 | inst.instruction |= inst.operands[1].reg << 16; | |
8767 | inst.instruction |= inst.operands[1].reg; | |
8768 | } | |
90e4755a | 8769 | |
dfa9f0d5 PB |
8770 | static void |
8771 | do_t_cps (void) | |
8772 | { | |
8773 | constraint (current_it_mask, BAD_NOT_IT); | |
8774 | inst.instruction |= inst.operands[0].imm; | |
8775 | } | |
8776 | ||
c19d1205 ZW |
8777 | static void |
8778 | do_t_cpsi (void) | |
8779 | { | |
dfa9f0d5 | 8780 | constraint (current_it_mask, BAD_NOT_IT); |
c19d1205 | 8781 | if (unified_syntax |
62b3e311 PB |
8782 | && (inst.operands[1].present || inst.size_req == 4) |
8783 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) | |
90e4755a | 8784 | { |
c19d1205 ZW |
8785 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
8786 | inst.instruction = 0xf3af8000; | |
8787 | inst.instruction |= imod << 9; | |
8788 | inst.instruction |= inst.operands[0].imm << 5; | |
8789 | if (inst.operands[1].present) | |
8790 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 8791 | } |
c19d1205 | 8792 | else |
90e4755a | 8793 | { |
62b3e311 PB |
8794 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) |
8795 | && (inst.operands[0].imm & 4), | |
8796 | _("selected processor does not support 'A' form " | |
8797 | "of this instruction")); | |
8798 | constraint (inst.operands[1].present || inst.size_req == 4, | |
c19d1205 ZW |
8799 | _("Thumb does not support the 2-argument " |
8800 | "form of this instruction")); | |
8801 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 8802 | } |
90e4755a RE |
8803 | } |
8804 | ||
c19d1205 ZW |
8805 | /* THUMB CPY instruction (argument parse). */ |
8806 | ||
90e4755a | 8807 | static void |
c19d1205 | 8808 | do_t_cpy (void) |
90e4755a | 8809 | { |
c19d1205 | 8810 | if (inst.size_req == 4) |
90e4755a | 8811 | { |
c19d1205 ZW |
8812 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
8813 | inst.instruction |= inst.operands[0].reg << 8; | |
8814 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 8815 | } |
c19d1205 | 8816 | else |
90e4755a | 8817 | { |
c19d1205 ZW |
8818 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
8819 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
8820 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 8821 | } |
90e4755a RE |
8822 | } |
8823 | ||
90e4755a | 8824 | static void |
c19d1205 | 8825 | do_t_czb (void) |
90e4755a | 8826 | { |
dfa9f0d5 | 8827 | constraint (current_it_mask, BAD_NOT_IT); |
c19d1205 ZW |
8828 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
8829 | inst.instruction |= inst.operands[0].reg; | |
8830 | inst.reloc.pc_rel = 1; | |
8831 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
8832 | } | |
90e4755a | 8833 | |
62b3e311 PB |
8834 | static void |
8835 | do_t_dbg (void) | |
8836 | { | |
8837 | inst.instruction |= inst.operands[0].imm; | |
8838 | } | |
8839 | ||
8840 | static void | |
8841 | do_t_div (void) | |
8842 | { | |
8843 | if (!inst.operands[1].present) | |
8844 | inst.operands[1].reg = inst.operands[0].reg; | |
8845 | inst.instruction |= inst.operands[0].reg << 8; | |
8846 | inst.instruction |= inst.operands[1].reg << 16; | |
8847 | inst.instruction |= inst.operands[2].reg; | |
8848 | } | |
8849 | ||
c19d1205 ZW |
8850 | static void |
8851 | do_t_hint (void) | |
8852 | { | |
8853 | if (unified_syntax && inst.size_req == 4) | |
8854 | inst.instruction = THUMB_OP32 (inst.instruction); | |
8855 | else | |
8856 | inst.instruction = THUMB_OP16 (inst.instruction); | |
8857 | } | |
90e4755a | 8858 | |
c19d1205 ZW |
8859 | static void |
8860 | do_t_it (void) | |
8861 | { | |
8862 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e | 8863 | |
dfa9f0d5 | 8864 | constraint (current_it_mask, BAD_NOT_IT); |
e27ec89e PB |
8865 | current_it_mask = (inst.instruction & 0xf) | 0x10; |
8866 | current_cc = cond; | |
8867 | ||
8868 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 8869 | if ((cond & 0x1) == 0x0) |
90e4755a | 8870 | { |
c19d1205 | 8871 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 8872 | |
c19d1205 ZW |
8873 | if ((mask & 0x7) == 0) |
8874 | /* no conversion needed */; | |
8875 | else if ((mask & 0x3) == 0) | |
e27ec89e PB |
8876 | mask ^= 0x8; |
8877 | else if ((mask & 0x1) == 0) | |
8878 | mask ^= 0xC; | |
c19d1205 | 8879 | else |
e27ec89e | 8880 | mask ^= 0xE; |
90e4755a | 8881 | |
e27ec89e PB |
8882 | inst.instruction &= 0xfff0; |
8883 | inst.instruction |= mask; | |
c19d1205 | 8884 | } |
90e4755a | 8885 | |
c19d1205 ZW |
8886 | inst.instruction |= cond << 4; |
8887 | } | |
90e4755a | 8888 | |
c19d1205 ZW |
8889 | static void |
8890 | do_t_ldmstm (void) | |
8891 | { | |
8892 | /* This really doesn't seem worth it. */ | |
8893 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
8894 | _("expression too complex")); | |
8895 | constraint (inst.operands[1].writeback, | |
8896 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 8897 | |
c19d1205 ZW |
8898 | if (unified_syntax) |
8899 | { | |
8900 | /* See if we can use a 16-bit instruction. */ | |
8901 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
8902 | && inst.size_req != 4 | |
8903 | && inst.operands[0].reg <= 7 | |
8904 | && !(inst.operands[1].imm & ~0xff) | |
8905 | && (inst.instruction == T_MNEM_stmia | |
8906 | ? inst.operands[0].writeback | |
8907 | : (inst.operands[0].writeback | |
8908 | == !(inst.operands[1].imm & (1 << inst.operands[0].reg))))) | |
90e4755a | 8909 | { |
c19d1205 ZW |
8910 | if (inst.instruction == T_MNEM_stmia |
8911 | && (inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
8912 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
8913 | as_warn (_("value stored for r%d is UNPREDICTABLE"), | |
8914 | inst.operands[0].reg); | |
90e4755a | 8915 | |
c19d1205 ZW |
8916 | inst.instruction = THUMB_OP16 (inst.instruction); |
8917 | inst.instruction |= inst.operands[0].reg << 8; | |
8918 | inst.instruction |= inst.operands[1].imm; | |
8919 | } | |
8920 | else | |
8921 | { | |
8922 | if (inst.operands[1].imm & (1 << 13)) | |
8923 | as_warn (_("SP should not be in register list")); | |
8924 | if (inst.instruction == T_MNEM_stmia) | |
90e4755a | 8925 | { |
c19d1205 ZW |
8926 | if (inst.operands[1].imm & (1 << 15)) |
8927 | as_warn (_("PC should not be in register list")); | |
8928 | if (inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
8929 | as_warn (_("value stored for r%d is UNPREDICTABLE"), | |
8930 | inst.operands[0].reg); | |
90e4755a RE |
8931 | } |
8932 | else | |
8933 | { | |
c19d1205 ZW |
8934 | if (inst.operands[1].imm & (1 << 14) |
8935 | && inst.operands[1].imm & (1 << 15)) | |
8936 | as_warn (_("LR and PC should not both be in register list")); | |
8937 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
8938 | && inst.operands[0].writeback) | |
8939 | as_warn (_("base register should not be in register list " | |
8940 | "when written back")); | |
90e4755a | 8941 | } |
c19d1205 ZW |
8942 | if (inst.instruction < 0xffff) |
8943 | inst.instruction = THUMB_OP32 (inst.instruction); | |
8944 | inst.instruction |= inst.operands[0].reg << 16; | |
8945 | inst.instruction |= inst.operands[1].imm; | |
8946 | if (inst.operands[0].writeback) | |
8947 | inst.instruction |= WRITE_BACK; | |
90e4755a RE |
8948 | } |
8949 | } | |
c19d1205 | 8950 | else |
90e4755a | 8951 | { |
c19d1205 ZW |
8952 | constraint (inst.operands[0].reg > 7 |
8953 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
8954 | if (inst.instruction == T_MNEM_stmia) | |
f03698e6 | 8955 | { |
c19d1205 ZW |
8956 | if (!inst.operands[0].writeback) |
8957 | as_warn (_("this instruction will write back the base register")); | |
8958 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
8959 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
8960 | as_warn (_("value stored for r%d is UNPREDICTABLE"), | |
8961 | inst.operands[0].reg); | |
f03698e6 | 8962 | } |
c19d1205 | 8963 | else |
90e4755a | 8964 | { |
c19d1205 ZW |
8965 | if (!inst.operands[0].writeback |
8966 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
8967 | as_warn (_("this instruction will write back the base register")); | |
8968 | else if (inst.operands[0].writeback | |
8969 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
8970 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
8971 | } |
8972 | ||
c19d1205 ZW |
8973 | inst.instruction = THUMB_OP16 (inst.instruction); |
8974 | inst.instruction |= inst.operands[0].reg << 8; | |
8975 | inst.instruction |= inst.operands[1].imm; | |
8976 | } | |
8977 | } | |
e28cd48c | 8978 | |
c19d1205 ZW |
8979 | static void |
8980 | do_t_ldrex (void) | |
8981 | { | |
8982 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
8983 | || inst.operands[1].postind || inst.operands[1].writeback | |
8984 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
8985 | || inst.operands[1].negative, | |
01cfc07f | 8986 | BAD_ADDR_MODE); |
e28cd48c | 8987 | |
c19d1205 ZW |
8988 | inst.instruction |= inst.operands[0].reg << 12; |
8989 | inst.instruction |= inst.operands[1].reg << 16; | |
8990 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
8991 | } | |
e28cd48c | 8992 | |
c19d1205 ZW |
8993 | static void |
8994 | do_t_ldrexd (void) | |
8995 | { | |
8996 | if (!inst.operands[1].present) | |
1cac9012 | 8997 | { |
c19d1205 ZW |
8998 | constraint (inst.operands[0].reg == REG_LR, |
8999 | _("r14 not allowed as first register " | |
9000 | "when second register is omitted")); | |
9001 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 9002 | } |
c19d1205 ZW |
9003 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
9004 | BAD_OVERLAP); | |
b99bd4ef | 9005 | |
c19d1205 ZW |
9006 | inst.instruction |= inst.operands[0].reg << 12; |
9007 | inst.instruction |= inst.operands[1].reg << 8; | |
9008 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
9009 | } |
9010 | ||
9011 | static void | |
c19d1205 | 9012 | do_t_ldst (void) |
b99bd4ef | 9013 | { |
0110f2b8 PB |
9014 | unsigned long opcode; |
9015 | int Rn; | |
9016 | ||
9017 | opcode = inst.instruction; | |
c19d1205 | 9018 | if (unified_syntax) |
b99bd4ef | 9019 | { |
53365c0d PB |
9020 | if (!inst.operands[1].isreg) |
9021 | { | |
9022 | if (opcode <= 0xffff) | |
9023 | inst.instruction = THUMB_OP32 (opcode); | |
9024 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
9025 | return; | |
9026 | } | |
0110f2b8 PB |
9027 | if (inst.operands[1].isreg |
9028 | && !inst.operands[1].writeback | |
c19d1205 ZW |
9029 | && !inst.operands[1].shifted && !inst.operands[1].postind |
9030 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
9031 | && opcode <= 0xffff |
9032 | && inst.size_req != 4) | |
c19d1205 | 9033 | { |
0110f2b8 PB |
9034 | /* Insn may have a 16-bit form. */ |
9035 | Rn = inst.operands[1].reg; | |
9036 | if (inst.operands[1].immisreg) | |
9037 | { | |
9038 | inst.instruction = THUMB_OP16 (opcode); | |
9039 | /* [Rn, Ri] */ | |
9040 | if (Rn <= 7 && inst.operands[1].imm <= 7) | |
9041 | goto op16; | |
9042 | } | |
9043 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
9044 | && opcode != T_MNEM_ldrsb) | |
9045 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
9046 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
9047 | { | |
9048 | /* [Rn, #const] */ | |
9049 | if (Rn > 7) | |
9050 | { | |
9051 | if (Rn == REG_PC) | |
9052 | { | |
9053 | if (inst.reloc.pc_rel) | |
9054 | opcode = T_MNEM_ldr_pc2; | |
9055 | else | |
9056 | opcode = T_MNEM_ldr_pc; | |
9057 | } | |
9058 | else | |
9059 | { | |
9060 | if (opcode == T_MNEM_ldr) | |
9061 | opcode = T_MNEM_ldr_sp; | |
9062 | else | |
9063 | opcode = T_MNEM_str_sp; | |
9064 | } | |
9065 | inst.instruction = inst.operands[0].reg << 8; | |
9066 | } | |
9067 | else | |
9068 | { | |
9069 | inst.instruction = inst.operands[0].reg; | |
9070 | inst.instruction |= inst.operands[1].reg << 3; | |
9071 | } | |
9072 | inst.instruction |= THUMB_OP16 (opcode); | |
9073 | if (inst.size_req == 2) | |
9074 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
9075 | else | |
9076 | inst.relax = opcode; | |
9077 | return; | |
9078 | } | |
c19d1205 | 9079 | } |
0110f2b8 PB |
9080 | /* Definitely a 32-bit variant. */ |
9081 | inst.instruction = THUMB_OP32 (opcode); | |
c19d1205 ZW |
9082 | inst.instruction |= inst.operands[0].reg << 12; |
9083 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
b99bd4ef NC |
9084 | return; |
9085 | } | |
9086 | ||
c19d1205 ZW |
9087 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
9088 | ||
9089 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 9090 | { |
c19d1205 ZW |
9091 | /* Only [Rn,Rm] is acceptable. */ |
9092 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
9093 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
9094 | || inst.operands[1].postind || inst.operands[1].shifted | |
9095 | || inst.operands[1].negative, | |
9096 | _("Thumb does not support this addressing mode")); | |
9097 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9098 | goto op16; | |
b99bd4ef | 9099 | } |
c19d1205 ZW |
9100 | |
9101 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9102 | if (!inst.operands[1].isreg) | |
9103 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
9104 | return; | |
b99bd4ef | 9105 | |
c19d1205 ZW |
9106 | constraint (!inst.operands[1].preind |
9107 | || inst.operands[1].shifted | |
9108 | || inst.operands[1].writeback, | |
9109 | _("Thumb does not support this addressing mode")); | |
9110 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 9111 | { |
c19d1205 ZW |
9112 | constraint (inst.instruction & 0x0600, |
9113 | _("byte or halfword not valid for base register")); | |
9114 | constraint (inst.operands[1].reg == REG_PC | |
9115 | && !(inst.instruction & THUMB_LOAD_BIT), | |
9116 | _("r15 based store not allowed")); | |
9117 | constraint (inst.operands[1].immisreg, | |
9118 | _("invalid base register for register offset")); | |
b99bd4ef | 9119 | |
c19d1205 ZW |
9120 | if (inst.operands[1].reg == REG_PC) |
9121 | inst.instruction = T_OPCODE_LDR_PC; | |
9122 | else if (inst.instruction & THUMB_LOAD_BIT) | |
9123 | inst.instruction = T_OPCODE_LDR_SP; | |
9124 | else | |
9125 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 9126 | |
c19d1205 ZW |
9127 | inst.instruction |= inst.operands[0].reg << 8; |
9128 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
9129 | return; | |
9130 | } | |
90e4755a | 9131 | |
c19d1205 ZW |
9132 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
9133 | if (!inst.operands[1].immisreg) | |
9134 | { | |
9135 | /* Immediate offset. */ | |
9136 | inst.instruction |= inst.operands[0].reg; | |
9137 | inst.instruction |= inst.operands[1].reg << 3; | |
9138 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
9139 | return; | |
9140 | } | |
90e4755a | 9141 | |
c19d1205 ZW |
9142 | /* Register offset. */ |
9143 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
9144 | constraint (inst.operands[1].negative, | |
9145 | _("Thumb does not support this addressing mode")); | |
90e4755a | 9146 | |
c19d1205 ZW |
9147 | op16: |
9148 | switch (inst.instruction) | |
9149 | { | |
9150 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
9151 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
9152 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
9153 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
9154 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
9155 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
9156 | case 0x5600 /* ldrsb */: | |
9157 | case 0x5e00 /* ldrsh */: break; | |
9158 | default: abort (); | |
9159 | } | |
90e4755a | 9160 | |
c19d1205 ZW |
9161 | inst.instruction |= inst.operands[0].reg; |
9162 | inst.instruction |= inst.operands[1].reg << 3; | |
9163 | inst.instruction |= inst.operands[1].imm << 6; | |
9164 | } | |
90e4755a | 9165 | |
c19d1205 ZW |
9166 | static void |
9167 | do_t_ldstd (void) | |
9168 | { | |
9169 | if (!inst.operands[1].present) | |
b99bd4ef | 9170 | { |
c19d1205 ZW |
9171 | inst.operands[1].reg = inst.operands[0].reg + 1; |
9172 | constraint (inst.operands[0].reg == REG_LR, | |
9173 | _("r14 not allowed here")); | |
b99bd4ef | 9174 | } |
c19d1205 ZW |
9175 | inst.instruction |= inst.operands[0].reg << 12; |
9176 | inst.instruction |= inst.operands[1].reg << 8; | |
9177 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
9178 | ||
b99bd4ef NC |
9179 | } |
9180 | ||
c19d1205 ZW |
9181 | static void |
9182 | do_t_ldstt (void) | |
9183 | { | |
9184 | inst.instruction |= inst.operands[0].reg << 12; | |
9185 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
9186 | } | |
a737bd4d | 9187 | |
b99bd4ef | 9188 | static void |
c19d1205 | 9189 | do_t_mla (void) |
b99bd4ef | 9190 | { |
c19d1205 ZW |
9191 | inst.instruction |= inst.operands[0].reg << 8; |
9192 | inst.instruction |= inst.operands[1].reg << 16; | |
9193 | inst.instruction |= inst.operands[2].reg; | |
9194 | inst.instruction |= inst.operands[3].reg << 12; | |
9195 | } | |
b99bd4ef | 9196 | |
c19d1205 ZW |
9197 | static void |
9198 | do_t_mlal (void) | |
9199 | { | |
9200 | inst.instruction |= inst.operands[0].reg << 12; | |
9201 | inst.instruction |= inst.operands[1].reg << 8; | |
9202 | inst.instruction |= inst.operands[2].reg << 16; | |
9203 | inst.instruction |= inst.operands[3].reg; | |
9204 | } | |
b99bd4ef | 9205 | |
c19d1205 ZW |
9206 | static void |
9207 | do_t_mov_cmp (void) | |
9208 | { | |
9209 | if (unified_syntax) | |
b99bd4ef | 9210 | { |
c19d1205 ZW |
9211 | int r0off = (inst.instruction == T_MNEM_mov |
9212 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 9213 | unsigned long opcode; |
3d388997 PB |
9214 | bfd_boolean narrow; |
9215 | bfd_boolean low_regs; | |
9216 | ||
9217 | low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7); | |
0110f2b8 | 9218 | opcode = inst.instruction; |
3d388997 | 9219 | if (current_it_mask) |
0110f2b8 | 9220 | narrow = opcode != T_MNEM_movs; |
3d388997 | 9221 | else |
0110f2b8 | 9222 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
9223 | if (inst.size_req == 4 |
9224 | || inst.operands[1].shifted) | |
9225 | narrow = FALSE; | |
9226 | ||
c19d1205 ZW |
9227 | if (!inst.operands[1].isreg) |
9228 | { | |
0110f2b8 PB |
9229 | /* Immediate operand. */ |
9230 | if (current_it_mask == 0 && opcode == T_MNEM_mov) | |
9231 | narrow = 0; | |
9232 | if (low_regs && narrow) | |
9233 | { | |
9234 | inst.instruction = THUMB_OP16 (opcode); | |
9235 | inst.instruction |= inst.operands[0].reg << 8; | |
9236 | if (inst.size_req == 2) | |
9237 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
9238 | else | |
9239 | inst.relax = opcode; | |
9240 | } | |
9241 | else | |
9242 | { | |
9243 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9244 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
9245 | inst.instruction |= inst.operands[0].reg << r0off; | |
9246 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9247 | } | |
c19d1205 | 9248 | } |
3d388997 | 9249 | else if (!narrow) |
c19d1205 ZW |
9250 | { |
9251 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9252 | inst.instruction |= inst.operands[0].reg << r0off; | |
9253 | encode_thumb32_shifted_operand (1); | |
9254 | } | |
9255 | else | |
9256 | switch (inst.instruction) | |
9257 | { | |
9258 | case T_MNEM_mov: | |
9259 | inst.instruction = T_OPCODE_MOV_HR; | |
9260 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; | |
9261 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
9262 | inst.instruction |= inst.operands[1].reg << 3; | |
9263 | break; | |
b99bd4ef | 9264 | |
c19d1205 ZW |
9265 | case T_MNEM_movs: |
9266 | /* We know we have low registers at this point. | |
9267 | Generate ADD Rd, Rs, #0. */ | |
9268 | inst.instruction = T_OPCODE_ADD_I3; | |
9269 | inst.instruction |= inst.operands[0].reg; | |
9270 | inst.instruction |= inst.operands[1].reg << 3; | |
9271 | break; | |
9272 | ||
9273 | case T_MNEM_cmp: | |
3d388997 | 9274 | if (low_regs) |
c19d1205 ZW |
9275 | { |
9276 | inst.instruction = T_OPCODE_CMP_LR; | |
9277 | inst.instruction |= inst.operands[0].reg; | |
9278 | inst.instruction |= inst.operands[1].reg << 3; | |
9279 | } | |
9280 | else | |
9281 | { | |
9282 | inst.instruction = T_OPCODE_CMP_HR; | |
9283 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; | |
9284 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
9285 | inst.instruction |= inst.operands[1].reg << 3; | |
9286 | } | |
9287 | break; | |
9288 | } | |
b99bd4ef NC |
9289 | return; |
9290 | } | |
9291 | ||
c19d1205 ZW |
9292 | inst.instruction = THUMB_OP16 (inst.instruction); |
9293 | if (inst.operands[1].isreg) | |
b99bd4ef | 9294 | { |
c19d1205 | 9295 | if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8) |
b99bd4ef | 9296 | { |
c19d1205 ZW |
9297 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
9298 | since a MOV instruction produces unpredictable results. */ | |
9299 | if (inst.instruction == T_OPCODE_MOV_I8) | |
9300 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 9301 | else |
c19d1205 | 9302 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 9303 | |
c19d1205 ZW |
9304 | inst.instruction |= inst.operands[0].reg; |
9305 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
9306 | } |
9307 | else | |
9308 | { | |
c19d1205 ZW |
9309 | if (inst.instruction == T_OPCODE_MOV_I8) |
9310 | inst.instruction = T_OPCODE_MOV_HR; | |
9311 | else | |
9312 | inst.instruction = T_OPCODE_CMP_HR; | |
9313 | do_t_cpy (); | |
b99bd4ef NC |
9314 | } |
9315 | } | |
c19d1205 | 9316 | else |
b99bd4ef | 9317 | { |
c19d1205 ZW |
9318 | constraint (inst.operands[0].reg > 7, |
9319 | _("only lo regs allowed with immediate")); | |
9320 | inst.instruction |= inst.operands[0].reg << 8; | |
9321 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
9322 | } | |
9323 | } | |
b99bd4ef | 9324 | |
c19d1205 ZW |
9325 | static void |
9326 | do_t_mov16 (void) | |
9327 | { | |
b6895b4f PB |
9328 | bfd_vma imm; |
9329 | bfd_boolean top; | |
9330 | ||
9331 | top = (inst.instruction & 0x00800000) != 0; | |
9332 | if (inst.reloc.type == BFD_RELOC_ARM_MOVW) | |
9333 | { | |
9334 | constraint (top, _(":lower16: not allowed this instruction")); | |
9335 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; | |
9336 | } | |
9337 | else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) | |
9338 | { | |
9339 | constraint (!top, _(":upper16: not allowed this instruction")); | |
9340 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; | |
9341 | } | |
9342 | ||
c19d1205 | 9343 | inst.instruction |= inst.operands[0].reg << 8; |
b6895b4f PB |
9344 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
9345 | { | |
9346 | imm = inst.reloc.exp.X_add_number; | |
9347 | inst.instruction |= (imm & 0xf000) << 4; | |
9348 | inst.instruction |= (imm & 0x0800) << 15; | |
9349 | inst.instruction |= (imm & 0x0700) << 4; | |
9350 | inst.instruction |= (imm & 0x00ff); | |
9351 | } | |
c19d1205 | 9352 | } |
b99bd4ef | 9353 | |
c19d1205 ZW |
9354 | static void |
9355 | do_t_mvn_tst (void) | |
9356 | { | |
9357 | if (unified_syntax) | |
9358 | { | |
9359 | int r0off = (inst.instruction == T_MNEM_mvn | |
9360 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
9361 | bfd_boolean narrow; |
9362 | ||
9363 | if (inst.size_req == 4 | |
9364 | || inst.instruction > 0xffff | |
9365 | || inst.operands[1].shifted | |
9366 | || inst.operands[0].reg > 7 || inst.operands[1].reg > 7) | |
9367 | narrow = FALSE; | |
9368 | else if (inst.instruction == T_MNEM_cmn) | |
9369 | narrow = TRUE; | |
9370 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
9371 | narrow = (current_it_mask == 0); | |
9372 | else | |
9373 | narrow = (current_it_mask != 0); | |
9374 | ||
c19d1205 | 9375 | if (!inst.operands[1].isreg) |
b99bd4ef | 9376 | { |
c19d1205 ZW |
9377 | /* For an immediate, we always generate a 32-bit opcode; |
9378 | section relaxation will shrink it later if possible. */ | |
9379 | if (inst.instruction < 0xffff) | |
9380 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9381 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
9382 | inst.instruction |= inst.operands[0].reg << r0off; | |
9383 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 9384 | } |
c19d1205 | 9385 | else |
b99bd4ef | 9386 | { |
c19d1205 | 9387 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 9388 | if (narrow) |
b99bd4ef | 9389 | { |
c19d1205 ZW |
9390 | inst.instruction = THUMB_OP16 (inst.instruction); |
9391 | inst.instruction |= inst.operands[0].reg; | |
9392 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef | 9393 | } |
c19d1205 | 9394 | else |
b99bd4ef | 9395 | { |
c19d1205 ZW |
9396 | constraint (inst.operands[1].shifted |
9397 | && inst.operands[1].immisreg, | |
9398 | _("shift must be constant")); | |
9399 | if (inst.instruction < 0xffff) | |
9400 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9401 | inst.instruction |= inst.operands[0].reg << r0off; | |
9402 | encode_thumb32_shifted_operand (1); | |
b99bd4ef | 9403 | } |
b99bd4ef NC |
9404 | } |
9405 | } | |
9406 | else | |
9407 | { | |
c19d1205 ZW |
9408 | constraint (inst.instruction > 0xffff |
9409 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
9410 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
9411 | _("unshifted register required")); | |
9412 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, | |
9413 | BAD_HIREG); | |
b99bd4ef | 9414 | |
c19d1205 ZW |
9415 | inst.instruction = THUMB_OP16 (inst.instruction); |
9416 | inst.instruction |= inst.operands[0].reg; | |
9417 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef | 9418 | } |
b99bd4ef NC |
9419 | } |
9420 | ||
b05fe5cf | 9421 | static void |
c19d1205 | 9422 | do_t_mrs (void) |
b05fe5cf | 9423 | { |
62b3e311 | 9424 | int flags; |
037e8744 JB |
9425 | |
9426 | if (do_vfp_nsyn_mrs () == SUCCESS) | |
9427 | return; | |
9428 | ||
62b3e311 PB |
9429 | flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
9430 | if (flags == 0) | |
9431 | { | |
9432 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m), | |
9433 | _("selected processor does not support " | |
9434 | "requested special purpose register")); | |
9435 | } | |
9436 | else | |
9437 | { | |
9438 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), | |
9439 | _("selected processor does not support " | |
9440 | "requested special purpose register %x")); | |
9441 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ | |
9442 | constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), | |
9443 | _("'CPSR' or 'SPSR' expected")); | |
9444 | } | |
9445 | ||
c19d1205 | 9446 | inst.instruction |= inst.operands[0].reg << 8; |
62b3e311 PB |
9447 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
9448 | inst.instruction |= inst.operands[1].imm & 0xff; | |
c19d1205 | 9449 | } |
b05fe5cf | 9450 | |
c19d1205 ZW |
9451 | static void |
9452 | do_t_msr (void) | |
9453 | { | |
62b3e311 PB |
9454 | int flags; |
9455 | ||
037e8744 JB |
9456 | if (do_vfp_nsyn_msr () == SUCCESS) |
9457 | return; | |
9458 | ||
c19d1205 ZW |
9459 | constraint (!inst.operands[1].isreg, |
9460 | _("Thumb encoding does not support an immediate here")); | |
62b3e311 PB |
9461 | flags = inst.operands[0].imm; |
9462 | if (flags & ~0xff) | |
9463 | { | |
9464 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), | |
9465 | _("selected processor does not support " | |
9466 | "requested special purpose register")); | |
9467 | } | |
9468 | else | |
9469 | { | |
9470 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m), | |
9471 | _("selected processor does not support " | |
9472 | "requested special purpose register")); | |
9473 | flags |= PSR_f; | |
9474 | } | |
9475 | inst.instruction |= (flags & SPSR_BIT) >> 2; | |
9476 | inst.instruction |= (flags & ~SPSR_BIT) >> 8; | |
9477 | inst.instruction |= (flags & 0xff); | |
c19d1205 ZW |
9478 | inst.instruction |= inst.operands[1].reg << 16; |
9479 | } | |
b05fe5cf | 9480 | |
c19d1205 ZW |
9481 | static void |
9482 | do_t_mul (void) | |
9483 | { | |
9484 | if (!inst.operands[2].present) | |
9485 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 9486 | |
c19d1205 ZW |
9487 | /* There is no 32-bit MULS and no 16-bit MUL. */ |
9488 | if (unified_syntax && inst.instruction == T_MNEM_mul) | |
b05fe5cf | 9489 | { |
c19d1205 ZW |
9490 | inst.instruction = THUMB_OP32 (inst.instruction); |
9491 | inst.instruction |= inst.operands[0].reg << 8; | |
9492 | inst.instruction |= inst.operands[1].reg << 16; | |
9493 | inst.instruction |= inst.operands[2].reg << 0; | |
b05fe5cf | 9494 | } |
c19d1205 | 9495 | else |
b05fe5cf | 9496 | { |
c19d1205 ZW |
9497 | constraint (!unified_syntax |
9498 | && inst.instruction == T_MNEM_muls, BAD_THUMB32); | |
9499 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, | |
9500 | BAD_HIREG); | |
b05fe5cf | 9501 | |
c19d1205 ZW |
9502 | inst.instruction = THUMB_OP16 (inst.instruction); |
9503 | inst.instruction |= inst.operands[0].reg; | |
b05fe5cf | 9504 | |
c19d1205 ZW |
9505 | if (inst.operands[0].reg == inst.operands[1].reg) |
9506 | inst.instruction |= inst.operands[2].reg << 3; | |
9507 | else if (inst.operands[0].reg == inst.operands[2].reg) | |
9508 | inst.instruction |= inst.operands[1].reg << 3; | |
9509 | else | |
9510 | constraint (1, _("dest must overlap one source register")); | |
9511 | } | |
9512 | } | |
b05fe5cf | 9513 | |
c19d1205 ZW |
9514 | static void |
9515 | do_t_mull (void) | |
9516 | { | |
9517 | inst.instruction |= inst.operands[0].reg << 12; | |
9518 | inst.instruction |= inst.operands[1].reg << 8; | |
9519 | inst.instruction |= inst.operands[2].reg << 16; | |
9520 | inst.instruction |= inst.operands[3].reg; | |
b05fe5cf | 9521 | |
c19d1205 ZW |
9522 | if (inst.operands[0].reg == inst.operands[1].reg) |
9523 | as_tsktsk (_("rdhi and rdlo must be different")); | |
9524 | } | |
b05fe5cf | 9525 | |
c19d1205 ZW |
9526 | static void |
9527 | do_t_nop (void) | |
9528 | { | |
9529 | if (unified_syntax) | |
9530 | { | |
9531 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 9532 | { |
c19d1205 ZW |
9533 | inst.instruction = THUMB_OP32 (inst.instruction); |
9534 | inst.instruction |= inst.operands[0].imm; | |
9535 | } | |
9536 | else | |
9537 | { | |
9538 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9539 | inst.instruction |= inst.operands[0].imm << 4; | |
9540 | } | |
9541 | } | |
9542 | else | |
9543 | { | |
9544 | constraint (inst.operands[0].present, | |
9545 | _("Thumb does not support NOP with hints")); | |
9546 | inst.instruction = 0x46c0; | |
9547 | } | |
9548 | } | |
b05fe5cf | 9549 | |
c19d1205 ZW |
9550 | static void |
9551 | do_t_neg (void) | |
9552 | { | |
9553 | if (unified_syntax) | |
9554 | { | |
3d388997 PB |
9555 | bfd_boolean narrow; |
9556 | ||
9557 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
9558 | narrow = (current_it_mask == 0); | |
9559 | else | |
9560 | narrow = (current_it_mask != 0); | |
9561 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) | |
9562 | narrow = FALSE; | |
9563 | if (inst.size_req == 4) | |
9564 | narrow = FALSE; | |
9565 | ||
9566 | if (!narrow) | |
c19d1205 ZW |
9567 | { |
9568 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9569 | inst.instruction |= inst.operands[0].reg << 8; | |
9570 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
9571 | } |
9572 | else | |
9573 | { | |
c19d1205 ZW |
9574 | inst.instruction = THUMB_OP16 (inst.instruction); |
9575 | inst.instruction |= inst.operands[0].reg; | |
9576 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
9577 | } |
9578 | } | |
9579 | else | |
9580 | { | |
c19d1205 ZW |
9581 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
9582 | BAD_HIREG); | |
9583 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
9584 | ||
9585 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9586 | inst.instruction |= inst.operands[0].reg; | |
9587 | inst.instruction |= inst.operands[1].reg << 3; | |
9588 | } | |
9589 | } | |
9590 | ||
9591 | static void | |
9592 | do_t_pkhbt (void) | |
9593 | { | |
9594 | inst.instruction |= inst.operands[0].reg << 8; | |
9595 | inst.instruction |= inst.operands[1].reg << 16; | |
9596 | inst.instruction |= inst.operands[2].reg; | |
9597 | if (inst.operands[3].present) | |
9598 | { | |
9599 | unsigned int val = inst.reloc.exp.X_add_number; | |
9600 | constraint (inst.reloc.exp.X_op != O_constant, | |
9601 | _("expression too complex")); | |
9602 | inst.instruction |= (val & 0x1c) << 10; | |
9603 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 9604 | } |
c19d1205 | 9605 | } |
b05fe5cf | 9606 | |
c19d1205 ZW |
9607 | static void |
9608 | do_t_pkhtb (void) | |
9609 | { | |
9610 | if (!inst.operands[3].present) | |
9611 | inst.instruction &= ~0x00000020; | |
9612 | do_t_pkhbt (); | |
b05fe5cf ZW |
9613 | } |
9614 | ||
c19d1205 ZW |
9615 | static void |
9616 | do_t_pld (void) | |
9617 | { | |
9618 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
9619 | } | |
b05fe5cf | 9620 | |
c19d1205 ZW |
9621 | static void |
9622 | do_t_push_pop (void) | |
b99bd4ef | 9623 | { |
e9f89963 PB |
9624 | unsigned mask; |
9625 | ||
c19d1205 ZW |
9626 | constraint (inst.operands[0].writeback, |
9627 | _("push/pop do not support {reglist}^")); | |
9628 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
9629 | _("expression too complex")); | |
b99bd4ef | 9630 | |
e9f89963 PB |
9631 | mask = inst.operands[0].imm; |
9632 | if ((mask & ~0xff) == 0) | |
c19d1205 ZW |
9633 | inst.instruction = THUMB_OP16 (inst.instruction); |
9634 | else if ((inst.instruction == T_MNEM_push | |
e9f89963 | 9635 | && (mask & ~0xff) == 1 << REG_LR) |
c19d1205 | 9636 | || (inst.instruction == T_MNEM_pop |
e9f89963 | 9637 | && (mask & ~0xff) == 1 << REG_PC)) |
b99bd4ef | 9638 | { |
c19d1205 ZW |
9639 | inst.instruction = THUMB_OP16 (inst.instruction); |
9640 | inst.instruction |= THUMB_PP_PC_LR; | |
e9f89963 | 9641 | mask &= 0xff; |
c19d1205 ZW |
9642 | } |
9643 | else if (unified_syntax) | |
9644 | { | |
e9f89963 PB |
9645 | if (mask & (1 << 13)) |
9646 | inst.error = _("SP not allowed in register list"); | |
c19d1205 | 9647 | if (inst.instruction == T_MNEM_push) |
b99bd4ef | 9648 | { |
e9f89963 PB |
9649 | if (mask & (1 << 15)) |
9650 | inst.error = _("PC not allowed in register list"); | |
c19d1205 ZW |
9651 | } |
9652 | else | |
9653 | { | |
e9f89963 PB |
9654 | if (mask & (1 << 14) |
9655 | && mask & (1 << 15)) | |
9656 | inst.error = _("LR and PC should not both be in register list"); | |
c19d1205 | 9657 | } |
e9f89963 PB |
9658 | if ((mask & (mask - 1)) == 0) |
9659 | { | |
9660 | /* Single register push/pop implemented as str/ldr. */ | |
9661 | if (inst.instruction == T_MNEM_push) | |
9662 | inst.instruction = 0xf84d0d04; /* str reg, [sp, #-4]! */ | |
9663 | else | |
9664 | inst.instruction = 0xf85d0b04; /* ldr reg, [sp], #4 */ | |
9665 | mask = ffs(mask) - 1; | |
9666 | mask <<= 12; | |
9667 | } | |
9668 | else | |
9669 | inst.instruction = THUMB_OP32 (inst.instruction); | |
c19d1205 ZW |
9670 | } |
9671 | else | |
9672 | { | |
9673 | inst.error = _("invalid register list to push/pop instruction"); | |
9674 | return; | |
9675 | } | |
b99bd4ef | 9676 | |
e9f89963 | 9677 | inst.instruction |= mask; |
c19d1205 | 9678 | } |
b99bd4ef | 9679 | |
c19d1205 ZW |
9680 | static void |
9681 | do_t_rbit (void) | |
9682 | { | |
9683 | inst.instruction |= inst.operands[0].reg << 8; | |
9684 | inst.instruction |= inst.operands[1].reg << 16; | |
9685 | } | |
b99bd4ef | 9686 | |
c19d1205 ZW |
9687 | static void |
9688 | do_t_rev (void) | |
9689 | { | |
9690 | if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 | |
9691 | && inst.size_req != 4) | |
9692 | { | |
9693 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9694 | inst.instruction |= inst.operands[0].reg; | |
9695 | inst.instruction |= inst.operands[1].reg << 3; | |
9696 | } | |
9697 | else if (unified_syntax) | |
9698 | { | |
9699 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9700 | inst.instruction |= inst.operands[0].reg << 8; | |
9701 | inst.instruction |= inst.operands[1].reg << 16; | |
9702 | inst.instruction |= inst.operands[1].reg; | |
9703 | } | |
9704 | else | |
9705 | inst.error = BAD_HIREG; | |
9706 | } | |
b99bd4ef | 9707 | |
c19d1205 ZW |
9708 | static void |
9709 | do_t_rsb (void) | |
9710 | { | |
9711 | int Rd, Rs; | |
b99bd4ef | 9712 | |
c19d1205 ZW |
9713 | Rd = inst.operands[0].reg; |
9714 | Rs = (inst.operands[1].present | |
9715 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9716 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 9717 | |
c19d1205 ZW |
9718 | inst.instruction |= Rd << 8; |
9719 | inst.instruction |= Rs << 16; | |
9720 | if (!inst.operands[2].isreg) | |
9721 | { | |
9722 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
9723 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9724 | } | |
9725 | else | |
9726 | encode_thumb32_shifted_operand (2); | |
9727 | } | |
b99bd4ef | 9728 | |
c19d1205 ZW |
9729 | static void |
9730 | do_t_setend (void) | |
9731 | { | |
dfa9f0d5 | 9732 | constraint (current_it_mask, BAD_NOT_IT); |
c19d1205 ZW |
9733 | if (inst.operands[0].imm) |
9734 | inst.instruction |= 0x8; | |
9735 | } | |
b99bd4ef | 9736 | |
c19d1205 ZW |
9737 | static void |
9738 | do_t_shift (void) | |
9739 | { | |
9740 | if (!inst.operands[1].present) | |
9741 | inst.operands[1].reg = inst.operands[0].reg; | |
9742 | ||
9743 | if (unified_syntax) | |
9744 | { | |
3d388997 PB |
9745 | bfd_boolean narrow; |
9746 | int shift_kind; | |
9747 | ||
9748 | switch (inst.instruction) | |
9749 | { | |
9750 | case T_MNEM_asr: | |
9751 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
9752 | case T_MNEM_lsl: | |
9753 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
9754 | case T_MNEM_lsr: | |
9755 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
9756 | case T_MNEM_ror: | |
9757 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
9758 | default: abort (); | |
9759 | } | |
9760 | ||
9761 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
9762 | narrow = (current_it_mask == 0); | |
9763 | else | |
9764 | narrow = (current_it_mask != 0); | |
9765 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) | |
9766 | narrow = FALSE; | |
9767 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
9768 | narrow = FALSE; | |
9769 | if (inst.operands[2].isreg | |
9770 | && (inst.operands[1].reg != inst.operands[0].reg | |
9771 | || inst.operands[2].reg > 7)) | |
9772 | narrow = FALSE; | |
9773 | if (inst.size_req == 4) | |
9774 | narrow = FALSE; | |
9775 | ||
9776 | if (!narrow) | |
c19d1205 ZW |
9777 | { |
9778 | if (inst.operands[2].isreg) | |
b99bd4ef | 9779 | { |
c19d1205 ZW |
9780 | inst.instruction = THUMB_OP32 (inst.instruction); |
9781 | inst.instruction |= inst.operands[0].reg << 8; | |
9782 | inst.instruction |= inst.operands[1].reg << 16; | |
9783 | inst.instruction |= inst.operands[2].reg; | |
9784 | } | |
9785 | else | |
9786 | { | |
9787 | inst.operands[1].shifted = 1; | |
3d388997 | 9788 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
9789 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
9790 | ? T_MNEM_movs : T_MNEM_mov); | |
9791 | inst.instruction |= inst.operands[0].reg << 8; | |
9792 | encode_thumb32_shifted_operand (1); | |
9793 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
9794 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef NC |
9795 | } |
9796 | } | |
9797 | else | |
9798 | { | |
c19d1205 | 9799 | if (inst.operands[2].isreg) |
b99bd4ef | 9800 | { |
3d388997 | 9801 | switch (shift_kind) |
b99bd4ef | 9802 | { |
3d388997 PB |
9803 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
9804 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
9805 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
9806 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 9807 | default: abort (); |
b99bd4ef | 9808 | } |
c19d1205 ZW |
9809 | |
9810 | inst.instruction |= inst.operands[0].reg; | |
9811 | inst.instruction |= inst.operands[2].reg << 3; | |
b99bd4ef NC |
9812 | } |
9813 | else | |
9814 | { | |
3d388997 | 9815 | switch (shift_kind) |
b99bd4ef | 9816 | { |
3d388997 PB |
9817 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
9818 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
9819 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 9820 | default: abort (); |
b99bd4ef | 9821 | } |
c19d1205 ZW |
9822 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
9823 | inst.instruction |= inst.operands[0].reg; | |
9824 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
9825 | } |
9826 | } | |
c19d1205 ZW |
9827 | } |
9828 | else | |
9829 | { | |
9830 | constraint (inst.operands[0].reg > 7 | |
9831 | || inst.operands[1].reg > 7, BAD_HIREG); | |
9832 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 9833 | |
c19d1205 ZW |
9834 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
9835 | { | |
9836 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
9837 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
9838 | _("source1 and dest must be same register")); | |
b99bd4ef | 9839 | |
c19d1205 ZW |
9840 | switch (inst.instruction) |
9841 | { | |
9842 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
9843 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
9844 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
9845 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
9846 | default: abort (); | |
9847 | } | |
9848 | ||
9849 | inst.instruction |= inst.operands[0].reg; | |
9850 | inst.instruction |= inst.operands[2].reg << 3; | |
9851 | } | |
9852 | else | |
b99bd4ef | 9853 | { |
c19d1205 ZW |
9854 | switch (inst.instruction) |
9855 | { | |
9856 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
9857 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
9858 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
9859 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
9860 | default: abort (); | |
9861 | } | |
9862 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
9863 | inst.instruction |= inst.operands[0].reg; | |
9864 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
9865 | } |
9866 | } | |
b99bd4ef NC |
9867 | } |
9868 | ||
9869 | static void | |
c19d1205 | 9870 | do_t_simd (void) |
b99bd4ef | 9871 | { |
c19d1205 ZW |
9872 | inst.instruction |= inst.operands[0].reg << 8; |
9873 | inst.instruction |= inst.operands[1].reg << 16; | |
9874 | inst.instruction |= inst.operands[2].reg; | |
9875 | } | |
b99bd4ef | 9876 | |
c19d1205 | 9877 | static void |
3eb17e6b | 9878 | do_t_smc (void) |
c19d1205 ZW |
9879 | { |
9880 | unsigned int value = inst.reloc.exp.X_add_number; | |
9881 | constraint (inst.reloc.exp.X_op != O_constant, | |
9882 | _("expression too complex")); | |
9883 | inst.reloc.type = BFD_RELOC_UNUSED; | |
9884 | inst.instruction |= (value & 0xf000) >> 12; | |
9885 | inst.instruction |= (value & 0x0ff0); | |
9886 | inst.instruction |= (value & 0x000f) << 16; | |
9887 | } | |
b99bd4ef | 9888 | |
c19d1205 ZW |
9889 | static void |
9890 | do_t_ssat (void) | |
9891 | { | |
9892 | inst.instruction |= inst.operands[0].reg << 8; | |
9893 | inst.instruction |= inst.operands[1].imm - 1; | |
9894 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef | 9895 | |
c19d1205 | 9896 | if (inst.operands[3].present) |
b99bd4ef | 9897 | { |
c19d1205 ZW |
9898 | constraint (inst.reloc.exp.X_op != O_constant, |
9899 | _("expression too complex")); | |
b99bd4ef | 9900 | |
c19d1205 | 9901 | if (inst.reloc.exp.X_add_number != 0) |
6189168b | 9902 | { |
c19d1205 ZW |
9903 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
9904 | inst.instruction |= 0x00200000; /* sh bit */ | |
9905 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; | |
9906 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; | |
6189168b | 9907 | } |
c19d1205 | 9908 | inst.reloc.type = BFD_RELOC_UNUSED; |
6189168b | 9909 | } |
b99bd4ef NC |
9910 | } |
9911 | ||
0dd132b6 | 9912 | static void |
c19d1205 | 9913 | do_t_ssat16 (void) |
0dd132b6 | 9914 | { |
c19d1205 ZW |
9915 | inst.instruction |= inst.operands[0].reg << 8; |
9916 | inst.instruction |= inst.operands[1].imm - 1; | |
9917 | inst.instruction |= inst.operands[2].reg << 16; | |
9918 | } | |
0dd132b6 | 9919 | |
c19d1205 ZW |
9920 | static void |
9921 | do_t_strex (void) | |
9922 | { | |
9923 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
9924 | || inst.operands[2].postind || inst.operands[2].writeback | |
9925 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
9926 | || inst.operands[2].negative, | |
01cfc07f | 9927 | BAD_ADDR_MODE); |
0dd132b6 | 9928 | |
c19d1205 ZW |
9929 | inst.instruction |= inst.operands[0].reg << 8; |
9930 | inst.instruction |= inst.operands[1].reg << 12; | |
9931 | inst.instruction |= inst.operands[2].reg << 16; | |
9932 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
0dd132b6 NC |
9933 | } |
9934 | ||
b99bd4ef | 9935 | static void |
c19d1205 | 9936 | do_t_strexd (void) |
b99bd4ef | 9937 | { |
c19d1205 ZW |
9938 | if (!inst.operands[2].present) |
9939 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 9940 | |
c19d1205 ZW |
9941 | constraint (inst.operands[0].reg == inst.operands[1].reg |
9942 | || inst.operands[0].reg == inst.operands[2].reg | |
9943 | || inst.operands[0].reg == inst.operands[3].reg | |
9944 | || inst.operands[1].reg == inst.operands[2].reg, | |
9945 | BAD_OVERLAP); | |
b99bd4ef | 9946 | |
c19d1205 ZW |
9947 | inst.instruction |= inst.operands[0].reg; |
9948 | inst.instruction |= inst.operands[1].reg << 12; | |
9949 | inst.instruction |= inst.operands[2].reg << 8; | |
9950 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
9951 | } |
9952 | ||
9953 | static void | |
c19d1205 | 9954 | do_t_sxtah (void) |
b99bd4ef | 9955 | { |
c19d1205 ZW |
9956 | inst.instruction |= inst.operands[0].reg << 8; |
9957 | inst.instruction |= inst.operands[1].reg << 16; | |
9958 | inst.instruction |= inst.operands[2].reg; | |
9959 | inst.instruction |= inst.operands[3].imm << 4; | |
9960 | } | |
b99bd4ef | 9961 | |
c19d1205 ZW |
9962 | static void |
9963 | do_t_sxth (void) | |
9964 | { | |
9965 | if (inst.instruction <= 0xffff && inst.size_req != 4 | |
9966 | && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 | |
9967 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) | |
b99bd4ef | 9968 | { |
c19d1205 ZW |
9969 | inst.instruction = THUMB_OP16 (inst.instruction); |
9970 | inst.instruction |= inst.operands[0].reg; | |
9971 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef | 9972 | } |
c19d1205 | 9973 | else if (unified_syntax) |
b99bd4ef | 9974 | { |
c19d1205 ZW |
9975 | if (inst.instruction <= 0xffff) |
9976 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9977 | inst.instruction |= inst.operands[0].reg << 8; | |
9978 | inst.instruction |= inst.operands[1].reg; | |
9979 | inst.instruction |= inst.operands[2].imm << 4; | |
b99bd4ef | 9980 | } |
c19d1205 | 9981 | else |
b99bd4ef | 9982 | { |
c19d1205 ZW |
9983 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
9984 | _("Thumb encoding does not support rotation")); | |
9985 | constraint (1, BAD_HIREG); | |
b99bd4ef | 9986 | } |
c19d1205 | 9987 | } |
b99bd4ef | 9988 | |
c19d1205 ZW |
9989 | static void |
9990 | do_t_swi (void) | |
9991 | { | |
9992 | inst.reloc.type = BFD_RELOC_ARM_SWI; | |
9993 | } | |
b99bd4ef | 9994 | |
92e90b6e PB |
9995 | static void |
9996 | do_t_tb (void) | |
9997 | { | |
9998 | int half; | |
9999 | ||
10000 | half = (inst.instruction & 0x10) != 0; | |
dfa9f0d5 PB |
10001 | constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); |
10002 | constraint (inst.operands[0].immisreg, | |
10003 | _("instruction requires register index")); | |
92e90b6e PB |
10004 | constraint (inst.operands[0].imm == 15, |
10005 | _("PC is not a valid index register")); | |
10006 | constraint (!half && inst.operands[0].shifted, | |
10007 | _("instruction does not allow shifted index")); | |
92e90b6e PB |
10008 | inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm; |
10009 | } | |
10010 | ||
c19d1205 ZW |
10011 | static void |
10012 | do_t_usat (void) | |
10013 | { | |
10014 | inst.instruction |= inst.operands[0].reg << 8; | |
10015 | inst.instruction |= inst.operands[1].imm; | |
10016 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef | 10017 | |
c19d1205 | 10018 | if (inst.operands[3].present) |
b99bd4ef | 10019 | { |
c19d1205 ZW |
10020 | constraint (inst.reloc.exp.X_op != O_constant, |
10021 | _("expression too complex")); | |
10022 | if (inst.reloc.exp.X_add_number != 0) | |
10023 | { | |
10024 | if (inst.operands[3].shift_kind == SHIFT_ASR) | |
10025 | inst.instruction |= 0x00200000; /* sh bit */ | |
b99bd4ef | 10026 | |
c19d1205 ZW |
10027 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; |
10028 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; | |
10029 | } | |
10030 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 10031 | } |
b99bd4ef NC |
10032 | } |
10033 | ||
10034 | static void | |
c19d1205 | 10035 | do_t_usat16 (void) |
b99bd4ef | 10036 | { |
c19d1205 ZW |
10037 | inst.instruction |= inst.operands[0].reg << 8; |
10038 | inst.instruction |= inst.operands[1].imm; | |
10039 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef | 10040 | } |
c19d1205 | 10041 | |
5287ad62 JB |
10042 | /* Neon instruction encoder helpers. */ |
10043 | ||
10044 | /* Encodings for the different types for various Neon opcodes. */ | |
b99bd4ef | 10045 | |
5287ad62 JB |
10046 | /* An "invalid" code for the following tables. */ |
10047 | #define N_INV -1u | |
10048 | ||
10049 | struct neon_tab_entry | |
b99bd4ef | 10050 | { |
5287ad62 JB |
10051 | unsigned integer; |
10052 | unsigned float_or_poly; | |
10053 | unsigned scalar_or_imm; | |
10054 | }; | |
10055 | ||
10056 | /* Map overloaded Neon opcodes to their respective encodings. */ | |
10057 | #define NEON_ENC_TAB \ | |
10058 | X(vabd, 0x0000700, 0x1200d00, N_INV), \ | |
10059 | X(vmax, 0x0000600, 0x0000f00, N_INV), \ | |
10060 | X(vmin, 0x0000610, 0x0200f00, N_INV), \ | |
10061 | X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ | |
10062 | X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ | |
10063 | X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ | |
10064 | X(vadd, 0x0000800, 0x0000d00, N_INV), \ | |
10065 | X(vsub, 0x1000800, 0x0200d00, N_INV), \ | |
10066 | X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ | |
10067 | X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ | |
10068 | X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ | |
10069 | /* Register variants of the following two instructions are encoded as | |
10070 | vcge / vcgt with the operands reversed. */ \ | |
10071 | X(vclt, 0x0000310, 0x1000e00, 0x1b10200), \ | |
10072 | X(vcle, 0x0000300, 0x1200e00, 0x1b10180), \ | |
10073 | X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ | |
10074 | X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ | |
10075 | X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ | |
10076 | X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ | |
10077 | X(vmlal, 0x0800800, N_INV, 0x0800240), \ | |
10078 | X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ | |
10079 | X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ | |
10080 | X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ | |
10081 | X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ | |
10082 | X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ | |
10083 | X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ | |
10084 | X(vshl, 0x0000400, N_INV, 0x0800510), \ | |
10085 | X(vqshl, 0x0000410, N_INV, 0x0800710), \ | |
10086 | X(vand, 0x0000110, N_INV, 0x0800030), \ | |
10087 | X(vbic, 0x0100110, N_INV, 0x0800030), \ | |
10088 | X(veor, 0x1000110, N_INV, N_INV), \ | |
10089 | X(vorn, 0x0300110, N_INV, 0x0800010), \ | |
10090 | X(vorr, 0x0200110, N_INV, 0x0800010), \ | |
10091 | X(vmvn, 0x1b00580, N_INV, 0x0800030), \ | |
10092 | X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ | |
10093 | X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ | |
10094 | X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ | |
10095 | X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ | |
10096 | X(vst1, 0x0000000, 0x0800000, N_INV), \ | |
10097 | X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ | |
10098 | X(vst2, 0x0000100, 0x0800100, N_INV), \ | |
10099 | X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ | |
10100 | X(vst3, 0x0000200, 0x0800200, N_INV), \ | |
10101 | X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ | |
10102 | X(vst4, 0x0000300, 0x0800300, N_INV), \ | |
10103 | X(vmovn, 0x1b20200, N_INV, N_INV), \ | |
10104 | X(vtrn, 0x1b20080, N_INV, N_INV), \ | |
10105 | X(vqmovn, 0x1b20200, N_INV, N_INV), \ | |
037e8744 JB |
10106 | X(vqmovun, 0x1b20240, N_INV, N_INV), \ |
10107 | X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ | |
10108 | X(vnmla, 0xe000a40, 0xe000b40, N_INV), \ | |
10109 | X(vnmls, 0xe100a40, 0xe100b40, N_INV), \ | |
10110 | X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ | |
10111 | X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ | |
10112 | X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ | |
10113 | X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV) | |
5287ad62 JB |
10114 | |
10115 | enum neon_opc | |
10116 | { | |
10117 | #define X(OPC,I,F,S) N_MNEM_##OPC | |
10118 | NEON_ENC_TAB | |
10119 | #undef X | |
10120 | }; | |
b99bd4ef | 10121 | |
5287ad62 JB |
10122 | static const struct neon_tab_entry neon_enc_tab[] = |
10123 | { | |
10124 | #define X(OPC,I,F,S) { (I), (F), (S) } | |
10125 | NEON_ENC_TAB | |
10126 | #undef X | |
10127 | }; | |
b99bd4ef | 10128 | |
5287ad62 JB |
10129 | #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer) |
10130 | #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
10131 | #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
10132 | #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
10133 | #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
10134 | #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
10135 | #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
10136 | #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
10137 | #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
037e8744 JB |
10138 | #define NEON_ENC_SINGLE(X) \ |
10139 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) | |
10140 | #define NEON_ENC_DOUBLE(X) \ | |
10141 | ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) | |
5287ad62 | 10142 | |
037e8744 JB |
10143 | /* Define shapes for instruction operands. The following mnemonic characters |
10144 | are used in this table: | |
5287ad62 | 10145 | |
037e8744 | 10146 | F - VFP S<n> register |
5287ad62 JB |
10147 | D - Neon D<n> register |
10148 | Q - Neon Q<n> register | |
10149 | I - Immediate | |
10150 | S - Scalar | |
10151 | R - ARM register | |
10152 | L - D<n> register list | |
037e8744 JB |
10153 | |
10154 | This table is used to generate various data: | |
10155 | - enumerations of the form NS_DDR to be used as arguments to | |
10156 | neon_select_shape. | |
10157 | - a table classifying shapes into single, double, quad, mixed. | |
10158 | - a table used to drive neon_select_shape. | |
5287ad62 | 10159 | */ |
b99bd4ef | 10160 | |
037e8744 JB |
10161 | #define NEON_SHAPE_DEF \ |
10162 | X(3, (D, D, D), DOUBLE), \ | |
10163 | X(3, (Q, Q, Q), QUAD), \ | |
10164 | X(3, (D, D, I), DOUBLE), \ | |
10165 | X(3, (Q, Q, I), QUAD), \ | |
10166 | X(3, (D, D, S), DOUBLE), \ | |
10167 | X(3, (Q, Q, S), QUAD), \ | |
10168 | X(2, (D, D), DOUBLE), \ | |
10169 | X(2, (Q, Q), QUAD), \ | |
10170 | X(2, (D, S), DOUBLE), \ | |
10171 | X(2, (Q, S), QUAD), \ | |
10172 | X(2, (D, R), DOUBLE), \ | |
10173 | X(2, (Q, R), QUAD), \ | |
10174 | X(2, (D, I), DOUBLE), \ | |
10175 | X(2, (Q, I), QUAD), \ | |
10176 | X(3, (D, L, D), DOUBLE), \ | |
10177 | X(2, (D, Q), MIXED), \ | |
10178 | X(2, (Q, D), MIXED), \ | |
10179 | X(3, (D, Q, I), MIXED), \ | |
10180 | X(3, (Q, D, I), MIXED), \ | |
10181 | X(3, (Q, D, D), MIXED), \ | |
10182 | X(3, (D, Q, Q), MIXED), \ | |
10183 | X(3, (Q, Q, D), MIXED), \ | |
10184 | X(3, (Q, D, S), MIXED), \ | |
10185 | X(3, (D, Q, S), MIXED), \ | |
10186 | X(4, (D, D, D, I), DOUBLE), \ | |
10187 | X(4, (Q, Q, Q, I), QUAD), \ | |
10188 | X(2, (F, F), SINGLE), \ | |
10189 | X(3, (F, F, F), SINGLE), \ | |
10190 | X(2, (F, I), SINGLE), \ | |
10191 | X(2, (F, D), MIXED), \ | |
10192 | X(2, (D, F), MIXED), \ | |
10193 | X(3, (F, F, I), MIXED), \ | |
10194 | X(4, (R, R, F, F), SINGLE), \ | |
10195 | X(4, (F, F, R, R), SINGLE), \ | |
10196 | X(3, (D, R, R), DOUBLE), \ | |
10197 | X(3, (R, R, D), DOUBLE), \ | |
10198 | X(2, (S, R), SINGLE), \ | |
10199 | X(2, (R, S), SINGLE), \ | |
10200 | X(2, (F, R), SINGLE), \ | |
10201 | X(2, (R, F), SINGLE) | |
10202 | ||
10203 | #define S2(A,B) NS_##A##B | |
10204 | #define S3(A,B,C) NS_##A##B##C | |
10205 | #define S4(A,B,C,D) NS_##A##B##C##D | |
10206 | ||
10207 | #define X(N, L, C) S##N L | |
10208 | ||
5287ad62 JB |
10209 | enum neon_shape |
10210 | { | |
037e8744 JB |
10211 | NEON_SHAPE_DEF, |
10212 | NS_NULL | |
5287ad62 | 10213 | }; |
b99bd4ef | 10214 | |
037e8744 JB |
10215 | #undef X |
10216 | #undef S2 | |
10217 | #undef S3 | |
10218 | #undef S4 | |
10219 | ||
10220 | enum neon_shape_class | |
10221 | { | |
10222 | SC_SINGLE, | |
10223 | SC_DOUBLE, | |
10224 | SC_QUAD, | |
10225 | SC_MIXED | |
10226 | }; | |
10227 | ||
10228 | #define X(N, L, C) SC_##C | |
10229 | ||
10230 | static enum neon_shape_class neon_shape_class[] = | |
10231 | { | |
10232 | NEON_SHAPE_DEF | |
10233 | }; | |
10234 | ||
10235 | #undef X | |
10236 | ||
10237 | enum neon_shape_el | |
10238 | { | |
10239 | SE_F, | |
10240 | SE_D, | |
10241 | SE_Q, | |
10242 | SE_I, | |
10243 | SE_S, | |
10244 | SE_R, | |
10245 | SE_L | |
10246 | }; | |
10247 | ||
10248 | /* Register widths of above. */ | |
10249 | static unsigned neon_shape_el_size[] = | |
10250 | { | |
10251 | 32, | |
10252 | 64, | |
10253 | 128, | |
10254 | 0, | |
10255 | 32, | |
10256 | 32, | |
10257 | 0 | |
10258 | }; | |
10259 | ||
10260 | struct neon_shape_info | |
10261 | { | |
10262 | unsigned els; | |
10263 | enum neon_shape_el el[NEON_MAX_TYPE_ELS]; | |
10264 | }; | |
10265 | ||
10266 | #define S2(A,B) { SE_##A, SE_##B } | |
10267 | #define S3(A,B,C) { SE_##A, SE_##B, SE_##C } | |
10268 | #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } | |
10269 | ||
10270 | #define X(N, L, C) { N, S##N L } | |
10271 | ||
10272 | static struct neon_shape_info neon_shape_tab[] = | |
10273 | { | |
10274 | NEON_SHAPE_DEF | |
10275 | }; | |
10276 | ||
10277 | #undef X | |
10278 | #undef S2 | |
10279 | #undef S3 | |
10280 | #undef S4 | |
10281 | ||
5287ad62 JB |
10282 | /* Bit masks used in type checking given instructions. |
10283 | 'N_EQK' means the type must be the same as (or based on in some way) the key | |
10284 | type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is | |
10285 | set, various other bits can be set as well in order to modify the meaning of | |
10286 | the type constraint. */ | |
10287 | ||
10288 | enum neon_type_mask | |
10289 | { | |
10290 | N_S8 = 0x000001, | |
10291 | N_S16 = 0x000002, | |
10292 | N_S32 = 0x000004, | |
10293 | N_S64 = 0x000008, | |
10294 | N_U8 = 0x000010, | |
10295 | N_U16 = 0x000020, | |
10296 | N_U32 = 0x000040, | |
10297 | N_U64 = 0x000080, | |
10298 | N_I8 = 0x000100, | |
10299 | N_I16 = 0x000200, | |
10300 | N_I32 = 0x000400, | |
10301 | N_I64 = 0x000800, | |
10302 | N_8 = 0x001000, | |
10303 | N_16 = 0x002000, | |
10304 | N_32 = 0x004000, | |
10305 | N_64 = 0x008000, | |
10306 | N_P8 = 0x010000, | |
10307 | N_P16 = 0x020000, | |
10308 | N_F32 = 0x040000, | |
037e8744 JB |
10309 | N_F64 = 0x080000, |
10310 | N_KEY = 0x100000, /* key element (main type specifier). */ | |
10311 | N_EQK = 0x200000, /* given operand has the same type & size as the key. */ | |
10312 | N_VFP = 0x400000, /* VFP mode: operand size must match register width. */ | |
5287ad62 JB |
10313 | N_DBL = 0x000001, /* if N_EQK, this operand is twice the size. */ |
10314 | N_HLF = 0x000002, /* if N_EQK, this operand is half the size. */ | |
10315 | N_SGN = 0x000004, /* if N_EQK, this operand is forced to be signed. */ | |
10316 | N_UNS = 0x000008, /* if N_EQK, this operand is forced to be unsigned. */ | |
10317 | N_INT = 0x000010, /* if N_EQK, this operand is forced to be integer. */ | |
10318 | N_FLT = 0x000020, /* if N_EQK, this operand is forced to be float. */ | |
dcbf9037 | 10319 | N_SIZ = 0x000040, /* if N_EQK, this operand is forced to be size-only. */ |
5287ad62 | 10320 | N_UTYP = 0, |
037e8744 | 10321 | N_MAX_NONSPECIAL = N_F64 |
5287ad62 JB |
10322 | }; |
10323 | ||
dcbf9037 JB |
10324 | #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) |
10325 | ||
5287ad62 JB |
10326 | #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) |
10327 | #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) | |
10328 | #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) | |
10329 | #define N_SUF_32 (N_SU_32 | N_F32) | |
10330 | #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) | |
10331 | #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) | |
10332 | ||
10333 | /* Pass this as the first type argument to neon_check_type to ignore types | |
10334 | altogether. */ | |
10335 | #define N_IGNORE_TYPE (N_KEY | N_EQK) | |
10336 | ||
037e8744 JB |
10337 | /* Select a "shape" for the current instruction (describing register types or |
10338 | sizes) from a list of alternatives. Return NS_NULL if the current instruction | |
10339 | doesn't fit. For non-polymorphic shapes, checking is usually done as a | |
10340 | function of operand parsing, so this function doesn't need to be called. | |
10341 | Shapes should be listed in order of decreasing length. */ | |
5287ad62 JB |
10342 | |
10343 | static enum neon_shape | |
037e8744 | 10344 | neon_select_shape (enum neon_shape shape, ...) |
5287ad62 | 10345 | { |
037e8744 JB |
10346 | va_list ap; |
10347 | enum neon_shape first_shape = shape; | |
5287ad62 JB |
10348 | |
10349 | /* Fix missing optional operands. FIXME: we don't know at this point how | |
10350 | many arguments we should have, so this makes the assumption that we have | |
10351 | > 1. This is true of all current Neon opcodes, I think, but may not be | |
10352 | true in the future. */ | |
10353 | if (!inst.operands[1].present) | |
10354 | inst.operands[1] = inst.operands[0]; | |
10355 | ||
037e8744 | 10356 | va_start (ap, shape); |
5287ad62 | 10357 | |
037e8744 JB |
10358 | for (; shape != NS_NULL; shape = va_arg (ap, int)) |
10359 | { | |
10360 | unsigned j; | |
10361 | int matches = 1; | |
10362 | ||
10363 | for (j = 0; j < neon_shape_tab[shape].els; j++) | |
10364 | { | |
10365 | if (!inst.operands[j].present) | |
10366 | { | |
10367 | matches = 0; | |
10368 | break; | |
10369 | } | |
10370 | ||
10371 | switch (neon_shape_tab[shape].el[j]) | |
10372 | { | |
10373 | case SE_F: | |
10374 | if (!(inst.operands[j].isreg | |
10375 | && inst.operands[j].isvec | |
10376 | && inst.operands[j].issingle | |
10377 | && !inst.operands[j].isquad)) | |
10378 | matches = 0; | |
10379 | break; | |
10380 | ||
10381 | case SE_D: | |
10382 | if (!(inst.operands[j].isreg | |
10383 | && inst.operands[j].isvec | |
10384 | && !inst.operands[j].isquad | |
10385 | && !inst.operands[j].issingle)) | |
10386 | matches = 0; | |
10387 | break; | |
10388 | ||
10389 | case SE_R: | |
10390 | if (!(inst.operands[j].isreg | |
10391 | && !inst.operands[j].isvec)) | |
10392 | matches = 0; | |
10393 | break; | |
10394 | ||
10395 | case SE_Q: | |
10396 | if (!(inst.operands[j].isreg | |
10397 | && inst.operands[j].isvec | |
10398 | && inst.operands[j].isquad | |
10399 | && !inst.operands[j].issingle)) | |
10400 | matches = 0; | |
10401 | break; | |
10402 | ||
10403 | case SE_I: | |
10404 | if (!(!inst.operands[j].isreg | |
10405 | && !inst.operands[j].isscalar)) | |
10406 | matches = 0; | |
10407 | break; | |
10408 | ||
10409 | case SE_S: | |
10410 | if (!(!inst.operands[j].isreg | |
10411 | && inst.operands[j].isscalar)) | |
10412 | matches = 0; | |
10413 | break; | |
10414 | ||
10415 | case SE_L: | |
10416 | break; | |
10417 | } | |
10418 | } | |
10419 | if (matches) | |
5287ad62 | 10420 | break; |
037e8744 | 10421 | } |
5287ad62 | 10422 | |
037e8744 | 10423 | va_end (ap); |
5287ad62 | 10424 | |
037e8744 JB |
10425 | if (shape == NS_NULL && first_shape != NS_NULL) |
10426 | first_error (_("invalid instruction shape")); | |
5287ad62 | 10427 | |
037e8744 JB |
10428 | return shape; |
10429 | } | |
5287ad62 | 10430 | |
037e8744 JB |
10431 | /* True if SHAPE is predominantly a quadword operation (most of the time, this |
10432 | means the Q bit should be set). */ | |
10433 | ||
10434 | static int | |
10435 | neon_quad (enum neon_shape shape) | |
10436 | { | |
10437 | return neon_shape_class[shape] == SC_QUAD; | |
5287ad62 | 10438 | } |
037e8744 | 10439 | |
5287ad62 JB |
10440 | static void |
10441 | neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, | |
10442 | unsigned *g_size) | |
10443 | { | |
10444 | /* Allow modification to be made to types which are constrained to be | |
10445 | based on the key element, based on bits set alongside N_EQK. */ | |
10446 | if ((typebits & N_EQK) != 0) | |
10447 | { | |
10448 | if ((typebits & N_HLF) != 0) | |
10449 | *g_size /= 2; | |
10450 | else if ((typebits & N_DBL) != 0) | |
10451 | *g_size *= 2; | |
10452 | if ((typebits & N_SGN) != 0) | |
10453 | *g_type = NT_signed; | |
10454 | else if ((typebits & N_UNS) != 0) | |
10455 | *g_type = NT_unsigned; | |
10456 | else if ((typebits & N_INT) != 0) | |
10457 | *g_type = NT_integer; | |
10458 | else if ((typebits & N_FLT) != 0) | |
10459 | *g_type = NT_float; | |
dcbf9037 JB |
10460 | else if ((typebits & N_SIZ) != 0) |
10461 | *g_type = NT_untyped; | |
5287ad62 JB |
10462 | } |
10463 | } | |
10464 | ||
10465 | /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" | |
10466 | operand type, i.e. the single type specified in a Neon instruction when it | |
10467 | is the only one given. */ | |
10468 | ||
10469 | static struct neon_type_el | |
10470 | neon_type_promote (struct neon_type_el *key, unsigned thisarg) | |
10471 | { | |
10472 | struct neon_type_el dest = *key; | |
10473 | ||
10474 | assert ((thisarg & N_EQK) != 0); | |
10475 | ||
10476 | neon_modify_type_size (thisarg, &dest.type, &dest.size); | |
10477 | ||
10478 | return dest; | |
10479 | } | |
10480 | ||
10481 | /* Convert Neon type and size into compact bitmask representation. */ | |
10482 | ||
10483 | static enum neon_type_mask | |
10484 | type_chk_of_el_type (enum neon_el_type type, unsigned size) | |
10485 | { | |
10486 | switch (type) | |
10487 | { | |
10488 | case NT_untyped: | |
10489 | switch (size) | |
10490 | { | |
10491 | case 8: return N_8; | |
10492 | case 16: return N_16; | |
10493 | case 32: return N_32; | |
10494 | case 64: return N_64; | |
10495 | default: ; | |
10496 | } | |
10497 | break; | |
10498 | ||
10499 | case NT_integer: | |
10500 | switch (size) | |
10501 | { | |
10502 | case 8: return N_I8; | |
10503 | case 16: return N_I16; | |
10504 | case 32: return N_I32; | |
10505 | case 64: return N_I64; | |
10506 | default: ; | |
10507 | } | |
10508 | break; | |
10509 | ||
10510 | case NT_float: | |
037e8744 JB |
10511 | switch (size) |
10512 | { | |
10513 | case 32: return N_F32; | |
10514 | case 64: return N_F64; | |
10515 | default: ; | |
10516 | } | |
5287ad62 JB |
10517 | break; |
10518 | ||
10519 | case NT_poly: | |
10520 | switch (size) | |
10521 | { | |
10522 | case 8: return N_P8; | |
10523 | case 16: return N_P16; | |
10524 | default: ; | |
10525 | } | |
10526 | break; | |
10527 | ||
10528 | case NT_signed: | |
10529 | switch (size) | |
10530 | { | |
10531 | case 8: return N_S8; | |
10532 | case 16: return N_S16; | |
10533 | case 32: return N_S32; | |
10534 | case 64: return N_S64; | |
10535 | default: ; | |
10536 | } | |
10537 | break; | |
10538 | ||
10539 | case NT_unsigned: | |
10540 | switch (size) | |
10541 | { | |
10542 | case 8: return N_U8; | |
10543 | case 16: return N_U16; | |
10544 | case 32: return N_U32; | |
10545 | case 64: return N_U64; | |
10546 | default: ; | |
10547 | } | |
10548 | break; | |
10549 | ||
10550 | default: ; | |
10551 | } | |
10552 | ||
10553 | return N_UTYP; | |
10554 | } | |
10555 | ||
10556 | /* Convert compact Neon bitmask type representation to a type and size. Only | |
10557 | handles the case where a single bit is set in the mask. */ | |
10558 | ||
dcbf9037 | 10559 | static int |
5287ad62 JB |
10560 | el_type_of_type_chk (enum neon_el_type *type, unsigned *size, |
10561 | enum neon_type_mask mask) | |
10562 | { | |
dcbf9037 JB |
10563 | if ((mask & N_EQK) != 0) |
10564 | return FAIL; | |
10565 | ||
5287ad62 JB |
10566 | if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) |
10567 | *size = 8; | |
dcbf9037 | 10568 | else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0) |
5287ad62 | 10569 | *size = 16; |
dcbf9037 | 10570 | else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) |
5287ad62 | 10571 | *size = 32; |
037e8744 | 10572 | else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0) |
5287ad62 | 10573 | *size = 64; |
dcbf9037 JB |
10574 | else |
10575 | return FAIL; | |
10576 | ||
5287ad62 JB |
10577 | if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) |
10578 | *type = NT_signed; | |
dcbf9037 | 10579 | else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) |
5287ad62 | 10580 | *type = NT_unsigned; |
dcbf9037 | 10581 | else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) |
5287ad62 | 10582 | *type = NT_integer; |
dcbf9037 | 10583 | else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) |
5287ad62 | 10584 | *type = NT_untyped; |
dcbf9037 | 10585 | else if ((mask & (N_P8 | N_P16)) != 0) |
5287ad62 | 10586 | *type = NT_poly; |
037e8744 | 10587 | else if ((mask & (N_F32 | N_F64)) != 0) |
5287ad62 | 10588 | *type = NT_float; |
dcbf9037 JB |
10589 | else |
10590 | return FAIL; | |
10591 | ||
10592 | return SUCCESS; | |
5287ad62 JB |
10593 | } |
10594 | ||
10595 | /* Modify a bitmask of allowed types. This is only needed for type | |
10596 | relaxation. */ | |
10597 | ||
10598 | static unsigned | |
10599 | modify_types_allowed (unsigned allowed, unsigned mods) | |
10600 | { | |
10601 | unsigned size; | |
10602 | enum neon_el_type type; | |
10603 | unsigned destmask; | |
10604 | int i; | |
10605 | ||
10606 | destmask = 0; | |
10607 | ||
10608 | for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) | |
10609 | { | |
dcbf9037 JB |
10610 | if (el_type_of_type_chk (&type, &size, allowed & i) == SUCCESS) |
10611 | { | |
10612 | neon_modify_type_size (mods, &type, &size); | |
10613 | destmask |= type_chk_of_el_type (type, size); | |
10614 | } | |
5287ad62 JB |
10615 | } |
10616 | ||
10617 | return destmask; | |
10618 | } | |
10619 | ||
10620 | /* Check type and return type classification. | |
10621 | The manual states (paraphrase): If one datatype is given, it indicates the | |
10622 | type given in: | |
10623 | - the second operand, if there is one | |
10624 | - the operand, if there is no second operand | |
10625 | - the result, if there are no operands. | |
10626 | This isn't quite good enough though, so we use a concept of a "key" datatype | |
10627 | which is set on a per-instruction basis, which is the one which matters when | |
10628 | only one data type is written. | |
10629 | Note: this function has side-effects (e.g. filling in missing operands). All | |
037e8744 | 10630 | Neon instructions should call it before performing bit encoding. */ |
5287ad62 JB |
10631 | |
10632 | static struct neon_type_el | |
10633 | neon_check_type (unsigned els, enum neon_shape ns, ...) | |
10634 | { | |
10635 | va_list ap; | |
10636 | unsigned i, pass, key_el = 0; | |
10637 | unsigned types[NEON_MAX_TYPE_ELS]; | |
10638 | enum neon_el_type k_type = NT_invtype; | |
10639 | unsigned k_size = -1u; | |
10640 | struct neon_type_el badtype = {NT_invtype, -1}; | |
10641 | unsigned key_allowed = 0; | |
10642 | ||
10643 | /* Optional registers in Neon instructions are always (not) in operand 1. | |
10644 | Fill in the missing operand here, if it was omitted. */ | |
10645 | if (els > 1 && !inst.operands[1].present) | |
10646 | inst.operands[1] = inst.operands[0]; | |
10647 | ||
10648 | /* Suck up all the varargs. */ | |
10649 | va_start (ap, ns); | |
10650 | for (i = 0; i < els; i++) | |
10651 | { | |
10652 | unsigned thisarg = va_arg (ap, unsigned); | |
10653 | if (thisarg == N_IGNORE_TYPE) | |
10654 | { | |
10655 | va_end (ap); | |
10656 | return badtype; | |
10657 | } | |
10658 | types[i] = thisarg; | |
10659 | if ((thisarg & N_KEY) != 0) | |
10660 | key_el = i; | |
10661 | } | |
10662 | va_end (ap); | |
10663 | ||
dcbf9037 JB |
10664 | if (inst.vectype.elems > 0) |
10665 | for (i = 0; i < els; i++) | |
10666 | if (inst.operands[i].vectype.type != NT_invtype) | |
10667 | { | |
10668 | first_error (_("types specified in both the mnemonic and operands")); | |
10669 | return badtype; | |
10670 | } | |
10671 | ||
5287ad62 JB |
10672 | /* Duplicate inst.vectype elements here as necessary. |
10673 | FIXME: No idea if this is exactly the same as the ARM assembler, | |
10674 | particularly when an insn takes one register and one non-register | |
10675 | operand. */ | |
10676 | if (inst.vectype.elems == 1 && els > 1) | |
10677 | { | |
10678 | unsigned j; | |
10679 | inst.vectype.elems = els; | |
10680 | inst.vectype.el[key_el] = inst.vectype.el[0]; | |
10681 | for (j = 0; j < els; j++) | |
dcbf9037 JB |
10682 | if (j != key_el) |
10683 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
10684 | types[j]); | |
10685 | } | |
10686 | else if (inst.vectype.elems == 0 && els > 0) | |
10687 | { | |
10688 | unsigned j; | |
10689 | /* No types were given after the mnemonic, so look for types specified | |
10690 | after each operand. We allow some flexibility here; as long as the | |
10691 | "key" operand has a type, we can infer the others. */ | |
10692 | for (j = 0; j < els; j++) | |
10693 | if (inst.operands[j].vectype.type != NT_invtype) | |
10694 | inst.vectype.el[j] = inst.operands[j].vectype; | |
10695 | ||
10696 | if (inst.operands[key_el].vectype.type != NT_invtype) | |
5287ad62 | 10697 | { |
dcbf9037 JB |
10698 | for (j = 0; j < els; j++) |
10699 | if (inst.operands[j].vectype.type == NT_invtype) | |
10700 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
10701 | types[j]); | |
10702 | } | |
10703 | else | |
10704 | { | |
10705 | first_error (_("operand types can't be inferred")); | |
10706 | return badtype; | |
5287ad62 JB |
10707 | } |
10708 | } | |
10709 | else if (inst.vectype.elems != els) | |
10710 | { | |
dcbf9037 | 10711 | first_error (_("type specifier has the wrong number of parts")); |
5287ad62 JB |
10712 | return badtype; |
10713 | } | |
10714 | ||
10715 | for (pass = 0; pass < 2; pass++) | |
10716 | { | |
10717 | for (i = 0; i < els; i++) | |
10718 | { | |
10719 | unsigned thisarg = types[i]; | |
10720 | unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) | |
10721 | ? modify_types_allowed (key_allowed, thisarg) : thisarg; | |
10722 | enum neon_el_type g_type = inst.vectype.el[i].type; | |
10723 | unsigned g_size = inst.vectype.el[i].size; | |
10724 | ||
10725 | /* Decay more-specific signed & unsigned types to sign-insensitive | |
10726 | integer types if sign-specific variants are unavailable. */ | |
10727 | if ((g_type == NT_signed || g_type == NT_unsigned) | |
10728 | && (types_allowed & N_SU_ALL) == 0) | |
10729 | g_type = NT_integer; | |
10730 | ||
10731 | /* If only untyped args are allowed, decay any more specific types to | |
10732 | them. Some instructions only care about signs for some element | |
10733 | sizes, so handle that properly. */ | |
10734 | if ((g_size == 8 && (types_allowed & N_8) != 0) | |
10735 | || (g_size == 16 && (types_allowed & N_16) != 0) | |
10736 | || (g_size == 32 && (types_allowed & N_32) != 0) | |
10737 | || (g_size == 64 && (types_allowed & N_64) != 0)) | |
10738 | g_type = NT_untyped; | |
10739 | ||
10740 | if (pass == 0) | |
10741 | { | |
10742 | if ((thisarg & N_KEY) != 0) | |
10743 | { | |
10744 | k_type = g_type; | |
10745 | k_size = g_size; | |
10746 | key_allowed = thisarg & ~N_KEY; | |
10747 | } | |
10748 | } | |
10749 | else | |
10750 | { | |
037e8744 JB |
10751 | if ((thisarg & N_VFP) != 0) |
10752 | { | |
10753 | enum neon_shape_el regshape = neon_shape_tab[ns].el[i]; | |
10754 | unsigned regwidth = neon_shape_el_size[regshape], match; | |
10755 | ||
10756 | /* In VFP mode, operands must match register widths. If we | |
10757 | have a key operand, use its width, else use the width of | |
10758 | the current operand. */ | |
10759 | if (k_size != -1u) | |
10760 | match = k_size; | |
10761 | else | |
10762 | match = g_size; | |
10763 | ||
10764 | if (regwidth != match) | |
10765 | { | |
10766 | first_error (_("operand size must match register width")); | |
10767 | return badtype; | |
10768 | } | |
10769 | } | |
10770 | ||
5287ad62 JB |
10771 | if ((thisarg & N_EQK) == 0) |
10772 | { | |
10773 | unsigned given_type = type_chk_of_el_type (g_type, g_size); | |
10774 | ||
10775 | if ((given_type & types_allowed) == 0) | |
10776 | { | |
dcbf9037 | 10777 | first_error (_("bad type in Neon instruction")); |
5287ad62 JB |
10778 | return badtype; |
10779 | } | |
10780 | } | |
10781 | else | |
10782 | { | |
10783 | enum neon_el_type mod_k_type = k_type; | |
10784 | unsigned mod_k_size = k_size; | |
10785 | neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); | |
10786 | if (g_type != mod_k_type || g_size != mod_k_size) | |
10787 | { | |
dcbf9037 | 10788 | first_error (_("inconsistent types in Neon instruction")); |
5287ad62 JB |
10789 | return badtype; |
10790 | } | |
10791 | } | |
10792 | } | |
10793 | } | |
10794 | } | |
10795 | ||
10796 | return inst.vectype.el[key_el]; | |
10797 | } | |
10798 | ||
037e8744 | 10799 | /* Neon-style VFP instruction forwarding. */ |
5287ad62 | 10800 | |
037e8744 JB |
10801 | /* Thumb VFP instructions have 0xE in the condition field. */ |
10802 | ||
10803 | static void | |
10804 | do_vfp_cond_or_thumb (void) | |
5287ad62 JB |
10805 | { |
10806 | if (thumb_mode) | |
037e8744 | 10807 | inst.instruction |= 0xe0000000; |
5287ad62 | 10808 | else |
037e8744 | 10809 | inst.instruction |= inst.cond << 28; |
5287ad62 JB |
10810 | } |
10811 | ||
037e8744 JB |
10812 | /* Look up and encode a simple mnemonic, for use as a helper function for the |
10813 | Neon-style VFP syntax. This avoids duplication of bits of the insns table, | |
10814 | etc. It is assumed that operand parsing has already been done, and that the | |
10815 | operands are in the form expected by the given opcode (this isn't necessarily | |
10816 | the same as the form in which they were parsed, hence some massaging must | |
10817 | take place before this function is called). | |
10818 | Checks current arch version against that in the looked-up opcode. */ | |
5287ad62 | 10819 | |
037e8744 JB |
10820 | static void |
10821 | do_vfp_nsyn_opcode (const char *opname) | |
5287ad62 | 10822 | { |
037e8744 JB |
10823 | const struct asm_opcode *opcode; |
10824 | ||
10825 | opcode = hash_find (arm_ops_hsh, opname); | |
5287ad62 | 10826 | |
037e8744 JB |
10827 | if (!opcode) |
10828 | abort (); | |
5287ad62 | 10829 | |
037e8744 JB |
10830 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, |
10831 | thumb_mode ? *opcode->tvariant : *opcode->avariant), | |
10832 | _(BAD_FPU)); | |
5287ad62 | 10833 | |
037e8744 JB |
10834 | if (thumb_mode) |
10835 | { | |
10836 | inst.instruction = opcode->tvalue; | |
10837 | opcode->tencode (); | |
10838 | } | |
10839 | else | |
10840 | { | |
10841 | inst.instruction = (inst.cond << 28) | opcode->avalue; | |
10842 | opcode->aencode (); | |
10843 | } | |
10844 | } | |
5287ad62 JB |
10845 | |
10846 | static void | |
037e8744 | 10847 | do_vfp_nsyn_add_sub (enum neon_shape rs) |
5287ad62 | 10848 | { |
037e8744 JB |
10849 | int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; |
10850 | ||
10851 | if (rs == NS_FFF) | |
10852 | { | |
10853 | if (is_add) | |
10854 | do_vfp_nsyn_opcode ("fadds"); | |
10855 | else | |
10856 | do_vfp_nsyn_opcode ("fsubs"); | |
10857 | } | |
10858 | else | |
10859 | { | |
10860 | if (is_add) | |
10861 | do_vfp_nsyn_opcode ("faddd"); | |
10862 | else | |
10863 | do_vfp_nsyn_opcode ("fsubd"); | |
10864 | } | |
10865 | } | |
10866 | ||
10867 | /* Check operand types to see if this is a VFP instruction, and if so call | |
10868 | PFN (). */ | |
10869 | ||
10870 | static int | |
10871 | try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) | |
10872 | { | |
10873 | enum neon_shape rs; | |
10874 | struct neon_type_el et; | |
10875 | ||
10876 | switch (args) | |
10877 | { | |
10878 | case 2: | |
10879 | rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
10880 | et = neon_check_type (2, rs, | |
10881 | N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
10882 | break; | |
10883 | ||
10884 | case 3: | |
10885 | rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
10886 | et = neon_check_type (3, rs, | |
10887 | N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
10888 | break; | |
10889 | ||
10890 | default: | |
10891 | abort (); | |
10892 | } | |
10893 | ||
10894 | if (et.type != NT_invtype) | |
10895 | { | |
10896 | pfn (rs); | |
10897 | return SUCCESS; | |
10898 | } | |
10899 | else | |
10900 | inst.error = NULL; | |
10901 | ||
10902 | return FAIL; | |
10903 | } | |
10904 | ||
10905 | static void | |
10906 | do_vfp_nsyn_mla_mls (enum neon_shape rs) | |
10907 | { | |
10908 | int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; | |
10909 | ||
10910 | if (rs == NS_FFF) | |
10911 | { | |
10912 | if (is_mla) | |
10913 | do_vfp_nsyn_opcode ("fmacs"); | |
10914 | else | |
10915 | do_vfp_nsyn_opcode ("fmscs"); | |
10916 | } | |
10917 | else | |
10918 | { | |
10919 | if (is_mla) | |
10920 | do_vfp_nsyn_opcode ("fmacd"); | |
10921 | else | |
10922 | do_vfp_nsyn_opcode ("fmscd"); | |
10923 | } | |
10924 | } | |
10925 | ||
10926 | static void | |
10927 | do_vfp_nsyn_mul (enum neon_shape rs) | |
10928 | { | |
10929 | if (rs == NS_FFF) | |
10930 | do_vfp_nsyn_opcode ("fmuls"); | |
10931 | else | |
10932 | do_vfp_nsyn_opcode ("fmuld"); | |
10933 | } | |
10934 | ||
10935 | static void | |
10936 | do_vfp_nsyn_abs_neg (enum neon_shape rs) | |
10937 | { | |
10938 | int is_neg = (inst.instruction & 0x80) != 0; | |
10939 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); | |
10940 | ||
10941 | if (rs == NS_FF) | |
10942 | { | |
10943 | if (is_neg) | |
10944 | do_vfp_nsyn_opcode ("fnegs"); | |
10945 | else | |
10946 | do_vfp_nsyn_opcode ("fabss"); | |
10947 | } | |
10948 | else | |
10949 | { | |
10950 | if (is_neg) | |
10951 | do_vfp_nsyn_opcode ("fnegd"); | |
10952 | else | |
10953 | do_vfp_nsyn_opcode ("fabsd"); | |
10954 | } | |
10955 | } | |
10956 | ||
10957 | /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision | |
10958 | insns belong to Neon, and are handled elsewhere. */ | |
10959 | ||
10960 | static void | |
10961 | do_vfp_nsyn_ldm_stm (int is_dbmode) | |
10962 | { | |
10963 | int is_ldm = (inst.instruction & (1 << 20)) != 0; | |
10964 | if (is_ldm) | |
10965 | { | |
10966 | if (is_dbmode) | |
10967 | do_vfp_nsyn_opcode ("fldmdbs"); | |
10968 | else | |
10969 | do_vfp_nsyn_opcode ("fldmias"); | |
10970 | } | |
10971 | else | |
10972 | { | |
10973 | if (is_dbmode) | |
10974 | do_vfp_nsyn_opcode ("fstmdbs"); | |
10975 | else | |
10976 | do_vfp_nsyn_opcode ("fstmias"); | |
10977 | } | |
10978 | } | |
10979 | ||
037e8744 JB |
10980 | static void |
10981 | do_vfp_nsyn_sqrt (void) | |
10982 | { | |
10983 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
10984 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
10985 | ||
10986 | if (rs == NS_FF) | |
10987 | do_vfp_nsyn_opcode ("fsqrts"); | |
10988 | else | |
10989 | do_vfp_nsyn_opcode ("fsqrtd"); | |
10990 | } | |
10991 | ||
10992 | static void | |
10993 | do_vfp_nsyn_div (void) | |
10994 | { | |
10995 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
10996 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
10997 | N_F32 | N_F64 | N_KEY | N_VFP); | |
10998 | ||
10999 | if (rs == NS_FFF) | |
11000 | do_vfp_nsyn_opcode ("fdivs"); | |
11001 | else | |
11002 | do_vfp_nsyn_opcode ("fdivd"); | |
11003 | } | |
11004 | ||
11005 | static void | |
11006 | do_vfp_nsyn_nmul (void) | |
11007 | { | |
11008 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
11009 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
11010 | N_F32 | N_F64 | N_KEY | N_VFP); | |
11011 | ||
11012 | if (rs == NS_FFF) | |
11013 | { | |
11014 | inst.instruction = NEON_ENC_SINGLE (inst.instruction); | |
11015 | do_vfp_sp_dyadic (); | |
11016 | } | |
11017 | else | |
11018 | { | |
11019 | inst.instruction = NEON_ENC_DOUBLE (inst.instruction); | |
11020 | do_vfp_dp_rd_rn_rm (); | |
11021 | } | |
11022 | do_vfp_cond_or_thumb (); | |
11023 | } | |
11024 | ||
11025 | static void | |
11026 | do_vfp_nsyn_cmp (void) | |
11027 | { | |
11028 | if (inst.operands[1].isreg) | |
11029 | { | |
11030 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
11031 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
11032 | ||
11033 | if (rs == NS_FF) | |
11034 | { | |
11035 | inst.instruction = NEON_ENC_SINGLE (inst.instruction); | |
11036 | do_vfp_sp_monadic (); | |
11037 | } | |
11038 | else | |
11039 | { | |
11040 | inst.instruction = NEON_ENC_DOUBLE (inst.instruction); | |
11041 | do_vfp_dp_rd_rm (); | |
11042 | } | |
11043 | } | |
11044 | else | |
11045 | { | |
11046 | enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); | |
11047 | neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); | |
11048 | ||
11049 | switch (inst.instruction & 0x0fffffff) | |
11050 | { | |
11051 | case N_MNEM_vcmp: | |
11052 | inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; | |
11053 | break; | |
11054 | case N_MNEM_vcmpe: | |
11055 | inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; | |
11056 | break; | |
11057 | default: | |
11058 | abort (); | |
11059 | } | |
11060 | ||
11061 | if (rs == NS_FI) | |
11062 | { | |
11063 | inst.instruction = NEON_ENC_SINGLE (inst.instruction); | |
11064 | do_vfp_sp_compare_z (); | |
11065 | } | |
11066 | else | |
11067 | { | |
11068 | inst.instruction = NEON_ENC_DOUBLE (inst.instruction); | |
11069 | do_vfp_dp_rd (); | |
11070 | } | |
11071 | } | |
11072 | do_vfp_cond_or_thumb (); | |
11073 | } | |
11074 | ||
11075 | static void | |
11076 | nsyn_insert_sp (void) | |
11077 | { | |
11078 | inst.operands[1] = inst.operands[0]; | |
11079 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
11080 | inst.operands[0].reg = 13; | |
11081 | inst.operands[0].isreg = 1; | |
11082 | inst.operands[0].writeback = 1; | |
11083 | inst.operands[0].present = 1; | |
11084 | } | |
11085 | ||
11086 | static void | |
11087 | do_vfp_nsyn_push (void) | |
11088 | { | |
11089 | nsyn_insert_sp (); | |
11090 | if (inst.operands[1].issingle) | |
11091 | do_vfp_nsyn_opcode ("fstmdbs"); | |
11092 | else | |
11093 | do_vfp_nsyn_opcode ("fstmdbd"); | |
11094 | } | |
11095 | ||
11096 | static void | |
11097 | do_vfp_nsyn_pop (void) | |
11098 | { | |
11099 | nsyn_insert_sp (); | |
11100 | if (inst.operands[1].issingle) | |
11101 | do_vfp_nsyn_opcode ("fldmdbs"); | |
11102 | else | |
11103 | do_vfp_nsyn_opcode ("fldmdbd"); | |
11104 | } | |
11105 | ||
11106 | /* Fix up Neon data-processing instructions, ORing in the correct bits for | |
11107 | ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ | |
11108 | ||
11109 | static unsigned | |
11110 | neon_dp_fixup (unsigned i) | |
11111 | { | |
11112 | if (thumb_mode) | |
11113 | { | |
11114 | /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ | |
11115 | if (i & (1 << 24)) | |
11116 | i |= 1 << 28; | |
11117 | ||
11118 | i &= ~(1 << 24); | |
11119 | ||
11120 | i |= 0xef000000; | |
11121 | } | |
11122 | else | |
11123 | i |= 0xf2000000; | |
11124 | ||
11125 | return i; | |
11126 | } | |
11127 | ||
11128 | /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 | |
11129 | (0, 1, 2, 3). */ | |
11130 | ||
11131 | static unsigned | |
11132 | neon_logbits (unsigned x) | |
11133 | { | |
11134 | return ffs (x) - 4; | |
11135 | } | |
11136 | ||
11137 | #define LOW4(R) ((R) & 0xf) | |
11138 | #define HI1(R) (((R) >> 4) & 1) | |
11139 | ||
11140 | /* Encode insns with bit pattern: | |
11141 | ||
11142 | |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
11143 | | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | | |
11144 | ||
11145 | SIZE is passed in bits. -1 means size field isn't changed, in case it has a | |
11146 | different meaning for some instruction. */ | |
11147 | ||
11148 | static void | |
11149 | neon_three_same (int isquad, int ubit, int size) | |
11150 | { | |
11151 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
11152 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
11153 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
11154 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
11155 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
11156 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
11157 | inst.instruction |= (isquad != 0) << 6; | |
11158 | inst.instruction |= (ubit != 0) << 24; | |
11159 | if (size != -1) | |
11160 | inst.instruction |= neon_logbits (size) << 20; | |
11161 | ||
11162 | inst.instruction = neon_dp_fixup (inst.instruction); | |
11163 | } | |
11164 | ||
11165 | /* Encode instructions of the form: | |
11166 | ||
11167 | |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| | |
11168 | | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | | |
5287ad62 JB |
11169 | |
11170 | Don't write size if SIZE == -1. */ | |
11171 | ||
11172 | static void | |
11173 | neon_two_same (int qbit, int ubit, int size) | |
11174 | { | |
11175 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
11176 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
11177 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
11178 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
11179 | inst.instruction |= (qbit != 0) << 6; | |
11180 | inst.instruction |= (ubit != 0) << 24; | |
11181 | ||
11182 | if (size != -1) | |
11183 | inst.instruction |= neon_logbits (size) << 18; | |
11184 | ||
11185 | inst.instruction = neon_dp_fixup (inst.instruction); | |
11186 | } | |
11187 | ||
11188 | /* Neon instruction encoders, in approximate order of appearance. */ | |
11189 | ||
11190 | static void | |
11191 | do_neon_dyadic_i_su (void) | |
11192 | { | |
037e8744 | 11193 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
11194 | struct neon_type_el et = neon_check_type (3, rs, |
11195 | N_EQK, N_EQK, N_SU_32 | N_KEY); | |
037e8744 | 11196 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
11197 | } |
11198 | ||
11199 | static void | |
11200 | do_neon_dyadic_i64_su (void) | |
11201 | { | |
037e8744 | 11202 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
11203 | struct neon_type_el et = neon_check_type (3, rs, |
11204 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
037e8744 | 11205 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
11206 | } |
11207 | ||
11208 | static void | |
11209 | neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, | |
11210 | unsigned immbits) | |
11211 | { | |
11212 | unsigned size = et.size >> 3; | |
11213 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
11214 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
11215 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
11216 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
11217 | inst.instruction |= (isquad != 0) << 6; | |
11218 | inst.instruction |= immbits << 16; | |
11219 | inst.instruction |= (size >> 3) << 7; | |
11220 | inst.instruction |= (size & 0x7) << 19; | |
11221 | if (write_ubit) | |
11222 | inst.instruction |= (uval != 0) << 24; | |
11223 | ||
11224 | inst.instruction = neon_dp_fixup (inst.instruction); | |
11225 | } | |
11226 | ||
11227 | static void | |
11228 | do_neon_shl_imm (void) | |
11229 | { | |
11230 | if (!inst.operands[2].isreg) | |
11231 | { | |
037e8744 | 11232 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
11233 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); |
11234 | inst.instruction = NEON_ENC_IMMED (inst.instruction); | |
037e8744 | 11235 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm); |
5287ad62 JB |
11236 | } |
11237 | else | |
11238 | { | |
037e8744 | 11239 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
11240 | struct neon_type_el et = neon_check_type (3, rs, |
11241 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
11242 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
037e8744 | 11243 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
11244 | } |
11245 | } | |
11246 | ||
11247 | static void | |
11248 | do_neon_qshl_imm (void) | |
11249 | { | |
11250 | if (!inst.operands[2].isreg) | |
11251 | { | |
037e8744 | 11252 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
11253 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
11254 | inst.instruction = NEON_ENC_IMMED (inst.instruction); | |
037e8744 | 11255 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
11256 | inst.operands[2].imm); |
11257 | } | |
11258 | else | |
11259 | { | |
037e8744 | 11260 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
11261 | struct neon_type_el et = neon_check_type (3, rs, |
11262 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
11263 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
037e8744 | 11264 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
11265 | } |
11266 | } | |
11267 | ||
11268 | static int | |
11269 | neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) | |
11270 | { | |
11271 | /* Handle .I8 and .I64 as pseudo-instructions. */ | |
11272 | switch (size) | |
11273 | { | |
11274 | case 8: | |
11275 | /* Unfortunately, this will make everything apart from zero out-of-range. | |
11276 | FIXME is this the intended semantics? There doesn't seem much point in | |
11277 | accepting .I8 if so. */ | |
11278 | immediate |= immediate << 8; | |
11279 | size = 16; | |
11280 | break; | |
11281 | case 64: | |
11282 | /* Similarly, anything other than zero will be replicated in bits [63:32], | |
11283 | which probably isn't want we want if we specified .I64. */ | |
11284 | if (immediate != 0) | |
11285 | goto bad_immediate; | |
11286 | size = 32; | |
11287 | break; | |
11288 | default: ; | |
11289 | } | |
11290 | ||
11291 | if (immediate == (immediate & 0x000000ff)) | |
11292 | { | |
11293 | *immbits = immediate; | |
11294 | return (size == 16) ? 0x9 : 0x1; | |
11295 | } | |
11296 | else if (immediate == (immediate & 0x0000ff00)) | |
11297 | { | |
11298 | *immbits = immediate >> 8; | |
11299 | return (size == 16) ? 0xb : 0x3; | |
11300 | } | |
11301 | else if (immediate == (immediate & 0x00ff0000)) | |
11302 | { | |
11303 | *immbits = immediate >> 16; | |
11304 | return 0x5; | |
11305 | } | |
11306 | else if (immediate == (immediate & 0xff000000)) | |
11307 | { | |
11308 | *immbits = immediate >> 24; | |
11309 | return 0x7; | |
11310 | } | |
11311 | ||
11312 | bad_immediate: | |
dcbf9037 | 11313 | first_error (_("immediate value out of range")); |
5287ad62 JB |
11314 | return FAIL; |
11315 | } | |
11316 | ||
11317 | /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits | |
11318 | A, B, C, D. */ | |
11319 | ||
11320 | static int | |
11321 | neon_bits_same_in_bytes (unsigned imm) | |
11322 | { | |
11323 | return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) | |
11324 | && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) | |
11325 | && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) | |
11326 | && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); | |
11327 | } | |
11328 | ||
11329 | /* For immediate of above form, return 0bABCD. */ | |
11330 | ||
11331 | static unsigned | |
11332 | neon_squash_bits (unsigned imm) | |
11333 | { | |
11334 | return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) | |
11335 | | ((imm & 0x01000000) >> 21); | |
11336 | } | |
11337 | ||
136da414 | 11338 | /* Compress quarter-float representation to 0b...000 abcdefgh. */ |
5287ad62 JB |
11339 | |
11340 | static unsigned | |
11341 | neon_qfloat_bits (unsigned imm) | |
11342 | { | |
136da414 | 11343 | return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); |
5287ad62 JB |
11344 | } |
11345 | ||
11346 | /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into | |
11347 | the instruction. *OP is passed as the initial value of the op field, and | |
11348 | may be set to a different value depending on the constant (i.e. | |
11349 | "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not | |
11350 | MVN). */ | |
11351 | ||
11352 | static int | |
11353 | neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, unsigned *immbits, | |
136da414 | 11354 | int *op, int size, enum neon_el_type type) |
5287ad62 | 11355 | { |
136da414 JB |
11356 | if (type == NT_float && is_quarter_float (immlo) && immhi == 0) |
11357 | { | |
11358 | if (size != 32 || *op == 1) | |
11359 | return FAIL; | |
11360 | *immbits = neon_qfloat_bits (immlo); | |
11361 | return 0xf; | |
11362 | } | |
11363 | else if (size == 64 && neon_bits_same_in_bytes (immhi) | |
5287ad62 JB |
11364 | && neon_bits_same_in_bytes (immlo)) |
11365 | { | |
11366 | /* Check this one first so we don't have to bother with immhi in later | |
11367 | tests. */ | |
11368 | if (*op == 1) | |
11369 | return FAIL; | |
11370 | *immbits = (neon_squash_bits (immhi) << 4) | neon_squash_bits (immlo); | |
11371 | *op = 1; | |
11372 | return 0xe; | |
11373 | } | |
11374 | else if (immhi != 0) | |
11375 | return FAIL; | |
11376 | else if (immlo == (immlo & 0x000000ff)) | |
11377 | { | |
11378 | /* 64-bit case was already handled. Don't allow MVN with 8-bit | |
11379 | immediate. */ | |
11380 | if ((size != 8 && size != 16 && size != 32) | |
11381 | || (size == 8 && *op == 1)) | |
11382 | return FAIL; | |
11383 | *immbits = immlo; | |
11384 | return (size == 8) ? 0xe : (size == 16) ? 0x8 : 0x0; | |
11385 | } | |
11386 | else if (immlo == (immlo & 0x0000ff00)) | |
11387 | { | |
11388 | if (size != 16 && size != 32) | |
11389 | return FAIL; | |
11390 | *immbits = immlo >> 8; | |
11391 | return (size == 16) ? 0xa : 0x2; | |
11392 | } | |
11393 | else if (immlo == (immlo & 0x00ff0000)) | |
11394 | { | |
11395 | if (size != 32) | |
11396 | return FAIL; | |
11397 | *immbits = immlo >> 16; | |
11398 | return 0x4; | |
11399 | } | |
11400 | else if (immlo == (immlo & 0xff000000)) | |
11401 | { | |
11402 | if (size != 32) | |
11403 | return FAIL; | |
11404 | *immbits = immlo >> 24; | |
11405 | return 0x6; | |
11406 | } | |
11407 | else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) | |
11408 | { | |
11409 | if (size != 32) | |
11410 | return FAIL; | |
11411 | *immbits = (immlo >> 8) & 0xff; | |
11412 | return 0xc; | |
11413 | } | |
11414 | else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) | |
11415 | { | |
11416 | if (size != 32) | |
11417 | return FAIL; | |
11418 | *immbits = (immlo >> 16) & 0xff; | |
11419 | return 0xd; | |
11420 | } | |
5287ad62 JB |
11421 | |
11422 | return FAIL; | |
11423 | } | |
11424 | ||
11425 | /* Write immediate bits [7:0] to the following locations: | |
11426 | ||
11427 | |28/24|23 19|18 16|15 4|3 0| | |
11428 | | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| | |
11429 | ||
11430 | This function is used by VMOV/VMVN/VORR/VBIC. */ | |
11431 | ||
11432 | static void | |
11433 | neon_write_immbits (unsigned immbits) | |
11434 | { | |
11435 | inst.instruction |= immbits & 0xf; | |
11436 | inst.instruction |= ((immbits >> 4) & 0x7) << 16; | |
11437 | inst.instruction |= ((immbits >> 7) & 0x1) << 24; | |
11438 | } | |
11439 | ||
11440 | /* Invert low-order SIZE bits of XHI:XLO. */ | |
11441 | ||
11442 | static void | |
11443 | neon_invert_size (unsigned *xlo, unsigned *xhi, int size) | |
11444 | { | |
11445 | unsigned immlo = xlo ? *xlo : 0; | |
11446 | unsigned immhi = xhi ? *xhi : 0; | |
11447 | ||
11448 | switch (size) | |
11449 | { | |
11450 | case 8: | |
11451 | immlo = (~immlo) & 0xff; | |
11452 | break; | |
11453 | ||
11454 | case 16: | |
11455 | immlo = (~immlo) & 0xffff; | |
11456 | break; | |
11457 | ||
11458 | case 64: | |
11459 | immhi = (~immhi) & 0xffffffff; | |
11460 | /* fall through. */ | |
11461 | ||
11462 | case 32: | |
11463 | immlo = (~immlo) & 0xffffffff; | |
11464 | break; | |
11465 | ||
11466 | default: | |
11467 | abort (); | |
11468 | } | |
11469 | ||
11470 | if (xlo) | |
11471 | *xlo = immlo; | |
11472 | ||
11473 | if (xhi) | |
11474 | *xhi = immhi; | |
11475 | } | |
11476 | ||
11477 | static void | |
11478 | do_neon_logic (void) | |
11479 | { | |
11480 | if (inst.operands[2].present && inst.operands[2].isreg) | |
11481 | { | |
037e8744 | 11482 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
11483 | neon_check_type (3, rs, N_IGNORE_TYPE); |
11484 | /* U bit and size field were set as part of the bitmask. */ | |
11485 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
037e8744 | 11486 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
11487 | } |
11488 | else | |
11489 | { | |
037e8744 JB |
11490 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
11491 | struct neon_type_el et = neon_check_type (2, rs, | |
11492 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
5287ad62 JB |
11493 | enum neon_opc opcode = inst.instruction & 0x0fffffff; |
11494 | unsigned immbits; | |
11495 | int cmode; | |
11496 | ||
11497 | if (et.type == NT_invtype) | |
11498 | return; | |
11499 | ||
11500 | inst.instruction = NEON_ENC_IMMED (inst.instruction); | |
11501 | ||
11502 | switch (opcode) | |
11503 | { | |
11504 | case N_MNEM_vbic: | |
11505 | cmode = neon_cmode_for_logic_imm (inst.operands[1].imm, &immbits, | |
11506 | et.size); | |
11507 | break; | |
11508 | ||
11509 | case N_MNEM_vorr: | |
11510 | cmode = neon_cmode_for_logic_imm (inst.operands[1].imm, &immbits, | |
11511 | et.size); | |
11512 | break; | |
11513 | ||
11514 | case N_MNEM_vand: | |
11515 | /* Pseudo-instruction for VBIC. */ | |
11516 | immbits = inst.operands[1].imm; | |
11517 | neon_invert_size (&immbits, 0, et.size); | |
11518 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
11519 | break; | |
11520 | ||
11521 | case N_MNEM_vorn: | |
11522 | /* Pseudo-instruction for VORR. */ | |
11523 | immbits = inst.operands[1].imm; | |
11524 | neon_invert_size (&immbits, 0, et.size); | |
11525 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
11526 | break; | |
11527 | ||
11528 | default: | |
11529 | abort (); | |
11530 | } | |
11531 | ||
11532 | if (cmode == FAIL) | |
11533 | return; | |
11534 | ||
037e8744 | 11535 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
11536 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
11537 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
11538 | inst.instruction |= cmode << 8; | |
11539 | neon_write_immbits (immbits); | |
11540 | ||
11541 | inst.instruction = neon_dp_fixup (inst.instruction); | |
11542 | } | |
11543 | } | |
11544 | ||
11545 | static void | |
11546 | do_neon_bitfield (void) | |
11547 | { | |
037e8744 | 11548 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 11549 | neon_check_type (3, rs, N_IGNORE_TYPE); |
037e8744 | 11550 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
11551 | } |
11552 | ||
11553 | static void | |
dcbf9037 JB |
11554 | neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, |
11555 | unsigned destbits) | |
5287ad62 | 11556 | { |
037e8744 | 11557 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 JB |
11558 | struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, |
11559 | types | N_KEY); | |
5287ad62 JB |
11560 | if (et.type == NT_float) |
11561 | { | |
11562 | inst.instruction = NEON_ENC_FLOAT (inst.instruction); | |
037e8744 | 11563 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
11564 | } |
11565 | else | |
11566 | { | |
11567 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
037e8744 | 11568 | neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); |
5287ad62 JB |
11569 | } |
11570 | } | |
11571 | ||
11572 | static void | |
11573 | do_neon_dyadic_if_su (void) | |
11574 | { | |
dcbf9037 | 11575 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
11576 | } |
11577 | ||
11578 | static void | |
11579 | do_neon_dyadic_if_su_d (void) | |
11580 | { | |
11581 | /* This version only allow D registers, but that constraint is enforced during | |
11582 | operand parsing so we don't need to do anything extra here. */ | |
dcbf9037 | 11583 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
11584 | } |
11585 | ||
11586 | static void | |
11587 | do_neon_dyadic_if_i (void) | |
11588 | { | |
dcbf9037 | 11589 | neon_dyadic_misc (NT_unsigned, N_IF_32, 0); |
5287ad62 JB |
11590 | } |
11591 | ||
11592 | static void | |
11593 | do_neon_dyadic_if_i_d (void) | |
11594 | { | |
dcbf9037 | 11595 | neon_dyadic_misc (NT_unsigned, N_IF_32, 0); |
5287ad62 JB |
11596 | } |
11597 | ||
037e8744 JB |
11598 | enum vfp_or_neon_is_neon_bits |
11599 | { | |
11600 | NEON_CHECK_CC = 1, | |
11601 | NEON_CHECK_ARCH = 2 | |
11602 | }; | |
11603 | ||
11604 | /* Call this function if an instruction which may have belonged to the VFP or | |
11605 | Neon instruction sets, but turned out to be a Neon instruction (due to the | |
11606 | operand types involved, etc.). We have to check and/or fix-up a couple of | |
11607 | things: | |
11608 | ||
11609 | - Make sure the user hasn't attempted to make a Neon instruction | |
11610 | conditional. | |
11611 | - Alter the value in the condition code field if necessary. | |
11612 | - Make sure that the arch supports Neon instructions. | |
11613 | ||
11614 | Which of these operations take place depends on bits from enum | |
11615 | vfp_or_neon_is_neon_bits. | |
11616 | ||
11617 | WARNING: This function has side effects! If NEON_CHECK_CC is used and the | |
11618 | current instruction's condition is COND_ALWAYS, the condition field is | |
11619 | changed to inst.uncond_value. This is necessary because instructions shared | |
11620 | between VFP and Neon may be conditional for the VFP variants only, and the | |
11621 | unconditional Neon version must have, e.g., 0xF in the condition field. */ | |
11622 | ||
11623 | static int | |
11624 | vfp_or_neon_is_neon (unsigned check) | |
11625 | { | |
11626 | /* Conditions are always legal in Thumb mode (IT blocks). */ | |
11627 | if (!thumb_mode && (check & NEON_CHECK_CC)) | |
11628 | { | |
11629 | if (inst.cond != COND_ALWAYS) | |
11630 | { | |
11631 | first_error (_(BAD_COND)); | |
11632 | return FAIL; | |
11633 | } | |
11634 | if (inst.uncond_value != -1) | |
11635 | inst.instruction |= inst.uncond_value << 28; | |
11636 | } | |
11637 | ||
11638 | if ((check & NEON_CHECK_ARCH) | |
11639 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) | |
11640 | { | |
11641 | first_error (_(BAD_FPU)); | |
11642 | return FAIL; | |
11643 | } | |
11644 | ||
11645 | return SUCCESS; | |
11646 | } | |
11647 | ||
5287ad62 JB |
11648 | static void |
11649 | do_neon_addsub_if_i (void) | |
11650 | { | |
037e8744 JB |
11651 | if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) |
11652 | return; | |
11653 | ||
11654 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
11655 | return; | |
11656 | ||
5287ad62 JB |
11657 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
11658 | affected if we specify unsigned args. */ | |
dcbf9037 | 11659 | neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); |
5287ad62 JB |
11660 | } |
11661 | ||
11662 | /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the | |
11663 | result to be: | |
11664 | V<op> A,B (A is operand 0, B is operand 2) | |
11665 | to mean: | |
11666 | V<op> A,B,A | |
11667 | not: | |
11668 | V<op> A,B,B | |
11669 | so handle that case specially. */ | |
11670 | ||
11671 | static void | |
11672 | neon_exchange_operands (void) | |
11673 | { | |
11674 | void *scratch = alloca (sizeof (inst.operands[0])); | |
11675 | if (inst.operands[1].present) | |
11676 | { | |
11677 | /* Swap operands[1] and operands[2]. */ | |
11678 | memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); | |
11679 | inst.operands[1] = inst.operands[2]; | |
11680 | memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); | |
11681 | } | |
11682 | else | |
11683 | { | |
11684 | inst.operands[1] = inst.operands[2]; | |
11685 | inst.operands[2] = inst.operands[0]; | |
11686 | } | |
11687 | } | |
11688 | ||
11689 | static void | |
11690 | neon_compare (unsigned regtypes, unsigned immtypes, int invert) | |
11691 | { | |
11692 | if (inst.operands[2].isreg) | |
11693 | { | |
11694 | if (invert) | |
11695 | neon_exchange_operands (); | |
dcbf9037 | 11696 | neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); |
5287ad62 JB |
11697 | } |
11698 | else | |
11699 | { | |
037e8744 | 11700 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
dcbf9037 JB |
11701 | struct neon_type_el et = neon_check_type (2, rs, |
11702 | N_EQK | N_SIZ, immtypes | N_KEY); | |
5287ad62 JB |
11703 | |
11704 | inst.instruction = NEON_ENC_IMMED (inst.instruction); | |
11705 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
11706 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
11707 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
11708 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 11709 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
11710 | inst.instruction |= (et.type == NT_float) << 10; |
11711 | inst.instruction |= neon_logbits (et.size) << 18; | |
11712 | ||
11713 | inst.instruction = neon_dp_fixup (inst.instruction); | |
11714 | } | |
11715 | } | |
11716 | ||
11717 | static void | |
11718 | do_neon_cmp (void) | |
11719 | { | |
11720 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); | |
11721 | } | |
11722 | ||
11723 | static void | |
11724 | do_neon_cmp_inv (void) | |
11725 | { | |
11726 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); | |
11727 | } | |
11728 | ||
11729 | static void | |
11730 | do_neon_ceq (void) | |
11731 | { | |
11732 | neon_compare (N_IF_32, N_IF_32, FALSE); | |
11733 | } | |
11734 | ||
11735 | /* For multiply instructions, we have the possibility of 16-bit or 32-bit | |
11736 | scalars, which are encoded in 5 bits, M : Rm. | |
11737 | For 16-bit scalars, the register is encoded in Rm[2:0] and the index in | |
11738 | M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the | |
11739 | index in M. */ | |
11740 | ||
11741 | static unsigned | |
11742 | neon_scalar_for_mul (unsigned scalar, unsigned elsize) | |
11743 | { | |
dcbf9037 JB |
11744 | unsigned regno = NEON_SCALAR_REG (scalar); |
11745 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
5287ad62 JB |
11746 | |
11747 | switch (elsize) | |
11748 | { | |
11749 | case 16: | |
11750 | if (regno > 7 || elno > 3) | |
11751 | goto bad_scalar; | |
11752 | return regno | (elno << 3); | |
11753 | ||
11754 | case 32: | |
11755 | if (regno > 15 || elno > 1) | |
11756 | goto bad_scalar; | |
11757 | return regno | (elno << 4); | |
11758 | ||
11759 | default: | |
11760 | bad_scalar: | |
dcbf9037 | 11761 | first_error (_("scalar out of range for multiply instruction")); |
5287ad62 JB |
11762 | } |
11763 | ||
11764 | return 0; | |
11765 | } | |
11766 | ||
11767 | /* Encode multiply / multiply-accumulate scalar instructions. */ | |
11768 | ||
11769 | static void | |
11770 | neon_mul_mac (struct neon_type_el et, int ubit) | |
11771 | { | |
dcbf9037 JB |
11772 | unsigned scalar; |
11773 | ||
11774 | /* Give a more helpful error message if we have an invalid type. */ | |
11775 | if (et.type == NT_invtype) | |
11776 | return; | |
11777 | ||
11778 | scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); | |
5287ad62 JB |
11779 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
11780 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
11781 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
11782 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
11783 | inst.instruction |= LOW4 (scalar); | |
11784 | inst.instruction |= HI1 (scalar) << 5; | |
11785 | inst.instruction |= (et.type == NT_float) << 8; | |
11786 | inst.instruction |= neon_logbits (et.size) << 20; | |
11787 | inst.instruction |= (ubit != 0) << 24; | |
11788 | ||
11789 | inst.instruction = neon_dp_fixup (inst.instruction); | |
11790 | } | |
11791 | ||
11792 | static void | |
11793 | do_neon_mac_maybe_scalar (void) | |
11794 | { | |
037e8744 JB |
11795 | if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) |
11796 | return; | |
11797 | ||
11798 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
11799 | return; | |
11800 | ||
5287ad62 JB |
11801 | if (inst.operands[2].isscalar) |
11802 | { | |
037e8744 | 11803 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
11804 | struct neon_type_el et = neon_check_type (3, rs, |
11805 | N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); | |
11806 | inst.instruction = NEON_ENC_SCALAR (inst.instruction); | |
037e8744 | 11807 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
11808 | } |
11809 | else | |
11810 | do_neon_dyadic_if_i (); | |
11811 | } | |
11812 | ||
11813 | static void | |
11814 | do_neon_tst (void) | |
11815 | { | |
037e8744 | 11816 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
11817 | struct neon_type_el et = neon_check_type (3, rs, |
11818 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
037e8744 | 11819 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
11820 | } |
11821 | ||
11822 | /* VMUL with 3 registers allows the P8 type. The scalar version supports the | |
11823 | same types as the MAC equivalents. The polynomial type for this instruction | |
11824 | is encoded the same as the integer type. */ | |
11825 | ||
11826 | static void | |
11827 | do_neon_mul (void) | |
11828 | { | |
037e8744 JB |
11829 | if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) |
11830 | return; | |
11831 | ||
11832 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
11833 | return; | |
11834 | ||
5287ad62 JB |
11835 | if (inst.operands[2].isscalar) |
11836 | do_neon_mac_maybe_scalar (); | |
11837 | else | |
dcbf9037 | 11838 | neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); |
5287ad62 JB |
11839 | } |
11840 | ||
11841 | static void | |
11842 | do_neon_qdmulh (void) | |
11843 | { | |
11844 | if (inst.operands[2].isscalar) | |
11845 | { | |
037e8744 | 11846 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
11847 | struct neon_type_el et = neon_check_type (3, rs, |
11848 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
11849 | inst.instruction = NEON_ENC_SCALAR (inst.instruction); | |
037e8744 | 11850 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
11851 | } |
11852 | else | |
11853 | { | |
037e8744 | 11854 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
11855 | struct neon_type_el et = neon_check_type (3, rs, |
11856 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
11857 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
11858 | /* The U bit (rounding) comes from bit mask. */ | |
037e8744 | 11859 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
11860 | } |
11861 | } | |
11862 | ||
11863 | static void | |
11864 | do_neon_fcmp_absolute (void) | |
11865 | { | |
037e8744 | 11866 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
11867 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
11868 | /* Size field comes from bit mask. */ | |
037e8744 | 11869 | neon_three_same (neon_quad (rs), 1, -1); |
5287ad62 JB |
11870 | } |
11871 | ||
11872 | static void | |
11873 | do_neon_fcmp_absolute_inv (void) | |
11874 | { | |
11875 | neon_exchange_operands (); | |
11876 | do_neon_fcmp_absolute (); | |
11877 | } | |
11878 | ||
11879 | static void | |
11880 | do_neon_step (void) | |
11881 | { | |
037e8744 | 11882 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 11883 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
037e8744 | 11884 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
11885 | } |
11886 | ||
11887 | static void | |
11888 | do_neon_abs_neg (void) | |
11889 | { | |
037e8744 JB |
11890 | enum neon_shape rs; |
11891 | struct neon_type_el et; | |
11892 | ||
11893 | if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) | |
11894 | return; | |
11895 | ||
11896 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
11897 | return; | |
11898 | ||
11899 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
11900 | et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); | |
11901 | ||
5287ad62 JB |
11902 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
11903 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
11904 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
11905 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 11906 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
11907 | inst.instruction |= (et.type == NT_float) << 10; |
11908 | inst.instruction |= neon_logbits (et.size) << 18; | |
11909 | ||
11910 | inst.instruction = neon_dp_fixup (inst.instruction); | |
11911 | } | |
11912 | ||
11913 | static void | |
11914 | do_neon_sli (void) | |
11915 | { | |
037e8744 | 11916 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
11917 | struct neon_type_el et = neon_check_type (2, rs, |
11918 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
11919 | int imm = inst.operands[2].imm; | |
11920 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
11921 | _("immediate out of range for insert")); | |
037e8744 | 11922 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
11923 | } |
11924 | ||
11925 | static void | |
11926 | do_neon_sri (void) | |
11927 | { | |
037e8744 | 11928 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
11929 | struct neon_type_el et = neon_check_type (2, rs, |
11930 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
11931 | int imm = inst.operands[2].imm; | |
11932 | constraint (imm < 1 || (unsigned)imm > et.size, | |
11933 | _("immediate out of range for insert")); | |
037e8744 | 11934 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); |
5287ad62 JB |
11935 | } |
11936 | ||
11937 | static void | |
11938 | do_neon_qshlu_imm (void) | |
11939 | { | |
037e8744 | 11940 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
11941 | struct neon_type_el et = neon_check_type (2, rs, |
11942 | N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); | |
11943 | int imm = inst.operands[2].imm; | |
11944 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
11945 | _("immediate out of range for shift")); | |
11946 | /* Only encodes the 'U present' variant of the instruction. | |
11947 | In this case, signed types have OP (bit 8) set to 0. | |
11948 | Unsigned types have OP set to 1. */ | |
11949 | inst.instruction |= (et.type == NT_unsigned) << 8; | |
11950 | /* The rest of the bits are the same as other immediate shifts. */ | |
037e8744 | 11951 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
11952 | } |
11953 | ||
11954 | static void | |
11955 | do_neon_qmovn (void) | |
11956 | { | |
11957 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
11958 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
11959 | /* Saturating move where operands can be signed or unsigned, and the | |
11960 | destination has the same signedness. */ | |
11961 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
11962 | if (et.type == NT_unsigned) | |
11963 | inst.instruction |= 0xc0; | |
11964 | else | |
11965 | inst.instruction |= 0x80; | |
11966 | neon_two_same (0, 1, et.size / 2); | |
11967 | } | |
11968 | ||
11969 | static void | |
11970 | do_neon_qmovun (void) | |
11971 | { | |
11972 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
11973 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
11974 | /* Saturating move with unsigned results. Operands must be signed. */ | |
11975 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
11976 | neon_two_same (0, 1, et.size / 2); | |
11977 | } | |
11978 | ||
11979 | static void | |
11980 | do_neon_rshift_sat_narrow (void) | |
11981 | { | |
11982 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
11983 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
11984 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
11985 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
11986 | int imm = inst.operands[2].imm; | |
11987 | /* This gets the bounds check, size encoding and immediate bits calculation | |
11988 | right. */ | |
11989 | et.size /= 2; | |
11990 | ||
11991 | /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for | |
11992 | VQMOVN.I<size> <Dd>, <Qm>. */ | |
11993 | if (imm == 0) | |
11994 | { | |
11995 | inst.operands[2].present = 0; | |
11996 | inst.instruction = N_MNEM_vqmovn; | |
11997 | do_neon_qmovn (); | |
11998 | return; | |
11999 | } | |
12000 | ||
12001 | constraint (imm < 1 || (unsigned)imm > et.size, | |
12002 | _("immediate out of range")); | |
12003 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); | |
12004 | } | |
12005 | ||
12006 | static void | |
12007 | do_neon_rshift_sat_narrow_u (void) | |
12008 | { | |
12009 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
12010 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
12011 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
12012 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
12013 | int imm = inst.operands[2].imm; | |
12014 | /* This gets the bounds check, size encoding and immediate bits calculation | |
12015 | right. */ | |
12016 | et.size /= 2; | |
12017 | ||
12018 | /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for | |
12019 | VQMOVUN.I<size> <Dd>, <Qm>. */ | |
12020 | if (imm == 0) | |
12021 | { | |
12022 | inst.operands[2].present = 0; | |
12023 | inst.instruction = N_MNEM_vqmovun; | |
12024 | do_neon_qmovun (); | |
12025 | return; | |
12026 | } | |
12027 | ||
12028 | constraint (imm < 1 || (unsigned)imm > et.size, | |
12029 | _("immediate out of range")); | |
12030 | /* FIXME: The manual is kind of unclear about what value U should have in | |
12031 | VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it | |
12032 | must be 1. */ | |
12033 | neon_imm_shift (TRUE, 1, 0, et, et.size - imm); | |
12034 | } | |
12035 | ||
12036 | static void | |
12037 | do_neon_movn (void) | |
12038 | { | |
12039 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
12040 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
12041 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
12042 | neon_two_same (0, 1, et.size / 2); | |
12043 | } | |
12044 | ||
12045 | static void | |
12046 | do_neon_rshift_narrow (void) | |
12047 | { | |
12048 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
12049 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
12050 | int imm = inst.operands[2].imm; | |
12051 | /* This gets the bounds check, size encoding and immediate bits calculation | |
12052 | right. */ | |
12053 | et.size /= 2; | |
12054 | ||
12055 | /* If immediate is zero then we are a pseudo-instruction for | |
12056 | VMOVN.I<size> <Dd>, <Qm> */ | |
12057 | if (imm == 0) | |
12058 | { | |
12059 | inst.operands[2].present = 0; | |
12060 | inst.instruction = N_MNEM_vmovn; | |
12061 | do_neon_movn (); | |
12062 | return; | |
12063 | } | |
12064 | ||
12065 | constraint (imm < 1 || (unsigned)imm > et.size, | |
12066 | _("immediate out of range for narrowing operation")); | |
12067 | neon_imm_shift (FALSE, 0, 0, et, et.size - imm); | |
12068 | } | |
12069 | ||
12070 | static void | |
12071 | do_neon_shll (void) | |
12072 | { | |
12073 | /* FIXME: Type checking when lengthening. */ | |
12074 | struct neon_type_el et = neon_check_type (2, NS_QDI, | |
12075 | N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); | |
12076 | unsigned imm = inst.operands[2].imm; | |
12077 | ||
12078 | if (imm == et.size) | |
12079 | { | |
12080 | /* Maximum shift variant. */ | |
12081 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
12082 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12083 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12084 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
12085 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
12086 | inst.instruction |= neon_logbits (et.size) << 18; | |
12087 | ||
12088 | inst.instruction = neon_dp_fixup (inst.instruction); | |
12089 | } | |
12090 | else | |
12091 | { | |
12092 | /* A more-specific type check for non-max versions. */ | |
12093 | et = neon_check_type (2, NS_QDI, | |
12094 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
12095 | inst.instruction = NEON_ENC_IMMED (inst.instruction); | |
12096 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); | |
12097 | } | |
12098 | } | |
12099 | ||
037e8744 | 12100 | /* Check the various types for the VCVT instruction, and return which version |
5287ad62 JB |
12101 | the current instruction is. */ |
12102 | ||
12103 | static int | |
12104 | neon_cvt_flavour (enum neon_shape rs) | |
12105 | { | |
037e8744 JB |
12106 | #define CVT_VAR(C,X,Y) \ |
12107 | et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \ | |
12108 | if (et.type != NT_invtype) \ | |
12109 | { \ | |
12110 | inst.error = NULL; \ | |
12111 | return (C); \ | |
5287ad62 JB |
12112 | } |
12113 | struct neon_type_el et; | |
037e8744 JB |
12114 | unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF |
12115 | || rs == NS_FF) ? N_VFP : 0; | |
12116 | /* The instruction versions which take an immediate take one register | |
12117 | argument, which is extended to the width of the full register. Thus the | |
12118 | "source" and "destination" registers must have the same width. Hack that | |
12119 | here by making the size equal to the key (wider, in this case) operand. */ | |
12120 | unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; | |
5287ad62 JB |
12121 | |
12122 | CVT_VAR (0, N_S32, N_F32); | |
12123 | CVT_VAR (1, N_U32, N_F32); | |
12124 | CVT_VAR (2, N_F32, N_S32); | |
12125 | CVT_VAR (3, N_F32, N_U32); | |
12126 | ||
037e8744 JB |
12127 | whole_reg = N_VFP; |
12128 | ||
12129 | /* VFP instructions. */ | |
12130 | CVT_VAR (4, N_F32, N_F64); | |
12131 | CVT_VAR (5, N_F64, N_F32); | |
12132 | CVT_VAR (6, N_S32, N_F64 | key); | |
12133 | CVT_VAR (7, N_U32, N_F64 | key); | |
12134 | CVT_VAR (8, N_F64 | key, N_S32); | |
12135 | CVT_VAR (9, N_F64 | key, N_U32); | |
12136 | /* VFP instructions with bitshift. */ | |
12137 | CVT_VAR (10, N_F32 | key, N_S16); | |
12138 | CVT_VAR (11, N_F32 | key, N_U16); | |
12139 | CVT_VAR (12, N_F64 | key, N_S16); | |
12140 | CVT_VAR (13, N_F64 | key, N_U16); | |
12141 | CVT_VAR (14, N_S16, N_F32 | key); | |
12142 | CVT_VAR (15, N_U16, N_F32 | key); | |
12143 | CVT_VAR (16, N_S16, N_F64 | key); | |
12144 | CVT_VAR (17, N_U16, N_F64 | key); | |
12145 | ||
5287ad62 JB |
12146 | return -1; |
12147 | #undef CVT_VAR | |
12148 | } | |
12149 | ||
037e8744 JB |
12150 | /* Neon-syntax VFP conversions. */ |
12151 | ||
5287ad62 | 12152 | static void |
037e8744 | 12153 | do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) |
5287ad62 | 12154 | { |
037e8744 JB |
12155 | const char *opname = 0; |
12156 | ||
12157 | if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) | |
5287ad62 | 12158 | { |
037e8744 JB |
12159 | /* Conversions with immediate bitshift. */ |
12160 | const char *enc[] = | |
12161 | { | |
12162 | "ftosls", | |
12163 | "ftouls", | |
12164 | "fsltos", | |
12165 | "fultos", | |
12166 | NULL, | |
12167 | NULL, | |
12168 | "ftosld", | |
12169 | "ftould", | |
12170 | "fsltod", | |
12171 | "fultod", | |
12172 | "fshtos", | |
12173 | "fuhtos", | |
12174 | "fshtod", | |
12175 | "fuhtod", | |
12176 | "ftoshs", | |
12177 | "ftouhs", | |
12178 | "ftoshd", | |
12179 | "ftouhd" | |
12180 | }; | |
12181 | ||
12182 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
12183 | { | |
12184 | opname = enc[flavour]; | |
12185 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
12186 | _("operands 0 and 1 must be the same register")); | |
12187 | inst.operands[1] = inst.operands[2]; | |
12188 | memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); | |
12189 | } | |
5287ad62 JB |
12190 | } |
12191 | else | |
12192 | { | |
037e8744 JB |
12193 | /* Conversions without bitshift. */ |
12194 | const char *enc[] = | |
12195 | { | |
12196 | "ftosis", | |
12197 | "ftouis", | |
12198 | "fsitos", | |
12199 | "fuitos", | |
12200 | "fcvtsd", | |
12201 | "fcvtds", | |
12202 | "ftosid", | |
12203 | "ftouid", | |
12204 | "fsitod", | |
12205 | "fuitod" | |
12206 | }; | |
12207 | ||
12208 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
12209 | opname = enc[flavour]; | |
12210 | } | |
12211 | ||
12212 | if (opname) | |
12213 | do_vfp_nsyn_opcode (opname); | |
12214 | } | |
12215 | ||
12216 | static void | |
12217 | do_vfp_nsyn_cvtz (void) | |
12218 | { | |
12219 | enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); | |
12220 | int flavour = neon_cvt_flavour (rs); | |
12221 | const char *enc[] = | |
12222 | { | |
12223 | "ftosizs", | |
12224 | "ftouizs", | |
12225 | NULL, | |
12226 | NULL, | |
12227 | NULL, | |
12228 | NULL, | |
12229 | "ftosizd", | |
12230 | "ftouizd" | |
12231 | }; | |
12232 | ||
12233 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) | |
12234 | do_vfp_nsyn_opcode (enc[flavour]); | |
12235 | } | |
12236 | ||
12237 | static void | |
12238 | do_neon_cvt (void) | |
12239 | { | |
12240 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, | |
12241 | NS_FD, NS_DF, NS_FF, NS_NULL); | |
12242 | int flavour = neon_cvt_flavour (rs); | |
12243 | ||
12244 | /* VFP rather than Neon conversions. */ | |
12245 | if (flavour >= 4) | |
12246 | { | |
12247 | do_vfp_nsyn_cvt (rs, flavour); | |
12248 | return; | |
12249 | } | |
12250 | ||
12251 | switch (rs) | |
12252 | { | |
12253 | case NS_DDI: | |
12254 | case NS_QQI: | |
12255 | { | |
12256 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
12257 | return; | |
12258 | ||
12259 | /* Fixed-point conversion with #0 immediate is encoded as an | |
12260 | integer conversion. */ | |
12261 | if (inst.operands[2].present && inst.operands[2].imm == 0) | |
12262 | goto int_encode; | |
12263 | unsigned immbits = 32 - inst.operands[2].imm; | |
12264 | unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; | |
12265 | inst.instruction = NEON_ENC_IMMED (inst.instruction); | |
12266 | if (flavour != -1) | |
12267 | inst.instruction |= enctab[flavour]; | |
12268 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12269 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12270 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
12271 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
12272 | inst.instruction |= neon_quad (rs) << 6; | |
12273 | inst.instruction |= 1 << 21; | |
12274 | inst.instruction |= immbits << 16; | |
12275 | ||
12276 | inst.instruction = neon_dp_fixup (inst.instruction); | |
12277 | } | |
12278 | break; | |
12279 | ||
12280 | case NS_DD: | |
12281 | case NS_QQ: | |
12282 | int_encode: | |
12283 | { | |
12284 | unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; | |
12285 | ||
12286 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
12287 | ||
12288 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
12289 | return; | |
12290 | ||
12291 | if (flavour != -1) | |
12292 | inst.instruction |= enctab[flavour]; | |
12293 | ||
12294 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12295 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12296 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
12297 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
12298 | inst.instruction |= neon_quad (rs) << 6; | |
12299 | inst.instruction |= 2 << 18; | |
12300 | ||
12301 | inst.instruction = neon_dp_fixup (inst.instruction); | |
12302 | } | |
12303 | break; | |
12304 | ||
12305 | default: | |
12306 | /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ | |
12307 | do_vfp_nsyn_cvt (rs, flavour); | |
5287ad62 | 12308 | } |
5287ad62 JB |
12309 | } |
12310 | ||
12311 | static void | |
12312 | neon_move_immediate (void) | |
12313 | { | |
037e8744 JB |
12314 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
12315 | struct neon_type_el et = neon_check_type (2, rs, | |
12316 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
5287ad62 JB |
12317 | unsigned immlo, immhi = 0, immbits; |
12318 | int op, cmode; | |
12319 | ||
037e8744 JB |
12320 | constraint (et.type == NT_invtype, |
12321 | _("operand size must be specified for immediate VMOV")); | |
12322 | ||
5287ad62 JB |
12323 | /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ |
12324 | op = (inst.instruction & (1 << 5)) != 0; | |
12325 | ||
12326 | immlo = inst.operands[1].imm; | |
12327 | if (inst.operands[1].regisimm) | |
12328 | immhi = inst.operands[1].reg; | |
12329 | ||
12330 | constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, | |
12331 | _("immediate has bits set outside the operand size")); | |
12332 | ||
12333 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, &immbits, &op, | |
136da414 | 12334 | et.size, et.type)) == FAIL) |
5287ad62 JB |
12335 | { |
12336 | /* Invert relevant bits only. */ | |
12337 | neon_invert_size (&immlo, &immhi, et.size); | |
12338 | /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable | |
12339 | with one or the other; those cases are caught by | |
12340 | neon_cmode_for_move_imm. */ | |
12341 | op = !op; | |
12342 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, &immbits, &op, | |
136da414 | 12343 | et.size, et.type)) == FAIL) |
5287ad62 | 12344 | { |
dcbf9037 | 12345 | first_error (_("immediate out of range")); |
5287ad62 JB |
12346 | return; |
12347 | } | |
12348 | } | |
12349 | ||
12350 | inst.instruction &= ~(1 << 5); | |
12351 | inst.instruction |= op << 5; | |
12352 | ||
12353 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12354 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
037e8744 | 12355 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
12356 | inst.instruction |= cmode << 8; |
12357 | ||
12358 | neon_write_immbits (immbits); | |
12359 | } | |
12360 | ||
12361 | static void | |
12362 | do_neon_mvn (void) | |
12363 | { | |
12364 | if (inst.operands[1].isreg) | |
12365 | { | |
037e8744 | 12366 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
12367 | |
12368 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
12369 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12370 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12371 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
12372 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 12373 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
12374 | } |
12375 | else | |
12376 | { | |
12377 | inst.instruction = NEON_ENC_IMMED (inst.instruction); | |
12378 | neon_move_immediate (); | |
12379 | } | |
12380 | ||
12381 | inst.instruction = neon_dp_fixup (inst.instruction); | |
12382 | } | |
12383 | ||
12384 | /* Encode instructions of form: | |
12385 | ||
12386 | |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
12387 | | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | | |
12388 | ||
12389 | */ | |
12390 | ||
12391 | static void | |
12392 | neon_mixed_length (struct neon_type_el et, unsigned size) | |
12393 | { | |
12394 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12395 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12396 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
12397 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
12398 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
12399 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
12400 | inst.instruction |= (et.type == NT_unsigned) << 24; | |
12401 | inst.instruction |= neon_logbits (size) << 20; | |
12402 | ||
12403 | inst.instruction = neon_dp_fixup (inst.instruction); | |
12404 | } | |
12405 | ||
12406 | static void | |
12407 | do_neon_dyadic_long (void) | |
12408 | { | |
12409 | /* FIXME: Type checking for lengthening op. */ | |
12410 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
12411 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
12412 | neon_mixed_length (et, et.size); | |
12413 | } | |
12414 | ||
12415 | static void | |
12416 | do_neon_abal (void) | |
12417 | { | |
12418 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
12419 | N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
12420 | neon_mixed_length (et, et.size); | |
12421 | } | |
12422 | ||
12423 | static void | |
12424 | neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) | |
12425 | { | |
12426 | if (inst.operands[2].isscalar) | |
12427 | { | |
dcbf9037 JB |
12428 | struct neon_type_el et = neon_check_type (3, NS_QDS, |
12429 | N_EQK | N_DBL, N_EQK, regtypes | N_KEY); | |
5287ad62 JB |
12430 | inst.instruction = NEON_ENC_SCALAR (inst.instruction); |
12431 | neon_mul_mac (et, et.type == NT_unsigned); | |
12432 | } | |
12433 | else | |
12434 | { | |
12435 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
12436 | N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); | |
12437 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
12438 | neon_mixed_length (et, et.size); | |
12439 | } | |
12440 | } | |
12441 | ||
12442 | static void | |
12443 | do_neon_mac_maybe_scalar_long (void) | |
12444 | { | |
12445 | neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); | |
12446 | } | |
12447 | ||
12448 | static void | |
12449 | do_neon_dyadic_wide (void) | |
12450 | { | |
12451 | struct neon_type_el et = neon_check_type (3, NS_QQD, | |
12452 | N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); | |
12453 | neon_mixed_length (et, et.size); | |
12454 | } | |
12455 | ||
12456 | static void | |
12457 | do_neon_dyadic_narrow (void) | |
12458 | { | |
12459 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
12460 | N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); | |
12461 | neon_mixed_length (et, et.size / 2); | |
12462 | } | |
12463 | ||
12464 | static void | |
12465 | do_neon_mul_sat_scalar_long (void) | |
12466 | { | |
12467 | neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); | |
12468 | } | |
12469 | ||
12470 | static void | |
12471 | do_neon_vmull (void) | |
12472 | { | |
12473 | if (inst.operands[2].isscalar) | |
12474 | do_neon_mac_maybe_scalar_long (); | |
12475 | else | |
12476 | { | |
12477 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
12478 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY); | |
12479 | if (et.type == NT_poly) | |
12480 | inst.instruction = NEON_ENC_POLY (inst.instruction); | |
12481 | else | |
12482 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
12483 | /* For polynomial encoding, size field must be 0b00 and the U bit must be | |
12484 | zero. Should be OK as-is. */ | |
12485 | neon_mixed_length (et, et.size); | |
12486 | } | |
12487 | } | |
12488 | ||
12489 | static void | |
12490 | do_neon_ext (void) | |
12491 | { | |
037e8744 | 12492 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
5287ad62 JB |
12493 | struct neon_type_el et = neon_check_type (3, rs, |
12494 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
12495 | unsigned imm = (inst.operands[3].imm * et.size) / 8; | |
12496 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12497 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12498 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
12499 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
12500 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
12501 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
037e8744 | 12502 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
12503 | inst.instruction |= imm << 8; |
12504 | ||
12505 | inst.instruction = neon_dp_fixup (inst.instruction); | |
12506 | } | |
12507 | ||
12508 | static void | |
12509 | do_neon_rev (void) | |
12510 | { | |
037e8744 | 12511 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
12512 | struct neon_type_el et = neon_check_type (2, rs, |
12513 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
12514 | unsigned op = (inst.instruction >> 7) & 3; | |
12515 | /* N (width of reversed regions) is encoded as part of the bitmask. We | |
12516 | extract it here to check the elements to be reversed are smaller. | |
12517 | Otherwise we'd get a reserved instruction. */ | |
12518 | unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; | |
12519 | assert (elsize != 0); | |
12520 | constraint (et.size >= elsize, | |
12521 | _("elements must be smaller than reversal region")); | |
037e8744 | 12522 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
12523 | } |
12524 | ||
12525 | static void | |
12526 | do_neon_dup (void) | |
12527 | { | |
12528 | if (inst.operands[1].isscalar) | |
12529 | { | |
037e8744 | 12530 | enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); |
dcbf9037 JB |
12531 | struct neon_type_el et = neon_check_type (2, rs, |
12532 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
5287ad62 | 12533 | unsigned sizebits = et.size >> 3; |
dcbf9037 | 12534 | unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); |
5287ad62 | 12535 | int logsize = neon_logbits (et.size); |
dcbf9037 | 12536 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; |
037e8744 JB |
12537 | |
12538 | if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) | |
12539 | return; | |
12540 | ||
5287ad62 JB |
12541 | inst.instruction = NEON_ENC_SCALAR (inst.instruction); |
12542 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12543 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12544 | inst.instruction |= LOW4 (dm); | |
12545 | inst.instruction |= HI1 (dm) << 5; | |
037e8744 | 12546 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
12547 | inst.instruction |= x << 17; |
12548 | inst.instruction |= sizebits << 16; | |
12549 | ||
12550 | inst.instruction = neon_dp_fixup (inst.instruction); | |
12551 | } | |
12552 | else | |
12553 | { | |
037e8744 JB |
12554 | enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); |
12555 | struct neon_type_el et = neon_check_type (2, rs, | |
12556 | N_8 | N_16 | N_32 | N_KEY, N_EQK); | |
5287ad62 JB |
12557 | /* Duplicate ARM register to lanes of vector. */ |
12558 | inst.instruction = NEON_ENC_ARMREG (inst.instruction); | |
12559 | switch (et.size) | |
12560 | { | |
12561 | case 8: inst.instruction |= 0x400000; break; | |
12562 | case 16: inst.instruction |= 0x000020; break; | |
12563 | case 32: inst.instruction |= 0x000000; break; | |
12564 | default: break; | |
12565 | } | |
12566 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
12567 | inst.instruction |= LOW4 (inst.operands[0].reg) << 16; | |
12568 | inst.instruction |= HI1 (inst.operands[0].reg) << 7; | |
037e8744 | 12569 | inst.instruction |= neon_quad (rs) << 21; |
5287ad62 JB |
12570 | /* The encoding for this instruction is identical for the ARM and Thumb |
12571 | variants, except for the condition field. */ | |
037e8744 | 12572 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
12573 | } |
12574 | } | |
12575 | ||
12576 | /* VMOV has particularly many variations. It can be one of: | |
12577 | 0. VMOV<c><q> <Qd>, <Qm> | |
12578 | 1. VMOV<c><q> <Dd>, <Dm> | |
12579 | (Register operations, which are VORR with Rm = Rn.) | |
12580 | 2. VMOV<c><q>.<dt> <Qd>, #<imm> | |
12581 | 3. VMOV<c><q>.<dt> <Dd>, #<imm> | |
12582 | (Immediate loads.) | |
12583 | 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> | |
12584 | (ARM register to scalar.) | |
12585 | 5. VMOV<c><q> <Dm>, <Rd>, <Rn> | |
12586 | (Two ARM registers to vector.) | |
12587 | 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> | |
12588 | (Scalar to ARM register.) | |
12589 | 7. VMOV<c><q> <Rd>, <Rn>, <Dm> | |
12590 | (Vector to two ARM registers.) | |
037e8744 JB |
12591 | 8. VMOV.F32 <Sd>, <Sm> |
12592 | 9. VMOV.F64 <Dd>, <Dm> | |
12593 | (VFP register moves.) | |
12594 | 10. VMOV.F32 <Sd>, #imm | |
12595 | 11. VMOV.F64 <Dd>, #imm | |
12596 | (VFP float immediate load.) | |
12597 | 12. VMOV <Rd>, <Sm> | |
12598 | (VFP single to ARM reg.) | |
12599 | 13. VMOV <Sd>, <Rm> | |
12600 | (ARM reg to VFP single.) | |
12601 | 14. VMOV <Rd>, <Re>, <Sn>, <Sm> | |
12602 | (Two ARM regs to two VFP singles.) | |
12603 | 15. VMOV <Sd>, <Se>, <Rn>, <Rm> | |
12604 | (Two VFP singles to two ARM regs.) | |
5287ad62 | 12605 | |
037e8744 JB |
12606 | These cases can be disambiguated using neon_select_shape, except cases 1/9 |
12607 | and 3/11 which depend on the operand type too. | |
5287ad62 JB |
12608 | |
12609 | All the encoded bits are hardcoded by this function. | |
12610 | ||
b7fc2769 JB |
12611 | Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). |
12612 | Cases 5, 7 may be used with VFPv2 and above. | |
12613 | ||
5287ad62 JB |
12614 | FIXME: Some of the checking may be a bit sloppy (in a couple of cases you |
12615 | can specify a type where it doesn't make sense to, and is ignored). | |
12616 | */ | |
12617 | ||
12618 | static void | |
12619 | do_neon_mov (void) | |
12620 | { | |
037e8744 JB |
12621 | enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, |
12622 | NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, | |
12623 | NS_NULL); | |
12624 | struct neon_type_el et; | |
12625 | const char *ldconst = 0; | |
5287ad62 | 12626 | |
037e8744 | 12627 | switch (rs) |
5287ad62 | 12628 | { |
037e8744 JB |
12629 | case NS_DD: /* case 1/9. */ |
12630 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
12631 | /* It is not an error here if no type is given. */ | |
12632 | inst.error = NULL; | |
12633 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 12634 | { |
037e8744 JB |
12635 | do_vfp_nsyn_opcode ("fcpyd"); |
12636 | break; | |
5287ad62 | 12637 | } |
037e8744 | 12638 | /* fall through. */ |
5287ad62 | 12639 | |
037e8744 JB |
12640 | case NS_QQ: /* case 0/1. */ |
12641 | { | |
12642 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
12643 | return; | |
12644 | /* The architecture manual I have doesn't explicitly state which | |
12645 | value the U bit should have for register->register moves, but | |
12646 | the equivalent VORR instruction has U = 0, so do that. */ | |
12647 | inst.instruction = 0x0200110; | |
12648 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12649 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12650 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
12651 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
12652 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
12653 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
12654 | inst.instruction |= neon_quad (rs) << 6; | |
12655 | ||
12656 | inst.instruction = neon_dp_fixup (inst.instruction); | |
12657 | } | |
12658 | break; | |
12659 | ||
12660 | case NS_DI: /* case 3/11. */ | |
12661 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
12662 | inst.error = NULL; | |
12663 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 12664 | { |
037e8744 JB |
12665 | /* case 11 (fconstd). */ |
12666 | ldconst = "fconstd"; | |
12667 | goto encode_fconstd; | |
5287ad62 | 12668 | } |
037e8744 JB |
12669 | /* fall through. */ |
12670 | ||
12671 | case NS_QI: /* case 2/3. */ | |
12672 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
12673 | return; | |
12674 | inst.instruction = 0x0800010; | |
12675 | neon_move_immediate (); | |
12676 | inst.instruction = neon_dp_fixup (inst.instruction); | |
5287ad62 JB |
12677 | break; |
12678 | ||
037e8744 JB |
12679 | case NS_SR: /* case 4. */ |
12680 | { | |
12681 | unsigned bcdebits = 0; | |
12682 | struct neon_type_el et = neon_check_type (2, NS_NULL, | |
12683 | N_8 | N_16 | N_32 | N_KEY, N_EQK); | |
12684 | int logsize = neon_logbits (et.size); | |
12685 | unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); | |
12686 | unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); | |
12687 | ||
12688 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), | |
12689 | _(BAD_FPU)); | |
12690 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
12691 | && et.size != 32, _(BAD_FPU)); | |
12692 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
12693 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
12694 | ||
12695 | switch (et.size) | |
12696 | { | |
12697 | case 8: bcdebits = 0x8; break; | |
12698 | case 16: bcdebits = 0x1; break; | |
12699 | case 32: bcdebits = 0x0; break; | |
12700 | default: ; | |
12701 | } | |
12702 | ||
12703 | bcdebits |= x << logsize; | |
12704 | ||
12705 | inst.instruction = 0xe000b10; | |
12706 | do_vfp_cond_or_thumb (); | |
12707 | inst.instruction |= LOW4 (dn) << 16; | |
12708 | inst.instruction |= HI1 (dn) << 7; | |
12709 | inst.instruction |= inst.operands[1].reg << 12; | |
12710 | inst.instruction |= (bcdebits & 3) << 5; | |
12711 | inst.instruction |= (bcdebits >> 2) << 21; | |
12712 | } | |
12713 | break; | |
12714 | ||
12715 | case NS_DRR: /* case 5 (fmdrr). */ | |
b7fc2769 | 12716 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), |
037e8744 | 12717 | _(BAD_FPU)); |
b7fc2769 | 12718 | |
037e8744 JB |
12719 | inst.instruction = 0xc400b10; |
12720 | do_vfp_cond_or_thumb (); | |
12721 | inst.instruction |= LOW4 (inst.operands[0].reg); | |
12722 | inst.instruction |= HI1 (inst.operands[0].reg) << 5; | |
12723 | inst.instruction |= inst.operands[1].reg << 12; | |
12724 | inst.instruction |= inst.operands[2].reg << 16; | |
12725 | break; | |
12726 | ||
12727 | case NS_RS: /* case 6. */ | |
12728 | { | |
12729 | struct neon_type_el et = neon_check_type (2, NS_NULL, | |
12730 | N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); | |
12731 | unsigned logsize = neon_logbits (et.size); | |
12732 | unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); | |
12733 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); | |
12734 | unsigned abcdebits = 0; | |
12735 | ||
12736 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), | |
12737 | _(BAD_FPU)); | |
12738 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
12739 | && et.size != 32, _(BAD_FPU)); | |
12740 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
12741 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
12742 | ||
12743 | switch (et.size) | |
12744 | { | |
12745 | case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; | |
12746 | case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; | |
12747 | case 32: abcdebits = 0x00; break; | |
12748 | default: ; | |
12749 | } | |
12750 | ||
12751 | abcdebits |= x << logsize; | |
12752 | inst.instruction = 0xe100b10; | |
12753 | do_vfp_cond_or_thumb (); | |
12754 | inst.instruction |= LOW4 (dn) << 16; | |
12755 | inst.instruction |= HI1 (dn) << 7; | |
12756 | inst.instruction |= inst.operands[0].reg << 12; | |
12757 | inst.instruction |= (abcdebits & 3) << 5; | |
12758 | inst.instruction |= (abcdebits >> 2) << 21; | |
12759 | } | |
12760 | break; | |
12761 | ||
12762 | case NS_RRD: /* case 7 (fmrrd). */ | |
12763 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), | |
12764 | _(BAD_FPU)); | |
12765 | ||
12766 | inst.instruction = 0xc500b10; | |
12767 | do_vfp_cond_or_thumb (); | |
12768 | inst.instruction |= inst.operands[0].reg << 12; | |
12769 | inst.instruction |= inst.operands[1].reg << 16; | |
12770 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
12771 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
12772 | break; | |
12773 | ||
12774 | case NS_FF: /* case 8 (fcpys). */ | |
12775 | do_vfp_nsyn_opcode ("fcpys"); | |
12776 | break; | |
12777 | ||
12778 | case NS_FI: /* case 10 (fconsts). */ | |
12779 | ldconst = "fconsts"; | |
12780 | encode_fconstd: | |
12781 | if (is_quarter_float (inst.operands[1].imm)) | |
5287ad62 | 12782 | { |
037e8744 JB |
12783 | inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); |
12784 | do_vfp_nsyn_opcode (ldconst); | |
5287ad62 JB |
12785 | } |
12786 | else | |
037e8744 JB |
12787 | first_error (_("immediate out of range")); |
12788 | break; | |
12789 | ||
12790 | case NS_RF: /* case 12 (fmrs). */ | |
12791 | do_vfp_nsyn_opcode ("fmrs"); | |
12792 | break; | |
12793 | ||
12794 | case NS_FR: /* case 13 (fmsr). */ | |
12795 | do_vfp_nsyn_opcode ("fmsr"); | |
12796 | break; | |
12797 | ||
12798 | /* The encoders for the fmrrs and fmsrr instructions expect three operands | |
12799 | (one of which is a list), but we have parsed four. Do some fiddling to | |
12800 | make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 | |
12801 | expect. */ | |
12802 | case NS_RRFF: /* case 14 (fmrrs). */ | |
12803 | constraint (inst.operands[3].reg != inst.operands[2].reg + 1, | |
12804 | _("VFP registers must be adjacent")); | |
12805 | inst.operands[2].imm = 2; | |
12806 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
12807 | do_vfp_nsyn_opcode ("fmrrs"); | |
12808 | break; | |
12809 | ||
12810 | case NS_FFRR: /* case 15 (fmsrr). */ | |
12811 | constraint (inst.operands[1].reg != inst.operands[0].reg + 1, | |
12812 | _("VFP registers must be adjacent")); | |
12813 | inst.operands[1] = inst.operands[2]; | |
12814 | inst.operands[2] = inst.operands[3]; | |
12815 | inst.operands[0].imm = 2; | |
12816 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
12817 | do_vfp_nsyn_opcode ("fmsrr"); | |
5287ad62 JB |
12818 | break; |
12819 | ||
12820 | default: | |
12821 | abort (); | |
12822 | } | |
12823 | } | |
12824 | ||
12825 | static void | |
12826 | do_neon_rshift_round_imm (void) | |
12827 | { | |
037e8744 | 12828 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
12829 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
12830 | int imm = inst.operands[2].imm; | |
12831 | ||
12832 | /* imm == 0 case is encoded as VMOV for V{R}SHR. */ | |
12833 | if (imm == 0) | |
12834 | { | |
12835 | inst.operands[2].present = 0; | |
12836 | do_neon_mov (); | |
12837 | return; | |
12838 | } | |
12839 | ||
12840 | constraint (imm < 1 || (unsigned)imm > et.size, | |
12841 | _("immediate out of range for shift")); | |
037e8744 | 12842 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
12843 | et.size - imm); |
12844 | } | |
12845 | ||
12846 | static void | |
12847 | do_neon_movl (void) | |
12848 | { | |
12849 | struct neon_type_el et = neon_check_type (2, NS_QD, | |
12850 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
12851 | unsigned sizebits = et.size >> 3; | |
12852 | inst.instruction |= sizebits << 19; | |
12853 | neon_two_same (0, et.type == NT_unsigned, -1); | |
12854 | } | |
12855 | ||
12856 | static void | |
12857 | do_neon_trn (void) | |
12858 | { | |
037e8744 | 12859 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
12860 | struct neon_type_el et = neon_check_type (2, rs, |
12861 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
12862 | inst.instruction = NEON_ENC_INTEGER (inst.instruction); | |
037e8744 | 12863 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
12864 | } |
12865 | ||
12866 | static void | |
12867 | do_neon_zip_uzp (void) | |
12868 | { | |
037e8744 | 12869 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
12870 | struct neon_type_el et = neon_check_type (2, rs, |
12871 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
12872 | if (rs == NS_DD && et.size == 32) | |
12873 | { | |
12874 | /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ | |
12875 | inst.instruction = N_MNEM_vtrn; | |
12876 | do_neon_trn (); | |
12877 | return; | |
12878 | } | |
037e8744 | 12879 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
12880 | } |
12881 | ||
12882 | static void | |
12883 | do_neon_sat_abs_neg (void) | |
12884 | { | |
037e8744 | 12885 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
12886 | struct neon_type_el et = neon_check_type (2, rs, |
12887 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 12888 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
12889 | } |
12890 | ||
12891 | static void | |
12892 | do_neon_pair_long (void) | |
12893 | { | |
037e8744 | 12894 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
12895 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); |
12896 | /* Unsigned is encoded in OP field (bit 7) for these instruction. */ | |
12897 | inst.instruction |= (et.type == NT_unsigned) << 7; | |
037e8744 | 12898 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
12899 | } |
12900 | ||
12901 | static void | |
12902 | do_neon_recip_est (void) | |
12903 | { | |
037e8744 | 12904 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
12905 | struct neon_type_el et = neon_check_type (2, rs, |
12906 | N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); | |
12907 | inst.instruction |= (et.type == NT_float) << 8; | |
037e8744 | 12908 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
12909 | } |
12910 | ||
12911 | static void | |
12912 | do_neon_cls (void) | |
12913 | { | |
037e8744 | 12914 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
12915 | struct neon_type_el et = neon_check_type (2, rs, |
12916 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 12917 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
12918 | } |
12919 | ||
12920 | static void | |
12921 | do_neon_clz (void) | |
12922 | { | |
037e8744 | 12923 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
12924 | struct neon_type_el et = neon_check_type (2, rs, |
12925 | N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); | |
037e8744 | 12926 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
12927 | } |
12928 | ||
12929 | static void | |
12930 | do_neon_cnt (void) | |
12931 | { | |
037e8744 | 12932 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
12933 | struct neon_type_el et = neon_check_type (2, rs, |
12934 | N_EQK | N_INT, N_8 | N_KEY); | |
037e8744 | 12935 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
12936 | } |
12937 | ||
12938 | static void | |
12939 | do_neon_swp (void) | |
12940 | { | |
037e8744 JB |
12941 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
12942 | neon_two_same (neon_quad (rs), 1, -1); | |
5287ad62 JB |
12943 | } |
12944 | ||
12945 | static void | |
12946 | do_neon_tbl_tbx (void) | |
12947 | { | |
12948 | unsigned listlenbits; | |
dcbf9037 | 12949 | neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); |
5287ad62 JB |
12950 | |
12951 | if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) | |
12952 | { | |
dcbf9037 | 12953 | first_error (_("bad list length for table lookup")); |
5287ad62 JB |
12954 | return; |
12955 | } | |
12956 | ||
12957 | listlenbits = inst.operands[1].imm - 1; | |
12958 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12959 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12960 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
12961 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
12962 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
12963 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
12964 | inst.instruction |= listlenbits << 8; | |
12965 | ||
12966 | inst.instruction = neon_dp_fixup (inst.instruction); | |
12967 | } | |
12968 | ||
12969 | static void | |
12970 | do_neon_ldm_stm (void) | |
12971 | { | |
12972 | /* P, U and L bits are part of bitmask. */ | |
12973 | int is_dbmode = (inst.instruction & (1 << 24)) != 0; | |
12974 | unsigned offsetbits = inst.operands[1].imm * 2; | |
12975 | ||
037e8744 JB |
12976 | if (inst.operands[1].issingle) |
12977 | { | |
12978 | do_vfp_nsyn_ldm_stm (is_dbmode); | |
12979 | return; | |
12980 | } | |
12981 | ||
5287ad62 JB |
12982 | constraint (is_dbmode && !inst.operands[0].writeback, |
12983 | _("writeback (!) must be used for VLDMDB and VSTMDB")); | |
12984 | ||
12985 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
12986 | _("register list must contain at least 1 and at most 16 " | |
12987 | "registers")); | |
12988 | ||
12989 | inst.instruction |= inst.operands[0].reg << 16; | |
12990 | inst.instruction |= inst.operands[0].writeback << 21; | |
12991 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
12992 | inst.instruction |= HI1 (inst.operands[1].reg) << 22; | |
12993 | ||
12994 | inst.instruction |= offsetbits; | |
12995 | ||
037e8744 | 12996 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
12997 | } |
12998 | ||
12999 | static void | |
13000 | do_neon_ldr_str (void) | |
13001 | { | |
5287ad62 JB |
13002 | int is_ldr = (inst.instruction & (1 << 20)) != 0; |
13003 | ||
037e8744 JB |
13004 | if (inst.operands[0].issingle) |
13005 | { | |
cd2f129f JB |
13006 | if (is_ldr) |
13007 | do_vfp_nsyn_opcode ("flds"); | |
13008 | else | |
13009 | do_vfp_nsyn_opcode ("fsts"); | |
5287ad62 JB |
13010 | } |
13011 | else | |
5287ad62 | 13012 | { |
cd2f129f JB |
13013 | if (is_ldr) |
13014 | do_vfp_nsyn_opcode ("fldd"); | |
5287ad62 | 13015 | else |
cd2f129f | 13016 | do_vfp_nsyn_opcode ("fstd"); |
5287ad62 | 13017 | } |
5287ad62 JB |
13018 | } |
13019 | ||
13020 | /* "interleave" version also handles non-interleaving register VLD1/VST1 | |
13021 | instructions. */ | |
13022 | ||
13023 | static void | |
13024 | do_neon_ld_st_interleave (void) | |
13025 | { | |
037e8744 | 13026 | struct neon_type_el et = neon_check_type (1, NS_NULL, |
5287ad62 JB |
13027 | N_8 | N_16 | N_32 | N_64); |
13028 | unsigned alignbits = 0; | |
13029 | unsigned idx; | |
13030 | /* The bits in this table go: | |
13031 | 0: register stride of one (0) or two (1) | |
13032 | 1,2: register list length, minus one (1, 2, 3, 4). | |
13033 | 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). | |
13034 | We use -1 for invalid entries. */ | |
13035 | const int typetable[] = | |
13036 | { | |
13037 | 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ | |
13038 | -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ | |
13039 | -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ | |
13040 | -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ | |
13041 | }; | |
13042 | int typebits; | |
13043 | ||
dcbf9037 JB |
13044 | if (et.type == NT_invtype) |
13045 | return; | |
13046 | ||
5287ad62 JB |
13047 | if (inst.operands[1].immisalign) |
13048 | switch (inst.operands[1].imm >> 8) | |
13049 | { | |
13050 | case 64: alignbits = 1; break; | |
13051 | case 128: | |
13052 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3) | |
13053 | goto bad_alignment; | |
13054 | alignbits = 2; | |
13055 | break; | |
13056 | case 256: | |
13057 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3) | |
13058 | goto bad_alignment; | |
13059 | alignbits = 3; | |
13060 | break; | |
13061 | default: | |
13062 | bad_alignment: | |
dcbf9037 | 13063 | first_error (_("bad alignment")); |
5287ad62 JB |
13064 | return; |
13065 | } | |
13066 | ||
13067 | inst.instruction |= alignbits << 4; | |
13068 | inst.instruction |= neon_logbits (et.size) << 6; | |
13069 | ||
13070 | /* Bits [4:6] of the immediate in a list specifier encode register stride | |
13071 | (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of | |
13072 | VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look | |
13073 | up the right value for "type" in a table based on this value and the given | |
13074 | list style, then stick it back. */ | |
13075 | idx = ((inst.operands[0].imm >> 4) & 7) | |
13076 | | (((inst.instruction >> 8) & 3) << 3); | |
13077 | ||
13078 | typebits = typetable[idx]; | |
13079 | ||
13080 | constraint (typebits == -1, _("bad list type for instruction")); | |
13081 | ||
13082 | inst.instruction &= ~0xf00; | |
13083 | inst.instruction |= typebits << 8; | |
13084 | } | |
13085 | ||
13086 | /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. | |
13087 | *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 | |
13088 | otherwise. The variable arguments are a list of pairs of legal (size, align) | |
13089 | values, terminated with -1. */ | |
13090 | ||
13091 | static int | |
13092 | neon_alignment_bit (int size, int align, int *do_align, ...) | |
13093 | { | |
13094 | va_list ap; | |
13095 | int result = FAIL, thissize, thisalign; | |
13096 | ||
13097 | if (!inst.operands[1].immisalign) | |
13098 | { | |
13099 | *do_align = 0; | |
13100 | return SUCCESS; | |
13101 | } | |
13102 | ||
13103 | va_start (ap, do_align); | |
13104 | ||
13105 | do | |
13106 | { | |
13107 | thissize = va_arg (ap, int); | |
13108 | if (thissize == -1) | |
13109 | break; | |
13110 | thisalign = va_arg (ap, int); | |
13111 | ||
13112 | if (size == thissize && align == thisalign) | |
13113 | result = SUCCESS; | |
13114 | } | |
13115 | while (result != SUCCESS); | |
13116 | ||
13117 | va_end (ap); | |
13118 | ||
13119 | if (result == SUCCESS) | |
13120 | *do_align = 1; | |
13121 | else | |
dcbf9037 | 13122 | first_error (_("unsupported alignment for instruction")); |
5287ad62 JB |
13123 | |
13124 | return result; | |
13125 | } | |
13126 | ||
13127 | static void | |
13128 | do_neon_ld_st_lane (void) | |
13129 | { | |
037e8744 | 13130 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
13131 | int align_good, do_align = 0; |
13132 | int logsize = neon_logbits (et.size); | |
13133 | int align = inst.operands[1].imm >> 8; | |
13134 | int n = (inst.instruction >> 8) & 3; | |
13135 | int max_el = 64 / et.size; | |
13136 | ||
dcbf9037 JB |
13137 | if (et.type == NT_invtype) |
13138 | return; | |
13139 | ||
5287ad62 JB |
13140 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, |
13141 | _("bad list length")); | |
13142 | constraint (NEON_LANE (inst.operands[0].imm) >= max_el, | |
13143 | _("scalar index out of range")); | |
13144 | constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 | |
13145 | && et.size == 8, | |
13146 | _("stride of 2 unavailable when element size is 8")); | |
13147 | ||
13148 | switch (n) | |
13149 | { | |
13150 | case 0: /* VLD1 / VST1. */ | |
13151 | align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, | |
13152 | 32, 32, -1); | |
13153 | if (align_good == FAIL) | |
13154 | return; | |
13155 | if (do_align) | |
13156 | { | |
13157 | unsigned alignbits = 0; | |
13158 | switch (et.size) | |
13159 | { | |
13160 | case 16: alignbits = 0x1; break; | |
13161 | case 32: alignbits = 0x3; break; | |
13162 | default: ; | |
13163 | } | |
13164 | inst.instruction |= alignbits << 4; | |
13165 | } | |
13166 | break; | |
13167 | ||
13168 | case 1: /* VLD2 / VST2. */ | |
13169 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, | |
13170 | 32, 64, -1); | |
13171 | if (align_good == FAIL) | |
13172 | return; | |
13173 | if (do_align) | |
13174 | inst.instruction |= 1 << 4; | |
13175 | break; | |
13176 | ||
13177 | case 2: /* VLD3 / VST3. */ | |
13178 | constraint (inst.operands[1].immisalign, | |
13179 | _("can't use alignment with this instruction")); | |
13180 | break; | |
13181 | ||
13182 | case 3: /* VLD4 / VST4. */ | |
13183 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
13184 | 16, 64, 32, 64, 32, 128, -1); | |
13185 | if (align_good == FAIL) | |
13186 | return; | |
13187 | if (do_align) | |
13188 | { | |
13189 | unsigned alignbits = 0; | |
13190 | switch (et.size) | |
13191 | { | |
13192 | case 8: alignbits = 0x1; break; | |
13193 | case 16: alignbits = 0x1; break; | |
13194 | case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; | |
13195 | default: ; | |
13196 | } | |
13197 | inst.instruction |= alignbits << 4; | |
13198 | } | |
13199 | break; | |
13200 | ||
13201 | default: ; | |
13202 | } | |
13203 | ||
13204 | /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ | |
13205 | if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
13206 | inst.instruction |= 1 << (4 + logsize); | |
13207 | ||
13208 | inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); | |
13209 | inst.instruction |= logsize << 10; | |
13210 | } | |
13211 | ||
13212 | /* Encode single n-element structure to all lanes VLD<n> instructions. */ | |
13213 | ||
13214 | static void | |
13215 | do_neon_ld_dup (void) | |
13216 | { | |
037e8744 | 13217 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
13218 | int align_good, do_align = 0; |
13219 | ||
dcbf9037 JB |
13220 | if (et.type == NT_invtype) |
13221 | return; | |
13222 | ||
5287ad62 JB |
13223 | switch ((inst.instruction >> 8) & 3) |
13224 | { | |
13225 | case 0: /* VLD1. */ | |
13226 | assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); | |
13227 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, | |
13228 | &do_align, 16, 16, 32, 32, -1); | |
13229 | if (align_good == FAIL) | |
13230 | return; | |
13231 | switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) | |
13232 | { | |
13233 | case 1: break; | |
13234 | case 2: inst.instruction |= 1 << 5; break; | |
dcbf9037 | 13235 | default: first_error (_("bad list length")); return; |
5287ad62 JB |
13236 | } |
13237 | inst.instruction |= neon_logbits (et.size) << 6; | |
13238 | break; | |
13239 | ||
13240 | case 1: /* VLD2. */ | |
13241 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, | |
13242 | &do_align, 8, 16, 16, 32, 32, 64, -1); | |
13243 | if (align_good == FAIL) | |
13244 | return; | |
13245 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, | |
13246 | _("bad list length")); | |
13247 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
13248 | inst.instruction |= 1 << 5; | |
13249 | inst.instruction |= neon_logbits (et.size) << 6; | |
13250 | break; | |
13251 | ||
13252 | case 2: /* VLD3. */ | |
13253 | constraint (inst.operands[1].immisalign, | |
13254 | _("can't use alignment with this instruction")); | |
13255 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, | |
13256 | _("bad list length")); | |
13257 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
13258 | inst.instruction |= 1 << 5; | |
13259 | inst.instruction |= neon_logbits (et.size) << 6; | |
13260 | break; | |
13261 | ||
13262 | case 3: /* VLD4. */ | |
13263 | { | |
13264 | int align = inst.operands[1].imm >> 8; | |
13265 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
13266 | 16, 64, 32, 64, 32, 128, -1); | |
13267 | if (align_good == FAIL) | |
13268 | return; | |
13269 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, | |
13270 | _("bad list length")); | |
13271 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
13272 | inst.instruction |= 1 << 5; | |
13273 | if (et.size == 32 && align == 128) | |
13274 | inst.instruction |= 0x3 << 6; | |
13275 | else | |
13276 | inst.instruction |= neon_logbits (et.size) << 6; | |
13277 | } | |
13278 | break; | |
13279 | ||
13280 | default: ; | |
13281 | } | |
13282 | ||
13283 | inst.instruction |= do_align << 4; | |
13284 | } | |
13285 | ||
13286 | /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those | |
13287 | apart from bits [11:4]. */ | |
13288 | ||
13289 | static void | |
13290 | do_neon_ldx_stx (void) | |
13291 | { | |
13292 | switch (NEON_LANE (inst.operands[0].imm)) | |
13293 | { | |
13294 | case NEON_INTERLEAVE_LANES: | |
13295 | inst.instruction = NEON_ENC_INTERLV (inst.instruction); | |
13296 | do_neon_ld_st_interleave (); | |
13297 | break; | |
13298 | ||
13299 | case NEON_ALL_LANES: | |
13300 | inst.instruction = NEON_ENC_DUP (inst.instruction); | |
13301 | do_neon_ld_dup (); | |
13302 | break; | |
13303 | ||
13304 | default: | |
13305 | inst.instruction = NEON_ENC_LANE (inst.instruction); | |
13306 | do_neon_ld_st_lane (); | |
13307 | } | |
13308 | ||
13309 | /* L bit comes from bit mask. */ | |
13310 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13311 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13312 | inst.instruction |= inst.operands[1].reg << 16; | |
13313 | ||
13314 | if (inst.operands[1].postind) | |
13315 | { | |
13316 | int postreg = inst.operands[1].imm & 0xf; | |
13317 | constraint (!inst.operands[1].immisreg, | |
13318 | _("post-index must be a register")); | |
13319 | constraint (postreg == 0xd || postreg == 0xf, | |
13320 | _("bad register for post-index")); | |
13321 | inst.instruction |= postreg; | |
13322 | } | |
13323 | else if (inst.operands[1].writeback) | |
13324 | { | |
13325 | inst.instruction |= 0xd; | |
13326 | } | |
13327 | else | |
13328 | inst.instruction |= 0xf; | |
13329 | ||
13330 | if (thumb_mode) | |
13331 | inst.instruction |= 0xf9000000; | |
13332 | else | |
13333 | inst.instruction |= 0xf4000000; | |
13334 | } | |
13335 | ||
13336 | \f | |
13337 | /* Overall per-instruction processing. */ | |
13338 | ||
13339 | /* We need to be able to fix up arbitrary expressions in some statements. | |
13340 | This is so that we can handle symbols that are an arbitrary distance from | |
13341 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
13342 | which returns part of an address in a form which will be valid for | |
13343 | a data instruction. We do this by pushing the expression into a symbol | |
13344 | in the expr_section, and creating a fix for that. */ | |
13345 | ||
13346 | static void | |
13347 | fix_new_arm (fragS * frag, | |
13348 | int where, | |
13349 | short int size, | |
13350 | expressionS * exp, | |
13351 | int pc_rel, | |
13352 | int reloc) | |
13353 | { | |
13354 | fixS * new_fix; | |
13355 | ||
13356 | switch (exp->X_op) | |
13357 | { | |
13358 | case O_constant: | |
13359 | case O_symbol: | |
13360 | case O_add: | |
13361 | case O_subtract: | |
13362 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc); | |
13363 | break; | |
13364 | ||
13365 | default: | |
13366 | new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0, | |
13367 | pc_rel, reloc); | |
13368 | break; | |
13369 | } | |
13370 | ||
13371 | /* Mark whether the fix is to a THUMB instruction, or an ARM | |
13372 | instruction. */ | |
13373 | new_fix->tc_fix_data = thumb_mode; | |
13374 | } | |
13375 | ||
13376 | /* Create a frg for an instruction requiring relaxation. */ | |
13377 | static void | |
13378 | output_relax_insn (void) | |
13379 | { | |
13380 | char * to; | |
13381 | symbolS *sym; | |
0110f2b8 PB |
13382 | int offset; |
13383 | ||
6e1cb1a6 PB |
13384 | #ifdef OBJ_ELF |
13385 | /* The size of the instruction is unknown, so tie the debug info to the | |
13386 | start of the instruction. */ | |
13387 | dwarf2_emit_insn (0); | |
13388 | #endif | |
13389 | ||
0110f2b8 PB |
13390 | switch (inst.reloc.exp.X_op) |
13391 | { | |
13392 | case O_symbol: | |
13393 | sym = inst.reloc.exp.X_add_symbol; | |
13394 | offset = inst.reloc.exp.X_add_number; | |
13395 | break; | |
13396 | case O_constant: | |
13397 | sym = NULL; | |
13398 | offset = inst.reloc.exp.X_add_number; | |
13399 | break; | |
13400 | default: | |
13401 | sym = make_expr_symbol (&inst.reloc.exp); | |
13402 | offset = 0; | |
13403 | break; | |
13404 | } | |
13405 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
13406 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
13407 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
0110f2b8 PB |
13408 | } |
13409 | ||
13410 | /* Write a 32-bit thumb instruction to buf. */ | |
13411 | static void | |
13412 | put_thumb32_insn (char * buf, unsigned long insn) | |
13413 | { | |
13414 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
13415 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
13416 | } | |
13417 | ||
b99bd4ef | 13418 | static void |
c19d1205 | 13419 | output_inst (const char * str) |
b99bd4ef | 13420 | { |
c19d1205 | 13421 | char * to = NULL; |
b99bd4ef | 13422 | |
c19d1205 | 13423 | if (inst.error) |
b99bd4ef | 13424 | { |
c19d1205 | 13425 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
13426 | return; |
13427 | } | |
0110f2b8 PB |
13428 | if (inst.relax) { |
13429 | output_relax_insn(); | |
13430 | return; | |
13431 | } | |
c19d1205 ZW |
13432 | if (inst.size == 0) |
13433 | return; | |
b99bd4ef | 13434 | |
c19d1205 ZW |
13435 | to = frag_more (inst.size); |
13436 | ||
13437 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 13438 | { |
c19d1205 | 13439 | assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 13440 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 13441 | } |
c19d1205 | 13442 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 13443 | { |
c19d1205 ZW |
13444 | assert (inst.size == (2 * INSN_SIZE)); |
13445 | md_number_to_chars (to, inst.instruction, INSN_SIZE); | |
13446 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 13447 | } |
c19d1205 ZW |
13448 | else |
13449 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 13450 | |
c19d1205 ZW |
13451 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
13452 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
13453 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
13454 | inst.reloc.type); | |
b99bd4ef | 13455 | |
c19d1205 ZW |
13456 | #ifdef OBJ_ELF |
13457 | dwarf2_emit_insn (inst.size); | |
13458 | #endif | |
13459 | } | |
b99bd4ef | 13460 | |
c19d1205 ZW |
13461 | /* Tag values used in struct asm_opcode's tag field. */ |
13462 | enum opcode_tag | |
13463 | { | |
13464 | OT_unconditional, /* Instruction cannot be conditionalized. | |
13465 | The ARM condition field is still 0xE. */ | |
13466 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
13467 | and carries 0xF in its ARM condition field. */ | |
13468 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
037e8744 JB |
13469 | OT_csuffixF, /* Some forms of the instruction take a conditional |
13470 | suffix, others place 0xF where the condition field | |
13471 | would be. */ | |
c19d1205 ZW |
13472 | OT_cinfix3, /* Instruction takes a conditional infix, |
13473 | beginning at character index 3. (In | |
13474 | unified mode, it becomes a suffix.) */ | |
088fa78e KH |
13475 | OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for |
13476 | tsts, cmps, cmns, and teqs. */ | |
e3cb604e PB |
13477 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
13478 | character index 3, even in unified mode. Used for | |
13479 | legacy instructions where suffix and infix forms | |
13480 | may be ambiguous. */ | |
c19d1205 | 13481 | OT_csuf_or_in3, /* Instruction takes either a conditional |
e3cb604e | 13482 | suffix or an infix at character index 3. */ |
c19d1205 ZW |
13483 | OT_odd_infix_unc, /* This is the unconditional variant of an |
13484 | instruction that takes a conditional infix | |
13485 | at an unusual position. In unified mode, | |
13486 | this variant will accept a suffix. */ | |
13487 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
13488 | are the conditional variants of instructions that | |
13489 | take conditional infixes in unusual positions. | |
13490 | The infix appears at character index | |
13491 | (tag - OT_odd_infix_0). These are not accepted | |
13492 | in unified mode. */ | |
13493 | }; | |
b99bd4ef | 13494 | |
c19d1205 ZW |
13495 | /* Subroutine of md_assemble, responsible for looking up the primary |
13496 | opcode from the mnemonic the user wrote. STR points to the | |
13497 | beginning of the mnemonic. | |
13498 | ||
13499 | This is not simply a hash table lookup, because of conditional | |
13500 | variants. Most instructions have conditional variants, which are | |
13501 | expressed with a _conditional affix_ to the mnemonic. If we were | |
13502 | to encode each conditional variant as a literal string in the opcode | |
13503 | table, it would have approximately 20,000 entries. | |
13504 | ||
13505 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
13506 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
13507 | instructions take the affix as an infix, notably the s-variants of | |
13508 | the arithmetic instructions. Of those instructions, all but six | |
13509 | have the infix appear after the third character of the mnemonic. | |
13510 | ||
13511 | Accordingly, the algorithm for looking up primary opcodes given | |
13512 | an identifier is: | |
13513 | ||
13514 | 1. Look up the identifier in the opcode table. | |
13515 | If we find a match, go to step U. | |
13516 | ||
13517 | 2. Look up the last two characters of the identifier in the | |
13518 | conditions table. If we find a match, look up the first N-2 | |
13519 | characters of the identifier in the opcode table. If we | |
13520 | find a match, go to step CE. | |
13521 | ||
13522 | 3. Look up the fourth and fifth characters of the identifier in | |
13523 | the conditions table. If we find a match, extract those | |
13524 | characters from the identifier, and look up the remaining | |
13525 | characters in the opcode table. If we find a match, go | |
13526 | to step CM. | |
13527 | ||
13528 | 4. Fail. | |
13529 | ||
13530 | U. Examine the tag field of the opcode structure, in case this is | |
13531 | one of the six instructions with its conditional infix in an | |
13532 | unusual place. If it is, the tag tells us where to find the | |
13533 | infix; look it up in the conditions table and set inst.cond | |
13534 | accordingly. Otherwise, this is an unconditional instruction. | |
13535 | Again set inst.cond accordingly. Return the opcode structure. | |
13536 | ||
13537 | CE. Examine the tag field to make sure this is an instruction that | |
13538 | should receive a conditional suffix. If it is not, fail. | |
13539 | Otherwise, set inst.cond from the suffix we already looked up, | |
13540 | and return the opcode structure. | |
13541 | ||
13542 | CM. Examine the tag field to make sure this is an instruction that | |
13543 | should receive a conditional infix after the third character. | |
13544 | If it is not, fail. Otherwise, undo the edits to the current | |
13545 | line of input and proceed as for case CE. */ | |
13546 | ||
13547 | static const struct asm_opcode * | |
13548 | opcode_lookup (char **str) | |
13549 | { | |
13550 | char *end, *base; | |
13551 | char *affix; | |
13552 | const struct asm_opcode *opcode; | |
13553 | const struct asm_cond *cond; | |
e3cb604e | 13554 | char save[2]; |
c19d1205 ZW |
13555 | |
13556 | /* Scan up to the end of the mnemonic, which must end in white space, | |
13557 | '.' (in unified mode only), or end of string. */ | |
13558 | for (base = end = *str; *end != '\0'; end++) | |
13559 | if (*end == ' ' || (unified_syntax && *end == '.')) | |
13560 | break; | |
b99bd4ef | 13561 | |
c19d1205 ZW |
13562 | if (end == base) |
13563 | return 0; | |
b99bd4ef | 13564 | |
5287ad62 | 13565 | /* Handle a possible width suffix and/or Neon type suffix. */ |
c19d1205 | 13566 | if (end[0] == '.') |
b99bd4ef | 13567 | { |
5287ad62 JB |
13568 | int offset = 2; |
13569 | ||
13570 | if (end[1] == 'w') | |
c19d1205 | 13571 | inst.size_req = 4; |
5287ad62 | 13572 | else if (end[1] == 'n') |
c19d1205 ZW |
13573 | inst.size_req = 2; |
13574 | else | |
5287ad62 JB |
13575 | offset = 0; |
13576 | ||
13577 | inst.vectype.elems = 0; | |
13578 | ||
13579 | *str = end + offset; | |
b99bd4ef | 13580 | |
5287ad62 JB |
13581 | if (end[offset] == '.') |
13582 | { | |
13583 | /* See if we have a Neon type suffix. */ | |
dcbf9037 | 13584 | if (parse_neon_type (&inst.vectype, str) == FAIL) |
5287ad62 JB |
13585 | return 0; |
13586 | } | |
13587 | else if (end[offset] != '\0' && end[offset] != ' ') | |
13588 | return 0; | |
b99bd4ef | 13589 | } |
c19d1205 ZW |
13590 | else |
13591 | *str = end; | |
b99bd4ef | 13592 | |
c19d1205 ZW |
13593 | /* Look for unaffixed or special-case affixed mnemonic. */ |
13594 | opcode = hash_find_n (arm_ops_hsh, base, end - base); | |
13595 | if (opcode) | |
b99bd4ef | 13596 | { |
c19d1205 ZW |
13597 | /* step U */ |
13598 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 13599 | { |
c19d1205 ZW |
13600 | inst.cond = COND_ALWAYS; |
13601 | return opcode; | |
b99bd4ef | 13602 | } |
b99bd4ef | 13603 | |
c19d1205 ZW |
13604 | if (unified_syntax) |
13605 | as_warn (_("conditional infixes are deprecated in unified syntax")); | |
13606 | affix = base + (opcode->tag - OT_odd_infix_0); | |
13607 | cond = hash_find_n (arm_cond_hsh, affix, 2); | |
13608 | assert (cond); | |
b99bd4ef | 13609 | |
c19d1205 ZW |
13610 | inst.cond = cond->value; |
13611 | return opcode; | |
13612 | } | |
b99bd4ef | 13613 | |
c19d1205 ZW |
13614 | /* Cannot have a conditional suffix on a mnemonic of less than two |
13615 | characters. */ | |
13616 | if (end - base < 3) | |
13617 | return 0; | |
b99bd4ef | 13618 | |
c19d1205 ZW |
13619 | /* Look for suffixed mnemonic. */ |
13620 | affix = end - 2; | |
13621 | cond = hash_find_n (arm_cond_hsh, affix, 2); | |
13622 | opcode = hash_find_n (arm_ops_hsh, base, affix - base); | |
13623 | if (opcode && cond) | |
13624 | { | |
13625 | /* step CE */ | |
13626 | switch (opcode->tag) | |
13627 | { | |
e3cb604e PB |
13628 | case OT_cinfix3_legacy: |
13629 | /* Ignore conditional suffixes matched on infix only mnemonics. */ | |
13630 | break; | |
13631 | ||
c19d1205 | 13632 | case OT_cinfix3: |
088fa78e | 13633 | case OT_cinfix3_deprecated: |
c19d1205 ZW |
13634 | case OT_odd_infix_unc: |
13635 | if (!unified_syntax) | |
e3cb604e | 13636 | return 0; |
c19d1205 ZW |
13637 | /* else fall through */ |
13638 | ||
13639 | case OT_csuffix: | |
037e8744 | 13640 | case OT_csuffixF: |
c19d1205 ZW |
13641 | case OT_csuf_or_in3: |
13642 | inst.cond = cond->value; | |
13643 | return opcode; | |
13644 | ||
13645 | case OT_unconditional: | |
13646 | case OT_unconditionalF: | |
dfa9f0d5 PB |
13647 | if (thumb_mode) |
13648 | { | |
13649 | inst.cond = cond->value; | |
13650 | } | |
13651 | else | |
13652 | { | |
13653 | /* delayed diagnostic */ | |
13654 | inst.error = BAD_COND; | |
13655 | inst.cond = COND_ALWAYS; | |
13656 | } | |
c19d1205 | 13657 | return opcode; |
b99bd4ef | 13658 | |
c19d1205 ZW |
13659 | default: |
13660 | return 0; | |
13661 | } | |
13662 | } | |
b99bd4ef | 13663 | |
c19d1205 ZW |
13664 | /* Cannot have a usual-position infix on a mnemonic of less than |
13665 | six characters (five would be a suffix). */ | |
13666 | if (end - base < 6) | |
13667 | return 0; | |
b99bd4ef | 13668 | |
c19d1205 ZW |
13669 | /* Look for infixed mnemonic in the usual position. */ |
13670 | affix = base + 3; | |
13671 | cond = hash_find_n (arm_cond_hsh, affix, 2); | |
e3cb604e PB |
13672 | if (!cond) |
13673 | return 0; | |
13674 | ||
13675 | memcpy (save, affix, 2); | |
13676 | memmove (affix, affix + 2, (end - affix) - 2); | |
13677 | opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2); | |
13678 | memmove (affix + 2, affix, (end - affix) - 2); | |
13679 | memcpy (affix, save, 2); | |
13680 | ||
088fa78e KH |
13681 | if (opcode |
13682 | && (opcode->tag == OT_cinfix3 | |
13683 | || opcode->tag == OT_cinfix3_deprecated | |
13684 | || opcode->tag == OT_csuf_or_in3 | |
13685 | || opcode->tag == OT_cinfix3_legacy)) | |
b99bd4ef | 13686 | { |
c19d1205 | 13687 | /* step CM */ |
088fa78e KH |
13688 | if (unified_syntax |
13689 | && (opcode->tag == OT_cinfix3 | |
13690 | || opcode->tag == OT_cinfix3_deprecated)) | |
c19d1205 ZW |
13691 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
13692 | ||
13693 | inst.cond = cond->value; | |
13694 | return opcode; | |
b99bd4ef NC |
13695 | } |
13696 | ||
c19d1205 | 13697 | return 0; |
b99bd4ef NC |
13698 | } |
13699 | ||
c19d1205 ZW |
13700 | void |
13701 | md_assemble (char *str) | |
b99bd4ef | 13702 | { |
c19d1205 ZW |
13703 | char *p = str; |
13704 | const struct asm_opcode * opcode; | |
b99bd4ef | 13705 | |
c19d1205 ZW |
13706 | /* Align the previous label if needed. */ |
13707 | if (last_label_seen != NULL) | |
b99bd4ef | 13708 | { |
c19d1205 ZW |
13709 | symbol_set_frag (last_label_seen, frag_now); |
13710 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
13711 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
13712 | } |
13713 | ||
c19d1205 ZW |
13714 | memset (&inst, '\0', sizeof (inst)); |
13715 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 13716 | |
c19d1205 ZW |
13717 | opcode = opcode_lookup (&p); |
13718 | if (!opcode) | |
b99bd4ef | 13719 | { |
c19d1205 | 13720 | /* It wasn't an instruction, but it might be a register alias of |
dcbf9037 JB |
13721 | the form alias .req reg, or a Neon .dn/.qn directive. */ |
13722 | if (!create_register_alias (str, p) | |
13723 | && !create_neon_reg_alias (str, p)) | |
c19d1205 | 13724 | as_bad (_("bad instruction `%s'"), str); |
b99bd4ef | 13725 | |
b99bd4ef NC |
13726 | return; |
13727 | } | |
13728 | ||
088fa78e KH |
13729 | if (opcode->tag == OT_cinfix3_deprecated) |
13730 | as_warn (_("s suffix on comparison instruction is deprecated")); | |
13731 | ||
037e8744 JB |
13732 | /* The value which unconditional instructions should have in place of the |
13733 | condition field. */ | |
13734 | inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; | |
13735 | ||
c19d1205 | 13736 | if (thumb_mode) |
b99bd4ef | 13737 | { |
e74cfd16 | 13738 | arm_feature_set variant; |
8f06b2d8 PB |
13739 | |
13740 | variant = cpu_variant; | |
13741 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
e74cfd16 PB |
13742 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
13743 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); | |
c19d1205 | 13744 | /* Check that this instruction is supported for this CPU. */ |
62b3e311 PB |
13745 | if (!opcode->tvariant |
13746 | || (thumb_mode == 1 | |
13747 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) | |
b99bd4ef | 13748 | { |
c19d1205 | 13749 | as_bad (_("selected processor does not support `%s'"), str); |
b99bd4ef NC |
13750 | return; |
13751 | } | |
c19d1205 ZW |
13752 | if (inst.cond != COND_ALWAYS && !unified_syntax |
13753 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 13754 | { |
c19d1205 | 13755 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
13756 | return; |
13757 | } | |
13758 | ||
e27ec89e PB |
13759 | /* Check conditional suffixes. */ |
13760 | if (current_it_mask) | |
13761 | { | |
13762 | int cond; | |
13763 | cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1; | |
dfa9f0d5 PB |
13764 | current_it_mask <<= 1; |
13765 | current_it_mask &= 0x1f; | |
13766 | /* The BKPT instruction is unconditional even in an IT block. */ | |
13767 | if (!inst.error | |
13768 | && cond != inst.cond && opcode->tencode != do_t_bkpt) | |
e27ec89e PB |
13769 | { |
13770 | as_bad (_("incorrect condition in IT block")); | |
13771 | return; | |
13772 | } | |
e27ec89e PB |
13773 | } |
13774 | else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch) | |
13775 | { | |
13776 | as_bad (_("thumb conditional instrunction not in IT block")); | |
13777 | return; | |
13778 | } | |
13779 | ||
c19d1205 ZW |
13780 | mapping_state (MAP_THUMB); |
13781 | inst.instruction = opcode->tvalue; | |
13782 | ||
13783 | if (!parse_operands (p, opcode->operands)) | |
13784 | opcode->tencode (); | |
13785 | ||
e27ec89e PB |
13786 | /* Clear current_it_mask at the end of an IT block. */ |
13787 | if (current_it_mask == 0x10) | |
13788 | current_it_mask = 0; | |
13789 | ||
0110f2b8 | 13790 | if (!(inst.error || inst.relax)) |
b99bd4ef | 13791 | { |
c19d1205 ZW |
13792 | assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
13793 | inst.size = (inst.instruction > 0xffff ? 4 : 2); | |
13794 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 13795 | { |
c19d1205 | 13796 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
13797 | return; |
13798 | } | |
13799 | } | |
e74cfd16 PB |
13800 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
13801 | *opcode->tvariant); | |
ee065d83 | 13802 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
708587a4 | 13803 | set those bits when Thumb-2 32-bit instructions are seen. ie. |
ee065d83 PB |
13804 | anything other than bl/blx. |
13805 | This is overly pessimistic for relaxable instructions. */ | |
13806 | if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) | |
13807 | || inst.relax) | |
e74cfd16 PB |
13808 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
13809 | arm_ext_v6t2); | |
c19d1205 ZW |
13810 | } |
13811 | else | |
13812 | { | |
13813 | /* Check that this instruction is supported for this CPU. */ | |
62b3e311 PB |
13814 | if (!opcode->avariant || |
13815 | !ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)) | |
b99bd4ef | 13816 | { |
c19d1205 ZW |
13817 | as_bad (_("selected processor does not support `%s'"), str); |
13818 | return; | |
b99bd4ef | 13819 | } |
c19d1205 | 13820 | if (inst.size_req) |
b99bd4ef | 13821 | { |
c19d1205 ZW |
13822 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
13823 | return; | |
b99bd4ef NC |
13824 | } |
13825 | ||
c19d1205 ZW |
13826 | mapping_state (MAP_ARM); |
13827 | inst.instruction = opcode->avalue; | |
13828 | if (opcode->tag == OT_unconditionalF) | |
13829 | inst.instruction |= 0xF << 28; | |
13830 | else | |
13831 | inst.instruction |= inst.cond << 28; | |
13832 | inst.size = INSN_SIZE; | |
13833 | if (!parse_operands (p, opcode->operands)) | |
13834 | opcode->aencode (); | |
ee065d83 PB |
13835 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
13836 | on a hypothetical non-thumb v5 core. */ | |
e74cfd16 PB |
13837 | if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t) |
13838 | || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5)) | |
13839 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); | |
ee065d83 | 13840 | else |
e74cfd16 PB |
13841 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
13842 | *opcode->avariant); | |
b99bd4ef | 13843 | } |
c19d1205 ZW |
13844 | output_inst (str); |
13845 | } | |
b99bd4ef | 13846 | |
c19d1205 ZW |
13847 | /* Various frobbings of labels and their addresses. */ |
13848 | ||
13849 | void | |
13850 | arm_start_line_hook (void) | |
13851 | { | |
13852 | last_label_seen = NULL; | |
b99bd4ef NC |
13853 | } |
13854 | ||
c19d1205 ZW |
13855 | void |
13856 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 13857 | { |
c19d1205 | 13858 | last_label_seen = sym; |
b99bd4ef | 13859 | |
c19d1205 | 13860 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 13861 | |
c19d1205 ZW |
13862 | #if defined OBJ_COFF || defined OBJ_ELF |
13863 | ARM_SET_INTERWORK (sym, support_interwork); | |
13864 | #endif | |
b99bd4ef | 13865 | |
c19d1205 ZW |
13866 | /* Note - do not allow local symbols (.Lxxx) to be labeled |
13867 | as Thumb functions. This is because these labels, whilst | |
13868 | they exist inside Thumb code, are not the entry points for | |
13869 | possible ARM->Thumb calls. Also, these labels can be used | |
13870 | as part of a computed goto or switch statement. eg gcc | |
13871 | can generate code that looks like this: | |
b99bd4ef | 13872 | |
c19d1205 ZW |
13873 | ldr r2, [pc, .Laaa] |
13874 | lsl r3, r3, #2 | |
13875 | ldr r2, [r3, r2] | |
13876 | mov pc, r2 | |
b99bd4ef | 13877 | |
c19d1205 ZW |
13878 | .Lbbb: .word .Lxxx |
13879 | .Lccc: .word .Lyyy | |
13880 | ..etc... | |
13881 | .Laaa: .word Lbbb | |
b99bd4ef | 13882 | |
c19d1205 ZW |
13883 | The first instruction loads the address of the jump table. |
13884 | The second instruction converts a table index into a byte offset. | |
13885 | The third instruction gets the jump address out of the table. | |
13886 | The fourth instruction performs the jump. | |
b99bd4ef | 13887 | |
c19d1205 ZW |
13888 | If the address stored at .Laaa is that of a symbol which has the |
13889 | Thumb_Func bit set, then the linker will arrange for this address | |
13890 | to have the bottom bit set, which in turn would mean that the | |
13891 | address computation performed by the third instruction would end | |
13892 | up with the bottom bit set. Since the ARM is capable of unaligned | |
13893 | word loads, the instruction would then load the incorrect address | |
13894 | out of the jump table, and chaos would ensue. */ | |
13895 | if (label_is_thumb_function_name | |
13896 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
13897 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 13898 | { |
c19d1205 ZW |
13899 | /* When the address of a Thumb function is taken the bottom |
13900 | bit of that address should be set. This will allow | |
13901 | interworking between Arm and Thumb functions to work | |
13902 | correctly. */ | |
b99bd4ef | 13903 | |
c19d1205 | 13904 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 13905 | |
c19d1205 | 13906 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 13907 | } |
07a53e5c RH |
13908 | |
13909 | #ifdef OBJ_ELF | |
13910 | dwarf2_emit_label (sym); | |
13911 | #endif | |
b99bd4ef NC |
13912 | } |
13913 | ||
c19d1205 ZW |
13914 | int |
13915 | arm_data_in_code (void) | |
b99bd4ef | 13916 | { |
c19d1205 | 13917 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 13918 | { |
c19d1205 ZW |
13919 | *input_line_pointer = '/'; |
13920 | input_line_pointer += 5; | |
13921 | *input_line_pointer = 0; | |
13922 | return 1; | |
b99bd4ef NC |
13923 | } |
13924 | ||
c19d1205 | 13925 | return 0; |
b99bd4ef NC |
13926 | } |
13927 | ||
c19d1205 ZW |
13928 | char * |
13929 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 13930 | { |
c19d1205 | 13931 | int len; |
b99bd4ef | 13932 | |
c19d1205 ZW |
13933 | if (thumb_mode && (len = strlen (name)) > 5 |
13934 | && streq (name + len - 5, "/data")) | |
13935 | *(name + len - 5) = 0; | |
b99bd4ef | 13936 | |
c19d1205 | 13937 | return name; |
b99bd4ef | 13938 | } |
c19d1205 ZW |
13939 | \f |
13940 | /* Table of all register names defined by default. The user can | |
13941 | define additional names with .req. Note that all register names | |
13942 | should appear in both upper and lowercase variants. Some registers | |
13943 | also have mixed-case names. */ | |
b99bd4ef | 13944 | |
dcbf9037 | 13945 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } |
c19d1205 | 13946 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) |
5287ad62 | 13947 | #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) |
c19d1205 ZW |
13948 | #define REGSET(p,t) \ |
13949 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
13950 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
13951 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
13952 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
5287ad62 JB |
13953 | #define REGSETH(p,t) \ |
13954 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ | |
13955 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ | |
13956 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ | |
13957 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) | |
13958 | #define REGSET2(p,t) \ | |
13959 | REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ | |
13960 | REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ | |
13961 | REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ | |
13962 | REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) | |
7ed4c4c5 | 13963 | |
c19d1205 | 13964 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 13965 | { |
c19d1205 ZW |
13966 | /* ARM integer registers. */ |
13967 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 13968 | |
c19d1205 ZW |
13969 | /* ATPCS synonyms. */ |
13970 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
13971 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
13972 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 13973 | |
c19d1205 ZW |
13974 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
13975 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
13976 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 13977 | |
c19d1205 ZW |
13978 | /* Well-known aliases. */ |
13979 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
13980 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
13981 | ||
13982 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
13983 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
13984 | ||
13985 | /* Coprocessor numbers. */ | |
13986 | REGSET(p, CP), REGSET(P, CP), | |
13987 | ||
13988 | /* Coprocessor register numbers. The "cr" variants are for backward | |
13989 | compatibility. */ | |
13990 | REGSET(c, CN), REGSET(C, CN), | |
13991 | REGSET(cr, CN), REGSET(CR, CN), | |
13992 | ||
13993 | /* FPA registers. */ | |
13994 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
13995 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
13996 | ||
13997 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
13998 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
13999 | ||
14000 | /* VFP SP registers. */ | |
5287ad62 JB |
14001 | REGSET(s,VFS), REGSET(S,VFS), |
14002 | REGSETH(s,VFS), REGSETH(S,VFS), | |
c19d1205 ZW |
14003 | |
14004 | /* VFP DP Registers. */ | |
5287ad62 JB |
14005 | REGSET(d,VFD), REGSET(D,VFD), |
14006 | /* Extra Neon DP registers. */ | |
14007 | REGSETH(d,VFD), REGSETH(D,VFD), | |
14008 | ||
14009 | /* Neon QP registers. */ | |
14010 | REGSET2(q,NQ), REGSET2(Q,NQ), | |
c19d1205 ZW |
14011 | |
14012 | /* VFP control registers. */ | |
14013 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
14014 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
14015 | ||
14016 | /* Maverick DSP coprocessor registers. */ | |
14017 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
14018 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
14019 | ||
14020 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
14021 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
14022 | REGDEF(dspsc,0,DSPSC), | |
14023 | ||
14024 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
14025 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
14026 | REGDEF(DSPSC,0,DSPSC), | |
14027 | ||
14028 | /* iWMMXt data registers - p0, c0-15. */ | |
14029 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
14030 | ||
14031 | /* iWMMXt control registers - p1, c0-3. */ | |
14032 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
14033 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
14034 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
14035 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
14036 | ||
14037 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
14038 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
14039 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
14040 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
14041 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
14042 | ||
14043 | /* XScale accumulator registers. */ | |
14044 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
14045 | }; | |
14046 | #undef REGDEF | |
14047 | #undef REGNUM | |
14048 | #undef REGSET | |
7ed4c4c5 | 14049 | |
c19d1205 ZW |
14050 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
14051 | within psr_required_here. */ | |
14052 | static const struct asm_psr psrs[] = | |
14053 | { | |
14054 | /* Backward compatibility notation. Note that "all" is no longer | |
14055 | truly all possible PSR bits. */ | |
14056 | {"all", PSR_c | PSR_f}, | |
14057 | {"flg", PSR_f}, | |
14058 | {"ctl", PSR_c}, | |
14059 | ||
14060 | /* Individual flags. */ | |
14061 | {"f", PSR_f}, | |
14062 | {"c", PSR_c}, | |
14063 | {"x", PSR_x}, | |
14064 | {"s", PSR_s}, | |
14065 | /* Combinations of flags. */ | |
14066 | {"fs", PSR_f | PSR_s}, | |
14067 | {"fx", PSR_f | PSR_x}, | |
14068 | {"fc", PSR_f | PSR_c}, | |
14069 | {"sf", PSR_s | PSR_f}, | |
14070 | {"sx", PSR_s | PSR_x}, | |
14071 | {"sc", PSR_s | PSR_c}, | |
14072 | {"xf", PSR_x | PSR_f}, | |
14073 | {"xs", PSR_x | PSR_s}, | |
14074 | {"xc", PSR_x | PSR_c}, | |
14075 | {"cf", PSR_c | PSR_f}, | |
14076 | {"cs", PSR_c | PSR_s}, | |
14077 | {"cx", PSR_c | PSR_x}, | |
14078 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
14079 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
14080 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
14081 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
14082 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
14083 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
14084 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
14085 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
14086 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
14087 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
14088 | {"scf", PSR_s | PSR_c | PSR_f}, | |
14089 | {"scx", PSR_s | PSR_c | PSR_x}, | |
14090 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
14091 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
14092 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
14093 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
14094 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
14095 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
14096 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
14097 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
14098 | {"csf", PSR_c | PSR_s | PSR_f}, | |
14099 | {"csx", PSR_c | PSR_s | PSR_x}, | |
14100 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
14101 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
14102 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
14103 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
14104 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
14105 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
14106 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
14107 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
14108 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
14109 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
14110 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
14111 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
14112 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
14113 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
14114 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
14115 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
14116 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
14117 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
14118 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
14119 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
14120 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
14121 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
14122 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
14123 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
14124 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
14125 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
14126 | }; | |
14127 | ||
62b3e311 PB |
14128 | /* Table of V7M psr names. */ |
14129 | static const struct asm_psr v7m_psrs[] = | |
14130 | { | |
14131 | {"apsr", 0 }, | |
14132 | {"iapsr", 1 }, | |
14133 | {"eapsr", 2 }, | |
14134 | {"psr", 3 }, | |
14135 | {"ipsr", 5 }, | |
14136 | {"epsr", 6 }, | |
14137 | {"iepsr", 7 }, | |
14138 | {"msp", 8 }, | |
14139 | {"psp", 9 }, | |
14140 | {"primask", 16}, | |
14141 | {"basepri", 17}, | |
14142 | {"basepri_max", 18}, | |
14143 | {"faultmask", 19}, | |
14144 | {"control", 20} | |
14145 | }; | |
14146 | ||
c19d1205 ZW |
14147 | /* Table of all shift-in-operand names. */ |
14148 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 14149 | { |
c19d1205 ZW |
14150 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
14151 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
14152 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
14153 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
14154 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
14155 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } | |
14156 | }; | |
b99bd4ef | 14157 | |
c19d1205 ZW |
14158 | /* Table of all explicit relocation names. */ |
14159 | #ifdef OBJ_ELF | |
14160 | static struct reloc_entry reloc_names[] = | |
14161 | { | |
14162 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
14163 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
14164 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
14165 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
14166 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
14167 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
14168 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
14169 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
14170 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
14171 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
14172 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32} | |
14173 | }; | |
14174 | #endif | |
b99bd4ef | 14175 | |
c19d1205 ZW |
14176 | /* Table of all conditional affixes. 0xF is not defined as a condition code. */ |
14177 | static const struct asm_cond conds[] = | |
14178 | { | |
14179 | {"eq", 0x0}, | |
14180 | {"ne", 0x1}, | |
14181 | {"cs", 0x2}, {"hs", 0x2}, | |
14182 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
14183 | {"mi", 0x4}, | |
14184 | {"pl", 0x5}, | |
14185 | {"vs", 0x6}, | |
14186 | {"vc", 0x7}, | |
14187 | {"hi", 0x8}, | |
14188 | {"ls", 0x9}, | |
14189 | {"ge", 0xa}, | |
14190 | {"lt", 0xb}, | |
14191 | {"gt", 0xc}, | |
14192 | {"le", 0xd}, | |
14193 | {"al", 0xe} | |
14194 | }; | |
bfae80f2 | 14195 | |
62b3e311 PB |
14196 | static struct asm_barrier_opt barrier_opt_names[] = |
14197 | { | |
14198 | { "sy", 0xf }, | |
14199 | { "un", 0x7 }, | |
14200 | { "st", 0xe }, | |
14201 | { "unst", 0x6 } | |
14202 | }; | |
14203 | ||
c19d1205 ZW |
14204 | /* Table of ARM-format instructions. */ |
14205 | ||
14206 | /* Macros for gluing together operand strings. N.B. In all cases | |
14207 | other than OPS0, the trailing OP_stop comes from default | |
14208 | zero-initialization of the unspecified elements of the array. */ | |
14209 | #define OPS0() { OP_stop, } | |
14210 | #define OPS1(a) { OP_##a, } | |
14211 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
14212 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
14213 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
14214 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
14215 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
14216 | ||
14217 | /* These macros abstract out the exact format of the mnemonic table and | |
14218 | save some repeated characters. */ | |
14219 | ||
14220 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
14221 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
14222 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ | |
1887dd22 | 14223 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
14224 | |
14225 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
14226 | a T_MNEM_xyz enumerator. */ | |
14227 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
14228 | TxCE(mnem, aop, 0x##top, nops, ops, ae, te) | |
14229 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ | |
14230 | TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te) | |
14231 | ||
14232 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
14233 | infix after the third character. */ | |
14234 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
14235 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ | |
1887dd22 | 14236 | THUMB_VARIANT, do_##ae, do_##te } |
088fa78e KH |
14237 | #define TxC3w(mnem, op, top, nops, ops, ae, te) \ |
14238 | { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ | |
14239 | THUMB_VARIANT, do_##ae, do_##te } | |
c19d1205 ZW |
14240 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
14241 | TxC3(mnem, aop, 0x##top, nops, ops, ae, te) | |
088fa78e KH |
14242 | #define TC3w(mnem, aop, top, nops, ops, ae, te) \ |
14243 | TxC3w(mnem, aop, 0x##top, nops, ops, ae, te) | |
c19d1205 ZW |
14244 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ |
14245 | TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te) | |
088fa78e KH |
14246 | #define tC3w(mnem, aop, top, nops, ops, ae, te) \ |
14247 | TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te) | |
c19d1205 ZW |
14248 | |
14249 | /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to | |
14250 | appear in the condition table. */ | |
14251 | #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ | |
14252 | { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ | |
1887dd22 | 14253 | 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
14254 | |
14255 | #define TxCM(m1, m2, op, top, nops, ops, ae, te) \ | |
14256 | TxCM_(m1, , m2, op, top, nops, ops, ae, te), \ | |
14257 | TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \ | |
14258 | TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \ | |
14259 | TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \ | |
14260 | TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \ | |
14261 | TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \ | |
14262 | TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \ | |
14263 | TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \ | |
14264 | TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \ | |
14265 | TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \ | |
14266 | TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \ | |
14267 | TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \ | |
14268 | TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \ | |
14269 | TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \ | |
14270 | TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \ | |
14271 | TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \ | |
14272 | TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \ | |
14273 | TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \ | |
14274 | TxCM_(m1, al, m2, op, top, nops, ops, ae, te) | |
14275 | ||
14276 | #define TCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
14277 | TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te) | |
14278 | #define tCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
14279 | TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te) | |
14280 | ||
14281 | /* Mnemonic that cannot be conditionalized. The ARM condition-code | |
dfa9f0d5 PB |
14282 | field is still 0xE. Many of the Thumb variants can be executed |
14283 | conditionally, so this is checked separately. */ | |
c19d1205 ZW |
14284 | #define TUE(mnem, op, top, nops, ops, ae, te) \ |
14285 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ | |
1887dd22 | 14286 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
14287 | |
14288 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM | |
14289 | condition code field. */ | |
14290 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
14291 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ | |
1887dd22 | 14292 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
14293 | |
14294 | /* ARM-only variants of all the above. */ | |
6a86118a NC |
14295 | #define CE(mnem, op, nops, ops, ae) \ |
14296 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
14297 | ||
14298 | #define C3(mnem, op, nops, ops, ae) \ | |
14299 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
14300 | ||
e3cb604e PB |
14301 | /* Legacy mnemonics that always have conditional infix after the third |
14302 | character. */ | |
14303 | #define CL(mnem, op, nops, ops, ae) \ | |
14304 | { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ | |
14305 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
14306 | ||
8f06b2d8 PB |
14307 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
14308 | #define cCE(mnem, op, nops, ops, ae) \ | |
14309 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } | |
14310 | ||
e3cb604e PB |
14311 | /* Legacy coprocessor instructions where conditional infix and conditional |
14312 | suffix are ambiguous. For consistency this includes all FPA instructions, | |
14313 | not just the potentially ambiguous ones. */ | |
14314 | #define cCL(mnem, op, nops, ops, ae) \ | |
14315 | { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ | |
14316 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } | |
14317 | ||
14318 | /* Coprocessor, takes either a suffix or a position-3 infix | |
14319 | (for an FPA corner case). */ | |
14320 | #define C3E(mnem, op, nops, ops, ae) \ | |
14321 | { #mnem, OPS##nops ops, OT_csuf_or_in3, \ | |
14322 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } | |
8f06b2d8 | 14323 | |
6a86118a NC |
14324 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
14325 | { #m1 #m2 #m3, OPS##nops ops, \ | |
14326 | sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ | |
14327 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
14328 | ||
14329 | #define CM(m1, m2, op, nops, ops, ae) \ | |
14330 | xCM_(m1, , m2, op, nops, ops, ae), \ | |
14331 | xCM_(m1, eq, m2, op, nops, ops, ae), \ | |
14332 | xCM_(m1, ne, m2, op, nops, ops, ae), \ | |
14333 | xCM_(m1, cs, m2, op, nops, ops, ae), \ | |
14334 | xCM_(m1, hs, m2, op, nops, ops, ae), \ | |
14335 | xCM_(m1, cc, m2, op, nops, ops, ae), \ | |
14336 | xCM_(m1, ul, m2, op, nops, ops, ae), \ | |
14337 | xCM_(m1, lo, m2, op, nops, ops, ae), \ | |
14338 | xCM_(m1, mi, m2, op, nops, ops, ae), \ | |
14339 | xCM_(m1, pl, m2, op, nops, ops, ae), \ | |
14340 | xCM_(m1, vs, m2, op, nops, ops, ae), \ | |
14341 | xCM_(m1, vc, m2, op, nops, ops, ae), \ | |
14342 | xCM_(m1, hi, m2, op, nops, ops, ae), \ | |
14343 | xCM_(m1, ls, m2, op, nops, ops, ae), \ | |
14344 | xCM_(m1, ge, m2, op, nops, ops, ae), \ | |
14345 | xCM_(m1, lt, m2, op, nops, ops, ae), \ | |
14346 | xCM_(m1, gt, m2, op, nops, ops, ae), \ | |
14347 | xCM_(m1, le, m2, op, nops, ops, ae), \ | |
14348 | xCM_(m1, al, m2, op, nops, ops, ae) | |
14349 | ||
14350 | #define UE(mnem, op, nops, ops, ae) \ | |
14351 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
14352 | ||
14353 | #define UF(mnem, op, nops, ops, ae) \ | |
14354 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
14355 | ||
5287ad62 JB |
14356 | /* Neon data-processing. ARM versions are unconditional with cond=0xf. |
14357 | The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we | |
14358 | use the same encoding function for each. */ | |
14359 | #define NUF(mnem, op, nops, ops, enc) \ | |
14360 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ | |
14361 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } | |
14362 | ||
14363 | /* Neon data processing, version which indirects through neon_enc_tab for | |
14364 | the various overloaded versions of opcodes. */ | |
14365 | #define nUF(mnem, op, nops, ops, enc) \ | |
14366 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \ | |
14367 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } | |
14368 | ||
14369 | /* Neon insn with conditional suffix for the ARM version, non-overloaded | |
14370 | version. */ | |
037e8744 JB |
14371 | #define NCE_tag(mnem, op, nops, ops, enc, tag) \ |
14372 | { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ | |
5287ad62 JB |
14373 | THUMB_VARIANT, do_##enc, do_##enc } |
14374 | ||
037e8744 JB |
14375 | #define NCE(mnem, op, nops, ops, enc) \ |
14376 | NCE_tag(mnem, op, nops, ops, enc, OT_csuffix) | |
14377 | ||
14378 | #define NCEF(mnem, op, nops, ops, enc) \ | |
14379 | NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF) | |
14380 | ||
5287ad62 | 14381 | /* Neon insn with conditional suffix for the ARM version, overloaded types. */ |
037e8744 JB |
14382 | #define nCE_tag(mnem, op, nops, ops, enc, tag) \ |
14383 | { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \ | |
5287ad62 JB |
14384 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
14385 | ||
037e8744 JB |
14386 | #define nCE(mnem, op, nops, ops, enc) \ |
14387 | nCE_tag(mnem, op, nops, ops, enc, OT_csuffix) | |
14388 | ||
14389 | #define nCEF(mnem, op, nops, ops, enc) \ | |
14390 | nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF) | |
14391 | ||
c19d1205 ZW |
14392 | #define do_0 0 |
14393 | ||
14394 | /* Thumb-only, unconditional. */ | |
14395 | #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te) | |
14396 | ||
c19d1205 | 14397 | static const struct asm_opcode insns[] = |
bfae80f2 | 14398 | { |
e74cfd16 PB |
14399 | #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ |
14400 | #define THUMB_VARIANT &arm_ext_v4t | |
c19d1205 ZW |
14401 | tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c), |
14402 | tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
14403 | tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
14404 | tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
14405 | tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
14406 | tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
4962c51a MS |
14407 | tCE(add, 0800000, add, 3, (RR, oRR, SHG), arit, t_add_sub), |
14408 | tC3(adds, 0900000, adds, 3, (RR, oRR, SHG), arit, t_add_sub), | |
c19d1205 ZW |
14409 | tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c), |
14410 | tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
14411 | tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
14412 | tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
14413 | tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
14414 | tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
14415 | tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3), | |
14416 | tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3), | |
14417 | ||
14418 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
14419 | for setting PSR flag bits. They are obsolete in V6 and do not | |
14420 | have Thumb equivalents. */ | |
14421 | tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), | |
088fa78e | 14422 | tC3w(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), |
e3cb604e | 14423 | CL(tstp, 110f000, 2, (RR, SH), cmp), |
c19d1205 | 14424 | tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), |
088fa78e | 14425 | tC3w(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), |
e3cb604e | 14426 | CL(cmpp, 150f000, 2, (RR, SH), cmp), |
c19d1205 | 14427 | tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), |
088fa78e | 14428 | tC3w(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), |
e3cb604e | 14429 | CL(cmnp, 170f000, 2, (RR, SH), cmp), |
c19d1205 ZW |
14430 | |
14431 | tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp), | |
14432 | tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp), | |
14433 | tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst), | |
14434 | tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst), | |
14435 | ||
4962c51a MS |
14436 | tCE(ldr, 4100000, ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), |
14437 | tC3(ldrb, 4500000, ldrb, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
14438 | tCE(str, 4000000, str, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
14439 | tC3(strb, 4400000, strb, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
c19d1205 | 14440 | |
f5208ef2 | 14441 | tCE(stm, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
c19d1205 ZW |
14442 | tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
14443 | tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
f5208ef2 | 14444 | tCE(ldm, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
c19d1205 ZW |
14445 | tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
14446 | tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
14447 | ||
14448 | TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi), | |
c16d2bf0 | 14449 | TCE(svc, f000000, df00, 1, (EXPi), swi, t_swi), |
0110f2b8 | 14450 | tCE(b, a000000, b, 1, (EXPr), branch, t_branch), |
39b41c9c | 14451 | TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23), |
bfae80f2 | 14452 | |
c19d1205 | 14453 | /* Pseudo ops. */ |
e9f89963 | 14454 | tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac ZW |
14455 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
14456 | tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop), | |
c19d1205 ZW |
14457 | |
14458 | /* Thumb-compatibility pseudo ops. */ | |
14459 | tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift), | |
14460 | tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift), | |
14461 | tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift), | |
14462 | tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
14463 | tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift), | |
2fc8bdac | 14464 | tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift), |
c19d1205 ZW |
14465 | tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift), |
14466 | tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift), | |
14467 | tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg), | |
14468 | tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg), | |
14469 | tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop), | |
14470 | tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop), | |
14471 | ||
14472 | #undef THUMB_VARIANT | |
e74cfd16 | 14473 | #define THUMB_VARIANT &arm_ext_v6 |
2fc8bdac | 14474 | TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
14475 | |
14476 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
14477 | #undef THUMB_VARIANT | |
e74cfd16 | 14478 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
14479 | TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), |
14480 | TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
14481 | TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
088fa78e | 14482 | TC3w(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
e3cb604e | 14483 | CL(teqp, 130f000, 2, (RR, SH), cmp), |
c19d1205 ZW |
14484 | |
14485 | TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt), | |
3e94bf1a | 14486 | TC3(ldrbt, 4700000, f8100e00, 2, (RR, ADDR), ldstt, t_ldstt), |
c19d1205 | 14487 | TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt), |
3e94bf1a | 14488 | TC3(strbt, 4600000, f8000e00, 2, (RR, ADDR), ldstt, t_ldstt), |
c19d1205 | 14489 | |
9c3c69f2 PB |
14490 | TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
14491 | TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 14492 | |
9c3c69f2 PB |
14493 | TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
14494 | TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
14495 | |
14496 | /* V1 instructions with no Thumb analogue at all. */ | |
14497 | CE(rsc, 0e00000, 3, (RR, oRR, SH), arit), | |
14498 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), | |
14499 | ||
14500 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
14501 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
14502 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
14503 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
14504 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
14505 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
14506 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
14507 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
14508 | ||
14509 | #undef ARM_VARIANT | |
e74cfd16 | 14510 | #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */ |
c19d1205 | 14511 | #undef THUMB_VARIANT |
e74cfd16 | 14512 | #define THUMB_VARIANT &arm_ext_v4t |
c19d1205 ZW |
14513 | tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
14514 | tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
14515 | ||
14516 | #undef THUMB_VARIANT | |
e74cfd16 | 14517 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
14518 | TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
14519 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), | |
14520 | ||
14521 | /* Generic coprocessor instructions. */ | |
14522 | TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
4962c51a MS |
14523 | TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), |
14524 | TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
14525 | TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
14526 | TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
c19d1205 ZW |
14527 | TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), |
14528 | TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
14529 | ||
14530 | #undef ARM_VARIANT | |
e74cfd16 | 14531 | #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */ |
c19d1205 ZW |
14532 | CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
14533 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), | |
14534 | ||
14535 | #undef ARM_VARIANT | |
e74cfd16 | 14536 | #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */ |
037e8744 JB |
14537 | TCE(mrs, 10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs), |
14538 | TCE(msr, 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr), | |
c19d1205 ZW |
14539 | |
14540 | #undef ARM_VARIANT | |
e74cfd16 | 14541 | #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */ |
c19d1205 ZW |
14542 | TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
14543 | CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
14544 | TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
14545 | CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
14546 | TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
14547 | CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
14548 | TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
14549 | CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
14550 | ||
14551 | #undef ARM_VARIANT | |
e74cfd16 | 14552 | #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */ |
c19d1205 | 14553 | #undef THUMB_VARIANT |
e74cfd16 | 14554 | #define THUMB_VARIANT &arm_ext_v4t |
4962c51a MS |
14555 | tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), |
14556 | tC3(strh, 00000b0, strh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), | |
14557 | tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), | |
14558 | tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), | |
14559 | tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), | |
14560 | tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), | |
c19d1205 ZW |
14561 | |
14562 | #undef ARM_VARIANT | |
e74cfd16 | 14563 | #define ARM_VARIANT &arm_ext_v4t_5 |
c19d1205 ZW |
14564 | /* ARM Architecture 4T. */ |
14565 | /* Note: bx (and blx) are required on V5, even if the processor does | |
14566 | not support Thumb. */ | |
14567 | TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx), | |
14568 | ||
14569 | #undef ARM_VARIANT | |
e74cfd16 | 14570 | #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */ |
c19d1205 | 14571 | #undef THUMB_VARIANT |
e74cfd16 | 14572 | #define THUMB_VARIANT &arm_ext_v5t |
c19d1205 ZW |
14573 | /* Note: blx has 2 variants; the .value coded here is for |
14574 | BLX(2). Only this variant has conditional execution. */ | |
14575 | TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx), | |
14576 | TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
14577 | ||
14578 | #undef THUMB_VARIANT | |
e74cfd16 | 14579 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 | 14580 | TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
4962c51a MS |
14581 | TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), |
14582 | TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
14583 | TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
14584 | TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
c19d1205 ZW |
14585 | TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), |
14586 | TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
14587 | TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
14588 | ||
14589 | #undef ARM_VARIANT | |
e74cfd16 | 14590 | #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */ |
c19d1205 ZW |
14591 | TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
14592 | TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
14593 | TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
14594 | TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
14595 | ||
14596 | TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
14597 | TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
14598 | ||
14599 | TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
14600 | TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
14601 | TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
14602 | TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
14603 | ||
14604 | TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
14605 | TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
14606 | TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
14607 | TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
14608 | ||
14609 | TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
14610 | TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
14611 | ||
14612 | TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
14613 | TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
14614 | TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
14615 | TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
14616 | ||
14617 | #undef ARM_VARIANT | |
e74cfd16 | 14618 | #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */ |
c19d1205 | 14619 | TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld), |
4962c51a MS |
14620 | TC3(ldrd, 00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), |
14621 | TC3(strd, 00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), | |
c19d1205 ZW |
14622 | |
14623 | TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
14624 | TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
14625 | ||
14626 | #undef ARM_VARIANT | |
e74cfd16 | 14627 | #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */ |
c19d1205 ZW |
14628 | TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
14629 | ||
14630 | #undef ARM_VARIANT | |
e74cfd16 | 14631 | #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */ |
c19d1205 | 14632 | #undef THUMB_VARIANT |
e74cfd16 | 14633 | #define THUMB_VARIANT &arm_ext_v6 |
c19d1205 ZW |
14634 | TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
14635 | TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
14636 | tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
14637 | tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
14638 | tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
14639 | tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
14640 | tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
14641 | tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
14642 | tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
14643 | TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend), | |
14644 | ||
14645 | #undef THUMB_VARIANT | |
e74cfd16 | 14646 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
14647 | TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex), |
14648 | TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
14649 | TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
62b3e311 PB |
14650 | |
14651 | TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), | |
14652 | TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
14653 | ||
14654 | /* ARM V6 not included in V7M (eg. integer SIMD). */ | |
14655 | #undef THUMB_VARIANT | |
14656 | #define THUMB_VARIANT &arm_ext_v6_notm | |
dfa9f0d5 | 14657 | TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, t_cps), |
c19d1205 ZW |
14658 | TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), |
14659 | TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
14660 | TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14661 | TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14662 | TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14663 | TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14664 | TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14665 | TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14666 | TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14667 | TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14668 | TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14669 | TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14670 | TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14671 | TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14672 | TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14673 | TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14674 | TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14675 | TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14676 | TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14677 | TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14678 | TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14679 | TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14680 | TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14681 | TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14682 | TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14683 | TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14684 | TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14685 | TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14686 | TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14687 | TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14688 | TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14689 | TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14690 | TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14691 | TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14692 | TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14693 | TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14694 | TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14695 | TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
14696 | TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
14697 | UF(rfeib, 9900a00, 1, (RRw), rfe), | |
14698 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
14699 | TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
14700 | TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
14701 | UF(rfefa, 9900a00, 1, (RRw), rfe), | |
14702 | UF(rfeea, 8100a00, 1, (RRw), rfe), | |
14703 | TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
14704 | TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
14705 | TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
14706 | TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
14707 | TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
14708 | TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
14709 | TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
14710 | TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
14711 | TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
f1022c90 | 14712 | TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
c19d1205 ZW |
14713 | TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), |
14714 | TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
14715 | TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
14716 | TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
14717 | TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
14718 | TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
14719 | TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
14720 | TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
14721 | TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
14722 | TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
14723 | TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
14724 | TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
14725 | TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
14726 | TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
14727 | TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
14728 | TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
14729 | TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
14730 | TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
14731 | TUF(srsia, 8cd0500, e980c000, 1, (I31w), srs, srs), | |
14732 | UF(srsib, 9cd0500, 1, (I31w), srs), | |
14733 | UF(srsda, 84d0500, 1, (I31w), srs), | |
14734 | TUF(srsdb, 94d0500, e800c000, 1, (I31w), srs, srs), | |
c19d1205 ZW |
14735 | TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), |
14736 | TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex), | |
14737 | TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
14738 | TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
14739 | TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
c19d1205 ZW |
14740 | TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), |
14741 | ||
14742 | #undef ARM_VARIANT | |
e74cfd16 | 14743 | #define ARM_VARIANT &arm_ext_v6k |
c19d1205 | 14744 | #undef THUMB_VARIANT |
e74cfd16 | 14745 | #define THUMB_VARIANT &arm_ext_v6k |
c19d1205 ZW |
14746 | tCE(yield, 320f001, yield, 0, (), noargs, t_hint), |
14747 | tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint), | |
14748 | tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint), | |
14749 | tCE(sev, 320f004, sev, 0, (), noargs, t_hint), | |
14750 | ||
ebdca51a PB |
14751 | #undef THUMB_VARIANT |
14752 | #define THUMB_VARIANT &arm_ext_v6_notm | |
14753 | TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd), | |
14754 | TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd), | |
14755 | ||
c19d1205 | 14756 | #undef THUMB_VARIANT |
e74cfd16 | 14757 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
14758 | TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), |
14759 | TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
c19d1205 ZW |
14760 | TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), |
14761 | TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), | |
c19d1205 ZW |
14762 | TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs), |
14763 | ||
14764 | #undef ARM_VARIANT | |
e74cfd16 | 14765 | #define ARM_VARIANT &arm_ext_v6z |
3eb17e6b | 14766 | TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 ZW |
14767 | |
14768 | #undef ARM_VARIANT | |
e74cfd16 | 14769 | #define ARM_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
14770 | TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
14771 | TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
14772 | TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
14773 | TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
14774 | ||
14775 | TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), | |
b6895b4f PB |
14776 | TCE(movw, 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), |
14777 | TCE(movt, 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), | |
401a54cf | 14778 | TCE(rbit, 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), |
c19d1205 ZW |
14779 | |
14780 | TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
14781 | TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
14782 | TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
14783 | TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
14784 | ||
14785 | UT(cbnz, b900, 2, (RR, EXP), t_czb), | |
14786 | UT(cbz, b100, 2, (RR, EXP), t_czb), | |
14787 | /* ARM does not really have an IT instruction. */ | |
14788 | TUE(it, 0, bf08, 1, (COND), it, t_it), | |
14789 | TUE(itt, 0, bf0c, 1, (COND), it, t_it), | |
14790 | TUE(ite, 0, bf04, 1, (COND), it, t_it), | |
14791 | TUE(ittt, 0, bf0e, 1, (COND), it, t_it), | |
14792 | TUE(itet, 0, bf06, 1, (COND), it, t_it), | |
14793 | TUE(itte, 0, bf0a, 1, (COND), it, t_it), | |
14794 | TUE(itee, 0, bf02, 1, (COND), it, t_it), | |
14795 | TUE(itttt, 0, bf0f, 1, (COND), it, t_it), | |
14796 | TUE(itett, 0, bf07, 1, (COND), it, t_it), | |
14797 | TUE(ittet, 0, bf0b, 1, (COND), it, t_it), | |
14798 | TUE(iteet, 0, bf03, 1, (COND), it, t_it), | |
14799 | TUE(ittte, 0, bf0d, 1, (COND), it, t_it), | |
14800 | TUE(itete, 0, bf05, 1, (COND), it, t_it), | |
14801 | TUE(ittee, 0, bf09, 1, (COND), it, t_it), | |
14802 | TUE(iteee, 0, bf01, 1, (COND), it, t_it), | |
14803 | ||
92e90b6e PB |
14804 | /* Thumb2 only instructions. */ |
14805 | #undef ARM_VARIANT | |
e74cfd16 | 14806 | #define ARM_VARIANT NULL |
92e90b6e PB |
14807 | |
14808 | TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
14809 | TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
14810 | TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb), | |
14811 | TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb), | |
14812 | ||
62b3e311 PB |
14813 | /* Thumb-2 hardware division instructions (R and M profiles only). */ |
14814 | #undef THUMB_VARIANT | |
14815 | #define THUMB_VARIANT &arm_ext_div | |
14816 | TCE(sdiv, 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div), | |
14817 | TCE(udiv, 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div), | |
14818 | ||
14819 | /* ARM V7 instructions. */ | |
14820 | #undef ARM_VARIANT | |
14821 | #define ARM_VARIANT &arm_ext_v7 | |
14822 | #undef THUMB_VARIANT | |
14823 | #define THUMB_VARIANT &arm_ext_v7 | |
14824 | TUF(pli, 450f000, f910f000, 1, (ADDR), pli, t_pld), | |
14825 | TCE(dbg, 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), | |
14826 | TUF(dmb, 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier), | |
14827 | TUF(dsb, 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier), | |
14828 | TUF(isb, 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier), | |
14829 | ||
c19d1205 | 14830 | #undef ARM_VARIANT |
e74cfd16 | 14831 | #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ |
8f06b2d8 PB |
14832 | cCE(wfs, e200110, 1, (RR), rd), |
14833 | cCE(rfs, e300110, 1, (RR), rd), | |
14834 | cCE(wfc, e400110, 1, (RR), rd), | |
14835 | cCE(rfc, e500110, 1, (RR), rd), | |
14836 | ||
4962c51a MS |
14837 | cCL(ldfs, c100100, 2, (RF, ADDRGLDC), rd_cpaddr), |
14838 | cCL(ldfd, c108100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
14839 | cCL(ldfe, c500100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
14840 | cCL(ldfp, c508100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
e3cb604e | 14841 | |
4962c51a MS |
14842 | cCL(stfs, c000100, 2, (RF, ADDRGLDC), rd_cpaddr), |
14843 | cCL(stfd, c008100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
14844 | cCL(stfe, c400100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
14845 | cCL(stfp, c408100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
e3cb604e PB |
14846 | |
14847 | cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm), | |
14848 | cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm), | |
14849 | cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm), | |
14850 | cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm), | |
14851 | cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm), | |
14852 | cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm), | |
14853 | cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm), | |
14854 | cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm), | |
14855 | cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm), | |
14856 | cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm), | |
14857 | cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm), | |
14858 | cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm), | |
14859 | ||
14860 | cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm), | |
14861 | cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm), | |
14862 | cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm), | |
14863 | cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm), | |
14864 | cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm), | |
14865 | cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm), | |
14866 | cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm), | |
14867 | cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm), | |
14868 | cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm), | |
14869 | cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm), | |
14870 | cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm), | |
14871 | cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm), | |
14872 | ||
14873 | cCL(abss, e208100, 2, (RF, RF_IF), rd_rm), | |
14874 | cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm), | |
14875 | cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm), | |
14876 | cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm), | |
14877 | cCL(absd, e208180, 2, (RF, RF_IF), rd_rm), | |
14878 | cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm), | |
14879 | cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm), | |
14880 | cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm), | |
14881 | cCL(abse, e288100, 2, (RF, RF_IF), rd_rm), | |
14882 | cCL(absep, e288120, 2, (RF, RF_IF), rd_rm), | |
14883 | cCL(absem, e288140, 2, (RF, RF_IF), rd_rm), | |
14884 | cCL(absez, e288160, 2, (RF, RF_IF), rd_rm), | |
14885 | ||
14886 | cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm), | |
14887 | cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm), | |
14888 | cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm), | |
14889 | cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm), | |
14890 | cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm), | |
14891 | cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm), | |
14892 | cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm), | |
14893 | cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm), | |
14894 | cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm), | |
14895 | cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm), | |
14896 | cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm), | |
14897 | cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm), | |
14898 | ||
14899 | cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm), | |
14900 | cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm), | |
14901 | cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm), | |
14902 | cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm), | |
14903 | cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm), | |
14904 | cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm), | |
14905 | cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm), | |
14906 | cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm), | |
14907 | cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm), | |
14908 | cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm), | |
14909 | cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm), | |
14910 | cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm), | |
14911 | ||
14912 | cCL(logs, e508100, 2, (RF, RF_IF), rd_rm), | |
14913 | cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm), | |
14914 | cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm), | |
14915 | cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm), | |
14916 | cCL(logd, e508180, 2, (RF, RF_IF), rd_rm), | |
14917 | cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm), | |
14918 | cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm), | |
14919 | cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm), | |
14920 | cCL(loge, e588100, 2, (RF, RF_IF), rd_rm), | |
14921 | cCL(logep, e588120, 2, (RF, RF_IF), rd_rm), | |
14922 | cCL(logem, e588140, 2, (RF, RF_IF), rd_rm), | |
14923 | cCL(logez, e588160, 2, (RF, RF_IF), rd_rm), | |
14924 | ||
14925 | cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm), | |
14926 | cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm), | |
14927 | cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm), | |
14928 | cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm), | |
14929 | cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm), | |
14930 | cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm), | |
14931 | cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm), | |
14932 | cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm), | |
14933 | cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm), | |
14934 | cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm), | |
14935 | cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm), | |
14936 | cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm), | |
14937 | ||
14938 | cCL(exps, e708100, 2, (RF, RF_IF), rd_rm), | |
14939 | cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm), | |
14940 | cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm), | |
14941 | cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm), | |
14942 | cCL(expd, e708180, 2, (RF, RF_IF), rd_rm), | |
14943 | cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm), | |
14944 | cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm), | |
14945 | cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm), | |
14946 | cCL(expe, e788100, 2, (RF, RF_IF), rd_rm), | |
14947 | cCL(expep, e788120, 2, (RF, RF_IF), rd_rm), | |
14948 | cCL(expem, e788140, 2, (RF, RF_IF), rd_rm), | |
14949 | cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm), | |
14950 | ||
14951 | cCL(sins, e808100, 2, (RF, RF_IF), rd_rm), | |
14952 | cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm), | |
14953 | cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm), | |
14954 | cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm), | |
14955 | cCL(sind, e808180, 2, (RF, RF_IF), rd_rm), | |
14956 | cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm), | |
14957 | cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm), | |
14958 | cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm), | |
14959 | cCL(sine, e888100, 2, (RF, RF_IF), rd_rm), | |
14960 | cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm), | |
14961 | cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm), | |
14962 | cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm), | |
14963 | ||
14964 | cCL(coss, e908100, 2, (RF, RF_IF), rd_rm), | |
14965 | cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm), | |
14966 | cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm), | |
14967 | cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm), | |
14968 | cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm), | |
14969 | cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm), | |
14970 | cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm), | |
14971 | cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm), | |
14972 | cCL(cose, e988100, 2, (RF, RF_IF), rd_rm), | |
14973 | cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm), | |
14974 | cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm), | |
14975 | cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm), | |
14976 | ||
14977 | cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm), | |
14978 | cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm), | |
14979 | cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm), | |
14980 | cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm), | |
14981 | cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm), | |
14982 | cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm), | |
14983 | cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm), | |
14984 | cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm), | |
14985 | cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm), | |
14986 | cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm), | |
14987 | cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm), | |
14988 | cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm), | |
14989 | ||
14990 | cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm), | |
14991 | cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm), | |
14992 | cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm), | |
14993 | cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm), | |
14994 | cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm), | |
14995 | cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm), | |
14996 | cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm), | |
14997 | cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm), | |
14998 | cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm), | |
14999 | cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm), | |
15000 | cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm), | |
15001 | cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm), | |
15002 | ||
15003 | cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm), | |
15004 | cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm), | |
15005 | cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm), | |
15006 | cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm), | |
15007 | cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm), | |
15008 | cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm), | |
15009 | cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm), | |
15010 | cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm), | |
15011 | cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm), | |
15012 | cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm), | |
15013 | cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm), | |
15014 | cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm), | |
15015 | ||
15016 | cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm), | |
15017 | cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm), | |
15018 | cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm), | |
15019 | cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm), | |
15020 | cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm), | |
15021 | cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm), | |
15022 | cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm), | |
15023 | cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm), | |
15024 | cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm), | |
15025 | cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm), | |
15026 | cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm), | |
15027 | cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm), | |
15028 | ||
15029 | cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm), | |
15030 | cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm), | |
15031 | cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm), | |
15032 | cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm), | |
15033 | cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm), | |
15034 | cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm), | |
15035 | cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm), | |
15036 | cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm), | |
15037 | cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm), | |
15038 | cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm), | |
15039 | cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm), | |
15040 | cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm), | |
15041 | ||
15042 | cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm), | |
15043 | cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm), | |
15044 | cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm), | |
15045 | cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm), | |
15046 | cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm), | |
15047 | cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm), | |
15048 | cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm), | |
15049 | cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm), | |
15050 | cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm), | |
15051 | cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm), | |
15052 | cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm), | |
15053 | cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm), | |
15054 | ||
15055 | cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15056 | cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15057 | cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15058 | cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15059 | cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15060 | cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15061 | cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15062 | cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15063 | cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15064 | cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15065 | cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15066 | cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15067 | ||
15068 | cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15069 | cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15070 | cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15071 | cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15072 | cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15073 | cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15074 | cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15075 | cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15076 | cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15077 | cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15078 | cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15079 | cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15080 | ||
15081 | cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15082 | cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15083 | cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15084 | cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15085 | cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15086 | cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15087 | cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15088 | cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15089 | cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15090 | cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15091 | cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15092 | cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15093 | ||
15094 | cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15095 | cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15096 | cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15097 | cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15098 | cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15099 | cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15100 | cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15101 | cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15102 | cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15103 | cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15104 | cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15105 | cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15106 | ||
15107 | cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15108 | cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15109 | cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15110 | cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15111 | cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15112 | cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15113 | cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15114 | cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15115 | cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15116 | cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15117 | cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15118 | cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15119 | ||
15120 | cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15121 | cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15122 | cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15123 | cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15124 | cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15125 | cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15126 | cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15127 | cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15128 | cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15129 | cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15130 | cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15131 | cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15132 | ||
15133 | cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15134 | cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15135 | cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15136 | cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15137 | cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15138 | cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15139 | cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15140 | cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15141 | cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15142 | cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15143 | cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15144 | cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15145 | ||
15146 | cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15147 | cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15148 | cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15149 | cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15150 | cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15151 | cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15152 | cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15153 | cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15154 | cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15155 | cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15156 | cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15157 | cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15158 | ||
15159 | cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15160 | cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15161 | cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15162 | cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15163 | cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15164 | cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15165 | cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15166 | cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15167 | cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15168 | cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15169 | cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15170 | cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15171 | ||
15172 | cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15173 | cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15174 | cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15175 | cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15176 | cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15177 | cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15178 | cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15179 | cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15180 | cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15181 | cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15182 | cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15183 | cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15184 | ||
15185 | cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15186 | cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15187 | cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15188 | cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15189 | cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15190 | cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15191 | cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15192 | cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15193 | cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15194 | cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15195 | cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15196 | cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15197 | ||
15198 | cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15199 | cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15200 | cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15201 | cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15202 | cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15203 | cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15204 | cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15205 | cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15206 | cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15207 | cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15208 | cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15209 | cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15210 | ||
15211 | cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15212 | cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15213 | cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15214 | cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15215 | cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15216 | cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15217 | cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15218 | cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15219 | cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15220 | cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15221 | cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
15222 | cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8f06b2d8 PB |
15223 | |
15224 | cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp), | |
c19d1205 | 15225 | C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp), |
8f06b2d8 | 15226 | cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp), |
c19d1205 ZW |
15227 | C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp), |
15228 | ||
e3cb604e PB |
15229 | cCL(flts, e000110, 2, (RF, RR), rn_rd), |
15230 | cCL(fltsp, e000130, 2, (RF, RR), rn_rd), | |
15231 | cCL(fltsm, e000150, 2, (RF, RR), rn_rd), | |
15232 | cCL(fltsz, e000170, 2, (RF, RR), rn_rd), | |
15233 | cCL(fltd, e000190, 2, (RF, RR), rn_rd), | |
15234 | cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd), | |
15235 | cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd), | |
15236 | cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd), | |
15237 | cCL(flte, e080110, 2, (RF, RR), rn_rd), | |
15238 | cCL(fltep, e080130, 2, (RF, RR), rn_rd), | |
15239 | cCL(fltem, e080150, 2, (RF, RR), rn_rd), | |
15240 | cCL(fltez, e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 15241 | |
c19d1205 ZW |
15242 | /* The implementation of the FIX instruction is broken on some |
15243 | assemblers, in that it accepts a precision specifier as well as a | |
15244 | rounding specifier, despite the fact that this is meaningless. | |
15245 | To be more compatible, we accept it as well, though of course it | |
15246 | does not set any bits. */ | |
8f06b2d8 | 15247 | cCE(fix, e100110, 2, (RR, RF), rd_rm), |
e3cb604e PB |
15248 | cCL(fixp, e100130, 2, (RR, RF), rd_rm), |
15249 | cCL(fixm, e100150, 2, (RR, RF), rd_rm), | |
15250 | cCL(fixz, e100170, 2, (RR, RF), rd_rm), | |
15251 | cCL(fixsp, e100130, 2, (RR, RF), rd_rm), | |
15252 | cCL(fixsm, e100150, 2, (RR, RF), rd_rm), | |
15253 | cCL(fixsz, e100170, 2, (RR, RF), rd_rm), | |
15254 | cCL(fixdp, e100130, 2, (RR, RF), rd_rm), | |
15255 | cCL(fixdm, e100150, 2, (RR, RF), rd_rm), | |
15256 | cCL(fixdz, e100170, 2, (RR, RF), rd_rm), | |
15257 | cCL(fixep, e100130, 2, (RR, RF), rd_rm), | |
15258 | cCL(fixem, e100150, 2, (RR, RF), rd_rm), | |
15259 | cCL(fixez, e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 15260 | |
c19d1205 ZW |
15261 | /* Instructions that were new with the real FPA, call them V2. */ |
15262 | #undef ARM_VARIANT | |
e74cfd16 | 15263 | #define ARM_VARIANT &fpu_fpa_ext_v2 |
8f06b2d8 | 15264 | cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
e3cb604e PB |
15265 | cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
15266 | cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
8f06b2d8 | 15267 | cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
e3cb604e PB |
15268 | cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
15269 | cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 ZW |
15270 | |
15271 | #undef ARM_VARIANT | |
e74cfd16 | 15272 | #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ |
c19d1205 | 15273 | /* Moves and type conversions. */ |
8f06b2d8 PB |
15274 | cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
15275 | cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
15276 | cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
15277 | cCE(fmstat, ef1fa10, 0, (), noargs), | |
15278 | cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
15279 | cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
15280 | cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
15281 | cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
15282 | cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
15283 | cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
15284 | cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn), | |
15285 | cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
15286 | |
15287 | /* Memory operations. */ | |
4962c51a MS |
15288 | cCE(flds, d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), |
15289 | cCE(fsts, d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), | |
8f06b2d8 PB |
15290 | cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), |
15291 | cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
15292 | cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
15293 | cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
15294 | cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
15295 | cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
15296 | cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
15297 | cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
15298 | cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
15299 | cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
15300 | cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
15301 | cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
15302 | cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
15303 | cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
15304 | cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
15305 | cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 15306 | |
c19d1205 | 15307 | /* Monadic operations. */ |
8f06b2d8 PB |
15308 | cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
15309 | cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
15310 | cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
15311 | |
15312 | /* Dyadic operations. */ | |
8f06b2d8 PB |
15313 | cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
15314 | cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
15315 | cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
15316 | cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
15317 | cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
15318 | cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
15319 | cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
15320 | cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
15321 | cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 15322 | |
c19d1205 | 15323 | /* Comparisons. */ |
8f06b2d8 PB |
15324 | cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
15325 | cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z), | |
15326 | cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
15327 | cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 15328 | |
c19d1205 | 15329 | #undef ARM_VARIANT |
e74cfd16 | 15330 | #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ |
c19d1205 | 15331 | /* Moves and type conversions. */ |
5287ad62 | 15332 | cCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
8f06b2d8 PB |
15333 | cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), |
15334 | cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
5287ad62 JB |
15335 | cCE(fmdhr, e200b10, 2, (RVD, RR), vfp_dp_rn_rd), |
15336 | cCE(fmdlr, e000b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
15337 | cCE(fmrdh, e300b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
15338 | cCE(fmrdl, e100b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
8f06b2d8 PB |
15339 | cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), |
15340 | cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
15341 | cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
15342 | cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
15343 | cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
15344 | cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 ZW |
15345 | |
15346 | /* Memory operations. */ | |
4962c51a MS |
15347 | cCE(fldd, d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), |
15348 | cCE(fstd, d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
8f06b2d8 PB |
15349 | cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), |
15350 | cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
15351 | cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
15352 | cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
15353 | cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
15354 | cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
15355 | cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
15356 | cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
b99bd4ef | 15357 | |
c19d1205 | 15358 | /* Monadic operations. */ |
5287ad62 JB |
15359 | cCE(fabsd, eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
15360 | cCE(fnegd, eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), | |
15361 | cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
c19d1205 ZW |
15362 | |
15363 | /* Dyadic operations. */ | |
5287ad62 JB |
15364 | cCE(faddd, e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
15365 | cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
15366 | cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
15367 | cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
15368 | cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
15369 | cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
15370 | cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
15371 | cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
15372 | cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
b99bd4ef | 15373 | |
c19d1205 | 15374 | /* Comparisons. */ |
5287ad62 JB |
15375 | cCE(fcmpd, eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
15376 | cCE(fcmpzd, eb50b40, 1, (RVD), vfp_dp_rd), | |
15377 | cCE(fcmped, eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
15378 | cCE(fcmpezd, eb50bc0, 1, (RVD), vfp_dp_rd), | |
c19d1205 ZW |
15379 | |
15380 | #undef ARM_VARIANT | |
e74cfd16 | 15381 | #define ARM_VARIANT &fpu_vfp_ext_v2 |
8f06b2d8 PB |
15382 | cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
15383 | cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
5287ad62 JB |
15384 | cCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), |
15385 | cCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), | |
15386 | ||
037e8744 JB |
15387 | /* Instructions which may belong to either the Neon or VFP instruction sets. |
15388 | Individual encoder functions perform additional architecture checks. */ | |
15389 | #undef ARM_VARIANT | |
15390 | #define ARM_VARIANT &fpu_vfp_ext_v1xd | |
15391 | #undef THUMB_VARIANT | |
15392 | #define THUMB_VARIANT &fpu_vfp_ext_v1xd | |
15393 | /* These mnemonics are unique to VFP. */ | |
15394 | NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), | |
15395 | NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), | |
15396 | nCE(vnmul, vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
15397 | nCE(vnmla, vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
15398 | nCE(vnmls, vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
15399 | nCE(vcmp, vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
15400 | nCE(vcmpe, vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
15401 | NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), | |
15402 | NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), | |
15403 | NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), | |
15404 | ||
15405 | /* Mnemonics shared by Neon and VFP. */ | |
15406 | nCEF(vmul, vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), | |
15407 | nCEF(vmla, vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
15408 | nCEF(vmls, vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
15409 | ||
15410 | nCEF(vadd, vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), | |
15411 | nCEF(vsub, vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), | |
15412 | ||
15413 | NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
15414 | NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
15415 | ||
15416 | NCE(vldm, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), | |
15417 | NCE(vldmia, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), | |
15418 | NCE(vldmdb, d100b00, 2, (RRw, VRSDLST), neon_ldm_stm), | |
15419 | NCE(vstm, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), | |
15420 | NCE(vstmia, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), | |
15421 | NCE(vstmdb, d000b00, 2, (RRw, VRSDLST), neon_ldm_stm), | |
4962c51a MS |
15422 | NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), |
15423 | NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), | |
037e8744 JB |
15424 | |
15425 | nCEF(vcvt, vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt), | |
15426 | ||
15427 | /* NOTE: All VMOV encoding is special-cased! */ | |
15428 | NCE(vmov, 0, 1, (VMOV), neon_mov), | |
15429 | NCE(vmovq, 0, 1, (VMOV), neon_mov), | |
15430 | ||
5287ad62 JB |
15431 | #undef THUMB_VARIANT |
15432 | #define THUMB_VARIANT &fpu_neon_ext_v1 | |
15433 | #undef ARM_VARIANT | |
15434 | #define ARM_VARIANT &fpu_neon_ext_v1 | |
15435 | /* Data processing with three registers of the same length. */ | |
15436 | /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ | |
15437 | NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), | |
15438 | NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), | |
15439 | NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
15440 | NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
15441 | NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
15442 | NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
15443 | NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
15444 | NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
15445 | /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ | |
15446 | NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
15447 | NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
15448 | NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
15449 | NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
15450 | NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
15451 | NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
15452 | NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
15453 | NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
15454 | /* If not immediate, fall back to neon_dyadic_i64_su. | |
15455 | shl_imm should accept I8 I16 I32 I64, | |
15456 | qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ | |
15457 | nUF(vshl, vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), | |
15458 | nUF(vshlq, vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), | |
15459 | nUF(vqshl, vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), | |
15460 | nUF(vqshlq, vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), | |
15461 | /* Logic ops, types optional & ignored. */ | |
15462 | nUF(vand, vand, 2, (RNDQ, NILO), neon_logic), | |
15463 | nUF(vandq, vand, 2, (RNQ, NILO), neon_logic), | |
15464 | nUF(vbic, vbic, 2, (RNDQ, NILO), neon_logic), | |
15465 | nUF(vbicq, vbic, 2, (RNQ, NILO), neon_logic), | |
15466 | nUF(vorr, vorr, 2, (RNDQ, NILO), neon_logic), | |
15467 | nUF(vorrq, vorr, 2, (RNQ, NILO), neon_logic), | |
15468 | nUF(vorn, vorn, 2, (RNDQ, NILO), neon_logic), | |
15469 | nUF(vornq, vorn, 2, (RNQ, NILO), neon_logic), | |
15470 | nUF(veor, veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), | |
15471 | nUF(veorq, veor, 3, (RNQ, oRNQ, RNQ), neon_logic), | |
15472 | /* Bitfield ops, untyped. */ | |
15473 | NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
15474 | NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
15475 | NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
15476 | NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
15477 | NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
15478 | NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
15479 | /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ | |
15480 | nUF(vabd, vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
15481 | nUF(vabdq, vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
15482 | nUF(vmax, vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
15483 | nUF(vmaxq, vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
15484 | nUF(vmin, vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
15485 | nUF(vminq, vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
15486 | /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall | |
15487 | back to neon_dyadic_if_su. */ | |
15488 | nUF(vcge, vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), | |
15489 | nUF(vcgeq, vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
15490 | nUF(vcgt, vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), | |
15491 | nUF(vcgtq, vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
15492 | nUF(vclt, vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
15493 | nUF(vcltq, vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
15494 | nUF(vcle, vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
15495 | nUF(vcleq, vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
15496 | /* Comparison. Type I8 I16 I32 F32. Non-immediate -> neon_dyadic_if_i. */ | |
15497 | nUF(vceq, vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), | |
15498 | nUF(vceqq, vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), | |
15499 | /* As above, D registers only. */ | |
15500 | nUF(vpmax, vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), | |
15501 | nUF(vpmin, vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), | |
15502 | /* Int and float variants, signedness unimportant. */ | |
15503 | /* If not scalar, fall back to neon_dyadic_if_i. */ | |
5287ad62 | 15504 | nUF(vmlaq, vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
5287ad62 JB |
15505 | nUF(vmlsq, vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
15506 | nUF(vpadd, vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), | |
15507 | /* Add/sub take types I8 I16 I32 I64 F32. */ | |
5287ad62 | 15508 | nUF(vaddq, vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
5287ad62 JB |
15509 | nUF(vsubq, vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
15510 | /* vtst takes sizes 8, 16, 32. */ | |
15511 | NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), | |
15512 | NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), | |
15513 | /* VMUL takes I8 I16 I32 F32 P8. */ | |
037e8744 | 15514 | nUF(vmulq, vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), |
5287ad62 JB |
15515 | /* VQD{R}MULH takes S16 S32. */ |
15516 | nUF(vqdmulh, vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
15517 | nUF(vqdmulhq, vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
15518 | nUF(vqrdmulh, vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
15519 | nUF(vqrdmulhq, vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
15520 | NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), | |
15521 | NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
15522 | NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), | |
15523 | NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
15524 | NUF(vaclt, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), | |
15525 | NUF(vacltq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
15526 | NUF(vacle, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), | |
15527 | NUF(vacleq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
15528 | NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), | |
15529 | NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
15530 | NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), | |
15531 | NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
15532 | ||
15533 | /* Two address, int/float. Types S8 S16 S32 F32. */ | |
5287ad62 | 15534 | NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), |
5287ad62 JB |
15535 | NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), |
15536 | ||
15537 | /* Data processing with two registers and a shift amount. */ | |
15538 | /* Right shifts, and variants with rounding. | |
15539 | Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ | |
15540 | NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
15541 | NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
15542 | NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
15543 | NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
15544 | NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
15545 | NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
15546 | NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
15547 | NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
15548 | /* Shift and insert. Sizes accepted 8 16 32 64. */ | |
15549 | NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), | |
15550 | NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), | |
15551 | NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), | |
15552 | NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), | |
15553 | /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ | |
15554 | NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), | |
15555 | NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), | |
15556 | /* Right shift immediate, saturating & narrowing, with rounding variants. | |
15557 | Types accepted S16 S32 S64 U16 U32 U64. */ | |
15558 | NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
15559 | NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
15560 | /* As above, unsigned. Types accepted S16 S32 S64. */ | |
15561 | NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
15562 | NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
15563 | /* Right shift narrowing. Types accepted I16 I32 I64. */ | |
15564 | NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
15565 | NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
15566 | /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ | |
15567 | nUF(vshll, vshll, 3, (RNQ, RND, I32), neon_shll), | |
15568 | /* CVT with optional immediate for fixed-point variant. */ | |
037e8744 | 15569 | nUF(vcvtq, vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), |
b7fc2769 | 15570 | |
5287ad62 JB |
15571 | nUF(vmvn, vmvn, 2, (RNDQ, RNDQ_IMVNb), neon_mvn), |
15572 | nUF(vmvnq, vmvn, 2, (RNQ, RNDQ_IMVNb), neon_mvn), | |
15573 | ||
15574 | /* Data processing, three registers of different lengths. */ | |
15575 | /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ | |
15576 | NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), | |
15577 | NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), | |
15578 | NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), | |
15579 | NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), | |
15580 | /* If not scalar, fall back to neon_dyadic_long. | |
15581 | Vector types as above, scalar types S16 S32 U16 U32. */ | |
15582 | nUF(vmlal, vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), | |
15583 | nUF(vmlsl, vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), | |
15584 | /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ | |
15585 | NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
15586 | NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
15587 | /* Dyadic, narrowing insns. Types I16 I32 I64. */ | |
15588 | NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
15589 | NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
15590 | NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
15591 | NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
15592 | /* Saturating doubling multiplies. Types S16 S32. */ | |
15593 | nUF(vqdmlal, vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
15594 | nUF(vqdmlsl, vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
15595 | nUF(vqdmull, vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
15596 | /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types | |
15597 | S16 S32 U16 U32. */ | |
15598 | nUF(vmull, vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), | |
15599 | ||
15600 | /* Extract. Size 8. */ | |
15601 | NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I7), neon_ext), | |
15602 | NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I7), neon_ext), | |
15603 | ||
15604 | /* Two registers, miscellaneous. */ | |
15605 | /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ | |
15606 | NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), | |
15607 | NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), | |
15608 | NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), | |
15609 | NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), | |
15610 | NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), | |
15611 | NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), | |
15612 | /* Vector replicate. Sizes 8 16 32. */ | |
15613 | nCE(vdup, vdup, 2, (RNDQ, RR_RNSC), neon_dup), | |
15614 | nCE(vdupq, vdup, 2, (RNQ, RR_RNSC), neon_dup), | |
15615 | /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ | |
15616 | NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), | |
15617 | /* VMOVN. Types I16 I32 I64. */ | |
15618 | nUF(vmovn, vmovn, 2, (RND, RNQ), neon_movn), | |
15619 | /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ | |
15620 | nUF(vqmovn, vqmovn, 2, (RND, RNQ), neon_qmovn), | |
15621 | /* VQMOVUN. Types S16 S32 S64. */ | |
15622 | nUF(vqmovun, vqmovun, 2, (RND, RNQ), neon_qmovun), | |
15623 | /* VZIP / VUZP. Sizes 8 16 32. */ | |
15624 | NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
15625 | NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), | |
15626 | NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
15627 | NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), | |
15628 | /* VQABS / VQNEG. Types S8 S16 S32. */ | |
15629 | NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
15630 | NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
15631 | NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
15632 | NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
15633 | /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ | |
15634 | NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), | |
15635 | NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), | |
15636 | NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), | |
15637 | NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), | |
15638 | /* Reciprocal estimates. Types U32 F32. */ | |
15639 | NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), | |
15640 | NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), | |
15641 | NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), | |
15642 | NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), | |
15643 | /* VCLS. Types S8 S16 S32. */ | |
15644 | NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), | |
15645 | NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), | |
15646 | /* VCLZ. Types I8 I16 I32. */ | |
15647 | NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), | |
15648 | NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), | |
15649 | /* VCNT. Size 8. */ | |
15650 | NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), | |
15651 | NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), | |
15652 | /* Two address, untyped. */ | |
15653 | NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), | |
15654 | NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), | |
15655 | /* VTRN. Sizes 8 16 32. */ | |
15656 | nUF(vtrn, vtrn, 2, (RNDQ, RNDQ), neon_trn), | |
15657 | nUF(vtrnq, vtrn, 2, (RNQ, RNQ), neon_trn), | |
15658 | ||
15659 | /* Table lookup. Size 8. */ | |
15660 | NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
15661 | NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
15662 | ||
b7fc2769 JB |
15663 | #undef THUMB_VARIANT |
15664 | #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext | |
15665 | #undef ARM_VARIANT | |
15666 | #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext | |
5287ad62 JB |
15667 | /* Neon element/structure load/store. */ |
15668 | nUF(vld1, vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
15669 | nUF(vst1, vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
15670 | nUF(vld2, vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
15671 | nUF(vst2, vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
15672 | nUF(vld3, vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
15673 | nUF(vst3, vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
15674 | nUF(vld4, vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
15675 | nUF(vst4, vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
15676 | ||
15677 | #undef THUMB_VARIANT | |
15678 | #define THUMB_VARIANT &fpu_vfp_ext_v3 | |
15679 | #undef ARM_VARIANT | |
15680 | #define ARM_VARIANT &fpu_vfp_ext_v3 | |
5287ad62 JB |
15681 | cCE(fconsts, eb00a00, 2, (RVS, I255), vfp_sp_const), |
15682 | cCE(fconstd, eb00b00, 2, (RVD, I255), vfp_dp_const), | |
15683 | cCE(fshtos, eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
15684 | cCE(fshtod, eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), | |
15685 | cCE(fsltos, eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
15686 | cCE(fsltod, eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), | |
15687 | cCE(fuhtos, ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
15688 | cCE(fuhtod, ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), | |
15689 | cCE(fultos, ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
15690 | cCE(fultod, ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), | |
15691 | cCE(ftoshs, ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
15692 | cCE(ftoshd, ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), | |
15693 | cCE(ftosls, ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
15694 | cCE(ftosld, ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), | |
15695 | cCE(ftouhs, ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
15696 | cCE(ftouhd, ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), | |
15697 | cCE(ftouls, ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
15698 | cCE(ftould, ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), | |
c19d1205 | 15699 | |
5287ad62 | 15700 | #undef THUMB_VARIANT |
c19d1205 | 15701 | #undef ARM_VARIANT |
e74cfd16 | 15702 | #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */ |
8f06b2d8 PB |
15703 | cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
15704 | cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
15705 | cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
15706 | cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
15707 | cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
15708 | cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
15709 | cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
15710 | cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 ZW |
15711 | |
15712 | #undef ARM_VARIANT | |
e74cfd16 | 15713 | #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */ |
8f06b2d8 PB |
15714 | cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc), |
15715 | cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc), | |
15716 | cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc), | |
15717 | cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd), | |
15718 | cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd), | |
15719 | cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd), | |
15720 | cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc), | |
15721 | cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc), | |
15722 | cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc), | |
15723 | cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
15724 | cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
15725 | cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
15726 | cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
15727 | cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
15728 | cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
15729 | cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
15730 | cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
15731 | cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
41adaa5c | 15732 | cCE(tmcr, e000110, 2, (RIWC_RIWG, RR), rn_rd), |
8f06b2d8 PB |
15733 | cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn), |
15734 | cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
15735 | cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
15736 | cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
15737 | cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
15738 | cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
15739 | cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
15740 | cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn), | |
15741 | cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn), | |
15742 | cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn), | |
41adaa5c | 15743 | cCE(tmrc, e100110, 2, (RR, RIWC_RIWG), rd_rn), |
8f06b2d8 PB |
15744 | cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm), |
15745 | cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc), | |
15746 | cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc), | |
15747 | cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc), | |
15748 | cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn), | |
15749 | cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn), | |
15750 | cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn), | |
15751 | cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15752 | cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15753 | cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15754 | cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15755 | cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15756 | cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15757 | cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15758 | cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15759 | cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15760 | cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
15761 | cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15762 | cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15763 | cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15764 | cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15765 | cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15766 | cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15767 | cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15768 | cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15769 | cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15770 | cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15771 | cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15772 | cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15773 | cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15774 | cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15775 | cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15776 | cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15777 | cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15778 | cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15779 | cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15780 | cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
15781 | cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
15782 | cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
15783 | cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
15784 | cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15785 | cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15786 | cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15787 | cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15788 | cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15789 | cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15790 | cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15791 | cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15792 | cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15793 | cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15794 | cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15795 | cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15796 | cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15797 | cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15798 | cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15799 | cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15800 | cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15801 | cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15802 | cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
15803 | cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15804 | cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15805 | cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15806 | cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15807 | cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15808 | cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15809 | cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15810 | cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15811 | cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15812 | cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15813 | cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15814 | cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15815 | cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
15816 | cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15817 | cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
15818 | cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15819 | cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
15820 | cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15821 | cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15822 | cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15823 | cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15824 | cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
15825 | cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15826 | cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
15827 | cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15828 | cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
15829 | cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15830 | cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
15831 | cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15832 | cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
15833 | cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15834 | cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
15835 | cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15836 | cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
15837 | cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15838 | cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
15839 | cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15840 | cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
15841 | cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15842 | cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
15843 | cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
15844 | cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
15845 | cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
15846 | cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
15847 | cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15848 | cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15849 | cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15850 | cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15851 | cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15852 | cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15853 | cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15854 | cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15855 | cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15856 | cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn), | |
15857 | cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn), | |
15858 | cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn), | |
15859 | cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn), | |
15860 | cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn), | |
15861 | cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn), | |
15862 | cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15863 | cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15864 | cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15865 | cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn), | |
15866 | cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn), | |
15867 | cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn), | |
15868 | cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn), | |
15869 | cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn), | |
15870 | cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn), | |
15871 | cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15872 | cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15873 | cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15874 | cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
15875 | cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 ZW |
15876 | |
15877 | #undef ARM_VARIANT | |
e74cfd16 | 15878 | #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */ |
4962c51a MS |
15879 | cCE(cfldrs, c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), |
15880 | cCE(cfldrd, c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
15881 | cCE(cfldr32, c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
15882 | cCE(cfldr64, c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
15883 | cCE(cfstrs, c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), | |
15884 | cCE(cfstrd, c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
15885 | cCE(cfstr32, c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
15886 | cCE(cfstr64, c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
8f06b2d8 PB |
15887 | cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd), |
15888 | cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn), | |
15889 | cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd), | |
15890 | cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn), | |
15891 | cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd), | |
15892 | cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn), | |
15893 | cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd), | |
15894 | cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn), | |
15895 | cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd), | |
15896 | cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn), | |
15897 | cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn), | |
15898 | cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn), | |
15899 | cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn), | |
15900 | cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn), | |
15901 | cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn), | |
15902 | cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn), | |
15903 | cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn), | |
15904 | cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn), | |
15905 | cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn), | |
15906 | cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn), | |
15907 | cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc), | |
15908 | cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd), | |
15909 | cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn), | |
15910 | cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn), | |
15911 | cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn), | |
15912 | cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn), | |
15913 | cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn), | |
15914 | cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn), | |
15915 | cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn), | |
15916 | cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn), | |
15917 | cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn), | |
15918 | cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn), | |
15919 | cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn), | |
15920 | cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn), | |
15921 | cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple), | |
15922 | cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
15923 | cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift), | |
15924 | cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
15925 | cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
15926 | cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
15927 | cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
15928 | cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
15929 | cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn), | |
15930 | cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn), | |
15931 | cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn), | |
15932 | cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn), | |
15933 | cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
15934 | cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
15935 | cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
15936 | cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
15937 | cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
15938 | cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
15939 | cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn), | |
15940 | cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn), | |
15941 | cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn), | |
15942 | cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn), | |
15943 | cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
15944 | cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
15945 | cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
15946 | cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
15947 | cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
15948 | cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
15949 | cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
15950 | cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
15951 | cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
15952 | cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
15953 | cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
15954 | cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
c19d1205 ZW |
15955 | }; |
15956 | #undef ARM_VARIANT | |
15957 | #undef THUMB_VARIANT | |
15958 | #undef TCE | |
15959 | #undef TCM | |
15960 | #undef TUE | |
15961 | #undef TUF | |
15962 | #undef TCC | |
8f06b2d8 | 15963 | #undef cCE |
e3cb604e PB |
15964 | #undef cCL |
15965 | #undef C3E | |
c19d1205 ZW |
15966 | #undef CE |
15967 | #undef CM | |
15968 | #undef UE | |
15969 | #undef UF | |
15970 | #undef UT | |
5287ad62 JB |
15971 | #undef NUF |
15972 | #undef nUF | |
15973 | #undef NCE | |
15974 | #undef nCE | |
c19d1205 ZW |
15975 | #undef OPS0 |
15976 | #undef OPS1 | |
15977 | #undef OPS2 | |
15978 | #undef OPS3 | |
15979 | #undef OPS4 | |
15980 | #undef OPS5 | |
15981 | #undef OPS6 | |
15982 | #undef do_0 | |
15983 | \f | |
15984 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 15985 | |
c19d1205 ZW |
15986 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
15987 | for use in the a.out file, and stores them in the array pointed to by buf. | |
15988 | This knows about the endian-ness of the target machine and does | |
15989 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
15990 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
15991 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 15992 | |
c19d1205 ZW |
15993 | void |
15994 | md_number_to_chars (char * buf, valueT val, int n) | |
15995 | { | |
15996 | if (target_big_endian) | |
15997 | number_to_chars_bigendian (buf, val, n); | |
15998 | else | |
15999 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
16000 | } |
16001 | ||
c19d1205 ZW |
16002 | static valueT |
16003 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 16004 | { |
c19d1205 ZW |
16005 | valueT result = 0; |
16006 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 16007 | |
c19d1205 | 16008 | if (target_big_endian) |
b99bd4ef | 16009 | { |
c19d1205 ZW |
16010 | while (n--) |
16011 | { | |
16012 | result <<= 8; | |
16013 | result |= (*where++ & 255); | |
16014 | } | |
b99bd4ef | 16015 | } |
c19d1205 | 16016 | else |
b99bd4ef | 16017 | { |
c19d1205 ZW |
16018 | while (n--) |
16019 | { | |
16020 | result <<= 8; | |
16021 | result |= (where[n] & 255); | |
16022 | } | |
bfae80f2 | 16023 | } |
b99bd4ef | 16024 | |
c19d1205 | 16025 | return result; |
bfae80f2 | 16026 | } |
b99bd4ef | 16027 | |
c19d1205 | 16028 | /* MD interface: Sections. */ |
b99bd4ef | 16029 | |
0110f2b8 PB |
16030 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
16031 | 2 bytes. */ | |
16032 | ||
c19d1205 | 16033 | int |
0110f2b8 | 16034 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
16035 | segT segtype ATTRIBUTE_UNUSED) |
16036 | { | |
0110f2b8 PB |
16037 | fragp->fr_var = 2; |
16038 | return 2; | |
16039 | } | |
16040 | ||
16041 | /* Convert a machine dependent frag. */ | |
16042 | ||
16043 | void | |
16044 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
16045 | { | |
16046 | unsigned long insn; | |
16047 | unsigned long old_op; | |
16048 | char *buf; | |
16049 | expressionS exp; | |
16050 | fixS *fixp; | |
16051 | int reloc_type; | |
16052 | int pc_rel; | |
16053 | int opcode; | |
16054 | ||
16055 | buf = fragp->fr_literal + fragp->fr_fix; | |
16056 | ||
16057 | old_op = bfd_get_16(abfd, buf); | |
16058 | if (fragp->fr_symbol) { | |
16059 | exp.X_op = O_symbol; | |
16060 | exp.X_add_symbol = fragp->fr_symbol; | |
16061 | } else { | |
16062 | exp.X_op = O_constant; | |
16063 | } | |
16064 | exp.X_add_number = fragp->fr_offset; | |
16065 | opcode = fragp->fr_subtype; | |
16066 | switch (opcode) | |
16067 | { | |
16068 | case T_MNEM_ldr_pc: | |
16069 | case T_MNEM_ldr_pc2: | |
16070 | case T_MNEM_ldr_sp: | |
16071 | case T_MNEM_str_sp: | |
16072 | case T_MNEM_ldr: | |
16073 | case T_MNEM_ldrb: | |
16074 | case T_MNEM_ldrh: | |
16075 | case T_MNEM_str: | |
16076 | case T_MNEM_strb: | |
16077 | case T_MNEM_strh: | |
16078 | if (fragp->fr_var == 4) | |
16079 | { | |
16080 | insn = THUMB_OP32(opcode); | |
16081 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) | |
16082 | { | |
16083 | insn |= (old_op & 0x700) << 4; | |
16084 | } | |
16085 | else | |
16086 | { | |
16087 | insn |= (old_op & 7) << 12; | |
16088 | insn |= (old_op & 0x38) << 13; | |
16089 | } | |
16090 | insn |= 0x00000c00; | |
16091 | put_thumb32_insn (buf, insn); | |
16092 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
16093 | } | |
16094 | else | |
16095 | { | |
16096 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
16097 | } | |
16098 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
16099 | break; | |
16100 | case T_MNEM_adr: | |
16101 | if (fragp->fr_var == 4) | |
16102 | { | |
16103 | insn = THUMB_OP32 (opcode); | |
16104 | insn |= (old_op & 0xf0) << 4; | |
16105 | put_thumb32_insn (buf, insn); | |
16106 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
16107 | } | |
16108 | else | |
16109 | { | |
16110 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
16111 | exp.X_add_number -= 4; | |
16112 | } | |
16113 | pc_rel = 1; | |
16114 | break; | |
16115 | case T_MNEM_mov: | |
16116 | case T_MNEM_movs: | |
16117 | case T_MNEM_cmp: | |
16118 | case T_MNEM_cmn: | |
16119 | if (fragp->fr_var == 4) | |
16120 | { | |
16121 | int r0off = (opcode == T_MNEM_mov | |
16122 | || opcode == T_MNEM_movs) ? 0 : 8; | |
16123 | insn = THUMB_OP32 (opcode); | |
16124 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
16125 | insn |= (old_op & 0x700) << r0off; | |
16126 | put_thumb32_insn (buf, insn); | |
16127 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
16128 | } | |
16129 | else | |
16130 | { | |
16131 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
16132 | } | |
16133 | pc_rel = 0; | |
16134 | break; | |
16135 | case T_MNEM_b: | |
16136 | if (fragp->fr_var == 4) | |
16137 | { | |
16138 | insn = THUMB_OP32(opcode); | |
16139 | put_thumb32_insn (buf, insn); | |
16140 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
16141 | } | |
16142 | else | |
16143 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
16144 | pc_rel = 1; | |
16145 | break; | |
16146 | case T_MNEM_bcond: | |
16147 | if (fragp->fr_var == 4) | |
16148 | { | |
16149 | insn = THUMB_OP32(opcode); | |
16150 | insn |= (old_op & 0xf00) << 14; | |
16151 | put_thumb32_insn (buf, insn); | |
16152 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
16153 | } | |
16154 | else | |
16155 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
16156 | pc_rel = 1; | |
16157 | break; | |
16158 | case T_MNEM_add_sp: | |
16159 | case T_MNEM_add_pc: | |
16160 | case T_MNEM_inc_sp: | |
16161 | case T_MNEM_dec_sp: | |
16162 | if (fragp->fr_var == 4) | |
16163 | { | |
16164 | /* ??? Choose between add and addw. */ | |
16165 | insn = THUMB_OP32 (opcode); | |
16166 | insn |= (old_op & 0xf0) << 4; | |
16167 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
16168 | if (opcode == T_MNEM_add_pc) |
16169 | reloc_type = BFD_RELOC_ARM_T32_IMM12; | |
16170 | else | |
16171 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
0110f2b8 PB |
16172 | } |
16173 | else | |
16174 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
16175 | pc_rel = 0; | |
16176 | break; | |
16177 | ||
16178 | case T_MNEM_addi: | |
16179 | case T_MNEM_addis: | |
16180 | case T_MNEM_subi: | |
16181 | case T_MNEM_subis: | |
16182 | if (fragp->fr_var == 4) | |
16183 | { | |
16184 | insn = THUMB_OP32 (opcode); | |
16185 | insn |= (old_op & 0xf0) << 4; | |
16186 | insn |= (old_op & 0xf) << 16; | |
16187 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
16188 | if (insn & (1 << 20)) |
16189 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
16190 | else | |
16191 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
0110f2b8 PB |
16192 | } |
16193 | else | |
16194 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
16195 | pc_rel = 0; | |
16196 | break; | |
16197 | default: | |
16198 | abort(); | |
16199 | } | |
16200 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
16201 | reloc_type); | |
16202 | fixp->fx_file = fragp->fr_file; | |
16203 | fixp->fx_line = fragp->fr_line; | |
16204 | fragp->fr_fix += fragp->fr_var; | |
16205 | } | |
16206 | ||
16207 | /* Return the size of a relaxable immediate operand instruction. | |
16208 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
16209 | static int | |
16210 | relax_immediate (fragS *fragp, int size, int shift) | |
16211 | { | |
16212 | offsetT offset; | |
16213 | offsetT mask; | |
16214 | offsetT low; | |
16215 | ||
16216 | /* ??? Should be able to do better than this. */ | |
16217 | if (fragp->fr_symbol) | |
16218 | return 4; | |
16219 | ||
16220 | low = (1 << shift) - 1; | |
16221 | mask = (1 << (shift + size)) - (1 << shift); | |
16222 | offset = fragp->fr_offset; | |
16223 | /* Force misaligned offsets to 32-bit variant. */ | |
16224 | if (offset & low) | |
16225 | return -4; | |
16226 | if (offset & ~mask) | |
16227 | return 4; | |
16228 | return 2; | |
16229 | } | |
16230 | ||
16231 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative | |
16232 | load. */ | |
16233 | static int | |
16234 | relax_adr (fragS *fragp, asection *sec) | |
16235 | { | |
16236 | addressT addr; | |
16237 | offsetT val; | |
16238 | ||
16239 | /* Assume worst case for symbols not known to be in the same section. */ | |
16240 | if (!S_IS_DEFINED(fragp->fr_symbol) | |
16241 | || sec != S_GET_SEGMENT (fragp->fr_symbol)) | |
16242 | return 4; | |
16243 | ||
16244 | val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset; | |
16245 | addr = fragp->fr_address + fragp->fr_fix; | |
16246 | addr = (addr + 4) & ~3; | |
16247 | /* Fix the insn as the 4-byte version if the target address is not | |
16248 | sufficiently aligned. This is prevents an infinite loop when two | |
16249 | instructions have contradictory range/alignment requirements. */ | |
16250 | if (val & 3) | |
16251 | return -4; | |
16252 | val -= addr; | |
16253 | if (val < 0 || val > 1020) | |
16254 | return 4; | |
16255 | return 2; | |
16256 | } | |
16257 | ||
16258 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
16259 | static int | |
16260 | relax_addsub (fragS *fragp, asection *sec) | |
16261 | { | |
16262 | char *buf; | |
16263 | int op; | |
16264 | ||
16265 | buf = fragp->fr_literal + fragp->fr_fix; | |
16266 | op = bfd_get_16(sec->owner, buf); | |
16267 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
16268 | return relax_immediate (fragp, 8, 0); | |
16269 | else | |
16270 | return relax_immediate (fragp, 3, 0); | |
16271 | } | |
16272 | ||
16273 | ||
16274 | /* Return the size of a relaxable branch instruction. BITS is the | |
16275 | size of the offset field in the narrow instruction. */ | |
16276 | ||
16277 | static int | |
16278 | relax_branch (fragS *fragp, asection *sec, int bits) | |
16279 | { | |
16280 | addressT addr; | |
16281 | offsetT val; | |
16282 | offsetT limit; | |
16283 | ||
16284 | /* Assume worst case for symbols not known to be in the same section. */ | |
16285 | if (!S_IS_DEFINED(fragp->fr_symbol) | |
16286 | || sec != S_GET_SEGMENT (fragp->fr_symbol)) | |
16287 | return 4; | |
16288 | ||
16289 | val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset; | |
16290 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
16291 | val -= addr; | |
16292 | ||
16293 | /* Offset is a signed value *2 */ | |
16294 | limit = 1 << bits; | |
16295 | if (val >= limit || val < -limit) | |
16296 | return 4; | |
16297 | return 2; | |
16298 | } | |
16299 | ||
16300 | ||
16301 | /* Relax a machine dependent frag. This returns the amount by which | |
16302 | the current size of the frag should change. */ | |
16303 | ||
16304 | int | |
16305 | arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED) | |
16306 | { | |
16307 | int oldsize; | |
16308 | int newsize; | |
16309 | ||
16310 | oldsize = fragp->fr_var; | |
16311 | switch (fragp->fr_subtype) | |
16312 | { | |
16313 | case T_MNEM_ldr_pc2: | |
16314 | newsize = relax_adr(fragp, sec); | |
16315 | break; | |
16316 | case T_MNEM_ldr_pc: | |
16317 | case T_MNEM_ldr_sp: | |
16318 | case T_MNEM_str_sp: | |
16319 | newsize = relax_immediate(fragp, 8, 2); | |
16320 | break; | |
16321 | case T_MNEM_ldr: | |
16322 | case T_MNEM_str: | |
16323 | newsize = relax_immediate(fragp, 5, 2); | |
16324 | break; | |
16325 | case T_MNEM_ldrh: | |
16326 | case T_MNEM_strh: | |
16327 | newsize = relax_immediate(fragp, 5, 1); | |
16328 | break; | |
16329 | case T_MNEM_ldrb: | |
16330 | case T_MNEM_strb: | |
16331 | newsize = relax_immediate(fragp, 5, 0); | |
16332 | break; | |
16333 | case T_MNEM_adr: | |
16334 | newsize = relax_adr(fragp, sec); | |
16335 | break; | |
16336 | case T_MNEM_mov: | |
16337 | case T_MNEM_movs: | |
16338 | case T_MNEM_cmp: | |
16339 | case T_MNEM_cmn: | |
16340 | newsize = relax_immediate(fragp, 8, 0); | |
16341 | break; | |
16342 | case T_MNEM_b: | |
16343 | newsize = relax_branch(fragp, sec, 11); | |
16344 | break; | |
16345 | case T_MNEM_bcond: | |
16346 | newsize = relax_branch(fragp, sec, 8); | |
16347 | break; | |
16348 | case T_MNEM_add_sp: | |
16349 | case T_MNEM_add_pc: | |
16350 | newsize = relax_immediate (fragp, 8, 2); | |
16351 | break; | |
16352 | case T_MNEM_inc_sp: | |
16353 | case T_MNEM_dec_sp: | |
16354 | newsize = relax_immediate (fragp, 7, 2); | |
16355 | break; | |
16356 | case T_MNEM_addi: | |
16357 | case T_MNEM_addis: | |
16358 | case T_MNEM_subi: | |
16359 | case T_MNEM_subis: | |
16360 | newsize = relax_addsub (fragp, sec); | |
16361 | break; | |
16362 | default: | |
16363 | abort(); | |
16364 | } | |
16365 | if (newsize < 0) | |
16366 | { | |
16367 | fragp->fr_var = -newsize; | |
16368 | md_convert_frag (sec->owner, sec, fragp); | |
16369 | frag_wane(fragp); | |
16370 | return -(newsize + oldsize); | |
16371 | } | |
16372 | fragp->fr_var = newsize; | |
16373 | return newsize - oldsize; | |
c19d1205 | 16374 | } |
b99bd4ef | 16375 | |
c19d1205 | 16376 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 16377 | |
c19d1205 ZW |
16378 | valueT |
16379 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
16380 | valueT size) | |
16381 | { | |
16382 | #ifdef OBJ_ELF | |
16383 | return size; | |
16384 | #else | |
16385 | /* Round all sects to multiple of 4. */ | |
16386 | return (size + 3) & ~3; | |
16387 | #endif | |
bfae80f2 | 16388 | } |
b99bd4ef | 16389 | |
c19d1205 ZW |
16390 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
16391 | of an rs_align_code fragment. */ | |
16392 | ||
16393 | void | |
16394 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 16395 | { |
c19d1205 ZW |
16396 | static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 }; |
16397 | static char const thumb_noop[2] = { 0xc0, 0x46 }; | |
16398 | static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 }; | |
16399 | static char const thumb_bigend_noop[2] = { 0x46, 0xc0 }; | |
16400 | ||
16401 | int bytes, fix, noop_size; | |
16402 | char * p; | |
16403 | const char * noop; | |
bfae80f2 | 16404 | |
c19d1205 | 16405 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
16406 | return; |
16407 | ||
c19d1205 ZW |
16408 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
16409 | p = fragP->fr_literal + fragP->fr_fix; | |
16410 | fix = 0; | |
bfae80f2 | 16411 | |
c19d1205 ZW |
16412 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
16413 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 16414 | |
c19d1205 | 16415 | if (fragP->tc_frag_data) |
a737bd4d | 16416 | { |
c19d1205 ZW |
16417 | if (target_big_endian) |
16418 | noop = thumb_bigend_noop; | |
16419 | else | |
16420 | noop = thumb_noop; | |
16421 | noop_size = sizeof (thumb_noop); | |
7ed4c4c5 NC |
16422 | } |
16423 | else | |
16424 | { | |
c19d1205 ZW |
16425 | if (target_big_endian) |
16426 | noop = arm_bigend_noop; | |
16427 | else | |
16428 | noop = arm_noop; | |
16429 | noop_size = sizeof (arm_noop); | |
7ed4c4c5 | 16430 | } |
a737bd4d | 16431 | |
c19d1205 | 16432 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 16433 | { |
c19d1205 ZW |
16434 | fix = bytes & (noop_size - 1); |
16435 | memset (p, 0, fix); | |
16436 | p += fix; | |
16437 | bytes -= fix; | |
a737bd4d | 16438 | } |
a737bd4d | 16439 | |
c19d1205 | 16440 | while (bytes >= noop_size) |
a737bd4d | 16441 | { |
c19d1205 ZW |
16442 | memcpy (p, noop, noop_size); |
16443 | p += noop_size; | |
16444 | bytes -= noop_size; | |
16445 | fix += noop_size; | |
a737bd4d NC |
16446 | } |
16447 | ||
c19d1205 ZW |
16448 | fragP->fr_fix += fix; |
16449 | fragP->fr_var = noop_size; | |
a737bd4d NC |
16450 | } |
16451 | ||
c19d1205 ZW |
16452 | /* Called from md_do_align. Used to create an alignment |
16453 | frag in a code section. */ | |
16454 | ||
16455 | void | |
16456 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 16457 | { |
c19d1205 | 16458 | char * p; |
7ed4c4c5 | 16459 | |
c19d1205 ZW |
16460 | /* We assume that there will never be a requirement |
16461 | to support alignments greater than 32 bytes. */ | |
16462 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) | |
16463 | as_fatal (_("alignments greater than 32 bytes not supported in .text sections.")); | |
bfae80f2 | 16464 | |
c19d1205 ZW |
16465 | p = frag_var (rs_align_code, |
16466 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
16467 | 1, | |
16468 | (relax_substateT) max, | |
16469 | (symbolS *) NULL, | |
16470 | (offsetT) n, | |
16471 | (char *) NULL); | |
16472 | *p = 0; | |
16473 | } | |
bfae80f2 | 16474 | |
c19d1205 | 16475 | /* Perform target specific initialisation of a frag. */ |
bfae80f2 | 16476 | |
c19d1205 ZW |
16477 | void |
16478 | arm_init_frag (fragS * fragP) | |
16479 | { | |
16480 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
16481 | fragP->tc_frag_data = thumb_mode; | |
bfae80f2 RE |
16482 | } |
16483 | ||
c19d1205 ZW |
16484 | #ifdef OBJ_ELF |
16485 | /* When we change sections we need to issue a new mapping symbol. */ | |
16486 | ||
16487 | void | |
16488 | arm_elf_change_section (void) | |
bfae80f2 | 16489 | { |
c19d1205 ZW |
16490 | flagword flags; |
16491 | segment_info_type *seginfo; | |
bfae80f2 | 16492 | |
c19d1205 ZW |
16493 | /* Link an unlinked unwind index table section to the .text section. */ |
16494 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
16495 | && elf_linked_to_section (now_seg) == NULL) | |
16496 | elf_linked_to_section (now_seg) = text_section; | |
16497 | ||
16498 | if (!SEG_NORMAL (now_seg)) | |
bfae80f2 RE |
16499 | return; |
16500 | ||
c19d1205 ZW |
16501 | flags = bfd_get_section_flags (stdoutput, now_seg); |
16502 | ||
16503 | /* We can ignore sections that only contain debug info. */ | |
16504 | if ((flags & SEC_ALLOC) == 0) | |
16505 | return; | |
bfae80f2 | 16506 | |
c19d1205 ZW |
16507 | seginfo = seg_info (now_seg); |
16508 | mapstate = seginfo->tc_segment_info_data.mapstate; | |
16509 | marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency; | |
bfae80f2 RE |
16510 | } |
16511 | ||
c19d1205 ZW |
16512 | int |
16513 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 16514 | { |
c19d1205 ZW |
16515 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
16516 | return SHT_ARM_EXIDX; | |
e45d0630 | 16517 | |
c19d1205 ZW |
16518 | return -1; |
16519 | } | |
16520 | \f | |
16521 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 16522 | |
c19d1205 | 16523 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 16524 | |
c19d1205 | 16525 | /* Cenerate and deferred unwind frame offset. */ |
e45d0630 | 16526 | |
bfae80f2 | 16527 | static void |
c19d1205 | 16528 | flush_pending_unwind (void) |
bfae80f2 | 16529 | { |
c19d1205 | 16530 | offsetT offset; |
bfae80f2 | 16531 | |
c19d1205 ZW |
16532 | offset = unwind.pending_offset; |
16533 | unwind.pending_offset = 0; | |
16534 | if (offset != 0) | |
16535 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
16536 | } |
16537 | ||
c19d1205 ZW |
16538 | /* Add an opcode to this list for this function. Two-byte opcodes should |
16539 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
16540 | order. */ | |
16541 | ||
bfae80f2 | 16542 | static void |
c19d1205 | 16543 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 16544 | { |
c19d1205 ZW |
16545 | /* Add any deferred stack adjustment. */ |
16546 | if (unwind.pending_offset) | |
16547 | flush_pending_unwind (); | |
bfae80f2 | 16548 | |
c19d1205 | 16549 | unwind.sp_restored = 0; |
bfae80f2 | 16550 | |
c19d1205 | 16551 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 16552 | { |
c19d1205 ZW |
16553 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
16554 | if (unwind.opcodes) | |
16555 | unwind.opcodes = xrealloc (unwind.opcodes, | |
16556 | unwind.opcode_alloc); | |
16557 | else | |
16558 | unwind.opcodes = xmalloc (unwind.opcode_alloc); | |
bfae80f2 | 16559 | } |
c19d1205 | 16560 | while (length > 0) |
bfae80f2 | 16561 | { |
c19d1205 ZW |
16562 | length--; |
16563 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
16564 | op >>= 8; | |
16565 | unwind.opcode_count++; | |
bfae80f2 | 16566 | } |
bfae80f2 RE |
16567 | } |
16568 | ||
c19d1205 ZW |
16569 | /* Add unwind opcodes to adjust the stack pointer. */ |
16570 | ||
bfae80f2 | 16571 | static void |
c19d1205 | 16572 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 16573 | { |
c19d1205 | 16574 | valueT op; |
bfae80f2 | 16575 | |
c19d1205 | 16576 | if (offset > 0x200) |
bfae80f2 | 16577 | { |
c19d1205 ZW |
16578 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
16579 | char bytes[5]; | |
16580 | int n; | |
16581 | valueT o; | |
bfae80f2 | 16582 | |
c19d1205 ZW |
16583 | /* Long form: 0xb2, uleb128. */ |
16584 | /* This might not fit in a word so add the individual bytes, | |
16585 | remembering the list is built in reverse order. */ | |
16586 | o = (valueT) ((offset - 0x204) >> 2); | |
16587 | if (o == 0) | |
16588 | add_unwind_opcode (0, 1); | |
bfae80f2 | 16589 | |
c19d1205 ZW |
16590 | /* Calculate the uleb128 encoding of the offset. */ |
16591 | n = 0; | |
16592 | while (o) | |
16593 | { | |
16594 | bytes[n] = o & 0x7f; | |
16595 | o >>= 7; | |
16596 | if (o) | |
16597 | bytes[n] |= 0x80; | |
16598 | n++; | |
16599 | } | |
16600 | /* Add the insn. */ | |
16601 | for (; n; n--) | |
16602 | add_unwind_opcode (bytes[n - 1], 1); | |
16603 | add_unwind_opcode (0xb2, 1); | |
16604 | } | |
16605 | else if (offset > 0x100) | |
bfae80f2 | 16606 | { |
c19d1205 ZW |
16607 | /* Two short opcodes. */ |
16608 | add_unwind_opcode (0x3f, 1); | |
16609 | op = (offset - 0x104) >> 2; | |
16610 | add_unwind_opcode (op, 1); | |
bfae80f2 | 16611 | } |
c19d1205 ZW |
16612 | else if (offset > 0) |
16613 | { | |
16614 | /* Short opcode. */ | |
16615 | op = (offset - 4) >> 2; | |
16616 | add_unwind_opcode (op, 1); | |
16617 | } | |
16618 | else if (offset < 0) | |
bfae80f2 | 16619 | { |
c19d1205 ZW |
16620 | offset = -offset; |
16621 | while (offset > 0x100) | |
bfae80f2 | 16622 | { |
c19d1205 ZW |
16623 | add_unwind_opcode (0x7f, 1); |
16624 | offset -= 0x100; | |
bfae80f2 | 16625 | } |
c19d1205 ZW |
16626 | op = ((offset - 4) >> 2) | 0x40; |
16627 | add_unwind_opcode (op, 1); | |
bfae80f2 | 16628 | } |
bfae80f2 RE |
16629 | } |
16630 | ||
c19d1205 ZW |
16631 | /* Finish the list of unwind opcodes for this function. */ |
16632 | static void | |
16633 | finish_unwind_opcodes (void) | |
bfae80f2 | 16634 | { |
c19d1205 | 16635 | valueT op; |
bfae80f2 | 16636 | |
c19d1205 | 16637 | if (unwind.fp_used) |
bfae80f2 | 16638 | { |
708587a4 | 16639 | /* Adjust sp as necessary. */ |
c19d1205 ZW |
16640 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; |
16641 | flush_pending_unwind (); | |
bfae80f2 | 16642 | |
c19d1205 ZW |
16643 | /* After restoring sp from the frame pointer. */ |
16644 | op = 0x90 | unwind.fp_reg; | |
16645 | add_unwind_opcode (op, 1); | |
16646 | } | |
16647 | else | |
16648 | flush_pending_unwind (); | |
bfae80f2 RE |
16649 | } |
16650 | ||
bfae80f2 | 16651 | |
c19d1205 ZW |
16652 | /* Start an exception table entry. If idx is nonzero this is an index table |
16653 | entry. */ | |
bfae80f2 RE |
16654 | |
16655 | static void | |
c19d1205 | 16656 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 16657 | { |
c19d1205 ZW |
16658 | const char * text_name; |
16659 | const char * prefix; | |
16660 | const char * prefix_once; | |
16661 | const char * group_name; | |
16662 | size_t prefix_len; | |
16663 | size_t text_len; | |
16664 | char * sec_name; | |
16665 | size_t sec_name_len; | |
16666 | int type; | |
16667 | int flags; | |
16668 | int linkonce; | |
bfae80f2 | 16669 | |
c19d1205 | 16670 | if (idx) |
bfae80f2 | 16671 | { |
c19d1205 ZW |
16672 | prefix = ELF_STRING_ARM_unwind; |
16673 | prefix_once = ELF_STRING_ARM_unwind_once; | |
16674 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 16675 | } |
c19d1205 | 16676 | else |
bfae80f2 | 16677 | { |
c19d1205 ZW |
16678 | prefix = ELF_STRING_ARM_unwind_info; |
16679 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
16680 | type = SHT_PROGBITS; | |
bfae80f2 RE |
16681 | } |
16682 | ||
c19d1205 ZW |
16683 | text_name = segment_name (text_seg); |
16684 | if (streq (text_name, ".text")) | |
16685 | text_name = ""; | |
16686 | ||
16687 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
16688 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 16689 | { |
c19d1205 ZW |
16690 | prefix = prefix_once; |
16691 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
16692 | } |
16693 | ||
c19d1205 ZW |
16694 | prefix_len = strlen (prefix); |
16695 | text_len = strlen (text_name); | |
16696 | sec_name_len = prefix_len + text_len; | |
16697 | sec_name = xmalloc (sec_name_len + 1); | |
16698 | memcpy (sec_name, prefix, prefix_len); | |
16699 | memcpy (sec_name + prefix_len, text_name, text_len); | |
16700 | sec_name[prefix_len + text_len] = '\0'; | |
bfae80f2 | 16701 | |
c19d1205 ZW |
16702 | flags = SHF_ALLOC; |
16703 | linkonce = 0; | |
16704 | group_name = 0; | |
bfae80f2 | 16705 | |
c19d1205 ZW |
16706 | /* Handle COMDAT group. */ |
16707 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 16708 | { |
c19d1205 ZW |
16709 | group_name = elf_group_name (text_seg); |
16710 | if (group_name == NULL) | |
16711 | { | |
16712 | as_bad ("Group section `%s' has no group signature", | |
16713 | segment_name (text_seg)); | |
16714 | ignore_rest_of_line (); | |
16715 | return; | |
16716 | } | |
16717 | flags |= SHF_GROUP; | |
16718 | linkonce = 1; | |
bfae80f2 RE |
16719 | } |
16720 | ||
c19d1205 | 16721 | obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); |
bfae80f2 | 16722 | |
c19d1205 ZW |
16723 | /* Set the setion link for index tables. */ |
16724 | if (idx) | |
16725 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
16726 | } |
16727 | ||
bfae80f2 | 16728 | |
c19d1205 ZW |
16729 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
16730 | personality routine data. Returns zero, or the index table value for | |
16731 | and inline entry. */ | |
16732 | ||
16733 | static valueT | |
16734 | create_unwind_entry (int have_data) | |
bfae80f2 | 16735 | { |
c19d1205 ZW |
16736 | int size; |
16737 | addressT where; | |
16738 | char *ptr; | |
16739 | /* The current word of data. */ | |
16740 | valueT data; | |
16741 | /* The number of bytes left in this word. */ | |
16742 | int n; | |
bfae80f2 | 16743 | |
c19d1205 | 16744 | finish_unwind_opcodes (); |
bfae80f2 | 16745 | |
c19d1205 ZW |
16746 | /* Remember the current text section. */ |
16747 | unwind.saved_seg = now_seg; | |
16748 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 16749 | |
c19d1205 | 16750 | start_unwind_section (now_seg, 0); |
bfae80f2 | 16751 | |
c19d1205 | 16752 | if (unwind.personality_routine == NULL) |
bfae80f2 | 16753 | { |
c19d1205 ZW |
16754 | if (unwind.personality_index == -2) |
16755 | { | |
16756 | if (have_data) | |
16757 | as_bad (_("handerdata in cantunwind frame")); | |
16758 | return 1; /* EXIDX_CANTUNWIND. */ | |
16759 | } | |
bfae80f2 | 16760 | |
c19d1205 ZW |
16761 | /* Use a default personality routine if none is specified. */ |
16762 | if (unwind.personality_index == -1) | |
16763 | { | |
16764 | if (unwind.opcode_count > 3) | |
16765 | unwind.personality_index = 1; | |
16766 | else | |
16767 | unwind.personality_index = 0; | |
16768 | } | |
bfae80f2 | 16769 | |
c19d1205 ZW |
16770 | /* Space for the personality routine entry. */ |
16771 | if (unwind.personality_index == 0) | |
16772 | { | |
16773 | if (unwind.opcode_count > 3) | |
16774 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 16775 | |
c19d1205 ZW |
16776 | if (!have_data) |
16777 | { | |
16778 | /* All the data is inline in the index table. */ | |
16779 | data = 0x80; | |
16780 | n = 3; | |
16781 | while (unwind.opcode_count > 0) | |
16782 | { | |
16783 | unwind.opcode_count--; | |
16784 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
16785 | n--; | |
16786 | } | |
bfae80f2 | 16787 | |
c19d1205 ZW |
16788 | /* Pad with "finish" opcodes. */ |
16789 | while (n--) | |
16790 | data = (data << 8) | 0xb0; | |
bfae80f2 | 16791 | |
c19d1205 ZW |
16792 | return data; |
16793 | } | |
16794 | size = 0; | |
16795 | } | |
16796 | else | |
16797 | /* We get two opcodes "free" in the first word. */ | |
16798 | size = unwind.opcode_count - 2; | |
16799 | } | |
16800 | else | |
16801 | /* An extra byte is required for the opcode count. */ | |
16802 | size = unwind.opcode_count + 1; | |
bfae80f2 | 16803 | |
c19d1205 ZW |
16804 | size = (size + 3) >> 2; |
16805 | if (size > 0xff) | |
16806 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 16807 | |
c19d1205 ZW |
16808 | frag_align (2, 0, 0); |
16809 | record_alignment (now_seg, 2); | |
16810 | unwind.table_entry = expr_build_dot (); | |
16811 | ||
16812 | /* Allocate the table entry. */ | |
16813 | ptr = frag_more ((size << 2) + 4); | |
16814 | where = frag_now_fix () - ((size << 2) + 4); | |
bfae80f2 | 16815 | |
c19d1205 | 16816 | switch (unwind.personality_index) |
bfae80f2 | 16817 | { |
c19d1205 ZW |
16818 | case -1: |
16819 | /* ??? Should this be a PLT generating relocation? */ | |
16820 | /* Custom personality routine. */ | |
16821 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
16822 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 16823 | |
c19d1205 ZW |
16824 | where += 4; |
16825 | ptr += 4; | |
bfae80f2 | 16826 | |
c19d1205 ZW |
16827 | /* Set the first byte to the number of additional words. */ |
16828 | data = size - 1; | |
16829 | n = 3; | |
16830 | break; | |
bfae80f2 | 16831 | |
c19d1205 ZW |
16832 | /* ABI defined personality routines. */ |
16833 | case 0: | |
16834 | /* Three opcodes bytes are packed into the first word. */ | |
16835 | data = 0x80; | |
16836 | n = 3; | |
16837 | break; | |
bfae80f2 | 16838 | |
c19d1205 ZW |
16839 | case 1: |
16840 | case 2: | |
16841 | /* The size and first two opcode bytes go in the first word. */ | |
16842 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
16843 | n = 2; | |
16844 | break; | |
bfae80f2 | 16845 | |
c19d1205 ZW |
16846 | default: |
16847 | /* Should never happen. */ | |
16848 | abort (); | |
16849 | } | |
bfae80f2 | 16850 | |
c19d1205 ZW |
16851 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
16852 | time. */ | |
16853 | while (unwind.opcode_count > 0) | |
16854 | { | |
16855 | if (n == 0) | |
16856 | { | |
16857 | md_number_to_chars (ptr, data, 4); | |
16858 | ptr += 4; | |
16859 | n = 4; | |
16860 | data = 0; | |
16861 | } | |
16862 | unwind.opcode_count--; | |
16863 | n--; | |
16864 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
16865 | } | |
16866 | ||
16867 | /* Finish off the last word. */ | |
16868 | if (n < 4) | |
16869 | { | |
16870 | /* Pad with "finish" opcodes. */ | |
16871 | while (n--) | |
16872 | data = (data << 8) | 0xb0; | |
16873 | ||
16874 | md_number_to_chars (ptr, data, 4); | |
16875 | } | |
16876 | ||
16877 | if (!have_data) | |
16878 | { | |
16879 | /* Add an empty descriptor if there is no user-specified data. */ | |
16880 | ptr = frag_more (4); | |
16881 | md_number_to_chars (ptr, 0, 4); | |
16882 | } | |
16883 | ||
16884 | return 0; | |
bfae80f2 RE |
16885 | } |
16886 | ||
c19d1205 ZW |
16887 | /* Convert REGNAME to a DWARF-2 register number. */ |
16888 | ||
16889 | int | |
1df69f4f | 16890 | tc_arm_regname_to_dw2regnum (char *regname) |
bfae80f2 | 16891 | { |
1df69f4f | 16892 | int reg = arm_reg_parse (®name, REG_TYPE_RN); |
c19d1205 ZW |
16893 | |
16894 | if (reg == FAIL) | |
16895 | return -1; | |
16896 | ||
16897 | return reg; | |
bfae80f2 RE |
16898 | } |
16899 | ||
c19d1205 ZW |
16900 | /* Initialize the DWARF-2 unwind information for this procedure. */ |
16901 | ||
16902 | void | |
16903 | tc_arm_frame_initial_instructions (void) | |
bfae80f2 | 16904 | { |
c19d1205 | 16905 | cfi_add_CFA_def_cfa (REG_SP, 0); |
bfae80f2 | 16906 | } |
c19d1205 | 16907 | #endif /* OBJ_ELF */ |
bfae80f2 | 16908 | |
bfae80f2 | 16909 | |
c19d1205 | 16910 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 16911 | |
2fc8bdac ZW |
16912 | /* Return the address within the segment that a PC-relative fixup is |
16913 | relative to. For ARM, PC-relative fixups applied to instructions | |
16914 | are generally relative to the location of the fixup plus 8 bytes. | |
16915 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
16916 | require special handling. */ | |
bfae80f2 | 16917 | |
c19d1205 | 16918 | long |
2fc8bdac | 16919 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 16920 | { |
2fc8bdac ZW |
16921 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
16922 | ||
16923 | /* If this is pc-relative and we are going to emit a relocation | |
16924 | then we just want to put out any pipeline compensation that the linker | |
53baae48 NC |
16925 | will need. Otherwise we want to use the calculated base. |
16926 | For WinCE we skip the bias for externals as well, since this | |
16927 | is how the MS ARM-CE assembler behaves and we want to be compatible. */ | |
2fc8bdac ZW |
16928 | if (fixP->fx_pcrel |
16929 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
53baae48 NC |
16930 | || (arm_force_relocation (fixP) |
16931 | #ifdef TE_WINCE | |
16932 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
16933 | #endif | |
16934 | ))) | |
2fc8bdac | 16935 | base = 0; |
bfae80f2 | 16936 | |
c19d1205 | 16937 | switch (fixP->fx_r_type) |
bfae80f2 | 16938 | { |
2fc8bdac ZW |
16939 | /* PC relative addressing on the Thumb is slightly odd as the |
16940 | bottom two bits of the PC are forced to zero for the | |
16941 | calculation. This happens *after* application of the | |
16942 | pipeline offset. However, Thumb adrl already adjusts for | |
16943 | this, so we need not do it again. */ | |
c19d1205 | 16944 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 16945 | return base & ~3; |
c19d1205 ZW |
16946 | |
16947 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
16948 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 16949 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 16950 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 16951 | return (base + 4) & ~3; |
c19d1205 | 16952 | |
2fc8bdac ZW |
16953 | /* Thumb branches are simply offset by +4. */ |
16954 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
16955 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
16956 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
16957 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
16958 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
16959 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
16960 | case BFD_RELOC_THUMB_PCREL_BLX: | |
16961 | return base + 4; | |
bfae80f2 | 16962 | |
2fc8bdac ZW |
16963 | /* ARM mode branches are offset by +8. However, the Windows CE |
16964 | loader expects the relocation not to take this into account. */ | |
16965 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
39b41c9c PB |
16966 | case BFD_RELOC_ARM_PCREL_CALL: |
16967 | case BFD_RELOC_ARM_PCREL_JUMP: | |
2fc8bdac ZW |
16968 | case BFD_RELOC_ARM_PCREL_BLX: |
16969 | case BFD_RELOC_ARM_PLT32: | |
c19d1205 | 16970 | #ifdef TE_WINCE |
53baae48 NC |
16971 | /* When handling fixups immediately, because we have already |
16972 | discovered the value of a symbol, or the address of the frag involved | |
16973 | we must account for the offset by +8, as the OS loader will never see the reloc. | |
16974 | see fixup_segment() in write.c | |
16975 | The S_IS_EXTERNAL test handles the case of global symbols. | |
16976 | Those need the calculated base, not just the pipe compensation the linker will need. */ | |
16977 | if (fixP->fx_pcrel | |
16978 | && fixP->fx_addsy != NULL | |
16979 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
16980 | && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) | |
16981 | return base + 8; | |
2fc8bdac | 16982 | return base; |
c19d1205 | 16983 | #else |
2fc8bdac | 16984 | return base + 8; |
c19d1205 | 16985 | #endif |
2fc8bdac ZW |
16986 | |
16987 | /* ARM mode loads relative to PC are also offset by +8. Unlike | |
16988 | branches, the Windows CE loader *does* expect the relocation | |
16989 | to take this into account. */ | |
16990 | case BFD_RELOC_ARM_OFFSET_IMM: | |
16991 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
16992 | case BFD_RELOC_ARM_HWLITERAL: | |
16993 | case BFD_RELOC_ARM_LITERAL: | |
16994 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
16995 | return base + 8; | |
16996 | ||
16997 | ||
16998 | /* Other PC-relative relocations are un-offset. */ | |
16999 | default: | |
17000 | return base; | |
17001 | } | |
bfae80f2 RE |
17002 | } |
17003 | ||
c19d1205 ZW |
17004 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. |
17005 | Otherwise we have no need to default values of symbols. */ | |
17006 | ||
17007 | symbolS * | |
17008 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
bfae80f2 | 17009 | { |
c19d1205 ZW |
17010 | #ifdef OBJ_ELF |
17011 | if (name[0] == '_' && name[1] == 'G' | |
17012 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
17013 | { | |
17014 | if (!GOT_symbol) | |
17015 | { | |
17016 | if (symbol_find (name)) | |
17017 | as_bad ("GOT already in the symbol table"); | |
bfae80f2 | 17018 | |
c19d1205 ZW |
17019 | GOT_symbol = symbol_new (name, undefined_section, |
17020 | (valueT) 0, & zero_address_frag); | |
17021 | } | |
bfae80f2 | 17022 | |
c19d1205 | 17023 | return GOT_symbol; |
bfae80f2 | 17024 | } |
c19d1205 | 17025 | #endif |
bfae80f2 | 17026 | |
c19d1205 | 17027 | return 0; |
bfae80f2 RE |
17028 | } |
17029 | ||
55cf6793 | 17030 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
17031 | computed as two separate immediate values, added together. We |
17032 | already know that this value cannot be computed by just one ARM | |
17033 | instruction. */ | |
17034 | ||
17035 | static unsigned int | |
17036 | validate_immediate_twopart (unsigned int val, | |
17037 | unsigned int * highpart) | |
bfae80f2 | 17038 | { |
c19d1205 ZW |
17039 | unsigned int a; |
17040 | unsigned int i; | |
bfae80f2 | 17041 | |
c19d1205 ZW |
17042 | for (i = 0; i < 32; i += 2) |
17043 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
17044 | { | |
17045 | if (a & 0xff00) | |
17046 | { | |
17047 | if (a & ~ 0xffff) | |
17048 | continue; | |
17049 | * highpart = (a >> 8) | ((i + 24) << 7); | |
17050 | } | |
17051 | else if (a & 0xff0000) | |
17052 | { | |
17053 | if (a & 0xff000000) | |
17054 | continue; | |
17055 | * highpart = (a >> 16) | ((i + 16) << 7); | |
17056 | } | |
17057 | else | |
17058 | { | |
17059 | assert (a & 0xff000000); | |
17060 | * highpart = (a >> 24) | ((i + 8) << 7); | |
17061 | } | |
bfae80f2 | 17062 | |
c19d1205 ZW |
17063 | return (a & 0xff) | (i << 7); |
17064 | } | |
bfae80f2 | 17065 | |
c19d1205 | 17066 | return FAIL; |
bfae80f2 RE |
17067 | } |
17068 | ||
c19d1205 ZW |
17069 | static int |
17070 | validate_offset_imm (unsigned int val, int hwse) | |
17071 | { | |
17072 | if ((hwse && val > 255) || val > 4095) | |
17073 | return FAIL; | |
17074 | return val; | |
17075 | } | |
bfae80f2 | 17076 | |
55cf6793 | 17077 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
17078 | negative immediate constant by altering the instruction. A bit of |
17079 | a hack really. | |
17080 | MOV <-> MVN | |
17081 | AND <-> BIC | |
17082 | ADC <-> SBC | |
17083 | by inverting the second operand, and | |
17084 | ADD <-> SUB | |
17085 | CMP <-> CMN | |
17086 | by negating the second operand. */ | |
bfae80f2 | 17087 | |
c19d1205 ZW |
17088 | static int |
17089 | negate_data_op (unsigned long * instruction, | |
17090 | unsigned long value) | |
bfae80f2 | 17091 | { |
c19d1205 ZW |
17092 | int op, new_inst; |
17093 | unsigned long negated, inverted; | |
bfae80f2 | 17094 | |
c19d1205 ZW |
17095 | negated = encode_arm_immediate (-value); |
17096 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 17097 | |
c19d1205 ZW |
17098 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
17099 | switch (op) | |
bfae80f2 | 17100 | { |
c19d1205 ZW |
17101 | /* First negates. */ |
17102 | case OPCODE_SUB: /* ADD <-> SUB */ | |
17103 | new_inst = OPCODE_ADD; | |
17104 | value = negated; | |
17105 | break; | |
bfae80f2 | 17106 | |
c19d1205 ZW |
17107 | case OPCODE_ADD: |
17108 | new_inst = OPCODE_SUB; | |
17109 | value = negated; | |
17110 | break; | |
bfae80f2 | 17111 | |
c19d1205 ZW |
17112 | case OPCODE_CMP: /* CMP <-> CMN */ |
17113 | new_inst = OPCODE_CMN; | |
17114 | value = negated; | |
17115 | break; | |
bfae80f2 | 17116 | |
c19d1205 ZW |
17117 | case OPCODE_CMN: |
17118 | new_inst = OPCODE_CMP; | |
17119 | value = negated; | |
17120 | break; | |
bfae80f2 | 17121 | |
c19d1205 ZW |
17122 | /* Now Inverted ops. */ |
17123 | case OPCODE_MOV: /* MOV <-> MVN */ | |
17124 | new_inst = OPCODE_MVN; | |
17125 | value = inverted; | |
17126 | break; | |
bfae80f2 | 17127 | |
c19d1205 ZW |
17128 | case OPCODE_MVN: |
17129 | new_inst = OPCODE_MOV; | |
17130 | value = inverted; | |
17131 | break; | |
bfae80f2 | 17132 | |
c19d1205 ZW |
17133 | case OPCODE_AND: /* AND <-> BIC */ |
17134 | new_inst = OPCODE_BIC; | |
17135 | value = inverted; | |
17136 | break; | |
bfae80f2 | 17137 | |
c19d1205 ZW |
17138 | case OPCODE_BIC: |
17139 | new_inst = OPCODE_AND; | |
17140 | value = inverted; | |
17141 | break; | |
bfae80f2 | 17142 | |
c19d1205 ZW |
17143 | case OPCODE_ADC: /* ADC <-> SBC */ |
17144 | new_inst = OPCODE_SBC; | |
17145 | value = inverted; | |
17146 | break; | |
bfae80f2 | 17147 | |
c19d1205 ZW |
17148 | case OPCODE_SBC: |
17149 | new_inst = OPCODE_ADC; | |
17150 | value = inverted; | |
17151 | break; | |
bfae80f2 | 17152 | |
c19d1205 ZW |
17153 | /* We cannot do anything. */ |
17154 | default: | |
17155 | return FAIL; | |
b99bd4ef NC |
17156 | } |
17157 | ||
c19d1205 ZW |
17158 | if (value == (unsigned) FAIL) |
17159 | return FAIL; | |
17160 | ||
17161 | *instruction &= OPCODE_MASK; | |
17162 | *instruction |= new_inst << DATA_OP_SHIFT; | |
17163 | return value; | |
b99bd4ef NC |
17164 | } |
17165 | ||
ef8d22e6 PB |
17166 | /* Like negate_data_op, but for Thumb-2. */ |
17167 | ||
17168 | static unsigned int | |
17169 | thumb32_negate_data_op (offsetT *instruction, offsetT value) | |
17170 | { | |
17171 | int op, new_inst; | |
17172 | int rd; | |
17173 | offsetT negated, inverted; | |
17174 | ||
17175 | negated = encode_thumb32_immediate (-value); | |
17176 | inverted = encode_thumb32_immediate (~value); | |
17177 | ||
17178 | rd = (*instruction >> 8) & 0xf; | |
17179 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; | |
17180 | switch (op) | |
17181 | { | |
17182 | /* ADD <-> SUB. Includes CMP <-> CMN. */ | |
17183 | case T2_OPCODE_SUB: | |
17184 | new_inst = T2_OPCODE_ADD; | |
17185 | value = negated; | |
17186 | break; | |
17187 | ||
17188 | case T2_OPCODE_ADD: | |
17189 | new_inst = T2_OPCODE_SUB; | |
17190 | value = negated; | |
17191 | break; | |
17192 | ||
17193 | /* ORR <-> ORN. Includes MOV <-> MVN. */ | |
17194 | case T2_OPCODE_ORR: | |
17195 | new_inst = T2_OPCODE_ORN; | |
17196 | value = inverted; | |
17197 | break; | |
17198 | ||
17199 | case T2_OPCODE_ORN: | |
17200 | new_inst = T2_OPCODE_ORR; | |
17201 | value = inverted; | |
17202 | break; | |
17203 | ||
17204 | /* AND <-> BIC. TST has no inverted equivalent. */ | |
17205 | case T2_OPCODE_AND: | |
17206 | new_inst = T2_OPCODE_BIC; | |
17207 | if (rd == 15) | |
17208 | value = FAIL; | |
17209 | else | |
17210 | value = inverted; | |
17211 | break; | |
17212 | ||
17213 | case T2_OPCODE_BIC: | |
17214 | new_inst = T2_OPCODE_AND; | |
17215 | value = inverted; | |
17216 | break; | |
17217 | ||
17218 | /* ADC <-> SBC */ | |
17219 | case T2_OPCODE_ADC: | |
17220 | new_inst = T2_OPCODE_SBC; | |
17221 | value = inverted; | |
17222 | break; | |
17223 | ||
17224 | case T2_OPCODE_SBC: | |
17225 | new_inst = T2_OPCODE_ADC; | |
17226 | value = inverted; | |
17227 | break; | |
17228 | ||
17229 | /* We cannot do anything. */ | |
17230 | default: | |
17231 | return FAIL; | |
17232 | } | |
17233 | ||
17234 | if (value == FAIL) | |
17235 | return FAIL; | |
17236 | ||
17237 | *instruction &= T2_OPCODE_MASK; | |
17238 | *instruction |= new_inst << T2_DATA_OP_SHIFT; | |
17239 | return value; | |
17240 | } | |
17241 | ||
8f06b2d8 PB |
17242 | /* Read a 32-bit thumb instruction from buf. */ |
17243 | static unsigned long | |
17244 | get_thumb32_insn (char * buf) | |
17245 | { | |
17246 | unsigned long insn; | |
17247 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
17248 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
17249 | ||
17250 | return insn; | |
17251 | } | |
17252 | ||
a8bc6c78 PB |
17253 | |
17254 | /* We usually want to set the low bit on the address of thumb function | |
17255 | symbols. In particular .word foo - . should have the low bit set. | |
17256 | Generic code tries to fold the difference of two symbols to | |
17257 | a constant. Prevent this and force a relocation when the first symbols | |
17258 | is a thumb function. */ | |
17259 | int | |
17260 | arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) | |
17261 | { | |
17262 | if (op == O_subtract | |
17263 | && l->X_op == O_symbol | |
17264 | && r->X_op == O_symbol | |
17265 | && THUMB_IS_FUNC (l->X_add_symbol)) | |
17266 | { | |
17267 | l->X_op = O_subtract; | |
17268 | l->X_op_symbol = r->X_add_symbol; | |
17269 | l->X_add_number -= r->X_add_number; | |
17270 | return 1; | |
17271 | } | |
17272 | /* Process as normal. */ | |
17273 | return 0; | |
17274 | } | |
17275 | ||
c19d1205 | 17276 | void |
55cf6793 | 17277 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
17278 | valueT * valP, |
17279 | segT seg) | |
17280 | { | |
17281 | offsetT value = * valP; | |
17282 | offsetT newval; | |
17283 | unsigned int newimm; | |
17284 | unsigned long temp; | |
17285 | int sign; | |
17286 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 17287 | |
c19d1205 | 17288 | assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 17289 | |
c19d1205 | 17290 | /* Note whether this will delete the relocation. */ |
4962c51a | 17291 | |
c19d1205 ZW |
17292 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) |
17293 | fixP->fx_done = 1; | |
b99bd4ef | 17294 | |
adbaf948 ZW |
17295 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
17296 | consistency with the behavior on 32-bit hosts. Remember value | |
17297 | for emit_reloc. */ | |
17298 | value &= 0xffffffff; | |
17299 | value ^= 0x80000000; | |
17300 | value -= 0x80000000; | |
17301 | ||
17302 | *valP = value; | |
c19d1205 | 17303 | fixP->fx_addnumber = value; |
b99bd4ef | 17304 | |
adbaf948 ZW |
17305 | /* Same treatment for fixP->fx_offset. */ |
17306 | fixP->fx_offset &= 0xffffffff; | |
17307 | fixP->fx_offset ^= 0x80000000; | |
17308 | fixP->fx_offset -= 0x80000000; | |
17309 | ||
c19d1205 | 17310 | switch (fixP->fx_r_type) |
b99bd4ef | 17311 | { |
c19d1205 ZW |
17312 | case BFD_RELOC_NONE: |
17313 | /* This will need to go in the object file. */ | |
17314 | fixP->fx_done = 0; | |
17315 | break; | |
b99bd4ef | 17316 | |
c19d1205 ZW |
17317 | case BFD_RELOC_ARM_IMMEDIATE: |
17318 | /* We claim that this fixup has been processed here, | |
17319 | even if in fact we generate an error because we do | |
17320 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
17321 | fixP->fx_done = 1; | |
b99bd4ef | 17322 | |
c19d1205 ZW |
17323 | if (fixP->fx_addsy |
17324 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
b99bd4ef | 17325 | { |
c19d1205 ZW |
17326 | as_bad_where (fixP->fx_file, fixP->fx_line, |
17327 | _("undefined symbol %s used as an immediate value"), | |
17328 | S_GET_NAME (fixP->fx_addsy)); | |
17329 | break; | |
b99bd4ef NC |
17330 | } |
17331 | ||
c19d1205 ZW |
17332 | newimm = encode_arm_immediate (value); |
17333 | temp = md_chars_to_number (buf, INSN_SIZE); | |
17334 | ||
17335 | /* If the instruction will fail, see if we can fix things up by | |
17336 | changing the opcode. */ | |
17337 | if (newimm == (unsigned int) FAIL | |
17338 | && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) | |
b99bd4ef | 17339 | { |
c19d1205 ZW |
17340 | as_bad_where (fixP->fx_file, fixP->fx_line, |
17341 | _("invalid constant (%lx) after fixup"), | |
17342 | (unsigned long) value); | |
17343 | break; | |
b99bd4ef | 17344 | } |
b99bd4ef | 17345 | |
c19d1205 ZW |
17346 | newimm |= (temp & 0xfffff000); |
17347 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
17348 | break; | |
b99bd4ef | 17349 | |
c19d1205 ZW |
17350 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
17351 | { | |
17352 | unsigned int highpart = 0; | |
17353 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 17354 | |
c19d1205 ZW |
17355 | newimm = encode_arm_immediate (value); |
17356 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 17357 | |
c19d1205 ZW |
17358 | /* If the instruction will fail, see if we can fix things up by |
17359 | changing the opcode. */ | |
17360 | if (newimm == (unsigned int) FAIL | |
17361 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
17362 | { | |
17363 | /* No ? OK - try using two ADD instructions to generate | |
17364 | the value. */ | |
17365 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 17366 | |
c19d1205 ZW |
17367 | /* Yes - then make sure that the second instruction is |
17368 | also an add. */ | |
17369 | if (newimm != (unsigned int) FAIL) | |
17370 | newinsn = temp; | |
17371 | /* Still No ? Try using a negated value. */ | |
17372 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
17373 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
17374 | /* Otherwise - give up. */ | |
17375 | else | |
17376 | { | |
17377 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17378 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
17379 | (long) value); | |
17380 | break; | |
17381 | } | |
b99bd4ef | 17382 | |
c19d1205 ZW |
17383 | /* Replace the first operand in the 2nd instruction (which |
17384 | is the PC) with the destination register. We have | |
17385 | already added in the PC in the first instruction and we | |
17386 | do not want to do it again. */ | |
17387 | newinsn &= ~ 0xf0000; | |
17388 | newinsn |= ((newinsn & 0x0f000) << 4); | |
17389 | } | |
b99bd4ef | 17390 | |
c19d1205 ZW |
17391 | newimm |= (temp & 0xfffff000); |
17392 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 17393 | |
c19d1205 ZW |
17394 | highpart |= (newinsn & 0xfffff000); |
17395 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
17396 | } | |
17397 | break; | |
b99bd4ef | 17398 | |
c19d1205 | 17399 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
17400 | if (!fixP->fx_done && seg->use_rela_p) |
17401 | value = 0; | |
17402 | ||
c19d1205 ZW |
17403 | case BFD_RELOC_ARM_LITERAL: |
17404 | sign = value >= 0; | |
b99bd4ef | 17405 | |
c19d1205 ZW |
17406 | if (value < 0) |
17407 | value = - value; | |
b99bd4ef | 17408 | |
c19d1205 | 17409 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 17410 | { |
c19d1205 ZW |
17411 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
17412 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17413 | _("invalid literal constant: pool needs to be closer")); | |
17414 | else | |
17415 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17416 | _("bad immediate value for offset (%ld)"), | |
17417 | (long) value); | |
17418 | break; | |
f03698e6 RE |
17419 | } |
17420 | ||
c19d1205 ZW |
17421 | newval = md_chars_to_number (buf, INSN_SIZE); |
17422 | newval &= 0xff7ff000; | |
17423 | newval |= value | (sign ? INDEX_UP : 0); | |
17424 | md_number_to_chars (buf, newval, INSN_SIZE); | |
17425 | break; | |
b99bd4ef | 17426 | |
c19d1205 ZW |
17427 | case BFD_RELOC_ARM_OFFSET_IMM8: |
17428 | case BFD_RELOC_ARM_HWLITERAL: | |
17429 | sign = value >= 0; | |
b99bd4ef | 17430 | |
c19d1205 ZW |
17431 | if (value < 0) |
17432 | value = - value; | |
b99bd4ef | 17433 | |
c19d1205 | 17434 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 17435 | { |
c19d1205 ZW |
17436 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
17437 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17438 | _("invalid literal constant: pool needs to be closer")); | |
17439 | else | |
17440 | as_bad (_("bad immediate value for half-word offset (%ld)"), | |
17441 | (long) value); | |
17442 | break; | |
b99bd4ef NC |
17443 | } |
17444 | ||
c19d1205 ZW |
17445 | newval = md_chars_to_number (buf, INSN_SIZE); |
17446 | newval &= 0xff7ff0f0; | |
17447 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
17448 | md_number_to_chars (buf, newval, INSN_SIZE); | |
17449 | break; | |
b99bd4ef | 17450 | |
c19d1205 ZW |
17451 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
17452 | if (value < 0 || value > 1020 || value % 4 != 0) | |
17453 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17454 | _("bad immediate value for offset (%ld)"), (long) value); | |
17455 | value /= 4; | |
b99bd4ef | 17456 | |
c19d1205 | 17457 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
17458 | newval |= value; |
17459 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
17460 | break; | |
b99bd4ef | 17461 | |
c19d1205 ZW |
17462 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
17463 | /* This is a complicated relocation used for all varieties of Thumb32 | |
17464 | load/store instruction with immediate offset: | |
17465 | ||
17466 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
17467 | *4, optional writeback(W) | |
17468 | (doubleword load/store) | |
17469 | ||
17470 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
17471 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
17472 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
17473 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
17474 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
17475 | ||
17476 | Uppercase letters indicate bits that are already encoded at | |
17477 | this point. Lowercase letters are our problem. For the | |
17478 | second block of instructions, the secondary opcode nybble | |
17479 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
17480 | a PC-relative operation. */ | |
17481 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
17482 | newval <<= 16; | |
17483 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 17484 | |
c19d1205 | 17485 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 17486 | { |
c19d1205 ZW |
17487 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
17488 | if (value >= 0) | |
17489 | newval |= (1 << 23); | |
17490 | else | |
17491 | value = -value; | |
17492 | if (value % 4 != 0) | |
17493 | { | |
17494 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17495 | _("offset not a multiple of 4")); | |
17496 | break; | |
17497 | } | |
17498 | value /= 4; | |
216d22bc | 17499 | if (value > 0xff) |
c19d1205 ZW |
17500 | { |
17501 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17502 | _("offset out of range")); | |
17503 | break; | |
17504 | } | |
17505 | newval &= ~0xff; | |
b99bd4ef | 17506 | } |
c19d1205 | 17507 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 17508 | { |
c19d1205 ZW |
17509 | /* PC-relative, 12-bit offset. */ |
17510 | if (value >= 0) | |
17511 | newval |= (1 << 23); | |
17512 | else | |
17513 | value = -value; | |
216d22bc | 17514 | if (value > 0xfff) |
c19d1205 ZW |
17515 | { |
17516 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17517 | _("offset out of range")); | |
17518 | break; | |
17519 | } | |
17520 | newval &= ~0xfff; | |
b99bd4ef | 17521 | } |
c19d1205 | 17522 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 17523 | { |
c19d1205 ZW |
17524 | /* Writeback: 8-bit, +/- offset. */ |
17525 | if (value >= 0) | |
17526 | newval |= (1 << 9); | |
17527 | else | |
17528 | value = -value; | |
216d22bc | 17529 | if (value > 0xff) |
c19d1205 ZW |
17530 | { |
17531 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17532 | _("offset out of range")); | |
17533 | break; | |
17534 | } | |
17535 | newval &= ~0xff; | |
b99bd4ef | 17536 | } |
c19d1205 | 17537 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 17538 | { |
c19d1205 | 17539 | /* T-instruction: positive 8-bit offset. */ |
216d22bc | 17540 | if (value < 0 || value > 0xff) |
b99bd4ef | 17541 | { |
c19d1205 ZW |
17542 | as_bad_where (fixP->fx_file, fixP->fx_line, |
17543 | _("offset out of range")); | |
17544 | break; | |
b99bd4ef | 17545 | } |
c19d1205 ZW |
17546 | newval &= ~0xff; |
17547 | newval |= value; | |
b99bd4ef NC |
17548 | } |
17549 | else | |
b99bd4ef | 17550 | { |
c19d1205 ZW |
17551 | /* Positive 12-bit or negative 8-bit offset. */ |
17552 | int limit; | |
17553 | if (value >= 0) | |
b99bd4ef | 17554 | { |
c19d1205 ZW |
17555 | newval |= (1 << 23); |
17556 | limit = 0xfff; | |
17557 | } | |
17558 | else | |
17559 | { | |
17560 | value = -value; | |
17561 | limit = 0xff; | |
17562 | } | |
17563 | if (value > limit) | |
17564 | { | |
17565 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17566 | _("offset out of range")); | |
17567 | break; | |
b99bd4ef | 17568 | } |
c19d1205 | 17569 | newval &= ~limit; |
b99bd4ef | 17570 | } |
b99bd4ef | 17571 | |
c19d1205 ZW |
17572 | newval |= value; |
17573 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
17574 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
17575 | break; | |
404ff6b5 | 17576 | |
c19d1205 ZW |
17577 | case BFD_RELOC_ARM_SHIFT_IMM: |
17578 | newval = md_chars_to_number (buf, INSN_SIZE); | |
17579 | if (((unsigned long) value) > 32 | |
17580 | || (value == 32 | |
17581 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
17582 | { | |
17583 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17584 | _("shift expression is too large")); | |
17585 | break; | |
17586 | } | |
404ff6b5 | 17587 | |
c19d1205 ZW |
17588 | if (value == 0) |
17589 | /* Shifts of zero must be done as lsl. */ | |
17590 | newval &= ~0x60; | |
17591 | else if (value == 32) | |
17592 | value = 0; | |
17593 | newval &= 0xfffff07f; | |
17594 | newval |= (value & 0x1f) << 7; | |
17595 | md_number_to_chars (buf, newval, INSN_SIZE); | |
17596 | break; | |
404ff6b5 | 17597 | |
c19d1205 | 17598 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
16805f35 | 17599 | case BFD_RELOC_ARM_T32_ADD_IMM: |
92e90b6e | 17600 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 17601 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
17602 | /* We claim that this fixup has been processed here, |
17603 | even if in fact we generate an error because we do | |
17604 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
17605 | fixP->fx_done = 1; | |
404ff6b5 | 17606 | |
c19d1205 ZW |
17607 | if (fixP->fx_addsy |
17608 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
17609 | { | |
17610 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17611 | _("undefined symbol %s used as an immediate value"), | |
17612 | S_GET_NAME (fixP->fx_addsy)); | |
17613 | break; | |
17614 | } | |
404ff6b5 | 17615 | |
c19d1205 ZW |
17616 | newval = md_chars_to_number (buf, THUMB_SIZE); |
17617 | newval <<= 16; | |
17618 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 17619 | |
16805f35 PB |
17620 | newimm = FAIL; |
17621 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE | |
17622 | || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
ef8d22e6 PB |
17623 | { |
17624 | newimm = encode_thumb32_immediate (value); | |
17625 | if (newimm == (unsigned int) FAIL) | |
17626 | newimm = thumb32_negate_data_op (&newval, value); | |
17627 | } | |
16805f35 PB |
17628 | if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE |
17629 | && newimm == (unsigned int) FAIL) | |
92e90b6e | 17630 | { |
16805f35 PB |
17631 | /* Turn add/sum into addw/subw. */ |
17632 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
17633 | newval = (newval & 0xfeffffff) | 0x02000000; | |
17634 | ||
e9f89963 PB |
17635 | /* 12 bit immediate for addw/subw. */ |
17636 | if (value < 0) | |
17637 | { | |
17638 | value = -value; | |
17639 | newval ^= 0x00a00000; | |
17640 | } | |
92e90b6e PB |
17641 | if (value > 0xfff) |
17642 | newimm = (unsigned int) FAIL; | |
17643 | else | |
17644 | newimm = value; | |
17645 | } | |
cc8a6dd0 | 17646 | |
c19d1205 | 17647 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 17648 | { |
c19d1205 ZW |
17649 | as_bad_where (fixP->fx_file, fixP->fx_line, |
17650 | _("invalid constant (%lx) after fixup"), | |
17651 | (unsigned long) value); | |
17652 | break; | |
3631a3c8 NC |
17653 | } |
17654 | ||
c19d1205 ZW |
17655 | newval |= (newimm & 0x800) << 15; |
17656 | newval |= (newimm & 0x700) << 4; | |
17657 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 17658 | |
c19d1205 ZW |
17659 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
17660 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
17661 | break; | |
a737bd4d | 17662 | |
3eb17e6b | 17663 | case BFD_RELOC_ARM_SMC: |
c19d1205 ZW |
17664 | if (((unsigned long) value) > 0xffff) |
17665 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3eb17e6b | 17666 | _("invalid smc expression")); |
2fc8bdac | 17667 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
17668 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
17669 | md_number_to_chars (buf, newval, INSN_SIZE); | |
17670 | break; | |
a737bd4d | 17671 | |
c19d1205 | 17672 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 17673 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
17674 | { |
17675 | if (((unsigned long) value) > 0xff) | |
17676 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17677 | _("invalid swi expression")); | |
2fc8bdac | 17678 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
17679 | newval |= value; |
17680 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
17681 | } | |
17682 | else | |
17683 | { | |
17684 | if (((unsigned long) value) > 0x00ffffff) | |
17685 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17686 | _("invalid swi expression")); | |
2fc8bdac | 17687 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
17688 | newval |= value; |
17689 | md_number_to_chars (buf, newval, INSN_SIZE); | |
17690 | } | |
17691 | break; | |
a737bd4d | 17692 | |
c19d1205 ZW |
17693 | case BFD_RELOC_ARM_MULTI: |
17694 | if (((unsigned long) value) > 0xffff) | |
17695 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17696 | _("invalid expression in load/store multiple")); | |
17697 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
17698 | md_number_to_chars (buf, newval, INSN_SIZE); | |
17699 | break; | |
a737bd4d | 17700 | |
c19d1205 | 17701 | #ifdef OBJ_ELF |
39b41c9c PB |
17702 | case BFD_RELOC_ARM_PCREL_CALL: |
17703 | newval = md_chars_to_number (buf, INSN_SIZE); | |
17704 | if ((newval & 0xf0000000) == 0xf0000000) | |
17705 | temp = 1; | |
17706 | else | |
17707 | temp = 3; | |
17708 | goto arm_branch_common; | |
17709 | ||
17710 | case BFD_RELOC_ARM_PCREL_JUMP: | |
2fc8bdac | 17711 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 17712 | #endif |
39b41c9c PB |
17713 | case BFD_RELOC_ARM_PCREL_BRANCH: |
17714 | temp = 3; | |
17715 | goto arm_branch_common; | |
a737bd4d | 17716 | |
39b41c9c PB |
17717 | case BFD_RELOC_ARM_PCREL_BLX: |
17718 | temp = 1; | |
17719 | arm_branch_common: | |
c19d1205 | 17720 | /* We are going to store value (shifted right by two) in the |
39b41c9c PB |
17721 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
17722 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must | |
17723 | also be be clear. */ | |
17724 | if (value & temp) | |
c19d1205 | 17725 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
17726 | _("misaligned branch destination")); |
17727 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
17728 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
17729 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17730 | _("branch out of range")); | |
a737bd4d | 17731 | |
2fc8bdac | 17732 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 17733 | { |
2fc8bdac ZW |
17734 | newval = md_chars_to_number (buf, INSN_SIZE); |
17735 | newval |= (value >> 2) & 0x00ffffff; | |
7ae2971b PB |
17736 | /* Set the H bit on BLX instructions. */ |
17737 | if (temp == 1) | |
17738 | { | |
17739 | if (value & 2) | |
17740 | newval |= 0x01000000; | |
17741 | else | |
17742 | newval &= ~0x01000000; | |
17743 | } | |
2fc8bdac | 17744 | md_number_to_chars (buf, newval, INSN_SIZE); |
c19d1205 | 17745 | } |
c19d1205 | 17746 | break; |
a737bd4d | 17747 | |
c19d1205 | 17748 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */ |
2fc8bdac ZW |
17749 | /* CZB can only branch forward. */ |
17750 | if (value & ~0x7e) | |
17751 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17752 | _("branch out of range")); | |
a737bd4d | 17753 | |
2fc8bdac ZW |
17754 | if (fixP->fx_done || !seg->use_rela_p) |
17755 | { | |
17756 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
080eb7fe | 17757 | newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); |
2fc8bdac ZW |
17758 | md_number_to_chars (buf, newval, THUMB_SIZE); |
17759 | } | |
c19d1205 | 17760 | break; |
a737bd4d | 17761 | |
c19d1205 | 17762 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac ZW |
17763 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
17764 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17765 | _("branch out of range")); | |
a737bd4d | 17766 | |
2fc8bdac ZW |
17767 | if (fixP->fx_done || !seg->use_rela_p) |
17768 | { | |
17769 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
17770 | newval |= (value & 0x1ff) >> 1; | |
17771 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
17772 | } | |
c19d1205 | 17773 | break; |
a737bd4d | 17774 | |
c19d1205 | 17775 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac ZW |
17776 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
17777 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17778 | _("branch out of range")); | |
a737bd4d | 17779 | |
2fc8bdac ZW |
17780 | if (fixP->fx_done || !seg->use_rela_p) |
17781 | { | |
17782 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
17783 | newval |= (value & 0xfff) >> 1; | |
17784 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
17785 | } | |
c19d1205 | 17786 | break; |
a737bd4d | 17787 | |
c19d1205 | 17788 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
2fc8bdac ZW |
17789 | if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) |
17790 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17791 | _("conditional branch out of range")); | |
404ff6b5 | 17792 | |
2fc8bdac ZW |
17793 | if (fixP->fx_done || !seg->use_rela_p) |
17794 | { | |
17795 | offsetT newval2; | |
17796 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 17797 | |
2fc8bdac ZW |
17798 | S = (value & 0x00100000) >> 20; |
17799 | J2 = (value & 0x00080000) >> 19; | |
17800 | J1 = (value & 0x00040000) >> 18; | |
17801 | hi = (value & 0x0003f000) >> 12; | |
17802 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 17803 | |
2fc8bdac ZW |
17804 | newval = md_chars_to_number (buf, THUMB_SIZE); |
17805 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
17806 | newval |= (S << 10) | hi; | |
17807 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
17808 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
17809 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
17810 | } | |
c19d1205 | 17811 | break; |
6c43fab6 | 17812 | |
c19d1205 ZW |
17813 | case BFD_RELOC_THUMB_PCREL_BLX: |
17814 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
2fc8bdac ZW |
17815 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
17816 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17817 | _("branch out of range")); | |
404ff6b5 | 17818 | |
2fc8bdac ZW |
17819 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
17820 | /* For a BLX instruction, make sure that the relocation is rounded up | |
17821 | to a word boundary. This follows the semantics of the instruction | |
17822 | which specifies that bit 1 of the target address will come from bit | |
17823 | 1 of the base address. */ | |
17824 | value = (value + 1) & ~ 1; | |
404ff6b5 | 17825 | |
2fc8bdac | 17826 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 17827 | { |
2fc8bdac ZW |
17828 | offsetT newval2; |
17829 | ||
17830 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
17831 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
17832 | newval |= (value & 0x7fffff) >> 12; | |
17833 | newval2 |= (value & 0xfff) >> 1; | |
17834 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
17835 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
c19d1205 | 17836 | } |
c19d1205 | 17837 | break; |
404ff6b5 | 17838 | |
c19d1205 | 17839 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac ZW |
17840 | if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) |
17841 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17842 | _("branch out of range")); | |
6c43fab6 | 17843 | |
2fc8bdac ZW |
17844 | if (fixP->fx_done || !seg->use_rela_p) |
17845 | { | |
17846 | offsetT newval2; | |
17847 | addressT S, I1, I2, lo, hi; | |
6c43fab6 | 17848 | |
2fc8bdac ZW |
17849 | S = (value & 0x01000000) >> 24; |
17850 | I1 = (value & 0x00800000) >> 23; | |
17851 | I2 = (value & 0x00400000) >> 22; | |
17852 | hi = (value & 0x003ff000) >> 12; | |
17853 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 17854 | |
2fc8bdac ZW |
17855 | I1 = !(I1 ^ S); |
17856 | I2 = !(I2 ^ S); | |
a737bd4d | 17857 | |
2fc8bdac ZW |
17858 | newval = md_chars_to_number (buf, THUMB_SIZE); |
17859 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
17860 | newval |= (S << 10) | hi; | |
17861 | newval2 |= (I1 << 13) | (I2 << 11) | lo; | |
17862 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
17863 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
17864 | } | |
17865 | break; | |
a737bd4d | 17866 | |
2fc8bdac ZW |
17867 | case BFD_RELOC_8: |
17868 | if (fixP->fx_done || !seg->use_rela_p) | |
17869 | md_number_to_chars (buf, value, 1); | |
c19d1205 | 17870 | break; |
a737bd4d | 17871 | |
c19d1205 | 17872 | case BFD_RELOC_16: |
2fc8bdac | 17873 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 17874 | md_number_to_chars (buf, value, 2); |
c19d1205 | 17875 | break; |
a737bd4d | 17876 | |
c19d1205 ZW |
17877 | #ifdef OBJ_ELF |
17878 | case BFD_RELOC_ARM_TLS_GD32: | |
17879 | case BFD_RELOC_ARM_TLS_LE32: | |
17880 | case BFD_RELOC_ARM_TLS_IE32: | |
17881 | case BFD_RELOC_ARM_TLS_LDM32: | |
17882 | case BFD_RELOC_ARM_TLS_LDO32: | |
17883 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
17884 | /* fall through */ | |
6c43fab6 | 17885 | |
c19d1205 ZW |
17886 | case BFD_RELOC_ARM_GOT32: |
17887 | case BFD_RELOC_ARM_GOTOFF: | |
17888 | case BFD_RELOC_ARM_TARGET2: | |
2fc8bdac ZW |
17889 | if (fixP->fx_done || !seg->use_rela_p) |
17890 | md_number_to_chars (buf, 0, 4); | |
c19d1205 ZW |
17891 | break; |
17892 | #endif | |
6c43fab6 | 17893 | |
c19d1205 ZW |
17894 | case BFD_RELOC_RVA: |
17895 | case BFD_RELOC_32: | |
17896 | case BFD_RELOC_ARM_TARGET1: | |
17897 | case BFD_RELOC_ARM_ROSEGREL32: | |
17898 | case BFD_RELOC_ARM_SBREL32: | |
17899 | case BFD_RELOC_32_PCREL: | |
2fc8bdac | 17900 | if (fixP->fx_done || !seg->use_rela_p) |
53baae48 NC |
17901 | #ifdef TE_WINCE |
17902 | /* For WinCE we only do this for pcrel fixups. */ | |
17903 | if (fixP->fx_done || fixP->fx_pcrel) | |
17904 | #endif | |
17905 | md_number_to_chars (buf, value, 4); | |
c19d1205 | 17906 | break; |
6c43fab6 | 17907 | |
c19d1205 ZW |
17908 | #ifdef OBJ_ELF |
17909 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 17910 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
17911 | { |
17912 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
17913 | if ((value ^ (value >> 1)) & 0x40000000) | |
17914 | { | |
17915 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17916 | _("rel31 relocation overflow")); | |
17917 | } | |
17918 | newval |= value & 0x7fffffff; | |
17919 | md_number_to_chars (buf, newval, 4); | |
17920 | } | |
17921 | break; | |
c19d1205 | 17922 | #endif |
a737bd4d | 17923 | |
c19d1205 | 17924 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 17925 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
c19d1205 ZW |
17926 | if (value < -1023 || value > 1023 || (value & 3)) |
17927 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17928 | _("co-processor offset out of range")); | |
17929 | cp_off_common: | |
17930 | sign = value >= 0; | |
17931 | if (value < 0) | |
17932 | value = -value; | |
8f06b2d8 PB |
17933 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
17934 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
17935 | newval = md_chars_to_number (buf, INSN_SIZE); | |
17936 | else | |
17937 | newval = get_thumb32_insn (buf); | |
17938 | newval &= 0xff7fff00; | |
c19d1205 ZW |
17939 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); |
17940 | if (value == 0) | |
17941 | newval &= ~WRITE_BACK; | |
8f06b2d8 PB |
17942 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
17943 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
17944 | md_number_to_chars (buf, newval, INSN_SIZE); | |
17945 | else | |
17946 | put_thumb32_insn (buf, newval); | |
c19d1205 | 17947 | break; |
a737bd4d | 17948 | |
c19d1205 | 17949 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 17950 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
17951 | if (value < -255 || value > 255) |
17952 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17953 | _("co-processor offset out of range")); | |
df7849c5 | 17954 | value *= 4; |
c19d1205 | 17955 | goto cp_off_common; |
6c43fab6 | 17956 | |
c19d1205 ZW |
17957 | case BFD_RELOC_ARM_THUMB_OFFSET: |
17958 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
17959 | /* Exactly what ranges, and where the offset is inserted depends | |
17960 | on the type of instruction, we can establish this from the | |
17961 | top 4 bits. */ | |
17962 | switch (newval >> 12) | |
17963 | { | |
17964 | case 4: /* PC load. */ | |
17965 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
17966 | forced to zero for these loads; md_pcrel_from has already | |
17967 | compensated for this. */ | |
17968 | if (value & 3) | |
17969 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17970 | _("invalid offset, target not word aligned (0x%08lX)"), | |
0359e808 NC |
17971 | (((unsigned long) fixP->fx_frag->fr_address |
17972 | + (unsigned long) fixP->fx_where) & ~3) | |
17973 | + (unsigned long) value); | |
a737bd4d | 17974 | |
c19d1205 ZW |
17975 | if (value & ~0x3fc) |
17976 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17977 | _("invalid offset, value too big (0x%08lX)"), | |
17978 | (long) value); | |
a737bd4d | 17979 | |
c19d1205 ZW |
17980 | newval |= value >> 2; |
17981 | break; | |
a737bd4d | 17982 | |
c19d1205 ZW |
17983 | case 9: /* SP load/store. */ |
17984 | if (value & ~0x3fc) | |
17985 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17986 | _("invalid offset, value too big (0x%08lX)"), | |
17987 | (long) value); | |
17988 | newval |= value >> 2; | |
17989 | break; | |
6c43fab6 | 17990 | |
c19d1205 ZW |
17991 | case 6: /* Word load/store. */ |
17992 | if (value & ~0x7c) | |
17993 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
17994 | _("invalid offset, value too big (0x%08lX)"), | |
17995 | (long) value); | |
17996 | newval |= value << 4; /* 6 - 2. */ | |
17997 | break; | |
a737bd4d | 17998 | |
c19d1205 ZW |
17999 | case 7: /* Byte load/store. */ |
18000 | if (value & ~0x1f) | |
18001 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18002 | _("invalid offset, value too big (0x%08lX)"), | |
18003 | (long) value); | |
18004 | newval |= value << 6; | |
18005 | break; | |
a737bd4d | 18006 | |
c19d1205 ZW |
18007 | case 8: /* Halfword load/store. */ |
18008 | if (value & ~0x3e) | |
18009 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18010 | _("invalid offset, value too big (0x%08lX)"), | |
18011 | (long) value); | |
18012 | newval |= value << 5; /* 6 - 1. */ | |
18013 | break; | |
a737bd4d | 18014 | |
c19d1205 ZW |
18015 | default: |
18016 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18017 | "Unable to process relocation for thumb opcode: %lx", | |
18018 | (unsigned long) newval); | |
18019 | break; | |
18020 | } | |
18021 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
18022 | break; | |
a737bd4d | 18023 | |
c19d1205 ZW |
18024 | case BFD_RELOC_ARM_THUMB_ADD: |
18025 | /* This is a complicated relocation, since we use it for all of | |
18026 | the following immediate relocations: | |
a737bd4d | 18027 | |
c19d1205 ZW |
18028 | 3bit ADD/SUB |
18029 | 8bit ADD/SUB | |
18030 | 9bit ADD/SUB SP word-aligned | |
18031 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 18032 | |
c19d1205 ZW |
18033 | The type of instruction being processed is encoded in the |
18034 | instruction field: | |
a737bd4d | 18035 | |
c19d1205 ZW |
18036 | 0x8000 SUB |
18037 | 0x00F0 Rd | |
18038 | 0x000F Rs | |
18039 | */ | |
18040 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
18041 | { | |
18042 | int rd = (newval >> 4) & 0xf; | |
18043 | int rs = newval & 0xf; | |
18044 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 18045 | |
c19d1205 ZW |
18046 | /* Check for HI regs, only very restricted cases allowed: |
18047 | Adjusting SP, and using PC or SP to get an address. */ | |
18048 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
18049 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
18050 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18051 | _("invalid Hi register with immediate")); | |
a737bd4d | 18052 | |
c19d1205 ZW |
18053 | /* If value is negative, choose the opposite instruction. */ |
18054 | if (value < 0) | |
18055 | { | |
18056 | value = -value; | |
18057 | subtract = !subtract; | |
18058 | if (value < 0) | |
18059 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18060 | _("immediate value out of range")); | |
18061 | } | |
a737bd4d | 18062 | |
c19d1205 ZW |
18063 | if (rd == REG_SP) |
18064 | { | |
18065 | if (value & ~0x1fc) | |
18066 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18067 | _("invalid immediate for stack address calculation")); | |
18068 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
18069 | newval |= value >> 2; | |
18070 | } | |
18071 | else if (rs == REG_PC || rs == REG_SP) | |
18072 | { | |
18073 | if (subtract || value & ~0x3fc) | |
18074 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18075 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
18076 | (unsigned long) value); | |
18077 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); | |
18078 | newval |= rd << 8; | |
18079 | newval |= value >> 2; | |
18080 | } | |
18081 | else if (rs == rd) | |
18082 | { | |
18083 | if (value & ~0xff) | |
18084 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18085 | _("immediate value out of range")); | |
18086 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
18087 | newval |= (rd << 8) | value; | |
18088 | } | |
18089 | else | |
18090 | { | |
18091 | if (value & ~0x7) | |
18092 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18093 | _("immediate value out of range")); | |
18094 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
18095 | newval |= rd | (rs << 3) | (value << 6); | |
18096 | } | |
18097 | } | |
18098 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
18099 | break; | |
a737bd4d | 18100 | |
c19d1205 ZW |
18101 | case BFD_RELOC_ARM_THUMB_IMM: |
18102 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
18103 | if (value < 0 || value > 255) | |
18104 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18105 | _("invalid immediate: %ld is too large"), | |
18106 | (long) value); | |
18107 | newval |= value; | |
18108 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
18109 | break; | |
a737bd4d | 18110 | |
c19d1205 ZW |
18111 | case BFD_RELOC_ARM_THUMB_SHIFT: |
18112 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
18113 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
18114 | temp = newval & 0xf800; | |
18115 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
18116 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18117 | _("invalid shift value: %ld"), (long) value); | |
18118 | /* Shifts of zero must be encoded as LSL. */ | |
18119 | if (value == 0) | |
18120 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
18121 | /* Shifts of 32 are encoded as zero. */ | |
18122 | else if (value == 32) | |
18123 | value = 0; | |
18124 | newval |= value << 6; | |
18125 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
18126 | break; | |
a737bd4d | 18127 | |
c19d1205 ZW |
18128 | case BFD_RELOC_VTABLE_INHERIT: |
18129 | case BFD_RELOC_VTABLE_ENTRY: | |
18130 | fixP->fx_done = 0; | |
18131 | return; | |
6c43fab6 | 18132 | |
b6895b4f PB |
18133 | case BFD_RELOC_ARM_MOVW: |
18134 | case BFD_RELOC_ARM_MOVT: | |
18135 | case BFD_RELOC_ARM_THUMB_MOVW: | |
18136 | case BFD_RELOC_ARM_THUMB_MOVT: | |
18137 | if (fixP->fx_done || !seg->use_rela_p) | |
18138 | { | |
18139 | /* REL format relocations are limited to a 16-bit addend. */ | |
18140 | if (!fixP->fx_done) | |
18141 | { | |
18142 | if (value < -0x1000 || value > 0xffff) | |
18143 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18144 | _("offset too big")); | |
18145 | } | |
18146 | else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
18147 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
18148 | { | |
18149 | value >>= 16; | |
18150 | } | |
18151 | ||
18152 | if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
18153 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
18154 | { | |
18155 | newval = get_thumb32_insn (buf); | |
18156 | newval &= 0xfbf08f00; | |
18157 | newval |= (value & 0xf000) << 4; | |
18158 | newval |= (value & 0x0800) << 15; | |
18159 | newval |= (value & 0x0700) << 4; | |
18160 | newval |= (value & 0x00ff); | |
18161 | put_thumb32_insn (buf, newval); | |
18162 | } | |
18163 | else | |
18164 | { | |
18165 | newval = md_chars_to_number (buf, 4); | |
18166 | newval &= 0xfff0f000; | |
18167 | newval |= value & 0x0fff; | |
18168 | newval |= (value & 0xf000) << 4; | |
18169 | md_number_to_chars (buf, newval, 4); | |
18170 | } | |
18171 | } | |
18172 | return; | |
18173 | ||
4962c51a MS |
18174 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
18175 | case BFD_RELOC_ARM_ALU_PC_G0: | |
18176 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
18177 | case BFD_RELOC_ARM_ALU_PC_G1: | |
18178 | case BFD_RELOC_ARM_ALU_PC_G2: | |
18179 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
18180 | case BFD_RELOC_ARM_ALU_SB_G0: | |
18181 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
18182 | case BFD_RELOC_ARM_ALU_SB_G1: | |
18183 | case BFD_RELOC_ARM_ALU_SB_G2: | |
18184 | assert (!fixP->fx_done); | |
18185 | if (!seg->use_rela_p) | |
18186 | { | |
18187 | bfd_vma insn; | |
18188 | bfd_vma encoded_addend; | |
18189 | bfd_vma addend_abs = abs (value); | |
18190 | ||
18191 | /* Check that the absolute value of the addend can be | |
18192 | expressed as an 8-bit constant plus a rotation. */ | |
18193 | encoded_addend = encode_arm_immediate (addend_abs); | |
18194 | if (encoded_addend == (unsigned int) FAIL) | |
18195 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18196 | _("the offset 0x%08lX is not representable"), | |
18197 | addend_abs); | |
18198 | ||
18199 | /* Extract the instruction. */ | |
18200 | insn = md_chars_to_number (buf, INSN_SIZE); | |
18201 | ||
18202 | /* If the addend is positive, use an ADD instruction. | |
18203 | Otherwise use a SUB. Take care not to destroy the S bit. */ | |
18204 | insn &= 0xff1fffff; | |
18205 | if (value < 0) | |
18206 | insn |= 1 << 22; | |
18207 | else | |
18208 | insn |= 1 << 23; | |
18209 | ||
18210 | /* Place the encoded addend into the first 12 bits of the | |
18211 | instruction. */ | |
18212 | insn &= 0xfffff000; | |
18213 | insn |= encoded_addend; | |
18214 | ||
18215 | /* Update the instruction. */ | |
18216 | md_number_to_chars (buf, insn, INSN_SIZE); | |
18217 | } | |
18218 | break; | |
18219 | ||
18220 | case BFD_RELOC_ARM_LDR_PC_G0: | |
18221 | case BFD_RELOC_ARM_LDR_PC_G1: | |
18222 | case BFD_RELOC_ARM_LDR_PC_G2: | |
18223 | case BFD_RELOC_ARM_LDR_SB_G0: | |
18224 | case BFD_RELOC_ARM_LDR_SB_G1: | |
18225 | case BFD_RELOC_ARM_LDR_SB_G2: | |
18226 | assert (!fixP->fx_done); | |
18227 | if (!seg->use_rela_p) | |
18228 | { | |
18229 | bfd_vma insn; | |
18230 | bfd_vma addend_abs = abs (value); | |
18231 | ||
18232 | /* Check that the absolute value of the addend can be | |
18233 | encoded in 12 bits. */ | |
18234 | if (addend_abs >= 0x1000) | |
18235 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18236 | _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), | |
18237 | addend_abs); | |
18238 | ||
18239 | /* Extract the instruction. */ | |
18240 | insn = md_chars_to_number (buf, INSN_SIZE); | |
18241 | ||
18242 | /* If the addend is negative, clear bit 23 of the instruction. | |
18243 | Otherwise set it. */ | |
18244 | if (value < 0) | |
18245 | insn &= ~(1 << 23); | |
18246 | else | |
18247 | insn |= 1 << 23; | |
18248 | ||
18249 | /* Place the absolute value of the addend into the first 12 bits | |
18250 | of the instruction. */ | |
18251 | insn &= 0xfffff000; | |
18252 | insn |= addend_abs; | |
18253 | ||
18254 | /* Update the instruction. */ | |
18255 | md_number_to_chars (buf, insn, INSN_SIZE); | |
18256 | } | |
18257 | break; | |
18258 | ||
18259 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
18260 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
18261 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
18262 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
18263 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
18264 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
18265 | assert (!fixP->fx_done); | |
18266 | if (!seg->use_rela_p) | |
18267 | { | |
18268 | bfd_vma insn; | |
18269 | bfd_vma addend_abs = abs (value); | |
18270 | ||
18271 | /* Check that the absolute value of the addend can be | |
18272 | encoded in 8 bits. */ | |
18273 | if (addend_abs >= 0x100) | |
18274 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18275 | _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), | |
18276 | addend_abs); | |
18277 | ||
18278 | /* Extract the instruction. */ | |
18279 | insn = md_chars_to_number (buf, INSN_SIZE); | |
18280 | ||
18281 | /* If the addend is negative, clear bit 23 of the instruction. | |
18282 | Otherwise set it. */ | |
18283 | if (value < 0) | |
18284 | insn &= ~(1 << 23); | |
18285 | else | |
18286 | insn |= 1 << 23; | |
18287 | ||
18288 | /* Place the first four bits of the absolute value of the addend | |
18289 | into the first 4 bits of the instruction, and the remaining | |
18290 | four into bits 8 .. 11. */ | |
18291 | insn &= 0xfffff0f0; | |
18292 | insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); | |
18293 | ||
18294 | /* Update the instruction. */ | |
18295 | md_number_to_chars (buf, insn, INSN_SIZE); | |
18296 | } | |
18297 | break; | |
18298 | ||
18299 | case BFD_RELOC_ARM_LDC_PC_G0: | |
18300 | case BFD_RELOC_ARM_LDC_PC_G1: | |
18301 | case BFD_RELOC_ARM_LDC_PC_G2: | |
18302 | case BFD_RELOC_ARM_LDC_SB_G0: | |
18303 | case BFD_RELOC_ARM_LDC_SB_G1: | |
18304 | case BFD_RELOC_ARM_LDC_SB_G2: | |
18305 | assert (!fixP->fx_done); | |
18306 | if (!seg->use_rela_p) | |
18307 | { | |
18308 | bfd_vma insn; | |
18309 | bfd_vma addend_abs = abs (value); | |
18310 | ||
18311 | /* Check that the absolute value of the addend is a multiple of | |
18312 | four and, when divided by four, fits in 8 bits. */ | |
18313 | if (addend_abs & 0x3) | |
18314 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18315 | _("bad offset 0x%08lX (must be word-aligned)"), | |
18316 | addend_abs); | |
18317 | ||
18318 | if ((addend_abs >> 2) > 0xff) | |
18319 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18320 | _("bad offset 0x%08lX (must be an 8-bit number of words)"), | |
18321 | addend_abs); | |
18322 | ||
18323 | /* Extract the instruction. */ | |
18324 | insn = md_chars_to_number (buf, INSN_SIZE); | |
18325 | ||
18326 | /* If the addend is negative, clear bit 23 of the instruction. | |
18327 | Otherwise set it. */ | |
18328 | if (value < 0) | |
18329 | insn &= ~(1 << 23); | |
18330 | else | |
18331 | insn |= 1 << 23; | |
18332 | ||
18333 | /* Place the addend (divided by four) into the first eight | |
18334 | bits of the instruction. */ | |
18335 | insn &= 0xfffffff0; | |
18336 | insn |= addend_abs >> 2; | |
18337 | ||
18338 | /* Update the instruction. */ | |
18339 | md_number_to_chars (buf, insn, INSN_SIZE); | |
18340 | } | |
18341 | break; | |
18342 | ||
c19d1205 ZW |
18343 | case BFD_RELOC_UNUSED: |
18344 | default: | |
18345 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18346 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
18347 | } | |
6c43fab6 RE |
18348 | } |
18349 | ||
c19d1205 ZW |
18350 | /* Translate internal representation of relocation info to BFD target |
18351 | format. */ | |
a737bd4d | 18352 | |
c19d1205 | 18353 | arelent * |
00a97672 | 18354 | tc_gen_reloc (asection *section, fixS *fixp) |
a737bd4d | 18355 | { |
c19d1205 ZW |
18356 | arelent * reloc; |
18357 | bfd_reloc_code_real_type code; | |
a737bd4d | 18358 | |
c19d1205 | 18359 | reloc = xmalloc (sizeof (arelent)); |
a737bd4d | 18360 | |
c19d1205 ZW |
18361 | reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); |
18362 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
18363 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 18364 | |
2fc8bdac | 18365 | if (fixp->fx_pcrel) |
00a97672 RS |
18366 | { |
18367 | if (section->use_rela_p) | |
18368 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
18369 | else | |
18370 | fixp->fx_offset = reloc->address; | |
18371 | } | |
c19d1205 | 18372 | reloc->addend = fixp->fx_offset; |
a737bd4d | 18373 | |
c19d1205 | 18374 | switch (fixp->fx_r_type) |
a737bd4d | 18375 | { |
c19d1205 ZW |
18376 | case BFD_RELOC_8: |
18377 | if (fixp->fx_pcrel) | |
18378 | { | |
18379 | code = BFD_RELOC_8_PCREL; | |
18380 | break; | |
18381 | } | |
a737bd4d | 18382 | |
c19d1205 ZW |
18383 | case BFD_RELOC_16: |
18384 | if (fixp->fx_pcrel) | |
18385 | { | |
18386 | code = BFD_RELOC_16_PCREL; | |
18387 | break; | |
18388 | } | |
6c43fab6 | 18389 | |
c19d1205 ZW |
18390 | case BFD_RELOC_32: |
18391 | if (fixp->fx_pcrel) | |
18392 | { | |
18393 | code = BFD_RELOC_32_PCREL; | |
18394 | break; | |
18395 | } | |
a737bd4d | 18396 | |
b6895b4f PB |
18397 | case BFD_RELOC_ARM_MOVW: |
18398 | if (fixp->fx_pcrel) | |
18399 | { | |
18400 | code = BFD_RELOC_ARM_MOVW_PCREL; | |
18401 | break; | |
18402 | } | |
18403 | ||
18404 | case BFD_RELOC_ARM_MOVT: | |
18405 | if (fixp->fx_pcrel) | |
18406 | { | |
18407 | code = BFD_RELOC_ARM_MOVT_PCREL; | |
18408 | break; | |
18409 | } | |
18410 | ||
18411 | case BFD_RELOC_ARM_THUMB_MOVW: | |
18412 | if (fixp->fx_pcrel) | |
18413 | { | |
18414 | code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; | |
18415 | break; | |
18416 | } | |
18417 | ||
18418 | case BFD_RELOC_ARM_THUMB_MOVT: | |
18419 | if (fixp->fx_pcrel) | |
18420 | { | |
18421 | code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; | |
18422 | break; | |
18423 | } | |
18424 | ||
c19d1205 ZW |
18425 | case BFD_RELOC_NONE: |
18426 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
18427 | case BFD_RELOC_ARM_PCREL_BLX: | |
18428 | case BFD_RELOC_RVA: | |
18429 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
18430 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
18431 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
18432 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
18433 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
18434 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
18435 | case BFD_RELOC_THUMB_PCREL_BLX: | |
18436 | case BFD_RELOC_VTABLE_ENTRY: | |
18437 | case BFD_RELOC_VTABLE_INHERIT: | |
18438 | code = fixp->fx_r_type; | |
18439 | break; | |
a737bd4d | 18440 | |
c19d1205 ZW |
18441 | case BFD_RELOC_ARM_LITERAL: |
18442 | case BFD_RELOC_ARM_HWLITERAL: | |
18443 | /* If this is called then the a literal has | |
18444 | been referenced across a section boundary. */ | |
18445 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
18446 | _("literal referenced across section boundary")); | |
18447 | return NULL; | |
a737bd4d | 18448 | |
c19d1205 ZW |
18449 | #ifdef OBJ_ELF |
18450 | case BFD_RELOC_ARM_GOT32: | |
18451 | case BFD_RELOC_ARM_GOTOFF: | |
18452 | case BFD_RELOC_ARM_PLT32: | |
18453 | case BFD_RELOC_ARM_TARGET1: | |
18454 | case BFD_RELOC_ARM_ROSEGREL32: | |
18455 | case BFD_RELOC_ARM_SBREL32: | |
18456 | case BFD_RELOC_ARM_PREL31: | |
18457 | case BFD_RELOC_ARM_TARGET2: | |
18458 | case BFD_RELOC_ARM_TLS_LE32: | |
18459 | case BFD_RELOC_ARM_TLS_LDO32: | |
39b41c9c PB |
18460 | case BFD_RELOC_ARM_PCREL_CALL: |
18461 | case BFD_RELOC_ARM_PCREL_JUMP: | |
4962c51a MS |
18462 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
18463 | case BFD_RELOC_ARM_ALU_PC_G0: | |
18464 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
18465 | case BFD_RELOC_ARM_ALU_PC_G1: | |
18466 | case BFD_RELOC_ARM_ALU_PC_G2: | |
18467 | case BFD_RELOC_ARM_LDR_PC_G0: | |
18468 | case BFD_RELOC_ARM_LDR_PC_G1: | |
18469 | case BFD_RELOC_ARM_LDR_PC_G2: | |
18470 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
18471 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
18472 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
18473 | case BFD_RELOC_ARM_LDC_PC_G0: | |
18474 | case BFD_RELOC_ARM_LDC_PC_G1: | |
18475 | case BFD_RELOC_ARM_LDC_PC_G2: | |
18476 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
18477 | case BFD_RELOC_ARM_ALU_SB_G0: | |
18478 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
18479 | case BFD_RELOC_ARM_ALU_SB_G1: | |
18480 | case BFD_RELOC_ARM_ALU_SB_G2: | |
18481 | case BFD_RELOC_ARM_LDR_SB_G0: | |
18482 | case BFD_RELOC_ARM_LDR_SB_G1: | |
18483 | case BFD_RELOC_ARM_LDR_SB_G2: | |
18484 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
18485 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
18486 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
18487 | case BFD_RELOC_ARM_LDC_SB_G0: | |
18488 | case BFD_RELOC_ARM_LDC_SB_G1: | |
18489 | case BFD_RELOC_ARM_LDC_SB_G2: | |
c19d1205 ZW |
18490 | code = fixp->fx_r_type; |
18491 | break; | |
a737bd4d | 18492 | |
c19d1205 ZW |
18493 | case BFD_RELOC_ARM_TLS_GD32: |
18494 | case BFD_RELOC_ARM_TLS_IE32: | |
18495 | case BFD_RELOC_ARM_TLS_LDM32: | |
18496 | /* BFD will include the symbol's address in the addend. | |
18497 | But we don't want that, so subtract it out again here. */ | |
18498 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
18499 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
18500 | code = fixp->fx_r_type; | |
18501 | break; | |
18502 | #endif | |
a737bd4d | 18503 | |
c19d1205 ZW |
18504 | case BFD_RELOC_ARM_IMMEDIATE: |
18505 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
18506 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
18507 | return NULL; | |
a737bd4d | 18508 | |
c19d1205 ZW |
18509 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
18510 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
18511 | _("ADRL used for a symbol not defined in the same file")); | |
18512 | return NULL; | |
a737bd4d | 18513 | |
c19d1205 | 18514 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
18515 | if (section->use_rela_p) |
18516 | { | |
18517 | code = fixp->fx_r_type; | |
18518 | break; | |
18519 | } | |
18520 | ||
c19d1205 ZW |
18521 | if (fixp->fx_addsy != NULL |
18522 | && !S_IS_DEFINED (fixp->fx_addsy) | |
18523 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 18524 | { |
c19d1205 ZW |
18525 | as_bad_where (fixp->fx_file, fixp->fx_line, |
18526 | _("undefined local label `%s'"), | |
18527 | S_GET_NAME (fixp->fx_addsy)); | |
18528 | return NULL; | |
a737bd4d NC |
18529 | } |
18530 | ||
c19d1205 ZW |
18531 | as_bad_where (fixp->fx_file, fixp->fx_line, |
18532 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
18533 | return NULL; | |
a737bd4d | 18534 | |
c19d1205 ZW |
18535 | default: |
18536 | { | |
18537 | char * type; | |
6c43fab6 | 18538 | |
c19d1205 ZW |
18539 | switch (fixp->fx_r_type) |
18540 | { | |
18541 | case BFD_RELOC_NONE: type = "NONE"; break; | |
18542 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
18543 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 18544 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
18545 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
18546 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
18547 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
8f06b2d8 | 18548 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
18549 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
18550 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
18551 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
18552 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
18553 | default: type = _("<unknown>"); break; | |
18554 | } | |
18555 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
18556 | _("cannot represent %s relocation in this object file format"), | |
18557 | type); | |
18558 | return NULL; | |
18559 | } | |
a737bd4d | 18560 | } |
6c43fab6 | 18561 | |
c19d1205 ZW |
18562 | #ifdef OBJ_ELF |
18563 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
18564 | && GOT_symbol | |
18565 | && fixp->fx_addsy == GOT_symbol) | |
18566 | { | |
18567 | code = BFD_RELOC_ARM_GOTPC; | |
18568 | reloc->addend = fixp->fx_offset = reloc->address; | |
18569 | } | |
18570 | #endif | |
6c43fab6 | 18571 | |
c19d1205 | 18572 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 18573 | |
c19d1205 ZW |
18574 | if (reloc->howto == NULL) |
18575 | { | |
18576 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
18577 | _("cannot represent %s relocation in this object file format"), | |
18578 | bfd_get_reloc_code_name (code)); | |
18579 | return NULL; | |
18580 | } | |
6c43fab6 | 18581 | |
c19d1205 ZW |
18582 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
18583 | vtable entry to be used in the relocation's section offset. */ | |
18584 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
18585 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 18586 | |
c19d1205 | 18587 | return reloc; |
6c43fab6 RE |
18588 | } |
18589 | ||
c19d1205 | 18590 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 18591 | |
c19d1205 ZW |
18592 | void |
18593 | cons_fix_new_arm (fragS * frag, | |
18594 | int where, | |
18595 | int size, | |
18596 | expressionS * exp) | |
6c43fab6 | 18597 | { |
c19d1205 ZW |
18598 | bfd_reloc_code_real_type type; |
18599 | int pcrel = 0; | |
6c43fab6 | 18600 | |
c19d1205 ZW |
18601 | /* Pick a reloc. |
18602 | FIXME: @@ Should look at CPU word size. */ | |
18603 | switch (size) | |
18604 | { | |
18605 | case 1: | |
18606 | type = BFD_RELOC_8; | |
18607 | break; | |
18608 | case 2: | |
18609 | type = BFD_RELOC_16; | |
18610 | break; | |
18611 | case 4: | |
18612 | default: | |
18613 | type = BFD_RELOC_32; | |
18614 | break; | |
18615 | case 8: | |
18616 | type = BFD_RELOC_64; | |
18617 | break; | |
18618 | } | |
6c43fab6 | 18619 | |
c19d1205 ZW |
18620 | fix_new_exp (frag, where, (int) size, exp, pcrel, type); |
18621 | } | |
6c43fab6 | 18622 | |
c19d1205 ZW |
18623 | #if defined OBJ_COFF || defined OBJ_ELF |
18624 | void | |
18625 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 18626 | { |
c19d1205 ZW |
18627 | /* If the destination of the branch is a defined symbol which does not have |
18628 | the THUMB_FUNC attribute, then we must be calling a function which has | |
18629 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
18630 | function and change the branch to refer to that function instead. */ | |
18631 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
18632 | && fixP->fx_addsy != NULL | |
18633 | && S_IS_DEFINED (fixP->fx_addsy) | |
18634 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 18635 | { |
c19d1205 | 18636 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 18637 | } |
c19d1205 ZW |
18638 | } |
18639 | #endif | |
6c43fab6 | 18640 | |
c19d1205 ZW |
18641 | int |
18642 | arm_force_relocation (struct fix * fixp) | |
18643 | { | |
18644 | #if defined (OBJ_COFF) && defined (TE_PE) | |
18645 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
18646 | return 1; | |
18647 | #endif | |
6c43fab6 | 18648 | |
c19d1205 ZW |
18649 | /* Resolve these relocations even if the symbol is extern or weak. */ |
18650 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE | |
18651 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
0110f2b8 | 18652 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
16805f35 | 18653 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM |
0110f2b8 PB |
18654 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
18655 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
18656 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12) | |
c19d1205 | 18657 | return 0; |
a737bd4d | 18658 | |
4962c51a MS |
18659 | /* Always leave these relocations for the linker. */ |
18660 | if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
18661 | && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
18662 | || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
18663 | return 1; | |
18664 | ||
c19d1205 | 18665 | return generic_force_reloc (fixp); |
404ff6b5 AH |
18666 | } |
18667 | ||
c19d1205 | 18668 | #ifdef OBJ_COFF |
c19d1205 ZW |
18669 | bfd_boolean |
18670 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 18671 | { |
337ff0a5 NC |
18672 | /* This is a little hack to help the gas/arm/adrl.s test. It prevents |
18673 | local labels from being added to the output symbol table when they | |
18674 | are used with the ADRL pseudo op. The ADRL relocation should always | |
18675 | be resolved before the binbary is emitted, so it is safe to say that | |
18676 | it is adjustable. */ | |
c19d1205 ZW |
18677 | if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE) |
18678 | return 1; | |
337ff0a5 NC |
18679 | |
18680 | /* This is a hack for the gas/all/redef2.s test. This test causes symbols | |
18681 | to be cloned, and without this test relocs would still be generated | |
6e0080dd | 18682 | against the original, pre-cloned symbol. Such symbols would not appear |
337ff0a5 NC |
18683 | in the symbol table however, and so a valid reloc could not be |
18684 | generated. So check to see if the fixup is against a symbol which has | |
18685 | been removed from the symbol chain, and if it is, then allow it to be | |
18686 | adjusted into a reloc against a section symbol. */ | |
6e0080dd NC |
18687 | if (fixP->fx_addsy != NULL |
18688 | && ! S_IS_LOCAL (fixP->fx_addsy) | |
18689 | && symbol_next (fixP->fx_addsy) == NULL | |
18690 | && symbol_next (fixP->fx_addsy) == symbol_previous (fixP->fx_addsy)) | |
18691 | return 1; | |
337ff0a5 | 18692 | |
c19d1205 | 18693 | return 0; |
404ff6b5 | 18694 | } |
c19d1205 | 18695 | #endif |
404ff6b5 | 18696 | |
c19d1205 | 18697 | #ifdef OBJ_ELF |
e28387c3 PB |
18698 | /* Relocations against function names must be left unadjusted, |
18699 | so that the linker can use this information to generate interworking | |
18700 | stubs. The MIPS version of this function | |
c19d1205 ZW |
18701 | also prevents relocations that are mips-16 specific, but I do not |
18702 | know why it does this. | |
404ff6b5 | 18703 | |
c19d1205 ZW |
18704 | FIXME: |
18705 | There is one other problem that ought to be addressed here, but | |
18706 | which currently is not: Taking the address of a label (rather | |
18707 | than a function) and then later jumping to that address. Such | |
18708 | addresses also ought to have their bottom bit set (assuming that | |
18709 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 18710 | |
c19d1205 ZW |
18711 | bfd_boolean |
18712 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 18713 | { |
c19d1205 ZW |
18714 | if (fixP->fx_addsy == NULL) |
18715 | return 1; | |
404ff6b5 | 18716 | |
e28387c3 PB |
18717 | /* Preserve relocations against symbols with function type. */ |
18718 | if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) | |
18719 | return 0; | |
18720 | ||
c19d1205 ZW |
18721 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
18722 | && fixP->fx_subsy == NULL) | |
18723 | return 0; | |
a737bd4d | 18724 | |
c19d1205 ZW |
18725 | /* We need the symbol name for the VTABLE entries. */ |
18726 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
18727 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
18728 | return 0; | |
404ff6b5 | 18729 | |
c19d1205 ZW |
18730 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
18731 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
18732 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
18733 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
18734 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
18735 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 | |
18736 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
18737 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 | |
18738 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 | |
18739 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) | |
18740 | return 0; | |
a737bd4d | 18741 | |
4962c51a MS |
18742 | /* Similarly for group relocations. */ |
18743 | if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
18744 | && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
18745 | || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
18746 | return 0; | |
18747 | ||
c19d1205 | 18748 | return 1; |
a737bd4d | 18749 | } |
404ff6b5 | 18750 | |
c19d1205 ZW |
18751 | const char * |
18752 | elf32_arm_target_format (void) | |
404ff6b5 | 18753 | { |
c19d1205 ZW |
18754 | #ifdef TE_SYMBIAN |
18755 | return (target_big_endian | |
18756 | ? "elf32-bigarm-symbian" | |
18757 | : "elf32-littlearm-symbian"); | |
18758 | #elif defined (TE_VXWORKS) | |
18759 | return (target_big_endian | |
18760 | ? "elf32-bigarm-vxworks" | |
18761 | : "elf32-littlearm-vxworks"); | |
18762 | #else | |
18763 | if (target_big_endian) | |
18764 | return "elf32-bigarm"; | |
18765 | else | |
18766 | return "elf32-littlearm"; | |
18767 | #endif | |
404ff6b5 AH |
18768 | } |
18769 | ||
c19d1205 ZW |
18770 | void |
18771 | armelf_frob_symbol (symbolS * symp, | |
18772 | int * puntp) | |
404ff6b5 | 18773 | { |
c19d1205 ZW |
18774 | elf_frob_symbol (symp, puntp); |
18775 | } | |
18776 | #endif | |
404ff6b5 | 18777 | |
c19d1205 | 18778 | /* MD interface: Finalization. */ |
a737bd4d | 18779 | |
c19d1205 ZW |
18780 | /* A good place to do this, although this was probably not intended |
18781 | for this kind of use. We need to dump the literal pool before | |
18782 | references are made to a null symbol pointer. */ | |
a737bd4d | 18783 | |
c19d1205 ZW |
18784 | void |
18785 | arm_cleanup (void) | |
18786 | { | |
18787 | literal_pool * pool; | |
a737bd4d | 18788 | |
c19d1205 ZW |
18789 | for (pool = list_of_pools; pool; pool = pool->next) |
18790 | { | |
18791 | /* Put it at the end of the relevent section. */ | |
18792 | subseg_set (pool->section, pool->sub_section); | |
18793 | #ifdef OBJ_ELF | |
18794 | arm_elf_change_section (); | |
18795 | #endif | |
18796 | s_ltorg (0); | |
18797 | } | |
404ff6b5 AH |
18798 | } |
18799 | ||
c19d1205 ZW |
18800 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
18801 | ARM ones. */ | |
404ff6b5 | 18802 | |
c19d1205 ZW |
18803 | void |
18804 | arm_adjust_symtab (void) | |
404ff6b5 | 18805 | { |
c19d1205 ZW |
18806 | #ifdef OBJ_COFF |
18807 | symbolS * sym; | |
404ff6b5 | 18808 | |
c19d1205 ZW |
18809 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
18810 | { | |
18811 | if (ARM_IS_THUMB (sym)) | |
18812 | { | |
18813 | if (THUMB_IS_FUNC (sym)) | |
18814 | { | |
18815 | /* Mark the symbol as a Thumb function. */ | |
18816 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
18817 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
18818 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 18819 | |
c19d1205 ZW |
18820 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
18821 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
18822 | else | |
18823 | as_bad (_("%s: unexpected function type: %d"), | |
18824 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
18825 | } | |
18826 | else switch (S_GET_STORAGE_CLASS (sym)) | |
18827 | { | |
18828 | case C_EXT: | |
18829 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
18830 | break; | |
18831 | case C_STAT: | |
18832 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
18833 | break; | |
18834 | case C_LABEL: | |
18835 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
18836 | break; | |
18837 | default: | |
18838 | /* Do nothing. */ | |
18839 | break; | |
18840 | } | |
18841 | } | |
a737bd4d | 18842 | |
c19d1205 ZW |
18843 | if (ARM_IS_INTERWORK (sym)) |
18844 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 18845 | } |
c19d1205 ZW |
18846 | #endif |
18847 | #ifdef OBJ_ELF | |
18848 | symbolS * sym; | |
18849 | char bind; | |
404ff6b5 | 18850 | |
c19d1205 | 18851 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 18852 | { |
c19d1205 ZW |
18853 | if (ARM_IS_THUMB (sym)) |
18854 | { | |
18855 | elf_symbol_type * elf_sym; | |
404ff6b5 | 18856 | |
c19d1205 ZW |
18857 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
18858 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 18859 | |
b0796911 PB |
18860 | if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, |
18861 | BFD_ARM_SPECIAL_SYM_TYPE_ANY)) | |
c19d1205 ZW |
18862 | { |
18863 | /* If it's a .thumb_func, declare it as so, | |
18864 | otherwise tag label as .code 16. */ | |
18865 | if (THUMB_IS_FUNC (sym)) | |
18866 | elf_sym->internal_elf_sym.st_info = | |
18867 | ELF_ST_INFO (bind, STT_ARM_TFUNC); | |
18868 | else | |
18869 | elf_sym->internal_elf_sym.st_info = | |
18870 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
18871 | } | |
18872 | } | |
18873 | } | |
18874 | #endif | |
404ff6b5 AH |
18875 | } |
18876 | ||
c19d1205 | 18877 | /* MD interface: Initialization. */ |
404ff6b5 | 18878 | |
a737bd4d | 18879 | static void |
c19d1205 | 18880 | set_constant_flonums (void) |
a737bd4d | 18881 | { |
c19d1205 | 18882 | int i; |
404ff6b5 | 18883 | |
c19d1205 ZW |
18884 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
18885 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
18886 | abort (); | |
a737bd4d | 18887 | } |
404ff6b5 | 18888 | |
c19d1205 ZW |
18889 | void |
18890 | md_begin (void) | |
a737bd4d | 18891 | { |
c19d1205 ZW |
18892 | unsigned mach; |
18893 | unsigned int i; | |
404ff6b5 | 18894 | |
c19d1205 ZW |
18895 | if ( (arm_ops_hsh = hash_new ()) == NULL |
18896 | || (arm_cond_hsh = hash_new ()) == NULL | |
18897 | || (arm_shift_hsh = hash_new ()) == NULL | |
18898 | || (arm_psr_hsh = hash_new ()) == NULL | |
62b3e311 | 18899 | || (arm_v7m_psr_hsh = hash_new ()) == NULL |
c19d1205 | 18900 | || (arm_reg_hsh = hash_new ()) == NULL |
62b3e311 PB |
18901 | || (arm_reloc_hsh = hash_new ()) == NULL |
18902 | || (arm_barrier_opt_hsh = hash_new ()) == NULL) | |
c19d1205 ZW |
18903 | as_fatal (_("virtual memory exhausted")); |
18904 | ||
18905 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
18906 | hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i)); | |
18907 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) | |
18908 | hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i)); | |
18909 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) | |
18910 | hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i)); | |
18911 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) | |
18912 | hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i)); | |
62b3e311 PB |
18913 | for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) |
18914 | hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template, (PTR) (v7m_psrs + i)); | |
c19d1205 ZW |
18915 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) |
18916 | hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i)); | |
62b3e311 PB |
18917 | for (i = 0; |
18918 | i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); | |
18919 | i++) | |
18920 | hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template, | |
18921 | (PTR) (barrier_opt_names + i)); | |
c19d1205 ZW |
18922 | #ifdef OBJ_ELF |
18923 | for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++) | |
18924 | hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i)); | |
18925 | #endif | |
18926 | ||
18927 | set_constant_flonums (); | |
404ff6b5 | 18928 | |
c19d1205 ZW |
18929 | /* Set the cpu variant based on the command-line options. We prefer |
18930 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
18931 | -mfpu= over any other way of setting the floating point unit. | |
18932 | Use of legacy options with new options are faulted. */ | |
e74cfd16 | 18933 | if (legacy_cpu) |
404ff6b5 | 18934 | { |
e74cfd16 | 18935 | if (mcpu_cpu_opt || march_cpu_opt) |
c19d1205 ZW |
18936 | as_bad (_("use of old and new-style options to set CPU type")); |
18937 | ||
18938 | mcpu_cpu_opt = legacy_cpu; | |
404ff6b5 | 18939 | } |
e74cfd16 | 18940 | else if (!mcpu_cpu_opt) |
c19d1205 | 18941 | mcpu_cpu_opt = march_cpu_opt; |
404ff6b5 | 18942 | |
e74cfd16 | 18943 | if (legacy_fpu) |
c19d1205 | 18944 | { |
e74cfd16 | 18945 | if (mfpu_opt) |
c19d1205 | 18946 | as_bad (_("use of old and new-style options to set FPU type")); |
03b1477f RE |
18947 | |
18948 | mfpu_opt = legacy_fpu; | |
18949 | } | |
e74cfd16 | 18950 | else if (!mfpu_opt) |
03b1477f | 18951 | { |
c19d1205 | 18952 | #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS)) |
39c2da32 RE |
18953 | /* Some environments specify a default FPU. If they don't, infer it |
18954 | from the processor. */ | |
e74cfd16 | 18955 | if (mcpu_fpu_opt) |
03b1477f RE |
18956 | mfpu_opt = mcpu_fpu_opt; |
18957 | else | |
18958 | mfpu_opt = march_fpu_opt; | |
39c2da32 | 18959 | #else |
e74cfd16 | 18960 | mfpu_opt = &fpu_default; |
39c2da32 | 18961 | #endif |
03b1477f RE |
18962 | } |
18963 | ||
e74cfd16 | 18964 | if (!mfpu_opt) |
03b1477f | 18965 | { |
e74cfd16 PB |
18966 | if (!mcpu_cpu_opt) |
18967 | mfpu_opt = &fpu_default; | |
18968 | else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) | |
18969 | mfpu_opt = &fpu_arch_vfp_v2; | |
03b1477f | 18970 | else |
e74cfd16 | 18971 | mfpu_opt = &fpu_arch_fpa; |
03b1477f RE |
18972 | } |
18973 | ||
ee065d83 | 18974 | #ifdef CPU_DEFAULT |
e74cfd16 | 18975 | if (!mcpu_cpu_opt) |
ee065d83 | 18976 | { |
e74cfd16 PB |
18977 | mcpu_cpu_opt = &cpu_default; |
18978 | selected_cpu = cpu_default; | |
ee065d83 | 18979 | } |
e74cfd16 PB |
18980 | #else |
18981 | if (mcpu_cpu_opt) | |
18982 | selected_cpu = *mcpu_cpu_opt; | |
ee065d83 | 18983 | else |
e74cfd16 | 18984 | mcpu_cpu_opt = &arm_arch_any; |
ee065d83 | 18985 | #endif |
03b1477f | 18986 | |
e74cfd16 | 18987 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
03b1477f | 18988 | |
e74cfd16 | 18989 | arm_arch_used = thumb_arch_used = arm_arch_none; |
ee065d83 | 18990 | |
f17c130b | 18991 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 18992 | { |
7cc69913 NC |
18993 | unsigned int flags = 0; |
18994 | ||
18995 | #if defined OBJ_ELF | |
18996 | flags = meabi_flags; | |
d507cf36 PB |
18997 | |
18998 | switch (meabi_flags) | |
33a392fb | 18999 | { |
d507cf36 | 19000 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 19001 | #endif |
d507cf36 PB |
19002 | /* Set the flags in the private structure. */ |
19003 | if (uses_apcs_26) flags |= F_APCS26; | |
19004 | if (support_interwork) flags |= F_INTERWORK; | |
19005 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 19006 | if (pic_code) flags |= F_PIC; |
e74cfd16 | 19007 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
7cc69913 NC |
19008 | flags |= F_SOFT_FLOAT; |
19009 | ||
d507cf36 PB |
19010 | switch (mfloat_abi_opt) |
19011 | { | |
19012 | case ARM_FLOAT_ABI_SOFT: | |
19013 | case ARM_FLOAT_ABI_SOFTFP: | |
19014 | flags |= F_SOFT_FLOAT; | |
19015 | break; | |
33a392fb | 19016 | |
d507cf36 PB |
19017 | case ARM_FLOAT_ABI_HARD: |
19018 | if (flags & F_SOFT_FLOAT) | |
19019 | as_bad (_("hard-float conflicts with specified fpu")); | |
19020 | break; | |
19021 | } | |
03b1477f | 19022 | |
e74cfd16 PB |
19023 | /* Using pure-endian doubles (even if soft-float). */ |
19024 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
7cc69913 | 19025 | flags |= F_VFP_FLOAT; |
f17c130b | 19026 | |
fde78edd | 19027 | #if defined OBJ_ELF |
e74cfd16 | 19028 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
d507cf36 | 19029 | flags |= EF_ARM_MAVERICK_FLOAT; |
d507cf36 PB |
19030 | break; |
19031 | ||
8cb51566 | 19032 | case EF_ARM_EABI_VER4: |
3a4a14e9 | 19033 | case EF_ARM_EABI_VER5: |
c19d1205 | 19034 | /* No additional flags to set. */ |
d507cf36 PB |
19035 | break; |
19036 | ||
19037 | default: | |
19038 | abort (); | |
19039 | } | |
7cc69913 | 19040 | #endif |
b99bd4ef NC |
19041 | bfd_set_private_flags (stdoutput, flags); |
19042 | ||
19043 | /* We have run out flags in the COFF header to encode the | |
19044 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 19045 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
19046 | if (atpcs) |
19047 | { | |
19048 | asection * sec; | |
19049 | ||
19050 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
19051 | ||
19052 | if (sec != NULL) | |
19053 | { | |
19054 | bfd_set_section_flags | |
19055 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
19056 | bfd_set_section_size (stdoutput, sec, 0); | |
19057 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
19058 | } | |
19059 | } | |
7cc69913 | 19060 | } |
f17c130b | 19061 | #endif |
b99bd4ef NC |
19062 | |
19063 | /* Record the CPU type as well. */ | |
e74cfd16 | 19064 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) |
e16bb312 | 19065 | mach = bfd_mach_arm_iWMMXt; |
e74cfd16 | 19066 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
b99bd4ef | 19067 | mach = bfd_mach_arm_XScale; |
e74cfd16 | 19068 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
fde78edd | 19069 | mach = bfd_mach_arm_ep9312; |
e74cfd16 | 19070 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
b99bd4ef | 19071 | mach = bfd_mach_arm_5TE; |
e74cfd16 | 19072 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
b99bd4ef | 19073 | { |
e74cfd16 | 19074 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
19075 | mach = bfd_mach_arm_5T; |
19076 | else | |
19077 | mach = bfd_mach_arm_5; | |
19078 | } | |
e74cfd16 | 19079 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
b99bd4ef | 19080 | { |
e74cfd16 | 19081 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
19082 | mach = bfd_mach_arm_4T; |
19083 | else | |
19084 | mach = bfd_mach_arm_4; | |
19085 | } | |
e74cfd16 | 19086 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
b99bd4ef | 19087 | mach = bfd_mach_arm_3M; |
e74cfd16 PB |
19088 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
19089 | mach = bfd_mach_arm_3; | |
19090 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) | |
19091 | mach = bfd_mach_arm_2a; | |
19092 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) | |
19093 | mach = bfd_mach_arm_2; | |
19094 | else | |
19095 | mach = bfd_mach_arm_unknown; | |
b99bd4ef NC |
19096 | |
19097 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
19098 | } | |
19099 | ||
c19d1205 | 19100 | /* Command line processing. */ |
b99bd4ef | 19101 | |
c19d1205 ZW |
19102 | /* md_parse_option |
19103 | Invocation line includes a switch not recognized by the base assembler. | |
19104 | See if it's a processor-specific option. | |
b99bd4ef | 19105 | |
c19d1205 ZW |
19106 | This routine is somewhat complicated by the need for backwards |
19107 | compatibility (since older releases of gcc can't be changed). | |
19108 | The new options try to make the interface as compatible as | |
19109 | possible with GCC. | |
b99bd4ef | 19110 | |
c19d1205 | 19111 | New options (supported) are: |
b99bd4ef | 19112 | |
c19d1205 ZW |
19113 | -mcpu=<cpu name> Assemble for selected processor |
19114 | -march=<architecture name> Assemble for selected architecture | |
19115 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
19116 | -EB/-mbig-endian Big-endian | |
19117 | -EL/-mlittle-endian Little-endian | |
19118 | -k Generate PIC code | |
19119 | -mthumb Start in Thumb mode | |
19120 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 19121 | |
c19d1205 | 19122 | For now we will also provide support for: |
b99bd4ef | 19123 | |
c19d1205 ZW |
19124 | -mapcs-32 32-bit Program counter |
19125 | -mapcs-26 26-bit Program counter | |
19126 | -macps-float Floats passed in FP registers | |
19127 | -mapcs-reentrant Reentrant code | |
19128 | -matpcs | |
19129 | (sometime these will probably be replaced with -mapcs=<list of options> | |
19130 | and -matpcs=<list of options>) | |
b99bd4ef | 19131 | |
c19d1205 ZW |
19132 | The remaining options are only supported for back-wards compatibility. |
19133 | Cpu variants, the arm part is optional: | |
19134 | -m[arm]1 Currently not supported. | |
19135 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
19136 | -m[arm]3 Arm 3 processor | |
19137 | -m[arm]6[xx], Arm 6 processors | |
19138 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
19139 | -m[arm]8[10] Arm 8 processors | |
19140 | -m[arm]9[20][tdmi] Arm 9 processors | |
19141 | -mstrongarm[110[0]] StrongARM processors | |
19142 | -mxscale XScale processors | |
19143 | -m[arm]v[2345[t[e]]] Arm architectures | |
19144 | -mall All (except the ARM1) | |
19145 | FP variants: | |
19146 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
19147 | -mfpe-old (No float load/store multiples) | |
19148 | -mvfpxd VFP Single precision | |
19149 | -mvfp All VFP | |
19150 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 19151 | |
c19d1205 ZW |
19152 | The following CPU names are recognized: |
19153 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
19154 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
19155 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
19156 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
19157 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
19158 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
19159 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 19160 | |
c19d1205 | 19161 | */ |
b99bd4ef | 19162 | |
c19d1205 | 19163 | const char * md_shortopts = "m:k"; |
b99bd4ef | 19164 | |
c19d1205 ZW |
19165 | #ifdef ARM_BI_ENDIAN |
19166 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
19167 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 19168 | #else |
c19d1205 ZW |
19169 | #if TARGET_BYTES_BIG_ENDIAN |
19170 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 19171 | #else |
c19d1205 ZW |
19172 | #define OPTION_EL (OPTION_MD_BASE + 1) |
19173 | #endif | |
b99bd4ef | 19174 | #endif |
b99bd4ef | 19175 | |
c19d1205 | 19176 | struct option md_longopts[] = |
b99bd4ef | 19177 | { |
c19d1205 ZW |
19178 | #ifdef OPTION_EB |
19179 | {"EB", no_argument, NULL, OPTION_EB}, | |
19180 | #endif | |
19181 | #ifdef OPTION_EL | |
19182 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 19183 | #endif |
c19d1205 ZW |
19184 | {NULL, no_argument, NULL, 0} |
19185 | }; | |
b99bd4ef | 19186 | |
c19d1205 | 19187 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 19188 | |
c19d1205 | 19189 | struct arm_option_table |
b99bd4ef | 19190 | { |
c19d1205 ZW |
19191 | char *option; /* Option name to match. */ |
19192 | char *help; /* Help information. */ | |
19193 | int *var; /* Variable to change. */ | |
19194 | int value; /* What to change it to. */ | |
19195 | char *deprecated; /* If non-null, print this message. */ | |
19196 | }; | |
b99bd4ef | 19197 | |
c19d1205 ZW |
19198 | struct arm_option_table arm_opts[] = |
19199 | { | |
19200 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
19201 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
19202 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
19203 | &support_interwork, 1, NULL}, | |
19204 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
19205 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
19206 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
19207 | 1, NULL}, | |
19208 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
19209 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
19210 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
19211 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
19212 | NULL}, | |
b99bd4ef | 19213 | |
c19d1205 ZW |
19214 | /* These are recognized by the assembler, but have no affect on code. */ |
19215 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
19216 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
e74cfd16 PB |
19217 | {NULL, NULL, NULL, 0, NULL} |
19218 | }; | |
19219 | ||
19220 | struct arm_legacy_option_table | |
19221 | { | |
19222 | char *option; /* Option name to match. */ | |
19223 | const arm_feature_set **var; /* Variable to change. */ | |
19224 | const arm_feature_set value; /* What to change it to. */ | |
19225 | char *deprecated; /* If non-null, print this message. */ | |
19226 | }; | |
b99bd4ef | 19227 | |
e74cfd16 PB |
19228 | const struct arm_legacy_option_table arm_legacy_opts[] = |
19229 | { | |
c19d1205 ZW |
19230 | /* DON'T add any new processors to this list -- we want the whole list |
19231 | to go away... Add them to the processors table instead. */ | |
e74cfd16 PB |
19232 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
19233 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
19234 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
19235 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
19236 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
19237 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
19238 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
19239 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
19240 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
19241 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
19242 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
19243 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
19244 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
19245 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
19246 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
19247 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
19248 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
19249 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
19250 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
19251 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
19252 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
19253 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
19254 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
19255 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
19256 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
19257 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
19258 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
19259 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
19260 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
19261 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
19262 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
19263 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
19264 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
19265 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
19266 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
19267 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
19268 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
19269 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
19270 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
19271 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
19272 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
19273 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
19274 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
19275 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
19276 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
19277 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
19278 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
19279 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
19280 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
19281 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
19282 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
19283 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
19284 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
19285 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
19286 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
19287 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
19288 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
19289 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
19290 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
19291 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
19292 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
19293 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
19294 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
19295 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
19296 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
19297 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
19298 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
19299 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
19300 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
19301 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, | |
c19d1205 | 19302 | N_("use -mcpu=strongarm110")}, |
e74cfd16 | 19303 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 19304 | N_("use -mcpu=strongarm1100")}, |
e74cfd16 | 19305 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 19306 | N_("use -mcpu=strongarm1110")}, |
e74cfd16 PB |
19307 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
19308 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
19309 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 19310 | |
c19d1205 | 19311 | /* Architecture variants -- don't add any more to this list either. */ |
e74cfd16 PB |
19312 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
19313 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
19314 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
19315 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
19316 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
19317 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
19318 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
19319 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
19320 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
19321 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
19322 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
19323 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
19324 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
19325 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
19326 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
19327 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
19328 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
19329 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 19330 | |
c19d1205 | 19331 | /* Floating point variants -- don't add any more to this list either. */ |
e74cfd16 PB |
19332 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
19333 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
19334 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
19335 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, | |
c19d1205 | 19336 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
7ed4c4c5 | 19337 | |
e74cfd16 | 19338 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
c19d1205 | 19339 | }; |
7ed4c4c5 | 19340 | |
c19d1205 | 19341 | struct arm_cpu_option_table |
7ed4c4c5 | 19342 | { |
c19d1205 | 19343 | char *name; |
e74cfd16 | 19344 | const arm_feature_set value; |
c19d1205 ZW |
19345 | /* For some CPUs we assume an FPU unless the user explicitly sets |
19346 | -mfpu=... */ | |
e74cfd16 | 19347 | const arm_feature_set default_fpu; |
ee065d83 PB |
19348 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
19349 | case. */ | |
19350 | const char *canonical_name; | |
c19d1205 | 19351 | }; |
7ed4c4c5 | 19352 | |
c19d1205 ZW |
19353 | /* This list should, at a minimum, contain all the cpu names |
19354 | recognized by GCC. */ | |
e74cfd16 | 19355 | static const struct arm_cpu_option_table arm_cpus[] = |
c19d1205 | 19356 | { |
ee065d83 PB |
19357 | {"all", ARM_ANY, FPU_ARCH_FPA, NULL}, |
19358 | {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL}, | |
19359 | {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL}, | |
19360 | {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, | |
19361 | {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, | |
19362 | {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
19363 | {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
19364 | {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
19365 | {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
19366 | {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
19367 | {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
19368 | {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
19369 | {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
19370 | {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
19371 | {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
19372 | {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
19373 | {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
19374 | {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
19375 | {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
19376 | {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
19377 | {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
19378 | {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
19379 | {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
19380 | {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
19381 | {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
19382 | {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
19383 | {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
19384 | {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
19385 | {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
19386 | {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
19387 | {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
19388 | {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
19389 | {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
19390 | {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
19391 | {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
19392 | {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
19393 | {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
19394 | {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
19395 | {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
19396 | {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"}, | |
19397 | {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
19398 | {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
19399 | {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
19400 | {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
c19d1205 ZW |
19401 | /* For V5 or later processors we default to using VFP; but the user |
19402 | should really set the FPU type explicitly. */ | |
ee065d83 PB |
19403 | {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, |
19404 | {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
19405 | {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, | |
19406 | {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, | |
19407 | {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, | |
19408 | {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, | |
19409 | {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"}, | |
19410 | {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
19411 | {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, | |
19412 | {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"}, | |
19413 | {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
19414 | {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
19415 | {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
19416 | {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
19417 | {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
19418 | {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"}, | |
19419 | {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
19420 | {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
19421 | {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
19422 | {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"}, | |
19423 | {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, | |
19424 | {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"}, | |
19425 | {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL}, | |
19426 | {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"}, | |
19427 | {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL}, | |
19428 | {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL}, | |
19429 | {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL}, | |
19430 | {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL}, | |
19431 | {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL}, | |
19432 | {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL}, | |
19433 | {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL}, | |
5287ad62 JB |
19434 | {"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3 |
19435 | | FPU_NEON_EXT_V1), | |
19436 | NULL}, | |
62b3e311 PB |
19437 | {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL}, |
19438 | {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL}, | |
c19d1205 | 19439 | /* ??? XSCALE is really an architecture. */ |
ee065d83 | 19440 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, |
c19d1205 | 19441 | /* ??? iwmmxt is not a processor. */ |
ee065d83 PB |
19442 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL}, |
19443 | {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, | |
c19d1205 | 19444 | /* Maverick */ |
e74cfd16 PB |
19445 | {"ep9312", ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"}, |
19446 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL} | |
c19d1205 | 19447 | }; |
7ed4c4c5 | 19448 | |
c19d1205 | 19449 | struct arm_arch_option_table |
7ed4c4c5 | 19450 | { |
c19d1205 | 19451 | char *name; |
e74cfd16 PB |
19452 | const arm_feature_set value; |
19453 | const arm_feature_set default_fpu; | |
c19d1205 | 19454 | }; |
7ed4c4c5 | 19455 | |
c19d1205 ZW |
19456 | /* This list should, at a minimum, contain all the architecture names |
19457 | recognized by GCC. */ | |
e74cfd16 | 19458 | static const struct arm_arch_option_table arm_archs[] = |
c19d1205 ZW |
19459 | { |
19460 | {"all", ARM_ANY, FPU_ARCH_FPA}, | |
19461 | {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA}, | |
19462 | {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA}, | |
19463 | {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
19464 | {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
19465 | {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
19466 | {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA}, | |
19467 | {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
19468 | {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA}, | |
19469 | {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
19470 | {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA}, | |
19471 | {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP}, | |
19472 | {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP}, | |
19473 | {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP}, | |
19474 | {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP}, | |
19475 | {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP}, | |
19476 | {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP}, | |
19477 | {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
19478 | {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
19479 | {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP}, | |
19480 | {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP}, | |
19481 | {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP}, | |
19482 | {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP}, | |
19483 | {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP}, | |
19484 | {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP}, | |
19485 | {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP}, | |
62b3e311 PB |
19486 | {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP}, |
19487 | {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP}, | |
19488 | {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP}, | |
19489 | {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP}, | |
c19d1205 ZW |
19490 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP}, |
19491 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP}, | |
e74cfd16 | 19492 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} |
c19d1205 | 19493 | }; |
7ed4c4c5 | 19494 | |
c19d1205 | 19495 | /* ISA extensions in the co-processor space. */ |
e74cfd16 | 19496 | struct arm_option_cpu_value_table |
c19d1205 ZW |
19497 | { |
19498 | char *name; | |
e74cfd16 | 19499 | const arm_feature_set value; |
c19d1205 | 19500 | }; |
7ed4c4c5 | 19501 | |
e74cfd16 | 19502 | static const struct arm_option_cpu_value_table arm_extensions[] = |
c19d1205 | 19503 | { |
e74cfd16 PB |
19504 | {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)}, |
19505 | {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)}, | |
19506 | {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)}, | |
19507 | {NULL, ARM_ARCH_NONE} | |
c19d1205 | 19508 | }; |
7ed4c4c5 | 19509 | |
c19d1205 ZW |
19510 | /* This list should, at a minimum, contain all the fpu names |
19511 | recognized by GCC. */ | |
e74cfd16 | 19512 | static const struct arm_option_cpu_value_table arm_fpus[] = |
c19d1205 ZW |
19513 | { |
19514 | {"softfpa", FPU_NONE}, | |
19515 | {"fpe", FPU_ARCH_FPE}, | |
19516 | {"fpe2", FPU_ARCH_FPE}, | |
19517 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
19518 | {"fpa", FPU_ARCH_FPA}, | |
19519 | {"fpa10", FPU_ARCH_FPA}, | |
19520 | {"fpa11", FPU_ARCH_FPA}, | |
19521 | {"arm7500fe", FPU_ARCH_FPA}, | |
19522 | {"softvfp", FPU_ARCH_VFP}, | |
19523 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
19524 | {"vfp", FPU_ARCH_VFP_V2}, | |
19525 | {"vfp9", FPU_ARCH_VFP_V2}, | |
5287ad62 | 19526 | {"vfp3", FPU_ARCH_VFP_V3}, |
c19d1205 ZW |
19527 | {"vfp10", FPU_ARCH_VFP_V2}, |
19528 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
19529 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
19530 | {"arm1020t", FPU_ARCH_VFP_V1}, | |
19531 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
19532 | {"arm1136jfs", FPU_ARCH_VFP_V2}, | |
19533 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, | |
19534 | {"maverick", FPU_ARCH_MAVERICK}, | |
5287ad62 | 19535 | {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
e74cfd16 PB |
19536 | {NULL, ARM_ARCH_NONE} |
19537 | }; | |
19538 | ||
19539 | struct arm_option_value_table | |
19540 | { | |
19541 | char *name; | |
19542 | long value; | |
c19d1205 | 19543 | }; |
7ed4c4c5 | 19544 | |
e74cfd16 | 19545 | static const struct arm_option_value_table arm_float_abis[] = |
c19d1205 ZW |
19546 | { |
19547 | {"hard", ARM_FLOAT_ABI_HARD}, | |
19548 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
19549 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
e74cfd16 | 19550 | {NULL, 0} |
c19d1205 | 19551 | }; |
7ed4c4c5 | 19552 | |
c19d1205 | 19553 | #ifdef OBJ_ELF |
3a4a14e9 | 19554 | /* We only know how to output GNU and ver 4/5 (AAELF) formats. */ |
e74cfd16 | 19555 | static const struct arm_option_value_table arm_eabis[] = |
c19d1205 ZW |
19556 | { |
19557 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
19558 | {"4", EF_ARM_EABI_VER4}, | |
3a4a14e9 | 19559 | {"5", EF_ARM_EABI_VER5}, |
e74cfd16 | 19560 | {NULL, 0} |
c19d1205 ZW |
19561 | }; |
19562 | #endif | |
7ed4c4c5 | 19563 | |
c19d1205 ZW |
19564 | struct arm_long_option_table |
19565 | { | |
19566 | char * option; /* Substring to match. */ | |
19567 | char * help; /* Help information. */ | |
19568 | int (* func) (char * subopt); /* Function to decode sub-option. */ | |
19569 | char * deprecated; /* If non-null, print this message. */ | |
19570 | }; | |
7ed4c4c5 NC |
19571 | |
19572 | static int | |
e74cfd16 | 19573 | arm_parse_extension (char * str, const arm_feature_set **opt_p) |
7ed4c4c5 | 19574 | { |
e74cfd16 PB |
19575 | arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set)); |
19576 | ||
19577 | /* Copy the feature set, so that we can modify it. */ | |
19578 | *ext_set = **opt_p; | |
19579 | *opt_p = ext_set; | |
19580 | ||
c19d1205 | 19581 | while (str != NULL && *str != 0) |
7ed4c4c5 | 19582 | { |
e74cfd16 | 19583 | const struct arm_option_cpu_value_table * opt; |
c19d1205 ZW |
19584 | char * ext; |
19585 | int optlen; | |
7ed4c4c5 | 19586 | |
c19d1205 ZW |
19587 | if (*str != '+') |
19588 | { | |
19589 | as_bad (_("invalid architectural extension")); | |
19590 | return 0; | |
19591 | } | |
7ed4c4c5 | 19592 | |
c19d1205 ZW |
19593 | str++; |
19594 | ext = strchr (str, '+'); | |
7ed4c4c5 | 19595 | |
c19d1205 ZW |
19596 | if (ext != NULL) |
19597 | optlen = ext - str; | |
19598 | else | |
19599 | optlen = strlen (str); | |
7ed4c4c5 | 19600 | |
c19d1205 ZW |
19601 | if (optlen == 0) |
19602 | { | |
19603 | as_bad (_("missing architectural extension")); | |
19604 | return 0; | |
19605 | } | |
7ed4c4c5 | 19606 | |
c19d1205 ZW |
19607 | for (opt = arm_extensions; opt->name != NULL; opt++) |
19608 | if (strncmp (opt->name, str, optlen) == 0) | |
19609 | { | |
e74cfd16 | 19610 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); |
c19d1205 ZW |
19611 | break; |
19612 | } | |
7ed4c4c5 | 19613 | |
c19d1205 ZW |
19614 | if (opt->name == NULL) |
19615 | { | |
19616 | as_bad (_("unknown architectural extnsion `%s'"), str); | |
19617 | return 0; | |
19618 | } | |
7ed4c4c5 | 19619 | |
c19d1205 ZW |
19620 | str = ext; |
19621 | }; | |
7ed4c4c5 | 19622 | |
c19d1205 ZW |
19623 | return 1; |
19624 | } | |
7ed4c4c5 | 19625 | |
c19d1205 ZW |
19626 | static int |
19627 | arm_parse_cpu (char * str) | |
7ed4c4c5 | 19628 | { |
e74cfd16 | 19629 | const struct arm_cpu_option_table * opt; |
c19d1205 ZW |
19630 | char * ext = strchr (str, '+'); |
19631 | int optlen; | |
7ed4c4c5 | 19632 | |
c19d1205 ZW |
19633 | if (ext != NULL) |
19634 | optlen = ext - str; | |
7ed4c4c5 | 19635 | else |
c19d1205 | 19636 | optlen = strlen (str); |
7ed4c4c5 | 19637 | |
c19d1205 | 19638 | if (optlen == 0) |
7ed4c4c5 | 19639 | { |
c19d1205 ZW |
19640 | as_bad (_("missing cpu name `%s'"), str); |
19641 | return 0; | |
7ed4c4c5 NC |
19642 | } |
19643 | ||
c19d1205 ZW |
19644 | for (opt = arm_cpus; opt->name != NULL; opt++) |
19645 | if (strncmp (opt->name, str, optlen) == 0) | |
19646 | { | |
e74cfd16 PB |
19647 | mcpu_cpu_opt = &opt->value; |
19648 | mcpu_fpu_opt = &opt->default_fpu; | |
ee065d83 PB |
19649 | if (opt->canonical_name) |
19650 | strcpy(selected_cpu_name, opt->canonical_name); | |
19651 | else | |
19652 | { | |
19653 | int i; | |
19654 | for (i = 0; i < optlen; i++) | |
19655 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
19656 | selected_cpu_name[i] = 0; | |
19657 | } | |
7ed4c4c5 | 19658 | |
c19d1205 ZW |
19659 | if (ext != NULL) |
19660 | return arm_parse_extension (ext, &mcpu_cpu_opt); | |
7ed4c4c5 | 19661 | |
c19d1205 ZW |
19662 | return 1; |
19663 | } | |
7ed4c4c5 | 19664 | |
c19d1205 ZW |
19665 | as_bad (_("unknown cpu `%s'"), str); |
19666 | return 0; | |
7ed4c4c5 NC |
19667 | } |
19668 | ||
c19d1205 ZW |
19669 | static int |
19670 | arm_parse_arch (char * str) | |
7ed4c4c5 | 19671 | { |
e74cfd16 | 19672 | const struct arm_arch_option_table *opt; |
c19d1205 ZW |
19673 | char *ext = strchr (str, '+'); |
19674 | int optlen; | |
7ed4c4c5 | 19675 | |
c19d1205 ZW |
19676 | if (ext != NULL) |
19677 | optlen = ext - str; | |
7ed4c4c5 | 19678 | else |
c19d1205 | 19679 | optlen = strlen (str); |
7ed4c4c5 | 19680 | |
c19d1205 | 19681 | if (optlen == 0) |
7ed4c4c5 | 19682 | { |
c19d1205 ZW |
19683 | as_bad (_("missing architecture name `%s'"), str); |
19684 | return 0; | |
7ed4c4c5 NC |
19685 | } |
19686 | ||
c19d1205 ZW |
19687 | for (opt = arm_archs; opt->name != NULL; opt++) |
19688 | if (streq (opt->name, str)) | |
19689 | { | |
e74cfd16 PB |
19690 | march_cpu_opt = &opt->value; |
19691 | march_fpu_opt = &opt->default_fpu; | |
ee065d83 | 19692 | strcpy(selected_cpu_name, opt->name); |
7ed4c4c5 | 19693 | |
c19d1205 ZW |
19694 | if (ext != NULL) |
19695 | return arm_parse_extension (ext, &march_cpu_opt); | |
7ed4c4c5 | 19696 | |
c19d1205 ZW |
19697 | return 1; |
19698 | } | |
19699 | ||
19700 | as_bad (_("unknown architecture `%s'\n"), str); | |
19701 | return 0; | |
7ed4c4c5 | 19702 | } |
eb043451 | 19703 | |
c19d1205 ZW |
19704 | static int |
19705 | arm_parse_fpu (char * str) | |
19706 | { | |
e74cfd16 | 19707 | const struct arm_option_cpu_value_table * opt; |
b99bd4ef | 19708 | |
c19d1205 ZW |
19709 | for (opt = arm_fpus; opt->name != NULL; opt++) |
19710 | if (streq (opt->name, str)) | |
19711 | { | |
e74cfd16 | 19712 | mfpu_opt = &opt->value; |
c19d1205 ZW |
19713 | return 1; |
19714 | } | |
b99bd4ef | 19715 | |
c19d1205 ZW |
19716 | as_bad (_("unknown floating point format `%s'\n"), str); |
19717 | return 0; | |
19718 | } | |
19719 | ||
19720 | static int | |
19721 | arm_parse_float_abi (char * str) | |
b99bd4ef | 19722 | { |
e74cfd16 | 19723 | const struct arm_option_value_table * opt; |
b99bd4ef | 19724 | |
c19d1205 ZW |
19725 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
19726 | if (streq (opt->name, str)) | |
19727 | { | |
19728 | mfloat_abi_opt = opt->value; | |
19729 | return 1; | |
19730 | } | |
cc8a6dd0 | 19731 | |
c19d1205 ZW |
19732 | as_bad (_("unknown floating point abi `%s'\n"), str); |
19733 | return 0; | |
19734 | } | |
b99bd4ef | 19735 | |
c19d1205 ZW |
19736 | #ifdef OBJ_ELF |
19737 | static int | |
19738 | arm_parse_eabi (char * str) | |
19739 | { | |
e74cfd16 | 19740 | const struct arm_option_value_table *opt; |
cc8a6dd0 | 19741 | |
c19d1205 ZW |
19742 | for (opt = arm_eabis; opt->name != NULL; opt++) |
19743 | if (streq (opt->name, str)) | |
19744 | { | |
19745 | meabi_flags = opt->value; | |
19746 | return 1; | |
19747 | } | |
19748 | as_bad (_("unknown EABI `%s'\n"), str); | |
19749 | return 0; | |
19750 | } | |
19751 | #endif | |
cc8a6dd0 | 19752 | |
c19d1205 ZW |
19753 | struct arm_long_option_table arm_long_opts[] = |
19754 | { | |
19755 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
19756 | arm_parse_cpu, NULL}, | |
19757 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
19758 | arm_parse_arch, NULL}, | |
19759 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
19760 | arm_parse_fpu, NULL}, | |
19761 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
19762 | arm_parse_float_abi, NULL}, | |
19763 | #ifdef OBJ_ELF | |
19764 | {"meabi=", N_("<ver>\t assemble for eabi version <ver>"), | |
19765 | arm_parse_eabi, NULL}, | |
19766 | #endif | |
19767 | {NULL, NULL, 0, NULL} | |
19768 | }; | |
cc8a6dd0 | 19769 | |
c19d1205 ZW |
19770 | int |
19771 | md_parse_option (int c, char * arg) | |
19772 | { | |
19773 | struct arm_option_table *opt; | |
e74cfd16 | 19774 | const struct arm_legacy_option_table *fopt; |
c19d1205 | 19775 | struct arm_long_option_table *lopt; |
b99bd4ef | 19776 | |
c19d1205 | 19777 | switch (c) |
b99bd4ef | 19778 | { |
c19d1205 ZW |
19779 | #ifdef OPTION_EB |
19780 | case OPTION_EB: | |
19781 | target_big_endian = 1; | |
19782 | break; | |
19783 | #endif | |
cc8a6dd0 | 19784 | |
c19d1205 ZW |
19785 | #ifdef OPTION_EL |
19786 | case OPTION_EL: | |
19787 | target_big_endian = 0; | |
19788 | break; | |
19789 | #endif | |
b99bd4ef | 19790 | |
c19d1205 ZW |
19791 | case 'a': |
19792 | /* Listing option. Just ignore these, we don't support additional | |
19793 | ones. */ | |
19794 | return 0; | |
b99bd4ef | 19795 | |
c19d1205 ZW |
19796 | default: |
19797 | for (opt = arm_opts; opt->option != NULL; opt++) | |
19798 | { | |
19799 | if (c == opt->option[0] | |
19800 | && ((arg == NULL && opt->option[1] == 0) | |
19801 | || streq (arg, opt->option + 1))) | |
19802 | { | |
19803 | #if WARN_DEPRECATED | |
19804 | /* If the option is deprecated, tell the user. */ | |
19805 | if (opt->deprecated != NULL) | |
19806 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, | |
19807 | arg ? arg : "", _(opt->deprecated)); | |
19808 | #endif | |
b99bd4ef | 19809 | |
c19d1205 ZW |
19810 | if (opt->var != NULL) |
19811 | *opt->var = opt->value; | |
cc8a6dd0 | 19812 | |
c19d1205 ZW |
19813 | return 1; |
19814 | } | |
19815 | } | |
b99bd4ef | 19816 | |
e74cfd16 PB |
19817 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
19818 | { | |
19819 | if (c == fopt->option[0] | |
19820 | && ((arg == NULL && fopt->option[1] == 0) | |
19821 | || streq (arg, fopt->option + 1))) | |
19822 | { | |
19823 | #if WARN_DEPRECATED | |
19824 | /* If the option is deprecated, tell the user. */ | |
19825 | if (fopt->deprecated != NULL) | |
19826 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, | |
19827 | arg ? arg : "", _(fopt->deprecated)); | |
19828 | #endif | |
19829 | ||
19830 | if (fopt->var != NULL) | |
19831 | *fopt->var = &fopt->value; | |
19832 | ||
19833 | return 1; | |
19834 | } | |
19835 | } | |
19836 | ||
c19d1205 ZW |
19837 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
19838 | { | |
19839 | /* These options are expected to have an argument. */ | |
19840 | if (c == lopt->option[0] | |
19841 | && arg != NULL | |
19842 | && strncmp (arg, lopt->option + 1, | |
19843 | strlen (lopt->option + 1)) == 0) | |
19844 | { | |
19845 | #if WARN_DEPRECATED | |
19846 | /* If the option is deprecated, tell the user. */ | |
19847 | if (lopt->deprecated != NULL) | |
19848 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, | |
19849 | _(lopt->deprecated)); | |
19850 | #endif | |
b99bd4ef | 19851 | |
c19d1205 ZW |
19852 | /* Call the sup-option parser. */ |
19853 | return lopt->func (arg + strlen (lopt->option) - 1); | |
19854 | } | |
19855 | } | |
a737bd4d | 19856 | |
c19d1205 ZW |
19857 | return 0; |
19858 | } | |
a394c00f | 19859 | |
c19d1205 ZW |
19860 | return 1; |
19861 | } | |
a394c00f | 19862 | |
c19d1205 ZW |
19863 | void |
19864 | md_show_usage (FILE * fp) | |
a394c00f | 19865 | { |
c19d1205 ZW |
19866 | struct arm_option_table *opt; |
19867 | struct arm_long_option_table *lopt; | |
a394c00f | 19868 | |
c19d1205 | 19869 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 19870 | |
c19d1205 ZW |
19871 | for (opt = arm_opts; opt->option != NULL; opt++) |
19872 | if (opt->help != NULL) | |
19873 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 19874 | |
c19d1205 ZW |
19875 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
19876 | if (lopt->help != NULL) | |
19877 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 19878 | |
c19d1205 ZW |
19879 | #ifdef OPTION_EB |
19880 | fprintf (fp, _("\ | |
19881 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
19882 | #endif |
19883 | ||
c19d1205 ZW |
19884 | #ifdef OPTION_EL |
19885 | fprintf (fp, _("\ | |
19886 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 19887 | #endif |
c19d1205 | 19888 | } |
ee065d83 PB |
19889 | |
19890 | ||
19891 | #ifdef OBJ_ELF | |
62b3e311 PB |
19892 | typedef struct |
19893 | { | |
19894 | int val; | |
19895 | arm_feature_set flags; | |
19896 | } cpu_arch_ver_table; | |
19897 | ||
19898 | /* Mapping from CPU features to EABI CPU arch values. Table must be sorted | |
19899 | least features first. */ | |
19900 | static const cpu_arch_ver_table cpu_arch_ver[] = | |
19901 | { | |
19902 | {1, ARM_ARCH_V4}, | |
19903 | {2, ARM_ARCH_V4T}, | |
19904 | {3, ARM_ARCH_V5}, | |
19905 | {4, ARM_ARCH_V5TE}, | |
19906 | {5, ARM_ARCH_V5TEJ}, | |
19907 | {6, ARM_ARCH_V6}, | |
19908 | {7, ARM_ARCH_V6Z}, | |
19909 | {8, ARM_ARCH_V6K}, | |
19910 | {9, ARM_ARCH_V6T2}, | |
19911 | {10, ARM_ARCH_V7A}, | |
19912 | {10, ARM_ARCH_V7R}, | |
19913 | {10, ARM_ARCH_V7M}, | |
19914 | {0, ARM_ARCH_NONE} | |
19915 | }; | |
19916 | ||
ee065d83 PB |
19917 | /* Set the public EABI object attributes. */ |
19918 | static void | |
19919 | aeabi_set_public_attributes (void) | |
19920 | { | |
19921 | int arch; | |
e74cfd16 | 19922 | arm_feature_set flags; |
62b3e311 PB |
19923 | arm_feature_set tmp; |
19924 | const cpu_arch_ver_table *p; | |
ee065d83 PB |
19925 | |
19926 | /* Choose the architecture based on the capabilities of the requested cpu | |
19927 | (if any) and/or the instructions actually used. */ | |
e74cfd16 PB |
19928 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); |
19929 | ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); | |
19930 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); | |
5287ad62 | 19931 | |
62b3e311 PB |
19932 | tmp = flags; |
19933 | arch = 0; | |
19934 | for (p = cpu_arch_ver; p->val; p++) | |
19935 | { | |
19936 | if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) | |
19937 | { | |
19938 | arch = p->val; | |
19939 | ARM_CLEAR_FEATURE (tmp, tmp, p->flags); | |
19940 | } | |
19941 | } | |
ee065d83 PB |
19942 | |
19943 | /* Tag_CPU_name. */ | |
19944 | if (selected_cpu_name[0]) | |
19945 | { | |
19946 | char *p; | |
19947 | ||
19948 | p = selected_cpu_name; | |
19949 | if (strncmp(p, "armv", 4) == 0) | |
19950 | { | |
19951 | int i; | |
19952 | ||
19953 | p += 4; | |
19954 | for (i = 0; p[i]; i++) | |
19955 | p[i] = TOUPPER (p[i]); | |
19956 | } | |
19957 | elf32_arm_add_eabi_attr_string (stdoutput, 5, p); | |
19958 | } | |
19959 | /* Tag_CPU_arch. */ | |
19960 | elf32_arm_add_eabi_attr_int (stdoutput, 6, arch); | |
62b3e311 PB |
19961 | /* Tag_CPU_arch_profile. */ |
19962 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) | |
19963 | elf32_arm_add_eabi_attr_int (stdoutput, 7, 'A'); | |
19964 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) | |
19965 | elf32_arm_add_eabi_attr_int (stdoutput, 7, 'R'); | |
19966 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)) | |
19967 | elf32_arm_add_eabi_attr_int (stdoutput, 7, 'M'); | |
ee065d83 | 19968 | /* Tag_ARM_ISA_use. */ |
e74cfd16 | 19969 | if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full)) |
ee065d83 PB |
19970 | elf32_arm_add_eabi_attr_int (stdoutput, 8, 1); |
19971 | /* Tag_THUMB_ISA_use. */ | |
e74cfd16 | 19972 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full)) |
ee065d83 | 19973 | elf32_arm_add_eabi_attr_int (stdoutput, 9, |
e74cfd16 | 19974 | ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1); |
ee065d83 | 19975 | /* Tag_VFP_arch. */ |
5287ad62 JB |
19976 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v3) |
19977 | || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v3)) | |
19978 | elf32_arm_add_eabi_attr_int (stdoutput, 10, 3); | |
19979 | else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v2) | |
19980 | || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v2)) | |
ee065d83 | 19981 | elf32_arm_add_eabi_attr_int (stdoutput, 10, 2); |
5287ad62 JB |
19982 | else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1) |
19983 | || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1) | |
19984 | || ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1xd) | |
19985 | || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1xd)) | |
ee065d83 PB |
19986 | elf32_arm_add_eabi_attr_int (stdoutput, 10, 1); |
19987 | /* Tag_WMMX_arch. */ | |
e74cfd16 PB |
19988 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt) |
19989 | || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt)) | |
ee065d83 | 19990 | elf32_arm_add_eabi_attr_int (stdoutput, 11, 1); |
5287ad62 JB |
19991 | /* Tag_NEON_arch. */ |
19992 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_neon_ext_v1) | |
19993 | || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_neon_ext_v1)) | |
19994 | elf32_arm_add_eabi_attr_int (stdoutput, 12, 1); | |
ee065d83 PB |
19995 | } |
19996 | ||
19997 | /* Add the .ARM.attributes section. */ | |
19998 | void | |
19999 | arm_md_end (void) | |
20000 | { | |
20001 | segT s; | |
20002 | char *p; | |
20003 | addressT addr; | |
20004 | offsetT size; | |
20005 | ||
20006 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) | |
20007 | return; | |
20008 | ||
20009 | aeabi_set_public_attributes (); | |
20010 | size = elf32_arm_eabi_attr_size (stdoutput); | |
20011 | s = subseg_new (".ARM.attributes", 0); | |
20012 | bfd_set_section_flags (stdoutput, s, SEC_READONLY | SEC_DATA); | |
20013 | addr = frag_now_fix (); | |
20014 | p = frag_more (size); | |
20015 | elf32_arm_set_eabi_attr_contents (stdoutput, (bfd_byte *)p, size); | |
20016 | } | |
8463be01 | 20017 | #endif /* OBJ_ELF */ |
ee065d83 PB |
20018 | |
20019 | ||
20020 | /* Parse a .cpu directive. */ | |
20021 | ||
20022 | static void | |
20023 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) | |
20024 | { | |
e74cfd16 | 20025 | const struct arm_cpu_option_table *opt; |
ee065d83 PB |
20026 | char *name; |
20027 | char saved_char; | |
20028 | ||
20029 | name = input_line_pointer; | |
20030 | while (*input_line_pointer && !ISSPACE(*input_line_pointer)) | |
20031 | input_line_pointer++; | |
20032 | saved_char = *input_line_pointer; | |
20033 | *input_line_pointer = 0; | |
20034 | ||
20035 | /* Skip the first "all" entry. */ | |
20036 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) | |
20037 | if (streq (opt->name, name)) | |
20038 | { | |
e74cfd16 PB |
20039 | mcpu_cpu_opt = &opt->value; |
20040 | selected_cpu = opt->value; | |
ee065d83 PB |
20041 | if (opt->canonical_name) |
20042 | strcpy(selected_cpu_name, opt->canonical_name); | |
20043 | else | |
20044 | { | |
20045 | int i; | |
20046 | for (i = 0; opt->name[i]; i++) | |
20047 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
20048 | selected_cpu_name[i] = 0; | |
20049 | } | |
e74cfd16 | 20050 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
20051 | *input_line_pointer = saved_char; |
20052 | demand_empty_rest_of_line (); | |
20053 | return; | |
20054 | } | |
20055 | as_bad (_("unknown cpu `%s'"), name); | |
20056 | *input_line_pointer = saved_char; | |
20057 | ignore_rest_of_line (); | |
20058 | } | |
20059 | ||
20060 | ||
20061 | /* Parse a .arch directive. */ | |
20062 | ||
20063 | static void | |
20064 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) | |
20065 | { | |
e74cfd16 | 20066 | const struct arm_arch_option_table *opt; |
ee065d83 PB |
20067 | char saved_char; |
20068 | char *name; | |
20069 | ||
20070 | name = input_line_pointer; | |
20071 | while (*input_line_pointer && !ISSPACE(*input_line_pointer)) | |
20072 | input_line_pointer++; | |
20073 | saved_char = *input_line_pointer; | |
20074 | *input_line_pointer = 0; | |
20075 | ||
20076 | /* Skip the first "all" entry. */ | |
20077 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
20078 | if (streq (opt->name, name)) | |
20079 | { | |
e74cfd16 PB |
20080 | mcpu_cpu_opt = &opt->value; |
20081 | selected_cpu = opt->value; | |
ee065d83 | 20082 | strcpy(selected_cpu_name, opt->name); |
e74cfd16 | 20083 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
20084 | *input_line_pointer = saved_char; |
20085 | demand_empty_rest_of_line (); | |
20086 | return; | |
20087 | } | |
20088 | ||
20089 | as_bad (_("unknown architecture `%s'\n"), name); | |
20090 | *input_line_pointer = saved_char; | |
20091 | ignore_rest_of_line (); | |
20092 | } | |
20093 | ||
20094 | ||
20095 | /* Parse a .fpu directive. */ | |
20096 | ||
20097 | static void | |
20098 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) | |
20099 | { | |
e74cfd16 | 20100 | const struct arm_option_cpu_value_table *opt; |
ee065d83 PB |
20101 | char saved_char; |
20102 | char *name; | |
20103 | ||
20104 | name = input_line_pointer; | |
20105 | while (*input_line_pointer && !ISSPACE(*input_line_pointer)) | |
20106 | input_line_pointer++; | |
20107 | saved_char = *input_line_pointer; | |
20108 | *input_line_pointer = 0; | |
20109 | ||
20110 | for (opt = arm_fpus; opt->name != NULL; opt++) | |
20111 | if (streq (opt->name, name)) | |
20112 | { | |
e74cfd16 PB |
20113 | mfpu_opt = &opt->value; |
20114 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
ee065d83 PB |
20115 | *input_line_pointer = saved_char; |
20116 | demand_empty_rest_of_line (); | |
20117 | return; | |
20118 | } | |
20119 | ||
20120 | as_bad (_("unknown floating point format `%s'\n"), name); | |
20121 | *input_line_pointer = saved_char; | |
20122 | ignore_rest_of_line (); | |
20123 | } | |
ee065d83 | 20124 |