Commit | Line | Data |
---|---|---|
b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
82704155 | 2 | Copyright (C) 1994-2019 Free Software Foundation, Inc. |
b99bd4ef NC |
3 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) |
4 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 5 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
6 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
7 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
8 | |
9 | This file is part of GAS, the GNU Assembler. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 13 | the Free Software Foundation; either version 3, or (at your option) |
b99bd4ef NC |
14 | any later version. |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
19 | GNU General Public License for more details. |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
b99bd4ef | 25 | |
42a68e18 | 26 | #include "as.h" |
5287ad62 | 27 | #include <limits.h> |
037e8744 | 28 | #include <stdarg.h> |
c19d1205 | 29 | #define NO_RELOC 0 |
3882b010 | 30 | #include "safe-ctype.h" |
b99bd4ef NC |
31 | #include "subsegs.h" |
32 | #include "obstack.h" | |
3da1d841 | 33 | #include "libiberty.h" |
f263249b RE |
34 | #include "opcode/arm.h" |
35 | ||
b99bd4ef NC |
36 | #ifdef OBJ_ELF |
37 | #include "elf/arm.h" | |
a394c00f | 38 | #include "dw2gencfi.h" |
b99bd4ef NC |
39 | #endif |
40 | ||
f0927246 NC |
41 | #include "dwarf2dbg.h" |
42 | ||
7ed4c4c5 NC |
43 | #ifdef OBJ_ELF |
44 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
45 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
46 | ||
47 | /* This structure holds the unwinding state. */ | |
48 | ||
49 | static struct | |
50 | { | |
c19d1205 ZW |
51 | symbolS * proc_start; |
52 | symbolS * table_entry; | |
53 | symbolS * personality_routine; | |
54 | int personality_index; | |
7ed4c4c5 | 55 | /* The segment containing the function. */ |
c19d1205 ZW |
56 | segT saved_seg; |
57 | subsegT saved_subseg; | |
7ed4c4c5 NC |
58 | /* Opcodes generated from this function. */ |
59 | unsigned char * opcodes; | |
c19d1205 ZW |
60 | int opcode_count; |
61 | int opcode_alloc; | |
7ed4c4c5 | 62 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 63 | offsetT frame_size; |
7ed4c4c5 NC |
64 | /* We don't add stack adjustment opcodes immediately so that we can merge |
65 | multiple adjustments. We can also omit the final adjustment | |
66 | when using a frame pointer. */ | |
c19d1205 | 67 | offsetT pending_offset; |
7ed4c4c5 | 68 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
69 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
70 | offsetT fp_offset; | |
71 | int fp_reg; | |
7ed4c4c5 | 72 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 73 | unsigned fp_used:1; |
7ed4c4c5 | 74 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 75 | unsigned sp_restored:1; |
7ed4c4c5 NC |
76 | } unwind; |
77 | ||
18a20338 CL |
78 | /* Whether --fdpic was given. */ |
79 | static int arm_fdpic; | |
80 | ||
8b1ad454 NC |
81 | #endif /* OBJ_ELF */ |
82 | ||
4962c51a MS |
83 | /* Results from operand parsing worker functions. */ |
84 | ||
85 | typedef enum | |
86 | { | |
87 | PARSE_OPERAND_SUCCESS, | |
88 | PARSE_OPERAND_FAIL, | |
89 | PARSE_OPERAND_FAIL_NO_BACKTRACK | |
90 | } parse_operand_result; | |
91 | ||
33a392fb PB |
92 | enum arm_float_abi |
93 | { | |
94 | ARM_FLOAT_ABI_HARD, | |
95 | ARM_FLOAT_ABI_SOFTFP, | |
96 | ARM_FLOAT_ABI_SOFT | |
97 | }; | |
98 | ||
c19d1205 | 99 | /* Types of processor to assemble for. */ |
b99bd4ef | 100 | #ifndef CPU_DEFAULT |
8a59fff3 | 101 | /* The code that was here used to select a default CPU depending on compiler |
fa94de6b | 102 | pre-defines which were only present when doing native builds, thus |
8a59fff3 MGD |
103 | changing gas' default behaviour depending upon the build host. |
104 | ||
105 | If you have a target that requires a default CPU option then the you | |
106 | should define CPU_DEFAULT here. */ | |
b99bd4ef NC |
107 | #endif |
108 | ||
109 | #ifndef FPU_DEFAULT | |
c820d418 MM |
110 | # ifdef TE_LINUX |
111 | # define FPU_DEFAULT FPU_ARCH_FPA | |
112 | # elif defined (TE_NetBSD) | |
113 | # ifdef OBJ_ELF | |
114 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
115 | # else | |
116 | /* Legacy a.out format. */ | |
117 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
118 | # endif | |
4e7fd91e PB |
119 | # elif defined (TE_VXWORKS) |
120 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
121 | # else |
122 | /* For backwards compatibility, default to FPA. */ | |
123 | # define FPU_DEFAULT FPU_ARCH_FPA | |
124 | # endif | |
125 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 126 | |
c19d1205 | 127 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 128 | |
4d354d8b TP |
129 | /* Current set of feature bits available (CPU+FPU). Different from |
130 | selected_cpu + selected_fpu in case of autodetection since the CPU | |
131 | feature bits are then all set. */ | |
e74cfd16 | 132 | static arm_feature_set cpu_variant; |
4d354d8b TP |
133 | /* Feature bits used in each execution state. Used to set build attribute |
134 | (in particular Tag_*_ISA_use) in CPU autodetection mode. */ | |
e74cfd16 PB |
135 | static arm_feature_set arm_arch_used; |
136 | static arm_feature_set thumb_arch_used; | |
b99bd4ef | 137 | |
b99bd4ef | 138 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
139 | static int uses_apcs_26 = FALSE; |
140 | static int atpcs = FALSE; | |
b34976b6 AM |
141 | static int support_interwork = FALSE; |
142 | static int uses_apcs_float = FALSE; | |
c19d1205 | 143 | static int pic_code = FALSE; |
845b51d6 | 144 | static int fix_v4bx = FALSE; |
278df34e NS |
145 | /* Warn on using deprecated features. */ |
146 | static int warn_on_deprecated = TRUE; | |
147 | ||
2e6976a8 DG |
148 | /* Understand CodeComposer Studio assembly syntax. */ |
149 | bfd_boolean codecomposer_syntax = FALSE; | |
03b1477f RE |
150 | |
151 | /* Variables that we set while parsing command-line options. Once all | |
152 | options have been read we re-process these values to set the real | |
153 | assembly flags. */ | |
4d354d8b TP |
154 | |
155 | /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1 | |
156 | instead of -mcpu=arm1). */ | |
157 | static const arm_feature_set *legacy_cpu = NULL; | |
158 | static const arm_feature_set *legacy_fpu = NULL; | |
159 | ||
160 | /* CPU, extension and FPU feature bits selected by -mcpu. */ | |
161 | static const arm_feature_set *mcpu_cpu_opt = NULL; | |
162 | static arm_feature_set *mcpu_ext_opt = NULL; | |
163 | static const arm_feature_set *mcpu_fpu_opt = NULL; | |
164 | ||
165 | /* CPU, extension and FPU feature bits selected by -march. */ | |
166 | static const arm_feature_set *march_cpu_opt = NULL; | |
167 | static arm_feature_set *march_ext_opt = NULL; | |
168 | static const arm_feature_set *march_fpu_opt = NULL; | |
169 | ||
170 | /* Feature bits selected by -mfpu. */ | |
171 | static const arm_feature_set *mfpu_opt = NULL; | |
e74cfd16 PB |
172 | |
173 | /* Constants for known architecture features. */ | |
174 | static const arm_feature_set fpu_default = FPU_DEFAULT; | |
f85d59c3 | 175 | static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V1; |
e74cfd16 | 176 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; |
f85d59c3 KT |
177 | static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V3; |
178 | static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED = FPU_ARCH_NEON_V1; | |
e74cfd16 PB |
179 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; |
180 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; | |
69c9e028 | 181 | #ifdef OBJ_ELF |
e74cfd16 | 182 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; |
69c9e028 | 183 | #endif |
e74cfd16 PB |
184 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; |
185 | ||
186 | #ifdef CPU_DEFAULT | |
187 | static const arm_feature_set cpu_default = CPU_DEFAULT; | |
188 | #endif | |
189 | ||
823d2571 | 190 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1); |
4070243b | 191 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V2); |
823d2571 TG |
192 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S); |
193 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3); | |
194 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M); | |
195 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4); | |
196 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T); | |
197 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5); | |
e74cfd16 | 198 | static const arm_feature_set arm_ext_v4t_5 = |
823d2571 TG |
199 | ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5); |
200 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T); | |
201 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E); | |
202 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP); | |
203 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J); | |
204 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6); | |
205 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K); | |
206 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2); | |
55e8aae7 SP |
207 | /* Only for compatability of hint instructions. */ |
208 | static const arm_feature_set arm_ext_v6k_v6t2 = | |
209 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6K | ARM_EXT_V6T2); | |
823d2571 TG |
210 | static const arm_feature_set arm_ext_v6_notm = |
211 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM); | |
212 | static const arm_feature_set arm_ext_v6_dsp = | |
213 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP); | |
214 | static const arm_feature_set arm_ext_barrier = | |
215 | ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER); | |
216 | static const arm_feature_set arm_ext_msr = | |
217 | ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR); | |
218 | static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV); | |
219 | static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7); | |
220 | static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A); | |
221 | static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R); | |
69c9e028 | 222 | #ifdef OBJ_ELF |
e7d39ed3 | 223 | static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M); |
69c9e028 | 224 | #endif |
823d2571 | 225 | static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8); |
7e806470 | 226 | static const arm_feature_set arm_ext_m = |
173205ca | 227 | ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_V7M, |
16a1fa25 | 228 | ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN); |
823d2571 TG |
229 | static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP); |
230 | static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC); | |
231 | static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS); | |
232 | static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV); | |
233 | static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT); | |
ddfded2f | 234 | static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN); |
4ed7ed8d | 235 | static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M); |
16a1fa25 TP |
236 | static const arm_feature_set arm_ext_v8m_main = |
237 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN); | |
e12437dc AV |
238 | static const arm_feature_set arm_ext_v8_1m_main = |
239 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN); | |
16a1fa25 TP |
240 | /* Instructions in ARMv8-M only found in M profile architectures. */ |
241 | static const arm_feature_set arm_ext_v8m_m_only = | |
242 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN); | |
ff8646ee TP |
243 | static const arm_feature_set arm_ext_v6t2_v8m = |
244 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M); | |
4ed7ed8d TP |
245 | /* Instructions shared between ARMv8-A and ARMv8-M. */ |
246 | static const arm_feature_set arm_ext_atomics = | |
247 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS); | |
69c9e028 | 248 | #ifdef OBJ_ELF |
15afaa63 TP |
249 | /* DSP instructions Tag_DSP_extension refers to. */ |
250 | static const arm_feature_set arm_ext_dsp = | |
251 | ARM_FEATURE_CORE_LOW (ARM_EXT_V5E | ARM_EXT_V5ExP | ARM_EXT_V6_DSP); | |
69c9e028 | 252 | #endif |
4d1464f2 MW |
253 | static const arm_feature_set arm_ext_ras = |
254 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS); | |
b8ec4e87 JW |
255 | /* FP16 instructions. */ |
256 | static const arm_feature_set arm_ext_fp16 = | |
257 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST); | |
01f48020 TC |
258 | static const arm_feature_set arm_ext_fp16_fml = |
259 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML); | |
dec41383 JW |
260 | static const arm_feature_set arm_ext_v8_2 = |
261 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A); | |
49e8a725 SN |
262 | static const arm_feature_set arm_ext_v8_3 = |
263 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A); | |
7fadb25d SD |
264 | static const arm_feature_set arm_ext_sb = |
265 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB); | |
dad0c3bf SD |
266 | static const arm_feature_set arm_ext_predres = |
267 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES); | |
e74cfd16 PB |
268 | |
269 | static const arm_feature_set arm_arch_any = ARM_ANY; | |
49fa50ef | 270 | #ifdef OBJ_ELF |
2c6b98ea | 271 | static const arm_feature_set fpu_any = FPU_ANY; |
49fa50ef | 272 | #endif |
f85d59c3 | 273 | static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1); |
e74cfd16 PB |
274 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; |
275 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; | |
276 | ||
2d447fca | 277 | static const arm_feature_set arm_cext_iwmmxt2 = |
823d2571 | 278 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2); |
e74cfd16 | 279 | static const arm_feature_set arm_cext_iwmmxt = |
823d2571 | 280 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT); |
e74cfd16 | 281 | static const arm_feature_set arm_cext_xscale = |
823d2571 | 282 | ARM_FEATURE_COPROC (ARM_CEXT_XSCALE); |
e74cfd16 | 283 | static const arm_feature_set arm_cext_maverick = |
823d2571 TG |
284 | ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK); |
285 | static const arm_feature_set fpu_fpa_ext_v1 = | |
286 | ARM_FEATURE_COPROC (FPU_FPA_EXT_V1); | |
287 | static const arm_feature_set fpu_fpa_ext_v2 = | |
288 | ARM_FEATURE_COPROC (FPU_FPA_EXT_V2); | |
e74cfd16 | 289 | static const arm_feature_set fpu_vfp_ext_v1xd = |
823d2571 TG |
290 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD); |
291 | static const arm_feature_set fpu_vfp_ext_v1 = | |
292 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V1); | |
293 | static const arm_feature_set fpu_vfp_ext_v2 = | |
294 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V2); | |
295 | static const arm_feature_set fpu_vfp_ext_v3xd = | |
296 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD); | |
297 | static const arm_feature_set fpu_vfp_ext_v3 = | |
298 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V3); | |
b1cc4aeb | 299 | static const arm_feature_set fpu_vfp_ext_d32 = |
823d2571 TG |
300 | ARM_FEATURE_COPROC (FPU_VFP_EXT_D32); |
301 | static const arm_feature_set fpu_neon_ext_v1 = | |
302 | ARM_FEATURE_COPROC (FPU_NEON_EXT_V1); | |
5287ad62 | 303 | static const arm_feature_set fpu_vfp_v3_or_neon_ext = |
823d2571 | 304 | ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); |
a7ad558c AV |
305 | static const arm_feature_set mve_ext = |
306 | ARM_FEATURE_COPROC (FPU_MVE); | |
307 | static const arm_feature_set mve_fp_ext = | |
308 | ARM_FEATURE_COPROC (FPU_MVE_FP); | |
69c9e028 | 309 | #ifdef OBJ_ELF |
823d2571 TG |
310 | static const arm_feature_set fpu_vfp_fp16 = |
311 | ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16); | |
312 | static const arm_feature_set fpu_neon_ext_fma = | |
313 | ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA); | |
69c9e028 | 314 | #endif |
823d2571 TG |
315 | static const arm_feature_set fpu_vfp_ext_fma = |
316 | ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA); | |
bca38921 | 317 | static const arm_feature_set fpu_vfp_ext_armv8 = |
823d2571 | 318 | ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8); |
a715796b | 319 | static const arm_feature_set fpu_vfp_ext_armv8xd = |
823d2571 | 320 | ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD); |
bca38921 | 321 | static const arm_feature_set fpu_neon_ext_armv8 = |
823d2571 | 322 | ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8); |
bca38921 | 323 | static const arm_feature_set fpu_crypto_ext_armv8 = |
823d2571 | 324 | ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8); |
dd5181d5 | 325 | static const arm_feature_set crc_ext_armv8 = |
823d2571 | 326 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8); |
d6b4b13e | 327 | static const arm_feature_set fpu_neon_ext_v8_1 = |
643afb90 | 328 | ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA); |
c604a79a JW |
329 | static const arm_feature_set fpu_neon_ext_dotprod = |
330 | ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD); | |
e74cfd16 | 331 | |
33a392fb | 332 | static int mfloat_abi_opt = -1; |
4d354d8b TP |
333 | /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch |
334 | directive. */ | |
335 | static arm_feature_set selected_arch = ARM_ARCH_NONE; | |
336 | /* Extension feature bits selected by the last -mcpu/-march or .arch_extension | |
337 | directive. */ | |
338 | static arm_feature_set selected_ext = ARM_ARCH_NONE; | |
339 | /* Feature bits selected by the last -mcpu/-march or by the combination of the | |
340 | last .cpu/.arch directive .arch_extension directives since that | |
341 | directive. */ | |
e74cfd16 | 342 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; |
4d354d8b TP |
343 | /* FPU feature bits selected by the last -mfpu or .fpu directive. */ |
344 | static arm_feature_set selected_fpu = FPU_NONE; | |
345 | /* Feature bits selected by the last .object_arch directive. */ | |
346 | static arm_feature_set selected_object_arch = ARM_ARCH_NONE; | |
ee065d83 | 347 | /* Must be long enough to hold any of the names in arm_cpus. */ |
ef8e6722 | 348 | static char selected_cpu_name[20]; |
8d67f500 | 349 | |
aacf0b33 KT |
350 | extern FLONUM_TYPE generic_floating_point_number; |
351 | ||
8d67f500 NC |
352 | /* Return if no cpu was selected on command-line. */ |
353 | static bfd_boolean | |
354 | no_cpu_selected (void) | |
355 | { | |
823d2571 | 356 | return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none); |
8d67f500 NC |
357 | } |
358 | ||
7cc69913 | 359 | #ifdef OBJ_ELF |
deeaaff8 DJ |
360 | # ifdef EABI_DEFAULT |
361 | static int meabi_flags = EABI_DEFAULT; | |
362 | # else | |
d507cf36 | 363 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 364 | # endif |
e1da3f5b | 365 | |
ee3c0378 AS |
366 | static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; |
367 | ||
e1da3f5b | 368 | bfd_boolean |
5f4273c7 | 369 | arm_is_eabi (void) |
e1da3f5b PB |
370 | { |
371 | return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); | |
372 | } | |
7cc69913 | 373 | #endif |
b99bd4ef | 374 | |
b99bd4ef | 375 | #ifdef OBJ_ELF |
c19d1205 | 376 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
377 | symbolS * GOT_symbol; |
378 | #endif | |
379 | ||
b99bd4ef NC |
380 | /* 0: assemble for ARM, |
381 | 1: assemble for Thumb, | |
382 | 2: assemble for Thumb even though target CPU does not support thumb | |
383 | instructions. */ | |
384 | static int thumb_mode = 0; | |
8dc2430f NC |
385 | /* A value distinct from the possible values for thumb_mode that we |
386 | can use to record whether thumb_mode has been copied into the | |
387 | tc_frag_data field of a frag. */ | |
388 | #define MODE_RECORDED (1 << 4) | |
b99bd4ef | 389 | |
e07e6e58 NC |
390 | /* Specifies the intrinsic IT insn behavior mode. */ |
391 | enum implicit_it_mode | |
392 | { | |
393 | IMPLICIT_IT_MODE_NEVER = 0x00, | |
394 | IMPLICIT_IT_MODE_ARM = 0x01, | |
395 | IMPLICIT_IT_MODE_THUMB = 0x02, | |
396 | IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB) | |
397 | }; | |
398 | static int implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
399 | ||
c19d1205 ZW |
400 | /* If unified_syntax is true, we are processing the new unified |
401 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
402 | ||
403 | - Immediate operands do not require a # prefix. | |
404 | - Conditional affixes always appear at the end of the | |
405 | instruction. (For backward compatibility, those instructions | |
406 | that formerly had them in the middle, continue to accept them | |
407 | there.) | |
408 | - The IT instruction may appear, and if it does is validated | |
409 | against subsequent conditional affixes. It does not generate | |
410 | machine code. | |
411 | ||
412 | Important differences from the old Thumb mode: | |
413 | ||
414 | - Immediate operands do not require a # prefix. | |
415 | - Most of the V6T2 instructions are only available in unified mode. | |
416 | - The .N and .W suffixes are recognized and honored (it is an error | |
417 | if they cannot be honored). | |
418 | - All instructions set the flags if and only if they have an 's' affix. | |
419 | - Conditional affixes may be used. They are validated against | |
420 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
421 | conditional affix except in the scope of an IT instruction. */ | |
422 | ||
423 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef | 424 | |
bacebabc RM |
425 | /* An immediate operand can start with #, and ld*, st*, pld operands |
426 | can contain [ and ]. We need to tell APP not to elide whitespace | |
477330fc RM |
427 | before a [, which can appear as the first operand for pld. |
428 | Likewise, a { can appear as the first operand for push, pop, vld*, etc. */ | |
429 | const char arm_symbol_chars[] = "#[]{}"; | |
bacebabc | 430 | |
5287ad62 JB |
431 | enum neon_el_type |
432 | { | |
dcbf9037 | 433 | NT_invtype, |
5287ad62 JB |
434 | NT_untyped, |
435 | NT_integer, | |
436 | NT_float, | |
437 | NT_poly, | |
438 | NT_signed, | |
dcbf9037 | 439 | NT_unsigned |
5287ad62 JB |
440 | }; |
441 | ||
442 | struct neon_type_el | |
443 | { | |
444 | enum neon_el_type type; | |
445 | unsigned size; | |
446 | }; | |
447 | ||
448 | #define NEON_MAX_TYPE_ELS 4 | |
449 | ||
450 | struct neon_type | |
451 | { | |
452 | struct neon_type_el el[NEON_MAX_TYPE_ELS]; | |
453 | unsigned elems; | |
454 | }; | |
455 | ||
5ee91343 | 456 | enum pred_instruction_type |
e07e6e58 | 457 | { |
5ee91343 AV |
458 | OUTSIDE_PRED_INSN, |
459 | INSIDE_VPT_INSN, | |
e07e6e58 NC |
460 | INSIDE_IT_INSN, |
461 | INSIDE_IT_LAST_INSN, | |
462 | IF_INSIDE_IT_LAST_INSN, /* Either outside or inside; | |
477330fc | 463 | if inside, should be the last one. */ |
e07e6e58 | 464 | NEUTRAL_IT_INSN, /* This could be either inside or outside, |
477330fc | 465 | i.e. BKPT and NOP. */ |
5ee91343 AV |
466 | IT_INSN, /* The IT insn has been parsed. */ |
467 | VPT_INSN, /* The VPT/VPST insn has been parsed. */ | |
35c228db | 468 | MVE_OUTSIDE_PRED_INSN , /* Instruction to indicate a MVE instruction without |
5ee91343 | 469 | a predication code. */ |
35c228db | 470 | MVE_UNPREDICABLE_INSN /* MVE instruction that is non-predicable. */ |
e07e6e58 NC |
471 | }; |
472 | ||
ad6cec43 MGD |
473 | /* The maximum number of operands we need. */ |
474 | #define ARM_IT_MAX_OPERANDS 6 | |
e2b0ab59 | 475 | #define ARM_IT_MAX_RELOCS 3 |
ad6cec43 | 476 | |
b99bd4ef NC |
477 | struct arm_it |
478 | { | |
c19d1205 | 479 | const char * error; |
b99bd4ef | 480 | unsigned long instruction; |
c19d1205 ZW |
481 | int size; |
482 | int size_req; | |
483 | int cond; | |
037e8744 JB |
484 | /* "uncond_value" is set to the value in place of the conditional field in |
485 | unconditional versions of the instruction, or -1 if nothing is | |
486 | appropriate. */ | |
487 | int uncond_value; | |
5287ad62 | 488 | struct neon_type vectype; |
88714cb8 DG |
489 | /* This does not indicate an actual NEON instruction, only that |
490 | the mnemonic accepts neon-style type suffixes. */ | |
491 | int is_neon; | |
0110f2b8 PB |
492 | /* Set to the opcode if the instruction needs relaxation. |
493 | Zero if the instruction is not relaxed. */ | |
494 | unsigned long relax; | |
b99bd4ef NC |
495 | struct |
496 | { | |
497 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
498 | expressionS exp; |
499 | int pc_rel; | |
e2b0ab59 | 500 | } relocs[ARM_IT_MAX_RELOCS]; |
b99bd4ef | 501 | |
5ee91343 | 502 | enum pred_instruction_type pred_insn_type; |
e07e6e58 | 503 | |
c19d1205 ZW |
504 | struct |
505 | { | |
506 | unsigned reg; | |
ca3f61f7 | 507 | signed int imm; |
dcbf9037 | 508 | struct neon_type_el vectype; |
ca3f61f7 NC |
509 | unsigned present : 1; /* Operand present. */ |
510 | unsigned isreg : 1; /* Operand was a register. */ | |
f5f10c66 AV |
511 | unsigned immisreg : 2; /* .imm field is a second register. |
512 | 0: imm, 1: gpr, 2: MVE Q-register. */ | |
57785aa2 AV |
513 | unsigned isscalar : 2; /* Operand is a (SIMD) scalar: |
514 | 0) not scalar, | |
515 | 1) Neon scalar, | |
516 | 2) MVE scalar. */ | |
5287ad62 | 517 | unsigned immisalign : 1; /* Immediate is an alignment specifier. */ |
c96612cc | 518 | unsigned immisfloat : 1; /* Immediate was parsed as a float. */ |
5287ad62 JB |
519 | /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV |
520 | instructions. This allows us to disambiguate ARM <-> vector insns. */ | |
521 | unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ | |
037e8744 | 522 | unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ |
5ee91343 | 523 | unsigned isquad : 1; /* Operand is SIMD quad register. */ |
037e8744 | 524 | unsigned issingle : 1; /* Operand is VFP single-precision register. */ |
1b883319 | 525 | unsigned iszr : 1; /* Operand is ZR register. */ |
ca3f61f7 NC |
526 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ |
527 | unsigned writeback : 1; /* Operand has trailing ! */ | |
528 | unsigned preind : 1; /* Preindexed address. */ | |
529 | unsigned postind : 1; /* Postindexed address. */ | |
530 | unsigned negative : 1; /* Index register was negated. */ | |
531 | unsigned shifted : 1; /* Shift applied to operation. */ | |
532 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
ad6cec43 | 533 | } operands[ARM_IT_MAX_OPERANDS]; |
b99bd4ef NC |
534 | }; |
535 | ||
c19d1205 | 536 | static struct arm_it inst; |
b99bd4ef NC |
537 | |
538 | #define NUM_FLOAT_VALS 8 | |
539 | ||
05d2d07e | 540 | const char * fp_const[] = |
b99bd4ef NC |
541 | { |
542 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
543 | }; | |
544 | ||
b99bd4ef NC |
545 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; |
546 | ||
547 | #define FAIL (-1) | |
548 | #define SUCCESS (0) | |
549 | ||
550 | #define SUFF_S 1 | |
551 | #define SUFF_D 2 | |
552 | #define SUFF_E 3 | |
553 | #define SUFF_P 4 | |
554 | ||
c19d1205 ZW |
555 | #define CP_T_X 0x00008000 |
556 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 557 | |
c19d1205 ZW |
558 | #define CONDS_BIT 0x00100000 |
559 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
560 | |
561 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
562 | ||
563 | struct asm_cond | |
564 | { | |
d3ce72d0 | 565 | const char * template_name; |
c921be7d | 566 | unsigned long value; |
b99bd4ef NC |
567 | }; |
568 | ||
c19d1205 | 569 | #define COND_ALWAYS 0xE |
b99bd4ef | 570 | |
b99bd4ef NC |
571 | struct asm_psr |
572 | { | |
d3ce72d0 | 573 | const char * template_name; |
c921be7d | 574 | unsigned long field; |
b99bd4ef NC |
575 | }; |
576 | ||
62b3e311 PB |
577 | struct asm_barrier_opt |
578 | { | |
e797f7e0 MGD |
579 | const char * template_name; |
580 | unsigned long value; | |
581 | const arm_feature_set arch; | |
62b3e311 PB |
582 | }; |
583 | ||
2d2255b5 | 584 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
585 | #define SPSR_BIT (1 << 22) |
586 | ||
c19d1205 ZW |
587 | /* The individual PSR flag bits. */ |
588 | #define PSR_c (1 << 16) | |
589 | #define PSR_x (1 << 17) | |
590 | #define PSR_s (1 << 18) | |
591 | #define PSR_f (1 << 19) | |
b99bd4ef | 592 | |
c19d1205 | 593 | struct reloc_entry |
bfae80f2 | 594 | { |
0198d5e6 | 595 | const char * name; |
c921be7d | 596 | bfd_reloc_code_real_type reloc; |
bfae80f2 RE |
597 | }; |
598 | ||
5287ad62 | 599 | enum vfp_reg_pos |
bfae80f2 | 600 | { |
5287ad62 JB |
601 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, |
602 | VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn | |
bfae80f2 RE |
603 | }; |
604 | ||
605 | enum vfp_ldstm_type | |
606 | { | |
607 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
608 | }; | |
609 | ||
dcbf9037 JB |
610 | /* Bits for DEFINED field in neon_typed_alias. */ |
611 | #define NTA_HASTYPE 1 | |
612 | #define NTA_HASINDEX 2 | |
613 | ||
614 | struct neon_typed_alias | |
615 | { | |
c921be7d NC |
616 | unsigned char defined; |
617 | unsigned char index; | |
618 | struct neon_type_el eltype; | |
dcbf9037 JB |
619 | }; |
620 | ||
c19d1205 | 621 | /* ARM register categories. This includes coprocessor numbers and various |
5aa75429 TP |
622 | architecture extensions' registers. Each entry should have an error message |
623 | in reg_expected_msgs below. */ | |
c19d1205 | 624 | enum arm_reg_type |
bfae80f2 | 625 | { |
c19d1205 ZW |
626 | REG_TYPE_RN, |
627 | REG_TYPE_CP, | |
628 | REG_TYPE_CN, | |
629 | REG_TYPE_FN, | |
630 | REG_TYPE_VFS, | |
631 | REG_TYPE_VFD, | |
5287ad62 | 632 | REG_TYPE_NQ, |
037e8744 | 633 | REG_TYPE_VFSD, |
5287ad62 | 634 | REG_TYPE_NDQ, |
dec41383 | 635 | REG_TYPE_NSD, |
037e8744 | 636 | REG_TYPE_NSDQ, |
c19d1205 ZW |
637 | REG_TYPE_VFC, |
638 | REG_TYPE_MVF, | |
639 | REG_TYPE_MVD, | |
640 | REG_TYPE_MVFX, | |
641 | REG_TYPE_MVDX, | |
642 | REG_TYPE_MVAX, | |
5ee91343 | 643 | REG_TYPE_MQ, |
c19d1205 ZW |
644 | REG_TYPE_DSPSC, |
645 | REG_TYPE_MMXWR, | |
646 | REG_TYPE_MMXWC, | |
647 | REG_TYPE_MMXWCG, | |
648 | REG_TYPE_XSCALE, | |
5ee91343 | 649 | REG_TYPE_RNB, |
1b883319 | 650 | REG_TYPE_ZR |
bfae80f2 RE |
651 | }; |
652 | ||
dcbf9037 JB |
653 | /* Structure for a hash table entry for a register. |
654 | If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra | |
655 | information which states whether a vector type or index is specified (for a | |
656 | register alias created with .dn or .qn). Otherwise NEON should be NULL. */ | |
6c43fab6 RE |
657 | struct reg_entry |
658 | { | |
c921be7d | 659 | const char * name; |
90ec0d68 | 660 | unsigned int number; |
c921be7d NC |
661 | unsigned char type; |
662 | unsigned char builtin; | |
663 | struct neon_typed_alias * neon; | |
6c43fab6 RE |
664 | }; |
665 | ||
c19d1205 | 666 | /* Diagnostics used when we don't get a register of the expected type. */ |
c921be7d | 667 | const char * const reg_expected_msgs[] = |
c19d1205 | 668 | { |
5aa75429 TP |
669 | [REG_TYPE_RN] = N_("ARM register expected"), |
670 | [REG_TYPE_CP] = N_("bad or missing co-processor number"), | |
671 | [REG_TYPE_CN] = N_("co-processor register expected"), | |
672 | [REG_TYPE_FN] = N_("FPA register expected"), | |
673 | [REG_TYPE_VFS] = N_("VFP single precision register expected"), | |
674 | [REG_TYPE_VFD] = N_("VFP/Neon double precision register expected"), | |
675 | [REG_TYPE_NQ] = N_("Neon quad precision register expected"), | |
676 | [REG_TYPE_VFSD] = N_("VFP single or double precision register expected"), | |
677 | [REG_TYPE_NDQ] = N_("Neon double or quad precision register expected"), | |
678 | [REG_TYPE_NSD] = N_("Neon single or double precision register expected"), | |
679 | [REG_TYPE_NSDQ] = N_("VFP single, double or Neon quad precision register" | |
680 | " expected"), | |
681 | [REG_TYPE_VFC] = N_("VFP system register expected"), | |
682 | [REG_TYPE_MVF] = N_("Maverick MVF register expected"), | |
683 | [REG_TYPE_MVD] = N_("Maverick MVD register expected"), | |
684 | [REG_TYPE_MVFX] = N_("Maverick MVFX register expected"), | |
685 | [REG_TYPE_MVDX] = N_("Maverick MVDX register expected"), | |
686 | [REG_TYPE_MVAX] = N_("Maverick MVAX register expected"), | |
687 | [REG_TYPE_DSPSC] = N_("Maverick DSPSC register expected"), | |
688 | [REG_TYPE_MMXWR] = N_("iWMMXt data register expected"), | |
689 | [REG_TYPE_MMXWC] = N_("iWMMXt control register expected"), | |
690 | [REG_TYPE_MMXWCG] = N_("iWMMXt scalar register expected"), | |
691 | [REG_TYPE_XSCALE] = N_("XScale accumulator register expected"), | |
5ee91343 | 692 | [REG_TYPE_MQ] = N_("MVE vector register expected"), |
5aa75429 | 693 | [REG_TYPE_RNB] = N_("") |
6c43fab6 RE |
694 | }; |
695 | ||
c19d1205 | 696 | /* Some well known registers that we refer to directly elsewhere. */ |
bd340a04 | 697 | #define REG_R12 12 |
c19d1205 ZW |
698 | #define REG_SP 13 |
699 | #define REG_LR 14 | |
700 | #define REG_PC 15 | |
404ff6b5 | 701 | |
b99bd4ef NC |
702 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
703 | take 2: */ | |
c19d1205 | 704 | #define INSN_SIZE 4 |
b99bd4ef NC |
705 | |
706 | struct asm_opcode | |
707 | { | |
708 | /* Basic string to match. */ | |
d3ce72d0 | 709 | const char * template_name; |
c19d1205 ZW |
710 | |
711 | /* Parameters to instruction. */ | |
5be8be5d | 712 | unsigned int operands[8]; |
c19d1205 ZW |
713 | |
714 | /* Conditional tag - see opcode_lookup. */ | |
715 | unsigned int tag : 4; | |
b99bd4ef NC |
716 | |
717 | /* Basic instruction code. */ | |
a302e574 | 718 | unsigned int avalue; |
b99bd4ef | 719 | |
c19d1205 ZW |
720 | /* Thumb-format instruction code. */ |
721 | unsigned int tvalue; | |
b99bd4ef | 722 | |
90e4755a | 723 | /* Which architecture variant provides this instruction. */ |
c921be7d NC |
724 | const arm_feature_set * avariant; |
725 | const arm_feature_set * tvariant; | |
c19d1205 ZW |
726 | |
727 | /* Function to call to encode instruction in ARM format. */ | |
728 | void (* aencode) (void); | |
b99bd4ef | 729 | |
c19d1205 ZW |
730 | /* Function to call to encode instruction in Thumb format. */ |
731 | void (* tencode) (void); | |
5ee91343 AV |
732 | |
733 | /* Indicates whether this instruction may be vector predicated. */ | |
734 | unsigned int mayBeVecPred : 1; | |
b99bd4ef NC |
735 | }; |
736 | ||
a737bd4d NC |
737 | /* Defines for various bits that we will want to toggle. */ |
738 | #define INST_IMMEDIATE 0x02000000 | |
739 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 740 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
741 | #define SHIFT_BY_REG 0x00000010 |
742 | #define PRE_INDEX 0x01000000 | |
743 | #define INDEX_UP 0x00800000 | |
744 | #define WRITE_BACK 0x00200000 | |
745 | #define LDM_TYPE_2_OR_3 0x00400000 | |
a028a6f5 | 746 | #define CPSI_MMOD 0x00020000 |
90e4755a | 747 | |
a737bd4d NC |
748 | #define LITERAL_MASK 0xf000f000 |
749 | #define OPCODE_MASK 0xfe1fffff | |
750 | #define V4_STR_BIT 0x00000020 | |
8335d6aa | 751 | #define VLDR_VMOV_SAME 0x0040f000 |
90e4755a | 752 | |
efd81785 PB |
753 | #define T2_SUBS_PC_LR 0xf3de8f00 |
754 | ||
a737bd4d | 755 | #define DATA_OP_SHIFT 21 |
bada4342 | 756 | #define SBIT_SHIFT 20 |
90e4755a | 757 | |
ef8d22e6 PB |
758 | #define T2_OPCODE_MASK 0xfe1fffff |
759 | #define T2_DATA_OP_SHIFT 21 | |
bada4342 | 760 | #define T2_SBIT_SHIFT 20 |
ef8d22e6 | 761 | |
6530b175 NC |
762 | #define A_COND_MASK 0xf0000000 |
763 | #define A_PUSH_POP_OP_MASK 0x0fff0000 | |
764 | ||
765 | /* Opcodes for pushing/poping registers to/from the stack. */ | |
766 | #define A1_OPCODE_PUSH 0x092d0000 | |
767 | #define A2_OPCODE_PUSH 0x052d0004 | |
768 | #define A2_OPCODE_POP 0x049d0004 | |
769 | ||
a737bd4d NC |
770 | /* Codes to distinguish the arithmetic instructions. */ |
771 | #define OPCODE_AND 0 | |
772 | #define OPCODE_EOR 1 | |
773 | #define OPCODE_SUB 2 | |
774 | #define OPCODE_RSB 3 | |
775 | #define OPCODE_ADD 4 | |
776 | #define OPCODE_ADC 5 | |
777 | #define OPCODE_SBC 6 | |
778 | #define OPCODE_RSC 7 | |
779 | #define OPCODE_TST 8 | |
780 | #define OPCODE_TEQ 9 | |
781 | #define OPCODE_CMP 10 | |
782 | #define OPCODE_CMN 11 | |
783 | #define OPCODE_ORR 12 | |
784 | #define OPCODE_MOV 13 | |
785 | #define OPCODE_BIC 14 | |
786 | #define OPCODE_MVN 15 | |
90e4755a | 787 | |
ef8d22e6 PB |
788 | #define T2_OPCODE_AND 0 |
789 | #define T2_OPCODE_BIC 1 | |
790 | #define T2_OPCODE_ORR 2 | |
791 | #define T2_OPCODE_ORN 3 | |
792 | #define T2_OPCODE_EOR 4 | |
793 | #define T2_OPCODE_ADD 8 | |
794 | #define T2_OPCODE_ADC 10 | |
795 | #define T2_OPCODE_SBC 11 | |
796 | #define T2_OPCODE_SUB 13 | |
797 | #define T2_OPCODE_RSB 14 | |
798 | ||
a737bd4d NC |
799 | #define T_OPCODE_MUL 0x4340 |
800 | #define T_OPCODE_TST 0x4200 | |
801 | #define T_OPCODE_CMN 0x42c0 | |
802 | #define T_OPCODE_NEG 0x4240 | |
803 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 804 | |
a737bd4d NC |
805 | #define T_OPCODE_ADD_R3 0x1800 |
806 | #define T_OPCODE_SUB_R3 0x1a00 | |
807 | #define T_OPCODE_ADD_HI 0x4400 | |
808 | #define T_OPCODE_ADD_ST 0xb000 | |
809 | #define T_OPCODE_SUB_ST 0xb080 | |
810 | #define T_OPCODE_ADD_SP 0xa800 | |
811 | #define T_OPCODE_ADD_PC 0xa000 | |
812 | #define T_OPCODE_ADD_I8 0x3000 | |
813 | #define T_OPCODE_SUB_I8 0x3800 | |
814 | #define T_OPCODE_ADD_I3 0x1c00 | |
815 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 816 | |
a737bd4d NC |
817 | #define T_OPCODE_ASR_R 0x4100 |
818 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
819 | #define T_OPCODE_LSR_R 0x40c0 |
820 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
821 | #define T_OPCODE_ASR_I 0x1000 |
822 | #define T_OPCODE_LSL_I 0x0000 | |
823 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 824 | |
a737bd4d NC |
825 | #define T_OPCODE_MOV_I8 0x2000 |
826 | #define T_OPCODE_CMP_I8 0x2800 | |
827 | #define T_OPCODE_CMP_LR 0x4280 | |
828 | #define T_OPCODE_MOV_HR 0x4600 | |
829 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 830 | |
a737bd4d NC |
831 | #define T_OPCODE_LDR_PC 0x4800 |
832 | #define T_OPCODE_LDR_SP 0x9800 | |
833 | #define T_OPCODE_STR_SP 0x9000 | |
834 | #define T_OPCODE_LDR_IW 0x6800 | |
835 | #define T_OPCODE_STR_IW 0x6000 | |
836 | #define T_OPCODE_LDR_IH 0x8800 | |
837 | #define T_OPCODE_STR_IH 0x8000 | |
838 | #define T_OPCODE_LDR_IB 0x7800 | |
839 | #define T_OPCODE_STR_IB 0x7000 | |
840 | #define T_OPCODE_LDR_RW 0x5800 | |
841 | #define T_OPCODE_STR_RW 0x5000 | |
842 | #define T_OPCODE_LDR_RH 0x5a00 | |
843 | #define T_OPCODE_STR_RH 0x5200 | |
844 | #define T_OPCODE_LDR_RB 0x5c00 | |
845 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 846 | |
a737bd4d NC |
847 | #define T_OPCODE_PUSH 0xb400 |
848 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 849 | |
2fc8bdac | 850 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 851 | |
a737bd4d | 852 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 853 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 | 854 | #define THUMB_LOAD_BIT 0x0800 |
53365c0d | 855 | #define THUMB2_LOAD_BIT 0x00100000 |
c19d1205 | 856 | |
5ee91343 | 857 | #define BAD_SYNTAX _("syntax error") |
c19d1205 | 858 | #define BAD_ARGS _("bad arguments to instruction") |
fdfde340 | 859 | #define BAD_SP _("r13 not allowed here") |
c19d1205 | 860 | #define BAD_PC _("r15 not allowed here") |
a302e574 AV |
861 | #define BAD_ODD _("Odd register not allowed here") |
862 | #define BAD_EVEN _("Even register not allowed here") | |
c19d1205 ZW |
863 | #define BAD_COND _("instruction cannot be conditional") |
864 | #define BAD_OVERLAP _("registers may not be the same") | |
865 | #define BAD_HIREG _("lo register required") | |
866 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
35c228db | 867 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode") |
dfa9f0d5 | 868 | #define BAD_BRANCH _("branch must be last instruction in IT block") |
e12437dc | 869 | #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2") |
dfa9f0d5 | 870 | #define BAD_NOT_IT _("instruction not allowed in IT block") |
5ee91343 | 871 | #define BAD_NOT_VPT _("instruction missing MVE vector predication code") |
037e8744 | 872 | #define BAD_FPU _("selected FPU does not support instruction") |
e07e6e58 | 873 | #define BAD_OUT_IT _("thumb conditional instruction should be in IT block") |
5ee91343 AV |
874 | #define BAD_OUT_VPT \ |
875 | _("vector predicated instruction should be in VPT/VPST block") | |
e07e6e58 | 876 | #define BAD_IT_COND _("incorrect condition in IT block") |
5ee91343 | 877 | #define BAD_VPT_COND _("incorrect condition in VPT/VPST block") |
e07e6e58 | 878 | #define BAD_IT_IT _("IT falling in the range of a previous IT block") |
921e5f0a | 879 | #define MISSING_FNSTART _("missing .fnstart before unwinding directive") |
5be8be5d DG |
880 | #define BAD_PC_ADDRESSING \ |
881 | _("cannot use register index with PC-relative addressing") | |
882 | #define BAD_PC_WRITEBACK \ | |
883 | _("cannot use writeback with PC-relative addressing") | |
9db2f6b4 RL |
884 | #define BAD_RANGE _("branch out of range") |
885 | #define BAD_FP16 _("selected processor does not support fp16 instruction") | |
dd5181d5 | 886 | #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour") |
a9f02af8 | 887 | #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only") |
5ee91343 AV |
888 | #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \ |
889 | "block") | |
890 | #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \ | |
891 | "block") | |
892 | #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \ | |
893 | " operand") | |
894 | #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \ | |
895 | " operand") | |
a302e574 | 896 | #define BAD_SIMD_TYPE _("bad type in SIMD instruction") |
886e1c73 AV |
897 | #define BAD_MVE_AUTO \ |
898 | _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \ | |
899 | " use a valid -march or -mcpu option.") | |
900 | #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\ | |
901 | "and source operands makes instruction UNPREDICTABLE") | |
35c228db | 902 | #define BAD_EL_TYPE _("bad element type for instruction") |
1b883319 | 903 | #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected") |
c19d1205 | 904 | |
c921be7d NC |
905 | static struct hash_control * arm_ops_hsh; |
906 | static struct hash_control * arm_cond_hsh; | |
5ee91343 | 907 | static struct hash_control * arm_vcond_hsh; |
c921be7d NC |
908 | static struct hash_control * arm_shift_hsh; |
909 | static struct hash_control * arm_psr_hsh; | |
910 | static struct hash_control * arm_v7m_psr_hsh; | |
911 | static struct hash_control * arm_reg_hsh; | |
912 | static struct hash_control * arm_reloc_hsh; | |
913 | static struct hash_control * arm_barrier_opt_hsh; | |
b99bd4ef | 914 | |
b99bd4ef NC |
915 | /* Stuff needed to resolve the label ambiguity |
916 | As: | |
917 | ... | |
918 | label: <insn> | |
919 | may differ from: | |
920 | ... | |
921 | label: | |
5f4273c7 | 922 | <insn> */ |
b99bd4ef NC |
923 | |
924 | symbolS * last_label_seen; | |
b34976b6 | 925 | static int label_is_thumb_function_name = FALSE; |
e07e6e58 | 926 | |
3d0c9500 NC |
927 | /* Literal pool structure. Held on a per-section |
928 | and per-sub-section basis. */ | |
a737bd4d | 929 | |
c19d1205 | 930 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 931 | typedef struct literal_pool |
b99bd4ef | 932 | { |
c921be7d NC |
933 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
934 | unsigned int next_free_entry; | |
935 | unsigned int id; | |
936 | symbolS * symbol; | |
937 | segT section; | |
938 | subsegT sub_section; | |
a8040cf2 NC |
939 | #ifdef OBJ_ELF |
940 | struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE]; | |
941 | #endif | |
c921be7d | 942 | struct literal_pool * next; |
8335d6aa | 943 | unsigned int alignment; |
3d0c9500 | 944 | } literal_pool; |
b99bd4ef | 945 | |
3d0c9500 NC |
946 | /* Pointer to a linked list of literal pools. */ |
947 | literal_pool * list_of_pools = NULL; | |
e27ec89e | 948 | |
2e6976a8 DG |
949 | typedef enum asmfunc_states |
950 | { | |
951 | OUTSIDE_ASMFUNC, | |
952 | WAITING_ASMFUNC_NAME, | |
953 | WAITING_ENDASMFUNC | |
954 | } asmfunc_states; | |
955 | ||
956 | static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC; | |
957 | ||
e07e6e58 | 958 | #ifdef OBJ_ELF |
5ee91343 | 959 | # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred |
e07e6e58 | 960 | #else |
5ee91343 | 961 | static struct current_pred now_pred; |
e07e6e58 NC |
962 | #endif |
963 | ||
964 | static inline int | |
5ee91343 | 965 | now_pred_compatible (int cond) |
e07e6e58 | 966 | { |
5ee91343 | 967 | return (cond & ~1) == (now_pred.cc & ~1); |
e07e6e58 NC |
968 | } |
969 | ||
970 | static inline int | |
971 | conditional_insn (void) | |
972 | { | |
973 | return inst.cond != COND_ALWAYS; | |
974 | } | |
975 | ||
5ee91343 | 976 | static int in_pred_block (void); |
e07e6e58 | 977 | |
5ee91343 | 978 | static int handle_pred_state (void); |
e07e6e58 NC |
979 | |
980 | static void force_automatic_it_block_close (void); | |
981 | ||
c921be7d NC |
982 | static void it_fsm_post_encode (void); |
983 | ||
5ee91343 | 984 | #define set_pred_insn_type(type) \ |
e07e6e58 NC |
985 | do \ |
986 | { \ | |
5ee91343 AV |
987 | inst.pred_insn_type = type; \ |
988 | if (handle_pred_state () == FAIL) \ | |
477330fc | 989 | return; \ |
e07e6e58 NC |
990 | } \ |
991 | while (0) | |
992 | ||
5ee91343 | 993 | #define set_pred_insn_type_nonvoid(type, failret) \ |
c921be7d NC |
994 | do \ |
995 | { \ | |
5ee91343 AV |
996 | inst.pred_insn_type = type; \ |
997 | if (handle_pred_state () == FAIL) \ | |
477330fc | 998 | return failret; \ |
c921be7d NC |
999 | } \ |
1000 | while(0) | |
1001 | ||
5ee91343 | 1002 | #define set_pred_insn_type_last() \ |
e07e6e58 NC |
1003 | do \ |
1004 | { \ | |
1005 | if (inst.cond == COND_ALWAYS) \ | |
5ee91343 | 1006 | set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \ |
e07e6e58 | 1007 | else \ |
5ee91343 | 1008 | set_pred_insn_type (INSIDE_IT_LAST_INSN); \ |
e07e6e58 NC |
1009 | } \ |
1010 | while (0) | |
1011 | ||
e39c1607 SD |
1012 | /* Toggle value[pos]. */ |
1013 | #define TOGGLE_BIT(value, pos) (value ^ (1 << pos)) | |
1014 | ||
c19d1205 | 1015 | /* Pure syntax. */ |
b99bd4ef | 1016 | |
c19d1205 ZW |
1017 | /* This array holds the chars that always start a comment. If the |
1018 | pre-processor is disabled, these aren't very useful. */ | |
2e6976a8 | 1019 | char arm_comment_chars[] = "@"; |
3d0c9500 | 1020 | |
c19d1205 ZW |
1021 | /* This array holds the chars that only start a comment at the beginning of |
1022 | a line. If the line seems to have the form '# 123 filename' | |
1023 | .line and .file directives will appear in the pre-processed output. */ | |
1024 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
1025 | first line of the input file. This is because the compiler outputs | |
1026 | #NO_APP at the beginning of its output. */ | |
1027 | /* Also note that comments like this one will always work. */ | |
1028 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 1029 | |
2e6976a8 | 1030 | char arm_line_separator_chars[] = ";"; |
b99bd4ef | 1031 | |
c19d1205 ZW |
1032 | /* Chars that can be used to separate mant |
1033 | from exp in floating point numbers. */ | |
1034 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 1035 | |
c19d1205 ZW |
1036 | /* Chars that mean this number is a floating point constant. */ |
1037 | /* As in 0f12.456 */ | |
1038 | /* or 0d1.2345e12 */ | |
b99bd4ef | 1039 | |
c19d1205 | 1040 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 1041 | |
c19d1205 ZW |
1042 | /* Prefix characters that indicate the start of an immediate |
1043 | value. */ | |
1044 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 1045 | |
c19d1205 ZW |
1046 | /* Separator character handling. */ |
1047 | ||
1048 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
1049 | ||
1050 | static inline int | |
1051 | skip_past_char (char ** str, char c) | |
1052 | { | |
8ab8155f NC |
1053 | /* PR gas/14987: Allow for whitespace before the expected character. */ |
1054 | skip_whitespace (*str); | |
427d0db6 | 1055 | |
c19d1205 ZW |
1056 | if (**str == c) |
1057 | { | |
1058 | (*str)++; | |
1059 | return SUCCESS; | |
3d0c9500 | 1060 | } |
c19d1205 ZW |
1061 | else |
1062 | return FAIL; | |
1063 | } | |
c921be7d | 1064 | |
c19d1205 | 1065 | #define skip_past_comma(str) skip_past_char (str, ',') |
3d0c9500 | 1066 | |
c19d1205 ZW |
1067 | /* Arithmetic expressions (possibly involving symbols). */ |
1068 | ||
1069 | /* Return TRUE if anything in the expression is a bignum. */ | |
1070 | ||
0198d5e6 | 1071 | static bfd_boolean |
c19d1205 ZW |
1072 | walk_no_bignums (symbolS * sp) |
1073 | { | |
1074 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
0198d5e6 | 1075 | return TRUE; |
c19d1205 ZW |
1076 | |
1077 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 1078 | { |
c19d1205 ZW |
1079 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
1080 | || (symbol_get_value_expression (sp)->X_op_symbol | |
1081 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
1082 | } |
1083 | ||
0198d5e6 | 1084 | return FALSE; |
3d0c9500 NC |
1085 | } |
1086 | ||
0198d5e6 | 1087 | static bfd_boolean in_my_get_expression = FALSE; |
c19d1205 ZW |
1088 | |
1089 | /* Third argument to my_get_expression. */ | |
1090 | #define GE_NO_PREFIX 0 | |
1091 | #define GE_IMM_PREFIX 1 | |
1092 | #define GE_OPT_PREFIX 2 | |
5287ad62 JB |
1093 | /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) |
1094 | immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ | |
1095 | #define GE_OPT_PREFIX_BIG 3 | |
a737bd4d | 1096 | |
b99bd4ef | 1097 | static int |
c19d1205 | 1098 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 1099 | { |
c19d1205 | 1100 | char * save_in; |
b99bd4ef | 1101 | |
c19d1205 ZW |
1102 | /* In unified syntax, all prefixes are optional. */ |
1103 | if (unified_syntax) | |
5287ad62 | 1104 | prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode |
477330fc | 1105 | : GE_OPT_PREFIX; |
b99bd4ef | 1106 | |
c19d1205 | 1107 | switch (prefix_mode) |
b99bd4ef | 1108 | { |
c19d1205 ZW |
1109 | case GE_NO_PREFIX: break; |
1110 | case GE_IMM_PREFIX: | |
1111 | if (!is_immediate_prefix (**str)) | |
1112 | { | |
1113 | inst.error = _("immediate expression requires a # prefix"); | |
1114 | return FAIL; | |
1115 | } | |
1116 | (*str)++; | |
1117 | break; | |
1118 | case GE_OPT_PREFIX: | |
5287ad62 | 1119 | case GE_OPT_PREFIX_BIG: |
c19d1205 ZW |
1120 | if (is_immediate_prefix (**str)) |
1121 | (*str)++; | |
1122 | break; | |
0198d5e6 TC |
1123 | default: |
1124 | abort (); | |
c19d1205 | 1125 | } |
b99bd4ef | 1126 | |
c19d1205 | 1127 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 1128 | |
c19d1205 ZW |
1129 | save_in = input_line_pointer; |
1130 | input_line_pointer = *str; | |
0198d5e6 | 1131 | in_my_get_expression = TRUE; |
2ac93be7 | 1132 | expression (ep); |
0198d5e6 | 1133 | in_my_get_expression = FALSE; |
c19d1205 | 1134 | |
f86adc07 | 1135 | if (ep->X_op == O_illegal || ep->X_op == O_absent) |
b99bd4ef | 1136 | { |
f86adc07 | 1137 | /* We found a bad or missing expression in md_operand(). */ |
c19d1205 ZW |
1138 | *str = input_line_pointer; |
1139 | input_line_pointer = save_in; | |
1140 | if (inst.error == NULL) | |
f86adc07 NS |
1141 | inst.error = (ep->X_op == O_absent |
1142 | ? _("missing expression") :_("bad expression")); | |
c19d1205 ZW |
1143 | return 1; |
1144 | } | |
b99bd4ef | 1145 | |
c19d1205 ZW |
1146 | /* Get rid of any bignums now, so that we don't generate an error for which |
1147 | we can't establish a line number later on. Big numbers are never valid | |
1148 | in instructions, which is where this routine is always called. */ | |
5287ad62 JB |
1149 | if (prefix_mode != GE_OPT_PREFIX_BIG |
1150 | && (ep->X_op == O_big | |
477330fc | 1151 | || (ep->X_add_symbol |
5287ad62 | 1152 | && (walk_no_bignums (ep->X_add_symbol) |
477330fc | 1153 | || (ep->X_op_symbol |
5287ad62 | 1154 | && walk_no_bignums (ep->X_op_symbol)))))) |
c19d1205 ZW |
1155 | { |
1156 | inst.error = _("invalid constant"); | |
1157 | *str = input_line_pointer; | |
1158 | input_line_pointer = save_in; | |
1159 | return 1; | |
1160 | } | |
b99bd4ef | 1161 | |
c19d1205 ZW |
1162 | *str = input_line_pointer; |
1163 | input_line_pointer = save_in; | |
0198d5e6 | 1164 | return SUCCESS; |
b99bd4ef NC |
1165 | } |
1166 | ||
c19d1205 ZW |
1167 | /* Turn a string in input_line_pointer into a floating point constant |
1168 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
1169 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
1170 | returned, or NULL on OK. | |
b99bd4ef | 1171 | |
c19d1205 ZW |
1172 | Note that fp constants aren't represent in the normal way on the ARM. |
1173 | In big endian mode, things are as expected. However, in little endian | |
1174 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
1175 | within the words. For example, (double) 1.1 in big endian mode is | |
1176 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
1177 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 1178 | |
c19d1205 | 1179 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 1180 | |
6d4af3c2 | 1181 | const char * |
c19d1205 ZW |
1182 | md_atof (int type, char * litP, int * sizeP) |
1183 | { | |
1184 | int prec; | |
1185 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
1186 | char *t; | |
1187 | int i; | |
b99bd4ef | 1188 | |
c19d1205 ZW |
1189 | switch (type) |
1190 | { | |
1191 | case 'f': | |
1192 | case 'F': | |
1193 | case 's': | |
1194 | case 'S': | |
1195 | prec = 2; | |
1196 | break; | |
b99bd4ef | 1197 | |
c19d1205 ZW |
1198 | case 'd': |
1199 | case 'D': | |
1200 | case 'r': | |
1201 | case 'R': | |
1202 | prec = 4; | |
1203 | break; | |
b99bd4ef | 1204 | |
c19d1205 ZW |
1205 | case 'x': |
1206 | case 'X': | |
499ac353 | 1207 | prec = 5; |
c19d1205 | 1208 | break; |
b99bd4ef | 1209 | |
c19d1205 ZW |
1210 | case 'p': |
1211 | case 'P': | |
499ac353 | 1212 | prec = 5; |
c19d1205 | 1213 | break; |
a737bd4d | 1214 | |
c19d1205 ZW |
1215 | default: |
1216 | *sizeP = 0; | |
499ac353 | 1217 | return _("Unrecognized or unsupported floating point constant"); |
c19d1205 | 1218 | } |
b99bd4ef | 1219 | |
c19d1205 ZW |
1220 | t = atof_ieee (input_line_pointer, type, words); |
1221 | if (t) | |
1222 | input_line_pointer = t; | |
499ac353 | 1223 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
b99bd4ef | 1224 | |
c19d1205 ZW |
1225 | if (target_big_endian) |
1226 | { | |
1227 | for (i = 0; i < prec; i++) | |
1228 | { | |
499ac353 NC |
1229 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1230 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1231 | } |
1232 | } | |
1233 | else | |
1234 | { | |
e74cfd16 | 1235 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
c19d1205 ZW |
1236 | for (i = prec - 1; i >= 0; i--) |
1237 | { | |
499ac353 NC |
1238 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1239 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1240 | } |
1241 | else | |
1242 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
1243 | For an 8 byte float the order is 1 0 3 2. */ | |
1244 | for (i = 0; i < prec; i += 2) | |
1245 | { | |
499ac353 NC |
1246 | md_number_to_chars (litP, (valueT) words[i + 1], |
1247 | sizeof (LITTLENUM_TYPE)); | |
1248 | md_number_to_chars (litP + sizeof (LITTLENUM_TYPE), | |
1249 | (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
1250 | litP += 2 * sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1251 | } |
1252 | } | |
b99bd4ef | 1253 | |
499ac353 | 1254 | return NULL; |
c19d1205 | 1255 | } |
b99bd4ef | 1256 | |
c19d1205 ZW |
1257 | /* We handle all bad expressions here, so that we can report the faulty |
1258 | instruction in the error message. */ | |
0198d5e6 | 1259 | |
c19d1205 | 1260 | void |
91d6fa6a | 1261 | md_operand (expressionS * exp) |
c19d1205 ZW |
1262 | { |
1263 | if (in_my_get_expression) | |
91d6fa6a | 1264 | exp->X_op = O_illegal; |
b99bd4ef NC |
1265 | } |
1266 | ||
c19d1205 | 1267 | /* Immediate values. */ |
b99bd4ef | 1268 | |
0198d5e6 | 1269 | #ifdef OBJ_ELF |
c19d1205 ZW |
1270 | /* Generic immediate-value read function for use in directives. |
1271 | Accepts anything that 'expression' can fold to a constant. | |
1272 | *val receives the number. */ | |
0198d5e6 | 1273 | |
c19d1205 ZW |
1274 | static int |
1275 | immediate_for_directive (int *val) | |
b99bd4ef | 1276 | { |
c19d1205 ZW |
1277 | expressionS exp; |
1278 | exp.X_op = O_illegal; | |
b99bd4ef | 1279 | |
c19d1205 ZW |
1280 | if (is_immediate_prefix (*input_line_pointer)) |
1281 | { | |
1282 | input_line_pointer++; | |
1283 | expression (&exp); | |
1284 | } | |
b99bd4ef | 1285 | |
c19d1205 ZW |
1286 | if (exp.X_op != O_constant) |
1287 | { | |
1288 | as_bad (_("expected #constant")); | |
1289 | ignore_rest_of_line (); | |
1290 | return FAIL; | |
1291 | } | |
1292 | *val = exp.X_add_number; | |
1293 | return SUCCESS; | |
b99bd4ef | 1294 | } |
c19d1205 | 1295 | #endif |
b99bd4ef | 1296 | |
c19d1205 | 1297 | /* Register parsing. */ |
b99bd4ef | 1298 | |
c19d1205 ZW |
1299 | /* Generic register parser. CCP points to what should be the |
1300 | beginning of a register name. If it is indeed a valid register | |
1301 | name, advance CCP over it and return the reg_entry structure; | |
1302 | otherwise return NULL. Does not issue diagnostics. */ | |
1303 | ||
1304 | static struct reg_entry * | |
1305 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 1306 | { |
c19d1205 ZW |
1307 | char *start = *ccp; |
1308 | char *p; | |
1309 | struct reg_entry *reg; | |
b99bd4ef | 1310 | |
477330fc RM |
1311 | skip_whitespace (start); |
1312 | ||
c19d1205 ZW |
1313 | #ifdef REGISTER_PREFIX |
1314 | if (*start != REGISTER_PREFIX) | |
01cfc07f | 1315 | return NULL; |
c19d1205 ZW |
1316 | start++; |
1317 | #endif | |
1318 | #ifdef OPTIONAL_REGISTER_PREFIX | |
1319 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
1320 | start++; | |
1321 | #endif | |
b99bd4ef | 1322 | |
c19d1205 ZW |
1323 | p = start; |
1324 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
1325 | return NULL; | |
b99bd4ef | 1326 | |
c19d1205 ZW |
1327 | do |
1328 | p++; | |
1329 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
1330 | ||
1331 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
1332 | ||
1333 | if (!reg) | |
1334 | return NULL; | |
1335 | ||
1336 | *ccp = p; | |
1337 | return reg; | |
b99bd4ef NC |
1338 | } |
1339 | ||
1340 | static int | |
dcbf9037 | 1341 | arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, |
477330fc | 1342 | enum arm_reg_type type) |
b99bd4ef | 1343 | { |
c19d1205 ZW |
1344 | /* Alternative syntaxes are accepted for a few register classes. */ |
1345 | switch (type) | |
1346 | { | |
1347 | case REG_TYPE_MVF: | |
1348 | case REG_TYPE_MVD: | |
1349 | case REG_TYPE_MVFX: | |
1350 | case REG_TYPE_MVDX: | |
1351 | /* Generic coprocessor register names are allowed for these. */ | |
79134647 | 1352 | if (reg && reg->type == REG_TYPE_CN) |
c19d1205 ZW |
1353 | return reg->number; |
1354 | break; | |
69b97547 | 1355 | |
c19d1205 ZW |
1356 | case REG_TYPE_CP: |
1357 | /* For backward compatibility, a bare number is valid here. */ | |
1358 | { | |
1359 | unsigned long processor = strtoul (start, ccp, 10); | |
1360 | if (*ccp != start && processor <= 15) | |
1361 | return processor; | |
1362 | } | |
1a0670f3 | 1363 | /* Fall through. */ |
6057a28f | 1364 | |
c19d1205 ZW |
1365 | case REG_TYPE_MMXWC: |
1366 | /* WC includes WCG. ??? I'm not sure this is true for all | |
1367 | instructions that take WC registers. */ | |
79134647 | 1368 | if (reg && reg->type == REG_TYPE_MMXWCG) |
c19d1205 | 1369 | return reg->number; |
6057a28f | 1370 | break; |
c19d1205 | 1371 | |
6057a28f | 1372 | default: |
c19d1205 | 1373 | break; |
6057a28f NC |
1374 | } |
1375 | ||
dcbf9037 JB |
1376 | return FAIL; |
1377 | } | |
1378 | ||
1379 | /* As arm_reg_parse_multi, but the register must be of type TYPE, and the | |
1380 | return value is the register number or FAIL. */ | |
1381 | ||
1382 | static int | |
1383 | arm_reg_parse (char **ccp, enum arm_reg_type type) | |
1384 | { | |
1385 | char *start = *ccp; | |
1386 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
1387 | int ret; | |
1388 | ||
1389 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1390 | if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) | |
1391 | return FAIL; | |
1392 | ||
1393 | if (reg && reg->type == type) | |
1394 | return reg->number; | |
1395 | ||
1396 | if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) | |
1397 | return ret; | |
1398 | ||
c19d1205 ZW |
1399 | *ccp = start; |
1400 | return FAIL; | |
1401 | } | |
69b97547 | 1402 | |
dcbf9037 JB |
1403 | /* Parse a Neon type specifier. *STR should point at the leading '.' |
1404 | character. Does no verification at this stage that the type fits the opcode | |
1405 | properly. E.g., | |
1406 | ||
1407 | .i32.i32.s16 | |
1408 | .s32.f32 | |
1409 | .u16 | |
1410 | ||
1411 | Can all be legally parsed by this function. | |
1412 | ||
1413 | Fills in neon_type struct pointer with parsed information, and updates STR | |
1414 | to point after the parsed type specifier. Returns SUCCESS if this was a legal | |
1415 | type, FAIL if not. */ | |
1416 | ||
1417 | static int | |
1418 | parse_neon_type (struct neon_type *type, char **str) | |
1419 | { | |
1420 | char *ptr = *str; | |
1421 | ||
1422 | if (type) | |
1423 | type->elems = 0; | |
1424 | ||
1425 | while (type->elems < NEON_MAX_TYPE_ELS) | |
1426 | { | |
1427 | enum neon_el_type thistype = NT_untyped; | |
1428 | unsigned thissize = -1u; | |
1429 | ||
1430 | if (*ptr != '.') | |
1431 | break; | |
1432 | ||
1433 | ptr++; | |
1434 | ||
1435 | /* Just a size without an explicit type. */ | |
1436 | if (ISDIGIT (*ptr)) | |
1437 | goto parsesize; | |
1438 | ||
1439 | switch (TOLOWER (*ptr)) | |
1440 | { | |
1441 | case 'i': thistype = NT_integer; break; | |
1442 | case 'f': thistype = NT_float; break; | |
1443 | case 'p': thistype = NT_poly; break; | |
1444 | case 's': thistype = NT_signed; break; | |
1445 | case 'u': thistype = NT_unsigned; break; | |
477330fc RM |
1446 | case 'd': |
1447 | thistype = NT_float; | |
1448 | thissize = 64; | |
1449 | ptr++; | |
1450 | goto done; | |
dcbf9037 JB |
1451 | default: |
1452 | as_bad (_("unexpected character `%c' in type specifier"), *ptr); | |
1453 | return FAIL; | |
1454 | } | |
1455 | ||
1456 | ptr++; | |
1457 | ||
1458 | /* .f is an abbreviation for .f32. */ | |
1459 | if (thistype == NT_float && !ISDIGIT (*ptr)) | |
1460 | thissize = 32; | |
1461 | else | |
1462 | { | |
1463 | parsesize: | |
1464 | thissize = strtoul (ptr, &ptr, 10); | |
1465 | ||
1466 | if (thissize != 8 && thissize != 16 && thissize != 32 | |
477330fc RM |
1467 | && thissize != 64) |
1468 | { | |
1469 | as_bad (_("bad size %d in type specifier"), thissize); | |
dcbf9037 JB |
1470 | return FAIL; |
1471 | } | |
1472 | } | |
1473 | ||
037e8744 | 1474 | done: |
dcbf9037 | 1475 | if (type) |
477330fc RM |
1476 | { |
1477 | type->el[type->elems].type = thistype; | |
dcbf9037 JB |
1478 | type->el[type->elems].size = thissize; |
1479 | type->elems++; | |
1480 | } | |
1481 | } | |
1482 | ||
1483 | /* Empty/missing type is not a successful parse. */ | |
1484 | if (type->elems == 0) | |
1485 | return FAIL; | |
1486 | ||
1487 | *str = ptr; | |
1488 | ||
1489 | return SUCCESS; | |
1490 | } | |
1491 | ||
1492 | /* Errors may be set multiple times during parsing or bit encoding | |
1493 | (particularly in the Neon bits), but usually the earliest error which is set | |
1494 | will be the most meaningful. Avoid overwriting it with later (cascading) | |
1495 | errors by calling this function. */ | |
1496 | ||
1497 | static void | |
1498 | first_error (const char *err) | |
1499 | { | |
1500 | if (!inst.error) | |
1501 | inst.error = err; | |
1502 | } | |
1503 | ||
1504 | /* Parse a single type, e.g. ".s32", leading period included. */ | |
1505 | static int | |
1506 | parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) | |
1507 | { | |
1508 | char *str = *ccp; | |
1509 | struct neon_type optype; | |
1510 | ||
1511 | if (*str == '.') | |
1512 | { | |
1513 | if (parse_neon_type (&optype, &str) == SUCCESS) | |
477330fc RM |
1514 | { |
1515 | if (optype.elems == 1) | |
1516 | *vectype = optype.el[0]; | |
1517 | else | |
1518 | { | |
1519 | first_error (_("only one type should be specified for operand")); | |
1520 | return FAIL; | |
1521 | } | |
1522 | } | |
dcbf9037 | 1523 | else |
477330fc RM |
1524 | { |
1525 | first_error (_("vector type expected")); | |
1526 | return FAIL; | |
1527 | } | |
dcbf9037 JB |
1528 | } |
1529 | else | |
1530 | return FAIL; | |
5f4273c7 | 1531 | |
dcbf9037 | 1532 | *ccp = str; |
5f4273c7 | 1533 | |
dcbf9037 JB |
1534 | return SUCCESS; |
1535 | } | |
1536 | ||
1537 | /* Special meanings for indices (which have a range of 0-7), which will fit into | |
1538 | a 4-bit integer. */ | |
1539 | ||
1540 | #define NEON_ALL_LANES 15 | |
1541 | #define NEON_INTERLEAVE_LANES 14 | |
1542 | ||
5ee91343 AV |
1543 | /* Record a use of the given feature. */ |
1544 | static void | |
1545 | record_feature_use (const arm_feature_set *feature) | |
1546 | { | |
1547 | if (thumb_mode) | |
1548 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature); | |
1549 | else | |
1550 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature); | |
1551 | } | |
1552 | ||
1553 | /* If the given feature available in the selected CPU, mark it as used. | |
1554 | Returns TRUE iff feature is available. */ | |
1555 | static bfd_boolean | |
1556 | mark_feature_used (const arm_feature_set *feature) | |
1557 | { | |
886e1c73 AV |
1558 | |
1559 | /* Do not support the use of MVE only instructions when in auto-detection or | |
1560 | -march=all. */ | |
1561 | if (((feature == &mve_ext) || (feature == &mve_fp_ext)) | |
1562 | && ARM_CPU_IS_ANY (cpu_variant)) | |
1563 | { | |
1564 | first_error (BAD_MVE_AUTO); | |
1565 | return FALSE; | |
1566 | } | |
5ee91343 AV |
1567 | /* Ensure the option is valid on the current architecture. */ |
1568 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature)) | |
1569 | return FALSE; | |
1570 | ||
1571 | /* Add the appropriate architecture feature for the barrier option used. | |
1572 | */ | |
1573 | record_feature_use (feature); | |
1574 | ||
1575 | return TRUE; | |
1576 | } | |
1577 | ||
dcbf9037 JB |
1578 | /* Parse either a register or a scalar, with an optional type. Return the |
1579 | register number, and optionally fill in the actual type of the register | |
1580 | when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and | |
1581 | type/index information in *TYPEINFO. */ | |
1582 | ||
1583 | static int | |
1584 | parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, | |
477330fc RM |
1585 | enum arm_reg_type *rtype, |
1586 | struct neon_typed_alias *typeinfo) | |
dcbf9037 JB |
1587 | { |
1588 | char *str = *ccp; | |
1589 | struct reg_entry *reg = arm_reg_parse_multi (&str); | |
1590 | struct neon_typed_alias atype; | |
1591 | struct neon_type_el parsetype; | |
1592 | ||
1593 | atype.defined = 0; | |
1594 | atype.index = -1; | |
1595 | atype.eltype.type = NT_invtype; | |
1596 | atype.eltype.size = -1; | |
1597 | ||
1598 | /* Try alternate syntax for some types of register. Note these are mutually | |
1599 | exclusive with the Neon syntax extensions. */ | |
1600 | if (reg == NULL) | |
1601 | { | |
1602 | int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); | |
1603 | if (altreg != FAIL) | |
477330fc | 1604 | *ccp = str; |
dcbf9037 | 1605 | if (typeinfo) |
477330fc | 1606 | *typeinfo = atype; |
dcbf9037 JB |
1607 | return altreg; |
1608 | } | |
1609 | ||
037e8744 JB |
1610 | /* Undo polymorphism when a set of register types may be accepted. */ |
1611 | if ((type == REG_TYPE_NDQ | |
1612 | && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) | |
1613 | || (type == REG_TYPE_VFSD | |
477330fc | 1614 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) |
037e8744 | 1615 | || (type == REG_TYPE_NSDQ |
477330fc RM |
1616 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD |
1617 | || reg->type == REG_TYPE_NQ)) | |
dec41383 JW |
1618 | || (type == REG_TYPE_NSD |
1619 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) | |
f512f76f NC |
1620 | || (type == REG_TYPE_MMXWC |
1621 | && (reg->type == REG_TYPE_MMXWCG))) | |
21d799b5 | 1622 | type = (enum arm_reg_type) reg->type; |
dcbf9037 | 1623 | |
5ee91343 AV |
1624 | if (type == REG_TYPE_MQ) |
1625 | { | |
1626 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
1627 | return FAIL; | |
1628 | ||
1629 | if (!reg || reg->type != REG_TYPE_NQ) | |
1630 | return FAIL; | |
1631 | ||
1632 | if (reg->number > 14 && !mark_feature_used (&fpu_vfp_ext_d32)) | |
1633 | { | |
1634 | first_error (_("expected MVE register [q0..q7]")); | |
1635 | return FAIL; | |
1636 | } | |
1637 | type = REG_TYPE_NQ; | |
1638 | } | |
1639 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
1640 | && (type == REG_TYPE_NQ)) | |
1641 | return FAIL; | |
1642 | ||
1643 | ||
dcbf9037 JB |
1644 | if (type != reg->type) |
1645 | return FAIL; | |
1646 | ||
1647 | if (reg->neon) | |
1648 | atype = *reg->neon; | |
5f4273c7 | 1649 | |
dcbf9037 JB |
1650 | if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) |
1651 | { | |
1652 | if ((atype.defined & NTA_HASTYPE) != 0) | |
477330fc RM |
1653 | { |
1654 | first_error (_("can't redefine type for operand")); | |
1655 | return FAIL; | |
1656 | } | |
dcbf9037 JB |
1657 | atype.defined |= NTA_HASTYPE; |
1658 | atype.eltype = parsetype; | |
1659 | } | |
5f4273c7 | 1660 | |
dcbf9037 JB |
1661 | if (skip_past_char (&str, '[') == SUCCESS) |
1662 | { | |
dec41383 JW |
1663 | if (type != REG_TYPE_VFD |
1664 | && !(type == REG_TYPE_VFS | |
57785aa2 AV |
1665 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_2)) |
1666 | && !(type == REG_TYPE_NQ | |
1667 | && ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))) | |
477330fc | 1668 | { |
57785aa2 AV |
1669 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
1670 | first_error (_("only D and Q registers may be indexed")); | |
1671 | else | |
1672 | first_error (_("only D registers may be indexed")); | |
477330fc RM |
1673 | return FAIL; |
1674 | } | |
5f4273c7 | 1675 | |
dcbf9037 | 1676 | if ((atype.defined & NTA_HASINDEX) != 0) |
477330fc RM |
1677 | { |
1678 | first_error (_("can't change index for operand")); | |
1679 | return FAIL; | |
1680 | } | |
dcbf9037 JB |
1681 | |
1682 | atype.defined |= NTA_HASINDEX; | |
1683 | ||
1684 | if (skip_past_char (&str, ']') == SUCCESS) | |
477330fc | 1685 | atype.index = NEON_ALL_LANES; |
dcbf9037 | 1686 | else |
477330fc RM |
1687 | { |
1688 | expressionS exp; | |
dcbf9037 | 1689 | |
477330fc | 1690 | my_get_expression (&exp, &str, GE_NO_PREFIX); |
dcbf9037 | 1691 | |
477330fc RM |
1692 | if (exp.X_op != O_constant) |
1693 | { | |
1694 | first_error (_("constant expression required")); | |
1695 | return FAIL; | |
1696 | } | |
dcbf9037 | 1697 | |
477330fc RM |
1698 | if (skip_past_char (&str, ']') == FAIL) |
1699 | return FAIL; | |
dcbf9037 | 1700 | |
477330fc RM |
1701 | atype.index = exp.X_add_number; |
1702 | } | |
dcbf9037 | 1703 | } |
5f4273c7 | 1704 | |
dcbf9037 JB |
1705 | if (typeinfo) |
1706 | *typeinfo = atype; | |
5f4273c7 | 1707 | |
dcbf9037 JB |
1708 | if (rtype) |
1709 | *rtype = type; | |
5f4273c7 | 1710 | |
dcbf9037 | 1711 | *ccp = str; |
5f4273c7 | 1712 | |
dcbf9037 JB |
1713 | return reg->number; |
1714 | } | |
1715 | ||
efd6b359 | 1716 | /* Like arm_reg_parse, but also allow the following extra features: |
dcbf9037 JB |
1717 | - If RTYPE is non-zero, return the (possibly restricted) type of the |
1718 | register (e.g. Neon double or quad reg when either has been requested). | |
1719 | - If this is a Neon vector type with additional type information, fill | |
1720 | in the struct pointed to by VECTYPE (if non-NULL). | |
5f4273c7 | 1721 | This function will fault on encountering a scalar. */ |
dcbf9037 JB |
1722 | |
1723 | static int | |
1724 | arm_typed_reg_parse (char **ccp, enum arm_reg_type type, | |
477330fc | 1725 | enum arm_reg_type *rtype, struct neon_type_el *vectype) |
dcbf9037 JB |
1726 | { |
1727 | struct neon_typed_alias atype; | |
1728 | char *str = *ccp; | |
1729 | int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); | |
1730 | ||
1731 | if (reg == FAIL) | |
1732 | return FAIL; | |
1733 | ||
0855e32b NS |
1734 | /* Do not allow regname(... to parse as a register. */ |
1735 | if (*str == '(') | |
1736 | return FAIL; | |
1737 | ||
dcbf9037 JB |
1738 | /* Do not allow a scalar (reg+index) to parse as a register. */ |
1739 | if ((atype.defined & NTA_HASINDEX) != 0) | |
1740 | { | |
1741 | first_error (_("register operand expected, but got scalar")); | |
1742 | return FAIL; | |
1743 | } | |
1744 | ||
1745 | if (vectype) | |
1746 | *vectype = atype.eltype; | |
1747 | ||
1748 | *ccp = str; | |
1749 | ||
1750 | return reg; | |
1751 | } | |
1752 | ||
1753 | #define NEON_SCALAR_REG(X) ((X) >> 4) | |
1754 | #define NEON_SCALAR_INDEX(X) ((X) & 15) | |
1755 | ||
5287ad62 JB |
1756 | /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't |
1757 | have enough information to be able to do a good job bounds-checking. So, we | |
1758 | just do easy checks here, and do further checks later. */ | |
1759 | ||
1760 | static int | |
57785aa2 AV |
1761 | parse_scalar (char **ccp, int elsize, struct neon_type_el *type, enum |
1762 | arm_reg_type reg_type) | |
5287ad62 | 1763 | { |
dcbf9037 | 1764 | int reg; |
5287ad62 | 1765 | char *str = *ccp; |
dcbf9037 | 1766 | struct neon_typed_alias atype; |
57785aa2 | 1767 | unsigned reg_size; |
5f4273c7 | 1768 | |
dec41383 | 1769 | reg = parse_typed_reg_or_scalar (&str, reg_type, NULL, &atype); |
5f4273c7 | 1770 | |
57785aa2 AV |
1771 | switch (reg_type) |
1772 | { | |
1773 | case REG_TYPE_VFS: | |
1774 | reg_size = 32; | |
1775 | break; | |
1776 | case REG_TYPE_VFD: | |
1777 | reg_size = 64; | |
1778 | break; | |
1779 | case REG_TYPE_MQ: | |
1780 | reg_size = 128; | |
1781 | break; | |
1782 | default: | |
1783 | gas_assert (0); | |
1784 | return FAIL; | |
1785 | } | |
1786 | ||
dcbf9037 | 1787 | if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) |
5287ad62 | 1788 | return FAIL; |
5f4273c7 | 1789 | |
57785aa2 | 1790 | if (reg_type != REG_TYPE_MQ && atype.index == NEON_ALL_LANES) |
5287ad62 | 1791 | { |
dcbf9037 | 1792 | first_error (_("scalar must have an index")); |
5287ad62 JB |
1793 | return FAIL; |
1794 | } | |
57785aa2 | 1795 | else if (atype.index >= reg_size / elsize) |
5287ad62 | 1796 | { |
dcbf9037 | 1797 | first_error (_("scalar index out of range")); |
5287ad62 JB |
1798 | return FAIL; |
1799 | } | |
5f4273c7 | 1800 | |
dcbf9037 JB |
1801 | if (type) |
1802 | *type = atype.eltype; | |
5f4273c7 | 1803 | |
5287ad62 | 1804 | *ccp = str; |
5f4273c7 | 1805 | |
dcbf9037 | 1806 | return reg * 16 + atype.index; |
5287ad62 JB |
1807 | } |
1808 | ||
4b5a202f AV |
1809 | /* Types of registers in a list. */ |
1810 | ||
1811 | enum reg_list_els | |
1812 | { | |
1813 | REGLIST_RN, | |
1814 | REGLIST_CLRM, | |
1815 | REGLIST_VFP_S, | |
efd6b359 | 1816 | REGLIST_VFP_S_VPR, |
4b5a202f | 1817 | REGLIST_VFP_D, |
efd6b359 | 1818 | REGLIST_VFP_D_VPR, |
4b5a202f AV |
1819 | REGLIST_NEON_D |
1820 | }; | |
1821 | ||
c19d1205 | 1822 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
e07e6e58 | 1823 | |
c19d1205 | 1824 | static long |
4b5a202f | 1825 | parse_reg_list (char ** strp, enum reg_list_els etype) |
c19d1205 | 1826 | { |
4b5a202f AV |
1827 | char *str = *strp; |
1828 | long range = 0; | |
1829 | int another_range; | |
1830 | ||
1831 | gas_assert (etype == REGLIST_RN || etype == REGLIST_CLRM); | |
a737bd4d | 1832 | |
c19d1205 ZW |
1833 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
1834 | do | |
6057a28f | 1835 | { |
477330fc RM |
1836 | skip_whitespace (str); |
1837 | ||
c19d1205 | 1838 | another_range = 0; |
a737bd4d | 1839 | |
c19d1205 ZW |
1840 | if (*str == '{') |
1841 | { | |
1842 | int in_range = 0; | |
1843 | int cur_reg = -1; | |
a737bd4d | 1844 | |
c19d1205 ZW |
1845 | str++; |
1846 | do | |
1847 | { | |
1848 | int reg; | |
4b5a202f AV |
1849 | const char apsr_str[] = "apsr"; |
1850 | int apsr_str_len = strlen (apsr_str); | |
6057a28f | 1851 | |
4b5a202f AV |
1852 | reg = arm_reg_parse (&str, REGLIST_RN); |
1853 | if (etype == REGLIST_CLRM) | |
c19d1205 | 1854 | { |
4b5a202f AV |
1855 | if (reg == REG_SP || reg == REG_PC) |
1856 | reg = FAIL; | |
1857 | else if (reg == FAIL | |
1858 | && !strncasecmp (str, apsr_str, apsr_str_len) | |
1859 | && !ISALPHA (*(str + apsr_str_len))) | |
1860 | { | |
1861 | reg = 15; | |
1862 | str += apsr_str_len; | |
1863 | } | |
1864 | ||
1865 | if (reg == FAIL) | |
1866 | { | |
1867 | first_error (_("r0-r12, lr or APSR expected")); | |
1868 | return FAIL; | |
1869 | } | |
1870 | } | |
1871 | else /* etype == REGLIST_RN. */ | |
1872 | { | |
1873 | if (reg == FAIL) | |
1874 | { | |
1875 | first_error (_(reg_expected_msgs[REGLIST_RN])); | |
1876 | return FAIL; | |
1877 | } | |
c19d1205 | 1878 | } |
a737bd4d | 1879 | |
c19d1205 ZW |
1880 | if (in_range) |
1881 | { | |
1882 | int i; | |
a737bd4d | 1883 | |
c19d1205 ZW |
1884 | if (reg <= cur_reg) |
1885 | { | |
dcbf9037 | 1886 | first_error (_("bad range in register list")); |
c19d1205 ZW |
1887 | return FAIL; |
1888 | } | |
40a18ebd | 1889 | |
c19d1205 ZW |
1890 | for (i = cur_reg + 1; i < reg; i++) |
1891 | { | |
1892 | if (range & (1 << i)) | |
1893 | as_tsktsk | |
1894 | (_("Warning: duplicated register (r%d) in register list"), | |
1895 | i); | |
1896 | else | |
1897 | range |= 1 << i; | |
1898 | } | |
1899 | in_range = 0; | |
1900 | } | |
a737bd4d | 1901 | |
c19d1205 ZW |
1902 | if (range & (1 << reg)) |
1903 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
1904 | reg); | |
1905 | else if (reg <= cur_reg) | |
1906 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 1907 | |
c19d1205 ZW |
1908 | range |= 1 << reg; |
1909 | cur_reg = reg; | |
1910 | } | |
1911 | while (skip_past_comma (&str) != FAIL | |
1912 | || (in_range = 1, *str++ == '-')); | |
1913 | str--; | |
a737bd4d | 1914 | |
d996d970 | 1915 | if (skip_past_char (&str, '}') == FAIL) |
c19d1205 | 1916 | { |
dcbf9037 | 1917 | first_error (_("missing `}'")); |
c19d1205 ZW |
1918 | return FAIL; |
1919 | } | |
1920 | } | |
4b5a202f | 1921 | else if (etype == REGLIST_RN) |
c19d1205 | 1922 | { |
91d6fa6a | 1923 | expressionS exp; |
40a18ebd | 1924 | |
91d6fa6a | 1925 | if (my_get_expression (&exp, &str, GE_NO_PREFIX)) |
c19d1205 | 1926 | return FAIL; |
40a18ebd | 1927 | |
91d6fa6a | 1928 | if (exp.X_op == O_constant) |
c19d1205 | 1929 | { |
91d6fa6a NC |
1930 | if (exp.X_add_number |
1931 | != (exp.X_add_number & 0x0000ffff)) | |
c19d1205 ZW |
1932 | { |
1933 | inst.error = _("invalid register mask"); | |
1934 | return FAIL; | |
1935 | } | |
a737bd4d | 1936 | |
91d6fa6a | 1937 | if ((range & exp.X_add_number) != 0) |
c19d1205 | 1938 | { |
91d6fa6a | 1939 | int regno = range & exp.X_add_number; |
a737bd4d | 1940 | |
c19d1205 ZW |
1941 | regno &= -regno; |
1942 | regno = (1 << regno) - 1; | |
1943 | as_tsktsk | |
1944 | (_("Warning: duplicated register (r%d) in register list"), | |
1945 | regno); | |
1946 | } | |
a737bd4d | 1947 | |
91d6fa6a | 1948 | range |= exp.X_add_number; |
c19d1205 ZW |
1949 | } |
1950 | else | |
1951 | { | |
e2b0ab59 | 1952 | if (inst.relocs[0].type != 0) |
c19d1205 ZW |
1953 | { |
1954 | inst.error = _("expression too complex"); | |
1955 | return FAIL; | |
1956 | } | |
a737bd4d | 1957 | |
e2b0ab59 AV |
1958 | memcpy (&inst.relocs[0].exp, &exp, sizeof (expressionS)); |
1959 | inst.relocs[0].type = BFD_RELOC_ARM_MULTI; | |
1960 | inst.relocs[0].pc_rel = 0; | |
c19d1205 ZW |
1961 | } |
1962 | } | |
a737bd4d | 1963 | |
c19d1205 ZW |
1964 | if (*str == '|' || *str == '+') |
1965 | { | |
1966 | str++; | |
1967 | another_range = 1; | |
1968 | } | |
a737bd4d | 1969 | } |
c19d1205 | 1970 | while (another_range); |
a737bd4d | 1971 | |
c19d1205 ZW |
1972 | *strp = str; |
1973 | return range; | |
a737bd4d NC |
1974 | } |
1975 | ||
c19d1205 ZW |
1976 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1977 | Otherwise return the number of registers, and set PBASE to the first | |
5287ad62 JB |
1978 | register. Parses registers of type ETYPE. |
1979 | If REGLIST_NEON_D is used, several syntax enhancements are enabled: | |
1980 | - Q registers can be used to specify pairs of D registers | |
1981 | - { } can be omitted from around a singleton register list | |
477330fc RM |
1982 | FIXME: This is not implemented, as it would require backtracking in |
1983 | some cases, e.g.: | |
1984 | vtbl.8 d3,d4,d5 | |
1985 | This could be done (the meaning isn't really ambiguous), but doesn't | |
1986 | fit in well with the current parsing framework. | |
dcbf9037 JB |
1987 | - 32 D registers may be used (also true for VFPv3). |
1988 | FIXME: Types are ignored in these register lists, which is probably a | |
1989 | bug. */ | |
6057a28f | 1990 | |
c19d1205 | 1991 | static int |
efd6b359 AV |
1992 | parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype, |
1993 | bfd_boolean *partial_match) | |
6057a28f | 1994 | { |
037e8744 | 1995 | char *str = *ccp; |
c19d1205 ZW |
1996 | int base_reg; |
1997 | int new_base; | |
21d799b5 | 1998 | enum arm_reg_type regtype = (enum arm_reg_type) 0; |
5287ad62 | 1999 | int max_regs = 0; |
c19d1205 ZW |
2000 | int count = 0; |
2001 | int warned = 0; | |
2002 | unsigned long mask = 0; | |
a737bd4d | 2003 | int i; |
efd6b359 AV |
2004 | bfd_boolean vpr_seen = FALSE; |
2005 | bfd_boolean expect_vpr = | |
2006 | (etype == REGLIST_VFP_S_VPR) || (etype == REGLIST_VFP_D_VPR); | |
6057a28f | 2007 | |
477330fc | 2008 | if (skip_past_char (&str, '{') == FAIL) |
5287ad62 JB |
2009 | { |
2010 | inst.error = _("expecting {"); | |
2011 | return FAIL; | |
2012 | } | |
6057a28f | 2013 | |
5287ad62 | 2014 | switch (etype) |
c19d1205 | 2015 | { |
5287ad62 | 2016 | case REGLIST_VFP_S: |
efd6b359 | 2017 | case REGLIST_VFP_S_VPR: |
c19d1205 ZW |
2018 | regtype = REG_TYPE_VFS; |
2019 | max_regs = 32; | |
5287ad62 | 2020 | break; |
5f4273c7 | 2021 | |
5287ad62 | 2022 | case REGLIST_VFP_D: |
efd6b359 | 2023 | case REGLIST_VFP_D_VPR: |
5287ad62 | 2024 | regtype = REG_TYPE_VFD; |
b7fc2769 | 2025 | break; |
5f4273c7 | 2026 | |
b7fc2769 JB |
2027 | case REGLIST_NEON_D: |
2028 | regtype = REG_TYPE_NDQ; | |
2029 | break; | |
4b5a202f AV |
2030 | |
2031 | default: | |
2032 | gas_assert (0); | |
b7fc2769 JB |
2033 | } |
2034 | ||
efd6b359 | 2035 | if (etype != REGLIST_VFP_S && etype != REGLIST_VFP_S_VPR) |
b7fc2769 | 2036 | { |
b1cc4aeb PB |
2037 | /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */ |
2038 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) | |
477330fc RM |
2039 | { |
2040 | max_regs = 32; | |
2041 | if (thumb_mode) | |
2042 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
2043 | fpu_vfp_ext_d32); | |
2044 | else | |
2045 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
2046 | fpu_vfp_ext_d32); | |
2047 | } | |
5287ad62 | 2048 | else |
477330fc | 2049 | max_regs = 16; |
c19d1205 | 2050 | } |
6057a28f | 2051 | |
c19d1205 | 2052 | base_reg = max_regs; |
efd6b359 | 2053 | *partial_match = FALSE; |
a737bd4d | 2054 | |
c19d1205 ZW |
2055 | do |
2056 | { | |
5287ad62 | 2057 | int setmask = 1, addregs = 1; |
efd6b359 AV |
2058 | const char vpr_str[] = "vpr"; |
2059 | int vpr_str_len = strlen (vpr_str); | |
dcbf9037 | 2060 | |
037e8744 | 2061 | new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); |
dcbf9037 | 2062 | |
efd6b359 AV |
2063 | if (expect_vpr) |
2064 | { | |
2065 | if (new_base == FAIL | |
2066 | && !strncasecmp (str, vpr_str, vpr_str_len) | |
2067 | && !ISALPHA (*(str + vpr_str_len)) | |
2068 | && !vpr_seen) | |
2069 | { | |
2070 | vpr_seen = TRUE; | |
2071 | str += vpr_str_len; | |
2072 | if (count == 0) | |
2073 | base_reg = 0; /* Canonicalize VPR only on d0 with 0 regs. */ | |
2074 | } | |
2075 | else if (vpr_seen) | |
2076 | { | |
2077 | first_error (_("VPR expected last")); | |
2078 | return FAIL; | |
2079 | } | |
2080 | else if (new_base == FAIL) | |
2081 | { | |
2082 | if (regtype == REG_TYPE_VFS) | |
2083 | first_error (_("VFP single precision register or VPR " | |
2084 | "expected")); | |
2085 | else /* regtype == REG_TYPE_VFD. */ | |
2086 | first_error (_("VFP/Neon double precision register or VPR " | |
2087 | "expected")); | |
2088 | return FAIL; | |
2089 | } | |
2090 | } | |
2091 | else if (new_base == FAIL) | |
a737bd4d | 2092 | { |
dcbf9037 | 2093 | first_error (_(reg_expected_msgs[regtype])); |
c19d1205 ZW |
2094 | return FAIL; |
2095 | } | |
5f4273c7 | 2096 | |
efd6b359 AV |
2097 | *partial_match = TRUE; |
2098 | if (vpr_seen) | |
2099 | continue; | |
2100 | ||
b7fc2769 | 2101 | if (new_base >= max_regs) |
477330fc RM |
2102 | { |
2103 | first_error (_("register out of range in list")); | |
2104 | return FAIL; | |
2105 | } | |
5f4273c7 | 2106 | |
5287ad62 JB |
2107 | /* Note: a value of 2 * n is returned for the register Q<n>. */ |
2108 | if (regtype == REG_TYPE_NQ) | |
477330fc RM |
2109 | { |
2110 | setmask = 3; | |
2111 | addregs = 2; | |
2112 | } | |
5287ad62 | 2113 | |
c19d1205 ZW |
2114 | if (new_base < base_reg) |
2115 | base_reg = new_base; | |
a737bd4d | 2116 | |
5287ad62 | 2117 | if (mask & (setmask << new_base)) |
c19d1205 | 2118 | { |
dcbf9037 | 2119 | first_error (_("invalid register list")); |
c19d1205 | 2120 | return FAIL; |
a737bd4d | 2121 | } |
a737bd4d | 2122 | |
efd6b359 | 2123 | if ((mask >> new_base) != 0 && ! warned && !vpr_seen) |
c19d1205 ZW |
2124 | { |
2125 | as_tsktsk (_("register list not in ascending order")); | |
2126 | warned = 1; | |
2127 | } | |
0bbf2aa4 | 2128 | |
5287ad62 JB |
2129 | mask |= setmask << new_base; |
2130 | count += addregs; | |
0bbf2aa4 | 2131 | |
037e8744 | 2132 | if (*str == '-') /* We have the start of a range expression */ |
c19d1205 ZW |
2133 | { |
2134 | int high_range; | |
0bbf2aa4 | 2135 | |
037e8744 | 2136 | str++; |
0bbf2aa4 | 2137 | |
037e8744 | 2138 | if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) |
477330fc | 2139 | == FAIL) |
c19d1205 ZW |
2140 | { |
2141 | inst.error = gettext (reg_expected_msgs[regtype]); | |
2142 | return FAIL; | |
2143 | } | |
0bbf2aa4 | 2144 | |
477330fc RM |
2145 | if (high_range >= max_regs) |
2146 | { | |
2147 | first_error (_("register out of range in list")); | |
2148 | return FAIL; | |
2149 | } | |
b7fc2769 | 2150 | |
477330fc RM |
2151 | if (regtype == REG_TYPE_NQ) |
2152 | high_range = high_range + 1; | |
5287ad62 | 2153 | |
c19d1205 ZW |
2154 | if (high_range <= new_base) |
2155 | { | |
2156 | inst.error = _("register range not in ascending order"); | |
2157 | return FAIL; | |
2158 | } | |
0bbf2aa4 | 2159 | |
5287ad62 | 2160 | for (new_base += addregs; new_base <= high_range; new_base += addregs) |
0bbf2aa4 | 2161 | { |
5287ad62 | 2162 | if (mask & (setmask << new_base)) |
0bbf2aa4 | 2163 | { |
c19d1205 ZW |
2164 | inst.error = _("invalid register list"); |
2165 | return FAIL; | |
0bbf2aa4 | 2166 | } |
c19d1205 | 2167 | |
5287ad62 JB |
2168 | mask |= setmask << new_base; |
2169 | count += addregs; | |
0bbf2aa4 | 2170 | } |
0bbf2aa4 | 2171 | } |
0bbf2aa4 | 2172 | } |
037e8744 | 2173 | while (skip_past_comma (&str) != FAIL); |
0bbf2aa4 | 2174 | |
037e8744 | 2175 | str++; |
0bbf2aa4 | 2176 | |
c19d1205 | 2177 | /* Sanity check -- should have raised a parse error above. */ |
efd6b359 | 2178 | if ((!vpr_seen && count == 0) || count > max_regs) |
c19d1205 ZW |
2179 | abort (); |
2180 | ||
2181 | *pbase = base_reg; | |
2182 | ||
efd6b359 AV |
2183 | if (expect_vpr && !vpr_seen) |
2184 | { | |
2185 | first_error (_("VPR expected last")); | |
2186 | return FAIL; | |
2187 | } | |
2188 | ||
c19d1205 ZW |
2189 | /* Final test -- the registers must be consecutive. */ |
2190 | mask >>= base_reg; | |
2191 | for (i = 0; i < count; i++) | |
2192 | { | |
2193 | if ((mask & (1u << i)) == 0) | |
2194 | { | |
2195 | inst.error = _("non-contiguous register range"); | |
2196 | return FAIL; | |
2197 | } | |
2198 | } | |
2199 | ||
037e8744 JB |
2200 | *ccp = str; |
2201 | ||
c19d1205 | 2202 | return count; |
b99bd4ef NC |
2203 | } |
2204 | ||
dcbf9037 JB |
2205 | /* True if two alias types are the same. */ |
2206 | ||
c921be7d | 2207 | static bfd_boolean |
dcbf9037 JB |
2208 | neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) |
2209 | { | |
2210 | if (!a && !b) | |
c921be7d | 2211 | return TRUE; |
5f4273c7 | 2212 | |
dcbf9037 | 2213 | if (!a || !b) |
c921be7d | 2214 | return FALSE; |
dcbf9037 JB |
2215 | |
2216 | if (a->defined != b->defined) | |
c921be7d | 2217 | return FALSE; |
5f4273c7 | 2218 | |
dcbf9037 JB |
2219 | if ((a->defined & NTA_HASTYPE) != 0 |
2220 | && (a->eltype.type != b->eltype.type | |
477330fc | 2221 | || a->eltype.size != b->eltype.size)) |
c921be7d | 2222 | return FALSE; |
dcbf9037 JB |
2223 | |
2224 | if ((a->defined & NTA_HASINDEX) != 0 | |
2225 | && (a->index != b->index)) | |
c921be7d | 2226 | return FALSE; |
5f4273c7 | 2227 | |
c921be7d | 2228 | return TRUE; |
dcbf9037 JB |
2229 | } |
2230 | ||
5287ad62 JB |
2231 | /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. |
2232 | The base register is put in *PBASE. | |
dcbf9037 | 2233 | The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of |
5287ad62 JB |
2234 | the return value. |
2235 | The register stride (minus one) is put in bit 4 of the return value. | |
dcbf9037 JB |
2236 | Bits [6:5] encode the list length (minus one). |
2237 | The type of the list elements is put in *ELTYPE, if non-NULL. */ | |
5287ad62 | 2238 | |
5287ad62 | 2239 | #define NEON_LANE(X) ((X) & 0xf) |
dcbf9037 | 2240 | #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) |
5287ad62 JB |
2241 | #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) |
2242 | ||
2243 | static int | |
dcbf9037 | 2244 | parse_neon_el_struct_list (char **str, unsigned *pbase, |
35c228db | 2245 | int mve, |
477330fc | 2246 | struct neon_type_el *eltype) |
5287ad62 JB |
2247 | { |
2248 | char *ptr = *str; | |
2249 | int base_reg = -1; | |
2250 | int reg_incr = -1; | |
2251 | int count = 0; | |
2252 | int lane = -1; | |
2253 | int leading_brace = 0; | |
2254 | enum arm_reg_type rtype = REG_TYPE_NDQ; | |
35c228db AV |
2255 | const char *const incr_error = mve ? _("register stride must be 1") : |
2256 | _("register stride must be 1 or 2"); | |
20203fb9 | 2257 | const char *const type_error = _("mismatched element/structure types in list"); |
dcbf9037 | 2258 | struct neon_typed_alias firsttype; |
f85d59c3 KT |
2259 | firsttype.defined = 0; |
2260 | firsttype.eltype.type = NT_invtype; | |
2261 | firsttype.eltype.size = -1; | |
2262 | firsttype.index = -1; | |
5f4273c7 | 2263 | |
5287ad62 JB |
2264 | if (skip_past_char (&ptr, '{') == SUCCESS) |
2265 | leading_brace = 1; | |
5f4273c7 | 2266 | |
5287ad62 JB |
2267 | do |
2268 | { | |
dcbf9037 | 2269 | struct neon_typed_alias atype; |
35c228db AV |
2270 | if (mve) |
2271 | rtype = REG_TYPE_MQ; | |
dcbf9037 JB |
2272 | int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); |
2273 | ||
5287ad62 | 2274 | if (getreg == FAIL) |
477330fc RM |
2275 | { |
2276 | first_error (_(reg_expected_msgs[rtype])); | |
2277 | return FAIL; | |
2278 | } | |
5f4273c7 | 2279 | |
5287ad62 | 2280 | if (base_reg == -1) |
477330fc RM |
2281 | { |
2282 | base_reg = getreg; | |
2283 | if (rtype == REG_TYPE_NQ) | |
2284 | { | |
2285 | reg_incr = 1; | |
2286 | } | |
2287 | firsttype = atype; | |
2288 | } | |
5287ad62 | 2289 | else if (reg_incr == -1) |
477330fc RM |
2290 | { |
2291 | reg_incr = getreg - base_reg; | |
2292 | if (reg_incr < 1 || reg_incr > 2) | |
2293 | { | |
2294 | first_error (_(incr_error)); | |
2295 | return FAIL; | |
2296 | } | |
2297 | } | |
5287ad62 | 2298 | else if (getreg != base_reg + reg_incr * count) |
477330fc RM |
2299 | { |
2300 | first_error (_(incr_error)); | |
2301 | return FAIL; | |
2302 | } | |
dcbf9037 | 2303 | |
c921be7d | 2304 | if (! neon_alias_types_same (&atype, &firsttype)) |
477330fc RM |
2305 | { |
2306 | first_error (_(type_error)); | |
2307 | return FAIL; | |
2308 | } | |
5f4273c7 | 2309 | |
5287ad62 | 2310 | /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list |
477330fc | 2311 | modes. */ |
5287ad62 | 2312 | if (ptr[0] == '-') |
477330fc RM |
2313 | { |
2314 | struct neon_typed_alias htype; | |
2315 | int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; | |
2316 | if (lane == -1) | |
2317 | lane = NEON_INTERLEAVE_LANES; | |
2318 | else if (lane != NEON_INTERLEAVE_LANES) | |
2319 | { | |
2320 | first_error (_(type_error)); | |
2321 | return FAIL; | |
2322 | } | |
2323 | if (reg_incr == -1) | |
2324 | reg_incr = 1; | |
2325 | else if (reg_incr != 1) | |
2326 | { | |
2327 | first_error (_("don't use Rn-Rm syntax with non-unit stride")); | |
2328 | return FAIL; | |
2329 | } | |
2330 | ptr++; | |
2331 | hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); | |
2332 | if (hireg == FAIL) | |
2333 | { | |
2334 | first_error (_(reg_expected_msgs[rtype])); | |
2335 | return FAIL; | |
2336 | } | |
2337 | if (! neon_alias_types_same (&htype, &firsttype)) | |
2338 | { | |
2339 | first_error (_(type_error)); | |
2340 | return FAIL; | |
2341 | } | |
2342 | count += hireg + dregs - getreg; | |
2343 | continue; | |
2344 | } | |
5f4273c7 | 2345 | |
5287ad62 JB |
2346 | /* If we're using Q registers, we can't use [] or [n] syntax. */ |
2347 | if (rtype == REG_TYPE_NQ) | |
477330fc RM |
2348 | { |
2349 | count += 2; | |
2350 | continue; | |
2351 | } | |
5f4273c7 | 2352 | |
dcbf9037 | 2353 | if ((atype.defined & NTA_HASINDEX) != 0) |
477330fc RM |
2354 | { |
2355 | if (lane == -1) | |
2356 | lane = atype.index; | |
2357 | else if (lane != atype.index) | |
2358 | { | |
2359 | first_error (_(type_error)); | |
2360 | return FAIL; | |
2361 | } | |
2362 | } | |
5287ad62 | 2363 | else if (lane == -1) |
477330fc | 2364 | lane = NEON_INTERLEAVE_LANES; |
5287ad62 | 2365 | else if (lane != NEON_INTERLEAVE_LANES) |
477330fc RM |
2366 | { |
2367 | first_error (_(type_error)); | |
2368 | return FAIL; | |
2369 | } | |
5287ad62 JB |
2370 | count++; |
2371 | } | |
2372 | while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); | |
5f4273c7 | 2373 | |
5287ad62 JB |
2374 | /* No lane set by [x]. We must be interleaving structures. */ |
2375 | if (lane == -1) | |
2376 | lane = NEON_INTERLEAVE_LANES; | |
5f4273c7 | 2377 | |
5287ad62 | 2378 | /* Sanity check. */ |
35c228db | 2379 | if (lane == -1 || base_reg == -1 || count < 1 || (!mve && count > 4) |
5287ad62 JB |
2380 | || (count > 1 && reg_incr == -1)) |
2381 | { | |
dcbf9037 | 2382 | first_error (_("error parsing element/structure list")); |
5287ad62 JB |
2383 | return FAIL; |
2384 | } | |
2385 | ||
2386 | if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) | |
2387 | { | |
dcbf9037 | 2388 | first_error (_("expected }")); |
5287ad62 JB |
2389 | return FAIL; |
2390 | } | |
5f4273c7 | 2391 | |
5287ad62 JB |
2392 | if (reg_incr == -1) |
2393 | reg_incr = 1; | |
2394 | ||
dcbf9037 JB |
2395 | if (eltype) |
2396 | *eltype = firsttype.eltype; | |
2397 | ||
5287ad62 JB |
2398 | *pbase = base_reg; |
2399 | *str = ptr; | |
5f4273c7 | 2400 | |
5287ad62 JB |
2401 | return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); |
2402 | } | |
2403 | ||
c19d1205 ZW |
2404 | /* Parse an explicit relocation suffix on an expression. This is |
2405 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
2406 | arm_reloc_hsh contains no entries, so this function can only | |
2407 | succeed if there is no () after the word. Returns -1 on error, | |
2408 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
3da1d841 | 2409 | |
c19d1205 ZW |
2410 | static int |
2411 | parse_reloc (char **str) | |
b99bd4ef | 2412 | { |
c19d1205 ZW |
2413 | struct reloc_entry *r; |
2414 | char *p, *q; | |
b99bd4ef | 2415 | |
c19d1205 ZW |
2416 | if (**str != '(') |
2417 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 2418 | |
c19d1205 ZW |
2419 | p = *str + 1; |
2420 | q = p; | |
2421 | ||
2422 | while (*q && *q != ')' && *q != ',') | |
2423 | q++; | |
2424 | if (*q != ')') | |
2425 | return -1; | |
2426 | ||
21d799b5 NC |
2427 | if ((r = (struct reloc_entry *) |
2428 | hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
c19d1205 ZW |
2429 | return -1; |
2430 | ||
2431 | *str = q + 1; | |
2432 | return r->reloc; | |
b99bd4ef NC |
2433 | } |
2434 | ||
c19d1205 ZW |
2435 | /* Directives: register aliases. */ |
2436 | ||
dcbf9037 | 2437 | static struct reg_entry * |
90ec0d68 | 2438 | insert_reg_alias (char *str, unsigned number, int type) |
b99bd4ef | 2439 | { |
d3ce72d0 | 2440 | struct reg_entry *new_reg; |
c19d1205 | 2441 | const char *name; |
b99bd4ef | 2442 | |
d3ce72d0 | 2443 | if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0) |
c19d1205 | 2444 | { |
d3ce72d0 | 2445 | if (new_reg->builtin) |
c19d1205 | 2446 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); |
b99bd4ef | 2447 | |
c19d1205 ZW |
2448 | /* Only warn about a redefinition if it's not defined as the |
2449 | same register. */ | |
d3ce72d0 | 2450 | else if (new_reg->number != number || new_reg->type != type) |
c19d1205 | 2451 | as_warn (_("ignoring redefinition of register alias '%s'"), str); |
69b97547 | 2452 | |
d929913e | 2453 | return NULL; |
c19d1205 | 2454 | } |
b99bd4ef | 2455 | |
c19d1205 | 2456 | name = xstrdup (str); |
325801bd | 2457 | new_reg = XNEW (struct reg_entry); |
b99bd4ef | 2458 | |
d3ce72d0 NC |
2459 | new_reg->name = name; |
2460 | new_reg->number = number; | |
2461 | new_reg->type = type; | |
2462 | new_reg->builtin = FALSE; | |
2463 | new_reg->neon = NULL; | |
b99bd4ef | 2464 | |
d3ce72d0 | 2465 | if (hash_insert (arm_reg_hsh, name, (void *) new_reg)) |
c19d1205 | 2466 | abort (); |
5f4273c7 | 2467 | |
d3ce72d0 | 2468 | return new_reg; |
dcbf9037 JB |
2469 | } |
2470 | ||
2471 | static void | |
2472 | insert_neon_reg_alias (char *str, int number, int type, | |
477330fc | 2473 | struct neon_typed_alias *atype) |
dcbf9037 JB |
2474 | { |
2475 | struct reg_entry *reg = insert_reg_alias (str, number, type); | |
5f4273c7 | 2476 | |
dcbf9037 JB |
2477 | if (!reg) |
2478 | { | |
2479 | first_error (_("attempt to redefine typed alias")); | |
2480 | return; | |
2481 | } | |
5f4273c7 | 2482 | |
dcbf9037 JB |
2483 | if (atype) |
2484 | { | |
325801bd | 2485 | reg->neon = XNEW (struct neon_typed_alias); |
dcbf9037 JB |
2486 | *reg->neon = *atype; |
2487 | } | |
c19d1205 | 2488 | } |
b99bd4ef | 2489 | |
c19d1205 | 2490 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 2491 | |
c19d1205 | 2492 | new_register_name .req existing_register_name |
b99bd4ef | 2493 | |
c19d1205 | 2494 | If we find one, or if it looks sufficiently like one that we want to |
d929913e | 2495 | handle any error here, return TRUE. Otherwise return FALSE. */ |
b99bd4ef | 2496 | |
d929913e | 2497 | static bfd_boolean |
c19d1205 ZW |
2498 | create_register_alias (char * newname, char *p) |
2499 | { | |
2500 | struct reg_entry *old; | |
2501 | char *oldname, *nbuf; | |
2502 | size_t nlen; | |
b99bd4ef | 2503 | |
c19d1205 ZW |
2504 | /* The input scrubber ensures that whitespace after the mnemonic is |
2505 | collapsed to single spaces. */ | |
2506 | oldname = p; | |
2507 | if (strncmp (oldname, " .req ", 6) != 0) | |
d929913e | 2508 | return FALSE; |
b99bd4ef | 2509 | |
c19d1205 ZW |
2510 | oldname += 6; |
2511 | if (*oldname == '\0') | |
d929913e | 2512 | return FALSE; |
b99bd4ef | 2513 | |
21d799b5 | 2514 | old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname); |
c19d1205 | 2515 | if (!old) |
b99bd4ef | 2516 | { |
c19d1205 | 2517 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
d929913e | 2518 | return TRUE; |
b99bd4ef NC |
2519 | } |
2520 | ||
c19d1205 ZW |
2521 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2522 | the desired alias name, and p points to its end. If not, then | |
2523 | the desired alias name is in the global original_case_string. */ | |
2524 | #ifdef TC_CASE_SENSITIVE | |
2525 | nlen = p - newname; | |
2526 | #else | |
2527 | newname = original_case_string; | |
2528 | nlen = strlen (newname); | |
2529 | #endif | |
b99bd4ef | 2530 | |
29a2809e | 2531 | nbuf = xmemdup0 (newname, nlen); |
b99bd4ef | 2532 | |
c19d1205 ZW |
2533 | /* Create aliases under the new name as stated; an all-lowercase |
2534 | version of the new name; and an all-uppercase version of the new | |
2535 | name. */ | |
d929913e NC |
2536 | if (insert_reg_alias (nbuf, old->number, old->type) != NULL) |
2537 | { | |
2538 | for (p = nbuf; *p; p++) | |
2539 | *p = TOUPPER (*p); | |
c19d1205 | 2540 | |
d929913e NC |
2541 | if (strncmp (nbuf, newname, nlen)) |
2542 | { | |
2543 | /* If this attempt to create an additional alias fails, do not bother | |
2544 | trying to create the all-lower case alias. We will fail and issue | |
2545 | a second, duplicate error message. This situation arises when the | |
2546 | programmer does something like: | |
2547 | foo .req r0 | |
2548 | Foo .req r1 | |
2549 | The second .req creates the "Foo" alias but then fails to create | |
5f4273c7 | 2550 | the artificial FOO alias because it has already been created by the |
d929913e NC |
2551 | first .req. */ |
2552 | if (insert_reg_alias (nbuf, old->number, old->type) == NULL) | |
e1fa0163 NC |
2553 | { |
2554 | free (nbuf); | |
2555 | return TRUE; | |
2556 | } | |
d929913e | 2557 | } |
c19d1205 | 2558 | |
d929913e NC |
2559 | for (p = nbuf; *p; p++) |
2560 | *p = TOLOWER (*p); | |
c19d1205 | 2561 | |
d929913e NC |
2562 | if (strncmp (nbuf, newname, nlen)) |
2563 | insert_reg_alias (nbuf, old->number, old->type); | |
2564 | } | |
c19d1205 | 2565 | |
e1fa0163 | 2566 | free (nbuf); |
d929913e | 2567 | return TRUE; |
b99bd4ef NC |
2568 | } |
2569 | ||
dcbf9037 JB |
2570 | /* Create a Neon typed/indexed register alias using directives, e.g.: |
2571 | X .dn d5.s32[1] | |
2572 | Y .qn 6.s16 | |
2573 | Z .dn d7 | |
2574 | T .dn Z[0] | |
2575 | These typed registers can be used instead of the types specified after the | |
2576 | Neon mnemonic, so long as all operands given have types. Types can also be | |
2577 | specified directly, e.g.: | |
5f4273c7 | 2578 | vadd d0.s32, d1.s32, d2.s32 */ |
dcbf9037 | 2579 | |
c921be7d | 2580 | static bfd_boolean |
dcbf9037 JB |
2581 | create_neon_reg_alias (char *newname, char *p) |
2582 | { | |
2583 | enum arm_reg_type basetype; | |
2584 | struct reg_entry *basereg; | |
2585 | struct reg_entry mybasereg; | |
2586 | struct neon_type ntype; | |
2587 | struct neon_typed_alias typeinfo; | |
12d6b0b7 | 2588 | char *namebuf, *nameend ATTRIBUTE_UNUSED; |
dcbf9037 | 2589 | int namelen; |
5f4273c7 | 2590 | |
dcbf9037 JB |
2591 | typeinfo.defined = 0; |
2592 | typeinfo.eltype.type = NT_invtype; | |
2593 | typeinfo.eltype.size = -1; | |
2594 | typeinfo.index = -1; | |
5f4273c7 | 2595 | |
dcbf9037 | 2596 | nameend = p; |
5f4273c7 | 2597 | |
dcbf9037 JB |
2598 | if (strncmp (p, " .dn ", 5) == 0) |
2599 | basetype = REG_TYPE_VFD; | |
2600 | else if (strncmp (p, " .qn ", 5) == 0) | |
2601 | basetype = REG_TYPE_NQ; | |
2602 | else | |
c921be7d | 2603 | return FALSE; |
5f4273c7 | 2604 | |
dcbf9037 | 2605 | p += 5; |
5f4273c7 | 2606 | |
dcbf9037 | 2607 | if (*p == '\0') |
c921be7d | 2608 | return FALSE; |
5f4273c7 | 2609 | |
dcbf9037 JB |
2610 | basereg = arm_reg_parse_multi (&p); |
2611 | ||
2612 | if (basereg && basereg->type != basetype) | |
2613 | { | |
2614 | as_bad (_("bad type for register")); | |
c921be7d | 2615 | return FALSE; |
dcbf9037 JB |
2616 | } |
2617 | ||
2618 | if (basereg == NULL) | |
2619 | { | |
2620 | expressionS exp; | |
2621 | /* Try parsing as an integer. */ | |
2622 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
2623 | if (exp.X_op != O_constant) | |
477330fc RM |
2624 | { |
2625 | as_bad (_("expression must be constant")); | |
2626 | return FALSE; | |
2627 | } | |
dcbf9037 JB |
2628 | basereg = &mybasereg; |
2629 | basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 | |
477330fc | 2630 | : exp.X_add_number; |
dcbf9037 JB |
2631 | basereg->neon = 0; |
2632 | } | |
2633 | ||
2634 | if (basereg->neon) | |
2635 | typeinfo = *basereg->neon; | |
2636 | ||
2637 | if (parse_neon_type (&ntype, &p) == SUCCESS) | |
2638 | { | |
2639 | /* We got a type. */ | |
2640 | if (typeinfo.defined & NTA_HASTYPE) | |
477330fc RM |
2641 | { |
2642 | as_bad (_("can't redefine the type of a register alias")); | |
2643 | return FALSE; | |
2644 | } | |
5f4273c7 | 2645 | |
dcbf9037 JB |
2646 | typeinfo.defined |= NTA_HASTYPE; |
2647 | if (ntype.elems != 1) | |
477330fc RM |
2648 | { |
2649 | as_bad (_("you must specify a single type only")); | |
2650 | return FALSE; | |
2651 | } | |
dcbf9037 JB |
2652 | typeinfo.eltype = ntype.el[0]; |
2653 | } | |
5f4273c7 | 2654 | |
dcbf9037 JB |
2655 | if (skip_past_char (&p, '[') == SUCCESS) |
2656 | { | |
2657 | expressionS exp; | |
2658 | /* We got a scalar index. */ | |
5f4273c7 | 2659 | |
dcbf9037 | 2660 | if (typeinfo.defined & NTA_HASINDEX) |
477330fc RM |
2661 | { |
2662 | as_bad (_("can't redefine the index of a scalar alias")); | |
2663 | return FALSE; | |
2664 | } | |
5f4273c7 | 2665 | |
dcbf9037 | 2666 | my_get_expression (&exp, &p, GE_NO_PREFIX); |
5f4273c7 | 2667 | |
dcbf9037 | 2668 | if (exp.X_op != O_constant) |
477330fc RM |
2669 | { |
2670 | as_bad (_("scalar index must be constant")); | |
2671 | return FALSE; | |
2672 | } | |
5f4273c7 | 2673 | |
dcbf9037 JB |
2674 | typeinfo.defined |= NTA_HASINDEX; |
2675 | typeinfo.index = exp.X_add_number; | |
5f4273c7 | 2676 | |
dcbf9037 | 2677 | if (skip_past_char (&p, ']') == FAIL) |
477330fc RM |
2678 | { |
2679 | as_bad (_("expecting ]")); | |
2680 | return FALSE; | |
2681 | } | |
dcbf9037 JB |
2682 | } |
2683 | ||
15735687 NS |
2684 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2685 | the desired alias name, and p points to its end. If not, then | |
2686 | the desired alias name is in the global original_case_string. */ | |
2687 | #ifdef TC_CASE_SENSITIVE | |
dcbf9037 | 2688 | namelen = nameend - newname; |
15735687 NS |
2689 | #else |
2690 | newname = original_case_string; | |
2691 | namelen = strlen (newname); | |
2692 | #endif | |
2693 | ||
29a2809e | 2694 | namebuf = xmemdup0 (newname, namelen); |
5f4273c7 | 2695 | |
dcbf9037 | 2696 | insert_neon_reg_alias (namebuf, basereg->number, basetype, |
477330fc | 2697 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2698 | |
dcbf9037 JB |
2699 | /* Insert name in all uppercase. */ |
2700 | for (p = namebuf; *p; p++) | |
2701 | *p = TOUPPER (*p); | |
5f4273c7 | 2702 | |
dcbf9037 JB |
2703 | if (strncmp (namebuf, newname, namelen)) |
2704 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
477330fc | 2705 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2706 | |
dcbf9037 JB |
2707 | /* Insert name in all lowercase. */ |
2708 | for (p = namebuf; *p; p++) | |
2709 | *p = TOLOWER (*p); | |
5f4273c7 | 2710 | |
dcbf9037 JB |
2711 | if (strncmp (namebuf, newname, namelen)) |
2712 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
477330fc | 2713 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2714 | |
e1fa0163 | 2715 | free (namebuf); |
c921be7d | 2716 | return TRUE; |
dcbf9037 JB |
2717 | } |
2718 | ||
c19d1205 ZW |
2719 | /* Should never be called, as .req goes between the alias and the |
2720 | register name, not at the beginning of the line. */ | |
c921be7d | 2721 | |
b99bd4ef | 2722 | static void |
c19d1205 | 2723 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2724 | { |
c19d1205 ZW |
2725 | as_bad (_("invalid syntax for .req directive")); |
2726 | } | |
b99bd4ef | 2727 | |
dcbf9037 JB |
2728 | static void |
2729 | s_dn (int a ATTRIBUTE_UNUSED) | |
2730 | { | |
2731 | as_bad (_("invalid syntax for .dn directive")); | |
2732 | } | |
2733 | ||
2734 | static void | |
2735 | s_qn (int a ATTRIBUTE_UNUSED) | |
2736 | { | |
2737 | as_bad (_("invalid syntax for .qn directive")); | |
2738 | } | |
2739 | ||
c19d1205 ZW |
2740 | /* The .unreq directive deletes an alias which was previously defined |
2741 | by .req. For example: | |
b99bd4ef | 2742 | |
c19d1205 ZW |
2743 | my_alias .req r11 |
2744 | .unreq my_alias */ | |
b99bd4ef NC |
2745 | |
2746 | static void | |
c19d1205 | 2747 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2748 | { |
c19d1205 ZW |
2749 | char * name; |
2750 | char saved_char; | |
b99bd4ef | 2751 | |
c19d1205 ZW |
2752 | name = input_line_pointer; |
2753 | ||
2754 | while (*input_line_pointer != 0 | |
2755 | && *input_line_pointer != ' ' | |
2756 | && *input_line_pointer != '\n') | |
2757 | ++input_line_pointer; | |
2758 | ||
2759 | saved_char = *input_line_pointer; | |
2760 | *input_line_pointer = 0; | |
2761 | ||
2762 | if (!*name) | |
2763 | as_bad (_("invalid syntax for .unreq directive")); | |
2764 | else | |
2765 | { | |
21d799b5 | 2766 | struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh, |
477330fc | 2767 | name); |
c19d1205 ZW |
2768 | |
2769 | if (!reg) | |
2770 | as_bad (_("unknown register alias '%s'"), name); | |
2771 | else if (reg->builtin) | |
a1727c1a | 2772 | as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"), |
c19d1205 ZW |
2773 | name); |
2774 | else | |
2775 | { | |
d929913e NC |
2776 | char * p; |
2777 | char * nbuf; | |
2778 | ||
db0bc284 | 2779 | hash_delete (arm_reg_hsh, name, FALSE); |
c19d1205 | 2780 | free ((char *) reg->name); |
477330fc RM |
2781 | if (reg->neon) |
2782 | free (reg->neon); | |
c19d1205 | 2783 | free (reg); |
d929913e NC |
2784 | |
2785 | /* Also locate the all upper case and all lower case versions. | |
2786 | Do not complain if we cannot find one or the other as it | |
2787 | was probably deleted above. */ | |
5f4273c7 | 2788 | |
d929913e NC |
2789 | nbuf = strdup (name); |
2790 | for (p = nbuf; *p; p++) | |
2791 | *p = TOUPPER (*p); | |
21d799b5 | 2792 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2793 | if (reg) |
2794 | { | |
db0bc284 | 2795 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2796 | free ((char *) reg->name); |
2797 | if (reg->neon) | |
2798 | free (reg->neon); | |
2799 | free (reg); | |
2800 | } | |
2801 | ||
2802 | for (p = nbuf; *p; p++) | |
2803 | *p = TOLOWER (*p); | |
21d799b5 | 2804 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2805 | if (reg) |
2806 | { | |
db0bc284 | 2807 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2808 | free ((char *) reg->name); |
2809 | if (reg->neon) | |
2810 | free (reg->neon); | |
2811 | free (reg); | |
2812 | } | |
2813 | ||
2814 | free (nbuf); | |
c19d1205 ZW |
2815 | } |
2816 | } | |
b99bd4ef | 2817 | |
c19d1205 | 2818 | *input_line_pointer = saved_char; |
b99bd4ef NC |
2819 | demand_empty_rest_of_line (); |
2820 | } | |
2821 | ||
c19d1205 ZW |
2822 | /* Directives: Instruction set selection. */ |
2823 | ||
2824 | #ifdef OBJ_ELF | |
2825 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
2826 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
2827 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
2828 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
2829 | ||
cd000bff DJ |
2830 | /* Create a new mapping symbol for the transition to STATE. */ |
2831 | ||
2832 | static void | |
2833 | make_mapping_symbol (enum mstate state, valueT value, fragS *frag) | |
b99bd4ef | 2834 | { |
a737bd4d | 2835 | symbolS * symbolP; |
c19d1205 ZW |
2836 | const char * symname; |
2837 | int type; | |
b99bd4ef | 2838 | |
c19d1205 | 2839 | switch (state) |
b99bd4ef | 2840 | { |
c19d1205 ZW |
2841 | case MAP_DATA: |
2842 | symname = "$d"; | |
2843 | type = BSF_NO_FLAGS; | |
2844 | break; | |
2845 | case MAP_ARM: | |
2846 | symname = "$a"; | |
2847 | type = BSF_NO_FLAGS; | |
2848 | break; | |
2849 | case MAP_THUMB: | |
2850 | symname = "$t"; | |
2851 | type = BSF_NO_FLAGS; | |
2852 | break; | |
c19d1205 ZW |
2853 | default: |
2854 | abort (); | |
2855 | } | |
2856 | ||
cd000bff | 2857 | symbolP = symbol_new (symname, now_seg, value, frag); |
c19d1205 ZW |
2858 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; |
2859 | ||
2860 | switch (state) | |
2861 | { | |
2862 | case MAP_ARM: | |
2863 | THUMB_SET_FUNC (symbolP, 0); | |
2864 | ARM_SET_THUMB (symbolP, 0); | |
2865 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2866 | break; | |
2867 | ||
2868 | case MAP_THUMB: | |
2869 | THUMB_SET_FUNC (symbolP, 1); | |
2870 | ARM_SET_THUMB (symbolP, 1); | |
2871 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2872 | break; | |
2873 | ||
2874 | case MAP_DATA: | |
2875 | default: | |
cd000bff DJ |
2876 | break; |
2877 | } | |
2878 | ||
2879 | /* Save the mapping symbols for future reference. Also check that | |
2880 | we do not place two mapping symbols at the same offset within a | |
2881 | frag. We'll handle overlap between frags in | |
2de7820f JZ |
2882 | check_mapping_symbols. |
2883 | ||
2884 | If .fill or other data filling directive generates zero sized data, | |
2885 | the mapping symbol for the following code will have the same value | |
2886 | as the one generated for the data filling directive. In this case, | |
2887 | we replace the old symbol with the new one at the same address. */ | |
cd000bff DJ |
2888 | if (value == 0) |
2889 | { | |
2de7820f JZ |
2890 | if (frag->tc_frag_data.first_map != NULL) |
2891 | { | |
2892 | know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0); | |
2893 | symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP); | |
2894 | } | |
cd000bff DJ |
2895 | frag->tc_frag_data.first_map = symbolP; |
2896 | } | |
2897 | if (frag->tc_frag_data.last_map != NULL) | |
0f020cef JZ |
2898 | { |
2899 | know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP)); | |
0f020cef JZ |
2900 | if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP)) |
2901 | symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP); | |
2902 | } | |
cd000bff DJ |
2903 | frag->tc_frag_data.last_map = symbolP; |
2904 | } | |
2905 | ||
2906 | /* We must sometimes convert a region marked as code to data during | |
2907 | code alignment, if an odd number of bytes have to be padded. The | |
2908 | code mapping symbol is pushed to an aligned address. */ | |
2909 | ||
2910 | static void | |
2911 | insert_data_mapping_symbol (enum mstate state, | |
2912 | valueT value, fragS *frag, offsetT bytes) | |
2913 | { | |
2914 | /* If there was already a mapping symbol, remove it. */ | |
2915 | if (frag->tc_frag_data.last_map != NULL | |
2916 | && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value) | |
2917 | { | |
2918 | symbolS *symp = frag->tc_frag_data.last_map; | |
2919 | ||
2920 | if (value == 0) | |
2921 | { | |
2922 | know (frag->tc_frag_data.first_map == symp); | |
2923 | frag->tc_frag_data.first_map = NULL; | |
2924 | } | |
2925 | frag->tc_frag_data.last_map = NULL; | |
2926 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
c19d1205 | 2927 | } |
cd000bff DJ |
2928 | |
2929 | make_mapping_symbol (MAP_DATA, value, frag); | |
2930 | make_mapping_symbol (state, value + bytes, frag); | |
2931 | } | |
2932 | ||
2933 | static void mapping_state_2 (enum mstate state, int max_chars); | |
2934 | ||
2935 | /* Set the mapping state to STATE. Only call this when about to | |
2936 | emit some STATE bytes to the file. */ | |
2937 | ||
4e9aaefb | 2938 | #define TRANSITION(from, to) (mapstate == (from) && state == (to)) |
cd000bff DJ |
2939 | void |
2940 | mapping_state (enum mstate state) | |
2941 | { | |
940b5ce0 DJ |
2942 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2943 | ||
cd000bff DJ |
2944 | if (mapstate == state) |
2945 | /* The mapping symbol has already been emitted. | |
2946 | There is nothing else to do. */ | |
2947 | return; | |
49c62a33 NC |
2948 | |
2949 | if (state == MAP_ARM || state == MAP_THUMB) | |
2950 | /* PR gas/12931 | |
2951 | All ARM instructions require 4-byte alignment. | |
2952 | (Almost) all Thumb instructions require 2-byte alignment. | |
2953 | ||
2954 | When emitting instructions into any section, mark the section | |
2955 | appropriately. | |
2956 | ||
2957 | Some Thumb instructions are alignment-sensitive modulo 4 bytes, | |
2958 | but themselves require 2-byte alignment; this applies to some | |
33eaf5de | 2959 | PC- relative forms. However, these cases will involve implicit |
49c62a33 NC |
2960 | literal pool generation or an explicit .align >=2, both of |
2961 | which will cause the section to me marked with sufficient | |
2962 | alignment. Thus, we don't handle those cases here. */ | |
2963 | record_alignment (now_seg, state == MAP_ARM ? 2 : 1); | |
2964 | ||
2965 | if (TRANSITION (MAP_UNDEFINED, MAP_DATA)) | |
4e9aaefb | 2966 | /* This case will be evaluated later. */ |
cd000bff | 2967 | return; |
cd000bff DJ |
2968 | |
2969 | mapping_state_2 (state, 0); | |
cd000bff DJ |
2970 | } |
2971 | ||
2972 | /* Same as mapping_state, but MAX_CHARS bytes have already been | |
2973 | allocated. Put the mapping symbol that far back. */ | |
2974 | ||
2975 | static void | |
2976 | mapping_state_2 (enum mstate state, int max_chars) | |
2977 | { | |
940b5ce0 DJ |
2978 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2979 | ||
2980 | if (!SEG_NORMAL (now_seg)) | |
2981 | return; | |
2982 | ||
cd000bff DJ |
2983 | if (mapstate == state) |
2984 | /* The mapping symbol has already been emitted. | |
2985 | There is nothing else to do. */ | |
2986 | return; | |
2987 | ||
4e9aaefb SA |
2988 | if (TRANSITION (MAP_UNDEFINED, MAP_ARM) |
2989 | || TRANSITION (MAP_UNDEFINED, MAP_THUMB)) | |
2990 | { | |
2991 | struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root; | |
2992 | const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0); | |
2993 | ||
2994 | if (add_symbol) | |
2995 | make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); | |
2996 | } | |
2997 | ||
cd000bff DJ |
2998 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; |
2999 | make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); | |
c19d1205 | 3000 | } |
4e9aaefb | 3001 | #undef TRANSITION |
c19d1205 | 3002 | #else |
d3106081 NS |
3003 | #define mapping_state(x) ((void)0) |
3004 | #define mapping_state_2(x, y) ((void)0) | |
c19d1205 ZW |
3005 | #endif |
3006 | ||
3007 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
3008 | ||
4343666d | 3009 | #ifdef OBJ_COFF |
c19d1205 ZW |
3010 | static symbolS * |
3011 | find_real_start (symbolS * symbolP) | |
3012 | { | |
3013 | char * real_start; | |
3014 | const char * name = S_GET_NAME (symbolP); | |
3015 | symbolS * new_target; | |
3016 | ||
3017 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
3018 | #define STUB_NAME ".real_start_of" | |
3019 | ||
3020 | if (name == NULL) | |
3021 | abort (); | |
3022 | ||
37f6032b ZW |
3023 | /* The compiler may generate BL instructions to local labels because |
3024 | it needs to perform a branch to a far away location. These labels | |
3025 | do not have a corresponding ".real_start_of" label. We check | |
3026 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
3027 | the ".real_start_of" convention for nonlocal branches. */ | |
3028 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
3029 | return symbolP; |
3030 | ||
e1fa0163 | 3031 | real_start = concat (STUB_NAME, name, NULL); |
c19d1205 | 3032 | new_target = symbol_find (real_start); |
e1fa0163 | 3033 | free (real_start); |
c19d1205 ZW |
3034 | |
3035 | if (new_target == NULL) | |
3036 | { | |
bd3ba5d1 | 3037 | as_warn (_("Failed to find real start of function: %s\n"), name); |
c19d1205 ZW |
3038 | new_target = symbolP; |
3039 | } | |
3040 | ||
c19d1205 ZW |
3041 | return new_target; |
3042 | } | |
4343666d | 3043 | #endif |
c19d1205 ZW |
3044 | |
3045 | static void | |
3046 | opcode_select (int width) | |
3047 | { | |
3048 | switch (width) | |
3049 | { | |
3050 | case 16: | |
3051 | if (! thumb_mode) | |
3052 | { | |
e74cfd16 | 3053 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
c19d1205 ZW |
3054 | as_bad (_("selected processor does not support THUMB opcodes")); |
3055 | ||
3056 | thumb_mode = 1; | |
3057 | /* No need to force the alignment, since we will have been | |
3058 | coming from ARM mode, which is word-aligned. */ | |
3059 | record_alignment (now_seg, 1); | |
3060 | } | |
c19d1205 ZW |
3061 | break; |
3062 | ||
3063 | case 32: | |
3064 | if (thumb_mode) | |
3065 | { | |
e74cfd16 | 3066 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 ZW |
3067 | as_bad (_("selected processor does not support ARM opcodes")); |
3068 | ||
3069 | thumb_mode = 0; | |
3070 | ||
3071 | if (!need_pass_2) | |
3072 | frag_align (2, 0, 0); | |
3073 | ||
3074 | record_alignment (now_seg, 1); | |
3075 | } | |
c19d1205 ZW |
3076 | break; |
3077 | ||
3078 | default: | |
3079 | as_bad (_("invalid instruction size selected (%d)"), width); | |
3080 | } | |
3081 | } | |
3082 | ||
3083 | static void | |
3084 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
3085 | { | |
3086 | opcode_select (32); | |
3087 | demand_empty_rest_of_line (); | |
3088 | } | |
3089 | ||
3090 | static void | |
3091 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
3092 | { | |
3093 | opcode_select (16); | |
3094 | demand_empty_rest_of_line (); | |
3095 | } | |
3096 | ||
3097 | static void | |
3098 | s_code (int unused ATTRIBUTE_UNUSED) | |
3099 | { | |
3100 | int temp; | |
3101 | ||
3102 | temp = get_absolute_expression (); | |
3103 | switch (temp) | |
3104 | { | |
3105 | case 16: | |
3106 | case 32: | |
3107 | opcode_select (temp); | |
3108 | break; | |
3109 | ||
3110 | default: | |
3111 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
3112 | } | |
3113 | } | |
3114 | ||
3115 | static void | |
3116 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
3117 | { | |
3118 | /* If we are not already in thumb mode go into it, EVEN if | |
3119 | the target processor does not support thumb instructions. | |
3120 | This is used by gcc/config/arm/lib1funcs.asm for example | |
3121 | to compile interworking support functions even if the | |
3122 | target processor should not support interworking. */ | |
3123 | if (! thumb_mode) | |
3124 | { | |
3125 | thumb_mode = 2; | |
3126 | record_alignment (now_seg, 1); | |
3127 | } | |
3128 | ||
3129 | demand_empty_rest_of_line (); | |
3130 | } | |
3131 | ||
3132 | static void | |
3133 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
3134 | { | |
3135 | s_thumb (0); | |
3136 | ||
3137 | /* The following label is the name/address of the start of a Thumb function. | |
3138 | We need to know this for the interworking support. */ | |
3139 | label_is_thumb_function_name = TRUE; | |
3140 | } | |
3141 | ||
3142 | /* Perform a .set directive, but also mark the alias as | |
3143 | being a thumb function. */ | |
3144 | ||
3145 | static void | |
3146 | s_thumb_set (int equiv) | |
3147 | { | |
3148 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
3149 | We cannot just call that code as we need to get at the symbol that | |
3150 | is created. */ | |
3151 | char * name; | |
3152 | char delim; | |
3153 | char * end_name; | |
3154 | symbolS * symbolP; | |
3155 | ||
3156 | /* Especial apologies for the random logic: | |
3157 | This just grew, and could be parsed much more simply! | |
3158 | Dean - in haste. */ | |
d02603dc | 3159 | delim = get_symbol_name (& name); |
c19d1205 | 3160 | end_name = input_line_pointer; |
d02603dc | 3161 | (void) restore_line_pointer (delim); |
c19d1205 ZW |
3162 | |
3163 | if (*input_line_pointer != ',') | |
3164 | { | |
3165 | *end_name = 0; | |
3166 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
3167 | *end_name = delim; |
3168 | ignore_rest_of_line (); | |
3169 | return; | |
3170 | } | |
3171 | ||
3172 | input_line_pointer++; | |
3173 | *end_name = 0; | |
3174 | ||
3175 | if (name[0] == '.' && name[1] == '\0') | |
3176 | { | |
3177 | /* XXX - this should not happen to .thumb_set. */ | |
3178 | abort (); | |
3179 | } | |
3180 | ||
3181 | if ((symbolP = symbol_find (name)) == NULL | |
3182 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
3183 | { | |
3184 | #ifndef NO_LISTING | |
3185 | /* When doing symbol listings, play games with dummy fragments living | |
3186 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 3187 | for this symbol. */ |
b99bd4ef NC |
3188 | if (listing & LISTING_SYMBOLS) |
3189 | { | |
3190 | extern struct list_info_struct * listing_tail; | |
21d799b5 | 3191 | fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS)); |
b99bd4ef NC |
3192 | |
3193 | memset (dummy_frag, 0, sizeof (fragS)); | |
3194 | dummy_frag->fr_type = rs_fill; | |
3195 | dummy_frag->line = listing_tail; | |
3196 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
3197 | dummy_frag->fr_symbol = symbolP; | |
3198 | } | |
3199 | else | |
3200 | #endif | |
3201 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
3202 | ||
3203 | #ifdef OBJ_COFF | |
3204 | /* "set" symbols are local unless otherwise specified. */ | |
3205 | SF_SET_LOCAL (symbolP); | |
3206 | #endif /* OBJ_COFF */ | |
3207 | } /* Make a new symbol. */ | |
3208 | ||
3209 | symbol_table_insert (symbolP); | |
3210 | ||
3211 | * end_name = delim; | |
3212 | ||
3213 | if (equiv | |
3214 | && S_IS_DEFINED (symbolP) | |
3215 | && S_GET_SEGMENT (symbolP) != reg_section) | |
3216 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
3217 | ||
3218 | pseudo_set (symbolP); | |
3219 | ||
3220 | demand_empty_rest_of_line (); | |
3221 | ||
c19d1205 | 3222 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
3223 | |
3224 | THUMB_SET_FUNC (symbolP, 1); | |
3225 | ARM_SET_THUMB (symbolP, 1); | |
3226 | #if defined OBJ_ELF || defined OBJ_COFF | |
3227 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
3228 | #endif | |
3229 | } | |
3230 | ||
c19d1205 | 3231 | /* Directives: Mode selection. */ |
b99bd4ef | 3232 | |
c19d1205 ZW |
3233 | /* .syntax [unified|divided] - choose the new unified syntax |
3234 | (same for Arm and Thumb encoding, modulo slight differences in what | |
3235 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 3236 | static void |
c19d1205 | 3237 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 3238 | { |
c19d1205 ZW |
3239 | char *name, delim; |
3240 | ||
d02603dc | 3241 | delim = get_symbol_name (& name); |
c19d1205 ZW |
3242 | |
3243 | if (!strcasecmp (name, "unified")) | |
3244 | unified_syntax = TRUE; | |
3245 | else if (!strcasecmp (name, "divided")) | |
3246 | unified_syntax = FALSE; | |
3247 | else | |
3248 | { | |
3249 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
3250 | return; | |
3251 | } | |
d02603dc | 3252 | (void) restore_line_pointer (delim); |
b99bd4ef NC |
3253 | demand_empty_rest_of_line (); |
3254 | } | |
3255 | ||
c19d1205 ZW |
3256 | /* Directives: sectioning and alignment. */ |
3257 | ||
c19d1205 ZW |
3258 | static void |
3259 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 3260 | { |
c19d1205 ZW |
3261 | /* We don't support putting frags in the BSS segment, we fake it by |
3262 | marking in_bss, then looking at s_skip for clues. */ | |
3263 | subseg_set (bss_section, 0); | |
3264 | demand_empty_rest_of_line (); | |
cd000bff DJ |
3265 | |
3266 | #ifdef md_elf_section_change_hook | |
3267 | md_elf_section_change_hook (); | |
3268 | #endif | |
c19d1205 | 3269 | } |
b99bd4ef | 3270 | |
c19d1205 ZW |
3271 | static void |
3272 | s_even (int ignore ATTRIBUTE_UNUSED) | |
3273 | { | |
3274 | /* Never make frag if expect extra pass. */ | |
3275 | if (!need_pass_2) | |
3276 | frag_align (1, 0, 0); | |
b99bd4ef | 3277 | |
c19d1205 | 3278 | record_alignment (now_seg, 1); |
b99bd4ef | 3279 | |
c19d1205 | 3280 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3281 | } |
3282 | ||
2e6976a8 DG |
3283 | /* Directives: CodeComposer Studio. */ |
3284 | ||
3285 | /* .ref (for CodeComposer Studio syntax only). */ | |
3286 | static void | |
3287 | s_ccs_ref (int unused ATTRIBUTE_UNUSED) | |
3288 | { | |
3289 | if (codecomposer_syntax) | |
3290 | ignore_rest_of_line (); | |
3291 | else | |
3292 | as_bad (_(".ref pseudo-op only available with -mccs flag.")); | |
3293 | } | |
3294 | ||
3295 | /* If name is not NULL, then it is used for marking the beginning of a | |
2b0f3761 | 3296 | function, whereas if it is NULL then it means the function end. */ |
2e6976a8 DG |
3297 | static void |
3298 | asmfunc_debug (const char * name) | |
3299 | { | |
3300 | static const char * last_name = NULL; | |
3301 | ||
3302 | if (name != NULL) | |
3303 | { | |
3304 | gas_assert (last_name == NULL); | |
3305 | last_name = name; | |
3306 | ||
3307 | if (debug_type == DEBUG_STABS) | |
3308 | stabs_generate_asm_func (name, name); | |
3309 | } | |
3310 | else | |
3311 | { | |
3312 | gas_assert (last_name != NULL); | |
3313 | ||
3314 | if (debug_type == DEBUG_STABS) | |
3315 | stabs_generate_asm_endfunc (last_name, last_name); | |
3316 | ||
3317 | last_name = NULL; | |
3318 | } | |
3319 | } | |
3320 | ||
3321 | static void | |
3322 | s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED) | |
3323 | { | |
3324 | if (codecomposer_syntax) | |
3325 | { | |
3326 | switch (asmfunc_state) | |
3327 | { | |
3328 | case OUTSIDE_ASMFUNC: | |
3329 | asmfunc_state = WAITING_ASMFUNC_NAME; | |
3330 | break; | |
3331 | ||
3332 | case WAITING_ASMFUNC_NAME: | |
3333 | as_bad (_(".asmfunc repeated.")); | |
3334 | break; | |
3335 | ||
3336 | case WAITING_ENDASMFUNC: | |
3337 | as_bad (_(".asmfunc without function.")); | |
3338 | break; | |
3339 | } | |
3340 | demand_empty_rest_of_line (); | |
3341 | } | |
3342 | else | |
3343 | as_bad (_(".asmfunc pseudo-op only available with -mccs flag.")); | |
3344 | } | |
3345 | ||
3346 | static void | |
3347 | s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED) | |
3348 | { | |
3349 | if (codecomposer_syntax) | |
3350 | { | |
3351 | switch (asmfunc_state) | |
3352 | { | |
3353 | case OUTSIDE_ASMFUNC: | |
3354 | as_bad (_(".endasmfunc without a .asmfunc.")); | |
3355 | break; | |
3356 | ||
3357 | case WAITING_ASMFUNC_NAME: | |
3358 | as_bad (_(".endasmfunc without function.")); | |
3359 | break; | |
3360 | ||
3361 | case WAITING_ENDASMFUNC: | |
3362 | asmfunc_state = OUTSIDE_ASMFUNC; | |
3363 | asmfunc_debug (NULL); | |
3364 | break; | |
3365 | } | |
3366 | demand_empty_rest_of_line (); | |
3367 | } | |
3368 | else | |
3369 | as_bad (_(".endasmfunc pseudo-op only available with -mccs flag.")); | |
3370 | } | |
3371 | ||
3372 | static void | |
3373 | s_ccs_def (int name) | |
3374 | { | |
3375 | if (codecomposer_syntax) | |
3376 | s_globl (name); | |
3377 | else | |
3378 | as_bad (_(".def pseudo-op only available with -mccs flag.")); | |
3379 | } | |
3380 | ||
c19d1205 | 3381 | /* Directives: Literal pools. */ |
a737bd4d | 3382 | |
c19d1205 ZW |
3383 | static literal_pool * |
3384 | find_literal_pool (void) | |
a737bd4d | 3385 | { |
c19d1205 | 3386 | literal_pool * pool; |
a737bd4d | 3387 | |
c19d1205 | 3388 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 3389 | { |
c19d1205 ZW |
3390 | if (pool->section == now_seg |
3391 | && pool->sub_section == now_subseg) | |
3392 | break; | |
a737bd4d NC |
3393 | } |
3394 | ||
c19d1205 | 3395 | return pool; |
a737bd4d NC |
3396 | } |
3397 | ||
c19d1205 ZW |
3398 | static literal_pool * |
3399 | find_or_make_literal_pool (void) | |
a737bd4d | 3400 | { |
c19d1205 ZW |
3401 | /* Next literal pool ID number. */ |
3402 | static unsigned int latest_pool_num = 1; | |
3403 | literal_pool * pool; | |
a737bd4d | 3404 | |
c19d1205 | 3405 | pool = find_literal_pool (); |
a737bd4d | 3406 | |
c19d1205 | 3407 | if (pool == NULL) |
a737bd4d | 3408 | { |
c19d1205 | 3409 | /* Create a new pool. */ |
325801bd | 3410 | pool = XNEW (literal_pool); |
c19d1205 ZW |
3411 | if (! pool) |
3412 | return NULL; | |
a737bd4d | 3413 | |
c19d1205 ZW |
3414 | pool->next_free_entry = 0; |
3415 | pool->section = now_seg; | |
3416 | pool->sub_section = now_subseg; | |
3417 | pool->next = list_of_pools; | |
3418 | pool->symbol = NULL; | |
8335d6aa | 3419 | pool->alignment = 2; |
c19d1205 ZW |
3420 | |
3421 | /* Add it to the list. */ | |
3422 | list_of_pools = pool; | |
a737bd4d | 3423 | } |
a737bd4d | 3424 | |
c19d1205 ZW |
3425 | /* New pools, and emptied pools, will have a NULL symbol. */ |
3426 | if (pool->symbol == NULL) | |
a737bd4d | 3427 | { |
c19d1205 ZW |
3428 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
3429 | (valueT) 0, &zero_address_frag); | |
3430 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
3431 | } |
3432 | ||
c19d1205 ZW |
3433 | /* Done. */ |
3434 | return pool; | |
a737bd4d NC |
3435 | } |
3436 | ||
c19d1205 | 3437 | /* Add the literal in the global 'inst' |
5f4273c7 | 3438 | structure to the relevant literal pool. */ |
b99bd4ef NC |
3439 | |
3440 | static int | |
8335d6aa | 3441 | add_to_lit_pool (unsigned int nbytes) |
b99bd4ef | 3442 | { |
8335d6aa JW |
3443 | #define PADDING_SLOT 0x1 |
3444 | #define LIT_ENTRY_SIZE_MASK 0xFF | |
c19d1205 | 3445 | literal_pool * pool; |
8335d6aa JW |
3446 | unsigned int entry, pool_size = 0; |
3447 | bfd_boolean padding_slot_p = FALSE; | |
e56c722b | 3448 | unsigned imm1 = 0; |
8335d6aa JW |
3449 | unsigned imm2 = 0; |
3450 | ||
3451 | if (nbytes == 8) | |
3452 | { | |
3453 | imm1 = inst.operands[1].imm; | |
3454 | imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg | |
e2b0ab59 | 3455 | : inst.relocs[0].exp.X_unsigned ? 0 |
2569ceb0 | 3456 | : ((bfd_int64_t) inst.operands[1].imm) >> 32); |
8335d6aa JW |
3457 | if (target_big_endian) |
3458 | { | |
3459 | imm1 = imm2; | |
3460 | imm2 = inst.operands[1].imm; | |
3461 | } | |
3462 | } | |
b99bd4ef | 3463 | |
c19d1205 ZW |
3464 | pool = find_or_make_literal_pool (); |
3465 | ||
3466 | /* Check if this literal value is already in the pool. */ | |
3467 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 3468 | { |
8335d6aa JW |
3469 | if (nbytes == 4) |
3470 | { | |
e2b0ab59 AV |
3471 | if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op) |
3472 | && (inst.relocs[0].exp.X_op == O_constant) | |
8335d6aa | 3473 | && (pool->literals[entry].X_add_number |
e2b0ab59 | 3474 | == inst.relocs[0].exp.X_add_number) |
8335d6aa JW |
3475 | && (pool->literals[entry].X_md == nbytes) |
3476 | && (pool->literals[entry].X_unsigned | |
e2b0ab59 | 3477 | == inst.relocs[0].exp.X_unsigned)) |
8335d6aa JW |
3478 | break; |
3479 | ||
e2b0ab59 AV |
3480 | if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op) |
3481 | && (inst.relocs[0].exp.X_op == O_symbol) | |
8335d6aa | 3482 | && (pool->literals[entry].X_add_number |
e2b0ab59 | 3483 | == inst.relocs[0].exp.X_add_number) |
8335d6aa | 3484 | && (pool->literals[entry].X_add_symbol |
e2b0ab59 | 3485 | == inst.relocs[0].exp.X_add_symbol) |
8335d6aa | 3486 | && (pool->literals[entry].X_op_symbol |
e2b0ab59 | 3487 | == inst.relocs[0].exp.X_op_symbol) |
8335d6aa JW |
3488 | && (pool->literals[entry].X_md == nbytes)) |
3489 | break; | |
3490 | } | |
3491 | else if ((nbytes == 8) | |
3492 | && !(pool_size & 0x7) | |
3493 | && ((entry + 1) != pool->next_free_entry) | |
3494 | && (pool->literals[entry].X_op == O_constant) | |
19f2f6a9 | 3495 | && (pool->literals[entry].X_add_number == (offsetT) imm1) |
8335d6aa | 3496 | && (pool->literals[entry].X_unsigned |
e2b0ab59 | 3497 | == inst.relocs[0].exp.X_unsigned) |
8335d6aa | 3498 | && (pool->literals[entry + 1].X_op == O_constant) |
19f2f6a9 | 3499 | && (pool->literals[entry + 1].X_add_number == (offsetT) imm2) |
8335d6aa | 3500 | && (pool->literals[entry + 1].X_unsigned |
e2b0ab59 | 3501 | == inst.relocs[0].exp.X_unsigned)) |
c19d1205 ZW |
3502 | break; |
3503 | ||
8335d6aa JW |
3504 | padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT); |
3505 | if (padding_slot_p && (nbytes == 4)) | |
c19d1205 | 3506 | break; |
8335d6aa JW |
3507 | |
3508 | pool_size += 4; | |
b99bd4ef NC |
3509 | } |
3510 | ||
c19d1205 ZW |
3511 | /* Do we need to create a new entry? */ |
3512 | if (entry == pool->next_free_entry) | |
3513 | { | |
3514 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
3515 | { | |
3516 | inst.error = _("literal pool overflow"); | |
3517 | return FAIL; | |
3518 | } | |
3519 | ||
8335d6aa JW |
3520 | if (nbytes == 8) |
3521 | { | |
3522 | /* For 8-byte entries, we align to an 8-byte boundary, | |
3523 | and split it into two 4-byte entries, because on 32-bit | |
3524 | host, 8-byte constants are treated as big num, thus | |
3525 | saved in "generic_bignum" which will be overwritten | |
3526 | by later assignments. | |
3527 | ||
3528 | We also need to make sure there is enough space for | |
3529 | the split. | |
3530 | ||
3531 | We also check to make sure the literal operand is a | |
3532 | constant number. */ | |
e2b0ab59 AV |
3533 | if (!(inst.relocs[0].exp.X_op == O_constant |
3534 | || inst.relocs[0].exp.X_op == O_big)) | |
8335d6aa JW |
3535 | { |
3536 | inst.error = _("invalid type for literal pool"); | |
3537 | return FAIL; | |
3538 | } | |
3539 | else if (pool_size & 0x7) | |
3540 | { | |
3541 | if ((entry + 2) >= MAX_LITERAL_POOL_SIZE) | |
3542 | { | |
3543 | inst.error = _("literal pool overflow"); | |
3544 | return FAIL; | |
3545 | } | |
3546 | ||
e2b0ab59 | 3547 | pool->literals[entry] = inst.relocs[0].exp; |
a6684f0d | 3548 | pool->literals[entry].X_op = O_constant; |
8335d6aa JW |
3549 | pool->literals[entry].X_add_number = 0; |
3550 | pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4; | |
3551 | pool->next_free_entry += 1; | |
3552 | pool_size += 4; | |
3553 | } | |
3554 | else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE) | |
3555 | { | |
3556 | inst.error = _("literal pool overflow"); | |
3557 | return FAIL; | |
3558 | } | |
3559 | ||
e2b0ab59 | 3560 | pool->literals[entry] = inst.relocs[0].exp; |
8335d6aa JW |
3561 | pool->literals[entry].X_op = O_constant; |
3562 | pool->literals[entry].X_add_number = imm1; | |
e2b0ab59 | 3563 | pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned; |
8335d6aa | 3564 | pool->literals[entry++].X_md = 4; |
e2b0ab59 | 3565 | pool->literals[entry] = inst.relocs[0].exp; |
8335d6aa JW |
3566 | pool->literals[entry].X_op = O_constant; |
3567 | pool->literals[entry].X_add_number = imm2; | |
e2b0ab59 | 3568 | pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned; |
8335d6aa JW |
3569 | pool->literals[entry].X_md = 4; |
3570 | pool->alignment = 3; | |
3571 | pool->next_free_entry += 1; | |
3572 | } | |
3573 | else | |
3574 | { | |
e2b0ab59 | 3575 | pool->literals[entry] = inst.relocs[0].exp; |
8335d6aa JW |
3576 | pool->literals[entry].X_md = 4; |
3577 | } | |
3578 | ||
a8040cf2 NC |
3579 | #ifdef OBJ_ELF |
3580 | /* PR ld/12974: Record the location of the first source line to reference | |
3581 | this entry in the literal pool. If it turns out during linking that the | |
3582 | symbol does not exist we will be able to give an accurate line number for | |
3583 | the (first use of the) missing reference. */ | |
3584 | if (debug_type == DEBUG_DWARF2) | |
3585 | dwarf2_where (pool->locs + entry); | |
3586 | #endif | |
c19d1205 ZW |
3587 | pool->next_free_entry += 1; |
3588 | } | |
8335d6aa JW |
3589 | else if (padding_slot_p) |
3590 | { | |
e2b0ab59 | 3591 | pool->literals[entry] = inst.relocs[0].exp; |
8335d6aa JW |
3592 | pool->literals[entry].X_md = nbytes; |
3593 | } | |
b99bd4ef | 3594 | |
e2b0ab59 AV |
3595 | inst.relocs[0].exp.X_op = O_symbol; |
3596 | inst.relocs[0].exp.X_add_number = pool_size; | |
3597 | inst.relocs[0].exp.X_add_symbol = pool->symbol; | |
b99bd4ef | 3598 | |
c19d1205 | 3599 | return SUCCESS; |
b99bd4ef NC |
3600 | } |
3601 | ||
2e6976a8 | 3602 | bfd_boolean |
2e57ce7b | 3603 | tc_start_label_without_colon (void) |
2e6976a8 DG |
3604 | { |
3605 | bfd_boolean ret = TRUE; | |
3606 | ||
3607 | if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME) | |
3608 | { | |
2e57ce7b | 3609 | const char *label = input_line_pointer; |
2e6976a8 DG |
3610 | |
3611 | while (!is_end_of_line[(int) label[-1]]) | |
3612 | --label; | |
3613 | ||
3614 | if (*label == '.') | |
3615 | { | |
3616 | as_bad (_("Invalid label '%s'"), label); | |
3617 | ret = FALSE; | |
3618 | } | |
3619 | ||
3620 | asmfunc_debug (label); | |
3621 | ||
3622 | asmfunc_state = WAITING_ENDASMFUNC; | |
3623 | } | |
3624 | ||
3625 | return ret; | |
3626 | } | |
3627 | ||
c19d1205 | 3628 | /* Can't use symbol_new here, so have to create a symbol and then at |
33eaf5de | 3629 | a later date assign it a value. That's what these functions do. */ |
e16bb312 | 3630 | |
c19d1205 ZW |
3631 | static void |
3632 | symbol_locate (symbolS * symbolP, | |
3633 | const char * name, /* It is copied, the caller can modify. */ | |
3634 | segT segment, /* Segment identifier (SEG_<something>). */ | |
3635 | valueT valu, /* Symbol value. */ | |
3636 | fragS * frag) /* Associated fragment. */ | |
3637 | { | |
e57e6ddc | 3638 | size_t name_length; |
c19d1205 | 3639 | char * preserved_copy_of_name; |
e16bb312 | 3640 | |
c19d1205 ZW |
3641 | name_length = strlen (name) + 1; /* +1 for \0. */ |
3642 | obstack_grow (¬es, name, name_length); | |
21d799b5 | 3643 | preserved_copy_of_name = (char *) obstack_finish (¬es); |
e16bb312 | 3644 | |
c19d1205 ZW |
3645 | #ifdef tc_canonicalize_symbol_name |
3646 | preserved_copy_of_name = | |
3647 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
3648 | #endif | |
b99bd4ef | 3649 | |
c19d1205 | 3650 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 3651 | |
c19d1205 ZW |
3652 | S_SET_SEGMENT (symbolP, segment); |
3653 | S_SET_VALUE (symbolP, valu); | |
3654 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 3655 | |
c19d1205 | 3656 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 3657 | |
c19d1205 ZW |
3658 | /* Link to end of symbol chain. */ |
3659 | { | |
3660 | extern int symbol_table_frozen; | |
b99bd4ef | 3661 | |
c19d1205 ZW |
3662 | if (symbol_table_frozen) |
3663 | abort (); | |
3664 | } | |
b99bd4ef | 3665 | |
c19d1205 | 3666 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 3667 | |
c19d1205 | 3668 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 3669 | |
c19d1205 ZW |
3670 | #ifdef tc_symbol_new_hook |
3671 | tc_symbol_new_hook (symbolP); | |
3672 | #endif | |
3673 | ||
3674 | #ifdef DEBUG_SYMS | |
3675 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
3676 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
3677 | } |
3678 | ||
c19d1205 ZW |
3679 | static void |
3680 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 3681 | { |
c19d1205 ZW |
3682 | unsigned int entry; |
3683 | literal_pool * pool; | |
3684 | char sym_name[20]; | |
b99bd4ef | 3685 | |
c19d1205 ZW |
3686 | pool = find_literal_pool (); |
3687 | if (pool == NULL | |
3688 | || pool->symbol == NULL | |
3689 | || pool->next_free_entry == 0) | |
3690 | return; | |
b99bd4ef | 3691 | |
c19d1205 ZW |
3692 | /* Align pool as you have word accesses. |
3693 | Only make a frag if we have to. */ | |
3694 | if (!need_pass_2) | |
8335d6aa | 3695 | frag_align (pool->alignment, 0, 0); |
b99bd4ef | 3696 | |
c19d1205 | 3697 | record_alignment (now_seg, 2); |
b99bd4ef | 3698 | |
aaca88ef | 3699 | #ifdef OBJ_ELF |
47fc6e36 WN |
3700 | seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA; |
3701 | make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now); | |
aaca88ef | 3702 | #endif |
c19d1205 | 3703 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 3704 | |
c19d1205 ZW |
3705 | symbol_locate (pool->symbol, sym_name, now_seg, |
3706 | (valueT) frag_now_fix (), frag_now); | |
3707 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 3708 | |
c19d1205 | 3709 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 3710 | |
c19d1205 ZW |
3711 | #if defined OBJ_COFF || defined OBJ_ELF |
3712 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
3713 | #endif | |
6c43fab6 | 3714 | |
c19d1205 | 3715 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
a8040cf2 NC |
3716 | { |
3717 | #ifdef OBJ_ELF | |
3718 | if (debug_type == DEBUG_DWARF2) | |
3719 | dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry); | |
3720 | #endif | |
3721 | /* First output the expression in the instruction to the pool. */ | |
8335d6aa JW |
3722 | emit_expr (&(pool->literals[entry]), |
3723 | pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK); | |
a8040cf2 | 3724 | } |
b99bd4ef | 3725 | |
c19d1205 ZW |
3726 | /* Mark the pool as empty. */ |
3727 | pool->next_free_entry = 0; | |
3728 | pool->symbol = NULL; | |
b99bd4ef NC |
3729 | } |
3730 | ||
c19d1205 ZW |
3731 | #ifdef OBJ_ELF |
3732 | /* Forward declarations for functions below, in the MD interface | |
3733 | section. */ | |
3734 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
3735 | static valueT create_unwind_entry (int); | |
3736 | static void start_unwind_section (const segT, int); | |
3737 | static void add_unwind_opcode (valueT, int); | |
3738 | static void flush_pending_unwind (void); | |
b99bd4ef | 3739 | |
c19d1205 | 3740 | /* Directives: Data. */ |
b99bd4ef | 3741 | |
c19d1205 ZW |
3742 | static void |
3743 | s_arm_elf_cons (int nbytes) | |
3744 | { | |
3745 | expressionS exp; | |
b99bd4ef | 3746 | |
c19d1205 ZW |
3747 | #ifdef md_flush_pending_output |
3748 | md_flush_pending_output (); | |
3749 | #endif | |
b99bd4ef | 3750 | |
c19d1205 | 3751 | if (is_it_end_of_statement ()) |
b99bd4ef | 3752 | { |
c19d1205 ZW |
3753 | demand_empty_rest_of_line (); |
3754 | return; | |
b99bd4ef NC |
3755 | } |
3756 | ||
c19d1205 ZW |
3757 | #ifdef md_cons_align |
3758 | md_cons_align (nbytes); | |
3759 | #endif | |
b99bd4ef | 3760 | |
c19d1205 ZW |
3761 | mapping_state (MAP_DATA); |
3762 | do | |
b99bd4ef | 3763 | { |
c19d1205 ZW |
3764 | int reloc; |
3765 | char *base = input_line_pointer; | |
b99bd4ef | 3766 | |
c19d1205 | 3767 | expression (& exp); |
b99bd4ef | 3768 | |
c19d1205 ZW |
3769 | if (exp.X_op != O_symbol) |
3770 | emit_expr (&exp, (unsigned int) nbytes); | |
3771 | else | |
3772 | { | |
3773 | char *before_reloc = input_line_pointer; | |
3774 | reloc = parse_reloc (&input_line_pointer); | |
3775 | if (reloc == -1) | |
3776 | { | |
3777 | as_bad (_("unrecognized relocation suffix")); | |
3778 | ignore_rest_of_line (); | |
3779 | return; | |
3780 | } | |
3781 | else if (reloc == BFD_RELOC_UNUSED) | |
3782 | emit_expr (&exp, (unsigned int) nbytes); | |
3783 | else | |
3784 | { | |
21d799b5 | 3785 | reloc_howto_type *howto = (reloc_howto_type *) |
477330fc RM |
3786 | bfd_reloc_type_lookup (stdoutput, |
3787 | (bfd_reloc_code_real_type) reloc); | |
c19d1205 | 3788 | int size = bfd_get_reloc_size (howto); |
b99bd4ef | 3789 | |
2fc8bdac ZW |
3790 | if (reloc == BFD_RELOC_ARM_PLT32) |
3791 | { | |
3792 | as_bad (_("(plt) is only valid on branch targets")); | |
3793 | reloc = BFD_RELOC_UNUSED; | |
3794 | size = 0; | |
3795 | } | |
3796 | ||
c19d1205 | 3797 | if (size > nbytes) |
992a06ee AM |
3798 | as_bad (ngettext ("%s relocations do not fit in %d byte", |
3799 | "%s relocations do not fit in %d bytes", | |
3800 | nbytes), | |
c19d1205 ZW |
3801 | howto->name, nbytes); |
3802 | else | |
3803 | { | |
3804 | /* We've parsed an expression stopping at O_symbol. | |
3805 | But there may be more expression left now that we | |
3806 | have parsed the relocation marker. Parse it again. | |
3807 | XXX Surely there is a cleaner way to do this. */ | |
3808 | char *p = input_line_pointer; | |
3809 | int offset; | |
325801bd | 3810 | char *save_buf = XNEWVEC (char, input_line_pointer - base); |
e1fa0163 | 3811 | |
c19d1205 ZW |
3812 | memcpy (save_buf, base, input_line_pointer - base); |
3813 | memmove (base + (input_line_pointer - before_reloc), | |
3814 | base, before_reloc - base); | |
3815 | ||
3816 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
3817 | expression (&exp); | |
3818 | memcpy (base, save_buf, p - base); | |
3819 | ||
3820 | offset = nbytes - size; | |
4b1a927e AM |
3821 | p = frag_more (nbytes); |
3822 | memset (p, 0, nbytes); | |
c19d1205 | 3823 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, |
21d799b5 | 3824 | size, &exp, 0, (enum bfd_reloc_code_real) reloc); |
e1fa0163 | 3825 | free (save_buf); |
c19d1205 ZW |
3826 | } |
3827 | } | |
3828 | } | |
b99bd4ef | 3829 | } |
c19d1205 | 3830 | while (*input_line_pointer++ == ','); |
b99bd4ef | 3831 | |
c19d1205 ZW |
3832 | /* Put terminator back into stream. */ |
3833 | input_line_pointer --; | |
3834 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
3835 | } |
3836 | ||
c921be7d NC |
3837 | /* Emit an expression containing a 32-bit thumb instruction. |
3838 | Implementation based on put_thumb32_insn. */ | |
3839 | ||
3840 | static void | |
3841 | emit_thumb32_expr (expressionS * exp) | |
3842 | { | |
3843 | expressionS exp_high = *exp; | |
3844 | ||
3845 | exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16; | |
3846 | emit_expr (& exp_high, (unsigned int) THUMB_SIZE); | |
3847 | exp->X_add_number &= 0xffff; | |
3848 | emit_expr (exp, (unsigned int) THUMB_SIZE); | |
3849 | } | |
3850 | ||
3851 | /* Guess the instruction size based on the opcode. */ | |
3852 | ||
3853 | static int | |
3854 | thumb_insn_size (int opcode) | |
3855 | { | |
3856 | if ((unsigned int) opcode < 0xe800u) | |
3857 | return 2; | |
3858 | else if ((unsigned int) opcode >= 0xe8000000u) | |
3859 | return 4; | |
3860 | else | |
3861 | return 0; | |
3862 | } | |
3863 | ||
3864 | static bfd_boolean | |
3865 | emit_insn (expressionS *exp, int nbytes) | |
3866 | { | |
3867 | int size = 0; | |
3868 | ||
3869 | if (exp->X_op == O_constant) | |
3870 | { | |
3871 | size = nbytes; | |
3872 | ||
3873 | if (size == 0) | |
3874 | size = thumb_insn_size (exp->X_add_number); | |
3875 | ||
3876 | if (size != 0) | |
3877 | { | |
3878 | if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu) | |
3879 | { | |
3880 | as_bad (_(".inst.n operand too big. "\ | |
3881 | "Use .inst.w instead")); | |
3882 | size = 0; | |
3883 | } | |
3884 | else | |
3885 | { | |
5ee91343 AV |
3886 | if (now_pred.state == AUTOMATIC_PRED_BLOCK) |
3887 | set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN, 0); | |
c921be7d | 3888 | else |
5ee91343 | 3889 | set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN, 0); |
c921be7d NC |
3890 | |
3891 | if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian) | |
3892 | emit_thumb32_expr (exp); | |
3893 | else | |
3894 | emit_expr (exp, (unsigned int) size); | |
3895 | ||
3896 | it_fsm_post_encode (); | |
3897 | } | |
3898 | } | |
3899 | else | |
3900 | as_bad (_("cannot determine Thumb instruction size. " \ | |
3901 | "Use .inst.n/.inst.w instead")); | |
3902 | } | |
3903 | else | |
3904 | as_bad (_("constant expression required")); | |
3905 | ||
3906 | return (size != 0); | |
3907 | } | |
3908 | ||
3909 | /* Like s_arm_elf_cons but do not use md_cons_align and | |
3910 | set the mapping state to MAP_ARM/MAP_THUMB. */ | |
3911 | ||
3912 | static void | |
3913 | s_arm_elf_inst (int nbytes) | |
3914 | { | |
3915 | if (is_it_end_of_statement ()) | |
3916 | { | |
3917 | demand_empty_rest_of_line (); | |
3918 | return; | |
3919 | } | |
3920 | ||
3921 | /* Calling mapping_state () here will not change ARM/THUMB, | |
3922 | but will ensure not to be in DATA state. */ | |
3923 | ||
3924 | if (thumb_mode) | |
3925 | mapping_state (MAP_THUMB); | |
3926 | else | |
3927 | { | |
3928 | if (nbytes != 0) | |
3929 | { | |
3930 | as_bad (_("width suffixes are invalid in ARM mode")); | |
3931 | ignore_rest_of_line (); | |
3932 | return; | |
3933 | } | |
3934 | ||
3935 | nbytes = 4; | |
3936 | ||
3937 | mapping_state (MAP_ARM); | |
3938 | } | |
3939 | ||
3940 | do | |
3941 | { | |
3942 | expressionS exp; | |
3943 | ||
3944 | expression (& exp); | |
3945 | ||
3946 | if (! emit_insn (& exp, nbytes)) | |
3947 | { | |
3948 | ignore_rest_of_line (); | |
3949 | return; | |
3950 | } | |
3951 | } | |
3952 | while (*input_line_pointer++ == ','); | |
3953 | ||
3954 | /* Put terminator back into stream. */ | |
3955 | input_line_pointer --; | |
3956 | demand_empty_rest_of_line (); | |
3957 | } | |
b99bd4ef | 3958 | |
c19d1205 | 3959 | /* Parse a .rel31 directive. */ |
b99bd4ef | 3960 | |
c19d1205 ZW |
3961 | static void |
3962 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
3963 | { | |
3964 | expressionS exp; | |
3965 | char *p; | |
3966 | valueT highbit; | |
b99bd4ef | 3967 | |
c19d1205 ZW |
3968 | highbit = 0; |
3969 | if (*input_line_pointer == '1') | |
3970 | highbit = 0x80000000; | |
3971 | else if (*input_line_pointer != '0') | |
3972 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 3973 | |
c19d1205 ZW |
3974 | input_line_pointer++; |
3975 | if (*input_line_pointer != ',') | |
3976 | as_bad (_("missing comma")); | |
3977 | input_line_pointer++; | |
b99bd4ef | 3978 | |
c19d1205 ZW |
3979 | #ifdef md_flush_pending_output |
3980 | md_flush_pending_output (); | |
3981 | #endif | |
b99bd4ef | 3982 | |
c19d1205 ZW |
3983 | #ifdef md_cons_align |
3984 | md_cons_align (4); | |
3985 | #endif | |
b99bd4ef | 3986 | |
c19d1205 | 3987 | mapping_state (MAP_DATA); |
b99bd4ef | 3988 | |
c19d1205 | 3989 | expression (&exp); |
b99bd4ef | 3990 | |
c19d1205 ZW |
3991 | p = frag_more (4); |
3992 | md_number_to_chars (p, highbit, 4); | |
3993 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
3994 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 3995 | |
c19d1205 | 3996 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3997 | } |
3998 | ||
c19d1205 | 3999 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 4000 | |
c19d1205 | 4001 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 4002 | |
c19d1205 ZW |
4003 | static void |
4004 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
4005 | { | |
4006 | demand_empty_rest_of_line (); | |
921e5f0a PB |
4007 | if (unwind.proc_start) |
4008 | { | |
c921be7d | 4009 | as_bad (_("duplicate .fnstart directive")); |
921e5f0a PB |
4010 | return; |
4011 | } | |
4012 | ||
c19d1205 ZW |
4013 | /* Mark the start of the function. */ |
4014 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 4015 | |
c19d1205 ZW |
4016 | /* Reset the rest of the unwind info. */ |
4017 | unwind.opcode_count = 0; | |
4018 | unwind.table_entry = NULL; | |
4019 | unwind.personality_routine = NULL; | |
4020 | unwind.personality_index = -1; | |
4021 | unwind.frame_size = 0; | |
4022 | unwind.fp_offset = 0; | |
fdfde340 | 4023 | unwind.fp_reg = REG_SP; |
c19d1205 ZW |
4024 | unwind.fp_used = 0; |
4025 | unwind.sp_restored = 0; | |
4026 | } | |
b99bd4ef | 4027 | |
b99bd4ef | 4028 | |
c19d1205 ZW |
4029 | /* Parse a handlerdata directive. Creates the exception handling table entry |
4030 | for the function. */ | |
b99bd4ef | 4031 | |
c19d1205 ZW |
4032 | static void |
4033 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
4034 | { | |
4035 | demand_empty_rest_of_line (); | |
921e5f0a | 4036 | if (!unwind.proc_start) |
c921be7d | 4037 | as_bad (MISSING_FNSTART); |
921e5f0a | 4038 | |
c19d1205 | 4039 | if (unwind.table_entry) |
6decc662 | 4040 | as_bad (_("duplicate .handlerdata directive")); |
f02232aa | 4041 | |
c19d1205 ZW |
4042 | create_unwind_entry (1); |
4043 | } | |
a737bd4d | 4044 | |
c19d1205 | 4045 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 4046 | |
c19d1205 ZW |
4047 | static void |
4048 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
4049 | { | |
4050 | long where; | |
4051 | char *ptr; | |
4052 | valueT val; | |
940b5ce0 | 4053 | unsigned int marked_pr_dependency; |
f02232aa | 4054 | |
c19d1205 | 4055 | demand_empty_rest_of_line (); |
f02232aa | 4056 | |
921e5f0a PB |
4057 | if (!unwind.proc_start) |
4058 | { | |
c921be7d | 4059 | as_bad (_(".fnend directive without .fnstart")); |
921e5f0a PB |
4060 | return; |
4061 | } | |
4062 | ||
c19d1205 ZW |
4063 | /* Add eh table entry. */ |
4064 | if (unwind.table_entry == NULL) | |
4065 | val = create_unwind_entry (0); | |
4066 | else | |
4067 | val = 0; | |
f02232aa | 4068 | |
c19d1205 ZW |
4069 | /* Add index table entry. This is two words. */ |
4070 | start_unwind_section (unwind.saved_seg, 1); | |
4071 | frag_align (2, 0, 0); | |
4072 | record_alignment (now_seg, 2); | |
b99bd4ef | 4073 | |
c19d1205 | 4074 | ptr = frag_more (8); |
5011093d | 4075 | memset (ptr, 0, 8); |
c19d1205 | 4076 | where = frag_now_fix () - 8; |
f02232aa | 4077 | |
c19d1205 ZW |
4078 | /* Self relative offset of the function start. */ |
4079 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
4080 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 4081 | |
c19d1205 ZW |
4082 | /* Indicate dependency on EHABI-defined personality routines to the |
4083 | linker, if it hasn't been done already. */ | |
940b5ce0 DJ |
4084 | marked_pr_dependency |
4085 | = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency; | |
c19d1205 ZW |
4086 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 |
4087 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
4088 | { | |
5f4273c7 NC |
4089 | static const char *const name[] = |
4090 | { | |
4091 | "__aeabi_unwind_cpp_pr0", | |
4092 | "__aeabi_unwind_cpp_pr1", | |
4093 | "__aeabi_unwind_cpp_pr2" | |
4094 | }; | |
c19d1205 ZW |
4095 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); |
4096 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
c19d1205 | 4097 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency |
940b5ce0 | 4098 | |= 1 << unwind.personality_index; |
c19d1205 | 4099 | } |
f02232aa | 4100 | |
c19d1205 ZW |
4101 | if (val) |
4102 | /* Inline exception table entry. */ | |
4103 | md_number_to_chars (ptr + 4, val, 4); | |
4104 | else | |
4105 | /* Self relative offset of the table entry. */ | |
4106 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
4107 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 4108 | |
c19d1205 ZW |
4109 | /* Restore the original section. */ |
4110 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
921e5f0a PB |
4111 | |
4112 | unwind.proc_start = NULL; | |
c19d1205 | 4113 | } |
f02232aa | 4114 | |
f02232aa | 4115 | |
c19d1205 | 4116 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 4117 | |
c19d1205 ZW |
4118 | static void |
4119 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
4120 | { | |
4121 | demand_empty_rest_of_line (); | |
921e5f0a | 4122 | if (!unwind.proc_start) |
c921be7d | 4123 | as_bad (MISSING_FNSTART); |
921e5f0a | 4124 | |
c19d1205 ZW |
4125 | if (unwind.personality_routine || unwind.personality_index != -1) |
4126 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 4127 | |
c19d1205 ZW |
4128 | unwind.personality_index = -2; |
4129 | } | |
b99bd4ef | 4130 | |
b99bd4ef | 4131 | |
c19d1205 | 4132 | /* Parse a personalityindex directive. */ |
b99bd4ef | 4133 | |
c19d1205 ZW |
4134 | static void |
4135 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
4136 | { | |
4137 | expressionS exp; | |
b99bd4ef | 4138 | |
921e5f0a | 4139 | if (!unwind.proc_start) |
c921be7d | 4140 | as_bad (MISSING_FNSTART); |
921e5f0a | 4141 | |
c19d1205 ZW |
4142 | if (unwind.personality_routine || unwind.personality_index != -1) |
4143 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 4144 | |
c19d1205 | 4145 | expression (&exp); |
b99bd4ef | 4146 | |
c19d1205 ZW |
4147 | if (exp.X_op != O_constant |
4148 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 4149 | { |
c19d1205 ZW |
4150 | as_bad (_("bad personality routine number")); |
4151 | ignore_rest_of_line (); | |
4152 | return; | |
b99bd4ef NC |
4153 | } |
4154 | ||
c19d1205 | 4155 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 4156 | |
c19d1205 ZW |
4157 | demand_empty_rest_of_line (); |
4158 | } | |
e16bb312 | 4159 | |
e16bb312 | 4160 | |
c19d1205 | 4161 | /* Parse a personality directive. */ |
e16bb312 | 4162 | |
c19d1205 ZW |
4163 | static void |
4164 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
4165 | { | |
4166 | char *name, *p, c; | |
a737bd4d | 4167 | |
921e5f0a | 4168 | if (!unwind.proc_start) |
c921be7d | 4169 | as_bad (MISSING_FNSTART); |
921e5f0a | 4170 | |
c19d1205 ZW |
4171 | if (unwind.personality_routine || unwind.personality_index != -1) |
4172 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 4173 | |
d02603dc | 4174 | c = get_symbol_name (& name); |
c19d1205 | 4175 | p = input_line_pointer; |
d02603dc NC |
4176 | if (c == '"') |
4177 | ++ input_line_pointer; | |
c19d1205 ZW |
4178 | unwind.personality_routine = symbol_find_or_make (name); |
4179 | *p = c; | |
4180 | demand_empty_rest_of_line (); | |
4181 | } | |
e16bb312 | 4182 | |
e16bb312 | 4183 | |
c19d1205 | 4184 | /* Parse a directive saving core registers. */ |
e16bb312 | 4185 | |
c19d1205 ZW |
4186 | static void |
4187 | s_arm_unwind_save_core (void) | |
e16bb312 | 4188 | { |
c19d1205 ZW |
4189 | valueT op; |
4190 | long range; | |
4191 | int n; | |
e16bb312 | 4192 | |
4b5a202f | 4193 | range = parse_reg_list (&input_line_pointer, REGLIST_RN); |
c19d1205 | 4194 | if (range == FAIL) |
e16bb312 | 4195 | { |
c19d1205 ZW |
4196 | as_bad (_("expected register list")); |
4197 | ignore_rest_of_line (); | |
4198 | return; | |
4199 | } | |
e16bb312 | 4200 | |
c19d1205 | 4201 | demand_empty_rest_of_line (); |
e16bb312 | 4202 | |
c19d1205 ZW |
4203 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
4204 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
4205 | ip because it is clobbered by calls. */ | |
4206 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
4207 | && (range & 0x3000) == 0x1000) | |
4208 | { | |
4209 | unwind.opcode_count--; | |
4210 | unwind.sp_restored = 0; | |
4211 | range = (range | 0x2000) & ~0x1000; | |
4212 | unwind.pending_offset = 0; | |
4213 | } | |
e16bb312 | 4214 | |
01ae4198 DJ |
4215 | /* Pop r4-r15. */ |
4216 | if (range & 0xfff0) | |
c19d1205 | 4217 | { |
01ae4198 DJ |
4218 | /* See if we can use the short opcodes. These pop a block of up to 8 |
4219 | registers starting with r4, plus maybe r14. */ | |
4220 | for (n = 0; n < 8; n++) | |
4221 | { | |
4222 | /* Break at the first non-saved register. */ | |
4223 | if ((range & (1 << (n + 4))) == 0) | |
4224 | break; | |
4225 | } | |
4226 | /* See if there are any other bits set. */ | |
4227 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
4228 | { | |
4229 | /* Use the long form. */ | |
4230 | op = 0x8000 | ((range >> 4) & 0xfff); | |
4231 | add_unwind_opcode (op, 2); | |
4232 | } | |
0dd132b6 | 4233 | else |
01ae4198 DJ |
4234 | { |
4235 | /* Use the short form. */ | |
4236 | if (range & 0x4000) | |
4237 | op = 0xa8; /* Pop r14. */ | |
4238 | else | |
4239 | op = 0xa0; /* Do not pop r14. */ | |
4240 | op |= (n - 1); | |
4241 | add_unwind_opcode (op, 1); | |
4242 | } | |
c19d1205 | 4243 | } |
0dd132b6 | 4244 | |
c19d1205 ZW |
4245 | /* Pop r0-r3. */ |
4246 | if (range & 0xf) | |
4247 | { | |
4248 | op = 0xb100 | (range & 0xf); | |
4249 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
4250 | } |
4251 | ||
c19d1205 ZW |
4252 | /* Record the number of bytes pushed. */ |
4253 | for (n = 0; n < 16; n++) | |
4254 | { | |
4255 | if (range & (1 << n)) | |
4256 | unwind.frame_size += 4; | |
4257 | } | |
0dd132b6 NC |
4258 | } |
4259 | ||
c19d1205 ZW |
4260 | |
4261 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
4262 | |
4263 | static void | |
c19d1205 | 4264 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 4265 | { |
c19d1205 ZW |
4266 | expressionS exp; |
4267 | int num_regs; | |
4268 | valueT op; | |
b99bd4ef | 4269 | |
c19d1205 ZW |
4270 | /* Get Number of registers to transfer. */ |
4271 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4272 | expression (&exp); | |
4273 | else | |
4274 | exp.X_op = O_illegal; | |
b99bd4ef | 4275 | |
c19d1205 | 4276 | if (exp.X_op != O_constant) |
b99bd4ef | 4277 | { |
c19d1205 ZW |
4278 | as_bad (_("expected , <constant>")); |
4279 | ignore_rest_of_line (); | |
b99bd4ef NC |
4280 | return; |
4281 | } | |
4282 | ||
c19d1205 ZW |
4283 | num_regs = exp.X_add_number; |
4284 | ||
4285 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 4286 | { |
c19d1205 ZW |
4287 | as_bad (_("number of registers must be in the range [1:4]")); |
4288 | ignore_rest_of_line (); | |
b99bd4ef NC |
4289 | return; |
4290 | } | |
4291 | ||
c19d1205 | 4292 | demand_empty_rest_of_line (); |
b99bd4ef | 4293 | |
c19d1205 ZW |
4294 | if (reg == 4) |
4295 | { | |
4296 | /* Short form. */ | |
4297 | op = 0xb4 | (num_regs - 1); | |
4298 | add_unwind_opcode (op, 1); | |
4299 | } | |
b99bd4ef NC |
4300 | else |
4301 | { | |
c19d1205 ZW |
4302 | /* Long form. */ |
4303 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
4304 | add_unwind_opcode (op, 2); | |
b99bd4ef | 4305 | } |
c19d1205 | 4306 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
4307 | } |
4308 | ||
c19d1205 | 4309 | |
fa073d69 MS |
4310 | /* Parse a directive saving VFP registers for ARMv6 and above. */ |
4311 | ||
4312 | static void | |
4313 | s_arm_unwind_save_vfp_armv6 (void) | |
4314 | { | |
4315 | int count; | |
4316 | unsigned int start; | |
4317 | valueT op; | |
4318 | int num_vfpv3_regs = 0; | |
4319 | int num_regs_below_16; | |
efd6b359 | 4320 | bfd_boolean partial_match; |
fa073d69 | 4321 | |
efd6b359 AV |
4322 | count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D, |
4323 | &partial_match); | |
fa073d69 MS |
4324 | if (count == FAIL) |
4325 | { | |
4326 | as_bad (_("expected register list")); | |
4327 | ignore_rest_of_line (); | |
4328 | return; | |
4329 | } | |
4330 | ||
4331 | demand_empty_rest_of_line (); | |
4332 | ||
4333 | /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather | |
4334 | than FSTMX/FLDMX-style ones). */ | |
4335 | ||
4336 | /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ | |
4337 | if (start >= 16) | |
4338 | num_vfpv3_regs = count; | |
4339 | else if (start + count > 16) | |
4340 | num_vfpv3_regs = start + count - 16; | |
4341 | ||
4342 | if (num_vfpv3_regs > 0) | |
4343 | { | |
4344 | int start_offset = start > 16 ? start - 16 : 0; | |
4345 | op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); | |
4346 | add_unwind_opcode (op, 2); | |
4347 | } | |
4348 | ||
4349 | /* Generate opcode for registers numbered in the range 0 .. 15. */ | |
4350 | num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; | |
9c2799c2 | 4351 | gas_assert (num_regs_below_16 + num_vfpv3_regs == count); |
fa073d69 MS |
4352 | if (num_regs_below_16 > 0) |
4353 | { | |
4354 | op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); | |
4355 | add_unwind_opcode (op, 2); | |
4356 | } | |
4357 | ||
4358 | unwind.frame_size += count * 8; | |
4359 | } | |
4360 | ||
4361 | ||
4362 | /* Parse a directive saving VFP registers for pre-ARMv6. */ | |
b99bd4ef NC |
4363 | |
4364 | static void | |
c19d1205 | 4365 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 4366 | { |
c19d1205 | 4367 | int count; |
ca3f61f7 | 4368 | unsigned int reg; |
c19d1205 | 4369 | valueT op; |
efd6b359 | 4370 | bfd_boolean partial_match; |
b99bd4ef | 4371 | |
efd6b359 AV |
4372 | count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D, |
4373 | &partial_match); | |
c19d1205 | 4374 | if (count == FAIL) |
b99bd4ef | 4375 | { |
c19d1205 ZW |
4376 | as_bad (_("expected register list")); |
4377 | ignore_rest_of_line (); | |
b99bd4ef NC |
4378 | return; |
4379 | } | |
4380 | ||
c19d1205 | 4381 | demand_empty_rest_of_line (); |
b99bd4ef | 4382 | |
c19d1205 | 4383 | if (reg == 8) |
b99bd4ef | 4384 | { |
c19d1205 ZW |
4385 | /* Short form. */ |
4386 | op = 0xb8 | (count - 1); | |
4387 | add_unwind_opcode (op, 1); | |
b99bd4ef | 4388 | } |
c19d1205 | 4389 | else |
b99bd4ef | 4390 | { |
c19d1205 ZW |
4391 | /* Long form. */ |
4392 | op = 0xb300 | (reg << 4) | (count - 1); | |
4393 | add_unwind_opcode (op, 2); | |
b99bd4ef | 4394 | } |
c19d1205 ZW |
4395 | unwind.frame_size += count * 8 + 4; |
4396 | } | |
b99bd4ef | 4397 | |
b99bd4ef | 4398 | |
c19d1205 ZW |
4399 | /* Parse a directive saving iWMMXt data registers. */ |
4400 | ||
4401 | static void | |
4402 | s_arm_unwind_save_mmxwr (void) | |
4403 | { | |
4404 | int reg; | |
4405 | int hi_reg; | |
4406 | int i; | |
4407 | unsigned mask = 0; | |
4408 | valueT op; | |
b99bd4ef | 4409 | |
c19d1205 ZW |
4410 | if (*input_line_pointer == '{') |
4411 | input_line_pointer++; | |
b99bd4ef | 4412 | |
c19d1205 | 4413 | do |
b99bd4ef | 4414 | { |
dcbf9037 | 4415 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 4416 | |
c19d1205 | 4417 | if (reg == FAIL) |
b99bd4ef | 4418 | { |
9b7132d3 | 4419 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 | 4420 | goto error; |
b99bd4ef NC |
4421 | } |
4422 | ||
c19d1205 ZW |
4423 | if (mask >> reg) |
4424 | as_tsktsk (_("register list not in ascending order")); | |
4425 | mask |= 1 << reg; | |
b99bd4ef | 4426 | |
c19d1205 ZW |
4427 | if (*input_line_pointer == '-') |
4428 | { | |
4429 | input_line_pointer++; | |
dcbf9037 | 4430 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
c19d1205 ZW |
4431 | if (hi_reg == FAIL) |
4432 | { | |
9b7132d3 | 4433 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 ZW |
4434 | goto error; |
4435 | } | |
4436 | else if (reg >= hi_reg) | |
4437 | { | |
4438 | as_bad (_("bad register range")); | |
4439 | goto error; | |
4440 | } | |
4441 | for (; reg < hi_reg; reg++) | |
4442 | mask |= 1 << reg; | |
4443 | } | |
4444 | } | |
4445 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 4446 | |
d996d970 | 4447 | skip_past_char (&input_line_pointer, '}'); |
b99bd4ef | 4448 | |
c19d1205 | 4449 | demand_empty_rest_of_line (); |
b99bd4ef | 4450 | |
708587a4 | 4451 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
4452 | the list. */ |
4453 | flush_pending_unwind (); | |
b99bd4ef | 4454 | |
c19d1205 | 4455 | for (i = 0; i < 16; i++) |
b99bd4ef | 4456 | { |
c19d1205 ZW |
4457 | if (mask & (1 << i)) |
4458 | unwind.frame_size += 8; | |
b99bd4ef NC |
4459 | } |
4460 | ||
c19d1205 ZW |
4461 | /* Attempt to combine with a previous opcode. We do this because gcc |
4462 | likes to output separate unwind directives for a single block of | |
4463 | registers. */ | |
4464 | if (unwind.opcode_count > 0) | |
b99bd4ef | 4465 | { |
c19d1205 ZW |
4466 | i = unwind.opcodes[unwind.opcode_count - 1]; |
4467 | if ((i & 0xf8) == 0xc0) | |
4468 | { | |
4469 | i &= 7; | |
4470 | /* Only merge if the blocks are contiguous. */ | |
4471 | if (i < 6) | |
4472 | { | |
4473 | if ((mask & 0xfe00) == (1 << 9)) | |
4474 | { | |
4475 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
4476 | unwind.opcode_count--; | |
4477 | } | |
4478 | } | |
4479 | else if (i == 6 && unwind.opcode_count >= 2) | |
4480 | { | |
4481 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
4482 | reg = i >> 4; | |
4483 | i &= 0xf; | |
b99bd4ef | 4484 | |
c19d1205 ZW |
4485 | op = 0xffff << (reg - 1); |
4486 | if (reg > 0 | |
87a1fd79 | 4487 | && ((mask & op) == (1u << (reg - 1)))) |
c19d1205 ZW |
4488 | { |
4489 | op = (1 << (reg + i + 1)) - 1; | |
4490 | op &= ~((1 << reg) - 1); | |
4491 | mask |= op; | |
4492 | unwind.opcode_count -= 2; | |
4493 | } | |
4494 | } | |
4495 | } | |
b99bd4ef NC |
4496 | } |
4497 | ||
c19d1205 ZW |
4498 | hi_reg = 15; |
4499 | /* We want to generate opcodes in the order the registers have been | |
4500 | saved, ie. descending order. */ | |
4501 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 4502 | { |
c19d1205 ZW |
4503 | /* Save registers in blocks. */ |
4504 | if (reg < 0 | |
4505 | || !(mask & (1 << reg))) | |
4506 | { | |
4507 | /* We found an unsaved reg. Generate opcodes to save the | |
5f4273c7 | 4508 | preceding block. */ |
c19d1205 ZW |
4509 | if (reg != hi_reg) |
4510 | { | |
4511 | if (reg == 9) | |
4512 | { | |
4513 | /* Short form. */ | |
4514 | op = 0xc0 | (hi_reg - 10); | |
4515 | add_unwind_opcode (op, 1); | |
4516 | } | |
4517 | else | |
4518 | { | |
4519 | /* Long form. */ | |
4520 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
4521 | add_unwind_opcode (op, 2); | |
4522 | } | |
4523 | } | |
4524 | hi_reg = reg - 1; | |
4525 | } | |
b99bd4ef NC |
4526 | } |
4527 | ||
c19d1205 ZW |
4528 | return; |
4529 | error: | |
4530 | ignore_rest_of_line (); | |
b99bd4ef NC |
4531 | } |
4532 | ||
4533 | static void | |
c19d1205 | 4534 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 4535 | { |
c19d1205 ZW |
4536 | int reg; |
4537 | int hi_reg; | |
4538 | unsigned mask = 0; | |
4539 | valueT op; | |
b99bd4ef | 4540 | |
c19d1205 ZW |
4541 | if (*input_line_pointer == '{') |
4542 | input_line_pointer++; | |
b99bd4ef | 4543 | |
477330fc RM |
4544 | skip_whitespace (input_line_pointer); |
4545 | ||
c19d1205 | 4546 | do |
b99bd4ef | 4547 | { |
dcbf9037 | 4548 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 4549 | |
c19d1205 ZW |
4550 | if (reg == FAIL) |
4551 | { | |
9b7132d3 | 4552 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4553 | goto error; |
4554 | } | |
b99bd4ef | 4555 | |
c19d1205 ZW |
4556 | reg -= 8; |
4557 | if (mask >> reg) | |
4558 | as_tsktsk (_("register list not in ascending order")); | |
4559 | mask |= 1 << reg; | |
b99bd4ef | 4560 | |
c19d1205 ZW |
4561 | if (*input_line_pointer == '-') |
4562 | { | |
4563 | input_line_pointer++; | |
dcbf9037 | 4564 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
c19d1205 ZW |
4565 | if (hi_reg == FAIL) |
4566 | { | |
9b7132d3 | 4567 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4568 | goto error; |
4569 | } | |
4570 | else if (reg >= hi_reg) | |
4571 | { | |
4572 | as_bad (_("bad register range")); | |
4573 | goto error; | |
4574 | } | |
4575 | for (; reg < hi_reg; reg++) | |
4576 | mask |= 1 << reg; | |
4577 | } | |
b99bd4ef | 4578 | } |
c19d1205 | 4579 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 4580 | |
d996d970 | 4581 | skip_past_char (&input_line_pointer, '}'); |
b99bd4ef | 4582 | |
c19d1205 ZW |
4583 | demand_empty_rest_of_line (); |
4584 | ||
708587a4 | 4585 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
4586 | the list. */ |
4587 | flush_pending_unwind (); | |
b99bd4ef | 4588 | |
c19d1205 | 4589 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 4590 | { |
c19d1205 ZW |
4591 | if (mask & (1 << reg)) |
4592 | unwind.frame_size += 4; | |
b99bd4ef | 4593 | } |
c19d1205 ZW |
4594 | op = 0xc700 | mask; |
4595 | add_unwind_opcode (op, 2); | |
4596 | return; | |
4597 | error: | |
4598 | ignore_rest_of_line (); | |
b99bd4ef NC |
4599 | } |
4600 | ||
c19d1205 | 4601 | |
fa073d69 MS |
4602 | /* Parse an unwind_save directive. |
4603 | If the argument is non-zero, this is a .vsave directive. */ | |
c19d1205 | 4604 | |
b99bd4ef | 4605 | static void |
fa073d69 | 4606 | s_arm_unwind_save (int arch_v6) |
b99bd4ef | 4607 | { |
c19d1205 ZW |
4608 | char *peek; |
4609 | struct reg_entry *reg; | |
4610 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 4611 | |
921e5f0a | 4612 | if (!unwind.proc_start) |
c921be7d | 4613 | as_bad (MISSING_FNSTART); |
921e5f0a | 4614 | |
c19d1205 ZW |
4615 | /* Figure out what sort of save we have. */ |
4616 | peek = input_line_pointer; | |
b99bd4ef | 4617 | |
c19d1205 | 4618 | if (*peek == '{') |
b99bd4ef | 4619 | { |
c19d1205 ZW |
4620 | had_brace = TRUE; |
4621 | peek++; | |
b99bd4ef NC |
4622 | } |
4623 | ||
c19d1205 | 4624 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 4625 | |
c19d1205 | 4626 | if (!reg) |
b99bd4ef | 4627 | { |
c19d1205 ZW |
4628 | as_bad (_("register expected")); |
4629 | ignore_rest_of_line (); | |
b99bd4ef NC |
4630 | return; |
4631 | } | |
4632 | ||
c19d1205 | 4633 | switch (reg->type) |
b99bd4ef | 4634 | { |
c19d1205 ZW |
4635 | case REG_TYPE_FN: |
4636 | if (had_brace) | |
4637 | { | |
4638 | as_bad (_("FPA .unwind_save does not take a register list")); | |
4639 | ignore_rest_of_line (); | |
4640 | return; | |
4641 | } | |
93ac2687 | 4642 | input_line_pointer = peek; |
c19d1205 | 4643 | s_arm_unwind_save_fpa (reg->number); |
b99bd4ef | 4644 | return; |
c19d1205 | 4645 | |
1f5afe1c NC |
4646 | case REG_TYPE_RN: |
4647 | s_arm_unwind_save_core (); | |
4648 | return; | |
4649 | ||
fa073d69 MS |
4650 | case REG_TYPE_VFD: |
4651 | if (arch_v6) | |
477330fc | 4652 | s_arm_unwind_save_vfp_armv6 (); |
fa073d69 | 4653 | else |
477330fc | 4654 | s_arm_unwind_save_vfp (); |
fa073d69 | 4655 | return; |
1f5afe1c NC |
4656 | |
4657 | case REG_TYPE_MMXWR: | |
4658 | s_arm_unwind_save_mmxwr (); | |
4659 | return; | |
4660 | ||
4661 | case REG_TYPE_MMXWCG: | |
4662 | s_arm_unwind_save_mmxwcg (); | |
4663 | return; | |
c19d1205 ZW |
4664 | |
4665 | default: | |
4666 | as_bad (_(".unwind_save does not support this kind of register")); | |
4667 | ignore_rest_of_line (); | |
b99bd4ef | 4668 | } |
c19d1205 | 4669 | } |
b99bd4ef | 4670 | |
b99bd4ef | 4671 | |
c19d1205 ZW |
4672 | /* Parse an unwind_movsp directive. */ |
4673 | ||
4674 | static void | |
4675 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
4676 | { | |
4677 | int reg; | |
4678 | valueT op; | |
4fa3602b | 4679 | int offset; |
c19d1205 | 4680 | |
921e5f0a | 4681 | if (!unwind.proc_start) |
c921be7d | 4682 | as_bad (MISSING_FNSTART); |
921e5f0a | 4683 | |
dcbf9037 | 4684 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 | 4685 | if (reg == FAIL) |
b99bd4ef | 4686 | { |
9b7132d3 | 4687 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 | 4688 | ignore_rest_of_line (); |
b99bd4ef NC |
4689 | return; |
4690 | } | |
4fa3602b PB |
4691 | |
4692 | /* Optional constant. */ | |
4693 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4694 | { | |
4695 | if (immediate_for_directive (&offset) == FAIL) | |
4696 | return; | |
4697 | } | |
4698 | else | |
4699 | offset = 0; | |
4700 | ||
c19d1205 | 4701 | demand_empty_rest_of_line (); |
b99bd4ef | 4702 | |
c19d1205 | 4703 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 4704 | { |
c19d1205 | 4705 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
4706 | return; |
4707 | } | |
4708 | ||
c19d1205 ZW |
4709 | if (unwind.fp_reg != REG_SP) |
4710 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 4711 | |
c19d1205 ZW |
4712 | /* Generate opcode to restore the value. */ |
4713 | op = 0x90 | reg; | |
4714 | add_unwind_opcode (op, 1); | |
4715 | ||
4716 | /* Record the information for later. */ | |
4717 | unwind.fp_reg = reg; | |
4fa3602b | 4718 | unwind.fp_offset = unwind.frame_size - offset; |
c19d1205 | 4719 | unwind.sp_restored = 1; |
b05fe5cf ZW |
4720 | } |
4721 | ||
c19d1205 ZW |
4722 | /* Parse an unwind_pad directive. */ |
4723 | ||
b05fe5cf | 4724 | static void |
c19d1205 | 4725 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 4726 | { |
c19d1205 | 4727 | int offset; |
b05fe5cf | 4728 | |
921e5f0a | 4729 | if (!unwind.proc_start) |
c921be7d | 4730 | as_bad (MISSING_FNSTART); |
921e5f0a | 4731 | |
c19d1205 ZW |
4732 | if (immediate_for_directive (&offset) == FAIL) |
4733 | return; | |
b99bd4ef | 4734 | |
c19d1205 ZW |
4735 | if (offset & 3) |
4736 | { | |
4737 | as_bad (_("stack increment must be multiple of 4")); | |
4738 | ignore_rest_of_line (); | |
4739 | return; | |
4740 | } | |
b99bd4ef | 4741 | |
c19d1205 ZW |
4742 | /* Don't generate any opcodes, just record the details for later. */ |
4743 | unwind.frame_size += offset; | |
4744 | unwind.pending_offset += offset; | |
4745 | ||
4746 | demand_empty_rest_of_line (); | |
4747 | } | |
4748 | ||
4749 | /* Parse an unwind_setfp directive. */ | |
4750 | ||
4751 | static void | |
4752 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 4753 | { |
c19d1205 ZW |
4754 | int sp_reg; |
4755 | int fp_reg; | |
4756 | int offset; | |
4757 | ||
921e5f0a | 4758 | if (!unwind.proc_start) |
c921be7d | 4759 | as_bad (MISSING_FNSTART); |
921e5f0a | 4760 | |
dcbf9037 | 4761 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 ZW |
4762 | if (skip_past_comma (&input_line_pointer) == FAIL) |
4763 | sp_reg = FAIL; | |
4764 | else | |
dcbf9037 | 4765 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
b99bd4ef | 4766 | |
c19d1205 ZW |
4767 | if (fp_reg == FAIL || sp_reg == FAIL) |
4768 | { | |
4769 | as_bad (_("expected <reg>, <reg>")); | |
4770 | ignore_rest_of_line (); | |
4771 | return; | |
4772 | } | |
b99bd4ef | 4773 | |
c19d1205 ZW |
4774 | /* Optional constant. */ |
4775 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4776 | { | |
4777 | if (immediate_for_directive (&offset) == FAIL) | |
4778 | return; | |
4779 | } | |
4780 | else | |
4781 | offset = 0; | |
a737bd4d | 4782 | |
c19d1205 | 4783 | demand_empty_rest_of_line (); |
a737bd4d | 4784 | |
fdfde340 | 4785 | if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) |
a737bd4d | 4786 | { |
c19d1205 ZW |
4787 | as_bad (_("register must be either sp or set by a previous" |
4788 | "unwind_movsp directive")); | |
4789 | return; | |
a737bd4d NC |
4790 | } |
4791 | ||
c19d1205 ZW |
4792 | /* Don't generate any opcodes, just record the information for later. */ |
4793 | unwind.fp_reg = fp_reg; | |
4794 | unwind.fp_used = 1; | |
fdfde340 | 4795 | if (sp_reg == REG_SP) |
c19d1205 ZW |
4796 | unwind.fp_offset = unwind.frame_size - offset; |
4797 | else | |
4798 | unwind.fp_offset -= offset; | |
a737bd4d NC |
4799 | } |
4800 | ||
c19d1205 ZW |
4801 | /* Parse an unwind_raw directive. */ |
4802 | ||
4803 | static void | |
4804 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 4805 | { |
c19d1205 | 4806 | expressionS exp; |
708587a4 | 4807 | /* This is an arbitrary limit. */ |
c19d1205 ZW |
4808 | unsigned char op[16]; |
4809 | int count; | |
a737bd4d | 4810 | |
921e5f0a | 4811 | if (!unwind.proc_start) |
c921be7d | 4812 | as_bad (MISSING_FNSTART); |
921e5f0a | 4813 | |
c19d1205 ZW |
4814 | expression (&exp); |
4815 | if (exp.X_op == O_constant | |
4816 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 4817 | { |
c19d1205 ZW |
4818 | unwind.frame_size += exp.X_add_number; |
4819 | expression (&exp); | |
4820 | } | |
4821 | else | |
4822 | exp.X_op = O_illegal; | |
a737bd4d | 4823 | |
c19d1205 ZW |
4824 | if (exp.X_op != O_constant) |
4825 | { | |
4826 | as_bad (_("expected <offset>, <opcode>")); | |
4827 | ignore_rest_of_line (); | |
4828 | return; | |
4829 | } | |
a737bd4d | 4830 | |
c19d1205 | 4831 | count = 0; |
a737bd4d | 4832 | |
c19d1205 ZW |
4833 | /* Parse the opcode. */ |
4834 | for (;;) | |
4835 | { | |
4836 | if (count >= 16) | |
4837 | { | |
4838 | as_bad (_("unwind opcode too long")); | |
4839 | ignore_rest_of_line (); | |
a737bd4d | 4840 | } |
c19d1205 | 4841 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 4842 | { |
c19d1205 ZW |
4843 | as_bad (_("invalid unwind opcode")); |
4844 | ignore_rest_of_line (); | |
4845 | return; | |
a737bd4d | 4846 | } |
c19d1205 | 4847 | op[count++] = exp.X_add_number; |
a737bd4d | 4848 | |
c19d1205 ZW |
4849 | /* Parse the next byte. */ |
4850 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
4851 | break; | |
a737bd4d | 4852 | |
c19d1205 ZW |
4853 | expression (&exp); |
4854 | } | |
b99bd4ef | 4855 | |
c19d1205 ZW |
4856 | /* Add the opcode bytes in reverse order. */ |
4857 | while (count--) | |
4858 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 4859 | |
c19d1205 | 4860 | demand_empty_rest_of_line (); |
b99bd4ef | 4861 | } |
ee065d83 PB |
4862 | |
4863 | ||
4864 | /* Parse a .eabi_attribute directive. */ | |
4865 | ||
4866 | static void | |
4867 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) | |
4868 | { | |
0420f52b | 4869 | int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC); |
ee3c0378 | 4870 | |
3076e594 | 4871 | if (tag >= 0 && tag < NUM_KNOWN_OBJ_ATTRIBUTES) |
ee3c0378 | 4872 | attributes_set_explicitly[tag] = 1; |
ee065d83 PB |
4873 | } |
4874 | ||
0855e32b NS |
4875 | /* Emit a tls fix for the symbol. */ |
4876 | ||
4877 | static void | |
4878 | s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED) | |
4879 | { | |
4880 | char *p; | |
4881 | expressionS exp; | |
4882 | #ifdef md_flush_pending_output | |
4883 | md_flush_pending_output (); | |
4884 | #endif | |
4885 | ||
4886 | #ifdef md_cons_align | |
4887 | md_cons_align (4); | |
4888 | #endif | |
4889 | ||
4890 | /* Since we're just labelling the code, there's no need to define a | |
4891 | mapping symbol. */ | |
4892 | expression (&exp); | |
4893 | p = obstack_next_free (&frchain_now->frch_obstack); | |
4894 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0, | |
4895 | thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
4896 | : BFD_RELOC_ARM_TLS_DESCSEQ); | |
4897 | } | |
cdf9ccec | 4898 | #endif /* OBJ_ELF */ |
0855e32b | 4899 | |
ee065d83 | 4900 | static void s_arm_arch (int); |
7a1d4c38 | 4901 | static void s_arm_object_arch (int); |
ee065d83 PB |
4902 | static void s_arm_cpu (int); |
4903 | static void s_arm_fpu (int); | |
69133863 | 4904 | static void s_arm_arch_extension (int); |
b99bd4ef | 4905 | |
f0927246 NC |
4906 | #ifdef TE_PE |
4907 | ||
4908 | static void | |
5f4273c7 | 4909 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
f0927246 NC |
4910 | { |
4911 | expressionS exp; | |
4912 | ||
4913 | do | |
4914 | { | |
4915 | expression (&exp); | |
4916 | if (exp.X_op == O_symbol) | |
4917 | exp.X_op = O_secrel; | |
4918 | ||
4919 | emit_expr (&exp, 4); | |
4920 | } | |
4921 | while (*input_line_pointer++ == ','); | |
4922 | ||
4923 | input_line_pointer--; | |
4924 | demand_empty_rest_of_line (); | |
4925 | } | |
4926 | #endif /* TE_PE */ | |
4927 | ||
c19d1205 ZW |
4928 | /* This table describes all the machine specific pseudo-ops the assembler |
4929 | has to support. The fields are: | |
4930 | pseudo-op name without dot | |
4931 | function to call to execute this pseudo-op | |
4932 | Integer arg to pass to the function. */ | |
b99bd4ef | 4933 | |
c19d1205 | 4934 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 4935 | { |
c19d1205 ZW |
4936 | /* Never called because '.req' does not start a line. */ |
4937 | { "req", s_req, 0 }, | |
dcbf9037 JB |
4938 | /* Following two are likewise never called. */ |
4939 | { "dn", s_dn, 0 }, | |
4940 | { "qn", s_qn, 0 }, | |
c19d1205 ZW |
4941 | { "unreq", s_unreq, 0 }, |
4942 | { "bss", s_bss, 0 }, | |
db2ed2e0 | 4943 | { "align", s_align_ptwo, 2 }, |
c19d1205 ZW |
4944 | { "arm", s_arm, 0 }, |
4945 | { "thumb", s_thumb, 0 }, | |
4946 | { "code", s_code, 0 }, | |
4947 | { "force_thumb", s_force_thumb, 0 }, | |
4948 | { "thumb_func", s_thumb_func, 0 }, | |
4949 | { "thumb_set", s_thumb_set, 0 }, | |
4950 | { "even", s_even, 0 }, | |
4951 | { "ltorg", s_ltorg, 0 }, | |
4952 | { "pool", s_ltorg, 0 }, | |
4953 | { "syntax", s_syntax, 0 }, | |
8463be01 PB |
4954 | { "cpu", s_arm_cpu, 0 }, |
4955 | { "arch", s_arm_arch, 0 }, | |
7a1d4c38 | 4956 | { "object_arch", s_arm_object_arch, 0 }, |
8463be01 | 4957 | { "fpu", s_arm_fpu, 0 }, |
69133863 | 4958 | { "arch_extension", s_arm_arch_extension, 0 }, |
c19d1205 | 4959 | #ifdef OBJ_ELF |
c921be7d NC |
4960 | { "word", s_arm_elf_cons, 4 }, |
4961 | { "long", s_arm_elf_cons, 4 }, | |
4962 | { "inst.n", s_arm_elf_inst, 2 }, | |
4963 | { "inst.w", s_arm_elf_inst, 4 }, | |
4964 | { "inst", s_arm_elf_inst, 0 }, | |
4965 | { "rel31", s_arm_rel31, 0 }, | |
c19d1205 ZW |
4966 | { "fnstart", s_arm_unwind_fnstart, 0 }, |
4967 | { "fnend", s_arm_unwind_fnend, 0 }, | |
4968 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
4969 | { "personality", s_arm_unwind_personality, 0 }, | |
4970 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
4971 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
4972 | { "save", s_arm_unwind_save, 0 }, | |
fa073d69 | 4973 | { "vsave", s_arm_unwind_save, 1 }, |
c19d1205 ZW |
4974 | { "movsp", s_arm_unwind_movsp, 0 }, |
4975 | { "pad", s_arm_unwind_pad, 0 }, | |
4976 | { "setfp", s_arm_unwind_setfp, 0 }, | |
4977 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
ee065d83 | 4978 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, |
0855e32b | 4979 | { "tlsdescseq", s_arm_tls_descseq, 0 }, |
c19d1205 ZW |
4980 | #else |
4981 | { "word", cons, 4}, | |
f0927246 NC |
4982 | |
4983 | /* These are used for dwarf. */ | |
4984 | {"2byte", cons, 2}, | |
4985 | {"4byte", cons, 4}, | |
4986 | {"8byte", cons, 8}, | |
4987 | /* These are used for dwarf2. */ | |
68d20676 | 4988 | { "file", dwarf2_directive_file, 0 }, |
f0927246 NC |
4989 | { "loc", dwarf2_directive_loc, 0 }, |
4990 | { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, | |
c19d1205 ZW |
4991 | #endif |
4992 | { "extend", float_cons, 'x' }, | |
4993 | { "ldouble", float_cons, 'x' }, | |
4994 | { "packed", float_cons, 'p' }, | |
f0927246 NC |
4995 | #ifdef TE_PE |
4996 | {"secrel32", pe_directive_secrel, 0}, | |
4997 | #endif | |
2e6976a8 DG |
4998 | |
4999 | /* These are for compatibility with CodeComposer Studio. */ | |
5000 | {"ref", s_ccs_ref, 0}, | |
5001 | {"def", s_ccs_def, 0}, | |
5002 | {"asmfunc", s_ccs_asmfunc, 0}, | |
5003 | {"endasmfunc", s_ccs_endasmfunc, 0}, | |
5004 | ||
c19d1205 ZW |
5005 | { 0, 0, 0 } |
5006 | }; | |
5007 | \f | |
5008 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 5009 | |
c19d1205 ZW |
5010 | /* Generic immediate-value read function for use in insn parsing. |
5011 | STR points to the beginning of the immediate (the leading #); | |
5012 | VAL receives the value; if the value is outside [MIN, MAX] | |
5013 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
5014 | optional. */ | |
b99bd4ef | 5015 | |
c19d1205 ZW |
5016 | static int |
5017 | parse_immediate (char **str, int *val, int min, int max, | |
5018 | bfd_boolean prefix_opt) | |
5019 | { | |
5020 | expressionS exp; | |
0198d5e6 | 5021 | |
c19d1205 ZW |
5022 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); |
5023 | if (exp.X_op != O_constant) | |
b99bd4ef | 5024 | { |
c19d1205 ZW |
5025 | inst.error = _("constant expression required"); |
5026 | return FAIL; | |
5027 | } | |
b99bd4ef | 5028 | |
c19d1205 ZW |
5029 | if (exp.X_add_number < min || exp.X_add_number > max) |
5030 | { | |
5031 | inst.error = _("immediate value out of range"); | |
5032 | return FAIL; | |
5033 | } | |
b99bd4ef | 5034 | |
c19d1205 ZW |
5035 | *val = exp.X_add_number; |
5036 | return SUCCESS; | |
5037 | } | |
b99bd4ef | 5038 | |
5287ad62 | 5039 | /* Less-generic immediate-value read function with the possibility of loading a |
036dc3f7 | 5040 | big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate |
5287ad62 JB |
5041 | instructions. Puts the result directly in inst.operands[i]. */ |
5042 | ||
5043 | static int | |
8335d6aa JW |
5044 | parse_big_immediate (char **str, int i, expressionS *in_exp, |
5045 | bfd_boolean allow_symbol_p) | |
5287ad62 JB |
5046 | { |
5047 | expressionS exp; | |
8335d6aa | 5048 | expressionS *exp_p = in_exp ? in_exp : &exp; |
5287ad62 JB |
5049 | char *ptr = *str; |
5050 | ||
8335d6aa | 5051 | my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG); |
5287ad62 | 5052 | |
8335d6aa | 5053 | if (exp_p->X_op == O_constant) |
036dc3f7 | 5054 | { |
8335d6aa | 5055 | inst.operands[i].imm = exp_p->X_add_number & 0xffffffff; |
036dc3f7 PB |
5056 | /* If we're on a 64-bit host, then a 64-bit number can be returned using |
5057 | O_constant. We have to be careful not to break compilation for | |
5058 | 32-bit X_add_number, though. */ | |
8335d6aa | 5059 | if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0) |
036dc3f7 | 5060 | { |
8335d6aa JW |
5061 | /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */ |
5062 | inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16) | |
5063 | & 0xffffffff); | |
036dc3f7 PB |
5064 | inst.operands[i].regisimm = 1; |
5065 | } | |
5066 | } | |
8335d6aa JW |
5067 | else if (exp_p->X_op == O_big |
5068 | && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32) | |
5287ad62 JB |
5069 | { |
5070 | unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; | |
95b75c01 | 5071 | |
5287ad62 | 5072 | /* Bignums have their least significant bits in |
477330fc RM |
5073 | generic_bignum[0]. Make sure we put 32 bits in imm and |
5074 | 32 bits in reg, in a (hopefully) portable way. */ | |
9c2799c2 | 5075 | gas_assert (parts != 0); |
95b75c01 NC |
5076 | |
5077 | /* Make sure that the number is not too big. | |
5078 | PR 11972: Bignums can now be sign-extended to the | |
5079 | size of a .octa so check that the out of range bits | |
5080 | are all zero or all one. */ | |
8335d6aa | 5081 | if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64) |
95b75c01 NC |
5082 | { |
5083 | LITTLENUM_TYPE m = -1; | |
5084 | ||
5085 | if (generic_bignum[parts * 2] != 0 | |
5086 | && generic_bignum[parts * 2] != m) | |
5087 | return FAIL; | |
5088 | ||
8335d6aa | 5089 | for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++) |
95b75c01 NC |
5090 | if (generic_bignum[j] != generic_bignum[j-1]) |
5091 | return FAIL; | |
5092 | } | |
5093 | ||
5287ad62 JB |
5094 | inst.operands[i].imm = 0; |
5095 | for (j = 0; j < parts; j++, idx++) | |
477330fc RM |
5096 | inst.operands[i].imm |= generic_bignum[idx] |
5097 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
5287ad62 JB |
5098 | inst.operands[i].reg = 0; |
5099 | for (j = 0; j < parts; j++, idx++) | |
477330fc RM |
5100 | inst.operands[i].reg |= generic_bignum[idx] |
5101 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
5287ad62 JB |
5102 | inst.operands[i].regisimm = 1; |
5103 | } | |
8335d6aa | 5104 | else if (!(exp_p->X_op == O_symbol && allow_symbol_p)) |
5287ad62 | 5105 | return FAIL; |
5f4273c7 | 5106 | |
5287ad62 JB |
5107 | *str = ptr; |
5108 | ||
5109 | return SUCCESS; | |
5110 | } | |
5111 | ||
c19d1205 ZW |
5112 | /* Returns the pseudo-register number of an FPA immediate constant, |
5113 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 5114 | |
c19d1205 ZW |
5115 | static int |
5116 | parse_fpa_immediate (char ** str) | |
5117 | { | |
5118 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
5119 | char * save_in; | |
5120 | expressionS exp; | |
5121 | int i; | |
5122 | int j; | |
b99bd4ef | 5123 | |
c19d1205 ZW |
5124 | /* First try and match exact strings, this is to guarantee |
5125 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 5126 | |
c19d1205 ZW |
5127 | for (i = 0; fp_const[i]; i++) |
5128 | { | |
5129 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 5130 | { |
c19d1205 | 5131 | char *start = *str; |
b99bd4ef | 5132 | |
c19d1205 ZW |
5133 | *str += strlen (fp_const[i]); |
5134 | if (is_end_of_line[(unsigned char) **str]) | |
5135 | return i + 8; | |
5136 | *str = start; | |
5137 | } | |
5138 | } | |
b99bd4ef | 5139 | |
c19d1205 ZW |
5140 | /* Just because we didn't get a match doesn't mean that the constant |
5141 | isn't valid, just that it is in a format that we don't | |
5142 | automatically recognize. Try parsing it with the standard | |
5143 | expression routines. */ | |
b99bd4ef | 5144 | |
c19d1205 | 5145 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 5146 | |
c19d1205 ZW |
5147 | /* Look for a raw floating point number. */ |
5148 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
5149 | && is_end_of_line[(unsigned char) *save_in]) | |
5150 | { | |
5151 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
5152 | { | |
5153 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 5154 | { |
c19d1205 ZW |
5155 | if (words[j] != fp_values[i][j]) |
5156 | break; | |
b99bd4ef NC |
5157 | } |
5158 | ||
c19d1205 | 5159 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 5160 | { |
c19d1205 ZW |
5161 | *str = save_in; |
5162 | return i + 8; | |
b99bd4ef NC |
5163 | } |
5164 | } | |
5165 | } | |
b99bd4ef | 5166 | |
c19d1205 ZW |
5167 | /* Try and parse a more complex expression, this will probably fail |
5168 | unless the code uses a floating point prefix (eg "0f"). */ | |
5169 | save_in = input_line_pointer; | |
5170 | input_line_pointer = *str; | |
5171 | if (expression (&exp) == absolute_section | |
5172 | && exp.X_op == O_big | |
5173 | && exp.X_add_number < 0) | |
5174 | { | |
5175 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
5176 | Ditto for 15. */ | |
ba592044 AM |
5177 | #define X_PRECISION 5 |
5178 | #define E_PRECISION 15L | |
5179 | if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0) | |
c19d1205 ZW |
5180 | { |
5181 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
5182 | { | |
5183 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
5184 | { | |
5185 | if (words[j] != fp_values[i][j]) | |
5186 | break; | |
5187 | } | |
b99bd4ef | 5188 | |
c19d1205 ZW |
5189 | if (j == MAX_LITTLENUMS) |
5190 | { | |
5191 | *str = input_line_pointer; | |
5192 | input_line_pointer = save_in; | |
5193 | return i + 8; | |
5194 | } | |
5195 | } | |
5196 | } | |
b99bd4ef NC |
5197 | } |
5198 | ||
c19d1205 ZW |
5199 | *str = input_line_pointer; |
5200 | input_line_pointer = save_in; | |
5201 | inst.error = _("invalid FPA immediate expression"); | |
5202 | return FAIL; | |
b99bd4ef NC |
5203 | } |
5204 | ||
136da414 JB |
5205 | /* Returns 1 if a number has "quarter-precision" float format |
5206 | 0baBbbbbbc defgh000 00000000 00000000. */ | |
5207 | ||
5208 | static int | |
5209 | is_quarter_float (unsigned imm) | |
5210 | { | |
5211 | int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; | |
5212 | return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; | |
5213 | } | |
5214 | ||
aacf0b33 KT |
5215 | |
5216 | /* Detect the presence of a floating point or integer zero constant, | |
5217 | i.e. #0.0 or #0. */ | |
5218 | ||
5219 | static bfd_boolean | |
5220 | parse_ifimm_zero (char **in) | |
5221 | { | |
5222 | int error_code; | |
5223 | ||
5224 | if (!is_immediate_prefix (**in)) | |
3c6452ae TP |
5225 | { |
5226 | /* In unified syntax, all prefixes are optional. */ | |
5227 | if (!unified_syntax) | |
5228 | return FALSE; | |
5229 | } | |
5230 | else | |
5231 | ++*in; | |
0900a05b JW |
5232 | |
5233 | /* Accept #0x0 as a synonym for #0. */ | |
5234 | if (strncmp (*in, "0x", 2) == 0) | |
5235 | { | |
5236 | int val; | |
5237 | if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL) | |
5238 | return FALSE; | |
5239 | return TRUE; | |
5240 | } | |
5241 | ||
aacf0b33 KT |
5242 | error_code = atof_generic (in, ".", EXP_CHARS, |
5243 | &generic_floating_point_number); | |
5244 | ||
5245 | if (!error_code | |
5246 | && generic_floating_point_number.sign == '+' | |
5247 | && (generic_floating_point_number.low | |
5248 | > generic_floating_point_number.leader)) | |
5249 | return TRUE; | |
5250 | ||
5251 | return FALSE; | |
5252 | } | |
5253 | ||
136da414 JB |
5254 | /* Parse an 8-bit "quarter-precision" floating point number of the form: |
5255 | 0baBbbbbbc defgh000 00000000 00000000. | |
c96612cc JB |
5256 | The zero and minus-zero cases need special handling, since they can't be |
5257 | encoded in the "quarter-precision" float format, but can nonetheless be | |
5258 | loaded as integer constants. */ | |
136da414 JB |
5259 | |
5260 | static unsigned | |
5261 | parse_qfloat_immediate (char **ccp, int *immed) | |
5262 | { | |
5263 | char *str = *ccp; | |
c96612cc | 5264 | char *fpnum; |
136da414 | 5265 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
c96612cc | 5266 | int found_fpchar = 0; |
5f4273c7 | 5267 | |
136da414 | 5268 | skip_past_char (&str, '#'); |
5f4273c7 | 5269 | |
c96612cc JB |
5270 | /* We must not accidentally parse an integer as a floating-point number. Make |
5271 | sure that the value we parse is not an integer by checking for special | |
5272 | characters '.' or 'e'. | |
5273 | FIXME: This is a horrible hack, but doing better is tricky because type | |
5274 | information isn't in a very usable state at parse time. */ | |
5275 | fpnum = str; | |
5276 | skip_whitespace (fpnum); | |
5277 | ||
5278 | if (strncmp (fpnum, "0x", 2) == 0) | |
5279 | return FAIL; | |
5280 | else | |
5281 | { | |
5282 | for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) | |
477330fc RM |
5283 | if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') |
5284 | { | |
5285 | found_fpchar = 1; | |
5286 | break; | |
5287 | } | |
c96612cc JB |
5288 | |
5289 | if (!found_fpchar) | |
477330fc | 5290 | return FAIL; |
c96612cc | 5291 | } |
5f4273c7 | 5292 | |
136da414 JB |
5293 | if ((str = atof_ieee (str, 's', words)) != NULL) |
5294 | { | |
5295 | unsigned fpword = 0; | |
5296 | int i; | |
5f4273c7 | 5297 | |
136da414 JB |
5298 | /* Our FP word must be 32 bits (single-precision FP). */ |
5299 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) | |
477330fc RM |
5300 | { |
5301 | fpword <<= LITTLENUM_NUMBER_OF_BITS; | |
5302 | fpword |= words[i]; | |
5303 | } | |
5f4273c7 | 5304 | |
c96612cc | 5305 | if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) |
477330fc | 5306 | *immed = fpword; |
136da414 | 5307 | else |
477330fc | 5308 | return FAIL; |
136da414 JB |
5309 | |
5310 | *ccp = str; | |
5f4273c7 | 5311 | |
136da414 JB |
5312 | return SUCCESS; |
5313 | } | |
5f4273c7 | 5314 | |
136da414 JB |
5315 | return FAIL; |
5316 | } | |
5317 | ||
c19d1205 ZW |
5318 | /* Shift operands. */ |
5319 | enum shift_kind | |
b99bd4ef | 5320 | { |
f5f10c66 | 5321 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX, SHIFT_UXTW |
c19d1205 | 5322 | }; |
b99bd4ef | 5323 | |
c19d1205 ZW |
5324 | struct asm_shift_name |
5325 | { | |
5326 | const char *name; | |
5327 | enum shift_kind kind; | |
5328 | }; | |
b99bd4ef | 5329 | |
c19d1205 ZW |
5330 | /* Third argument to parse_shift. */ |
5331 | enum parse_shift_mode | |
5332 | { | |
5333 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
5334 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
5335 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
5336 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
5337 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
f5f10c66 | 5338 | SHIFT_UXTW_IMMEDIATE /* Shift must be UXTW immediate. */ |
c19d1205 | 5339 | }; |
b99bd4ef | 5340 | |
c19d1205 ZW |
5341 | /* Parse a <shift> specifier on an ARM data processing instruction. |
5342 | This has three forms: | |
b99bd4ef | 5343 | |
c19d1205 ZW |
5344 | (LSL|LSR|ASL|ASR|ROR) Rs |
5345 | (LSL|LSR|ASL|ASR|ROR) #imm | |
5346 | RRX | |
b99bd4ef | 5347 | |
c19d1205 ZW |
5348 | Note that ASL is assimilated to LSL in the instruction encoding, and |
5349 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 5350 | |
c19d1205 ZW |
5351 | static int |
5352 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 5353 | { |
c19d1205 ZW |
5354 | const struct asm_shift_name *shift_name; |
5355 | enum shift_kind shift; | |
5356 | char *s = *str; | |
5357 | char *p = s; | |
5358 | int reg; | |
b99bd4ef | 5359 | |
c19d1205 ZW |
5360 | for (p = *str; ISALPHA (*p); p++) |
5361 | ; | |
b99bd4ef | 5362 | |
c19d1205 | 5363 | if (p == *str) |
b99bd4ef | 5364 | { |
c19d1205 ZW |
5365 | inst.error = _("shift expression expected"); |
5366 | return FAIL; | |
b99bd4ef NC |
5367 | } |
5368 | ||
21d799b5 | 5369 | shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str, |
477330fc | 5370 | p - *str); |
c19d1205 ZW |
5371 | |
5372 | if (shift_name == NULL) | |
b99bd4ef | 5373 | { |
c19d1205 ZW |
5374 | inst.error = _("shift expression expected"); |
5375 | return FAIL; | |
b99bd4ef NC |
5376 | } |
5377 | ||
c19d1205 | 5378 | shift = shift_name->kind; |
b99bd4ef | 5379 | |
c19d1205 ZW |
5380 | switch (mode) |
5381 | { | |
5382 | case NO_SHIFT_RESTRICT: | |
f5f10c66 AV |
5383 | case SHIFT_IMMEDIATE: |
5384 | if (shift == SHIFT_UXTW) | |
5385 | { | |
5386 | inst.error = _("'UXTW' not allowed here"); | |
5387 | return FAIL; | |
5388 | } | |
5389 | break; | |
b99bd4ef | 5390 | |
c19d1205 ZW |
5391 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
5392 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
5393 | { | |
5394 | inst.error = _("'LSL' or 'ASR' required"); | |
5395 | return FAIL; | |
5396 | } | |
5397 | break; | |
b99bd4ef | 5398 | |
c19d1205 ZW |
5399 | case SHIFT_LSL_IMMEDIATE: |
5400 | if (shift != SHIFT_LSL) | |
5401 | { | |
5402 | inst.error = _("'LSL' required"); | |
5403 | return FAIL; | |
5404 | } | |
5405 | break; | |
b99bd4ef | 5406 | |
c19d1205 ZW |
5407 | case SHIFT_ASR_IMMEDIATE: |
5408 | if (shift != SHIFT_ASR) | |
5409 | { | |
5410 | inst.error = _("'ASR' required"); | |
5411 | return FAIL; | |
5412 | } | |
5413 | break; | |
f5f10c66 AV |
5414 | case SHIFT_UXTW_IMMEDIATE: |
5415 | if (shift != SHIFT_UXTW) | |
5416 | { | |
5417 | inst.error = _("'UXTW' required"); | |
5418 | return FAIL; | |
5419 | } | |
5420 | break; | |
b99bd4ef | 5421 | |
c19d1205 ZW |
5422 | default: abort (); |
5423 | } | |
b99bd4ef | 5424 | |
c19d1205 ZW |
5425 | if (shift != SHIFT_RRX) |
5426 | { | |
5427 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
5428 | skip_whitespace (p); | |
b99bd4ef | 5429 | |
c19d1205 | 5430 | if (mode == NO_SHIFT_RESTRICT |
dcbf9037 | 5431 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
5432 | { |
5433 | inst.operands[i].imm = reg; | |
5434 | inst.operands[i].immisreg = 1; | |
5435 | } | |
e2b0ab59 | 5436 | else if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX)) |
c19d1205 ZW |
5437 | return FAIL; |
5438 | } | |
5439 | inst.operands[i].shift_kind = shift; | |
5440 | inst.operands[i].shifted = 1; | |
5441 | *str = p; | |
5442 | return SUCCESS; | |
b99bd4ef NC |
5443 | } |
5444 | ||
c19d1205 | 5445 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 5446 | |
c19d1205 ZW |
5447 | #<immediate> |
5448 | #<immediate>, <rotate> | |
5449 | <Rm> | |
5450 | <Rm>, <shift> | |
b99bd4ef | 5451 | |
c19d1205 ZW |
5452 | where <shift> is defined by parse_shift above, and <rotate> is a |
5453 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 5454 | is deferred to md_apply_fix. */ |
b99bd4ef | 5455 | |
c19d1205 ZW |
5456 | static int |
5457 | parse_shifter_operand (char **str, int i) | |
5458 | { | |
5459 | int value; | |
91d6fa6a | 5460 | expressionS exp; |
b99bd4ef | 5461 | |
dcbf9037 | 5462 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
5463 | { |
5464 | inst.operands[i].reg = value; | |
5465 | inst.operands[i].isreg = 1; | |
b99bd4ef | 5466 | |
c19d1205 | 5467 | /* parse_shift will override this if appropriate */ |
e2b0ab59 AV |
5468 | inst.relocs[0].exp.X_op = O_constant; |
5469 | inst.relocs[0].exp.X_add_number = 0; | |
b99bd4ef | 5470 | |
c19d1205 ZW |
5471 | if (skip_past_comma (str) == FAIL) |
5472 | return SUCCESS; | |
b99bd4ef | 5473 | |
c19d1205 ZW |
5474 | /* Shift operation on register. */ |
5475 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
5476 | } |
5477 | ||
e2b0ab59 | 5478 | if (my_get_expression (&inst.relocs[0].exp, str, GE_IMM_PREFIX)) |
c19d1205 | 5479 | return FAIL; |
b99bd4ef | 5480 | |
c19d1205 | 5481 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 5482 | { |
c19d1205 | 5483 | /* #x, y -- ie explicit rotation by Y. */ |
91d6fa6a | 5484 | if (my_get_expression (&exp, str, GE_NO_PREFIX)) |
c19d1205 | 5485 | return FAIL; |
b99bd4ef | 5486 | |
e2b0ab59 | 5487 | if (exp.X_op != O_constant || inst.relocs[0].exp.X_op != O_constant) |
c19d1205 ZW |
5488 | { |
5489 | inst.error = _("constant expression expected"); | |
5490 | return FAIL; | |
5491 | } | |
b99bd4ef | 5492 | |
91d6fa6a | 5493 | value = exp.X_add_number; |
c19d1205 ZW |
5494 | if (value < 0 || value > 30 || value % 2 != 0) |
5495 | { | |
5496 | inst.error = _("invalid rotation"); | |
5497 | return FAIL; | |
5498 | } | |
e2b0ab59 AV |
5499 | if (inst.relocs[0].exp.X_add_number < 0 |
5500 | || inst.relocs[0].exp.X_add_number > 255) | |
c19d1205 ZW |
5501 | { |
5502 | inst.error = _("invalid constant"); | |
5503 | return FAIL; | |
5504 | } | |
09d92015 | 5505 | |
a415b1cd | 5506 | /* Encode as specified. */ |
e2b0ab59 | 5507 | inst.operands[i].imm = inst.relocs[0].exp.X_add_number | value << 7; |
a415b1cd | 5508 | return SUCCESS; |
09d92015 MM |
5509 | } |
5510 | ||
e2b0ab59 AV |
5511 | inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE; |
5512 | inst.relocs[0].pc_rel = 0; | |
c19d1205 | 5513 | return SUCCESS; |
09d92015 MM |
5514 | } |
5515 | ||
4962c51a MS |
5516 | /* Group relocation information. Each entry in the table contains the |
5517 | textual name of the relocation as may appear in assembler source | |
5518 | and must end with a colon. | |
5519 | Along with this textual name are the relocation codes to be used if | |
5520 | the corresponding instruction is an ALU instruction (ADD or SUB only), | |
5521 | an LDR, an LDRS, or an LDC. */ | |
5522 | ||
5523 | struct group_reloc_table_entry | |
5524 | { | |
5525 | const char *name; | |
5526 | int alu_code; | |
5527 | int ldr_code; | |
5528 | int ldrs_code; | |
5529 | int ldc_code; | |
5530 | }; | |
5531 | ||
5532 | typedef enum | |
5533 | { | |
5534 | /* Varieties of non-ALU group relocation. */ | |
5535 | ||
5536 | GROUP_LDR, | |
5537 | GROUP_LDRS, | |
35c228db AV |
5538 | GROUP_LDC, |
5539 | GROUP_MVE | |
4962c51a MS |
5540 | } group_reloc_type; |
5541 | ||
5542 | static struct group_reloc_table_entry group_reloc_table[] = | |
5543 | { /* Program counter relative: */ | |
5544 | { "pc_g0_nc", | |
5545 | BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ | |
5546 | 0, /* LDR */ | |
5547 | 0, /* LDRS */ | |
5548 | 0 }, /* LDC */ | |
5549 | { "pc_g0", | |
5550 | BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ | |
5551 | BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ | |
5552 | BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ | |
5553 | BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ | |
5554 | { "pc_g1_nc", | |
5555 | BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ | |
5556 | 0, /* LDR */ | |
5557 | 0, /* LDRS */ | |
5558 | 0 }, /* LDC */ | |
5559 | { "pc_g1", | |
5560 | BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ | |
5561 | BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ | |
5562 | BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ | |
5563 | BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ | |
5564 | { "pc_g2", | |
5565 | BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ | |
5566 | BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ | |
5567 | BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ | |
5568 | BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ | |
5569 | /* Section base relative */ | |
5570 | { "sb_g0_nc", | |
5571 | BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ | |
5572 | 0, /* LDR */ | |
5573 | 0, /* LDRS */ | |
5574 | 0 }, /* LDC */ | |
5575 | { "sb_g0", | |
5576 | BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ | |
5577 | BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ | |
5578 | BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ | |
5579 | BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ | |
5580 | { "sb_g1_nc", | |
5581 | BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ | |
5582 | 0, /* LDR */ | |
5583 | 0, /* LDRS */ | |
5584 | 0 }, /* LDC */ | |
5585 | { "sb_g1", | |
5586 | BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ | |
5587 | BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ | |
5588 | BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ | |
5589 | BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ | |
5590 | { "sb_g2", | |
5591 | BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ | |
5592 | BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ | |
5593 | BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ | |
72d98d16 MG |
5594 | BFD_RELOC_ARM_LDC_SB_G2 }, /* LDC */ |
5595 | /* Absolute thumb alu relocations. */ | |
5596 | { "lower0_7", | |
5597 | BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC,/* ALU. */ | |
5598 | 0, /* LDR. */ | |
5599 | 0, /* LDRS. */ | |
5600 | 0 }, /* LDC. */ | |
5601 | { "lower8_15", | |
5602 | BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC,/* ALU. */ | |
5603 | 0, /* LDR. */ | |
5604 | 0, /* LDRS. */ | |
5605 | 0 }, /* LDC. */ | |
5606 | { "upper0_7", | |
5607 | BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC,/* ALU. */ | |
5608 | 0, /* LDR. */ | |
5609 | 0, /* LDRS. */ | |
5610 | 0 }, /* LDC. */ | |
5611 | { "upper8_15", | |
5612 | BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC,/* ALU. */ | |
5613 | 0, /* LDR. */ | |
5614 | 0, /* LDRS. */ | |
5615 | 0 } }; /* LDC. */ | |
4962c51a MS |
5616 | |
5617 | /* Given the address of a pointer pointing to the textual name of a group | |
5618 | relocation as may appear in assembler source, attempt to find its details | |
5619 | in group_reloc_table. The pointer will be updated to the character after | |
5620 | the trailing colon. On failure, FAIL will be returned; SUCCESS | |
5621 | otherwise. On success, *entry will be updated to point at the relevant | |
5622 | group_reloc_table entry. */ | |
5623 | ||
5624 | static int | |
5625 | find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) | |
5626 | { | |
5627 | unsigned int i; | |
5628 | for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) | |
5629 | { | |
5630 | int length = strlen (group_reloc_table[i].name); | |
5631 | ||
5f4273c7 NC |
5632 | if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 |
5633 | && (*str)[length] == ':') | |
477330fc RM |
5634 | { |
5635 | *out = &group_reloc_table[i]; | |
5636 | *str += (length + 1); | |
5637 | return SUCCESS; | |
5638 | } | |
4962c51a MS |
5639 | } |
5640 | ||
5641 | return FAIL; | |
5642 | } | |
5643 | ||
5644 | /* Parse a <shifter_operand> for an ARM data processing instruction | |
5645 | (as for parse_shifter_operand) where group relocations are allowed: | |
5646 | ||
5647 | #<immediate> | |
5648 | #<immediate>, <rotate> | |
5649 | #:<group_reloc>:<expression> | |
5650 | <Rm> | |
5651 | <Rm>, <shift> | |
5652 | ||
5653 | where <group_reloc> is one of the strings defined in group_reloc_table. | |
5654 | The hashes are optional. | |
5655 | ||
5656 | Everything else is as for parse_shifter_operand. */ | |
5657 | ||
5658 | static parse_operand_result | |
5659 | parse_shifter_operand_group_reloc (char **str, int i) | |
5660 | { | |
5661 | /* Determine if we have the sequence of characters #: or just : | |
5662 | coming next. If we do, then we check for a group relocation. | |
5663 | If we don't, punt the whole lot to parse_shifter_operand. */ | |
5664 | ||
5665 | if (((*str)[0] == '#' && (*str)[1] == ':') | |
5666 | || (*str)[0] == ':') | |
5667 | { | |
5668 | struct group_reloc_table_entry *entry; | |
5669 | ||
5670 | if ((*str)[0] == '#') | |
477330fc | 5671 | (*str) += 2; |
4962c51a | 5672 | else |
477330fc | 5673 | (*str)++; |
4962c51a MS |
5674 | |
5675 | /* Try to parse a group relocation. Anything else is an error. */ | |
5676 | if (find_group_reloc_table_entry (str, &entry) == FAIL) | |
477330fc RM |
5677 | { |
5678 | inst.error = _("unknown group relocation"); | |
5679 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5680 | } | |
4962c51a MS |
5681 | |
5682 | /* We now have the group relocation table entry corresponding to | |
477330fc | 5683 | the name in the assembler source. Next, we parse the expression. */ |
e2b0ab59 | 5684 | if (my_get_expression (&inst.relocs[0].exp, str, GE_NO_PREFIX)) |
477330fc | 5685 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; |
4962c51a MS |
5686 | |
5687 | /* Record the relocation type (always the ALU variant here). */ | |
e2b0ab59 AV |
5688 | inst.relocs[0].type = (bfd_reloc_code_real_type) entry->alu_code; |
5689 | gas_assert (inst.relocs[0].type != 0); | |
4962c51a MS |
5690 | |
5691 | return PARSE_OPERAND_SUCCESS; | |
5692 | } | |
5693 | else | |
5694 | return parse_shifter_operand (str, i) == SUCCESS | |
477330fc | 5695 | ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; |
4962c51a MS |
5696 | |
5697 | /* Never reached. */ | |
5698 | } | |
5699 | ||
8e560766 MGD |
5700 | /* Parse a Neon alignment expression. Information is written to |
5701 | inst.operands[i]. We assume the initial ':' has been skipped. | |
fa94de6b | 5702 | |
8e560766 MGD |
5703 | align .imm = align << 8, .immisalign=1, .preind=0 */ |
5704 | static parse_operand_result | |
5705 | parse_neon_alignment (char **str, int i) | |
5706 | { | |
5707 | char *p = *str; | |
5708 | expressionS exp; | |
5709 | ||
5710 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
5711 | ||
5712 | if (exp.X_op != O_constant) | |
5713 | { | |
5714 | inst.error = _("alignment must be constant"); | |
5715 | return PARSE_OPERAND_FAIL; | |
5716 | } | |
5717 | ||
5718 | inst.operands[i].imm = exp.X_add_number << 8; | |
5719 | inst.operands[i].immisalign = 1; | |
5720 | /* Alignments are not pre-indexes. */ | |
5721 | inst.operands[i].preind = 0; | |
5722 | ||
5723 | *str = p; | |
5724 | return PARSE_OPERAND_SUCCESS; | |
5725 | } | |
5726 | ||
c19d1205 | 5727 | /* Parse all forms of an ARM address expression. Information is written |
e2b0ab59 | 5728 | to inst.operands[i] and/or inst.relocs[0]. |
09d92015 | 5729 | |
c19d1205 | 5730 | Preindexed addressing (.preind=1): |
09d92015 | 5731 | |
e2b0ab59 | 5732 | [Rn, #offset] .reg=Rn .relocs[0].exp=offset |
c19d1205 ZW |
5733 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 |
5734 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
e2b0ab59 | 5735 | .shift_kind=shift .relocs[0].exp=shift_imm |
09d92015 | 5736 | |
c19d1205 | 5737 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 5738 | |
c19d1205 | 5739 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 5740 | |
e2b0ab59 | 5741 | [Rn], #offset .reg=Rn .relocs[0].exp=offset |
c19d1205 ZW |
5742 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 |
5743 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
e2b0ab59 | 5744 | .shift_kind=shift .relocs[0].exp=shift_imm |
09d92015 | 5745 | |
c19d1205 | 5746 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 5747 | |
c19d1205 | 5748 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 5749 | |
c19d1205 | 5750 | Other: |
09d92015 | 5751 | |
c19d1205 | 5752 | [Rn]{!} shorthand for [Rn,#0]{!} |
e2b0ab59 AV |
5753 | =immediate .isreg=0 .relocs[0].exp=immediate |
5754 | label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label | |
09d92015 | 5755 | |
c19d1205 | 5756 | It is the caller's responsibility to check for addressing modes not |
e2b0ab59 | 5757 | supported by the instruction, and to set inst.relocs[0].type. */ |
c19d1205 | 5758 | |
4962c51a MS |
5759 | static parse_operand_result |
5760 | parse_address_main (char **str, int i, int group_relocations, | |
477330fc | 5761 | group_reloc_type group_type) |
09d92015 | 5762 | { |
c19d1205 ZW |
5763 | char *p = *str; |
5764 | int reg; | |
09d92015 | 5765 | |
c19d1205 | 5766 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 5767 | { |
c19d1205 ZW |
5768 | if (skip_past_char (&p, '=') == FAIL) |
5769 | { | |
974da60d | 5770 | /* Bare address - translate to PC-relative offset. */ |
e2b0ab59 | 5771 | inst.relocs[0].pc_rel = 1; |
c19d1205 ZW |
5772 | inst.operands[i].reg = REG_PC; |
5773 | inst.operands[i].isreg = 1; | |
5774 | inst.operands[i].preind = 1; | |
09d92015 | 5775 | |
e2b0ab59 | 5776 | if (my_get_expression (&inst.relocs[0].exp, &p, GE_OPT_PREFIX_BIG)) |
8335d6aa JW |
5777 | return PARSE_OPERAND_FAIL; |
5778 | } | |
e2b0ab59 | 5779 | else if (parse_big_immediate (&p, i, &inst.relocs[0].exp, |
8335d6aa | 5780 | /*allow_symbol_p=*/TRUE)) |
4962c51a | 5781 | return PARSE_OPERAND_FAIL; |
09d92015 | 5782 | |
c19d1205 | 5783 | *str = p; |
4962c51a | 5784 | return PARSE_OPERAND_SUCCESS; |
09d92015 MM |
5785 | } |
5786 | ||
8ab8155f NC |
5787 | /* PR gas/14887: Allow for whitespace after the opening bracket. */ |
5788 | skip_whitespace (p); | |
5789 | ||
f5f10c66 AV |
5790 | if (group_type == GROUP_MVE) |
5791 | { | |
5792 | enum arm_reg_type rtype = REG_TYPE_MQ; | |
5793 | struct neon_type_el et; | |
5794 | if ((reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL) | |
5795 | { | |
5796 | inst.operands[i].isquad = 1; | |
5797 | } | |
5798 | else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) | |
5799 | { | |
5800 | inst.error = BAD_ADDR_MODE; | |
5801 | return PARSE_OPERAND_FAIL; | |
5802 | } | |
5803 | } | |
5804 | else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) | |
09d92015 | 5805 | { |
35c228db AV |
5806 | if (group_type == GROUP_MVE) |
5807 | inst.error = BAD_ADDR_MODE; | |
5808 | else | |
5809 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
4962c51a | 5810 | return PARSE_OPERAND_FAIL; |
09d92015 | 5811 | } |
c19d1205 ZW |
5812 | inst.operands[i].reg = reg; |
5813 | inst.operands[i].isreg = 1; | |
09d92015 | 5814 | |
c19d1205 | 5815 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5816 | { |
c19d1205 | 5817 | inst.operands[i].preind = 1; |
09d92015 | 5818 | |
c19d1205 ZW |
5819 | if (*p == '+') p++; |
5820 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
5821 | ||
f5f10c66 AV |
5822 | enum arm_reg_type rtype = REG_TYPE_MQ; |
5823 | struct neon_type_el et; | |
5824 | if (group_type == GROUP_MVE | |
5825 | && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL) | |
5826 | { | |
5827 | inst.operands[i].immisreg = 2; | |
5828 | inst.operands[i].imm = reg; | |
5829 | ||
5830 | if (skip_past_comma (&p) == SUCCESS) | |
5831 | { | |
5832 | if (parse_shift (&p, i, SHIFT_UXTW_IMMEDIATE) == SUCCESS) | |
5833 | { | |
5834 | inst.operands[i].imm |= inst.relocs[0].exp.X_add_number << 5; | |
5835 | inst.relocs[0].exp.X_add_number = 0; | |
5836 | } | |
5837 | else | |
5838 | return PARSE_OPERAND_FAIL; | |
5839 | } | |
5840 | } | |
5841 | else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) | |
09d92015 | 5842 | { |
c19d1205 ZW |
5843 | inst.operands[i].imm = reg; |
5844 | inst.operands[i].immisreg = 1; | |
5845 | ||
5846 | if (skip_past_comma (&p) == SUCCESS) | |
5847 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5848 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5849 | } |
5287ad62 | 5850 | else if (skip_past_char (&p, ':') == SUCCESS) |
8e560766 MGD |
5851 | { |
5852 | /* FIXME: '@' should be used here, but it's filtered out by generic | |
5853 | code before we get to see it here. This may be subject to | |
5854 | change. */ | |
5855 | parse_operand_result result = parse_neon_alignment (&p, i); | |
fa94de6b | 5856 | |
8e560766 MGD |
5857 | if (result != PARSE_OPERAND_SUCCESS) |
5858 | return result; | |
5859 | } | |
c19d1205 ZW |
5860 | else |
5861 | { | |
5862 | if (inst.operands[i].negative) | |
5863 | { | |
5864 | inst.operands[i].negative = 0; | |
5865 | p--; | |
5866 | } | |
4962c51a | 5867 | |
5f4273c7 NC |
5868 | if (group_relocations |
5869 | && ((*p == '#' && *(p + 1) == ':') || *p == ':')) | |
4962c51a MS |
5870 | { |
5871 | struct group_reloc_table_entry *entry; | |
5872 | ||
477330fc RM |
5873 | /* Skip over the #: or : sequence. */ |
5874 | if (*p == '#') | |
5875 | p += 2; | |
5876 | else | |
5877 | p++; | |
4962c51a MS |
5878 | |
5879 | /* Try to parse a group relocation. Anything else is an | |
477330fc | 5880 | error. */ |
4962c51a MS |
5881 | if (find_group_reloc_table_entry (&p, &entry) == FAIL) |
5882 | { | |
5883 | inst.error = _("unknown group relocation"); | |
5884 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5885 | } | |
5886 | ||
5887 | /* We now have the group relocation table entry corresponding to | |
5888 | the name in the assembler source. Next, we parse the | |
477330fc | 5889 | expression. */ |
e2b0ab59 | 5890 | if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX)) |
4962c51a MS |
5891 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; |
5892 | ||
5893 | /* Record the relocation type. */ | |
477330fc RM |
5894 | switch (group_type) |
5895 | { | |
5896 | case GROUP_LDR: | |
e2b0ab59 AV |
5897 | inst.relocs[0].type |
5898 | = (bfd_reloc_code_real_type) entry->ldr_code; | |
477330fc | 5899 | break; |
4962c51a | 5900 | |
477330fc | 5901 | case GROUP_LDRS: |
e2b0ab59 AV |
5902 | inst.relocs[0].type |
5903 | = (bfd_reloc_code_real_type) entry->ldrs_code; | |
477330fc | 5904 | break; |
4962c51a | 5905 | |
477330fc | 5906 | case GROUP_LDC: |
e2b0ab59 AV |
5907 | inst.relocs[0].type |
5908 | = (bfd_reloc_code_real_type) entry->ldc_code; | |
477330fc | 5909 | break; |
4962c51a | 5910 | |
477330fc RM |
5911 | default: |
5912 | gas_assert (0); | |
5913 | } | |
4962c51a | 5914 | |
e2b0ab59 | 5915 | if (inst.relocs[0].type == 0) |
4962c51a MS |
5916 | { |
5917 | inst.error = _("this group relocation is not allowed on this instruction"); | |
5918 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5919 | } | |
477330fc RM |
5920 | } |
5921 | else | |
26d97720 NS |
5922 | { |
5923 | char *q = p; | |
0198d5e6 | 5924 | |
e2b0ab59 | 5925 | if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX)) |
26d97720 NS |
5926 | return PARSE_OPERAND_FAIL; |
5927 | /* If the offset is 0, find out if it's a +0 or -0. */ | |
e2b0ab59 AV |
5928 | if (inst.relocs[0].exp.X_op == O_constant |
5929 | && inst.relocs[0].exp.X_add_number == 0) | |
26d97720 NS |
5930 | { |
5931 | skip_whitespace (q); | |
5932 | if (*q == '#') | |
5933 | { | |
5934 | q++; | |
5935 | skip_whitespace (q); | |
5936 | } | |
5937 | if (*q == '-') | |
5938 | inst.operands[i].negative = 1; | |
5939 | } | |
5940 | } | |
09d92015 MM |
5941 | } |
5942 | } | |
8e560766 MGD |
5943 | else if (skip_past_char (&p, ':') == SUCCESS) |
5944 | { | |
5945 | /* FIXME: '@' should be used here, but it's filtered out by generic code | |
5946 | before we get to see it here. This may be subject to change. */ | |
5947 | parse_operand_result result = parse_neon_alignment (&p, i); | |
fa94de6b | 5948 | |
8e560766 MGD |
5949 | if (result != PARSE_OPERAND_SUCCESS) |
5950 | return result; | |
5951 | } | |
09d92015 | 5952 | |
c19d1205 | 5953 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 5954 | { |
c19d1205 | 5955 | inst.error = _("']' expected"); |
4962c51a | 5956 | return PARSE_OPERAND_FAIL; |
09d92015 MM |
5957 | } |
5958 | ||
c19d1205 ZW |
5959 | if (skip_past_char (&p, '!') == SUCCESS) |
5960 | inst.operands[i].writeback = 1; | |
09d92015 | 5961 | |
c19d1205 | 5962 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5963 | { |
c19d1205 ZW |
5964 | if (skip_past_char (&p, '{') == SUCCESS) |
5965 | { | |
5966 | /* [Rn], {expr} - unindexed, with option */ | |
5967 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 5968 | 0, 255, TRUE) == FAIL) |
4962c51a | 5969 | return PARSE_OPERAND_FAIL; |
09d92015 | 5970 | |
c19d1205 ZW |
5971 | if (skip_past_char (&p, '}') == FAIL) |
5972 | { | |
5973 | inst.error = _("'}' expected at end of 'option' field"); | |
4962c51a | 5974 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5975 | } |
5976 | if (inst.operands[i].preind) | |
5977 | { | |
5978 | inst.error = _("cannot combine index with option"); | |
4962c51a | 5979 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5980 | } |
5981 | *str = p; | |
4962c51a | 5982 | return PARSE_OPERAND_SUCCESS; |
09d92015 | 5983 | } |
c19d1205 ZW |
5984 | else |
5985 | { | |
5986 | inst.operands[i].postind = 1; | |
5987 | inst.operands[i].writeback = 1; | |
09d92015 | 5988 | |
c19d1205 ZW |
5989 | if (inst.operands[i].preind) |
5990 | { | |
5991 | inst.error = _("cannot combine pre- and post-indexing"); | |
4962c51a | 5992 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5993 | } |
09d92015 | 5994 | |
c19d1205 ZW |
5995 | if (*p == '+') p++; |
5996 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 5997 | |
f5f10c66 AV |
5998 | enum arm_reg_type rtype = REG_TYPE_MQ; |
5999 | struct neon_type_el et; | |
6000 | if (group_type == GROUP_MVE | |
6001 | && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL) | |
6002 | { | |
6003 | inst.operands[i].immisreg = 2; | |
6004 | inst.operands[i].imm = reg; | |
6005 | } | |
6006 | else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) | |
c19d1205 | 6007 | { |
477330fc RM |
6008 | /* We might be using the immediate for alignment already. If we |
6009 | are, OR the register number into the low-order bits. */ | |
6010 | if (inst.operands[i].immisalign) | |
6011 | inst.operands[i].imm |= reg; | |
6012 | else | |
6013 | inst.operands[i].imm = reg; | |
c19d1205 | 6014 | inst.operands[i].immisreg = 1; |
a737bd4d | 6015 | |
c19d1205 ZW |
6016 | if (skip_past_comma (&p) == SUCCESS) |
6017 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 6018 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
6019 | } |
6020 | else | |
6021 | { | |
26d97720 | 6022 | char *q = p; |
0198d5e6 | 6023 | |
c19d1205 ZW |
6024 | if (inst.operands[i].negative) |
6025 | { | |
6026 | inst.operands[i].negative = 0; | |
6027 | p--; | |
6028 | } | |
e2b0ab59 | 6029 | if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX)) |
4962c51a | 6030 | return PARSE_OPERAND_FAIL; |
26d97720 | 6031 | /* If the offset is 0, find out if it's a +0 or -0. */ |
e2b0ab59 AV |
6032 | if (inst.relocs[0].exp.X_op == O_constant |
6033 | && inst.relocs[0].exp.X_add_number == 0) | |
26d97720 NS |
6034 | { |
6035 | skip_whitespace (q); | |
6036 | if (*q == '#') | |
6037 | { | |
6038 | q++; | |
6039 | skip_whitespace (q); | |
6040 | } | |
6041 | if (*q == '-') | |
6042 | inst.operands[i].negative = 1; | |
6043 | } | |
c19d1205 ZW |
6044 | } |
6045 | } | |
a737bd4d NC |
6046 | } |
6047 | ||
c19d1205 ZW |
6048 | /* If at this point neither .preind nor .postind is set, we have a |
6049 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
6050 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
6051 | { | |
6052 | inst.operands[i].preind = 1; | |
e2b0ab59 AV |
6053 | inst.relocs[0].exp.X_op = O_constant; |
6054 | inst.relocs[0].exp.X_add_number = 0; | |
c19d1205 ZW |
6055 | } |
6056 | *str = p; | |
4962c51a MS |
6057 | return PARSE_OPERAND_SUCCESS; |
6058 | } | |
6059 | ||
6060 | static int | |
6061 | parse_address (char **str, int i) | |
6062 | { | |
21d799b5 | 6063 | return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS |
477330fc | 6064 | ? SUCCESS : FAIL; |
4962c51a MS |
6065 | } |
6066 | ||
6067 | static parse_operand_result | |
6068 | parse_address_group_reloc (char **str, int i, group_reloc_type type) | |
6069 | { | |
6070 | return parse_address_main (str, i, 1, type); | |
a737bd4d NC |
6071 | } |
6072 | ||
b6895b4f PB |
6073 | /* Parse an operand for a MOVW or MOVT instruction. */ |
6074 | static int | |
6075 | parse_half (char **str) | |
6076 | { | |
6077 | char * p; | |
5f4273c7 | 6078 | |
b6895b4f PB |
6079 | p = *str; |
6080 | skip_past_char (&p, '#'); | |
5f4273c7 | 6081 | if (strncasecmp (p, ":lower16:", 9) == 0) |
e2b0ab59 | 6082 | inst.relocs[0].type = BFD_RELOC_ARM_MOVW; |
b6895b4f | 6083 | else if (strncasecmp (p, ":upper16:", 9) == 0) |
e2b0ab59 | 6084 | inst.relocs[0].type = BFD_RELOC_ARM_MOVT; |
b6895b4f | 6085 | |
e2b0ab59 | 6086 | if (inst.relocs[0].type != BFD_RELOC_UNUSED) |
b6895b4f PB |
6087 | { |
6088 | p += 9; | |
5f4273c7 | 6089 | skip_whitespace (p); |
b6895b4f PB |
6090 | } |
6091 | ||
e2b0ab59 | 6092 | if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX)) |
b6895b4f PB |
6093 | return FAIL; |
6094 | ||
e2b0ab59 | 6095 | if (inst.relocs[0].type == BFD_RELOC_UNUSED) |
b6895b4f | 6096 | { |
e2b0ab59 | 6097 | if (inst.relocs[0].exp.X_op != O_constant) |
b6895b4f PB |
6098 | { |
6099 | inst.error = _("constant expression expected"); | |
6100 | return FAIL; | |
6101 | } | |
e2b0ab59 AV |
6102 | if (inst.relocs[0].exp.X_add_number < 0 |
6103 | || inst.relocs[0].exp.X_add_number > 0xffff) | |
b6895b4f PB |
6104 | { |
6105 | inst.error = _("immediate value out of range"); | |
6106 | return FAIL; | |
6107 | } | |
6108 | } | |
6109 | *str = p; | |
6110 | return SUCCESS; | |
6111 | } | |
6112 | ||
c19d1205 | 6113 | /* Miscellaneous. */ |
a737bd4d | 6114 | |
c19d1205 ZW |
6115 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
6116 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
6117 | static int | |
d2cd1205 | 6118 | parse_psr (char **str, bfd_boolean lhs) |
09d92015 | 6119 | { |
c19d1205 ZW |
6120 | char *p; |
6121 | unsigned long psr_field; | |
62b3e311 PB |
6122 | const struct asm_psr *psr; |
6123 | char *start; | |
d2cd1205 | 6124 | bfd_boolean is_apsr = FALSE; |
ac7f631b | 6125 | bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m); |
09d92015 | 6126 | |
a4482bb6 NC |
6127 | /* PR gas/12698: If the user has specified -march=all then m_profile will |
6128 | be TRUE, but we want to ignore it in this case as we are building for any | |
6129 | CPU type, including non-m variants. */ | |
823d2571 | 6130 | if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any)) |
a4482bb6 NC |
6131 | m_profile = FALSE; |
6132 | ||
c19d1205 ZW |
6133 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
6134 | feature for ease of use and backwards compatibility. */ | |
6135 | p = *str; | |
62b3e311 | 6136 | if (strncasecmp (p, "SPSR", 4) == 0) |
d2cd1205 JB |
6137 | { |
6138 | if (m_profile) | |
6139 | goto unsupported_psr; | |
fa94de6b | 6140 | |
d2cd1205 JB |
6141 | psr_field = SPSR_BIT; |
6142 | } | |
6143 | else if (strncasecmp (p, "CPSR", 4) == 0) | |
6144 | { | |
6145 | if (m_profile) | |
6146 | goto unsupported_psr; | |
6147 | ||
6148 | psr_field = 0; | |
6149 | } | |
6150 | else if (strncasecmp (p, "APSR", 4) == 0) | |
6151 | { | |
6152 | /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A | |
6153 | and ARMv7-R architecture CPUs. */ | |
6154 | is_apsr = TRUE; | |
6155 | psr_field = 0; | |
6156 | } | |
6157 | else if (m_profile) | |
62b3e311 PB |
6158 | { |
6159 | start = p; | |
6160 | do | |
6161 | p++; | |
6162 | while (ISALNUM (*p) || *p == '_'); | |
6163 | ||
d2cd1205 JB |
6164 | if (strncasecmp (start, "iapsr", 5) == 0 |
6165 | || strncasecmp (start, "eapsr", 5) == 0 | |
6166 | || strncasecmp (start, "xpsr", 4) == 0 | |
6167 | || strncasecmp (start, "psr", 3) == 0) | |
6168 | p = start + strcspn (start, "rR") + 1; | |
6169 | ||
21d799b5 | 6170 | psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start, |
477330fc | 6171 | p - start); |
d2cd1205 | 6172 | |
62b3e311 PB |
6173 | if (!psr) |
6174 | return FAIL; | |
09d92015 | 6175 | |
d2cd1205 JB |
6176 | /* If APSR is being written, a bitfield may be specified. Note that |
6177 | APSR itself is handled above. */ | |
6178 | if (psr->field <= 3) | |
6179 | { | |
6180 | psr_field = psr->field; | |
6181 | is_apsr = TRUE; | |
6182 | goto check_suffix; | |
6183 | } | |
6184 | ||
62b3e311 | 6185 | *str = p; |
d2cd1205 JB |
6186 | /* M-profile MSR instructions have the mask field set to "10", except |
6187 | *PSR variants which modify APSR, which may use a different mask (and | |
6188 | have been handled already). Do that by setting the PSR_f field | |
6189 | here. */ | |
6190 | return psr->field | (lhs ? PSR_f : 0); | |
62b3e311 | 6191 | } |
d2cd1205 JB |
6192 | else |
6193 | goto unsupported_psr; | |
09d92015 | 6194 | |
62b3e311 | 6195 | p += 4; |
d2cd1205 | 6196 | check_suffix: |
c19d1205 ZW |
6197 | if (*p == '_') |
6198 | { | |
6199 | /* A suffix follows. */ | |
c19d1205 ZW |
6200 | p++; |
6201 | start = p; | |
a737bd4d | 6202 | |
c19d1205 ZW |
6203 | do |
6204 | p++; | |
6205 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 6206 | |
d2cd1205 JB |
6207 | if (is_apsr) |
6208 | { | |
6209 | /* APSR uses a notation for bits, rather than fields. */ | |
6210 | unsigned int nzcvq_bits = 0; | |
6211 | unsigned int g_bit = 0; | |
6212 | char *bit; | |
fa94de6b | 6213 | |
d2cd1205 JB |
6214 | for (bit = start; bit != p; bit++) |
6215 | { | |
6216 | switch (TOLOWER (*bit)) | |
477330fc | 6217 | { |
d2cd1205 JB |
6218 | case 'n': |
6219 | nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01; | |
6220 | break; | |
6221 | ||
6222 | case 'z': | |
6223 | nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02; | |
6224 | break; | |
6225 | ||
6226 | case 'c': | |
6227 | nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04; | |
6228 | break; | |
6229 | ||
6230 | case 'v': | |
6231 | nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08; | |
6232 | break; | |
fa94de6b | 6233 | |
d2cd1205 JB |
6234 | case 'q': |
6235 | nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10; | |
6236 | break; | |
fa94de6b | 6237 | |
d2cd1205 JB |
6238 | case 'g': |
6239 | g_bit |= (g_bit & 0x1) ? 0x2 : 0x1; | |
6240 | break; | |
fa94de6b | 6241 | |
d2cd1205 JB |
6242 | default: |
6243 | inst.error = _("unexpected bit specified after APSR"); | |
6244 | return FAIL; | |
6245 | } | |
6246 | } | |
fa94de6b | 6247 | |
d2cd1205 JB |
6248 | if (nzcvq_bits == 0x1f) |
6249 | psr_field |= PSR_f; | |
fa94de6b | 6250 | |
d2cd1205 JB |
6251 | if (g_bit == 0x1) |
6252 | { | |
6253 | if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)) | |
477330fc | 6254 | { |
d2cd1205 JB |
6255 | inst.error = _("selected processor does not " |
6256 | "support DSP extension"); | |
6257 | return FAIL; | |
6258 | } | |
6259 | ||
6260 | psr_field |= PSR_s; | |
6261 | } | |
fa94de6b | 6262 | |
d2cd1205 JB |
6263 | if ((nzcvq_bits & 0x20) != 0 |
6264 | || (nzcvq_bits != 0x1f && nzcvq_bits != 0) | |
6265 | || (g_bit & 0x2) != 0) | |
6266 | { | |
6267 | inst.error = _("bad bitmask specified after APSR"); | |
6268 | return FAIL; | |
6269 | } | |
6270 | } | |
6271 | else | |
477330fc | 6272 | { |
d2cd1205 | 6273 | psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start, |
477330fc | 6274 | p - start); |
d2cd1205 | 6275 | if (!psr) |
477330fc | 6276 | goto error; |
a737bd4d | 6277 | |
d2cd1205 JB |
6278 | psr_field |= psr->field; |
6279 | } | |
a737bd4d | 6280 | } |
c19d1205 | 6281 | else |
a737bd4d | 6282 | { |
c19d1205 ZW |
6283 | if (ISALNUM (*p)) |
6284 | goto error; /* Garbage after "[CS]PSR". */ | |
6285 | ||
d2cd1205 | 6286 | /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This |
477330fc | 6287 | is deprecated, but allow it anyway. */ |
d2cd1205 JB |
6288 | if (is_apsr && lhs) |
6289 | { | |
6290 | psr_field |= PSR_f; | |
6291 | as_tsktsk (_("writing to APSR without specifying a bitmask is " | |
6292 | "deprecated")); | |
6293 | } | |
6294 | else if (!m_profile) | |
6295 | /* These bits are never right for M-profile devices: don't set them | |
6296 | (only code paths which read/write APSR reach here). */ | |
6297 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 6298 | } |
c19d1205 ZW |
6299 | *str = p; |
6300 | return psr_field; | |
a737bd4d | 6301 | |
d2cd1205 JB |
6302 | unsupported_psr: |
6303 | inst.error = _("selected processor does not support requested special " | |
6304 | "purpose register"); | |
6305 | return FAIL; | |
6306 | ||
c19d1205 ZW |
6307 | error: |
6308 | inst.error = _("flag for {c}psr instruction expected"); | |
6309 | return FAIL; | |
a737bd4d NC |
6310 | } |
6311 | ||
32c36c3c AV |
6312 | static int |
6313 | parse_sys_vldr_vstr (char **str) | |
6314 | { | |
6315 | unsigned i; | |
6316 | int val = FAIL; | |
6317 | struct { | |
6318 | const char *name; | |
6319 | int regl; | |
6320 | int regh; | |
6321 | } sysregs[] = { | |
6322 | {"FPSCR", 0x1, 0x0}, | |
6323 | {"FPSCR_nzcvqc", 0x2, 0x0}, | |
6324 | {"VPR", 0x4, 0x1}, | |
6325 | {"P0", 0x5, 0x1}, | |
6326 | {"FPCXTNS", 0x6, 0x1}, | |
6327 | {"FPCXTS", 0x7, 0x1} | |
6328 | }; | |
6329 | char *op_end = strchr (*str, ','); | |
6330 | size_t op_strlen = op_end - *str; | |
6331 | ||
6332 | for (i = 0; i < sizeof (sysregs) / sizeof (sysregs[0]); i++) | |
6333 | { | |
6334 | if (!strncmp (*str, sysregs[i].name, op_strlen)) | |
6335 | { | |
6336 | val = sysregs[i].regl | (sysregs[i].regh << 3); | |
6337 | *str = op_end; | |
6338 | break; | |
6339 | } | |
6340 | } | |
6341 | ||
6342 | return val; | |
6343 | } | |
6344 | ||
c19d1205 ZW |
6345 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
6346 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 6347 | |
c19d1205 ZW |
6348 | static int |
6349 | parse_cps_flags (char **str) | |
a737bd4d | 6350 | { |
c19d1205 ZW |
6351 | int val = 0; |
6352 | int saw_a_flag = 0; | |
6353 | char *s = *str; | |
a737bd4d | 6354 | |
c19d1205 ZW |
6355 | for (;;) |
6356 | switch (*s++) | |
6357 | { | |
6358 | case '\0': case ',': | |
6359 | goto done; | |
a737bd4d | 6360 | |
c19d1205 ZW |
6361 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
6362 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
6363 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 6364 | |
c19d1205 ZW |
6365 | default: |
6366 | inst.error = _("unrecognized CPS flag"); | |
6367 | return FAIL; | |
6368 | } | |
a737bd4d | 6369 | |
c19d1205 ZW |
6370 | done: |
6371 | if (saw_a_flag == 0) | |
a737bd4d | 6372 | { |
c19d1205 ZW |
6373 | inst.error = _("missing CPS flags"); |
6374 | return FAIL; | |
a737bd4d | 6375 | } |
a737bd4d | 6376 | |
c19d1205 ZW |
6377 | *str = s - 1; |
6378 | return val; | |
a737bd4d NC |
6379 | } |
6380 | ||
c19d1205 ZW |
6381 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
6382 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
6383 | |
6384 | static int | |
c19d1205 | 6385 | parse_endian_specifier (char **str) |
a737bd4d | 6386 | { |
c19d1205 ZW |
6387 | int little_endian; |
6388 | char *s = *str; | |
a737bd4d | 6389 | |
c19d1205 ZW |
6390 | if (strncasecmp (s, "BE", 2)) |
6391 | little_endian = 0; | |
6392 | else if (strncasecmp (s, "LE", 2)) | |
6393 | little_endian = 1; | |
6394 | else | |
a737bd4d | 6395 | { |
c19d1205 | 6396 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
6397 | return FAIL; |
6398 | } | |
6399 | ||
c19d1205 | 6400 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 6401 | { |
c19d1205 | 6402 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
6403 | return FAIL; |
6404 | } | |
6405 | ||
c19d1205 ZW |
6406 | *str = s + 2; |
6407 | return little_endian; | |
6408 | } | |
a737bd4d | 6409 | |
c19d1205 ZW |
6410 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
6411 | value suitable for poking into the rotate field of an sxt or sxta | |
6412 | instruction, or FAIL on error. */ | |
6413 | ||
6414 | static int | |
6415 | parse_ror (char **str) | |
6416 | { | |
6417 | int rot; | |
6418 | char *s = *str; | |
6419 | ||
6420 | if (strncasecmp (s, "ROR", 3) == 0) | |
6421 | s += 3; | |
6422 | else | |
a737bd4d | 6423 | { |
c19d1205 | 6424 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
6425 | return FAIL; |
6426 | } | |
c19d1205 ZW |
6427 | |
6428 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
6429 | return FAIL; | |
6430 | ||
6431 | switch (rot) | |
a737bd4d | 6432 | { |
c19d1205 ZW |
6433 | case 0: *str = s; return 0x0; |
6434 | case 8: *str = s; return 0x1; | |
6435 | case 16: *str = s; return 0x2; | |
6436 | case 24: *str = s; return 0x3; | |
6437 | ||
6438 | default: | |
6439 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
6440 | return FAIL; |
6441 | } | |
c19d1205 | 6442 | } |
a737bd4d | 6443 | |
c19d1205 ZW |
6444 | /* Parse a conditional code (from conds[] below). The value returned is in the |
6445 | range 0 .. 14, or FAIL. */ | |
6446 | static int | |
6447 | parse_cond (char **str) | |
6448 | { | |
c462b453 | 6449 | char *q; |
c19d1205 | 6450 | const struct asm_cond *c; |
c462b453 PB |
6451 | int n; |
6452 | /* Condition codes are always 2 characters, so matching up to | |
6453 | 3 characters is sufficient. */ | |
6454 | char cond[3]; | |
a737bd4d | 6455 | |
c462b453 PB |
6456 | q = *str; |
6457 | n = 0; | |
6458 | while (ISALPHA (*q) && n < 3) | |
6459 | { | |
e07e6e58 | 6460 | cond[n] = TOLOWER (*q); |
c462b453 PB |
6461 | q++; |
6462 | n++; | |
6463 | } | |
a737bd4d | 6464 | |
21d799b5 | 6465 | c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n); |
c19d1205 | 6466 | if (!c) |
a737bd4d | 6467 | { |
c19d1205 | 6468 | inst.error = _("condition required"); |
a737bd4d NC |
6469 | return FAIL; |
6470 | } | |
6471 | ||
c19d1205 ZW |
6472 | *str = q; |
6473 | return c->value; | |
6474 | } | |
6475 | ||
62b3e311 PB |
6476 | /* Parse an option for a barrier instruction. Returns the encoding for the |
6477 | option, or FAIL. */ | |
6478 | static int | |
6479 | parse_barrier (char **str) | |
6480 | { | |
6481 | char *p, *q; | |
6482 | const struct asm_barrier_opt *o; | |
6483 | ||
6484 | p = q = *str; | |
6485 | while (ISALPHA (*q)) | |
6486 | q++; | |
6487 | ||
21d799b5 | 6488 | o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p, |
477330fc | 6489 | q - p); |
62b3e311 PB |
6490 | if (!o) |
6491 | return FAIL; | |
6492 | ||
e797f7e0 MGD |
6493 | if (!mark_feature_used (&o->arch)) |
6494 | return FAIL; | |
6495 | ||
62b3e311 PB |
6496 | *str = q; |
6497 | return o->value; | |
6498 | } | |
6499 | ||
92e90b6e PB |
6500 | /* Parse the operands of a table branch instruction. Similar to a memory |
6501 | operand. */ | |
6502 | static int | |
6503 | parse_tb (char **str) | |
6504 | { | |
6505 | char * p = *str; | |
6506 | int reg; | |
6507 | ||
6508 | if (skip_past_char (&p, '[') == FAIL) | |
ab1eb5fe PB |
6509 | { |
6510 | inst.error = _("'[' expected"); | |
6511 | return FAIL; | |
6512 | } | |
92e90b6e | 6513 | |
dcbf9037 | 6514 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
6515 | { |
6516 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
6517 | return FAIL; | |
6518 | } | |
6519 | inst.operands[0].reg = reg; | |
6520 | ||
6521 | if (skip_past_comma (&p) == FAIL) | |
ab1eb5fe PB |
6522 | { |
6523 | inst.error = _("',' expected"); | |
6524 | return FAIL; | |
6525 | } | |
5f4273c7 | 6526 | |
dcbf9037 | 6527 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
6528 | { |
6529 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
6530 | return FAIL; | |
6531 | } | |
6532 | inst.operands[0].imm = reg; | |
6533 | ||
6534 | if (skip_past_comma (&p) == SUCCESS) | |
6535 | { | |
6536 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
6537 | return FAIL; | |
e2b0ab59 | 6538 | if (inst.relocs[0].exp.X_add_number != 1) |
92e90b6e PB |
6539 | { |
6540 | inst.error = _("invalid shift"); | |
6541 | return FAIL; | |
6542 | } | |
6543 | inst.operands[0].shifted = 1; | |
6544 | } | |
6545 | ||
6546 | if (skip_past_char (&p, ']') == FAIL) | |
6547 | { | |
6548 | inst.error = _("']' expected"); | |
6549 | return FAIL; | |
6550 | } | |
6551 | *str = p; | |
6552 | return SUCCESS; | |
6553 | } | |
6554 | ||
5287ad62 JB |
6555 | /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more |
6556 | information on the types the operands can take and how they are encoded. | |
037e8744 JB |
6557 | Up to four operands may be read; this function handles setting the |
6558 | ".present" field for each read operand itself. | |
5287ad62 JB |
6559 | Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, |
6560 | else returns FAIL. */ | |
6561 | ||
6562 | static int | |
6563 | parse_neon_mov (char **str, int *which_operand) | |
6564 | { | |
6565 | int i = *which_operand, val; | |
6566 | enum arm_reg_type rtype; | |
6567 | char *ptr = *str; | |
dcbf9037 | 6568 | struct neon_type_el optype; |
5f4273c7 | 6569 | |
57785aa2 AV |
6570 | if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL) |
6571 | { | |
6572 | /* Cases 17 or 19. */ | |
6573 | inst.operands[i].reg = val; | |
6574 | inst.operands[i].isvec = 1; | |
6575 | inst.operands[i].isscalar = 2; | |
6576 | inst.operands[i].vectype = optype; | |
6577 | inst.operands[i++].present = 1; | |
6578 | ||
6579 | if (skip_past_comma (&ptr) == FAIL) | |
6580 | goto wanted_comma; | |
6581 | ||
6582 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) | |
6583 | { | |
6584 | /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */ | |
6585 | inst.operands[i].reg = val; | |
6586 | inst.operands[i].isreg = 1; | |
6587 | inst.operands[i].present = 1; | |
6588 | } | |
6589 | else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL) | |
6590 | { | |
6591 | /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */ | |
6592 | inst.operands[i].reg = val; | |
6593 | inst.operands[i].isvec = 1; | |
6594 | inst.operands[i].isscalar = 2; | |
6595 | inst.operands[i].vectype = optype; | |
6596 | inst.operands[i++].present = 1; | |
6597 | ||
6598 | if (skip_past_comma (&ptr) == FAIL) | |
6599 | goto wanted_comma; | |
6600 | ||
6601 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6602 | goto wanted_arm; | |
6603 | ||
6604 | inst.operands[i].reg = val; | |
6605 | inst.operands[i].isreg = 1; | |
6606 | inst.operands[i++].present = 1; | |
6607 | ||
6608 | if (skip_past_comma (&ptr) == FAIL) | |
6609 | goto wanted_comma; | |
6610 | ||
6611 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6612 | goto wanted_arm; | |
6613 | ||
6614 | inst.operands[i].reg = val; | |
6615 | inst.operands[i].isreg = 1; | |
6616 | inst.operands[i].present = 1; | |
6617 | } | |
6618 | else | |
6619 | { | |
6620 | first_error (_("expected ARM or MVE vector register")); | |
6621 | return FAIL; | |
6622 | } | |
6623 | } | |
6624 | else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL) | |
5287ad62 JB |
6625 | { |
6626 | /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ | |
6627 | inst.operands[i].reg = val; | |
6628 | inst.operands[i].isscalar = 1; | |
dcbf9037 | 6629 | inst.operands[i].vectype = optype; |
5287ad62 JB |
6630 | inst.operands[i++].present = 1; |
6631 | ||
6632 | if (skip_past_comma (&ptr) == FAIL) | |
477330fc | 6633 | goto wanted_comma; |
5f4273c7 | 6634 | |
dcbf9037 | 6635 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
477330fc | 6636 | goto wanted_arm; |
5f4273c7 | 6637 | |
5287ad62 JB |
6638 | inst.operands[i].reg = val; |
6639 | inst.operands[i].isreg = 1; | |
6640 | inst.operands[i].present = 1; | |
6641 | } | |
57785aa2 AV |
6642 | else if (((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) |
6643 | != FAIL) | |
6644 | || ((val = arm_typed_reg_parse (&ptr, REG_TYPE_MQ, &rtype, &optype)) | |
6645 | != FAIL)) | |
5287ad62 JB |
6646 | { |
6647 | /* Cases 0, 1, 2, 3, 5 (D only). */ | |
6648 | if (skip_past_comma (&ptr) == FAIL) | |
477330fc | 6649 | goto wanted_comma; |
5f4273c7 | 6650 | |
5287ad62 JB |
6651 | inst.operands[i].reg = val; |
6652 | inst.operands[i].isreg = 1; | |
6653 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
6654 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
6655 | inst.operands[i].isvec = 1; | |
dcbf9037 | 6656 | inst.operands[i].vectype = optype; |
5287ad62 JB |
6657 | inst.operands[i++].present = 1; |
6658 | ||
dcbf9037 | 6659 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
477330fc RM |
6660 | { |
6661 | /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. | |
6662 | Case 13: VMOV <Sd>, <Rm> */ | |
6663 | inst.operands[i].reg = val; | |
6664 | inst.operands[i].isreg = 1; | |
6665 | inst.operands[i].present = 1; | |
6666 | ||
6667 | if (rtype == REG_TYPE_NQ) | |
6668 | { | |
6669 | first_error (_("can't use Neon quad register here")); | |
6670 | return FAIL; | |
6671 | } | |
6672 | else if (rtype != REG_TYPE_VFS) | |
6673 | { | |
6674 | i++; | |
6675 | if (skip_past_comma (&ptr) == FAIL) | |
6676 | goto wanted_comma; | |
6677 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6678 | goto wanted_arm; | |
6679 | inst.operands[i].reg = val; | |
6680 | inst.operands[i].isreg = 1; | |
6681 | inst.operands[i].present = 1; | |
6682 | } | |
6683 | } | |
037e8744 | 6684 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, |
477330fc RM |
6685 | &optype)) != FAIL) |
6686 | { | |
6687 | /* Case 0: VMOV<c><q> <Qd>, <Qm> | |
6688 | Case 1: VMOV<c><q> <Dd>, <Dm> | |
6689 | Case 8: VMOV.F32 <Sd>, <Sm> | |
6690 | Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ | |
6691 | ||
6692 | inst.operands[i].reg = val; | |
6693 | inst.operands[i].isreg = 1; | |
6694 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
6695 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
6696 | inst.operands[i].isvec = 1; | |
6697 | inst.operands[i].vectype = optype; | |
6698 | inst.operands[i].present = 1; | |
6699 | ||
6700 | if (skip_past_comma (&ptr) == SUCCESS) | |
6701 | { | |
6702 | /* Case 15. */ | |
6703 | i++; | |
6704 | ||
6705 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6706 | goto wanted_arm; | |
6707 | ||
6708 | inst.operands[i].reg = val; | |
6709 | inst.operands[i].isreg = 1; | |
6710 | inst.operands[i++].present = 1; | |
6711 | ||
6712 | if (skip_past_comma (&ptr) == FAIL) | |
6713 | goto wanted_comma; | |
6714 | ||
6715 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6716 | goto wanted_arm; | |
6717 | ||
6718 | inst.operands[i].reg = val; | |
6719 | inst.operands[i].isreg = 1; | |
6720 | inst.operands[i].present = 1; | |
6721 | } | |
6722 | } | |
4641781c | 6723 | else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) |
477330fc RM |
6724 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> |
6725 | Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> | |
6726 | Case 10: VMOV.F32 <Sd>, #<imm> | |
6727 | Case 11: VMOV.F64 <Dd>, #<imm> */ | |
6728 | inst.operands[i].immisfloat = 1; | |
8335d6aa JW |
6729 | else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE) |
6730 | == SUCCESS) | |
477330fc RM |
6731 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> |
6732 | Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ | |
6733 | ; | |
5287ad62 | 6734 | else |
477330fc RM |
6735 | { |
6736 | first_error (_("expected <Rm> or <Dm> or <Qm> operand")); | |
6737 | return FAIL; | |
6738 | } | |
5287ad62 | 6739 | } |
dcbf9037 | 6740 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 | 6741 | { |
57785aa2 | 6742 | /* Cases 6, 7, 16, 18. */ |
5287ad62 JB |
6743 | inst.operands[i].reg = val; |
6744 | inst.operands[i].isreg = 1; | |
6745 | inst.operands[i++].present = 1; | |
5f4273c7 | 6746 | |
5287ad62 | 6747 | if (skip_past_comma (&ptr) == FAIL) |
477330fc | 6748 | goto wanted_comma; |
5f4273c7 | 6749 | |
57785aa2 AV |
6750 | if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL) |
6751 | { | |
6752 | /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */ | |
6753 | inst.operands[i].reg = val; | |
6754 | inst.operands[i].isscalar = 2; | |
6755 | inst.operands[i].present = 1; | |
6756 | inst.operands[i].vectype = optype; | |
6757 | } | |
6758 | else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL) | |
477330fc RM |
6759 | { |
6760 | /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ | |
6761 | inst.operands[i].reg = val; | |
6762 | inst.operands[i].isscalar = 1; | |
6763 | inst.operands[i].present = 1; | |
6764 | inst.operands[i].vectype = optype; | |
6765 | } | |
dcbf9037 | 6766 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
477330fc | 6767 | { |
477330fc RM |
6768 | inst.operands[i].reg = val; |
6769 | inst.operands[i].isreg = 1; | |
6770 | inst.operands[i++].present = 1; | |
6771 | ||
6772 | if (skip_past_comma (&ptr) == FAIL) | |
6773 | goto wanted_comma; | |
6774 | ||
6775 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) | |
57785aa2 | 6776 | != FAIL) |
477330fc | 6777 | { |
57785aa2 | 6778 | /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ |
477330fc | 6779 | |
477330fc RM |
6780 | inst.operands[i].reg = val; |
6781 | inst.operands[i].isreg = 1; | |
6782 | inst.operands[i].isvec = 1; | |
57785aa2 | 6783 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
477330fc RM |
6784 | inst.operands[i].vectype = optype; |
6785 | inst.operands[i].present = 1; | |
57785aa2 AV |
6786 | |
6787 | if (rtype == REG_TYPE_VFS) | |
6788 | { | |
6789 | /* Case 14. */ | |
6790 | i++; | |
6791 | if (skip_past_comma (&ptr) == FAIL) | |
6792 | goto wanted_comma; | |
6793 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, | |
6794 | &optype)) == FAIL) | |
6795 | { | |
6796 | first_error (_(reg_expected_msgs[REG_TYPE_VFS])); | |
6797 | return FAIL; | |
6798 | } | |
6799 | inst.operands[i].reg = val; | |
6800 | inst.operands[i].isreg = 1; | |
6801 | inst.operands[i].isvec = 1; | |
6802 | inst.operands[i].issingle = 1; | |
6803 | inst.operands[i].vectype = optype; | |
6804 | inst.operands[i].present = 1; | |
6805 | } | |
6806 | } | |
6807 | else | |
6808 | { | |
6809 | if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) | |
6810 | != FAIL) | |
6811 | { | |
6812 | /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */ | |
6813 | inst.operands[i].reg = val; | |
6814 | inst.operands[i].isvec = 1; | |
6815 | inst.operands[i].isscalar = 2; | |
6816 | inst.operands[i].vectype = optype; | |
6817 | inst.operands[i++].present = 1; | |
6818 | ||
6819 | if (skip_past_comma (&ptr) == FAIL) | |
6820 | goto wanted_comma; | |
6821 | ||
6822 | if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) | |
6823 | == FAIL) | |
6824 | { | |
6825 | first_error (_(reg_expected_msgs[REG_TYPE_MQ])); | |
6826 | return FAIL; | |
6827 | } | |
6828 | inst.operands[i].reg = val; | |
6829 | inst.operands[i].isvec = 1; | |
6830 | inst.operands[i].isscalar = 2; | |
6831 | inst.operands[i].vectype = optype; | |
6832 | inst.operands[i].present = 1; | |
6833 | } | |
6834 | else | |
6835 | { | |
6836 | first_error (_("VFP single, double or MVE vector register" | |
6837 | " expected")); | |
6838 | return FAIL; | |
6839 | } | |
477330fc RM |
6840 | } |
6841 | } | |
037e8744 | 6842 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) |
477330fc RM |
6843 | != FAIL) |
6844 | { | |
6845 | /* Case 13. */ | |
6846 | inst.operands[i].reg = val; | |
6847 | inst.operands[i].isreg = 1; | |
6848 | inst.operands[i].isvec = 1; | |
6849 | inst.operands[i].issingle = 1; | |
6850 | inst.operands[i].vectype = optype; | |
6851 | inst.operands[i].present = 1; | |
6852 | } | |
5287ad62 JB |
6853 | } |
6854 | else | |
6855 | { | |
dcbf9037 | 6856 | first_error (_("parse error")); |
5287ad62 JB |
6857 | return FAIL; |
6858 | } | |
6859 | ||
6860 | /* Successfully parsed the operands. Update args. */ | |
6861 | *which_operand = i; | |
6862 | *str = ptr; | |
6863 | return SUCCESS; | |
6864 | ||
5f4273c7 | 6865 | wanted_comma: |
dcbf9037 | 6866 | first_error (_("expected comma")); |
5287ad62 | 6867 | return FAIL; |
5f4273c7 NC |
6868 | |
6869 | wanted_arm: | |
dcbf9037 | 6870 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
5287ad62 | 6871 | return FAIL; |
5287ad62 JB |
6872 | } |
6873 | ||
5be8be5d DG |
6874 | /* Use this macro when the operand constraints are different |
6875 | for ARM and THUMB (e.g. ldrd). */ | |
6876 | #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \ | |
6877 | ((arm_operand) | ((thumb_operand) << 16)) | |
6878 | ||
c19d1205 ZW |
6879 | /* Matcher codes for parse_operands. */ |
6880 | enum operand_parse_code | |
6881 | { | |
6882 | OP_stop, /* end of line */ | |
6883 | ||
6884 | OP_RR, /* ARM register */ | |
6885 | OP_RRnpc, /* ARM register, not r15 */ | |
5be8be5d | 6886 | OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */ |
c19d1205 | 6887 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ |
fa94de6b | 6888 | OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback, |
55881a11 | 6889 | optional trailing ! */ |
c19d1205 ZW |
6890 | OP_RRw, /* ARM register, not r15, optional trailing ! */ |
6891 | OP_RCP, /* Coprocessor number */ | |
6892 | OP_RCN, /* Coprocessor register */ | |
6893 | OP_RF, /* FPA register */ | |
6894 | OP_RVS, /* VFP single precision register */ | |
5287ad62 JB |
6895 | OP_RVD, /* VFP double precision register (0..15) */ |
6896 | OP_RND, /* Neon double precision register (0..31) */ | |
5ee91343 AV |
6897 | OP_RNDMQ, /* Neon double precision (0..31) or MVE vector register. */ |
6898 | OP_RNDMQR, /* Neon double precision (0..31), MVE vector or ARM register. | |
6899 | */ | |
5287ad62 | 6900 | OP_RNQ, /* Neon quad precision register */ |
5ee91343 | 6901 | OP_RNQMQ, /* Neon quad or MVE vector register. */ |
037e8744 | 6902 | OP_RVSD, /* VFP single or double precision register */ |
1b883319 | 6903 | OP_RVSD_COND, /* VFP single, double precision register or condition code. */ |
dd9634d9 | 6904 | OP_RVSDMQ, /* VFP single, double precision or MVE vector register. */ |
dec41383 | 6905 | OP_RNSD, /* Neon single or double precision register */ |
5287ad62 | 6906 | OP_RNDQ, /* Neon double or quad precision register */ |
5ee91343 | 6907 | OP_RNDQMQ, /* Neon double, quad or MVE vector register. */ |
7df54120 | 6908 | OP_RNDQMQR, /* Neon double, quad, MVE vector or ARM register. */ |
037e8744 | 6909 | OP_RNSDQ, /* Neon single, double or quad precision register */ |
5287ad62 | 6910 | OP_RNSC, /* Neon scalar D[X] */ |
c19d1205 ZW |
6911 | OP_RVC, /* VFP control register */ |
6912 | OP_RMF, /* Maverick F register */ | |
6913 | OP_RMD, /* Maverick D register */ | |
6914 | OP_RMFX, /* Maverick FX register */ | |
6915 | OP_RMDX, /* Maverick DX register */ | |
6916 | OP_RMAX, /* Maverick AX register */ | |
6917 | OP_RMDS, /* Maverick DSPSC register */ | |
6918 | OP_RIWR, /* iWMMXt wR register */ | |
6919 | OP_RIWC, /* iWMMXt wC register */ | |
6920 | OP_RIWG, /* iWMMXt wCG register */ | |
6921 | OP_RXA, /* XScale accumulator register */ | |
6922 | ||
5ee91343 AV |
6923 | OP_RNSDQMQ, /* Neon single, double or quad register or MVE vector register |
6924 | */ | |
6925 | OP_RNSDQMQR, /* Neon single, double or quad register, MVE vector register or | |
6926 | GPR (no SP/SP) */ | |
a302e574 | 6927 | OP_RMQ, /* MVE vector register. */ |
1b883319 | 6928 | OP_RMQRZ, /* MVE vector or ARM register including ZR. */ |
35d1cfc2 | 6929 | OP_RMQRR, /* MVE vector or ARM register. */ |
a302e574 | 6930 | |
60f993ce AV |
6931 | /* New operands for Armv8.1-M Mainline. */ |
6932 | OP_LR, /* ARM LR register */ | |
a302e574 AV |
6933 | OP_RRe, /* ARM register, only even numbered. */ |
6934 | OP_RRo, /* ARM register, only odd numbered, not r13 or r15. */ | |
60f993ce | 6935 | OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */ |
e39c1607 | 6936 | OP_RR_ZR, /* ARM register or ZR but no PC */ |
60f993ce | 6937 | |
c19d1205 | 6938 | OP_REGLST, /* ARM register list */ |
4b5a202f | 6939 | OP_CLRMLST, /* CLRM register list */ |
c19d1205 ZW |
6940 | OP_VRSLST, /* VFP single-precision register list */ |
6941 | OP_VRDLST, /* VFP double-precision register list */ | |
037e8744 | 6942 | OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ |
5287ad62 JB |
6943 | OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ |
6944 | OP_NSTRLST, /* Neon element/structure list */ | |
efd6b359 | 6945 | OP_VRSDVLST, /* VFP single or double-precision register list and VPR */ |
35c228db AV |
6946 | OP_MSTRLST2, /* MVE vector list with two elements. */ |
6947 | OP_MSTRLST4, /* MVE vector list with four elements. */ | |
5287ad62 | 6948 | |
5287ad62 | 6949 | OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ |
037e8744 | 6950 | OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ |
aacf0b33 | 6951 | OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */ |
1b883319 AV |
6952 | OP_RSVDMQ_FI0, /* VFP S, D, MVE vector register or floating point immediate |
6953 | zero. */ | |
5287ad62 | 6954 | OP_RR_RNSC, /* ARM reg or Neon scalar. */ |
dec41383 | 6955 | OP_RNSD_RNSC, /* Neon S or D reg, or Neon scalar. */ |
037e8744 | 6956 | OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ |
886e1c73 AV |
6957 | OP_RNSDQ_RNSC_MQ, /* Vector S, D or Q reg, Neon scalar or MVE vector register. |
6958 | */ | |
a8465a06 AV |
6959 | OP_RNSDQ_RNSC_MQ_RR, /* Vector S, D or Q reg, or MVE vector reg , or Neon |
6960 | scalar, or ARM register. */ | |
5287ad62 | 6961 | OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ |
42b16635 AV |
6962 | OP_RNDQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, or ARM register. */ |
6963 | OP_RNDQMQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, MVE vector or ARM | |
6964 | register. */ | |
5d281bf0 | 6965 | OP_RNDQMQ_RNSC, /* Neon D, Q or MVE vector reg, or Neon scalar. */ |
5287ad62 JB |
6966 | OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ |
6967 | OP_VMOV, /* Neon VMOV operands. */ | |
4316f0d2 | 6968 | OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */ |
f601a00c AV |
6969 | /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */ |
6970 | OP_RNDQMQ_Ibig, | |
5287ad62 | 6971 | OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ |
5150f0d8 AV |
6972 | OP_RNDQMQ_I63b_RR, /* Neon D or Q reg, immediate for shift, MVE vector or |
6973 | ARM register. */ | |
2d447fca | 6974 | OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ |
32c36c3c | 6975 | OP_VLDR, /* VLDR operand. */ |
5287ad62 JB |
6976 | |
6977 | OP_I0, /* immediate zero */ | |
c19d1205 ZW |
6978 | OP_I7, /* immediate value 0 .. 7 */ |
6979 | OP_I15, /* 0 .. 15 */ | |
6980 | OP_I16, /* 1 .. 16 */ | |
5287ad62 | 6981 | OP_I16z, /* 0 .. 16 */ |
c19d1205 ZW |
6982 | OP_I31, /* 0 .. 31 */ |
6983 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
6984 | OP_I32, /* 1 .. 32 */ | |
5287ad62 JB |
6985 | OP_I32z, /* 0 .. 32 */ |
6986 | OP_I63, /* 0 .. 63 */ | |
c19d1205 | 6987 | OP_I63s, /* -64 .. 63 */ |
5287ad62 JB |
6988 | OP_I64, /* 1 .. 64 */ |
6989 | OP_I64z, /* 0 .. 64 */ | |
c19d1205 | 6990 | OP_I255, /* 0 .. 255 */ |
c19d1205 ZW |
6991 | |
6992 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
6993 | OP_I7b, /* 0 .. 7 */ | |
6994 | OP_I15b, /* 0 .. 15 */ | |
6995 | OP_I31b, /* 0 .. 31 */ | |
6996 | ||
6997 | OP_SH, /* shifter operand */ | |
4962c51a | 6998 | OP_SHG, /* shifter operand with possible group relocation */ |
c19d1205 | 6999 | OP_ADDR, /* Memory address expression (any mode) */ |
35c228db | 7000 | OP_ADDRMVE, /* Memory address expression for MVE's VSTR/VLDR. */ |
4962c51a MS |
7001 | OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ |
7002 | OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ | |
7003 | OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ | |
c19d1205 ZW |
7004 | OP_EXP, /* arbitrary expression */ |
7005 | OP_EXPi, /* same, with optional immediate prefix */ | |
7006 | OP_EXPr, /* same, with optional relocation suffix */ | |
e2b0ab59 | 7007 | OP_EXPs, /* same, with optional non-first operand relocation suffix */ |
b6895b4f | 7008 | OP_HALF, /* 0 .. 65535 or low/high reloc. */ |
c28eeff2 SN |
7009 | OP_IROT1, /* VCADD rotate immediate: 90, 270. */ |
7010 | OP_IROT2, /* VCMLA rotate immediate: 0, 90, 180, 270. */ | |
c19d1205 ZW |
7011 | |
7012 | OP_CPSF, /* CPS flags */ | |
7013 | OP_ENDI, /* Endianness specifier */ | |
d2cd1205 JB |
7014 | OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */ |
7015 | OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */ | |
c19d1205 | 7016 | OP_COND, /* conditional code */ |
92e90b6e | 7017 | OP_TB, /* Table branch. */ |
c19d1205 | 7018 | |
037e8744 JB |
7019 | OP_APSR_RR, /* ARM register or "APSR_nzcv". */ |
7020 | ||
c19d1205 | 7021 | OP_RRnpc_I0, /* ARM register or literal 0 */ |
33eaf5de | 7022 | OP_RR_EXr, /* ARM register or expression with opt. reloc stuff. */ |
c19d1205 ZW |
7023 | OP_RR_EXi, /* ARM register or expression with imm prefix */ |
7024 | OP_RF_IF, /* FPA register or immediate */ | |
7025 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
41adaa5c | 7026 | OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ |
c19d1205 ZW |
7027 | |
7028 | /* Optional operands. */ | |
7029 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
7030 | OP_oI31b, /* 0 .. 31 */ | |
5287ad62 | 7031 | OP_oI32b, /* 1 .. 32 */ |
5f1af56b | 7032 | OP_oI32z, /* 0 .. 32 */ |
c19d1205 ZW |
7033 | OP_oIffffb, /* 0 .. 65535 */ |
7034 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
7035 | ||
7036 | OP_oRR, /* ARM register */ | |
60f993ce | 7037 | OP_oLR, /* ARM LR register */ |
c19d1205 | 7038 | OP_oRRnpc, /* ARM register, not the PC */ |
5be8be5d | 7039 | OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */ |
b6702015 | 7040 | OP_oRRw, /* ARM register, not r15, optional trailing ! */ |
5287ad62 JB |
7041 | OP_oRND, /* Optional Neon double precision register */ |
7042 | OP_oRNQ, /* Optional Neon quad precision register */ | |
5ee91343 | 7043 | OP_oRNDQMQ, /* Optional Neon double, quad or MVE vector register. */ |
5287ad62 | 7044 | OP_oRNDQ, /* Optional Neon double or quad precision register */ |
037e8744 | 7045 | OP_oRNSDQ, /* Optional single, double or quad precision vector register */ |
5ee91343 AV |
7046 | OP_oRNSDQMQ, /* Optional single, double or quad register or MVE vector |
7047 | register. */ | |
c19d1205 ZW |
7048 | OP_oSHll, /* LSL immediate */ |
7049 | OP_oSHar, /* ASR immediate */ | |
7050 | OP_oSHllar, /* LSL or ASR immediate */ | |
7051 | OP_oROR, /* ROR 0/8/16/24 */ | |
52e7f43d | 7052 | OP_oBARRIER_I15, /* Option argument for a barrier instruction. */ |
c19d1205 | 7053 | |
1b883319 AV |
7054 | OP_oRMQRZ, /* optional MVE vector or ARM register including ZR. */ |
7055 | ||
5be8be5d DG |
7056 | /* Some pre-defined mixed (ARM/THUMB) operands. */ |
7057 | OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp), | |
7058 | OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp), | |
7059 | OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp), | |
7060 | ||
c19d1205 ZW |
7061 | OP_FIRST_OPTIONAL = OP_oI7b |
7062 | }; | |
a737bd4d | 7063 | |
c19d1205 ZW |
7064 | /* Generic instruction operand parser. This does no encoding and no |
7065 | semantic validation; it merely squirrels values away in the inst | |
7066 | structure. Returns SUCCESS or FAIL depending on whether the | |
7067 | specified grammar matched. */ | |
7068 | static int | |
5be8be5d | 7069 | parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) |
c19d1205 | 7070 | { |
5be8be5d | 7071 | unsigned const int *upat = pattern; |
c19d1205 ZW |
7072 | char *backtrack_pos = 0; |
7073 | const char *backtrack_error = 0; | |
99aad254 | 7074 | int i, val = 0, backtrack_index = 0; |
5287ad62 | 7075 | enum arm_reg_type rtype; |
4962c51a | 7076 | parse_operand_result result; |
5be8be5d | 7077 | unsigned int op_parse_code; |
efd6b359 | 7078 | bfd_boolean partial_match; |
c19d1205 | 7079 | |
e07e6e58 NC |
7080 | #define po_char_or_fail(chr) \ |
7081 | do \ | |
7082 | { \ | |
7083 | if (skip_past_char (&str, chr) == FAIL) \ | |
477330fc | 7084 | goto bad_args; \ |
e07e6e58 NC |
7085 | } \ |
7086 | while (0) | |
c19d1205 | 7087 | |
e07e6e58 NC |
7088 | #define po_reg_or_fail(regtype) \ |
7089 | do \ | |
dcbf9037 | 7090 | { \ |
e07e6e58 | 7091 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ |
477330fc | 7092 | & inst.operands[i].vectype); \ |
e07e6e58 | 7093 | if (val == FAIL) \ |
477330fc RM |
7094 | { \ |
7095 | first_error (_(reg_expected_msgs[regtype])); \ | |
7096 | goto failure; \ | |
7097 | } \ | |
e07e6e58 NC |
7098 | inst.operands[i].reg = val; \ |
7099 | inst.operands[i].isreg = 1; \ | |
7100 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
7101 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
7102 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
477330fc RM |
7103 | || rtype == REG_TYPE_VFD \ |
7104 | || rtype == REG_TYPE_NQ); \ | |
1b883319 | 7105 | inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \ |
dcbf9037 | 7106 | } \ |
e07e6e58 NC |
7107 | while (0) |
7108 | ||
7109 | #define po_reg_or_goto(regtype, label) \ | |
7110 | do \ | |
7111 | { \ | |
7112 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ | |
7113 | & inst.operands[i].vectype); \ | |
7114 | if (val == FAIL) \ | |
7115 | goto label; \ | |
dcbf9037 | 7116 | \ |
e07e6e58 NC |
7117 | inst.operands[i].reg = val; \ |
7118 | inst.operands[i].isreg = 1; \ | |
7119 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
7120 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
7121 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
477330fc | 7122 | || rtype == REG_TYPE_VFD \ |
e07e6e58 | 7123 | || rtype == REG_TYPE_NQ); \ |
1b883319 | 7124 | inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \ |
e07e6e58 NC |
7125 | } \ |
7126 | while (0) | |
7127 | ||
7128 | #define po_imm_or_fail(min, max, popt) \ | |
7129 | do \ | |
7130 | { \ | |
7131 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
7132 | goto failure; \ | |
7133 | inst.operands[i].imm = val; \ | |
7134 | } \ | |
7135 | while (0) | |
7136 | ||
57785aa2 | 7137 | #define po_scalar_or_goto(elsz, label, reg_type) \ |
e07e6e58 NC |
7138 | do \ |
7139 | { \ | |
57785aa2 AV |
7140 | val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \ |
7141 | reg_type); \ | |
e07e6e58 NC |
7142 | if (val == FAIL) \ |
7143 | goto label; \ | |
7144 | inst.operands[i].reg = val; \ | |
7145 | inst.operands[i].isscalar = 1; \ | |
7146 | } \ | |
7147 | while (0) | |
7148 | ||
7149 | #define po_misc_or_fail(expr) \ | |
7150 | do \ | |
7151 | { \ | |
7152 | if (expr) \ | |
7153 | goto failure; \ | |
7154 | } \ | |
7155 | while (0) | |
7156 | ||
7157 | #define po_misc_or_fail_no_backtrack(expr) \ | |
7158 | do \ | |
7159 | { \ | |
7160 | result = expr; \ | |
7161 | if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \ | |
7162 | backtrack_pos = 0; \ | |
7163 | if (result != PARSE_OPERAND_SUCCESS) \ | |
7164 | goto failure; \ | |
7165 | } \ | |
7166 | while (0) | |
4962c51a | 7167 | |
52e7f43d RE |
7168 | #define po_barrier_or_imm(str) \ |
7169 | do \ | |
7170 | { \ | |
7171 | val = parse_barrier (&str); \ | |
ccb84d65 JB |
7172 | if (val == FAIL && ! ISALPHA (*str)) \ |
7173 | goto immediate; \ | |
7174 | if (val == FAIL \ | |
7175 | /* ISB can only take SY as an option. */ \ | |
7176 | || ((inst.instruction & 0xf0) == 0x60 \ | |
7177 | && val != 0xf)) \ | |
52e7f43d | 7178 | { \ |
ccb84d65 JB |
7179 | inst.error = _("invalid barrier type"); \ |
7180 | backtrack_pos = 0; \ | |
7181 | goto failure; \ | |
52e7f43d RE |
7182 | } \ |
7183 | } \ | |
7184 | while (0) | |
7185 | ||
c19d1205 ZW |
7186 | skip_whitespace (str); |
7187 | ||
7188 | for (i = 0; upat[i] != OP_stop; i++) | |
7189 | { | |
5be8be5d DG |
7190 | op_parse_code = upat[i]; |
7191 | if (op_parse_code >= 1<<16) | |
7192 | op_parse_code = thumb ? (op_parse_code >> 16) | |
7193 | : (op_parse_code & ((1<<16)-1)); | |
7194 | ||
7195 | if (op_parse_code >= OP_FIRST_OPTIONAL) | |
c19d1205 ZW |
7196 | { |
7197 | /* Remember where we are in case we need to backtrack. */ | |
c19d1205 ZW |
7198 | backtrack_pos = str; |
7199 | backtrack_error = inst.error; | |
7200 | backtrack_index = i; | |
7201 | } | |
7202 | ||
b6702015 | 7203 | if (i > 0 && (i > 1 || inst.operands[0].present)) |
c19d1205 ZW |
7204 | po_char_or_fail (','); |
7205 | ||
5be8be5d | 7206 | switch (op_parse_code) |
c19d1205 ZW |
7207 | { |
7208 | /* Registers */ | |
7209 | case OP_oRRnpc: | |
5be8be5d | 7210 | case OP_oRRnpcsp: |
c19d1205 | 7211 | case OP_RRnpc: |
5be8be5d | 7212 | case OP_RRnpcsp: |
c19d1205 | 7213 | case OP_oRR: |
a302e574 AV |
7214 | case OP_RRe: |
7215 | case OP_RRo: | |
60f993ce AV |
7216 | case OP_LR: |
7217 | case OP_oLR: | |
c19d1205 ZW |
7218 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; |
7219 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
7220 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
7221 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
7222 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
7223 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
477330fc | 7224 | case OP_oRND: |
5ee91343 AV |
7225 | case OP_RNDMQR: |
7226 | po_reg_or_goto (REG_TYPE_RN, try_rndmq); | |
7227 | break; | |
7228 | try_rndmq: | |
7229 | case OP_RNDMQ: | |
7230 | po_reg_or_goto (REG_TYPE_MQ, try_rnd); | |
7231 | break; | |
7232 | try_rnd: | |
5287ad62 | 7233 | case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; |
cd2cf30b PB |
7234 | case OP_RVC: |
7235 | po_reg_or_goto (REG_TYPE_VFC, coproc_reg); | |
7236 | break; | |
7237 | /* Also accept generic coprocessor regs for unknown registers. */ | |
7238 | coproc_reg: | |
ba6cd17f SD |
7239 | po_reg_or_goto (REG_TYPE_CN, vpr_po); |
7240 | break; | |
7241 | /* Also accept P0 or p0 for VPR.P0. Since P0 is already an | |
7242 | existing register with a value of 0, this seems like the | |
7243 | best way to parse P0. */ | |
7244 | vpr_po: | |
7245 | if (strncasecmp (str, "P0", 2) == 0) | |
7246 | { | |
7247 | str += 2; | |
7248 | inst.operands[i].isreg = 1; | |
7249 | inst.operands[i].reg = 13; | |
7250 | } | |
7251 | else | |
7252 | goto failure; | |
cd2cf30b | 7253 | break; |
c19d1205 ZW |
7254 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; |
7255 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
7256 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
7257 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
7258 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
7259 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
7260 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
7261 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
7262 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
7263 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
477330fc | 7264 | case OP_oRNQ: |
5ee91343 AV |
7265 | case OP_RNQMQ: |
7266 | po_reg_or_goto (REG_TYPE_MQ, try_nq); | |
7267 | break; | |
7268 | try_nq: | |
5287ad62 | 7269 | case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; |
dec41383 | 7270 | case OP_RNSD: po_reg_or_fail (REG_TYPE_NSD); break; |
7df54120 AV |
7271 | case OP_RNDQMQR: |
7272 | po_reg_or_goto (REG_TYPE_RN, try_rndqmq); | |
7273 | break; | |
7274 | try_rndqmq: | |
5ee91343 AV |
7275 | case OP_oRNDQMQ: |
7276 | case OP_RNDQMQ: | |
7277 | po_reg_or_goto (REG_TYPE_MQ, try_rndq); | |
7278 | break; | |
7279 | try_rndq: | |
477330fc | 7280 | case OP_oRNDQ: |
5287ad62 | 7281 | case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; |
dd9634d9 AV |
7282 | case OP_RVSDMQ: |
7283 | po_reg_or_goto (REG_TYPE_MQ, try_rvsd); | |
7284 | break; | |
7285 | try_rvsd: | |
477330fc | 7286 | case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; |
1b883319 AV |
7287 | case OP_RVSD_COND: |
7288 | po_reg_or_goto (REG_TYPE_VFSD, try_cond); | |
7289 | break; | |
477330fc RM |
7290 | case OP_oRNSDQ: |
7291 | case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; | |
5ee91343 AV |
7292 | case OP_RNSDQMQR: |
7293 | po_reg_or_goto (REG_TYPE_RN, try_mq); | |
7294 | break; | |
7295 | try_mq: | |
7296 | case OP_oRNSDQMQ: | |
7297 | case OP_RNSDQMQ: | |
7298 | po_reg_or_goto (REG_TYPE_MQ, try_nsdq2); | |
7299 | break; | |
7300 | try_nsdq2: | |
7301 | po_reg_or_fail (REG_TYPE_NSDQ); | |
7302 | inst.error = 0; | |
7303 | break; | |
35d1cfc2 AV |
7304 | case OP_RMQRR: |
7305 | po_reg_or_goto (REG_TYPE_RN, try_rmq); | |
7306 | break; | |
7307 | try_rmq: | |
a302e574 AV |
7308 | case OP_RMQ: |
7309 | po_reg_or_fail (REG_TYPE_MQ); | |
7310 | break; | |
477330fc RM |
7311 | /* Neon scalar. Using an element size of 8 means that some invalid |
7312 | scalars are accepted here, so deal with those in later code. */ | |
57785aa2 | 7313 | case OP_RNSC: po_scalar_or_goto (8, failure, REG_TYPE_VFD); break; |
477330fc RM |
7314 | |
7315 | case OP_RNDQ_I0: | |
7316 | { | |
7317 | po_reg_or_goto (REG_TYPE_NDQ, try_imm0); | |
7318 | break; | |
7319 | try_imm0: | |
7320 | po_imm_or_fail (0, 0, TRUE); | |
7321 | } | |
7322 | break; | |
7323 | ||
7324 | case OP_RVSD_I0: | |
7325 | po_reg_or_goto (REG_TYPE_VFSD, try_imm0); | |
7326 | break; | |
7327 | ||
1b883319 AV |
7328 | case OP_RSVDMQ_FI0: |
7329 | po_reg_or_goto (REG_TYPE_MQ, try_rsvd_fi0); | |
7330 | break; | |
7331 | try_rsvd_fi0: | |
aacf0b33 KT |
7332 | case OP_RSVD_FI0: |
7333 | { | |
7334 | po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0); | |
7335 | break; | |
7336 | try_ifimm0: | |
7337 | if (parse_ifimm_zero (&str)) | |
7338 | inst.operands[i].imm = 0; | |
7339 | else | |
7340 | { | |
7341 | inst.error | |
7342 | = _("only floating point zero is allowed as immediate value"); | |
7343 | goto failure; | |
7344 | } | |
7345 | } | |
7346 | break; | |
7347 | ||
477330fc RM |
7348 | case OP_RR_RNSC: |
7349 | { | |
57785aa2 | 7350 | po_scalar_or_goto (8, try_rr, REG_TYPE_VFD); |
477330fc RM |
7351 | break; |
7352 | try_rr: | |
7353 | po_reg_or_fail (REG_TYPE_RN); | |
7354 | } | |
7355 | break; | |
7356 | ||
a8465a06 AV |
7357 | case OP_RNSDQ_RNSC_MQ_RR: |
7358 | po_reg_or_goto (REG_TYPE_RN, try_rnsdq_rnsc_mq); | |
7359 | break; | |
7360 | try_rnsdq_rnsc_mq: | |
886e1c73 AV |
7361 | case OP_RNSDQ_RNSC_MQ: |
7362 | po_reg_or_goto (REG_TYPE_MQ, try_rnsdq_rnsc); | |
7363 | break; | |
7364 | try_rnsdq_rnsc: | |
477330fc RM |
7365 | case OP_RNSDQ_RNSC: |
7366 | { | |
57785aa2 AV |
7367 | po_scalar_or_goto (8, try_nsdq, REG_TYPE_VFD); |
7368 | inst.error = 0; | |
477330fc RM |
7369 | break; |
7370 | try_nsdq: | |
7371 | po_reg_or_fail (REG_TYPE_NSDQ); | |
57785aa2 | 7372 | inst.error = 0; |
477330fc RM |
7373 | } |
7374 | break; | |
7375 | ||
dec41383 JW |
7376 | case OP_RNSD_RNSC: |
7377 | { | |
57785aa2 | 7378 | po_scalar_or_goto (8, try_s_scalar, REG_TYPE_VFD); |
dec41383 JW |
7379 | break; |
7380 | try_s_scalar: | |
57785aa2 | 7381 | po_scalar_or_goto (4, try_nsd, REG_TYPE_VFS); |
dec41383 JW |
7382 | break; |
7383 | try_nsd: | |
7384 | po_reg_or_fail (REG_TYPE_NSD); | |
7385 | } | |
7386 | break; | |
7387 | ||
42b16635 AV |
7388 | case OP_RNDQMQ_RNSC_RR: |
7389 | po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc_rr); | |
7390 | break; | |
7391 | try_rndq_rnsc_rr: | |
7392 | case OP_RNDQ_RNSC_RR: | |
7393 | po_reg_or_goto (REG_TYPE_RN, try_rndq_rnsc); | |
7394 | break; | |
5d281bf0 AV |
7395 | case OP_RNDQMQ_RNSC: |
7396 | po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc); | |
7397 | break; | |
7398 | try_rndq_rnsc: | |
477330fc RM |
7399 | case OP_RNDQ_RNSC: |
7400 | { | |
57785aa2 | 7401 | po_scalar_or_goto (8, try_ndq, REG_TYPE_VFD); |
477330fc RM |
7402 | break; |
7403 | try_ndq: | |
7404 | po_reg_or_fail (REG_TYPE_NDQ); | |
7405 | } | |
7406 | break; | |
7407 | ||
7408 | case OP_RND_RNSC: | |
7409 | { | |
57785aa2 | 7410 | po_scalar_or_goto (8, try_vfd, REG_TYPE_VFD); |
477330fc RM |
7411 | break; |
7412 | try_vfd: | |
7413 | po_reg_or_fail (REG_TYPE_VFD); | |
7414 | } | |
7415 | break; | |
7416 | ||
7417 | case OP_VMOV: | |
7418 | /* WARNING: parse_neon_mov can move the operand counter, i. If we're | |
7419 | not careful then bad things might happen. */ | |
7420 | po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); | |
7421 | break; | |
7422 | ||
f601a00c AV |
7423 | case OP_RNDQMQ_Ibig: |
7424 | po_reg_or_goto (REG_TYPE_MQ, try_rndq_ibig); | |
7425 | break; | |
7426 | try_rndq_ibig: | |
477330fc RM |
7427 | case OP_RNDQ_Ibig: |
7428 | { | |
7429 | po_reg_or_goto (REG_TYPE_NDQ, try_immbig); | |
7430 | break; | |
7431 | try_immbig: | |
7432 | /* There's a possibility of getting a 64-bit immediate here, so | |
7433 | we need special handling. */ | |
8335d6aa JW |
7434 | if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE) |
7435 | == FAIL) | |
477330fc RM |
7436 | { |
7437 | inst.error = _("immediate value is out of range"); | |
7438 | goto failure; | |
7439 | } | |
7440 | } | |
7441 | break; | |
7442 | ||
5150f0d8 AV |
7443 | case OP_RNDQMQ_I63b_RR: |
7444 | po_reg_or_goto (REG_TYPE_MQ, try_rndq_i63b_rr); | |
7445 | break; | |
7446 | try_rndq_i63b_rr: | |
7447 | po_reg_or_goto (REG_TYPE_RN, try_rndq_i63b); | |
7448 | break; | |
7449 | try_rndq_i63b: | |
477330fc RM |
7450 | case OP_RNDQ_I63b: |
7451 | { | |
7452 | po_reg_or_goto (REG_TYPE_NDQ, try_shimm); | |
7453 | break; | |
7454 | try_shimm: | |
7455 | po_imm_or_fail (0, 63, TRUE); | |
7456 | } | |
7457 | break; | |
c19d1205 ZW |
7458 | |
7459 | case OP_RRnpcb: | |
7460 | po_char_or_fail ('['); | |
7461 | po_reg_or_fail (REG_TYPE_RN); | |
7462 | po_char_or_fail (']'); | |
7463 | break; | |
a737bd4d | 7464 | |
55881a11 | 7465 | case OP_RRnpctw: |
c19d1205 | 7466 | case OP_RRw: |
b6702015 | 7467 | case OP_oRRw: |
c19d1205 ZW |
7468 | po_reg_or_fail (REG_TYPE_RN); |
7469 | if (skip_past_char (&str, '!') == SUCCESS) | |
7470 | inst.operands[i].writeback = 1; | |
7471 | break; | |
7472 | ||
7473 | /* Immediates */ | |
7474 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
7475 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
7476 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
477330fc | 7477 | case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; |
c19d1205 ZW |
7478 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; |
7479 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
477330fc | 7480 | case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; |
c19d1205 | 7481 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; |
477330fc RM |
7482 | case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; |
7483 | case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; | |
7484 | case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; | |
c19d1205 | 7485 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; |
c19d1205 ZW |
7486 | |
7487 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
7488 | case OP_oI7b: | |
7489 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
7490 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
7491 | case OP_oI31b: | |
7492 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
477330fc RM |
7493 | case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; |
7494 | case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break; | |
c19d1205 ZW |
7495 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; |
7496 | ||
7497 | /* Immediate variants */ | |
7498 | case OP_oI255c: | |
7499 | po_char_or_fail ('{'); | |
7500 | po_imm_or_fail (0, 255, TRUE); | |
7501 | po_char_or_fail ('}'); | |
7502 | break; | |
7503 | ||
7504 | case OP_I31w: | |
7505 | /* The expression parser chokes on a trailing !, so we have | |
7506 | to find it first and zap it. */ | |
7507 | { | |
7508 | char *s = str; | |
7509 | while (*s && *s != ',') | |
7510 | s++; | |
7511 | if (s[-1] == '!') | |
7512 | { | |
7513 | s[-1] = '\0'; | |
7514 | inst.operands[i].writeback = 1; | |
7515 | } | |
7516 | po_imm_or_fail (0, 31, TRUE); | |
7517 | if (str == s - 1) | |
7518 | str = s; | |
7519 | } | |
7520 | break; | |
7521 | ||
7522 | /* Expressions */ | |
7523 | case OP_EXPi: EXPi: | |
e2b0ab59 | 7524 | po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str, |
c19d1205 ZW |
7525 | GE_OPT_PREFIX)); |
7526 | break; | |
7527 | ||
7528 | case OP_EXP: | |
e2b0ab59 | 7529 | po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str, |
c19d1205 ZW |
7530 | GE_NO_PREFIX)); |
7531 | break; | |
7532 | ||
7533 | case OP_EXPr: EXPr: | |
e2b0ab59 | 7534 | po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str, |
c19d1205 | 7535 | GE_NO_PREFIX)); |
e2b0ab59 | 7536 | if (inst.relocs[0].exp.X_op == O_symbol) |
a737bd4d | 7537 | { |
c19d1205 ZW |
7538 | val = parse_reloc (&str); |
7539 | if (val == -1) | |
7540 | { | |
7541 | inst.error = _("unrecognized relocation suffix"); | |
7542 | goto failure; | |
7543 | } | |
7544 | else if (val != BFD_RELOC_UNUSED) | |
7545 | { | |
7546 | inst.operands[i].imm = val; | |
7547 | inst.operands[i].hasreloc = 1; | |
7548 | } | |
a737bd4d | 7549 | } |
c19d1205 | 7550 | break; |
a737bd4d | 7551 | |
e2b0ab59 AV |
7552 | case OP_EXPs: |
7553 | po_misc_or_fail (my_get_expression (&inst.relocs[i].exp, &str, | |
7554 | GE_NO_PREFIX)); | |
7555 | if (inst.relocs[i].exp.X_op == O_symbol) | |
7556 | { | |
7557 | inst.operands[i].hasreloc = 1; | |
7558 | } | |
7559 | else if (inst.relocs[i].exp.X_op == O_constant) | |
7560 | { | |
7561 | inst.operands[i].imm = inst.relocs[i].exp.X_add_number; | |
7562 | inst.operands[i].hasreloc = 0; | |
7563 | } | |
7564 | break; | |
7565 | ||
b6895b4f PB |
7566 | /* Operand for MOVW or MOVT. */ |
7567 | case OP_HALF: | |
7568 | po_misc_or_fail (parse_half (&str)); | |
7569 | break; | |
7570 | ||
e07e6e58 | 7571 | /* Register or expression. */ |
c19d1205 ZW |
7572 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; |
7573 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 7574 | |
e07e6e58 | 7575 | /* Register or immediate. */ |
c19d1205 ZW |
7576 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; |
7577 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 7578 | |
23d00a41 SD |
7579 | case OP_RRnpcsp_I32: po_reg_or_goto (REG_TYPE_RN, I32); break; |
7580 | I32: po_imm_or_fail (1, 32, FALSE); break; | |
7581 | ||
c19d1205 ZW |
7582 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
7583 | IF: | |
7584 | if (!is_immediate_prefix (*str)) | |
7585 | goto bad_args; | |
7586 | str++; | |
7587 | val = parse_fpa_immediate (&str); | |
7588 | if (val == FAIL) | |
7589 | goto failure; | |
7590 | /* FPA immediates are encoded as registers 8-15. | |
7591 | parse_fpa_immediate has already applied the offset. */ | |
7592 | inst.operands[i].reg = val; | |
7593 | inst.operands[i].isreg = 1; | |
7594 | break; | |
09d92015 | 7595 | |
2d447fca JM |
7596 | case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; |
7597 | I32z: po_imm_or_fail (0, 32, FALSE); break; | |
7598 | ||
e07e6e58 | 7599 | /* Two kinds of register. */ |
c19d1205 ZW |
7600 | case OP_RIWR_RIWC: |
7601 | { | |
7602 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
97f87066 JM |
7603 | if (!rege |
7604 | || (rege->type != REG_TYPE_MMXWR | |
7605 | && rege->type != REG_TYPE_MMXWC | |
7606 | && rege->type != REG_TYPE_MMXWCG)) | |
c19d1205 ZW |
7607 | { |
7608 | inst.error = _("iWMMXt data or control register expected"); | |
7609 | goto failure; | |
7610 | } | |
7611 | inst.operands[i].reg = rege->number; | |
7612 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
7613 | } | |
7614 | break; | |
09d92015 | 7615 | |
41adaa5c JM |
7616 | case OP_RIWC_RIWG: |
7617 | { | |
7618 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
7619 | if (!rege | |
7620 | || (rege->type != REG_TYPE_MMXWC | |
7621 | && rege->type != REG_TYPE_MMXWCG)) | |
7622 | { | |
7623 | inst.error = _("iWMMXt control register expected"); | |
7624 | goto failure; | |
7625 | } | |
7626 | inst.operands[i].reg = rege->number; | |
7627 | inst.operands[i].isreg = 1; | |
7628 | } | |
7629 | break; | |
7630 | ||
c19d1205 ZW |
7631 | /* Misc */ |
7632 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
7633 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
7634 | case OP_oROR: val = parse_ror (&str); break; | |
1b883319 | 7635 | try_cond: |
c19d1205 | 7636 | case OP_COND: val = parse_cond (&str); break; |
52e7f43d RE |
7637 | case OP_oBARRIER_I15: |
7638 | po_barrier_or_imm (str); break; | |
7639 | immediate: | |
7640 | if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL) | |
477330fc | 7641 | goto failure; |
52e7f43d | 7642 | break; |
c19d1205 | 7643 | |
fa94de6b | 7644 | case OP_wPSR: |
d2cd1205 | 7645 | case OP_rPSR: |
90ec0d68 MGD |
7646 | po_reg_or_goto (REG_TYPE_RNB, try_psr); |
7647 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt)) | |
7648 | { | |
7649 | inst.error = _("Banked registers are not available with this " | |
7650 | "architecture."); | |
7651 | goto failure; | |
7652 | } | |
7653 | break; | |
d2cd1205 JB |
7654 | try_psr: |
7655 | val = parse_psr (&str, op_parse_code == OP_wPSR); | |
7656 | break; | |
037e8744 | 7657 | |
32c36c3c AV |
7658 | case OP_VLDR: |
7659 | po_reg_or_goto (REG_TYPE_VFSD, try_sysreg); | |
7660 | break; | |
7661 | try_sysreg: | |
7662 | val = parse_sys_vldr_vstr (&str); | |
7663 | break; | |
7664 | ||
477330fc RM |
7665 | case OP_APSR_RR: |
7666 | po_reg_or_goto (REG_TYPE_RN, try_apsr); | |
7667 | break; | |
7668 | try_apsr: | |
7669 | /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS | |
7670 | instruction). */ | |
7671 | if (strncasecmp (str, "APSR_", 5) == 0) | |
7672 | { | |
7673 | unsigned found = 0; | |
7674 | str += 5; | |
7675 | while (found < 15) | |
7676 | switch (*str++) | |
7677 | { | |
7678 | case 'c': found = (found & 1) ? 16 : found | 1; break; | |
7679 | case 'n': found = (found & 2) ? 16 : found | 2; break; | |
7680 | case 'z': found = (found & 4) ? 16 : found | 4; break; | |
7681 | case 'v': found = (found & 8) ? 16 : found | 8; break; | |
7682 | default: found = 16; | |
7683 | } | |
7684 | if (found != 15) | |
7685 | goto failure; | |
7686 | inst.operands[i].isvec = 1; | |
f7c21dc7 NC |
7687 | /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */ |
7688 | inst.operands[i].reg = REG_PC; | |
477330fc RM |
7689 | } |
7690 | else | |
7691 | goto failure; | |
7692 | break; | |
037e8744 | 7693 | |
92e90b6e PB |
7694 | case OP_TB: |
7695 | po_misc_or_fail (parse_tb (&str)); | |
7696 | break; | |
7697 | ||
e07e6e58 | 7698 | /* Register lists. */ |
c19d1205 | 7699 | case OP_REGLST: |
4b5a202f | 7700 | val = parse_reg_list (&str, REGLIST_RN); |
c19d1205 ZW |
7701 | if (*str == '^') |
7702 | { | |
5e0d7f77 | 7703 | inst.operands[i].writeback = 1; |
c19d1205 ZW |
7704 | str++; |
7705 | } | |
7706 | break; | |
09d92015 | 7707 | |
4b5a202f AV |
7708 | case OP_CLRMLST: |
7709 | val = parse_reg_list (&str, REGLIST_CLRM); | |
7710 | break; | |
7711 | ||
c19d1205 | 7712 | case OP_VRSLST: |
efd6b359 AV |
7713 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S, |
7714 | &partial_match); | |
c19d1205 | 7715 | break; |
09d92015 | 7716 | |
c19d1205 | 7717 | case OP_VRDLST: |
efd6b359 AV |
7718 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D, |
7719 | &partial_match); | |
c19d1205 | 7720 | break; |
a737bd4d | 7721 | |
477330fc RM |
7722 | case OP_VRSDLST: |
7723 | /* Allow Q registers too. */ | |
7724 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
efd6b359 | 7725 | REGLIST_NEON_D, &partial_match); |
477330fc RM |
7726 | if (val == FAIL) |
7727 | { | |
7728 | inst.error = NULL; | |
7729 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
efd6b359 AV |
7730 | REGLIST_VFP_S, &partial_match); |
7731 | inst.operands[i].issingle = 1; | |
7732 | } | |
7733 | break; | |
7734 | ||
7735 | case OP_VRSDVLST: | |
7736 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
7737 | REGLIST_VFP_D_VPR, &partial_match); | |
7738 | if (val == FAIL && !partial_match) | |
7739 | { | |
7740 | inst.error = NULL; | |
7741 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
7742 | REGLIST_VFP_S_VPR, &partial_match); | |
477330fc RM |
7743 | inst.operands[i].issingle = 1; |
7744 | } | |
7745 | break; | |
7746 | ||
7747 | case OP_NRDLST: | |
7748 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
efd6b359 | 7749 | REGLIST_NEON_D, &partial_match); |
477330fc | 7750 | break; |
5287ad62 | 7751 | |
35c228db AV |
7752 | case OP_MSTRLST4: |
7753 | case OP_MSTRLST2: | |
7754 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, | |
7755 | 1, &inst.operands[i].vectype); | |
7756 | if (val != (((op_parse_code == OP_MSTRLST2) ? 3 : 7) << 5 | 0xe)) | |
7757 | goto failure; | |
7758 | break; | |
5287ad62 | 7759 | case OP_NSTRLST: |
477330fc | 7760 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, |
35c228db | 7761 | 0, &inst.operands[i].vectype); |
477330fc | 7762 | break; |
5287ad62 | 7763 | |
c19d1205 | 7764 | /* Addressing modes */ |
35c228db AV |
7765 | case OP_ADDRMVE: |
7766 | po_misc_or_fail (parse_address_group_reloc (&str, i, GROUP_MVE)); | |
7767 | break; | |
7768 | ||
c19d1205 ZW |
7769 | case OP_ADDR: |
7770 | po_misc_or_fail (parse_address (&str, i)); | |
7771 | break; | |
09d92015 | 7772 | |
4962c51a MS |
7773 | case OP_ADDRGLDR: |
7774 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7775 | parse_address_group_reloc (&str, i, GROUP_LDR)); |
4962c51a MS |
7776 | break; |
7777 | ||
7778 | case OP_ADDRGLDRS: | |
7779 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7780 | parse_address_group_reloc (&str, i, GROUP_LDRS)); |
4962c51a MS |
7781 | break; |
7782 | ||
7783 | case OP_ADDRGLDC: | |
7784 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7785 | parse_address_group_reloc (&str, i, GROUP_LDC)); |
4962c51a MS |
7786 | break; |
7787 | ||
c19d1205 ZW |
7788 | case OP_SH: |
7789 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
7790 | break; | |
09d92015 | 7791 | |
4962c51a MS |
7792 | case OP_SHG: |
7793 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7794 | parse_shifter_operand_group_reloc (&str, i)); |
4962c51a MS |
7795 | break; |
7796 | ||
c19d1205 ZW |
7797 | case OP_oSHll: |
7798 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
7799 | break; | |
09d92015 | 7800 | |
c19d1205 ZW |
7801 | case OP_oSHar: |
7802 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
7803 | break; | |
09d92015 | 7804 | |
c19d1205 ZW |
7805 | case OP_oSHllar: |
7806 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
7807 | break; | |
09d92015 | 7808 | |
1b883319 AV |
7809 | case OP_RMQRZ: |
7810 | case OP_oRMQRZ: | |
7811 | po_reg_or_goto (REG_TYPE_MQ, try_rr_zr); | |
7812 | break; | |
e39c1607 SD |
7813 | |
7814 | case OP_RR_ZR: | |
1b883319 AV |
7815 | try_rr_zr: |
7816 | po_reg_or_goto (REG_TYPE_RN, ZR); | |
7817 | break; | |
7818 | ZR: | |
7819 | po_reg_or_fail (REG_TYPE_ZR); | |
7820 | break; | |
7821 | ||
c19d1205 | 7822 | default: |
5be8be5d | 7823 | as_fatal (_("unhandled operand code %d"), op_parse_code); |
c19d1205 | 7824 | } |
09d92015 | 7825 | |
c19d1205 ZW |
7826 | /* Various value-based sanity checks and shared operations. We |
7827 | do not signal immediate failures for the register constraints; | |
7828 | this allows a syntax error to take precedence. */ | |
5be8be5d | 7829 | switch (op_parse_code) |
c19d1205 ZW |
7830 | { |
7831 | case OP_oRRnpc: | |
7832 | case OP_RRnpc: | |
7833 | case OP_RRnpcb: | |
7834 | case OP_RRw: | |
b6702015 | 7835 | case OP_oRRw: |
c19d1205 ZW |
7836 | case OP_RRnpc_I0: |
7837 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
7838 | inst.error = BAD_PC; | |
7839 | break; | |
09d92015 | 7840 | |
5be8be5d DG |
7841 | case OP_oRRnpcsp: |
7842 | case OP_RRnpcsp: | |
23d00a41 | 7843 | case OP_RRnpcsp_I32: |
5be8be5d DG |
7844 | if (inst.operands[i].isreg) |
7845 | { | |
7846 | if (inst.operands[i].reg == REG_PC) | |
7847 | inst.error = BAD_PC; | |
5c8ed6a4 JW |
7848 | else if (inst.operands[i].reg == REG_SP |
7849 | /* The restriction on Rd/Rt/Rt2 on Thumb mode has been | |
7850 | relaxed since ARMv8-A. */ | |
7851 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
7852 | { | |
7853 | gas_assert (thumb); | |
7854 | inst.error = BAD_SP; | |
7855 | } | |
5be8be5d DG |
7856 | } |
7857 | break; | |
7858 | ||
55881a11 | 7859 | case OP_RRnpctw: |
fa94de6b RM |
7860 | if (inst.operands[i].isreg |
7861 | && inst.operands[i].reg == REG_PC | |
55881a11 MGD |
7862 | && (inst.operands[i].writeback || thumb)) |
7863 | inst.error = BAD_PC; | |
7864 | break; | |
7865 | ||
1b883319 | 7866 | case OP_RVSD_COND: |
32c36c3c AV |
7867 | case OP_VLDR: |
7868 | if (inst.operands[i].isreg) | |
7869 | break; | |
7870 | /* fall through. */ | |
1b883319 | 7871 | |
c19d1205 ZW |
7872 | case OP_CPSF: |
7873 | case OP_ENDI: | |
7874 | case OP_oROR: | |
d2cd1205 JB |
7875 | case OP_wPSR: |
7876 | case OP_rPSR: | |
c19d1205 | 7877 | case OP_COND: |
52e7f43d | 7878 | case OP_oBARRIER_I15: |
c19d1205 | 7879 | case OP_REGLST: |
4b5a202f | 7880 | case OP_CLRMLST: |
c19d1205 ZW |
7881 | case OP_VRSLST: |
7882 | case OP_VRDLST: | |
477330fc | 7883 | case OP_VRSDLST: |
efd6b359 | 7884 | case OP_VRSDVLST: |
477330fc RM |
7885 | case OP_NRDLST: |
7886 | case OP_NSTRLST: | |
35c228db AV |
7887 | case OP_MSTRLST2: |
7888 | case OP_MSTRLST4: | |
c19d1205 ZW |
7889 | if (val == FAIL) |
7890 | goto failure; | |
7891 | inst.operands[i].imm = val; | |
7892 | break; | |
a737bd4d | 7893 | |
60f993ce AV |
7894 | case OP_LR: |
7895 | case OP_oLR: | |
7896 | if (inst.operands[i].reg != REG_LR) | |
7897 | inst.error = _("operand must be LR register"); | |
7898 | break; | |
7899 | ||
1b883319 AV |
7900 | case OP_RMQRZ: |
7901 | case OP_oRMQRZ: | |
e39c1607 | 7902 | case OP_RR_ZR: |
1b883319 AV |
7903 | if (!inst.operands[i].iszr && inst.operands[i].reg == REG_PC) |
7904 | inst.error = BAD_PC; | |
7905 | break; | |
7906 | ||
a302e574 AV |
7907 | case OP_RRe: |
7908 | if (inst.operands[i].isreg | |
7909 | && (inst.operands[i].reg & 0x00000001) != 0) | |
7910 | inst.error = BAD_ODD; | |
7911 | break; | |
7912 | ||
7913 | case OP_RRo: | |
7914 | if (inst.operands[i].isreg) | |
7915 | { | |
7916 | if ((inst.operands[i].reg & 0x00000001) != 1) | |
7917 | inst.error = BAD_EVEN; | |
7918 | else if (inst.operands[i].reg == REG_SP) | |
7919 | as_tsktsk (MVE_BAD_SP); | |
7920 | else if (inst.operands[i].reg == REG_PC) | |
7921 | inst.error = BAD_PC; | |
7922 | } | |
7923 | break; | |
7924 | ||
c19d1205 ZW |
7925 | default: |
7926 | break; | |
7927 | } | |
09d92015 | 7928 | |
c19d1205 ZW |
7929 | /* If we get here, this operand was successfully parsed. */ |
7930 | inst.operands[i].present = 1; | |
7931 | continue; | |
09d92015 | 7932 | |
c19d1205 | 7933 | bad_args: |
09d92015 | 7934 | inst.error = BAD_ARGS; |
c19d1205 ZW |
7935 | |
7936 | failure: | |
7937 | if (!backtrack_pos) | |
d252fdde PB |
7938 | { |
7939 | /* The parse routine should already have set inst.error, but set a | |
5f4273c7 | 7940 | default here just in case. */ |
d252fdde | 7941 | if (!inst.error) |
5ee91343 | 7942 | inst.error = BAD_SYNTAX; |
d252fdde PB |
7943 | return FAIL; |
7944 | } | |
c19d1205 ZW |
7945 | |
7946 | /* Do not backtrack over a trailing optional argument that | |
7947 | absorbed some text. We will only fail again, with the | |
7948 | 'garbage following instruction' error message, which is | |
7949 | probably less helpful than the current one. */ | |
7950 | if (backtrack_index == i && backtrack_pos != str | |
7951 | && upat[i+1] == OP_stop) | |
d252fdde PB |
7952 | { |
7953 | if (!inst.error) | |
5ee91343 | 7954 | inst.error = BAD_SYNTAX; |
d252fdde PB |
7955 | return FAIL; |
7956 | } | |
c19d1205 ZW |
7957 | |
7958 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
7959 | str = backtrack_pos; | |
7960 | inst.error = backtrack_error; | |
7961 | inst.operands[backtrack_index].present = 0; | |
7962 | i = backtrack_index; | |
7963 | backtrack_pos = 0; | |
09d92015 | 7964 | } |
09d92015 | 7965 | |
c19d1205 ZW |
7966 | /* Check that we have parsed all the arguments. */ |
7967 | if (*str != '\0' && !inst.error) | |
7968 | inst.error = _("garbage following instruction"); | |
09d92015 | 7969 | |
c19d1205 | 7970 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
7971 | } |
7972 | ||
c19d1205 ZW |
7973 | #undef po_char_or_fail |
7974 | #undef po_reg_or_fail | |
7975 | #undef po_reg_or_goto | |
7976 | #undef po_imm_or_fail | |
5287ad62 | 7977 | #undef po_scalar_or_fail |
52e7f43d | 7978 | #undef po_barrier_or_imm |
e07e6e58 | 7979 | |
c19d1205 | 7980 | /* Shorthand macro for instruction encoding functions issuing errors. */ |
e07e6e58 NC |
7981 | #define constraint(expr, err) \ |
7982 | do \ | |
c19d1205 | 7983 | { \ |
e07e6e58 NC |
7984 | if (expr) \ |
7985 | { \ | |
7986 | inst.error = err; \ | |
7987 | return; \ | |
7988 | } \ | |
c19d1205 | 7989 | } \ |
e07e6e58 | 7990 | while (0) |
c19d1205 | 7991 | |
fdfde340 JM |
7992 | /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 |
7993 | instructions are unpredictable if these registers are used. This | |
5c8ed6a4 JW |
7994 | is the BadReg predicate in ARM's Thumb-2 documentation. |
7995 | ||
7996 | Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few | |
7997 | places, while the restriction on REG_SP was relaxed since ARMv8-A. */ | |
7998 | #define reject_bad_reg(reg) \ | |
7999 | do \ | |
8000 | if (reg == REG_PC) \ | |
8001 | { \ | |
8002 | inst.error = BAD_PC; \ | |
8003 | return; \ | |
8004 | } \ | |
8005 | else if (reg == REG_SP \ | |
8006 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \ | |
8007 | { \ | |
8008 | inst.error = BAD_SP; \ | |
8009 | return; \ | |
8010 | } \ | |
fdfde340 JM |
8011 | while (0) |
8012 | ||
94206790 MM |
8013 | /* If REG is R13 (the stack pointer), warn that its use is |
8014 | deprecated. */ | |
8015 | #define warn_deprecated_sp(reg) \ | |
8016 | do \ | |
8017 | if (warn_on_deprecated && reg == REG_SP) \ | |
5c3696f8 | 8018 | as_tsktsk (_("use of r13 is deprecated")); \ |
94206790 MM |
8019 | while (0) |
8020 | ||
c19d1205 ZW |
8021 | /* Functions for operand encoding. ARM, then Thumb. */ |
8022 | ||
d840c081 | 8023 | #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31)) |
c19d1205 | 8024 | |
9db2f6b4 RL |
8025 | /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding. |
8026 | ||
8027 | The only binary encoding difference is the Coprocessor number. Coprocessor | |
8028 | 9 is used for half-precision calculations or conversions. The format of the | |
2b0f3761 | 8029 | instruction is the same as the equivalent Coprocessor 10 instruction that |
9db2f6b4 RL |
8030 | exists for Single-Precision operation. */ |
8031 | ||
8032 | static void | |
8033 | do_scalar_fp16_v82_encode (void) | |
8034 | { | |
5ee91343 | 8035 | if (inst.cond < COND_ALWAYS) |
9db2f6b4 RL |
8036 | as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional," |
8037 | " the behaviour is UNPREDICTABLE")); | |
8038 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16), | |
8039 | _(BAD_FP16)); | |
8040 | ||
8041 | inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900; | |
8042 | mark_feature_used (&arm_ext_fp16); | |
8043 | } | |
8044 | ||
c19d1205 ZW |
8045 | /* If VAL can be encoded in the immediate field of an ARM instruction, |
8046 | return the encoded form. Otherwise, return FAIL. */ | |
8047 | ||
8048 | static unsigned int | |
8049 | encode_arm_immediate (unsigned int val) | |
09d92015 | 8050 | { |
c19d1205 ZW |
8051 | unsigned int a, i; |
8052 | ||
4f1d6205 L |
8053 | if (val <= 0xff) |
8054 | return val; | |
8055 | ||
8056 | for (i = 2; i < 32; i += 2) | |
c19d1205 ZW |
8057 | if ((a = rotate_left (val, i)) <= 0xff) |
8058 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
8059 | ||
8060 | return FAIL; | |
09d92015 MM |
8061 | } |
8062 | ||
c19d1205 ZW |
8063 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
8064 | return the encoded form. Otherwise, return FAIL. */ | |
8065 | static unsigned int | |
8066 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 8067 | { |
c19d1205 | 8068 | unsigned int a, i; |
09d92015 | 8069 | |
9c3c69f2 | 8070 | if (val <= 0xff) |
c19d1205 | 8071 | return val; |
a737bd4d | 8072 | |
9c3c69f2 | 8073 | for (i = 1; i <= 24; i++) |
09d92015 | 8074 | { |
9c3c69f2 PB |
8075 | a = val >> i; |
8076 | if ((val & ~(0xff << i)) == 0) | |
8077 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 8078 | } |
a737bd4d | 8079 | |
c19d1205 ZW |
8080 | a = val & 0xff; |
8081 | if (val == ((a << 16) | a)) | |
8082 | return 0x100 | a; | |
8083 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
8084 | return 0x300 | a; | |
09d92015 | 8085 | |
c19d1205 ZW |
8086 | a = val & 0xff00; |
8087 | if (val == ((a << 16) | a)) | |
8088 | return 0x200 | (a >> 8); | |
a737bd4d | 8089 | |
c19d1205 | 8090 | return FAIL; |
09d92015 | 8091 | } |
5287ad62 | 8092 | /* Encode a VFP SP or DP register number into inst.instruction. */ |
09d92015 MM |
8093 | |
8094 | static void | |
5287ad62 JB |
8095 | encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) |
8096 | { | |
8097 | if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) | |
8098 | && reg > 15) | |
8099 | { | |
b1cc4aeb | 8100 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) |
477330fc RM |
8101 | { |
8102 | if (thumb_mode) | |
8103 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
8104 | fpu_vfp_ext_d32); | |
8105 | else | |
8106 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
8107 | fpu_vfp_ext_d32); | |
8108 | } | |
5287ad62 | 8109 | else |
477330fc RM |
8110 | { |
8111 | first_error (_("D register out of range for selected VFP version")); | |
8112 | return; | |
8113 | } | |
5287ad62 JB |
8114 | } |
8115 | ||
c19d1205 | 8116 | switch (pos) |
09d92015 | 8117 | { |
c19d1205 ZW |
8118 | case VFP_REG_Sd: |
8119 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
8120 | break; | |
8121 | ||
8122 | case VFP_REG_Sn: | |
8123 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
8124 | break; | |
8125 | ||
8126 | case VFP_REG_Sm: | |
8127 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
8128 | break; | |
8129 | ||
5287ad62 JB |
8130 | case VFP_REG_Dd: |
8131 | inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); | |
8132 | break; | |
5f4273c7 | 8133 | |
5287ad62 JB |
8134 | case VFP_REG_Dn: |
8135 | inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); | |
8136 | break; | |
5f4273c7 | 8137 | |
5287ad62 JB |
8138 | case VFP_REG_Dm: |
8139 | inst.instruction |= (reg & 15) | ((reg >> 4) << 5); | |
8140 | break; | |
8141 | ||
c19d1205 ZW |
8142 | default: |
8143 | abort (); | |
09d92015 | 8144 | } |
09d92015 MM |
8145 | } |
8146 | ||
c19d1205 | 8147 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 8148 | if any, is handled by md_apply_fix. */ |
09d92015 | 8149 | static void |
c19d1205 | 8150 | encode_arm_shift (int i) |
09d92015 | 8151 | { |
008a97ef RL |
8152 | /* register-shifted register. */ |
8153 | if (inst.operands[i].immisreg) | |
8154 | { | |
bf355b69 MR |
8155 | int op_index; |
8156 | for (op_index = 0; op_index <= i; ++op_index) | |
008a97ef | 8157 | { |
5689c942 RL |
8158 | /* Check the operand only when it's presented. In pre-UAL syntax, |
8159 | if the destination register is the same as the first operand, two | |
8160 | register form of the instruction can be used. */ | |
bf355b69 MR |
8161 | if (inst.operands[op_index].present && inst.operands[op_index].isreg |
8162 | && inst.operands[op_index].reg == REG_PC) | |
008a97ef RL |
8163 | as_warn (UNPRED_REG ("r15")); |
8164 | } | |
8165 | ||
8166 | if (inst.operands[i].imm == REG_PC) | |
8167 | as_warn (UNPRED_REG ("r15")); | |
8168 | } | |
8169 | ||
c19d1205 ZW |
8170 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
8171 | inst.instruction |= SHIFT_ROR << 5; | |
8172 | else | |
09d92015 | 8173 | { |
c19d1205 ZW |
8174 | inst.instruction |= inst.operands[i].shift_kind << 5; |
8175 | if (inst.operands[i].immisreg) | |
8176 | { | |
8177 | inst.instruction |= SHIFT_BY_REG; | |
8178 | inst.instruction |= inst.operands[i].imm << 8; | |
8179 | } | |
8180 | else | |
e2b0ab59 | 8181 | inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM; |
09d92015 | 8182 | } |
c19d1205 | 8183 | } |
09d92015 | 8184 | |
c19d1205 ZW |
8185 | static void |
8186 | encode_arm_shifter_operand (int i) | |
8187 | { | |
8188 | if (inst.operands[i].isreg) | |
09d92015 | 8189 | { |
c19d1205 ZW |
8190 | inst.instruction |= inst.operands[i].reg; |
8191 | encode_arm_shift (i); | |
09d92015 | 8192 | } |
c19d1205 | 8193 | else |
a415b1cd JB |
8194 | { |
8195 | inst.instruction |= INST_IMMEDIATE; | |
e2b0ab59 | 8196 | if (inst.relocs[0].type != BFD_RELOC_ARM_IMMEDIATE) |
a415b1cd JB |
8197 | inst.instruction |= inst.operands[i].imm; |
8198 | } | |
09d92015 MM |
8199 | } |
8200 | ||
c19d1205 | 8201 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 8202 | static void |
c19d1205 | 8203 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 8204 | { |
2b2f5df9 NC |
8205 | /* PR 14260: |
8206 | Generate an error if the operand is not a register. */ | |
8207 | constraint (!inst.operands[i].isreg, | |
8208 | _("Instruction does not support =N addresses")); | |
8209 | ||
c19d1205 | 8210 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 8211 | |
c19d1205 | 8212 | if (inst.operands[i].preind) |
09d92015 | 8213 | { |
c19d1205 ZW |
8214 | if (is_t) |
8215 | { | |
8216 | inst.error = _("instruction does not accept preindexed addressing"); | |
8217 | return; | |
8218 | } | |
8219 | inst.instruction |= PRE_INDEX; | |
8220 | if (inst.operands[i].writeback) | |
8221 | inst.instruction |= WRITE_BACK; | |
09d92015 | 8222 | |
c19d1205 ZW |
8223 | } |
8224 | else if (inst.operands[i].postind) | |
8225 | { | |
9c2799c2 | 8226 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
8227 | if (is_t) |
8228 | inst.instruction |= WRITE_BACK; | |
8229 | } | |
8230 | else /* unindexed - only for coprocessor */ | |
09d92015 | 8231 | { |
c19d1205 | 8232 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
8233 | return; |
8234 | } | |
8235 | ||
c19d1205 ZW |
8236 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
8237 | && (((inst.instruction & 0x000f0000) >> 16) | |
8238 | == ((inst.instruction & 0x0000f000) >> 12))) | |
8239 | as_warn ((inst.instruction & LOAD_BIT) | |
8240 | ? _("destination register same as write-back base") | |
8241 | : _("source register same as write-back base")); | |
09d92015 MM |
8242 | } |
8243 | ||
c19d1205 ZW |
8244 | /* inst.operands[i] was set up by parse_address. Encode it into an |
8245 | ARM-format mode 2 load or store instruction. If is_t is true, | |
8246 | reject forms that cannot be used with a T instruction (i.e. not | |
8247 | post-indexed). */ | |
a737bd4d | 8248 | static void |
c19d1205 | 8249 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 8250 | { |
5be8be5d DG |
8251 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
8252 | ||
c19d1205 | 8253 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 8254 | |
c19d1205 | 8255 | if (inst.operands[i].immisreg) |
09d92015 | 8256 | { |
5be8be5d DG |
8257 | constraint ((inst.operands[i].imm == REG_PC |
8258 | || (is_pc && inst.operands[i].writeback)), | |
8259 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
8260 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
8261 | inst.instruction |= inst.operands[i].imm; | |
8262 | if (!inst.operands[i].negative) | |
8263 | inst.instruction |= INDEX_UP; | |
8264 | if (inst.operands[i].shifted) | |
8265 | { | |
8266 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
8267 | inst.instruction |= SHIFT_ROR << 5; | |
8268 | else | |
8269 | { | |
8270 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
e2b0ab59 | 8271 | inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM; |
c19d1205 ZW |
8272 | } |
8273 | } | |
09d92015 | 8274 | } |
e2b0ab59 | 8275 | else /* immediate offset in inst.relocs[0] */ |
09d92015 | 8276 | { |
e2b0ab59 | 8277 | if (is_pc && !inst.relocs[0].pc_rel) |
5be8be5d DG |
8278 | { |
8279 | const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0); | |
23a10334 JZ |
8280 | |
8281 | /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt | |
8282 | cannot use PC in addressing. | |
8283 | PC cannot be used in writeback addressing, either. */ | |
8284 | constraint ((is_t || inst.operands[i].writeback), | |
5be8be5d | 8285 | BAD_PC_ADDRESSING); |
23a10334 | 8286 | |
dc5ec521 | 8287 | /* Use of PC in str is deprecated for ARMv7. */ |
23a10334 JZ |
8288 | if (warn_on_deprecated |
8289 | && !is_load | |
8290 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) | |
5c3696f8 | 8291 | as_tsktsk (_("use of PC in this instruction is deprecated")); |
5be8be5d DG |
8292 | } |
8293 | ||
e2b0ab59 | 8294 | if (inst.relocs[0].type == BFD_RELOC_UNUSED) |
26d97720 NS |
8295 | { |
8296 | /* Prefer + for zero encoded value. */ | |
8297 | if (!inst.operands[i].negative) | |
8298 | inst.instruction |= INDEX_UP; | |
e2b0ab59 | 8299 | inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM; |
26d97720 | 8300 | } |
09d92015 | 8301 | } |
09d92015 MM |
8302 | } |
8303 | ||
c19d1205 ZW |
8304 | /* inst.operands[i] was set up by parse_address. Encode it into an |
8305 | ARM-format mode 3 load or store instruction. Reject forms that | |
8306 | cannot be used with such instructions. If is_t is true, reject | |
8307 | forms that cannot be used with a T instruction (i.e. not | |
8308 | post-indexed). */ | |
8309 | static void | |
8310 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 8311 | { |
c19d1205 | 8312 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 8313 | { |
c19d1205 ZW |
8314 | inst.error = _("instruction does not accept scaled register index"); |
8315 | return; | |
09d92015 | 8316 | } |
a737bd4d | 8317 | |
c19d1205 | 8318 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 8319 | |
c19d1205 ZW |
8320 | if (inst.operands[i].immisreg) |
8321 | { | |
5be8be5d | 8322 | constraint ((inst.operands[i].imm == REG_PC |
eb9f3f00 | 8323 | || (is_t && inst.operands[i].reg == REG_PC)), |
5be8be5d | 8324 | BAD_PC_ADDRESSING); |
eb9f3f00 JB |
8325 | constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback, |
8326 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
8327 | inst.instruction |= inst.operands[i].imm; |
8328 | if (!inst.operands[i].negative) | |
8329 | inst.instruction |= INDEX_UP; | |
8330 | } | |
e2b0ab59 | 8331 | else /* immediate offset in inst.relocs[0] */ |
c19d1205 | 8332 | { |
e2b0ab59 | 8333 | constraint ((inst.operands[i].reg == REG_PC && !inst.relocs[0].pc_rel |
5be8be5d DG |
8334 | && inst.operands[i].writeback), |
8335 | BAD_PC_WRITEBACK); | |
c19d1205 | 8336 | inst.instruction |= HWOFFSET_IMM; |
e2b0ab59 | 8337 | if (inst.relocs[0].type == BFD_RELOC_UNUSED) |
26d97720 NS |
8338 | { |
8339 | /* Prefer + for zero encoded value. */ | |
8340 | if (!inst.operands[i].negative) | |
8341 | inst.instruction |= INDEX_UP; | |
8342 | ||
e2b0ab59 | 8343 | inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM8; |
26d97720 | 8344 | } |
c19d1205 | 8345 | } |
a737bd4d NC |
8346 | } |
8347 | ||
8335d6aa JW |
8348 | /* Write immediate bits [7:0] to the following locations: |
8349 | ||
8350 | |28/24|23 19|18 16|15 4|3 0| | |
8351 | | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| | |
8352 | ||
8353 | This function is used by VMOV/VMVN/VORR/VBIC. */ | |
8354 | ||
8355 | static void | |
8356 | neon_write_immbits (unsigned immbits) | |
8357 | { | |
8358 | inst.instruction |= immbits & 0xf; | |
8359 | inst.instruction |= ((immbits >> 4) & 0x7) << 16; | |
8360 | inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24); | |
8361 | } | |
8362 | ||
8363 | /* Invert low-order SIZE bits of XHI:XLO. */ | |
8364 | ||
8365 | static void | |
8366 | neon_invert_size (unsigned *xlo, unsigned *xhi, int size) | |
8367 | { | |
8368 | unsigned immlo = xlo ? *xlo : 0; | |
8369 | unsigned immhi = xhi ? *xhi : 0; | |
8370 | ||
8371 | switch (size) | |
8372 | { | |
8373 | case 8: | |
8374 | immlo = (~immlo) & 0xff; | |
8375 | break; | |
8376 | ||
8377 | case 16: | |
8378 | immlo = (~immlo) & 0xffff; | |
8379 | break; | |
8380 | ||
8381 | case 64: | |
8382 | immhi = (~immhi) & 0xffffffff; | |
8383 | /* fall through. */ | |
8384 | ||
8385 | case 32: | |
8386 | immlo = (~immlo) & 0xffffffff; | |
8387 | break; | |
8388 | ||
8389 | default: | |
8390 | abort (); | |
8391 | } | |
8392 | ||
8393 | if (xlo) | |
8394 | *xlo = immlo; | |
8395 | ||
8396 | if (xhi) | |
8397 | *xhi = immhi; | |
8398 | } | |
8399 | ||
8400 | /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits | |
8401 | A, B, C, D. */ | |
09d92015 | 8402 | |
c19d1205 | 8403 | static int |
8335d6aa | 8404 | neon_bits_same_in_bytes (unsigned imm) |
09d92015 | 8405 | { |
8335d6aa JW |
8406 | return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) |
8407 | && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) | |
8408 | && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) | |
8409 | && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); | |
8410 | } | |
a737bd4d | 8411 | |
8335d6aa | 8412 | /* For immediate of above form, return 0bABCD. */ |
09d92015 | 8413 | |
8335d6aa JW |
8414 | static unsigned |
8415 | neon_squash_bits (unsigned imm) | |
8416 | { | |
8417 | return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) | |
8418 | | ((imm & 0x01000000) >> 21); | |
8419 | } | |
8420 | ||
8421 | /* Compress quarter-float representation to 0b...000 abcdefgh. */ | |
8422 | ||
8423 | static unsigned | |
8424 | neon_qfloat_bits (unsigned imm) | |
8425 | { | |
8426 | return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); | |
8427 | } | |
8428 | ||
8429 | /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into | |
8430 | the instruction. *OP is passed as the initial value of the op field, and | |
8431 | may be set to a different value depending on the constant (i.e. | |
8432 | "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not | |
8433 | MVN). If the immediate looks like a repeated pattern then also | |
8434 | try smaller element sizes. */ | |
8435 | ||
8436 | static int | |
8437 | neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, | |
8438 | unsigned *immbits, int *op, int size, | |
8439 | enum neon_el_type type) | |
8440 | { | |
8441 | /* Only permit float immediates (including 0.0/-0.0) if the operand type is | |
8442 | float. */ | |
8443 | if (type == NT_float && !float_p) | |
8444 | return FAIL; | |
8445 | ||
8446 | if (type == NT_float && is_quarter_float (immlo) && immhi == 0) | |
09d92015 | 8447 | { |
8335d6aa JW |
8448 | if (size != 32 || *op == 1) |
8449 | return FAIL; | |
8450 | *immbits = neon_qfloat_bits (immlo); | |
8451 | return 0xf; | |
8452 | } | |
8453 | ||
8454 | if (size == 64) | |
8455 | { | |
8456 | if (neon_bits_same_in_bytes (immhi) | |
8457 | && neon_bits_same_in_bytes (immlo)) | |
c19d1205 | 8458 | { |
8335d6aa JW |
8459 | if (*op == 1) |
8460 | return FAIL; | |
8461 | *immbits = (neon_squash_bits (immhi) << 4) | |
8462 | | neon_squash_bits (immlo); | |
8463 | *op = 1; | |
8464 | return 0xe; | |
c19d1205 | 8465 | } |
a737bd4d | 8466 | |
8335d6aa JW |
8467 | if (immhi != immlo) |
8468 | return FAIL; | |
8469 | } | |
a737bd4d | 8470 | |
8335d6aa | 8471 | if (size >= 32) |
09d92015 | 8472 | { |
8335d6aa | 8473 | if (immlo == (immlo & 0x000000ff)) |
c19d1205 | 8474 | { |
8335d6aa JW |
8475 | *immbits = immlo; |
8476 | return 0x0; | |
c19d1205 | 8477 | } |
8335d6aa | 8478 | else if (immlo == (immlo & 0x0000ff00)) |
c19d1205 | 8479 | { |
8335d6aa JW |
8480 | *immbits = immlo >> 8; |
8481 | return 0x2; | |
c19d1205 | 8482 | } |
8335d6aa JW |
8483 | else if (immlo == (immlo & 0x00ff0000)) |
8484 | { | |
8485 | *immbits = immlo >> 16; | |
8486 | return 0x4; | |
8487 | } | |
8488 | else if (immlo == (immlo & 0xff000000)) | |
8489 | { | |
8490 | *immbits = immlo >> 24; | |
8491 | return 0x6; | |
8492 | } | |
8493 | else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) | |
8494 | { | |
8495 | *immbits = (immlo >> 8) & 0xff; | |
8496 | return 0xc; | |
8497 | } | |
8498 | else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) | |
8499 | { | |
8500 | *immbits = (immlo >> 16) & 0xff; | |
8501 | return 0xd; | |
8502 | } | |
8503 | ||
8504 | if ((immlo & 0xffff) != (immlo >> 16)) | |
8505 | return FAIL; | |
8506 | immlo &= 0xffff; | |
09d92015 | 8507 | } |
a737bd4d | 8508 | |
8335d6aa | 8509 | if (size >= 16) |
4962c51a | 8510 | { |
8335d6aa JW |
8511 | if (immlo == (immlo & 0x000000ff)) |
8512 | { | |
8513 | *immbits = immlo; | |
8514 | return 0x8; | |
8515 | } | |
8516 | else if (immlo == (immlo & 0x0000ff00)) | |
8517 | { | |
8518 | *immbits = immlo >> 8; | |
8519 | return 0xa; | |
8520 | } | |
8521 | ||
8522 | if ((immlo & 0xff) != (immlo >> 8)) | |
8523 | return FAIL; | |
8524 | immlo &= 0xff; | |
4962c51a MS |
8525 | } |
8526 | ||
8335d6aa JW |
8527 | if (immlo == (immlo & 0x000000ff)) |
8528 | { | |
8529 | /* Don't allow MVN with 8-bit immediate. */ | |
8530 | if (*op == 1) | |
8531 | return FAIL; | |
8532 | *immbits = immlo; | |
8533 | return 0xe; | |
8534 | } | |
26d97720 | 8535 | |
8335d6aa | 8536 | return FAIL; |
c19d1205 | 8537 | } |
a737bd4d | 8538 | |
5fc177c8 | 8539 | #if defined BFD_HOST_64_BIT |
ba592044 AM |
8540 | /* Returns TRUE if double precision value V may be cast |
8541 | to single precision without loss of accuracy. */ | |
8542 | ||
8543 | static bfd_boolean | |
5fc177c8 | 8544 | is_double_a_single (bfd_int64_t v) |
ba592044 | 8545 | { |
5fc177c8 | 8546 | int exp = (int)((v >> 52) & 0x7FF); |
8fe3f3d6 | 8547 | bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL); |
ba592044 AM |
8548 | |
8549 | return (exp == 0 || exp == 0x7FF | |
8550 | || (exp >= 1023 - 126 && exp <= 1023 + 127)) | |
8551 | && (mantissa & 0x1FFFFFFFl) == 0; | |
8552 | } | |
8553 | ||
3739860c | 8554 | /* Returns a double precision value casted to single precision |
ba592044 AM |
8555 | (ignoring the least significant bits in exponent and mantissa). */ |
8556 | ||
8557 | static int | |
5fc177c8 | 8558 | double_to_single (bfd_int64_t v) |
ba592044 AM |
8559 | { |
8560 | int sign = (int) ((v >> 63) & 1l); | |
5fc177c8 | 8561 | int exp = (int) ((v >> 52) & 0x7FF); |
8fe3f3d6 | 8562 | bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL); |
ba592044 AM |
8563 | |
8564 | if (exp == 0x7FF) | |
8565 | exp = 0xFF; | |
8566 | else | |
8567 | { | |
8568 | exp = exp - 1023 + 127; | |
8569 | if (exp >= 0xFF) | |
8570 | { | |
8571 | /* Infinity. */ | |
8572 | exp = 0x7F; | |
8573 | mantissa = 0; | |
8574 | } | |
8575 | else if (exp < 0) | |
8576 | { | |
8577 | /* No denormalized numbers. */ | |
8578 | exp = 0; | |
8579 | mantissa = 0; | |
8580 | } | |
8581 | } | |
8582 | mantissa >>= 29; | |
8583 | return (sign << 31) | (exp << 23) | mantissa; | |
8584 | } | |
5fc177c8 | 8585 | #endif /* BFD_HOST_64_BIT */ |
ba592044 | 8586 | |
8335d6aa JW |
8587 | enum lit_type |
8588 | { | |
8589 | CONST_THUMB, | |
8590 | CONST_ARM, | |
8591 | CONST_VEC | |
8592 | }; | |
8593 | ||
ba592044 AM |
8594 | static void do_vfp_nsyn_opcode (const char *); |
8595 | ||
e2b0ab59 | 8596 | /* inst.relocs[0].exp describes an "=expr" load pseudo-operation. |
c19d1205 ZW |
8597 | Determine whether it can be performed with a move instruction; if |
8598 | it can, convert inst.instruction to that move instruction and | |
c921be7d NC |
8599 | return TRUE; if it can't, convert inst.instruction to a literal-pool |
8600 | load and return FALSE. If this is not a valid thing to do in the | |
8601 | current context, set inst.error and return TRUE. | |
a737bd4d | 8602 | |
c19d1205 ZW |
8603 | inst.operands[i] describes the destination register. */ |
8604 | ||
c921be7d | 8605 | static bfd_boolean |
8335d6aa | 8606 | move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3) |
c19d1205 | 8607 | { |
53365c0d | 8608 | unsigned long tbit; |
8335d6aa JW |
8609 | bfd_boolean thumb_p = (t == CONST_THUMB); |
8610 | bfd_boolean arm_p = (t == CONST_ARM); | |
53365c0d PB |
8611 | |
8612 | if (thumb_p) | |
8613 | tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; | |
8614 | else | |
8615 | tbit = LOAD_BIT; | |
8616 | ||
8617 | if ((inst.instruction & tbit) == 0) | |
09d92015 | 8618 | { |
c19d1205 | 8619 | inst.error = _("invalid pseudo operation"); |
c921be7d | 8620 | return TRUE; |
09d92015 | 8621 | } |
ba592044 | 8622 | |
e2b0ab59 AV |
8623 | if (inst.relocs[0].exp.X_op != O_constant |
8624 | && inst.relocs[0].exp.X_op != O_symbol | |
8625 | && inst.relocs[0].exp.X_op != O_big) | |
09d92015 MM |
8626 | { |
8627 | inst.error = _("constant expression expected"); | |
c921be7d | 8628 | return TRUE; |
09d92015 | 8629 | } |
ba592044 | 8630 | |
e2b0ab59 AV |
8631 | if (inst.relocs[0].exp.X_op == O_constant |
8632 | || inst.relocs[0].exp.X_op == O_big) | |
8335d6aa | 8633 | { |
5fc177c8 NC |
8634 | #if defined BFD_HOST_64_BIT |
8635 | bfd_int64_t v; | |
8636 | #else | |
ba592044 | 8637 | offsetT v; |
5fc177c8 | 8638 | #endif |
e2b0ab59 | 8639 | if (inst.relocs[0].exp.X_op == O_big) |
8335d6aa | 8640 | { |
ba592044 AM |
8641 | LITTLENUM_TYPE w[X_PRECISION]; |
8642 | LITTLENUM_TYPE * l; | |
8643 | ||
e2b0ab59 | 8644 | if (inst.relocs[0].exp.X_add_number == -1) |
8335d6aa | 8645 | { |
ba592044 AM |
8646 | gen_to_words (w, X_PRECISION, E_PRECISION); |
8647 | l = w; | |
8648 | /* FIXME: Should we check words w[2..5] ? */ | |
8335d6aa | 8649 | } |
ba592044 AM |
8650 | else |
8651 | l = generic_bignum; | |
3739860c | 8652 | |
5fc177c8 NC |
8653 | #if defined BFD_HOST_64_BIT |
8654 | v = | |
8655 | ((((((((bfd_int64_t) l[3] & LITTLENUM_MASK) | |
8656 | << LITTLENUM_NUMBER_OF_BITS) | |
8657 | | ((bfd_int64_t) l[2] & LITTLENUM_MASK)) | |
8658 | << LITTLENUM_NUMBER_OF_BITS) | |
8659 | | ((bfd_int64_t) l[1] & LITTLENUM_MASK)) | |
8660 | << LITTLENUM_NUMBER_OF_BITS) | |
8661 | | ((bfd_int64_t) l[0] & LITTLENUM_MASK)); | |
8662 | #else | |
ba592044 AM |
8663 | v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS) |
8664 | | (l[0] & LITTLENUM_MASK); | |
5fc177c8 | 8665 | #endif |
8335d6aa | 8666 | } |
ba592044 | 8667 | else |
e2b0ab59 | 8668 | v = inst.relocs[0].exp.X_add_number; |
ba592044 AM |
8669 | |
8670 | if (!inst.operands[i].issingle) | |
8335d6aa | 8671 | { |
12569877 | 8672 | if (thumb_p) |
8335d6aa | 8673 | { |
53445554 TP |
8674 | /* LDR should not use lead in a flag-setting instruction being |
8675 | chosen so we do not check whether movs can be used. */ | |
12569877 | 8676 | |
53445554 | 8677 | if ((ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2) |
ff8646ee | 8678 | || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)) |
53445554 TP |
8679 | && inst.operands[i].reg != 13 |
8680 | && inst.operands[i].reg != 15) | |
12569877 | 8681 | { |
fc289b0a TP |
8682 | /* Check if on thumb2 it can be done with a mov.w, mvn or |
8683 | movw instruction. */ | |
12569877 AM |
8684 | unsigned int newimm; |
8685 | bfd_boolean isNegated; | |
8686 | ||
8687 | newimm = encode_thumb32_immediate (v); | |
8688 | if (newimm != (unsigned int) FAIL) | |
8689 | isNegated = FALSE; | |
8690 | else | |
8691 | { | |
582cfe03 | 8692 | newimm = encode_thumb32_immediate (~v); |
12569877 AM |
8693 | if (newimm != (unsigned int) FAIL) |
8694 | isNegated = TRUE; | |
8695 | } | |
8696 | ||
fc289b0a TP |
8697 | /* The number can be loaded with a mov.w or mvn |
8698 | instruction. */ | |
ff8646ee TP |
8699 | if (newimm != (unsigned int) FAIL |
8700 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)) | |
12569877 | 8701 | { |
fc289b0a | 8702 | inst.instruction = (0xf04f0000 /* MOV.W. */ |
582cfe03 | 8703 | | (inst.operands[i].reg << 8)); |
fc289b0a | 8704 | /* Change to MOVN. */ |
582cfe03 | 8705 | inst.instruction |= (isNegated ? 0x200000 : 0); |
12569877 AM |
8706 | inst.instruction |= (newimm & 0x800) << 15; |
8707 | inst.instruction |= (newimm & 0x700) << 4; | |
8708 | inst.instruction |= (newimm & 0x0ff); | |
8709 | return TRUE; | |
8710 | } | |
fc289b0a | 8711 | /* The number can be loaded with a movw instruction. */ |
ff8646ee TP |
8712 | else if ((v & ~0xFFFF) == 0 |
8713 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)) | |
3739860c | 8714 | { |
582cfe03 | 8715 | int imm = v & 0xFFFF; |
12569877 | 8716 | |
582cfe03 | 8717 | inst.instruction = 0xf2400000; /* MOVW. */ |
12569877 AM |
8718 | inst.instruction |= (inst.operands[i].reg << 8); |
8719 | inst.instruction |= (imm & 0xf000) << 4; | |
8720 | inst.instruction |= (imm & 0x0800) << 15; | |
8721 | inst.instruction |= (imm & 0x0700) << 4; | |
8722 | inst.instruction |= (imm & 0x00ff); | |
8fe9a076 AV |
8723 | /* In case this replacement is being done on Armv8-M |
8724 | Baseline we need to make sure to disable the | |
8725 | instruction size check, as otherwise GAS will reject | |
8726 | the use of this T32 instruction. */ | |
8727 | inst.size_req = 0; | |
12569877 AM |
8728 | return TRUE; |
8729 | } | |
8730 | } | |
8335d6aa | 8731 | } |
12569877 | 8732 | else if (arm_p) |
ba592044 AM |
8733 | { |
8734 | int value = encode_arm_immediate (v); | |
12569877 | 8735 | |
ba592044 AM |
8736 | if (value != FAIL) |
8737 | { | |
8738 | /* This can be done with a mov instruction. */ | |
8739 | inst.instruction &= LITERAL_MASK; | |
8740 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
8741 | inst.instruction |= value & 0xfff; | |
8742 | return TRUE; | |
8743 | } | |
8335d6aa | 8744 | |
ba592044 AM |
8745 | value = encode_arm_immediate (~ v); |
8746 | if (value != FAIL) | |
8747 | { | |
8748 | /* This can be done with a mvn instruction. */ | |
8749 | inst.instruction &= LITERAL_MASK; | |
8750 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
8751 | inst.instruction |= value & 0xfff; | |
8752 | return TRUE; | |
8753 | } | |
8754 | } | |
934c2632 | 8755 | else if (t == CONST_VEC && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) |
8335d6aa | 8756 | { |
ba592044 AM |
8757 | int op = 0; |
8758 | unsigned immbits = 0; | |
8759 | unsigned immlo = inst.operands[1].imm; | |
8760 | unsigned immhi = inst.operands[1].regisimm | |
8761 | ? inst.operands[1].reg | |
e2b0ab59 | 8762 | : inst.relocs[0].exp.X_unsigned |
ba592044 AM |
8763 | ? 0 |
8764 | : ((bfd_int64_t)((int) immlo)) >> 32; | |
8765 | int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits, | |
8766 | &op, 64, NT_invtype); | |
8767 | ||
8768 | if (cmode == FAIL) | |
8769 | { | |
8770 | neon_invert_size (&immlo, &immhi, 64); | |
8771 | op = !op; | |
8772 | cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits, | |
8773 | &op, 64, NT_invtype); | |
8774 | } | |
8775 | ||
8776 | if (cmode != FAIL) | |
8777 | { | |
8778 | inst.instruction = (inst.instruction & VLDR_VMOV_SAME) | |
8779 | | (1 << 23) | |
8780 | | (cmode << 8) | |
8781 | | (op << 5) | |
8782 | | (1 << 4); | |
8783 | ||
8784 | /* Fill other bits in vmov encoding for both thumb and arm. */ | |
8785 | if (thumb_mode) | |
eff0bc54 | 8786 | inst.instruction |= (0x7U << 29) | (0xF << 24); |
ba592044 | 8787 | else |
eff0bc54 | 8788 | inst.instruction |= (0xFU << 28) | (0x1 << 25); |
ba592044 AM |
8789 | neon_write_immbits (immbits); |
8790 | return TRUE; | |
8791 | } | |
8335d6aa JW |
8792 | } |
8793 | } | |
8335d6aa | 8794 | |
ba592044 AM |
8795 | if (t == CONST_VEC) |
8796 | { | |
8797 | /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */ | |
8798 | if (inst.operands[i].issingle | |
8799 | && is_quarter_float (inst.operands[1].imm) | |
8800 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd)) | |
8335d6aa | 8801 | { |
ba592044 AM |
8802 | inst.operands[1].imm = |
8803 | neon_qfloat_bits (v); | |
8804 | do_vfp_nsyn_opcode ("fconsts"); | |
8805 | return TRUE; | |
8335d6aa | 8806 | } |
5fc177c8 NC |
8807 | |
8808 | /* If our host does not support a 64-bit type then we cannot perform | |
8809 | the following optimization. This mean that there will be a | |
8810 | discrepancy between the output produced by an assembler built for | |
8811 | a 32-bit-only host and the output produced from a 64-bit host, but | |
8812 | this cannot be helped. */ | |
8813 | #if defined BFD_HOST_64_BIT | |
ba592044 AM |
8814 | else if (!inst.operands[1].issingle |
8815 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) | |
8335d6aa | 8816 | { |
ba592044 AM |
8817 | if (is_double_a_single (v) |
8818 | && is_quarter_float (double_to_single (v))) | |
8819 | { | |
8820 | inst.operands[1].imm = | |
8821 | neon_qfloat_bits (double_to_single (v)); | |
8822 | do_vfp_nsyn_opcode ("fconstd"); | |
8823 | return TRUE; | |
8824 | } | |
8335d6aa | 8825 | } |
5fc177c8 | 8826 | #endif |
8335d6aa JW |
8827 | } |
8828 | } | |
8829 | ||
8830 | if (add_to_lit_pool ((!inst.operands[i].isvec | |
8831 | || inst.operands[i].issingle) ? 4 : 8) == FAIL) | |
8832 | return TRUE; | |
8833 | ||
8834 | inst.operands[1].reg = REG_PC; | |
8835 | inst.operands[1].isreg = 1; | |
8836 | inst.operands[1].preind = 1; | |
e2b0ab59 AV |
8837 | inst.relocs[0].pc_rel = 1; |
8838 | inst.relocs[0].type = (thumb_p | |
8335d6aa JW |
8839 | ? BFD_RELOC_ARM_THUMB_OFFSET |
8840 | : (mode_3 | |
8841 | ? BFD_RELOC_ARM_HWLITERAL | |
8842 | : BFD_RELOC_ARM_LITERAL)); | |
8843 | return FALSE; | |
8844 | } | |
8845 | ||
8846 | /* inst.operands[i] was set up by parse_address. Encode it into an | |
8847 | ARM-format instruction. Reject all forms which cannot be encoded | |
8848 | into a coprocessor load/store instruction. If wb_ok is false, | |
8849 | reject use of writeback; if unind_ok is false, reject use of | |
8850 | unindexed addressing. If reloc_override is not 0, use it instead | |
8851 | of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one | |
8852 | (in which case it is preserved). */ | |
8853 | ||
8854 | static int | |
8855 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
8856 | { | |
8857 | if (!inst.operands[i].isreg) | |
8858 | { | |
99b2a2dd NC |
8859 | /* PR 18256 */ |
8860 | if (! inst.operands[0].isvec) | |
8861 | { | |
8862 | inst.error = _("invalid co-processor operand"); | |
8863 | return FAIL; | |
8864 | } | |
8335d6aa JW |
8865 | if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE)) |
8866 | return SUCCESS; | |
8867 | } | |
8868 | ||
8869 | inst.instruction |= inst.operands[i].reg << 16; | |
8870 | ||
8871 | gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); | |
8872 | ||
8873 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ | |
8874 | { | |
8875 | gas_assert (!inst.operands[i].writeback); | |
8876 | if (!unind_ok) | |
8877 | { | |
8878 | inst.error = _("instruction does not support unindexed addressing"); | |
8879 | return FAIL; | |
8880 | } | |
8881 | inst.instruction |= inst.operands[i].imm; | |
8882 | inst.instruction |= INDEX_UP; | |
8883 | return SUCCESS; | |
8884 | } | |
8885 | ||
8886 | if (inst.operands[i].preind) | |
8887 | inst.instruction |= PRE_INDEX; | |
8888 | ||
8889 | if (inst.operands[i].writeback) | |
09d92015 | 8890 | { |
8335d6aa | 8891 | if (inst.operands[i].reg == REG_PC) |
c19d1205 | 8892 | { |
8335d6aa JW |
8893 | inst.error = _("pc may not be used with write-back"); |
8894 | return FAIL; | |
c19d1205 | 8895 | } |
8335d6aa | 8896 | if (!wb_ok) |
c19d1205 | 8897 | { |
8335d6aa JW |
8898 | inst.error = _("instruction does not support writeback"); |
8899 | return FAIL; | |
c19d1205 | 8900 | } |
8335d6aa | 8901 | inst.instruction |= WRITE_BACK; |
09d92015 MM |
8902 | } |
8903 | ||
8335d6aa | 8904 | if (reloc_override) |
e2b0ab59 AV |
8905 | inst.relocs[0].type = (bfd_reloc_code_real_type) reloc_override; |
8906 | else if ((inst.relocs[0].type < BFD_RELOC_ARM_ALU_PC_G0_NC | |
8907 | || inst.relocs[0].type > BFD_RELOC_ARM_LDC_SB_G2) | |
8908 | && inst.relocs[0].type != BFD_RELOC_ARM_LDR_PC_G0) | |
c19d1205 | 8909 | { |
8335d6aa | 8910 | if (thumb_mode) |
e2b0ab59 | 8911 | inst.relocs[0].type = BFD_RELOC_ARM_T32_CP_OFF_IMM; |
8335d6aa | 8912 | else |
e2b0ab59 | 8913 | inst.relocs[0].type = BFD_RELOC_ARM_CP_OFF_IMM; |
c19d1205 | 8914 | } |
8335d6aa JW |
8915 | |
8916 | /* Prefer + for zero encoded value. */ | |
8917 | if (!inst.operands[i].negative) | |
8918 | inst.instruction |= INDEX_UP; | |
8919 | ||
8920 | return SUCCESS; | |
09d92015 MM |
8921 | } |
8922 | ||
5f4273c7 | 8923 | /* Functions for instruction encoding, sorted by sub-architecture. |
c19d1205 ZW |
8924 | First some generics; their names are taken from the conventional |
8925 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 8926 | |
a737bd4d | 8927 | static void |
c19d1205 | 8928 | do_noargs (void) |
09d92015 | 8929 | { |
c19d1205 | 8930 | } |
a737bd4d | 8931 | |
c19d1205 ZW |
8932 | static void |
8933 | do_rd (void) | |
8934 | { | |
8935 | inst.instruction |= inst.operands[0].reg << 12; | |
8936 | } | |
a737bd4d | 8937 | |
16a1fa25 TP |
8938 | static void |
8939 | do_rn (void) | |
8940 | { | |
8941 | inst.instruction |= inst.operands[0].reg << 16; | |
8942 | } | |
8943 | ||
c19d1205 ZW |
8944 | static void |
8945 | do_rd_rm (void) | |
8946 | { | |
8947 | inst.instruction |= inst.operands[0].reg << 12; | |
8948 | inst.instruction |= inst.operands[1].reg; | |
8949 | } | |
09d92015 | 8950 | |
9eb6c0f1 MGD |
8951 | static void |
8952 | do_rm_rn (void) | |
8953 | { | |
8954 | inst.instruction |= inst.operands[0].reg; | |
8955 | inst.instruction |= inst.operands[1].reg << 16; | |
8956 | } | |
8957 | ||
c19d1205 ZW |
8958 | static void |
8959 | do_rd_rn (void) | |
8960 | { | |
8961 | inst.instruction |= inst.operands[0].reg << 12; | |
8962 | inst.instruction |= inst.operands[1].reg << 16; | |
8963 | } | |
a737bd4d | 8964 | |
c19d1205 ZW |
8965 | static void |
8966 | do_rn_rd (void) | |
8967 | { | |
8968 | inst.instruction |= inst.operands[0].reg << 16; | |
8969 | inst.instruction |= inst.operands[1].reg << 12; | |
8970 | } | |
09d92015 | 8971 | |
4ed7ed8d TP |
8972 | static void |
8973 | do_tt (void) | |
8974 | { | |
8975 | inst.instruction |= inst.operands[0].reg << 8; | |
8976 | inst.instruction |= inst.operands[1].reg << 16; | |
8977 | } | |
8978 | ||
59d09be6 MGD |
8979 | static bfd_boolean |
8980 | check_obsolete (const arm_feature_set *feature, const char *msg) | |
8981 | { | |
8982 | if (ARM_CPU_IS_ANY (cpu_variant)) | |
8983 | { | |
5c3696f8 | 8984 | as_tsktsk ("%s", msg); |
59d09be6 MGD |
8985 | return TRUE; |
8986 | } | |
8987 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature)) | |
8988 | { | |
8989 | as_bad ("%s", msg); | |
8990 | return TRUE; | |
8991 | } | |
8992 | ||
8993 | return FALSE; | |
8994 | } | |
8995 | ||
c19d1205 ZW |
8996 | static void |
8997 | do_rd_rm_rn (void) | |
8998 | { | |
9a64e435 | 8999 | unsigned Rn = inst.operands[2].reg; |
708587a4 | 9000 | /* Enforce restrictions on SWP instruction. */ |
9a64e435 | 9001 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) |
56adecf4 DG |
9002 | { |
9003 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
9004 | _("Rn must not overlap other operands")); | |
9005 | ||
59d09be6 MGD |
9006 | /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7. |
9007 | */ | |
9008 | if (!check_obsolete (&arm_ext_v8, | |
9009 | _("swp{b} use is obsoleted for ARMv8 and later")) | |
9010 | && warn_on_deprecated | |
9011 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6)) | |
5c3696f8 | 9012 | as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7")); |
56adecf4 | 9013 | } |
59d09be6 | 9014 | |
c19d1205 ZW |
9015 | inst.instruction |= inst.operands[0].reg << 12; |
9016 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 9017 | inst.instruction |= Rn << 16; |
c19d1205 | 9018 | } |
09d92015 | 9019 | |
c19d1205 ZW |
9020 | static void |
9021 | do_rd_rn_rm (void) | |
9022 | { | |
9023 | inst.instruction |= inst.operands[0].reg << 12; | |
9024 | inst.instruction |= inst.operands[1].reg << 16; | |
9025 | inst.instruction |= inst.operands[2].reg; | |
9026 | } | |
a737bd4d | 9027 | |
c19d1205 ZW |
9028 | static void |
9029 | do_rm_rd_rn (void) | |
9030 | { | |
5be8be5d | 9031 | constraint ((inst.operands[2].reg == REG_PC), BAD_PC); |
e2b0ab59 AV |
9032 | constraint (((inst.relocs[0].exp.X_op != O_constant |
9033 | && inst.relocs[0].exp.X_op != O_illegal) | |
9034 | || inst.relocs[0].exp.X_add_number != 0), | |
5be8be5d | 9035 | BAD_ADDR_MODE); |
c19d1205 ZW |
9036 | inst.instruction |= inst.operands[0].reg; |
9037 | inst.instruction |= inst.operands[1].reg << 12; | |
9038 | inst.instruction |= inst.operands[2].reg << 16; | |
9039 | } | |
09d92015 | 9040 | |
c19d1205 ZW |
9041 | static void |
9042 | do_imm0 (void) | |
9043 | { | |
9044 | inst.instruction |= inst.operands[0].imm; | |
9045 | } | |
09d92015 | 9046 | |
c19d1205 ZW |
9047 | static void |
9048 | do_rd_cpaddr (void) | |
9049 | { | |
9050 | inst.instruction |= inst.operands[0].reg << 12; | |
9051 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 9052 | } |
a737bd4d | 9053 | |
c19d1205 ZW |
9054 | /* ARM instructions, in alphabetical order by function name (except |
9055 | that wrapper functions appear immediately after the function they | |
9056 | wrap). */ | |
09d92015 | 9057 | |
c19d1205 ZW |
9058 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
9059 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
9060 | |
9061 | static void | |
c19d1205 | 9062 | do_adr (void) |
09d92015 | 9063 | { |
c19d1205 | 9064 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 9065 | |
c19d1205 ZW |
9066 | /* Frag hacking will turn this into a sub instruction if the offset turns |
9067 | out to be negative. */ | |
e2b0ab59 AV |
9068 | inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE; |
9069 | inst.relocs[0].pc_rel = 1; | |
9070 | inst.relocs[0].exp.X_add_number -= 8; | |
52a86f84 | 9071 | |
fc6141f0 | 9072 | if (support_interwork |
e2b0ab59 AV |
9073 | && inst.relocs[0].exp.X_op == O_symbol |
9074 | && inst.relocs[0].exp.X_add_symbol != NULL | |
9075 | && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol) | |
9076 | && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol)) | |
9077 | inst.relocs[0].exp.X_add_number |= 1; | |
c19d1205 | 9078 | } |
b99bd4ef | 9079 | |
c19d1205 ZW |
9080 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
9081 | into a relative address of the form: | |
9082 | add rd, pc, #low(label-.-8)" | |
9083 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 9084 | |
c19d1205 ZW |
9085 | static void |
9086 | do_adrl (void) | |
9087 | { | |
9088 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 9089 | |
c19d1205 ZW |
9090 | /* Frag hacking will turn this into a sub instruction if the offset turns |
9091 | out to be negative. */ | |
e2b0ab59 AV |
9092 | inst.relocs[0].type = BFD_RELOC_ARM_ADRL_IMMEDIATE; |
9093 | inst.relocs[0].pc_rel = 1; | |
c19d1205 | 9094 | inst.size = INSN_SIZE * 2; |
e2b0ab59 | 9095 | inst.relocs[0].exp.X_add_number -= 8; |
52a86f84 | 9096 | |
fc6141f0 | 9097 | if (support_interwork |
e2b0ab59 AV |
9098 | && inst.relocs[0].exp.X_op == O_symbol |
9099 | && inst.relocs[0].exp.X_add_symbol != NULL | |
9100 | && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol) | |
9101 | && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol)) | |
9102 | inst.relocs[0].exp.X_add_number |= 1; | |
b99bd4ef NC |
9103 | } |
9104 | ||
b99bd4ef | 9105 | static void |
c19d1205 | 9106 | do_arit (void) |
b99bd4ef | 9107 | { |
e2b0ab59 AV |
9108 | constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC |
9109 | && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC , | |
a9f02af8 | 9110 | THUMB1_RELOC_ONLY); |
c19d1205 ZW |
9111 | if (!inst.operands[1].present) |
9112 | inst.operands[1].reg = inst.operands[0].reg; | |
9113 | inst.instruction |= inst.operands[0].reg << 12; | |
9114 | inst.instruction |= inst.operands[1].reg << 16; | |
9115 | encode_arm_shifter_operand (2); | |
9116 | } | |
b99bd4ef | 9117 | |
62b3e311 PB |
9118 | static void |
9119 | do_barrier (void) | |
9120 | { | |
9121 | if (inst.operands[0].present) | |
ccb84d65 | 9122 | inst.instruction |= inst.operands[0].imm; |
62b3e311 PB |
9123 | else |
9124 | inst.instruction |= 0xf; | |
9125 | } | |
9126 | ||
c19d1205 ZW |
9127 | static void |
9128 | do_bfc (void) | |
9129 | { | |
9130 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
9131 | constraint (msb > 32, _("bit-field extends past end of register")); | |
9132 | /* The instruction encoding stores the LSB and MSB, | |
9133 | not the LSB and width. */ | |
9134 | inst.instruction |= inst.operands[0].reg << 12; | |
9135 | inst.instruction |= inst.operands[1].imm << 7; | |
9136 | inst.instruction |= (msb - 1) << 16; | |
9137 | } | |
b99bd4ef | 9138 | |
c19d1205 ZW |
9139 | static void |
9140 | do_bfi (void) | |
9141 | { | |
9142 | unsigned int msb; | |
b99bd4ef | 9143 | |
c19d1205 ZW |
9144 | /* #0 in second position is alternative syntax for bfc, which is |
9145 | the same instruction but with REG_PC in the Rm field. */ | |
9146 | if (!inst.operands[1].isreg) | |
9147 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 9148 | |
c19d1205 ZW |
9149 | msb = inst.operands[2].imm + inst.operands[3].imm; |
9150 | constraint (msb > 32, _("bit-field extends past end of register")); | |
9151 | /* The instruction encoding stores the LSB and MSB, | |
9152 | not the LSB and width. */ | |
9153 | inst.instruction |= inst.operands[0].reg << 12; | |
9154 | inst.instruction |= inst.operands[1].reg; | |
9155 | inst.instruction |= inst.operands[2].imm << 7; | |
9156 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
9157 | } |
9158 | ||
b99bd4ef | 9159 | static void |
c19d1205 | 9160 | do_bfx (void) |
b99bd4ef | 9161 | { |
c19d1205 ZW |
9162 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
9163 | _("bit-field extends past end of register")); | |
9164 | inst.instruction |= inst.operands[0].reg << 12; | |
9165 | inst.instruction |= inst.operands[1].reg; | |
9166 | inst.instruction |= inst.operands[2].imm << 7; | |
9167 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
9168 | } | |
09d92015 | 9169 | |
c19d1205 ZW |
9170 | /* ARM V5 breakpoint instruction (argument parse) |
9171 | BKPT <16 bit unsigned immediate> | |
9172 | Instruction is not conditional. | |
9173 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
9174 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 9175 | |
c19d1205 ZW |
9176 | static void |
9177 | do_bkpt (void) | |
9178 | { | |
9179 | /* Top 12 of 16 bits to bits 19:8. */ | |
9180 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 9181 | |
c19d1205 ZW |
9182 | /* Bottom 4 of 16 bits to bits 3:0. */ |
9183 | inst.instruction |= inst.operands[0].imm & 0xf; | |
9184 | } | |
09d92015 | 9185 | |
c19d1205 ZW |
9186 | static void |
9187 | encode_branch (int default_reloc) | |
9188 | { | |
9189 | if (inst.operands[0].hasreloc) | |
9190 | { | |
0855e32b NS |
9191 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32 |
9192 | && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL, | |
9193 | _("the only valid suffixes here are '(plt)' and '(tlscall)'")); | |
e2b0ab59 | 9194 | inst.relocs[0].type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32 |
0855e32b NS |
9195 | ? BFD_RELOC_ARM_PLT32 |
9196 | : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL; | |
c19d1205 | 9197 | } |
b99bd4ef | 9198 | else |
e2b0ab59 AV |
9199 | inst.relocs[0].type = (bfd_reloc_code_real_type) default_reloc; |
9200 | inst.relocs[0].pc_rel = 1; | |
b99bd4ef NC |
9201 | } |
9202 | ||
b99bd4ef | 9203 | static void |
c19d1205 | 9204 | do_branch (void) |
b99bd4ef | 9205 | { |
39b41c9c PB |
9206 | #ifdef OBJ_ELF |
9207 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
9208 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
9209 | else | |
9210 | #endif | |
9211 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
9212 | } | |
9213 | ||
9214 | static void | |
9215 | do_bl (void) | |
9216 | { | |
9217 | #ifdef OBJ_ELF | |
9218 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
9219 | { | |
9220 | if (inst.cond == COND_ALWAYS) | |
9221 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
9222 | else | |
9223 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
9224 | } | |
9225 | else | |
9226 | #endif | |
9227 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
c19d1205 | 9228 | } |
b99bd4ef | 9229 | |
c19d1205 ZW |
9230 | /* ARM V5 branch-link-exchange instruction (argument parse) |
9231 | BLX <target_addr> ie BLX(1) | |
9232 | BLX{<condition>} <Rm> ie BLX(2) | |
9233 | Unfortunately, there are two different opcodes for this mnemonic. | |
9234 | So, the insns[].value is not used, and the code here zaps values | |
9235 | into inst.instruction. | |
9236 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 9237 | |
c19d1205 ZW |
9238 | static void |
9239 | do_blx (void) | |
9240 | { | |
9241 | if (inst.operands[0].isreg) | |
b99bd4ef | 9242 | { |
c19d1205 ZW |
9243 | /* Arg is a register; the opcode provided by insns[] is correct. |
9244 | It is not illegal to do "blx pc", just useless. */ | |
9245 | if (inst.operands[0].reg == REG_PC) | |
9246 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 9247 | |
c19d1205 ZW |
9248 | inst.instruction |= inst.operands[0].reg; |
9249 | } | |
9250 | else | |
b99bd4ef | 9251 | { |
c19d1205 | 9252 | /* Arg is an address; this instruction cannot be executed |
267bf995 RR |
9253 | conditionally, and the opcode must be adjusted. |
9254 | We retain the BFD_RELOC_ARM_PCREL_BLX till the very end | |
9255 | where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */ | |
c19d1205 | 9256 | constraint (inst.cond != COND_ALWAYS, BAD_COND); |
2fc8bdac | 9257 | inst.instruction = 0xfa000000; |
267bf995 | 9258 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); |
b99bd4ef | 9259 | } |
c19d1205 ZW |
9260 | } |
9261 | ||
9262 | static void | |
9263 | do_bx (void) | |
9264 | { | |
845b51d6 PB |
9265 | bfd_boolean want_reloc; |
9266 | ||
c19d1205 ZW |
9267 | if (inst.operands[0].reg == REG_PC) |
9268 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 9269 | |
c19d1205 | 9270 | inst.instruction |= inst.operands[0].reg; |
845b51d6 PB |
9271 | /* Output R_ARM_V4BX relocations if is an EABI object that looks like |
9272 | it is for ARMv4t or earlier. */ | |
9273 | want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5); | |
4d354d8b TP |
9274 | if (!ARM_FEATURE_ZERO (selected_object_arch) |
9275 | && !ARM_CPU_HAS_FEATURE (selected_object_arch, arm_ext_v5)) | |
845b51d6 PB |
9276 | want_reloc = TRUE; |
9277 | ||
5ad34203 | 9278 | #ifdef OBJ_ELF |
845b51d6 | 9279 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
5ad34203 | 9280 | #endif |
584206db | 9281 | want_reloc = FALSE; |
845b51d6 PB |
9282 | |
9283 | if (want_reloc) | |
e2b0ab59 | 9284 | inst.relocs[0].type = BFD_RELOC_ARM_V4BX; |
09d92015 MM |
9285 | } |
9286 | ||
c19d1205 ZW |
9287 | |
9288 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
9289 | |
9290 | static void | |
c19d1205 | 9291 | do_bxj (void) |
a737bd4d | 9292 | { |
c19d1205 ZW |
9293 | if (inst.operands[0].reg == REG_PC) |
9294 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
9295 | ||
9296 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
9297 | } |
9298 | ||
c19d1205 ZW |
9299 | /* Co-processor data operation: |
9300 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
9301 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
9302 | static void | |
9303 | do_cdp (void) | |
9304 | { | |
9305 | inst.instruction |= inst.operands[0].reg << 8; | |
9306 | inst.instruction |= inst.operands[1].imm << 20; | |
9307 | inst.instruction |= inst.operands[2].reg << 12; | |
9308 | inst.instruction |= inst.operands[3].reg << 16; | |
9309 | inst.instruction |= inst.operands[4].reg; | |
9310 | inst.instruction |= inst.operands[5].imm << 5; | |
9311 | } | |
a737bd4d NC |
9312 | |
9313 | static void | |
c19d1205 | 9314 | do_cmp (void) |
a737bd4d | 9315 | { |
c19d1205 ZW |
9316 | inst.instruction |= inst.operands[0].reg << 16; |
9317 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
9318 | } |
9319 | ||
c19d1205 ZW |
9320 | /* Transfer between coprocessor and ARM registers. |
9321 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
9322 | MRC2 | |
9323 | MCR{cond} | |
9324 | MCR2 | |
9325 | ||
9326 | No special properties. */ | |
09d92015 | 9327 | |
dcbd0d71 MGD |
9328 | struct deprecated_coproc_regs_s |
9329 | { | |
9330 | unsigned cp; | |
9331 | int opc1; | |
9332 | unsigned crn; | |
9333 | unsigned crm; | |
9334 | int opc2; | |
9335 | arm_feature_set deprecated; | |
9336 | arm_feature_set obsoleted; | |
9337 | const char *dep_msg; | |
9338 | const char *obs_msg; | |
9339 | }; | |
9340 | ||
9341 | #define DEPR_ACCESS_V8 \ | |
9342 | N_("This coprocessor register access is deprecated in ARMv8") | |
9343 | ||
9344 | /* Table of all deprecated coprocessor registers. */ | |
9345 | static struct deprecated_coproc_regs_s deprecated_coproc_regs[] = | |
9346 | { | |
9347 | {15, 0, 7, 10, 5, /* CP15DMB. */ | |
823d2571 | 9348 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
9349 | DEPR_ACCESS_V8, NULL}, |
9350 | {15, 0, 7, 10, 4, /* CP15DSB. */ | |
823d2571 | 9351 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
9352 | DEPR_ACCESS_V8, NULL}, |
9353 | {15, 0, 7, 5, 4, /* CP15ISB. */ | |
823d2571 | 9354 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
9355 | DEPR_ACCESS_V8, NULL}, |
9356 | {14, 6, 1, 0, 0, /* TEEHBR. */ | |
823d2571 | 9357 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
9358 | DEPR_ACCESS_V8, NULL}, |
9359 | {14, 6, 0, 0, 0, /* TEECR. */ | |
823d2571 | 9360 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
9361 | DEPR_ACCESS_V8, NULL}, |
9362 | }; | |
9363 | ||
9364 | #undef DEPR_ACCESS_V8 | |
9365 | ||
9366 | static const size_t deprecated_coproc_reg_count = | |
9367 | sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]); | |
9368 | ||
09d92015 | 9369 | static void |
c19d1205 | 9370 | do_co_reg (void) |
09d92015 | 9371 | { |
fdfde340 | 9372 | unsigned Rd; |
dcbd0d71 | 9373 | size_t i; |
fdfde340 JM |
9374 | |
9375 | Rd = inst.operands[2].reg; | |
9376 | if (thumb_mode) | |
9377 | { | |
9378 | if (inst.instruction == 0xee000010 | |
9379 | || inst.instruction == 0xfe000010) | |
9380 | /* MCR, MCR2 */ | |
9381 | reject_bad_reg (Rd); | |
5c8ed6a4 | 9382 | else if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
fdfde340 JM |
9383 | /* MRC, MRC2 */ |
9384 | constraint (Rd == REG_SP, BAD_SP); | |
9385 | } | |
9386 | else | |
9387 | { | |
9388 | /* MCR */ | |
9389 | if (inst.instruction == 0xe000010) | |
9390 | constraint (Rd == REG_PC, BAD_PC); | |
9391 | } | |
9392 | ||
dcbd0d71 MGD |
9393 | for (i = 0; i < deprecated_coproc_reg_count; ++i) |
9394 | { | |
9395 | const struct deprecated_coproc_regs_s *r = | |
9396 | deprecated_coproc_regs + i; | |
9397 | ||
9398 | if (inst.operands[0].reg == r->cp | |
9399 | && inst.operands[1].imm == r->opc1 | |
9400 | && inst.operands[3].reg == r->crn | |
9401 | && inst.operands[4].reg == r->crm | |
9402 | && inst.operands[5].imm == r->opc2) | |
9403 | { | |
b10bf8c5 | 9404 | if (! ARM_CPU_IS_ANY (cpu_variant) |
477330fc | 9405 | && warn_on_deprecated |
dcbd0d71 | 9406 | && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated)) |
5c3696f8 | 9407 | as_tsktsk ("%s", r->dep_msg); |
dcbd0d71 MGD |
9408 | } |
9409 | } | |
fdfde340 | 9410 | |
c19d1205 ZW |
9411 | inst.instruction |= inst.operands[0].reg << 8; |
9412 | inst.instruction |= inst.operands[1].imm << 21; | |
fdfde340 | 9413 | inst.instruction |= Rd << 12; |
c19d1205 ZW |
9414 | inst.instruction |= inst.operands[3].reg << 16; |
9415 | inst.instruction |= inst.operands[4].reg; | |
9416 | inst.instruction |= inst.operands[5].imm << 5; | |
9417 | } | |
09d92015 | 9418 | |
c19d1205 ZW |
9419 | /* Transfer between coprocessor register and pair of ARM registers. |
9420 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
9421 | MCRR2 | |
9422 | MRRC{cond} | |
9423 | MRRC2 | |
b99bd4ef | 9424 | |
c19d1205 | 9425 | Two XScale instructions are special cases of these: |
09d92015 | 9426 | |
c19d1205 ZW |
9427 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
9428 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 9429 | |
5f4273c7 | 9430 | Result unpredictable if Rd or Rn is R15. */ |
a737bd4d | 9431 | |
c19d1205 ZW |
9432 | static void |
9433 | do_co_reg2c (void) | |
9434 | { | |
fdfde340 JM |
9435 | unsigned Rd, Rn; |
9436 | ||
9437 | Rd = inst.operands[2].reg; | |
9438 | Rn = inst.operands[3].reg; | |
9439 | ||
9440 | if (thumb_mode) | |
9441 | { | |
9442 | reject_bad_reg (Rd); | |
9443 | reject_bad_reg (Rn); | |
9444 | } | |
9445 | else | |
9446 | { | |
9447 | constraint (Rd == REG_PC, BAD_PC); | |
9448 | constraint (Rn == REG_PC, BAD_PC); | |
9449 | } | |
9450 | ||
873f10f0 TC |
9451 | /* Only check the MRRC{2} variants. */ |
9452 | if ((inst.instruction & 0x0FF00000) == 0x0C500000) | |
9453 | { | |
9454 | /* If Rd == Rn, error that the operation is | |
9455 | unpredictable (example MRRC p3,#1,r1,r1,c4). */ | |
9456 | constraint (Rd == Rn, BAD_OVERLAP); | |
9457 | } | |
9458 | ||
c19d1205 ZW |
9459 | inst.instruction |= inst.operands[0].reg << 8; |
9460 | inst.instruction |= inst.operands[1].imm << 4; | |
fdfde340 JM |
9461 | inst.instruction |= Rd << 12; |
9462 | inst.instruction |= Rn << 16; | |
c19d1205 | 9463 | inst.instruction |= inst.operands[4].reg; |
b99bd4ef NC |
9464 | } |
9465 | ||
c19d1205 ZW |
9466 | static void |
9467 | do_cpsi (void) | |
9468 | { | |
9469 | inst.instruction |= inst.operands[0].imm << 6; | |
a028a6f5 PB |
9470 | if (inst.operands[1].present) |
9471 | { | |
9472 | inst.instruction |= CPSI_MMOD; | |
9473 | inst.instruction |= inst.operands[1].imm; | |
9474 | } | |
c19d1205 | 9475 | } |
b99bd4ef | 9476 | |
62b3e311 PB |
9477 | static void |
9478 | do_dbg (void) | |
9479 | { | |
9480 | inst.instruction |= inst.operands[0].imm; | |
9481 | } | |
9482 | ||
eea54501 MGD |
9483 | static void |
9484 | do_div (void) | |
9485 | { | |
9486 | unsigned Rd, Rn, Rm; | |
9487 | ||
9488 | Rd = inst.operands[0].reg; | |
9489 | Rn = (inst.operands[1].present | |
9490 | ? inst.operands[1].reg : Rd); | |
9491 | Rm = inst.operands[2].reg; | |
9492 | ||
9493 | constraint ((Rd == REG_PC), BAD_PC); | |
9494 | constraint ((Rn == REG_PC), BAD_PC); | |
9495 | constraint ((Rm == REG_PC), BAD_PC); | |
9496 | ||
9497 | inst.instruction |= Rd << 16; | |
9498 | inst.instruction |= Rn << 0; | |
9499 | inst.instruction |= Rm << 8; | |
9500 | } | |
9501 | ||
b99bd4ef | 9502 | static void |
c19d1205 | 9503 | do_it (void) |
b99bd4ef | 9504 | { |
c19d1205 | 9505 | /* There is no IT instruction in ARM mode. We |
e07e6e58 NC |
9506 | process it to do the validation as if in |
9507 | thumb mode, just in case the code gets | |
9508 | assembled for thumb using the unified syntax. */ | |
9509 | ||
c19d1205 | 9510 | inst.size = 0; |
e07e6e58 NC |
9511 | if (unified_syntax) |
9512 | { | |
5ee91343 AV |
9513 | set_pred_insn_type (IT_INSN); |
9514 | now_pred.mask = (inst.instruction & 0xf) | 0x10; | |
9515 | now_pred.cc = inst.operands[0].imm; | |
e07e6e58 | 9516 | } |
09d92015 | 9517 | } |
b99bd4ef | 9518 | |
6530b175 NC |
9519 | /* If there is only one register in the register list, |
9520 | then return its register number. Otherwise return -1. */ | |
9521 | static int | |
9522 | only_one_reg_in_list (int range) | |
9523 | { | |
9524 | int i = ffs (range) - 1; | |
9525 | return (i > 15 || range != (1 << i)) ? -1 : i; | |
9526 | } | |
9527 | ||
09d92015 | 9528 | static void |
6530b175 | 9529 | encode_ldmstm(int from_push_pop_mnem) |
ea6ef066 | 9530 | { |
c19d1205 ZW |
9531 | int base_reg = inst.operands[0].reg; |
9532 | int range = inst.operands[1].imm; | |
6530b175 | 9533 | int one_reg; |
ea6ef066 | 9534 | |
c19d1205 ZW |
9535 | inst.instruction |= base_reg << 16; |
9536 | inst.instruction |= range; | |
ea6ef066 | 9537 | |
c19d1205 ZW |
9538 | if (inst.operands[1].writeback) |
9539 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 9540 | |
c19d1205 | 9541 | if (inst.operands[0].writeback) |
ea6ef066 | 9542 | { |
c19d1205 ZW |
9543 | inst.instruction |= WRITE_BACK; |
9544 | /* Check for unpredictable uses of writeback. */ | |
9545 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 9546 | { |
c19d1205 ZW |
9547 | /* Not allowed in LDM type 2. */ |
9548 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
9549 | && ((range & (1 << REG_PC)) == 0)) | |
9550 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
9551 | /* Only allowed if base reg not in list for other types. */ | |
9552 | else if (range & (1 << base_reg)) | |
9553 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
9554 | } | |
9555 | else /* STM. */ | |
9556 | { | |
9557 | /* Not allowed for type 2. */ | |
9558 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
9559 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
9560 | /* Only allowed if base reg not in list, or first in list. */ | |
9561 | else if ((range & (1 << base_reg)) | |
9562 | && (range & ((1 << base_reg) - 1))) | |
9563 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 9564 | } |
ea6ef066 | 9565 | } |
6530b175 NC |
9566 | |
9567 | /* If PUSH/POP has only one register, then use the A2 encoding. */ | |
9568 | one_reg = only_one_reg_in_list (range); | |
9569 | if (from_push_pop_mnem && one_reg >= 0) | |
9570 | { | |
9571 | int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH; | |
9572 | ||
4f588891 NC |
9573 | if (is_push && one_reg == 13 /* SP */) |
9574 | /* PR 22483: The A2 encoding cannot be used when | |
9575 | pushing the stack pointer as this is UNPREDICTABLE. */ | |
9576 | return; | |
9577 | ||
6530b175 NC |
9578 | inst.instruction &= A_COND_MASK; |
9579 | inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP; | |
9580 | inst.instruction |= one_reg << 12; | |
9581 | } | |
9582 | } | |
9583 | ||
9584 | static void | |
9585 | do_ldmstm (void) | |
9586 | { | |
9587 | encode_ldmstm (/*from_push_pop_mnem=*/FALSE); | |
a737bd4d NC |
9588 | } |
9589 | ||
c19d1205 ZW |
9590 | /* ARMv5TE load-consecutive (argument parse) |
9591 | Mode is like LDRH. | |
9592 | ||
9593 | LDRccD R, mode | |
9594 | STRccD R, mode. */ | |
9595 | ||
a737bd4d | 9596 | static void |
c19d1205 | 9597 | do_ldrd (void) |
a737bd4d | 9598 | { |
c19d1205 | 9599 | constraint (inst.operands[0].reg % 2 != 0, |
c56791bb | 9600 | _("first transfer register must be even")); |
c19d1205 ZW |
9601 | constraint (inst.operands[1].present |
9602 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
c56791bb | 9603 | _("can only transfer two consecutive registers")); |
c19d1205 ZW |
9604 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); |
9605 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 9606 | |
c19d1205 ZW |
9607 | if (!inst.operands[1].present) |
9608 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
5f4273c7 | 9609 | |
c56791bb RE |
9610 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
9611 | register and the first register written; we have to diagnose | |
9612 | overlap between the base and the second register written here. */ | |
ea6ef066 | 9613 | |
c56791bb RE |
9614 | if (inst.operands[2].reg == inst.operands[1].reg |
9615 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
9616 | as_warn (_("base register written back, and overlaps " | |
9617 | "second transfer register")); | |
b05fe5cf | 9618 | |
c56791bb RE |
9619 | if (!(inst.instruction & V4_STR_BIT)) |
9620 | { | |
c19d1205 | 9621 | /* For an index-register load, the index register must not overlap the |
c56791bb RE |
9622 | destination (even if not write-back). */ |
9623 | if (inst.operands[2].immisreg | |
9624 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg | |
9625 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
9626 | as_warn (_("index register overlaps transfer register")); | |
b05fe5cf | 9627 | } |
c19d1205 ZW |
9628 | inst.instruction |= inst.operands[0].reg << 12; |
9629 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
9630 | } |
9631 | ||
9632 | static void | |
c19d1205 | 9633 | do_ldrex (void) |
b05fe5cf | 9634 | { |
c19d1205 ZW |
9635 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
9636 | || inst.operands[1].postind || inst.operands[1].writeback | |
9637 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
01cfc07f NC |
9638 | || inst.operands[1].negative |
9639 | /* This can arise if the programmer has written | |
9640 | strex rN, rM, foo | |
9641 | or if they have mistakenly used a register name as the last | |
9642 | operand, eg: | |
9643 | strex rN, rM, rX | |
9644 | It is very difficult to distinguish between these two cases | |
9645 | because "rX" might actually be a label. ie the register | |
9646 | name has been occluded by a symbol of the same name. So we | |
9647 | just generate a general 'bad addressing mode' type error | |
9648 | message and leave it up to the programmer to discover the | |
9649 | true cause and fix their mistake. */ | |
9650 | || (inst.operands[1].reg == REG_PC), | |
9651 | BAD_ADDR_MODE); | |
b05fe5cf | 9652 | |
e2b0ab59 AV |
9653 | constraint (inst.relocs[0].exp.X_op != O_constant |
9654 | || inst.relocs[0].exp.X_add_number != 0, | |
c19d1205 | 9655 | _("offset must be zero in ARM encoding")); |
b05fe5cf | 9656 | |
5be8be5d DG |
9657 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
9658 | ||
c19d1205 ZW |
9659 | inst.instruction |= inst.operands[0].reg << 12; |
9660 | inst.instruction |= inst.operands[1].reg << 16; | |
e2b0ab59 | 9661 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
b05fe5cf ZW |
9662 | } |
9663 | ||
9664 | static void | |
c19d1205 | 9665 | do_ldrexd (void) |
b05fe5cf | 9666 | { |
c19d1205 ZW |
9667 | constraint (inst.operands[0].reg % 2 != 0, |
9668 | _("even register required")); | |
9669 | constraint (inst.operands[1].present | |
9670 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
9671 | _("can only load two consecutive registers")); | |
9672 | /* If op 1 were present and equal to PC, this function wouldn't | |
9673 | have been called in the first place. */ | |
9674 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 9675 | |
c19d1205 ZW |
9676 | inst.instruction |= inst.operands[0].reg << 12; |
9677 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
9678 | } |
9679 | ||
1be5fd2e NC |
9680 | /* In both ARM and thumb state 'ldr pc, #imm' with an immediate |
9681 | which is not a multiple of four is UNPREDICTABLE. */ | |
9682 | static void | |
9683 | check_ldr_r15_aligned (void) | |
9684 | { | |
9685 | constraint (!(inst.operands[1].immisreg) | |
9686 | && (inst.operands[0].reg == REG_PC | |
9687 | && inst.operands[1].reg == REG_PC | |
e2b0ab59 | 9688 | && (inst.relocs[0].exp.X_add_number & 0x3)), |
de194d85 | 9689 | _("ldr to register 15 must be 4-byte aligned")); |
1be5fd2e NC |
9690 | } |
9691 | ||
b05fe5cf | 9692 | static void |
c19d1205 | 9693 | do_ldst (void) |
b05fe5cf | 9694 | { |
c19d1205 ZW |
9695 | inst.instruction |= inst.operands[0].reg << 12; |
9696 | if (!inst.operands[1].isreg) | |
8335d6aa | 9697 | if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE)) |
b05fe5cf | 9698 | return; |
c19d1205 | 9699 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
1be5fd2e | 9700 | check_ldr_r15_aligned (); |
b05fe5cf ZW |
9701 | } |
9702 | ||
9703 | static void | |
c19d1205 | 9704 | do_ldstt (void) |
b05fe5cf | 9705 | { |
c19d1205 ZW |
9706 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
9707 | reject [Rn,...]. */ | |
9708 | if (inst.operands[1].preind) | |
b05fe5cf | 9709 | { |
e2b0ab59 AV |
9710 | constraint (inst.relocs[0].exp.X_op != O_constant |
9711 | || inst.relocs[0].exp.X_add_number != 0, | |
c19d1205 | 9712 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 9713 | |
c19d1205 ZW |
9714 | inst.operands[1].preind = 0; |
9715 | inst.operands[1].postind = 1; | |
9716 | inst.operands[1].writeback = 1; | |
b05fe5cf | 9717 | } |
c19d1205 ZW |
9718 | inst.instruction |= inst.operands[0].reg << 12; |
9719 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
9720 | } | |
b05fe5cf | 9721 | |
c19d1205 | 9722 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 9723 | |
c19d1205 ZW |
9724 | static void |
9725 | do_ldstv4 (void) | |
9726 | { | |
ff4a8d2b | 9727 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 ZW |
9728 | inst.instruction |= inst.operands[0].reg << 12; |
9729 | if (!inst.operands[1].isreg) | |
8335d6aa | 9730 | if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE)) |
b05fe5cf | 9731 | return; |
c19d1205 | 9732 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
9733 | } |
9734 | ||
9735 | static void | |
c19d1205 | 9736 | do_ldsttv4 (void) |
b05fe5cf | 9737 | { |
c19d1205 ZW |
9738 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
9739 | reject [Rn,...]. */ | |
9740 | if (inst.operands[1].preind) | |
b05fe5cf | 9741 | { |
e2b0ab59 AV |
9742 | constraint (inst.relocs[0].exp.X_op != O_constant |
9743 | || inst.relocs[0].exp.X_add_number != 0, | |
c19d1205 | 9744 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 9745 | |
c19d1205 ZW |
9746 | inst.operands[1].preind = 0; |
9747 | inst.operands[1].postind = 1; | |
9748 | inst.operands[1].writeback = 1; | |
b05fe5cf | 9749 | } |
c19d1205 ZW |
9750 | inst.instruction |= inst.operands[0].reg << 12; |
9751 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
9752 | } | |
b05fe5cf | 9753 | |
c19d1205 ZW |
9754 | /* Co-processor register load/store. |
9755 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
9756 | static void | |
9757 | do_lstc (void) | |
9758 | { | |
9759 | inst.instruction |= inst.operands[0].reg << 8; | |
9760 | inst.instruction |= inst.operands[1].reg << 12; | |
9761 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
9762 | } |
9763 | ||
b05fe5cf | 9764 | static void |
c19d1205 | 9765 | do_mlas (void) |
b05fe5cf | 9766 | { |
8fb9d7b9 | 9767 | /* This restriction does not apply to mls (nor to mla in v6 or later). */ |
c19d1205 | 9768 | if (inst.operands[0].reg == inst.operands[1].reg |
8fb9d7b9 | 9769 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) |
c19d1205 | 9770 | && !(inst.instruction & 0x00400000)) |
8fb9d7b9 | 9771 | as_tsktsk (_("Rd and Rm should be different in mla")); |
b05fe5cf | 9772 | |
c19d1205 ZW |
9773 | inst.instruction |= inst.operands[0].reg << 16; |
9774 | inst.instruction |= inst.operands[1].reg; | |
9775 | inst.instruction |= inst.operands[2].reg << 8; | |
9776 | inst.instruction |= inst.operands[3].reg << 12; | |
c19d1205 | 9777 | } |
b05fe5cf | 9778 | |
c19d1205 ZW |
9779 | static void |
9780 | do_mov (void) | |
9781 | { | |
e2b0ab59 AV |
9782 | constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC |
9783 | && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC , | |
a9f02af8 | 9784 | THUMB1_RELOC_ONLY); |
c19d1205 ZW |
9785 | inst.instruction |= inst.operands[0].reg << 12; |
9786 | encode_arm_shifter_operand (1); | |
9787 | } | |
b05fe5cf | 9788 | |
c19d1205 ZW |
9789 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
9790 | static void | |
9791 | do_mov16 (void) | |
9792 | { | |
b6895b4f PB |
9793 | bfd_vma imm; |
9794 | bfd_boolean top; | |
9795 | ||
9796 | top = (inst.instruction & 0x00400000) != 0; | |
e2b0ab59 | 9797 | constraint (top && inst.relocs[0].type == BFD_RELOC_ARM_MOVW, |
33eaf5de | 9798 | _(":lower16: not allowed in this instruction")); |
e2b0ab59 | 9799 | constraint (!top && inst.relocs[0].type == BFD_RELOC_ARM_MOVT, |
33eaf5de | 9800 | _(":upper16: not allowed in this instruction")); |
c19d1205 | 9801 | inst.instruction |= inst.operands[0].reg << 12; |
e2b0ab59 | 9802 | if (inst.relocs[0].type == BFD_RELOC_UNUSED) |
b6895b4f | 9803 | { |
e2b0ab59 | 9804 | imm = inst.relocs[0].exp.X_add_number; |
b6895b4f PB |
9805 | /* The value is in two pieces: 0:11, 16:19. */ |
9806 | inst.instruction |= (imm & 0x00000fff); | |
9807 | inst.instruction |= (imm & 0x0000f000) << 4; | |
9808 | } | |
b05fe5cf | 9809 | } |
b99bd4ef | 9810 | |
037e8744 JB |
9811 | static int |
9812 | do_vfp_nsyn_mrs (void) | |
9813 | { | |
9814 | if (inst.operands[0].isvec) | |
9815 | { | |
9816 | if (inst.operands[1].reg != 1) | |
477330fc | 9817 | first_error (_("operand 1 must be FPSCR")); |
037e8744 JB |
9818 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); |
9819 | memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); | |
9820 | do_vfp_nsyn_opcode ("fmstat"); | |
9821 | } | |
9822 | else if (inst.operands[1].isvec) | |
9823 | do_vfp_nsyn_opcode ("fmrx"); | |
9824 | else | |
9825 | return FAIL; | |
5f4273c7 | 9826 | |
037e8744 JB |
9827 | return SUCCESS; |
9828 | } | |
9829 | ||
9830 | static int | |
9831 | do_vfp_nsyn_msr (void) | |
9832 | { | |
9833 | if (inst.operands[0].isvec) | |
9834 | do_vfp_nsyn_opcode ("fmxr"); | |
9835 | else | |
9836 | return FAIL; | |
9837 | ||
9838 | return SUCCESS; | |
9839 | } | |
9840 | ||
f7c21dc7 NC |
9841 | static void |
9842 | do_vmrs (void) | |
9843 | { | |
9844 | unsigned Rt = inst.operands[0].reg; | |
fa94de6b | 9845 | |
16d02dc9 | 9846 | if (thumb_mode && Rt == REG_SP) |
f7c21dc7 NC |
9847 | { |
9848 | inst.error = BAD_SP; | |
9849 | return; | |
9850 | } | |
9851 | ||
ba6cd17f SD |
9852 | switch (inst.operands[1].reg) |
9853 | { | |
9854 | /* MVFR2 is only valid for Armv8-A. */ | |
9855 | case 5: | |
9856 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
9857 | _(BAD_FPU)); | |
9858 | break; | |
9859 | ||
9860 | /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */ | |
9861 | case 1: /* fpscr. */ | |
9862 | constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
9863 | || ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)), | |
9864 | _(BAD_FPU)); | |
9865 | break; | |
9866 | ||
9867 | case 14: /* fpcxt_ns. */ | |
9868 | case 15: /* fpcxt_s. */ | |
9869 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main), | |
9870 | _("selected processor does not support instruction")); | |
9871 | break; | |
9872 | ||
9873 | case 2: /* fpscr_nzcvqc. */ | |
9874 | case 12: /* vpr. */ | |
9875 | case 13: /* p0. */ | |
9876 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main) | |
9877 | || (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
9878 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)), | |
9879 | _("selected processor does not support instruction")); | |
9880 | if (inst.operands[0].reg != 2 | |
9881 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
9882 | as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE")); | |
9883 | break; | |
9884 | ||
9885 | default: | |
9886 | break; | |
9887 | } | |
40c7d507 | 9888 | |
f7c21dc7 | 9889 | /* APSR_ sets isvec. All other refs to PC are illegal. */ |
16d02dc9 | 9890 | if (!inst.operands[0].isvec && Rt == REG_PC) |
f7c21dc7 NC |
9891 | { |
9892 | inst.error = BAD_PC; | |
9893 | return; | |
9894 | } | |
9895 | ||
16d02dc9 JB |
9896 | /* If we get through parsing the register name, we just insert the number |
9897 | generated into the instruction without further validation. */ | |
9898 | inst.instruction |= (inst.operands[1].reg << 16); | |
f7c21dc7 NC |
9899 | inst.instruction |= (Rt << 12); |
9900 | } | |
9901 | ||
9902 | static void | |
9903 | do_vmsr (void) | |
9904 | { | |
9905 | unsigned Rt = inst.operands[1].reg; | |
fa94de6b | 9906 | |
f7c21dc7 NC |
9907 | if (thumb_mode) |
9908 | reject_bad_reg (Rt); | |
9909 | else if (Rt == REG_PC) | |
9910 | { | |
9911 | inst.error = BAD_PC; | |
9912 | return; | |
9913 | } | |
9914 | ||
ba6cd17f SD |
9915 | switch (inst.operands[0].reg) |
9916 | { | |
9917 | /* MVFR2 is only valid for Armv8-A. */ | |
9918 | case 5: | |
9919 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
9920 | _(BAD_FPU)); | |
9921 | break; | |
9922 | ||
9923 | /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */ | |
9924 | case 1: /* fpcr. */ | |
9925 | constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
9926 | || ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)), | |
9927 | _(BAD_FPU)); | |
9928 | break; | |
9929 | ||
9930 | case 14: /* fpcxt_ns. */ | |
9931 | case 15: /* fpcxt_s. */ | |
9932 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main), | |
9933 | _("selected processor does not support instruction")); | |
9934 | break; | |
9935 | ||
9936 | case 2: /* fpscr_nzcvqc. */ | |
9937 | case 12: /* vpr. */ | |
9938 | case 13: /* p0. */ | |
9939 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main) | |
9940 | || (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
9941 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)), | |
9942 | _("selected processor does not support instruction")); | |
9943 | if (inst.operands[0].reg != 2 | |
9944 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
9945 | as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE")); | |
9946 | break; | |
9947 | ||
9948 | default: | |
9949 | break; | |
9950 | } | |
40c7d507 | 9951 | |
16d02dc9 JB |
9952 | /* If we get through parsing the register name, we just insert the number |
9953 | generated into the instruction without further validation. */ | |
9954 | inst.instruction |= (inst.operands[0].reg << 16); | |
f7c21dc7 NC |
9955 | inst.instruction |= (Rt << 12); |
9956 | } | |
9957 | ||
b99bd4ef | 9958 | static void |
c19d1205 | 9959 | do_mrs (void) |
b99bd4ef | 9960 | { |
90ec0d68 MGD |
9961 | unsigned br; |
9962 | ||
037e8744 JB |
9963 | if (do_vfp_nsyn_mrs () == SUCCESS) |
9964 | return; | |
9965 | ||
ff4a8d2b | 9966 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 | 9967 | inst.instruction |= inst.operands[0].reg << 12; |
90ec0d68 MGD |
9968 | |
9969 | if (inst.operands[1].isreg) | |
9970 | { | |
9971 | br = inst.operands[1].reg; | |
806ab1c0 | 9972 | if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf0000)) |
90ec0d68 MGD |
9973 | as_bad (_("bad register for mrs")); |
9974 | } | |
9975 | else | |
9976 | { | |
9977 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ | |
9978 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
9979 | != (PSR_c|PSR_f), | |
d2cd1205 | 9980 | _("'APSR', 'CPSR' or 'SPSR' expected")); |
90ec0d68 MGD |
9981 | br = (15<<16) | (inst.operands[1].imm & SPSR_BIT); |
9982 | } | |
9983 | ||
9984 | inst.instruction |= br; | |
c19d1205 | 9985 | } |
b99bd4ef | 9986 | |
c19d1205 ZW |
9987 | /* Two possible forms: |
9988 | "{C|S}PSR_<field>, Rm", | |
9989 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 9990 | |
c19d1205 ZW |
9991 | static void |
9992 | do_msr (void) | |
9993 | { | |
037e8744 JB |
9994 | if (do_vfp_nsyn_msr () == SUCCESS) |
9995 | return; | |
9996 | ||
c19d1205 ZW |
9997 | inst.instruction |= inst.operands[0].imm; |
9998 | if (inst.operands[1].isreg) | |
9999 | inst.instruction |= inst.operands[1].reg; | |
10000 | else | |
b99bd4ef | 10001 | { |
c19d1205 | 10002 | inst.instruction |= INST_IMMEDIATE; |
e2b0ab59 AV |
10003 | inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE; |
10004 | inst.relocs[0].pc_rel = 0; | |
b99bd4ef | 10005 | } |
b99bd4ef NC |
10006 | } |
10007 | ||
c19d1205 ZW |
10008 | static void |
10009 | do_mul (void) | |
a737bd4d | 10010 | { |
ff4a8d2b NC |
10011 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
10012 | ||
c19d1205 ZW |
10013 | if (!inst.operands[2].present) |
10014 | inst.operands[2].reg = inst.operands[0].reg; | |
10015 | inst.instruction |= inst.operands[0].reg << 16; | |
10016 | inst.instruction |= inst.operands[1].reg; | |
10017 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 10018 | |
8fb9d7b9 MS |
10019 | if (inst.operands[0].reg == inst.operands[1].reg |
10020 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
10021 | as_tsktsk (_("Rd and Rm should be different in mul")); | |
a737bd4d NC |
10022 | } |
10023 | ||
c19d1205 ZW |
10024 | /* Long Multiply Parser |
10025 | UMULL RdLo, RdHi, Rm, Rs | |
10026 | SMULL RdLo, RdHi, Rm, Rs | |
10027 | UMLAL RdLo, RdHi, Rm, Rs | |
10028 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
10029 | |
10030 | static void | |
c19d1205 | 10031 | do_mull (void) |
b99bd4ef | 10032 | { |
c19d1205 ZW |
10033 | inst.instruction |= inst.operands[0].reg << 12; |
10034 | inst.instruction |= inst.operands[1].reg << 16; | |
10035 | inst.instruction |= inst.operands[2].reg; | |
10036 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 10037 | |
682b27ad PB |
10038 | /* rdhi and rdlo must be different. */ |
10039 | if (inst.operands[0].reg == inst.operands[1].reg) | |
10040 | as_tsktsk (_("rdhi and rdlo must be different")); | |
10041 | ||
10042 | /* rdhi, rdlo and rm must all be different before armv6. */ | |
10043 | if ((inst.operands[0].reg == inst.operands[2].reg | |
c19d1205 | 10044 | || inst.operands[1].reg == inst.operands[2].reg) |
682b27ad | 10045 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) |
c19d1205 ZW |
10046 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); |
10047 | } | |
b99bd4ef | 10048 | |
c19d1205 ZW |
10049 | static void |
10050 | do_nop (void) | |
10051 | { | |
e7495e45 NS |
10052 | if (inst.operands[0].present |
10053 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k)) | |
c19d1205 ZW |
10054 | { |
10055 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
10056 | inst.instruction &= 0xf0000000; | |
e7495e45 NS |
10057 | inst.instruction |= 0x0320f000; |
10058 | if (inst.operands[0].present) | |
10059 | inst.instruction |= inst.operands[0].imm; | |
c19d1205 | 10060 | } |
b99bd4ef NC |
10061 | } |
10062 | ||
c19d1205 ZW |
10063 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
10064 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
10065 | Condition defaults to COND_ALWAYS. | |
10066 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
10067 | |
10068 | static void | |
c19d1205 | 10069 | do_pkhbt (void) |
b99bd4ef | 10070 | { |
c19d1205 ZW |
10071 | inst.instruction |= inst.operands[0].reg << 12; |
10072 | inst.instruction |= inst.operands[1].reg << 16; | |
10073 | inst.instruction |= inst.operands[2].reg; | |
10074 | if (inst.operands[3].present) | |
10075 | encode_arm_shift (3); | |
10076 | } | |
b99bd4ef | 10077 | |
c19d1205 | 10078 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 10079 | |
c19d1205 ZW |
10080 | static void |
10081 | do_pkhtb (void) | |
10082 | { | |
10083 | if (!inst.operands[3].present) | |
b99bd4ef | 10084 | { |
c19d1205 ZW |
10085 | /* If the shift specifier is omitted, turn the instruction |
10086 | into pkhbt rd, rm, rn. */ | |
10087 | inst.instruction &= 0xfff00010; | |
10088 | inst.instruction |= inst.operands[0].reg << 12; | |
10089 | inst.instruction |= inst.operands[1].reg; | |
10090 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
10091 | } |
10092 | else | |
10093 | { | |
c19d1205 ZW |
10094 | inst.instruction |= inst.operands[0].reg << 12; |
10095 | inst.instruction |= inst.operands[1].reg << 16; | |
10096 | inst.instruction |= inst.operands[2].reg; | |
10097 | encode_arm_shift (3); | |
b99bd4ef NC |
10098 | } |
10099 | } | |
10100 | ||
c19d1205 | 10101 | /* ARMv5TE: Preload-Cache |
60e5ef9f | 10102 | MP Extensions: Preload for write |
c19d1205 | 10103 | |
60e5ef9f | 10104 | PLD(W) <addr_mode> |
c19d1205 ZW |
10105 | |
10106 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
10107 | |
10108 | static void | |
c19d1205 | 10109 | do_pld (void) |
b99bd4ef | 10110 | { |
c19d1205 ZW |
10111 | constraint (!inst.operands[0].isreg, |
10112 | _("'[' expected after PLD mnemonic")); | |
10113 | constraint (inst.operands[0].postind, | |
10114 | _("post-indexed expression used in preload instruction")); | |
10115 | constraint (inst.operands[0].writeback, | |
10116 | _("writeback used in preload instruction")); | |
10117 | constraint (!inst.operands[0].preind, | |
10118 | _("unindexed addressing used in preload instruction")); | |
c19d1205 ZW |
10119 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
10120 | } | |
b99bd4ef | 10121 | |
62b3e311 PB |
10122 | /* ARMv7: PLI <addr_mode> */ |
10123 | static void | |
10124 | do_pli (void) | |
10125 | { | |
10126 | constraint (!inst.operands[0].isreg, | |
10127 | _("'[' expected after PLI mnemonic")); | |
10128 | constraint (inst.operands[0].postind, | |
10129 | _("post-indexed expression used in preload instruction")); | |
10130 | constraint (inst.operands[0].writeback, | |
10131 | _("writeback used in preload instruction")); | |
10132 | constraint (!inst.operands[0].preind, | |
10133 | _("unindexed addressing used in preload instruction")); | |
10134 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
10135 | inst.instruction &= ~PRE_INDEX; | |
10136 | } | |
10137 | ||
c19d1205 ZW |
10138 | static void |
10139 | do_push_pop (void) | |
10140 | { | |
5e0d7f77 MP |
10141 | constraint (inst.operands[0].writeback, |
10142 | _("push/pop do not support {reglist}^")); | |
c19d1205 ZW |
10143 | inst.operands[1] = inst.operands[0]; |
10144 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
10145 | inst.operands[0].isreg = 1; | |
10146 | inst.operands[0].writeback = 1; | |
10147 | inst.operands[0].reg = REG_SP; | |
6530b175 | 10148 | encode_ldmstm (/*from_push_pop_mnem=*/TRUE); |
c19d1205 | 10149 | } |
b99bd4ef | 10150 | |
c19d1205 ZW |
10151 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
10152 | word at the specified address and the following word | |
10153 | respectively. | |
10154 | Unconditionally executed. | |
10155 | Error if Rn is R15. */ | |
b99bd4ef | 10156 | |
c19d1205 ZW |
10157 | static void |
10158 | do_rfe (void) | |
10159 | { | |
10160 | inst.instruction |= inst.operands[0].reg << 16; | |
10161 | if (inst.operands[0].writeback) | |
10162 | inst.instruction |= WRITE_BACK; | |
10163 | } | |
b99bd4ef | 10164 | |
c19d1205 | 10165 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 10166 | |
c19d1205 ZW |
10167 | static void |
10168 | do_ssat (void) | |
10169 | { | |
10170 | inst.instruction |= inst.operands[0].reg << 12; | |
10171 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
10172 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 10173 | |
c19d1205 ZW |
10174 | if (inst.operands[3].present) |
10175 | encode_arm_shift (3); | |
b99bd4ef NC |
10176 | } |
10177 | ||
c19d1205 | 10178 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
10179 | |
10180 | static void | |
c19d1205 | 10181 | do_usat (void) |
b99bd4ef | 10182 | { |
c19d1205 ZW |
10183 | inst.instruction |= inst.operands[0].reg << 12; |
10184 | inst.instruction |= inst.operands[1].imm << 16; | |
10185 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 10186 | |
c19d1205 ZW |
10187 | if (inst.operands[3].present) |
10188 | encode_arm_shift (3); | |
b99bd4ef NC |
10189 | } |
10190 | ||
c19d1205 | 10191 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
10192 | |
10193 | static void | |
c19d1205 | 10194 | do_ssat16 (void) |
09d92015 | 10195 | { |
c19d1205 ZW |
10196 | inst.instruction |= inst.operands[0].reg << 12; |
10197 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
10198 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
10199 | } |
10200 | ||
c19d1205 ZW |
10201 | static void |
10202 | do_usat16 (void) | |
a737bd4d | 10203 | { |
c19d1205 ZW |
10204 | inst.instruction |= inst.operands[0].reg << 12; |
10205 | inst.instruction |= inst.operands[1].imm << 16; | |
10206 | inst.instruction |= inst.operands[2].reg; | |
10207 | } | |
a737bd4d | 10208 | |
c19d1205 ZW |
10209 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
10210 | preserving the other bits. | |
a737bd4d | 10211 | |
c19d1205 ZW |
10212 | setend <endian_specifier>, where <endian_specifier> is either |
10213 | BE or LE. */ | |
a737bd4d | 10214 | |
c19d1205 ZW |
10215 | static void |
10216 | do_setend (void) | |
10217 | { | |
12e37cbc MGD |
10218 | if (warn_on_deprecated |
10219 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
5c3696f8 | 10220 | as_tsktsk (_("setend use is deprecated for ARMv8")); |
12e37cbc | 10221 | |
c19d1205 ZW |
10222 | if (inst.operands[0].imm) |
10223 | inst.instruction |= 0x200; | |
a737bd4d NC |
10224 | } |
10225 | ||
10226 | static void | |
c19d1205 | 10227 | do_shift (void) |
a737bd4d | 10228 | { |
c19d1205 ZW |
10229 | unsigned int Rm = (inst.operands[1].present |
10230 | ? inst.operands[1].reg | |
10231 | : inst.operands[0].reg); | |
a737bd4d | 10232 | |
c19d1205 ZW |
10233 | inst.instruction |= inst.operands[0].reg << 12; |
10234 | inst.instruction |= Rm; | |
10235 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 10236 | { |
c19d1205 ZW |
10237 | inst.instruction |= inst.operands[2].reg << 8; |
10238 | inst.instruction |= SHIFT_BY_REG; | |
94342ec3 NC |
10239 | /* PR 12854: Error on extraneous shifts. */ |
10240 | constraint (inst.operands[2].shifted, | |
10241 | _("extraneous shift as part of operand to shift insn")); | |
a737bd4d NC |
10242 | } |
10243 | else | |
e2b0ab59 | 10244 | inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
10245 | } |
10246 | ||
09d92015 | 10247 | static void |
3eb17e6b | 10248 | do_smc (void) |
09d92015 | 10249 | { |
ba85f98c BW |
10250 | unsigned int value = inst.relocs[0].exp.X_add_number; |
10251 | constraint (value > 0xf, _("immediate too large (bigger than 0xF)")); | |
10252 | ||
e2b0ab59 AV |
10253 | inst.relocs[0].type = BFD_RELOC_ARM_SMC; |
10254 | inst.relocs[0].pc_rel = 0; | |
09d92015 MM |
10255 | } |
10256 | ||
90ec0d68 MGD |
10257 | static void |
10258 | do_hvc (void) | |
10259 | { | |
e2b0ab59 AV |
10260 | inst.relocs[0].type = BFD_RELOC_ARM_HVC; |
10261 | inst.relocs[0].pc_rel = 0; | |
90ec0d68 MGD |
10262 | } |
10263 | ||
09d92015 | 10264 | static void |
c19d1205 | 10265 | do_swi (void) |
09d92015 | 10266 | { |
e2b0ab59 AV |
10267 | inst.relocs[0].type = BFD_RELOC_ARM_SWI; |
10268 | inst.relocs[0].pc_rel = 0; | |
09d92015 MM |
10269 | } |
10270 | ||
ddfded2f MW |
10271 | static void |
10272 | do_setpan (void) | |
10273 | { | |
10274 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan), | |
10275 | _("selected processor does not support SETPAN instruction")); | |
10276 | ||
10277 | inst.instruction |= ((inst.operands[0].imm & 1) << 9); | |
10278 | } | |
10279 | ||
10280 | static void | |
10281 | do_t_setpan (void) | |
10282 | { | |
10283 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan), | |
10284 | _("selected processor does not support SETPAN instruction")); | |
10285 | ||
10286 | inst.instruction |= (inst.operands[0].imm << 3); | |
10287 | } | |
10288 | ||
c19d1205 ZW |
10289 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
10290 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
10291 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
10292 | Error if any register is R15. */ | |
e16bb312 | 10293 | |
c19d1205 ZW |
10294 | static void |
10295 | do_smla (void) | |
e16bb312 | 10296 | { |
c19d1205 ZW |
10297 | inst.instruction |= inst.operands[0].reg << 16; |
10298 | inst.instruction |= inst.operands[1].reg; | |
10299 | inst.instruction |= inst.operands[2].reg << 8; | |
10300 | inst.instruction |= inst.operands[3].reg << 12; | |
10301 | } | |
a737bd4d | 10302 | |
c19d1205 ZW |
10303 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
10304 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
10305 | Error if any register is R15. | |
10306 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 10307 | |
c19d1205 ZW |
10308 | static void |
10309 | do_smlal (void) | |
10310 | { | |
10311 | inst.instruction |= inst.operands[0].reg << 12; | |
10312 | inst.instruction |= inst.operands[1].reg << 16; | |
10313 | inst.instruction |= inst.operands[2].reg; | |
10314 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 10315 | |
c19d1205 ZW |
10316 | if (inst.operands[0].reg == inst.operands[1].reg) |
10317 | as_tsktsk (_("rdhi and rdlo must be different")); | |
10318 | } | |
a737bd4d | 10319 | |
c19d1205 ZW |
10320 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
10321 | SMULxy{cond} Rd,Rm,Rs | |
10322 | Error if any register is R15. */ | |
a737bd4d | 10323 | |
c19d1205 ZW |
10324 | static void |
10325 | do_smul (void) | |
10326 | { | |
10327 | inst.instruction |= inst.operands[0].reg << 16; | |
10328 | inst.instruction |= inst.operands[1].reg; | |
10329 | inst.instruction |= inst.operands[2].reg << 8; | |
10330 | } | |
a737bd4d | 10331 | |
b6702015 PB |
10332 | /* ARM V6 srs (argument parse). The variable fields in the encoding are |
10333 | the same for both ARM and Thumb-2. */ | |
a737bd4d | 10334 | |
c19d1205 ZW |
10335 | static void |
10336 | do_srs (void) | |
10337 | { | |
b6702015 PB |
10338 | int reg; |
10339 | ||
10340 | if (inst.operands[0].present) | |
10341 | { | |
10342 | reg = inst.operands[0].reg; | |
fdfde340 | 10343 | constraint (reg != REG_SP, _("SRS base register must be r13")); |
b6702015 PB |
10344 | } |
10345 | else | |
fdfde340 | 10346 | reg = REG_SP; |
b6702015 PB |
10347 | |
10348 | inst.instruction |= reg << 16; | |
10349 | inst.instruction |= inst.operands[1].imm; | |
10350 | if (inst.operands[0].writeback || inst.operands[1].writeback) | |
c19d1205 ZW |
10351 | inst.instruction |= WRITE_BACK; |
10352 | } | |
a737bd4d | 10353 | |
c19d1205 | 10354 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 10355 | |
c19d1205 ZW |
10356 | static void |
10357 | do_strex (void) | |
10358 | { | |
10359 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
10360 | || inst.operands[2].postind || inst.operands[2].writeback | |
10361 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
01cfc07f NC |
10362 | || inst.operands[2].negative |
10363 | /* See comment in do_ldrex(). */ | |
10364 | || (inst.operands[2].reg == REG_PC), | |
10365 | BAD_ADDR_MODE); | |
a737bd4d | 10366 | |
c19d1205 ZW |
10367 | constraint (inst.operands[0].reg == inst.operands[1].reg |
10368 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 10369 | |
e2b0ab59 AV |
10370 | constraint (inst.relocs[0].exp.X_op != O_constant |
10371 | || inst.relocs[0].exp.X_add_number != 0, | |
c19d1205 | 10372 | _("offset must be zero in ARM encoding")); |
a737bd4d | 10373 | |
c19d1205 ZW |
10374 | inst.instruction |= inst.operands[0].reg << 12; |
10375 | inst.instruction |= inst.operands[1].reg; | |
10376 | inst.instruction |= inst.operands[2].reg << 16; | |
e2b0ab59 | 10377 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
e16bb312 NC |
10378 | } |
10379 | ||
877807f8 NC |
10380 | static void |
10381 | do_t_strexbh (void) | |
10382 | { | |
10383 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
10384 | || inst.operands[2].postind || inst.operands[2].writeback | |
10385 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
10386 | || inst.operands[2].negative, | |
10387 | BAD_ADDR_MODE); | |
10388 | ||
10389 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
10390 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
10391 | ||
10392 | do_rm_rd_rn (); | |
10393 | } | |
10394 | ||
e16bb312 | 10395 | static void |
c19d1205 | 10396 | do_strexd (void) |
e16bb312 | 10397 | { |
c19d1205 ZW |
10398 | constraint (inst.operands[1].reg % 2 != 0, |
10399 | _("even register required")); | |
10400 | constraint (inst.operands[2].present | |
10401 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
10402 | _("can only store two consecutive registers")); | |
10403 | /* If op 2 were present and equal to PC, this function wouldn't | |
10404 | have been called in the first place. */ | |
10405 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 10406 | |
c19d1205 ZW |
10407 | constraint (inst.operands[0].reg == inst.operands[1].reg |
10408 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
10409 | || inst.operands[0].reg == inst.operands[3].reg, | |
10410 | BAD_OVERLAP); | |
e16bb312 | 10411 | |
c19d1205 ZW |
10412 | inst.instruction |= inst.operands[0].reg << 12; |
10413 | inst.instruction |= inst.operands[1].reg; | |
10414 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
10415 | } |
10416 | ||
9eb6c0f1 MGD |
10417 | /* ARM V8 STRL. */ |
10418 | static void | |
4b8c8c02 | 10419 | do_stlex (void) |
9eb6c0f1 MGD |
10420 | { |
10421 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
10422 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
10423 | ||
10424 | do_rd_rm_rn (); | |
10425 | } | |
10426 | ||
10427 | static void | |
4b8c8c02 | 10428 | do_t_stlex (void) |
9eb6c0f1 MGD |
10429 | { |
10430 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
10431 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
10432 | ||
10433 | do_rm_rd_rn (); | |
10434 | } | |
10435 | ||
c19d1205 ZW |
10436 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
10437 | extends it to 32-bits, and adds the result to a value in another | |
10438 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
10439 | before extracting the 16-bit value. | |
10440 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
10441 | Condition defaults to COND_ALWAYS. | |
10442 | Error if any register uses R15. */ | |
10443 | ||
e16bb312 | 10444 | static void |
c19d1205 | 10445 | do_sxtah (void) |
e16bb312 | 10446 | { |
c19d1205 ZW |
10447 | inst.instruction |= inst.operands[0].reg << 12; |
10448 | inst.instruction |= inst.operands[1].reg << 16; | |
10449 | inst.instruction |= inst.operands[2].reg; | |
10450 | inst.instruction |= inst.operands[3].imm << 10; | |
10451 | } | |
e16bb312 | 10452 | |
c19d1205 | 10453 | /* ARM V6 SXTH. |
e16bb312 | 10454 | |
c19d1205 ZW |
10455 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
10456 | Condition defaults to COND_ALWAYS. | |
10457 | Error if any register uses R15. */ | |
e16bb312 NC |
10458 | |
10459 | static void | |
c19d1205 | 10460 | do_sxth (void) |
e16bb312 | 10461 | { |
c19d1205 ZW |
10462 | inst.instruction |= inst.operands[0].reg << 12; |
10463 | inst.instruction |= inst.operands[1].reg; | |
10464 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 10465 | } |
c19d1205 ZW |
10466 | \f |
10467 | /* VFP instructions. In a logical order: SP variant first, monad | |
10468 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
10469 | |
10470 | static void | |
c19d1205 | 10471 | do_vfp_sp_monadic (void) |
e16bb312 | 10472 | { |
57785aa2 AV |
10473 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd) |
10474 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
10475 | _(BAD_FPU)); | |
10476 | ||
5287ad62 JB |
10477 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
10478 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
10479 | } |
10480 | ||
10481 | static void | |
c19d1205 | 10482 | do_vfp_sp_dyadic (void) |
e16bb312 | 10483 | { |
5287ad62 JB |
10484 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
10485 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
10486 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
10487 | } |
10488 | ||
10489 | static void | |
c19d1205 | 10490 | do_vfp_sp_compare_z (void) |
e16bb312 | 10491 | { |
5287ad62 | 10492 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
10493 | } |
10494 | ||
10495 | static void | |
c19d1205 | 10496 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 10497 | { |
5287ad62 JB |
10498 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
10499 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
10500 | } |
10501 | ||
10502 | static void | |
c19d1205 | 10503 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 10504 | { |
5287ad62 JB |
10505 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
10506 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
e16bb312 NC |
10507 | } |
10508 | ||
10509 | static void | |
c19d1205 | 10510 | do_vfp_reg_from_sp (void) |
e16bb312 | 10511 | { |
57785aa2 AV |
10512 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd) |
10513 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
10514 | _(BAD_FPU)); | |
10515 | ||
c19d1205 | 10516 | inst.instruction |= inst.operands[0].reg << 12; |
5287ad62 | 10517 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); |
e16bb312 NC |
10518 | } |
10519 | ||
10520 | static void | |
c19d1205 | 10521 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 10522 | { |
c19d1205 ZW |
10523 | constraint (inst.operands[2].imm != 2, |
10524 | _("only two consecutive VFP SP registers allowed here")); | |
10525 | inst.instruction |= inst.operands[0].reg << 12; | |
10526 | inst.instruction |= inst.operands[1].reg << 16; | |
5287ad62 | 10527 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); |
e16bb312 NC |
10528 | } |
10529 | ||
10530 | static void | |
c19d1205 | 10531 | do_vfp_sp_from_reg (void) |
e16bb312 | 10532 | { |
57785aa2 AV |
10533 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd) |
10534 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
10535 | _(BAD_FPU)); | |
10536 | ||
5287ad62 | 10537 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); |
c19d1205 | 10538 | inst.instruction |= inst.operands[1].reg << 12; |
e16bb312 NC |
10539 | } |
10540 | ||
10541 | static void | |
c19d1205 | 10542 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 10543 | { |
c19d1205 ZW |
10544 | constraint (inst.operands[0].imm != 2, |
10545 | _("only two consecutive VFP SP registers allowed here")); | |
5287ad62 | 10546 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); |
c19d1205 ZW |
10547 | inst.instruction |= inst.operands[1].reg << 12; |
10548 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
10549 | } |
10550 | ||
10551 | static void | |
c19d1205 | 10552 | do_vfp_sp_ldst (void) |
e16bb312 | 10553 | { |
5287ad62 | 10554 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
c19d1205 | 10555 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
10556 | } |
10557 | ||
10558 | static void | |
c19d1205 | 10559 | do_vfp_dp_ldst (void) |
e16bb312 | 10560 | { |
5287ad62 | 10561 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
c19d1205 | 10562 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
10563 | } |
10564 | ||
c19d1205 | 10565 | |
e16bb312 | 10566 | static void |
c19d1205 | 10567 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 10568 | { |
c19d1205 ZW |
10569 | if (inst.operands[0].writeback) |
10570 | inst.instruction |= WRITE_BACK; | |
10571 | else | |
10572 | constraint (ldstm_type != VFP_LDSTMIA, | |
10573 | _("this addressing mode requires base-register writeback")); | |
10574 | inst.instruction |= inst.operands[0].reg << 16; | |
5287ad62 | 10575 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); |
c19d1205 | 10576 | inst.instruction |= inst.operands[1].imm; |
e16bb312 NC |
10577 | } |
10578 | ||
10579 | static void | |
c19d1205 | 10580 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 10581 | { |
c19d1205 | 10582 | int count; |
e16bb312 | 10583 | |
c19d1205 ZW |
10584 | if (inst.operands[0].writeback) |
10585 | inst.instruction |= WRITE_BACK; | |
10586 | else | |
10587 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
10588 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 10589 | |
c19d1205 | 10590 | inst.instruction |= inst.operands[0].reg << 16; |
5287ad62 | 10591 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
e16bb312 | 10592 | |
c19d1205 ZW |
10593 | count = inst.operands[1].imm << 1; |
10594 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
10595 | count += 1; | |
e16bb312 | 10596 | |
c19d1205 | 10597 | inst.instruction |= count; |
e16bb312 NC |
10598 | } |
10599 | ||
10600 | static void | |
c19d1205 | 10601 | do_vfp_sp_ldstmia (void) |
e16bb312 | 10602 | { |
c19d1205 | 10603 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
10604 | } |
10605 | ||
10606 | static void | |
c19d1205 | 10607 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 10608 | { |
c19d1205 | 10609 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
10610 | } |
10611 | ||
10612 | static void | |
c19d1205 | 10613 | do_vfp_dp_ldstmia (void) |
e16bb312 | 10614 | { |
c19d1205 | 10615 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
10616 | } |
10617 | ||
10618 | static void | |
c19d1205 | 10619 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 10620 | { |
c19d1205 | 10621 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
10622 | } |
10623 | ||
10624 | static void | |
c19d1205 | 10625 | do_vfp_xp_ldstmia (void) |
e16bb312 | 10626 | { |
c19d1205 ZW |
10627 | vfp_dp_ldstm (VFP_LDSTMIAX); |
10628 | } | |
e16bb312 | 10629 | |
c19d1205 ZW |
10630 | static void |
10631 | do_vfp_xp_ldstmdb (void) | |
10632 | { | |
10633 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 10634 | } |
5287ad62 JB |
10635 | |
10636 | static void | |
10637 | do_vfp_dp_rd_rm (void) | |
10638 | { | |
57785aa2 AV |
10639 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1) |
10640 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
10641 | _(BAD_FPU)); | |
10642 | ||
5287ad62 JB |
10643 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
10644 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
10645 | } | |
10646 | ||
10647 | static void | |
10648 | do_vfp_dp_rn_rd (void) | |
10649 | { | |
10650 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); | |
10651 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
10652 | } | |
10653 | ||
10654 | static void | |
10655 | do_vfp_dp_rd_rn (void) | |
10656 | { | |
10657 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
10658 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
10659 | } | |
10660 | ||
10661 | static void | |
10662 | do_vfp_dp_rd_rn_rm (void) | |
10663 | { | |
57785aa2 AV |
10664 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) |
10665 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
10666 | _(BAD_FPU)); | |
10667 | ||
5287ad62 JB |
10668 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
10669 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
10670 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); | |
10671 | } | |
10672 | ||
10673 | static void | |
10674 | do_vfp_dp_rd (void) | |
10675 | { | |
10676 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
10677 | } | |
10678 | ||
10679 | static void | |
10680 | do_vfp_dp_rm_rd_rn (void) | |
10681 | { | |
57785aa2 AV |
10682 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) |
10683 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
10684 | _(BAD_FPU)); | |
10685 | ||
5287ad62 JB |
10686 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); |
10687 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
10688 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); | |
10689 | } | |
10690 | ||
10691 | /* VFPv3 instructions. */ | |
10692 | static void | |
10693 | do_vfp_sp_const (void) | |
10694 | { | |
10695 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
00249aaa PB |
10696 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
10697 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
10698 | } |
10699 | ||
10700 | static void | |
10701 | do_vfp_dp_const (void) | |
10702 | { | |
10703 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
00249aaa PB |
10704 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
10705 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
10706 | } |
10707 | ||
10708 | static void | |
10709 | vfp_conv (int srcsize) | |
10710 | { | |
5f1af56b MGD |
10711 | int immbits = srcsize - inst.operands[1].imm; |
10712 | ||
fa94de6b RM |
10713 | if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize)) |
10714 | { | |
5f1af56b | 10715 | /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16. |
477330fc | 10716 | i.e. immbits must be in range 0 - 16. */ |
5f1af56b MGD |
10717 | inst.error = _("immediate value out of range, expected range [0, 16]"); |
10718 | return; | |
10719 | } | |
fa94de6b | 10720 | else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize)) |
5f1af56b MGD |
10721 | { |
10722 | /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32. | |
477330fc | 10723 | i.e. immbits must be in range 0 - 31. */ |
5f1af56b MGD |
10724 | inst.error = _("immediate value out of range, expected range [1, 32]"); |
10725 | return; | |
10726 | } | |
10727 | ||
5287ad62 JB |
10728 | inst.instruction |= (immbits & 1) << 5; |
10729 | inst.instruction |= (immbits >> 1); | |
10730 | } | |
10731 | ||
10732 | static void | |
10733 | do_vfp_sp_conv_16 (void) | |
10734 | { | |
10735 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
10736 | vfp_conv (16); | |
10737 | } | |
10738 | ||
10739 | static void | |
10740 | do_vfp_dp_conv_16 (void) | |
10741 | { | |
10742 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
10743 | vfp_conv (16); | |
10744 | } | |
10745 | ||
10746 | static void | |
10747 | do_vfp_sp_conv_32 (void) | |
10748 | { | |
10749 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
10750 | vfp_conv (32); | |
10751 | } | |
10752 | ||
10753 | static void | |
10754 | do_vfp_dp_conv_32 (void) | |
10755 | { | |
10756 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
10757 | vfp_conv (32); | |
10758 | } | |
c19d1205 ZW |
10759 | \f |
10760 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 10761 | |
c19d1205 ZW |
10762 | static void |
10763 | do_fpa_cmp (void) | |
10764 | { | |
10765 | inst.instruction |= inst.operands[0].reg << 16; | |
10766 | inst.instruction |= inst.operands[1].reg; | |
10767 | } | |
b99bd4ef NC |
10768 | |
10769 | static void | |
c19d1205 | 10770 | do_fpa_ldmstm (void) |
b99bd4ef | 10771 | { |
c19d1205 ZW |
10772 | inst.instruction |= inst.operands[0].reg << 12; |
10773 | switch (inst.operands[1].imm) | |
10774 | { | |
10775 | case 1: inst.instruction |= CP_T_X; break; | |
10776 | case 2: inst.instruction |= CP_T_Y; break; | |
10777 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
10778 | case 4: break; | |
10779 | default: abort (); | |
10780 | } | |
b99bd4ef | 10781 | |
c19d1205 ZW |
10782 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
10783 | { | |
10784 | /* The instruction specified "ea" or "fd", so we can only accept | |
10785 | [Rn]{!}. The instruction does not really support stacking or | |
10786 | unstacking, so we have to emulate these by setting appropriate | |
10787 | bits and offsets. */ | |
e2b0ab59 AV |
10788 | constraint (inst.relocs[0].exp.X_op != O_constant |
10789 | || inst.relocs[0].exp.X_add_number != 0, | |
c19d1205 | 10790 | _("this instruction does not support indexing")); |
b99bd4ef | 10791 | |
c19d1205 | 10792 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
e2b0ab59 | 10793 | inst.relocs[0].exp.X_add_number = 12 * inst.operands[1].imm; |
b99bd4ef | 10794 | |
c19d1205 | 10795 | if (!(inst.instruction & INDEX_UP)) |
e2b0ab59 | 10796 | inst.relocs[0].exp.X_add_number = -inst.relocs[0].exp.X_add_number; |
b99bd4ef | 10797 | |
c19d1205 ZW |
10798 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
10799 | { | |
10800 | inst.operands[2].preind = 0; | |
10801 | inst.operands[2].postind = 1; | |
10802 | } | |
10803 | } | |
b99bd4ef | 10804 | |
c19d1205 | 10805 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 10806 | } |
c19d1205 ZW |
10807 | \f |
10808 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 10809 | |
c19d1205 ZW |
10810 | static void |
10811 | do_iwmmxt_tandorc (void) | |
10812 | { | |
10813 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
10814 | } | |
b99bd4ef | 10815 | |
c19d1205 ZW |
10816 | static void |
10817 | do_iwmmxt_textrc (void) | |
10818 | { | |
10819 | inst.instruction |= inst.operands[0].reg << 12; | |
10820 | inst.instruction |= inst.operands[1].imm; | |
10821 | } | |
b99bd4ef NC |
10822 | |
10823 | static void | |
c19d1205 | 10824 | do_iwmmxt_textrm (void) |
b99bd4ef | 10825 | { |
c19d1205 ZW |
10826 | inst.instruction |= inst.operands[0].reg << 12; |
10827 | inst.instruction |= inst.operands[1].reg << 16; | |
10828 | inst.instruction |= inst.operands[2].imm; | |
10829 | } | |
b99bd4ef | 10830 | |
c19d1205 ZW |
10831 | static void |
10832 | do_iwmmxt_tinsr (void) | |
10833 | { | |
10834 | inst.instruction |= inst.operands[0].reg << 16; | |
10835 | inst.instruction |= inst.operands[1].reg << 12; | |
10836 | inst.instruction |= inst.operands[2].imm; | |
10837 | } | |
b99bd4ef | 10838 | |
c19d1205 ZW |
10839 | static void |
10840 | do_iwmmxt_tmia (void) | |
10841 | { | |
10842 | inst.instruction |= inst.operands[0].reg << 5; | |
10843 | inst.instruction |= inst.operands[1].reg; | |
10844 | inst.instruction |= inst.operands[2].reg << 12; | |
10845 | } | |
b99bd4ef | 10846 | |
c19d1205 ZW |
10847 | static void |
10848 | do_iwmmxt_waligni (void) | |
10849 | { | |
10850 | inst.instruction |= inst.operands[0].reg << 12; | |
10851 | inst.instruction |= inst.operands[1].reg << 16; | |
10852 | inst.instruction |= inst.operands[2].reg; | |
10853 | inst.instruction |= inst.operands[3].imm << 20; | |
10854 | } | |
b99bd4ef | 10855 | |
2d447fca JM |
10856 | static void |
10857 | do_iwmmxt_wmerge (void) | |
10858 | { | |
10859 | inst.instruction |= inst.operands[0].reg << 12; | |
10860 | inst.instruction |= inst.operands[1].reg << 16; | |
10861 | inst.instruction |= inst.operands[2].reg; | |
10862 | inst.instruction |= inst.operands[3].imm << 21; | |
10863 | } | |
10864 | ||
c19d1205 ZW |
10865 | static void |
10866 | do_iwmmxt_wmov (void) | |
10867 | { | |
10868 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
10869 | inst.instruction |= inst.operands[0].reg << 12; | |
10870 | inst.instruction |= inst.operands[1].reg << 16; | |
10871 | inst.instruction |= inst.operands[1].reg; | |
10872 | } | |
b99bd4ef | 10873 | |
c19d1205 ZW |
10874 | static void |
10875 | do_iwmmxt_wldstbh (void) | |
10876 | { | |
8f06b2d8 | 10877 | int reloc; |
c19d1205 | 10878 | inst.instruction |= inst.operands[0].reg << 12; |
8f06b2d8 PB |
10879 | if (thumb_mode) |
10880 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
10881 | else | |
10882 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
10883 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
10884 | } |
10885 | ||
c19d1205 ZW |
10886 | static void |
10887 | do_iwmmxt_wldstw (void) | |
10888 | { | |
10889 | /* RIWR_RIWC clears .isreg for a control register. */ | |
10890 | if (!inst.operands[0].isreg) | |
10891 | { | |
10892 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
10893 | inst.instruction |= 0xf0000000; | |
10894 | } | |
b99bd4ef | 10895 | |
c19d1205 ZW |
10896 | inst.instruction |= inst.operands[0].reg << 12; |
10897 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
10898 | } | |
b99bd4ef NC |
10899 | |
10900 | static void | |
c19d1205 | 10901 | do_iwmmxt_wldstd (void) |
b99bd4ef | 10902 | { |
c19d1205 | 10903 | inst.instruction |= inst.operands[0].reg << 12; |
2d447fca JM |
10904 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) |
10905 | && inst.operands[1].immisreg) | |
10906 | { | |
10907 | inst.instruction &= ~0x1a000ff; | |
eff0bc54 | 10908 | inst.instruction |= (0xfU << 28); |
2d447fca JM |
10909 | if (inst.operands[1].preind) |
10910 | inst.instruction |= PRE_INDEX; | |
10911 | if (!inst.operands[1].negative) | |
10912 | inst.instruction |= INDEX_UP; | |
10913 | if (inst.operands[1].writeback) | |
10914 | inst.instruction |= WRITE_BACK; | |
10915 | inst.instruction |= inst.operands[1].reg << 16; | |
e2b0ab59 | 10916 | inst.instruction |= inst.relocs[0].exp.X_add_number << 4; |
2d447fca JM |
10917 | inst.instruction |= inst.operands[1].imm; |
10918 | } | |
10919 | else | |
10920 | encode_arm_cp_address (1, TRUE, FALSE, 0); | |
c19d1205 | 10921 | } |
b99bd4ef | 10922 | |
c19d1205 ZW |
10923 | static void |
10924 | do_iwmmxt_wshufh (void) | |
10925 | { | |
10926 | inst.instruction |= inst.operands[0].reg << 12; | |
10927 | inst.instruction |= inst.operands[1].reg << 16; | |
10928 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
10929 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
10930 | } | |
b99bd4ef | 10931 | |
c19d1205 ZW |
10932 | static void |
10933 | do_iwmmxt_wzero (void) | |
10934 | { | |
10935 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
10936 | inst.instruction |= inst.operands[0].reg; | |
10937 | inst.instruction |= inst.operands[0].reg << 12; | |
10938 | inst.instruction |= inst.operands[0].reg << 16; | |
10939 | } | |
2d447fca JM |
10940 | |
10941 | static void | |
10942 | do_iwmmxt_wrwrwr_or_imm5 (void) | |
10943 | { | |
10944 | if (inst.operands[2].isreg) | |
10945 | do_rd_rn_rm (); | |
10946 | else { | |
10947 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), | |
10948 | _("immediate operand requires iWMMXt2")); | |
10949 | do_rd_rn (); | |
10950 | if (inst.operands[2].imm == 0) | |
10951 | { | |
10952 | switch ((inst.instruction >> 20) & 0xf) | |
10953 | { | |
10954 | case 4: | |
10955 | case 5: | |
10956 | case 6: | |
5f4273c7 | 10957 | case 7: |
2d447fca JM |
10958 | /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ |
10959 | inst.operands[2].imm = 16; | |
10960 | inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); | |
10961 | break; | |
10962 | case 8: | |
10963 | case 9: | |
10964 | case 10: | |
10965 | case 11: | |
10966 | /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ | |
10967 | inst.operands[2].imm = 32; | |
10968 | inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); | |
10969 | break; | |
10970 | case 12: | |
10971 | case 13: | |
10972 | case 14: | |
10973 | case 15: | |
10974 | { | |
10975 | /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ | |
10976 | unsigned long wrn; | |
10977 | wrn = (inst.instruction >> 16) & 0xf; | |
10978 | inst.instruction &= 0xff0fff0f; | |
10979 | inst.instruction |= wrn; | |
10980 | /* Bail out here; the instruction is now assembled. */ | |
10981 | return; | |
10982 | } | |
10983 | } | |
10984 | } | |
10985 | /* Map 32 -> 0, etc. */ | |
10986 | inst.operands[2].imm &= 0x1f; | |
eff0bc54 | 10987 | inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); |
2d447fca JM |
10988 | } |
10989 | } | |
c19d1205 ZW |
10990 | \f |
10991 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
10992 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 10993 | |
c19d1205 | 10994 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 10995 | |
c19d1205 ZW |
10996 | static void |
10997 | do_mav_triple (void) | |
10998 | { | |
10999 | inst.instruction |= inst.operands[0].reg << 16; | |
11000 | inst.instruction |= inst.operands[1].reg; | |
11001 | inst.instruction |= inst.operands[2].reg << 12; | |
11002 | } | |
b99bd4ef | 11003 | |
c19d1205 ZW |
11004 | /* Insns like "foo W,X,Y,Z". |
11005 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 11006 | |
c19d1205 ZW |
11007 | static void |
11008 | do_mav_quad (void) | |
11009 | { | |
11010 | inst.instruction |= inst.operands[0].reg << 5; | |
11011 | inst.instruction |= inst.operands[1].reg << 12; | |
11012 | inst.instruction |= inst.operands[2].reg << 16; | |
11013 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
11014 | } |
11015 | ||
c19d1205 ZW |
11016 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
11017 | static void | |
11018 | do_mav_dspsc (void) | |
a737bd4d | 11019 | { |
c19d1205 ZW |
11020 | inst.instruction |= inst.operands[1].reg << 12; |
11021 | } | |
a737bd4d | 11022 | |
c19d1205 ZW |
11023 | /* Maverick shift immediate instructions. |
11024 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
11025 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 11026 | |
c19d1205 ZW |
11027 | static void |
11028 | do_mav_shift (void) | |
11029 | { | |
11030 | int imm = inst.operands[2].imm; | |
a737bd4d | 11031 | |
c19d1205 ZW |
11032 | inst.instruction |= inst.operands[0].reg << 12; |
11033 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 11034 | |
c19d1205 ZW |
11035 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
11036 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
11037 | Bit 4 should be 0. */ | |
11038 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 11039 | |
c19d1205 ZW |
11040 | inst.instruction |= imm; |
11041 | } | |
11042 | \f | |
11043 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 11044 | |
c19d1205 ZW |
11045 | /* Xscale multiply-accumulate (argument parse) |
11046 | MIAcc acc0,Rm,Rs | |
11047 | MIAPHcc acc0,Rm,Rs | |
11048 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 11049 | |
c19d1205 ZW |
11050 | static void |
11051 | do_xsc_mia (void) | |
11052 | { | |
11053 | inst.instruction |= inst.operands[1].reg; | |
11054 | inst.instruction |= inst.operands[2].reg << 12; | |
11055 | } | |
a737bd4d | 11056 | |
c19d1205 | 11057 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 11058 | |
c19d1205 | 11059 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 11060 | |
c19d1205 ZW |
11061 | static void |
11062 | do_xsc_mar (void) | |
11063 | { | |
11064 | inst.instruction |= inst.operands[1].reg << 12; | |
11065 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
11066 | } |
11067 | ||
c19d1205 | 11068 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 11069 | |
c19d1205 | 11070 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
11071 | |
11072 | static void | |
c19d1205 | 11073 | do_xsc_mra (void) |
b99bd4ef | 11074 | { |
c19d1205 ZW |
11075 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
11076 | inst.instruction |= inst.operands[0].reg << 12; | |
11077 | inst.instruction |= inst.operands[1].reg << 16; | |
11078 | } | |
11079 | \f | |
11080 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 11081 | |
c19d1205 ZW |
11082 | /* inst.operands[i] is a shifted-register operand; encode |
11083 | it into inst.instruction in the format used by Thumb32. */ | |
11084 | ||
11085 | static void | |
11086 | encode_thumb32_shifted_operand (int i) | |
11087 | { | |
e2b0ab59 | 11088 | unsigned int value = inst.relocs[0].exp.X_add_number; |
c19d1205 | 11089 | unsigned int shift = inst.operands[i].shift_kind; |
b99bd4ef | 11090 | |
9c3c69f2 PB |
11091 | constraint (inst.operands[i].immisreg, |
11092 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
11093 | inst.instruction |= inst.operands[i].reg; |
11094 | if (shift == SHIFT_RRX) | |
11095 | inst.instruction |= SHIFT_ROR << 4; | |
11096 | else | |
b99bd4ef | 11097 | { |
e2b0ab59 | 11098 | constraint (inst.relocs[0].exp.X_op != O_constant, |
c19d1205 ZW |
11099 | _("expression too complex")); |
11100 | ||
11101 | constraint (value > 32 | |
11102 | || (value == 32 && (shift == SHIFT_LSL | |
11103 | || shift == SHIFT_ROR)), | |
11104 | _("shift expression is too large")); | |
11105 | ||
11106 | if (value == 0) | |
11107 | shift = SHIFT_LSL; | |
11108 | else if (value == 32) | |
11109 | value = 0; | |
11110 | ||
11111 | inst.instruction |= shift << 4; | |
11112 | inst.instruction |= (value & 0x1c) << 10; | |
11113 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 11114 | } |
c19d1205 | 11115 | } |
b99bd4ef | 11116 | |
b99bd4ef | 11117 | |
c19d1205 ZW |
11118 | /* inst.operands[i] was set up by parse_address. Encode it into a |
11119 | Thumb32 format load or store instruction. Reject forms that cannot | |
11120 | be used with such instructions. If is_t is true, reject forms that | |
11121 | cannot be used with a T instruction; if is_d is true, reject forms | |
5be8be5d DG |
11122 | that cannot be used with a D instruction. If it is a store insn, |
11123 | reject PC in Rn. */ | |
b99bd4ef | 11124 | |
c19d1205 ZW |
11125 | static void |
11126 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
11127 | { | |
5be8be5d | 11128 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
c19d1205 ZW |
11129 | |
11130 | constraint (!inst.operands[i].isreg, | |
53365c0d | 11131 | _("Instruction does not support =N addresses")); |
b99bd4ef | 11132 | |
c19d1205 ZW |
11133 | inst.instruction |= inst.operands[i].reg << 16; |
11134 | if (inst.operands[i].immisreg) | |
b99bd4ef | 11135 | { |
5be8be5d | 11136 | constraint (is_pc, BAD_PC_ADDRESSING); |
c19d1205 ZW |
11137 | constraint (is_t || is_d, _("cannot use register index with this instruction")); |
11138 | constraint (inst.operands[i].negative, | |
11139 | _("Thumb does not support negative register indexing")); | |
11140 | constraint (inst.operands[i].postind, | |
11141 | _("Thumb does not support register post-indexing")); | |
11142 | constraint (inst.operands[i].writeback, | |
11143 | _("Thumb does not support register indexing with writeback")); | |
11144 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
11145 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 11146 | |
f40d1643 | 11147 | inst.instruction |= inst.operands[i].imm; |
c19d1205 | 11148 | if (inst.operands[i].shifted) |
b99bd4ef | 11149 | { |
e2b0ab59 | 11150 | constraint (inst.relocs[0].exp.X_op != O_constant, |
c19d1205 | 11151 | _("expression too complex")); |
e2b0ab59 AV |
11152 | constraint (inst.relocs[0].exp.X_add_number < 0 |
11153 | || inst.relocs[0].exp.X_add_number > 3, | |
c19d1205 | 11154 | _("shift out of range")); |
e2b0ab59 | 11155 | inst.instruction |= inst.relocs[0].exp.X_add_number << 4; |
c19d1205 | 11156 | } |
e2b0ab59 | 11157 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
c19d1205 ZW |
11158 | } |
11159 | else if (inst.operands[i].preind) | |
11160 | { | |
5be8be5d | 11161 | constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK); |
f40d1643 | 11162 | constraint (is_t && inst.operands[i].writeback, |
c19d1205 | 11163 | _("cannot use writeback with this instruction")); |
4755303e WN |
11164 | constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0), |
11165 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
11166 | |
11167 | if (is_d) | |
11168 | { | |
11169 | inst.instruction |= 0x01000000; | |
11170 | if (inst.operands[i].writeback) | |
11171 | inst.instruction |= 0x00200000; | |
b99bd4ef | 11172 | } |
c19d1205 | 11173 | else |
b99bd4ef | 11174 | { |
c19d1205 ZW |
11175 | inst.instruction |= 0x00000c00; |
11176 | if (inst.operands[i].writeback) | |
11177 | inst.instruction |= 0x00000100; | |
b99bd4ef | 11178 | } |
e2b0ab59 | 11179 | inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 11180 | } |
c19d1205 | 11181 | else if (inst.operands[i].postind) |
b99bd4ef | 11182 | { |
9c2799c2 | 11183 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
11184 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); |
11185 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
11186 | ||
11187 | if (is_d) | |
11188 | inst.instruction |= 0x00200000; | |
11189 | else | |
11190 | inst.instruction |= 0x00000900; | |
e2b0ab59 | 11191 | inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
c19d1205 ZW |
11192 | } |
11193 | else /* unindexed - only for coprocessor */ | |
11194 | inst.error = _("instruction does not accept unindexed addressing"); | |
11195 | } | |
11196 | ||
e39c1607 | 11197 | /* Table of Thumb instructions which exist in 16- and/or 32-bit |
c19d1205 ZW |
11198 | encodings (the latter only in post-V6T2 cores). The index is the |
11199 | value used in the insns table below. When there is more than one | |
11200 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
11201 | holds variant (1). |
11202 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 | 11203 | #define T16_32_TAB \ |
21d799b5 NC |
11204 | X(_adc, 4140, eb400000), \ |
11205 | X(_adcs, 4140, eb500000), \ | |
11206 | X(_add, 1c00, eb000000), \ | |
11207 | X(_adds, 1c00, eb100000), \ | |
11208 | X(_addi, 0000, f1000000), \ | |
11209 | X(_addis, 0000, f1100000), \ | |
11210 | X(_add_pc,000f, f20f0000), \ | |
11211 | X(_add_sp,000d, f10d0000), \ | |
11212 | X(_adr, 000f, f20f0000), \ | |
11213 | X(_and, 4000, ea000000), \ | |
11214 | X(_ands, 4000, ea100000), \ | |
11215 | X(_asr, 1000, fa40f000), \ | |
11216 | X(_asrs, 1000, fa50f000), \ | |
11217 | X(_b, e000, f000b000), \ | |
11218 | X(_bcond, d000, f0008000), \ | |
4389b29a | 11219 | X(_bf, 0000, f040e001), \ |
f6b2b12d | 11220 | X(_bfcsel,0000, f000e001), \ |
f1c7f421 | 11221 | X(_bfx, 0000, f060e001), \ |
65d1bc05 | 11222 | X(_bfl, 0000, f000c001), \ |
f1c7f421 | 11223 | X(_bflx, 0000, f070e001), \ |
21d799b5 NC |
11224 | X(_bic, 4380, ea200000), \ |
11225 | X(_bics, 4380, ea300000), \ | |
e39c1607 SD |
11226 | X(_cinc, 0000, ea509000), \ |
11227 | X(_cinv, 0000, ea50a000), \ | |
21d799b5 NC |
11228 | X(_cmn, 42c0, eb100f00), \ |
11229 | X(_cmp, 2800, ebb00f00), \ | |
e39c1607 | 11230 | X(_cneg, 0000, ea50b000), \ |
21d799b5 NC |
11231 | X(_cpsie, b660, f3af8400), \ |
11232 | X(_cpsid, b670, f3af8600), \ | |
11233 | X(_cpy, 4600, ea4f0000), \ | |
e39c1607 SD |
11234 | X(_csel, 0000, ea508000), \ |
11235 | X(_cset, 0000, ea5f900f), \ | |
11236 | X(_csetm, 0000, ea5fa00f), \ | |
11237 | X(_csinc, 0000, ea509000), \ | |
11238 | X(_csinv, 0000, ea50a000), \ | |
11239 | X(_csneg, 0000, ea50b000), \ | |
21d799b5 | 11240 | X(_dec_sp,80dd, f1ad0d00), \ |
60f993ce | 11241 | X(_dls, 0000, f040e001), \ |
1f6234a3 | 11242 | X(_dlstp, 0000, f000e001), \ |
21d799b5 NC |
11243 | X(_eor, 4040, ea800000), \ |
11244 | X(_eors, 4040, ea900000), \ | |
11245 | X(_inc_sp,00dd, f10d0d00), \ | |
1f6234a3 | 11246 | X(_lctp, 0000, f00fe001), \ |
21d799b5 NC |
11247 | X(_ldmia, c800, e8900000), \ |
11248 | X(_ldr, 6800, f8500000), \ | |
11249 | X(_ldrb, 7800, f8100000), \ | |
11250 | X(_ldrh, 8800, f8300000), \ | |
11251 | X(_ldrsb, 5600, f9100000), \ | |
11252 | X(_ldrsh, 5e00, f9300000), \ | |
11253 | X(_ldr_pc,4800, f85f0000), \ | |
11254 | X(_ldr_pc2,4800, f85f0000), \ | |
11255 | X(_ldr_sp,9800, f85d0000), \ | |
60f993ce | 11256 | X(_le, 0000, f00fc001), \ |
1f6234a3 | 11257 | X(_letp, 0000, f01fc001), \ |
21d799b5 NC |
11258 | X(_lsl, 0000, fa00f000), \ |
11259 | X(_lsls, 0000, fa10f000), \ | |
11260 | X(_lsr, 0800, fa20f000), \ | |
11261 | X(_lsrs, 0800, fa30f000), \ | |
11262 | X(_mov, 2000, ea4f0000), \ | |
11263 | X(_movs, 2000, ea5f0000), \ | |
11264 | X(_mul, 4340, fb00f000), \ | |
11265 | X(_muls, 4340, ffffffff), /* no 32b muls */ \ | |
11266 | X(_mvn, 43c0, ea6f0000), \ | |
11267 | X(_mvns, 43c0, ea7f0000), \ | |
11268 | X(_neg, 4240, f1c00000), /* rsb #0 */ \ | |
11269 | X(_negs, 4240, f1d00000), /* rsbs #0 */ \ | |
11270 | X(_orr, 4300, ea400000), \ | |
11271 | X(_orrs, 4300, ea500000), \ | |
11272 | X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \ | |
11273 | X(_push, b400, e92d0000), /* stmdb sp!,... */ \ | |
11274 | X(_rev, ba00, fa90f080), \ | |
11275 | X(_rev16, ba40, fa90f090), \ | |
11276 | X(_revsh, bac0, fa90f0b0), \ | |
11277 | X(_ror, 41c0, fa60f000), \ | |
11278 | X(_rors, 41c0, fa70f000), \ | |
11279 | X(_sbc, 4180, eb600000), \ | |
11280 | X(_sbcs, 4180, eb700000), \ | |
11281 | X(_stmia, c000, e8800000), \ | |
11282 | X(_str, 6000, f8400000), \ | |
11283 | X(_strb, 7000, f8000000), \ | |
11284 | X(_strh, 8000, f8200000), \ | |
11285 | X(_str_sp,9000, f84d0000), \ | |
11286 | X(_sub, 1e00, eba00000), \ | |
11287 | X(_subs, 1e00, ebb00000), \ | |
11288 | X(_subi, 8000, f1a00000), \ | |
11289 | X(_subis, 8000, f1b00000), \ | |
11290 | X(_sxtb, b240, fa4ff080), \ | |
11291 | X(_sxth, b200, fa0ff080), \ | |
11292 | X(_tst, 4200, ea100f00), \ | |
11293 | X(_uxtb, b2c0, fa5ff080), \ | |
11294 | X(_uxth, b280, fa1ff080), \ | |
11295 | X(_nop, bf00, f3af8000), \ | |
11296 | X(_yield, bf10, f3af8001), \ | |
11297 | X(_wfe, bf20, f3af8002), \ | |
11298 | X(_wfi, bf30, f3af8003), \ | |
60f993ce | 11299 | X(_wls, 0000, f040c001), \ |
1f6234a3 | 11300 | X(_wlstp, 0000, f000c001), \ |
53c4b28b | 11301 | X(_sev, bf40, f3af8004), \ |
74db7efb NC |
11302 | X(_sevl, bf50, f3af8005), \ |
11303 | X(_udf, de00, f7f0a000) | |
c19d1205 ZW |
11304 | |
11305 | /* To catch errors in encoding functions, the codes are all offset by | |
11306 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
11307 | as 16-bit instructions. */ | |
21d799b5 | 11308 | #define X(a,b,c) T_MNEM##a |
c19d1205 ZW |
11309 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; |
11310 | #undef X | |
11311 | ||
11312 | #define X(a,b,c) 0x##b | |
11313 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
11314 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
11315 | #undef X | |
11316 | ||
11317 | #define X(a,b,c) 0x##c | |
11318 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
c921be7d NC |
11319 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) |
11320 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
c19d1205 ZW |
11321 | #undef X |
11322 | #undef T16_32_TAB | |
11323 | ||
11324 | /* Thumb instruction encoders, in alphabetical order. */ | |
11325 | ||
92e90b6e | 11326 | /* ADDW or SUBW. */ |
c921be7d | 11327 | |
92e90b6e PB |
11328 | static void |
11329 | do_t_add_sub_w (void) | |
11330 | { | |
11331 | int Rd, Rn; | |
11332 | ||
11333 | Rd = inst.operands[0].reg; | |
11334 | Rn = inst.operands[1].reg; | |
11335 | ||
539d4391 NC |
11336 | /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this |
11337 | is the SP-{plus,minus}-immediate form of the instruction. */ | |
11338 | if (Rn == REG_SP) | |
11339 | constraint (Rd == REG_PC, BAD_PC); | |
11340 | else | |
11341 | reject_bad_reg (Rd); | |
fdfde340 | 11342 | |
92e90b6e | 11343 | inst.instruction |= (Rn << 16) | (Rd << 8); |
e2b0ab59 | 11344 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12; |
92e90b6e PB |
11345 | } |
11346 | ||
c19d1205 | 11347 | /* Parse an add or subtract instruction. We get here with inst.instruction |
33eaf5de | 11348 | equaling any of THUMB_OPCODE_add, adds, sub, or subs. */ |
c19d1205 ZW |
11349 | |
11350 | static void | |
11351 | do_t_add_sub (void) | |
11352 | { | |
11353 | int Rd, Rs, Rn; | |
11354 | ||
11355 | Rd = inst.operands[0].reg; | |
11356 | Rs = (inst.operands[1].present | |
11357 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
11358 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
11359 | ||
e07e6e58 | 11360 | if (Rd == REG_PC) |
5ee91343 | 11361 | set_pred_insn_type_last (); |
e07e6e58 | 11362 | |
c19d1205 ZW |
11363 | if (unified_syntax) |
11364 | { | |
0110f2b8 PB |
11365 | bfd_boolean flags; |
11366 | bfd_boolean narrow; | |
11367 | int opcode; | |
11368 | ||
11369 | flags = (inst.instruction == T_MNEM_adds | |
11370 | || inst.instruction == T_MNEM_subs); | |
11371 | if (flags) | |
5ee91343 | 11372 | narrow = !in_pred_block (); |
0110f2b8 | 11373 | else |
5ee91343 | 11374 | narrow = in_pred_block (); |
c19d1205 | 11375 | if (!inst.operands[2].isreg) |
b99bd4ef | 11376 | { |
16805f35 PB |
11377 | int add; |
11378 | ||
5c8ed6a4 JW |
11379 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
11380 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); | |
fdfde340 | 11381 | |
16805f35 PB |
11382 | add = (inst.instruction == T_MNEM_add |
11383 | || inst.instruction == T_MNEM_adds); | |
0110f2b8 PB |
11384 | opcode = 0; |
11385 | if (inst.size_req != 4) | |
11386 | { | |
0110f2b8 | 11387 | /* Attempt to use a narrow opcode, with relaxation if |
477330fc | 11388 | appropriate. */ |
0110f2b8 PB |
11389 | if (Rd == REG_SP && Rs == REG_SP && !flags) |
11390 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
11391 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
11392 | opcode = T_MNEM_add_sp; | |
11393 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
11394 | opcode = T_MNEM_add_pc; | |
11395 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
11396 | { | |
11397 | if (flags) | |
11398 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
11399 | else | |
11400 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
11401 | } | |
11402 | if (opcode) | |
11403 | { | |
11404 | inst.instruction = THUMB_OP16(opcode); | |
11405 | inst.instruction |= (Rd << 4) | Rs; | |
e2b0ab59 AV |
11406 | if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC |
11407 | || (inst.relocs[0].type | |
11408 | > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)) | |
a9f02af8 MG |
11409 | { |
11410 | if (inst.size_req == 2) | |
e2b0ab59 | 11411 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD; |
a9f02af8 MG |
11412 | else |
11413 | inst.relax = opcode; | |
11414 | } | |
0110f2b8 PB |
11415 | } |
11416 | else | |
11417 | constraint (inst.size_req == 2, BAD_HIREG); | |
11418 | } | |
11419 | if (inst.size_req == 4 | |
11420 | || (inst.size_req != 2 && !opcode)) | |
11421 | { | |
e2b0ab59 AV |
11422 | constraint ((inst.relocs[0].type |
11423 | >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC) | |
11424 | && (inst.relocs[0].type | |
11425 | <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) , | |
a9f02af8 | 11426 | THUMB1_RELOC_ONLY); |
efd81785 PB |
11427 | if (Rd == REG_PC) |
11428 | { | |
fdfde340 | 11429 | constraint (add, BAD_PC); |
efd81785 PB |
11430 | constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, |
11431 | _("only SUBS PC, LR, #const allowed")); | |
e2b0ab59 | 11432 | constraint (inst.relocs[0].exp.X_op != O_constant, |
efd81785 | 11433 | _("expression too complex")); |
e2b0ab59 AV |
11434 | constraint (inst.relocs[0].exp.X_add_number < 0 |
11435 | || inst.relocs[0].exp.X_add_number > 0xff, | |
efd81785 PB |
11436 | _("immediate value out of range")); |
11437 | inst.instruction = T2_SUBS_PC_LR | |
e2b0ab59 AV |
11438 | | inst.relocs[0].exp.X_add_number; |
11439 | inst.relocs[0].type = BFD_RELOC_UNUSED; | |
efd81785 PB |
11440 | return; |
11441 | } | |
11442 | else if (Rs == REG_PC) | |
16805f35 PB |
11443 | { |
11444 | /* Always use addw/subw. */ | |
11445 | inst.instruction = add ? 0xf20f0000 : 0xf2af0000; | |
e2b0ab59 | 11446 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12; |
16805f35 PB |
11447 | } |
11448 | else | |
11449 | { | |
11450 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11451 | inst.instruction = (inst.instruction & 0xe1ffffff) | |
11452 | | 0x10000000; | |
11453 | if (flags) | |
e2b0ab59 | 11454 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
16805f35 | 11455 | else |
e2b0ab59 | 11456 | inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_IMM; |
16805f35 | 11457 | } |
dc4503c6 PB |
11458 | inst.instruction |= Rd << 8; |
11459 | inst.instruction |= Rs << 16; | |
0110f2b8 | 11460 | } |
b99bd4ef | 11461 | } |
c19d1205 ZW |
11462 | else |
11463 | { | |
e2b0ab59 | 11464 | unsigned int value = inst.relocs[0].exp.X_add_number; |
5f4cb198 NC |
11465 | unsigned int shift = inst.operands[2].shift_kind; |
11466 | ||
c19d1205 ZW |
11467 | Rn = inst.operands[2].reg; |
11468 | /* See if we can do this with a 16-bit instruction. */ | |
11469 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
11470 | { | |
e27ec89e PB |
11471 | if (Rd > 7 || Rs > 7 || Rn > 7) |
11472 | narrow = FALSE; | |
11473 | ||
11474 | if (narrow) | |
c19d1205 | 11475 | { |
e27ec89e PB |
11476 | inst.instruction = ((inst.instruction == T_MNEM_adds |
11477 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
11478 | ? T_OPCODE_ADD_R3 |
11479 | : T_OPCODE_SUB_R3); | |
11480 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
11481 | return; | |
11482 | } | |
b99bd4ef | 11483 | |
7e806470 | 11484 | if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) |
c19d1205 | 11485 | { |
7e806470 PB |
11486 | /* Thumb-1 cores (except v6-M) require at least one high |
11487 | register in a narrow non flag setting add. */ | |
11488 | if (Rd > 7 || Rn > 7 | |
11489 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2) | |
11490 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr)) | |
c19d1205 | 11491 | { |
7e806470 PB |
11492 | if (Rd == Rn) |
11493 | { | |
11494 | Rn = Rs; | |
11495 | Rs = Rd; | |
11496 | } | |
c19d1205 ZW |
11497 | inst.instruction = T_OPCODE_ADD_HI; |
11498 | inst.instruction |= (Rd & 8) << 4; | |
11499 | inst.instruction |= (Rd & 7); | |
11500 | inst.instruction |= Rn << 3; | |
11501 | return; | |
11502 | } | |
c19d1205 ZW |
11503 | } |
11504 | } | |
c921be7d | 11505 | |
fdfde340 | 11506 | constraint (Rd == REG_PC, BAD_PC); |
5c8ed6a4 JW |
11507 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
11508 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); | |
fdfde340 JM |
11509 | constraint (Rs == REG_PC, BAD_PC); |
11510 | reject_bad_reg (Rn); | |
11511 | ||
c19d1205 ZW |
11512 | /* If we get here, it can't be done in 16 bits. */ |
11513 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
11514 | _("shift must be constant")); | |
11515 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11516 | inst.instruction |= Rd << 8; | |
11517 | inst.instruction |= Rs << 16; | |
5f4cb198 NC |
11518 | constraint (Rd == REG_SP && Rs == REG_SP && value > 3, |
11519 | _("shift value over 3 not allowed in thumb mode")); | |
11520 | constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL, | |
11521 | _("only LSL shift allowed in thumb mode")); | |
c19d1205 ZW |
11522 | encode_thumb32_shifted_operand (2); |
11523 | } | |
11524 | } | |
11525 | else | |
11526 | { | |
11527 | constraint (inst.instruction == T_MNEM_adds | |
11528 | || inst.instruction == T_MNEM_subs, | |
11529 | BAD_THUMB32); | |
b99bd4ef | 11530 | |
c19d1205 | 11531 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 11532 | { |
c19d1205 ZW |
11533 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
11534 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
11535 | BAD_HIREG); | |
11536 | ||
11537 | inst.instruction = (inst.instruction == T_MNEM_add | |
11538 | ? 0x0000 : 0x8000); | |
11539 | inst.instruction |= (Rd << 4) | Rs; | |
e2b0ab59 | 11540 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD; |
b99bd4ef NC |
11541 | return; |
11542 | } | |
11543 | ||
c19d1205 ZW |
11544 | Rn = inst.operands[2].reg; |
11545 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 11546 | |
c19d1205 ZW |
11547 | /* We now have Rd, Rs, and Rn set to registers. */ |
11548 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 11549 | { |
c19d1205 ZW |
11550 | /* Can't do this for SUB. */ |
11551 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
11552 | inst.instruction = T_OPCODE_ADD_HI; | |
11553 | inst.instruction |= (Rd & 8) << 4; | |
11554 | inst.instruction |= (Rd & 7); | |
11555 | if (Rs == Rd) | |
11556 | inst.instruction |= Rn << 3; | |
11557 | else if (Rn == Rd) | |
11558 | inst.instruction |= Rs << 3; | |
11559 | else | |
11560 | constraint (1, _("dest must overlap one source register")); | |
11561 | } | |
11562 | else | |
11563 | { | |
11564 | inst.instruction = (inst.instruction == T_MNEM_add | |
11565 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
11566 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 11567 | } |
b99bd4ef | 11568 | } |
b99bd4ef NC |
11569 | } |
11570 | ||
c19d1205 ZW |
11571 | static void |
11572 | do_t_adr (void) | |
11573 | { | |
fdfde340 JM |
11574 | unsigned Rd; |
11575 | ||
11576 | Rd = inst.operands[0].reg; | |
11577 | reject_bad_reg (Rd); | |
11578 | ||
11579 | if (unified_syntax && inst.size_req == 0 && Rd <= 7) | |
0110f2b8 PB |
11580 | { |
11581 | /* Defer to section relaxation. */ | |
11582 | inst.relax = inst.instruction; | |
11583 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 | 11584 | inst.instruction |= Rd << 4; |
0110f2b8 PB |
11585 | } |
11586 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 11587 | { |
0110f2b8 | 11588 | /* Generate a 32-bit opcode. */ |
e9f89963 | 11589 | inst.instruction = THUMB_OP32 (inst.instruction); |
fdfde340 | 11590 | inst.instruction |= Rd << 8; |
e2b0ab59 AV |
11591 | inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_PC12; |
11592 | inst.relocs[0].pc_rel = 1; | |
e9f89963 PB |
11593 | } |
11594 | else | |
11595 | { | |
0110f2b8 | 11596 | /* Generate a 16-bit opcode. */ |
e9f89963 | 11597 | inst.instruction = THUMB_OP16 (inst.instruction); |
e2b0ab59 AV |
11598 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD; |
11599 | inst.relocs[0].exp.X_add_number -= 4; /* PC relative adjust. */ | |
11600 | inst.relocs[0].pc_rel = 1; | |
fdfde340 | 11601 | inst.instruction |= Rd << 4; |
e9f89963 | 11602 | } |
52a86f84 | 11603 | |
e2b0ab59 AV |
11604 | if (inst.relocs[0].exp.X_op == O_symbol |
11605 | && inst.relocs[0].exp.X_add_symbol != NULL | |
11606 | && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol) | |
11607 | && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol)) | |
11608 | inst.relocs[0].exp.X_add_number += 1; | |
c19d1205 | 11609 | } |
b99bd4ef | 11610 | |
c19d1205 ZW |
11611 | /* Arithmetic instructions for which there is just one 16-bit |
11612 | instruction encoding, and it allows only two low registers. | |
11613 | For maximal compatibility with ARM syntax, we allow three register | |
11614 | operands even when Thumb-32 instructions are not available, as long | |
11615 | as the first two are identical. For instance, both "sbc r0,r1" and | |
11616 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 11617 | static void |
c19d1205 | 11618 | do_t_arit3 (void) |
b99bd4ef | 11619 | { |
c19d1205 | 11620 | int Rd, Rs, Rn; |
b99bd4ef | 11621 | |
c19d1205 ZW |
11622 | Rd = inst.operands[0].reg; |
11623 | Rs = (inst.operands[1].present | |
11624 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
11625 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
11626 | Rn = inst.operands[2].reg; | |
b99bd4ef | 11627 | |
fdfde340 JM |
11628 | reject_bad_reg (Rd); |
11629 | reject_bad_reg (Rs); | |
11630 | if (inst.operands[2].isreg) | |
11631 | reject_bad_reg (Rn); | |
11632 | ||
c19d1205 | 11633 | if (unified_syntax) |
b99bd4ef | 11634 | { |
c19d1205 ZW |
11635 | if (!inst.operands[2].isreg) |
11636 | { | |
11637 | /* For an immediate, we always generate a 32-bit opcode; | |
11638 | section relaxation will shrink it later if possible. */ | |
11639 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11640 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
11641 | inst.instruction |= Rd << 8; | |
11642 | inst.instruction |= Rs << 16; | |
e2b0ab59 | 11643 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
c19d1205 ZW |
11644 | } |
11645 | else | |
11646 | { | |
e27ec89e PB |
11647 | bfd_boolean narrow; |
11648 | ||
c19d1205 | 11649 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 11650 | if (THUMB_SETS_FLAGS (inst.instruction)) |
5ee91343 | 11651 | narrow = !in_pred_block (); |
e27ec89e | 11652 | else |
5ee91343 | 11653 | narrow = in_pred_block (); |
e27ec89e PB |
11654 | |
11655 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
11656 | narrow = FALSE; | |
11657 | if (inst.operands[2].shifted) | |
11658 | narrow = FALSE; | |
11659 | if (inst.size_req == 4) | |
11660 | narrow = FALSE; | |
11661 | ||
11662 | if (narrow | |
c19d1205 ZW |
11663 | && Rd == Rs) |
11664 | { | |
11665 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11666 | inst.instruction |= Rd; | |
11667 | inst.instruction |= Rn << 3; | |
11668 | return; | |
11669 | } | |
b99bd4ef | 11670 | |
c19d1205 ZW |
11671 | /* If we get here, it can't be done in 16 bits. */ |
11672 | constraint (inst.operands[2].shifted | |
11673 | && inst.operands[2].immisreg, | |
11674 | _("shift must be constant")); | |
11675 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11676 | inst.instruction |= Rd << 8; | |
11677 | inst.instruction |= Rs << 16; | |
11678 | encode_thumb32_shifted_operand (2); | |
11679 | } | |
a737bd4d | 11680 | } |
c19d1205 | 11681 | else |
b99bd4ef | 11682 | { |
c19d1205 ZW |
11683 | /* On its face this is a lie - the instruction does set the |
11684 | flags. However, the only supported mnemonic in this mode | |
11685 | says it doesn't. */ | |
11686 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 11687 | |
c19d1205 ZW |
11688 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
11689 | _("unshifted register required")); | |
11690 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
11691 | constraint (Rd != Rs, | |
11692 | _("dest and source1 must be the same register")); | |
a737bd4d | 11693 | |
c19d1205 ZW |
11694 | inst.instruction = THUMB_OP16 (inst.instruction); |
11695 | inst.instruction |= Rd; | |
11696 | inst.instruction |= Rn << 3; | |
b99bd4ef | 11697 | } |
a737bd4d | 11698 | } |
b99bd4ef | 11699 | |
c19d1205 ZW |
11700 | /* Similarly, but for instructions where the arithmetic operation is |
11701 | commutative, so we can allow either of them to be different from | |
11702 | the destination operand in a 16-bit instruction. For instance, all | |
11703 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
11704 | accepted. */ | |
11705 | static void | |
11706 | do_t_arit3c (void) | |
a737bd4d | 11707 | { |
c19d1205 | 11708 | int Rd, Rs, Rn; |
b99bd4ef | 11709 | |
c19d1205 ZW |
11710 | Rd = inst.operands[0].reg; |
11711 | Rs = (inst.operands[1].present | |
11712 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
11713 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
11714 | Rn = inst.operands[2].reg; | |
c921be7d | 11715 | |
fdfde340 JM |
11716 | reject_bad_reg (Rd); |
11717 | reject_bad_reg (Rs); | |
11718 | if (inst.operands[2].isreg) | |
11719 | reject_bad_reg (Rn); | |
a737bd4d | 11720 | |
c19d1205 | 11721 | if (unified_syntax) |
a737bd4d | 11722 | { |
c19d1205 | 11723 | if (!inst.operands[2].isreg) |
b99bd4ef | 11724 | { |
c19d1205 ZW |
11725 | /* For an immediate, we always generate a 32-bit opcode; |
11726 | section relaxation will shrink it later if possible. */ | |
11727 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11728 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
11729 | inst.instruction |= Rd << 8; | |
11730 | inst.instruction |= Rs << 16; | |
e2b0ab59 | 11731 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
b99bd4ef | 11732 | } |
c19d1205 | 11733 | else |
a737bd4d | 11734 | { |
e27ec89e PB |
11735 | bfd_boolean narrow; |
11736 | ||
c19d1205 | 11737 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 11738 | if (THUMB_SETS_FLAGS (inst.instruction)) |
5ee91343 | 11739 | narrow = !in_pred_block (); |
e27ec89e | 11740 | else |
5ee91343 | 11741 | narrow = in_pred_block (); |
e27ec89e PB |
11742 | |
11743 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
11744 | narrow = FALSE; | |
11745 | if (inst.operands[2].shifted) | |
11746 | narrow = FALSE; | |
11747 | if (inst.size_req == 4) | |
11748 | narrow = FALSE; | |
11749 | ||
11750 | if (narrow) | |
a737bd4d | 11751 | { |
c19d1205 | 11752 | if (Rd == Rs) |
a737bd4d | 11753 | { |
c19d1205 ZW |
11754 | inst.instruction = THUMB_OP16 (inst.instruction); |
11755 | inst.instruction |= Rd; | |
11756 | inst.instruction |= Rn << 3; | |
11757 | return; | |
a737bd4d | 11758 | } |
c19d1205 | 11759 | if (Rd == Rn) |
a737bd4d | 11760 | { |
c19d1205 ZW |
11761 | inst.instruction = THUMB_OP16 (inst.instruction); |
11762 | inst.instruction |= Rd; | |
11763 | inst.instruction |= Rs << 3; | |
11764 | return; | |
a737bd4d NC |
11765 | } |
11766 | } | |
c19d1205 ZW |
11767 | |
11768 | /* If we get here, it can't be done in 16 bits. */ | |
11769 | constraint (inst.operands[2].shifted | |
11770 | && inst.operands[2].immisreg, | |
11771 | _("shift must be constant")); | |
11772 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11773 | inst.instruction |= Rd << 8; | |
11774 | inst.instruction |= Rs << 16; | |
11775 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 11776 | } |
b99bd4ef | 11777 | } |
c19d1205 ZW |
11778 | else |
11779 | { | |
11780 | /* On its face this is a lie - the instruction does set the | |
11781 | flags. However, the only supported mnemonic in this mode | |
11782 | says it doesn't. */ | |
11783 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 11784 | |
c19d1205 ZW |
11785 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
11786 | _("unshifted register required")); | |
11787 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
11788 | ||
11789 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11790 | inst.instruction |= Rd; | |
11791 | ||
11792 | if (Rd == Rs) | |
11793 | inst.instruction |= Rn << 3; | |
11794 | else if (Rd == Rn) | |
11795 | inst.instruction |= Rs << 3; | |
11796 | else | |
11797 | constraint (1, _("dest must overlap one source register")); | |
11798 | } | |
a737bd4d NC |
11799 | } |
11800 | ||
c19d1205 ZW |
11801 | static void |
11802 | do_t_bfc (void) | |
a737bd4d | 11803 | { |
fdfde340 | 11804 | unsigned Rd; |
c19d1205 ZW |
11805 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
11806 | constraint (msb > 32, _("bit-field extends past end of register")); | |
11807 | /* The instruction encoding stores the LSB and MSB, | |
11808 | not the LSB and width. */ | |
fdfde340 JM |
11809 | Rd = inst.operands[0].reg; |
11810 | reject_bad_reg (Rd); | |
11811 | inst.instruction |= Rd << 8; | |
c19d1205 ZW |
11812 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; |
11813 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
11814 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
11815 | } |
11816 | ||
c19d1205 ZW |
11817 | static void |
11818 | do_t_bfi (void) | |
b99bd4ef | 11819 | { |
fdfde340 | 11820 | int Rd, Rn; |
c19d1205 | 11821 | unsigned int msb; |
b99bd4ef | 11822 | |
fdfde340 JM |
11823 | Rd = inst.operands[0].reg; |
11824 | reject_bad_reg (Rd); | |
11825 | ||
c19d1205 ZW |
11826 | /* #0 in second position is alternative syntax for bfc, which is |
11827 | the same instruction but with REG_PC in the Rm field. */ | |
11828 | if (!inst.operands[1].isreg) | |
fdfde340 JM |
11829 | Rn = REG_PC; |
11830 | else | |
11831 | { | |
11832 | Rn = inst.operands[1].reg; | |
11833 | reject_bad_reg (Rn); | |
11834 | } | |
b99bd4ef | 11835 | |
c19d1205 ZW |
11836 | msb = inst.operands[2].imm + inst.operands[3].imm; |
11837 | constraint (msb > 32, _("bit-field extends past end of register")); | |
11838 | /* The instruction encoding stores the LSB and MSB, | |
11839 | not the LSB and width. */ | |
fdfde340 JM |
11840 | inst.instruction |= Rd << 8; |
11841 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
11842 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
11843 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
11844 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
11845 | } |
11846 | ||
c19d1205 ZW |
11847 | static void |
11848 | do_t_bfx (void) | |
b99bd4ef | 11849 | { |
fdfde340 JM |
11850 | unsigned Rd, Rn; |
11851 | ||
11852 | Rd = inst.operands[0].reg; | |
11853 | Rn = inst.operands[1].reg; | |
11854 | ||
11855 | reject_bad_reg (Rd); | |
11856 | reject_bad_reg (Rn); | |
11857 | ||
c19d1205 ZW |
11858 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
11859 | _("bit-field extends past end of register")); | |
fdfde340 JM |
11860 | inst.instruction |= Rd << 8; |
11861 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
11862 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
11863 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
11864 | inst.instruction |= inst.operands[3].imm - 1; | |
11865 | } | |
b99bd4ef | 11866 | |
c19d1205 ZW |
11867 | /* ARM V5 Thumb BLX (argument parse) |
11868 | BLX <target_addr> which is BLX(1) | |
11869 | BLX <Rm> which is BLX(2) | |
11870 | Unfortunately, there are two different opcodes for this mnemonic. | |
11871 | So, the insns[].value is not used, and the code here zaps values | |
11872 | into inst.instruction. | |
b99bd4ef | 11873 | |
c19d1205 ZW |
11874 | ??? How to take advantage of the additional two bits of displacement |
11875 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 11876 | |
c19d1205 ZW |
11877 | static void |
11878 | do_t_blx (void) | |
11879 | { | |
5ee91343 | 11880 | set_pred_insn_type_last (); |
e07e6e58 | 11881 | |
c19d1205 | 11882 | if (inst.operands[0].isreg) |
fdfde340 JM |
11883 | { |
11884 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); | |
11885 | /* We have a register, so this is BLX(2). */ | |
11886 | inst.instruction |= inst.operands[0].reg << 3; | |
11887 | } | |
b99bd4ef NC |
11888 | else |
11889 | { | |
c19d1205 | 11890 | /* No register. This must be BLX(1). */ |
2fc8bdac | 11891 | inst.instruction = 0xf000e800; |
0855e32b | 11892 | encode_branch (BFD_RELOC_THUMB_PCREL_BLX); |
b99bd4ef NC |
11893 | } |
11894 | } | |
11895 | ||
c19d1205 ZW |
11896 | static void |
11897 | do_t_branch (void) | |
b99bd4ef | 11898 | { |
0110f2b8 | 11899 | int opcode; |
dfa9f0d5 | 11900 | int cond; |
2fe88214 | 11901 | bfd_reloc_code_real_type reloc; |
dfa9f0d5 | 11902 | |
e07e6e58 | 11903 | cond = inst.cond; |
5ee91343 | 11904 | set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); |
e07e6e58 | 11905 | |
5ee91343 | 11906 | if (in_pred_block ()) |
dfa9f0d5 PB |
11907 | { |
11908 | /* Conditional branches inside IT blocks are encoded as unconditional | |
477330fc | 11909 | branches. */ |
dfa9f0d5 | 11910 | cond = COND_ALWAYS; |
dfa9f0d5 PB |
11911 | } |
11912 | else | |
11913 | cond = inst.cond; | |
11914 | ||
11915 | if (cond != COND_ALWAYS) | |
0110f2b8 PB |
11916 | opcode = T_MNEM_bcond; |
11917 | else | |
11918 | opcode = inst.instruction; | |
11919 | ||
12d6b0b7 RS |
11920 | if (unified_syntax |
11921 | && (inst.size_req == 4 | |
10960bfb PB |
11922 | || (inst.size_req != 2 |
11923 | && (inst.operands[0].hasreloc | |
e2b0ab59 | 11924 | || inst.relocs[0].exp.X_op == O_constant)))) |
c19d1205 | 11925 | { |
0110f2b8 | 11926 | inst.instruction = THUMB_OP32(opcode); |
dfa9f0d5 | 11927 | if (cond == COND_ALWAYS) |
9ae92b05 | 11928 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
11929 | else |
11930 | { | |
ff8646ee TP |
11931 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2), |
11932 | _("selected architecture does not support " | |
11933 | "wide conditional branch instruction")); | |
11934 | ||
9c2799c2 | 11935 | gas_assert (cond != 0xF); |
dfa9f0d5 | 11936 | inst.instruction |= cond << 22; |
9ae92b05 | 11937 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH20; |
c19d1205 ZW |
11938 | } |
11939 | } | |
b99bd4ef NC |
11940 | else |
11941 | { | |
0110f2b8 | 11942 | inst.instruction = THUMB_OP16(opcode); |
dfa9f0d5 | 11943 | if (cond == COND_ALWAYS) |
9ae92b05 | 11944 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH12; |
c19d1205 | 11945 | else |
b99bd4ef | 11946 | { |
dfa9f0d5 | 11947 | inst.instruction |= cond << 8; |
9ae92b05 | 11948 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 11949 | } |
0110f2b8 PB |
11950 | /* Allow section relaxation. */ |
11951 | if (unified_syntax && inst.size_req != 2) | |
11952 | inst.relax = opcode; | |
b99bd4ef | 11953 | } |
e2b0ab59 AV |
11954 | inst.relocs[0].type = reloc; |
11955 | inst.relocs[0].pc_rel = 1; | |
b99bd4ef NC |
11956 | } |
11957 | ||
8884b720 | 11958 | /* Actually do the work for Thumb state bkpt and hlt. The only difference |
bacebabc | 11959 | between the two is the maximum immediate allowed - which is passed in |
8884b720 | 11960 | RANGE. */ |
b99bd4ef | 11961 | static void |
8884b720 | 11962 | do_t_bkpt_hlt1 (int range) |
b99bd4ef | 11963 | { |
dfa9f0d5 PB |
11964 | constraint (inst.cond != COND_ALWAYS, |
11965 | _("instruction is always unconditional")); | |
c19d1205 | 11966 | if (inst.operands[0].present) |
b99bd4ef | 11967 | { |
8884b720 | 11968 | constraint (inst.operands[0].imm > range, |
c19d1205 ZW |
11969 | _("immediate value out of range")); |
11970 | inst.instruction |= inst.operands[0].imm; | |
b99bd4ef | 11971 | } |
8884b720 | 11972 | |
5ee91343 | 11973 | set_pred_insn_type (NEUTRAL_IT_INSN); |
8884b720 MGD |
11974 | } |
11975 | ||
11976 | static void | |
11977 | do_t_hlt (void) | |
11978 | { | |
11979 | do_t_bkpt_hlt1 (63); | |
11980 | } | |
11981 | ||
11982 | static void | |
11983 | do_t_bkpt (void) | |
11984 | { | |
11985 | do_t_bkpt_hlt1 (255); | |
b99bd4ef NC |
11986 | } |
11987 | ||
11988 | static void | |
c19d1205 | 11989 | do_t_branch23 (void) |
b99bd4ef | 11990 | { |
5ee91343 | 11991 | set_pred_insn_type_last (); |
0855e32b | 11992 | encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23); |
fa94de6b | 11993 | |
0855e32b NS |
11994 | /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in |
11995 | this file. We used to simply ignore the PLT reloc type here -- | |
11996 | the branch encoding is now needed to deal with TLSCALL relocs. | |
11997 | So if we see a PLT reloc now, put it back to how it used to be to | |
11998 | keep the preexisting behaviour. */ | |
e2b0ab59 AV |
11999 | if (inst.relocs[0].type == BFD_RELOC_ARM_PLT32) |
12000 | inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
90e4755a | 12001 | |
4343666d | 12002 | #if defined(OBJ_COFF) |
c19d1205 ZW |
12003 | /* If the destination of the branch is a defined symbol which does not have |
12004 | the THUMB_FUNC attribute, then we must be calling a function which has | |
12005 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
12006 | function and change the branch to refer to that function instead. */ | |
e2b0ab59 AV |
12007 | if ( inst.relocs[0].exp.X_op == O_symbol |
12008 | && inst.relocs[0].exp.X_add_symbol != NULL | |
12009 | && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol) | |
12010 | && ! THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol)) | |
12011 | inst.relocs[0].exp.X_add_symbol | |
12012 | = find_real_start (inst.relocs[0].exp.X_add_symbol); | |
4343666d | 12013 | #endif |
90e4755a RE |
12014 | } |
12015 | ||
12016 | static void | |
c19d1205 | 12017 | do_t_bx (void) |
90e4755a | 12018 | { |
5ee91343 | 12019 | set_pred_insn_type_last (); |
c19d1205 ZW |
12020 | inst.instruction |= inst.operands[0].reg << 3; |
12021 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
12022 | should cause the alignment to be checked once it is known. This is | |
12023 | because BX PC only works if the instruction is word aligned. */ | |
12024 | } | |
90e4755a | 12025 | |
c19d1205 ZW |
12026 | static void |
12027 | do_t_bxj (void) | |
12028 | { | |
fdfde340 | 12029 | int Rm; |
90e4755a | 12030 | |
5ee91343 | 12031 | set_pred_insn_type_last (); |
fdfde340 JM |
12032 | Rm = inst.operands[0].reg; |
12033 | reject_bad_reg (Rm); | |
12034 | inst.instruction |= Rm << 16; | |
90e4755a RE |
12035 | } |
12036 | ||
12037 | static void | |
c19d1205 | 12038 | do_t_clz (void) |
90e4755a | 12039 | { |
fdfde340 JM |
12040 | unsigned Rd; |
12041 | unsigned Rm; | |
12042 | ||
12043 | Rd = inst.operands[0].reg; | |
12044 | Rm = inst.operands[1].reg; | |
12045 | ||
12046 | reject_bad_reg (Rd); | |
12047 | reject_bad_reg (Rm); | |
12048 | ||
12049 | inst.instruction |= Rd << 8; | |
12050 | inst.instruction |= Rm << 16; | |
12051 | inst.instruction |= Rm; | |
c19d1205 | 12052 | } |
90e4755a | 12053 | |
e39c1607 SD |
12054 | /* For the Armv8.1-M conditional instructions. */ |
12055 | static void | |
12056 | do_t_cond (void) | |
12057 | { | |
12058 | unsigned Rd, Rn, Rm; | |
12059 | signed int cond; | |
12060 | ||
12061 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
12062 | ||
12063 | Rd = inst.operands[0].reg; | |
12064 | switch (inst.instruction) | |
12065 | { | |
12066 | case T_MNEM_csinc: | |
12067 | case T_MNEM_csinv: | |
12068 | case T_MNEM_csneg: | |
12069 | case T_MNEM_csel: | |
12070 | Rn = inst.operands[1].reg; | |
12071 | Rm = inst.operands[2].reg; | |
12072 | cond = inst.operands[3].imm; | |
12073 | constraint (Rn == REG_SP, BAD_SP); | |
12074 | constraint (Rm == REG_SP, BAD_SP); | |
12075 | break; | |
12076 | ||
12077 | case T_MNEM_cinc: | |
12078 | case T_MNEM_cinv: | |
12079 | case T_MNEM_cneg: | |
12080 | Rn = inst.operands[1].reg; | |
12081 | cond = inst.operands[2].imm; | |
12082 | /* Invert the last bit to invert the cond. */ | |
12083 | cond = TOGGLE_BIT (cond, 0); | |
12084 | constraint (Rn == REG_SP, BAD_SP); | |
12085 | Rm = Rn; | |
12086 | break; | |
12087 | ||
12088 | case T_MNEM_csetm: | |
12089 | case T_MNEM_cset: | |
12090 | cond = inst.operands[1].imm; | |
12091 | /* Invert the last bit to invert the cond. */ | |
12092 | cond = TOGGLE_BIT (cond, 0); | |
12093 | Rn = REG_PC; | |
12094 | Rm = REG_PC; | |
12095 | break; | |
12096 | ||
12097 | default: abort (); | |
12098 | } | |
12099 | ||
12100 | set_pred_insn_type (OUTSIDE_PRED_INSN); | |
12101 | inst.instruction = THUMB_OP32 (inst.instruction); | |
12102 | inst.instruction |= Rd << 8; | |
12103 | inst.instruction |= Rn << 16; | |
12104 | inst.instruction |= Rm; | |
12105 | inst.instruction |= cond << 4; | |
12106 | } | |
12107 | ||
91d8b670 JG |
12108 | static void |
12109 | do_t_csdb (void) | |
12110 | { | |
5ee91343 | 12111 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
91d8b670 JG |
12112 | } |
12113 | ||
dfa9f0d5 PB |
12114 | static void |
12115 | do_t_cps (void) | |
12116 | { | |
5ee91343 | 12117 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
dfa9f0d5 PB |
12118 | inst.instruction |= inst.operands[0].imm; |
12119 | } | |
12120 | ||
c19d1205 ZW |
12121 | static void |
12122 | do_t_cpsi (void) | |
12123 | { | |
5ee91343 | 12124 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
c19d1205 | 12125 | if (unified_syntax |
62b3e311 PB |
12126 | && (inst.operands[1].present || inst.size_req == 4) |
12127 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) | |
90e4755a | 12128 | { |
c19d1205 ZW |
12129 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
12130 | inst.instruction = 0xf3af8000; | |
12131 | inst.instruction |= imod << 9; | |
12132 | inst.instruction |= inst.operands[0].imm << 5; | |
12133 | if (inst.operands[1].present) | |
12134 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 12135 | } |
c19d1205 | 12136 | else |
90e4755a | 12137 | { |
62b3e311 PB |
12138 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) |
12139 | && (inst.operands[0].imm & 4), | |
12140 | _("selected processor does not support 'A' form " | |
12141 | "of this instruction")); | |
12142 | constraint (inst.operands[1].present || inst.size_req == 4, | |
c19d1205 ZW |
12143 | _("Thumb does not support the 2-argument " |
12144 | "form of this instruction")); | |
12145 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 12146 | } |
90e4755a RE |
12147 | } |
12148 | ||
c19d1205 ZW |
12149 | /* THUMB CPY instruction (argument parse). */ |
12150 | ||
90e4755a | 12151 | static void |
c19d1205 | 12152 | do_t_cpy (void) |
90e4755a | 12153 | { |
c19d1205 | 12154 | if (inst.size_req == 4) |
90e4755a | 12155 | { |
c19d1205 ZW |
12156 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
12157 | inst.instruction |= inst.operands[0].reg << 8; | |
12158 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 12159 | } |
c19d1205 | 12160 | else |
90e4755a | 12161 | { |
c19d1205 ZW |
12162 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
12163 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
12164 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 12165 | } |
90e4755a RE |
12166 | } |
12167 | ||
90e4755a | 12168 | static void |
25fe350b | 12169 | do_t_cbz (void) |
90e4755a | 12170 | { |
5ee91343 | 12171 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
c19d1205 ZW |
12172 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
12173 | inst.instruction |= inst.operands[0].reg; | |
e2b0ab59 AV |
12174 | inst.relocs[0].pc_rel = 1; |
12175 | inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
c19d1205 | 12176 | } |
90e4755a | 12177 | |
62b3e311 PB |
12178 | static void |
12179 | do_t_dbg (void) | |
12180 | { | |
12181 | inst.instruction |= inst.operands[0].imm; | |
12182 | } | |
12183 | ||
12184 | static void | |
12185 | do_t_div (void) | |
12186 | { | |
fdfde340 JM |
12187 | unsigned Rd, Rn, Rm; |
12188 | ||
12189 | Rd = inst.operands[0].reg; | |
12190 | Rn = (inst.operands[1].present | |
12191 | ? inst.operands[1].reg : Rd); | |
12192 | Rm = inst.operands[2].reg; | |
12193 | ||
12194 | reject_bad_reg (Rd); | |
12195 | reject_bad_reg (Rn); | |
12196 | reject_bad_reg (Rm); | |
12197 | ||
12198 | inst.instruction |= Rd << 8; | |
12199 | inst.instruction |= Rn << 16; | |
12200 | inst.instruction |= Rm; | |
62b3e311 PB |
12201 | } |
12202 | ||
c19d1205 ZW |
12203 | static void |
12204 | do_t_hint (void) | |
12205 | { | |
12206 | if (unified_syntax && inst.size_req == 4) | |
12207 | inst.instruction = THUMB_OP32 (inst.instruction); | |
12208 | else | |
12209 | inst.instruction = THUMB_OP16 (inst.instruction); | |
12210 | } | |
90e4755a | 12211 | |
c19d1205 ZW |
12212 | static void |
12213 | do_t_it (void) | |
12214 | { | |
12215 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e | 12216 | |
5ee91343 AV |
12217 | set_pred_insn_type (IT_INSN); |
12218 | now_pred.mask = (inst.instruction & 0xf) | 0x10; | |
12219 | now_pred.cc = cond; | |
12220 | now_pred.warn_deprecated = FALSE; | |
12221 | now_pred.type = SCALAR_PRED; | |
e27ec89e PB |
12222 | |
12223 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 12224 | if ((cond & 0x1) == 0x0) |
90e4755a | 12225 | { |
c19d1205 | 12226 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 12227 | |
c19d1205 | 12228 | if ((mask & 0x7) == 0) |
5a01bb1d MGD |
12229 | { |
12230 | /* No conversion needed. */ | |
5ee91343 | 12231 | now_pred.block_length = 1; |
5a01bb1d | 12232 | } |
c19d1205 | 12233 | else if ((mask & 0x3) == 0) |
5a01bb1d MGD |
12234 | { |
12235 | mask ^= 0x8; | |
5ee91343 | 12236 | now_pred.block_length = 2; |
5a01bb1d | 12237 | } |
e27ec89e | 12238 | else if ((mask & 0x1) == 0) |
5a01bb1d MGD |
12239 | { |
12240 | mask ^= 0xC; | |
5ee91343 | 12241 | now_pred.block_length = 3; |
5a01bb1d | 12242 | } |
c19d1205 | 12243 | else |
5a01bb1d MGD |
12244 | { |
12245 | mask ^= 0xE; | |
5ee91343 | 12246 | now_pred.block_length = 4; |
5a01bb1d | 12247 | } |
90e4755a | 12248 | |
e27ec89e PB |
12249 | inst.instruction &= 0xfff0; |
12250 | inst.instruction |= mask; | |
c19d1205 | 12251 | } |
90e4755a | 12252 | |
c19d1205 ZW |
12253 | inst.instruction |= cond << 4; |
12254 | } | |
90e4755a | 12255 | |
3c707909 PB |
12256 | /* Helper function used for both push/pop and ldm/stm. */ |
12257 | static void | |
4b5a202f AV |
12258 | encode_thumb2_multi (bfd_boolean do_io, int base, unsigned mask, |
12259 | bfd_boolean writeback) | |
3c707909 | 12260 | { |
4b5a202f | 12261 | bfd_boolean load, store; |
3c707909 | 12262 | |
4b5a202f AV |
12263 | gas_assert (base != -1 || !do_io); |
12264 | load = do_io && ((inst.instruction & (1 << 20)) != 0); | |
12265 | store = do_io && !load; | |
3c707909 PB |
12266 | |
12267 | if (mask & (1 << 13)) | |
12268 | inst.error = _("SP not allowed in register list"); | |
1e5b0379 | 12269 | |
4b5a202f | 12270 | if (do_io && (mask & (1 << base)) != 0 |
1e5b0379 NC |
12271 | && writeback) |
12272 | inst.error = _("having the base register in the register list when " | |
12273 | "using write back is UNPREDICTABLE"); | |
12274 | ||
3c707909 PB |
12275 | if (load) |
12276 | { | |
e07e6e58 | 12277 | if (mask & (1 << 15)) |
477330fc RM |
12278 | { |
12279 | if (mask & (1 << 14)) | |
12280 | inst.error = _("LR and PC should not both be in register list"); | |
12281 | else | |
5ee91343 | 12282 | set_pred_insn_type_last (); |
477330fc | 12283 | } |
3c707909 | 12284 | } |
4b5a202f | 12285 | else if (store) |
3c707909 PB |
12286 | { |
12287 | if (mask & (1 << 15)) | |
12288 | inst.error = _("PC not allowed in register list"); | |
3c707909 PB |
12289 | } |
12290 | ||
4b5a202f | 12291 | if (do_io && ((mask & (mask - 1)) == 0)) |
3c707909 PB |
12292 | { |
12293 | /* Single register transfers implemented as str/ldr. */ | |
12294 | if (writeback) | |
12295 | { | |
12296 | if (inst.instruction & (1 << 23)) | |
12297 | inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ | |
12298 | else | |
12299 | inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ | |
12300 | } | |
12301 | else | |
12302 | { | |
12303 | if (inst.instruction & (1 << 23)) | |
12304 | inst.instruction = 0x00800000; /* ia -> [base] */ | |
12305 | else | |
12306 | inst.instruction = 0x00000c04; /* db -> [base, #-4] */ | |
12307 | } | |
12308 | ||
12309 | inst.instruction |= 0xf8400000; | |
12310 | if (load) | |
12311 | inst.instruction |= 0x00100000; | |
12312 | ||
5f4273c7 | 12313 | mask = ffs (mask) - 1; |
3c707909 PB |
12314 | mask <<= 12; |
12315 | } | |
12316 | else if (writeback) | |
12317 | inst.instruction |= WRITE_BACK; | |
12318 | ||
12319 | inst.instruction |= mask; | |
4b5a202f AV |
12320 | if (do_io) |
12321 | inst.instruction |= base << 16; | |
3c707909 PB |
12322 | } |
12323 | ||
c19d1205 ZW |
12324 | static void |
12325 | do_t_ldmstm (void) | |
12326 | { | |
12327 | /* This really doesn't seem worth it. */ | |
e2b0ab59 | 12328 | constraint (inst.relocs[0].type != BFD_RELOC_UNUSED, |
c19d1205 ZW |
12329 | _("expression too complex")); |
12330 | constraint (inst.operands[1].writeback, | |
12331 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 12332 | |
c19d1205 ZW |
12333 | if (unified_syntax) |
12334 | { | |
3c707909 PB |
12335 | bfd_boolean narrow; |
12336 | unsigned mask; | |
12337 | ||
12338 | narrow = FALSE; | |
c19d1205 ZW |
12339 | /* See if we can use a 16-bit instruction. */ |
12340 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
12341 | && inst.size_req != 4 | |
3c707909 | 12342 | && !(inst.operands[1].imm & ~0xff)) |
90e4755a | 12343 | { |
3c707909 | 12344 | mask = 1 << inst.operands[0].reg; |
90e4755a | 12345 | |
eab4f823 | 12346 | if (inst.operands[0].reg <= 7) |
90e4755a | 12347 | { |
3c707909 | 12348 | if (inst.instruction == T_MNEM_stmia |
eab4f823 MGD |
12349 | ? inst.operands[0].writeback |
12350 | : (inst.operands[0].writeback | |
12351 | == !(inst.operands[1].imm & mask))) | |
477330fc | 12352 | { |
eab4f823 MGD |
12353 | if (inst.instruction == T_MNEM_stmia |
12354 | && (inst.operands[1].imm & mask) | |
12355 | && (inst.operands[1].imm & (mask - 1))) | |
12356 | as_warn (_("value stored for r%d is UNKNOWN"), | |
12357 | inst.operands[0].reg); | |
3c707909 | 12358 | |
eab4f823 MGD |
12359 | inst.instruction = THUMB_OP16 (inst.instruction); |
12360 | inst.instruction |= inst.operands[0].reg << 8; | |
12361 | inst.instruction |= inst.operands[1].imm; | |
12362 | narrow = TRUE; | |
12363 | } | |
12364 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
12365 | { | |
12366 | /* This means 1 register in reg list one of 3 situations: | |
12367 | 1. Instruction is stmia, but without writeback. | |
12368 | 2. lmdia without writeback, but with Rn not in | |
477330fc | 12369 | reglist. |
eab4f823 MGD |
12370 | 3. ldmia with writeback, but with Rn in reglist. |
12371 | Case 3 is UNPREDICTABLE behaviour, so we handle | |
12372 | case 1 and 2 which can be converted into a 16-bit | |
12373 | str or ldr. The SP cases are handled below. */ | |
12374 | unsigned long opcode; | |
12375 | /* First, record an error for Case 3. */ | |
12376 | if (inst.operands[1].imm & mask | |
12377 | && inst.operands[0].writeback) | |
fa94de6b | 12378 | inst.error = |
eab4f823 MGD |
12379 | _("having the base register in the register list when " |
12380 | "using write back is UNPREDICTABLE"); | |
fa94de6b RM |
12381 | |
12382 | opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str | |
eab4f823 MGD |
12383 | : T_MNEM_ldr); |
12384 | inst.instruction = THUMB_OP16 (opcode); | |
12385 | inst.instruction |= inst.operands[0].reg << 3; | |
12386 | inst.instruction |= (ffs (inst.operands[1].imm)-1); | |
12387 | narrow = TRUE; | |
12388 | } | |
90e4755a | 12389 | } |
eab4f823 | 12390 | else if (inst.operands[0] .reg == REG_SP) |
90e4755a | 12391 | { |
eab4f823 MGD |
12392 | if (inst.operands[0].writeback) |
12393 | { | |
fa94de6b | 12394 | inst.instruction = |
eab4f823 | 12395 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
477330fc | 12396 | ? T_MNEM_push : T_MNEM_pop); |
eab4f823 | 12397 | inst.instruction |= inst.operands[1].imm; |
477330fc | 12398 | narrow = TRUE; |
eab4f823 MGD |
12399 | } |
12400 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
12401 | { | |
fa94de6b | 12402 | inst.instruction = |
eab4f823 | 12403 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
477330fc | 12404 | ? T_MNEM_str_sp : T_MNEM_ldr_sp); |
eab4f823 | 12405 | inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8); |
477330fc | 12406 | narrow = TRUE; |
eab4f823 | 12407 | } |
90e4755a | 12408 | } |
3c707909 PB |
12409 | } |
12410 | ||
12411 | if (!narrow) | |
12412 | { | |
c19d1205 ZW |
12413 | if (inst.instruction < 0xffff) |
12414 | inst.instruction = THUMB_OP32 (inst.instruction); | |
3c707909 | 12415 | |
4b5a202f AV |
12416 | encode_thumb2_multi (TRUE /* do_io */, inst.operands[0].reg, |
12417 | inst.operands[1].imm, | |
12418 | inst.operands[0].writeback); | |
90e4755a RE |
12419 | } |
12420 | } | |
c19d1205 | 12421 | else |
90e4755a | 12422 | { |
c19d1205 ZW |
12423 | constraint (inst.operands[0].reg > 7 |
12424 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
1198ca51 PB |
12425 | constraint (inst.instruction != T_MNEM_ldmia |
12426 | && inst.instruction != T_MNEM_stmia, | |
12427 | _("Thumb-2 instruction only valid in unified syntax")); | |
c19d1205 | 12428 | if (inst.instruction == T_MNEM_stmia) |
f03698e6 | 12429 | { |
c19d1205 ZW |
12430 | if (!inst.operands[0].writeback) |
12431 | as_warn (_("this instruction will write back the base register")); | |
12432 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
12433 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
1e5b0379 | 12434 | as_warn (_("value stored for r%d is UNKNOWN"), |
c19d1205 | 12435 | inst.operands[0].reg); |
f03698e6 | 12436 | } |
c19d1205 | 12437 | else |
90e4755a | 12438 | { |
c19d1205 ZW |
12439 | if (!inst.operands[0].writeback |
12440 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
12441 | as_warn (_("this instruction will write back the base register")); | |
12442 | else if (inst.operands[0].writeback | |
12443 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
12444 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
12445 | } |
12446 | ||
c19d1205 ZW |
12447 | inst.instruction = THUMB_OP16 (inst.instruction); |
12448 | inst.instruction |= inst.operands[0].reg << 8; | |
12449 | inst.instruction |= inst.operands[1].imm; | |
12450 | } | |
12451 | } | |
e28cd48c | 12452 | |
c19d1205 ZW |
12453 | static void |
12454 | do_t_ldrex (void) | |
12455 | { | |
12456 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
12457 | || inst.operands[1].postind || inst.operands[1].writeback | |
12458 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
12459 | || inst.operands[1].negative, | |
01cfc07f | 12460 | BAD_ADDR_MODE); |
e28cd48c | 12461 | |
5be8be5d DG |
12462 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
12463 | ||
c19d1205 ZW |
12464 | inst.instruction |= inst.operands[0].reg << 12; |
12465 | inst.instruction |= inst.operands[1].reg << 16; | |
e2b0ab59 | 12466 | inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8; |
c19d1205 | 12467 | } |
e28cd48c | 12468 | |
c19d1205 ZW |
12469 | static void |
12470 | do_t_ldrexd (void) | |
12471 | { | |
12472 | if (!inst.operands[1].present) | |
1cac9012 | 12473 | { |
c19d1205 ZW |
12474 | constraint (inst.operands[0].reg == REG_LR, |
12475 | _("r14 not allowed as first register " | |
12476 | "when second register is omitted")); | |
12477 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 12478 | } |
c19d1205 ZW |
12479 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
12480 | BAD_OVERLAP); | |
b99bd4ef | 12481 | |
c19d1205 ZW |
12482 | inst.instruction |= inst.operands[0].reg << 12; |
12483 | inst.instruction |= inst.operands[1].reg << 8; | |
12484 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
12485 | } |
12486 | ||
12487 | static void | |
c19d1205 | 12488 | do_t_ldst (void) |
b99bd4ef | 12489 | { |
0110f2b8 PB |
12490 | unsigned long opcode; |
12491 | int Rn; | |
12492 | ||
e07e6e58 NC |
12493 | if (inst.operands[0].isreg |
12494 | && !inst.operands[0].preind | |
12495 | && inst.operands[0].reg == REG_PC) | |
5ee91343 | 12496 | set_pred_insn_type_last (); |
e07e6e58 | 12497 | |
0110f2b8 | 12498 | opcode = inst.instruction; |
c19d1205 | 12499 | if (unified_syntax) |
b99bd4ef | 12500 | { |
53365c0d PB |
12501 | if (!inst.operands[1].isreg) |
12502 | { | |
12503 | if (opcode <= 0xffff) | |
12504 | inst.instruction = THUMB_OP32 (opcode); | |
8335d6aa | 12505 | if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE)) |
53365c0d PB |
12506 | return; |
12507 | } | |
0110f2b8 PB |
12508 | if (inst.operands[1].isreg |
12509 | && !inst.operands[1].writeback | |
c19d1205 ZW |
12510 | && !inst.operands[1].shifted && !inst.operands[1].postind |
12511 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
12512 | && opcode <= 0xffff |
12513 | && inst.size_req != 4) | |
c19d1205 | 12514 | { |
0110f2b8 PB |
12515 | /* Insn may have a 16-bit form. */ |
12516 | Rn = inst.operands[1].reg; | |
12517 | if (inst.operands[1].immisreg) | |
12518 | { | |
12519 | inst.instruction = THUMB_OP16 (opcode); | |
5f4273c7 | 12520 | /* [Rn, Rik] */ |
0110f2b8 PB |
12521 | if (Rn <= 7 && inst.operands[1].imm <= 7) |
12522 | goto op16; | |
5be8be5d DG |
12523 | else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str) |
12524 | reject_bad_reg (inst.operands[1].imm); | |
0110f2b8 PB |
12525 | } |
12526 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
12527 | && opcode != T_MNEM_ldrsb) | |
12528 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
12529 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
12530 | { | |
12531 | /* [Rn, #const] */ | |
12532 | if (Rn > 7) | |
12533 | { | |
12534 | if (Rn == REG_PC) | |
12535 | { | |
e2b0ab59 | 12536 | if (inst.relocs[0].pc_rel) |
0110f2b8 PB |
12537 | opcode = T_MNEM_ldr_pc2; |
12538 | else | |
12539 | opcode = T_MNEM_ldr_pc; | |
12540 | } | |
12541 | else | |
12542 | { | |
12543 | if (opcode == T_MNEM_ldr) | |
12544 | opcode = T_MNEM_ldr_sp; | |
12545 | else | |
12546 | opcode = T_MNEM_str_sp; | |
12547 | } | |
12548 | inst.instruction = inst.operands[0].reg << 8; | |
12549 | } | |
12550 | else | |
12551 | { | |
12552 | inst.instruction = inst.operands[0].reg; | |
12553 | inst.instruction |= inst.operands[1].reg << 3; | |
12554 | } | |
12555 | inst.instruction |= THUMB_OP16 (opcode); | |
12556 | if (inst.size_req == 2) | |
e2b0ab59 | 12557 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET; |
0110f2b8 PB |
12558 | else |
12559 | inst.relax = opcode; | |
12560 | return; | |
12561 | } | |
c19d1205 | 12562 | } |
0110f2b8 | 12563 | /* Definitely a 32-bit variant. */ |
5be8be5d | 12564 | |
8d67f500 NC |
12565 | /* Warning for Erratum 752419. */ |
12566 | if (opcode == T_MNEM_ldr | |
12567 | && inst.operands[0].reg == REG_SP | |
12568 | && inst.operands[1].writeback == 1 | |
12569 | && !inst.operands[1].immisreg) | |
12570 | { | |
12571 | if (no_cpu_selected () | |
12572 | || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7) | |
477330fc RM |
12573 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a) |
12574 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r))) | |
8d67f500 NC |
12575 | as_warn (_("This instruction may be unpredictable " |
12576 | "if executed on M-profile cores " | |
12577 | "with interrupts enabled.")); | |
12578 | } | |
12579 | ||
5be8be5d | 12580 | /* Do some validations regarding addressing modes. */ |
1be5fd2e | 12581 | if (inst.operands[1].immisreg) |
5be8be5d DG |
12582 | reject_bad_reg (inst.operands[1].imm); |
12583 | ||
1be5fd2e NC |
12584 | constraint (inst.operands[1].writeback == 1 |
12585 | && inst.operands[0].reg == inst.operands[1].reg, | |
12586 | BAD_OVERLAP); | |
12587 | ||
0110f2b8 | 12588 | inst.instruction = THUMB_OP32 (opcode); |
c19d1205 ZW |
12589 | inst.instruction |= inst.operands[0].reg << 12; |
12590 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
1be5fd2e | 12591 | check_ldr_r15_aligned (); |
b99bd4ef NC |
12592 | return; |
12593 | } | |
12594 | ||
c19d1205 ZW |
12595 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
12596 | ||
12597 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 12598 | { |
c19d1205 ZW |
12599 | /* Only [Rn,Rm] is acceptable. */ |
12600 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
12601 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
12602 | || inst.operands[1].postind || inst.operands[1].shifted | |
12603 | || inst.operands[1].negative, | |
12604 | _("Thumb does not support this addressing mode")); | |
12605 | inst.instruction = THUMB_OP16 (inst.instruction); | |
12606 | goto op16; | |
b99bd4ef | 12607 | } |
5f4273c7 | 12608 | |
c19d1205 ZW |
12609 | inst.instruction = THUMB_OP16 (inst.instruction); |
12610 | if (!inst.operands[1].isreg) | |
8335d6aa | 12611 | if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE)) |
c19d1205 | 12612 | return; |
b99bd4ef | 12613 | |
c19d1205 ZW |
12614 | constraint (!inst.operands[1].preind |
12615 | || inst.operands[1].shifted | |
12616 | || inst.operands[1].writeback, | |
12617 | _("Thumb does not support this addressing mode")); | |
12618 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 12619 | { |
c19d1205 ZW |
12620 | constraint (inst.instruction & 0x0600, |
12621 | _("byte or halfword not valid for base register")); | |
12622 | constraint (inst.operands[1].reg == REG_PC | |
12623 | && !(inst.instruction & THUMB_LOAD_BIT), | |
12624 | _("r15 based store not allowed")); | |
12625 | constraint (inst.operands[1].immisreg, | |
12626 | _("invalid base register for register offset")); | |
b99bd4ef | 12627 | |
c19d1205 ZW |
12628 | if (inst.operands[1].reg == REG_PC) |
12629 | inst.instruction = T_OPCODE_LDR_PC; | |
12630 | else if (inst.instruction & THUMB_LOAD_BIT) | |
12631 | inst.instruction = T_OPCODE_LDR_SP; | |
12632 | else | |
12633 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 12634 | |
c19d1205 | 12635 | inst.instruction |= inst.operands[0].reg << 8; |
e2b0ab59 | 12636 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET; |
c19d1205 ZW |
12637 | return; |
12638 | } | |
90e4755a | 12639 | |
c19d1205 ZW |
12640 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
12641 | if (!inst.operands[1].immisreg) | |
12642 | { | |
12643 | /* Immediate offset. */ | |
12644 | inst.instruction |= inst.operands[0].reg; | |
12645 | inst.instruction |= inst.operands[1].reg << 3; | |
e2b0ab59 | 12646 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET; |
c19d1205 ZW |
12647 | return; |
12648 | } | |
90e4755a | 12649 | |
c19d1205 ZW |
12650 | /* Register offset. */ |
12651 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
12652 | constraint (inst.operands[1].negative, | |
12653 | _("Thumb does not support this addressing mode")); | |
90e4755a | 12654 | |
c19d1205 ZW |
12655 | op16: |
12656 | switch (inst.instruction) | |
12657 | { | |
12658 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
12659 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
12660 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
12661 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
12662 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
12663 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
12664 | case 0x5600 /* ldrsb */: | |
12665 | case 0x5e00 /* ldrsh */: break; | |
12666 | default: abort (); | |
12667 | } | |
90e4755a | 12668 | |
c19d1205 ZW |
12669 | inst.instruction |= inst.operands[0].reg; |
12670 | inst.instruction |= inst.operands[1].reg << 3; | |
12671 | inst.instruction |= inst.operands[1].imm << 6; | |
12672 | } | |
90e4755a | 12673 | |
c19d1205 ZW |
12674 | static void |
12675 | do_t_ldstd (void) | |
12676 | { | |
12677 | if (!inst.operands[1].present) | |
b99bd4ef | 12678 | { |
c19d1205 ZW |
12679 | inst.operands[1].reg = inst.operands[0].reg + 1; |
12680 | constraint (inst.operands[0].reg == REG_LR, | |
12681 | _("r14 not allowed here")); | |
bd340a04 | 12682 | constraint (inst.operands[0].reg == REG_R12, |
477330fc | 12683 | _("r12 not allowed here")); |
b99bd4ef | 12684 | } |
bd340a04 MGD |
12685 | |
12686 | if (inst.operands[2].writeback | |
12687 | && (inst.operands[0].reg == inst.operands[2].reg | |
12688 | || inst.operands[1].reg == inst.operands[2].reg)) | |
12689 | as_warn (_("base register written back, and overlaps " | |
477330fc | 12690 | "one of transfer registers")); |
bd340a04 | 12691 | |
c19d1205 ZW |
12692 | inst.instruction |= inst.operands[0].reg << 12; |
12693 | inst.instruction |= inst.operands[1].reg << 8; | |
12694 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
b99bd4ef NC |
12695 | } |
12696 | ||
c19d1205 ZW |
12697 | static void |
12698 | do_t_ldstt (void) | |
12699 | { | |
12700 | inst.instruction |= inst.operands[0].reg << 12; | |
12701 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
12702 | } | |
a737bd4d | 12703 | |
b99bd4ef | 12704 | static void |
c19d1205 | 12705 | do_t_mla (void) |
b99bd4ef | 12706 | { |
fdfde340 | 12707 | unsigned Rd, Rn, Rm, Ra; |
c921be7d | 12708 | |
fdfde340 JM |
12709 | Rd = inst.operands[0].reg; |
12710 | Rn = inst.operands[1].reg; | |
12711 | Rm = inst.operands[2].reg; | |
12712 | Ra = inst.operands[3].reg; | |
12713 | ||
12714 | reject_bad_reg (Rd); | |
12715 | reject_bad_reg (Rn); | |
12716 | reject_bad_reg (Rm); | |
12717 | reject_bad_reg (Ra); | |
12718 | ||
12719 | inst.instruction |= Rd << 8; | |
12720 | inst.instruction |= Rn << 16; | |
12721 | inst.instruction |= Rm; | |
12722 | inst.instruction |= Ra << 12; | |
c19d1205 | 12723 | } |
b99bd4ef | 12724 | |
c19d1205 ZW |
12725 | static void |
12726 | do_t_mlal (void) | |
12727 | { | |
fdfde340 JM |
12728 | unsigned RdLo, RdHi, Rn, Rm; |
12729 | ||
12730 | RdLo = inst.operands[0].reg; | |
12731 | RdHi = inst.operands[1].reg; | |
12732 | Rn = inst.operands[2].reg; | |
12733 | Rm = inst.operands[3].reg; | |
12734 | ||
12735 | reject_bad_reg (RdLo); | |
12736 | reject_bad_reg (RdHi); | |
12737 | reject_bad_reg (Rn); | |
12738 | reject_bad_reg (Rm); | |
12739 | ||
12740 | inst.instruction |= RdLo << 12; | |
12741 | inst.instruction |= RdHi << 8; | |
12742 | inst.instruction |= Rn << 16; | |
12743 | inst.instruction |= Rm; | |
c19d1205 | 12744 | } |
b99bd4ef | 12745 | |
c19d1205 ZW |
12746 | static void |
12747 | do_t_mov_cmp (void) | |
12748 | { | |
fdfde340 JM |
12749 | unsigned Rn, Rm; |
12750 | ||
12751 | Rn = inst.operands[0].reg; | |
12752 | Rm = inst.operands[1].reg; | |
12753 | ||
e07e6e58 | 12754 | if (Rn == REG_PC) |
5ee91343 | 12755 | set_pred_insn_type_last (); |
e07e6e58 | 12756 | |
c19d1205 | 12757 | if (unified_syntax) |
b99bd4ef | 12758 | { |
c19d1205 ZW |
12759 | int r0off = (inst.instruction == T_MNEM_mov |
12760 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 12761 | unsigned long opcode; |
3d388997 PB |
12762 | bfd_boolean narrow; |
12763 | bfd_boolean low_regs; | |
12764 | ||
fdfde340 | 12765 | low_regs = (Rn <= 7 && Rm <= 7); |
0110f2b8 | 12766 | opcode = inst.instruction; |
5ee91343 | 12767 | if (in_pred_block ()) |
0110f2b8 | 12768 | narrow = opcode != T_MNEM_movs; |
3d388997 | 12769 | else |
0110f2b8 | 12770 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
12771 | if (inst.size_req == 4 |
12772 | || inst.operands[1].shifted) | |
12773 | narrow = FALSE; | |
12774 | ||
efd81785 PB |
12775 | /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ |
12776 | if (opcode == T_MNEM_movs && inst.operands[1].isreg | |
12777 | && !inst.operands[1].shifted | |
fdfde340 JM |
12778 | && Rn == REG_PC |
12779 | && Rm == REG_LR) | |
efd81785 PB |
12780 | { |
12781 | inst.instruction = T2_SUBS_PC_LR; | |
12782 | return; | |
12783 | } | |
12784 | ||
fdfde340 JM |
12785 | if (opcode == T_MNEM_cmp) |
12786 | { | |
12787 | constraint (Rn == REG_PC, BAD_PC); | |
94206790 MM |
12788 | if (narrow) |
12789 | { | |
12790 | /* In the Thumb-2 ISA, use of R13 as Rm is deprecated, | |
12791 | but valid. */ | |
12792 | warn_deprecated_sp (Rm); | |
12793 | /* R15 was documented as a valid choice for Rm in ARMv6, | |
12794 | but as UNPREDICTABLE in ARMv7. ARM's proprietary | |
12795 | tools reject R15, so we do too. */ | |
12796 | constraint (Rm == REG_PC, BAD_PC); | |
12797 | } | |
12798 | else | |
12799 | reject_bad_reg (Rm); | |
fdfde340 JM |
12800 | } |
12801 | else if (opcode == T_MNEM_mov | |
12802 | || opcode == T_MNEM_movs) | |
12803 | { | |
12804 | if (inst.operands[1].isreg) | |
12805 | { | |
12806 | if (opcode == T_MNEM_movs) | |
12807 | { | |
12808 | reject_bad_reg (Rn); | |
12809 | reject_bad_reg (Rm); | |
12810 | } | |
76fa04a4 MGD |
12811 | else if (narrow) |
12812 | { | |
12813 | /* This is mov.n. */ | |
12814 | if ((Rn == REG_SP || Rn == REG_PC) | |
12815 | && (Rm == REG_SP || Rm == REG_PC)) | |
12816 | { | |
5c3696f8 | 12817 | as_tsktsk (_("Use of r%u as a source register is " |
76fa04a4 MGD |
12818 | "deprecated when r%u is the destination " |
12819 | "register."), Rm, Rn); | |
12820 | } | |
12821 | } | |
12822 | else | |
12823 | { | |
12824 | /* This is mov.w. */ | |
12825 | constraint (Rn == REG_PC, BAD_PC); | |
12826 | constraint (Rm == REG_PC, BAD_PC); | |
5c8ed6a4 JW |
12827 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
12828 | constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); | |
76fa04a4 | 12829 | } |
fdfde340 JM |
12830 | } |
12831 | else | |
12832 | reject_bad_reg (Rn); | |
12833 | } | |
12834 | ||
c19d1205 ZW |
12835 | if (!inst.operands[1].isreg) |
12836 | { | |
0110f2b8 | 12837 | /* Immediate operand. */ |
5ee91343 | 12838 | if (!in_pred_block () && opcode == T_MNEM_mov) |
0110f2b8 PB |
12839 | narrow = 0; |
12840 | if (low_regs && narrow) | |
12841 | { | |
12842 | inst.instruction = THUMB_OP16 (opcode); | |
fdfde340 | 12843 | inst.instruction |= Rn << 8; |
e2b0ab59 AV |
12844 | if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC |
12845 | || inst.relocs[0].type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) | |
72d98d16 | 12846 | { |
a9f02af8 | 12847 | if (inst.size_req == 2) |
e2b0ab59 | 12848 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM; |
a9f02af8 MG |
12849 | else |
12850 | inst.relax = opcode; | |
72d98d16 | 12851 | } |
0110f2b8 PB |
12852 | } |
12853 | else | |
12854 | { | |
e2b0ab59 AV |
12855 | constraint ((inst.relocs[0].type |
12856 | >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC) | |
12857 | && (inst.relocs[0].type | |
12858 | <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) , | |
a9f02af8 MG |
12859 | THUMB1_RELOC_ONLY); |
12860 | ||
0110f2b8 PB |
12861 | inst.instruction = THUMB_OP32 (inst.instruction); |
12862 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 12863 | inst.instruction |= Rn << r0off; |
e2b0ab59 | 12864 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
0110f2b8 | 12865 | } |
c19d1205 | 12866 | } |
728ca7c9 PB |
12867 | else if (inst.operands[1].shifted && inst.operands[1].immisreg |
12868 | && (inst.instruction == T_MNEM_mov | |
12869 | || inst.instruction == T_MNEM_movs)) | |
12870 | { | |
12871 | /* Register shifts are encoded as separate shift instructions. */ | |
12872 | bfd_boolean flags = (inst.instruction == T_MNEM_movs); | |
12873 | ||
5ee91343 | 12874 | if (in_pred_block ()) |
728ca7c9 PB |
12875 | narrow = !flags; |
12876 | else | |
12877 | narrow = flags; | |
12878 | ||
12879 | if (inst.size_req == 4) | |
12880 | narrow = FALSE; | |
12881 | ||
12882 | if (!low_regs || inst.operands[1].imm > 7) | |
12883 | narrow = FALSE; | |
12884 | ||
fdfde340 | 12885 | if (Rn != Rm) |
728ca7c9 PB |
12886 | narrow = FALSE; |
12887 | ||
12888 | switch (inst.operands[1].shift_kind) | |
12889 | { | |
12890 | case SHIFT_LSL: | |
12891 | opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); | |
12892 | break; | |
12893 | case SHIFT_ASR: | |
12894 | opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); | |
12895 | break; | |
12896 | case SHIFT_LSR: | |
12897 | opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); | |
12898 | break; | |
12899 | case SHIFT_ROR: | |
12900 | opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); | |
12901 | break; | |
12902 | default: | |
5f4273c7 | 12903 | abort (); |
728ca7c9 PB |
12904 | } |
12905 | ||
12906 | inst.instruction = opcode; | |
12907 | if (narrow) | |
12908 | { | |
fdfde340 | 12909 | inst.instruction |= Rn; |
728ca7c9 PB |
12910 | inst.instruction |= inst.operands[1].imm << 3; |
12911 | } | |
12912 | else | |
12913 | { | |
12914 | if (flags) | |
12915 | inst.instruction |= CONDS_BIT; | |
12916 | ||
fdfde340 JM |
12917 | inst.instruction |= Rn << 8; |
12918 | inst.instruction |= Rm << 16; | |
728ca7c9 PB |
12919 | inst.instruction |= inst.operands[1].imm; |
12920 | } | |
12921 | } | |
3d388997 | 12922 | else if (!narrow) |
c19d1205 | 12923 | { |
728ca7c9 PB |
12924 | /* Some mov with immediate shift have narrow variants. |
12925 | Register shifts are handled above. */ | |
12926 | if (low_regs && inst.operands[1].shifted | |
12927 | && (inst.instruction == T_MNEM_mov | |
12928 | || inst.instruction == T_MNEM_movs)) | |
12929 | { | |
5ee91343 | 12930 | if (in_pred_block ()) |
728ca7c9 PB |
12931 | narrow = (inst.instruction == T_MNEM_mov); |
12932 | else | |
12933 | narrow = (inst.instruction == T_MNEM_movs); | |
12934 | } | |
12935 | ||
12936 | if (narrow) | |
12937 | { | |
12938 | switch (inst.operands[1].shift_kind) | |
12939 | { | |
12940 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
12941 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
12942 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; | |
12943 | default: narrow = FALSE; break; | |
12944 | } | |
12945 | } | |
12946 | ||
12947 | if (narrow) | |
12948 | { | |
fdfde340 JM |
12949 | inst.instruction |= Rn; |
12950 | inst.instruction |= Rm << 3; | |
e2b0ab59 | 12951 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT; |
728ca7c9 PB |
12952 | } |
12953 | else | |
12954 | { | |
12955 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 12956 | inst.instruction |= Rn << r0off; |
728ca7c9 PB |
12957 | encode_thumb32_shifted_operand (1); |
12958 | } | |
c19d1205 ZW |
12959 | } |
12960 | else | |
12961 | switch (inst.instruction) | |
12962 | { | |
12963 | case T_MNEM_mov: | |
837b3435 | 12964 | /* In v4t or v5t a move of two lowregs produces unpredictable |
c6400f8a MGD |
12965 | results. Don't allow this. */ |
12966 | if (low_regs) | |
12967 | { | |
12968 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6), | |
12969 | "MOV Rd, Rs with two low registers is not " | |
12970 | "permitted on this architecture"); | |
fa94de6b | 12971 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
c6400f8a MGD |
12972 | arm_ext_v6); |
12973 | } | |
12974 | ||
c19d1205 | 12975 | inst.instruction = T_OPCODE_MOV_HR; |
fdfde340 JM |
12976 | inst.instruction |= (Rn & 0x8) << 4; |
12977 | inst.instruction |= (Rn & 0x7); | |
12978 | inst.instruction |= Rm << 3; | |
c19d1205 | 12979 | break; |
b99bd4ef | 12980 | |
c19d1205 ZW |
12981 | case T_MNEM_movs: |
12982 | /* We know we have low registers at this point. | |
941a8a52 MGD |
12983 | Generate LSLS Rd, Rs, #0. */ |
12984 | inst.instruction = T_OPCODE_LSL_I; | |
fdfde340 JM |
12985 | inst.instruction |= Rn; |
12986 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
12987 | break; |
12988 | ||
12989 | case T_MNEM_cmp: | |
3d388997 | 12990 | if (low_regs) |
c19d1205 ZW |
12991 | { |
12992 | inst.instruction = T_OPCODE_CMP_LR; | |
fdfde340 JM |
12993 | inst.instruction |= Rn; |
12994 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
12995 | } |
12996 | else | |
12997 | { | |
12998 | inst.instruction = T_OPCODE_CMP_HR; | |
fdfde340 JM |
12999 | inst.instruction |= (Rn & 0x8) << 4; |
13000 | inst.instruction |= (Rn & 0x7); | |
13001 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
13002 | } |
13003 | break; | |
13004 | } | |
b99bd4ef NC |
13005 | return; |
13006 | } | |
13007 | ||
c19d1205 | 13008 | inst.instruction = THUMB_OP16 (inst.instruction); |
539d4391 NC |
13009 | |
13010 | /* PR 10443: Do not silently ignore shifted operands. */ | |
13011 | constraint (inst.operands[1].shifted, | |
13012 | _("shifts in CMP/MOV instructions are only supported in unified syntax")); | |
13013 | ||
c19d1205 | 13014 | if (inst.operands[1].isreg) |
b99bd4ef | 13015 | { |
fdfde340 | 13016 | if (Rn < 8 && Rm < 8) |
b99bd4ef | 13017 | { |
c19d1205 ZW |
13018 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
13019 | since a MOV instruction produces unpredictable results. */ | |
13020 | if (inst.instruction == T_OPCODE_MOV_I8) | |
13021 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 13022 | else |
c19d1205 | 13023 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 13024 | |
fdfde340 JM |
13025 | inst.instruction |= Rn; |
13026 | inst.instruction |= Rm << 3; | |
b99bd4ef NC |
13027 | } |
13028 | else | |
13029 | { | |
c19d1205 ZW |
13030 | if (inst.instruction == T_OPCODE_MOV_I8) |
13031 | inst.instruction = T_OPCODE_MOV_HR; | |
13032 | else | |
13033 | inst.instruction = T_OPCODE_CMP_HR; | |
13034 | do_t_cpy (); | |
b99bd4ef NC |
13035 | } |
13036 | } | |
c19d1205 | 13037 | else |
b99bd4ef | 13038 | { |
fdfde340 | 13039 | constraint (Rn > 7, |
c19d1205 | 13040 | _("only lo regs allowed with immediate")); |
fdfde340 | 13041 | inst.instruction |= Rn << 8; |
e2b0ab59 | 13042 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM; |
c19d1205 ZW |
13043 | } |
13044 | } | |
b99bd4ef | 13045 | |
c19d1205 ZW |
13046 | static void |
13047 | do_t_mov16 (void) | |
13048 | { | |
fdfde340 | 13049 | unsigned Rd; |
b6895b4f PB |
13050 | bfd_vma imm; |
13051 | bfd_boolean top; | |
13052 | ||
13053 | top = (inst.instruction & 0x00800000) != 0; | |
e2b0ab59 | 13054 | if (inst.relocs[0].type == BFD_RELOC_ARM_MOVW) |
b6895b4f | 13055 | { |
33eaf5de | 13056 | constraint (top, _(":lower16: not allowed in this instruction")); |
e2b0ab59 | 13057 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVW; |
b6895b4f | 13058 | } |
e2b0ab59 | 13059 | else if (inst.relocs[0].type == BFD_RELOC_ARM_MOVT) |
b6895b4f | 13060 | { |
33eaf5de | 13061 | constraint (!top, _(":upper16: not allowed in this instruction")); |
e2b0ab59 | 13062 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVT; |
b6895b4f PB |
13063 | } |
13064 | ||
fdfde340 JM |
13065 | Rd = inst.operands[0].reg; |
13066 | reject_bad_reg (Rd); | |
13067 | ||
13068 | inst.instruction |= Rd << 8; | |
e2b0ab59 | 13069 | if (inst.relocs[0].type == BFD_RELOC_UNUSED) |
b6895b4f | 13070 | { |
e2b0ab59 | 13071 | imm = inst.relocs[0].exp.X_add_number; |
b6895b4f PB |
13072 | inst.instruction |= (imm & 0xf000) << 4; |
13073 | inst.instruction |= (imm & 0x0800) << 15; | |
13074 | inst.instruction |= (imm & 0x0700) << 4; | |
13075 | inst.instruction |= (imm & 0x00ff); | |
13076 | } | |
c19d1205 | 13077 | } |
b99bd4ef | 13078 | |
c19d1205 ZW |
13079 | static void |
13080 | do_t_mvn_tst (void) | |
13081 | { | |
fdfde340 | 13082 | unsigned Rn, Rm; |
c921be7d | 13083 | |
fdfde340 JM |
13084 | Rn = inst.operands[0].reg; |
13085 | Rm = inst.operands[1].reg; | |
13086 | ||
13087 | if (inst.instruction == T_MNEM_cmp | |
13088 | || inst.instruction == T_MNEM_cmn) | |
13089 | constraint (Rn == REG_PC, BAD_PC); | |
13090 | else | |
13091 | reject_bad_reg (Rn); | |
13092 | reject_bad_reg (Rm); | |
13093 | ||
c19d1205 ZW |
13094 | if (unified_syntax) |
13095 | { | |
13096 | int r0off = (inst.instruction == T_MNEM_mvn | |
13097 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
13098 | bfd_boolean narrow; |
13099 | ||
13100 | if (inst.size_req == 4 | |
13101 | || inst.instruction > 0xffff | |
13102 | || inst.operands[1].shifted | |
fdfde340 | 13103 | || Rn > 7 || Rm > 7) |
3d388997 | 13104 | narrow = FALSE; |
fe8b4cc3 KT |
13105 | else if (inst.instruction == T_MNEM_cmn |
13106 | || inst.instruction == T_MNEM_tst) | |
3d388997 PB |
13107 | narrow = TRUE; |
13108 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
5ee91343 | 13109 | narrow = !in_pred_block (); |
3d388997 | 13110 | else |
5ee91343 | 13111 | narrow = in_pred_block (); |
3d388997 | 13112 | |
c19d1205 | 13113 | if (!inst.operands[1].isreg) |
b99bd4ef | 13114 | { |
c19d1205 ZW |
13115 | /* For an immediate, we always generate a 32-bit opcode; |
13116 | section relaxation will shrink it later if possible. */ | |
13117 | if (inst.instruction < 0xffff) | |
13118 | inst.instruction = THUMB_OP32 (inst.instruction); | |
13119 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 13120 | inst.instruction |= Rn << r0off; |
e2b0ab59 | 13121 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
b99bd4ef | 13122 | } |
c19d1205 | 13123 | else |
b99bd4ef | 13124 | { |
c19d1205 | 13125 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 13126 | if (narrow) |
b99bd4ef | 13127 | { |
c19d1205 | 13128 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
13129 | inst.instruction |= Rn; |
13130 | inst.instruction |= Rm << 3; | |
b99bd4ef | 13131 | } |
c19d1205 | 13132 | else |
b99bd4ef | 13133 | { |
c19d1205 ZW |
13134 | constraint (inst.operands[1].shifted |
13135 | && inst.operands[1].immisreg, | |
13136 | _("shift must be constant")); | |
13137 | if (inst.instruction < 0xffff) | |
13138 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 13139 | inst.instruction |= Rn << r0off; |
c19d1205 | 13140 | encode_thumb32_shifted_operand (1); |
b99bd4ef | 13141 | } |
b99bd4ef NC |
13142 | } |
13143 | } | |
13144 | else | |
13145 | { | |
c19d1205 ZW |
13146 | constraint (inst.instruction > 0xffff |
13147 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
13148 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
13149 | _("unshifted register required")); | |
fdfde340 | 13150 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 13151 | BAD_HIREG); |
b99bd4ef | 13152 | |
c19d1205 | 13153 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
13154 | inst.instruction |= Rn; |
13155 | inst.instruction |= Rm << 3; | |
b99bd4ef | 13156 | } |
b99bd4ef NC |
13157 | } |
13158 | ||
b05fe5cf | 13159 | static void |
c19d1205 | 13160 | do_t_mrs (void) |
b05fe5cf | 13161 | { |
fdfde340 | 13162 | unsigned Rd; |
037e8744 JB |
13163 | |
13164 | if (do_vfp_nsyn_mrs () == SUCCESS) | |
13165 | return; | |
13166 | ||
90ec0d68 MGD |
13167 | Rd = inst.operands[0].reg; |
13168 | reject_bad_reg (Rd); | |
13169 | inst.instruction |= Rd << 8; | |
13170 | ||
13171 | if (inst.operands[1].isreg) | |
62b3e311 | 13172 | { |
90ec0d68 MGD |
13173 | unsigned br = inst.operands[1].reg; |
13174 | if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000)) | |
13175 | as_bad (_("bad register for mrs")); | |
13176 | ||
13177 | inst.instruction |= br & (0xf << 16); | |
13178 | inst.instruction |= (br & 0x300) >> 4; | |
13179 | inst.instruction |= (br & SPSR_BIT) >> 2; | |
62b3e311 PB |
13180 | } |
13181 | else | |
13182 | { | |
90ec0d68 | 13183 | int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
5f4273c7 | 13184 | |
d2cd1205 | 13185 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
1a43faaf NC |
13186 | { |
13187 | /* PR gas/12698: The constraint is only applied for m_profile. | |
13188 | If the user has specified -march=all, we want to ignore it as | |
13189 | we are building for any CPU type, including non-m variants. */ | |
823d2571 TG |
13190 | bfd_boolean m_profile = |
13191 | !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any); | |
1a43faaf NC |
13192 | constraint ((flags != 0) && m_profile, _("selected processor does " |
13193 | "not support requested special purpose register")); | |
13194 | } | |
90ec0d68 | 13195 | else |
d2cd1205 JB |
13196 | /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile |
13197 | devices). */ | |
13198 | constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), | |
13199 | _("'APSR', 'CPSR' or 'SPSR' expected")); | |
fdfde340 | 13200 | |
90ec0d68 MGD |
13201 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
13202 | inst.instruction |= inst.operands[1].imm & 0xff; | |
13203 | inst.instruction |= 0xf0000; | |
13204 | } | |
c19d1205 | 13205 | } |
b05fe5cf | 13206 | |
c19d1205 ZW |
13207 | static void |
13208 | do_t_msr (void) | |
13209 | { | |
62b3e311 | 13210 | int flags; |
fdfde340 | 13211 | unsigned Rn; |
62b3e311 | 13212 | |
037e8744 JB |
13213 | if (do_vfp_nsyn_msr () == SUCCESS) |
13214 | return; | |
13215 | ||
c19d1205 ZW |
13216 | constraint (!inst.operands[1].isreg, |
13217 | _("Thumb encoding does not support an immediate here")); | |
90ec0d68 MGD |
13218 | |
13219 | if (inst.operands[0].isreg) | |
13220 | flags = (int)(inst.operands[0].reg); | |
13221 | else | |
13222 | flags = inst.operands[0].imm; | |
13223 | ||
d2cd1205 | 13224 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
62b3e311 | 13225 | { |
d2cd1205 JB |
13226 | int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
13227 | ||
1a43faaf | 13228 | /* PR gas/12698: The constraint is only applied for m_profile. |
477330fc RM |
13229 | If the user has specified -march=all, we want to ignore it as |
13230 | we are building for any CPU type, including non-m variants. */ | |
823d2571 TG |
13231 | bfd_boolean m_profile = |
13232 | !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any); | |
1a43faaf | 13233 | constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) |
477330fc RM |
13234 | && (bits & ~(PSR_s | PSR_f)) != 0) |
13235 | || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) | |
13236 | && bits != PSR_f)) && m_profile, | |
13237 | _("selected processor does not support requested special " | |
13238 | "purpose register")); | |
62b3e311 PB |
13239 | } |
13240 | else | |
d2cd1205 JB |
13241 | constraint ((flags & 0xff) != 0, _("selected processor does not support " |
13242 | "requested special purpose register")); | |
c921be7d | 13243 | |
fdfde340 JM |
13244 | Rn = inst.operands[1].reg; |
13245 | reject_bad_reg (Rn); | |
13246 | ||
62b3e311 | 13247 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
90ec0d68 MGD |
13248 | inst.instruction |= (flags & 0xf0000) >> 8; |
13249 | inst.instruction |= (flags & 0x300) >> 4; | |
62b3e311 | 13250 | inst.instruction |= (flags & 0xff); |
fdfde340 | 13251 | inst.instruction |= Rn << 16; |
c19d1205 | 13252 | } |
b05fe5cf | 13253 | |
c19d1205 ZW |
13254 | static void |
13255 | do_t_mul (void) | |
13256 | { | |
17828f45 | 13257 | bfd_boolean narrow; |
fdfde340 | 13258 | unsigned Rd, Rn, Rm; |
17828f45 | 13259 | |
c19d1205 ZW |
13260 | if (!inst.operands[2].present) |
13261 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 13262 | |
fdfde340 JM |
13263 | Rd = inst.operands[0].reg; |
13264 | Rn = inst.operands[1].reg; | |
13265 | Rm = inst.operands[2].reg; | |
13266 | ||
17828f45 | 13267 | if (unified_syntax) |
b05fe5cf | 13268 | { |
17828f45 | 13269 | if (inst.size_req == 4 |
fdfde340 JM |
13270 | || (Rd != Rn |
13271 | && Rd != Rm) | |
13272 | || Rn > 7 | |
13273 | || Rm > 7) | |
17828f45 JM |
13274 | narrow = FALSE; |
13275 | else if (inst.instruction == T_MNEM_muls) | |
5ee91343 | 13276 | narrow = !in_pred_block (); |
17828f45 | 13277 | else |
5ee91343 | 13278 | narrow = in_pred_block (); |
b05fe5cf | 13279 | } |
c19d1205 | 13280 | else |
b05fe5cf | 13281 | { |
17828f45 | 13282 | constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); |
fdfde340 | 13283 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 13284 | BAD_HIREG); |
17828f45 JM |
13285 | narrow = TRUE; |
13286 | } | |
b05fe5cf | 13287 | |
17828f45 JM |
13288 | if (narrow) |
13289 | { | |
13290 | /* 16-bit MULS/Conditional MUL. */ | |
c19d1205 | 13291 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 | 13292 | inst.instruction |= Rd; |
b05fe5cf | 13293 | |
fdfde340 JM |
13294 | if (Rd == Rn) |
13295 | inst.instruction |= Rm << 3; | |
13296 | else if (Rd == Rm) | |
13297 | inst.instruction |= Rn << 3; | |
c19d1205 ZW |
13298 | else |
13299 | constraint (1, _("dest must overlap one source register")); | |
13300 | } | |
17828f45 JM |
13301 | else |
13302 | { | |
e07e6e58 NC |
13303 | constraint (inst.instruction != T_MNEM_mul, |
13304 | _("Thumb-2 MUL must not set flags")); | |
17828f45 JM |
13305 | /* 32-bit MUL. */ |
13306 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
13307 | inst.instruction |= Rd << 8; |
13308 | inst.instruction |= Rn << 16; | |
13309 | inst.instruction |= Rm << 0; | |
13310 | ||
13311 | reject_bad_reg (Rd); | |
13312 | reject_bad_reg (Rn); | |
13313 | reject_bad_reg (Rm); | |
17828f45 | 13314 | } |
c19d1205 | 13315 | } |
b05fe5cf | 13316 | |
c19d1205 ZW |
13317 | static void |
13318 | do_t_mull (void) | |
13319 | { | |
fdfde340 | 13320 | unsigned RdLo, RdHi, Rn, Rm; |
b05fe5cf | 13321 | |
fdfde340 JM |
13322 | RdLo = inst.operands[0].reg; |
13323 | RdHi = inst.operands[1].reg; | |
13324 | Rn = inst.operands[2].reg; | |
13325 | Rm = inst.operands[3].reg; | |
13326 | ||
13327 | reject_bad_reg (RdLo); | |
13328 | reject_bad_reg (RdHi); | |
13329 | reject_bad_reg (Rn); | |
13330 | reject_bad_reg (Rm); | |
13331 | ||
13332 | inst.instruction |= RdLo << 12; | |
13333 | inst.instruction |= RdHi << 8; | |
13334 | inst.instruction |= Rn << 16; | |
13335 | inst.instruction |= Rm; | |
13336 | ||
13337 | if (RdLo == RdHi) | |
c19d1205 ZW |
13338 | as_tsktsk (_("rdhi and rdlo must be different")); |
13339 | } | |
b05fe5cf | 13340 | |
c19d1205 ZW |
13341 | static void |
13342 | do_t_nop (void) | |
13343 | { | |
5ee91343 | 13344 | set_pred_insn_type (NEUTRAL_IT_INSN); |
e07e6e58 | 13345 | |
c19d1205 ZW |
13346 | if (unified_syntax) |
13347 | { | |
13348 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 13349 | { |
c19d1205 ZW |
13350 | inst.instruction = THUMB_OP32 (inst.instruction); |
13351 | inst.instruction |= inst.operands[0].imm; | |
13352 | } | |
13353 | else | |
13354 | { | |
bc2d1808 NC |
13355 | /* PR9722: Check for Thumb2 availability before |
13356 | generating a thumb2 nop instruction. */ | |
afa62d5e | 13357 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
bc2d1808 NC |
13358 | { |
13359 | inst.instruction = THUMB_OP16 (inst.instruction); | |
13360 | inst.instruction |= inst.operands[0].imm << 4; | |
13361 | } | |
13362 | else | |
13363 | inst.instruction = 0x46c0; | |
c19d1205 ZW |
13364 | } |
13365 | } | |
13366 | else | |
13367 | { | |
13368 | constraint (inst.operands[0].present, | |
13369 | _("Thumb does not support NOP with hints")); | |
13370 | inst.instruction = 0x46c0; | |
13371 | } | |
13372 | } | |
b05fe5cf | 13373 | |
c19d1205 ZW |
13374 | static void |
13375 | do_t_neg (void) | |
13376 | { | |
13377 | if (unified_syntax) | |
13378 | { | |
3d388997 PB |
13379 | bfd_boolean narrow; |
13380 | ||
13381 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
5ee91343 | 13382 | narrow = !in_pred_block (); |
3d388997 | 13383 | else |
5ee91343 | 13384 | narrow = in_pred_block (); |
3d388997 PB |
13385 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
13386 | narrow = FALSE; | |
13387 | if (inst.size_req == 4) | |
13388 | narrow = FALSE; | |
13389 | ||
13390 | if (!narrow) | |
c19d1205 ZW |
13391 | { |
13392 | inst.instruction = THUMB_OP32 (inst.instruction); | |
13393 | inst.instruction |= inst.operands[0].reg << 8; | |
13394 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
13395 | } |
13396 | else | |
13397 | { | |
c19d1205 ZW |
13398 | inst.instruction = THUMB_OP16 (inst.instruction); |
13399 | inst.instruction |= inst.operands[0].reg; | |
13400 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
13401 | } |
13402 | } | |
13403 | else | |
13404 | { | |
c19d1205 ZW |
13405 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
13406 | BAD_HIREG); | |
13407 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
13408 | ||
13409 | inst.instruction = THUMB_OP16 (inst.instruction); | |
13410 | inst.instruction |= inst.operands[0].reg; | |
13411 | inst.instruction |= inst.operands[1].reg << 3; | |
13412 | } | |
13413 | } | |
13414 | ||
1c444d06 JM |
13415 | static void |
13416 | do_t_orn (void) | |
13417 | { | |
13418 | unsigned Rd, Rn; | |
13419 | ||
13420 | Rd = inst.operands[0].reg; | |
13421 | Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; | |
13422 | ||
fdfde340 JM |
13423 | reject_bad_reg (Rd); |
13424 | /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ | |
13425 | reject_bad_reg (Rn); | |
13426 | ||
1c444d06 JM |
13427 | inst.instruction |= Rd << 8; |
13428 | inst.instruction |= Rn << 16; | |
13429 | ||
13430 | if (!inst.operands[2].isreg) | |
13431 | { | |
13432 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
e2b0ab59 | 13433 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
1c444d06 JM |
13434 | } |
13435 | else | |
13436 | { | |
13437 | unsigned Rm; | |
13438 | ||
13439 | Rm = inst.operands[2].reg; | |
fdfde340 | 13440 | reject_bad_reg (Rm); |
1c444d06 JM |
13441 | |
13442 | constraint (inst.operands[2].shifted | |
13443 | && inst.operands[2].immisreg, | |
13444 | _("shift must be constant")); | |
13445 | encode_thumb32_shifted_operand (2); | |
13446 | } | |
13447 | } | |
13448 | ||
c19d1205 ZW |
13449 | static void |
13450 | do_t_pkhbt (void) | |
13451 | { | |
fdfde340 JM |
13452 | unsigned Rd, Rn, Rm; |
13453 | ||
13454 | Rd = inst.operands[0].reg; | |
13455 | Rn = inst.operands[1].reg; | |
13456 | Rm = inst.operands[2].reg; | |
13457 | ||
13458 | reject_bad_reg (Rd); | |
13459 | reject_bad_reg (Rn); | |
13460 | reject_bad_reg (Rm); | |
13461 | ||
13462 | inst.instruction |= Rd << 8; | |
13463 | inst.instruction |= Rn << 16; | |
13464 | inst.instruction |= Rm; | |
c19d1205 ZW |
13465 | if (inst.operands[3].present) |
13466 | { | |
e2b0ab59 AV |
13467 | unsigned int val = inst.relocs[0].exp.X_add_number; |
13468 | constraint (inst.relocs[0].exp.X_op != O_constant, | |
c19d1205 ZW |
13469 | _("expression too complex")); |
13470 | inst.instruction |= (val & 0x1c) << 10; | |
13471 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 13472 | } |
c19d1205 | 13473 | } |
b05fe5cf | 13474 | |
c19d1205 ZW |
13475 | static void |
13476 | do_t_pkhtb (void) | |
13477 | { | |
13478 | if (!inst.operands[3].present) | |
1ef52f49 NC |
13479 | { |
13480 | unsigned Rtmp; | |
13481 | ||
13482 | inst.instruction &= ~0x00000020; | |
13483 | ||
13484 | /* PR 10168. Swap the Rm and Rn registers. */ | |
13485 | Rtmp = inst.operands[1].reg; | |
13486 | inst.operands[1].reg = inst.operands[2].reg; | |
13487 | inst.operands[2].reg = Rtmp; | |
13488 | } | |
c19d1205 | 13489 | do_t_pkhbt (); |
b05fe5cf ZW |
13490 | } |
13491 | ||
c19d1205 ZW |
13492 | static void |
13493 | do_t_pld (void) | |
13494 | { | |
fdfde340 JM |
13495 | if (inst.operands[0].immisreg) |
13496 | reject_bad_reg (inst.operands[0].imm); | |
13497 | ||
c19d1205 ZW |
13498 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); |
13499 | } | |
b05fe5cf | 13500 | |
c19d1205 ZW |
13501 | static void |
13502 | do_t_push_pop (void) | |
b99bd4ef | 13503 | { |
e9f89963 | 13504 | unsigned mask; |
5f4273c7 | 13505 | |
c19d1205 ZW |
13506 | constraint (inst.operands[0].writeback, |
13507 | _("push/pop do not support {reglist}^")); | |
e2b0ab59 | 13508 | constraint (inst.relocs[0].type != BFD_RELOC_UNUSED, |
c19d1205 | 13509 | _("expression too complex")); |
b99bd4ef | 13510 | |
e9f89963 | 13511 | mask = inst.operands[0].imm; |
d3bfe16e | 13512 | if (inst.size_req != 4 && (mask & ~0xff) == 0) |
3c707909 | 13513 | inst.instruction = THUMB_OP16 (inst.instruction) | mask; |
d3bfe16e | 13514 | else if (inst.size_req != 4 |
c6025a80 | 13515 | && (mask & ~0xff) == (1U << (inst.instruction == T_MNEM_push |
d3bfe16e | 13516 | ? REG_LR : REG_PC))) |
b99bd4ef | 13517 | { |
c19d1205 ZW |
13518 | inst.instruction = THUMB_OP16 (inst.instruction); |
13519 | inst.instruction |= THUMB_PP_PC_LR; | |
3c707909 | 13520 | inst.instruction |= mask & 0xff; |
c19d1205 ZW |
13521 | } |
13522 | else if (unified_syntax) | |
13523 | { | |
3c707909 | 13524 | inst.instruction = THUMB_OP32 (inst.instruction); |
4b5a202f AV |
13525 | encode_thumb2_multi (TRUE /* do_io */, 13, mask, TRUE); |
13526 | } | |
13527 | else | |
13528 | { | |
13529 | inst.error = _("invalid register list to push/pop instruction"); | |
13530 | return; | |
c19d1205 | 13531 | } |
4b5a202f AV |
13532 | } |
13533 | ||
13534 | static void | |
13535 | do_t_clrm (void) | |
13536 | { | |
13537 | if (unified_syntax) | |
13538 | encode_thumb2_multi (FALSE /* do_io */, -1, inst.operands[0].imm, FALSE); | |
c19d1205 ZW |
13539 | else |
13540 | { | |
13541 | inst.error = _("invalid register list to push/pop instruction"); | |
13542 | return; | |
13543 | } | |
c19d1205 | 13544 | } |
b99bd4ef | 13545 | |
efd6b359 AV |
13546 | static void |
13547 | do_t_vscclrm (void) | |
13548 | { | |
13549 | if (inst.operands[0].issingle) | |
13550 | { | |
13551 | inst.instruction |= (inst.operands[0].reg & 0x1) << 22; | |
13552 | inst.instruction |= (inst.operands[0].reg & 0x1e) << 11; | |
13553 | inst.instruction |= inst.operands[0].imm; | |
13554 | } | |
13555 | else | |
13556 | { | |
13557 | inst.instruction |= (inst.operands[0].reg & 0x10) << 18; | |
13558 | inst.instruction |= (inst.operands[0].reg & 0xf) << 12; | |
13559 | inst.instruction |= 1 << 8; | |
13560 | inst.instruction |= inst.operands[0].imm << 1; | |
13561 | } | |
13562 | } | |
13563 | ||
c19d1205 ZW |
13564 | static void |
13565 | do_t_rbit (void) | |
13566 | { | |
fdfde340 JM |
13567 | unsigned Rd, Rm; |
13568 | ||
13569 | Rd = inst.operands[0].reg; | |
13570 | Rm = inst.operands[1].reg; | |
13571 | ||
13572 | reject_bad_reg (Rd); | |
13573 | reject_bad_reg (Rm); | |
13574 | ||
13575 | inst.instruction |= Rd << 8; | |
13576 | inst.instruction |= Rm << 16; | |
13577 | inst.instruction |= Rm; | |
c19d1205 | 13578 | } |
b99bd4ef | 13579 | |
c19d1205 ZW |
13580 | static void |
13581 | do_t_rev (void) | |
13582 | { | |
fdfde340 JM |
13583 | unsigned Rd, Rm; |
13584 | ||
13585 | Rd = inst.operands[0].reg; | |
13586 | Rm = inst.operands[1].reg; | |
13587 | ||
13588 | reject_bad_reg (Rd); | |
13589 | reject_bad_reg (Rm); | |
13590 | ||
13591 | if (Rd <= 7 && Rm <= 7 | |
c19d1205 ZW |
13592 | && inst.size_req != 4) |
13593 | { | |
13594 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 JM |
13595 | inst.instruction |= Rd; |
13596 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
13597 | } |
13598 | else if (unified_syntax) | |
13599 | { | |
13600 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
13601 | inst.instruction |= Rd << 8; |
13602 | inst.instruction |= Rm << 16; | |
13603 | inst.instruction |= Rm; | |
c19d1205 ZW |
13604 | } |
13605 | else | |
13606 | inst.error = BAD_HIREG; | |
13607 | } | |
b99bd4ef | 13608 | |
1c444d06 JM |
13609 | static void |
13610 | do_t_rrx (void) | |
13611 | { | |
13612 | unsigned Rd, Rm; | |
13613 | ||
13614 | Rd = inst.operands[0].reg; | |
13615 | Rm = inst.operands[1].reg; | |
13616 | ||
fdfde340 JM |
13617 | reject_bad_reg (Rd); |
13618 | reject_bad_reg (Rm); | |
c921be7d | 13619 | |
1c444d06 JM |
13620 | inst.instruction |= Rd << 8; |
13621 | inst.instruction |= Rm; | |
13622 | } | |
13623 | ||
c19d1205 ZW |
13624 | static void |
13625 | do_t_rsb (void) | |
13626 | { | |
fdfde340 | 13627 | unsigned Rd, Rs; |
b99bd4ef | 13628 | |
c19d1205 ZW |
13629 | Rd = inst.operands[0].reg; |
13630 | Rs = (inst.operands[1].present | |
13631 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
13632 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 13633 | |
fdfde340 JM |
13634 | reject_bad_reg (Rd); |
13635 | reject_bad_reg (Rs); | |
13636 | if (inst.operands[2].isreg) | |
13637 | reject_bad_reg (inst.operands[2].reg); | |
13638 | ||
c19d1205 ZW |
13639 | inst.instruction |= Rd << 8; |
13640 | inst.instruction |= Rs << 16; | |
13641 | if (!inst.operands[2].isreg) | |
13642 | { | |
026d3abb PB |
13643 | bfd_boolean narrow; |
13644 | ||
13645 | if ((inst.instruction & 0x00100000) != 0) | |
5ee91343 | 13646 | narrow = !in_pred_block (); |
026d3abb | 13647 | else |
5ee91343 | 13648 | narrow = in_pred_block (); |
026d3abb PB |
13649 | |
13650 | if (Rd > 7 || Rs > 7) | |
13651 | narrow = FALSE; | |
13652 | ||
13653 | if (inst.size_req == 4 || !unified_syntax) | |
13654 | narrow = FALSE; | |
13655 | ||
e2b0ab59 AV |
13656 | if (inst.relocs[0].exp.X_op != O_constant |
13657 | || inst.relocs[0].exp.X_add_number != 0) | |
026d3abb PB |
13658 | narrow = FALSE; |
13659 | ||
13660 | /* Turn rsb #0 into 16-bit neg. We should probably do this via | |
477330fc | 13661 | relaxation, but it doesn't seem worth the hassle. */ |
026d3abb PB |
13662 | if (narrow) |
13663 | { | |
e2b0ab59 | 13664 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
026d3abb PB |
13665 | inst.instruction = THUMB_OP16 (T_MNEM_negs); |
13666 | inst.instruction |= Rs << 3; | |
13667 | inst.instruction |= Rd; | |
13668 | } | |
13669 | else | |
13670 | { | |
13671 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
e2b0ab59 | 13672 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
026d3abb | 13673 | } |
c19d1205 ZW |
13674 | } |
13675 | else | |
13676 | encode_thumb32_shifted_operand (2); | |
13677 | } | |
b99bd4ef | 13678 | |
c19d1205 ZW |
13679 | static void |
13680 | do_t_setend (void) | |
13681 | { | |
12e37cbc MGD |
13682 | if (warn_on_deprecated |
13683 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
5c3696f8 | 13684 | as_tsktsk (_("setend use is deprecated for ARMv8")); |
12e37cbc | 13685 | |
5ee91343 | 13686 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
c19d1205 ZW |
13687 | if (inst.operands[0].imm) |
13688 | inst.instruction |= 0x8; | |
13689 | } | |
b99bd4ef | 13690 | |
c19d1205 ZW |
13691 | static void |
13692 | do_t_shift (void) | |
13693 | { | |
13694 | if (!inst.operands[1].present) | |
13695 | inst.operands[1].reg = inst.operands[0].reg; | |
13696 | ||
13697 | if (unified_syntax) | |
13698 | { | |
3d388997 PB |
13699 | bfd_boolean narrow; |
13700 | int shift_kind; | |
13701 | ||
13702 | switch (inst.instruction) | |
13703 | { | |
13704 | case T_MNEM_asr: | |
13705 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
13706 | case T_MNEM_lsl: | |
13707 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
13708 | case T_MNEM_lsr: | |
13709 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
13710 | case T_MNEM_ror: | |
13711 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
13712 | default: abort (); | |
13713 | } | |
13714 | ||
13715 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
5ee91343 | 13716 | narrow = !in_pred_block (); |
3d388997 | 13717 | else |
5ee91343 | 13718 | narrow = in_pred_block (); |
3d388997 PB |
13719 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
13720 | narrow = FALSE; | |
13721 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
13722 | narrow = FALSE; | |
13723 | if (inst.operands[2].isreg | |
13724 | && (inst.operands[1].reg != inst.operands[0].reg | |
13725 | || inst.operands[2].reg > 7)) | |
13726 | narrow = FALSE; | |
13727 | if (inst.size_req == 4) | |
13728 | narrow = FALSE; | |
13729 | ||
fdfde340 JM |
13730 | reject_bad_reg (inst.operands[0].reg); |
13731 | reject_bad_reg (inst.operands[1].reg); | |
c921be7d | 13732 | |
3d388997 | 13733 | if (!narrow) |
c19d1205 ZW |
13734 | { |
13735 | if (inst.operands[2].isreg) | |
b99bd4ef | 13736 | { |
fdfde340 | 13737 | reject_bad_reg (inst.operands[2].reg); |
c19d1205 ZW |
13738 | inst.instruction = THUMB_OP32 (inst.instruction); |
13739 | inst.instruction |= inst.operands[0].reg << 8; | |
13740 | inst.instruction |= inst.operands[1].reg << 16; | |
13741 | inst.instruction |= inst.operands[2].reg; | |
94342ec3 NC |
13742 | |
13743 | /* PR 12854: Error on extraneous shifts. */ | |
13744 | constraint (inst.operands[2].shifted, | |
13745 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
13746 | } |
13747 | else | |
13748 | { | |
13749 | inst.operands[1].shifted = 1; | |
3d388997 | 13750 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
13751 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
13752 | ? T_MNEM_movs : T_MNEM_mov); | |
13753 | inst.instruction |= inst.operands[0].reg << 8; | |
13754 | encode_thumb32_shifted_operand (1); | |
13755 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
e2b0ab59 | 13756 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
b99bd4ef NC |
13757 | } |
13758 | } | |
13759 | else | |
13760 | { | |
c19d1205 | 13761 | if (inst.operands[2].isreg) |
b99bd4ef | 13762 | { |
3d388997 | 13763 | switch (shift_kind) |
b99bd4ef | 13764 | { |
3d388997 PB |
13765 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
13766 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
13767 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
13768 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 13769 | default: abort (); |
b99bd4ef | 13770 | } |
5f4273c7 | 13771 | |
c19d1205 ZW |
13772 | inst.instruction |= inst.operands[0].reg; |
13773 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
13774 | |
13775 | /* PR 12854: Error on extraneous shifts. */ | |
13776 | constraint (inst.operands[2].shifted, | |
13777 | _("extraneous shift as part of operand to shift insn")); | |
b99bd4ef NC |
13778 | } |
13779 | else | |
13780 | { | |
3d388997 | 13781 | switch (shift_kind) |
b99bd4ef | 13782 | { |
3d388997 PB |
13783 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
13784 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
13785 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 13786 | default: abort (); |
b99bd4ef | 13787 | } |
e2b0ab59 | 13788 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT; |
c19d1205 ZW |
13789 | inst.instruction |= inst.operands[0].reg; |
13790 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
13791 | } |
13792 | } | |
c19d1205 ZW |
13793 | } |
13794 | else | |
13795 | { | |
13796 | constraint (inst.operands[0].reg > 7 | |
13797 | || inst.operands[1].reg > 7, BAD_HIREG); | |
13798 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 13799 | |
c19d1205 ZW |
13800 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
13801 | { | |
13802 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
13803 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
13804 | _("source1 and dest must be same register")); | |
b99bd4ef | 13805 | |
c19d1205 ZW |
13806 | switch (inst.instruction) |
13807 | { | |
13808 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
13809 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
13810 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
13811 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
13812 | default: abort (); | |
13813 | } | |
5f4273c7 | 13814 | |
c19d1205 ZW |
13815 | inst.instruction |= inst.operands[0].reg; |
13816 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
13817 | |
13818 | /* PR 12854: Error on extraneous shifts. */ | |
13819 | constraint (inst.operands[2].shifted, | |
13820 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
13821 | } |
13822 | else | |
b99bd4ef | 13823 | { |
c19d1205 ZW |
13824 | switch (inst.instruction) |
13825 | { | |
13826 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
13827 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
13828 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
13829 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
13830 | default: abort (); | |
13831 | } | |
e2b0ab59 | 13832 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT; |
c19d1205 ZW |
13833 | inst.instruction |= inst.operands[0].reg; |
13834 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
13835 | } |
13836 | } | |
b99bd4ef NC |
13837 | } |
13838 | ||
13839 | static void | |
c19d1205 | 13840 | do_t_simd (void) |
b99bd4ef | 13841 | { |
fdfde340 JM |
13842 | unsigned Rd, Rn, Rm; |
13843 | ||
13844 | Rd = inst.operands[0].reg; | |
13845 | Rn = inst.operands[1].reg; | |
13846 | Rm = inst.operands[2].reg; | |
13847 | ||
13848 | reject_bad_reg (Rd); | |
13849 | reject_bad_reg (Rn); | |
13850 | reject_bad_reg (Rm); | |
13851 | ||
13852 | inst.instruction |= Rd << 8; | |
13853 | inst.instruction |= Rn << 16; | |
13854 | inst.instruction |= Rm; | |
c19d1205 | 13855 | } |
b99bd4ef | 13856 | |
03ee1b7f NC |
13857 | static void |
13858 | do_t_simd2 (void) | |
13859 | { | |
13860 | unsigned Rd, Rn, Rm; | |
13861 | ||
13862 | Rd = inst.operands[0].reg; | |
13863 | Rm = inst.operands[1].reg; | |
13864 | Rn = inst.operands[2].reg; | |
13865 | ||
13866 | reject_bad_reg (Rd); | |
13867 | reject_bad_reg (Rn); | |
13868 | reject_bad_reg (Rm); | |
13869 | ||
13870 | inst.instruction |= Rd << 8; | |
13871 | inst.instruction |= Rn << 16; | |
13872 | inst.instruction |= Rm; | |
13873 | } | |
13874 | ||
c19d1205 | 13875 | static void |
3eb17e6b | 13876 | do_t_smc (void) |
c19d1205 | 13877 | { |
e2b0ab59 | 13878 | unsigned int value = inst.relocs[0].exp.X_add_number; |
f4c65163 MGD |
13879 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a), |
13880 | _("SMC is not permitted on this architecture")); | |
e2b0ab59 | 13881 | constraint (inst.relocs[0].exp.X_op != O_constant, |
c19d1205 | 13882 | _("expression too complex")); |
ba85f98c BW |
13883 | constraint (value > 0xf, _("immediate too large (bigger than 0xF)")); |
13884 | ||
e2b0ab59 | 13885 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
c19d1205 | 13886 | inst.instruction |= (value & 0x000f) << 16; |
ba85f98c | 13887 | |
24382199 | 13888 | /* PR gas/15623: SMC instructions must be last in an IT block. */ |
5ee91343 | 13889 | set_pred_insn_type_last (); |
c19d1205 | 13890 | } |
b99bd4ef | 13891 | |
90ec0d68 MGD |
13892 | static void |
13893 | do_t_hvc (void) | |
13894 | { | |
e2b0ab59 | 13895 | unsigned int value = inst.relocs[0].exp.X_add_number; |
90ec0d68 | 13896 | |
e2b0ab59 | 13897 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
90ec0d68 MGD |
13898 | inst.instruction |= (value & 0x0fff); |
13899 | inst.instruction |= (value & 0xf000) << 4; | |
13900 | } | |
13901 | ||
c19d1205 | 13902 | static void |
3a21c15a | 13903 | do_t_ssat_usat (int bias) |
c19d1205 | 13904 | { |
fdfde340 JM |
13905 | unsigned Rd, Rn; |
13906 | ||
13907 | Rd = inst.operands[0].reg; | |
13908 | Rn = inst.operands[2].reg; | |
13909 | ||
13910 | reject_bad_reg (Rd); | |
13911 | reject_bad_reg (Rn); | |
13912 | ||
13913 | inst.instruction |= Rd << 8; | |
3a21c15a | 13914 | inst.instruction |= inst.operands[1].imm - bias; |
fdfde340 | 13915 | inst.instruction |= Rn << 16; |
b99bd4ef | 13916 | |
c19d1205 | 13917 | if (inst.operands[3].present) |
b99bd4ef | 13918 | { |
e2b0ab59 | 13919 | offsetT shift_amount = inst.relocs[0].exp.X_add_number; |
3a21c15a | 13920 | |
e2b0ab59 | 13921 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
3a21c15a | 13922 | |
e2b0ab59 | 13923 | constraint (inst.relocs[0].exp.X_op != O_constant, |
c19d1205 | 13924 | _("expression too complex")); |
b99bd4ef | 13925 | |
3a21c15a | 13926 | if (shift_amount != 0) |
6189168b | 13927 | { |
3a21c15a NC |
13928 | constraint (shift_amount > 31, |
13929 | _("shift expression is too large")); | |
13930 | ||
c19d1205 | 13931 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
3a21c15a NC |
13932 | inst.instruction |= 0x00200000; /* sh bit. */ |
13933 | ||
13934 | inst.instruction |= (shift_amount & 0x1c) << 10; | |
13935 | inst.instruction |= (shift_amount & 0x03) << 6; | |
6189168b NC |
13936 | } |
13937 | } | |
b99bd4ef | 13938 | } |
c921be7d | 13939 | |
3a21c15a NC |
13940 | static void |
13941 | do_t_ssat (void) | |
13942 | { | |
13943 | do_t_ssat_usat (1); | |
13944 | } | |
b99bd4ef | 13945 | |
0dd132b6 | 13946 | static void |
c19d1205 | 13947 | do_t_ssat16 (void) |
0dd132b6 | 13948 | { |
fdfde340 JM |
13949 | unsigned Rd, Rn; |
13950 | ||
13951 | Rd = inst.operands[0].reg; | |
13952 | Rn = inst.operands[2].reg; | |
13953 | ||
13954 | reject_bad_reg (Rd); | |
13955 | reject_bad_reg (Rn); | |
13956 | ||
13957 | inst.instruction |= Rd << 8; | |
c19d1205 | 13958 | inst.instruction |= inst.operands[1].imm - 1; |
fdfde340 | 13959 | inst.instruction |= Rn << 16; |
c19d1205 | 13960 | } |
0dd132b6 | 13961 | |
c19d1205 ZW |
13962 | static void |
13963 | do_t_strex (void) | |
13964 | { | |
13965 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
13966 | || inst.operands[2].postind || inst.operands[2].writeback | |
13967 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
13968 | || inst.operands[2].negative, | |
01cfc07f | 13969 | BAD_ADDR_MODE); |
0dd132b6 | 13970 | |
5be8be5d DG |
13971 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
13972 | ||
c19d1205 ZW |
13973 | inst.instruction |= inst.operands[0].reg << 8; |
13974 | inst.instruction |= inst.operands[1].reg << 12; | |
13975 | inst.instruction |= inst.operands[2].reg << 16; | |
e2b0ab59 | 13976 | inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8; |
0dd132b6 NC |
13977 | } |
13978 | ||
b99bd4ef | 13979 | static void |
c19d1205 | 13980 | do_t_strexd (void) |
b99bd4ef | 13981 | { |
c19d1205 ZW |
13982 | if (!inst.operands[2].present) |
13983 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 13984 | |
c19d1205 ZW |
13985 | constraint (inst.operands[0].reg == inst.operands[1].reg |
13986 | || inst.operands[0].reg == inst.operands[2].reg | |
f8a8e9d6 | 13987 | || inst.operands[0].reg == inst.operands[3].reg, |
c19d1205 | 13988 | BAD_OVERLAP); |
b99bd4ef | 13989 | |
c19d1205 ZW |
13990 | inst.instruction |= inst.operands[0].reg; |
13991 | inst.instruction |= inst.operands[1].reg << 12; | |
13992 | inst.instruction |= inst.operands[2].reg << 8; | |
13993 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
13994 | } |
13995 | ||
13996 | static void | |
c19d1205 | 13997 | do_t_sxtah (void) |
b99bd4ef | 13998 | { |
fdfde340 JM |
13999 | unsigned Rd, Rn, Rm; |
14000 | ||
14001 | Rd = inst.operands[0].reg; | |
14002 | Rn = inst.operands[1].reg; | |
14003 | Rm = inst.operands[2].reg; | |
14004 | ||
14005 | reject_bad_reg (Rd); | |
14006 | reject_bad_reg (Rn); | |
14007 | reject_bad_reg (Rm); | |
14008 | ||
14009 | inst.instruction |= Rd << 8; | |
14010 | inst.instruction |= Rn << 16; | |
14011 | inst.instruction |= Rm; | |
c19d1205 ZW |
14012 | inst.instruction |= inst.operands[3].imm << 4; |
14013 | } | |
b99bd4ef | 14014 | |
c19d1205 ZW |
14015 | static void |
14016 | do_t_sxth (void) | |
14017 | { | |
fdfde340 JM |
14018 | unsigned Rd, Rm; |
14019 | ||
14020 | Rd = inst.operands[0].reg; | |
14021 | Rm = inst.operands[1].reg; | |
14022 | ||
14023 | reject_bad_reg (Rd); | |
14024 | reject_bad_reg (Rm); | |
c921be7d NC |
14025 | |
14026 | if (inst.instruction <= 0xffff | |
14027 | && inst.size_req != 4 | |
fdfde340 | 14028 | && Rd <= 7 && Rm <= 7 |
c19d1205 | 14029 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) |
b99bd4ef | 14030 | { |
c19d1205 | 14031 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
14032 | inst.instruction |= Rd; |
14033 | inst.instruction |= Rm << 3; | |
b99bd4ef | 14034 | } |
c19d1205 | 14035 | else if (unified_syntax) |
b99bd4ef | 14036 | { |
c19d1205 ZW |
14037 | if (inst.instruction <= 0xffff) |
14038 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
14039 | inst.instruction |= Rd << 8; |
14040 | inst.instruction |= Rm; | |
c19d1205 | 14041 | inst.instruction |= inst.operands[2].imm << 4; |
b99bd4ef | 14042 | } |
c19d1205 | 14043 | else |
b99bd4ef | 14044 | { |
c19d1205 ZW |
14045 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
14046 | _("Thumb encoding does not support rotation")); | |
14047 | constraint (1, BAD_HIREG); | |
b99bd4ef | 14048 | } |
c19d1205 | 14049 | } |
b99bd4ef | 14050 | |
c19d1205 ZW |
14051 | static void |
14052 | do_t_swi (void) | |
14053 | { | |
e2b0ab59 | 14054 | inst.relocs[0].type = BFD_RELOC_ARM_SWI; |
c19d1205 | 14055 | } |
b99bd4ef | 14056 | |
92e90b6e PB |
14057 | static void |
14058 | do_t_tb (void) | |
14059 | { | |
fdfde340 | 14060 | unsigned Rn, Rm; |
92e90b6e PB |
14061 | int half; |
14062 | ||
14063 | half = (inst.instruction & 0x10) != 0; | |
5ee91343 | 14064 | set_pred_insn_type_last (); |
dfa9f0d5 PB |
14065 | constraint (inst.operands[0].immisreg, |
14066 | _("instruction requires register index")); | |
fdfde340 JM |
14067 | |
14068 | Rn = inst.operands[0].reg; | |
14069 | Rm = inst.operands[0].imm; | |
c921be7d | 14070 | |
5c8ed6a4 JW |
14071 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
14072 | constraint (Rn == REG_SP, BAD_SP); | |
fdfde340 JM |
14073 | reject_bad_reg (Rm); |
14074 | ||
92e90b6e PB |
14075 | constraint (!half && inst.operands[0].shifted, |
14076 | _("instruction does not allow shifted index")); | |
fdfde340 | 14077 | inst.instruction |= (Rn << 16) | Rm; |
92e90b6e PB |
14078 | } |
14079 | ||
74db7efb NC |
14080 | static void |
14081 | do_t_udf (void) | |
14082 | { | |
14083 | if (!inst.operands[0].present) | |
14084 | inst.operands[0].imm = 0; | |
14085 | ||
14086 | if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4) | |
14087 | { | |
14088 | constraint (inst.size_req == 2, | |
14089 | _("immediate value out of range")); | |
14090 | inst.instruction = THUMB_OP32 (inst.instruction); | |
14091 | inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4; | |
14092 | inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0; | |
14093 | } | |
14094 | else | |
14095 | { | |
14096 | inst.instruction = THUMB_OP16 (inst.instruction); | |
14097 | inst.instruction |= inst.operands[0].imm; | |
14098 | } | |
14099 | ||
5ee91343 | 14100 | set_pred_insn_type (NEUTRAL_IT_INSN); |
74db7efb NC |
14101 | } |
14102 | ||
14103 | ||
c19d1205 ZW |
14104 | static void |
14105 | do_t_usat (void) | |
14106 | { | |
3a21c15a | 14107 | do_t_ssat_usat (0); |
b99bd4ef NC |
14108 | } |
14109 | ||
14110 | static void | |
c19d1205 | 14111 | do_t_usat16 (void) |
b99bd4ef | 14112 | { |
fdfde340 JM |
14113 | unsigned Rd, Rn; |
14114 | ||
14115 | Rd = inst.operands[0].reg; | |
14116 | Rn = inst.operands[2].reg; | |
14117 | ||
14118 | reject_bad_reg (Rd); | |
14119 | reject_bad_reg (Rn); | |
14120 | ||
14121 | inst.instruction |= Rd << 8; | |
c19d1205 | 14122 | inst.instruction |= inst.operands[1].imm; |
fdfde340 | 14123 | inst.instruction |= Rn << 16; |
b99bd4ef | 14124 | } |
c19d1205 | 14125 | |
e12437dc AV |
14126 | /* Checking the range of the branch offset (VAL) with NBITS bits |
14127 | and IS_SIGNED signedness. Also checks the LSB to be 0. */ | |
14128 | static int | |
14129 | v8_1_branch_value_check (int val, int nbits, int is_signed) | |
14130 | { | |
14131 | gas_assert (nbits > 0 && nbits <= 32); | |
14132 | if (is_signed) | |
14133 | { | |
14134 | int cmp = (1 << (nbits - 1)); | |
14135 | if ((val < -cmp) || (val >= cmp) || (val & 0x01)) | |
14136 | return FAIL; | |
14137 | } | |
14138 | else | |
14139 | { | |
14140 | if ((val <= 0) || (val >= (1 << nbits)) || (val & 0x1)) | |
14141 | return FAIL; | |
14142 | } | |
14143 | return SUCCESS; | |
14144 | } | |
14145 | ||
4389b29a AV |
14146 | /* For branches in Armv8.1-M Mainline. */ |
14147 | static void | |
14148 | do_t_branch_future (void) | |
14149 | { | |
14150 | unsigned long insn = inst.instruction; | |
14151 | ||
14152 | inst.instruction = THUMB_OP32 (inst.instruction); | |
14153 | if (inst.operands[0].hasreloc == 0) | |
14154 | { | |
14155 | if (v8_1_branch_value_check (inst.operands[0].imm, 5, FALSE) == FAIL) | |
14156 | as_bad (BAD_BRANCH_OFF); | |
14157 | ||
14158 | inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23; | |
14159 | } | |
14160 | else | |
14161 | { | |
14162 | inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH5; | |
14163 | inst.relocs[0].pc_rel = 1; | |
14164 | } | |
14165 | ||
14166 | switch (insn) | |
14167 | { | |
14168 | case T_MNEM_bf: | |
14169 | if (inst.operands[1].hasreloc == 0) | |
14170 | { | |
14171 | int val = inst.operands[1].imm; | |
14172 | if (v8_1_branch_value_check (inst.operands[1].imm, 17, TRUE) == FAIL) | |
14173 | as_bad (BAD_BRANCH_OFF); | |
14174 | ||
14175 | int immA = (val & 0x0001f000) >> 12; | |
14176 | int immB = (val & 0x00000ffc) >> 2; | |
14177 | int immC = (val & 0x00000002) >> 1; | |
14178 | inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11); | |
14179 | } | |
14180 | else | |
14181 | { | |
14182 | inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF17; | |
14183 | inst.relocs[1].pc_rel = 1; | |
14184 | } | |
14185 | break; | |
14186 | ||
65d1bc05 AV |
14187 | case T_MNEM_bfl: |
14188 | if (inst.operands[1].hasreloc == 0) | |
14189 | { | |
14190 | int val = inst.operands[1].imm; | |
14191 | if (v8_1_branch_value_check (inst.operands[1].imm, 19, TRUE) == FAIL) | |
14192 | as_bad (BAD_BRANCH_OFF); | |
14193 | ||
14194 | int immA = (val & 0x0007f000) >> 12; | |
14195 | int immB = (val & 0x00000ffc) >> 2; | |
14196 | int immC = (val & 0x00000002) >> 1; | |
14197 | inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11); | |
14198 | } | |
14199 | else | |
14200 | { | |
14201 | inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF19; | |
14202 | inst.relocs[1].pc_rel = 1; | |
14203 | } | |
14204 | break; | |
14205 | ||
f6b2b12d AV |
14206 | case T_MNEM_bfcsel: |
14207 | /* Operand 1. */ | |
14208 | if (inst.operands[1].hasreloc == 0) | |
14209 | { | |
14210 | int val = inst.operands[1].imm; | |
14211 | int immA = (val & 0x00001000) >> 12; | |
14212 | int immB = (val & 0x00000ffc) >> 2; | |
14213 | int immC = (val & 0x00000002) >> 1; | |
14214 | inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11); | |
14215 | } | |
14216 | else | |
14217 | { | |
14218 | inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF13; | |
14219 | inst.relocs[1].pc_rel = 1; | |
14220 | } | |
14221 | ||
14222 | /* Operand 2. */ | |
14223 | if (inst.operands[2].hasreloc == 0) | |
14224 | { | |
14225 | constraint ((inst.operands[0].hasreloc != 0), BAD_ARGS); | |
14226 | int val2 = inst.operands[2].imm; | |
14227 | int val0 = inst.operands[0].imm & 0x1f; | |
14228 | int diff = val2 - val0; | |
14229 | if (diff == 4) | |
14230 | inst.instruction |= 1 << 17; /* T bit. */ | |
14231 | else if (diff != 2) | |
14232 | as_bad (_("out of range label-relative fixup value")); | |
14233 | } | |
14234 | else | |
14235 | { | |
14236 | constraint ((inst.operands[0].hasreloc == 0), BAD_ARGS); | |
14237 | inst.relocs[2].type = BFD_RELOC_THUMB_PCREL_BFCSEL; | |
14238 | inst.relocs[2].pc_rel = 1; | |
14239 | } | |
14240 | ||
14241 | /* Operand 3. */ | |
14242 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
14243 | inst.instruction |= (inst.operands[3].imm & 0xf) << 18; | |
14244 | break; | |
14245 | ||
f1c7f421 AV |
14246 | case T_MNEM_bfx: |
14247 | case T_MNEM_bflx: | |
14248 | inst.instruction |= inst.operands[1].reg << 16; | |
14249 | break; | |
14250 | ||
4389b29a AV |
14251 | default: abort (); |
14252 | } | |
14253 | } | |
14254 | ||
60f993ce AV |
14255 | /* Helper function for do_t_loloop to handle relocations. */ |
14256 | static void | |
14257 | v8_1_loop_reloc (int is_le) | |
14258 | { | |
14259 | if (inst.relocs[0].exp.X_op == O_constant) | |
14260 | { | |
14261 | int value = inst.relocs[0].exp.X_add_number; | |
14262 | value = (is_le) ? -value : value; | |
14263 | ||
14264 | if (v8_1_branch_value_check (value, 12, FALSE) == FAIL) | |
14265 | as_bad (BAD_BRANCH_OFF); | |
14266 | ||
14267 | int imml, immh; | |
14268 | ||
14269 | immh = (value & 0x00000ffc) >> 2; | |
14270 | imml = (value & 0x00000002) >> 1; | |
14271 | ||
14272 | inst.instruction |= (imml << 11) | (immh << 1); | |
14273 | } | |
14274 | else | |
14275 | { | |
14276 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_LOOP12; | |
14277 | inst.relocs[0].pc_rel = 1; | |
14278 | } | |
14279 | } | |
14280 | ||
23d00a41 SD |
14281 | /* For shifts in MVE. */ |
14282 | static void | |
14283 | do_mve_scalar_shift (void) | |
14284 | { | |
14285 | if (!inst.operands[2].present) | |
14286 | { | |
14287 | inst.operands[2] = inst.operands[1]; | |
14288 | inst.operands[1].reg = 0xf; | |
14289 | } | |
14290 | ||
14291 | inst.instruction |= inst.operands[0].reg << 16; | |
14292 | inst.instruction |= inst.operands[1].reg << 8; | |
14293 | ||
14294 | if (inst.operands[2].isreg) | |
14295 | { | |
14296 | /* Assuming Rm is already checked not to be 11x1. */ | |
14297 | constraint (inst.operands[2].reg == inst.operands[0].reg, BAD_OVERLAP); | |
14298 | constraint (inst.operands[2].reg == inst.operands[1].reg, BAD_OVERLAP); | |
14299 | inst.instruction |= inst.operands[2].reg << 12; | |
14300 | } | |
14301 | else | |
14302 | { | |
14303 | /* Assuming imm is already checked as [1,32]. */ | |
14304 | unsigned int value = inst.operands[2].imm; | |
14305 | inst.instruction |= (value & 0x1c) << 10; | |
14306 | inst.instruction |= (value & 0x03) << 6; | |
14307 | /* Change last 4 bits from 0xd to 0xf. */ | |
14308 | inst.instruction |= 0x2; | |
14309 | } | |
14310 | } | |
14311 | ||
a302e574 AV |
14312 | /* MVE instruction encoder helpers. */ |
14313 | #define M_MNEM_vabav 0xee800f01 | |
14314 | #define M_MNEM_vmladav 0xeef00e00 | |
14315 | #define M_MNEM_vmladava 0xeef00e20 | |
14316 | #define M_MNEM_vmladavx 0xeef01e00 | |
14317 | #define M_MNEM_vmladavax 0xeef01e20 | |
14318 | #define M_MNEM_vmlsdav 0xeef00e01 | |
14319 | #define M_MNEM_vmlsdava 0xeef00e21 | |
14320 | #define M_MNEM_vmlsdavx 0xeef01e01 | |
14321 | #define M_MNEM_vmlsdavax 0xeef01e21 | |
886e1c73 AV |
14322 | #define M_MNEM_vmullt 0xee011e00 |
14323 | #define M_MNEM_vmullb 0xee010e00 | |
35c228db AV |
14324 | #define M_MNEM_vst20 0xfc801e00 |
14325 | #define M_MNEM_vst21 0xfc801e20 | |
14326 | #define M_MNEM_vst40 0xfc801e01 | |
14327 | #define M_MNEM_vst41 0xfc801e21 | |
14328 | #define M_MNEM_vst42 0xfc801e41 | |
14329 | #define M_MNEM_vst43 0xfc801e61 | |
14330 | #define M_MNEM_vld20 0xfc901e00 | |
14331 | #define M_MNEM_vld21 0xfc901e20 | |
14332 | #define M_MNEM_vld40 0xfc901e01 | |
14333 | #define M_MNEM_vld41 0xfc901e21 | |
14334 | #define M_MNEM_vld42 0xfc901e41 | |
14335 | #define M_MNEM_vld43 0xfc901e61 | |
f5f10c66 AV |
14336 | #define M_MNEM_vstrb 0xec000e00 |
14337 | #define M_MNEM_vstrh 0xec000e10 | |
14338 | #define M_MNEM_vstrw 0xec000e40 | |
14339 | #define M_MNEM_vstrd 0xec000e50 | |
14340 | #define M_MNEM_vldrb 0xec100e00 | |
14341 | #define M_MNEM_vldrh 0xec100e10 | |
14342 | #define M_MNEM_vldrw 0xec100e40 | |
14343 | #define M_MNEM_vldrd 0xec100e50 | |
57785aa2 AV |
14344 | #define M_MNEM_vmovlt 0xeea01f40 |
14345 | #define M_MNEM_vmovlb 0xeea00f40 | |
14346 | #define M_MNEM_vmovnt 0xfe311e81 | |
14347 | #define M_MNEM_vmovnb 0xfe310e81 | |
c2dafc2a AV |
14348 | #define M_MNEM_vadc 0xee300f00 |
14349 | #define M_MNEM_vadci 0xee301f00 | |
14350 | #define M_MNEM_vbrsr 0xfe011e60 | |
26c1e780 AV |
14351 | #define M_MNEM_vaddlv 0xee890f00 |
14352 | #define M_MNEM_vaddlva 0xee890f20 | |
14353 | #define M_MNEM_vaddv 0xeef10f00 | |
14354 | #define M_MNEM_vaddva 0xeef10f20 | |
b409bdb6 AV |
14355 | #define M_MNEM_vddup 0xee011f6e |
14356 | #define M_MNEM_vdwdup 0xee011f60 | |
14357 | #define M_MNEM_vidup 0xee010f6e | |
14358 | #define M_MNEM_viwdup 0xee010f60 | |
13ccd4c0 AV |
14359 | #define M_MNEM_vmaxv 0xeee20f00 |
14360 | #define M_MNEM_vmaxav 0xeee00f00 | |
14361 | #define M_MNEM_vminv 0xeee20f80 | |
14362 | #define M_MNEM_vminav 0xeee00f80 | |
93925576 AV |
14363 | #define M_MNEM_vmlaldav 0xee800e00 |
14364 | #define M_MNEM_vmlaldava 0xee800e20 | |
14365 | #define M_MNEM_vmlaldavx 0xee801e00 | |
14366 | #define M_MNEM_vmlaldavax 0xee801e20 | |
14367 | #define M_MNEM_vmlsldav 0xee800e01 | |
14368 | #define M_MNEM_vmlsldava 0xee800e21 | |
14369 | #define M_MNEM_vmlsldavx 0xee801e01 | |
14370 | #define M_MNEM_vmlsldavax 0xee801e21 | |
14371 | #define M_MNEM_vrmlaldavhx 0xee801f00 | |
14372 | #define M_MNEM_vrmlaldavhax 0xee801f20 | |
14373 | #define M_MNEM_vrmlsldavh 0xfe800e01 | |
14374 | #define M_MNEM_vrmlsldavha 0xfe800e21 | |
14375 | #define M_MNEM_vrmlsldavhx 0xfe801e01 | |
14376 | #define M_MNEM_vrmlsldavhax 0xfe801e21 | |
1be7aba3 AV |
14377 | #define M_MNEM_vqmovnt 0xee331e01 |
14378 | #define M_MNEM_vqmovnb 0xee330e01 | |
14379 | #define M_MNEM_vqmovunt 0xee311e81 | |
14380 | #define M_MNEM_vqmovunb 0xee310e81 | |
4aa88b50 AV |
14381 | #define M_MNEM_vshrnt 0xee801fc1 |
14382 | #define M_MNEM_vshrnb 0xee800fc1 | |
14383 | #define M_MNEM_vrshrnt 0xfe801fc1 | |
14384 | #define M_MNEM_vqshrnt 0xee801f40 | |
14385 | #define M_MNEM_vqshrnb 0xee800f40 | |
14386 | #define M_MNEM_vqshrunt 0xee801fc0 | |
14387 | #define M_MNEM_vqshrunb 0xee800fc0 | |
14388 | #define M_MNEM_vrshrnb 0xfe800fc1 | |
14389 | #define M_MNEM_vqrshrnt 0xee801f41 | |
14390 | #define M_MNEM_vqrshrnb 0xee800f41 | |
14391 | #define M_MNEM_vqrshrunt 0xfe801fc0 | |
14392 | #define M_MNEM_vqrshrunb 0xfe800fc0 | |
a302e574 | 14393 | |
5287ad62 | 14394 | /* Neon instruction encoder helpers. */ |
5f4273c7 | 14395 | |
5287ad62 | 14396 | /* Encodings for the different types for various Neon opcodes. */ |
b99bd4ef | 14397 | |
5287ad62 JB |
14398 | /* An "invalid" code for the following tables. */ |
14399 | #define N_INV -1u | |
14400 | ||
14401 | struct neon_tab_entry | |
b99bd4ef | 14402 | { |
5287ad62 JB |
14403 | unsigned integer; |
14404 | unsigned float_or_poly; | |
14405 | unsigned scalar_or_imm; | |
14406 | }; | |
5f4273c7 | 14407 | |
5287ad62 JB |
14408 | /* Map overloaded Neon opcodes to their respective encodings. */ |
14409 | #define NEON_ENC_TAB \ | |
14410 | X(vabd, 0x0000700, 0x1200d00, N_INV), \ | |
5ee91343 | 14411 | X(vabdl, 0x0800700, N_INV, N_INV), \ |
5287ad62 JB |
14412 | X(vmax, 0x0000600, 0x0000f00, N_INV), \ |
14413 | X(vmin, 0x0000610, 0x0200f00, N_INV), \ | |
14414 | X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ | |
14415 | X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ | |
14416 | X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ | |
14417 | X(vadd, 0x0000800, 0x0000d00, N_INV), \ | |
5ee91343 | 14418 | X(vaddl, 0x0800000, N_INV, N_INV), \ |
5287ad62 | 14419 | X(vsub, 0x1000800, 0x0200d00, N_INV), \ |
5ee91343 | 14420 | X(vsubl, 0x0800200, N_INV, N_INV), \ |
5287ad62 JB |
14421 | X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ |
14422 | X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ | |
14423 | X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ | |
14424 | /* Register variants of the following two instructions are encoded as | |
e07e6e58 | 14425 | vcge / vcgt with the operands reversed. */ \ |
92559b5b PB |
14426 | X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ |
14427 | X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ | |
62f3b8c8 PB |
14428 | X(vfma, N_INV, 0x0000c10, N_INV), \ |
14429 | X(vfms, N_INV, 0x0200c10, N_INV), \ | |
5287ad62 JB |
14430 | X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ |
14431 | X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ | |
14432 | X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ | |
14433 | X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ | |
14434 | X(vmlal, 0x0800800, N_INV, 0x0800240), \ | |
14435 | X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ | |
14436 | X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ | |
14437 | X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ | |
14438 | X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ | |
14439 | X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ | |
14440 | X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ | |
d6b4b13e MW |
14441 | X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \ |
14442 | X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \ | |
5287ad62 JB |
14443 | X(vshl, 0x0000400, N_INV, 0x0800510), \ |
14444 | X(vqshl, 0x0000410, N_INV, 0x0800710), \ | |
14445 | X(vand, 0x0000110, N_INV, 0x0800030), \ | |
14446 | X(vbic, 0x0100110, N_INV, 0x0800030), \ | |
14447 | X(veor, 0x1000110, N_INV, N_INV), \ | |
14448 | X(vorn, 0x0300110, N_INV, 0x0800010), \ | |
14449 | X(vorr, 0x0200110, N_INV, 0x0800010), \ | |
14450 | X(vmvn, 0x1b00580, N_INV, 0x0800030), \ | |
14451 | X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ | |
14452 | X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ | |
14453 | X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ | |
14454 | X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ | |
14455 | X(vst1, 0x0000000, 0x0800000, N_INV), \ | |
14456 | X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ | |
14457 | X(vst2, 0x0000100, 0x0800100, N_INV), \ | |
14458 | X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ | |
14459 | X(vst3, 0x0000200, 0x0800200, N_INV), \ | |
14460 | X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ | |
14461 | X(vst4, 0x0000300, 0x0800300, N_INV), \ | |
14462 | X(vmovn, 0x1b20200, N_INV, N_INV), \ | |
14463 | X(vtrn, 0x1b20080, N_INV, N_INV), \ | |
14464 | X(vqmovn, 0x1b20200, N_INV, N_INV), \ | |
037e8744 JB |
14465 | X(vqmovun, 0x1b20240, N_INV, N_INV), \ |
14466 | X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ | |
e6655fda PB |
14467 | X(vnmla, 0xe100a40, 0xe100b40, N_INV), \ |
14468 | X(vnmls, 0xe100a00, 0xe100b00, N_INV), \ | |
62f3b8c8 PB |
14469 | X(vfnma, 0xe900a40, 0xe900b40, N_INV), \ |
14470 | X(vfnms, 0xe900a00, 0xe900b00, N_INV), \ | |
037e8744 JB |
14471 | X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ |
14472 | X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ | |
14473 | X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ | |
33399f07 MGD |
14474 | X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \ |
14475 | X(vseleq, 0xe000a00, N_INV, N_INV), \ | |
14476 | X(vselvs, 0xe100a00, N_INV, N_INV), \ | |
14477 | X(vselge, 0xe200a00, N_INV, N_INV), \ | |
73924fbc MGD |
14478 | X(vselgt, 0xe300a00, N_INV, N_INV), \ |
14479 | X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \ | |
7e8e6784 | 14480 | X(vminnm, 0xe800a40, 0x3200f10, N_INV), \ |
30bdf752 MGD |
14481 | X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \ |
14482 | X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \ | |
91ff7894 | 14483 | X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \ |
48adcd8e | 14484 | X(aes, 0x3b00300, N_INV, N_INV), \ |
3c9017d2 MGD |
14485 | X(sha3op, 0x2000c00, N_INV, N_INV), \ |
14486 | X(sha1h, 0x3b902c0, N_INV, N_INV), \ | |
14487 | X(sha2op, 0x3ba0380, N_INV, N_INV) | |
5287ad62 JB |
14488 | |
14489 | enum neon_opc | |
14490 | { | |
14491 | #define X(OPC,I,F,S) N_MNEM_##OPC | |
14492 | NEON_ENC_TAB | |
14493 | #undef X | |
14494 | }; | |
b99bd4ef | 14495 | |
5287ad62 JB |
14496 | static const struct neon_tab_entry neon_enc_tab[] = |
14497 | { | |
14498 | #define X(OPC,I,F,S) { (I), (F), (S) } | |
14499 | NEON_ENC_TAB | |
14500 | #undef X | |
14501 | }; | |
b99bd4ef | 14502 | |
88714cb8 DG |
14503 | /* Do not use these macros; instead, use NEON_ENCODE defined below. */ |
14504 | #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
14505 | #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
14506 | #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
14507 | #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
14508 | #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
14509 | #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
14510 | #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
14511 | #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
14512 | #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
14513 | #define NEON_ENC_SINGLE_(X) \ | |
037e8744 | 14514 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) |
88714cb8 | 14515 | #define NEON_ENC_DOUBLE_(X) \ |
037e8744 | 14516 | ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) |
33399f07 MGD |
14517 | #define NEON_ENC_FPV8_(X) \ |
14518 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000)) | |
5287ad62 | 14519 | |
88714cb8 DG |
14520 | #define NEON_ENCODE(type, inst) \ |
14521 | do \ | |
14522 | { \ | |
14523 | inst.instruction = NEON_ENC_##type##_ (inst.instruction); \ | |
14524 | inst.is_neon = 1; \ | |
14525 | } \ | |
14526 | while (0) | |
14527 | ||
14528 | #define check_neon_suffixes \ | |
14529 | do \ | |
14530 | { \ | |
14531 | if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \ | |
14532 | { \ | |
14533 | as_bad (_("invalid neon suffix for non neon instruction")); \ | |
14534 | return; \ | |
14535 | } \ | |
14536 | } \ | |
14537 | while (0) | |
14538 | ||
037e8744 JB |
14539 | /* Define shapes for instruction operands. The following mnemonic characters |
14540 | are used in this table: | |
5287ad62 | 14541 | |
037e8744 | 14542 | F - VFP S<n> register |
5287ad62 JB |
14543 | D - Neon D<n> register |
14544 | Q - Neon Q<n> register | |
14545 | I - Immediate | |
14546 | S - Scalar | |
14547 | R - ARM register | |
14548 | L - D<n> register list | |
5f4273c7 | 14549 | |
037e8744 JB |
14550 | This table is used to generate various data: |
14551 | - enumerations of the form NS_DDR to be used as arguments to | |
14552 | neon_select_shape. | |
14553 | - a table classifying shapes into single, double, quad, mixed. | |
5f4273c7 | 14554 | - a table used to drive neon_select_shape. */ |
b99bd4ef | 14555 | |
037e8744 | 14556 | #define NEON_SHAPE_DEF \ |
93925576 | 14557 | X(4, (R, R, Q, Q), QUAD), \ |
b409bdb6 | 14558 | X(4, (Q, R, R, I), QUAD), \ |
57785aa2 AV |
14559 | X(4, (R, R, S, S), QUAD), \ |
14560 | X(4, (S, S, R, R), QUAD), \ | |
b409bdb6 | 14561 | X(3, (Q, R, I), QUAD), \ |
1b883319 AV |
14562 | X(3, (I, Q, Q), QUAD), \ |
14563 | X(3, (I, Q, R), QUAD), \ | |
a302e574 | 14564 | X(3, (R, Q, Q), QUAD), \ |
037e8744 JB |
14565 | X(3, (D, D, D), DOUBLE), \ |
14566 | X(3, (Q, Q, Q), QUAD), \ | |
14567 | X(3, (D, D, I), DOUBLE), \ | |
14568 | X(3, (Q, Q, I), QUAD), \ | |
14569 | X(3, (D, D, S), DOUBLE), \ | |
14570 | X(3, (Q, Q, S), QUAD), \ | |
5ee91343 | 14571 | X(3, (Q, Q, R), QUAD), \ |
26c1e780 AV |
14572 | X(3, (R, R, Q), QUAD), \ |
14573 | X(2, (R, Q), QUAD), \ | |
037e8744 JB |
14574 | X(2, (D, D), DOUBLE), \ |
14575 | X(2, (Q, Q), QUAD), \ | |
14576 | X(2, (D, S), DOUBLE), \ | |
14577 | X(2, (Q, S), QUAD), \ | |
14578 | X(2, (D, R), DOUBLE), \ | |
14579 | X(2, (Q, R), QUAD), \ | |
14580 | X(2, (D, I), DOUBLE), \ | |
14581 | X(2, (Q, I), QUAD), \ | |
14582 | X(3, (D, L, D), DOUBLE), \ | |
14583 | X(2, (D, Q), MIXED), \ | |
14584 | X(2, (Q, D), MIXED), \ | |
14585 | X(3, (D, Q, I), MIXED), \ | |
14586 | X(3, (Q, D, I), MIXED), \ | |
14587 | X(3, (Q, D, D), MIXED), \ | |
14588 | X(3, (D, Q, Q), MIXED), \ | |
14589 | X(3, (Q, Q, D), MIXED), \ | |
14590 | X(3, (Q, D, S), MIXED), \ | |
14591 | X(3, (D, Q, S), MIXED), \ | |
14592 | X(4, (D, D, D, I), DOUBLE), \ | |
14593 | X(4, (Q, Q, Q, I), QUAD), \ | |
c28eeff2 SN |
14594 | X(4, (D, D, S, I), DOUBLE), \ |
14595 | X(4, (Q, Q, S, I), QUAD), \ | |
037e8744 JB |
14596 | X(2, (F, F), SINGLE), \ |
14597 | X(3, (F, F, F), SINGLE), \ | |
14598 | X(2, (F, I), SINGLE), \ | |
14599 | X(2, (F, D), MIXED), \ | |
14600 | X(2, (D, F), MIXED), \ | |
14601 | X(3, (F, F, I), MIXED), \ | |
14602 | X(4, (R, R, F, F), SINGLE), \ | |
14603 | X(4, (F, F, R, R), SINGLE), \ | |
14604 | X(3, (D, R, R), DOUBLE), \ | |
14605 | X(3, (R, R, D), DOUBLE), \ | |
14606 | X(2, (S, R), SINGLE), \ | |
14607 | X(2, (R, S), SINGLE), \ | |
14608 | X(2, (F, R), SINGLE), \ | |
d54af2d0 | 14609 | X(2, (R, F), SINGLE), \ |
1f6234a3 AV |
14610 | /* Used for MVE tail predicated loop instructions. */\ |
14611 | X(2, (R, R), QUAD), \ | |
d54af2d0 RL |
14612 | /* Half float shape supported so far. */\ |
14613 | X (2, (H, D), MIXED), \ | |
14614 | X (2, (D, H), MIXED), \ | |
14615 | X (2, (H, F), MIXED), \ | |
14616 | X (2, (F, H), MIXED), \ | |
14617 | X (2, (H, H), HALF), \ | |
14618 | X (2, (H, R), HALF), \ | |
14619 | X (2, (R, H), HALF), \ | |
14620 | X (2, (H, I), HALF), \ | |
14621 | X (3, (H, H, H), HALF), \ | |
14622 | X (3, (H, F, I), MIXED), \ | |
dec41383 JW |
14623 | X (3, (F, H, I), MIXED), \ |
14624 | X (3, (D, H, H), MIXED), \ | |
14625 | X (3, (D, H, S), MIXED) | |
037e8744 JB |
14626 | |
14627 | #define S2(A,B) NS_##A##B | |
14628 | #define S3(A,B,C) NS_##A##B##C | |
14629 | #define S4(A,B,C,D) NS_##A##B##C##D | |
14630 | ||
14631 | #define X(N, L, C) S##N L | |
14632 | ||
5287ad62 JB |
14633 | enum neon_shape |
14634 | { | |
037e8744 JB |
14635 | NEON_SHAPE_DEF, |
14636 | NS_NULL | |
5287ad62 | 14637 | }; |
b99bd4ef | 14638 | |
037e8744 JB |
14639 | #undef X |
14640 | #undef S2 | |
14641 | #undef S3 | |
14642 | #undef S4 | |
14643 | ||
14644 | enum neon_shape_class | |
14645 | { | |
d54af2d0 | 14646 | SC_HALF, |
037e8744 JB |
14647 | SC_SINGLE, |
14648 | SC_DOUBLE, | |
14649 | SC_QUAD, | |
14650 | SC_MIXED | |
14651 | }; | |
14652 | ||
14653 | #define X(N, L, C) SC_##C | |
14654 | ||
14655 | static enum neon_shape_class neon_shape_class[] = | |
14656 | { | |
14657 | NEON_SHAPE_DEF | |
14658 | }; | |
14659 | ||
14660 | #undef X | |
14661 | ||
14662 | enum neon_shape_el | |
14663 | { | |
d54af2d0 | 14664 | SE_H, |
037e8744 JB |
14665 | SE_F, |
14666 | SE_D, | |
14667 | SE_Q, | |
14668 | SE_I, | |
14669 | SE_S, | |
14670 | SE_R, | |
14671 | SE_L | |
14672 | }; | |
14673 | ||
14674 | /* Register widths of above. */ | |
14675 | static unsigned neon_shape_el_size[] = | |
14676 | { | |
d54af2d0 | 14677 | 16, |
037e8744 JB |
14678 | 32, |
14679 | 64, | |
14680 | 128, | |
14681 | 0, | |
14682 | 32, | |
14683 | 32, | |
14684 | 0 | |
14685 | }; | |
14686 | ||
14687 | struct neon_shape_info | |
14688 | { | |
14689 | unsigned els; | |
14690 | enum neon_shape_el el[NEON_MAX_TYPE_ELS]; | |
14691 | }; | |
14692 | ||
14693 | #define S2(A,B) { SE_##A, SE_##B } | |
14694 | #define S3(A,B,C) { SE_##A, SE_##B, SE_##C } | |
14695 | #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } | |
14696 | ||
14697 | #define X(N, L, C) { N, S##N L } | |
14698 | ||
14699 | static struct neon_shape_info neon_shape_tab[] = | |
14700 | { | |
14701 | NEON_SHAPE_DEF | |
14702 | }; | |
14703 | ||
14704 | #undef X | |
14705 | #undef S2 | |
14706 | #undef S3 | |
14707 | #undef S4 | |
14708 | ||
5287ad62 JB |
14709 | /* Bit masks used in type checking given instructions. |
14710 | 'N_EQK' means the type must be the same as (or based on in some way) the key | |
14711 | type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is | |
14712 | set, various other bits can be set as well in order to modify the meaning of | |
14713 | the type constraint. */ | |
14714 | ||
14715 | enum neon_type_mask | |
14716 | { | |
8e79c3df CM |
14717 | N_S8 = 0x0000001, |
14718 | N_S16 = 0x0000002, | |
14719 | N_S32 = 0x0000004, | |
14720 | N_S64 = 0x0000008, | |
14721 | N_U8 = 0x0000010, | |
14722 | N_U16 = 0x0000020, | |
14723 | N_U32 = 0x0000040, | |
14724 | N_U64 = 0x0000080, | |
14725 | N_I8 = 0x0000100, | |
14726 | N_I16 = 0x0000200, | |
14727 | N_I32 = 0x0000400, | |
14728 | N_I64 = 0x0000800, | |
14729 | N_8 = 0x0001000, | |
14730 | N_16 = 0x0002000, | |
14731 | N_32 = 0x0004000, | |
14732 | N_64 = 0x0008000, | |
14733 | N_P8 = 0x0010000, | |
14734 | N_P16 = 0x0020000, | |
14735 | N_F16 = 0x0040000, | |
14736 | N_F32 = 0x0080000, | |
14737 | N_F64 = 0x0100000, | |
4f51b4bd | 14738 | N_P64 = 0x0200000, |
c921be7d NC |
14739 | N_KEY = 0x1000000, /* Key element (main type specifier). */ |
14740 | N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */ | |
8e79c3df | 14741 | N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ |
91ff7894 | 14742 | N_UNT = 0x8000000, /* Must be explicitly untyped. */ |
c921be7d NC |
14743 | N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */ |
14744 | N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */ | |
14745 | N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */ | |
14746 | N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */ | |
14747 | N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */ | |
14748 | N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */ | |
14749 | N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */ | |
5287ad62 | 14750 | N_UTYP = 0, |
4f51b4bd | 14751 | N_MAX_NONSPECIAL = N_P64 |
5287ad62 JB |
14752 | }; |
14753 | ||
dcbf9037 JB |
14754 | #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) |
14755 | ||
5287ad62 JB |
14756 | #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) |
14757 | #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) | |
14758 | #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) | |
cc933301 JW |
14759 | #define N_S_32 (N_S8 | N_S16 | N_S32) |
14760 | #define N_F_16_32 (N_F16 | N_F32) | |
14761 | #define N_SUF_32 (N_SU_32 | N_F_16_32) | |
5287ad62 | 14762 | #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) |
cc933301 | 14763 | #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32) |
d54af2d0 | 14764 | #define N_F_ALL (N_F16 | N_F32 | N_F64) |
5ee91343 AV |
14765 | #define N_I_MVE (N_I8 | N_I16 | N_I32) |
14766 | #define N_F_MVE (N_F16 | N_F32) | |
14767 | #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) | |
5287ad62 JB |
14768 | |
14769 | /* Pass this as the first type argument to neon_check_type to ignore types | |
14770 | altogether. */ | |
14771 | #define N_IGNORE_TYPE (N_KEY | N_EQK) | |
14772 | ||
037e8744 JB |
14773 | /* Select a "shape" for the current instruction (describing register types or |
14774 | sizes) from a list of alternatives. Return NS_NULL if the current instruction | |
14775 | doesn't fit. For non-polymorphic shapes, checking is usually done as a | |
14776 | function of operand parsing, so this function doesn't need to be called. | |
14777 | Shapes should be listed in order of decreasing length. */ | |
5287ad62 JB |
14778 | |
14779 | static enum neon_shape | |
037e8744 | 14780 | neon_select_shape (enum neon_shape shape, ...) |
5287ad62 | 14781 | { |
037e8744 JB |
14782 | va_list ap; |
14783 | enum neon_shape first_shape = shape; | |
5287ad62 JB |
14784 | |
14785 | /* Fix missing optional operands. FIXME: we don't know at this point how | |
14786 | many arguments we should have, so this makes the assumption that we have | |
14787 | > 1. This is true of all current Neon opcodes, I think, but may not be | |
14788 | true in the future. */ | |
14789 | if (!inst.operands[1].present) | |
14790 | inst.operands[1] = inst.operands[0]; | |
14791 | ||
037e8744 | 14792 | va_start (ap, shape); |
5f4273c7 | 14793 | |
21d799b5 | 14794 | for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int)) |
037e8744 JB |
14795 | { |
14796 | unsigned j; | |
14797 | int matches = 1; | |
14798 | ||
14799 | for (j = 0; j < neon_shape_tab[shape].els; j++) | |
477330fc RM |
14800 | { |
14801 | if (!inst.operands[j].present) | |
14802 | { | |
14803 | matches = 0; | |
14804 | break; | |
14805 | } | |
14806 | ||
14807 | switch (neon_shape_tab[shape].el[j]) | |
14808 | { | |
d54af2d0 RL |
14809 | /* If a .f16, .16, .u16, .s16 type specifier is given over |
14810 | a VFP single precision register operand, it's essentially | |
14811 | means only half of the register is used. | |
14812 | ||
14813 | If the type specifier is given after the mnemonics, the | |
14814 | information is stored in inst.vectype. If the type specifier | |
14815 | is given after register operand, the information is stored | |
14816 | in inst.operands[].vectype. | |
14817 | ||
14818 | When there is only one type specifier, and all the register | |
14819 | operands are the same type of hardware register, the type | |
14820 | specifier applies to all register operands. | |
14821 | ||
14822 | If no type specifier is given, the shape is inferred from | |
14823 | operand information. | |
14824 | ||
14825 | for example: | |
14826 | vadd.f16 s0, s1, s2: NS_HHH | |
14827 | vabs.f16 s0, s1: NS_HH | |
14828 | vmov.f16 s0, r1: NS_HR | |
14829 | vmov.f16 r0, s1: NS_RH | |
14830 | vcvt.f16 r0, s1: NS_RH | |
14831 | vcvt.f16.s32 s2, s2, #29: NS_HFI | |
14832 | vcvt.f16.s32 s2, s2: NS_HF | |
14833 | */ | |
14834 | case SE_H: | |
14835 | if (!(inst.operands[j].isreg | |
14836 | && inst.operands[j].isvec | |
14837 | && inst.operands[j].issingle | |
14838 | && !inst.operands[j].isquad | |
14839 | && ((inst.vectype.elems == 1 | |
14840 | && inst.vectype.el[0].size == 16) | |
14841 | || (inst.vectype.elems > 1 | |
14842 | && inst.vectype.el[j].size == 16) | |
14843 | || (inst.vectype.elems == 0 | |
14844 | && inst.operands[j].vectype.type != NT_invtype | |
14845 | && inst.operands[j].vectype.size == 16)))) | |
14846 | matches = 0; | |
14847 | break; | |
14848 | ||
477330fc RM |
14849 | case SE_F: |
14850 | if (!(inst.operands[j].isreg | |
14851 | && inst.operands[j].isvec | |
14852 | && inst.operands[j].issingle | |
d54af2d0 RL |
14853 | && !inst.operands[j].isquad |
14854 | && ((inst.vectype.elems == 1 && inst.vectype.el[0].size == 32) | |
14855 | || (inst.vectype.elems > 1 && inst.vectype.el[j].size == 32) | |
14856 | || (inst.vectype.elems == 0 | |
14857 | && (inst.operands[j].vectype.size == 32 | |
14858 | || inst.operands[j].vectype.type == NT_invtype))))) | |
477330fc RM |
14859 | matches = 0; |
14860 | break; | |
14861 | ||
14862 | case SE_D: | |
14863 | if (!(inst.operands[j].isreg | |
14864 | && inst.operands[j].isvec | |
14865 | && !inst.operands[j].isquad | |
14866 | && !inst.operands[j].issingle)) | |
14867 | matches = 0; | |
14868 | break; | |
14869 | ||
14870 | case SE_R: | |
14871 | if (!(inst.operands[j].isreg | |
14872 | && !inst.operands[j].isvec)) | |
14873 | matches = 0; | |
14874 | break; | |
14875 | ||
14876 | case SE_Q: | |
14877 | if (!(inst.operands[j].isreg | |
14878 | && inst.operands[j].isvec | |
14879 | && inst.operands[j].isquad | |
14880 | && !inst.operands[j].issingle)) | |
14881 | matches = 0; | |
14882 | break; | |
14883 | ||
14884 | case SE_I: | |
14885 | if (!(!inst.operands[j].isreg | |
14886 | && !inst.operands[j].isscalar)) | |
14887 | matches = 0; | |
14888 | break; | |
14889 | ||
14890 | case SE_S: | |
14891 | if (!(!inst.operands[j].isreg | |
14892 | && inst.operands[j].isscalar)) | |
14893 | matches = 0; | |
14894 | break; | |
14895 | ||
14896 | case SE_L: | |
14897 | break; | |
14898 | } | |
3fde54a2 JZ |
14899 | if (!matches) |
14900 | break; | |
477330fc | 14901 | } |
ad6cec43 MGD |
14902 | if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present)) |
14903 | /* We've matched all the entries in the shape table, and we don't | |
14904 | have any left over operands which have not been matched. */ | |
477330fc | 14905 | break; |
037e8744 | 14906 | } |
5f4273c7 | 14907 | |
037e8744 | 14908 | va_end (ap); |
5287ad62 | 14909 | |
037e8744 JB |
14910 | if (shape == NS_NULL && first_shape != NS_NULL) |
14911 | first_error (_("invalid instruction shape")); | |
5287ad62 | 14912 | |
037e8744 JB |
14913 | return shape; |
14914 | } | |
5287ad62 | 14915 | |
037e8744 JB |
14916 | /* True if SHAPE is predominantly a quadword operation (most of the time, this |
14917 | means the Q bit should be set). */ | |
14918 | ||
14919 | static int | |
14920 | neon_quad (enum neon_shape shape) | |
14921 | { | |
14922 | return neon_shape_class[shape] == SC_QUAD; | |
5287ad62 | 14923 | } |
037e8744 | 14924 | |
5287ad62 JB |
14925 | static void |
14926 | neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, | |
477330fc | 14927 | unsigned *g_size) |
5287ad62 JB |
14928 | { |
14929 | /* Allow modification to be made to types which are constrained to be | |
14930 | based on the key element, based on bits set alongside N_EQK. */ | |
14931 | if ((typebits & N_EQK) != 0) | |
14932 | { | |
14933 | if ((typebits & N_HLF) != 0) | |
14934 | *g_size /= 2; | |
14935 | else if ((typebits & N_DBL) != 0) | |
14936 | *g_size *= 2; | |
14937 | if ((typebits & N_SGN) != 0) | |
14938 | *g_type = NT_signed; | |
14939 | else if ((typebits & N_UNS) != 0) | |
477330fc | 14940 | *g_type = NT_unsigned; |
5287ad62 | 14941 | else if ((typebits & N_INT) != 0) |
477330fc | 14942 | *g_type = NT_integer; |
5287ad62 | 14943 | else if ((typebits & N_FLT) != 0) |
477330fc | 14944 | *g_type = NT_float; |
dcbf9037 | 14945 | else if ((typebits & N_SIZ) != 0) |
477330fc | 14946 | *g_type = NT_untyped; |
5287ad62 JB |
14947 | } |
14948 | } | |
5f4273c7 | 14949 | |
5287ad62 JB |
14950 | /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" |
14951 | operand type, i.e. the single type specified in a Neon instruction when it | |
14952 | is the only one given. */ | |
14953 | ||
14954 | static struct neon_type_el | |
14955 | neon_type_promote (struct neon_type_el *key, unsigned thisarg) | |
14956 | { | |
14957 | struct neon_type_el dest = *key; | |
5f4273c7 | 14958 | |
9c2799c2 | 14959 | gas_assert ((thisarg & N_EQK) != 0); |
5f4273c7 | 14960 | |
5287ad62 JB |
14961 | neon_modify_type_size (thisarg, &dest.type, &dest.size); |
14962 | ||
14963 | return dest; | |
14964 | } | |
14965 | ||
14966 | /* Convert Neon type and size into compact bitmask representation. */ | |
14967 | ||
14968 | static enum neon_type_mask | |
14969 | type_chk_of_el_type (enum neon_el_type type, unsigned size) | |
14970 | { | |
14971 | switch (type) | |
14972 | { | |
14973 | case NT_untyped: | |
14974 | switch (size) | |
477330fc RM |
14975 | { |
14976 | case 8: return N_8; | |
14977 | case 16: return N_16; | |
14978 | case 32: return N_32; | |
14979 | case 64: return N_64; | |
14980 | default: ; | |
14981 | } | |
5287ad62 JB |
14982 | break; |
14983 | ||
14984 | case NT_integer: | |
14985 | switch (size) | |
477330fc RM |
14986 | { |
14987 | case 8: return N_I8; | |
14988 | case 16: return N_I16; | |
14989 | case 32: return N_I32; | |
14990 | case 64: return N_I64; | |
14991 | default: ; | |
14992 | } | |
5287ad62 JB |
14993 | break; |
14994 | ||
14995 | case NT_float: | |
037e8744 | 14996 | switch (size) |
477330fc | 14997 | { |
8e79c3df | 14998 | case 16: return N_F16; |
477330fc RM |
14999 | case 32: return N_F32; |
15000 | case 64: return N_F64; | |
15001 | default: ; | |
15002 | } | |
5287ad62 JB |
15003 | break; |
15004 | ||
15005 | case NT_poly: | |
15006 | switch (size) | |
477330fc RM |
15007 | { |
15008 | case 8: return N_P8; | |
15009 | case 16: return N_P16; | |
4f51b4bd | 15010 | case 64: return N_P64; |
477330fc RM |
15011 | default: ; |
15012 | } | |
5287ad62 JB |
15013 | break; |
15014 | ||
15015 | case NT_signed: | |
15016 | switch (size) | |
477330fc RM |
15017 | { |
15018 | case 8: return N_S8; | |
15019 | case 16: return N_S16; | |
15020 | case 32: return N_S32; | |
15021 | case 64: return N_S64; | |
15022 | default: ; | |
15023 | } | |
5287ad62 JB |
15024 | break; |
15025 | ||
15026 | case NT_unsigned: | |
15027 | switch (size) | |
477330fc RM |
15028 | { |
15029 | case 8: return N_U8; | |
15030 | case 16: return N_U16; | |
15031 | case 32: return N_U32; | |
15032 | case 64: return N_U64; | |
15033 | default: ; | |
15034 | } | |
5287ad62 JB |
15035 | break; |
15036 | ||
15037 | default: ; | |
15038 | } | |
5f4273c7 | 15039 | |
5287ad62 JB |
15040 | return N_UTYP; |
15041 | } | |
15042 | ||
15043 | /* Convert compact Neon bitmask type representation to a type and size. Only | |
15044 | handles the case where a single bit is set in the mask. */ | |
15045 | ||
dcbf9037 | 15046 | static int |
5287ad62 | 15047 | el_type_of_type_chk (enum neon_el_type *type, unsigned *size, |
477330fc | 15048 | enum neon_type_mask mask) |
5287ad62 | 15049 | { |
dcbf9037 JB |
15050 | if ((mask & N_EQK) != 0) |
15051 | return FAIL; | |
15052 | ||
5287ad62 JB |
15053 | if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) |
15054 | *size = 8; | |
c70a8987 | 15055 | else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0) |
5287ad62 | 15056 | *size = 16; |
dcbf9037 | 15057 | else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) |
5287ad62 | 15058 | *size = 32; |
4f51b4bd | 15059 | else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0) |
5287ad62 | 15060 | *size = 64; |
dcbf9037 JB |
15061 | else |
15062 | return FAIL; | |
15063 | ||
5287ad62 JB |
15064 | if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) |
15065 | *type = NT_signed; | |
dcbf9037 | 15066 | else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) |
5287ad62 | 15067 | *type = NT_unsigned; |
dcbf9037 | 15068 | else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) |
5287ad62 | 15069 | *type = NT_integer; |
dcbf9037 | 15070 | else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) |
5287ad62 | 15071 | *type = NT_untyped; |
4f51b4bd | 15072 | else if ((mask & (N_P8 | N_P16 | N_P64)) != 0) |
5287ad62 | 15073 | *type = NT_poly; |
d54af2d0 | 15074 | else if ((mask & (N_F_ALL)) != 0) |
5287ad62 | 15075 | *type = NT_float; |
dcbf9037 JB |
15076 | else |
15077 | return FAIL; | |
5f4273c7 | 15078 | |
dcbf9037 | 15079 | return SUCCESS; |
5287ad62 JB |
15080 | } |
15081 | ||
15082 | /* Modify a bitmask of allowed types. This is only needed for type | |
15083 | relaxation. */ | |
15084 | ||
15085 | static unsigned | |
15086 | modify_types_allowed (unsigned allowed, unsigned mods) | |
15087 | { | |
15088 | unsigned size; | |
15089 | enum neon_el_type type; | |
15090 | unsigned destmask; | |
15091 | int i; | |
5f4273c7 | 15092 | |
5287ad62 | 15093 | destmask = 0; |
5f4273c7 | 15094 | |
5287ad62 JB |
15095 | for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) |
15096 | { | |
21d799b5 | 15097 | if (el_type_of_type_chk (&type, &size, |
477330fc RM |
15098 | (enum neon_type_mask) (allowed & i)) == SUCCESS) |
15099 | { | |
15100 | neon_modify_type_size (mods, &type, &size); | |
15101 | destmask |= type_chk_of_el_type (type, size); | |
15102 | } | |
5287ad62 | 15103 | } |
5f4273c7 | 15104 | |
5287ad62 JB |
15105 | return destmask; |
15106 | } | |
15107 | ||
15108 | /* Check type and return type classification. | |
15109 | The manual states (paraphrase): If one datatype is given, it indicates the | |
15110 | type given in: | |
15111 | - the second operand, if there is one | |
15112 | - the operand, if there is no second operand | |
15113 | - the result, if there are no operands. | |
15114 | This isn't quite good enough though, so we use a concept of a "key" datatype | |
15115 | which is set on a per-instruction basis, which is the one which matters when | |
15116 | only one data type is written. | |
15117 | Note: this function has side-effects (e.g. filling in missing operands). All | |
037e8744 | 15118 | Neon instructions should call it before performing bit encoding. */ |
5287ad62 JB |
15119 | |
15120 | static struct neon_type_el | |
15121 | neon_check_type (unsigned els, enum neon_shape ns, ...) | |
15122 | { | |
15123 | va_list ap; | |
15124 | unsigned i, pass, key_el = 0; | |
15125 | unsigned types[NEON_MAX_TYPE_ELS]; | |
15126 | enum neon_el_type k_type = NT_invtype; | |
15127 | unsigned k_size = -1u; | |
15128 | struct neon_type_el badtype = {NT_invtype, -1}; | |
15129 | unsigned key_allowed = 0; | |
15130 | ||
15131 | /* Optional registers in Neon instructions are always (not) in operand 1. | |
15132 | Fill in the missing operand here, if it was omitted. */ | |
15133 | if (els > 1 && !inst.operands[1].present) | |
15134 | inst.operands[1] = inst.operands[0]; | |
15135 | ||
15136 | /* Suck up all the varargs. */ | |
15137 | va_start (ap, ns); | |
15138 | for (i = 0; i < els; i++) | |
15139 | { | |
15140 | unsigned thisarg = va_arg (ap, unsigned); | |
15141 | if (thisarg == N_IGNORE_TYPE) | |
477330fc RM |
15142 | { |
15143 | va_end (ap); | |
15144 | return badtype; | |
15145 | } | |
5287ad62 JB |
15146 | types[i] = thisarg; |
15147 | if ((thisarg & N_KEY) != 0) | |
477330fc | 15148 | key_el = i; |
5287ad62 JB |
15149 | } |
15150 | va_end (ap); | |
15151 | ||
dcbf9037 JB |
15152 | if (inst.vectype.elems > 0) |
15153 | for (i = 0; i < els; i++) | |
15154 | if (inst.operands[i].vectype.type != NT_invtype) | |
477330fc RM |
15155 | { |
15156 | first_error (_("types specified in both the mnemonic and operands")); | |
15157 | return badtype; | |
15158 | } | |
dcbf9037 | 15159 | |
5287ad62 JB |
15160 | /* Duplicate inst.vectype elements here as necessary. |
15161 | FIXME: No idea if this is exactly the same as the ARM assembler, | |
15162 | particularly when an insn takes one register and one non-register | |
15163 | operand. */ | |
15164 | if (inst.vectype.elems == 1 && els > 1) | |
15165 | { | |
15166 | unsigned j; | |
15167 | inst.vectype.elems = els; | |
15168 | inst.vectype.el[key_el] = inst.vectype.el[0]; | |
15169 | for (j = 0; j < els; j++) | |
477330fc RM |
15170 | if (j != key_el) |
15171 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
15172 | types[j]); | |
dcbf9037 JB |
15173 | } |
15174 | else if (inst.vectype.elems == 0 && els > 0) | |
15175 | { | |
15176 | unsigned j; | |
15177 | /* No types were given after the mnemonic, so look for types specified | |
477330fc RM |
15178 | after each operand. We allow some flexibility here; as long as the |
15179 | "key" operand has a type, we can infer the others. */ | |
dcbf9037 | 15180 | for (j = 0; j < els; j++) |
477330fc RM |
15181 | if (inst.operands[j].vectype.type != NT_invtype) |
15182 | inst.vectype.el[j] = inst.operands[j].vectype; | |
dcbf9037 JB |
15183 | |
15184 | if (inst.operands[key_el].vectype.type != NT_invtype) | |
477330fc RM |
15185 | { |
15186 | for (j = 0; j < els; j++) | |
15187 | if (inst.operands[j].vectype.type == NT_invtype) | |
15188 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
15189 | types[j]); | |
15190 | } | |
dcbf9037 | 15191 | else |
477330fc RM |
15192 | { |
15193 | first_error (_("operand types can't be inferred")); | |
15194 | return badtype; | |
15195 | } | |
5287ad62 JB |
15196 | } |
15197 | else if (inst.vectype.elems != els) | |
15198 | { | |
dcbf9037 | 15199 | first_error (_("type specifier has the wrong number of parts")); |
5287ad62 JB |
15200 | return badtype; |
15201 | } | |
15202 | ||
15203 | for (pass = 0; pass < 2; pass++) | |
15204 | { | |
15205 | for (i = 0; i < els; i++) | |
477330fc RM |
15206 | { |
15207 | unsigned thisarg = types[i]; | |
15208 | unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) | |
15209 | ? modify_types_allowed (key_allowed, thisarg) : thisarg; | |
15210 | enum neon_el_type g_type = inst.vectype.el[i].type; | |
15211 | unsigned g_size = inst.vectype.el[i].size; | |
15212 | ||
15213 | /* Decay more-specific signed & unsigned types to sign-insensitive | |
5287ad62 | 15214 | integer types if sign-specific variants are unavailable. */ |
477330fc | 15215 | if ((g_type == NT_signed || g_type == NT_unsigned) |
5287ad62 JB |
15216 | && (types_allowed & N_SU_ALL) == 0) |
15217 | g_type = NT_integer; | |
15218 | ||
477330fc | 15219 | /* If only untyped args are allowed, decay any more specific types to |
5287ad62 JB |
15220 | them. Some instructions only care about signs for some element |
15221 | sizes, so handle that properly. */ | |
477330fc | 15222 | if (((types_allowed & N_UNT) == 0) |
91ff7894 MGD |
15223 | && ((g_size == 8 && (types_allowed & N_8) != 0) |
15224 | || (g_size == 16 && (types_allowed & N_16) != 0) | |
15225 | || (g_size == 32 && (types_allowed & N_32) != 0) | |
15226 | || (g_size == 64 && (types_allowed & N_64) != 0))) | |
5287ad62 JB |
15227 | g_type = NT_untyped; |
15228 | ||
477330fc RM |
15229 | if (pass == 0) |
15230 | { | |
15231 | if ((thisarg & N_KEY) != 0) | |
15232 | { | |
15233 | k_type = g_type; | |
15234 | k_size = g_size; | |
15235 | key_allowed = thisarg & ~N_KEY; | |
cc933301 JW |
15236 | |
15237 | /* Check architecture constraint on FP16 extension. */ | |
15238 | if (k_size == 16 | |
15239 | && k_type == NT_float | |
15240 | && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)) | |
15241 | { | |
15242 | inst.error = _(BAD_FP16); | |
15243 | return badtype; | |
15244 | } | |
477330fc RM |
15245 | } |
15246 | } | |
15247 | else | |
15248 | { | |
15249 | if ((thisarg & N_VFP) != 0) | |
15250 | { | |
15251 | enum neon_shape_el regshape; | |
15252 | unsigned regwidth, match; | |
99b253c5 NC |
15253 | |
15254 | /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */ | |
15255 | if (ns == NS_NULL) | |
15256 | { | |
15257 | first_error (_("invalid instruction shape")); | |
15258 | return badtype; | |
15259 | } | |
477330fc RM |
15260 | regshape = neon_shape_tab[ns].el[i]; |
15261 | regwidth = neon_shape_el_size[regshape]; | |
15262 | ||
15263 | /* In VFP mode, operands must match register widths. If we | |
15264 | have a key operand, use its width, else use the width of | |
15265 | the current operand. */ | |
15266 | if (k_size != -1u) | |
15267 | match = k_size; | |
15268 | else | |
15269 | match = g_size; | |
15270 | ||
9db2f6b4 RL |
15271 | /* FP16 will use a single precision register. */ |
15272 | if (regwidth == 32 && match == 16) | |
15273 | { | |
15274 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)) | |
15275 | match = regwidth; | |
15276 | else | |
15277 | { | |
15278 | inst.error = _(BAD_FP16); | |
15279 | return badtype; | |
15280 | } | |
15281 | } | |
15282 | ||
477330fc RM |
15283 | if (regwidth != match) |
15284 | { | |
15285 | first_error (_("operand size must match register width")); | |
15286 | return badtype; | |
15287 | } | |
15288 | } | |
15289 | ||
15290 | if ((thisarg & N_EQK) == 0) | |
15291 | { | |
15292 | unsigned given_type = type_chk_of_el_type (g_type, g_size); | |
15293 | ||
15294 | if ((given_type & types_allowed) == 0) | |
15295 | { | |
a302e574 | 15296 | first_error (BAD_SIMD_TYPE); |
477330fc RM |
15297 | return badtype; |
15298 | } | |
15299 | } | |
15300 | else | |
15301 | { | |
15302 | enum neon_el_type mod_k_type = k_type; | |
15303 | unsigned mod_k_size = k_size; | |
15304 | neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); | |
15305 | if (g_type != mod_k_type || g_size != mod_k_size) | |
15306 | { | |
15307 | first_error (_("inconsistent types in Neon instruction")); | |
15308 | return badtype; | |
15309 | } | |
15310 | } | |
15311 | } | |
15312 | } | |
5287ad62 JB |
15313 | } |
15314 | ||
15315 | return inst.vectype.el[key_el]; | |
15316 | } | |
15317 | ||
037e8744 | 15318 | /* Neon-style VFP instruction forwarding. */ |
5287ad62 | 15319 | |
037e8744 JB |
15320 | /* Thumb VFP instructions have 0xE in the condition field. */ |
15321 | ||
15322 | static void | |
15323 | do_vfp_cond_or_thumb (void) | |
5287ad62 | 15324 | { |
88714cb8 DG |
15325 | inst.is_neon = 1; |
15326 | ||
5287ad62 | 15327 | if (thumb_mode) |
037e8744 | 15328 | inst.instruction |= 0xe0000000; |
5287ad62 | 15329 | else |
037e8744 | 15330 | inst.instruction |= inst.cond << 28; |
5287ad62 JB |
15331 | } |
15332 | ||
037e8744 JB |
15333 | /* Look up and encode a simple mnemonic, for use as a helper function for the |
15334 | Neon-style VFP syntax. This avoids duplication of bits of the insns table, | |
15335 | etc. It is assumed that operand parsing has already been done, and that the | |
15336 | operands are in the form expected by the given opcode (this isn't necessarily | |
15337 | the same as the form in which they were parsed, hence some massaging must | |
15338 | take place before this function is called). | |
15339 | Checks current arch version against that in the looked-up opcode. */ | |
5287ad62 | 15340 | |
037e8744 JB |
15341 | static void |
15342 | do_vfp_nsyn_opcode (const char *opname) | |
5287ad62 | 15343 | { |
037e8744 | 15344 | const struct asm_opcode *opcode; |
5f4273c7 | 15345 | |
21d799b5 | 15346 | opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname); |
5287ad62 | 15347 | |
037e8744 JB |
15348 | if (!opcode) |
15349 | abort (); | |
5287ad62 | 15350 | |
037e8744 | 15351 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, |
477330fc RM |
15352 | thumb_mode ? *opcode->tvariant : *opcode->avariant), |
15353 | _(BAD_FPU)); | |
5287ad62 | 15354 | |
88714cb8 DG |
15355 | inst.is_neon = 1; |
15356 | ||
037e8744 JB |
15357 | if (thumb_mode) |
15358 | { | |
15359 | inst.instruction = opcode->tvalue; | |
15360 | opcode->tencode (); | |
15361 | } | |
15362 | else | |
15363 | { | |
15364 | inst.instruction = (inst.cond << 28) | opcode->avalue; | |
15365 | opcode->aencode (); | |
15366 | } | |
15367 | } | |
5287ad62 JB |
15368 | |
15369 | static void | |
037e8744 | 15370 | do_vfp_nsyn_add_sub (enum neon_shape rs) |
5287ad62 | 15371 | { |
037e8744 JB |
15372 | int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; |
15373 | ||
9db2f6b4 | 15374 | if (rs == NS_FFF || rs == NS_HHH) |
037e8744 JB |
15375 | { |
15376 | if (is_add) | |
477330fc | 15377 | do_vfp_nsyn_opcode ("fadds"); |
037e8744 | 15378 | else |
477330fc | 15379 | do_vfp_nsyn_opcode ("fsubs"); |
9db2f6b4 RL |
15380 | |
15381 | /* ARMv8.2 fp16 instruction. */ | |
15382 | if (rs == NS_HHH) | |
15383 | do_scalar_fp16_v82_encode (); | |
037e8744 JB |
15384 | } |
15385 | else | |
15386 | { | |
15387 | if (is_add) | |
477330fc | 15388 | do_vfp_nsyn_opcode ("faddd"); |
037e8744 | 15389 | else |
477330fc | 15390 | do_vfp_nsyn_opcode ("fsubd"); |
037e8744 JB |
15391 | } |
15392 | } | |
15393 | ||
15394 | /* Check operand types to see if this is a VFP instruction, and if so call | |
15395 | PFN (). */ | |
15396 | ||
15397 | static int | |
15398 | try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) | |
15399 | { | |
15400 | enum neon_shape rs; | |
15401 | struct neon_type_el et; | |
15402 | ||
15403 | switch (args) | |
15404 | { | |
15405 | case 2: | |
9db2f6b4 RL |
15406 | rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL); |
15407 | et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP); | |
037e8744 | 15408 | break; |
5f4273c7 | 15409 | |
037e8744 | 15410 | case 3: |
9db2f6b4 RL |
15411 | rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL); |
15412 | et = neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
15413 | N_F_ALL | N_KEY | N_VFP); | |
037e8744 JB |
15414 | break; |
15415 | ||
15416 | default: | |
15417 | abort (); | |
15418 | } | |
15419 | ||
15420 | if (et.type != NT_invtype) | |
15421 | { | |
15422 | pfn (rs); | |
15423 | return SUCCESS; | |
15424 | } | |
037e8744 | 15425 | |
99b253c5 | 15426 | inst.error = NULL; |
037e8744 JB |
15427 | return FAIL; |
15428 | } | |
15429 | ||
15430 | static void | |
15431 | do_vfp_nsyn_mla_mls (enum neon_shape rs) | |
15432 | { | |
15433 | int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; | |
5f4273c7 | 15434 | |
9db2f6b4 | 15435 | if (rs == NS_FFF || rs == NS_HHH) |
037e8744 JB |
15436 | { |
15437 | if (is_mla) | |
477330fc | 15438 | do_vfp_nsyn_opcode ("fmacs"); |
037e8744 | 15439 | else |
477330fc | 15440 | do_vfp_nsyn_opcode ("fnmacs"); |
9db2f6b4 RL |
15441 | |
15442 | /* ARMv8.2 fp16 instruction. */ | |
15443 | if (rs == NS_HHH) | |
15444 | do_scalar_fp16_v82_encode (); | |
037e8744 JB |
15445 | } |
15446 | else | |
15447 | { | |
15448 | if (is_mla) | |
477330fc | 15449 | do_vfp_nsyn_opcode ("fmacd"); |
037e8744 | 15450 | else |
477330fc | 15451 | do_vfp_nsyn_opcode ("fnmacd"); |
037e8744 JB |
15452 | } |
15453 | } | |
15454 | ||
62f3b8c8 PB |
15455 | static void |
15456 | do_vfp_nsyn_fma_fms (enum neon_shape rs) | |
15457 | { | |
15458 | int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma; | |
15459 | ||
9db2f6b4 | 15460 | if (rs == NS_FFF || rs == NS_HHH) |
62f3b8c8 PB |
15461 | { |
15462 | if (is_fma) | |
477330fc | 15463 | do_vfp_nsyn_opcode ("ffmas"); |
62f3b8c8 | 15464 | else |
477330fc | 15465 | do_vfp_nsyn_opcode ("ffnmas"); |
9db2f6b4 RL |
15466 | |
15467 | /* ARMv8.2 fp16 instruction. */ | |
15468 | if (rs == NS_HHH) | |
15469 | do_scalar_fp16_v82_encode (); | |
62f3b8c8 PB |
15470 | } |
15471 | else | |
15472 | { | |
15473 | if (is_fma) | |
477330fc | 15474 | do_vfp_nsyn_opcode ("ffmad"); |
62f3b8c8 | 15475 | else |
477330fc | 15476 | do_vfp_nsyn_opcode ("ffnmad"); |
62f3b8c8 PB |
15477 | } |
15478 | } | |
15479 | ||
037e8744 JB |
15480 | static void |
15481 | do_vfp_nsyn_mul (enum neon_shape rs) | |
15482 | { | |
9db2f6b4 RL |
15483 | if (rs == NS_FFF || rs == NS_HHH) |
15484 | { | |
15485 | do_vfp_nsyn_opcode ("fmuls"); | |
15486 | ||
15487 | /* ARMv8.2 fp16 instruction. */ | |
15488 | if (rs == NS_HHH) | |
15489 | do_scalar_fp16_v82_encode (); | |
15490 | } | |
037e8744 JB |
15491 | else |
15492 | do_vfp_nsyn_opcode ("fmuld"); | |
15493 | } | |
15494 | ||
15495 | static void | |
15496 | do_vfp_nsyn_abs_neg (enum neon_shape rs) | |
15497 | { | |
15498 | int is_neg = (inst.instruction & 0x80) != 0; | |
9db2f6b4 | 15499 | neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_VFP | N_KEY); |
037e8744 | 15500 | |
9db2f6b4 | 15501 | if (rs == NS_FF || rs == NS_HH) |
037e8744 JB |
15502 | { |
15503 | if (is_neg) | |
477330fc | 15504 | do_vfp_nsyn_opcode ("fnegs"); |
037e8744 | 15505 | else |
477330fc | 15506 | do_vfp_nsyn_opcode ("fabss"); |
9db2f6b4 RL |
15507 | |
15508 | /* ARMv8.2 fp16 instruction. */ | |
15509 | if (rs == NS_HH) | |
15510 | do_scalar_fp16_v82_encode (); | |
037e8744 JB |
15511 | } |
15512 | else | |
15513 | { | |
15514 | if (is_neg) | |
477330fc | 15515 | do_vfp_nsyn_opcode ("fnegd"); |
037e8744 | 15516 | else |
477330fc | 15517 | do_vfp_nsyn_opcode ("fabsd"); |
037e8744 JB |
15518 | } |
15519 | } | |
15520 | ||
15521 | /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision | |
15522 | insns belong to Neon, and are handled elsewhere. */ | |
15523 | ||
15524 | static void | |
15525 | do_vfp_nsyn_ldm_stm (int is_dbmode) | |
15526 | { | |
15527 | int is_ldm = (inst.instruction & (1 << 20)) != 0; | |
15528 | if (is_ldm) | |
15529 | { | |
15530 | if (is_dbmode) | |
477330fc | 15531 | do_vfp_nsyn_opcode ("fldmdbs"); |
037e8744 | 15532 | else |
477330fc | 15533 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 JB |
15534 | } |
15535 | else | |
15536 | { | |
15537 | if (is_dbmode) | |
477330fc | 15538 | do_vfp_nsyn_opcode ("fstmdbs"); |
037e8744 | 15539 | else |
477330fc | 15540 | do_vfp_nsyn_opcode ("fstmias"); |
037e8744 JB |
15541 | } |
15542 | } | |
15543 | ||
037e8744 JB |
15544 | static void |
15545 | do_vfp_nsyn_sqrt (void) | |
15546 | { | |
9db2f6b4 RL |
15547 | enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL); |
15548 | neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP); | |
5f4273c7 | 15549 | |
9db2f6b4 RL |
15550 | if (rs == NS_FF || rs == NS_HH) |
15551 | { | |
15552 | do_vfp_nsyn_opcode ("fsqrts"); | |
15553 | ||
15554 | /* ARMv8.2 fp16 instruction. */ | |
15555 | if (rs == NS_HH) | |
15556 | do_scalar_fp16_v82_encode (); | |
15557 | } | |
037e8744 JB |
15558 | else |
15559 | do_vfp_nsyn_opcode ("fsqrtd"); | |
15560 | } | |
15561 | ||
15562 | static void | |
15563 | do_vfp_nsyn_div (void) | |
15564 | { | |
9db2f6b4 | 15565 | enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL); |
037e8744 | 15566 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, |
9db2f6b4 | 15567 | N_F_ALL | N_KEY | N_VFP); |
5f4273c7 | 15568 | |
9db2f6b4 RL |
15569 | if (rs == NS_FFF || rs == NS_HHH) |
15570 | { | |
15571 | do_vfp_nsyn_opcode ("fdivs"); | |
15572 | ||
15573 | /* ARMv8.2 fp16 instruction. */ | |
15574 | if (rs == NS_HHH) | |
15575 | do_scalar_fp16_v82_encode (); | |
15576 | } | |
037e8744 JB |
15577 | else |
15578 | do_vfp_nsyn_opcode ("fdivd"); | |
15579 | } | |
15580 | ||
15581 | static void | |
15582 | do_vfp_nsyn_nmul (void) | |
15583 | { | |
9db2f6b4 | 15584 | enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL); |
037e8744 | 15585 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, |
9db2f6b4 | 15586 | N_F_ALL | N_KEY | N_VFP); |
5f4273c7 | 15587 | |
9db2f6b4 | 15588 | if (rs == NS_FFF || rs == NS_HHH) |
037e8744 | 15589 | { |
88714cb8 | 15590 | NEON_ENCODE (SINGLE, inst); |
037e8744 | 15591 | do_vfp_sp_dyadic (); |
9db2f6b4 RL |
15592 | |
15593 | /* ARMv8.2 fp16 instruction. */ | |
15594 | if (rs == NS_HHH) | |
15595 | do_scalar_fp16_v82_encode (); | |
037e8744 JB |
15596 | } |
15597 | else | |
15598 | { | |
88714cb8 | 15599 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
15600 | do_vfp_dp_rd_rn_rm (); |
15601 | } | |
15602 | do_vfp_cond_or_thumb (); | |
9db2f6b4 | 15603 | |
037e8744 JB |
15604 | } |
15605 | ||
1b883319 AV |
15606 | /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 |
15607 | (0, 1, 2, 3). */ | |
15608 | ||
15609 | static unsigned | |
15610 | neon_logbits (unsigned x) | |
15611 | { | |
15612 | return ffs (x) - 4; | |
15613 | } | |
15614 | ||
15615 | #define LOW4(R) ((R) & 0xf) | |
15616 | #define HI1(R) (((R) >> 4) & 1) | |
15617 | ||
15618 | static unsigned | |
15619 | mve_get_vcmp_vpt_cond (struct neon_type_el et) | |
15620 | { | |
15621 | switch (et.type) | |
15622 | { | |
15623 | default: | |
15624 | first_error (BAD_EL_TYPE); | |
15625 | return 0; | |
15626 | case NT_float: | |
15627 | switch (inst.operands[0].imm) | |
15628 | { | |
15629 | default: | |
15630 | first_error (_("invalid condition")); | |
15631 | return 0; | |
15632 | case 0x0: | |
15633 | /* eq. */ | |
15634 | return 0; | |
15635 | case 0x1: | |
15636 | /* ne. */ | |
15637 | return 1; | |
15638 | case 0xa: | |
15639 | /* ge/ */ | |
15640 | return 4; | |
15641 | case 0xb: | |
15642 | /* lt. */ | |
15643 | return 5; | |
15644 | case 0xc: | |
15645 | /* gt. */ | |
15646 | return 6; | |
15647 | case 0xd: | |
15648 | /* le. */ | |
15649 | return 7; | |
15650 | } | |
15651 | case NT_integer: | |
15652 | /* only accept eq and ne. */ | |
15653 | if (inst.operands[0].imm > 1) | |
15654 | { | |
15655 | first_error (_("invalid condition")); | |
15656 | return 0; | |
15657 | } | |
15658 | return inst.operands[0].imm; | |
15659 | case NT_unsigned: | |
15660 | if (inst.operands[0].imm == 0x2) | |
15661 | return 2; | |
15662 | else if (inst.operands[0].imm == 0x8) | |
15663 | return 3; | |
15664 | else | |
15665 | { | |
15666 | first_error (_("invalid condition")); | |
15667 | return 0; | |
15668 | } | |
15669 | case NT_signed: | |
15670 | switch (inst.operands[0].imm) | |
15671 | { | |
15672 | default: | |
15673 | first_error (_("invalid condition")); | |
15674 | return 0; | |
15675 | case 0xa: | |
15676 | /* ge. */ | |
15677 | return 4; | |
15678 | case 0xb: | |
15679 | /* lt. */ | |
15680 | return 5; | |
15681 | case 0xc: | |
15682 | /* gt. */ | |
15683 | return 6; | |
15684 | case 0xd: | |
15685 | /* le. */ | |
15686 | return 7; | |
15687 | } | |
15688 | } | |
15689 | /* Should be unreachable. */ | |
15690 | abort (); | |
15691 | } | |
15692 | ||
15693 | static void | |
15694 | do_mve_vpt (void) | |
15695 | { | |
15696 | /* We are dealing with a vector predicated block. */ | |
15697 | if (inst.operands[0].present) | |
15698 | { | |
15699 | enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL); | |
15700 | struct neon_type_el et | |
15701 | = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32, | |
15702 | N_EQK); | |
15703 | ||
15704 | unsigned fcond = mve_get_vcmp_vpt_cond (et); | |
15705 | ||
15706 | constraint (inst.operands[1].reg > 14, MVE_BAD_QREG); | |
15707 | ||
15708 | if (et.type == NT_invtype) | |
15709 | return; | |
15710 | ||
15711 | if (et.type == NT_float) | |
15712 | { | |
15713 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext), | |
15714 | BAD_FPU); | |
15715 | constraint (et.size != 16 && et.size != 32, BAD_EL_TYPE); | |
15716 | inst.instruction |= (et.size == 16) << 28; | |
15717 | inst.instruction |= 0x3 << 20; | |
15718 | } | |
15719 | else | |
15720 | { | |
15721 | constraint (et.size != 8 && et.size != 16 && et.size != 32, | |
15722 | BAD_EL_TYPE); | |
15723 | inst.instruction |= 1 << 28; | |
15724 | inst.instruction |= neon_logbits (et.size) << 20; | |
15725 | } | |
15726 | ||
15727 | if (inst.operands[2].isquad) | |
15728 | { | |
15729 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
15730 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15731 | inst.instruction |= (fcond & 0x2) >> 1; | |
15732 | } | |
15733 | else | |
15734 | { | |
15735 | if (inst.operands[2].reg == REG_SP) | |
15736 | as_tsktsk (MVE_BAD_SP); | |
15737 | inst.instruction |= 1 << 6; | |
15738 | inst.instruction |= (fcond & 0x2) << 4; | |
15739 | inst.instruction |= inst.operands[2].reg; | |
15740 | } | |
15741 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15742 | inst.instruction |= (fcond & 0x4) << 10; | |
15743 | inst.instruction |= (fcond & 0x1) << 7; | |
15744 | ||
15745 | } | |
15746 | set_pred_insn_type (VPT_INSN); | |
15747 | now_pred.cc = 0; | |
15748 | now_pred.mask = ((inst.instruction & 0x00400000) >> 19) | |
15749 | | ((inst.instruction & 0xe000) >> 13); | |
15750 | now_pred.warn_deprecated = FALSE; | |
15751 | now_pred.type = VECTOR_PRED; | |
15752 | inst.is_neon = 1; | |
15753 | } | |
15754 | ||
15755 | static void | |
15756 | do_mve_vcmp (void) | |
15757 | { | |
15758 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); | |
15759 | if (!inst.operands[1].isreg || !inst.operands[1].isquad) | |
15760 | first_error (_(reg_expected_msgs[REG_TYPE_MQ])); | |
15761 | if (!inst.operands[2].present) | |
15762 | first_error (_("MVE vector or ARM register expected")); | |
15763 | constraint (inst.operands[1].reg > 14, MVE_BAD_QREG); | |
15764 | ||
15765 | /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */ | |
15766 | if ((inst.instruction & 0xffffffff) == N_MNEM_vcmpe | |
15767 | && inst.operands[1].isquad) | |
15768 | { | |
15769 | inst.instruction = N_MNEM_vcmp; | |
15770 | inst.cond = 0x10; | |
15771 | } | |
15772 | ||
15773 | if (inst.cond > COND_ALWAYS) | |
15774 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
15775 | else | |
15776 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
15777 | ||
15778 | enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL); | |
15779 | struct neon_type_el et | |
15780 | = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32, | |
15781 | N_EQK); | |
15782 | ||
15783 | constraint (rs == NS_IQR && inst.operands[2].reg == REG_PC | |
15784 | && !inst.operands[2].iszr, BAD_PC); | |
15785 | ||
15786 | unsigned fcond = mve_get_vcmp_vpt_cond (et); | |
15787 | ||
15788 | inst.instruction = 0xee010f00; | |
15789 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15790 | inst.instruction |= (fcond & 0x4) << 10; | |
15791 | inst.instruction |= (fcond & 0x1) << 7; | |
15792 | if (et.type == NT_float) | |
15793 | { | |
15794 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext), | |
15795 | BAD_FPU); | |
15796 | inst.instruction |= (et.size == 16) << 28; | |
15797 | inst.instruction |= 0x3 << 20; | |
15798 | } | |
15799 | else | |
15800 | { | |
15801 | inst.instruction |= 1 << 28; | |
15802 | inst.instruction |= neon_logbits (et.size) << 20; | |
15803 | } | |
15804 | if (inst.operands[2].isquad) | |
15805 | { | |
15806 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
15807 | inst.instruction |= (fcond & 0x2) >> 1; | |
15808 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15809 | } | |
15810 | else | |
15811 | { | |
15812 | if (inst.operands[2].reg == REG_SP) | |
15813 | as_tsktsk (MVE_BAD_SP); | |
15814 | inst.instruction |= 1 << 6; | |
15815 | inst.instruction |= (fcond & 0x2) << 4; | |
15816 | inst.instruction |= inst.operands[2].reg; | |
15817 | } | |
15818 | ||
15819 | inst.is_neon = 1; | |
15820 | return; | |
15821 | } | |
15822 | ||
935295b5 AV |
15823 | static void |
15824 | do_mve_vmaxa_vmina (void) | |
15825 | { | |
15826 | if (inst.cond > COND_ALWAYS) | |
15827 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
15828 | else | |
15829 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
15830 | ||
15831 | enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL); | |
15832 | struct neon_type_el et | |
15833 | = neon_check_type (2, rs, N_EQK, N_KEY | N_S8 | N_S16 | N_S32); | |
15834 | ||
15835 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15836 | inst.instruction |= neon_logbits (et.size) << 18; | |
15837 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15838 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15839 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15840 | inst.is_neon = 1; | |
15841 | } | |
15842 | ||
f30ee27c AV |
15843 | static void |
15844 | do_mve_vfmas (void) | |
15845 | { | |
15846 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); | |
15847 | struct neon_type_el et | |
15848 | = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK, N_EQK); | |
15849 | ||
15850 | if (inst.cond > COND_ALWAYS) | |
15851 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
15852 | else | |
15853 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
15854 | ||
15855 | if (inst.operands[2].reg == REG_SP) | |
15856 | as_tsktsk (MVE_BAD_SP); | |
15857 | else if (inst.operands[2].reg == REG_PC) | |
15858 | as_tsktsk (MVE_BAD_PC); | |
15859 | ||
15860 | inst.instruction |= (et.size == 16) << 28; | |
15861 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15862 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15863 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15864 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15865 | inst.instruction |= inst.operands[2].reg; | |
15866 | inst.is_neon = 1; | |
15867 | } | |
15868 | ||
b409bdb6 AV |
15869 | static void |
15870 | do_mve_viddup (void) | |
15871 | { | |
15872 | if (inst.cond > COND_ALWAYS) | |
15873 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
15874 | else | |
15875 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
15876 | ||
15877 | unsigned imm = inst.relocs[0].exp.X_add_number; | |
15878 | constraint (imm != 1 && imm != 2 && imm != 4 && imm != 8, | |
15879 | _("immediate must be either 1, 2, 4 or 8")); | |
15880 | ||
15881 | enum neon_shape rs; | |
15882 | struct neon_type_el et; | |
15883 | unsigned Rm; | |
15884 | if (inst.instruction == M_MNEM_vddup || inst.instruction == M_MNEM_vidup) | |
15885 | { | |
15886 | rs = neon_select_shape (NS_QRI, NS_NULL); | |
15887 | et = neon_check_type (2, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK); | |
15888 | Rm = 7; | |
15889 | } | |
15890 | else | |
15891 | { | |
15892 | constraint ((inst.operands[2].reg % 2) != 1, BAD_EVEN); | |
15893 | if (inst.operands[2].reg == REG_SP) | |
15894 | as_tsktsk (MVE_BAD_SP); | |
15895 | else if (inst.operands[2].reg == REG_PC) | |
15896 | first_error (BAD_PC); | |
15897 | ||
15898 | rs = neon_select_shape (NS_QRRI, NS_NULL); | |
15899 | et = neon_check_type (3, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK, N_EQK); | |
15900 | Rm = inst.operands[2].reg >> 1; | |
15901 | } | |
15902 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15903 | inst.instruction |= neon_logbits (et.size) << 20; | |
15904 | inst.instruction |= inst.operands[1].reg << 16; | |
15905 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15906 | inst.instruction |= (imm > 2) << 7; | |
15907 | inst.instruction |= Rm << 1; | |
15908 | inst.instruction |= (imm == 2 || imm == 8); | |
15909 | inst.is_neon = 1; | |
15910 | } | |
15911 | ||
2d78f95b AV |
15912 | static void |
15913 | do_mve_vmlas (void) | |
15914 | { | |
15915 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); | |
15916 | struct neon_type_el et | |
15917 | = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); | |
15918 | ||
15919 | if (inst.operands[2].reg == REG_PC) | |
15920 | as_tsktsk (MVE_BAD_PC); | |
15921 | else if (inst.operands[2].reg == REG_SP) | |
15922 | as_tsktsk (MVE_BAD_SP); | |
15923 | ||
15924 | if (inst.cond > COND_ALWAYS) | |
15925 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
15926 | else | |
15927 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
15928 | ||
15929 | inst.instruction |= (et.type == NT_unsigned) << 28; | |
15930 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15931 | inst.instruction |= neon_logbits (et.size) << 20; | |
15932 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15933 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15934 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15935 | inst.instruction |= inst.operands[2].reg; | |
15936 | inst.is_neon = 1; | |
15937 | } | |
15938 | ||
acca5630 AV |
15939 | static void |
15940 | do_mve_vshll (void) | |
15941 | { | |
15942 | struct neon_type_el et | |
15943 | = neon_check_type (2, NS_QQI, N_EQK, N_S8 | N_U8 | N_S16 | N_U16 | N_KEY); | |
15944 | ||
15945 | if (inst.cond > COND_ALWAYS) | |
15946 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
15947 | else | |
15948 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
15949 | ||
15950 | int imm = inst.operands[2].imm; | |
15951 | constraint (imm < 1 || (unsigned)imm > et.size, | |
15952 | _("immediate value out of range")); | |
15953 | ||
15954 | if ((unsigned)imm == et.size) | |
15955 | { | |
15956 | inst.instruction |= neon_logbits (et.size) << 18; | |
15957 | inst.instruction |= 0x110001; | |
15958 | } | |
15959 | else | |
15960 | { | |
15961 | inst.instruction |= (et.size + imm) << 16; | |
15962 | inst.instruction |= 0x800140; | |
15963 | } | |
15964 | ||
15965 | inst.instruction |= (et.type == NT_unsigned) << 28; | |
15966 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15967 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15968 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15969 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15970 | inst.is_neon = 1; | |
15971 | } | |
15972 | ||
15973 | static void | |
15974 | do_mve_vshlc (void) | |
15975 | { | |
15976 | if (inst.cond > COND_ALWAYS) | |
15977 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
15978 | else | |
15979 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
15980 | ||
15981 | if (inst.operands[1].reg == REG_PC) | |
15982 | as_tsktsk (MVE_BAD_PC); | |
15983 | else if (inst.operands[1].reg == REG_SP) | |
15984 | as_tsktsk (MVE_BAD_SP); | |
15985 | ||
15986 | int imm = inst.operands[2].imm; | |
15987 | constraint (imm < 1 || imm > 32, _("immediate value out of range")); | |
15988 | ||
15989 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15990 | inst.instruction |= (imm & 0x1f) << 16; | |
15991 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15992 | inst.instruction |= inst.operands[1].reg; | |
15993 | inst.is_neon = 1; | |
15994 | } | |
15995 | ||
4aa88b50 AV |
15996 | static void |
15997 | do_mve_vshrn (void) | |
15998 | { | |
15999 | unsigned types; | |
16000 | switch (inst.instruction) | |
16001 | { | |
16002 | case M_MNEM_vshrnt: | |
16003 | case M_MNEM_vshrnb: | |
16004 | case M_MNEM_vrshrnt: | |
16005 | case M_MNEM_vrshrnb: | |
16006 | types = N_I16 | N_I32; | |
16007 | break; | |
16008 | case M_MNEM_vqshrnt: | |
16009 | case M_MNEM_vqshrnb: | |
16010 | case M_MNEM_vqrshrnt: | |
16011 | case M_MNEM_vqrshrnb: | |
16012 | types = N_U16 | N_U32 | N_S16 | N_S32; | |
16013 | break; | |
16014 | case M_MNEM_vqshrunt: | |
16015 | case M_MNEM_vqshrunb: | |
16016 | case M_MNEM_vqrshrunt: | |
16017 | case M_MNEM_vqrshrunb: | |
16018 | types = N_S16 | N_S32; | |
16019 | break; | |
16020 | default: | |
16021 | abort (); | |
16022 | } | |
16023 | ||
16024 | struct neon_type_el et = neon_check_type (2, NS_QQI, N_EQK, types | N_KEY); | |
16025 | ||
16026 | if (inst.cond > COND_ALWAYS) | |
16027 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
16028 | else | |
16029 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16030 | ||
16031 | unsigned Qd = inst.operands[0].reg; | |
16032 | unsigned Qm = inst.operands[1].reg; | |
16033 | unsigned imm = inst.operands[2].imm; | |
16034 | constraint (imm < 1 || ((unsigned) imm) > (et.size / 2), | |
16035 | et.size == 16 | |
16036 | ? _("immediate operand expected in the range [1,8]") | |
16037 | : _("immediate operand expected in the range [1,16]")); | |
16038 | ||
16039 | inst.instruction |= (et.type == NT_unsigned) << 28; | |
16040 | inst.instruction |= HI1 (Qd) << 22; | |
16041 | inst.instruction |= (et.size - imm) << 16; | |
16042 | inst.instruction |= LOW4 (Qd) << 12; | |
16043 | inst.instruction |= HI1 (Qm) << 5; | |
16044 | inst.instruction |= LOW4 (Qm); | |
16045 | inst.is_neon = 1; | |
16046 | } | |
16047 | ||
1be7aba3 AV |
16048 | static void |
16049 | do_mve_vqmovn (void) | |
16050 | { | |
16051 | struct neon_type_el et; | |
16052 | if (inst.instruction == M_MNEM_vqmovnt | |
16053 | || inst.instruction == M_MNEM_vqmovnb) | |
16054 | et = neon_check_type (2, NS_QQ, N_EQK, | |
16055 | N_U16 | N_U32 | N_S16 | N_S32 | N_KEY); | |
16056 | else | |
16057 | et = neon_check_type (2, NS_QQ, N_EQK, N_S16 | N_S32 | N_KEY); | |
16058 | ||
16059 | if (inst.cond > COND_ALWAYS) | |
16060 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
16061 | else | |
16062 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16063 | ||
16064 | inst.instruction |= (et.type == NT_unsigned) << 28; | |
16065 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16066 | inst.instruction |= (et.size == 32) << 18; | |
16067 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16068 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
16069 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16070 | inst.is_neon = 1; | |
16071 | } | |
16072 | ||
3063888e AV |
16073 | static void |
16074 | do_mve_vpsel (void) | |
16075 | { | |
16076 | neon_select_shape (NS_QQQ, NS_NULL); | |
16077 | ||
16078 | if (inst.cond > COND_ALWAYS) | |
16079 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
16080 | else | |
16081 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16082 | ||
16083 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16084 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16085 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16086 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16087 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
16088 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16089 | inst.is_neon = 1; | |
16090 | } | |
16091 | ||
16092 | static void | |
16093 | do_mve_vpnot (void) | |
16094 | { | |
16095 | if (inst.cond > COND_ALWAYS) | |
16096 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
16097 | else | |
16098 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16099 | } | |
16100 | ||
935295b5 AV |
16101 | static void |
16102 | do_mve_vmaxnma_vminnma (void) | |
16103 | { | |
16104 | enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL); | |
16105 | struct neon_type_el et | |
16106 | = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY); | |
16107 | ||
16108 | if (inst.cond > COND_ALWAYS) | |
16109 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
16110 | else | |
16111 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16112 | ||
16113 | inst.instruction |= (et.size == 16) << 28; | |
16114 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16115 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16116 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
16117 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16118 | inst.is_neon = 1; | |
16119 | } | |
16120 | ||
5d281bf0 AV |
16121 | static void |
16122 | do_mve_vcmul (void) | |
16123 | { | |
16124 | enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL); | |
16125 | struct neon_type_el et | |
16126 | = neon_check_type (3, rs, N_EQK, N_EQK, N_F_MVE | N_KEY); | |
16127 | ||
16128 | if (inst.cond > COND_ALWAYS) | |
16129 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
16130 | else | |
16131 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16132 | ||
16133 | unsigned rot = inst.relocs[0].exp.X_add_number; | |
16134 | constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270, | |
16135 | _("immediate out of range")); | |
16136 | ||
16137 | if (et.size == 32 && (inst.operands[0].reg == inst.operands[1].reg | |
16138 | || inst.operands[0].reg == inst.operands[2].reg)) | |
16139 | as_tsktsk (BAD_MVE_SRCDEST); | |
16140 | ||
16141 | inst.instruction |= (et.size == 32) << 28; | |
16142 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16143 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16144 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16145 | inst.instruction |= (rot > 90) << 12; | |
16146 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16147 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
16148 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16149 | inst.instruction |= (rot == 90 || rot == 270); | |
16150 | inst.is_neon = 1; | |
16151 | } | |
16152 | ||
1f6234a3 AV |
16153 | /* To handle the Low Overhead Loop instructions |
16154 | in Armv8.1-M Mainline and MVE. */ | |
16155 | static void | |
16156 | do_t_loloop (void) | |
16157 | { | |
16158 | unsigned long insn = inst.instruction; | |
16159 | ||
16160 | inst.instruction = THUMB_OP32 (inst.instruction); | |
16161 | ||
16162 | if (insn == T_MNEM_lctp) | |
16163 | return; | |
16164 | ||
16165 | set_pred_insn_type (MVE_OUTSIDE_PRED_INSN); | |
16166 | ||
16167 | if (insn == T_MNEM_wlstp || insn == T_MNEM_dlstp) | |
16168 | { | |
16169 | struct neon_type_el et | |
16170 | = neon_check_type (2, NS_RR, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
16171 | inst.instruction |= neon_logbits (et.size) << 20; | |
16172 | inst.is_neon = 1; | |
16173 | } | |
16174 | ||
16175 | switch (insn) | |
16176 | { | |
16177 | case T_MNEM_letp: | |
16178 | constraint (!inst.operands[0].present, | |
16179 | _("expected LR")); | |
16180 | /* fall through. */ | |
16181 | case T_MNEM_le: | |
16182 | /* le <label>. */ | |
16183 | if (!inst.operands[0].present) | |
16184 | inst.instruction |= 1 << 21; | |
16185 | ||
16186 | v8_1_loop_reloc (TRUE); | |
16187 | break; | |
16188 | ||
16189 | case T_MNEM_wls: | |
16190 | case T_MNEM_wlstp: | |
16191 | v8_1_loop_reloc (FALSE); | |
16192 | /* fall through. */ | |
16193 | case T_MNEM_dlstp: | |
16194 | case T_MNEM_dls: | |
16195 | constraint (inst.operands[1].isreg != 1, BAD_ARGS); | |
16196 | ||
16197 | if (insn == T_MNEM_wlstp || insn == T_MNEM_dlstp) | |
16198 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); | |
16199 | else if (inst.operands[1].reg == REG_PC) | |
16200 | as_tsktsk (MVE_BAD_PC); | |
16201 | if (inst.operands[1].reg == REG_SP) | |
16202 | as_tsktsk (MVE_BAD_SP); | |
16203 | ||
16204 | inst.instruction |= (inst.operands[1].reg << 16); | |
16205 | break; | |
16206 | ||
16207 | default: | |
16208 | abort (); | |
16209 | } | |
16210 | } | |
16211 | ||
16212 | ||
037e8744 JB |
16213 | static void |
16214 | do_vfp_nsyn_cmp (void) | |
16215 | { | |
9db2f6b4 | 16216 | enum neon_shape rs; |
1b883319 AV |
16217 | if (!inst.operands[0].isreg) |
16218 | { | |
16219 | do_mve_vcmp (); | |
16220 | return; | |
16221 | } | |
16222 | else | |
16223 | { | |
16224 | constraint (inst.operands[2].present, BAD_SYNTAX); | |
16225 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd), | |
16226 | BAD_FPU); | |
16227 | } | |
16228 | ||
037e8744 JB |
16229 | if (inst.operands[1].isreg) |
16230 | { | |
9db2f6b4 RL |
16231 | rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL); |
16232 | neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP); | |
5f4273c7 | 16233 | |
9db2f6b4 | 16234 | if (rs == NS_FF || rs == NS_HH) |
477330fc RM |
16235 | { |
16236 | NEON_ENCODE (SINGLE, inst); | |
16237 | do_vfp_sp_monadic (); | |
16238 | } | |
037e8744 | 16239 | else |
477330fc RM |
16240 | { |
16241 | NEON_ENCODE (DOUBLE, inst); | |
16242 | do_vfp_dp_rd_rm (); | |
16243 | } | |
037e8744 JB |
16244 | } |
16245 | else | |
16246 | { | |
9db2f6b4 RL |
16247 | rs = neon_select_shape (NS_HI, NS_FI, NS_DI, NS_NULL); |
16248 | neon_check_type (2, rs, N_F_ALL | N_KEY | N_VFP, N_EQK); | |
037e8744 JB |
16249 | |
16250 | switch (inst.instruction & 0x0fffffff) | |
477330fc RM |
16251 | { |
16252 | case N_MNEM_vcmp: | |
16253 | inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; | |
16254 | break; | |
16255 | case N_MNEM_vcmpe: | |
16256 | inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; | |
16257 | break; | |
16258 | default: | |
16259 | abort (); | |
16260 | } | |
5f4273c7 | 16261 | |
9db2f6b4 | 16262 | if (rs == NS_FI || rs == NS_HI) |
477330fc RM |
16263 | { |
16264 | NEON_ENCODE (SINGLE, inst); | |
16265 | do_vfp_sp_compare_z (); | |
16266 | } | |
037e8744 | 16267 | else |
477330fc RM |
16268 | { |
16269 | NEON_ENCODE (DOUBLE, inst); | |
16270 | do_vfp_dp_rd (); | |
16271 | } | |
037e8744 JB |
16272 | } |
16273 | do_vfp_cond_or_thumb (); | |
9db2f6b4 RL |
16274 | |
16275 | /* ARMv8.2 fp16 instruction. */ | |
16276 | if (rs == NS_HI || rs == NS_HH) | |
16277 | do_scalar_fp16_v82_encode (); | |
037e8744 JB |
16278 | } |
16279 | ||
16280 | static void | |
16281 | nsyn_insert_sp (void) | |
16282 | { | |
16283 | inst.operands[1] = inst.operands[0]; | |
16284 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
fdfde340 | 16285 | inst.operands[0].reg = REG_SP; |
037e8744 JB |
16286 | inst.operands[0].isreg = 1; |
16287 | inst.operands[0].writeback = 1; | |
16288 | inst.operands[0].present = 1; | |
16289 | } | |
16290 | ||
16291 | static void | |
16292 | do_vfp_nsyn_push (void) | |
16293 | { | |
16294 | nsyn_insert_sp (); | |
b126985e NC |
16295 | |
16296 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
16297 | _("register list must contain at least 1 and at most 16 " | |
16298 | "registers")); | |
16299 | ||
037e8744 JB |
16300 | if (inst.operands[1].issingle) |
16301 | do_vfp_nsyn_opcode ("fstmdbs"); | |
16302 | else | |
16303 | do_vfp_nsyn_opcode ("fstmdbd"); | |
16304 | } | |
16305 | ||
16306 | static void | |
16307 | do_vfp_nsyn_pop (void) | |
16308 | { | |
16309 | nsyn_insert_sp (); | |
b126985e NC |
16310 | |
16311 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
16312 | _("register list must contain at least 1 and at most 16 " | |
16313 | "registers")); | |
16314 | ||
037e8744 | 16315 | if (inst.operands[1].issingle) |
22b5b651 | 16316 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 | 16317 | else |
22b5b651 | 16318 | do_vfp_nsyn_opcode ("fldmiad"); |
037e8744 JB |
16319 | } |
16320 | ||
16321 | /* Fix up Neon data-processing instructions, ORing in the correct bits for | |
16322 | ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ | |
16323 | ||
88714cb8 DG |
16324 | static void |
16325 | neon_dp_fixup (struct arm_it* insn) | |
037e8744 | 16326 | { |
88714cb8 DG |
16327 | unsigned int i = insn->instruction; |
16328 | insn->is_neon = 1; | |
16329 | ||
037e8744 JB |
16330 | if (thumb_mode) |
16331 | { | |
16332 | /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ | |
16333 | if (i & (1 << 24)) | |
477330fc | 16334 | i |= 1 << 28; |
5f4273c7 | 16335 | |
037e8744 | 16336 | i &= ~(1 << 24); |
5f4273c7 | 16337 | |
037e8744 JB |
16338 | i |= 0xef000000; |
16339 | } | |
16340 | else | |
16341 | i |= 0xf2000000; | |
5f4273c7 | 16342 | |
88714cb8 | 16343 | insn->instruction = i; |
037e8744 JB |
16344 | } |
16345 | ||
5ee91343 | 16346 | static void |
7df54120 | 16347 | mve_encode_qqr (int size, int U, int fp) |
5ee91343 AV |
16348 | { |
16349 | if (inst.operands[2].reg == REG_SP) | |
16350 | as_tsktsk (MVE_BAD_SP); | |
16351 | else if (inst.operands[2].reg == REG_PC) | |
16352 | as_tsktsk (MVE_BAD_PC); | |
16353 | ||
16354 | if (fp) | |
16355 | { | |
16356 | /* vadd. */ | |
16357 | if (((unsigned)inst.instruction) == 0xd00) | |
16358 | inst.instruction = 0xee300f40; | |
16359 | /* vsub. */ | |
16360 | else if (((unsigned)inst.instruction) == 0x200d00) | |
16361 | inst.instruction = 0xee301f40; | |
a8465a06 AV |
16362 | /* vmul. */ |
16363 | else if (((unsigned)inst.instruction) == 0x1000d10) | |
16364 | inst.instruction = 0xee310e60; | |
5ee91343 AV |
16365 | |
16366 | /* Setting size which is 1 for F16 and 0 for F32. */ | |
16367 | inst.instruction |= (size == 16) << 28; | |
16368 | } | |
16369 | else | |
16370 | { | |
16371 | /* vadd. */ | |
16372 | if (((unsigned)inst.instruction) == 0x800) | |
16373 | inst.instruction = 0xee010f40; | |
16374 | /* vsub. */ | |
16375 | else if (((unsigned)inst.instruction) == 0x1000800) | |
16376 | inst.instruction = 0xee011f40; | |
7df54120 AV |
16377 | /* vhadd. */ |
16378 | else if (((unsigned)inst.instruction) == 0) | |
16379 | inst.instruction = 0xee000f40; | |
16380 | /* vhsub. */ | |
16381 | else if (((unsigned)inst.instruction) == 0x200) | |
16382 | inst.instruction = 0xee001f40; | |
a8465a06 AV |
16383 | /* vmla. */ |
16384 | else if (((unsigned)inst.instruction) == 0x900) | |
16385 | inst.instruction = 0xee010e40; | |
16386 | /* vmul. */ | |
16387 | else if (((unsigned)inst.instruction) == 0x910) | |
16388 | inst.instruction = 0xee011e60; | |
16389 | /* vqadd. */ | |
16390 | else if (((unsigned)inst.instruction) == 0x10) | |
16391 | inst.instruction = 0xee000f60; | |
16392 | /* vqsub. */ | |
16393 | else if (((unsigned)inst.instruction) == 0x210) | |
16394 | inst.instruction = 0xee001f60; | |
42b16635 AV |
16395 | /* vqrdmlah. */ |
16396 | else if (((unsigned)inst.instruction) == 0x3000b10) | |
16397 | inst.instruction = 0xee000e40; | |
16398 | /* vqdmulh. */ | |
16399 | else if (((unsigned)inst.instruction) == 0x0000b00) | |
16400 | inst.instruction = 0xee010e60; | |
16401 | /* vqrdmulh. */ | |
16402 | else if (((unsigned)inst.instruction) == 0x1000b00) | |
16403 | inst.instruction = 0xfe010e60; | |
7df54120 AV |
16404 | |
16405 | /* Set U-bit. */ | |
16406 | inst.instruction |= U << 28; | |
16407 | ||
5ee91343 AV |
16408 | /* Setting bits for size. */ |
16409 | inst.instruction |= neon_logbits (size) << 20; | |
16410 | } | |
16411 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16412 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16413 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16414 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16415 | inst.instruction |= inst.operands[2].reg; | |
16416 | inst.is_neon = 1; | |
16417 | } | |
16418 | ||
a302e574 AV |
16419 | static void |
16420 | mve_encode_rqq (unsigned bit28, unsigned size) | |
16421 | { | |
16422 | inst.instruction |= bit28 << 28; | |
16423 | inst.instruction |= neon_logbits (size) << 20; | |
16424 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16425 | inst.instruction |= inst.operands[0].reg << 12; | |
16426 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16427 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
16428 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16429 | inst.is_neon = 1; | |
16430 | } | |
16431 | ||
886e1c73 AV |
16432 | static void |
16433 | mve_encode_qqq (int ubit, int size) | |
16434 | { | |
16435 | ||
16436 | inst.instruction |= (ubit != 0) << 28; | |
16437 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16438 | inst.instruction |= neon_logbits (size) << 20; | |
16439 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16440 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16441 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16442 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
16443 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16444 | ||
16445 | inst.is_neon = 1; | |
16446 | } | |
16447 | ||
26c1e780 AV |
16448 | static void |
16449 | mve_encode_rq (unsigned bit28, unsigned size) | |
16450 | { | |
16451 | inst.instruction |= bit28 << 28; | |
16452 | inst.instruction |= neon_logbits (size) << 18; | |
16453 | inst.instruction |= inst.operands[0].reg << 12; | |
16454 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16455 | inst.is_neon = 1; | |
16456 | } | |
886e1c73 | 16457 | |
93925576 AV |
16458 | static void |
16459 | mve_encode_rrqq (unsigned U, unsigned size) | |
16460 | { | |
16461 | constraint (inst.operands[3].reg > 14, MVE_BAD_QREG); | |
16462 | ||
16463 | inst.instruction |= U << 28; | |
16464 | inst.instruction |= (inst.operands[1].reg >> 1) << 20; | |
16465 | inst.instruction |= LOW4 (inst.operands[2].reg) << 16; | |
16466 | inst.instruction |= (size == 32) << 16; | |
16467 | inst.instruction |= inst.operands[0].reg << 12; | |
16468 | inst.instruction |= HI1 (inst.operands[2].reg) << 7; | |
16469 | inst.instruction |= inst.operands[3].reg; | |
16470 | inst.is_neon = 1; | |
16471 | } | |
16472 | ||
037e8744 JB |
16473 | /* Encode insns with bit pattern: |
16474 | ||
16475 | |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
16476 | | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | | |
5f4273c7 | 16477 | |
037e8744 JB |
16478 | SIZE is passed in bits. -1 means size field isn't changed, in case it has a |
16479 | different meaning for some instruction. */ | |
16480 | ||
16481 | static void | |
16482 | neon_three_same (int isquad, int ubit, int size) | |
16483 | { | |
16484 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16485 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16486 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16487 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16488 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16489 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
16490 | inst.instruction |= (isquad != 0) << 6; | |
16491 | inst.instruction |= (ubit != 0) << 24; | |
16492 | if (size != -1) | |
16493 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 16494 | |
88714cb8 | 16495 | neon_dp_fixup (&inst); |
037e8744 JB |
16496 | } |
16497 | ||
16498 | /* Encode instructions of the form: | |
16499 | ||
16500 | |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| | |
16501 | | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | | |
5287ad62 JB |
16502 | |
16503 | Don't write size if SIZE == -1. */ | |
16504 | ||
16505 | static void | |
16506 | neon_two_same (int qbit, int ubit, int size) | |
16507 | { | |
16508 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16509 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16510 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16511 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
16512 | inst.instruction |= (qbit != 0) << 6; | |
16513 | inst.instruction |= (ubit != 0) << 24; | |
16514 | ||
16515 | if (size != -1) | |
16516 | inst.instruction |= neon_logbits (size) << 18; | |
16517 | ||
88714cb8 | 16518 | neon_dp_fixup (&inst); |
5287ad62 JB |
16519 | } |
16520 | ||
7df54120 AV |
16521 | enum vfp_or_neon_is_neon_bits |
16522 | { | |
16523 | NEON_CHECK_CC = 1, | |
16524 | NEON_CHECK_ARCH = 2, | |
16525 | NEON_CHECK_ARCH8 = 4 | |
16526 | }; | |
16527 | ||
16528 | /* Call this function if an instruction which may have belonged to the VFP or | |
16529 | Neon instruction sets, but turned out to be a Neon instruction (due to the | |
16530 | operand types involved, etc.). We have to check and/or fix-up a couple of | |
16531 | things: | |
16532 | ||
16533 | - Make sure the user hasn't attempted to make a Neon instruction | |
16534 | conditional. | |
16535 | - Alter the value in the condition code field if necessary. | |
16536 | - Make sure that the arch supports Neon instructions. | |
16537 | ||
16538 | Which of these operations take place depends on bits from enum | |
16539 | vfp_or_neon_is_neon_bits. | |
16540 | ||
16541 | WARNING: This function has side effects! If NEON_CHECK_CC is used and the | |
16542 | current instruction's condition is COND_ALWAYS, the condition field is | |
16543 | changed to inst.uncond_value. This is necessary because instructions shared | |
16544 | between VFP and Neon may be conditional for the VFP variants only, and the | |
16545 | unconditional Neon version must have, e.g., 0xF in the condition field. */ | |
16546 | ||
16547 | static int | |
16548 | vfp_or_neon_is_neon (unsigned check) | |
16549 | { | |
16550 | /* Conditions are always legal in Thumb mode (IT blocks). */ | |
16551 | if (!thumb_mode && (check & NEON_CHECK_CC)) | |
16552 | { | |
16553 | if (inst.cond != COND_ALWAYS) | |
16554 | { | |
16555 | first_error (_(BAD_COND)); | |
16556 | return FAIL; | |
16557 | } | |
16558 | if (inst.uncond_value != -1) | |
16559 | inst.instruction |= inst.uncond_value << 28; | |
16560 | } | |
16561 | ||
16562 | ||
16563 | if (((check & NEON_CHECK_ARCH) && !mark_feature_used (&fpu_neon_ext_v1)) | |
16564 | || ((check & NEON_CHECK_ARCH8) | |
16565 | && !mark_feature_used (&fpu_neon_ext_armv8))) | |
16566 | { | |
16567 | first_error (_(BAD_FPU)); | |
16568 | return FAIL; | |
16569 | } | |
16570 | ||
16571 | return SUCCESS; | |
16572 | } | |
16573 | ||
64c350f2 AV |
16574 | |
16575 | /* Return TRUE if the SIMD instruction is available for the current | |
16576 | cpu_variant. FP is set to TRUE if this is a SIMD floating-point | |
16577 | instruction. CHECK contains th. CHECK contains the set of bits to pass to | |
16578 | vfp_or_neon_is_neon for the NEON specific checks. */ | |
16579 | ||
16580 | static bfd_boolean | |
7df54120 AV |
16581 | check_simd_pred_availability (int fp, unsigned check) |
16582 | { | |
16583 | if (inst.cond > COND_ALWAYS) | |
16584 | { | |
16585 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
16586 | { | |
16587 | inst.error = BAD_FPU; | |
64c350f2 | 16588 | return FALSE; |
7df54120 AV |
16589 | } |
16590 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
16591 | } | |
16592 | else if (inst.cond < COND_ALWAYS) | |
16593 | { | |
16594 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
16595 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16596 | else if (vfp_or_neon_is_neon (check) == FAIL) | |
64c350f2 | 16597 | return FALSE; |
7df54120 AV |
16598 | } |
16599 | else | |
16600 | { | |
16601 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fp ? mve_fp_ext : mve_ext) | |
16602 | && vfp_or_neon_is_neon (check) == FAIL) | |
64c350f2 | 16603 | return FALSE; |
7df54120 AV |
16604 | |
16605 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
16606 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16607 | } | |
64c350f2 | 16608 | return TRUE; |
7df54120 AV |
16609 | } |
16610 | ||
5287ad62 JB |
16611 | /* Neon instruction encoders, in approximate order of appearance. */ |
16612 | ||
16613 | static void | |
16614 | do_neon_dyadic_i_su (void) | |
16615 | { | |
64c350f2 | 16616 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
7df54120 AV |
16617 | return; |
16618 | ||
16619 | enum neon_shape rs; | |
16620 | struct neon_type_el et; | |
16621 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
16622 | rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL); | |
16623 | else | |
16624 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
16625 | ||
16626 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_32 | N_KEY); | |
16627 | ||
16628 | ||
16629 | if (rs != NS_QQR) | |
16630 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
16631 | else | |
16632 | mve_encode_qqr (et.size, et.type == NT_unsigned, 0); | |
5287ad62 JB |
16633 | } |
16634 | ||
16635 | static void | |
16636 | do_neon_dyadic_i64_su (void) | |
16637 | { | |
64c350f2 | 16638 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
a8465a06 AV |
16639 | return; |
16640 | enum neon_shape rs; | |
16641 | struct neon_type_el et; | |
16642 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
16643 | { | |
16644 | rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL); | |
16645 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); | |
16646 | } | |
16647 | else | |
16648 | { | |
16649 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
16650 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
16651 | } | |
16652 | if (rs == NS_QQR) | |
16653 | mve_encode_qqr (et.size, et.type == NT_unsigned, 0); | |
16654 | else | |
16655 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
5287ad62 JB |
16656 | } |
16657 | ||
16658 | static void | |
16659 | neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, | |
477330fc | 16660 | unsigned immbits) |
5287ad62 JB |
16661 | { |
16662 | unsigned size = et.size >> 3; | |
16663 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16664 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16665 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16666 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
16667 | inst.instruction |= (isquad != 0) << 6; | |
16668 | inst.instruction |= immbits << 16; | |
16669 | inst.instruction |= (size >> 3) << 7; | |
16670 | inst.instruction |= (size & 0x7) << 19; | |
16671 | if (write_ubit) | |
16672 | inst.instruction |= (uval != 0) << 24; | |
16673 | ||
88714cb8 | 16674 | neon_dp_fixup (&inst); |
5287ad62 JB |
16675 | } |
16676 | ||
16677 | static void | |
5150f0d8 | 16678 | do_neon_shl (void) |
5287ad62 | 16679 | { |
64c350f2 | 16680 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
5150f0d8 AV |
16681 | return; |
16682 | ||
5287ad62 JB |
16683 | if (!inst.operands[2].isreg) |
16684 | { | |
5150f0d8 AV |
16685 | enum neon_shape rs; |
16686 | struct neon_type_el et; | |
16687 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
16688 | { | |
16689 | rs = neon_select_shape (NS_QQI, NS_NULL); | |
16690 | et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_MVE); | |
16691 | } | |
16692 | else | |
16693 | { | |
16694 | rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); | |
16695 | et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); | |
16696 | } | |
cb3b1e65 JB |
16697 | int imm = inst.operands[2].imm; |
16698 | ||
16699 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
16700 | _("immediate out of range for shift")); | |
88714cb8 | 16701 | NEON_ENCODE (IMMED, inst); |
cb3b1e65 | 16702 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
16703 | } |
16704 | else | |
16705 | { | |
5150f0d8 AV |
16706 | enum neon_shape rs; |
16707 | struct neon_type_el et; | |
16708 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
16709 | { | |
16710 | rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL); | |
16711 | et = neon_check_type (3, rs, N_EQK, N_SU_MVE | N_KEY, N_EQK | N_EQK); | |
16712 | } | |
16713 | else | |
16714 | { | |
16715 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
16716 | et = neon_check_type (3, rs, N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
16717 | } | |
16718 | ||
16719 | ||
16720 | if (rs == NS_QQR) | |
16721 | { | |
16722 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
16723 | _("invalid instruction shape")); | |
16724 | if (inst.operands[2].reg == REG_SP) | |
16725 | as_tsktsk (MVE_BAD_SP); | |
16726 | else if (inst.operands[2].reg == REG_PC) | |
16727 | as_tsktsk (MVE_BAD_PC); | |
16728 | ||
16729 | inst.instruction = 0xee311e60; | |
16730 | inst.instruction |= (et.type == NT_unsigned) << 28; | |
16731 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16732 | inst.instruction |= neon_logbits (et.size) << 18; | |
16733 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16734 | inst.instruction |= inst.operands[2].reg; | |
16735 | inst.is_neon = 1; | |
16736 | } | |
16737 | else | |
16738 | { | |
16739 | unsigned int tmp; | |
16740 | ||
16741 | /* VSHL/VQSHL 3-register variants have syntax such as: | |
16742 | vshl.xx Dd, Dm, Dn | |
16743 | whereas other 3-register operations encoded by neon_three_same have | |
16744 | syntax like: | |
16745 | vadd.xx Dd, Dn, Dm | |
16746 | (i.e. with Dn & Dm reversed). Swap operands[1].reg and | |
16747 | operands[2].reg here. */ | |
16748 | tmp = inst.operands[2].reg; | |
16749 | inst.operands[2].reg = inst.operands[1].reg; | |
16750 | inst.operands[1].reg = tmp; | |
16751 | NEON_ENCODE (INTEGER, inst); | |
16752 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
16753 | } | |
5287ad62 JB |
16754 | } |
16755 | } | |
16756 | ||
16757 | static void | |
5150f0d8 | 16758 | do_neon_qshl (void) |
5287ad62 | 16759 | { |
64c350f2 | 16760 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
5150f0d8 AV |
16761 | return; |
16762 | ||
5287ad62 JB |
16763 | if (!inst.operands[2].isreg) |
16764 | { | |
5150f0d8 AV |
16765 | enum neon_shape rs; |
16766 | struct neon_type_el et; | |
16767 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
16768 | { | |
16769 | rs = neon_select_shape (NS_QQI, NS_NULL); | |
16770 | et = neon_check_type (2, rs, N_EQK, N_KEY | N_SU_MVE); | |
16771 | } | |
16772 | else | |
16773 | { | |
16774 | rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); | |
16775 | et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); | |
16776 | } | |
cb3b1e65 | 16777 | int imm = inst.operands[2].imm; |
627907b7 | 16778 | |
cb3b1e65 JB |
16779 | constraint (imm < 0 || (unsigned)imm >= et.size, |
16780 | _("immediate out of range for shift")); | |
88714cb8 | 16781 | NEON_ENCODE (IMMED, inst); |
cb3b1e65 | 16782 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm); |
5287ad62 JB |
16783 | } |
16784 | else | |
16785 | { | |
5150f0d8 AV |
16786 | enum neon_shape rs; |
16787 | struct neon_type_el et; | |
627907b7 | 16788 | |
5150f0d8 AV |
16789 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
16790 | { | |
16791 | rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL); | |
16792 | et = neon_check_type (3, rs, N_EQK, N_SU_MVE | N_KEY, N_EQK | N_EQK); | |
16793 | } | |
16794 | else | |
16795 | { | |
16796 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
16797 | et = neon_check_type (3, rs, N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
16798 | } | |
16799 | ||
16800 | if (rs == NS_QQR) | |
16801 | { | |
16802 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
16803 | _("invalid instruction shape")); | |
16804 | if (inst.operands[2].reg == REG_SP) | |
16805 | as_tsktsk (MVE_BAD_SP); | |
16806 | else if (inst.operands[2].reg == REG_PC) | |
16807 | as_tsktsk (MVE_BAD_PC); | |
16808 | ||
16809 | inst.instruction = 0xee311ee0; | |
16810 | inst.instruction |= (et.type == NT_unsigned) << 28; | |
16811 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16812 | inst.instruction |= neon_logbits (et.size) << 18; | |
16813 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16814 | inst.instruction |= inst.operands[2].reg; | |
16815 | inst.is_neon = 1; | |
16816 | } | |
16817 | else | |
16818 | { | |
16819 | unsigned int tmp; | |
16820 | ||
16821 | /* See note in do_neon_shl. */ | |
16822 | tmp = inst.operands[2].reg; | |
16823 | inst.operands[2].reg = inst.operands[1].reg; | |
16824 | inst.operands[1].reg = tmp; | |
16825 | NEON_ENCODE (INTEGER, inst); | |
16826 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
16827 | } | |
5287ad62 JB |
16828 | } |
16829 | } | |
16830 | ||
627907b7 JB |
16831 | static void |
16832 | do_neon_rshl (void) | |
16833 | { | |
64c350f2 | 16834 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
1be7aba3 AV |
16835 | return; |
16836 | ||
16837 | enum neon_shape rs; | |
16838 | struct neon_type_el et; | |
16839 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
16840 | { | |
16841 | rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL); | |
16842 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); | |
16843 | } | |
16844 | else | |
16845 | { | |
16846 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
16847 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
16848 | } | |
16849 | ||
627907b7 JB |
16850 | unsigned int tmp; |
16851 | ||
1be7aba3 AV |
16852 | if (rs == NS_QQR) |
16853 | { | |
16854 | if (inst.operands[2].reg == REG_PC) | |
16855 | as_tsktsk (MVE_BAD_PC); | |
16856 | else if (inst.operands[2].reg == REG_SP) | |
16857 | as_tsktsk (MVE_BAD_SP); | |
16858 | ||
16859 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
16860 | _("invalid instruction shape")); | |
16861 | ||
16862 | if (inst.instruction == 0x0000510) | |
16863 | /* We are dealing with vqrshl. */ | |
16864 | inst.instruction = 0xee331ee0; | |
16865 | else | |
16866 | /* We are dealing with vrshl. */ | |
16867 | inst.instruction = 0xee331e60; | |
16868 | ||
16869 | inst.instruction |= (et.type == NT_unsigned) << 28; | |
16870 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16871 | inst.instruction |= neon_logbits (et.size) << 18; | |
16872 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16873 | inst.instruction |= inst.operands[2].reg; | |
16874 | inst.is_neon = 1; | |
16875 | } | |
16876 | else | |
16877 | { | |
16878 | tmp = inst.operands[2].reg; | |
16879 | inst.operands[2].reg = inst.operands[1].reg; | |
16880 | inst.operands[1].reg = tmp; | |
16881 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
16882 | } | |
627907b7 JB |
16883 | } |
16884 | ||
5287ad62 JB |
16885 | static int |
16886 | neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) | |
16887 | { | |
036dc3f7 PB |
16888 | /* Handle .I8 pseudo-instructions. */ |
16889 | if (size == 8) | |
5287ad62 | 16890 | { |
5287ad62 | 16891 | /* Unfortunately, this will make everything apart from zero out-of-range. |
477330fc RM |
16892 | FIXME is this the intended semantics? There doesn't seem much point in |
16893 | accepting .I8 if so. */ | |
5287ad62 JB |
16894 | immediate |= immediate << 8; |
16895 | size = 16; | |
036dc3f7 PB |
16896 | } |
16897 | ||
16898 | if (size >= 32) | |
16899 | { | |
16900 | if (immediate == (immediate & 0x000000ff)) | |
16901 | { | |
16902 | *immbits = immediate; | |
16903 | return 0x1; | |
16904 | } | |
16905 | else if (immediate == (immediate & 0x0000ff00)) | |
16906 | { | |
16907 | *immbits = immediate >> 8; | |
16908 | return 0x3; | |
16909 | } | |
16910 | else if (immediate == (immediate & 0x00ff0000)) | |
16911 | { | |
16912 | *immbits = immediate >> 16; | |
16913 | return 0x5; | |
16914 | } | |
16915 | else if (immediate == (immediate & 0xff000000)) | |
16916 | { | |
16917 | *immbits = immediate >> 24; | |
16918 | return 0x7; | |
16919 | } | |
16920 | if ((immediate & 0xffff) != (immediate >> 16)) | |
16921 | goto bad_immediate; | |
16922 | immediate &= 0xffff; | |
5287ad62 JB |
16923 | } |
16924 | ||
16925 | if (immediate == (immediate & 0x000000ff)) | |
16926 | { | |
16927 | *immbits = immediate; | |
036dc3f7 | 16928 | return 0x9; |
5287ad62 JB |
16929 | } |
16930 | else if (immediate == (immediate & 0x0000ff00)) | |
16931 | { | |
16932 | *immbits = immediate >> 8; | |
036dc3f7 | 16933 | return 0xb; |
5287ad62 JB |
16934 | } |
16935 | ||
16936 | bad_immediate: | |
dcbf9037 | 16937 | first_error (_("immediate value out of range")); |
5287ad62 JB |
16938 | return FAIL; |
16939 | } | |
16940 | ||
5287ad62 JB |
16941 | static void |
16942 | do_neon_logic (void) | |
16943 | { | |
16944 | if (inst.operands[2].present && inst.operands[2].isreg) | |
16945 | { | |
037e8744 | 16946 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
f601a00c | 16947 | if (rs == NS_QQQ |
64c350f2 AV |
16948 | && !check_simd_pred_availability (FALSE, |
16949 | NEON_CHECK_ARCH | NEON_CHECK_CC)) | |
f601a00c AV |
16950 | return; |
16951 | else if (rs != NS_QQQ | |
16952 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) | |
16953 | first_error (BAD_FPU); | |
16954 | ||
5287ad62 JB |
16955 | neon_check_type (3, rs, N_IGNORE_TYPE); |
16956 | /* U bit and size field were set as part of the bitmask. */ | |
88714cb8 | 16957 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 16958 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
16959 | } |
16960 | else | |
16961 | { | |
4316f0d2 DG |
16962 | const int three_ops_form = (inst.operands[2].present |
16963 | && !inst.operands[2].isreg); | |
16964 | const int immoperand = (three_ops_form ? 2 : 1); | |
16965 | enum neon_shape rs = (three_ops_form | |
16966 | ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL) | |
16967 | : neon_select_shape (NS_DI, NS_QI, NS_NULL)); | |
f601a00c AV |
16968 | /* Because neon_select_shape makes the second operand a copy of the first |
16969 | if the second operand is not present. */ | |
16970 | if (rs == NS_QQI | |
64c350f2 AV |
16971 | && !check_simd_pred_availability (FALSE, |
16972 | NEON_CHECK_ARCH | NEON_CHECK_CC)) | |
f601a00c AV |
16973 | return; |
16974 | else if (rs != NS_QQI | |
16975 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) | |
16976 | first_error (BAD_FPU); | |
16977 | ||
16978 | struct neon_type_el et; | |
16979 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
16980 | et = neon_check_type (2, rs, N_I32 | N_I16 | N_KEY, N_EQK); | |
16981 | else | |
16982 | et = neon_check_type (2, rs, N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | |
16983 | | N_KEY, N_EQK); | |
16984 | ||
16985 | if (et.type == NT_invtype) | |
16986 | return; | |
21d799b5 | 16987 | enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff; |
5287ad62 JB |
16988 | unsigned immbits; |
16989 | int cmode; | |
5f4273c7 | 16990 | |
5f4273c7 | 16991 | |
4316f0d2 DG |
16992 | if (three_ops_form) |
16993 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
16994 | _("first and second operands shall be the same register")); | |
16995 | ||
88714cb8 | 16996 | NEON_ENCODE (IMMED, inst); |
5287ad62 | 16997 | |
4316f0d2 | 16998 | immbits = inst.operands[immoperand].imm; |
036dc3f7 PB |
16999 | if (et.size == 64) |
17000 | { | |
17001 | /* .i64 is a pseudo-op, so the immediate must be a repeating | |
17002 | pattern. */ | |
4316f0d2 DG |
17003 | if (immbits != (inst.operands[immoperand].regisimm ? |
17004 | inst.operands[immoperand].reg : 0)) | |
036dc3f7 PB |
17005 | { |
17006 | /* Set immbits to an invalid constant. */ | |
17007 | immbits = 0xdeadbeef; | |
17008 | } | |
17009 | } | |
17010 | ||
5287ad62 | 17011 | switch (opcode) |
477330fc RM |
17012 | { |
17013 | case N_MNEM_vbic: | |
17014 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
17015 | break; | |
17016 | ||
17017 | case N_MNEM_vorr: | |
17018 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
17019 | break; | |
17020 | ||
17021 | case N_MNEM_vand: | |
17022 | /* Pseudo-instruction for VBIC. */ | |
17023 | neon_invert_size (&immbits, 0, et.size); | |
17024 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
17025 | break; | |
17026 | ||
17027 | case N_MNEM_vorn: | |
17028 | /* Pseudo-instruction for VORR. */ | |
17029 | neon_invert_size (&immbits, 0, et.size); | |
17030 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
17031 | break; | |
17032 | ||
17033 | default: | |
17034 | abort (); | |
17035 | } | |
5287ad62 JB |
17036 | |
17037 | if (cmode == FAIL) | |
477330fc | 17038 | return; |
5287ad62 | 17039 | |
037e8744 | 17040 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
17041 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
17042 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17043 | inst.instruction |= cmode << 8; | |
17044 | neon_write_immbits (immbits); | |
5f4273c7 | 17045 | |
88714cb8 | 17046 | neon_dp_fixup (&inst); |
5287ad62 JB |
17047 | } |
17048 | } | |
17049 | ||
17050 | static void | |
17051 | do_neon_bitfield (void) | |
17052 | { | |
037e8744 | 17053 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 17054 | neon_check_type (3, rs, N_IGNORE_TYPE); |
037e8744 | 17055 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
17056 | } |
17057 | ||
17058 | static void | |
dcbf9037 | 17059 | neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, |
477330fc | 17060 | unsigned destbits) |
5287ad62 | 17061 | { |
5ee91343 | 17062 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL); |
dcbf9037 | 17063 | struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, |
477330fc | 17064 | types | N_KEY); |
5287ad62 JB |
17065 | if (et.type == NT_float) |
17066 | { | |
88714cb8 | 17067 | NEON_ENCODE (FLOAT, inst); |
5ee91343 | 17068 | if (rs == NS_QQR) |
7df54120 | 17069 | mve_encode_qqr (et.size, 0, 1); |
5ee91343 AV |
17070 | else |
17071 | neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1); | |
5287ad62 JB |
17072 | } |
17073 | else | |
17074 | { | |
88714cb8 | 17075 | NEON_ENCODE (INTEGER, inst); |
5ee91343 | 17076 | if (rs == NS_QQR) |
a8465a06 | 17077 | mve_encode_qqr (et.size, et.type == ubit_meaning, 0); |
5ee91343 AV |
17078 | else |
17079 | neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); | |
5287ad62 JB |
17080 | } |
17081 | } | |
17082 | ||
5287ad62 JB |
17083 | |
17084 | static void | |
17085 | do_neon_dyadic_if_su_d (void) | |
17086 | { | |
17087 | /* This version only allow D registers, but that constraint is enforced during | |
17088 | operand parsing so we don't need to do anything extra here. */ | |
dcbf9037 | 17089 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
17090 | } |
17091 | ||
5287ad62 JB |
17092 | static void |
17093 | do_neon_dyadic_if_i_d (void) | |
17094 | { | |
428e3f1f PB |
17095 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
17096 | affected if we specify unsigned args. */ | |
17097 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
5287ad62 JB |
17098 | } |
17099 | ||
f5f10c66 AV |
17100 | static void |
17101 | do_mve_vstr_vldr_QI (int size, int elsize, int load) | |
17102 | { | |
17103 | constraint (size < 32, BAD_ADDR_MODE); | |
17104 | constraint (size != elsize, BAD_EL_TYPE); | |
17105 | constraint (inst.operands[1].immisreg, BAD_ADDR_MODE); | |
17106 | constraint (!inst.operands[1].preind, BAD_ADDR_MODE); | |
17107 | constraint (load && inst.operands[0].reg == inst.operands[1].reg, | |
17108 | _("destination register and offset register may not be the" | |
17109 | " same")); | |
17110 | ||
17111 | int imm = inst.relocs[0].exp.X_add_number; | |
17112 | int add = 1; | |
17113 | if (imm < 0) | |
17114 | { | |
17115 | add = 0; | |
17116 | imm = -imm; | |
17117 | } | |
17118 | constraint ((imm % (size / 8) != 0) | |
17119 | || imm > (0x7f << neon_logbits (size)), | |
17120 | (size == 32) ? _("immediate must be a multiple of 4 in the" | |
17121 | " range of +/-[0,508]") | |
17122 | : _("immediate must be a multiple of 8 in the" | |
17123 | " range of +/-[0,1016]")); | |
17124 | inst.instruction |= 0x11 << 24; | |
17125 | inst.instruction |= add << 23; | |
17126 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17127 | inst.instruction |= inst.operands[1].writeback << 21; | |
17128 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
17129 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
17130 | inst.instruction |= 1 << 12; | |
17131 | inst.instruction |= (size == 64) << 8; | |
17132 | inst.instruction &= 0xffffff00; | |
17133 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
17134 | inst.instruction |= imm >> neon_logbits (size); | |
17135 | } | |
17136 | ||
17137 | static void | |
17138 | do_mve_vstr_vldr_RQ (int size, int elsize, int load) | |
17139 | { | |
17140 | unsigned os = inst.operands[1].imm >> 5; | |
17141 | constraint (os != 0 && size == 8, | |
17142 | _("can not shift offsets when accessing less than half-word")); | |
17143 | constraint (os && os != neon_logbits (size), | |
17144 | _("shift immediate must be 1, 2 or 3 for half-word, word" | |
17145 | " or double-word accesses respectively")); | |
17146 | if (inst.operands[1].reg == REG_PC) | |
17147 | as_tsktsk (MVE_BAD_PC); | |
17148 | ||
17149 | switch (size) | |
17150 | { | |
17151 | case 8: | |
17152 | constraint (elsize >= 64, BAD_EL_TYPE); | |
17153 | break; | |
17154 | case 16: | |
17155 | constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE); | |
17156 | break; | |
17157 | case 32: | |
17158 | case 64: | |
17159 | constraint (elsize != size, BAD_EL_TYPE); | |
17160 | break; | |
17161 | default: | |
17162 | break; | |
17163 | } | |
17164 | constraint (inst.operands[1].writeback || !inst.operands[1].preind, | |
17165 | BAD_ADDR_MODE); | |
17166 | if (load) | |
17167 | { | |
17168 | constraint (inst.operands[0].reg == (inst.operands[1].imm & 0x1f), | |
17169 | _("destination register and offset register may not be" | |
17170 | " the same")); | |
17171 | constraint (size == elsize && inst.vectype.el[0].type != NT_unsigned, | |
17172 | BAD_EL_TYPE); | |
17173 | constraint (inst.vectype.el[0].type != NT_unsigned | |
17174 | && inst.vectype.el[0].type != NT_signed, BAD_EL_TYPE); | |
17175 | inst.instruction |= (inst.vectype.el[0].type == NT_unsigned) << 28; | |
17176 | } | |
17177 | else | |
17178 | { | |
17179 | constraint (inst.vectype.el[0].type != NT_untyped, BAD_EL_TYPE); | |
17180 | } | |
17181 | ||
17182 | inst.instruction |= 1 << 23; | |
17183 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17184 | inst.instruction |= inst.operands[1].reg << 16; | |
17185 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
17186 | inst.instruction |= neon_logbits (elsize) << 7; | |
17187 | inst.instruction |= HI1 (inst.operands[1].imm) << 5; | |
17188 | inst.instruction |= LOW4 (inst.operands[1].imm); | |
17189 | inst.instruction |= !!os; | |
17190 | } | |
17191 | ||
17192 | static void | |
17193 | do_mve_vstr_vldr_RI (int size, int elsize, int load) | |
17194 | { | |
17195 | enum neon_el_type type = inst.vectype.el[0].type; | |
17196 | ||
17197 | constraint (size >= 64, BAD_ADDR_MODE); | |
17198 | switch (size) | |
17199 | { | |
17200 | case 16: | |
17201 | constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE); | |
17202 | break; | |
17203 | case 32: | |
17204 | constraint (elsize != size, BAD_EL_TYPE); | |
17205 | break; | |
17206 | default: | |
17207 | break; | |
17208 | } | |
17209 | if (load) | |
17210 | { | |
17211 | constraint (elsize != size && type != NT_unsigned | |
17212 | && type != NT_signed, BAD_EL_TYPE); | |
17213 | } | |
17214 | else | |
17215 | { | |
17216 | constraint (elsize != size && type != NT_untyped, BAD_EL_TYPE); | |
17217 | } | |
17218 | ||
17219 | int imm = inst.relocs[0].exp.X_add_number; | |
17220 | int add = 1; | |
17221 | if (imm < 0) | |
17222 | { | |
17223 | add = 0; | |
17224 | imm = -imm; | |
17225 | } | |
17226 | ||
17227 | if ((imm % (size / 8) != 0) || imm > (0x7f << neon_logbits (size))) | |
17228 | { | |
17229 | switch (size) | |
17230 | { | |
17231 | case 8: | |
17232 | constraint (1, _("immediate must be in the range of +/-[0,127]")); | |
17233 | break; | |
17234 | case 16: | |
17235 | constraint (1, _("immediate must be a multiple of 2 in the" | |
17236 | " range of +/-[0,254]")); | |
17237 | break; | |
17238 | case 32: | |
17239 | constraint (1, _("immediate must be a multiple of 4 in the" | |
17240 | " range of +/-[0,508]")); | |
17241 | break; | |
17242 | } | |
17243 | } | |
17244 | ||
17245 | if (size != elsize) | |
17246 | { | |
17247 | constraint (inst.operands[1].reg > 7, BAD_HIREG); | |
17248 | constraint (inst.operands[0].reg > 14, | |
17249 | _("MVE vector register in the range [Q0..Q7] expected")); | |
17250 | inst.instruction |= (load && type == NT_unsigned) << 28; | |
17251 | inst.instruction |= (size == 16) << 19; | |
17252 | inst.instruction |= neon_logbits (elsize) << 7; | |
17253 | } | |
17254 | else | |
17255 | { | |
17256 | if (inst.operands[1].reg == REG_PC) | |
17257 | as_tsktsk (MVE_BAD_PC); | |
17258 | else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback) | |
17259 | as_tsktsk (MVE_BAD_SP); | |
17260 | inst.instruction |= 1 << 12; | |
17261 | inst.instruction |= neon_logbits (size) << 7; | |
17262 | } | |
17263 | inst.instruction |= inst.operands[1].preind << 24; | |
17264 | inst.instruction |= add << 23; | |
17265 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17266 | inst.instruction |= inst.operands[1].writeback << 21; | |
17267 | inst.instruction |= inst.operands[1].reg << 16; | |
17268 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
17269 | inst.instruction &= 0xffffff80; | |
17270 | inst.instruction |= imm >> neon_logbits (size); | |
17271 | ||
17272 | } | |
17273 | ||
17274 | static void | |
17275 | do_mve_vstr_vldr (void) | |
17276 | { | |
17277 | unsigned size; | |
17278 | int load = 0; | |
17279 | ||
17280 | if (inst.cond > COND_ALWAYS) | |
17281 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
17282 | else | |
17283 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
17284 | ||
17285 | switch (inst.instruction) | |
17286 | { | |
17287 | default: | |
17288 | gas_assert (0); | |
17289 | break; | |
17290 | case M_MNEM_vldrb: | |
17291 | load = 1; | |
17292 | /* fall through. */ | |
17293 | case M_MNEM_vstrb: | |
17294 | size = 8; | |
17295 | break; | |
17296 | case M_MNEM_vldrh: | |
17297 | load = 1; | |
17298 | /* fall through. */ | |
17299 | case M_MNEM_vstrh: | |
17300 | size = 16; | |
17301 | break; | |
17302 | case M_MNEM_vldrw: | |
17303 | load = 1; | |
17304 | /* fall through. */ | |
17305 | case M_MNEM_vstrw: | |
17306 | size = 32; | |
17307 | break; | |
17308 | case M_MNEM_vldrd: | |
17309 | load = 1; | |
17310 | /* fall through. */ | |
17311 | case M_MNEM_vstrd: | |
17312 | size = 64; | |
17313 | break; | |
17314 | } | |
17315 | unsigned elsize = inst.vectype.el[0].size; | |
17316 | ||
17317 | if (inst.operands[1].isquad) | |
17318 | { | |
17319 | /* We are dealing with [Q, imm]{!} cases. */ | |
17320 | do_mve_vstr_vldr_QI (size, elsize, load); | |
17321 | } | |
17322 | else | |
17323 | { | |
17324 | if (inst.operands[1].immisreg == 2) | |
17325 | { | |
17326 | /* We are dealing with [R, Q, {UXTW #os}] cases. */ | |
17327 | do_mve_vstr_vldr_RQ (size, elsize, load); | |
17328 | } | |
17329 | else if (!inst.operands[1].immisreg) | |
17330 | { | |
17331 | /* We are dealing with [R, Imm]{!}/[R], Imm cases. */ | |
17332 | do_mve_vstr_vldr_RI (size, elsize, load); | |
17333 | } | |
17334 | else | |
17335 | constraint (1, BAD_ADDR_MODE); | |
17336 | } | |
17337 | ||
17338 | inst.is_neon = 1; | |
17339 | } | |
17340 | ||
35c228db AV |
17341 | static void |
17342 | do_mve_vst_vld (void) | |
17343 | { | |
17344 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
17345 | return; | |
17346 | ||
17347 | constraint (!inst.operands[1].preind || inst.relocs[0].exp.X_add_symbol != 0 | |
17348 | || inst.relocs[0].exp.X_add_number != 0 | |
17349 | || inst.operands[1].immisreg != 0, | |
17350 | BAD_ADDR_MODE); | |
17351 | constraint (inst.vectype.el[0].size > 32, BAD_EL_TYPE); | |
17352 | if (inst.operands[1].reg == REG_PC) | |
17353 | as_tsktsk (MVE_BAD_PC); | |
17354 | else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback) | |
17355 | as_tsktsk (MVE_BAD_SP); | |
17356 | ||
17357 | ||
17358 | /* These instructions are one of the "exceptions" mentioned in | |
17359 | handle_pred_state. They are MVE instructions that are not VPT compatible | |
17360 | and do not accept a VPT code, thus appending such a code is a syntax | |
17361 | error. */ | |
17362 | if (inst.cond > COND_ALWAYS) | |
17363 | first_error (BAD_SYNTAX); | |
17364 | /* If we append a scalar condition code we can set this to | |
17365 | MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */ | |
17366 | else if (inst.cond < COND_ALWAYS) | |
17367 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
17368 | else | |
17369 | inst.pred_insn_type = MVE_UNPREDICABLE_INSN; | |
17370 | ||
17371 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17372 | inst.instruction |= inst.operands[1].writeback << 21; | |
17373 | inst.instruction |= inst.operands[1].reg << 16; | |
17374 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
17375 | inst.instruction |= neon_logbits (inst.vectype.el[0].size) << 7; | |
17376 | inst.is_neon = 1; | |
17377 | } | |
17378 | ||
26c1e780 AV |
17379 | static void |
17380 | do_mve_vaddlv (void) | |
17381 | { | |
17382 | enum neon_shape rs = neon_select_shape (NS_RRQ, NS_NULL); | |
17383 | struct neon_type_el et | |
17384 | = neon_check_type (3, rs, N_EQK, N_EQK, N_S32 | N_U32 | N_KEY); | |
17385 | ||
17386 | if (et.type == NT_invtype) | |
17387 | first_error (BAD_EL_TYPE); | |
17388 | ||
17389 | if (inst.cond > COND_ALWAYS) | |
17390 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
17391 | else | |
17392 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
17393 | ||
17394 | constraint (inst.operands[1].reg > 14, MVE_BAD_QREG); | |
17395 | ||
17396 | inst.instruction |= (et.type == NT_unsigned) << 28; | |
17397 | inst.instruction |= inst.operands[1].reg << 19; | |
17398 | inst.instruction |= inst.operands[0].reg << 12; | |
17399 | inst.instruction |= inst.operands[2].reg; | |
17400 | inst.is_neon = 1; | |
17401 | } | |
17402 | ||
5287ad62 | 17403 | static void |
5ee91343 | 17404 | do_neon_dyadic_if_su (void) |
5287ad62 | 17405 | { |
5ee91343 AV |
17406 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL); |
17407 | struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK, | |
17408 | N_SUF_32 | N_KEY); | |
17409 | ||
935295b5 AV |
17410 | constraint ((inst.instruction == ((unsigned) N_MNEM_vmax) |
17411 | || inst.instruction == ((unsigned) N_MNEM_vmin)) | |
17412 | && et.type == NT_float | |
17413 | && !ARM_CPU_HAS_FEATURE (cpu_variant,fpu_neon_ext_v1), BAD_FPU); | |
17414 | ||
64c350f2 AV |
17415 | if (!check_simd_pred_availability (et.type == NT_float, |
17416 | NEON_CHECK_ARCH | NEON_CHECK_CC)) | |
037e8744 JB |
17417 | return; |
17418 | ||
5ee91343 AV |
17419 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
17420 | } | |
17421 | ||
17422 | static void | |
17423 | do_neon_addsub_if_i (void) | |
17424 | { | |
17425 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd) | |
17426 | && try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) | |
037e8744 JB |
17427 | return; |
17428 | ||
5ee91343 AV |
17429 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL); |
17430 | struct neon_type_el et = neon_check_type (3, rs, N_EQK, | |
17431 | N_EQK, N_IF_32 | N_I64 | N_KEY); | |
17432 | ||
17433 | constraint (rs == NS_QQR && et.size == 64, BAD_FPU); | |
17434 | /* If we are parsing Q registers and the element types match MVE, which NEON | |
17435 | also supports, then we must check whether this is an instruction that can | |
17436 | be used by both MVE/NEON. This distinction can be made based on whether | |
17437 | they are predicated or not. */ | |
17438 | if ((rs == NS_QQQ || rs == NS_QQR) && et.size != 64) | |
17439 | { | |
64c350f2 AV |
17440 | if (!check_simd_pred_availability (et.type == NT_float, |
17441 | NEON_CHECK_ARCH | NEON_CHECK_CC)) | |
5ee91343 AV |
17442 | return; |
17443 | } | |
17444 | else | |
17445 | { | |
17446 | /* If they are either in a D register or are using an unsupported. */ | |
17447 | if (rs != NS_QQR | |
17448 | && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
17449 | return; | |
17450 | } | |
17451 | ||
5287ad62 JB |
17452 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
17453 | affected if we specify unsigned args. */ | |
dcbf9037 | 17454 | neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); |
5287ad62 JB |
17455 | } |
17456 | ||
17457 | /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the | |
17458 | result to be: | |
17459 | V<op> A,B (A is operand 0, B is operand 2) | |
17460 | to mean: | |
17461 | V<op> A,B,A | |
17462 | not: | |
17463 | V<op> A,B,B | |
17464 | so handle that case specially. */ | |
17465 | ||
17466 | static void | |
17467 | neon_exchange_operands (void) | |
17468 | { | |
5287ad62 JB |
17469 | if (inst.operands[1].present) |
17470 | { | |
e1fa0163 NC |
17471 | void *scratch = xmalloc (sizeof (inst.operands[0])); |
17472 | ||
5287ad62 JB |
17473 | /* Swap operands[1] and operands[2]. */ |
17474 | memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); | |
17475 | inst.operands[1] = inst.operands[2]; | |
17476 | memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); | |
e1fa0163 | 17477 | free (scratch); |
5287ad62 JB |
17478 | } |
17479 | else | |
17480 | { | |
17481 | inst.operands[1] = inst.operands[2]; | |
17482 | inst.operands[2] = inst.operands[0]; | |
17483 | } | |
17484 | } | |
17485 | ||
17486 | static void | |
17487 | neon_compare (unsigned regtypes, unsigned immtypes, int invert) | |
17488 | { | |
17489 | if (inst.operands[2].isreg) | |
17490 | { | |
17491 | if (invert) | |
477330fc | 17492 | neon_exchange_operands (); |
dcbf9037 | 17493 | neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); |
5287ad62 JB |
17494 | } |
17495 | else | |
17496 | { | |
037e8744 | 17497 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
dcbf9037 | 17498 | struct neon_type_el et = neon_check_type (2, rs, |
477330fc | 17499 | N_EQK | N_SIZ, immtypes | N_KEY); |
5287ad62 | 17500 | |
88714cb8 | 17501 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
17502 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
17503 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17504 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
17505 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 17506 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
17507 | inst.instruction |= (et.type == NT_float) << 10; |
17508 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 17509 | |
88714cb8 | 17510 | neon_dp_fixup (&inst); |
5287ad62 JB |
17511 | } |
17512 | } | |
17513 | ||
17514 | static void | |
17515 | do_neon_cmp (void) | |
17516 | { | |
cc933301 | 17517 | neon_compare (N_SUF_32, N_S_32 | N_F_16_32, FALSE); |
5287ad62 JB |
17518 | } |
17519 | ||
17520 | static void | |
17521 | do_neon_cmp_inv (void) | |
17522 | { | |
cc933301 | 17523 | neon_compare (N_SUF_32, N_S_32 | N_F_16_32, TRUE); |
5287ad62 JB |
17524 | } |
17525 | ||
17526 | static void | |
17527 | do_neon_ceq (void) | |
17528 | { | |
17529 | neon_compare (N_IF_32, N_IF_32, FALSE); | |
17530 | } | |
17531 | ||
17532 | /* For multiply instructions, we have the possibility of 16-bit or 32-bit | |
17533 | scalars, which are encoded in 5 bits, M : Rm. | |
17534 | For 16-bit scalars, the register is encoded in Rm[2:0] and the index in | |
17535 | M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the | |
c604a79a JW |
17536 | index in M. |
17537 | ||
17538 | Dot Product instructions are similar to multiply instructions except elsize | |
17539 | should always be 32. | |
17540 | ||
17541 | This function translates SCALAR, which is GAS's internal encoding of indexed | |
17542 | scalar register, to raw encoding. There is also register and index range | |
17543 | check based on ELSIZE. */ | |
5287ad62 JB |
17544 | |
17545 | static unsigned | |
17546 | neon_scalar_for_mul (unsigned scalar, unsigned elsize) | |
17547 | { | |
dcbf9037 JB |
17548 | unsigned regno = NEON_SCALAR_REG (scalar); |
17549 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
5287ad62 JB |
17550 | |
17551 | switch (elsize) | |
17552 | { | |
17553 | case 16: | |
17554 | if (regno > 7 || elno > 3) | |
477330fc | 17555 | goto bad_scalar; |
5287ad62 | 17556 | return regno | (elno << 3); |
5f4273c7 | 17557 | |
5287ad62 JB |
17558 | case 32: |
17559 | if (regno > 15 || elno > 1) | |
477330fc | 17560 | goto bad_scalar; |
5287ad62 JB |
17561 | return regno | (elno << 4); |
17562 | ||
17563 | default: | |
17564 | bad_scalar: | |
dcbf9037 | 17565 | first_error (_("scalar out of range for multiply instruction")); |
5287ad62 JB |
17566 | } |
17567 | ||
17568 | return 0; | |
17569 | } | |
17570 | ||
17571 | /* Encode multiply / multiply-accumulate scalar instructions. */ | |
17572 | ||
17573 | static void | |
17574 | neon_mul_mac (struct neon_type_el et, int ubit) | |
17575 | { | |
dcbf9037 JB |
17576 | unsigned scalar; |
17577 | ||
17578 | /* Give a more helpful error message if we have an invalid type. */ | |
17579 | if (et.type == NT_invtype) | |
17580 | return; | |
5f4273c7 | 17581 | |
dcbf9037 | 17582 | scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); |
5287ad62 JB |
17583 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
17584 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17585 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
17586 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
17587 | inst.instruction |= LOW4 (scalar); | |
17588 | inst.instruction |= HI1 (scalar) << 5; | |
17589 | inst.instruction |= (et.type == NT_float) << 8; | |
17590 | inst.instruction |= neon_logbits (et.size) << 20; | |
17591 | inst.instruction |= (ubit != 0) << 24; | |
17592 | ||
88714cb8 | 17593 | neon_dp_fixup (&inst); |
5287ad62 JB |
17594 | } |
17595 | ||
17596 | static void | |
17597 | do_neon_mac_maybe_scalar (void) | |
17598 | { | |
037e8744 JB |
17599 | if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) |
17600 | return; | |
17601 | ||
64c350f2 | 17602 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
037e8744 JB |
17603 | return; |
17604 | ||
5287ad62 JB |
17605 | if (inst.operands[2].isscalar) |
17606 | { | |
a8465a06 | 17607 | constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); |
037e8744 | 17608 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 | 17609 | struct neon_type_el et = neon_check_type (3, rs, |
589a7d88 | 17610 | N_EQK, N_EQK, N_I16 | N_I32 | N_F_16_32 | N_KEY); |
88714cb8 | 17611 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 17612 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 | 17613 | } |
a8465a06 AV |
17614 | else if (!inst.operands[2].isvec) |
17615 | { | |
17616 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); | |
17617 | ||
17618 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); | |
17619 | neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); | |
17620 | ||
17621 | neon_dyadic_misc (NT_unsigned, N_SU_MVE, 0); | |
17622 | } | |
5287ad62 | 17623 | else |
428e3f1f | 17624 | { |
a8465a06 | 17625 | constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); |
428e3f1f PB |
17626 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
17627 | affected if we specify unsigned args. */ | |
17628 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
17629 | } | |
5287ad62 JB |
17630 | } |
17631 | ||
62f3b8c8 PB |
17632 | static void |
17633 | do_neon_fmac (void) | |
17634 | { | |
d58196e0 AV |
17635 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_fma) |
17636 | && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS) | |
62f3b8c8 PB |
17637 | return; |
17638 | ||
64c350f2 | 17639 | if (!check_simd_pred_availability (TRUE, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
62f3b8c8 PB |
17640 | return; |
17641 | ||
d58196e0 AV |
17642 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) |
17643 | { | |
17644 | enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL); | |
17645 | struct neon_type_el et = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK, | |
17646 | N_EQK); | |
17647 | ||
17648 | if (rs == NS_QQR) | |
17649 | { | |
17650 | if (inst.operands[2].reg == REG_SP) | |
17651 | as_tsktsk (MVE_BAD_SP); | |
17652 | else if (inst.operands[2].reg == REG_PC) | |
17653 | as_tsktsk (MVE_BAD_PC); | |
17654 | ||
17655 | inst.instruction = 0xee310e40; | |
17656 | inst.instruction |= (et.size == 16) << 28; | |
17657 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17658 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
17659 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
17660 | inst.instruction |= HI1 (inst.operands[1].reg) << 6; | |
17661 | inst.instruction |= inst.operands[2].reg; | |
17662 | inst.is_neon = 1; | |
17663 | return; | |
17664 | } | |
17665 | } | |
17666 | else | |
17667 | { | |
17668 | constraint (!inst.operands[2].isvec, BAD_FPU); | |
17669 | } | |
17670 | ||
62f3b8c8 PB |
17671 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); |
17672 | } | |
17673 | ||
5287ad62 JB |
17674 | static void |
17675 | do_neon_tst (void) | |
17676 | { | |
037e8744 | 17677 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
17678 | struct neon_type_el et = neon_check_type (3, rs, |
17679 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
037e8744 | 17680 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
17681 | } |
17682 | ||
17683 | /* VMUL with 3 registers allows the P8 type. The scalar version supports the | |
17684 | same types as the MAC equivalents. The polynomial type for this instruction | |
17685 | is encoded the same as the integer type. */ | |
17686 | ||
17687 | static void | |
17688 | do_neon_mul (void) | |
17689 | { | |
037e8744 JB |
17690 | if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) |
17691 | return; | |
17692 | ||
64c350f2 | 17693 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
037e8744 JB |
17694 | return; |
17695 | ||
5287ad62 | 17696 | if (inst.operands[2].isscalar) |
a8465a06 AV |
17697 | { |
17698 | constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); | |
17699 | do_neon_mac_maybe_scalar (); | |
17700 | } | |
5287ad62 | 17701 | else |
a8465a06 AV |
17702 | { |
17703 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
17704 | { | |
17705 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL); | |
17706 | struct neon_type_el et | |
17707 | = neon_check_type (3, rs, N_EQK, N_EQK, N_I_MVE | N_F_MVE | N_KEY); | |
17708 | if (et.type == NT_float) | |
17709 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext), | |
17710 | BAD_FPU); | |
17711 | ||
17712 | neon_dyadic_misc (NT_float, N_I_MVE | N_F_MVE, 0); | |
17713 | } | |
17714 | else | |
17715 | { | |
17716 | constraint (!inst.operands[2].isvec, BAD_FPU); | |
17717 | neon_dyadic_misc (NT_poly, | |
17718 | N_I8 | N_I16 | N_I32 | N_F16 | N_F32 | N_P8, 0); | |
17719 | } | |
17720 | } | |
5287ad62 JB |
17721 | } |
17722 | ||
17723 | static void | |
17724 | do_neon_qdmulh (void) | |
17725 | { | |
64c350f2 | 17726 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
42b16635 AV |
17727 | return; |
17728 | ||
5287ad62 JB |
17729 | if (inst.operands[2].isscalar) |
17730 | { | |
42b16635 | 17731 | constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); |
037e8744 | 17732 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 | 17733 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 17734 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); |
88714cb8 | 17735 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 17736 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
17737 | } |
17738 | else | |
17739 | { | |
42b16635 AV |
17740 | enum neon_shape rs; |
17741 | struct neon_type_el et; | |
17742 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
17743 | { | |
17744 | rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL); | |
17745 | et = neon_check_type (3, rs, | |
17746 | N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
17747 | } | |
17748 | else | |
17749 | { | |
17750 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
17751 | et = neon_check_type (3, rs, | |
17752 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
17753 | } | |
17754 | ||
88714cb8 | 17755 | NEON_ENCODE (INTEGER, inst); |
42b16635 AV |
17756 | if (rs == NS_QQR) |
17757 | mve_encode_qqr (et.size, 0, 0); | |
17758 | else | |
17759 | /* The U bit (rounding) comes from bit mask. */ | |
17760 | neon_three_same (neon_quad (rs), 0, et.size); | |
5287ad62 JB |
17761 | } |
17762 | } | |
17763 | ||
26c1e780 AV |
17764 | static void |
17765 | do_mve_vaddv (void) | |
17766 | { | |
17767 | enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL); | |
17768 | struct neon_type_el et | |
17769 | = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); | |
17770 | ||
17771 | if (et.type == NT_invtype) | |
17772 | first_error (BAD_EL_TYPE); | |
17773 | ||
17774 | if (inst.cond > COND_ALWAYS) | |
17775 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
17776 | else | |
17777 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
17778 | ||
17779 | constraint (inst.operands[1].reg > 14, MVE_BAD_QREG); | |
17780 | ||
17781 | mve_encode_rq (et.type == NT_unsigned, et.size); | |
17782 | } | |
17783 | ||
7df54120 AV |
17784 | static void |
17785 | do_mve_vhcadd (void) | |
17786 | { | |
17787 | enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL); | |
17788 | struct neon_type_el et | |
17789 | = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
17790 | ||
17791 | if (inst.cond > COND_ALWAYS) | |
17792 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
17793 | else | |
17794 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
17795 | ||
17796 | unsigned rot = inst.relocs[0].exp.X_add_number; | |
17797 | constraint (rot != 90 && rot != 270, _("immediate out of range")); | |
17798 | ||
17799 | if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg) | |
17800 | as_tsktsk (_("Warning: 32-bit element size and same first and third " | |
17801 | "operand makes instruction UNPREDICTABLE")); | |
17802 | ||
17803 | mve_encode_qqq (0, et.size); | |
17804 | inst.instruction |= (rot == 270) << 12; | |
17805 | inst.is_neon = 1; | |
17806 | } | |
17807 | ||
35d1cfc2 AV |
17808 | static void |
17809 | do_mve_vqdmull (void) | |
17810 | { | |
17811 | enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL); | |
17812 | struct neon_type_el et | |
17813 | = neon_check_type (3, rs, N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
17814 | ||
17815 | if (et.size == 32 | |
17816 | && (inst.operands[0].reg == inst.operands[1].reg | |
17817 | || (rs == NS_QQQ && inst.operands[0].reg == inst.operands[2].reg))) | |
17818 | as_tsktsk (BAD_MVE_SRCDEST); | |
17819 | ||
17820 | if (inst.cond > COND_ALWAYS) | |
17821 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
17822 | else | |
17823 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
17824 | ||
17825 | if (rs == NS_QQQ) | |
17826 | { | |
17827 | mve_encode_qqq (et.size == 32, 64); | |
17828 | inst.instruction |= 1; | |
17829 | } | |
17830 | else | |
17831 | { | |
17832 | mve_encode_qqr (64, et.size == 32, 0); | |
17833 | inst.instruction |= 0x3 << 5; | |
17834 | } | |
17835 | } | |
17836 | ||
c2dafc2a AV |
17837 | static void |
17838 | do_mve_vadc (void) | |
17839 | { | |
17840 | enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL); | |
17841 | struct neon_type_el et | |
17842 | = neon_check_type (3, rs, N_KEY | N_I32, N_EQK, N_EQK); | |
17843 | ||
17844 | if (et.type == NT_invtype) | |
17845 | first_error (BAD_EL_TYPE); | |
17846 | ||
17847 | if (inst.cond > COND_ALWAYS) | |
17848 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
17849 | else | |
17850 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
17851 | ||
17852 | mve_encode_qqq (0, 64); | |
17853 | } | |
17854 | ||
17855 | static void | |
17856 | do_mve_vbrsr (void) | |
17857 | { | |
17858 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); | |
17859 | struct neon_type_el et | |
17860 | = neon_check_type (3, rs, N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
17861 | ||
17862 | if (inst.cond > COND_ALWAYS) | |
17863 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
17864 | else | |
17865 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
17866 | ||
7df54120 | 17867 | mve_encode_qqr (et.size, 0, 0); |
c2dafc2a AV |
17868 | } |
17869 | ||
17870 | static void | |
17871 | do_mve_vsbc (void) | |
17872 | { | |
17873 | neon_check_type (3, NS_QQQ, N_EQK, N_EQK, N_I32 | N_KEY); | |
17874 | ||
17875 | if (inst.cond > COND_ALWAYS) | |
17876 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
17877 | else | |
17878 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
17879 | ||
17880 | mve_encode_qqq (1, 64); | |
17881 | } | |
17882 | ||
2d78f95b AV |
17883 | static void |
17884 | do_mve_vmulh (void) | |
17885 | { | |
17886 | enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL); | |
17887 | struct neon_type_el et | |
17888 | = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); | |
17889 | ||
17890 | if (inst.cond > COND_ALWAYS) | |
17891 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
17892 | else | |
17893 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
17894 | ||
17895 | mve_encode_qqq (et.type == NT_unsigned, et.size); | |
17896 | } | |
17897 | ||
42b16635 AV |
17898 | static void |
17899 | do_mve_vqdmlah (void) | |
17900 | { | |
17901 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); | |
17902 | struct neon_type_el et | |
17903 | = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); | |
17904 | ||
17905 | if (inst.cond > COND_ALWAYS) | |
17906 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
17907 | else | |
17908 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
17909 | ||
17910 | mve_encode_qqr (et.size, et.type == NT_unsigned, 0); | |
17911 | } | |
8b8b22a4 AV |
17912 | |
17913 | static void | |
17914 | do_mve_vqdmladh (void) | |
17915 | { | |
17916 | enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL); | |
17917 | struct neon_type_el et | |
17918 | = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
17919 | ||
17920 | if (inst.cond > COND_ALWAYS) | |
17921 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
17922 | else | |
17923 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
17924 | ||
8b8b22a4 AV |
17925 | mve_encode_qqq (0, et.size); |
17926 | } | |
17927 | ||
17928 | ||
886e1c73 AV |
17929 | static void |
17930 | do_mve_vmull (void) | |
17931 | { | |
17932 | ||
17933 | enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_DDS, | |
17934 | NS_QQS, NS_QQQ, NS_QQR, NS_NULL); | |
17935 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
17936 | && inst.cond == COND_ALWAYS | |
17937 | && ((unsigned)inst.instruction) == M_MNEM_vmullt) | |
17938 | { | |
17939 | if (rs == NS_QQQ) | |
17940 | { | |
17941 | ||
17942 | struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK, | |
17943 | N_SUF_32 | N_F64 | N_P8 | |
17944 | | N_P16 | N_I_MVE | N_KEY); | |
17945 | if (((et.type == NT_poly) && et.size == 8 | |
17946 | && ARM_CPU_IS_ANY (cpu_variant)) | |
17947 | || (et.type == NT_integer) || (et.type == NT_float)) | |
17948 | goto neon_vmul; | |
17949 | } | |
17950 | else | |
17951 | goto neon_vmul; | |
17952 | } | |
17953 | ||
17954 | constraint (rs != NS_QQQ, BAD_FPU); | |
17955 | struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK, | |
17956 | N_SU_32 | N_P8 | N_P16 | N_KEY); | |
17957 | ||
17958 | /* We are dealing with MVE's vmullt. */ | |
17959 | if (et.size == 32 | |
17960 | && (inst.operands[0].reg == inst.operands[1].reg | |
17961 | || inst.operands[0].reg == inst.operands[2].reg)) | |
17962 | as_tsktsk (BAD_MVE_SRCDEST); | |
17963 | ||
17964 | if (inst.cond > COND_ALWAYS) | |
17965 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
17966 | else | |
17967 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
17968 | ||
17969 | if (et.type == NT_poly) | |
17970 | mve_encode_qqq (neon_logbits (et.size), 64); | |
17971 | else | |
17972 | mve_encode_qqq (et.type == NT_unsigned, et.size); | |
17973 | ||
17974 | return; | |
17975 | ||
17976 | neon_vmul: | |
17977 | inst.instruction = N_MNEM_vmul; | |
17978 | inst.cond = 0xb; | |
17979 | if (thumb_mode) | |
17980 | inst.pred_insn_type = INSIDE_IT_INSN; | |
17981 | do_neon_mul (); | |
17982 | } | |
17983 | ||
a302e574 AV |
17984 | static void |
17985 | do_mve_vabav (void) | |
17986 | { | |
17987 | enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL); | |
17988 | ||
17989 | if (rs == NS_NULL) | |
17990 | return; | |
17991 | ||
17992 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
17993 | return; | |
17994 | ||
17995 | struct neon_type_el et = neon_check_type (2, NS_NULL, N_EQK, N_KEY | N_S8 | |
17996 | | N_S16 | N_S32 | N_U8 | N_U16 | |
17997 | | N_U32); | |
17998 | ||
17999 | if (inst.cond > COND_ALWAYS) | |
18000 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
18001 | else | |
18002 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
18003 | ||
18004 | mve_encode_rqq (et.type == NT_unsigned, et.size); | |
18005 | } | |
18006 | ||
18007 | static void | |
18008 | do_mve_vmladav (void) | |
18009 | { | |
18010 | enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL); | |
18011 | struct neon_type_el et = neon_check_type (3, rs, | |
18012 | N_EQK, N_EQK, N_SU_MVE | N_KEY); | |
18013 | ||
18014 | if (et.type == NT_unsigned | |
18015 | && (inst.instruction == M_MNEM_vmladavx | |
18016 | || inst.instruction == M_MNEM_vmladavax | |
18017 | || inst.instruction == M_MNEM_vmlsdav | |
18018 | || inst.instruction == M_MNEM_vmlsdava | |
18019 | || inst.instruction == M_MNEM_vmlsdavx | |
18020 | || inst.instruction == M_MNEM_vmlsdavax)) | |
18021 | first_error (BAD_SIMD_TYPE); | |
18022 | ||
18023 | constraint (inst.operands[2].reg > 14, | |
18024 | _("MVE vector register in the range [Q0..Q7] expected")); | |
18025 | ||
18026 | if (inst.cond > COND_ALWAYS) | |
18027 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
18028 | else | |
18029 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
18030 | ||
18031 | if (inst.instruction == M_MNEM_vmlsdav | |
18032 | || inst.instruction == M_MNEM_vmlsdava | |
18033 | || inst.instruction == M_MNEM_vmlsdavx | |
18034 | || inst.instruction == M_MNEM_vmlsdavax) | |
18035 | inst.instruction |= (et.size == 8) << 28; | |
18036 | else | |
18037 | inst.instruction |= (et.size == 8) << 8; | |
18038 | ||
18039 | mve_encode_rqq (et.type == NT_unsigned, 64); | |
18040 | inst.instruction |= (et.size == 32) << 16; | |
18041 | } | |
18042 | ||
93925576 AV |
18043 | static void |
18044 | do_mve_vmlaldav (void) | |
18045 | { | |
18046 | enum neon_shape rs = neon_select_shape (NS_RRQQ, NS_NULL); | |
18047 | struct neon_type_el et | |
18048 | = neon_check_type (4, rs, N_EQK, N_EQK, N_EQK, | |
18049 | N_S16 | N_S32 | N_U16 | N_U32 | N_KEY); | |
18050 | ||
18051 | if (et.type == NT_unsigned | |
18052 | && (inst.instruction == M_MNEM_vmlsldav | |
18053 | || inst.instruction == M_MNEM_vmlsldava | |
18054 | || inst.instruction == M_MNEM_vmlsldavx | |
18055 | || inst.instruction == M_MNEM_vmlsldavax)) | |
18056 | first_error (BAD_SIMD_TYPE); | |
18057 | ||
18058 | if (inst.cond > COND_ALWAYS) | |
18059 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
18060 | else | |
18061 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
18062 | ||
18063 | mve_encode_rrqq (et.type == NT_unsigned, et.size); | |
18064 | } | |
18065 | ||
18066 | static void | |
18067 | do_mve_vrmlaldavh (void) | |
18068 | { | |
18069 | struct neon_type_el et; | |
18070 | if (inst.instruction == M_MNEM_vrmlsldavh | |
18071 | || inst.instruction == M_MNEM_vrmlsldavha | |
18072 | || inst.instruction == M_MNEM_vrmlsldavhx | |
18073 | || inst.instruction == M_MNEM_vrmlsldavhax) | |
18074 | { | |
18075 | et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY); | |
18076 | if (inst.operands[1].reg == REG_SP) | |
18077 | as_tsktsk (MVE_BAD_SP); | |
18078 | } | |
18079 | else | |
18080 | { | |
18081 | if (inst.instruction == M_MNEM_vrmlaldavhx | |
18082 | || inst.instruction == M_MNEM_vrmlaldavhax) | |
18083 | et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY); | |
18084 | else | |
18085 | et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, | |
18086 | N_U32 | N_S32 | N_KEY); | |
18087 | /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias | |
18088 | with vmax/min instructions, making the use of SP in assembly really | |
18089 | nonsensical, so instead of issuing a warning like we do for other uses | |
18090 | of SP for the odd register operand we error out. */ | |
18091 | constraint (inst.operands[1].reg == REG_SP, BAD_SP); | |
18092 | } | |
18093 | ||
18094 | /* Make sure we still check the second operand is an odd one and that PC is | |
18095 | disallowed. This because we are parsing for any GPR operand, to be able | |
18096 | to distinguish between giving a warning or an error for SP as described | |
18097 | above. */ | |
18098 | constraint ((inst.operands[1].reg % 2) != 1, BAD_EVEN); | |
18099 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); | |
18100 | ||
18101 | if (inst.cond > COND_ALWAYS) | |
18102 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
18103 | else | |
18104 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
18105 | ||
18106 | mve_encode_rrqq (et.type == NT_unsigned, 0); | |
18107 | } | |
18108 | ||
18109 | ||
8cd78170 AV |
18110 | static void |
18111 | do_mve_vmaxnmv (void) | |
18112 | { | |
18113 | enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL); | |
18114 | struct neon_type_el et | |
18115 | = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY); | |
18116 | ||
18117 | if (inst.cond > COND_ALWAYS) | |
18118 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
18119 | else | |
18120 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
18121 | ||
18122 | if (inst.operands[0].reg == REG_SP) | |
18123 | as_tsktsk (MVE_BAD_SP); | |
18124 | else if (inst.operands[0].reg == REG_PC) | |
18125 | as_tsktsk (MVE_BAD_PC); | |
18126 | ||
18127 | mve_encode_rq (et.size == 16, 64); | |
18128 | } | |
18129 | ||
13ccd4c0 AV |
18130 | static void |
18131 | do_mve_vmaxv (void) | |
18132 | { | |
18133 | enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL); | |
18134 | struct neon_type_el et; | |
18135 | ||
18136 | if (inst.instruction == M_MNEM_vmaxv || inst.instruction == M_MNEM_vminv) | |
18137 | et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY); | |
18138 | else | |
18139 | et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
18140 | ||
18141 | if (inst.cond > COND_ALWAYS) | |
18142 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
18143 | else | |
18144 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
18145 | ||
18146 | if (inst.operands[0].reg == REG_SP) | |
18147 | as_tsktsk (MVE_BAD_SP); | |
18148 | else if (inst.operands[0].reg == REG_PC) | |
18149 | as_tsktsk (MVE_BAD_PC); | |
18150 | ||
18151 | mve_encode_rq (et.type == NT_unsigned, et.size); | |
18152 | } | |
18153 | ||
18154 | ||
643afb90 MW |
18155 | static void |
18156 | do_neon_qrdmlah (void) | |
18157 | { | |
64c350f2 | 18158 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
42b16635 AV |
18159 | return; |
18160 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
643afb90 | 18161 | { |
42b16635 AV |
18162 | /* Check we're on the correct architecture. */ |
18163 | if (!mark_feature_used (&fpu_neon_ext_armv8)) | |
18164 | inst.error | |
18165 | = _("instruction form not available on this architecture."); | |
18166 | else if (!mark_feature_used (&fpu_neon_ext_v8_1)) | |
18167 | { | |
18168 | as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD.")); | |
18169 | record_feature_use (&fpu_neon_ext_v8_1); | |
18170 | } | |
18171 | if (inst.operands[2].isscalar) | |
18172 | { | |
18173 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); | |
18174 | struct neon_type_el et = neon_check_type (3, rs, | |
18175 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
18176 | NEON_ENCODE (SCALAR, inst); | |
18177 | neon_mul_mac (et, neon_quad (rs)); | |
18178 | } | |
18179 | else | |
18180 | { | |
18181 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
18182 | struct neon_type_el et = neon_check_type (3, rs, | |
18183 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
18184 | NEON_ENCODE (INTEGER, inst); | |
18185 | /* The U bit (rounding) comes from bit mask. */ | |
18186 | neon_three_same (neon_quad (rs), 0, et.size); | |
18187 | } | |
643afb90 MW |
18188 | } |
18189 | else | |
18190 | { | |
42b16635 AV |
18191 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); |
18192 | struct neon_type_el et | |
18193 | = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); | |
18194 | ||
643afb90 | 18195 | NEON_ENCODE (INTEGER, inst); |
42b16635 | 18196 | mve_encode_qqr (et.size, et.type == NT_unsigned, 0); |
643afb90 MW |
18197 | } |
18198 | } | |
18199 | ||
5287ad62 JB |
18200 | static void |
18201 | do_neon_fcmp_absolute (void) | |
18202 | { | |
037e8744 | 18203 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
cc933301 JW |
18204 | struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK, |
18205 | N_F_16_32 | N_KEY); | |
5287ad62 | 18206 | /* Size field comes from bit mask. */ |
cc933301 | 18207 | neon_three_same (neon_quad (rs), 1, et.size == 16 ? (int) et.size : -1); |
5287ad62 JB |
18208 | } |
18209 | ||
18210 | static void | |
18211 | do_neon_fcmp_absolute_inv (void) | |
18212 | { | |
18213 | neon_exchange_operands (); | |
18214 | do_neon_fcmp_absolute (); | |
18215 | } | |
18216 | ||
18217 | static void | |
18218 | do_neon_step (void) | |
18219 | { | |
037e8744 | 18220 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
cc933301 JW |
18221 | struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK, |
18222 | N_F_16_32 | N_KEY); | |
18223 | neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1); | |
5287ad62 JB |
18224 | } |
18225 | ||
18226 | static void | |
18227 | do_neon_abs_neg (void) | |
18228 | { | |
037e8744 JB |
18229 | enum neon_shape rs; |
18230 | struct neon_type_el et; | |
5f4273c7 | 18231 | |
037e8744 JB |
18232 | if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) |
18233 | return; | |
18234 | ||
037e8744 | 18235 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
cc933301 | 18236 | et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY); |
5f4273c7 | 18237 | |
64c350f2 AV |
18238 | if (!check_simd_pred_availability (et.type == NT_float, |
18239 | NEON_CHECK_ARCH | NEON_CHECK_CC)) | |
485dee97 AV |
18240 | return; |
18241 | ||
5287ad62 JB |
18242 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
18243 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
18244 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
18245 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 18246 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
18247 | inst.instruction |= (et.type == NT_float) << 10; |
18248 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 18249 | |
88714cb8 | 18250 | neon_dp_fixup (&inst); |
5287ad62 JB |
18251 | } |
18252 | ||
18253 | static void | |
18254 | do_neon_sli (void) | |
18255 | { | |
64c350f2 | 18256 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
4401c241 AV |
18257 | return; |
18258 | ||
18259 | enum neon_shape rs; | |
18260 | struct neon_type_el et; | |
18261 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
18262 | { | |
18263 | rs = neon_select_shape (NS_QQI, NS_NULL); | |
18264 | et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
18265 | } | |
18266 | else | |
18267 | { | |
18268 | rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); | |
18269 | et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
18270 | } | |
18271 | ||
18272 | ||
5287ad62 JB |
18273 | int imm = inst.operands[2].imm; |
18274 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
477330fc | 18275 | _("immediate out of range for insert")); |
037e8744 | 18276 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
18277 | } |
18278 | ||
18279 | static void | |
18280 | do_neon_sri (void) | |
18281 | { | |
64c350f2 | 18282 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
4401c241 AV |
18283 | return; |
18284 | ||
18285 | enum neon_shape rs; | |
18286 | struct neon_type_el et; | |
18287 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
18288 | { | |
18289 | rs = neon_select_shape (NS_QQI, NS_NULL); | |
18290 | et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
18291 | } | |
18292 | else | |
18293 | { | |
18294 | rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); | |
18295 | et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
18296 | } | |
18297 | ||
5287ad62 JB |
18298 | int imm = inst.operands[2].imm; |
18299 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 18300 | _("immediate out of range for insert")); |
037e8744 | 18301 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); |
5287ad62 JB |
18302 | } |
18303 | ||
18304 | static void | |
18305 | do_neon_qshlu_imm (void) | |
18306 | { | |
64c350f2 | 18307 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
5150f0d8 AV |
18308 | return; |
18309 | ||
18310 | enum neon_shape rs; | |
18311 | struct neon_type_el et; | |
18312 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
18313 | { | |
18314 | rs = neon_select_shape (NS_QQI, NS_NULL); | |
18315 | et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
18316 | } | |
18317 | else | |
18318 | { | |
18319 | rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); | |
18320 | et = neon_check_type (2, rs, N_EQK | N_UNS, | |
18321 | N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); | |
18322 | } | |
18323 | ||
5287ad62 JB |
18324 | int imm = inst.operands[2].imm; |
18325 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
477330fc | 18326 | _("immediate out of range for shift")); |
5287ad62 JB |
18327 | /* Only encodes the 'U present' variant of the instruction. |
18328 | In this case, signed types have OP (bit 8) set to 0. | |
18329 | Unsigned types have OP set to 1. */ | |
18330 | inst.instruction |= (et.type == NT_unsigned) << 8; | |
18331 | /* The rest of the bits are the same as other immediate shifts. */ | |
037e8744 | 18332 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
18333 | } |
18334 | ||
18335 | static void | |
18336 | do_neon_qmovn (void) | |
18337 | { | |
18338 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
18339 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
18340 | /* Saturating move where operands can be signed or unsigned, and the | |
18341 | destination has the same signedness. */ | |
88714cb8 | 18342 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
18343 | if (et.type == NT_unsigned) |
18344 | inst.instruction |= 0xc0; | |
18345 | else | |
18346 | inst.instruction |= 0x80; | |
18347 | neon_two_same (0, 1, et.size / 2); | |
18348 | } | |
18349 | ||
18350 | static void | |
18351 | do_neon_qmovun (void) | |
18352 | { | |
18353 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
18354 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
18355 | /* Saturating move with unsigned results. Operands must be signed. */ | |
88714cb8 | 18356 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
18357 | neon_two_same (0, 1, et.size / 2); |
18358 | } | |
18359 | ||
18360 | static void | |
18361 | do_neon_rshift_sat_narrow (void) | |
18362 | { | |
18363 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
18364 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
18365 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
18366 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
18367 | int imm = inst.operands[2].imm; | |
18368 | /* This gets the bounds check, size encoding and immediate bits calculation | |
18369 | right. */ | |
18370 | et.size /= 2; | |
5f4273c7 | 18371 | |
5287ad62 JB |
18372 | /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for |
18373 | VQMOVN.I<size> <Dd>, <Qm>. */ | |
18374 | if (imm == 0) | |
18375 | { | |
18376 | inst.operands[2].present = 0; | |
18377 | inst.instruction = N_MNEM_vqmovn; | |
18378 | do_neon_qmovn (); | |
18379 | return; | |
18380 | } | |
5f4273c7 | 18381 | |
5287ad62 | 18382 | constraint (imm < 1 || (unsigned)imm > et.size, |
477330fc | 18383 | _("immediate out of range")); |
5287ad62 JB |
18384 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); |
18385 | } | |
18386 | ||
18387 | static void | |
18388 | do_neon_rshift_sat_narrow_u (void) | |
18389 | { | |
18390 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
18391 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
18392 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
18393 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
18394 | int imm = inst.operands[2].imm; | |
18395 | /* This gets the bounds check, size encoding and immediate bits calculation | |
18396 | right. */ | |
18397 | et.size /= 2; | |
18398 | ||
18399 | /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for | |
18400 | VQMOVUN.I<size> <Dd>, <Qm>. */ | |
18401 | if (imm == 0) | |
18402 | { | |
18403 | inst.operands[2].present = 0; | |
18404 | inst.instruction = N_MNEM_vqmovun; | |
18405 | do_neon_qmovun (); | |
18406 | return; | |
18407 | } | |
18408 | ||
18409 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 18410 | _("immediate out of range")); |
5287ad62 JB |
18411 | /* FIXME: The manual is kind of unclear about what value U should have in |
18412 | VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it | |
18413 | must be 1. */ | |
18414 | neon_imm_shift (TRUE, 1, 0, et, et.size - imm); | |
18415 | } | |
18416 | ||
18417 | static void | |
18418 | do_neon_movn (void) | |
18419 | { | |
18420 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
18421 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
88714cb8 | 18422 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
18423 | neon_two_same (0, 1, et.size / 2); |
18424 | } | |
18425 | ||
18426 | static void | |
18427 | do_neon_rshift_narrow (void) | |
18428 | { | |
18429 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
18430 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
18431 | int imm = inst.operands[2].imm; | |
18432 | /* This gets the bounds check, size encoding and immediate bits calculation | |
18433 | right. */ | |
18434 | et.size /= 2; | |
5f4273c7 | 18435 | |
5287ad62 JB |
18436 | /* If immediate is zero then we are a pseudo-instruction for |
18437 | VMOVN.I<size> <Dd>, <Qm> */ | |
18438 | if (imm == 0) | |
18439 | { | |
18440 | inst.operands[2].present = 0; | |
18441 | inst.instruction = N_MNEM_vmovn; | |
18442 | do_neon_movn (); | |
18443 | return; | |
18444 | } | |
5f4273c7 | 18445 | |
5287ad62 | 18446 | constraint (imm < 1 || (unsigned)imm > et.size, |
477330fc | 18447 | _("immediate out of range for narrowing operation")); |
5287ad62 JB |
18448 | neon_imm_shift (FALSE, 0, 0, et, et.size - imm); |
18449 | } | |
18450 | ||
18451 | static void | |
18452 | do_neon_shll (void) | |
18453 | { | |
18454 | /* FIXME: Type checking when lengthening. */ | |
18455 | struct neon_type_el et = neon_check_type (2, NS_QDI, | |
18456 | N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); | |
18457 | unsigned imm = inst.operands[2].imm; | |
18458 | ||
18459 | if (imm == et.size) | |
18460 | { | |
18461 | /* Maximum shift variant. */ | |
88714cb8 | 18462 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
18463 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
18464 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
18465 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
18466 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
18467 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 18468 | |
88714cb8 | 18469 | neon_dp_fixup (&inst); |
5287ad62 JB |
18470 | } |
18471 | else | |
18472 | { | |
18473 | /* A more-specific type check for non-max versions. */ | |
18474 | et = neon_check_type (2, NS_QDI, | |
477330fc | 18475 | N_EQK | N_DBL, N_SU_32 | N_KEY); |
88714cb8 | 18476 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
18477 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); |
18478 | } | |
18479 | } | |
18480 | ||
037e8744 | 18481 | /* Check the various types for the VCVT instruction, and return which version |
5287ad62 JB |
18482 | the current instruction is. */ |
18483 | ||
6b9a8b67 MGD |
18484 | #define CVT_FLAVOUR_VAR \ |
18485 | CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \ | |
18486 | CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \ | |
18487 | CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \ | |
18488 | CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \ | |
18489 | /* Half-precision conversions. */ \ | |
cc933301 JW |
18490 | CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \ |
18491 | CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \ | |
18492 | CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \ | |
18493 | CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \ | |
6b9a8b67 MGD |
18494 | CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \ |
18495 | CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \ | |
9db2f6b4 RL |
18496 | /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \ |
18497 | Compared with single/double precision variants, only the co-processor \ | |
18498 | field is different, so the encoding flow is reused here. */ \ | |
18499 | CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \ | |
18500 | CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \ | |
18501 | CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\ | |
18502 | CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\ | |
6b9a8b67 MGD |
18503 | /* VFP instructions. */ \ |
18504 | CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \ | |
18505 | CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \ | |
18506 | CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \ | |
18507 | CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \ | |
18508 | CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \ | |
18509 | CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \ | |
18510 | /* VFP instructions with bitshift. */ \ | |
18511 | CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \ | |
18512 | CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \ | |
18513 | CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \ | |
18514 | CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \ | |
18515 | CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \ | |
18516 | CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \ | |
18517 | CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \ | |
18518 | CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL) | |
18519 | ||
18520 | #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \ | |
18521 | neon_cvt_flavour_##C, | |
18522 | ||
18523 | /* The different types of conversions we can do. */ | |
18524 | enum neon_cvt_flavour | |
18525 | { | |
18526 | CVT_FLAVOUR_VAR | |
18527 | neon_cvt_flavour_invalid, | |
18528 | neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64 | |
18529 | }; | |
18530 | ||
18531 | #undef CVT_VAR | |
18532 | ||
18533 | static enum neon_cvt_flavour | |
18534 | get_neon_cvt_flavour (enum neon_shape rs) | |
5287ad62 | 18535 | { |
6b9a8b67 MGD |
18536 | #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \ |
18537 | et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \ | |
18538 | if (et.type != NT_invtype) \ | |
18539 | { \ | |
18540 | inst.error = NULL; \ | |
18541 | return (neon_cvt_flavour_##C); \ | |
5287ad62 | 18542 | } |
6b9a8b67 | 18543 | |
5287ad62 | 18544 | struct neon_type_el et; |
037e8744 | 18545 | unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF |
477330fc | 18546 | || rs == NS_FF) ? N_VFP : 0; |
037e8744 JB |
18547 | /* The instruction versions which take an immediate take one register |
18548 | argument, which is extended to the width of the full register. Thus the | |
18549 | "source" and "destination" registers must have the same width. Hack that | |
18550 | here by making the size equal to the key (wider, in this case) operand. */ | |
18551 | unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; | |
5f4273c7 | 18552 | |
6b9a8b67 MGD |
18553 | CVT_FLAVOUR_VAR; |
18554 | ||
18555 | return neon_cvt_flavour_invalid; | |
5287ad62 JB |
18556 | #undef CVT_VAR |
18557 | } | |
18558 | ||
7e8e6784 MGD |
18559 | enum neon_cvt_mode |
18560 | { | |
18561 | neon_cvt_mode_a, | |
18562 | neon_cvt_mode_n, | |
18563 | neon_cvt_mode_p, | |
18564 | neon_cvt_mode_m, | |
18565 | neon_cvt_mode_z, | |
30bdf752 MGD |
18566 | neon_cvt_mode_x, |
18567 | neon_cvt_mode_r | |
7e8e6784 MGD |
18568 | }; |
18569 | ||
037e8744 JB |
18570 | /* Neon-syntax VFP conversions. */ |
18571 | ||
5287ad62 | 18572 | static void |
6b9a8b67 | 18573 | do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour) |
5287ad62 | 18574 | { |
037e8744 | 18575 | const char *opname = 0; |
5f4273c7 | 18576 | |
d54af2d0 RL |
18577 | if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI |
18578 | || rs == NS_FHI || rs == NS_HFI) | |
5287ad62 | 18579 | { |
037e8744 JB |
18580 | /* Conversions with immediate bitshift. */ |
18581 | const char *enc[] = | |
477330fc | 18582 | { |
6b9a8b67 MGD |
18583 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN, |
18584 | CVT_FLAVOUR_VAR | |
18585 | NULL | |
18586 | #undef CVT_VAR | |
477330fc | 18587 | }; |
037e8744 | 18588 | |
6b9a8b67 | 18589 | if (flavour < (int) ARRAY_SIZE (enc)) |
477330fc RM |
18590 | { |
18591 | opname = enc[flavour]; | |
18592 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
18593 | _("operands 0 and 1 must be the same register")); | |
18594 | inst.operands[1] = inst.operands[2]; | |
18595 | memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); | |
18596 | } | |
5287ad62 JB |
18597 | } |
18598 | else | |
18599 | { | |
037e8744 JB |
18600 | /* Conversions without bitshift. */ |
18601 | const char *enc[] = | |
477330fc | 18602 | { |
6b9a8b67 MGD |
18603 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN, |
18604 | CVT_FLAVOUR_VAR | |
18605 | NULL | |
18606 | #undef CVT_VAR | |
477330fc | 18607 | }; |
037e8744 | 18608 | |
6b9a8b67 | 18609 | if (flavour < (int) ARRAY_SIZE (enc)) |
477330fc | 18610 | opname = enc[flavour]; |
037e8744 JB |
18611 | } |
18612 | ||
18613 | if (opname) | |
18614 | do_vfp_nsyn_opcode (opname); | |
9db2f6b4 RL |
18615 | |
18616 | /* ARMv8.2 fp16 VCVT instruction. */ | |
18617 | if (flavour == neon_cvt_flavour_s32_f16 | |
18618 | || flavour == neon_cvt_flavour_u32_f16 | |
18619 | || flavour == neon_cvt_flavour_f16_u32 | |
18620 | || flavour == neon_cvt_flavour_f16_s32) | |
18621 | do_scalar_fp16_v82_encode (); | |
037e8744 JB |
18622 | } |
18623 | ||
18624 | static void | |
18625 | do_vfp_nsyn_cvtz (void) | |
18626 | { | |
d54af2d0 | 18627 | enum neon_shape rs = neon_select_shape (NS_FH, NS_FF, NS_FD, NS_NULL); |
6b9a8b67 | 18628 | enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs); |
037e8744 JB |
18629 | const char *enc[] = |
18630 | { | |
6b9a8b67 MGD |
18631 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN, |
18632 | CVT_FLAVOUR_VAR | |
18633 | NULL | |
18634 | #undef CVT_VAR | |
037e8744 JB |
18635 | }; |
18636 | ||
6b9a8b67 | 18637 | if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) |
037e8744 JB |
18638 | do_vfp_nsyn_opcode (enc[flavour]); |
18639 | } | |
f31fef98 | 18640 | |
037e8744 | 18641 | static void |
bacebabc | 18642 | do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour, |
7e8e6784 MGD |
18643 | enum neon_cvt_mode mode) |
18644 | { | |
18645 | int sz, op; | |
18646 | int rm; | |
18647 | ||
a715796b TG |
18648 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
18649 | D register operands. */ | |
18650 | if (flavour == neon_cvt_flavour_s32_f64 | |
18651 | || flavour == neon_cvt_flavour_u32_f64) | |
18652 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
18653 | _(BAD_FPU)); | |
18654 | ||
9db2f6b4 RL |
18655 | if (flavour == neon_cvt_flavour_s32_f16 |
18656 | || flavour == neon_cvt_flavour_u32_f16) | |
18657 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16), | |
18658 | _(BAD_FP16)); | |
18659 | ||
5ee91343 | 18660 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
7e8e6784 MGD |
18661 | |
18662 | switch (flavour) | |
18663 | { | |
18664 | case neon_cvt_flavour_s32_f64: | |
18665 | sz = 1; | |
827f64ff | 18666 | op = 1; |
7e8e6784 MGD |
18667 | break; |
18668 | case neon_cvt_flavour_s32_f32: | |
18669 | sz = 0; | |
18670 | op = 1; | |
18671 | break; | |
9db2f6b4 RL |
18672 | case neon_cvt_flavour_s32_f16: |
18673 | sz = 0; | |
18674 | op = 1; | |
18675 | break; | |
7e8e6784 MGD |
18676 | case neon_cvt_flavour_u32_f64: |
18677 | sz = 1; | |
18678 | op = 0; | |
18679 | break; | |
18680 | case neon_cvt_flavour_u32_f32: | |
18681 | sz = 0; | |
18682 | op = 0; | |
18683 | break; | |
9db2f6b4 RL |
18684 | case neon_cvt_flavour_u32_f16: |
18685 | sz = 0; | |
18686 | op = 0; | |
18687 | break; | |
7e8e6784 MGD |
18688 | default: |
18689 | first_error (_("invalid instruction shape")); | |
18690 | return; | |
18691 | } | |
18692 | ||
18693 | switch (mode) | |
18694 | { | |
18695 | case neon_cvt_mode_a: rm = 0; break; | |
18696 | case neon_cvt_mode_n: rm = 1; break; | |
18697 | case neon_cvt_mode_p: rm = 2; break; | |
18698 | case neon_cvt_mode_m: rm = 3; break; | |
18699 | default: first_error (_("invalid rounding mode")); return; | |
18700 | } | |
18701 | ||
18702 | NEON_ENCODE (FPV8, inst); | |
18703 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
18704 | encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm); | |
18705 | inst.instruction |= sz << 8; | |
9db2f6b4 RL |
18706 | |
18707 | /* ARMv8.2 fp16 VCVT instruction. */ | |
18708 | if (flavour == neon_cvt_flavour_s32_f16 | |
18709 | ||flavour == neon_cvt_flavour_u32_f16) | |
18710 | do_scalar_fp16_v82_encode (); | |
7e8e6784 MGD |
18711 | inst.instruction |= op << 7; |
18712 | inst.instruction |= rm << 16; | |
18713 | inst.instruction |= 0xf0000000; | |
18714 | inst.is_neon = TRUE; | |
18715 | } | |
18716 | ||
18717 | static void | |
18718 | do_neon_cvt_1 (enum neon_cvt_mode mode) | |
037e8744 JB |
18719 | { |
18720 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, | |
d54af2d0 RL |
18721 | NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, |
18722 | NS_FH, NS_HF, NS_FHI, NS_HFI, | |
18723 | NS_NULL); | |
6b9a8b67 | 18724 | enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs); |
037e8744 | 18725 | |
cc933301 JW |
18726 | if (flavour == neon_cvt_flavour_invalid) |
18727 | return; | |
18728 | ||
e3e535bc | 18729 | /* PR11109: Handle round-to-zero for VCVT conversions. */ |
7e8e6784 | 18730 | if (mode == neon_cvt_mode_z |
e3e535bc | 18731 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2) |
cc933301 JW |
18732 | && (flavour == neon_cvt_flavour_s16_f16 |
18733 | || flavour == neon_cvt_flavour_u16_f16 | |
18734 | || flavour == neon_cvt_flavour_s32_f32 | |
bacebabc RM |
18735 | || flavour == neon_cvt_flavour_u32_f32 |
18736 | || flavour == neon_cvt_flavour_s32_f64 | |
6b9a8b67 | 18737 | || flavour == neon_cvt_flavour_u32_f64) |
e3e535bc NC |
18738 | && (rs == NS_FD || rs == NS_FF)) |
18739 | { | |
18740 | do_vfp_nsyn_cvtz (); | |
18741 | return; | |
18742 | } | |
18743 | ||
9db2f6b4 RL |
18744 | /* ARMv8.2 fp16 VCVT conversions. */ |
18745 | if (mode == neon_cvt_mode_z | |
18746 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16) | |
18747 | && (flavour == neon_cvt_flavour_s32_f16 | |
18748 | || flavour == neon_cvt_flavour_u32_f16) | |
18749 | && (rs == NS_FH)) | |
18750 | { | |
18751 | do_vfp_nsyn_cvtz (); | |
18752 | do_scalar_fp16_v82_encode (); | |
18753 | return; | |
18754 | } | |
18755 | ||
037e8744 | 18756 | /* VFP rather than Neon conversions. */ |
6b9a8b67 | 18757 | if (flavour >= neon_cvt_flavour_first_fp) |
037e8744 | 18758 | { |
7e8e6784 MGD |
18759 | if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z) |
18760 | do_vfp_nsyn_cvt (rs, flavour); | |
18761 | else | |
18762 | do_vfp_nsyn_cvt_fpv8 (flavour, mode); | |
18763 | ||
037e8744 JB |
18764 | return; |
18765 | } | |
18766 | ||
18767 | switch (rs) | |
18768 | { | |
037e8744 | 18769 | case NS_QQI: |
dd9634d9 AV |
18770 | if (mode == neon_cvt_mode_z |
18771 | && (flavour == neon_cvt_flavour_f16_s16 | |
18772 | || flavour == neon_cvt_flavour_f16_u16 | |
18773 | || flavour == neon_cvt_flavour_s16_f16 | |
18774 | || flavour == neon_cvt_flavour_u16_f16 | |
18775 | || flavour == neon_cvt_flavour_f32_u32 | |
18776 | || flavour == neon_cvt_flavour_f32_s32 | |
18777 | || flavour == neon_cvt_flavour_s32_f32 | |
18778 | || flavour == neon_cvt_flavour_u32_f32)) | |
18779 | { | |
64c350f2 AV |
18780 | if (!check_simd_pred_availability (TRUE, |
18781 | NEON_CHECK_CC | NEON_CHECK_ARCH)) | |
dd9634d9 AV |
18782 | return; |
18783 | } | |
18784 | else if (mode == neon_cvt_mode_n) | |
18785 | { | |
18786 | /* We are dealing with vcvt with the 'ne' condition. */ | |
18787 | inst.cond = 0x1; | |
18788 | inst.instruction = N_MNEM_vcvt; | |
18789 | do_neon_cvt_1 (neon_cvt_mode_z); | |
18790 | return; | |
18791 | } | |
18792 | /* fall through. */ | |
18793 | case NS_DDI: | |
037e8744 | 18794 | { |
477330fc | 18795 | unsigned immbits; |
cc933301 JW |
18796 | unsigned enctab[] = {0x0000100, 0x1000100, 0x0, 0x1000000, |
18797 | 0x0000100, 0x1000100, 0x0, 0x1000000}; | |
35997600 | 18798 | |
dd9634d9 AV |
18799 | if ((rs != NS_QQI || !ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) |
18800 | && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
18801 | return; | |
18802 | ||
18803 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) | |
18804 | { | |
18805 | constraint (inst.operands[2].present && inst.operands[2].imm == 0, | |
18806 | _("immediate value out of range")); | |
18807 | switch (flavour) | |
18808 | { | |
18809 | case neon_cvt_flavour_f16_s16: | |
18810 | case neon_cvt_flavour_f16_u16: | |
18811 | case neon_cvt_flavour_s16_f16: | |
18812 | case neon_cvt_flavour_u16_f16: | |
18813 | constraint (inst.operands[2].imm > 16, | |
18814 | _("immediate value out of range")); | |
18815 | break; | |
18816 | case neon_cvt_flavour_f32_u32: | |
18817 | case neon_cvt_flavour_f32_s32: | |
18818 | case neon_cvt_flavour_s32_f32: | |
18819 | case neon_cvt_flavour_u32_f32: | |
18820 | constraint (inst.operands[2].imm > 32, | |
18821 | _("immediate value out of range")); | |
18822 | break; | |
18823 | default: | |
18824 | inst.error = BAD_FPU; | |
18825 | return; | |
18826 | } | |
18827 | } | |
037e8744 | 18828 | |
477330fc RM |
18829 | /* Fixed-point conversion with #0 immediate is encoded as an |
18830 | integer conversion. */ | |
18831 | if (inst.operands[2].present && inst.operands[2].imm == 0) | |
18832 | goto int_encode; | |
477330fc RM |
18833 | NEON_ENCODE (IMMED, inst); |
18834 | if (flavour != neon_cvt_flavour_invalid) | |
18835 | inst.instruction |= enctab[flavour]; | |
18836 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
18837 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
18838 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
18839 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
18840 | inst.instruction |= neon_quad (rs) << 6; | |
18841 | inst.instruction |= 1 << 21; | |
cc933301 JW |
18842 | if (flavour < neon_cvt_flavour_s16_f16) |
18843 | { | |
18844 | inst.instruction |= 1 << 21; | |
18845 | immbits = 32 - inst.operands[2].imm; | |
18846 | inst.instruction |= immbits << 16; | |
18847 | } | |
18848 | else | |
18849 | { | |
18850 | inst.instruction |= 3 << 20; | |
18851 | immbits = 16 - inst.operands[2].imm; | |
18852 | inst.instruction |= immbits << 16; | |
18853 | inst.instruction &= ~(1 << 9); | |
18854 | } | |
477330fc RM |
18855 | |
18856 | neon_dp_fixup (&inst); | |
037e8744 JB |
18857 | } |
18858 | break; | |
18859 | ||
037e8744 | 18860 | case NS_QQ: |
dd9634d9 AV |
18861 | if ((mode == neon_cvt_mode_a || mode == neon_cvt_mode_n |
18862 | || mode == neon_cvt_mode_m || mode == neon_cvt_mode_p) | |
18863 | && (flavour == neon_cvt_flavour_s16_f16 | |
18864 | || flavour == neon_cvt_flavour_u16_f16 | |
18865 | || flavour == neon_cvt_flavour_s32_f32 | |
18866 | || flavour == neon_cvt_flavour_u32_f32)) | |
18867 | { | |
64c350f2 AV |
18868 | if (!check_simd_pred_availability (TRUE, |
18869 | NEON_CHECK_CC | NEON_CHECK_ARCH8)) | |
dd9634d9 AV |
18870 | return; |
18871 | } | |
18872 | else if (mode == neon_cvt_mode_z | |
18873 | && (flavour == neon_cvt_flavour_f16_s16 | |
18874 | || flavour == neon_cvt_flavour_f16_u16 | |
18875 | || flavour == neon_cvt_flavour_s16_f16 | |
18876 | || flavour == neon_cvt_flavour_u16_f16 | |
18877 | || flavour == neon_cvt_flavour_f32_u32 | |
18878 | || flavour == neon_cvt_flavour_f32_s32 | |
18879 | || flavour == neon_cvt_flavour_s32_f32 | |
18880 | || flavour == neon_cvt_flavour_u32_f32)) | |
18881 | { | |
64c350f2 AV |
18882 | if (!check_simd_pred_availability (TRUE, |
18883 | NEON_CHECK_CC | NEON_CHECK_ARCH)) | |
dd9634d9 AV |
18884 | return; |
18885 | } | |
18886 | /* fall through. */ | |
18887 | case NS_DD: | |
7e8e6784 MGD |
18888 | if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z) |
18889 | { | |
7e8e6784 | 18890 | |
dd9634d9 | 18891 | NEON_ENCODE (FLOAT, inst); |
64c350f2 AV |
18892 | if (!check_simd_pred_availability (TRUE, |
18893 | NEON_CHECK_CC | NEON_CHECK_ARCH8)) | |
7e8e6784 MGD |
18894 | return; |
18895 | ||
18896 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
18897 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
18898 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
18899 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
18900 | inst.instruction |= neon_quad (rs) << 6; | |
cc933301 JW |
18901 | inst.instruction |= (flavour == neon_cvt_flavour_u16_f16 |
18902 | || flavour == neon_cvt_flavour_u32_f32) << 7; | |
7e8e6784 | 18903 | inst.instruction |= mode << 8; |
cc933301 JW |
18904 | if (flavour == neon_cvt_flavour_u16_f16 |
18905 | || flavour == neon_cvt_flavour_s16_f16) | |
18906 | /* Mask off the original size bits and reencode them. */ | |
18907 | inst.instruction = ((inst.instruction & 0xfff3ffff) | (1 << 18)); | |
18908 | ||
7e8e6784 MGD |
18909 | if (thumb_mode) |
18910 | inst.instruction |= 0xfc000000; | |
18911 | else | |
18912 | inst.instruction |= 0xf0000000; | |
18913 | } | |
18914 | else | |
18915 | { | |
037e8744 | 18916 | int_encode: |
7e8e6784 | 18917 | { |
cc933301 JW |
18918 | unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080, |
18919 | 0x100, 0x180, 0x0, 0x080}; | |
037e8744 | 18920 | |
7e8e6784 | 18921 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 18922 | |
dd9634d9 AV |
18923 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) |
18924 | { | |
18925 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
18926 | return; | |
18927 | } | |
037e8744 | 18928 | |
7e8e6784 MGD |
18929 | if (flavour != neon_cvt_flavour_invalid) |
18930 | inst.instruction |= enctab[flavour]; | |
037e8744 | 18931 | |
7e8e6784 MGD |
18932 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
18933 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
18934 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
18935 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
18936 | inst.instruction |= neon_quad (rs) << 6; | |
cc933301 JW |
18937 | if (flavour >= neon_cvt_flavour_s16_f16 |
18938 | && flavour <= neon_cvt_flavour_f16_u16) | |
18939 | /* Half precision. */ | |
18940 | inst.instruction |= 1 << 18; | |
18941 | else | |
18942 | inst.instruction |= 2 << 18; | |
037e8744 | 18943 | |
7e8e6784 MGD |
18944 | neon_dp_fixup (&inst); |
18945 | } | |
18946 | } | |
18947 | break; | |
037e8744 | 18948 | |
8e79c3df CM |
18949 | /* Half-precision conversions for Advanced SIMD -- neon. */ |
18950 | case NS_QD: | |
18951 | case NS_DQ: | |
bc52d49c MM |
18952 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
18953 | return; | |
8e79c3df CM |
18954 | |
18955 | if ((rs == NS_DQ) | |
18956 | && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) | |
18957 | { | |
18958 | as_bad (_("operand size must match register width")); | |
18959 | break; | |
18960 | } | |
18961 | ||
18962 | if ((rs == NS_QD) | |
18963 | && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) | |
18964 | { | |
18965 | as_bad (_("operand size must match register width")); | |
18966 | break; | |
18967 | } | |
18968 | ||
18969 | if (rs == NS_DQ) | |
477330fc | 18970 | inst.instruction = 0x3b60600; |
8e79c3df CM |
18971 | else |
18972 | inst.instruction = 0x3b60700; | |
18973 | ||
18974 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
18975 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
18976 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
18977 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
88714cb8 | 18978 | neon_dp_fixup (&inst); |
8e79c3df CM |
18979 | break; |
18980 | ||
037e8744 JB |
18981 | default: |
18982 | /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ | |
7e8e6784 MGD |
18983 | if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z) |
18984 | do_vfp_nsyn_cvt (rs, flavour); | |
18985 | else | |
18986 | do_vfp_nsyn_cvt_fpv8 (flavour, mode); | |
5287ad62 | 18987 | } |
5287ad62 JB |
18988 | } |
18989 | ||
e3e535bc NC |
18990 | static void |
18991 | do_neon_cvtr (void) | |
18992 | { | |
7e8e6784 | 18993 | do_neon_cvt_1 (neon_cvt_mode_x); |
e3e535bc NC |
18994 | } |
18995 | ||
18996 | static void | |
18997 | do_neon_cvt (void) | |
18998 | { | |
7e8e6784 MGD |
18999 | do_neon_cvt_1 (neon_cvt_mode_z); |
19000 | } | |
19001 | ||
19002 | static void | |
19003 | do_neon_cvta (void) | |
19004 | { | |
19005 | do_neon_cvt_1 (neon_cvt_mode_a); | |
19006 | } | |
19007 | ||
19008 | static void | |
19009 | do_neon_cvtn (void) | |
19010 | { | |
19011 | do_neon_cvt_1 (neon_cvt_mode_n); | |
19012 | } | |
19013 | ||
19014 | static void | |
19015 | do_neon_cvtp (void) | |
19016 | { | |
19017 | do_neon_cvt_1 (neon_cvt_mode_p); | |
19018 | } | |
19019 | ||
19020 | static void | |
19021 | do_neon_cvtm (void) | |
19022 | { | |
19023 | do_neon_cvt_1 (neon_cvt_mode_m); | |
e3e535bc NC |
19024 | } |
19025 | ||
8e79c3df | 19026 | static void |
c70a8987 | 19027 | do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double) |
8e79c3df | 19028 | { |
c70a8987 MGD |
19029 | if (is_double) |
19030 | mark_feature_used (&fpu_vfp_ext_armv8); | |
8e79c3df | 19031 | |
c70a8987 MGD |
19032 | encode_arm_vfp_reg (inst.operands[0].reg, |
19033 | (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd); | |
19034 | encode_arm_vfp_reg (inst.operands[1].reg, | |
19035 | (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm); | |
19036 | inst.instruction |= to ? 0x10000 : 0; | |
19037 | inst.instruction |= t ? 0x80 : 0; | |
19038 | inst.instruction |= is_double ? 0x100 : 0; | |
19039 | do_vfp_cond_or_thumb (); | |
19040 | } | |
8e79c3df | 19041 | |
c70a8987 MGD |
19042 | static void |
19043 | do_neon_cvttb_1 (bfd_boolean t) | |
19044 | { | |
d54af2d0 | 19045 | enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD, |
dd9634d9 | 19046 | NS_DF, NS_DH, NS_QQ, NS_QQI, NS_NULL); |
8e79c3df | 19047 | |
c70a8987 MGD |
19048 | if (rs == NS_NULL) |
19049 | return; | |
dd9634d9 AV |
19050 | else if (rs == NS_QQ || rs == NS_QQI) |
19051 | { | |
19052 | int single_to_half = 0; | |
64c350f2 | 19053 | if (!check_simd_pred_availability (TRUE, NEON_CHECK_ARCH)) |
dd9634d9 AV |
19054 | return; |
19055 | ||
19056 | enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs); | |
19057 | ||
19058 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
19059 | && (flavour == neon_cvt_flavour_u16_f16 | |
19060 | || flavour == neon_cvt_flavour_s16_f16 | |
19061 | || flavour == neon_cvt_flavour_f16_s16 | |
19062 | || flavour == neon_cvt_flavour_f16_u16 | |
19063 | || flavour == neon_cvt_flavour_u32_f32 | |
19064 | || flavour == neon_cvt_flavour_s32_f32 | |
19065 | || flavour == neon_cvt_flavour_f32_s32 | |
19066 | || flavour == neon_cvt_flavour_f32_u32)) | |
19067 | { | |
19068 | inst.cond = 0xf; | |
19069 | inst.instruction = N_MNEM_vcvt; | |
19070 | set_pred_insn_type (INSIDE_VPT_INSN); | |
19071 | do_neon_cvt_1 (neon_cvt_mode_z); | |
19072 | return; | |
19073 | } | |
19074 | else if (rs == NS_QQ && flavour == neon_cvt_flavour_f32_f16) | |
19075 | single_to_half = 1; | |
19076 | else if (rs == NS_QQ && flavour != neon_cvt_flavour_f16_f32) | |
19077 | { | |
19078 | first_error (BAD_FPU); | |
19079 | return; | |
19080 | } | |
19081 | ||
19082 | inst.instruction = 0xee3f0e01; | |
19083 | inst.instruction |= single_to_half << 28; | |
19084 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
19085 | inst.instruction |= LOW4 (inst.operands[0].reg) << 13; | |
19086 | inst.instruction |= t << 12; | |
19087 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
19088 | inst.instruction |= LOW4 (inst.operands[1].reg) << 1; | |
19089 | inst.is_neon = 1; | |
19090 | } | |
c70a8987 MGD |
19091 | else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype) |
19092 | { | |
19093 | inst.error = NULL; | |
19094 | do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE); | |
19095 | } | |
19096 | else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype) | |
19097 | { | |
19098 | inst.error = NULL; | |
19099 | do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE); | |
19100 | } | |
19101 | else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype) | |
19102 | { | |
a715796b TG |
19103 | /* The VCVTB and VCVTT instructions with D-register operands |
19104 | don't work for SP only targets. */ | |
19105 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
19106 | _(BAD_FPU)); | |
19107 | ||
c70a8987 MGD |
19108 | inst.error = NULL; |
19109 | do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE); | |
19110 | } | |
19111 | else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype) | |
19112 | { | |
a715796b TG |
19113 | /* The VCVTB and VCVTT instructions with D-register operands |
19114 | don't work for SP only targets. */ | |
19115 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
19116 | _(BAD_FPU)); | |
19117 | ||
c70a8987 MGD |
19118 | inst.error = NULL; |
19119 | do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE); | |
19120 | } | |
19121 | else | |
19122 | return; | |
19123 | } | |
19124 | ||
19125 | static void | |
19126 | do_neon_cvtb (void) | |
19127 | { | |
19128 | do_neon_cvttb_1 (FALSE); | |
8e79c3df CM |
19129 | } |
19130 | ||
19131 | ||
19132 | static void | |
19133 | do_neon_cvtt (void) | |
19134 | { | |
c70a8987 | 19135 | do_neon_cvttb_1 (TRUE); |
8e79c3df CM |
19136 | } |
19137 | ||
5287ad62 JB |
19138 | static void |
19139 | neon_move_immediate (void) | |
19140 | { | |
037e8744 JB |
19141 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
19142 | struct neon_type_el et = neon_check_type (2, rs, | |
19143 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
5287ad62 | 19144 | unsigned immlo, immhi = 0, immbits; |
c96612cc | 19145 | int op, cmode, float_p; |
5287ad62 | 19146 | |
037e8744 | 19147 | constraint (et.type == NT_invtype, |
477330fc | 19148 | _("operand size must be specified for immediate VMOV")); |
037e8744 | 19149 | |
5287ad62 JB |
19150 | /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ |
19151 | op = (inst.instruction & (1 << 5)) != 0; | |
19152 | ||
19153 | immlo = inst.operands[1].imm; | |
19154 | if (inst.operands[1].regisimm) | |
19155 | immhi = inst.operands[1].reg; | |
19156 | ||
19157 | constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, | |
477330fc | 19158 | _("immediate has bits set outside the operand size")); |
5287ad62 | 19159 | |
c96612cc JB |
19160 | float_p = inst.operands[1].immisfloat; |
19161 | ||
19162 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, | |
477330fc | 19163 | et.size, et.type)) == FAIL) |
5287ad62 JB |
19164 | { |
19165 | /* Invert relevant bits only. */ | |
19166 | neon_invert_size (&immlo, &immhi, et.size); | |
19167 | /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable | |
477330fc RM |
19168 | with one or the other; those cases are caught by |
19169 | neon_cmode_for_move_imm. */ | |
5287ad62 | 19170 | op = !op; |
c96612cc JB |
19171 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, |
19172 | &op, et.size, et.type)) == FAIL) | |
477330fc RM |
19173 | { |
19174 | first_error (_("immediate out of range")); | |
19175 | return; | |
19176 | } | |
5287ad62 JB |
19177 | } |
19178 | ||
19179 | inst.instruction &= ~(1 << 5); | |
19180 | inst.instruction |= op << 5; | |
19181 | ||
19182 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
19183 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
037e8744 | 19184 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
19185 | inst.instruction |= cmode << 8; |
19186 | ||
19187 | neon_write_immbits (immbits); | |
19188 | } | |
19189 | ||
19190 | static void | |
19191 | do_neon_mvn (void) | |
19192 | { | |
64c350f2 | 19193 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
1a186d29 AV |
19194 | return; |
19195 | ||
5287ad62 JB |
19196 | if (inst.operands[1].isreg) |
19197 | { | |
1a186d29 AV |
19198 | enum neon_shape rs; |
19199 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
19200 | rs = neon_select_shape (NS_QQ, NS_NULL); | |
19201 | else | |
19202 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
5f4273c7 | 19203 | |
88714cb8 | 19204 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
19205 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
19206 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
19207 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
19208 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 19209 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
19210 | } |
19211 | else | |
19212 | { | |
88714cb8 | 19213 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
19214 | neon_move_immediate (); |
19215 | } | |
19216 | ||
88714cb8 | 19217 | neon_dp_fixup (&inst); |
1a186d29 AV |
19218 | |
19219 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
19220 | { | |
19221 | constraint (!inst.operands[1].isreg && !inst.operands[0].isquad, BAD_FPU); | |
19222 | constraint ((inst.instruction & 0xd00) == 0xd00, | |
19223 | _("immediate value out of range")); | |
19224 | } | |
5287ad62 JB |
19225 | } |
19226 | ||
19227 | /* Encode instructions of form: | |
19228 | ||
19229 | |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
5f4273c7 | 19230 | | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */ |
5287ad62 JB |
19231 | |
19232 | static void | |
19233 | neon_mixed_length (struct neon_type_el et, unsigned size) | |
19234 | { | |
19235 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
19236 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
19237 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
19238 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
19239 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
19240 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
19241 | inst.instruction |= (et.type == NT_unsigned) << 24; | |
19242 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 19243 | |
88714cb8 | 19244 | neon_dp_fixup (&inst); |
5287ad62 JB |
19245 | } |
19246 | ||
19247 | static void | |
19248 | do_neon_dyadic_long (void) | |
19249 | { | |
5ee91343 AV |
19250 | enum neon_shape rs = neon_select_shape (NS_QDD, NS_QQQ, NS_QQR, NS_NULL); |
19251 | if (rs == NS_QDD) | |
19252 | { | |
19253 | if (vfp_or_neon_is_neon (NEON_CHECK_ARCH | NEON_CHECK_CC) == FAIL) | |
19254 | return; | |
19255 | ||
19256 | NEON_ENCODE (INTEGER, inst); | |
19257 | /* FIXME: Type checking for lengthening op. */ | |
19258 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
19259 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
19260 | neon_mixed_length (et, et.size); | |
19261 | } | |
19262 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
19263 | && (inst.cond == 0xf || inst.cond == 0x10)) | |
19264 | { | |
19265 | /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd | |
19266 | in an IT block with le/lt conditions. */ | |
19267 | ||
19268 | if (inst.cond == 0xf) | |
19269 | inst.cond = 0xb; | |
19270 | else if (inst.cond == 0x10) | |
19271 | inst.cond = 0xd; | |
19272 | ||
19273 | inst.pred_insn_type = INSIDE_IT_INSN; | |
19274 | ||
19275 | if (inst.instruction == N_MNEM_vaddl) | |
19276 | { | |
19277 | inst.instruction = N_MNEM_vadd; | |
19278 | do_neon_addsub_if_i (); | |
19279 | } | |
19280 | else if (inst.instruction == N_MNEM_vsubl) | |
19281 | { | |
19282 | inst.instruction = N_MNEM_vsub; | |
19283 | do_neon_addsub_if_i (); | |
19284 | } | |
19285 | else if (inst.instruction == N_MNEM_vabdl) | |
19286 | { | |
19287 | inst.instruction = N_MNEM_vabd; | |
19288 | do_neon_dyadic_if_su (); | |
19289 | } | |
19290 | } | |
19291 | else | |
19292 | first_error (BAD_FPU); | |
5287ad62 JB |
19293 | } |
19294 | ||
19295 | static void | |
19296 | do_neon_abal (void) | |
19297 | { | |
19298 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
19299 | N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
19300 | neon_mixed_length (et, et.size); | |
19301 | } | |
19302 | ||
19303 | static void | |
19304 | neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) | |
19305 | { | |
19306 | if (inst.operands[2].isscalar) | |
19307 | { | |
dcbf9037 | 19308 | struct neon_type_el et = neon_check_type (3, NS_QDS, |
477330fc | 19309 | N_EQK | N_DBL, N_EQK, regtypes | N_KEY); |
88714cb8 | 19310 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
19311 | neon_mul_mac (et, et.type == NT_unsigned); |
19312 | } | |
19313 | else | |
19314 | { | |
19315 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
477330fc | 19316 | N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); |
88714cb8 | 19317 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
19318 | neon_mixed_length (et, et.size); |
19319 | } | |
19320 | } | |
19321 | ||
19322 | static void | |
19323 | do_neon_mac_maybe_scalar_long (void) | |
19324 | { | |
19325 | neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); | |
19326 | } | |
19327 | ||
dec41383 JW |
19328 | /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's |
19329 | internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */ | |
19330 | ||
19331 | static unsigned | |
19332 | neon_scalar_for_fmac_fp16_long (unsigned scalar, unsigned quad_p) | |
19333 | { | |
19334 | unsigned regno = NEON_SCALAR_REG (scalar); | |
19335 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
19336 | ||
19337 | if (quad_p) | |
19338 | { | |
19339 | if (regno > 7 || elno > 3) | |
19340 | goto bad_scalar; | |
19341 | ||
19342 | return ((regno & 0x7) | |
19343 | | ((elno & 0x1) << 3) | |
19344 | | (((elno >> 1) & 0x1) << 5)); | |
19345 | } | |
19346 | else | |
19347 | { | |
19348 | if (regno > 15 || elno > 1) | |
19349 | goto bad_scalar; | |
19350 | ||
19351 | return (((regno & 0x1) << 5) | |
19352 | | ((regno >> 1) & 0x7) | |
19353 | | ((elno & 0x1) << 3)); | |
19354 | } | |
19355 | ||
19356 | bad_scalar: | |
19357 | first_error (_("scalar out of range for multiply instruction")); | |
19358 | return 0; | |
19359 | } | |
19360 | ||
19361 | static void | |
19362 | do_neon_fmac_maybe_scalar_long (int subtype) | |
19363 | { | |
19364 | enum neon_shape rs; | |
19365 | int high8; | |
19366 | /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size" | |
19367 | field (bits[21:20]) has different meaning. For scalar index variant, it's | |
19368 | used to differentiate add and subtract, otherwise it's with fixed value | |
19369 | 0x2. */ | |
19370 | int size = -1; | |
19371 | ||
19372 | if (inst.cond != COND_ALWAYS) | |
19373 | as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the " | |
19374 | "behaviour is UNPREDICTABLE")); | |
19375 | ||
01f48020 | 19376 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16_fml), |
dec41383 JW |
19377 | _(BAD_FP16)); |
19378 | ||
19379 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8), | |
19380 | _(BAD_FPU)); | |
19381 | ||
19382 | /* vfmal/vfmsl are in three-same D/Q register format or the third operand can | |
19383 | be a scalar index register. */ | |
19384 | if (inst.operands[2].isscalar) | |
19385 | { | |
19386 | high8 = 0xfe000000; | |
19387 | if (subtype) | |
19388 | size = 16; | |
19389 | rs = neon_select_shape (NS_DHS, NS_QDS, NS_NULL); | |
19390 | } | |
19391 | else | |
19392 | { | |
19393 | high8 = 0xfc000000; | |
19394 | size = 32; | |
19395 | if (subtype) | |
19396 | inst.instruction |= (0x1 << 23); | |
19397 | rs = neon_select_shape (NS_DHH, NS_QDD, NS_NULL); | |
19398 | } | |
19399 | ||
19400 | neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16); | |
19401 | ||
19402 | /* "opcode" from template has included "ubit", so simply pass 0 here. Also, | |
19403 | the "S" bit in size field has been reused to differentiate vfmal and vfmsl, | |
19404 | so we simply pass -1 as size. */ | |
19405 | unsigned quad_p = (rs == NS_QDD || rs == NS_QDS); | |
19406 | neon_three_same (quad_p, 0, size); | |
19407 | ||
19408 | /* Undo neon_dp_fixup. Redo the high eight bits. */ | |
19409 | inst.instruction &= 0x00ffffff; | |
19410 | inst.instruction |= high8; | |
19411 | ||
19412 | #define LOW1(R) ((R) & 0x1) | |
19413 | #define HI4(R) (((R) >> 1) & 0xf) | |
19414 | /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on | |
19415 | whether the instruction is in Q form and whether Vm is a scalar indexed | |
19416 | operand. */ | |
19417 | if (inst.operands[2].isscalar) | |
19418 | { | |
19419 | unsigned rm | |
19420 | = neon_scalar_for_fmac_fp16_long (inst.operands[2].reg, quad_p); | |
19421 | inst.instruction &= 0xffffffd0; | |
19422 | inst.instruction |= rm; | |
19423 | ||
19424 | if (!quad_p) | |
19425 | { | |
19426 | /* Redo Rn as well. */ | |
19427 | inst.instruction &= 0xfff0ff7f; | |
19428 | inst.instruction |= HI4 (inst.operands[1].reg) << 16; | |
19429 | inst.instruction |= LOW1 (inst.operands[1].reg) << 7; | |
19430 | } | |
19431 | } | |
19432 | else if (!quad_p) | |
19433 | { | |
19434 | /* Redo Rn and Rm. */ | |
19435 | inst.instruction &= 0xfff0ff50; | |
19436 | inst.instruction |= HI4 (inst.operands[1].reg) << 16; | |
19437 | inst.instruction |= LOW1 (inst.operands[1].reg) << 7; | |
19438 | inst.instruction |= HI4 (inst.operands[2].reg); | |
19439 | inst.instruction |= LOW1 (inst.operands[2].reg) << 5; | |
19440 | } | |
19441 | } | |
19442 | ||
19443 | static void | |
19444 | do_neon_vfmal (void) | |
19445 | { | |
19446 | return do_neon_fmac_maybe_scalar_long (0); | |
19447 | } | |
19448 | ||
19449 | static void | |
19450 | do_neon_vfmsl (void) | |
19451 | { | |
19452 | return do_neon_fmac_maybe_scalar_long (1); | |
19453 | } | |
19454 | ||
5287ad62 JB |
19455 | static void |
19456 | do_neon_dyadic_wide (void) | |
19457 | { | |
19458 | struct neon_type_el et = neon_check_type (3, NS_QQD, | |
19459 | N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); | |
19460 | neon_mixed_length (et, et.size); | |
19461 | } | |
19462 | ||
19463 | static void | |
19464 | do_neon_dyadic_narrow (void) | |
19465 | { | |
19466 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
19467 | N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); | |
428e3f1f PB |
19468 | /* Operand sign is unimportant, and the U bit is part of the opcode, |
19469 | so force the operand type to integer. */ | |
19470 | et.type = NT_integer; | |
5287ad62 JB |
19471 | neon_mixed_length (et, et.size / 2); |
19472 | } | |
19473 | ||
19474 | static void | |
19475 | do_neon_mul_sat_scalar_long (void) | |
19476 | { | |
19477 | neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); | |
19478 | } | |
19479 | ||
19480 | static void | |
19481 | do_neon_vmull (void) | |
19482 | { | |
19483 | if (inst.operands[2].isscalar) | |
19484 | do_neon_mac_maybe_scalar_long (); | |
19485 | else | |
19486 | { | |
19487 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
477330fc | 19488 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY); |
4f51b4bd | 19489 | |
5287ad62 | 19490 | if (et.type == NT_poly) |
477330fc | 19491 | NEON_ENCODE (POLY, inst); |
5287ad62 | 19492 | else |
477330fc | 19493 | NEON_ENCODE (INTEGER, inst); |
4f51b4bd MGD |
19494 | |
19495 | /* For polynomial encoding the U bit must be zero, and the size must | |
19496 | be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non | |
19497 | obviously, as 0b10). */ | |
19498 | if (et.size == 64) | |
19499 | { | |
19500 | /* Check we're on the correct architecture. */ | |
19501 | if (!mark_feature_used (&fpu_crypto_ext_armv8)) | |
19502 | inst.error = | |
19503 | _("Instruction form not available on this architecture."); | |
19504 | ||
19505 | et.size = 32; | |
19506 | } | |
19507 | ||
5287ad62 JB |
19508 | neon_mixed_length (et, et.size); |
19509 | } | |
19510 | } | |
19511 | ||
19512 | static void | |
19513 | do_neon_ext (void) | |
19514 | { | |
037e8744 | 19515 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
5287ad62 JB |
19516 | struct neon_type_el et = neon_check_type (3, rs, |
19517 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
19518 | unsigned imm = (inst.operands[3].imm * et.size) / 8; | |
35997600 NC |
19519 | |
19520 | constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), | |
19521 | _("shift out of range")); | |
5287ad62 JB |
19522 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
19523 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
19524 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
19525 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
19526 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
19527 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
037e8744 | 19528 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 | 19529 | inst.instruction |= imm << 8; |
5f4273c7 | 19530 | |
88714cb8 | 19531 | neon_dp_fixup (&inst); |
5287ad62 JB |
19532 | } |
19533 | ||
19534 | static void | |
19535 | do_neon_rev (void) | |
19536 | { | |
64c350f2 | 19537 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
4401c241 AV |
19538 | return; |
19539 | ||
19540 | enum neon_shape rs; | |
19541 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
19542 | rs = neon_select_shape (NS_QQ, NS_NULL); | |
19543 | else | |
19544 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
19545 | ||
5287ad62 JB |
19546 | struct neon_type_el et = neon_check_type (2, rs, |
19547 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
4401c241 | 19548 | |
5287ad62 JB |
19549 | unsigned op = (inst.instruction >> 7) & 3; |
19550 | /* N (width of reversed regions) is encoded as part of the bitmask. We | |
19551 | extract it here to check the elements to be reversed are smaller. | |
19552 | Otherwise we'd get a reserved instruction. */ | |
19553 | unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; | |
4401c241 AV |
19554 | |
19555 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) && elsize == 64 | |
19556 | && inst.operands[0].reg == inst.operands[1].reg) | |
19557 | as_tsktsk (_("Warning: 64-bit element size and same destination and source" | |
19558 | " operands makes instruction UNPREDICTABLE")); | |
19559 | ||
9c2799c2 | 19560 | gas_assert (elsize != 0); |
5287ad62 | 19561 | constraint (et.size >= elsize, |
477330fc | 19562 | _("elements must be smaller than reversal region")); |
037e8744 | 19563 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
19564 | } |
19565 | ||
19566 | static void | |
19567 | do_neon_dup (void) | |
19568 | { | |
19569 | if (inst.operands[1].isscalar) | |
19570 | { | |
b409bdb6 AV |
19571 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1), |
19572 | BAD_FPU); | |
037e8744 | 19573 | enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); |
dcbf9037 | 19574 | struct neon_type_el et = neon_check_type (2, rs, |
477330fc | 19575 | N_EQK, N_8 | N_16 | N_32 | N_KEY); |
5287ad62 | 19576 | unsigned sizebits = et.size >> 3; |
dcbf9037 | 19577 | unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); |
5287ad62 | 19578 | int logsize = neon_logbits (et.size); |
dcbf9037 | 19579 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; |
037e8744 JB |
19580 | |
19581 | if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) | |
477330fc | 19582 | return; |
037e8744 | 19583 | |
88714cb8 | 19584 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
19585 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
19586 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
19587 | inst.instruction |= LOW4 (dm); | |
19588 | inst.instruction |= HI1 (dm) << 5; | |
037e8744 | 19589 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
19590 | inst.instruction |= x << 17; |
19591 | inst.instruction |= sizebits << 16; | |
5f4273c7 | 19592 | |
88714cb8 | 19593 | neon_dp_fixup (&inst); |
5287ad62 JB |
19594 | } |
19595 | else | |
19596 | { | |
037e8744 JB |
19597 | enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); |
19598 | struct neon_type_el et = neon_check_type (2, rs, | |
477330fc | 19599 | N_8 | N_16 | N_32 | N_KEY, N_EQK); |
b409bdb6 AV |
19600 | if (rs == NS_QR) |
19601 | { | |
64c350f2 | 19602 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH)) |
b409bdb6 AV |
19603 | return; |
19604 | } | |
19605 | else | |
19606 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1), | |
19607 | BAD_FPU); | |
19608 | ||
19609 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
19610 | { | |
19611 | if (inst.operands[1].reg == REG_SP) | |
19612 | as_tsktsk (MVE_BAD_SP); | |
19613 | else if (inst.operands[1].reg == REG_PC) | |
19614 | as_tsktsk (MVE_BAD_PC); | |
19615 | } | |
19616 | ||
5287ad62 | 19617 | /* Duplicate ARM register to lanes of vector. */ |
88714cb8 | 19618 | NEON_ENCODE (ARMREG, inst); |
5287ad62 | 19619 | switch (et.size) |
477330fc RM |
19620 | { |
19621 | case 8: inst.instruction |= 0x400000; break; | |
19622 | case 16: inst.instruction |= 0x000020; break; | |
19623 | case 32: inst.instruction |= 0x000000; break; | |
19624 | default: break; | |
19625 | } | |
5287ad62 JB |
19626 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; |
19627 | inst.instruction |= LOW4 (inst.operands[0].reg) << 16; | |
19628 | inst.instruction |= HI1 (inst.operands[0].reg) << 7; | |
037e8744 | 19629 | inst.instruction |= neon_quad (rs) << 21; |
5287ad62 | 19630 | /* The encoding for this instruction is identical for the ARM and Thumb |
477330fc | 19631 | variants, except for the condition field. */ |
037e8744 | 19632 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
19633 | } |
19634 | } | |
19635 | ||
57785aa2 AV |
19636 | static void |
19637 | do_mve_mov (int toQ) | |
19638 | { | |
19639 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
19640 | return; | |
19641 | if (inst.cond > COND_ALWAYS) | |
19642 | inst.pred_insn_type = MVE_UNPREDICABLE_INSN; | |
19643 | ||
19644 | unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3; | |
19645 | if (toQ) | |
19646 | { | |
19647 | Q0 = 0; | |
19648 | Q1 = 1; | |
19649 | Rt = 2; | |
19650 | Rt2 = 3; | |
19651 | } | |
19652 | ||
19653 | constraint (inst.operands[Q0].reg != inst.operands[Q1].reg + 2, | |
19654 | _("Index one must be [2,3] and index two must be two less than" | |
19655 | " index one.")); | |
19656 | constraint (inst.operands[Rt].reg == inst.operands[Rt2].reg, | |
19657 | _("General purpose registers may not be the same")); | |
19658 | constraint (inst.operands[Rt].reg == REG_SP | |
19659 | || inst.operands[Rt2].reg == REG_SP, | |
19660 | BAD_SP); | |
19661 | constraint (inst.operands[Rt].reg == REG_PC | |
19662 | || inst.operands[Rt2].reg == REG_PC, | |
19663 | BAD_PC); | |
19664 | ||
19665 | inst.instruction = 0xec000f00; | |
19666 | inst.instruction |= HI1 (inst.operands[Q1].reg / 32) << 23; | |
19667 | inst.instruction |= !!toQ << 20; | |
19668 | inst.instruction |= inst.operands[Rt2].reg << 16; | |
19669 | inst.instruction |= LOW4 (inst.operands[Q1].reg / 32) << 13; | |
19670 | inst.instruction |= (inst.operands[Q1].reg % 4) << 4; | |
19671 | inst.instruction |= inst.operands[Rt].reg; | |
19672 | } | |
19673 | ||
19674 | static void | |
19675 | do_mve_movn (void) | |
19676 | { | |
19677 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
19678 | return; | |
19679 | ||
19680 | if (inst.cond > COND_ALWAYS) | |
19681 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
19682 | else | |
19683 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
19684 | ||
19685 | struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_I16 | N_I32 | |
19686 | | N_KEY); | |
19687 | ||
19688 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
19689 | inst.instruction |= (neon_logbits (et.size) - 1) << 18; | |
19690 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
19691 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
19692 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
19693 | inst.is_neon = 1; | |
19694 | ||
19695 | } | |
19696 | ||
5287ad62 JB |
19697 | /* VMOV has particularly many variations. It can be one of: |
19698 | 0. VMOV<c><q> <Qd>, <Qm> | |
19699 | 1. VMOV<c><q> <Dd>, <Dm> | |
19700 | (Register operations, which are VORR with Rm = Rn.) | |
19701 | 2. VMOV<c><q>.<dt> <Qd>, #<imm> | |
19702 | 3. VMOV<c><q>.<dt> <Dd>, #<imm> | |
19703 | (Immediate loads.) | |
19704 | 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> | |
19705 | (ARM register to scalar.) | |
19706 | 5. VMOV<c><q> <Dm>, <Rd>, <Rn> | |
19707 | (Two ARM registers to vector.) | |
19708 | 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> | |
19709 | (Scalar to ARM register.) | |
19710 | 7. VMOV<c><q> <Rd>, <Rn>, <Dm> | |
19711 | (Vector to two ARM registers.) | |
037e8744 JB |
19712 | 8. VMOV.F32 <Sd>, <Sm> |
19713 | 9. VMOV.F64 <Dd>, <Dm> | |
19714 | (VFP register moves.) | |
19715 | 10. VMOV.F32 <Sd>, #imm | |
19716 | 11. VMOV.F64 <Dd>, #imm | |
19717 | (VFP float immediate load.) | |
19718 | 12. VMOV <Rd>, <Sm> | |
19719 | (VFP single to ARM reg.) | |
19720 | 13. VMOV <Sd>, <Rm> | |
19721 | (ARM reg to VFP single.) | |
19722 | 14. VMOV <Rd>, <Re>, <Sn>, <Sm> | |
19723 | (Two ARM regs to two VFP singles.) | |
19724 | 15. VMOV <Sd>, <Se>, <Rn>, <Rm> | |
19725 | (Two VFP singles to two ARM regs.) | |
57785aa2 AV |
19726 | 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> |
19727 | 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> | |
19728 | 18. VMOV<c>.<dt> <Rt>, <Qn[idx]> | |
19729 | 19. VMOV<c>.<dt> <Qd[idx]>, <Rt> | |
5f4273c7 | 19730 | |
037e8744 JB |
19731 | These cases can be disambiguated using neon_select_shape, except cases 1/9 |
19732 | and 3/11 which depend on the operand type too. | |
5f4273c7 | 19733 | |
5287ad62 | 19734 | All the encoded bits are hardcoded by this function. |
5f4273c7 | 19735 | |
b7fc2769 JB |
19736 | Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). |
19737 | Cases 5, 7 may be used with VFPv2 and above. | |
5f4273c7 | 19738 | |
5287ad62 | 19739 | FIXME: Some of the checking may be a bit sloppy (in a couple of cases you |
5f4273c7 | 19740 | can specify a type where it doesn't make sense to, and is ignored). */ |
5287ad62 JB |
19741 | |
19742 | static void | |
19743 | do_neon_mov (void) | |
19744 | { | |
57785aa2 AV |
19745 | enum neon_shape rs = neon_select_shape (NS_RRSS, NS_SSRR, NS_RRFF, NS_FFRR, |
19746 | NS_DRR, NS_RRD, NS_QQ, NS_DD, NS_QI, | |
19747 | NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, | |
19748 | NS_RF, NS_FR, NS_HR, NS_RH, NS_HI, | |
19749 | NS_NULL); | |
037e8744 JB |
19750 | struct neon_type_el et; |
19751 | const char *ldconst = 0; | |
5287ad62 | 19752 | |
037e8744 | 19753 | switch (rs) |
5287ad62 | 19754 | { |
037e8744 JB |
19755 | case NS_DD: /* case 1/9. */ |
19756 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
19757 | /* It is not an error here if no type is given. */ | |
19758 | inst.error = NULL; | |
19759 | if (et.type == NT_float && et.size == 64) | |
477330fc RM |
19760 | { |
19761 | do_vfp_nsyn_opcode ("fcpyd"); | |
19762 | break; | |
19763 | } | |
037e8744 | 19764 | /* fall through. */ |
5287ad62 | 19765 | |
037e8744 JB |
19766 | case NS_QQ: /* case 0/1. */ |
19767 | { | |
64c350f2 AV |
19768 | if (!check_simd_pred_availability (FALSE, |
19769 | NEON_CHECK_CC | NEON_CHECK_ARCH)) | |
477330fc RM |
19770 | return; |
19771 | /* The architecture manual I have doesn't explicitly state which | |
19772 | value the U bit should have for register->register moves, but | |
19773 | the equivalent VORR instruction has U = 0, so do that. */ | |
19774 | inst.instruction = 0x0200110; | |
19775 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
19776 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
19777 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
19778 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
19779 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
19780 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
19781 | inst.instruction |= neon_quad (rs) << 6; | |
19782 | ||
19783 | neon_dp_fixup (&inst); | |
037e8744 JB |
19784 | } |
19785 | break; | |
5f4273c7 | 19786 | |
037e8744 JB |
19787 | case NS_DI: /* case 3/11. */ |
19788 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
19789 | inst.error = NULL; | |
19790 | if (et.type == NT_float && et.size == 64) | |
477330fc RM |
19791 | { |
19792 | /* case 11 (fconstd). */ | |
19793 | ldconst = "fconstd"; | |
19794 | goto encode_fconstd; | |
19795 | } | |
037e8744 JB |
19796 | /* fall through. */ |
19797 | ||
19798 | case NS_QI: /* case 2/3. */ | |
64c350f2 AV |
19799 | if (!check_simd_pred_availability (FALSE, |
19800 | NEON_CHECK_CC | NEON_CHECK_ARCH)) | |
477330fc | 19801 | return; |
037e8744 JB |
19802 | inst.instruction = 0x0800010; |
19803 | neon_move_immediate (); | |
88714cb8 | 19804 | neon_dp_fixup (&inst); |
5287ad62 | 19805 | break; |
5f4273c7 | 19806 | |
037e8744 JB |
19807 | case NS_SR: /* case 4. */ |
19808 | { | |
477330fc RM |
19809 | unsigned bcdebits = 0; |
19810 | int logsize; | |
19811 | unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); | |
19812 | unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); | |
037e8744 | 19813 | |
05ac0ffb JB |
19814 | /* .<size> is optional here, defaulting to .32. */ |
19815 | if (inst.vectype.elems == 0 | |
19816 | && inst.operands[0].vectype.type == NT_invtype | |
19817 | && inst.operands[1].vectype.type == NT_invtype) | |
19818 | { | |
19819 | inst.vectype.el[0].type = NT_untyped; | |
19820 | inst.vectype.el[0].size = 32; | |
19821 | inst.vectype.elems = 1; | |
19822 | } | |
19823 | ||
477330fc RM |
19824 | et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK); |
19825 | logsize = neon_logbits (et.size); | |
19826 | ||
57785aa2 AV |
19827 | if (et.size != 32) |
19828 | { | |
19829 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
19830 | && vfp_or_neon_is_neon (NEON_CHECK_ARCH) == FAIL) | |
19831 | return; | |
19832 | } | |
19833 | else | |
19834 | { | |
19835 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1) | |
19836 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
19837 | _(BAD_FPU)); | |
19838 | } | |
19839 | ||
19840 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
19841 | { | |
19842 | if (inst.operands[1].reg == REG_SP) | |
19843 | as_tsktsk (MVE_BAD_SP); | |
19844 | else if (inst.operands[1].reg == REG_PC) | |
19845 | as_tsktsk (MVE_BAD_PC); | |
19846 | } | |
19847 | unsigned size = inst.operands[0].isscalar == 1 ? 64 : 128; | |
19848 | ||
477330fc | 19849 | constraint (et.type == NT_invtype, _("bad type for scalar")); |
57785aa2 AV |
19850 | constraint (x >= size / et.size, _("scalar index out of range")); |
19851 | ||
477330fc RM |
19852 | |
19853 | switch (et.size) | |
19854 | { | |
19855 | case 8: bcdebits = 0x8; break; | |
19856 | case 16: bcdebits = 0x1; break; | |
19857 | case 32: bcdebits = 0x0; break; | |
19858 | default: ; | |
19859 | } | |
19860 | ||
57785aa2 | 19861 | bcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize; |
477330fc RM |
19862 | |
19863 | inst.instruction = 0xe000b10; | |
19864 | do_vfp_cond_or_thumb (); | |
19865 | inst.instruction |= LOW4 (dn) << 16; | |
19866 | inst.instruction |= HI1 (dn) << 7; | |
19867 | inst.instruction |= inst.operands[1].reg << 12; | |
19868 | inst.instruction |= (bcdebits & 3) << 5; | |
57785aa2 AV |
19869 | inst.instruction |= ((bcdebits >> 2) & 3) << 21; |
19870 | inst.instruction |= (x >> (3-logsize)) << 16; | |
037e8744 JB |
19871 | } |
19872 | break; | |
5f4273c7 | 19873 | |
037e8744 | 19874 | case NS_DRR: /* case 5 (fmdrr). */ |
57785aa2 AV |
19875 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) |
19876 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
477330fc | 19877 | _(BAD_FPU)); |
b7fc2769 | 19878 | |
037e8744 JB |
19879 | inst.instruction = 0xc400b10; |
19880 | do_vfp_cond_or_thumb (); | |
19881 | inst.instruction |= LOW4 (inst.operands[0].reg); | |
19882 | inst.instruction |= HI1 (inst.operands[0].reg) << 5; | |
19883 | inst.instruction |= inst.operands[1].reg << 12; | |
19884 | inst.instruction |= inst.operands[2].reg << 16; | |
19885 | break; | |
5f4273c7 | 19886 | |
037e8744 JB |
19887 | case NS_RS: /* case 6. */ |
19888 | { | |
477330fc RM |
19889 | unsigned logsize; |
19890 | unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); | |
19891 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); | |
19892 | unsigned abcdebits = 0; | |
037e8744 | 19893 | |
05ac0ffb JB |
19894 | /* .<dt> is optional here, defaulting to .32. */ |
19895 | if (inst.vectype.elems == 0 | |
19896 | && inst.operands[0].vectype.type == NT_invtype | |
19897 | && inst.operands[1].vectype.type == NT_invtype) | |
19898 | { | |
19899 | inst.vectype.el[0].type = NT_untyped; | |
19900 | inst.vectype.el[0].size = 32; | |
19901 | inst.vectype.elems = 1; | |
19902 | } | |
19903 | ||
91d6fa6a NC |
19904 | et = neon_check_type (2, NS_NULL, |
19905 | N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); | |
477330fc RM |
19906 | logsize = neon_logbits (et.size); |
19907 | ||
57785aa2 AV |
19908 | if (et.size != 32) |
19909 | { | |
19910 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
19911 | && vfp_or_neon_is_neon (NEON_CHECK_CC | |
19912 | | NEON_CHECK_ARCH) == FAIL) | |
19913 | return; | |
19914 | } | |
19915 | else | |
19916 | { | |
19917 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1) | |
19918 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
19919 | _(BAD_FPU)); | |
19920 | } | |
19921 | ||
19922 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
19923 | { | |
19924 | if (inst.operands[0].reg == REG_SP) | |
19925 | as_tsktsk (MVE_BAD_SP); | |
19926 | else if (inst.operands[0].reg == REG_PC) | |
19927 | as_tsktsk (MVE_BAD_PC); | |
19928 | } | |
19929 | ||
19930 | unsigned size = inst.operands[1].isscalar == 1 ? 64 : 128; | |
19931 | ||
477330fc | 19932 | constraint (et.type == NT_invtype, _("bad type for scalar")); |
57785aa2 | 19933 | constraint (x >= size / et.size, _("scalar index out of range")); |
477330fc RM |
19934 | |
19935 | switch (et.size) | |
19936 | { | |
19937 | case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; | |
19938 | case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; | |
19939 | case 32: abcdebits = 0x00; break; | |
19940 | default: ; | |
19941 | } | |
19942 | ||
57785aa2 | 19943 | abcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize; |
477330fc RM |
19944 | inst.instruction = 0xe100b10; |
19945 | do_vfp_cond_or_thumb (); | |
19946 | inst.instruction |= LOW4 (dn) << 16; | |
19947 | inst.instruction |= HI1 (dn) << 7; | |
19948 | inst.instruction |= inst.operands[0].reg << 12; | |
19949 | inst.instruction |= (abcdebits & 3) << 5; | |
19950 | inst.instruction |= (abcdebits >> 2) << 21; | |
57785aa2 | 19951 | inst.instruction |= (x >> (3-logsize)) << 16; |
037e8744 JB |
19952 | } |
19953 | break; | |
5f4273c7 | 19954 | |
037e8744 | 19955 | case NS_RRD: /* case 7 (fmrrd). */ |
57785aa2 AV |
19956 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) |
19957 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
477330fc | 19958 | _(BAD_FPU)); |
037e8744 JB |
19959 | |
19960 | inst.instruction = 0xc500b10; | |
19961 | do_vfp_cond_or_thumb (); | |
19962 | inst.instruction |= inst.operands[0].reg << 12; | |
19963 | inst.instruction |= inst.operands[1].reg << 16; | |
19964 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
19965 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
19966 | break; | |
5f4273c7 | 19967 | |
037e8744 JB |
19968 | case NS_FF: /* case 8 (fcpys). */ |
19969 | do_vfp_nsyn_opcode ("fcpys"); | |
19970 | break; | |
5f4273c7 | 19971 | |
9db2f6b4 | 19972 | case NS_HI: |
037e8744 JB |
19973 | case NS_FI: /* case 10 (fconsts). */ |
19974 | ldconst = "fconsts"; | |
4ef4710f | 19975 | encode_fconstd: |
58ed5c38 TC |
19976 | if (!inst.operands[1].immisfloat) |
19977 | { | |
4ef4710f | 19978 | unsigned new_imm; |
58ed5c38 | 19979 | /* Immediate has to fit in 8 bits so float is enough. */ |
4ef4710f NC |
19980 | float imm = (float) inst.operands[1].imm; |
19981 | memcpy (&new_imm, &imm, sizeof (float)); | |
19982 | /* But the assembly may have been written to provide an integer | |
19983 | bit pattern that equates to a float, so check that the | |
19984 | conversion has worked. */ | |
19985 | if (is_quarter_float (new_imm)) | |
19986 | { | |
19987 | if (is_quarter_float (inst.operands[1].imm)) | |
19988 | as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)")); | |
19989 | ||
19990 | inst.operands[1].imm = new_imm; | |
19991 | inst.operands[1].immisfloat = 1; | |
19992 | } | |
58ed5c38 TC |
19993 | } |
19994 | ||
037e8744 | 19995 | if (is_quarter_float (inst.operands[1].imm)) |
477330fc RM |
19996 | { |
19997 | inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); | |
19998 | do_vfp_nsyn_opcode (ldconst); | |
9db2f6b4 RL |
19999 | |
20000 | /* ARMv8.2 fp16 vmov.f16 instruction. */ | |
20001 | if (rs == NS_HI) | |
20002 | do_scalar_fp16_v82_encode (); | |
477330fc | 20003 | } |
5287ad62 | 20004 | else |
477330fc | 20005 | first_error (_("immediate out of range")); |
037e8744 | 20006 | break; |
5f4273c7 | 20007 | |
9db2f6b4 | 20008 | case NS_RH: |
037e8744 JB |
20009 | case NS_RF: /* case 12 (fmrs). */ |
20010 | do_vfp_nsyn_opcode ("fmrs"); | |
9db2f6b4 RL |
20011 | /* ARMv8.2 fp16 vmov.f16 instruction. */ |
20012 | if (rs == NS_RH) | |
20013 | do_scalar_fp16_v82_encode (); | |
037e8744 | 20014 | break; |
5f4273c7 | 20015 | |
9db2f6b4 | 20016 | case NS_HR: |
037e8744 JB |
20017 | case NS_FR: /* case 13 (fmsr). */ |
20018 | do_vfp_nsyn_opcode ("fmsr"); | |
9db2f6b4 RL |
20019 | /* ARMv8.2 fp16 vmov.f16 instruction. */ |
20020 | if (rs == NS_HR) | |
20021 | do_scalar_fp16_v82_encode (); | |
037e8744 | 20022 | break; |
5f4273c7 | 20023 | |
57785aa2 AV |
20024 | case NS_RRSS: |
20025 | do_mve_mov (0); | |
20026 | break; | |
20027 | case NS_SSRR: | |
20028 | do_mve_mov (1); | |
20029 | break; | |
20030 | ||
037e8744 JB |
20031 | /* The encoders for the fmrrs and fmsrr instructions expect three operands |
20032 | (one of which is a list), but we have parsed four. Do some fiddling to | |
20033 | make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 | |
20034 | expect. */ | |
20035 | case NS_RRFF: /* case 14 (fmrrs). */ | |
57785aa2 AV |
20036 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) |
20037 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
20038 | _(BAD_FPU)); | |
037e8744 | 20039 | constraint (inst.operands[3].reg != inst.operands[2].reg + 1, |
477330fc | 20040 | _("VFP registers must be adjacent")); |
037e8744 JB |
20041 | inst.operands[2].imm = 2; |
20042 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
20043 | do_vfp_nsyn_opcode ("fmrrs"); | |
20044 | break; | |
5f4273c7 | 20045 | |
037e8744 | 20046 | case NS_FFRR: /* case 15 (fmsrr). */ |
57785aa2 AV |
20047 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) |
20048 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
20049 | _(BAD_FPU)); | |
037e8744 | 20050 | constraint (inst.operands[1].reg != inst.operands[0].reg + 1, |
477330fc | 20051 | _("VFP registers must be adjacent")); |
037e8744 JB |
20052 | inst.operands[1] = inst.operands[2]; |
20053 | inst.operands[2] = inst.operands[3]; | |
20054 | inst.operands[0].imm = 2; | |
20055 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
20056 | do_vfp_nsyn_opcode ("fmsrr"); | |
5287ad62 | 20057 | break; |
5f4273c7 | 20058 | |
4c261dff NC |
20059 | case NS_NULL: |
20060 | /* neon_select_shape has determined that the instruction | |
20061 | shape is wrong and has already set the error message. */ | |
20062 | break; | |
20063 | ||
5287ad62 JB |
20064 | default: |
20065 | abort (); | |
20066 | } | |
20067 | } | |
20068 | ||
57785aa2 AV |
20069 | static void |
20070 | do_mve_movl (void) | |
20071 | { | |
20072 | if (!(inst.operands[0].present && inst.operands[0].isquad | |
20073 | && inst.operands[1].present && inst.operands[1].isquad | |
20074 | && !inst.operands[2].present)) | |
20075 | { | |
20076 | inst.instruction = 0; | |
20077 | inst.cond = 0xb; | |
20078 | if (thumb_mode) | |
20079 | set_pred_insn_type (INSIDE_IT_INSN); | |
20080 | do_neon_mov (); | |
20081 | return; | |
20082 | } | |
20083 | ||
20084 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
20085 | return; | |
20086 | ||
20087 | if (inst.cond != COND_ALWAYS) | |
20088 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
20089 | ||
20090 | struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_S8 | N_U8 | |
20091 | | N_S16 | N_U16 | N_KEY); | |
20092 | ||
20093 | inst.instruction |= (et.type == NT_unsigned) << 28; | |
20094 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
20095 | inst.instruction |= (neon_logbits (et.size) + 1) << 19; | |
20096 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
20097 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
20098 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
20099 | inst.is_neon = 1; | |
20100 | } | |
20101 | ||
5287ad62 JB |
20102 | static void |
20103 | do_neon_rshift_round_imm (void) | |
20104 | { | |
64c350f2 | 20105 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
4401c241 AV |
20106 | return; |
20107 | ||
20108 | enum neon_shape rs; | |
20109 | struct neon_type_el et; | |
20110 | ||
20111 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
20112 | { | |
20113 | rs = neon_select_shape (NS_QQI, NS_NULL); | |
20114 | et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY); | |
20115 | } | |
20116 | else | |
20117 | { | |
20118 | rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); | |
20119 | et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); | |
20120 | } | |
5287ad62 JB |
20121 | int imm = inst.operands[2].imm; |
20122 | ||
20123 | /* imm == 0 case is encoded as VMOV for V{R}SHR. */ | |
20124 | if (imm == 0) | |
20125 | { | |
20126 | inst.operands[2].present = 0; | |
20127 | do_neon_mov (); | |
20128 | return; | |
20129 | } | |
20130 | ||
20131 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 20132 | _("immediate out of range for shift")); |
037e8744 | 20133 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
477330fc | 20134 | et.size - imm); |
5287ad62 JB |
20135 | } |
20136 | ||
9db2f6b4 RL |
20137 | static void |
20138 | do_neon_movhf (void) | |
20139 | { | |
20140 | enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL); | |
20141 | constraint (rs != NS_HH, _("invalid suffix")); | |
20142 | ||
7bdf778b ASDV |
20143 | if (inst.cond != COND_ALWAYS) |
20144 | { | |
20145 | if (thumb_mode) | |
20146 | { | |
20147 | as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional," | |
20148 | " the behaviour is UNPREDICTABLE")); | |
20149 | } | |
20150 | else | |
20151 | { | |
20152 | inst.error = BAD_COND; | |
20153 | return; | |
20154 | } | |
20155 | } | |
20156 | ||
9db2f6b4 RL |
20157 | do_vfp_sp_monadic (); |
20158 | ||
20159 | inst.is_neon = 1; | |
20160 | inst.instruction |= 0xf0000000; | |
20161 | } | |
20162 | ||
5287ad62 JB |
20163 | static void |
20164 | do_neon_movl (void) | |
20165 | { | |
20166 | struct neon_type_el et = neon_check_type (2, NS_QD, | |
20167 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
20168 | unsigned sizebits = et.size >> 3; | |
20169 | inst.instruction |= sizebits << 19; | |
20170 | neon_two_same (0, et.type == NT_unsigned, -1); | |
20171 | } | |
20172 | ||
20173 | static void | |
20174 | do_neon_trn (void) | |
20175 | { | |
037e8744 | 20176 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
20177 | struct neon_type_el et = neon_check_type (2, rs, |
20178 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
88714cb8 | 20179 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 20180 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
20181 | } |
20182 | ||
20183 | static void | |
20184 | do_neon_zip_uzp (void) | |
20185 | { | |
037e8744 | 20186 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
20187 | struct neon_type_el et = neon_check_type (2, rs, |
20188 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
20189 | if (rs == NS_DD && et.size == 32) | |
20190 | { | |
20191 | /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ | |
20192 | inst.instruction = N_MNEM_vtrn; | |
20193 | do_neon_trn (); | |
20194 | return; | |
20195 | } | |
037e8744 | 20196 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
20197 | } |
20198 | ||
20199 | static void | |
20200 | do_neon_sat_abs_neg (void) | |
20201 | { | |
64c350f2 | 20202 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
1a186d29 AV |
20203 | return; |
20204 | ||
20205 | enum neon_shape rs; | |
20206 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
20207 | rs = neon_select_shape (NS_QQ, NS_NULL); | |
20208 | else | |
20209 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
5287ad62 JB |
20210 | struct neon_type_el et = neon_check_type (2, rs, |
20211 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 20212 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
20213 | } |
20214 | ||
20215 | static void | |
20216 | do_neon_pair_long (void) | |
20217 | { | |
037e8744 | 20218 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
20219 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); |
20220 | /* Unsigned is encoded in OP field (bit 7) for these instruction. */ | |
20221 | inst.instruction |= (et.type == NT_unsigned) << 7; | |
037e8744 | 20222 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
20223 | } |
20224 | ||
20225 | static void | |
20226 | do_neon_recip_est (void) | |
20227 | { | |
037e8744 | 20228 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 | 20229 | struct neon_type_el et = neon_check_type (2, rs, |
cc933301 | 20230 | N_EQK | N_FLT, N_F_16_32 | N_U32 | N_KEY); |
5287ad62 | 20231 | inst.instruction |= (et.type == NT_float) << 8; |
037e8744 | 20232 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
20233 | } |
20234 | ||
20235 | static void | |
20236 | do_neon_cls (void) | |
20237 | { | |
64c350f2 | 20238 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
f30ee27c AV |
20239 | return; |
20240 | ||
20241 | enum neon_shape rs; | |
20242 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
20243 | rs = neon_select_shape (NS_QQ, NS_NULL); | |
20244 | else | |
20245 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
20246 | ||
5287ad62 JB |
20247 | struct neon_type_el et = neon_check_type (2, rs, |
20248 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 20249 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
20250 | } |
20251 | ||
20252 | static void | |
20253 | do_neon_clz (void) | |
20254 | { | |
64c350f2 | 20255 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
f30ee27c AV |
20256 | return; |
20257 | ||
20258 | enum neon_shape rs; | |
20259 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
20260 | rs = neon_select_shape (NS_QQ, NS_NULL); | |
20261 | else | |
20262 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
20263 | ||
5287ad62 JB |
20264 | struct neon_type_el et = neon_check_type (2, rs, |
20265 | N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); | |
037e8744 | 20266 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
20267 | } |
20268 | ||
20269 | static void | |
20270 | do_neon_cnt (void) | |
20271 | { | |
037e8744 | 20272 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
20273 | struct neon_type_el et = neon_check_type (2, rs, |
20274 | N_EQK | N_INT, N_8 | N_KEY); | |
037e8744 | 20275 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
20276 | } |
20277 | ||
20278 | static void | |
20279 | do_neon_swp (void) | |
20280 | { | |
037e8744 JB |
20281 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
20282 | neon_two_same (neon_quad (rs), 1, -1); | |
5287ad62 JB |
20283 | } |
20284 | ||
20285 | static void | |
20286 | do_neon_tbl_tbx (void) | |
20287 | { | |
20288 | unsigned listlenbits; | |
dcbf9037 | 20289 | neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); |
5f4273c7 | 20290 | |
5287ad62 JB |
20291 | if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) |
20292 | { | |
dcbf9037 | 20293 | first_error (_("bad list length for table lookup")); |
5287ad62 JB |
20294 | return; |
20295 | } | |
5f4273c7 | 20296 | |
5287ad62 JB |
20297 | listlenbits = inst.operands[1].imm - 1; |
20298 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
20299 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
20300 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
20301 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
20302 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
20303 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
20304 | inst.instruction |= listlenbits << 8; | |
5f4273c7 | 20305 | |
88714cb8 | 20306 | neon_dp_fixup (&inst); |
5287ad62 JB |
20307 | } |
20308 | ||
20309 | static void | |
20310 | do_neon_ldm_stm (void) | |
20311 | { | |
20312 | /* P, U and L bits are part of bitmask. */ | |
20313 | int is_dbmode = (inst.instruction & (1 << 24)) != 0; | |
20314 | unsigned offsetbits = inst.operands[1].imm * 2; | |
20315 | ||
037e8744 JB |
20316 | if (inst.operands[1].issingle) |
20317 | { | |
20318 | do_vfp_nsyn_ldm_stm (is_dbmode); | |
20319 | return; | |
20320 | } | |
20321 | ||
5287ad62 | 20322 | constraint (is_dbmode && !inst.operands[0].writeback, |
477330fc | 20323 | _("writeback (!) must be used for VLDMDB and VSTMDB")); |
5287ad62 JB |
20324 | |
20325 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
477330fc RM |
20326 | _("register list must contain at least 1 and at most 16 " |
20327 | "registers")); | |
5287ad62 JB |
20328 | |
20329 | inst.instruction |= inst.operands[0].reg << 16; | |
20330 | inst.instruction |= inst.operands[0].writeback << 21; | |
20331 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
20332 | inst.instruction |= HI1 (inst.operands[1].reg) << 22; | |
20333 | ||
20334 | inst.instruction |= offsetbits; | |
5f4273c7 | 20335 | |
037e8744 | 20336 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
20337 | } |
20338 | ||
20339 | static void | |
20340 | do_neon_ldr_str (void) | |
20341 | { | |
5287ad62 | 20342 | int is_ldr = (inst.instruction & (1 << 20)) != 0; |
5f4273c7 | 20343 | |
6844b2c2 MGD |
20344 | /* Use of PC in vstr in ARM mode is deprecated in ARMv7. |
20345 | And is UNPREDICTABLE in thumb mode. */ | |
fa94de6b | 20346 | if (!is_ldr |
6844b2c2 | 20347 | && inst.operands[1].reg == REG_PC |
ba86b375 | 20348 | && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode)) |
6844b2c2 | 20349 | { |
94dcf8bf | 20350 | if (thumb_mode) |
6844b2c2 | 20351 | inst.error = _("Use of PC here is UNPREDICTABLE"); |
94dcf8bf | 20352 | else if (warn_on_deprecated) |
5c3696f8 | 20353 | as_tsktsk (_("Use of PC here is deprecated")); |
6844b2c2 MGD |
20354 | } |
20355 | ||
037e8744 JB |
20356 | if (inst.operands[0].issingle) |
20357 | { | |
cd2f129f | 20358 | if (is_ldr) |
477330fc | 20359 | do_vfp_nsyn_opcode ("flds"); |
cd2f129f | 20360 | else |
477330fc | 20361 | do_vfp_nsyn_opcode ("fsts"); |
9db2f6b4 RL |
20362 | |
20363 | /* ARMv8.2 vldr.16/vstr.16 instruction. */ | |
20364 | if (inst.vectype.el[0].size == 16) | |
20365 | do_scalar_fp16_v82_encode (); | |
5287ad62 JB |
20366 | } |
20367 | else | |
5287ad62 | 20368 | { |
cd2f129f | 20369 | if (is_ldr) |
477330fc | 20370 | do_vfp_nsyn_opcode ("fldd"); |
5287ad62 | 20371 | else |
477330fc | 20372 | do_vfp_nsyn_opcode ("fstd"); |
5287ad62 | 20373 | } |
5287ad62 JB |
20374 | } |
20375 | ||
32c36c3c AV |
20376 | static void |
20377 | do_t_vldr_vstr_sysreg (void) | |
20378 | { | |
20379 | int fp_vldr_bitno = 20, sysreg_vldr_bitno = 20; | |
20380 | bfd_boolean is_vldr = ((inst.instruction & (1 << fp_vldr_bitno)) != 0); | |
20381 | ||
20382 | /* Use of PC is UNPREDICTABLE. */ | |
20383 | if (inst.operands[1].reg == REG_PC) | |
20384 | inst.error = _("Use of PC here is UNPREDICTABLE"); | |
20385 | ||
20386 | if (inst.operands[1].immisreg) | |
20387 | inst.error = _("instruction does not accept register index"); | |
20388 | ||
20389 | if (!inst.operands[1].isreg) | |
20390 | inst.error = _("instruction does not accept PC-relative addressing"); | |
20391 | ||
20392 | if (abs (inst.operands[1].imm) >= (1 << 7)) | |
20393 | inst.error = _("immediate value out of range"); | |
20394 | ||
20395 | inst.instruction = 0xec000f80; | |
20396 | if (is_vldr) | |
20397 | inst.instruction |= 1 << sysreg_vldr_bitno; | |
20398 | encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM); | |
20399 | inst.instruction |= (inst.operands[0].imm & 0x7) << 13; | |
20400 | inst.instruction |= (inst.operands[0].imm & 0x8) << 19; | |
20401 | } | |
20402 | ||
20403 | static void | |
20404 | do_vldr_vstr (void) | |
20405 | { | |
20406 | bfd_boolean sysreg_op = !inst.operands[0].isreg; | |
20407 | ||
20408 | /* VLDR/VSTR (System Register). */ | |
20409 | if (sysreg_op) | |
20410 | { | |
20411 | if (!mark_feature_used (&arm_ext_v8_1m_main)) | |
20412 | as_bad (_("Instruction not permitted on this architecture")); | |
20413 | ||
20414 | do_t_vldr_vstr_sysreg (); | |
20415 | } | |
20416 | /* VLDR/VSTR. */ | |
20417 | else | |
20418 | { | |
20419 | if (!mark_feature_used (&fpu_vfp_ext_v1xd)) | |
20420 | as_bad (_("Instruction not permitted on this architecture")); | |
20421 | do_neon_ldr_str (); | |
20422 | } | |
20423 | } | |
20424 | ||
5287ad62 JB |
20425 | /* "interleave" version also handles non-interleaving register VLD1/VST1 |
20426 | instructions. */ | |
20427 | ||
20428 | static void | |
20429 | do_neon_ld_st_interleave (void) | |
20430 | { | |
037e8744 | 20431 | struct neon_type_el et = neon_check_type (1, NS_NULL, |
477330fc | 20432 | N_8 | N_16 | N_32 | N_64); |
5287ad62 JB |
20433 | unsigned alignbits = 0; |
20434 | unsigned idx; | |
20435 | /* The bits in this table go: | |
20436 | 0: register stride of one (0) or two (1) | |
20437 | 1,2: register list length, minus one (1, 2, 3, 4). | |
20438 | 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). | |
20439 | We use -1 for invalid entries. */ | |
20440 | const int typetable[] = | |
20441 | { | |
20442 | 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ | |
20443 | -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ | |
20444 | -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ | |
20445 | -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ | |
20446 | }; | |
20447 | int typebits; | |
20448 | ||
dcbf9037 JB |
20449 | if (et.type == NT_invtype) |
20450 | return; | |
20451 | ||
5287ad62 JB |
20452 | if (inst.operands[1].immisalign) |
20453 | switch (inst.operands[1].imm >> 8) | |
20454 | { | |
20455 | case 64: alignbits = 1; break; | |
20456 | case 128: | |
477330fc | 20457 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2 |
e23c0ad8 | 20458 | && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
477330fc RM |
20459 | goto bad_alignment; |
20460 | alignbits = 2; | |
20461 | break; | |
5287ad62 | 20462 | case 256: |
477330fc RM |
20463 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
20464 | goto bad_alignment; | |
20465 | alignbits = 3; | |
20466 | break; | |
5287ad62 JB |
20467 | default: |
20468 | bad_alignment: | |
477330fc RM |
20469 | first_error (_("bad alignment")); |
20470 | return; | |
5287ad62 JB |
20471 | } |
20472 | ||
20473 | inst.instruction |= alignbits << 4; | |
20474 | inst.instruction |= neon_logbits (et.size) << 6; | |
20475 | ||
20476 | /* Bits [4:6] of the immediate in a list specifier encode register stride | |
20477 | (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of | |
20478 | VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look | |
20479 | up the right value for "type" in a table based on this value and the given | |
20480 | list style, then stick it back. */ | |
20481 | idx = ((inst.operands[0].imm >> 4) & 7) | |
477330fc | 20482 | | (((inst.instruction >> 8) & 3) << 3); |
5287ad62 JB |
20483 | |
20484 | typebits = typetable[idx]; | |
5f4273c7 | 20485 | |
5287ad62 | 20486 | constraint (typebits == -1, _("bad list type for instruction")); |
1d50d57c | 20487 | constraint (((inst.instruction >> 8) & 3) && et.size == 64, |
35c228db | 20488 | BAD_EL_TYPE); |
5287ad62 JB |
20489 | |
20490 | inst.instruction &= ~0xf00; | |
20491 | inst.instruction |= typebits << 8; | |
20492 | } | |
20493 | ||
20494 | /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. | |
20495 | *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 | |
20496 | otherwise. The variable arguments are a list of pairs of legal (size, align) | |
20497 | values, terminated with -1. */ | |
20498 | ||
20499 | static int | |
aa8a0863 | 20500 | neon_alignment_bit (int size, int align, int *do_alignment, ...) |
5287ad62 JB |
20501 | { |
20502 | va_list ap; | |
20503 | int result = FAIL, thissize, thisalign; | |
5f4273c7 | 20504 | |
5287ad62 JB |
20505 | if (!inst.operands[1].immisalign) |
20506 | { | |
aa8a0863 | 20507 | *do_alignment = 0; |
5287ad62 JB |
20508 | return SUCCESS; |
20509 | } | |
5f4273c7 | 20510 | |
aa8a0863 | 20511 | va_start (ap, do_alignment); |
5287ad62 JB |
20512 | |
20513 | do | |
20514 | { | |
20515 | thissize = va_arg (ap, int); | |
20516 | if (thissize == -1) | |
477330fc | 20517 | break; |
5287ad62 JB |
20518 | thisalign = va_arg (ap, int); |
20519 | ||
20520 | if (size == thissize && align == thisalign) | |
477330fc | 20521 | result = SUCCESS; |
5287ad62 JB |
20522 | } |
20523 | while (result != SUCCESS); | |
20524 | ||
20525 | va_end (ap); | |
20526 | ||
20527 | if (result == SUCCESS) | |
aa8a0863 | 20528 | *do_alignment = 1; |
5287ad62 | 20529 | else |
dcbf9037 | 20530 | first_error (_("unsupported alignment for instruction")); |
5f4273c7 | 20531 | |
5287ad62 JB |
20532 | return result; |
20533 | } | |
20534 | ||
20535 | static void | |
20536 | do_neon_ld_st_lane (void) | |
20537 | { | |
037e8744 | 20538 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
aa8a0863 | 20539 | int align_good, do_alignment = 0; |
5287ad62 JB |
20540 | int logsize = neon_logbits (et.size); |
20541 | int align = inst.operands[1].imm >> 8; | |
20542 | int n = (inst.instruction >> 8) & 3; | |
20543 | int max_el = 64 / et.size; | |
5f4273c7 | 20544 | |
dcbf9037 JB |
20545 | if (et.type == NT_invtype) |
20546 | return; | |
5f4273c7 | 20547 | |
5287ad62 | 20548 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, |
477330fc | 20549 | _("bad list length")); |
5287ad62 | 20550 | constraint (NEON_LANE (inst.operands[0].imm) >= max_el, |
477330fc | 20551 | _("scalar index out of range")); |
5287ad62 | 20552 | constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 |
477330fc RM |
20553 | && et.size == 8, |
20554 | _("stride of 2 unavailable when element size is 8")); | |
5f4273c7 | 20555 | |
5287ad62 JB |
20556 | switch (n) |
20557 | { | |
20558 | case 0: /* VLD1 / VST1. */ | |
aa8a0863 | 20559 | align_good = neon_alignment_bit (et.size, align, &do_alignment, 16, 16, |
477330fc | 20560 | 32, 32, -1); |
5287ad62 | 20561 | if (align_good == FAIL) |
477330fc | 20562 | return; |
aa8a0863 | 20563 | if (do_alignment) |
477330fc RM |
20564 | { |
20565 | unsigned alignbits = 0; | |
20566 | switch (et.size) | |
20567 | { | |
20568 | case 16: alignbits = 0x1; break; | |
20569 | case 32: alignbits = 0x3; break; | |
20570 | default: ; | |
20571 | } | |
20572 | inst.instruction |= alignbits << 4; | |
20573 | } | |
5287ad62 JB |
20574 | break; |
20575 | ||
20576 | case 1: /* VLD2 / VST2. */ | |
aa8a0863 TS |
20577 | align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 16, |
20578 | 16, 32, 32, 64, -1); | |
5287ad62 | 20579 | if (align_good == FAIL) |
477330fc | 20580 | return; |
aa8a0863 | 20581 | if (do_alignment) |
477330fc | 20582 | inst.instruction |= 1 << 4; |
5287ad62 JB |
20583 | break; |
20584 | ||
20585 | case 2: /* VLD3 / VST3. */ | |
20586 | constraint (inst.operands[1].immisalign, | |
477330fc | 20587 | _("can't use alignment with this instruction")); |
5287ad62 JB |
20588 | break; |
20589 | ||
20590 | case 3: /* VLD4 / VST4. */ | |
aa8a0863 | 20591 | align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32, |
477330fc | 20592 | 16, 64, 32, 64, 32, 128, -1); |
5287ad62 | 20593 | if (align_good == FAIL) |
477330fc | 20594 | return; |
aa8a0863 | 20595 | if (do_alignment) |
477330fc RM |
20596 | { |
20597 | unsigned alignbits = 0; | |
20598 | switch (et.size) | |
20599 | { | |
20600 | case 8: alignbits = 0x1; break; | |
20601 | case 16: alignbits = 0x1; break; | |
20602 | case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; | |
20603 | default: ; | |
20604 | } | |
20605 | inst.instruction |= alignbits << 4; | |
20606 | } | |
5287ad62 JB |
20607 | break; |
20608 | ||
20609 | default: ; | |
20610 | } | |
20611 | ||
20612 | /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ | |
20613 | if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
20614 | inst.instruction |= 1 << (4 + logsize); | |
5f4273c7 | 20615 | |
5287ad62 JB |
20616 | inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); |
20617 | inst.instruction |= logsize << 10; | |
20618 | } | |
20619 | ||
20620 | /* Encode single n-element structure to all lanes VLD<n> instructions. */ | |
20621 | ||
20622 | static void | |
20623 | do_neon_ld_dup (void) | |
20624 | { | |
037e8744 | 20625 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
aa8a0863 | 20626 | int align_good, do_alignment = 0; |
5287ad62 | 20627 | |
dcbf9037 JB |
20628 | if (et.type == NT_invtype) |
20629 | return; | |
20630 | ||
5287ad62 JB |
20631 | switch ((inst.instruction >> 8) & 3) |
20632 | { | |
20633 | case 0: /* VLD1. */ | |
9c2799c2 | 20634 | gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); |
5287ad62 | 20635 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, |
aa8a0863 | 20636 | &do_alignment, 16, 16, 32, 32, -1); |
5287ad62 | 20637 | if (align_good == FAIL) |
477330fc | 20638 | return; |
5287ad62 | 20639 | switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) |
477330fc RM |
20640 | { |
20641 | case 1: break; | |
20642 | case 2: inst.instruction |= 1 << 5; break; | |
20643 | default: first_error (_("bad list length")); return; | |
20644 | } | |
5287ad62 JB |
20645 | inst.instruction |= neon_logbits (et.size) << 6; |
20646 | break; | |
20647 | ||
20648 | case 1: /* VLD2. */ | |
20649 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, | |
aa8a0863 TS |
20650 | &do_alignment, 8, 16, 16, 32, 32, 64, |
20651 | -1); | |
5287ad62 | 20652 | if (align_good == FAIL) |
477330fc | 20653 | return; |
5287ad62 | 20654 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, |
477330fc | 20655 | _("bad list length")); |
5287ad62 | 20656 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) |
477330fc | 20657 | inst.instruction |= 1 << 5; |
5287ad62 JB |
20658 | inst.instruction |= neon_logbits (et.size) << 6; |
20659 | break; | |
20660 | ||
20661 | case 2: /* VLD3. */ | |
20662 | constraint (inst.operands[1].immisalign, | |
477330fc | 20663 | _("can't use alignment with this instruction")); |
5287ad62 | 20664 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, |
477330fc | 20665 | _("bad list length")); |
5287ad62 | 20666 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) |
477330fc | 20667 | inst.instruction |= 1 << 5; |
5287ad62 JB |
20668 | inst.instruction |= neon_logbits (et.size) << 6; |
20669 | break; | |
20670 | ||
20671 | case 3: /* VLD4. */ | |
20672 | { | |
477330fc | 20673 | int align = inst.operands[1].imm >> 8; |
aa8a0863 | 20674 | align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32, |
477330fc RM |
20675 | 16, 64, 32, 64, 32, 128, -1); |
20676 | if (align_good == FAIL) | |
20677 | return; | |
20678 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, | |
20679 | _("bad list length")); | |
20680 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
20681 | inst.instruction |= 1 << 5; | |
20682 | if (et.size == 32 && align == 128) | |
20683 | inst.instruction |= 0x3 << 6; | |
20684 | else | |
20685 | inst.instruction |= neon_logbits (et.size) << 6; | |
5287ad62 JB |
20686 | } |
20687 | break; | |
20688 | ||
20689 | default: ; | |
20690 | } | |
20691 | ||
aa8a0863 | 20692 | inst.instruction |= do_alignment << 4; |
5287ad62 JB |
20693 | } |
20694 | ||
20695 | /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those | |
20696 | apart from bits [11:4]. */ | |
20697 | ||
20698 | static void | |
20699 | do_neon_ldx_stx (void) | |
20700 | { | |
b1a769ed DG |
20701 | if (inst.operands[1].isreg) |
20702 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); | |
20703 | ||
5287ad62 JB |
20704 | switch (NEON_LANE (inst.operands[0].imm)) |
20705 | { | |
20706 | case NEON_INTERLEAVE_LANES: | |
88714cb8 | 20707 | NEON_ENCODE (INTERLV, inst); |
5287ad62 JB |
20708 | do_neon_ld_st_interleave (); |
20709 | break; | |
5f4273c7 | 20710 | |
5287ad62 | 20711 | case NEON_ALL_LANES: |
88714cb8 | 20712 | NEON_ENCODE (DUP, inst); |
2d51fb74 JB |
20713 | if (inst.instruction == N_INV) |
20714 | { | |
20715 | first_error ("only loads support such operands"); | |
20716 | break; | |
20717 | } | |
5287ad62 JB |
20718 | do_neon_ld_dup (); |
20719 | break; | |
5f4273c7 | 20720 | |
5287ad62 | 20721 | default: |
88714cb8 | 20722 | NEON_ENCODE (LANE, inst); |
5287ad62 JB |
20723 | do_neon_ld_st_lane (); |
20724 | } | |
20725 | ||
20726 | /* L bit comes from bit mask. */ | |
20727 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
20728 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
20729 | inst.instruction |= inst.operands[1].reg << 16; | |
5f4273c7 | 20730 | |
5287ad62 JB |
20731 | if (inst.operands[1].postind) |
20732 | { | |
20733 | int postreg = inst.operands[1].imm & 0xf; | |
20734 | constraint (!inst.operands[1].immisreg, | |
477330fc | 20735 | _("post-index must be a register")); |
5287ad62 | 20736 | constraint (postreg == 0xd || postreg == 0xf, |
477330fc | 20737 | _("bad register for post-index")); |
5287ad62 JB |
20738 | inst.instruction |= postreg; |
20739 | } | |
4f2374c7 | 20740 | else |
5287ad62 | 20741 | { |
4f2374c7 | 20742 | constraint (inst.operands[1].immisreg, BAD_ADDR_MODE); |
e2b0ab59 AV |
20743 | constraint (inst.relocs[0].exp.X_op != O_constant |
20744 | || inst.relocs[0].exp.X_add_number != 0, | |
4f2374c7 WN |
20745 | BAD_ADDR_MODE); |
20746 | ||
20747 | if (inst.operands[1].writeback) | |
20748 | { | |
20749 | inst.instruction |= 0xd; | |
20750 | } | |
20751 | else | |
20752 | inst.instruction |= 0xf; | |
5287ad62 | 20753 | } |
5f4273c7 | 20754 | |
5287ad62 JB |
20755 | if (thumb_mode) |
20756 | inst.instruction |= 0xf9000000; | |
20757 | else | |
20758 | inst.instruction |= 0xf4000000; | |
20759 | } | |
33399f07 MGD |
20760 | |
20761 | /* FP v8. */ | |
20762 | static void | |
20763 | do_vfp_nsyn_fpv8 (enum neon_shape rs) | |
20764 | { | |
a715796b TG |
20765 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
20766 | D register operands. */ | |
20767 | if (neon_shape_class[rs] == SC_DOUBLE) | |
20768 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
20769 | _(BAD_FPU)); | |
20770 | ||
33399f07 MGD |
20771 | NEON_ENCODE (FPV8, inst); |
20772 | ||
9db2f6b4 RL |
20773 | if (rs == NS_FFF || rs == NS_HHH) |
20774 | { | |
20775 | do_vfp_sp_dyadic (); | |
20776 | ||
20777 | /* ARMv8.2 fp16 instruction. */ | |
20778 | if (rs == NS_HHH) | |
20779 | do_scalar_fp16_v82_encode (); | |
20780 | } | |
33399f07 MGD |
20781 | else |
20782 | do_vfp_dp_rd_rn_rm (); | |
20783 | ||
20784 | if (rs == NS_DDD) | |
20785 | inst.instruction |= 0x100; | |
20786 | ||
20787 | inst.instruction |= 0xf0000000; | |
20788 | } | |
20789 | ||
20790 | static void | |
20791 | do_vsel (void) | |
20792 | { | |
5ee91343 | 20793 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
33399f07 MGD |
20794 | |
20795 | if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS) | |
20796 | first_error (_("invalid instruction shape")); | |
20797 | } | |
20798 | ||
73924fbc MGD |
20799 | static void |
20800 | do_vmaxnm (void) | |
20801 | { | |
935295b5 AV |
20802 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
20803 | set_pred_insn_type (OUTSIDE_PRED_INSN); | |
73924fbc MGD |
20804 | |
20805 | if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS) | |
20806 | return; | |
20807 | ||
64c350f2 | 20808 | if (!check_simd_pred_availability (TRUE, NEON_CHECK_CC | NEON_CHECK_ARCH8)) |
73924fbc MGD |
20809 | return; |
20810 | ||
cc933301 | 20811 | neon_dyadic_misc (NT_untyped, N_F_16_32, 0); |
73924fbc MGD |
20812 | } |
20813 | ||
30bdf752 MGD |
20814 | static void |
20815 | do_vrint_1 (enum neon_cvt_mode mode) | |
20816 | { | |
9db2f6b4 | 20817 | enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_QQ, NS_NULL); |
30bdf752 MGD |
20818 | struct neon_type_el et; |
20819 | ||
20820 | if (rs == NS_NULL) | |
20821 | return; | |
20822 | ||
a715796b TG |
20823 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
20824 | D register operands. */ | |
20825 | if (neon_shape_class[rs] == SC_DOUBLE) | |
20826 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
20827 | _(BAD_FPU)); | |
20828 | ||
9db2f6b4 RL |
20829 | et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY |
20830 | | N_VFP); | |
30bdf752 MGD |
20831 | if (et.type != NT_invtype) |
20832 | { | |
20833 | /* VFP encodings. */ | |
20834 | if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n | |
20835 | || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m) | |
5ee91343 | 20836 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
30bdf752 MGD |
20837 | |
20838 | NEON_ENCODE (FPV8, inst); | |
9db2f6b4 | 20839 | if (rs == NS_FF || rs == NS_HH) |
30bdf752 MGD |
20840 | do_vfp_sp_monadic (); |
20841 | else | |
20842 | do_vfp_dp_rd_rm (); | |
20843 | ||
20844 | switch (mode) | |
20845 | { | |
20846 | case neon_cvt_mode_r: inst.instruction |= 0x00000000; break; | |
20847 | case neon_cvt_mode_z: inst.instruction |= 0x00000080; break; | |
20848 | case neon_cvt_mode_x: inst.instruction |= 0x00010000; break; | |
20849 | case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break; | |
20850 | case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break; | |
20851 | case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break; | |
20852 | case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break; | |
20853 | default: abort (); | |
20854 | } | |
20855 | ||
20856 | inst.instruction |= (rs == NS_DD) << 8; | |
20857 | do_vfp_cond_or_thumb (); | |
9db2f6b4 RL |
20858 | |
20859 | /* ARMv8.2 fp16 vrint instruction. */ | |
20860 | if (rs == NS_HH) | |
20861 | do_scalar_fp16_v82_encode (); | |
30bdf752 MGD |
20862 | } |
20863 | else | |
20864 | { | |
20865 | /* Neon encodings (or something broken...). */ | |
20866 | inst.error = NULL; | |
cc933301 | 20867 | et = neon_check_type (2, rs, N_EQK, N_F_16_32 | N_KEY); |
30bdf752 MGD |
20868 | |
20869 | if (et.type == NT_invtype) | |
20870 | return; | |
20871 | ||
64c350f2 AV |
20872 | if (!check_simd_pred_availability (TRUE, |
20873 | NEON_CHECK_CC | NEON_CHECK_ARCH8)) | |
30bdf752 MGD |
20874 | return; |
20875 | ||
a710b305 AV |
20876 | NEON_ENCODE (FLOAT, inst); |
20877 | ||
30bdf752 MGD |
20878 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
20879 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
20880 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
20881 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
20882 | inst.instruction |= neon_quad (rs) << 6; | |
cc933301 JW |
20883 | /* Mask off the original size bits and reencode them. */ |
20884 | inst.instruction = ((inst.instruction & 0xfff3ffff) | |
20885 | | neon_logbits (et.size) << 18); | |
20886 | ||
30bdf752 MGD |
20887 | switch (mode) |
20888 | { | |
20889 | case neon_cvt_mode_z: inst.instruction |= 3 << 7; break; | |
20890 | case neon_cvt_mode_x: inst.instruction |= 1 << 7; break; | |
20891 | case neon_cvt_mode_a: inst.instruction |= 2 << 7; break; | |
20892 | case neon_cvt_mode_n: inst.instruction |= 0 << 7; break; | |
20893 | case neon_cvt_mode_p: inst.instruction |= 7 << 7; break; | |
20894 | case neon_cvt_mode_m: inst.instruction |= 5 << 7; break; | |
20895 | case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break; | |
20896 | default: abort (); | |
20897 | } | |
20898 | ||
20899 | if (thumb_mode) | |
20900 | inst.instruction |= 0xfc000000; | |
20901 | else | |
20902 | inst.instruction |= 0xf0000000; | |
20903 | } | |
20904 | } | |
20905 | ||
20906 | static void | |
20907 | do_vrintx (void) | |
20908 | { | |
20909 | do_vrint_1 (neon_cvt_mode_x); | |
20910 | } | |
20911 | ||
20912 | static void | |
20913 | do_vrintz (void) | |
20914 | { | |
20915 | do_vrint_1 (neon_cvt_mode_z); | |
20916 | } | |
20917 | ||
20918 | static void | |
20919 | do_vrintr (void) | |
20920 | { | |
20921 | do_vrint_1 (neon_cvt_mode_r); | |
20922 | } | |
20923 | ||
20924 | static void | |
20925 | do_vrinta (void) | |
20926 | { | |
20927 | do_vrint_1 (neon_cvt_mode_a); | |
20928 | } | |
20929 | ||
20930 | static void | |
20931 | do_vrintn (void) | |
20932 | { | |
20933 | do_vrint_1 (neon_cvt_mode_n); | |
20934 | } | |
20935 | ||
20936 | static void | |
20937 | do_vrintp (void) | |
20938 | { | |
20939 | do_vrint_1 (neon_cvt_mode_p); | |
20940 | } | |
20941 | ||
20942 | static void | |
20943 | do_vrintm (void) | |
20944 | { | |
20945 | do_vrint_1 (neon_cvt_mode_m); | |
20946 | } | |
20947 | ||
c28eeff2 SN |
20948 | static unsigned |
20949 | neon_scalar_for_vcmla (unsigned opnd, unsigned elsize) | |
20950 | { | |
20951 | unsigned regno = NEON_SCALAR_REG (opnd); | |
20952 | unsigned elno = NEON_SCALAR_INDEX (opnd); | |
20953 | ||
20954 | if (elsize == 16 && elno < 2 && regno < 16) | |
20955 | return regno | (elno << 4); | |
20956 | else if (elsize == 32 && elno == 0) | |
20957 | return regno; | |
20958 | ||
20959 | first_error (_("scalar out of range")); | |
20960 | return 0; | |
20961 | } | |
20962 | ||
20963 | static void | |
20964 | do_vcmla (void) | |
20965 | { | |
5d281bf0 AV |
20966 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) |
20967 | && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8) | |
20968 | || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU)); | |
e2b0ab59 AV |
20969 | constraint (inst.relocs[0].exp.X_op != O_constant, |
20970 | _("expression too complex")); | |
20971 | unsigned rot = inst.relocs[0].exp.X_add_number; | |
c28eeff2 SN |
20972 | constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270, |
20973 | _("immediate out of range")); | |
20974 | rot /= 90; | |
5d281bf0 | 20975 | |
64c350f2 AV |
20976 | if (!check_simd_pred_availability (TRUE, |
20977 | NEON_CHECK_ARCH8 | NEON_CHECK_CC)) | |
5d281bf0 AV |
20978 | return; |
20979 | ||
c28eeff2 SN |
20980 | if (inst.operands[2].isscalar) |
20981 | { | |
5d281bf0 AV |
20982 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) |
20983 | first_error (_("invalid instruction shape")); | |
c28eeff2 SN |
20984 | enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL); |
20985 | unsigned size = neon_check_type (3, rs, N_EQK, N_EQK, | |
20986 | N_KEY | N_F16 | N_F32).size; | |
20987 | unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size); | |
20988 | inst.is_neon = 1; | |
20989 | inst.instruction = 0xfe000800; | |
20990 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
20991 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
20992 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
20993 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
20994 | inst.instruction |= LOW4 (m); | |
20995 | inst.instruction |= HI1 (m) << 5; | |
20996 | inst.instruction |= neon_quad (rs) << 6; | |
20997 | inst.instruction |= rot << 20; | |
20998 | inst.instruction |= (size == 32) << 23; | |
20999 | } | |
21000 | else | |
21001 | { | |
5d281bf0 AV |
21002 | enum neon_shape rs; |
21003 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) | |
21004 | rs = neon_select_shape (NS_QQQI, NS_NULL); | |
21005 | else | |
21006 | rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); | |
21007 | ||
c28eeff2 SN |
21008 | unsigned size = neon_check_type (3, rs, N_EQK, N_EQK, |
21009 | N_KEY | N_F16 | N_F32).size; | |
5d281bf0 AV |
21010 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) && size == 32 |
21011 | && (inst.operands[0].reg == inst.operands[1].reg | |
21012 | || inst.operands[0].reg == inst.operands[2].reg)) | |
21013 | as_tsktsk (BAD_MVE_SRCDEST); | |
21014 | ||
c28eeff2 SN |
21015 | neon_three_same (neon_quad (rs), 0, -1); |
21016 | inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */ | |
21017 | inst.instruction |= 0xfc200800; | |
21018 | inst.instruction |= rot << 23; | |
21019 | inst.instruction |= (size == 32) << 20; | |
21020 | } | |
21021 | } | |
21022 | ||
21023 | static void | |
21024 | do_vcadd (void) | |
21025 | { | |
5d281bf0 AV |
21026 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) |
21027 | && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8) | |
21028 | || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU)); | |
e2b0ab59 AV |
21029 | constraint (inst.relocs[0].exp.X_op != O_constant, |
21030 | _("expression too complex")); | |
5d281bf0 | 21031 | |
e2b0ab59 | 21032 | unsigned rot = inst.relocs[0].exp.X_add_number; |
c28eeff2 | 21033 | constraint (rot != 90 && rot != 270, _("immediate out of range")); |
5d281bf0 AV |
21034 | enum neon_shape rs; |
21035 | struct neon_type_el et; | |
21036 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
21037 | { | |
21038 | rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); | |
21039 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32); | |
21040 | } | |
21041 | else | |
21042 | { | |
21043 | rs = neon_select_shape (NS_QQQI, NS_NULL); | |
21044 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32 | N_I8 | |
21045 | | N_I16 | N_I32); | |
21046 | if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg) | |
21047 | as_tsktsk (_("Warning: 32-bit element size and same first and third " | |
21048 | "operand makes instruction UNPREDICTABLE")); | |
21049 | } | |
21050 | ||
21051 | if (et.type == NT_invtype) | |
21052 | return; | |
21053 | ||
64c350f2 AV |
21054 | if (!check_simd_pred_availability (et.type == NT_float, |
21055 | NEON_CHECK_ARCH8 | NEON_CHECK_CC)) | |
5d281bf0 AV |
21056 | return; |
21057 | ||
21058 | if (et.type == NT_float) | |
21059 | { | |
21060 | neon_three_same (neon_quad (rs), 0, -1); | |
21061 | inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */ | |
21062 | inst.instruction |= 0xfc800800; | |
21063 | inst.instruction |= (rot == 270) << 24; | |
21064 | inst.instruction |= (et.size == 32) << 20; | |
21065 | } | |
21066 | else | |
21067 | { | |
21068 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); | |
21069 | inst.instruction = 0xfe000f00; | |
21070 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
21071 | inst.instruction |= neon_logbits (et.size) << 20; | |
21072 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
21073 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
21074 | inst.instruction |= (rot == 270) << 12; | |
21075 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
21076 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
21077 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
21078 | inst.is_neon = 1; | |
21079 | } | |
c28eeff2 SN |
21080 | } |
21081 | ||
c604a79a JW |
21082 | /* Dot Product instructions encoding support. */ |
21083 | ||
21084 | static void | |
21085 | do_neon_dotproduct (int unsigned_p) | |
21086 | { | |
21087 | enum neon_shape rs; | |
21088 | unsigned scalar_oprd2 = 0; | |
21089 | int high8; | |
21090 | ||
21091 | if (inst.cond != COND_ALWAYS) | |
21092 | as_warn (_("Dot Product instructions cannot be conditional, the behaviour " | |
21093 | "is UNPREDICTABLE")); | |
21094 | ||
21095 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8), | |
21096 | _(BAD_FPU)); | |
21097 | ||
21098 | /* Dot Product instructions are in three-same D/Q register format or the third | |
21099 | operand can be a scalar index register. */ | |
21100 | if (inst.operands[2].isscalar) | |
21101 | { | |
21102 | scalar_oprd2 = neon_scalar_for_mul (inst.operands[2].reg, 32); | |
21103 | high8 = 0xfe000000; | |
21104 | rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); | |
21105 | } | |
21106 | else | |
21107 | { | |
21108 | high8 = 0xfc000000; | |
21109 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
21110 | } | |
21111 | ||
21112 | if (unsigned_p) | |
21113 | neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_U8); | |
21114 | else | |
21115 | neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_S8); | |
21116 | ||
21117 | /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot | |
21118 | Product instruction, so we pass 0 as the "ubit" parameter. And the | |
21119 | "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */ | |
21120 | neon_three_same (neon_quad (rs), 0, 32); | |
21121 | ||
21122 | /* Undo neon_dp_fixup. Dot Product instructions are using a slightly | |
21123 | different NEON three-same encoding. */ | |
21124 | inst.instruction &= 0x00ffffff; | |
21125 | inst.instruction |= high8; | |
21126 | /* Encode 'U' bit which indicates signedness. */ | |
21127 | inst.instruction |= (unsigned_p ? 1 : 0) << 4; | |
21128 | /* Re-encode operand2 if it's indexed scalar operand. What has been encoded | |
21129 | from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not | |
21130 | the instruction encoding. */ | |
21131 | if (inst.operands[2].isscalar) | |
21132 | { | |
21133 | inst.instruction &= 0xffffffd0; | |
21134 | inst.instruction |= LOW4 (scalar_oprd2); | |
21135 | inst.instruction |= HI1 (scalar_oprd2) << 5; | |
21136 | } | |
21137 | } | |
21138 | ||
21139 | /* Dot Product instructions for signed integer. */ | |
21140 | ||
21141 | static void | |
21142 | do_neon_dotproduct_s (void) | |
21143 | { | |
21144 | return do_neon_dotproduct (0); | |
21145 | } | |
21146 | ||
21147 | /* Dot Product instructions for unsigned integer. */ | |
21148 | ||
21149 | static void | |
21150 | do_neon_dotproduct_u (void) | |
21151 | { | |
21152 | return do_neon_dotproduct (1); | |
21153 | } | |
21154 | ||
91ff7894 MGD |
21155 | /* Crypto v1 instructions. */ |
21156 | static void | |
21157 | do_crypto_2op_1 (unsigned elttype, int op) | |
21158 | { | |
5ee91343 | 21159 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
91ff7894 MGD |
21160 | |
21161 | if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type | |
21162 | == NT_invtype) | |
21163 | return; | |
21164 | ||
21165 | inst.error = NULL; | |
21166 | ||
21167 | NEON_ENCODE (INTEGER, inst); | |
21168 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
21169 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
21170 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
21171 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
21172 | if (op != -1) | |
21173 | inst.instruction |= op << 6; | |
21174 | ||
21175 | if (thumb_mode) | |
21176 | inst.instruction |= 0xfc000000; | |
21177 | else | |
21178 | inst.instruction |= 0xf0000000; | |
21179 | } | |
21180 | ||
48adcd8e MGD |
21181 | static void |
21182 | do_crypto_3op_1 (int u, int op) | |
21183 | { | |
5ee91343 | 21184 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
48adcd8e MGD |
21185 | |
21186 | if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT, | |
21187 | N_32 | N_UNT | N_KEY).type == NT_invtype) | |
21188 | return; | |
21189 | ||
21190 | inst.error = NULL; | |
21191 | ||
21192 | NEON_ENCODE (INTEGER, inst); | |
21193 | neon_three_same (1, u, 8 << op); | |
21194 | } | |
21195 | ||
91ff7894 MGD |
21196 | static void |
21197 | do_aese (void) | |
21198 | { | |
21199 | do_crypto_2op_1 (N_8, 0); | |
21200 | } | |
21201 | ||
21202 | static void | |
21203 | do_aesd (void) | |
21204 | { | |
21205 | do_crypto_2op_1 (N_8, 1); | |
21206 | } | |
21207 | ||
21208 | static void | |
21209 | do_aesmc (void) | |
21210 | { | |
21211 | do_crypto_2op_1 (N_8, 2); | |
21212 | } | |
21213 | ||
21214 | static void | |
21215 | do_aesimc (void) | |
21216 | { | |
21217 | do_crypto_2op_1 (N_8, 3); | |
21218 | } | |
21219 | ||
48adcd8e MGD |
21220 | static void |
21221 | do_sha1c (void) | |
21222 | { | |
21223 | do_crypto_3op_1 (0, 0); | |
21224 | } | |
21225 | ||
21226 | static void | |
21227 | do_sha1p (void) | |
21228 | { | |
21229 | do_crypto_3op_1 (0, 1); | |
21230 | } | |
21231 | ||
21232 | static void | |
21233 | do_sha1m (void) | |
21234 | { | |
21235 | do_crypto_3op_1 (0, 2); | |
21236 | } | |
21237 | ||
21238 | static void | |
21239 | do_sha1su0 (void) | |
21240 | { | |
21241 | do_crypto_3op_1 (0, 3); | |
21242 | } | |
91ff7894 | 21243 | |
48adcd8e MGD |
21244 | static void |
21245 | do_sha256h (void) | |
21246 | { | |
21247 | do_crypto_3op_1 (1, 0); | |
21248 | } | |
21249 | ||
21250 | static void | |
21251 | do_sha256h2 (void) | |
21252 | { | |
21253 | do_crypto_3op_1 (1, 1); | |
21254 | } | |
21255 | ||
21256 | static void | |
21257 | do_sha256su1 (void) | |
21258 | { | |
21259 | do_crypto_3op_1 (1, 2); | |
21260 | } | |
3c9017d2 MGD |
21261 | |
21262 | static void | |
21263 | do_sha1h (void) | |
21264 | { | |
21265 | do_crypto_2op_1 (N_32, -1); | |
21266 | } | |
21267 | ||
21268 | static void | |
21269 | do_sha1su1 (void) | |
21270 | { | |
21271 | do_crypto_2op_1 (N_32, 0); | |
21272 | } | |
21273 | ||
21274 | static void | |
21275 | do_sha256su0 (void) | |
21276 | { | |
21277 | do_crypto_2op_1 (N_32, 1); | |
21278 | } | |
dd5181d5 KT |
21279 | |
21280 | static void | |
21281 | do_crc32_1 (unsigned int poly, unsigned int sz) | |
21282 | { | |
21283 | unsigned int Rd = inst.operands[0].reg; | |
21284 | unsigned int Rn = inst.operands[1].reg; | |
21285 | unsigned int Rm = inst.operands[2].reg; | |
21286 | ||
5ee91343 | 21287 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
dd5181d5 KT |
21288 | inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12); |
21289 | inst.instruction |= LOW4 (Rn) << 16; | |
21290 | inst.instruction |= LOW4 (Rm); | |
21291 | inst.instruction |= sz << (thumb_mode ? 4 : 21); | |
21292 | inst.instruction |= poly << (thumb_mode ? 20 : 9); | |
21293 | ||
21294 | if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC) | |
21295 | as_warn (UNPRED_REG ("r15")); | |
dd5181d5 KT |
21296 | } |
21297 | ||
21298 | static void | |
21299 | do_crc32b (void) | |
21300 | { | |
21301 | do_crc32_1 (0, 0); | |
21302 | } | |
21303 | ||
21304 | static void | |
21305 | do_crc32h (void) | |
21306 | { | |
21307 | do_crc32_1 (0, 1); | |
21308 | } | |
21309 | ||
21310 | static void | |
21311 | do_crc32w (void) | |
21312 | { | |
21313 | do_crc32_1 (0, 2); | |
21314 | } | |
21315 | ||
21316 | static void | |
21317 | do_crc32cb (void) | |
21318 | { | |
21319 | do_crc32_1 (1, 0); | |
21320 | } | |
21321 | ||
21322 | static void | |
21323 | do_crc32ch (void) | |
21324 | { | |
21325 | do_crc32_1 (1, 1); | |
21326 | } | |
21327 | ||
21328 | static void | |
21329 | do_crc32cw (void) | |
21330 | { | |
21331 | do_crc32_1 (1, 2); | |
21332 | } | |
21333 | ||
49e8a725 SN |
21334 | static void |
21335 | do_vjcvt (void) | |
21336 | { | |
21337 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
21338 | _(BAD_FPU)); | |
21339 | neon_check_type (2, NS_FD, N_S32, N_F64); | |
21340 | do_vfp_sp_dp_cvt (); | |
21341 | do_vfp_cond_or_thumb (); | |
21342 | } | |
21343 | ||
5287ad62 JB |
21344 | \f |
21345 | /* Overall per-instruction processing. */ | |
21346 | ||
21347 | /* We need to be able to fix up arbitrary expressions in some statements. | |
21348 | This is so that we can handle symbols that are an arbitrary distance from | |
21349 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
21350 | which returns part of an address in a form which will be valid for | |
21351 | a data instruction. We do this by pushing the expression into a symbol | |
21352 | in the expr_section, and creating a fix for that. */ | |
21353 | ||
21354 | static void | |
21355 | fix_new_arm (fragS * frag, | |
21356 | int where, | |
21357 | short int size, | |
21358 | expressionS * exp, | |
21359 | int pc_rel, | |
21360 | int reloc) | |
21361 | { | |
21362 | fixS * new_fix; | |
21363 | ||
21364 | switch (exp->X_op) | |
21365 | { | |
21366 | case O_constant: | |
6e7ce2cd PB |
21367 | if (pc_rel) |
21368 | { | |
21369 | /* Create an absolute valued symbol, so we have something to | |
477330fc RM |
21370 | refer to in the object file. Unfortunately for us, gas's |
21371 | generic expression parsing will already have folded out | |
21372 | any use of .set foo/.type foo %function that may have | |
21373 | been used to set type information of the target location, | |
21374 | that's being specified symbolically. We have to presume | |
21375 | the user knows what they are doing. */ | |
6e7ce2cd PB |
21376 | char name[16 + 8]; |
21377 | symbolS *symbol; | |
21378 | ||
21379 | sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number); | |
21380 | ||
21381 | symbol = symbol_find_or_make (name); | |
21382 | S_SET_SEGMENT (symbol, absolute_section); | |
21383 | symbol_set_frag (symbol, &zero_address_frag); | |
21384 | S_SET_VALUE (symbol, exp->X_add_number); | |
21385 | exp->X_op = O_symbol; | |
21386 | exp->X_add_symbol = symbol; | |
21387 | exp->X_add_number = 0; | |
21388 | } | |
21389 | /* FALLTHROUGH */ | |
5287ad62 JB |
21390 | case O_symbol: |
21391 | case O_add: | |
21392 | case O_subtract: | |
21d799b5 | 21393 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, |
477330fc | 21394 | (enum bfd_reloc_code_real) reloc); |
5287ad62 JB |
21395 | break; |
21396 | ||
21397 | default: | |
21d799b5 | 21398 | new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0, |
477330fc | 21399 | pc_rel, (enum bfd_reloc_code_real) reloc); |
5287ad62 JB |
21400 | break; |
21401 | } | |
21402 | ||
21403 | /* Mark whether the fix is to a THUMB instruction, or an ARM | |
21404 | instruction. */ | |
21405 | new_fix->tc_fix_data = thumb_mode; | |
21406 | } | |
21407 | ||
21408 | /* Create a frg for an instruction requiring relaxation. */ | |
21409 | static void | |
21410 | output_relax_insn (void) | |
21411 | { | |
21412 | char * to; | |
21413 | symbolS *sym; | |
0110f2b8 PB |
21414 | int offset; |
21415 | ||
6e1cb1a6 PB |
21416 | /* The size of the instruction is unknown, so tie the debug info to the |
21417 | start of the instruction. */ | |
21418 | dwarf2_emit_insn (0); | |
6e1cb1a6 | 21419 | |
e2b0ab59 | 21420 | switch (inst.relocs[0].exp.X_op) |
0110f2b8 PB |
21421 | { |
21422 | case O_symbol: | |
e2b0ab59 AV |
21423 | sym = inst.relocs[0].exp.X_add_symbol; |
21424 | offset = inst.relocs[0].exp.X_add_number; | |
0110f2b8 PB |
21425 | break; |
21426 | case O_constant: | |
21427 | sym = NULL; | |
e2b0ab59 | 21428 | offset = inst.relocs[0].exp.X_add_number; |
0110f2b8 PB |
21429 | break; |
21430 | default: | |
e2b0ab59 | 21431 | sym = make_expr_symbol (&inst.relocs[0].exp); |
0110f2b8 PB |
21432 | offset = 0; |
21433 | break; | |
21434 | } | |
21435 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
21436 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
21437 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
0110f2b8 PB |
21438 | } |
21439 | ||
21440 | /* Write a 32-bit thumb instruction to buf. */ | |
21441 | static void | |
21442 | put_thumb32_insn (char * buf, unsigned long insn) | |
21443 | { | |
21444 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
21445 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
21446 | } | |
21447 | ||
b99bd4ef | 21448 | static void |
c19d1205 | 21449 | output_inst (const char * str) |
b99bd4ef | 21450 | { |
c19d1205 | 21451 | char * to = NULL; |
b99bd4ef | 21452 | |
c19d1205 | 21453 | if (inst.error) |
b99bd4ef | 21454 | { |
c19d1205 | 21455 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
21456 | return; |
21457 | } | |
5f4273c7 NC |
21458 | if (inst.relax) |
21459 | { | |
21460 | output_relax_insn (); | |
0110f2b8 | 21461 | return; |
5f4273c7 | 21462 | } |
c19d1205 ZW |
21463 | if (inst.size == 0) |
21464 | return; | |
b99bd4ef | 21465 | |
c19d1205 | 21466 | to = frag_more (inst.size); |
8dc2430f NC |
21467 | /* PR 9814: Record the thumb mode into the current frag so that we know |
21468 | what type of NOP padding to use, if necessary. We override any previous | |
21469 | setting so that if the mode has changed then the NOPS that we use will | |
21470 | match the encoding of the last instruction in the frag. */ | |
cd000bff | 21471 | frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
c19d1205 ZW |
21472 | |
21473 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 21474 | { |
9c2799c2 | 21475 | gas_assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 21476 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 21477 | } |
c19d1205 | 21478 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 21479 | { |
9c2799c2 | 21480 | gas_assert (inst.size == (2 * INSN_SIZE)); |
c19d1205 ZW |
21481 | md_number_to_chars (to, inst.instruction, INSN_SIZE); |
21482 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 21483 | } |
c19d1205 ZW |
21484 | else |
21485 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 21486 | |
e2b0ab59 AV |
21487 | int r; |
21488 | for (r = 0; r < ARM_IT_MAX_RELOCS; r++) | |
21489 | { | |
21490 | if (inst.relocs[r].type != BFD_RELOC_UNUSED) | |
21491 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
21492 | inst.size, & inst.relocs[r].exp, inst.relocs[r].pc_rel, | |
21493 | inst.relocs[r].type); | |
21494 | } | |
b99bd4ef | 21495 | |
c19d1205 | 21496 | dwarf2_emit_insn (inst.size); |
c19d1205 | 21497 | } |
b99bd4ef | 21498 | |
e07e6e58 NC |
21499 | static char * |
21500 | output_it_inst (int cond, int mask, char * to) | |
21501 | { | |
21502 | unsigned long instruction = 0xbf00; | |
21503 | ||
21504 | mask &= 0xf; | |
21505 | instruction |= mask; | |
21506 | instruction |= cond << 4; | |
21507 | ||
21508 | if (to == NULL) | |
21509 | { | |
21510 | to = frag_more (2); | |
21511 | #ifdef OBJ_ELF | |
21512 | dwarf2_emit_insn (2); | |
21513 | #endif | |
21514 | } | |
21515 | ||
21516 | md_number_to_chars (to, instruction, 2); | |
21517 | ||
21518 | return to; | |
21519 | } | |
21520 | ||
c19d1205 ZW |
21521 | /* Tag values used in struct asm_opcode's tag field. */ |
21522 | enum opcode_tag | |
21523 | { | |
21524 | OT_unconditional, /* Instruction cannot be conditionalized. | |
21525 | The ARM condition field is still 0xE. */ | |
21526 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
21527 | and carries 0xF in its ARM condition field. */ | |
21528 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
5ee91343 AV |
21529 | OT_csuffixF, /* Some forms of the instruction take a scalar |
21530 | conditional suffix, others place 0xF where the | |
21531 | condition field would be, others take a vector | |
21532 | conditional suffix. */ | |
c19d1205 ZW |
21533 | OT_cinfix3, /* Instruction takes a conditional infix, |
21534 | beginning at character index 3. (In | |
21535 | unified mode, it becomes a suffix.) */ | |
088fa78e KH |
21536 | OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for |
21537 | tsts, cmps, cmns, and teqs. */ | |
e3cb604e PB |
21538 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
21539 | character index 3, even in unified mode. Used for | |
21540 | legacy instructions where suffix and infix forms | |
21541 | may be ambiguous. */ | |
c19d1205 | 21542 | OT_csuf_or_in3, /* Instruction takes either a conditional |
e3cb604e | 21543 | suffix or an infix at character index 3. */ |
c19d1205 ZW |
21544 | OT_odd_infix_unc, /* This is the unconditional variant of an |
21545 | instruction that takes a conditional infix | |
21546 | at an unusual position. In unified mode, | |
21547 | this variant will accept a suffix. */ | |
21548 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
21549 | are the conditional variants of instructions that | |
21550 | take conditional infixes in unusual positions. | |
21551 | The infix appears at character index | |
21552 | (tag - OT_odd_infix_0). These are not accepted | |
21553 | in unified mode. */ | |
21554 | }; | |
b99bd4ef | 21555 | |
c19d1205 ZW |
21556 | /* Subroutine of md_assemble, responsible for looking up the primary |
21557 | opcode from the mnemonic the user wrote. STR points to the | |
21558 | beginning of the mnemonic. | |
21559 | ||
21560 | This is not simply a hash table lookup, because of conditional | |
21561 | variants. Most instructions have conditional variants, which are | |
21562 | expressed with a _conditional affix_ to the mnemonic. If we were | |
21563 | to encode each conditional variant as a literal string in the opcode | |
21564 | table, it would have approximately 20,000 entries. | |
21565 | ||
21566 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
21567 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
21568 | instructions take the affix as an infix, notably the s-variants of | |
21569 | the arithmetic instructions. Of those instructions, all but six | |
21570 | have the infix appear after the third character of the mnemonic. | |
21571 | ||
21572 | Accordingly, the algorithm for looking up primary opcodes given | |
21573 | an identifier is: | |
21574 | ||
21575 | 1. Look up the identifier in the opcode table. | |
21576 | If we find a match, go to step U. | |
21577 | ||
21578 | 2. Look up the last two characters of the identifier in the | |
21579 | conditions table. If we find a match, look up the first N-2 | |
21580 | characters of the identifier in the opcode table. If we | |
21581 | find a match, go to step CE. | |
21582 | ||
21583 | 3. Look up the fourth and fifth characters of the identifier in | |
21584 | the conditions table. If we find a match, extract those | |
21585 | characters from the identifier, and look up the remaining | |
21586 | characters in the opcode table. If we find a match, go | |
21587 | to step CM. | |
21588 | ||
21589 | 4. Fail. | |
21590 | ||
21591 | U. Examine the tag field of the opcode structure, in case this is | |
21592 | one of the six instructions with its conditional infix in an | |
21593 | unusual place. If it is, the tag tells us where to find the | |
21594 | infix; look it up in the conditions table and set inst.cond | |
21595 | accordingly. Otherwise, this is an unconditional instruction. | |
21596 | Again set inst.cond accordingly. Return the opcode structure. | |
21597 | ||
21598 | CE. Examine the tag field to make sure this is an instruction that | |
21599 | should receive a conditional suffix. If it is not, fail. | |
21600 | Otherwise, set inst.cond from the suffix we already looked up, | |
21601 | and return the opcode structure. | |
21602 | ||
21603 | CM. Examine the tag field to make sure this is an instruction that | |
21604 | should receive a conditional infix after the third character. | |
21605 | If it is not, fail. Otherwise, undo the edits to the current | |
21606 | line of input and proceed as for case CE. */ | |
21607 | ||
21608 | static const struct asm_opcode * | |
21609 | opcode_lookup (char **str) | |
21610 | { | |
21611 | char *end, *base; | |
21612 | char *affix; | |
21613 | const struct asm_opcode *opcode; | |
21614 | const struct asm_cond *cond; | |
e3cb604e | 21615 | char save[2]; |
c19d1205 ZW |
21616 | |
21617 | /* Scan up to the end of the mnemonic, which must end in white space, | |
721a8186 | 21618 | '.' (in unified mode, or for Neon/VFP instructions), or end of string. */ |
c19d1205 | 21619 | for (base = end = *str; *end != '\0'; end++) |
721a8186 | 21620 | if (*end == ' ' || *end == '.') |
c19d1205 | 21621 | break; |
b99bd4ef | 21622 | |
c19d1205 | 21623 | if (end == base) |
c921be7d | 21624 | return NULL; |
b99bd4ef | 21625 | |
5287ad62 | 21626 | /* Handle a possible width suffix and/or Neon type suffix. */ |
c19d1205 | 21627 | if (end[0] == '.') |
b99bd4ef | 21628 | { |
5287ad62 | 21629 | int offset = 2; |
5f4273c7 | 21630 | |
267d2029 | 21631 | /* The .w and .n suffixes are only valid if the unified syntax is in |
477330fc | 21632 | use. */ |
267d2029 | 21633 | if (unified_syntax && end[1] == 'w') |
c19d1205 | 21634 | inst.size_req = 4; |
267d2029 | 21635 | else if (unified_syntax && end[1] == 'n') |
c19d1205 ZW |
21636 | inst.size_req = 2; |
21637 | else | |
477330fc | 21638 | offset = 0; |
5287ad62 JB |
21639 | |
21640 | inst.vectype.elems = 0; | |
21641 | ||
21642 | *str = end + offset; | |
b99bd4ef | 21643 | |
5f4273c7 | 21644 | if (end[offset] == '.') |
5287ad62 | 21645 | { |
267d2029 | 21646 | /* See if we have a Neon type suffix (possible in either unified or |
477330fc RM |
21647 | non-unified ARM syntax mode). */ |
21648 | if (parse_neon_type (&inst.vectype, str) == FAIL) | |
c921be7d | 21649 | return NULL; |
477330fc | 21650 | } |
5287ad62 | 21651 | else if (end[offset] != '\0' && end[offset] != ' ') |
477330fc | 21652 | return NULL; |
b99bd4ef | 21653 | } |
c19d1205 ZW |
21654 | else |
21655 | *str = end; | |
b99bd4ef | 21656 | |
c19d1205 | 21657 | /* Look for unaffixed or special-case affixed mnemonic. */ |
21d799b5 | 21658 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
477330fc | 21659 | end - base); |
c19d1205 | 21660 | if (opcode) |
b99bd4ef | 21661 | { |
c19d1205 ZW |
21662 | /* step U */ |
21663 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 21664 | { |
c19d1205 ZW |
21665 | inst.cond = COND_ALWAYS; |
21666 | return opcode; | |
b99bd4ef | 21667 | } |
b99bd4ef | 21668 | |
278df34e | 21669 | if (warn_on_deprecated && unified_syntax) |
5c3696f8 | 21670 | as_tsktsk (_("conditional infixes are deprecated in unified syntax")); |
c19d1205 | 21671 | affix = base + (opcode->tag - OT_odd_infix_0); |
21d799b5 | 21672 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
9c2799c2 | 21673 | gas_assert (cond); |
b99bd4ef | 21674 | |
c19d1205 ZW |
21675 | inst.cond = cond->value; |
21676 | return opcode; | |
21677 | } | |
5ee91343 AV |
21678 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
21679 | { | |
21680 | /* Cannot have a conditional suffix on a mnemonic of less than a character. | |
21681 | */ | |
21682 | if (end - base < 2) | |
21683 | return NULL; | |
21684 | affix = end - 1; | |
21685 | cond = (const struct asm_cond *) hash_find_n (arm_vcond_hsh, affix, 1); | |
21686 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, | |
21687 | affix - base); | |
21688 | /* If this opcode can not be vector predicated then don't accept it with a | |
21689 | vector predication code. */ | |
21690 | if (opcode && !opcode->mayBeVecPred) | |
21691 | opcode = NULL; | |
21692 | } | |
21693 | if (!opcode || !cond) | |
21694 | { | |
21695 | /* Cannot have a conditional suffix on a mnemonic of less than two | |
21696 | characters. */ | |
21697 | if (end - base < 3) | |
21698 | return NULL; | |
b99bd4ef | 21699 | |
5ee91343 AV |
21700 | /* Look for suffixed mnemonic. */ |
21701 | affix = end - 2; | |
21702 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); | |
21703 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, | |
21704 | affix - base); | |
21705 | } | |
b99bd4ef | 21706 | |
c19d1205 ZW |
21707 | if (opcode && cond) |
21708 | { | |
21709 | /* step CE */ | |
21710 | switch (opcode->tag) | |
21711 | { | |
e3cb604e PB |
21712 | case OT_cinfix3_legacy: |
21713 | /* Ignore conditional suffixes matched on infix only mnemonics. */ | |
21714 | break; | |
21715 | ||
c19d1205 | 21716 | case OT_cinfix3: |
088fa78e | 21717 | case OT_cinfix3_deprecated: |
c19d1205 ZW |
21718 | case OT_odd_infix_unc: |
21719 | if (!unified_syntax) | |
0198d5e6 | 21720 | return NULL; |
1a0670f3 | 21721 | /* Fall through. */ |
c19d1205 ZW |
21722 | |
21723 | case OT_csuffix: | |
477330fc | 21724 | case OT_csuffixF: |
c19d1205 ZW |
21725 | case OT_csuf_or_in3: |
21726 | inst.cond = cond->value; | |
21727 | return opcode; | |
21728 | ||
21729 | case OT_unconditional: | |
21730 | case OT_unconditionalF: | |
dfa9f0d5 | 21731 | if (thumb_mode) |
c921be7d | 21732 | inst.cond = cond->value; |
dfa9f0d5 PB |
21733 | else |
21734 | { | |
c921be7d | 21735 | /* Delayed diagnostic. */ |
dfa9f0d5 PB |
21736 | inst.error = BAD_COND; |
21737 | inst.cond = COND_ALWAYS; | |
21738 | } | |
c19d1205 | 21739 | return opcode; |
b99bd4ef | 21740 | |
c19d1205 | 21741 | default: |
c921be7d | 21742 | return NULL; |
c19d1205 ZW |
21743 | } |
21744 | } | |
b99bd4ef | 21745 | |
c19d1205 ZW |
21746 | /* Cannot have a usual-position infix on a mnemonic of less than |
21747 | six characters (five would be a suffix). */ | |
21748 | if (end - base < 6) | |
c921be7d | 21749 | return NULL; |
b99bd4ef | 21750 | |
c19d1205 ZW |
21751 | /* Look for infixed mnemonic in the usual position. */ |
21752 | affix = base + 3; | |
21d799b5 | 21753 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
e3cb604e | 21754 | if (!cond) |
c921be7d | 21755 | return NULL; |
e3cb604e PB |
21756 | |
21757 | memcpy (save, affix, 2); | |
21758 | memmove (affix, affix + 2, (end - affix) - 2); | |
21d799b5 | 21759 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
477330fc | 21760 | (end - base) - 2); |
e3cb604e PB |
21761 | memmove (affix + 2, affix, (end - affix) - 2); |
21762 | memcpy (affix, save, 2); | |
21763 | ||
088fa78e KH |
21764 | if (opcode |
21765 | && (opcode->tag == OT_cinfix3 | |
21766 | || opcode->tag == OT_cinfix3_deprecated | |
21767 | || opcode->tag == OT_csuf_or_in3 | |
21768 | || opcode->tag == OT_cinfix3_legacy)) | |
b99bd4ef | 21769 | { |
c921be7d | 21770 | /* Step CM. */ |
278df34e | 21771 | if (warn_on_deprecated && unified_syntax |
088fa78e KH |
21772 | && (opcode->tag == OT_cinfix3 |
21773 | || opcode->tag == OT_cinfix3_deprecated)) | |
5c3696f8 | 21774 | as_tsktsk (_("conditional infixes are deprecated in unified syntax")); |
c19d1205 ZW |
21775 | |
21776 | inst.cond = cond->value; | |
21777 | return opcode; | |
b99bd4ef NC |
21778 | } |
21779 | ||
c921be7d | 21780 | return NULL; |
b99bd4ef NC |
21781 | } |
21782 | ||
e07e6e58 NC |
21783 | /* This function generates an initial IT instruction, leaving its block |
21784 | virtually open for the new instructions. Eventually, | |
5ee91343 | 21785 | the mask will be updated by now_pred_add_mask () each time |
e07e6e58 NC |
21786 | a new instruction needs to be included in the IT block. |
21787 | Finally, the block is closed with close_automatic_it_block (). | |
21788 | The block closure can be requested either from md_assemble (), | |
21789 | a tencode (), or due to a label hook. */ | |
21790 | ||
21791 | static void | |
21792 | new_automatic_it_block (int cond) | |
21793 | { | |
5ee91343 AV |
21794 | now_pred.state = AUTOMATIC_PRED_BLOCK; |
21795 | now_pred.mask = 0x18; | |
21796 | now_pred.cc = cond; | |
21797 | now_pred.block_length = 1; | |
cd000bff | 21798 | mapping_state (MAP_THUMB); |
5ee91343 AV |
21799 | now_pred.insn = output_it_inst (cond, now_pred.mask, NULL); |
21800 | now_pred.warn_deprecated = FALSE; | |
21801 | now_pred.insn_cond = TRUE; | |
e07e6e58 NC |
21802 | } |
21803 | ||
21804 | /* Close an automatic IT block. | |
21805 | See comments in new_automatic_it_block (). */ | |
21806 | ||
21807 | static void | |
21808 | close_automatic_it_block (void) | |
21809 | { | |
5ee91343 AV |
21810 | now_pred.mask = 0x10; |
21811 | now_pred.block_length = 0; | |
e07e6e58 NC |
21812 | } |
21813 | ||
21814 | /* Update the mask of the current automatically-generated IT | |
21815 | instruction. See comments in new_automatic_it_block (). */ | |
21816 | ||
21817 | static void | |
5ee91343 | 21818 | now_pred_add_mask (int cond) |
e07e6e58 NC |
21819 | { |
21820 | #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit))) | |
21821 | #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \ | |
477330fc | 21822 | | ((bitvalue) << (nbit))) |
e07e6e58 | 21823 | const int resulting_bit = (cond & 1); |
c921be7d | 21824 | |
5ee91343 AV |
21825 | now_pred.mask &= 0xf; |
21826 | now_pred.mask = SET_BIT_VALUE (now_pred.mask, | |
477330fc | 21827 | resulting_bit, |
5ee91343 AV |
21828 | (5 - now_pred.block_length)); |
21829 | now_pred.mask = SET_BIT_VALUE (now_pred.mask, | |
477330fc | 21830 | 1, |
5ee91343 AV |
21831 | ((5 - now_pred.block_length) - 1)); |
21832 | output_it_inst (now_pred.cc, now_pred.mask, now_pred.insn); | |
e07e6e58 NC |
21833 | |
21834 | #undef CLEAR_BIT | |
21835 | #undef SET_BIT_VALUE | |
e07e6e58 NC |
21836 | } |
21837 | ||
21838 | /* The IT blocks handling machinery is accessed through the these functions: | |
21839 | it_fsm_pre_encode () from md_assemble () | |
5ee91343 AV |
21840 | set_pred_insn_type () optional, from the tencode functions |
21841 | set_pred_insn_type_last () ditto | |
21842 | in_pred_block () ditto | |
e07e6e58 | 21843 | it_fsm_post_encode () from md_assemble () |
33eaf5de | 21844 | force_automatic_it_block_close () from label handling functions |
e07e6e58 NC |
21845 | |
21846 | Rationale: | |
21847 | 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), | |
477330fc RM |
21848 | initializing the IT insn type with a generic initial value depending |
21849 | on the inst.condition. | |
e07e6e58 | 21850 | 2) During the tencode function, two things may happen: |
477330fc | 21851 | a) The tencode function overrides the IT insn type by |
5ee91343 AV |
21852 | calling either set_pred_insn_type (type) or |
21853 | set_pred_insn_type_last (). | |
477330fc | 21854 | b) The tencode function queries the IT block state by |
5ee91343 | 21855 | calling in_pred_block () (i.e. to determine narrow/not narrow mode). |
477330fc | 21856 | |
5ee91343 AV |
21857 | Both set_pred_insn_type and in_pred_block run the internal FSM state |
21858 | handling function (handle_pred_state), because: a) setting the IT insn | |
477330fc RM |
21859 | type may incur in an invalid state (exiting the function), |
21860 | and b) querying the state requires the FSM to be updated. | |
21861 | Specifically we want to avoid creating an IT block for conditional | |
21862 | branches, so it_fsm_pre_encode is actually a guess and we can't | |
21863 | determine whether an IT block is required until the tencode () routine | |
21864 | has decided what type of instruction this actually it. | |
5ee91343 AV |
21865 | Because of this, if set_pred_insn_type and in_pred_block have to be |
21866 | used, set_pred_insn_type has to be called first. | |
477330fc | 21867 | |
5ee91343 AV |
21868 | set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type), |
21869 | that determines the insn IT type depending on the inst.cond code. | |
477330fc RM |
21870 | When a tencode () routine encodes an instruction that can be |
21871 | either outside an IT block, or, in the case of being inside, has to be | |
5ee91343 | 21872 | the last one, set_pred_insn_type_last () will determine the proper |
477330fc | 21873 | IT instruction type based on the inst.cond code. Otherwise, |
5ee91343 | 21874 | set_pred_insn_type can be called for overriding that logic or |
477330fc RM |
21875 | for covering other cases. |
21876 | ||
5ee91343 AV |
21877 | Calling handle_pred_state () may not transition the IT block state to |
21878 | OUTSIDE_PRED_BLOCK immediately, since the (current) state could be | |
477330fc | 21879 | still queried. Instead, if the FSM determines that the state should |
5ee91343 | 21880 | be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed |
477330fc RM |
21881 | after the tencode () function: that's what it_fsm_post_encode () does. |
21882 | ||
5ee91343 | 21883 | Since in_pred_block () calls the state handling function to get an |
477330fc RM |
21884 | updated state, an error may occur (due to invalid insns combination). |
21885 | In that case, inst.error is set. | |
21886 | Therefore, inst.error has to be checked after the execution of | |
21887 | the tencode () routine. | |
e07e6e58 NC |
21888 | |
21889 | 3) Back in md_assemble(), it_fsm_post_encode () is called to commit | |
477330fc | 21890 | any pending state change (if any) that didn't take place in |
5ee91343 | 21891 | handle_pred_state () as explained above. */ |
e07e6e58 NC |
21892 | |
21893 | static void | |
21894 | it_fsm_pre_encode (void) | |
21895 | { | |
21896 | if (inst.cond != COND_ALWAYS) | |
5ee91343 | 21897 | inst.pred_insn_type = INSIDE_IT_INSN; |
e07e6e58 | 21898 | else |
5ee91343 | 21899 | inst.pred_insn_type = OUTSIDE_PRED_INSN; |
e07e6e58 | 21900 | |
5ee91343 | 21901 | now_pred.state_handled = 0; |
e07e6e58 NC |
21902 | } |
21903 | ||
21904 | /* IT state FSM handling function. */ | |
5ee91343 AV |
21905 | /* MVE instructions and non-MVE instructions are handled differently because of |
21906 | the introduction of VPT blocks. | |
21907 | Specifications say that any non-MVE instruction inside a VPT block is | |
21908 | UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE | |
21909 | instructions are deemed to be UNPREDICTABLE if inside an IT block. For the | |
35c228db | 21910 | few exceptions we have MVE_UNPREDICABLE_INSN. |
5ee91343 AV |
21911 | The error messages provided depending on the different combinations possible |
21912 | are described in the cases below: | |
21913 | For 'most' MVE instructions: | |
21914 | 1) In an IT block, with an IT code: syntax error | |
21915 | 2) In an IT block, with a VPT code: error: must be in a VPT block | |
21916 | 3) In an IT block, with no code: warning: UNPREDICTABLE | |
21917 | 4) In a VPT block, with an IT code: syntax error | |
21918 | 5) In a VPT block, with a VPT code: OK! | |
21919 | 6) In a VPT block, with no code: error: missing code | |
21920 | 7) Outside a pred block, with an IT code: error: syntax error | |
21921 | 8) Outside a pred block, with a VPT code: error: should be in a VPT block | |
21922 | 9) Outside a pred block, with no code: OK! | |
21923 | For non-MVE instructions: | |
21924 | 10) In an IT block, with an IT code: OK! | |
21925 | 11) In an IT block, with a VPT code: syntax error | |
21926 | 12) In an IT block, with no code: error: missing code | |
21927 | 13) In a VPT block, with an IT code: error: should be in an IT block | |
21928 | 14) In a VPT block, with a VPT code: syntax error | |
21929 | 15) In a VPT block, with no code: UNPREDICTABLE | |
21930 | 16) Outside a pred block, with an IT code: error: should be in an IT block | |
21931 | 17) Outside a pred block, with a VPT code: syntax error | |
21932 | 18) Outside a pred block, with no code: OK! | |
21933 | */ | |
21934 | ||
e07e6e58 NC |
21935 | |
21936 | static int | |
5ee91343 | 21937 | handle_pred_state (void) |
e07e6e58 | 21938 | { |
5ee91343 AV |
21939 | now_pred.state_handled = 1; |
21940 | now_pred.insn_cond = FALSE; | |
e07e6e58 | 21941 | |
5ee91343 | 21942 | switch (now_pred.state) |
e07e6e58 | 21943 | { |
5ee91343 AV |
21944 | case OUTSIDE_PRED_BLOCK: |
21945 | switch (inst.pred_insn_type) | |
e07e6e58 | 21946 | { |
35c228db | 21947 | case MVE_UNPREDICABLE_INSN: |
5ee91343 AV |
21948 | case MVE_OUTSIDE_PRED_INSN: |
21949 | if (inst.cond < COND_ALWAYS) | |
21950 | { | |
21951 | /* Case 7: Outside a pred block, with an IT code: error: syntax | |
21952 | error. */ | |
21953 | inst.error = BAD_SYNTAX; | |
21954 | return FAIL; | |
21955 | } | |
21956 | /* Case 9: Outside a pred block, with no code: OK! */ | |
21957 | break; | |
21958 | case OUTSIDE_PRED_INSN: | |
21959 | if (inst.cond > COND_ALWAYS) | |
21960 | { | |
21961 | /* Case 17: Outside a pred block, with a VPT code: syntax error. | |
21962 | */ | |
21963 | inst.error = BAD_SYNTAX; | |
21964 | return FAIL; | |
21965 | } | |
21966 | /* Case 18: Outside a pred block, with no code: OK! */ | |
e07e6e58 NC |
21967 | break; |
21968 | ||
5ee91343 AV |
21969 | case INSIDE_VPT_INSN: |
21970 | /* Case 8: Outside a pred block, with a VPT code: error: should be in | |
21971 | a VPT block. */ | |
21972 | inst.error = BAD_OUT_VPT; | |
21973 | return FAIL; | |
21974 | ||
e07e6e58 NC |
21975 | case INSIDE_IT_INSN: |
21976 | case INSIDE_IT_LAST_INSN: | |
5ee91343 | 21977 | if (inst.cond < COND_ALWAYS) |
e07e6e58 | 21978 | { |
5ee91343 AV |
21979 | /* Case 16: Outside a pred block, with an IT code: error: should |
21980 | be in an IT block. */ | |
21981 | if (thumb_mode == 0) | |
e07e6e58 | 21982 | { |
5ee91343 AV |
21983 | if (unified_syntax |
21984 | && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM)) | |
21985 | as_tsktsk (_("Warning: conditional outside an IT block"\ | |
21986 | " for Thumb.")); | |
e07e6e58 NC |
21987 | } |
21988 | else | |
21989 | { | |
5ee91343 AV |
21990 | if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB) |
21991 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)) | |
21992 | { | |
21993 | /* Automatically generate the IT instruction. */ | |
21994 | new_automatic_it_block (inst.cond); | |
21995 | if (inst.pred_insn_type == INSIDE_IT_LAST_INSN) | |
21996 | close_automatic_it_block (); | |
21997 | } | |
21998 | else | |
21999 | { | |
22000 | inst.error = BAD_OUT_IT; | |
22001 | return FAIL; | |
22002 | } | |
e07e6e58 | 22003 | } |
5ee91343 | 22004 | break; |
e07e6e58 | 22005 | } |
5ee91343 AV |
22006 | else if (inst.cond > COND_ALWAYS) |
22007 | { | |
22008 | /* Case 17: Outside a pred block, with a VPT code: syntax error. | |
22009 | */ | |
22010 | inst.error = BAD_SYNTAX; | |
22011 | return FAIL; | |
22012 | } | |
22013 | else | |
22014 | gas_assert (0); | |
e07e6e58 NC |
22015 | case IF_INSIDE_IT_LAST_INSN: |
22016 | case NEUTRAL_IT_INSN: | |
22017 | break; | |
22018 | ||
5ee91343 AV |
22019 | case VPT_INSN: |
22020 | if (inst.cond != COND_ALWAYS) | |
22021 | first_error (BAD_SYNTAX); | |
22022 | now_pred.state = MANUAL_PRED_BLOCK; | |
22023 | now_pred.block_length = 0; | |
22024 | now_pred.type = VECTOR_PRED; | |
22025 | now_pred.cc = 0; | |
22026 | break; | |
e07e6e58 | 22027 | case IT_INSN: |
5ee91343 AV |
22028 | now_pred.state = MANUAL_PRED_BLOCK; |
22029 | now_pred.block_length = 0; | |
22030 | now_pred.type = SCALAR_PRED; | |
e07e6e58 NC |
22031 | break; |
22032 | } | |
22033 | break; | |
22034 | ||
5ee91343 | 22035 | case AUTOMATIC_PRED_BLOCK: |
e07e6e58 NC |
22036 | /* Three things may happen now: |
22037 | a) We should increment current it block size; | |
22038 | b) We should close current it block (closing insn or 4 insns); | |
22039 | c) We should close current it block and start a new one (due | |
22040 | to incompatible conditions or | |
22041 | 4 insns-length block reached). */ | |
22042 | ||
5ee91343 | 22043 | switch (inst.pred_insn_type) |
e07e6e58 | 22044 | { |
5ee91343 AV |
22045 | case INSIDE_VPT_INSN: |
22046 | case VPT_INSN: | |
35c228db | 22047 | case MVE_UNPREDICABLE_INSN: |
5ee91343 AV |
22048 | case MVE_OUTSIDE_PRED_INSN: |
22049 | gas_assert (0); | |
22050 | case OUTSIDE_PRED_INSN: | |
2b0f3761 | 22051 | /* The closure of the block shall happen immediately, |
5ee91343 | 22052 | so any in_pred_block () call reports the block as closed. */ |
e07e6e58 NC |
22053 | force_automatic_it_block_close (); |
22054 | break; | |
22055 | ||
22056 | case INSIDE_IT_INSN: | |
22057 | case INSIDE_IT_LAST_INSN: | |
22058 | case IF_INSIDE_IT_LAST_INSN: | |
5ee91343 | 22059 | now_pred.block_length++; |
e07e6e58 | 22060 | |
5ee91343 AV |
22061 | if (now_pred.block_length > 4 |
22062 | || !now_pred_compatible (inst.cond)) | |
e07e6e58 NC |
22063 | { |
22064 | force_automatic_it_block_close (); | |
5ee91343 | 22065 | if (inst.pred_insn_type != IF_INSIDE_IT_LAST_INSN) |
e07e6e58 NC |
22066 | new_automatic_it_block (inst.cond); |
22067 | } | |
22068 | else | |
22069 | { | |
5ee91343 AV |
22070 | now_pred.insn_cond = TRUE; |
22071 | now_pred_add_mask (inst.cond); | |
e07e6e58 NC |
22072 | } |
22073 | ||
5ee91343 AV |
22074 | if (now_pred.state == AUTOMATIC_PRED_BLOCK |
22075 | && (inst.pred_insn_type == INSIDE_IT_LAST_INSN | |
22076 | || inst.pred_insn_type == IF_INSIDE_IT_LAST_INSN)) | |
e07e6e58 NC |
22077 | close_automatic_it_block (); |
22078 | break; | |
22079 | ||
22080 | case NEUTRAL_IT_INSN: | |
5ee91343 AV |
22081 | now_pred.block_length++; |
22082 | now_pred.insn_cond = TRUE; | |
e07e6e58 | 22083 | |
5ee91343 | 22084 | if (now_pred.block_length > 4) |
e07e6e58 NC |
22085 | force_automatic_it_block_close (); |
22086 | else | |
5ee91343 | 22087 | now_pred_add_mask (now_pred.cc & 1); |
e07e6e58 NC |
22088 | break; |
22089 | ||
22090 | case IT_INSN: | |
22091 | close_automatic_it_block (); | |
5ee91343 | 22092 | now_pred.state = MANUAL_PRED_BLOCK; |
e07e6e58 NC |
22093 | break; |
22094 | } | |
22095 | break; | |
22096 | ||
5ee91343 | 22097 | case MANUAL_PRED_BLOCK: |
e07e6e58 | 22098 | { |
5ee91343 AV |
22099 | int cond, is_last; |
22100 | if (now_pred.type == SCALAR_PRED) | |
e07e6e58 | 22101 | { |
5ee91343 AV |
22102 | /* Check conditional suffixes. */ |
22103 | cond = now_pred.cc ^ ((now_pred.mask >> 4) & 1) ^ 1; | |
22104 | now_pred.mask <<= 1; | |
22105 | now_pred.mask &= 0x1f; | |
22106 | is_last = (now_pred.mask == 0x10); | |
22107 | } | |
22108 | else | |
22109 | { | |
22110 | now_pred.cc ^= (now_pred.mask >> 4); | |
22111 | cond = now_pred.cc + 0xf; | |
22112 | now_pred.mask <<= 1; | |
22113 | now_pred.mask &= 0x1f; | |
22114 | is_last = now_pred.mask == 0x10; | |
22115 | } | |
22116 | now_pred.insn_cond = TRUE; | |
e07e6e58 | 22117 | |
5ee91343 AV |
22118 | switch (inst.pred_insn_type) |
22119 | { | |
22120 | case OUTSIDE_PRED_INSN: | |
22121 | if (now_pred.type == SCALAR_PRED) | |
22122 | { | |
22123 | if (inst.cond == COND_ALWAYS) | |
22124 | { | |
22125 | /* Case 12: In an IT block, with no code: error: missing | |
22126 | code. */ | |
22127 | inst.error = BAD_NOT_IT; | |
22128 | return FAIL; | |
22129 | } | |
22130 | else if (inst.cond > COND_ALWAYS) | |
22131 | { | |
22132 | /* Case 11: In an IT block, with a VPT code: syntax error. | |
22133 | */ | |
22134 | inst.error = BAD_SYNTAX; | |
22135 | return FAIL; | |
22136 | } | |
22137 | else if (thumb_mode) | |
22138 | { | |
22139 | /* This is for some special cases where a non-MVE | |
22140 | instruction is not allowed in an IT block, such as cbz, | |
22141 | but are put into one with a condition code. | |
22142 | You could argue this should be a syntax error, but we | |
22143 | gave the 'not allowed in IT block' diagnostic in the | |
22144 | past so we will keep doing so. */ | |
22145 | inst.error = BAD_NOT_IT; | |
22146 | return FAIL; | |
22147 | } | |
22148 | break; | |
22149 | } | |
22150 | else | |
22151 | { | |
22152 | /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */ | |
22153 | as_tsktsk (MVE_NOT_VPT); | |
22154 | return SUCCESS; | |
22155 | } | |
22156 | case MVE_OUTSIDE_PRED_INSN: | |
22157 | if (now_pred.type == SCALAR_PRED) | |
22158 | { | |
22159 | if (inst.cond == COND_ALWAYS) | |
22160 | { | |
22161 | /* Case 3: In an IT block, with no code: warning: | |
22162 | UNPREDICTABLE. */ | |
22163 | as_tsktsk (MVE_NOT_IT); | |
22164 | return SUCCESS; | |
22165 | } | |
22166 | else if (inst.cond < COND_ALWAYS) | |
22167 | { | |
22168 | /* Case 1: In an IT block, with an IT code: syntax error. | |
22169 | */ | |
22170 | inst.error = BAD_SYNTAX; | |
22171 | return FAIL; | |
22172 | } | |
22173 | else | |
22174 | gas_assert (0); | |
22175 | } | |
22176 | else | |
22177 | { | |
22178 | if (inst.cond < COND_ALWAYS) | |
22179 | { | |
22180 | /* Case 4: In a VPT block, with an IT code: syntax error. | |
22181 | */ | |
22182 | inst.error = BAD_SYNTAX; | |
22183 | return FAIL; | |
22184 | } | |
22185 | else if (inst.cond == COND_ALWAYS) | |
22186 | { | |
22187 | /* Case 6: In a VPT block, with no code: error: missing | |
22188 | code. */ | |
22189 | inst.error = BAD_NOT_VPT; | |
22190 | return FAIL; | |
22191 | } | |
22192 | else | |
22193 | { | |
22194 | gas_assert (0); | |
22195 | } | |
22196 | } | |
35c228db AV |
22197 | case MVE_UNPREDICABLE_INSN: |
22198 | as_tsktsk (now_pred.type == SCALAR_PRED ? MVE_NOT_IT : MVE_NOT_VPT); | |
22199 | return SUCCESS; | |
e07e6e58 | 22200 | case INSIDE_IT_INSN: |
5ee91343 | 22201 | if (inst.cond > COND_ALWAYS) |
e07e6e58 | 22202 | { |
5ee91343 AV |
22203 | /* Case 11: In an IT block, with a VPT code: syntax error. */ |
22204 | /* Case 14: In a VPT block, with a VPT code: syntax error. */ | |
22205 | inst.error = BAD_SYNTAX; | |
22206 | return FAIL; | |
22207 | } | |
22208 | else if (now_pred.type == SCALAR_PRED) | |
22209 | { | |
22210 | /* Case 10: In an IT block, with an IT code: OK! */ | |
22211 | if (cond != inst.cond) | |
22212 | { | |
22213 | inst.error = now_pred.type == SCALAR_PRED ? BAD_IT_COND : | |
22214 | BAD_VPT_COND; | |
22215 | return FAIL; | |
22216 | } | |
22217 | } | |
22218 | else | |
22219 | { | |
22220 | /* Case 13: In a VPT block, with an IT code: error: should be | |
22221 | in an IT block. */ | |
22222 | inst.error = BAD_OUT_IT; | |
e07e6e58 NC |
22223 | return FAIL; |
22224 | } | |
22225 | break; | |
22226 | ||
5ee91343 AV |
22227 | case INSIDE_VPT_INSN: |
22228 | if (now_pred.type == SCALAR_PRED) | |
22229 | { | |
22230 | /* Case 2: In an IT block, with a VPT code: error: must be in a | |
22231 | VPT block. */ | |
22232 | inst.error = BAD_OUT_VPT; | |
22233 | return FAIL; | |
22234 | } | |
22235 | /* Case 5: In a VPT block, with a VPT code: OK! */ | |
22236 | else if (cond != inst.cond) | |
22237 | { | |
22238 | inst.error = BAD_VPT_COND; | |
22239 | return FAIL; | |
22240 | } | |
22241 | break; | |
e07e6e58 NC |
22242 | case INSIDE_IT_LAST_INSN: |
22243 | case IF_INSIDE_IT_LAST_INSN: | |
5ee91343 AV |
22244 | if (now_pred.type == VECTOR_PRED || inst.cond > COND_ALWAYS) |
22245 | { | |
22246 | /* Case 4: In a VPT block, with an IT code: syntax error. */ | |
22247 | /* Case 11: In an IT block, with a VPT code: syntax error. */ | |
22248 | inst.error = BAD_SYNTAX; | |
22249 | return FAIL; | |
22250 | } | |
22251 | else if (cond != inst.cond) | |
e07e6e58 NC |
22252 | { |
22253 | inst.error = BAD_IT_COND; | |
22254 | return FAIL; | |
22255 | } | |
22256 | if (!is_last) | |
22257 | { | |
22258 | inst.error = BAD_BRANCH; | |
22259 | return FAIL; | |
22260 | } | |
22261 | break; | |
22262 | ||
22263 | case NEUTRAL_IT_INSN: | |
5ee91343 AV |
22264 | /* The BKPT instruction is unconditional even in a IT or VPT |
22265 | block. */ | |
e07e6e58 NC |
22266 | break; |
22267 | ||
22268 | case IT_INSN: | |
5ee91343 AV |
22269 | if (now_pred.type == SCALAR_PRED) |
22270 | { | |
22271 | inst.error = BAD_IT_IT; | |
22272 | return FAIL; | |
22273 | } | |
22274 | /* fall through. */ | |
22275 | case VPT_INSN: | |
22276 | if (inst.cond == COND_ALWAYS) | |
22277 | { | |
22278 | /* Executing a VPT/VPST instruction inside an IT block or a | |
22279 | VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE. | |
22280 | */ | |
22281 | if (now_pred.type == SCALAR_PRED) | |
22282 | as_tsktsk (MVE_NOT_IT); | |
22283 | else | |
22284 | as_tsktsk (MVE_NOT_VPT); | |
22285 | return SUCCESS; | |
22286 | } | |
22287 | else | |
22288 | { | |
22289 | /* VPT/VPST do not accept condition codes. */ | |
22290 | inst.error = BAD_SYNTAX; | |
22291 | return FAIL; | |
22292 | } | |
e07e6e58 | 22293 | } |
5ee91343 | 22294 | } |
e07e6e58 NC |
22295 | break; |
22296 | } | |
22297 | ||
22298 | return SUCCESS; | |
22299 | } | |
22300 | ||
5a01bb1d MGD |
22301 | struct depr_insn_mask |
22302 | { | |
22303 | unsigned long pattern; | |
22304 | unsigned long mask; | |
22305 | const char* description; | |
22306 | }; | |
22307 | ||
22308 | /* List of 16-bit instruction patterns deprecated in an IT block in | |
22309 | ARMv8. */ | |
22310 | static const struct depr_insn_mask depr_it_insns[] = { | |
22311 | { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") }, | |
22312 | { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") }, | |
22313 | { 0xa000, 0xb800, N_("ADR") }, | |
22314 | { 0x4800, 0xf800, N_("Literal loads") }, | |
22315 | { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") }, | |
22316 | { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") }, | |
c8de034b JW |
22317 | /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue' |
22318 | field in asm_opcode. 'tvalue' is used at the stage this check happen. */ | |
22319 | { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") }, | |
5a01bb1d MGD |
22320 | { 0, 0, NULL } |
22321 | }; | |
22322 | ||
e07e6e58 NC |
22323 | static void |
22324 | it_fsm_post_encode (void) | |
22325 | { | |
22326 | int is_last; | |
22327 | ||
5ee91343 AV |
22328 | if (!now_pred.state_handled) |
22329 | handle_pred_state (); | |
e07e6e58 | 22330 | |
5ee91343 AV |
22331 | if (now_pred.insn_cond |
22332 | && !now_pred.warn_deprecated | |
5a01bb1d | 22333 | && warn_on_deprecated |
df9909b8 TP |
22334 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8) |
22335 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m)) | |
5a01bb1d MGD |
22336 | { |
22337 | if (inst.instruction >= 0x10000) | |
22338 | { | |
5c3696f8 | 22339 | as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are " |
df9909b8 | 22340 | "performance deprecated in ARMv8-A and ARMv8-R")); |
5ee91343 | 22341 | now_pred.warn_deprecated = TRUE; |
5a01bb1d MGD |
22342 | } |
22343 | else | |
22344 | { | |
22345 | const struct depr_insn_mask *p = depr_it_insns; | |
22346 | ||
22347 | while (p->mask != 0) | |
22348 | { | |
22349 | if ((inst.instruction & p->mask) == p->pattern) | |
22350 | { | |
df9909b8 TP |
22351 | as_tsktsk (_("IT blocks containing 16-bit Thumb " |
22352 | "instructions of the following class are " | |
22353 | "performance deprecated in ARMv8-A and " | |
22354 | "ARMv8-R: %s"), p->description); | |
5ee91343 | 22355 | now_pred.warn_deprecated = TRUE; |
5a01bb1d MGD |
22356 | break; |
22357 | } | |
22358 | ||
22359 | ++p; | |
22360 | } | |
22361 | } | |
22362 | ||
5ee91343 | 22363 | if (now_pred.block_length > 1) |
5a01bb1d | 22364 | { |
5c3696f8 | 22365 | as_tsktsk (_("IT blocks containing more than one conditional " |
df9909b8 TP |
22366 | "instruction are performance deprecated in ARMv8-A and " |
22367 | "ARMv8-R")); | |
5ee91343 | 22368 | now_pred.warn_deprecated = TRUE; |
5a01bb1d MGD |
22369 | } |
22370 | } | |
22371 | ||
5ee91343 AV |
22372 | is_last = (now_pred.mask == 0x10); |
22373 | if (is_last) | |
22374 | { | |
22375 | now_pred.state = OUTSIDE_PRED_BLOCK; | |
22376 | now_pred.mask = 0; | |
22377 | } | |
e07e6e58 NC |
22378 | } |
22379 | ||
22380 | static void | |
22381 | force_automatic_it_block_close (void) | |
22382 | { | |
5ee91343 | 22383 | if (now_pred.state == AUTOMATIC_PRED_BLOCK) |
e07e6e58 NC |
22384 | { |
22385 | close_automatic_it_block (); | |
5ee91343 AV |
22386 | now_pred.state = OUTSIDE_PRED_BLOCK; |
22387 | now_pred.mask = 0; | |
e07e6e58 NC |
22388 | } |
22389 | } | |
22390 | ||
22391 | static int | |
5ee91343 | 22392 | in_pred_block (void) |
e07e6e58 | 22393 | { |
5ee91343 AV |
22394 | if (!now_pred.state_handled) |
22395 | handle_pred_state (); | |
e07e6e58 | 22396 | |
5ee91343 | 22397 | return now_pred.state != OUTSIDE_PRED_BLOCK; |
e07e6e58 NC |
22398 | } |
22399 | ||
ff8646ee TP |
22400 | /* Whether OPCODE only has T32 encoding. Since this function is only used by |
22401 | t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed | |
22402 | here, hence the "known" in the function name. */ | |
fc289b0a TP |
22403 | |
22404 | static bfd_boolean | |
ff8646ee | 22405 | known_t32_only_insn (const struct asm_opcode *opcode) |
fc289b0a TP |
22406 | { |
22407 | /* Original Thumb-1 wide instruction. */ | |
22408 | if (opcode->tencode == do_t_blx | |
22409 | || opcode->tencode == do_t_branch23 | |
22410 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) | |
22411 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)) | |
22412 | return TRUE; | |
22413 | ||
16a1fa25 TP |
22414 | /* Wide-only instruction added to ARMv8-M Baseline. */ |
22415 | if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m_m_only) | |
ff8646ee TP |
22416 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics) |
22417 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m) | |
22418 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div)) | |
22419 | return TRUE; | |
22420 | ||
22421 | return FALSE; | |
22422 | } | |
22423 | ||
22424 | /* Whether wide instruction variant can be used if available for a valid OPCODE | |
22425 | in ARCH. */ | |
22426 | ||
22427 | static bfd_boolean | |
22428 | t32_insn_ok (arm_feature_set arch, const struct asm_opcode *opcode) | |
22429 | { | |
22430 | if (known_t32_only_insn (opcode)) | |
22431 | return TRUE; | |
22432 | ||
22433 | /* Instruction with narrow and wide encoding added to ARMv8-M. Availability | |
22434 | of variant T3 of B.W is checked in do_t_branch. */ | |
22435 | if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m) | |
22436 | && opcode->tencode == do_t_branch) | |
22437 | return TRUE; | |
22438 | ||
bada4342 JW |
22439 | /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */ |
22440 | if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m) | |
22441 | && opcode->tencode == do_t_mov_cmp | |
22442 | /* Make sure CMP instruction is not affected. */ | |
22443 | && opcode->aencode == do_mov) | |
22444 | return TRUE; | |
22445 | ||
ff8646ee TP |
22446 | /* Wide instruction variants of all instructions with narrow *and* wide |
22447 | variants become available with ARMv6t2. Other opcodes are either | |
22448 | narrow-only or wide-only and are thus available if OPCODE is valid. */ | |
22449 | if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v6t2)) | |
22450 | return TRUE; | |
22451 | ||
22452 | /* OPCODE with narrow only instruction variant or wide variant not | |
22453 | available. */ | |
fc289b0a TP |
22454 | return FALSE; |
22455 | } | |
22456 | ||
c19d1205 ZW |
22457 | void |
22458 | md_assemble (char *str) | |
b99bd4ef | 22459 | { |
c19d1205 ZW |
22460 | char *p = str; |
22461 | const struct asm_opcode * opcode; | |
b99bd4ef | 22462 | |
c19d1205 ZW |
22463 | /* Align the previous label if needed. */ |
22464 | if (last_label_seen != NULL) | |
b99bd4ef | 22465 | { |
c19d1205 ZW |
22466 | symbol_set_frag (last_label_seen, frag_now); |
22467 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
22468 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
22469 | } |
22470 | ||
c19d1205 | 22471 | memset (&inst, '\0', sizeof (inst)); |
e2b0ab59 AV |
22472 | int r; |
22473 | for (r = 0; r < ARM_IT_MAX_RELOCS; r++) | |
22474 | inst.relocs[r].type = BFD_RELOC_UNUSED; | |
b99bd4ef | 22475 | |
c19d1205 ZW |
22476 | opcode = opcode_lookup (&p); |
22477 | if (!opcode) | |
b99bd4ef | 22478 | { |
c19d1205 | 22479 | /* It wasn't an instruction, but it might be a register alias of |
dcbf9037 | 22480 | the form alias .req reg, or a Neon .dn/.qn directive. */ |
c921be7d | 22481 | if (! create_register_alias (str, p) |
477330fc | 22482 | && ! create_neon_reg_alias (str, p)) |
c19d1205 | 22483 | as_bad (_("bad instruction `%s'"), str); |
b99bd4ef | 22484 | |
b99bd4ef NC |
22485 | return; |
22486 | } | |
22487 | ||
278df34e | 22488 | if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated) |
5c3696f8 | 22489 | as_tsktsk (_("s suffix on comparison instruction is deprecated")); |
088fa78e | 22490 | |
037e8744 JB |
22491 | /* The value which unconditional instructions should have in place of the |
22492 | condition field. */ | |
22493 | inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; | |
22494 | ||
c19d1205 | 22495 | if (thumb_mode) |
b99bd4ef | 22496 | { |
e74cfd16 | 22497 | arm_feature_set variant; |
8f06b2d8 PB |
22498 | |
22499 | variant = cpu_variant; | |
22500 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
e74cfd16 PB |
22501 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
22502 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); | |
c19d1205 | 22503 | /* Check that this instruction is supported for this CPU. */ |
62b3e311 PB |
22504 | if (!opcode->tvariant |
22505 | || (thumb_mode == 1 | |
22506 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) | |
b99bd4ef | 22507 | { |
173205ca TP |
22508 | if (opcode->tencode == do_t_swi) |
22509 | as_bad (_("SVC is not permitted on this architecture")); | |
22510 | else | |
22511 | as_bad (_("selected processor does not support `%s' in Thumb mode"), str); | |
b99bd4ef NC |
22512 | return; |
22513 | } | |
c19d1205 ZW |
22514 | if (inst.cond != COND_ALWAYS && !unified_syntax |
22515 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 22516 | { |
c19d1205 | 22517 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
22518 | return; |
22519 | } | |
22520 | ||
fc289b0a TP |
22521 | /* Two things are addressed here: |
22522 | 1) Implicit require narrow instructions on Thumb-1. | |
22523 | This avoids relaxation accidentally introducing Thumb-2 | |
22524 | instructions. | |
22525 | 2) Reject wide instructions in non Thumb-2 cores. | |
22526 | ||
22527 | Only instructions with narrow and wide variants need to be handled | |
22528 | but selecting all non wide-only instructions is easier. */ | |
22529 | if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) | |
ff8646ee | 22530 | && !t32_insn_ok (variant, opcode)) |
076d447c | 22531 | { |
fc289b0a TP |
22532 | if (inst.size_req == 0) |
22533 | inst.size_req = 2; | |
22534 | else if (inst.size_req == 4) | |
752d5da4 | 22535 | { |
ff8646ee TP |
22536 | if (ARM_CPU_HAS_FEATURE (variant, arm_ext_v8m)) |
22537 | as_bad (_("selected processor does not support 32bit wide " | |
22538 | "variant of instruction `%s'"), str); | |
22539 | else | |
22540 | as_bad (_("selected processor does not support `%s' in " | |
22541 | "Thumb-2 mode"), str); | |
fc289b0a | 22542 | return; |
752d5da4 | 22543 | } |
076d447c PB |
22544 | } |
22545 | ||
c19d1205 ZW |
22546 | inst.instruction = opcode->tvalue; |
22547 | ||
5be8be5d | 22548 | if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE)) |
477330fc | 22549 | { |
5ee91343 | 22550 | /* Prepare the pred_insn_type for those encodings that don't set |
477330fc RM |
22551 | it. */ |
22552 | it_fsm_pre_encode (); | |
c19d1205 | 22553 | |
477330fc | 22554 | opcode->tencode (); |
e07e6e58 | 22555 | |
477330fc RM |
22556 | it_fsm_post_encode (); |
22557 | } | |
e27ec89e | 22558 | |
0110f2b8 | 22559 | if (!(inst.error || inst.relax)) |
b99bd4ef | 22560 | { |
9c2799c2 | 22561 | gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
c19d1205 ZW |
22562 | inst.size = (inst.instruction > 0xffff ? 4 : 2); |
22563 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 22564 | { |
c19d1205 | 22565 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
22566 | return; |
22567 | } | |
22568 | } | |
076d447c PB |
22569 | |
22570 | /* Something has gone badly wrong if we try to relax a fixed size | |
477330fc | 22571 | instruction. */ |
9c2799c2 | 22572 | gas_assert (inst.size_req == 0 || !inst.relax); |
076d447c | 22573 | |
e74cfd16 PB |
22574 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
22575 | *opcode->tvariant); | |
ee065d83 | 22576 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
fc289b0a TP |
22577 | set those bits when Thumb-2 32-bit instructions are seen. The impact |
22578 | of relaxable instructions will be considered later after we finish all | |
22579 | relaxation. */ | |
ff8646ee TP |
22580 | if (ARM_FEATURE_CORE_EQUAL (cpu_variant, arm_arch_any)) |
22581 | variant = arm_arch_none; | |
22582 | else | |
22583 | variant = cpu_variant; | |
22584 | if (inst.size == 4 && !t32_insn_ok (variant, opcode)) | |
e74cfd16 PB |
22585 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
22586 | arm_ext_v6t2); | |
cd000bff | 22587 | |
88714cb8 DG |
22588 | check_neon_suffixes; |
22589 | ||
cd000bff | 22590 | if (!inst.error) |
c877a2f2 NC |
22591 | { |
22592 | mapping_state (MAP_THUMB); | |
22593 | } | |
c19d1205 | 22594 | } |
3e9e4fcf | 22595 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 | 22596 | { |
845b51d6 PB |
22597 | bfd_boolean is_bx; |
22598 | ||
22599 | /* bx is allowed on v5 cores, and sometimes on v4 cores. */ | |
22600 | is_bx = (opcode->aencode == do_bx); | |
22601 | ||
c19d1205 | 22602 | /* Check that this instruction is supported for this CPU. */ |
845b51d6 PB |
22603 | if (!(is_bx && fix_v4bx) |
22604 | && !(opcode->avariant && | |
22605 | ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))) | |
b99bd4ef | 22606 | { |
84b52b66 | 22607 | as_bad (_("selected processor does not support `%s' in ARM mode"), str); |
c19d1205 | 22608 | return; |
b99bd4ef | 22609 | } |
c19d1205 | 22610 | if (inst.size_req) |
b99bd4ef | 22611 | { |
c19d1205 ZW |
22612 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
22613 | return; | |
b99bd4ef NC |
22614 | } |
22615 | ||
c19d1205 ZW |
22616 | inst.instruction = opcode->avalue; |
22617 | if (opcode->tag == OT_unconditionalF) | |
eff0bc54 | 22618 | inst.instruction |= 0xFU << 28; |
c19d1205 ZW |
22619 | else |
22620 | inst.instruction |= inst.cond << 28; | |
22621 | inst.size = INSN_SIZE; | |
5be8be5d | 22622 | if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE)) |
477330fc RM |
22623 | { |
22624 | it_fsm_pre_encode (); | |
22625 | opcode->aencode (); | |
22626 | it_fsm_post_encode (); | |
22627 | } | |
ee065d83 | 22628 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
477330fc | 22629 | on a hypothetical non-thumb v5 core. */ |
845b51d6 | 22630 | if (is_bx) |
e74cfd16 | 22631 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); |
ee065d83 | 22632 | else |
e74cfd16 PB |
22633 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
22634 | *opcode->avariant); | |
88714cb8 DG |
22635 | |
22636 | check_neon_suffixes; | |
22637 | ||
cd000bff | 22638 | if (!inst.error) |
c877a2f2 NC |
22639 | { |
22640 | mapping_state (MAP_ARM); | |
22641 | } | |
b99bd4ef | 22642 | } |
3e9e4fcf JB |
22643 | else |
22644 | { | |
22645 | as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " | |
22646 | "-- `%s'"), str); | |
22647 | return; | |
22648 | } | |
c19d1205 ZW |
22649 | output_inst (str); |
22650 | } | |
b99bd4ef | 22651 | |
e07e6e58 | 22652 | static void |
5ee91343 | 22653 | check_pred_blocks_finished (void) |
e07e6e58 NC |
22654 | { |
22655 | #ifdef OBJ_ELF | |
22656 | asection *sect; | |
22657 | ||
22658 | for (sect = stdoutput->sections; sect != NULL; sect = sect->next) | |
5ee91343 AV |
22659 | if (seg_info (sect)->tc_segment_info_data.current_pred.state |
22660 | == MANUAL_PRED_BLOCK) | |
e07e6e58 | 22661 | { |
5ee91343 AV |
22662 | if (now_pred.type == SCALAR_PRED) |
22663 | as_warn (_("section '%s' finished with an open IT block."), | |
22664 | sect->name); | |
22665 | else | |
22666 | as_warn (_("section '%s' finished with an open VPT/VPST block."), | |
22667 | sect->name); | |
e07e6e58 NC |
22668 | } |
22669 | #else | |
5ee91343 AV |
22670 | if (now_pred.state == MANUAL_PRED_BLOCK) |
22671 | { | |
22672 | if (now_pred.type == SCALAR_PRED) | |
22673 | as_warn (_("file finished with an open IT block.")); | |
22674 | else | |
22675 | as_warn (_("file finished with an open VPT/VPST block.")); | |
22676 | } | |
e07e6e58 NC |
22677 | #endif |
22678 | } | |
22679 | ||
c19d1205 ZW |
22680 | /* Various frobbings of labels and their addresses. */ |
22681 | ||
22682 | void | |
22683 | arm_start_line_hook (void) | |
22684 | { | |
22685 | last_label_seen = NULL; | |
b99bd4ef NC |
22686 | } |
22687 | ||
c19d1205 ZW |
22688 | void |
22689 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 22690 | { |
c19d1205 | 22691 | last_label_seen = sym; |
b99bd4ef | 22692 | |
c19d1205 | 22693 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 22694 | |
c19d1205 ZW |
22695 | #if defined OBJ_COFF || defined OBJ_ELF |
22696 | ARM_SET_INTERWORK (sym, support_interwork); | |
22697 | #endif | |
b99bd4ef | 22698 | |
e07e6e58 NC |
22699 | force_automatic_it_block_close (); |
22700 | ||
5f4273c7 | 22701 | /* Note - do not allow local symbols (.Lxxx) to be labelled |
c19d1205 ZW |
22702 | as Thumb functions. This is because these labels, whilst |
22703 | they exist inside Thumb code, are not the entry points for | |
22704 | possible ARM->Thumb calls. Also, these labels can be used | |
22705 | as part of a computed goto or switch statement. eg gcc | |
22706 | can generate code that looks like this: | |
b99bd4ef | 22707 | |
c19d1205 ZW |
22708 | ldr r2, [pc, .Laaa] |
22709 | lsl r3, r3, #2 | |
22710 | ldr r2, [r3, r2] | |
22711 | mov pc, r2 | |
b99bd4ef | 22712 | |
c19d1205 ZW |
22713 | .Lbbb: .word .Lxxx |
22714 | .Lccc: .word .Lyyy | |
22715 | ..etc... | |
22716 | .Laaa: .word Lbbb | |
b99bd4ef | 22717 | |
c19d1205 ZW |
22718 | The first instruction loads the address of the jump table. |
22719 | The second instruction converts a table index into a byte offset. | |
22720 | The third instruction gets the jump address out of the table. | |
22721 | The fourth instruction performs the jump. | |
b99bd4ef | 22722 | |
c19d1205 ZW |
22723 | If the address stored at .Laaa is that of a symbol which has the |
22724 | Thumb_Func bit set, then the linker will arrange for this address | |
22725 | to have the bottom bit set, which in turn would mean that the | |
22726 | address computation performed by the third instruction would end | |
22727 | up with the bottom bit set. Since the ARM is capable of unaligned | |
22728 | word loads, the instruction would then load the incorrect address | |
22729 | out of the jump table, and chaos would ensue. */ | |
22730 | if (label_is_thumb_function_name | |
22731 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
22732 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 22733 | { |
c19d1205 ZW |
22734 | /* When the address of a Thumb function is taken the bottom |
22735 | bit of that address should be set. This will allow | |
22736 | interworking between Arm and Thumb functions to work | |
22737 | correctly. */ | |
b99bd4ef | 22738 | |
c19d1205 | 22739 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 22740 | |
c19d1205 | 22741 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 22742 | } |
07a53e5c | 22743 | |
07a53e5c | 22744 | dwarf2_emit_label (sym); |
b99bd4ef NC |
22745 | } |
22746 | ||
c921be7d | 22747 | bfd_boolean |
c19d1205 | 22748 | arm_data_in_code (void) |
b99bd4ef | 22749 | { |
c19d1205 | 22750 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 22751 | { |
c19d1205 ZW |
22752 | *input_line_pointer = '/'; |
22753 | input_line_pointer += 5; | |
22754 | *input_line_pointer = 0; | |
c921be7d | 22755 | return TRUE; |
b99bd4ef NC |
22756 | } |
22757 | ||
c921be7d | 22758 | return FALSE; |
b99bd4ef NC |
22759 | } |
22760 | ||
c19d1205 ZW |
22761 | char * |
22762 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 22763 | { |
c19d1205 | 22764 | int len; |
b99bd4ef | 22765 | |
c19d1205 ZW |
22766 | if (thumb_mode && (len = strlen (name)) > 5 |
22767 | && streq (name + len - 5, "/data")) | |
22768 | *(name + len - 5) = 0; | |
b99bd4ef | 22769 | |
c19d1205 | 22770 | return name; |
b99bd4ef | 22771 | } |
c19d1205 ZW |
22772 | \f |
22773 | /* Table of all register names defined by default. The user can | |
22774 | define additional names with .req. Note that all register names | |
22775 | should appear in both upper and lowercase variants. Some registers | |
22776 | also have mixed-case names. */ | |
b99bd4ef | 22777 | |
dcbf9037 | 22778 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } |
c19d1205 | 22779 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) |
5287ad62 | 22780 | #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) |
c19d1205 ZW |
22781 | #define REGSET(p,t) \ |
22782 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
22783 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
22784 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
22785 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
5287ad62 JB |
22786 | #define REGSETH(p,t) \ |
22787 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ | |
22788 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ | |
22789 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ | |
22790 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) | |
22791 | #define REGSET2(p,t) \ | |
22792 | REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ | |
22793 | REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ | |
22794 | REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ | |
22795 | REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) | |
90ec0d68 MGD |
22796 | #define SPLRBANK(base,bank,t) \ |
22797 | REGDEF(lr_##bank, 768|((base+0)<<16), t), \ | |
22798 | REGDEF(sp_##bank, 768|((base+1)<<16), t), \ | |
22799 | REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \ | |
22800 | REGDEF(LR_##bank, 768|((base+0)<<16), t), \ | |
22801 | REGDEF(SP_##bank, 768|((base+1)<<16), t), \ | |
22802 | REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t) | |
7ed4c4c5 | 22803 | |
c19d1205 | 22804 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 22805 | { |
c19d1205 ZW |
22806 | /* ARM integer registers. */ |
22807 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 22808 | |
c19d1205 ZW |
22809 | /* ATPCS synonyms. */ |
22810 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
22811 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
22812 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 22813 | |
c19d1205 ZW |
22814 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
22815 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
22816 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 22817 | |
c19d1205 ZW |
22818 | /* Well-known aliases. */ |
22819 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
22820 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
22821 | ||
22822 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
22823 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
22824 | ||
1b883319 AV |
22825 | /* Defining the new Zero register from ARMv8.1-M. */ |
22826 | REGDEF(zr,15,ZR), | |
22827 | REGDEF(ZR,15,ZR), | |
22828 | ||
c19d1205 ZW |
22829 | /* Coprocessor numbers. */ |
22830 | REGSET(p, CP), REGSET(P, CP), | |
22831 | ||
22832 | /* Coprocessor register numbers. The "cr" variants are for backward | |
22833 | compatibility. */ | |
22834 | REGSET(c, CN), REGSET(C, CN), | |
22835 | REGSET(cr, CN), REGSET(CR, CN), | |
22836 | ||
90ec0d68 MGD |
22837 | /* ARM banked registers. */ |
22838 | REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB), | |
22839 | REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB), | |
22840 | REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB), | |
22841 | REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB), | |
22842 | REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB), | |
22843 | REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB), | |
22844 | REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB), | |
22845 | ||
22846 | REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB), | |
22847 | REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB), | |
22848 | REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB), | |
22849 | REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB), | |
22850 | REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB), | |
1472d06f | 22851 | REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB), |
90ec0d68 MGD |
22852 | REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB), |
22853 | REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB), | |
22854 | ||
22855 | SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB), | |
22856 | SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB), | |
22857 | SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB), | |
22858 | SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB), | |
22859 | SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB), | |
22860 | REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB), | |
22861 | REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB), | |
fa94de6b | 22862 | REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB), |
90ec0d68 MGD |
22863 | REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB), |
22864 | ||
c19d1205 ZW |
22865 | /* FPA registers. */ |
22866 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
22867 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
22868 | ||
22869 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
22870 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
22871 | ||
22872 | /* VFP SP registers. */ | |
5287ad62 JB |
22873 | REGSET(s,VFS), REGSET(S,VFS), |
22874 | REGSETH(s,VFS), REGSETH(S,VFS), | |
c19d1205 ZW |
22875 | |
22876 | /* VFP DP Registers. */ | |
5287ad62 JB |
22877 | REGSET(d,VFD), REGSET(D,VFD), |
22878 | /* Extra Neon DP registers. */ | |
22879 | REGSETH(d,VFD), REGSETH(D,VFD), | |
22880 | ||
22881 | /* Neon QP registers. */ | |
22882 | REGSET2(q,NQ), REGSET2(Q,NQ), | |
c19d1205 ZW |
22883 | |
22884 | /* VFP control registers. */ | |
22885 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
22886 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
cd2cf30b PB |
22887 | REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), |
22888 | REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), | |
22889 | REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), | |
22890 | REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), | |
40c7d507 | 22891 | REGDEF(mvfr2,5,VFC), REGDEF(MVFR2,5,VFC), |
ba6cd17f SD |
22892 | REGDEF(fpscr_nzcvqc,2,VFC), REGDEF(FPSCR_nzcvqc,2,VFC), |
22893 | REGDEF(vpr,12,VFC), REGDEF(VPR,12,VFC), | |
22894 | REGDEF(fpcxt_ns,14,VFC), REGDEF(FPCXT_NS,14,VFC), | |
22895 | REGDEF(fpcxt_s,15,VFC), REGDEF(FPCXT_S,15,VFC), | |
c19d1205 ZW |
22896 | |
22897 | /* Maverick DSP coprocessor registers. */ | |
22898 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
22899 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
22900 | ||
22901 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
22902 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
22903 | REGDEF(dspsc,0,DSPSC), | |
22904 | ||
22905 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
22906 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
22907 | REGDEF(DSPSC,0,DSPSC), | |
22908 | ||
22909 | /* iWMMXt data registers - p0, c0-15. */ | |
22910 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
22911 | ||
22912 | /* iWMMXt control registers - p1, c0-3. */ | |
22913 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
22914 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
22915 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
22916 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
22917 | ||
22918 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
22919 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
22920 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
22921 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
22922 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
22923 | ||
22924 | /* XScale accumulator registers. */ | |
22925 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
22926 | }; | |
22927 | #undef REGDEF | |
22928 | #undef REGNUM | |
22929 | #undef REGSET | |
7ed4c4c5 | 22930 | |
c19d1205 ZW |
22931 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
22932 | within psr_required_here. */ | |
22933 | static const struct asm_psr psrs[] = | |
22934 | { | |
22935 | /* Backward compatibility notation. Note that "all" is no longer | |
22936 | truly all possible PSR bits. */ | |
22937 | {"all", PSR_c | PSR_f}, | |
22938 | {"flg", PSR_f}, | |
22939 | {"ctl", PSR_c}, | |
22940 | ||
22941 | /* Individual flags. */ | |
22942 | {"f", PSR_f}, | |
22943 | {"c", PSR_c}, | |
22944 | {"x", PSR_x}, | |
22945 | {"s", PSR_s}, | |
59b42a0d | 22946 | |
c19d1205 ZW |
22947 | /* Combinations of flags. */ |
22948 | {"fs", PSR_f | PSR_s}, | |
22949 | {"fx", PSR_f | PSR_x}, | |
22950 | {"fc", PSR_f | PSR_c}, | |
22951 | {"sf", PSR_s | PSR_f}, | |
22952 | {"sx", PSR_s | PSR_x}, | |
22953 | {"sc", PSR_s | PSR_c}, | |
22954 | {"xf", PSR_x | PSR_f}, | |
22955 | {"xs", PSR_x | PSR_s}, | |
22956 | {"xc", PSR_x | PSR_c}, | |
22957 | {"cf", PSR_c | PSR_f}, | |
22958 | {"cs", PSR_c | PSR_s}, | |
22959 | {"cx", PSR_c | PSR_x}, | |
22960 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
22961 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
22962 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
22963 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
22964 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
22965 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
22966 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
22967 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
22968 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
22969 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
22970 | {"scf", PSR_s | PSR_c | PSR_f}, | |
22971 | {"scx", PSR_s | PSR_c | PSR_x}, | |
22972 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
22973 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
22974 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
22975 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
22976 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
22977 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
22978 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
22979 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
22980 | {"csf", PSR_c | PSR_s | PSR_f}, | |
22981 | {"csx", PSR_c | PSR_s | PSR_x}, | |
22982 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
22983 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
22984 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
22985 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
22986 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
22987 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
22988 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
22989 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
22990 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
22991 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
22992 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
22993 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
22994 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
22995 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
22996 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
22997 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
22998 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
22999 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
23000 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
23001 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
23002 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
23003 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
23004 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
23005 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
23006 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
23007 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
23008 | }; | |
23009 | ||
62b3e311 PB |
23010 | /* Table of V7M psr names. */ |
23011 | static const struct asm_psr v7m_psrs[] = | |
23012 | { | |
1a336194 TP |
23013 | {"apsr", 0x0 }, {"APSR", 0x0 }, |
23014 | {"iapsr", 0x1 }, {"IAPSR", 0x1 }, | |
23015 | {"eapsr", 0x2 }, {"EAPSR", 0x2 }, | |
23016 | {"psr", 0x3 }, {"PSR", 0x3 }, | |
23017 | {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 }, | |
23018 | {"ipsr", 0x5 }, {"IPSR", 0x5 }, | |
23019 | {"epsr", 0x6 }, {"EPSR", 0x6 }, | |
23020 | {"iepsr", 0x7 }, {"IEPSR", 0x7 }, | |
23021 | {"msp", 0x8 }, {"MSP", 0x8 }, | |
23022 | {"psp", 0x9 }, {"PSP", 0x9 }, | |
23023 | {"msplim", 0xa }, {"MSPLIM", 0xa }, | |
23024 | {"psplim", 0xb }, {"PSPLIM", 0xb }, | |
23025 | {"primask", 0x10}, {"PRIMASK", 0x10}, | |
23026 | {"basepri", 0x11}, {"BASEPRI", 0x11}, | |
23027 | {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12}, | |
1a336194 TP |
23028 | {"faultmask", 0x13}, {"FAULTMASK", 0x13}, |
23029 | {"control", 0x14}, {"CONTROL", 0x14}, | |
23030 | {"msp_ns", 0x88}, {"MSP_NS", 0x88}, | |
23031 | {"psp_ns", 0x89}, {"PSP_NS", 0x89}, | |
23032 | {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a}, | |
23033 | {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b}, | |
23034 | {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90}, | |
23035 | {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91}, | |
23036 | {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93}, | |
23037 | {"control_ns", 0x94}, {"CONTROL_NS", 0x94}, | |
23038 | {"sp_ns", 0x98}, {"SP_NS", 0x98 } | |
62b3e311 PB |
23039 | }; |
23040 | ||
c19d1205 ZW |
23041 | /* Table of all shift-in-operand names. */ |
23042 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 23043 | { |
c19d1205 ZW |
23044 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
23045 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
23046 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
23047 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
23048 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
f5f10c66 AV |
23049 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }, |
23050 | { "uxtw", SHIFT_UXTW}, { "UXTW", SHIFT_UXTW} | |
c19d1205 | 23051 | }; |
b99bd4ef | 23052 | |
c19d1205 ZW |
23053 | /* Table of all explicit relocation names. */ |
23054 | #ifdef OBJ_ELF | |
23055 | static struct reloc_entry reloc_names[] = | |
23056 | { | |
23057 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
23058 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
23059 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
23060 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
23061 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
23062 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
23063 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
23064 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
23065 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
23066 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
b43420e6 | 23067 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}, |
0855e32b NS |
23068 | { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL}, |
23069 | { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC}, | |
477330fc | 23070 | { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC}, |
0855e32b | 23071 | { "tlscall", BFD_RELOC_ARM_TLS_CALL}, |
477330fc | 23072 | { "TLSCALL", BFD_RELOC_ARM_TLS_CALL}, |
0855e32b | 23073 | { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ}, |
188fd7ae CL |
23074 | { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}, |
23075 | { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC }, | |
23076 | { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC }, | |
23077 | { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC }, | |
23078 | { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC }, | |
23079 | { "funcdesc", BFD_RELOC_ARM_FUNCDESC }, | |
5c5a4843 CL |
23080 | { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC }, |
23081 | { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC }, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC }, | |
23082 | { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC }, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC }, | |
23083 | { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC }, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC }, | |
c19d1205 ZW |
23084 | }; |
23085 | #endif | |
b99bd4ef | 23086 | |
5ee91343 | 23087 | /* Table of all conditional affixes. */ |
c19d1205 ZW |
23088 | static const struct asm_cond conds[] = |
23089 | { | |
23090 | {"eq", 0x0}, | |
23091 | {"ne", 0x1}, | |
23092 | {"cs", 0x2}, {"hs", 0x2}, | |
23093 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
23094 | {"mi", 0x4}, | |
23095 | {"pl", 0x5}, | |
23096 | {"vs", 0x6}, | |
23097 | {"vc", 0x7}, | |
23098 | {"hi", 0x8}, | |
23099 | {"ls", 0x9}, | |
23100 | {"ge", 0xa}, | |
23101 | {"lt", 0xb}, | |
23102 | {"gt", 0xc}, | |
23103 | {"le", 0xd}, | |
23104 | {"al", 0xe} | |
23105 | }; | |
5ee91343 AV |
23106 | static const struct asm_cond vconds[] = |
23107 | { | |
23108 | {"t", 0xf}, | |
23109 | {"e", 0x10} | |
23110 | }; | |
bfae80f2 | 23111 | |
e797f7e0 | 23112 | #define UL_BARRIER(L,U,CODE,FEAT) \ |
823d2571 TG |
23113 | { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \ |
23114 | { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) } | |
e797f7e0 | 23115 | |
62b3e311 PB |
23116 | static struct asm_barrier_opt barrier_opt_names[] = |
23117 | { | |
e797f7e0 MGD |
23118 | UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER), |
23119 | UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER), | |
23120 | UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8), | |
23121 | UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER), | |
23122 | UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER), | |
23123 | UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER), | |
23124 | UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER), | |
23125 | UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8), | |
23126 | UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER), | |
23127 | UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER), | |
23128 | UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER), | |
23129 | UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER), | |
23130 | UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8), | |
23131 | UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER), | |
23132 | UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER), | |
23133 | UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8) | |
62b3e311 PB |
23134 | }; |
23135 | ||
e797f7e0 MGD |
23136 | #undef UL_BARRIER |
23137 | ||
c19d1205 ZW |
23138 | /* Table of ARM-format instructions. */ |
23139 | ||
23140 | /* Macros for gluing together operand strings. N.B. In all cases | |
23141 | other than OPS0, the trailing OP_stop comes from default | |
23142 | zero-initialization of the unspecified elements of the array. */ | |
23143 | #define OPS0() { OP_stop, } | |
23144 | #define OPS1(a) { OP_##a, } | |
23145 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
23146 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
23147 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
23148 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
23149 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
23150 | ||
5be8be5d DG |
23151 | /* These macros are similar to the OPSn, but do not prepend the OP_ prefix. |
23152 | This is useful when mixing operands for ARM and THUMB, i.e. using the | |
23153 | MIX_ARM_THUMB_OPERANDS macro. | |
23154 | In order to use these macros, prefix the number of operands with _ | |
23155 | e.g. _3. */ | |
23156 | #define OPS_1(a) { a, } | |
23157 | #define OPS_2(a,b) { a,b, } | |
23158 | #define OPS_3(a,b,c) { a,b,c, } | |
23159 | #define OPS_4(a,b,c,d) { a,b,c,d, } | |
23160 | #define OPS_5(a,b,c,d,e) { a,b,c,d,e, } | |
23161 | #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, } | |
23162 | ||
c19d1205 ZW |
23163 | /* These macros abstract out the exact format of the mnemonic table and |
23164 | save some repeated characters. */ | |
23165 | ||
23166 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
23167 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 23168 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ |
5ee91343 | 23169 | THUMB_VARIANT, do_##ae, do_##te, 0 } |
c19d1205 ZW |
23170 | |
23171 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
23172 | a T_MNEM_xyz enumerator. */ | |
23173 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
e07e6e58 | 23174 | TxCE (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 23175 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 23176 | TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
23177 | |
23178 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
23179 | infix after the third character. */ | |
23180 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 23181 | { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ |
5ee91343 | 23182 | THUMB_VARIANT, do_##ae, do_##te, 0 } |
088fa78e | 23183 | #define TxC3w(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 23184 | { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ |
5ee91343 | 23185 | THUMB_VARIANT, do_##ae, do_##te, 0 } |
c19d1205 | 23186 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 23187 | TxC3 (mnem, aop, 0x##top, nops, ops, ae, te) |
088fa78e | 23188 | #define TC3w(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 23189 | TxC3w (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 23190 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 23191 | TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
088fa78e | 23192 | #define tC3w(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 23193 | TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 | 23194 | |
c19d1205 | 23195 | /* Mnemonic that cannot be conditionalized. The ARM condition-code |
dfa9f0d5 PB |
23196 | field is still 0xE. Many of the Thumb variants can be executed |
23197 | conditionally, so this is checked separately. */ | |
c19d1205 | 23198 | #define TUE(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 23199 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ |
5ee91343 | 23200 | THUMB_VARIANT, do_##ae, do_##te, 0 } |
c19d1205 | 23201 | |
dd5181d5 KT |
23202 | /* Same as TUE but the encoding function for ARM and Thumb modes is the same. |
23203 | Used by mnemonics that have very minimal differences in the encoding for | |
23204 | ARM and Thumb variants and can be handled in a common function. */ | |
23205 | #define TUEc(mnem, op, top, nops, ops, en) \ | |
23206 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ | |
5ee91343 | 23207 | THUMB_VARIANT, do_##en, do_##en, 0 } |
dd5181d5 | 23208 | |
c19d1205 ZW |
23209 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM |
23210 | condition code field. */ | |
23211 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 23212 | { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ |
5ee91343 | 23213 | THUMB_VARIANT, do_##ae, do_##te, 0 } |
c19d1205 ZW |
23214 | |
23215 | /* ARM-only variants of all the above. */ | |
6a86118a | 23216 | #define CE(mnem, op, nops, ops, ae) \ |
5ee91343 | 23217 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 } |
6a86118a NC |
23218 | |
23219 | #define C3(mnem, op, nops, ops, ae) \ | |
5ee91343 | 23220 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 } |
6a86118a | 23221 | |
cf3cf39d TP |
23222 | /* Thumb-only variants of TCE and TUE. */ |
23223 | #define ToC(mnem, top, nops, ops, te) \ | |
23224 | { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \ | |
5ee91343 | 23225 | do_##te, 0 } |
cf3cf39d TP |
23226 | |
23227 | #define ToU(mnem, top, nops, ops, te) \ | |
23228 | { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \ | |
5ee91343 | 23229 | NULL, do_##te, 0 } |
cf3cf39d | 23230 | |
4389b29a AV |
23231 | /* T_MNEM_xyz enumerator variants of ToC. */ |
23232 | #define toC(mnem, top, nops, ops, te) \ | |
23233 | { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \ | |
5ee91343 | 23234 | do_##te, 0 } |
4389b29a | 23235 | |
f6b2b12d AV |
23236 | /* T_MNEM_xyz enumerator variants of ToU. */ |
23237 | #define toU(mnem, top, nops, ops, te) \ | |
23238 | { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \ | |
5ee91343 | 23239 | NULL, do_##te, 0 } |
f6b2b12d | 23240 | |
e3cb604e PB |
23241 | /* Legacy mnemonics that always have conditional infix after the third |
23242 | character. */ | |
23243 | #define CL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 23244 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
5ee91343 | 23245 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 } |
e3cb604e | 23246 | |
8f06b2d8 PB |
23247 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
23248 | #define cCE(mnem, op, nops, ops, ae) \ | |
5ee91343 | 23249 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 } |
8f06b2d8 | 23250 | |
57785aa2 AV |
23251 | /* mov instructions that are shared between coprocessor and MVE. */ |
23252 | #define mcCE(mnem, op, nops, ops, ae) \ | |
23253 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 } | |
23254 | ||
e3cb604e PB |
23255 | /* Legacy coprocessor instructions where conditional infix and conditional |
23256 | suffix are ambiguous. For consistency this includes all FPA instructions, | |
23257 | not just the potentially ambiguous ones. */ | |
23258 | #define cCL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 23259 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
5ee91343 | 23260 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 } |
e3cb604e PB |
23261 | |
23262 | /* Coprocessor, takes either a suffix or a position-3 infix | |
23263 | (for an FPA corner case). */ | |
23264 | #define C3E(mnem, op, nops, ops, ae) \ | |
21d799b5 | 23265 | { mnem, OPS##nops ops, OT_csuf_or_in3, \ |
5ee91343 | 23266 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 } |
8f06b2d8 | 23267 | |
6a86118a | 23268 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
21d799b5 NC |
23269 | { m1 #m2 m3, OPS##nops ops, \ |
23270 | sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ | |
5ee91343 | 23271 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 } |
6a86118a NC |
23272 | |
23273 | #define CM(m1, m2, op, nops, ops, ae) \ | |
e07e6e58 NC |
23274 | xCM_ (m1, , m2, op, nops, ops, ae), \ |
23275 | xCM_ (m1, eq, m2, op, nops, ops, ae), \ | |
23276 | xCM_ (m1, ne, m2, op, nops, ops, ae), \ | |
23277 | xCM_ (m1, cs, m2, op, nops, ops, ae), \ | |
23278 | xCM_ (m1, hs, m2, op, nops, ops, ae), \ | |
23279 | xCM_ (m1, cc, m2, op, nops, ops, ae), \ | |
23280 | xCM_ (m1, ul, m2, op, nops, ops, ae), \ | |
23281 | xCM_ (m1, lo, m2, op, nops, ops, ae), \ | |
23282 | xCM_ (m1, mi, m2, op, nops, ops, ae), \ | |
23283 | xCM_ (m1, pl, m2, op, nops, ops, ae), \ | |
23284 | xCM_ (m1, vs, m2, op, nops, ops, ae), \ | |
23285 | xCM_ (m1, vc, m2, op, nops, ops, ae), \ | |
23286 | xCM_ (m1, hi, m2, op, nops, ops, ae), \ | |
23287 | xCM_ (m1, ls, m2, op, nops, ops, ae), \ | |
23288 | xCM_ (m1, ge, m2, op, nops, ops, ae), \ | |
23289 | xCM_ (m1, lt, m2, op, nops, ops, ae), \ | |
23290 | xCM_ (m1, gt, m2, op, nops, ops, ae), \ | |
23291 | xCM_ (m1, le, m2, op, nops, ops, ae), \ | |
23292 | xCM_ (m1, al, m2, op, nops, ops, ae) | |
6a86118a NC |
23293 | |
23294 | #define UE(mnem, op, nops, ops, ae) \ | |
5ee91343 | 23295 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 } |
6a86118a NC |
23296 | |
23297 | #define UF(mnem, op, nops, ops, ae) \ | |
5ee91343 | 23298 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 } |
6a86118a | 23299 | |
5287ad62 JB |
23300 | /* Neon data-processing. ARM versions are unconditional with cond=0xf. |
23301 | The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we | |
23302 | use the same encoding function for each. */ | |
23303 | #define NUF(mnem, op, nops, ops, enc) \ | |
23304 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ | |
5ee91343 | 23305 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 } |
5287ad62 JB |
23306 | |
23307 | /* Neon data processing, version which indirects through neon_enc_tab for | |
23308 | the various overloaded versions of opcodes. */ | |
23309 | #define nUF(mnem, op, nops, ops, enc) \ | |
21d799b5 | 23310 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ |
5ee91343 | 23311 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 } |
5287ad62 JB |
23312 | |
23313 | /* Neon insn with conditional suffix for the ARM version, non-overloaded | |
23314 | version. */ | |
5ee91343 | 23315 | #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \ |
037e8744 | 23316 | { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ |
5ee91343 | 23317 | THUMB_VARIANT, do_##enc, do_##enc, mve_p } |
5287ad62 | 23318 | |
037e8744 | 23319 | #define NCE(mnem, op, nops, ops, enc) \ |
5ee91343 | 23320 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0) |
037e8744 JB |
23321 | |
23322 | #define NCEF(mnem, op, nops, ops, enc) \ | |
5ee91343 | 23323 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0) |
037e8744 | 23324 | |
5287ad62 | 23325 | /* Neon insn with conditional suffix for the ARM version, overloaded types. */ |
5ee91343 | 23326 | #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \ |
21d799b5 | 23327 | { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \ |
5ee91343 | 23328 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p } |
5287ad62 | 23329 | |
037e8744 | 23330 | #define nCE(mnem, op, nops, ops, enc) \ |
5ee91343 | 23331 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0) |
037e8744 JB |
23332 | |
23333 | #define nCEF(mnem, op, nops, ops, enc) \ | |
5ee91343 AV |
23334 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0) |
23335 | ||
23336 | /* */ | |
23337 | #define mCEF(mnem, op, nops, ops, enc) \ | |
a302e574 | 23338 | { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \ |
5ee91343 AV |
23339 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 } |
23340 | ||
23341 | ||
23342 | /* nCEF but for MVE predicated instructions. */ | |
23343 | #define mnCEF(mnem, op, nops, ops, enc) \ | |
23344 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1) | |
23345 | ||
23346 | /* nCE but for MVE predicated instructions. */ | |
23347 | #define mnCE(mnem, op, nops, ops, enc) \ | |
23348 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1) | |
037e8744 | 23349 | |
5ee91343 AV |
23350 | /* NUF but for potentially MVE predicated instructions. */ |
23351 | #define MNUF(mnem, op, nops, ops, enc) \ | |
23352 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ | |
23353 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 } | |
23354 | ||
23355 | /* nUF but for potentially MVE predicated instructions. */ | |
23356 | #define mnUF(mnem, op, nops, ops, enc) \ | |
23357 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ | |
23358 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 } | |
23359 | ||
23360 | /* ToC but for potentially MVE predicated instructions. */ | |
23361 | #define mToC(mnem, top, nops, ops, te) \ | |
23362 | { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \ | |
23363 | do_##te, 1 } | |
23364 | ||
23365 | /* NCE but for MVE predicated instructions. */ | |
23366 | #define MNCE(mnem, op, nops, ops, enc) \ | |
23367 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1) | |
23368 | ||
23369 | /* NCEF but for MVE predicated instructions. */ | |
23370 | #define MNCEF(mnem, op, nops, ops, enc) \ | |
23371 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1) | |
c19d1205 ZW |
23372 | #define do_0 0 |
23373 | ||
c19d1205 | 23374 | static const struct asm_opcode insns[] = |
bfae80f2 | 23375 | { |
74db7efb NC |
23376 | #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */ |
23377 | #define THUMB_VARIANT & arm_ext_v4t | |
21d799b5 NC |
23378 | tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c), |
23379 | tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
23380 | tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
23381 | tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
23382 | tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
23383 | tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
23384 | tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub), | |
23385 | tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub), | |
23386 | tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c), | |
23387 | tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
23388 | tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
23389 | tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
23390 | tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
23391 | tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
23392 | tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3), | |
23393 | tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3), | |
c19d1205 ZW |
23394 | |
23395 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
23396 | for setting PSR flag bits. They are obsolete in V6 and do not | |
23397 | have Thumb equivalents. */ | |
21d799b5 NC |
23398 | tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), |
23399 | tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), | |
23400 | CL("tstp", 110f000, 2, (RR, SH), cmp), | |
23401 | tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
23402 | tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
23403 | CL("cmpp", 150f000, 2, (RR, SH), cmp), | |
23404 | tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
23405 | tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
23406 | CL("cmnp", 170f000, 2, (RR, SH), cmp), | |
23407 | ||
23408 | tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp), | |
72d98d16 | 23409 | tC3("movs", 1b00000, _movs, 2, (RR, SHG), mov, t_mov_cmp), |
21d799b5 NC |
23410 | tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst), |
23411 | tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst), | |
23412 | ||
23413 | tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
5be8be5d DG |
23414 | tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), |
23415 | tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR, | |
23416 | OP_RRnpc), | |
23417 | OP_ADDRGLDR),ldst, t_ldst), | |
23418 | tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), | |
21d799b5 NC |
23419 | |
23420 | tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
23421 | tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
23422 | tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
23423 | tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
23424 | tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
23425 | tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
23426 | ||
21d799b5 NC |
23427 | tCE("b", a000000, _b, 1, (EXPr), branch, t_branch), |
23428 | TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23), | |
bfae80f2 | 23429 | |
c19d1205 | 23430 | /* Pseudo ops. */ |
21d799b5 | 23431 | tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac | 23432 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
21d799b5 | 23433 | tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop), |
74db7efb | 23434 | tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf), |
c19d1205 ZW |
23435 | |
23436 | /* Thumb-compatibility pseudo ops. */ | |
21d799b5 NC |
23437 | tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift), |
23438 | tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift), | |
23439 | tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift), | |
23440 | tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
23441 | tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift), | |
23442 | tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift), | |
23443 | tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift), | |
23444 | tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift), | |
23445 | tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg), | |
23446 | tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg), | |
23447 | tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop), | |
23448 | tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop), | |
c19d1205 | 23449 | |
16a4cf17 | 23450 | /* These may simplify to neg. */ |
21d799b5 NC |
23451 | TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), |
23452 | TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
16a4cf17 | 23453 | |
173205ca TP |
23454 | #undef THUMB_VARIANT |
23455 | #define THUMB_VARIANT & arm_ext_os | |
23456 | ||
23457 | TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi), | |
23458 | TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi), | |
23459 | ||
c921be7d NC |
23460 | #undef THUMB_VARIANT |
23461 | #define THUMB_VARIANT & arm_ext_v6 | |
23462 | ||
21d799b5 | 23463 | TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
23464 | |
23465 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
c921be7d NC |
23466 | #undef THUMB_VARIANT |
23467 | #define THUMB_VARIANT & arm_ext_v6t2 | |
23468 | ||
21d799b5 NC |
23469 | TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
23470 | TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
23471 | CL("teqp", 130f000, 2, (RR, SH), cmp), | |
c19d1205 | 23472 | |
5be8be5d DG |
23473 | TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), |
23474 | TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
23475 | TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt), | |
23476 | TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
c19d1205 | 23477 | |
21d799b5 NC |
23478 | TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
23479 | TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 23480 | |
21d799b5 NC |
23481 | TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
23482 | TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
23483 | |
23484 | /* V1 instructions with no Thumb analogue at all. */ | |
21d799b5 | 23485 | CE("rsc", 0e00000, 3, (RR, oRR, SH), arit), |
c19d1205 ZW |
23486 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), |
23487 | ||
23488 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
23489 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
23490 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
23491 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
23492 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
23493 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
23494 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
23495 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
23496 | ||
c921be7d NC |
23497 | #undef ARM_VARIANT |
23498 | #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */ | |
23499 | #undef THUMB_VARIANT | |
23500 | #define THUMB_VARIANT & arm_ext_v4t | |
23501 | ||
21d799b5 NC |
23502 | tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
23503 | tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
c19d1205 | 23504 | |
c921be7d NC |
23505 | #undef THUMB_VARIANT |
23506 | #define THUMB_VARIANT & arm_ext_v6t2 | |
23507 | ||
21d799b5 | 23508 | TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
c19d1205 ZW |
23509 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), |
23510 | ||
23511 | /* Generic coprocessor instructions. */ | |
21d799b5 NC |
23512 | TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), |
23513 | TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
23514 | TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
23515 | TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
23516 | TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
23517 | TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
db472d6f | 23518 | TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), |
c19d1205 | 23519 | |
c921be7d NC |
23520 | #undef ARM_VARIANT |
23521 | #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */ | |
23522 | ||
21d799b5 | 23523 | CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
c19d1205 ZW |
23524 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
23525 | ||
c921be7d NC |
23526 | #undef ARM_VARIANT |
23527 | #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */ | |
23528 | #undef THUMB_VARIANT | |
23529 | #define THUMB_VARIANT & arm_ext_msr | |
23530 | ||
d2cd1205 JB |
23531 | TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs), |
23532 | TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr), | |
c19d1205 | 23533 | |
c921be7d NC |
23534 | #undef ARM_VARIANT |
23535 | #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */ | |
23536 | #undef THUMB_VARIANT | |
23537 | #define THUMB_VARIANT & arm_ext_v6t2 | |
23538 | ||
21d799b5 NC |
23539 | TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
23540 | CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
23541 | TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
23542 | CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
23543 | TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
23544 | CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
23545 | TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
23546 | CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
c19d1205 | 23547 | |
c921be7d NC |
23548 | #undef ARM_VARIANT |
23549 | #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */ | |
23550 | #undef THUMB_VARIANT | |
23551 | #define THUMB_VARIANT & arm_ext_v4t | |
23552 | ||
5be8be5d DG |
23553 | tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
23554 | tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
23555 | tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
23556 | tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
56c0a61f RE |
23557 | tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
23558 | tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
c19d1205 | 23559 | |
c921be7d NC |
23560 | #undef ARM_VARIANT |
23561 | #define ARM_VARIANT & arm_ext_v4t_5 | |
23562 | ||
c19d1205 ZW |
23563 | /* ARM Architecture 4T. */ |
23564 | /* Note: bx (and blx) are required on V5, even if the processor does | |
23565 | not support Thumb. */ | |
21d799b5 | 23566 | TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx), |
c19d1205 | 23567 | |
c921be7d NC |
23568 | #undef ARM_VARIANT |
23569 | #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */ | |
23570 | #undef THUMB_VARIANT | |
23571 | #define THUMB_VARIANT & arm_ext_v5t | |
23572 | ||
c19d1205 ZW |
23573 | /* Note: blx has 2 variants; the .value coded here is for |
23574 | BLX(2). Only this variant has conditional execution. */ | |
21d799b5 NC |
23575 | TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx), |
23576 | TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
c19d1205 | 23577 | |
c921be7d NC |
23578 | #undef THUMB_VARIANT |
23579 | #define THUMB_VARIANT & arm_ext_v6t2 | |
23580 | ||
21d799b5 NC |
23581 | TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
23582 | TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
23583 | TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
23584 | TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
23585 | TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
23586 | TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
23587 | TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
23588 | TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
c19d1205 | 23589 | |
c921be7d | 23590 | #undef ARM_VARIANT |
74db7efb NC |
23591 | #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */ |
23592 | #undef THUMB_VARIANT | |
23593 | #define THUMB_VARIANT & arm_ext_v5exp | |
c921be7d | 23594 | |
21d799b5 NC |
23595 | TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
23596 | TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
23597 | TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
23598 | TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 23599 | |
21d799b5 NC |
23600 | TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
23601 | TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 23602 | |
21d799b5 NC |
23603 | TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), |
23604 | TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
23605 | TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
23606 | TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
c19d1205 | 23607 | |
21d799b5 NC |
23608 | TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
23609 | TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
23610 | TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
23611 | TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 23612 | |
21d799b5 NC |
23613 | TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
23614 | TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 23615 | |
03ee1b7f NC |
23616 | TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), |
23617 | TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
23618 | TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
23619 | TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
c19d1205 | 23620 | |
c921be7d | 23621 | #undef ARM_VARIANT |
74db7efb NC |
23622 | #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */ |
23623 | #undef THUMB_VARIANT | |
23624 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 23625 | |
21d799b5 | 23626 | TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld), |
5be8be5d DG |
23627 | TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS), |
23628 | ldrd, t_ldstd), | |
23629 | TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp, | |
23630 | ADDRGLDRS), ldrd, t_ldstd), | |
c19d1205 | 23631 | |
21d799b5 NC |
23632 | TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
23633 | TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
c19d1205 | 23634 | |
c921be7d NC |
23635 | #undef ARM_VARIANT |
23636 | #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */ | |
23637 | ||
21d799b5 | 23638 | TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
c19d1205 | 23639 | |
c921be7d NC |
23640 | #undef ARM_VARIANT |
23641 | #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */ | |
23642 | #undef THUMB_VARIANT | |
23643 | #define THUMB_VARIANT & arm_ext_v6 | |
23644 | ||
21d799b5 NC |
23645 | TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
23646 | TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
23647 | tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
23648 | tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
23649 | tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
23650 | tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
23651 | tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
23652 | tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
23653 | tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
23654 | TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend), | |
c19d1205 | 23655 | |
c921be7d | 23656 | #undef THUMB_VARIANT |
ff8646ee | 23657 | #define THUMB_VARIANT & arm_ext_v6t2_v8m |
c921be7d | 23658 | |
5be8be5d DG |
23659 | TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex), |
23660 | TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
23661 | strex, t_strex), | |
ff8646ee TP |
23662 | #undef THUMB_VARIANT |
23663 | #define THUMB_VARIANT & arm_ext_v6t2 | |
23664 | ||
21d799b5 NC |
23665 | TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
23666 | TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
62b3e311 | 23667 | |
21d799b5 NC |
23668 | TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), |
23669 | TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
62b3e311 | 23670 | |
9e3c6df6 | 23671 | /* ARM V6 not included in V7M. */ |
c921be7d NC |
23672 | #undef THUMB_VARIANT |
23673 | #define THUMB_VARIANT & arm_ext_v6_notm | |
9e3c6df6 | 23674 | TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
d709e4e6 | 23675 | TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
9e3c6df6 PB |
23676 | UF(rfeib, 9900a00, 1, (RRw), rfe), |
23677 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
23678 | TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
23679 | TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
d709e4e6 RE |
23680 | UF(rfefa, 8100a00, 1, (RRw), rfe), |
23681 | TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
23682 | UF(rfeed, 9900a00, 1, (RRw), rfe), | |
9e3c6df6 | 23683 | TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), |
d709e4e6 RE |
23684 | TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), |
23685 | TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), | |
9e3c6df6 | 23686 | UF(srsib, 9c00500, 2, (oRRw, I31w), srs), |
d709e4e6 | 23687 | UF(srsfa, 9c00500, 2, (oRRw, I31w), srs), |
9e3c6df6 | 23688 | UF(srsda, 8400500, 2, (oRRw, I31w), srs), |
d709e4e6 | 23689 | UF(srsed, 8400500, 2, (oRRw, I31w), srs), |
9e3c6df6 | 23690 | TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), |
d709e4e6 | 23691 | TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), |
941c9cad | 23692 | TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps), |
c921be7d | 23693 | |
9e3c6df6 PB |
23694 | /* ARM V6 not included in V7M (eg. integer SIMD). */ |
23695 | #undef THUMB_VARIANT | |
23696 | #define THUMB_VARIANT & arm_ext_v6_dsp | |
21d799b5 NC |
23697 | TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), |
23698 | TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
23699 | TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23700 | TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23701 | TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 23702 | /* Old name for QASX. */ |
74db7efb | 23703 | TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 | 23704 | TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 23705 | /* Old name for QSAX. */ |
74db7efb | 23706 | TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
23707 | TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
23708 | TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23709 | TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23710 | TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23711 | TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 23712 | /* Old name for SASX. */ |
74db7efb | 23713 | TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
23714 | TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
23715 | TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 23716 | TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 23717 | /* Old name for SHASX. */ |
21d799b5 | 23718 | TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
74db7efb | 23719 | TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 23720 | /* Old name for SHSAX. */ |
21d799b5 NC |
23721 | TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
23722 | TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23723 | TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23724 | TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 23725 | /* Old name for SSAX. */ |
74db7efb | 23726 | TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
23727 | TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
23728 | TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23729 | TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23730 | TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23731 | TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 23732 | /* Old name for UASX. */ |
74db7efb | 23733 | TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
23734 | TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
23735 | TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 23736 | TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 23737 | /* Old name for UHASX. */ |
21d799b5 NC |
23738 | TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
23739 | TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 23740 | /* Old name for UHSAX. */ |
21d799b5 NC |
23741 | TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
23742 | TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23743 | TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23744 | TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23745 | TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 23746 | TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 23747 | /* Old name for UQASX. */ |
21d799b5 NC |
23748 | TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
23749 | TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 23750 | /* Old name for UQSAX. */ |
21d799b5 NC |
23751 | TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
23752 | TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23753 | TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23754 | TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23755 | TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 23756 | /* Old name for USAX. */ |
74db7efb | 23757 | TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 | 23758 | TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
23759 | TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
23760 | TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
23761 | TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
23762 | TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
23763 | TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
23764 | TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
23765 | TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
23766 | TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
23767 | TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23768 | TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
23769 | TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
23770 | TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
23771 | TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
23772 | TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
23773 | TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
23774 | TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
23775 | TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
23776 | TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
23777 | TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
23778 | TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
23779 | TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
23780 | TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
23781 | TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
23782 | TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
23783 | TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
23784 | TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
23785 | TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
21d799b5 NC |
23786 | TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), |
23787 | TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
23788 | TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
23789 | TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
23790 | TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), | |
c19d1205 | 23791 | |
c921be7d | 23792 | #undef ARM_VARIANT |
55e8aae7 | 23793 | #define ARM_VARIANT & arm_ext_v6k_v6t2 |
c921be7d | 23794 | #undef THUMB_VARIANT |
55e8aae7 | 23795 | #define THUMB_VARIANT & arm_ext_v6k_v6t2 |
c921be7d | 23796 | |
21d799b5 NC |
23797 | tCE("yield", 320f001, _yield, 0, (), noargs, t_hint), |
23798 | tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint), | |
23799 | tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint), | |
23800 | tCE("sev", 320f004, _sev, 0, (), noargs, t_hint), | |
c19d1205 | 23801 | |
c921be7d NC |
23802 | #undef THUMB_VARIANT |
23803 | #define THUMB_VARIANT & arm_ext_v6_notm | |
5be8be5d DG |
23804 | TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb), |
23805 | ldrexd, t_ldrexd), | |
23806 | TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp, | |
23807 | RRnpcb), strexd, t_strexd), | |
ebdca51a | 23808 | |
c921be7d | 23809 | #undef THUMB_VARIANT |
ff8646ee | 23810 | #define THUMB_VARIANT & arm_ext_v6t2_v8m |
5be8be5d DG |
23811 | TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb), |
23812 | rd_rn, rd_rn), | |
23813 | TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb), | |
23814 | rd_rn, rd_rn), | |
23815 | TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
877807f8 | 23816 | strex, t_strexbh), |
5be8be5d | 23817 | TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), |
877807f8 | 23818 | strex, t_strexbh), |
21d799b5 | 23819 | TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs), |
c19d1205 | 23820 | |
c921be7d | 23821 | #undef ARM_VARIANT |
f4c65163 | 23822 | #define ARM_VARIANT & arm_ext_sec |
74db7efb | 23823 | #undef THUMB_VARIANT |
f4c65163 | 23824 | #define THUMB_VARIANT & arm_ext_sec |
c921be7d | 23825 | |
21d799b5 | 23826 | TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 | 23827 | |
90ec0d68 MGD |
23828 | #undef ARM_VARIANT |
23829 | #define ARM_VARIANT & arm_ext_virt | |
23830 | #undef THUMB_VARIANT | |
23831 | #define THUMB_VARIANT & arm_ext_virt | |
23832 | ||
23833 | TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc), | |
23834 | TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs), | |
23835 | ||
ddfded2f MW |
23836 | #undef ARM_VARIANT |
23837 | #define ARM_VARIANT & arm_ext_pan | |
23838 | #undef THUMB_VARIANT | |
23839 | #define THUMB_VARIANT & arm_ext_pan | |
23840 | ||
23841 | TUF("setpan", 1100000, b610, 1, (I7), setpan, t_setpan), | |
23842 | ||
c921be7d | 23843 | #undef ARM_VARIANT |
74db7efb | 23844 | #define ARM_VARIANT & arm_ext_v6t2 |
f4c65163 MGD |
23845 | #undef THUMB_VARIANT |
23846 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 23847 | |
21d799b5 NC |
23848 | TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
23849 | TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
23850 | TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
23851 | TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
c19d1205 | 23852 | |
21d799b5 | 23853 | TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
21d799b5 | 23854 | TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), |
c19d1205 | 23855 | |
5be8be5d DG |
23856 | TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), |
23857 | TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
23858 | TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
23859 | TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
c19d1205 | 23860 | |
91d8b670 JG |
23861 | #undef ARM_VARIANT |
23862 | #define ARM_VARIANT & arm_ext_v3 | |
23863 | #undef THUMB_VARIANT | |
23864 | #define THUMB_VARIANT & arm_ext_v6t2 | |
23865 | ||
23866 | TUE("csdb", 320f014, f3af8014, 0, (), noargs, t_csdb), | |
c597cc3d SD |
23867 | TUF("ssbb", 57ff040, f3bf8f40, 0, (), noargs, t_csdb), |
23868 | TUF("pssbb", 57ff044, f3bf8f44, 0, (), noargs, t_csdb), | |
91d8b670 JG |
23869 | |
23870 | #undef ARM_VARIANT | |
23871 | #define ARM_VARIANT & arm_ext_v6t2 | |
ff8646ee TP |
23872 | #undef THUMB_VARIANT |
23873 | #define THUMB_VARIANT & arm_ext_v6t2_v8m | |
23874 | TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), | |
23875 | TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), | |
23876 | ||
bf3eeda7 | 23877 | /* Thumb-only instructions. */ |
74db7efb | 23878 | #undef ARM_VARIANT |
bf3eeda7 NS |
23879 | #define ARM_VARIANT NULL |
23880 | TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz), | |
23881 | TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz), | |
c921be7d NC |
23882 | |
23883 | /* ARM does not really have an IT instruction, so always allow it. | |
23884 | The opcode is copied from Thumb in order to allow warnings in | |
23885 | -mimplicit-it=[never | arm] modes. */ | |
23886 | #undef ARM_VARIANT | |
23887 | #define ARM_VARIANT & arm_ext_v1 | |
ff8646ee TP |
23888 | #undef THUMB_VARIANT |
23889 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 23890 | |
21d799b5 NC |
23891 | TUE("it", bf08, bf08, 1, (COND), it, t_it), |
23892 | TUE("itt", bf0c, bf0c, 1, (COND), it, t_it), | |
23893 | TUE("ite", bf04, bf04, 1, (COND), it, t_it), | |
23894 | TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it), | |
23895 | TUE("itet", bf06, bf06, 1, (COND), it, t_it), | |
23896 | TUE("itte", bf0a, bf0a, 1, (COND), it, t_it), | |
23897 | TUE("itee", bf02, bf02, 1, (COND), it, t_it), | |
23898 | TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it), | |
23899 | TUE("itett", bf07, bf07, 1, (COND), it, t_it), | |
23900 | TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it), | |
23901 | TUE("iteet", bf03, bf03, 1, (COND), it, t_it), | |
23902 | TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it), | |
23903 | TUE("itete", bf05, bf05, 1, (COND), it, t_it), | |
23904 | TUE("ittee", bf09, bf09, 1, (COND), it, t_it), | |
23905 | TUE("iteee", bf01, bf01, 1, (COND), it, t_it), | |
1c444d06 | 23906 | /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */ |
21d799b5 NC |
23907 | TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx), |
23908 | TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx), | |
c19d1205 | 23909 | |
92e90b6e | 23910 | /* Thumb2 only instructions. */ |
c921be7d NC |
23911 | #undef ARM_VARIANT |
23912 | #define ARM_VARIANT NULL | |
92e90b6e | 23913 | |
21d799b5 NC |
23914 | TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), |
23915 | TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
23916 | TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn), | |
23917 | TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn), | |
23918 | TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb), | |
23919 | TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb), | |
92e90b6e | 23920 | |
eea54501 MGD |
23921 | /* Hardware division instructions. */ |
23922 | #undef ARM_VARIANT | |
23923 | #define ARM_VARIANT & arm_ext_adiv | |
c921be7d NC |
23924 | #undef THUMB_VARIANT |
23925 | #define THUMB_VARIANT & arm_ext_div | |
23926 | ||
eea54501 MGD |
23927 | TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div), |
23928 | TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div), | |
62b3e311 | 23929 | |
7e806470 | 23930 | /* ARM V6M/V7 instructions. */ |
c921be7d NC |
23931 | #undef ARM_VARIANT |
23932 | #define ARM_VARIANT & arm_ext_barrier | |
23933 | #undef THUMB_VARIANT | |
23934 | #define THUMB_VARIANT & arm_ext_barrier | |
23935 | ||
ccb84d65 JB |
23936 | TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier), |
23937 | TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier), | |
23938 | TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier), | |
7e806470 | 23939 | |
62b3e311 | 23940 | /* ARM V7 instructions. */ |
c921be7d NC |
23941 | #undef ARM_VARIANT |
23942 | #define ARM_VARIANT & arm_ext_v7 | |
23943 | #undef THUMB_VARIANT | |
23944 | #define THUMB_VARIANT & arm_ext_v7 | |
23945 | ||
21d799b5 NC |
23946 | TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld), |
23947 | TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), | |
62b3e311 | 23948 | |
74db7efb | 23949 | #undef ARM_VARIANT |
60e5ef9f | 23950 | #define ARM_VARIANT & arm_ext_mp |
74db7efb | 23951 | #undef THUMB_VARIANT |
60e5ef9f MGD |
23952 | #define THUMB_VARIANT & arm_ext_mp |
23953 | ||
23954 | TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld), | |
23955 | ||
53c4b28b MGD |
23956 | /* AArchv8 instructions. */ |
23957 | #undef ARM_VARIANT | |
23958 | #define ARM_VARIANT & arm_ext_v8 | |
4ed7ed8d TP |
23959 | |
23960 | /* Instructions shared between armv8-a and armv8-m. */ | |
53c4b28b | 23961 | #undef THUMB_VARIANT |
4ed7ed8d | 23962 | #define THUMB_VARIANT & arm_ext_atomics |
53c4b28b | 23963 | |
4ed7ed8d TP |
23964 | TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), |
23965 | TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
23966 | TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
23967 | TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
23968 | TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
23969 | TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
4b8c8c02 | 23970 | TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), |
4b8c8c02 RE |
23971 | TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn), |
23972 | TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
23973 | TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb), | |
23974 | stlex, t_stlex), | |
4b8c8c02 RE |
23975 | TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb), |
23976 | stlex, t_stlex), | |
23977 | TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb), | |
23978 | stlex, t_stlex), | |
4ed7ed8d TP |
23979 | #undef THUMB_VARIANT |
23980 | #define THUMB_VARIANT & arm_ext_v8 | |
53c4b28b | 23981 | |
4ed7ed8d | 23982 | tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint), |
4ed7ed8d TP |
23983 | TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb), |
23984 | ldrexd, t_ldrexd), | |
23985 | TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), | |
23986 | strexd, t_strexd), | |
f7dd2fb2 TC |
23987 | |
23988 | /* Defined in V8 but is in undefined encoding space for earlier | |
23989 | architectures. However earlier architectures are required to treat | |
23990 | this instuction as a semihosting trap as well. Hence while not explicitly | |
23991 | defined as such, it is in fact correct to define the instruction for all | |
23992 | architectures. */ | |
23993 | #undef THUMB_VARIANT | |
23994 | #define THUMB_VARIANT & arm_ext_v1 | |
23995 | #undef ARM_VARIANT | |
23996 | #define ARM_VARIANT & arm_ext_v1 | |
23997 | TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt), | |
23998 | ||
8884b720 | 23999 | /* ARMv8 T32 only. */ |
74db7efb | 24000 | #undef ARM_VARIANT |
b79f7053 MGD |
24001 | #define ARM_VARIANT NULL |
24002 | TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs), | |
24003 | TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs), | |
24004 | TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs), | |
24005 | ||
33399f07 MGD |
24006 | /* FP for ARMv8. */ |
24007 | #undef ARM_VARIANT | |
a715796b | 24008 | #define ARM_VARIANT & fpu_vfp_ext_armv8xd |
33399f07 | 24009 | #undef THUMB_VARIANT |
a715796b | 24010 | #define THUMB_VARIANT & fpu_vfp_ext_armv8xd |
33399f07 MGD |
24011 | |
24012 | nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel), | |
24013 | nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel), | |
24014 | nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel), | |
24015 | nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel), | |
30bdf752 | 24016 | nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr), |
a710b305 AV |
24017 | mnCE(vrintz, _vrintr, 2, (RNSDQMQ, oRNSDQMQ), vrintz), |
24018 | mnCE(vrintx, _vrintr, 2, (RNSDQMQ, oRNSDQMQ), vrintx), | |
24019 | mnUF(vrinta, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrinta), | |
24020 | mnUF(vrintn, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintn), | |
24021 | mnUF(vrintp, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintp), | |
24022 | mnUF(vrintm, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintm), | |
33399f07 | 24023 | |
91ff7894 MGD |
24024 | /* Crypto v1 extensions. */ |
24025 | #undef ARM_VARIANT | |
24026 | #define ARM_VARIANT & fpu_crypto_ext_armv8 | |
24027 | #undef THUMB_VARIANT | |
24028 | #define THUMB_VARIANT & fpu_crypto_ext_armv8 | |
24029 | ||
24030 | nUF(aese, _aes, 2, (RNQ, RNQ), aese), | |
24031 | nUF(aesd, _aes, 2, (RNQ, RNQ), aesd), | |
24032 | nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc), | |
24033 | nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc), | |
48adcd8e MGD |
24034 | nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c), |
24035 | nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p), | |
24036 | nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m), | |
24037 | nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0), | |
24038 | nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h), | |
24039 | nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2), | |
24040 | nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1), | |
3c9017d2 MGD |
24041 | nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h), |
24042 | nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1), | |
24043 | nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0), | |
91ff7894 | 24044 | |
dd5181d5 | 24045 | #undef ARM_VARIANT |
74db7efb | 24046 | #define ARM_VARIANT & crc_ext_armv8 |
dd5181d5 KT |
24047 | #undef THUMB_VARIANT |
24048 | #define THUMB_VARIANT & crc_ext_armv8 | |
24049 | TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b), | |
24050 | TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h), | |
24051 | TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w), | |
24052 | TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb), | |
24053 | TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch), | |
24054 | TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw), | |
24055 | ||
105bde57 MW |
24056 | /* ARMv8.2 RAS extension. */ |
24057 | #undef ARM_VARIANT | |
4d1464f2 | 24058 | #define ARM_VARIANT & arm_ext_ras |
105bde57 | 24059 | #undef THUMB_VARIANT |
4d1464f2 | 24060 | #define THUMB_VARIANT & arm_ext_ras |
105bde57 MW |
24061 | TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs), |
24062 | ||
49e8a725 SN |
24063 | #undef ARM_VARIANT |
24064 | #define ARM_VARIANT & arm_ext_v8_3 | |
24065 | #undef THUMB_VARIANT | |
24066 | #define THUMB_VARIANT & arm_ext_v8_3 | |
24067 | NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt), | |
24068 | ||
c604a79a JW |
24069 | #undef ARM_VARIANT |
24070 | #define ARM_VARIANT & fpu_neon_ext_dotprod | |
24071 | #undef THUMB_VARIANT | |
24072 | #define THUMB_VARIANT & fpu_neon_ext_dotprod | |
24073 | NUF (vsdot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_s), | |
24074 | NUF (vudot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_u), | |
24075 | ||
c921be7d NC |
24076 | #undef ARM_VARIANT |
24077 | #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ | |
53c4b28b MGD |
24078 | #undef THUMB_VARIANT |
24079 | #define THUMB_VARIANT NULL | |
c921be7d | 24080 | |
21d799b5 NC |
24081 | cCE("wfs", e200110, 1, (RR), rd), |
24082 | cCE("rfs", e300110, 1, (RR), rd), | |
24083 | cCE("wfc", e400110, 1, (RR), rd), | |
24084 | cCE("rfc", e500110, 1, (RR), rd), | |
24085 | ||
24086 | cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
24087 | cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
24088 | cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
24089 | cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
24090 | ||
24091 | cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
24092 | cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
24093 | cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
24094 | cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
24095 | ||
24096 | cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm), | |
24097 | cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm), | |
24098 | cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm), | |
24099 | cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm), | |
24100 | cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm), | |
24101 | cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm), | |
24102 | cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm), | |
24103 | cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm), | |
24104 | cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm), | |
24105 | cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm), | |
24106 | cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm), | |
24107 | cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm), | |
24108 | ||
24109 | cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm), | |
24110 | cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm), | |
24111 | cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm), | |
24112 | cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm), | |
24113 | cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm), | |
24114 | cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm), | |
24115 | cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm), | |
24116 | cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm), | |
24117 | cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm), | |
24118 | cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm), | |
24119 | cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm), | |
24120 | cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm), | |
24121 | ||
24122 | cCL("abss", e208100, 2, (RF, RF_IF), rd_rm), | |
24123 | cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm), | |
24124 | cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm), | |
24125 | cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm), | |
24126 | cCL("absd", e208180, 2, (RF, RF_IF), rd_rm), | |
24127 | cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm), | |
24128 | cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm), | |
24129 | cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm), | |
24130 | cCL("abse", e288100, 2, (RF, RF_IF), rd_rm), | |
24131 | cCL("absep", e288120, 2, (RF, RF_IF), rd_rm), | |
24132 | cCL("absem", e288140, 2, (RF, RF_IF), rd_rm), | |
24133 | cCL("absez", e288160, 2, (RF, RF_IF), rd_rm), | |
24134 | ||
24135 | cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm), | |
24136 | cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm), | |
24137 | cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm), | |
24138 | cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm), | |
24139 | cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm), | |
24140 | cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm), | |
24141 | cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm), | |
24142 | cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm), | |
24143 | cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm), | |
24144 | cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm), | |
24145 | cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm), | |
24146 | cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm), | |
24147 | ||
24148 | cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm), | |
24149 | cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm), | |
24150 | cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm), | |
24151 | cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm), | |
24152 | cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm), | |
24153 | cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm), | |
24154 | cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm), | |
24155 | cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm), | |
24156 | cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm), | |
24157 | cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm), | |
24158 | cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm), | |
24159 | cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm), | |
24160 | ||
24161 | cCL("logs", e508100, 2, (RF, RF_IF), rd_rm), | |
24162 | cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm), | |
24163 | cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm), | |
24164 | cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm), | |
24165 | cCL("logd", e508180, 2, (RF, RF_IF), rd_rm), | |
24166 | cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm), | |
24167 | cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm), | |
24168 | cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm), | |
24169 | cCL("loge", e588100, 2, (RF, RF_IF), rd_rm), | |
24170 | cCL("logep", e588120, 2, (RF, RF_IF), rd_rm), | |
24171 | cCL("logem", e588140, 2, (RF, RF_IF), rd_rm), | |
24172 | cCL("logez", e588160, 2, (RF, RF_IF), rd_rm), | |
24173 | ||
24174 | cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm), | |
24175 | cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm), | |
24176 | cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm), | |
24177 | cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm), | |
24178 | cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm), | |
24179 | cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm), | |
24180 | cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm), | |
24181 | cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm), | |
24182 | cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm), | |
24183 | cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm), | |
24184 | cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm), | |
24185 | cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm), | |
24186 | ||
24187 | cCL("exps", e708100, 2, (RF, RF_IF), rd_rm), | |
24188 | cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm), | |
24189 | cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm), | |
24190 | cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm), | |
24191 | cCL("expd", e708180, 2, (RF, RF_IF), rd_rm), | |
24192 | cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm), | |
24193 | cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm), | |
24194 | cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm), | |
24195 | cCL("expe", e788100, 2, (RF, RF_IF), rd_rm), | |
24196 | cCL("expep", e788120, 2, (RF, RF_IF), rd_rm), | |
24197 | cCL("expem", e788140, 2, (RF, RF_IF), rd_rm), | |
24198 | cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm), | |
24199 | ||
24200 | cCL("sins", e808100, 2, (RF, RF_IF), rd_rm), | |
24201 | cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm), | |
24202 | cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm), | |
24203 | cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm), | |
24204 | cCL("sind", e808180, 2, (RF, RF_IF), rd_rm), | |
24205 | cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm), | |
24206 | cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm), | |
24207 | cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm), | |
24208 | cCL("sine", e888100, 2, (RF, RF_IF), rd_rm), | |
24209 | cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm), | |
24210 | cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm), | |
24211 | cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm), | |
24212 | ||
24213 | cCL("coss", e908100, 2, (RF, RF_IF), rd_rm), | |
24214 | cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm), | |
24215 | cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm), | |
24216 | cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm), | |
24217 | cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm), | |
24218 | cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm), | |
24219 | cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm), | |
24220 | cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm), | |
24221 | cCL("cose", e988100, 2, (RF, RF_IF), rd_rm), | |
24222 | cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm), | |
24223 | cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm), | |
24224 | cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm), | |
24225 | ||
24226 | cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm), | |
24227 | cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm), | |
24228 | cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm), | |
24229 | cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm), | |
24230 | cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm), | |
24231 | cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm), | |
24232 | cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm), | |
24233 | cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm), | |
24234 | cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm), | |
24235 | cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm), | |
24236 | cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm), | |
24237 | cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm), | |
24238 | ||
24239 | cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm), | |
24240 | cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm), | |
24241 | cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm), | |
24242 | cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm), | |
24243 | cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm), | |
24244 | cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm), | |
24245 | cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm), | |
24246 | cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm), | |
24247 | cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm), | |
24248 | cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm), | |
24249 | cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm), | |
24250 | cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm), | |
24251 | ||
24252 | cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm), | |
24253 | cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm), | |
24254 | cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm), | |
24255 | cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm), | |
24256 | cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm), | |
24257 | cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm), | |
24258 | cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm), | |
24259 | cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm), | |
24260 | cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm), | |
24261 | cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm), | |
24262 | cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm), | |
24263 | cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm), | |
24264 | ||
24265 | cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm), | |
24266 | cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm), | |
24267 | cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm), | |
24268 | cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm), | |
24269 | cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm), | |
24270 | cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm), | |
24271 | cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm), | |
24272 | cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm), | |
24273 | cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm), | |
24274 | cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm), | |
24275 | cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm), | |
24276 | cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm), | |
24277 | ||
24278 | cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm), | |
24279 | cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm), | |
24280 | cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm), | |
24281 | cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm), | |
24282 | cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm), | |
24283 | cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm), | |
24284 | cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm), | |
24285 | cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm), | |
24286 | cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm), | |
24287 | cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm), | |
24288 | cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm), | |
24289 | cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm), | |
24290 | ||
24291 | cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm), | |
24292 | cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm), | |
24293 | cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm), | |
24294 | cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm), | |
24295 | cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm), | |
24296 | cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm), | |
24297 | cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm), | |
24298 | cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm), | |
24299 | cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm), | |
24300 | cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm), | |
24301 | cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm), | |
24302 | cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm), | |
24303 | ||
24304 | cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24305 | cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24306 | cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24307 | cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24308 | cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24309 | cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24310 | cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24311 | cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24312 | cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24313 | cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24314 | cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24315 | cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24316 | ||
24317 | cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24318 | cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24319 | cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24320 | cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24321 | cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24322 | cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24323 | cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24324 | cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24325 | cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24326 | cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24327 | cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24328 | cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24329 | ||
24330 | cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24331 | cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24332 | cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24333 | cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24334 | cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24335 | cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24336 | cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24337 | cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24338 | cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24339 | cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24340 | cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24341 | cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24342 | ||
24343 | cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24344 | cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24345 | cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24346 | cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24347 | cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24348 | cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24349 | cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24350 | cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24351 | cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24352 | cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24353 | cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24354 | cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24355 | ||
24356 | cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24357 | cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24358 | cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24359 | cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24360 | cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24361 | cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24362 | cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24363 | cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24364 | cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24365 | cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24366 | cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24367 | cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24368 | ||
24369 | cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24370 | cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24371 | cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24372 | cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24373 | cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24374 | cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24375 | cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24376 | cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24377 | cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24378 | cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24379 | cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24380 | cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24381 | ||
24382 | cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24383 | cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24384 | cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24385 | cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24386 | cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24387 | cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24388 | cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24389 | cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24390 | cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24391 | cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24392 | cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24393 | cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24394 | ||
24395 | cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24396 | cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24397 | cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24398 | cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24399 | cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24400 | cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24401 | cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24402 | cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24403 | cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24404 | cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24405 | cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24406 | cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24407 | ||
24408 | cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24409 | cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24410 | cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24411 | cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24412 | cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24413 | cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24414 | cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24415 | cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24416 | cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24417 | cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24418 | cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24419 | cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24420 | ||
24421 | cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24422 | cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24423 | cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24424 | cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24425 | cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24426 | cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24427 | cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24428 | cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24429 | cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24430 | cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24431 | cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24432 | cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24433 | ||
24434 | cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24435 | cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24436 | cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24437 | cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24438 | cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24439 | cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24440 | cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24441 | cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24442 | cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24443 | cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24444 | cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24445 | cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24446 | ||
24447 | cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24448 | cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24449 | cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24450 | cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24451 | cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24452 | cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24453 | cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24454 | cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24455 | cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24456 | cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24457 | cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24458 | cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24459 | ||
24460 | cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24461 | cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24462 | cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24463 | cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24464 | cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24465 | cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24466 | cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24467 | cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24468 | cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24469 | cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24470 | cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24471 | cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24472 | ||
24473 | cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp), | |
24474 | C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp), | |
24475 | cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp), | |
24476 | C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp), | |
24477 | ||
24478 | cCL("flts", e000110, 2, (RF, RR), rn_rd), | |
24479 | cCL("fltsp", e000130, 2, (RF, RR), rn_rd), | |
24480 | cCL("fltsm", e000150, 2, (RF, RR), rn_rd), | |
24481 | cCL("fltsz", e000170, 2, (RF, RR), rn_rd), | |
24482 | cCL("fltd", e000190, 2, (RF, RR), rn_rd), | |
24483 | cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd), | |
24484 | cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd), | |
24485 | cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd), | |
24486 | cCL("flte", e080110, 2, (RF, RR), rn_rd), | |
24487 | cCL("fltep", e080130, 2, (RF, RR), rn_rd), | |
24488 | cCL("fltem", e080150, 2, (RF, RR), rn_rd), | |
24489 | cCL("fltez", e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 24490 | |
c19d1205 ZW |
24491 | /* The implementation of the FIX instruction is broken on some |
24492 | assemblers, in that it accepts a precision specifier as well as a | |
24493 | rounding specifier, despite the fact that this is meaningless. | |
24494 | To be more compatible, we accept it as well, though of course it | |
24495 | does not set any bits. */ | |
21d799b5 NC |
24496 | cCE("fix", e100110, 2, (RR, RF), rd_rm), |
24497 | cCL("fixp", e100130, 2, (RR, RF), rd_rm), | |
24498 | cCL("fixm", e100150, 2, (RR, RF), rd_rm), | |
24499 | cCL("fixz", e100170, 2, (RR, RF), rd_rm), | |
24500 | cCL("fixsp", e100130, 2, (RR, RF), rd_rm), | |
24501 | cCL("fixsm", e100150, 2, (RR, RF), rd_rm), | |
24502 | cCL("fixsz", e100170, 2, (RR, RF), rd_rm), | |
24503 | cCL("fixdp", e100130, 2, (RR, RF), rd_rm), | |
24504 | cCL("fixdm", e100150, 2, (RR, RF), rd_rm), | |
24505 | cCL("fixdz", e100170, 2, (RR, RF), rd_rm), | |
24506 | cCL("fixep", e100130, 2, (RR, RF), rd_rm), | |
24507 | cCL("fixem", e100150, 2, (RR, RF), rd_rm), | |
24508 | cCL("fixez", e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 24509 | |
c19d1205 | 24510 | /* Instructions that were new with the real FPA, call them V2. */ |
c921be7d NC |
24511 | #undef ARM_VARIANT |
24512 | #define ARM_VARIANT & fpu_fpa_ext_v2 | |
24513 | ||
21d799b5 NC |
24514 | cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
24515 | cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
24516 | cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
24517 | cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
24518 | cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
24519 | cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 | 24520 | |
c921be7d NC |
24521 | #undef ARM_VARIANT |
24522 | #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ | |
ba6cd17f SD |
24523 | #undef THUMB_VARIANT |
24524 | #define THUMB_VARIANT & arm_ext_v6t2 | |
24525 | mcCE(vmrs, ef00a10, 2, (APSR_RR, RVC), vmrs), | |
24526 | mcCE(vmsr, ee00a10, 2, (RVC, RR), vmsr), | |
24527 | #undef THUMB_VARIANT | |
c921be7d | 24528 | |
c19d1205 | 24529 | /* Moves and type conversions. */ |
21d799b5 NC |
24530 | cCE("fmstat", ef1fa10, 0, (), noargs), |
24531 | cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
24532 | cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
24533 | cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
24534 | cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
24535 | cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
24536 | cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
24537 | cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn), | |
24538 | cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
24539 | |
24540 | /* Memory operations. */ | |
21d799b5 NC |
24541 | cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), |
24542 | cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), | |
55881a11 MGD |
24543 | cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), |
24544 | cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
24545 | cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
24546 | cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
24547 | cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
24548 | cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
24549 | cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
24550 | cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
24551 | cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
24552 | cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
24553 | cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
24554 | cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
24555 | cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
24556 | cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
24557 | cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
24558 | cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 24559 | |
c19d1205 | 24560 | /* Monadic operations. */ |
21d799b5 NC |
24561 | cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
24562 | cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
24563 | cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
24564 | |
24565 | /* Dyadic operations. */ | |
21d799b5 NC |
24566 | cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
24567 | cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
24568 | cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
24569 | cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
24570 | cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
24571 | cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
24572 | cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
24573 | cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
24574 | cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 24575 | |
c19d1205 | 24576 | /* Comparisons. */ |
21d799b5 NC |
24577 | cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
24578 | cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z), | |
24579 | cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
24580 | cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 24581 | |
62f3b8c8 PB |
24582 | /* Double precision load/store are still present on single precision |
24583 | implementations. */ | |
24584 | cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
24585 | cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
55881a11 MGD |
24586 | cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), |
24587 | cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
24588 | cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
24589 | cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
24590 | cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
24591 | cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
24592 | cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
24593 | cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
62f3b8c8 | 24594 | |
c921be7d NC |
24595 | #undef ARM_VARIANT |
24596 | #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ | |
24597 | ||
c19d1205 | 24598 | /* Moves and type conversions. */ |
21d799b5 NC |
24599 | cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), |
24600 | cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
24601 | cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
24602 | cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
24603 | cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
24604 | cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
24605 | cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
24606 | cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
24607 | cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
24608 | cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
24609 | cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
24610 | cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 | 24611 | |
c19d1205 | 24612 | /* Monadic operations. */ |
21d799b5 NC |
24613 | cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
24614 | cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), | |
24615 | cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
c19d1205 ZW |
24616 | |
24617 | /* Dyadic operations. */ | |
21d799b5 NC |
24618 | cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
24619 | cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
24620 | cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
24621 | cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
24622 | cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
24623 | cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
24624 | cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
24625 | cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
24626 | cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
b99bd4ef | 24627 | |
c19d1205 | 24628 | /* Comparisons. */ |
21d799b5 NC |
24629 | cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
24630 | cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd), | |
24631 | cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
24632 | cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd), | |
c19d1205 | 24633 | |
037e8744 JB |
24634 | /* Instructions which may belong to either the Neon or VFP instruction sets. |
24635 | Individual encoder functions perform additional architecture checks. */ | |
c921be7d NC |
24636 | #undef ARM_VARIANT |
24637 | #define ARM_VARIANT & fpu_vfp_ext_v1xd | |
24638 | #undef THUMB_VARIANT | |
24639 | #define THUMB_VARIANT & fpu_vfp_ext_v1xd | |
24640 | ||
037e8744 JB |
24641 | /* These mnemonics are unique to VFP. */ |
24642 | NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), | |
24643 | NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), | |
21d799b5 NC |
24644 | nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
24645 | nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
24646 | nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
037e8744 JB |
24647 | NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), |
24648 | NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), | |
24649 | NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), | |
24650 | ||
24651 | /* Mnemonics shared by Neon and VFP. */ | |
21d799b5 | 24652 | nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), |
037e8744 | 24653 | |
55881a11 MGD |
24654 | NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
24655 | NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
24656 | NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
24657 | NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
24658 | NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
24659 | NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
037e8744 | 24660 | |
dd9634d9 | 24661 | mnCEF(vcvt, _vcvt, 3, (RNSDQMQ, RNSDQMQ, oI32z), neon_cvt), |
e3e535bc | 24662 | nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr), |
dd9634d9 AV |
24663 | MNCEF(vcvtb, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtb), |
24664 | MNCEF(vcvtt, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtt), | |
f31fef98 | 24665 | |
037e8744 JB |
24666 | |
24667 | /* NOTE: All VMOV encoding is special-cased! */ | |
037e8744 JB |
24668 | NCE(vmovq, 0, 1, (VMOV), neon_mov), |
24669 | ||
32c36c3c AV |
24670 | #undef THUMB_VARIANT |
24671 | /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded | |
24672 | by different feature bits. Since we are setting the Thumb guard, we can | |
24673 | require Thumb-1 which makes it a nop guard and set the right feature bit in | |
24674 | do_vldr_vstr (). */ | |
24675 | #define THUMB_VARIANT & arm_ext_v4t | |
24676 | NCE(vldr, d100b00, 2, (VLDR, ADDRGLDC), vldr_vstr), | |
24677 | NCE(vstr, d000b00, 2, (VLDR, ADDRGLDC), vldr_vstr), | |
24678 | ||
9db2f6b4 RL |
24679 | #undef ARM_VARIANT |
24680 | #define ARM_VARIANT & arm_ext_fp16 | |
24681 | #undef THUMB_VARIANT | |
24682 | #define THUMB_VARIANT & arm_ext_fp16 | |
24683 | /* New instructions added from v8.2, allowing the extraction and insertion of | |
24684 | the upper 16 bits of a 32-bit vector register. */ | |
24685 | NCE (vmovx, eb00a40, 2, (RVS, RVS), neon_movhf), | |
24686 | NCE (vins, eb00ac0, 2, (RVS, RVS), neon_movhf), | |
24687 | ||
dec41383 JW |
24688 | /* New backported fma/fms instructions optional in v8.2. */ |
24689 | NCE (vfmal, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmal), | |
24690 | NCE (vfmsl, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmsl), | |
24691 | ||
c921be7d NC |
24692 | #undef THUMB_VARIANT |
24693 | #define THUMB_VARIANT & fpu_neon_ext_v1 | |
24694 | #undef ARM_VARIANT | |
24695 | #define ARM_VARIANT & fpu_neon_ext_v1 | |
24696 | ||
5287ad62 JB |
24697 | /* Data processing with three registers of the same length. */ |
24698 | /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ | |
24699 | NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), | |
24700 | NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), | |
5287ad62 | 24701 | NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), |
5287ad62 | 24702 | NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), |
5287ad62 JB |
24703 | NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), |
24704 | /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ | |
5287ad62 | 24705 | NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), |
5287ad62 | 24706 | NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), |
627907b7 | 24707 | NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), |
627907b7 | 24708 | NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), |
5287ad62 | 24709 | /* If not immediate, fall back to neon_dyadic_i64_su. |
5150f0d8 AV |
24710 | shl should accept I8 I16 I32 I64, |
24711 | qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */ | |
24712 | nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl), | |
24713 | nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl), | |
5287ad62 | 24714 | /* Logic ops, types optional & ignored. */ |
4316f0d2 | 24715 | nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), |
4316f0d2 | 24716 | nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), |
4316f0d2 | 24717 | nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), |
4316f0d2 | 24718 | nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), |
4316f0d2 | 24719 | nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic), |
5287ad62 JB |
24720 | /* Bitfield ops, untyped. */ |
24721 | NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
24722 | NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
24723 | NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
24724 | NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
24725 | NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
24726 | NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
cc933301 | 24727 | /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */ |
21d799b5 | 24728 | nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), |
21d799b5 | 24729 | nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), |
21d799b5 | 24730 | nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), |
5287ad62 JB |
24731 | /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall |
24732 | back to neon_dyadic_if_su. */ | |
21d799b5 NC |
24733 | nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), |
24734 | nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
24735 | nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), | |
24736 | nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
24737 | nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
24738 | nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
24739 | nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
24740 | nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
428e3f1f | 24741 | /* Comparison. Type I8 I16 I32 F32. */ |
21d799b5 NC |
24742 | nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), |
24743 | nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), | |
5287ad62 | 24744 | /* As above, D registers only. */ |
21d799b5 NC |
24745 | nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), |
24746 | nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), | |
5287ad62 | 24747 | /* Int and float variants, signedness unimportant. */ |
21d799b5 NC |
24748 | nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
24749 | nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), | |
24750 | nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), | |
5287ad62 | 24751 | /* Add/sub take types I8 I16 I32 I64 F32. */ |
21d799b5 NC |
24752 | nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
24753 | nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), | |
5287ad62 JB |
24754 | /* vtst takes sizes 8, 16, 32. */ |
24755 | NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), | |
24756 | NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), | |
24757 | /* VMUL takes I8 I16 I32 F32 P8. */ | |
21d799b5 | 24758 | nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), |
5287ad62 | 24759 | /* VQD{R}MULH takes S16 S32. */ |
21d799b5 | 24760 | nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), |
21d799b5 | 24761 | nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), |
5287ad62 JB |
24762 | NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), |
24763 | NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
24764 | NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), | |
24765 | NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
92559b5b PB |
24766 | NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), |
24767 | NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
24768 | NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), | |
24769 | NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
5287ad62 JB |
24770 | NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), |
24771 | NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
24772 | NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), | |
24773 | NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
d6b4b13e | 24774 | /* ARM v8.1 extension. */ |
643afb90 MW |
24775 | nUF (vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah), |
24776 | nUF (vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah), | |
24777 | nUF (vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah), | |
5287ad62 JB |
24778 | |
24779 | /* Two address, int/float. Types S8 S16 S32 F32. */ | |
5287ad62 | 24780 | NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), |
5287ad62 JB |
24781 | NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), |
24782 | ||
24783 | /* Data processing with two registers and a shift amount. */ | |
24784 | /* Right shifts, and variants with rounding. | |
24785 | Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ | |
5287ad62 | 24786 | NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), |
5287ad62 JB |
24787 | NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), |
24788 | NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
24789 | NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
24790 | NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
24791 | NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
24792 | /* Shift and insert. Sizes accepted 8 16 32 64. */ | |
5287ad62 | 24793 | NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), |
5287ad62 JB |
24794 | NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), |
24795 | /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ | |
5287ad62 JB |
24796 | NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), |
24797 | /* Right shift immediate, saturating & narrowing, with rounding variants. | |
24798 | Types accepted S16 S32 S64 U16 U32 U64. */ | |
24799 | NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
24800 | NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
24801 | /* As above, unsigned. Types accepted S16 S32 S64. */ | |
24802 | NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
24803 | NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
24804 | /* Right shift narrowing. Types accepted I16 I32 I64. */ | |
24805 | NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
24806 | NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
24807 | /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ | |
21d799b5 | 24808 | nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll), |
5287ad62 | 24809 | /* CVT with optional immediate for fixed-point variant. */ |
21d799b5 | 24810 | nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), |
b7fc2769 | 24811 | |
4316f0d2 | 24812 | nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn), |
5287ad62 JB |
24813 | |
24814 | /* Data processing, three registers of different lengths. */ | |
24815 | /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ | |
24816 | NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), | |
5287ad62 JB |
24817 | /* If not scalar, fall back to neon_dyadic_long. |
24818 | Vector types as above, scalar types S16 S32 U16 U32. */ | |
21d799b5 NC |
24819 | nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), |
24820 | nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), | |
5287ad62 JB |
24821 | /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ |
24822 | NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
24823 | NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
24824 | /* Dyadic, narrowing insns. Types I16 I32 I64. */ | |
24825 | NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
24826 | NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
24827 | NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
24828 | NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
24829 | /* Saturating doubling multiplies. Types S16 S32. */ | |
21d799b5 NC |
24830 | nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), |
24831 | nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
24832 | nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
5287ad62 JB |
24833 | /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types |
24834 | S16 S32 U16 U32. */ | |
21d799b5 | 24835 | nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), |
5287ad62 JB |
24836 | |
24837 | /* Extract. Size 8. */ | |
3b8d421e PB |
24838 | NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), |
24839 | NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), | |
5287ad62 JB |
24840 | |
24841 | /* Two registers, miscellaneous. */ | |
24842 | /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ | |
5287ad62 | 24843 | NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), |
5287ad62 | 24844 | NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), |
5287ad62 JB |
24845 | NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), |
24846 | /* Vector replicate. Sizes 8 16 32. */ | |
21d799b5 | 24847 | nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup), |
5287ad62 JB |
24848 | /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ |
24849 | NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), | |
24850 | /* VMOVN. Types I16 I32 I64. */ | |
21d799b5 | 24851 | nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn), |
5287ad62 | 24852 | /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ |
21d799b5 | 24853 | nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn), |
5287ad62 | 24854 | /* VQMOVUN. Types S16 S32 S64. */ |
21d799b5 | 24855 | nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun), |
5287ad62 JB |
24856 | /* VZIP / VUZP. Sizes 8 16 32. */ |
24857 | NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
24858 | NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), | |
24859 | NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
24860 | NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), | |
24861 | /* VQABS / VQNEG. Types S8 S16 S32. */ | |
5287ad62 | 24862 | NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), |
5287ad62 JB |
24863 | NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), |
24864 | /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ | |
24865 | NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), | |
24866 | NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), | |
24867 | NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), | |
24868 | NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), | |
cc933301 | 24869 | /* Reciprocal estimates. Types U32 F16 F32. */ |
5287ad62 JB |
24870 | NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), |
24871 | NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), | |
24872 | NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), | |
24873 | NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), | |
24874 | /* VCLS. Types S8 S16 S32. */ | |
5287ad62 JB |
24875 | NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), |
24876 | /* VCLZ. Types I8 I16 I32. */ | |
5287ad62 JB |
24877 | NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), |
24878 | /* VCNT. Size 8. */ | |
24879 | NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), | |
24880 | NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), | |
24881 | /* Two address, untyped. */ | |
24882 | NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), | |
24883 | NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), | |
24884 | /* VTRN. Sizes 8 16 32. */ | |
21d799b5 NC |
24885 | nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn), |
24886 | nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn), | |
5287ad62 JB |
24887 | |
24888 | /* Table lookup. Size 8. */ | |
24889 | NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
24890 | NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
24891 | ||
c921be7d NC |
24892 | #undef THUMB_VARIANT |
24893 | #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext | |
24894 | #undef ARM_VARIANT | |
24895 | #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext | |
24896 | ||
5287ad62 | 24897 | /* Neon element/structure load/store. */ |
21d799b5 NC |
24898 | nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), |
24899 | nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
24900 | nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
24901 | nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
24902 | nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
24903 | nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
24904 | nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
24905 | nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
5287ad62 | 24906 | |
c921be7d | 24907 | #undef THUMB_VARIANT |
74db7efb NC |
24908 | #define THUMB_VARIANT & fpu_vfp_ext_v3xd |
24909 | #undef ARM_VARIANT | |
24910 | #define ARM_VARIANT & fpu_vfp_ext_v3xd | |
62f3b8c8 PB |
24911 | cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const), |
24912 | cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
24913 | cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
24914 | cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
24915 | cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
24916 | cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
24917 | cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
24918 | cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
24919 | cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
24920 | ||
74db7efb | 24921 | #undef THUMB_VARIANT |
c921be7d NC |
24922 | #define THUMB_VARIANT & fpu_vfp_ext_v3 |
24923 | #undef ARM_VARIANT | |
24924 | #define ARM_VARIANT & fpu_vfp_ext_v3 | |
24925 | ||
21d799b5 | 24926 | cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const), |
21d799b5 | 24927 | cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 24928 | cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 24929 | cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 24930 | cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 24931 | cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 24932 | cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 24933 | cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 24934 | cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
c19d1205 | 24935 | |
74db7efb NC |
24936 | #undef ARM_VARIANT |
24937 | #define ARM_VARIANT & fpu_vfp_ext_fma | |
24938 | #undef THUMB_VARIANT | |
24939 | #define THUMB_VARIANT & fpu_vfp_ext_fma | |
d58196e0 | 24940 | /* Mnemonics shared by Neon, VFP and MVE. These are included in the |
62f3b8c8 PB |
24941 | VFP FMA variant; NEON and VFP FMA always includes the NEON |
24942 | FMA instructions. */ | |
d58196e0 AV |
24943 | mnCEF(vfma, _vfma, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_fmac), |
24944 | mnCEF(vfms, _vfms, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), neon_fmac), | |
24945 | ||
62f3b8c8 PB |
24946 | /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas; |
24947 | the v form should always be used. */ | |
24948 | cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
24949 | cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
24950 | cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
24951 | cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
24952 | nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
24953 | nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
24954 | ||
5287ad62 | 24955 | #undef THUMB_VARIANT |
c921be7d NC |
24956 | #undef ARM_VARIANT |
24957 | #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */ | |
24958 | ||
21d799b5 NC |
24959 | cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
24960 | cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
24961 | cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
24962 | cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
24963 | cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
24964 | cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
24965 | cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
24966 | cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 | 24967 | |
c921be7d NC |
24968 | #undef ARM_VARIANT |
24969 | #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */ | |
24970 | ||
21d799b5 NC |
24971 | cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc), |
24972 | cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc), | |
24973 | cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc), | |
24974 | cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd), | |
24975 | cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd), | |
24976 | cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd), | |
24977 | cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc), | |
24978 | cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc), | |
24979 | cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc), | |
74db7efb NC |
24980 | cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), |
24981 | cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
24982 | cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
24983 | cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
24984 | cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
24985 | cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
21d799b5 NC |
24986 | cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), |
24987 | cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
24988 | cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
24989 | cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd), | |
24990 | cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn), | |
24991 | cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
24992 | cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
24993 | cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
24994 | cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
24995 | cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
24996 | cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
74db7efb NC |
24997 | cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn), |
24998 | cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn), | |
24999 | cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn), | |
21d799b5 NC |
25000 | cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn), |
25001 | cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm), | |
25002 | cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc), | |
25003 | cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc), | |
25004 | cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc), | |
25005 | cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn), | |
25006 | cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn), | |
25007 | cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn), | |
25008 | cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25009 | cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25010 | cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25011 | cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25012 | cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25013 | cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25014 | cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25015 | cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25016 | cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25017 | cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
74db7efb NC |
25018 | cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
25019 | cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25020 | cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25021 | cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
25022 | cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
25023 | cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25024 | cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25025 | cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25026 | cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25027 | cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25028 | cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25029 | cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25030 | cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
74db7efb NC |
25031 | cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
25032 | cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25033 | cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25034 | cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25035 | cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25036 | cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
25037 | cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), |
25038 | cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
25039 | cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
25040 | cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
25041 | cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25042 | cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25043 | cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25044 | cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25045 | cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25046 | cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25047 | cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25048 | cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25049 | cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25050 | cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25051 | cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25052 | cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25053 | cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25054 | cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25055 | cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25056 | cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25057 | cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25058 | cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25059 | cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
25060 | cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25061 | cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25062 | cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25063 | cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25064 | cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
74db7efb NC |
25065 | cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
25066 | cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25067 | cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25068 | cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25069 | cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25070 | cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
25071 | cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
25072 | cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25073 | cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25074 | cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25075 | cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25076 | cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25077 | cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25078 | cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25079 | cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25080 | cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25081 | cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
25082 | cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25083 | cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25084 | cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25085 | cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25086 | cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25087 | cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25088 | cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25089 | cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25090 | cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25091 | cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25092 | cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25093 | cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25094 | cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25095 | cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25096 | cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25097 | cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25098 | cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25099 | cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25100 | cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
25101 | cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
25102 | cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
25103 | cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
25104 | cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25105 | cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25106 | cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25107 | cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25108 | cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25109 | cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25110 | cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25111 | cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25112 | cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25113 | cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn), | |
25114 | cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn), | |
25115 | cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn), | |
25116 | cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn), | |
25117 | cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn), | |
25118 | cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn), | |
25119 | cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25120 | cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25121 | cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25122 | cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn), | |
25123 | cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn), | |
25124 | cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn), | |
25125 | cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn), | |
25126 | cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn), | |
25127 | cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn), | |
25128 | cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25129 | cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25130 | cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25131 | cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25132 | cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 | 25133 | |
c921be7d NC |
25134 | #undef ARM_VARIANT |
25135 | #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ | |
25136 | ||
21d799b5 NC |
25137 | cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc), |
25138 | cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc), | |
25139 | cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc), | |
25140 | cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn), | |
25141 | cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn), | |
25142 | cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn), | |
25143 | cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25144 | cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25145 | cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25146 | cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25147 | cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25148 | cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25149 | cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25150 | cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25151 | cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25152 | cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25153 | cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25154 | cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25155 | cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25156 | cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25157 | cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), | |
25158 | cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25159 | cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25160 | cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25161 | cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25162 | cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25163 | cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25164 | cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25165 | cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25166 | cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25167 | cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25168 | cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25169 | cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25170 | cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25171 | cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25172 | cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25173 | cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25174 | cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25175 | cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25176 | cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25177 | cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25178 | cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25179 | cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25180 | cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25181 | cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25182 | cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25183 | cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25184 | cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25185 | cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25186 | cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25187 | cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25188 | cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25189 | cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25190 | cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25191 | cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25192 | cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25193 | cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
2d447fca | 25194 | |
c921be7d NC |
25195 | #undef ARM_VARIANT |
25196 | #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */ | |
25197 | ||
21d799b5 NC |
25198 | cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), |
25199 | cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
25200 | cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
25201 | cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
25202 | cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), | |
25203 | cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
25204 | cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
25205 | cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
25206 | cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd), | |
25207 | cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn), | |
25208 | cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd), | |
25209 | cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn), | |
25210 | cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd), | |
25211 | cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn), | |
74db7efb NC |
25212 | cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd), |
25213 | cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn), | |
25214 | cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd), | |
25215 | cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn), | |
25216 | cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn), | |
25217 | cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn), | |
25218 | cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn), | |
25219 | cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn), | |
25220 | cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn), | |
25221 | cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn), | |
21d799b5 NC |
25222 | cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn), |
25223 | cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn), | |
25224 | cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn), | |
25225 | cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn), | |
74db7efb NC |
25226 | cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc), |
25227 | cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd), | |
21d799b5 NC |
25228 | cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn), |
25229 | cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn), | |
25230 | cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn), | |
25231 | cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn), | |
74db7efb NC |
25232 | cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn), |
25233 | cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn), | |
25234 | cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn), | |
25235 | cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn), | |
25236 | cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn), | |
25237 | cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn), | |
21d799b5 NC |
25238 | cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn), |
25239 | cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn), | |
74db7efb NC |
25240 | cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple), |
25241 | cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
21d799b5 NC |
25242 | cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift), |
25243 | cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
25244 | cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
25245 | cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
25246 | cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
25247 | cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
25248 | cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn), | |
25249 | cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn), | |
25250 | cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn), | |
25251 | cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn), | |
25252 | cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
25253 | cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
25254 | cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
25255 | cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
25256 | cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
25257 | cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
25258 | cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn), | |
25259 | cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn), | |
25260 | cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn), | |
25261 | cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn), | |
25262 | cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
25263 | cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
25264 | cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
25265 | cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
25266 | cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
25267 | cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
25268 | cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
25269 | cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
74db7efb NC |
25270 | cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), |
25271 | cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
21d799b5 NC |
25272 | cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), |
25273 | cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
4ed7ed8d | 25274 | |
7fadb25d SD |
25275 | /* ARMv8.5-A instructions. */ |
25276 | #undef ARM_VARIANT | |
25277 | #define ARM_VARIANT & arm_ext_sb | |
25278 | #undef THUMB_VARIANT | |
25279 | #define THUMB_VARIANT & arm_ext_sb | |
25280 | TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs), | |
25281 | ||
dad0c3bf SD |
25282 | #undef ARM_VARIANT |
25283 | #define ARM_VARIANT & arm_ext_predres | |
25284 | #undef THUMB_VARIANT | |
25285 | #define THUMB_VARIANT & arm_ext_predres | |
25286 | CE("cfprctx", e070f93, 1, (RRnpc), rd), | |
25287 | CE("dvprctx", e070fb3, 1, (RRnpc), rd), | |
25288 | CE("cpprctx", e070ff3, 1, (RRnpc), rd), | |
25289 | ||
16a1fa25 | 25290 | /* ARMv8-M instructions. */ |
4ed7ed8d TP |
25291 | #undef ARM_VARIANT |
25292 | #define ARM_VARIANT NULL | |
25293 | #undef THUMB_VARIANT | |
25294 | #define THUMB_VARIANT & arm_ext_v8m | |
cf3cf39d TP |
25295 | ToU("sg", e97fe97f, 0, (), noargs), |
25296 | ToC("blxns", 4784, 1, (RRnpc), t_blx), | |
25297 | ToC("bxns", 4704, 1, (RRnpc), t_bx), | |
25298 | ToC("tt", e840f000, 2, (RRnpc, RRnpc), tt), | |
25299 | ToC("ttt", e840f040, 2, (RRnpc, RRnpc), tt), | |
25300 | ToC("tta", e840f080, 2, (RRnpc, RRnpc), tt), | |
25301 | ToC("ttat", e840f0c0, 2, (RRnpc, RRnpc), tt), | |
16a1fa25 TP |
25302 | |
25303 | /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the | |
25304 | instructions behave as nop if no VFP is present. */ | |
25305 | #undef THUMB_VARIANT | |
25306 | #define THUMB_VARIANT & arm_ext_v8m_main | |
cf3cf39d TP |
25307 | ToC("vlldm", ec300a00, 1, (RRnpc), rn), |
25308 | ToC("vlstm", ec200a00, 1, (RRnpc), rn), | |
4389b29a AV |
25309 | |
25310 | /* Armv8.1-M Mainline instructions. */ | |
25311 | #undef THUMB_VARIANT | |
25312 | #define THUMB_VARIANT & arm_ext_v8_1m_main | |
e39c1607 SD |
25313 | toU("cinc", _cinc, 3, (RRnpcsp, RR_ZR, COND), t_cond), |
25314 | toU("cinv", _cinv, 3, (RRnpcsp, RR_ZR, COND), t_cond), | |
25315 | toU("cneg", _cneg, 3, (RRnpcsp, RR_ZR, COND), t_cond), | |
25316 | toU("csel", _csel, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond), | |
25317 | toU("csetm", _csetm, 2, (RRnpcsp, COND), t_cond), | |
25318 | toU("cset", _cset, 2, (RRnpcsp, COND), t_cond), | |
25319 | toU("csinc", _csinc, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond), | |
25320 | toU("csinv", _csinv, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond), | |
25321 | toU("csneg", _csneg, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond), | |
25322 | ||
4389b29a | 25323 | toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future), |
f6b2b12d | 25324 | toU("bfcsel", _bfcsel, 4, (EXPs, EXPs, EXPs, COND), t_branch_future), |
f1c7f421 | 25325 | toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future), |
65d1bc05 | 25326 | toC("bfl", _bfl, 2, (EXPs, EXPs), t_branch_future), |
f1c7f421 | 25327 | toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future), |
60f993ce AV |
25328 | |
25329 | toU("dls", _dls, 2, (LR, RRnpcsp), t_loloop), | |
25330 | toU("wls", _wls, 3, (LR, RRnpcsp, EXP), t_loloop), | |
25331 | toU("le", _le, 2, (oLR, EXP), t_loloop), | |
4b5a202f | 25332 | |
efd6b359 | 25333 | ToC("clrm", e89f0000, 1, (CLRMLST), t_clrm), |
5ee91343 AV |
25334 | ToC("vscclrm", ec9f0a00, 1, (VRSDVLST), t_vscclrm), |
25335 | ||
25336 | #undef THUMB_VARIANT | |
25337 | #define THUMB_VARIANT & mve_ext | |
23d00a41 SD |
25338 | ToC("lsll", ea50010d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift), |
25339 | ToC("lsrl", ea50011f, 3, (RRe, RRo, I32), mve_scalar_shift), | |
25340 | ToC("asrl", ea50012d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift), | |
25341 | ToC("uqrshll", ea51010d, 3, (RRe, RRo, RRnpcsp), mve_scalar_shift), | |
25342 | ToC("sqrshrl", ea51012d, 3, (RRe, RRo, RRnpcsp), mve_scalar_shift), | |
25343 | ToC("uqshll", ea51010f, 3, (RRe, RRo, I32), mve_scalar_shift), | |
25344 | ToC("urshrl", ea51011f, 3, (RRe, RRo, I32), mve_scalar_shift), | |
25345 | ToC("srshrl", ea51012f, 3, (RRe, RRo, I32), mve_scalar_shift), | |
25346 | ToC("sqshll", ea51013f, 3, (RRe, RRo, I32), mve_scalar_shift), | |
25347 | ToC("uqrshl", ea500f0d, 2, (RRnpcsp, RRnpcsp), mve_scalar_shift), | |
25348 | ToC("sqrshr", ea500f2d, 2, (RRnpcsp, RRnpcsp), mve_scalar_shift), | |
25349 | ToC("uqshl", ea500f0f, 2, (RRnpcsp, I32), mve_scalar_shift), | |
25350 | ToC("urshr", ea500f1f, 2, (RRnpcsp, I32), mve_scalar_shift), | |
25351 | ToC("srshr", ea500f2f, 2, (RRnpcsp, I32), mve_scalar_shift), | |
25352 | ToC("sqshl", ea500f3f, 2, (RRnpcsp, I32), mve_scalar_shift), | |
1b883319 AV |
25353 | |
25354 | ToC("vpt", ee410f00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25355 | ToC("vptt", ee018f00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25356 | ToC("vpte", ee418f00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25357 | ToC("vpttt", ee014f00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25358 | ToC("vptte", ee01cf00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25359 | ToC("vptet", ee41cf00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25360 | ToC("vptee", ee414f00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25361 | ToC("vptttt", ee012f00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25362 | ToC("vpttte", ee016f00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25363 | ToC("vpttet", ee01ef00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25364 | ToC("vpttee", ee01af00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25365 | ToC("vptett", ee41af00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25366 | ToC("vptete", ee41ef00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25367 | ToC("vpteet", ee416f00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25368 | ToC("vpteee", ee412f00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25369 | ||
5ee91343 AV |
25370 | ToC("vpst", fe710f4d, 0, (), mve_vpt), |
25371 | ToC("vpstt", fe318f4d, 0, (), mve_vpt), | |
25372 | ToC("vpste", fe718f4d, 0, (), mve_vpt), | |
25373 | ToC("vpsttt", fe314f4d, 0, (), mve_vpt), | |
25374 | ToC("vpstte", fe31cf4d, 0, (), mve_vpt), | |
25375 | ToC("vpstet", fe71cf4d, 0, (), mve_vpt), | |
25376 | ToC("vpstee", fe714f4d, 0, (), mve_vpt), | |
25377 | ToC("vpstttt", fe312f4d, 0, (), mve_vpt), | |
25378 | ToC("vpsttte", fe316f4d, 0, (), mve_vpt), | |
25379 | ToC("vpsttet", fe31ef4d, 0, (), mve_vpt), | |
25380 | ToC("vpsttee", fe31af4d, 0, (), mve_vpt), | |
25381 | ToC("vpstett", fe71af4d, 0, (), mve_vpt), | |
25382 | ToC("vpstete", fe71ef4d, 0, (), mve_vpt), | |
25383 | ToC("vpsteet", fe716f4d, 0, (), mve_vpt), | |
25384 | ToC("vpsteee", fe712f4d, 0, (), mve_vpt), | |
25385 | ||
a302e574 | 25386 | /* MVE and MVE FP only. */ |
7df54120 | 25387 | mToC("vhcadd", ee000f00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vhcadd), |
c2dafc2a AV |
25388 | mCEF(vadc, _vadc, 3, (RMQ, RMQ, RMQ), mve_vadc), |
25389 | mCEF(vadci, _vadci, 3, (RMQ, RMQ, RMQ), mve_vadc), | |
25390 | mToC("vsbc", fe300f00, 3, (RMQ, RMQ, RMQ), mve_vsbc), | |
25391 | mToC("vsbci", fe301f00, 3, (RMQ, RMQ, RMQ), mve_vsbc), | |
886e1c73 | 25392 | mCEF(vmullb, _vmullb, 3, (RMQ, RMQ, RMQ), mve_vmull), |
a302e574 AV |
25393 | mCEF(vabav, _vabav, 3, (RRnpcsp, RMQ, RMQ), mve_vabav), |
25394 | mCEF(vmladav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25395 | mCEF(vmladava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25396 | mCEF(vmladavx, _vmladavx, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25397 | mCEF(vmladavax, _vmladavax, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25398 | mCEF(vmlav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25399 | mCEF(vmlava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25400 | mCEF(vmlsdav, _vmlsdav, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25401 | mCEF(vmlsdava, _vmlsdava, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25402 | mCEF(vmlsdavx, _vmlsdavx, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25403 | mCEF(vmlsdavax, _vmlsdavax, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25404 | ||
35c228db AV |
25405 | mCEF(vst20, _vst20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld), |
25406 | mCEF(vst21, _vst21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld), | |
25407 | mCEF(vst40, _vst40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), | |
25408 | mCEF(vst41, _vst41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), | |
25409 | mCEF(vst42, _vst42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), | |
25410 | mCEF(vst43, _vst43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), | |
25411 | mCEF(vld20, _vld20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld), | |
25412 | mCEF(vld21, _vld21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld), | |
25413 | mCEF(vld40, _vld40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), | |
25414 | mCEF(vld41, _vld41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), | |
25415 | mCEF(vld42, _vld42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), | |
25416 | mCEF(vld43, _vld43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), | |
f5f10c66 AV |
25417 | mCEF(vstrb, _vstrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr), |
25418 | mCEF(vstrh, _vstrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr), | |
25419 | mCEF(vstrw, _vstrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr), | |
25420 | mCEF(vstrd, _vstrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr), | |
25421 | mCEF(vldrb, _vldrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr), | |
25422 | mCEF(vldrh, _vldrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr), | |
25423 | mCEF(vldrw, _vldrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr), | |
25424 | mCEF(vldrd, _vldrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr), | |
35c228db | 25425 | |
57785aa2 AV |
25426 | mCEF(vmovnt, _vmovnt, 2, (RMQ, RMQ), mve_movn), |
25427 | mCEF(vmovnb, _vmovnb, 2, (RMQ, RMQ), mve_movn), | |
c2dafc2a | 25428 | mCEF(vbrsr, _vbrsr, 3, (RMQ, RMQ, RR), mve_vbrsr), |
26c1e780 AV |
25429 | mCEF(vaddlv, _vaddlv, 3, (RRe, RRo, RMQ), mve_vaddlv), |
25430 | mCEF(vaddlva, _vaddlva, 3, (RRe, RRo, RMQ), mve_vaddlv), | |
25431 | mCEF(vaddv, _vaddv, 2, (RRe, RMQ), mve_vaddv), | |
25432 | mCEF(vaddva, _vaddva, 2, (RRe, RMQ), mve_vaddv), | |
b409bdb6 AV |
25433 | mCEF(vddup, _vddup, 3, (RMQ, RRe, EXPi), mve_viddup), |
25434 | mCEF(vdwdup, _vdwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup), | |
25435 | mCEF(vidup, _vidup, 3, (RMQ, RRe, EXPi), mve_viddup), | |
25436 | mCEF(viwdup, _viwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup), | |
935295b5 AV |
25437 | mToC("vmaxa", ee330e81, 2, (RMQ, RMQ), mve_vmaxa_vmina), |
25438 | mToC("vmina", ee331e81, 2, (RMQ, RMQ), mve_vmaxa_vmina), | |
13ccd4c0 AV |
25439 | mCEF(vmaxv, _vmaxv, 2, (RR, RMQ), mve_vmaxv), |
25440 | mCEF(vmaxav, _vmaxav, 2, (RR, RMQ), mve_vmaxv), | |
25441 | mCEF(vminv, _vminv, 2, (RR, RMQ), mve_vmaxv), | |
25442 | mCEF(vminav, _vminav, 2, (RR, RMQ), mve_vmaxv), | |
57785aa2 | 25443 | |
93925576 AV |
25444 | mCEF(vmlaldav, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), |
25445 | mCEF(vmlaldava, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), | |
25446 | mCEF(vmlaldavx, _vmlaldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), | |
25447 | mCEF(vmlaldavax, _vmlaldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), | |
25448 | mCEF(vmlalv, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), | |
25449 | mCEF(vmlalva, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), | |
25450 | mCEF(vmlsldav, _vmlsldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), | |
25451 | mCEF(vmlsldava, _vmlsldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), | |
25452 | mCEF(vmlsldavx, _vmlsldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), | |
25453 | mCEF(vmlsldavax, _vmlsldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), | |
25454 | mToC("vrmlaldavh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25455 | mToC("vrmlaldavha",ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25456 | mCEF(vrmlaldavhx, _vrmlaldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25457 | mCEF(vrmlaldavhax, _vrmlaldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25458 | mToC("vrmlalvh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25459 | mToC("vrmlalvha", ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25460 | mCEF(vrmlsldavh, _vrmlsldavh, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25461 | mCEF(vrmlsldavha, _vrmlsldavha, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25462 | mCEF(vrmlsldavhx, _vrmlsldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25463 | mCEF(vrmlsldavhax, _vrmlsldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25464 | ||
2d78f95b AV |
25465 | mToC("vmlas", ee011e40, 3, (RMQ, RMQ, RR), mve_vmlas), |
25466 | mToC("vmulh", ee010e01, 3, (RMQ, RMQ, RMQ), mve_vmulh), | |
25467 | mToC("vrmulh", ee011e01, 3, (RMQ, RMQ, RMQ), mve_vmulh), | |
3063888e AV |
25468 | mToC("vpnot", fe310f4d, 0, (), mve_vpnot), |
25469 | mToC("vpsel", fe310f01, 3, (RMQ, RMQ, RMQ), mve_vpsel), | |
2d78f95b | 25470 | |
8b8b22a4 AV |
25471 | mToC("vqdmladh", ee000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), |
25472 | mToC("vqdmladhx", ee001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), | |
25473 | mToC("vqrdmladh", ee000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), | |
25474 | mToC("vqrdmladhx",ee001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), | |
25475 | mToC("vqdmlsdh", fe000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), | |
25476 | mToC("vqdmlsdhx", fe001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), | |
25477 | mToC("vqrdmlsdh", fe000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), | |
25478 | mToC("vqrdmlsdhx",fe001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), | |
42b16635 AV |
25479 | mToC("vqdmlah", ee000e60, 3, (RMQ, RMQ, RR), mve_vqdmlah), |
25480 | mToC("vqdmlash", ee001e60, 3, (RMQ, RMQ, RR), mve_vqdmlah), | |
25481 | mToC("vqrdmlash", ee001e40, 3, (RMQ, RMQ, RR), mve_vqdmlah), | |
35d1cfc2 AV |
25482 | mToC("vqdmullt", ee301f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull), |
25483 | mToC("vqdmullb", ee300f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull), | |
1be7aba3 AV |
25484 | mCEF(vqmovnt, _vqmovnt, 2, (RMQ, RMQ), mve_vqmovn), |
25485 | mCEF(vqmovnb, _vqmovnb, 2, (RMQ, RMQ), mve_vqmovn), | |
25486 | mCEF(vqmovunt, _vqmovunt, 2, (RMQ, RMQ), mve_vqmovn), | |
25487 | mCEF(vqmovunb, _vqmovunb, 2, (RMQ, RMQ), mve_vqmovn), | |
8b8b22a4 | 25488 | |
4aa88b50 AV |
25489 | mCEF(vshrnt, _vshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), |
25490 | mCEF(vshrnb, _vshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25491 | mCEF(vrshrnt, _vrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25492 | mCEF(vrshrnb, _vrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25493 | mCEF(vqshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25494 | mCEF(vqshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25495 | mCEF(vqshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25496 | mCEF(vqshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25497 | mCEF(vqrshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25498 | mCEF(vqrshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25499 | mCEF(vqrshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25500 | mCEF(vqrshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25501 | ||
acca5630 AV |
25502 | mToC("vshlc", eea00fc0, 3, (RMQ, RR, I32z), mve_vshlc), |
25503 | mToC("vshllt", ee201e00, 3, (RMQ, RMQ, I32), mve_vshll), | |
25504 | mToC("vshllb", ee200e00, 3, (RMQ, RMQ, I32), mve_vshll), | |
25505 | ||
1f6234a3 AV |
25506 | toU("dlstp", _dlstp, 2, (LR, RR), t_loloop), |
25507 | toU("wlstp", _wlstp, 3, (LR, RR, EXP), t_loloop), | |
25508 | toU("letp", _letp, 2, (LR, EXP), t_loloop), | |
25509 | toU("lctp", _lctp, 0, (), t_loloop), | |
25510 | ||
5d281bf0 AV |
25511 | #undef THUMB_VARIANT |
25512 | #define THUMB_VARIANT & mve_fp_ext | |
25513 | mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul), | |
f30ee27c | 25514 | mToC("vfmas", ee311e40, 3, (RMQ, RMQ, RR), mve_vfmas), |
935295b5 AV |
25515 | mToC("vmaxnma", ee3f0e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma), |
25516 | mToC("vminnma", ee3f1e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma), | |
8cd78170 AV |
25517 | mToC("vmaxnmv", eeee0f00, 2, (RR, RMQ), mve_vmaxnmv), |
25518 | mToC("vmaxnmav",eeec0f00, 2, (RR, RMQ), mve_vmaxnmv), | |
25519 | mToC("vminnmv", eeee0f80, 2, (RR, RMQ), mve_vmaxnmv), | |
25520 | mToC("vminnmav",eeec0f80, 2, (RR, RMQ), mve_vmaxnmv), | |
5d281bf0 | 25521 | |
5ee91343 | 25522 | #undef ARM_VARIANT |
57785aa2 | 25523 | #define ARM_VARIANT & fpu_vfp_ext_v1 |
5ee91343 AV |
25524 | #undef THUMB_VARIANT |
25525 | #define THUMB_VARIANT & arm_ext_v6t2 | |
a8465a06 AV |
25526 | mnCEF(vmla, _vmla, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mac_maybe_scalar), |
25527 | mnCEF(vmul, _vmul, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mul), | |
5ee91343 | 25528 | |
57785aa2 AV |
25529 | mcCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
25530 | ||
25531 | #undef ARM_VARIANT | |
25532 | #define ARM_VARIANT & fpu_vfp_ext_v1xd | |
25533 | ||
25534 | MNCE(vmov, 0, 1, (VMOV), neon_mov), | |
25535 | mcCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
25536 | mcCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
25537 | mcCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic), | |
25538 | ||
886e1c73 AV |
25539 | mCEF(vmullt, _vmullt, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ), mve_vmull), |
25540 | mnCEF(vadd, _vadd, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i), | |
25541 | mnCEF(vsub, _vsub, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i), | |
5ee91343 | 25542 | |
485dee97 AV |
25543 | MNCEF(vabs, 1b10300, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg), |
25544 | MNCEF(vneg, 1b10380, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg), | |
25545 | ||
57785aa2 AV |
25546 | mCEF(vmovlt, _vmovlt, 1, (VMOV), mve_movl), |
25547 | mCEF(vmovlb, _vmovlb, 1, (VMOV), mve_movl), | |
25548 | ||
1b883319 AV |
25549 | mnCE(vcmp, _vcmp, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp), |
25550 | mnCE(vcmpe, _vcmpe, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp), | |
25551 | ||
57785aa2 AV |
25552 | #undef ARM_VARIANT |
25553 | #define ARM_VARIANT & fpu_vfp_ext_v2 | |
25554 | ||
25555 | mcCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), | |
25556 | mcCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
25557 | mcCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), | |
25558 | mcCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), | |
25559 | ||
dd9634d9 AV |
25560 | #undef ARM_VARIANT |
25561 | #define ARM_VARIANT & fpu_vfp_ext_armv8xd | |
25562 | mnUF(vcvta, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvta), | |
25563 | mnUF(vcvtp, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtp), | |
25564 | mnUF(vcvtn, _vcvta, 3, (RNSDQMQ, oRNSDQMQ, oI32z), neon_cvtn), | |
25565 | mnUF(vcvtm, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtm), | |
935295b5 AV |
25566 | mnUF(vmaxnm, _vmaxnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm), |
25567 | mnUF(vminnm, _vminnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm), | |
dd9634d9 AV |
25568 | |
25569 | #undef ARM_VARIANT | |
5ee91343 | 25570 | #define ARM_VARIANT & fpu_neon_ext_v1 |
f601a00c | 25571 | mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su), |
5ee91343 AV |
25572 | mnUF(vabdl, _vabdl, 3, (RNQMQ, RNDMQ, RNDMQ), neon_dyadic_long), |
25573 | mnUF(vaddl, _vaddl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long), | |
25574 | mnUF(vsubl, _vsubl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long), | |
f601a00c AV |
25575 | mnUF(vand, _vand, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic), |
25576 | mnUF(vbic, _vbic, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic), | |
25577 | mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic), | |
25578 | mnUF(vorn, _vorn, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic), | |
25579 | mnUF(veor, _veor, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_logic), | |
f30ee27c AV |
25580 | MNUF(vcls, 1b00400, 2, (RNDQMQ, RNDQMQ), neon_cls), |
25581 | MNUF(vclz, 1b00480, 2, (RNDQMQ, RNDQMQ), neon_clz), | |
b409bdb6 | 25582 | mnCE(vdup, _vdup, 2, (RNDQMQ, RR_RNSC), neon_dup), |
7df54120 AV |
25583 | MNUF(vhadd, 00000000, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su), |
25584 | MNUF(vrhadd, 00000100, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_i_su), | |
25585 | MNUF(vhsub, 00000200, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su), | |
935295b5 AV |
25586 | mnUF(vmin, _vmin, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su), |
25587 | mnUF(vmax, _vmax, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su), | |
a8465a06 AV |
25588 | MNUF(vqadd, 0000010, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su), |
25589 | MNUF(vqsub, 0000210, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su), | |
1a186d29 AV |
25590 | mnUF(vmvn, _vmvn, 2, (RNDQMQ, RNDQMQ_Ibig), neon_mvn), |
25591 | MNUF(vqabs, 1b00700, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg), | |
25592 | MNUF(vqneg, 1b00780, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg), | |
42b16635 AV |
25593 | mnUF(vqrdmlah, _vqrdmlah,3, (RNDQMQ, oRNDQMQ, RNDQ_RNSC_RR), neon_qrdmlah), |
25594 | mnUF(vqdmulh, _vqdmulh, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh), | |
25595 | mnUF(vqrdmulh, _vqrdmulh,3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh), | |
1be7aba3 AV |
25596 | MNUF(vqrshl, 0000510, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl), |
25597 | MNUF(vrshl, 0000500, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl), | |
4401c241 AV |
25598 | MNUF(vshr, 0800010, 3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm), |
25599 | MNUF(vrshr, 0800210, 3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm), | |
25600 | MNUF(vsli, 1800510, 3, (RNDQMQ, oRNDQMQ, I63), neon_sli), | |
25601 | MNUF(vsri, 1800410, 3, (RNDQMQ, oRNDQMQ, I64z), neon_sri), | |
25602 | MNUF(vrev64, 1b00000, 2, (RNDQMQ, RNDQMQ), neon_rev), | |
25603 | MNUF(vrev32, 1b00080, 2, (RNDQMQ, RNDQMQ), neon_rev), | |
25604 | MNUF(vrev16, 1b00100, 2, (RNDQMQ, RNDQMQ), neon_rev), | |
5150f0d8 AV |
25605 | mnUF(vshl, _vshl, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_I63b_RR), neon_shl), |
25606 | mnUF(vqshl, _vqshl, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_I63b_RR), neon_qshl), | |
25607 | MNUF(vqshlu, 1800610, 3, (RNDQMQ, oRNDQMQ, I63), neon_qshlu_imm), | |
5d281bf0 AV |
25608 | |
25609 | #undef ARM_VARIANT | |
25610 | #define ARM_VARIANT & arm_ext_v8_3 | |
25611 | #undef THUMB_VARIANT | |
25612 | #define THUMB_VARIANT & arm_ext_v6t2_v8m | |
25613 | MNUF (vcadd, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ, EXPi), vcadd), | |
25614 | MNUF (vcmla, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ_RNSC, EXPi), vcmla), | |
c19d1205 ZW |
25615 | }; |
25616 | #undef ARM_VARIANT | |
25617 | #undef THUMB_VARIANT | |
25618 | #undef TCE | |
c19d1205 ZW |
25619 | #undef TUE |
25620 | #undef TUF | |
25621 | #undef TCC | |
8f06b2d8 | 25622 | #undef cCE |
e3cb604e PB |
25623 | #undef cCL |
25624 | #undef C3E | |
4389b29a | 25625 | #undef C3 |
c19d1205 ZW |
25626 | #undef CE |
25627 | #undef CM | |
4389b29a | 25628 | #undef CL |
c19d1205 ZW |
25629 | #undef UE |
25630 | #undef UF | |
25631 | #undef UT | |
5287ad62 JB |
25632 | #undef NUF |
25633 | #undef nUF | |
25634 | #undef NCE | |
25635 | #undef nCE | |
c19d1205 ZW |
25636 | #undef OPS0 |
25637 | #undef OPS1 | |
25638 | #undef OPS2 | |
25639 | #undef OPS3 | |
25640 | #undef OPS4 | |
25641 | #undef OPS5 | |
25642 | #undef OPS6 | |
25643 | #undef do_0 | |
4389b29a AV |
25644 | #undef ToC |
25645 | #undef toC | |
25646 | #undef ToU | |
f6b2b12d | 25647 | #undef toU |
c19d1205 ZW |
25648 | \f |
25649 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 25650 | |
c19d1205 ZW |
25651 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
25652 | for use in the a.out file, and stores them in the array pointed to by buf. | |
25653 | This knows about the endian-ness of the target machine and does | |
25654 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
25655 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
25656 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 25657 | |
c19d1205 ZW |
25658 | void |
25659 | md_number_to_chars (char * buf, valueT val, int n) | |
25660 | { | |
25661 | if (target_big_endian) | |
25662 | number_to_chars_bigendian (buf, val, n); | |
25663 | else | |
25664 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
25665 | } |
25666 | ||
c19d1205 ZW |
25667 | static valueT |
25668 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 25669 | { |
c19d1205 ZW |
25670 | valueT result = 0; |
25671 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 25672 | |
c19d1205 | 25673 | if (target_big_endian) |
b99bd4ef | 25674 | { |
c19d1205 ZW |
25675 | while (n--) |
25676 | { | |
25677 | result <<= 8; | |
25678 | result |= (*where++ & 255); | |
25679 | } | |
b99bd4ef | 25680 | } |
c19d1205 | 25681 | else |
b99bd4ef | 25682 | { |
c19d1205 ZW |
25683 | while (n--) |
25684 | { | |
25685 | result <<= 8; | |
25686 | result |= (where[n] & 255); | |
25687 | } | |
bfae80f2 | 25688 | } |
b99bd4ef | 25689 | |
c19d1205 | 25690 | return result; |
bfae80f2 | 25691 | } |
b99bd4ef | 25692 | |
c19d1205 | 25693 | /* MD interface: Sections. */ |
b99bd4ef | 25694 | |
fa94de6b RM |
25695 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
25696 | that an rs_machine_dependent frag may reach. */ | |
25697 | ||
25698 | unsigned int | |
25699 | arm_frag_max_var (fragS *fragp) | |
25700 | { | |
25701 | /* We only use rs_machine_dependent for variable-size Thumb instructions, | |
25702 | which are either THUMB_SIZE (2) or INSN_SIZE (4). | |
25703 | ||
25704 | Note that we generate relaxable instructions even for cases that don't | |
25705 | really need it, like an immediate that's a trivial constant. So we're | |
25706 | overestimating the instruction size for some of those cases. Rather | |
25707 | than putting more intelligence here, it would probably be better to | |
25708 | avoid generating a relaxation frag in the first place when it can be | |
25709 | determined up front that a short instruction will suffice. */ | |
25710 | ||
25711 | gas_assert (fragp->fr_type == rs_machine_dependent); | |
25712 | return INSN_SIZE; | |
25713 | } | |
25714 | ||
0110f2b8 PB |
25715 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
25716 | 2 bytes. */ | |
25717 | ||
c19d1205 | 25718 | int |
0110f2b8 | 25719 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
25720 | segT segtype ATTRIBUTE_UNUSED) |
25721 | { | |
0110f2b8 PB |
25722 | fragp->fr_var = 2; |
25723 | return 2; | |
25724 | } | |
25725 | ||
25726 | /* Convert a machine dependent frag. */ | |
25727 | ||
25728 | void | |
25729 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
25730 | { | |
25731 | unsigned long insn; | |
25732 | unsigned long old_op; | |
25733 | char *buf; | |
25734 | expressionS exp; | |
25735 | fixS *fixp; | |
25736 | int reloc_type; | |
25737 | int pc_rel; | |
25738 | int opcode; | |
25739 | ||
25740 | buf = fragp->fr_literal + fragp->fr_fix; | |
25741 | ||
25742 | old_op = bfd_get_16(abfd, buf); | |
5f4273c7 NC |
25743 | if (fragp->fr_symbol) |
25744 | { | |
0110f2b8 PB |
25745 | exp.X_op = O_symbol; |
25746 | exp.X_add_symbol = fragp->fr_symbol; | |
5f4273c7 NC |
25747 | } |
25748 | else | |
25749 | { | |
0110f2b8 | 25750 | exp.X_op = O_constant; |
5f4273c7 | 25751 | } |
0110f2b8 PB |
25752 | exp.X_add_number = fragp->fr_offset; |
25753 | opcode = fragp->fr_subtype; | |
25754 | switch (opcode) | |
25755 | { | |
25756 | case T_MNEM_ldr_pc: | |
25757 | case T_MNEM_ldr_pc2: | |
25758 | case T_MNEM_ldr_sp: | |
25759 | case T_MNEM_str_sp: | |
25760 | case T_MNEM_ldr: | |
25761 | case T_MNEM_ldrb: | |
25762 | case T_MNEM_ldrh: | |
25763 | case T_MNEM_str: | |
25764 | case T_MNEM_strb: | |
25765 | case T_MNEM_strh: | |
25766 | if (fragp->fr_var == 4) | |
25767 | { | |
5f4273c7 | 25768 | insn = THUMB_OP32 (opcode); |
0110f2b8 PB |
25769 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) |
25770 | { | |
25771 | insn |= (old_op & 0x700) << 4; | |
25772 | } | |
25773 | else | |
25774 | { | |
25775 | insn |= (old_op & 7) << 12; | |
25776 | insn |= (old_op & 0x38) << 13; | |
25777 | } | |
25778 | insn |= 0x00000c00; | |
25779 | put_thumb32_insn (buf, insn); | |
25780 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
25781 | } | |
25782 | else | |
25783 | { | |
25784 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
25785 | } | |
25786 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
25787 | break; | |
25788 | case T_MNEM_adr: | |
25789 | if (fragp->fr_var == 4) | |
25790 | { | |
25791 | insn = THUMB_OP32 (opcode); | |
25792 | insn |= (old_op & 0xf0) << 4; | |
25793 | put_thumb32_insn (buf, insn); | |
25794 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
25795 | } | |
25796 | else | |
25797 | { | |
25798 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
25799 | exp.X_add_number -= 4; | |
25800 | } | |
25801 | pc_rel = 1; | |
25802 | break; | |
25803 | case T_MNEM_mov: | |
25804 | case T_MNEM_movs: | |
25805 | case T_MNEM_cmp: | |
25806 | case T_MNEM_cmn: | |
25807 | if (fragp->fr_var == 4) | |
25808 | { | |
25809 | int r0off = (opcode == T_MNEM_mov | |
25810 | || opcode == T_MNEM_movs) ? 0 : 8; | |
25811 | insn = THUMB_OP32 (opcode); | |
25812 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
25813 | insn |= (old_op & 0x700) << r0off; | |
25814 | put_thumb32_insn (buf, insn); | |
25815 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
25816 | } | |
25817 | else | |
25818 | { | |
25819 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
25820 | } | |
25821 | pc_rel = 0; | |
25822 | break; | |
25823 | case T_MNEM_b: | |
25824 | if (fragp->fr_var == 4) | |
25825 | { | |
25826 | insn = THUMB_OP32(opcode); | |
25827 | put_thumb32_insn (buf, insn); | |
25828 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
25829 | } | |
25830 | else | |
25831 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
25832 | pc_rel = 1; | |
25833 | break; | |
25834 | case T_MNEM_bcond: | |
25835 | if (fragp->fr_var == 4) | |
25836 | { | |
25837 | insn = THUMB_OP32(opcode); | |
25838 | insn |= (old_op & 0xf00) << 14; | |
25839 | put_thumb32_insn (buf, insn); | |
25840 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
25841 | } | |
25842 | else | |
25843 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
25844 | pc_rel = 1; | |
25845 | break; | |
25846 | case T_MNEM_add_sp: | |
25847 | case T_MNEM_add_pc: | |
25848 | case T_MNEM_inc_sp: | |
25849 | case T_MNEM_dec_sp: | |
25850 | if (fragp->fr_var == 4) | |
25851 | { | |
25852 | /* ??? Choose between add and addw. */ | |
25853 | insn = THUMB_OP32 (opcode); | |
25854 | insn |= (old_op & 0xf0) << 4; | |
25855 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
25856 | if (opcode == T_MNEM_add_pc) |
25857 | reloc_type = BFD_RELOC_ARM_T32_IMM12; | |
25858 | else | |
25859 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
0110f2b8 PB |
25860 | } |
25861 | else | |
25862 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
25863 | pc_rel = 0; | |
25864 | break; | |
25865 | ||
25866 | case T_MNEM_addi: | |
25867 | case T_MNEM_addis: | |
25868 | case T_MNEM_subi: | |
25869 | case T_MNEM_subis: | |
25870 | if (fragp->fr_var == 4) | |
25871 | { | |
25872 | insn = THUMB_OP32 (opcode); | |
25873 | insn |= (old_op & 0xf0) << 4; | |
25874 | insn |= (old_op & 0xf) << 16; | |
25875 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
25876 | if (insn & (1 << 20)) |
25877 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
25878 | else | |
25879 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
0110f2b8 PB |
25880 | } |
25881 | else | |
25882 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
25883 | pc_rel = 0; | |
25884 | break; | |
25885 | default: | |
5f4273c7 | 25886 | abort (); |
0110f2b8 PB |
25887 | } |
25888 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
21d799b5 | 25889 | (enum bfd_reloc_code_real) reloc_type); |
0110f2b8 PB |
25890 | fixp->fx_file = fragp->fr_file; |
25891 | fixp->fx_line = fragp->fr_line; | |
25892 | fragp->fr_fix += fragp->fr_var; | |
3cfdb781 TG |
25893 | |
25894 | /* Set whether we use thumb-2 ISA based on final relaxation results. */ | |
25895 | if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected () | |
25896 | && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2)) | |
25897 | ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2); | |
0110f2b8 PB |
25898 | } |
25899 | ||
25900 | /* Return the size of a relaxable immediate operand instruction. | |
25901 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
25902 | static int | |
25903 | relax_immediate (fragS *fragp, int size, int shift) | |
25904 | { | |
25905 | offsetT offset; | |
25906 | offsetT mask; | |
25907 | offsetT low; | |
25908 | ||
25909 | /* ??? Should be able to do better than this. */ | |
25910 | if (fragp->fr_symbol) | |
25911 | return 4; | |
25912 | ||
25913 | low = (1 << shift) - 1; | |
25914 | mask = (1 << (shift + size)) - (1 << shift); | |
25915 | offset = fragp->fr_offset; | |
25916 | /* Force misaligned offsets to 32-bit variant. */ | |
25917 | if (offset & low) | |
5e77afaa | 25918 | return 4; |
0110f2b8 PB |
25919 | if (offset & ~mask) |
25920 | return 4; | |
25921 | return 2; | |
25922 | } | |
25923 | ||
5e77afaa PB |
25924 | /* Get the address of a symbol during relaxation. */ |
25925 | static addressT | |
5f4273c7 | 25926 | relaxed_symbol_addr (fragS *fragp, long stretch) |
5e77afaa PB |
25927 | { |
25928 | fragS *sym_frag; | |
25929 | addressT addr; | |
25930 | symbolS *sym; | |
25931 | ||
25932 | sym = fragp->fr_symbol; | |
25933 | sym_frag = symbol_get_frag (sym); | |
25934 | know (S_GET_SEGMENT (sym) != absolute_section | |
25935 | || sym_frag == &zero_address_frag); | |
25936 | addr = S_GET_VALUE (sym) + fragp->fr_offset; | |
25937 | ||
25938 | /* If frag has yet to be reached on this pass, assume it will | |
25939 | move by STRETCH just as we did. If this is not so, it will | |
25940 | be because some frag between grows, and that will force | |
25941 | another pass. */ | |
25942 | ||
25943 | if (stretch != 0 | |
25944 | && sym_frag->relax_marker != fragp->relax_marker) | |
4396b686 PB |
25945 | { |
25946 | fragS *f; | |
25947 | ||
25948 | /* Adjust stretch for any alignment frag. Note that if have | |
25949 | been expanding the earlier code, the symbol may be | |
25950 | defined in what appears to be an earlier frag. FIXME: | |
25951 | This doesn't handle the fr_subtype field, which specifies | |
25952 | a maximum number of bytes to skip when doing an | |
25953 | alignment. */ | |
25954 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
25955 | { | |
25956 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
25957 | { | |
25958 | if (stretch < 0) | |
25959 | stretch = - ((- stretch) | |
25960 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
25961 | else | |
25962 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
25963 | if (stretch == 0) | |
25964 | break; | |
25965 | } | |
25966 | } | |
25967 | if (f != NULL) | |
25968 | addr += stretch; | |
25969 | } | |
5e77afaa PB |
25970 | |
25971 | return addr; | |
25972 | } | |
25973 | ||
0110f2b8 PB |
25974 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative |
25975 | load. */ | |
25976 | static int | |
5e77afaa | 25977 | relax_adr (fragS *fragp, asection *sec, long stretch) |
0110f2b8 PB |
25978 | { |
25979 | addressT addr; | |
25980 | offsetT val; | |
25981 | ||
25982 | /* Assume worst case for symbols not known to be in the same section. */ | |
974da60d NC |
25983 | if (fragp->fr_symbol == NULL |
25984 | || !S_IS_DEFINED (fragp->fr_symbol) | |
77db8e2e NC |
25985 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
25986 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
25987 | return 4; |
25988 | ||
5f4273c7 | 25989 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
25990 | addr = fragp->fr_address + fragp->fr_fix; |
25991 | addr = (addr + 4) & ~3; | |
5e77afaa | 25992 | /* Force misaligned targets to 32-bit variant. */ |
0110f2b8 | 25993 | if (val & 3) |
5e77afaa | 25994 | return 4; |
0110f2b8 PB |
25995 | val -= addr; |
25996 | if (val < 0 || val > 1020) | |
25997 | return 4; | |
25998 | return 2; | |
25999 | } | |
26000 | ||
26001 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
26002 | static int | |
26003 | relax_addsub (fragS *fragp, asection *sec) | |
26004 | { | |
26005 | char *buf; | |
26006 | int op; | |
26007 | ||
26008 | buf = fragp->fr_literal + fragp->fr_fix; | |
26009 | op = bfd_get_16(sec->owner, buf); | |
26010 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
26011 | return relax_immediate (fragp, 8, 0); | |
26012 | else | |
26013 | return relax_immediate (fragp, 3, 0); | |
26014 | } | |
26015 | ||
e83a675f RE |
26016 | /* Return TRUE iff the definition of symbol S could be pre-empted |
26017 | (overridden) at link or load time. */ | |
26018 | static bfd_boolean | |
26019 | symbol_preemptible (symbolS *s) | |
26020 | { | |
26021 | /* Weak symbols can always be pre-empted. */ | |
26022 | if (S_IS_WEAK (s)) | |
26023 | return TRUE; | |
26024 | ||
26025 | /* Non-global symbols cannot be pre-empted. */ | |
26026 | if (! S_IS_EXTERNAL (s)) | |
26027 | return FALSE; | |
26028 | ||
26029 | #ifdef OBJ_ELF | |
26030 | /* In ELF, a global symbol can be marked protected, or private. In that | |
26031 | case it can't be pre-empted (other definitions in the same link unit | |
26032 | would violate the ODR). */ | |
26033 | if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT) | |
26034 | return FALSE; | |
26035 | #endif | |
26036 | ||
26037 | /* Other global symbols might be pre-empted. */ | |
26038 | return TRUE; | |
26039 | } | |
0110f2b8 PB |
26040 | |
26041 | /* Return the size of a relaxable branch instruction. BITS is the | |
26042 | size of the offset field in the narrow instruction. */ | |
26043 | ||
26044 | static int | |
5e77afaa | 26045 | relax_branch (fragS *fragp, asection *sec, int bits, long stretch) |
0110f2b8 PB |
26046 | { |
26047 | addressT addr; | |
26048 | offsetT val; | |
26049 | offsetT limit; | |
26050 | ||
26051 | /* Assume worst case for symbols not known to be in the same section. */ | |
5f4273c7 | 26052 | if (!S_IS_DEFINED (fragp->fr_symbol) |
77db8e2e NC |
26053 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
26054 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
26055 | return 4; |
26056 | ||
267bf995 | 26057 | #ifdef OBJ_ELF |
e83a675f | 26058 | /* A branch to a function in ARM state will require interworking. */ |
267bf995 RR |
26059 | if (S_IS_DEFINED (fragp->fr_symbol) |
26060 | && ARM_IS_FUNC (fragp->fr_symbol)) | |
26061 | return 4; | |
e83a675f | 26062 | #endif |
0d9b4b55 | 26063 | |
e83a675f | 26064 | if (symbol_preemptible (fragp->fr_symbol)) |
0d9b4b55 | 26065 | return 4; |
267bf995 | 26066 | |
5f4273c7 | 26067 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
26068 | addr = fragp->fr_address + fragp->fr_fix + 4; |
26069 | val -= addr; | |
26070 | ||
26071 | /* Offset is a signed value *2 */ | |
26072 | limit = 1 << bits; | |
26073 | if (val >= limit || val < -limit) | |
26074 | return 4; | |
26075 | return 2; | |
26076 | } | |
26077 | ||
26078 | ||
26079 | /* Relax a machine dependent frag. This returns the amount by which | |
26080 | the current size of the frag should change. */ | |
26081 | ||
26082 | int | |
5e77afaa | 26083 | arm_relax_frag (asection *sec, fragS *fragp, long stretch) |
0110f2b8 PB |
26084 | { |
26085 | int oldsize; | |
26086 | int newsize; | |
26087 | ||
26088 | oldsize = fragp->fr_var; | |
26089 | switch (fragp->fr_subtype) | |
26090 | { | |
26091 | case T_MNEM_ldr_pc2: | |
5f4273c7 | 26092 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
26093 | break; |
26094 | case T_MNEM_ldr_pc: | |
26095 | case T_MNEM_ldr_sp: | |
26096 | case T_MNEM_str_sp: | |
5f4273c7 | 26097 | newsize = relax_immediate (fragp, 8, 2); |
0110f2b8 PB |
26098 | break; |
26099 | case T_MNEM_ldr: | |
26100 | case T_MNEM_str: | |
5f4273c7 | 26101 | newsize = relax_immediate (fragp, 5, 2); |
0110f2b8 PB |
26102 | break; |
26103 | case T_MNEM_ldrh: | |
26104 | case T_MNEM_strh: | |
5f4273c7 | 26105 | newsize = relax_immediate (fragp, 5, 1); |
0110f2b8 PB |
26106 | break; |
26107 | case T_MNEM_ldrb: | |
26108 | case T_MNEM_strb: | |
5f4273c7 | 26109 | newsize = relax_immediate (fragp, 5, 0); |
0110f2b8 PB |
26110 | break; |
26111 | case T_MNEM_adr: | |
5f4273c7 | 26112 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
26113 | break; |
26114 | case T_MNEM_mov: | |
26115 | case T_MNEM_movs: | |
26116 | case T_MNEM_cmp: | |
26117 | case T_MNEM_cmn: | |
5f4273c7 | 26118 | newsize = relax_immediate (fragp, 8, 0); |
0110f2b8 PB |
26119 | break; |
26120 | case T_MNEM_b: | |
5f4273c7 | 26121 | newsize = relax_branch (fragp, sec, 11, stretch); |
0110f2b8 PB |
26122 | break; |
26123 | case T_MNEM_bcond: | |
5f4273c7 | 26124 | newsize = relax_branch (fragp, sec, 8, stretch); |
0110f2b8 PB |
26125 | break; |
26126 | case T_MNEM_add_sp: | |
26127 | case T_MNEM_add_pc: | |
26128 | newsize = relax_immediate (fragp, 8, 2); | |
26129 | break; | |
26130 | case T_MNEM_inc_sp: | |
26131 | case T_MNEM_dec_sp: | |
26132 | newsize = relax_immediate (fragp, 7, 2); | |
26133 | break; | |
26134 | case T_MNEM_addi: | |
26135 | case T_MNEM_addis: | |
26136 | case T_MNEM_subi: | |
26137 | case T_MNEM_subis: | |
26138 | newsize = relax_addsub (fragp, sec); | |
26139 | break; | |
26140 | default: | |
5f4273c7 | 26141 | abort (); |
0110f2b8 | 26142 | } |
5e77afaa PB |
26143 | |
26144 | fragp->fr_var = newsize; | |
26145 | /* Freeze wide instructions that are at or before the same location as | |
26146 | in the previous pass. This avoids infinite loops. | |
5f4273c7 NC |
26147 | Don't freeze them unconditionally because targets may be artificially |
26148 | misaligned by the expansion of preceding frags. */ | |
5e77afaa | 26149 | if (stretch <= 0 && newsize > 2) |
0110f2b8 | 26150 | { |
0110f2b8 | 26151 | md_convert_frag (sec->owner, sec, fragp); |
5f4273c7 | 26152 | frag_wane (fragp); |
0110f2b8 | 26153 | } |
5e77afaa | 26154 | |
0110f2b8 | 26155 | return newsize - oldsize; |
c19d1205 | 26156 | } |
b99bd4ef | 26157 | |
c19d1205 | 26158 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 26159 | |
c19d1205 ZW |
26160 | valueT |
26161 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
26162 | valueT size) | |
26163 | { | |
6844c0cc | 26164 | return size; |
bfae80f2 | 26165 | } |
b99bd4ef | 26166 | |
c19d1205 ZW |
26167 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
26168 | of an rs_align_code fragment. */ | |
26169 | ||
26170 | void | |
26171 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 26172 | { |
d9235011 | 26173 | static unsigned char const arm_noop[2][2][4] = |
e7495e45 NS |
26174 | { |
26175 | { /* ARMv1 */ | |
26176 | {0x00, 0x00, 0xa0, 0xe1}, /* LE */ | |
26177 | {0xe1, 0xa0, 0x00, 0x00}, /* BE */ | |
26178 | }, | |
26179 | { /* ARMv6k */ | |
26180 | {0x00, 0xf0, 0x20, 0xe3}, /* LE */ | |
26181 | {0xe3, 0x20, 0xf0, 0x00}, /* BE */ | |
26182 | }, | |
26183 | }; | |
d9235011 | 26184 | static unsigned char const thumb_noop[2][2][2] = |
e7495e45 NS |
26185 | { |
26186 | { /* Thumb-1 */ | |
26187 | {0xc0, 0x46}, /* LE */ | |
26188 | {0x46, 0xc0}, /* BE */ | |
26189 | }, | |
26190 | { /* Thumb-2 */ | |
26191 | {0x00, 0xbf}, /* LE */ | |
26192 | {0xbf, 0x00} /* BE */ | |
26193 | } | |
26194 | }; | |
d9235011 | 26195 | static unsigned char const wide_thumb_noop[2][4] = |
e7495e45 NS |
26196 | { /* Wide Thumb-2 */ |
26197 | {0xaf, 0xf3, 0x00, 0x80}, /* LE */ | |
26198 | {0xf3, 0xaf, 0x80, 0x00}, /* BE */ | |
26199 | }; | |
c921be7d | 26200 | |
e7495e45 | 26201 | unsigned bytes, fix, noop_size; |
c19d1205 | 26202 | char * p; |
d9235011 TS |
26203 | const unsigned char * noop; |
26204 | const unsigned char *narrow_noop = NULL; | |
cd000bff DJ |
26205 | #ifdef OBJ_ELF |
26206 | enum mstate state; | |
26207 | #endif | |
bfae80f2 | 26208 | |
c19d1205 | 26209 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
26210 | return; |
26211 | ||
c19d1205 ZW |
26212 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
26213 | p = fragP->fr_literal + fragP->fr_fix; | |
26214 | fix = 0; | |
bfae80f2 | 26215 | |
c19d1205 ZW |
26216 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
26217 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 26218 | |
cd000bff | 26219 | gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0); |
8dc2430f | 26220 | |
cd000bff | 26221 | if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED)) |
a737bd4d | 26222 | { |
7f78eb34 JW |
26223 | if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0] |
26224 | ? selected_cpu : arm_arch_none, arm_ext_v6t2)) | |
e7495e45 NS |
26225 | { |
26226 | narrow_noop = thumb_noop[1][target_big_endian]; | |
26227 | noop = wide_thumb_noop[target_big_endian]; | |
26228 | } | |
c19d1205 | 26229 | else |
e7495e45 NS |
26230 | noop = thumb_noop[0][target_big_endian]; |
26231 | noop_size = 2; | |
cd000bff DJ |
26232 | #ifdef OBJ_ELF |
26233 | state = MAP_THUMB; | |
26234 | #endif | |
7ed4c4c5 NC |
26235 | } |
26236 | else | |
26237 | { | |
7f78eb34 JW |
26238 | noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0] |
26239 | ? selected_cpu : arm_arch_none, | |
26240 | arm_ext_v6k) != 0] | |
e7495e45 NS |
26241 | [target_big_endian]; |
26242 | noop_size = 4; | |
cd000bff DJ |
26243 | #ifdef OBJ_ELF |
26244 | state = MAP_ARM; | |
26245 | #endif | |
7ed4c4c5 | 26246 | } |
c921be7d | 26247 | |
e7495e45 | 26248 | fragP->fr_var = noop_size; |
c921be7d | 26249 | |
c19d1205 | 26250 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 26251 | { |
c19d1205 | 26252 | fix = bytes & (noop_size - 1); |
cd000bff DJ |
26253 | #ifdef OBJ_ELF |
26254 | insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix); | |
26255 | #endif | |
c19d1205 ZW |
26256 | memset (p, 0, fix); |
26257 | p += fix; | |
26258 | bytes -= fix; | |
a737bd4d | 26259 | } |
a737bd4d | 26260 | |
e7495e45 NS |
26261 | if (narrow_noop) |
26262 | { | |
26263 | if (bytes & noop_size) | |
26264 | { | |
26265 | /* Insert a narrow noop. */ | |
26266 | memcpy (p, narrow_noop, noop_size); | |
26267 | p += noop_size; | |
26268 | bytes -= noop_size; | |
26269 | fix += noop_size; | |
26270 | } | |
26271 | ||
26272 | /* Use wide noops for the remainder */ | |
26273 | noop_size = 4; | |
26274 | } | |
26275 | ||
c19d1205 | 26276 | while (bytes >= noop_size) |
a737bd4d | 26277 | { |
c19d1205 ZW |
26278 | memcpy (p, noop, noop_size); |
26279 | p += noop_size; | |
26280 | bytes -= noop_size; | |
26281 | fix += noop_size; | |
a737bd4d NC |
26282 | } |
26283 | ||
c19d1205 | 26284 | fragP->fr_fix += fix; |
a737bd4d NC |
26285 | } |
26286 | ||
c19d1205 ZW |
26287 | /* Called from md_do_align. Used to create an alignment |
26288 | frag in a code section. */ | |
26289 | ||
26290 | void | |
26291 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 26292 | { |
c19d1205 | 26293 | char * p; |
7ed4c4c5 | 26294 | |
c19d1205 | 26295 | /* We assume that there will never be a requirement |
6ec8e702 | 26296 | to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */ |
c19d1205 | 26297 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) |
6ec8e702 NC |
26298 | { |
26299 | char err_msg[128]; | |
26300 | ||
fa94de6b | 26301 | sprintf (err_msg, |
477330fc RM |
26302 | _("alignments greater than %d bytes not supported in .text sections."), |
26303 | MAX_MEM_FOR_RS_ALIGN_CODE + 1); | |
20203fb9 | 26304 | as_fatal ("%s", err_msg); |
6ec8e702 | 26305 | } |
bfae80f2 | 26306 | |
c19d1205 ZW |
26307 | p = frag_var (rs_align_code, |
26308 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
26309 | 1, | |
26310 | (relax_substateT) max, | |
26311 | (symbolS *) NULL, | |
26312 | (offsetT) n, | |
26313 | (char *) NULL); | |
26314 | *p = 0; | |
26315 | } | |
bfae80f2 | 26316 | |
8dc2430f NC |
26317 | /* Perform target specific initialisation of a frag. |
26318 | Note - despite the name this initialisation is not done when the frag | |
26319 | is created, but only when its type is assigned. A frag can be created | |
26320 | and used a long time before its type is set, so beware of assuming that | |
33eaf5de | 26321 | this initialisation is performed first. */ |
bfae80f2 | 26322 | |
cd000bff DJ |
26323 | #ifndef OBJ_ELF |
26324 | void | |
26325 | arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED) | |
26326 | { | |
26327 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
2e98972e | 26328 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
cd000bff DJ |
26329 | } |
26330 | ||
26331 | #else /* OBJ_ELF is defined. */ | |
c19d1205 | 26332 | void |
cd000bff | 26333 | arm_init_frag (fragS * fragP, int max_chars) |
c19d1205 | 26334 | { |
e8d84ca1 | 26335 | bfd_boolean frag_thumb_mode; |
b968d18a | 26336 | |
8dc2430f NC |
26337 | /* If the current ARM vs THUMB mode has not already |
26338 | been recorded into this frag then do so now. */ | |
cd000bff | 26339 | if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0) |
b968d18a JW |
26340 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
26341 | ||
e8d84ca1 NC |
26342 | /* PR 21809: Do not set a mapping state for debug sections |
26343 | - it just confuses other tools. */ | |
26344 | if (bfd_get_section_flags (NULL, now_seg) & SEC_DEBUGGING) | |
26345 | return; | |
26346 | ||
b968d18a | 26347 | frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED; |
cd000bff | 26348 | |
f9c1b181 RL |
26349 | /* Record a mapping symbol for alignment frags. We will delete this |
26350 | later if the alignment ends up empty. */ | |
26351 | switch (fragP->fr_type) | |
26352 | { | |
26353 | case rs_align: | |
26354 | case rs_align_test: | |
26355 | case rs_fill: | |
26356 | mapping_state_2 (MAP_DATA, max_chars); | |
26357 | break; | |
26358 | case rs_align_code: | |
b968d18a | 26359 | mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars); |
f9c1b181 RL |
26360 | break; |
26361 | default: | |
26362 | break; | |
cd000bff | 26363 | } |
bfae80f2 RE |
26364 | } |
26365 | ||
c19d1205 ZW |
26366 | /* When we change sections we need to issue a new mapping symbol. */ |
26367 | ||
26368 | void | |
26369 | arm_elf_change_section (void) | |
bfae80f2 | 26370 | { |
c19d1205 ZW |
26371 | /* Link an unlinked unwind index table section to the .text section. */ |
26372 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
26373 | && elf_linked_to_section (now_seg) == NULL) | |
26374 | elf_linked_to_section (now_seg) = text_section; | |
bfae80f2 RE |
26375 | } |
26376 | ||
c19d1205 ZW |
26377 | int |
26378 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 26379 | { |
c19d1205 ZW |
26380 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
26381 | return SHT_ARM_EXIDX; | |
e45d0630 | 26382 | |
c19d1205 ZW |
26383 | return -1; |
26384 | } | |
26385 | \f | |
26386 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 26387 | |
c19d1205 | 26388 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 26389 | |
5f4273c7 | 26390 | /* Generate any deferred unwind frame offset. */ |
e45d0630 | 26391 | |
bfae80f2 | 26392 | static void |
c19d1205 | 26393 | flush_pending_unwind (void) |
bfae80f2 | 26394 | { |
c19d1205 | 26395 | offsetT offset; |
bfae80f2 | 26396 | |
c19d1205 ZW |
26397 | offset = unwind.pending_offset; |
26398 | unwind.pending_offset = 0; | |
26399 | if (offset != 0) | |
26400 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
26401 | } |
26402 | ||
c19d1205 ZW |
26403 | /* Add an opcode to this list for this function. Two-byte opcodes should |
26404 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
26405 | order. */ | |
26406 | ||
bfae80f2 | 26407 | static void |
c19d1205 | 26408 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 26409 | { |
c19d1205 ZW |
26410 | /* Add any deferred stack adjustment. */ |
26411 | if (unwind.pending_offset) | |
26412 | flush_pending_unwind (); | |
bfae80f2 | 26413 | |
c19d1205 | 26414 | unwind.sp_restored = 0; |
bfae80f2 | 26415 | |
c19d1205 | 26416 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 26417 | { |
c19d1205 ZW |
26418 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
26419 | if (unwind.opcodes) | |
325801bd TS |
26420 | unwind.opcodes = XRESIZEVEC (unsigned char, unwind.opcodes, |
26421 | unwind.opcode_alloc); | |
c19d1205 | 26422 | else |
325801bd | 26423 | unwind.opcodes = XNEWVEC (unsigned char, unwind.opcode_alloc); |
bfae80f2 | 26424 | } |
c19d1205 | 26425 | while (length > 0) |
bfae80f2 | 26426 | { |
c19d1205 ZW |
26427 | length--; |
26428 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
26429 | op >>= 8; | |
26430 | unwind.opcode_count++; | |
bfae80f2 | 26431 | } |
bfae80f2 RE |
26432 | } |
26433 | ||
c19d1205 ZW |
26434 | /* Add unwind opcodes to adjust the stack pointer. */ |
26435 | ||
bfae80f2 | 26436 | static void |
c19d1205 | 26437 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 26438 | { |
c19d1205 | 26439 | valueT op; |
bfae80f2 | 26440 | |
c19d1205 | 26441 | if (offset > 0x200) |
bfae80f2 | 26442 | { |
c19d1205 ZW |
26443 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
26444 | char bytes[5]; | |
26445 | int n; | |
26446 | valueT o; | |
bfae80f2 | 26447 | |
c19d1205 ZW |
26448 | /* Long form: 0xb2, uleb128. */ |
26449 | /* This might not fit in a word so add the individual bytes, | |
26450 | remembering the list is built in reverse order. */ | |
26451 | o = (valueT) ((offset - 0x204) >> 2); | |
26452 | if (o == 0) | |
26453 | add_unwind_opcode (0, 1); | |
bfae80f2 | 26454 | |
c19d1205 ZW |
26455 | /* Calculate the uleb128 encoding of the offset. */ |
26456 | n = 0; | |
26457 | while (o) | |
26458 | { | |
26459 | bytes[n] = o & 0x7f; | |
26460 | o >>= 7; | |
26461 | if (o) | |
26462 | bytes[n] |= 0x80; | |
26463 | n++; | |
26464 | } | |
26465 | /* Add the insn. */ | |
26466 | for (; n; n--) | |
26467 | add_unwind_opcode (bytes[n - 1], 1); | |
26468 | add_unwind_opcode (0xb2, 1); | |
26469 | } | |
26470 | else if (offset > 0x100) | |
bfae80f2 | 26471 | { |
c19d1205 ZW |
26472 | /* Two short opcodes. */ |
26473 | add_unwind_opcode (0x3f, 1); | |
26474 | op = (offset - 0x104) >> 2; | |
26475 | add_unwind_opcode (op, 1); | |
bfae80f2 | 26476 | } |
c19d1205 ZW |
26477 | else if (offset > 0) |
26478 | { | |
26479 | /* Short opcode. */ | |
26480 | op = (offset - 4) >> 2; | |
26481 | add_unwind_opcode (op, 1); | |
26482 | } | |
26483 | else if (offset < 0) | |
bfae80f2 | 26484 | { |
c19d1205 ZW |
26485 | offset = -offset; |
26486 | while (offset > 0x100) | |
bfae80f2 | 26487 | { |
c19d1205 ZW |
26488 | add_unwind_opcode (0x7f, 1); |
26489 | offset -= 0x100; | |
bfae80f2 | 26490 | } |
c19d1205 ZW |
26491 | op = ((offset - 4) >> 2) | 0x40; |
26492 | add_unwind_opcode (op, 1); | |
bfae80f2 | 26493 | } |
bfae80f2 RE |
26494 | } |
26495 | ||
c19d1205 | 26496 | /* Finish the list of unwind opcodes for this function. */ |
0198d5e6 | 26497 | |
c19d1205 ZW |
26498 | static void |
26499 | finish_unwind_opcodes (void) | |
bfae80f2 | 26500 | { |
c19d1205 | 26501 | valueT op; |
bfae80f2 | 26502 | |
c19d1205 | 26503 | if (unwind.fp_used) |
bfae80f2 | 26504 | { |
708587a4 | 26505 | /* Adjust sp as necessary. */ |
c19d1205 ZW |
26506 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; |
26507 | flush_pending_unwind (); | |
bfae80f2 | 26508 | |
c19d1205 ZW |
26509 | /* After restoring sp from the frame pointer. */ |
26510 | op = 0x90 | unwind.fp_reg; | |
26511 | add_unwind_opcode (op, 1); | |
26512 | } | |
26513 | else | |
26514 | flush_pending_unwind (); | |
bfae80f2 RE |
26515 | } |
26516 | ||
bfae80f2 | 26517 | |
c19d1205 ZW |
26518 | /* Start an exception table entry. If idx is nonzero this is an index table |
26519 | entry. */ | |
bfae80f2 RE |
26520 | |
26521 | static void | |
c19d1205 | 26522 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 26523 | { |
c19d1205 ZW |
26524 | const char * text_name; |
26525 | const char * prefix; | |
26526 | const char * prefix_once; | |
26527 | const char * group_name; | |
c19d1205 | 26528 | char * sec_name; |
c19d1205 ZW |
26529 | int type; |
26530 | int flags; | |
26531 | int linkonce; | |
bfae80f2 | 26532 | |
c19d1205 | 26533 | if (idx) |
bfae80f2 | 26534 | { |
c19d1205 ZW |
26535 | prefix = ELF_STRING_ARM_unwind; |
26536 | prefix_once = ELF_STRING_ARM_unwind_once; | |
26537 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 26538 | } |
c19d1205 | 26539 | else |
bfae80f2 | 26540 | { |
c19d1205 ZW |
26541 | prefix = ELF_STRING_ARM_unwind_info; |
26542 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
26543 | type = SHT_PROGBITS; | |
bfae80f2 RE |
26544 | } |
26545 | ||
c19d1205 ZW |
26546 | text_name = segment_name (text_seg); |
26547 | if (streq (text_name, ".text")) | |
26548 | text_name = ""; | |
26549 | ||
26550 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
26551 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 26552 | { |
c19d1205 ZW |
26553 | prefix = prefix_once; |
26554 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
26555 | } |
26556 | ||
29a2809e | 26557 | sec_name = concat (prefix, text_name, (char *) NULL); |
bfae80f2 | 26558 | |
c19d1205 ZW |
26559 | flags = SHF_ALLOC; |
26560 | linkonce = 0; | |
26561 | group_name = 0; | |
bfae80f2 | 26562 | |
c19d1205 ZW |
26563 | /* Handle COMDAT group. */ |
26564 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 26565 | { |
c19d1205 ZW |
26566 | group_name = elf_group_name (text_seg); |
26567 | if (group_name == NULL) | |
26568 | { | |
bd3ba5d1 | 26569 | as_bad (_("Group section `%s' has no group signature"), |
c19d1205 ZW |
26570 | segment_name (text_seg)); |
26571 | ignore_rest_of_line (); | |
26572 | return; | |
26573 | } | |
26574 | flags |= SHF_GROUP; | |
26575 | linkonce = 1; | |
bfae80f2 RE |
26576 | } |
26577 | ||
a91e1603 L |
26578 | obj_elf_change_section (sec_name, type, 0, flags, 0, group_name, |
26579 | linkonce, 0); | |
bfae80f2 | 26580 | |
5f4273c7 | 26581 | /* Set the section link for index tables. */ |
c19d1205 ZW |
26582 | if (idx) |
26583 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
26584 | } |
26585 | ||
bfae80f2 | 26586 | |
c19d1205 ZW |
26587 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
26588 | personality routine data. Returns zero, or the index table value for | |
cad0da33 | 26589 | an inline entry. */ |
c19d1205 ZW |
26590 | |
26591 | static valueT | |
26592 | create_unwind_entry (int have_data) | |
bfae80f2 | 26593 | { |
c19d1205 ZW |
26594 | int size; |
26595 | addressT where; | |
26596 | char *ptr; | |
26597 | /* The current word of data. */ | |
26598 | valueT data; | |
26599 | /* The number of bytes left in this word. */ | |
26600 | int n; | |
bfae80f2 | 26601 | |
c19d1205 | 26602 | finish_unwind_opcodes (); |
bfae80f2 | 26603 | |
c19d1205 ZW |
26604 | /* Remember the current text section. */ |
26605 | unwind.saved_seg = now_seg; | |
26606 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 26607 | |
c19d1205 | 26608 | start_unwind_section (now_seg, 0); |
bfae80f2 | 26609 | |
c19d1205 | 26610 | if (unwind.personality_routine == NULL) |
bfae80f2 | 26611 | { |
c19d1205 ZW |
26612 | if (unwind.personality_index == -2) |
26613 | { | |
26614 | if (have_data) | |
5f4273c7 | 26615 | as_bad (_("handlerdata in cantunwind frame")); |
c19d1205 ZW |
26616 | return 1; /* EXIDX_CANTUNWIND. */ |
26617 | } | |
bfae80f2 | 26618 | |
c19d1205 ZW |
26619 | /* Use a default personality routine if none is specified. */ |
26620 | if (unwind.personality_index == -1) | |
26621 | { | |
26622 | if (unwind.opcode_count > 3) | |
26623 | unwind.personality_index = 1; | |
26624 | else | |
26625 | unwind.personality_index = 0; | |
26626 | } | |
bfae80f2 | 26627 | |
c19d1205 ZW |
26628 | /* Space for the personality routine entry. */ |
26629 | if (unwind.personality_index == 0) | |
26630 | { | |
26631 | if (unwind.opcode_count > 3) | |
26632 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 26633 | |
c19d1205 ZW |
26634 | if (!have_data) |
26635 | { | |
26636 | /* All the data is inline in the index table. */ | |
26637 | data = 0x80; | |
26638 | n = 3; | |
26639 | while (unwind.opcode_count > 0) | |
26640 | { | |
26641 | unwind.opcode_count--; | |
26642 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
26643 | n--; | |
26644 | } | |
bfae80f2 | 26645 | |
c19d1205 ZW |
26646 | /* Pad with "finish" opcodes. */ |
26647 | while (n--) | |
26648 | data = (data << 8) | 0xb0; | |
bfae80f2 | 26649 | |
c19d1205 ZW |
26650 | return data; |
26651 | } | |
26652 | size = 0; | |
26653 | } | |
26654 | else | |
26655 | /* We get two opcodes "free" in the first word. */ | |
26656 | size = unwind.opcode_count - 2; | |
26657 | } | |
26658 | else | |
5011093d | 26659 | { |
cad0da33 NC |
26660 | /* PR 16765: Missing or misplaced unwind directives can trigger this. */ |
26661 | if (unwind.personality_index != -1) | |
26662 | { | |
26663 | as_bad (_("attempt to recreate an unwind entry")); | |
26664 | return 1; | |
26665 | } | |
5011093d NC |
26666 | |
26667 | /* An extra byte is required for the opcode count. */ | |
26668 | size = unwind.opcode_count + 1; | |
26669 | } | |
bfae80f2 | 26670 | |
c19d1205 ZW |
26671 | size = (size + 3) >> 2; |
26672 | if (size > 0xff) | |
26673 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 26674 | |
c19d1205 ZW |
26675 | frag_align (2, 0, 0); |
26676 | record_alignment (now_seg, 2); | |
26677 | unwind.table_entry = expr_build_dot (); | |
26678 | ||
26679 | /* Allocate the table entry. */ | |
26680 | ptr = frag_more ((size << 2) + 4); | |
74929e7b NC |
26681 | /* PR 13449: Zero the table entries in case some of them are not used. */ |
26682 | memset (ptr, 0, (size << 2) + 4); | |
c19d1205 | 26683 | where = frag_now_fix () - ((size << 2) + 4); |
bfae80f2 | 26684 | |
c19d1205 | 26685 | switch (unwind.personality_index) |
bfae80f2 | 26686 | { |
c19d1205 ZW |
26687 | case -1: |
26688 | /* ??? Should this be a PLT generating relocation? */ | |
26689 | /* Custom personality routine. */ | |
26690 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
26691 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 26692 | |
c19d1205 ZW |
26693 | where += 4; |
26694 | ptr += 4; | |
bfae80f2 | 26695 | |
c19d1205 | 26696 | /* Set the first byte to the number of additional words. */ |
5011093d | 26697 | data = size > 0 ? size - 1 : 0; |
c19d1205 ZW |
26698 | n = 3; |
26699 | break; | |
bfae80f2 | 26700 | |
c19d1205 ZW |
26701 | /* ABI defined personality routines. */ |
26702 | case 0: | |
26703 | /* Three opcodes bytes are packed into the first word. */ | |
26704 | data = 0x80; | |
26705 | n = 3; | |
26706 | break; | |
bfae80f2 | 26707 | |
c19d1205 ZW |
26708 | case 1: |
26709 | case 2: | |
26710 | /* The size and first two opcode bytes go in the first word. */ | |
26711 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
26712 | n = 2; | |
26713 | break; | |
bfae80f2 | 26714 | |
c19d1205 ZW |
26715 | default: |
26716 | /* Should never happen. */ | |
26717 | abort (); | |
26718 | } | |
bfae80f2 | 26719 | |
c19d1205 ZW |
26720 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
26721 | time. */ | |
26722 | while (unwind.opcode_count > 0) | |
26723 | { | |
26724 | if (n == 0) | |
26725 | { | |
26726 | md_number_to_chars (ptr, data, 4); | |
26727 | ptr += 4; | |
26728 | n = 4; | |
26729 | data = 0; | |
26730 | } | |
26731 | unwind.opcode_count--; | |
26732 | n--; | |
26733 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
26734 | } | |
26735 | ||
26736 | /* Finish off the last word. */ | |
26737 | if (n < 4) | |
26738 | { | |
26739 | /* Pad with "finish" opcodes. */ | |
26740 | while (n--) | |
26741 | data = (data << 8) | 0xb0; | |
26742 | ||
26743 | md_number_to_chars (ptr, data, 4); | |
26744 | } | |
26745 | ||
26746 | if (!have_data) | |
26747 | { | |
26748 | /* Add an empty descriptor if there is no user-specified data. */ | |
26749 | ptr = frag_more (4); | |
26750 | md_number_to_chars (ptr, 0, 4); | |
26751 | } | |
26752 | ||
26753 | return 0; | |
bfae80f2 RE |
26754 | } |
26755 | ||
f0927246 NC |
26756 | |
26757 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
26758 | ||
26759 | void | |
26760 | tc_arm_frame_initial_instructions (void) | |
26761 | { | |
26762 | cfi_add_CFA_def_cfa (REG_SP, 0); | |
26763 | } | |
26764 | #endif /* OBJ_ELF */ | |
26765 | ||
c19d1205 ZW |
26766 | /* Convert REGNAME to a DWARF-2 register number. */ |
26767 | ||
26768 | int | |
1df69f4f | 26769 | tc_arm_regname_to_dw2regnum (char *regname) |
bfae80f2 | 26770 | { |
1df69f4f | 26771 | int reg = arm_reg_parse (®name, REG_TYPE_RN); |
1f5afe1c NC |
26772 | if (reg != FAIL) |
26773 | return reg; | |
c19d1205 | 26774 | |
1f5afe1c NC |
26775 | /* PR 16694: Allow VFP registers as well. */ |
26776 | reg = arm_reg_parse (®name, REG_TYPE_VFS); | |
26777 | if (reg != FAIL) | |
26778 | return 64 + reg; | |
c19d1205 | 26779 | |
1f5afe1c NC |
26780 | reg = arm_reg_parse (®name, REG_TYPE_VFD); |
26781 | if (reg != FAIL) | |
26782 | return reg + 256; | |
26783 | ||
0198d5e6 | 26784 | return FAIL; |
bfae80f2 RE |
26785 | } |
26786 | ||
f0927246 | 26787 | #ifdef TE_PE |
c19d1205 | 26788 | void |
f0927246 | 26789 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
bfae80f2 | 26790 | { |
91d6fa6a | 26791 | expressionS exp; |
bfae80f2 | 26792 | |
91d6fa6a NC |
26793 | exp.X_op = O_secrel; |
26794 | exp.X_add_symbol = symbol; | |
26795 | exp.X_add_number = 0; | |
26796 | emit_expr (&exp, size); | |
f0927246 NC |
26797 | } |
26798 | #endif | |
bfae80f2 | 26799 | |
c19d1205 | 26800 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 26801 | |
2fc8bdac ZW |
26802 | /* Return the address within the segment that a PC-relative fixup is |
26803 | relative to. For ARM, PC-relative fixups applied to instructions | |
26804 | are generally relative to the location of the fixup plus 8 bytes. | |
26805 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
26806 | require special handling. */ | |
bfae80f2 | 26807 | |
c19d1205 | 26808 | long |
2fc8bdac | 26809 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 26810 | { |
2fc8bdac ZW |
26811 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
26812 | ||
26813 | /* If this is pc-relative and we are going to emit a relocation | |
26814 | then we just want to put out any pipeline compensation that the linker | |
53baae48 NC |
26815 | will need. Otherwise we want to use the calculated base. |
26816 | For WinCE we skip the bias for externals as well, since this | |
26817 | is how the MS ARM-CE assembler behaves and we want to be compatible. */ | |
5f4273c7 | 26818 | if (fixP->fx_pcrel |
2fc8bdac | 26819 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) |
53baae48 NC |
26820 | || (arm_force_relocation (fixP) |
26821 | #ifdef TE_WINCE | |
26822 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
26823 | #endif | |
26824 | ))) | |
2fc8bdac | 26825 | base = 0; |
bfae80f2 | 26826 | |
267bf995 | 26827 | |
c19d1205 | 26828 | switch (fixP->fx_r_type) |
bfae80f2 | 26829 | { |
2fc8bdac ZW |
26830 | /* PC relative addressing on the Thumb is slightly odd as the |
26831 | bottom two bits of the PC are forced to zero for the | |
26832 | calculation. This happens *after* application of the | |
26833 | pipeline offset. However, Thumb adrl already adjusts for | |
26834 | this, so we need not do it again. */ | |
c19d1205 | 26835 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 26836 | return base & ~3; |
c19d1205 ZW |
26837 | |
26838 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
26839 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 26840 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 26841 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 26842 | return (base + 4) & ~3; |
c19d1205 | 26843 | |
2fc8bdac | 26844 | /* Thumb branches are simply offset by +4. */ |
e12437dc | 26845 | case BFD_RELOC_THUMB_PCREL_BRANCH5: |
2fc8bdac ZW |
26846 | case BFD_RELOC_THUMB_PCREL_BRANCH7: |
26847 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
26848 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
26849 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
2fc8bdac | 26850 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
f6b2b12d | 26851 | case BFD_RELOC_THUMB_PCREL_BFCSEL: |
e5d6e09e | 26852 | case BFD_RELOC_ARM_THUMB_BF17: |
1caf72a5 | 26853 | case BFD_RELOC_ARM_THUMB_BF19: |
1889da70 | 26854 | case BFD_RELOC_ARM_THUMB_BF13: |
60f993ce | 26855 | case BFD_RELOC_ARM_THUMB_LOOP12: |
2fc8bdac | 26856 | return base + 4; |
bfae80f2 | 26857 | |
267bf995 | 26858 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
486499d0 CL |
26859 | if (fixP->fx_addsy |
26860 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 26861 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 | 26862 | && ARM_IS_FUNC (fixP->fx_addsy) |
477330fc RM |
26863 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) |
26864 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
267bf995 RR |
26865 | return base + 4; |
26866 | ||
00adf2d4 JB |
26867 | /* BLX is like branches above, but forces the low two bits of PC to |
26868 | zero. */ | |
486499d0 CL |
26869 | case BFD_RELOC_THUMB_PCREL_BLX: |
26870 | if (fixP->fx_addsy | |
26871 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 26872 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
26873 | && THUMB_IS_FUNC (fixP->fx_addsy) |
26874 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
26875 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
00adf2d4 JB |
26876 | return (base + 4) & ~3; |
26877 | ||
2fc8bdac ZW |
26878 | /* ARM mode branches are offset by +8. However, the Windows CE |
26879 | loader expects the relocation not to take this into account. */ | |
267bf995 | 26880 | case BFD_RELOC_ARM_PCREL_BLX: |
486499d0 CL |
26881 | if (fixP->fx_addsy |
26882 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 26883 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
26884 | && ARM_IS_FUNC (fixP->fx_addsy) |
26885 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
26886 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 26887 | return base + 8; |
267bf995 | 26888 | |
486499d0 CL |
26889 | case BFD_RELOC_ARM_PCREL_CALL: |
26890 | if (fixP->fx_addsy | |
26891 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 26892 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
26893 | && THUMB_IS_FUNC (fixP->fx_addsy) |
26894 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
26895 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 26896 | return base + 8; |
267bf995 | 26897 | |
2fc8bdac | 26898 | case BFD_RELOC_ARM_PCREL_BRANCH: |
39b41c9c | 26899 | case BFD_RELOC_ARM_PCREL_JUMP: |
2fc8bdac | 26900 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 26901 | #ifdef TE_WINCE |
5f4273c7 | 26902 | /* When handling fixups immediately, because we have already |
477330fc | 26903 | discovered the value of a symbol, or the address of the frag involved |
53baae48 | 26904 | we must account for the offset by +8, as the OS loader will never see the reloc. |
477330fc RM |
26905 | see fixup_segment() in write.c |
26906 | The S_IS_EXTERNAL test handles the case of global symbols. | |
26907 | Those need the calculated base, not just the pipe compensation the linker will need. */ | |
53baae48 NC |
26908 | if (fixP->fx_pcrel |
26909 | && fixP->fx_addsy != NULL | |
26910 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
26911 | && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) | |
26912 | return base + 8; | |
2fc8bdac | 26913 | return base; |
c19d1205 | 26914 | #else |
2fc8bdac | 26915 | return base + 8; |
c19d1205 | 26916 | #endif |
2fc8bdac | 26917 | |
267bf995 | 26918 | |
2fc8bdac ZW |
26919 | /* ARM mode loads relative to PC are also offset by +8. Unlike |
26920 | branches, the Windows CE loader *does* expect the relocation | |
26921 | to take this into account. */ | |
26922 | case BFD_RELOC_ARM_OFFSET_IMM: | |
26923 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
26924 | case BFD_RELOC_ARM_HWLITERAL: | |
26925 | case BFD_RELOC_ARM_LITERAL: | |
26926 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
26927 | return base + 8; | |
26928 | ||
26929 | ||
26930 | /* Other PC-relative relocations are un-offset. */ | |
26931 | default: | |
26932 | return base; | |
26933 | } | |
bfae80f2 RE |
26934 | } |
26935 | ||
8b2d793c NC |
26936 | static bfd_boolean flag_warn_syms = TRUE; |
26937 | ||
ae8714c2 NC |
26938 | bfd_boolean |
26939 | arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name) | |
bfae80f2 | 26940 | { |
8b2d793c NC |
26941 | /* PR 18347 - Warn if the user attempts to create a symbol with the same |
26942 | name as an ARM instruction. Whilst strictly speaking it is allowed, it | |
26943 | does mean that the resulting code might be very confusing to the reader. | |
26944 | Also this warning can be triggered if the user omits an operand before | |
26945 | an immediate address, eg: | |
26946 | ||
26947 | LDR =foo | |
26948 | ||
26949 | GAS treats this as an assignment of the value of the symbol foo to a | |
26950 | symbol LDR, and so (without this code) it will not issue any kind of | |
26951 | warning or error message. | |
26952 | ||
26953 | Note - ARM instructions are case-insensitive but the strings in the hash | |
26954 | table are all stored in lower case, so we must first ensure that name is | |
ae8714c2 NC |
26955 | lower case too. */ |
26956 | if (flag_warn_syms && arm_ops_hsh) | |
8b2d793c NC |
26957 | { |
26958 | char * nbuf = strdup (name); | |
26959 | char * p; | |
26960 | ||
26961 | for (p = nbuf; *p; p++) | |
26962 | *p = TOLOWER (*p); | |
26963 | if (hash_find (arm_ops_hsh, nbuf) != NULL) | |
26964 | { | |
26965 | static struct hash_control * already_warned = NULL; | |
26966 | ||
26967 | if (already_warned == NULL) | |
26968 | already_warned = hash_new (); | |
26969 | /* Only warn about the symbol once. To keep the code | |
26970 | simple we let hash_insert do the lookup for us. */ | |
3076e594 | 26971 | if (hash_insert (already_warned, nbuf, NULL) == NULL) |
ae8714c2 | 26972 | as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name); |
8b2d793c NC |
26973 | } |
26974 | else | |
26975 | free (nbuf); | |
26976 | } | |
3739860c | 26977 | |
ae8714c2 NC |
26978 | return FALSE; |
26979 | } | |
26980 | ||
26981 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. | |
26982 | Otherwise we have no need to default values of symbols. */ | |
26983 | ||
26984 | symbolS * | |
26985 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
26986 | { | |
26987 | #ifdef OBJ_ELF | |
26988 | if (name[0] == '_' && name[1] == 'G' | |
26989 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
26990 | { | |
26991 | if (!GOT_symbol) | |
26992 | { | |
26993 | if (symbol_find (name)) | |
26994 | as_bad (_("GOT already in the symbol table")); | |
26995 | ||
26996 | GOT_symbol = symbol_new (name, undefined_section, | |
26997 | (valueT) 0, & zero_address_frag); | |
26998 | } | |
26999 | ||
27000 | return GOT_symbol; | |
27001 | } | |
27002 | #endif | |
27003 | ||
c921be7d | 27004 | return NULL; |
bfae80f2 RE |
27005 | } |
27006 | ||
55cf6793 | 27007 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
27008 | computed as two separate immediate values, added together. We |
27009 | already know that this value cannot be computed by just one ARM | |
27010 | instruction. */ | |
27011 | ||
27012 | static unsigned int | |
27013 | validate_immediate_twopart (unsigned int val, | |
27014 | unsigned int * highpart) | |
bfae80f2 | 27015 | { |
c19d1205 ZW |
27016 | unsigned int a; |
27017 | unsigned int i; | |
bfae80f2 | 27018 | |
c19d1205 ZW |
27019 | for (i = 0; i < 32; i += 2) |
27020 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
27021 | { | |
27022 | if (a & 0xff00) | |
27023 | { | |
27024 | if (a & ~ 0xffff) | |
27025 | continue; | |
27026 | * highpart = (a >> 8) | ((i + 24) << 7); | |
27027 | } | |
27028 | else if (a & 0xff0000) | |
27029 | { | |
27030 | if (a & 0xff000000) | |
27031 | continue; | |
27032 | * highpart = (a >> 16) | ((i + 16) << 7); | |
27033 | } | |
27034 | else | |
27035 | { | |
9c2799c2 | 27036 | gas_assert (a & 0xff000000); |
c19d1205 ZW |
27037 | * highpart = (a >> 24) | ((i + 8) << 7); |
27038 | } | |
bfae80f2 | 27039 | |
c19d1205 ZW |
27040 | return (a & 0xff) | (i << 7); |
27041 | } | |
bfae80f2 | 27042 | |
c19d1205 | 27043 | return FAIL; |
bfae80f2 RE |
27044 | } |
27045 | ||
c19d1205 ZW |
27046 | static int |
27047 | validate_offset_imm (unsigned int val, int hwse) | |
27048 | { | |
27049 | if ((hwse && val > 255) || val > 4095) | |
27050 | return FAIL; | |
27051 | return val; | |
27052 | } | |
bfae80f2 | 27053 | |
55cf6793 | 27054 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
27055 | negative immediate constant by altering the instruction. A bit of |
27056 | a hack really. | |
27057 | MOV <-> MVN | |
27058 | AND <-> BIC | |
27059 | ADC <-> SBC | |
27060 | by inverting the second operand, and | |
27061 | ADD <-> SUB | |
27062 | CMP <-> CMN | |
27063 | by negating the second operand. */ | |
bfae80f2 | 27064 | |
c19d1205 ZW |
27065 | static int |
27066 | negate_data_op (unsigned long * instruction, | |
27067 | unsigned long value) | |
bfae80f2 | 27068 | { |
c19d1205 ZW |
27069 | int op, new_inst; |
27070 | unsigned long negated, inverted; | |
bfae80f2 | 27071 | |
c19d1205 ZW |
27072 | negated = encode_arm_immediate (-value); |
27073 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 27074 | |
c19d1205 ZW |
27075 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
27076 | switch (op) | |
bfae80f2 | 27077 | { |
c19d1205 ZW |
27078 | /* First negates. */ |
27079 | case OPCODE_SUB: /* ADD <-> SUB */ | |
27080 | new_inst = OPCODE_ADD; | |
27081 | value = negated; | |
27082 | break; | |
bfae80f2 | 27083 | |
c19d1205 ZW |
27084 | case OPCODE_ADD: |
27085 | new_inst = OPCODE_SUB; | |
27086 | value = negated; | |
27087 | break; | |
bfae80f2 | 27088 | |
c19d1205 ZW |
27089 | case OPCODE_CMP: /* CMP <-> CMN */ |
27090 | new_inst = OPCODE_CMN; | |
27091 | value = negated; | |
27092 | break; | |
bfae80f2 | 27093 | |
c19d1205 ZW |
27094 | case OPCODE_CMN: |
27095 | new_inst = OPCODE_CMP; | |
27096 | value = negated; | |
27097 | break; | |
bfae80f2 | 27098 | |
c19d1205 ZW |
27099 | /* Now Inverted ops. */ |
27100 | case OPCODE_MOV: /* MOV <-> MVN */ | |
27101 | new_inst = OPCODE_MVN; | |
27102 | value = inverted; | |
27103 | break; | |
bfae80f2 | 27104 | |
c19d1205 ZW |
27105 | case OPCODE_MVN: |
27106 | new_inst = OPCODE_MOV; | |
27107 | value = inverted; | |
27108 | break; | |
bfae80f2 | 27109 | |
c19d1205 ZW |
27110 | case OPCODE_AND: /* AND <-> BIC */ |
27111 | new_inst = OPCODE_BIC; | |
27112 | value = inverted; | |
27113 | break; | |
bfae80f2 | 27114 | |
c19d1205 ZW |
27115 | case OPCODE_BIC: |
27116 | new_inst = OPCODE_AND; | |
27117 | value = inverted; | |
27118 | break; | |
bfae80f2 | 27119 | |
c19d1205 ZW |
27120 | case OPCODE_ADC: /* ADC <-> SBC */ |
27121 | new_inst = OPCODE_SBC; | |
27122 | value = inverted; | |
27123 | break; | |
bfae80f2 | 27124 | |
c19d1205 ZW |
27125 | case OPCODE_SBC: |
27126 | new_inst = OPCODE_ADC; | |
27127 | value = inverted; | |
27128 | break; | |
bfae80f2 | 27129 | |
c19d1205 ZW |
27130 | /* We cannot do anything. */ |
27131 | default: | |
27132 | return FAIL; | |
b99bd4ef NC |
27133 | } |
27134 | ||
c19d1205 ZW |
27135 | if (value == (unsigned) FAIL) |
27136 | return FAIL; | |
27137 | ||
27138 | *instruction &= OPCODE_MASK; | |
27139 | *instruction |= new_inst << DATA_OP_SHIFT; | |
27140 | return value; | |
b99bd4ef NC |
27141 | } |
27142 | ||
ef8d22e6 PB |
27143 | /* Like negate_data_op, but for Thumb-2. */ |
27144 | ||
27145 | static unsigned int | |
16dd5e42 | 27146 | thumb32_negate_data_op (offsetT *instruction, unsigned int value) |
ef8d22e6 PB |
27147 | { |
27148 | int op, new_inst; | |
27149 | int rd; | |
16dd5e42 | 27150 | unsigned int negated, inverted; |
ef8d22e6 PB |
27151 | |
27152 | negated = encode_thumb32_immediate (-value); | |
27153 | inverted = encode_thumb32_immediate (~value); | |
27154 | ||
27155 | rd = (*instruction >> 8) & 0xf; | |
27156 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; | |
27157 | switch (op) | |
27158 | { | |
27159 | /* ADD <-> SUB. Includes CMP <-> CMN. */ | |
27160 | case T2_OPCODE_SUB: | |
27161 | new_inst = T2_OPCODE_ADD; | |
27162 | value = negated; | |
27163 | break; | |
27164 | ||
27165 | case T2_OPCODE_ADD: | |
27166 | new_inst = T2_OPCODE_SUB; | |
27167 | value = negated; | |
27168 | break; | |
27169 | ||
27170 | /* ORR <-> ORN. Includes MOV <-> MVN. */ | |
27171 | case T2_OPCODE_ORR: | |
27172 | new_inst = T2_OPCODE_ORN; | |
27173 | value = inverted; | |
27174 | break; | |
27175 | ||
27176 | case T2_OPCODE_ORN: | |
27177 | new_inst = T2_OPCODE_ORR; | |
27178 | value = inverted; | |
27179 | break; | |
27180 | ||
27181 | /* AND <-> BIC. TST has no inverted equivalent. */ | |
27182 | case T2_OPCODE_AND: | |
27183 | new_inst = T2_OPCODE_BIC; | |
27184 | if (rd == 15) | |
27185 | value = FAIL; | |
27186 | else | |
27187 | value = inverted; | |
27188 | break; | |
27189 | ||
27190 | case T2_OPCODE_BIC: | |
27191 | new_inst = T2_OPCODE_AND; | |
27192 | value = inverted; | |
27193 | break; | |
27194 | ||
27195 | /* ADC <-> SBC */ | |
27196 | case T2_OPCODE_ADC: | |
27197 | new_inst = T2_OPCODE_SBC; | |
27198 | value = inverted; | |
27199 | break; | |
27200 | ||
27201 | case T2_OPCODE_SBC: | |
27202 | new_inst = T2_OPCODE_ADC; | |
27203 | value = inverted; | |
27204 | break; | |
27205 | ||
27206 | /* We cannot do anything. */ | |
27207 | default: | |
27208 | return FAIL; | |
27209 | } | |
27210 | ||
16dd5e42 | 27211 | if (value == (unsigned int)FAIL) |
ef8d22e6 PB |
27212 | return FAIL; |
27213 | ||
27214 | *instruction &= T2_OPCODE_MASK; | |
27215 | *instruction |= new_inst << T2_DATA_OP_SHIFT; | |
27216 | return value; | |
27217 | } | |
27218 | ||
8f06b2d8 | 27219 | /* Read a 32-bit thumb instruction from buf. */ |
0198d5e6 | 27220 | |
8f06b2d8 PB |
27221 | static unsigned long |
27222 | get_thumb32_insn (char * buf) | |
27223 | { | |
27224 | unsigned long insn; | |
27225 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
27226 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
27227 | ||
27228 | return insn; | |
27229 | } | |
27230 | ||
a8bc6c78 PB |
27231 | /* We usually want to set the low bit on the address of thumb function |
27232 | symbols. In particular .word foo - . should have the low bit set. | |
27233 | Generic code tries to fold the difference of two symbols to | |
27234 | a constant. Prevent this and force a relocation when the first symbols | |
27235 | is a thumb function. */ | |
c921be7d NC |
27236 | |
27237 | bfd_boolean | |
a8bc6c78 PB |
27238 | arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) |
27239 | { | |
27240 | if (op == O_subtract | |
27241 | && l->X_op == O_symbol | |
27242 | && r->X_op == O_symbol | |
27243 | && THUMB_IS_FUNC (l->X_add_symbol)) | |
27244 | { | |
27245 | l->X_op = O_subtract; | |
27246 | l->X_op_symbol = r->X_add_symbol; | |
27247 | l->X_add_number -= r->X_add_number; | |
c921be7d | 27248 | return TRUE; |
a8bc6c78 | 27249 | } |
c921be7d | 27250 | |
a8bc6c78 | 27251 | /* Process as normal. */ |
c921be7d | 27252 | return FALSE; |
a8bc6c78 PB |
27253 | } |
27254 | ||
4a42ebbc RR |
27255 | /* Encode Thumb2 unconditional branches and calls. The encoding |
27256 | for the 2 are identical for the immediate values. */ | |
27257 | ||
27258 | static void | |
27259 | encode_thumb2_b_bl_offset (char * buf, offsetT value) | |
27260 | { | |
27261 | #define T2I1I2MASK ((1 << 13) | (1 << 11)) | |
27262 | offsetT newval; | |
27263 | offsetT newval2; | |
27264 | addressT S, I1, I2, lo, hi; | |
27265 | ||
27266 | S = (value >> 24) & 0x01; | |
27267 | I1 = (value >> 23) & 0x01; | |
27268 | I2 = (value >> 22) & 0x01; | |
27269 | hi = (value >> 12) & 0x3ff; | |
fa94de6b | 27270 | lo = (value >> 1) & 0x7ff; |
4a42ebbc RR |
27271 | newval = md_chars_to_number (buf, THUMB_SIZE); |
27272 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
27273 | newval |= (S << 10) | hi; | |
27274 | newval2 &= ~T2I1I2MASK; | |
27275 | newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK; | |
27276 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
27277 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
27278 | } | |
27279 | ||
c19d1205 | 27280 | void |
55cf6793 | 27281 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
27282 | valueT * valP, |
27283 | segT seg) | |
27284 | { | |
27285 | offsetT value = * valP; | |
27286 | offsetT newval; | |
27287 | unsigned int newimm; | |
27288 | unsigned long temp; | |
27289 | int sign; | |
27290 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 27291 | |
9c2799c2 | 27292 | gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 27293 | |
c19d1205 | 27294 | /* Note whether this will delete the relocation. */ |
4962c51a | 27295 | |
c19d1205 ZW |
27296 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) |
27297 | fixP->fx_done = 1; | |
b99bd4ef | 27298 | |
adbaf948 | 27299 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
5f4273c7 | 27300 | consistency with the behaviour on 32-bit hosts. Remember value |
adbaf948 ZW |
27301 | for emit_reloc. */ |
27302 | value &= 0xffffffff; | |
27303 | value ^= 0x80000000; | |
5f4273c7 | 27304 | value -= 0x80000000; |
adbaf948 ZW |
27305 | |
27306 | *valP = value; | |
c19d1205 | 27307 | fixP->fx_addnumber = value; |
b99bd4ef | 27308 | |
adbaf948 ZW |
27309 | /* Same treatment for fixP->fx_offset. */ |
27310 | fixP->fx_offset &= 0xffffffff; | |
27311 | fixP->fx_offset ^= 0x80000000; | |
27312 | fixP->fx_offset -= 0x80000000; | |
27313 | ||
c19d1205 | 27314 | switch (fixP->fx_r_type) |
b99bd4ef | 27315 | { |
c19d1205 ZW |
27316 | case BFD_RELOC_NONE: |
27317 | /* This will need to go in the object file. */ | |
27318 | fixP->fx_done = 0; | |
27319 | break; | |
b99bd4ef | 27320 | |
c19d1205 ZW |
27321 | case BFD_RELOC_ARM_IMMEDIATE: |
27322 | /* We claim that this fixup has been processed here, | |
27323 | even if in fact we generate an error because we do | |
27324 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
27325 | fixP->fx_done = 1; | |
b99bd4ef | 27326 | |
77db8e2e | 27327 | if (fixP->fx_addsy) |
b99bd4ef | 27328 | { |
77db8e2e | 27329 | const char *msg = 0; |
b99bd4ef | 27330 | |
77db8e2e NC |
27331 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
27332 | msg = _("undefined symbol %s used as an immediate value"); | |
27333 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
27334 | msg = _("symbol %s is in a different section"); | |
27335 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
27336 | msg = _("symbol %s is weak and may be overridden later"); | |
27337 | ||
27338 | if (msg) | |
27339 | { | |
27340 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27341 | msg, S_GET_NAME (fixP->fx_addsy)); | |
27342 | break; | |
27343 | } | |
42e5fcbf AS |
27344 | } |
27345 | ||
c19d1205 ZW |
27346 | temp = md_chars_to_number (buf, INSN_SIZE); |
27347 | ||
5e73442d SL |
27348 | /* If the offset is negative, we should use encoding A2 for ADR. */ |
27349 | if ((temp & 0xfff0000) == 0x28f0000 && value < 0) | |
27350 | newimm = negate_data_op (&temp, value); | |
27351 | else | |
27352 | { | |
27353 | newimm = encode_arm_immediate (value); | |
27354 | ||
27355 | /* If the instruction will fail, see if we can fix things up by | |
27356 | changing the opcode. */ | |
27357 | if (newimm == (unsigned int) FAIL) | |
27358 | newimm = negate_data_op (&temp, value); | |
bada4342 JW |
27359 | /* MOV accepts both ARM modified immediate (A1 encoding) and |
27360 | UINT16 (A2 encoding) when possible, MOVW only accepts UINT16. | |
27361 | When disassembling, MOV is preferred when there is no encoding | |
27362 | overlap. */ | |
27363 | if (newimm == (unsigned int) FAIL | |
27364 | && ((temp >> DATA_OP_SHIFT) & 0xf) == OPCODE_MOV | |
27365 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2) | |
27366 | && !((temp >> SBIT_SHIFT) & 0x1) | |
27367 | && value >= 0 && value <= 0xffff) | |
27368 | { | |
27369 | /* Clear bits[23:20] to change encoding from A1 to A2. */ | |
27370 | temp &= 0xff0fffff; | |
27371 | /* Encoding high 4bits imm. Code below will encode the remaining | |
27372 | low 12bits. */ | |
27373 | temp |= (value & 0x0000f000) << 4; | |
27374 | newimm = value & 0x00000fff; | |
27375 | } | |
5e73442d SL |
27376 | } |
27377 | ||
27378 | if (newimm == (unsigned int) FAIL) | |
b99bd4ef | 27379 | { |
c19d1205 ZW |
27380 | as_bad_where (fixP->fx_file, fixP->fx_line, |
27381 | _("invalid constant (%lx) after fixup"), | |
27382 | (unsigned long) value); | |
27383 | break; | |
b99bd4ef | 27384 | } |
b99bd4ef | 27385 | |
c19d1205 ZW |
27386 | newimm |= (temp & 0xfffff000); |
27387 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
27388 | break; | |
b99bd4ef | 27389 | |
c19d1205 ZW |
27390 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
27391 | { | |
27392 | unsigned int highpart = 0; | |
27393 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 27394 | |
77db8e2e | 27395 | if (fixP->fx_addsy) |
42e5fcbf | 27396 | { |
77db8e2e | 27397 | const char *msg = 0; |
42e5fcbf | 27398 | |
77db8e2e NC |
27399 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
27400 | msg = _("undefined symbol %s used as an immediate value"); | |
27401 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
27402 | msg = _("symbol %s is in a different section"); | |
27403 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
27404 | msg = _("symbol %s is weak and may be overridden later"); | |
42e5fcbf | 27405 | |
77db8e2e NC |
27406 | if (msg) |
27407 | { | |
27408 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27409 | msg, S_GET_NAME (fixP->fx_addsy)); | |
27410 | break; | |
27411 | } | |
27412 | } | |
fa94de6b | 27413 | |
c19d1205 ZW |
27414 | newimm = encode_arm_immediate (value); |
27415 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 27416 | |
c19d1205 ZW |
27417 | /* If the instruction will fail, see if we can fix things up by |
27418 | changing the opcode. */ | |
27419 | if (newimm == (unsigned int) FAIL | |
27420 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
27421 | { | |
27422 | /* No ? OK - try using two ADD instructions to generate | |
27423 | the value. */ | |
27424 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 27425 | |
c19d1205 ZW |
27426 | /* Yes - then make sure that the second instruction is |
27427 | also an add. */ | |
27428 | if (newimm != (unsigned int) FAIL) | |
27429 | newinsn = temp; | |
27430 | /* Still No ? Try using a negated value. */ | |
27431 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
27432 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
27433 | /* Otherwise - give up. */ | |
27434 | else | |
27435 | { | |
27436 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27437 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
27438 | (long) value); | |
27439 | break; | |
27440 | } | |
b99bd4ef | 27441 | |
c19d1205 ZW |
27442 | /* Replace the first operand in the 2nd instruction (which |
27443 | is the PC) with the destination register. We have | |
27444 | already added in the PC in the first instruction and we | |
27445 | do not want to do it again. */ | |
27446 | newinsn &= ~ 0xf0000; | |
27447 | newinsn |= ((newinsn & 0x0f000) << 4); | |
27448 | } | |
b99bd4ef | 27449 | |
c19d1205 ZW |
27450 | newimm |= (temp & 0xfffff000); |
27451 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 27452 | |
c19d1205 ZW |
27453 | highpart |= (newinsn & 0xfffff000); |
27454 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
27455 | } | |
27456 | break; | |
b99bd4ef | 27457 | |
c19d1205 | 27458 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
27459 | if (!fixP->fx_done && seg->use_rela_p) |
27460 | value = 0; | |
1a0670f3 | 27461 | /* Fall through. */ |
00a97672 | 27462 | |
c19d1205 | 27463 | case BFD_RELOC_ARM_LITERAL: |
26d97720 | 27464 | sign = value > 0; |
b99bd4ef | 27465 | |
c19d1205 ZW |
27466 | if (value < 0) |
27467 | value = - value; | |
b99bd4ef | 27468 | |
c19d1205 | 27469 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 27470 | { |
c19d1205 ZW |
27471 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
27472 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27473 | _("invalid literal constant: pool needs to be closer")); | |
27474 | else | |
27475 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27476 | _("bad immediate value for offset (%ld)"), | |
27477 | (long) value); | |
27478 | break; | |
f03698e6 RE |
27479 | } |
27480 | ||
c19d1205 | 27481 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
27482 | if (value == 0) |
27483 | newval &= 0xfffff000; | |
27484 | else | |
27485 | { | |
27486 | newval &= 0xff7ff000; | |
27487 | newval |= value | (sign ? INDEX_UP : 0); | |
27488 | } | |
c19d1205 ZW |
27489 | md_number_to_chars (buf, newval, INSN_SIZE); |
27490 | break; | |
b99bd4ef | 27491 | |
c19d1205 ZW |
27492 | case BFD_RELOC_ARM_OFFSET_IMM8: |
27493 | case BFD_RELOC_ARM_HWLITERAL: | |
26d97720 | 27494 | sign = value > 0; |
b99bd4ef | 27495 | |
c19d1205 ZW |
27496 | if (value < 0) |
27497 | value = - value; | |
b99bd4ef | 27498 | |
c19d1205 | 27499 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 27500 | { |
c19d1205 ZW |
27501 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
27502 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27503 | _("invalid literal constant: pool needs to be closer")); | |
27504 | else | |
427d0db6 RM |
27505 | as_bad_where (fixP->fx_file, fixP->fx_line, |
27506 | _("bad immediate value for 8-bit offset (%ld)"), | |
27507 | (long) value); | |
c19d1205 | 27508 | break; |
b99bd4ef NC |
27509 | } |
27510 | ||
c19d1205 | 27511 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
27512 | if (value == 0) |
27513 | newval &= 0xfffff0f0; | |
27514 | else | |
27515 | { | |
27516 | newval &= 0xff7ff0f0; | |
27517 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
27518 | } | |
c19d1205 ZW |
27519 | md_number_to_chars (buf, newval, INSN_SIZE); |
27520 | break; | |
b99bd4ef | 27521 | |
c19d1205 ZW |
27522 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
27523 | if (value < 0 || value > 1020 || value % 4 != 0) | |
27524 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27525 | _("bad immediate value for offset (%ld)"), (long) value); | |
27526 | value /= 4; | |
b99bd4ef | 27527 | |
c19d1205 | 27528 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
27529 | newval |= value; |
27530 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
27531 | break; | |
b99bd4ef | 27532 | |
c19d1205 ZW |
27533 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
27534 | /* This is a complicated relocation used for all varieties of Thumb32 | |
27535 | load/store instruction with immediate offset: | |
27536 | ||
27537 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
477330fc | 27538 | *4, optional writeback(W) |
c19d1205 ZW |
27539 | (doubleword load/store) |
27540 | ||
27541 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
27542 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
27543 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
27544 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
27545 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
27546 | ||
27547 | Uppercase letters indicate bits that are already encoded at | |
27548 | this point. Lowercase letters are our problem. For the | |
27549 | second block of instructions, the secondary opcode nybble | |
27550 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
27551 | a PC-relative operation. */ | |
27552 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
27553 | newval <<= 16; | |
27554 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 27555 | |
c19d1205 | 27556 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 27557 | { |
c19d1205 ZW |
27558 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
27559 | if (value >= 0) | |
27560 | newval |= (1 << 23); | |
27561 | else | |
27562 | value = -value; | |
27563 | if (value % 4 != 0) | |
27564 | { | |
27565 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27566 | _("offset not a multiple of 4")); | |
27567 | break; | |
27568 | } | |
27569 | value /= 4; | |
216d22bc | 27570 | if (value > 0xff) |
c19d1205 ZW |
27571 | { |
27572 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27573 | _("offset out of range")); | |
27574 | break; | |
27575 | } | |
27576 | newval &= ~0xff; | |
b99bd4ef | 27577 | } |
c19d1205 | 27578 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 27579 | { |
c19d1205 ZW |
27580 | /* PC-relative, 12-bit offset. */ |
27581 | if (value >= 0) | |
27582 | newval |= (1 << 23); | |
27583 | else | |
27584 | value = -value; | |
216d22bc | 27585 | if (value > 0xfff) |
c19d1205 ZW |
27586 | { |
27587 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27588 | _("offset out of range")); | |
27589 | break; | |
27590 | } | |
27591 | newval &= ~0xfff; | |
b99bd4ef | 27592 | } |
c19d1205 | 27593 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 27594 | { |
c19d1205 ZW |
27595 | /* Writeback: 8-bit, +/- offset. */ |
27596 | if (value >= 0) | |
27597 | newval |= (1 << 9); | |
27598 | else | |
27599 | value = -value; | |
216d22bc | 27600 | if (value > 0xff) |
c19d1205 ZW |
27601 | { |
27602 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27603 | _("offset out of range")); | |
27604 | break; | |
27605 | } | |
27606 | newval &= ~0xff; | |
b99bd4ef | 27607 | } |
c19d1205 | 27608 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 27609 | { |
c19d1205 | 27610 | /* T-instruction: positive 8-bit offset. */ |
216d22bc | 27611 | if (value < 0 || value > 0xff) |
b99bd4ef | 27612 | { |
c19d1205 ZW |
27613 | as_bad_where (fixP->fx_file, fixP->fx_line, |
27614 | _("offset out of range")); | |
27615 | break; | |
b99bd4ef | 27616 | } |
c19d1205 ZW |
27617 | newval &= ~0xff; |
27618 | newval |= value; | |
b99bd4ef NC |
27619 | } |
27620 | else | |
b99bd4ef | 27621 | { |
c19d1205 ZW |
27622 | /* Positive 12-bit or negative 8-bit offset. */ |
27623 | int limit; | |
27624 | if (value >= 0) | |
b99bd4ef | 27625 | { |
c19d1205 ZW |
27626 | newval |= (1 << 23); |
27627 | limit = 0xfff; | |
27628 | } | |
27629 | else | |
27630 | { | |
27631 | value = -value; | |
27632 | limit = 0xff; | |
27633 | } | |
27634 | if (value > limit) | |
27635 | { | |
27636 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27637 | _("offset out of range")); | |
27638 | break; | |
b99bd4ef | 27639 | } |
c19d1205 | 27640 | newval &= ~limit; |
b99bd4ef | 27641 | } |
b99bd4ef | 27642 | |
c19d1205 ZW |
27643 | newval |= value; |
27644 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
27645 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
27646 | break; | |
404ff6b5 | 27647 | |
c19d1205 ZW |
27648 | case BFD_RELOC_ARM_SHIFT_IMM: |
27649 | newval = md_chars_to_number (buf, INSN_SIZE); | |
27650 | if (((unsigned long) value) > 32 | |
27651 | || (value == 32 | |
27652 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
27653 | { | |
27654 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27655 | _("shift expression is too large")); | |
27656 | break; | |
27657 | } | |
404ff6b5 | 27658 | |
c19d1205 ZW |
27659 | if (value == 0) |
27660 | /* Shifts of zero must be done as lsl. */ | |
27661 | newval &= ~0x60; | |
27662 | else if (value == 32) | |
27663 | value = 0; | |
27664 | newval &= 0xfffff07f; | |
27665 | newval |= (value & 0x1f) << 7; | |
27666 | md_number_to_chars (buf, newval, INSN_SIZE); | |
27667 | break; | |
404ff6b5 | 27668 | |
c19d1205 | 27669 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
16805f35 | 27670 | case BFD_RELOC_ARM_T32_ADD_IMM: |
92e90b6e | 27671 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 27672 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
27673 | /* We claim that this fixup has been processed here, |
27674 | even if in fact we generate an error because we do | |
27675 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
27676 | fixP->fx_done = 1; | |
404ff6b5 | 27677 | |
c19d1205 ZW |
27678 | if (fixP->fx_addsy |
27679 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
27680 | { | |
27681 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27682 | _("undefined symbol %s used as an immediate value"), | |
27683 | S_GET_NAME (fixP->fx_addsy)); | |
27684 | break; | |
27685 | } | |
404ff6b5 | 27686 | |
c19d1205 ZW |
27687 | newval = md_chars_to_number (buf, THUMB_SIZE); |
27688 | newval <<= 16; | |
27689 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 27690 | |
16805f35 | 27691 | newimm = FAIL; |
bada4342 JW |
27692 | if ((fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
27693 | /* ARMv8-M Baseline MOV will reach here, but it doesn't support | |
27694 | Thumb2 modified immediate encoding (T2). */ | |
27695 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)) | |
16805f35 | 27696 | || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) |
ef8d22e6 PB |
27697 | { |
27698 | newimm = encode_thumb32_immediate (value); | |
27699 | if (newimm == (unsigned int) FAIL) | |
27700 | newimm = thumb32_negate_data_op (&newval, value); | |
27701 | } | |
bada4342 | 27702 | if (newimm == (unsigned int) FAIL) |
92e90b6e | 27703 | { |
bada4342 | 27704 | if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE) |
e9f89963 | 27705 | { |
bada4342 JW |
27706 | /* Turn add/sum into addw/subw. */ |
27707 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
27708 | newval = (newval & 0xfeffffff) | 0x02000000; | |
27709 | /* No flat 12-bit imm encoding for addsw/subsw. */ | |
27710 | if ((newval & 0x00100000) == 0) | |
40f246e3 | 27711 | { |
bada4342 JW |
27712 | /* 12 bit immediate for addw/subw. */ |
27713 | if (value < 0) | |
27714 | { | |
27715 | value = -value; | |
27716 | newval ^= 0x00a00000; | |
27717 | } | |
27718 | if (value > 0xfff) | |
27719 | newimm = (unsigned int) FAIL; | |
27720 | else | |
27721 | newimm = value; | |
27722 | } | |
27723 | } | |
27724 | else | |
27725 | { | |
27726 | /* MOV accepts both Thumb2 modified immediate (T2 encoding) and | |
27727 | UINT16 (T3 encoding), MOVW only accepts UINT16. When | |
27728 | disassembling, MOV is preferred when there is no encoding | |
db7bf105 | 27729 | overlap. */ |
bada4342 | 27730 | if (((newval >> T2_DATA_OP_SHIFT) & 0xf) == T2_OPCODE_ORR |
db7bf105 NC |
27731 | /* NOTE: MOV uses the ORR opcode in Thumb 2 mode |
27732 | but with the Rn field [19:16] set to 1111. */ | |
27733 | && (((newval >> 16) & 0xf) == 0xf) | |
bada4342 JW |
27734 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m) |
27735 | && !((newval >> T2_SBIT_SHIFT) & 0x1) | |
db7bf105 | 27736 | && value >= 0 && value <= 0xffff) |
bada4342 JW |
27737 | { |
27738 | /* Toggle bit[25] to change encoding from T2 to T3. */ | |
27739 | newval ^= 1 << 25; | |
27740 | /* Clear bits[19:16]. */ | |
27741 | newval &= 0xfff0ffff; | |
27742 | /* Encoding high 4bits imm. Code below will encode the | |
27743 | remaining low 12bits. */ | |
27744 | newval |= (value & 0x0000f000) << 4; | |
27745 | newimm = value & 0x00000fff; | |
40f246e3 | 27746 | } |
e9f89963 | 27747 | } |
92e90b6e | 27748 | } |
cc8a6dd0 | 27749 | |
c19d1205 | 27750 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 27751 | { |
c19d1205 ZW |
27752 | as_bad_where (fixP->fx_file, fixP->fx_line, |
27753 | _("invalid constant (%lx) after fixup"), | |
27754 | (unsigned long) value); | |
27755 | break; | |
3631a3c8 NC |
27756 | } |
27757 | ||
c19d1205 ZW |
27758 | newval |= (newimm & 0x800) << 15; |
27759 | newval |= (newimm & 0x700) << 4; | |
27760 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 27761 | |
c19d1205 ZW |
27762 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
27763 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
27764 | break; | |
a737bd4d | 27765 | |
3eb17e6b | 27766 | case BFD_RELOC_ARM_SMC: |
ba85f98c | 27767 | if (((unsigned long) value) > 0xf) |
c19d1205 | 27768 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3eb17e6b | 27769 | _("invalid smc expression")); |
ba85f98c | 27770 | |
2fc8bdac | 27771 | newval = md_chars_to_number (buf, INSN_SIZE); |
ba85f98c | 27772 | newval |= (value & 0xf); |
c19d1205 ZW |
27773 | md_number_to_chars (buf, newval, INSN_SIZE); |
27774 | break; | |
a737bd4d | 27775 | |
90ec0d68 MGD |
27776 | case BFD_RELOC_ARM_HVC: |
27777 | if (((unsigned long) value) > 0xffff) | |
27778 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27779 | _("invalid hvc expression")); | |
27780 | newval = md_chars_to_number (buf, INSN_SIZE); | |
27781 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); | |
27782 | md_number_to_chars (buf, newval, INSN_SIZE); | |
27783 | break; | |
27784 | ||
c19d1205 | 27785 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 27786 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
27787 | { |
27788 | if (((unsigned long) value) > 0xff) | |
27789 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27790 | _("invalid swi expression")); | |
2fc8bdac | 27791 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
27792 | newval |= value; |
27793 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
27794 | } | |
27795 | else | |
27796 | { | |
27797 | if (((unsigned long) value) > 0x00ffffff) | |
27798 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27799 | _("invalid swi expression")); | |
2fc8bdac | 27800 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
27801 | newval |= value; |
27802 | md_number_to_chars (buf, newval, INSN_SIZE); | |
27803 | } | |
27804 | break; | |
a737bd4d | 27805 | |
c19d1205 ZW |
27806 | case BFD_RELOC_ARM_MULTI: |
27807 | if (((unsigned long) value) > 0xffff) | |
27808 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27809 | _("invalid expression in load/store multiple")); | |
27810 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
27811 | md_number_to_chars (buf, newval, INSN_SIZE); | |
27812 | break; | |
a737bd4d | 27813 | |
c19d1205 | 27814 | #ifdef OBJ_ELF |
39b41c9c | 27815 | case BFD_RELOC_ARM_PCREL_CALL: |
267bf995 RR |
27816 | |
27817 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
27818 | && fixP->fx_addsy | |
34e77a92 | 27819 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
27820 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
27821 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
27822 | /* Flip the bl to blx. This is a simple flip | |
27823 | bit here because we generate PCREL_CALL for | |
27824 | unconditional bls. */ | |
27825 | { | |
27826 | newval = md_chars_to_number (buf, INSN_SIZE); | |
27827 | newval = newval | 0x10000000; | |
27828 | md_number_to_chars (buf, newval, INSN_SIZE); | |
27829 | temp = 1; | |
27830 | fixP->fx_done = 1; | |
27831 | } | |
39b41c9c PB |
27832 | else |
27833 | temp = 3; | |
27834 | goto arm_branch_common; | |
27835 | ||
27836 | case BFD_RELOC_ARM_PCREL_JUMP: | |
267bf995 RR |
27837 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
27838 | && fixP->fx_addsy | |
34e77a92 | 27839 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
27840 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
27841 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
27842 | { | |
27843 | /* This would map to a bl<cond>, b<cond>, | |
27844 | b<always> to a Thumb function. We | |
27845 | need to force a relocation for this particular | |
27846 | case. */ | |
27847 | newval = md_chars_to_number (buf, INSN_SIZE); | |
27848 | fixP->fx_done = 0; | |
27849 | } | |
1a0670f3 | 27850 | /* Fall through. */ |
267bf995 | 27851 | |
2fc8bdac | 27852 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 27853 | #endif |
39b41c9c PB |
27854 | case BFD_RELOC_ARM_PCREL_BRANCH: |
27855 | temp = 3; | |
27856 | goto arm_branch_common; | |
a737bd4d | 27857 | |
39b41c9c | 27858 | case BFD_RELOC_ARM_PCREL_BLX: |
267bf995 | 27859 | |
39b41c9c | 27860 | temp = 1; |
267bf995 RR |
27861 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
27862 | && fixP->fx_addsy | |
34e77a92 | 27863 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
27864 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
27865 | && ARM_IS_FUNC (fixP->fx_addsy)) | |
27866 | { | |
27867 | /* Flip the blx to a bl and warn. */ | |
27868 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
27869 | newval = 0xeb000000; | |
27870 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
27871 | _("blx to '%s' an ARM ISA state function changed to bl"), | |
27872 | name); | |
27873 | md_number_to_chars (buf, newval, INSN_SIZE); | |
27874 | temp = 3; | |
27875 | fixP->fx_done = 1; | |
27876 | } | |
27877 | ||
27878 | #ifdef OBJ_ELF | |
27879 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
477330fc | 27880 | fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL; |
267bf995 RR |
27881 | #endif |
27882 | ||
39b41c9c | 27883 | arm_branch_common: |
c19d1205 | 27884 | /* We are going to store value (shifted right by two) in the |
39b41c9c PB |
27885 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
27886 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must | |
de194d85 | 27887 | also be clear. */ |
39b41c9c | 27888 | if (value & temp) |
c19d1205 | 27889 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
27890 | _("misaligned branch destination")); |
27891 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
27892 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
08f10d51 | 27893 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 27894 | |
2fc8bdac | 27895 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 27896 | { |
2fc8bdac ZW |
27897 | newval = md_chars_to_number (buf, INSN_SIZE); |
27898 | newval |= (value >> 2) & 0x00ffffff; | |
7ae2971b PB |
27899 | /* Set the H bit on BLX instructions. */ |
27900 | if (temp == 1) | |
27901 | { | |
27902 | if (value & 2) | |
27903 | newval |= 0x01000000; | |
27904 | else | |
27905 | newval &= ~0x01000000; | |
27906 | } | |
2fc8bdac | 27907 | md_number_to_chars (buf, newval, INSN_SIZE); |
c19d1205 | 27908 | } |
c19d1205 | 27909 | break; |
a737bd4d | 27910 | |
25fe350b MS |
27911 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ |
27912 | /* CBZ can only branch forward. */ | |
a737bd4d | 27913 | |
738755b0 | 27914 | /* Attempts to use CBZ to branch to the next instruction |
477330fc RM |
27915 | (which, strictly speaking, are prohibited) will be turned into |
27916 | no-ops. | |
738755b0 MS |
27917 | |
27918 | FIXME: It may be better to remove the instruction completely and | |
27919 | perform relaxation. */ | |
27920 | if (value == -2) | |
2fc8bdac ZW |
27921 | { |
27922 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
738755b0 | 27923 | newval = 0xbf00; /* NOP encoding T1 */ |
2fc8bdac ZW |
27924 | md_number_to_chars (buf, newval, THUMB_SIZE); |
27925 | } | |
738755b0 MS |
27926 | else |
27927 | { | |
27928 | if (value & ~0x7e) | |
08f10d51 | 27929 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
738755b0 | 27930 | |
477330fc | 27931 | if (fixP->fx_done || !seg->use_rela_p) |
738755b0 MS |
27932 | { |
27933 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
27934 | newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); | |
27935 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
27936 | } | |
27937 | } | |
c19d1205 | 27938 | break; |
a737bd4d | 27939 | |
c19d1205 | 27940 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac | 27941 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
08f10d51 | 27942 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 27943 | |
2fc8bdac ZW |
27944 | if (fixP->fx_done || !seg->use_rela_p) |
27945 | { | |
27946 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
27947 | newval |= (value & 0x1ff) >> 1; | |
27948 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
27949 | } | |
c19d1205 | 27950 | break; |
a737bd4d | 27951 | |
c19d1205 | 27952 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac | 27953 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
08f10d51 | 27954 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 27955 | |
2fc8bdac ZW |
27956 | if (fixP->fx_done || !seg->use_rela_p) |
27957 | { | |
27958 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
27959 | newval |= (value & 0xfff) >> 1; | |
27960 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
27961 | } | |
c19d1205 | 27962 | break; |
a737bd4d | 27963 | |
c19d1205 | 27964 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
267bf995 RR |
27965 | if (fixP->fx_addsy |
27966 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 27967 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
27968 | && ARM_IS_FUNC (fixP->fx_addsy) |
27969 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
27970 | { | |
27971 | /* Force a relocation for a branch 20 bits wide. */ | |
27972 | fixP->fx_done = 0; | |
27973 | } | |
08f10d51 | 27974 | if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff)) |
2fc8bdac ZW |
27975 | as_bad_where (fixP->fx_file, fixP->fx_line, |
27976 | _("conditional branch out of range")); | |
404ff6b5 | 27977 | |
2fc8bdac ZW |
27978 | if (fixP->fx_done || !seg->use_rela_p) |
27979 | { | |
27980 | offsetT newval2; | |
27981 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 27982 | |
2fc8bdac ZW |
27983 | S = (value & 0x00100000) >> 20; |
27984 | J2 = (value & 0x00080000) >> 19; | |
27985 | J1 = (value & 0x00040000) >> 18; | |
27986 | hi = (value & 0x0003f000) >> 12; | |
27987 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 27988 | |
2fc8bdac ZW |
27989 | newval = md_chars_to_number (buf, THUMB_SIZE); |
27990 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
27991 | newval |= (S << 10) | hi; | |
27992 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
27993 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
27994 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
27995 | } | |
c19d1205 | 27996 | break; |
6c43fab6 | 27997 | |
c19d1205 | 27998 | case BFD_RELOC_THUMB_PCREL_BLX: |
267bf995 RR |
27999 | /* If there is a blx from a thumb state function to |
28000 | another thumb function flip this to a bl and warn | |
28001 | about it. */ | |
28002 | ||
28003 | if (fixP->fx_addsy | |
34e77a92 | 28004 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
28005 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
28006 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
28007 | { | |
28008 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
28009 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
28010 | _("blx to Thumb func '%s' from Thumb ISA state changed to bl"), | |
28011 | name); | |
28012 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
28013 | newval = newval | 0x1000; | |
28014 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
28015 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
28016 | fixP->fx_done = 1; | |
28017 | } | |
28018 | ||
28019 | ||
28020 | goto thumb_bl_common; | |
28021 | ||
c19d1205 | 28022 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
267bf995 RR |
28023 | /* A bl from Thumb state ISA to an internal ARM state function |
28024 | is converted to a blx. */ | |
28025 | if (fixP->fx_addsy | |
28026 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 28027 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
28028 | && ARM_IS_FUNC (fixP->fx_addsy) |
28029 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
28030 | { | |
28031 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
28032 | newval = newval & ~0x1000; | |
28033 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
28034 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX; | |
28035 | fixP->fx_done = 1; | |
28036 | } | |
28037 | ||
28038 | thumb_bl_common: | |
28039 | ||
2fc8bdac ZW |
28040 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
28041 | /* For a BLX instruction, make sure that the relocation is rounded up | |
28042 | to a word boundary. This follows the semantics of the instruction | |
28043 | which specifies that bit 1 of the target address will come from bit | |
28044 | 1 of the base address. */ | |
d406f3e4 JB |
28045 | value = (value + 3) & ~ 3; |
28046 | ||
28047 | #ifdef OBJ_ELF | |
28048 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 | |
28049 | && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) | |
28050 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
28051 | #endif | |
404ff6b5 | 28052 | |
2b2f5df9 NC |
28053 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
28054 | { | |
fc289b0a | 28055 | if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))) |
2b2f5df9 NC |
28056 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
28057 | else if ((value & ~0x1ffffff) | |
28058 | && ((value & ~0x1ffffff) != ~0x1ffffff)) | |
28059 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28060 | _("Thumb2 branch out of range")); | |
28061 | } | |
4a42ebbc RR |
28062 | |
28063 | if (fixP->fx_done || !seg->use_rela_p) | |
28064 | encode_thumb2_b_bl_offset (buf, value); | |
28065 | ||
c19d1205 | 28066 | break; |
404ff6b5 | 28067 | |
c19d1205 | 28068 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
08f10d51 NC |
28069 | if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff)) |
28070 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); | |
6c43fab6 | 28071 | |
2fc8bdac | 28072 | if (fixP->fx_done || !seg->use_rela_p) |
4a42ebbc | 28073 | encode_thumb2_b_bl_offset (buf, value); |
6c43fab6 | 28074 | |
2fc8bdac | 28075 | break; |
a737bd4d | 28076 | |
2fc8bdac ZW |
28077 | case BFD_RELOC_8: |
28078 | if (fixP->fx_done || !seg->use_rela_p) | |
4b1a927e | 28079 | *buf = value; |
c19d1205 | 28080 | break; |
a737bd4d | 28081 | |
c19d1205 | 28082 | case BFD_RELOC_16: |
2fc8bdac | 28083 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 28084 | md_number_to_chars (buf, value, 2); |
c19d1205 | 28085 | break; |
a737bd4d | 28086 | |
c19d1205 | 28087 | #ifdef OBJ_ELF |
0855e32b NS |
28088 | case BFD_RELOC_ARM_TLS_CALL: |
28089 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
28090 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
28091 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
0855e32b | 28092 | case BFD_RELOC_ARM_TLS_GOTDESC: |
c19d1205 ZW |
28093 | case BFD_RELOC_ARM_TLS_GD32: |
28094 | case BFD_RELOC_ARM_TLS_LE32: | |
28095 | case BFD_RELOC_ARM_TLS_IE32: | |
28096 | case BFD_RELOC_ARM_TLS_LDM32: | |
28097 | case BFD_RELOC_ARM_TLS_LDO32: | |
28098 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
4b1a927e | 28099 | break; |
6c43fab6 | 28100 | |
5c5a4843 CL |
28101 | /* Same handling as above, but with the arm_fdpic guard. */ |
28102 | case BFD_RELOC_ARM_TLS_GD32_FDPIC: | |
28103 | case BFD_RELOC_ARM_TLS_IE32_FDPIC: | |
28104 | case BFD_RELOC_ARM_TLS_LDM32_FDPIC: | |
28105 | if (arm_fdpic) | |
28106 | { | |
28107 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
28108 | } | |
28109 | else | |
28110 | { | |
28111 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28112 | _("Relocation supported only in FDPIC mode")); | |
28113 | } | |
28114 | break; | |
28115 | ||
c19d1205 ZW |
28116 | case BFD_RELOC_ARM_GOT32: |
28117 | case BFD_RELOC_ARM_GOTOFF: | |
c19d1205 | 28118 | break; |
b43420e6 NC |
28119 | |
28120 | case BFD_RELOC_ARM_GOT_PREL: | |
28121 | if (fixP->fx_done || !seg->use_rela_p) | |
477330fc | 28122 | md_number_to_chars (buf, value, 4); |
b43420e6 NC |
28123 | break; |
28124 | ||
9a6f4e97 NS |
28125 | case BFD_RELOC_ARM_TARGET2: |
28126 | /* TARGET2 is not partial-inplace, so we need to write the | |
477330fc RM |
28127 | addend here for REL targets, because it won't be written out |
28128 | during reloc processing later. */ | |
9a6f4e97 NS |
28129 | if (fixP->fx_done || !seg->use_rela_p) |
28130 | md_number_to_chars (buf, fixP->fx_offset, 4); | |
28131 | break; | |
188fd7ae CL |
28132 | |
28133 | /* Relocations for FDPIC. */ | |
28134 | case BFD_RELOC_ARM_GOTFUNCDESC: | |
28135 | case BFD_RELOC_ARM_GOTOFFFUNCDESC: | |
28136 | case BFD_RELOC_ARM_FUNCDESC: | |
28137 | if (arm_fdpic) | |
28138 | { | |
28139 | if (fixP->fx_done || !seg->use_rela_p) | |
28140 | md_number_to_chars (buf, 0, 4); | |
28141 | } | |
28142 | else | |
28143 | { | |
28144 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28145 | _("Relocation supported only in FDPIC mode")); | |
28146 | } | |
28147 | break; | |
c19d1205 | 28148 | #endif |
6c43fab6 | 28149 | |
c19d1205 ZW |
28150 | case BFD_RELOC_RVA: |
28151 | case BFD_RELOC_32: | |
28152 | case BFD_RELOC_ARM_TARGET1: | |
28153 | case BFD_RELOC_ARM_ROSEGREL32: | |
28154 | case BFD_RELOC_ARM_SBREL32: | |
28155 | case BFD_RELOC_32_PCREL: | |
f0927246 NC |
28156 | #ifdef TE_PE |
28157 | case BFD_RELOC_32_SECREL: | |
28158 | #endif | |
2fc8bdac | 28159 | if (fixP->fx_done || !seg->use_rela_p) |
53baae48 NC |
28160 | #ifdef TE_WINCE |
28161 | /* For WinCE we only do this for pcrel fixups. */ | |
28162 | if (fixP->fx_done || fixP->fx_pcrel) | |
28163 | #endif | |
28164 | md_number_to_chars (buf, value, 4); | |
c19d1205 | 28165 | break; |
6c43fab6 | 28166 | |
c19d1205 ZW |
28167 | #ifdef OBJ_ELF |
28168 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 28169 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
28170 | { |
28171 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
28172 | if ((value ^ (value >> 1)) & 0x40000000) | |
28173 | { | |
28174 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28175 | _("rel31 relocation overflow")); | |
28176 | } | |
28177 | newval |= value & 0x7fffffff; | |
28178 | md_number_to_chars (buf, newval, 4); | |
28179 | } | |
28180 | break; | |
c19d1205 | 28181 | #endif |
a737bd4d | 28182 | |
c19d1205 | 28183 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 28184 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
32c36c3c | 28185 | case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM: |
9db2f6b4 RL |
28186 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM) |
28187 | newval = md_chars_to_number (buf, INSN_SIZE); | |
28188 | else | |
28189 | newval = get_thumb32_insn (buf); | |
28190 | if ((newval & 0x0f200f00) == 0x0d000900) | |
28191 | { | |
28192 | /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic | |
28193 | has permitted values that are multiples of 2, in the range 0 | |
28194 | to 510. */ | |
28195 | if (value < -510 || value > 510 || (value & 1)) | |
28196 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28197 | _("co-processor offset out of range")); | |
28198 | } | |
32c36c3c AV |
28199 | else if ((newval & 0xfe001f80) == 0xec000f80) |
28200 | { | |
28201 | if (value < -511 || value > 512 || (value & 3)) | |
28202 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28203 | _("co-processor offset out of range")); | |
28204 | } | |
9db2f6b4 | 28205 | else if (value < -1023 || value > 1023 || (value & 3)) |
c19d1205 ZW |
28206 | as_bad_where (fixP->fx_file, fixP->fx_line, |
28207 | _("co-processor offset out of range")); | |
28208 | cp_off_common: | |
26d97720 | 28209 | sign = value > 0; |
c19d1205 ZW |
28210 | if (value < 0) |
28211 | value = -value; | |
8f06b2d8 PB |
28212 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
28213 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
28214 | newval = md_chars_to_number (buf, INSN_SIZE); | |
28215 | else | |
28216 | newval = get_thumb32_insn (buf); | |
26d97720 | 28217 | if (value == 0) |
32c36c3c AV |
28218 | { |
28219 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM) | |
28220 | newval &= 0xffffff80; | |
28221 | else | |
28222 | newval &= 0xffffff00; | |
28223 | } | |
26d97720 NS |
28224 | else |
28225 | { | |
32c36c3c AV |
28226 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM) |
28227 | newval &= 0xff7fff80; | |
28228 | else | |
28229 | newval &= 0xff7fff00; | |
9db2f6b4 RL |
28230 | if ((newval & 0x0f200f00) == 0x0d000900) |
28231 | { | |
28232 | /* This is a fp16 vstr/vldr. | |
28233 | ||
28234 | It requires the immediate offset in the instruction is shifted | |
28235 | left by 1 to be a half-word offset. | |
28236 | ||
28237 | Here, left shift by 1 first, and later right shift by 2 | |
28238 | should get the right offset. */ | |
28239 | value <<= 1; | |
28240 | } | |
26d97720 NS |
28241 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); |
28242 | } | |
8f06b2d8 PB |
28243 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
28244 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
28245 | md_number_to_chars (buf, newval, INSN_SIZE); | |
28246 | else | |
28247 | put_thumb32_insn (buf, newval); | |
c19d1205 | 28248 | break; |
a737bd4d | 28249 | |
c19d1205 | 28250 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 28251 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
28252 | if (value < -255 || value > 255) |
28253 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28254 | _("co-processor offset out of range")); | |
df7849c5 | 28255 | value *= 4; |
c19d1205 | 28256 | goto cp_off_common; |
6c43fab6 | 28257 | |
c19d1205 ZW |
28258 | case BFD_RELOC_ARM_THUMB_OFFSET: |
28259 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
28260 | /* Exactly what ranges, and where the offset is inserted depends | |
28261 | on the type of instruction, we can establish this from the | |
28262 | top 4 bits. */ | |
28263 | switch (newval >> 12) | |
28264 | { | |
28265 | case 4: /* PC load. */ | |
28266 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
28267 | forced to zero for these loads; md_pcrel_from has already | |
28268 | compensated for this. */ | |
28269 | if (value & 3) | |
28270 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28271 | _("invalid offset, target not word aligned (0x%08lX)"), | |
0359e808 NC |
28272 | (((unsigned long) fixP->fx_frag->fr_address |
28273 | + (unsigned long) fixP->fx_where) & ~3) | |
28274 | + (unsigned long) value); | |
a737bd4d | 28275 | |
c19d1205 ZW |
28276 | if (value & ~0x3fc) |
28277 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28278 | _("invalid offset, value too big (0x%08lX)"), | |
28279 | (long) value); | |
a737bd4d | 28280 | |
c19d1205 ZW |
28281 | newval |= value >> 2; |
28282 | break; | |
a737bd4d | 28283 | |
c19d1205 ZW |
28284 | case 9: /* SP load/store. */ |
28285 | if (value & ~0x3fc) | |
28286 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28287 | _("invalid offset, value too big (0x%08lX)"), | |
28288 | (long) value); | |
28289 | newval |= value >> 2; | |
28290 | break; | |
6c43fab6 | 28291 | |
c19d1205 ZW |
28292 | case 6: /* Word load/store. */ |
28293 | if (value & ~0x7c) | |
28294 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28295 | _("invalid offset, value too big (0x%08lX)"), | |
28296 | (long) value); | |
28297 | newval |= value << 4; /* 6 - 2. */ | |
28298 | break; | |
a737bd4d | 28299 | |
c19d1205 ZW |
28300 | case 7: /* Byte load/store. */ |
28301 | if (value & ~0x1f) | |
28302 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28303 | _("invalid offset, value too big (0x%08lX)"), | |
28304 | (long) value); | |
28305 | newval |= value << 6; | |
28306 | break; | |
a737bd4d | 28307 | |
c19d1205 ZW |
28308 | case 8: /* Halfword load/store. */ |
28309 | if (value & ~0x3e) | |
28310 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28311 | _("invalid offset, value too big (0x%08lX)"), | |
28312 | (long) value); | |
28313 | newval |= value << 5; /* 6 - 1. */ | |
28314 | break; | |
a737bd4d | 28315 | |
c19d1205 ZW |
28316 | default: |
28317 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28318 | "Unable to process relocation for thumb opcode: %lx", | |
28319 | (unsigned long) newval); | |
28320 | break; | |
28321 | } | |
28322 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28323 | break; | |
a737bd4d | 28324 | |
c19d1205 ZW |
28325 | case BFD_RELOC_ARM_THUMB_ADD: |
28326 | /* This is a complicated relocation, since we use it for all of | |
28327 | the following immediate relocations: | |
a737bd4d | 28328 | |
c19d1205 ZW |
28329 | 3bit ADD/SUB |
28330 | 8bit ADD/SUB | |
28331 | 9bit ADD/SUB SP word-aligned | |
28332 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 28333 | |
c19d1205 ZW |
28334 | The type of instruction being processed is encoded in the |
28335 | instruction field: | |
a737bd4d | 28336 | |
c19d1205 ZW |
28337 | 0x8000 SUB |
28338 | 0x00F0 Rd | |
28339 | 0x000F Rs | |
28340 | */ | |
28341 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
28342 | { | |
28343 | int rd = (newval >> 4) & 0xf; | |
28344 | int rs = newval & 0xf; | |
28345 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 28346 | |
c19d1205 ZW |
28347 | /* Check for HI regs, only very restricted cases allowed: |
28348 | Adjusting SP, and using PC or SP to get an address. */ | |
28349 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
28350 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
28351 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28352 | _("invalid Hi register with immediate")); | |
a737bd4d | 28353 | |
c19d1205 ZW |
28354 | /* If value is negative, choose the opposite instruction. */ |
28355 | if (value < 0) | |
28356 | { | |
28357 | value = -value; | |
28358 | subtract = !subtract; | |
28359 | if (value < 0) | |
28360 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28361 | _("immediate value out of range")); | |
28362 | } | |
a737bd4d | 28363 | |
c19d1205 ZW |
28364 | if (rd == REG_SP) |
28365 | { | |
75c11999 | 28366 | if (value & ~0x1fc) |
c19d1205 ZW |
28367 | as_bad_where (fixP->fx_file, fixP->fx_line, |
28368 | _("invalid immediate for stack address calculation")); | |
28369 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
28370 | newval |= value >> 2; | |
28371 | } | |
28372 | else if (rs == REG_PC || rs == REG_SP) | |
28373 | { | |
c12d2c9d NC |
28374 | /* PR gas/18541. If the addition is for a defined symbol |
28375 | within range of an ADR instruction then accept it. */ | |
28376 | if (subtract | |
28377 | && value == 4 | |
28378 | && fixP->fx_addsy != NULL) | |
28379 | { | |
28380 | subtract = 0; | |
28381 | ||
28382 | if (! S_IS_DEFINED (fixP->fx_addsy) | |
28383 | || S_GET_SEGMENT (fixP->fx_addsy) != seg | |
28384 | || S_IS_WEAK (fixP->fx_addsy)) | |
28385 | { | |
28386 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28387 | _("address calculation needs a strongly defined nearby symbol")); | |
28388 | } | |
28389 | else | |
28390 | { | |
28391 | offsetT v = fixP->fx_where + fixP->fx_frag->fr_address; | |
28392 | ||
28393 | /* Round up to the next 4-byte boundary. */ | |
28394 | if (v & 3) | |
28395 | v = (v + 3) & ~ 3; | |
28396 | else | |
28397 | v += 4; | |
28398 | v = S_GET_VALUE (fixP->fx_addsy) - v; | |
28399 | ||
28400 | if (v & ~0x3fc) | |
28401 | { | |
28402 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28403 | _("symbol too far away")); | |
28404 | } | |
28405 | else | |
28406 | { | |
28407 | fixP->fx_done = 1; | |
28408 | value = v; | |
28409 | } | |
28410 | } | |
28411 | } | |
28412 | ||
c19d1205 ZW |
28413 | if (subtract || value & ~0x3fc) |
28414 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28415 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
5fc177c8 | 28416 | (unsigned long) (subtract ? - value : value)); |
c19d1205 ZW |
28417 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); |
28418 | newval |= rd << 8; | |
28419 | newval |= value >> 2; | |
28420 | } | |
28421 | else if (rs == rd) | |
28422 | { | |
28423 | if (value & ~0xff) | |
28424 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28425 | _("immediate value out of range")); | |
28426 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
28427 | newval |= (rd << 8) | value; | |
28428 | } | |
28429 | else | |
28430 | { | |
28431 | if (value & ~0x7) | |
28432 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28433 | _("immediate value out of range")); | |
28434 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
28435 | newval |= rd | (rs << 3) | (value << 6); | |
28436 | } | |
28437 | } | |
28438 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28439 | break; | |
a737bd4d | 28440 | |
c19d1205 ZW |
28441 | case BFD_RELOC_ARM_THUMB_IMM: |
28442 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
28443 | if (value < 0 || value > 255) | |
28444 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
4e6e072b | 28445 | _("invalid immediate: %ld is out of range"), |
c19d1205 ZW |
28446 | (long) value); |
28447 | newval |= value; | |
28448 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28449 | break; | |
a737bd4d | 28450 | |
c19d1205 ZW |
28451 | case BFD_RELOC_ARM_THUMB_SHIFT: |
28452 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
28453 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
28454 | temp = newval & 0xf800; | |
28455 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
28456 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28457 | _("invalid shift value: %ld"), (long) value); | |
28458 | /* Shifts of zero must be encoded as LSL. */ | |
28459 | if (value == 0) | |
28460 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
28461 | /* Shifts of 32 are encoded as zero. */ | |
28462 | else if (value == 32) | |
28463 | value = 0; | |
28464 | newval |= value << 6; | |
28465 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28466 | break; | |
a737bd4d | 28467 | |
c19d1205 ZW |
28468 | case BFD_RELOC_VTABLE_INHERIT: |
28469 | case BFD_RELOC_VTABLE_ENTRY: | |
28470 | fixP->fx_done = 0; | |
28471 | return; | |
6c43fab6 | 28472 | |
b6895b4f PB |
28473 | case BFD_RELOC_ARM_MOVW: |
28474 | case BFD_RELOC_ARM_MOVT: | |
28475 | case BFD_RELOC_ARM_THUMB_MOVW: | |
28476 | case BFD_RELOC_ARM_THUMB_MOVT: | |
28477 | if (fixP->fx_done || !seg->use_rela_p) | |
28478 | { | |
28479 | /* REL format relocations are limited to a 16-bit addend. */ | |
28480 | if (!fixP->fx_done) | |
28481 | { | |
39623e12 | 28482 | if (value < -0x8000 || value > 0x7fff) |
b6895b4f | 28483 | as_bad_where (fixP->fx_file, fixP->fx_line, |
ff5075ca | 28484 | _("offset out of range")); |
b6895b4f PB |
28485 | } |
28486 | else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
28487 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
28488 | { | |
28489 | value >>= 16; | |
28490 | } | |
28491 | ||
28492 | if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
28493 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
28494 | { | |
28495 | newval = get_thumb32_insn (buf); | |
28496 | newval &= 0xfbf08f00; | |
28497 | newval |= (value & 0xf000) << 4; | |
28498 | newval |= (value & 0x0800) << 15; | |
28499 | newval |= (value & 0x0700) << 4; | |
28500 | newval |= (value & 0x00ff); | |
28501 | put_thumb32_insn (buf, newval); | |
28502 | } | |
28503 | else | |
28504 | { | |
28505 | newval = md_chars_to_number (buf, 4); | |
28506 | newval &= 0xfff0f000; | |
28507 | newval |= value & 0x0fff; | |
28508 | newval |= (value & 0xf000) << 4; | |
28509 | md_number_to_chars (buf, newval, 4); | |
28510 | } | |
28511 | } | |
28512 | return; | |
28513 | ||
72d98d16 MG |
28514 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC: |
28515 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC: | |
28516 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC: | |
28517 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC: | |
28518 | gas_assert (!fixP->fx_done); | |
28519 | { | |
28520 | bfd_vma insn; | |
28521 | bfd_boolean is_mov; | |
28522 | bfd_vma encoded_addend = value; | |
28523 | ||
28524 | /* Check that addend can be encoded in instruction. */ | |
28525 | if (!seg->use_rela_p && (value < 0 || value > 255)) | |
28526 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28527 | _("the offset 0x%08lX is not representable"), | |
28528 | (unsigned long) encoded_addend); | |
28529 | ||
28530 | /* Extract the instruction. */ | |
28531 | insn = md_chars_to_number (buf, THUMB_SIZE); | |
28532 | is_mov = (insn & 0xf800) == 0x2000; | |
28533 | ||
28534 | /* Encode insn. */ | |
28535 | if (is_mov) | |
28536 | { | |
28537 | if (!seg->use_rela_p) | |
28538 | insn |= encoded_addend; | |
28539 | } | |
28540 | else | |
28541 | { | |
28542 | int rd, rs; | |
28543 | ||
28544 | /* Extract the instruction. */ | |
28545 | /* Encoding is the following | |
28546 | 0x8000 SUB | |
28547 | 0x00F0 Rd | |
28548 | 0x000F Rs | |
28549 | */ | |
28550 | /* The following conditions must be true : | |
28551 | - ADD | |
28552 | - Rd == Rs | |
28553 | - Rd <= 7 | |
28554 | */ | |
28555 | rd = (insn >> 4) & 0xf; | |
28556 | rs = insn & 0xf; | |
28557 | if ((insn & 0x8000) || (rd != rs) || rd > 7) | |
28558 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28559 | _("Unable to process relocation for thumb opcode: %lx"), | |
28560 | (unsigned long) insn); | |
28561 | ||
28562 | /* Encode as ADD immediate8 thumb 1 code. */ | |
28563 | insn = 0x3000 | (rd << 8); | |
28564 | ||
28565 | /* Place the encoded addend into the first 8 bits of the | |
28566 | instruction. */ | |
28567 | if (!seg->use_rela_p) | |
28568 | insn |= encoded_addend; | |
28569 | } | |
28570 | ||
28571 | /* Update the instruction. */ | |
28572 | md_number_to_chars (buf, insn, THUMB_SIZE); | |
28573 | } | |
28574 | break; | |
28575 | ||
4962c51a MS |
28576 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
28577 | case BFD_RELOC_ARM_ALU_PC_G0: | |
28578 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
28579 | case BFD_RELOC_ARM_ALU_PC_G1: | |
28580 | case BFD_RELOC_ARM_ALU_PC_G2: | |
28581 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
28582 | case BFD_RELOC_ARM_ALU_SB_G0: | |
28583 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
28584 | case BFD_RELOC_ARM_ALU_SB_G1: | |
28585 | case BFD_RELOC_ARM_ALU_SB_G2: | |
9c2799c2 | 28586 | gas_assert (!fixP->fx_done); |
4962c51a MS |
28587 | if (!seg->use_rela_p) |
28588 | { | |
477330fc RM |
28589 | bfd_vma insn; |
28590 | bfd_vma encoded_addend; | |
3ca4a8ec | 28591 | bfd_vma addend_abs = llabs (value); |
477330fc RM |
28592 | |
28593 | /* Check that the absolute value of the addend can be | |
28594 | expressed as an 8-bit constant plus a rotation. */ | |
28595 | encoded_addend = encode_arm_immediate (addend_abs); | |
28596 | if (encoded_addend == (unsigned int) FAIL) | |
4962c51a | 28597 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
28598 | _("the offset 0x%08lX is not representable"), |
28599 | (unsigned long) addend_abs); | |
28600 | ||
28601 | /* Extract the instruction. */ | |
28602 | insn = md_chars_to_number (buf, INSN_SIZE); | |
28603 | ||
28604 | /* If the addend is positive, use an ADD instruction. | |
28605 | Otherwise use a SUB. Take care not to destroy the S bit. */ | |
28606 | insn &= 0xff1fffff; | |
28607 | if (value < 0) | |
28608 | insn |= 1 << 22; | |
28609 | else | |
28610 | insn |= 1 << 23; | |
28611 | ||
28612 | /* Place the encoded addend into the first 12 bits of the | |
28613 | instruction. */ | |
28614 | insn &= 0xfffff000; | |
28615 | insn |= encoded_addend; | |
28616 | ||
28617 | /* Update the instruction. */ | |
28618 | md_number_to_chars (buf, insn, INSN_SIZE); | |
4962c51a MS |
28619 | } |
28620 | break; | |
28621 | ||
28622 | case BFD_RELOC_ARM_LDR_PC_G0: | |
28623 | case BFD_RELOC_ARM_LDR_PC_G1: | |
28624 | case BFD_RELOC_ARM_LDR_PC_G2: | |
28625 | case BFD_RELOC_ARM_LDR_SB_G0: | |
28626 | case BFD_RELOC_ARM_LDR_SB_G1: | |
28627 | case BFD_RELOC_ARM_LDR_SB_G2: | |
9c2799c2 | 28628 | gas_assert (!fixP->fx_done); |
4962c51a | 28629 | if (!seg->use_rela_p) |
477330fc RM |
28630 | { |
28631 | bfd_vma insn; | |
3ca4a8ec | 28632 | bfd_vma addend_abs = llabs (value); |
4962c51a | 28633 | |
477330fc RM |
28634 | /* Check that the absolute value of the addend can be |
28635 | encoded in 12 bits. */ | |
28636 | if (addend_abs >= 0x1000) | |
4962c51a | 28637 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
28638 | _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), |
28639 | (unsigned long) addend_abs); | |
28640 | ||
28641 | /* Extract the instruction. */ | |
28642 | insn = md_chars_to_number (buf, INSN_SIZE); | |
28643 | ||
28644 | /* If the addend is negative, clear bit 23 of the instruction. | |
28645 | Otherwise set it. */ | |
28646 | if (value < 0) | |
28647 | insn &= ~(1 << 23); | |
28648 | else | |
28649 | insn |= 1 << 23; | |
28650 | ||
28651 | /* Place the absolute value of the addend into the first 12 bits | |
28652 | of the instruction. */ | |
28653 | insn &= 0xfffff000; | |
28654 | insn |= addend_abs; | |
28655 | ||
28656 | /* Update the instruction. */ | |
28657 | md_number_to_chars (buf, insn, INSN_SIZE); | |
28658 | } | |
4962c51a MS |
28659 | break; |
28660 | ||
28661 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
28662 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
28663 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
28664 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
28665 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
28666 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
9c2799c2 | 28667 | gas_assert (!fixP->fx_done); |
4962c51a | 28668 | if (!seg->use_rela_p) |
477330fc RM |
28669 | { |
28670 | bfd_vma insn; | |
3ca4a8ec | 28671 | bfd_vma addend_abs = llabs (value); |
4962c51a | 28672 | |
477330fc RM |
28673 | /* Check that the absolute value of the addend can be |
28674 | encoded in 8 bits. */ | |
28675 | if (addend_abs >= 0x100) | |
4962c51a | 28676 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
28677 | _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), |
28678 | (unsigned long) addend_abs); | |
28679 | ||
28680 | /* Extract the instruction. */ | |
28681 | insn = md_chars_to_number (buf, INSN_SIZE); | |
28682 | ||
28683 | /* If the addend is negative, clear bit 23 of the instruction. | |
28684 | Otherwise set it. */ | |
28685 | if (value < 0) | |
28686 | insn &= ~(1 << 23); | |
28687 | else | |
28688 | insn |= 1 << 23; | |
28689 | ||
28690 | /* Place the first four bits of the absolute value of the addend | |
28691 | into the first 4 bits of the instruction, and the remaining | |
28692 | four into bits 8 .. 11. */ | |
28693 | insn &= 0xfffff0f0; | |
28694 | insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); | |
28695 | ||
28696 | /* Update the instruction. */ | |
28697 | md_number_to_chars (buf, insn, INSN_SIZE); | |
28698 | } | |
4962c51a MS |
28699 | break; |
28700 | ||
28701 | case BFD_RELOC_ARM_LDC_PC_G0: | |
28702 | case BFD_RELOC_ARM_LDC_PC_G1: | |
28703 | case BFD_RELOC_ARM_LDC_PC_G2: | |
28704 | case BFD_RELOC_ARM_LDC_SB_G0: | |
28705 | case BFD_RELOC_ARM_LDC_SB_G1: | |
28706 | case BFD_RELOC_ARM_LDC_SB_G2: | |
9c2799c2 | 28707 | gas_assert (!fixP->fx_done); |
4962c51a | 28708 | if (!seg->use_rela_p) |
477330fc RM |
28709 | { |
28710 | bfd_vma insn; | |
3ca4a8ec | 28711 | bfd_vma addend_abs = llabs (value); |
4962c51a | 28712 | |
477330fc RM |
28713 | /* Check that the absolute value of the addend is a multiple of |
28714 | four and, when divided by four, fits in 8 bits. */ | |
28715 | if (addend_abs & 0x3) | |
4962c51a | 28716 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
28717 | _("bad offset 0x%08lX (must be word-aligned)"), |
28718 | (unsigned long) addend_abs); | |
4962c51a | 28719 | |
477330fc | 28720 | if ((addend_abs >> 2) > 0xff) |
4962c51a | 28721 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
28722 | _("bad offset 0x%08lX (must be an 8-bit number of words)"), |
28723 | (unsigned long) addend_abs); | |
28724 | ||
28725 | /* Extract the instruction. */ | |
28726 | insn = md_chars_to_number (buf, INSN_SIZE); | |
28727 | ||
28728 | /* If the addend is negative, clear bit 23 of the instruction. | |
28729 | Otherwise set it. */ | |
28730 | if (value < 0) | |
28731 | insn &= ~(1 << 23); | |
28732 | else | |
28733 | insn |= 1 << 23; | |
28734 | ||
28735 | /* Place the addend (divided by four) into the first eight | |
28736 | bits of the instruction. */ | |
28737 | insn &= 0xfffffff0; | |
28738 | insn |= addend_abs >> 2; | |
28739 | ||
28740 | /* Update the instruction. */ | |
28741 | md_number_to_chars (buf, insn, INSN_SIZE); | |
28742 | } | |
4962c51a MS |
28743 | break; |
28744 | ||
e12437dc AV |
28745 | case BFD_RELOC_THUMB_PCREL_BRANCH5: |
28746 | if (fixP->fx_addsy | |
28747 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
28748 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
28749 | && ARM_IS_FUNC (fixP->fx_addsy) | |
28750 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) | |
28751 | { | |
28752 | /* Force a relocation for a branch 5 bits wide. */ | |
28753 | fixP->fx_done = 0; | |
28754 | } | |
28755 | if (v8_1_branch_value_check (value, 5, FALSE) == FAIL) | |
28756 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28757 | BAD_BRANCH_OFF); | |
28758 | ||
28759 | if (fixP->fx_done || !seg->use_rela_p) | |
28760 | { | |
28761 | addressT boff = value >> 1; | |
28762 | ||
28763 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
28764 | newval |= (boff << 7); | |
28765 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28766 | } | |
28767 | break; | |
28768 | ||
f6b2b12d AV |
28769 | case BFD_RELOC_THUMB_PCREL_BFCSEL: |
28770 | if (fixP->fx_addsy | |
28771 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
28772 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
28773 | && ARM_IS_FUNC (fixP->fx_addsy) | |
28774 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) | |
28775 | { | |
28776 | fixP->fx_done = 0; | |
28777 | } | |
28778 | if ((value & ~0x7f) && ((value & ~0x3f) != ~0x3f)) | |
28779 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28780 | _("branch out of range")); | |
28781 | ||
28782 | if (fixP->fx_done || !seg->use_rela_p) | |
28783 | { | |
28784 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
28785 | ||
28786 | addressT boff = ((newval & 0x0780) >> 7) << 1; | |
28787 | addressT diff = value - boff; | |
28788 | ||
28789 | if (diff == 4) | |
28790 | { | |
28791 | newval |= 1 << 1; /* T bit. */ | |
28792 | } | |
28793 | else if (diff != 2) | |
28794 | { | |
28795 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28796 | _("out of range label-relative fixup value")); | |
28797 | } | |
28798 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28799 | } | |
28800 | break; | |
28801 | ||
e5d6e09e AV |
28802 | case BFD_RELOC_ARM_THUMB_BF17: |
28803 | if (fixP->fx_addsy | |
28804 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
28805 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
28806 | && ARM_IS_FUNC (fixP->fx_addsy) | |
28807 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) | |
28808 | { | |
28809 | /* Force a relocation for a branch 17 bits wide. */ | |
28810 | fixP->fx_done = 0; | |
28811 | } | |
28812 | ||
28813 | if (v8_1_branch_value_check (value, 17, TRUE) == FAIL) | |
28814 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28815 | BAD_BRANCH_OFF); | |
28816 | ||
28817 | if (fixP->fx_done || !seg->use_rela_p) | |
28818 | { | |
28819 | offsetT newval2; | |
28820 | addressT immA, immB, immC; | |
28821 | ||
28822 | immA = (value & 0x0001f000) >> 12; | |
28823 | immB = (value & 0x00000ffc) >> 2; | |
28824 | immC = (value & 0x00000002) >> 1; | |
28825 | ||
28826 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
28827 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
28828 | newval |= immA; | |
28829 | newval2 |= (immC << 11) | (immB << 1); | |
28830 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28831 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
28832 | } | |
28833 | break; | |
28834 | ||
1caf72a5 AV |
28835 | case BFD_RELOC_ARM_THUMB_BF19: |
28836 | if (fixP->fx_addsy | |
28837 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
28838 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
28839 | && ARM_IS_FUNC (fixP->fx_addsy) | |
28840 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) | |
28841 | { | |
28842 | /* Force a relocation for a branch 19 bits wide. */ | |
28843 | fixP->fx_done = 0; | |
28844 | } | |
28845 | ||
28846 | if (v8_1_branch_value_check (value, 19, TRUE) == FAIL) | |
28847 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28848 | BAD_BRANCH_OFF); | |
28849 | ||
28850 | if (fixP->fx_done || !seg->use_rela_p) | |
28851 | { | |
28852 | offsetT newval2; | |
28853 | addressT immA, immB, immC; | |
28854 | ||
28855 | immA = (value & 0x0007f000) >> 12; | |
28856 | immB = (value & 0x00000ffc) >> 2; | |
28857 | immC = (value & 0x00000002) >> 1; | |
28858 | ||
28859 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
28860 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
28861 | newval |= immA; | |
28862 | newval2 |= (immC << 11) | (immB << 1); | |
28863 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28864 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
28865 | } | |
28866 | break; | |
28867 | ||
1889da70 AV |
28868 | case BFD_RELOC_ARM_THUMB_BF13: |
28869 | if (fixP->fx_addsy | |
28870 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
28871 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
28872 | && ARM_IS_FUNC (fixP->fx_addsy) | |
28873 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) | |
28874 | { | |
28875 | /* Force a relocation for a branch 13 bits wide. */ | |
28876 | fixP->fx_done = 0; | |
28877 | } | |
28878 | ||
28879 | if (v8_1_branch_value_check (value, 13, TRUE) == FAIL) | |
28880 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28881 | BAD_BRANCH_OFF); | |
28882 | ||
28883 | if (fixP->fx_done || !seg->use_rela_p) | |
28884 | { | |
28885 | offsetT newval2; | |
28886 | addressT immA, immB, immC; | |
28887 | ||
28888 | immA = (value & 0x00001000) >> 12; | |
28889 | immB = (value & 0x00000ffc) >> 2; | |
28890 | immC = (value & 0x00000002) >> 1; | |
28891 | ||
28892 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
28893 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
28894 | newval |= immA; | |
28895 | newval2 |= (immC << 11) | (immB << 1); | |
28896 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28897 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
28898 | } | |
28899 | break; | |
28900 | ||
60f993ce AV |
28901 | case BFD_RELOC_ARM_THUMB_LOOP12: |
28902 | if (fixP->fx_addsy | |
28903 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
28904 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
28905 | && ARM_IS_FUNC (fixP->fx_addsy) | |
28906 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) | |
28907 | { | |
28908 | /* Force a relocation for a branch 12 bits wide. */ | |
28909 | fixP->fx_done = 0; | |
28910 | } | |
28911 | ||
28912 | bfd_vma insn = get_thumb32_insn (buf); | |
1f6234a3 | 28913 | /* le lr, <label>, le <label> or letp lr, <label> */ |
60f993ce | 28914 | if (((insn & 0xffffffff) == 0xf00fc001) |
1f6234a3 AV |
28915 | || ((insn & 0xffffffff) == 0xf02fc001) |
28916 | || ((insn & 0xffffffff) == 0xf01fc001)) | |
60f993ce AV |
28917 | value = -value; |
28918 | ||
28919 | if (v8_1_branch_value_check (value, 12, FALSE) == FAIL) | |
28920 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28921 | BAD_BRANCH_OFF); | |
28922 | if (fixP->fx_done || !seg->use_rela_p) | |
28923 | { | |
28924 | addressT imml, immh; | |
28925 | ||
28926 | immh = (value & 0x00000ffc) >> 2; | |
28927 | imml = (value & 0x00000002) >> 1; | |
28928 | ||
28929 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
28930 | newval |= (imml << 11) | (immh << 1); | |
28931 | md_number_to_chars (buf + THUMB_SIZE, newval, THUMB_SIZE); | |
28932 | } | |
28933 | break; | |
28934 | ||
845b51d6 PB |
28935 | case BFD_RELOC_ARM_V4BX: |
28936 | /* This will need to go in the object file. */ | |
28937 | fixP->fx_done = 0; | |
28938 | break; | |
28939 | ||
c19d1205 ZW |
28940 | case BFD_RELOC_UNUSED: |
28941 | default: | |
28942 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28943 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
28944 | } | |
6c43fab6 RE |
28945 | } |
28946 | ||
c19d1205 ZW |
28947 | /* Translate internal representation of relocation info to BFD target |
28948 | format. */ | |
a737bd4d | 28949 | |
c19d1205 | 28950 | arelent * |
00a97672 | 28951 | tc_gen_reloc (asection *section, fixS *fixp) |
a737bd4d | 28952 | { |
c19d1205 ZW |
28953 | arelent * reloc; |
28954 | bfd_reloc_code_real_type code; | |
a737bd4d | 28955 | |
325801bd | 28956 | reloc = XNEW (arelent); |
a737bd4d | 28957 | |
325801bd | 28958 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
c19d1205 ZW |
28959 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
28960 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 28961 | |
2fc8bdac | 28962 | if (fixp->fx_pcrel) |
00a97672 RS |
28963 | { |
28964 | if (section->use_rela_p) | |
28965 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
28966 | else | |
28967 | fixp->fx_offset = reloc->address; | |
28968 | } | |
c19d1205 | 28969 | reloc->addend = fixp->fx_offset; |
a737bd4d | 28970 | |
c19d1205 | 28971 | switch (fixp->fx_r_type) |
a737bd4d | 28972 | { |
c19d1205 ZW |
28973 | case BFD_RELOC_8: |
28974 | if (fixp->fx_pcrel) | |
28975 | { | |
28976 | code = BFD_RELOC_8_PCREL; | |
28977 | break; | |
28978 | } | |
1a0670f3 | 28979 | /* Fall through. */ |
a737bd4d | 28980 | |
c19d1205 ZW |
28981 | case BFD_RELOC_16: |
28982 | if (fixp->fx_pcrel) | |
28983 | { | |
28984 | code = BFD_RELOC_16_PCREL; | |
28985 | break; | |
28986 | } | |
1a0670f3 | 28987 | /* Fall through. */ |
6c43fab6 | 28988 | |
c19d1205 ZW |
28989 | case BFD_RELOC_32: |
28990 | if (fixp->fx_pcrel) | |
28991 | { | |
28992 | code = BFD_RELOC_32_PCREL; | |
28993 | break; | |
28994 | } | |
1a0670f3 | 28995 | /* Fall through. */ |
a737bd4d | 28996 | |
b6895b4f PB |
28997 | case BFD_RELOC_ARM_MOVW: |
28998 | if (fixp->fx_pcrel) | |
28999 | { | |
29000 | code = BFD_RELOC_ARM_MOVW_PCREL; | |
29001 | break; | |
29002 | } | |
1a0670f3 | 29003 | /* Fall through. */ |
b6895b4f PB |
29004 | |
29005 | case BFD_RELOC_ARM_MOVT: | |
29006 | if (fixp->fx_pcrel) | |
29007 | { | |
29008 | code = BFD_RELOC_ARM_MOVT_PCREL; | |
29009 | break; | |
29010 | } | |
1a0670f3 | 29011 | /* Fall through. */ |
b6895b4f PB |
29012 | |
29013 | case BFD_RELOC_ARM_THUMB_MOVW: | |
29014 | if (fixp->fx_pcrel) | |
29015 | { | |
29016 | code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; | |
29017 | break; | |
29018 | } | |
1a0670f3 | 29019 | /* Fall through. */ |
b6895b4f PB |
29020 | |
29021 | case BFD_RELOC_ARM_THUMB_MOVT: | |
29022 | if (fixp->fx_pcrel) | |
29023 | { | |
29024 | code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; | |
29025 | break; | |
29026 | } | |
1a0670f3 | 29027 | /* Fall through. */ |
b6895b4f | 29028 | |
c19d1205 ZW |
29029 | case BFD_RELOC_NONE: |
29030 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
29031 | case BFD_RELOC_ARM_PCREL_BLX: | |
29032 | case BFD_RELOC_RVA: | |
29033 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
29034 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
29035 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
29036 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
29037 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
29038 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
c19d1205 ZW |
29039 | case BFD_RELOC_VTABLE_ENTRY: |
29040 | case BFD_RELOC_VTABLE_INHERIT: | |
f0927246 NC |
29041 | #ifdef TE_PE |
29042 | case BFD_RELOC_32_SECREL: | |
29043 | #endif | |
c19d1205 ZW |
29044 | code = fixp->fx_r_type; |
29045 | break; | |
a737bd4d | 29046 | |
00adf2d4 JB |
29047 | case BFD_RELOC_THUMB_PCREL_BLX: |
29048 | #ifdef OBJ_ELF | |
29049 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
29050 | code = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
29051 | else | |
29052 | #endif | |
29053 | code = BFD_RELOC_THUMB_PCREL_BLX; | |
29054 | break; | |
29055 | ||
c19d1205 ZW |
29056 | case BFD_RELOC_ARM_LITERAL: |
29057 | case BFD_RELOC_ARM_HWLITERAL: | |
29058 | /* If this is called then the a literal has | |
29059 | been referenced across a section boundary. */ | |
29060 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
29061 | _("literal referenced across section boundary")); | |
29062 | return NULL; | |
a737bd4d | 29063 | |
c19d1205 | 29064 | #ifdef OBJ_ELF |
0855e32b NS |
29065 | case BFD_RELOC_ARM_TLS_CALL: |
29066 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
29067 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
29068 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
c19d1205 ZW |
29069 | case BFD_RELOC_ARM_GOT32: |
29070 | case BFD_RELOC_ARM_GOTOFF: | |
b43420e6 | 29071 | case BFD_RELOC_ARM_GOT_PREL: |
c19d1205 ZW |
29072 | case BFD_RELOC_ARM_PLT32: |
29073 | case BFD_RELOC_ARM_TARGET1: | |
29074 | case BFD_RELOC_ARM_ROSEGREL32: | |
29075 | case BFD_RELOC_ARM_SBREL32: | |
29076 | case BFD_RELOC_ARM_PREL31: | |
29077 | case BFD_RELOC_ARM_TARGET2: | |
c19d1205 | 29078 | case BFD_RELOC_ARM_TLS_LDO32: |
39b41c9c PB |
29079 | case BFD_RELOC_ARM_PCREL_CALL: |
29080 | case BFD_RELOC_ARM_PCREL_JUMP: | |
4962c51a MS |
29081 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
29082 | case BFD_RELOC_ARM_ALU_PC_G0: | |
29083 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
29084 | case BFD_RELOC_ARM_ALU_PC_G1: | |
29085 | case BFD_RELOC_ARM_ALU_PC_G2: | |
29086 | case BFD_RELOC_ARM_LDR_PC_G0: | |
29087 | case BFD_RELOC_ARM_LDR_PC_G1: | |
29088 | case BFD_RELOC_ARM_LDR_PC_G2: | |
29089 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
29090 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
29091 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
29092 | case BFD_RELOC_ARM_LDC_PC_G0: | |
29093 | case BFD_RELOC_ARM_LDC_PC_G1: | |
29094 | case BFD_RELOC_ARM_LDC_PC_G2: | |
29095 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
29096 | case BFD_RELOC_ARM_ALU_SB_G0: | |
29097 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
29098 | case BFD_RELOC_ARM_ALU_SB_G1: | |
29099 | case BFD_RELOC_ARM_ALU_SB_G2: | |
29100 | case BFD_RELOC_ARM_LDR_SB_G0: | |
29101 | case BFD_RELOC_ARM_LDR_SB_G1: | |
29102 | case BFD_RELOC_ARM_LDR_SB_G2: | |
29103 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
29104 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
29105 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
29106 | case BFD_RELOC_ARM_LDC_SB_G0: | |
29107 | case BFD_RELOC_ARM_LDC_SB_G1: | |
29108 | case BFD_RELOC_ARM_LDC_SB_G2: | |
845b51d6 | 29109 | case BFD_RELOC_ARM_V4BX: |
72d98d16 MG |
29110 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC: |
29111 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC: | |
29112 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC: | |
29113 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC: | |
188fd7ae CL |
29114 | case BFD_RELOC_ARM_GOTFUNCDESC: |
29115 | case BFD_RELOC_ARM_GOTOFFFUNCDESC: | |
29116 | case BFD_RELOC_ARM_FUNCDESC: | |
e5d6e09e | 29117 | case BFD_RELOC_ARM_THUMB_BF17: |
1caf72a5 | 29118 | case BFD_RELOC_ARM_THUMB_BF19: |
1889da70 | 29119 | case BFD_RELOC_ARM_THUMB_BF13: |
c19d1205 ZW |
29120 | code = fixp->fx_r_type; |
29121 | break; | |
a737bd4d | 29122 | |
0855e32b | 29123 | case BFD_RELOC_ARM_TLS_GOTDESC: |
c19d1205 | 29124 | case BFD_RELOC_ARM_TLS_GD32: |
5c5a4843 | 29125 | case BFD_RELOC_ARM_TLS_GD32_FDPIC: |
75c11999 | 29126 | case BFD_RELOC_ARM_TLS_LE32: |
c19d1205 | 29127 | case BFD_RELOC_ARM_TLS_IE32: |
5c5a4843 | 29128 | case BFD_RELOC_ARM_TLS_IE32_FDPIC: |
c19d1205 | 29129 | case BFD_RELOC_ARM_TLS_LDM32: |
5c5a4843 | 29130 | case BFD_RELOC_ARM_TLS_LDM32_FDPIC: |
c19d1205 ZW |
29131 | /* BFD will include the symbol's address in the addend. |
29132 | But we don't want that, so subtract it out again here. */ | |
29133 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
29134 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
29135 | code = fixp->fx_r_type; | |
29136 | break; | |
29137 | #endif | |
a737bd4d | 29138 | |
c19d1205 ZW |
29139 | case BFD_RELOC_ARM_IMMEDIATE: |
29140 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
29141 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
29142 | return NULL; | |
a737bd4d | 29143 | |
c19d1205 ZW |
29144 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
29145 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
29146 | _("ADRL used for a symbol not defined in the same file")); | |
29147 | return NULL; | |
a737bd4d | 29148 | |
e12437dc | 29149 | case BFD_RELOC_THUMB_PCREL_BRANCH5: |
f6b2b12d | 29150 | case BFD_RELOC_THUMB_PCREL_BFCSEL: |
60f993ce | 29151 | case BFD_RELOC_ARM_THUMB_LOOP12: |
e12437dc AV |
29152 | as_bad_where (fixp->fx_file, fixp->fx_line, |
29153 | _("%s used for a symbol not defined in the same file"), | |
29154 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
29155 | return NULL; | |
29156 | ||
c19d1205 | 29157 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
29158 | if (section->use_rela_p) |
29159 | { | |
29160 | code = fixp->fx_r_type; | |
29161 | break; | |
29162 | } | |
29163 | ||
c19d1205 ZW |
29164 | if (fixp->fx_addsy != NULL |
29165 | && !S_IS_DEFINED (fixp->fx_addsy) | |
29166 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 29167 | { |
c19d1205 ZW |
29168 | as_bad_where (fixp->fx_file, fixp->fx_line, |
29169 | _("undefined local label `%s'"), | |
29170 | S_GET_NAME (fixp->fx_addsy)); | |
29171 | return NULL; | |
a737bd4d NC |
29172 | } |
29173 | ||
c19d1205 ZW |
29174 | as_bad_where (fixp->fx_file, fixp->fx_line, |
29175 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
29176 | return NULL; | |
a737bd4d | 29177 | |
c19d1205 ZW |
29178 | default: |
29179 | { | |
e0471c16 | 29180 | const char * type; |
6c43fab6 | 29181 | |
c19d1205 ZW |
29182 | switch (fixp->fx_r_type) |
29183 | { | |
29184 | case BFD_RELOC_NONE: type = "NONE"; break; | |
29185 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
29186 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 29187 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
29188 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
29189 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
29190 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
db187cb9 | 29191 | case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break; |
8f06b2d8 | 29192 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
29193 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
29194 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
29195 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
29196 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
29197 | default: type = _("<unknown>"); break; | |
29198 | } | |
29199 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
29200 | _("cannot represent %s relocation in this object file format"), | |
29201 | type); | |
29202 | return NULL; | |
29203 | } | |
a737bd4d | 29204 | } |
6c43fab6 | 29205 | |
c19d1205 ZW |
29206 | #ifdef OBJ_ELF |
29207 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
29208 | && GOT_symbol | |
29209 | && fixp->fx_addsy == GOT_symbol) | |
29210 | { | |
29211 | code = BFD_RELOC_ARM_GOTPC; | |
29212 | reloc->addend = fixp->fx_offset = reloc->address; | |
29213 | } | |
29214 | #endif | |
6c43fab6 | 29215 | |
c19d1205 | 29216 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 29217 | |
c19d1205 ZW |
29218 | if (reloc->howto == NULL) |
29219 | { | |
29220 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
29221 | _("cannot represent %s relocation in this object file format"), | |
29222 | bfd_get_reloc_code_name (code)); | |
29223 | return NULL; | |
29224 | } | |
6c43fab6 | 29225 | |
c19d1205 ZW |
29226 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
29227 | vtable entry to be used in the relocation's section offset. */ | |
29228 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
29229 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 29230 | |
c19d1205 | 29231 | return reloc; |
6c43fab6 RE |
29232 | } |
29233 | ||
c19d1205 | 29234 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 29235 | |
c19d1205 ZW |
29236 | void |
29237 | cons_fix_new_arm (fragS * frag, | |
29238 | int where, | |
29239 | int size, | |
62ebcb5c AM |
29240 | expressionS * exp, |
29241 | bfd_reloc_code_real_type reloc) | |
6c43fab6 | 29242 | { |
c19d1205 | 29243 | int pcrel = 0; |
6c43fab6 | 29244 | |
c19d1205 ZW |
29245 | /* Pick a reloc. |
29246 | FIXME: @@ Should look at CPU word size. */ | |
29247 | switch (size) | |
29248 | { | |
29249 | case 1: | |
62ebcb5c | 29250 | reloc = BFD_RELOC_8; |
c19d1205 ZW |
29251 | break; |
29252 | case 2: | |
62ebcb5c | 29253 | reloc = BFD_RELOC_16; |
c19d1205 ZW |
29254 | break; |
29255 | case 4: | |
29256 | default: | |
62ebcb5c | 29257 | reloc = BFD_RELOC_32; |
c19d1205 ZW |
29258 | break; |
29259 | case 8: | |
62ebcb5c | 29260 | reloc = BFD_RELOC_64; |
c19d1205 ZW |
29261 | break; |
29262 | } | |
6c43fab6 | 29263 | |
f0927246 NC |
29264 | #ifdef TE_PE |
29265 | if (exp->X_op == O_secrel) | |
29266 | { | |
29267 | exp->X_op = O_symbol; | |
62ebcb5c | 29268 | reloc = BFD_RELOC_32_SECREL; |
f0927246 NC |
29269 | } |
29270 | #endif | |
29271 | ||
62ebcb5c | 29272 | fix_new_exp (frag, where, size, exp, pcrel, reloc); |
c19d1205 | 29273 | } |
6c43fab6 | 29274 | |
4343666d | 29275 | #if defined (OBJ_COFF) |
c19d1205 ZW |
29276 | void |
29277 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 29278 | { |
c19d1205 ZW |
29279 | /* If the destination of the branch is a defined symbol which does not have |
29280 | the THUMB_FUNC attribute, then we must be calling a function which has | |
29281 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
29282 | function and change the branch to refer to that function instead. */ | |
29283 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
29284 | && fixP->fx_addsy != NULL | |
29285 | && S_IS_DEFINED (fixP->fx_addsy) | |
29286 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 29287 | { |
c19d1205 | 29288 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 29289 | } |
c19d1205 ZW |
29290 | } |
29291 | #endif | |
6c43fab6 | 29292 | |
267bf995 | 29293 | |
c19d1205 ZW |
29294 | int |
29295 | arm_force_relocation (struct fix * fixp) | |
29296 | { | |
29297 | #if defined (OBJ_COFF) && defined (TE_PE) | |
29298 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
29299 | return 1; | |
29300 | #endif | |
6c43fab6 | 29301 | |
267bf995 RR |
29302 | /* In case we have a call or a branch to a function in ARM ISA mode from |
29303 | a thumb function or vice-versa force the relocation. These relocations | |
29304 | are cleared off for some cores that might have blx and simple transformations | |
29305 | are possible. */ | |
29306 | ||
29307 | #ifdef OBJ_ELF | |
29308 | switch (fixp->fx_r_type) | |
29309 | { | |
29310 | case BFD_RELOC_ARM_PCREL_JUMP: | |
29311 | case BFD_RELOC_ARM_PCREL_CALL: | |
29312 | case BFD_RELOC_THUMB_PCREL_BLX: | |
29313 | if (THUMB_IS_FUNC (fixp->fx_addsy)) | |
29314 | return 1; | |
29315 | break; | |
29316 | ||
29317 | case BFD_RELOC_ARM_PCREL_BLX: | |
29318 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
29319 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
29320 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
29321 | if (ARM_IS_FUNC (fixp->fx_addsy)) | |
29322 | return 1; | |
29323 | break; | |
29324 | ||
29325 | default: | |
29326 | break; | |
29327 | } | |
29328 | #endif | |
29329 | ||
b5884301 PB |
29330 | /* Resolve these relocations even if the symbol is extern or weak. |
29331 | Technically this is probably wrong due to symbol preemption. | |
29332 | In practice these relocations do not have enough range to be useful | |
29333 | at dynamic link time, and some code (e.g. in the Linux kernel) | |
29334 | expects these references to be resolved. */ | |
c19d1205 ZW |
29335 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE |
29336 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
b5884301 | 29337 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8 |
0110f2b8 | 29338 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
b5884301 PB |
29339 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
29340 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2 | |
29341 | || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET | |
16805f35 | 29342 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM |
0110f2b8 PB |
29343 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
29344 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
b5884301 PB |
29345 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM |
29346 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12 | |
29347 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM | |
29348 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2) | |
c19d1205 | 29349 | return 0; |
a737bd4d | 29350 | |
4962c51a MS |
29351 | /* Always leave these relocations for the linker. */ |
29352 | if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
29353 | && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
29354 | || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
29355 | return 1; | |
29356 | ||
f0291e4c PB |
29357 | /* Always generate relocations against function symbols. */ |
29358 | if (fixp->fx_r_type == BFD_RELOC_32 | |
29359 | && fixp->fx_addsy | |
29360 | && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) | |
29361 | return 1; | |
29362 | ||
c19d1205 | 29363 | return generic_force_reloc (fixp); |
404ff6b5 AH |
29364 | } |
29365 | ||
0ffdc86c | 29366 | #if defined (OBJ_ELF) || defined (OBJ_COFF) |
e28387c3 PB |
29367 | /* Relocations against function names must be left unadjusted, |
29368 | so that the linker can use this information to generate interworking | |
29369 | stubs. The MIPS version of this function | |
c19d1205 ZW |
29370 | also prevents relocations that are mips-16 specific, but I do not |
29371 | know why it does this. | |
404ff6b5 | 29372 | |
c19d1205 ZW |
29373 | FIXME: |
29374 | There is one other problem that ought to be addressed here, but | |
29375 | which currently is not: Taking the address of a label (rather | |
29376 | than a function) and then later jumping to that address. Such | |
29377 | addresses also ought to have their bottom bit set (assuming that | |
29378 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 29379 | |
c19d1205 ZW |
29380 | bfd_boolean |
29381 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 29382 | { |
c19d1205 ZW |
29383 | if (fixP->fx_addsy == NULL) |
29384 | return 1; | |
404ff6b5 | 29385 | |
e28387c3 PB |
29386 | /* Preserve relocations against symbols with function type. */ |
29387 | if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) | |
c921be7d | 29388 | return FALSE; |
e28387c3 | 29389 | |
c19d1205 ZW |
29390 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
29391 | && fixP->fx_subsy == NULL) | |
c921be7d | 29392 | return FALSE; |
a737bd4d | 29393 | |
c19d1205 ZW |
29394 | /* We need the symbol name for the VTABLE entries. */ |
29395 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
29396 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
c921be7d | 29397 | return FALSE; |
404ff6b5 | 29398 | |
c19d1205 ZW |
29399 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
29400 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
29401 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
29402 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
29403 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
5c5a4843 | 29404 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32_FDPIC |
c19d1205 ZW |
29405 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 |
29406 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
5c5a4843 | 29407 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32_FDPIC |
c19d1205 | 29408 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 |
5c5a4843 | 29409 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32_FDPIC |
c19d1205 | 29410 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 |
0855e32b NS |
29411 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC |
29412 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL | |
29413 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL | |
29414 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ | |
29415 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
c19d1205 | 29416 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) |
c921be7d | 29417 | return FALSE; |
a737bd4d | 29418 | |
4962c51a MS |
29419 | /* Similarly for group relocations. */ |
29420 | if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
29421 | && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
29422 | || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
c921be7d | 29423 | return FALSE; |
4962c51a | 29424 | |
79947c54 CD |
29425 | /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */ |
29426 | if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW | |
29427 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
29428 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL | |
29429 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL | |
29430 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
29431 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT | |
29432 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL | |
29433 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL) | |
c921be7d | 29434 | return FALSE; |
79947c54 | 29435 | |
72d98d16 MG |
29436 | /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited |
29437 | offsets, so keep these symbols. */ | |
29438 | if (fixP->fx_r_type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC | |
29439 | && fixP->fx_r_type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) | |
29440 | return FALSE; | |
29441 | ||
c921be7d | 29442 | return TRUE; |
a737bd4d | 29443 | } |
0ffdc86c NC |
29444 | #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ |
29445 | ||
29446 | #ifdef OBJ_ELF | |
c19d1205 ZW |
29447 | const char * |
29448 | elf32_arm_target_format (void) | |
404ff6b5 | 29449 | { |
c19d1205 ZW |
29450 | #ifdef TE_SYMBIAN |
29451 | return (target_big_endian | |
29452 | ? "elf32-bigarm-symbian" | |
29453 | : "elf32-littlearm-symbian"); | |
29454 | #elif defined (TE_VXWORKS) | |
29455 | return (target_big_endian | |
29456 | ? "elf32-bigarm-vxworks" | |
29457 | : "elf32-littlearm-vxworks"); | |
b38cadfb NC |
29458 | #elif defined (TE_NACL) |
29459 | return (target_big_endian | |
29460 | ? "elf32-bigarm-nacl" | |
29461 | : "elf32-littlearm-nacl"); | |
c19d1205 | 29462 | #else |
18a20338 CL |
29463 | if (arm_fdpic) |
29464 | { | |
29465 | if (target_big_endian) | |
29466 | return "elf32-bigarm-fdpic"; | |
29467 | else | |
29468 | return "elf32-littlearm-fdpic"; | |
29469 | } | |
c19d1205 | 29470 | else |
18a20338 CL |
29471 | { |
29472 | if (target_big_endian) | |
29473 | return "elf32-bigarm"; | |
29474 | else | |
29475 | return "elf32-littlearm"; | |
29476 | } | |
c19d1205 | 29477 | #endif |
404ff6b5 AH |
29478 | } |
29479 | ||
c19d1205 ZW |
29480 | void |
29481 | armelf_frob_symbol (symbolS * symp, | |
29482 | int * puntp) | |
404ff6b5 | 29483 | { |
c19d1205 ZW |
29484 | elf_frob_symbol (symp, puntp); |
29485 | } | |
29486 | #endif | |
404ff6b5 | 29487 | |
c19d1205 | 29488 | /* MD interface: Finalization. */ |
a737bd4d | 29489 | |
c19d1205 ZW |
29490 | void |
29491 | arm_cleanup (void) | |
29492 | { | |
29493 | literal_pool * pool; | |
a737bd4d | 29494 | |
5ee91343 AV |
29495 | /* Ensure that all the predication blocks are properly closed. */ |
29496 | check_pred_blocks_finished (); | |
e07e6e58 | 29497 | |
c19d1205 ZW |
29498 | for (pool = list_of_pools; pool; pool = pool->next) |
29499 | { | |
5f4273c7 | 29500 | /* Put it at the end of the relevant section. */ |
c19d1205 ZW |
29501 | subseg_set (pool->section, pool->sub_section); |
29502 | #ifdef OBJ_ELF | |
29503 | arm_elf_change_section (); | |
29504 | #endif | |
29505 | s_ltorg (0); | |
29506 | } | |
404ff6b5 AH |
29507 | } |
29508 | ||
cd000bff DJ |
29509 | #ifdef OBJ_ELF |
29510 | /* Remove any excess mapping symbols generated for alignment frags in | |
29511 | SEC. We may have created a mapping symbol before a zero byte | |
29512 | alignment; remove it if there's a mapping symbol after the | |
29513 | alignment. */ | |
29514 | static void | |
29515 | check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, | |
29516 | void *dummy ATTRIBUTE_UNUSED) | |
29517 | { | |
29518 | segment_info_type *seginfo = seg_info (sec); | |
29519 | fragS *fragp; | |
29520 | ||
29521 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
29522 | return; | |
29523 | ||
29524 | for (fragp = seginfo->frchainP->frch_root; | |
29525 | fragp != NULL; | |
29526 | fragp = fragp->fr_next) | |
29527 | { | |
29528 | symbolS *sym = fragp->tc_frag_data.last_map; | |
29529 | fragS *next = fragp->fr_next; | |
29530 | ||
29531 | /* Variable-sized frags have been converted to fixed size by | |
29532 | this point. But if this was variable-sized to start with, | |
29533 | there will be a fixed-size frag after it. So don't handle | |
29534 | next == NULL. */ | |
29535 | if (sym == NULL || next == NULL) | |
29536 | continue; | |
29537 | ||
29538 | if (S_GET_VALUE (sym) < next->fr_address) | |
29539 | /* Not at the end of this frag. */ | |
29540 | continue; | |
29541 | know (S_GET_VALUE (sym) == next->fr_address); | |
29542 | ||
29543 | do | |
29544 | { | |
29545 | if (next->tc_frag_data.first_map != NULL) | |
29546 | { | |
29547 | /* Next frag starts with a mapping symbol. Discard this | |
29548 | one. */ | |
29549 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
29550 | break; | |
29551 | } | |
29552 | ||
29553 | if (next->fr_next == NULL) | |
29554 | { | |
29555 | /* This mapping symbol is at the end of the section. Discard | |
29556 | it. */ | |
29557 | know (next->fr_fix == 0 && next->fr_var == 0); | |
29558 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
29559 | break; | |
29560 | } | |
29561 | ||
29562 | /* As long as we have empty frags without any mapping symbols, | |
29563 | keep looking. */ | |
29564 | /* If the next frag is non-empty and does not start with a | |
29565 | mapping symbol, then this mapping symbol is required. */ | |
29566 | if (next->fr_address != next->fr_next->fr_address) | |
29567 | break; | |
29568 | ||
29569 | next = next->fr_next; | |
29570 | } | |
29571 | while (next != NULL); | |
29572 | } | |
29573 | } | |
29574 | #endif | |
29575 | ||
c19d1205 ZW |
29576 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
29577 | ARM ones. */ | |
404ff6b5 | 29578 | |
c19d1205 ZW |
29579 | void |
29580 | arm_adjust_symtab (void) | |
404ff6b5 | 29581 | { |
c19d1205 ZW |
29582 | #ifdef OBJ_COFF |
29583 | symbolS * sym; | |
404ff6b5 | 29584 | |
c19d1205 ZW |
29585 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
29586 | { | |
29587 | if (ARM_IS_THUMB (sym)) | |
29588 | { | |
29589 | if (THUMB_IS_FUNC (sym)) | |
29590 | { | |
29591 | /* Mark the symbol as a Thumb function. */ | |
29592 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
29593 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
29594 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 29595 | |
c19d1205 ZW |
29596 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
29597 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
29598 | else | |
29599 | as_bad (_("%s: unexpected function type: %d"), | |
29600 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
29601 | } | |
29602 | else switch (S_GET_STORAGE_CLASS (sym)) | |
29603 | { | |
29604 | case C_EXT: | |
29605 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
29606 | break; | |
29607 | case C_STAT: | |
29608 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
29609 | break; | |
29610 | case C_LABEL: | |
29611 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
29612 | break; | |
29613 | default: | |
29614 | /* Do nothing. */ | |
29615 | break; | |
29616 | } | |
29617 | } | |
a737bd4d | 29618 | |
c19d1205 ZW |
29619 | if (ARM_IS_INTERWORK (sym)) |
29620 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 29621 | } |
c19d1205 ZW |
29622 | #endif |
29623 | #ifdef OBJ_ELF | |
29624 | symbolS * sym; | |
29625 | char bind; | |
404ff6b5 | 29626 | |
c19d1205 | 29627 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 29628 | { |
c19d1205 ZW |
29629 | if (ARM_IS_THUMB (sym)) |
29630 | { | |
29631 | elf_symbol_type * elf_sym; | |
404ff6b5 | 29632 | |
c19d1205 ZW |
29633 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
29634 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 29635 | |
b0796911 PB |
29636 | if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, |
29637 | BFD_ARM_SPECIAL_SYM_TYPE_ANY)) | |
c19d1205 ZW |
29638 | { |
29639 | /* If it's a .thumb_func, declare it as so, | |
29640 | otherwise tag label as .code 16. */ | |
29641 | if (THUMB_IS_FUNC (sym)) | |
39d911fc TP |
29642 | ARM_SET_SYM_BRANCH_TYPE (elf_sym->internal_elf_sym.st_target_internal, |
29643 | ST_BRANCH_TO_THUMB); | |
3ba67470 | 29644 | else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
c19d1205 ZW |
29645 | elf_sym->internal_elf_sym.st_info = |
29646 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
29647 | } | |
29648 | } | |
29649 | } | |
cd000bff DJ |
29650 | |
29651 | /* Remove any overlapping mapping symbols generated by alignment frags. */ | |
29652 | bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); | |
709001e9 MM |
29653 | /* Now do generic ELF adjustments. */ |
29654 | elf_adjust_symtab (); | |
c19d1205 | 29655 | #endif |
404ff6b5 AH |
29656 | } |
29657 | ||
c19d1205 | 29658 | /* MD interface: Initialization. */ |
404ff6b5 | 29659 | |
a737bd4d | 29660 | static void |
c19d1205 | 29661 | set_constant_flonums (void) |
a737bd4d | 29662 | { |
c19d1205 | 29663 | int i; |
404ff6b5 | 29664 | |
c19d1205 ZW |
29665 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
29666 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
29667 | abort (); | |
a737bd4d | 29668 | } |
404ff6b5 | 29669 | |
3e9e4fcf JB |
29670 | /* Auto-select Thumb mode if it's the only available instruction set for the |
29671 | given architecture. */ | |
29672 | ||
29673 | static void | |
29674 | autoselect_thumb_from_cpu_variant (void) | |
29675 | { | |
29676 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) | |
29677 | opcode_select (16); | |
29678 | } | |
29679 | ||
c19d1205 ZW |
29680 | void |
29681 | md_begin (void) | |
a737bd4d | 29682 | { |
c19d1205 ZW |
29683 | unsigned mach; |
29684 | unsigned int i; | |
404ff6b5 | 29685 | |
c19d1205 ZW |
29686 | if ( (arm_ops_hsh = hash_new ()) == NULL |
29687 | || (arm_cond_hsh = hash_new ()) == NULL | |
5ee91343 | 29688 | || (arm_vcond_hsh = hash_new ()) == NULL |
c19d1205 ZW |
29689 | || (arm_shift_hsh = hash_new ()) == NULL |
29690 | || (arm_psr_hsh = hash_new ()) == NULL | |
62b3e311 | 29691 | || (arm_v7m_psr_hsh = hash_new ()) == NULL |
c19d1205 | 29692 | || (arm_reg_hsh = hash_new ()) == NULL |
62b3e311 PB |
29693 | || (arm_reloc_hsh = hash_new ()) == NULL |
29694 | || (arm_barrier_opt_hsh = hash_new ()) == NULL) | |
c19d1205 ZW |
29695 | as_fatal (_("virtual memory exhausted")); |
29696 | ||
29697 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
d3ce72d0 | 29698 | hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i)); |
c19d1205 | 29699 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) |
d3ce72d0 | 29700 | hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i)); |
5ee91343 AV |
29701 | for (i = 0; i < sizeof (vconds) / sizeof (struct asm_cond); i++) |
29702 | hash_insert (arm_vcond_hsh, vconds[i].template_name, (void *) (vconds + i)); | |
c19d1205 | 29703 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) |
5a49b8ac | 29704 | hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i)); |
c19d1205 | 29705 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 29706 | hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i)); |
62b3e311 | 29707 | for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 29708 | hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name, |
477330fc | 29709 | (void *) (v7m_psrs + i)); |
c19d1205 | 29710 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) |
5a49b8ac | 29711 | hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); |
62b3e311 PB |
29712 | for (i = 0; |
29713 | i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); | |
29714 | i++) | |
d3ce72d0 | 29715 | hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name, |
5a49b8ac | 29716 | (void *) (barrier_opt_names + i)); |
c19d1205 | 29717 | #ifdef OBJ_ELF |
3da1d841 NC |
29718 | for (i = 0; i < ARRAY_SIZE (reloc_names); i++) |
29719 | { | |
29720 | struct reloc_entry * entry = reloc_names + i; | |
29721 | ||
29722 | if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32) | |
29723 | /* This makes encode_branch() use the EABI versions of this relocation. */ | |
29724 | entry->reloc = BFD_RELOC_UNUSED; | |
29725 | ||
29726 | hash_insert (arm_reloc_hsh, entry->name, (void *) entry); | |
29727 | } | |
c19d1205 ZW |
29728 | #endif |
29729 | ||
29730 | set_constant_flonums (); | |
404ff6b5 | 29731 | |
c19d1205 ZW |
29732 | /* Set the cpu variant based on the command-line options. We prefer |
29733 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
29734 | -mfpu= over any other way of setting the floating point unit. | |
29735 | Use of legacy options with new options are faulted. */ | |
e74cfd16 | 29736 | if (legacy_cpu) |
404ff6b5 | 29737 | { |
e74cfd16 | 29738 | if (mcpu_cpu_opt || march_cpu_opt) |
c19d1205 ZW |
29739 | as_bad (_("use of old and new-style options to set CPU type")); |
29740 | ||
4d354d8b | 29741 | selected_arch = *legacy_cpu; |
404ff6b5 | 29742 | } |
4d354d8b TP |
29743 | else if (mcpu_cpu_opt) |
29744 | { | |
29745 | selected_arch = *mcpu_cpu_opt; | |
29746 | selected_ext = *mcpu_ext_opt; | |
29747 | } | |
29748 | else if (march_cpu_opt) | |
c168ce07 | 29749 | { |
4d354d8b TP |
29750 | selected_arch = *march_cpu_opt; |
29751 | selected_ext = *march_ext_opt; | |
c168ce07 | 29752 | } |
4d354d8b | 29753 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext); |
404ff6b5 | 29754 | |
e74cfd16 | 29755 | if (legacy_fpu) |
c19d1205 | 29756 | { |
e74cfd16 | 29757 | if (mfpu_opt) |
c19d1205 | 29758 | as_bad (_("use of old and new-style options to set FPU type")); |
03b1477f | 29759 | |
4d354d8b | 29760 | selected_fpu = *legacy_fpu; |
03b1477f | 29761 | } |
4d354d8b TP |
29762 | else if (mfpu_opt) |
29763 | selected_fpu = *mfpu_opt; | |
29764 | else | |
03b1477f | 29765 | { |
45eb4c1b NS |
29766 | #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \ |
29767 | || defined (TE_NetBSD) || defined (TE_VXWORKS)) | |
39c2da32 RE |
29768 | /* Some environments specify a default FPU. If they don't, infer it |
29769 | from the processor. */ | |
e74cfd16 | 29770 | if (mcpu_fpu_opt) |
4d354d8b | 29771 | selected_fpu = *mcpu_fpu_opt; |
e7da50fa | 29772 | else if (march_fpu_opt) |
4d354d8b | 29773 | selected_fpu = *march_fpu_opt; |
39c2da32 | 29774 | #else |
4d354d8b | 29775 | selected_fpu = fpu_default; |
39c2da32 | 29776 | #endif |
03b1477f RE |
29777 | } |
29778 | ||
4d354d8b | 29779 | if (ARM_FEATURE_ZERO (selected_fpu)) |
03b1477f | 29780 | { |
4d354d8b TP |
29781 | if (!no_cpu_selected ()) |
29782 | selected_fpu = fpu_default; | |
03b1477f | 29783 | else |
4d354d8b | 29784 | selected_fpu = fpu_arch_fpa; |
03b1477f RE |
29785 | } |
29786 | ||
ee065d83 | 29787 | #ifdef CPU_DEFAULT |
4d354d8b | 29788 | if (ARM_FEATURE_ZERO (selected_arch)) |
ee065d83 | 29789 | { |
4d354d8b TP |
29790 | selected_arch = cpu_default; |
29791 | selected_cpu = selected_arch; | |
ee065d83 | 29792 | } |
4d354d8b | 29793 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); |
e74cfd16 | 29794 | #else |
4d354d8b TP |
29795 | /* Autodection of feature mode: allow all features in cpu_variant but leave |
29796 | selected_cpu unset. It will be set in aeabi_set_public_attributes () | |
29797 | after all instruction have been processed and we can decide what CPU | |
29798 | should be selected. */ | |
29799 | if (ARM_FEATURE_ZERO (selected_arch)) | |
29800 | ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu); | |
ee065d83 | 29801 | else |
4d354d8b | 29802 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); |
ee065d83 | 29803 | #endif |
03b1477f | 29804 | |
3e9e4fcf JB |
29805 | autoselect_thumb_from_cpu_variant (); |
29806 | ||
e74cfd16 | 29807 | arm_arch_used = thumb_arch_used = arm_arch_none; |
ee065d83 | 29808 | |
f17c130b | 29809 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 29810 | { |
7cc69913 NC |
29811 | unsigned int flags = 0; |
29812 | ||
29813 | #if defined OBJ_ELF | |
29814 | flags = meabi_flags; | |
d507cf36 PB |
29815 | |
29816 | switch (meabi_flags) | |
33a392fb | 29817 | { |
d507cf36 | 29818 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 29819 | #endif |
d507cf36 PB |
29820 | /* Set the flags in the private structure. */ |
29821 | if (uses_apcs_26) flags |= F_APCS26; | |
29822 | if (support_interwork) flags |= F_INTERWORK; | |
29823 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 29824 | if (pic_code) flags |= F_PIC; |
e74cfd16 | 29825 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
7cc69913 NC |
29826 | flags |= F_SOFT_FLOAT; |
29827 | ||
d507cf36 PB |
29828 | switch (mfloat_abi_opt) |
29829 | { | |
29830 | case ARM_FLOAT_ABI_SOFT: | |
29831 | case ARM_FLOAT_ABI_SOFTFP: | |
29832 | flags |= F_SOFT_FLOAT; | |
29833 | break; | |
33a392fb | 29834 | |
d507cf36 PB |
29835 | case ARM_FLOAT_ABI_HARD: |
29836 | if (flags & F_SOFT_FLOAT) | |
29837 | as_bad (_("hard-float conflicts with specified fpu")); | |
29838 | break; | |
29839 | } | |
03b1477f | 29840 | |
e74cfd16 PB |
29841 | /* Using pure-endian doubles (even if soft-float). */ |
29842 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
7cc69913 | 29843 | flags |= F_VFP_FLOAT; |
f17c130b | 29844 | |
fde78edd | 29845 | #if defined OBJ_ELF |
e74cfd16 | 29846 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
d507cf36 | 29847 | flags |= EF_ARM_MAVERICK_FLOAT; |
d507cf36 PB |
29848 | break; |
29849 | ||
8cb51566 | 29850 | case EF_ARM_EABI_VER4: |
3a4a14e9 | 29851 | case EF_ARM_EABI_VER5: |
c19d1205 | 29852 | /* No additional flags to set. */ |
d507cf36 PB |
29853 | break; |
29854 | ||
29855 | default: | |
29856 | abort (); | |
29857 | } | |
7cc69913 | 29858 | #endif |
b99bd4ef NC |
29859 | bfd_set_private_flags (stdoutput, flags); |
29860 | ||
29861 | /* We have run out flags in the COFF header to encode the | |
29862 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 29863 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
29864 | if (atpcs) |
29865 | { | |
29866 | asection * sec; | |
29867 | ||
29868 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
29869 | ||
29870 | if (sec != NULL) | |
29871 | { | |
29872 | bfd_set_section_flags | |
29873 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
29874 | bfd_set_section_size (stdoutput, sec, 0); | |
29875 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
29876 | } | |
29877 | } | |
7cc69913 | 29878 | } |
f17c130b | 29879 | #endif |
b99bd4ef NC |
29880 | |
29881 | /* Record the CPU type as well. */ | |
2d447fca JM |
29882 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) |
29883 | mach = bfd_mach_arm_iWMMXt2; | |
29884 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) | |
e16bb312 | 29885 | mach = bfd_mach_arm_iWMMXt; |
e74cfd16 | 29886 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
b99bd4ef | 29887 | mach = bfd_mach_arm_XScale; |
e74cfd16 | 29888 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
fde78edd | 29889 | mach = bfd_mach_arm_ep9312; |
e74cfd16 | 29890 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
b99bd4ef | 29891 | mach = bfd_mach_arm_5TE; |
e74cfd16 | 29892 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
b99bd4ef | 29893 | { |
e74cfd16 | 29894 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
29895 | mach = bfd_mach_arm_5T; |
29896 | else | |
29897 | mach = bfd_mach_arm_5; | |
29898 | } | |
e74cfd16 | 29899 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
b99bd4ef | 29900 | { |
e74cfd16 | 29901 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
29902 | mach = bfd_mach_arm_4T; |
29903 | else | |
29904 | mach = bfd_mach_arm_4; | |
29905 | } | |
e74cfd16 | 29906 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
b99bd4ef | 29907 | mach = bfd_mach_arm_3M; |
e74cfd16 PB |
29908 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
29909 | mach = bfd_mach_arm_3; | |
29910 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) | |
29911 | mach = bfd_mach_arm_2a; | |
29912 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) | |
29913 | mach = bfd_mach_arm_2; | |
29914 | else | |
29915 | mach = bfd_mach_arm_unknown; | |
b99bd4ef NC |
29916 | |
29917 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
29918 | } | |
29919 | ||
c19d1205 | 29920 | /* Command line processing. */ |
b99bd4ef | 29921 | |
c19d1205 ZW |
29922 | /* md_parse_option |
29923 | Invocation line includes a switch not recognized by the base assembler. | |
29924 | See if it's a processor-specific option. | |
b99bd4ef | 29925 | |
c19d1205 ZW |
29926 | This routine is somewhat complicated by the need for backwards |
29927 | compatibility (since older releases of gcc can't be changed). | |
29928 | The new options try to make the interface as compatible as | |
29929 | possible with GCC. | |
b99bd4ef | 29930 | |
c19d1205 | 29931 | New options (supported) are: |
b99bd4ef | 29932 | |
c19d1205 ZW |
29933 | -mcpu=<cpu name> Assemble for selected processor |
29934 | -march=<architecture name> Assemble for selected architecture | |
29935 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
29936 | -EB/-mbig-endian Big-endian | |
29937 | -EL/-mlittle-endian Little-endian | |
29938 | -k Generate PIC code | |
29939 | -mthumb Start in Thumb mode | |
29940 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 29941 | |
278df34e | 29942 | -m[no-]warn-deprecated Warn about deprecated features |
8b2d793c | 29943 | -m[no-]warn-syms Warn when symbols match instructions |
267bf995 | 29944 | |
c19d1205 | 29945 | For now we will also provide support for: |
b99bd4ef | 29946 | |
c19d1205 ZW |
29947 | -mapcs-32 32-bit Program counter |
29948 | -mapcs-26 26-bit Program counter | |
29949 | -macps-float Floats passed in FP registers | |
29950 | -mapcs-reentrant Reentrant code | |
29951 | -matpcs | |
29952 | (sometime these will probably be replaced with -mapcs=<list of options> | |
29953 | and -matpcs=<list of options>) | |
b99bd4ef | 29954 | |
c19d1205 ZW |
29955 | The remaining options are only supported for back-wards compatibility. |
29956 | Cpu variants, the arm part is optional: | |
29957 | -m[arm]1 Currently not supported. | |
29958 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
29959 | -m[arm]3 Arm 3 processor | |
29960 | -m[arm]6[xx], Arm 6 processors | |
29961 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
29962 | -m[arm]8[10] Arm 8 processors | |
29963 | -m[arm]9[20][tdmi] Arm 9 processors | |
29964 | -mstrongarm[110[0]] StrongARM processors | |
29965 | -mxscale XScale processors | |
29966 | -m[arm]v[2345[t[e]]] Arm architectures | |
29967 | -mall All (except the ARM1) | |
29968 | FP variants: | |
29969 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
29970 | -mfpe-old (No float load/store multiples) | |
29971 | -mvfpxd VFP Single precision | |
29972 | -mvfp All VFP | |
29973 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 29974 | |
c19d1205 ZW |
29975 | The following CPU names are recognized: |
29976 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
29977 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
29978 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
29979 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
29980 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
29981 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
29982 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 29983 | |
c19d1205 | 29984 | */ |
b99bd4ef | 29985 | |
c19d1205 | 29986 | const char * md_shortopts = "m:k"; |
b99bd4ef | 29987 | |
c19d1205 ZW |
29988 | #ifdef ARM_BI_ENDIAN |
29989 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
29990 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 29991 | #else |
c19d1205 ZW |
29992 | #if TARGET_BYTES_BIG_ENDIAN |
29993 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 29994 | #else |
c19d1205 ZW |
29995 | #define OPTION_EL (OPTION_MD_BASE + 1) |
29996 | #endif | |
b99bd4ef | 29997 | #endif |
845b51d6 | 29998 | #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2) |
18a20338 | 29999 | #define OPTION_FDPIC (OPTION_MD_BASE + 3) |
b99bd4ef | 30000 | |
c19d1205 | 30001 | struct option md_longopts[] = |
b99bd4ef | 30002 | { |
c19d1205 ZW |
30003 | #ifdef OPTION_EB |
30004 | {"EB", no_argument, NULL, OPTION_EB}, | |
30005 | #endif | |
30006 | #ifdef OPTION_EL | |
30007 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 30008 | #endif |
845b51d6 | 30009 | {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, |
18a20338 CL |
30010 | #ifdef OBJ_ELF |
30011 | {"fdpic", no_argument, NULL, OPTION_FDPIC}, | |
30012 | #endif | |
c19d1205 ZW |
30013 | {NULL, no_argument, NULL, 0} |
30014 | }; | |
b99bd4ef | 30015 | |
c19d1205 | 30016 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 30017 | |
c19d1205 | 30018 | struct arm_option_table |
b99bd4ef | 30019 | { |
0198d5e6 TC |
30020 | const char * option; /* Option name to match. */ |
30021 | const char * help; /* Help information. */ | |
30022 | int * var; /* Variable to change. */ | |
30023 | int value; /* What to change it to. */ | |
30024 | const char * deprecated; /* If non-null, print this message. */ | |
c19d1205 | 30025 | }; |
b99bd4ef | 30026 | |
c19d1205 ZW |
30027 | struct arm_option_table arm_opts[] = |
30028 | { | |
30029 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
30030 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
30031 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
30032 | &support_interwork, 1, NULL}, | |
30033 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
30034 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
30035 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
30036 | 1, NULL}, | |
30037 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
30038 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
30039 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
30040 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
30041 | NULL}, | |
b99bd4ef | 30042 | |
c19d1205 ZW |
30043 | /* These are recognized by the assembler, but have no affect on code. */ |
30044 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
30045 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
278df34e NS |
30046 | |
30047 | {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL}, | |
30048 | {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"), | |
30049 | &warn_on_deprecated, 0, NULL}, | |
8b2d793c NC |
30050 | {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL}, |
30051 | {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL}, | |
e74cfd16 PB |
30052 | {NULL, NULL, NULL, 0, NULL} |
30053 | }; | |
30054 | ||
30055 | struct arm_legacy_option_table | |
30056 | { | |
0198d5e6 TC |
30057 | const char * option; /* Option name to match. */ |
30058 | const arm_feature_set ** var; /* Variable to change. */ | |
30059 | const arm_feature_set value; /* What to change it to. */ | |
30060 | const char * deprecated; /* If non-null, print this message. */ | |
e74cfd16 | 30061 | }; |
b99bd4ef | 30062 | |
e74cfd16 PB |
30063 | const struct arm_legacy_option_table arm_legacy_opts[] = |
30064 | { | |
c19d1205 ZW |
30065 | /* DON'T add any new processors to this list -- we want the whole list |
30066 | to go away... Add them to the processors table instead. */ | |
e74cfd16 PB |
30067 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
30068 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
30069 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
30070 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
30071 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
30072 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
30073 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
30074 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
30075 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
30076 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
30077 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
30078 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
30079 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
30080 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
30081 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
30082 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
30083 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
30084 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
30085 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
30086 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
30087 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
30088 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
30089 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
30090 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
30091 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
30092 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
30093 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
30094 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
30095 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
30096 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
30097 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
30098 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
30099 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
30100 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
30101 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
30102 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
30103 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
30104 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
30105 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
30106 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
30107 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
30108 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
30109 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
30110 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
30111 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
30112 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
30113 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
30114 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
30115 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
30116 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
30117 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
30118 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
30119 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
30120 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
30121 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
30122 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
30123 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
30124 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
30125 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
30126 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
30127 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
30128 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
30129 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
30130 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
30131 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
30132 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
30133 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
30134 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
30135 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
30136 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, | |
c19d1205 | 30137 | N_("use -mcpu=strongarm110")}, |
e74cfd16 | 30138 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 30139 | N_("use -mcpu=strongarm1100")}, |
e74cfd16 | 30140 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 30141 | N_("use -mcpu=strongarm1110")}, |
e74cfd16 PB |
30142 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
30143 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
30144 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 30145 | |
c19d1205 | 30146 | /* Architecture variants -- don't add any more to this list either. */ |
e74cfd16 PB |
30147 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
30148 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
30149 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
30150 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
30151 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
30152 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
30153 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
30154 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
30155 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
30156 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
30157 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
30158 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
30159 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
30160 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
30161 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
30162 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
30163 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
30164 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 30165 | |
c19d1205 | 30166 | /* Floating point variants -- don't add any more to this list either. */ |
0198d5e6 TC |
30167 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
30168 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
30169 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
30170 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, | |
c19d1205 | 30171 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
7ed4c4c5 | 30172 | |
e74cfd16 | 30173 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
c19d1205 | 30174 | }; |
7ed4c4c5 | 30175 | |
c19d1205 | 30176 | struct arm_cpu_option_table |
7ed4c4c5 | 30177 | { |
0198d5e6 TC |
30178 | const char * name; |
30179 | size_t name_len; | |
30180 | const arm_feature_set value; | |
30181 | const arm_feature_set ext; | |
c19d1205 ZW |
30182 | /* For some CPUs we assume an FPU unless the user explicitly sets |
30183 | -mfpu=... */ | |
0198d5e6 | 30184 | const arm_feature_set default_fpu; |
ee065d83 PB |
30185 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
30186 | case. */ | |
0198d5e6 | 30187 | const char * canonical_name; |
c19d1205 | 30188 | }; |
7ed4c4c5 | 30189 | |
c19d1205 ZW |
30190 | /* This list should, at a minimum, contain all the cpu names |
30191 | recognized by GCC. */ | |
996b5569 | 30192 | #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN } |
0198d5e6 | 30193 | |
e74cfd16 | 30194 | static const struct arm_cpu_option_table arm_cpus[] = |
c19d1205 | 30195 | { |
996b5569 TP |
30196 | ARM_CPU_OPT ("all", NULL, ARM_ANY, |
30197 | ARM_ARCH_NONE, | |
30198 | FPU_ARCH_FPA), | |
30199 | ARM_CPU_OPT ("arm1", NULL, ARM_ARCH_V1, | |
30200 | ARM_ARCH_NONE, | |
30201 | FPU_ARCH_FPA), | |
30202 | ARM_CPU_OPT ("arm2", NULL, ARM_ARCH_V2, | |
30203 | ARM_ARCH_NONE, | |
30204 | FPU_ARCH_FPA), | |
30205 | ARM_CPU_OPT ("arm250", NULL, ARM_ARCH_V2S, | |
30206 | ARM_ARCH_NONE, | |
30207 | FPU_ARCH_FPA), | |
30208 | ARM_CPU_OPT ("arm3", NULL, ARM_ARCH_V2S, | |
30209 | ARM_ARCH_NONE, | |
30210 | FPU_ARCH_FPA), | |
30211 | ARM_CPU_OPT ("arm6", NULL, ARM_ARCH_V3, | |
30212 | ARM_ARCH_NONE, | |
30213 | FPU_ARCH_FPA), | |
30214 | ARM_CPU_OPT ("arm60", NULL, ARM_ARCH_V3, | |
30215 | ARM_ARCH_NONE, | |
30216 | FPU_ARCH_FPA), | |
30217 | ARM_CPU_OPT ("arm600", NULL, ARM_ARCH_V3, | |
30218 | ARM_ARCH_NONE, | |
30219 | FPU_ARCH_FPA), | |
30220 | ARM_CPU_OPT ("arm610", NULL, ARM_ARCH_V3, | |
30221 | ARM_ARCH_NONE, | |
30222 | FPU_ARCH_FPA), | |
30223 | ARM_CPU_OPT ("arm620", NULL, ARM_ARCH_V3, | |
30224 | ARM_ARCH_NONE, | |
30225 | FPU_ARCH_FPA), | |
30226 | ARM_CPU_OPT ("arm7", NULL, ARM_ARCH_V3, | |
30227 | ARM_ARCH_NONE, | |
30228 | FPU_ARCH_FPA), | |
30229 | ARM_CPU_OPT ("arm7m", NULL, ARM_ARCH_V3M, | |
30230 | ARM_ARCH_NONE, | |
30231 | FPU_ARCH_FPA), | |
30232 | ARM_CPU_OPT ("arm7d", NULL, ARM_ARCH_V3, | |
30233 | ARM_ARCH_NONE, | |
30234 | FPU_ARCH_FPA), | |
30235 | ARM_CPU_OPT ("arm7dm", NULL, ARM_ARCH_V3M, | |
30236 | ARM_ARCH_NONE, | |
30237 | FPU_ARCH_FPA), | |
30238 | ARM_CPU_OPT ("arm7di", NULL, ARM_ARCH_V3, | |
30239 | ARM_ARCH_NONE, | |
30240 | FPU_ARCH_FPA), | |
30241 | ARM_CPU_OPT ("arm7dmi", NULL, ARM_ARCH_V3M, | |
30242 | ARM_ARCH_NONE, | |
30243 | FPU_ARCH_FPA), | |
30244 | ARM_CPU_OPT ("arm70", NULL, ARM_ARCH_V3, | |
30245 | ARM_ARCH_NONE, | |
30246 | FPU_ARCH_FPA), | |
30247 | ARM_CPU_OPT ("arm700", NULL, ARM_ARCH_V3, | |
30248 | ARM_ARCH_NONE, | |
30249 | FPU_ARCH_FPA), | |
30250 | ARM_CPU_OPT ("arm700i", NULL, ARM_ARCH_V3, | |
30251 | ARM_ARCH_NONE, | |
30252 | FPU_ARCH_FPA), | |
30253 | ARM_CPU_OPT ("arm710", NULL, ARM_ARCH_V3, | |
30254 | ARM_ARCH_NONE, | |
30255 | FPU_ARCH_FPA), | |
30256 | ARM_CPU_OPT ("arm710t", NULL, ARM_ARCH_V4T, | |
30257 | ARM_ARCH_NONE, | |
30258 | FPU_ARCH_FPA), | |
30259 | ARM_CPU_OPT ("arm720", NULL, ARM_ARCH_V3, | |
30260 | ARM_ARCH_NONE, | |
30261 | FPU_ARCH_FPA), | |
30262 | ARM_CPU_OPT ("arm720t", NULL, ARM_ARCH_V4T, | |
30263 | ARM_ARCH_NONE, | |
30264 | FPU_ARCH_FPA), | |
30265 | ARM_CPU_OPT ("arm740t", NULL, ARM_ARCH_V4T, | |
30266 | ARM_ARCH_NONE, | |
30267 | FPU_ARCH_FPA), | |
30268 | ARM_CPU_OPT ("arm710c", NULL, ARM_ARCH_V3, | |
30269 | ARM_ARCH_NONE, | |
30270 | FPU_ARCH_FPA), | |
30271 | ARM_CPU_OPT ("arm7100", NULL, ARM_ARCH_V3, | |
30272 | ARM_ARCH_NONE, | |
30273 | FPU_ARCH_FPA), | |
30274 | ARM_CPU_OPT ("arm7500", NULL, ARM_ARCH_V3, | |
30275 | ARM_ARCH_NONE, | |
30276 | FPU_ARCH_FPA), | |
30277 | ARM_CPU_OPT ("arm7500fe", NULL, ARM_ARCH_V3, | |
30278 | ARM_ARCH_NONE, | |
30279 | FPU_ARCH_FPA), | |
30280 | ARM_CPU_OPT ("arm7t", NULL, ARM_ARCH_V4T, | |
30281 | ARM_ARCH_NONE, | |
30282 | FPU_ARCH_FPA), | |
30283 | ARM_CPU_OPT ("arm7tdmi", NULL, ARM_ARCH_V4T, | |
30284 | ARM_ARCH_NONE, | |
30285 | FPU_ARCH_FPA), | |
30286 | ARM_CPU_OPT ("arm7tdmi-s", NULL, ARM_ARCH_V4T, | |
30287 | ARM_ARCH_NONE, | |
30288 | FPU_ARCH_FPA), | |
30289 | ARM_CPU_OPT ("arm8", NULL, ARM_ARCH_V4, | |
30290 | ARM_ARCH_NONE, | |
30291 | FPU_ARCH_FPA), | |
30292 | ARM_CPU_OPT ("arm810", NULL, ARM_ARCH_V4, | |
30293 | ARM_ARCH_NONE, | |
30294 | FPU_ARCH_FPA), | |
30295 | ARM_CPU_OPT ("strongarm", NULL, ARM_ARCH_V4, | |
30296 | ARM_ARCH_NONE, | |
30297 | FPU_ARCH_FPA), | |
30298 | ARM_CPU_OPT ("strongarm1", NULL, ARM_ARCH_V4, | |
30299 | ARM_ARCH_NONE, | |
30300 | FPU_ARCH_FPA), | |
30301 | ARM_CPU_OPT ("strongarm110", NULL, ARM_ARCH_V4, | |
30302 | ARM_ARCH_NONE, | |
30303 | FPU_ARCH_FPA), | |
30304 | ARM_CPU_OPT ("strongarm1100", NULL, ARM_ARCH_V4, | |
30305 | ARM_ARCH_NONE, | |
30306 | FPU_ARCH_FPA), | |
30307 | ARM_CPU_OPT ("strongarm1110", NULL, ARM_ARCH_V4, | |
30308 | ARM_ARCH_NONE, | |
30309 | FPU_ARCH_FPA), | |
30310 | ARM_CPU_OPT ("arm9", NULL, ARM_ARCH_V4T, | |
30311 | ARM_ARCH_NONE, | |
30312 | FPU_ARCH_FPA), | |
30313 | ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T, | |
30314 | ARM_ARCH_NONE, | |
30315 | FPU_ARCH_FPA), | |
30316 | ARM_CPU_OPT ("arm920t", NULL, ARM_ARCH_V4T, | |
30317 | ARM_ARCH_NONE, | |
30318 | FPU_ARCH_FPA), | |
30319 | ARM_CPU_OPT ("arm922t", NULL, ARM_ARCH_V4T, | |
30320 | ARM_ARCH_NONE, | |
30321 | FPU_ARCH_FPA), | |
30322 | ARM_CPU_OPT ("arm940t", NULL, ARM_ARCH_V4T, | |
30323 | ARM_ARCH_NONE, | |
30324 | FPU_ARCH_FPA), | |
30325 | ARM_CPU_OPT ("arm9tdmi", NULL, ARM_ARCH_V4T, | |
30326 | ARM_ARCH_NONE, | |
30327 | FPU_ARCH_FPA), | |
30328 | ARM_CPU_OPT ("fa526", NULL, ARM_ARCH_V4, | |
30329 | ARM_ARCH_NONE, | |
30330 | FPU_ARCH_FPA), | |
30331 | ARM_CPU_OPT ("fa626", NULL, ARM_ARCH_V4, | |
30332 | ARM_ARCH_NONE, | |
30333 | FPU_ARCH_FPA), | |
30334 | ||
c19d1205 ZW |
30335 | /* For V5 or later processors we default to using VFP; but the user |
30336 | should really set the FPU type explicitly. */ | |
996b5569 TP |
30337 | ARM_CPU_OPT ("arm9e-r0", NULL, ARM_ARCH_V5TExP, |
30338 | ARM_ARCH_NONE, | |
30339 | FPU_ARCH_VFP_V2), | |
30340 | ARM_CPU_OPT ("arm9e", NULL, ARM_ARCH_V5TE, | |
30341 | ARM_ARCH_NONE, | |
30342 | FPU_ARCH_VFP_V2), | |
30343 | ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ, | |
30344 | ARM_ARCH_NONE, | |
30345 | FPU_ARCH_VFP_V2), | |
30346 | ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ, | |
30347 | ARM_ARCH_NONE, | |
30348 | FPU_ARCH_VFP_V2), | |
30349 | ARM_CPU_OPT ("arm926ej-s", NULL, ARM_ARCH_V5TEJ, | |
30350 | ARM_ARCH_NONE, | |
30351 | FPU_ARCH_VFP_V2), | |
30352 | ARM_CPU_OPT ("arm946e-r0", NULL, ARM_ARCH_V5TExP, | |
30353 | ARM_ARCH_NONE, | |
30354 | FPU_ARCH_VFP_V2), | |
30355 | ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE, | |
30356 | ARM_ARCH_NONE, | |
30357 | FPU_ARCH_VFP_V2), | |
30358 | ARM_CPU_OPT ("arm946e-s", NULL, ARM_ARCH_V5TE, | |
30359 | ARM_ARCH_NONE, | |
30360 | FPU_ARCH_VFP_V2), | |
30361 | ARM_CPU_OPT ("arm966e-r0", NULL, ARM_ARCH_V5TExP, | |
30362 | ARM_ARCH_NONE, | |
30363 | FPU_ARCH_VFP_V2), | |
30364 | ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE, | |
30365 | ARM_ARCH_NONE, | |
30366 | FPU_ARCH_VFP_V2), | |
30367 | ARM_CPU_OPT ("arm966e-s", NULL, ARM_ARCH_V5TE, | |
30368 | ARM_ARCH_NONE, | |
30369 | FPU_ARCH_VFP_V2), | |
30370 | ARM_CPU_OPT ("arm968e-s", NULL, ARM_ARCH_V5TE, | |
30371 | ARM_ARCH_NONE, | |
30372 | FPU_ARCH_VFP_V2), | |
30373 | ARM_CPU_OPT ("arm10t", NULL, ARM_ARCH_V5T, | |
30374 | ARM_ARCH_NONE, | |
30375 | FPU_ARCH_VFP_V1), | |
30376 | ARM_CPU_OPT ("arm10tdmi", NULL, ARM_ARCH_V5T, | |
30377 | ARM_ARCH_NONE, | |
30378 | FPU_ARCH_VFP_V1), | |
30379 | ARM_CPU_OPT ("arm10e", NULL, ARM_ARCH_V5TE, | |
30380 | ARM_ARCH_NONE, | |
30381 | FPU_ARCH_VFP_V2), | |
30382 | ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE, | |
30383 | ARM_ARCH_NONE, | |
30384 | FPU_ARCH_VFP_V2), | |
30385 | ARM_CPU_OPT ("arm1020t", NULL, ARM_ARCH_V5T, | |
30386 | ARM_ARCH_NONE, | |
30387 | FPU_ARCH_VFP_V1), | |
30388 | ARM_CPU_OPT ("arm1020e", NULL, ARM_ARCH_V5TE, | |
30389 | ARM_ARCH_NONE, | |
30390 | FPU_ARCH_VFP_V2), | |
30391 | ARM_CPU_OPT ("arm1022e", NULL, ARM_ARCH_V5TE, | |
30392 | ARM_ARCH_NONE, | |
30393 | FPU_ARCH_VFP_V2), | |
30394 | ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ, | |
30395 | ARM_ARCH_NONE, | |
30396 | FPU_ARCH_VFP_V2), | |
30397 | ARM_CPU_OPT ("arm1026ej-s", NULL, ARM_ARCH_V5TEJ, | |
30398 | ARM_ARCH_NONE, | |
30399 | FPU_ARCH_VFP_V2), | |
30400 | ARM_CPU_OPT ("fa606te", NULL, ARM_ARCH_V5TE, | |
30401 | ARM_ARCH_NONE, | |
30402 | FPU_ARCH_VFP_V2), | |
30403 | ARM_CPU_OPT ("fa616te", NULL, ARM_ARCH_V5TE, | |
30404 | ARM_ARCH_NONE, | |
30405 | FPU_ARCH_VFP_V2), | |
30406 | ARM_CPU_OPT ("fa626te", NULL, ARM_ARCH_V5TE, | |
30407 | ARM_ARCH_NONE, | |
30408 | FPU_ARCH_VFP_V2), | |
30409 | ARM_CPU_OPT ("fmp626", NULL, ARM_ARCH_V5TE, | |
30410 | ARM_ARCH_NONE, | |
30411 | FPU_ARCH_VFP_V2), | |
30412 | ARM_CPU_OPT ("fa726te", NULL, ARM_ARCH_V5TE, | |
30413 | ARM_ARCH_NONE, | |
30414 | FPU_ARCH_VFP_V2), | |
30415 | ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6, | |
30416 | ARM_ARCH_NONE, | |
30417 | FPU_NONE), | |
30418 | ARM_CPU_OPT ("arm1136j-s", NULL, ARM_ARCH_V6, | |
30419 | ARM_ARCH_NONE, | |
30420 | FPU_NONE), | |
30421 | ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6, | |
30422 | ARM_ARCH_NONE, | |
30423 | FPU_ARCH_VFP_V2), | |
30424 | ARM_CPU_OPT ("arm1136jf-s", NULL, ARM_ARCH_V6, | |
30425 | ARM_ARCH_NONE, | |
30426 | FPU_ARCH_VFP_V2), | |
30427 | ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K, | |
30428 | ARM_ARCH_NONE, | |
30429 | FPU_ARCH_VFP_V2), | |
30430 | ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K, | |
30431 | ARM_ARCH_NONE, | |
30432 | FPU_NONE), | |
30433 | ARM_CPU_OPT ("arm1156t2-s", NULL, ARM_ARCH_V6T2, | |
30434 | ARM_ARCH_NONE, | |
30435 | FPU_NONE), | |
30436 | ARM_CPU_OPT ("arm1156t2f-s", NULL, ARM_ARCH_V6T2, | |
30437 | ARM_ARCH_NONE, | |
30438 | FPU_ARCH_VFP_V2), | |
30439 | ARM_CPU_OPT ("arm1176jz-s", NULL, ARM_ARCH_V6KZ, | |
30440 | ARM_ARCH_NONE, | |
30441 | FPU_NONE), | |
30442 | ARM_CPU_OPT ("arm1176jzf-s", NULL, ARM_ARCH_V6KZ, | |
30443 | ARM_ARCH_NONE, | |
30444 | FPU_ARCH_VFP_V2), | |
30445 | ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A, | |
30446 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), | |
30447 | FPU_NONE), | |
30448 | ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE, | |
30449 | ARM_ARCH_NONE, | |
30450 | FPU_ARCH_NEON_VFP_V4), | |
30451 | ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A, | |
30452 | ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), | |
30453 | ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)), | |
30454 | ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A, | |
30455 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), | |
30456 | ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)), | |
30457 | ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE, | |
30458 | ARM_ARCH_NONE, | |
30459 | FPU_ARCH_NEON_VFP_V4), | |
30460 | ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE, | |
30461 | ARM_ARCH_NONE, | |
30462 | FPU_ARCH_NEON_VFP_V4), | |
30463 | ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE, | |
30464 | ARM_ARCH_NONE, | |
30465 | FPU_ARCH_NEON_VFP_V4), | |
30466 | ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A, | |
30467 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
30468 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
30469 | ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A, | |
30470 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
30471 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
30472 | ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A, | |
30473 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
30474 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
15a7695f JG |
30475 | ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A, |
30476 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), | |
0198d5e6 | 30477 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), |
996b5569 TP |
30478 | ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A, |
30479 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
30480 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
30481 | ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A, | |
30482 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
30483 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
30484 | ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A, | |
30485 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
30486 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
15a7695f JG |
30487 | ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A, |
30488 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), | |
0198d5e6 | 30489 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), |
7ebd1359 | 30490 | ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A, |
30491 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), | |
30492 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), | |
ef8df4ca KT |
30493 | ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A, |
30494 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), | |
30495 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), | |
996b5569 TP |
30496 | ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R, |
30497 | ARM_ARCH_NONE, | |
30498 | FPU_NONE), | |
30499 | ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R, | |
30500 | ARM_ARCH_NONE, | |
30501 | FPU_ARCH_VFP_V3D16), | |
30502 | ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R, | |
30503 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), | |
30504 | FPU_NONE), | |
30505 | ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R, | |
30506 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), | |
30507 | FPU_ARCH_VFP_V3D16), | |
30508 | ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R, | |
30509 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), | |
30510 | FPU_ARCH_VFP_V3D16), | |
0cda1e19 TP |
30511 | ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R, |
30512 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
30513 | FPU_ARCH_NEON_VFP_ARMV8), | |
996b5569 TP |
30514 | ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN, |
30515 | ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), | |
30516 | FPU_NONE), | |
30517 | ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE, | |
30518 | ARM_ARCH_NONE, | |
30519 | FPU_NONE), | |
30520 | ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM, | |
30521 | ARM_ARCH_NONE, | |
30522 | FPU_NONE), | |
30523 | ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM, | |
30524 | ARM_ARCH_NONE, | |
30525 | FPU_NONE), | |
30526 | ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M, | |
30527 | ARM_ARCH_NONE, | |
30528 | FPU_NONE), | |
30529 | ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM, | |
30530 | ARM_ARCH_NONE, | |
30531 | FPU_NONE), | |
30532 | ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM, | |
30533 | ARM_ARCH_NONE, | |
30534 | FPU_NONE), | |
30535 | ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM, | |
30536 | ARM_ARCH_NONE, | |
30537 | FPU_NONE), | |
30538 | ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A, | |
30539 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
30540 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
83f43c83 KT |
30541 | ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A, |
30542 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), | |
30543 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), | |
c19d1205 | 30544 | /* ??? XSCALE is really an architecture. */ |
996b5569 TP |
30545 | ARM_CPU_OPT ("xscale", NULL, ARM_ARCH_XSCALE, |
30546 | ARM_ARCH_NONE, | |
30547 | FPU_ARCH_VFP_V2), | |
30548 | ||
c19d1205 | 30549 | /* ??? iwmmxt is not a processor. */ |
996b5569 TP |
30550 | ARM_CPU_OPT ("iwmmxt", NULL, ARM_ARCH_IWMMXT, |
30551 | ARM_ARCH_NONE, | |
30552 | FPU_ARCH_VFP_V2), | |
30553 | ARM_CPU_OPT ("iwmmxt2", NULL, ARM_ARCH_IWMMXT2, | |
30554 | ARM_ARCH_NONE, | |
30555 | FPU_ARCH_VFP_V2), | |
30556 | ARM_CPU_OPT ("i80200", NULL, ARM_ARCH_XSCALE, | |
30557 | ARM_ARCH_NONE, | |
30558 | FPU_ARCH_VFP_V2), | |
30559 | ||
0198d5e6 | 30560 | /* Maverick. */ |
996b5569 TP |
30561 | ARM_CPU_OPT ("ep9312", "ARM920T", |
30562 | ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), | |
30563 | ARM_ARCH_NONE, FPU_ARCH_MAVERICK), | |
30564 | ||
da4339ed | 30565 | /* Marvell processors. */ |
996b5569 TP |
30566 | ARM_CPU_OPT ("marvell-pj4", NULL, ARM_ARCH_V7A, |
30567 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), | |
30568 | FPU_ARCH_VFP_V3D16), | |
30569 | ARM_CPU_OPT ("marvell-whitney", NULL, ARM_ARCH_V7A, | |
30570 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), | |
30571 | FPU_ARCH_NEON_VFP_V4), | |
da4339ed | 30572 | |
996b5569 TP |
30573 | /* APM X-Gene family. */ |
30574 | ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A, | |
30575 | ARM_ARCH_NONE, | |
30576 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
30577 | ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A, | |
30578 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
30579 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
30580 | ||
30581 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL } | |
c19d1205 | 30582 | }; |
f3bad469 | 30583 | #undef ARM_CPU_OPT |
7ed4c4c5 | 30584 | |
34ef62f4 AV |
30585 | struct arm_ext_table |
30586 | { | |
30587 | const char * name; | |
30588 | size_t name_len; | |
30589 | const arm_feature_set merge; | |
30590 | const arm_feature_set clear; | |
30591 | }; | |
30592 | ||
c19d1205 | 30593 | struct arm_arch_option_table |
7ed4c4c5 | 30594 | { |
34ef62f4 AV |
30595 | const char * name; |
30596 | size_t name_len; | |
30597 | const arm_feature_set value; | |
30598 | const arm_feature_set default_fpu; | |
30599 | const struct arm_ext_table * ext_table; | |
30600 | }; | |
30601 | ||
30602 | /* Used to add support for +E and +noE extension. */ | |
30603 | #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C } | |
30604 | /* Used to add support for a +E extension. */ | |
30605 | #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE } | |
30606 | /* Used to add support for a +noE extension. */ | |
30607 | #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C } | |
30608 | ||
30609 | #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \ | |
30610 | ~0 & ~FPU_ENDIAN_PURE) | |
30611 | ||
30612 | static const struct arm_ext_table armv5te_ext_table[] = | |
30613 | { | |
30614 | ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP), | |
30615 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30616 | }; | |
30617 | ||
30618 | static const struct arm_ext_table armv7_ext_table[] = | |
30619 | { | |
30620 | ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP), | |
30621 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30622 | }; | |
30623 | ||
30624 | static const struct arm_ext_table armv7ve_ext_table[] = | |
30625 | { | |
30626 | ARM_EXT ("fp", FPU_ARCH_VFP_V4D16, ALL_FP), | |
30627 | ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), | |
30628 | ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3), | |
30629 | ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16), | |
30630 | ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16), | |
30631 | ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16), /* Alias for +fp. */ | |
30632 | ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4), | |
30633 | ||
30634 | ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4, | |
30635 | ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)), | |
30636 | ||
30637 | /* Aliases for +simd. */ | |
30638 | ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4), | |
30639 | ||
30640 | ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1), | |
30641 | ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1), | |
30642 | ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16), | |
30643 | ||
30644 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30645 | }; | |
30646 | ||
30647 | static const struct arm_ext_table armv7a_ext_table[] = | |
30648 | { | |
30649 | ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP), | |
30650 | ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */ | |
30651 | ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3), | |
30652 | ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16), | |
30653 | ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16), | |
30654 | ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16), | |
30655 | ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4), | |
30656 | ||
30657 | ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1, | |
30658 | ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)), | |
30659 | ||
30660 | /* Aliases for +simd. */ | |
30661 | ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1), | |
30662 | ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1), | |
30663 | ||
30664 | ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16), | |
30665 | ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4), | |
30666 | ||
30667 | ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP)), | |
30668 | ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC)), | |
30669 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30670 | }; | |
30671 | ||
30672 | static const struct arm_ext_table armv7r_ext_table[] = | |
30673 | { | |
30674 | ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD), | |
30675 | ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD), /* Alias for +fp.sp. */ | |
30676 | ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP), | |
30677 | ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */ | |
30678 | ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16), | |
30679 | ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16), | |
30680 | ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV), | |
30681 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV)), | |
30682 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30683 | }; | |
30684 | ||
30685 | static const struct arm_ext_table armv7em_ext_table[] = | |
30686 | { | |
30687 | ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16, ALL_FP), | |
30688 | /* Alias for +fp, used to be known as fpv4-sp-d16. */ | |
30689 | ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16), | |
30690 | ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16), | |
30691 | ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16), | |
30692 | ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16), | |
30693 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30694 | }; | |
30695 | ||
30696 | static const struct arm_ext_table armv8a_ext_table[] = | |
30697 | { | |
30698 | ARM_ADD ("crc", ARCH_CRC_ARMV8), | |
30699 | ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8), | |
30700 | ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, | |
30701 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)), | |
30702 | ||
30703 | /* Armv8-a does not allow an FP implementation without SIMD, so the user | |
30704 | should use the +simd option to turn on FP. */ | |
30705 | ARM_REMOVE ("fp", ALL_FP), | |
30706 | ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)), | |
30707 | ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)), | |
30708 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30709 | }; | |
30710 | ||
30711 | ||
30712 | static const struct arm_ext_table armv81a_ext_table[] = | |
30713 | { | |
30714 | ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1), | |
30715 | ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1, | |
30716 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)), | |
30717 | ||
30718 | /* Armv8-a does not allow an FP implementation without SIMD, so the user | |
30719 | should use the +simd option to turn on FP. */ | |
30720 | ARM_REMOVE ("fp", ALL_FP), | |
30721 | ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)), | |
30722 | ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)), | |
30723 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30724 | }; | |
30725 | ||
30726 | static const struct arm_ext_table armv82a_ext_table[] = | |
30727 | { | |
30728 | ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1), | |
30729 | ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16), | |
30730 | ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML), | |
30731 | ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1, | |
30732 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)), | |
30733 | ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8), | |
30734 | ||
30735 | /* Armv8-a does not allow an FP implementation without SIMD, so the user | |
30736 | should use the +simd option to turn on FP. */ | |
30737 | ARM_REMOVE ("fp", ALL_FP), | |
30738 | ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)), | |
30739 | ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)), | |
30740 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30741 | }; | |
30742 | ||
30743 | static const struct arm_ext_table armv84a_ext_table[] = | |
30744 | { | |
30745 | ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8), | |
30746 | ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML), | |
30747 | ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4, | |
30748 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)), | |
30749 | ||
30750 | /* Armv8-a does not allow an FP implementation without SIMD, so the user | |
30751 | should use the +simd option to turn on FP. */ | |
30752 | ARM_REMOVE ("fp", ALL_FP), | |
30753 | ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)), | |
30754 | ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)), | |
30755 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30756 | }; | |
30757 | ||
30758 | static const struct arm_ext_table armv85a_ext_table[] = | |
30759 | { | |
30760 | ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8), | |
30761 | ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML), | |
30762 | ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4, | |
30763 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)), | |
30764 | ||
30765 | /* Armv8-a does not allow an FP implementation without SIMD, so the user | |
30766 | should use the +simd option to turn on FP. */ | |
30767 | ARM_REMOVE ("fp", ALL_FP), | |
30768 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30769 | }; | |
30770 | ||
30771 | static const struct arm_ext_table armv8m_main_ext_table[] = | |
30772 | { | |
30773 | ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), | |
30774 | ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)), | |
30775 | ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16, ALL_FP), | |
30776 | ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16), | |
30777 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30778 | }; | |
30779 | ||
e0991585 AV |
30780 | static const struct arm_ext_table armv8_1m_main_ext_table[] = |
30781 | { | |
30782 | ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), | |
30783 | ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)), | |
30784 | ARM_EXT ("fp", | |
30785 | ARM_FEATURE (0, ARM_EXT2_FP16_INST, | |
30786 | FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA), | |
30787 | ALL_FP), | |
30788 | ARM_ADD ("fp.dp", | |
30789 | ARM_FEATURE (0, ARM_EXT2_FP16_INST, | |
30790 | FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)), | |
a7ad558c AV |
30791 | ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE), |
30792 | ARM_FEATURE_COPROC (FPU_MVE | FPU_MVE_FP)), | |
30793 | ARM_ADD ("mve.fp", | |
30794 | ARM_FEATURE (0, ARM_EXT2_FP16_INST, | |
30795 | FPU_MVE | FPU_MVE_FP | FPU_VFP_V5_SP_D16 | | |
30796 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)), | |
e0991585 AV |
30797 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } |
30798 | }; | |
30799 | ||
34ef62f4 AV |
30800 | static const struct arm_ext_table armv8r_ext_table[] = |
30801 | { | |
30802 | ARM_ADD ("crc", ARCH_CRC_ARMV8), | |
30803 | ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8), | |
30804 | ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, | |
30805 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)), | |
30806 | ARM_REMOVE ("fp", ALL_FP), | |
30807 | ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16), | |
30808 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
c19d1205 | 30809 | }; |
7ed4c4c5 | 30810 | |
c19d1205 ZW |
30811 | /* This list should, at a minimum, contain all the architecture names |
30812 | recognized by GCC. */ | |
34ef62f4 AV |
30813 | #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL } |
30814 | #define ARM_ARCH_OPT2(N, V, DF, ext) \ | |
30815 | { N, sizeof (N) - 1, V, DF, ext##_ext_table } | |
0198d5e6 | 30816 | |
e74cfd16 | 30817 | static const struct arm_arch_option_table arm_archs[] = |
c19d1205 | 30818 | { |
497d849d TP |
30819 | ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA), |
30820 | ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA), | |
30821 | ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA), | |
30822 | ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
30823 | ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
30824 | ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA), | |
30825 | ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA), | |
30826 | ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA), | |
30827 | ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA), | |
30828 | ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA), | |
30829 | ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA), | |
30830 | ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP), | |
30831 | ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP), | |
30832 | ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP), | |
34ef62f4 AV |
30833 | ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP, armv5te), |
30834 | ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP, armv5te), | |
30835 | ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP, armv5te), | |
30836 | ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te), | |
30837 | ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te), | |
30838 | ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP, armv5te), | |
30839 | ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP, armv5te), | |
f33026a9 MW |
30840 | /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is |
30841 | kept to preserve existing behaviour. */ | |
34ef62f4 AV |
30842 | ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te), |
30843 | ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te), | |
30844 | ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP, armv5te), | |
30845 | ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP, armv5te), | |
30846 | ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP, armv5te), | |
f33026a9 MW |
30847 | /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is |
30848 | kept to preserve existing behaviour. */ | |
34ef62f4 AV |
30849 | ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te), |
30850 | ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te), | |
497d849d TP |
30851 | ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP), |
30852 | ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP), | |
34ef62f4 | 30853 | ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP, armv7), |
c450d570 PB |
30854 | /* The official spelling of the ARMv7 profile variants is the dashed form. |
30855 | Accept the non-dashed form for compatibility with old toolchains. */ | |
34ef62f4 AV |
30856 | ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a), |
30857 | ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP, armv7ve), | |
30858 | ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r), | |
497d849d | 30859 | ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP), |
34ef62f4 AV |
30860 | ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a), |
30861 | ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r), | |
497d849d | 30862 | ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP), |
34ef62f4 | 30863 | ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP, armv7em), |
497d849d | 30864 | ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP), |
34ef62f4 AV |
30865 | ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP, |
30866 | armv8m_main), | |
e0991585 AV |
30867 | ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN, FPU_ARCH_VFP, |
30868 | armv8_1m_main), | |
34ef62f4 AV |
30869 | ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP, armv8a), |
30870 | ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP, armv81a), | |
30871 | ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP, armv82a), | |
30872 | ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A, FPU_ARCH_VFP, armv82a), | |
30873 | ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R, FPU_ARCH_VFP, armv8r), | |
30874 | ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A, FPU_ARCH_VFP, armv84a), | |
30875 | ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A, FPU_ARCH_VFP, armv85a), | |
497d849d TP |
30876 | ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP), |
30877 | ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP), | |
30878 | ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2, FPU_ARCH_VFP), | |
34ef62f4 | 30879 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL } |
c19d1205 | 30880 | }; |
f3bad469 | 30881 | #undef ARM_ARCH_OPT |
7ed4c4c5 | 30882 | |
69133863 | 30883 | /* ISA extensions in the co-processor and main instruction set space. */ |
0198d5e6 | 30884 | |
69133863 | 30885 | struct arm_option_extension_value_table |
c19d1205 | 30886 | { |
0198d5e6 TC |
30887 | const char * name; |
30888 | size_t name_len; | |
30889 | const arm_feature_set merge_value; | |
30890 | const arm_feature_set clear_value; | |
d942732e TP |
30891 | /* List of architectures for which an extension is available. ARM_ARCH_NONE |
30892 | indicates that an extension is available for all architectures while | |
30893 | ARM_ANY marks an empty entry. */ | |
0198d5e6 | 30894 | const arm_feature_set allowed_archs[2]; |
c19d1205 | 30895 | }; |
7ed4c4c5 | 30896 | |
0198d5e6 TC |
30897 | /* The following table must be in alphabetical order with a NULL last entry. */ |
30898 | ||
d942732e TP |
30899 | #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } } |
30900 | #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} } | |
0198d5e6 | 30901 | |
34ef62f4 AV |
30902 | /* DEPRECATED: Refrain from using this table to add any new extensions, instead |
30903 | use the context sensitive approach using arm_ext_table's. */ | |
69133863 | 30904 | static const struct arm_option_extension_value_table arm_extensions[] = |
c19d1205 | 30905 | { |
823d2571 TG |
30906 | ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8), |
30907 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
bca38921 | 30908 | ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
823d2571 TG |
30909 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8), |
30910 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
c604a79a JW |
30911 | ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8, |
30912 | ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), | |
30913 | ARM_ARCH_V8_2A), | |
15afaa63 TP |
30914 | ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), |
30915 | ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), | |
30916 | ARM_FEATURE_CORE (ARM_EXT_V7M, ARM_EXT2_V8M)), | |
823d2571 TG |
30917 | ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8), |
30918 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
b8ec4e87 JW |
30919 | ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
30920 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), | |
30921 | ARM_ARCH_V8_2A), | |
01f48020 TC |
30922 | ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST |
30923 | | ARM_EXT2_FP16_FML), | |
30924 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | |
30925 | | ARM_EXT2_FP16_FML), | |
30926 | ARM_ARCH_V8_2A), | |
d942732e | 30927 | ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV), |
823d2571 | 30928 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV), |
d942732e TP |
30929 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A), |
30930 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)), | |
3d030cdb TP |
30931 | /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of |
30932 | Thumb divide instruction. Due to this having the same name as the | |
30933 | previous entry, this will be ignored when doing command-line parsing and | |
30934 | only considered by build attribute selection code. */ | |
30935 | ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), | |
30936 | ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), | |
30937 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7)), | |
823d2571 | 30938 | ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), |
d942732e | 30939 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ARCH_NONE), |
823d2571 | 30940 | ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), |
d942732e | 30941 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ARCH_NONE), |
823d2571 | 30942 | ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), |
d942732e TP |
30943 | ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ARCH_NONE), |
30944 | ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP), | |
823d2571 | 30945 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP), |
d942732e TP |
30946 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A), |
30947 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)), | |
823d2571 TG |
30948 | ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS), |
30949 | ARM_FEATURE_CORE_LOW (ARM_EXT_OS), | |
30950 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)), | |
ddfded2f MW |
30951 | ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), |
30952 | ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0), | |
ced40572 | 30953 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)), |
dad0c3bf SD |
30954 | ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES), |
30955 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES), | |
30956 | ARM_ARCH_V8A), | |
4d1464f2 MW |
30957 | ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), |
30958 | ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0), | |
ced40572 | 30959 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)), |
643afb90 MW |
30960 | ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1, |
30961 | ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA), | |
ced40572 | 30962 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)), |
7fadb25d SD |
30963 | ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), |
30964 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), | |
30965 | ARM_ARCH_V8A), | |
d942732e | 30966 | ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), |
823d2571 | 30967 | ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), |
d942732e TP |
30968 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), |
30969 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)), | |
643afb90 MW |
30970 | ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8, |
30971 | ARM_FEATURE_COPROC (FPU_NEON_ARMV8), | |
30972 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
823d2571 TG |
30973 | ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV |
30974 | | ARM_EXT_DIV), | |
30975 | ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), | |
30976 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)), | |
30977 | ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), | |
d942732e TP |
30978 | ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ARCH_NONE), |
30979 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, { ARM_ARCH_NONE, ARM_ARCH_NONE } } | |
69133863 | 30980 | }; |
f3bad469 | 30981 | #undef ARM_EXT_OPT |
69133863 MGD |
30982 | |
30983 | /* ISA floating-point and Advanced SIMD extensions. */ | |
30984 | struct arm_option_fpu_value_table | |
30985 | { | |
0198d5e6 TC |
30986 | const char * name; |
30987 | const arm_feature_set value; | |
c19d1205 | 30988 | }; |
7ed4c4c5 | 30989 | |
c19d1205 ZW |
30990 | /* This list should, at a minimum, contain all the fpu names |
30991 | recognized by GCC. */ | |
69133863 | 30992 | static const struct arm_option_fpu_value_table arm_fpus[] = |
c19d1205 ZW |
30993 | { |
30994 | {"softfpa", FPU_NONE}, | |
30995 | {"fpe", FPU_ARCH_FPE}, | |
30996 | {"fpe2", FPU_ARCH_FPE}, | |
30997 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
30998 | {"fpa", FPU_ARCH_FPA}, | |
30999 | {"fpa10", FPU_ARCH_FPA}, | |
31000 | {"fpa11", FPU_ARCH_FPA}, | |
31001 | {"arm7500fe", FPU_ARCH_FPA}, | |
31002 | {"softvfp", FPU_ARCH_VFP}, | |
31003 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
31004 | {"vfp", FPU_ARCH_VFP_V2}, | |
31005 | {"vfp9", FPU_ARCH_VFP_V2}, | |
d5e0ba9c | 31006 | {"vfp3", FPU_ARCH_VFP_V3}, /* Undocumented, use vfpv3. */ |
c19d1205 ZW |
31007 | {"vfp10", FPU_ARCH_VFP_V2}, |
31008 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
31009 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
b1cc4aeb PB |
31010 | {"vfpv2", FPU_ARCH_VFP_V2}, |
31011 | {"vfpv3", FPU_ARCH_VFP_V3}, | |
62f3b8c8 | 31012 | {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16}, |
b1cc4aeb | 31013 | {"vfpv3-d16", FPU_ARCH_VFP_V3D16}, |
62f3b8c8 PB |
31014 | {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16}, |
31015 | {"vfpv3xd", FPU_ARCH_VFP_V3xD}, | |
31016 | {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16}, | |
c19d1205 ZW |
31017 | {"arm1020t", FPU_ARCH_VFP_V1}, |
31018 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
d5e0ba9c | 31019 | {"arm1136jfs", FPU_ARCH_VFP_V2}, /* Undocumented, use arm1136jf-s. */ |
c19d1205 ZW |
31020 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, |
31021 | {"maverick", FPU_ARCH_MAVERICK}, | |
d5e0ba9c | 31022 | {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
d3375ddd | 31023 | {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
8e79c3df | 31024 | {"neon-fp16", FPU_ARCH_NEON_FP16}, |
62f3b8c8 PB |
31025 | {"vfpv4", FPU_ARCH_VFP_V4}, |
31026 | {"vfpv4-d16", FPU_ARCH_VFP_V4D16}, | |
ada65aa3 | 31027 | {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16}, |
a715796b TG |
31028 | {"fpv5-d16", FPU_ARCH_VFP_V5D16}, |
31029 | {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16}, | |
62f3b8c8 | 31030 | {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4}, |
bca38921 MGD |
31031 | {"fp-armv8", FPU_ARCH_VFP_ARMV8}, |
31032 | {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8}, | |
31033 | {"crypto-neon-fp-armv8", | |
31034 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8}, | |
d6b4b13e | 31035 | {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1}, |
081e4c7d MW |
31036 | {"crypto-neon-fp-armv8.1", |
31037 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1}, | |
e74cfd16 PB |
31038 | {NULL, ARM_ARCH_NONE} |
31039 | }; | |
31040 | ||
31041 | struct arm_option_value_table | |
31042 | { | |
e0471c16 | 31043 | const char *name; |
e74cfd16 | 31044 | long value; |
c19d1205 | 31045 | }; |
7ed4c4c5 | 31046 | |
e74cfd16 | 31047 | static const struct arm_option_value_table arm_float_abis[] = |
c19d1205 ZW |
31048 | { |
31049 | {"hard", ARM_FLOAT_ABI_HARD}, | |
31050 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
31051 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
e74cfd16 | 31052 | {NULL, 0} |
c19d1205 | 31053 | }; |
7ed4c4c5 | 31054 | |
c19d1205 | 31055 | #ifdef OBJ_ELF |
3a4a14e9 | 31056 | /* We only know how to output GNU and ver 4/5 (AAELF) formats. */ |
e74cfd16 | 31057 | static const struct arm_option_value_table arm_eabis[] = |
c19d1205 ZW |
31058 | { |
31059 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
31060 | {"4", EF_ARM_EABI_VER4}, | |
3a4a14e9 | 31061 | {"5", EF_ARM_EABI_VER5}, |
e74cfd16 | 31062 | {NULL, 0} |
c19d1205 ZW |
31063 | }; |
31064 | #endif | |
7ed4c4c5 | 31065 | |
c19d1205 ZW |
31066 | struct arm_long_option_table |
31067 | { | |
0198d5e6 | 31068 | const char * option; /* Substring to match. */ |
e0471c16 | 31069 | const char * help; /* Help information. */ |
17b9d67d | 31070 | int (* func) (const char * subopt); /* Function to decode sub-option. */ |
e0471c16 | 31071 | const char * deprecated; /* If non-null, print this message. */ |
c19d1205 | 31072 | }; |
7ed4c4c5 | 31073 | |
c921be7d | 31074 | static bfd_boolean |
c168ce07 | 31075 | arm_parse_extension (const char *str, const arm_feature_set *opt_set, |
34ef62f4 AV |
31076 | arm_feature_set *ext_set, |
31077 | const struct arm_ext_table *ext_table) | |
7ed4c4c5 | 31078 | { |
69133863 | 31079 | /* We insist on extensions being specified in alphabetical order, and with |
fa94de6b RM |
31080 | extensions being added before being removed. We achieve this by having |
31081 | the global ARM_EXTENSIONS table in alphabetical order, and using the | |
69133863 | 31082 | ADDING_VALUE variable to indicate whether we are adding an extension (1) |
fa94de6b | 31083 | or removing it (0) and only allowing it to change in the order |
69133863 MGD |
31084 | -1 -> 1 -> 0. */ |
31085 | const struct arm_option_extension_value_table * opt = NULL; | |
d942732e | 31086 | const arm_feature_set arm_any = ARM_ANY; |
69133863 MGD |
31087 | int adding_value = -1; |
31088 | ||
c19d1205 | 31089 | while (str != NULL && *str != 0) |
7ed4c4c5 | 31090 | { |
82b8a785 | 31091 | const char *ext; |
f3bad469 | 31092 | size_t len; |
7ed4c4c5 | 31093 | |
c19d1205 ZW |
31094 | if (*str != '+') |
31095 | { | |
31096 | as_bad (_("invalid architectural extension")); | |
c921be7d | 31097 | return FALSE; |
c19d1205 | 31098 | } |
7ed4c4c5 | 31099 | |
c19d1205 ZW |
31100 | str++; |
31101 | ext = strchr (str, '+'); | |
7ed4c4c5 | 31102 | |
c19d1205 | 31103 | if (ext != NULL) |
f3bad469 | 31104 | len = ext - str; |
c19d1205 | 31105 | else |
f3bad469 | 31106 | len = strlen (str); |
7ed4c4c5 | 31107 | |
f3bad469 | 31108 | if (len >= 2 && strncmp (str, "no", 2) == 0) |
69133863 MGD |
31109 | { |
31110 | if (adding_value != 0) | |
31111 | { | |
31112 | adding_value = 0; | |
31113 | opt = arm_extensions; | |
31114 | } | |
31115 | ||
f3bad469 | 31116 | len -= 2; |
69133863 MGD |
31117 | str += 2; |
31118 | } | |
f3bad469 | 31119 | else if (len > 0) |
69133863 MGD |
31120 | { |
31121 | if (adding_value == -1) | |
31122 | { | |
31123 | adding_value = 1; | |
31124 | opt = arm_extensions; | |
31125 | } | |
31126 | else if (adding_value != 1) | |
31127 | { | |
31128 | as_bad (_("must specify extensions to add before specifying " | |
31129 | "those to remove")); | |
31130 | return FALSE; | |
31131 | } | |
31132 | } | |
31133 | ||
f3bad469 | 31134 | if (len == 0) |
c19d1205 ZW |
31135 | { |
31136 | as_bad (_("missing architectural extension")); | |
c921be7d | 31137 | return FALSE; |
c19d1205 | 31138 | } |
7ed4c4c5 | 31139 | |
69133863 MGD |
31140 | gas_assert (adding_value != -1); |
31141 | gas_assert (opt != NULL); | |
31142 | ||
34ef62f4 AV |
31143 | if (ext_table != NULL) |
31144 | { | |
31145 | const struct arm_ext_table * ext_opt = ext_table; | |
31146 | bfd_boolean found = FALSE; | |
31147 | for (; ext_opt->name != NULL; ext_opt++) | |
31148 | if (ext_opt->name_len == len | |
31149 | && strncmp (ext_opt->name, str, len) == 0) | |
31150 | { | |
31151 | if (adding_value) | |
31152 | { | |
31153 | if (ARM_FEATURE_ZERO (ext_opt->merge)) | |
31154 | /* TODO: Option not supported. When we remove the | |
31155 | legacy table this case should error out. */ | |
31156 | continue; | |
31157 | ||
31158 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, ext_opt->merge); | |
31159 | } | |
31160 | else | |
31161 | { | |
31162 | if (ARM_FEATURE_ZERO (ext_opt->clear)) | |
31163 | /* TODO: Option not supported. When we remove the | |
31164 | legacy table this case should error out. */ | |
31165 | continue; | |
31166 | ARM_CLEAR_FEATURE (*ext_set, *ext_set, ext_opt->clear); | |
31167 | } | |
31168 | found = TRUE; | |
31169 | break; | |
31170 | } | |
31171 | if (found) | |
31172 | { | |
31173 | str = ext; | |
31174 | continue; | |
31175 | } | |
31176 | } | |
31177 | ||
69133863 MGD |
31178 | /* Scan over the options table trying to find an exact match. */ |
31179 | for (; opt->name != NULL; opt++) | |
f3bad469 | 31180 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 31181 | { |
d942732e TP |
31182 | int i, nb_allowed_archs = |
31183 | sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]); | |
69133863 | 31184 | /* Check we can apply the extension to this architecture. */ |
d942732e TP |
31185 | for (i = 0; i < nb_allowed_archs; i++) |
31186 | { | |
31187 | /* Empty entry. */ | |
31188 | if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any)) | |
31189 | continue; | |
c168ce07 | 31190 | if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *opt_set)) |
d942732e TP |
31191 | break; |
31192 | } | |
31193 | if (i == nb_allowed_archs) | |
69133863 MGD |
31194 | { |
31195 | as_bad (_("extension does not apply to the base architecture")); | |
31196 | return FALSE; | |
31197 | } | |
31198 | ||
31199 | /* Add or remove the extension. */ | |
31200 | if (adding_value) | |
4d354d8b | 31201 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value); |
69133863 | 31202 | else |
4d354d8b | 31203 | ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value); |
69133863 | 31204 | |
3d030cdb TP |
31205 | /* Allowing Thumb division instructions for ARMv7 in autodetection |
31206 | rely on this break so that duplicate extensions (extensions | |
31207 | with the same name as a previous extension in the list) are not | |
31208 | considered for command-line parsing. */ | |
c19d1205 ZW |
31209 | break; |
31210 | } | |
7ed4c4c5 | 31211 | |
c19d1205 ZW |
31212 | if (opt->name == NULL) |
31213 | { | |
69133863 MGD |
31214 | /* Did we fail to find an extension because it wasn't specified in |
31215 | alphabetical order, or because it does not exist? */ | |
31216 | ||
31217 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
f3bad469 | 31218 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
69133863 MGD |
31219 | break; |
31220 | ||
31221 | if (opt->name == NULL) | |
31222 | as_bad (_("unknown architectural extension `%s'"), str); | |
31223 | else | |
31224 | as_bad (_("architectural extensions must be specified in " | |
31225 | "alphabetical order")); | |
31226 | ||
c921be7d | 31227 | return FALSE; |
c19d1205 | 31228 | } |
69133863 MGD |
31229 | else |
31230 | { | |
31231 | /* We should skip the extension we've just matched the next time | |
31232 | round. */ | |
31233 | opt++; | |
31234 | } | |
7ed4c4c5 | 31235 | |
c19d1205 ZW |
31236 | str = ext; |
31237 | }; | |
7ed4c4c5 | 31238 | |
c921be7d | 31239 | return TRUE; |
c19d1205 | 31240 | } |
7ed4c4c5 | 31241 | |
c921be7d | 31242 | static bfd_boolean |
17b9d67d | 31243 | arm_parse_cpu (const char *str) |
7ed4c4c5 | 31244 | { |
f3bad469 | 31245 | const struct arm_cpu_option_table *opt; |
82b8a785 | 31246 | const char *ext = strchr (str, '+'); |
f3bad469 | 31247 | size_t len; |
7ed4c4c5 | 31248 | |
c19d1205 | 31249 | if (ext != NULL) |
f3bad469 | 31250 | len = ext - str; |
7ed4c4c5 | 31251 | else |
f3bad469 | 31252 | len = strlen (str); |
7ed4c4c5 | 31253 | |
f3bad469 | 31254 | if (len == 0) |
7ed4c4c5 | 31255 | { |
c19d1205 | 31256 | as_bad (_("missing cpu name `%s'"), str); |
c921be7d | 31257 | return FALSE; |
7ed4c4c5 NC |
31258 | } |
31259 | ||
c19d1205 | 31260 | for (opt = arm_cpus; opt->name != NULL; opt++) |
f3bad469 | 31261 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 31262 | { |
c168ce07 | 31263 | mcpu_cpu_opt = &opt->value; |
4d354d8b TP |
31264 | if (mcpu_ext_opt == NULL) |
31265 | mcpu_ext_opt = XNEW (arm_feature_set); | |
31266 | *mcpu_ext_opt = opt->ext; | |
e74cfd16 | 31267 | mcpu_fpu_opt = &opt->default_fpu; |
ee065d83 | 31268 | if (opt->canonical_name) |
ef8e6722 JW |
31269 | { |
31270 | gas_assert (sizeof selected_cpu_name > strlen (opt->canonical_name)); | |
31271 | strcpy (selected_cpu_name, opt->canonical_name); | |
31272 | } | |
ee065d83 PB |
31273 | else |
31274 | { | |
f3bad469 | 31275 | size_t i; |
c921be7d | 31276 | |
ef8e6722 JW |
31277 | if (len >= sizeof selected_cpu_name) |
31278 | len = (sizeof selected_cpu_name) - 1; | |
31279 | ||
f3bad469 | 31280 | for (i = 0; i < len; i++) |
ee065d83 PB |
31281 | selected_cpu_name[i] = TOUPPER (opt->name[i]); |
31282 | selected_cpu_name[i] = 0; | |
31283 | } | |
7ed4c4c5 | 31284 | |
c19d1205 | 31285 | if (ext != NULL) |
34ef62f4 | 31286 | return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL); |
7ed4c4c5 | 31287 | |
c921be7d | 31288 | return TRUE; |
c19d1205 | 31289 | } |
7ed4c4c5 | 31290 | |
c19d1205 | 31291 | as_bad (_("unknown cpu `%s'"), str); |
c921be7d | 31292 | return FALSE; |
7ed4c4c5 NC |
31293 | } |
31294 | ||
c921be7d | 31295 | static bfd_boolean |
17b9d67d | 31296 | arm_parse_arch (const char *str) |
7ed4c4c5 | 31297 | { |
e74cfd16 | 31298 | const struct arm_arch_option_table *opt; |
82b8a785 | 31299 | const char *ext = strchr (str, '+'); |
f3bad469 | 31300 | size_t len; |
7ed4c4c5 | 31301 | |
c19d1205 | 31302 | if (ext != NULL) |
f3bad469 | 31303 | len = ext - str; |
7ed4c4c5 | 31304 | else |
f3bad469 | 31305 | len = strlen (str); |
7ed4c4c5 | 31306 | |
f3bad469 | 31307 | if (len == 0) |
7ed4c4c5 | 31308 | { |
c19d1205 | 31309 | as_bad (_("missing architecture name `%s'"), str); |
c921be7d | 31310 | return FALSE; |
7ed4c4c5 NC |
31311 | } |
31312 | ||
c19d1205 | 31313 | for (opt = arm_archs; opt->name != NULL; opt++) |
f3bad469 | 31314 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 31315 | { |
e74cfd16 | 31316 | march_cpu_opt = &opt->value; |
4d354d8b TP |
31317 | if (march_ext_opt == NULL) |
31318 | march_ext_opt = XNEW (arm_feature_set); | |
31319 | *march_ext_opt = arm_arch_none; | |
e74cfd16 | 31320 | march_fpu_opt = &opt->default_fpu; |
5f4273c7 | 31321 | strcpy (selected_cpu_name, opt->name); |
7ed4c4c5 | 31322 | |
c19d1205 | 31323 | if (ext != NULL) |
34ef62f4 AV |
31324 | return arm_parse_extension (ext, march_cpu_opt, march_ext_opt, |
31325 | opt->ext_table); | |
7ed4c4c5 | 31326 | |
c921be7d | 31327 | return TRUE; |
c19d1205 ZW |
31328 | } |
31329 | ||
31330 | as_bad (_("unknown architecture `%s'\n"), str); | |
c921be7d | 31331 | return FALSE; |
7ed4c4c5 | 31332 | } |
eb043451 | 31333 | |
c921be7d | 31334 | static bfd_boolean |
17b9d67d | 31335 | arm_parse_fpu (const char * str) |
c19d1205 | 31336 | { |
69133863 | 31337 | const struct arm_option_fpu_value_table * opt; |
b99bd4ef | 31338 | |
c19d1205 ZW |
31339 | for (opt = arm_fpus; opt->name != NULL; opt++) |
31340 | if (streq (opt->name, str)) | |
31341 | { | |
e74cfd16 | 31342 | mfpu_opt = &opt->value; |
c921be7d | 31343 | return TRUE; |
c19d1205 | 31344 | } |
b99bd4ef | 31345 | |
c19d1205 | 31346 | as_bad (_("unknown floating point format `%s'\n"), str); |
c921be7d | 31347 | return FALSE; |
c19d1205 ZW |
31348 | } |
31349 | ||
c921be7d | 31350 | static bfd_boolean |
17b9d67d | 31351 | arm_parse_float_abi (const char * str) |
b99bd4ef | 31352 | { |
e74cfd16 | 31353 | const struct arm_option_value_table * opt; |
b99bd4ef | 31354 | |
c19d1205 ZW |
31355 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
31356 | if (streq (opt->name, str)) | |
31357 | { | |
31358 | mfloat_abi_opt = opt->value; | |
c921be7d | 31359 | return TRUE; |
c19d1205 | 31360 | } |
cc8a6dd0 | 31361 | |
c19d1205 | 31362 | as_bad (_("unknown floating point abi `%s'\n"), str); |
c921be7d | 31363 | return FALSE; |
c19d1205 | 31364 | } |
b99bd4ef | 31365 | |
c19d1205 | 31366 | #ifdef OBJ_ELF |
c921be7d | 31367 | static bfd_boolean |
17b9d67d | 31368 | arm_parse_eabi (const char * str) |
c19d1205 | 31369 | { |
e74cfd16 | 31370 | const struct arm_option_value_table *opt; |
cc8a6dd0 | 31371 | |
c19d1205 ZW |
31372 | for (opt = arm_eabis; opt->name != NULL; opt++) |
31373 | if (streq (opt->name, str)) | |
31374 | { | |
31375 | meabi_flags = opt->value; | |
c921be7d | 31376 | return TRUE; |
c19d1205 ZW |
31377 | } |
31378 | as_bad (_("unknown EABI `%s'\n"), str); | |
c921be7d | 31379 | return FALSE; |
c19d1205 ZW |
31380 | } |
31381 | #endif | |
cc8a6dd0 | 31382 | |
c921be7d | 31383 | static bfd_boolean |
17b9d67d | 31384 | arm_parse_it_mode (const char * str) |
e07e6e58 | 31385 | { |
c921be7d | 31386 | bfd_boolean ret = TRUE; |
e07e6e58 NC |
31387 | |
31388 | if (streq ("arm", str)) | |
31389 | implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
31390 | else if (streq ("thumb", str)) | |
31391 | implicit_it_mode = IMPLICIT_IT_MODE_THUMB; | |
31392 | else if (streq ("always", str)) | |
31393 | implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS; | |
31394 | else if (streq ("never", str)) | |
31395 | implicit_it_mode = IMPLICIT_IT_MODE_NEVER; | |
31396 | else | |
31397 | { | |
31398 | as_bad (_("unknown implicit IT mode `%s', should be "\ | |
477330fc | 31399 | "arm, thumb, always, or never."), str); |
c921be7d | 31400 | ret = FALSE; |
e07e6e58 NC |
31401 | } |
31402 | ||
31403 | return ret; | |
31404 | } | |
31405 | ||
2e6976a8 | 31406 | static bfd_boolean |
17b9d67d | 31407 | arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED) |
2e6976a8 DG |
31408 | { |
31409 | codecomposer_syntax = TRUE; | |
31410 | arm_comment_chars[0] = ';'; | |
31411 | arm_line_separator_chars[0] = 0; | |
31412 | return TRUE; | |
31413 | } | |
31414 | ||
c19d1205 ZW |
31415 | struct arm_long_option_table arm_long_opts[] = |
31416 | { | |
31417 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
31418 | arm_parse_cpu, NULL}, | |
31419 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
31420 | arm_parse_arch, NULL}, | |
31421 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
31422 | arm_parse_fpu, NULL}, | |
31423 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
31424 | arm_parse_float_abi, NULL}, | |
31425 | #ifdef OBJ_ELF | |
7fac0536 | 31426 | {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"), |
c19d1205 ZW |
31427 | arm_parse_eabi, NULL}, |
31428 | #endif | |
e07e6e58 NC |
31429 | {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"), |
31430 | arm_parse_it_mode, NULL}, | |
2e6976a8 DG |
31431 | {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"), |
31432 | arm_ccs_mode, NULL}, | |
c19d1205 ZW |
31433 | {NULL, NULL, 0, NULL} |
31434 | }; | |
cc8a6dd0 | 31435 | |
c19d1205 | 31436 | int |
17b9d67d | 31437 | md_parse_option (int c, const char * arg) |
c19d1205 ZW |
31438 | { |
31439 | struct arm_option_table *opt; | |
e74cfd16 | 31440 | const struct arm_legacy_option_table *fopt; |
c19d1205 | 31441 | struct arm_long_option_table *lopt; |
b99bd4ef | 31442 | |
c19d1205 | 31443 | switch (c) |
b99bd4ef | 31444 | { |
c19d1205 ZW |
31445 | #ifdef OPTION_EB |
31446 | case OPTION_EB: | |
31447 | target_big_endian = 1; | |
31448 | break; | |
31449 | #endif | |
cc8a6dd0 | 31450 | |
c19d1205 ZW |
31451 | #ifdef OPTION_EL |
31452 | case OPTION_EL: | |
31453 | target_big_endian = 0; | |
31454 | break; | |
31455 | #endif | |
b99bd4ef | 31456 | |
845b51d6 PB |
31457 | case OPTION_FIX_V4BX: |
31458 | fix_v4bx = TRUE; | |
31459 | break; | |
31460 | ||
18a20338 CL |
31461 | #ifdef OBJ_ELF |
31462 | case OPTION_FDPIC: | |
31463 | arm_fdpic = TRUE; | |
31464 | break; | |
31465 | #endif /* OBJ_ELF */ | |
31466 | ||
c19d1205 ZW |
31467 | case 'a': |
31468 | /* Listing option. Just ignore these, we don't support additional | |
31469 | ones. */ | |
31470 | return 0; | |
b99bd4ef | 31471 | |
c19d1205 ZW |
31472 | default: |
31473 | for (opt = arm_opts; opt->option != NULL; opt++) | |
31474 | { | |
31475 | if (c == opt->option[0] | |
31476 | && ((arg == NULL && opt->option[1] == 0) | |
31477 | || streq (arg, opt->option + 1))) | |
31478 | { | |
c19d1205 | 31479 | /* If the option is deprecated, tell the user. */ |
278df34e | 31480 | if (warn_on_deprecated && opt->deprecated != NULL) |
c19d1205 ZW |
31481 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
31482 | arg ? arg : "", _(opt->deprecated)); | |
b99bd4ef | 31483 | |
c19d1205 ZW |
31484 | if (opt->var != NULL) |
31485 | *opt->var = opt->value; | |
cc8a6dd0 | 31486 | |
c19d1205 ZW |
31487 | return 1; |
31488 | } | |
31489 | } | |
b99bd4ef | 31490 | |
e74cfd16 PB |
31491 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
31492 | { | |
31493 | if (c == fopt->option[0] | |
31494 | && ((arg == NULL && fopt->option[1] == 0) | |
31495 | || streq (arg, fopt->option + 1))) | |
31496 | { | |
e74cfd16 | 31497 | /* If the option is deprecated, tell the user. */ |
278df34e | 31498 | if (warn_on_deprecated && fopt->deprecated != NULL) |
e74cfd16 PB |
31499 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
31500 | arg ? arg : "", _(fopt->deprecated)); | |
e74cfd16 PB |
31501 | |
31502 | if (fopt->var != NULL) | |
31503 | *fopt->var = &fopt->value; | |
31504 | ||
31505 | return 1; | |
31506 | } | |
31507 | } | |
31508 | ||
c19d1205 ZW |
31509 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
31510 | { | |
31511 | /* These options are expected to have an argument. */ | |
31512 | if (c == lopt->option[0] | |
31513 | && arg != NULL | |
31514 | && strncmp (arg, lopt->option + 1, | |
31515 | strlen (lopt->option + 1)) == 0) | |
31516 | { | |
c19d1205 | 31517 | /* If the option is deprecated, tell the user. */ |
278df34e | 31518 | if (warn_on_deprecated && lopt->deprecated != NULL) |
c19d1205 ZW |
31519 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, |
31520 | _(lopt->deprecated)); | |
b99bd4ef | 31521 | |
c19d1205 ZW |
31522 | /* Call the sup-option parser. */ |
31523 | return lopt->func (arg + strlen (lopt->option) - 1); | |
31524 | } | |
31525 | } | |
a737bd4d | 31526 | |
c19d1205 ZW |
31527 | return 0; |
31528 | } | |
a394c00f | 31529 | |
c19d1205 ZW |
31530 | return 1; |
31531 | } | |
a394c00f | 31532 | |
c19d1205 ZW |
31533 | void |
31534 | md_show_usage (FILE * fp) | |
a394c00f | 31535 | { |
c19d1205 ZW |
31536 | struct arm_option_table *opt; |
31537 | struct arm_long_option_table *lopt; | |
a394c00f | 31538 | |
c19d1205 | 31539 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 31540 | |
c19d1205 ZW |
31541 | for (opt = arm_opts; opt->option != NULL; opt++) |
31542 | if (opt->help != NULL) | |
31543 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 31544 | |
c19d1205 ZW |
31545 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
31546 | if (lopt->help != NULL) | |
31547 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 31548 | |
c19d1205 ZW |
31549 | #ifdef OPTION_EB |
31550 | fprintf (fp, _("\ | |
31551 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
31552 | #endif |
31553 | ||
c19d1205 ZW |
31554 | #ifdef OPTION_EL |
31555 | fprintf (fp, _("\ | |
31556 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 31557 | #endif |
845b51d6 PB |
31558 | |
31559 | fprintf (fp, _("\ | |
31560 | --fix-v4bx Allow BX in ARMv4 code\n")); | |
18a20338 CL |
31561 | |
31562 | #ifdef OBJ_ELF | |
31563 | fprintf (fp, _("\ | |
31564 | --fdpic generate an FDPIC object file\n")); | |
31565 | #endif /* OBJ_ELF */ | |
c19d1205 | 31566 | } |
ee065d83 | 31567 | |
ee065d83 | 31568 | #ifdef OBJ_ELF |
0198d5e6 | 31569 | |
62b3e311 PB |
31570 | typedef struct |
31571 | { | |
31572 | int val; | |
31573 | arm_feature_set flags; | |
31574 | } cpu_arch_ver_table; | |
31575 | ||
2c6b98ea TP |
31576 | /* Mapping from CPU features to EABI CPU arch values. Table must be sorted |
31577 | chronologically for architectures, with an exception for ARMv6-M and | |
31578 | ARMv6S-M due to legacy reasons. No new architecture should have a | |
31579 | special case. This allows for build attribute selection results to be | |
31580 | stable when new architectures are added. */ | |
62b3e311 PB |
31581 | static const cpu_arch_ver_table cpu_arch_ver[] = |
31582 | { | |
031254f2 AV |
31583 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1}, |
31584 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2}, | |
31585 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S}, | |
31586 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3}, | |
31587 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M}, | |
31588 | {TAG_CPU_ARCH_V4, ARM_ARCH_V4xM}, | |
31589 | {TAG_CPU_ARCH_V4, ARM_ARCH_V4}, | |
31590 | {TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM}, | |
31591 | {TAG_CPU_ARCH_V4T, ARM_ARCH_V4T}, | |
31592 | {TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM}, | |
31593 | {TAG_CPU_ARCH_V5T, ARM_ARCH_V5}, | |
31594 | {TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM}, | |
31595 | {TAG_CPU_ARCH_V5T, ARM_ARCH_V5T}, | |
31596 | {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP}, | |
31597 | {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE}, | |
31598 | {TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ}, | |
31599 | {TAG_CPU_ARCH_V6, ARM_ARCH_V6}, | |
31600 | {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z}, | |
31601 | {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ}, | |
31602 | {TAG_CPU_ARCH_V6K, ARM_ARCH_V6K}, | |
31603 | {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2}, | |
31604 | {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2}, | |
31605 | {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2}, | |
31606 | {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2}, | |
2c6b98ea TP |
31607 | |
31608 | /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as | |
31609 | always selected build attributes to match those of ARMv6-M | |
31610 | (resp. ARMv6S-M). However, due to these architectures being a strict | |
31611 | subset of ARMv7-M in terms of instructions available, ARMv7-M attributes | |
31612 | would be selected when fully respecting chronology of architectures. | |
31613 | It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and | |
31614 | move them before ARMv7 architectures. */ | |
031254f2 AV |
31615 | {TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M}, |
31616 | {TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM}, | |
31617 | ||
31618 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7}, | |
31619 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7A}, | |
31620 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7R}, | |
31621 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7M}, | |
31622 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7VE}, | |
31623 | {TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM}, | |
31624 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8A}, | |
31625 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A}, | |
31626 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A}, | |
31627 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A}, | |
31628 | {TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE}, | |
31629 | {TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN}, | |
31630 | {TAG_CPU_ARCH_V8R, ARM_ARCH_V8R}, | |
31631 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A}, | |
31632 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A}, | |
31633 | {TAG_CPU_ARCH_V8_1M_MAIN, ARM_ARCH_V8_1M_MAIN}, | |
31634 | {-1, ARM_ARCH_NONE} | |
62b3e311 PB |
31635 | }; |
31636 | ||
ee3c0378 | 31637 | /* Set an attribute if it has not already been set by the user. */ |
0198d5e6 | 31638 | |
ee3c0378 AS |
31639 | static void |
31640 | aeabi_set_attribute_int (int tag, int value) | |
31641 | { | |
31642 | if (tag < 1 | |
31643 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
31644 | || !attributes_set_explicitly[tag]) | |
31645 | bfd_elf_add_proc_attr_int (stdoutput, tag, value); | |
31646 | } | |
31647 | ||
31648 | static void | |
31649 | aeabi_set_attribute_string (int tag, const char *value) | |
31650 | { | |
31651 | if (tag < 1 | |
31652 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
31653 | || !attributes_set_explicitly[tag]) | |
31654 | bfd_elf_add_proc_attr_string (stdoutput, tag, value); | |
31655 | } | |
31656 | ||
2c6b98ea TP |
31657 | /* Return whether features in the *NEEDED feature set are available via |
31658 | extensions for the architecture whose feature set is *ARCH_FSET. */ | |
0198d5e6 | 31659 | |
2c6b98ea TP |
31660 | static bfd_boolean |
31661 | have_ext_for_needed_feat_p (const arm_feature_set *arch_fset, | |
31662 | const arm_feature_set *needed) | |
31663 | { | |
31664 | int i, nb_allowed_archs; | |
31665 | arm_feature_set ext_fset; | |
31666 | const struct arm_option_extension_value_table *opt; | |
31667 | ||
31668 | ext_fset = arm_arch_none; | |
31669 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
31670 | { | |
31671 | /* Extension does not provide any feature we need. */ | |
31672 | if (!ARM_CPU_HAS_FEATURE (*needed, opt->merge_value)) | |
31673 | continue; | |
31674 | ||
31675 | nb_allowed_archs = | |
31676 | sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]); | |
31677 | for (i = 0; i < nb_allowed_archs; i++) | |
31678 | { | |
31679 | /* Empty entry. */ | |
31680 | if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_arch_any)) | |
31681 | break; | |
31682 | ||
31683 | /* Extension is available, add it. */ | |
31684 | if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *arch_fset)) | |
31685 | ARM_MERGE_FEATURE_SETS (ext_fset, ext_fset, opt->merge_value); | |
31686 | } | |
31687 | } | |
31688 | ||
31689 | /* Can we enable all features in *needed? */ | |
31690 | return ARM_FSET_CPU_SUBSET (*needed, ext_fset); | |
31691 | } | |
31692 | ||
31693 | /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for | |
31694 | a given architecture feature set *ARCH_EXT_FSET including extension feature | |
31695 | set *EXT_FSET. Selection logic used depend on EXACT_MATCH: | |
31696 | - if true, check for an exact match of the architecture modulo extensions; | |
31697 | - otherwise, select build attribute value of the first superset | |
31698 | architecture released so that results remains stable when new architectures | |
31699 | are added. | |
31700 | For -march/-mcpu=all the build attribute value of the most featureful | |
31701 | architecture is returned. Tag_CPU_arch_profile result is returned in | |
31702 | PROFILE. */ | |
0198d5e6 | 31703 | |
2c6b98ea TP |
31704 | static int |
31705 | get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset, | |
31706 | const arm_feature_set *ext_fset, | |
31707 | char *profile, int exact_match) | |
31708 | { | |
31709 | arm_feature_set arch_fset; | |
31710 | const cpu_arch_ver_table *p_ver, *p_ver_ret = NULL; | |
31711 | ||
31712 | /* Select most featureful architecture with all its extensions if building | |
31713 | for -march=all as the feature sets used to set build attributes. */ | |
31714 | if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any)) | |
31715 | { | |
31716 | /* Force revisiting of decision for each new architecture. */ | |
031254f2 | 31717 | gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8_1M_MAIN); |
2c6b98ea TP |
31718 | *profile = 'A'; |
31719 | return TAG_CPU_ARCH_V8; | |
31720 | } | |
31721 | ||
31722 | ARM_CLEAR_FEATURE (arch_fset, *arch_ext_fset, *ext_fset); | |
31723 | ||
31724 | for (p_ver = cpu_arch_ver; p_ver->val != -1; p_ver++) | |
31725 | { | |
31726 | arm_feature_set known_arch_fset; | |
31727 | ||
31728 | ARM_CLEAR_FEATURE (known_arch_fset, p_ver->flags, fpu_any); | |
31729 | if (exact_match) | |
31730 | { | |
31731 | /* Base architecture match user-specified architecture and | |
31732 | extensions, eg. ARMv6S-M matching -march=armv6-m+os. */ | |
31733 | if (ARM_FEATURE_EQUAL (*arch_ext_fset, known_arch_fset)) | |
31734 | { | |
31735 | p_ver_ret = p_ver; | |
31736 | goto found; | |
31737 | } | |
31738 | /* Base architecture match user-specified architecture only | |
31739 | (eg. ARMv6-M in the same case as above). Record it in case we | |
31740 | find a match with above condition. */ | |
31741 | else if (p_ver_ret == NULL | |
31742 | && ARM_FEATURE_EQUAL (arch_fset, known_arch_fset)) | |
31743 | p_ver_ret = p_ver; | |
31744 | } | |
31745 | else | |
31746 | { | |
31747 | ||
31748 | /* Architecture has all features wanted. */ | |
31749 | if (ARM_FSET_CPU_SUBSET (arch_fset, known_arch_fset)) | |
31750 | { | |
31751 | arm_feature_set added_fset; | |
31752 | ||
31753 | /* Compute features added by this architecture over the one | |
31754 | recorded in p_ver_ret. */ | |
31755 | if (p_ver_ret != NULL) | |
31756 | ARM_CLEAR_FEATURE (added_fset, known_arch_fset, | |
31757 | p_ver_ret->flags); | |
31758 | /* First architecture that match incl. with extensions, or the | |
31759 | only difference in features over the recorded match is | |
31760 | features that were optional and are now mandatory. */ | |
31761 | if (p_ver_ret == NULL | |
31762 | || ARM_FSET_CPU_SUBSET (added_fset, arch_fset)) | |
31763 | { | |
31764 | p_ver_ret = p_ver; | |
31765 | goto found; | |
31766 | } | |
31767 | } | |
31768 | else if (p_ver_ret == NULL) | |
31769 | { | |
31770 | arm_feature_set needed_ext_fset; | |
31771 | ||
31772 | ARM_CLEAR_FEATURE (needed_ext_fset, arch_fset, known_arch_fset); | |
31773 | ||
31774 | /* Architecture has all features needed when using some | |
31775 | extensions. Record it and continue searching in case there | |
31776 | exist an architecture providing all needed features without | |
31777 | the need for extensions (eg. ARMv6S-M Vs ARMv6-M with | |
31778 | OS extension). */ | |
31779 | if (have_ext_for_needed_feat_p (&known_arch_fset, | |
31780 | &needed_ext_fset)) | |
31781 | p_ver_ret = p_ver; | |
31782 | } | |
31783 | } | |
31784 | } | |
31785 | ||
31786 | if (p_ver_ret == NULL) | |
31787 | return -1; | |
31788 | ||
31789 | found: | |
31790 | /* Tag_CPU_arch_profile. */ | |
31791 | if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7a) | |
31792 | || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8) | |
31793 | || (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_atomics) | |
31794 | && !ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8m_m_only))) | |
31795 | *profile = 'A'; | |
31796 | else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7r)) | |
31797 | *profile = 'R'; | |
31798 | else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_m)) | |
31799 | *profile = 'M'; | |
31800 | else | |
31801 | *profile = '\0'; | |
31802 | return p_ver_ret->val; | |
31803 | } | |
31804 | ||
ee065d83 | 31805 | /* Set the public EABI object attributes. */ |
0198d5e6 | 31806 | |
c168ce07 | 31807 | static void |
ee065d83 PB |
31808 | aeabi_set_public_attributes (void) |
31809 | { | |
b90d5ba0 | 31810 | char profile = '\0'; |
2c6b98ea | 31811 | int arch = -1; |
90ec0d68 | 31812 | int virt_sec = 0; |
bca38921 | 31813 | int fp16_optional = 0; |
2c6b98ea TP |
31814 | int skip_exact_match = 0; |
31815 | arm_feature_set flags, flags_arch, flags_ext; | |
ee065d83 | 31816 | |
54bab281 TP |
31817 | /* Autodetection mode, choose the architecture based the instructions |
31818 | actually used. */ | |
31819 | if (no_cpu_selected ()) | |
31820 | { | |
31821 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); | |
ddd7f988 | 31822 | |
54bab281 TP |
31823 | if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)) |
31824 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1); | |
ddd7f988 | 31825 | |
54bab281 TP |
31826 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any)) |
31827 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t); | |
ddd7f988 | 31828 | |
54bab281 | 31829 | /* Code run during relaxation relies on selected_cpu being set. */ |
4d354d8b TP |
31830 | ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any); |
31831 | flags_ext = arm_arch_none; | |
31832 | ARM_CLEAR_FEATURE (selected_arch, flags_arch, flags_ext); | |
31833 | selected_ext = flags_ext; | |
54bab281 TP |
31834 | selected_cpu = flags; |
31835 | } | |
31836 | /* Otherwise, choose the architecture based on the capabilities of the | |
31837 | requested cpu. */ | |
31838 | else | |
4d354d8b TP |
31839 | { |
31840 | ARM_MERGE_FEATURE_SETS (flags_arch, selected_arch, selected_ext); | |
31841 | ARM_CLEAR_FEATURE (flags_arch, flags_arch, fpu_any); | |
31842 | flags_ext = selected_ext; | |
31843 | flags = selected_cpu; | |
31844 | } | |
31845 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_fpu); | |
7f78eb34 | 31846 | |
ddd7f988 | 31847 | /* Allow the user to override the reported architecture. */ |
4d354d8b | 31848 | if (!ARM_FEATURE_ZERO (selected_object_arch)) |
7a1d4c38 | 31849 | { |
4d354d8b | 31850 | ARM_CLEAR_FEATURE (flags_arch, selected_object_arch, fpu_any); |
2c6b98ea | 31851 | flags_ext = arm_arch_none; |
7a1d4c38 | 31852 | } |
2c6b98ea | 31853 | else |
4d354d8b | 31854 | skip_exact_match = ARM_FEATURE_EQUAL (selected_cpu, arm_arch_any); |
2c6b98ea TP |
31855 | |
31856 | /* When this function is run again after relaxation has happened there is no | |
31857 | way to determine whether an architecture or CPU was specified by the user: | |
31858 | - selected_cpu is set above for relaxation to work; | |
31859 | - march_cpu_opt is not set if only -mcpu or .cpu is used; | |
31860 | - mcpu_cpu_opt is set to arm_arch_any for autodetection. | |
31861 | Therefore, if not in -march=all case we first try an exact match and fall | |
31862 | back to autodetection. */ | |
31863 | if (!skip_exact_match) | |
31864 | arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 1); | |
31865 | if (arch == -1) | |
31866 | arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 0); | |
31867 | if (arch == -1) | |
31868 | as_bad (_("no architecture contains all the instructions used\n")); | |
9e3c6df6 | 31869 | |
ee065d83 PB |
31870 | /* Tag_CPU_name. */ |
31871 | if (selected_cpu_name[0]) | |
31872 | { | |
91d6fa6a | 31873 | char *q; |
ee065d83 | 31874 | |
91d6fa6a NC |
31875 | q = selected_cpu_name; |
31876 | if (strncmp (q, "armv", 4) == 0) | |
ee065d83 PB |
31877 | { |
31878 | int i; | |
5f4273c7 | 31879 | |
91d6fa6a NC |
31880 | q += 4; |
31881 | for (i = 0; q[i]; i++) | |
31882 | q[i] = TOUPPER (q[i]); | |
ee065d83 | 31883 | } |
91d6fa6a | 31884 | aeabi_set_attribute_string (Tag_CPU_name, q); |
ee065d83 | 31885 | } |
62f3b8c8 | 31886 | |
ee065d83 | 31887 | /* Tag_CPU_arch. */ |
ee3c0378 | 31888 | aeabi_set_attribute_int (Tag_CPU_arch, arch); |
62f3b8c8 | 31889 | |
62b3e311 | 31890 | /* Tag_CPU_arch_profile. */ |
69239280 MGD |
31891 | if (profile != '\0') |
31892 | aeabi_set_attribute_int (Tag_CPU_arch_profile, profile); | |
62f3b8c8 | 31893 | |
15afaa63 | 31894 | /* Tag_DSP_extension. */ |
4d354d8b | 31895 | if (ARM_CPU_HAS_FEATURE (selected_ext, arm_ext_dsp)) |
6c290d53 | 31896 | aeabi_set_attribute_int (Tag_DSP_extension, 1); |
15afaa63 | 31897 | |
2c6b98ea | 31898 | ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any); |
ee065d83 | 31899 | /* Tag_ARM_ISA_use. */ |
ee3c0378 | 31900 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) |
2c6b98ea | 31901 | || ARM_FEATURE_ZERO (flags_arch)) |
ee3c0378 | 31902 | aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); |
62f3b8c8 | 31903 | |
ee065d83 | 31904 | /* Tag_THUMB_ISA_use. */ |
ee3c0378 | 31905 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) |
2c6b98ea | 31906 | || ARM_FEATURE_ZERO (flags_arch)) |
4ed7ed8d TP |
31907 | { |
31908 | int thumb_isa_use; | |
31909 | ||
31910 | if (!ARM_CPU_HAS_FEATURE (flags, arm_ext_v8) | |
16a1fa25 | 31911 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only)) |
4ed7ed8d TP |
31912 | thumb_isa_use = 3; |
31913 | else if (ARM_CPU_HAS_FEATURE (flags, arm_arch_t2)) | |
31914 | thumb_isa_use = 2; | |
31915 | else | |
31916 | thumb_isa_use = 1; | |
31917 | aeabi_set_attribute_int (Tag_THUMB_ISA_use, thumb_isa_use); | |
31918 | } | |
62f3b8c8 | 31919 | |
ee065d83 | 31920 | /* Tag_VFP_arch. */ |
a715796b TG |
31921 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd)) |
31922 | aeabi_set_attribute_int (Tag_VFP_arch, | |
31923 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
31924 | ? 7 : 8); | |
bca38921 | 31925 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma)) |
62f3b8c8 PB |
31926 | aeabi_set_attribute_int (Tag_VFP_arch, |
31927 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
31928 | ? 5 : 6); | |
31929 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) | |
bca38921 MGD |
31930 | { |
31931 | fp16_optional = 1; | |
31932 | aeabi_set_attribute_int (Tag_VFP_arch, 3); | |
31933 | } | |
ada65aa3 | 31934 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd)) |
bca38921 MGD |
31935 | { |
31936 | aeabi_set_attribute_int (Tag_VFP_arch, 4); | |
31937 | fp16_optional = 1; | |
31938 | } | |
ee3c0378 AS |
31939 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) |
31940 | aeabi_set_attribute_int (Tag_VFP_arch, 2); | |
31941 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) | |
477330fc | 31942 | || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)) |
ee3c0378 | 31943 | aeabi_set_attribute_int (Tag_VFP_arch, 1); |
62f3b8c8 | 31944 | |
4547cb56 NC |
31945 | /* Tag_ABI_HardFP_use. */ |
31946 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd) | |
31947 | && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)) | |
31948 | aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1); | |
31949 | ||
ee065d83 | 31950 | /* Tag_WMMX_arch. */ |
ee3c0378 AS |
31951 | if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2)) |
31952 | aeabi_set_attribute_int (Tag_WMMX_arch, 2); | |
31953 | else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt)) | |
31954 | aeabi_set_attribute_int (Tag_WMMX_arch, 1); | |
62f3b8c8 | 31955 | |
ee3c0378 | 31956 | /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ |
9411fd44 MW |
31957 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v8_1)) |
31958 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 4); | |
31959 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8)) | |
bca38921 MGD |
31960 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3); |
31961 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) | |
31962 | { | |
31963 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)) | |
31964 | { | |
31965 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2); | |
31966 | } | |
31967 | else | |
31968 | { | |
31969 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1); | |
31970 | fp16_optional = 1; | |
31971 | } | |
31972 | } | |
fa94de6b | 31973 | |
a7ad558c AV |
31974 | if (ARM_CPU_HAS_FEATURE (flags, mve_fp_ext)) |
31975 | aeabi_set_attribute_int (Tag_MVE_arch, 2); | |
31976 | else if (ARM_CPU_HAS_FEATURE (flags, mve_ext)) | |
31977 | aeabi_set_attribute_int (Tag_MVE_arch, 1); | |
31978 | ||
ee3c0378 | 31979 | /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ |
bca38921 | 31980 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional) |
ee3c0378 | 31981 | aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); |
4547cb56 | 31982 | |
69239280 MGD |
31983 | /* Tag_DIV_use. |
31984 | ||
31985 | We set Tag_DIV_use to two when integer divide instructions have been used | |
31986 | in ARM state, or when Thumb integer divide instructions have been used, | |
31987 | but we have no architecture profile set, nor have we any ARM instructions. | |
31988 | ||
4ed7ed8d TP |
31989 | For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied |
31990 | by the base architecture. | |
bca38921 | 31991 | |
69239280 | 31992 | For new architectures we will have to check these tests. */ |
031254f2 | 31993 | gas_assert (arch <= TAG_CPU_ARCH_V8_1M_MAIN); |
4ed7ed8d TP |
31994 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8) |
31995 | || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m)) | |
bca38921 MGD |
31996 | aeabi_set_attribute_int (Tag_DIV_use, 0); |
31997 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv) | |
31998 | || (profile == '\0' | |
31999 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_div) | |
32000 | && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))) | |
eea54501 | 32001 | aeabi_set_attribute_int (Tag_DIV_use, 2); |
60e5ef9f MGD |
32002 | |
32003 | /* Tag_MP_extension_use. */ | |
32004 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp)) | |
32005 | aeabi_set_attribute_int (Tag_MPextension_use, 1); | |
f4c65163 MGD |
32006 | |
32007 | /* Tag Virtualization_use. */ | |
32008 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec)) | |
90ec0d68 MGD |
32009 | virt_sec |= 1; |
32010 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt)) | |
32011 | virt_sec |= 2; | |
32012 | if (virt_sec != 0) | |
32013 | aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec); | |
ee065d83 PB |
32014 | } |
32015 | ||
c168ce07 TP |
32016 | /* Post relaxation hook. Recompute ARM attributes now that relaxation is |
32017 | finished and free extension feature bits which will not be used anymore. */ | |
0198d5e6 | 32018 | |
c168ce07 TP |
32019 | void |
32020 | arm_md_post_relax (void) | |
32021 | { | |
32022 | aeabi_set_public_attributes (); | |
4d354d8b TP |
32023 | XDELETE (mcpu_ext_opt); |
32024 | mcpu_ext_opt = NULL; | |
32025 | XDELETE (march_ext_opt); | |
32026 | march_ext_opt = NULL; | |
c168ce07 TP |
32027 | } |
32028 | ||
104d59d1 | 32029 | /* Add the default contents for the .ARM.attributes section. */ |
0198d5e6 | 32030 | |
ee065d83 PB |
32031 | void |
32032 | arm_md_end (void) | |
32033 | { | |
ee065d83 PB |
32034 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
32035 | return; | |
32036 | ||
32037 | aeabi_set_public_attributes (); | |
ee065d83 | 32038 | } |
8463be01 | 32039 | #endif /* OBJ_ELF */ |
ee065d83 | 32040 | |
ee065d83 PB |
32041 | /* Parse a .cpu directive. */ |
32042 | ||
32043 | static void | |
32044 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) | |
32045 | { | |
e74cfd16 | 32046 | const struct arm_cpu_option_table *opt; |
ee065d83 PB |
32047 | char *name; |
32048 | char saved_char; | |
32049 | ||
32050 | name = input_line_pointer; | |
5f4273c7 | 32051 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
32052 | input_line_pointer++; |
32053 | saved_char = *input_line_pointer; | |
32054 | *input_line_pointer = 0; | |
32055 | ||
32056 | /* Skip the first "all" entry. */ | |
32057 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) | |
32058 | if (streq (opt->name, name)) | |
32059 | { | |
4d354d8b TP |
32060 | selected_arch = opt->value; |
32061 | selected_ext = opt->ext; | |
32062 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext); | |
ee065d83 | 32063 | if (opt->canonical_name) |
5f4273c7 | 32064 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
32065 | else |
32066 | { | |
32067 | int i; | |
32068 | for (i = 0; opt->name[i]; i++) | |
32069 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
f3bad469 | 32070 | |
ee065d83 PB |
32071 | selected_cpu_name[i] = 0; |
32072 | } | |
4d354d8b TP |
32073 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); |
32074 | ||
ee065d83 PB |
32075 | *input_line_pointer = saved_char; |
32076 | demand_empty_rest_of_line (); | |
32077 | return; | |
32078 | } | |
32079 | as_bad (_("unknown cpu `%s'"), name); | |
32080 | *input_line_pointer = saved_char; | |
32081 | ignore_rest_of_line (); | |
32082 | } | |
32083 | ||
ee065d83 PB |
32084 | /* Parse a .arch directive. */ |
32085 | ||
32086 | static void | |
32087 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) | |
32088 | { | |
e74cfd16 | 32089 | const struct arm_arch_option_table *opt; |
ee065d83 PB |
32090 | char saved_char; |
32091 | char *name; | |
32092 | ||
32093 | name = input_line_pointer; | |
5f4273c7 | 32094 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
32095 | input_line_pointer++; |
32096 | saved_char = *input_line_pointer; | |
32097 | *input_line_pointer = 0; | |
32098 | ||
32099 | /* Skip the first "all" entry. */ | |
32100 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
32101 | if (streq (opt->name, name)) | |
32102 | { | |
4d354d8b TP |
32103 | selected_arch = opt->value; |
32104 | selected_ext = arm_arch_none; | |
32105 | selected_cpu = selected_arch; | |
5f4273c7 | 32106 | strcpy (selected_cpu_name, opt->name); |
4d354d8b | 32107 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); |
ee065d83 PB |
32108 | *input_line_pointer = saved_char; |
32109 | demand_empty_rest_of_line (); | |
32110 | return; | |
32111 | } | |
32112 | ||
32113 | as_bad (_("unknown architecture `%s'\n"), name); | |
32114 | *input_line_pointer = saved_char; | |
32115 | ignore_rest_of_line (); | |
32116 | } | |
32117 | ||
7a1d4c38 PB |
32118 | /* Parse a .object_arch directive. */ |
32119 | ||
32120 | static void | |
32121 | s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) | |
32122 | { | |
32123 | const struct arm_arch_option_table *opt; | |
32124 | char saved_char; | |
32125 | char *name; | |
32126 | ||
32127 | name = input_line_pointer; | |
5f4273c7 | 32128 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
7a1d4c38 PB |
32129 | input_line_pointer++; |
32130 | saved_char = *input_line_pointer; | |
32131 | *input_line_pointer = 0; | |
32132 | ||
32133 | /* Skip the first "all" entry. */ | |
32134 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
32135 | if (streq (opt->name, name)) | |
32136 | { | |
4d354d8b | 32137 | selected_object_arch = opt->value; |
7a1d4c38 PB |
32138 | *input_line_pointer = saved_char; |
32139 | demand_empty_rest_of_line (); | |
32140 | return; | |
32141 | } | |
32142 | ||
32143 | as_bad (_("unknown architecture `%s'\n"), name); | |
32144 | *input_line_pointer = saved_char; | |
32145 | ignore_rest_of_line (); | |
32146 | } | |
32147 | ||
69133863 MGD |
32148 | /* Parse a .arch_extension directive. */ |
32149 | ||
32150 | static void | |
32151 | s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED) | |
32152 | { | |
32153 | const struct arm_option_extension_value_table *opt; | |
32154 | char saved_char; | |
32155 | char *name; | |
32156 | int adding_value = 1; | |
32157 | ||
32158 | name = input_line_pointer; | |
32159 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) | |
32160 | input_line_pointer++; | |
32161 | saved_char = *input_line_pointer; | |
32162 | *input_line_pointer = 0; | |
32163 | ||
32164 | if (strlen (name) >= 2 | |
32165 | && strncmp (name, "no", 2) == 0) | |
32166 | { | |
32167 | adding_value = 0; | |
32168 | name += 2; | |
32169 | } | |
32170 | ||
32171 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
32172 | if (streq (opt->name, name)) | |
32173 | { | |
d942732e TP |
32174 | int i, nb_allowed_archs = |
32175 | sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[i]); | |
32176 | for (i = 0; i < nb_allowed_archs; i++) | |
32177 | { | |
32178 | /* Empty entry. */ | |
4d354d8b | 32179 | if (ARM_CPU_IS_ANY (opt->allowed_archs[i])) |
d942732e | 32180 | continue; |
4d354d8b | 32181 | if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], selected_arch)) |
d942732e TP |
32182 | break; |
32183 | } | |
32184 | ||
32185 | if (i == nb_allowed_archs) | |
69133863 MGD |
32186 | { |
32187 | as_bad (_("architectural extension `%s' is not allowed for the " | |
32188 | "current base architecture"), name); | |
32189 | break; | |
32190 | } | |
32191 | ||
32192 | if (adding_value) | |
4d354d8b | 32193 | ARM_MERGE_FEATURE_SETS (selected_ext, selected_ext, |
5a70a223 | 32194 | opt->merge_value); |
69133863 | 32195 | else |
4d354d8b | 32196 | ARM_CLEAR_FEATURE (selected_ext, selected_ext, opt->clear_value); |
69133863 | 32197 | |
4d354d8b TP |
32198 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext); |
32199 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); | |
69133863 MGD |
32200 | *input_line_pointer = saved_char; |
32201 | demand_empty_rest_of_line (); | |
3d030cdb TP |
32202 | /* Allowing Thumb division instructions for ARMv7 in autodetection rely |
32203 | on this return so that duplicate extensions (extensions with the | |
32204 | same name as a previous extension in the list) are not considered | |
32205 | for command-line parsing. */ | |
69133863 MGD |
32206 | return; |
32207 | } | |
32208 | ||
32209 | if (opt->name == NULL) | |
e673710a | 32210 | as_bad (_("unknown architecture extension `%s'\n"), name); |
69133863 MGD |
32211 | |
32212 | *input_line_pointer = saved_char; | |
32213 | ignore_rest_of_line (); | |
32214 | } | |
32215 | ||
ee065d83 PB |
32216 | /* Parse a .fpu directive. */ |
32217 | ||
32218 | static void | |
32219 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) | |
32220 | { | |
69133863 | 32221 | const struct arm_option_fpu_value_table *opt; |
ee065d83 PB |
32222 | char saved_char; |
32223 | char *name; | |
32224 | ||
32225 | name = input_line_pointer; | |
5f4273c7 | 32226 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
32227 | input_line_pointer++; |
32228 | saved_char = *input_line_pointer; | |
32229 | *input_line_pointer = 0; | |
5f4273c7 | 32230 | |
ee065d83 PB |
32231 | for (opt = arm_fpus; opt->name != NULL; opt++) |
32232 | if (streq (opt->name, name)) | |
32233 | { | |
4d354d8b TP |
32234 | selected_fpu = opt->value; |
32235 | #ifndef CPU_DEFAULT | |
32236 | if (no_cpu_selected ()) | |
32237 | ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu); | |
32238 | else | |
32239 | #endif | |
32240 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); | |
ee065d83 PB |
32241 | *input_line_pointer = saved_char; |
32242 | demand_empty_rest_of_line (); | |
32243 | return; | |
32244 | } | |
32245 | ||
32246 | as_bad (_("unknown floating point format `%s'\n"), name); | |
32247 | *input_line_pointer = saved_char; | |
32248 | ignore_rest_of_line (); | |
32249 | } | |
ee065d83 | 32250 | |
794ba86a | 32251 | /* Copy symbol information. */ |
f31fef98 | 32252 | |
794ba86a DJ |
32253 | void |
32254 | arm_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
32255 | { | |
32256 | ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); | |
32257 | } | |
e04befd0 | 32258 | |
f31fef98 | 32259 | #ifdef OBJ_ELF |
e04befd0 AS |
32260 | /* Given a symbolic attribute NAME, return the proper integer value. |
32261 | Returns -1 if the attribute is not known. */ | |
f31fef98 | 32262 | |
e04befd0 AS |
32263 | int |
32264 | arm_convert_symbolic_attribute (const char *name) | |
32265 | { | |
f31fef98 NC |
32266 | static const struct |
32267 | { | |
32268 | const char * name; | |
32269 | const int tag; | |
32270 | } | |
32271 | attribute_table[] = | |
32272 | { | |
32273 | /* When you modify this table you should | |
32274 | also modify the list in doc/c-arm.texi. */ | |
e04befd0 | 32275 | #define T(tag) {#tag, tag} |
f31fef98 NC |
32276 | T (Tag_CPU_raw_name), |
32277 | T (Tag_CPU_name), | |
32278 | T (Tag_CPU_arch), | |
32279 | T (Tag_CPU_arch_profile), | |
32280 | T (Tag_ARM_ISA_use), | |
32281 | T (Tag_THUMB_ISA_use), | |
75375b3e | 32282 | T (Tag_FP_arch), |
f31fef98 NC |
32283 | T (Tag_VFP_arch), |
32284 | T (Tag_WMMX_arch), | |
32285 | T (Tag_Advanced_SIMD_arch), | |
32286 | T (Tag_PCS_config), | |
32287 | T (Tag_ABI_PCS_R9_use), | |
32288 | T (Tag_ABI_PCS_RW_data), | |
32289 | T (Tag_ABI_PCS_RO_data), | |
32290 | T (Tag_ABI_PCS_GOT_use), | |
32291 | T (Tag_ABI_PCS_wchar_t), | |
32292 | T (Tag_ABI_FP_rounding), | |
32293 | T (Tag_ABI_FP_denormal), | |
32294 | T (Tag_ABI_FP_exceptions), | |
32295 | T (Tag_ABI_FP_user_exceptions), | |
32296 | T (Tag_ABI_FP_number_model), | |
75375b3e | 32297 | T (Tag_ABI_align_needed), |
f31fef98 | 32298 | T (Tag_ABI_align8_needed), |
75375b3e | 32299 | T (Tag_ABI_align_preserved), |
f31fef98 NC |
32300 | T (Tag_ABI_align8_preserved), |
32301 | T (Tag_ABI_enum_size), | |
32302 | T (Tag_ABI_HardFP_use), | |
32303 | T (Tag_ABI_VFP_args), | |
32304 | T (Tag_ABI_WMMX_args), | |
32305 | T (Tag_ABI_optimization_goals), | |
32306 | T (Tag_ABI_FP_optimization_goals), | |
32307 | T (Tag_compatibility), | |
32308 | T (Tag_CPU_unaligned_access), | |
75375b3e | 32309 | T (Tag_FP_HP_extension), |
f31fef98 NC |
32310 | T (Tag_VFP_HP_extension), |
32311 | T (Tag_ABI_FP_16bit_format), | |
cd21e546 MGD |
32312 | T (Tag_MPextension_use), |
32313 | T (Tag_DIV_use), | |
f31fef98 NC |
32314 | T (Tag_nodefaults), |
32315 | T (Tag_also_compatible_with), | |
32316 | T (Tag_conformance), | |
32317 | T (Tag_T2EE_use), | |
32318 | T (Tag_Virtualization_use), | |
15afaa63 | 32319 | T (Tag_DSP_extension), |
a7ad558c | 32320 | T (Tag_MVE_arch), |
cd21e546 | 32321 | /* We deliberately do not include Tag_MPextension_use_legacy. */ |
e04befd0 | 32322 | #undef T |
f31fef98 | 32323 | }; |
e04befd0 AS |
32324 | unsigned int i; |
32325 | ||
32326 | if (name == NULL) | |
32327 | return -1; | |
32328 | ||
f31fef98 | 32329 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
c921be7d | 32330 | if (streq (name, attribute_table[i].name)) |
e04befd0 AS |
32331 | return attribute_table[i].tag; |
32332 | ||
32333 | return -1; | |
32334 | } | |
267bf995 | 32335 | |
93ef582d NC |
32336 | /* Apply sym value for relocations only in the case that they are for |
32337 | local symbols in the same segment as the fixup and you have the | |
32338 | respective architectural feature for blx and simple switches. */ | |
0198d5e6 | 32339 | |
267bf995 | 32340 | int |
93ef582d | 32341 | arm_apply_sym_value (struct fix * fixP, segT this_seg) |
267bf995 RR |
32342 | { |
32343 | if (fixP->fx_addsy | |
32344 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
93ef582d NC |
32345 | /* PR 17444: If the local symbol is in a different section then a reloc |
32346 | will always be generated for it, so applying the symbol value now | |
32347 | will result in a double offset being stored in the relocation. */ | |
32348 | && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg) | |
34e77a92 | 32349 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
267bf995 RR |
32350 | { |
32351 | switch (fixP->fx_r_type) | |
32352 | { | |
32353 | case BFD_RELOC_ARM_PCREL_BLX: | |
32354 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
32355 | if (ARM_IS_FUNC (fixP->fx_addsy)) | |
32356 | return 1; | |
32357 | break; | |
32358 | ||
32359 | case BFD_RELOC_ARM_PCREL_CALL: | |
32360 | case BFD_RELOC_THUMB_PCREL_BLX: | |
32361 | if (THUMB_IS_FUNC (fixP->fx_addsy)) | |
93ef582d | 32362 | return 1; |
267bf995 RR |
32363 | break; |
32364 | ||
32365 | default: | |
32366 | break; | |
32367 | } | |
32368 | ||
32369 | } | |
32370 | return 0; | |
32371 | } | |
f31fef98 | 32372 | #endif /* OBJ_ELF */ |