Commit | Line | Data |
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b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
b90efa5b | 2 | Copyright (C) 1994-2015 Free Software Foundation, Inc. |
b99bd4ef NC |
3 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) |
4 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 5 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
6 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
7 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
8 | |
9 | This file is part of GAS, the GNU Assembler. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 13 | the Free Software Foundation; either version 3, or (at your option) |
b99bd4ef NC |
14 | any later version. |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
19 | GNU General Public License for more details. |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
b99bd4ef | 25 | |
42a68e18 | 26 | #include "as.h" |
5287ad62 | 27 | #include <limits.h> |
037e8744 | 28 | #include <stdarg.h> |
c19d1205 | 29 | #define NO_RELOC 0 |
3882b010 | 30 | #include "safe-ctype.h" |
b99bd4ef NC |
31 | #include "subsegs.h" |
32 | #include "obstack.h" | |
3da1d841 | 33 | #include "libiberty.h" |
f263249b RE |
34 | #include "opcode/arm.h" |
35 | ||
b99bd4ef NC |
36 | #ifdef OBJ_ELF |
37 | #include "elf/arm.h" | |
a394c00f | 38 | #include "dw2gencfi.h" |
b99bd4ef NC |
39 | #endif |
40 | ||
f0927246 NC |
41 | #include "dwarf2dbg.h" |
42 | ||
7ed4c4c5 NC |
43 | #ifdef OBJ_ELF |
44 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
45 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
46 | ||
47 | /* This structure holds the unwinding state. */ | |
48 | ||
49 | static struct | |
50 | { | |
c19d1205 ZW |
51 | symbolS * proc_start; |
52 | symbolS * table_entry; | |
53 | symbolS * personality_routine; | |
54 | int personality_index; | |
7ed4c4c5 | 55 | /* The segment containing the function. */ |
c19d1205 ZW |
56 | segT saved_seg; |
57 | subsegT saved_subseg; | |
7ed4c4c5 NC |
58 | /* Opcodes generated from this function. */ |
59 | unsigned char * opcodes; | |
c19d1205 ZW |
60 | int opcode_count; |
61 | int opcode_alloc; | |
7ed4c4c5 | 62 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 63 | offsetT frame_size; |
7ed4c4c5 NC |
64 | /* We don't add stack adjustment opcodes immediately so that we can merge |
65 | multiple adjustments. We can also omit the final adjustment | |
66 | when using a frame pointer. */ | |
c19d1205 | 67 | offsetT pending_offset; |
7ed4c4c5 | 68 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
69 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
70 | offsetT fp_offset; | |
71 | int fp_reg; | |
7ed4c4c5 | 72 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 73 | unsigned fp_used:1; |
7ed4c4c5 | 74 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 75 | unsigned sp_restored:1; |
7ed4c4c5 NC |
76 | } unwind; |
77 | ||
8b1ad454 NC |
78 | #endif /* OBJ_ELF */ |
79 | ||
4962c51a MS |
80 | /* Results from operand parsing worker functions. */ |
81 | ||
82 | typedef enum | |
83 | { | |
84 | PARSE_OPERAND_SUCCESS, | |
85 | PARSE_OPERAND_FAIL, | |
86 | PARSE_OPERAND_FAIL_NO_BACKTRACK | |
87 | } parse_operand_result; | |
88 | ||
33a392fb PB |
89 | enum arm_float_abi |
90 | { | |
91 | ARM_FLOAT_ABI_HARD, | |
92 | ARM_FLOAT_ABI_SOFTFP, | |
93 | ARM_FLOAT_ABI_SOFT | |
94 | }; | |
95 | ||
c19d1205 | 96 | /* Types of processor to assemble for. */ |
b99bd4ef | 97 | #ifndef CPU_DEFAULT |
8a59fff3 | 98 | /* The code that was here used to select a default CPU depending on compiler |
fa94de6b | 99 | pre-defines which were only present when doing native builds, thus |
8a59fff3 MGD |
100 | changing gas' default behaviour depending upon the build host. |
101 | ||
102 | If you have a target that requires a default CPU option then the you | |
103 | should define CPU_DEFAULT here. */ | |
b99bd4ef NC |
104 | #endif |
105 | ||
106 | #ifndef FPU_DEFAULT | |
c820d418 MM |
107 | # ifdef TE_LINUX |
108 | # define FPU_DEFAULT FPU_ARCH_FPA | |
109 | # elif defined (TE_NetBSD) | |
110 | # ifdef OBJ_ELF | |
111 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
112 | # else | |
113 | /* Legacy a.out format. */ | |
114 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
115 | # endif | |
4e7fd91e PB |
116 | # elif defined (TE_VXWORKS) |
117 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
118 | # else |
119 | /* For backwards compatibility, default to FPA. */ | |
120 | # define FPU_DEFAULT FPU_ARCH_FPA | |
121 | # endif | |
122 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 123 | |
c19d1205 | 124 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 125 | |
e74cfd16 PB |
126 | static arm_feature_set cpu_variant; |
127 | static arm_feature_set arm_arch_used; | |
128 | static arm_feature_set thumb_arch_used; | |
b99bd4ef | 129 | |
b99bd4ef | 130 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
131 | static int uses_apcs_26 = FALSE; |
132 | static int atpcs = FALSE; | |
b34976b6 AM |
133 | static int support_interwork = FALSE; |
134 | static int uses_apcs_float = FALSE; | |
c19d1205 | 135 | static int pic_code = FALSE; |
845b51d6 | 136 | static int fix_v4bx = FALSE; |
278df34e NS |
137 | /* Warn on using deprecated features. */ |
138 | static int warn_on_deprecated = TRUE; | |
139 | ||
2e6976a8 DG |
140 | /* Understand CodeComposer Studio assembly syntax. */ |
141 | bfd_boolean codecomposer_syntax = FALSE; | |
03b1477f RE |
142 | |
143 | /* Variables that we set while parsing command-line options. Once all | |
144 | options have been read we re-process these values to set the real | |
145 | assembly flags. */ | |
e74cfd16 PB |
146 | static const arm_feature_set *legacy_cpu = NULL; |
147 | static const arm_feature_set *legacy_fpu = NULL; | |
148 | ||
149 | static const arm_feature_set *mcpu_cpu_opt = NULL; | |
150 | static const arm_feature_set *mcpu_fpu_opt = NULL; | |
151 | static const arm_feature_set *march_cpu_opt = NULL; | |
152 | static const arm_feature_set *march_fpu_opt = NULL; | |
153 | static const arm_feature_set *mfpu_opt = NULL; | |
7a1d4c38 | 154 | static const arm_feature_set *object_arch = NULL; |
e74cfd16 PB |
155 | |
156 | /* Constants for known architecture features. */ | |
157 | static const arm_feature_set fpu_default = FPU_DEFAULT; | |
158 | static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; | |
159 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; | |
5287ad62 JB |
160 | static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; |
161 | static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; | |
e74cfd16 PB |
162 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; |
163 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; | |
164 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; | |
165 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; | |
166 | ||
167 | #ifdef CPU_DEFAULT | |
168 | static const arm_feature_set cpu_default = CPU_DEFAULT; | |
169 | #endif | |
170 | ||
171 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); | |
172 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); | |
173 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); | |
174 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); | |
175 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); | |
176 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); | |
177 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); | |
178 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); | |
179 | static const arm_feature_set arm_ext_v4t_5 = | |
180 | ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); | |
181 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); | |
182 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); | |
183 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); | |
184 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); | |
185 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); | |
186 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); | |
e74cfd16 | 187 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); |
b2a5fbdc | 188 | static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0); |
62b3e311 | 189 | static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); |
9e3c6df6 | 190 | static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0); |
7e806470 PB |
191 | static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0); |
192 | static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0); | |
62b3e311 PB |
193 | static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); |
194 | static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); | |
195 | static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); | |
196 | static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); | |
9e3c6df6 | 197 | static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); |
bca38921 | 198 | static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0); |
7e806470 | 199 | static const arm_feature_set arm_ext_m = |
b2a5fbdc | 200 | ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0); |
60e5ef9f | 201 | static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0); |
f4c65163 | 202 | static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0); |
b2a5fbdc | 203 | static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0); |
eea54501 | 204 | static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0); |
90ec0d68 | 205 | static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0); |
e74cfd16 PB |
206 | |
207 | static const arm_feature_set arm_arch_any = ARM_ANY; | |
208 | static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); | |
209 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; | |
210 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; | |
251665fc | 211 | static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY; |
e74cfd16 | 212 | |
2d447fca JM |
213 | static const arm_feature_set arm_cext_iwmmxt2 = |
214 | ARM_FEATURE (0, ARM_CEXT_IWMMXT2); | |
e74cfd16 PB |
215 | static const arm_feature_set arm_cext_iwmmxt = |
216 | ARM_FEATURE (0, ARM_CEXT_IWMMXT); | |
217 | static const arm_feature_set arm_cext_xscale = | |
218 | ARM_FEATURE (0, ARM_CEXT_XSCALE); | |
219 | static const arm_feature_set arm_cext_maverick = | |
220 | ARM_FEATURE (0, ARM_CEXT_MAVERICK); | |
221 | static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); | |
222 | static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); | |
223 | static const arm_feature_set fpu_vfp_ext_v1xd = | |
224 | ARM_FEATURE (0, FPU_VFP_EXT_V1xD); | |
225 | static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); | |
226 | static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); | |
62f3b8c8 | 227 | static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD); |
5287ad62 | 228 | static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); |
b1cc4aeb PB |
229 | static const arm_feature_set fpu_vfp_ext_d32 = |
230 | ARM_FEATURE (0, FPU_VFP_EXT_D32); | |
5287ad62 JB |
231 | static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); |
232 | static const arm_feature_set fpu_vfp_v3_or_neon_ext = | |
233 | ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); | |
62f3b8c8 PB |
234 | static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16); |
235 | static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA); | |
236 | static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA); | |
bca38921 MGD |
237 | static const arm_feature_set fpu_vfp_ext_armv8 = |
238 | ARM_FEATURE (0, FPU_VFP_EXT_ARMV8); | |
a715796b TG |
239 | static const arm_feature_set fpu_vfp_ext_armv8xd = |
240 | ARM_FEATURE (0, FPU_VFP_EXT_ARMV8xD); | |
bca38921 MGD |
241 | static const arm_feature_set fpu_neon_ext_armv8 = |
242 | ARM_FEATURE (0, FPU_NEON_EXT_ARMV8); | |
243 | static const arm_feature_set fpu_crypto_ext_armv8 = | |
244 | ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8); | |
dd5181d5 KT |
245 | static const arm_feature_set crc_ext_armv8 = |
246 | ARM_FEATURE (0, CRC_EXT_ARMV8); | |
e74cfd16 | 247 | |
33a392fb | 248 | static int mfloat_abi_opt = -1; |
e74cfd16 PB |
249 | /* Record user cpu selection for object attributes. */ |
250 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; | |
ee065d83 PB |
251 | /* Must be long enough to hold any of the names in arm_cpus. */ |
252 | static char selected_cpu_name[16]; | |
8d67f500 | 253 | |
aacf0b33 KT |
254 | extern FLONUM_TYPE generic_floating_point_number; |
255 | ||
8d67f500 NC |
256 | /* Return if no cpu was selected on command-line. */ |
257 | static bfd_boolean | |
258 | no_cpu_selected (void) | |
259 | { | |
260 | return selected_cpu.core == arm_arch_none.core | |
261 | && selected_cpu.coproc == arm_arch_none.coproc; | |
262 | } | |
263 | ||
7cc69913 | 264 | #ifdef OBJ_ELF |
deeaaff8 DJ |
265 | # ifdef EABI_DEFAULT |
266 | static int meabi_flags = EABI_DEFAULT; | |
267 | # else | |
d507cf36 | 268 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 269 | # endif |
e1da3f5b | 270 | |
ee3c0378 AS |
271 | static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; |
272 | ||
e1da3f5b | 273 | bfd_boolean |
5f4273c7 | 274 | arm_is_eabi (void) |
e1da3f5b PB |
275 | { |
276 | return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); | |
277 | } | |
7cc69913 | 278 | #endif |
b99bd4ef | 279 | |
b99bd4ef | 280 | #ifdef OBJ_ELF |
c19d1205 | 281 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
282 | symbolS * GOT_symbol; |
283 | #endif | |
284 | ||
b99bd4ef NC |
285 | /* 0: assemble for ARM, |
286 | 1: assemble for Thumb, | |
287 | 2: assemble for Thumb even though target CPU does not support thumb | |
288 | instructions. */ | |
289 | static int thumb_mode = 0; | |
8dc2430f NC |
290 | /* A value distinct from the possible values for thumb_mode that we |
291 | can use to record whether thumb_mode has been copied into the | |
292 | tc_frag_data field of a frag. */ | |
293 | #define MODE_RECORDED (1 << 4) | |
b99bd4ef | 294 | |
e07e6e58 NC |
295 | /* Specifies the intrinsic IT insn behavior mode. */ |
296 | enum implicit_it_mode | |
297 | { | |
298 | IMPLICIT_IT_MODE_NEVER = 0x00, | |
299 | IMPLICIT_IT_MODE_ARM = 0x01, | |
300 | IMPLICIT_IT_MODE_THUMB = 0x02, | |
301 | IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB) | |
302 | }; | |
303 | static int implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
304 | ||
c19d1205 ZW |
305 | /* If unified_syntax is true, we are processing the new unified |
306 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
307 | ||
308 | - Immediate operands do not require a # prefix. | |
309 | - Conditional affixes always appear at the end of the | |
310 | instruction. (For backward compatibility, those instructions | |
311 | that formerly had them in the middle, continue to accept them | |
312 | there.) | |
313 | - The IT instruction may appear, and if it does is validated | |
314 | against subsequent conditional affixes. It does not generate | |
315 | machine code. | |
316 | ||
317 | Important differences from the old Thumb mode: | |
318 | ||
319 | - Immediate operands do not require a # prefix. | |
320 | - Most of the V6T2 instructions are only available in unified mode. | |
321 | - The .N and .W suffixes are recognized and honored (it is an error | |
322 | if they cannot be honored). | |
323 | - All instructions set the flags if and only if they have an 's' affix. | |
324 | - Conditional affixes may be used. They are validated against | |
325 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
326 | conditional affix except in the scope of an IT instruction. */ | |
327 | ||
328 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef | 329 | |
bacebabc RM |
330 | /* An immediate operand can start with #, and ld*, st*, pld operands |
331 | can contain [ and ]. We need to tell APP not to elide whitespace | |
477330fc RM |
332 | before a [, which can appear as the first operand for pld. |
333 | Likewise, a { can appear as the first operand for push, pop, vld*, etc. */ | |
334 | const char arm_symbol_chars[] = "#[]{}"; | |
bacebabc | 335 | |
5287ad62 JB |
336 | enum neon_el_type |
337 | { | |
dcbf9037 | 338 | NT_invtype, |
5287ad62 JB |
339 | NT_untyped, |
340 | NT_integer, | |
341 | NT_float, | |
342 | NT_poly, | |
343 | NT_signed, | |
dcbf9037 | 344 | NT_unsigned |
5287ad62 JB |
345 | }; |
346 | ||
347 | struct neon_type_el | |
348 | { | |
349 | enum neon_el_type type; | |
350 | unsigned size; | |
351 | }; | |
352 | ||
353 | #define NEON_MAX_TYPE_ELS 4 | |
354 | ||
355 | struct neon_type | |
356 | { | |
357 | struct neon_type_el el[NEON_MAX_TYPE_ELS]; | |
358 | unsigned elems; | |
359 | }; | |
360 | ||
e07e6e58 NC |
361 | enum it_instruction_type |
362 | { | |
363 | OUTSIDE_IT_INSN, | |
364 | INSIDE_IT_INSN, | |
365 | INSIDE_IT_LAST_INSN, | |
366 | IF_INSIDE_IT_LAST_INSN, /* Either outside or inside; | |
477330fc | 367 | if inside, should be the last one. */ |
e07e6e58 | 368 | NEUTRAL_IT_INSN, /* This could be either inside or outside, |
477330fc | 369 | i.e. BKPT and NOP. */ |
e07e6e58 NC |
370 | IT_INSN /* The IT insn has been parsed. */ |
371 | }; | |
372 | ||
ad6cec43 MGD |
373 | /* The maximum number of operands we need. */ |
374 | #define ARM_IT_MAX_OPERANDS 6 | |
375 | ||
b99bd4ef NC |
376 | struct arm_it |
377 | { | |
c19d1205 | 378 | const char * error; |
b99bd4ef | 379 | unsigned long instruction; |
c19d1205 ZW |
380 | int size; |
381 | int size_req; | |
382 | int cond; | |
037e8744 JB |
383 | /* "uncond_value" is set to the value in place of the conditional field in |
384 | unconditional versions of the instruction, or -1 if nothing is | |
385 | appropriate. */ | |
386 | int uncond_value; | |
5287ad62 | 387 | struct neon_type vectype; |
88714cb8 DG |
388 | /* This does not indicate an actual NEON instruction, only that |
389 | the mnemonic accepts neon-style type suffixes. */ | |
390 | int is_neon; | |
0110f2b8 PB |
391 | /* Set to the opcode if the instruction needs relaxation. |
392 | Zero if the instruction is not relaxed. */ | |
393 | unsigned long relax; | |
b99bd4ef NC |
394 | struct |
395 | { | |
396 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
397 | expressionS exp; |
398 | int pc_rel; | |
b99bd4ef | 399 | } reloc; |
b99bd4ef | 400 | |
e07e6e58 NC |
401 | enum it_instruction_type it_insn_type; |
402 | ||
c19d1205 ZW |
403 | struct |
404 | { | |
405 | unsigned reg; | |
ca3f61f7 | 406 | signed int imm; |
dcbf9037 | 407 | struct neon_type_el vectype; |
ca3f61f7 NC |
408 | unsigned present : 1; /* Operand present. */ |
409 | unsigned isreg : 1; /* Operand was a register. */ | |
410 | unsigned immisreg : 1; /* .imm field is a second register. */ | |
5287ad62 JB |
411 | unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ |
412 | unsigned immisalign : 1; /* Immediate is an alignment specifier. */ | |
c96612cc | 413 | unsigned immisfloat : 1; /* Immediate was parsed as a float. */ |
5287ad62 JB |
414 | /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV |
415 | instructions. This allows us to disambiguate ARM <-> vector insns. */ | |
416 | unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ | |
037e8744 | 417 | unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ |
5287ad62 | 418 | unsigned isquad : 1; /* Operand is Neon quad-precision register. */ |
037e8744 | 419 | unsigned issingle : 1; /* Operand is VFP single-precision register. */ |
ca3f61f7 NC |
420 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ |
421 | unsigned writeback : 1; /* Operand has trailing ! */ | |
422 | unsigned preind : 1; /* Preindexed address. */ | |
423 | unsigned postind : 1; /* Postindexed address. */ | |
424 | unsigned negative : 1; /* Index register was negated. */ | |
425 | unsigned shifted : 1; /* Shift applied to operation. */ | |
426 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
ad6cec43 | 427 | } operands[ARM_IT_MAX_OPERANDS]; |
b99bd4ef NC |
428 | }; |
429 | ||
c19d1205 | 430 | static struct arm_it inst; |
b99bd4ef NC |
431 | |
432 | #define NUM_FLOAT_VALS 8 | |
433 | ||
05d2d07e | 434 | const char * fp_const[] = |
b99bd4ef NC |
435 | { |
436 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
437 | }; | |
438 | ||
c19d1205 | 439 | /* Number of littlenums required to hold an extended precision number. */ |
b99bd4ef NC |
440 | #define MAX_LITTLENUMS 6 |
441 | ||
442 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
443 | ||
444 | #define FAIL (-1) | |
445 | #define SUCCESS (0) | |
446 | ||
447 | #define SUFF_S 1 | |
448 | #define SUFF_D 2 | |
449 | #define SUFF_E 3 | |
450 | #define SUFF_P 4 | |
451 | ||
c19d1205 ZW |
452 | #define CP_T_X 0x00008000 |
453 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 454 | |
c19d1205 ZW |
455 | #define CONDS_BIT 0x00100000 |
456 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
457 | |
458 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
459 | ||
460 | struct asm_cond | |
461 | { | |
d3ce72d0 | 462 | const char * template_name; |
c921be7d | 463 | unsigned long value; |
b99bd4ef NC |
464 | }; |
465 | ||
c19d1205 | 466 | #define COND_ALWAYS 0xE |
b99bd4ef | 467 | |
b99bd4ef NC |
468 | struct asm_psr |
469 | { | |
d3ce72d0 | 470 | const char * template_name; |
c921be7d | 471 | unsigned long field; |
b99bd4ef NC |
472 | }; |
473 | ||
62b3e311 PB |
474 | struct asm_barrier_opt |
475 | { | |
e797f7e0 MGD |
476 | const char * template_name; |
477 | unsigned long value; | |
478 | const arm_feature_set arch; | |
62b3e311 PB |
479 | }; |
480 | ||
2d2255b5 | 481 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
482 | #define SPSR_BIT (1 << 22) |
483 | ||
c19d1205 ZW |
484 | /* The individual PSR flag bits. */ |
485 | #define PSR_c (1 << 16) | |
486 | #define PSR_x (1 << 17) | |
487 | #define PSR_s (1 << 18) | |
488 | #define PSR_f (1 << 19) | |
b99bd4ef | 489 | |
c19d1205 | 490 | struct reloc_entry |
bfae80f2 | 491 | { |
c921be7d NC |
492 | char * name; |
493 | bfd_reloc_code_real_type reloc; | |
bfae80f2 RE |
494 | }; |
495 | ||
5287ad62 | 496 | enum vfp_reg_pos |
bfae80f2 | 497 | { |
5287ad62 JB |
498 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, |
499 | VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn | |
bfae80f2 RE |
500 | }; |
501 | ||
502 | enum vfp_ldstm_type | |
503 | { | |
504 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
505 | }; | |
506 | ||
dcbf9037 JB |
507 | /* Bits for DEFINED field in neon_typed_alias. */ |
508 | #define NTA_HASTYPE 1 | |
509 | #define NTA_HASINDEX 2 | |
510 | ||
511 | struct neon_typed_alias | |
512 | { | |
c921be7d NC |
513 | unsigned char defined; |
514 | unsigned char index; | |
515 | struct neon_type_el eltype; | |
dcbf9037 JB |
516 | }; |
517 | ||
c19d1205 ZW |
518 | /* ARM register categories. This includes coprocessor numbers and various |
519 | architecture extensions' registers. */ | |
520 | enum arm_reg_type | |
bfae80f2 | 521 | { |
c19d1205 ZW |
522 | REG_TYPE_RN, |
523 | REG_TYPE_CP, | |
524 | REG_TYPE_CN, | |
525 | REG_TYPE_FN, | |
526 | REG_TYPE_VFS, | |
527 | REG_TYPE_VFD, | |
5287ad62 | 528 | REG_TYPE_NQ, |
037e8744 | 529 | REG_TYPE_VFSD, |
5287ad62 | 530 | REG_TYPE_NDQ, |
037e8744 | 531 | REG_TYPE_NSDQ, |
c19d1205 ZW |
532 | REG_TYPE_VFC, |
533 | REG_TYPE_MVF, | |
534 | REG_TYPE_MVD, | |
535 | REG_TYPE_MVFX, | |
536 | REG_TYPE_MVDX, | |
537 | REG_TYPE_MVAX, | |
538 | REG_TYPE_DSPSC, | |
539 | REG_TYPE_MMXWR, | |
540 | REG_TYPE_MMXWC, | |
541 | REG_TYPE_MMXWCG, | |
542 | REG_TYPE_XSCALE, | |
90ec0d68 | 543 | REG_TYPE_RNB |
bfae80f2 RE |
544 | }; |
545 | ||
dcbf9037 JB |
546 | /* Structure for a hash table entry for a register. |
547 | If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra | |
548 | information which states whether a vector type or index is specified (for a | |
549 | register alias created with .dn or .qn). Otherwise NEON should be NULL. */ | |
6c43fab6 RE |
550 | struct reg_entry |
551 | { | |
c921be7d | 552 | const char * name; |
90ec0d68 | 553 | unsigned int number; |
c921be7d NC |
554 | unsigned char type; |
555 | unsigned char builtin; | |
556 | struct neon_typed_alias * neon; | |
6c43fab6 RE |
557 | }; |
558 | ||
c19d1205 | 559 | /* Diagnostics used when we don't get a register of the expected type. */ |
c921be7d | 560 | const char * const reg_expected_msgs[] = |
c19d1205 ZW |
561 | { |
562 | N_("ARM register expected"), | |
563 | N_("bad or missing co-processor number"), | |
564 | N_("co-processor register expected"), | |
565 | N_("FPA register expected"), | |
566 | N_("VFP single precision register expected"), | |
5287ad62 JB |
567 | N_("VFP/Neon double precision register expected"), |
568 | N_("Neon quad precision register expected"), | |
037e8744 | 569 | N_("VFP single or double precision register expected"), |
5287ad62 | 570 | N_("Neon double or quad precision register expected"), |
037e8744 | 571 | N_("VFP single, double or Neon quad precision register expected"), |
c19d1205 ZW |
572 | N_("VFP system register expected"), |
573 | N_("Maverick MVF register expected"), | |
574 | N_("Maverick MVD register expected"), | |
575 | N_("Maverick MVFX register expected"), | |
576 | N_("Maverick MVDX register expected"), | |
577 | N_("Maverick MVAX register expected"), | |
578 | N_("Maverick DSPSC register expected"), | |
579 | N_("iWMMXt data register expected"), | |
580 | N_("iWMMXt control register expected"), | |
581 | N_("iWMMXt scalar register expected"), | |
582 | N_("XScale accumulator register expected"), | |
6c43fab6 RE |
583 | }; |
584 | ||
c19d1205 | 585 | /* Some well known registers that we refer to directly elsewhere. */ |
bd340a04 | 586 | #define REG_R12 12 |
c19d1205 ZW |
587 | #define REG_SP 13 |
588 | #define REG_LR 14 | |
589 | #define REG_PC 15 | |
404ff6b5 | 590 | |
b99bd4ef NC |
591 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
592 | take 2: */ | |
c19d1205 | 593 | #define INSN_SIZE 4 |
b99bd4ef NC |
594 | |
595 | struct asm_opcode | |
596 | { | |
597 | /* Basic string to match. */ | |
d3ce72d0 | 598 | const char * template_name; |
c19d1205 ZW |
599 | |
600 | /* Parameters to instruction. */ | |
5be8be5d | 601 | unsigned int operands[8]; |
c19d1205 ZW |
602 | |
603 | /* Conditional tag - see opcode_lookup. */ | |
604 | unsigned int tag : 4; | |
b99bd4ef NC |
605 | |
606 | /* Basic instruction code. */ | |
c19d1205 | 607 | unsigned int avalue : 28; |
b99bd4ef | 608 | |
c19d1205 ZW |
609 | /* Thumb-format instruction code. */ |
610 | unsigned int tvalue; | |
b99bd4ef | 611 | |
90e4755a | 612 | /* Which architecture variant provides this instruction. */ |
c921be7d NC |
613 | const arm_feature_set * avariant; |
614 | const arm_feature_set * tvariant; | |
c19d1205 ZW |
615 | |
616 | /* Function to call to encode instruction in ARM format. */ | |
617 | void (* aencode) (void); | |
b99bd4ef | 618 | |
c19d1205 ZW |
619 | /* Function to call to encode instruction in Thumb format. */ |
620 | void (* tencode) (void); | |
b99bd4ef NC |
621 | }; |
622 | ||
a737bd4d NC |
623 | /* Defines for various bits that we will want to toggle. */ |
624 | #define INST_IMMEDIATE 0x02000000 | |
625 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 626 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
627 | #define SHIFT_BY_REG 0x00000010 |
628 | #define PRE_INDEX 0x01000000 | |
629 | #define INDEX_UP 0x00800000 | |
630 | #define WRITE_BACK 0x00200000 | |
631 | #define LDM_TYPE_2_OR_3 0x00400000 | |
a028a6f5 | 632 | #define CPSI_MMOD 0x00020000 |
90e4755a | 633 | |
a737bd4d NC |
634 | #define LITERAL_MASK 0xf000f000 |
635 | #define OPCODE_MASK 0xfe1fffff | |
636 | #define V4_STR_BIT 0x00000020 | |
8335d6aa | 637 | #define VLDR_VMOV_SAME 0x0040f000 |
90e4755a | 638 | |
efd81785 PB |
639 | #define T2_SUBS_PC_LR 0xf3de8f00 |
640 | ||
a737bd4d | 641 | #define DATA_OP_SHIFT 21 |
90e4755a | 642 | |
ef8d22e6 PB |
643 | #define T2_OPCODE_MASK 0xfe1fffff |
644 | #define T2_DATA_OP_SHIFT 21 | |
645 | ||
6530b175 NC |
646 | #define A_COND_MASK 0xf0000000 |
647 | #define A_PUSH_POP_OP_MASK 0x0fff0000 | |
648 | ||
649 | /* Opcodes for pushing/poping registers to/from the stack. */ | |
650 | #define A1_OPCODE_PUSH 0x092d0000 | |
651 | #define A2_OPCODE_PUSH 0x052d0004 | |
652 | #define A2_OPCODE_POP 0x049d0004 | |
653 | ||
a737bd4d NC |
654 | /* Codes to distinguish the arithmetic instructions. */ |
655 | #define OPCODE_AND 0 | |
656 | #define OPCODE_EOR 1 | |
657 | #define OPCODE_SUB 2 | |
658 | #define OPCODE_RSB 3 | |
659 | #define OPCODE_ADD 4 | |
660 | #define OPCODE_ADC 5 | |
661 | #define OPCODE_SBC 6 | |
662 | #define OPCODE_RSC 7 | |
663 | #define OPCODE_TST 8 | |
664 | #define OPCODE_TEQ 9 | |
665 | #define OPCODE_CMP 10 | |
666 | #define OPCODE_CMN 11 | |
667 | #define OPCODE_ORR 12 | |
668 | #define OPCODE_MOV 13 | |
669 | #define OPCODE_BIC 14 | |
670 | #define OPCODE_MVN 15 | |
90e4755a | 671 | |
ef8d22e6 PB |
672 | #define T2_OPCODE_AND 0 |
673 | #define T2_OPCODE_BIC 1 | |
674 | #define T2_OPCODE_ORR 2 | |
675 | #define T2_OPCODE_ORN 3 | |
676 | #define T2_OPCODE_EOR 4 | |
677 | #define T2_OPCODE_ADD 8 | |
678 | #define T2_OPCODE_ADC 10 | |
679 | #define T2_OPCODE_SBC 11 | |
680 | #define T2_OPCODE_SUB 13 | |
681 | #define T2_OPCODE_RSB 14 | |
682 | ||
a737bd4d NC |
683 | #define T_OPCODE_MUL 0x4340 |
684 | #define T_OPCODE_TST 0x4200 | |
685 | #define T_OPCODE_CMN 0x42c0 | |
686 | #define T_OPCODE_NEG 0x4240 | |
687 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 688 | |
a737bd4d NC |
689 | #define T_OPCODE_ADD_R3 0x1800 |
690 | #define T_OPCODE_SUB_R3 0x1a00 | |
691 | #define T_OPCODE_ADD_HI 0x4400 | |
692 | #define T_OPCODE_ADD_ST 0xb000 | |
693 | #define T_OPCODE_SUB_ST 0xb080 | |
694 | #define T_OPCODE_ADD_SP 0xa800 | |
695 | #define T_OPCODE_ADD_PC 0xa000 | |
696 | #define T_OPCODE_ADD_I8 0x3000 | |
697 | #define T_OPCODE_SUB_I8 0x3800 | |
698 | #define T_OPCODE_ADD_I3 0x1c00 | |
699 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 700 | |
a737bd4d NC |
701 | #define T_OPCODE_ASR_R 0x4100 |
702 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
703 | #define T_OPCODE_LSR_R 0x40c0 |
704 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
705 | #define T_OPCODE_ASR_I 0x1000 |
706 | #define T_OPCODE_LSL_I 0x0000 | |
707 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 708 | |
a737bd4d NC |
709 | #define T_OPCODE_MOV_I8 0x2000 |
710 | #define T_OPCODE_CMP_I8 0x2800 | |
711 | #define T_OPCODE_CMP_LR 0x4280 | |
712 | #define T_OPCODE_MOV_HR 0x4600 | |
713 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 714 | |
a737bd4d NC |
715 | #define T_OPCODE_LDR_PC 0x4800 |
716 | #define T_OPCODE_LDR_SP 0x9800 | |
717 | #define T_OPCODE_STR_SP 0x9000 | |
718 | #define T_OPCODE_LDR_IW 0x6800 | |
719 | #define T_OPCODE_STR_IW 0x6000 | |
720 | #define T_OPCODE_LDR_IH 0x8800 | |
721 | #define T_OPCODE_STR_IH 0x8000 | |
722 | #define T_OPCODE_LDR_IB 0x7800 | |
723 | #define T_OPCODE_STR_IB 0x7000 | |
724 | #define T_OPCODE_LDR_RW 0x5800 | |
725 | #define T_OPCODE_STR_RW 0x5000 | |
726 | #define T_OPCODE_LDR_RH 0x5a00 | |
727 | #define T_OPCODE_STR_RH 0x5200 | |
728 | #define T_OPCODE_LDR_RB 0x5c00 | |
729 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 730 | |
a737bd4d NC |
731 | #define T_OPCODE_PUSH 0xb400 |
732 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 733 | |
2fc8bdac | 734 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 735 | |
a737bd4d | 736 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 737 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 | 738 | #define THUMB_LOAD_BIT 0x0800 |
53365c0d | 739 | #define THUMB2_LOAD_BIT 0x00100000 |
c19d1205 ZW |
740 | |
741 | #define BAD_ARGS _("bad arguments to instruction") | |
fdfde340 | 742 | #define BAD_SP _("r13 not allowed here") |
c19d1205 ZW |
743 | #define BAD_PC _("r15 not allowed here") |
744 | #define BAD_COND _("instruction cannot be conditional") | |
745 | #define BAD_OVERLAP _("registers may not be the same") | |
746 | #define BAD_HIREG _("lo register required") | |
747 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
01cfc07f | 748 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); |
dfa9f0d5 PB |
749 | #define BAD_BRANCH _("branch must be last instruction in IT block") |
750 | #define BAD_NOT_IT _("instruction not allowed in IT block") | |
037e8744 | 751 | #define BAD_FPU _("selected FPU does not support instruction") |
e07e6e58 NC |
752 | #define BAD_OUT_IT _("thumb conditional instruction should be in IT block") |
753 | #define BAD_IT_COND _("incorrect condition in IT block") | |
754 | #define BAD_IT_IT _("IT falling in the range of a previous IT block") | |
921e5f0a | 755 | #define MISSING_FNSTART _("missing .fnstart before unwinding directive") |
5be8be5d DG |
756 | #define BAD_PC_ADDRESSING \ |
757 | _("cannot use register index with PC-relative addressing") | |
758 | #define BAD_PC_WRITEBACK \ | |
759 | _("cannot use writeback with PC-relative addressing") | |
08f10d51 | 760 | #define BAD_RANGE _("branch out of range") |
dd5181d5 | 761 | #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour") |
c19d1205 | 762 | |
c921be7d NC |
763 | static struct hash_control * arm_ops_hsh; |
764 | static struct hash_control * arm_cond_hsh; | |
765 | static struct hash_control * arm_shift_hsh; | |
766 | static struct hash_control * arm_psr_hsh; | |
767 | static struct hash_control * arm_v7m_psr_hsh; | |
768 | static struct hash_control * arm_reg_hsh; | |
769 | static struct hash_control * arm_reloc_hsh; | |
770 | static struct hash_control * arm_barrier_opt_hsh; | |
b99bd4ef | 771 | |
b99bd4ef NC |
772 | /* Stuff needed to resolve the label ambiguity |
773 | As: | |
774 | ... | |
775 | label: <insn> | |
776 | may differ from: | |
777 | ... | |
778 | label: | |
5f4273c7 | 779 | <insn> */ |
b99bd4ef NC |
780 | |
781 | symbolS * last_label_seen; | |
b34976b6 | 782 | static int label_is_thumb_function_name = FALSE; |
e07e6e58 | 783 | |
3d0c9500 NC |
784 | /* Literal pool structure. Held on a per-section |
785 | and per-sub-section basis. */ | |
a737bd4d | 786 | |
c19d1205 | 787 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 788 | typedef struct literal_pool |
b99bd4ef | 789 | { |
c921be7d NC |
790 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
791 | unsigned int next_free_entry; | |
792 | unsigned int id; | |
793 | symbolS * symbol; | |
794 | segT section; | |
795 | subsegT sub_section; | |
a8040cf2 NC |
796 | #ifdef OBJ_ELF |
797 | struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE]; | |
798 | #endif | |
c921be7d | 799 | struct literal_pool * next; |
8335d6aa | 800 | unsigned int alignment; |
3d0c9500 | 801 | } literal_pool; |
b99bd4ef | 802 | |
3d0c9500 NC |
803 | /* Pointer to a linked list of literal pools. */ |
804 | literal_pool * list_of_pools = NULL; | |
e27ec89e | 805 | |
2e6976a8 DG |
806 | typedef enum asmfunc_states |
807 | { | |
808 | OUTSIDE_ASMFUNC, | |
809 | WAITING_ASMFUNC_NAME, | |
810 | WAITING_ENDASMFUNC | |
811 | } asmfunc_states; | |
812 | ||
813 | static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC; | |
814 | ||
e07e6e58 NC |
815 | #ifdef OBJ_ELF |
816 | # define now_it seg_info (now_seg)->tc_segment_info_data.current_it | |
817 | #else | |
818 | static struct current_it now_it; | |
819 | #endif | |
820 | ||
821 | static inline int | |
822 | now_it_compatible (int cond) | |
823 | { | |
824 | return (cond & ~1) == (now_it.cc & ~1); | |
825 | } | |
826 | ||
827 | static inline int | |
828 | conditional_insn (void) | |
829 | { | |
830 | return inst.cond != COND_ALWAYS; | |
831 | } | |
832 | ||
833 | static int in_it_block (void); | |
834 | ||
835 | static int handle_it_state (void); | |
836 | ||
837 | static void force_automatic_it_block_close (void); | |
838 | ||
c921be7d NC |
839 | static void it_fsm_post_encode (void); |
840 | ||
e07e6e58 NC |
841 | #define set_it_insn_type(type) \ |
842 | do \ | |
843 | { \ | |
844 | inst.it_insn_type = type; \ | |
845 | if (handle_it_state () == FAIL) \ | |
477330fc | 846 | return; \ |
e07e6e58 NC |
847 | } \ |
848 | while (0) | |
849 | ||
c921be7d NC |
850 | #define set_it_insn_type_nonvoid(type, failret) \ |
851 | do \ | |
852 | { \ | |
853 | inst.it_insn_type = type; \ | |
854 | if (handle_it_state () == FAIL) \ | |
477330fc | 855 | return failret; \ |
c921be7d NC |
856 | } \ |
857 | while(0) | |
858 | ||
e07e6e58 NC |
859 | #define set_it_insn_type_last() \ |
860 | do \ | |
861 | { \ | |
862 | if (inst.cond == COND_ALWAYS) \ | |
477330fc | 863 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \ |
e07e6e58 | 864 | else \ |
477330fc | 865 | set_it_insn_type (INSIDE_IT_LAST_INSN); \ |
e07e6e58 NC |
866 | } \ |
867 | while (0) | |
868 | ||
c19d1205 | 869 | /* Pure syntax. */ |
b99bd4ef | 870 | |
c19d1205 ZW |
871 | /* This array holds the chars that always start a comment. If the |
872 | pre-processor is disabled, these aren't very useful. */ | |
2e6976a8 | 873 | char arm_comment_chars[] = "@"; |
3d0c9500 | 874 | |
c19d1205 ZW |
875 | /* This array holds the chars that only start a comment at the beginning of |
876 | a line. If the line seems to have the form '# 123 filename' | |
877 | .line and .file directives will appear in the pre-processed output. */ | |
878 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
879 | first line of the input file. This is because the compiler outputs | |
880 | #NO_APP at the beginning of its output. */ | |
881 | /* Also note that comments like this one will always work. */ | |
882 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 883 | |
2e6976a8 | 884 | char arm_line_separator_chars[] = ";"; |
b99bd4ef | 885 | |
c19d1205 ZW |
886 | /* Chars that can be used to separate mant |
887 | from exp in floating point numbers. */ | |
888 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 889 | |
c19d1205 ZW |
890 | /* Chars that mean this number is a floating point constant. */ |
891 | /* As in 0f12.456 */ | |
892 | /* or 0d1.2345e12 */ | |
b99bd4ef | 893 | |
c19d1205 | 894 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 895 | |
c19d1205 ZW |
896 | /* Prefix characters that indicate the start of an immediate |
897 | value. */ | |
898 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 899 | |
c19d1205 ZW |
900 | /* Separator character handling. */ |
901 | ||
902 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
903 | ||
904 | static inline int | |
905 | skip_past_char (char ** str, char c) | |
906 | { | |
8ab8155f NC |
907 | /* PR gas/14987: Allow for whitespace before the expected character. */ |
908 | skip_whitespace (*str); | |
427d0db6 | 909 | |
c19d1205 ZW |
910 | if (**str == c) |
911 | { | |
912 | (*str)++; | |
913 | return SUCCESS; | |
3d0c9500 | 914 | } |
c19d1205 ZW |
915 | else |
916 | return FAIL; | |
917 | } | |
c921be7d | 918 | |
c19d1205 | 919 | #define skip_past_comma(str) skip_past_char (str, ',') |
3d0c9500 | 920 | |
c19d1205 ZW |
921 | /* Arithmetic expressions (possibly involving symbols). */ |
922 | ||
923 | /* Return TRUE if anything in the expression is a bignum. */ | |
924 | ||
925 | static int | |
926 | walk_no_bignums (symbolS * sp) | |
927 | { | |
928 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
929 | return 1; | |
930 | ||
931 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 932 | { |
c19d1205 ZW |
933 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
934 | || (symbol_get_value_expression (sp)->X_op_symbol | |
935 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
936 | } |
937 | ||
c19d1205 | 938 | return 0; |
3d0c9500 NC |
939 | } |
940 | ||
c19d1205 ZW |
941 | static int in_my_get_expression = 0; |
942 | ||
943 | /* Third argument to my_get_expression. */ | |
944 | #define GE_NO_PREFIX 0 | |
945 | #define GE_IMM_PREFIX 1 | |
946 | #define GE_OPT_PREFIX 2 | |
5287ad62 JB |
947 | /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) |
948 | immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ | |
949 | #define GE_OPT_PREFIX_BIG 3 | |
a737bd4d | 950 | |
b99bd4ef | 951 | static int |
c19d1205 | 952 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 953 | { |
c19d1205 ZW |
954 | char * save_in; |
955 | segT seg; | |
b99bd4ef | 956 | |
c19d1205 ZW |
957 | /* In unified syntax, all prefixes are optional. */ |
958 | if (unified_syntax) | |
5287ad62 | 959 | prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode |
477330fc | 960 | : GE_OPT_PREFIX; |
b99bd4ef | 961 | |
c19d1205 | 962 | switch (prefix_mode) |
b99bd4ef | 963 | { |
c19d1205 ZW |
964 | case GE_NO_PREFIX: break; |
965 | case GE_IMM_PREFIX: | |
966 | if (!is_immediate_prefix (**str)) | |
967 | { | |
968 | inst.error = _("immediate expression requires a # prefix"); | |
969 | return FAIL; | |
970 | } | |
971 | (*str)++; | |
972 | break; | |
973 | case GE_OPT_PREFIX: | |
5287ad62 | 974 | case GE_OPT_PREFIX_BIG: |
c19d1205 ZW |
975 | if (is_immediate_prefix (**str)) |
976 | (*str)++; | |
977 | break; | |
978 | default: abort (); | |
979 | } | |
b99bd4ef | 980 | |
c19d1205 | 981 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 982 | |
c19d1205 ZW |
983 | save_in = input_line_pointer; |
984 | input_line_pointer = *str; | |
985 | in_my_get_expression = 1; | |
986 | seg = expression (ep); | |
987 | in_my_get_expression = 0; | |
988 | ||
f86adc07 | 989 | if (ep->X_op == O_illegal || ep->X_op == O_absent) |
b99bd4ef | 990 | { |
f86adc07 | 991 | /* We found a bad or missing expression in md_operand(). */ |
c19d1205 ZW |
992 | *str = input_line_pointer; |
993 | input_line_pointer = save_in; | |
994 | if (inst.error == NULL) | |
f86adc07 NS |
995 | inst.error = (ep->X_op == O_absent |
996 | ? _("missing expression") :_("bad expression")); | |
c19d1205 ZW |
997 | return 1; |
998 | } | |
b99bd4ef | 999 | |
c19d1205 ZW |
1000 | #ifdef OBJ_AOUT |
1001 | if (seg != absolute_section | |
1002 | && seg != text_section | |
1003 | && seg != data_section | |
1004 | && seg != bss_section | |
1005 | && seg != undefined_section) | |
1006 | { | |
1007 | inst.error = _("bad segment"); | |
1008 | *str = input_line_pointer; | |
1009 | input_line_pointer = save_in; | |
1010 | return 1; | |
b99bd4ef | 1011 | } |
87975d2a AM |
1012 | #else |
1013 | (void) seg; | |
c19d1205 | 1014 | #endif |
b99bd4ef | 1015 | |
c19d1205 ZW |
1016 | /* Get rid of any bignums now, so that we don't generate an error for which |
1017 | we can't establish a line number later on. Big numbers are never valid | |
1018 | in instructions, which is where this routine is always called. */ | |
5287ad62 JB |
1019 | if (prefix_mode != GE_OPT_PREFIX_BIG |
1020 | && (ep->X_op == O_big | |
477330fc | 1021 | || (ep->X_add_symbol |
5287ad62 | 1022 | && (walk_no_bignums (ep->X_add_symbol) |
477330fc | 1023 | || (ep->X_op_symbol |
5287ad62 | 1024 | && walk_no_bignums (ep->X_op_symbol)))))) |
c19d1205 ZW |
1025 | { |
1026 | inst.error = _("invalid constant"); | |
1027 | *str = input_line_pointer; | |
1028 | input_line_pointer = save_in; | |
1029 | return 1; | |
1030 | } | |
b99bd4ef | 1031 | |
c19d1205 ZW |
1032 | *str = input_line_pointer; |
1033 | input_line_pointer = save_in; | |
1034 | return 0; | |
b99bd4ef NC |
1035 | } |
1036 | ||
c19d1205 ZW |
1037 | /* Turn a string in input_line_pointer into a floating point constant |
1038 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
1039 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
1040 | returned, or NULL on OK. | |
b99bd4ef | 1041 | |
c19d1205 ZW |
1042 | Note that fp constants aren't represent in the normal way on the ARM. |
1043 | In big endian mode, things are as expected. However, in little endian | |
1044 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
1045 | within the words. For example, (double) 1.1 in big endian mode is | |
1046 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
1047 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 1048 | |
c19d1205 | 1049 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 1050 | |
c19d1205 ZW |
1051 | char * |
1052 | md_atof (int type, char * litP, int * sizeP) | |
1053 | { | |
1054 | int prec; | |
1055 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
1056 | char *t; | |
1057 | int i; | |
b99bd4ef | 1058 | |
c19d1205 ZW |
1059 | switch (type) |
1060 | { | |
1061 | case 'f': | |
1062 | case 'F': | |
1063 | case 's': | |
1064 | case 'S': | |
1065 | prec = 2; | |
1066 | break; | |
b99bd4ef | 1067 | |
c19d1205 ZW |
1068 | case 'd': |
1069 | case 'D': | |
1070 | case 'r': | |
1071 | case 'R': | |
1072 | prec = 4; | |
1073 | break; | |
b99bd4ef | 1074 | |
c19d1205 ZW |
1075 | case 'x': |
1076 | case 'X': | |
499ac353 | 1077 | prec = 5; |
c19d1205 | 1078 | break; |
b99bd4ef | 1079 | |
c19d1205 ZW |
1080 | case 'p': |
1081 | case 'P': | |
499ac353 | 1082 | prec = 5; |
c19d1205 | 1083 | break; |
a737bd4d | 1084 | |
c19d1205 ZW |
1085 | default: |
1086 | *sizeP = 0; | |
499ac353 | 1087 | return _("Unrecognized or unsupported floating point constant"); |
c19d1205 | 1088 | } |
b99bd4ef | 1089 | |
c19d1205 ZW |
1090 | t = atof_ieee (input_line_pointer, type, words); |
1091 | if (t) | |
1092 | input_line_pointer = t; | |
499ac353 | 1093 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
b99bd4ef | 1094 | |
c19d1205 ZW |
1095 | if (target_big_endian) |
1096 | { | |
1097 | for (i = 0; i < prec; i++) | |
1098 | { | |
499ac353 NC |
1099 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1100 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1101 | } |
1102 | } | |
1103 | else | |
1104 | { | |
e74cfd16 | 1105 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
c19d1205 ZW |
1106 | for (i = prec - 1; i >= 0; i--) |
1107 | { | |
499ac353 NC |
1108 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1109 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1110 | } |
1111 | else | |
1112 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
1113 | For an 8 byte float the order is 1 0 3 2. */ | |
1114 | for (i = 0; i < prec; i += 2) | |
1115 | { | |
499ac353 NC |
1116 | md_number_to_chars (litP, (valueT) words[i + 1], |
1117 | sizeof (LITTLENUM_TYPE)); | |
1118 | md_number_to_chars (litP + sizeof (LITTLENUM_TYPE), | |
1119 | (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
1120 | litP += 2 * sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1121 | } |
1122 | } | |
b99bd4ef | 1123 | |
499ac353 | 1124 | return NULL; |
c19d1205 | 1125 | } |
b99bd4ef | 1126 | |
c19d1205 ZW |
1127 | /* We handle all bad expressions here, so that we can report the faulty |
1128 | instruction in the error message. */ | |
1129 | void | |
91d6fa6a | 1130 | md_operand (expressionS * exp) |
c19d1205 ZW |
1131 | { |
1132 | if (in_my_get_expression) | |
91d6fa6a | 1133 | exp->X_op = O_illegal; |
b99bd4ef NC |
1134 | } |
1135 | ||
c19d1205 | 1136 | /* Immediate values. */ |
b99bd4ef | 1137 | |
c19d1205 ZW |
1138 | /* Generic immediate-value read function for use in directives. |
1139 | Accepts anything that 'expression' can fold to a constant. | |
1140 | *val receives the number. */ | |
1141 | #ifdef OBJ_ELF | |
1142 | static int | |
1143 | immediate_for_directive (int *val) | |
b99bd4ef | 1144 | { |
c19d1205 ZW |
1145 | expressionS exp; |
1146 | exp.X_op = O_illegal; | |
b99bd4ef | 1147 | |
c19d1205 ZW |
1148 | if (is_immediate_prefix (*input_line_pointer)) |
1149 | { | |
1150 | input_line_pointer++; | |
1151 | expression (&exp); | |
1152 | } | |
b99bd4ef | 1153 | |
c19d1205 ZW |
1154 | if (exp.X_op != O_constant) |
1155 | { | |
1156 | as_bad (_("expected #constant")); | |
1157 | ignore_rest_of_line (); | |
1158 | return FAIL; | |
1159 | } | |
1160 | *val = exp.X_add_number; | |
1161 | return SUCCESS; | |
b99bd4ef | 1162 | } |
c19d1205 | 1163 | #endif |
b99bd4ef | 1164 | |
c19d1205 | 1165 | /* Register parsing. */ |
b99bd4ef | 1166 | |
c19d1205 ZW |
1167 | /* Generic register parser. CCP points to what should be the |
1168 | beginning of a register name. If it is indeed a valid register | |
1169 | name, advance CCP over it and return the reg_entry structure; | |
1170 | otherwise return NULL. Does not issue diagnostics. */ | |
1171 | ||
1172 | static struct reg_entry * | |
1173 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 1174 | { |
c19d1205 ZW |
1175 | char *start = *ccp; |
1176 | char *p; | |
1177 | struct reg_entry *reg; | |
b99bd4ef | 1178 | |
477330fc RM |
1179 | skip_whitespace (start); |
1180 | ||
c19d1205 ZW |
1181 | #ifdef REGISTER_PREFIX |
1182 | if (*start != REGISTER_PREFIX) | |
01cfc07f | 1183 | return NULL; |
c19d1205 ZW |
1184 | start++; |
1185 | #endif | |
1186 | #ifdef OPTIONAL_REGISTER_PREFIX | |
1187 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
1188 | start++; | |
1189 | #endif | |
b99bd4ef | 1190 | |
c19d1205 ZW |
1191 | p = start; |
1192 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
1193 | return NULL; | |
b99bd4ef | 1194 | |
c19d1205 ZW |
1195 | do |
1196 | p++; | |
1197 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
1198 | ||
1199 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
1200 | ||
1201 | if (!reg) | |
1202 | return NULL; | |
1203 | ||
1204 | *ccp = p; | |
1205 | return reg; | |
b99bd4ef NC |
1206 | } |
1207 | ||
1208 | static int | |
dcbf9037 | 1209 | arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, |
477330fc | 1210 | enum arm_reg_type type) |
b99bd4ef | 1211 | { |
c19d1205 ZW |
1212 | /* Alternative syntaxes are accepted for a few register classes. */ |
1213 | switch (type) | |
1214 | { | |
1215 | case REG_TYPE_MVF: | |
1216 | case REG_TYPE_MVD: | |
1217 | case REG_TYPE_MVFX: | |
1218 | case REG_TYPE_MVDX: | |
1219 | /* Generic coprocessor register names are allowed for these. */ | |
79134647 | 1220 | if (reg && reg->type == REG_TYPE_CN) |
c19d1205 ZW |
1221 | return reg->number; |
1222 | break; | |
69b97547 | 1223 | |
c19d1205 ZW |
1224 | case REG_TYPE_CP: |
1225 | /* For backward compatibility, a bare number is valid here. */ | |
1226 | { | |
1227 | unsigned long processor = strtoul (start, ccp, 10); | |
1228 | if (*ccp != start && processor <= 15) | |
1229 | return processor; | |
1230 | } | |
6057a28f | 1231 | |
c19d1205 ZW |
1232 | case REG_TYPE_MMXWC: |
1233 | /* WC includes WCG. ??? I'm not sure this is true for all | |
1234 | instructions that take WC registers. */ | |
79134647 | 1235 | if (reg && reg->type == REG_TYPE_MMXWCG) |
c19d1205 | 1236 | return reg->number; |
6057a28f | 1237 | break; |
c19d1205 | 1238 | |
6057a28f | 1239 | default: |
c19d1205 | 1240 | break; |
6057a28f NC |
1241 | } |
1242 | ||
dcbf9037 JB |
1243 | return FAIL; |
1244 | } | |
1245 | ||
1246 | /* As arm_reg_parse_multi, but the register must be of type TYPE, and the | |
1247 | return value is the register number or FAIL. */ | |
1248 | ||
1249 | static int | |
1250 | arm_reg_parse (char **ccp, enum arm_reg_type type) | |
1251 | { | |
1252 | char *start = *ccp; | |
1253 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
1254 | int ret; | |
1255 | ||
1256 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1257 | if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) | |
1258 | return FAIL; | |
1259 | ||
1260 | if (reg && reg->type == type) | |
1261 | return reg->number; | |
1262 | ||
1263 | if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) | |
1264 | return ret; | |
1265 | ||
c19d1205 ZW |
1266 | *ccp = start; |
1267 | return FAIL; | |
1268 | } | |
69b97547 | 1269 | |
dcbf9037 JB |
1270 | /* Parse a Neon type specifier. *STR should point at the leading '.' |
1271 | character. Does no verification at this stage that the type fits the opcode | |
1272 | properly. E.g., | |
1273 | ||
1274 | .i32.i32.s16 | |
1275 | .s32.f32 | |
1276 | .u16 | |
1277 | ||
1278 | Can all be legally parsed by this function. | |
1279 | ||
1280 | Fills in neon_type struct pointer with parsed information, and updates STR | |
1281 | to point after the parsed type specifier. Returns SUCCESS if this was a legal | |
1282 | type, FAIL if not. */ | |
1283 | ||
1284 | static int | |
1285 | parse_neon_type (struct neon_type *type, char **str) | |
1286 | { | |
1287 | char *ptr = *str; | |
1288 | ||
1289 | if (type) | |
1290 | type->elems = 0; | |
1291 | ||
1292 | while (type->elems < NEON_MAX_TYPE_ELS) | |
1293 | { | |
1294 | enum neon_el_type thistype = NT_untyped; | |
1295 | unsigned thissize = -1u; | |
1296 | ||
1297 | if (*ptr != '.') | |
1298 | break; | |
1299 | ||
1300 | ptr++; | |
1301 | ||
1302 | /* Just a size without an explicit type. */ | |
1303 | if (ISDIGIT (*ptr)) | |
1304 | goto parsesize; | |
1305 | ||
1306 | switch (TOLOWER (*ptr)) | |
1307 | { | |
1308 | case 'i': thistype = NT_integer; break; | |
1309 | case 'f': thistype = NT_float; break; | |
1310 | case 'p': thistype = NT_poly; break; | |
1311 | case 's': thistype = NT_signed; break; | |
1312 | case 'u': thistype = NT_unsigned; break; | |
477330fc RM |
1313 | case 'd': |
1314 | thistype = NT_float; | |
1315 | thissize = 64; | |
1316 | ptr++; | |
1317 | goto done; | |
dcbf9037 JB |
1318 | default: |
1319 | as_bad (_("unexpected character `%c' in type specifier"), *ptr); | |
1320 | return FAIL; | |
1321 | } | |
1322 | ||
1323 | ptr++; | |
1324 | ||
1325 | /* .f is an abbreviation for .f32. */ | |
1326 | if (thistype == NT_float && !ISDIGIT (*ptr)) | |
1327 | thissize = 32; | |
1328 | else | |
1329 | { | |
1330 | parsesize: | |
1331 | thissize = strtoul (ptr, &ptr, 10); | |
1332 | ||
1333 | if (thissize != 8 && thissize != 16 && thissize != 32 | |
477330fc RM |
1334 | && thissize != 64) |
1335 | { | |
1336 | as_bad (_("bad size %d in type specifier"), thissize); | |
dcbf9037 JB |
1337 | return FAIL; |
1338 | } | |
1339 | } | |
1340 | ||
037e8744 | 1341 | done: |
dcbf9037 | 1342 | if (type) |
477330fc RM |
1343 | { |
1344 | type->el[type->elems].type = thistype; | |
dcbf9037 JB |
1345 | type->el[type->elems].size = thissize; |
1346 | type->elems++; | |
1347 | } | |
1348 | } | |
1349 | ||
1350 | /* Empty/missing type is not a successful parse. */ | |
1351 | if (type->elems == 0) | |
1352 | return FAIL; | |
1353 | ||
1354 | *str = ptr; | |
1355 | ||
1356 | return SUCCESS; | |
1357 | } | |
1358 | ||
1359 | /* Errors may be set multiple times during parsing or bit encoding | |
1360 | (particularly in the Neon bits), but usually the earliest error which is set | |
1361 | will be the most meaningful. Avoid overwriting it with later (cascading) | |
1362 | errors by calling this function. */ | |
1363 | ||
1364 | static void | |
1365 | first_error (const char *err) | |
1366 | { | |
1367 | if (!inst.error) | |
1368 | inst.error = err; | |
1369 | } | |
1370 | ||
1371 | /* Parse a single type, e.g. ".s32", leading period included. */ | |
1372 | static int | |
1373 | parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) | |
1374 | { | |
1375 | char *str = *ccp; | |
1376 | struct neon_type optype; | |
1377 | ||
1378 | if (*str == '.') | |
1379 | { | |
1380 | if (parse_neon_type (&optype, &str) == SUCCESS) | |
477330fc RM |
1381 | { |
1382 | if (optype.elems == 1) | |
1383 | *vectype = optype.el[0]; | |
1384 | else | |
1385 | { | |
1386 | first_error (_("only one type should be specified for operand")); | |
1387 | return FAIL; | |
1388 | } | |
1389 | } | |
dcbf9037 | 1390 | else |
477330fc RM |
1391 | { |
1392 | first_error (_("vector type expected")); | |
1393 | return FAIL; | |
1394 | } | |
dcbf9037 JB |
1395 | } |
1396 | else | |
1397 | return FAIL; | |
5f4273c7 | 1398 | |
dcbf9037 | 1399 | *ccp = str; |
5f4273c7 | 1400 | |
dcbf9037 JB |
1401 | return SUCCESS; |
1402 | } | |
1403 | ||
1404 | /* Special meanings for indices (which have a range of 0-7), which will fit into | |
1405 | a 4-bit integer. */ | |
1406 | ||
1407 | #define NEON_ALL_LANES 15 | |
1408 | #define NEON_INTERLEAVE_LANES 14 | |
1409 | ||
1410 | /* Parse either a register or a scalar, with an optional type. Return the | |
1411 | register number, and optionally fill in the actual type of the register | |
1412 | when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and | |
1413 | type/index information in *TYPEINFO. */ | |
1414 | ||
1415 | static int | |
1416 | parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, | |
477330fc RM |
1417 | enum arm_reg_type *rtype, |
1418 | struct neon_typed_alias *typeinfo) | |
dcbf9037 JB |
1419 | { |
1420 | char *str = *ccp; | |
1421 | struct reg_entry *reg = arm_reg_parse_multi (&str); | |
1422 | struct neon_typed_alias atype; | |
1423 | struct neon_type_el parsetype; | |
1424 | ||
1425 | atype.defined = 0; | |
1426 | atype.index = -1; | |
1427 | atype.eltype.type = NT_invtype; | |
1428 | atype.eltype.size = -1; | |
1429 | ||
1430 | /* Try alternate syntax for some types of register. Note these are mutually | |
1431 | exclusive with the Neon syntax extensions. */ | |
1432 | if (reg == NULL) | |
1433 | { | |
1434 | int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); | |
1435 | if (altreg != FAIL) | |
477330fc | 1436 | *ccp = str; |
dcbf9037 | 1437 | if (typeinfo) |
477330fc | 1438 | *typeinfo = atype; |
dcbf9037 JB |
1439 | return altreg; |
1440 | } | |
1441 | ||
037e8744 JB |
1442 | /* Undo polymorphism when a set of register types may be accepted. */ |
1443 | if ((type == REG_TYPE_NDQ | |
1444 | && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) | |
1445 | || (type == REG_TYPE_VFSD | |
477330fc | 1446 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) |
037e8744 | 1447 | || (type == REG_TYPE_NSDQ |
477330fc RM |
1448 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD |
1449 | || reg->type == REG_TYPE_NQ)) | |
f512f76f NC |
1450 | || (type == REG_TYPE_MMXWC |
1451 | && (reg->type == REG_TYPE_MMXWCG))) | |
21d799b5 | 1452 | type = (enum arm_reg_type) reg->type; |
dcbf9037 JB |
1453 | |
1454 | if (type != reg->type) | |
1455 | return FAIL; | |
1456 | ||
1457 | if (reg->neon) | |
1458 | atype = *reg->neon; | |
5f4273c7 | 1459 | |
dcbf9037 JB |
1460 | if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) |
1461 | { | |
1462 | if ((atype.defined & NTA_HASTYPE) != 0) | |
477330fc RM |
1463 | { |
1464 | first_error (_("can't redefine type for operand")); | |
1465 | return FAIL; | |
1466 | } | |
dcbf9037 JB |
1467 | atype.defined |= NTA_HASTYPE; |
1468 | atype.eltype = parsetype; | |
1469 | } | |
5f4273c7 | 1470 | |
dcbf9037 JB |
1471 | if (skip_past_char (&str, '[') == SUCCESS) |
1472 | { | |
1473 | if (type != REG_TYPE_VFD) | |
477330fc RM |
1474 | { |
1475 | first_error (_("only D registers may be indexed")); | |
1476 | return FAIL; | |
1477 | } | |
5f4273c7 | 1478 | |
dcbf9037 | 1479 | if ((atype.defined & NTA_HASINDEX) != 0) |
477330fc RM |
1480 | { |
1481 | first_error (_("can't change index for operand")); | |
1482 | return FAIL; | |
1483 | } | |
dcbf9037 JB |
1484 | |
1485 | atype.defined |= NTA_HASINDEX; | |
1486 | ||
1487 | if (skip_past_char (&str, ']') == SUCCESS) | |
477330fc | 1488 | atype.index = NEON_ALL_LANES; |
dcbf9037 | 1489 | else |
477330fc RM |
1490 | { |
1491 | expressionS exp; | |
dcbf9037 | 1492 | |
477330fc | 1493 | my_get_expression (&exp, &str, GE_NO_PREFIX); |
dcbf9037 | 1494 | |
477330fc RM |
1495 | if (exp.X_op != O_constant) |
1496 | { | |
1497 | first_error (_("constant expression required")); | |
1498 | return FAIL; | |
1499 | } | |
dcbf9037 | 1500 | |
477330fc RM |
1501 | if (skip_past_char (&str, ']') == FAIL) |
1502 | return FAIL; | |
dcbf9037 | 1503 | |
477330fc RM |
1504 | atype.index = exp.X_add_number; |
1505 | } | |
dcbf9037 | 1506 | } |
5f4273c7 | 1507 | |
dcbf9037 JB |
1508 | if (typeinfo) |
1509 | *typeinfo = atype; | |
5f4273c7 | 1510 | |
dcbf9037 JB |
1511 | if (rtype) |
1512 | *rtype = type; | |
5f4273c7 | 1513 | |
dcbf9037 | 1514 | *ccp = str; |
5f4273c7 | 1515 | |
dcbf9037 JB |
1516 | return reg->number; |
1517 | } | |
1518 | ||
1519 | /* Like arm_reg_parse, but allow allow the following extra features: | |
1520 | - If RTYPE is non-zero, return the (possibly restricted) type of the | |
1521 | register (e.g. Neon double or quad reg when either has been requested). | |
1522 | - If this is a Neon vector type with additional type information, fill | |
1523 | in the struct pointed to by VECTYPE (if non-NULL). | |
5f4273c7 | 1524 | This function will fault on encountering a scalar. */ |
dcbf9037 JB |
1525 | |
1526 | static int | |
1527 | arm_typed_reg_parse (char **ccp, enum arm_reg_type type, | |
477330fc | 1528 | enum arm_reg_type *rtype, struct neon_type_el *vectype) |
dcbf9037 JB |
1529 | { |
1530 | struct neon_typed_alias atype; | |
1531 | char *str = *ccp; | |
1532 | int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); | |
1533 | ||
1534 | if (reg == FAIL) | |
1535 | return FAIL; | |
1536 | ||
0855e32b NS |
1537 | /* Do not allow regname(... to parse as a register. */ |
1538 | if (*str == '(') | |
1539 | return FAIL; | |
1540 | ||
dcbf9037 JB |
1541 | /* Do not allow a scalar (reg+index) to parse as a register. */ |
1542 | if ((atype.defined & NTA_HASINDEX) != 0) | |
1543 | { | |
1544 | first_error (_("register operand expected, but got scalar")); | |
1545 | return FAIL; | |
1546 | } | |
1547 | ||
1548 | if (vectype) | |
1549 | *vectype = atype.eltype; | |
1550 | ||
1551 | *ccp = str; | |
1552 | ||
1553 | return reg; | |
1554 | } | |
1555 | ||
1556 | #define NEON_SCALAR_REG(X) ((X) >> 4) | |
1557 | #define NEON_SCALAR_INDEX(X) ((X) & 15) | |
1558 | ||
5287ad62 JB |
1559 | /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't |
1560 | have enough information to be able to do a good job bounds-checking. So, we | |
1561 | just do easy checks here, and do further checks later. */ | |
1562 | ||
1563 | static int | |
dcbf9037 | 1564 | parse_scalar (char **ccp, int elsize, struct neon_type_el *type) |
5287ad62 | 1565 | { |
dcbf9037 | 1566 | int reg; |
5287ad62 | 1567 | char *str = *ccp; |
dcbf9037 | 1568 | struct neon_typed_alias atype; |
5f4273c7 | 1569 | |
dcbf9037 | 1570 | reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); |
5f4273c7 | 1571 | |
dcbf9037 | 1572 | if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) |
5287ad62 | 1573 | return FAIL; |
5f4273c7 | 1574 | |
dcbf9037 | 1575 | if (atype.index == NEON_ALL_LANES) |
5287ad62 | 1576 | { |
dcbf9037 | 1577 | first_error (_("scalar must have an index")); |
5287ad62 JB |
1578 | return FAIL; |
1579 | } | |
dcbf9037 | 1580 | else if (atype.index >= 64 / elsize) |
5287ad62 | 1581 | { |
dcbf9037 | 1582 | first_error (_("scalar index out of range")); |
5287ad62 JB |
1583 | return FAIL; |
1584 | } | |
5f4273c7 | 1585 | |
dcbf9037 JB |
1586 | if (type) |
1587 | *type = atype.eltype; | |
5f4273c7 | 1588 | |
5287ad62 | 1589 | *ccp = str; |
5f4273c7 | 1590 | |
dcbf9037 | 1591 | return reg * 16 + atype.index; |
5287ad62 JB |
1592 | } |
1593 | ||
c19d1205 | 1594 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
e07e6e58 | 1595 | |
c19d1205 ZW |
1596 | static long |
1597 | parse_reg_list (char ** strp) | |
1598 | { | |
1599 | char * str = * strp; | |
1600 | long range = 0; | |
1601 | int another_range; | |
a737bd4d | 1602 | |
c19d1205 ZW |
1603 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
1604 | do | |
6057a28f | 1605 | { |
477330fc RM |
1606 | skip_whitespace (str); |
1607 | ||
c19d1205 | 1608 | another_range = 0; |
a737bd4d | 1609 | |
c19d1205 ZW |
1610 | if (*str == '{') |
1611 | { | |
1612 | int in_range = 0; | |
1613 | int cur_reg = -1; | |
a737bd4d | 1614 | |
c19d1205 ZW |
1615 | str++; |
1616 | do | |
1617 | { | |
1618 | int reg; | |
6057a28f | 1619 | |
dcbf9037 | 1620 | if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) |
c19d1205 | 1621 | { |
dcbf9037 | 1622 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 ZW |
1623 | return FAIL; |
1624 | } | |
a737bd4d | 1625 | |
c19d1205 ZW |
1626 | if (in_range) |
1627 | { | |
1628 | int i; | |
a737bd4d | 1629 | |
c19d1205 ZW |
1630 | if (reg <= cur_reg) |
1631 | { | |
dcbf9037 | 1632 | first_error (_("bad range in register list")); |
c19d1205 ZW |
1633 | return FAIL; |
1634 | } | |
40a18ebd | 1635 | |
c19d1205 ZW |
1636 | for (i = cur_reg + 1; i < reg; i++) |
1637 | { | |
1638 | if (range & (1 << i)) | |
1639 | as_tsktsk | |
1640 | (_("Warning: duplicated register (r%d) in register list"), | |
1641 | i); | |
1642 | else | |
1643 | range |= 1 << i; | |
1644 | } | |
1645 | in_range = 0; | |
1646 | } | |
a737bd4d | 1647 | |
c19d1205 ZW |
1648 | if (range & (1 << reg)) |
1649 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
1650 | reg); | |
1651 | else if (reg <= cur_reg) | |
1652 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 1653 | |
c19d1205 ZW |
1654 | range |= 1 << reg; |
1655 | cur_reg = reg; | |
1656 | } | |
1657 | while (skip_past_comma (&str) != FAIL | |
1658 | || (in_range = 1, *str++ == '-')); | |
1659 | str--; | |
a737bd4d | 1660 | |
d996d970 | 1661 | if (skip_past_char (&str, '}') == FAIL) |
c19d1205 | 1662 | { |
dcbf9037 | 1663 | first_error (_("missing `}'")); |
c19d1205 ZW |
1664 | return FAIL; |
1665 | } | |
1666 | } | |
1667 | else | |
1668 | { | |
91d6fa6a | 1669 | expressionS exp; |
40a18ebd | 1670 | |
91d6fa6a | 1671 | if (my_get_expression (&exp, &str, GE_NO_PREFIX)) |
c19d1205 | 1672 | return FAIL; |
40a18ebd | 1673 | |
91d6fa6a | 1674 | if (exp.X_op == O_constant) |
c19d1205 | 1675 | { |
91d6fa6a NC |
1676 | if (exp.X_add_number |
1677 | != (exp.X_add_number & 0x0000ffff)) | |
c19d1205 ZW |
1678 | { |
1679 | inst.error = _("invalid register mask"); | |
1680 | return FAIL; | |
1681 | } | |
a737bd4d | 1682 | |
91d6fa6a | 1683 | if ((range & exp.X_add_number) != 0) |
c19d1205 | 1684 | { |
91d6fa6a | 1685 | int regno = range & exp.X_add_number; |
a737bd4d | 1686 | |
c19d1205 ZW |
1687 | regno &= -regno; |
1688 | regno = (1 << regno) - 1; | |
1689 | as_tsktsk | |
1690 | (_("Warning: duplicated register (r%d) in register list"), | |
1691 | regno); | |
1692 | } | |
a737bd4d | 1693 | |
91d6fa6a | 1694 | range |= exp.X_add_number; |
c19d1205 ZW |
1695 | } |
1696 | else | |
1697 | { | |
1698 | if (inst.reloc.type != 0) | |
1699 | { | |
1700 | inst.error = _("expression too complex"); | |
1701 | return FAIL; | |
1702 | } | |
a737bd4d | 1703 | |
91d6fa6a | 1704 | memcpy (&inst.reloc.exp, &exp, sizeof (expressionS)); |
c19d1205 ZW |
1705 | inst.reloc.type = BFD_RELOC_ARM_MULTI; |
1706 | inst.reloc.pc_rel = 0; | |
1707 | } | |
1708 | } | |
a737bd4d | 1709 | |
c19d1205 ZW |
1710 | if (*str == '|' || *str == '+') |
1711 | { | |
1712 | str++; | |
1713 | another_range = 1; | |
1714 | } | |
a737bd4d | 1715 | } |
c19d1205 | 1716 | while (another_range); |
a737bd4d | 1717 | |
c19d1205 ZW |
1718 | *strp = str; |
1719 | return range; | |
a737bd4d NC |
1720 | } |
1721 | ||
5287ad62 JB |
1722 | /* Types of registers in a list. */ |
1723 | ||
1724 | enum reg_list_els | |
1725 | { | |
1726 | REGLIST_VFP_S, | |
1727 | REGLIST_VFP_D, | |
1728 | REGLIST_NEON_D | |
1729 | }; | |
1730 | ||
c19d1205 ZW |
1731 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1732 | Otherwise return the number of registers, and set PBASE to the first | |
5287ad62 JB |
1733 | register. Parses registers of type ETYPE. |
1734 | If REGLIST_NEON_D is used, several syntax enhancements are enabled: | |
1735 | - Q registers can be used to specify pairs of D registers | |
1736 | - { } can be omitted from around a singleton register list | |
477330fc RM |
1737 | FIXME: This is not implemented, as it would require backtracking in |
1738 | some cases, e.g.: | |
1739 | vtbl.8 d3,d4,d5 | |
1740 | This could be done (the meaning isn't really ambiguous), but doesn't | |
1741 | fit in well with the current parsing framework. | |
dcbf9037 JB |
1742 | - 32 D registers may be used (also true for VFPv3). |
1743 | FIXME: Types are ignored in these register lists, which is probably a | |
1744 | bug. */ | |
6057a28f | 1745 | |
c19d1205 | 1746 | static int |
037e8744 | 1747 | parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) |
6057a28f | 1748 | { |
037e8744 | 1749 | char *str = *ccp; |
c19d1205 ZW |
1750 | int base_reg; |
1751 | int new_base; | |
21d799b5 | 1752 | enum arm_reg_type regtype = (enum arm_reg_type) 0; |
5287ad62 | 1753 | int max_regs = 0; |
c19d1205 ZW |
1754 | int count = 0; |
1755 | int warned = 0; | |
1756 | unsigned long mask = 0; | |
a737bd4d | 1757 | int i; |
6057a28f | 1758 | |
477330fc | 1759 | if (skip_past_char (&str, '{') == FAIL) |
5287ad62 JB |
1760 | { |
1761 | inst.error = _("expecting {"); | |
1762 | return FAIL; | |
1763 | } | |
6057a28f | 1764 | |
5287ad62 | 1765 | switch (etype) |
c19d1205 | 1766 | { |
5287ad62 | 1767 | case REGLIST_VFP_S: |
c19d1205 ZW |
1768 | regtype = REG_TYPE_VFS; |
1769 | max_regs = 32; | |
5287ad62 | 1770 | break; |
5f4273c7 | 1771 | |
5287ad62 JB |
1772 | case REGLIST_VFP_D: |
1773 | regtype = REG_TYPE_VFD; | |
b7fc2769 | 1774 | break; |
5f4273c7 | 1775 | |
b7fc2769 JB |
1776 | case REGLIST_NEON_D: |
1777 | regtype = REG_TYPE_NDQ; | |
1778 | break; | |
1779 | } | |
1780 | ||
1781 | if (etype != REGLIST_VFP_S) | |
1782 | { | |
b1cc4aeb PB |
1783 | /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */ |
1784 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) | |
477330fc RM |
1785 | { |
1786 | max_regs = 32; | |
1787 | if (thumb_mode) | |
1788 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
1789 | fpu_vfp_ext_d32); | |
1790 | else | |
1791 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
1792 | fpu_vfp_ext_d32); | |
1793 | } | |
5287ad62 | 1794 | else |
477330fc | 1795 | max_regs = 16; |
c19d1205 | 1796 | } |
6057a28f | 1797 | |
c19d1205 | 1798 | base_reg = max_regs; |
a737bd4d | 1799 | |
c19d1205 ZW |
1800 | do |
1801 | { | |
5287ad62 | 1802 | int setmask = 1, addregs = 1; |
dcbf9037 | 1803 | |
037e8744 | 1804 | new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); |
dcbf9037 | 1805 | |
c19d1205 | 1806 | if (new_base == FAIL) |
a737bd4d | 1807 | { |
dcbf9037 | 1808 | first_error (_(reg_expected_msgs[regtype])); |
c19d1205 ZW |
1809 | return FAIL; |
1810 | } | |
5f4273c7 | 1811 | |
b7fc2769 | 1812 | if (new_base >= max_regs) |
477330fc RM |
1813 | { |
1814 | first_error (_("register out of range in list")); | |
1815 | return FAIL; | |
1816 | } | |
5f4273c7 | 1817 | |
5287ad62 JB |
1818 | /* Note: a value of 2 * n is returned for the register Q<n>. */ |
1819 | if (regtype == REG_TYPE_NQ) | |
477330fc RM |
1820 | { |
1821 | setmask = 3; | |
1822 | addregs = 2; | |
1823 | } | |
5287ad62 | 1824 | |
c19d1205 ZW |
1825 | if (new_base < base_reg) |
1826 | base_reg = new_base; | |
a737bd4d | 1827 | |
5287ad62 | 1828 | if (mask & (setmask << new_base)) |
c19d1205 | 1829 | { |
dcbf9037 | 1830 | first_error (_("invalid register list")); |
c19d1205 | 1831 | return FAIL; |
a737bd4d | 1832 | } |
a737bd4d | 1833 | |
c19d1205 ZW |
1834 | if ((mask >> new_base) != 0 && ! warned) |
1835 | { | |
1836 | as_tsktsk (_("register list not in ascending order")); | |
1837 | warned = 1; | |
1838 | } | |
0bbf2aa4 | 1839 | |
5287ad62 JB |
1840 | mask |= setmask << new_base; |
1841 | count += addregs; | |
0bbf2aa4 | 1842 | |
037e8744 | 1843 | if (*str == '-') /* We have the start of a range expression */ |
c19d1205 ZW |
1844 | { |
1845 | int high_range; | |
0bbf2aa4 | 1846 | |
037e8744 | 1847 | str++; |
0bbf2aa4 | 1848 | |
037e8744 | 1849 | if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) |
477330fc | 1850 | == FAIL) |
c19d1205 ZW |
1851 | { |
1852 | inst.error = gettext (reg_expected_msgs[regtype]); | |
1853 | return FAIL; | |
1854 | } | |
0bbf2aa4 | 1855 | |
477330fc RM |
1856 | if (high_range >= max_regs) |
1857 | { | |
1858 | first_error (_("register out of range in list")); | |
1859 | return FAIL; | |
1860 | } | |
b7fc2769 | 1861 | |
477330fc RM |
1862 | if (regtype == REG_TYPE_NQ) |
1863 | high_range = high_range + 1; | |
5287ad62 | 1864 | |
c19d1205 ZW |
1865 | if (high_range <= new_base) |
1866 | { | |
1867 | inst.error = _("register range not in ascending order"); | |
1868 | return FAIL; | |
1869 | } | |
0bbf2aa4 | 1870 | |
5287ad62 | 1871 | for (new_base += addregs; new_base <= high_range; new_base += addregs) |
0bbf2aa4 | 1872 | { |
5287ad62 | 1873 | if (mask & (setmask << new_base)) |
0bbf2aa4 | 1874 | { |
c19d1205 ZW |
1875 | inst.error = _("invalid register list"); |
1876 | return FAIL; | |
0bbf2aa4 | 1877 | } |
c19d1205 | 1878 | |
5287ad62 JB |
1879 | mask |= setmask << new_base; |
1880 | count += addregs; | |
0bbf2aa4 | 1881 | } |
0bbf2aa4 | 1882 | } |
0bbf2aa4 | 1883 | } |
037e8744 | 1884 | while (skip_past_comma (&str) != FAIL); |
0bbf2aa4 | 1885 | |
037e8744 | 1886 | str++; |
0bbf2aa4 | 1887 | |
c19d1205 ZW |
1888 | /* Sanity check -- should have raised a parse error above. */ |
1889 | if (count == 0 || count > max_regs) | |
1890 | abort (); | |
1891 | ||
1892 | *pbase = base_reg; | |
1893 | ||
1894 | /* Final test -- the registers must be consecutive. */ | |
1895 | mask >>= base_reg; | |
1896 | for (i = 0; i < count; i++) | |
1897 | { | |
1898 | if ((mask & (1u << i)) == 0) | |
1899 | { | |
1900 | inst.error = _("non-contiguous register range"); | |
1901 | return FAIL; | |
1902 | } | |
1903 | } | |
1904 | ||
037e8744 JB |
1905 | *ccp = str; |
1906 | ||
c19d1205 | 1907 | return count; |
b99bd4ef NC |
1908 | } |
1909 | ||
dcbf9037 JB |
1910 | /* True if two alias types are the same. */ |
1911 | ||
c921be7d | 1912 | static bfd_boolean |
dcbf9037 JB |
1913 | neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) |
1914 | { | |
1915 | if (!a && !b) | |
c921be7d | 1916 | return TRUE; |
5f4273c7 | 1917 | |
dcbf9037 | 1918 | if (!a || !b) |
c921be7d | 1919 | return FALSE; |
dcbf9037 JB |
1920 | |
1921 | if (a->defined != b->defined) | |
c921be7d | 1922 | return FALSE; |
5f4273c7 | 1923 | |
dcbf9037 JB |
1924 | if ((a->defined & NTA_HASTYPE) != 0 |
1925 | && (a->eltype.type != b->eltype.type | |
477330fc | 1926 | || a->eltype.size != b->eltype.size)) |
c921be7d | 1927 | return FALSE; |
dcbf9037 JB |
1928 | |
1929 | if ((a->defined & NTA_HASINDEX) != 0 | |
1930 | && (a->index != b->index)) | |
c921be7d | 1931 | return FALSE; |
5f4273c7 | 1932 | |
c921be7d | 1933 | return TRUE; |
dcbf9037 JB |
1934 | } |
1935 | ||
5287ad62 JB |
1936 | /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. |
1937 | The base register is put in *PBASE. | |
dcbf9037 | 1938 | The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of |
5287ad62 JB |
1939 | the return value. |
1940 | The register stride (minus one) is put in bit 4 of the return value. | |
dcbf9037 JB |
1941 | Bits [6:5] encode the list length (minus one). |
1942 | The type of the list elements is put in *ELTYPE, if non-NULL. */ | |
5287ad62 | 1943 | |
5287ad62 | 1944 | #define NEON_LANE(X) ((X) & 0xf) |
dcbf9037 | 1945 | #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) |
5287ad62 JB |
1946 | #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) |
1947 | ||
1948 | static int | |
dcbf9037 | 1949 | parse_neon_el_struct_list (char **str, unsigned *pbase, |
477330fc | 1950 | struct neon_type_el *eltype) |
5287ad62 JB |
1951 | { |
1952 | char *ptr = *str; | |
1953 | int base_reg = -1; | |
1954 | int reg_incr = -1; | |
1955 | int count = 0; | |
1956 | int lane = -1; | |
1957 | int leading_brace = 0; | |
1958 | enum arm_reg_type rtype = REG_TYPE_NDQ; | |
20203fb9 NC |
1959 | const char *const incr_error = _("register stride must be 1 or 2"); |
1960 | const char *const type_error = _("mismatched element/structure types in list"); | |
dcbf9037 | 1961 | struct neon_typed_alias firsttype; |
5f4273c7 | 1962 | |
5287ad62 JB |
1963 | if (skip_past_char (&ptr, '{') == SUCCESS) |
1964 | leading_brace = 1; | |
5f4273c7 | 1965 | |
5287ad62 JB |
1966 | do |
1967 | { | |
dcbf9037 JB |
1968 | struct neon_typed_alias atype; |
1969 | int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); | |
1970 | ||
5287ad62 | 1971 | if (getreg == FAIL) |
477330fc RM |
1972 | { |
1973 | first_error (_(reg_expected_msgs[rtype])); | |
1974 | return FAIL; | |
1975 | } | |
5f4273c7 | 1976 | |
5287ad62 | 1977 | if (base_reg == -1) |
477330fc RM |
1978 | { |
1979 | base_reg = getreg; | |
1980 | if (rtype == REG_TYPE_NQ) | |
1981 | { | |
1982 | reg_incr = 1; | |
1983 | } | |
1984 | firsttype = atype; | |
1985 | } | |
5287ad62 | 1986 | else if (reg_incr == -1) |
477330fc RM |
1987 | { |
1988 | reg_incr = getreg - base_reg; | |
1989 | if (reg_incr < 1 || reg_incr > 2) | |
1990 | { | |
1991 | first_error (_(incr_error)); | |
1992 | return FAIL; | |
1993 | } | |
1994 | } | |
5287ad62 | 1995 | else if (getreg != base_reg + reg_incr * count) |
477330fc RM |
1996 | { |
1997 | first_error (_(incr_error)); | |
1998 | return FAIL; | |
1999 | } | |
dcbf9037 | 2000 | |
c921be7d | 2001 | if (! neon_alias_types_same (&atype, &firsttype)) |
477330fc RM |
2002 | { |
2003 | first_error (_(type_error)); | |
2004 | return FAIL; | |
2005 | } | |
5f4273c7 | 2006 | |
5287ad62 | 2007 | /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list |
477330fc | 2008 | modes. */ |
5287ad62 | 2009 | if (ptr[0] == '-') |
477330fc RM |
2010 | { |
2011 | struct neon_typed_alias htype; | |
2012 | int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; | |
2013 | if (lane == -1) | |
2014 | lane = NEON_INTERLEAVE_LANES; | |
2015 | else if (lane != NEON_INTERLEAVE_LANES) | |
2016 | { | |
2017 | first_error (_(type_error)); | |
2018 | return FAIL; | |
2019 | } | |
2020 | if (reg_incr == -1) | |
2021 | reg_incr = 1; | |
2022 | else if (reg_incr != 1) | |
2023 | { | |
2024 | first_error (_("don't use Rn-Rm syntax with non-unit stride")); | |
2025 | return FAIL; | |
2026 | } | |
2027 | ptr++; | |
2028 | hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); | |
2029 | if (hireg == FAIL) | |
2030 | { | |
2031 | first_error (_(reg_expected_msgs[rtype])); | |
2032 | return FAIL; | |
2033 | } | |
2034 | if (! neon_alias_types_same (&htype, &firsttype)) | |
2035 | { | |
2036 | first_error (_(type_error)); | |
2037 | return FAIL; | |
2038 | } | |
2039 | count += hireg + dregs - getreg; | |
2040 | continue; | |
2041 | } | |
5f4273c7 | 2042 | |
5287ad62 JB |
2043 | /* If we're using Q registers, we can't use [] or [n] syntax. */ |
2044 | if (rtype == REG_TYPE_NQ) | |
477330fc RM |
2045 | { |
2046 | count += 2; | |
2047 | continue; | |
2048 | } | |
5f4273c7 | 2049 | |
dcbf9037 | 2050 | if ((atype.defined & NTA_HASINDEX) != 0) |
477330fc RM |
2051 | { |
2052 | if (lane == -1) | |
2053 | lane = atype.index; | |
2054 | else if (lane != atype.index) | |
2055 | { | |
2056 | first_error (_(type_error)); | |
2057 | return FAIL; | |
2058 | } | |
2059 | } | |
5287ad62 | 2060 | else if (lane == -1) |
477330fc | 2061 | lane = NEON_INTERLEAVE_LANES; |
5287ad62 | 2062 | else if (lane != NEON_INTERLEAVE_LANES) |
477330fc RM |
2063 | { |
2064 | first_error (_(type_error)); | |
2065 | return FAIL; | |
2066 | } | |
5287ad62 JB |
2067 | count++; |
2068 | } | |
2069 | while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); | |
5f4273c7 | 2070 | |
5287ad62 JB |
2071 | /* No lane set by [x]. We must be interleaving structures. */ |
2072 | if (lane == -1) | |
2073 | lane = NEON_INTERLEAVE_LANES; | |
5f4273c7 | 2074 | |
5287ad62 JB |
2075 | /* Sanity check. */ |
2076 | if (lane == -1 || base_reg == -1 || count < 1 || count > 4 | |
2077 | || (count > 1 && reg_incr == -1)) | |
2078 | { | |
dcbf9037 | 2079 | first_error (_("error parsing element/structure list")); |
5287ad62 JB |
2080 | return FAIL; |
2081 | } | |
2082 | ||
2083 | if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) | |
2084 | { | |
dcbf9037 | 2085 | first_error (_("expected }")); |
5287ad62 JB |
2086 | return FAIL; |
2087 | } | |
5f4273c7 | 2088 | |
5287ad62 JB |
2089 | if (reg_incr == -1) |
2090 | reg_incr = 1; | |
2091 | ||
dcbf9037 JB |
2092 | if (eltype) |
2093 | *eltype = firsttype.eltype; | |
2094 | ||
5287ad62 JB |
2095 | *pbase = base_reg; |
2096 | *str = ptr; | |
5f4273c7 | 2097 | |
5287ad62 JB |
2098 | return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); |
2099 | } | |
2100 | ||
c19d1205 ZW |
2101 | /* Parse an explicit relocation suffix on an expression. This is |
2102 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
2103 | arm_reloc_hsh contains no entries, so this function can only | |
2104 | succeed if there is no () after the word. Returns -1 on error, | |
2105 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
3da1d841 | 2106 | |
c19d1205 ZW |
2107 | static int |
2108 | parse_reloc (char **str) | |
b99bd4ef | 2109 | { |
c19d1205 ZW |
2110 | struct reloc_entry *r; |
2111 | char *p, *q; | |
b99bd4ef | 2112 | |
c19d1205 ZW |
2113 | if (**str != '(') |
2114 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 2115 | |
c19d1205 ZW |
2116 | p = *str + 1; |
2117 | q = p; | |
2118 | ||
2119 | while (*q && *q != ')' && *q != ',') | |
2120 | q++; | |
2121 | if (*q != ')') | |
2122 | return -1; | |
2123 | ||
21d799b5 NC |
2124 | if ((r = (struct reloc_entry *) |
2125 | hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
c19d1205 ZW |
2126 | return -1; |
2127 | ||
2128 | *str = q + 1; | |
2129 | return r->reloc; | |
b99bd4ef NC |
2130 | } |
2131 | ||
c19d1205 ZW |
2132 | /* Directives: register aliases. */ |
2133 | ||
dcbf9037 | 2134 | static struct reg_entry * |
90ec0d68 | 2135 | insert_reg_alias (char *str, unsigned number, int type) |
b99bd4ef | 2136 | { |
d3ce72d0 | 2137 | struct reg_entry *new_reg; |
c19d1205 | 2138 | const char *name; |
b99bd4ef | 2139 | |
d3ce72d0 | 2140 | if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0) |
c19d1205 | 2141 | { |
d3ce72d0 | 2142 | if (new_reg->builtin) |
c19d1205 | 2143 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); |
b99bd4ef | 2144 | |
c19d1205 ZW |
2145 | /* Only warn about a redefinition if it's not defined as the |
2146 | same register. */ | |
d3ce72d0 | 2147 | else if (new_reg->number != number || new_reg->type != type) |
c19d1205 | 2148 | as_warn (_("ignoring redefinition of register alias '%s'"), str); |
69b97547 | 2149 | |
d929913e | 2150 | return NULL; |
c19d1205 | 2151 | } |
b99bd4ef | 2152 | |
c19d1205 | 2153 | name = xstrdup (str); |
d3ce72d0 | 2154 | new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry)); |
b99bd4ef | 2155 | |
d3ce72d0 NC |
2156 | new_reg->name = name; |
2157 | new_reg->number = number; | |
2158 | new_reg->type = type; | |
2159 | new_reg->builtin = FALSE; | |
2160 | new_reg->neon = NULL; | |
b99bd4ef | 2161 | |
d3ce72d0 | 2162 | if (hash_insert (arm_reg_hsh, name, (void *) new_reg)) |
c19d1205 | 2163 | abort (); |
5f4273c7 | 2164 | |
d3ce72d0 | 2165 | return new_reg; |
dcbf9037 JB |
2166 | } |
2167 | ||
2168 | static void | |
2169 | insert_neon_reg_alias (char *str, int number, int type, | |
477330fc | 2170 | struct neon_typed_alias *atype) |
dcbf9037 JB |
2171 | { |
2172 | struct reg_entry *reg = insert_reg_alias (str, number, type); | |
5f4273c7 | 2173 | |
dcbf9037 JB |
2174 | if (!reg) |
2175 | { | |
2176 | first_error (_("attempt to redefine typed alias")); | |
2177 | return; | |
2178 | } | |
5f4273c7 | 2179 | |
dcbf9037 JB |
2180 | if (atype) |
2181 | { | |
21d799b5 | 2182 | reg->neon = (struct neon_typed_alias *) |
477330fc | 2183 | xmalloc (sizeof (struct neon_typed_alias)); |
dcbf9037 JB |
2184 | *reg->neon = *atype; |
2185 | } | |
c19d1205 | 2186 | } |
b99bd4ef | 2187 | |
c19d1205 | 2188 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 2189 | |
c19d1205 | 2190 | new_register_name .req existing_register_name |
b99bd4ef | 2191 | |
c19d1205 | 2192 | If we find one, or if it looks sufficiently like one that we want to |
d929913e | 2193 | handle any error here, return TRUE. Otherwise return FALSE. */ |
b99bd4ef | 2194 | |
d929913e | 2195 | static bfd_boolean |
c19d1205 ZW |
2196 | create_register_alias (char * newname, char *p) |
2197 | { | |
2198 | struct reg_entry *old; | |
2199 | char *oldname, *nbuf; | |
2200 | size_t nlen; | |
b99bd4ef | 2201 | |
c19d1205 ZW |
2202 | /* The input scrubber ensures that whitespace after the mnemonic is |
2203 | collapsed to single spaces. */ | |
2204 | oldname = p; | |
2205 | if (strncmp (oldname, " .req ", 6) != 0) | |
d929913e | 2206 | return FALSE; |
b99bd4ef | 2207 | |
c19d1205 ZW |
2208 | oldname += 6; |
2209 | if (*oldname == '\0') | |
d929913e | 2210 | return FALSE; |
b99bd4ef | 2211 | |
21d799b5 | 2212 | old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname); |
c19d1205 | 2213 | if (!old) |
b99bd4ef | 2214 | { |
c19d1205 | 2215 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
d929913e | 2216 | return TRUE; |
b99bd4ef NC |
2217 | } |
2218 | ||
c19d1205 ZW |
2219 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2220 | the desired alias name, and p points to its end. If not, then | |
2221 | the desired alias name is in the global original_case_string. */ | |
2222 | #ifdef TC_CASE_SENSITIVE | |
2223 | nlen = p - newname; | |
2224 | #else | |
2225 | newname = original_case_string; | |
2226 | nlen = strlen (newname); | |
2227 | #endif | |
b99bd4ef | 2228 | |
21d799b5 | 2229 | nbuf = (char *) alloca (nlen + 1); |
c19d1205 ZW |
2230 | memcpy (nbuf, newname, nlen); |
2231 | nbuf[nlen] = '\0'; | |
b99bd4ef | 2232 | |
c19d1205 ZW |
2233 | /* Create aliases under the new name as stated; an all-lowercase |
2234 | version of the new name; and an all-uppercase version of the new | |
2235 | name. */ | |
d929913e NC |
2236 | if (insert_reg_alias (nbuf, old->number, old->type) != NULL) |
2237 | { | |
2238 | for (p = nbuf; *p; p++) | |
2239 | *p = TOUPPER (*p); | |
c19d1205 | 2240 | |
d929913e NC |
2241 | if (strncmp (nbuf, newname, nlen)) |
2242 | { | |
2243 | /* If this attempt to create an additional alias fails, do not bother | |
2244 | trying to create the all-lower case alias. We will fail and issue | |
2245 | a second, duplicate error message. This situation arises when the | |
2246 | programmer does something like: | |
2247 | foo .req r0 | |
2248 | Foo .req r1 | |
2249 | The second .req creates the "Foo" alias but then fails to create | |
5f4273c7 | 2250 | the artificial FOO alias because it has already been created by the |
d929913e NC |
2251 | first .req. */ |
2252 | if (insert_reg_alias (nbuf, old->number, old->type) == NULL) | |
2253 | return TRUE; | |
2254 | } | |
c19d1205 | 2255 | |
d929913e NC |
2256 | for (p = nbuf; *p; p++) |
2257 | *p = TOLOWER (*p); | |
c19d1205 | 2258 | |
d929913e NC |
2259 | if (strncmp (nbuf, newname, nlen)) |
2260 | insert_reg_alias (nbuf, old->number, old->type); | |
2261 | } | |
c19d1205 | 2262 | |
d929913e | 2263 | return TRUE; |
b99bd4ef NC |
2264 | } |
2265 | ||
dcbf9037 JB |
2266 | /* Create a Neon typed/indexed register alias using directives, e.g.: |
2267 | X .dn d5.s32[1] | |
2268 | Y .qn 6.s16 | |
2269 | Z .dn d7 | |
2270 | T .dn Z[0] | |
2271 | These typed registers can be used instead of the types specified after the | |
2272 | Neon mnemonic, so long as all operands given have types. Types can also be | |
2273 | specified directly, e.g.: | |
5f4273c7 | 2274 | vadd d0.s32, d1.s32, d2.s32 */ |
dcbf9037 | 2275 | |
c921be7d | 2276 | static bfd_boolean |
dcbf9037 JB |
2277 | create_neon_reg_alias (char *newname, char *p) |
2278 | { | |
2279 | enum arm_reg_type basetype; | |
2280 | struct reg_entry *basereg; | |
2281 | struct reg_entry mybasereg; | |
2282 | struct neon_type ntype; | |
2283 | struct neon_typed_alias typeinfo; | |
12d6b0b7 | 2284 | char *namebuf, *nameend ATTRIBUTE_UNUSED; |
dcbf9037 | 2285 | int namelen; |
5f4273c7 | 2286 | |
dcbf9037 JB |
2287 | typeinfo.defined = 0; |
2288 | typeinfo.eltype.type = NT_invtype; | |
2289 | typeinfo.eltype.size = -1; | |
2290 | typeinfo.index = -1; | |
5f4273c7 | 2291 | |
dcbf9037 | 2292 | nameend = p; |
5f4273c7 | 2293 | |
dcbf9037 JB |
2294 | if (strncmp (p, " .dn ", 5) == 0) |
2295 | basetype = REG_TYPE_VFD; | |
2296 | else if (strncmp (p, " .qn ", 5) == 0) | |
2297 | basetype = REG_TYPE_NQ; | |
2298 | else | |
c921be7d | 2299 | return FALSE; |
5f4273c7 | 2300 | |
dcbf9037 | 2301 | p += 5; |
5f4273c7 | 2302 | |
dcbf9037 | 2303 | if (*p == '\0') |
c921be7d | 2304 | return FALSE; |
5f4273c7 | 2305 | |
dcbf9037 JB |
2306 | basereg = arm_reg_parse_multi (&p); |
2307 | ||
2308 | if (basereg && basereg->type != basetype) | |
2309 | { | |
2310 | as_bad (_("bad type for register")); | |
c921be7d | 2311 | return FALSE; |
dcbf9037 JB |
2312 | } |
2313 | ||
2314 | if (basereg == NULL) | |
2315 | { | |
2316 | expressionS exp; | |
2317 | /* Try parsing as an integer. */ | |
2318 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
2319 | if (exp.X_op != O_constant) | |
477330fc RM |
2320 | { |
2321 | as_bad (_("expression must be constant")); | |
2322 | return FALSE; | |
2323 | } | |
dcbf9037 JB |
2324 | basereg = &mybasereg; |
2325 | basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 | |
477330fc | 2326 | : exp.X_add_number; |
dcbf9037 JB |
2327 | basereg->neon = 0; |
2328 | } | |
2329 | ||
2330 | if (basereg->neon) | |
2331 | typeinfo = *basereg->neon; | |
2332 | ||
2333 | if (parse_neon_type (&ntype, &p) == SUCCESS) | |
2334 | { | |
2335 | /* We got a type. */ | |
2336 | if (typeinfo.defined & NTA_HASTYPE) | |
477330fc RM |
2337 | { |
2338 | as_bad (_("can't redefine the type of a register alias")); | |
2339 | return FALSE; | |
2340 | } | |
5f4273c7 | 2341 | |
dcbf9037 JB |
2342 | typeinfo.defined |= NTA_HASTYPE; |
2343 | if (ntype.elems != 1) | |
477330fc RM |
2344 | { |
2345 | as_bad (_("you must specify a single type only")); | |
2346 | return FALSE; | |
2347 | } | |
dcbf9037 JB |
2348 | typeinfo.eltype = ntype.el[0]; |
2349 | } | |
5f4273c7 | 2350 | |
dcbf9037 JB |
2351 | if (skip_past_char (&p, '[') == SUCCESS) |
2352 | { | |
2353 | expressionS exp; | |
2354 | /* We got a scalar index. */ | |
5f4273c7 | 2355 | |
dcbf9037 | 2356 | if (typeinfo.defined & NTA_HASINDEX) |
477330fc RM |
2357 | { |
2358 | as_bad (_("can't redefine the index of a scalar alias")); | |
2359 | return FALSE; | |
2360 | } | |
5f4273c7 | 2361 | |
dcbf9037 | 2362 | my_get_expression (&exp, &p, GE_NO_PREFIX); |
5f4273c7 | 2363 | |
dcbf9037 | 2364 | if (exp.X_op != O_constant) |
477330fc RM |
2365 | { |
2366 | as_bad (_("scalar index must be constant")); | |
2367 | return FALSE; | |
2368 | } | |
5f4273c7 | 2369 | |
dcbf9037 JB |
2370 | typeinfo.defined |= NTA_HASINDEX; |
2371 | typeinfo.index = exp.X_add_number; | |
5f4273c7 | 2372 | |
dcbf9037 | 2373 | if (skip_past_char (&p, ']') == FAIL) |
477330fc RM |
2374 | { |
2375 | as_bad (_("expecting ]")); | |
2376 | return FALSE; | |
2377 | } | |
dcbf9037 JB |
2378 | } |
2379 | ||
15735687 NS |
2380 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2381 | the desired alias name, and p points to its end. If not, then | |
2382 | the desired alias name is in the global original_case_string. */ | |
2383 | #ifdef TC_CASE_SENSITIVE | |
dcbf9037 | 2384 | namelen = nameend - newname; |
15735687 NS |
2385 | #else |
2386 | newname = original_case_string; | |
2387 | namelen = strlen (newname); | |
2388 | #endif | |
2389 | ||
21d799b5 | 2390 | namebuf = (char *) alloca (namelen + 1); |
dcbf9037 JB |
2391 | strncpy (namebuf, newname, namelen); |
2392 | namebuf[namelen] = '\0'; | |
5f4273c7 | 2393 | |
dcbf9037 | 2394 | insert_neon_reg_alias (namebuf, basereg->number, basetype, |
477330fc | 2395 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2396 | |
dcbf9037 JB |
2397 | /* Insert name in all uppercase. */ |
2398 | for (p = namebuf; *p; p++) | |
2399 | *p = TOUPPER (*p); | |
5f4273c7 | 2400 | |
dcbf9037 JB |
2401 | if (strncmp (namebuf, newname, namelen)) |
2402 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
477330fc | 2403 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2404 | |
dcbf9037 JB |
2405 | /* Insert name in all lowercase. */ |
2406 | for (p = namebuf; *p; p++) | |
2407 | *p = TOLOWER (*p); | |
5f4273c7 | 2408 | |
dcbf9037 JB |
2409 | if (strncmp (namebuf, newname, namelen)) |
2410 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
477330fc | 2411 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2412 | |
c921be7d | 2413 | return TRUE; |
dcbf9037 JB |
2414 | } |
2415 | ||
c19d1205 ZW |
2416 | /* Should never be called, as .req goes between the alias and the |
2417 | register name, not at the beginning of the line. */ | |
c921be7d | 2418 | |
b99bd4ef | 2419 | static void |
c19d1205 | 2420 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2421 | { |
c19d1205 ZW |
2422 | as_bad (_("invalid syntax for .req directive")); |
2423 | } | |
b99bd4ef | 2424 | |
dcbf9037 JB |
2425 | static void |
2426 | s_dn (int a ATTRIBUTE_UNUSED) | |
2427 | { | |
2428 | as_bad (_("invalid syntax for .dn directive")); | |
2429 | } | |
2430 | ||
2431 | static void | |
2432 | s_qn (int a ATTRIBUTE_UNUSED) | |
2433 | { | |
2434 | as_bad (_("invalid syntax for .qn directive")); | |
2435 | } | |
2436 | ||
c19d1205 ZW |
2437 | /* The .unreq directive deletes an alias which was previously defined |
2438 | by .req. For example: | |
b99bd4ef | 2439 | |
c19d1205 ZW |
2440 | my_alias .req r11 |
2441 | .unreq my_alias */ | |
b99bd4ef NC |
2442 | |
2443 | static void | |
c19d1205 | 2444 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2445 | { |
c19d1205 ZW |
2446 | char * name; |
2447 | char saved_char; | |
b99bd4ef | 2448 | |
c19d1205 ZW |
2449 | name = input_line_pointer; |
2450 | ||
2451 | while (*input_line_pointer != 0 | |
2452 | && *input_line_pointer != ' ' | |
2453 | && *input_line_pointer != '\n') | |
2454 | ++input_line_pointer; | |
2455 | ||
2456 | saved_char = *input_line_pointer; | |
2457 | *input_line_pointer = 0; | |
2458 | ||
2459 | if (!*name) | |
2460 | as_bad (_("invalid syntax for .unreq directive")); | |
2461 | else | |
2462 | { | |
21d799b5 | 2463 | struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh, |
477330fc | 2464 | name); |
c19d1205 ZW |
2465 | |
2466 | if (!reg) | |
2467 | as_bad (_("unknown register alias '%s'"), name); | |
2468 | else if (reg->builtin) | |
a1727c1a | 2469 | as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"), |
c19d1205 ZW |
2470 | name); |
2471 | else | |
2472 | { | |
d929913e NC |
2473 | char * p; |
2474 | char * nbuf; | |
2475 | ||
db0bc284 | 2476 | hash_delete (arm_reg_hsh, name, FALSE); |
c19d1205 | 2477 | free ((char *) reg->name); |
477330fc RM |
2478 | if (reg->neon) |
2479 | free (reg->neon); | |
c19d1205 | 2480 | free (reg); |
d929913e NC |
2481 | |
2482 | /* Also locate the all upper case and all lower case versions. | |
2483 | Do not complain if we cannot find one or the other as it | |
2484 | was probably deleted above. */ | |
5f4273c7 | 2485 | |
d929913e NC |
2486 | nbuf = strdup (name); |
2487 | for (p = nbuf; *p; p++) | |
2488 | *p = TOUPPER (*p); | |
21d799b5 | 2489 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2490 | if (reg) |
2491 | { | |
db0bc284 | 2492 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2493 | free ((char *) reg->name); |
2494 | if (reg->neon) | |
2495 | free (reg->neon); | |
2496 | free (reg); | |
2497 | } | |
2498 | ||
2499 | for (p = nbuf; *p; p++) | |
2500 | *p = TOLOWER (*p); | |
21d799b5 | 2501 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2502 | if (reg) |
2503 | { | |
db0bc284 | 2504 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2505 | free ((char *) reg->name); |
2506 | if (reg->neon) | |
2507 | free (reg->neon); | |
2508 | free (reg); | |
2509 | } | |
2510 | ||
2511 | free (nbuf); | |
c19d1205 ZW |
2512 | } |
2513 | } | |
b99bd4ef | 2514 | |
c19d1205 | 2515 | *input_line_pointer = saved_char; |
b99bd4ef NC |
2516 | demand_empty_rest_of_line (); |
2517 | } | |
2518 | ||
c19d1205 ZW |
2519 | /* Directives: Instruction set selection. */ |
2520 | ||
2521 | #ifdef OBJ_ELF | |
2522 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
2523 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
2524 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
2525 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
2526 | ||
cd000bff DJ |
2527 | /* Create a new mapping symbol for the transition to STATE. */ |
2528 | ||
2529 | static void | |
2530 | make_mapping_symbol (enum mstate state, valueT value, fragS *frag) | |
b99bd4ef | 2531 | { |
a737bd4d | 2532 | symbolS * symbolP; |
c19d1205 ZW |
2533 | const char * symname; |
2534 | int type; | |
b99bd4ef | 2535 | |
c19d1205 | 2536 | switch (state) |
b99bd4ef | 2537 | { |
c19d1205 ZW |
2538 | case MAP_DATA: |
2539 | symname = "$d"; | |
2540 | type = BSF_NO_FLAGS; | |
2541 | break; | |
2542 | case MAP_ARM: | |
2543 | symname = "$a"; | |
2544 | type = BSF_NO_FLAGS; | |
2545 | break; | |
2546 | case MAP_THUMB: | |
2547 | symname = "$t"; | |
2548 | type = BSF_NO_FLAGS; | |
2549 | break; | |
c19d1205 ZW |
2550 | default: |
2551 | abort (); | |
2552 | } | |
2553 | ||
cd000bff | 2554 | symbolP = symbol_new (symname, now_seg, value, frag); |
c19d1205 ZW |
2555 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; |
2556 | ||
2557 | switch (state) | |
2558 | { | |
2559 | case MAP_ARM: | |
2560 | THUMB_SET_FUNC (symbolP, 0); | |
2561 | ARM_SET_THUMB (symbolP, 0); | |
2562 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2563 | break; | |
2564 | ||
2565 | case MAP_THUMB: | |
2566 | THUMB_SET_FUNC (symbolP, 1); | |
2567 | ARM_SET_THUMB (symbolP, 1); | |
2568 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2569 | break; | |
2570 | ||
2571 | case MAP_DATA: | |
2572 | default: | |
cd000bff DJ |
2573 | break; |
2574 | } | |
2575 | ||
2576 | /* Save the mapping symbols for future reference. Also check that | |
2577 | we do not place two mapping symbols at the same offset within a | |
2578 | frag. We'll handle overlap between frags in | |
2de7820f JZ |
2579 | check_mapping_symbols. |
2580 | ||
2581 | If .fill or other data filling directive generates zero sized data, | |
2582 | the mapping symbol for the following code will have the same value | |
2583 | as the one generated for the data filling directive. In this case, | |
2584 | we replace the old symbol with the new one at the same address. */ | |
cd000bff DJ |
2585 | if (value == 0) |
2586 | { | |
2de7820f JZ |
2587 | if (frag->tc_frag_data.first_map != NULL) |
2588 | { | |
2589 | know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0); | |
2590 | symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP); | |
2591 | } | |
cd000bff DJ |
2592 | frag->tc_frag_data.first_map = symbolP; |
2593 | } | |
2594 | if (frag->tc_frag_data.last_map != NULL) | |
0f020cef JZ |
2595 | { |
2596 | know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP)); | |
0f020cef JZ |
2597 | if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP)) |
2598 | symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP); | |
2599 | } | |
cd000bff DJ |
2600 | frag->tc_frag_data.last_map = symbolP; |
2601 | } | |
2602 | ||
2603 | /* We must sometimes convert a region marked as code to data during | |
2604 | code alignment, if an odd number of bytes have to be padded. The | |
2605 | code mapping symbol is pushed to an aligned address. */ | |
2606 | ||
2607 | static void | |
2608 | insert_data_mapping_symbol (enum mstate state, | |
2609 | valueT value, fragS *frag, offsetT bytes) | |
2610 | { | |
2611 | /* If there was already a mapping symbol, remove it. */ | |
2612 | if (frag->tc_frag_data.last_map != NULL | |
2613 | && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value) | |
2614 | { | |
2615 | symbolS *symp = frag->tc_frag_data.last_map; | |
2616 | ||
2617 | if (value == 0) | |
2618 | { | |
2619 | know (frag->tc_frag_data.first_map == symp); | |
2620 | frag->tc_frag_data.first_map = NULL; | |
2621 | } | |
2622 | frag->tc_frag_data.last_map = NULL; | |
2623 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
c19d1205 | 2624 | } |
cd000bff DJ |
2625 | |
2626 | make_mapping_symbol (MAP_DATA, value, frag); | |
2627 | make_mapping_symbol (state, value + bytes, frag); | |
2628 | } | |
2629 | ||
2630 | static void mapping_state_2 (enum mstate state, int max_chars); | |
2631 | ||
2632 | /* Set the mapping state to STATE. Only call this when about to | |
2633 | emit some STATE bytes to the file. */ | |
2634 | ||
2635 | void | |
2636 | mapping_state (enum mstate state) | |
2637 | { | |
940b5ce0 DJ |
2638 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2639 | ||
cd000bff DJ |
2640 | #define TRANSITION(from, to) (mapstate == (from) && state == (to)) |
2641 | ||
2642 | if (mapstate == state) | |
2643 | /* The mapping symbol has already been emitted. | |
2644 | There is nothing else to do. */ | |
2645 | return; | |
49c62a33 NC |
2646 | |
2647 | if (state == MAP_ARM || state == MAP_THUMB) | |
2648 | /* PR gas/12931 | |
2649 | All ARM instructions require 4-byte alignment. | |
2650 | (Almost) all Thumb instructions require 2-byte alignment. | |
2651 | ||
2652 | When emitting instructions into any section, mark the section | |
2653 | appropriately. | |
2654 | ||
2655 | Some Thumb instructions are alignment-sensitive modulo 4 bytes, | |
2656 | but themselves require 2-byte alignment; this applies to some | |
2657 | PC- relative forms. However, these cases will invovle implicit | |
2658 | literal pool generation or an explicit .align >=2, both of | |
2659 | which will cause the section to me marked with sufficient | |
2660 | alignment. Thus, we don't handle those cases here. */ | |
2661 | record_alignment (now_seg, state == MAP_ARM ? 2 : 1); | |
2662 | ||
2663 | if (TRANSITION (MAP_UNDEFINED, MAP_DATA)) | |
cd000bff DJ |
2664 | /* This case will be evaluated later in the next else. */ |
2665 | return; | |
2666 | else if (TRANSITION (MAP_UNDEFINED, MAP_ARM) | |
477330fc | 2667 | || TRANSITION (MAP_UNDEFINED, MAP_THUMB)) |
cd000bff DJ |
2668 | { |
2669 | /* Only add the symbol if the offset is > 0: | |
477330fc RM |
2670 | if we're at the first frag, check it's size > 0; |
2671 | if we're not at the first frag, then for sure | |
2672 | the offset is > 0. */ | |
cd000bff DJ |
2673 | struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root; |
2674 | const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0); | |
2675 | ||
2676 | if (add_symbol) | |
477330fc | 2677 | make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); |
cd000bff DJ |
2678 | } |
2679 | ||
2680 | mapping_state_2 (state, 0); | |
2681 | #undef TRANSITION | |
2682 | } | |
2683 | ||
2684 | /* Same as mapping_state, but MAX_CHARS bytes have already been | |
2685 | allocated. Put the mapping symbol that far back. */ | |
2686 | ||
2687 | static void | |
2688 | mapping_state_2 (enum mstate state, int max_chars) | |
2689 | { | |
940b5ce0 DJ |
2690 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2691 | ||
2692 | if (!SEG_NORMAL (now_seg)) | |
2693 | return; | |
2694 | ||
cd000bff DJ |
2695 | if (mapstate == state) |
2696 | /* The mapping symbol has already been emitted. | |
2697 | There is nothing else to do. */ | |
2698 | return; | |
2699 | ||
cd000bff DJ |
2700 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; |
2701 | make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); | |
c19d1205 ZW |
2702 | } |
2703 | #else | |
d3106081 NS |
2704 | #define mapping_state(x) ((void)0) |
2705 | #define mapping_state_2(x, y) ((void)0) | |
c19d1205 ZW |
2706 | #endif |
2707 | ||
2708 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
2709 | ||
4343666d | 2710 | #ifdef OBJ_COFF |
c19d1205 ZW |
2711 | static symbolS * |
2712 | find_real_start (symbolS * symbolP) | |
2713 | { | |
2714 | char * real_start; | |
2715 | const char * name = S_GET_NAME (symbolP); | |
2716 | symbolS * new_target; | |
2717 | ||
2718 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
2719 | #define STUB_NAME ".real_start_of" | |
2720 | ||
2721 | if (name == NULL) | |
2722 | abort (); | |
2723 | ||
37f6032b ZW |
2724 | /* The compiler may generate BL instructions to local labels because |
2725 | it needs to perform a branch to a far away location. These labels | |
2726 | do not have a corresponding ".real_start_of" label. We check | |
2727 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
2728 | the ".real_start_of" convention for nonlocal branches. */ | |
2729 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
2730 | return symbolP; |
2731 | ||
37f6032b | 2732 | real_start = ACONCAT ((STUB_NAME, name, NULL)); |
c19d1205 ZW |
2733 | new_target = symbol_find (real_start); |
2734 | ||
2735 | if (new_target == NULL) | |
2736 | { | |
bd3ba5d1 | 2737 | as_warn (_("Failed to find real start of function: %s\n"), name); |
c19d1205 ZW |
2738 | new_target = symbolP; |
2739 | } | |
2740 | ||
c19d1205 ZW |
2741 | return new_target; |
2742 | } | |
4343666d | 2743 | #endif |
c19d1205 ZW |
2744 | |
2745 | static void | |
2746 | opcode_select (int width) | |
2747 | { | |
2748 | switch (width) | |
2749 | { | |
2750 | case 16: | |
2751 | if (! thumb_mode) | |
2752 | { | |
e74cfd16 | 2753 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
c19d1205 ZW |
2754 | as_bad (_("selected processor does not support THUMB opcodes")); |
2755 | ||
2756 | thumb_mode = 1; | |
2757 | /* No need to force the alignment, since we will have been | |
2758 | coming from ARM mode, which is word-aligned. */ | |
2759 | record_alignment (now_seg, 1); | |
2760 | } | |
c19d1205 ZW |
2761 | break; |
2762 | ||
2763 | case 32: | |
2764 | if (thumb_mode) | |
2765 | { | |
e74cfd16 | 2766 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 ZW |
2767 | as_bad (_("selected processor does not support ARM opcodes")); |
2768 | ||
2769 | thumb_mode = 0; | |
2770 | ||
2771 | if (!need_pass_2) | |
2772 | frag_align (2, 0, 0); | |
2773 | ||
2774 | record_alignment (now_seg, 1); | |
2775 | } | |
c19d1205 ZW |
2776 | break; |
2777 | ||
2778 | default: | |
2779 | as_bad (_("invalid instruction size selected (%d)"), width); | |
2780 | } | |
2781 | } | |
2782 | ||
2783 | static void | |
2784 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
2785 | { | |
2786 | opcode_select (32); | |
2787 | demand_empty_rest_of_line (); | |
2788 | } | |
2789 | ||
2790 | static void | |
2791 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
2792 | { | |
2793 | opcode_select (16); | |
2794 | demand_empty_rest_of_line (); | |
2795 | } | |
2796 | ||
2797 | static void | |
2798 | s_code (int unused ATTRIBUTE_UNUSED) | |
2799 | { | |
2800 | int temp; | |
2801 | ||
2802 | temp = get_absolute_expression (); | |
2803 | switch (temp) | |
2804 | { | |
2805 | case 16: | |
2806 | case 32: | |
2807 | opcode_select (temp); | |
2808 | break; | |
2809 | ||
2810 | default: | |
2811 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
2812 | } | |
2813 | } | |
2814 | ||
2815 | static void | |
2816 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
2817 | { | |
2818 | /* If we are not already in thumb mode go into it, EVEN if | |
2819 | the target processor does not support thumb instructions. | |
2820 | This is used by gcc/config/arm/lib1funcs.asm for example | |
2821 | to compile interworking support functions even if the | |
2822 | target processor should not support interworking. */ | |
2823 | if (! thumb_mode) | |
2824 | { | |
2825 | thumb_mode = 2; | |
2826 | record_alignment (now_seg, 1); | |
2827 | } | |
2828 | ||
2829 | demand_empty_rest_of_line (); | |
2830 | } | |
2831 | ||
2832 | static void | |
2833 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
2834 | { | |
2835 | s_thumb (0); | |
2836 | ||
2837 | /* The following label is the name/address of the start of a Thumb function. | |
2838 | We need to know this for the interworking support. */ | |
2839 | label_is_thumb_function_name = TRUE; | |
2840 | } | |
2841 | ||
2842 | /* Perform a .set directive, but also mark the alias as | |
2843 | being a thumb function. */ | |
2844 | ||
2845 | static void | |
2846 | s_thumb_set (int equiv) | |
2847 | { | |
2848 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
2849 | We cannot just call that code as we need to get at the symbol that | |
2850 | is created. */ | |
2851 | char * name; | |
2852 | char delim; | |
2853 | char * end_name; | |
2854 | symbolS * symbolP; | |
2855 | ||
2856 | /* Especial apologies for the random logic: | |
2857 | This just grew, and could be parsed much more simply! | |
2858 | Dean - in haste. */ | |
2859 | name = input_line_pointer; | |
2860 | delim = get_symbol_end (); | |
2861 | end_name = input_line_pointer; | |
2862 | *end_name = delim; | |
2863 | ||
2864 | if (*input_line_pointer != ',') | |
2865 | { | |
2866 | *end_name = 0; | |
2867 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
2868 | *end_name = delim; |
2869 | ignore_rest_of_line (); | |
2870 | return; | |
2871 | } | |
2872 | ||
2873 | input_line_pointer++; | |
2874 | *end_name = 0; | |
2875 | ||
2876 | if (name[0] == '.' && name[1] == '\0') | |
2877 | { | |
2878 | /* XXX - this should not happen to .thumb_set. */ | |
2879 | abort (); | |
2880 | } | |
2881 | ||
2882 | if ((symbolP = symbol_find (name)) == NULL | |
2883 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
2884 | { | |
2885 | #ifndef NO_LISTING | |
2886 | /* When doing symbol listings, play games with dummy fragments living | |
2887 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 2888 | for this symbol. */ |
b99bd4ef NC |
2889 | if (listing & LISTING_SYMBOLS) |
2890 | { | |
2891 | extern struct list_info_struct * listing_tail; | |
21d799b5 | 2892 | fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS)); |
b99bd4ef NC |
2893 | |
2894 | memset (dummy_frag, 0, sizeof (fragS)); | |
2895 | dummy_frag->fr_type = rs_fill; | |
2896 | dummy_frag->line = listing_tail; | |
2897 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
2898 | dummy_frag->fr_symbol = symbolP; | |
2899 | } | |
2900 | else | |
2901 | #endif | |
2902 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
2903 | ||
2904 | #ifdef OBJ_COFF | |
2905 | /* "set" symbols are local unless otherwise specified. */ | |
2906 | SF_SET_LOCAL (symbolP); | |
2907 | #endif /* OBJ_COFF */ | |
2908 | } /* Make a new symbol. */ | |
2909 | ||
2910 | symbol_table_insert (symbolP); | |
2911 | ||
2912 | * end_name = delim; | |
2913 | ||
2914 | if (equiv | |
2915 | && S_IS_DEFINED (symbolP) | |
2916 | && S_GET_SEGMENT (symbolP) != reg_section) | |
2917 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
2918 | ||
2919 | pseudo_set (symbolP); | |
2920 | ||
2921 | demand_empty_rest_of_line (); | |
2922 | ||
c19d1205 | 2923 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
2924 | |
2925 | THUMB_SET_FUNC (symbolP, 1); | |
2926 | ARM_SET_THUMB (symbolP, 1); | |
2927 | #if defined OBJ_ELF || defined OBJ_COFF | |
2928 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2929 | #endif | |
2930 | } | |
2931 | ||
c19d1205 | 2932 | /* Directives: Mode selection. */ |
b99bd4ef | 2933 | |
c19d1205 ZW |
2934 | /* .syntax [unified|divided] - choose the new unified syntax |
2935 | (same for Arm and Thumb encoding, modulo slight differences in what | |
2936 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 2937 | static void |
c19d1205 | 2938 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2939 | { |
c19d1205 ZW |
2940 | char *name, delim; |
2941 | ||
2942 | name = input_line_pointer; | |
2943 | delim = get_symbol_end (); | |
2944 | ||
2945 | if (!strcasecmp (name, "unified")) | |
2946 | unified_syntax = TRUE; | |
2947 | else if (!strcasecmp (name, "divided")) | |
2948 | unified_syntax = FALSE; | |
2949 | else | |
2950 | { | |
2951 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
2952 | return; | |
2953 | } | |
2954 | *input_line_pointer = delim; | |
b99bd4ef NC |
2955 | demand_empty_rest_of_line (); |
2956 | } | |
2957 | ||
c19d1205 ZW |
2958 | /* Directives: sectioning and alignment. */ |
2959 | ||
2960 | /* Same as s_align_ptwo but align 0 => align 2. */ | |
2961 | ||
b99bd4ef | 2962 | static void |
c19d1205 | 2963 | s_align (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2964 | { |
a737bd4d | 2965 | int temp; |
dce323d1 | 2966 | bfd_boolean fill_p; |
c19d1205 ZW |
2967 | long temp_fill; |
2968 | long max_alignment = 15; | |
b99bd4ef NC |
2969 | |
2970 | temp = get_absolute_expression (); | |
c19d1205 ZW |
2971 | if (temp > max_alignment) |
2972 | as_bad (_("alignment too large: %d assumed"), temp = max_alignment); | |
2973 | else if (temp < 0) | |
b99bd4ef | 2974 | { |
c19d1205 ZW |
2975 | as_bad (_("alignment negative. 0 assumed.")); |
2976 | temp = 0; | |
2977 | } | |
b99bd4ef | 2978 | |
c19d1205 ZW |
2979 | if (*input_line_pointer == ',') |
2980 | { | |
2981 | input_line_pointer++; | |
2982 | temp_fill = get_absolute_expression (); | |
dce323d1 | 2983 | fill_p = TRUE; |
b99bd4ef | 2984 | } |
c19d1205 | 2985 | else |
dce323d1 PB |
2986 | { |
2987 | fill_p = FALSE; | |
2988 | temp_fill = 0; | |
2989 | } | |
b99bd4ef | 2990 | |
c19d1205 ZW |
2991 | if (!temp) |
2992 | temp = 2; | |
b99bd4ef | 2993 | |
c19d1205 ZW |
2994 | /* Only make a frag if we HAVE to. */ |
2995 | if (temp && !need_pass_2) | |
dce323d1 PB |
2996 | { |
2997 | if (!fill_p && subseg_text_p (now_seg)) | |
2998 | frag_align_code (temp, 0); | |
2999 | else | |
3000 | frag_align (temp, (int) temp_fill, 0); | |
3001 | } | |
c19d1205 ZW |
3002 | demand_empty_rest_of_line (); |
3003 | ||
3004 | record_alignment (now_seg, temp); | |
b99bd4ef NC |
3005 | } |
3006 | ||
c19d1205 ZW |
3007 | static void |
3008 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 3009 | { |
c19d1205 ZW |
3010 | /* We don't support putting frags in the BSS segment, we fake it by |
3011 | marking in_bss, then looking at s_skip for clues. */ | |
3012 | subseg_set (bss_section, 0); | |
3013 | demand_empty_rest_of_line (); | |
cd000bff DJ |
3014 | |
3015 | #ifdef md_elf_section_change_hook | |
3016 | md_elf_section_change_hook (); | |
3017 | #endif | |
c19d1205 | 3018 | } |
b99bd4ef | 3019 | |
c19d1205 ZW |
3020 | static void |
3021 | s_even (int ignore ATTRIBUTE_UNUSED) | |
3022 | { | |
3023 | /* Never make frag if expect extra pass. */ | |
3024 | if (!need_pass_2) | |
3025 | frag_align (1, 0, 0); | |
b99bd4ef | 3026 | |
c19d1205 | 3027 | record_alignment (now_seg, 1); |
b99bd4ef | 3028 | |
c19d1205 | 3029 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3030 | } |
3031 | ||
2e6976a8 DG |
3032 | /* Directives: CodeComposer Studio. */ |
3033 | ||
3034 | /* .ref (for CodeComposer Studio syntax only). */ | |
3035 | static void | |
3036 | s_ccs_ref (int unused ATTRIBUTE_UNUSED) | |
3037 | { | |
3038 | if (codecomposer_syntax) | |
3039 | ignore_rest_of_line (); | |
3040 | else | |
3041 | as_bad (_(".ref pseudo-op only available with -mccs flag.")); | |
3042 | } | |
3043 | ||
3044 | /* If name is not NULL, then it is used for marking the beginning of a | |
3045 | function, wherease if it is NULL then it means the function end. */ | |
3046 | static void | |
3047 | asmfunc_debug (const char * name) | |
3048 | { | |
3049 | static const char * last_name = NULL; | |
3050 | ||
3051 | if (name != NULL) | |
3052 | { | |
3053 | gas_assert (last_name == NULL); | |
3054 | last_name = name; | |
3055 | ||
3056 | if (debug_type == DEBUG_STABS) | |
3057 | stabs_generate_asm_func (name, name); | |
3058 | } | |
3059 | else | |
3060 | { | |
3061 | gas_assert (last_name != NULL); | |
3062 | ||
3063 | if (debug_type == DEBUG_STABS) | |
3064 | stabs_generate_asm_endfunc (last_name, last_name); | |
3065 | ||
3066 | last_name = NULL; | |
3067 | } | |
3068 | } | |
3069 | ||
3070 | static void | |
3071 | s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED) | |
3072 | { | |
3073 | if (codecomposer_syntax) | |
3074 | { | |
3075 | switch (asmfunc_state) | |
3076 | { | |
3077 | case OUTSIDE_ASMFUNC: | |
3078 | asmfunc_state = WAITING_ASMFUNC_NAME; | |
3079 | break; | |
3080 | ||
3081 | case WAITING_ASMFUNC_NAME: | |
3082 | as_bad (_(".asmfunc repeated.")); | |
3083 | break; | |
3084 | ||
3085 | case WAITING_ENDASMFUNC: | |
3086 | as_bad (_(".asmfunc without function.")); | |
3087 | break; | |
3088 | } | |
3089 | demand_empty_rest_of_line (); | |
3090 | } | |
3091 | else | |
3092 | as_bad (_(".asmfunc pseudo-op only available with -mccs flag.")); | |
3093 | } | |
3094 | ||
3095 | static void | |
3096 | s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED) | |
3097 | { | |
3098 | if (codecomposer_syntax) | |
3099 | { | |
3100 | switch (asmfunc_state) | |
3101 | { | |
3102 | case OUTSIDE_ASMFUNC: | |
3103 | as_bad (_(".endasmfunc without a .asmfunc.")); | |
3104 | break; | |
3105 | ||
3106 | case WAITING_ASMFUNC_NAME: | |
3107 | as_bad (_(".endasmfunc without function.")); | |
3108 | break; | |
3109 | ||
3110 | case WAITING_ENDASMFUNC: | |
3111 | asmfunc_state = OUTSIDE_ASMFUNC; | |
3112 | asmfunc_debug (NULL); | |
3113 | break; | |
3114 | } | |
3115 | demand_empty_rest_of_line (); | |
3116 | } | |
3117 | else | |
3118 | as_bad (_(".endasmfunc pseudo-op only available with -mccs flag.")); | |
3119 | } | |
3120 | ||
3121 | static void | |
3122 | s_ccs_def (int name) | |
3123 | { | |
3124 | if (codecomposer_syntax) | |
3125 | s_globl (name); | |
3126 | else | |
3127 | as_bad (_(".def pseudo-op only available with -mccs flag.")); | |
3128 | } | |
3129 | ||
c19d1205 | 3130 | /* Directives: Literal pools. */ |
a737bd4d | 3131 | |
c19d1205 ZW |
3132 | static literal_pool * |
3133 | find_literal_pool (void) | |
a737bd4d | 3134 | { |
c19d1205 | 3135 | literal_pool * pool; |
a737bd4d | 3136 | |
c19d1205 | 3137 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 3138 | { |
c19d1205 ZW |
3139 | if (pool->section == now_seg |
3140 | && pool->sub_section == now_subseg) | |
3141 | break; | |
a737bd4d NC |
3142 | } |
3143 | ||
c19d1205 | 3144 | return pool; |
a737bd4d NC |
3145 | } |
3146 | ||
c19d1205 ZW |
3147 | static literal_pool * |
3148 | find_or_make_literal_pool (void) | |
a737bd4d | 3149 | { |
c19d1205 ZW |
3150 | /* Next literal pool ID number. */ |
3151 | static unsigned int latest_pool_num = 1; | |
3152 | literal_pool * pool; | |
a737bd4d | 3153 | |
c19d1205 | 3154 | pool = find_literal_pool (); |
a737bd4d | 3155 | |
c19d1205 | 3156 | if (pool == NULL) |
a737bd4d | 3157 | { |
c19d1205 | 3158 | /* Create a new pool. */ |
21d799b5 | 3159 | pool = (literal_pool *) xmalloc (sizeof (* pool)); |
c19d1205 ZW |
3160 | if (! pool) |
3161 | return NULL; | |
a737bd4d | 3162 | |
c19d1205 ZW |
3163 | pool->next_free_entry = 0; |
3164 | pool->section = now_seg; | |
3165 | pool->sub_section = now_subseg; | |
3166 | pool->next = list_of_pools; | |
3167 | pool->symbol = NULL; | |
8335d6aa | 3168 | pool->alignment = 2; |
c19d1205 ZW |
3169 | |
3170 | /* Add it to the list. */ | |
3171 | list_of_pools = pool; | |
a737bd4d | 3172 | } |
a737bd4d | 3173 | |
c19d1205 ZW |
3174 | /* New pools, and emptied pools, will have a NULL symbol. */ |
3175 | if (pool->symbol == NULL) | |
a737bd4d | 3176 | { |
c19d1205 ZW |
3177 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
3178 | (valueT) 0, &zero_address_frag); | |
3179 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
3180 | } |
3181 | ||
c19d1205 ZW |
3182 | /* Done. */ |
3183 | return pool; | |
a737bd4d NC |
3184 | } |
3185 | ||
c19d1205 | 3186 | /* Add the literal in the global 'inst' |
5f4273c7 | 3187 | structure to the relevant literal pool. */ |
b99bd4ef NC |
3188 | |
3189 | static int | |
8335d6aa | 3190 | add_to_lit_pool (unsigned int nbytes) |
b99bd4ef | 3191 | { |
8335d6aa JW |
3192 | #define PADDING_SLOT 0x1 |
3193 | #define LIT_ENTRY_SIZE_MASK 0xFF | |
c19d1205 | 3194 | literal_pool * pool; |
8335d6aa JW |
3195 | unsigned int entry, pool_size = 0; |
3196 | bfd_boolean padding_slot_p = FALSE; | |
e56c722b | 3197 | unsigned imm1 = 0; |
8335d6aa JW |
3198 | unsigned imm2 = 0; |
3199 | ||
3200 | if (nbytes == 8) | |
3201 | { | |
3202 | imm1 = inst.operands[1].imm; | |
3203 | imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg | |
3204 | : inst.reloc.exp.X_unsigned ? 0 | |
2569ceb0 | 3205 | : ((bfd_int64_t) inst.operands[1].imm) >> 32); |
8335d6aa JW |
3206 | if (target_big_endian) |
3207 | { | |
3208 | imm1 = imm2; | |
3209 | imm2 = inst.operands[1].imm; | |
3210 | } | |
3211 | } | |
b99bd4ef | 3212 | |
c19d1205 ZW |
3213 | pool = find_or_make_literal_pool (); |
3214 | ||
3215 | /* Check if this literal value is already in the pool. */ | |
3216 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 3217 | { |
8335d6aa JW |
3218 | if (nbytes == 4) |
3219 | { | |
3220 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
3221 | && (inst.reloc.exp.X_op == O_constant) | |
3222 | && (pool->literals[entry].X_add_number | |
3223 | == inst.reloc.exp.X_add_number) | |
3224 | && (pool->literals[entry].X_md == nbytes) | |
3225 | && (pool->literals[entry].X_unsigned | |
3226 | == inst.reloc.exp.X_unsigned)) | |
3227 | break; | |
3228 | ||
3229 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
3230 | && (inst.reloc.exp.X_op == O_symbol) | |
3231 | && (pool->literals[entry].X_add_number | |
3232 | == inst.reloc.exp.X_add_number) | |
3233 | && (pool->literals[entry].X_add_symbol | |
3234 | == inst.reloc.exp.X_add_symbol) | |
3235 | && (pool->literals[entry].X_op_symbol | |
3236 | == inst.reloc.exp.X_op_symbol) | |
3237 | && (pool->literals[entry].X_md == nbytes)) | |
3238 | break; | |
3239 | } | |
3240 | else if ((nbytes == 8) | |
3241 | && !(pool_size & 0x7) | |
3242 | && ((entry + 1) != pool->next_free_entry) | |
3243 | && (pool->literals[entry].X_op == O_constant) | |
19f2f6a9 | 3244 | && (pool->literals[entry].X_add_number == (offsetT) imm1) |
8335d6aa JW |
3245 | && (pool->literals[entry].X_unsigned |
3246 | == inst.reloc.exp.X_unsigned) | |
3247 | && (pool->literals[entry + 1].X_op == O_constant) | |
19f2f6a9 | 3248 | && (pool->literals[entry + 1].X_add_number == (offsetT) imm2) |
8335d6aa JW |
3249 | && (pool->literals[entry + 1].X_unsigned |
3250 | == inst.reloc.exp.X_unsigned)) | |
c19d1205 ZW |
3251 | break; |
3252 | ||
8335d6aa JW |
3253 | padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT); |
3254 | if (padding_slot_p && (nbytes == 4)) | |
c19d1205 | 3255 | break; |
8335d6aa JW |
3256 | |
3257 | pool_size += 4; | |
b99bd4ef NC |
3258 | } |
3259 | ||
c19d1205 ZW |
3260 | /* Do we need to create a new entry? */ |
3261 | if (entry == pool->next_free_entry) | |
3262 | { | |
3263 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
3264 | { | |
3265 | inst.error = _("literal pool overflow"); | |
3266 | return FAIL; | |
3267 | } | |
3268 | ||
8335d6aa JW |
3269 | if (nbytes == 8) |
3270 | { | |
3271 | /* For 8-byte entries, we align to an 8-byte boundary, | |
3272 | and split it into two 4-byte entries, because on 32-bit | |
3273 | host, 8-byte constants are treated as big num, thus | |
3274 | saved in "generic_bignum" which will be overwritten | |
3275 | by later assignments. | |
3276 | ||
3277 | We also need to make sure there is enough space for | |
3278 | the split. | |
3279 | ||
3280 | We also check to make sure the literal operand is a | |
3281 | constant number. */ | |
19f2f6a9 JW |
3282 | if (!(inst.reloc.exp.X_op == O_constant |
3283 | || inst.reloc.exp.X_op == O_big)) | |
8335d6aa JW |
3284 | { |
3285 | inst.error = _("invalid type for literal pool"); | |
3286 | return FAIL; | |
3287 | } | |
3288 | else if (pool_size & 0x7) | |
3289 | { | |
3290 | if ((entry + 2) >= MAX_LITERAL_POOL_SIZE) | |
3291 | { | |
3292 | inst.error = _("literal pool overflow"); | |
3293 | return FAIL; | |
3294 | } | |
3295 | ||
3296 | pool->literals[entry] = inst.reloc.exp; | |
3297 | pool->literals[entry].X_add_number = 0; | |
3298 | pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4; | |
3299 | pool->next_free_entry += 1; | |
3300 | pool_size += 4; | |
3301 | } | |
3302 | else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE) | |
3303 | { | |
3304 | inst.error = _("literal pool overflow"); | |
3305 | return FAIL; | |
3306 | } | |
3307 | ||
3308 | pool->literals[entry] = inst.reloc.exp; | |
3309 | pool->literals[entry].X_op = O_constant; | |
3310 | pool->literals[entry].X_add_number = imm1; | |
3311 | pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned; | |
3312 | pool->literals[entry++].X_md = 4; | |
3313 | pool->literals[entry] = inst.reloc.exp; | |
3314 | pool->literals[entry].X_op = O_constant; | |
3315 | pool->literals[entry].X_add_number = imm2; | |
3316 | pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned; | |
3317 | pool->literals[entry].X_md = 4; | |
3318 | pool->alignment = 3; | |
3319 | pool->next_free_entry += 1; | |
3320 | } | |
3321 | else | |
3322 | { | |
3323 | pool->literals[entry] = inst.reloc.exp; | |
3324 | pool->literals[entry].X_md = 4; | |
3325 | } | |
3326 | ||
a8040cf2 NC |
3327 | #ifdef OBJ_ELF |
3328 | /* PR ld/12974: Record the location of the first source line to reference | |
3329 | this entry in the literal pool. If it turns out during linking that the | |
3330 | symbol does not exist we will be able to give an accurate line number for | |
3331 | the (first use of the) missing reference. */ | |
3332 | if (debug_type == DEBUG_DWARF2) | |
3333 | dwarf2_where (pool->locs + entry); | |
3334 | #endif | |
c19d1205 ZW |
3335 | pool->next_free_entry += 1; |
3336 | } | |
8335d6aa JW |
3337 | else if (padding_slot_p) |
3338 | { | |
3339 | pool->literals[entry] = inst.reloc.exp; | |
3340 | pool->literals[entry].X_md = nbytes; | |
3341 | } | |
b99bd4ef | 3342 | |
c19d1205 | 3343 | inst.reloc.exp.X_op = O_symbol; |
8335d6aa | 3344 | inst.reloc.exp.X_add_number = pool_size; |
c19d1205 | 3345 | inst.reloc.exp.X_add_symbol = pool->symbol; |
b99bd4ef | 3346 | |
c19d1205 | 3347 | return SUCCESS; |
b99bd4ef NC |
3348 | } |
3349 | ||
2e6976a8 DG |
3350 | bfd_boolean |
3351 | tc_start_label_without_colon (char unused1 ATTRIBUTE_UNUSED, const char * rest) | |
3352 | { | |
3353 | bfd_boolean ret = TRUE; | |
3354 | ||
3355 | if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME) | |
3356 | { | |
3357 | const char *label = rest; | |
3358 | ||
3359 | while (!is_end_of_line[(int) label[-1]]) | |
3360 | --label; | |
3361 | ||
3362 | if (*label == '.') | |
3363 | { | |
3364 | as_bad (_("Invalid label '%s'"), label); | |
3365 | ret = FALSE; | |
3366 | } | |
3367 | ||
3368 | asmfunc_debug (label); | |
3369 | ||
3370 | asmfunc_state = WAITING_ENDASMFUNC; | |
3371 | } | |
3372 | ||
3373 | return ret; | |
3374 | } | |
3375 | ||
c19d1205 ZW |
3376 | /* Can't use symbol_new here, so have to create a symbol and then at |
3377 | a later date assign it a value. Thats what these functions do. */ | |
e16bb312 | 3378 | |
c19d1205 ZW |
3379 | static void |
3380 | symbol_locate (symbolS * symbolP, | |
3381 | const char * name, /* It is copied, the caller can modify. */ | |
3382 | segT segment, /* Segment identifier (SEG_<something>). */ | |
3383 | valueT valu, /* Symbol value. */ | |
3384 | fragS * frag) /* Associated fragment. */ | |
3385 | { | |
e57e6ddc | 3386 | size_t name_length; |
c19d1205 | 3387 | char * preserved_copy_of_name; |
e16bb312 | 3388 | |
c19d1205 ZW |
3389 | name_length = strlen (name) + 1; /* +1 for \0. */ |
3390 | obstack_grow (¬es, name, name_length); | |
21d799b5 | 3391 | preserved_copy_of_name = (char *) obstack_finish (¬es); |
e16bb312 | 3392 | |
c19d1205 ZW |
3393 | #ifdef tc_canonicalize_symbol_name |
3394 | preserved_copy_of_name = | |
3395 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
3396 | #endif | |
b99bd4ef | 3397 | |
c19d1205 | 3398 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 3399 | |
c19d1205 ZW |
3400 | S_SET_SEGMENT (symbolP, segment); |
3401 | S_SET_VALUE (symbolP, valu); | |
3402 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 3403 | |
c19d1205 | 3404 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 3405 | |
c19d1205 ZW |
3406 | /* Link to end of symbol chain. */ |
3407 | { | |
3408 | extern int symbol_table_frozen; | |
b99bd4ef | 3409 | |
c19d1205 ZW |
3410 | if (symbol_table_frozen) |
3411 | abort (); | |
3412 | } | |
b99bd4ef | 3413 | |
c19d1205 | 3414 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 3415 | |
c19d1205 | 3416 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 3417 | |
c19d1205 ZW |
3418 | #ifdef tc_symbol_new_hook |
3419 | tc_symbol_new_hook (symbolP); | |
3420 | #endif | |
3421 | ||
3422 | #ifdef DEBUG_SYMS | |
3423 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
3424 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
3425 | } |
3426 | ||
c19d1205 ZW |
3427 | static void |
3428 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 3429 | { |
c19d1205 ZW |
3430 | unsigned int entry; |
3431 | literal_pool * pool; | |
3432 | char sym_name[20]; | |
b99bd4ef | 3433 | |
c19d1205 ZW |
3434 | pool = find_literal_pool (); |
3435 | if (pool == NULL | |
3436 | || pool->symbol == NULL | |
3437 | || pool->next_free_entry == 0) | |
3438 | return; | |
b99bd4ef | 3439 | |
c19d1205 ZW |
3440 | /* Align pool as you have word accesses. |
3441 | Only make a frag if we have to. */ | |
3442 | if (!need_pass_2) | |
8335d6aa | 3443 | frag_align (pool->alignment, 0, 0); |
b99bd4ef | 3444 | |
c19d1205 | 3445 | record_alignment (now_seg, 2); |
b99bd4ef | 3446 | |
aaca88ef | 3447 | #ifdef OBJ_ELF |
47fc6e36 WN |
3448 | seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA; |
3449 | make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now); | |
aaca88ef | 3450 | #endif |
c19d1205 | 3451 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 3452 | |
c19d1205 ZW |
3453 | symbol_locate (pool->symbol, sym_name, now_seg, |
3454 | (valueT) frag_now_fix (), frag_now); | |
3455 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 3456 | |
c19d1205 | 3457 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 3458 | |
c19d1205 ZW |
3459 | #if defined OBJ_COFF || defined OBJ_ELF |
3460 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
3461 | #endif | |
6c43fab6 | 3462 | |
c19d1205 | 3463 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
a8040cf2 NC |
3464 | { |
3465 | #ifdef OBJ_ELF | |
3466 | if (debug_type == DEBUG_DWARF2) | |
3467 | dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry); | |
3468 | #endif | |
3469 | /* First output the expression in the instruction to the pool. */ | |
8335d6aa JW |
3470 | emit_expr (&(pool->literals[entry]), |
3471 | pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK); | |
a8040cf2 | 3472 | } |
b99bd4ef | 3473 | |
c19d1205 ZW |
3474 | /* Mark the pool as empty. */ |
3475 | pool->next_free_entry = 0; | |
3476 | pool->symbol = NULL; | |
b99bd4ef NC |
3477 | } |
3478 | ||
c19d1205 ZW |
3479 | #ifdef OBJ_ELF |
3480 | /* Forward declarations for functions below, in the MD interface | |
3481 | section. */ | |
3482 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
3483 | static valueT create_unwind_entry (int); | |
3484 | static void start_unwind_section (const segT, int); | |
3485 | static void add_unwind_opcode (valueT, int); | |
3486 | static void flush_pending_unwind (void); | |
b99bd4ef | 3487 | |
c19d1205 | 3488 | /* Directives: Data. */ |
b99bd4ef | 3489 | |
c19d1205 ZW |
3490 | static void |
3491 | s_arm_elf_cons (int nbytes) | |
3492 | { | |
3493 | expressionS exp; | |
b99bd4ef | 3494 | |
c19d1205 ZW |
3495 | #ifdef md_flush_pending_output |
3496 | md_flush_pending_output (); | |
3497 | #endif | |
b99bd4ef | 3498 | |
c19d1205 | 3499 | if (is_it_end_of_statement ()) |
b99bd4ef | 3500 | { |
c19d1205 ZW |
3501 | demand_empty_rest_of_line (); |
3502 | return; | |
b99bd4ef NC |
3503 | } |
3504 | ||
c19d1205 ZW |
3505 | #ifdef md_cons_align |
3506 | md_cons_align (nbytes); | |
3507 | #endif | |
b99bd4ef | 3508 | |
c19d1205 ZW |
3509 | mapping_state (MAP_DATA); |
3510 | do | |
b99bd4ef | 3511 | { |
c19d1205 ZW |
3512 | int reloc; |
3513 | char *base = input_line_pointer; | |
b99bd4ef | 3514 | |
c19d1205 | 3515 | expression (& exp); |
b99bd4ef | 3516 | |
c19d1205 ZW |
3517 | if (exp.X_op != O_symbol) |
3518 | emit_expr (&exp, (unsigned int) nbytes); | |
3519 | else | |
3520 | { | |
3521 | char *before_reloc = input_line_pointer; | |
3522 | reloc = parse_reloc (&input_line_pointer); | |
3523 | if (reloc == -1) | |
3524 | { | |
3525 | as_bad (_("unrecognized relocation suffix")); | |
3526 | ignore_rest_of_line (); | |
3527 | return; | |
3528 | } | |
3529 | else if (reloc == BFD_RELOC_UNUSED) | |
3530 | emit_expr (&exp, (unsigned int) nbytes); | |
3531 | else | |
3532 | { | |
21d799b5 | 3533 | reloc_howto_type *howto = (reloc_howto_type *) |
477330fc RM |
3534 | bfd_reloc_type_lookup (stdoutput, |
3535 | (bfd_reloc_code_real_type) reloc); | |
c19d1205 | 3536 | int size = bfd_get_reloc_size (howto); |
b99bd4ef | 3537 | |
2fc8bdac ZW |
3538 | if (reloc == BFD_RELOC_ARM_PLT32) |
3539 | { | |
3540 | as_bad (_("(plt) is only valid on branch targets")); | |
3541 | reloc = BFD_RELOC_UNUSED; | |
3542 | size = 0; | |
3543 | } | |
3544 | ||
c19d1205 | 3545 | if (size > nbytes) |
2fc8bdac | 3546 | as_bad (_("%s relocations do not fit in %d bytes"), |
c19d1205 ZW |
3547 | howto->name, nbytes); |
3548 | else | |
3549 | { | |
3550 | /* We've parsed an expression stopping at O_symbol. | |
3551 | But there may be more expression left now that we | |
3552 | have parsed the relocation marker. Parse it again. | |
3553 | XXX Surely there is a cleaner way to do this. */ | |
3554 | char *p = input_line_pointer; | |
3555 | int offset; | |
21d799b5 | 3556 | char *save_buf = (char *) alloca (input_line_pointer - base); |
c19d1205 ZW |
3557 | memcpy (save_buf, base, input_line_pointer - base); |
3558 | memmove (base + (input_line_pointer - before_reloc), | |
3559 | base, before_reloc - base); | |
3560 | ||
3561 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
3562 | expression (&exp); | |
3563 | memcpy (base, save_buf, p - base); | |
3564 | ||
3565 | offset = nbytes - size; | |
4b1a927e AM |
3566 | p = frag_more (nbytes); |
3567 | memset (p, 0, nbytes); | |
c19d1205 | 3568 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, |
21d799b5 | 3569 | size, &exp, 0, (enum bfd_reloc_code_real) reloc); |
c19d1205 ZW |
3570 | } |
3571 | } | |
3572 | } | |
b99bd4ef | 3573 | } |
c19d1205 | 3574 | while (*input_line_pointer++ == ','); |
b99bd4ef | 3575 | |
c19d1205 ZW |
3576 | /* Put terminator back into stream. */ |
3577 | input_line_pointer --; | |
3578 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
3579 | } |
3580 | ||
c921be7d NC |
3581 | /* Emit an expression containing a 32-bit thumb instruction. |
3582 | Implementation based on put_thumb32_insn. */ | |
3583 | ||
3584 | static void | |
3585 | emit_thumb32_expr (expressionS * exp) | |
3586 | { | |
3587 | expressionS exp_high = *exp; | |
3588 | ||
3589 | exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16; | |
3590 | emit_expr (& exp_high, (unsigned int) THUMB_SIZE); | |
3591 | exp->X_add_number &= 0xffff; | |
3592 | emit_expr (exp, (unsigned int) THUMB_SIZE); | |
3593 | } | |
3594 | ||
3595 | /* Guess the instruction size based on the opcode. */ | |
3596 | ||
3597 | static int | |
3598 | thumb_insn_size (int opcode) | |
3599 | { | |
3600 | if ((unsigned int) opcode < 0xe800u) | |
3601 | return 2; | |
3602 | else if ((unsigned int) opcode >= 0xe8000000u) | |
3603 | return 4; | |
3604 | else | |
3605 | return 0; | |
3606 | } | |
3607 | ||
3608 | static bfd_boolean | |
3609 | emit_insn (expressionS *exp, int nbytes) | |
3610 | { | |
3611 | int size = 0; | |
3612 | ||
3613 | if (exp->X_op == O_constant) | |
3614 | { | |
3615 | size = nbytes; | |
3616 | ||
3617 | if (size == 0) | |
3618 | size = thumb_insn_size (exp->X_add_number); | |
3619 | ||
3620 | if (size != 0) | |
3621 | { | |
3622 | if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu) | |
3623 | { | |
3624 | as_bad (_(".inst.n operand too big. "\ | |
3625 | "Use .inst.w instead")); | |
3626 | size = 0; | |
3627 | } | |
3628 | else | |
3629 | { | |
3630 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
3631 | set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0); | |
3632 | else | |
3633 | set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0); | |
3634 | ||
3635 | if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian) | |
3636 | emit_thumb32_expr (exp); | |
3637 | else | |
3638 | emit_expr (exp, (unsigned int) size); | |
3639 | ||
3640 | it_fsm_post_encode (); | |
3641 | } | |
3642 | } | |
3643 | else | |
3644 | as_bad (_("cannot determine Thumb instruction size. " \ | |
3645 | "Use .inst.n/.inst.w instead")); | |
3646 | } | |
3647 | else | |
3648 | as_bad (_("constant expression required")); | |
3649 | ||
3650 | return (size != 0); | |
3651 | } | |
3652 | ||
3653 | /* Like s_arm_elf_cons but do not use md_cons_align and | |
3654 | set the mapping state to MAP_ARM/MAP_THUMB. */ | |
3655 | ||
3656 | static void | |
3657 | s_arm_elf_inst (int nbytes) | |
3658 | { | |
3659 | if (is_it_end_of_statement ()) | |
3660 | { | |
3661 | demand_empty_rest_of_line (); | |
3662 | return; | |
3663 | } | |
3664 | ||
3665 | /* Calling mapping_state () here will not change ARM/THUMB, | |
3666 | but will ensure not to be in DATA state. */ | |
3667 | ||
3668 | if (thumb_mode) | |
3669 | mapping_state (MAP_THUMB); | |
3670 | else | |
3671 | { | |
3672 | if (nbytes != 0) | |
3673 | { | |
3674 | as_bad (_("width suffixes are invalid in ARM mode")); | |
3675 | ignore_rest_of_line (); | |
3676 | return; | |
3677 | } | |
3678 | ||
3679 | nbytes = 4; | |
3680 | ||
3681 | mapping_state (MAP_ARM); | |
3682 | } | |
3683 | ||
3684 | do | |
3685 | { | |
3686 | expressionS exp; | |
3687 | ||
3688 | expression (& exp); | |
3689 | ||
3690 | if (! emit_insn (& exp, nbytes)) | |
3691 | { | |
3692 | ignore_rest_of_line (); | |
3693 | return; | |
3694 | } | |
3695 | } | |
3696 | while (*input_line_pointer++ == ','); | |
3697 | ||
3698 | /* Put terminator back into stream. */ | |
3699 | input_line_pointer --; | |
3700 | demand_empty_rest_of_line (); | |
3701 | } | |
b99bd4ef | 3702 | |
c19d1205 | 3703 | /* Parse a .rel31 directive. */ |
b99bd4ef | 3704 | |
c19d1205 ZW |
3705 | static void |
3706 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
3707 | { | |
3708 | expressionS exp; | |
3709 | char *p; | |
3710 | valueT highbit; | |
b99bd4ef | 3711 | |
c19d1205 ZW |
3712 | highbit = 0; |
3713 | if (*input_line_pointer == '1') | |
3714 | highbit = 0x80000000; | |
3715 | else if (*input_line_pointer != '0') | |
3716 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 3717 | |
c19d1205 ZW |
3718 | input_line_pointer++; |
3719 | if (*input_line_pointer != ',') | |
3720 | as_bad (_("missing comma")); | |
3721 | input_line_pointer++; | |
b99bd4ef | 3722 | |
c19d1205 ZW |
3723 | #ifdef md_flush_pending_output |
3724 | md_flush_pending_output (); | |
3725 | #endif | |
b99bd4ef | 3726 | |
c19d1205 ZW |
3727 | #ifdef md_cons_align |
3728 | md_cons_align (4); | |
3729 | #endif | |
b99bd4ef | 3730 | |
c19d1205 | 3731 | mapping_state (MAP_DATA); |
b99bd4ef | 3732 | |
c19d1205 | 3733 | expression (&exp); |
b99bd4ef | 3734 | |
c19d1205 ZW |
3735 | p = frag_more (4); |
3736 | md_number_to_chars (p, highbit, 4); | |
3737 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
3738 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 3739 | |
c19d1205 | 3740 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3741 | } |
3742 | ||
c19d1205 | 3743 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 3744 | |
c19d1205 | 3745 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 3746 | |
c19d1205 ZW |
3747 | static void |
3748 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
3749 | { | |
3750 | demand_empty_rest_of_line (); | |
921e5f0a PB |
3751 | if (unwind.proc_start) |
3752 | { | |
c921be7d | 3753 | as_bad (_("duplicate .fnstart directive")); |
921e5f0a PB |
3754 | return; |
3755 | } | |
3756 | ||
c19d1205 ZW |
3757 | /* Mark the start of the function. */ |
3758 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 3759 | |
c19d1205 ZW |
3760 | /* Reset the rest of the unwind info. */ |
3761 | unwind.opcode_count = 0; | |
3762 | unwind.table_entry = NULL; | |
3763 | unwind.personality_routine = NULL; | |
3764 | unwind.personality_index = -1; | |
3765 | unwind.frame_size = 0; | |
3766 | unwind.fp_offset = 0; | |
fdfde340 | 3767 | unwind.fp_reg = REG_SP; |
c19d1205 ZW |
3768 | unwind.fp_used = 0; |
3769 | unwind.sp_restored = 0; | |
3770 | } | |
b99bd4ef | 3771 | |
b99bd4ef | 3772 | |
c19d1205 ZW |
3773 | /* Parse a handlerdata directive. Creates the exception handling table entry |
3774 | for the function. */ | |
b99bd4ef | 3775 | |
c19d1205 ZW |
3776 | static void |
3777 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
3778 | { | |
3779 | demand_empty_rest_of_line (); | |
921e5f0a | 3780 | if (!unwind.proc_start) |
c921be7d | 3781 | as_bad (MISSING_FNSTART); |
921e5f0a | 3782 | |
c19d1205 | 3783 | if (unwind.table_entry) |
6decc662 | 3784 | as_bad (_("duplicate .handlerdata directive")); |
f02232aa | 3785 | |
c19d1205 ZW |
3786 | create_unwind_entry (1); |
3787 | } | |
a737bd4d | 3788 | |
c19d1205 | 3789 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 3790 | |
c19d1205 ZW |
3791 | static void |
3792 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
3793 | { | |
3794 | long where; | |
3795 | char *ptr; | |
3796 | valueT val; | |
940b5ce0 | 3797 | unsigned int marked_pr_dependency; |
f02232aa | 3798 | |
c19d1205 | 3799 | demand_empty_rest_of_line (); |
f02232aa | 3800 | |
921e5f0a PB |
3801 | if (!unwind.proc_start) |
3802 | { | |
c921be7d | 3803 | as_bad (_(".fnend directive without .fnstart")); |
921e5f0a PB |
3804 | return; |
3805 | } | |
3806 | ||
c19d1205 ZW |
3807 | /* Add eh table entry. */ |
3808 | if (unwind.table_entry == NULL) | |
3809 | val = create_unwind_entry (0); | |
3810 | else | |
3811 | val = 0; | |
f02232aa | 3812 | |
c19d1205 ZW |
3813 | /* Add index table entry. This is two words. */ |
3814 | start_unwind_section (unwind.saved_seg, 1); | |
3815 | frag_align (2, 0, 0); | |
3816 | record_alignment (now_seg, 2); | |
b99bd4ef | 3817 | |
c19d1205 | 3818 | ptr = frag_more (8); |
5011093d | 3819 | memset (ptr, 0, 8); |
c19d1205 | 3820 | where = frag_now_fix () - 8; |
f02232aa | 3821 | |
c19d1205 ZW |
3822 | /* Self relative offset of the function start. */ |
3823 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
3824 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3825 | |
c19d1205 ZW |
3826 | /* Indicate dependency on EHABI-defined personality routines to the |
3827 | linker, if it hasn't been done already. */ | |
940b5ce0 DJ |
3828 | marked_pr_dependency |
3829 | = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency; | |
c19d1205 ZW |
3830 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 |
3831 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
3832 | { | |
5f4273c7 NC |
3833 | static const char *const name[] = |
3834 | { | |
3835 | "__aeabi_unwind_cpp_pr0", | |
3836 | "__aeabi_unwind_cpp_pr1", | |
3837 | "__aeabi_unwind_cpp_pr2" | |
3838 | }; | |
c19d1205 ZW |
3839 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); |
3840 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
c19d1205 | 3841 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency |
940b5ce0 | 3842 | |= 1 << unwind.personality_index; |
c19d1205 | 3843 | } |
f02232aa | 3844 | |
c19d1205 ZW |
3845 | if (val) |
3846 | /* Inline exception table entry. */ | |
3847 | md_number_to_chars (ptr + 4, val, 4); | |
3848 | else | |
3849 | /* Self relative offset of the table entry. */ | |
3850 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
3851 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3852 | |
c19d1205 ZW |
3853 | /* Restore the original section. */ |
3854 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
921e5f0a PB |
3855 | |
3856 | unwind.proc_start = NULL; | |
c19d1205 | 3857 | } |
f02232aa | 3858 | |
f02232aa | 3859 | |
c19d1205 | 3860 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 3861 | |
c19d1205 ZW |
3862 | static void |
3863 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
3864 | { | |
3865 | demand_empty_rest_of_line (); | |
921e5f0a | 3866 | if (!unwind.proc_start) |
c921be7d | 3867 | as_bad (MISSING_FNSTART); |
921e5f0a | 3868 | |
c19d1205 ZW |
3869 | if (unwind.personality_routine || unwind.personality_index != -1) |
3870 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 3871 | |
c19d1205 ZW |
3872 | unwind.personality_index = -2; |
3873 | } | |
b99bd4ef | 3874 | |
b99bd4ef | 3875 | |
c19d1205 | 3876 | /* Parse a personalityindex directive. */ |
b99bd4ef | 3877 | |
c19d1205 ZW |
3878 | static void |
3879 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
3880 | { | |
3881 | expressionS exp; | |
b99bd4ef | 3882 | |
921e5f0a | 3883 | if (!unwind.proc_start) |
c921be7d | 3884 | as_bad (MISSING_FNSTART); |
921e5f0a | 3885 | |
c19d1205 ZW |
3886 | if (unwind.personality_routine || unwind.personality_index != -1) |
3887 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 3888 | |
c19d1205 | 3889 | expression (&exp); |
b99bd4ef | 3890 | |
c19d1205 ZW |
3891 | if (exp.X_op != O_constant |
3892 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 3893 | { |
c19d1205 ZW |
3894 | as_bad (_("bad personality routine number")); |
3895 | ignore_rest_of_line (); | |
3896 | return; | |
b99bd4ef NC |
3897 | } |
3898 | ||
c19d1205 | 3899 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 3900 | |
c19d1205 ZW |
3901 | demand_empty_rest_of_line (); |
3902 | } | |
e16bb312 | 3903 | |
e16bb312 | 3904 | |
c19d1205 | 3905 | /* Parse a personality directive. */ |
e16bb312 | 3906 | |
c19d1205 ZW |
3907 | static void |
3908 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
3909 | { | |
3910 | char *name, *p, c; | |
a737bd4d | 3911 | |
921e5f0a | 3912 | if (!unwind.proc_start) |
c921be7d | 3913 | as_bad (MISSING_FNSTART); |
921e5f0a | 3914 | |
c19d1205 ZW |
3915 | if (unwind.personality_routine || unwind.personality_index != -1) |
3916 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 3917 | |
c19d1205 ZW |
3918 | name = input_line_pointer; |
3919 | c = get_symbol_end (); | |
3920 | p = input_line_pointer; | |
3921 | unwind.personality_routine = symbol_find_or_make (name); | |
3922 | *p = c; | |
3923 | demand_empty_rest_of_line (); | |
3924 | } | |
e16bb312 | 3925 | |
e16bb312 | 3926 | |
c19d1205 | 3927 | /* Parse a directive saving core registers. */ |
e16bb312 | 3928 | |
c19d1205 ZW |
3929 | static void |
3930 | s_arm_unwind_save_core (void) | |
e16bb312 | 3931 | { |
c19d1205 ZW |
3932 | valueT op; |
3933 | long range; | |
3934 | int n; | |
e16bb312 | 3935 | |
c19d1205 ZW |
3936 | range = parse_reg_list (&input_line_pointer); |
3937 | if (range == FAIL) | |
e16bb312 | 3938 | { |
c19d1205 ZW |
3939 | as_bad (_("expected register list")); |
3940 | ignore_rest_of_line (); | |
3941 | return; | |
3942 | } | |
e16bb312 | 3943 | |
c19d1205 | 3944 | demand_empty_rest_of_line (); |
e16bb312 | 3945 | |
c19d1205 ZW |
3946 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
3947 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
3948 | ip because it is clobbered by calls. */ | |
3949 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
3950 | && (range & 0x3000) == 0x1000) | |
3951 | { | |
3952 | unwind.opcode_count--; | |
3953 | unwind.sp_restored = 0; | |
3954 | range = (range | 0x2000) & ~0x1000; | |
3955 | unwind.pending_offset = 0; | |
3956 | } | |
e16bb312 | 3957 | |
01ae4198 DJ |
3958 | /* Pop r4-r15. */ |
3959 | if (range & 0xfff0) | |
c19d1205 | 3960 | { |
01ae4198 DJ |
3961 | /* See if we can use the short opcodes. These pop a block of up to 8 |
3962 | registers starting with r4, plus maybe r14. */ | |
3963 | for (n = 0; n < 8; n++) | |
3964 | { | |
3965 | /* Break at the first non-saved register. */ | |
3966 | if ((range & (1 << (n + 4))) == 0) | |
3967 | break; | |
3968 | } | |
3969 | /* See if there are any other bits set. */ | |
3970 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
3971 | { | |
3972 | /* Use the long form. */ | |
3973 | op = 0x8000 | ((range >> 4) & 0xfff); | |
3974 | add_unwind_opcode (op, 2); | |
3975 | } | |
0dd132b6 | 3976 | else |
01ae4198 DJ |
3977 | { |
3978 | /* Use the short form. */ | |
3979 | if (range & 0x4000) | |
3980 | op = 0xa8; /* Pop r14. */ | |
3981 | else | |
3982 | op = 0xa0; /* Do not pop r14. */ | |
3983 | op |= (n - 1); | |
3984 | add_unwind_opcode (op, 1); | |
3985 | } | |
c19d1205 | 3986 | } |
0dd132b6 | 3987 | |
c19d1205 ZW |
3988 | /* Pop r0-r3. */ |
3989 | if (range & 0xf) | |
3990 | { | |
3991 | op = 0xb100 | (range & 0xf); | |
3992 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
3993 | } |
3994 | ||
c19d1205 ZW |
3995 | /* Record the number of bytes pushed. */ |
3996 | for (n = 0; n < 16; n++) | |
3997 | { | |
3998 | if (range & (1 << n)) | |
3999 | unwind.frame_size += 4; | |
4000 | } | |
0dd132b6 NC |
4001 | } |
4002 | ||
c19d1205 ZW |
4003 | |
4004 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
4005 | |
4006 | static void | |
c19d1205 | 4007 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 4008 | { |
c19d1205 ZW |
4009 | expressionS exp; |
4010 | int num_regs; | |
4011 | valueT op; | |
b99bd4ef | 4012 | |
c19d1205 ZW |
4013 | /* Get Number of registers to transfer. */ |
4014 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4015 | expression (&exp); | |
4016 | else | |
4017 | exp.X_op = O_illegal; | |
b99bd4ef | 4018 | |
c19d1205 | 4019 | if (exp.X_op != O_constant) |
b99bd4ef | 4020 | { |
c19d1205 ZW |
4021 | as_bad (_("expected , <constant>")); |
4022 | ignore_rest_of_line (); | |
b99bd4ef NC |
4023 | return; |
4024 | } | |
4025 | ||
c19d1205 ZW |
4026 | num_regs = exp.X_add_number; |
4027 | ||
4028 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 4029 | { |
c19d1205 ZW |
4030 | as_bad (_("number of registers must be in the range [1:4]")); |
4031 | ignore_rest_of_line (); | |
b99bd4ef NC |
4032 | return; |
4033 | } | |
4034 | ||
c19d1205 | 4035 | demand_empty_rest_of_line (); |
b99bd4ef | 4036 | |
c19d1205 ZW |
4037 | if (reg == 4) |
4038 | { | |
4039 | /* Short form. */ | |
4040 | op = 0xb4 | (num_regs - 1); | |
4041 | add_unwind_opcode (op, 1); | |
4042 | } | |
b99bd4ef NC |
4043 | else |
4044 | { | |
c19d1205 ZW |
4045 | /* Long form. */ |
4046 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
4047 | add_unwind_opcode (op, 2); | |
b99bd4ef | 4048 | } |
c19d1205 | 4049 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
4050 | } |
4051 | ||
c19d1205 | 4052 | |
fa073d69 MS |
4053 | /* Parse a directive saving VFP registers for ARMv6 and above. */ |
4054 | ||
4055 | static void | |
4056 | s_arm_unwind_save_vfp_armv6 (void) | |
4057 | { | |
4058 | int count; | |
4059 | unsigned int start; | |
4060 | valueT op; | |
4061 | int num_vfpv3_regs = 0; | |
4062 | int num_regs_below_16; | |
4063 | ||
4064 | count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); | |
4065 | if (count == FAIL) | |
4066 | { | |
4067 | as_bad (_("expected register list")); | |
4068 | ignore_rest_of_line (); | |
4069 | return; | |
4070 | } | |
4071 | ||
4072 | demand_empty_rest_of_line (); | |
4073 | ||
4074 | /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather | |
4075 | than FSTMX/FLDMX-style ones). */ | |
4076 | ||
4077 | /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ | |
4078 | if (start >= 16) | |
4079 | num_vfpv3_regs = count; | |
4080 | else if (start + count > 16) | |
4081 | num_vfpv3_regs = start + count - 16; | |
4082 | ||
4083 | if (num_vfpv3_regs > 0) | |
4084 | { | |
4085 | int start_offset = start > 16 ? start - 16 : 0; | |
4086 | op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); | |
4087 | add_unwind_opcode (op, 2); | |
4088 | } | |
4089 | ||
4090 | /* Generate opcode for registers numbered in the range 0 .. 15. */ | |
4091 | num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; | |
9c2799c2 | 4092 | gas_assert (num_regs_below_16 + num_vfpv3_regs == count); |
fa073d69 MS |
4093 | if (num_regs_below_16 > 0) |
4094 | { | |
4095 | op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); | |
4096 | add_unwind_opcode (op, 2); | |
4097 | } | |
4098 | ||
4099 | unwind.frame_size += count * 8; | |
4100 | } | |
4101 | ||
4102 | ||
4103 | /* Parse a directive saving VFP registers for pre-ARMv6. */ | |
b99bd4ef NC |
4104 | |
4105 | static void | |
c19d1205 | 4106 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 4107 | { |
c19d1205 | 4108 | int count; |
ca3f61f7 | 4109 | unsigned int reg; |
c19d1205 | 4110 | valueT op; |
b99bd4ef | 4111 | |
5287ad62 | 4112 | count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); |
c19d1205 | 4113 | if (count == FAIL) |
b99bd4ef | 4114 | { |
c19d1205 ZW |
4115 | as_bad (_("expected register list")); |
4116 | ignore_rest_of_line (); | |
b99bd4ef NC |
4117 | return; |
4118 | } | |
4119 | ||
c19d1205 | 4120 | demand_empty_rest_of_line (); |
b99bd4ef | 4121 | |
c19d1205 | 4122 | if (reg == 8) |
b99bd4ef | 4123 | { |
c19d1205 ZW |
4124 | /* Short form. */ |
4125 | op = 0xb8 | (count - 1); | |
4126 | add_unwind_opcode (op, 1); | |
b99bd4ef | 4127 | } |
c19d1205 | 4128 | else |
b99bd4ef | 4129 | { |
c19d1205 ZW |
4130 | /* Long form. */ |
4131 | op = 0xb300 | (reg << 4) | (count - 1); | |
4132 | add_unwind_opcode (op, 2); | |
b99bd4ef | 4133 | } |
c19d1205 ZW |
4134 | unwind.frame_size += count * 8 + 4; |
4135 | } | |
b99bd4ef | 4136 | |
b99bd4ef | 4137 | |
c19d1205 ZW |
4138 | /* Parse a directive saving iWMMXt data registers. */ |
4139 | ||
4140 | static void | |
4141 | s_arm_unwind_save_mmxwr (void) | |
4142 | { | |
4143 | int reg; | |
4144 | int hi_reg; | |
4145 | int i; | |
4146 | unsigned mask = 0; | |
4147 | valueT op; | |
b99bd4ef | 4148 | |
c19d1205 ZW |
4149 | if (*input_line_pointer == '{') |
4150 | input_line_pointer++; | |
b99bd4ef | 4151 | |
c19d1205 | 4152 | do |
b99bd4ef | 4153 | { |
dcbf9037 | 4154 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 4155 | |
c19d1205 | 4156 | if (reg == FAIL) |
b99bd4ef | 4157 | { |
9b7132d3 | 4158 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 | 4159 | goto error; |
b99bd4ef NC |
4160 | } |
4161 | ||
c19d1205 ZW |
4162 | if (mask >> reg) |
4163 | as_tsktsk (_("register list not in ascending order")); | |
4164 | mask |= 1 << reg; | |
b99bd4ef | 4165 | |
c19d1205 ZW |
4166 | if (*input_line_pointer == '-') |
4167 | { | |
4168 | input_line_pointer++; | |
dcbf9037 | 4169 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
c19d1205 ZW |
4170 | if (hi_reg == FAIL) |
4171 | { | |
9b7132d3 | 4172 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 ZW |
4173 | goto error; |
4174 | } | |
4175 | else if (reg >= hi_reg) | |
4176 | { | |
4177 | as_bad (_("bad register range")); | |
4178 | goto error; | |
4179 | } | |
4180 | for (; reg < hi_reg; reg++) | |
4181 | mask |= 1 << reg; | |
4182 | } | |
4183 | } | |
4184 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 4185 | |
d996d970 | 4186 | skip_past_char (&input_line_pointer, '}'); |
b99bd4ef | 4187 | |
c19d1205 | 4188 | demand_empty_rest_of_line (); |
b99bd4ef | 4189 | |
708587a4 | 4190 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
4191 | the list. */ |
4192 | flush_pending_unwind (); | |
b99bd4ef | 4193 | |
c19d1205 | 4194 | for (i = 0; i < 16; i++) |
b99bd4ef | 4195 | { |
c19d1205 ZW |
4196 | if (mask & (1 << i)) |
4197 | unwind.frame_size += 8; | |
b99bd4ef NC |
4198 | } |
4199 | ||
c19d1205 ZW |
4200 | /* Attempt to combine with a previous opcode. We do this because gcc |
4201 | likes to output separate unwind directives for a single block of | |
4202 | registers. */ | |
4203 | if (unwind.opcode_count > 0) | |
b99bd4ef | 4204 | { |
c19d1205 ZW |
4205 | i = unwind.opcodes[unwind.opcode_count - 1]; |
4206 | if ((i & 0xf8) == 0xc0) | |
4207 | { | |
4208 | i &= 7; | |
4209 | /* Only merge if the blocks are contiguous. */ | |
4210 | if (i < 6) | |
4211 | { | |
4212 | if ((mask & 0xfe00) == (1 << 9)) | |
4213 | { | |
4214 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
4215 | unwind.opcode_count--; | |
4216 | } | |
4217 | } | |
4218 | else if (i == 6 && unwind.opcode_count >= 2) | |
4219 | { | |
4220 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
4221 | reg = i >> 4; | |
4222 | i &= 0xf; | |
b99bd4ef | 4223 | |
c19d1205 ZW |
4224 | op = 0xffff << (reg - 1); |
4225 | if (reg > 0 | |
87a1fd79 | 4226 | && ((mask & op) == (1u << (reg - 1)))) |
c19d1205 ZW |
4227 | { |
4228 | op = (1 << (reg + i + 1)) - 1; | |
4229 | op &= ~((1 << reg) - 1); | |
4230 | mask |= op; | |
4231 | unwind.opcode_count -= 2; | |
4232 | } | |
4233 | } | |
4234 | } | |
b99bd4ef NC |
4235 | } |
4236 | ||
c19d1205 ZW |
4237 | hi_reg = 15; |
4238 | /* We want to generate opcodes in the order the registers have been | |
4239 | saved, ie. descending order. */ | |
4240 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 4241 | { |
c19d1205 ZW |
4242 | /* Save registers in blocks. */ |
4243 | if (reg < 0 | |
4244 | || !(mask & (1 << reg))) | |
4245 | { | |
4246 | /* We found an unsaved reg. Generate opcodes to save the | |
5f4273c7 | 4247 | preceding block. */ |
c19d1205 ZW |
4248 | if (reg != hi_reg) |
4249 | { | |
4250 | if (reg == 9) | |
4251 | { | |
4252 | /* Short form. */ | |
4253 | op = 0xc0 | (hi_reg - 10); | |
4254 | add_unwind_opcode (op, 1); | |
4255 | } | |
4256 | else | |
4257 | { | |
4258 | /* Long form. */ | |
4259 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
4260 | add_unwind_opcode (op, 2); | |
4261 | } | |
4262 | } | |
4263 | hi_reg = reg - 1; | |
4264 | } | |
b99bd4ef NC |
4265 | } |
4266 | ||
c19d1205 ZW |
4267 | return; |
4268 | error: | |
4269 | ignore_rest_of_line (); | |
b99bd4ef NC |
4270 | } |
4271 | ||
4272 | static void | |
c19d1205 | 4273 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 4274 | { |
c19d1205 ZW |
4275 | int reg; |
4276 | int hi_reg; | |
4277 | unsigned mask = 0; | |
4278 | valueT op; | |
b99bd4ef | 4279 | |
c19d1205 ZW |
4280 | if (*input_line_pointer == '{') |
4281 | input_line_pointer++; | |
b99bd4ef | 4282 | |
477330fc RM |
4283 | skip_whitespace (input_line_pointer); |
4284 | ||
c19d1205 | 4285 | do |
b99bd4ef | 4286 | { |
dcbf9037 | 4287 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 4288 | |
c19d1205 ZW |
4289 | if (reg == FAIL) |
4290 | { | |
9b7132d3 | 4291 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4292 | goto error; |
4293 | } | |
b99bd4ef | 4294 | |
c19d1205 ZW |
4295 | reg -= 8; |
4296 | if (mask >> reg) | |
4297 | as_tsktsk (_("register list not in ascending order")); | |
4298 | mask |= 1 << reg; | |
b99bd4ef | 4299 | |
c19d1205 ZW |
4300 | if (*input_line_pointer == '-') |
4301 | { | |
4302 | input_line_pointer++; | |
dcbf9037 | 4303 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
c19d1205 ZW |
4304 | if (hi_reg == FAIL) |
4305 | { | |
9b7132d3 | 4306 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4307 | goto error; |
4308 | } | |
4309 | else if (reg >= hi_reg) | |
4310 | { | |
4311 | as_bad (_("bad register range")); | |
4312 | goto error; | |
4313 | } | |
4314 | for (; reg < hi_reg; reg++) | |
4315 | mask |= 1 << reg; | |
4316 | } | |
b99bd4ef | 4317 | } |
c19d1205 | 4318 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 4319 | |
d996d970 | 4320 | skip_past_char (&input_line_pointer, '}'); |
b99bd4ef | 4321 | |
c19d1205 ZW |
4322 | demand_empty_rest_of_line (); |
4323 | ||
708587a4 | 4324 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
4325 | the list. */ |
4326 | flush_pending_unwind (); | |
b99bd4ef | 4327 | |
c19d1205 | 4328 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 4329 | { |
c19d1205 ZW |
4330 | if (mask & (1 << reg)) |
4331 | unwind.frame_size += 4; | |
b99bd4ef | 4332 | } |
c19d1205 ZW |
4333 | op = 0xc700 | mask; |
4334 | add_unwind_opcode (op, 2); | |
4335 | return; | |
4336 | error: | |
4337 | ignore_rest_of_line (); | |
b99bd4ef NC |
4338 | } |
4339 | ||
c19d1205 | 4340 | |
fa073d69 MS |
4341 | /* Parse an unwind_save directive. |
4342 | If the argument is non-zero, this is a .vsave directive. */ | |
c19d1205 | 4343 | |
b99bd4ef | 4344 | static void |
fa073d69 | 4345 | s_arm_unwind_save (int arch_v6) |
b99bd4ef | 4346 | { |
c19d1205 ZW |
4347 | char *peek; |
4348 | struct reg_entry *reg; | |
4349 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 4350 | |
921e5f0a | 4351 | if (!unwind.proc_start) |
c921be7d | 4352 | as_bad (MISSING_FNSTART); |
921e5f0a | 4353 | |
c19d1205 ZW |
4354 | /* Figure out what sort of save we have. */ |
4355 | peek = input_line_pointer; | |
b99bd4ef | 4356 | |
c19d1205 | 4357 | if (*peek == '{') |
b99bd4ef | 4358 | { |
c19d1205 ZW |
4359 | had_brace = TRUE; |
4360 | peek++; | |
b99bd4ef NC |
4361 | } |
4362 | ||
c19d1205 | 4363 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 4364 | |
c19d1205 | 4365 | if (!reg) |
b99bd4ef | 4366 | { |
c19d1205 ZW |
4367 | as_bad (_("register expected")); |
4368 | ignore_rest_of_line (); | |
b99bd4ef NC |
4369 | return; |
4370 | } | |
4371 | ||
c19d1205 | 4372 | switch (reg->type) |
b99bd4ef | 4373 | { |
c19d1205 ZW |
4374 | case REG_TYPE_FN: |
4375 | if (had_brace) | |
4376 | { | |
4377 | as_bad (_("FPA .unwind_save does not take a register list")); | |
4378 | ignore_rest_of_line (); | |
4379 | return; | |
4380 | } | |
93ac2687 | 4381 | input_line_pointer = peek; |
c19d1205 | 4382 | s_arm_unwind_save_fpa (reg->number); |
b99bd4ef | 4383 | return; |
c19d1205 | 4384 | |
1f5afe1c NC |
4385 | case REG_TYPE_RN: |
4386 | s_arm_unwind_save_core (); | |
4387 | return; | |
4388 | ||
fa073d69 MS |
4389 | case REG_TYPE_VFD: |
4390 | if (arch_v6) | |
477330fc | 4391 | s_arm_unwind_save_vfp_armv6 (); |
fa073d69 | 4392 | else |
477330fc | 4393 | s_arm_unwind_save_vfp (); |
fa073d69 | 4394 | return; |
1f5afe1c NC |
4395 | |
4396 | case REG_TYPE_MMXWR: | |
4397 | s_arm_unwind_save_mmxwr (); | |
4398 | return; | |
4399 | ||
4400 | case REG_TYPE_MMXWCG: | |
4401 | s_arm_unwind_save_mmxwcg (); | |
4402 | return; | |
c19d1205 ZW |
4403 | |
4404 | default: | |
4405 | as_bad (_(".unwind_save does not support this kind of register")); | |
4406 | ignore_rest_of_line (); | |
b99bd4ef | 4407 | } |
c19d1205 | 4408 | } |
b99bd4ef | 4409 | |
b99bd4ef | 4410 | |
c19d1205 ZW |
4411 | /* Parse an unwind_movsp directive. */ |
4412 | ||
4413 | static void | |
4414 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
4415 | { | |
4416 | int reg; | |
4417 | valueT op; | |
4fa3602b | 4418 | int offset; |
c19d1205 | 4419 | |
921e5f0a | 4420 | if (!unwind.proc_start) |
c921be7d | 4421 | as_bad (MISSING_FNSTART); |
921e5f0a | 4422 | |
dcbf9037 | 4423 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 | 4424 | if (reg == FAIL) |
b99bd4ef | 4425 | { |
9b7132d3 | 4426 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 | 4427 | ignore_rest_of_line (); |
b99bd4ef NC |
4428 | return; |
4429 | } | |
4fa3602b PB |
4430 | |
4431 | /* Optional constant. */ | |
4432 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4433 | { | |
4434 | if (immediate_for_directive (&offset) == FAIL) | |
4435 | return; | |
4436 | } | |
4437 | else | |
4438 | offset = 0; | |
4439 | ||
c19d1205 | 4440 | demand_empty_rest_of_line (); |
b99bd4ef | 4441 | |
c19d1205 | 4442 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 4443 | { |
c19d1205 | 4444 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
4445 | return; |
4446 | } | |
4447 | ||
c19d1205 ZW |
4448 | if (unwind.fp_reg != REG_SP) |
4449 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 4450 | |
c19d1205 ZW |
4451 | /* Generate opcode to restore the value. */ |
4452 | op = 0x90 | reg; | |
4453 | add_unwind_opcode (op, 1); | |
4454 | ||
4455 | /* Record the information for later. */ | |
4456 | unwind.fp_reg = reg; | |
4fa3602b | 4457 | unwind.fp_offset = unwind.frame_size - offset; |
c19d1205 | 4458 | unwind.sp_restored = 1; |
b05fe5cf ZW |
4459 | } |
4460 | ||
c19d1205 ZW |
4461 | /* Parse an unwind_pad directive. */ |
4462 | ||
b05fe5cf | 4463 | static void |
c19d1205 | 4464 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 4465 | { |
c19d1205 | 4466 | int offset; |
b05fe5cf | 4467 | |
921e5f0a | 4468 | if (!unwind.proc_start) |
c921be7d | 4469 | as_bad (MISSING_FNSTART); |
921e5f0a | 4470 | |
c19d1205 ZW |
4471 | if (immediate_for_directive (&offset) == FAIL) |
4472 | return; | |
b99bd4ef | 4473 | |
c19d1205 ZW |
4474 | if (offset & 3) |
4475 | { | |
4476 | as_bad (_("stack increment must be multiple of 4")); | |
4477 | ignore_rest_of_line (); | |
4478 | return; | |
4479 | } | |
b99bd4ef | 4480 | |
c19d1205 ZW |
4481 | /* Don't generate any opcodes, just record the details for later. */ |
4482 | unwind.frame_size += offset; | |
4483 | unwind.pending_offset += offset; | |
4484 | ||
4485 | demand_empty_rest_of_line (); | |
4486 | } | |
4487 | ||
4488 | /* Parse an unwind_setfp directive. */ | |
4489 | ||
4490 | static void | |
4491 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 4492 | { |
c19d1205 ZW |
4493 | int sp_reg; |
4494 | int fp_reg; | |
4495 | int offset; | |
4496 | ||
921e5f0a | 4497 | if (!unwind.proc_start) |
c921be7d | 4498 | as_bad (MISSING_FNSTART); |
921e5f0a | 4499 | |
dcbf9037 | 4500 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 ZW |
4501 | if (skip_past_comma (&input_line_pointer) == FAIL) |
4502 | sp_reg = FAIL; | |
4503 | else | |
dcbf9037 | 4504 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
b99bd4ef | 4505 | |
c19d1205 ZW |
4506 | if (fp_reg == FAIL || sp_reg == FAIL) |
4507 | { | |
4508 | as_bad (_("expected <reg>, <reg>")); | |
4509 | ignore_rest_of_line (); | |
4510 | return; | |
4511 | } | |
b99bd4ef | 4512 | |
c19d1205 ZW |
4513 | /* Optional constant. */ |
4514 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4515 | { | |
4516 | if (immediate_for_directive (&offset) == FAIL) | |
4517 | return; | |
4518 | } | |
4519 | else | |
4520 | offset = 0; | |
a737bd4d | 4521 | |
c19d1205 | 4522 | demand_empty_rest_of_line (); |
a737bd4d | 4523 | |
fdfde340 | 4524 | if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) |
a737bd4d | 4525 | { |
c19d1205 ZW |
4526 | as_bad (_("register must be either sp or set by a previous" |
4527 | "unwind_movsp directive")); | |
4528 | return; | |
a737bd4d NC |
4529 | } |
4530 | ||
c19d1205 ZW |
4531 | /* Don't generate any opcodes, just record the information for later. */ |
4532 | unwind.fp_reg = fp_reg; | |
4533 | unwind.fp_used = 1; | |
fdfde340 | 4534 | if (sp_reg == REG_SP) |
c19d1205 ZW |
4535 | unwind.fp_offset = unwind.frame_size - offset; |
4536 | else | |
4537 | unwind.fp_offset -= offset; | |
a737bd4d NC |
4538 | } |
4539 | ||
c19d1205 ZW |
4540 | /* Parse an unwind_raw directive. */ |
4541 | ||
4542 | static void | |
4543 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 4544 | { |
c19d1205 | 4545 | expressionS exp; |
708587a4 | 4546 | /* This is an arbitrary limit. */ |
c19d1205 ZW |
4547 | unsigned char op[16]; |
4548 | int count; | |
a737bd4d | 4549 | |
921e5f0a | 4550 | if (!unwind.proc_start) |
c921be7d | 4551 | as_bad (MISSING_FNSTART); |
921e5f0a | 4552 | |
c19d1205 ZW |
4553 | expression (&exp); |
4554 | if (exp.X_op == O_constant | |
4555 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 4556 | { |
c19d1205 ZW |
4557 | unwind.frame_size += exp.X_add_number; |
4558 | expression (&exp); | |
4559 | } | |
4560 | else | |
4561 | exp.X_op = O_illegal; | |
a737bd4d | 4562 | |
c19d1205 ZW |
4563 | if (exp.X_op != O_constant) |
4564 | { | |
4565 | as_bad (_("expected <offset>, <opcode>")); | |
4566 | ignore_rest_of_line (); | |
4567 | return; | |
4568 | } | |
a737bd4d | 4569 | |
c19d1205 | 4570 | count = 0; |
a737bd4d | 4571 | |
c19d1205 ZW |
4572 | /* Parse the opcode. */ |
4573 | for (;;) | |
4574 | { | |
4575 | if (count >= 16) | |
4576 | { | |
4577 | as_bad (_("unwind opcode too long")); | |
4578 | ignore_rest_of_line (); | |
a737bd4d | 4579 | } |
c19d1205 | 4580 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 4581 | { |
c19d1205 ZW |
4582 | as_bad (_("invalid unwind opcode")); |
4583 | ignore_rest_of_line (); | |
4584 | return; | |
a737bd4d | 4585 | } |
c19d1205 | 4586 | op[count++] = exp.X_add_number; |
a737bd4d | 4587 | |
c19d1205 ZW |
4588 | /* Parse the next byte. */ |
4589 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
4590 | break; | |
a737bd4d | 4591 | |
c19d1205 ZW |
4592 | expression (&exp); |
4593 | } | |
b99bd4ef | 4594 | |
c19d1205 ZW |
4595 | /* Add the opcode bytes in reverse order. */ |
4596 | while (count--) | |
4597 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 4598 | |
c19d1205 | 4599 | demand_empty_rest_of_line (); |
b99bd4ef | 4600 | } |
ee065d83 PB |
4601 | |
4602 | ||
4603 | /* Parse a .eabi_attribute directive. */ | |
4604 | ||
4605 | static void | |
4606 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) | |
4607 | { | |
0420f52b | 4608 | int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC); |
ee3c0378 AS |
4609 | |
4610 | if (tag < NUM_KNOWN_OBJ_ATTRIBUTES) | |
4611 | attributes_set_explicitly[tag] = 1; | |
ee065d83 PB |
4612 | } |
4613 | ||
0855e32b NS |
4614 | /* Emit a tls fix for the symbol. */ |
4615 | ||
4616 | static void | |
4617 | s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED) | |
4618 | { | |
4619 | char *p; | |
4620 | expressionS exp; | |
4621 | #ifdef md_flush_pending_output | |
4622 | md_flush_pending_output (); | |
4623 | #endif | |
4624 | ||
4625 | #ifdef md_cons_align | |
4626 | md_cons_align (4); | |
4627 | #endif | |
4628 | ||
4629 | /* Since we're just labelling the code, there's no need to define a | |
4630 | mapping symbol. */ | |
4631 | expression (&exp); | |
4632 | p = obstack_next_free (&frchain_now->frch_obstack); | |
4633 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0, | |
4634 | thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
4635 | : BFD_RELOC_ARM_TLS_DESCSEQ); | |
4636 | } | |
cdf9ccec | 4637 | #endif /* OBJ_ELF */ |
0855e32b | 4638 | |
ee065d83 | 4639 | static void s_arm_arch (int); |
7a1d4c38 | 4640 | static void s_arm_object_arch (int); |
ee065d83 PB |
4641 | static void s_arm_cpu (int); |
4642 | static void s_arm_fpu (int); | |
69133863 | 4643 | static void s_arm_arch_extension (int); |
b99bd4ef | 4644 | |
f0927246 NC |
4645 | #ifdef TE_PE |
4646 | ||
4647 | static void | |
5f4273c7 | 4648 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
f0927246 NC |
4649 | { |
4650 | expressionS exp; | |
4651 | ||
4652 | do | |
4653 | { | |
4654 | expression (&exp); | |
4655 | if (exp.X_op == O_symbol) | |
4656 | exp.X_op = O_secrel; | |
4657 | ||
4658 | emit_expr (&exp, 4); | |
4659 | } | |
4660 | while (*input_line_pointer++ == ','); | |
4661 | ||
4662 | input_line_pointer--; | |
4663 | demand_empty_rest_of_line (); | |
4664 | } | |
4665 | #endif /* TE_PE */ | |
4666 | ||
c19d1205 ZW |
4667 | /* This table describes all the machine specific pseudo-ops the assembler |
4668 | has to support. The fields are: | |
4669 | pseudo-op name without dot | |
4670 | function to call to execute this pseudo-op | |
4671 | Integer arg to pass to the function. */ | |
b99bd4ef | 4672 | |
c19d1205 | 4673 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 4674 | { |
c19d1205 ZW |
4675 | /* Never called because '.req' does not start a line. */ |
4676 | { "req", s_req, 0 }, | |
dcbf9037 JB |
4677 | /* Following two are likewise never called. */ |
4678 | { "dn", s_dn, 0 }, | |
4679 | { "qn", s_qn, 0 }, | |
c19d1205 ZW |
4680 | { "unreq", s_unreq, 0 }, |
4681 | { "bss", s_bss, 0 }, | |
4682 | { "align", s_align, 0 }, | |
4683 | { "arm", s_arm, 0 }, | |
4684 | { "thumb", s_thumb, 0 }, | |
4685 | { "code", s_code, 0 }, | |
4686 | { "force_thumb", s_force_thumb, 0 }, | |
4687 | { "thumb_func", s_thumb_func, 0 }, | |
4688 | { "thumb_set", s_thumb_set, 0 }, | |
4689 | { "even", s_even, 0 }, | |
4690 | { "ltorg", s_ltorg, 0 }, | |
4691 | { "pool", s_ltorg, 0 }, | |
4692 | { "syntax", s_syntax, 0 }, | |
8463be01 PB |
4693 | { "cpu", s_arm_cpu, 0 }, |
4694 | { "arch", s_arm_arch, 0 }, | |
7a1d4c38 | 4695 | { "object_arch", s_arm_object_arch, 0 }, |
8463be01 | 4696 | { "fpu", s_arm_fpu, 0 }, |
69133863 | 4697 | { "arch_extension", s_arm_arch_extension, 0 }, |
c19d1205 | 4698 | #ifdef OBJ_ELF |
c921be7d NC |
4699 | { "word", s_arm_elf_cons, 4 }, |
4700 | { "long", s_arm_elf_cons, 4 }, | |
4701 | { "inst.n", s_arm_elf_inst, 2 }, | |
4702 | { "inst.w", s_arm_elf_inst, 4 }, | |
4703 | { "inst", s_arm_elf_inst, 0 }, | |
4704 | { "rel31", s_arm_rel31, 0 }, | |
c19d1205 ZW |
4705 | { "fnstart", s_arm_unwind_fnstart, 0 }, |
4706 | { "fnend", s_arm_unwind_fnend, 0 }, | |
4707 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
4708 | { "personality", s_arm_unwind_personality, 0 }, | |
4709 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
4710 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
4711 | { "save", s_arm_unwind_save, 0 }, | |
fa073d69 | 4712 | { "vsave", s_arm_unwind_save, 1 }, |
c19d1205 ZW |
4713 | { "movsp", s_arm_unwind_movsp, 0 }, |
4714 | { "pad", s_arm_unwind_pad, 0 }, | |
4715 | { "setfp", s_arm_unwind_setfp, 0 }, | |
4716 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
ee065d83 | 4717 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, |
0855e32b | 4718 | { "tlsdescseq", s_arm_tls_descseq, 0 }, |
c19d1205 ZW |
4719 | #else |
4720 | { "word", cons, 4}, | |
f0927246 NC |
4721 | |
4722 | /* These are used for dwarf. */ | |
4723 | {"2byte", cons, 2}, | |
4724 | {"4byte", cons, 4}, | |
4725 | {"8byte", cons, 8}, | |
4726 | /* These are used for dwarf2. */ | |
4727 | { "file", (void (*) (int)) dwarf2_directive_file, 0 }, | |
4728 | { "loc", dwarf2_directive_loc, 0 }, | |
4729 | { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, | |
c19d1205 ZW |
4730 | #endif |
4731 | { "extend", float_cons, 'x' }, | |
4732 | { "ldouble", float_cons, 'x' }, | |
4733 | { "packed", float_cons, 'p' }, | |
f0927246 NC |
4734 | #ifdef TE_PE |
4735 | {"secrel32", pe_directive_secrel, 0}, | |
4736 | #endif | |
2e6976a8 DG |
4737 | |
4738 | /* These are for compatibility with CodeComposer Studio. */ | |
4739 | {"ref", s_ccs_ref, 0}, | |
4740 | {"def", s_ccs_def, 0}, | |
4741 | {"asmfunc", s_ccs_asmfunc, 0}, | |
4742 | {"endasmfunc", s_ccs_endasmfunc, 0}, | |
4743 | ||
c19d1205 ZW |
4744 | { 0, 0, 0 } |
4745 | }; | |
4746 | \f | |
4747 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 4748 | |
c19d1205 ZW |
4749 | /* Generic immediate-value read function for use in insn parsing. |
4750 | STR points to the beginning of the immediate (the leading #); | |
4751 | VAL receives the value; if the value is outside [MIN, MAX] | |
4752 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
4753 | optional. */ | |
b99bd4ef | 4754 | |
c19d1205 ZW |
4755 | static int |
4756 | parse_immediate (char **str, int *val, int min, int max, | |
4757 | bfd_boolean prefix_opt) | |
4758 | { | |
4759 | expressionS exp; | |
4760 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); | |
4761 | if (exp.X_op != O_constant) | |
b99bd4ef | 4762 | { |
c19d1205 ZW |
4763 | inst.error = _("constant expression required"); |
4764 | return FAIL; | |
4765 | } | |
b99bd4ef | 4766 | |
c19d1205 ZW |
4767 | if (exp.X_add_number < min || exp.X_add_number > max) |
4768 | { | |
4769 | inst.error = _("immediate value out of range"); | |
4770 | return FAIL; | |
4771 | } | |
b99bd4ef | 4772 | |
c19d1205 ZW |
4773 | *val = exp.X_add_number; |
4774 | return SUCCESS; | |
4775 | } | |
b99bd4ef | 4776 | |
5287ad62 | 4777 | /* Less-generic immediate-value read function with the possibility of loading a |
036dc3f7 | 4778 | big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate |
5287ad62 JB |
4779 | instructions. Puts the result directly in inst.operands[i]. */ |
4780 | ||
4781 | static int | |
8335d6aa JW |
4782 | parse_big_immediate (char **str, int i, expressionS *in_exp, |
4783 | bfd_boolean allow_symbol_p) | |
5287ad62 JB |
4784 | { |
4785 | expressionS exp; | |
8335d6aa | 4786 | expressionS *exp_p = in_exp ? in_exp : &exp; |
5287ad62 JB |
4787 | char *ptr = *str; |
4788 | ||
8335d6aa | 4789 | my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG); |
5287ad62 | 4790 | |
8335d6aa | 4791 | if (exp_p->X_op == O_constant) |
036dc3f7 | 4792 | { |
8335d6aa | 4793 | inst.operands[i].imm = exp_p->X_add_number & 0xffffffff; |
036dc3f7 PB |
4794 | /* If we're on a 64-bit host, then a 64-bit number can be returned using |
4795 | O_constant. We have to be careful not to break compilation for | |
4796 | 32-bit X_add_number, though. */ | |
8335d6aa | 4797 | if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0) |
036dc3f7 | 4798 | { |
8335d6aa JW |
4799 | /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */ |
4800 | inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16) | |
4801 | & 0xffffffff); | |
036dc3f7 PB |
4802 | inst.operands[i].regisimm = 1; |
4803 | } | |
4804 | } | |
8335d6aa JW |
4805 | else if (exp_p->X_op == O_big |
4806 | && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32) | |
5287ad62 JB |
4807 | { |
4808 | unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; | |
95b75c01 | 4809 | |
5287ad62 | 4810 | /* Bignums have their least significant bits in |
477330fc RM |
4811 | generic_bignum[0]. Make sure we put 32 bits in imm and |
4812 | 32 bits in reg, in a (hopefully) portable way. */ | |
9c2799c2 | 4813 | gas_assert (parts != 0); |
95b75c01 NC |
4814 | |
4815 | /* Make sure that the number is not too big. | |
4816 | PR 11972: Bignums can now be sign-extended to the | |
4817 | size of a .octa so check that the out of range bits | |
4818 | are all zero or all one. */ | |
8335d6aa | 4819 | if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64) |
95b75c01 NC |
4820 | { |
4821 | LITTLENUM_TYPE m = -1; | |
4822 | ||
4823 | if (generic_bignum[parts * 2] != 0 | |
4824 | && generic_bignum[parts * 2] != m) | |
4825 | return FAIL; | |
4826 | ||
8335d6aa | 4827 | for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++) |
95b75c01 NC |
4828 | if (generic_bignum[j] != generic_bignum[j-1]) |
4829 | return FAIL; | |
4830 | } | |
4831 | ||
5287ad62 JB |
4832 | inst.operands[i].imm = 0; |
4833 | for (j = 0; j < parts; j++, idx++) | |
477330fc RM |
4834 | inst.operands[i].imm |= generic_bignum[idx] |
4835 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
5287ad62 JB |
4836 | inst.operands[i].reg = 0; |
4837 | for (j = 0; j < parts; j++, idx++) | |
477330fc RM |
4838 | inst.operands[i].reg |= generic_bignum[idx] |
4839 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
5287ad62 JB |
4840 | inst.operands[i].regisimm = 1; |
4841 | } | |
8335d6aa | 4842 | else if (!(exp_p->X_op == O_symbol && allow_symbol_p)) |
5287ad62 | 4843 | return FAIL; |
5f4273c7 | 4844 | |
5287ad62 JB |
4845 | *str = ptr; |
4846 | ||
4847 | return SUCCESS; | |
4848 | } | |
4849 | ||
c19d1205 ZW |
4850 | /* Returns the pseudo-register number of an FPA immediate constant, |
4851 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 4852 | |
c19d1205 ZW |
4853 | static int |
4854 | parse_fpa_immediate (char ** str) | |
4855 | { | |
4856 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4857 | char * save_in; | |
4858 | expressionS exp; | |
4859 | int i; | |
4860 | int j; | |
b99bd4ef | 4861 | |
c19d1205 ZW |
4862 | /* First try and match exact strings, this is to guarantee |
4863 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 4864 | |
c19d1205 ZW |
4865 | for (i = 0; fp_const[i]; i++) |
4866 | { | |
4867 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 4868 | { |
c19d1205 | 4869 | char *start = *str; |
b99bd4ef | 4870 | |
c19d1205 ZW |
4871 | *str += strlen (fp_const[i]); |
4872 | if (is_end_of_line[(unsigned char) **str]) | |
4873 | return i + 8; | |
4874 | *str = start; | |
4875 | } | |
4876 | } | |
b99bd4ef | 4877 | |
c19d1205 ZW |
4878 | /* Just because we didn't get a match doesn't mean that the constant |
4879 | isn't valid, just that it is in a format that we don't | |
4880 | automatically recognize. Try parsing it with the standard | |
4881 | expression routines. */ | |
b99bd4ef | 4882 | |
c19d1205 | 4883 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 4884 | |
c19d1205 ZW |
4885 | /* Look for a raw floating point number. */ |
4886 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
4887 | && is_end_of_line[(unsigned char) *save_in]) | |
4888 | { | |
4889 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4890 | { | |
4891 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 4892 | { |
c19d1205 ZW |
4893 | if (words[j] != fp_values[i][j]) |
4894 | break; | |
b99bd4ef NC |
4895 | } |
4896 | ||
c19d1205 | 4897 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 4898 | { |
c19d1205 ZW |
4899 | *str = save_in; |
4900 | return i + 8; | |
b99bd4ef NC |
4901 | } |
4902 | } | |
4903 | } | |
b99bd4ef | 4904 | |
c19d1205 ZW |
4905 | /* Try and parse a more complex expression, this will probably fail |
4906 | unless the code uses a floating point prefix (eg "0f"). */ | |
4907 | save_in = input_line_pointer; | |
4908 | input_line_pointer = *str; | |
4909 | if (expression (&exp) == absolute_section | |
4910 | && exp.X_op == O_big | |
4911 | && exp.X_add_number < 0) | |
4912 | { | |
4913 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
4914 | Ditto for 15. */ | |
4915 | if (gen_to_words (words, 5, (long) 15) == 0) | |
4916 | { | |
4917 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4918 | { | |
4919 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
4920 | { | |
4921 | if (words[j] != fp_values[i][j]) | |
4922 | break; | |
4923 | } | |
b99bd4ef | 4924 | |
c19d1205 ZW |
4925 | if (j == MAX_LITTLENUMS) |
4926 | { | |
4927 | *str = input_line_pointer; | |
4928 | input_line_pointer = save_in; | |
4929 | return i + 8; | |
4930 | } | |
4931 | } | |
4932 | } | |
b99bd4ef NC |
4933 | } |
4934 | ||
c19d1205 ZW |
4935 | *str = input_line_pointer; |
4936 | input_line_pointer = save_in; | |
4937 | inst.error = _("invalid FPA immediate expression"); | |
4938 | return FAIL; | |
b99bd4ef NC |
4939 | } |
4940 | ||
136da414 JB |
4941 | /* Returns 1 if a number has "quarter-precision" float format |
4942 | 0baBbbbbbc defgh000 00000000 00000000. */ | |
4943 | ||
4944 | static int | |
4945 | is_quarter_float (unsigned imm) | |
4946 | { | |
4947 | int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; | |
4948 | return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; | |
4949 | } | |
4950 | ||
aacf0b33 KT |
4951 | |
4952 | /* Detect the presence of a floating point or integer zero constant, | |
4953 | i.e. #0.0 or #0. */ | |
4954 | ||
4955 | static bfd_boolean | |
4956 | parse_ifimm_zero (char **in) | |
4957 | { | |
4958 | int error_code; | |
4959 | ||
4960 | if (!is_immediate_prefix (**in)) | |
4961 | return FALSE; | |
4962 | ||
4963 | ++*in; | |
0900a05b JW |
4964 | |
4965 | /* Accept #0x0 as a synonym for #0. */ | |
4966 | if (strncmp (*in, "0x", 2) == 0) | |
4967 | { | |
4968 | int val; | |
4969 | if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL) | |
4970 | return FALSE; | |
4971 | return TRUE; | |
4972 | } | |
4973 | ||
aacf0b33 KT |
4974 | error_code = atof_generic (in, ".", EXP_CHARS, |
4975 | &generic_floating_point_number); | |
4976 | ||
4977 | if (!error_code | |
4978 | && generic_floating_point_number.sign == '+' | |
4979 | && (generic_floating_point_number.low | |
4980 | > generic_floating_point_number.leader)) | |
4981 | return TRUE; | |
4982 | ||
4983 | return FALSE; | |
4984 | } | |
4985 | ||
136da414 JB |
4986 | /* Parse an 8-bit "quarter-precision" floating point number of the form: |
4987 | 0baBbbbbbc defgh000 00000000 00000000. | |
c96612cc JB |
4988 | The zero and minus-zero cases need special handling, since they can't be |
4989 | encoded in the "quarter-precision" float format, but can nonetheless be | |
4990 | loaded as integer constants. */ | |
136da414 JB |
4991 | |
4992 | static unsigned | |
4993 | parse_qfloat_immediate (char **ccp, int *immed) | |
4994 | { | |
4995 | char *str = *ccp; | |
c96612cc | 4996 | char *fpnum; |
136da414 | 4997 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
c96612cc | 4998 | int found_fpchar = 0; |
5f4273c7 | 4999 | |
136da414 | 5000 | skip_past_char (&str, '#'); |
5f4273c7 | 5001 | |
c96612cc JB |
5002 | /* We must not accidentally parse an integer as a floating-point number. Make |
5003 | sure that the value we parse is not an integer by checking for special | |
5004 | characters '.' or 'e'. | |
5005 | FIXME: This is a horrible hack, but doing better is tricky because type | |
5006 | information isn't in a very usable state at parse time. */ | |
5007 | fpnum = str; | |
5008 | skip_whitespace (fpnum); | |
5009 | ||
5010 | if (strncmp (fpnum, "0x", 2) == 0) | |
5011 | return FAIL; | |
5012 | else | |
5013 | { | |
5014 | for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) | |
477330fc RM |
5015 | if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') |
5016 | { | |
5017 | found_fpchar = 1; | |
5018 | break; | |
5019 | } | |
c96612cc JB |
5020 | |
5021 | if (!found_fpchar) | |
477330fc | 5022 | return FAIL; |
c96612cc | 5023 | } |
5f4273c7 | 5024 | |
136da414 JB |
5025 | if ((str = atof_ieee (str, 's', words)) != NULL) |
5026 | { | |
5027 | unsigned fpword = 0; | |
5028 | int i; | |
5f4273c7 | 5029 | |
136da414 JB |
5030 | /* Our FP word must be 32 bits (single-precision FP). */ |
5031 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) | |
477330fc RM |
5032 | { |
5033 | fpword <<= LITTLENUM_NUMBER_OF_BITS; | |
5034 | fpword |= words[i]; | |
5035 | } | |
5f4273c7 | 5036 | |
c96612cc | 5037 | if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) |
477330fc | 5038 | *immed = fpword; |
136da414 | 5039 | else |
477330fc | 5040 | return FAIL; |
136da414 JB |
5041 | |
5042 | *ccp = str; | |
5f4273c7 | 5043 | |
136da414 JB |
5044 | return SUCCESS; |
5045 | } | |
5f4273c7 | 5046 | |
136da414 JB |
5047 | return FAIL; |
5048 | } | |
5049 | ||
c19d1205 ZW |
5050 | /* Shift operands. */ |
5051 | enum shift_kind | |
b99bd4ef | 5052 | { |
c19d1205 ZW |
5053 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX |
5054 | }; | |
b99bd4ef | 5055 | |
c19d1205 ZW |
5056 | struct asm_shift_name |
5057 | { | |
5058 | const char *name; | |
5059 | enum shift_kind kind; | |
5060 | }; | |
b99bd4ef | 5061 | |
c19d1205 ZW |
5062 | /* Third argument to parse_shift. */ |
5063 | enum parse_shift_mode | |
5064 | { | |
5065 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
5066 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
5067 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
5068 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
5069 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
5070 | }; | |
b99bd4ef | 5071 | |
c19d1205 ZW |
5072 | /* Parse a <shift> specifier on an ARM data processing instruction. |
5073 | This has three forms: | |
b99bd4ef | 5074 | |
c19d1205 ZW |
5075 | (LSL|LSR|ASL|ASR|ROR) Rs |
5076 | (LSL|LSR|ASL|ASR|ROR) #imm | |
5077 | RRX | |
b99bd4ef | 5078 | |
c19d1205 ZW |
5079 | Note that ASL is assimilated to LSL in the instruction encoding, and |
5080 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 5081 | |
c19d1205 ZW |
5082 | static int |
5083 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 5084 | { |
c19d1205 ZW |
5085 | const struct asm_shift_name *shift_name; |
5086 | enum shift_kind shift; | |
5087 | char *s = *str; | |
5088 | char *p = s; | |
5089 | int reg; | |
b99bd4ef | 5090 | |
c19d1205 ZW |
5091 | for (p = *str; ISALPHA (*p); p++) |
5092 | ; | |
b99bd4ef | 5093 | |
c19d1205 | 5094 | if (p == *str) |
b99bd4ef | 5095 | { |
c19d1205 ZW |
5096 | inst.error = _("shift expression expected"); |
5097 | return FAIL; | |
b99bd4ef NC |
5098 | } |
5099 | ||
21d799b5 | 5100 | shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str, |
477330fc | 5101 | p - *str); |
c19d1205 ZW |
5102 | |
5103 | if (shift_name == NULL) | |
b99bd4ef | 5104 | { |
c19d1205 ZW |
5105 | inst.error = _("shift expression expected"); |
5106 | return FAIL; | |
b99bd4ef NC |
5107 | } |
5108 | ||
c19d1205 | 5109 | shift = shift_name->kind; |
b99bd4ef | 5110 | |
c19d1205 ZW |
5111 | switch (mode) |
5112 | { | |
5113 | case NO_SHIFT_RESTRICT: | |
5114 | case SHIFT_IMMEDIATE: break; | |
b99bd4ef | 5115 | |
c19d1205 ZW |
5116 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
5117 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
5118 | { | |
5119 | inst.error = _("'LSL' or 'ASR' required"); | |
5120 | return FAIL; | |
5121 | } | |
5122 | break; | |
b99bd4ef | 5123 | |
c19d1205 ZW |
5124 | case SHIFT_LSL_IMMEDIATE: |
5125 | if (shift != SHIFT_LSL) | |
5126 | { | |
5127 | inst.error = _("'LSL' required"); | |
5128 | return FAIL; | |
5129 | } | |
5130 | break; | |
b99bd4ef | 5131 | |
c19d1205 ZW |
5132 | case SHIFT_ASR_IMMEDIATE: |
5133 | if (shift != SHIFT_ASR) | |
5134 | { | |
5135 | inst.error = _("'ASR' required"); | |
5136 | return FAIL; | |
5137 | } | |
5138 | break; | |
b99bd4ef | 5139 | |
c19d1205 ZW |
5140 | default: abort (); |
5141 | } | |
b99bd4ef | 5142 | |
c19d1205 ZW |
5143 | if (shift != SHIFT_RRX) |
5144 | { | |
5145 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
5146 | skip_whitespace (p); | |
b99bd4ef | 5147 | |
c19d1205 | 5148 | if (mode == NO_SHIFT_RESTRICT |
dcbf9037 | 5149 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
5150 | { |
5151 | inst.operands[i].imm = reg; | |
5152 | inst.operands[i].immisreg = 1; | |
5153 | } | |
5154 | else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
5155 | return FAIL; | |
5156 | } | |
5157 | inst.operands[i].shift_kind = shift; | |
5158 | inst.operands[i].shifted = 1; | |
5159 | *str = p; | |
5160 | return SUCCESS; | |
b99bd4ef NC |
5161 | } |
5162 | ||
c19d1205 | 5163 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 5164 | |
c19d1205 ZW |
5165 | #<immediate> |
5166 | #<immediate>, <rotate> | |
5167 | <Rm> | |
5168 | <Rm>, <shift> | |
b99bd4ef | 5169 | |
c19d1205 ZW |
5170 | where <shift> is defined by parse_shift above, and <rotate> is a |
5171 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 5172 | is deferred to md_apply_fix. */ |
b99bd4ef | 5173 | |
c19d1205 ZW |
5174 | static int |
5175 | parse_shifter_operand (char **str, int i) | |
5176 | { | |
5177 | int value; | |
91d6fa6a | 5178 | expressionS exp; |
b99bd4ef | 5179 | |
dcbf9037 | 5180 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
5181 | { |
5182 | inst.operands[i].reg = value; | |
5183 | inst.operands[i].isreg = 1; | |
b99bd4ef | 5184 | |
c19d1205 ZW |
5185 | /* parse_shift will override this if appropriate */ |
5186 | inst.reloc.exp.X_op = O_constant; | |
5187 | inst.reloc.exp.X_add_number = 0; | |
b99bd4ef | 5188 | |
c19d1205 ZW |
5189 | if (skip_past_comma (str) == FAIL) |
5190 | return SUCCESS; | |
b99bd4ef | 5191 | |
c19d1205 ZW |
5192 | /* Shift operation on register. */ |
5193 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
5194 | } |
5195 | ||
c19d1205 ZW |
5196 | if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) |
5197 | return FAIL; | |
b99bd4ef | 5198 | |
c19d1205 | 5199 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 5200 | { |
c19d1205 | 5201 | /* #x, y -- ie explicit rotation by Y. */ |
91d6fa6a | 5202 | if (my_get_expression (&exp, str, GE_NO_PREFIX)) |
c19d1205 | 5203 | return FAIL; |
b99bd4ef | 5204 | |
91d6fa6a | 5205 | if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant) |
c19d1205 ZW |
5206 | { |
5207 | inst.error = _("constant expression expected"); | |
5208 | return FAIL; | |
5209 | } | |
b99bd4ef | 5210 | |
91d6fa6a | 5211 | value = exp.X_add_number; |
c19d1205 ZW |
5212 | if (value < 0 || value > 30 || value % 2 != 0) |
5213 | { | |
5214 | inst.error = _("invalid rotation"); | |
5215 | return FAIL; | |
5216 | } | |
5217 | if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) | |
5218 | { | |
5219 | inst.error = _("invalid constant"); | |
5220 | return FAIL; | |
5221 | } | |
09d92015 | 5222 | |
a415b1cd JB |
5223 | /* Encode as specified. */ |
5224 | inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7; | |
5225 | return SUCCESS; | |
09d92015 MM |
5226 | } |
5227 | ||
c19d1205 ZW |
5228 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; |
5229 | inst.reloc.pc_rel = 0; | |
5230 | return SUCCESS; | |
09d92015 MM |
5231 | } |
5232 | ||
4962c51a MS |
5233 | /* Group relocation information. Each entry in the table contains the |
5234 | textual name of the relocation as may appear in assembler source | |
5235 | and must end with a colon. | |
5236 | Along with this textual name are the relocation codes to be used if | |
5237 | the corresponding instruction is an ALU instruction (ADD or SUB only), | |
5238 | an LDR, an LDRS, or an LDC. */ | |
5239 | ||
5240 | struct group_reloc_table_entry | |
5241 | { | |
5242 | const char *name; | |
5243 | int alu_code; | |
5244 | int ldr_code; | |
5245 | int ldrs_code; | |
5246 | int ldc_code; | |
5247 | }; | |
5248 | ||
5249 | typedef enum | |
5250 | { | |
5251 | /* Varieties of non-ALU group relocation. */ | |
5252 | ||
5253 | GROUP_LDR, | |
5254 | GROUP_LDRS, | |
5255 | GROUP_LDC | |
5256 | } group_reloc_type; | |
5257 | ||
5258 | static struct group_reloc_table_entry group_reloc_table[] = | |
5259 | { /* Program counter relative: */ | |
5260 | { "pc_g0_nc", | |
5261 | BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ | |
5262 | 0, /* LDR */ | |
5263 | 0, /* LDRS */ | |
5264 | 0 }, /* LDC */ | |
5265 | { "pc_g0", | |
5266 | BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ | |
5267 | BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ | |
5268 | BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ | |
5269 | BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ | |
5270 | { "pc_g1_nc", | |
5271 | BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ | |
5272 | 0, /* LDR */ | |
5273 | 0, /* LDRS */ | |
5274 | 0 }, /* LDC */ | |
5275 | { "pc_g1", | |
5276 | BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ | |
5277 | BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ | |
5278 | BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ | |
5279 | BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ | |
5280 | { "pc_g2", | |
5281 | BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ | |
5282 | BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ | |
5283 | BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ | |
5284 | BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ | |
5285 | /* Section base relative */ | |
5286 | { "sb_g0_nc", | |
5287 | BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ | |
5288 | 0, /* LDR */ | |
5289 | 0, /* LDRS */ | |
5290 | 0 }, /* LDC */ | |
5291 | { "sb_g0", | |
5292 | BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ | |
5293 | BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ | |
5294 | BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ | |
5295 | BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ | |
5296 | { "sb_g1_nc", | |
5297 | BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ | |
5298 | 0, /* LDR */ | |
5299 | 0, /* LDRS */ | |
5300 | 0 }, /* LDC */ | |
5301 | { "sb_g1", | |
5302 | BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ | |
5303 | BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ | |
5304 | BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ | |
5305 | BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ | |
5306 | { "sb_g2", | |
5307 | BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ | |
5308 | BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ | |
5309 | BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ | |
5310 | BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ | |
5311 | ||
5312 | /* Given the address of a pointer pointing to the textual name of a group | |
5313 | relocation as may appear in assembler source, attempt to find its details | |
5314 | in group_reloc_table. The pointer will be updated to the character after | |
5315 | the trailing colon. On failure, FAIL will be returned; SUCCESS | |
5316 | otherwise. On success, *entry will be updated to point at the relevant | |
5317 | group_reloc_table entry. */ | |
5318 | ||
5319 | static int | |
5320 | find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) | |
5321 | { | |
5322 | unsigned int i; | |
5323 | for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) | |
5324 | { | |
5325 | int length = strlen (group_reloc_table[i].name); | |
5326 | ||
5f4273c7 NC |
5327 | if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 |
5328 | && (*str)[length] == ':') | |
477330fc RM |
5329 | { |
5330 | *out = &group_reloc_table[i]; | |
5331 | *str += (length + 1); | |
5332 | return SUCCESS; | |
5333 | } | |
4962c51a MS |
5334 | } |
5335 | ||
5336 | return FAIL; | |
5337 | } | |
5338 | ||
5339 | /* Parse a <shifter_operand> for an ARM data processing instruction | |
5340 | (as for parse_shifter_operand) where group relocations are allowed: | |
5341 | ||
5342 | #<immediate> | |
5343 | #<immediate>, <rotate> | |
5344 | #:<group_reloc>:<expression> | |
5345 | <Rm> | |
5346 | <Rm>, <shift> | |
5347 | ||
5348 | where <group_reloc> is one of the strings defined in group_reloc_table. | |
5349 | The hashes are optional. | |
5350 | ||
5351 | Everything else is as for parse_shifter_operand. */ | |
5352 | ||
5353 | static parse_operand_result | |
5354 | parse_shifter_operand_group_reloc (char **str, int i) | |
5355 | { | |
5356 | /* Determine if we have the sequence of characters #: or just : | |
5357 | coming next. If we do, then we check for a group relocation. | |
5358 | If we don't, punt the whole lot to parse_shifter_operand. */ | |
5359 | ||
5360 | if (((*str)[0] == '#' && (*str)[1] == ':') | |
5361 | || (*str)[0] == ':') | |
5362 | { | |
5363 | struct group_reloc_table_entry *entry; | |
5364 | ||
5365 | if ((*str)[0] == '#') | |
477330fc | 5366 | (*str) += 2; |
4962c51a | 5367 | else |
477330fc | 5368 | (*str)++; |
4962c51a MS |
5369 | |
5370 | /* Try to parse a group relocation. Anything else is an error. */ | |
5371 | if (find_group_reloc_table_entry (str, &entry) == FAIL) | |
477330fc RM |
5372 | { |
5373 | inst.error = _("unknown group relocation"); | |
5374 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5375 | } | |
4962c51a MS |
5376 | |
5377 | /* We now have the group relocation table entry corresponding to | |
477330fc | 5378 | the name in the assembler source. Next, we parse the expression. */ |
4962c51a | 5379 | if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) |
477330fc | 5380 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; |
4962c51a MS |
5381 | |
5382 | /* Record the relocation type (always the ALU variant here). */ | |
21d799b5 | 5383 | inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code; |
9c2799c2 | 5384 | gas_assert (inst.reloc.type != 0); |
4962c51a MS |
5385 | |
5386 | return PARSE_OPERAND_SUCCESS; | |
5387 | } | |
5388 | else | |
5389 | return parse_shifter_operand (str, i) == SUCCESS | |
477330fc | 5390 | ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; |
4962c51a MS |
5391 | |
5392 | /* Never reached. */ | |
5393 | } | |
5394 | ||
8e560766 MGD |
5395 | /* Parse a Neon alignment expression. Information is written to |
5396 | inst.operands[i]. We assume the initial ':' has been skipped. | |
fa94de6b | 5397 | |
8e560766 MGD |
5398 | align .imm = align << 8, .immisalign=1, .preind=0 */ |
5399 | static parse_operand_result | |
5400 | parse_neon_alignment (char **str, int i) | |
5401 | { | |
5402 | char *p = *str; | |
5403 | expressionS exp; | |
5404 | ||
5405 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
5406 | ||
5407 | if (exp.X_op != O_constant) | |
5408 | { | |
5409 | inst.error = _("alignment must be constant"); | |
5410 | return PARSE_OPERAND_FAIL; | |
5411 | } | |
5412 | ||
5413 | inst.operands[i].imm = exp.X_add_number << 8; | |
5414 | inst.operands[i].immisalign = 1; | |
5415 | /* Alignments are not pre-indexes. */ | |
5416 | inst.operands[i].preind = 0; | |
5417 | ||
5418 | *str = p; | |
5419 | return PARSE_OPERAND_SUCCESS; | |
5420 | } | |
5421 | ||
c19d1205 ZW |
5422 | /* Parse all forms of an ARM address expression. Information is written |
5423 | to inst.operands[i] and/or inst.reloc. | |
09d92015 | 5424 | |
c19d1205 | 5425 | Preindexed addressing (.preind=1): |
09d92015 | 5426 | |
c19d1205 ZW |
5427 | [Rn, #offset] .reg=Rn .reloc.exp=offset |
5428 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5429 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5430 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5431 | |
c19d1205 | 5432 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 5433 | |
c19d1205 | 5434 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 5435 | |
c19d1205 ZW |
5436 | [Rn], #offset .reg=Rn .reloc.exp=offset |
5437 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5438 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5439 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5440 | |
c19d1205 | 5441 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 5442 | |
c19d1205 | 5443 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 5444 | |
c19d1205 | 5445 | Other: |
09d92015 | 5446 | |
c19d1205 ZW |
5447 | [Rn]{!} shorthand for [Rn,#0]{!} |
5448 | =immediate .isreg=0 .reloc.exp=immediate | |
5449 | label .reg=PC .reloc.pc_rel=1 .reloc.exp=label | |
09d92015 | 5450 | |
c19d1205 ZW |
5451 | It is the caller's responsibility to check for addressing modes not |
5452 | supported by the instruction, and to set inst.reloc.type. */ | |
5453 | ||
4962c51a MS |
5454 | static parse_operand_result |
5455 | parse_address_main (char **str, int i, int group_relocations, | |
477330fc | 5456 | group_reloc_type group_type) |
09d92015 | 5457 | { |
c19d1205 ZW |
5458 | char *p = *str; |
5459 | int reg; | |
09d92015 | 5460 | |
c19d1205 | 5461 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 5462 | { |
c19d1205 ZW |
5463 | if (skip_past_char (&p, '=') == FAIL) |
5464 | { | |
974da60d | 5465 | /* Bare address - translate to PC-relative offset. */ |
c19d1205 ZW |
5466 | inst.reloc.pc_rel = 1; |
5467 | inst.operands[i].reg = REG_PC; | |
5468 | inst.operands[i].isreg = 1; | |
5469 | inst.operands[i].preind = 1; | |
09d92015 | 5470 | |
8335d6aa JW |
5471 | if (my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX_BIG)) |
5472 | return PARSE_OPERAND_FAIL; | |
5473 | } | |
5474 | else if (parse_big_immediate (&p, i, &inst.reloc.exp, | |
5475 | /*allow_symbol_p=*/TRUE)) | |
4962c51a | 5476 | return PARSE_OPERAND_FAIL; |
09d92015 | 5477 | |
c19d1205 | 5478 | *str = p; |
4962c51a | 5479 | return PARSE_OPERAND_SUCCESS; |
09d92015 MM |
5480 | } |
5481 | ||
8ab8155f NC |
5482 | /* PR gas/14887: Allow for whitespace after the opening bracket. */ |
5483 | skip_whitespace (p); | |
5484 | ||
dcbf9037 | 5485 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
09d92015 | 5486 | { |
c19d1205 | 5487 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
4962c51a | 5488 | return PARSE_OPERAND_FAIL; |
09d92015 | 5489 | } |
c19d1205 ZW |
5490 | inst.operands[i].reg = reg; |
5491 | inst.operands[i].isreg = 1; | |
09d92015 | 5492 | |
c19d1205 | 5493 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5494 | { |
c19d1205 | 5495 | inst.operands[i].preind = 1; |
09d92015 | 5496 | |
c19d1205 ZW |
5497 | if (*p == '+') p++; |
5498 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
5499 | ||
dcbf9037 | 5500 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
09d92015 | 5501 | { |
c19d1205 ZW |
5502 | inst.operands[i].imm = reg; |
5503 | inst.operands[i].immisreg = 1; | |
5504 | ||
5505 | if (skip_past_comma (&p) == SUCCESS) | |
5506 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5507 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5508 | } |
5287ad62 | 5509 | else if (skip_past_char (&p, ':') == SUCCESS) |
8e560766 MGD |
5510 | { |
5511 | /* FIXME: '@' should be used here, but it's filtered out by generic | |
5512 | code before we get to see it here. This may be subject to | |
5513 | change. */ | |
5514 | parse_operand_result result = parse_neon_alignment (&p, i); | |
fa94de6b | 5515 | |
8e560766 MGD |
5516 | if (result != PARSE_OPERAND_SUCCESS) |
5517 | return result; | |
5518 | } | |
c19d1205 ZW |
5519 | else |
5520 | { | |
5521 | if (inst.operands[i].negative) | |
5522 | { | |
5523 | inst.operands[i].negative = 0; | |
5524 | p--; | |
5525 | } | |
4962c51a | 5526 | |
5f4273c7 NC |
5527 | if (group_relocations |
5528 | && ((*p == '#' && *(p + 1) == ':') || *p == ':')) | |
4962c51a MS |
5529 | { |
5530 | struct group_reloc_table_entry *entry; | |
5531 | ||
477330fc RM |
5532 | /* Skip over the #: or : sequence. */ |
5533 | if (*p == '#') | |
5534 | p += 2; | |
5535 | else | |
5536 | p++; | |
4962c51a MS |
5537 | |
5538 | /* Try to parse a group relocation. Anything else is an | |
477330fc | 5539 | error. */ |
4962c51a MS |
5540 | if (find_group_reloc_table_entry (&p, &entry) == FAIL) |
5541 | { | |
5542 | inst.error = _("unknown group relocation"); | |
5543 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5544 | } | |
5545 | ||
5546 | /* We now have the group relocation table entry corresponding to | |
5547 | the name in the assembler source. Next, we parse the | |
477330fc | 5548 | expression. */ |
4962c51a MS |
5549 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) |
5550 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5551 | ||
5552 | /* Record the relocation type. */ | |
477330fc RM |
5553 | switch (group_type) |
5554 | { | |
5555 | case GROUP_LDR: | |
5556 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code; | |
5557 | break; | |
4962c51a | 5558 | |
477330fc RM |
5559 | case GROUP_LDRS: |
5560 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code; | |
5561 | break; | |
4962c51a | 5562 | |
477330fc RM |
5563 | case GROUP_LDC: |
5564 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code; | |
5565 | break; | |
4962c51a | 5566 | |
477330fc RM |
5567 | default: |
5568 | gas_assert (0); | |
5569 | } | |
4962c51a | 5570 | |
477330fc | 5571 | if (inst.reloc.type == 0) |
4962c51a MS |
5572 | { |
5573 | inst.error = _("this group relocation is not allowed on this instruction"); | |
5574 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5575 | } | |
477330fc RM |
5576 | } |
5577 | else | |
26d97720 NS |
5578 | { |
5579 | char *q = p; | |
5580 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
5581 | return PARSE_OPERAND_FAIL; | |
5582 | /* If the offset is 0, find out if it's a +0 or -0. */ | |
5583 | if (inst.reloc.exp.X_op == O_constant | |
5584 | && inst.reloc.exp.X_add_number == 0) | |
5585 | { | |
5586 | skip_whitespace (q); | |
5587 | if (*q == '#') | |
5588 | { | |
5589 | q++; | |
5590 | skip_whitespace (q); | |
5591 | } | |
5592 | if (*q == '-') | |
5593 | inst.operands[i].negative = 1; | |
5594 | } | |
5595 | } | |
09d92015 MM |
5596 | } |
5597 | } | |
8e560766 MGD |
5598 | else if (skip_past_char (&p, ':') == SUCCESS) |
5599 | { | |
5600 | /* FIXME: '@' should be used here, but it's filtered out by generic code | |
5601 | before we get to see it here. This may be subject to change. */ | |
5602 | parse_operand_result result = parse_neon_alignment (&p, i); | |
fa94de6b | 5603 | |
8e560766 MGD |
5604 | if (result != PARSE_OPERAND_SUCCESS) |
5605 | return result; | |
5606 | } | |
09d92015 | 5607 | |
c19d1205 | 5608 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 5609 | { |
c19d1205 | 5610 | inst.error = _("']' expected"); |
4962c51a | 5611 | return PARSE_OPERAND_FAIL; |
09d92015 MM |
5612 | } |
5613 | ||
c19d1205 ZW |
5614 | if (skip_past_char (&p, '!') == SUCCESS) |
5615 | inst.operands[i].writeback = 1; | |
09d92015 | 5616 | |
c19d1205 | 5617 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5618 | { |
c19d1205 ZW |
5619 | if (skip_past_char (&p, '{') == SUCCESS) |
5620 | { | |
5621 | /* [Rn], {expr} - unindexed, with option */ | |
5622 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 5623 | 0, 255, TRUE) == FAIL) |
4962c51a | 5624 | return PARSE_OPERAND_FAIL; |
09d92015 | 5625 | |
c19d1205 ZW |
5626 | if (skip_past_char (&p, '}') == FAIL) |
5627 | { | |
5628 | inst.error = _("'}' expected at end of 'option' field"); | |
4962c51a | 5629 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5630 | } |
5631 | if (inst.operands[i].preind) | |
5632 | { | |
5633 | inst.error = _("cannot combine index with option"); | |
4962c51a | 5634 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5635 | } |
5636 | *str = p; | |
4962c51a | 5637 | return PARSE_OPERAND_SUCCESS; |
09d92015 | 5638 | } |
c19d1205 ZW |
5639 | else |
5640 | { | |
5641 | inst.operands[i].postind = 1; | |
5642 | inst.operands[i].writeback = 1; | |
09d92015 | 5643 | |
c19d1205 ZW |
5644 | if (inst.operands[i].preind) |
5645 | { | |
5646 | inst.error = _("cannot combine pre- and post-indexing"); | |
4962c51a | 5647 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5648 | } |
09d92015 | 5649 | |
c19d1205 ZW |
5650 | if (*p == '+') p++; |
5651 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 5652 | |
dcbf9037 | 5653 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 | 5654 | { |
477330fc RM |
5655 | /* We might be using the immediate for alignment already. If we |
5656 | are, OR the register number into the low-order bits. */ | |
5657 | if (inst.operands[i].immisalign) | |
5658 | inst.operands[i].imm |= reg; | |
5659 | else | |
5660 | inst.operands[i].imm = reg; | |
c19d1205 | 5661 | inst.operands[i].immisreg = 1; |
a737bd4d | 5662 | |
c19d1205 ZW |
5663 | if (skip_past_comma (&p) == SUCCESS) |
5664 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5665 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5666 | } |
5667 | else | |
5668 | { | |
26d97720 | 5669 | char *q = p; |
c19d1205 ZW |
5670 | if (inst.operands[i].negative) |
5671 | { | |
5672 | inst.operands[i].negative = 0; | |
5673 | p--; | |
5674 | } | |
5675 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4962c51a | 5676 | return PARSE_OPERAND_FAIL; |
26d97720 NS |
5677 | /* If the offset is 0, find out if it's a +0 or -0. */ |
5678 | if (inst.reloc.exp.X_op == O_constant | |
5679 | && inst.reloc.exp.X_add_number == 0) | |
5680 | { | |
5681 | skip_whitespace (q); | |
5682 | if (*q == '#') | |
5683 | { | |
5684 | q++; | |
5685 | skip_whitespace (q); | |
5686 | } | |
5687 | if (*q == '-') | |
5688 | inst.operands[i].negative = 1; | |
5689 | } | |
c19d1205 ZW |
5690 | } |
5691 | } | |
a737bd4d NC |
5692 | } |
5693 | ||
c19d1205 ZW |
5694 | /* If at this point neither .preind nor .postind is set, we have a |
5695 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
5696 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
5697 | { | |
5698 | inst.operands[i].preind = 1; | |
5699 | inst.reloc.exp.X_op = O_constant; | |
5700 | inst.reloc.exp.X_add_number = 0; | |
5701 | } | |
5702 | *str = p; | |
4962c51a MS |
5703 | return PARSE_OPERAND_SUCCESS; |
5704 | } | |
5705 | ||
5706 | static int | |
5707 | parse_address (char **str, int i) | |
5708 | { | |
21d799b5 | 5709 | return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS |
477330fc | 5710 | ? SUCCESS : FAIL; |
4962c51a MS |
5711 | } |
5712 | ||
5713 | static parse_operand_result | |
5714 | parse_address_group_reloc (char **str, int i, group_reloc_type type) | |
5715 | { | |
5716 | return parse_address_main (str, i, 1, type); | |
a737bd4d NC |
5717 | } |
5718 | ||
b6895b4f PB |
5719 | /* Parse an operand for a MOVW or MOVT instruction. */ |
5720 | static int | |
5721 | parse_half (char **str) | |
5722 | { | |
5723 | char * p; | |
5f4273c7 | 5724 | |
b6895b4f PB |
5725 | p = *str; |
5726 | skip_past_char (&p, '#'); | |
5f4273c7 | 5727 | if (strncasecmp (p, ":lower16:", 9) == 0) |
b6895b4f PB |
5728 | inst.reloc.type = BFD_RELOC_ARM_MOVW; |
5729 | else if (strncasecmp (p, ":upper16:", 9) == 0) | |
5730 | inst.reloc.type = BFD_RELOC_ARM_MOVT; | |
5731 | ||
5732 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
5733 | { | |
5734 | p += 9; | |
5f4273c7 | 5735 | skip_whitespace (p); |
b6895b4f PB |
5736 | } |
5737 | ||
5738 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5739 | return FAIL; | |
5740 | ||
5741 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
5742 | { | |
5743 | if (inst.reloc.exp.X_op != O_constant) | |
5744 | { | |
5745 | inst.error = _("constant expression expected"); | |
5746 | return FAIL; | |
5747 | } | |
5748 | if (inst.reloc.exp.X_add_number < 0 | |
5749 | || inst.reloc.exp.X_add_number > 0xffff) | |
5750 | { | |
5751 | inst.error = _("immediate value out of range"); | |
5752 | return FAIL; | |
5753 | } | |
5754 | } | |
5755 | *str = p; | |
5756 | return SUCCESS; | |
5757 | } | |
5758 | ||
c19d1205 | 5759 | /* Miscellaneous. */ |
a737bd4d | 5760 | |
c19d1205 ZW |
5761 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
5762 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
5763 | static int | |
d2cd1205 | 5764 | parse_psr (char **str, bfd_boolean lhs) |
09d92015 | 5765 | { |
c19d1205 ZW |
5766 | char *p; |
5767 | unsigned long psr_field; | |
62b3e311 PB |
5768 | const struct asm_psr *psr; |
5769 | char *start; | |
d2cd1205 | 5770 | bfd_boolean is_apsr = FALSE; |
ac7f631b | 5771 | bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m); |
09d92015 | 5772 | |
a4482bb6 NC |
5773 | /* PR gas/12698: If the user has specified -march=all then m_profile will |
5774 | be TRUE, but we want to ignore it in this case as we are building for any | |
5775 | CPU type, including non-m variants. */ | |
5776 | if (selected_cpu.core == arm_arch_any.core) | |
5777 | m_profile = FALSE; | |
5778 | ||
c19d1205 ZW |
5779 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
5780 | feature for ease of use and backwards compatibility. */ | |
5781 | p = *str; | |
62b3e311 | 5782 | if (strncasecmp (p, "SPSR", 4) == 0) |
d2cd1205 JB |
5783 | { |
5784 | if (m_profile) | |
5785 | goto unsupported_psr; | |
fa94de6b | 5786 | |
d2cd1205 JB |
5787 | psr_field = SPSR_BIT; |
5788 | } | |
5789 | else if (strncasecmp (p, "CPSR", 4) == 0) | |
5790 | { | |
5791 | if (m_profile) | |
5792 | goto unsupported_psr; | |
5793 | ||
5794 | psr_field = 0; | |
5795 | } | |
5796 | else if (strncasecmp (p, "APSR", 4) == 0) | |
5797 | { | |
5798 | /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A | |
5799 | and ARMv7-R architecture CPUs. */ | |
5800 | is_apsr = TRUE; | |
5801 | psr_field = 0; | |
5802 | } | |
5803 | else if (m_profile) | |
62b3e311 PB |
5804 | { |
5805 | start = p; | |
5806 | do | |
5807 | p++; | |
5808 | while (ISALNUM (*p) || *p == '_'); | |
5809 | ||
d2cd1205 JB |
5810 | if (strncasecmp (start, "iapsr", 5) == 0 |
5811 | || strncasecmp (start, "eapsr", 5) == 0 | |
5812 | || strncasecmp (start, "xpsr", 4) == 0 | |
5813 | || strncasecmp (start, "psr", 3) == 0) | |
5814 | p = start + strcspn (start, "rR") + 1; | |
5815 | ||
21d799b5 | 5816 | psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start, |
477330fc | 5817 | p - start); |
d2cd1205 | 5818 | |
62b3e311 PB |
5819 | if (!psr) |
5820 | return FAIL; | |
09d92015 | 5821 | |
d2cd1205 JB |
5822 | /* If APSR is being written, a bitfield may be specified. Note that |
5823 | APSR itself is handled above. */ | |
5824 | if (psr->field <= 3) | |
5825 | { | |
5826 | psr_field = psr->field; | |
5827 | is_apsr = TRUE; | |
5828 | goto check_suffix; | |
5829 | } | |
5830 | ||
62b3e311 | 5831 | *str = p; |
d2cd1205 JB |
5832 | /* M-profile MSR instructions have the mask field set to "10", except |
5833 | *PSR variants which modify APSR, which may use a different mask (and | |
5834 | have been handled already). Do that by setting the PSR_f field | |
5835 | here. */ | |
5836 | return psr->field | (lhs ? PSR_f : 0); | |
62b3e311 | 5837 | } |
d2cd1205 JB |
5838 | else |
5839 | goto unsupported_psr; | |
09d92015 | 5840 | |
62b3e311 | 5841 | p += 4; |
d2cd1205 | 5842 | check_suffix: |
c19d1205 ZW |
5843 | if (*p == '_') |
5844 | { | |
5845 | /* A suffix follows. */ | |
c19d1205 ZW |
5846 | p++; |
5847 | start = p; | |
a737bd4d | 5848 | |
c19d1205 ZW |
5849 | do |
5850 | p++; | |
5851 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 5852 | |
d2cd1205 JB |
5853 | if (is_apsr) |
5854 | { | |
5855 | /* APSR uses a notation for bits, rather than fields. */ | |
5856 | unsigned int nzcvq_bits = 0; | |
5857 | unsigned int g_bit = 0; | |
5858 | char *bit; | |
fa94de6b | 5859 | |
d2cd1205 JB |
5860 | for (bit = start; bit != p; bit++) |
5861 | { | |
5862 | switch (TOLOWER (*bit)) | |
477330fc | 5863 | { |
d2cd1205 JB |
5864 | case 'n': |
5865 | nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01; | |
5866 | break; | |
5867 | ||
5868 | case 'z': | |
5869 | nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02; | |
5870 | break; | |
5871 | ||
5872 | case 'c': | |
5873 | nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04; | |
5874 | break; | |
5875 | ||
5876 | case 'v': | |
5877 | nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08; | |
5878 | break; | |
fa94de6b | 5879 | |
d2cd1205 JB |
5880 | case 'q': |
5881 | nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10; | |
5882 | break; | |
fa94de6b | 5883 | |
d2cd1205 JB |
5884 | case 'g': |
5885 | g_bit |= (g_bit & 0x1) ? 0x2 : 0x1; | |
5886 | break; | |
fa94de6b | 5887 | |
d2cd1205 JB |
5888 | default: |
5889 | inst.error = _("unexpected bit specified after APSR"); | |
5890 | return FAIL; | |
5891 | } | |
5892 | } | |
fa94de6b | 5893 | |
d2cd1205 JB |
5894 | if (nzcvq_bits == 0x1f) |
5895 | psr_field |= PSR_f; | |
fa94de6b | 5896 | |
d2cd1205 JB |
5897 | if (g_bit == 0x1) |
5898 | { | |
5899 | if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)) | |
477330fc | 5900 | { |
d2cd1205 JB |
5901 | inst.error = _("selected processor does not " |
5902 | "support DSP extension"); | |
5903 | return FAIL; | |
5904 | } | |
5905 | ||
5906 | psr_field |= PSR_s; | |
5907 | } | |
fa94de6b | 5908 | |
d2cd1205 JB |
5909 | if ((nzcvq_bits & 0x20) != 0 |
5910 | || (nzcvq_bits != 0x1f && nzcvq_bits != 0) | |
5911 | || (g_bit & 0x2) != 0) | |
5912 | { | |
5913 | inst.error = _("bad bitmask specified after APSR"); | |
5914 | return FAIL; | |
5915 | } | |
5916 | } | |
5917 | else | |
477330fc | 5918 | { |
d2cd1205 | 5919 | psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start, |
477330fc | 5920 | p - start); |
d2cd1205 | 5921 | if (!psr) |
477330fc | 5922 | goto error; |
a737bd4d | 5923 | |
d2cd1205 JB |
5924 | psr_field |= psr->field; |
5925 | } | |
a737bd4d | 5926 | } |
c19d1205 | 5927 | else |
a737bd4d | 5928 | { |
c19d1205 ZW |
5929 | if (ISALNUM (*p)) |
5930 | goto error; /* Garbage after "[CS]PSR". */ | |
5931 | ||
d2cd1205 | 5932 | /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This |
477330fc | 5933 | is deprecated, but allow it anyway. */ |
d2cd1205 JB |
5934 | if (is_apsr && lhs) |
5935 | { | |
5936 | psr_field |= PSR_f; | |
5937 | as_tsktsk (_("writing to APSR without specifying a bitmask is " | |
5938 | "deprecated")); | |
5939 | } | |
5940 | else if (!m_profile) | |
5941 | /* These bits are never right for M-profile devices: don't set them | |
5942 | (only code paths which read/write APSR reach here). */ | |
5943 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 5944 | } |
c19d1205 ZW |
5945 | *str = p; |
5946 | return psr_field; | |
a737bd4d | 5947 | |
d2cd1205 JB |
5948 | unsupported_psr: |
5949 | inst.error = _("selected processor does not support requested special " | |
5950 | "purpose register"); | |
5951 | return FAIL; | |
5952 | ||
c19d1205 ZW |
5953 | error: |
5954 | inst.error = _("flag for {c}psr instruction expected"); | |
5955 | return FAIL; | |
a737bd4d NC |
5956 | } |
5957 | ||
c19d1205 ZW |
5958 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
5959 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 5960 | |
c19d1205 ZW |
5961 | static int |
5962 | parse_cps_flags (char **str) | |
a737bd4d | 5963 | { |
c19d1205 ZW |
5964 | int val = 0; |
5965 | int saw_a_flag = 0; | |
5966 | char *s = *str; | |
a737bd4d | 5967 | |
c19d1205 ZW |
5968 | for (;;) |
5969 | switch (*s++) | |
5970 | { | |
5971 | case '\0': case ',': | |
5972 | goto done; | |
a737bd4d | 5973 | |
c19d1205 ZW |
5974 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
5975 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
5976 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 5977 | |
c19d1205 ZW |
5978 | default: |
5979 | inst.error = _("unrecognized CPS flag"); | |
5980 | return FAIL; | |
5981 | } | |
a737bd4d | 5982 | |
c19d1205 ZW |
5983 | done: |
5984 | if (saw_a_flag == 0) | |
a737bd4d | 5985 | { |
c19d1205 ZW |
5986 | inst.error = _("missing CPS flags"); |
5987 | return FAIL; | |
a737bd4d | 5988 | } |
a737bd4d | 5989 | |
c19d1205 ZW |
5990 | *str = s - 1; |
5991 | return val; | |
a737bd4d NC |
5992 | } |
5993 | ||
c19d1205 ZW |
5994 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
5995 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
5996 | |
5997 | static int | |
c19d1205 | 5998 | parse_endian_specifier (char **str) |
a737bd4d | 5999 | { |
c19d1205 ZW |
6000 | int little_endian; |
6001 | char *s = *str; | |
a737bd4d | 6002 | |
c19d1205 ZW |
6003 | if (strncasecmp (s, "BE", 2)) |
6004 | little_endian = 0; | |
6005 | else if (strncasecmp (s, "LE", 2)) | |
6006 | little_endian = 1; | |
6007 | else | |
a737bd4d | 6008 | { |
c19d1205 | 6009 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
6010 | return FAIL; |
6011 | } | |
6012 | ||
c19d1205 | 6013 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 6014 | { |
c19d1205 | 6015 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
6016 | return FAIL; |
6017 | } | |
6018 | ||
c19d1205 ZW |
6019 | *str = s + 2; |
6020 | return little_endian; | |
6021 | } | |
a737bd4d | 6022 | |
c19d1205 ZW |
6023 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
6024 | value suitable for poking into the rotate field of an sxt or sxta | |
6025 | instruction, or FAIL on error. */ | |
6026 | ||
6027 | static int | |
6028 | parse_ror (char **str) | |
6029 | { | |
6030 | int rot; | |
6031 | char *s = *str; | |
6032 | ||
6033 | if (strncasecmp (s, "ROR", 3) == 0) | |
6034 | s += 3; | |
6035 | else | |
a737bd4d | 6036 | { |
c19d1205 | 6037 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
6038 | return FAIL; |
6039 | } | |
c19d1205 ZW |
6040 | |
6041 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
6042 | return FAIL; | |
6043 | ||
6044 | switch (rot) | |
a737bd4d | 6045 | { |
c19d1205 ZW |
6046 | case 0: *str = s; return 0x0; |
6047 | case 8: *str = s; return 0x1; | |
6048 | case 16: *str = s; return 0x2; | |
6049 | case 24: *str = s; return 0x3; | |
6050 | ||
6051 | default: | |
6052 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
6053 | return FAIL; |
6054 | } | |
c19d1205 | 6055 | } |
a737bd4d | 6056 | |
c19d1205 ZW |
6057 | /* Parse a conditional code (from conds[] below). The value returned is in the |
6058 | range 0 .. 14, or FAIL. */ | |
6059 | static int | |
6060 | parse_cond (char **str) | |
6061 | { | |
c462b453 | 6062 | char *q; |
c19d1205 | 6063 | const struct asm_cond *c; |
c462b453 PB |
6064 | int n; |
6065 | /* Condition codes are always 2 characters, so matching up to | |
6066 | 3 characters is sufficient. */ | |
6067 | char cond[3]; | |
a737bd4d | 6068 | |
c462b453 PB |
6069 | q = *str; |
6070 | n = 0; | |
6071 | while (ISALPHA (*q) && n < 3) | |
6072 | { | |
e07e6e58 | 6073 | cond[n] = TOLOWER (*q); |
c462b453 PB |
6074 | q++; |
6075 | n++; | |
6076 | } | |
a737bd4d | 6077 | |
21d799b5 | 6078 | c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n); |
c19d1205 | 6079 | if (!c) |
a737bd4d | 6080 | { |
c19d1205 | 6081 | inst.error = _("condition required"); |
a737bd4d NC |
6082 | return FAIL; |
6083 | } | |
6084 | ||
c19d1205 ZW |
6085 | *str = q; |
6086 | return c->value; | |
6087 | } | |
6088 | ||
e797f7e0 MGD |
6089 | /* If the given feature available in the selected CPU, mark it as used. |
6090 | Returns TRUE iff feature is available. */ | |
6091 | static bfd_boolean | |
6092 | mark_feature_used (const arm_feature_set *feature) | |
6093 | { | |
6094 | /* Ensure the option is valid on the current architecture. */ | |
6095 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature)) | |
6096 | return FALSE; | |
6097 | ||
6098 | /* Add the appropriate architecture feature for the barrier option used. | |
6099 | */ | |
6100 | if (thumb_mode) | |
6101 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature); | |
6102 | else | |
6103 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature); | |
6104 | ||
6105 | return TRUE; | |
6106 | } | |
6107 | ||
62b3e311 PB |
6108 | /* Parse an option for a barrier instruction. Returns the encoding for the |
6109 | option, or FAIL. */ | |
6110 | static int | |
6111 | parse_barrier (char **str) | |
6112 | { | |
6113 | char *p, *q; | |
6114 | const struct asm_barrier_opt *o; | |
6115 | ||
6116 | p = q = *str; | |
6117 | while (ISALPHA (*q)) | |
6118 | q++; | |
6119 | ||
21d799b5 | 6120 | o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p, |
477330fc | 6121 | q - p); |
62b3e311 PB |
6122 | if (!o) |
6123 | return FAIL; | |
6124 | ||
e797f7e0 MGD |
6125 | if (!mark_feature_used (&o->arch)) |
6126 | return FAIL; | |
6127 | ||
62b3e311 PB |
6128 | *str = q; |
6129 | return o->value; | |
6130 | } | |
6131 | ||
92e90b6e PB |
6132 | /* Parse the operands of a table branch instruction. Similar to a memory |
6133 | operand. */ | |
6134 | static int | |
6135 | parse_tb (char **str) | |
6136 | { | |
6137 | char * p = *str; | |
6138 | int reg; | |
6139 | ||
6140 | if (skip_past_char (&p, '[') == FAIL) | |
ab1eb5fe PB |
6141 | { |
6142 | inst.error = _("'[' expected"); | |
6143 | return FAIL; | |
6144 | } | |
92e90b6e | 6145 | |
dcbf9037 | 6146 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
6147 | { |
6148 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
6149 | return FAIL; | |
6150 | } | |
6151 | inst.operands[0].reg = reg; | |
6152 | ||
6153 | if (skip_past_comma (&p) == FAIL) | |
ab1eb5fe PB |
6154 | { |
6155 | inst.error = _("',' expected"); | |
6156 | return FAIL; | |
6157 | } | |
5f4273c7 | 6158 | |
dcbf9037 | 6159 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
6160 | { |
6161 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
6162 | return FAIL; | |
6163 | } | |
6164 | inst.operands[0].imm = reg; | |
6165 | ||
6166 | if (skip_past_comma (&p) == SUCCESS) | |
6167 | { | |
6168 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
6169 | return FAIL; | |
6170 | if (inst.reloc.exp.X_add_number != 1) | |
6171 | { | |
6172 | inst.error = _("invalid shift"); | |
6173 | return FAIL; | |
6174 | } | |
6175 | inst.operands[0].shifted = 1; | |
6176 | } | |
6177 | ||
6178 | if (skip_past_char (&p, ']') == FAIL) | |
6179 | { | |
6180 | inst.error = _("']' expected"); | |
6181 | return FAIL; | |
6182 | } | |
6183 | *str = p; | |
6184 | return SUCCESS; | |
6185 | } | |
6186 | ||
5287ad62 JB |
6187 | /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more |
6188 | information on the types the operands can take and how they are encoded. | |
037e8744 JB |
6189 | Up to four operands may be read; this function handles setting the |
6190 | ".present" field for each read operand itself. | |
5287ad62 JB |
6191 | Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, |
6192 | else returns FAIL. */ | |
6193 | ||
6194 | static int | |
6195 | parse_neon_mov (char **str, int *which_operand) | |
6196 | { | |
6197 | int i = *which_operand, val; | |
6198 | enum arm_reg_type rtype; | |
6199 | char *ptr = *str; | |
dcbf9037 | 6200 | struct neon_type_el optype; |
5f4273c7 | 6201 | |
dcbf9037 | 6202 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
6203 | { |
6204 | /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ | |
6205 | inst.operands[i].reg = val; | |
6206 | inst.operands[i].isscalar = 1; | |
dcbf9037 | 6207 | inst.operands[i].vectype = optype; |
5287ad62 JB |
6208 | inst.operands[i++].present = 1; |
6209 | ||
6210 | if (skip_past_comma (&ptr) == FAIL) | |
477330fc | 6211 | goto wanted_comma; |
5f4273c7 | 6212 | |
dcbf9037 | 6213 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
477330fc | 6214 | goto wanted_arm; |
5f4273c7 | 6215 | |
5287ad62 JB |
6216 | inst.operands[i].reg = val; |
6217 | inst.operands[i].isreg = 1; | |
6218 | inst.operands[i].present = 1; | |
6219 | } | |
037e8744 | 6220 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) |
477330fc | 6221 | != FAIL) |
5287ad62 JB |
6222 | { |
6223 | /* Cases 0, 1, 2, 3, 5 (D only). */ | |
6224 | if (skip_past_comma (&ptr) == FAIL) | |
477330fc | 6225 | goto wanted_comma; |
5f4273c7 | 6226 | |
5287ad62 JB |
6227 | inst.operands[i].reg = val; |
6228 | inst.operands[i].isreg = 1; | |
6229 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
6230 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
6231 | inst.operands[i].isvec = 1; | |
dcbf9037 | 6232 | inst.operands[i].vectype = optype; |
5287ad62 JB |
6233 | inst.operands[i++].present = 1; |
6234 | ||
dcbf9037 | 6235 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
477330fc RM |
6236 | { |
6237 | /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. | |
6238 | Case 13: VMOV <Sd>, <Rm> */ | |
6239 | inst.operands[i].reg = val; | |
6240 | inst.operands[i].isreg = 1; | |
6241 | inst.operands[i].present = 1; | |
6242 | ||
6243 | if (rtype == REG_TYPE_NQ) | |
6244 | { | |
6245 | first_error (_("can't use Neon quad register here")); | |
6246 | return FAIL; | |
6247 | } | |
6248 | else if (rtype != REG_TYPE_VFS) | |
6249 | { | |
6250 | i++; | |
6251 | if (skip_past_comma (&ptr) == FAIL) | |
6252 | goto wanted_comma; | |
6253 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6254 | goto wanted_arm; | |
6255 | inst.operands[i].reg = val; | |
6256 | inst.operands[i].isreg = 1; | |
6257 | inst.operands[i].present = 1; | |
6258 | } | |
6259 | } | |
037e8744 | 6260 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, |
477330fc RM |
6261 | &optype)) != FAIL) |
6262 | { | |
6263 | /* Case 0: VMOV<c><q> <Qd>, <Qm> | |
6264 | Case 1: VMOV<c><q> <Dd>, <Dm> | |
6265 | Case 8: VMOV.F32 <Sd>, <Sm> | |
6266 | Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ | |
6267 | ||
6268 | inst.operands[i].reg = val; | |
6269 | inst.operands[i].isreg = 1; | |
6270 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
6271 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
6272 | inst.operands[i].isvec = 1; | |
6273 | inst.operands[i].vectype = optype; | |
6274 | inst.operands[i].present = 1; | |
6275 | ||
6276 | if (skip_past_comma (&ptr) == SUCCESS) | |
6277 | { | |
6278 | /* Case 15. */ | |
6279 | i++; | |
6280 | ||
6281 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6282 | goto wanted_arm; | |
6283 | ||
6284 | inst.operands[i].reg = val; | |
6285 | inst.operands[i].isreg = 1; | |
6286 | inst.operands[i++].present = 1; | |
6287 | ||
6288 | if (skip_past_comma (&ptr) == FAIL) | |
6289 | goto wanted_comma; | |
6290 | ||
6291 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6292 | goto wanted_arm; | |
6293 | ||
6294 | inst.operands[i].reg = val; | |
6295 | inst.operands[i].isreg = 1; | |
6296 | inst.operands[i].present = 1; | |
6297 | } | |
6298 | } | |
4641781c | 6299 | else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) |
477330fc RM |
6300 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> |
6301 | Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> | |
6302 | Case 10: VMOV.F32 <Sd>, #<imm> | |
6303 | Case 11: VMOV.F64 <Dd>, #<imm> */ | |
6304 | inst.operands[i].immisfloat = 1; | |
8335d6aa JW |
6305 | else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE) |
6306 | == SUCCESS) | |
477330fc RM |
6307 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> |
6308 | Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ | |
6309 | ; | |
5287ad62 | 6310 | else |
477330fc RM |
6311 | { |
6312 | first_error (_("expected <Rm> or <Dm> or <Qm> operand")); | |
6313 | return FAIL; | |
6314 | } | |
5287ad62 | 6315 | } |
dcbf9037 | 6316 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
6317 | { |
6318 | /* Cases 6, 7. */ | |
6319 | inst.operands[i].reg = val; | |
6320 | inst.operands[i].isreg = 1; | |
6321 | inst.operands[i++].present = 1; | |
5f4273c7 | 6322 | |
5287ad62 | 6323 | if (skip_past_comma (&ptr) == FAIL) |
477330fc | 6324 | goto wanted_comma; |
5f4273c7 | 6325 | |
dcbf9037 | 6326 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
477330fc RM |
6327 | { |
6328 | /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ | |
6329 | inst.operands[i].reg = val; | |
6330 | inst.operands[i].isscalar = 1; | |
6331 | inst.operands[i].present = 1; | |
6332 | inst.operands[i].vectype = optype; | |
6333 | } | |
dcbf9037 | 6334 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
477330fc RM |
6335 | { |
6336 | /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ | |
6337 | inst.operands[i].reg = val; | |
6338 | inst.operands[i].isreg = 1; | |
6339 | inst.operands[i++].present = 1; | |
6340 | ||
6341 | if (skip_past_comma (&ptr) == FAIL) | |
6342 | goto wanted_comma; | |
6343 | ||
6344 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) | |
6345 | == FAIL) | |
6346 | { | |
6347 | first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); | |
6348 | return FAIL; | |
6349 | } | |
6350 | ||
6351 | inst.operands[i].reg = val; | |
6352 | inst.operands[i].isreg = 1; | |
6353 | inst.operands[i].isvec = 1; | |
6354 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
6355 | inst.operands[i].vectype = optype; | |
6356 | inst.operands[i].present = 1; | |
6357 | ||
6358 | if (rtype == REG_TYPE_VFS) | |
6359 | { | |
6360 | /* Case 14. */ | |
6361 | i++; | |
6362 | if (skip_past_comma (&ptr) == FAIL) | |
6363 | goto wanted_comma; | |
6364 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, | |
6365 | &optype)) == FAIL) | |
6366 | { | |
6367 | first_error (_(reg_expected_msgs[REG_TYPE_VFS])); | |
6368 | return FAIL; | |
6369 | } | |
6370 | inst.operands[i].reg = val; | |
6371 | inst.operands[i].isreg = 1; | |
6372 | inst.operands[i].isvec = 1; | |
6373 | inst.operands[i].issingle = 1; | |
6374 | inst.operands[i].vectype = optype; | |
6375 | inst.operands[i].present = 1; | |
6376 | } | |
6377 | } | |
037e8744 | 6378 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) |
477330fc RM |
6379 | != FAIL) |
6380 | { | |
6381 | /* Case 13. */ | |
6382 | inst.operands[i].reg = val; | |
6383 | inst.operands[i].isreg = 1; | |
6384 | inst.operands[i].isvec = 1; | |
6385 | inst.operands[i].issingle = 1; | |
6386 | inst.operands[i].vectype = optype; | |
6387 | inst.operands[i].present = 1; | |
6388 | } | |
5287ad62 JB |
6389 | } |
6390 | else | |
6391 | { | |
dcbf9037 | 6392 | first_error (_("parse error")); |
5287ad62 JB |
6393 | return FAIL; |
6394 | } | |
6395 | ||
6396 | /* Successfully parsed the operands. Update args. */ | |
6397 | *which_operand = i; | |
6398 | *str = ptr; | |
6399 | return SUCCESS; | |
6400 | ||
5f4273c7 | 6401 | wanted_comma: |
dcbf9037 | 6402 | first_error (_("expected comma")); |
5287ad62 | 6403 | return FAIL; |
5f4273c7 NC |
6404 | |
6405 | wanted_arm: | |
dcbf9037 | 6406 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
5287ad62 | 6407 | return FAIL; |
5287ad62 JB |
6408 | } |
6409 | ||
5be8be5d DG |
6410 | /* Use this macro when the operand constraints are different |
6411 | for ARM and THUMB (e.g. ldrd). */ | |
6412 | #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \ | |
6413 | ((arm_operand) | ((thumb_operand) << 16)) | |
6414 | ||
c19d1205 ZW |
6415 | /* Matcher codes for parse_operands. */ |
6416 | enum operand_parse_code | |
6417 | { | |
6418 | OP_stop, /* end of line */ | |
6419 | ||
6420 | OP_RR, /* ARM register */ | |
6421 | OP_RRnpc, /* ARM register, not r15 */ | |
5be8be5d | 6422 | OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */ |
c19d1205 | 6423 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ |
fa94de6b | 6424 | OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback, |
55881a11 | 6425 | optional trailing ! */ |
c19d1205 ZW |
6426 | OP_RRw, /* ARM register, not r15, optional trailing ! */ |
6427 | OP_RCP, /* Coprocessor number */ | |
6428 | OP_RCN, /* Coprocessor register */ | |
6429 | OP_RF, /* FPA register */ | |
6430 | OP_RVS, /* VFP single precision register */ | |
5287ad62 JB |
6431 | OP_RVD, /* VFP double precision register (0..15) */ |
6432 | OP_RND, /* Neon double precision register (0..31) */ | |
6433 | OP_RNQ, /* Neon quad precision register */ | |
037e8744 | 6434 | OP_RVSD, /* VFP single or double precision register */ |
5287ad62 | 6435 | OP_RNDQ, /* Neon double or quad precision register */ |
037e8744 | 6436 | OP_RNSDQ, /* Neon single, double or quad precision register */ |
5287ad62 | 6437 | OP_RNSC, /* Neon scalar D[X] */ |
c19d1205 ZW |
6438 | OP_RVC, /* VFP control register */ |
6439 | OP_RMF, /* Maverick F register */ | |
6440 | OP_RMD, /* Maverick D register */ | |
6441 | OP_RMFX, /* Maverick FX register */ | |
6442 | OP_RMDX, /* Maverick DX register */ | |
6443 | OP_RMAX, /* Maverick AX register */ | |
6444 | OP_RMDS, /* Maverick DSPSC register */ | |
6445 | OP_RIWR, /* iWMMXt wR register */ | |
6446 | OP_RIWC, /* iWMMXt wC register */ | |
6447 | OP_RIWG, /* iWMMXt wCG register */ | |
6448 | OP_RXA, /* XScale accumulator register */ | |
6449 | ||
6450 | OP_REGLST, /* ARM register list */ | |
6451 | OP_VRSLST, /* VFP single-precision register list */ | |
6452 | OP_VRDLST, /* VFP double-precision register list */ | |
037e8744 | 6453 | OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ |
5287ad62 JB |
6454 | OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ |
6455 | OP_NSTRLST, /* Neon element/structure list */ | |
6456 | ||
5287ad62 | 6457 | OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ |
037e8744 | 6458 | OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ |
aacf0b33 | 6459 | OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */ |
5287ad62 | 6460 | OP_RR_RNSC, /* ARM reg or Neon scalar. */ |
037e8744 | 6461 | OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ |
5287ad62 JB |
6462 | OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ |
6463 | OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ | |
6464 | OP_VMOV, /* Neon VMOV operands. */ | |
4316f0d2 | 6465 | OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */ |
5287ad62 | 6466 | OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ |
2d447fca | 6467 | OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ |
5287ad62 JB |
6468 | |
6469 | OP_I0, /* immediate zero */ | |
c19d1205 ZW |
6470 | OP_I7, /* immediate value 0 .. 7 */ |
6471 | OP_I15, /* 0 .. 15 */ | |
6472 | OP_I16, /* 1 .. 16 */ | |
5287ad62 | 6473 | OP_I16z, /* 0 .. 16 */ |
c19d1205 ZW |
6474 | OP_I31, /* 0 .. 31 */ |
6475 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
6476 | OP_I32, /* 1 .. 32 */ | |
5287ad62 JB |
6477 | OP_I32z, /* 0 .. 32 */ |
6478 | OP_I63, /* 0 .. 63 */ | |
c19d1205 | 6479 | OP_I63s, /* -64 .. 63 */ |
5287ad62 JB |
6480 | OP_I64, /* 1 .. 64 */ |
6481 | OP_I64z, /* 0 .. 64 */ | |
c19d1205 | 6482 | OP_I255, /* 0 .. 255 */ |
c19d1205 ZW |
6483 | |
6484 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
6485 | OP_I7b, /* 0 .. 7 */ | |
6486 | OP_I15b, /* 0 .. 15 */ | |
6487 | OP_I31b, /* 0 .. 31 */ | |
6488 | ||
6489 | OP_SH, /* shifter operand */ | |
4962c51a | 6490 | OP_SHG, /* shifter operand with possible group relocation */ |
c19d1205 | 6491 | OP_ADDR, /* Memory address expression (any mode) */ |
4962c51a MS |
6492 | OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ |
6493 | OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ | |
6494 | OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ | |
c19d1205 ZW |
6495 | OP_EXP, /* arbitrary expression */ |
6496 | OP_EXPi, /* same, with optional immediate prefix */ | |
6497 | OP_EXPr, /* same, with optional relocation suffix */ | |
b6895b4f | 6498 | OP_HALF, /* 0 .. 65535 or low/high reloc. */ |
c19d1205 ZW |
6499 | |
6500 | OP_CPSF, /* CPS flags */ | |
6501 | OP_ENDI, /* Endianness specifier */ | |
d2cd1205 JB |
6502 | OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */ |
6503 | OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */ | |
c19d1205 | 6504 | OP_COND, /* conditional code */ |
92e90b6e | 6505 | OP_TB, /* Table branch. */ |
c19d1205 | 6506 | |
037e8744 JB |
6507 | OP_APSR_RR, /* ARM register or "APSR_nzcv". */ |
6508 | ||
c19d1205 ZW |
6509 | OP_RRnpc_I0, /* ARM register or literal 0 */ |
6510 | OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ | |
6511 | OP_RR_EXi, /* ARM register or expression with imm prefix */ | |
6512 | OP_RF_IF, /* FPA register or immediate */ | |
6513 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
41adaa5c | 6514 | OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ |
c19d1205 ZW |
6515 | |
6516 | /* Optional operands. */ | |
6517 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
6518 | OP_oI31b, /* 0 .. 31 */ | |
5287ad62 | 6519 | OP_oI32b, /* 1 .. 32 */ |
5f1af56b | 6520 | OP_oI32z, /* 0 .. 32 */ |
c19d1205 ZW |
6521 | OP_oIffffb, /* 0 .. 65535 */ |
6522 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
6523 | ||
6524 | OP_oRR, /* ARM register */ | |
6525 | OP_oRRnpc, /* ARM register, not the PC */ | |
5be8be5d | 6526 | OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */ |
b6702015 | 6527 | OP_oRRw, /* ARM register, not r15, optional trailing ! */ |
5287ad62 JB |
6528 | OP_oRND, /* Optional Neon double precision register */ |
6529 | OP_oRNQ, /* Optional Neon quad precision register */ | |
6530 | OP_oRNDQ, /* Optional Neon double or quad precision register */ | |
037e8744 | 6531 | OP_oRNSDQ, /* Optional single, double or quad precision vector register */ |
c19d1205 ZW |
6532 | OP_oSHll, /* LSL immediate */ |
6533 | OP_oSHar, /* ASR immediate */ | |
6534 | OP_oSHllar, /* LSL or ASR immediate */ | |
6535 | OP_oROR, /* ROR 0/8/16/24 */ | |
52e7f43d | 6536 | OP_oBARRIER_I15, /* Option argument for a barrier instruction. */ |
c19d1205 | 6537 | |
5be8be5d DG |
6538 | /* Some pre-defined mixed (ARM/THUMB) operands. */ |
6539 | OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp), | |
6540 | OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp), | |
6541 | OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp), | |
6542 | ||
c19d1205 ZW |
6543 | OP_FIRST_OPTIONAL = OP_oI7b |
6544 | }; | |
a737bd4d | 6545 | |
c19d1205 ZW |
6546 | /* Generic instruction operand parser. This does no encoding and no |
6547 | semantic validation; it merely squirrels values away in the inst | |
6548 | structure. Returns SUCCESS or FAIL depending on whether the | |
6549 | specified grammar matched. */ | |
6550 | static int | |
5be8be5d | 6551 | parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) |
c19d1205 | 6552 | { |
5be8be5d | 6553 | unsigned const int *upat = pattern; |
c19d1205 ZW |
6554 | char *backtrack_pos = 0; |
6555 | const char *backtrack_error = 0; | |
99aad254 | 6556 | int i, val = 0, backtrack_index = 0; |
5287ad62 | 6557 | enum arm_reg_type rtype; |
4962c51a | 6558 | parse_operand_result result; |
5be8be5d | 6559 | unsigned int op_parse_code; |
c19d1205 | 6560 | |
e07e6e58 NC |
6561 | #define po_char_or_fail(chr) \ |
6562 | do \ | |
6563 | { \ | |
6564 | if (skip_past_char (&str, chr) == FAIL) \ | |
477330fc | 6565 | goto bad_args; \ |
e07e6e58 NC |
6566 | } \ |
6567 | while (0) | |
c19d1205 | 6568 | |
e07e6e58 NC |
6569 | #define po_reg_or_fail(regtype) \ |
6570 | do \ | |
dcbf9037 | 6571 | { \ |
e07e6e58 | 6572 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ |
477330fc | 6573 | & inst.operands[i].vectype); \ |
e07e6e58 | 6574 | if (val == FAIL) \ |
477330fc RM |
6575 | { \ |
6576 | first_error (_(reg_expected_msgs[regtype])); \ | |
6577 | goto failure; \ | |
6578 | } \ | |
e07e6e58 NC |
6579 | inst.operands[i].reg = val; \ |
6580 | inst.operands[i].isreg = 1; \ | |
6581 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6582 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6583 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
477330fc RM |
6584 | || rtype == REG_TYPE_VFD \ |
6585 | || rtype == REG_TYPE_NQ); \ | |
dcbf9037 | 6586 | } \ |
e07e6e58 NC |
6587 | while (0) |
6588 | ||
6589 | #define po_reg_or_goto(regtype, label) \ | |
6590 | do \ | |
6591 | { \ | |
6592 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ | |
6593 | & inst.operands[i].vectype); \ | |
6594 | if (val == FAIL) \ | |
6595 | goto label; \ | |
dcbf9037 | 6596 | \ |
e07e6e58 NC |
6597 | inst.operands[i].reg = val; \ |
6598 | inst.operands[i].isreg = 1; \ | |
6599 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6600 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6601 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
477330fc | 6602 | || rtype == REG_TYPE_VFD \ |
e07e6e58 NC |
6603 | || rtype == REG_TYPE_NQ); \ |
6604 | } \ | |
6605 | while (0) | |
6606 | ||
6607 | #define po_imm_or_fail(min, max, popt) \ | |
6608 | do \ | |
6609 | { \ | |
6610 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
6611 | goto failure; \ | |
6612 | inst.operands[i].imm = val; \ | |
6613 | } \ | |
6614 | while (0) | |
6615 | ||
6616 | #define po_scalar_or_goto(elsz, label) \ | |
6617 | do \ | |
6618 | { \ | |
6619 | val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \ | |
6620 | if (val == FAIL) \ | |
6621 | goto label; \ | |
6622 | inst.operands[i].reg = val; \ | |
6623 | inst.operands[i].isscalar = 1; \ | |
6624 | } \ | |
6625 | while (0) | |
6626 | ||
6627 | #define po_misc_or_fail(expr) \ | |
6628 | do \ | |
6629 | { \ | |
6630 | if (expr) \ | |
6631 | goto failure; \ | |
6632 | } \ | |
6633 | while (0) | |
6634 | ||
6635 | #define po_misc_or_fail_no_backtrack(expr) \ | |
6636 | do \ | |
6637 | { \ | |
6638 | result = expr; \ | |
6639 | if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \ | |
6640 | backtrack_pos = 0; \ | |
6641 | if (result != PARSE_OPERAND_SUCCESS) \ | |
6642 | goto failure; \ | |
6643 | } \ | |
6644 | while (0) | |
4962c51a | 6645 | |
52e7f43d RE |
6646 | #define po_barrier_or_imm(str) \ |
6647 | do \ | |
6648 | { \ | |
6649 | val = parse_barrier (&str); \ | |
ccb84d65 JB |
6650 | if (val == FAIL && ! ISALPHA (*str)) \ |
6651 | goto immediate; \ | |
6652 | if (val == FAIL \ | |
6653 | /* ISB can only take SY as an option. */ \ | |
6654 | || ((inst.instruction & 0xf0) == 0x60 \ | |
6655 | && val != 0xf)) \ | |
52e7f43d | 6656 | { \ |
ccb84d65 JB |
6657 | inst.error = _("invalid barrier type"); \ |
6658 | backtrack_pos = 0; \ | |
6659 | goto failure; \ | |
52e7f43d RE |
6660 | } \ |
6661 | } \ | |
6662 | while (0) | |
6663 | ||
c19d1205 ZW |
6664 | skip_whitespace (str); |
6665 | ||
6666 | for (i = 0; upat[i] != OP_stop; i++) | |
6667 | { | |
5be8be5d DG |
6668 | op_parse_code = upat[i]; |
6669 | if (op_parse_code >= 1<<16) | |
6670 | op_parse_code = thumb ? (op_parse_code >> 16) | |
6671 | : (op_parse_code & ((1<<16)-1)); | |
6672 | ||
6673 | if (op_parse_code >= OP_FIRST_OPTIONAL) | |
c19d1205 ZW |
6674 | { |
6675 | /* Remember where we are in case we need to backtrack. */ | |
9c2799c2 | 6676 | gas_assert (!backtrack_pos); |
c19d1205 ZW |
6677 | backtrack_pos = str; |
6678 | backtrack_error = inst.error; | |
6679 | backtrack_index = i; | |
6680 | } | |
6681 | ||
b6702015 | 6682 | if (i > 0 && (i > 1 || inst.operands[0].present)) |
c19d1205 ZW |
6683 | po_char_or_fail (','); |
6684 | ||
5be8be5d | 6685 | switch (op_parse_code) |
c19d1205 ZW |
6686 | { |
6687 | /* Registers */ | |
6688 | case OP_oRRnpc: | |
5be8be5d | 6689 | case OP_oRRnpcsp: |
c19d1205 | 6690 | case OP_RRnpc: |
5be8be5d | 6691 | case OP_RRnpcsp: |
c19d1205 ZW |
6692 | case OP_oRR: |
6693 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; | |
6694 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
6695 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
6696 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
6697 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
6698 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
477330fc | 6699 | case OP_oRND: |
5287ad62 | 6700 | case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; |
cd2cf30b PB |
6701 | case OP_RVC: |
6702 | po_reg_or_goto (REG_TYPE_VFC, coproc_reg); | |
6703 | break; | |
6704 | /* Also accept generic coprocessor regs for unknown registers. */ | |
6705 | coproc_reg: | |
6706 | po_reg_or_fail (REG_TYPE_CN); | |
6707 | break; | |
c19d1205 ZW |
6708 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; |
6709 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
6710 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
6711 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
6712 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
6713 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
6714 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
6715 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
6716 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
6717 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
477330fc | 6718 | case OP_oRNQ: |
5287ad62 | 6719 | case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; |
477330fc | 6720 | case OP_oRNDQ: |
5287ad62 | 6721 | case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; |
477330fc RM |
6722 | case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; |
6723 | case OP_oRNSDQ: | |
6724 | case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; | |
6725 | ||
6726 | /* Neon scalar. Using an element size of 8 means that some invalid | |
6727 | scalars are accepted here, so deal with those in later code. */ | |
6728 | case OP_RNSC: po_scalar_or_goto (8, failure); break; | |
6729 | ||
6730 | case OP_RNDQ_I0: | |
6731 | { | |
6732 | po_reg_or_goto (REG_TYPE_NDQ, try_imm0); | |
6733 | break; | |
6734 | try_imm0: | |
6735 | po_imm_or_fail (0, 0, TRUE); | |
6736 | } | |
6737 | break; | |
6738 | ||
6739 | case OP_RVSD_I0: | |
6740 | po_reg_or_goto (REG_TYPE_VFSD, try_imm0); | |
6741 | break; | |
6742 | ||
aacf0b33 KT |
6743 | case OP_RSVD_FI0: |
6744 | { | |
6745 | po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0); | |
6746 | break; | |
6747 | try_ifimm0: | |
6748 | if (parse_ifimm_zero (&str)) | |
6749 | inst.operands[i].imm = 0; | |
6750 | else | |
6751 | { | |
6752 | inst.error | |
6753 | = _("only floating point zero is allowed as immediate value"); | |
6754 | goto failure; | |
6755 | } | |
6756 | } | |
6757 | break; | |
6758 | ||
477330fc RM |
6759 | case OP_RR_RNSC: |
6760 | { | |
6761 | po_scalar_or_goto (8, try_rr); | |
6762 | break; | |
6763 | try_rr: | |
6764 | po_reg_or_fail (REG_TYPE_RN); | |
6765 | } | |
6766 | break; | |
6767 | ||
6768 | case OP_RNSDQ_RNSC: | |
6769 | { | |
6770 | po_scalar_or_goto (8, try_nsdq); | |
6771 | break; | |
6772 | try_nsdq: | |
6773 | po_reg_or_fail (REG_TYPE_NSDQ); | |
6774 | } | |
6775 | break; | |
6776 | ||
6777 | case OP_RNDQ_RNSC: | |
6778 | { | |
6779 | po_scalar_or_goto (8, try_ndq); | |
6780 | break; | |
6781 | try_ndq: | |
6782 | po_reg_or_fail (REG_TYPE_NDQ); | |
6783 | } | |
6784 | break; | |
6785 | ||
6786 | case OP_RND_RNSC: | |
6787 | { | |
6788 | po_scalar_or_goto (8, try_vfd); | |
6789 | break; | |
6790 | try_vfd: | |
6791 | po_reg_or_fail (REG_TYPE_VFD); | |
6792 | } | |
6793 | break; | |
6794 | ||
6795 | case OP_VMOV: | |
6796 | /* WARNING: parse_neon_mov can move the operand counter, i. If we're | |
6797 | not careful then bad things might happen. */ | |
6798 | po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); | |
6799 | break; | |
6800 | ||
6801 | case OP_RNDQ_Ibig: | |
6802 | { | |
6803 | po_reg_or_goto (REG_TYPE_NDQ, try_immbig); | |
6804 | break; | |
6805 | try_immbig: | |
6806 | /* There's a possibility of getting a 64-bit immediate here, so | |
6807 | we need special handling. */ | |
8335d6aa JW |
6808 | if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE) |
6809 | == FAIL) | |
477330fc RM |
6810 | { |
6811 | inst.error = _("immediate value is out of range"); | |
6812 | goto failure; | |
6813 | } | |
6814 | } | |
6815 | break; | |
6816 | ||
6817 | case OP_RNDQ_I63b: | |
6818 | { | |
6819 | po_reg_or_goto (REG_TYPE_NDQ, try_shimm); | |
6820 | break; | |
6821 | try_shimm: | |
6822 | po_imm_or_fail (0, 63, TRUE); | |
6823 | } | |
6824 | break; | |
c19d1205 ZW |
6825 | |
6826 | case OP_RRnpcb: | |
6827 | po_char_or_fail ('['); | |
6828 | po_reg_or_fail (REG_TYPE_RN); | |
6829 | po_char_or_fail (']'); | |
6830 | break; | |
a737bd4d | 6831 | |
55881a11 | 6832 | case OP_RRnpctw: |
c19d1205 | 6833 | case OP_RRw: |
b6702015 | 6834 | case OP_oRRw: |
c19d1205 ZW |
6835 | po_reg_or_fail (REG_TYPE_RN); |
6836 | if (skip_past_char (&str, '!') == SUCCESS) | |
6837 | inst.operands[i].writeback = 1; | |
6838 | break; | |
6839 | ||
6840 | /* Immediates */ | |
6841 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
6842 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
6843 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
477330fc | 6844 | case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; |
c19d1205 ZW |
6845 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; |
6846 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
477330fc | 6847 | case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; |
c19d1205 | 6848 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; |
477330fc RM |
6849 | case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; |
6850 | case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; | |
6851 | case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; | |
c19d1205 | 6852 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; |
c19d1205 ZW |
6853 | |
6854 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
6855 | case OP_oI7b: | |
6856 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
6857 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
6858 | case OP_oI31b: | |
6859 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
477330fc RM |
6860 | case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; |
6861 | case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break; | |
c19d1205 ZW |
6862 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; |
6863 | ||
6864 | /* Immediate variants */ | |
6865 | case OP_oI255c: | |
6866 | po_char_or_fail ('{'); | |
6867 | po_imm_or_fail (0, 255, TRUE); | |
6868 | po_char_or_fail ('}'); | |
6869 | break; | |
6870 | ||
6871 | case OP_I31w: | |
6872 | /* The expression parser chokes on a trailing !, so we have | |
6873 | to find it first and zap it. */ | |
6874 | { | |
6875 | char *s = str; | |
6876 | while (*s && *s != ',') | |
6877 | s++; | |
6878 | if (s[-1] == '!') | |
6879 | { | |
6880 | s[-1] = '\0'; | |
6881 | inst.operands[i].writeback = 1; | |
6882 | } | |
6883 | po_imm_or_fail (0, 31, TRUE); | |
6884 | if (str == s - 1) | |
6885 | str = s; | |
6886 | } | |
6887 | break; | |
6888 | ||
6889 | /* Expressions */ | |
6890 | case OP_EXPi: EXPi: | |
6891 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6892 | GE_OPT_PREFIX)); | |
6893 | break; | |
6894 | ||
6895 | case OP_EXP: | |
6896 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6897 | GE_NO_PREFIX)); | |
6898 | break; | |
6899 | ||
6900 | case OP_EXPr: EXPr: | |
6901 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6902 | GE_NO_PREFIX)); | |
6903 | if (inst.reloc.exp.X_op == O_symbol) | |
a737bd4d | 6904 | { |
c19d1205 ZW |
6905 | val = parse_reloc (&str); |
6906 | if (val == -1) | |
6907 | { | |
6908 | inst.error = _("unrecognized relocation suffix"); | |
6909 | goto failure; | |
6910 | } | |
6911 | else if (val != BFD_RELOC_UNUSED) | |
6912 | { | |
6913 | inst.operands[i].imm = val; | |
6914 | inst.operands[i].hasreloc = 1; | |
6915 | } | |
a737bd4d | 6916 | } |
c19d1205 | 6917 | break; |
a737bd4d | 6918 | |
b6895b4f PB |
6919 | /* Operand for MOVW or MOVT. */ |
6920 | case OP_HALF: | |
6921 | po_misc_or_fail (parse_half (&str)); | |
6922 | break; | |
6923 | ||
e07e6e58 | 6924 | /* Register or expression. */ |
c19d1205 ZW |
6925 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; |
6926 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 6927 | |
e07e6e58 | 6928 | /* Register or immediate. */ |
c19d1205 ZW |
6929 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; |
6930 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 6931 | |
c19d1205 ZW |
6932 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
6933 | IF: | |
6934 | if (!is_immediate_prefix (*str)) | |
6935 | goto bad_args; | |
6936 | str++; | |
6937 | val = parse_fpa_immediate (&str); | |
6938 | if (val == FAIL) | |
6939 | goto failure; | |
6940 | /* FPA immediates are encoded as registers 8-15. | |
6941 | parse_fpa_immediate has already applied the offset. */ | |
6942 | inst.operands[i].reg = val; | |
6943 | inst.operands[i].isreg = 1; | |
6944 | break; | |
09d92015 | 6945 | |
2d447fca JM |
6946 | case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; |
6947 | I32z: po_imm_or_fail (0, 32, FALSE); break; | |
6948 | ||
e07e6e58 | 6949 | /* Two kinds of register. */ |
c19d1205 ZW |
6950 | case OP_RIWR_RIWC: |
6951 | { | |
6952 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
97f87066 JM |
6953 | if (!rege |
6954 | || (rege->type != REG_TYPE_MMXWR | |
6955 | && rege->type != REG_TYPE_MMXWC | |
6956 | && rege->type != REG_TYPE_MMXWCG)) | |
c19d1205 ZW |
6957 | { |
6958 | inst.error = _("iWMMXt data or control register expected"); | |
6959 | goto failure; | |
6960 | } | |
6961 | inst.operands[i].reg = rege->number; | |
6962 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
6963 | } | |
6964 | break; | |
09d92015 | 6965 | |
41adaa5c JM |
6966 | case OP_RIWC_RIWG: |
6967 | { | |
6968 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
6969 | if (!rege | |
6970 | || (rege->type != REG_TYPE_MMXWC | |
6971 | && rege->type != REG_TYPE_MMXWCG)) | |
6972 | { | |
6973 | inst.error = _("iWMMXt control register expected"); | |
6974 | goto failure; | |
6975 | } | |
6976 | inst.operands[i].reg = rege->number; | |
6977 | inst.operands[i].isreg = 1; | |
6978 | } | |
6979 | break; | |
6980 | ||
c19d1205 ZW |
6981 | /* Misc */ |
6982 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
6983 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
6984 | case OP_oROR: val = parse_ror (&str); break; | |
c19d1205 | 6985 | case OP_COND: val = parse_cond (&str); break; |
52e7f43d RE |
6986 | case OP_oBARRIER_I15: |
6987 | po_barrier_or_imm (str); break; | |
6988 | immediate: | |
6989 | if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL) | |
477330fc | 6990 | goto failure; |
52e7f43d | 6991 | break; |
c19d1205 | 6992 | |
fa94de6b | 6993 | case OP_wPSR: |
d2cd1205 | 6994 | case OP_rPSR: |
90ec0d68 MGD |
6995 | po_reg_or_goto (REG_TYPE_RNB, try_psr); |
6996 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt)) | |
6997 | { | |
6998 | inst.error = _("Banked registers are not available with this " | |
6999 | "architecture."); | |
7000 | goto failure; | |
7001 | } | |
7002 | break; | |
d2cd1205 JB |
7003 | try_psr: |
7004 | val = parse_psr (&str, op_parse_code == OP_wPSR); | |
7005 | break; | |
037e8744 | 7006 | |
477330fc RM |
7007 | case OP_APSR_RR: |
7008 | po_reg_or_goto (REG_TYPE_RN, try_apsr); | |
7009 | break; | |
7010 | try_apsr: | |
7011 | /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS | |
7012 | instruction). */ | |
7013 | if (strncasecmp (str, "APSR_", 5) == 0) | |
7014 | { | |
7015 | unsigned found = 0; | |
7016 | str += 5; | |
7017 | while (found < 15) | |
7018 | switch (*str++) | |
7019 | { | |
7020 | case 'c': found = (found & 1) ? 16 : found | 1; break; | |
7021 | case 'n': found = (found & 2) ? 16 : found | 2; break; | |
7022 | case 'z': found = (found & 4) ? 16 : found | 4; break; | |
7023 | case 'v': found = (found & 8) ? 16 : found | 8; break; | |
7024 | default: found = 16; | |
7025 | } | |
7026 | if (found != 15) | |
7027 | goto failure; | |
7028 | inst.operands[i].isvec = 1; | |
f7c21dc7 NC |
7029 | /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */ |
7030 | inst.operands[i].reg = REG_PC; | |
477330fc RM |
7031 | } |
7032 | else | |
7033 | goto failure; | |
7034 | break; | |
037e8744 | 7035 | |
92e90b6e PB |
7036 | case OP_TB: |
7037 | po_misc_or_fail (parse_tb (&str)); | |
7038 | break; | |
7039 | ||
e07e6e58 | 7040 | /* Register lists. */ |
c19d1205 ZW |
7041 | case OP_REGLST: |
7042 | val = parse_reg_list (&str); | |
7043 | if (*str == '^') | |
7044 | { | |
7045 | inst.operands[1].writeback = 1; | |
7046 | str++; | |
7047 | } | |
7048 | break; | |
09d92015 | 7049 | |
c19d1205 | 7050 | case OP_VRSLST: |
5287ad62 | 7051 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); |
c19d1205 | 7052 | break; |
09d92015 | 7053 | |
c19d1205 | 7054 | case OP_VRDLST: |
5287ad62 | 7055 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); |
c19d1205 | 7056 | break; |
a737bd4d | 7057 | |
477330fc RM |
7058 | case OP_VRSDLST: |
7059 | /* Allow Q registers too. */ | |
7060 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
7061 | REGLIST_NEON_D); | |
7062 | if (val == FAIL) | |
7063 | { | |
7064 | inst.error = NULL; | |
7065 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
7066 | REGLIST_VFP_S); | |
7067 | inst.operands[i].issingle = 1; | |
7068 | } | |
7069 | break; | |
7070 | ||
7071 | case OP_NRDLST: | |
7072 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
7073 | REGLIST_NEON_D); | |
7074 | break; | |
5287ad62 JB |
7075 | |
7076 | case OP_NSTRLST: | |
477330fc RM |
7077 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, |
7078 | &inst.operands[i].vectype); | |
7079 | break; | |
5287ad62 | 7080 | |
c19d1205 ZW |
7081 | /* Addressing modes */ |
7082 | case OP_ADDR: | |
7083 | po_misc_or_fail (parse_address (&str, i)); | |
7084 | break; | |
09d92015 | 7085 | |
4962c51a MS |
7086 | case OP_ADDRGLDR: |
7087 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7088 | parse_address_group_reloc (&str, i, GROUP_LDR)); |
4962c51a MS |
7089 | break; |
7090 | ||
7091 | case OP_ADDRGLDRS: | |
7092 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7093 | parse_address_group_reloc (&str, i, GROUP_LDRS)); |
4962c51a MS |
7094 | break; |
7095 | ||
7096 | case OP_ADDRGLDC: | |
7097 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7098 | parse_address_group_reloc (&str, i, GROUP_LDC)); |
4962c51a MS |
7099 | break; |
7100 | ||
c19d1205 ZW |
7101 | case OP_SH: |
7102 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
7103 | break; | |
09d92015 | 7104 | |
4962c51a MS |
7105 | case OP_SHG: |
7106 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7107 | parse_shifter_operand_group_reloc (&str, i)); |
4962c51a MS |
7108 | break; |
7109 | ||
c19d1205 ZW |
7110 | case OP_oSHll: |
7111 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
7112 | break; | |
09d92015 | 7113 | |
c19d1205 ZW |
7114 | case OP_oSHar: |
7115 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
7116 | break; | |
09d92015 | 7117 | |
c19d1205 ZW |
7118 | case OP_oSHllar: |
7119 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
7120 | break; | |
09d92015 | 7121 | |
c19d1205 | 7122 | default: |
5be8be5d | 7123 | as_fatal (_("unhandled operand code %d"), op_parse_code); |
c19d1205 | 7124 | } |
09d92015 | 7125 | |
c19d1205 ZW |
7126 | /* Various value-based sanity checks and shared operations. We |
7127 | do not signal immediate failures for the register constraints; | |
7128 | this allows a syntax error to take precedence. */ | |
5be8be5d | 7129 | switch (op_parse_code) |
c19d1205 ZW |
7130 | { |
7131 | case OP_oRRnpc: | |
7132 | case OP_RRnpc: | |
7133 | case OP_RRnpcb: | |
7134 | case OP_RRw: | |
b6702015 | 7135 | case OP_oRRw: |
c19d1205 ZW |
7136 | case OP_RRnpc_I0: |
7137 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
7138 | inst.error = BAD_PC; | |
7139 | break; | |
09d92015 | 7140 | |
5be8be5d DG |
7141 | case OP_oRRnpcsp: |
7142 | case OP_RRnpcsp: | |
7143 | if (inst.operands[i].isreg) | |
7144 | { | |
7145 | if (inst.operands[i].reg == REG_PC) | |
7146 | inst.error = BAD_PC; | |
7147 | else if (inst.operands[i].reg == REG_SP) | |
7148 | inst.error = BAD_SP; | |
7149 | } | |
7150 | break; | |
7151 | ||
55881a11 | 7152 | case OP_RRnpctw: |
fa94de6b RM |
7153 | if (inst.operands[i].isreg |
7154 | && inst.operands[i].reg == REG_PC | |
55881a11 MGD |
7155 | && (inst.operands[i].writeback || thumb)) |
7156 | inst.error = BAD_PC; | |
7157 | break; | |
7158 | ||
c19d1205 ZW |
7159 | case OP_CPSF: |
7160 | case OP_ENDI: | |
7161 | case OP_oROR: | |
d2cd1205 JB |
7162 | case OP_wPSR: |
7163 | case OP_rPSR: | |
c19d1205 | 7164 | case OP_COND: |
52e7f43d | 7165 | case OP_oBARRIER_I15: |
c19d1205 ZW |
7166 | case OP_REGLST: |
7167 | case OP_VRSLST: | |
7168 | case OP_VRDLST: | |
477330fc RM |
7169 | case OP_VRSDLST: |
7170 | case OP_NRDLST: | |
7171 | case OP_NSTRLST: | |
c19d1205 ZW |
7172 | if (val == FAIL) |
7173 | goto failure; | |
7174 | inst.operands[i].imm = val; | |
7175 | break; | |
a737bd4d | 7176 | |
c19d1205 ZW |
7177 | default: |
7178 | break; | |
7179 | } | |
09d92015 | 7180 | |
c19d1205 ZW |
7181 | /* If we get here, this operand was successfully parsed. */ |
7182 | inst.operands[i].present = 1; | |
7183 | continue; | |
09d92015 | 7184 | |
c19d1205 | 7185 | bad_args: |
09d92015 | 7186 | inst.error = BAD_ARGS; |
c19d1205 ZW |
7187 | |
7188 | failure: | |
7189 | if (!backtrack_pos) | |
d252fdde PB |
7190 | { |
7191 | /* The parse routine should already have set inst.error, but set a | |
5f4273c7 | 7192 | default here just in case. */ |
d252fdde PB |
7193 | if (!inst.error) |
7194 | inst.error = _("syntax error"); | |
7195 | return FAIL; | |
7196 | } | |
c19d1205 ZW |
7197 | |
7198 | /* Do not backtrack over a trailing optional argument that | |
7199 | absorbed some text. We will only fail again, with the | |
7200 | 'garbage following instruction' error message, which is | |
7201 | probably less helpful than the current one. */ | |
7202 | if (backtrack_index == i && backtrack_pos != str | |
7203 | && upat[i+1] == OP_stop) | |
d252fdde PB |
7204 | { |
7205 | if (!inst.error) | |
7206 | inst.error = _("syntax error"); | |
7207 | return FAIL; | |
7208 | } | |
c19d1205 ZW |
7209 | |
7210 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
7211 | str = backtrack_pos; | |
7212 | inst.error = backtrack_error; | |
7213 | inst.operands[backtrack_index].present = 0; | |
7214 | i = backtrack_index; | |
7215 | backtrack_pos = 0; | |
09d92015 | 7216 | } |
09d92015 | 7217 | |
c19d1205 ZW |
7218 | /* Check that we have parsed all the arguments. */ |
7219 | if (*str != '\0' && !inst.error) | |
7220 | inst.error = _("garbage following instruction"); | |
09d92015 | 7221 | |
c19d1205 | 7222 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
7223 | } |
7224 | ||
c19d1205 ZW |
7225 | #undef po_char_or_fail |
7226 | #undef po_reg_or_fail | |
7227 | #undef po_reg_or_goto | |
7228 | #undef po_imm_or_fail | |
5287ad62 | 7229 | #undef po_scalar_or_fail |
52e7f43d | 7230 | #undef po_barrier_or_imm |
e07e6e58 | 7231 | |
c19d1205 | 7232 | /* Shorthand macro for instruction encoding functions issuing errors. */ |
e07e6e58 NC |
7233 | #define constraint(expr, err) \ |
7234 | do \ | |
c19d1205 | 7235 | { \ |
e07e6e58 NC |
7236 | if (expr) \ |
7237 | { \ | |
7238 | inst.error = err; \ | |
7239 | return; \ | |
7240 | } \ | |
c19d1205 | 7241 | } \ |
e07e6e58 | 7242 | while (0) |
c19d1205 | 7243 | |
fdfde340 JM |
7244 | /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 |
7245 | instructions are unpredictable if these registers are used. This | |
7246 | is the BadReg predicate in ARM's Thumb-2 documentation. */ | |
7247 | #define reject_bad_reg(reg) \ | |
7248 | do \ | |
7249 | if (reg == REG_SP || reg == REG_PC) \ | |
7250 | { \ | |
7251 | inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \ | |
7252 | return; \ | |
7253 | } \ | |
7254 | while (0) | |
7255 | ||
94206790 MM |
7256 | /* If REG is R13 (the stack pointer), warn that its use is |
7257 | deprecated. */ | |
7258 | #define warn_deprecated_sp(reg) \ | |
7259 | do \ | |
7260 | if (warn_on_deprecated && reg == REG_SP) \ | |
5c3696f8 | 7261 | as_tsktsk (_("use of r13 is deprecated")); \ |
94206790 MM |
7262 | while (0) |
7263 | ||
c19d1205 ZW |
7264 | /* Functions for operand encoding. ARM, then Thumb. */ |
7265 | ||
d840c081 | 7266 | #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31)) |
c19d1205 ZW |
7267 | |
7268 | /* If VAL can be encoded in the immediate field of an ARM instruction, | |
7269 | return the encoded form. Otherwise, return FAIL. */ | |
7270 | ||
7271 | static unsigned int | |
7272 | encode_arm_immediate (unsigned int val) | |
09d92015 | 7273 | { |
c19d1205 ZW |
7274 | unsigned int a, i; |
7275 | ||
7276 | for (i = 0; i < 32; i += 2) | |
7277 | if ((a = rotate_left (val, i)) <= 0xff) | |
7278 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
7279 | ||
7280 | return FAIL; | |
09d92015 MM |
7281 | } |
7282 | ||
c19d1205 ZW |
7283 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
7284 | return the encoded form. Otherwise, return FAIL. */ | |
7285 | static unsigned int | |
7286 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 7287 | { |
c19d1205 | 7288 | unsigned int a, i; |
09d92015 | 7289 | |
9c3c69f2 | 7290 | if (val <= 0xff) |
c19d1205 | 7291 | return val; |
a737bd4d | 7292 | |
9c3c69f2 | 7293 | for (i = 1; i <= 24; i++) |
09d92015 | 7294 | { |
9c3c69f2 PB |
7295 | a = val >> i; |
7296 | if ((val & ~(0xff << i)) == 0) | |
7297 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 7298 | } |
a737bd4d | 7299 | |
c19d1205 ZW |
7300 | a = val & 0xff; |
7301 | if (val == ((a << 16) | a)) | |
7302 | return 0x100 | a; | |
7303 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
7304 | return 0x300 | a; | |
09d92015 | 7305 | |
c19d1205 ZW |
7306 | a = val & 0xff00; |
7307 | if (val == ((a << 16) | a)) | |
7308 | return 0x200 | (a >> 8); | |
a737bd4d | 7309 | |
c19d1205 | 7310 | return FAIL; |
09d92015 | 7311 | } |
5287ad62 | 7312 | /* Encode a VFP SP or DP register number into inst.instruction. */ |
09d92015 MM |
7313 | |
7314 | static void | |
5287ad62 JB |
7315 | encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) |
7316 | { | |
7317 | if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) | |
7318 | && reg > 15) | |
7319 | { | |
b1cc4aeb | 7320 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) |
477330fc RM |
7321 | { |
7322 | if (thumb_mode) | |
7323 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
7324 | fpu_vfp_ext_d32); | |
7325 | else | |
7326 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
7327 | fpu_vfp_ext_d32); | |
7328 | } | |
5287ad62 | 7329 | else |
477330fc RM |
7330 | { |
7331 | first_error (_("D register out of range for selected VFP version")); | |
7332 | return; | |
7333 | } | |
5287ad62 JB |
7334 | } |
7335 | ||
c19d1205 | 7336 | switch (pos) |
09d92015 | 7337 | { |
c19d1205 ZW |
7338 | case VFP_REG_Sd: |
7339 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
7340 | break; | |
7341 | ||
7342 | case VFP_REG_Sn: | |
7343 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
7344 | break; | |
7345 | ||
7346 | case VFP_REG_Sm: | |
7347 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
7348 | break; | |
7349 | ||
5287ad62 JB |
7350 | case VFP_REG_Dd: |
7351 | inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); | |
7352 | break; | |
5f4273c7 | 7353 | |
5287ad62 JB |
7354 | case VFP_REG_Dn: |
7355 | inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); | |
7356 | break; | |
5f4273c7 | 7357 | |
5287ad62 JB |
7358 | case VFP_REG_Dm: |
7359 | inst.instruction |= (reg & 15) | ((reg >> 4) << 5); | |
7360 | break; | |
7361 | ||
c19d1205 ZW |
7362 | default: |
7363 | abort (); | |
09d92015 | 7364 | } |
09d92015 MM |
7365 | } |
7366 | ||
c19d1205 | 7367 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 7368 | if any, is handled by md_apply_fix. */ |
09d92015 | 7369 | static void |
c19d1205 | 7370 | encode_arm_shift (int i) |
09d92015 | 7371 | { |
c19d1205 ZW |
7372 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
7373 | inst.instruction |= SHIFT_ROR << 5; | |
7374 | else | |
09d92015 | 7375 | { |
c19d1205 ZW |
7376 | inst.instruction |= inst.operands[i].shift_kind << 5; |
7377 | if (inst.operands[i].immisreg) | |
7378 | { | |
7379 | inst.instruction |= SHIFT_BY_REG; | |
7380 | inst.instruction |= inst.operands[i].imm << 8; | |
7381 | } | |
7382 | else | |
7383 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
09d92015 | 7384 | } |
c19d1205 | 7385 | } |
09d92015 | 7386 | |
c19d1205 ZW |
7387 | static void |
7388 | encode_arm_shifter_operand (int i) | |
7389 | { | |
7390 | if (inst.operands[i].isreg) | |
09d92015 | 7391 | { |
c19d1205 ZW |
7392 | inst.instruction |= inst.operands[i].reg; |
7393 | encode_arm_shift (i); | |
09d92015 | 7394 | } |
c19d1205 | 7395 | else |
a415b1cd JB |
7396 | { |
7397 | inst.instruction |= INST_IMMEDIATE; | |
7398 | if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE) | |
7399 | inst.instruction |= inst.operands[i].imm; | |
7400 | } | |
09d92015 MM |
7401 | } |
7402 | ||
c19d1205 | 7403 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 7404 | static void |
c19d1205 | 7405 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 7406 | { |
2b2f5df9 NC |
7407 | /* PR 14260: |
7408 | Generate an error if the operand is not a register. */ | |
7409 | constraint (!inst.operands[i].isreg, | |
7410 | _("Instruction does not support =N addresses")); | |
7411 | ||
c19d1205 | 7412 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 7413 | |
c19d1205 | 7414 | if (inst.operands[i].preind) |
09d92015 | 7415 | { |
c19d1205 ZW |
7416 | if (is_t) |
7417 | { | |
7418 | inst.error = _("instruction does not accept preindexed addressing"); | |
7419 | return; | |
7420 | } | |
7421 | inst.instruction |= PRE_INDEX; | |
7422 | if (inst.operands[i].writeback) | |
7423 | inst.instruction |= WRITE_BACK; | |
09d92015 | 7424 | |
c19d1205 ZW |
7425 | } |
7426 | else if (inst.operands[i].postind) | |
7427 | { | |
9c2799c2 | 7428 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
7429 | if (is_t) |
7430 | inst.instruction |= WRITE_BACK; | |
7431 | } | |
7432 | else /* unindexed - only for coprocessor */ | |
09d92015 | 7433 | { |
c19d1205 | 7434 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
7435 | return; |
7436 | } | |
7437 | ||
c19d1205 ZW |
7438 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
7439 | && (((inst.instruction & 0x000f0000) >> 16) | |
7440 | == ((inst.instruction & 0x0000f000) >> 12))) | |
7441 | as_warn ((inst.instruction & LOAD_BIT) | |
7442 | ? _("destination register same as write-back base") | |
7443 | : _("source register same as write-back base")); | |
09d92015 MM |
7444 | } |
7445 | ||
c19d1205 ZW |
7446 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7447 | ARM-format mode 2 load or store instruction. If is_t is true, | |
7448 | reject forms that cannot be used with a T instruction (i.e. not | |
7449 | post-indexed). */ | |
a737bd4d | 7450 | static void |
c19d1205 | 7451 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 7452 | { |
5be8be5d DG |
7453 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
7454 | ||
c19d1205 | 7455 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 7456 | |
c19d1205 | 7457 | if (inst.operands[i].immisreg) |
09d92015 | 7458 | { |
5be8be5d DG |
7459 | constraint ((inst.operands[i].imm == REG_PC |
7460 | || (is_pc && inst.operands[i].writeback)), | |
7461 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
7462 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
7463 | inst.instruction |= inst.operands[i].imm; | |
7464 | if (!inst.operands[i].negative) | |
7465 | inst.instruction |= INDEX_UP; | |
7466 | if (inst.operands[i].shifted) | |
7467 | { | |
7468 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
7469 | inst.instruction |= SHIFT_ROR << 5; | |
7470 | else | |
7471 | { | |
7472 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
7473 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
7474 | } | |
7475 | } | |
09d92015 | 7476 | } |
c19d1205 | 7477 | else /* immediate offset in inst.reloc */ |
09d92015 | 7478 | { |
5be8be5d DG |
7479 | if (is_pc && !inst.reloc.pc_rel) |
7480 | { | |
7481 | const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0); | |
23a10334 JZ |
7482 | |
7483 | /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt | |
7484 | cannot use PC in addressing. | |
7485 | PC cannot be used in writeback addressing, either. */ | |
7486 | constraint ((is_t || inst.operands[i].writeback), | |
5be8be5d | 7487 | BAD_PC_ADDRESSING); |
23a10334 | 7488 | |
dc5ec521 | 7489 | /* Use of PC in str is deprecated for ARMv7. */ |
23a10334 JZ |
7490 | if (warn_on_deprecated |
7491 | && !is_load | |
7492 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) | |
5c3696f8 | 7493 | as_tsktsk (_("use of PC in this instruction is deprecated")); |
5be8be5d DG |
7494 | } |
7495 | ||
c19d1205 | 7496 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
26d97720 NS |
7497 | { |
7498 | /* Prefer + for zero encoded value. */ | |
7499 | if (!inst.operands[i].negative) | |
7500 | inst.instruction |= INDEX_UP; | |
7501 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
7502 | } | |
09d92015 | 7503 | } |
09d92015 MM |
7504 | } |
7505 | ||
c19d1205 ZW |
7506 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7507 | ARM-format mode 3 load or store instruction. Reject forms that | |
7508 | cannot be used with such instructions. If is_t is true, reject | |
7509 | forms that cannot be used with a T instruction (i.e. not | |
7510 | post-indexed). */ | |
7511 | static void | |
7512 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 7513 | { |
c19d1205 | 7514 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 7515 | { |
c19d1205 ZW |
7516 | inst.error = _("instruction does not accept scaled register index"); |
7517 | return; | |
09d92015 | 7518 | } |
a737bd4d | 7519 | |
c19d1205 | 7520 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 7521 | |
c19d1205 ZW |
7522 | if (inst.operands[i].immisreg) |
7523 | { | |
5be8be5d | 7524 | constraint ((inst.operands[i].imm == REG_PC |
eb9f3f00 | 7525 | || (is_t && inst.operands[i].reg == REG_PC)), |
5be8be5d | 7526 | BAD_PC_ADDRESSING); |
eb9f3f00 JB |
7527 | constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback, |
7528 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
7529 | inst.instruction |= inst.operands[i].imm; |
7530 | if (!inst.operands[i].negative) | |
7531 | inst.instruction |= INDEX_UP; | |
7532 | } | |
7533 | else /* immediate offset in inst.reloc */ | |
7534 | { | |
5be8be5d DG |
7535 | constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel |
7536 | && inst.operands[i].writeback), | |
7537 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
7538 | inst.instruction |= HWOFFSET_IMM; |
7539 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
26d97720 NS |
7540 | { |
7541 | /* Prefer + for zero encoded value. */ | |
7542 | if (!inst.operands[i].negative) | |
7543 | inst.instruction |= INDEX_UP; | |
7544 | ||
7545 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
7546 | } | |
c19d1205 | 7547 | } |
a737bd4d NC |
7548 | } |
7549 | ||
8335d6aa JW |
7550 | /* Write immediate bits [7:0] to the following locations: |
7551 | ||
7552 | |28/24|23 19|18 16|15 4|3 0| | |
7553 | | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| | |
7554 | ||
7555 | This function is used by VMOV/VMVN/VORR/VBIC. */ | |
7556 | ||
7557 | static void | |
7558 | neon_write_immbits (unsigned immbits) | |
7559 | { | |
7560 | inst.instruction |= immbits & 0xf; | |
7561 | inst.instruction |= ((immbits >> 4) & 0x7) << 16; | |
7562 | inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24); | |
7563 | } | |
7564 | ||
7565 | /* Invert low-order SIZE bits of XHI:XLO. */ | |
7566 | ||
7567 | static void | |
7568 | neon_invert_size (unsigned *xlo, unsigned *xhi, int size) | |
7569 | { | |
7570 | unsigned immlo = xlo ? *xlo : 0; | |
7571 | unsigned immhi = xhi ? *xhi : 0; | |
7572 | ||
7573 | switch (size) | |
7574 | { | |
7575 | case 8: | |
7576 | immlo = (~immlo) & 0xff; | |
7577 | break; | |
7578 | ||
7579 | case 16: | |
7580 | immlo = (~immlo) & 0xffff; | |
7581 | break; | |
7582 | ||
7583 | case 64: | |
7584 | immhi = (~immhi) & 0xffffffff; | |
7585 | /* fall through. */ | |
7586 | ||
7587 | case 32: | |
7588 | immlo = (~immlo) & 0xffffffff; | |
7589 | break; | |
7590 | ||
7591 | default: | |
7592 | abort (); | |
7593 | } | |
7594 | ||
7595 | if (xlo) | |
7596 | *xlo = immlo; | |
7597 | ||
7598 | if (xhi) | |
7599 | *xhi = immhi; | |
7600 | } | |
7601 | ||
7602 | /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits | |
7603 | A, B, C, D. */ | |
09d92015 | 7604 | |
c19d1205 | 7605 | static int |
8335d6aa | 7606 | neon_bits_same_in_bytes (unsigned imm) |
09d92015 | 7607 | { |
8335d6aa JW |
7608 | return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) |
7609 | && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) | |
7610 | && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) | |
7611 | && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); | |
7612 | } | |
a737bd4d | 7613 | |
8335d6aa | 7614 | /* For immediate of above form, return 0bABCD. */ |
09d92015 | 7615 | |
8335d6aa JW |
7616 | static unsigned |
7617 | neon_squash_bits (unsigned imm) | |
7618 | { | |
7619 | return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) | |
7620 | | ((imm & 0x01000000) >> 21); | |
7621 | } | |
7622 | ||
7623 | /* Compress quarter-float representation to 0b...000 abcdefgh. */ | |
7624 | ||
7625 | static unsigned | |
7626 | neon_qfloat_bits (unsigned imm) | |
7627 | { | |
7628 | return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); | |
7629 | } | |
7630 | ||
7631 | /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into | |
7632 | the instruction. *OP is passed as the initial value of the op field, and | |
7633 | may be set to a different value depending on the constant (i.e. | |
7634 | "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not | |
7635 | MVN). If the immediate looks like a repeated pattern then also | |
7636 | try smaller element sizes. */ | |
7637 | ||
7638 | static int | |
7639 | neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, | |
7640 | unsigned *immbits, int *op, int size, | |
7641 | enum neon_el_type type) | |
7642 | { | |
7643 | /* Only permit float immediates (including 0.0/-0.0) if the operand type is | |
7644 | float. */ | |
7645 | if (type == NT_float && !float_p) | |
7646 | return FAIL; | |
7647 | ||
7648 | if (type == NT_float && is_quarter_float (immlo) && immhi == 0) | |
09d92015 | 7649 | { |
8335d6aa JW |
7650 | if (size != 32 || *op == 1) |
7651 | return FAIL; | |
7652 | *immbits = neon_qfloat_bits (immlo); | |
7653 | return 0xf; | |
7654 | } | |
7655 | ||
7656 | if (size == 64) | |
7657 | { | |
7658 | if (neon_bits_same_in_bytes (immhi) | |
7659 | && neon_bits_same_in_bytes (immlo)) | |
c19d1205 | 7660 | { |
8335d6aa JW |
7661 | if (*op == 1) |
7662 | return FAIL; | |
7663 | *immbits = (neon_squash_bits (immhi) << 4) | |
7664 | | neon_squash_bits (immlo); | |
7665 | *op = 1; | |
7666 | return 0xe; | |
c19d1205 | 7667 | } |
a737bd4d | 7668 | |
8335d6aa JW |
7669 | if (immhi != immlo) |
7670 | return FAIL; | |
7671 | } | |
a737bd4d | 7672 | |
8335d6aa | 7673 | if (size >= 32) |
09d92015 | 7674 | { |
8335d6aa | 7675 | if (immlo == (immlo & 0x000000ff)) |
c19d1205 | 7676 | { |
8335d6aa JW |
7677 | *immbits = immlo; |
7678 | return 0x0; | |
c19d1205 | 7679 | } |
8335d6aa | 7680 | else if (immlo == (immlo & 0x0000ff00)) |
c19d1205 | 7681 | { |
8335d6aa JW |
7682 | *immbits = immlo >> 8; |
7683 | return 0x2; | |
c19d1205 | 7684 | } |
8335d6aa JW |
7685 | else if (immlo == (immlo & 0x00ff0000)) |
7686 | { | |
7687 | *immbits = immlo >> 16; | |
7688 | return 0x4; | |
7689 | } | |
7690 | else if (immlo == (immlo & 0xff000000)) | |
7691 | { | |
7692 | *immbits = immlo >> 24; | |
7693 | return 0x6; | |
7694 | } | |
7695 | else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) | |
7696 | { | |
7697 | *immbits = (immlo >> 8) & 0xff; | |
7698 | return 0xc; | |
7699 | } | |
7700 | else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) | |
7701 | { | |
7702 | *immbits = (immlo >> 16) & 0xff; | |
7703 | return 0xd; | |
7704 | } | |
7705 | ||
7706 | if ((immlo & 0xffff) != (immlo >> 16)) | |
7707 | return FAIL; | |
7708 | immlo &= 0xffff; | |
09d92015 | 7709 | } |
a737bd4d | 7710 | |
8335d6aa | 7711 | if (size >= 16) |
4962c51a | 7712 | { |
8335d6aa JW |
7713 | if (immlo == (immlo & 0x000000ff)) |
7714 | { | |
7715 | *immbits = immlo; | |
7716 | return 0x8; | |
7717 | } | |
7718 | else if (immlo == (immlo & 0x0000ff00)) | |
7719 | { | |
7720 | *immbits = immlo >> 8; | |
7721 | return 0xa; | |
7722 | } | |
7723 | ||
7724 | if ((immlo & 0xff) != (immlo >> 8)) | |
7725 | return FAIL; | |
7726 | immlo &= 0xff; | |
4962c51a MS |
7727 | } |
7728 | ||
8335d6aa JW |
7729 | if (immlo == (immlo & 0x000000ff)) |
7730 | { | |
7731 | /* Don't allow MVN with 8-bit immediate. */ | |
7732 | if (*op == 1) | |
7733 | return FAIL; | |
7734 | *immbits = immlo; | |
7735 | return 0xe; | |
7736 | } | |
26d97720 | 7737 | |
8335d6aa | 7738 | return FAIL; |
c19d1205 | 7739 | } |
a737bd4d | 7740 | |
8335d6aa JW |
7741 | enum lit_type |
7742 | { | |
7743 | CONST_THUMB, | |
7744 | CONST_ARM, | |
7745 | CONST_VEC | |
7746 | }; | |
7747 | ||
c19d1205 ZW |
7748 | /* inst.reloc.exp describes an "=expr" load pseudo-operation. |
7749 | Determine whether it can be performed with a move instruction; if | |
7750 | it can, convert inst.instruction to that move instruction and | |
c921be7d NC |
7751 | return TRUE; if it can't, convert inst.instruction to a literal-pool |
7752 | load and return FALSE. If this is not a valid thing to do in the | |
7753 | current context, set inst.error and return TRUE. | |
a737bd4d | 7754 | |
c19d1205 ZW |
7755 | inst.operands[i] describes the destination register. */ |
7756 | ||
c921be7d | 7757 | static bfd_boolean |
8335d6aa | 7758 | move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3) |
c19d1205 | 7759 | { |
53365c0d | 7760 | unsigned long tbit; |
8335d6aa JW |
7761 | bfd_boolean thumb_p = (t == CONST_THUMB); |
7762 | bfd_boolean arm_p = (t == CONST_ARM); | |
7763 | bfd_boolean vec64_p = (t == CONST_VEC) && !inst.operands[i].issingle; | |
53365c0d PB |
7764 | |
7765 | if (thumb_p) | |
7766 | tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; | |
7767 | else | |
7768 | tbit = LOAD_BIT; | |
7769 | ||
7770 | if ((inst.instruction & tbit) == 0) | |
09d92015 | 7771 | { |
c19d1205 | 7772 | inst.error = _("invalid pseudo operation"); |
c921be7d | 7773 | return TRUE; |
09d92015 | 7774 | } |
8335d6aa JW |
7775 | if (inst.reloc.exp.X_op != O_constant |
7776 | && inst.reloc.exp.X_op != O_symbol | |
7777 | && inst.reloc.exp.X_op != O_big) | |
09d92015 MM |
7778 | { |
7779 | inst.error = _("constant expression expected"); | |
c921be7d | 7780 | return TRUE; |
09d92015 | 7781 | } |
8335d6aa JW |
7782 | if ((inst.reloc.exp.X_op == O_constant |
7783 | || inst.reloc.exp.X_op == O_big) | |
7784 | && !inst.operands[i].issingle) | |
7785 | { | |
7786 | if (thumb_p && inst.reloc.exp.X_op == O_constant) | |
7787 | { | |
7788 | if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) | |
7789 | { | |
7790 | /* This can be done with a mov(1) instruction. */ | |
7791 | inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); | |
7792 | inst.instruction |= inst.reloc.exp.X_add_number; | |
7793 | return TRUE; | |
7794 | } | |
7795 | } | |
7796 | else if (arm_p && inst.reloc.exp.X_op == O_constant) | |
7797 | { | |
7798 | int value = encode_arm_immediate (inst.reloc.exp.X_add_number); | |
7799 | if (value != FAIL) | |
7800 | { | |
7801 | /* This can be done with a mov instruction. */ | |
7802 | inst.instruction &= LITERAL_MASK; | |
7803 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
7804 | inst.instruction |= value & 0xfff; | |
7805 | return TRUE; | |
7806 | } | |
7807 | ||
7808 | value = encode_arm_immediate (~inst.reloc.exp.X_add_number); | |
7809 | if (value != FAIL) | |
7810 | { | |
7811 | /* This can be done with a mvn instruction. */ | |
7812 | inst.instruction &= LITERAL_MASK; | |
7813 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
7814 | inst.instruction |= value & 0xfff; | |
7815 | return TRUE; | |
7816 | } | |
7817 | } | |
7818 | else if (vec64_p) | |
7819 | { | |
7820 | int op = 0; | |
7821 | unsigned immbits = 0; | |
7822 | unsigned immlo = inst.operands[1].imm; | |
7823 | unsigned immhi = inst.operands[1].regisimm | |
7824 | ? inst.operands[1].reg | |
7825 | : inst.reloc.exp.X_unsigned | |
7826 | ? 0 | |
2569ceb0 | 7827 | : ((bfd_int64_t)((int) immlo)) >> 32; |
8335d6aa JW |
7828 | int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits, |
7829 | &op, 64, NT_invtype); | |
7830 | ||
7831 | if (cmode == FAIL) | |
7832 | { | |
7833 | neon_invert_size (&immlo, &immhi, 64); | |
7834 | op = !op; | |
7835 | cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits, | |
7836 | &op, 64, NT_invtype); | |
7837 | } | |
7838 | if (cmode != FAIL) | |
7839 | { | |
7840 | inst.instruction = (inst.instruction & VLDR_VMOV_SAME) | |
7841 | | (1 << 23) | |
7842 | | (cmode << 8) | |
7843 | | (op << 5) | |
7844 | | (1 << 4); | |
7845 | /* Fill other bits in vmov encoding for both thumb and arm. */ | |
7846 | if (thumb_mode) | |
7847 | inst.instruction |= (0x7 << 29) | (0xF << 24); | |
7848 | else | |
7849 | inst.instruction |= (0xF << 28) | (0x1 << 25); | |
7850 | neon_write_immbits (immbits); | |
7851 | return TRUE; | |
7852 | } | |
7853 | } | |
7854 | } | |
7855 | ||
7856 | if (add_to_lit_pool ((!inst.operands[i].isvec | |
7857 | || inst.operands[i].issingle) ? 4 : 8) == FAIL) | |
7858 | return TRUE; | |
7859 | ||
7860 | inst.operands[1].reg = REG_PC; | |
7861 | inst.operands[1].isreg = 1; | |
7862 | inst.operands[1].preind = 1; | |
7863 | inst.reloc.pc_rel = 1; | |
7864 | inst.reloc.type = (thumb_p | |
7865 | ? BFD_RELOC_ARM_THUMB_OFFSET | |
7866 | : (mode_3 | |
7867 | ? BFD_RELOC_ARM_HWLITERAL | |
7868 | : BFD_RELOC_ARM_LITERAL)); | |
7869 | return FALSE; | |
7870 | } | |
7871 | ||
7872 | /* inst.operands[i] was set up by parse_address. Encode it into an | |
7873 | ARM-format instruction. Reject all forms which cannot be encoded | |
7874 | into a coprocessor load/store instruction. If wb_ok is false, | |
7875 | reject use of writeback; if unind_ok is false, reject use of | |
7876 | unindexed addressing. If reloc_override is not 0, use it instead | |
7877 | of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one | |
7878 | (in which case it is preserved). */ | |
7879 | ||
7880 | static int | |
7881 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
7882 | { | |
7883 | if (!inst.operands[i].isreg) | |
7884 | { | |
7885 | gas_assert (inst.operands[0].isvec); | |
7886 | if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE)) | |
7887 | return SUCCESS; | |
7888 | } | |
7889 | ||
7890 | inst.instruction |= inst.operands[i].reg << 16; | |
7891 | ||
7892 | gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); | |
7893 | ||
7894 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ | |
7895 | { | |
7896 | gas_assert (!inst.operands[i].writeback); | |
7897 | if (!unind_ok) | |
7898 | { | |
7899 | inst.error = _("instruction does not support unindexed addressing"); | |
7900 | return FAIL; | |
7901 | } | |
7902 | inst.instruction |= inst.operands[i].imm; | |
7903 | inst.instruction |= INDEX_UP; | |
7904 | return SUCCESS; | |
7905 | } | |
7906 | ||
7907 | if (inst.operands[i].preind) | |
7908 | inst.instruction |= PRE_INDEX; | |
7909 | ||
7910 | if (inst.operands[i].writeback) | |
09d92015 | 7911 | { |
8335d6aa | 7912 | if (inst.operands[i].reg == REG_PC) |
c19d1205 | 7913 | { |
8335d6aa JW |
7914 | inst.error = _("pc may not be used with write-back"); |
7915 | return FAIL; | |
c19d1205 | 7916 | } |
8335d6aa | 7917 | if (!wb_ok) |
c19d1205 | 7918 | { |
8335d6aa JW |
7919 | inst.error = _("instruction does not support writeback"); |
7920 | return FAIL; | |
c19d1205 | 7921 | } |
8335d6aa | 7922 | inst.instruction |= WRITE_BACK; |
09d92015 MM |
7923 | } |
7924 | ||
8335d6aa JW |
7925 | if (reloc_override) |
7926 | inst.reloc.type = (bfd_reloc_code_real_type) reloc_override; | |
7927 | else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC | |
7928 | || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) | |
7929 | && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) | |
c19d1205 | 7930 | { |
8335d6aa JW |
7931 | if (thumb_mode) |
7932 | inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; | |
7933 | else | |
7934 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; | |
c19d1205 | 7935 | } |
8335d6aa JW |
7936 | |
7937 | /* Prefer + for zero encoded value. */ | |
7938 | if (!inst.operands[i].negative) | |
7939 | inst.instruction |= INDEX_UP; | |
7940 | ||
7941 | return SUCCESS; | |
09d92015 MM |
7942 | } |
7943 | ||
5f4273c7 | 7944 | /* Functions for instruction encoding, sorted by sub-architecture. |
c19d1205 ZW |
7945 | First some generics; their names are taken from the conventional |
7946 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 7947 | |
a737bd4d | 7948 | static void |
c19d1205 | 7949 | do_noargs (void) |
09d92015 | 7950 | { |
c19d1205 | 7951 | } |
a737bd4d | 7952 | |
c19d1205 ZW |
7953 | static void |
7954 | do_rd (void) | |
7955 | { | |
7956 | inst.instruction |= inst.operands[0].reg << 12; | |
7957 | } | |
a737bd4d | 7958 | |
c19d1205 ZW |
7959 | static void |
7960 | do_rd_rm (void) | |
7961 | { | |
7962 | inst.instruction |= inst.operands[0].reg << 12; | |
7963 | inst.instruction |= inst.operands[1].reg; | |
7964 | } | |
09d92015 | 7965 | |
9eb6c0f1 MGD |
7966 | static void |
7967 | do_rm_rn (void) | |
7968 | { | |
7969 | inst.instruction |= inst.operands[0].reg; | |
7970 | inst.instruction |= inst.operands[1].reg << 16; | |
7971 | } | |
7972 | ||
c19d1205 ZW |
7973 | static void |
7974 | do_rd_rn (void) | |
7975 | { | |
7976 | inst.instruction |= inst.operands[0].reg << 12; | |
7977 | inst.instruction |= inst.operands[1].reg << 16; | |
7978 | } | |
a737bd4d | 7979 | |
c19d1205 ZW |
7980 | static void |
7981 | do_rn_rd (void) | |
7982 | { | |
7983 | inst.instruction |= inst.operands[0].reg << 16; | |
7984 | inst.instruction |= inst.operands[1].reg << 12; | |
7985 | } | |
09d92015 | 7986 | |
59d09be6 MGD |
7987 | static bfd_boolean |
7988 | check_obsolete (const arm_feature_set *feature, const char *msg) | |
7989 | { | |
7990 | if (ARM_CPU_IS_ANY (cpu_variant)) | |
7991 | { | |
5c3696f8 | 7992 | as_tsktsk ("%s", msg); |
59d09be6 MGD |
7993 | return TRUE; |
7994 | } | |
7995 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature)) | |
7996 | { | |
7997 | as_bad ("%s", msg); | |
7998 | return TRUE; | |
7999 | } | |
8000 | ||
8001 | return FALSE; | |
8002 | } | |
8003 | ||
c19d1205 ZW |
8004 | static void |
8005 | do_rd_rm_rn (void) | |
8006 | { | |
9a64e435 | 8007 | unsigned Rn = inst.operands[2].reg; |
708587a4 | 8008 | /* Enforce restrictions on SWP instruction. */ |
9a64e435 | 8009 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) |
56adecf4 DG |
8010 | { |
8011 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
8012 | _("Rn must not overlap other operands")); | |
8013 | ||
59d09be6 MGD |
8014 | /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7. |
8015 | */ | |
8016 | if (!check_obsolete (&arm_ext_v8, | |
8017 | _("swp{b} use is obsoleted for ARMv8 and later")) | |
8018 | && warn_on_deprecated | |
8019 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6)) | |
5c3696f8 | 8020 | as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7")); |
56adecf4 | 8021 | } |
59d09be6 | 8022 | |
c19d1205 ZW |
8023 | inst.instruction |= inst.operands[0].reg << 12; |
8024 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 8025 | inst.instruction |= Rn << 16; |
c19d1205 | 8026 | } |
09d92015 | 8027 | |
c19d1205 ZW |
8028 | static void |
8029 | do_rd_rn_rm (void) | |
8030 | { | |
8031 | inst.instruction |= inst.operands[0].reg << 12; | |
8032 | inst.instruction |= inst.operands[1].reg << 16; | |
8033 | inst.instruction |= inst.operands[2].reg; | |
8034 | } | |
a737bd4d | 8035 | |
c19d1205 ZW |
8036 | static void |
8037 | do_rm_rd_rn (void) | |
8038 | { | |
5be8be5d DG |
8039 | constraint ((inst.operands[2].reg == REG_PC), BAD_PC); |
8040 | constraint (((inst.reloc.exp.X_op != O_constant | |
8041 | && inst.reloc.exp.X_op != O_illegal) | |
8042 | || inst.reloc.exp.X_add_number != 0), | |
8043 | BAD_ADDR_MODE); | |
c19d1205 ZW |
8044 | inst.instruction |= inst.operands[0].reg; |
8045 | inst.instruction |= inst.operands[1].reg << 12; | |
8046 | inst.instruction |= inst.operands[2].reg << 16; | |
8047 | } | |
09d92015 | 8048 | |
c19d1205 ZW |
8049 | static void |
8050 | do_imm0 (void) | |
8051 | { | |
8052 | inst.instruction |= inst.operands[0].imm; | |
8053 | } | |
09d92015 | 8054 | |
c19d1205 ZW |
8055 | static void |
8056 | do_rd_cpaddr (void) | |
8057 | { | |
8058 | inst.instruction |= inst.operands[0].reg << 12; | |
8059 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 8060 | } |
a737bd4d | 8061 | |
c19d1205 ZW |
8062 | /* ARM instructions, in alphabetical order by function name (except |
8063 | that wrapper functions appear immediately after the function they | |
8064 | wrap). */ | |
09d92015 | 8065 | |
c19d1205 ZW |
8066 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
8067 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
8068 | |
8069 | static void | |
c19d1205 | 8070 | do_adr (void) |
09d92015 | 8071 | { |
c19d1205 | 8072 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 8073 | |
c19d1205 ZW |
8074 | /* Frag hacking will turn this into a sub instruction if the offset turns |
8075 | out to be negative. */ | |
8076 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
c19d1205 | 8077 | inst.reloc.pc_rel = 1; |
2fc8bdac | 8078 | inst.reloc.exp.X_add_number -= 8; |
c19d1205 | 8079 | } |
b99bd4ef | 8080 | |
c19d1205 ZW |
8081 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
8082 | into a relative address of the form: | |
8083 | add rd, pc, #low(label-.-8)" | |
8084 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 8085 | |
c19d1205 ZW |
8086 | static void |
8087 | do_adrl (void) | |
8088 | { | |
8089 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 8090 | |
c19d1205 ZW |
8091 | /* Frag hacking will turn this into a sub instruction if the offset turns |
8092 | out to be negative. */ | |
8093 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
c19d1205 ZW |
8094 | inst.reloc.pc_rel = 1; |
8095 | inst.size = INSN_SIZE * 2; | |
2fc8bdac | 8096 | inst.reloc.exp.X_add_number -= 8; |
b99bd4ef NC |
8097 | } |
8098 | ||
b99bd4ef | 8099 | static void |
c19d1205 | 8100 | do_arit (void) |
b99bd4ef | 8101 | { |
c19d1205 ZW |
8102 | if (!inst.operands[1].present) |
8103 | inst.operands[1].reg = inst.operands[0].reg; | |
8104 | inst.instruction |= inst.operands[0].reg << 12; | |
8105 | inst.instruction |= inst.operands[1].reg << 16; | |
8106 | encode_arm_shifter_operand (2); | |
8107 | } | |
b99bd4ef | 8108 | |
62b3e311 PB |
8109 | static void |
8110 | do_barrier (void) | |
8111 | { | |
8112 | if (inst.operands[0].present) | |
ccb84d65 | 8113 | inst.instruction |= inst.operands[0].imm; |
62b3e311 PB |
8114 | else |
8115 | inst.instruction |= 0xf; | |
8116 | } | |
8117 | ||
c19d1205 ZW |
8118 | static void |
8119 | do_bfc (void) | |
8120 | { | |
8121 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
8122 | constraint (msb > 32, _("bit-field extends past end of register")); | |
8123 | /* The instruction encoding stores the LSB and MSB, | |
8124 | not the LSB and width. */ | |
8125 | inst.instruction |= inst.operands[0].reg << 12; | |
8126 | inst.instruction |= inst.operands[1].imm << 7; | |
8127 | inst.instruction |= (msb - 1) << 16; | |
8128 | } | |
b99bd4ef | 8129 | |
c19d1205 ZW |
8130 | static void |
8131 | do_bfi (void) | |
8132 | { | |
8133 | unsigned int msb; | |
b99bd4ef | 8134 | |
c19d1205 ZW |
8135 | /* #0 in second position is alternative syntax for bfc, which is |
8136 | the same instruction but with REG_PC in the Rm field. */ | |
8137 | if (!inst.operands[1].isreg) | |
8138 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 8139 | |
c19d1205 ZW |
8140 | msb = inst.operands[2].imm + inst.operands[3].imm; |
8141 | constraint (msb > 32, _("bit-field extends past end of register")); | |
8142 | /* The instruction encoding stores the LSB and MSB, | |
8143 | not the LSB and width. */ | |
8144 | inst.instruction |= inst.operands[0].reg << 12; | |
8145 | inst.instruction |= inst.operands[1].reg; | |
8146 | inst.instruction |= inst.operands[2].imm << 7; | |
8147 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
8148 | } |
8149 | ||
b99bd4ef | 8150 | static void |
c19d1205 | 8151 | do_bfx (void) |
b99bd4ef | 8152 | { |
c19d1205 ZW |
8153 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
8154 | _("bit-field extends past end of register")); | |
8155 | inst.instruction |= inst.operands[0].reg << 12; | |
8156 | inst.instruction |= inst.operands[1].reg; | |
8157 | inst.instruction |= inst.operands[2].imm << 7; | |
8158 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
8159 | } | |
09d92015 | 8160 | |
c19d1205 ZW |
8161 | /* ARM V5 breakpoint instruction (argument parse) |
8162 | BKPT <16 bit unsigned immediate> | |
8163 | Instruction is not conditional. | |
8164 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
8165 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 8166 | |
c19d1205 ZW |
8167 | static void |
8168 | do_bkpt (void) | |
8169 | { | |
8170 | /* Top 12 of 16 bits to bits 19:8. */ | |
8171 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 8172 | |
c19d1205 ZW |
8173 | /* Bottom 4 of 16 bits to bits 3:0. */ |
8174 | inst.instruction |= inst.operands[0].imm & 0xf; | |
8175 | } | |
09d92015 | 8176 | |
c19d1205 ZW |
8177 | static void |
8178 | encode_branch (int default_reloc) | |
8179 | { | |
8180 | if (inst.operands[0].hasreloc) | |
8181 | { | |
0855e32b NS |
8182 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32 |
8183 | && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL, | |
8184 | _("the only valid suffixes here are '(plt)' and '(tlscall)'")); | |
8185 | inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32 | |
8186 | ? BFD_RELOC_ARM_PLT32 | |
8187 | : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL; | |
c19d1205 | 8188 | } |
b99bd4ef | 8189 | else |
9ae92b05 | 8190 | inst.reloc.type = (bfd_reloc_code_real_type) default_reloc; |
2fc8bdac | 8191 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
8192 | } |
8193 | ||
b99bd4ef | 8194 | static void |
c19d1205 | 8195 | do_branch (void) |
b99bd4ef | 8196 | { |
39b41c9c PB |
8197 | #ifdef OBJ_ELF |
8198 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
8199 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
8200 | else | |
8201 | #endif | |
8202 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
8203 | } | |
8204 | ||
8205 | static void | |
8206 | do_bl (void) | |
8207 | { | |
8208 | #ifdef OBJ_ELF | |
8209 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
8210 | { | |
8211 | if (inst.cond == COND_ALWAYS) | |
8212 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
8213 | else | |
8214 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
8215 | } | |
8216 | else | |
8217 | #endif | |
8218 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
c19d1205 | 8219 | } |
b99bd4ef | 8220 | |
c19d1205 ZW |
8221 | /* ARM V5 branch-link-exchange instruction (argument parse) |
8222 | BLX <target_addr> ie BLX(1) | |
8223 | BLX{<condition>} <Rm> ie BLX(2) | |
8224 | Unfortunately, there are two different opcodes for this mnemonic. | |
8225 | So, the insns[].value is not used, and the code here zaps values | |
8226 | into inst.instruction. | |
8227 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 8228 | |
c19d1205 ZW |
8229 | static void |
8230 | do_blx (void) | |
8231 | { | |
8232 | if (inst.operands[0].isreg) | |
b99bd4ef | 8233 | { |
c19d1205 ZW |
8234 | /* Arg is a register; the opcode provided by insns[] is correct. |
8235 | It is not illegal to do "blx pc", just useless. */ | |
8236 | if (inst.operands[0].reg == REG_PC) | |
8237 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 8238 | |
c19d1205 ZW |
8239 | inst.instruction |= inst.operands[0].reg; |
8240 | } | |
8241 | else | |
b99bd4ef | 8242 | { |
c19d1205 | 8243 | /* Arg is an address; this instruction cannot be executed |
267bf995 RR |
8244 | conditionally, and the opcode must be adjusted. |
8245 | We retain the BFD_RELOC_ARM_PCREL_BLX till the very end | |
8246 | where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */ | |
c19d1205 | 8247 | constraint (inst.cond != COND_ALWAYS, BAD_COND); |
2fc8bdac | 8248 | inst.instruction = 0xfa000000; |
267bf995 | 8249 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); |
b99bd4ef | 8250 | } |
c19d1205 ZW |
8251 | } |
8252 | ||
8253 | static void | |
8254 | do_bx (void) | |
8255 | { | |
845b51d6 PB |
8256 | bfd_boolean want_reloc; |
8257 | ||
c19d1205 ZW |
8258 | if (inst.operands[0].reg == REG_PC) |
8259 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 8260 | |
c19d1205 | 8261 | inst.instruction |= inst.operands[0].reg; |
845b51d6 PB |
8262 | /* Output R_ARM_V4BX relocations if is an EABI object that looks like |
8263 | it is for ARMv4t or earlier. */ | |
8264 | want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5); | |
8265 | if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5)) | |
8266 | want_reloc = TRUE; | |
8267 | ||
5ad34203 | 8268 | #ifdef OBJ_ELF |
845b51d6 | 8269 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
5ad34203 | 8270 | #endif |
584206db | 8271 | want_reloc = FALSE; |
845b51d6 PB |
8272 | |
8273 | if (want_reloc) | |
8274 | inst.reloc.type = BFD_RELOC_ARM_V4BX; | |
09d92015 MM |
8275 | } |
8276 | ||
c19d1205 ZW |
8277 | |
8278 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
8279 | |
8280 | static void | |
c19d1205 | 8281 | do_bxj (void) |
a737bd4d | 8282 | { |
c19d1205 ZW |
8283 | if (inst.operands[0].reg == REG_PC) |
8284 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
8285 | ||
8286 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
8287 | } |
8288 | ||
c19d1205 ZW |
8289 | /* Co-processor data operation: |
8290 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
8291 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
8292 | static void | |
8293 | do_cdp (void) | |
8294 | { | |
8295 | inst.instruction |= inst.operands[0].reg << 8; | |
8296 | inst.instruction |= inst.operands[1].imm << 20; | |
8297 | inst.instruction |= inst.operands[2].reg << 12; | |
8298 | inst.instruction |= inst.operands[3].reg << 16; | |
8299 | inst.instruction |= inst.operands[4].reg; | |
8300 | inst.instruction |= inst.operands[5].imm << 5; | |
8301 | } | |
a737bd4d NC |
8302 | |
8303 | static void | |
c19d1205 | 8304 | do_cmp (void) |
a737bd4d | 8305 | { |
c19d1205 ZW |
8306 | inst.instruction |= inst.operands[0].reg << 16; |
8307 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
8308 | } |
8309 | ||
c19d1205 ZW |
8310 | /* Transfer between coprocessor and ARM registers. |
8311 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
8312 | MRC2 | |
8313 | MCR{cond} | |
8314 | MCR2 | |
8315 | ||
8316 | No special properties. */ | |
09d92015 | 8317 | |
dcbd0d71 MGD |
8318 | struct deprecated_coproc_regs_s |
8319 | { | |
8320 | unsigned cp; | |
8321 | int opc1; | |
8322 | unsigned crn; | |
8323 | unsigned crm; | |
8324 | int opc2; | |
8325 | arm_feature_set deprecated; | |
8326 | arm_feature_set obsoleted; | |
8327 | const char *dep_msg; | |
8328 | const char *obs_msg; | |
8329 | }; | |
8330 | ||
8331 | #define DEPR_ACCESS_V8 \ | |
8332 | N_("This coprocessor register access is deprecated in ARMv8") | |
8333 | ||
8334 | /* Table of all deprecated coprocessor registers. */ | |
8335 | static struct deprecated_coproc_regs_s deprecated_coproc_regs[] = | |
8336 | { | |
8337 | {15, 0, 7, 10, 5, /* CP15DMB. */ | |
8338 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
8339 | DEPR_ACCESS_V8, NULL}, | |
8340 | {15, 0, 7, 10, 4, /* CP15DSB. */ | |
8341 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
8342 | DEPR_ACCESS_V8, NULL}, | |
8343 | {15, 0, 7, 5, 4, /* CP15ISB. */ | |
8344 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
8345 | DEPR_ACCESS_V8, NULL}, | |
8346 | {14, 6, 1, 0, 0, /* TEEHBR. */ | |
8347 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
8348 | DEPR_ACCESS_V8, NULL}, | |
8349 | {14, 6, 0, 0, 0, /* TEECR. */ | |
8350 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
8351 | DEPR_ACCESS_V8, NULL}, | |
8352 | }; | |
8353 | ||
8354 | #undef DEPR_ACCESS_V8 | |
8355 | ||
8356 | static const size_t deprecated_coproc_reg_count = | |
8357 | sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]); | |
8358 | ||
09d92015 | 8359 | static void |
c19d1205 | 8360 | do_co_reg (void) |
09d92015 | 8361 | { |
fdfde340 | 8362 | unsigned Rd; |
dcbd0d71 | 8363 | size_t i; |
fdfde340 JM |
8364 | |
8365 | Rd = inst.operands[2].reg; | |
8366 | if (thumb_mode) | |
8367 | { | |
8368 | if (inst.instruction == 0xee000010 | |
8369 | || inst.instruction == 0xfe000010) | |
8370 | /* MCR, MCR2 */ | |
8371 | reject_bad_reg (Rd); | |
8372 | else | |
8373 | /* MRC, MRC2 */ | |
8374 | constraint (Rd == REG_SP, BAD_SP); | |
8375 | } | |
8376 | else | |
8377 | { | |
8378 | /* MCR */ | |
8379 | if (inst.instruction == 0xe000010) | |
8380 | constraint (Rd == REG_PC, BAD_PC); | |
8381 | } | |
8382 | ||
dcbd0d71 MGD |
8383 | for (i = 0; i < deprecated_coproc_reg_count; ++i) |
8384 | { | |
8385 | const struct deprecated_coproc_regs_s *r = | |
8386 | deprecated_coproc_regs + i; | |
8387 | ||
8388 | if (inst.operands[0].reg == r->cp | |
8389 | && inst.operands[1].imm == r->opc1 | |
8390 | && inst.operands[3].reg == r->crn | |
8391 | && inst.operands[4].reg == r->crm | |
8392 | && inst.operands[5].imm == r->opc2) | |
8393 | { | |
b10bf8c5 | 8394 | if (! ARM_CPU_IS_ANY (cpu_variant) |
477330fc | 8395 | && warn_on_deprecated |
dcbd0d71 | 8396 | && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated)) |
5c3696f8 | 8397 | as_tsktsk ("%s", r->dep_msg); |
dcbd0d71 MGD |
8398 | } |
8399 | } | |
fdfde340 | 8400 | |
c19d1205 ZW |
8401 | inst.instruction |= inst.operands[0].reg << 8; |
8402 | inst.instruction |= inst.operands[1].imm << 21; | |
fdfde340 | 8403 | inst.instruction |= Rd << 12; |
c19d1205 ZW |
8404 | inst.instruction |= inst.operands[3].reg << 16; |
8405 | inst.instruction |= inst.operands[4].reg; | |
8406 | inst.instruction |= inst.operands[5].imm << 5; | |
8407 | } | |
09d92015 | 8408 | |
c19d1205 ZW |
8409 | /* Transfer between coprocessor register and pair of ARM registers. |
8410 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
8411 | MCRR2 | |
8412 | MRRC{cond} | |
8413 | MRRC2 | |
b99bd4ef | 8414 | |
c19d1205 | 8415 | Two XScale instructions are special cases of these: |
09d92015 | 8416 | |
c19d1205 ZW |
8417 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
8418 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 8419 | |
5f4273c7 | 8420 | Result unpredictable if Rd or Rn is R15. */ |
a737bd4d | 8421 | |
c19d1205 ZW |
8422 | static void |
8423 | do_co_reg2c (void) | |
8424 | { | |
fdfde340 JM |
8425 | unsigned Rd, Rn; |
8426 | ||
8427 | Rd = inst.operands[2].reg; | |
8428 | Rn = inst.operands[3].reg; | |
8429 | ||
8430 | if (thumb_mode) | |
8431 | { | |
8432 | reject_bad_reg (Rd); | |
8433 | reject_bad_reg (Rn); | |
8434 | } | |
8435 | else | |
8436 | { | |
8437 | constraint (Rd == REG_PC, BAD_PC); | |
8438 | constraint (Rn == REG_PC, BAD_PC); | |
8439 | } | |
8440 | ||
c19d1205 ZW |
8441 | inst.instruction |= inst.operands[0].reg << 8; |
8442 | inst.instruction |= inst.operands[1].imm << 4; | |
fdfde340 JM |
8443 | inst.instruction |= Rd << 12; |
8444 | inst.instruction |= Rn << 16; | |
c19d1205 | 8445 | inst.instruction |= inst.operands[4].reg; |
b99bd4ef NC |
8446 | } |
8447 | ||
c19d1205 ZW |
8448 | static void |
8449 | do_cpsi (void) | |
8450 | { | |
8451 | inst.instruction |= inst.operands[0].imm << 6; | |
a028a6f5 PB |
8452 | if (inst.operands[1].present) |
8453 | { | |
8454 | inst.instruction |= CPSI_MMOD; | |
8455 | inst.instruction |= inst.operands[1].imm; | |
8456 | } | |
c19d1205 | 8457 | } |
b99bd4ef | 8458 | |
62b3e311 PB |
8459 | static void |
8460 | do_dbg (void) | |
8461 | { | |
8462 | inst.instruction |= inst.operands[0].imm; | |
8463 | } | |
8464 | ||
eea54501 MGD |
8465 | static void |
8466 | do_div (void) | |
8467 | { | |
8468 | unsigned Rd, Rn, Rm; | |
8469 | ||
8470 | Rd = inst.operands[0].reg; | |
8471 | Rn = (inst.operands[1].present | |
8472 | ? inst.operands[1].reg : Rd); | |
8473 | Rm = inst.operands[2].reg; | |
8474 | ||
8475 | constraint ((Rd == REG_PC), BAD_PC); | |
8476 | constraint ((Rn == REG_PC), BAD_PC); | |
8477 | constraint ((Rm == REG_PC), BAD_PC); | |
8478 | ||
8479 | inst.instruction |= Rd << 16; | |
8480 | inst.instruction |= Rn << 0; | |
8481 | inst.instruction |= Rm << 8; | |
8482 | } | |
8483 | ||
b99bd4ef | 8484 | static void |
c19d1205 | 8485 | do_it (void) |
b99bd4ef | 8486 | { |
c19d1205 | 8487 | /* There is no IT instruction in ARM mode. We |
e07e6e58 NC |
8488 | process it to do the validation as if in |
8489 | thumb mode, just in case the code gets | |
8490 | assembled for thumb using the unified syntax. */ | |
8491 | ||
c19d1205 | 8492 | inst.size = 0; |
e07e6e58 NC |
8493 | if (unified_syntax) |
8494 | { | |
8495 | set_it_insn_type (IT_INSN); | |
8496 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
8497 | now_it.cc = inst.operands[0].imm; | |
8498 | } | |
09d92015 | 8499 | } |
b99bd4ef | 8500 | |
6530b175 NC |
8501 | /* If there is only one register in the register list, |
8502 | then return its register number. Otherwise return -1. */ | |
8503 | static int | |
8504 | only_one_reg_in_list (int range) | |
8505 | { | |
8506 | int i = ffs (range) - 1; | |
8507 | return (i > 15 || range != (1 << i)) ? -1 : i; | |
8508 | } | |
8509 | ||
09d92015 | 8510 | static void |
6530b175 | 8511 | encode_ldmstm(int from_push_pop_mnem) |
ea6ef066 | 8512 | { |
c19d1205 ZW |
8513 | int base_reg = inst.operands[0].reg; |
8514 | int range = inst.operands[1].imm; | |
6530b175 | 8515 | int one_reg; |
ea6ef066 | 8516 | |
c19d1205 ZW |
8517 | inst.instruction |= base_reg << 16; |
8518 | inst.instruction |= range; | |
ea6ef066 | 8519 | |
c19d1205 ZW |
8520 | if (inst.operands[1].writeback) |
8521 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 8522 | |
c19d1205 | 8523 | if (inst.operands[0].writeback) |
ea6ef066 | 8524 | { |
c19d1205 ZW |
8525 | inst.instruction |= WRITE_BACK; |
8526 | /* Check for unpredictable uses of writeback. */ | |
8527 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 8528 | { |
c19d1205 ZW |
8529 | /* Not allowed in LDM type 2. */ |
8530 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
8531 | && ((range & (1 << REG_PC)) == 0)) | |
8532 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
8533 | /* Only allowed if base reg not in list for other types. */ | |
8534 | else if (range & (1 << base_reg)) | |
8535 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
8536 | } | |
8537 | else /* STM. */ | |
8538 | { | |
8539 | /* Not allowed for type 2. */ | |
8540 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
8541 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
8542 | /* Only allowed if base reg not in list, or first in list. */ | |
8543 | else if ((range & (1 << base_reg)) | |
8544 | && (range & ((1 << base_reg) - 1))) | |
8545 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 8546 | } |
ea6ef066 | 8547 | } |
6530b175 NC |
8548 | |
8549 | /* If PUSH/POP has only one register, then use the A2 encoding. */ | |
8550 | one_reg = only_one_reg_in_list (range); | |
8551 | if (from_push_pop_mnem && one_reg >= 0) | |
8552 | { | |
8553 | int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH; | |
8554 | ||
8555 | inst.instruction &= A_COND_MASK; | |
8556 | inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP; | |
8557 | inst.instruction |= one_reg << 12; | |
8558 | } | |
8559 | } | |
8560 | ||
8561 | static void | |
8562 | do_ldmstm (void) | |
8563 | { | |
8564 | encode_ldmstm (/*from_push_pop_mnem=*/FALSE); | |
a737bd4d NC |
8565 | } |
8566 | ||
c19d1205 ZW |
8567 | /* ARMv5TE load-consecutive (argument parse) |
8568 | Mode is like LDRH. | |
8569 | ||
8570 | LDRccD R, mode | |
8571 | STRccD R, mode. */ | |
8572 | ||
a737bd4d | 8573 | static void |
c19d1205 | 8574 | do_ldrd (void) |
a737bd4d | 8575 | { |
c19d1205 | 8576 | constraint (inst.operands[0].reg % 2 != 0, |
c56791bb | 8577 | _("first transfer register must be even")); |
c19d1205 ZW |
8578 | constraint (inst.operands[1].present |
8579 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
c56791bb | 8580 | _("can only transfer two consecutive registers")); |
c19d1205 ZW |
8581 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); |
8582 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 8583 | |
c19d1205 ZW |
8584 | if (!inst.operands[1].present) |
8585 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
5f4273c7 | 8586 | |
c56791bb RE |
8587 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
8588 | register and the first register written; we have to diagnose | |
8589 | overlap between the base and the second register written here. */ | |
ea6ef066 | 8590 | |
c56791bb RE |
8591 | if (inst.operands[2].reg == inst.operands[1].reg |
8592 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
8593 | as_warn (_("base register written back, and overlaps " | |
8594 | "second transfer register")); | |
b05fe5cf | 8595 | |
c56791bb RE |
8596 | if (!(inst.instruction & V4_STR_BIT)) |
8597 | { | |
c19d1205 | 8598 | /* For an index-register load, the index register must not overlap the |
c56791bb RE |
8599 | destination (even if not write-back). */ |
8600 | if (inst.operands[2].immisreg | |
8601 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg | |
8602 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
8603 | as_warn (_("index register overlaps transfer register")); | |
b05fe5cf | 8604 | } |
c19d1205 ZW |
8605 | inst.instruction |= inst.operands[0].reg << 12; |
8606 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
8607 | } |
8608 | ||
8609 | static void | |
c19d1205 | 8610 | do_ldrex (void) |
b05fe5cf | 8611 | { |
c19d1205 ZW |
8612 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
8613 | || inst.operands[1].postind || inst.operands[1].writeback | |
8614 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
01cfc07f NC |
8615 | || inst.operands[1].negative |
8616 | /* This can arise if the programmer has written | |
8617 | strex rN, rM, foo | |
8618 | or if they have mistakenly used a register name as the last | |
8619 | operand, eg: | |
8620 | strex rN, rM, rX | |
8621 | It is very difficult to distinguish between these two cases | |
8622 | because "rX" might actually be a label. ie the register | |
8623 | name has been occluded by a symbol of the same name. So we | |
8624 | just generate a general 'bad addressing mode' type error | |
8625 | message and leave it up to the programmer to discover the | |
8626 | true cause and fix their mistake. */ | |
8627 | || (inst.operands[1].reg == REG_PC), | |
8628 | BAD_ADDR_MODE); | |
b05fe5cf | 8629 | |
c19d1205 ZW |
8630 | constraint (inst.reloc.exp.X_op != O_constant |
8631 | || inst.reloc.exp.X_add_number != 0, | |
8632 | _("offset must be zero in ARM encoding")); | |
b05fe5cf | 8633 | |
5be8be5d DG |
8634 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
8635 | ||
c19d1205 ZW |
8636 | inst.instruction |= inst.operands[0].reg << 12; |
8637 | inst.instruction |= inst.operands[1].reg << 16; | |
8638 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b05fe5cf ZW |
8639 | } |
8640 | ||
8641 | static void | |
c19d1205 | 8642 | do_ldrexd (void) |
b05fe5cf | 8643 | { |
c19d1205 ZW |
8644 | constraint (inst.operands[0].reg % 2 != 0, |
8645 | _("even register required")); | |
8646 | constraint (inst.operands[1].present | |
8647 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
8648 | _("can only load two consecutive registers")); | |
8649 | /* If op 1 were present and equal to PC, this function wouldn't | |
8650 | have been called in the first place. */ | |
8651 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 8652 | |
c19d1205 ZW |
8653 | inst.instruction |= inst.operands[0].reg << 12; |
8654 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
8655 | } |
8656 | ||
1be5fd2e NC |
8657 | /* In both ARM and thumb state 'ldr pc, #imm' with an immediate |
8658 | which is not a multiple of four is UNPREDICTABLE. */ | |
8659 | static void | |
8660 | check_ldr_r15_aligned (void) | |
8661 | { | |
8662 | constraint (!(inst.operands[1].immisreg) | |
8663 | && (inst.operands[0].reg == REG_PC | |
8664 | && inst.operands[1].reg == REG_PC | |
8665 | && (inst.reloc.exp.X_add_number & 0x3)), | |
8666 | _("ldr to register 15 must be 4-byte alligned")); | |
8667 | } | |
8668 | ||
b05fe5cf | 8669 | static void |
c19d1205 | 8670 | do_ldst (void) |
b05fe5cf | 8671 | { |
c19d1205 ZW |
8672 | inst.instruction |= inst.operands[0].reg << 12; |
8673 | if (!inst.operands[1].isreg) | |
8335d6aa | 8674 | if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE)) |
b05fe5cf | 8675 | return; |
c19d1205 | 8676 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
1be5fd2e | 8677 | check_ldr_r15_aligned (); |
b05fe5cf ZW |
8678 | } |
8679 | ||
8680 | static void | |
c19d1205 | 8681 | do_ldstt (void) |
b05fe5cf | 8682 | { |
c19d1205 ZW |
8683 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
8684 | reject [Rn,...]. */ | |
8685 | if (inst.operands[1].preind) | |
b05fe5cf | 8686 | { |
bd3ba5d1 NC |
8687 | constraint (inst.reloc.exp.X_op != O_constant |
8688 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 8689 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 8690 | |
c19d1205 ZW |
8691 | inst.operands[1].preind = 0; |
8692 | inst.operands[1].postind = 1; | |
8693 | inst.operands[1].writeback = 1; | |
b05fe5cf | 8694 | } |
c19d1205 ZW |
8695 | inst.instruction |= inst.operands[0].reg << 12; |
8696 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
8697 | } | |
b05fe5cf | 8698 | |
c19d1205 | 8699 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 8700 | |
c19d1205 ZW |
8701 | static void |
8702 | do_ldstv4 (void) | |
8703 | { | |
ff4a8d2b | 8704 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 ZW |
8705 | inst.instruction |= inst.operands[0].reg << 12; |
8706 | if (!inst.operands[1].isreg) | |
8335d6aa | 8707 | if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE)) |
b05fe5cf | 8708 | return; |
c19d1205 | 8709 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
8710 | } |
8711 | ||
8712 | static void | |
c19d1205 | 8713 | do_ldsttv4 (void) |
b05fe5cf | 8714 | { |
c19d1205 ZW |
8715 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
8716 | reject [Rn,...]. */ | |
8717 | if (inst.operands[1].preind) | |
b05fe5cf | 8718 | { |
bd3ba5d1 NC |
8719 | constraint (inst.reloc.exp.X_op != O_constant |
8720 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 8721 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 8722 | |
c19d1205 ZW |
8723 | inst.operands[1].preind = 0; |
8724 | inst.operands[1].postind = 1; | |
8725 | inst.operands[1].writeback = 1; | |
b05fe5cf | 8726 | } |
c19d1205 ZW |
8727 | inst.instruction |= inst.operands[0].reg << 12; |
8728 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
8729 | } | |
b05fe5cf | 8730 | |
c19d1205 ZW |
8731 | /* Co-processor register load/store. |
8732 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
8733 | static void | |
8734 | do_lstc (void) | |
8735 | { | |
8736 | inst.instruction |= inst.operands[0].reg << 8; | |
8737 | inst.instruction |= inst.operands[1].reg << 12; | |
8738 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
8739 | } |
8740 | ||
b05fe5cf | 8741 | static void |
c19d1205 | 8742 | do_mlas (void) |
b05fe5cf | 8743 | { |
8fb9d7b9 | 8744 | /* This restriction does not apply to mls (nor to mla in v6 or later). */ |
c19d1205 | 8745 | if (inst.operands[0].reg == inst.operands[1].reg |
8fb9d7b9 | 8746 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) |
c19d1205 | 8747 | && !(inst.instruction & 0x00400000)) |
8fb9d7b9 | 8748 | as_tsktsk (_("Rd and Rm should be different in mla")); |
b05fe5cf | 8749 | |
c19d1205 ZW |
8750 | inst.instruction |= inst.operands[0].reg << 16; |
8751 | inst.instruction |= inst.operands[1].reg; | |
8752 | inst.instruction |= inst.operands[2].reg << 8; | |
8753 | inst.instruction |= inst.operands[3].reg << 12; | |
c19d1205 | 8754 | } |
b05fe5cf | 8755 | |
c19d1205 ZW |
8756 | static void |
8757 | do_mov (void) | |
8758 | { | |
8759 | inst.instruction |= inst.operands[0].reg << 12; | |
8760 | encode_arm_shifter_operand (1); | |
8761 | } | |
b05fe5cf | 8762 | |
c19d1205 ZW |
8763 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
8764 | static void | |
8765 | do_mov16 (void) | |
8766 | { | |
b6895b4f PB |
8767 | bfd_vma imm; |
8768 | bfd_boolean top; | |
8769 | ||
8770 | top = (inst.instruction & 0x00400000) != 0; | |
8771 | constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, | |
8772 | _(":lower16: not allowed this instruction")); | |
8773 | constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, | |
8774 | _(":upper16: not allowed instruction")); | |
c19d1205 | 8775 | inst.instruction |= inst.operands[0].reg << 12; |
b6895b4f PB |
8776 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
8777 | { | |
8778 | imm = inst.reloc.exp.X_add_number; | |
8779 | /* The value is in two pieces: 0:11, 16:19. */ | |
8780 | inst.instruction |= (imm & 0x00000fff); | |
8781 | inst.instruction |= (imm & 0x0000f000) << 4; | |
8782 | } | |
b05fe5cf | 8783 | } |
b99bd4ef | 8784 | |
037e8744 JB |
8785 | static void do_vfp_nsyn_opcode (const char *); |
8786 | ||
8787 | static int | |
8788 | do_vfp_nsyn_mrs (void) | |
8789 | { | |
8790 | if (inst.operands[0].isvec) | |
8791 | { | |
8792 | if (inst.operands[1].reg != 1) | |
477330fc | 8793 | first_error (_("operand 1 must be FPSCR")); |
037e8744 JB |
8794 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); |
8795 | memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); | |
8796 | do_vfp_nsyn_opcode ("fmstat"); | |
8797 | } | |
8798 | else if (inst.operands[1].isvec) | |
8799 | do_vfp_nsyn_opcode ("fmrx"); | |
8800 | else | |
8801 | return FAIL; | |
5f4273c7 | 8802 | |
037e8744 JB |
8803 | return SUCCESS; |
8804 | } | |
8805 | ||
8806 | static int | |
8807 | do_vfp_nsyn_msr (void) | |
8808 | { | |
8809 | if (inst.operands[0].isvec) | |
8810 | do_vfp_nsyn_opcode ("fmxr"); | |
8811 | else | |
8812 | return FAIL; | |
8813 | ||
8814 | return SUCCESS; | |
8815 | } | |
8816 | ||
f7c21dc7 NC |
8817 | static void |
8818 | do_vmrs (void) | |
8819 | { | |
8820 | unsigned Rt = inst.operands[0].reg; | |
fa94de6b | 8821 | |
16d02dc9 | 8822 | if (thumb_mode && Rt == REG_SP) |
f7c21dc7 NC |
8823 | { |
8824 | inst.error = BAD_SP; | |
8825 | return; | |
8826 | } | |
8827 | ||
8828 | /* APSR_ sets isvec. All other refs to PC are illegal. */ | |
16d02dc9 | 8829 | if (!inst.operands[0].isvec && Rt == REG_PC) |
f7c21dc7 NC |
8830 | { |
8831 | inst.error = BAD_PC; | |
8832 | return; | |
8833 | } | |
8834 | ||
16d02dc9 JB |
8835 | /* If we get through parsing the register name, we just insert the number |
8836 | generated into the instruction without further validation. */ | |
8837 | inst.instruction |= (inst.operands[1].reg << 16); | |
f7c21dc7 NC |
8838 | inst.instruction |= (Rt << 12); |
8839 | } | |
8840 | ||
8841 | static void | |
8842 | do_vmsr (void) | |
8843 | { | |
8844 | unsigned Rt = inst.operands[1].reg; | |
fa94de6b | 8845 | |
f7c21dc7 NC |
8846 | if (thumb_mode) |
8847 | reject_bad_reg (Rt); | |
8848 | else if (Rt == REG_PC) | |
8849 | { | |
8850 | inst.error = BAD_PC; | |
8851 | return; | |
8852 | } | |
8853 | ||
16d02dc9 JB |
8854 | /* If we get through parsing the register name, we just insert the number |
8855 | generated into the instruction without further validation. */ | |
8856 | inst.instruction |= (inst.operands[0].reg << 16); | |
f7c21dc7 NC |
8857 | inst.instruction |= (Rt << 12); |
8858 | } | |
8859 | ||
b99bd4ef | 8860 | static void |
c19d1205 | 8861 | do_mrs (void) |
b99bd4ef | 8862 | { |
90ec0d68 MGD |
8863 | unsigned br; |
8864 | ||
037e8744 JB |
8865 | if (do_vfp_nsyn_mrs () == SUCCESS) |
8866 | return; | |
8867 | ||
ff4a8d2b | 8868 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 | 8869 | inst.instruction |= inst.operands[0].reg << 12; |
90ec0d68 MGD |
8870 | |
8871 | if (inst.operands[1].isreg) | |
8872 | { | |
8873 | br = inst.operands[1].reg; | |
8874 | if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000)) | |
8875 | as_bad (_("bad register for mrs")); | |
8876 | } | |
8877 | else | |
8878 | { | |
8879 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ | |
8880 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
8881 | != (PSR_c|PSR_f), | |
d2cd1205 | 8882 | _("'APSR', 'CPSR' or 'SPSR' expected")); |
90ec0d68 MGD |
8883 | br = (15<<16) | (inst.operands[1].imm & SPSR_BIT); |
8884 | } | |
8885 | ||
8886 | inst.instruction |= br; | |
c19d1205 | 8887 | } |
b99bd4ef | 8888 | |
c19d1205 ZW |
8889 | /* Two possible forms: |
8890 | "{C|S}PSR_<field>, Rm", | |
8891 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 8892 | |
c19d1205 ZW |
8893 | static void |
8894 | do_msr (void) | |
8895 | { | |
037e8744 JB |
8896 | if (do_vfp_nsyn_msr () == SUCCESS) |
8897 | return; | |
8898 | ||
c19d1205 ZW |
8899 | inst.instruction |= inst.operands[0].imm; |
8900 | if (inst.operands[1].isreg) | |
8901 | inst.instruction |= inst.operands[1].reg; | |
8902 | else | |
b99bd4ef | 8903 | { |
c19d1205 ZW |
8904 | inst.instruction |= INST_IMMEDIATE; |
8905 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
8906 | inst.reloc.pc_rel = 0; | |
b99bd4ef | 8907 | } |
b99bd4ef NC |
8908 | } |
8909 | ||
c19d1205 ZW |
8910 | static void |
8911 | do_mul (void) | |
a737bd4d | 8912 | { |
ff4a8d2b NC |
8913 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
8914 | ||
c19d1205 ZW |
8915 | if (!inst.operands[2].present) |
8916 | inst.operands[2].reg = inst.operands[0].reg; | |
8917 | inst.instruction |= inst.operands[0].reg << 16; | |
8918 | inst.instruction |= inst.operands[1].reg; | |
8919 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 8920 | |
8fb9d7b9 MS |
8921 | if (inst.operands[0].reg == inst.operands[1].reg |
8922 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
8923 | as_tsktsk (_("Rd and Rm should be different in mul")); | |
a737bd4d NC |
8924 | } |
8925 | ||
c19d1205 ZW |
8926 | /* Long Multiply Parser |
8927 | UMULL RdLo, RdHi, Rm, Rs | |
8928 | SMULL RdLo, RdHi, Rm, Rs | |
8929 | UMLAL RdLo, RdHi, Rm, Rs | |
8930 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
8931 | |
8932 | static void | |
c19d1205 | 8933 | do_mull (void) |
b99bd4ef | 8934 | { |
c19d1205 ZW |
8935 | inst.instruction |= inst.operands[0].reg << 12; |
8936 | inst.instruction |= inst.operands[1].reg << 16; | |
8937 | inst.instruction |= inst.operands[2].reg; | |
8938 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 8939 | |
682b27ad PB |
8940 | /* rdhi and rdlo must be different. */ |
8941 | if (inst.operands[0].reg == inst.operands[1].reg) | |
8942 | as_tsktsk (_("rdhi and rdlo must be different")); | |
8943 | ||
8944 | /* rdhi, rdlo and rm must all be different before armv6. */ | |
8945 | if ((inst.operands[0].reg == inst.operands[2].reg | |
c19d1205 | 8946 | || inst.operands[1].reg == inst.operands[2].reg) |
682b27ad | 8947 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) |
c19d1205 ZW |
8948 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); |
8949 | } | |
b99bd4ef | 8950 | |
c19d1205 ZW |
8951 | static void |
8952 | do_nop (void) | |
8953 | { | |
e7495e45 NS |
8954 | if (inst.operands[0].present |
8955 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k)) | |
c19d1205 ZW |
8956 | { |
8957 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
8958 | inst.instruction &= 0xf0000000; | |
e7495e45 NS |
8959 | inst.instruction |= 0x0320f000; |
8960 | if (inst.operands[0].present) | |
8961 | inst.instruction |= inst.operands[0].imm; | |
c19d1205 | 8962 | } |
b99bd4ef NC |
8963 | } |
8964 | ||
c19d1205 ZW |
8965 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
8966 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
8967 | Condition defaults to COND_ALWAYS. | |
8968 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
8969 | |
8970 | static void | |
c19d1205 | 8971 | do_pkhbt (void) |
b99bd4ef | 8972 | { |
c19d1205 ZW |
8973 | inst.instruction |= inst.operands[0].reg << 12; |
8974 | inst.instruction |= inst.operands[1].reg << 16; | |
8975 | inst.instruction |= inst.operands[2].reg; | |
8976 | if (inst.operands[3].present) | |
8977 | encode_arm_shift (3); | |
8978 | } | |
b99bd4ef | 8979 | |
c19d1205 | 8980 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 8981 | |
c19d1205 ZW |
8982 | static void |
8983 | do_pkhtb (void) | |
8984 | { | |
8985 | if (!inst.operands[3].present) | |
b99bd4ef | 8986 | { |
c19d1205 ZW |
8987 | /* If the shift specifier is omitted, turn the instruction |
8988 | into pkhbt rd, rm, rn. */ | |
8989 | inst.instruction &= 0xfff00010; | |
8990 | inst.instruction |= inst.operands[0].reg << 12; | |
8991 | inst.instruction |= inst.operands[1].reg; | |
8992 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
8993 | } |
8994 | else | |
8995 | { | |
c19d1205 ZW |
8996 | inst.instruction |= inst.operands[0].reg << 12; |
8997 | inst.instruction |= inst.operands[1].reg << 16; | |
8998 | inst.instruction |= inst.operands[2].reg; | |
8999 | encode_arm_shift (3); | |
b99bd4ef NC |
9000 | } |
9001 | } | |
9002 | ||
c19d1205 | 9003 | /* ARMv5TE: Preload-Cache |
60e5ef9f | 9004 | MP Extensions: Preload for write |
c19d1205 | 9005 | |
60e5ef9f | 9006 | PLD(W) <addr_mode> |
c19d1205 ZW |
9007 | |
9008 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
9009 | |
9010 | static void | |
c19d1205 | 9011 | do_pld (void) |
b99bd4ef | 9012 | { |
c19d1205 ZW |
9013 | constraint (!inst.operands[0].isreg, |
9014 | _("'[' expected after PLD mnemonic")); | |
9015 | constraint (inst.operands[0].postind, | |
9016 | _("post-indexed expression used in preload instruction")); | |
9017 | constraint (inst.operands[0].writeback, | |
9018 | _("writeback used in preload instruction")); | |
9019 | constraint (!inst.operands[0].preind, | |
9020 | _("unindexed addressing used in preload instruction")); | |
c19d1205 ZW |
9021 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
9022 | } | |
b99bd4ef | 9023 | |
62b3e311 PB |
9024 | /* ARMv7: PLI <addr_mode> */ |
9025 | static void | |
9026 | do_pli (void) | |
9027 | { | |
9028 | constraint (!inst.operands[0].isreg, | |
9029 | _("'[' expected after PLI mnemonic")); | |
9030 | constraint (inst.operands[0].postind, | |
9031 | _("post-indexed expression used in preload instruction")); | |
9032 | constraint (inst.operands[0].writeback, | |
9033 | _("writeback used in preload instruction")); | |
9034 | constraint (!inst.operands[0].preind, | |
9035 | _("unindexed addressing used in preload instruction")); | |
9036 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
9037 | inst.instruction &= ~PRE_INDEX; | |
9038 | } | |
9039 | ||
c19d1205 ZW |
9040 | static void |
9041 | do_push_pop (void) | |
9042 | { | |
9043 | inst.operands[1] = inst.operands[0]; | |
9044 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
9045 | inst.operands[0].isreg = 1; | |
9046 | inst.operands[0].writeback = 1; | |
9047 | inst.operands[0].reg = REG_SP; | |
6530b175 | 9048 | encode_ldmstm (/*from_push_pop_mnem=*/TRUE); |
c19d1205 | 9049 | } |
b99bd4ef | 9050 | |
c19d1205 ZW |
9051 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
9052 | word at the specified address and the following word | |
9053 | respectively. | |
9054 | Unconditionally executed. | |
9055 | Error if Rn is R15. */ | |
b99bd4ef | 9056 | |
c19d1205 ZW |
9057 | static void |
9058 | do_rfe (void) | |
9059 | { | |
9060 | inst.instruction |= inst.operands[0].reg << 16; | |
9061 | if (inst.operands[0].writeback) | |
9062 | inst.instruction |= WRITE_BACK; | |
9063 | } | |
b99bd4ef | 9064 | |
c19d1205 | 9065 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 9066 | |
c19d1205 ZW |
9067 | static void |
9068 | do_ssat (void) | |
9069 | { | |
9070 | inst.instruction |= inst.operands[0].reg << 12; | |
9071 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
9072 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 9073 | |
c19d1205 ZW |
9074 | if (inst.operands[3].present) |
9075 | encode_arm_shift (3); | |
b99bd4ef NC |
9076 | } |
9077 | ||
c19d1205 | 9078 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
9079 | |
9080 | static void | |
c19d1205 | 9081 | do_usat (void) |
b99bd4ef | 9082 | { |
c19d1205 ZW |
9083 | inst.instruction |= inst.operands[0].reg << 12; |
9084 | inst.instruction |= inst.operands[1].imm << 16; | |
9085 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 9086 | |
c19d1205 ZW |
9087 | if (inst.operands[3].present) |
9088 | encode_arm_shift (3); | |
b99bd4ef NC |
9089 | } |
9090 | ||
c19d1205 | 9091 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
9092 | |
9093 | static void | |
c19d1205 | 9094 | do_ssat16 (void) |
09d92015 | 9095 | { |
c19d1205 ZW |
9096 | inst.instruction |= inst.operands[0].reg << 12; |
9097 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
9098 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
9099 | } |
9100 | ||
c19d1205 ZW |
9101 | static void |
9102 | do_usat16 (void) | |
a737bd4d | 9103 | { |
c19d1205 ZW |
9104 | inst.instruction |= inst.operands[0].reg << 12; |
9105 | inst.instruction |= inst.operands[1].imm << 16; | |
9106 | inst.instruction |= inst.operands[2].reg; | |
9107 | } | |
a737bd4d | 9108 | |
c19d1205 ZW |
9109 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
9110 | preserving the other bits. | |
a737bd4d | 9111 | |
c19d1205 ZW |
9112 | setend <endian_specifier>, where <endian_specifier> is either |
9113 | BE or LE. */ | |
a737bd4d | 9114 | |
c19d1205 ZW |
9115 | static void |
9116 | do_setend (void) | |
9117 | { | |
12e37cbc MGD |
9118 | if (warn_on_deprecated |
9119 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
5c3696f8 | 9120 | as_tsktsk (_("setend use is deprecated for ARMv8")); |
12e37cbc | 9121 | |
c19d1205 ZW |
9122 | if (inst.operands[0].imm) |
9123 | inst.instruction |= 0x200; | |
a737bd4d NC |
9124 | } |
9125 | ||
9126 | static void | |
c19d1205 | 9127 | do_shift (void) |
a737bd4d | 9128 | { |
c19d1205 ZW |
9129 | unsigned int Rm = (inst.operands[1].present |
9130 | ? inst.operands[1].reg | |
9131 | : inst.operands[0].reg); | |
a737bd4d | 9132 | |
c19d1205 ZW |
9133 | inst.instruction |= inst.operands[0].reg << 12; |
9134 | inst.instruction |= Rm; | |
9135 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 9136 | { |
c19d1205 ZW |
9137 | inst.instruction |= inst.operands[2].reg << 8; |
9138 | inst.instruction |= SHIFT_BY_REG; | |
94342ec3 NC |
9139 | /* PR 12854: Error on extraneous shifts. */ |
9140 | constraint (inst.operands[2].shifted, | |
9141 | _("extraneous shift as part of operand to shift insn")); | |
a737bd4d NC |
9142 | } |
9143 | else | |
c19d1205 | 9144 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
9145 | } |
9146 | ||
09d92015 | 9147 | static void |
3eb17e6b | 9148 | do_smc (void) |
09d92015 | 9149 | { |
3eb17e6b | 9150 | inst.reloc.type = BFD_RELOC_ARM_SMC; |
c19d1205 | 9151 | inst.reloc.pc_rel = 0; |
09d92015 MM |
9152 | } |
9153 | ||
90ec0d68 MGD |
9154 | static void |
9155 | do_hvc (void) | |
9156 | { | |
9157 | inst.reloc.type = BFD_RELOC_ARM_HVC; | |
9158 | inst.reloc.pc_rel = 0; | |
9159 | } | |
9160 | ||
09d92015 | 9161 | static void |
c19d1205 | 9162 | do_swi (void) |
09d92015 | 9163 | { |
c19d1205 ZW |
9164 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
9165 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
9166 | } |
9167 | ||
c19d1205 ZW |
9168 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
9169 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
9170 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
9171 | Error if any register is R15. */ | |
e16bb312 | 9172 | |
c19d1205 ZW |
9173 | static void |
9174 | do_smla (void) | |
e16bb312 | 9175 | { |
c19d1205 ZW |
9176 | inst.instruction |= inst.operands[0].reg << 16; |
9177 | inst.instruction |= inst.operands[1].reg; | |
9178 | inst.instruction |= inst.operands[2].reg << 8; | |
9179 | inst.instruction |= inst.operands[3].reg << 12; | |
9180 | } | |
a737bd4d | 9181 | |
c19d1205 ZW |
9182 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
9183 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
9184 | Error if any register is R15. | |
9185 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 9186 | |
c19d1205 ZW |
9187 | static void |
9188 | do_smlal (void) | |
9189 | { | |
9190 | inst.instruction |= inst.operands[0].reg << 12; | |
9191 | inst.instruction |= inst.operands[1].reg << 16; | |
9192 | inst.instruction |= inst.operands[2].reg; | |
9193 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 9194 | |
c19d1205 ZW |
9195 | if (inst.operands[0].reg == inst.operands[1].reg) |
9196 | as_tsktsk (_("rdhi and rdlo must be different")); | |
9197 | } | |
a737bd4d | 9198 | |
c19d1205 ZW |
9199 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
9200 | SMULxy{cond} Rd,Rm,Rs | |
9201 | Error if any register is R15. */ | |
a737bd4d | 9202 | |
c19d1205 ZW |
9203 | static void |
9204 | do_smul (void) | |
9205 | { | |
9206 | inst.instruction |= inst.operands[0].reg << 16; | |
9207 | inst.instruction |= inst.operands[1].reg; | |
9208 | inst.instruction |= inst.operands[2].reg << 8; | |
9209 | } | |
a737bd4d | 9210 | |
b6702015 PB |
9211 | /* ARM V6 srs (argument parse). The variable fields in the encoding are |
9212 | the same for both ARM and Thumb-2. */ | |
a737bd4d | 9213 | |
c19d1205 ZW |
9214 | static void |
9215 | do_srs (void) | |
9216 | { | |
b6702015 PB |
9217 | int reg; |
9218 | ||
9219 | if (inst.operands[0].present) | |
9220 | { | |
9221 | reg = inst.operands[0].reg; | |
fdfde340 | 9222 | constraint (reg != REG_SP, _("SRS base register must be r13")); |
b6702015 PB |
9223 | } |
9224 | else | |
fdfde340 | 9225 | reg = REG_SP; |
b6702015 PB |
9226 | |
9227 | inst.instruction |= reg << 16; | |
9228 | inst.instruction |= inst.operands[1].imm; | |
9229 | if (inst.operands[0].writeback || inst.operands[1].writeback) | |
c19d1205 ZW |
9230 | inst.instruction |= WRITE_BACK; |
9231 | } | |
a737bd4d | 9232 | |
c19d1205 | 9233 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 9234 | |
c19d1205 ZW |
9235 | static void |
9236 | do_strex (void) | |
9237 | { | |
9238 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
9239 | || inst.operands[2].postind || inst.operands[2].writeback | |
9240 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
01cfc07f NC |
9241 | || inst.operands[2].negative |
9242 | /* See comment in do_ldrex(). */ | |
9243 | || (inst.operands[2].reg == REG_PC), | |
9244 | BAD_ADDR_MODE); | |
a737bd4d | 9245 | |
c19d1205 ZW |
9246 | constraint (inst.operands[0].reg == inst.operands[1].reg |
9247 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 9248 | |
c19d1205 ZW |
9249 | constraint (inst.reloc.exp.X_op != O_constant |
9250 | || inst.reloc.exp.X_add_number != 0, | |
9251 | _("offset must be zero in ARM encoding")); | |
a737bd4d | 9252 | |
c19d1205 ZW |
9253 | inst.instruction |= inst.operands[0].reg << 12; |
9254 | inst.instruction |= inst.operands[1].reg; | |
9255 | inst.instruction |= inst.operands[2].reg << 16; | |
9256 | inst.reloc.type = BFD_RELOC_UNUSED; | |
e16bb312 NC |
9257 | } |
9258 | ||
877807f8 NC |
9259 | static void |
9260 | do_t_strexbh (void) | |
9261 | { | |
9262 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
9263 | || inst.operands[2].postind || inst.operands[2].writeback | |
9264 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
9265 | || inst.operands[2].negative, | |
9266 | BAD_ADDR_MODE); | |
9267 | ||
9268 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
9269 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
9270 | ||
9271 | do_rm_rd_rn (); | |
9272 | } | |
9273 | ||
e16bb312 | 9274 | static void |
c19d1205 | 9275 | do_strexd (void) |
e16bb312 | 9276 | { |
c19d1205 ZW |
9277 | constraint (inst.operands[1].reg % 2 != 0, |
9278 | _("even register required")); | |
9279 | constraint (inst.operands[2].present | |
9280 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
9281 | _("can only store two consecutive registers")); | |
9282 | /* If op 2 were present and equal to PC, this function wouldn't | |
9283 | have been called in the first place. */ | |
9284 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 9285 | |
c19d1205 ZW |
9286 | constraint (inst.operands[0].reg == inst.operands[1].reg |
9287 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
9288 | || inst.operands[0].reg == inst.operands[3].reg, | |
9289 | BAD_OVERLAP); | |
e16bb312 | 9290 | |
c19d1205 ZW |
9291 | inst.instruction |= inst.operands[0].reg << 12; |
9292 | inst.instruction |= inst.operands[1].reg; | |
9293 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
9294 | } |
9295 | ||
9eb6c0f1 MGD |
9296 | /* ARM V8 STRL. */ |
9297 | static void | |
4b8c8c02 | 9298 | do_stlex (void) |
9eb6c0f1 MGD |
9299 | { |
9300 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
9301 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
9302 | ||
9303 | do_rd_rm_rn (); | |
9304 | } | |
9305 | ||
9306 | static void | |
4b8c8c02 | 9307 | do_t_stlex (void) |
9eb6c0f1 MGD |
9308 | { |
9309 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
9310 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
9311 | ||
9312 | do_rm_rd_rn (); | |
9313 | } | |
9314 | ||
c19d1205 ZW |
9315 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
9316 | extends it to 32-bits, and adds the result to a value in another | |
9317 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
9318 | before extracting the 16-bit value. | |
9319 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
9320 | Condition defaults to COND_ALWAYS. | |
9321 | Error if any register uses R15. */ | |
9322 | ||
e16bb312 | 9323 | static void |
c19d1205 | 9324 | do_sxtah (void) |
e16bb312 | 9325 | { |
c19d1205 ZW |
9326 | inst.instruction |= inst.operands[0].reg << 12; |
9327 | inst.instruction |= inst.operands[1].reg << 16; | |
9328 | inst.instruction |= inst.operands[2].reg; | |
9329 | inst.instruction |= inst.operands[3].imm << 10; | |
9330 | } | |
e16bb312 | 9331 | |
c19d1205 | 9332 | /* ARM V6 SXTH. |
e16bb312 | 9333 | |
c19d1205 ZW |
9334 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
9335 | Condition defaults to COND_ALWAYS. | |
9336 | Error if any register uses R15. */ | |
e16bb312 NC |
9337 | |
9338 | static void | |
c19d1205 | 9339 | do_sxth (void) |
e16bb312 | 9340 | { |
c19d1205 ZW |
9341 | inst.instruction |= inst.operands[0].reg << 12; |
9342 | inst.instruction |= inst.operands[1].reg; | |
9343 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 9344 | } |
c19d1205 ZW |
9345 | \f |
9346 | /* VFP instructions. In a logical order: SP variant first, monad | |
9347 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
9348 | |
9349 | static void | |
c19d1205 | 9350 | do_vfp_sp_monadic (void) |
e16bb312 | 9351 | { |
5287ad62 JB |
9352 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
9353 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
9354 | } |
9355 | ||
9356 | static void | |
c19d1205 | 9357 | do_vfp_sp_dyadic (void) |
e16bb312 | 9358 | { |
5287ad62 JB |
9359 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
9360 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
9361 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
9362 | } |
9363 | ||
9364 | static void | |
c19d1205 | 9365 | do_vfp_sp_compare_z (void) |
e16bb312 | 9366 | { |
5287ad62 | 9367 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
9368 | } |
9369 | ||
9370 | static void | |
c19d1205 | 9371 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 9372 | { |
5287ad62 JB |
9373 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
9374 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
9375 | } |
9376 | ||
9377 | static void | |
c19d1205 | 9378 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 9379 | { |
5287ad62 JB |
9380 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
9381 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
e16bb312 NC |
9382 | } |
9383 | ||
9384 | static void | |
c19d1205 | 9385 | do_vfp_reg_from_sp (void) |
e16bb312 | 9386 | { |
c19d1205 | 9387 | inst.instruction |= inst.operands[0].reg << 12; |
5287ad62 | 9388 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); |
e16bb312 NC |
9389 | } |
9390 | ||
9391 | static void | |
c19d1205 | 9392 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 9393 | { |
c19d1205 ZW |
9394 | constraint (inst.operands[2].imm != 2, |
9395 | _("only two consecutive VFP SP registers allowed here")); | |
9396 | inst.instruction |= inst.operands[0].reg << 12; | |
9397 | inst.instruction |= inst.operands[1].reg << 16; | |
5287ad62 | 9398 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); |
e16bb312 NC |
9399 | } |
9400 | ||
9401 | static void | |
c19d1205 | 9402 | do_vfp_sp_from_reg (void) |
e16bb312 | 9403 | { |
5287ad62 | 9404 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); |
c19d1205 | 9405 | inst.instruction |= inst.operands[1].reg << 12; |
e16bb312 NC |
9406 | } |
9407 | ||
9408 | static void | |
c19d1205 | 9409 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 9410 | { |
c19d1205 ZW |
9411 | constraint (inst.operands[0].imm != 2, |
9412 | _("only two consecutive VFP SP registers allowed here")); | |
5287ad62 | 9413 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); |
c19d1205 ZW |
9414 | inst.instruction |= inst.operands[1].reg << 12; |
9415 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
9416 | } |
9417 | ||
9418 | static void | |
c19d1205 | 9419 | do_vfp_sp_ldst (void) |
e16bb312 | 9420 | { |
5287ad62 | 9421 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
c19d1205 | 9422 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
9423 | } |
9424 | ||
9425 | static void | |
c19d1205 | 9426 | do_vfp_dp_ldst (void) |
e16bb312 | 9427 | { |
5287ad62 | 9428 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
c19d1205 | 9429 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
9430 | } |
9431 | ||
c19d1205 | 9432 | |
e16bb312 | 9433 | static void |
c19d1205 | 9434 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 9435 | { |
c19d1205 ZW |
9436 | if (inst.operands[0].writeback) |
9437 | inst.instruction |= WRITE_BACK; | |
9438 | else | |
9439 | constraint (ldstm_type != VFP_LDSTMIA, | |
9440 | _("this addressing mode requires base-register writeback")); | |
9441 | inst.instruction |= inst.operands[0].reg << 16; | |
5287ad62 | 9442 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); |
c19d1205 | 9443 | inst.instruction |= inst.operands[1].imm; |
e16bb312 NC |
9444 | } |
9445 | ||
9446 | static void | |
c19d1205 | 9447 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 9448 | { |
c19d1205 | 9449 | int count; |
e16bb312 | 9450 | |
c19d1205 ZW |
9451 | if (inst.operands[0].writeback) |
9452 | inst.instruction |= WRITE_BACK; | |
9453 | else | |
9454 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
9455 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 9456 | |
c19d1205 | 9457 | inst.instruction |= inst.operands[0].reg << 16; |
5287ad62 | 9458 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
e16bb312 | 9459 | |
c19d1205 ZW |
9460 | count = inst.operands[1].imm << 1; |
9461 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
9462 | count += 1; | |
e16bb312 | 9463 | |
c19d1205 | 9464 | inst.instruction |= count; |
e16bb312 NC |
9465 | } |
9466 | ||
9467 | static void | |
c19d1205 | 9468 | do_vfp_sp_ldstmia (void) |
e16bb312 | 9469 | { |
c19d1205 | 9470 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
9471 | } |
9472 | ||
9473 | static void | |
c19d1205 | 9474 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 9475 | { |
c19d1205 | 9476 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
9477 | } |
9478 | ||
9479 | static void | |
c19d1205 | 9480 | do_vfp_dp_ldstmia (void) |
e16bb312 | 9481 | { |
c19d1205 | 9482 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
9483 | } |
9484 | ||
9485 | static void | |
c19d1205 | 9486 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 9487 | { |
c19d1205 | 9488 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
9489 | } |
9490 | ||
9491 | static void | |
c19d1205 | 9492 | do_vfp_xp_ldstmia (void) |
e16bb312 | 9493 | { |
c19d1205 ZW |
9494 | vfp_dp_ldstm (VFP_LDSTMIAX); |
9495 | } | |
e16bb312 | 9496 | |
c19d1205 ZW |
9497 | static void |
9498 | do_vfp_xp_ldstmdb (void) | |
9499 | { | |
9500 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 9501 | } |
5287ad62 JB |
9502 | |
9503 | static void | |
9504 | do_vfp_dp_rd_rm (void) | |
9505 | { | |
9506 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9507 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
9508 | } | |
9509 | ||
9510 | static void | |
9511 | do_vfp_dp_rn_rd (void) | |
9512 | { | |
9513 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); | |
9514 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
9515 | } | |
9516 | ||
9517 | static void | |
9518 | do_vfp_dp_rd_rn (void) | |
9519 | { | |
9520 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9521 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
9522 | } | |
9523 | ||
9524 | static void | |
9525 | do_vfp_dp_rd_rn_rm (void) | |
9526 | { | |
9527 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9528 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
9529 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); | |
9530 | } | |
9531 | ||
9532 | static void | |
9533 | do_vfp_dp_rd (void) | |
9534 | { | |
9535 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9536 | } | |
9537 | ||
9538 | static void | |
9539 | do_vfp_dp_rm_rd_rn (void) | |
9540 | { | |
9541 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); | |
9542 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
9543 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); | |
9544 | } | |
9545 | ||
9546 | /* VFPv3 instructions. */ | |
9547 | static void | |
9548 | do_vfp_sp_const (void) | |
9549 | { | |
9550 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
00249aaa PB |
9551 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
9552 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
9553 | } |
9554 | ||
9555 | static void | |
9556 | do_vfp_dp_const (void) | |
9557 | { | |
9558 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
00249aaa PB |
9559 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
9560 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
9561 | } |
9562 | ||
9563 | static void | |
9564 | vfp_conv (int srcsize) | |
9565 | { | |
5f1af56b MGD |
9566 | int immbits = srcsize - inst.operands[1].imm; |
9567 | ||
fa94de6b RM |
9568 | if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize)) |
9569 | { | |
5f1af56b | 9570 | /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16. |
477330fc | 9571 | i.e. immbits must be in range 0 - 16. */ |
5f1af56b MGD |
9572 | inst.error = _("immediate value out of range, expected range [0, 16]"); |
9573 | return; | |
9574 | } | |
fa94de6b | 9575 | else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize)) |
5f1af56b MGD |
9576 | { |
9577 | /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32. | |
477330fc | 9578 | i.e. immbits must be in range 0 - 31. */ |
5f1af56b MGD |
9579 | inst.error = _("immediate value out of range, expected range [1, 32]"); |
9580 | return; | |
9581 | } | |
9582 | ||
5287ad62 JB |
9583 | inst.instruction |= (immbits & 1) << 5; |
9584 | inst.instruction |= (immbits >> 1); | |
9585 | } | |
9586 | ||
9587 | static void | |
9588 | do_vfp_sp_conv_16 (void) | |
9589 | { | |
9590 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
9591 | vfp_conv (16); | |
9592 | } | |
9593 | ||
9594 | static void | |
9595 | do_vfp_dp_conv_16 (void) | |
9596 | { | |
9597 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9598 | vfp_conv (16); | |
9599 | } | |
9600 | ||
9601 | static void | |
9602 | do_vfp_sp_conv_32 (void) | |
9603 | { | |
9604 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
9605 | vfp_conv (32); | |
9606 | } | |
9607 | ||
9608 | static void | |
9609 | do_vfp_dp_conv_32 (void) | |
9610 | { | |
9611 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9612 | vfp_conv (32); | |
9613 | } | |
c19d1205 ZW |
9614 | \f |
9615 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 9616 | |
c19d1205 ZW |
9617 | static void |
9618 | do_fpa_cmp (void) | |
9619 | { | |
9620 | inst.instruction |= inst.operands[0].reg << 16; | |
9621 | inst.instruction |= inst.operands[1].reg; | |
9622 | } | |
b99bd4ef NC |
9623 | |
9624 | static void | |
c19d1205 | 9625 | do_fpa_ldmstm (void) |
b99bd4ef | 9626 | { |
c19d1205 ZW |
9627 | inst.instruction |= inst.operands[0].reg << 12; |
9628 | switch (inst.operands[1].imm) | |
9629 | { | |
9630 | case 1: inst.instruction |= CP_T_X; break; | |
9631 | case 2: inst.instruction |= CP_T_Y; break; | |
9632 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
9633 | case 4: break; | |
9634 | default: abort (); | |
9635 | } | |
b99bd4ef | 9636 | |
c19d1205 ZW |
9637 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
9638 | { | |
9639 | /* The instruction specified "ea" or "fd", so we can only accept | |
9640 | [Rn]{!}. The instruction does not really support stacking or | |
9641 | unstacking, so we have to emulate these by setting appropriate | |
9642 | bits and offsets. */ | |
9643 | constraint (inst.reloc.exp.X_op != O_constant | |
9644 | || inst.reloc.exp.X_add_number != 0, | |
9645 | _("this instruction does not support indexing")); | |
b99bd4ef | 9646 | |
c19d1205 ZW |
9647 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
9648 | inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; | |
b99bd4ef | 9649 | |
c19d1205 ZW |
9650 | if (!(inst.instruction & INDEX_UP)) |
9651 | inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; | |
b99bd4ef | 9652 | |
c19d1205 ZW |
9653 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
9654 | { | |
9655 | inst.operands[2].preind = 0; | |
9656 | inst.operands[2].postind = 1; | |
9657 | } | |
9658 | } | |
b99bd4ef | 9659 | |
c19d1205 | 9660 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 9661 | } |
c19d1205 ZW |
9662 | \f |
9663 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 9664 | |
c19d1205 ZW |
9665 | static void |
9666 | do_iwmmxt_tandorc (void) | |
9667 | { | |
9668 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
9669 | } | |
b99bd4ef | 9670 | |
c19d1205 ZW |
9671 | static void |
9672 | do_iwmmxt_textrc (void) | |
9673 | { | |
9674 | inst.instruction |= inst.operands[0].reg << 12; | |
9675 | inst.instruction |= inst.operands[1].imm; | |
9676 | } | |
b99bd4ef NC |
9677 | |
9678 | static void | |
c19d1205 | 9679 | do_iwmmxt_textrm (void) |
b99bd4ef | 9680 | { |
c19d1205 ZW |
9681 | inst.instruction |= inst.operands[0].reg << 12; |
9682 | inst.instruction |= inst.operands[1].reg << 16; | |
9683 | inst.instruction |= inst.operands[2].imm; | |
9684 | } | |
b99bd4ef | 9685 | |
c19d1205 ZW |
9686 | static void |
9687 | do_iwmmxt_tinsr (void) | |
9688 | { | |
9689 | inst.instruction |= inst.operands[0].reg << 16; | |
9690 | inst.instruction |= inst.operands[1].reg << 12; | |
9691 | inst.instruction |= inst.operands[2].imm; | |
9692 | } | |
b99bd4ef | 9693 | |
c19d1205 ZW |
9694 | static void |
9695 | do_iwmmxt_tmia (void) | |
9696 | { | |
9697 | inst.instruction |= inst.operands[0].reg << 5; | |
9698 | inst.instruction |= inst.operands[1].reg; | |
9699 | inst.instruction |= inst.operands[2].reg << 12; | |
9700 | } | |
b99bd4ef | 9701 | |
c19d1205 ZW |
9702 | static void |
9703 | do_iwmmxt_waligni (void) | |
9704 | { | |
9705 | inst.instruction |= inst.operands[0].reg << 12; | |
9706 | inst.instruction |= inst.operands[1].reg << 16; | |
9707 | inst.instruction |= inst.operands[2].reg; | |
9708 | inst.instruction |= inst.operands[3].imm << 20; | |
9709 | } | |
b99bd4ef | 9710 | |
2d447fca JM |
9711 | static void |
9712 | do_iwmmxt_wmerge (void) | |
9713 | { | |
9714 | inst.instruction |= inst.operands[0].reg << 12; | |
9715 | inst.instruction |= inst.operands[1].reg << 16; | |
9716 | inst.instruction |= inst.operands[2].reg; | |
9717 | inst.instruction |= inst.operands[3].imm << 21; | |
9718 | } | |
9719 | ||
c19d1205 ZW |
9720 | static void |
9721 | do_iwmmxt_wmov (void) | |
9722 | { | |
9723 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
9724 | inst.instruction |= inst.operands[0].reg << 12; | |
9725 | inst.instruction |= inst.operands[1].reg << 16; | |
9726 | inst.instruction |= inst.operands[1].reg; | |
9727 | } | |
b99bd4ef | 9728 | |
c19d1205 ZW |
9729 | static void |
9730 | do_iwmmxt_wldstbh (void) | |
9731 | { | |
8f06b2d8 | 9732 | int reloc; |
c19d1205 | 9733 | inst.instruction |= inst.operands[0].reg << 12; |
8f06b2d8 PB |
9734 | if (thumb_mode) |
9735 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
9736 | else | |
9737 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
9738 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
9739 | } |
9740 | ||
c19d1205 ZW |
9741 | static void |
9742 | do_iwmmxt_wldstw (void) | |
9743 | { | |
9744 | /* RIWR_RIWC clears .isreg for a control register. */ | |
9745 | if (!inst.operands[0].isreg) | |
9746 | { | |
9747 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
9748 | inst.instruction |= 0xf0000000; | |
9749 | } | |
b99bd4ef | 9750 | |
c19d1205 ZW |
9751 | inst.instruction |= inst.operands[0].reg << 12; |
9752 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
9753 | } | |
b99bd4ef NC |
9754 | |
9755 | static void | |
c19d1205 | 9756 | do_iwmmxt_wldstd (void) |
b99bd4ef | 9757 | { |
c19d1205 | 9758 | inst.instruction |= inst.operands[0].reg << 12; |
2d447fca JM |
9759 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) |
9760 | && inst.operands[1].immisreg) | |
9761 | { | |
9762 | inst.instruction &= ~0x1a000ff; | |
9763 | inst.instruction |= (0xf << 28); | |
9764 | if (inst.operands[1].preind) | |
9765 | inst.instruction |= PRE_INDEX; | |
9766 | if (!inst.operands[1].negative) | |
9767 | inst.instruction |= INDEX_UP; | |
9768 | if (inst.operands[1].writeback) | |
9769 | inst.instruction |= WRITE_BACK; | |
9770 | inst.instruction |= inst.operands[1].reg << 16; | |
9771 | inst.instruction |= inst.reloc.exp.X_add_number << 4; | |
9772 | inst.instruction |= inst.operands[1].imm; | |
9773 | } | |
9774 | else | |
9775 | encode_arm_cp_address (1, TRUE, FALSE, 0); | |
c19d1205 | 9776 | } |
b99bd4ef | 9777 | |
c19d1205 ZW |
9778 | static void |
9779 | do_iwmmxt_wshufh (void) | |
9780 | { | |
9781 | inst.instruction |= inst.operands[0].reg << 12; | |
9782 | inst.instruction |= inst.operands[1].reg << 16; | |
9783 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
9784 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
9785 | } | |
b99bd4ef | 9786 | |
c19d1205 ZW |
9787 | static void |
9788 | do_iwmmxt_wzero (void) | |
9789 | { | |
9790 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
9791 | inst.instruction |= inst.operands[0].reg; | |
9792 | inst.instruction |= inst.operands[0].reg << 12; | |
9793 | inst.instruction |= inst.operands[0].reg << 16; | |
9794 | } | |
2d447fca JM |
9795 | |
9796 | static void | |
9797 | do_iwmmxt_wrwrwr_or_imm5 (void) | |
9798 | { | |
9799 | if (inst.operands[2].isreg) | |
9800 | do_rd_rn_rm (); | |
9801 | else { | |
9802 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), | |
9803 | _("immediate operand requires iWMMXt2")); | |
9804 | do_rd_rn (); | |
9805 | if (inst.operands[2].imm == 0) | |
9806 | { | |
9807 | switch ((inst.instruction >> 20) & 0xf) | |
9808 | { | |
9809 | case 4: | |
9810 | case 5: | |
9811 | case 6: | |
5f4273c7 | 9812 | case 7: |
2d447fca JM |
9813 | /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ |
9814 | inst.operands[2].imm = 16; | |
9815 | inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); | |
9816 | break; | |
9817 | case 8: | |
9818 | case 9: | |
9819 | case 10: | |
9820 | case 11: | |
9821 | /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ | |
9822 | inst.operands[2].imm = 32; | |
9823 | inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); | |
9824 | break; | |
9825 | case 12: | |
9826 | case 13: | |
9827 | case 14: | |
9828 | case 15: | |
9829 | { | |
9830 | /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ | |
9831 | unsigned long wrn; | |
9832 | wrn = (inst.instruction >> 16) & 0xf; | |
9833 | inst.instruction &= 0xff0fff0f; | |
9834 | inst.instruction |= wrn; | |
9835 | /* Bail out here; the instruction is now assembled. */ | |
9836 | return; | |
9837 | } | |
9838 | } | |
9839 | } | |
9840 | /* Map 32 -> 0, etc. */ | |
9841 | inst.operands[2].imm &= 0x1f; | |
9842 | inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); | |
9843 | } | |
9844 | } | |
c19d1205 ZW |
9845 | \f |
9846 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
9847 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 9848 | |
c19d1205 | 9849 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 9850 | |
c19d1205 ZW |
9851 | static void |
9852 | do_mav_triple (void) | |
9853 | { | |
9854 | inst.instruction |= inst.operands[0].reg << 16; | |
9855 | inst.instruction |= inst.operands[1].reg; | |
9856 | inst.instruction |= inst.operands[2].reg << 12; | |
9857 | } | |
b99bd4ef | 9858 | |
c19d1205 ZW |
9859 | /* Insns like "foo W,X,Y,Z". |
9860 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 9861 | |
c19d1205 ZW |
9862 | static void |
9863 | do_mav_quad (void) | |
9864 | { | |
9865 | inst.instruction |= inst.operands[0].reg << 5; | |
9866 | inst.instruction |= inst.operands[1].reg << 12; | |
9867 | inst.instruction |= inst.operands[2].reg << 16; | |
9868 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
9869 | } |
9870 | ||
c19d1205 ZW |
9871 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
9872 | static void | |
9873 | do_mav_dspsc (void) | |
a737bd4d | 9874 | { |
c19d1205 ZW |
9875 | inst.instruction |= inst.operands[1].reg << 12; |
9876 | } | |
a737bd4d | 9877 | |
c19d1205 ZW |
9878 | /* Maverick shift immediate instructions. |
9879 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
9880 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 9881 | |
c19d1205 ZW |
9882 | static void |
9883 | do_mav_shift (void) | |
9884 | { | |
9885 | int imm = inst.operands[2].imm; | |
a737bd4d | 9886 | |
c19d1205 ZW |
9887 | inst.instruction |= inst.operands[0].reg << 12; |
9888 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 9889 | |
c19d1205 ZW |
9890 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
9891 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
9892 | Bit 4 should be 0. */ | |
9893 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 9894 | |
c19d1205 ZW |
9895 | inst.instruction |= imm; |
9896 | } | |
9897 | \f | |
9898 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 9899 | |
c19d1205 ZW |
9900 | /* Xscale multiply-accumulate (argument parse) |
9901 | MIAcc acc0,Rm,Rs | |
9902 | MIAPHcc acc0,Rm,Rs | |
9903 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 9904 | |
c19d1205 ZW |
9905 | static void |
9906 | do_xsc_mia (void) | |
9907 | { | |
9908 | inst.instruction |= inst.operands[1].reg; | |
9909 | inst.instruction |= inst.operands[2].reg << 12; | |
9910 | } | |
a737bd4d | 9911 | |
c19d1205 | 9912 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 9913 | |
c19d1205 | 9914 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 9915 | |
c19d1205 ZW |
9916 | static void |
9917 | do_xsc_mar (void) | |
9918 | { | |
9919 | inst.instruction |= inst.operands[1].reg << 12; | |
9920 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
9921 | } |
9922 | ||
c19d1205 | 9923 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 9924 | |
c19d1205 | 9925 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
9926 | |
9927 | static void | |
c19d1205 | 9928 | do_xsc_mra (void) |
b99bd4ef | 9929 | { |
c19d1205 ZW |
9930 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
9931 | inst.instruction |= inst.operands[0].reg << 12; | |
9932 | inst.instruction |= inst.operands[1].reg << 16; | |
9933 | } | |
9934 | \f | |
9935 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 9936 | |
c19d1205 ZW |
9937 | /* inst.operands[i] is a shifted-register operand; encode |
9938 | it into inst.instruction in the format used by Thumb32. */ | |
9939 | ||
9940 | static void | |
9941 | encode_thumb32_shifted_operand (int i) | |
9942 | { | |
9943 | unsigned int value = inst.reloc.exp.X_add_number; | |
9944 | unsigned int shift = inst.operands[i].shift_kind; | |
b99bd4ef | 9945 | |
9c3c69f2 PB |
9946 | constraint (inst.operands[i].immisreg, |
9947 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
9948 | inst.instruction |= inst.operands[i].reg; |
9949 | if (shift == SHIFT_RRX) | |
9950 | inst.instruction |= SHIFT_ROR << 4; | |
9951 | else | |
b99bd4ef | 9952 | { |
c19d1205 ZW |
9953 | constraint (inst.reloc.exp.X_op != O_constant, |
9954 | _("expression too complex")); | |
9955 | ||
9956 | constraint (value > 32 | |
9957 | || (value == 32 && (shift == SHIFT_LSL | |
9958 | || shift == SHIFT_ROR)), | |
9959 | _("shift expression is too large")); | |
9960 | ||
9961 | if (value == 0) | |
9962 | shift = SHIFT_LSL; | |
9963 | else if (value == 32) | |
9964 | value = 0; | |
9965 | ||
9966 | inst.instruction |= shift << 4; | |
9967 | inst.instruction |= (value & 0x1c) << 10; | |
9968 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 9969 | } |
c19d1205 | 9970 | } |
b99bd4ef | 9971 | |
b99bd4ef | 9972 | |
c19d1205 ZW |
9973 | /* inst.operands[i] was set up by parse_address. Encode it into a |
9974 | Thumb32 format load or store instruction. Reject forms that cannot | |
9975 | be used with such instructions. If is_t is true, reject forms that | |
9976 | cannot be used with a T instruction; if is_d is true, reject forms | |
5be8be5d DG |
9977 | that cannot be used with a D instruction. If it is a store insn, |
9978 | reject PC in Rn. */ | |
b99bd4ef | 9979 | |
c19d1205 ZW |
9980 | static void |
9981 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
9982 | { | |
5be8be5d | 9983 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
c19d1205 ZW |
9984 | |
9985 | constraint (!inst.operands[i].isreg, | |
53365c0d | 9986 | _("Instruction does not support =N addresses")); |
b99bd4ef | 9987 | |
c19d1205 ZW |
9988 | inst.instruction |= inst.operands[i].reg << 16; |
9989 | if (inst.operands[i].immisreg) | |
b99bd4ef | 9990 | { |
5be8be5d | 9991 | constraint (is_pc, BAD_PC_ADDRESSING); |
c19d1205 ZW |
9992 | constraint (is_t || is_d, _("cannot use register index with this instruction")); |
9993 | constraint (inst.operands[i].negative, | |
9994 | _("Thumb does not support negative register indexing")); | |
9995 | constraint (inst.operands[i].postind, | |
9996 | _("Thumb does not support register post-indexing")); | |
9997 | constraint (inst.operands[i].writeback, | |
9998 | _("Thumb does not support register indexing with writeback")); | |
9999 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
10000 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 10001 | |
f40d1643 | 10002 | inst.instruction |= inst.operands[i].imm; |
c19d1205 | 10003 | if (inst.operands[i].shifted) |
b99bd4ef | 10004 | { |
c19d1205 ZW |
10005 | constraint (inst.reloc.exp.X_op != O_constant, |
10006 | _("expression too complex")); | |
9c3c69f2 PB |
10007 | constraint (inst.reloc.exp.X_add_number < 0 |
10008 | || inst.reloc.exp.X_add_number > 3, | |
c19d1205 | 10009 | _("shift out of range")); |
9c3c69f2 | 10010 | inst.instruction |= inst.reloc.exp.X_add_number << 4; |
c19d1205 ZW |
10011 | } |
10012 | inst.reloc.type = BFD_RELOC_UNUSED; | |
10013 | } | |
10014 | else if (inst.operands[i].preind) | |
10015 | { | |
5be8be5d | 10016 | constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK); |
f40d1643 | 10017 | constraint (is_t && inst.operands[i].writeback, |
c19d1205 | 10018 | _("cannot use writeback with this instruction")); |
4755303e WN |
10019 | constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0), |
10020 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
10021 | |
10022 | if (is_d) | |
10023 | { | |
10024 | inst.instruction |= 0x01000000; | |
10025 | if (inst.operands[i].writeback) | |
10026 | inst.instruction |= 0x00200000; | |
b99bd4ef | 10027 | } |
c19d1205 | 10028 | else |
b99bd4ef | 10029 | { |
c19d1205 ZW |
10030 | inst.instruction |= 0x00000c00; |
10031 | if (inst.operands[i].writeback) | |
10032 | inst.instruction |= 0x00000100; | |
b99bd4ef | 10033 | } |
c19d1205 | 10034 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 10035 | } |
c19d1205 | 10036 | else if (inst.operands[i].postind) |
b99bd4ef | 10037 | { |
9c2799c2 | 10038 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
10039 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); |
10040 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
10041 | ||
10042 | if (is_d) | |
10043 | inst.instruction |= 0x00200000; | |
10044 | else | |
10045 | inst.instruction |= 0x00000900; | |
10046 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
10047 | } | |
10048 | else /* unindexed - only for coprocessor */ | |
10049 | inst.error = _("instruction does not accept unindexed addressing"); | |
10050 | } | |
10051 | ||
10052 | /* Table of Thumb instructions which exist in both 16- and 32-bit | |
10053 | encodings (the latter only in post-V6T2 cores). The index is the | |
10054 | value used in the insns table below. When there is more than one | |
10055 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
10056 | holds variant (1). |
10057 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 | 10058 | #define T16_32_TAB \ |
21d799b5 NC |
10059 | X(_adc, 4140, eb400000), \ |
10060 | X(_adcs, 4140, eb500000), \ | |
10061 | X(_add, 1c00, eb000000), \ | |
10062 | X(_adds, 1c00, eb100000), \ | |
10063 | X(_addi, 0000, f1000000), \ | |
10064 | X(_addis, 0000, f1100000), \ | |
10065 | X(_add_pc,000f, f20f0000), \ | |
10066 | X(_add_sp,000d, f10d0000), \ | |
10067 | X(_adr, 000f, f20f0000), \ | |
10068 | X(_and, 4000, ea000000), \ | |
10069 | X(_ands, 4000, ea100000), \ | |
10070 | X(_asr, 1000, fa40f000), \ | |
10071 | X(_asrs, 1000, fa50f000), \ | |
10072 | X(_b, e000, f000b000), \ | |
10073 | X(_bcond, d000, f0008000), \ | |
10074 | X(_bic, 4380, ea200000), \ | |
10075 | X(_bics, 4380, ea300000), \ | |
10076 | X(_cmn, 42c0, eb100f00), \ | |
10077 | X(_cmp, 2800, ebb00f00), \ | |
10078 | X(_cpsie, b660, f3af8400), \ | |
10079 | X(_cpsid, b670, f3af8600), \ | |
10080 | X(_cpy, 4600, ea4f0000), \ | |
10081 | X(_dec_sp,80dd, f1ad0d00), \ | |
10082 | X(_eor, 4040, ea800000), \ | |
10083 | X(_eors, 4040, ea900000), \ | |
10084 | X(_inc_sp,00dd, f10d0d00), \ | |
10085 | X(_ldmia, c800, e8900000), \ | |
10086 | X(_ldr, 6800, f8500000), \ | |
10087 | X(_ldrb, 7800, f8100000), \ | |
10088 | X(_ldrh, 8800, f8300000), \ | |
10089 | X(_ldrsb, 5600, f9100000), \ | |
10090 | X(_ldrsh, 5e00, f9300000), \ | |
10091 | X(_ldr_pc,4800, f85f0000), \ | |
10092 | X(_ldr_pc2,4800, f85f0000), \ | |
10093 | X(_ldr_sp,9800, f85d0000), \ | |
10094 | X(_lsl, 0000, fa00f000), \ | |
10095 | X(_lsls, 0000, fa10f000), \ | |
10096 | X(_lsr, 0800, fa20f000), \ | |
10097 | X(_lsrs, 0800, fa30f000), \ | |
10098 | X(_mov, 2000, ea4f0000), \ | |
10099 | X(_movs, 2000, ea5f0000), \ | |
10100 | X(_mul, 4340, fb00f000), \ | |
10101 | X(_muls, 4340, ffffffff), /* no 32b muls */ \ | |
10102 | X(_mvn, 43c0, ea6f0000), \ | |
10103 | X(_mvns, 43c0, ea7f0000), \ | |
10104 | X(_neg, 4240, f1c00000), /* rsb #0 */ \ | |
10105 | X(_negs, 4240, f1d00000), /* rsbs #0 */ \ | |
10106 | X(_orr, 4300, ea400000), \ | |
10107 | X(_orrs, 4300, ea500000), \ | |
10108 | X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \ | |
10109 | X(_push, b400, e92d0000), /* stmdb sp!,... */ \ | |
10110 | X(_rev, ba00, fa90f080), \ | |
10111 | X(_rev16, ba40, fa90f090), \ | |
10112 | X(_revsh, bac0, fa90f0b0), \ | |
10113 | X(_ror, 41c0, fa60f000), \ | |
10114 | X(_rors, 41c0, fa70f000), \ | |
10115 | X(_sbc, 4180, eb600000), \ | |
10116 | X(_sbcs, 4180, eb700000), \ | |
10117 | X(_stmia, c000, e8800000), \ | |
10118 | X(_str, 6000, f8400000), \ | |
10119 | X(_strb, 7000, f8000000), \ | |
10120 | X(_strh, 8000, f8200000), \ | |
10121 | X(_str_sp,9000, f84d0000), \ | |
10122 | X(_sub, 1e00, eba00000), \ | |
10123 | X(_subs, 1e00, ebb00000), \ | |
10124 | X(_subi, 8000, f1a00000), \ | |
10125 | X(_subis, 8000, f1b00000), \ | |
10126 | X(_sxtb, b240, fa4ff080), \ | |
10127 | X(_sxth, b200, fa0ff080), \ | |
10128 | X(_tst, 4200, ea100f00), \ | |
10129 | X(_uxtb, b2c0, fa5ff080), \ | |
10130 | X(_uxth, b280, fa1ff080), \ | |
10131 | X(_nop, bf00, f3af8000), \ | |
10132 | X(_yield, bf10, f3af8001), \ | |
10133 | X(_wfe, bf20, f3af8002), \ | |
10134 | X(_wfi, bf30, f3af8003), \ | |
53c4b28b | 10135 | X(_sev, bf40, f3af8004), \ |
74db7efb NC |
10136 | X(_sevl, bf50, f3af8005), \ |
10137 | X(_udf, de00, f7f0a000) | |
c19d1205 ZW |
10138 | |
10139 | /* To catch errors in encoding functions, the codes are all offset by | |
10140 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
10141 | as 16-bit instructions. */ | |
21d799b5 | 10142 | #define X(a,b,c) T_MNEM##a |
c19d1205 ZW |
10143 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; |
10144 | #undef X | |
10145 | ||
10146 | #define X(a,b,c) 0x##b | |
10147 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
10148 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
10149 | #undef X | |
10150 | ||
10151 | #define X(a,b,c) 0x##c | |
10152 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
c921be7d NC |
10153 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) |
10154 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
c19d1205 ZW |
10155 | #undef X |
10156 | #undef T16_32_TAB | |
10157 | ||
10158 | /* Thumb instruction encoders, in alphabetical order. */ | |
10159 | ||
92e90b6e | 10160 | /* ADDW or SUBW. */ |
c921be7d | 10161 | |
92e90b6e PB |
10162 | static void |
10163 | do_t_add_sub_w (void) | |
10164 | { | |
10165 | int Rd, Rn; | |
10166 | ||
10167 | Rd = inst.operands[0].reg; | |
10168 | Rn = inst.operands[1].reg; | |
10169 | ||
539d4391 NC |
10170 | /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this |
10171 | is the SP-{plus,minus}-immediate form of the instruction. */ | |
10172 | if (Rn == REG_SP) | |
10173 | constraint (Rd == REG_PC, BAD_PC); | |
10174 | else | |
10175 | reject_bad_reg (Rd); | |
fdfde340 | 10176 | |
92e90b6e PB |
10177 | inst.instruction |= (Rn << 16) | (Rd << 8); |
10178 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
10179 | } | |
10180 | ||
c19d1205 ZW |
10181 | /* Parse an add or subtract instruction. We get here with inst.instruction |
10182 | equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ | |
10183 | ||
10184 | static void | |
10185 | do_t_add_sub (void) | |
10186 | { | |
10187 | int Rd, Rs, Rn; | |
10188 | ||
10189 | Rd = inst.operands[0].reg; | |
10190 | Rs = (inst.operands[1].present | |
10191 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
10192 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
10193 | ||
e07e6e58 NC |
10194 | if (Rd == REG_PC) |
10195 | set_it_insn_type_last (); | |
10196 | ||
c19d1205 ZW |
10197 | if (unified_syntax) |
10198 | { | |
0110f2b8 PB |
10199 | bfd_boolean flags; |
10200 | bfd_boolean narrow; | |
10201 | int opcode; | |
10202 | ||
10203 | flags = (inst.instruction == T_MNEM_adds | |
10204 | || inst.instruction == T_MNEM_subs); | |
10205 | if (flags) | |
e07e6e58 | 10206 | narrow = !in_it_block (); |
0110f2b8 | 10207 | else |
e07e6e58 | 10208 | narrow = in_it_block (); |
c19d1205 | 10209 | if (!inst.operands[2].isreg) |
b99bd4ef | 10210 | { |
16805f35 PB |
10211 | int add; |
10212 | ||
fdfde340 JM |
10213 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); |
10214 | ||
16805f35 PB |
10215 | add = (inst.instruction == T_MNEM_add |
10216 | || inst.instruction == T_MNEM_adds); | |
0110f2b8 PB |
10217 | opcode = 0; |
10218 | if (inst.size_req != 4) | |
10219 | { | |
0110f2b8 | 10220 | /* Attempt to use a narrow opcode, with relaxation if |
477330fc | 10221 | appropriate. */ |
0110f2b8 PB |
10222 | if (Rd == REG_SP && Rs == REG_SP && !flags) |
10223 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
10224 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
10225 | opcode = T_MNEM_add_sp; | |
10226 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
10227 | opcode = T_MNEM_add_pc; | |
10228 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
10229 | { | |
10230 | if (flags) | |
10231 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
10232 | else | |
10233 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
10234 | } | |
10235 | if (opcode) | |
10236 | { | |
10237 | inst.instruction = THUMB_OP16(opcode); | |
10238 | inst.instruction |= (Rd << 4) | Rs; | |
10239 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
10240 | if (inst.size_req != 2) | |
10241 | inst.relax = opcode; | |
10242 | } | |
10243 | else | |
10244 | constraint (inst.size_req == 2, BAD_HIREG); | |
10245 | } | |
10246 | if (inst.size_req == 4 | |
10247 | || (inst.size_req != 2 && !opcode)) | |
10248 | { | |
efd81785 PB |
10249 | if (Rd == REG_PC) |
10250 | { | |
fdfde340 | 10251 | constraint (add, BAD_PC); |
efd81785 PB |
10252 | constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, |
10253 | _("only SUBS PC, LR, #const allowed")); | |
10254 | constraint (inst.reloc.exp.X_op != O_constant, | |
10255 | _("expression too complex")); | |
10256 | constraint (inst.reloc.exp.X_add_number < 0 | |
10257 | || inst.reloc.exp.X_add_number > 0xff, | |
10258 | _("immediate value out of range")); | |
10259 | inst.instruction = T2_SUBS_PC_LR | |
10260 | | inst.reloc.exp.X_add_number; | |
10261 | inst.reloc.type = BFD_RELOC_UNUSED; | |
10262 | return; | |
10263 | } | |
10264 | else if (Rs == REG_PC) | |
16805f35 PB |
10265 | { |
10266 | /* Always use addw/subw. */ | |
10267 | inst.instruction = add ? 0xf20f0000 : 0xf2af0000; | |
10268 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
10269 | } | |
10270 | else | |
10271 | { | |
10272 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10273 | inst.instruction = (inst.instruction & 0xe1ffffff) | |
10274 | | 0x10000000; | |
10275 | if (flags) | |
10276 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10277 | else | |
10278 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; | |
10279 | } | |
dc4503c6 PB |
10280 | inst.instruction |= Rd << 8; |
10281 | inst.instruction |= Rs << 16; | |
0110f2b8 | 10282 | } |
b99bd4ef | 10283 | } |
c19d1205 ZW |
10284 | else |
10285 | { | |
5f4cb198 NC |
10286 | unsigned int value = inst.reloc.exp.X_add_number; |
10287 | unsigned int shift = inst.operands[2].shift_kind; | |
10288 | ||
c19d1205 ZW |
10289 | Rn = inst.operands[2].reg; |
10290 | /* See if we can do this with a 16-bit instruction. */ | |
10291 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
10292 | { | |
e27ec89e PB |
10293 | if (Rd > 7 || Rs > 7 || Rn > 7) |
10294 | narrow = FALSE; | |
10295 | ||
10296 | if (narrow) | |
c19d1205 | 10297 | { |
e27ec89e PB |
10298 | inst.instruction = ((inst.instruction == T_MNEM_adds |
10299 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
10300 | ? T_OPCODE_ADD_R3 |
10301 | : T_OPCODE_SUB_R3); | |
10302 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
10303 | return; | |
10304 | } | |
b99bd4ef | 10305 | |
7e806470 | 10306 | if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) |
c19d1205 | 10307 | { |
7e806470 PB |
10308 | /* Thumb-1 cores (except v6-M) require at least one high |
10309 | register in a narrow non flag setting add. */ | |
10310 | if (Rd > 7 || Rn > 7 | |
10311 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2) | |
10312 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr)) | |
c19d1205 | 10313 | { |
7e806470 PB |
10314 | if (Rd == Rn) |
10315 | { | |
10316 | Rn = Rs; | |
10317 | Rs = Rd; | |
10318 | } | |
c19d1205 ZW |
10319 | inst.instruction = T_OPCODE_ADD_HI; |
10320 | inst.instruction |= (Rd & 8) << 4; | |
10321 | inst.instruction |= (Rd & 7); | |
10322 | inst.instruction |= Rn << 3; | |
10323 | return; | |
10324 | } | |
c19d1205 ZW |
10325 | } |
10326 | } | |
c921be7d | 10327 | |
fdfde340 JM |
10328 | constraint (Rd == REG_PC, BAD_PC); |
10329 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); | |
10330 | constraint (Rs == REG_PC, BAD_PC); | |
10331 | reject_bad_reg (Rn); | |
10332 | ||
c19d1205 ZW |
10333 | /* If we get here, it can't be done in 16 bits. */ |
10334 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
10335 | _("shift must be constant")); | |
10336 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10337 | inst.instruction |= Rd << 8; | |
10338 | inst.instruction |= Rs << 16; | |
5f4cb198 NC |
10339 | constraint (Rd == REG_SP && Rs == REG_SP && value > 3, |
10340 | _("shift value over 3 not allowed in thumb mode")); | |
10341 | constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL, | |
10342 | _("only LSL shift allowed in thumb mode")); | |
c19d1205 ZW |
10343 | encode_thumb32_shifted_operand (2); |
10344 | } | |
10345 | } | |
10346 | else | |
10347 | { | |
10348 | constraint (inst.instruction == T_MNEM_adds | |
10349 | || inst.instruction == T_MNEM_subs, | |
10350 | BAD_THUMB32); | |
b99bd4ef | 10351 | |
c19d1205 | 10352 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 10353 | { |
c19d1205 ZW |
10354 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
10355 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
10356 | BAD_HIREG); | |
10357 | ||
10358 | inst.instruction = (inst.instruction == T_MNEM_add | |
10359 | ? 0x0000 : 0x8000); | |
10360 | inst.instruction |= (Rd << 4) | Rs; | |
10361 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
b99bd4ef NC |
10362 | return; |
10363 | } | |
10364 | ||
c19d1205 ZW |
10365 | Rn = inst.operands[2].reg; |
10366 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 10367 | |
c19d1205 ZW |
10368 | /* We now have Rd, Rs, and Rn set to registers. */ |
10369 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 10370 | { |
c19d1205 ZW |
10371 | /* Can't do this for SUB. */ |
10372 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
10373 | inst.instruction = T_OPCODE_ADD_HI; | |
10374 | inst.instruction |= (Rd & 8) << 4; | |
10375 | inst.instruction |= (Rd & 7); | |
10376 | if (Rs == Rd) | |
10377 | inst.instruction |= Rn << 3; | |
10378 | else if (Rn == Rd) | |
10379 | inst.instruction |= Rs << 3; | |
10380 | else | |
10381 | constraint (1, _("dest must overlap one source register")); | |
10382 | } | |
10383 | else | |
10384 | { | |
10385 | inst.instruction = (inst.instruction == T_MNEM_add | |
10386 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
10387 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 10388 | } |
b99bd4ef | 10389 | } |
b99bd4ef NC |
10390 | } |
10391 | ||
c19d1205 ZW |
10392 | static void |
10393 | do_t_adr (void) | |
10394 | { | |
fdfde340 JM |
10395 | unsigned Rd; |
10396 | ||
10397 | Rd = inst.operands[0].reg; | |
10398 | reject_bad_reg (Rd); | |
10399 | ||
10400 | if (unified_syntax && inst.size_req == 0 && Rd <= 7) | |
0110f2b8 PB |
10401 | { |
10402 | /* Defer to section relaxation. */ | |
10403 | inst.relax = inst.instruction; | |
10404 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 | 10405 | inst.instruction |= Rd << 4; |
0110f2b8 PB |
10406 | } |
10407 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 10408 | { |
0110f2b8 | 10409 | /* Generate a 32-bit opcode. */ |
e9f89963 | 10410 | inst.instruction = THUMB_OP32 (inst.instruction); |
fdfde340 | 10411 | inst.instruction |= Rd << 8; |
e9f89963 PB |
10412 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; |
10413 | inst.reloc.pc_rel = 1; | |
10414 | } | |
10415 | else | |
10416 | { | |
0110f2b8 | 10417 | /* Generate a 16-bit opcode. */ |
e9f89963 PB |
10418 | inst.instruction = THUMB_OP16 (inst.instruction); |
10419 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
10420 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
10421 | inst.reloc.pc_rel = 1; | |
b99bd4ef | 10422 | |
fdfde340 | 10423 | inst.instruction |= Rd << 4; |
e9f89963 | 10424 | } |
c19d1205 | 10425 | } |
b99bd4ef | 10426 | |
c19d1205 ZW |
10427 | /* Arithmetic instructions for which there is just one 16-bit |
10428 | instruction encoding, and it allows only two low registers. | |
10429 | For maximal compatibility with ARM syntax, we allow three register | |
10430 | operands even when Thumb-32 instructions are not available, as long | |
10431 | as the first two are identical. For instance, both "sbc r0,r1" and | |
10432 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 10433 | static void |
c19d1205 | 10434 | do_t_arit3 (void) |
b99bd4ef | 10435 | { |
c19d1205 | 10436 | int Rd, Rs, Rn; |
b99bd4ef | 10437 | |
c19d1205 ZW |
10438 | Rd = inst.operands[0].reg; |
10439 | Rs = (inst.operands[1].present | |
10440 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
10441 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
10442 | Rn = inst.operands[2].reg; | |
b99bd4ef | 10443 | |
fdfde340 JM |
10444 | reject_bad_reg (Rd); |
10445 | reject_bad_reg (Rs); | |
10446 | if (inst.operands[2].isreg) | |
10447 | reject_bad_reg (Rn); | |
10448 | ||
c19d1205 | 10449 | if (unified_syntax) |
b99bd4ef | 10450 | { |
c19d1205 ZW |
10451 | if (!inst.operands[2].isreg) |
10452 | { | |
10453 | /* For an immediate, we always generate a 32-bit opcode; | |
10454 | section relaxation will shrink it later if possible. */ | |
10455 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10456 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
10457 | inst.instruction |= Rd << 8; | |
10458 | inst.instruction |= Rs << 16; | |
10459 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10460 | } | |
10461 | else | |
10462 | { | |
e27ec89e PB |
10463 | bfd_boolean narrow; |
10464 | ||
c19d1205 | 10465 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 10466 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 10467 | narrow = !in_it_block (); |
e27ec89e | 10468 | else |
e07e6e58 | 10469 | narrow = in_it_block (); |
e27ec89e PB |
10470 | |
10471 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
10472 | narrow = FALSE; | |
10473 | if (inst.operands[2].shifted) | |
10474 | narrow = FALSE; | |
10475 | if (inst.size_req == 4) | |
10476 | narrow = FALSE; | |
10477 | ||
10478 | if (narrow | |
c19d1205 ZW |
10479 | && Rd == Rs) |
10480 | { | |
10481 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10482 | inst.instruction |= Rd; | |
10483 | inst.instruction |= Rn << 3; | |
10484 | return; | |
10485 | } | |
b99bd4ef | 10486 | |
c19d1205 ZW |
10487 | /* If we get here, it can't be done in 16 bits. */ |
10488 | constraint (inst.operands[2].shifted | |
10489 | && inst.operands[2].immisreg, | |
10490 | _("shift must be constant")); | |
10491 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10492 | inst.instruction |= Rd << 8; | |
10493 | inst.instruction |= Rs << 16; | |
10494 | encode_thumb32_shifted_operand (2); | |
10495 | } | |
a737bd4d | 10496 | } |
c19d1205 | 10497 | else |
b99bd4ef | 10498 | { |
c19d1205 ZW |
10499 | /* On its face this is a lie - the instruction does set the |
10500 | flags. However, the only supported mnemonic in this mode | |
10501 | says it doesn't. */ | |
10502 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 10503 | |
c19d1205 ZW |
10504 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
10505 | _("unshifted register required")); | |
10506 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
10507 | constraint (Rd != Rs, | |
10508 | _("dest and source1 must be the same register")); | |
a737bd4d | 10509 | |
c19d1205 ZW |
10510 | inst.instruction = THUMB_OP16 (inst.instruction); |
10511 | inst.instruction |= Rd; | |
10512 | inst.instruction |= Rn << 3; | |
b99bd4ef | 10513 | } |
a737bd4d | 10514 | } |
b99bd4ef | 10515 | |
c19d1205 ZW |
10516 | /* Similarly, but for instructions where the arithmetic operation is |
10517 | commutative, so we can allow either of them to be different from | |
10518 | the destination operand in a 16-bit instruction. For instance, all | |
10519 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
10520 | accepted. */ | |
10521 | static void | |
10522 | do_t_arit3c (void) | |
a737bd4d | 10523 | { |
c19d1205 | 10524 | int Rd, Rs, Rn; |
b99bd4ef | 10525 | |
c19d1205 ZW |
10526 | Rd = inst.operands[0].reg; |
10527 | Rs = (inst.operands[1].present | |
10528 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
10529 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
10530 | Rn = inst.operands[2].reg; | |
c921be7d | 10531 | |
fdfde340 JM |
10532 | reject_bad_reg (Rd); |
10533 | reject_bad_reg (Rs); | |
10534 | if (inst.operands[2].isreg) | |
10535 | reject_bad_reg (Rn); | |
a737bd4d | 10536 | |
c19d1205 | 10537 | if (unified_syntax) |
a737bd4d | 10538 | { |
c19d1205 | 10539 | if (!inst.operands[2].isreg) |
b99bd4ef | 10540 | { |
c19d1205 ZW |
10541 | /* For an immediate, we always generate a 32-bit opcode; |
10542 | section relaxation will shrink it later if possible. */ | |
10543 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10544 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
10545 | inst.instruction |= Rd << 8; | |
10546 | inst.instruction |= Rs << 16; | |
10547 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 10548 | } |
c19d1205 | 10549 | else |
a737bd4d | 10550 | { |
e27ec89e PB |
10551 | bfd_boolean narrow; |
10552 | ||
c19d1205 | 10553 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 10554 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 10555 | narrow = !in_it_block (); |
e27ec89e | 10556 | else |
e07e6e58 | 10557 | narrow = in_it_block (); |
e27ec89e PB |
10558 | |
10559 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
10560 | narrow = FALSE; | |
10561 | if (inst.operands[2].shifted) | |
10562 | narrow = FALSE; | |
10563 | if (inst.size_req == 4) | |
10564 | narrow = FALSE; | |
10565 | ||
10566 | if (narrow) | |
a737bd4d | 10567 | { |
c19d1205 | 10568 | if (Rd == Rs) |
a737bd4d | 10569 | { |
c19d1205 ZW |
10570 | inst.instruction = THUMB_OP16 (inst.instruction); |
10571 | inst.instruction |= Rd; | |
10572 | inst.instruction |= Rn << 3; | |
10573 | return; | |
a737bd4d | 10574 | } |
c19d1205 | 10575 | if (Rd == Rn) |
a737bd4d | 10576 | { |
c19d1205 ZW |
10577 | inst.instruction = THUMB_OP16 (inst.instruction); |
10578 | inst.instruction |= Rd; | |
10579 | inst.instruction |= Rs << 3; | |
10580 | return; | |
a737bd4d NC |
10581 | } |
10582 | } | |
c19d1205 ZW |
10583 | |
10584 | /* If we get here, it can't be done in 16 bits. */ | |
10585 | constraint (inst.operands[2].shifted | |
10586 | && inst.operands[2].immisreg, | |
10587 | _("shift must be constant")); | |
10588 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10589 | inst.instruction |= Rd << 8; | |
10590 | inst.instruction |= Rs << 16; | |
10591 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 10592 | } |
b99bd4ef | 10593 | } |
c19d1205 ZW |
10594 | else |
10595 | { | |
10596 | /* On its face this is a lie - the instruction does set the | |
10597 | flags. However, the only supported mnemonic in this mode | |
10598 | says it doesn't. */ | |
10599 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 10600 | |
c19d1205 ZW |
10601 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
10602 | _("unshifted register required")); | |
10603 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
10604 | ||
10605 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10606 | inst.instruction |= Rd; | |
10607 | ||
10608 | if (Rd == Rs) | |
10609 | inst.instruction |= Rn << 3; | |
10610 | else if (Rd == Rn) | |
10611 | inst.instruction |= Rs << 3; | |
10612 | else | |
10613 | constraint (1, _("dest must overlap one source register")); | |
10614 | } | |
a737bd4d NC |
10615 | } |
10616 | ||
c19d1205 ZW |
10617 | static void |
10618 | do_t_bfc (void) | |
a737bd4d | 10619 | { |
fdfde340 | 10620 | unsigned Rd; |
c19d1205 ZW |
10621 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
10622 | constraint (msb > 32, _("bit-field extends past end of register")); | |
10623 | /* The instruction encoding stores the LSB and MSB, | |
10624 | not the LSB and width. */ | |
fdfde340 JM |
10625 | Rd = inst.operands[0].reg; |
10626 | reject_bad_reg (Rd); | |
10627 | inst.instruction |= Rd << 8; | |
c19d1205 ZW |
10628 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; |
10629 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
10630 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
10631 | } |
10632 | ||
c19d1205 ZW |
10633 | static void |
10634 | do_t_bfi (void) | |
b99bd4ef | 10635 | { |
fdfde340 | 10636 | int Rd, Rn; |
c19d1205 | 10637 | unsigned int msb; |
b99bd4ef | 10638 | |
fdfde340 JM |
10639 | Rd = inst.operands[0].reg; |
10640 | reject_bad_reg (Rd); | |
10641 | ||
c19d1205 ZW |
10642 | /* #0 in second position is alternative syntax for bfc, which is |
10643 | the same instruction but with REG_PC in the Rm field. */ | |
10644 | if (!inst.operands[1].isreg) | |
fdfde340 JM |
10645 | Rn = REG_PC; |
10646 | else | |
10647 | { | |
10648 | Rn = inst.operands[1].reg; | |
10649 | reject_bad_reg (Rn); | |
10650 | } | |
b99bd4ef | 10651 | |
c19d1205 ZW |
10652 | msb = inst.operands[2].imm + inst.operands[3].imm; |
10653 | constraint (msb > 32, _("bit-field extends past end of register")); | |
10654 | /* The instruction encoding stores the LSB and MSB, | |
10655 | not the LSB and width. */ | |
fdfde340 JM |
10656 | inst.instruction |= Rd << 8; |
10657 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
10658 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
10659 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
10660 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
10661 | } |
10662 | ||
c19d1205 ZW |
10663 | static void |
10664 | do_t_bfx (void) | |
b99bd4ef | 10665 | { |
fdfde340 JM |
10666 | unsigned Rd, Rn; |
10667 | ||
10668 | Rd = inst.operands[0].reg; | |
10669 | Rn = inst.operands[1].reg; | |
10670 | ||
10671 | reject_bad_reg (Rd); | |
10672 | reject_bad_reg (Rn); | |
10673 | ||
c19d1205 ZW |
10674 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
10675 | _("bit-field extends past end of register")); | |
fdfde340 JM |
10676 | inst.instruction |= Rd << 8; |
10677 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
10678 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
10679 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
10680 | inst.instruction |= inst.operands[3].imm - 1; | |
10681 | } | |
b99bd4ef | 10682 | |
c19d1205 ZW |
10683 | /* ARM V5 Thumb BLX (argument parse) |
10684 | BLX <target_addr> which is BLX(1) | |
10685 | BLX <Rm> which is BLX(2) | |
10686 | Unfortunately, there are two different opcodes for this mnemonic. | |
10687 | So, the insns[].value is not used, and the code here zaps values | |
10688 | into inst.instruction. | |
b99bd4ef | 10689 | |
c19d1205 ZW |
10690 | ??? How to take advantage of the additional two bits of displacement |
10691 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 10692 | |
c19d1205 ZW |
10693 | static void |
10694 | do_t_blx (void) | |
10695 | { | |
e07e6e58 NC |
10696 | set_it_insn_type_last (); |
10697 | ||
c19d1205 | 10698 | if (inst.operands[0].isreg) |
fdfde340 JM |
10699 | { |
10700 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); | |
10701 | /* We have a register, so this is BLX(2). */ | |
10702 | inst.instruction |= inst.operands[0].reg << 3; | |
10703 | } | |
b99bd4ef NC |
10704 | else |
10705 | { | |
c19d1205 | 10706 | /* No register. This must be BLX(1). */ |
2fc8bdac | 10707 | inst.instruction = 0xf000e800; |
0855e32b | 10708 | encode_branch (BFD_RELOC_THUMB_PCREL_BLX); |
b99bd4ef NC |
10709 | } |
10710 | } | |
10711 | ||
c19d1205 ZW |
10712 | static void |
10713 | do_t_branch (void) | |
b99bd4ef | 10714 | { |
0110f2b8 | 10715 | int opcode; |
dfa9f0d5 | 10716 | int cond; |
9ae92b05 | 10717 | int reloc; |
dfa9f0d5 | 10718 | |
e07e6e58 NC |
10719 | cond = inst.cond; |
10720 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); | |
10721 | ||
10722 | if (in_it_block ()) | |
dfa9f0d5 PB |
10723 | { |
10724 | /* Conditional branches inside IT blocks are encoded as unconditional | |
477330fc | 10725 | branches. */ |
dfa9f0d5 | 10726 | cond = COND_ALWAYS; |
dfa9f0d5 PB |
10727 | } |
10728 | else | |
10729 | cond = inst.cond; | |
10730 | ||
10731 | if (cond != COND_ALWAYS) | |
0110f2b8 PB |
10732 | opcode = T_MNEM_bcond; |
10733 | else | |
10734 | opcode = inst.instruction; | |
10735 | ||
12d6b0b7 RS |
10736 | if (unified_syntax |
10737 | && (inst.size_req == 4 | |
10960bfb PB |
10738 | || (inst.size_req != 2 |
10739 | && (inst.operands[0].hasreloc | |
10740 | || inst.reloc.exp.X_op == O_constant)))) | |
c19d1205 | 10741 | { |
0110f2b8 | 10742 | inst.instruction = THUMB_OP32(opcode); |
dfa9f0d5 | 10743 | if (cond == COND_ALWAYS) |
9ae92b05 | 10744 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
10745 | else |
10746 | { | |
9c2799c2 | 10747 | gas_assert (cond != 0xF); |
dfa9f0d5 | 10748 | inst.instruction |= cond << 22; |
9ae92b05 | 10749 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH20; |
c19d1205 ZW |
10750 | } |
10751 | } | |
b99bd4ef NC |
10752 | else |
10753 | { | |
0110f2b8 | 10754 | inst.instruction = THUMB_OP16(opcode); |
dfa9f0d5 | 10755 | if (cond == COND_ALWAYS) |
9ae92b05 | 10756 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH12; |
c19d1205 | 10757 | else |
b99bd4ef | 10758 | { |
dfa9f0d5 | 10759 | inst.instruction |= cond << 8; |
9ae92b05 | 10760 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 10761 | } |
0110f2b8 PB |
10762 | /* Allow section relaxation. */ |
10763 | if (unified_syntax && inst.size_req != 2) | |
10764 | inst.relax = opcode; | |
b99bd4ef | 10765 | } |
9ae92b05 | 10766 | inst.reloc.type = reloc; |
c19d1205 | 10767 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
10768 | } |
10769 | ||
8884b720 | 10770 | /* Actually do the work for Thumb state bkpt and hlt. The only difference |
bacebabc | 10771 | between the two is the maximum immediate allowed - which is passed in |
8884b720 | 10772 | RANGE. */ |
b99bd4ef | 10773 | static void |
8884b720 | 10774 | do_t_bkpt_hlt1 (int range) |
b99bd4ef | 10775 | { |
dfa9f0d5 PB |
10776 | constraint (inst.cond != COND_ALWAYS, |
10777 | _("instruction is always unconditional")); | |
c19d1205 | 10778 | if (inst.operands[0].present) |
b99bd4ef | 10779 | { |
8884b720 | 10780 | constraint (inst.operands[0].imm > range, |
c19d1205 ZW |
10781 | _("immediate value out of range")); |
10782 | inst.instruction |= inst.operands[0].imm; | |
b99bd4ef | 10783 | } |
8884b720 MGD |
10784 | |
10785 | set_it_insn_type (NEUTRAL_IT_INSN); | |
10786 | } | |
10787 | ||
10788 | static void | |
10789 | do_t_hlt (void) | |
10790 | { | |
10791 | do_t_bkpt_hlt1 (63); | |
10792 | } | |
10793 | ||
10794 | static void | |
10795 | do_t_bkpt (void) | |
10796 | { | |
10797 | do_t_bkpt_hlt1 (255); | |
b99bd4ef NC |
10798 | } |
10799 | ||
10800 | static void | |
c19d1205 | 10801 | do_t_branch23 (void) |
b99bd4ef | 10802 | { |
e07e6e58 | 10803 | set_it_insn_type_last (); |
0855e32b | 10804 | encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23); |
fa94de6b | 10805 | |
0855e32b NS |
10806 | /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in |
10807 | this file. We used to simply ignore the PLT reloc type here -- | |
10808 | the branch encoding is now needed to deal with TLSCALL relocs. | |
10809 | So if we see a PLT reloc now, put it back to how it used to be to | |
10810 | keep the preexisting behaviour. */ | |
10811 | if (inst.reloc.type == BFD_RELOC_ARM_PLT32) | |
10812 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
90e4755a | 10813 | |
4343666d | 10814 | #if defined(OBJ_COFF) |
c19d1205 ZW |
10815 | /* If the destination of the branch is a defined symbol which does not have |
10816 | the THUMB_FUNC attribute, then we must be calling a function which has | |
10817 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
10818 | function and change the branch to refer to that function instead. */ | |
10819 | if ( inst.reloc.exp.X_op == O_symbol | |
10820 | && inst.reloc.exp.X_add_symbol != NULL | |
10821 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
10822 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
10823 | inst.reloc.exp.X_add_symbol = | |
10824 | find_real_start (inst.reloc.exp.X_add_symbol); | |
4343666d | 10825 | #endif |
90e4755a RE |
10826 | } |
10827 | ||
10828 | static void | |
c19d1205 | 10829 | do_t_bx (void) |
90e4755a | 10830 | { |
e07e6e58 | 10831 | set_it_insn_type_last (); |
c19d1205 ZW |
10832 | inst.instruction |= inst.operands[0].reg << 3; |
10833 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
10834 | should cause the alignment to be checked once it is known. This is | |
10835 | because BX PC only works if the instruction is word aligned. */ | |
10836 | } | |
90e4755a | 10837 | |
c19d1205 ZW |
10838 | static void |
10839 | do_t_bxj (void) | |
10840 | { | |
fdfde340 | 10841 | int Rm; |
90e4755a | 10842 | |
e07e6e58 | 10843 | set_it_insn_type_last (); |
fdfde340 JM |
10844 | Rm = inst.operands[0].reg; |
10845 | reject_bad_reg (Rm); | |
10846 | inst.instruction |= Rm << 16; | |
90e4755a RE |
10847 | } |
10848 | ||
10849 | static void | |
c19d1205 | 10850 | do_t_clz (void) |
90e4755a | 10851 | { |
fdfde340 JM |
10852 | unsigned Rd; |
10853 | unsigned Rm; | |
10854 | ||
10855 | Rd = inst.operands[0].reg; | |
10856 | Rm = inst.operands[1].reg; | |
10857 | ||
10858 | reject_bad_reg (Rd); | |
10859 | reject_bad_reg (Rm); | |
10860 | ||
10861 | inst.instruction |= Rd << 8; | |
10862 | inst.instruction |= Rm << 16; | |
10863 | inst.instruction |= Rm; | |
c19d1205 | 10864 | } |
90e4755a | 10865 | |
dfa9f0d5 PB |
10866 | static void |
10867 | do_t_cps (void) | |
10868 | { | |
e07e6e58 | 10869 | set_it_insn_type (OUTSIDE_IT_INSN); |
dfa9f0d5 PB |
10870 | inst.instruction |= inst.operands[0].imm; |
10871 | } | |
10872 | ||
c19d1205 ZW |
10873 | static void |
10874 | do_t_cpsi (void) | |
10875 | { | |
e07e6e58 | 10876 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 | 10877 | if (unified_syntax |
62b3e311 PB |
10878 | && (inst.operands[1].present || inst.size_req == 4) |
10879 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) | |
90e4755a | 10880 | { |
c19d1205 ZW |
10881 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
10882 | inst.instruction = 0xf3af8000; | |
10883 | inst.instruction |= imod << 9; | |
10884 | inst.instruction |= inst.operands[0].imm << 5; | |
10885 | if (inst.operands[1].present) | |
10886 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 10887 | } |
c19d1205 | 10888 | else |
90e4755a | 10889 | { |
62b3e311 PB |
10890 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) |
10891 | && (inst.operands[0].imm & 4), | |
10892 | _("selected processor does not support 'A' form " | |
10893 | "of this instruction")); | |
10894 | constraint (inst.operands[1].present || inst.size_req == 4, | |
c19d1205 ZW |
10895 | _("Thumb does not support the 2-argument " |
10896 | "form of this instruction")); | |
10897 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 10898 | } |
90e4755a RE |
10899 | } |
10900 | ||
c19d1205 ZW |
10901 | /* THUMB CPY instruction (argument parse). */ |
10902 | ||
90e4755a | 10903 | static void |
c19d1205 | 10904 | do_t_cpy (void) |
90e4755a | 10905 | { |
c19d1205 | 10906 | if (inst.size_req == 4) |
90e4755a | 10907 | { |
c19d1205 ZW |
10908 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
10909 | inst.instruction |= inst.operands[0].reg << 8; | |
10910 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 10911 | } |
c19d1205 | 10912 | else |
90e4755a | 10913 | { |
c19d1205 ZW |
10914 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
10915 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
10916 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 10917 | } |
90e4755a RE |
10918 | } |
10919 | ||
90e4755a | 10920 | static void |
25fe350b | 10921 | do_t_cbz (void) |
90e4755a | 10922 | { |
e07e6e58 | 10923 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
10924 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
10925 | inst.instruction |= inst.operands[0].reg; | |
10926 | inst.reloc.pc_rel = 1; | |
10927 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
10928 | } | |
90e4755a | 10929 | |
62b3e311 PB |
10930 | static void |
10931 | do_t_dbg (void) | |
10932 | { | |
10933 | inst.instruction |= inst.operands[0].imm; | |
10934 | } | |
10935 | ||
10936 | static void | |
10937 | do_t_div (void) | |
10938 | { | |
fdfde340 JM |
10939 | unsigned Rd, Rn, Rm; |
10940 | ||
10941 | Rd = inst.operands[0].reg; | |
10942 | Rn = (inst.operands[1].present | |
10943 | ? inst.operands[1].reg : Rd); | |
10944 | Rm = inst.operands[2].reg; | |
10945 | ||
10946 | reject_bad_reg (Rd); | |
10947 | reject_bad_reg (Rn); | |
10948 | reject_bad_reg (Rm); | |
10949 | ||
10950 | inst.instruction |= Rd << 8; | |
10951 | inst.instruction |= Rn << 16; | |
10952 | inst.instruction |= Rm; | |
62b3e311 PB |
10953 | } |
10954 | ||
c19d1205 ZW |
10955 | static void |
10956 | do_t_hint (void) | |
10957 | { | |
10958 | if (unified_syntax && inst.size_req == 4) | |
10959 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10960 | else | |
10961 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10962 | } | |
90e4755a | 10963 | |
c19d1205 ZW |
10964 | static void |
10965 | do_t_it (void) | |
10966 | { | |
10967 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e | 10968 | |
e07e6e58 NC |
10969 | set_it_insn_type (IT_INSN); |
10970 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
10971 | now_it.cc = cond; | |
5a01bb1d | 10972 | now_it.warn_deprecated = FALSE; |
e27ec89e PB |
10973 | |
10974 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 10975 | if ((cond & 0x1) == 0x0) |
90e4755a | 10976 | { |
c19d1205 | 10977 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 10978 | |
c19d1205 | 10979 | if ((mask & 0x7) == 0) |
5a01bb1d MGD |
10980 | { |
10981 | /* No conversion needed. */ | |
10982 | now_it.block_length = 1; | |
10983 | } | |
c19d1205 | 10984 | else if ((mask & 0x3) == 0) |
5a01bb1d MGD |
10985 | { |
10986 | mask ^= 0x8; | |
10987 | now_it.block_length = 2; | |
10988 | } | |
e27ec89e | 10989 | else if ((mask & 0x1) == 0) |
5a01bb1d MGD |
10990 | { |
10991 | mask ^= 0xC; | |
10992 | now_it.block_length = 3; | |
10993 | } | |
c19d1205 | 10994 | else |
5a01bb1d MGD |
10995 | { |
10996 | mask ^= 0xE; | |
10997 | now_it.block_length = 4; | |
10998 | } | |
90e4755a | 10999 | |
e27ec89e PB |
11000 | inst.instruction &= 0xfff0; |
11001 | inst.instruction |= mask; | |
c19d1205 | 11002 | } |
90e4755a | 11003 | |
c19d1205 ZW |
11004 | inst.instruction |= cond << 4; |
11005 | } | |
90e4755a | 11006 | |
3c707909 PB |
11007 | /* Helper function used for both push/pop and ldm/stm. */ |
11008 | static void | |
11009 | encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) | |
11010 | { | |
11011 | bfd_boolean load; | |
11012 | ||
11013 | load = (inst.instruction & (1 << 20)) != 0; | |
11014 | ||
11015 | if (mask & (1 << 13)) | |
11016 | inst.error = _("SP not allowed in register list"); | |
1e5b0379 NC |
11017 | |
11018 | if ((mask & (1 << base)) != 0 | |
11019 | && writeback) | |
11020 | inst.error = _("having the base register in the register list when " | |
11021 | "using write back is UNPREDICTABLE"); | |
11022 | ||
3c707909 PB |
11023 | if (load) |
11024 | { | |
e07e6e58 | 11025 | if (mask & (1 << 15)) |
477330fc RM |
11026 | { |
11027 | if (mask & (1 << 14)) | |
11028 | inst.error = _("LR and PC should not both be in register list"); | |
11029 | else | |
11030 | set_it_insn_type_last (); | |
11031 | } | |
3c707909 PB |
11032 | } |
11033 | else | |
11034 | { | |
11035 | if (mask & (1 << 15)) | |
11036 | inst.error = _("PC not allowed in register list"); | |
3c707909 PB |
11037 | } |
11038 | ||
11039 | if ((mask & (mask - 1)) == 0) | |
11040 | { | |
11041 | /* Single register transfers implemented as str/ldr. */ | |
11042 | if (writeback) | |
11043 | { | |
11044 | if (inst.instruction & (1 << 23)) | |
11045 | inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ | |
11046 | else | |
11047 | inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ | |
11048 | } | |
11049 | else | |
11050 | { | |
11051 | if (inst.instruction & (1 << 23)) | |
11052 | inst.instruction = 0x00800000; /* ia -> [base] */ | |
11053 | else | |
11054 | inst.instruction = 0x00000c04; /* db -> [base, #-4] */ | |
11055 | } | |
11056 | ||
11057 | inst.instruction |= 0xf8400000; | |
11058 | if (load) | |
11059 | inst.instruction |= 0x00100000; | |
11060 | ||
5f4273c7 | 11061 | mask = ffs (mask) - 1; |
3c707909 PB |
11062 | mask <<= 12; |
11063 | } | |
11064 | else if (writeback) | |
11065 | inst.instruction |= WRITE_BACK; | |
11066 | ||
11067 | inst.instruction |= mask; | |
11068 | inst.instruction |= base << 16; | |
11069 | } | |
11070 | ||
c19d1205 ZW |
11071 | static void |
11072 | do_t_ldmstm (void) | |
11073 | { | |
11074 | /* This really doesn't seem worth it. */ | |
11075 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
11076 | _("expression too complex")); | |
11077 | constraint (inst.operands[1].writeback, | |
11078 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 11079 | |
c19d1205 ZW |
11080 | if (unified_syntax) |
11081 | { | |
3c707909 PB |
11082 | bfd_boolean narrow; |
11083 | unsigned mask; | |
11084 | ||
11085 | narrow = FALSE; | |
c19d1205 ZW |
11086 | /* See if we can use a 16-bit instruction. */ |
11087 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
11088 | && inst.size_req != 4 | |
3c707909 | 11089 | && !(inst.operands[1].imm & ~0xff)) |
90e4755a | 11090 | { |
3c707909 | 11091 | mask = 1 << inst.operands[0].reg; |
90e4755a | 11092 | |
eab4f823 | 11093 | if (inst.operands[0].reg <= 7) |
90e4755a | 11094 | { |
3c707909 | 11095 | if (inst.instruction == T_MNEM_stmia |
eab4f823 MGD |
11096 | ? inst.operands[0].writeback |
11097 | : (inst.operands[0].writeback | |
11098 | == !(inst.operands[1].imm & mask))) | |
477330fc | 11099 | { |
eab4f823 MGD |
11100 | if (inst.instruction == T_MNEM_stmia |
11101 | && (inst.operands[1].imm & mask) | |
11102 | && (inst.operands[1].imm & (mask - 1))) | |
11103 | as_warn (_("value stored for r%d is UNKNOWN"), | |
11104 | inst.operands[0].reg); | |
3c707909 | 11105 | |
eab4f823 MGD |
11106 | inst.instruction = THUMB_OP16 (inst.instruction); |
11107 | inst.instruction |= inst.operands[0].reg << 8; | |
11108 | inst.instruction |= inst.operands[1].imm; | |
11109 | narrow = TRUE; | |
11110 | } | |
11111 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
11112 | { | |
11113 | /* This means 1 register in reg list one of 3 situations: | |
11114 | 1. Instruction is stmia, but without writeback. | |
11115 | 2. lmdia without writeback, but with Rn not in | |
477330fc | 11116 | reglist. |
eab4f823 MGD |
11117 | 3. ldmia with writeback, but with Rn in reglist. |
11118 | Case 3 is UNPREDICTABLE behaviour, so we handle | |
11119 | case 1 and 2 which can be converted into a 16-bit | |
11120 | str or ldr. The SP cases are handled below. */ | |
11121 | unsigned long opcode; | |
11122 | /* First, record an error for Case 3. */ | |
11123 | if (inst.operands[1].imm & mask | |
11124 | && inst.operands[0].writeback) | |
fa94de6b | 11125 | inst.error = |
eab4f823 MGD |
11126 | _("having the base register in the register list when " |
11127 | "using write back is UNPREDICTABLE"); | |
fa94de6b RM |
11128 | |
11129 | opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str | |
eab4f823 MGD |
11130 | : T_MNEM_ldr); |
11131 | inst.instruction = THUMB_OP16 (opcode); | |
11132 | inst.instruction |= inst.operands[0].reg << 3; | |
11133 | inst.instruction |= (ffs (inst.operands[1].imm)-1); | |
11134 | narrow = TRUE; | |
11135 | } | |
90e4755a | 11136 | } |
eab4f823 | 11137 | else if (inst.operands[0] .reg == REG_SP) |
90e4755a | 11138 | { |
eab4f823 MGD |
11139 | if (inst.operands[0].writeback) |
11140 | { | |
fa94de6b | 11141 | inst.instruction = |
eab4f823 | 11142 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
477330fc | 11143 | ? T_MNEM_push : T_MNEM_pop); |
eab4f823 | 11144 | inst.instruction |= inst.operands[1].imm; |
477330fc | 11145 | narrow = TRUE; |
eab4f823 MGD |
11146 | } |
11147 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
11148 | { | |
fa94de6b | 11149 | inst.instruction = |
eab4f823 | 11150 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
477330fc | 11151 | ? T_MNEM_str_sp : T_MNEM_ldr_sp); |
eab4f823 | 11152 | inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8); |
477330fc | 11153 | narrow = TRUE; |
eab4f823 | 11154 | } |
90e4755a | 11155 | } |
3c707909 PB |
11156 | } |
11157 | ||
11158 | if (!narrow) | |
11159 | { | |
c19d1205 ZW |
11160 | if (inst.instruction < 0xffff) |
11161 | inst.instruction = THUMB_OP32 (inst.instruction); | |
3c707909 | 11162 | |
5f4273c7 NC |
11163 | encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm, |
11164 | inst.operands[0].writeback); | |
90e4755a RE |
11165 | } |
11166 | } | |
c19d1205 | 11167 | else |
90e4755a | 11168 | { |
c19d1205 ZW |
11169 | constraint (inst.operands[0].reg > 7 |
11170 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
1198ca51 PB |
11171 | constraint (inst.instruction != T_MNEM_ldmia |
11172 | && inst.instruction != T_MNEM_stmia, | |
11173 | _("Thumb-2 instruction only valid in unified syntax")); | |
c19d1205 | 11174 | if (inst.instruction == T_MNEM_stmia) |
f03698e6 | 11175 | { |
c19d1205 ZW |
11176 | if (!inst.operands[0].writeback) |
11177 | as_warn (_("this instruction will write back the base register")); | |
11178 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
11179 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
1e5b0379 | 11180 | as_warn (_("value stored for r%d is UNKNOWN"), |
c19d1205 | 11181 | inst.operands[0].reg); |
f03698e6 | 11182 | } |
c19d1205 | 11183 | else |
90e4755a | 11184 | { |
c19d1205 ZW |
11185 | if (!inst.operands[0].writeback |
11186 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
11187 | as_warn (_("this instruction will write back the base register")); | |
11188 | else if (inst.operands[0].writeback | |
11189 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
11190 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
11191 | } |
11192 | ||
c19d1205 ZW |
11193 | inst.instruction = THUMB_OP16 (inst.instruction); |
11194 | inst.instruction |= inst.operands[0].reg << 8; | |
11195 | inst.instruction |= inst.operands[1].imm; | |
11196 | } | |
11197 | } | |
e28cd48c | 11198 | |
c19d1205 ZW |
11199 | static void |
11200 | do_t_ldrex (void) | |
11201 | { | |
11202 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
11203 | || inst.operands[1].postind || inst.operands[1].writeback | |
11204 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
11205 | || inst.operands[1].negative, | |
01cfc07f | 11206 | BAD_ADDR_MODE); |
e28cd48c | 11207 | |
5be8be5d DG |
11208 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
11209 | ||
c19d1205 ZW |
11210 | inst.instruction |= inst.operands[0].reg << 12; |
11211 | inst.instruction |= inst.operands[1].reg << 16; | |
11212 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
11213 | } | |
e28cd48c | 11214 | |
c19d1205 ZW |
11215 | static void |
11216 | do_t_ldrexd (void) | |
11217 | { | |
11218 | if (!inst.operands[1].present) | |
1cac9012 | 11219 | { |
c19d1205 ZW |
11220 | constraint (inst.operands[0].reg == REG_LR, |
11221 | _("r14 not allowed as first register " | |
11222 | "when second register is omitted")); | |
11223 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 11224 | } |
c19d1205 ZW |
11225 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
11226 | BAD_OVERLAP); | |
b99bd4ef | 11227 | |
c19d1205 ZW |
11228 | inst.instruction |= inst.operands[0].reg << 12; |
11229 | inst.instruction |= inst.operands[1].reg << 8; | |
11230 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
11231 | } |
11232 | ||
11233 | static void | |
c19d1205 | 11234 | do_t_ldst (void) |
b99bd4ef | 11235 | { |
0110f2b8 PB |
11236 | unsigned long opcode; |
11237 | int Rn; | |
11238 | ||
e07e6e58 NC |
11239 | if (inst.operands[0].isreg |
11240 | && !inst.operands[0].preind | |
11241 | && inst.operands[0].reg == REG_PC) | |
11242 | set_it_insn_type_last (); | |
11243 | ||
0110f2b8 | 11244 | opcode = inst.instruction; |
c19d1205 | 11245 | if (unified_syntax) |
b99bd4ef | 11246 | { |
53365c0d PB |
11247 | if (!inst.operands[1].isreg) |
11248 | { | |
11249 | if (opcode <= 0xffff) | |
11250 | inst.instruction = THUMB_OP32 (opcode); | |
8335d6aa | 11251 | if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE)) |
53365c0d PB |
11252 | return; |
11253 | } | |
0110f2b8 PB |
11254 | if (inst.operands[1].isreg |
11255 | && !inst.operands[1].writeback | |
c19d1205 ZW |
11256 | && !inst.operands[1].shifted && !inst.operands[1].postind |
11257 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
11258 | && opcode <= 0xffff |
11259 | && inst.size_req != 4) | |
c19d1205 | 11260 | { |
0110f2b8 PB |
11261 | /* Insn may have a 16-bit form. */ |
11262 | Rn = inst.operands[1].reg; | |
11263 | if (inst.operands[1].immisreg) | |
11264 | { | |
11265 | inst.instruction = THUMB_OP16 (opcode); | |
5f4273c7 | 11266 | /* [Rn, Rik] */ |
0110f2b8 PB |
11267 | if (Rn <= 7 && inst.operands[1].imm <= 7) |
11268 | goto op16; | |
5be8be5d DG |
11269 | else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str) |
11270 | reject_bad_reg (inst.operands[1].imm); | |
0110f2b8 PB |
11271 | } |
11272 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
11273 | && opcode != T_MNEM_ldrsb) | |
11274 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
11275 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
11276 | { | |
11277 | /* [Rn, #const] */ | |
11278 | if (Rn > 7) | |
11279 | { | |
11280 | if (Rn == REG_PC) | |
11281 | { | |
11282 | if (inst.reloc.pc_rel) | |
11283 | opcode = T_MNEM_ldr_pc2; | |
11284 | else | |
11285 | opcode = T_MNEM_ldr_pc; | |
11286 | } | |
11287 | else | |
11288 | { | |
11289 | if (opcode == T_MNEM_ldr) | |
11290 | opcode = T_MNEM_ldr_sp; | |
11291 | else | |
11292 | opcode = T_MNEM_str_sp; | |
11293 | } | |
11294 | inst.instruction = inst.operands[0].reg << 8; | |
11295 | } | |
11296 | else | |
11297 | { | |
11298 | inst.instruction = inst.operands[0].reg; | |
11299 | inst.instruction |= inst.operands[1].reg << 3; | |
11300 | } | |
11301 | inst.instruction |= THUMB_OP16 (opcode); | |
11302 | if (inst.size_req == 2) | |
11303 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
11304 | else | |
11305 | inst.relax = opcode; | |
11306 | return; | |
11307 | } | |
c19d1205 | 11308 | } |
0110f2b8 | 11309 | /* Definitely a 32-bit variant. */ |
5be8be5d | 11310 | |
8d67f500 NC |
11311 | /* Warning for Erratum 752419. */ |
11312 | if (opcode == T_MNEM_ldr | |
11313 | && inst.operands[0].reg == REG_SP | |
11314 | && inst.operands[1].writeback == 1 | |
11315 | && !inst.operands[1].immisreg) | |
11316 | { | |
11317 | if (no_cpu_selected () | |
11318 | || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7) | |
477330fc RM |
11319 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a) |
11320 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r))) | |
8d67f500 NC |
11321 | as_warn (_("This instruction may be unpredictable " |
11322 | "if executed on M-profile cores " | |
11323 | "with interrupts enabled.")); | |
11324 | } | |
11325 | ||
5be8be5d | 11326 | /* Do some validations regarding addressing modes. */ |
1be5fd2e | 11327 | if (inst.operands[1].immisreg) |
5be8be5d DG |
11328 | reject_bad_reg (inst.operands[1].imm); |
11329 | ||
1be5fd2e NC |
11330 | constraint (inst.operands[1].writeback == 1 |
11331 | && inst.operands[0].reg == inst.operands[1].reg, | |
11332 | BAD_OVERLAP); | |
11333 | ||
0110f2b8 | 11334 | inst.instruction = THUMB_OP32 (opcode); |
c19d1205 ZW |
11335 | inst.instruction |= inst.operands[0].reg << 12; |
11336 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
1be5fd2e | 11337 | check_ldr_r15_aligned (); |
b99bd4ef NC |
11338 | return; |
11339 | } | |
11340 | ||
c19d1205 ZW |
11341 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
11342 | ||
11343 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 11344 | { |
c19d1205 ZW |
11345 | /* Only [Rn,Rm] is acceptable. */ |
11346 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
11347 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
11348 | || inst.operands[1].postind || inst.operands[1].shifted | |
11349 | || inst.operands[1].negative, | |
11350 | _("Thumb does not support this addressing mode")); | |
11351 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11352 | goto op16; | |
b99bd4ef | 11353 | } |
5f4273c7 | 11354 | |
c19d1205 ZW |
11355 | inst.instruction = THUMB_OP16 (inst.instruction); |
11356 | if (!inst.operands[1].isreg) | |
8335d6aa | 11357 | if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE)) |
c19d1205 | 11358 | return; |
b99bd4ef | 11359 | |
c19d1205 ZW |
11360 | constraint (!inst.operands[1].preind |
11361 | || inst.operands[1].shifted | |
11362 | || inst.operands[1].writeback, | |
11363 | _("Thumb does not support this addressing mode")); | |
11364 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 11365 | { |
c19d1205 ZW |
11366 | constraint (inst.instruction & 0x0600, |
11367 | _("byte or halfword not valid for base register")); | |
11368 | constraint (inst.operands[1].reg == REG_PC | |
11369 | && !(inst.instruction & THUMB_LOAD_BIT), | |
11370 | _("r15 based store not allowed")); | |
11371 | constraint (inst.operands[1].immisreg, | |
11372 | _("invalid base register for register offset")); | |
b99bd4ef | 11373 | |
c19d1205 ZW |
11374 | if (inst.operands[1].reg == REG_PC) |
11375 | inst.instruction = T_OPCODE_LDR_PC; | |
11376 | else if (inst.instruction & THUMB_LOAD_BIT) | |
11377 | inst.instruction = T_OPCODE_LDR_SP; | |
11378 | else | |
11379 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 11380 | |
c19d1205 ZW |
11381 | inst.instruction |= inst.operands[0].reg << 8; |
11382 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
11383 | return; | |
11384 | } | |
90e4755a | 11385 | |
c19d1205 ZW |
11386 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
11387 | if (!inst.operands[1].immisreg) | |
11388 | { | |
11389 | /* Immediate offset. */ | |
11390 | inst.instruction |= inst.operands[0].reg; | |
11391 | inst.instruction |= inst.operands[1].reg << 3; | |
11392 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
11393 | return; | |
11394 | } | |
90e4755a | 11395 | |
c19d1205 ZW |
11396 | /* Register offset. */ |
11397 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
11398 | constraint (inst.operands[1].negative, | |
11399 | _("Thumb does not support this addressing mode")); | |
90e4755a | 11400 | |
c19d1205 ZW |
11401 | op16: |
11402 | switch (inst.instruction) | |
11403 | { | |
11404 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
11405 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
11406 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
11407 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
11408 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
11409 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
11410 | case 0x5600 /* ldrsb */: | |
11411 | case 0x5e00 /* ldrsh */: break; | |
11412 | default: abort (); | |
11413 | } | |
90e4755a | 11414 | |
c19d1205 ZW |
11415 | inst.instruction |= inst.operands[0].reg; |
11416 | inst.instruction |= inst.operands[1].reg << 3; | |
11417 | inst.instruction |= inst.operands[1].imm << 6; | |
11418 | } | |
90e4755a | 11419 | |
c19d1205 ZW |
11420 | static void |
11421 | do_t_ldstd (void) | |
11422 | { | |
11423 | if (!inst.operands[1].present) | |
b99bd4ef | 11424 | { |
c19d1205 ZW |
11425 | inst.operands[1].reg = inst.operands[0].reg + 1; |
11426 | constraint (inst.operands[0].reg == REG_LR, | |
11427 | _("r14 not allowed here")); | |
bd340a04 | 11428 | constraint (inst.operands[0].reg == REG_R12, |
477330fc | 11429 | _("r12 not allowed here")); |
b99bd4ef | 11430 | } |
bd340a04 MGD |
11431 | |
11432 | if (inst.operands[2].writeback | |
11433 | && (inst.operands[0].reg == inst.operands[2].reg | |
11434 | || inst.operands[1].reg == inst.operands[2].reg)) | |
11435 | as_warn (_("base register written back, and overlaps " | |
477330fc | 11436 | "one of transfer registers")); |
bd340a04 | 11437 | |
c19d1205 ZW |
11438 | inst.instruction |= inst.operands[0].reg << 12; |
11439 | inst.instruction |= inst.operands[1].reg << 8; | |
11440 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
b99bd4ef NC |
11441 | } |
11442 | ||
c19d1205 ZW |
11443 | static void |
11444 | do_t_ldstt (void) | |
11445 | { | |
11446 | inst.instruction |= inst.operands[0].reg << 12; | |
11447 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
11448 | } | |
a737bd4d | 11449 | |
b99bd4ef | 11450 | static void |
c19d1205 | 11451 | do_t_mla (void) |
b99bd4ef | 11452 | { |
fdfde340 | 11453 | unsigned Rd, Rn, Rm, Ra; |
c921be7d | 11454 | |
fdfde340 JM |
11455 | Rd = inst.operands[0].reg; |
11456 | Rn = inst.operands[1].reg; | |
11457 | Rm = inst.operands[2].reg; | |
11458 | Ra = inst.operands[3].reg; | |
11459 | ||
11460 | reject_bad_reg (Rd); | |
11461 | reject_bad_reg (Rn); | |
11462 | reject_bad_reg (Rm); | |
11463 | reject_bad_reg (Ra); | |
11464 | ||
11465 | inst.instruction |= Rd << 8; | |
11466 | inst.instruction |= Rn << 16; | |
11467 | inst.instruction |= Rm; | |
11468 | inst.instruction |= Ra << 12; | |
c19d1205 | 11469 | } |
b99bd4ef | 11470 | |
c19d1205 ZW |
11471 | static void |
11472 | do_t_mlal (void) | |
11473 | { | |
fdfde340 JM |
11474 | unsigned RdLo, RdHi, Rn, Rm; |
11475 | ||
11476 | RdLo = inst.operands[0].reg; | |
11477 | RdHi = inst.operands[1].reg; | |
11478 | Rn = inst.operands[2].reg; | |
11479 | Rm = inst.operands[3].reg; | |
11480 | ||
11481 | reject_bad_reg (RdLo); | |
11482 | reject_bad_reg (RdHi); | |
11483 | reject_bad_reg (Rn); | |
11484 | reject_bad_reg (Rm); | |
11485 | ||
11486 | inst.instruction |= RdLo << 12; | |
11487 | inst.instruction |= RdHi << 8; | |
11488 | inst.instruction |= Rn << 16; | |
11489 | inst.instruction |= Rm; | |
c19d1205 | 11490 | } |
b99bd4ef | 11491 | |
c19d1205 ZW |
11492 | static void |
11493 | do_t_mov_cmp (void) | |
11494 | { | |
fdfde340 JM |
11495 | unsigned Rn, Rm; |
11496 | ||
11497 | Rn = inst.operands[0].reg; | |
11498 | Rm = inst.operands[1].reg; | |
11499 | ||
e07e6e58 NC |
11500 | if (Rn == REG_PC) |
11501 | set_it_insn_type_last (); | |
11502 | ||
c19d1205 | 11503 | if (unified_syntax) |
b99bd4ef | 11504 | { |
c19d1205 ZW |
11505 | int r0off = (inst.instruction == T_MNEM_mov |
11506 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 11507 | unsigned long opcode; |
3d388997 PB |
11508 | bfd_boolean narrow; |
11509 | bfd_boolean low_regs; | |
11510 | ||
fdfde340 | 11511 | low_regs = (Rn <= 7 && Rm <= 7); |
0110f2b8 | 11512 | opcode = inst.instruction; |
e07e6e58 | 11513 | if (in_it_block ()) |
0110f2b8 | 11514 | narrow = opcode != T_MNEM_movs; |
3d388997 | 11515 | else |
0110f2b8 | 11516 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
11517 | if (inst.size_req == 4 |
11518 | || inst.operands[1].shifted) | |
11519 | narrow = FALSE; | |
11520 | ||
efd81785 PB |
11521 | /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ |
11522 | if (opcode == T_MNEM_movs && inst.operands[1].isreg | |
11523 | && !inst.operands[1].shifted | |
fdfde340 JM |
11524 | && Rn == REG_PC |
11525 | && Rm == REG_LR) | |
efd81785 PB |
11526 | { |
11527 | inst.instruction = T2_SUBS_PC_LR; | |
11528 | return; | |
11529 | } | |
11530 | ||
fdfde340 JM |
11531 | if (opcode == T_MNEM_cmp) |
11532 | { | |
11533 | constraint (Rn == REG_PC, BAD_PC); | |
94206790 MM |
11534 | if (narrow) |
11535 | { | |
11536 | /* In the Thumb-2 ISA, use of R13 as Rm is deprecated, | |
11537 | but valid. */ | |
11538 | warn_deprecated_sp (Rm); | |
11539 | /* R15 was documented as a valid choice for Rm in ARMv6, | |
11540 | but as UNPREDICTABLE in ARMv7. ARM's proprietary | |
11541 | tools reject R15, so we do too. */ | |
11542 | constraint (Rm == REG_PC, BAD_PC); | |
11543 | } | |
11544 | else | |
11545 | reject_bad_reg (Rm); | |
fdfde340 JM |
11546 | } |
11547 | else if (opcode == T_MNEM_mov | |
11548 | || opcode == T_MNEM_movs) | |
11549 | { | |
11550 | if (inst.operands[1].isreg) | |
11551 | { | |
11552 | if (opcode == T_MNEM_movs) | |
11553 | { | |
11554 | reject_bad_reg (Rn); | |
11555 | reject_bad_reg (Rm); | |
11556 | } | |
76fa04a4 MGD |
11557 | else if (narrow) |
11558 | { | |
11559 | /* This is mov.n. */ | |
11560 | if ((Rn == REG_SP || Rn == REG_PC) | |
11561 | && (Rm == REG_SP || Rm == REG_PC)) | |
11562 | { | |
5c3696f8 | 11563 | as_tsktsk (_("Use of r%u as a source register is " |
76fa04a4 MGD |
11564 | "deprecated when r%u is the destination " |
11565 | "register."), Rm, Rn); | |
11566 | } | |
11567 | } | |
11568 | else | |
11569 | { | |
11570 | /* This is mov.w. */ | |
11571 | constraint (Rn == REG_PC, BAD_PC); | |
11572 | constraint (Rm == REG_PC, BAD_PC); | |
11573 | constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); | |
11574 | } | |
fdfde340 JM |
11575 | } |
11576 | else | |
11577 | reject_bad_reg (Rn); | |
11578 | } | |
11579 | ||
c19d1205 ZW |
11580 | if (!inst.operands[1].isreg) |
11581 | { | |
0110f2b8 | 11582 | /* Immediate operand. */ |
e07e6e58 | 11583 | if (!in_it_block () && opcode == T_MNEM_mov) |
0110f2b8 PB |
11584 | narrow = 0; |
11585 | if (low_regs && narrow) | |
11586 | { | |
11587 | inst.instruction = THUMB_OP16 (opcode); | |
fdfde340 | 11588 | inst.instruction |= Rn << 8; |
0110f2b8 PB |
11589 | if (inst.size_req == 2) |
11590 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
11591 | else | |
11592 | inst.relax = opcode; | |
11593 | } | |
11594 | else | |
11595 | { | |
11596 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11597 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 11598 | inst.instruction |= Rn << r0off; |
0110f2b8 PB |
11599 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
11600 | } | |
c19d1205 | 11601 | } |
728ca7c9 PB |
11602 | else if (inst.operands[1].shifted && inst.operands[1].immisreg |
11603 | && (inst.instruction == T_MNEM_mov | |
11604 | || inst.instruction == T_MNEM_movs)) | |
11605 | { | |
11606 | /* Register shifts are encoded as separate shift instructions. */ | |
11607 | bfd_boolean flags = (inst.instruction == T_MNEM_movs); | |
11608 | ||
e07e6e58 | 11609 | if (in_it_block ()) |
728ca7c9 PB |
11610 | narrow = !flags; |
11611 | else | |
11612 | narrow = flags; | |
11613 | ||
11614 | if (inst.size_req == 4) | |
11615 | narrow = FALSE; | |
11616 | ||
11617 | if (!low_regs || inst.operands[1].imm > 7) | |
11618 | narrow = FALSE; | |
11619 | ||
fdfde340 | 11620 | if (Rn != Rm) |
728ca7c9 PB |
11621 | narrow = FALSE; |
11622 | ||
11623 | switch (inst.operands[1].shift_kind) | |
11624 | { | |
11625 | case SHIFT_LSL: | |
11626 | opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); | |
11627 | break; | |
11628 | case SHIFT_ASR: | |
11629 | opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); | |
11630 | break; | |
11631 | case SHIFT_LSR: | |
11632 | opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); | |
11633 | break; | |
11634 | case SHIFT_ROR: | |
11635 | opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); | |
11636 | break; | |
11637 | default: | |
5f4273c7 | 11638 | abort (); |
728ca7c9 PB |
11639 | } |
11640 | ||
11641 | inst.instruction = opcode; | |
11642 | if (narrow) | |
11643 | { | |
fdfde340 | 11644 | inst.instruction |= Rn; |
728ca7c9 PB |
11645 | inst.instruction |= inst.operands[1].imm << 3; |
11646 | } | |
11647 | else | |
11648 | { | |
11649 | if (flags) | |
11650 | inst.instruction |= CONDS_BIT; | |
11651 | ||
fdfde340 JM |
11652 | inst.instruction |= Rn << 8; |
11653 | inst.instruction |= Rm << 16; | |
728ca7c9 PB |
11654 | inst.instruction |= inst.operands[1].imm; |
11655 | } | |
11656 | } | |
3d388997 | 11657 | else if (!narrow) |
c19d1205 | 11658 | { |
728ca7c9 PB |
11659 | /* Some mov with immediate shift have narrow variants. |
11660 | Register shifts are handled above. */ | |
11661 | if (low_regs && inst.operands[1].shifted | |
11662 | && (inst.instruction == T_MNEM_mov | |
11663 | || inst.instruction == T_MNEM_movs)) | |
11664 | { | |
e07e6e58 | 11665 | if (in_it_block ()) |
728ca7c9 PB |
11666 | narrow = (inst.instruction == T_MNEM_mov); |
11667 | else | |
11668 | narrow = (inst.instruction == T_MNEM_movs); | |
11669 | } | |
11670 | ||
11671 | if (narrow) | |
11672 | { | |
11673 | switch (inst.operands[1].shift_kind) | |
11674 | { | |
11675 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
11676 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
11677 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; | |
11678 | default: narrow = FALSE; break; | |
11679 | } | |
11680 | } | |
11681 | ||
11682 | if (narrow) | |
11683 | { | |
fdfde340 JM |
11684 | inst.instruction |= Rn; |
11685 | inst.instruction |= Rm << 3; | |
728ca7c9 PB |
11686 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
11687 | } | |
11688 | else | |
11689 | { | |
11690 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 11691 | inst.instruction |= Rn << r0off; |
728ca7c9 PB |
11692 | encode_thumb32_shifted_operand (1); |
11693 | } | |
c19d1205 ZW |
11694 | } |
11695 | else | |
11696 | switch (inst.instruction) | |
11697 | { | |
11698 | case T_MNEM_mov: | |
837b3435 | 11699 | /* In v4t or v5t a move of two lowregs produces unpredictable |
c6400f8a MGD |
11700 | results. Don't allow this. */ |
11701 | if (low_regs) | |
11702 | { | |
11703 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6), | |
11704 | "MOV Rd, Rs with two low registers is not " | |
11705 | "permitted on this architecture"); | |
fa94de6b | 11706 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
c6400f8a MGD |
11707 | arm_ext_v6); |
11708 | } | |
11709 | ||
c19d1205 | 11710 | inst.instruction = T_OPCODE_MOV_HR; |
fdfde340 JM |
11711 | inst.instruction |= (Rn & 0x8) << 4; |
11712 | inst.instruction |= (Rn & 0x7); | |
11713 | inst.instruction |= Rm << 3; | |
c19d1205 | 11714 | break; |
b99bd4ef | 11715 | |
c19d1205 ZW |
11716 | case T_MNEM_movs: |
11717 | /* We know we have low registers at this point. | |
941a8a52 MGD |
11718 | Generate LSLS Rd, Rs, #0. */ |
11719 | inst.instruction = T_OPCODE_LSL_I; | |
fdfde340 JM |
11720 | inst.instruction |= Rn; |
11721 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11722 | break; |
11723 | ||
11724 | case T_MNEM_cmp: | |
3d388997 | 11725 | if (low_regs) |
c19d1205 ZW |
11726 | { |
11727 | inst.instruction = T_OPCODE_CMP_LR; | |
fdfde340 JM |
11728 | inst.instruction |= Rn; |
11729 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11730 | } |
11731 | else | |
11732 | { | |
11733 | inst.instruction = T_OPCODE_CMP_HR; | |
fdfde340 JM |
11734 | inst.instruction |= (Rn & 0x8) << 4; |
11735 | inst.instruction |= (Rn & 0x7); | |
11736 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11737 | } |
11738 | break; | |
11739 | } | |
b99bd4ef NC |
11740 | return; |
11741 | } | |
11742 | ||
c19d1205 | 11743 | inst.instruction = THUMB_OP16 (inst.instruction); |
539d4391 NC |
11744 | |
11745 | /* PR 10443: Do not silently ignore shifted operands. */ | |
11746 | constraint (inst.operands[1].shifted, | |
11747 | _("shifts in CMP/MOV instructions are only supported in unified syntax")); | |
11748 | ||
c19d1205 | 11749 | if (inst.operands[1].isreg) |
b99bd4ef | 11750 | { |
fdfde340 | 11751 | if (Rn < 8 && Rm < 8) |
b99bd4ef | 11752 | { |
c19d1205 ZW |
11753 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
11754 | since a MOV instruction produces unpredictable results. */ | |
11755 | if (inst.instruction == T_OPCODE_MOV_I8) | |
11756 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 11757 | else |
c19d1205 | 11758 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 11759 | |
fdfde340 JM |
11760 | inst.instruction |= Rn; |
11761 | inst.instruction |= Rm << 3; | |
b99bd4ef NC |
11762 | } |
11763 | else | |
11764 | { | |
c19d1205 ZW |
11765 | if (inst.instruction == T_OPCODE_MOV_I8) |
11766 | inst.instruction = T_OPCODE_MOV_HR; | |
11767 | else | |
11768 | inst.instruction = T_OPCODE_CMP_HR; | |
11769 | do_t_cpy (); | |
b99bd4ef NC |
11770 | } |
11771 | } | |
c19d1205 | 11772 | else |
b99bd4ef | 11773 | { |
fdfde340 | 11774 | constraint (Rn > 7, |
c19d1205 | 11775 | _("only lo regs allowed with immediate")); |
fdfde340 | 11776 | inst.instruction |= Rn << 8; |
c19d1205 ZW |
11777 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; |
11778 | } | |
11779 | } | |
b99bd4ef | 11780 | |
c19d1205 ZW |
11781 | static void |
11782 | do_t_mov16 (void) | |
11783 | { | |
fdfde340 | 11784 | unsigned Rd; |
b6895b4f PB |
11785 | bfd_vma imm; |
11786 | bfd_boolean top; | |
11787 | ||
11788 | top = (inst.instruction & 0x00800000) != 0; | |
11789 | if (inst.reloc.type == BFD_RELOC_ARM_MOVW) | |
11790 | { | |
11791 | constraint (top, _(":lower16: not allowed this instruction")); | |
11792 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; | |
11793 | } | |
11794 | else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) | |
11795 | { | |
11796 | constraint (!top, _(":upper16: not allowed this instruction")); | |
11797 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; | |
11798 | } | |
11799 | ||
fdfde340 JM |
11800 | Rd = inst.operands[0].reg; |
11801 | reject_bad_reg (Rd); | |
11802 | ||
11803 | inst.instruction |= Rd << 8; | |
b6895b4f PB |
11804 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
11805 | { | |
11806 | imm = inst.reloc.exp.X_add_number; | |
11807 | inst.instruction |= (imm & 0xf000) << 4; | |
11808 | inst.instruction |= (imm & 0x0800) << 15; | |
11809 | inst.instruction |= (imm & 0x0700) << 4; | |
11810 | inst.instruction |= (imm & 0x00ff); | |
11811 | } | |
c19d1205 | 11812 | } |
b99bd4ef | 11813 | |
c19d1205 ZW |
11814 | static void |
11815 | do_t_mvn_tst (void) | |
11816 | { | |
fdfde340 | 11817 | unsigned Rn, Rm; |
c921be7d | 11818 | |
fdfde340 JM |
11819 | Rn = inst.operands[0].reg; |
11820 | Rm = inst.operands[1].reg; | |
11821 | ||
11822 | if (inst.instruction == T_MNEM_cmp | |
11823 | || inst.instruction == T_MNEM_cmn) | |
11824 | constraint (Rn == REG_PC, BAD_PC); | |
11825 | else | |
11826 | reject_bad_reg (Rn); | |
11827 | reject_bad_reg (Rm); | |
11828 | ||
c19d1205 ZW |
11829 | if (unified_syntax) |
11830 | { | |
11831 | int r0off = (inst.instruction == T_MNEM_mvn | |
11832 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
11833 | bfd_boolean narrow; |
11834 | ||
11835 | if (inst.size_req == 4 | |
11836 | || inst.instruction > 0xffff | |
11837 | || inst.operands[1].shifted | |
fdfde340 | 11838 | || Rn > 7 || Rm > 7) |
3d388997 | 11839 | narrow = FALSE; |
fe8b4cc3 KT |
11840 | else if (inst.instruction == T_MNEM_cmn |
11841 | || inst.instruction == T_MNEM_tst) | |
3d388997 PB |
11842 | narrow = TRUE; |
11843 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 11844 | narrow = !in_it_block (); |
3d388997 | 11845 | else |
e07e6e58 | 11846 | narrow = in_it_block (); |
3d388997 | 11847 | |
c19d1205 | 11848 | if (!inst.operands[1].isreg) |
b99bd4ef | 11849 | { |
c19d1205 ZW |
11850 | /* For an immediate, we always generate a 32-bit opcode; |
11851 | section relaxation will shrink it later if possible. */ | |
11852 | if (inst.instruction < 0xffff) | |
11853 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11854 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 11855 | inst.instruction |= Rn << r0off; |
c19d1205 | 11856 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
b99bd4ef | 11857 | } |
c19d1205 | 11858 | else |
b99bd4ef | 11859 | { |
c19d1205 | 11860 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 11861 | if (narrow) |
b99bd4ef | 11862 | { |
c19d1205 | 11863 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
11864 | inst.instruction |= Rn; |
11865 | inst.instruction |= Rm << 3; | |
b99bd4ef | 11866 | } |
c19d1205 | 11867 | else |
b99bd4ef | 11868 | { |
c19d1205 ZW |
11869 | constraint (inst.operands[1].shifted |
11870 | && inst.operands[1].immisreg, | |
11871 | _("shift must be constant")); | |
11872 | if (inst.instruction < 0xffff) | |
11873 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 11874 | inst.instruction |= Rn << r0off; |
c19d1205 | 11875 | encode_thumb32_shifted_operand (1); |
b99bd4ef | 11876 | } |
b99bd4ef NC |
11877 | } |
11878 | } | |
11879 | else | |
11880 | { | |
c19d1205 ZW |
11881 | constraint (inst.instruction > 0xffff |
11882 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
11883 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
11884 | _("unshifted register required")); | |
fdfde340 | 11885 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 11886 | BAD_HIREG); |
b99bd4ef | 11887 | |
c19d1205 | 11888 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
11889 | inst.instruction |= Rn; |
11890 | inst.instruction |= Rm << 3; | |
b99bd4ef | 11891 | } |
b99bd4ef NC |
11892 | } |
11893 | ||
b05fe5cf | 11894 | static void |
c19d1205 | 11895 | do_t_mrs (void) |
b05fe5cf | 11896 | { |
fdfde340 | 11897 | unsigned Rd; |
037e8744 JB |
11898 | |
11899 | if (do_vfp_nsyn_mrs () == SUCCESS) | |
11900 | return; | |
11901 | ||
90ec0d68 MGD |
11902 | Rd = inst.operands[0].reg; |
11903 | reject_bad_reg (Rd); | |
11904 | inst.instruction |= Rd << 8; | |
11905 | ||
11906 | if (inst.operands[1].isreg) | |
62b3e311 | 11907 | { |
90ec0d68 MGD |
11908 | unsigned br = inst.operands[1].reg; |
11909 | if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000)) | |
11910 | as_bad (_("bad register for mrs")); | |
11911 | ||
11912 | inst.instruction |= br & (0xf << 16); | |
11913 | inst.instruction |= (br & 0x300) >> 4; | |
11914 | inst.instruction |= (br & SPSR_BIT) >> 2; | |
62b3e311 PB |
11915 | } |
11916 | else | |
11917 | { | |
90ec0d68 | 11918 | int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
5f4273c7 | 11919 | |
d2cd1205 | 11920 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
1a43faaf NC |
11921 | { |
11922 | /* PR gas/12698: The constraint is only applied for m_profile. | |
11923 | If the user has specified -march=all, we want to ignore it as | |
11924 | we are building for any CPU type, including non-m variants. */ | |
11925 | bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core; | |
11926 | constraint ((flags != 0) && m_profile, _("selected processor does " | |
11927 | "not support requested special purpose register")); | |
11928 | } | |
90ec0d68 | 11929 | else |
d2cd1205 JB |
11930 | /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile |
11931 | devices). */ | |
11932 | constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), | |
11933 | _("'APSR', 'CPSR' or 'SPSR' expected")); | |
fdfde340 | 11934 | |
90ec0d68 MGD |
11935 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
11936 | inst.instruction |= inst.operands[1].imm & 0xff; | |
11937 | inst.instruction |= 0xf0000; | |
11938 | } | |
c19d1205 | 11939 | } |
b05fe5cf | 11940 | |
c19d1205 ZW |
11941 | static void |
11942 | do_t_msr (void) | |
11943 | { | |
62b3e311 | 11944 | int flags; |
fdfde340 | 11945 | unsigned Rn; |
62b3e311 | 11946 | |
037e8744 JB |
11947 | if (do_vfp_nsyn_msr () == SUCCESS) |
11948 | return; | |
11949 | ||
c19d1205 ZW |
11950 | constraint (!inst.operands[1].isreg, |
11951 | _("Thumb encoding does not support an immediate here")); | |
90ec0d68 MGD |
11952 | |
11953 | if (inst.operands[0].isreg) | |
11954 | flags = (int)(inst.operands[0].reg); | |
11955 | else | |
11956 | flags = inst.operands[0].imm; | |
11957 | ||
d2cd1205 | 11958 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
62b3e311 | 11959 | { |
d2cd1205 JB |
11960 | int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
11961 | ||
1a43faaf | 11962 | /* PR gas/12698: The constraint is only applied for m_profile. |
477330fc RM |
11963 | If the user has specified -march=all, we want to ignore it as |
11964 | we are building for any CPU type, including non-m variants. */ | |
1a43faaf NC |
11965 | bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core; |
11966 | constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) | |
477330fc RM |
11967 | && (bits & ~(PSR_s | PSR_f)) != 0) |
11968 | || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) | |
11969 | && bits != PSR_f)) && m_profile, | |
11970 | _("selected processor does not support requested special " | |
11971 | "purpose register")); | |
62b3e311 PB |
11972 | } |
11973 | else | |
d2cd1205 JB |
11974 | constraint ((flags & 0xff) != 0, _("selected processor does not support " |
11975 | "requested special purpose register")); | |
c921be7d | 11976 | |
fdfde340 JM |
11977 | Rn = inst.operands[1].reg; |
11978 | reject_bad_reg (Rn); | |
11979 | ||
62b3e311 | 11980 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
90ec0d68 MGD |
11981 | inst.instruction |= (flags & 0xf0000) >> 8; |
11982 | inst.instruction |= (flags & 0x300) >> 4; | |
62b3e311 | 11983 | inst.instruction |= (flags & 0xff); |
fdfde340 | 11984 | inst.instruction |= Rn << 16; |
c19d1205 | 11985 | } |
b05fe5cf | 11986 | |
c19d1205 ZW |
11987 | static void |
11988 | do_t_mul (void) | |
11989 | { | |
17828f45 | 11990 | bfd_boolean narrow; |
fdfde340 | 11991 | unsigned Rd, Rn, Rm; |
17828f45 | 11992 | |
c19d1205 ZW |
11993 | if (!inst.operands[2].present) |
11994 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 11995 | |
fdfde340 JM |
11996 | Rd = inst.operands[0].reg; |
11997 | Rn = inst.operands[1].reg; | |
11998 | Rm = inst.operands[2].reg; | |
11999 | ||
17828f45 | 12000 | if (unified_syntax) |
b05fe5cf | 12001 | { |
17828f45 | 12002 | if (inst.size_req == 4 |
fdfde340 JM |
12003 | || (Rd != Rn |
12004 | && Rd != Rm) | |
12005 | || Rn > 7 | |
12006 | || Rm > 7) | |
17828f45 JM |
12007 | narrow = FALSE; |
12008 | else if (inst.instruction == T_MNEM_muls) | |
e07e6e58 | 12009 | narrow = !in_it_block (); |
17828f45 | 12010 | else |
e07e6e58 | 12011 | narrow = in_it_block (); |
b05fe5cf | 12012 | } |
c19d1205 | 12013 | else |
b05fe5cf | 12014 | { |
17828f45 | 12015 | constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); |
fdfde340 | 12016 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 12017 | BAD_HIREG); |
17828f45 JM |
12018 | narrow = TRUE; |
12019 | } | |
b05fe5cf | 12020 | |
17828f45 JM |
12021 | if (narrow) |
12022 | { | |
12023 | /* 16-bit MULS/Conditional MUL. */ | |
c19d1205 | 12024 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 | 12025 | inst.instruction |= Rd; |
b05fe5cf | 12026 | |
fdfde340 JM |
12027 | if (Rd == Rn) |
12028 | inst.instruction |= Rm << 3; | |
12029 | else if (Rd == Rm) | |
12030 | inst.instruction |= Rn << 3; | |
c19d1205 ZW |
12031 | else |
12032 | constraint (1, _("dest must overlap one source register")); | |
12033 | } | |
17828f45 JM |
12034 | else |
12035 | { | |
e07e6e58 NC |
12036 | constraint (inst.instruction != T_MNEM_mul, |
12037 | _("Thumb-2 MUL must not set flags")); | |
17828f45 JM |
12038 | /* 32-bit MUL. */ |
12039 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
12040 | inst.instruction |= Rd << 8; |
12041 | inst.instruction |= Rn << 16; | |
12042 | inst.instruction |= Rm << 0; | |
12043 | ||
12044 | reject_bad_reg (Rd); | |
12045 | reject_bad_reg (Rn); | |
12046 | reject_bad_reg (Rm); | |
17828f45 | 12047 | } |
c19d1205 | 12048 | } |
b05fe5cf | 12049 | |
c19d1205 ZW |
12050 | static void |
12051 | do_t_mull (void) | |
12052 | { | |
fdfde340 | 12053 | unsigned RdLo, RdHi, Rn, Rm; |
b05fe5cf | 12054 | |
fdfde340 JM |
12055 | RdLo = inst.operands[0].reg; |
12056 | RdHi = inst.operands[1].reg; | |
12057 | Rn = inst.operands[2].reg; | |
12058 | Rm = inst.operands[3].reg; | |
12059 | ||
12060 | reject_bad_reg (RdLo); | |
12061 | reject_bad_reg (RdHi); | |
12062 | reject_bad_reg (Rn); | |
12063 | reject_bad_reg (Rm); | |
12064 | ||
12065 | inst.instruction |= RdLo << 12; | |
12066 | inst.instruction |= RdHi << 8; | |
12067 | inst.instruction |= Rn << 16; | |
12068 | inst.instruction |= Rm; | |
12069 | ||
12070 | if (RdLo == RdHi) | |
c19d1205 ZW |
12071 | as_tsktsk (_("rdhi and rdlo must be different")); |
12072 | } | |
b05fe5cf | 12073 | |
c19d1205 ZW |
12074 | static void |
12075 | do_t_nop (void) | |
12076 | { | |
e07e6e58 NC |
12077 | set_it_insn_type (NEUTRAL_IT_INSN); |
12078 | ||
c19d1205 ZW |
12079 | if (unified_syntax) |
12080 | { | |
12081 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 12082 | { |
c19d1205 ZW |
12083 | inst.instruction = THUMB_OP32 (inst.instruction); |
12084 | inst.instruction |= inst.operands[0].imm; | |
12085 | } | |
12086 | else | |
12087 | { | |
bc2d1808 NC |
12088 | /* PR9722: Check for Thumb2 availability before |
12089 | generating a thumb2 nop instruction. */ | |
afa62d5e | 12090 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
bc2d1808 NC |
12091 | { |
12092 | inst.instruction = THUMB_OP16 (inst.instruction); | |
12093 | inst.instruction |= inst.operands[0].imm << 4; | |
12094 | } | |
12095 | else | |
12096 | inst.instruction = 0x46c0; | |
c19d1205 ZW |
12097 | } |
12098 | } | |
12099 | else | |
12100 | { | |
12101 | constraint (inst.operands[0].present, | |
12102 | _("Thumb does not support NOP with hints")); | |
12103 | inst.instruction = 0x46c0; | |
12104 | } | |
12105 | } | |
b05fe5cf | 12106 | |
c19d1205 ZW |
12107 | static void |
12108 | do_t_neg (void) | |
12109 | { | |
12110 | if (unified_syntax) | |
12111 | { | |
3d388997 PB |
12112 | bfd_boolean narrow; |
12113 | ||
12114 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 12115 | narrow = !in_it_block (); |
3d388997 | 12116 | else |
e07e6e58 | 12117 | narrow = in_it_block (); |
3d388997 PB |
12118 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
12119 | narrow = FALSE; | |
12120 | if (inst.size_req == 4) | |
12121 | narrow = FALSE; | |
12122 | ||
12123 | if (!narrow) | |
c19d1205 ZW |
12124 | { |
12125 | inst.instruction = THUMB_OP32 (inst.instruction); | |
12126 | inst.instruction |= inst.operands[0].reg << 8; | |
12127 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
12128 | } |
12129 | else | |
12130 | { | |
c19d1205 ZW |
12131 | inst.instruction = THUMB_OP16 (inst.instruction); |
12132 | inst.instruction |= inst.operands[0].reg; | |
12133 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
12134 | } |
12135 | } | |
12136 | else | |
12137 | { | |
c19d1205 ZW |
12138 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
12139 | BAD_HIREG); | |
12140 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
12141 | ||
12142 | inst.instruction = THUMB_OP16 (inst.instruction); | |
12143 | inst.instruction |= inst.operands[0].reg; | |
12144 | inst.instruction |= inst.operands[1].reg << 3; | |
12145 | } | |
12146 | } | |
12147 | ||
1c444d06 JM |
12148 | static void |
12149 | do_t_orn (void) | |
12150 | { | |
12151 | unsigned Rd, Rn; | |
12152 | ||
12153 | Rd = inst.operands[0].reg; | |
12154 | Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; | |
12155 | ||
fdfde340 JM |
12156 | reject_bad_reg (Rd); |
12157 | /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ | |
12158 | reject_bad_reg (Rn); | |
12159 | ||
1c444d06 JM |
12160 | inst.instruction |= Rd << 8; |
12161 | inst.instruction |= Rn << 16; | |
12162 | ||
12163 | if (!inst.operands[2].isreg) | |
12164 | { | |
12165 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
12166 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
12167 | } | |
12168 | else | |
12169 | { | |
12170 | unsigned Rm; | |
12171 | ||
12172 | Rm = inst.operands[2].reg; | |
fdfde340 | 12173 | reject_bad_reg (Rm); |
1c444d06 JM |
12174 | |
12175 | constraint (inst.operands[2].shifted | |
12176 | && inst.operands[2].immisreg, | |
12177 | _("shift must be constant")); | |
12178 | encode_thumb32_shifted_operand (2); | |
12179 | } | |
12180 | } | |
12181 | ||
c19d1205 ZW |
12182 | static void |
12183 | do_t_pkhbt (void) | |
12184 | { | |
fdfde340 JM |
12185 | unsigned Rd, Rn, Rm; |
12186 | ||
12187 | Rd = inst.operands[0].reg; | |
12188 | Rn = inst.operands[1].reg; | |
12189 | Rm = inst.operands[2].reg; | |
12190 | ||
12191 | reject_bad_reg (Rd); | |
12192 | reject_bad_reg (Rn); | |
12193 | reject_bad_reg (Rm); | |
12194 | ||
12195 | inst.instruction |= Rd << 8; | |
12196 | inst.instruction |= Rn << 16; | |
12197 | inst.instruction |= Rm; | |
c19d1205 ZW |
12198 | if (inst.operands[3].present) |
12199 | { | |
12200 | unsigned int val = inst.reloc.exp.X_add_number; | |
12201 | constraint (inst.reloc.exp.X_op != O_constant, | |
12202 | _("expression too complex")); | |
12203 | inst.instruction |= (val & 0x1c) << 10; | |
12204 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 12205 | } |
c19d1205 | 12206 | } |
b05fe5cf | 12207 | |
c19d1205 ZW |
12208 | static void |
12209 | do_t_pkhtb (void) | |
12210 | { | |
12211 | if (!inst.operands[3].present) | |
1ef52f49 NC |
12212 | { |
12213 | unsigned Rtmp; | |
12214 | ||
12215 | inst.instruction &= ~0x00000020; | |
12216 | ||
12217 | /* PR 10168. Swap the Rm and Rn registers. */ | |
12218 | Rtmp = inst.operands[1].reg; | |
12219 | inst.operands[1].reg = inst.operands[2].reg; | |
12220 | inst.operands[2].reg = Rtmp; | |
12221 | } | |
c19d1205 | 12222 | do_t_pkhbt (); |
b05fe5cf ZW |
12223 | } |
12224 | ||
c19d1205 ZW |
12225 | static void |
12226 | do_t_pld (void) | |
12227 | { | |
fdfde340 JM |
12228 | if (inst.operands[0].immisreg) |
12229 | reject_bad_reg (inst.operands[0].imm); | |
12230 | ||
c19d1205 ZW |
12231 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); |
12232 | } | |
b05fe5cf | 12233 | |
c19d1205 ZW |
12234 | static void |
12235 | do_t_push_pop (void) | |
b99bd4ef | 12236 | { |
e9f89963 | 12237 | unsigned mask; |
5f4273c7 | 12238 | |
c19d1205 ZW |
12239 | constraint (inst.operands[0].writeback, |
12240 | _("push/pop do not support {reglist}^")); | |
12241 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
12242 | _("expression too complex")); | |
b99bd4ef | 12243 | |
e9f89963 | 12244 | mask = inst.operands[0].imm; |
d3bfe16e | 12245 | if (inst.size_req != 4 && (mask & ~0xff) == 0) |
3c707909 | 12246 | inst.instruction = THUMB_OP16 (inst.instruction) | mask; |
d3bfe16e JB |
12247 | else if (inst.size_req != 4 |
12248 | && (mask & ~0xff) == (1 << (inst.instruction == T_MNEM_push | |
12249 | ? REG_LR : REG_PC))) | |
b99bd4ef | 12250 | { |
c19d1205 ZW |
12251 | inst.instruction = THUMB_OP16 (inst.instruction); |
12252 | inst.instruction |= THUMB_PP_PC_LR; | |
3c707909 | 12253 | inst.instruction |= mask & 0xff; |
c19d1205 ZW |
12254 | } |
12255 | else if (unified_syntax) | |
12256 | { | |
3c707909 | 12257 | inst.instruction = THUMB_OP32 (inst.instruction); |
5f4273c7 | 12258 | encode_thumb2_ldmstm (13, mask, TRUE); |
c19d1205 ZW |
12259 | } |
12260 | else | |
12261 | { | |
12262 | inst.error = _("invalid register list to push/pop instruction"); | |
12263 | return; | |
12264 | } | |
c19d1205 | 12265 | } |
b99bd4ef | 12266 | |
c19d1205 ZW |
12267 | static void |
12268 | do_t_rbit (void) | |
12269 | { | |
fdfde340 JM |
12270 | unsigned Rd, Rm; |
12271 | ||
12272 | Rd = inst.operands[0].reg; | |
12273 | Rm = inst.operands[1].reg; | |
12274 | ||
12275 | reject_bad_reg (Rd); | |
12276 | reject_bad_reg (Rm); | |
12277 | ||
12278 | inst.instruction |= Rd << 8; | |
12279 | inst.instruction |= Rm << 16; | |
12280 | inst.instruction |= Rm; | |
c19d1205 | 12281 | } |
b99bd4ef | 12282 | |
c19d1205 ZW |
12283 | static void |
12284 | do_t_rev (void) | |
12285 | { | |
fdfde340 JM |
12286 | unsigned Rd, Rm; |
12287 | ||
12288 | Rd = inst.operands[0].reg; | |
12289 | Rm = inst.operands[1].reg; | |
12290 | ||
12291 | reject_bad_reg (Rd); | |
12292 | reject_bad_reg (Rm); | |
12293 | ||
12294 | if (Rd <= 7 && Rm <= 7 | |
c19d1205 ZW |
12295 | && inst.size_req != 4) |
12296 | { | |
12297 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 JM |
12298 | inst.instruction |= Rd; |
12299 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
12300 | } |
12301 | else if (unified_syntax) | |
12302 | { | |
12303 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
12304 | inst.instruction |= Rd << 8; |
12305 | inst.instruction |= Rm << 16; | |
12306 | inst.instruction |= Rm; | |
c19d1205 ZW |
12307 | } |
12308 | else | |
12309 | inst.error = BAD_HIREG; | |
12310 | } | |
b99bd4ef | 12311 | |
1c444d06 JM |
12312 | static void |
12313 | do_t_rrx (void) | |
12314 | { | |
12315 | unsigned Rd, Rm; | |
12316 | ||
12317 | Rd = inst.operands[0].reg; | |
12318 | Rm = inst.operands[1].reg; | |
12319 | ||
fdfde340 JM |
12320 | reject_bad_reg (Rd); |
12321 | reject_bad_reg (Rm); | |
c921be7d | 12322 | |
1c444d06 JM |
12323 | inst.instruction |= Rd << 8; |
12324 | inst.instruction |= Rm; | |
12325 | } | |
12326 | ||
c19d1205 ZW |
12327 | static void |
12328 | do_t_rsb (void) | |
12329 | { | |
fdfde340 | 12330 | unsigned Rd, Rs; |
b99bd4ef | 12331 | |
c19d1205 ZW |
12332 | Rd = inst.operands[0].reg; |
12333 | Rs = (inst.operands[1].present | |
12334 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
12335 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 12336 | |
fdfde340 JM |
12337 | reject_bad_reg (Rd); |
12338 | reject_bad_reg (Rs); | |
12339 | if (inst.operands[2].isreg) | |
12340 | reject_bad_reg (inst.operands[2].reg); | |
12341 | ||
c19d1205 ZW |
12342 | inst.instruction |= Rd << 8; |
12343 | inst.instruction |= Rs << 16; | |
12344 | if (!inst.operands[2].isreg) | |
12345 | { | |
026d3abb PB |
12346 | bfd_boolean narrow; |
12347 | ||
12348 | if ((inst.instruction & 0x00100000) != 0) | |
e07e6e58 | 12349 | narrow = !in_it_block (); |
026d3abb | 12350 | else |
e07e6e58 | 12351 | narrow = in_it_block (); |
026d3abb PB |
12352 | |
12353 | if (Rd > 7 || Rs > 7) | |
12354 | narrow = FALSE; | |
12355 | ||
12356 | if (inst.size_req == 4 || !unified_syntax) | |
12357 | narrow = FALSE; | |
12358 | ||
12359 | if (inst.reloc.exp.X_op != O_constant | |
12360 | || inst.reloc.exp.X_add_number != 0) | |
12361 | narrow = FALSE; | |
12362 | ||
12363 | /* Turn rsb #0 into 16-bit neg. We should probably do this via | |
477330fc | 12364 | relaxation, but it doesn't seem worth the hassle. */ |
026d3abb PB |
12365 | if (narrow) |
12366 | { | |
12367 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12368 | inst.instruction = THUMB_OP16 (T_MNEM_negs); | |
12369 | inst.instruction |= Rs << 3; | |
12370 | inst.instruction |= Rd; | |
12371 | } | |
12372 | else | |
12373 | { | |
12374 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
12375 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
12376 | } | |
c19d1205 ZW |
12377 | } |
12378 | else | |
12379 | encode_thumb32_shifted_operand (2); | |
12380 | } | |
b99bd4ef | 12381 | |
c19d1205 ZW |
12382 | static void |
12383 | do_t_setend (void) | |
12384 | { | |
12e37cbc MGD |
12385 | if (warn_on_deprecated |
12386 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
5c3696f8 | 12387 | as_tsktsk (_("setend use is deprecated for ARMv8")); |
12e37cbc | 12388 | |
e07e6e58 | 12389 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
12390 | if (inst.operands[0].imm) |
12391 | inst.instruction |= 0x8; | |
12392 | } | |
b99bd4ef | 12393 | |
c19d1205 ZW |
12394 | static void |
12395 | do_t_shift (void) | |
12396 | { | |
12397 | if (!inst.operands[1].present) | |
12398 | inst.operands[1].reg = inst.operands[0].reg; | |
12399 | ||
12400 | if (unified_syntax) | |
12401 | { | |
3d388997 PB |
12402 | bfd_boolean narrow; |
12403 | int shift_kind; | |
12404 | ||
12405 | switch (inst.instruction) | |
12406 | { | |
12407 | case T_MNEM_asr: | |
12408 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
12409 | case T_MNEM_lsl: | |
12410 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
12411 | case T_MNEM_lsr: | |
12412 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
12413 | case T_MNEM_ror: | |
12414 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
12415 | default: abort (); | |
12416 | } | |
12417 | ||
12418 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 12419 | narrow = !in_it_block (); |
3d388997 | 12420 | else |
e07e6e58 | 12421 | narrow = in_it_block (); |
3d388997 PB |
12422 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
12423 | narrow = FALSE; | |
12424 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
12425 | narrow = FALSE; | |
12426 | if (inst.operands[2].isreg | |
12427 | && (inst.operands[1].reg != inst.operands[0].reg | |
12428 | || inst.operands[2].reg > 7)) | |
12429 | narrow = FALSE; | |
12430 | if (inst.size_req == 4) | |
12431 | narrow = FALSE; | |
12432 | ||
fdfde340 JM |
12433 | reject_bad_reg (inst.operands[0].reg); |
12434 | reject_bad_reg (inst.operands[1].reg); | |
c921be7d | 12435 | |
3d388997 | 12436 | if (!narrow) |
c19d1205 ZW |
12437 | { |
12438 | if (inst.operands[2].isreg) | |
b99bd4ef | 12439 | { |
fdfde340 | 12440 | reject_bad_reg (inst.operands[2].reg); |
c19d1205 ZW |
12441 | inst.instruction = THUMB_OP32 (inst.instruction); |
12442 | inst.instruction |= inst.operands[0].reg << 8; | |
12443 | inst.instruction |= inst.operands[1].reg << 16; | |
12444 | inst.instruction |= inst.operands[2].reg; | |
94342ec3 NC |
12445 | |
12446 | /* PR 12854: Error on extraneous shifts. */ | |
12447 | constraint (inst.operands[2].shifted, | |
12448 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
12449 | } |
12450 | else | |
12451 | { | |
12452 | inst.operands[1].shifted = 1; | |
3d388997 | 12453 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
12454 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
12455 | ? T_MNEM_movs : T_MNEM_mov); | |
12456 | inst.instruction |= inst.operands[0].reg << 8; | |
12457 | encode_thumb32_shifted_operand (1); | |
12458 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
12459 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef NC |
12460 | } |
12461 | } | |
12462 | else | |
12463 | { | |
c19d1205 | 12464 | if (inst.operands[2].isreg) |
b99bd4ef | 12465 | { |
3d388997 | 12466 | switch (shift_kind) |
b99bd4ef | 12467 | { |
3d388997 PB |
12468 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
12469 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
12470 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
12471 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 12472 | default: abort (); |
b99bd4ef | 12473 | } |
5f4273c7 | 12474 | |
c19d1205 ZW |
12475 | inst.instruction |= inst.operands[0].reg; |
12476 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
12477 | |
12478 | /* PR 12854: Error on extraneous shifts. */ | |
12479 | constraint (inst.operands[2].shifted, | |
12480 | _("extraneous shift as part of operand to shift insn")); | |
b99bd4ef NC |
12481 | } |
12482 | else | |
12483 | { | |
3d388997 | 12484 | switch (shift_kind) |
b99bd4ef | 12485 | { |
3d388997 PB |
12486 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
12487 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
12488 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 12489 | default: abort (); |
b99bd4ef | 12490 | } |
c19d1205 ZW |
12491 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
12492 | inst.instruction |= inst.operands[0].reg; | |
12493 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
12494 | } |
12495 | } | |
c19d1205 ZW |
12496 | } |
12497 | else | |
12498 | { | |
12499 | constraint (inst.operands[0].reg > 7 | |
12500 | || inst.operands[1].reg > 7, BAD_HIREG); | |
12501 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 12502 | |
c19d1205 ZW |
12503 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
12504 | { | |
12505 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
12506 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
12507 | _("source1 and dest must be same register")); | |
b99bd4ef | 12508 | |
c19d1205 ZW |
12509 | switch (inst.instruction) |
12510 | { | |
12511 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
12512 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
12513 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
12514 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
12515 | default: abort (); | |
12516 | } | |
5f4273c7 | 12517 | |
c19d1205 ZW |
12518 | inst.instruction |= inst.operands[0].reg; |
12519 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
12520 | |
12521 | /* PR 12854: Error on extraneous shifts. */ | |
12522 | constraint (inst.operands[2].shifted, | |
12523 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
12524 | } |
12525 | else | |
b99bd4ef | 12526 | { |
c19d1205 ZW |
12527 | switch (inst.instruction) |
12528 | { | |
12529 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
12530 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
12531 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
12532 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
12533 | default: abort (); | |
12534 | } | |
12535 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
12536 | inst.instruction |= inst.operands[0].reg; | |
12537 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
12538 | } |
12539 | } | |
b99bd4ef NC |
12540 | } |
12541 | ||
12542 | static void | |
c19d1205 | 12543 | do_t_simd (void) |
b99bd4ef | 12544 | { |
fdfde340 JM |
12545 | unsigned Rd, Rn, Rm; |
12546 | ||
12547 | Rd = inst.operands[0].reg; | |
12548 | Rn = inst.operands[1].reg; | |
12549 | Rm = inst.operands[2].reg; | |
12550 | ||
12551 | reject_bad_reg (Rd); | |
12552 | reject_bad_reg (Rn); | |
12553 | reject_bad_reg (Rm); | |
12554 | ||
12555 | inst.instruction |= Rd << 8; | |
12556 | inst.instruction |= Rn << 16; | |
12557 | inst.instruction |= Rm; | |
c19d1205 | 12558 | } |
b99bd4ef | 12559 | |
03ee1b7f NC |
12560 | static void |
12561 | do_t_simd2 (void) | |
12562 | { | |
12563 | unsigned Rd, Rn, Rm; | |
12564 | ||
12565 | Rd = inst.operands[0].reg; | |
12566 | Rm = inst.operands[1].reg; | |
12567 | Rn = inst.operands[2].reg; | |
12568 | ||
12569 | reject_bad_reg (Rd); | |
12570 | reject_bad_reg (Rn); | |
12571 | reject_bad_reg (Rm); | |
12572 | ||
12573 | inst.instruction |= Rd << 8; | |
12574 | inst.instruction |= Rn << 16; | |
12575 | inst.instruction |= Rm; | |
12576 | } | |
12577 | ||
c19d1205 | 12578 | static void |
3eb17e6b | 12579 | do_t_smc (void) |
c19d1205 ZW |
12580 | { |
12581 | unsigned int value = inst.reloc.exp.X_add_number; | |
f4c65163 MGD |
12582 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a), |
12583 | _("SMC is not permitted on this architecture")); | |
c19d1205 ZW |
12584 | constraint (inst.reloc.exp.X_op != O_constant, |
12585 | _("expression too complex")); | |
12586 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12587 | inst.instruction |= (value & 0xf000) >> 12; | |
12588 | inst.instruction |= (value & 0x0ff0); | |
12589 | inst.instruction |= (value & 0x000f) << 16; | |
24382199 NC |
12590 | /* PR gas/15623: SMC instructions must be last in an IT block. */ |
12591 | set_it_insn_type_last (); | |
c19d1205 | 12592 | } |
b99bd4ef | 12593 | |
90ec0d68 MGD |
12594 | static void |
12595 | do_t_hvc (void) | |
12596 | { | |
12597 | unsigned int value = inst.reloc.exp.X_add_number; | |
12598 | ||
12599 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12600 | inst.instruction |= (value & 0x0fff); | |
12601 | inst.instruction |= (value & 0xf000) << 4; | |
12602 | } | |
12603 | ||
c19d1205 | 12604 | static void |
3a21c15a | 12605 | do_t_ssat_usat (int bias) |
c19d1205 | 12606 | { |
fdfde340 JM |
12607 | unsigned Rd, Rn; |
12608 | ||
12609 | Rd = inst.operands[0].reg; | |
12610 | Rn = inst.operands[2].reg; | |
12611 | ||
12612 | reject_bad_reg (Rd); | |
12613 | reject_bad_reg (Rn); | |
12614 | ||
12615 | inst.instruction |= Rd << 8; | |
3a21c15a | 12616 | inst.instruction |= inst.operands[1].imm - bias; |
fdfde340 | 12617 | inst.instruction |= Rn << 16; |
b99bd4ef | 12618 | |
c19d1205 | 12619 | if (inst.operands[3].present) |
b99bd4ef | 12620 | { |
3a21c15a NC |
12621 | offsetT shift_amount = inst.reloc.exp.X_add_number; |
12622 | ||
12623 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12624 | ||
c19d1205 ZW |
12625 | constraint (inst.reloc.exp.X_op != O_constant, |
12626 | _("expression too complex")); | |
b99bd4ef | 12627 | |
3a21c15a | 12628 | if (shift_amount != 0) |
6189168b | 12629 | { |
3a21c15a NC |
12630 | constraint (shift_amount > 31, |
12631 | _("shift expression is too large")); | |
12632 | ||
c19d1205 | 12633 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
3a21c15a NC |
12634 | inst.instruction |= 0x00200000; /* sh bit. */ |
12635 | ||
12636 | inst.instruction |= (shift_amount & 0x1c) << 10; | |
12637 | inst.instruction |= (shift_amount & 0x03) << 6; | |
6189168b NC |
12638 | } |
12639 | } | |
b99bd4ef | 12640 | } |
c921be7d | 12641 | |
3a21c15a NC |
12642 | static void |
12643 | do_t_ssat (void) | |
12644 | { | |
12645 | do_t_ssat_usat (1); | |
12646 | } | |
b99bd4ef | 12647 | |
0dd132b6 | 12648 | static void |
c19d1205 | 12649 | do_t_ssat16 (void) |
0dd132b6 | 12650 | { |
fdfde340 JM |
12651 | unsigned Rd, Rn; |
12652 | ||
12653 | Rd = inst.operands[0].reg; | |
12654 | Rn = inst.operands[2].reg; | |
12655 | ||
12656 | reject_bad_reg (Rd); | |
12657 | reject_bad_reg (Rn); | |
12658 | ||
12659 | inst.instruction |= Rd << 8; | |
c19d1205 | 12660 | inst.instruction |= inst.operands[1].imm - 1; |
fdfde340 | 12661 | inst.instruction |= Rn << 16; |
c19d1205 | 12662 | } |
0dd132b6 | 12663 | |
c19d1205 ZW |
12664 | static void |
12665 | do_t_strex (void) | |
12666 | { | |
12667 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
12668 | || inst.operands[2].postind || inst.operands[2].writeback | |
12669 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
12670 | || inst.operands[2].negative, | |
01cfc07f | 12671 | BAD_ADDR_MODE); |
0dd132b6 | 12672 | |
5be8be5d DG |
12673 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
12674 | ||
c19d1205 ZW |
12675 | inst.instruction |= inst.operands[0].reg << 8; |
12676 | inst.instruction |= inst.operands[1].reg << 12; | |
12677 | inst.instruction |= inst.operands[2].reg << 16; | |
12678 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
0dd132b6 NC |
12679 | } |
12680 | ||
b99bd4ef | 12681 | static void |
c19d1205 | 12682 | do_t_strexd (void) |
b99bd4ef | 12683 | { |
c19d1205 ZW |
12684 | if (!inst.operands[2].present) |
12685 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 12686 | |
c19d1205 ZW |
12687 | constraint (inst.operands[0].reg == inst.operands[1].reg |
12688 | || inst.operands[0].reg == inst.operands[2].reg | |
f8a8e9d6 | 12689 | || inst.operands[0].reg == inst.operands[3].reg, |
c19d1205 | 12690 | BAD_OVERLAP); |
b99bd4ef | 12691 | |
c19d1205 ZW |
12692 | inst.instruction |= inst.operands[0].reg; |
12693 | inst.instruction |= inst.operands[1].reg << 12; | |
12694 | inst.instruction |= inst.operands[2].reg << 8; | |
12695 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
12696 | } |
12697 | ||
12698 | static void | |
c19d1205 | 12699 | do_t_sxtah (void) |
b99bd4ef | 12700 | { |
fdfde340 JM |
12701 | unsigned Rd, Rn, Rm; |
12702 | ||
12703 | Rd = inst.operands[0].reg; | |
12704 | Rn = inst.operands[1].reg; | |
12705 | Rm = inst.operands[2].reg; | |
12706 | ||
12707 | reject_bad_reg (Rd); | |
12708 | reject_bad_reg (Rn); | |
12709 | reject_bad_reg (Rm); | |
12710 | ||
12711 | inst.instruction |= Rd << 8; | |
12712 | inst.instruction |= Rn << 16; | |
12713 | inst.instruction |= Rm; | |
c19d1205 ZW |
12714 | inst.instruction |= inst.operands[3].imm << 4; |
12715 | } | |
b99bd4ef | 12716 | |
c19d1205 ZW |
12717 | static void |
12718 | do_t_sxth (void) | |
12719 | { | |
fdfde340 JM |
12720 | unsigned Rd, Rm; |
12721 | ||
12722 | Rd = inst.operands[0].reg; | |
12723 | Rm = inst.operands[1].reg; | |
12724 | ||
12725 | reject_bad_reg (Rd); | |
12726 | reject_bad_reg (Rm); | |
c921be7d NC |
12727 | |
12728 | if (inst.instruction <= 0xffff | |
12729 | && inst.size_req != 4 | |
fdfde340 | 12730 | && Rd <= 7 && Rm <= 7 |
c19d1205 | 12731 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) |
b99bd4ef | 12732 | { |
c19d1205 | 12733 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
12734 | inst.instruction |= Rd; |
12735 | inst.instruction |= Rm << 3; | |
b99bd4ef | 12736 | } |
c19d1205 | 12737 | else if (unified_syntax) |
b99bd4ef | 12738 | { |
c19d1205 ZW |
12739 | if (inst.instruction <= 0xffff) |
12740 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
12741 | inst.instruction |= Rd << 8; |
12742 | inst.instruction |= Rm; | |
c19d1205 | 12743 | inst.instruction |= inst.operands[2].imm << 4; |
b99bd4ef | 12744 | } |
c19d1205 | 12745 | else |
b99bd4ef | 12746 | { |
c19d1205 ZW |
12747 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
12748 | _("Thumb encoding does not support rotation")); | |
12749 | constraint (1, BAD_HIREG); | |
b99bd4ef | 12750 | } |
c19d1205 | 12751 | } |
b99bd4ef | 12752 | |
c19d1205 ZW |
12753 | static void |
12754 | do_t_swi (void) | |
12755 | { | |
b2a5fbdc MGD |
12756 | /* We have to do the following check manually as ARM_EXT_OS only applies |
12757 | to ARM_EXT_V6M. */ | |
12758 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m)) | |
12759 | { | |
ac7f631b NC |
12760 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os) |
12761 | /* This only applies to the v6m howver, not later architectures. */ | |
12762 | && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)) | |
b2a5fbdc MGD |
12763 | as_bad (_("SVC is not permitted on this architecture")); |
12764 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os); | |
12765 | } | |
12766 | ||
c19d1205 ZW |
12767 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
12768 | } | |
b99bd4ef | 12769 | |
92e90b6e PB |
12770 | static void |
12771 | do_t_tb (void) | |
12772 | { | |
fdfde340 | 12773 | unsigned Rn, Rm; |
92e90b6e PB |
12774 | int half; |
12775 | ||
12776 | half = (inst.instruction & 0x10) != 0; | |
e07e6e58 | 12777 | set_it_insn_type_last (); |
dfa9f0d5 PB |
12778 | constraint (inst.operands[0].immisreg, |
12779 | _("instruction requires register index")); | |
fdfde340 JM |
12780 | |
12781 | Rn = inst.operands[0].reg; | |
12782 | Rm = inst.operands[0].imm; | |
c921be7d | 12783 | |
fdfde340 JM |
12784 | constraint (Rn == REG_SP, BAD_SP); |
12785 | reject_bad_reg (Rm); | |
12786 | ||
92e90b6e PB |
12787 | constraint (!half && inst.operands[0].shifted, |
12788 | _("instruction does not allow shifted index")); | |
fdfde340 | 12789 | inst.instruction |= (Rn << 16) | Rm; |
92e90b6e PB |
12790 | } |
12791 | ||
74db7efb NC |
12792 | static void |
12793 | do_t_udf (void) | |
12794 | { | |
12795 | if (!inst.operands[0].present) | |
12796 | inst.operands[0].imm = 0; | |
12797 | ||
12798 | if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4) | |
12799 | { | |
12800 | constraint (inst.size_req == 2, | |
12801 | _("immediate value out of range")); | |
12802 | inst.instruction = THUMB_OP32 (inst.instruction); | |
12803 | inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4; | |
12804 | inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0; | |
12805 | } | |
12806 | else | |
12807 | { | |
12808 | inst.instruction = THUMB_OP16 (inst.instruction); | |
12809 | inst.instruction |= inst.operands[0].imm; | |
12810 | } | |
12811 | ||
12812 | set_it_insn_type (NEUTRAL_IT_INSN); | |
12813 | } | |
12814 | ||
12815 | ||
c19d1205 ZW |
12816 | static void |
12817 | do_t_usat (void) | |
12818 | { | |
3a21c15a | 12819 | do_t_ssat_usat (0); |
b99bd4ef NC |
12820 | } |
12821 | ||
12822 | static void | |
c19d1205 | 12823 | do_t_usat16 (void) |
b99bd4ef | 12824 | { |
fdfde340 JM |
12825 | unsigned Rd, Rn; |
12826 | ||
12827 | Rd = inst.operands[0].reg; | |
12828 | Rn = inst.operands[2].reg; | |
12829 | ||
12830 | reject_bad_reg (Rd); | |
12831 | reject_bad_reg (Rn); | |
12832 | ||
12833 | inst.instruction |= Rd << 8; | |
c19d1205 | 12834 | inst.instruction |= inst.operands[1].imm; |
fdfde340 | 12835 | inst.instruction |= Rn << 16; |
b99bd4ef | 12836 | } |
c19d1205 | 12837 | |
5287ad62 | 12838 | /* Neon instruction encoder helpers. */ |
5f4273c7 | 12839 | |
5287ad62 | 12840 | /* Encodings for the different types for various Neon opcodes. */ |
b99bd4ef | 12841 | |
5287ad62 JB |
12842 | /* An "invalid" code for the following tables. */ |
12843 | #define N_INV -1u | |
12844 | ||
12845 | struct neon_tab_entry | |
b99bd4ef | 12846 | { |
5287ad62 JB |
12847 | unsigned integer; |
12848 | unsigned float_or_poly; | |
12849 | unsigned scalar_or_imm; | |
12850 | }; | |
5f4273c7 | 12851 | |
5287ad62 JB |
12852 | /* Map overloaded Neon opcodes to their respective encodings. */ |
12853 | #define NEON_ENC_TAB \ | |
12854 | X(vabd, 0x0000700, 0x1200d00, N_INV), \ | |
12855 | X(vmax, 0x0000600, 0x0000f00, N_INV), \ | |
12856 | X(vmin, 0x0000610, 0x0200f00, N_INV), \ | |
12857 | X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ | |
12858 | X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ | |
12859 | X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ | |
12860 | X(vadd, 0x0000800, 0x0000d00, N_INV), \ | |
12861 | X(vsub, 0x1000800, 0x0200d00, N_INV), \ | |
12862 | X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ | |
12863 | X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ | |
12864 | X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ | |
12865 | /* Register variants of the following two instructions are encoded as | |
e07e6e58 | 12866 | vcge / vcgt with the operands reversed. */ \ |
92559b5b PB |
12867 | X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ |
12868 | X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ | |
62f3b8c8 PB |
12869 | X(vfma, N_INV, 0x0000c10, N_INV), \ |
12870 | X(vfms, N_INV, 0x0200c10, N_INV), \ | |
5287ad62 JB |
12871 | X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ |
12872 | X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ | |
12873 | X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ | |
12874 | X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ | |
12875 | X(vmlal, 0x0800800, N_INV, 0x0800240), \ | |
12876 | X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ | |
12877 | X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ | |
12878 | X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ | |
12879 | X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ | |
12880 | X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ | |
12881 | X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ | |
12882 | X(vshl, 0x0000400, N_INV, 0x0800510), \ | |
12883 | X(vqshl, 0x0000410, N_INV, 0x0800710), \ | |
12884 | X(vand, 0x0000110, N_INV, 0x0800030), \ | |
12885 | X(vbic, 0x0100110, N_INV, 0x0800030), \ | |
12886 | X(veor, 0x1000110, N_INV, N_INV), \ | |
12887 | X(vorn, 0x0300110, N_INV, 0x0800010), \ | |
12888 | X(vorr, 0x0200110, N_INV, 0x0800010), \ | |
12889 | X(vmvn, 0x1b00580, N_INV, 0x0800030), \ | |
12890 | X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ | |
12891 | X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ | |
12892 | X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ | |
12893 | X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ | |
12894 | X(vst1, 0x0000000, 0x0800000, N_INV), \ | |
12895 | X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ | |
12896 | X(vst2, 0x0000100, 0x0800100, N_INV), \ | |
12897 | X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ | |
12898 | X(vst3, 0x0000200, 0x0800200, N_INV), \ | |
12899 | X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ | |
12900 | X(vst4, 0x0000300, 0x0800300, N_INV), \ | |
12901 | X(vmovn, 0x1b20200, N_INV, N_INV), \ | |
12902 | X(vtrn, 0x1b20080, N_INV, N_INV), \ | |
12903 | X(vqmovn, 0x1b20200, N_INV, N_INV), \ | |
037e8744 JB |
12904 | X(vqmovun, 0x1b20240, N_INV, N_INV), \ |
12905 | X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ | |
e6655fda PB |
12906 | X(vnmla, 0xe100a40, 0xe100b40, N_INV), \ |
12907 | X(vnmls, 0xe100a00, 0xe100b00, N_INV), \ | |
62f3b8c8 PB |
12908 | X(vfnma, 0xe900a40, 0xe900b40, N_INV), \ |
12909 | X(vfnms, 0xe900a00, 0xe900b00, N_INV), \ | |
037e8744 JB |
12910 | X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ |
12911 | X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ | |
12912 | X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ | |
33399f07 MGD |
12913 | X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \ |
12914 | X(vseleq, 0xe000a00, N_INV, N_INV), \ | |
12915 | X(vselvs, 0xe100a00, N_INV, N_INV), \ | |
12916 | X(vselge, 0xe200a00, N_INV, N_INV), \ | |
73924fbc MGD |
12917 | X(vselgt, 0xe300a00, N_INV, N_INV), \ |
12918 | X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \ | |
7e8e6784 | 12919 | X(vminnm, 0xe800a40, 0x3200f10, N_INV), \ |
30bdf752 MGD |
12920 | X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \ |
12921 | X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \ | |
91ff7894 | 12922 | X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \ |
48adcd8e | 12923 | X(aes, 0x3b00300, N_INV, N_INV), \ |
3c9017d2 MGD |
12924 | X(sha3op, 0x2000c00, N_INV, N_INV), \ |
12925 | X(sha1h, 0x3b902c0, N_INV, N_INV), \ | |
12926 | X(sha2op, 0x3ba0380, N_INV, N_INV) | |
5287ad62 JB |
12927 | |
12928 | enum neon_opc | |
12929 | { | |
12930 | #define X(OPC,I,F,S) N_MNEM_##OPC | |
12931 | NEON_ENC_TAB | |
12932 | #undef X | |
12933 | }; | |
b99bd4ef | 12934 | |
5287ad62 JB |
12935 | static const struct neon_tab_entry neon_enc_tab[] = |
12936 | { | |
12937 | #define X(OPC,I,F,S) { (I), (F), (S) } | |
12938 | NEON_ENC_TAB | |
12939 | #undef X | |
12940 | }; | |
b99bd4ef | 12941 | |
88714cb8 DG |
12942 | /* Do not use these macros; instead, use NEON_ENCODE defined below. */ |
12943 | #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
12944 | #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
12945 | #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
12946 | #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
12947 | #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
12948 | #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
12949 | #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
12950 | #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
12951 | #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
12952 | #define NEON_ENC_SINGLE_(X) \ | |
037e8744 | 12953 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) |
88714cb8 | 12954 | #define NEON_ENC_DOUBLE_(X) \ |
037e8744 | 12955 | ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) |
33399f07 MGD |
12956 | #define NEON_ENC_FPV8_(X) \ |
12957 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000)) | |
5287ad62 | 12958 | |
88714cb8 DG |
12959 | #define NEON_ENCODE(type, inst) \ |
12960 | do \ | |
12961 | { \ | |
12962 | inst.instruction = NEON_ENC_##type##_ (inst.instruction); \ | |
12963 | inst.is_neon = 1; \ | |
12964 | } \ | |
12965 | while (0) | |
12966 | ||
12967 | #define check_neon_suffixes \ | |
12968 | do \ | |
12969 | { \ | |
12970 | if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \ | |
12971 | { \ | |
12972 | as_bad (_("invalid neon suffix for non neon instruction")); \ | |
12973 | return; \ | |
12974 | } \ | |
12975 | } \ | |
12976 | while (0) | |
12977 | ||
037e8744 JB |
12978 | /* Define shapes for instruction operands. The following mnemonic characters |
12979 | are used in this table: | |
5287ad62 | 12980 | |
037e8744 | 12981 | F - VFP S<n> register |
5287ad62 JB |
12982 | D - Neon D<n> register |
12983 | Q - Neon Q<n> register | |
12984 | I - Immediate | |
12985 | S - Scalar | |
12986 | R - ARM register | |
12987 | L - D<n> register list | |
5f4273c7 | 12988 | |
037e8744 JB |
12989 | This table is used to generate various data: |
12990 | - enumerations of the form NS_DDR to be used as arguments to | |
12991 | neon_select_shape. | |
12992 | - a table classifying shapes into single, double, quad, mixed. | |
5f4273c7 | 12993 | - a table used to drive neon_select_shape. */ |
b99bd4ef | 12994 | |
037e8744 JB |
12995 | #define NEON_SHAPE_DEF \ |
12996 | X(3, (D, D, D), DOUBLE), \ | |
12997 | X(3, (Q, Q, Q), QUAD), \ | |
12998 | X(3, (D, D, I), DOUBLE), \ | |
12999 | X(3, (Q, Q, I), QUAD), \ | |
13000 | X(3, (D, D, S), DOUBLE), \ | |
13001 | X(3, (Q, Q, S), QUAD), \ | |
13002 | X(2, (D, D), DOUBLE), \ | |
13003 | X(2, (Q, Q), QUAD), \ | |
13004 | X(2, (D, S), DOUBLE), \ | |
13005 | X(2, (Q, S), QUAD), \ | |
13006 | X(2, (D, R), DOUBLE), \ | |
13007 | X(2, (Q, R), QUAD), \ | |
13008 | X(2, (D, I), DOUBLE), \ | |
13009 | X(2, (Q, I), QUAD), \ | |
13010 | X(3, (D, L, D), DOUBLE), \ | |
13011 | X(2, (D, Q), MIXED), \ | |
13012 | X(2, (Q, D), MIXED), \ | |
13013 | X(3, (D, Q, I), MIXED), \ | |
13014 | X(3, (Q, D, I), MIXED), \ | |
13015 | X(3, (Q, D, D), MIXED), \ | |
13016 | X(3, (D, Q, Q), MIXED), \ | |
13017 | X(3, (Q, Q, D), MIXED), \ | |
13018 | X(3, (Q, D, S), MIXED), \ | |
13019 | X(3, (D, Q, S), MIXED), \ | |
13020 | X(4, (D, D, D, I), DOUBLE), \ | |
13021 | X(4, (Q, Q, Q, I), QUAD), \ | |
13022 | X(2, (F, F), SINGLE), \ | |
13023 | X(3, (F, F, F), SINGLE), \ | |
13024 | X(2, (F, I), SINGLE), \ | |
13025 | X(2, (F, D), MIXED), \ | |
13026 | X(2, (D, F), MIXED), \ | |
13027 | X(3, (F, F, I), MIXED), \ | |
13028 | X(4, (R, R, F, F), SINGLE), \ | |
13029 | X(4, (F, F, R, R), SINGLE), \ | |
13030 | X(3, (D, R, R), DOUBLE), \ | |
13031 | X(3, (R, R, D), DOUBLE), \ | |
13032 | X(2, (S, R), SINGLE), \ | |
13033 | X(2, (R, S), SINGLE), \ | |
13034 | X(2, (F, R), SINGLE), \ | |
13035 | X(2, (R, F), SINGLE) | |
13036 | ||
13037 | #define S2(A,B) NS_##A##B | |
13038 | #define S3(A,B,C) NS_##A##B##C | |
13039 | #define S4(A,B,C,D) NS_##A##B##C##D | |
13040 | ||
13041 | #define X(N, L, C) S##N L | |
13042 | ||
5287ad62 JB |
13043 | enum neon_shape |
13044 | { | |
037e8744 JB |
13045 | NEON_SHAPE_DEF, |
13046 | NS_NULL | |
5287ad62 | 13047 | }; |
b99bd4ef | 13048 | |
037e8744 JB |
13049 | #undef X |
13050 | #undef S2 | |
13051 | #undef S3 | |
13052 | #undef S4 | |
13053 | ||
13054 | enum neon_shape_class | |
13055 | { | |
13056 | SC_SINGLE, | |
13057 | SC_DOUBLE, | |
13058 | SC_QUAD, | |
13059 | SC_MIXED | |
13060 | }; | |
13061 | ||
13062 | #define X(N, L, C) SC_##C | |
13063 | ||
13064 | static enum neon_shape_class neon_shape_class[] = | |
13065 | { | |
13066 | NEON_SHAPE_DEF | |
13067 | }; | |
13068 | ||
13069 | #undef X | |
13070 | ||
13071 | enum neon_shape_el | |
13072 | { | |
13073 | SE_F, | |
13074 | SE_D, | |
13075 | SE_Q, | |
13076 | SE_I, | |
13077 | SE_S, | |
13078 | SE_R, | |
13079 | SE_L | |
13080 | }; | |
13081 | ||
13082 | /* Register widths of above. */ | |
13083 | static unsigned neon_shape_el_size[] = | |
13084 | { | |
13085 | 32, | |
13086 | 64, | |
13087 | 128, | |
13088 | 0, | |
13089 | 32, | |
13090 | 32, | |
13091 | 0 | |
13092 | }; | |
13093 | ||
13094 | struct neon_shape_info | |
13095 | { | |
13096 | unsigned els; | |
13097 | enum neon_shape_el el[NEON_MAX_TYPE_ELS]; | |
13098 | }; | |
13099 | ||
13100 | #define S2(A,B) { SE_##A, SE_##B } | |
13101 | #define S3(A,B,C) { SE_##A, SE_##B, SE_##C } | |
13102 | #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } | |
13103 | ||
13104 | #define X(N, L, C) { N, S##N L } | |
13105 | ||
13106 | static struct neon_shape_info neon_shape_tab[] = | |
13107 | { | |
13108 | NEON_SHAPE_DEF | |
13109 | }; | |
13110 | ||
13111 | #undef X | |
13112 | #undef S2 | |
13113 | #undef S3 | |
13114 | #undef S4 | |
13115 | ||
5287ad62 JB |
13116 | /* Bit masks used in type checking given instructions. |
13117 | 'N_EQK' means the type must be the same as (or based on in some way) the key | |
13118 | type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is | |
13119 | set, various other bits can be set as well in order to modify the meaning of | |
13120 | the type constraint. */ | |
13121 | ||
13122 | enum neon_type_mask | |
13123 | { | |
8e79c3df CM |
13124 | N_S8 = 0x0000001, |
13125 | N_S16 = 0x0000002, | |
13126 | N_S32 = 0x0000004, | |
13127 | N_S64 = 0x0000008, | |
13128 | N_U8 = 0x0000010, | |
13129 | N_U16 = 0x0000020, | |
13130 | N_U32 = 0x0000040, | |
13131 | N_U64 = 0x0000080, | |
13132 | N_I8 = 0x0000100, | |
13133 | N_I16 = 0x0000200, | |
13134 | N_I32 = 0x0000400, | |
13135 | N_I64 = 0x0000800, | |
13136 | N_8 = 0x0001000, | |
13137 | N_16 = 0x0002000, | |
13138 | N_32 = 0x0004000, | |
13139 | N_64 = 0x0008000, | |
13140 | N_P8 = 0x0010000, | |
13141 | N_P16 = 0x0020000, | |
13142 | N_F16 = 0x0040000, | |
13143 | N_F32 = 0x0080000, | |
13144 | N_F64 = 0x0100000, | |
4f51b4bd | 13145 | N_P64 = 0x0200000, |
c921be7d NC |
13146 | N_KEY = 0x1000000, /* Key element (main type specifier). */ |
13147 | N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */ | |
8e79c3df | 13148 | N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ |
91ff7894 | 13149 | N_UNT = 0x8000000, /* Must be explicitly untyped. */ |
c921be7d NC |
13150 | N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */ |
13151 | N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */ | |
13152 | N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */ | |
13153 | N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */ | |
13154 | N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */ | |
13155 | N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */ | |
13156 | N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */ | |
5287ad62 | 13157 | N_UTYP = 0, |
4f51b4bd | 13158 | N_MAX_NONSPECIAL = N_P64 |
5287ad62 JB |
13159 | }; |
13160 | ||
dcbf9037 JB |
13161 | #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) |
13162 | ||
5287ad62 JB |
13163 | #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) |
13164 | #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) | |
13165 | #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) | |
13166 | #define N_SUF_32 (N_SU_32 | N_F32) | |
13167 | #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) | |
13168 | #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) | |
13169 | ||
13170 | /* Pass this as the first type argument to neon_check_type to ignore types | |
13171 | altogether. */ | |
13172 | #define N_IGNORE_TYPE (N_KEY | N_EQK) | |
13173 | ||
037e8744 JB |
13174 | /* Select a "shape" for the current instruction (describing register types or |
13175 | sizes) from a list of alternatives. Return NS_NULL if the current instruction | |
13176 | doesn't fit. For non-polymorphic shapes, checking is usually done as a | |
13177 | function of operand parsing, so this function doesn't need to be called. | |
13178 | Shapes should be listed in order of decreasing length. */ | |
5287ad62 JB |
13179 | |
13180 | static enum neon_shape | |
037e8744 | 13181 | neon_select_shape (enum neon_shape shape, ...) |
5287ad62 | 13182 | { |
037e8744 JB |
13183 | va_list ap; |
13184 | enum neon_shape first_shape = shape; | |
5287ad62 JB |
13185 | |
13186 | /* Fix missing optional operands. FIXME: we don't know at this point how | |
13187 | many arguments we should have, so this makes the assumption that we have | |
13188 | > 1. This is true of all current Neon opcodes, I think, but may not be | |
13189 | true in the future. */ | |
13190 | if (!inst.operands[1].present) | |
13191 | inst.operands[1] = inst.operands[0]; | |
13192 | ||
037e8744 | 13193 | va_start (ap, shape); |
5f4273c7 | 13194 | |
21d799b5 | 13195 | for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int)) |
037e8744 JB |
13196 | { |
13197 | unsigned j; | |
13198 | int matches = 1; | |
13199 | ||
13200 | for (j = 0; j < neon_shape_tab[shape].els; j++) | |
477330fc RM |
13201 | { |
13202 | if (!inst.operands[j].present) | |
13203 | { | |
13204 | matches = 0; | |
13205 | break; | |
13206 | } | |
13207 | ||
13208 | switch (neon_shape_tab[shape].el[j]) | |
13209 | { | |
13210 | case SE_F: | |
13211 | if (!(inst.operands[j].isreg | |
13212 | && inst.operands[j].isvec | |
13213 | && inst.operands[j].issingle | |
13214 | && !inst.operands[j].isquad)) | |
13215 | matches = 0; | |
13216 | break; | |
13217 | ||
13218 | case SE_D: | |
13219 | if (!(inst.operands[j].isreg | |
13220 | && inst.operands[j].isvec | |
13221 | && !inst.operands[j].isquad | |
13222 | && !inst.operands[j].issingle)) | |
13223 | matches = 0; | |
13224 | break; | |
13225 | ||
13226 | case SE_R: | |
13227 | if (!(inst.operands[j].isreg | |
13228 | && !inst.operands[j].isvec)) | |
13229 | matches = 0; | |
13230 | break; | |
13231 | ||
13232 | case SE_Q: | |
13233 | if (!(inst.operands[j].isreg | |
13234 | && inst.operands[j].isvec | |
13235 | && inst.operands[j].isquad | |
13236 | && !inst.operands[j].issingle)) | |
13237 | matches = 0; | |
13238 | break; | |
13239 | ||
13240 | case SE_I: | |
13241 | if (!(!inst.operands[j].isreg | |
13242 | && !inst.operands[j].isscalar)) | |
13243 | matches = 0; | |
13244 | break; | |
13245 | ||
13246 | case SE_S: | |
13247 | if (!(!inst.operands[j].isreg | |
13248 | && inst.operands[j].isscalar)) | |
13249 | matches = 0; | |
13250 | break; | |
13251 | ||
13252 | case SE_L: | |
13253 | break; | |
13254 | } | |
3fde54a2 JZ |
13255 | if (!matches) |
13256 | break; | |
477330fc | 13257 | } |
ad6cec43 MGD |
13258 | if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present)) |
13259 | /* We've matched all the entries in the shape table, and we don't | |
13260 | have any left over operands which have not been matched. */ | |
477330fc | 13261 | break; |
037e8744 | 13262 | } |
5f4273c7 | 13263 | |
037e8744 | 13264 | va_end (ap); |
5287ad62 | 13265 | |
037e8744 JB |
13266 | if (shape == NS_NULL && first_shape != NS_NULL) |
13267 | first_error (_("invalid instruction shape")); | |
5287ad62 | 13268 | |
037e8744 JB |
13269 | return shape; |
13270 | } | |
5287ad62 | 13271 | |
037e8744 JB |
13272 | /* True if SHAPE is predominantly a quadword operation (most of the time, this |
13273 | means the Q bit should be set). */ | |
13274 | ||
13275 | static int | |
13276 | neon_quad (enum neon_shape shape) | |
13277 | { | |
13278 | return neon_shape_class[shape] == SC_QUAD; | |
5287ad62 | 13279 | } |
037e8744 | 13280 | |
5287ad62 JB |
13281 | static void |
13282 | neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, | |
477330fc | 13283 | unsigned *g_size) |
5287ad62 JB |
13284 | { |
13285 | /* Allow modification to be made to types which are constrained to be | |
13286 | based on the key element, based on bits set alongside N_EQK. */ | |
13287 | if ((typebits & N_EQK) != 0) | |
13288 | { | |
13289 | if ((typebits & N_HLF) != 0) | |
13290 | *g_size /= 2; | |
13291 | else if ((typebits & N_DBL) != 0) | |
13292 | *g_size *= 2; | |
13293 | if ((typebits & N_SGN) != 0) | |
13294 | *g_type = NT_signed; | |
13295 | else if ((typebits & N_UNS) != 0) | |
477330fc | 13296 | *g_type = NT_unsigned; |
5287ad62 | 13297 | else if ((typebits & N_INT) != 0) |
477330fc | 13298 | *g_type = NT_integer; |
5287ad62 | 13299 | else if ((typebits & N_FLT) != 0) |
477330fc | 13300 | *g_type = NT_float; |
dcbf9037 | 13301 | else if ((typebits & N_SIZ) != 0) |
477330fc | 13302 | *g_type = NT_untyped; |
5287ad62 JB |
13303 | } |
13304 | } | |
5f4273c7 | 13305 | |
5287ad62 JB |
13306 | /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" |
13307 | operand type, i.e. the single type specified in a Neon instruction when it | |
13308 | is the only one given. */ | |
13309 | ||
13310 | static struct neon_type_el | |
13311 | neon_type_promote (struct neon_type_el *key, unsigned thisarg) | |
13312 | { | |
13313 | struct neon_type_el dest = *key; | |
5f4273c7 | 13314 | |
9c2799c2 | 13315 | gas_assert ((thisarg & N_EQK) != 0); |
5f4273c7 | 13316 | |
5287ad62 JB |
13317 | neon_modify_type_size (thisarg, &dest.type, &dest.size); |
13318 | ||
13319 | return dest; | |
13320 | } | |
13321 | ||
13322 | /* Convert Neon type and size into compact bitmask representation. */ | |
13323 | ||
13324 | static enum neon_type_mask | |
13325 | type_chk_of_el_type (enum neon_el_type type, unsigned size) | |
13326 | { | |
13327 | switch (type) | |
13328 | { | |
13329 | case NT_untyped: | |
13330 | switch (size) | |
477330fc RM |
13331 | { |
13332 | case 8: return N_8; | |
13333 | case 16: return N_16; | |
13334 | case 32: return N_32; | |
13335 | case 64: return N_64; | |
13336 | default: ; | |
13337 | } | |
5287ad62 JB |
13338 | break; |
13339 | ||
13340 | case NT_integer: | |
13341 | switch (size) | |
477330fc RM |
13342 | { |
13343 | case 8: return N_I8; | |
13344 | case 16: return N_I16; | |
13345 | case 32: return N_I32; | |
13346 | case 64: return N_I64; | |
13347 | default: ; | |
13348 | } | |
5287ad62 JB |
13349 | break; |
13350 | ||
13351 | case NT_float: | |
037e8744 | 13352 | switch (size) |
477330fc | 13353 | { |
8e79c3df | 13354 | case 16: return N_F16; |
477330fc RM |
13355 | case 32: return N_F32; |
13356 | case 64: return N_F64; | |
13357 | default: ; | |
13358 | } | |
5287ad62 JB |
13359 | break; |
13360 | ||
13361 | case NT_poly: | |
13362 | switch (size) | |
477330fc RM |
13363 | { |
13364 | case 8: return N_P8; | |
13365 | case 16: return N_P16; | |
4f51b4bd | 13366 | case 64: return N_P64; |
477330fc RM |
13367 | default: ; |
13368 | } | |
5287ad62 JB |
13369 | break; |
13370 | ||
13371 | case NT_signed: | |
13372 | switch (size) | |
477330fc RM |
13373 | { |
13374 | case 8: return N_S8; | |
13375 | case 16: return N_S16; | |
13376 | case 32: return N_S32; | |
13377 | case 64: return N_S64; | |
13378 | default: ; | |
13379 | } | |
5287ad62 JB |
13380 | break; |
13381 | ||
13382 | case NT_unsigned: | |
13383 | switch (size) | |
477330fc RM |
13384 | { |
13385 | case 8: return N_U8; | |
13386 | case 16: return N_U16; | |
13387 | case 32: return N_U32; | |
13388 | case 64: return N_U64; | |
13389 | default: ; | |
13390 | } | |
5287ad62 JB |
13391 | break; |
13392 | ||
13393 | default: ; | |
13394 | } | |
5f4273c7 | 13395 | |
5287ad62 JB |
13396 | return N_UTYP; |
13397 | } | |
13398 | ||
13399 | /* Convert compact Neon bitmask type representation to a type and size. Only | |
13400 | handles the case where a single bit is set in the mask. */ | |
13401 | ||
dcbf9037 | 13402 | static int |
5287ad62 | 13403 | el_type_of_type_chk (enum neon_el_type *type, unsigned *size, |
477330fc | 13404 | enum neon_type_mask mask) |
5287ad62 | 13405 | { |
dcbf9037 JB |
13406 | if ((mask & N_EQK) != 0) |
13407 | return FAIL; | |
13408 | ||
5287ad62 JB |
13409 | if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) |
13410 | *size = 8; | |
c70a8987 | 13411 | else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0) |
5287ad62 | 13412 | *size = 16; |
dcbf9037 | 13413 | else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) |
5287ad62 | 13414 | *size = 32; |
4f51b4bd | 13415 | else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0) |
5287ad62 | 13416 | *size = 64; |
dcbf9037 JB |
13417 | else |
13418 | return FAIL; | |
13419 | ||
5287ad62 JB |
13420 | if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) |
13421 | *type = NT_signed; | |
dcbf9037 | 13422 | else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) |
5287ad62 | 13423 | *type = NT_unsigned; |
dcbf9037 | 13424 | else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) |
5287ad62 | 13425 | *type = NT_integer; |
dcbf9037 | 13426 | else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) |
5287ad62 | 13427 | *type = NT_untyped; |
4f51b4bd | 13428 | else if ((mask & (N_P8 | N_P16 | N_P64)) != 0) |
5287ad62 | 13429 | *type = NT_poly; |
c70a8987 | 13430 | else if ((mask & (N_F16 | N_F32 | N_F64)) != 0) |
5287ad62 | 13431 | *type = NT_float; |
dcbf9037 JB |
13432 | else |
13433 | return FAIL; | |
5f4273c7 | 13434 | |
dcbf9037 | 13435 | return SUCCESS; |
5287ad62 JB |
13436 | } |
13437 | ||
13438 | /* Modify a bitmask of allowed types. This is only needed for type | |
13439 | relaxation. */ | |
13440 | ||
13441 | static unsigned | |
13442 | modify_types_allowed (unsigned allowed, unsigned mods) | |
13443 | { | |
13444 | unsigned size; | |
13445 | enum neon_el_type type; | |
13446 | unsigned destmask; | |
13447 | int i; | |
5f4273c7 | 13448 | |
5287ad62 | 13449 | destmask = 0; |
5f4273c7 | 13450 | |
5287ad62 JB |
13451 | for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) |
13452 | { | |
21d799b5 | 13453 | if (el_type_of_type_chk (&type, &size, |
477330fc RM |
13454 | (enum neon_type_mask) (allowed & i)) == SUCCESS) |
13455 | { | |
13456 | neon_modify_type_size (mods, &type, &size); | |
13457 | destmask |= type_chk_of_el_type (type, size); | |
13458 | } | |
5287ad62 | 13459 | } |
5f4273c7 | 13460 | |
5287ad62 JB |
13461 | return destmask; |
13462 | } | |
13463 | ||
13464 | /* Check type and return type classification. | |
13465 | The manual states (paraphrase): If one datatype is given, it indicates the | |
13466 | type given in: | |
13467 | - the second operand, if there is one | |
13468 | - the operand, if there is no second operand | |
13469 | - the result, if there are no operands. | |
13470 | This isn't quite good enough though, so we use a concept of a "key" datatype | |
13471 | which is set on a per-instruction basis, which is the one which matters when | |
13472 | only one data type is written. | |
13473 | Note: this function has side-effects (e.g. filling in missing operands). All | |
037e8744 | 13474 | Neon instructions should call it before performing bit encoding. */ |
5287ad62 JB |
13475 | |
13476 | static struct neon_type_el | |
13477 | neon_check_type (unsigned els, enum neon_shape ns, ...) | |
13478 | { | |
13479 | va_list ap; | |
13480 | unsigned i, pass, key_el = 0; | |
13481 | unsigned types[NEON_MAX_TYPE_ELS]; | |
13482 | enum neon_el_type k_type = NT_invtype; | |
13483 | unsigned k_size = -1u; | |
13484 | struct neon_type_el badtype = {NT_invtype, -1}; | |
13485 | unsigned key_allowed = 0; | |
13486 | ||
13487 | /* Optional registers in Neon instructions are always (not) in operand 1. | |
13488 | Fill in the missing operand here, if it was omitted. */ | |
13489 | if (els > 1 && !inst.operands[1].present) | |
13490 | inst.operands[1] = inst.operands[0]; | |
13491 | ||
13492 | /* Suck up all the varargs. */ | |
13493 | va_start (ap, ns); | |
13494 | for (i = 0; i < els; i++) | |
13495 | { | |
13496 | unsigned thisarg = va_arg (ap, unsigned); | |
13497 | if (thisarg == N_IGNORE_TYPE) | |
477330fc RM |
13498 | { |
13499 | va_end (ap); | |
13500 | return badtype; | |
13501 | } | |
5287ad62 JB |
13502 | types[i] = thisarg; |
13503 | if ((thisarg & N_KEY) != 0) | |
477330fc | 13504 | key_el = i; |
5287ad62 JB |
13505 | } |
13506 | va_end (ap); | |
13507 | ||
dcbf9037 JB |
13508 | if (inst.vectype.elems > 0) |
13509 | for (i = 0; i < els; i++) | |
13510 | if (inst.operands[i].vectype.type != NT_invtype) | |
477330fc RM |
13511 | { |
13512 | first_error (_("types specified in both the mnemonic and operands")); | |
13513 | return badtype; | |
13514 | } | |
dcbf9037 | 13515 | |
5287ad62 JB |
13516 | /* Duplicate inst.vectype elements here as necessary. |
13517 | FIXME: No idea if this is exactly the same as the ARM assembler, | |
13518 | particularly when an insn takes one register and one non-register | |
13519 | operand. */ | |
13520 | if (inst.vectype.elems == 1 && els > 1) | |
13521 | { | |
13522 | unsigned j; | |
13523 | inst.vectype.elems = els; | |
13524 | inst.vectype.el[key_el] = inst.vectype.el[0]; | |
13525 | for (j = 0; j < els; j++) | |
477330fc RM |
13526 | if (j != key_el) |
13527 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
13528 | types[j]); | |
dcbf9037 JB |
13529 | } |
13530 | else if (inst.vectype.elems == 0 && els > 0) | |
13531 | { | |
13532 | unsigned j; | |
13533 | /* No types were given after the mnemonic, so look for types specified | |
477330fc RM |
13534 | after each operand. We allow some flexibility here; as long as the |
13535 | "key" operand has a type, we can infer the others. */ | |
dcbf9037 | 13536 | for (j = 0; j < els; j++) |
477330fc RM |
13537 | if (inst.operands[j].vectype.type != NT_invtype) |
13538 | inst.vectype.el[j] = inst.operands[j].vectype; | |
dcbf9037 JB |
13539 | |
13540 | if (inst.operands[key_el].vectype.type != NT_invtype) | |
477330fc RM |
13541 | { |
13542 | for (j = 0; j < els; j++) | |
13543 | if (inst.operands[j].vectype.type == NT_invtype) | |
13544 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
13545 | types[j]); | |
13546 | } | |
dcbf9037 | 13547 | else |
477330fc RM |
13548 | { |
13549 | first_error (_("operand types can't be inferred")); | |
13550 | return badtype; | |
13551 | } | |
5287ad62 JB |
13552 | } |
13553 | else if (inst.vectype.elems != els) | |
13554 | { | |
dcbf9037 | 13555 | first_error (_("type specifier has the wrong number of parts")); |
5287ad62 JB |
13556 | return badtype; |
13557 | } | |
13558 | ||
13559 | for (pass = 0; pass < 2; pass++) | |
13560 | { | |
13561 | for (i = 0; i < els; i++) | |
477330fc RM |
13562 | { |
13563 | unsigned thisarg = types[i]; | |
13564 | unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) | |
13565 | ? modify_types_allowed (key_allowed, thisarg) : thisarg; | |
13566 | enum neon_el_type g_type = inst.vectype.el[i].type; | |
13567 | unsigned g_size = inst.vectype.el[i].size; | |
13568 | ||
13569 | /* Decay more-specific signed & unsigned types to sign-insensitive | |
5287ad62 | 13570 | integer types if sign-specific variants are unavailable. */ |
477330fc | 13571 | if ((g_type == NT_signed || g_type == NT_unsigned) |
5287ad62 JB |
13572 | && (types_allowed & N_SU_ALL) == 0) |
13573 | g_type = NT_integer; | |
13574 | ||
477330fc | 13575 | /* If only untyped args are allowed, decay any more specific types to |
5287ad62 JB |
13576 | them. Some instructions only care about signs for some element |
13577 | sizes, so handle that properly. */ | |
477330fc | 13578 | if (((types_allowed & N_UNT) == 0) |
91ff7894 MGD |
13579 | && ((g_size == 8 && (types_allowed & N_8) != 0) |
13580 | || (g_size == 16 && (types_allowed & N_16) != 0) | |
13581 | || (g_size == 32 && (types_allowed & N_32) != 0) | |
13582 | || (g_size == 64 && (types_allowed & N_64) != 0))) | |
5287ad62 JB |
13583 | g_type = NT_untyped; |
13584 | ||
477330fc RM |
13585 | if (pass == 0) |
13586 | { | |
13587 | if ((thisarg & N_KEY) != 0) | |
13588 | { | |
13589 | k_type = g_type; | |
13590 | k_size = g_size; | |
13591 | key_allowed = thisarg & ~N_KEY; | |
13592 | } | |
13593 | } | |
13594 | else | |
13595 | { | |
13596 | if ((thisarg & N_VFP) != 0) | |
13597 | { | |
13598 | enum neon_shape_el regshape; | |
13599 | unsigned regwidth, match; | |
99b253c5 NC |
13600 | |
13601 | /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */ | |
13602 | if (ns == NS_NULL) | |
13603 | { | |
13604 | first_error (_("invalid instruction shape")); | |
13605 | return badtype; | |
13606 | } | |
477330fc RM |
13607 | regshape = neon_shape_tab[ns].el[i]; |
13608 | regwidth = neon_shape_el_size[regshape]; | |
13609 | ||
13610 | /* In VFP mode, operands must match register widths. If we | |
13611 | have a key operand, use its width, else use the width of | |
13612 | the current operand. */ | |
13613 | if (k_size != -1u) | |
13614 | match = k_size; | |
13615 | else | |
13616 | match = g_size; | |
13617 | ||
13618 | if (regwidth != match) | |
13619 | { | |
13620 | first_error (_("operand size must match register width")); | |
13621 | return badtype; | |
13622 | } | |
13623 | } | |
13624 | ||
13625 | if ((thisarg & N_EQK) == 0) | |
13626 | { | |
13627 | unsigned given_type = type_chk_of_el_type (g_type, g_size); | |
13628 | ||
13629 | if ((given_type & types_allowed) == 0) | |
13630 | { | |
13631 | first_error (_("bad type in Neon instruction")); | |
13632 | return badtype; | |
13633 | } | |
13634 | } | |
13635 | else | |
13636 | { | |
13637 | enum neon_el_type mod_k_type = k_type; | |
13638 | unsigned mod_k_size = k_size; | |
13639 | neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); | |
13640 | if (g_type != mod_k_type || g_size != mod_k_size) | |
13641 | { | |
13642 | first_error (_("inconsistent types in Neon instruction")); | |
13643 | return badtype; | |
13644 | } | |
13645 | } | |
13646 | } | |
13647 | } | |
5287ad62 JB |
13648 | } |
13649 | ||
13650 | return inst.vectype.el[key_el]; | |
13651 | } | |
13652 | ||
037e8744 | 13653 | /* Neon-style VFP instruction forwarding. */ |
5287ad62 | 13654 | |
037e8744 JB |
13655 | /* Thumb VFP instructions have 0xE in the condition field. */ |
13656 | ||
13657 | static void | |
13658 | do_vfp_cond_or_thumb (void) | |
5287ad62 | 13659 | { |
88714cb8 DG |
13660 | inst.is_neon = 1; |
13661 | ||
5287ad62 | 13662 | if (thumb_mode) |
037e8744 | 13663 | inst.instruction |= 0xe0000000; |
5287ad62 | 13664 | else |
037e8744 | 13665 | inst.instruction |= inst.cond << 28; |
5287ad62 JB |
13666 | } |
13667 | ||
037e8744 JB |
13668 | /* Look up and encode a simple mnemonic, for use as a helper function for the |
13669 | Neon-style VFP syntax. This avoids duplication of bits of the insns table, | |
13670 | etc. It is assumed that operand parsing has already been done, and that the | |
13671 | operands are in the form expected by the given opcode (this isn't necessarily | |
13672 | the same as the form in which they were parsed, hence some massaging must | |
13673 | take place before this function is called). | |
13674 | Checks current arch version against that in the looked-up opcode. */ | |
5287ad62 | 13675 | |
037e8744 JB |
13676 | static void |
13677 | do_vfp_nsyn_opcode (const char *opname) | |
5287ad62 | 13678 | { |
037e8744 | 13679 | const struct asm_opcode *opcode; |
5f4273c7 | 13680 | |
21d799b5 | 13681 | opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname); |
5287ad62 | 13682 | |
037e8744 JB |
13683 | if (!opcode) |
13684 | abort (); | |
5287ad62 | 13685 | |
037e8744 | 13686 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, |
477330fc RM |
13687 | thumb_mode ? *opcode->tvariant : *opcode->avariant), |
13688 | _(BAD_FPU)); | |
5287ad62 | 13689 | |
88714cb8 DG |
13690 | inst.is_neon = 1; |
13691 | ||
037e8744 JB |
13692 | if (thumb_mode) |
13693 | { | |
13694 | inst.instruction = opcode->tvalue; | |
13695 | opcode->tencode (); | |
13696 | } | |
13697 | else | |
13698 | { | |
13699 | inst.instruction = (inst.cond << 28) | opcode->avalue; | |
13700 | opcode->aencode (); | |
13701 | } | |
13702 | } | |
5287ad62 JB |
13703 | |
13704 | static void | |
037e8744 | 13705 | do_vfp_nsyn_add_sub (enum neon_shape rs) |
5287ad62 | 13706 | { |
037e8744 JB |
13707 | int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; |
13708 | ||
13709 | if (rs == NS_FFF) | |
13710 | { | |
13711 | if (is_add) | |
477330fc | 13712 | do_vfp_nsyn_opcode ("fadds"); |
037e8744 | 13713 | else |
477330fc | 13714 | do_vfp_nsyn_opcode ("fsubs"); |
037e8744 JB |
13715 | } |
13716 | else | |
13717 | { | |
13718 | if (is_add) | |
477330fc | 13719 | do_vfp_nsyn_opcode ("faddd"); |
037e8744 | 13720 | else |
477330fc | 13721 | do_vfp_nsyn_opcode ("fsubd"); |
037e8744 JB |
13722 | } |
13723 | } | |
13724 | ||
13725 | /* Check operand types to see if this is a VFP instruction, and if so call | |
13726 | PFN (). */ | |
13727 | ||
13728 | static int | |
13729 | try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) | |
13730 | { | |
13731 | enum neon_shape rs; | |
13732 | struct neon_type_el et; | |
13733 | ||
13734 | switch (args) | |
13735 | { | |
13736 | case 2: | |
13737 | rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
13738 | et = neon_check_type (2, rs, | |
477330fc | 13739 | N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); |
037e8744 | 13740 | break; |
5f4273c7 | 13741 | |
037e8744 JB |
13742 | case 3: |
13743 | rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
13744 | et = neon_check_type (3, rs, | |
477330fc | 13745 | N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); |
037e8744 JB |
13746 | break; |
13747 | ||
13748 | default: | |
13749 | abort (); | |
13750 | } | |
13751 | ||
13752 | if (et.type != NT_invtype) | |
13753 | { | |
13754 | pfn (rs); | |
13755 | return SUCCESS; | |
13756 | } | |
037e8744 | 13757 | |
99b253c5 | 13758 | inst.error = NULL; |
037e8744 JB |
13759 | return FAIL; |
13760 | } | |
13761 | ||
13762 | static void | |
13763 | do_vfp_nsyn_mla_mls (enum neon_shape rs) | |
13764 | { | |
13765 | int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; | |
5f4273c7 | 13766 | |
037e8744 JB |
13767 | if (rs == NS_FFF) |
13768 | { | |
13769 | if (is_mla) | |
477330fc | 13770 | do_vfp_nsyn_opcode ("fmacs"); |
037e8744 | 13771 | else |
477330fc | 13772 | do_vfp_nsyn_opcode ("fnmacs"); |
037e8744 JB |
13773 | } |
13774 | else | |
13775 | { | |
13776 | if (is_mla) | |
477330fc | 13777 | do_vfp_nsyn_opcode ("fmacd"); |
037e8744 | 13778 | else |
477330fc | 13779 | do_vfp_nsyn_opcode ("fnmacd"); |
037e8744 JB |
13780 | } |
13781 | } | |
13782 | ||
62f3b8c8 PB |
13783 | static void |
13784 | do_vfp_nsyn_fma_fms (enum neon_shape rs) | |
13785 | { | |
13786 | int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma; | |
13787 | ||
13788 | if (rs == NS_FFF) | |
13789 | { | |
13790 | if (is_fma) | |
477330fc | 13791 | do_vfp_nsyn_opcode ("ffmas"); |
62f3b8c8 | 13792 | else |
477330fc | 13793 | do_vfp_nsyn_opcode ("ffnmas"); |
62f3b8c8 PB |
13794 | } |
13795 | else | |
13796 | { | |
13797 | if (is_fma) | |
477330fc | 13798 | do_vfp_nsyn_opcode ("ffmad"); |
62f3b8c8 | 13799 | else |
477330fc | 13800 | do_vfp_nsyn_opcode ("ffnmad"); |
62f3b8c8 PB |
13801 | } |
13802 | } | |
13803 | ||
037e8744 JB |
13804 | static void |
13805 | do_vfp_nsyn_mul (enum neon_shape rs) | |
13806 | { | |
13807 | if (rs == NS_FFF) | |
13808 | do_vfp_nsyn_opcode ("fmuls"); | |
13809 | else | |
13810 | do_vfp_nsyn_opcode ("fmuld"); | |
13811 | } | |
13812 | ||
13813 | static void | |
13814 | do_vfp_nsyn_abs_neg (enum neon_shape rs) | |
13815 | { | |
13816 | int is_neg = (inst.instruction & 0x80) != 0; | |
13817 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); | |
13818 | ||
13819 | if (rs == NS_FF) | |
13820 | { | |
13821 | if (is_neg) | |
477330fc | 13822 | do_vfp_nsyn_opcode ("fnegs"); |
037e8744 | 13823 | else |
477330fc | 13824 | do_vfp_nsyn_opcode ("fabss"); |
037e8744 JB |
13825 | } |
13826 | else | |
13827 | { | |
13828 | if (is_neg) | |
477330fc | 13829 | do_vfp_nsyn_opcode ("fnegd"); |
037e8744 | 13830 | else |
477330fc | 13831 | do_vfp_nsyn_opcode ("fabsd"); |
037e8744 JB |
13832 | } |
13833 | } | |
13834 | ||
13835 | /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision | |
13836 | insns belong to Neon, and are handled elsewhere. */ | |
13837 | ||
13838 | static void | |
13839 | do_vfp_nsyn_ldm_stm (int is_dbmode) | |
13840 | { | |
13841 | int is_ldm = (inst.instruction & (1 << 20)) != 0; | |
13842 | if (is_ldm) | |
13843 | { | |
13844 | if (is_dbmode) | |
477330fc | 13845 | do_vfp_nsyn_opcode ("fldmdbs"); |
037e8744 | 13846 | else |
477330fc | 13847 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 JB |
13848 | } |
13849 | else | |
13850 | { | |
13851 | if (is_dbmode) | |
477330fc | 13852 | do_vfp_nsyn_opcode ("fstmdbs"); |
037e8744 | 13853 | else |
477330fc | 13854 | do_vfp_nsyn_opcode ("fstmias"); |
037e8744 JB |
13855 | } |
13856 | } | |
13857 | ||
037e8744 JB |
13858 | static void |
13859 | do_vfp_nsyn_sqrt (void) | |
13860 | { | |
13861 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
13862 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13863 | |
037e8744 JB |
13864 | if (rs == NS_FF) |
13865 | do_vfp_nsyn_opcode ("fsqrts"); | |
13866 | else | |
13867 | do_vfp_nsyn_opcode ("fsqrtd"); | |
13868 | } | |
13869 | ||
13870 | static void | |
13871 | do_vfp_nsyn_div (void) | |
13872 | { | |
13873 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
13874 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
13875 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13876 | |
037e8744 JB |
13877 | if (rs == NS_FFF) |
13878 | do_vfp_nsyn_opcode ("fdivs"); | |
13879 | else | |
13880 | do_vfp_nsyn_opcode ("fdivd"); | |
13881 | } | |
13882 | ||
13883 | static void | |
13884 | do_vfp_nsyn_nmul (void) | |
13885 | { | |
13886 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
13887 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
13888 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13889 | |
037e8744 JB |
13890 | if (rs == NS_FFF) |
13891 | { | |
88714cb8 | 13892 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
13893 | do_vfp_sp_dyadic (); |
13894 | } | |
13895 | else | |
13896 | { | |
88714cb8 | 13897 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
13898 | do_vfp_dp_rd_rn_rm (); |
13899 | } | |
13900 | do_vfp_cond_or_thumb (); | |
13901 | } | |
13902 | ||
13903 | static void | |
13904 | do_vfp_nsyn_cmp (void) | |
13905 | { | |
13906 | if (inst.operands[1].isreg) | |
13907 | { | |
13908 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
13909 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13910 | |
037e8744 | 13911 | if (rs == NS_FF) |
477330fc RM |
13912 | { |
13913 | NEON_ENCODE (SINGLE, inst); | |
13914 | do_vfp_sp_monadic (); | |
13915 | } | |
037e8744 | 13916 | else |
477330fc RM |
13917 | { |
13918 | NEON_ENCODE (DOUBLE, inst); | |
13919 | do_vfp_dp_rd_rm (); | |
13920 | } | |
037e8744 JB |
13921 | } |
13922 | else | |
13923 | { | |
13924 | enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); | |
13925 | neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); | |
13926 | ||
13927 | switch (inst.instruction & 0x0fffffff) | |
477330fc RM |
13928 | { |
13929 | case N_MNEM_vcmp: | |
13930 | inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; | |
13931 | break; | |
13932 | case N_MNEM_vcmpe: | |
13933 | inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; | |
13934 | break; | |
13935 | default: | |
13936 | abort (); | |
13937 | } | |
5f4273c7 | 13938 | |
037e8744 | 13939 | if (rs == NS_FI) |
477330fc RM |
13940 | { |
13941 | NEON_ENCODE (SINGLE, inst); | |
13942 | do_vfp_sp_compare_z (); | |
13943 | } | |
037e8744 | 13944 | else |
477330fc RM |
13945 | { |
13946 | NEON_ENCODE (DOUBLE, inst); | |
13947 | do_vfp_dp_rd (); | |
13948 | } | |
037e8744 JB |
13949 | } |
13950 | do_vfp_cond_or_thumb (); | |
13951 | } | |
13952 | ||
13953 | static void | |
13954 | nsyn_insert_sp (void) | |
13955 | { | |
13956 | inst.operands[1] = inst.operands[0]; | |
13957 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
fdfde340 | 13958 | inst.operands[0].reg = REG_SP; |
037e8744 JB |
13959 | inst.operands[0].isreg = 1; |
13960 | inst.operands[0].writeback = 1; | |
13961 | inst.operands[0].present = 1; | |
13962 | } | |
13963 | ||
13964 | static void | |
13965 | do_vfp_nsyn_push (void) | |
13966 | { | |
13967 | nsyn_insert_sp (); | |
13968 | if (inst.operands[1].issingle) | |
13969 | do_vfp_nsyn_opcode ("fstmdbs"); | |
13970 | else | |
13971 | do_vfp_nsyn_opcode ("fstmdbd"); | |
13972 | } | |
13973 | ||
13974 | static void | |
13975 | do_vfp_nsyn_pop (void) | |
13976 | { | |
13977 | nsyn_insert_sp (); | |
13978 | if (inst.operands[1].issingle) | |
22b5b651 | 13979 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 | 13980 | else |
22b5b651 | 13981 | do_vfp_nsyn_opcode ("fldmiad"); |
037e8744 JB |
13982 | } |
13983 | ||
13984 | /* Fix up Neon data-processing instructions, ORing in the correct bits for | |
13985 | ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ | |
13986 | ||
88714cb8 DG |
13987 | static void |
13988 | neon_dp_fixup (struct arm_it* insn) | |
037e8744 | 13989 | { |
88714cb8 DG |
13990 | unsigned int i = insn->instruction; |
13991 | insn->is_neon = 1; | |
13992 | ||
037e8744 JB |
13993 | if (thumb_mode) |
13994 | { | |
13995 | /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ | |
13996 | if (i & (1 << 24)) | |
477330fc | 13997 | i |= 1 << 28; |
5f4273c7 | 13998 | |
037e8744 | 13999 | i &= ~(1 << 24); |
5f4273c7 | 14000 | |
037e8744 JB |
14001 | i |= 0xef000000; |
14002 | } | |
14003 | else | |
14004 | i |= 0xf2000000; | |
5f4273c7 | 14005 | |
88714cb8 | 14006 | insn->instruction = i; |
037e8744 JB |
14007 | } |
14008 | ||
14009 | /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 | |
14010 | (0, 1, 2, 3). */ | |
14011 | ||
14012 | static unsigned | |
14013 | neon_logbits (unsigned x) | |
14014 | { | |
14015 | return ffs (x) - 4; | |
14016 | } | |
14017 | ||
14018 | #define LOW4(R) ((R) & 0xf) | |
14019 | #define HI1(R) (((R) >> 4) & 1) | |
14020 | ||
14021 | /* Encode insns with bit pattern: | |
14022 | ||
14023 | |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
14024 | | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | | |
5f4273c7 | 14025 | |
037e8744 JB |
14026 | SIZE is passed in bits. -1 means size field isn't changed, in case it has a |
14027 | different meaning for some instruction. */ | |
14028 | ||
14029 | static void | |
14030 | neon_three_same (int isquad, int ubit, int size) | |
14031 | { | |
14032 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14033 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14034 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14035 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14036 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14037 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14038 | inst.instruction |= (isquad != 0) << 6; | |
14039 | inst.instruction |= (ubit != 0) << 24; | |
14040 | if (size != -1) | |
14041 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 14042 | |
88714cb8 | 14043 | neon_dp_fixup (&inst); |
037e8744 JB |
14044 | } |
14045 | ||
14046 | /* Encode instructions of the form: | |
14047 | ||
14048 | |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| | |
14049 | | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | | |
5287ad62 JB |
14050 | |
14051 | Don't write size if SIZE == -1. */ | |
14052 | ||
14053 | static void | |
14054 | neon_two_same (int qbit, int ubit, int size) | |
14055 | { | |
14056 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14057 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14058 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14059 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14060 | inst.instruction |= (qbit != 0) << 6; | |
14061 | inst.instruction |= (ubit != 0) << 24; | |
14062 | ||
14063 | if (size != -1) | |
14064 | inst.instruction |= neon_logbits (size) << 18; | |
14065 | ||
88714cb8 | 14066 | neon_dp_fixup (&inst); |
5287ad62 JB |
14067 | } |
14068 | ||
14069 | /* Neon instruction encoders, in approximate order of appearance. */ | |
14070 | ||
14071 | static void | |
14072 | do_neon_dyadic_i_su (void) | |
14073 | { | |
037e8744 | 14074 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14075 | struct neon_type_el et = neon_check_type (3, rs, |
14076 | N_EQK, N_EQK, N_SU_32 | N_KEY); | |
037e8744 | 14077 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14078 | } |
14079 | ||
14080 | static void | |
14081 | do_neon_dyadic_i64_su (void) | |
14082 | { | |
037e8744 | 14083 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14084 | struct neon_type_el et = neon_check_type (3, rs, |
14085 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
037e8744 | 14086 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14087 | } |
14088 | ||
14089 | static void | |
14090 | neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, | |
477330fc | 14091 | unsigned immbits) |
5287ad62 JB |
14092 | { |
14093 | unsigned size = et.size >> 3; | |
14094 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14095 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14096 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14097 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14098 | inst.instruction |= (isquad != 0) << 6; | |
14099 | inst.instruction |= immbits << 16; | |
14100 | inst.instruction |= (size >> 3) << 7; | |
14101 | inst.instruction |= (size & 0x7) << 19; | |
14102 | if (write_ubit) | |
14103 | inst.instruction |= (uval != 0) << 24; | |
14104 | ||
88714cb8 | 14105 | neon_dp_fixup (&inst); |
5287ad62 JB |
14106 | } |
14107 | ||
14108 | static void | |
14109 | do_neon_shl_imm (void) | |
14110 | { | |
14111 | if (!inst.operands[2].isreg) | |
14112 | { | |
037e8744 | 14113 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 14114 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); |
cb3b1e65 JB |
14115 | int imm = inst.operands[2].imm; |
14116 | ||
14117 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
14118 | _("immediate out of range for shift")); | |
88714cb8 | 14119 | NEON_ENCODE (IMMED, inst); |
cb3b1e65 | 14120 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
14121 | } |
14122 | else | |
14123 | { | |
037e8744 | 14124 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14125 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14126 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); |
627907b7 JB |
14127 | unsigned int tmp; |
14128 | ||
14129 | /* VSHL/VQSHL 3-register variants have syntax such as: | |
477330fc RM |
14130 | vshl.xx Dd, Dm, Dn |
14131 | whereas other 3-register operations encoded by neon_three_same have | |
14132 | syntax like: | |
14133 | vadd.xx Dd, Dn, Dm | |
14134 | (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg | |
14135 | here. */ | |
627907b7 JB |
14136 | tmp = inst.operands[2].reg; |
14137 | inst.operands[2].reg = inst.operands[1].reg; | |
14138 | inst.operands[1].reg = tmp; | |
88714cb8 | 14139 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14140 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14141 | } |
14142 | } | |
14143 | ||
14144 | static void | |
14145 | do_neon_qshl_imm (void) | |
14146 | { | |
14147 | if (!inst.operands[2].isreg) | |
14148 | { | |
037e8744 | 14149 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 14150 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
cb3b1e65 | 14151 | int imm = inst.operands[2].imm; |
627907b7 | 14152 | |
cb3b1e65 JB |
14153 | constraint (imm < 0 || (unsigned)imm >= et.size, |
14154 | _("immediate out of range for shift")); | |
88714cb8 | 14155 | NEON_ENCODE (IMMED, inst); |
cb3b1e65 | 14156 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm); |
5287ad62 JB |
14157 | } |
14158 | else | |
14159 | { | |
037e8744 | 14160 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14161 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14162 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); |
627907b7 JB |
14163 | unsigned int tmp; |
14164 | ||
14165 | /* See note in do_neon_shl_imm. */ | |
14166 | tmp = inst.operands[2].reg; | |
14167 | inst.operands[2].reg = inst.operands[1].reg; | |
14168 | inst.operands[1].reg = tmp; | |
88714cb8 | 14169 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14170 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14171 | } |
14172 | } | |
14173 | ||
627907b7 JB |
14174 | static void |
14175 | do_neon_rshl (void) | |
14176 | { | |
14177 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
14178 | struct neon_type_el et = neon_check_type (3, rs, | |
14179 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
14180 | unsigned int tmp; | |
14181 | ||
14182 | tmp = inst.operands[2].reg; | |
14183 | inst.operands[2].reg = inst.operands[1].reg; | |
14184 | inst.operands[1].reg = tmp; | |
14185 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
14186 | } | |
14187 | ||
5287ad62 JB |
14188 | static int |
14189 | neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) | |
14190 | { | |
036dc3f7 PB |
14191 | /* Handle .I8 pseudo-instructions. */ |
14192 | if (size == 8) | |
5287ad62 | 14193 | { |
5287ad62 | 14194 | /* Unfortunately, this will make everything apart from zero out-of-range. |
477330fc RM |
14195 | FIXME is this the intended semantics? There doesn't seem much point in |
14196 | accepting .I8 if so. */ | |
5287ad62 JB |
14197 | immediate |= immediate << 8; |
14198 | size = 16; | |
036dc3f7 PB |
14199 | } |
14200 | ||
14201 | if (size >= 32) | |
14202 | { | |
14203 | if (immediate == (immediate & 0x000000ff)) | |
14204 | { | |
14205 | *immbits = immediate; | |
14206 | return 0x1; | |
14207 | } | |
14208 | else if (immediate == (immediate & 0x0000ff00)) | |
14209 | { | |
14210 | *immbits = immediate >> 8; | |
14211 | return 0x3; | |
14212 | } | |
14213 | else if (immediate == (immediate & 0x00ff0000)) | |
14214 | { | |
14215 | *immbits = immediate >> 16; | |
14216 | return 0x5; | |
14217 | } | |
14218 | else if (immediate == (immediate & 0xff000000)) | |
14219 | { | |
14220 | *immbits = immediate >> 24; | |
14221 | return 0x7; | |
14222 | } | |
14223 | if ((immediate & 0xffff) != (immediate >> 16)) | |
14224 | goto bad_immediate; | |
14225 | immediate &= 0xffff; | |
5287ad62 JB |
14226 | } |
14227 | ||
14228 | if (immediate == (immediate & 0x000000ff)) | |
14229 | { | |
14230 | *immbits = immediate; | |
036dc3f7 | 14231 | return 0x9; |
5287ad62 JB |
14232 | } |
14233 | else if (immediate == (immediate & 0x0000ff00)) | |
14234 | { | |
14235 | *immbits = immediate >> 8; | |
036dc3f7 | 14236 | return 0xb; |
5287ad62 JB |
14237 | } |
14238 | ||
14239 | bad_immediate: | |
dcbf9037 | 14240 | first_error (_("immediate value out of range")); |
5287ad62 JB |
14241 | return FAIL; |
14242 | } | |
14243 | ||
5287ad62 JB |
14244 | static void |
14245 | do_neon_logic (void) | |
14246 | { | |
14247 | if (inst.operands[2].present && inst.operands[2].isreg) | |
14248 | { | |
037e8744 | 14249 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14250 | neon_check_type (3, rs, N_IGNORE_TYPE); |
14251 | /* U bit and size field were set as part of the bitmask. */ | |
88714cb8 | 14252 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14253 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14254 | } |
14255 | else | |
14256 | { | |
4316f0d2 DG |
14257 | const int three_ops_form = (inst.operands[2].present |
14258 | && !inst.operands[2].isreg); | |
14259 | const int immoperand = (three_ops_form ? 2 : 1); | |
14260 | enum neon_shape rs = (three_ops_form | |
14261 | ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL) | |
14262 | : neon_select_shape (NS_DI, NS_QI, NS_NULL)); | |
037e8744 | 14263 | struct neon_type_el et = neon_check_type (2, rs, |
477330fc | 14264 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); |
21d799b5 | 14265 | enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff; |
5287ad62 JB |
14266 | unsigned immbits; |
14267 | int cmode; | |
5f4273c7 | 14268 | |
5287ad62 | 14269 | if (et.type == NT_invtype) |
477330fc | 14270 | return; |
5f4273c7 | 14271 | |
4316f0d2 DG |
14272 | if (three_ops_form) |
14273 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
14274 | _("first and second operands shall be the same register")); | |
14275 | ||
88714cb8 | 14276 | NEON_ENCODE (IMMED, inst); |
5287ad62 | 14277 | |
4316f0d2 | 14278 | immbits = inst.operands[immoperand].imm; |
036dc3f7 PB |
14279 | if (et.size == 64) |
14280 | { | |
14281 | /* .i64 is a pseudo-op, so the immediate must be a repeating | |
14282 | pattern. */ | |
4316f0d2 DG |
14283 | if (immbits != (inst.operands[immoperand].regisimm ? |
14284 | inst.operands[immoperand].reg : 0)) | |
036dc3f7 PB |
14285 | { |
14286 | /* Set immbits to an invalid constant. */ | |
14287 | immbits = 0xdeadbeef; | |
14288 | } | |
14289 | } | |
14290 | ||
5287ad62 | 14291 | switch (opcode) |
477330fc RM |
14292 | { |
14293 | case N_MNEM_vbic: | |
14294 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14295 | break; | |
14296 | ||
14297 | case N_MNEM_vorr: | |
14298 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14299 | break; | |
14300 | ||
14301 | case N_MNEM_vand: | |
14302 | /* Pseudo-instruction for VBIC. */ | |
14303 | neon_invert_size (&immbits, 0, et.size); | |
14304 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14305 | break; | |
14306 | ||
14307 | case N_MNEM_vorn: | |
14308 | /* Pseudo-instruction for VORR. */ | |
14309 | neon_invert_size (&immbits, 0, et.size); | |
14310 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14311 | break; | |
14312 | ||
14313 | default: | |
14314 | abort (); | |
14315 | } | |
5287ad62 JB |
14316 | |
14317 | if (cmode == FAIL) | |
477330fc | 14318 | return; |
5287ad62 | 14319 | |
037e8744 | 14320 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14321 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14322 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14323 | inst.instruction |= cmode << 8; | |
14324 | neon_write_immbits (immbits); | |
5f4273c7 | 14325 | |
88714cb8 | 14326 | neon_dp_fixup (&inst); |
5287ad62 JB |
14327 | } |
14328 | } | |
14329 | ||
14330 | static void | |
14331 | do_neon_bitfield (void) | |
14332 | { | |
037e8744 | 14333 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 14334 | neon_check_type (3, rs, N_IGNORE_TYPE); |
037e8744 | 14335 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14336 | } |
14337 | ||
14338 | static void | |
dcbf9037 | 14339 | neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, |
477330fc | 14340 | unsigned destbits) |
5287ad62 | 14341 | { |
037e8744 | 14342 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 14343 | struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, |
477330fc | 14344 | types | N_KEY); |
5287ad62 JB |
14345 | if (et.type == NT_float) |
14346 | { | |
88714cb8 | 14347 | NEON_ENCODE (FLOAT, inst); |
037e8744 | 14348 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14349 | } |
14350 | else | |
14351 | { | |
88714cb8 | 14352 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14353 | neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); |
5287ad62 JB |
14354 | } |
14355 | } | |
14356 | ||
14357 | static void | |
14358 | do_neon_dyadic_if_su (void) | |
14359 | { | |
dcbf9037 | 14360 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
14361 | } |
14362 | ||
14363 | static void | |
14364 | do_neon_dyadic_if_su_d (void) | |
14365 | { | |
14366 | /* This version only allow D registers, but that constraint is enforced during | |
14367 | operand parsing so we don't need to do anything extra here. */ | |
dcbf9037 | 14368 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
14369 | } |
14370 | ||
5287ad62 JB |
14371 | static void |
14372 | do_neon_dyadic_if_i_d (void) | |
14373 | { | |
428e3f1f PB |
14374 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
14375 | affected if we specify unsigned args. */ | |
14376 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
5287ad62 JB |
14377 | } |
14378 | ||
037e8744 JB |
14379 | enum vfp_or_neon_is_neon_bits |
14380 | { | |
14381 | NEON_CHECK_CC = 1, | |
73924fbc MGD |
14382 | NEON_CHECK_ARCH = 2, |
14383 | NEON_CHECK_ARCH8 = 4 | |
037e8744 JB |
14384 | }; |
14385 | ||
14386 | /* Call this function if an instruction which may have belonged to the VFP or | |
14387 | Neon instruction sets, but turned out to be a Neon instruction (due to the | |
14388 | operand types involved, etc.). We have to check and/or fix-up a couple of | |
14389 | things: | |
14390 | ||
14391 | - Make sure the user hasn't attempted to make a Neon instruction | |
14392 | conditional. | |
14393 | - Alter the value in the condition code field if necessary. | |
14394 | - Make sure that the arch supports Neon instructions. | |
14395 | ||
14396 | Which of these operations take place depends on bits from enum | |
14397 | vfp_or_neon_is_neon_bits. | |
14398 | ||
14399 | WARNING: This function has side effects! If NEON_CHECK_CC is used and the | |
14400 | current instruction's condition is COND_ALWAYS, the condition field is | |
14401 | changed to inst.uncond_value. This is necessary because instructions shared | |
14402 | between VFP and Neon may be conditional for the VFP variants only, and the | |
14403 | unconditional Neon version must have, e.g., 0xF in the condition field. */ | |
14404 | ||
14405 | static int | |
14406 | vfp_or_neon_is_neon (unsigned check) | |
14407 | { | |
14408 | /* Conditions are always legal in Thumb mode (IT blocks). */ | |
14409 | if (!thumb_mode && (check & NEON_CHECK_CC)) | |
14410 | { | |
14411 | if (inst.cond != COND_ALWAYS) | |
477330fc RM |
14412 | { |
14413 | first_error (_(BAD_COND)); | |
14414 | return FAIL; | |
14415 | } | |
037e8744 | 14416 | if (inst.uncond_value != -1) |
477330fc | 14417 | inst.instruction |= inst.uncond_value << 28; |
037e8744 | 14418 | } |
5f4273c7 | 14419 | |
037e8744 | 14420 | if ((check & NEON_CHECK_ARCH) |
73924fbc MGD |
14421 | && !mark_feature_used (&fpu_neon_ext_v1)) |
14422 | { | |
14423 | first_error (_(BAD_FPU)); | |
14424 | return FAIL; | |
14425 | } | |
14426 | ||
14427 | if ((check & NEON_CHECK_ARCH8) | |
14428 | && !mark_feature_used (&fpu_neon_ext_armv8)) | |
037e8744 JB |
14429 | { |
14430 | first_error (_(BAD_FPU)); | |
14431 | return FAIL; | |
14432 | } | |
5f4273c7 | 14433 | |
037e8744 JB |
14434 | return SUCCESS; |
14435 | } | |
14436 | ||
5287ad62 JB |
14437 | static void |
14438 | do_neon_addsub_if_i (void) | |
14439 | { | |
037e8744 JB |
14440 | if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) |
14441 | return; | |
14442 | ||
14443 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14444 | return; | |
14445 | ||
5287ad62 JB |
14446 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
14447 | affected if we specify unsigned args. */ | |
dcbf9037 | 14448 | neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); |
5287ad62 JB |
14449 | } |
14450 | ||
14451 | /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the | |
14452 | result to be: | |
14453 | V<op> A,B (A is operand 0, B is operand 2) | |
14454 | to mean: | |
14455 | V<op> A,B,A | |
14456 | not: | |
14457 | V<op> A,B,B | |
14458 | so handle that case specially. */ | |
14459 | ||
14460 | static void | |
14461 | neon_exchange_operands (void) | |
14462 | { | |
14463 | void *scratch = alloca (sizeof (inst.operands[0])); | |
14464 | if (inst.operands[1].present) | |
14465 | { | |
14466 | /* Swap operands[1] and operands[2]. */ | |
14467 | memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); | |
14468 | inst.operands[1] = inst.operands[2]; | |
14469 | memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); | |
14470 | } | |
14471 | else | |
14472 | { | |
14473 | inst.operands[1] = inst.operands[2]; | |
14474 | inst.operands[2] = inst.operands[0]; | |
14475 | } | |
14476 | } | |
14477 | ||
14478 | static void | |
14479 | neon_compare (unsigned regtypes, unsigned immtypes, int invert) | |
14480 | { | |
14481 | if (inst.operands[2].isreg) | |
14482 | { | |
14483 | if (invert) | |
477330fc | 14484 | neon_exchange_operands (); |
dcbf9037 | 14485 | neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); |
5287ad62 JB |
14486 | } |
14487 | else | |
14488 | { | |
037e8744 | 14489 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
dcbf9037 | 14490 | struct neon_type_el et = neon_check_type (2, rs, |
477330fc | 14491 | N_EQK | N_SIZ, immtypes | N_KEY); |
5287ad62 | 14492 | |
88714cb8 | 14493 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14494 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14495 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14496 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14497 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14498 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14499 | inst.instruction |= (et.type == NT_float) << 10; |
14500 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14501 | |
88714cb8 | 14502 | neon_dp_fixup (&inst); |
5287ad62 JB |
14503 | } |
14504 | } | |
14505 | ||
14506 | static void | |
14507 | do_neon_cmp (void) | |
14508 | { | |
14509 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); | |
14510 | } | |
14511 | ||
14512 | static void | |
14513 | do_neon_cmp_inv (void) | |
14514 | { | |
14515 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); | |
14516 | } | |
14517 | ||
14518 | static void | |
14519 | do_neon_ceq (void) | |
14520 | { | |
14521 | neon_compare (N_IF_32, N_IF_32, FALSE); | |
14522 | } | |
14523 | ||
14524 | /* For multiply instructions, we have the possibility of 16-bit or 32-bit | |
14525 | scalars, which are encoded in 5 bits, M : Rm. | |
14526 | For 16-bit scalars, the register is encoded in Rm[2:0] and the index in | |
14527 | M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the | |
14528 | index in M. */ | |
14529 | ||
14530 | static unsigned | |
14531 | neon_scalar_for_mul (unsigned scalar, unsigned elsize) | |
14532 | { | |
dcbf9037 JB |
14533 | unsigned regno = NEON_SCALAR_REG (scalar); |
14534 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
5287ad62 JB |
14535 | |
14536 | switch (elsize) | |
14537 | { | |
14538 | case 16: | |
14539 | if (regno > 7 || elno > 3) | |
477330fc | 14540 | goto bad_scalar; |
5287ad62 | 14541 | return regno | (elno << 3); |
5f4273c7 | 14542 | |
5287ad62 JB |
14543 | case 32: |
14544 | if (regno > 15 || elno > 1) | |
477330fc | 14545 | goto bad_scalar; |
5287ad62 JB |
14546 | return regno | (elno << 4); |
14547 | ||
14548 | default: | |
14549 | bad_scalar: | |
dcbf9037 | 14550 | first_error (_("scalar out of range for multiply instruction")); |
5287ad62 JB |
14551 | } |
14552 | ||
14553 | return 0; | |
14554 | } | |
14555 | ||
14556 | /* Encode multiply / multiply-accumulate scalar instructions. */ | |
14557 | ||
14558 | static void | |
14559 | neon_mul_mac (struct neon_type_el et, int ubit) | |
14560 | { | |
dcbf9037 JB |
14561 | unsigned scalar; |
14562 | ||
14563 | /* Give a more helpful error message if we have an invalid type. */ | |
14564 | if (et.type == NT_invtype) | |
14565 | return; | |
5f4273c7 | 14566 | |
dcbf9037 | 14567 | scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); |
5287ad62 JB |
14568 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14569 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14570 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14571 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14572 | inst.instruction |= LOW4 (scalar); | |
14573 | inst.instruction |= HI1 (scalar) << 5; | |
14574 | inst.instruction |= (et.type == NT_float) << 8; | |
14575 | inst.instruction |= neon_logbits (et.size) << 20; | |
14576 | inst.instruction |= (ubit != 0) << 24; | |
14577 | ||
88714cb8 | 14578 | neon_dp_fixup (&inst); |
5287ad62 JB |
14579 | } |
14580 | ||
14581 | static void | |
14582 | do_neon_mac_maybe_scalar (void) | |
14583 | { | |
037e8744 JB |
14584 | if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) |
14585 | return; | |
14586 | ||
14587 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14588 | return; | |
14589 | ||
5287ad62 JB |
14590 | if (inst.operands[2].isscalar) |
14591 | { | |
037e8744 | 14592 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 | 14593 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14594 | N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); |
88714cb8 | 14595 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 14596 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
14597 | } |
14598 | else | |
428e3f1f PB |
14599 | { |
14600 | /* The "untyped" case can't happen. Do this to stop the "U" bit being | |
14601 | affected if we specify unsigned args. */ | |
14602 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
14603 | } | |
5287ad62 JB |
14604 | } |
14605 | ||
62f3b8c8 PB |
14606 | static void |
14607 | do_neon_fmac (void) | |
14608 | { | |
14609 | if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS) | |
14610 | return; | |
14611 | ||
14612 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14613 | return; | |
14614 | ||
14615 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
14616 | } | |
14617 | ||
5287ad62 JB |
14618 | static void |
14619 | do_neon_tst (void) | |
14620 | { | |
037e8744 | 14621 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14622 | struct neon_type_el et = neon_check_type (3, rs, |
14623 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
037e8744 | 14624 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
14625 | } |
14626 | ||
14627 | /* VMUL with 3 registers allows the P8 type. The scalar version supports the | |
14628 | same types as the MAC equivalents. The polynomial type for this instruction | |
14629 | is encoded the same as the integer type. */ | |
14630 | ||
14631 | static void | |
14632 | do_neon_mul (void) | |
14633 | { | |
037e8744 JB |
14634 | if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) |
14635 | return; | |
14636 | ||
14637 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14638 | return; | |
14639 | ||
5287ad62 JB |
14640 | if (inst.operands[2].isscalar) |
14641 | do_neon_mac_maybe_scalar (); | |
14642 | else | |
dcbf9037 | 14643 | neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); |
5287ad62 JB |
14644 | } |
14645 | ||
14646 | static void | |
14647 | do_neon_qdmulh (void) | |
14648 | { | |
14649 | if (inst.operands[2].isscalar) | |
14650 | { | |
037e8744 | 14651 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 | 14652 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14653 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); |
88714cb8 | 14654 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 14655 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
14656 | } |
14657 | else | |
14658 | { | |
037e8744 | 14659 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14660 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14661 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); |
88714cb8 | 14662 | NEON_ENCODE (INTEGER, inst); |
5287ad62 | 14663 | /* The U bit (rounding) comes from bit mask. */ |
037e8744 | 14664 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
14665 | } |
14666 | } | |
14667 | ||
14668 | static void | |
14669 | do_neon_fcmp_absolute (void) | |
14670 | { | |
037e8744 | 14671 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14672 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
14673 | /* Size field comes from bit mask. */ | |
037e8744 | 14674 | neon_three_same (neon_quad (rs), 1, -1); |
5287ad62 JB |
14675 | } |
14676 | ||
14677 | static void | |
14678 | do_neon_fcmp_absolute_inv (void) | |
14679 | { | |
14680 | neon_exchange_operands (); | |
14681 | do_neon_fcmp_absolute (); | |
14682 | } | |
14683 | ||
14684 | static void | |
14685 | do_neon_step (void) | |
14686 | { | |
037e8744 | 14687 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14688 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
037e8744 | 14689 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14690 | } |
14691 | ||
14692 | static void | |
14693 | do_neon_abs_neg (void) | |
14694 | { | |
037e8744 JB |
14695 | enum neon_shape rs; |
14696 | struct neon_type_el et; | |
5f4273c7 | 14697 | |
037e8744 JB |
14698 | if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) |
14699 | return; | |
14700 | ||
14701 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14702 | return; | |
14703 | ||
14704 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
14705 | et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); | |
5f4273c7 | 14706 | |
5287ad62 JB |
14707 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14708 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14709 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14710 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14711 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14712 | inst.instruction |= (et.type == NT_float) << 10; |
14713 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14714 | |
88714cb8 | 14715 | neon_dp_fixup (&inst); |
5287ad62 JB |
14716 | } |
14717 | ||
14718 | static void | |
14719 | do_neon_sli (void) | |
14720 | { | |
037e8744 | 14721 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14722 | struct neon_type_el et = neon_check_type (2, rs, |
14723 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14724 | int imm = inst.operands[2].imm; | |
14725 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
477330fc | 14726 | _("immediate out of range for insert")); |
037e8744 | 14727 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
14728 | } |
14729 | ||
14730 | static void | |
14731 | do_neon_sri (void) | |
14732 | { | |
037e8744 | 14733 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14734 | struct neon_type_el et = neon_check_type (2, rs, |
14735 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14736 | int imm = inst.operands[2].imm; | |
14737 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 14738 | _("immediate out of range for insert")); |
037e8744 | 14739 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); |
5287ad62 JB |
14740 | } |
14741 | ||
14742 | static void | |
14743 | do_neon_qshlu_imm (void) | |
14744 | { | |
037e8744 | 14745 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14746 | struct neon_type_el et = neon_check_type (2, rs, |
14747 | N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); | |
14748 | int imm = inst.operands[2].imm; | |
14749 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
477330fc | 14750 | _("immediate out of range for shift")); |
5287ad62 JB |
14751 | /* Only encodes the 'U present' variant of the instruction. |
14752 | In this case, signed types have OP (bit 8) set to 0. | |
14753 | Unsigned types have OP set to 1. */ | |
14754 | inst.instruction |= (et.type == NT_unsigned) << 8; | |
14755 | /* The rest of the bits are the same as other immediate shifts. */ | |
037e8744 | 14756 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
14757 | } |
14758 | ||
14759 | static void | |
14760 | do_neon_qmovn (void) | |
14761 | { | |
14762 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14763 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
14764 | /* Saturating move where operands can be signed or unsigned, and the | |
14765 | destination has the same signedness. */ | |
88714cb8 | 14766 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14767 | if (et.type == NT_unsigned) |
14768 | inst.instruction |= 0xc0; | |
14769 | else | |
14770 | inst.instruction |= 0x80; | |
14771 | neon_two_same (0, 1, et.size / 2); | |
14772 | } | |
14773 | ||
14774 | static void | |
14775 | do_neon_qmovun (void) | |
14776 | { | |
14777 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14778 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
14779 | /* Saturating move with unsigned results. Operands must be signed. */ | |
88714cb8 | 14780 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14781 | neon_two_same (0, 1, et.size / 2); |
14782 | } | |
14783 | ||
14784 | static void | |
14785 | do_neon_rshift_sat_narrow (void) | |
14786 | { | |
14787 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
14788 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
14789 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14790 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
14791 | int imm = inst.operands[2].imm; | |
14792 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14793 | right. */ | |
14794 | et.size /= 2; | |
5f4273c7 | 14795 | |
5287ad62 JB |
14796 | /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for |
14797 | VQMOVN.I<size> <Dd>, <Qm>. */ | |
14798 | if (imm == 0) | |
14799 | { | |
14800 | inst.operands[2].present = 0; | |
14801 | inst.instruction = N_MNEM_vqmovn; | |
14802 | do_neon_qmovn (); | |
14803 | return; | |
14804 | } | |
5f4273c7 | 14805 | |
5287ad62 | 14806 | constraint (imm < 1 || (unsigned)imm > et.size, |
477330fc | 14807 | _("immediate out of range")); |
5287ad62 JB |
14808 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); |
14809 | } | |
14810 | ||
14811 | static void | |
14812 | do_neon_rshift_sat_narrow_u (void) | |
14813 | { | |
14814 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
14815 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
14816 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14817 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
14818 | int imm = inst.operands[2].imm; | |
14819 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14820 | right. */ | |
14821 | et.size /= 2; | |
14822 | ||
14823 | /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for | |
14824 | VQMOVUN.I<size> <Dd>, <Qm>. */ | |
14825 | if (imm == 0) | |
14826 | { | |
14827 | inst.operands[2].present = 0; | |
14828 | inst.instruction = N_MNEM_vqmovun; | |
14829 | do_neon_qmovun (); | |
14830 | return; | |
14831 | } | |
14832 | ||
14833 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 14834 | _("immediate out of range")); |
5287ad62 JB |
14835 | /* FIXME: The manual is kind of unclear about what value U should have in |
14836 | VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it | |
14837 | must be 1. */ | |
14838 | neon_imm_shift (TRUE, 1, 0, et, et.size - imm); | |
14839 | } | |
14840 | ||
14841 | static void | |
14842 | do_neon_movn (void) | |
14843 | { | |
14844 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14845 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
88714cb8 | 14846 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14847 | neon_two_same (0, 1, et.size / 2); |
14848 | } | |
14849 | ||
14850 | static void | |
14851 | do_neon_rshift_narrow (void) | |
14852 | { | |
14853 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14854 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
14855 | int imm = inst.operands[2].imm; | |
14856 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14857 | right. */ | |
14858 | et.size /= 2; | |
5f4273c7 | 14859 | |
5287ad62 JB |
14860 | /* If immediate is zero then we are a pseudo-instruction for |
14861 | VMOVN.I<size> <Dd>, <Qm> */ | |
14862 | if (imm == 0) | |
14863 | { | |
14864 | inst.operands[2].present = 0; | |
14865 | inst.instruction = N_MNEM_vmovn; | |
14866 | do_neon_movn (); | |
14867 | return; | |
14868 | } | |
5f4273c7 | 14869 | |
5287ad62 | 14870 | constraint (imm < 1 || (unsigned)imm > et.size, |
477330fc | 14871 | _("immediate out of range for narrowing operation")); |
5287ad62 JB |
14872 | neon_imm_shift (FALSE, 0, 0, et, et.size - imm); |
14873 | } | |
14874 | ||
14875 | static void | |
14876 | do_neon_shll (void) | |
14877 | { | |
14878 | /* FIXME: Type checking when lengthening. */ | |
14879 | struct neon_type_el et = neon_check_type (2, NS_QDI, | |
14880 | N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); | |
14881 | unsigned imm = inst.operands[2].imm; | |
14882 | ||
14883 | if (imm == et.size) | |
14884 | { | |
14885 | /* Maximum shift variant. */ | |
88714cb8 | 14886 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14887 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14888 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14889 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14890 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14891 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14892 | |
88714cb8 | 14893 | neon_dp_fixup (&inst); |
5287ad62 JB |
14894 | } |
14895 | else | |
14896 | { | |
14897 | /* A more-specific type check for non-max versions. */ | |
14898 | et = neon_check_type (2, NS_QDI, | |
477330fc | 14899 | N_EQK | N_DBL, N_SU_32 | N_KEY); |
88714cb8 | 14900 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14901 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); |
14902 | } | |
14903 | } | |
14904 | ||
037e8744 | 14905 | /* Check the various types for the VCVT instruction, and return which version |
5287ad62 JB |
14906 | the current instruction is. */ |
14907 | ||
6b9a8b67 MGD |
14908 | #define CVT_FLAVOUR_VAR \ |
14909 | CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \ | |
14910 | CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \ | |
14911 | CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \ | |
14912 | CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \ | |
14913 | /* Half-precision conversions. */ \ | |
14914 | CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \ | |
14915 | CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \ | |
14916 | /* VFP instructions. */ \ | |
14917 | CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \ | |
14918 | CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \ | |
14919 | CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \ | |
14920 | CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \ | |
14921 | CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \ | |
14922 | CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \ | |
14923 | /* VFP instructions with bitshift. */ \ | |
14924 | CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \ | |
14925 | CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \ | |
14926 | CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \ | |
14927 | CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \ | |
14928 | CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \ | |
14929 | CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \ | |
14930 | CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \ | |
14931 | CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL) | |
14932 | ||
14933 | #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \ | |
14934 | neon_cvt_flavour_##C, | |
14935 | ||
14936 | /* The different types of conversions we can do. */ | |
14937 | enum neon_cvt_flavour | |
14938 | { | |
14939 | CVT_FLAVOUR_VAR | |
14940 | neon_cvt_flavour_invalid, | |
14941 | neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64 | |
14942 | }; | |
14943 | ||
14944 | #undef CVT_VAR | |
14945 | ||
14946 | static enum neon_cvt_flavour | |
14947 | get_neon_cvt_flavour (enum neon_shape rs) | |
5287ad62 | 14948 | { |
6b9a8b67 MGD |
14949 | #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \ |
14950 | et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \ | |
14951 | if (et.type != NT_invtype) \ | |
14952 | { \ | |
14953 | inst.error = NULL; \ | |
14954 | return (neon_cvt_flavour_##C); \ | |
5287ad62 | 14955 | } |
6b9a8b67 | 14956 | |
5287ad62 | 14957 | struct neon_type_el et; |
037e8744 | 14958 | unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF |
477330fc | 14959 | || rs == NS_FF) ? N_VFP : 0; |
037e8744 JB |
14960 | /* The instruction versions which take an immediate take one register |
14961 | argument, which is extended to the width of the full register. Thus the | |
14962 | "source" and "destination" registers must have the same width. Hack that | |
14963 | here by making the size equal to the key (wider, in this case) operand. */ | |
14964 | unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; | |
5f4273c7 | 14965 | |
6b9a8b67 MGD |
14966 | CVT_FLAVOUR_VAR; |
14967 | ||
14968 | return neon_cvt_flavour_invalid; | |
5287ad62 JB |
14969 | #undef CVT_VAR |
14970 | } | |
14971 | ||
7e8e6784 MGD |
14972 | enum neon_cvt_mode |
14973 | { | |
14974 | neon_cvt_mode_a, | |
14975 | neon_cvt_mode_n, | |
14976 | neon_cvt_mode_p, | |
14977 | neon_cvt_mode_m, | |
14978 | neon_cvt_mode_z, | |
30bdf752 MGD |
14979 | neon_cvt_mode_x, |
14980 | neon_cvt_mode_r | |
7e8e6784 MGD |
14981 | }; |
14982 | ||
037e8744 JB |
14983 | /* Neon-syntax VFP conversions. */ |
14984 | ||
5287ad62 | 14985 | static void |
6b9a8b67 | 14986 | do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour) |
5287ad62 | 14987 | { |
037e8744 | 14988 | const char *opname = 0; |
5f4273c7 | 14989 | |
037e8744 | 14990 | if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) |
5287ad62 | 14991 | { |
037e8744 JB |
14992 | /* Conversions with immediate bitshift. */ |
14993 | const char *enc[] = | |
477330fc | 14994 | { |
6b9a8b67 MGD |
14995 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN, |
14996 | CVT_FLAVOUR_VAR | |
14997 | NULL | |
14998 | #undef CVT_VAR | |
477330fc | 14999 | }; |
037e8744 | 15000 | |
6b9a8b67 | 15001 | if (flavour < (int) ARRAY_SIZE (enc)) |
477330fc RM |
15002 | { |
15003 | opname = enc[flavour]; | |
15004 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
15005 | _("operands 0 and 1 must be the same register")); | |
15006 | inst.operands[1] = inst.operands[2]; | |
15007 | memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); | |
15008 | } | |
5287ad62 JB |
15009 | } |
15010 | else | |
15011 | { | |
037e8744 JB |
15012 | /* Conversions without bitshift. */ |
15013 | const char *enc[] = | |
477330fc | 15014 | { |
6b9a8b67 MGD |
15015 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN, |
15016 | CVT_FLAVOUR_VAR | |
15017 | NULL | |
15018 | #undef CVT_VAR | |
477330fc | 15019 | }; |
037e8744 | 15020 | |
6b9a8b67 | 15021 | if (flavour < (int) ARRAY_SIZE (enc)) |
477330fc | 15022 | opname = enc[flavour]; |
037e8744 JB |
15023 | } |
15024 | ||
15025 | if (opname) | |
15026 | do_vfp_nsyn_opcode (opname); | |
15027 | } | |
15028 | ||
15029 | static void | |
15030 | do_vfp_nsyn_cvtz (void) | |
15031 | { | |
15032 | enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); | |
6b9a8b67 | 15033 | enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs); |
037e8744 JB |
15034 | const char *enc[] = |
15035 | { | |
6b9a8b67 MGD |
15036 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN, |
15037 | CVT_FLAVOUR_VAR | |
15038 | NULL | |
15039 | #undef CVT_VAR | |
037e8744 JB |
15040 | }; |
15041 | ||
6b9a8b67 | 15042 | if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) |
037e8744 JB |
15043 | do_vfp_nsyn_opcode (enc[flavour]); |
15044 | } | |
f31fef98 | 15045 | |
037e8744 | 15046 | static void |
bacebabc | 15047 | do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour, |
7e8e6784 MGD |
15048 | enum neon_cvt_mode mode) |
15049 | { | |
15050 | int sz, op; | |
15051 | int rm; | |
15052 | ||
a715796b TG |
15053 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
15054 | D register operands. */ | |
15055 | if (flavour == neon_cvt_flavour_s32_f64 | |
15056 | || flavour == neon_cvt_flavour_u32_f64) | |
15057 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
15058 | _(BAD_FPU)); | |
15059 | ||
7e8e6784 MGD |
15060 | set_it_insn_type (OUTSIDE_IT_INSN); |
15061 | ||
15062 | switch (flavour) | |
15063 | { | |
15064 | case neon_cvt_flavour_s32_f64: | |
15065 | sz = 1; | |
827f64ff | 15066 | op = 1; |
7e8e6784 MGD |
15067 | break; |
15068 | case neon_cvt_flavour_s32_f32: | |
15069 | sz = 0; | |
15070 | op = 1; | |
15071 | break; | |
15072 | case neon_cvt_flavour_u32_f64: | |
15073 | sz = 1; | |
15074 | op = 0; | |
15075 | break; | |
15076 | case neon_cvt_flavour_u32_f32: | |
15077 | sz = 0; | |
15078 | op = 0; | |
15079 | break; | |
15080 | default: | |
15081 | first_error (_("invalid instruction shape")); | |
15082 | return; | |
15083 | } | |
15084 | ||
15085 | switch (mode) | |
15086 | { | |
15087 | case neon_cvt_mode_a: rm = 0; break; | |
15088 | case neon_cvt_mode_n: rm = 1; break; | |
15089 | case neon_cvt_mode_p: rm = 2; break; | |
15090 | case neon_cvt_mode_m: rm = 3; break; | |
15091 | default: first_error (_("invalid rounding mode")); return; | |
15092 | } | |
15093 | ||
15094 | NEON_ENCODE (FPV8, inst); | |
15095 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
15096 | encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm); | |
15097 | inst.instruction |= sz << 8; | |
15098 | inst.instruction |= op << 7; | |
15099 | inst.instruction |= rm << 16; | |
15100 | inst.instruction |= 0xf0000000; | |
15101 | inst.is_neon = TRUE; | |
15102 | } | |
15103 | ||
15104 | static void | |
15105 | do_neon_cvt_1 (enum neon_cvt_mode mode) | |
037e8744 JB |
15106 | { |
15107 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, | |
8e79c3df | 15108 | NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL); |
6b9a8b67 | 15109 | enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs); |
037e8744 | 15110 | |
e3e535bc | 15111 | /* PR11109: Handle round-to-zero for VCVT conversions. */ |
7e8e6784 | 15112 | if (mode == neon_cvt_mode_z |
e3e535bc | 15113 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2) |
bacebabc RM |
15114 | && (flavour == neon_cvt_flavour_s32_f32 |
15115 | || flavour == neon_cvt_flavour_u32_f32 | |
15116 | || flavour == neon_cvt_flavour_s32_f64 | |
6b9a8b67 | 15117 | || flavour == neon_cvt_flavour_u32_f64) |
e3e535bc NC |
15118 | && (rs == NS_FD || rs == NS_FF)) |
15119 | { | |
15120 | do_vfp_nsyn_cvtz (); | |
15121 | return; | |
15122 | } | |
15123 | ||
037e8744 | 15124 | /* VFP rather than Neon conversions. */ |
6b9a8b67 | 15125 | if (flavour >= neon_cvt_flavour_first_fp) |
037e8744 | 15126 | { |
7e8e6784 MGD |
15127 | if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z) |
15128 | do_vfp_nsyn_cvt (rs, flavour); | |
15129 | else | |
15130 | do_vfp_nsyn_cvt_fpv8 (flavour, mode); | |
15131 | ||
037e8744 JB |
15132 | return; |
15133 | } | |
15134 | ||
15135 | switch (rs) | |
15136 | { | |
15137 | case NS_DDI: | |
15138 | case NS_QQI: | |
15139 | { | |
477330fc RM |
15140 | unsigned immbits; |
15141 | unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; | |
35997600 | 15142 | |
477330fc RM |
15143 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
15144 | return; | |
037e8744 | 15145 | |
477330fc RM |
15146 | /* Fixed-point conversion with #0 immediate is encoded as an |
15147 | integer conversion. */ | |
15148 | if (inst.operands[2].present && inst.operands[2].imm == 0) | |
15149 | goto int_encode; | |
35997600 | 15150 | immbits = 32 - inst.operands[2].imm; |
477330fc RM |
15151 | NEON_ENCODE (IMMED, inst); |
15152 | if (flavour != neon_cvt_flavour_invalid) | |
15153 | inst.instruction |= enctab[flavour]; | |
15154 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15155 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15156 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15157 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15158 | inst.instruction |= neon_quad (rs) << 6; | |
15159 | inst.instruction |= 1 << 21; | |
15160 | inst.instruction |= immbits << 16; | |
15161 | ||
15162 | neon_dp_fixup (&inst); | |
037e8744 JB |
15163 | } |
15164 | break; | |
15165 | ||
15166 | case NS_DD: | |
15167 | case NS_QQ: | |
7e8e6784 MGD |
15168 | if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z) |
15169 | { | |
15170 | NEON_ENCODE (FLOAT, inst); | |
15171 | set_it_insn_type (OUTSIDE_IT_INSN); | |
15172 | ||
15173 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL) | |
15174 | return; | |
15175 | ||
15176 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15177 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15178 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15179 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15180 | inst.instruction |= neon_quad (rs) << 6; | |
15181 | inst.instruction |= (flavour == neon_cvt_flavour_u32_f32) << 7; | |
15182 | inst.instruction |= mode << 8; | |
15183 | if (thumb_mode) | |
15184 | inst.instruction |= 0xfc000000; | |
15185 | else | |
15186 | inst.instruction |= 0xf0000000; | |
15187 | } | |
15188 | else | |
15189 | { | |
037e8744 | 15190 | int_encode: |
7e8e6784 MGD |
15191 | { |
15192 | unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; | |
037e8744 | 15193 | |
7e8e6784 | 15194 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 15195 | |
7e8e6784 MGD |
15196 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
15197 | return; | |
037e8744 | 15198 | |
7e8e6784 MGD |
15199 | if (flavour != neon_cvt_flavour_invalid) |
15200 | inst.instruction |= enctab[flavour]; | |
037e8744 | 15201 | |
7e8e6784 MGD |
15202 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15203 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15204 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15205 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15206 | inst.instruction |= neon_quad (rs) << 6; | |
15207 | inst.instruction |= 2 << 18; | |
037e8744 | 15208 | |
7e8e6784 MGD |
15209 | neon_dp_fixup (&inst); |
15210 | } | |
15211 | } | |
15212 | break; | |
037e8744 | 15213 | |
8e79c3df CM |
15214 | /* Half-precision conversions for Advanced SIMD -- neon. */ |
15215 | case NS_QD: | |
15216 | case NS_DQ: | |
15217 | ||
15218 | if ((rs == NS_DQ) | |
15219 | && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) | |
15220 | { | |
15221 | as_bad (_("operand size must match register width")); | |
15222 | break; | |
15223 | } | |
15224 | ||
15225 | if ((rs == NS_QD) | |
15226 | && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) | |
15227 | { | |
15228 | as_bad (_("operand size must match register width")); | |
15229 | break; | |
15230 | } | |
15231 | ||
15232 | if (rs == NS_DQ) | |
477330fc | 15233 | inst.instruction = 0x3b60600; |
8e79c3df CM |
15234 | else |
15235 | inst.instruction = 0x3b60700; | |
15236 | ||
15237 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15238 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15239 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15240 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
88714cb8 | 15241 | neon_dp_fixup (&inst); |
8e79c3df CM |
15242 | break; |
15243 | ||
037e8744 JB |
15244 | default: |
15245 | /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ | |
7e8e6784 MGD |
15246 | if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z) |
15247 | do_vfp_nsyn_cvt (rs, flavour); | |
15248 | else | |
15249 | do_vfp_nsyn_cvt_fpv8 (flavour, mode); | |
5287ad62 | 15250 | } |
5287ad62 JB |
15251 | } |
15252 | ||
e3e535bc NC |
15253 | static void |
15254 | do_neon_cvtr (void) | |
15255 | { | |
7e8e6784 | 15256 | do_neon_cvt_1 (neon_cvt_mode_x); |
e3e535bc NC |
15257 | } |
15258 | ||
15259 | static void | |
15260 | do_neon_cvt (void) | |
15261 | { | |
7e8e6784 MGD |
15262 | do_neon_cvt_1 (neon_cvt_mode_z); |
15263 | } | |
15264 | ||
15265 | static void | |
15266 | do_neon_cvta (void) | |
15267 | { | |
15268 | do_neon_cvt_1 (neon_cvt_mode_a); | |
15269 | } | |
15270 | ||
15271 | static void | |
15272 | do_neon_cvtn (void) | |
15273 | { | |
15274 | do_neon_cvt_1 (neon_cvt_mode_n); | |
15275 | } | |
15276 | ||
15277 | static void | |
15278 | do_neon_cvtp (void) | |
15279 | { | |
15280 | do_neon_cvt_1 (neon_cvt_mode_p); | |
15281 | } | |
15282 | ||
15283 | static void | |
15284 | do_neon_cvtm (void) | |
15285 | { | |
15286 | do_neon_cvt_1 (neon_cvt_mode_m); | |
e3e535bc NC |
15287 | } |
15288 | ||
8e79c3df | 15289 | static void |
c70a8987 | 15290 | do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double) |
8e79c3df | 15291 | { |
c70a8987 MGD |
15292 | if (is_double) |
15293 | mark_feature_used (&fpu_vfp_ext_armv8); | |
8e79c3df | 15294 | |
c70a8987 MGD |
15295 | encode_arm_vfp_reg (inst.operands[0].reg, |
15296 | (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd); | |
15297 | encode_arm_vfp_reg (inst.operands[1].reg, | |
15298 | (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm); | |
15299 | inst.instruction |= to ? 0x10000 : 0; | |
15300 | inst.instruction |= t ? 0x80 : 0; | |
15301 | inst.instruction |= is_double ? 0x100 : 0; | |
15302 | do_vfp_cond_or_thumb (); | |
15303 | } | |
8e79c3df | 15304 | |
c70a8987 MGD |
15305 | static void |
15306 | do_neon_cvttb_1 (bfd_boolean t) | |
15307 | { | |
15308 | enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_DF, NS_NULL); | |
8e79c3df | 15309 | |
c70a8987 MGD |
15310 | if (rs == NS_NULL) |
15311 | return; | |
15312 | else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype) | |
15313 | { | |
15314 | inst.error = NULL; | |
15315 | do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE); | |
15316 | } | |
15317 | else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype) | |
15318 | { | |
15319 | inst.error = NULL; | |
15320 | do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE); | |
15321 | } | |
15322 | else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype) | |
15323 | { | |
a715796b TG |
15324 | /* The VCVTB and VCVTT instructions with D-register operands |
15325 | don't work for SP only targets. */ | |
15326 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
15327 | _(BAD_FPU)); | |
15328 | ||
c70a8987 MGD |
15329 | inst.error = NULL; |
15330 | do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE); | |
15331 | } | |
15332 | else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype) | |
15333 | { | |
a715796b TG |
15334 | /* The VCVTB and VCVTT instructions with D-register operands |
15335 | don't work for SP only targets. */ | |
15336 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
15337 | _(BAD_FPU)); | |
15338 | ||
c70a8987 MGD |
15339 | inst.error = NULL; |
15340 | do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE); | |
15341 | } | |
15342 | else | |
15343 | return; | |
15344 | } | |
15345 | ||
15346 | static void | |
15347 | do_neon_cvtb (void) | |
15348 | { | |
15349 | do_neon_cvttb_1 (FALSE); | |
8e79c3df CM |
15350 | } |
15351 | ||
15352 | ||
15353 | static void | |
15354 | do_neon_cvtt (void) | |
15355 | { | |
c70a8987 | 15356 | do_neon_cvttb_1 (TRUE); |
8e79c3df CM |
15357 | } |
15358 | ||
5287ad62 JB |
15359 | static void |
15360 | neon_move_immediate (void) | |
15361 | { | |
037e8744 JB |
15362 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
15363 | struct neon_type_el et = neon_check_type (2, rs, | |
15364 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
5287ad62 | 15365 | unsigned immlo, immhi = 0, immbits; |
c96612cc | 15366 | int op, cmode, float_p; |
5287ad62 | 15367 | |
037e8744 | 15368 | constraint (et.type == NT_invtype, |
477330fc | 15369 | _("operand size must be specified for immediate VMOV")); |
037e8744 | 15370 | |
5287ad62 JB |
15371 | /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ |
15372 | op = (inst.instruction & (1 << 5)) != 0; | |
15373 | ||
15374 | immlo = inst.operands[1].imm; | |
15375 | if (inst.operands[1].regisimm) | |
15376 | immhi = inst.operands[1].reg; | |
15377 | ||
15378 | constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, | |
477330fc | 15379 | _("immediate has bits set outside the operand size")); |
5287ad62 | 15380 | |
c96612cc JB |
15381 | float_p = inst.operands[1].immisfloat; |
15382 | ||
15383 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, | |
477330fc | 15384 | et.size, et.type)) == FAIL) |
5287ad62 JB |
15385 | { |
15386 | /* Invert relevant bits only. */ | |
15387 | neon_invert_size (&immlo, &immhi, et.size); | |
15388 | /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable | |
477330fc RM |
15389 | with one or the other; those cases are caught by |
15390 | neon_cmode_for_move_imm. */ | |
5287ad62 | 15391 | op = !op; |
c96612cc JB |
15392 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, |
15393 | &op, et.size, et.type)) == FAIL) | |
477330fc RM |
15394 | { |
15395 | first_error (_("immediate out of range")); | |
15396 | return; | |
15397 | } | |
5287ad62 JB |
15398 | } |
15399 | ||
15400 | inst.instruction &= ~(1 << 5); | |
15401 | inst.instruction |= op << 5; | |
15402 | ||
15403 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15404 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
037e8744 | 15405 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
15406 | inst.instruction |= cmode << 8; |
15407 | ||
15408 | neon_write_immbits (immbits); | |
15409 | } | |
15410 | ||
15411 | static void | |
15412 | do_neon_mvn (void) | |
15413 | { | |
15414 | if (inst.operands[1].isreg) | |
15415 | { | |
037e8744 | 15416 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5f4273c7 | 15417 | |
88714cb8 | 15418 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
15419 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15420 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15421 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15422 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 15423 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
15424 | } |
15425 | else | |
15426 | { | |
88714cb8 | 15427 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
15428 | neon_move_immediate (); |
15429 | } | |
15430 | ||
88714cb8 | 15431 | neon_dp_fixup (&inst); |
5287ad62 JB |
15432 | } |
15433 | ||
15434 | /* Encode instructions of form: | |
15435 | ||
15436 | |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
5f4273c7 | 15437 | | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */ |
5287ad62 JB |
15438 | |
15439 | static void | |
15440 | neon_mixed_length (struct neon_type_el et, unsigned size) | |
15441 | { | |
15442 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15443 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15444 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15445 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15446 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15447 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
15448 | inst.instruction |= (et.type == NT_unsigned) << 24; | |
15449 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 15450 | |
88714cb8 | 15451 | neon_dp_fixup (&inst); |
5287ad62 JB |
15452 | } |
15453 | ||
15454 | static void | |
15455 | do_neon_dyadic_long (void) | |
15456 | { | |
15457 | /* FIXME: Type checking for lengthening op. */ | |
15458 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
15459 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
15460 | neon_mixed_length (et, et.size); | |
15461 | } | |
15462 | ||
15463 | static void | |
15464 | do_neon_abal (void) | |
15465 | { | |
15466 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
15467 | N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
15468 | neon_mixed_length (et, et.size); | |
15469 | } | |
15470 | ||
15471 | static void | |
15472 | neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) | |
15473 | { | |
15474 | if (inst.operands[2].isscalar) | |
15475 | { | |
dcbf9037 | 15476 | struct neon_type_el et = neon_check_type (3, NS_QDS, |
477330fc | 15477 | N_EQK | N_DBL, N_EQK, regtypes | N_KEY); |
88714cb8 | 15478 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
15479 | neon_mul_mac (et, et.type == NT_unsigned); |
15480 | } | |
15481 | else | |
15482 | { | |
15483 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
477330fc | 15484 | N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); |
88714cb8 | 15485 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
15486 | neon_mixed_length (et, et.size); |
15487 | } | |
15488 | } | |
15489 | ||
15490 | static void | |
15491 | do_neon_mac_maybe_scalar_long (void) | |
15492 | { | |
15493 | neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); | |
15494 | } | |
15495 | ||
15496 | static void | |
15497 | do_neon_dyadic_wide (void) | |
15498 | { | |
15499 | struct neon_type_el et = neon_check_type (3, NS_QQD, | |
15500 | N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); | |
15501 | neon_mixed_length (et, et.size); | |
15502 | } | |
15503 | ||
15504 | static void | |
15505 | do_neon_dyadic_narrow (void) | |
15506 | { | |
15507 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
15508 | N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); | |
428e3f1f PB |
15509 | /* Operand sign is unimportant, and the U bit is part of the opcode, |
15510 | so force the operand type to integer. */ | |
15511 | et.type = NT_integer; | |
5287ad62 JB |
15512 | neon_mixed_length (et, et.size / 2); |
15513 | } | |
15514 | ||
15515 | static void | |
15516 | do_neon_mul_sat_scalar_long (void) | |
15517 | { | |
15518 | neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); | |
15519 | } | |
15520 | ||
15521 | static void | |
15522 | do_neon_vmull (void) | |
15523 | { | |
15524 | if (inst.operands[2].isscalar) | |
15525 | do_neon_mac_maybe_scalar_long (); | |
15526 | else | |
15527 | { | |
15528 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
477330fc | 15529 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY); |
4f51b4bd | 15530 | |
5287ad62 | 15531 | if (et.type == NT_poly) |
477330fc | 15532 | NEON_ENCODE (POLY, inst); |
5287ad62 | 15533 | else |
477330fc | 15534 | NEON_ENCODE (INTEGER, inst); |
4f51b4bd MGD |
15535 | |
15536 | /* For polynomial encoding the U bit must be zero, and the size must | |
15537 | be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non | |
15538 | obviously, as 0b10). */ | |
15539 | if (et.size == 64) | |
15540 | { | |
15541 | /* Check we're on the correct architecture. */ | |
15542 | if (!mark_feature_used (&fpu_crypto_ext_armv8)) | |
15543 | inst.error = | |
15544 | _("Instruction form not available on this architecture."); | |
15545 | ||
15546 | et.size = 32; | |
15547 | } | |
15548 | ||
5287ad62 JB |
15549 | neon_mixed_length (et, et.size); |
15550 | } | |
15551 | } | |
15552 | ||
15553 | static void | |
15554 | do_neon_ext (void) | |
15555 | { | |
037e8744 | 15556 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
5287ad62 JB |
15557 | struct neon_type_el et = neon_check_type (3, rs, |
15558 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
15559 | unsigned imm = (inst.operands[3].imm * et.size) / 8; | |
35997600 NC |
15560 | |
15561 | constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), | |
15562 | _("shift out of range")); | |
5287ad62 JB |
15563 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15564 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15565 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15566 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15567 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15568 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
037e8744 | 15569 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 | 15570 | inst.instruction |= imm << 8; |
5f4273c7 | 15571 | |
88714cb8 | 15572 | neon_dp_fixup (&inst); |
5287ad62 JB |
15573 | } |
15574 | ||
15575 | static void | |
15576 | do_neon_rev (void) | |
15577 | { | |
037e8744 | 15578 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15579 | struct neon_type_el et = neon_check_type (2, rs, |
15580 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
15581 | unsigned op = (inst.instruction >> 7) & 3; | |
15582 | /* N (width of reversed regions) is encoded as part of the bitmask. We | |
15583 | extract it here to check the elements to be reversed are smaller. | |
15584 | Otherwise we'd get a reserved instruction. */ | |
15585 | unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; | |
9c2799c2 | 15586 | gas_assert (elsize != 0); |
5287ad62 | 15587 | constraint (et.size >= elsize, |
477330fc | 15588 | _("elements must be smaller than reversal region")); |
037e8744 | 15589 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15590 | } |
15591 | ||
15592 | static void | |
15593 | do_neon_dup (void) | |
15594 | { | |
15595 | if (inst.operands[1].isscalar) | |
15596 | { | |
037e8744 | 15597 | enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); |
dcbf9037 | 15598 | struct neon_type_el et = neon_check_type (2, rs, |
477330fc | 15599 | N_EQK, N_8 | N_16 | N_32 | N_KEY); |
5287ad62 | 15600 | unsigned sizebits = et.size >> 3; |
dcbf9037 | 15601 | unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); |
5287ad62 | 15602 | int logsize = neon_logbits (et.size); |
dcbf9037 | 15603 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; |
037e8744 JB |
15604 | |
15605 | if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) | |
477330fc | 15606 | return; |
037e8744 | 15607 | |
88714cb8 | 15608 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
15609 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15610 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15611 | inst.instruction |= LOW4 (dm); | |
15612 | inst.instruction |= HI1 (dm) << 5; | |
037e8744 | 15613 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
15614 | inst.instruction |= x << 17; |
15615 | inst.instruction |= sizebits << 16; | |
5f4273c7 | 15616 | |
88714cb8 | 15617 | neon_dp_fixup (&inst); |
5287ad62 JB |
15618 | } |
15619 | else | |
15620 | { | |
037e8744 JB |
15621 | enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); |
15622 | struct neon_type_el et = neon_check_type (2, rs, | |
477330fc | 15623 | N_8 | N_16 | N_32 | N_KEY, N_EQK); |
5287ad62 | 15624 | /* Duplicate ARM register to lanes of vector. */ |
88714cb8 | 15625 | NEON_ENCODE (ARMREG, inst); |
5287ad62 | 15626 | switch (et.size) |
477330fc RM |
15627 | { |
15628 | case 8: inst.instruction |= 0x400000; break; | |
15629 | case 16: inst.instruction |= 0x000020; break; | |
15630 | case 32: inst.instruction |= 0x000000; break; | |
15631 | default: break; | |
15632 | } | |
5287ad62 JB |
15633 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; |
15634 | inst.instruction |= LOW4 (inst.operands[0].reg) << 16; | |
15635 | inst.instruction |= HI1 (inst.operands[0].reg) << 7; | |
037e8744 | 15636 | inst.instruction |= neon_quad (rs) << 21; |
5287ad62 | 15637 | /* The encoding for this instruction is identical for the ARM and Thumb |
477330fc | 15638 | variants, except for the condition field. */ |
037e8744 | 15639 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
15640 | } |
15641 | } | |
15642 | ||
15643 | /* VMOV has particularly many variations. It can be one of: | |
15644 | 0. VMOV<c><q> <Qd>, <Qm> | |
15645 | 1. VMOV<c><q> <Dd>, <Dm> | |
15646 | (Register operations, which are VORR with Rm = Rn.) | |
15647 | 2. VMOV<c><q>.<dt> <Qd>, #<imm> | |
15648 | 3. VMOV<c><q>.<dt> <Dd>, #<imm> | |
15649 | (Immediate loads.) | |
15650 | 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> | |
15651 | (ARM register to scalar.) | |
15652 | 5. VMOV<c><q> <Dm>, <Rd>, <Rn> | |
15653 | (Two ARM registers to vector.) | |
15654 | 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> | |
15655 | (Scalar to ARM register.) | |
15656 | 7. VMOV<c><q> <Rd>, <Rn>, <Dm> | |
15657 | (Vector to two ARM registers.) | |
037e8744 JB |
15658 | 8. VMOV.F32 <Sd>, <Sm> |
15659 | 9. VMOV.F64 <Dd>, <Dm> | |
15660 | (VFP register moves.) | |
15661 | 10. VMOV.F32 <Sd>, #imm | |
15662 | 11. VMOV.F64 <Dd>, #imm | |
15663 | (VFP float immediate load.) | |
15664 | 12. VMOV <Rd>, <Sm> | |
15665 | (VFP single to ARM reg.) | |
15666 | 13. VMOV <Sd>, <Rm> | |
15667 | (ARM reg to VFP single.) | |
15668 | 14. VMOV <Rd>, <Re>, <Sn>, <Sm> | |
15669 | (Two ARM regs to two VFP singles.) | |
15670 | 15. VMOV <Sd>, <Se>, <Rn>, <Rm> | |
15671 | (Two VFP singles to two ARM regs.) | |
5f4273c7 | 15672 | |
037e8744 JB |
15673 | These cases can be disambiguated using neon_select_shape, except cases 1/9 |
15674 | and 3/11 which depend on the operand type too. | |
5f4273c7 | 15675 | |
5287ad62 | 15676 | All the encoded bits are hardcoded by this function. |
5f4273c7 | 15677 | |
b7fc2769 JB |
15678 | Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). |
15679 | Cases 5, 7 may be used with VFPv2 and above. | |
5f4273c7 | 15680 | |
5287ad62 | 15681 | FIXME: Some of the checking may be a bit sloppy (in a couple of cases you |
5f4273c7 | 15682 | can specify a type where it doesn't make sense to, and is ignored). */ |
5287ad62 JB |
15683 | |
15684 | static void | |
15685 | do_neon_mov (void) | |
15686 | { | |
037e8744 JB |
15687 | enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, |
15688 | NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, | |
15689 | NS_NULL); | |
15690 | struct neon_type_el et; | |
15691 | const char *ldconst = 0; | |
5287ad62 | 15692 | |
037e8744 | 15693 | switch (rs) |
5287ad62 | 15694 | { |
037e8744 JB |
15695 | case NS_DD: /* case 1/9. */ |
15696 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
15697 | /* It is not an error here if no type is given. */ | |
15698 | inst.error = NULL; | |
15699 | if (et.type == NT_float && et.size == 64) | |
477330fc RM |
15700 | { |
15701 | do_vfp_nsyn_opcode ("fcpyd"); | |
15702 | break; | |
15703 | } | |
037e8744 | 15704 | /* fall through. */ |
5287ad62 | 15705 | |
037e8744 JB |
15706 | case NS_QQ: /* case 0/1. */ |
15707 | { | |
477330fc RM |
15708 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
15709 | return; | |
15710 | /* The architecture manual I have doesn't explicitly state which | |
15711 | value the U bit should have for register->register moves, but | |
15712 | the equivalent VORR instruction has U = 0, so do that. */ | |
15713 | inst.instruction = 0x0200110; | |
15714 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15715 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15716 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15717 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15718 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15719 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15720 | inst.instruction |= neon_quad (rs) << 6; | |
15721 | ||
15722 | neon_dp_fixup (&inst); | |
037e8744 JB |
15723 | } |
15724 | break; | |
5f4273c7 | 15725 | |
037e8744 JB |
15726 | case NS_DI: /* case 3/11. */ |
15727 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
15728 | inst.error = NULL; | |
15729 | if (et.type == NT_float && et.size == 64) | |
477330fc RM |
15730 | { |
15731 | /* case 11 (fconstd). */ | |
15732 | ldconst = "fconstd"; | |
15733 | goto encode_fconstd; | |
15734 | } | |
037e8744 JB |
15735 | /* fall through. */ |
15736 | ||
15737 | case NS_QI: /* case 2/3. */ | |
15738 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
477330fc | 15739 | return; |
037e8744 JB |
15740 | inst.instruction = 0x0800010; |
15741 | neon_move_immediate (); | |
88714cb8 | 15742 | neon_dp_fixup (&inst); |
5287ad62 | 15743 | break; |
5f4273c7 | 15744 | |
037e8744 JB |
15745 | case NS_SR: /* case 4. */ |
15746 | { | |
477330fc RM |
15747 | unsigned bcdebits = 0; |
15748 | int logsize; | |
15749 | unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); | |
15750 | unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); | |
037e8744 | 15751 | |
05ac0ffb JB |
15752 | /* .<size> is optional here, defaulting to .32. */ |
15753 | if (inst.vectype.elems == 0 | |
15754 | && inst.operands[0].vectype.type == NT_invtype | |
15755 | && inst.operands[1].vectype.type == NT_invtype) | |
15756 | { | |
15757 | inst.vectype.el[0].type = NT_untyped; | |
15758 | inst.vectype.el[0].size = 32; | |
15759 | inst.vectype.elems = 1; | |
15760 | } | |
15761 | ||
477330fc RM |
15762 | et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK); |
15763 | logsize = neon_logbits (et.size); | |
15764 | ||
15765 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), | |
15766 | _(BAD_FPU)); | |
15767 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
15768 | && et.size != 32, _(BAD_FPU)); | |
15769 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
15770 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
15771 | ||
15772 | switch (et.size) | |
15773 | { | |
15774 | case 8: bcdebits = 0x8; break; | |
15775 | case 16: bcdebits = 0x1; break; | |
15776 | case 32: bcdebits = 0x0; break; | |
15777 | default: ; | |
15778 | } | |
15779 | ||
15780 | bcdebits |= x << logsize; | |
15781 | ||
15782 | inst.instruction = 0xe000b10; | |
15783 | do_vfp_cond_or_thumb (); | |
15784 | inst.instruction |= LOW4 (dn) << 16; | |
15785 | inst.instruction |= HI1 (dn) << 7; | |
15786 | inst.instruction |= inst.operands[1].reg << 12; | |
15787 | inst.instruction |= (bcdebits & 3) << 5; | |
15788 | inst.instruction |= (bcdebits >> 2) << 21; | |
037e8744 JB |
15789 | } |
15790 | break; | |
5f4273c7 | 15791 | |
037e8744 | 15792 | case NS_DRR: /* case 5 (fmdrr). */ |
b7fc2769 | 15793 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), |
477330fc | 15794 | _(BAD_FPU)); |
b7fc2769 | 15795 | |
037e8744 JB |
15796 | inst.instruction = 0xc400b10; |
15797 | do_vfp_cond_or_thumb (); | |
15798 | inst.instruction |= LOW4 (inst.operands[0].reg); | |
15799 | inst.instruction |= HI1 (inst.operands[0].reg) << 5; | |
15800 | inst.instruction |= inst.operands[1].reg << 12; | |
15801 | inst.instruction |= inst.operands[2].reg << 16; | |
15802 | break; | |
5f4273c7 | 15803 | |
037e8744 JB |
15804 | case NS_RS: /* case 6. */ |
15805 | { | |
477330fc RM |
15806 | unsigned logsize; |
15807 | unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); | |
15808 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); | |
15809 | unsigned abcdebits = 0; | |
037e8744 | 15810 | |
05ac0ffb JB |
15811 | /* .<dt> is optional here, defaulting to .32. */ |
15812 | if (inst.vectype.elems == 0 | |
15813 | && inst.operands[0].vectype.type == NT_invtype | |
15814 | && inst.operands[1].vectype.type == NT_invtype) | |
15815 | { | |
15816 | inst.vectype.el[0].type = NT_untyped; | |
15817 | inst.vectype.el[0].size = 32; | |
15818 | inst.vectype.elems = 1; | |
15819 | } | |
15820 | ||
91d6fa6a NC |
15821 | et = neon_check_type (2, NS_NULL, |
15822 | N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); | |
477330fc RM |
15823 | logsize = neon_logbits (et.size); |
15824 | ||
15825 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), | |
15826 | _(BAD_FPU)); | |
15827 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
15828 | && et.size != 32, _(BAD_FPU)); | |
15829 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
15830 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
15831 | ||
15832 | switch (et.size) | |
15833 | { | |
15834 | case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; | |
15835 | case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; | |
15836 | case 32: abcdebits = 0x00; break; | |
15837 | default: ; | |
15838 | } | |
15839 | ||
15840 | abcdebits |= x << logsize; | |
15841 | inst.instruction = 0xe100b10; | |
15842 | do_vfp_cond_or_thumb (); | |
15843 | inst.instruction |= LOW4 (dn) << 16; | |
15844 | inst.instruction |= HI1 (dn) << 7; | |
15845 | inst.instruction |= inst.operands[0].reg << 12; | |
15846 | inst.instruction |= (abcdebits & 3) << 5; | |
15847 | inst.instruction |= (abcdebits >> 2) << 21; | |
037e8744 JB |
15848 | } |
15849 | break; | |
5f4273c7 | 15850 | |
037e8744 JB |
15851 | case NS_RRD: /* case 7 (fmrrd). */ |
15852 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), | |
477330fc | 15853 | _(BAD_FPU)); |
037e8744 JB |
15854 | |
15855 | inst.instruction = 0xc500b10; | |
15856 | do_vfp_cond_or_thumb (); | |
15857 | inst.instruction |= inst.operands[0].reg << 12; | |
15858 | inst.instruction |= inst.operands[1].reg << 16; | |
15859 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15860 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
15861 | break; | |
5f4273c7 | 15862 | |
037e8744 JB |
15863 | case NS_FF: /* case 8 (fcpys). */ |
15864 | do_vfp_nsyn_opcode ("fcpys"); | |
15865 | break; | |
5f4273c7 | 15866 | |
037e8744 JB |
15867 | case NS_FI: /* case 10 (fconsts). */ |
15868 | ldconst = "fconsts"; | |
15869 | encode_fconstd: | |
15870 | if (is_quarter_float (inst.operands[1].imm)) | |
477330fc RM |
15871 | { |
15872 | inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); | |
15873 | do_vfp_nsyn_opcode (ldconst); | |
15874 | } | |
5287ad62 | 15875 | else |
477330fc | 15876 | first_error (_("immediate out of range")); |
037e8744 | 15877 | break; |
5f4273c7 | 15878 | |
037e8744 JB |
15879 | case NS_RF: /* case 12 (fmrs). */ |
15880 | do_vfp_nsyn_opcode ("fmrs"); | |
15881 | break; | |
5f4273c7 | 15882 | |
037e8744 JB |
15883 | case NS_FR: /* case 13 (fmsr). */ |
15884 | do_vfp_nsyn_opcode ("fmsr"); | |
15885 | break; | |
5f4273c7 | 15886 | |
037e8744 JB |
15887 | /* The encoders for the fmrrs and fmsrr instructions expect three operands |
15888 | (one of which is a list), but we have parsed four. Do some fiddling to | |
15889 | make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 | |
15890 | expect. */ | |
15891 | case NS_RRFF: /* case 14 (fmrrs). */ | |
15892 | constraint (inst.operands[3].reg != inst.operands[2].reg + 1, | |
477330fc | 15893 | _("VFP registers must be adjacent")); |
037e8744 JB |
15894 | inst.operands[2].imm = 2; |
15895 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
15896 | do_vfp_nsyn_opcode ("fmrrs"); | |
15897 | break; | |
5f4273c7 | 15898 | |
037e8744 JB |
15899 | case NS_FFRR: /* case 15 (fmsrr). */ |
15900 | constraint (inst.operands[1].reg != inst.operands[0].reg + 1, | |
477330fc | 15901 | _("VFP registers must be adjacent")); |
037e8744 JB |
15902 | inst.operands[1] = inst.operands[2]; |
15903 | inst.operands[2] = inst.operands[3]; | |
15904 | inst.operands[0].imm = 2; | |
15905 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
15906 | do_vfp_nsyn_opcode ("fmsrr"); | |
5287ad62 | 15907 | break; |
5f4273c7 | 15908 | |
4c261dff NC |
15909 | case NS_NULL: |
15910 | /* neon_select_shape has determined that the instruction | |
15911 | shape is wrong and has already set the error message. */ | |
15912 | break; | |
15913 | ||
5287ad62 JB |
15914 | default: |
15915 | abort (); | |
15916 | } | |
15917 | } | |
15918 | ||
15919 | static void | |
15920 | do_neon_rshift_round_imm (void) | |
15921 | { | |
037e8744 | 15922 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
15923 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
15924 | int imm = inst.operands[2].imm; | |
15925 | ||
15926 | /* imm == 0 case is encoded as VMOV for V{R}SHR. */ | |
15927 | if (imm == 0) | |
15928 | { | |
15929 | inst.operands[2].present = 0; | |
15930 | do_neon_mov (); | |
15931 | return; | |
15932 | } | |
15933 | ||
15934 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 15935 | _("immediate out of range for shift")); |
037e8744 | 15936 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
477330fc | 15937 | et.size - imm); |
5287ad62 JB |
15938 | } |
15939 | ||
15940 | static void | |
15941 | do_neon_movl (void) | |
15942 | { | |
15943 | struct neon_type_el et = neon_check_type (2, NS_QD, | |
15944 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
15945 | unsigned sizebits = et.size >> 3; | |
15946 | inst.instruction |= sizebits << 19; | |
15947 | neon_two_same (0, et.type == NT_unsigned, -1); | |
15948 | } | |
15949 | ||
15950 | static void | |
15951 | do_neon_trn (void) | |
15952 | { | |
037e8744 | 15953 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15954 | struct neon_type_el et = neon_check_type (2, rs, |
15955 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
88714cb8 | 15956 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 15957 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15958 | } |
15959 | ||
15960 | static void | |
15961 | do_neon_zip_uzp (void) | |
15962 | { | |
037e8744 | 15963 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15964 | struct neon_type_el et = neon_check_type (2, rs, |
15965 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
15966 | if (rs == NS_DD && et.size == 32) | |
15967 | { | |
15968 | /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ | |
15969 | inst.instruction = N_MNEM_vtrn; | |
15970 | do_neon_trn (); | |
15971 | return; | |
15972 | } | |
037e8744 | 15973 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15974 | } |
15975 | ||
15976 | static void | |
15977 | do_neon_sat_abs_neg (void) | |
15978 | { | |
037e8744 | 15979 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15980 | struct neon_type_el et = neon_check_type (2, rs, |
15981 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 15982 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15983 | } |
15984 | ||
15985 | static void | |
15986 | do_neon_pair_long (void) | |
15987 | { | |
037e8744 | 15988 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15989 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); |
15990 | /* Unsigned is encoded in OP field (bit 7) for these instruction. */ | |
15991 | inst.instruction |= (et.type == NT_unsigned) << 7; | |
037e8744 | 15992 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15993 | } |
15994 | ||
15995 | static void | |
15996 | do_neon_recip_est (void) | |
15997 | { | |
037e8744 | 15998 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15999 | struct neon_type_el et = neon_check_type (2, rs, |
16000 | N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); | |
16001 | inst.instruction |= (et.type == NT_float) << 8; | |
037e8744 | 16002 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16003 | } |
16004 | ||
16005 | static void | |
16006 | do_neon_cls (void) | |
16007 | { | |
037e8744 | 16008 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16009 | struct neon_type_el et = neon_check_type (2, rs, |
16010 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 16011 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16012 | } |
16013 | ||
16014 | static void | |
16015 | do_neon_clz (void) | |
16016 | { | |
037e8744 | 16017 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16018 | struct neon_type_el et = neon_check_type (2, rs, |
16019 | N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); | |
037e8744 | 16020 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16021 | } |
16022 | ||
16023 | static void | |
16024 | do_neon_cnt (void) | |
16025 | { | |
037e8744 | 16026 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16027 | struct neon_type_el et = neon_check_type (2, rs, |
16028 | N_EQK | N_INT, N_8 | N_KEY); | |
037e8744 | 16029 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16030 | } |
16031 | ||
16032 | static void | |
16033 | do_neon_swp (void) | |
16034 | { | |
037e8744 JB |
16035 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
16036 | neon_two_same (neon_quad (rs), 1, -1); | |
5287ad62 JB |
16037 | } |
16038 | ||
16039 | static void | |
16040 | do_neon_tbl_tbx (void) | |
16041 | { | |
16042 | unsigned listlenbits; | |
dcbf9037 | 16043 | neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); |
5f4273c7 | 16044 | |
5287ad62 JB |
16045 | if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) |
16046 | { | |
dcbf9037 | 16047 | first_error (_("bad list length for table lookup")); |
5287ad62 JB |
16048 | return; |
16049 | } | |
5f4273c7 | 16050 | |
5287ad62 JB |
16051 | listlenbits = inst.operands[1].imm - 1; |
16052 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16053 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16054 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16055 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16056 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16057 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
16058 | inst.instruction |= listlenbits << 8; | |
5f4273c7 | 16059 | |
88714cb8 | 16060 | neon_dp_fixup (&inst); |
5287ad62 JB |
16061 | } |
16062 | ||
16063 | static void | |
16064 | do_neon_ldm_stm (void) | |
16065 | { | |
16066 | /* P, U and L bits are part of bitmask. */ | |
16067 | int is_dbmode = (inst.instruction & (1 << 24)) != 0; | |
16068 | unsigned offsetbits = inst.operands[1].imm * 2; | |
16069 | ||
037e8744 JB |
16070 | if (inst.operands[1].issingle) |
16071 | { | |
16072 | do_vfp_nsyn_ldm_stm (is_dbmode); | |
16073 | return; | |
16074 | } | |
16075 | ||
5287ad62 | 16076 | constraint (is_dbmode && !inst.operands[0].writeback, |
477330fc | 16077 | _("writeback (!) must be used for VLDMDB and VSTMDB")); |
5287ad62 JB |
16078 | |
16079 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
477330fc RM |
16080 | _("register list must contain at least 1 and at most 16 " |
16081 | "registers")); | |
5287ad62 JB |
16082 | |
16083 | inst.instruction |= inst.operands[0].reg << 16; | |
16084 | inst.instruction |= inst.operands[0].writeback << 21; | |
16085 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
16086 | inst.instruction |= HI1 (inst.operands[1].reg) << 22; | |
16087 | ||
16088 | inst.instruction |= offsetbits; | |
5f4273c7 | 16089 | |
037e8744 | 16090 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
16091 | } |
16092 | ||
16093 | static void | |
16094 | do_neon_ldr_str (void) | |
16095 | { | |
5287ad62 | 16096 | int is_ldr = (inst.instruction & (1 << 20)) != 0; |
5f4273c7 | 16097 | |
6844b2c2 MGD |
16098 | /* Use of PC in vstr in ARM mode is deprecated in ARMv7. |
16099 | And is UNPREDICTABLE in thumb mode. */ | |
fa94de6b | 16100 | if (!is_ldr |
6844b2c2 | 16101 | && inst.operands[1].reg == REG_PC |
ba86b375 | 16102 | && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode)) |
6844b2c2 | 16103 | { |
94dcf8bf | 16104 | if (thumb_mode) |
6844b2c2 | 16105 | inst.error = _("Use of PC here is UNPREDICTABLE"); |
94dcf8bf | 16106 | else if (warn_on_deprecated) |
5c3696f8 | 16107 | as_tsktsk (_("Use of PC here is deprecated")); |
6844b2c2 MGD |
16108 | } |
16109 | ||
037e8744 JB |
16110 | if (inst.operands[0].issingle) |
16111 | { | |
cd2f129f | 16112 | if (is_ldr) |
477330fc | 16113 | do_vfp_nsyn_opcode ("flds"); |
cd2f129f | 16114 | else |
477330fc | 16115 | do_vfp_nsyn_opcode ("fsts"); |
5287ad62 JB |
16116 | } |
16117 | else | |
5287ad62 | 16118 | { |
cd2f129f | 16119 | if (is_ldr) |
477330fc | 16120 | do_vfp_nsyn_opcode ("fldd"); |
5287ad62 | 16121 | else |
477330fc | 16122 | do_vfp_nsyn_opcode ("fstd"); |
5287ad62 | 16123 | } |
5287ad62 JB |
16124 | } |
16125 | ||
16126 | /* "interleave" version also handles non-interleaving register VLD1/VST1 | |
16127 | instructions. */ | |
16128 | ||
16129 | static void | |
16130 | do_neon_ld_st_interleave (void) | |
16131 | { | |
037e8744 | 16132 | struct neon_type_el et = neon_check_type (1, NS_NULL, |
477330fc | 16133 | N_8 | N_16 | N_32 | N_64); |
5287ad62 JB |
16134 | unsigned alignbits = 0; |
16135 | unsigned idx; | |
16136 | /* The bits in this table go: | |
16137 | 0: register stride of one (0) or two (1) | |
16138 | 1,2: register list length, minus one (1, 2, 3, 4). | |
16139 | 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). | |
16140 | We use -1 for invalid entries. */ | |
16141 | const int typetable[] = | |
16142 | { | |
16143 | 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ | |
16144 | -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ | |
16145 | -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ | |
16146 | -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ | |
16147 | }; | |
16148 | int typebits; | |
16149 | ||
dcbf9037 JB |
16150 | if (et.type == NT_invtype) |
16151 | return; | |
16152 | ||
5287ad62 JB |
16153 | if (inst.operands[1].immisalign) |
16154 | switch (inst.operands[1].imm >> 8) | |
16155 | { | |
16156 | case 64: alignbits = 1; break; | |
16157 | case 128: | |
477330fc | 16158 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2 |
e23c0ad8 | 16159 | && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
477330fc RM |
16160 | goto bad_alignment; |
16161 | alignbits = 2; | |
16162 | break; | |
5287ad62 | 16163 | case 256: |
477330fc RM |
16164 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
16165 | goto bad_alignment; | |
16166 | alignbits = 3; | |
16167 | break; | |
5287ad62 JB |
16168 | default: |
16169 | bad_alignment: | |
477330fc RM |
16170 | first_error (_("bad alignment")); |
16171 | return; | |
5287ad62 JB |
16172 | } |
16173 | ||
16174 | inst.instruction |= alignbits << 4; | |
16175 | inst.instruction |= neon_logbits (et.size) << 6; | |
16176 | ||
16177 | /* Bits [4:6] of the immediate in a list specifier encode register stride | |
16178 | (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of | |
16179 | VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look | |
16180 | up the right value for "type" in a table based on this value and the given | |
16181 | list style, then stick it back. */ | |
16182 | idx = ((inst.operands[0].imm >> 4) & 7) | |
477330fc | 16183 | | (((inst.instruction >> 8) & 3) << 3); |
5287ad62 JB |
16184 | |
16185 | typebits = typetable[idx]; | |
5f4273c7 | 16186 | |
5287ad62 | 16187 | constraint (typebits == -1, _("bad list type for instruction")); |
1d50d57c WN |
16188 | constraint (((inst.instruction >> 8) & 3) && et.size == 64, |
16189 | _("bad element type for instruction")); | |
5287ad62 JB |
16190 | |
16191 | inst.instruction &= ~0xf00; | |
16192 | inst.instruction |= typebits << 8; | |
16193 | } | |
16194 | ||
16195 | /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. | |
16196 | *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 | |
16197 | otherwise. The variable arguments are a list of pairs of legal (size, align) | |
16198 | values, terminated with -1. */ | |
16199 | ||
16200 | static int | |
16201 | neon_alignment_bit (int size, int align, int *do_align, ...) | |
16202 | { | |
16203 | va_list ap; | |
16204 | int result = FAIL, thissize, thisalign; | |
5f4273c7 | 16205 | |
5287ad62 JB |
16206 | if (!inst.operands[1].immisalign) |
16207 | { | |
16208 | *do_align = 0; | |
16209 | return SUCCESS; | |
16210 | } | |
5f4273c7 | 16211 | |
5287ad62 JB |
16212 | va_start (ap, do_align); |
16213 | ||
16214 | do | |
16215 | { | |
16216 | thissize = va_arg (ap, int); | |
16217 | if (thissize == -1) | |
477330fc | 16218 | break; |
5287ad62 JB |
16219 | thisalign = va_arg (ap, int); |
16220 | ||
16221 | if (size == thissize && align == thisalign) | |
477330fc | 16222 | result = SUCCESS; |
5287ad62 JB |
16223 | } |
16224 | while (result != SUCCESS); | |
16225 | ||
16226 | va_end (ap); | |
16227 | ||
16228 | if (result == SUCCESS) | |
16229 | *do_align = 1; | |
16230 | else | |
dcbf9037 | 16231 | first_error (_("unsupported alignment for instruction")); |
5f4273c7 | 16232 | |
5287ad62 JB |
16233 | return result; |
16234 | } | |
16235 | ||
16236 | static void | |
16237 | do_neon_ld_st_lane (void) | |
16238 | { | |
037e8744 | 16239 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
16240 | int align_good, do_align = 0; |
16241 | int logsize = neon_logbits (et.size); | |
16242 | int align = inst.operands[1].imm >> 8; | |
16243 | int n = (inst.instruction >> 8) & 3; | |
16244 | int max_el = 64 / et.size; | |
5f4273c7 | 16245 | |
dcbf9037 JB |
16246 | if (et.type == NT_invtype) |
16247 | return; | |
5f4273c7 | 16248 | |
5287ad62 | 16249 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, |
477330fc | 16250 | _("bad list length")); |
5287ad62 | 16251 | constraint (NEON_LANE (inst.operands[0].imm) >= max_el, |
477330fc | 16252 | _("scalar index out of range")); |
5287ad62 | 16253 | constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 |
477330fc RM |
16254 | && et.size == 8, |
16255 | _("stride of 2 unavailable when element size is 8")); | |
5f4273c7 | 16256 | |
5287ad62 JB |
16257 | switch (n) |
16258 | { | |
16259 | case 0: /* VLD1 / VST1. */ | |
16260 | align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, | |
477330fc | 16261 | 32, 32, -1); |
5287ad62 | 16262 | if (align_good == FAIL) |
477330fc | 16263 | return; |
5287ad62 | 16264 | if (do_align) |
477330fc RM |
16265 | { |
16266 | unsigned alignbits = 0; | |
16267 | switch (et.size) | |
16268 | { | |
16269 | case 16: alignbits = 0x1; break; | |
16270 | case 32: alignbits = 0x3; break; | |
16271 | default: ; | |
16272 | } | |
16273 | inst.instruction |= alignbits << 4; | |
16274 | } | |
5287ad62 JB |
16275 | break; |
16276 | ||
16277 | case 1: /* VLD2 / VST2. */ | |
16278 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, | |
477330fc | 16279 | 32, 64, -1); |
5287ad62 | 16280 | if (align_good == FAIL) |
477330fc | 16281 | return; |
5287ad62 | 16282 | if (do_align) |
477330fc | 16283 | inst.instruction |= 1 << 4; |
5287ad62 JB |
16284 | break; |
16285 | ||
16286 | case 2: /* VLD3 / VST3. */ | |
16287 | constraint (inst.operands[1].immisalign, | |
477330fc | 16288 | _("can't use alignment with this instruction")); |
5287ad62 JB |
16289 | break; |
16290 | ||
16291 | case 3: /* VLD4 / VST4. */ | |
16292 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
477330fc | 16293 | 16, 64, 32, 64, 32, 128, -1); |
5287ad62 | 16294 | if (align_good == FAIL) |
477330fc | 16295 | return; |
5287ad62 | 16296 | if (do_align) |
477330fc RM |
16297 | { |
16298 | unsigned alignbits = 0; | |
16299 | switch (et.size) | |
16300 | { | |
16301 | case 8: alignbits = 0x1; break; | |
16302 | case 16: alignbits = 0x1; break; | |
16303 | case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; | |
16304 | default: ; | |
16305 | } | |
16306 | inst.instruction |= alignbits << 4; | |
16307 | } | |
5287ad62 JB |
16308 | break; |
16309 | ||
16310 | default: ; | |
16311 | } | |
16312 | ||
16313 | /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ | |
16314 | if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
16315 | inst.instruction |= 1 << (4 + logsize); | |
5f4273c7 | 16316 | |
5287ad62 JB |
16317 | inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); |
16318 | inst.instruction |= logsize << 10; | |
16319 | } | |
16320 | ||
16321 | /* Encode single n-element structure to all lanes VLD<n> instructions. */ | |
16322 | ||
16323 | static void | |
16324 | do_neon_ld_dup (void) | |
16325 | { | |
037e8744 | 16326 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
16327 | int align_good, do_align = 0; |
16328 | ||
dcbf9037 JB |
16329 | if (et.type == NT_invtype) |
16330 | return; | |
16331 | ||
5287ad62 JB |
16332 | switch ((inst.instruction >> 8) & 3) |
16333 | { | |
16334 | case 0: /* VLD1. */ | |
9c2799c2 | 16335 | gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); |
5287ad62 | 16336 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, |
477330fc | 16337 | &do_align, 16, 16, 32, 32, -1); |
5287ad62 | 16338 | if (align_good == FAIL) |
477330fc | 16339 | return; |
5287ad62 | 16340 | switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) |
477330fc RM |
16341 | { |
16342 | case 1: break; | |
16343 | case 2: inst.instruction |= 1 << 5; break; | |
16344 | default: first_error (_("bad list length")); return; | |
16345 | } | |
5287ad62 JB |
16346 | inst.instruction |= neon_logbits (et.size) << 6; |
16347 | break; | |
16348 | ||
16349 | case 1: /* VLD2. */ | |
16350 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, | |
477330fc | 16351 | &do_align, 8, 16, 16, 32, 32, 64, -1); |
5287ad62 | 16352 | if (align_good == FAIL) |
477330fc | 16353 | return; |
5287ad62 | 16354 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, |
477330fc | 16355 | _("bad list length")); |
5287ad62 | 16356 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) |
477330fc | 16357 | inst.instruction |= 1 << 5; |
5287ad62 JB |
16358 | inst.instruction |= neon_logbits (et.size) << 6; |
16359 | break; | |
16360 | ||
16361 | case 2: /* VLD3. */ | |
16362 | constraint (inst.operands[1].immisalign, | |
477330fc | 16363 | _("can't use alignment with this instruction")); |
5287ad62 | 16364 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, |
477330fc | 16365 | _("bad list length")); |
5287ad62 | 16366 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) |
477330fc | 16367 | inst.instruction |= 1 << 5; |
5287ad62 JB |
16368 | inst.instruction |= neon_logbits (et.size) << 6; |
16369 | break; | |
16370 | ||
16371 | case 3: /* VLD4. */ | |
16372 | { | |
477330fc RM |
16373 | int align = inst.operands[1].imm >> 8; |
16374 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
16375 | 16, 64, 32, 64, 32, 128, -1); | |
16376 | if (align_good == FAIL) | |
16377 | return; | |
16378 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, | |
16379 | _("bad list length")); | |
16380 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
16381 | inst.instruction |= 1 << 5; | |
16382 | if (et.size == 32 && align == 128) | |
16383 | inst.instruction |= 0x3 << 6; | |
16384 | else | |
16385 | inst.instruction |= neon_logbits (et.size) << 6; | |
5287ad62 JB |
16386 | } |
16387 | break; | |
16388 | ||
16389 | default: ; | |
16390 | } | |
16391 | ||
16392 | inst.instruction |= do_align << 4; | |
16393 | } | |
16394 | ||
16395 | /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those | |
16396 | apart from bits [11:4]. */ | |
16397 | ||
16398 | static void | |
16399 | do_neon_ldx_stx (void) | |
16400 | { | |
b1a769ed DG |
16401 | if (inst.operands[1].isreg) |
16402 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); | |
16403 | ||
5287ad62 JB |
16404 | switch (NEON_LANE (inst.operands[0].imm)) |
16405 | { | |
16406 | case NEON_INTERLEAVE_LANES: | |
88714cb8 | 16407 | NEON_ENCODE (INTERLV, inst); |
5287ad62 JB |
16408 | do_neon_ld_st_interleave (); |
16409 | break; | |
5f4273c7 | 16410 | |
5287ad62 | 16411 | case NEON_ALL_LANES: |
88714cb8 | 16412 | NEON_ENCODE (DUP, inst); |
2d51fb74 JB |
16413 | if (inst.instruction == N_INV) |
16414 | { | |
16415 | first_error ("only loads support such operands"); | |
16416 | break; | |
16417 | } | |
5287ad62 JB |
16418 | do_neon_ld_dup (); |
16419 | break; | |
5f4273c7 | 16420 | |
5287ad62 | 16421 | default: |
88714cb8 | 16422 | NEON_ENCODE (LANE, inst); |
5287ad62 JB |
16423 | do_neon_ld_st_lane (); |
16424 | } | |
16425 | ||
16426 | /* L bit comes from bit mask. */ | |
16427 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16428 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16429 | inst.instruction |= inst.operands[1].reg << 16; | |
5f4273c7 | 16430 | |
5287ad62 JB |
16431 | if (inst.operands[1].postind) |
16432 | { | |
16433 | int postreg = inst.operands[1].imm & 0xf; | |
16434 | constraint (!inst.operands[1].immisreg, | |
477330fc | 16435 | _("post-index must be a register")); |
5287ad62 | 16436 | constraint (postreg == 0xd || postreg == 0xf, |
477330fc | 16437 | _("bad register for post-index")); |
5287ad62 JB |
16438 | inst.instruction |= postreg; |
16439 | } | |
4f2374c7 | 16440 | else |
5287ad62 | 16441 | { |
4f2374c7 WN |
16442 | constraint (inst.operands[1].immisreg, BAD_ADDR_MODE); |
16443 | constraint (inst.reloc.exp.X_op != O_constant | |
16444 | || inst.reloc.exp.X_add_number != 0, | |
16445 | BAD_ADDR_MODE); | |
16446 | ||
16447 | if (inst.operands[1].writeback) | |
16448 | { | |
16449 | inst.instruction |= 0xd; | |
16450 | } | |
16451 | else | |
16452 | inst.instruction |= 0xf; | |
5287ad62 | 16453 | } |
5f4273c7 | 16454 | |
5287ad62 JB |
16455 | if (thumb_mode) |
16456 | inst.instruction |= 0xf9000000; | |
16457 | else | |
16458 | inst.instruction |= 0xf4000000; | |
16459 | } | |
33399f07 MGD |
16460 | |
16461 | /* FP v8. */ | |
16462 | static void | |
16463 | do_vfp_nsyn_fpv8 (enum neon_shape rs) | |
16464 | { | |
a715796b TG |
16465 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
16466 | D register operands. */ | |
16467 | if (neon_shape_class[rs] == SC_DOUBLE) | |
16468 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
16469 | _(BAD_FPU)); | |
16470 | ||
33399f07 MGD |
16471 | NEON_ENCODE (FPV8, inst); |
16472 | ||
16473 | if (rs == NS_FFF) | |
16474 | do_vfp_sp_dyadic (); | |
16475 | else | |
16476 | do_vfp_dp_rd_rn_rm (); | |
16477 | ||
16478 | if (rs == NS_DDD) | |
16479 | inst.instruction |= 0x100; | |
16480 | ||
16481 | inst.instruction |= 0xf0000000; | |
16482 | } | |
16483 | ||
16484 | static void | |
16485 | do_vsel (void) | |
16486 | { | |
16487 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16488 | ||
16489 | if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS) | |
16490 | first_error (_("invalid instruction shape")); | |
16491 | } | |
16492 | ||
73924fbc MGD |
16493 | static void |
16494 | do_vmaxnm (void) | |
16495 | { | |
16496 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16497 | ||
16498 | if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS) | |
16499 | return; | |
16500 | ||
16501 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL) | |
16502 | return; | |
16503 | ||
16504 | neon_dyadic_misc (NT_untyped, N_F32, 0); | |
16505 | } | |
16506 | ||
30bdf752 MGD |
16507 | static void |
16508 | do_vrint_1 (enum neon_cvt_mode mode) | |
16509 | { | |
16510 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_QQ, NS_NULL); | |
16511 | struct neon_type_el et; | |
16512 | ||
16513 | if (rs == NS_NULL) | |
16514 | return; | |
16515 | ||
a715796b TG |
16516 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
16517 | D register operands. */ | |
16518 | if (neon_shape_class[rs] == SC_DOUBLE) | |
16519 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
16520 | _(BAD_FPU)); | |
16521 | ||
30bdf752 MGD |
16522 | et = neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); |
16523 | if (et.type != NT_invtype) | |
16524 | { | |
16525 | /* VFP encodings. */ | |
16526 | if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n | |
16527 | || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m) | |
16528 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16529 | ||
16530 | NEON_ENCODE (FPV8, inst); | |
16531 | if (rs == NS_FF) | |
16532 | do_vfp_sp_monadic (); | |
16533 | else | |
16534 | do_vfp_dp_rd_rm (); | |
16535 | ||
16536 | switch (mode) | |
16537 | { | |
16538 | case neon_cvt_mode_r: inst.instruction |= 0x00000000; break; | |
16539 | case neon_cvt_mode_z: inst.instruction |= 0x00000080; break; | |
16540 | case neon_cvt_mode_x: inst.instruction |= 0x00010000; break; | |
16541 | case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break; | |
16542 | case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break; | |
16543 | case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break; | |
16544 | case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break; | |
16545 | default: abort (); | |
16546 | } | |
16547 | ||
16548 | inst.instruction |= (rs == NS_DD) << 8; | |
16549 | do_vfp_cond_or_thumb (); | |
16550 | } | |
16551 | else | |
16552 | { | |
16553 | /* Neon encodings (or something broken...). */ | |
16554 | inst.error = NULL; | |
16555 | et = neon_check_type (2, rs, N_EQK, N_F32 | N_KEY); | |
16556 | ||
16557 | if (et.type == NT_invtype) | |
16558 | return; | |
16559 | ||
16560 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16561 | NEON_ENCODE (FLOAT, inst); | |
16562 | ||
16563 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL) | |
16564 | return; | |
16565 | ||
16566 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16567 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16568 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16569 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
16570 | inst.instruction |= neon_quad (rs) << 6; | |
16571 | switch (mode) | |
16572 | { | |
16573 | case neon_cvt_mode_z: inst.instruction |= 3 << 7; break; | |
16574 | case neon_cvt_mode_x: inst.instruction |= 1 << 7; break; | |
16575 | case neon_cvt_mode_a: inst.instruction |= 2 << 7; break; | |
16576 | case neon_cvt_mode_n: inst.instruction |= 0 << 7; break; | |
16577 | case neon_cvt_mode_p: inst.instruction |= 7 << 7; break; | |
16578 | case neon_cvt_mode_m: inst.instruction |= 5 << 7; break; | |
16579 | case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break; | |
16580 | default: abort (); | |
16581 | } | |
16582 | ||
16583 | if (thumb_mode) | |
16584 | inst.instruction |= 0xfc000000; | |
16585 | else | |
16586 | inst.instruction |= 0xf0000000; | |
16587 | } | |
16588 | } | |
16589 | ||
16590 | static void | |
16591 | do_vrintx (void) | |
16592 | { | |
16593 | do_vrint_1 (neon_cvt_mode_x); | |
16594 | } | |
16595 | ||
16596 | static void | |
16597 | do_vrintz (void) | |
16598 | { | |
16599 | do_vrint_1 (neon_cvt_mode_z); | |
16600 | } | |
16601 | ||
16602 | static void | |
16603 | do_vrintr (void) | |
16604 | { | |
16605 | do_vrint_1 (neon_cvt_mode_r); | |
16606 | } | |
16607 | ||
16608 | static void | |
16609 | do_vrinta (void) | |
16610 | { | |
16611 | do_vrint_1 (neon_cvt_mode_a); | |
16612 | } | |
16613 | ||
16614 | static void | |
16615 | do_vrintn (void) | |
16616 | { | |
16617 | do_vrint_1 (neon_cvt_mode_n); | |
16618 | } | |
16619 | ||
16620 | static void | |
16621 | do_vrintp (void) | |
16622 | { | |
16623 | do_vrint_1 (neon_cvt_mode_p); | |
16624 | } | |
16625 | ||
16626 | static void | |
16627 | do_vrintm (void) | |
16628 | { | |
16629 | do_vrint_1 (neon_cvt_mode_m); | |
16630 | } | |
16631 | ||
91ff7894 MGD |
16632 | /* Crypto v1 instructions. */ |
16633 | static void | |
16634 | do_crypto_2op_1 (unsigned elttype, int op) | |
16635 | { | |
16636 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16637 | ||
16638 | if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type | |
16639 | == NT_invtype) | |
16640 | return; | |
16641 | ||
16642 | inst.error = NULL; | |
16643 | ||
16644 | NEON_ENCODE (INTEGER, inst); | |
16645 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16646 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16647 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16648 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
16649 | if (op != -1) | |
16650 | inst.instruction |= op << 6; | |
16651 | ||
16652 | if (thumb_mode) | |
16653 | inst.instruction |= 0xfc000000; | |
16654 | else | |
16655 | inst.instruction |= 0xf0000000; | |
16656 | } | |
16657 | ||
48adcd8e MGD |
16658 | static void |
16659 | do_crypto_3op_1 (int u, int op) | |
16660 | { | |
16661 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16662 | ||
16663 | if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT, | |
16664 | N_32 | N_UNT | N_KEY).type == NT_invtype) | |
16665 | return; | |
16666 | ||
16667 | inst.error = NULL; | |
16668 | ||
16669 | NEON_ENCODE (INTEGER, inst); | |
16670 | neon_three_same (1, u, 8 << op); | |
16671 | } | |
16672 | ||
91ff7894 MGD |
16673 | static void |
16674 | do_aese (void) | |
16675 | { | |
16676 | do_crypto_2op_1 (N_8, 0); | |
16677 | } | |
16678 | ||
16679 | static void | |
16680 | do_aesd (void) | |
16681 | { | |
16682 | do_crypto_2op_1 (N_8, 1); | |
16683 | } | |
16684 | ||
16685 | static void | |
16686 | do_aesmc (void) | |
16687 | { | |
16688 | do_crypto_2op_1 (N_8, 2); | |
16689 | } | |
16690 | ||
16691 | static void | |
16692 | do_aesimc (void) | |
16693 | { | |
16694 | do_crypto_2op_1 (N_8, 3); | |
16695 | } | |
16696 | ||
48adcd8e MGD |
16697 | static void |
16698 | do_sha1c (void) | |
16699 | { | |
16700 | do_crypto_3op_1 (0, 0); | |
16701 | } | |
16702 | ||
16703 | static void | |
16704 | do_sha1p (void) | |
16705 | { | |
16706 | do_crypto_3op_1 (0, 1); | |
16707 | } | |
16708 | ||
16709 | static void | |
16710 | do_sha1m (void) | |
16711 | { | |
16712 | do_crypto_3op_1 (0, 2); | |
16713 | } | |
16714 | ||
16715 | static void | |
16716 | do_sha1su0 (void) | |
16717 | { | |
16718 | do_crypto_3op_1 (0, 3); | |
16719 | } | |
91ff7894 | 16720 | |
48adcd8e MGD |
16721 | static void |
16722 | do_sha256h (void) | |
16723 | { | |
16724 | do_crypto_3op_1 (1, 0); | |
16725 | } | |
16726 | ||
16727 | static void | |
16728 | do_sha256h2 (void) | |
16729 | { | |
16730 | do_crypto_3op_1 (1, 1); | |
16731 | } | |
16732 | ||
16733 | static void | |
16734 | do_sha256su1 (void) | |
16735 | { | |
16736 | do_crypto_3op_1 (1, 2); | |
16737 | } | |
3c9017d2 MGD |
16738 | |
16739 | static void | |
16740 | do_sha1h (void) | |
16741 | { | |
16742 | do_crypto_2op_1 (N_32, -1); | |
16743 | } | |
16744 | ||
16745 | static void | |
16746 | do_sha1su1 (void) | |
16747 | { | |
16748 | do_crypto_2op_1 (N_32, 0); | |
16749 | } | |
16750 | ||
16751 | static void | |
16752 | do_sha256su0 (void) | |
16753 | { | |
16754 | do_crypto_2op_1 (N_32, 1); | |
16755 | } | |
dd5181d5 KT |
16756 | |
16757 | static void | |
16758 | do_crc32_1 (unsigned int poly, unsigned int sz) | |
16759 | { | |
16760 | unsigned int Rd = inst.operands[0].reg; | |
16761 | unsigned int Rn = inst.operands[1].reg; | |
16762 | unsigned int Rm = inst.operands[2].reg; | |
16763 | ||
16764 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16765 | inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12); | |
16766 | inst.instruction |= LOW4 (Rn) << 16; | |
16767 | inst.instruction |= LOW4 (Rm); | |
16768 | inst.instruction |= sz << (thumb_mode ? 4 : 21); | |
16769 | inst.instruction |= poly << (thumb_mode ? 20 : 9); | |
16770 | ||
16771 | if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC) | |
16772 | as_warn (UNPRED_REG ("r15")); | |
16773 | if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP)) | |
16774 | as_warn (UNPRED_REG ("r13")); | |
16775 | } | |
16776 | ||
16777 | static void | |
16778 | do_crc32b (void) | |
16779 | { | |
16780 | do_crc32_1 (0, 0); | |
16781 | } | |
16782 | ||
16783 | static void | |
16784 | do_crc32h (void) | |
16785 | { | |
16786 | do_crc32_1 (0, 1); | |
16787 | } | |
16788 | ||
16789 | static void | |
16790 | do_crc32w (void) | |
16791 | { | |
16792 | do_crc32_1 (0, 2); | |
16793 | } | |
16794 | ||
16795 | static void | |
16796 | do_crc32cb (void) | |
16797 | { | |
16798 | do_crc32_1 (1, 0); | |
16799 | } | |
16800 | ||
16801 | static void | |
16802 | do_crc32ch (void) | |
16803 | { | |
16804 | do_crc32_1 (1, 1); | |
16805 | } | |
16806 | ||
16807 | static void | |
16808 | do_crc32cw (void) | |
16809 | { | |
16810 | do_crc32_1 (1, 2); | |
16811 | } | |
16812 | ||
5287ad62 JB |
16813 | \f |
16814 | /* Overall per-instruction processing. */ | |
16815 | ||
16816 | /* We need to be able to fix up arbitrary expressions in some statements. | |
16817 | This is so that we can handle symbols that are an arbitrary distance from | |
16818 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
16819 | which returns part of an address in a form which will be valid for | |
16820 | a data instruction. We do this by pushing the expression into a symbol | |
16821 | in the expr_section, and creating a fix for that. */ | |
16822 | ||
16823 | static void | |
16824 | fix_new_arm (fragS * frag, | |
16825 | int where, | |
16826 | short int size, | |
16827 | expressionS * exp, | |
16828 | int pc_rel, | |
16829 | int reloc) | |
16830 | { | |
16831 | fixS * new_fix; | |
16832 | ||
16833 | switch (exp->X_op) | |
16834 | { | |
16835 | case O_constant: | |
6e7ce2cd PB |
16836 | if (pc_rel) |
16837 | { | |
16838 | /* Create an absolute valued symbol, so we have something to | |
477330fc RM |
16839 | refer to in the object file. Unfortunately for us, gas's |
16840 | generic expression parsing will already have folded out | |
16841 | any use of .set foo/.type foo %function that may have | |
16842 | been used to set type information of the target location, | |
16843 | that's being specified symbolically. We have to presume | |
16844 | the user knows what they are doing. */ | |
6e7ce2cd PB |
16845 | char name[16 + 8]; |
16846 | symbolS *symbol; | |
16847 | ||
16848 | sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number); | |
16849 | ||
16850 | symbol = symbol_find_or_make (name); | |
16851 | S_SET_SEGMENT (symbol, absolute_section); | |
16852 | symbol_set_frag (symbol, &zero_address_frag); | |
16853 | S_SET_VALUE (symbol, exp->X_add_number); | |
16854 | exp->X_op = O_symbol; | |
16855 | exp->X_add_symbol = symbol; | |
16856 | exp->X_add_number = 0; | |
16857 | } | |
16858 | /* FALLTHROUGH */ | |
5287ad62 JB |
16859 | case O_symbol: |
16860 | case O_add: | |
16861 | case O_subtract: | |
21d799b5 | 16862 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, |
477330fc | 16863 | (enum bfd_reloc_code_real) reloc); |
5287ad62 JB |
16864 | break; |
16865 | ||
16866 | default: | |
21d799b5 | 16867 | new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0, |
477330fc | 16868 | pc_rel, (enum bfd_reloc_code_real) reloc); |
5287ad62 JB |
16869 | break; |
16870 | } | |
16871 | ||
16872 | /* Mark whether the fix is to a THUMB instruction, or an ARM | |
16873 | instruction. */ | |
16874 | new_fix->tc_fix_data = thumb_mode; | |
16875 | } | |
16876 | ||
16877 | /* Create a frg for an instruction requiring relaxation. */ | |
16878 | static void | |
16879 | output_relax_insn (void) | |
16880 | { | |
16881 | char * to; | |
16882 | symbolS *sym; | |
0110f2b8 PB |
16883 | int offset; |
16884 | ||
6e1cb1a6 PB |
16885 | /* The size of the instruction is unknown, so tie the debug info to the |
16886 | start of the instruction. */ | |
16887 | dwarf2_emit_insn (0); | |
6e1cb1a6 | 16888 | |
0110f2b8 PB |
16889 | switch (inst.reloc.exp.X_op) |
16890 | { | |
16891 | case O_symbol: | |
16892 | sym = inst.reloc.exp.X_add_symbol; | |
16893 | offset = inst.reloc.exp.X_add_number; | |
16894 | break; | |
16895 | case O_constant: | |
16896 | sym = NULL; | |
16897 | offset = inst.reloc.exp.X_add_number; | |
16898 | break; | |
16899 | default: | |
16900 | sym = make_expr_symbol (&inst.reloc.exp); | |
16901 | offset = 0; | |
16902 | break; | |
16903 | } | |
16904 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
16905 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
16906 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
0110f2b8 PB |
16907 | } |
16908 | ||
16909 | /* Write a 32-bit thumb instruction to buf. */ | |
16910 | static void | |
16911 | put_thumb32_insn (char * buf, unsigned long insn) | |
16912 | { | |
16913 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
16914 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
16915 | } | |
16916 | ||
b99bd4ef | 16917 | static void |
c19d1205 | 16918 | output_inst (const char * str) |
b99bd4ef | 16919 | { |
c19d1205 | 16920 | char * to = NULL; |
b99bd4ef | 16921 | |
c19d1205 | 16922 | if (inst.error) |
b99bd4ef | 16923 | { |
c19d1205 | 16924 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
16925 | return; |
16926 | } | |
5f4273c7 NC |
16927 | if (inst.relax) |
16928 | { | |
16929 | output_relax_insn (); | |
0110f2b8 | 16930 | return; |
5f4273c7 | 16931 | } |
c19d1205 ZW |
16932 | if (inst.size == 0) |
16933 | return; | |
b99bd4ef | 16934 | |
c19d1205 | 16935 | to = frag_more (inst.size); |
8dc2430f NC |
16936 | /* PR 9814: Record the thumb mode into the current frag so that we know |
16937 | what type of NOP padding to use, if necessary. We override any previous | |
16938 | setting so that if the mode has changed then the NOPS that we use will | |
16939 | match the encoding of the last instruction in the frag. */ | |
cd000bff | 16940 | frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
c19d1205 ZW |
16941 | |
16942 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 16943 | { |
9c2799c2 | 16944 | gas_assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 16945 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 16946 | } |
c19d1205 | 16947 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 16948 | { |
9c2799c2 | 16949 | gas_assert (inst.size == (2 * INSN_SIZE)); |
c19d1205 ZW |
16950 | md_number_to_chars (to, inst.instruction, INSN_SIZE); |
16951 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 16952 | } |
c19d1205 ZW |
16953 | else |
16954 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 16955 | |
c19d1205 ZW |
16956 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
16957 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
16958 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
16959 | inst.reloc.type); | |
b99bd4ef | 16960 | |
c19d1205 | 16961 | dwarf2_emit_insn (inst.size); |
c19d1205 | 16962 | } |
b99bd4ef | 16963 | |
e07e6e58 NC |
16964 | static char * |
16965 | output_it_inst (int cond, int mask, char * to) | |
16966 | { | |
16967 | unsigned long instruction = 0xbf00; | |
16968 | ||
16969 | mask &= 0xf; | |
16970 | instruction |= mask; | |
16971 | instruction |= cond << 4; | |
16972 | ||
16973 | if (to == NULL) | |
16974 | { | |
16975 | to = frag_more (2); | |
16976 | #ifdef OBJ_ELF | |
16977 | dwarf2_emit_insn (2); | |
16978 | #endif | |
16979 | } | |
16980 | ||
16981 | md_number_to_chars (to, instruction, 2); | |
16982 | ||
16983 | return to; | |
16984 | } | |
16985 | ||
c19d1205 ZW |
16986 | /* Tag values used in struct asm_opcode's tag field. */ |
16987 | enum opcode_tag | |
16988 | { | |
16989 | OT_unconditional, /* Instruction cannot be conditionalized. | |
16990 | The ARM condition field is still 0xE. */ | |
16991 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
16992 | and carries 0xF in its ARM condition field. */ | |
16993 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
037e8744 | 16994 | OT_csuffixF, /* Some forms of the instruction take a conditional |
477330fc RM |
16995 | suffix, others place 0xF where the condition field |
16996 | would be. */ | |
c19d1205 ZW |
16997 | OT_cinfix3, /* Instruction takes a conditional infix, |
16998 | beginning at character index 3. (In | |
16999 | unified mode, it becomes a suffix.) */ | |
088fa78e KH |
17000 | OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for |
17001 | tsts, cmps, cmns, and teqs. */ | |
e3cb604e PB |
17002 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
17003 | character index 3, even in unified mode. Used for | |
17004 | legacy instructions where suffix and infix forms | |
17005 | may be ambiguous. */ | |
c19d1205 | 17006 | OT_csuf_or_in3, /* Instruction takes either a conditional |
e3cb604e | 17007 | suffix or an infix at character index 3. */ |
c19d1205 ZW |
17008 | OT_odd_infix_unc, /* This is the unconditional variant of an |
17009 | instruction that takes a conditional infix | |
17010 | at an unusual position. In unified mode, | |
17011 | this variant will accept a suffix. */ | |
17012 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
17013 | are the conditional variants of instructions that | |
17014 | take conditional infixes in unusual positions. | |
17015 | The infix appears at character index | |
17016 | (tag - OT_odd_infix_0). These are not accepted | |
17017 | in unified mode. */ | |
17018 | }; | |
b99bd4ef | 17019 | |
c19d1205 ZW |
17020 | /* Subroutine of md_assemble, responsible for looking up the primary |
17021 | opcode from the mnemonic the user wrote. STR points to the | |
17022 | beginning of the mnemonic. | |
17023 | ||
17024 | This is not simply a hash table lookup, because of conditional | |
17025 | variants. Most instructions have conditional variants, which are | |
17026 | expressed with a _conditional affix_ to the mnemonic. If we were | |
17027 | to encode each conditional variant as a literal string in the opcode | |
17028 | table, it would have approximately 20,000 entries. | |
17029 | ||
17030 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
17031 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
17032 | instructions take the affix as an infix, notably the s-variants of | |
17033 | the arithmetic instructions. Of those instructions, all but six | |
17034 | have the infix appear after the third character of the mnemonic. | |
17035 | ||
17036 | Accordingly, the algorithm for looking up primary opcodes given | |
17037 | an identifier is: | |
17038 | ||
17039 | 1. Look up the identifier in the opcode table. | |
17040 | If we find a match, go to step U. | |
17041 | ||
17042 | 2. Look up the last two characters of the identifier in the | |
17043 | conditions table. If we find a match, look up the first N-2 | |
17044 | characters of the identifier in the opcode table. If we | |
17045 | find a match, go to step CE. | |
17046 | ||
17047 | 3. Look up the fourth and fifth characters of the identifier in | |
17048 | the conditions table. If we find a match, extract those | |
17049 | characters from the identifier, and look up the remaining | |
17050 | characters in the opcode table. If we find a match, go | |
17051 | to step CM. | |
17052 | ||
17053 | 4. Fail. | |
17054 | ||
17055 | U. Examine the tag field of the opcode structure, in case this is | |
17056 | one of the six instructions with its conditional infix in an | |
17057 | unusual place. If it is, the tag tells us where to find the | |
17058 | infix; look it up in the conditions table and set inst.cond | |
17059 | accordingly. Otherwise, this is an unconditional instruction. | |
17060 | Again set inst.cond accordingly. Return the opcode structure. | |
17061 | ||
17062 | CE. Examine the tag field to make sure this is an instruction that | |
17063 | should receive a conditional suffix. If it is not, fail. | |
17064 | Otherwise, set inst.cond from the suffix we already looked up, | |
17065 | and return the opcode structure. | |
17066 | ||
17067 | CM. Examine the tag field to make sure this is an instruction that | |
17068 | should receive a conditional infix after the third character. | |
17069 | If it is not, fail. Otherwise, undo the edits to the current | |
17070 | line of input and proceed as for case CE. */ | |
17071 | ||
17072 | static const struct asm_opcode * | |
17073 | opcode_lookup (char **str) | |
17074 | { | |
17075 | char *end, *base; | |
17076 | char *affix; | |
17077 | const struct asm_opcode *opcode; | |
17078 | const struct asm_cond *cond; | |
e3cb604e | 17079 | char save[2]; |
c19d1205 ZW |
17080 | |
17081 | /* Scan up to the end of the mnemonic, which must end in white space, | |
721a8186 | 17082 | '.' (in unified mode, or for Neon/VFP instructions), or end of string. */ |
c19d1205 | 17083 | for (base = end = *str; *end != '\0'; end++) |
721a8186 | 17084 | if (*end == ' ' || *end == '.') |
c19d1205 | 17085 | break; |
b99bd4ef | 17086 | |
c19d1205 | 17087 | if (end == base) |
c921be7d | 17088 | return NULL; |
b99bd4ef | 17089 | |
5287ad62 | 17090 | /* Handle a possible width suffix and/or Neon type suffix. */ |
c19d1205 | 17091 | if (end[0] == '.') |
b99bd4ef | 17092 | { |
5287ad62 | 17093 | int offset = 2; |
5f4273c7 | 17094 | |
267d2029 | 17095 | /* The .w and .n suffixes are only valid if the unified syntax is in |
477330fc | 17096 | use. */ |
267d2029 | 17097 | if (unified_syntax && end[1] == 'w') |
c19d1205 | 17098 | inst.size_req = 4; |
267d2029 | 17099 | else if (unified_syntax && end[1] == 'n') |
c19d1205 ZW |
17100 | inst.size_req = 2; |
17101 | else | |
477330fc | 17102 | offset = 0; |
5287ad62 JB |
17103 | |
17104 | inst.vectype.elems = 0; | |
17105 | ||
17106 | *str = end + offset; | |
b99bd4ef | 17107 | |
5f4273c7 | 17108 | if (end[offset] == '.') |
5287ad62 | 17109 | { |
267d2029 | 17110 | /* See if we have a Neon type suffix (possible in either unified or |
477330fc RM |
17111 | non-unified ARM syntax mode). */ |
17112 | if (parse_neon_type (&inst.vectype, str) == FAIL) | |
c921be7d | 17113 | return NULL; |
477330fc | 17114 | } |
5287ad62 | 17115 | else if (end[offset] != '\0' && end[offset] != ' ') |
477330fc | 17116 | return NULL; |
b99bd4ef | 17117 | } |
c19d1205 ZW |
17118 | else |
17119 | *str = end; | |
b99bd4ef | 17120 | |
c19d1205 | 17121 | /* Look for unaffixed or special-case affixed mnemonic. */ |
21d799b5 | 17122 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
477330fc | 17123 | end - base); |
c19d1205 | 17124 | if (opcode) |
b99bd4ef | 17125 | { |
c19d1205 ZW |
17126 | /* step U */ |
17127 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 17128 | { |
c19d1205 ZW |
17129 | inst.cond = COND_ALWAYS; |
17130 | return opcode; | |
b99bd4ef | 17131 | } |
b99bd4ef | 17132 | |
278df34e | 17133 | if (warn_on_deprecated && unified_syntax) |
5c3696f8 | 17134 | as_tsktsk (_("conditional infixes are deprecated in unified syntax")); |
c19d1205 | 17135 | affix = base + (opcode->tag - OT_odd_infix_0); |
21d799b5 | 17136 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
9c2799c2 | 17137 | gas_assert (cond); |
b99bd4ef | 17138 | |
c19d1205 ZW |
17139 | inst.cond = cond->value; |
17140 | return opcode; | |
17141 | } | |
b99bd4ef | 17142 | |
c19d1205 ZW |
17143 | /* Cannot have a conditional suffix on a mnemonic of less than two |
17144 | characters. */ | |
17145 | if (end - base < 3) | |
c921be7d | 17146 | return NULL; |
b99bd4ef | 17147 | |
c19d1205 ZW |
17148 | /* Look for suffixed mnemonic. */ |
17149 | affix = end - 2; | |
21d799b5 NC |
17150 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
17151 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, | |
477330fc | 17152 | affix - base); |
c19d1205 ZW |
17153 | if (opcode && cond) |
17154 | { | |
17155 | /* step CE */ | |
17156 | switch (opcode->tag) | |
17157 | { | |
e3cb604e PB |
17158 | case OT_cinfix3_legacy: |
17159 | /* Ignore conditional suffixes matched on infix only mnemonics. */ | |
17160 | break; | |
17161 | ||
c19d1205 | 17162 | case OT_cinfix3: |
088fa78e | 17163 | case OT_cinfix3_deprecated: |
c19d1205 ZW |
17164 | case OT_odd_infix_unc: |
17165 | if (!unified_syntax) | |
e3cb604e | 17166 | return 0; |
c19d1205 ZW |
17167 | /* else fall through */ |
17168 | ||
17169 | case OT_csuffix: | |
477330fc | 17170 | case OT_csuffixF: |
c19d1205 ZW |
17171 | case OT_csuf_or_in3: |
17172 | inst.cond = cond->value; | |
17173 | return opcode; | |
17174 | ||
17175 | case OT_unconditional: | |
17176 | case OT_unconditionalF: | |
dfa9f0d5 | 17177 | if (thumb_mode) |
c921be7d | 17178 | inst.cond = cond->value; |
dfa9f0d5 PB |
17179 | else |
17180 | { | |
c921be7d | 17181 | /* Delayed diagnostic. */ |
dfa9f0d5 PB |
17182 | inst.error = BAD_COND; |
17183 | inst.cond = COND_ALWAYS; | |
17184 | } | |
c19d1205 | 17185 | return opcode; |
b99bd4ef | 17186 | |
c19d1205 | 17187 | default: |
c921be7d | 17188 | return NULL; |
c19d1205 ZW |
17189 | } |
17190 | } | |
b99bd4ef | 17191 | |
c19d1205 ZW |
17192 | /* Cannot have a usual-position infix on a mnemonic of less than |
17193 | six characters (five would be a suffix). */ | |
17194 | if (end - base < 6) | |
c921be7d | 17195 | return NULL; |
b99bd4ef | 17196 | |
c19d1205 ZW |
17197 | /* Look for infixed mnemonic in the usual position. */ |
17198 | affix = base + 3; | |
21d799b5 | 17199 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
e3cb604e | 17200 | if (!cond) |
c921be7d | 17201 | return NULL; |
e3cb604e PB |
17202 | |
17203 | memcpy (save, affix, 2); | |
17204 | memmove (affix, affix + 2, (end - affix) - 2); | |
21d799b5 | 17205 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
477330fc | 17206 | (end - base) - 2); |
e3cb604e PB |
17207 | memmove (affix + 2, affix, (end - affix) - 2); |
17208 | memcpy (affix, save, 2); | |
17209 | ||
088fa78e KH |
17210 | if (opcode |
17211 | && (opcode->tag == OT_cinfix3 | |
17212 | || opcode->tag == OT_cinfix3_deprecated | |
17213 | || opcode->tag == OT_csuf_or_in3 | |
17214 | || opcode->tag == OT_cinfix3_legacy)) | |
b99bd4ef | 17215 | { |
c921be7d | 17216 | /* Step CM. */ |
278df34e | 17217 | if (warn_on_deprecated && unified_syntax |
088fa78e KH |
17218 | && (opcode->tag == OT_cinfix3 |
17219 | || opcode->tag == OT_cinfix3_deprecated)) | |
5c3696f8 | 17220 | as_tsktsk (_("conditional infixes are deprecated in unified syntax")); |
c19d1205 ZW |
17221 | |
17222 | inst.cond = cond->value; | |
17223 | return opcode; | |
b99bd4ef NC |
17224 | } |
17225 | ||
c921be7d | 17226 | return NULL; |
b99bd4ef NC |
17227 | } |
17228 | ||
e07e6e58 NC |
17229 | /* This function generates an initial IT instruction, leaving its block |
17230 | virtually open for the new instructions. Eventually, | |
17231 | the mask will be updated by now_it_add_mask () each time | |
17232 | a new instruction needs to be included in the IT block. | |
17233 | Finally, the block is closed with close_automatic_it_block (). | |
17234 | The block closure can be requested either from md_assemble (), | |
17235 | a tencode (), or due to a label hook. */ | |
17236 | ||
17237 | static void | |
17238 | new_automatic_it_block (int cond) | |
17239 | { | |
17240 | now_it.state = AUTOMATIC_IT_BLOCK; | |
17241 | now_it.mask = 0x18; | |
17242 | now_it.cc = cond; | |
17243 | now_it.block_length = 1; | |
cd000bff | 17244 | mapping_state (MAP_THUMB); |
e07e6e58 | 17245 | now_it.insn = output_it_inst (cond, now_it.mask, NULL); |
5a01bb1d MGD |
17246 | now_it.warn_deprecated = FALSE; |
17247 | now_it.insn_cond = TRUE; | |
e07e6e58 NC |
17248 | } |
17249 | ||
17250 | /* Close an automatic IT block. | |
17251 | See comments in new_automatic_it_block (). */ | |
17252 | ||
17253 | static void | |
17254 | close_automatic_it_block (void) | |
17255 | { | |
17256 | now_it.mask = 0x10; | |
17257 | now_it.block_length = 0; | |
17258 | } | |
17259 | ||
17260 | /* Update the mask of the current automatically-generated IT | |
17261 | instruction. See comments in new_automatic_it_block (). */ | |
17262 | ||
17263 | static void | |
17264 | now_it_add_mask (int cond) | |
17265 | { | |
17266 | #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit))) | |
17267 | #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \ | |
477330fc | 17268 | | ((bitvalue) << (nbit))) |
e07e6e58 | 17269 | const int resulting_bit = (cond & 1); |
c921be7d | 17270 | |
e07e6e58 NC |
17271 | now_it.mask &= 0xf; |
17272 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
477330fc RM |
17273 | resulting_bit, |
17274 | (5 - now_it.block_length)); | |
e07e6e58 | 17275 | now_it.mask = SET_BIT_VALUE (now_it.mask, |
477330fc RM |
17276 | 1, |
17277 | ((5 - now_it.block_length) - 1) ); | |
e07e6e58 NC |
17278 | output_it_inst (now_it.cc, now_it.mask, now_it.insn); |
17279 | ||
17280 | #undef CLEAR_BIT | |
17281 | #undef SET_BIT_VALUE | |
e07e6e58 NC |
17282 | } |
17283 | ||
17284 | /* The IT blocks handling machinery is accessed through the these functions: | |
17285 | it_fsm_pre_encode () from md_assemble () | |
17286 | set_it_insn_type () optional, from the tencode functions | |
17287 | set_it_insn_type_last () ditto | |
17288 | in_it_block () ditto | |
17289 | it_fsm_post_encode () from md_assemble () | |
17290 | force_automatic_it_block_close () from label habdling functions | |
17291 | ||
17292 | Rationale: | |
17293 | 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), | |
477330fc RM |
17294 | initializing the IT insn type with a generic initial value depending |
17295 | on the inst.condition. | |
e07e6e58 | 17296 | 2) During the tencode function, two things may happen: |
477330fc RM |
17297 | a) The tencode function overrides the IT insn type by |
17298 | calling either set_it_insn_type (type) or set_it_insn_type_last (). | |
17299 | b) The tencode function queries the IT block state by | |
17300 | calling in_it_block () (i.e. to determine narrow/not narrow mode). | |
17301 | ||
17302 | Both set_it_insn_type and in_it_block run the internal FSM state | |
17303 | handling function (handle_it_state), because: a) setting the IT insn | |
17304 | type may incur in an invalid state (exiting the function), | |
17305 | and b) querying the state requires the FSM to be updated. | |
17306 | Specifically we want to avoid creating an IT block for conditional | |
17307 | branches, so it_fsm_pre_encode is actually a guess and we can't | |
17308 | determine whether an IT block is required until the tencode () routine | |
17309 | has decided what type of instruction this actually it. | |
17310 | Because of this, if set_it_insn_type and in_it_block have to be used, | |
17311 | set_it_insn_type has to be called first. | |
17312 | ||
17313 | set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that | |
17314 | determines the insn IT type depending on the inst.cond code. | |
17315 | When a tencode () routine encodes an instruction that can be | |
17316 | either outside an IT block, or, in the case of being inside, has to be | |
17317 | the last one, set_it_insn_type_last () will determine the proper | |
17318 | IT instruction type based on the inst.cond code. Otherwise, | |
17319 | set_it_insn_type can be called for overriding that logic or | |
17320 | for covering other cases. | |
17321 | ||
17322 | Calling handle_it_state () may not transition the IT block state to | |
17323 | OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be | |
17324 | still queried. Instead, if the FSM determines that the state should | |
17325 | be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed | |
17326 | after the tencode () function: that's what it_fsm_post_encode () does. | |
17327 | ||
17328 | Since in_it_block () calls the state handling function to get an | |
17329 | updated state, an error may occur (due to invalid insns combination). | |
17330 | In that case, inst.error is set. | |
17331 | Therefore, inst.error has to be checked after the execution of | |
17332 | the tencode () routine. | |
e07e6e58 NC |
17333 | |
17334 | 3) Back in md_assemble(), it_fsm_post_encode () is called to commit | |
477330fc RM |
17335 | any pending state change (if any) that didn't take place in |
17336 | handle_it_state () as explained above. */ | |
e07e6e58 NC |
17337 | |
17338 | static void | |
17339 | it_fsm_pre_encode (void) | |
17340 | { | |
17341 | if (inst.cond != COND_ALWAYS) | |
17342 | inst.it_insn_type = INSIDE_IT_INSN; | |
17343 | else | |
17344 | inst.it_insn_type = OUTSIDE_IT_INSN; | |
17345 | ||
17346 | now_it.state_handled = 0; | |
17347 | } | |
17348 | ||
17349 | /* IT state FSM handling function. */ | |
17350 | ||
17351 | static int | |
17352 | handle_it_state (void) | |
17353 | { | |
17354 | now_it.state_handled = 1; | |
5a01bb1d | 17355 | now_it.insn_cond = FALSE; |
e07e6e58 NC |
17356 | |
17357 | switch (now_it.state) | |
17358 | { | |
17359 | case OUTSIDE_IT_BLOCK: | |
17360 | switch (inst.it_insn_type) | |
17361 | { | |
17362 | case OUTSIDE_IT_INSN: | |
17363 | break; | |
17364 | ||
17365 | case INSIDE_IT_INSN: | |
17366 | case INSIDE_IT_LAST_INSN: | |
17367 | if (thumb_mode == 0) | |
17368 | { | |
c921be7d | 17369 | if (unified_syntax |
e07e6e58 NC |
17370 | && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM)) |
17371 | as_tsktsk (_("Warning: conditional outside an IT block"\ | |
17372 | " for Thumb.")); | |
17373 | } | |
17374 | else | |
17375 | { | |
17376 | if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB) | |
17377 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)) | |
17378 | { | |
17379 | /* Automatically generate the IT instruction. */ | |
17380 | new_automatic_it_block (inst.cond); | |
17381 | if (inst.it_insn_type == INSIDE_IT_LAST_INSN) | |
17382 | close_automatic_it_block (); | |
17383 | } | |
17384 | else | |
17385 | { | |
17386 | inst.error = BAD_OUT_IT; | |
17387 | return FAIL; | |
17388 | } | |
17389 | } | |
17390 | break; | |
17391 | ||
17392 | case IF_INSIDE_IT_LAST_INSN: | |
17393 | case NEUTRAL_IT_INSN: | |
17394 | break; | |
17395 | ||
17396 | case IT_INSN: | |
17397 | now_it.state = MANUAL_IT_BLOCK; | |
17398 | now_it.block_length = 0; | |
17399 | break; | |
17400 | } | |
17401 | break; | |
17402 | ||
17403 | case AUTOMATIC_IT_BLOCK: | |
17404 | /* Three things may happen now: | |
17405 | a) We should increment current it block size; | |
17406 | b) We should close current it block (closing insn or 4 insns); | |
17407 | c) We should close current it block and start a new one (due | |
17408 | to incompatible conditions or | |
17409 | 4 insns-length block reached). */ | |
17410 | ||
17411 | switch (inst.it_insn_type) | |
17412 | { | |
17413 | case OUTSIDE_IT_INSN: | |
17414 | /* The closure of the block shall happen immediatelly, | |
17415 | so any in_it_block () call reports the block as closed. */ | |
17416 | force_automatic_it_block_close (); | |
17417 | break; | |
17418 | ||
17419 | case INSIDE_IT_INSN: | |
17420 | case INSIDE_IT_LAST_INSN: | |
17421 | case IF_INSIDE_IT_LAST_INSN: | |
17422 | now_it.block_length++; | |
17423 | ||
17424 | if (now_it.block_length > 4 | |
17425 | || !now_it_compatible (inst.cond)) | |
17426 | { | |
17427 | force_automatic_it_block_close (); | |
17428 | if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN) | |
17429 | new_automatic_it_block (inst.cond); | |
17430 | } | |
17431 | else | |
17432 | { | |
5a01bb1d | 17433 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
17434 | now_it_add_mask (inst.cond); |
17435 | } | |
17436 | ||
17437 | if (now_it.state == AUTOMATIC_IT_BLOCK | |
17438 | && (inst.it_insn_type == INSIDE_IT_LAST_INSN | |
17439 | || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN)) | |
17440 | close_automatic_it_block (); | |
17441 | break; | |
17442 | ||
17443 | case NEUTRAL_IT_INSN: | |
17444 | now_it.block_length++; | |
5a01bb1d | 17445 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
17446 | |
17447 | if (now_it.block_length > 4) | |
17448 | force_automatic_it_block_close (); | |
17449 | else | |
17450 | now_it_add_mask (now_it.cc & 1); | |
17451 | break; | |
17452 | ||
17453 | case IT_INSN: | |
17454 | close_automatic_it_block (); | |
17455 | now_it.state = MANUAL_IT_BLOCK; | |
17456 | break; | |
17457 | } | |
17458 | break; | |
17459 | ||
17460 | case MANUAL_IT_BLOCK: | |
17461 | { | |
17462 | /* Check conditional suffixes. */ | |
17463 | const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1; | |
17464 | int is_last; | |
17465 | now_it.mask <<= 1; | |
17466 | now_it.mask &= 0x1f; | |
17467 | is_last = (now_it.mask == 0x10); | |
5a01bb1d | 17468 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
17469 | |
17470 | switch (inst.it_insn_type) | |
17471 | { | |
17472 | case OUTSIDE_IT_INSN: | |
17473 | inst.error = BAD_NOT_IT; | |
17474 | return FAIL; | |
17475 | ||
17476 | case INSIDE_IT_INSN: | |
17477 | if (cond != inst.cond) | |
17478 | { | |
17479 | inst.error = BAD_IT_COND; | |
17480 | return FAIL; | |
17481 | } | |
17482 | break; | |
17483 | ||
17484 | case INSIDE_IT_LAST_INSN: | |
17485 | case IF_INSIDE_IT_LAST_INSN: | |
17486 | if (cond != inst.cond) | |
17487 | { | |
17488 | inst.error = BAD_IT_COND; | |
17489 | return FAIL; | |
17490 | } | |
17491 | if (!is_last) | |
17492 | { | |
17493 | inst.error = BAD_BRANCH; | |
17494 | return FAIL; | |
17495 | } | |
17496 | break; | |
17497 | ||
17498 | case NEUTRAL_IT_INSN: | |
17499 | /* The BKPT instruction is unconditional even in an IT block. */ | |
17500 | break; | |
17501 | ||
17502 | case IT_INSN: | |
17503 | inst.error = BAD_IT_IT; | |
17504 | return FAIL; | |
17505 | } | |
17506 | } | |
17507 | break; | |
17508 | } | |
17509 | ||
17510 | return SUCCESS; | |
17511 | } | |
17512 | ||
5a01bb1d MGD |
17513 | struct depr_insn_mask |
17514 | { | |
17515 | unsigned long pattern; | |
17516 | unsigned long mask; | |
17517 | const char* description; | |
17518 | }; | |
17519 | ||
17520 | /* List of 16-bit instruction patterns deprecated in an IT block in | |
17521 | ARMv8. */ | |
17522 | static const struct depr_insn_mask depr_it_insns[] = { | |
17523 | { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") }, | |
17524 | { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") }, | |
17525 | { 0xa000, 0xb800, N_("ADR") }, | |
17526 | { 0x4800, 0xf800, N_("Literal loads") }, | |
17527 | { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") }, | |
17528 | { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") }, | |
c8de034b JW |
17529 | /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue' |
17530 | field in asm_opcode. 'tvalue' is used at the stage this check happen. */ | |
17531 | { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") }, | |
5a01bb1d MGD |
17532 | { 0, 0, NULL } |
17533 | }; | |
17534 | ||
e07e6e58 NC |
17535 | static void |
17536 | it_fsm_post_encode (void) | |
17537 | { | |
17538 | int is_last; | |
17539 | ||
17540 | if (!now_it.state_handled) | |
17541 | handle_it_state (); | |
17542 | ||
5a01bb1d MGD |
17543 | if (now_it.insn_cond |
17544 | && !now_it.warn_deprecated | |
17545 | && warn_on_deprecated | |
17546 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
17547 | { | |
17548 | if (inst.instruction >= 0x10000) | |
17549 | { | |
5c3696f8 | 17550 | as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are " |
5a01bb1d MGD |
17551 | "deprecated in ARMv8")); |
17552 | now_it.warn_deprecated = TRUE; | |
17553 | } | |
17554 | else | |
17555 | { | |
17556 | const struct depr_insn_mask *p = depr_it_insns; | |
17557 | ||
17558 | while (p->mask != 0) | |
17559 | { | |
17560 | if ((inst.instruction & p->mask) == p->pattern) | |
17561 | { | |
5c3696f8 | 17562 | as_tsktsk (_("IT blocks containing 16-bit Thumb instructions " |
5a01bb1d MGD |
17563 | "of the following class are deprecated in ARMv8: " |
17564 | "%s"), p->description); | |
17565 | now_it.warn_deprecated = TRUE; | |
17566 | break; | |
17567 | } | |
17568 | ||
17569 | ++p; | |
17570 | } | |
17571 | } | |
17572 | ||
17573 | if (now_it.block_length > 1) | |
17574 | { | |
5c3696f8 | 17575 | as_tsktsk (_("IT blocks containing more than one conditional " |
0a8897c7 | 17576 | "instruction are deprecated in ARMv8")); |
5a01bb1d MGD |
17577 | now_it.warn_deprecated = TRUE; |
17578 | } | |
17579 | } | |
17580 | ||
e07e6e58 NC |
17581 | is_last = (now_it.mask == 0x10); |
17582 | if (is_last) | |
17583 | { | |
17584 | now_it.state = OUTSIDE_IT_BLOCK; | |
17585 | now_it.mask = 0; | |
17586 | } | |
17587 | } | |
17588 | ||
17589 | static void | |
17590 | force_automatic_it_block_close (void) | |
17591 | { | |
17592 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
17593 | { | |
17594 | close_automatic_it_block (); | |
17595 | now_it.state = OUTSIDE_IT_BLOCK; | |
17596 | now_it.mask = 0; | |
17597 | } | |
17598 | } | |
17599 | ||
17600 | static int | |
17601 | in_it_block (void) | |
17602 | { | |
17603 | if (!now_it.state_handled) | |
17604 | handle_it_state (); | |
17605 | ||
17606 | return now_it.state != OUTSIDE_IT_BLOCK; | |
17607 | } | |
17608 | ||
c19d1205 ZW |
17609 | void |
17610 | md_assemble (char *str) | |
b99bd4ef | 17611 | { |
c19d1205 ZW |
17612 | char *p = str; |
17613 | const struct asm_opcode * opcode; | |
b99bd4ef | 17614 | |
c19d1205 ZW |
17615 | /* Align the previous label if needed. */ |
17616 | if (last_label_seen != NULL) | |
b99bd4ef | 17617 | { |
c19d1205 ZW |
17618 | symbol_set_frag (last_label_seen, frag_now); |
17619 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
17620 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
17621 | } |
17622 | ||
c19d1205 ZW |
17623 | memset (&inst, '\0', sizeof (inst)); |
17624 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 17625 | |
c19d1205 ZW |
17626 | opcode = opcode_lookup (&p); |
17627 | if (!opcode) | |
b99bd4ef | 17628 | { |
c19d1205 | 17629 | /* It wasn't an instruction, but it might be a register alias of |
dcbf9037 | 17630 | the form alias .req reg, or a Neon .dn/.qn directive. */ |
c921be7d | 17631 | if (! create_register_alias (str, p) |
477330fc | 17632 | && ! create_neon_reg_alias (str, p)) |
c19d1205 | 17633 | as_bad (_("bad instruction `%s'"), str); |
b99bd4ef | 17634 | |
b99bd4ef NC |
17635 | return; |
17636 | } | |
17637 | ||
278df34e | 17638 | if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated) |
5c3696f8 | 17639 | as_tsktsk (_("s suffix on comparison instruction is deprecated")); |
088fa78e | 17640 | |
037e8744 JB |
17641 | /* The value which unconditional instructions should have in place of the |
17642 | condition field. */ | |
17643 | inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; | |
17644 | ||
c19d1205 | 17645 | if (thumb_mode) |
b99bd4ef | 17646 | { |
e74cfd16 | 17647 | arm_feature_set variant; |
8f06b2d8 PB |
17648 | |
17649 | variant = cpu_variant; | |
17650 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
e74cfd16 PB |
17651 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
17652 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); | |
c19d1205 | 17653 | /* Check that this instruction is supported for this CPU. */ |
62b3e311 PB |
17654 | if (!opcode->tvariant |
17655 | || (thumb_mode == 1 | |
17656 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) | |
b99bd4ef | 17657 | { |
bf3eeda7 | 17658 | as_bad (_("selected processor does not support Thumb mode `%s'"), str); |
b99bd4ef NC |
17659 | return; |
17660 | } | |
c19d1205 ZW |
17661 | if (inst.cond != COND_ALWAYS && !unified_syntax |
17662 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 17663 | { |
c19d1205 | 17664 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
17665 | return; |
17666 | } | |
17667 | ||
752d5da4 | 17668 | if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)) |
076d447c | 17669 | { |
7e806470 | 17670 | if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23 |
752d5da4 NC |
17671 | && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr) |
17672 | || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier))) | |
17673 | { | |
17674 | /* Two things are addressed here. | |
17675 | 1) Implicit require narrow instructions on Thumb-1. | |
17676 | This avoids relaxation accidentally introducing Thumb-2 | |
17677 | instructions. | |
17678 | 2) Reject wide instructions in non Thumb-2 cores. */ | |
17679 | if (inst.size_req == 0) | |
17680 | inst.size_req = 2; | |
17681 | else if (inst.size_req == 4) | |
17682 | { | |
bf3eeda7 | 17683 | as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str); |
752d5da4 NC |
17684 | return; |
17685 | } | |
17686 | } | |
076d447c PB |
17687 | } |
17688 | ||
c19d1205 ZW |
17689 | inst.instruction = opcode->tvalue; |
17690 | ||
5be8be5d | 17691 | if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE)) |
477330fc RM |
17692 | { |
17693 | /* Prepare the it_insn_type for those encodings that don't set | |
17694 | it. */ | |
17695 | it_fsm_pre_encode (); | |
c19d1205 | 17696 | |
477330fc | 17697 | opcode->tencode (); |
e07e6e58 | 17698 | |
477330fc RM |
17699 | it_fsm_post_encode (); |
17700 | } | |
e27ec89e | 17701 | |
0110f2b8 | 17702 | if (!(inst.error || inst.relax)) |
b99bd4ef | 17703 | { |
9c2799c2 | 17704 | gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
c19d1205 ZW |
17705 | inst.size = (inst.instruction > 0xffff ? 4 : 2); |
17706 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 17707 | { |
c19d1205 | 17708 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
17709 | return; |
17710 | } | |
17711 | } | |
076d447c PB |
17712 | |
17713 | /* Something has gone badly wrong if we try to relax a fixed size | |
477330fc | 17714 | instruction. */ |
9c2799c2 | 17715 | gas_assert (inst.size_req == 0 || !inst.relax); |
076d447c | 17716 | |
e74cfd16 PB |
17717 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
17718 | *opcode->tvariant); | |
ee065d83 | 17719 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
708587a4 | 17720 | set those bits when Thumb-2 32-bit instructions are seen. ie. |
7e806470 | 17721 | anything other than bl/blx and v6-M instructions. |
3cfdb781 TG |
17722 | The impact of relaxable instructions will be considered later after we |
17723 | finish all relaxation. */ | |
17724 | if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) | |
e07e6e58 NC |
17725 | && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) |
17726 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))) | |
e74cfd16 PB |
17727 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
17728 | arm_ext_v6t2); | |
cd000bff | 17729 | |
88714cb8 DG |
17730 | check_neon_suffixes; |
17731 | ||
cd000bff | 17732 | if (!inst.error) |
c877a2f2 NC |
17733 | { |
17734 | mapping_state (MAP_THUMB); | |
17735 | } | |
c19d1205 | 17736 | } |
3e9e4fcf | 17737 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 | 17738 | { |
845b51d6 PB |
17739 | bfd_boolean is_bx; |
17740 | ||
17741 | /* bx is allowed on v5 cores, and sometimes on v4 cores. */ | |
17742 | is_bx = (opcode->aencode == do_bx); | |
17743 | ||
c19d1205 | 17744 | /* Check that this instruction is supported for this CPU. */ |
845b51d6 PB |
17745 | if (!(is_bx && fix_v4bx) |
17746 | && !(opcode->avariant && | |
17747 | ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))) | |
b99bd4ef | 17748 | { |
bf3eeda7 | 17749 | as_bad (_("selected processor does not support ARM mode `%s'"), str); |
c19d1205 | 17750 | return; |
b99bd4ef | 17751 | } |
c19d1205 | 17752 | if (inst.size_req) |
b99bd4ef | 17753 | { |
c19d1205 ZW |
17754 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
17755 | return; | |
b99bd4ef NC |
17756 | } |
17757 | ||
c19d1205 ZW |
17758 | inst.instruction = opcode->avalue; |
17759 | if (opcode->tag == OT_unconditionalF) | |
17760 | inst.instruction |= 0xF << 28; | |
17761 | else | |
17762 | inst.instruction |= inst.cond << 28; | |
17763 | inst.size = INSN_SIZE; | |
5be8be5d | 17764 | if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE)) |
477330fc RM |
17765 | { |
17766 | it_fsm_pre_encode (); | |
17767 | opcode->aencode (); | |
17768 | it_fsm_post_encode (); | |
17769 | } | |
ee065d83 | 17770 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
477330fc | 17771 | on a hypothetical non-thumb v5 core. */ |
845b51d6 | 17772 | if (is_bx) |
e74cfd16 | 17773 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); |
ee065d83 | 17774 | else |
e74cfd16 PB |
17775 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
17776 | *opcode->avariant); | |
88714cb8 DG |
17777 | |
17778 | check_neon_suffixes; | |
17779 | ||
cd000bff | 17780 | if (!inst.error) |
c877a2f2 NC |
17781 | { |
17782 | mapping_state (MAP_ARM); | |
17783 | } | |
b99bd4ef | 17784 | } |
3e9e4fcf JB |
17785 | else |
17786 | { | |
17787 | as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " | |
17788 | "-- `%s'"), str); | |
17789 | return; | |
17790 | } | |
c19d1205 ZW |
17791 | output_inst (str); |
17792 | } | |
b99bd4ef | 17793 | |
e07e6e58 NC |
17794 | static void |
17795 | check_it_blocks_finished (void) | |
17796 | { | |
17797 | #ifdef OBJ_ELF | |
17798 | asection *sect; | |
17799 | ||
17800 | for (sect = stdoutput->sections; sect != NULL; sect = sect->next) | |
17801 | if (seg_info (sect)->tc_segment_info_data.current_it.state | |
17802 | == MANUAL_IT_BLOCK) | |
17803 | { | |
17804 | as_warn (_("section '%s' finished with an open IT block."), | |
17805 | sect->name); | |
17806 | } | |
17807 | #else | |
17808 | if (now_it.state == MANUAL_IT_BLOCK) | |
17809 | as_warn (_("file finished with an open IT block.")); | |
17810 | #endif | |
17811 | } | |
17812 | ||
c19d1205 ZW |
17813 | /* Various frobbings of labels and their addresses. */ |
17814 | ||
17815 | void | |
17816 | arm_start_line_hook (void) | |
17817 | { | |
17818 | last_label_seen = NULL; | |
b99bd4ef NC |
17819 | } |
17820 | ||
c19d1205 ZW |
17821 | void |
17822 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 17823 | { |
c19d1205 | 17824 | last_label_seen = sym; |
b99bd4ef | 17825 | |
c19d1205 | 17826 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 17827 | |
c19d1205 ZW |
17828 | #if defined OBJ_COFF || defined OBJ_ELF |
17829 | ARM_SET_INTERWORK (sym, support_interwork); | |
17830 | #endif | |
b99bd4ef | 17831 | |
e07e6e58 NC |
17832 | force_automatic_it_block_close (); |
17833 | ||
5f4273c7 | 17834 | /* Note - do not allow local symbols (.Lxxx) to be labelled |
c19d1205 ZW |
17835 | as Thumb functions. This is because these labels, whilst |
17836 | they exist inside Thumb code, are not the entry points for | |
17837 | possible ARM->Thumb calls. Also, these labels can be used | |
17838 | as part of a computed goto or switch statement. eg gcc | |
17839 | can generate code that looks like this: | |
b99bd4ef | 17840 | |
c19d1205 ZW |
17841 | ldr r2, [pc, .Laaa] |
17842 | lsl r3, r3, #2 | |
17843 | ldr r2, [r3, r2] | |
17844 | mov pc, r2 | |
b99bd4ef | 17845 | |
c19d1205 ZW |
17846 | .Lbbb: .word .Lxxx |
17847 | .Lccc: .word .Lyyy | |
17848 | ..etc... | |
17849 | .Laaa: .word Lbbb | |
b99bd4ef | 17850 | |
c19d1205 ZW |
17851 | The first instruction loads the address of the jump table. |
17852 | The second instruction converts a table index into a byte offset. | |
17853 | The third instruction gets the jump address out of the table. | |
17854 | The fourth instruction performs the jump. | |
b99bd4ef | 17855 | |
c19d1205 ZW |
17856 | If the address stored at .Laaa is that of a symbol which has the |
17857 | Thumb_Func bit set, then the linker will arrange for this address | |
17858 | to have the bottom bit set, which in turn would mean that the | |
17859 | address computation performed by the third instruction would end | |
17860 | up with the bottom bit set. Since the ARM is capable of unaligned | |
17861 | word loads, the instruction would then load the incorrect address | |
17862 | out of the jump table, and chaos would ensue. */ | |
17863 | if (label_is_thumb_function_name | |
17864 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
17865 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 17866 | { |
c19d1205 ZW |
17867 | /* When the address of a Thumb function is taken the bottom |
17868 | bit of that address should be set. This will allow | |
17869 | interworking between Arm and Thumb functions to work | |
17870 | correctly. */ | |
b99bd4ef | 17871 | |
c19d1205 | 17872 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 17873 | |
c19d1205 | 17874 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 17875 | } |
07a53e5c | 17876 | |
07a53e5c | 17877 | dwarf2_emit_label (sym); |
b99bd4ef NC |
17878 | } |
17879 | ||
c921be7d | 17880 | bfd_boolean |
c19d1205 | 17881 | arm_data_in_code (void) |
b99bd4ef | 17882 | { |
c19d1205 | 17883 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 17884 | { |
c19d1205 ZW |
17885 | *input_line_pointer = '/'; |
17886 | input_line_pointer += 5; | |
17887 | *input_line_pointer = 0; | |
c921be7d | 17888 | return TRUE; |
b99bd4ef NC |
17889 | } |
17890 | ||
c921be7d | 17891 | return FALSE; |
b99bd4ef NC |
17892 | } |
17893 | ||
c19d1205 ZW |
17894 | char * |
17895 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 17896 | { |
c19d1205 | 17897 | int len; |
b99bd4ef | 17898 | |
c19d1205 ZW |
17899 | if (thumb_mode && (len = strlen (name)) > 5 |
17900 | && streq (name + len - 5, "/data")) | |
17901 | *(name + len - 5) = 0; | |
b99bd4ef | 17902 | |
c19d1205 | 17903 | return name; |
b99bd4ef | 17904 | } |
c19d1205 ZW |
17905 | \f |
17906 | /* Table of all register names defined by default. The user can | |
17907 | define additional names with .req. Note that all register names | |
17908 | should appear in both upper and lowercase variants. Some registers | |
17909 | also have mixed-case names. */ | |
b99bd4ef | 17910 | |
dcbf9037 | 17911 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } |
c19d1205 | 17912 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) |
5287ad62 | 17913 | #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) |
c19d1205 ZW |
17914 | #define REGSET(p,t) \ |
17915 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
17916 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
17917 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
17918 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
5287ad62 JB |
17919 | #define REGSETH(p,t) \ |
17920 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ | |
17921 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ | |
17922 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ | |
17923 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) | |
17924 | #define REGSET2(p,t) \ | |
17925 | REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ | |
17926 | REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ | |
17927 | REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ | |
17928 | REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) | |
90ec0d68 MGD |
17929 | #define SPLRBANK(base,bank,t) \ |
17930 | REGDEF(lr_##bank, 768|((base+0)<<16), t), \ | |
17931 | REGDEF(sp_##bank, 768|((base+1)<<16), t), \ | |
17932 | REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \ | |
17933 | REGDEF(LR_##bank, 768|((base+0)<<16), t), \ | |
17934 | REGDEF(SP_##bank, 768|((base+1)<<16), t), \ | |
17935 | REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t) | |
7ed4c4c5 | 17936 | |
c19d1205 | 17937 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 17938 | { |
c19d1205 ZW |
17939 | /* ARM integer registers. */ |
17940 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 17941 | |
c19d1205 ZW |
17942 | /* ATPCS synonyms. */ |
17943 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
17944 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
17945 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 17946 | |
c19d1205 ZW |
17947 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
17948 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
17949 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 17950 | |
c19d1205 ZW |
17951 | /* Well-known aliases. */ |
17952 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
17953 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
17954 | ||
17955 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
17956 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
17957 | ||
17958 | /* Coprocessor numbers. */ | |
17959 | REGSET(p, CP), REGSET(P, CP), | |
17960 | ||
17961 | /* Coprocessor register numbers. The "cr" variants are for backward | |
17962 | compatibility. */ | |
17963 | REGSET(c, CN), REGSET(C, CN), | |
17964 | REGSET(cr, CN), REGSET(CR, CN), | |
17965 | ||
90ec0d68 MGD |
17966 | /* ARM banked registers. */ |
17967 | REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB), | |
17968 | REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB), | |
17969 | REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB), | |
17970 | REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB), | |
17971 | REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB), | |
17972 | REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB), | |
17973 | REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB), | |
17974 | ||
17975 | REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB), | |
17976 | REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB), | |
17977 | REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB), | |
17978 | REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB), | |
17979 | REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB), | |
1472d06f | 17980 | REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB), |
90ec0d68 MGD |
17981 | REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB), |
17982 | REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB), | |
17983 | ||
17984 | SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB), | |
17985 | SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB), | |
17986 | SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB), | |
17987 | SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB), | |
17988 | SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB), | |
17989 | REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB), | |
17990 | REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB), | |
fa94de6b | 17991 | REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB), |
90ec0d68 MGD |
17992 | REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB), |
17993 | ||
c19d1205 ZW |
17994 | /* FPA registers. */ |
17995 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
17996 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
17997 | ||
17998 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
17999 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
18000 | ||
18001 | /* VFP SP registers. */ | |
5287ad62 JB |
18002 | REGSET(s,VFS), REGSET(S,VFS), |
18003 | REGSETH(s,VFS), REGSETH(S,VFS), | |
c19d1205 ZW |
18004 | |
18005 | /* VFP DP Registers. */ | |
5287ad62 JB |
18006 | REGSET(d,VFD), REGSET(D,VFD), |
18007 | /* Extra Neon DP registers. */ | |
18008 | REGSETH(d,VFD), REGSETH(D,VFD), | |
18009 | ||
18010 | /* Neon QP registers. */ | |
18011 | REGSET2(q,NQ), REGSET2(Q,NQ), | |
c19d1205 ZW |
18012 | |
18013 | /* VFP control registers. */ | |
18014 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
18015 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
cd2cf30b PB |
18016 | REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), |
18017 | REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), | |
18018 | REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), | |
18019 | REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), | |
c19d1205 ZW |
18020 | |
18021 | /* Maverick DSP coprocessor registers. */ | |
18022 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
18023 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
18024 | ||
18025 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
18026 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
18027 | REGDEF(dspsc,0,DSPSC), | |
18028 | ||
18029 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
18030 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
18031 | REGDEF(DSPSC,0,DSPSC), | |
18032 | ||
18033 | /* iWMMXt data registers - p0, c0-15. */ | |
18034 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
18035 | ||
18036 | /* iWMMXt control registers - p1, c0-3. */ | |
18037 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
18038 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
18039 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
18040 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
18041 | ||
18042 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
18043 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
18044 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
18045 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
18046 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
18047 | ||
18048 | /* XScale accumulator registers. */ | |
18049 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
18050 | }; | |
18051 | #undef REGDEF | |
18052 | #undef REGNUM | |
18053 | #undef REGSET | |
7ed4c4c5 | 18054 | |
c19d1205 ZW |
18055 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
18056 | within psr_required_here. */ | |
18057 | static const struct asm_psr psrs[] = | |
18058 | { | |
18059 | /* Backward compatibility notation. Note that "all" is no longer | |
18060 | truly all possible PSR bits. */ | |
18061 | {"all", PSR_c | PSR_f}, | |
18062 | {"flg", PSR_f}, | |
18063 | {"ctl", PSR_c}, | |
18064 | ||
18065 | /* Individual flags. */ | |
18066 | {"f", PSR_f}, | |
18067 | {"c", PSR_c}, | |
18068 | {"x", PSR_x}, | |
18069 | {"s", PSR_s}, | |
59b42a0d | 18070 | |
c19d1205 ZW |
18071 | /* Combinations of flags. */ |
18072 | {"fs", PSR_f | PSR_s}, | |
18073 | {"fx", PSR_f | PSR_x}, | |
18074 | {"fc", PSR_f | PSR_c}, | |
18075 | {"sf", PSR_s | PSR_f}, | |
18076 | {"sx", PSR_s | PSR_x}, | |
18077 | {"sc", PSR_s | PSR_c}, | |
18078 | {"xf", PSR_x | PSR_f}, | |
18079 | {"xs", PSR_x | PSR_s}, | |
18080 | {"xc", PSR_x | PSR_c}, | |
18081 | {"cf", PSR_c | PSR_f}, | |
18082 | {"cs", PSR_c | PSR_s}, | |
18083 | {"cx", PSR_c | PSR_x}, | |
18084 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
18085 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
18086 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
18087 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
18088 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
18089 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
18090 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
18091 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
18092 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
18093 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
18094 | {"scf", PSR_s | PSR_c | PSR_f}, | |
18095 | {"scx", PSR_s | PSR_c | PSR_x}, | |
18096 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
18097 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
18098 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
18099 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
18100 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
18101 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
18102 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
18103 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
18104 | {"csf", PSR_c | PSR_s | PSR_f}, | |
18105 | {"csx", PSR_c | PSR_s | PSR_x}, | |
18106 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
18107 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
18108 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
18109 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
18110 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
18111 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
18112 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
18113 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
18114 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
18115 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
18116 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
18117 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
18118 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
18119 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
18120 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
18121 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
18122 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
18123 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
18124 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
18125 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
18126 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
18127 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
18128 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
18129 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
18130 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
18131 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
18132 | }; | |
18133 | ||
62b3e311 PB |
18134 | /* Table of V7M psr names. */ |
18135 | static const struct asm_psr v7m_psrs[] = | |
18136 | { | |
2b744c99 PB |
18137 | {"apsr", 0 }, {"APSR", 0 }, |
18138 | {"iapsr", 1 }, {"IAPSR", 1 }, | |
18139 | {"eapsr", 2 }, {"EAPSR", 2 }, | |
18140 | {"psr", 3 }, {"PSR", 3 }, | |
18141 | {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, | |
18142 | {"ipsr", 5 }, {"IPSR", 5 }, | |
18143 | {"epsr", 6 }, {"EPSR", 6 }, | |
18144 | {"iepsr", 7 }, {"IEPSR", 7 }, | |
18145 | {"msp", 8 }, {"MSP", 8 }, | |
18146 | {"psp", 9 }, {"PSP", 9 }, | |
18147 | {"primask", 16}, {"PRIMASK", 16}, | |
18148 | {"basepri", 17}, {"BASEPRI", 17}, | |
00bbc0bd NC |
18149 | {"basepri_max", 18}, {"BASEPRI_MAX", 18}, |
18150 | {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */ | |
2b744c99 PB |
18151 | {"faultmask", 19}, {"FAULTMASK", 19}, |
18152 | {"control", 20}, {"CONTROL", 20} | |
62b3e311 PB |
18153 | }; |
18154 | ||
c19d1205 ZW |
18155 | /* Table of all shift-in-operand names. */ |
18156 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 18157 | { |
c19d1205 ZW |
18158 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
18159 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
18160 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
18161 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
18162 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
18163 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } | |
18164 | }; | |
b99bd4ef | 18165 | |
c19d1205 ZW |
18166 | /* Table of all explicit relocation names. */ |
18167 | #ifdef OBJ_ELF | |
18168 | static struct reloc_entry reloc_names[] = | |
18169 | { | |
18170 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
18171 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
18172 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
18173 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
18174 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
18175 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
18176 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
18177 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
18178 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
18179 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
b43420e6 | 18180 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}, |
0855e32b NS |
18181 | { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL}, |
18182 | { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC}, | |
477330fc | 18183 | { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC}, |
0855e32b | 18184 | { "tlscall", BFD_RELOC_ARM_TLS_CALL}, |
477330fc | 18185 | { "TLSCALL", BFD_RELOC_ARM_TLS_CALL}, |
0855e32b | 18186 | { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ}, |
477330fc | 18187 | { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ} |
c19d1205 ZW |
18188 | }; |
18189 | #endif | |
b99bd4ef | 18190 | |
c19d1205 ZW |
18191 | /* Table of all conditional affixes. 0xF is not defined as a condition code. */ |
18192 | static const struct asm_cond conds[] = | |
18193 | { | |
18194 | {"eq", 0x0}, | |
18195 | {"ne", 0x1}, | |
18196 | {"cs", 0x2}, {"hs", 0x2}, | |
18197 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
18198 | {"mi", 0x4}, | |
18199 | {"pl", 0x5}, | |
18200 | {"vs", 0x6}, | |
18201 | {"vc", 0x7}, | |
18202 | {"hi", 0x8}, | |
18203 | {"ls", 0x9}, | |
18204 | {"ge", 0xa}, | |
18205 | {"lt", 0xb}, | |
18206 | {"gt", 0xc}, | |
18207 | {"le", 0xd}, | |
18208 | {"al", 0xe} | |
18209 | }; | |
bfae80f2 | 18210 | |
e797f7e0 MGD |
18211 | #define UL_BARRIER(L,U,CODE,FEAT) \ |
18212 | { L, CODE, ARM_FEATURE (FEAT, 0) }, \ | |
18213 | { U, CODE, ARM_FEATURE (FEAT, 0) } | |
18214 | ||
62b3e311 PB |
18215 | static struct asm_barrier_opt barrier_opt_names[] = |
18216 | { | |
e797f7e0 MGD |
18217 | UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER), |
18218 | UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER), | |
18219 | UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8), | |
18220 | UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER), | |
18221 | UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER), | |
18222 | UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER), | |
18223 | UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER), | |
18224 | UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8), | |
18225 | UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER), | |
18226 | UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER), | |
18227 | UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER), | |
18228 | UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER), | |
18229 | UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8), | |
18230 | UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER), | |
18231 | UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER), | |
18232 | UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8) | |
62b3e311 PB |
18233 | }; |
18234 | ||
e797f7e0 MGD |
18235 | #undef UL_BARRIER |
18236 | ||
c19d1205 ZW |
18237 | /* Table of ARM-format instructions. */ |
18238 | ||
18239 | /* Macros for gluing together operand strings. N.B. In all cases | |
18240 | other than OPS0, the trailing OP_stop comes from default | |
18241 | zero-initialization of the unspecified elements of the array. */ | |
18242 | #define OPS0() { OP_stop, } | |
18243 | #define OPS1(a) { OP_##a, } | |
18244 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
18245 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
18246 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
18247 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
18248 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
18249 | ||
5be8be5d DG |
18250 | /* These macros are similar to the OPSn, but do not prepend the OP_ prefix. |
18251 | This is useful when mixing operands for ARM and THUMB, i.e. using the | |
18252 | MIX_ARM_THUMB_OPERANDS macro. | |
18253 | In order to use these macros, prefix the number of operands with _ | |
18254 | e.g. _3. */ | |
18255 | #define OPS_1(a) { a, } | |
18256 | #define OPS_2(a,b) { a,b, } | |
18257 | #define OPS_3(a,b,c) { a,b,c, } | |
18258 | #define OPS_4(a,b,c,d) { a,b,c,d, } | |
18259 | #define OPS_5(a,b,c,d,e) { a,b,c,d,e, } | |
18260 | #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, } | |
18261 | ||
c19d1205 ZW |
18262 | /* These macros abstract out the exact format of the mnemonic table and |
18263 | save some repeated characters. */ | |
18264 | ||
18265 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
18266 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 18267 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 18268 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
18269 | |
18270 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
18271 | a T_MNEM_xyz enumerator. */ | |
18272 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
e07e6e58 | 18273 | TxCE (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 18274 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 18275 | TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
18276 | |
18277 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
18278 | infix after the third character. */ | |
18279 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 18280 | { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 18281 | THUMB_VARIANT, do_##ae, do_##te } |
088fa78e | 18282 | #define TxC3w(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 18283 | { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ |
088fa78e | 18284 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 | 18285 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 18286 | TxC3 (mnem, aop, 0x##top, nops, ops, ae, te) |
088fa78e | 18287 | #define TC3w(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 18288 | TxC3w (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 18289 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 18290 | TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
088fa78e | 18291 | #define tC3w(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 18292 | TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 | 18293 | |
c19d1205 | 18294 | /* Mnemonic that cannot be conditionalized. The ARM condition-code |
dfa9f0d5 PB |
18295 | field is still 0xE. Many of the Thumb variants can be executed |
18296 | conditionally, so this is checked separately. */ | |
c19d1205 | 18297 | #define TUE(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 18298 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 18299 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 | 18300 | |
dd5181d5 KT |
18301 | /* Same as TUE but the encoding function for ARM and Thumb modes is the same. |
18302 | Used by mnemonics that have very minimal differences in the encoding for | |
18303 | ARM and Thumb variants and can be handled in a common function. */ | |
18304 | #define TUEc(mnem, op, top, nops, ops, en) \ | |
18305 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ | |
18306 | THUMB_VARIANT, do_##en, do_##en } | |
18307 | ||
c19d1205 ZW |
18308 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM |
18309 | condition code field. */ | |
18310 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 18311 | { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 18312 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
18313 | |
18314 | /* ARM-only variants of all the above. */ | |
6a86118a | 18315 | #define CE(mnem, op, nops, ops, ae) \ |
21d799b5 | 18316 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
6a86118a NC |
18317 | |
18318 | #define C3(mnem, op, nops, ops, ae) \ | |
18319 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
18320 | ||
e3cb604e PB |
18321 | /* Legacy mnemonics that always have conditional infix after the third |
18322 | character. */ | |
18323 | #define CL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 18324 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
18325 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
18326 | ||
8f06b2d8 PB |
18327 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
18328 | #define cCE(mnem, op, nops, ops, ae) \ | |
21d799b5 | 18329 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 18330 | |
e3cb604e PB |
18331 | /* Legacy coprocessor instructions where conditional infix and conditional |
18332 | suffix are ambiguous. For consistency this includes all FPA instructions, | |
18333 | not just the potentially ambiguous ones. */ | |
18334 | #define cCL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 18335 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
18336 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
18337 | ||
18338 | /* Coprocessor, takes either a suffix or a position-3 infix | |
18339 | (for an FPA corner case). */ | |
18340 | #define C3E(mnem, op, nops, ops, ae) \ | |
21d799b5 | 18341 | { mnem, OPS##nops ops, OT_csuf_or_in3, \ |
e3cb604e | 18342 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 18343 | |
6a86118a | 18344 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
21d799b5 NC |
18345 | { m1 #m2 m3, OPS##nops ops, \ |
18346 | sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ | |
6a86118a NC |
18347 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
18348 | ||
18349 | #define CM(m1, m2, op, nops, ops, ae) \ | |
e07e6e58 NC |
18350 | xCM_ (m1, , m2, op, nops, ops, ae), \ |
18351 | xCM_ (m1, eq, m2, op, nops, ops, ae), \ | |
18352 | xCM_ (m1, ne, m2, op, nops, ops, ae), \ | |
18353 | xCM_ (m1, cs, m2, op, nops, ops, ae), \ | |
18354 | xCM_ (m1, hs, m2, op, nops, ops, ae), \ | |
18355 | xCM_ (m1, cc, m2, op, nops, ops, ae), \ | |
18356 | xCM_ (m1, ul, m2, op, nops, ops, ae), \ | |
18357 | xCM_ (m1, lo, m2, op, nops, ops, ae), \ | |
18358 | xCM_ (m1, mi, m2, op, nops, ops, ae), \ | |
18359 | xCM_ (m1, pl, m2, op, nops, ops, ae), \ | |
18360 | xCM_ (m1, vs, m2, op, nops, ops, ae), \ | |
18361 | xCM_ (m1, vc, m2, op, nops, ops, ae), \ | |
18362 | xCM_ (m1, hi, m2, op, nops, ops, ae), \ | |
18363 | xCM_ (m1, ls, m2, op, nops, ops, ae), \ | |
18364 | xCM_ (m1, ge, m2, op, nops, ops, ae), \ | |
18365 | xCM_ (m1, lt, m2, op, nops, ops, ae), \ | |
18366 | xCM_ (m1, gt, m2, op, nops, ops, ae), \ | |
18367 | xCM_ (m1, le, m2, op, nops, ops, ae), \ | |
18368 | xCM_ (m1, al, m2, op, nops, ops, ae) | |
6a86118a NC |
18369 | |
18370 | #define UE(mnem, op, nops, ops, ae) \ | |
18371 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
18372 | ||
18373 | #define UF(mnem, op, nops, ops, ae) \ | |
18374 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
18375 | ||
5287ad62 JB |
18376 | /* Neon data-processing. ARM versions are unconditional with cond=0xf. |
18377 | The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we | |
18378 | use the same encoding function for each. */ | |
18379 | #define NUF(mnem, op, nops, ops, enc) \ | |
18380 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ | |
18381 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } | |
18382 | ||
18383 | /* Neon data processing, version which indirects through neon_enc_tab for | |
18384 | the various overloaded versions of opcodes. */ | |
18385 | #define nUF(mnem, op, nops, ops, enc) \ | |
21d799b5 | 18386 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
18387 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
18388 | ||
18389 | /* Neon insn with conditional suffix for the ARM version, non-overloaded | |
18390 | version. */ | |
037e8744 JB |
18391 | #define NCE_tag(mnem, op, nops, ops, enc, tag) \ |
18392 | { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ | |
5287ad62 JB |
18393 | THUMB_VARIANT, do_##enc, do_##enc } |
18394 | ||
037e8744 | 18395 | #define NCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 18396 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
18397 | |
18398 | #define NCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 18399 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 18400 | |
5287ad62 | 18401 | /* Neon insn with conditional suffix for the ARM version, overloaded types. */ |
037e8744 | 18402 | #define nCE_tag(mnem, op, nops, ops, enc, tag) \ |
21d799b5 | 18403 | { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
18404 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
18405 | ||
037e8744 | 18406 | #define nCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 18407 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
18408 | |
18409 | #define nCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 18410 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 18411 | |
c19d1205 ZW |
18412 | #define do_0 0 |
18413 | ||
c19d1205 | 18414 | static const struct asm_opcode insns[] = |
bfae80f2 | 18415 | { |
74db7efb NC |
18416 | #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */ |
18417 | #define THUMB_VARIANT & arm_ext_v4t | |
21d799b5 NC |
18418 | tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c), |
18419 | tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
18420 | tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
18421 | tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
18422 | tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
18423 | tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
18424 | tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub), | |
18425 | tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub), | |
18426 | tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c), | |
18427 | tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
18428 | tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
18429 | tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
18430 | tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
18431 | tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
18432 | tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3), | |
18433 | tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3), | |
c19d1205 ZW |
18434 | |
18435 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
18436 | for setting PSR flag bits. They are obsolete in V6 and do not | |
18437 | have Thumb equivalents. */ | |
21d799b5 NC |
18438 | tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), |
18439 | tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), | |
18440 | CL("tstp", 110f000, 2, (RR, SH), cmp), | |
18441 | tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
18442 | tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
18443 | CL("cmpp", 150f000, 2, (RR, SH), cmp), | |
18444 | tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
18445 | tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
18446 | CL("cmnp", 170f000, 2, (RR, SH), cmp), | |
18447 | ||
18448 | tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp), | |
18449 | tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp), | |
18450 | tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst), | |
18451 | tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst), | |
18452 | ||
18453 | tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
5be8be5d DG |
18454 | tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), |
18455 | tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR, | |
18456 | OP_RRnpc), | |
18457 | OP_ADDRGLDR),ldst, t_ldst), | |
18458 | tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), | |
21d799b5 NC |
18459 | |
18460 | tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18461 | tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18462 | tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18463 | tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18464 | tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18465 | tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18466 | ||
18467 | TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi), | |
18468 | TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi), | |
18469 | tCE("b", a000000, _b, 1, (EXPr), branch, t_branch), | |
18470 | TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23), | |
bfae80f2 | 18471 | |
c19d1205 | 18472 | /* Pseudo ops. */ |
21d799b5 | 18473 | tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac | 18474 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
21d799b5 | 18475 | tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop), |
74db7efb | 18476 | tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf), |
c19d1205 ZW |
18477 | |
18478 | /* Thumb-compatibility pseudo ops. */ | |
21d799b5 NC |
18479 | tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift), |
18480 | tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift), | |
18481 | tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift), | |
18482 | tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
18483 | tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift), | |
18484 | tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift), | |
18485 | tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift), | |
18486 | tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift), | |
18487 | tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg), | |
18488 | tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg), | |
18489 | tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop), | |
18490 | tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop), | |
c19d1205 | 18491 | |
16a4cf17 | 18492 | /* These may simplify to neg. */ |
21d799b5 NC |
18493 | TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), |
18494 | TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
16a4cf17 | 18495 | |
c921be7d NC |
18496 | #undef THUMB_VARIANT |
18497 | #define THUMB_VARIANT & arm_ext_v6 | |
18498 | ||
21d799b5 | 18499 | TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
18500 | |
18501 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
c921be7d NC |
18502 | #undef THUMB_VARIANT |
18503 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18504 | ||
21d799b5 NC |
18505 | TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
18506 | TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
18507 | CL("teqp", 130f000, 2, (RR, SH), cmp), | |
c19d1205 | 18508 | |
5be8be5d DG |
18509 | TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), |
18510 | TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
18511 | TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt), | |
18512 | TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
c19d1205 | 18513 | |
21d799b5 NC |
18514 | TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
18515 | TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 18516 | |
21d799b5 NC |
18517 | TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
18518 | TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
18519 | |
18520 | /* V1 instructions with no Thumb analogue at all. */ | |
21d799b5 | 18521 | CE("rsc", 0e00000, 3, (RR, oRR, SH), arit), |
c19d1205 ZW |
18522 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), |
18523 | ||
18524 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
18525 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
18526 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
18527 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
18528 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
18529 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
18530 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
18531 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
18532 | ||
c921be7d NC |
18533 | #undef ARM_VARIANT |
18534 | #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */ | |
18535 | #undef THUMB_VARIANT | |
18536 | #define THUMB_VARIANT & arm_ext_v4t | |
18537 | ||
21d799b5 NC |
18538 | tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
18539 | tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
c19d1205 | 18540 | |
c921be7d NC |
18541 | #undef THUMB_VARIANT |
18542 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18543 | ||
21d799b5 | 18544 | TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
c19d1205 ZW |
18545 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), |
18546 | ||
18547 | /* Generic coprocessor instructions. */ | |
21d799b5 NC |
18548 | TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), |
18549 | TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18550 | TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18551 | TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18552 | TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18553 | TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
db472d6f | 18554 | TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), |
c19d1205 | 18555 | |
c921be7d NC |
18556 | #undef ARM_VARIANT |
18557 | #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */ | |
18558 | ||
21d799b5 | 18559 | CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
c19d1205 ZW |
18560 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
18561 | ||
c921be7d NC |
18562 | #undef ARM_VARIANT |
18563 | #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */ | |
18564 | #undef THUMB_VARIANT | |
18565 | #define THUMB_VARIANT & arm_ext_msr | |
18566 | ||
d2cd1205 JB |
18567 | TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs), |
18568 | TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr), | |
c19d1205 | 18569 | |
c921be7d NC |
18570 | #undef ARM_VARIANT |
18571 | #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */ | |
18572 | #undef THUMB_VARIANT | |
18573 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18574 | ||
21d799b5 NC |
18575 | TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
18576 | CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
18577 | TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
18578 | CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
18579 | TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
18580 | CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
18581 | TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
18582 | CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
c19d1205 | 18583 | |
c921be7d NC |
18584 | #undef ARM_VARIANT |
18585 | #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */ | |
18586 | #undef THUMB_VARIANT | |
18587 | #define THUMB_VARIANT & arm_ext_v4t | |
18588 | ||
5be8be5d DG |
18589 | tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
18590 | tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
18591 | tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
18592 | tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
56c0a61f RE |
18593 | tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
18594 | tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
c19d1205 | 18595 | |
c921be7d NC |
18596 | #undef ARM_VARIANT |
18597 | #define ARM_VARIANT & arm_ext_v4t_5 | |
18598 | ||
c19d1205 ZW |
18599 | /* ARM Architecture 4T. */ |
18600 | /* Note: bx (and blx) are required on V5, even if the processor does | |
18601 | not support Thumb. */ | |
21d799b5 | 18602 | TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx), |
c19d1205 | 18603 | |
c921be7d NC |
18604 | #undef ARM_VARIANT |
18605 | #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */ | |
18606 | #undef THUMB_VARIANT | |
18607 | #define THUMB_VARIANT & arm_ext_v5t | |
18608 | ||
c19d1205 ZW |
18609 | /* Note: blx has 2 variants; the .value coded here is for |
18610 | BLX(2). Only this variant has conditional execution. */ | |
21d799b5 NC |
18611 | TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx), |
18612 | TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
c19d1205 | 18613 | |
c921be7d NC |
18614 | #undef THUMB_VARIANT |
18615 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18616 | ||
21d799b5 NC |
18617 | TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
18618 | TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18619 | TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18620 | TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18621 | TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18622 | TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
18623 | TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
18624 | TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
c19d1205 | 18625 | |
c921be7d | 18626 | #undef ARM_VARIANT |
74db7efb NC |
18627 | #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */ |
18628 | #undef THUMB_VARIANT | |
18629 | #define THUMB_VARIANT & arm_ext_v5exp | |
c921be7d | 18630 | |
21d799b5 NC |
18631 | TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
18632 | TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
18633 | TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
18634 | TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 18635 | |
21d799b5 NC |
18636 | TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
18637 | TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 18638 | |
21d799b5 NC |
18639 | TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), |
18640 | TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
18641 | TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
18642 | TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
c19d1205 | 18643 | |
21d799b5 NC |
18644 | TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
18645 | TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18646 | TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18647 | TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 18648 | |
21d799b5 NC |
18649 | TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
18650 | TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 18651 | |
03ee1b7f NC |
18652 | TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), |
18653 | TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
18654 | TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
18655 | TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
c19d1205 | 18656 | |
c921be7d | 18657 | #undef ARM_VARIANT |
74db7efb NC |
18658 | #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */ |
18659 | #undef THUMB_VARIANT | |
18660 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 18661 | |
21d799b5 | 18662 | TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld), |
5be8be5d DG |
18663 | TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS), |
18664 | ldrd, t_ldstd), | |
18665 | TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp, | |
18666 | ADDRGLDRS), ldrd, t_ldstd), | |
c19d1205 | 18667 | |
21d799b5 NC |
18668 | TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
18669 | TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
c19d1205 | 18670 | |
c921be7d NC |
18671 | #undef ARM_VARIANT |
18672 | #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */ | |
18673 | ||
21d799b5 | 18674 | TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
c19d1205 | 18675 | |
c921be7d NC |
18676 | #undef ARM_VARIANT |
18677 | #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */ | |
18678 | #undef THUMB_VARIANT | |
18679 | #define THUMB_VARIANT & arm_ext_v6 | |
18680 | ||
21d799b5 NC |
18681 | TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
18682 | TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
18683 | tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
18684 | tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
18685 | tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
18686 | tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18687 | tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18688 | tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18689 | tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18690 | TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend), | |
c19d1205 | 18691 | |
c921be7d NC |
18692 | #undef THUMB_VARIANT |
18693 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18694 | ||
5be8be5d DG |
18695 | TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex), |
18696 | TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
18697 | strex, t_strex), | |
21d799b5 NC |
18698 | TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
18699 | TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
62b3e311 | 18700 | |
21d799b5 NC |
18701 | TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), |
18702 | TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
62b3e311 | 18703 | |
9e3c6df6 | 18704 | /* ARM V6 not included in V7M. */ |
c921be7d NC |
18705 | #undef THUMB_VARIANT |
18706 | #define THUMB_VARIANT & arm_ext_v6_notm | |
9e3c6df6 | 18707 | TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
d709e4e6 | 18708 | TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
9e3c6df6 PB |
18709 | UF(rfeib, 9900a00, 1, (RRw), rfe), |
18710 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
18711 | TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
18712 | TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
d709e4e6 RE |
18713 | UF(rfefa, 8100a00, 1, (RRw), rfe), |
18714 | TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
18715 | UF(rfeed, 9900a00, 1, (RRw), rfe), | |
9e3c6df6 | 18716 | TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), |
d709e4e6 RE |
18717 | TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), |
18718 | TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), | |
9e3c6df6 | 18719 | UF(srsib, 9c00500, 2, (oRRw, I31w), srs), |
d709e4e6 | 18720 | UF(srsfa, 9c00500, 2, (oRRw, I31w), srs), |
9e3c6df6 | 18721 | UF(srsda, 8400500, 2, (oRRw, I31w), srs), |
d709e4e6 | 18722 | UF(srsed, 8400500, 2, (oRRw, I31w), srs), |
9e3c6df6 | 18723 | TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), |
d709e4e6 | 18724 | TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), |
c921be7d | 18725 | |
9e3c6df6 PB |
18726 | /* ARM V6 not included in V7M (eg. integer SIMD). */ |
18727 | #undef THUMB_VARIANT | |
18728 | #define THUMB_VARIANT & arm_ext_v6_dsp | |
21d799b5 NC |
18729 | TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps), |
18730 | TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), | |
18731 | TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
18732 | TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18733 | TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18734 | TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18735 | /* Old name for QASX. */ |
74db7efb | 18736 | TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 | 18737 | TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18738 | /* Old name for QSAX. */ |
74db7efb | 18739 | TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
18740 | TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18741 | TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18742 | TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18743 | TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18744 | TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18745 | /* Old name for SASX. */ |
74db7efb | 18746 | TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
18747 | TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18748 | TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 18749 | TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18750 | /* Old name for SHASX. */ |
21d799b5 | 18751 | TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
74db7efb | 18752 | TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18753 | /* Old name for SHSAX. */ |
21d799b5 NC |
18754 | TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18755 | TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18756 | TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18757 | TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18758 | /* Old name for SSAX. */ |
74db7efb | 18759 | TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
18760 | TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18761 | TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18762 | TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18763 | TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18764 | TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18765 | /* Old name for UASX. */ |
74db7efb | 18766 | TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
18767 | TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18768 | TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 18769 | TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18770 | /* Old name for UHASX. */ |
21d799b5 NC |
18771 | TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18772 | TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18773 | /* Old name for UHSAX. */ |
21d799b5 NC |
18774 | TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18775 | TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18776 | TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18777 | TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18778 | TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 18779 | TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18780 | /* Old name for UQASX. */ |
21d799b5 NC |
18781 | TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18782 | TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18783 | /* Old name for UQSAX. */ |
21d799b5 NC |
18784 | TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18785 | TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18786 | TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18787 | TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18788 | TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18789 | /* Old name for USAX. */ |
74db7efb | 18790 | TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 | 18791 | TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
18792 | TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
18793 | TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
18794 | TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
18795 | TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18796 | TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
18797 | TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
18798 | TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
18799 | TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18800 | TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18801 | TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18802 | TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18803 | TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
18804 | TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
18805 | TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18806 | TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18807 | TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
18808 | TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
18809 | TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18810 | TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18811 | TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18812 | TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18813 | TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18814 | TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18815 | TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18816 | TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18817 | TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18818 | TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
21d799b5 NC |
18819 | TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), |
18820 | TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
18821 | TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18822 | TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18823 | TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), | |
c19d1205 | 18824 | |
c921be7d NC |
18825 | #undef ARM_VARIANT |
18826 | #define ARM_VARIANT & arm_ext_v6k | |
18827 | #undef THUMB_VARIANT | |
18828 | #define THUMB_VARIANT & arm_ext_v6k | |
18829 | ||
21d799b5 NC |
18830 | tCE("yield", 320f001, _yield, 0, (), noargs, t_hint), |
18831 | tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint), | |
18832 | tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint), | |
18833 | tCE("sev", 320f004, _sev, 0, (), noargs, t_hint), | |
c19d1205 | 18834 | |
c921be7d NC |
18835 | #undef THUMB_VARIANT |
18836 | #define THUMB_VARIANT & arm_ext_v6_notm | |
5be8be5d DG |
18837 | TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb), |
18838 | ldrexd, t_ldrexd), | |
18839 | TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp, | |
18840 | RRnpcb), strexd, t_strexd), | |
ebdca51a | 18841 | |
c921be7d NC |
18842 | #undef THUMB_VARIANT |
18843 | #define THUMB_VARIANT & arm_ext_v6t2 | |
5be8be5d DG |
18844 | TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb), |
18845 | rd_rn, rd_rn), | |
18846 | TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb), | |
18847 | rd_rn, rd_rn), | |
18848 | TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
877807f8 | 18849 | strex, t_strexbh), |
5be8be5d | 18850 | TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), |
877807f8 | 18851 | strex, t_strexbh), |
21d799b5 | 18852 | TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs), |
c19d1205 | 18853 | |
c921be7d | 18854 | #undef ARM_VARIANT |
f4c65163 | 18855 | #define ARM_VARIANT & arm_ext_sec |
74db7efb | 18856 | #undef THUMB_VARIANT |
f4c65163 | 18857 | #define THUMB_VARIANT & arm_ext_sec |
c921be7d | 18858 | |
21d799b5 | 18859 | TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 | 18860 | |
90ec0d68 MGD |
18861 | #undef ARM_VARIANT |
18862 | #define ARM_VARIANT & arm_ext_virt | |
18863 | #undef THUMB_VARIANT | |
18864 | #define THUMB_VARIANT & arm_ext_virt | |
18865 | ||
18866 | TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc), | |
18867 | TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs), | |
18868 | ||
c921be7d | 18869 | #undef ARM_VARIANT |
74db7efb | 18870 | #define ARM_VARIANT & arm_ext_v6t2 |
f4c65163 MGD |
18871 | #undef THUMB_VARIANT |
18872 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 18873 | |
21d799b5 NC |
18874 | TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
18875 | TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
18876 | TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
18877 | TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
c19d1205 | 18878 | |
21d799b5 NC |
18879 | TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
18880 | TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), | |
18881 | TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), | |
18882 | TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), | |
c19d1205 | 18883 | |
5be8be5d DG |
18884 | TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), |
18885 | TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
18886 | TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
18887 | TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
c19d1205 | 18888 | |
bf3eeda7 | 18889 | /* Thumb-only instructions. */ |
74db7efb | 18890 | #undef ARM_VARIANT |
bf3eeda7 NS |
18891 | #define ARM_VARIANT NULL |
18892 | TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz), | |
18893 | TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz), | |
c921be7d NC |
18894 | |
18895 | /* ARM does not really have an IT instruction, so always allow it. | |
18896 | The opcode is copied from Thumb in order to allow warnings in | |
18897 | -mimplicit-it=[never | arm] modes. */ | |
18898 | #undef ARM_VARIANT | |
18899 | #define ARM_VARIANT & arm_ext_v1 | |
18900 | ||
21d799b5 NC |
18901 | TUE("it", bf08, bf08, 1, (COND), it, t_it), |
18902 | TUE("itt", bf0c, bf0c, 1, (COND), it, t_it), | |
18903 | TUE("ite", bf04, bf04, 1, (COND), it, t_it), | |
18904 | TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it), | |
18905 | TUE("itet", bf06, bf06, 1, (COND), it, t_it), | |
18906 | TUE("itte", bf0a, bf0a, 1, (COND), it, t_it), | |
18907 | TUE("itee", bf02, bf02, 1, (COND), it, t_it), | |
18908 | TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it), | |
18909 | TUE("itett", bf07, bf07, 1, (COND), it, t_it), | |
18910 | TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it), | |
18911 | TUE("iteet", bf03, bf03, 1, (COND), it, t_it), | |
18912 | TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it), | |
18913 | TUE("itete", bf05, bf05, 1, (COND), it, t_it), | |
18914 | TUE("ittee", bf09, bf09, 1, (COND), it, t_it), | |
18915 | TUE("iteee", bf01, bf01, 1, (COND), it, t_it), | |
1c444d06 | 18916 | /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */ |
21d799b5 NC |
18917 | TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx), |
18918 | TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx), | |
c19d1205 | 18919 | |
92e90b6e | 18920 | /* Thumb2 only instructions. */ |
c921be7d NC |
18921 | #undef ARM_VARIANT |
18922 | #define ARM_VARIANT NULL | |
92e90b6e | 18923 | |
21d799b5 NC |
18924 | TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), |
18925 | TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
18926 | TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn), | |
18927 | TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn), | |
18928 | TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb), | |
18929 | TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb), | |
92e90b6e | 18930 | |
eea54501 MGD |
18931 | /* Hardware division instructions. */ |
18932 | #undef ARM_VARIANT | |
18933 | #define ARM_VARIANT & arm_ext_adiv | |
c921be7d NC |
18934 | #undef THUMB_VARIANT |
18935 | #define THUMB_VARIANT & arm_ext_div | |
18936 | ||
eea54501 MGD |
18937 | TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div), |
18938 | TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div), | |
62b3e311 | 18939 | |
7e806470 | 18940 | /* ARM V6M/V7 instructions. */ |
c921be7d NC |
18941 | #undef ARM_VARIANT |
18942 | #define ARM_VARIANT & arm_ext_barrier | |
18943 | #undef THUMB_VARIANT | |
18944 | #define THUMB_VARIANT & arm_ext_barrier | |
18945 | ||
ccb84d65 JB |
18946 | TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier), |
18947 | TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier), | |
18948 | TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier), | |
7e806470 | 18949 | |
62b3e311 | 18950 | /* ARM V7 instructions. */ |
c921be7d NC |
18951 | #undef ARM_VARIANT |
18952 | #define ARM_VARIANT & arm_ext_v7 | |
18953 | #undef THUMB_VARIANT | |
18954 | #define THUMB_VARIANT & arm_ext_v7 | |
18955 | ||
21d799b5 NC |
18956 | TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld), |
18957 | TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), | |
62b3e311 | 18958 | |
74db7efb | 18959 | #undef ARM_VARIANT |
60e5ef9f | 18960 | #define ARM_VARIANT & arm_ext_mp |
74db7efb | 18961 | #undef THUMB_VARIANT |
60e5ef9f MGD |
18962 | #define THUMB_VARIANT & arm_ext_mp |
18963 | ||
18964 | TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld), | |
18965 | ||
53c4b28b MGD |
18966 | /* AArchv8 instructions. */ |
18967 | #undef ARM_VARIANT | |
18968 | #define ARM_VARIANT & arm_ext_v8 | |
18969 | #undef THUMB_VARIANT | |
18970 | #define THUMB_VARIANT & arm_ext_v8 | |
18971 | ||
18972 | tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint), | |
8884b720 | 18973 | TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt), |
4b8c8c02 RE |
18974 | TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), |
18975 | TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb), | |
9eb6c0f1 | 18976 | ldrexd, t_ldrexd), |
4b8c8c02 RE |
18977 | TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn), |
18978 | TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
18979 | TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb), | |
18980 | stlex, t_stlex), | |
18981 | TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), | |
9eb6c0f1 | 18982 | strexd, t_strexd), |
4b8c8c02 RE |
18983 | TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb), |
18984 | stlex, t_stlex), | |
18985 | TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb), | |
18986 | stlex, t_stlex), | |
18987 | TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
18988 | TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
18989 | TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
18990 | TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
18991 | TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
18992 | TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
53c4b28b | 18993 | |
8884b720 | 18994 | /* ARMv8 T32 only. */ |
74db7efb | 18995 | #undef ARM_VARIANT |
b79f7053 MGD |
18996 | #define ARM_VARIANT NULL |
18997 | TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs), | |
18998 | TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs), | |
18999 | TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs), | |
19000 | ||
33399f07 MGD |
19001 | /* FP for ARMv8. */ |
19002 | #undef ARM_VARIANT | |
a715796b | 19003 | #define ARM_VARIANT & fpu_vfp_ext_armv8xd |
33399f07 | 19004 | #undef THUMB_VARIANT |
a715796b | 19005 | #define THUMB_VARIANT & fpu_vfp_ext_armv8xd |
33399f07 MGD |
19006 | |
19007 | nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel), | |
19008 | nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel), | |
19009 | nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel), | |
19010 | nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel), | |
73924fbc MGD |
19011 | nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm), |
19012 | nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm), | |
7e8e6784 MGD |
19013 | nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta), |
19014 | nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn), | |
19015 | nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp), | |
19016 | nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm), | |
30bdf752 MGD |
19017 | nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr), |
19018 | nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz), | |
19019 | nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx), | |
19020 | nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta), | |
19021 | nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn), | |
19022 | nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp), | |
19023 | nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm), | |
33399f07 | 19024 | |
91ff7894 MGD |
19025 | /* Crypto v1 extensions. */ |
19026 | #undef ARM_VARIANT | |
19027 | #define ARM_VARIANT & fpu_crypto_ext_armv8 | |
19028 | #undef THUMB_VARIANT | |
19029 | #define THUMB_VARIANT & fpu_crypto_ext_armv8 | |
19030 | ||
19031 | nUF(aese, _aes, 2, (RNQ, RNQ), aese), | |
19032 | nUF(aesd, _aes, 2, (RNQ, RNQ), aesd), | |
19033 | nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc), | |
19034 | nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc), | |
48adcd8e MGD |
19035 | nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c), |
19036 | nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p), | |
19037 | nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m), | |
19038 | nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0), | |
19039 | nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h), | |
19040 | nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2), | |
19041 | nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1), | |
3c9017d2 MGD |
19042 | nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h), |
19043 | nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1), | |
19044 | nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0), | |
91ff7894 | 19045 | |
dd5181d5 | 19046 | #undef ARM_VARIANT |
74db7efb | 19047 | #define ARM_VARIANT & crc_ext_armv8 |
dd5181d5 KT |
19048 | #undef THUMB_VARIANT |
19049 | #define THUMB_VARIANT & crc_ext_armv8 | |
19050 | TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b), | |
19051 | TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h), | |
19052 | TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w), | |
19053 | TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb), | |
19054 | TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch), | |
19055 | TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw), | |
19056 | ||
c921be7d NC |
19057 | #undef ARM_VARIANT |
19058 | #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ | |
53c4b28b MGD |
19059 | #undef THUMB_VARIANT |
19060 | #define THUMB_VARIANT NULL | |
c921be7d | 19061 | |
21d799b5 NC |
19062 | cCE("wfs", e200110, 1, (RR), rd), |
19063 | cCE("rfs", e300110, 1, (RR), rd), | |
19064 | cCE("wfc", e400110, 1, (RR), rd), | |
19065 | cCE("rfc", e500110, 1, (RR), rd), | |
19066 | ||
19067 | cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19068 | cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19069 | cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19070 | cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19071 | ||
19072 | cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19073 | cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19074 | cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19075 | cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19076 | ||
19077 | cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm), | |
19078 | cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm), | |
19079 | cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm), | |
19080 | cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm), | |
19081 | cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm), | |
19082 | cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm), | |
19083 | cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm), | |
19084 | cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm), | |
19085 | cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm), | |
19086 | cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm), | |
19087 | cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm), | |
19088 | cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm), | |
19089 | ||
19090 | cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm), | |
19091 | cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm), | |
19092 | cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm), | |
19093 | cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm), | |
19094 | cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm), | |
19095 | cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm), | |
19096 | cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm), | |
19097 | cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm), | |
19098 | cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm), | |
19099 | cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm), | |
19100 | cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm), | |
19101 | cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm), | |
19102 | ||
19103 | cCL("abss", e208100, 2, (RF, RF_IF), rd_rm), | |
19104 | cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm), | |
19105 | cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm), | |
19106 | cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm), | |
19107 | cCL("absd", e208180, 2, (RF, RF_IF), rd_rm), | |
19108 | cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm), | |
19109 | cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm), | |
19110 | cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm), | |
19111 | cCL("abse", e288100, 2, (RF, RF_IF), rd_rm), | |
19112 | cCL("absep", e288120, 2, (RF, RF_IF), rd_rm), | |
19113 | cCL("absem", e288140, 2, (RF, RF_IF), rd_rm), | |
19114 | cCL("absez", e288160, 2, (RF, RF_IF), rd_rm), | |
19115 | ||
19116 | cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm), | |
19117 | cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm), | |
19118 | cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm), | |
19119 | cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm), | |
19120 | cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm), | |
19121 | cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm), | |
19122 | cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm), | |
19123 | cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm), | |
19124 | cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm), | |
19125 | cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm), | |
19126 | cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm), | |
19127 | cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm), | |
19128 | ||
19129 | cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm), | |
19130 | cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm), | |
19131 | cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm), | |
19132 | cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm), | |
19133 | cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm), | |
19134 | cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm), | |
19135 | cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm), | |
19136 | cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm), | |
19137 | cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm), | |
19138 | cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm), | |
19139 | cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm), | |
19140 | cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm), | |
19141 | ||
19142 | cCL("logs", e508100, 2, (RF, RF_IF), rd_rm), | |
19143 | cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm), | |
19144 | cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm), | |
19145 | cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm), | |
19146 | cCL("logd", e508180, 2, (RF, RF_IF), rd_rm), | |
19147 | cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm), | |
19148 | cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm), | |
19149 | cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm), | |
19150 | cCL("loge", e588100, 2, (RF, RF_IF), rd_rm), | |
19151 | cCL("logep", e588120, 2, (RF, RF_IF), rd_rm), | |
19152 | cCL("logem", e588140, 2, (RF, RF_IF), rd_rm), | |
19153 | cCL("logez", e588160, 2, (RF, RF_IF), rd_rm), | |
19154 | ||
19155 | cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm), | |
19156 | cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm), | |
19157 | cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm), | |
19158 | cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm), | |
19159 | cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm), | |
19160 | cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm), | |
19161 | cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm), | |
19162 | cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm), | |
19163 | cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm), | |
19164 | cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm), | |
19165 | cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm), | |
19166 | cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm), | |
19167 | ||
19168 | cCL("exps", e708100, 2, (RF, RF_IF), rd_rm), | |
19169 | cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm), | |
19170 | cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm), | |
19171 | cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm), | |
19172 | cCL("expd", e708180, 2, (RF, RF_IF), rd_rm), | |
19173 | cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm), | |
19174 | cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm), | |
19175 | cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm), | |
19176 | cCL("expe", e788100, 2, (RF, RF_IF), rd_rm), | |
19177 | cCL("expep", e788120, 2, (RF, RF_IF), rd_rm), | |
19178 | cCL("expem", e788140, 2, (RF, RF_IF), rd_rm), | |
19179 | cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm), | |
19180 | ||
19181 | cCL("sins", e808100, 2, (RF, RF_IF), rd_rm), | |
19182 | cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm), | |
19183 | cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm), | |
19184 | cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm), | |
19185 | cCL("sind", e808180, 2, (RF, RF_IF), rd_rm), | |
19186 | cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm), | |
19187 | cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm), | |
19188 | cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm), | |
19189 | cCL("sine", e888100, 2, (RF, RF_IF), rd_rm), | |
19190 | cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm), | |
19191 | cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm), | |
19192 | cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm), | |
19193 | ||
19194 | cCL("coss", e908100, 2, (RF, RF_IF), rd_rm), | |
19195 | cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm), | |
19196 | cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm), | |
19197 | cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm), | |
19198 | cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm), | |
19199 | cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm), | |
19200 | cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm), | |
19201 | cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm), | |
19202 | cCL("cose", e988100, 2, (RF, RF_IF), rd_rm), | |
19203 | cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm), | |
19204 | cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm), | |
19205 | cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm), | |
19206 | ||
19207 | cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm), | |
19208 | cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm), | |
19209 | cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm), | |
19210 | cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm), | |
19211 | cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm), | |
19212 | cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm), | |
19213 | cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm), | |
19214 | cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm), | |
19215 | cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm), | |
19216 | cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm), | |
19217 | cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm), | |
19218 | cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm), | |
19219 | ||
19220 | cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm), | |
19221 | cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm), | |
19222 | cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm), | |
19223 | cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm), | |
19224 | cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm), | |
19225 | cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm), | |
19226 | cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm), | |
19227 | cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm), | |
19228 | cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm), | |
19229 | cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm), | |
19230 | cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm), | |
19231 | cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm), | |
19232 | ||
19233 | cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm), | |
19234 | cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm), | |
19235 | cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm), | |
19236 | cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm), | |
19237 | cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm), | |
19238 | cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm), | |
19239 | cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm), | |
19240 | cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm), | |
19241 | cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm), | |
19242 | cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm), | |
19243 | cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm), | |
19244 | cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm), | |
19245 | ||
19246 | cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm), | |
19247 | cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm), | |
19248 | cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm), | |
19249 | cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm), | |
19250 | cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm), | |
19251 | cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm), | |
19252 | cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm), | |
19253 | cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm), | |
19254 | cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm), | |
19255 | cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm), | |
19256 | cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm), | |
19257 | cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm), | |
19258 | ||
19259 | cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm), | |
19260 | cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm), | |
19261 | cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm), | |
19262 | cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm), | |
19263 | cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm), | |
19264 | cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm), | |
19265 | cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm), | |
19266 | cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm), | |
19267 | cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm), | |
19268 | cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm), | |
19269 | cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm), | |
19270 | cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm), | |
19271 | ||
19272 | cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm), | |
19273 | cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm), | |
19274 | cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm), | |
19275 | cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm), | |
19276 | cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm), | |
19277 | cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm), | |
19278 | cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm), | |
19279 | cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm), | |
19280 | cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm), | |
19281 | cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm), | |
19282 | cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm), | |
19283 | cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm), | |
19284 | ||
19285 | cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19286 | cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19287 | cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19288 | cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19289 | cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19290 | cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19291 | cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19292 | cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19293 | cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19294 | cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19295 | cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19296 | cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19297 | ||
19298 | cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19299 | cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19300 | cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19301 | cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19302 | cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19303 | cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19304 | cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19305 | cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19306 | cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19307 | cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19308 | cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19309 | cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19310 | ||
19311 | cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19312 | cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19313 | cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19314 | cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19315 | cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19316 | cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19317 | cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19318 | cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19319 | cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19320 | cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19321 | cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19322 | cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19323 | ||
19324 | cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19325 | cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19326 | cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19327 | cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19328 | cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19329 | cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19330 | cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19331 | cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19332 | cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19333 | cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19334 | cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19335 | cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19336 | ||
19337 | cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19338 | cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19339 | cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19340 | cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19341 | cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19342 | cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19343 | cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19344 | cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19345 | cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19346 | cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19347 | cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19348 | cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19349 | ||
19350 | cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19351 | cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19352 | cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19353 | cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19354 | cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19355 | cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19356 | cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19357 | cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19358 | cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19359 | cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19360 | cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19361 | cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19362 | ||
19363 | cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19364 | cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19365 | cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19366 | cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19367 | cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19368 | cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19369 | cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19370 | cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19371 | cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19372 | cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19373 | cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19374 | cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19375 | ||
19376 | cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19377 | cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19378 | cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19379 | cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19380 | cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19381 | cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19382 | cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19383 | cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19384 | cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19385 | cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19386 | cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19387 | cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19388 | ||
19389 | cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19390 | cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19391 | cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19392 | cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19393 | cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19394 | cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19395 | cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19396 | cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19397 | cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19398 | cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19399 | cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19400 | cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19401 | ||
19402 | cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19403 | cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19404 | cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19405 | cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19406 | cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19407 | cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19408 | cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19409 | cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19410 | cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19411 | cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19412 | cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19413 | cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19414 | ||
19415 | cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19416 | cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19417 | cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19418 | cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19419 | cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19420 | cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19421 | cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19422 | cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19423 | cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19424 | cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19425 | cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19426 | cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19427 | ||
19428 | cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19429 | cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19430 | cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19431 | cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19432 | cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19433 | cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19434 | cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19435 | cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19436 | cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19437 | cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19438 | cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19439 | cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19440 | ||
19441 | cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19442 | cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19443 | cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19444 | cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19445 | cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19446 | cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19447 | cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19448 | cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19449 | cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19450 | cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19451 | cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19452 | cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19453 | ||
19454 | cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp), | |
19455 | C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp), | |
19456 | cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp), | |
19457 | C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp), | |
19458 | ||
19459 | cCL("flts", e000110, 2, (RF, RR), rn_rd), | |
19460 | cCL("fltsp", e000130, 2, (RF, RR), rn_rd), | |
19461 | cCL("fltsm", e000150, 2, (RF, RR), rn_rd), | |
19462 | cCL("fltsz", e000170, 2, (RF, RR), rn_rd), | |
19463 | cCL("fltd", e000190, 2, (RF, RR), rn_rd), | |
19464 | cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd), | |
19465 | cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd), | |
19466 | cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd), | |
19467 | cCL("flte", e080110, 2, (RF, RR), rn_rd), | |
19468 | cCL("fltep", e080130, 2, (RF, RR), rn_rd), | |
19469 | cCL("fltem", e080150, 2, (RF, RR), rn_rd), | |
19470 | cCL("fltez", e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 19471 | |
c19d1205 ZW |
19472 | /* The implementation of the FIX instruction is broken on some |
19473 | assemblers, in that it accepts a precision specifier as well as a | |
19474 | rounding specifier, despite the fact that this is meaningless. | |
19475 | To be more compatible, we accept it as well, though of course it | |
19476 | does not set any bits. */ | |
21d799b5 NC |
19477 | cCE("fix", e100110, 2, (RR, RF), rd_rm), |
19478 | cCL("fixp", e100130, 2, (RR, RF), rd_rm), | |
19479 | cCL("fixm", e100150, 2, (RR, RF), rd_rm), | |
19480 | cCL("fixz", e100170, 2, (RR, RF), rd_rm), | |
19481 | cCL("fixsp", e100130, 2, (RR, RF), rd_rm), | |
19482 | cCL("fixsm", e100150, 2, (RR, RF), rd_rm), | |
19483 | cCL("fixsz", e100170, 2, (RR, RF), rd_rm), | |
19484 | cCL("fixdp", e100130, 2, (RR, RF), rd_rm), | |
19485 | cCL("fixdm", e100150, 2, (RR, RF), rd_rm), | |
19486 | cCL("fixdz", e100170, 2, (RR, RF), rd_rm), | |
19487 | cCL("fixep", e100130, 2, (RR, RF), rd_rm), | |
19488 | cCL("fixem", e100150, 2, (RR, RF), rd_rm), | |
19489 | cCL("fixez", e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 19490 | |
c19d1205 | 19491 | /* Instructions that were new with the real FPA, call them V2. */ |
c921be7d NC |
19492 | #undef ARM_VARIANT |
19493 | #define ARM_VARIANT & fpu_fpa_ext_v2 | |
19494 | ||
21d799b5 NC |
19495 | cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
19496 | cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
19497 | cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
19498 | cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
19499 | cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
19500 | cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 | 19501 | |
c921be7d NC |
19502 | #undef ARM_VARIANT |
19503 | #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ | |
19504 | ||
c19d1205 | 19505 | /* Moves and type conversions. */ |
21d799b5 NC |
19506 | cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
19507 | cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
19508 | cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
19509 | cCE("fmstat", ef1fa10, 0, (), noargs), | |
7465e07a NC |
19510 | cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs), |
19511 | cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr), | |
21d799b5 NC |
19512 | cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), |
19513 | cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
19514 | cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
19515 | cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
19516 | cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
19517 | cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
19518 | cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn), | |
19519 | cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
19520 | |
19521 | /* Memory operations. */ | |
21d799b5 NC |
19522 | cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), |
19523 | cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), | |
55881a11 MGD |
19524 | cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), |
19525 | cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
19526 | cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
19527 | cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
19528 | cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
19529 | cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
19530 | cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
19531 | cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
19532 | cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
19533 | cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
19534 | cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
19535 | cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
19536 | cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
19537 | cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
19538 | cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
19539 | cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 19540 | |
c19d1205 | 19541 | /* Monadic operations. */ |
21d799b5 NC |
19542 | cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
19543 | cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
19544 | cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
19545 | |
19546 | /* Dyadic operations. */ | |
21d799b5 NC |
19547 | cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
19548 | cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19549 | cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19550 | cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19551 | cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19552 | cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19553 | cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19554 | cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19555 | cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 19556 | |
c19d1205 | 19557 | /* Comparisons. */ |
21d799b5 NC |
19558 | cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
19559 | cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z), | |
19560 | cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
19561 | cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 19562 | |
62f3b8c8 PB |
19563 | /* Double precision load/store are still present on single precision |
19564 | implementations. */ | |
19565 | cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
19566 | cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
55881a11 MGD |
19567 | cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), |
19568 | cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
19569 | cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
19570 | cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
19571 | cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
19572 | cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
19573 | cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
19574 | cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
62f3b8c8 | 19575 | |
c921be7d NC |
19576 | #undef ARM_VARIANT |
19577 | #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ | |
19578 | ||
c19d1205 | 19579 | /* Moves and type conversions. */ |
21d799b5 NC |
19580 | cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
19581 | cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
19582 | cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
19583 | cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
19584 | cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
19585 | cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
19586 | cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
19587 | cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
19588 | cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
19589 | cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
19590 | cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
19591 | cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
19592 | cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 | 19593 | |
c19d1205 | 19594 | /* Monadic operations. */ |
21d799b5 NC |
19595 | cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
19596 | cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), | |
19597 | cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
c19d1205 ZW |
19598 | |
19599 | /* Dyadic operations. */ | |
21d799b5 NC |
19600 | cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
19601 | cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19602 | cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19603 | cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19604 | cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19605 | cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19606 | cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19607 | cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19608 | cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
b99bd4ef | 19609 | |
c19d1205 | 19610 | /* Comparisons. */ |
21d799b5 NC |
19611 | cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
19612 | cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd), | |
19613 | cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
19614 | cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd), | |
c19d1205 | 19615 | |
c921be7d NC |
19616 | #undef ARM_VARIANT |
19617 | #define ARM_VARIANT & fpu_vfp_ext_v2 | |
19618 | ||
21d799b5 NC |
19619 | cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
19620 | cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
19621 | cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), | |
19622 | cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), | |
5287ad62 | 19623 | |
037e8744 JB |
19624 | /* Instructions which may belong to either the Neon or VFP instruction sets. |
19625 | Individual encoder functions perform additional architecture checks. */ | |
c921be7d NC |
19626 | #undef ARM_VARIANT |
19627 | #define ARM_VARIANT & fpu_vfp_ext_v1xd | |
19628 | #undef THUMB_VARIANT | |
19629 | #define THUMB_VARIANT & fpu_vfp_ext_v1xd | |
19630 | ||
037e8744 JB |
19631 | /* These mnemonics are unique to VFP. */ |
19632 | NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), | |
19633 | NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), | |
21d799b5 NC |
19634 | nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
19635 | nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
19636 | nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
aacf0b33 KT |
19637 | nCE(vcmp, _vcmp, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp), |
19638 | nCE(vcmpe, _vcmpe, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp), | |
037e8744 JB |
19639 | NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), |
19640 | NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), | |
19641 | NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), | |
19642 | ||
19643 | /* Mnemonics shared by Neon and VFP. */ | |
21d799b5 NC |
19644 | nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), |
19645 | nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
19646 | nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
037e8744 | 19647 | |
21d799b5 NC |
19648 | nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), |
19649 | nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), | |
037e8744 JB |
19650 | |
19651 | NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
19652 | NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
19653 | ||
55881a11 MGD |
19654 | NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
19655 | NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
19656 | NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
19657 | NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
19658 | NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
19659 | NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
4962c51a MS |
19660 | NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), |
19661 | NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), | |
037e8744 | 19662 | |
5f1af56b | 19663 | nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt), |
e3e535bc | 19664 | nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr), |
c70a8987 MGD |
19665 | NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb), |
19666 | NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt), | |
f31fef98 | 19667 | |
037e8744 JB |
19668 | |
19669 | /* NOTE: All VMOV encoding is special-cased! */ | |
19670 | NCE(vmov, 0, 1, (VMOV), neon_mov), | |
19671 | NCE(vmovq, 0, 1, (VMOV), neon_mov), | |
19672 | ||
c921be7d NC |
19673 | #undef THUMB_VARIANT |
19674 | #define THUMB_VARIANT & fpu_neon_ext_v1 | |
19675 | #undef ARM_VARIANT | |
19676 | #define ARM_VARIANT & fpu_neon_ext_v1 | |
19677 | ||
5287ad62 JB |
19678 | /* Data processing with three registers of the same length. */ |
19679 | /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ | |
19680 | NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), | |
19681 | NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), | |
19682 | NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
19683 | NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
19684 | NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
19685 | NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
19686 | NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
19687 | NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
19688 | /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ | |
19689 | NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
19690 | NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
19691 | NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
19692 | NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
627907b7 JB |
19693 | NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), |
19694 | NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
19695 | NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), | |
19696 | NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
5287ad62 JB |
19697 | /* If not immediate, fall back to neon_dyadic_i64_su. |
19698 | shl_imm should accept I8 I16 I32 I64, | |
19699 | qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ | |
21d799b5 NC |
19700 | nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), |
19701 | nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), | |
19702 | nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), | |
19703 | nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), | |
5287ad62 | 19704 | /* Logic ops, types optional & ignored. */ |
4316f0d2 DG |
19705 | nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), |
19706 | nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
19707 | nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
19708 | nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
19709 | nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
19710 | nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
19711 | nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
19712 | nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
19713 | nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), | |
19714 | nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic), | |
5287ad62 JB |
19715 | /* Bitfield ops, untyped. */ |
19716 | NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
19717 | NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
19718 | NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
19719 | NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
19720 | NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
19721 | NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
19722 | /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ | |
21d799b5 NC |
19723 | nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), |
19724 | nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
19725 | nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
19726 | nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
19727 | nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
19728 | nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
5287ad62 JB |
19729 | /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall |
19730 | back to neon_dyadic_if_su. */ | |
21d799b5 NC |
19731 | nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), |
19732 | nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
19733 | nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), | |
19734 | nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
19735 | nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
19736 | nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
19737 | nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
19738 | nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
428e3f1f | 19739 | /* Comparison. Type I8 I16 I32 F32. */ |
21d799b5 NC |
19740 | nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), |
19741 | nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), | |
5287ad62 | 19742 | /* As above, D registers only. */ |
21d799b5 NC |
19743 | nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), |
19744 | nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), | |
5287ad62 | 19745 | /* Int and float variants, signedness unimportant. */ |
21d799b5 NC |
19746 | nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
19747 | nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), | |
19748 | nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), | |
5287ad62 | 19749 | /* Add/sub take types I8 I16 I32 I64 F32. */ |
21d799b5 NC |
19750 | nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
19751 | nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), | |
5287ad62 JB |
19752 | /* vtst takes sizes 8, 16, 32. */ |
19753 | NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), | |
19754 | NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), | |
19755 | /* VMUL takes I8 I16 I32 F32 P8. */ | |
21d799b5 | 19756 | nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), |
5287ad62 | 19757 | /* VQD{R}MULH takes S16 S32. */ |
21d799b5 NC |
19758 | nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), |
19759 | nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
19760 | nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
19761 | nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
5287ad62 JB |
19762 | NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), |
19763 | NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
19764 | NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), | |
19765 | NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
92559b5b PB |
19766 | NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), |
19767 | NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
19768 | NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), | |
19769 | NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
5287ad62 JB |
19770 | NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), |
19771 | NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
19772 | NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), | |
19773 | NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
19774 | ||
19775 | /* Two address, int/float. Types S8 S16 S32 F32. */ | |
5287ad62 | 19776 | NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), |
5287ad62 JB |
19777 | NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), |
19778 | ||
19779 | /* Data processing with two registers and a shift amount. */ | |
19780 | /* Right shifts, and variants with rounding. | |
19781 | Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ | |
19782 | NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
19783 | NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
19784 | NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
19785 | NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
19786 | NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
19787 | NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
19788 | NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
19789 | NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
19790 | /* Shift and insert. Sizes accepted 8 16 32 64. */ | |
19791 | NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), | |
19792 | NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), | |
19793 | NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), | |
19794 | NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), | |
19795 | /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ | |
19796 | NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), | |
19797 | NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), | |
19798 | /* Right shift immediate, saturating & narrowing, with rounding variants. | |
19799 | Types accepted S16 S32 S64 U16 U32 U64. */ | |
19800 | NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
19801 | NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
19802 | /* As above, unsigned. Types accepted S16 S32 S64. */ | |
19803 | NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
19804 | NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
19805 | /* Right shift narrowing. Types accepted I16 I32 I64. */ | |
19806 | NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
19807 | NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
19808 | /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ | |
21d799b5 | 19809 | nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll), |
5287ad62 | 19810 | /* CVT with optional immediate for fixed-point variant. */ |
21d799b5 | 19811 | nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), |
b7fc2769 | 19812 | |
4316f0d2 DG |
19813 | nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn), |
19814 | nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn), | |
5287ad62 JB |
19815 | |
19816 | /* Data processing, three registers of different lengths. */ | |
19817 | /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ | |
19818 | NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), | |
19819 | NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), | |
19820 | NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), | |
19821 | NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), | |
19822 | /* If not scalar, fall back to neon_dyadic_long. | |
19823 | Vector types as above, scalar types S16 S32 U16 U32. */ | |
21d799b5 NC |
19824 | nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), |
19825 | nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), | |
5287ad62 JB |
19826 | /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ |
19827 | NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
19828 | NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
19829 | /* Dyadic, narrowing insns. Types I16 I32 I64. */ | |
19830 | NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
19831 | NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
19832 | NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
19833 | NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
19834 | /* Saturating doubling multiplies. Types S16 S32. */ | |
21d799b5 NC |
19835 | nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), |
19836 | nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
19837 | nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
5287ad62 JB |
19838 | /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types |
19839 | S16 S32 U16 U32. */ | |
21d799b5 | 19840 | nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), |
5287ad62 JB |
19841 | |
19842 | /* Extract. Size 8. */ | |
3b8d421e PB |
19843 | NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), |
19844 | NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), | |
5287ad62 JB |
19845 | |
19846 | /* Two registers, miscellaneous. */ | |
19847 | /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ | |
19848 | NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), | |
19849 | NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), | |
19850 | NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), | |
19851 | NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), | |
19852 | NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), | |
19853 | NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), | |
19854 | /* Vector replicate. Sizes 8 16 32. */ | |
21d799b5 NC |
19855 | nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup), |
19856 | nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup), | |
5287ad62 JB |
19857 | /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ |
19858 | NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), | |
19859 | /* VMOVN. Types I16 I32 I64. */ | |
21d799b5 | 19860 | nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn), |
5287ad62 | 19861 | /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ |
21d799b5 | 19862 | nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn), |
5287ad62 | 19863 | /* VQMOVUN. Types S16 S32 S64. */ |
21d799b5 | 19864 | nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun), |
5287ad62 JB |
19865 | /* VZIP / VUZP. Sizes 8 16 32. */ |
19866 | NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
19867 | NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), | |
19868 | NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
19869 | NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), | |
19870 | /* VQABS / VQNEG. Types S8 S16 S32. */ | |
19871 | NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
19872 | NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
19873 | NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
19874 | NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
19875 | /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ | |
19876 | NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), | |
19877 | NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), | |
19878 | NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), | |
19879 | NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), | |
19880 | /* Reciprocal estimates. Types U32 F32. */ | |
19881 | NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), | |
19882 | NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), | |
19883 | NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), | |
19884 | NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), | |
19885 | /* VCLS. Types S8 S16 S32. */ | |
19886 | NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), | |
19887 | NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), | |
19888 | /* VCLZ. Types I8 I16 I32. */ | |
19889 | NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), | |
19890 | NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), | |
19891 | /* VCNT. Size 8. */ | |
19892 | NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), | |
19893 | NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), | |
19894 | /* Two address, untyped. */ | |
19895 | NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), | |
19896 | NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), | |
19897 | /* VTRN. Sizes 8 16 32. */ | |
21d799b5 NC |
19898 | nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn), |
19899 | nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn), | |
5287ad62 JB |
19900 | |
19901 | /* Table lookup. Size 8. */ | |
19902 | NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
19903 | NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
19904 | ||
c921be7d NC |
19905 | #undef THUMB_VARIANT |
19906 | #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext | |
19907 | #undef ARM_VARIANT | |
19908 | #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext | |
19909 | ||
5287ad62 | 19910 | /* Neon element/structure load/store. */ |
21d799b5 NC |
19911 | nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), |
19912 | nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
19913 | nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
19914 | nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
19915 | nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
19916 | nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
19917 | nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
19918 | nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
5287ad62 | 19919 | |
c921be7d | 19920 | #undef THUMB_VARIANT |
74db7efb NC |
19921 | #define THUMB_VARIANT & fpu_vfp_ext_v3xd |
19922 | #undef ARM_VARIANT | |
19923 | #define ARM_VARIANT & fpu_vfp_ext_v3xd | |
62f3b8c8 PB |
19924 | cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const), |
19925 | cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
19926 | cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
19927 | cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
19928 | cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
19929 | cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
19930 | cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
19931 | cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
19932 | cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
19933 | ||
74db7efb | 19934 | #undef THUMB_VARIANT |
c921be7d NC |
19935 | #define THUMB_VARIANT & fpu_vfp_ext_v3 |
19936 | #undef ARM_VARIANT | |
19937 | #define ARM_VARIANT & fpu_vfp_ext_v3 | |
19938 | ||
21d799b5 | 19939 | cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const), |
21d799b5 | 19940 | cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 19941 | cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 19942 | cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 19943 | cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 19944 | cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 19945 | cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 19946 | cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 19947 | cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
c19d1205 | 19948 | |
74db7efb NC |
19949 | #undef ARM_VARIANT |
19950 | #define ARM_VARIANT & fpu_vfp_ext_fma | |
19951 | #undef THUMB_VARIANT | |
19952 | #define THUMB_VARIANT & fpu_vfp_ext_fma | |
62f3b8c8 PB |
19953 | /* Mnemonics shared by Neon and VFP. These are included in the |
19954 | VFP FMA variant; NEON and VFP FMA always includes the NEON | |
19955 | FMA instructions. */ | |
19956 | nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
19957 | nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
19958 | /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas; | |
19959 | the v form should always be used. */ | |
19960 | cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19961 | cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19962 | cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19963 | cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19964 | nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
19965 | nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
19966 | ||
5287ad62 | 19967 | #undef THUMB_VARIANT |
c921be7d NC |
19968 | #undef ARM_VARIANT |
19969 | #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */ | |
19970 | ||
21d799b5 NC |
19971 | cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
19972 | cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
19973 | cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
19974 | cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
19975 | cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
19976 | cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
19977 | cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
19978 | cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 | 19979 | |
c921be7d NC |
19980 | #undef ARM_VARIANT |
19981 | #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */ | |
19982 | ||
21d799b5 NC |
19983 | cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc), |
19984 | cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc), | |
19985 | cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc), | |
19986 | cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd), | |
19987 | cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd), | |
19988 | cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd), | |
19989 | cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc), | |
19990 | cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc), | |
19991 | cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc), | |
74db7efb NC |
19992 | cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), |
19993 | cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
19994 | cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
19995 | cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
19996 | cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
19997 | cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
21d799b5 NC |
19998 | cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), |
19999 | cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
20000 | cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
20001 | cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd), | |
20002 | cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn), | |
20003 | cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
20004 | cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
20005 | cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
20006 | cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
20007 | cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
20008 | cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
74db7efb NC |
20009 | cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn), |
20010 | cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn), | |
20011 | cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn), | |
21d799b5 NC |
20012 | cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn), |
20013 | cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm), | |
20014 | cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc), | |
20015 | cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc), | |
20016 | cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc), | |
20017 | cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn), | |
20018 | cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn), | |
20019 | cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn), | |
20020 | cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20021 | cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20022 | cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20023 | cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20024 | cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20025 | cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20026 | cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20027 | cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20028 | cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20029 | cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
74db7efb NC |
20030 | cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
20031 | cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20032 | cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20033 | cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
20034 | cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
20035 | cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20036 | cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20037 | cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20038 | cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20039 | cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20040 | cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20041 | cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20042 | cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
74db7efb NC |
20043 | cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
20044 | cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20045 | cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20046 | cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20047 | cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20048 | cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
20049 | cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), |
20050 | cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
20051 | cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
20052 | cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
20053 | cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20054 | cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20055 | cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20056 | cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20057 | cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20058 | cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20059 | cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20060 | cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20061 | cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20062 | cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20063 | cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20064 | cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20065 | cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20066 | cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20067 | cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20068 | cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20069 | cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20070 | cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20071 | cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
20072 | cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20073 | cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20074 | cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20075 | cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20076 | cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
74db7efb NC |
20077 | cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
20078 | cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20079 | cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20080 | cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20081 | cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20082 | cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
20083 | cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
20084 | cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20085 | cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20086 | cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20087 | cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20088 | cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20089 | cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20090 | cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20091 | cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20092 | cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20093 | cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
20094 | cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20095 | cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20096 | cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20097 | cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20098 | cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20099 | cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20100 | cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20101 | cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20102 | cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20103 | cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20104 | cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20105 | cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20106 | cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20107 | cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20108 | cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20109 | cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20110 | cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20111 | cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20112 | cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
20113 | cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
20114 | cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
20115 | cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
20116 | cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20117 | cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20118 | cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20119 | cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20120 | cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20121 | cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20122 | cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20123 | cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20124 | cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20125 | cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn), | |
20126 | cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn), | |
20127 | cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn), | |
20128 | cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn), | |
20129 | cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn), | |
20130 | cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn), | |
20131 | cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20132 | cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20133 | cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20134 | cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn), | |
20135 | cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn), | |
20136 | cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn), | |
20137 | cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn), | |
20138 | cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn), | |
20139 | cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn), | |
20140 | cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20141 | cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20142 | cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20143 | cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20144 | cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 | 20145 | |
c921be7d NC |
20146 | #undef ARM_VARIANT |
20147 | #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ | |
20148 | ||
21d799b5 NC |
20149 | cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc), |
20150 | cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc), | |
20151 | cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc), | |
20152 | cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn), | |
20153 | cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn), | |
20154 | cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn), | |
20155 | cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20156 | cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20157 | cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20158 | cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20159 | cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20160 | cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20161 | cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20162 | cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20163 | cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20164 | cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20165 | cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20166 | cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20167 | cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20168 | cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20169 | cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), | |
20170 | cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20171 | cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20172 | cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20173 | cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20174 | cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20175 | cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20176 | cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20177 | cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20178 | cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20179 | cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20180 | cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20181 | cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20182 | cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20183 | cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20184 | cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20185 | cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20186 | cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20187 | cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20188 | cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20189 | cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20190 | cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20191 | cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20192 | cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20193 | cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20194 | cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20195 | cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20196 | cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20197 | cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20198 | cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20199 | cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20200 | cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20201 | cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20202 | cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20203 | cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20204 | cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20205 | cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
2d447fca | 20206 | |
c921be7d NC |
20207 | #undef ARM_VARIANT |
20208 | #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */ | |
20209 | ||
21d799b5 NC |
20210 | cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), |
20211 | cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
20212 | cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
20213 | cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
20214 | cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), | |
20215 | cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
20216 | cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
20217 | cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
20218 | cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd), | |
20219 | cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn), | |
20220 | cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd), | |
20221 | cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn), | |
20222 | cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd), | |
20223 | cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn), | |
74db7efb NC |
20224 | cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd), |
20225 | cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn), | |
20226 | cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd), | |
20227 | cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn), | |
20228 | cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn), | |
20229 | cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn), | |
20230 | cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn), | |
20231 | cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn), | |
20232 | cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn), | |
20233 | cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn), | |
21d799b5 NC |
20234 | cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn), |
20235 | cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn), | |
20236 | cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn), | |
20237 | cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn), | |
74db7efb NC |
20238 | cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc), |
20239 | cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd), | |
21d799b5 NC |
20240 | cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn), |
20241 | cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn), | |
20242 | cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn), | |
20243 | cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn), | |
74db7efb NC |
20244 | cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn), |
20245 | cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn), | |
20246 | cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn), | |
20247 | cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn), | |
20248 | cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn), | |
20249 | cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn), | |
21d799b5 NC |
20250 | cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn), |
20251 | cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn), | |
74db7efb NC |
20252 | cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple), |
20253 | cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
21d799b5 NC |
20254 | cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift), |
20255 | cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
20256 | cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
20257 | cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
20258 | cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
20259 | cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
20260 | cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn), | |
20261 | cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn), | |
20262 | cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn), | |
20263 | cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn), | |
20264 | cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
20265 | cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
20266 | cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
20267 | cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
20268 | cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
20269 | cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
20270 | cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn), | |
20271 | cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn), | |
20272 | cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn), | |
20273 | cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn), | |
20274 | cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
20275 | cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
20276 | cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
20277 | cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
20278 | cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
20279 | cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
20280 | cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
20281 | cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
74db7efb NC |
20282 | cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), |
20283 | cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
21d799b5 NC |
20284 | cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), |
20285 | cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
c19d1205 ZW |
20286 | }; |
20287 | #undef ARM_VARIANT | |
20288 | #undef THUMB_VARIANT | |
20289 | #undef TCE | |
c19d1205 ZW |
20290 | #undef TUE |
20291 | #undef TUF | |
20292 | #undef TCC | |
8f06b2d8 | 20293 | #undef cCE |
e3cb604e PB |
20294 | #undef cCL |
20295 | #undef C3E | |
c19d1205 ZW |
20296 | #undef CE |
20297 | #undef CM | |
20298 | #undef UE | |
20299 | #undef UF | |
20300 | #undef UT | |
5287ad62 JB |
20301 | #undef NUF |
20302 | #undef nUF | |
20303 | #undef NCE | |
20304 | #undef nCE | |
c19d1205 ZW |
20305 | #undef OPS0 |
20306 | #undef OPS1 | |
20307 | #undef OPS2 | |
20308 | #undef OPS3 | |
20309 | #undef OPS4 | |
20310 | #undef OPS5 | |
20311 | #undef OPS6 | |
20312 | #undef do_0 | |
20313 | \f | |
20314 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 20315 | |
c19d1205 ZW |
20316 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
20317 | for use in the a.out file, and stores them in the array pointed to by buf. | |
20318 | This knows about the endian-ness of the target machine and does | |
20319 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
20320 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
20321 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 20322 | |
c19d1205 ZW |
20323 | void |
20324 | md_number_to_chars (char * buf, valueT val, int n) | |
20325 | { | |
20326 | if (target_big_endian) | |
20327 | number_to_chars_bigendian (buf, val, n); | |
20328 | else | |
20329 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
20330 | } |
20331 | ||
c19d1205 ZW |
20332 | static valueT |
20333 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 20334 | { |
c19d1205 ZW |
20335 | valueT result = 0; |
20336 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 20337 | |
c19d1205 | 20338 | if (target_big_endian) |
b99bd4ef | 20339 | { |
c19d1205 ZW |
20340 | while (n--) |
20341 | { | |
20342 | result <<= 8; | |
20343 | result |= (*where++ & 255); | |
20344 | } | |
b99bd4ef | 20345 | } |
c19d1205 | 20346 | else |
b99bd4ef | 20347 | { |
c19d1205 ZW |
20348 | while (n--) |
20349 | { | |
20350 | result <<= 8; | |
20351 | result |= (where[n] & 255); | |
20352 | } | |
bfae80f2 | 20353 | } |
b99bd4ef | 20354 | |
c19d1205 | 20355 | return result; |
bfae80f2 | 20356 | } |
b99bd4ef | 20357 | |
c19d1205 | 20358 | /* MD interface: Sections. */ |
b99bd4ef | 20359 | |
fa94de6b RM |
20360 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
20361 | that an rs_machine_dependent frag may reach. */ | |
20362 | ||
20363 | unsigned int | |
20364 | arm_frag_max_var (fragS *fragp) | |
20365 | { | |
20366 | /* We only use rs_machine_dependent for variable-size Thumb instructions, | |
20367 | which are either THUMB_SIZE (2) or INSN_SIZE (4). | |
20368 | ||
20369 | Note that we generate relaxable instructions even for cases that don't | |
20370 | really need it, like an immediate that's a trivial constant. So we're | |
20371 | overestimating the instruction size for some of those cases. Rather | |
20372 | than putting more intelligence here, it would probably be better to | |
20373 | avoid generating a relaxation frag in the first place when it can be | |
20374 | determined up front that a short instruction will suffice. */ | |
20375 | ||
20376 | gas_assert (fragp->fr_type == rs_machine_dependent); | |
20377 | return INSN_SIZE; | |
20378 | } | |
20379 | ||
0110f2b8 PB |
20380 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
20381 | 2 bytes. */ | |
20382 | ||
c19d1205 | 20383 | int |
0110f2b8 | 20384 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
20385 | segT segtype ATTRIBUTE_UNUSED) |
20386 | { | |
0110f2b8 PB |
20387 | fragp->fr_var = 2; |
20388 | return 2; | |
20389 | } | |
20390 | ||
20391 | /* Convert a machine dependent frag. */ | |
20392 | ||
20393 | void | |
20394 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
20395 | { | |
20396 | unsigned long insn; | |
20397 | unsigned long old_op; | |
20398 | char *buf; | |
20399 | expressionS exp; | |
20400 | fixS *fixp; | |
20401 | int reloc_type; | |
20402 | int pc_rel; | |
20403 | int opcode; | |
20404 | ||
20405 | buf = fragp->fr_literal + fragp->fr_fix; | |
20406 | ||
20407 | old_op = bfd_get_16(abfd, buf); | |
5f4273c7 NC |
20408 | if (fragp->fr_symbol) |
20409 | { | |
0110f2b8 PB |
20410 | exp.X_op = O_symbol; |
20411 | exp.X_add_symbol = fragp->fr_symbol; | |
5f4273c7 NC |
20412 | } |
20413 | else | |
20414 | { | |
0110f2b8 | 20415 | exp.X_op = O_constant; |
5f4273c7 | 20416 | } |
0110f2b8 PB |
20417 | exp.X_add_number = fragp->fr_offset; |
20418 | opcode = fragp->fr_subtype; | |
20419 | switch (opcode) | |
20420 | { | |
20421 | case T_MNEM_ldr_pc: | |
20422 | case T_MNEM_ldr_pc2: | |
20423 | case T_MNEM_ldr_sp: | |
20424 | case T_MNEM_str_sp: | |
20425 | case T_MNEM_ldr: | |
20426 | case T_MNEM_ldrb: | |
20427 | case T_MNEM_ldrh: | |
20428 | case T_MNEM_str: | |
20429 | case T_MNEM_strb: | |
20430 | case T_MNEM_strh: | |
20431 | if (fragp->fr_var == 4) | |
20432 | { | |
5f4273c7 | 20433 | insn = THUMB_OP32 (opcode); |
0110f2b8 PB |
20434 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) |
20435 | { | |
20436 | insn |= (old_op & 0x700) << 4; | |
20437 | } | |
20438 | else | |
20439 | { | |
20440 | insn |= (old_op & 7) << 12; | |
20441 | insn |= (old_op & 0x38) << 13; | |
20442 | } | |
20443 | insn |= 0x00000c00; | |
20444 | put_thumb32_insn (buf, insn); | |
20445 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
20446 | } | |
20447 | else | |
20448 | { | |
20449 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
20450 | } | |
20451 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
20452 | break; | |
20453 | case T_MNEM_adr: | |
20454 | if (fragp->fr_var == 4) | |
20455 | { | |
20456 | insn = THUMB_OP32 (opcode); | |
20457 | insn |= (old_op & 0xf0) << 4; | |
20458 | put_thumb32_insn (buf, insn); | |
20459 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
20460 | } | |
20461 | else | |
20462 | { | |
20463 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
20464 | exp.X_add_number -= 4; | |
20465 | } | |
20466 | pc_rel = 1; | |
20467 | break; | |
20468 | case T_MNEM_mov: | |
20469 | case T_MNEM_movs: | |
20470 | case T_MNEM_cmp: | |
20471 | case T_MNEM_cmn: | |
20472 | if (fragp->fr_var == 4) | |
20473 | { | |
20474 | int r0off = (opcode == T_MNEM_mov | |
20475 | || opcode == T_MNEM_movs) ? 0 : 8; | |
20476 | insn = THUMB_OP32 (opcode); | |
20477 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
20478 | insn |= (old_op & 0x700) << r0off; | |
20479 | put_thumb32_insn (buf, insn); | |
20480 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
20481 | } | |
20482 | else | |
20483 | { | |
20484 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
20485 | } | |
20486 | pc_rel = 0; | |
20487 | break; | |
20488 | case T_MNEM_b: | |
20489 | if (fragp->fr_var == 4) | |
20490 | { | |
20491 | insn = THUMB_OP32(opcode); | |
20492 | put_thumb32_insn (buf, insn); | |
20493 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
20494 | } | |
20495 | else | |
20496 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
20497 | pc_rel = 1; | |
20498 | break; | |
20499 | case T_MNEM_bcond: | |
20500 | if (fragp->fr_var == 4) | |
20501 | { | |
20502 | insn = THUMB_OP32(opcode); | |
20503 | insn |= (old_op & 0xf00) << 14; | |
20504 | put_thumb32_insn (buf, insn); | |
20505 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
20506 | } | |
20507 | else | |
20508 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
20509 | pc_rel = 1; | |
20510 | break; | |
20511 | case T_MNEM_add_sp: | |
20512 | case T_MNEM_add_pc: | |
20513 | case T_MNEM_inc_sp: | |
20514 | case T_MNEM_dec_sp: | |
20515 | if (fragp->fr_var == 4) | |
20516 | { | |
20517 | /* ??? Choose between add and addw. */ | |
20518 | insn = THUMB_OP32 (opcode); | |
20519 | insn |= (old_op & 0xf0) << 4; | |
20520 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
20521 | if (opcode == T_MNEM_add_pc) |
20522 | reloc_type = BFD_RELOC_ARM_T32_IMM12; | |
20523 | else | |
20524 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
0110f2b8 PB |
20525 | } |
20526 | else | |
20527 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
20528 | pc_rel = 0; | |
20529 | break; | |
20530 | ||
20531 | case T_MNEM_addi: | |
20532 | case T_MNEM_addis: | |
20533 | case T_MNEM_subi: | |
20534 | case T_MNEM_subis: | |
20535 | if (fragp->fr_var == 4) | |
20536 | { | |
20537 | insn = THUMB_OP32 (opcode); | |
20538 | insn |= (old_op & 0xf0) << 4; | |
20539 | insn |= (old_op & 0xf) << 16; | |
20540 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
20541 | if (insn & (1 << 20)) |
20542 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
20543 | else | |
20544 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
0110f2b8 PB |
20545 | } |
20546 | else | |
20547 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
20548 | pc_rel = 0; | |
20549 | break; | |
20550 | default: | |
5f4273c7 | 20551 | abort (); |
0110f2b8 PB |
20552 | } |
20553 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
21d799b5 | 20554 | (enum bfd_reloc_code_real) reloc_type); |
0110f2b8 PB |
20555 | fixp->fx_file = fragp->fr_file; |
20556 | fixp->fx_line = fragp->fr_line; | |
20557 | fragp->fr_fix += fragp->fr_var; | |
3cfdb781 TG |
20558 | |
20559 | /* Set whether we use thumb-2 ISA based on final relaxation results. */ | |
20560 | if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected () | |
20561 | && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2)) | |
20562 | ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2); | |
0110f2b8 PB |
20563 | } |
20564 | ||
20565 | /* Return the size of a relaxable immediate operand instruction. | |
20566 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
20567 | static int | |
20568 | relax_immediate (fragS *fragp, int size, int shift) | |
20569 | { | |
20570 | offsetT offset; | |
20571 | offsetT mask; | |
20572 | offsetT low; | |
20573 | ||
20574 | /* ??? Should be able to do better than this. */ | |
20575 | if (fragp->fr_symbol) | |
20576 | return 4; | |
20577 | ||
20578 | low = (1 << shift) - 1; | |
20579 | mask = (1 << (shift + size)) - (1 << shift); | |
20580 | offset = fragp->fr_offset; | |
20581 | /* Force misaligned offsets to 32-bit variant. */ | |
20582 | if (offset & low) | |
5e77afaa | 20583 | return 4; |
0110f2b8 PB |
20584 | if (offset & ~mask) |
20585 | return 4; | |
20586 | return 2; | |
20587 | } | |
20588 | ||
5e77afaa PB |
20589 | /* Get the address of a symbol during relaxation. */ |
20590 | static addressT | |
5f4273c7 | 20591 | relaxed_symbol_addr (fragS *fragp, long stretch) |
5e77afaa PB |
20592 | { |
20593 | fragS *sym_frag; | |
20594 | addressT addr; | |
20595 | symbolS *sym; | |
20596 | ||
20597 | sym = fragp->fr_symbol; | |
20598 | sym_frag = symbol_get_frag (sym); | |
20599 | know (S_GET_SEGMENT (sym) != absolute_section | |
20600 | || sym_frag == &zero_address_frag); | |
20601 | addr = S_GET_VALUE (sym) + fragp->fr_offset; | |
20602 | ||
20603 | /* If frag has yet to be reached on this pass, assume it will | |
20604 | move by STRETCH just as we did. If this is not so, it will | |
20605 | be because some frag between grows, and that will force | |
20606 | another pass. */ | |
20607 | ||
20608 | if (stretch != 0 | |
20609 | && sym_frag->relax_marker != fragp->relax_marker) | |
4396b686 PB |
20610 | { |
20611 | fragS *f; | |
20612 | ||
20613 | /* Adjust stretch for any alignment frag. Note that if have | |
20614 | been expanding the earlier code, the symbol may be | |
20615 | defined in what appears to be an earlier frag. FIXME: | |
20616 | This doesn't handle the fr_subtype field, which specifies | |
20617 | a maximum number of bytes to skip when doing an | |
20618 | alignment. */ | |
20619 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
20620 | { | |
20621 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
20622 | { | |
20623 | if (stretch < 0) | |
20624 | stretch = - ((- stretch) | |
20625 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
20626 | else | |
20627 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
20628 | if (stretch == 0) | |
20629 | break; | |
20630 | } | |
20631 | } | |
20632 | if (f != NULL) | |
20633 | addr += stretch; | |
20634 | } | |
5e77afaa PB |
20635 | |
20636 | return addr; | |
20637 | } | |
20638 | ||
0110f2b8 PB |
20639 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative |
20640 | load. */ | |
20641 | static int | |
5e77afaa | 20642 | relax_adr (fragS *fragp, asection *sec, long stretch) |
0110f2b8 PB |
20643 | { |
20644 | addressT addr; | |
20645 | offsetT val; | |
20646 | ||
20647 | /* Assume worst case for symbols not known to be in the same section. */ | |
974da60d NC |
20648 | if (fragp->fr_symbol == NULL |
20649 | || !S_IS_DEFINED (fragp->fr_symbol) | |
77db8e2e NC |
20650 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
20651 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
20652 | return 4; |
20653 | ||
5f4273c7 | 20654 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
20655 | addr = fragp->fr_address + fragp->fr_fix; |
20656 | addr = (addr + 4) & ~3; | |
5e77afaa | 20657 | /* Force misaligned targets to 32-bit variant. */ |
0110f2b8 | 20658 | if (val & 3) |
5e77afaa | 20659 | return 4; |
0110f2b8 PB |
20660 | val -= addr; |
20661 | if (val < 0 || val > 1020) | |
20662 | return 4; | |
20663 | return 2; | |
20664 | } | |
20665 | ||
20666 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
20667 | static int | |
20668 | relax_addsub (fragS *fragp, asection *sec) | |
20669 | { | |
20670 | char *buf; | |
20671 | int op; | |
20672 | ||
20673 | buf = fragp->fr_literal + fragp->fr_fix; | |
20674 | op = bfd_get_16(sec->owner, buf); | |
20675 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
20676 | return relax_immediate (fragp, 8, 0); | |
20677 | else | |
20678 | return relax_immediate (fragp, 3, 0); | |
20679 | } | |
20680 | ||
e83a675f RE |
20681 | /* Return TRUE iff the definition of symbol S could be pre-empted |
20682 | (overridden) at link or load time. */ | |
20683 | static bfd_boolean | |
20684 | symbol_preemptible (symbolS *s) | |
20685 | { | |
20686 | /* Weak symbols can always be pre-empted. */ | |
20687 | if (S_IS_WEAK (s)) | |
20688 | return TRUE; | |
20689 | ||
20690 | /* Non-global symbols cannot be pre-empted. */ | |
20691 | if (! S_IS_EXTERNAL (s)) | |
20692 | return FALSE; | |
20693 | ||
20694 | #ifdef OBJ_ELF | |
20695 | /* In ELF, a global symbol can be marked protected, or private. In that | |
20696 | case it can't be pre-empted (other definitions in the same link unit | |
20697 | would violate the ODR). */ | |
20698 | if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT) | |
20699 | return FALSE; | |
20700 | #endif | |
20701 | ||
20702 | /* Other global symbols might be pre-empted. */ | |
20703 | return TRUE; | |
20704 | } | |
0110f2b8 PB |
20705 | |
20706 | /* Return the size of a relaxable branch instruction. BITS is the | |
20707 | size of the offset field in the narrow instruction. */ | |
20708 | ||
20709 | static int | |
5e77afaa | 20710 | relax_branch (fragS *fragp, asection *sec, int bits, long stretch) |
0110f2b8 PB |
20711 | { |
20712 | addressT addr; | |
20713 | offsetT val; | |
20714 | offsetT limit; | |
20715 | ||
20716 | /* Assume worst case for symbols not known to be in the same section. */ | |
5f4273c7 | 20717 | if (!S_IS_DEFINED (fragp->fr_symbol) |
77db8e2e NC |
20718 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
20719 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
20720 | return 4; |
20721 | ||
267bf995 | 20722 | #ifdef OBJ_ELF |
e83a675f | 20723 | /* A branch to a function in ARM state will require interworking. */ |
267bf995 RR |
20724 | if (S_IS_DEFINED (fragp->fr_symbol) |
20725 | && ARM_IS_FUNC (fragp->fr_symbol)) | |
20726 | return 4; | |
e83a675f | 20727 | #endif |
0d9b4b55 | 20728 | |
e83a675f | 20729 | if (symbol_preemptible (fragp->fr_symbol)) |
0d9b4b55 | 20730 | return 4; |
267bf995 | 20731 | |
5f4273c7 | 20732 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
20733 | addr = fragp->fr_address + fragp->fr_fix + 4; |
20734 | val -= addr; | |
20735 | ||
20736 | /* Offset is a signed value *2 */ | |
20737 | limit = 1 << bits; | |
20738 | if (val >= limit || val < -limit) | |
20739 | return 4; | |
20740 | return 2; | |
20741 | } | |
20742 | ||
20743 | ||
20744 | /* Relax a machine dependent frag. This returns the amount by which | |
20745 | the current size of the frag should change. */ | |
20746 | ||
20747 | int | |
5e77afaa | 20748 | arm_relax_frag (asection *sec, fragS *fragp, long stretch) |
0110f2b8 PB |
20749 | { |
20750 | int oldsize; | |
20751 | int newsize; | |
20752 | ||
20753 | oldsize = fragp->fr_var; | |
20754 | switch (fragp->fr_subtype) | |
20755 | { | |
20756 | case T_MNEM_ldr_pc2: | |
5f4273c7 | 20757 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
20758 | break; |
20759 | case T_MNEM_ldr_pc: | |
20760 | case T_MNEM_ldr_sp: | |
20761 | case T_MNEM_str_sp: | |
5f4273c7 | 20762 | newsize = relax_immediate (fragp, 8, 2); |
0110f2b8 PB |
20763 | break; |
20764 | case T_MNEM_ldr: | |
20765 | case T_MNEM_str: | |
5f4273c7 | 20766 | newsize = relax_immediate (fragp, 5, 2); |
0110f2b8 PB |
20767 | break; |
20768 | case T_MNEM_ldrh: | |
20769 | case T_MNEM_strh: | |
5f4273c7 | 20770 | newsize = relax_immediate (fragp, 5, 1); |
0110f2b8 PB |
20771 | break; |
20772 | case T_MNEM_ldrb: | |
20773 | case T_MNEM_strb: | |
5f4273c7 | 20774 | newsize = relax_immediate (fragp, 5, 0); |
0110f2b8 PB |
20775 | break; |
20776 | case T_MNEM_adr: | |
5f4273c7 | 20777 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
20778 | break; |
20779 | case T_MNEM_mov: | |
20780 | case T_MNEM_movs: | |
20781 | case T_MNEM_cmp: | |
20782 | case T_MNEM_cmn: | |
5f4273c7 | 20783 | newsize = relax_immediate (fragp, 8, 0); |
0110f2b8 PB |
20784 | break; |
20785 | case T_MNEM_b: | |
5f4273c7 | 20786 | newsize = relax_branch (fragp, sec, 11, stretch); |
0110f2b8 PB |
20787 | break; |
20788 | case T_MNEM_bcond: | |
5f4273c7 | 20789 | newsize = relax_branch (fragp, sec, 8, stretch); |
0110f2b8 PB |
20790 | break; |
20791 | case T_MNEM_add_sp: | |
20792 | case T_MNEM_add_pc: | |
20793 | newsize = relax_immediate (fragp, 8, 2); | |
20794 | break; | |
20795 | case T_MNEM_inc_sp: | |
20796 | case T_MNEM_dec_sp: | |
20797 | newsize = relax_immediate (fragp, 7, 2); | |
20798 | break; | |
20799 | case T_MNEM_addi: | |
20800 | case T_MNEM_addis: | |
20801 | case T_MNEM_subi: | |
20802 | case T_MNEM_subis: | |
20803 | newsize = relax_addsub (fragp, sec); | |
20804 | break; | |
20805 | default: | |
5f4273c7 | 20806 | abort (); |
0110f2b8 | 20807 | } |
5e77afaa PB |
20808 | |
20809 | fragp->fr_var = newsize; | |
20810 | /* Freeze wide instructions that are at or before the same location as | |
20811 | in the previous pass. This avoids infinite loops. | |
5f4273c7 NC |
20812 | Don't freeze them unconditionally because targets may be artificially |
20813 | misaligned by the expansion of preceding frags. */ | |
5e77afaa | 20814 | if (stretch <= 0 && newsize > 2) |
0110f2b8 | 20815 | { |
0110f2b8 | 20816 | md_convert_frag (sec->owner, sec, fragp); |
5f4273c7 | 20817 | frag_wane (fragp); |
0110f2b8 | 20818 | } |
5e77afaa | 20819 | |
0110f2b8 | 20820 | return newsize - oldsize; |
c19d1205 | 20821 | } |
b99bd4ef | 20822 | |
c19d1205 | 20823 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 20824 | |
c19d1205 ZW |
20825 | valueT |
20826 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
20827 | valueT size) | |
20828 | { | |
f0927246 NC |
20829 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
20830 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
20831 | { | |
20832 | /* For a.out, force the section size to be aligned. If we don't do | |
20833 | this, BFD will align it for us, but it will not write out the | |
20834 | final bytes of the section. This may be a bug in BFD, but it is | |
20835 | easier to fix it here since that is how the other a.out targets | |
20836 | work. */ | |
20837 | int align; | |
20838 | ||
20839 | align = bfd_get_section_alignment (stdoutput, segment); | |
20840 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
20841 | } | |
c19d1205 | 20842 | #endif |
f0927246 NC |
20843 | |
20844 | return size; | |
bfae80f2 | 20845 | } |
b99bd4ef | 20846 | |
c19d1205 ZW |
20847 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
20848 | of an rs_align_code fragment. */ | |
20849 | ||
20850 | void | |
20851 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 20852 | { |
e7495e45 NS |
20853 | static char const arm_noop[2][2][4] = |
20854 | { | |
20855 | { /* ARMv1 */ | |
20856 | {0x00, 0x00, 0xa0, 0xe1}, /* LE */ | |
20857 | {0xe1, 0xa0, 0x00, 0x00}, /* BE */ | |
20858 | }, | |
20859 | { /* ARMv6k */ | |
20860 | {0x00, 0xf0, 0x20, 0xe3}, /* LE */ | |
20861 | {0xe3, 0x20, 0xf0, 0x00}, /* BE */ | |
20862 | }, | |
20863 | }; | |
20864 | static char const thumb_noop[2][2][2] = | |
20865 | { | |
20866 | { /* Thumb-1 */ | |
20867 | {0xc0, 0x46}, /* LE */ | |
20868 | {0x46, 0xc0}, /* BE */ | |
20869 | }, | |
20870 | { /* Thumb-2 */ | |
20871 | {0x00, 0xbf}, /* LE */ | |
20872 | {0xbf, 0x00} /* BE */ | |
20873 | } | |
20874 | }; | |
20875 | static char const wide_thumb_noop[2][4] = | |
20876 | { /* Wide Thumb-2 */ | |
20877 | {0xaf, 0xf3, 0x00, 0x80}, /* LE */ | |
20878 | {0xf3, 0xaf, 0x80, 0x00}, /* BE */ | |
20879 | }; | |
c921be7d | 20880 | |
e7495e45 | 20881 | unsigned bytes, fix, noop_size; |
c19d1205 ZW |
20882 | char * p; |
20883 | const char * noop; | |
e7495e45 | 20884 | const char *narrow_noop = NULL; |
cd000bff DJ |
20885 | #ifdef OBJ_ELF |
20886 | enum mstate state; | |
20887 | #endif | |
bfae80f2 | 20888 | |
c19d1205 | 20889 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
20890 | return; |
20891 | ||
c19d1205 ZW |
20892 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
20893 | p = fragP->fr_literal + fragP->fr_fix; | |
20894 | fix = 0; | |
bfae80f2 | 20895 | |
c19d1205 ZW |
20896 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
20897 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 20898 | |
cd000bff | 20899 | gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0); |
8dc2430f | 20900 | |
cd000bff | 20901 | if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED)) |
a737bd4d | 20902 | { |
7f78eb34 JW |
20903 | if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0] |
20904 | ? selected_cpu : arm_arch_none, arm_ext_v6t2)) | |
e7495e45 NS |
20905 | { |
20906 | narrow_noop = thumb_noop[1][target_big_endian]; | |
20907 | noop = wide_thumb_noop[target_big_endian]; | |
20908 | } | |
c19d1205 | 20909 | else |
e7495e45 NS |
20910 | noop = thumb_noop[0][target_big_endian]; |
20911 | noop_size = 2; | |
cd000bff DJ |
20912 | #ifdef OBJ_ELF |
20913 | state = MAP_THUMB; | |
20914 | #endif | |
7ed4c4c5 NC |
20915 | } |
20916 | else | |
20917 | { | |
7f78eb34 JW |
20918 | noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0] |
20919 | ? selected_cpu : arm_arch_none, | |
20920 | arm_ext_v6k) != 0] | |
e7495e45 NS |
20921 | [target_big_endian]; |
20922 | noop_size = 4; | |
cd000bff DJ |
20923 | #ifdef OBJ_ELF |
20924 | state = MAP_ARM; | |
20925 | #endif | |
7ed4c4c5 | 20926 | } |
c921be7d | 20927 | |
e7495e45 | 20928 | fragP->fr_var = noop_size; |
c921be7d | 20929 | |
c19d1205 | 20930 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 20931 | { |
c19d1205 | 20932 | fix = bytes & (noop_size - 1); |
cd000bff DJ |
20933 | #ifdef OBJ_ELF |
20934 | insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix); | |
20935 | #endif | |
c19d1205 ZW |
20936 | memset (p, 0, fix); |
20937 | p += fix; | |
20938 | bytes -= fix; | |
a737bd4d | 20939 | } |
a737bd4d | 20940 | |
e7495e45 NS |
20941 | if (narrow_noop) |
20942 | { | |
20943 | if (bytes & noop_size) | |
20944 | { | |
20945 | /* Insert a narrow noop. */ | |
20946 | memcpy (p, narrow_noop, noop_size); | |
20947 | p += noop_size; | |
20948 | bytes -= noop_size; | |
20949 | fix += noop_size; | |
20950 | } | |
20951 | ||
20952 | /* Use wide noops for the remainder */ | |
20953 | noop_size = 4; | |
20954 | } | |
20955 | ||
c19d1205 | 20956 | while (bytes >= noop_size) |
a737bd4d | 20957 | { |
c19d1205 ZW |
20958 | memcpy (p, noop, noop_size); |
20959 | p += noop_size; | |
20960 | bytes -= noop_size; | |
20961 | fix += noop_size; | |
a737bd4d NC |
20962 | } |
20963 | ||
c19d1205 | 20964 | fragP->fr_fix += fix; |
a737bd4d NC |
20965 | } |
20966 | ||
c19d1205 ZW |
20967 | /* Called from md_do_align. Used to create an alignment |
20968 | frag in a code section. */ | |
20969 | ||
20970 | void | |
20971 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 20972 | { |
c19d1205 | 20973 | char * p; |
7ed4c4c5 | 20974 | |
c19d1205 | 20975 | /* We assume that there will never be a requirement |
6ec8e702 | 20976 | to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */ |
c19d1205 | 20977 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) |
6ec8e702 NC |
20978 | { |
20979 | char err_msg[128]; | |
20980 | ||
fa94de6b | 20981 | sprintf (err_msg, |
477330fc RM |
20982 | _("alignments greater than %d bytes not supported in .text sections."), |
20983 | MAX_MEM_FOR_RS_ALIGN_CODE + 1); | |
20203fb9 | 20984 | as_fatal ("%s", err_msg); |
6ec8e702 | 20985 | } |
bfae80f2 | 20986 | |
c19d1205 ZW |
20987 | p = frag_var (rs_align_code, |
20988 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
20989 | 1, | |
20990 | (relax_substateT) max, | |
20991 | (symbolS *) NULL, | |
20992 | (offsetT) n, | |
20993 | (char *) NULL); | |
20994 | *p = 0; | |
20995 | } | |
bfae80f2 | 20996 | |
8dc2430f NC |
20997 | /* Perform target specific initialisation of a frag. |
20998 | Note - despite the name this initialisation is not done when the frag | |
20999 | is created, but only when its type is assigned. A frag can be created | |
21000 | and used a long time before its type is set, so beware of assuming that | |
21001 | this initialisationis performed first. */ | |
bfae80f2 | 21002 | |
cd000bff DJ |
21003 | #ifndef OBJ_ELF |
21004 | void | |
21005 | arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED) | |
21006 | { | |
21007 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
2e98972e | 21008 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
cd000bff DJ |
21009 | } |
21010 | ||
21011 | #else /* OBJ_ELF is defined. */ | |
c19d1205 | 21012 | void |
cd000bff | 21013 | arm_init_frag (fragS * fragP, int max_chars) |
c19d1205 | 21014 | { |
8dc2430f NC |
21015 | /* If the current ARM vs THUMB mode has not already |
21016 | been recorded into this frag then do so now. */ | |
cd000bff DJ |
21017 | if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0) |
21018 | { | |
21019 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; | |
21020 | ||
21021 | /* Record a mapping symbol for alignment frags. We will delete this | |
21022 | later if the alignment ends up empty. */ | |
21023 | switch (fragP->fr_type) | |
21024 | { | |
21025 | case rs_align: | |
21026 | case rs_align_test: | |
21027 | case rs_fill: | |
21028 | mapping_state_2 (MAP_DATA, max_chars); | |
21029 | break; | |
21030 | case rs_align_code: | |
21031 | mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars); | |
21032 | break; | |
21033 | default: | |
21034 | break; | |
21035 | } | |
21036 | } | |
bfae80f2 RE |
21037 | } |
21038 | ||
c19d1205 ZW |
21039 | /* When we change sections we need to issue a new mapping symbol. */ |
21040 | ||
21041 | void | |
21042 | arm_elf_change_section (void) | |
bfae80f2 | 21043 | { |
c19d1205 ZW |
21044 | /* Link an unlinked unwind index table section to the .text section. */ |
21045 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
21046 | && elf_linked_to_section (now_seg) == NULL) | |
21047 | elf_linked_to_section (now_seg) = text_section; | |
bfae80f2 RE |
21048 | } |
21049 | ||
c19d1205 ZW |
21050 | int |
21051 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 21052 | { |
c19d1205 ZW |
21053 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
21054 | return SHT_ARM_EXIDX; | |
e45d0630 | 21055 | |
c19d1205 ZW |
21056 | return -1; |
21057 | } | |
21058 | \f | |
21059 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 21060 | |
c19d1205 | 21061 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 21062 | |
5f4273c7 | 21063 | /* Generate any deferred unwind frame offset. */ |
e45d0630 | 21064 | |
bfae80f2 | 21065 | static void |
c19d1205 | 21066 | flush_pending_unwind (void) |
bfae80f2 | 21067 | { |
c19d1205 | 21068 | offsetT offset; |
bfae80f2 | 21069 | |
c19d1205 ZW |
21070 | offset = unwind.pending_offset; |
21071 | unwind.pending_offset = 0; | |
21072 | if (offset != 0) | |
21073 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
21074 | } |
21075 | ||
c19d1205 ZW |
21076 | /* Add an opcode to this list for this function. Two-byte opcodes should |
21077 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
21078 | order. */ | |
21079 | ||
bfae80f2 | 21080 | static void |
c19d1205 | 21081 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 21082 | { |
c19d1205 ZW |
21083 | /* Add any deferred stack adjustment. */ |
21084 | if (unwind.pending_offset) | |
21085 | flush_pending_unwind (); | |
bfae80f2 | 21086 | |
c19d1205 | 21087 | unwind.sp_restored = 0; |
bfae80f2 | 21088 | |
c19d1205 | 21089 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 21090 | { |
c19d1205 ZW |
21091 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
21092 | if (unwind.opcodes) | |
21d799b5 | 21093 | unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes, |
477330fc | 21094 | unwind.opcode_alloc); |
c19d1205 | 21095 | else |
21d799b5 | 21096 | unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc); |
bfae80f2 | 21097 | } |
c19d1205 | 21098 | while (length > 0) |
bfae80f2 | 21099 | { |
c19d1205 ZW |
21100 | length--; |
21101 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
21102 | op >>= 8; | |
21103 | unwind.opcode_count++; | |
bfae80f2 | 21104 | } |
bfae80f2 RE |
21105 | } |
21106 | ||
c19d1205 ZW |
21107 | /* Add unwind opcodes to adjust the stack pointer. */ |
21108 | ||
bfae80f2 | 21109 | static void |
c19d1205 | 21110 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 21111 | { |
c19d1205 | 21112 | valueT op; |
bfae80f2 | 21113 | |
c19d1205 | 21114 | if (offset > 0x200) |
bfae80f2 | 21115 | { |
c19d1205 ZW |
21116 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
21117 | char bytes[5]; | |
21118 | int n; | |
21119 | valueT o; | |
bfae80f2 | 21120 | |
c19d1205 ZW |
21121 | /* Long form: 0xb2, uleb128. */ |
21122 | /* This might not fit in a word so add the individual bytes, | |
21123 | remembering the list is built in reverse order. */ | |
21124 | o = (valueT) ((offset - 0x204) >> 2); | |
21125 | if (o == 0) | |
21126 | add_unwind_opcode (0, 1); | |
bfae80f2 | 21127 | |
c19d1205 ZW |
21128 | /* Calculate the uleb128 encoding of the offset. */ |
21129 | n = 0; | |
21130 | while (o) | |
21131 | { | |
21132 | bytes[n] = o & 0x7f; | |
21133 | o >>= 7; | |
21134 | if (o) | |
21135 | bytes[n] |= 0x80; | |
21136 | n++; | |
21137 | } | |
21138 | /* Add the insn. */ | |
21139 | for (; n; n--) | |
21140 | add_unwind_opcode (bytes[n - 1], 1); | |
21141 | add_unwind_opcode (0xb2, 1); | |
21142 | } | |
21143 | else if (offset > 0x100) | |
bfae80f2 | 21144 | { |
c19d1205 ZW |
21145 | /* Two short opcodes. */ |
21146 | add_unwind_opcode (0x3f, 1); | |
21147 | op = (offset - 0x104) >> 2; | |
21148 | add_unwind_opcode (op, 1); | |
bfae80f2 | 21149 | } |
c19d1205 ZW |
21150 | else if (offset > 0) |
21151 | { | |
21152 | /* Short opcode. */ | |
21153 | op = (offset - 4) >> 2; | |
21154 | add_unwind_opcode (op, 1); | |
21155 | } | |
21156 | else if (offset < 0) | |
bfae80f2 | 21157 | { |
c19d1205 ZW |
21158 | offset = -offset; |
21159 | while (offset > 0x100) | |
bfae80f2 | 21160 | { |
c19d1205 ZW |
21161 | add_unwind_opcode (0x7f, 1); |
21162 | offset -= 0x100; | |
bfae80f2 | 21163 | } |
c19d1205 ZW |
21164 | op = ((offset - 4) >> 2) | 0x40; |
21165 | add_unwind_opcode (op, 1); | |
bfae80f2 | 21166 | } |
bfae80f2 RE |
21167 | } |
21168 | ||
c19d1205 ZW |
21169 | /* Finish the list of unwind opcodes for this function. */ |
21170 | static void | |
21171 | finish_unwind_opcodes (void) | |
bfae80f2 | 21172 | { |
c19d1205 | 21173 | valueT op; |
bfae80f2 | 21174 | |
c19d1205 | 21175 | if (unwind.fp_used) |
bfae80f2 | 21176 | { |
708587a4 | 21177 | /* Adjust sp as necessary. */ |
c19d1205 ZW |
21178 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; |
21179 | flush_pending_unwind (); | |
bfae80f2 | 21180 | |
c19d1205 ZW |
21181 | /* After restoring sp from the frame pointer. */ |
21182 | op = 0x90 | unwind.fp_reg; | |
21183 | add_unwind_opcode (op, 1); | |
21184 | } | |
21185 | else | |
21186 | flush_pending_unwind (); | |
bfae80f2 RE |
21187 | } |
21188 | ||
bfae80f2 | 21189 | |
c19d1205 ZW |
21190 | /* Start an exception table entry. If idx is nonzero this is an index table |
21191 | entry. */ | |
bfae80f2 RE |
21192 | |
21193 | static void | |
c19d1205 | 21194 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 21195 | { |
c19d1205 ZW |
21196 | const char * text_name; |
21197 | const char * prefix; | |
21198 | const char * prefix_once; | |
21199 | const char * group_name; | |
21200 | size_t prefix_len; | |
21201 | size_t text_len; | |
21202 | char * sec_name; | |
21203 | size_t sec_name_len; | |
21204 | int type; | |
21205 | int flags; | |
21206 | int linkonce; | |
bfae80f2 | 21207 | |
c19d1205 | 21208 | if (idx) |
bfae80f2 | 21209 | { |
c19d1205 ZW |
21210 | prefix = ELF_STRING_ARM_unwind; |
21211 | prefix_once = ELF_STRING_ARM_unwind_once; | |
21212 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 21213 | } |
c19d1205 | 21214 | else |
bfae80f2 | 21215 | { |
c19d1205 ZW |
21216 | prefix = ELF_STRING_ARM_unwind_info; |
21217 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
21218 | type = SHT_PROGBITS; | |
bfae80f2 RE |
21219 | } |
21220 | ||
c19d1205 ZW |
21221 | text_name = segment_name (text_seg); |
21222 | if (streq (text_name, ".text")) | |
21223 | text_name = ""; | |
21224 | ||
21225 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
21226 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 21227 | { |
c19d1205 ZW |
21228 | prefix = prefix_once; |
21229 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
21230 | } |
21231 | ||
c19d1205 ZW |
21232 | prefix_len = strlen (prefix); |
21233 | text_len = strlen (text_name); | |
21234 | sec_name_len = prefix_len + text_len; | |
21d799b5 | 21235 | sec_name = (char *) xmalloc (sec_name_len + 1); |
c19d1205 ZW |
21236 | memcpy (sec_name, prefix, prefix_len); |
21237 | memcpy (sec_name + prefix_len, text_name, text_len); | |
21238 | sec_name[prefix_len + text_len] = '\0'; | |
bfae80f2 | 21239 | |
c19d1205 ZW |
21240 | flags = SHF_ALLOC; |
21241 | linkonce = 0; | |
21242 | group_name = 0; | |
bfae80f2 | 21243 | |
c19d1205 ZW |
21244 | /* Handle COMDAT group. */ |
21245 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 21246 | { |
c19d1205 ZW |
21247 | group_name = elf_group_name (text_seg); |
21248 | if (group_name == NULL) | |
21249 | { | |
bd3ba5d1 | 21250 | as_bad (_("Group section `%s' has no group signature"), |
c19d1205 ZW |
21251 | segment_name (text_seg)); |
21252 | ignore_rest_of_line (); | |
21253 | return; | |
21254 | } | |
21255 | flags |= SHF_GROUP; | |
21256 | linkonce = 1; | |
bfae80f2 RE |
21257 | } |
21258 | ||
c19d1205 | 21259 | obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); |
bfae80f2 | 21260 | |
5f4273c7 | 21261 | /* Set the section link for index tables. */ |
c19d1205 ZW |
21262 | if (idx) |
21263 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
21264 | } |
21265 | ||
bfae80f2 | 21266 | |
c19d1205 ZW |
21267 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
21268 | personality routine data. Returns zero, or the index table value for | |
cad0da33 | 21269 | an inline entry. */ |
c19d1205 ZW |
21270 | |
21271 | static valueT | |
21272 | create_unwind_entry (int have_data) | |
bfae80f2 | 21273 | { |
c19d1205 ZW |
21274 | int size; |
21275 | addressT where; | |
21276 | char *ptr; | |
21277 | /* The current word of data. */ | |
21278 | valueT data; | |
21279 | /* The number of bytes left in this word. */ | |
21280 | int n; | |
bfae80f2 | 21281 | |
c19d1205 | 21282 | finish_unwind_opcodes (); |
bfae80f2 | 21283 | |
c19d1205 ZW |
21284 | /* Remember the current text section. */ |
21285 | unwind.saved_seg = now_seg; | |
21286 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 21287 | |
c19d1205 | 21288 | start_unwind_section (now_seg, 0); |
bfae80f2 | 21289 | |
c19d1205 | 21290 | if (unwind.personality_routine == NULL) |
bfae80f2 | 21291 | { |
c19d1205 ZW |
21292 | if (unwind.personality_index == -2) |
21293 | { | |
21294 | if (have_data) | |
5f4273c7 | 21295 | as_bad (_("handlerdata in cantunwind frame")); |
c19d1205 ZW |
21296 | return 1; /* EXIDX_CANTUNWIND. */ |
21297 | } | |
bfae80f2 | 21298 | |
c19d1205 ZW |
21299 | /* Use a default personality routine if none is specified. */ |
21300 | if (unwind.personality_index == -1) | |
21301 | { | |
21302 | if (unwind.opcode_count > 3) | |
21303 | unwind.personality_index = 1; | |
21304 | else | |
21305 | unwind.personality_index = 0; | |
21306 | } | |
bfae80f2 | 21307 | |
c19d1205 ZW |
21308 | /* Space for the personality routine entry. */ |
21309 | if (unwind.personality_index == 0) | |
21310 | { | |
21311 | if (unwind.opcode_count > 3) | |
21312 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 21313 | |
c19d1205 ZW |
21314 | if (!have_data) |
21315 | { | |
21316 | /* All the data is inline in the index table. */ | |
21317 | data = 0x80; | |
21318 | n = 3; | |
21319 | while (unwind.opcode_count > 0) | |
21320 | { | |
21321 | unwind.opcode_count--; | |
21322 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
21323 | n--; | |
21324 | } | |
bfae80f2 | 21325 | |
c19d1205 ZW |
21326 | /* Pad with "finish" opcodes. */ |
21327 | while (n--) | |
21328 | data = (data << 8) | 0xb0; | |
bfae80f2 | 21329 | |
c19d1205 ZW |
21330 | return data; |
21331 | } | |
21332 | size = 0; | |
21333 | } | |
21334 | else | |
21335 | /* We get two opcodes "free" in the first word. */ | |
21336 | size = unwind.opcode_count - 2; | |
21337 | } | |
21338 | else | |
5011093d | 21339 | { |
cad0da33 NC |
21340 | /* PR 16765: Missing or misplaced unwind directives can trigger this. */ |
21341 | if (unwind.personality_index != -1) | |
21342 | { | |
21343 | as_bad (_("attempt to recreate an unwind entry")); | |
21344 | return 1; | |
21345 | } | |
5011093d NC |
21346 | |
21347 | /* An extra byte is required for the opcode count. */ | |
21348 | size = unwind.opcode_count + 1; | |
21349 | } | |
bfae80f2 | 21350 | |
c19d1205 ZW |
21351 | size = (size + 3) >> 2; |
21352 | if (size > 0xff) | |
21353 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 21354 | |
c19d1205 ZW |
21355 | frag_align (2, 0, 0); |
21356 | record_alignment (now_seg, 2); | |
21357 | unwind.table_entry = expr_build_dot (); | |
21358 | ||
21359 | /* Allocate the table entry. */ | |
21360 | ptr = frag_more ((size << 2) + 4); | |
74929e7b NC |
21361 | /* PR 13449: Zero the table entries in case some of them are not used. */ |
21362 | memset (ptr, 0, (size << 2) + 4); | |
c19d1205 | 21363 | where = frag_now_fix () - ((size << 2) + 4); |
bfae80f2 | 21364 | |
c19d1205 | 21365 | switch (unwind.personality_index) |
bfae80f2 | 21366 | { |
c19d1205 ZW |
21367 | case -1: |
21368 | /* ??? Should this be a PLT generating relocation? */ | |
21369 | /* Custom personality routine. */ | |
21370 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
21371 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 21372 | |
c19d1205 ZW |
21373 | where += 4; |
21374 | ptr += 4; | |
bfae80f2 | 21375 | |
c19d1205 | 21376 | /* Set the first byte to the number of additional words. */ |
5011093d | 21377 | data = size > 0 ? size - 1 : 0; |
c19d1205 ZW |
21378 | n = 3; |
21379 | break; | |
bfae80f2 | 21380 | |
c19d1205 ZW |
21381 | /* ABI defined personality routines. */ |
21382 | case 0: | |
21383 | /* Three opcodes bytes are packed into the first word. */ | |
21384 | data = 0x80; | |
21385 | n = 3; | |
21386 | break; | |
bfae80f2 | 21387 | |
c19d1205 ZW |
21388 | case 1: |
21389 | case 2: | |
21390 | /* The size and first two opcode bytes go in the first word. */ | |
21391 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
21392 | n = 2; | |
21393 | break; | |
bfae80f2 | 21394 | |
c19d1205 ZW |
21395 | default: |
21396 | /* Should never happen. */ | |
21397 | abort (); | |
21398 | } | |
bfae80f2 | 21399 | |
c19d1205 ZW |
21400 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
21401 | time. */ | |
21402 | while (unwind.opcode_count > 0) | |
21403 | { | |
21404 | if (n == 0) | |
21405 | { | |
21406 | md_number_to_chars (ptr, data, 4); | |
21407 | ptr += 4; | |
21408 | n = 4; | |
21409 | data = 0; | |
21410 | } | |
21411 | unwind.opcode_count--; | |
21412 | n--; | |
21413 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
21414 | } | |
21415 | ||
21416 | /* Finish off the last word. */ | |
21417 | if (n < 4) | |
21418 | { | |
21419 | /* Pad with "finish" opcodes. */ | |
21420 | while (n--) | |
21421 | data = (data << 8) | 0xb0; | |
21422 | ||
21423 | md_number_to_chars (ptr, data, 4); | |
21424 | } | |
21425 | ||
21426 | if (!have_data) | |
21427 | { | |
21428 | /* Add an empty descriptor if there is no user-specified data. */ | |
21429 | ptr = frag_more (4); | |
21430 | md_number_to_chars (ptr, 0, 4); | |
21431 | } | |
21432 | ||
21433 | return 0; | |
bfae80f2 RE |
21434 | } |
21435 | ||
f0927246 NC |
21436 | |
21437 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
21438 | ||
21439 | void | |
21440 | tc_arm_frame_initial_instructions (void) | |
21441 | { | |
21442 | cfi_add_CFA_def_cfa (REG_SP, 0); | |
21443 | } | |
21444 | #endif /* OBJ_ELF */ | |
21445 | ||
c19d1205 ZW |
21446 | /* Convert REGNAME to a DWARF-2 register number. */ |
21447 | ||
21448 | int | |
1df69f4f | 21449 | tc_arm_regname_to_dw2regnum (char *regname) |
bfae80f2 | 21450 | { |
1df69f4f | 21451 | int reg = arm_reg_parse (®name, REG_TYPE_RN); |
1f5afe1c NC |
21452 | if (reg != FAIL) |
21453 | return reg; | |
c19d1205 | 21454 | |
1f5afe1c NC |
21455 | /* PR 16694: Allow VFP registers as well. */ |
21456 | reg = arm_reg_parse (®name, REG_TYPE_VFS); | |
21457 | if (reg != FAIL) | |
21458 | return 64 + reg; | |
c19d1205 | 21459 | |
1f5afe1c NC |
21460 | reg = arm_reg_parse (®name, REG_TYPE_VFD); |
21461 | if (reg != FAIL) | |
21462 | return reg + 256; | |
21463 | ||
21464 | return -1; | |
bfae80f2 RE |
21465 | } |
21466 | ||
f0927246 | 21467 | #ifdef TE_PE |
c19d1205 | 21468 | void |
f0927246 | 21469 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
bfae80f2 | 21470 | { |
91d6fa6a | 21471 | expressionS exp; |
bfae80f2 | 21472 | |
91d6fa6a NC |
21473 | exp.X_op = O_secrel; |
21474 | exp.X_add_symbol = symbol; | |
21475 | exp.X_add_number = 0; | |
21476 | emit_expr (&exp, size); | |
f0927246 NC |
21477 | } |
21478 | #endif | |
bfae80f2 | 21479 | |
c19d1205 | 21480 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 21481 | |
2fc8bdac ZW |
21482 | /* Return the address within the segment that a PC-relative fixup is |
21483 | relative to. For ARM, PC-relative fixups applied to instructions | |
21484 | are generally relative to the location of the fixup plus 8 bytes. | |
21485 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
21486 | require special handling. */ | |
bfae80f2 | 21487 | |
c19d1205 | 21488 | long |
2fc8bdac | 21489 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 21490 | { |
2fc8bdac ZW |
21491 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
21492 | ||
21493 | /* If this is pc-relative and we are going to emit a relocation | |
21494 | then we just want to put out any pipeline compensation that the linker | |
53baae48 NC |
21495 | will need. Otherwise we want to use the calculated base. |
21496 | For WinCE we skip the bias for externals as well, since this | |
21497 | is how the MS ARM-CE assembler behaves and we want to be compatible. */ | |
5f4273c7 | 21498 | if (fixP->fx_pcrel |
2fc8bdac | 21499 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) |
53baae48 NC |
21500 | || (arm_force_relocation (fixP) |
21501 | #ifdef TE_WINCE | |
21502 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
21503 | #endif | |
21504 | ))) | |
2fc8bdac | 21505 | base = 0; |
bfae80f2 | 21506 | |
267bf995 | 21507 | |
c19d1205 | 21508 | switch (fixP->fx_r_type) |
bfae80f2 | 21509 | { |
2fc8bdac ZW |
21510 | /* PC relative addressing on the Thumb is slightly odd as the |
21511 | bottom two bits of the PC are forced to zero for the | |
21512 | calculation. This happens *after* application of the | |
21513 | pipeline offset. However, Thumb adrl already adjusts for | |
21514 | this, so we need not do it again. */ | |
c19d1205 | 21515 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 21516 | return base & ~3; |
c19d1205 ZW |
21517 | |
21518 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
21519 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 21520 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 21521 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 21522 | return (base + 4) & ~3; |
c19d1205 | 21523 | |
2fc8bdac ZW |
21524 | /* Thumb branches are simply offset by +4. */ |
21525 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
21526 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
21527 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
21528 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
2fc8bdac | 21529 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac | 21530 | return base + 4; |
bfae80f2 | 21531 | |
267bf995 | 21532 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
486499d0 CL |
21533 | if (fixP->fx_addsy |
21534 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21535 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 | 21536 | && ARM_IS_FUNC (fixP->fx_addsy) |
477330fc RM |
21537 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) |
21538 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
267bf995 RR |
21539 | return base + 4; |
21540 | ||
00adf2d4 JB |
21541 | /* BLX is like branches above, but forces the low two bits of PC to |
21542 | zero. */ | |
486499d0 CL |
21543 | case BFD_RELOC_THUMB_PCREL_BLX: |
21544 | if (fixP->fx_addsy | |
21545 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21546 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
21547 | && THUMB_IS_FUNC (fixP->fx_addsy) |
21548 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
21549 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
00adf2d4 JB |
21550 | return (base + 4) & ~3; |
21551 | ||
2fc8bdac ZW |
21552 | /* ARM mode branches are offset by +8. However, the Windows CE |
21553 | loader expects the relocation not to take this into account. */ | |
267bf995 | 21554 | case BFD_RELOC_ARM_PCREL_BLX: |
486499d0 CL |
21555 | if (fixP->fx_addsy |
21556 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21557 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
21558 | && ARM_IS_FUNC (fixP->fx_addsy) |
21559 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
21560 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 21561 | return base + 8; |
267bf995 | 21562 | |
486499d0 CL |
21563 | case BFD_RELOC_ARM_PCREL_CALL: |
21564 | if (fixP->fx_addsy | |
21565 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21566 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
21567 | && THUMB_IS_FUNC (fixP->fx_addsy) |
21568 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
21569 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 21570 | return base + 8; |
267bf995 | 21571 | |
2fc8bdac | 21572 | case BFD_RELOC_ARM_PCREL_BRANCH: |
39b41c9c | 21573 | case BFD_RELOC_ARM_PCREL_JUMP: |
2fc8bdac | 21574 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 21575 | #ifdef TE_WINCE |
5f4273c7 | 21576 | /* When handling fixups immediately, because we have already |
477330fc | 21577 | discovered the value of a symbol, or the address of the frag involved |
53baae48 | 21578 | we must account for the offset by +8, as the OS loader will never see the reloc. |
477330fc RM |
21579 | see fixup_segment() in write.c |
21580 | The S_IS_EXTERNAL test handles the case of global symbols. | |
21581 | Those need the calculated base, not just the pipe compensation the linker will need. */ | |
53baae48 NC |
21582 | if (fixP->fx_pcrel |
21583 | && fixP->fx_addsy != NULL | |
21584 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
21585 | && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) | |
21586 | return base + 8; | |
2fc8bdac | 21587 | return base; |
c19d1205 | 21588 | #else |
2fc8bdac | 21589 | return base + 8; |
c19d1205 | 21590 | #endif |
2fc8bdac | 21591 | |
267bf995 | 21592 | |
2fc8bdac ZW |
21593 | /* ARM mode loads relative to PC are also offset by +8. Unlike |
21594 | branches, the Windows CE loader *does* expect the relocation | |
21595 | to take this into account. */ | |
21596 | case BFD_RELOC_ARM_OFFSET_IMM: | |
21597 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
21598 | case BFD_RELOC_ARM_HWLITERAL: | |
21599 | case BFD_RELOC_ARM_LITERAL: | |
21600 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
21601 | return base + 8; | |
21602 | ||
21603 | ||
21604 | /* Other PC-relative relocations are un-offset. */ | |
21605 | default: | |
21606 | return base; | |
21607 | } | |
bfae80f2 RE |
21608 | } |
21609 | ||
c19d1205 ZW |
21610 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. |
21611 | Otherwise we have no need to default values of symbols. */ | |
21612 | ||
21613 | symbolS * | |
21614 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
bfae80f2 | 21615 | { |
c19d1205 ZW |
21616 | #ifdef OBJ_ELF |
21617 | if (name[0] == '_' && name[1] == 'G' | |
21618 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
21619 | { | |
21620 | if (!GOT_symbol) | |
21621 | { | |
21622 | if (symbol_find (name)) | |
bd3ba5d1 | 21623 | as_bad (_("GOT already in the symbol table")); |
bfae80f2 | 21624 | |
c19d1205 ZW |
21625 | GOT_symbol = symbol_new (name, undefined_section, |
21626 | (valueT) 0, & zero_address_frag); | |
21627 | } | |
bfae80f2 | 21628 | |
c19d1205 | 21629 | return GOT_symbol; |
bfae80f2 | 21630 | } |
c19d1205 | 21631 | #endif |
bfae80f2 | 21632 | |
c921be7d | 21633 | return NULL; |
bfae80f2 RE |
21634 | } |
21635 | ||
55cf6793 | 21636 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
21637 | computed as two separate immediate values, added together. We |
21638 | already know that this value cannot be computed by just one ARM | |
21639 | instruction. */ | |
21640 | ||
21641 | static unsigned int | |
21642 | validate_immediate_twopart (unsigned int val, | |
21643 | unsigned int * highpart) | |
bfae80f2 | 21644 | { |
c19d1205 ZW |
21645 | unsigned int a; |
21646 | unsigned int i; | |
bfae80f2 | 21647 | |
c19d1205 ZW |
21648 | for (i = 0; i < 32; i += 2) |
21649 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
21650 | { | |
21651 | if (a & 0xff00) | |
21652 | { | |
21653 | if (a & ~ 0xffff) | |
21654 | continue; | |
21655 | * highpart = (a >> 8) | ((i + 24) << 7); | |
21656 | } | |
21657 | else if (a & 0xff0000) | |
21658 | { | |
21659 | if (a & 0xff000000) | |
21660 | continue; | |
21661 | * highpart = (a >> 16) | ((i + 16) << 7); | |
21662 | } | |
21663 | else | |
21664 | { | |
9c2799c2 | 21665 | gas_assert (a & 0xff000000); |
c19d1205 ZW |
21666 | * highpart = (a >> 24) | ((i + 8) << 7); |
21667 | } | |
bfae80f2 | 21668 | |
c19d1205 ZW |
21669 | return (a & 0xff) | (i << 7); |
21670 | } | |
bfae80f2 | 21671 | |
c19d1205 | 21672 | return FAIL; |
bfae80f2 RE |
21673 | } |
21674 | ||
c19d1205 ZW |
21675 | static int |
21676 | validate_offset_imm (unsigned int val, int hwse) | |
21677 | { | |
21678 | if ((hwse && val > 255) || val > 4095) | |
21679 | return FAIL; | |
21680 | return val; | |
21681 | } | |
bfae80f2 | 21682 | |
55cf6793 | 21683 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
21684 | negative immediate constant by altering the instruction. A bit of |
21685 | a hack really. | |
21686 | MOV <-> MVN | |
21687 | AND <-> BIC | |
21688 | ADC <-> SBC | |
21689 | by inverting the second operand, and | |
21690 | ADD <-> SUB | |
21691 | CMP <-> CMN | |
21692 | by negating the second operand. */ | |
bfae80f2 | 21693 | |
c19d1205 ZW |
21694 | static int |
21695 | negate_data_op (unsigned long * instruction, | |
21696 | unsigned long value) | |
bfae80f2 | 21697 | { |
c19d1205 ZW |
21698 | int op, new_inst; |
21699 | unsigned long negated, inverted; | |
bfae80f2 | 21700 | |
c19d1205 ZW |
21701 | negated = encode_arm_immediate (-value); |
21702 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 21703 | |
c19d1205 ZW |
21704 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
21705 | switch (op) | |
bfae80f2 | 21706 | { |
c19d1205 ZW |
21707 | /* First negates. */ |
21708 | case OPCODE_SUB: /* ADD <-> SUB */ | |
21709 | new_inst = OPCODE_ADD; | |
21710 | value = negated; | |
21711 | break; | |
bfae80f2 | 21712 | |
c19d1205 ZW |
21713 | case OPCODE_ADD: |
21714 | new_inst = OPCODE_SUB; | |
21715 | value = negated; | |
21716 | break; | |
bfae80f2 | 21717 | |
c19d1205 ZW |
21718 | case OPCODE_CMP: /* CMP <-> CMN */ |
21719 | new_inst = OPCODE_CMN; | |
21720 | value = negated; | |
21721 | break; | |
bfae80f2 | 21722 | |
c19d1205 ZW |
21723 | case OPCODE_CMN: |
21724 | new_inst = OPCODE_CMP; | |
21725 | value = negated; | |
21726 | break; | |
bfae80f2 | 21727 | |
c19d1205 ZW |
21728 | /* Now Inverted ops. */ |
21729 | case OPCODE_MOV: /* MOV <-> MVN */ | |
21730 | new_inst = OPCODE_MVN; | |
21731 | value = inverted; | |
21732 | break; | |
bfae80f2 | 21733 | |
c19d1205 ZW |
21734 | case OPCODE_MVN: |
21735 | new_inst = OPCODE_MOV; | |
21736 | value = inverted; | |
21737 | break; | |
bfae80f2 | 21738 | |
c19d1205 ZW |
21739 | case OPCODE_AND: /* AND <-> BIC */ |
21740 | new_inst = OPCODE_BIC; | |
21741 | value = inverted; | |
21742 | break; | |
bfae80f2 | 21743 | |
c19d1205 ZW |
21744 | case OPCODE_BIC: |
21745 | new_inst = OPCODE_AND; | |
21746 | value = inverted; | |
21747 | break; | |
bfae80f2 | 21748 | |
c19d1205 ZW |
21749 | case OPCODE_ADC: /* ADC <-> SBC */ |
21750 | new_inst = OPCODE_SBC; | |
21751 | value = inverted; | |
21752 | break; | |
bfae80f2 | 21753 | |
c19d1205 ZW |
21754 | case OPCODE_SBC: |
21755 | new_inst = OPCODE_ADC; | |
21756 | value = inverted; | |
21757 | break; | |
bfae80f2 | 21758 | |
c19d1205 ZW |
21759 | /* We cannot do anything. */ |
21760 | default: | |
21761 | return FAIL; | |
b99bd4ef NC |
21762 | } |
21763 | ||
c19d1205 ZW |
21764 | if (value == (unsigned) FAIL) |
21765 | return FAIL; | |
21766 | ||
21767 | *instruction &= OPCODE_MASK; | |
21768 | *instruction |= new_inst << DATA_OP_SHIFT; | |
21769 | return value; | |
b99bd4ef NC |
21770 | } |
21771 | ||
ef8d22e6 PB |
21772 | /* Like negate_data_op, but for Thumb-2. */ |
21773 | ||
21774 | static unsigned int | |
16dd5e42 | 21775 | thumb32_negate_data_op (offsetT *instruction, unsigned int value) |
ef8d22e6 PB |
21776 | { |
21777 | int op, new_inst; | |
21778 | int rd; | |
16dd5e42 | 21779 | unsigned int negated, inverted; |
ef8d22e6 PB |
21780 | |
21781 | negated = encode_thumb32_immediate (-value); | |
21782 | inverted = encode_thumb32_immediate (~value); | |
21783 | ||
21784 | rd = (*instruction >> 8) & 0xf; | |
21785 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; | |
21786 | switch (op) | |
21787 | { | |
21788 | /* ADD <-> SUB. Includes CMP <-> CMN. */ | |
21789 | case T2_OPCODE_SUB: | |
21790 | new_inst = T2_OPCODE_ADD; | |
21791 | value = negated; | |
21792 | break; | |
21793 | ||
21794 | case T2_OPCODE_ADD: | |
21795 | new_inst = T2_OPCODE_SUB; | |
21796 | value = negated; | |
21797 | break; | |
21798 | ||
21799 | /* ORR <-> ORN. Includes MOV <-> MVN. */ | |
21800 | case T2_OPCODE_ORR: | |
21801 | new_inst = T2_OPCODE_ORN; | |
21802 | value = inverted; | |
21803 | break; | |
21804 | ||
21805 | case T2_OPCODE_ORN: | |
21806 | new_inst = T2_OPCODE_ORR; | |
21807 | value = inverted; | |
21808 | break; | |
21809 | ||
21810 | /* AND <-> BIC. TST has no inverted equivalent. */ | |
21811 | case T2_OPCODE_AND: | |
21812 | new_inst = T2_OPCODE_BIC; | |
21813 | if (rd == 15) | |
21814 | value = FAIL; | |
21815 | else | |
21816 | value = inverted; | |
21817 | break; | |
21818 | ||
21819 | case T2_OPCODE_BIC: | |
21820 | new_inst = T2_OPCODE_AND; | |
21821 | value = inverted; | |
21822 | break; | |
21823 | ||
21824 | /* ADC <-> SBC */ | |
21825 | case T2_OPCODE_ADC: | |
21826 | new_inst = T2_OPCODE_SBC; | |
21827 | value = inverted; | |
21828 | break; | |
21829 | ||
21830 | case T2_OPCODE_SBC: | |
21831 | new_inst = T2_OPCODE_ADC; | |
21832 | value = inverted; | |
21833 | break; | |
21834 | ||
21835 | /* We cannot do anything. */ | |
21836 | default: | |
21837 | return FAIL; | |
21838 | } | |
21839 | ||
16dd5e42 | 21840 | if (value == (unsigned int)FAIL) |
ef8d22e6 PB |
21841 | return FAIL; |
21842 | ||
21843 | *instruction &= T2_OPCODE_MASK; | |
21844 | *instruction |= new_inst << T2_DATA_OP_SHIFT; | |
21845 | return value; | |
21846 | } | |
21847 | ||
8f06b2d8 PB |
21848 | /* Read a 32-bit thumb instruction from buf. */ |
21849 | static unsigned long | |
21850 | get_thumb32_insn (char * buf) | |
21851 | { | |
21852 | unsigned long insn; | |
21853 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
21854 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
21855 | ||
21856 | return insn; | |
21857 | } | |
21858 | ||
a8bc6c78 PB |
21859 | |
21860 | /* We usually want to set the low bit on the address of thumb function | |
21861 | symbols. In particular .word foo - . should have the low bit set. | |
21862 | Generic code tries to fold the difference of two symbols to | |
21863 | a constant. Prevent this and force a relocation when the first symbols | |
21864 | is a thumb function. */ | |
c921be7d NC |
21865 | |
21866 | bfd_boolean | |
a8bc6c78 PB |
21867 | arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) |
21868 | { | |
21869 | if (op == O_subtract | |
21870 | && l->X_op == O_symbol | |
21871 | && r->X_op == O_symbol | |
21872 | && THUMB_IS_FUNC (l->X_add_symbol)) | |
21873 | { | |
21874 | l->X_op = O_subtract; | |
21875 | l->X_op_symbol = r->X_add_symbol; | |
21876 | l->X_add_number -= r->X_add_number; | |
c921be7d | 21877 | return TRUE; |
a8bc6c78 | 21878 | } |
c921be7d | 21879 | |
a8bc6c78 | 21880 | /* Process as normal. */ |
c921be7d | 21881 | return FALSE; |
a8bc6c78 PB |
21882 | } |
21883 | ||
4a42ebbc RR |
21884 | /* Encode Thumb2 unconditional branches and calls. The encoding |
21885 | for the 2 are identical for the immediate values. */ | |
21886 | ||
21887 | static void | |
21888 | encode_thumb2_b_bl_offset (char * buf, offsetT value) | |
21889 | { | |
21890 | #define T2I1I2MASK ((1 << 13) | (1 << 11)) | |
21891 | offsetT newval; | |
21892 | offsetT newval2; | |
21893 | addressT S, I1, I2, lo, hi; | |
21894 | ||
21895 | S = (value >> 24) & 0x01; | |
21896 | I1 = (value >> 23) & 0x01; | |
21897 | I2 = (value >> 22) & 0x01; | |
21898 | hi = (value >> 12) & 0x3ff; | |
fa94de6b | 21899 | lo = (value >> 1) & 0x7ff; |
4a42ebbc RR |
21900 | newval = md_chars_to_number (buf, THUMB_SIZE); |
21901 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
21902 | newval |= (S << 10) | hi; | |
21903 | newval2 &= ~T2I1I2MASK; | |
21904 | newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK; | |
21905 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21906 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
21907 | } | |
21908 | ||
c19d1205 | 21909 | void |
55cf6793 | 21910 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
21911 | valueT * valP, |
21912 | segT seg) | |
21913 | { | |
21914 | offsetT value = * valP; | |
21915 | offsetT newval; | |
21916 | unsigned int newimm; | |
21917 | unsigned long temp; | |
21918 | int sign; | |
21919 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 21920 | |
9c2799c2 | 21921 | gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 21922 | |
c19d1205 | 21923 | /* Note whether this will delete the relocation. */ |
4962c51a | 21924 | |
c19d1205 ZW |
21925 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) |
21926 | fixP->fx_done = 1; | |
b99bd4ef | 21927 | |
adbaf948 | 21928 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
5f4273c7 | 21929 | consistency with the behaviour on 32-bit hosts. Remember value |
adbaf948 ZW |
21930 | for emit_reloc. */ |
21931 | value &= 0xffffffff; | |
21932 | value ^= 0x80000000; | |
5f4273c7 | 21933 | value -= 0x80000000; |
adbaf948 ZW |
21934 | |
21935 | *valP = value; | |
c19d1205 | 21936 | fixP->fx_addnumber = value; |
b99bd4ef | 21937 | |
adbaf948 ZW |
21938 | /* Same treatment for fixP->fx_offset. */ |
21939 | fixP->fx_offset &= 0xffffffff; | |
21940 | fixP->fx_offset ^= 0x80000000; | |
21941 | fixP->fx_offset -= 0x80000000; | |
21942 | ||
c19d1205 | 21943 | switch (fixP->fx_r_type) |
b99bd4ef | 21944 | { |
c19d1205 ZW |
21945 | case BFD_RELOC_NONE: |
21946 | /* This will need to go in the object file. */ | |
21947 | fixP->fx_done = 0; | |
21948 | break; | |
b99bd4ef | 21949 | |
c19d1205 ZW |
21950 | case BFD_RELOC_ARM_IMMEDIATE: |
21951 | /* We claim that this fixup has been processed here, | |
21952 | even if in fact we generate an error because we do | |
21953 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
21954 | fixP->fx_done = 1; | |
b99bd4ef | 21955 | |
77db8e2e | 21956 | if (fixP->fx_addsy) |
b99bd4ef | 21957 | { |
77db8e2e | 21958 | const char *msg = 0; |
b99bd4ef | 21959 | |
77db8e2e NC |
21960 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
21961 | msg = _("undefined symbol %s used as an immediate value"); | |
21962 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
21963 | msg = _("symbol %s is in a different section"); | |
21964 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
21965 | msg = _("symbol %s is weak and may be overridden later"); | |
21966 | ||
21967 | if (msg) | |
21968 | { | |
21969 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21970 | msg, S_GET_NAME (fixP->fx_addsy)); | |
21971 | break; | |
21972 | } | |
42e5fcbf AS |
21973 | } |
21974 | ||
c19d1205 ZW |
21975 | temp = md_chars_to_number (buf, INSN_SIZE); |
21976 | ||
5e73442d SL |
21977 | /* If the offset is negative, we should use encoding A2 for ADR. */ |
21978 | if ((temp & 0xfff0000) == 0x28f0000 && value < 0) | |
21979 | newimm = negate_data_op (&temp, value); | |
21980 | else | |
21981 | { | |
21982 | newimm = encode_arm_immediate (value); | |
21983 | ||
21984 | /* If the instruction will fail, see if we can fix things up by | |
21985 | changing the opcode. */ | |
21986 | if (newimm == (unsigned int) FAIL) | |
21987 | newimm = negate_data_op (&temp, value); | |
21988 | } | |
21989 | ||
21990 | if (newimm == (unsigned int) FAIL) | |
b99bd4ef | 21991 | { |
c19d1205 ZW |
21992 | as_bad_where (fixP->fx_file, fixP->fx_line, |
21993 | _("invalid constant (%lx) after fixup"), | |
21994 | (unsigned long) value); | |
21995 | break; | |
b99bd4ef | 21996 | } |
b99bd4ef | 21997 | |
c19d1205 ZW |
21998 | newimm |= (temp & 0xfffff000); |
21999 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
22000 | break; | |
b99bd4ef | 22001 | |
c19d1205 ZW |
22002 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
22003 | { | |
22004 | unsigned int highpart = 0; | |
22005 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 22006 | |
77db8e2e | 22007 | if (fixP->fx_addsy) |
42e5fcbf | 22008 | { |
77db8e2e | 22009 | const char *msg = 0; |
42e5fcbf | 22010 | |
77db8e2e NC |
22011 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
22012 | msg = _("undefined symbol %s used as an immediate value"); | |
22013 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
22014 | msg = _("symbol %s is in a different section"); | |
22015 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
22016 | msg = _("symbol %s is weak and may be overridden later"); | |
42e5fcbf | 22017 | |
77db8e2e NC |
22018 | if (msg) |
22019 | { | |
22020 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22021 | msg, S_GET_NAME (fixP->fx_addsy)); | |
22022 | break; | |
22023 | } | |
22024 | } | |
fa94de6b | 22025 | |
c19d1205 ZW |
22026 | newimm = encode_arm_immediate (value); |
22027 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 22028 | |
c19d1205 ZW |
22029 | /* If the instruction will fail, see if we can fix things up by |
22030 | changing the opcode. */ | |
22031 | if (newimm == (unsigned int) FAIL | |
22032 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
22033 | { | |
22034 | /* No ? OK - try using two ADD instructions to generate | |
22035 | the value. */ | |
22036 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 22037 | |
c19d1205 ZW |
22038 | /* Yes - then make sure that the second instruction is |
22039 | also an add. */ | |
22040 | if (newimm != (unsigned int) FAIL) | |
22041 | newinsn = temp; | |
22042 | /* Still No ? Try using a negated value. */ | |
22043 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
22044 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
22045 | /* Otherwise - give up. */ | |
22046 | else | |
22047 | { | |
22048 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22049 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
22050 | (long) value); | |
22051 | break; | |
22052 | } | |
b99bd4ef | 22053 | |
c19d1205 ZW |
22054 | /* Replace the first operand in the 2nd instruction (which |
22055 | is the PC) with the destination register. We have | |
22056 | already added in the PC in the first instruction and we | |
22057 | do not want to do it again. */ | |
22058 | newinsn &= ~ 0xf0000; | |
22059 | newinsn |= ((newinsn & 0x0f000) << 4); | |
22060 | } | |
b99bd4ef | 22061 | |
c19d1205 ZW |
22062 | newimm |= (temp & 0xfffff000); |
22063 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 22064 | |
c19d1205 ZW |
22065 | highpart |= (newinsn & 0xfffff000); |
22066 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
22067 | } | |
22068 | break; | |
b99bd4ef | 22069 | |
c19d1205 | 22070 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
22071 | if (!fixP->fx_done && seg->use_rela_p) |
22072 | value = 0; | |
22073 | ||
c19d1205 | 22074 | case BFD_RELOC_ARM_LITERAL: |
26d97720 | 22075 | sign = value > 0; |
b99bd4ef | 22076 | |
c19d1205 ZW |
22077 | if (value < 0) |
22078 | value = - value; | |
b99bd4ef | 22079 | |
c19d1205 | 22080 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 22081 | { |
c19d1205 ZW |
22082 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
22083 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22084 | _("invalid literal constant: pool needs to be closer")); | |
22085 | else | |
22086 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22087 | _("bad immediate value for offset (%ld)"), | |
22088 | (long) value); | |
22089 | break; | |
f03698e6 RE |
22090 | } |
22091 | ||
c19d1205 | 22092 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
22093 | if (value == 0) |
22094 | newval &= 0xfffff000; | |
22095 | else | |
22096 | { | |
22097 | newval &= 0xff7ff000; | |
22098 | newval |= value | (sign ? INDEX_UP : 0); | |
22099 | } | |
c19d1205 ZW |
22100 | md_number_to_chars (buf, newval, INSN_SIZE); |
22101 | break; | |
b99bd4ef | 22102 | |
c19d1205 ZW |
22103 | case BFD_RELOC_ARM_OFFSET_IMM8: |
22104 | case BFD_RELOC_ARM_HWLITERAL: | |
26d97720 | 22105 | sign = value > 0; |
b99bd4ef | 22106 | |
c19d1205 ZW |
22107 | if (value < 0) |
22108 | value = - value; | |
b99bd4ef | 22109 | |
c19d1205 | 22110 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 22111 | { |
c19d1205 ZW |
22112 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
22113 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22114 | _("invalid literal constant: pool needs to be closer")); | |
22115 | else | |
427d0db6 RM |
22116 | as_bad_where (fixP->fx_file, fixP->fx_line, |
22117 | _("bad immediate value for 8-bit offset (%ld)"), | |
22118 | (long) value); | |
c19d1205 | 22119 | break; |
b99bd4ef NC |
22120 | } |
22121 | ||
c19d1205 | 22122 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
22123 | if (value == 0) |
22124 | newval &= 0xfffff0f0; | |
22125 | else | |
22126 | { | |
22127 | newval &= 0xff7ff0f0; | |
22128 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
22129 | } | |
c19d1205 ZW |
22130 | md_number_to_chars (buf, newval, INSN_SIZE); |
22131 | break; | |
b99bd4ef | 22132 | |
c19d1205 ZW |
22133 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
22134 | if (value < 0 || value > 1020 || value % 4 != 0) | |
22135 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22136 | _("bad immediate value for offset (%ld)"), (long) value); | |
22137 | value /= 4; | |
b99bd4ef | 22138 | |
c19d1205 | 22139 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
22140 | newval |= value; |
22141 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
22142 | break; | |
b99bd4ef | 22143 | |
c19d1205 ZW |
22144 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
22145 | /* This is a complicated relocation used for all varieties of Thumb32 | |
22146 | load/store instruction with immediate offset: | |
22147 | ||
22148 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
477330fc | 22149 | *4, optional writeback(W) |
c19d1205 ZW |
22150 | (doubleword load/store) |
22151 | ||
22152 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
22153 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
22154 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
22155 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
22156 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
22157 | ||
22158 | Uppercase letters indicate bits that are already encoded at | |
22159 | this point. Lowercase letters are our problem. For the | |
22160 | second block of instructions, the secondary opcode nybble | |
22161 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
22162 | a PC-relative operation. */ | |
22163 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22164 | newval <<= 16; | |
22165 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 22166 | |
c19d1205 | 22167 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 22168 | { |
c19d1205 ZW |
22169 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
22170 | if (value >= 0) | |
22171 | newval |= (1 << 23); | |
22172 | else | |
22173 | value = -value; | |
22174 | if (value % 4 != 0) | |
22175 | { | |
22176 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22177 | _("offset not a multiple of 4")); | |
22178 | break; | |
22179 | } | |
22180 | value /= 4; | |
216d22bc | 22181 | if (value > 0xff) |
c19d1205 ZW |
22182 | { |
22183 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22184 | _("offset out of range")); | |
22185 | break; | |
22186 | } | |
22187 | newval &= ~0xff; | |
b99bd4ef | 22188 | } |
c19d1205 | 22189 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 22190 | { |
c19d1205 ZW |
22191 | /* PC-relative, 12-bit offset. */ |
22192 | if (value >= 0) | |
22193 | newval |= (1 << 23); | |
22194 | else | |
22195 | value = -value; | |
216d22bc | 22196 | if (value > 0xfff) |
c19d1205 ZW |
22197 | { |
22198 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22199 | _("offset out of range")); | |
22200 | break; | |
22201 | } | |
22202 | newval &= ~0xfff; | |
b99bd4ef | 22203 | } |
c19d1205 | 22204 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 22205 | { |
c19d1205 ZW |
22206 | /* Writeback: 8-bit, +/- offset. */ |
22207 | if (value >= 0) | |
22208 | newval |= (1 << 9); | |
22209 | else | |
22210 | value = -value; | |
216d22bc | 22211 | if (value > 0xff) |
c19d1205 ZW |
22212 | { |
22213 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22214 | _("offset out of range")); | |
22215 | break; | |
22216 | } | |
22217 | newval &= ~0xff; | |
b99bd4ef | 22218 | } |
c19d1205 | 22219 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 22220 | { |
c19d1205 | 22221 | /* T-instruction: positive 8-bit offset. */ |
216d22bc | 22222 | if (value < 0 || value > 0xff) |
b99bd4ef | 22223 | { |
c19d1205 ZW |
22224 | as_bad_where (fixP->fx_file, fixP->fx_line, |
22225 | _("offset out of range")); | |
22226 | break; | |
b99bd4ef | 22227 | } |
c19d1205 ZW |
22228 | newval &= ~0xff; |
22229 | newval |= value; | |
b99bd4ef NC |
22230 | } |
22231 | else | |
b99bd4ef | 22232 | { |
c19d1205 ZW |
22233 | /* Positive 12-bit or negative 8-bit offset. */ |
22234 | int limit; | |
22235 | if (value >= 0) | |
b99bd4ef | 22236 | { |
c19d1205 ZW |
22237 | newval |= (1 << 23); |
22238 | limit = 0xfff; | |
22239 | } | |
22240 | else | |
22241 | { | |
22242 | value = -value; | |
22243 | limit = 0xff; | |
22244 | } | |
22245 | if (value > limit) | |
22246 | { | |
22247 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22248 | _("offset out of range")); | |
22249 | break; | |
b99bd4ef | 22250 | } |
c19d1205 | 22251 | newval &= ~limit; |
b99bd4ef | 22252 | } |
b99bd4ef | 22253 | |
c19d1205 ZW |
22254 | newval |= value; |
22255 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
22256 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
22257 | break; | |
404ff6b5 | 22258 | |
c19d1205 ZW |
22259 | case BFD_RELOC_ARM_SHIFT_IMM: |
22260 | newval = md_chars_to_number (buf, INSN_SIZE); | |
22261 | if (((unsigned long) value) > 32 | |
22262 | || (value == 32 | |
22263 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
22264 | { | |
22265 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22266 | _("shift expression is too large")); | |
22267 | break; | |
22268 | } | |
404ff6b5 | 22269 | |
c19d1205 ZW |
22270 | if (value == 0) |
22271 | /* Shifts of zero must be done as lsl. */ | |
22272 | newval &= ~0x60; | |
22273 | else if (value == 32) | |
22274 | value = 0; | |
22275 | newval &= 0xfffff07f; | |
22276 | newval |= (value & 0x1f) << 7; | |
22277 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22278 | break; | |
404ff6b5 | 22279 | |
c19d1205 | 22280 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
16805f35 | 22281 | case BFD_RELOC_ARM_T32_ADD_IMM: |
92e90b6e | 22282 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 22283 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
22284 | /* We claim that this fixup has been processed here, |
22285 | even if in fact we generate an error because we do | |
22286 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
22287 | fixP->fx_done = 1; | |
404ff6b5 | 22288 | |
c19d1205 ZW |
22289 | if (fixP->fx_addsy |
22290 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
22291 | { | |
22292 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22293 | _("undefined symbol %s used as an immediate value"), | |
22294 | S_GET_NAME (fixP->fx_addsy)); | |
22295 | break; | |
22296 | } | |
404ff6b5 | 22297 | |
c19d1205 ZW |
22298 | newval = md_chars_to_number (buf, THUMB_SIZE); |
22299 | newval <<= 16; | |
22300 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 22301 | |
16805f35 PB |
22302 | newimm = FAIL; |
22303 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE | |
22304 | || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
ef8d22e6 PB |
22305 | { |
22306 | newimm = encode_thumb32_immediate (value); | |
22307 | if (newimm == (unsigned int) FAIL) | |
22308 | newimm = thumb32_negate_data_op (&newval, value); | |
22309 | } | |
16805f35 PB |
22310 | if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE |
22311 | && newimm == (unsigned int) FAIL) | |
92e90b6e | 22312 | { |
16805f35 PB |
22313 | /* Turn add/sum into addw/subw. */ |
22314 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
22315 | newval = (newval & 0xfeffffff) | 0x02000000; | |
40f246e3 NC |
22316 | /* No flat 12-bit imm encoding for addsw/subsw. */ |
22317 | if ((newval & 0x00100000) == 0) | |
e9f89963 | 22318 | { |
40f246e3 NC |
22319 | /* 12 bit immediate for addw/subw. */ |
22320 | if (value < 0) | |
22321 | { | |
22322 | value = -value; | |
22323 | newval ^= 0x00a00000; | |
22324 | } | |
22325 | if (value > 0xfff) | |
22326 | newimm = (unsigned int) FAIL; | |
22327 | else | |
22328 | newimm = value; | |
e9f89963 | 22329 | } |
92e90b6e | 22330 | } |
cc8a6dd0 | 22331 | |
c19d1205 | 22332 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 22333 | { |
c19d1205 ZW |
22334 | as_bad_where (fixP->fx_file, fixP->fx_line, |
22335 | _("invalid constant (%lx) after fixup"), | |
22336 | (unsigned long) value); | |
22337 | break; | |
3631a3c8 NC |
22338 | } |
22339 | ||
c19d1205 ZW |
22340 | newval |= (newimm & 0x800) << 15; |
22341 | newval |= (newimm & 0x700) << 4; | |
22342 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 22343 | |
c19d1205 ZW |
22344 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
22345 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
22346 | break; | |
a737bd4d | 22347 | |
3eb17e6b | 22348 | case BFD_RELOC_ARM_SMC: |
c19d1205 ZW |
22349 | if (((unsigned long) value) > 0xffff) |
22350 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3eb17e6b | 22351 | _("invalid smc expression")); |
2fc8bdac | 22352 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
22353 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
22354 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22355 | break; | |
a737bd4d | 22356 | |
90ec0d68 MGD |
22357 | case BFD_RELOC_ARM_HVC: |
22358 | if (((unsigned long) value) > 0xffff) | |
22359 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22360 | _("invalid hvc expression")); | |
22361 | newval = md_chars_to_number (buf, INSN_SIZE); | |
22362 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); | |
22363 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22364 | break; | |
22365 | ||
c19d1205 | 22366 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 22367 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
22368 | { |
22369 | if (((unsigned long) value) > 0xff) | |
22370 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22371 | _("invalid swi expression")); | |
2fc8bdac | 22372 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
22373 | newval |= value; |
22374 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22375 | } | |
22376 | else | |
22377 | { | |
22378 | if (((unsigned long) value) > 0x00ffffff) | |
22379 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22380 | _("invalid swi expression")); | |
2fc8bdac | 22381 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
22382 | newval |= value; |
22383 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22384 | } | |
22385 | break; | |
a737bd4d | 22386 | |
c19d1205 ZW |
22387 | case BFD_RELOC_ARM_MULTI: |
22388 | if (((unsigned long) value) > 0xffff) | |
22389 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22390 | _("invalid expression in load/store multiple")); | |
22391 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
22392 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22393 | break; | |
a737bd4d | 22394 | |
c19d1205 | 22395 | #ifdef OBJ_ELF |
39b41c9c | 22396 | case BFD_RELOC_ARM_PCREL_CALL: |
267bf995 RR |
22397 | |
22398 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
22399 | && fixP->fx_addsy | |
34e77a92 | 22400 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22401 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
22402 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
22403 | /* Flip the bl to blx. This is a simple flip | |
22404 | bit here because we generate PCREL_CALL for | |
22405 | unconditional bls. */ | |
22406 | { | |
22407 | newval = md_chars_to_number (buf, INSN_SIZE); | |
22408 | newval = newval | 0x10000000; | |
22409 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22410 | temp = 1; | |
22411 | fixP->fx_done = 1; | |
22412 | } | |
39b41c9c PB |
22413 | else |
22414 | temp = 3; | |
22415 | goto arm_branch_common; | |
22416 | ||
22417 | case BFD_RELOC_ARM_PCREL_JUMP: | |
267bf995 RR |
22418 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
22419 | && fixP->fx_addsy | |
34e77a92 | 22420 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22421 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
22422 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
22423 | { | |
22424 | /* This would map to a bl<cond>, b<cond>, | |
22425 | b<always> to a Thumb function. We | |
22426 | need to force a relocation for this particular | |
22427 | case. */ | |
22428 | newval = md_chars_to_number (buf, INSN_SIZE); | |
22429 | fixP->fx_done = 0; | |
22430 | } | |
22431 | ||
2fc8bdac | 22432 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 22433 | #endif |
39b41c9c PB |
22434 | case BFD_RELOC_ARM_PCREL_BRANCH: |
22435 | temp = 3; | |
22436 | goto arm_branch_common; | |
a737bd4d | 22437 | |
39b41c9c | 22438 | case BFD_RELOC_ARM_PCREL_BLX: |
267bf995 | 22439 | |
39b41c9c | 22440 | temp = 1; |
267bf995 RR |
22441 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
22442 | && fixP->fx_addsy | |
34e77a92 | 22443 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22444 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
22445 | && ARM_IS_FUNC (fixP->fx_addsy)) | |
22446 | { | |
22447 | /* Flip the blx to a bl and warn. */ | |
22448 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
22449 | newval = 0xeb000000; | |
22450 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
22451 | _("blx to '%s' an ARM ISA state function changed to bl"), | |
22452 | name); | |
22453 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22454 | temp = 3; | |
22455 | fixP->fx_done = 1; | |
22456 | } | |
22457 | ||
22458 | #ifdef OBJ_ELF | |
22459 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
477330fc | 22460 | fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL; |
267bf995 RR |
22461 | #endif |
22462 | ||
39b41c9c | 22463 | arm_branch_common: |
c19d1205 | 22464 | /* We are going to store value (shifted right by two) in the |
39b41c9c PB |
22465 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
22466 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must | |
22467 | also be be clear. */ | |
22468 | if (value & temp) | |
c19d1205 | 22469 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
22470 | _("misaligned branch destination")); |
22471 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
22472 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
08f10d51 | 22473 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 22474 | |
2fc8bdac | 22475 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 22476 | { |
2fc8bdac ZW |
22477 | newval = md_chars_to_number (buf, INSN_SIZE); |
22478 | newval |= (value >> 2) & 0x00ffffff; | |
7ae2971b PB |
22479 | /* Set the H bit on BLX instructions. */ |
22480 | if (temp == 1) | |
22481 | { | |
22482 | if (value & 2) | |
22483 | newval |= 0x01000000; | |
22484 | else | |
22485 | newval &= ~0x01000000; | |
22486 | } | |
2fc8bdac | 22487 | md_number_to_chars (buf, newval, INSN_SIZE); |
c19d1205 | 22488 | } |
c19d1205 | 22489 | break; |
a737bd4d | 22490 | |
25fe350b MS |
22491 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ |
22492 | /* CBZ can only branch forward. */ | |
a737bd4d | 22493 | |
738755b0 | 22494 | /* Attempts to use CBZ to branch to the next instruction |
477330fc RM |
22495 | (which, strictly speaking, are prohibited) will be turned into |
22496 | no-ops. | |
738755b0 MS |
22497 | |
22498 | FIXME: It may be better to remove the instruction completely and | |
22499 | perform relaxation. */ | |
22500 | if (value == -2) | |
2fc8bdac ZW |
22501 | { |
22502 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
738755b0 | 22503 | newval = 0xbf00; /* NOP encoding T1 */ |
2fc8bdac ZW |
22504 | md_number_to_chars (buf, newval, THUMB_SIZE); |
22505 | } | |
738755b0 MS |
22506 | else |
22507 | { | |
22508 | if (value & ~0x7e) | |
08f10d51 | 22509 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
738755b0 | 22510 | |
477330fc | 22511 | if (fixP->fx_done || !seg->use_rela_p) |
738755b0 MS |
22512 | { |
22513 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22514 | newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); | |
22515 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22516 | } | |
22517 | } | |
c19d1205 | 22518 | break; |
a737bd4d | 22519 | |
c19d1205 | 22520 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac | 22521 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
08f10d51 | 22522 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 22523 | |
2fc8bdac ZW |
22524 | if (fixP->fx_done || !seg->use_rela_p) |
22525 | { | |
22526 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22527 | newval |= (value & 0x1ff) >> 1; | |
22528 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22529 | } | |
c19d1205 | 22530 | break; |
a737bd4d | 22531 | |
c19d1205 | 22532 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac | 22533 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
08f10d51 | 22534 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 22535 | |
2fc8bdac ZW |
22536 | if (fixP->fx_done || !seg->use_rela_p) |
22537 | { | |
22538 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22539 | newval |= (value & 0xfff) >> 1; | |
22540 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22541 | } | |
c19d1205 | 22542 | break; |
a737bd4d | 22543 | |
c19d1205 | 22544 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
267bf995 RR |
22545 | if (fixP->fx_addsy |
22546 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 22547 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22548 | && ARM_IS_FUNC (fixP->fx_addsy) |
22549 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
22550 | { | |
22551 | /* Force a relocation for a branch 20 bits wide. */ | |
22552 | fixP->fx_done = 0; | |
22553 | } | |
08f10d51 | 22554 | if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff)) |
2fc8bdac ZW |
22555 | as_bad_where (fixP->fx_file, fixP->fx_line, |
22556 | _("conditional branch out of range")); | |
404ff6b5 | 22557 | |
2fc8bdac ZW |
22558 | if (fixP->fx_done || !seg->use_rela_p) |
22559 | { | |
22560 | offsetT newval2; | |
22561 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 22562 | |
2fc8bdac ZW |
22563 | S = (value & 0x00100000) >> 20; |
22564 | J2 = (value & 0x00080000) >> 19; | |
22565 | J1 = (value & 0x00040000) >> 18; | |
22566 | hi = (value & 0x0003f000) >> 12; | |
22567 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 22568 | |
2fc8bdac ZW |
22569 | newval = md_chars_to_number (buf, THUMB_SIZE); |
22570 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
22571 | newval |= (S << 10) | hi; | |
22572 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
22573 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22574 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
22575 | } | |
c19d1205 | 22576 | break; |
6c43fab6 | 22577 | |
c19d1205 | 22578 | case BFD_RELOC_THUMB_PCREL_BLX: |
267bf995 RR |
22579 | /* If there is a blx from a thumb state function to |
22580 | another thumb function flip this to a bl and warn | |
22581 | about it. */ | |
22582 | ||
22583 | if (fixP->fx_addsy | |
34e77a92 | 22584 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22585 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
22586 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
22587 | { | |
22588 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
22589 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
22590 | _("blx to Thumb func '%s' from Thumb ISA state changed to bl"), | |
22591 | name); | |
22592 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
22593 | newval = newval | 0x1000; | |
22594 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
22595 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
22596 | fixP->fx_done = 1; | |
22597 | } | |
22598 | ||
22599 | ||
22600 | goto thumb_bl_common; | |
22601 | ||
c19d1205 | 22602 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
267bf995 RR |
22603 | /* A bl from Thumb state ISA to an internal ARM state function |
22604 | is converted to a blx. */ | |
22605 | if (fixP->fx_addsy | |
22606 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 22607 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22608 | && ARM_IS_FUNC (fixP->fx_addsy) |
22609 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
22610 | { | |
22611 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
22612 | newval = newval & ~0x1000; | |
22613 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
22614 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX; | |
22615 | fixP->fx_done = 1; | |
22616 | } | |
22617 | ||
22618 | thumb_bl_common: | |
22619 | ||
2fc8bdac ZW |
22620 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
22621 | /* For a BLX instruction, make sure that the relocation is rounded up | |
22622 | to a word boundary. This follows the semantics of the instruction | |
22623 | which specifies that bit 1 of the target address will come from bit | |
22624 | 1 of the base address. */ | |
d406f3e4 JB |
22625 | value = (value + 3) & ~ 3; |
22626 | ||
22627 | #ifdef OBJ_ELF | |
22628 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 | |
22629 | && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) | |
22630 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
22631 | #endif | |
404ff6b5 | 22632 | |
2b2f5df9 NC |
22633 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
22634 | { | |
22635 | if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))) | |
22636 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); | |
22637 | else if ((value & ~0x1ffffff) | |
22638 | && ((value & ~0x1ffffff) != ~0x1ffffff)) | |
22639 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22640 | _("Thumb2 branch out of range")); | |
22641 | } | |
4a42ebbc RR |
22642 | |
22643 | if (fixP->fx_done || !seg->use_rela_p) | |
22644 | encode_thumb2_b_bl_offset (buf, value); | |
22645 | ||
c19d1205 | 22646 | break; |
404ff6b5 | 22647 | |
c19d1205 | 22648 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
08f10d51 NC |
22649 | if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff)) |
22650 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); | |
6c43fab6 | 22651 | |
2fc8bdac | 22652 | if (fixP->fx_done || !seg->use_rela_p) |
4a42ebbc | 22653 | encode_thumb2_b_bl_offset (buf, value); |
6c43fab6 | 22654 | |
2fc8bdac | 22655 | break; |
a737bd4d | 22656 | |
2fc8bdac ZW |
22657 | case BFD_RELOC_8: |
22658 | if (fixP->fx_done || !seg->use_rela_p) | |
4b1a927e | 22659 | *buf = value; |
c19d1205 | 22660 | break; |
a737bd4d | 22661 | |
c19d1205 | 22662 | case BFD_RELOC_16: |
2fc8bdac | 22663 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 22664 | md_number_to_chars (buf, value, 2); |
c19d1205 | 22665 | break; |
a737bd4d | 22666 | |
c19d1205 | 22667 | #ifdef OBJ_ELF |
0855e32b NS |
22668 | case BFD_RELOC_ARM_TLS_CALL: |
22669 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
22670 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
22671 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
0855e32b | 22672 | case BFD_RELOC_ARM_TLS_GOTDESC: |
c19d1205 ZW |
22673 | case BFD_RELOC_ARM_TLS_GD32: |
22674 | case BFD_RELOC_ARM_TLS_LE32: | |
22675 | case BFD_RELOC_ARM_TLS_IE32: | |
22676 | case BFD_RELOC_ARM_TLS_LDM32: | |
22677 | case BFD_RELOC_ARM_TLS_LDO32: | |
22678 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
4b1a927e | 22679 | break; |
6c43fab6 | 22680 | |
c19d1205 ZW |
22681 | case BFD_RELOC_ARM_GOT32: |
22682 | case BFD_RELOC_ARM_GOTOFF: | |
c19d1205 | 22683 | break; |
b43420e6 NC |
22684 | |
22685 | case BFD_RELOC_ARM_GOT_PREL: | |
22686 | if (fixP->fx_done || !seg->use_rela_p) | |
477330fc | 22687 | md_number_to_chars (buf, value, 4); |
b43420e6 NC |
22688 | break; |
22689 | ||
9a6f4e97 NS |
22690 | case BFD_RELOC_ARM_TARGET2: |
22691 | /* TARGET2 is not partial-inplace, so we need to write the | |
477330fc RM |
22692 | addend here for REL targets, because it won't be written out |
22693 | during reloc processing later. */ | |
9a6f4e97 NS |
22694 | if (fixP->fx_done || !seg->use_rela_p) |
22695 | md_number_to_chars (buf, fixP->fx_offset, 4); | |
22696 | break; | |
c19d1205 | 22697 | #endif |
6c43fab6 | 22698 | |
c19d1205 ZW |
22699 | case BFD_RELOC_RVA: |
22700 | case BFD_RELOC_32: | |
22701 | case BFD_RELOC_ARM_TARGET1: | |
22702 | case BFD_RELOC_ARM_ROSEGREL32: | |
22703 | case BFD_RELOC_ARM_SBREL32: | |
22704 | case BFD_RELOC_32_PCREL: | |
f0927246 NC |
22705 | #ifdef TE_PE |
22706 | case BFD_RELOC_32_SECREL: | |
22707 | #endif | |
2fc8bdac | 22708 | if (fixP->fx_done || !seg->use_rela_p) |
53baae48 NC |
22709 | #ifdef TE_WINCE |
22710 | /* For WinCE we only do this for pcrel fixups. */ | |
22711 | if (fixP->fx_done || fixP->fx_pcrel) | |
22712 | #endif | |
22713 | md_number_to_chars (buf, value, 4); | |
c19d1205 | 22714 | break; |
6c43fab6 | 22715 | |
c19d1205 ZW |
22716 | #ifdef OBJ_ELF |
22717 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 22718 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
22719 | { |
22720 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
22721 | if ((value ^ (value >> 1)) & 0x40000000) | |
22722 | { | |
22723 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22724 | _("rel31 relocation overflow")); | |
22725 | } | |
22726 | newval |= value & 0x7fffffff; | |
22727 | md_number_to_chars (buf, newval, 4); | |
22728 | } | |
22729 | break; | |
c19d1205 | 22730 | #endif |
a737bd4d | 22731 | |
c19d1205 | 22732 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 22733 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
c19d1205 ZW |
22734 | if (value < -1023 || value > 1023 || (value & 3)) |
22735 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22736 | _("co-processor offset out of range")); | |
22737 | cp_off_common: | |
26d97720 | 22738 | sign = value > 0; |
c19d1205 ZW |
22739 | if (value < 0) |
22740 | value = -value; | |
8f06b2d8 PB |
22741 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
22742 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
22743 | newval = md_chars_to_number (buf, INSN_SIZE); | |
22744 | else | |
22745 | newval = get_thumb32_insn (buf); | |
26d97720 NS |
22746 | if (value == 0) |
22747 | newval &= 0xffffff00; | |
22748 | else | |
22749 | { | |
22750 | newval &= 0xff7fff00; | |
22751 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); | |
22752 | } | |
8f06b2d8 PB |
22753 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
22754 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
22755 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22756 | else | |
22757 | put_thumb32_insn (buf, newval); | |
c19d1205 | 22758 | break; |
a737bd4d | 22759 | |
c19d1205 | 22760 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 22761 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
22762 | if (value < -255 || value > 255) |
22763 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22764 | _("co-processor offset out of range")); | |
df7849c5 | 22765 | value *= 4; |
c19d1205 | 22766 | goto cp_off_common; |
6c43fab6 | 22767 | |
c19d1205 ZW |
22768 | case BFD_RELOC_ARM_THUMB_OFFSET: |
22769 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22770 | /* Exactly what ranges, and where the offset is inserted depends | |
22771 | on the type of instruction, we can establish this from the | |
22772 | top 4 bits. */ | |
22773 | switch (newval >> 12) | |
22774 | { | |
22775 | case 4: /* PC load. */ | |
22776 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
22777 | forced to zero for these loads; md_pcrel_from has already | |
22778 | compensated for this. */ | |
22779 | if (value & 3) | |
22780 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22781 | _("invalid offset, target not word aligned (0x%08lX)"), | |
0359e808 NC |
22782 | (((unsigned long) fixP->fx_frag->fr_address |
22783 | + (unsigned long) fixP->fx_where) & ~3) | |
22784 | + (unsigned long) value); | |
a737bd4d | 22785 | |
c19d1205 ZW |
22786 | if (value & ~0x3fc) |
22787 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22788 | _("invalid offset, value too big (0x%08lX)"), | |
22789 | (long) value); | |
a737bd4d | 22790 | |
c19d1205 ZW |
22791 | newval |= value >> 2; |
22792 | break; | |
a737bd4d | 22793 | |
c19d1205 ZW |
22794 | case 9: /* SP load/store. */ |
22795 | if (value & ~0x3fc) | |
22796 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22797 | _("invalid offset, value too big (0x%08lX)"), | |
22798 | (long) value); | |
22799 | newval |= value >> 2; | |
22800 | break; | |
6c43fab6 | 22801 | |
c19d1205 ZW |
22802 | case 6: /* Word load/store. */ |
22803 | if (value & ~0x7c) | |
22804 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22805 | _("invalid offset, value too big (0x%08lX)"), | |
22806 | (long) value); | |
22807 | newval |= value << 4; /* 6 - 2. */ | |
22808 | break; | |
a737bd4d | 22809 | |
c19d1205 ZW |
22810 | case 7: /* Byte load/store. */ |
22811 | if (value & ~0x1f) | |
22812 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22813 | _("invalid offset, value too big (0x%08lX)"), | |
22814 | (long) value); | |
22815 | newval |= value << 6; | |
22816 | break; | |
a737bd4d | 22817 | |
c19d1205 ZW |
22818 | case 8: /* Halfword load/store. */ |
22819 | if (value & ~0x3e) | |
22820 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22821 | _("invalid offset, value too big (0x%08lX)"), | |
22822 | (long) value); | |
22823 | newval |= value << 5; /* 6 - 1. */ | |
22824 | break; | |
a737bd4d | 22825 | |
c19d1205 ZW |
22826 | default: |
22827 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22828 | "Unable to process relocation for thumb opcode: %lx", | |
22829 | (unsigned long) newval); | |
22830 | break; | |
22831 | } | |
22832 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22833 | break; | |
a737bd4d | 22834 | |
c19d1205 ZW |
22835 | case BFD_RELOC_ARM_THUMB_ADD: |
22836 | /* This is a complicated relocation, since we use it for all of | |
22837 | the following immediate relocations: | |
a737bd4d | 22838 | |
c19d1205 ZW |
22839 | 3bit ADD/SUB |
22840 | 8bit ADD/SUB | |
22841 | 9bit ADD/SUB SP word-aligned | |
22842 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 22843 | |
c19d1205 ZW |
22844 | The type of instruction being processed is encoded in the |
22845 | instruction field: | |
a737bd4d | 22846 | |
c19d1205 ZW |
22847 | 0x8000 SUB |
22848 | 0x00F0 Rd | |
22849 | 0x000F Rs | |
22850 | */ | |
22851 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22852 | { | |
22853 | int rd = (newval >> 4) & 0xf; | |
22854 | int rs = newval & 0xf; | |
22855 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 22856 | |
c19d1205 ZW |
22857 | /* Check for HI regs, only very restricted cases allowed: |
22858 | Adjusting SP, and using PC or SP to get an address. */ | |
22859 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
22860 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
22861 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22862 | _("invalid Hi register with immediate")); | |
a737bd4d | 22863 | |
c19d1205 ZW |
22864 | /* If value is negative, choose the opposite instruction. */ |
22865 | if (value < 0) | |
22866 | { | |
22867 | value = -value; | |
22868 | subtract = !subtract; | |
22869 | if (value < 0) | |
22870 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22871 | _("immediate value out of range")); | |
22872 | } | |
a737bd4d | 22873 | |
c19d1205 ZW |
22874 | if (rd == REG_SP) |
22875 | { | |
22876 | if (value & ~0x1fc) | |
22877 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22878 | _("invalid immediate for stack address calculation")); | |
22879 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
22880 | newval |= value >> 2; | |
22881 | } | |
22882 | else if (rs == REG_PC || rs == REG_SP) | |
22883 | { | |
22884 | if (subtract || value & ~0x3fc) | |
22885 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22886 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
22887 | (unsigned long) value); | |
22888 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); | |
22889 | newval |= rd << 8; | |
22890 | newval |= value >> 2; | |
22891 | } | |
22892 | else if (rs == rd) | |
22893 | { | |
22894 | if (value & ~0xff) | |
22895 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22896 | _("immediate value out of range")); | |
22897 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
22898 | newval |= (rd << 8) | value; | |
22899 | } | |
22900 | else | |
22901 | { | |
22902 | if (value & ~0x7) | |
22903 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22904 | _("immediate value out of range")); | |
22905 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
22906 | newval |= rd | (rs << 3) | (value << 6); | |
22907 | } | |
22908 | } | |
22909 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22910 | break; | |
a737bd4d | 22911 | |
c19d1205 ZW |
22912 | case BFD_RELOC_ARM_THUMB_IMM: |
22913 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22914 | if (value < 0 || value > 255) | |
22915 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
4e6e072b | 22916 | _("invalid immediate: %ld is out of range"), |
c19d1205 ZW |
22917 | (long) value); |
22918 | newval |= value; | |
22919 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22920 | break; | |
a737bd4d | 22921 | |
c19d1205 ZW |
22922 | case BFD_RELOC_ARM_THUMB_SHIFT: |
22923 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
22924 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
22925 | temp = newval & 0xf800; | |
22926 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
22927 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22928 | _("invalid shift value: %ld"), (long) value); | |
22929 | /* Shifts of zero must be encoded as LSL. */ | |
22930 | if (value == 0) | |
22931 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
22932 | /* Shifts of 32 are encoded as zero. */ | |
22933 | else if (value == 32) | |
22934 | value = 0; | |
22935 | newval |= value << 6; | |
22936 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22937 | break; | |
a737bd4d | 22938 | |
c19d1205 ZW |
22939 | case BFD_RELOC_VTABLE_INHERIT: |
22940 | case BFD_RELOC_VTABLE_ENTRY: | |
22941 | fixP->fx_done = 0; | |
22942 | return; | |
6c43fab6 | 22943 | |
b6895b4f PB |
22944 | case BFD_RELOC_ARM_MOVW: |
22945 | case BFD_RELOC_ARM_MOVT: | |
22946 | case BFD_RELOC_ARM_THUMB_MOVW: | |
22947 | case BFD_RELOC_ARM_THUMB_MOVT: | |
22948 | if (fixP->fx_done || !seg->use_rela_p) | |
22949 | { | |
22950 | /* REL format relocations are limited to a 16-bit addend. */ | |
22951 | if (!fixP->fx_done) | |
22952 | { | |
39623e12 | 22953 | if (value < -0x8000 || value > 0x7fff) |
b6895b4f | 22954 | as_bad_where (fixP->fx_file, fixP->fx_line, |
ff5075ca | 22955 | _("offset out of range")); |
b6895b4f PB |
22956 | } |
22957 | else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
22958 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
22959 | { | |
22960 | value >>= 16; | |
22961 | } | |
22962 | ||
22963 | if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
22964 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
22965 | { | |
22966 | newval = get_thumb32_insn (buf); | |
22967 | newval &= 0xfbf08f00; | |
22968 | newval |= (value & 0xf000) << 4; | |
22969 | newval |= (value & 0x0800) << 15; | |
22970 | newval |= (value & 0x0700) << 4; | |
22971 | newval |= (value & 0x00ff); | |
22972 | put_thumb32_insn (buf, newval); | |
22973 | } | |
22974 | else | |
22975 | { | |
22976 | newval = md_chars_to_number (buf, 4); | |
22977 | newval &= 0xfff0f000; | |
22978 | newval |= value & 0x0fff; | |
22979 | newval |= (value & 0xf000) << 4; | |
22980 | md_number_to_chars (buf, newval, 4); | |
22981 | } | |
22982 | } | |
22983 | return; | |
22984 | ||
4962c51a MS |
22985 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
22986 | case BFD_RELOC_ARM_ALU_PC_G0: | |
22987 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
22988 | case BFD_RELOC_ARM_ALU_PC_G1: | |
22989 | case BFD_RELOC_ARM_ALU_PC_G2: | |
22990 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
22991 | case BFD_RELOC_ARM_ALU_SB_G0: | |
22992 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
22993 | case BFD_RELOC_ARM_ALU_SB_G1: | |
22994 | case BFD_RELOC_ARM_ALU_SB_G2: | |
9c2799c2 | 22995 | gas_assert (!fixP->fx_done); |
4962c51a MS |
22996 | if (!seg->use_rela_p) |
22997 | { | |
477330fc RM |
22998 | bfd_vma insn; |
22999 | bfd_vma encoded_addend; | |
23000 | bfd_vma addend_abs = abs (value); | |
23001 | ||
23002 | /* Check that the absolute value of the addend can be | |
23003 | expressed as an 8-bit constant plus a rotation. */ | |
23004 | encoded_addend = encode_arm_immediate (addend_abs); | |
23005 | if (encoded_addend == (unsigned int) FAIL) | |
4962c51a | 23006 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
23007 | _("the offset 0x%08lX is not representable"), |
23008 | (unsigned long) addend_abs); | |
23009 | ||
23010 | /* Extract the instruction. */ | |
23011 | insn = md_chars_to_number (buf, INSN_SIZE); | |
23012 | ||
23013 | /* If the addend is positive, use an ADD instruction. | |
23014 | Otherwise use a SUB. Take care not to destroy the S bit. */ | |
23015 | insn &= 0xff1fffff; | |
23016 | if (value < 0) | |
23017 | insn |= 1 << 22; | |
23018 | else | |
23019 | insn |= 1 << 23; | |
23020 | ||
23021 | /* Place the encoded addend into the first 12 bits of the | |
23022 | instruction. */ | |
23023 | insn &= 0xfffff000; | |
23024 | insn |= encoded_addend; | |
23025 | ||
23026 | /* Update the instruction. */ | |
23027 | md_number_to_chars (buf, insn, INSN_SIZE); | |
4962c51a MS |
23028 | } |
23029 | break; | |
23030 | ||
23031 | case BFD_RELOC_ARM_LDR_PC_G0: | |
23032 | case BFD_RELOC_ARM_LDR_PC_G1: | |
23033 | case BFD_RELOC_ARM_LDR_PC_G2: | |
23034 | case BFD_RELOC_ARM_LDR_SB_G0: | |
23035 | case BFD_RELOC_ARM_LDR_SB_G1: | |
23036 | case BFD_RELOC_ARM_LDR_SB_G2: | |
9c2799c2 | 23037 | gas_assert (!fixP->fx_done); |
4962c51a | 23038 | if (!seg->use_rela_p) |
477330fc RM |
23039 | { |
23040 | bfd_vma insn; | |
23041 | bfd_vma addend_abs = abs (value); | |
4962c51a | 23042 | |
477330fc RM |
23043 | /* Check that the absolute value of the addend can be |
23044 | encoded in 12 bits. */ | |
23045 | if (addend_abs >= 0x1000) | |
4962c51a | 23046 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
23047 | _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), |
23048 | (unsigned long) addend_abs); | |
23049 | ||
23050 | /* Extract the instruction. */ | |
23051 | insn = md_chars_to_number (buf, INSN_SIZE); | |
23052 | ||
23053 | /* If the addend is negative, clear bit 23 of the instruction. | |
23054 | Otherwise set it. */ | |
23055 | if (value < 0) | |
23056 | insn &= ~(1 << 23); | |
23057 | else | |
23058 | insn |= 1 << 23; | |
23059 | ||
23060 | /* Place the absolute value of the addend into the first 12 bits | |
23061 | of the instruction. */ | |
23062 | insn &= 0xfffff000; | |
23063 | insn |= addend_abs; | |
23064 | ||
23065 | /* Update the instruction. */ | |
23066 | md_number_to_chars (buf, insn, INSN_SIZE); | |
23067 | } | |
4962c51a MS |
23068 | break; |
23069 | ||
23070 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
23071 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
23072 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
23073 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
23074 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
23075 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
9c2799c2 | 23076 | gas_assert (!fixP->fx_done); |
4962c51a | 23077 | if (!seg->use_rela_p) |
477330fc RM |
23078 | { |
23079 | bfd_vma insn; | |
23080 | bfd_vma addend_abs = abs (value); | |
4962c51a | 23081 | |
477330fc RM |
23082 | /* Check that the absolute value of the addend can be |
23083 | encoded in 8 bits. */ | |
23084 | if (addend_abs >= 0x100) | |
4962c51a | 23085 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
23086 | _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), |
23087 | (unsigned long) addend_abs); | |
23088 | ||
23089 | /* Extract the instruction. */ | |
23090 | insn = md_chars_to_number (buf, INSN_SIZE); | |
23091 | ||
23092 | /* If the addend is negative, clear bit 23 of the instruction. | |
23093 | Otherwise set it. */ | |
23094 | if (value < 0) | |
23095 | insn &= ~(1 << 23); | |
23096 | else | |
23097 | insn |= 1 << 23; | |
23098 | ||
23099 | /* Place the first four bits of the absolute value of the addend | |
23100 | into the first 4 bits of the instruction, and the remaining | |
23101 | four into bits 8 .. 11. */ | |
23102 | insn &= 0xfffff0f0; | |
23103 | insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); | |
23104 | ||
23105 | /* Update the instruction. */ | |
23106 | md_number_to_chars (buf, insn, INSN_SIZE); | |
23107 | } | |
4962c51a MS |
23108 | break; |
23109 | ||
23110 | case BFD_RELOC_ARM_LDC_PC_G0: | |
23111 | case BFD_RELOC_ARM_LDC_PC_G1: | |
23112 | case BFD_RELOC_ARM_LDC_PC_G2: | |
23113 | case BFD_RELOC_ARM_LDC_SB_G0: | |
23114 | case BFD_RELOC_ARM_LDC_SB_G1: | |
23115 | case BFD_RELOC_ARM_LDC_SB_G2: | |
9c2799c2 | 23116 | gas_assert (!fixP->fx_done); |
4962c51a | 23117 | if (!seg->use_rela_p) |
477330fc RM |
23118 | { |
23119 | bfd_vma insn; | |
23120 | bfd_vma addend_abs = abs (value); | |
4962c51a | 23121 | |
477330fc RM |
23122 | /* Check that the absolute value of the addend is a multiple of |
23123 | four and, when divided by four, fits in 8 bits. */ | |
23124 | if (addend_abs & 0x3) | |
4962c51a | 23125 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
23126 | _("bad offset 0x%08lX (must be word-aligned)"), |
23127 | (unsigned long) addend_abs); | |
4962c51a | 23128 | |
477330fc | 23129 | if ((addend_abs >> 2) > 0xff) |
4962c51a | 23130 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
23131 | _("bad offset 0x%08lX (must be an 8-bit number of words)"), |
23132 | (unsigned long) addend_abs); | |
23133 | ||
23134 | /* Extract the instruction. */ | |
23135 | insn = md_chars_to_number (buf, INSN_SIZE); | |
23136 | ||
23137 | /* If the addend is negative, clear bit 23 of the instruction. | |
23138 | Otherwise set it. */ | |
23139 | if (value < 0) | |
23140 | insn &= ~(1 << 23); | |
23141 | else | |
23142 | insn |= 1 << 23; | |
23143 | ||
23144 | /* Place the addend (divided by four) into the first eight | |
23145 | bits of the instruction. */ | |
23146 | insn &= 0xfffffff0; | |
23147 | insn |= addend_abs >> 2; | |
23148 | ||
23149 | /* Update the instruction. */ | |
23150 | md_number_to_chars (buf, insn, INSN_SIZE); | |
23151 | } | |
4962c51a MS |
23152 | break; |
23153 | ||
845b51d6 PB |
23154 | case BFD_RELOC_ARM_V4BX: |
23155 | /* This will need to go in the object file. */ | |
23156 | fixP->fx_done = 0; | |
23157 | break; | |
23158 | ||
c19d1205 ZW |
23159 | case BFD_RELOC_UNUSED: |
23160 | default: | |
23161 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23162 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
23163 | } | |
6c43fab6 RE |
23164 | } |
23165 | ||
c19d1205 ZW |
23166 | /* Translate internal representation of relocation info to BFD target |
23167 | format. */ | |
a737bd4d | 23168 | |
c19d1205 | 23169 | arelent * |
00a97672 | 23170 | tc_gen_reloc (asection *section, fixS *fixp) |
a737bd4d | 23171 | { |
c19d1205 ZW |
23172 | arelent * reloc; |
23173 | bfd_reloc_code_real_type code; | |
a737bd4d | 23174 | |
21d799b5 | 23175 | reloc = (arelent *) xmalloc (sizeof (arelent)); |
a737bd4d | 23176 | |
21d799b5 | 23177 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
c19d1205 ZW |
23178 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
23179 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 23180 | |
2fc8bdac | 23181 | if (fixp->fx_pcrel) |
00a97672 RS |
23182 | { |
23183 | if (section->use_rela_p) | |
23184 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
23185 | else | |
23186 | fixp->fx_offset = reloc->address; | |
23187 | } | |
c19d1205 | 23188 | reloc->addend = fixp->fx_offset; |
a737bd4d | 23189 | |
c19d1205 | 23190 | switch (fixp->fx_r_type) |
a737bd4d | 23191 | { |
c19d1205 ZW |
23192 | case BFD_RELOC_8: |
23193 | if (fixp->fx_pcrel) | |
23194 | { | |
23195 | code = BFD_RELOC_8_PCREL; | |
23196 | break; | |
23197 | } | |
a737bd4d | 23198 | |
c19d1205 ZW |
23199 | case BFD_RELOC_16: |
23200 | if (fixp->fx_pcrel) | |
23201 | { | |
23202 | code = BFD_RELOC_16_PCREL; | |
23203 | break; | |
23204 | } | |
6c43fab6 | 23205 | |
c19d1205 ZW |
23206 | case BFD_RELOC_32: |
23207 | if (fixp->fx_pcrel) | |
23208 | { | |
23209 | code = BFD_RELOC_32_PCREL; | |
23210 | break; | |
23211 | } | |
a737bd4d | 23212 | |
b6895b4f PB |
23213 | case BFD_RELOC_ARM_MOVW: |
23214 | if (fixp->fx_pcrel) | |
23215 | { | |
23216 | code = BFD_RELOC_ARM_MOVW_PCREL; | |
23217 | break; | |
23218 | } | |
23219 | ||
23220 | case BFD_RELOC_ARM_MOVT: | |
23221 | if (fixp->fx_pcrel) | |
23222 | { | |
23223 | code = BFD_RELOC_ARM_MOVT_PCREL; | |
23224 | break; | |
23225 | } | |
23226 | ||
23227 | case BFD_RELOC_ARM_THUMB_MOVW: | |
23228 | if (fixp->fx_pcrel) | |
23229 | { | |
23230 | code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; | |
23231 | break; | |
23232 | } | |
23233 | ||
23234 | case BFD_RELOC_ARM_THUMB_MOVT: | |
23235 | if (fixp->fx_pcrel) | |
23236 | { | |
23237 | code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; | |
23238 | break; | |
23239 | } | |
23240 | ||
c19d1205 ZW |
23241 | case BFD_RELOC_NONE: |
23242 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
23243 | case BFD_RELOC_ARM_PCREL_BLX: | |
23244 | case BFD_RELOC_RVA: | |
23245 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
23246 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
23247 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
23248 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
23249 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
23250 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
c19d1205 ZW |
23251 | case BFD_RELOC_VTABLE_ENTRY: |
23252 | case BFD_RELOC_VTABLE_INHERIT: | |
f0927246 NC |
23253 | #ifdef TE_PE |
23254 | case BFD_RELOC_32_SECREL: | |
23255 | #endif | |
c19d1205 ZW |
23256 | code = fixp->fx_r_type; |
23257 | break; | |
a737bd4d | 23258 | |
00adf2d4 JB |
23259 | case BFD_RELOC_THUMB_PCREL_BLX: |
23260 | #ifdef OBJ_ELF | |
23261 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
23262 | code = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
23263 | else | |
23264 | #endif | |
23265 | code = BFD_RELOC_THUMB_PCREL_BLX; | |
23266 | break; | |
23267 | ||
c19d1205 ZW |
23268 | case BFD_RELOC_ARM_LITERAL: |
23269 | case BFD_RELOC_ARM_HWLITERAL: | |
23270 | /* If this is called then the a literal has | |
23271 | been referenced across a section boundary. */ | |
23272 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23273 | _("literal referenced across section boundary")); | |
23274 | return NULL; | |
a737bd4d | 23275 | |
c19d1205 | 23276 | #ifdef OBJ_ELF |
0855e32b NS |
23277 | case BFD_RELOC_ARM_TLS_CALL: |
23278 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
23279 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
23280 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
c19d1205 ZW |
23281 | case BFD_RELOC_ARM_GOT32: |
23282 | case BFD_RELOC_ARM_GOTOFF: | |
b43420e6 | 23283 | case BFD_RELOC_ARM_GOT_PREL: |
c19d1205 ZW |
23284 | case BFD_RELOC_ARM_PLT32: |
23285 | case BFD_RELOC_ARM_TARGET1: | |
23286 | case BFD_RELOC_ARM_ROSEGREL32: | |
23287 | case BFD_RELOC_ARM_SBREL32: | |
23288 | case BFD_RELOC_ARM_PREL31: | |
23289 | case BFD_RELOC_ARM_TARGET2: | |
23290 | case BFD_RELOC_ARM_TLS_LE32: | |
23291 | case BFD_RELOC_ARM_TLS_LDO32: | |
39b41c9c PB |
23292 | case BFD_RELOC_ARM_PCREL_CALL: |
23293 | case BFD_RELOC_ARM_PCREL_JUMP: | |
4962c51a MS |
23294 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
23295 | case BFD_RELOC_ARM_ALU_PC_G0: | |
23296 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
23297 | case BFD_RELOC_ARM_ALU_PC_G1: | |
23298 | case BFD_RELOC_ARM_ALU_PC_G2: | |
23299 | case BFD_RELOC_ARM_LDR_PC_G0: | |
23300 | case BFD_RELOC_ARM_LDR_PC_G1: | |
23301 | case BFD_RELOC_ARM_LDR_PC_G2: | |
23302 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
23303 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
23304 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
23305 | case BFD_RELOC_ARM_LDC_PC_G0: | |
23306 | case BFD_RELOC_ARM_LDC_PC_G1: | |
23307 | case BFD_RELOC_ARM_LDC_PC_G2: | |
23308 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
23309 | case BFD_RELOC_ARM_ALU_SB_G0: | |
23310 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
23311 | case BFD_RELOC_ARM_ALU_SB_G1: | |
23312 | case BFD_RELOC_ARM_ALU_SB_G2: | |
23313 | case BFD_RELOC_ARM_LDR_SB_G0: | |
23314 | case BFD_RELOC_ARM_LDR_SB_G1: | |
23315 | case BFD_RELOC_ARM_LDR_SB_G2: | |
23316 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
23317 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
23318 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
23319 | case BFD_RELOC_ARM_LDC_SB_G0: | |
23320 | case BFD_RELOC_ARM_LDC_SB_G1: | |
23321 | case BFD_RELOC_ARM_LDC_SB_G2: | |
845b51d6 | 23322 | case BFD_RELOC_ARM_V4BX: |
c19d1205 ZW |
23323 | code = fixp->fx_r_type; |
23324 | break; | |
a737bd4d | 23325 | |
0855e32b | 23326 | case BFD_RELOC_ARM_TLS_GOTDESC: |
c19d1205 ZW |
23327 | case BFD_RELOC_ARM_TLS_GD32: |
23328 | case BFD_RELOC_ARM_TLS_IE32: | |
23329 | case BFD_RELOC_ARM_TLS_LDM32: | |
23330 | /* BFD will include the symbol's address in the addend. | |
23331 | But we don't want that, so subtract it out again here. */ | |
23332 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
23333 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
23334 | code = fixp->fx_r_type; | |
23335 | break; | |
23336 | #endif | |
a737bd4d | 23337 | |
c19d1205 ZW |
23338 | case BFD_RELOC_ARM_IMMEDIATE: |
23339 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23340 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
23341 | return NULL; | |
a737bd4d | 23342 | |
c19d1205 ZW |
23343 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
23344 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23345 | _("ADRL used for a symbol not defined in the same file")); | |
23346 | return NULL; | |
a737bd4d | 23347 | |
c19d1205 | 23348 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
23349 | if (section->use_rela_p) |
23350 | { | |
23351 | code = fixp->fx_r_type; | |
23352 | break; | |
23353 | } | |
23354 | ||
c19d1205 ZW |
23355 | if (fixp->fx_addsy != NULL |
23356 | && !S_IS_DEFINED (fixp->fx_addsy) | |
23357 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 23358 | { |
c19d1205 ZW |
23359 | as_bad_where (fixp->fx_file, fixp->fx_line, |
23360 | _("undefined local label `%s'"), | |
23361 | S_GET_NAME (fixp->fx_addsy)); | |
23362 | return NULL; | |
a737bd4d NC |
23363 | } |
23364 | ||
c19d1205 ZW |
23365 | as_bad_where (fixp->fx_file, fixp->fx_line, |
23366 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
23367 | return NULL; | |
a737bd4d | 23368 | |
c19d1205 ZW |
23369 | default: |
23370 | { | |
23371 | char * type; | |
6c43fab6 | 23372 | |
c19d1205 ZW |
23373 | switch (fixp->fx_r_type) |
23374 | { | |
23375 | case BFD_RELOC_NONE: type = "NONE"; break; | |
23376 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
23377 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 23378 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
23379 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
23380 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
23381 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
db187cb9 | 23382 | case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break; |
8f06b2d8 | 23383 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
23384 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
23385 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
23386 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
23387 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
23388 | default: type = _("<unknown>"); break; | |
23389 | } | |
23390 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23391 | _("cannot represent %s relocation in this object file format"), | |
23392 | type); | |
23393 | return NULL; | |
23394 | } | |
a737bd4d | 23395 | } |
6c43fab6 | 23396 | |
c19d1205 ZW |
23397 | #ifdef OBJ_ELF |
23398 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
23399 | && GOT_symbol | |
23400 | && fixp->fx_addsy == GOT_symbol) | |
23401 | { | |
23402 | code = BFD_RELOC_ARM_GOTPC; | |
23403 | reloc->addend = fixp->fx_offset = reloc->address; | |
23404 | } | |
23405 | #endif | |
6c43fab6 | 23406 | |
c19d1205 | 23407 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 23408 | |
c19d1205 ZW |
23409 | if (reloc->howto == NULL) |
23410 | { | |
23411 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23412 | _("cannot represent %s relocation in this object file format"), | |
23413 | bfd_get_reloc_code_name (code)); | |
23414 | return NULL; | |
23415 | } | |
6c43fab6 | 23416 | |
c19d1205 ZW |
23417 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
23418 | vtable entry to be used in the relocation's section offset. */ | |
23419 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
23420 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 23421 | |
c19d1205 | 23422 | return reloc; |
6c43fab6 RE |
23423 | } |
23424 | ||
c19d1205 | 23425 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 23426 | |
c19d1205 ZW |
23427 | void |
23428 | cons_fix_new_arm (fragS * frag, | |
23429 | int where, | |
23430 | int size, | |
62ebcb5c AM |
23431 | expressionS * exp, |
23432 | bfd_reloc_code_real_type reloc) | |
6c43fab6 | 23433 | { |
c19d1205 | 23434 | int pcrel = 0; |
6c43fab6 | 23435 | |
c19d1205 ZW |
23436 | /* Pick a reloc. |
23437 | FIXME: @@ Should look at CPU word size. */ | |
23438 | switch (size) | |
23439 | { | |
23440 | case 1: | |
62ebcb5c | 23441 | reloc = BFD_RELOC_8; |
c19d1205 ZW |
23442 | break; |
23443 | case 2: | |
62ebcb5c | 23444 | reloc = BFD_RELOC_16; |
c19d1205 ZW |
23445 | break; |
23446 | case 4: | |
23447 | default: | |
62ebcb5c | 23448 | reloc = BFD_RELOC_32; |
c19d1205 ZW |
23449 | break; |
23450 | case 8: | |
62ebcb5c | 23451 | reloc = BFD_RELOC_64; |
c19d1205 ZW |
23452 | break; |
23453 | } | |
6c43fab6 | 23454 | |
f0927246 NC |
23455 | #ifdef TE_PE |
23456 | if (exp->X_op == O_secrel) | |
23457 | { | |
23458 | exp->X_op = O_symbol; | |
62ebcb5c | 23459 | reloc = BFD_RELOC_32_SECREL; |
f0927246 NC |
23460 | } |
23461 | #endif | |
23462 | ||
62ebcb5c | 23463 | fix_new_exp (frag, where, size, exp, pcrel, reloc); |
c19d1205 | 23464 | } |
6c43fab6 | 23465 | |
4343666d | 23466 | #if defined (OBJ_COFF) |
c19d1205 ZW |
23467 | void |
23468 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 23469 | { |
c19d1205 ZW |
23470 | /* If the destination of the branch is a defined symbol which does not have |
23471 | the THUMB_FUNC attribute, then we must be calling a function which has | |
23472 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
23473 | function and change the branch to refer to that function instead. */ | |
23474 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
23475 | && fixP->fx_addsy != NULL | |
23476 | && S_IS_DEFINED (fixP->fx_addsy) | |
23477 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 23478 | { |
c19d1205 | 23479 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 23480 | } |
c19d1205 ZW |
23481 | } |
23482 | #endif | |
6c43fab6 | 23483 | |
267bf995 | 23484 | |
c19d1205 ZW |
23485 | int |
23486 | arm_force_relocation (struct fix * fixp) | |
23487 | { | |
23488 | #if defined (OBJ_COFF) && defined (TE_PE) | |
23489 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
23490 | return 1; | |
23491 | #endif | |
6c43fab6 | 23492 | |
267bf995 RR |
23493 | /* In case we have a call or a branch to a function in ARM ISA mode from |
23494 | a thumb function or vice-versa force the relocation. These relocations | |
23495 | are cleared off for some cores that might have blx and simple transformations | |
23496 | are possible. */ | |
23497 | ||
23498 | #ifdef OBJ_ELF | |
23499 | switch (fixp->fx_r_type) | |
23500 | { | |
23501 | case BFD_RELOC_ARM_PCREL_JUMP: | |
23502 | case BFD_RELOC_ARM_PCREL_CALL: | |
23503 | case BFD_RELOC_THUMB_PCREL_BLX: | |
23504 | if (THUMB_IS_FUNC (fixp->fx_addsy)) | |
23505 | return 1; | |
23506 | break; | |
23507 | ||
23508 | case BFD_RELOC_ARM_PCREL_BLX: | |
23509 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
23510 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
23511 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
23512 | if (ARM_IS_FUNC (fixp->fx_addsy)) | |
23513 | return 1; | |
23514 | break; | |
23515 | ||
23516 | default: | |
23517 | break; | |
23518 | } | |
23519 | #endif | |
23520 | ||
b5884301 PB |
23521 | /* Resolve these relocations even if the symbol is extern or weak. |
23522 | Technically this is probably wrong due to symbol preemption. | |
23523 | In practice these relocations do not have enough range to be useful | |
23524 | at dynamic link time, and some code (e.g. in the Linux kernel) | |
23525 | expects these references to be resolved. */ | |
c19d1205 ZW |
23526 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE |
23527 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
b5884301 | 23528 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8 |
0110f2b8 | 23529 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
b5884301 PB |
23530 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
23531 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2 | |
23532 | || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET | |
16805f35 | 23533 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM |
0110f2b8 PB |
23534 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
23535 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
b5884301 PB |
23536 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM |
23537 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12 | |
23538 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM | |
23539 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2) | |
c19d1205 | 23540 | return 0; |
a737bd4d | 23541 | |
4962c51a MS |
23542 | /* Always leave these relocations for the linker. */ |
23543 | if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
23544 | && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
23545 | || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
23546 | return 1; | |
23547 | ||
f0291e4c PB |
23548 | /* Always generate relocations against function symbols. */ |
23549 | if (fixp->fx_r_type == BFD_RELOC_32 | |
23550 | && fixp->fx_addsy | |
23551 | && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) | |
23552 | return 1; | |
23553 | ||
c19d1205 | 23554 | return generic_force_reloc (fixp); |
404ff6b5 AH |
23555 | } |
23556 | ||
0ffdc86c | 23557 | #if defined (OBJ_ELF) || defined (OBJ_COFF) |
e28387c3 PB |
23558 | /* Relocations against function names must be left unadjusted, |
23559 | so that the linker can use this information to generate interworking | |
23560 | stubs. The MIPS version of this function | |
c19d1205 ZW |
23561 | also prevents relocations that are mips-16 specific, but I do not |
23562 | know why it does this. | |
404ff6b5 | 23563 | |
c19d1205 ZW |
23564 | FIXME: |
23565 | There is one other problem that ought to be addressed here, but | |
23566 | which currently is not: Taking the address of a label (rather | |
23567 | than a function) and then later jumping to that address. Such | |
23568 | addresses also ought to have their bottom bit set (assuming that | |
23569 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 23570 | |
c19d1205 ZW |
23571 | bfd_boolean |
23572 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 23573 | { |
c19d1205 ZW |
23574 | if (fixP->fx_addsy == NULL) |
23575 | return 1; | |
404ff6b5 | 23576 | |
e28387c3 PB |
23577 | /* Preserve relocations against symbols with function type. */ |
23578 | if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) | |
c921be7d | 23579 | return FALSE; |
e28387c3 | 23580 | |
c19d1205 ZW |
23581 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
23582 | && fixP->fx_subsy == NULL) | |
c921be7d | 23583 | return FALSE; |
a737bd4d | 23584 | |
c19d1205 ZW |
23585 | /* We need the symbol name for the VTABLE entries. */ |
23586 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
23587 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
c921be7d | 23588 | return FALSE; |
404ff6b5 | 23589 | |
c19d1205 ZW |
23590 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
23591 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
23592 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
23593 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
23594 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
23595 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 | |
23596 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
23597 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 | |
23598 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 | |
0855e32b NS |
23599 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC |
23600 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL | |
23601 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL | |
23602 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ | |
23603 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
c19d1205 | 23604 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) |
c921be7d | 23605 | return FALSE; |
a737bd4d | 23606 | |
4962c51a MS |
23607 | /* Similarly for group relocations. */ |
23608 | if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
23609 | && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
23610 | || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
c921be7d | 23611 | return FALSE; |
4962c51a | 23612 | |
79947c54 CD |
23613 | /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */ |
23614 | if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW | |
23615 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
23616 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL | |
23617 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL | |
23618 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
23619 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT | |
23620 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL | |
23621 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL) | |
c921be7d | 23622 | return FALSE; |
79947c54 | 23623 | |
c921be7d | 23624 | return TRUE; |
a737bd4d | 23625 | } |
0ffdc86c NC |
23626 | #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ |
23627 | ||
23628 | #ifdef OBJ_ELF | |
404ff6b5 | 23629 | |
c19d1205 ZW |
23630 | const char * |
23631 | elf32_arm_target_format (void) | |
404ff6b5 | 23632 | { |
c19d1205 ZW |
23633 | #ifdef TE_SYMBIAN |
23634 | return (target_big_endian | |
23635 | ? "elf32-bigarm-symbian" | |
23636 | : "elf32-littlearm-symbian"); | |
23637 | #elif defined (TE_VXWORKS) | |
23638 | return (target_big_endian | |
23639 | ? "elf32-bigarm-vxworks" | |
23640 | : "elf32-littlearm-vxworks"); | |
b38cadfb NC |
23641 | #elif defined (TE_NACL) |
23642 | return (target_big_endian | |
23643 | ? "elf32-bigarm-nacl" | |
23644 | : "elf32-littlearm-nacl"); | |
c19d1205 ZW |
23645 | #else |
23646 | if (target_big_endian) | |
23647 | return "elf32-bigarm"; | |
23648 | else | |
23649 | return "elf32-littlearm"; | |
23650 | #endif | |
404ff6b5 AH |
23651 | } |
23652 | ||
c19d1205 ZW |
23653 | void |
23654 | armelf_frob_symbol (symbolS * symp, | |
23655 | int * puntp) | |
404ff6b5 | 23656 | { |
c19d1205 ZW |
23657 | elf_frob_symbol (symp, puntp); |
23658 | } | |
23659 | #endif | |
404ff6b5 | 23660 | |
c19d1205 | 23661 | /* MD interface: Finalization. */ |
a737bd4d | 23662 | |
c19d1205 ZW |
23663 | void |
23664 | arm_cleanup (void) | |
23665 | { | |
23666 | literal_pool * pool; | |
a737bd4d | 23667 | |
e07e6e58 NC |
23668 | /* Ensure that all the IT blocks are properly closed. */ |
23669 | check_it_blocks_finished (); | |
23670 | ||
c19d1205 ZW |
23671 | for (pool = list_of_pools; pool; pool = pool->next) |
23672 | { | |
5f4273c7 | 23673 | /* Put it at the end of the relevant section. */ |
c19d1205 ZW |
23674 | subseg_set (pool->section, pool->sub_section); |
23675 | #ifdef OBJ_ELF | |
23676 | arm_elf_change_section (); | |
23677 | #endif | |
23678 | s_ltorg (0); | |
23679 | } | |
404ff6b5 AH |
23680 | } |
23681 | ||
cd000bff DJ |
23682 | #ifdef OBJ_ELF |
23683 | /* Remove any excess mapping symbols generated for alignment frags in | |
23684 | SEC. We may have created a mapping symbol before a zero byte | |
23685 | alignment; remove it if there's a mapping symbol after the | |
23686 | alignment. */ | |
23687 | static void | |
23688 | check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, | |
23689 | void *dummy ATTRIBUTE_UNUSED) | |
23690 | { | |
23691 | segment_info_type *seginfo = seg_info (sec); | |
23692 | fragS *fragp; | |
23693 | ||
23694 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
23695 | return; | |
23696 | ||
23697 | for (fragp = seginfo->frchainP->frch_root; | |
23698 | fragp != NULL; | |
23699 | fragp = fragp->fr_next) | |
23700 | { | |
23701 | symbolS *sym = fragp->tc_frag_data.last_map; | |
23702 | fragS *next = fragp->fr_next; | |
23703 | ||
23704 | /* Variable-sized frags have been converted to fixed size by | |
23705 | this point. But if this was variable-sized to start with, | |
23706 | there will be a fixed-size frag after it. So don't handle | |
23707 | next == NULL. */ | |
23708 | if (sym == NULL || next == NULL) | |
23709 | continue; | |
23710 | ||
23711 | if (S_GET_VALUE (sym) < next->fr_address) | |
23712 | /* Not at the end of this frag. */ | |
23713 | continue; | |
23714 | know (S_GET_VALUE (sym) == next->fr_address); | |
23715 | ||
23716 | do | |
23717 | { | |
23718 | if (next->tc_frag_data.first_map != NULL) | |
23719 | { | |
23720 | /* Next frag starts with a mapping symbol. Discard this | |
23721 | one. */ | |
23722 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
23723 | break; | |
23724 | } | |
23725 | ||
23726 | if (next->fr_next == NULL) | |
23727 | { | |
23728 | /* This mapping symbol is at the end of the section. Discard | |
23729 | it. */ | |
23730 | know (next->fr_fix == 0 && next->fr_var == 0); | |
23731 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
23732 | break; | |
23733 | } | |
23734 | ||
23735 | /* As long as we have empty frags without any mapping symbols, | |
23736 | keep looking. */ | |
23737 | /* If the next frag is non-empty and does not start with a | |
23738 | mapping symbol, then this mapping symbol is required. */ | |
23739 | if (next->fr_address != next->fr_next->fr_address) | |
23740 | break; | |
23741 | ||
23742 | next = next->fr_next; | |
23743 | } | |
23744 | while (next != NULL); | |
23745 | } | |
23746 | } | |
23747 | #endif | |
23748 | ||
c19d1205 ZW |
23749 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
23750 | ARM ones. */ | |
404ff6b5 | 23751 | |
c19d1205 ZW |
23752 | void |
23753 | arm_adjust_symtab (void) | |
404ff6b5 | 23754 | { |
c19d1205 ZW |
23755 | #ifdef OBJ_COFF |
23756 | symbolS * sym; | |
404ff6b5 | 23757 | |
c19d1205 ZW |
23758 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
23759 | { | |
23760 | if (ARM_IS_THUMB (sym)) | |
23761 | { | |
23762 | if (THUMB_IS_FUNC (sym)) | |
23763 | { | |
23764 | /* Mark the symbol as a Thumb function. */ | |
23765 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
23766 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
23767 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 23768 | |
c19d1205 ZW |
23769 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
23770 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
23771 | else | |
23772 | as_bad (_("%s: unexpected function type: %d"), | |
23773 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
23774 | } | |
23775 | else switch (S_GET_STORAGE_CLASS (sym)) | |
23776 | { | |
23777 | case C_EXT: | |
23778 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
23779 | break; | |
23780 | case C_STAT: | |
23781 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
23782 | break; | |
23783 | case C_LABEL: | |
23784 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
23785 | break; | |
23786 | default: | |
23787 | /* Do nothing. */ | |
23788 | break; | |
23789 | } | |
23790 | } | |
a737bd4d | 23791 | |
c19d1205 ZW |
23792 | if (ARM_IS_INTERWORK (sym)) |
23793 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 23794 | } |
c19d1205 ZW |
23795 | #endif |
23796 | #ifdef OBJ_ELF | |
23797 | symbolS * sym; | |
23798 | char bind; | |
404ff6b5 | 23799 | |
c19d1205 | 23800 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 23801 | { |
c19d1205 ZW |
23802 | if (ARM_IS_THUMB (sym)) |
23803 | { | |
23804 | elf_symbol_type * elf_sym; | |
404ff6b5 | 23805 | |
c19d1205 ZW |
23806 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
23807 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 23808 | |
b0796911 PB |
23809 | if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, |
23810 | BFD_ARM_SPECIAL_SYM_TYPE_ANY)) | |
c19d1205 ZW |
23811 | { |
23812 | /* If it's a .thumb_func, declare it as so, | |
23813 | otherwise tag label as .code 16. */ | |
23814 | if (THUMB_IS_FUNC (sym)) | |
35fc36a8 RS |
23815 | elf_sym->internal_elf_sym.st_target_internal |
23816 | = ST_BRANCH_TO_THUMB; | |
3ba67470 | 23817 | else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
c19d1205 ZW |
23818 | elf_sym->internal_elf_sym.st_info = |
23819 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
23820 | } | |
23821 | } | |
23822 | } | |
cd000bff DJ |
23823 | |
23824 | /* Remove any overlapping mapping symbols generated by alignment frags. */ | |
23825 | bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); | |
709001e9 MM |
23826 | /* Now do generic ELF adjustments. */ |
23827 | elf_adjust_symtab (); | |
c19d1205 | 23828 | #endif |
404ff6b5 AH |
23829 | } |
23830 | ||
c19d1205 | 23831 | /* MD interface: Initialization. */ |
404ff6b5 | 23832 | |
a737bd4d | 23833 | static void |
c19d1205 | 23834 | set_constant_flonums (void) |
a737bd4d | 23835 | { |
c19d1205 | 23836 | int i; |
404ff6b5 | 23837 | |
c19d1205 ZW |
23838 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
23839 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
23840 | abort (); | |
a737bd4d | 23841 | } |
404ff6b5 | 23842 | |
3e9e4fcf JB |
23843 | /* Auto-select Thumb mode if it's the only available instruction set for the |
23844 | given architecture. */ | |
23845 | ||
23846 | static void | |
23847 | autoselect_thumb_from_cpu_variant (void) | |
23848 | { | |
23849 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) | |
23850 | opcode_select (16); | |
23851 | } | |
23852 | ||
c19d1205 ZW |
23853 | void |
23854 | md_begin (void) | |
a737bd4d | 23855 | { |
c19d1205 ZW |
23856 | unsigned mach; |
23857 | unsigned int i; | |
404ff6b5 | 23858 | |
c19d1205 ZW |
23859 | if ( (arm_ops_hsh = hash_new ()) == NULL |
23860 | || (arm_cond_hsh = hash_new ()) == NULL | |
23861 | || (arm_shift_hsh = hash_new ()) == NULL | |
23862 | || (arm_psr_hsh = hash_new ()) == NULL | |
62b3e311 | 23863 | || (arm_v7m_psr_hsh = hash_new ()) == NULL |
c19d1205 | 23864 | || (arm_reg_hsh = hash_new ()) == NULL |
62b3e311 PB |
23865 | || (arm_reloc_hsh = hash_new ()) == NULL |
23866 | || (arm_barrier_opt_hsh = hash_new ()) == NULL) | |
c19d1205 ZW |
23867 | as_fatal (_("virtual memory exhausted")); |
23868 | ||
23869 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
d3ce72d0 | 23870 | hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i)); |
c19d1205 | 23871 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) |
d3ce72d0 | 23872 | hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i)); |
c19d1205 | 23873 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) |
5a49b8ac | 23874 | hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i)); |
c19d1205 | 23875 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 23876 | hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i)); |
62b3e311 | 23877 | for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 23878 | hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name, |
477330fc | 23879 | (void *) (v7m_psrs + i)); |
c19d1205 | 23880 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) |
5a49b8ac | 23881 | hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); |
62b3e311 PB |
23882 | for (i = 0; |
23883 | i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); | |
23884 | i++) | |
d3ce72d0 | 23885 | hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name, |
5a49b8ac | 23886 | (void *) (barrier_opt_names + i)); |
c19d1205 | 23887 | #ifdef OBJ_ELF |
3da1d841 NC |
23888 | for (i = 0; i < ARRAY_SIZE (reloc_names); i++) |
23889 | { | |
23890 | struct reloc_entry * entry = reloc_names + i; | |
23891 | ||
23892 | if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32) | |
23893 | /* This makes encode_branch() use the EABI versions of this relocation. */ | |
23894 | entry->reloc = BFD_RELOC_UNUSED; | |
23895 | ||
23896 | hash_insert (arm_reloc_hsh, entry->name, (void *) entry); | |
23897 | } | |
c19d1205 ZW |
23898 | #endif |
23899 | ||
23900 | set_constant_flonums (); | |
404ff6b5 | 23901 | |
c19d1205 ZW |
23902 | /* Set the cpu variant based on the command-line options. We prefer |
23903 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
23904 | -mfpu= over any other way of setting the floating point unit. | |
23905 | Use of legacy options with new options are faulted. */ | |
e74cfd16 | 23906 | if (legacy_cpu) |
404ff6b5 | 23907 | { |
e74cfd16 | 23908 | if (mcpu_cpu_opt || march_cpu_opt) |
c19d1205 ZW |
23909 | as_bad (_("use of old and new-style options to set CPU type")); |
23910 | ||
23911 | mcpu_cpu_opt = legacy_cpu; | |
404ff6b5 | 23912 | } |
e74cfd16 | 23913 | else if (!mcpu_cpu_opt) |
c19d1205 | 23914 | mcpu_cpu_opt = march_cpu_opt; |
404ff6b5 | 23915 | |
e74cfd16 | 23916 | if (legacy_fpu) |
c19d1205 | 23917 | { |
e74cfd16 | 23918 | if (mfpu_opt) |
c19d1205 | 23919 | as_bad (_("use of old and new-style options to set FPU type")); |
03b1477f RE |
23920 | |
23921 | mfpu_opt = legacy_fpu; | |
23922 | } | |
e74cfd16 | 23923 | else if (!mfpu_opt) |
03b1477f | 23924 | { |
45eb4c1b NS |
23925 | #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \ |
23926 | || defined (TE_NetBSD) || defined (TE_VXWORKS)) | |
39c2da32 RE |
23927 | /* Some environments specify a default FPU. If they don't, infer it |
23928 | from the processor. */ | |
e74cfd16 | 23929 | if (mcpu_fpu_opt) |
03b1477f RE |
23930 | mfpu_opt = mcpu_fpu_opt; |
23931 | else | |
23932 | mfpu_opt = march_fpu_opt; | |
39c2da32 | 23933 | #else |
e74cfd16 | 23934 | mfpu_opt = &fpu_default; |
39c2da32 | 23935 | #endif |
03b1477f RE |
23936 | } |
23937 | ||
e74cfd16 | 23938 | if (!mfpu_opt) |
03b1477f | 23939 | { |
493cb6ef | 23940 | if (mcpu_cpu_opt != NULL) |
e74cfd16 | 23941 | mfpu_opt = &fpu_default; |
493cb6ef | 23942 | else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) |
e74cfd16 | 23943 | mfpu_opt = &fpu_arch_vfp_v2; |
03b1477f | 23944 | else |
e74cfd16 | 23945 | mfpu_opt = &fpu_arch_fpa; |
03b1477f RE |
23946 | } |
23947 | ||
ee065d83 | 23948 | #ifdef CPU_DEFAULT |
e74cfd16 | 23949 | if (!mcpu_cpu_opt) |
ee065d83 | 23950 | { |
e74cfd16 PB |
23951 | mcpu_cpu_opt = &cpu_default; |
23952 | selected_cpu = cpu_default; | |
ee065d83 | 23953 | } |
73f43896 NC |
23954 | else if (no_cpu_selected ()) |
23955 | selected_cpu = cpu_default; | |
e74cfd16 PB |
23956 | #else |
23957 | if (mcpu_cpu_opt) | |
23958 | selected_cpu = *mcpu_cpu_opt; | |
ee065d83 | 23959 | else |
e74cfd16 | 23960 | mcpu_cpu_opt = &arm_arch_any; |
ee065d83 | 23961 | #endif |
03b1477f | 23962 | |
e74cfd16 | 23963 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
03b1477f | 23964 | |
3e9e4fcf JB |
23965 | autoselect_thumb_from_cpu_variant (); |
23966 | ||
e74cfd16 | 23967 | arm_arch_used = thumb_arch_used = arm_arch_none; |
ee065d83 | 23968 | |
f17c130b | 23969 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 23970 | { |
7cc69913 NC |
23971 | unsigned int flags = 0; |
23972 | ||
23973 | #if defined OBJ_ELF | |
23974 | flags = meabi_flags; | |
d507cf36 PB |
23975 | |
23976 | switch (meabi_flags) | |
33a392fb | 23977 | { |
d507cf36 | 23978 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 23979 | #endif |
d507cf36 PB |
23980 | /* Set the flags in the private structure. */ |
23981 | if (uses_apcs_26) flags |= F_APCS26; | |
23982 | if (support_interwork) flags |= F_INTERWORK; | |
23983 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 23984 | if (pic_code) flags |= F_PIC; |
e74cfd16 | 23985 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
7cc69913 NC |
23986 | flags |= F_SOFT_FLOAT; |
23987 | ||
d507cf36 PB |
23988 | switch (mfloat_abi_opt) |
23989 | { | |
23990 | case ARM_FLOAT_ABI_SOFT: | |
23991 | case ARM_FLOAT_ABI_SOFTFP: | |
23992 | flags |= F_SOFT_FLOAT; | |
23993 | break; | |
33a392fb | 23994 | |
d507cf36 PB |
23995 | case ARM_FLOAT_ABI_HARD: |
23996 | if (flags & F_SOFT_FLOAT) | |
23997 | as_bad (_("hard-float conflicts with specified fpu")); | |
23998 | break; | |
23999 | } | |
03b1477f | 24000 | |
e74cfd16 PB |
24001 | /* Using pure-endian doubles (even if soft-float). */ |
24002 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
7cc69913 | 24003 | flags |= F_VFP_FLOAT; |
f17c130b | 24004 | |
fde78edd | 24005 | #if defined OBJ_ELF |
e74cfd16 | 24006 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
d507cf36 | 24007 | flags |= EF_ARM_MAVERICK_FLOAT; |
d507cf36 PB |
24008 | break; |
24009 | ||
8cb51566 | 24010 | case EF_ARM_EABI_VER4: |
3a4a14e9 | 24011 | case EF_ARM_EABI_VER5: |
c19d1205 | 24012 | /* No additional flags to set. */ |
d507cf36 PB |
24013 | break; |
24014 | ||
24015 | default: | |
24016 | abort (); | |
24017 | } | |
7cc69913 | 24018 | #endif |
b99bd4ef NC |
24019 | bfd_set_private_flags (stdoutput, flags); |
24020 | ||
24021 | /* We have run out flags in the COFF header to encode the | |
24022 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 24023 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
24024 | if (atpcs) |
24025 | { | |
24026 | asection * sec; | |
24027 | ||
24028 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
24029 | ||
24030 | if (sec != NULL) | |
24031 | { | |
24032 | bfd_set_section_flags | |
24033 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
24034 | bfd_set_section_size (stdoutput, sec, 0); | |
24035 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
24036 | } | |
24037 | } | |
7cc69913 | 24038 | } |
f17c130b | 24039 | #endif |
b99bd4ef NC |
24040 | |
24041 | /* Record the CPU type as well. */ | |
2d447fca JM |
24042 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) |
24043 | mach = bfd_mach_arm_iWMMXt2; | |
24044 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) | |
e16bb312 | 24045 | mach = bfd_mach_arm_iWMMXt; |
e74cfd16 | 24046 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
b99bd4ef | 24047 | mach = bfd_mach_arm_XScale; |
e74cfd16 | 24048 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
fde78edd | 24049 | mach = bfd_mach_arm_ep9312; |
e74cfd16 | 24050 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
b99bd4ef | 24051 | mach = bfd_mach_arm_5TE; |
e74cfd16 | 24052 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
b99bd4ef | 24053 | { |
e74cfd16 | 24054 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
24055 | mach = bfd_mach_arm_5T; |
24056 | else | |
24057 | mach = bfd_mach_arm_5; | |
24058 | } | |
e74cfd16 | 24059 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
b99bd4ef | 24060 | { |
e74cfd16 | 24061 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
24062 | mach = bfd_mach_arm_4T; |
24063 | else | |
24064 | mach = bfd_mach_arm_4; | |
24065 | } | |
e74cfd16 | 24066 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
b99bd4ef | 24067 | mach = bfd_mach_arm_3M; |
e74cfd16 PB |
24068 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
24069 | mach = bfd_mach_arm_3; | |
24070 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) | |
24071 | mach = bfd_mach_arm_2a; | |
24072 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) | |
24073 | mach = bfd_mach_arm_2; | |
24074 | else | |
24075 | mach = bfd_mach_arm_unknown; | |
b99bd4ef NC |
24076 | |
24077 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
24078 | } | |
24079 | ||
c19d1205 | 24080 | /* Command line processing. */ |
b99bd4ef | 24081 | |
c19d1205 ZW |
24082 | /* md_parse_option |
24083 | Invocation line includes a switch not recognized by the base assembler. | |
24084 | See if it's a processor-specific option. | |
b99bd4ef | 24085 | |
c19d1205 ZW |
24086 | This routine is somewhat complicated by the need for backwards |
24087 | compatibility (since older releases of gcc can't be changed). | |
24088 | The new options try to make the interface as compatible as | |
24089 | possible with GCC. | |
b99bd4ef | 24090 | |
c19d1205 | 24091 | New options (supported) are: |
b99bd4ef | 24092 | |
c19d1205 ZW |
24093 | -mcpu=<cpu name> Assemble for selected processor |
24094 | -march=<architecture name> Assemble for selected architecture | |
24095 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
24096 | -EB/-mbig-endian Big-endian | |
24097 | -EL/-mlittle-endian Little-endian | |
24098 | -k Generate PIC code | |
24099 | -mthumb Start in Thumb mode | |
24100 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 24101 | |
278df34e | 24102 | -m[no-]warn-deprecated Warn about deprecated features |
267bf995 | 24103 | |
c19d1205 | 24104 | For now we will also provide support for: |
b99bd4ef | 24105 | |
c19d1205 ZW |
24106 | -mapcs-32 32-bit Program counter |
24107 | -mapcs-26 26-bit Program counter | |
24108 | -macps-float Floats passed in FP registers | |
24109 | -mapcs-reentrant Reentrant code | |
24110 | -matpcs | |
24111 | (sometime these will probably be replaced with -mapcs=<list of options> | |
24112 | and -matpcs=<list of options>) | |
b99bd4ef | 24113 | |
c19d1205 ZW |
24114 | The remaining options are only supported for back-wards compatibility. |
24115 | Cpu variants, the arm part is optional: | |
24116 | -m[arm]1 Currently not supported. | |
24117 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
24118 | -m[arm]3 Arm 3 processor | |
24119 | -m[arm]6[xx], Arm 6 processors | |
24120 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
24121 | -m[arm]8[10] Arm 8 processors | |
24122 | -m[arm]9[20][tdmi] Arm 9 processors | |
24123 | -mstrongarm[110[0]] StrongARM processors | |
24124 | -mxscale XScale processors | |
24125 | -m[arm]v[2345[t[e]]] Arm architectures | |
24126 | -mall All (except the ARM1) | |
24127 | FP variants: | |
24128 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
24129 | -mfpe-old (No float load/store multiples) | |
24130 | -mvfpxd VFP Single precision | |
24131 | -mvfp All VFP | |
24132 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 24133 | |
c19d1205 ZW |
24134 | The following CPU names are recognized: |
24135 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
24136 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
24137 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
24138 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
24139 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
24140 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
24141 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 24142 | |
c19d1205 | 24143 | */ |
b99bd4ef | 24144 | |
c19d1205 | 24145 | const char * md_shortopts = "m:k"; |
b99bd4ef | 24146 | |
c19d1205 ZW |
24147 | #ifdef ARM_BI_ENDIAN |
24148 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
24149 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 24150 | #else |
c19d1205 ZW |
24151 | #if TARGET_BYTES_BIG_ENDIAN |
24152 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 24153 | #else |
c19d1205 ZW |
24154 | #define OPTION_EL (OPTION_MD_BASE + 1) |
24155 | #endif | |
b99bd4ef | 24156 | #endif |
845b51d6 | 24157 | #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2) |
b99bd4ef | 24158 | |
c19d1205 | 24159 | struct option md_longopts[] = |
b99bd4ef | 24160 | { |
c19d1205 ZW |
24161 | #ifdef OPTION_EB |
24162 | {"EB", no_argument, NULL, OPTION_EB}, | |
24163 | #endif | |
24164 | #ifdef OPTION_EL | |
24165 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 24166 | #endif |
845b51d6 | 24167 | {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, |
c19d1205 ZW |
24168 | {NULL, no_argument, NULL, 0} |
24169 | }; | |
b99bd4ef | 24170 | |
c19d1205 | 24171 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 24172 | |
c19d1205 | 24173 | struct arm_option_table |
b99bd4ef | 24174 | { |
c19d1205 ZW |
24175 | char *option; /* Option name to match. */ |
24176 | char *help; /* Help information. */ | |
24177 | int *var; /* Variable to change. */ | |
24178 | int value; /* What to change it to. */ | |
24179 | char *deprecated; /* If non-null, print this message. */ | |
24180 | }; | |
b99bd4ef | 24181 | |
c19d1205 ZW |
24182 | struct arm_option_table arm_opts[] = |
24183 | { | |
24184 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
24185 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
24186 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
24187 | &support_interwork, 1, NULL}, | |
24188 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
24189 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
24190 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
24191 | 1, NULL}, | |
24192 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
24193 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
24194 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
24195 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
24196 | NULL}, | |
b99bd4ef | 24197 | |
c19d1205 ZW |
24198 | /* These are recognized by the assembler, but have no affect on code. */ |
24199 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
24200 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
278df34e NS |
24201 | |
24202 | {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL}, | |
24203 | {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"), | |
24204 | &warn_on_deprecated, 0, NULL}, | |
e74cfd16 PB |
24205 | {NULL, NULL, NULL, 0, NULL} |
24206 | }; | |
24207 | ||
24208 | struct arm_legacy_option_table | |
24209 | { | |
24210 | char *option; /* Option name to match. */ | |
24211 | const arm_feature_set **var; /* Variable to change. */ | |
24212 | const arm_feature_set value; /* What to change it to. */ | |
24213 | char *deprecated; /* If non-null, print this message. */ | |
24214 | }; | |
b99bd4ef | 24215 | |
e74cfd16 PB |
24216 | const struct arm_legacy_option_table arm_legacy_opts[] = |
24217 | { | |
c19d1205 ZW |
24218 | /* DON'T add any new processors to this list -- we want the whole list |
24219 | to go away... Add them to the processors table instead. */ | |
e74cfd16 PB |
24220 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
24221 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
24222 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
24223 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
24224 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
24225 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
24226 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
24227 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
24228 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
24229 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
24230 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
24231 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
24232 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
24233 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
24234 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
24235 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
24236 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
24237 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
24238 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
24239 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
24240 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
24241 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
24242 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
24243 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
24244 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
24245 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
24246 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
24247 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
24248 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
24249 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
24250 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
24251 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
24252 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
24253 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
24254 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
24255 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
24256 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
24257 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
24258 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
24259 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
24260 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
24261 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
24262 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
24263 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
24264 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
24265 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
24266 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
24267 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
24268 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
24269 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
24270 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
24271 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
24272 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
24273 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
24274 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
24275 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
24276 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
24277 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
24278 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
24279 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
24280 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
24281 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
24282 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
24283 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
24284 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
24285 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
24286 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
24287 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
24288 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
24289 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, | |
c19d1205 | 24290 | N_("use -mcpu=strongarm110")}, |
e74cfd16 | 24291 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 24292 | N_("use -mcpu=strongarm1100")}, |
e74cfd16 | 24293 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 24294 | N_("use -mcpu=strongarm1110")}, |
e74cfd16 PB |
24295 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
24296 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
24297 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 24298 | |
c19d1205 | 24299 | /* Architecture variants -- don't add any more to this list either. */ |
e74cfd16 PB |
24300 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
24301 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
24302 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
24303 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
24304 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
24305 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
24306 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
24307 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
24308 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
24309 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
24310 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
24311 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
24312 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
24313 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
24314 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
24315 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
24316 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
24317 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 24318 | |
c19d1205 | 24319 | /* Floating point variants -- don't add any more to this list either. */ |
e74cfd16 PB |
24320 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
24321 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
24322 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
24323 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, | |
c19d1205 | 24324 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
7ed4c4c5 | 24325 | |
e74cfd16 | 24326 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
c19d1205 | 24327 | }; |
7ed4c4c5 | 24328 | |
c19d1205 | 24329 | struct arm_cpu_option_table |
7ed4c4c5 | 24330 | { |
c19d1205 | 24331 | char *name; |
f3bad469 | 24332 | size_t name_len; |
e74cfd16 | 24333 | const arm_feature_set value; |
c19d1205 ZW |
24334 | /* For some CPUs we assume an FPU unless the user explicitly sets |
24335 | -mfpu=... */ | |
e74cfd16 | 24336 | const arm_feature_set default_fpu; |
ee065d83 PB |
24337 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
24338 | case. */ | |
24339 | const char *canonical_name; | |
c19d1205 | 24340 | }; |
7ed4c4c5 | 24341 | |
c19d1205 ZW |
24342 | /* This list should, at a minimum, contain all the cpu names |
24343 | recognized by GCC. */ | |
f3bad469 | 24344 | #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN } |
e74cfd16 | 24345 | static const struct arm_cpu_option_table arm_cpus[] = |
c19d1205 | 24346 | { |
f3bad469 MGD |
24347 | ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL), |
24348 | ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL), | |
24349 | ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL), | |
24350 | ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL), | |
24351 | ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL), | |
24352 | ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24353 | ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24354 | ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24355 | ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24356 | ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24357 | ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24358 | ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
24359 | ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24360 | ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
24361 | ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24362 | ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
24363 | ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24364 | ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24365 | ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24366 | ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24367 | ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24368 | ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24369 | ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24370 | ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24371 | ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24372 | ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24373 | ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24374 | ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24375 | ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24376 | ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24377 | ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24378 | ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24379 | ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24380 | ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24381 | ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24382 | ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24383 | ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24384 | ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24385 | ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24386 | ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"), | |
24387 | ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24388 | ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24389 | ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24390 | ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24391 | ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24392 | ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
c19d1205 ZW |
24393 | /* For V5 or later processors we default to using VFP; but the user |
24394 | should really set the FPU type explicitly. */ | |
f3bad469 MGD |
24395 | ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), |
24396 | ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24397 | ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"), | |
24398 | ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"), | |
24399 | ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL), | |
24400 | ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), | |
24401 | ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"), | |
24402 | ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24403 | ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), | |
24404 | ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"), | |
24405 | ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24406 | ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24407 | ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
24408 | ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
24409 | ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24410 | ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"), | |
24411 | ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
24412 | ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24413 | ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24414 | ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, | |
24415 | "ARM1026EJ-S"), | |
24416 | ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL), | |
24417 | ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24418 | ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24419 | ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24420 | ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24421 | ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24422 | ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"), | |
24423 | ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL), | |
24424 | ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, | |
24425 | "ARM1136JF-S"), | |
24426 | ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL), | |
24427 | ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"), | |
24428 | ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"), | |
24429 | ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL), | |
24430 | ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL), | |
24431 | ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL), | |
24432 | ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL), | |
24433 | ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC, | |
24434 | FPU_NONE, "Cortex-A5"), | |
c9fb6e58 | 24435 | ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, |
f3bad469 MGD |
24436 | "Cortex-A7"), |
24437 | ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC, | |
24438 | ARM_FEATURE (0, FPU_VFP_V3 | |
477330fc | 24439 | | FPU_NEON_EXT_V1), |
f3bad469 MGD |
24440 | "Cortex-A8"), |
24441 | ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC, | |
24442 | ARM_FEATURE (0, FPU_VFP_V3 | |
477330fc | 24443 | | FPU_NEON_EXT_V1), |
f3bad469 | 24444 | "Cortex-A9"), |
c9fb6e58 | 24445 | ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, |
63a4bc21 | 24446 | "Cortex-A12"), |
c9fb6e58 | 24447 | ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, |
f3bad469 | 24448 | "Cortex-A15"), |
d7adf960 KT |
24449 | ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, |
24450 | "Cortex-A17"), | |
92eb40d9 | 24451 | ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
477330fc | 24452 | "Cortex-A53"), |
92eb40d9 | 24453 | ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
477330fc | 24454 | "Cortex-A57"), |
b19f47ad JW |
24455 | ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
24456 | "Cortex-A72"), | |
f3bad469 MGD |
24457 | ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"), |
24458 | ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16, | |
24459 | "Cortex-R4F"), | |
24460 | ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV, | |
24461 | FPU_NONE, "Cortex-R5"), | |
70a8bc5b | 24462 | ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV, |
24463 | FPU_ARCH_VFP_V3D16, | |
24464 | "Cortex-R7"), | |
a715796b | 24465 | ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M7"), |
f3bad469 MGD |
24466 | ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"), |
24467 | ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"), | |
24468 | ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"), | |
24469 | ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"), | |
ce32bd10 | 24470 | ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"), |
c19d1205 | 24471 | /* ??? XSCALE is really an architecture. */ |
f3bad469 | 24472 | ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL), |
c19d1205 | 24473 | /* ??? iwmmxt is not a processor. */ |
f3bad469 MGD |
24474 | ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL), |
24475 | ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL), | |
24476 | ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL), | |
c19d1205 | 24477 | /* Maverick */ |
f3bad469 | 24478 | ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), |
da4339ed NC |
24479 | FPU_ARCH_MAVERICK, "ARM920T"), |
24480 | /* Marvell processors. */ | |
4a81b02a | 24481 | ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, 0), |
477330fc | 24482 | FPU_ARCH_VFP_V3D16, NULL), |
4347085a NC |
24483 | ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP |
24484 | | ARM_EXT_SEC, 0), | |
24485 | FPU_ARCH_NEON_VFP_V4, NULL), | |
ea0d6bb9 PT |
24486 | /* APM X-Gene family. */ |
24487 | ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, | |
24488 | "APM X-Gene 1"), | |
24489 | ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, | |
24490 | "APM X-Gene 2"), | |
da4339ed | 24491 | |
f3bad469 | 24492 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL } |
c19d1205 | 24493 | }; |
f3bad469 | 24494 | #undef ARM_CPU_OPT |
7ed4c4c5 | 24495 | |
c19d1205 | 24496 | struct arm_arch_option_table |
7ed4c4c5 | 24497 | { |
c19d1205 | 24498 | char *name; |
f3bad469 | 24499 | size_t name_len; |
e74cfd16 PB |
24500 | const arm_feature_set value; |
24501 | const arm_feature_set default_fpu; | |
c19d1205 | 24502 | }; |
7ed4c4c5 | 24503 | |
c19d1205 ZW |
24504 | /* This list should, at a minimum, contain all the architecture names |
24505 | recognized by GCC. */ | |
f3bad469 | 24506 | #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF } |
e74cfd16 | 24507 | static const struct arm_arch_option_table arm_archs[] = |
c19d1205 | 24508 | { |
f3bad469 MGD |
24509 | ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA), |
24510 | ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA), | |
24511 | ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA), | |
24512 | ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
24513 | ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
24514 | ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA), | |
24515 | ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA), | |
24516 | ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA), | |
24517 | ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA), | |
24518 | ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA), | |
24519 | ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA), | |
24520 | ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP), | |
24521 | ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP), | |
24522 | ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP), | |
24523 | ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP), | |
24524 | ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP), | |
24525 | ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP), | |
24526 | ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP), | |
24527 | ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP), | |
24528 | ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP), | |
24529 | ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP), | |
24530 | ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP), | |
24531 | ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP), | |
24532 | ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP), | |
24533 | ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP), | |
24534 | ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP), | |
24535 | ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP), | |
24536 | ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP), | |
24537 | ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP), | |
c450d570 PB |
24538 | /* The official spelling of the ARMv7 profile variants is the dashed form. |
24539 | Accept the non-dashed form for compatibility with old toolchains. */ | |
f3bad469 | 24540 | ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP), |
c9fb6e58 | 24541 | ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP), |
f3bad469 MGD |
24542 | ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP), |
24543 | ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP), | |
24544 | ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP), | |
24545 | ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP), | |
24546 | ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP), | |
24547 | ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP), | |
bca38921 | 24548 | ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP), |
f3bad469 MGD |
24549 | ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP), |
24550 | ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP), | |
24551 | ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP), | |
24552 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
c19d1205 | 24553 | }; |
f3bad469 | 24554 | #undef ARM_ARCH_OPT |
7ed4c4c5 | 24555 | |
69133863 MGD |
24556 | /* ISA extensions in the co-processor and main instruction set space. */ |
24557 | struct arm_option_extension_value_table | |
c19d1205 ZW |
24558 | { |
24559 | char *name; | |
f3bad469 | 24560 | size_t name_len; |
5a70a223 JB |
24561 | const arm_feature_set merge_value; |
24562 | const arm_feature_set clear_value; | |
69133863 | 24563 | const arm_feature_set allowed_archs; |
c19d1205 | 24564 | }; |
7ed4c4c5 | 24565 | |
69133863 MGD |
24566 | /* The following table must be in alphabetical order with a NULL last entry. |
24567 | */ | |
5a70a223 | 24568 | #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA } |
69133863 | 24569 | static const struct arm_option_extension_value_table arm_extensions[] = |
c19d1205 | 24570 | { |
5a70a223 JB |
24571 | ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE (0, CRC_EXT_ARMV8), |
24572 | ARM_FEATURE (ARM_EXT_V8, 0)), | |
bca38921 | 24573 | ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
5a70a223 | 24574 | ARM_FEATURE (0, FPU_CRYPTO_ARMV8), |
bca38921 | 24575 | ARM_FEATURE (ARM_EXT_V8, 0)), |
5a70a223 | 24576 | ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE (0, FPU_VFP_ARMV8), |
bca38921 | 24577 | ARM_FEATURE (ARM_EXT_V8, 0)), |
f3bad469 | 24578 | ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0), |
5a70a223 | 24579 | ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0), |
f3bad469 | 24580 | ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)), |
5a70a223 JB |
24581 | ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), |
24582 | ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY), | |
24583 | ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2), | |
24584 | ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY), | |
24585 | ARM_EXT_OPT ("maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK), | |
24586 | ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY), | |
f3bad469 | 24587 | ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0), |
5a70a223 | 24588 | ARM_FEATURE (ARM_EXT_MP, 0), |
f3bad469 | 24589 | ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)), |
bca38921 | 24590 | ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8, |
5a70a223 | 24591 | ARM_FEATURE(0, FPU_NEON_ARMV8), |
bca38921 | 24592 | ARM_FEATURE (ARM_EXT_V8, 0)), |
f3bad469 | 24593 | ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0), |
5a70a223 | 24594 | ARM_FEATURE (ARM_EXT_OS, 0), |
f3bad469 MGD |
24595 | ARM_FEATURE (ARM_EXT_V6M, 0)), |
24596 | ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0), | |
5a70a223 | 24597 | ARM_FEATURE (ARM_EXT_SEC, 0), |
f3bad469 MGD |
24598 | ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)), |
24599 | ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV | |
24600 | | ARM_EXT_DIV, 0), | |
5a70a223 | 24601 | ARM_FEATURE (ARM_EXT_VIRT, 0), |
f3bad469 | 24602 | ARM_FEATURE (ARM_EXT_V7A, 0)), |
5a70a223 JB |
24603 | ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), |
24604 | ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY), | |
24605 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
69133863 | 24606 | }; |
f3bad469 | 24607 | #undef ARM_EXT_OPT |
69133863 MGD |
24608 | |
24609 | /* ISA floating-point and Advanced SIMD extensions. */ | |
24610 | struct arm_option_fpu_value_table | |
24611 | { | |
24612 | char *name; | |
24613 | const arm_feature_set value; | |
c19d1205 | 24614 | }; |
7ed4c4c5 | 24615 | |
c19d1205 ZW |
24616 | /* This list should, at a minimum, contain all the fpu names |
24617 | recognized by GCC. */ | |
69133863 | 24618 | static const struct arm_option_fpu_value_table arm_fpus[] = |
c19d1205 ZW |
24619 | { |
24620 | {"softfpa", FPU_NONE}, | |
24621 | {"fpe", FPU_ARCH_FPE}, | |
24622 | {"fpe2", FPU_ARCH_FPE}, | |
24623 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
24624 | {"fpa", FPU_ARCH_FPA}, | |
24625 | {"fpa10", FPU_ARCH_FPA}, | |
24626 | {"fpa11", FPU_ARCH_FPA}, | |
24627 | {"arm7500fe", FPU_ARCH_FPA}, | |
24628 | {"softvfp", FPU_ARCH_VFP}, | |
24629 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
24630 | {"vfp", FPU_ARCH_VFP_V2}, | |
24631 | {"vfp9", FPU_ARCH_VFP_V2}, | |
b1cc4aeb | 24632 | {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */ |
c19d1205 ZW |
24633 | {"vfp10", FPU_ARCH_VFP_V2}, |
24634 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
24635 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
b1cc4aeb PB |
24636 | {"vfpv2", FPU_ARCH_VFP_V2}, |
24637 | {"vfpv3", FPU_ARCH_VFP_V3}, | |
62f3b8c8 | 24638 | {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16}, |
b1cc4aeb | 24639 | {"vfpv3-d16", FPU_ARCH_VFP_V3D16}, |
62f3b8c8 PB |
24640 | {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16}, |
24641 | {"vfpv3xd", FPU_ARCH_VFP_V3xD}, | |
24642 | {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16}, | |
c19d1205 ZW |
24643 | {"arm1020t", FPU_ARCH_VFP_V1}, |
24644 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
24645 | {"arm1136jfs", FPU_ARCH_VFP_V2}, | |
24646 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, | |
24647 | {"maverick", FPU_ARCH_MAVERICK}, | |
5287ad62 | 24648 | {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
8e79c3df | 24649 | {"neon-fp16", FPU_ARCH_NEON_FP16}, |
62f3b8c8 PB |
24650 | {"vfpv4", FPU_ARCH_VFP_V4}, |
24651 | {"vfpv4-d16", FPU_ARCH_VFP_V4D16}, | |
ada65aa3 | 24652 | {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16}, |
a715796b TG |
24653 | {"fpv5-d16", FPU_ARCH_VFP_V5D16}, |
24654 | {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16}, | |
62f3b8c8 | 24655 | {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4}, |
bca38921 MGD |
24656 | {"fp-armv8", FPU_ARCH_VFP_ARMV8}, |
24657 | {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8}, | |
24658 | {"crypto-neon-fp-armv8", | |
24659 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8}, | |
e74cfd16 PB |
24660 | {NULL, ARM_ARCH_NONE} |
24661 | }; | |
24662 | ||
24663 | struct arm_option_value_table | |
24664 | { | |
24665 | char *name; | |
24666 | long value; | |
c19d1205 | 24667 | }; |
7ed4c4c5 | 24668 | |
e74cfd16 | 24669 | static const struct arm_option_value_table arm_float_abis[] = |
c19d1205 ZW |
24670 | { |
24671 | {"hard", ARM_FLOAT_ABI_HARD}, | |
24672 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
24673 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
e74cfd16 | 24674 | {NULL, 0} |
c19d1205 | 24675 | }; |
7ed4c4c5 | 24676 | |
c19d1205 | 24677 | #ifdef OBJ_ELF |
3a4a14e9 | 24678 | /* We only know how to output GNU and ver 4/5 (AAELF) formats. */ |
e74cfd16 | 24679 | static const struct arm_option_value_table arm_eabis[] = |
c19d1205 ZW |
24680 | { |
24681 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
24682 | {"4", EF_ARM_EABI_VER4}, | |
3a4a14e9 | 24683 | {"5", EF_ARM_EABI_VER5}, |
e74cfd16 | 24684 | {NULL, 0} |
c19d1205 ZW |
24685 | }; |
24686 | #endif | |
7ed4c4c5 | 24687 | |
c19d1205 ZW |
24688 | struct arm_long_option_table |
24689 | { | |
24690 | char * option; /* Substring to match. */ | |
24691 | char * help; /* Help information. */ | |
24692 | int (* func) (char * subopt); /* Function to decode sub-option. */ | |
24693 | char * deprecated; /* If non-null, print this message. */ | |
24694 | }; | |
7ed4c4c5 | 24695 | |
c921be7d | 24696 | static bfd_boolean |
f3bad469 | 24697 | arm_parse_extension (char *str, const arm_feature_set **opt_p) |
7ed4c4c5 | 24698 | { |
21d799b5 NC |
24699 | arm_feature_set *ext_set = (arm_feature_set *) |
24700 | xmalloc (sizeof (arm_feature_set)); | |
e74cfd16 | 24701 | |
69133863 | 24702 | /* We insist on extensions being specified in alphabetical order, and with |
fa94de6b RM |
24703 | extensions being added before being removed. We achieve this by having |
24704 | the global ARM_EXTENSIONS table in alphabetical order, and using the | |
69133863 | 24705 | ADDING_VALUE variable to indicate whether we are adding an extension (1) |
fa94de6b | 24706 | or removing it (0) and only allowing it to change in the order |
69133863 MGD |
24707 | -1 -> 1 -> 0. */ |
24708 | const struct arm_option_extension_value_table * opt = NULL; | |
24709 | int adding_value = -1; | |
24710 | ||
e74cfd16 PB |
24711 | /* Copy the feature set, so that we can modify it. */ |
24712 | *ext_set = **opt_p; | |
24713 | *opt_p = ext_set; | |
24714 | ||
c19d1205 | 24715 | while (str != NULL && *str != 0) |
7ed4c4c5 | 24716 | { |
f3bad469 MGD |
24717 | char *ext; |
24718 | size_t len; | |
7ed4c4c5 | 24719 | |
c19d1205 ZW |
24720 | if (*str != '+') |
24721 | { | |
24722 | as_bad (_("invalid architectural extension")); | |
c921be7d | 24723 | return FALSE; |
c19d1205 | 24724 | } |
7ed4c4c5 | 24725 | |
c19d1205 ZW |
24726 | str++; |
24727 | ext = strchr (str, '+'); | |
7ed4c4c5 | 24728 | |
c19d1205 | 24729 | if (ext != NULL) |
f3bad469 | 24730 | len = ext - str; |
c19d1205 | 24731 | else |
f3bad469 | 24732 | len = strlen (str); |
7ed4c4c5 | 24733 | |
f3bad469 | 24734 | if (len >= 2 && strncmp (str, "no", 2) == 0) |
69133863 MGD |
24735 | { |
24736 | if (adding_value != 0) | |
24737 | { | |
24738 | adding_value = 0; | |
24739 | opt = arm_extensions; | |
24740 | } | |
24741 | ||
f3bad469 | 24742 | len -= 2; |
69133863 MGD |
24743 | str += 2; |
24744 | } | |
f3bad469 | 24745 | else if (len > 0) |
69133863 MGD |
24746 | { |
24747 | if (adding_value == -1) | |
24748 | { | |
24749 | adding_value = 1; | |
24750 | opt = arm_extensions; | |
24751 | } | |
24752 | else if (adding_value != 1) | |
24753 | { | |
24754 | as_bad (_("must specify extensions to add before specifying " | |
24755 | "those to remove")); | |
24756 | return FALSE; | |
24757 | } | |
24758 | } | |
24759 | ||
f3bad469 | 24760 | if (len == 0) |
c19d1205 ZW |
24761 | { |
24762 | as_bad (_("missing architectural extension")); | |
c921be7d | 24763 | return FALSE; |
c19d1205 | 24764 | } |
7ed4c4c5 | 24765 | |
69133863 MGD |
24766 | gas_assert (adding_value != -1); |
24767 | gas_assert (opt != NULL); | |
24768 | ||
24769 | /* Scan over the options table trying to find an exact match. */ | |
24770 | for (; opt->name != NULL; opt++) | |
f3bad469 | 24771 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 24772 | { |
69133863 MGD |
24773 | /* Check we can apply the extension to this architecture. */ |
24774 | if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs)) | |
24775 | { | |
24776 | as_bad (_("extension does not apply to the base architecture")); | |
24777 | return FALSE; | |
24778 | } | |
24779 | ||
24780 | /* Add or remove the extension. */ | |
24781 | if (adding_value) | |
5a70a223 | 24782 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value); |
69133863 | 24783 | else |
5a70a223 | 24784 | ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value); |
69133863 | 24785 | |
c19d1205 ZW |
24786 | break; |
24787 | } | |
7ed4c4c5 | 24788 | |
c19d1205 ZW |
24789 | if (opt->name == NULL) |
24790 | { | |
69133863 MGD |
24791 | /* Did we fail to find an extension because it wasn't specified in |
24792 | alphabetical order, or because it does not exist? */ | |
24793 | ||
24794 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
f3bad469 | 24795 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
69133863 MGD |
24796 | break; |
24797 | ||
24798 | if (opt->name == NULL) | |
24799 | as_bad (_("unknown architectural extension `%s'"), str); | |
24800 | else | |
24801 | as_bad (_("architectural extensions must be specified in " | |
24802 | "alphabetical order")); | |
24803 | ||
c921be7d | 24804 | return FALSE; |
c19d1205 | 24805 | } |
69133863 MGD |
24806 | else |
24807 | { | |
24808 | /* We should skip the extension we've just matched the next time | |
24809 | round. */ | |
24810 | opt++; | |
24811 | } | |
7ed4c4c5 | 24812 | |
c19d1205 ZW |
24813 | str = ext; |
24814 | }; | |
7ed4c4c5 | 24815 | |
c921be7d | 24816 | return TRUE; |
c19d1205 | 24817 | } |
7ed4c4c5 | 24818 | |
c921be7d | 24819 | static bfd_boolean |
f3bad469 | 24820 | arm_parse_cpu (char *str) |
7ed4c4c5 | 24821 | { |
f3bad469 MGD |
24822 | const struct arm_cpu_option_table *opt; |
24823 | char *ext = strchr (str, '+'); | |
24824 | size_t len; | |
7ed4c4c5 | 24825 | |
c19d1205 | 24826 | if (ext != NULL) |
f3bad469 | 24827 | len = ext - str; |
7ed4c4c5 | 24828 | else |
f3bad469 | 24829 | len = strlen (str); |
7ed4c4c5 | 24830 | |
f3bad469 | 24831 | if (len == 0) |
7ed4c4c5 | 24832 | { |
c19d1205 | 24833 | as_bad (_("missing cpu name `%s'"), str); |
c921be7d | 24834 | return FALSE; |
7ed4c4c5 NC |
24835 | } |
24836 | ||
c19d1205 | 24837 | for (opt = arm_cpus; opt->name != NULL; opt++) |
f3bad469 | 24838 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 24839 | { |
e74cfd16 PB |
24840 | mcpu_cpu_opt = &opt->value; |
24841 | mcpu_fpu_opt = &opt->default_fpu; | |
ee065d83 | 24842 | if (opt->canonical_name) |
5f4273c7 | 24843 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
24844 | else |
24845 | { | |
f3bad469 | 24846 | size_t i; |
c921be7d | 24847 | |
f3bad469 | 24848 | for (i = 0; i < len; i++) |
ee065d83 PB |
24849 | selected_cpu_name[i] = TOUPPER (opt->name[i]); |
24850 | selected_cpu_name[i] = 0; | |
24851 | } | |
7ed4c4c5 | 24852 | |
c19d1205 ZW |
24853 | if (ext != NULL) |
24854 | return arm_parse_extension (ext, &mcpu_cpu_opt); | |
7ed4c4c5 | 24855 | |
c921be7d | 24856 | return TRUE; |
c19d1205 | 24857 | } |
7ed4c4c5 | 24858 | |
c19d1205 | 24859 | as_bad (_("unknown cpu `%s'"), str); |
c921be7d | 24860 | return FALSE; |
7ed4c4c5 NC |
24861 | } |
24862 | ||
c921be7d | 24863 | static bfd_boolean |
f3bad469 | 24864 | arm_parse_arch (char *str) |
7ed4c4c5 | 24865 | { |
e74cfd16 | 24866 | const struct arm_arch_option_table *opt; |
c19d1205 | 24867 | char *ext = strchr (str, '+'); |
f3bad469 | 24868 | size_t len; |
7ed4c4c5 | 24869 | |
c19d1205 | 24870 | if (ext != NULL) |
f3bad469 | 24871 | len = ext - str; |
7ed4c4c5 | 24872 | else |
f3bad469 | 24873 | len = strlen (str); |
7ed4c4c5 | 24874 | |
f3bad469 | 24875 | if (len == 0) |
7ed4c4c5 | 24876 | { |
c19d1205 | 24877 | as_bad (_("missing architecture name `%s'"), str); |
c921be7d | 24878 | return FALSE; |
7ed4c4c5 NC |
24879 | } |
24880 | ||
c19d1205 | 24881 | for (opt = arm_archs; opt->name != NULL; opt++) |
f3bad469 | 24882 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 24883 | { |
e74cfd16 PB |
24884 | march_cpu_opt = &opt->value; |
24885 | march_fpu_opt = &opt->default_fpu; | |
5f4273c7 | 24886 | strcpy (selected_cpu_name, opt->name); |
7ed4c4c5 | 24887 | |
c19d1205 ZW |
24888 | if (ext != NULL) |
24889 | return arm_parse_extension (ext, &march_cpu_opt); | |
7ed4c4c5 | 24890 | |
c921be7d | 24891 | return TRUE; |
c19d1205 ZW |
24892 | } |
24893 | ||
24894 | as_bad (_("unknown architecture `%s'\n"), str); | |
c921be7d | 24895 | return FALSE; |
7ed4c4c5 | 24896 | } |
eb043451 | 24897 | |
c921be7d | 24898 | static bfd_boolean |
c19d1205 ZW |
24899 | arm_parse_fpu (char * str) |
24900 | { | |
69133863 | 24901 | const struct arm_option_fpu_value_table * opt; |
b99bd4ef | 24902 | |
c19d1205 ZW |
24903 | for (opt = arm_fpus; opt->name != NULL; opt++) |
24904 | if (streq (opt->name, str)) | |
24905 | { | |
e74cfd16 | 24906 | mfpu_opt = &opt->value; |
c921be7d | 24907 | return TRUE; |
c19d1205 | 24908 | } |
b99bd4ef | 24909 | |
c19d1205 | 24910 | as_bad (_("unknown floating point format `%s'\n"), str); |
c921be7d | 24911 | return FALSE; |
c19d1205 ZW |
24912 | } |
24913 | ||
c921be7d | 24914 | static bfd_boolean |
c19d1205 | 24915 | arm_parse_float_abi (char * str) |
b99bd4ef | 24916 | { |
e74cfd16 | 24917 | const struct arm_option_value_table * opt; |
b99bd4ef | 24918 | |
c19d1205 ZW |
24919 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
24920 | if (streq (opt->name, str)) | |
24921 | { | |
24922 | mfloat_abi_opt = opt->value; | |
c921be7d | 24923 | return TRUE; |
c19d1205 | 24924 | } |
cc8a6dd0 | 24925 | |
c19d1205 | 24926 | as_bad (_("unknown floating point abi `%s'\n"), str); |
c921be7d | 24927 | return FALSE; |
c19d1205 | 24928 | } |
b99bd4ef | 24929 | |
c19d1205 | 24930 | #ifdef OBJ_ELF |
c921be7d | 24931 | static bfd_boolean |
c19d1205 ZW |
24932 | arm_parse_eabi (char * str) |
24933 | { | |
e74cfd16 | 24934 | const struct arm_option_value_table *opt; |
cc8a6dd0 | 24935 | |
c19d1205 ZW |
24936 | for (opt = arm_eabis; opt->name != NULL; opt++) |
24937 | if (streq (opt->name, str)) | |
24938 | { | |
24939 | meabi_flags = opt->value; | |
c921be7d | 24940 | return TRUE; |
c19d1205 ZW |
24941 | } |
24942 | as_bad (_("unknown EABI `%s'\n"), str); | |
c921be7d | 24943 | return FALSE; |
c19d1205 ZW |
24944 | } |
24945 | #endif | |
cc8a6dd0 | 24946 | |
c921be7d | 24947 | static bfd_boolean |
e07e6e58 NC |
24948 | arm_parse_it_mode (char * str) |
24949 | { | |
c921be7d | 24950 | bfd_boolean ret = TRUE; |
e07e6e58 NC |
24951 | |
24952 | if (streq ("arm", str)) | |
24953 | implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
24954 | else if (streq ("thumb", str)) | |
24955 | implicit_it_mode = IMPLICIT_IT_MODE_THUMB; | |
24956 | else if (streq ("always", str)) | |
24957 | implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS; | |
24958 | else if (streq ("never", str)) | |
24959 | implicit_it_mode = IMPLICIT_IT_MODE_NEVER; | |
24960 | else | |
24961 | { | |
24962 | as_bad (_("unknown implicit IT mode `%s', should be "\ | |
477330fc | 24963 | "arm, thumb, always, or never."), str); |
c921be7d | 24964 | ret = FALSE; |
e07e6e58 NC |
24965 | } |
24966 | ||
24967 | return ret; | |
24968 | } | |
24969 | ||
2e6976a8 DG |
24970 | static bfd_boolean |
24971 | arm_ccs_mode (char * unused ATTRIBUTE_UNUSED) | |
24972 | { | |
24973 | codecomposer_syntax = TRUE; | |
24974 | arm_comment_chars[0] = ';'; | |
24975 | arm_line_separator_chars[0] = 0; | |
24976 | return TRUE; | |
24977 | } | |
24978 | ||
c19d1205 ZW |
24979 | struct arm_long_option_table arm_long_opts[] = |
24980 | { | |
24981 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
24982 | arm_parse_cpu, NULL}, | |
24983 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
24984 | arm_parse_arch, NULL}, | |
24985 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
24986 | arm_parse_fpu, NULL}, | |
24987 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
24988 | arm_parse_float_abi, NULL}, | |
24989 | #ifdef OBJ_ELF | |
7fac0536 | 24990 | {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"), |
c19d1205 ZW |
24991 | arm_parse_eabi, NULL}, |
24992 | #endif | |
e07e6e58 NC |
24993 | {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"), |
24994 | arm_parse_it_mode, NULL}, | |
2e6976a8 DG |
24995 | {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"), |
24996 | arm_ccs_mode, NULL}, | |
c19d1205 ZW |
24997 | {NULL, NULL, 0, NULL} |
24998 | }; | |
cc8a6dd0 | 24999 | |
c19d1205 ZW |
25000 | int |
25001 | md_parse_option (int c, char * arg) | |
25002 | { | |
25003 | struct arm_option_table *opt; | |
e74cfd16 | 25004 | const struct arm_legacy_option_table *fopt; |
c19d1205 | 25005 | struct arm_long_option_table *lopt; |
b99bd4ef | 25006 | |
c19d1205 | 25007 | switch (c) |
b99bd4ef | 25008 | { |
c19d1205 ZW |
25009 | #ifdef OPTION_EB |
25010 | case OPTION_EB: | |
25011 | target_big_endian = 1; | |
25012 | break; | |
25013 | #endif | |
cc8a6dd0 | 25014 | |
c19d1205 ZW |
25015 | #ifdef OPTION_EL |
25016 | case OPTION_EL: | |
25017 | target_big_endian = 0; | |
25018 | break; | |
25019 | #endif | |
b99bd4ef | 25020 | |
845b51d6 PB |
25021 | case OPTION_FIX_V4BX: |
25022 | fix_v4bx = TRUE; | |
25023 | break; | |
25024 | ||
c19d1205 ZW |
25025 | case 'a': |
25026 | /* Listing option. Just ignore these, we don't support additional | |
25027 | ones. */ | |
25028 | return 0; | |
b99bd4ef | 25029 | |
c19d1205 ZW |
25030 | default: |
25031 | for (opt = arm_opts; opt->option != NULL; opt++) | |
25032 | { | |
25033 | if (c == opt->option[0] | |
25034 | && ((arg == NULL && opt->option[1] == 0) | |
25035 | || streq (arg, opt->option + 1))) | |
25036 | { | |
c19d1205 | 25037 | /* If the option is deprecated, tell the user. */ |
278df34e | 25038 | if (warn_on_deprecated && opt->deprecated != NULL) |
c19d1205 ZW |
25039 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
25040 | arg ? arg : "", _(opt->deprecated)); | |
b99bd4ef | 25041 | |
c19d1205 ZW |
25042 | if (opt->var != NULL) |
25043 | *opt->var = opt->value; | |
cc8a6dd0 | 25044 | |
c19d1205 ZW |
25045 | return 1; |
25046 | } | |
25047 | } | |
b99bd4ef | 25048 | |
e74cfd16 PB |
25049 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
25050 | { | |
25051 | if (c == fopt->option[0] | |
25052 | && ((arg == NULL && fopt->option[1] == 0) | |
25053 | || streq (arg, fopt->option + 1))) | |
25054 | { | |
e74cfd16 | 25055 | /* If the option is deprecated, tell the user. */ |
278df34e | 25056 | if (warn_on_deprecated && fopt->deprecated != NULL) |
e74cfd16 PB |
25057 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
25058 | arg ? arg : "", _(fopt->deprecated)); | |
e74cfd16 PB |
25059 | |
25060 | if (fopt->var != NULL) | |
25061 | *fopt->var = &fopt->value; | |
25062 | ||
25063 | return 1; | |
25064 | } | |
25065 | } | |
25066 | ||
c19d1205 ZW |
25067 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
25068 | { | |
25069 | /* These options are expected to have an argument. */ | |
25070 | if (c == lopt->option[0] | |
25071 | && arg != NULL | |
25072 | && strncmp (arg, lopt->option + 1, | |
25073 | strlen (lopt->option + 1)) == 0) | |
25074 | { | |
c19d1205 | 25075 | /* If the option is deprecated, tell the user. */ |
278df34e | 25076 | if (warn_on_deprecated && lopt->deprecated != NULL) |
c19d1205 ZW |
25077 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, |
25078 | _(lopt->deprecated)); | |
b99bd4ef | 25079 | |
c19d1205 ZW |
25080 | /* Call the sup-option parser. */ |
25081 | return lopt->func (arg + strlen (lopt->option) - 1); | |
25082 | } | |
25083 | } | |
a737bd4d | 25084 | |
c19d1205 ZW |
25085 | return 0; |
25086 | } | |
a394c00f | 25087 | |
c19d1205 ZW |
25088 | return 1; |
25089 | } | |
a394c00f | 25090 | |
c19d1205 ZW |
25091 | void |
25092 | md_show_usage (FILE * fp) | |
a394c00f | 25093 | { |
c19d1205 ZW |
25094 | struct arm_option_table *opt; |
25095 | struct arm_long_option_table *lopt; | |
a394c00f | 25096 | |
c19d1205 | 25097 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 25098 | |
c19d1205 ZW |
25099 | for (opt = arm_opts; opt->option != NULL; opt++) |
25100 | if (opt->help != NULL) | |
25101 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 25102 | |
c19d1205 ZW |
25103 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
25104 | if (lopt->help != NULL) | |
25105 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 25106 | |
c19d1205 ZW |
25107 | #ifdef OPTION_EB |
25108 | fprintf (fp, _("\ | |
25109 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
25110 | #endif |
25111 | ||
c19d1205 ZW |
25112 | #ifdef OPTION_EL |
25113 | fprintf (fp, _("\ | |
25114 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 25115 | #endif |
845b51d6 PB |
25116 | |
25117 | fprintf (fp, _("\ | |
25118 | --fix-v4bx Allow BX in ARMv4 code\n")); | |
c19d1205 | 25119 | } |
ee065d83 PB |
25120 | |
25121 | ||
25122 | #ifdef OBJ_ELF | |
62b3e311 PB |
25123 | typedef struct |
25124 | { | |
25125 | int val; | |
25126 | arm_feature_set flags; | |
25127 | } cpu_arch_ver_table; | |
25128 | ||
25129 | /* Mapping from CPU features to EABI CPU arch values. Table must be sorted | |
25130 | least features first. */ | |
25131 | static const cpu_arch_ver_table cpu_arch_ver[] = | |
25132 | { | |
25133 | {1, ARM_ARCH_V4}, | |
25134 | {2, ARM_ARCH_V4T}, | |
25135 | {3, ARM_ARCH_V5}, | |
ee3c0378 | 25136 | {3, ARM_ARCH_V5T}, |
62b3e311 PB |
25137 | {4, ARM_ARCH_V5TE}, |
25138 | {5, ARM_ARCH_V5TEJ}, | |
25139 | {6, ARM_ARCH_V6}, | |
7e806470 | 25140 | {9, ARM_ARCH_V6K}, |
f4c65163 | 25141 | {7, ARM_ARCH_V6Z}, |
91e22acd | 25142 | {11, ARM_ARCH_V6M}, |
b2a5fbdc | 25143 | {12, ARM_ARCH_V6SM}, |
7e806470 | 25144 | {8, ARM_ARCH_V6T2}, |
c9fb6e58 | 25145 | {10, ARM_ARCH_V7VE}, |
62b3e311 PB |
25146 | {10, ARM_ARCH_V7R}, |
25147 | {10, ARM_ARCH_V7M}, | |
bca38921 | 25148 | {14, ARM_ARCH_V8A}, |
62b3e311 PB |
25149 | {0, ARM_ARCH_NONE} |
25150 | }; | |
25151 | ||
ee3c0378 AS |
25152 | /* Set an attribute if it has not already been set by the user. */ |
25153 | static void | |
25154 | aeabi_set_attribute_int (int tag, int value) | |
25155 | { | |
25156 | if (tag < 1 | |
25157 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
25158 | || !attributes_set_explicitly[tag]) | |
25159 | bfd_elf_add_proc_attr_int (stdoutput, tag, value); | |
25160 | } | |
25161 | ||
25162 | static void | |
25163 | aeabi_set_attribute_string (int tag, const char *value) | |
25164 | { | |
25165 | if (tag < 1 | |
25166 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
25167 | || !attributes_set_explicitly[tag]) | |
25168 | bfd_elf_add_proc_attr_string (stdoutput, tag, value); | |
25169 | } | |
25170 | ||
ee065d83 | 25171 | /* Set the public EABI object attributes. */ |
3cfdb781 | 25172 | void |
ee065d83 PB |
25173 | aeabi_set_public_attributes (void) |
25174 | { | |
25175 | int arch; | |
69239280 | 25176 | char profile; |
90ec0d68 | 25177 | int virt_sec = 0; |
bca38921 | 25178 | int fp16_optional = 0; |
e74cfd16 | 25179 | arm_feature_set flags; |
62b3e311 PB |
25180 | arm_feature_set tmp; |
25181 | const cpu_arch_ver_table *p; | |
ee065d83 PB |
25182 | |
25183 | /* Choose the architecture based on the capabilities of the requested cpu | |
25184 | (if any) and/or the instructions actually used. */ | |
e74cfd16 PB |
25185 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); |
25186 | ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); | |
25187 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); | |
ddd7f988 RE |
25188 | |
25189 | if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)) | |
25190 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1); | |
25191 | ||
25192 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any)) | |
25193 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t); | |
25194 | ||
7f78eb34 JW |
25195 | selected_cpu = flags; |
25196 | ||
ddd7f988 | 25197 | /* Allow the user to override the reported architecture. */ |
7a1d4c38 PB |
25198 | if (object_arch) |
25199 | { | |
25200 | ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); | |
25201 | ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); | |
25202 | } | |
25203 | ||
251665fc MGD |
25204 | /* We need to make sure that the attributes do not identify us as v6S-M |
25205 | when the only v6S-M feature in use is the Operating System Extensions. */ | |
25206 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os)) | |
25207 | if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only)) | |
477330fc | 25208 | ARM_CLEAR_FEATURE (flags, flags, arm_ext_os); |
251665fc | 25209 | |
62b3e311 PB |
25210 | tmp = flags; |
25211 | arch = 0; | |
25212 | for (p = cpu_arch_ver; p->val; p++) | |
25213 | { | |
25214 | if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) | |
25215 | { | |
25216 | arch = p->val; | |
25217 | ARM_CLEAR_FEATURE (tmp, tmp, p->flags); | |
25218 | } | |
25219 | } | |
ee065d83 | 25220 | |
9e3c6df6 PB |
25221 | /* The table lookup above finds the last architecture to contribute |
25222 | a new feature. Unfortunately, Tag13 is a subset of the union of | |
25223 | v6T2 and v7-M, so it is never seen as contributing a new feature. | |
25224 | We can not search for the last entry which is entirely used, | |
25225 | because if no CPU is specified we build up only those flags | |
25226 | actually used. Perhaps we should separate out the specified | |
25227 | and implicit cases. Avoid taking this path for -march=all by | |
25228 | checking for contradictory v7-A / v7-M features. */ | |
25229 | if (arch == 10 | |
25230 | && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a) | |
25231 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m) | |
25232 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp)) | |
25233 | arch = 13; | |
25234 | ||
ee065d83 PB |
25235 | /* Tag_CPU_name. */ |
25236 | if (selected_cpu_name[0]) | |
25237 | { | |
91d6fa6a | 25238 | char *q; |
ee065d83 | 25239 | |
91d6fa6a NC |
25240 | q = selected_cpu_name; |
25241 | if (strncmp (q, "armv", 4) == 0) | |
ee065d83 PB |
25242 | { |
25243 | int i; | |
5f4273c7 | 25244 | |
91d6fa6a NC |
25245 | q += 4; |
25246 | for (i = 0; q[i]; i++) | |
25247 | q[i] = TOUPPER (q[i]); | |
ee065d83 | 25248 | } |
91d6fa6a | 25249 | aeabi_set_attribute_string (Tag_CPU_name, q); |
ee065d83 | 25250 | } |
62f3b8c8 | 25251 | |
ee065d83 | 25252 | /* Tag_CPU_arch. */ |
ee3c0378 | 25253 | aeabi_set_attribute_int (Tag_CPU_arch, arch); |
62f3b8c8 | 25254 | |
62b3e311 PB |
25255 | /* Tag_CPU_arch_profile. */ |
25256 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) | |
69239280 | 25257 | profile = 'A'; |
62b3e311 | 25258 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) |
69239280 | 25259 | profile = 'R'; |
7e806470 | 25260 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m)) |
69239280 MGD |
25261 | profile = 'M'; |
25262 | else | |
25263 | profile = '\0'; | |
25264 | ||
25265 | if (profile != '\0') | |
25266 | aeabi_set_attribute_int (Tag_CPU_arch_profile, profile); | |
62f3b8c8 | 25267 | |
ee065d83 | 25268 | /* Tag_ARM_ISA_use. */ |
ee3c0378 AS |
25269 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) |
25270 | || arch == 0) | |
25271 | aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); | |
62f3b8c8 | 25272 | |
ee065d83 | 25273 | /* Tag_THUMB_ISA_use. */ |
ee3c0378 AS |
25274 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) |
25275 | || arch == 0) | |
25276 | aeabi_set_attribute_int (Tag_THUMB_ISA_use, | |
25277 | ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1); | |
62f3b8c8 | 25278 | |
ee065d83 | 25279 | /* Tag_VFP_arch. */ |
a715796b TG |
25280 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd)) |
25281 | aeabi_set_attribute_int (Tag_VFP_arch, | |
25282 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
25283 | ? 7 : 8); | |
bca38921 | 25284 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma)) |
62f3b8c8 PB |
25285 | aeabi_set_attribute_int (Tag_VFP_arch, |
25286 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
25287 | ? 5 : 6); | |
25288 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) | |
bca38921 MGD |
25289 | { |
25290 | fp16_optional = 1; | |
25291 | aeabi_set_attribute_int (Tag_VFP_arch, 3); | |
25292 | } | |
ada65aa3 | 25293 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd)) |
bca38921 MGD |
25294 | { |
25295 | aeabi_set_attribute_int (Tag_VFP_arch, 4); | |
25296 | fp16_optional = 1; | |
25297 | } | |
ee3c0378 AS |
25298 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) |
25299 | aeabi_set_attribute_int (Tag_VFP_arch, 2); | |
25300 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) | |
477330fc | 25301 | || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)) |
ee3c0378 | 25302 | aeabi_set_attribute_int (Tag_VFP_arch, 1); |
62f3b8c8 | 25303 | |
4547cb56 NC |
25304 | /* Tag_ABI_HardFP_use. */ |
25305 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd) | |
25306 | && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)) | |
25307 | aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1); | |
25308 | ||
ee065d83 | 25309 | /* Tag_WMMX_arch. */ |
ee3c0378 AS |
25310 | if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2)) |
25311 | aeabi_set_attribute_int (Tag_WMMX_arch, 2); | |
25312 | else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt)) | |
25313 | aeabi_set_attribute_int (Tag_WMMX_arch, 1); | |
62f3b8c8 | 25314 | |
ee3c0378 | 25315 | /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ |
bca38921 MGD |
25316 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8)) |
25317 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3); | |
25318 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) | |
25319 | { | |
25320 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)) | |
25321 | { | |
25322 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2); | |
25323 | } | |
25324 | else | |
25325 | { | |
25326 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1); | |
25327 | fp16_optional = 1; | |
25328 | } | |
25329 | } | |
fa94de6b | 25330 | |
ee3c0378 | 25331 | /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ |
bca38921 | 25332 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional) |
ee3c0378 | 25333 | aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); |
4547cb56 | 25334 | |
69239280 MGD |
25335 | /* Tag_DIV_use. |
25336 | ||
25337 | We set Tag_DIV_use to two when integer divide instructions have been used | |
25338 | in ARM state, or when Thumb integer divide instructions have been used, | |
25339 | but we have no architecture profile set, nor have we any ARM instructions. | |
25340 | ||
bca38921 MGD |
25341 | For ARMv8 we set the tag to 0 as integer divide is implied by the base |
25342 | architecture. | |
25343 | ||
69239280 | 25344 | For new architectures we will have to check these tests. */ |
bca38921 MGD |
25345 | gas_assert (arch <= TAG_CPU_ARCH_V8); |
25346 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)) | |
25347 | aeabi_set_attribute_int (Tag_DIV_use, 0); | |
25348 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv) | |
25349 | || (profile == '\0' | |
25350 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_div) | |
25351 | && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))) | |
eea54501 | 25352 | aeabi_set_attribute_int (Tag_DIV_use, 2); |
60e5ef9f MGD |
25353 | |
25354 | /* Tag_MP_extension_use. */ | |
25355 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp)) | |
25356 | aeabi_set_attribute_int (Tag_MPextension_use, 1); | |
f4c65163 MGD |
25357 | |
25358 | /* Tag Virtualization_use. */ | |
25359 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec)) | |
90ec0d68 MGD |
25360 | virt_sec |= 1; |
25361 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt)) | |
25362 | virt_sec |= 2; | |
25363 | if (virt_sec != 0) | |
25364 | aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec); | |
ee065d83 PB |
25365 | } |
25366 | ||
104d59d1 | 25367 | /* Add the default contents for the .ARM.attributes section. */ |
ee065d83 PB |
25368 | void |
25369 | arm_md_end (void) | |
25370 | { | |
ee065d83 PB |
25371 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
25372 | return; | |
25373 | ||
25374 | aeabi_set_public_attributes (); | |
ee065d83 | 25375 | } |
8463be01 | 25376 | #endif /* OBJ_ELF */ |
ee065d83 PB |
25377 | |
25378 | ||
25379 | /* Parse a .cpu directive. */ | |
25380 | ||
25381 | static void | |
25382 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) | |
25383 | { | |
e74cfd16 | 25384 | const struct arm_cpu_option_table *opt; |
ee065d83 PB |
25385 | char *name; |
25386 | char saved_char; | |
25387 | ||
25388 | name = input_line_pointer; | |
5f4273c7 | 25389 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
25390 | input_line_pointer++; |
25391 | saved_char = *input_line_pointer; | |
25392 | *input_line_pointer = 0; | |
25393 | ||
25394 | /* Skip the first "all" entry. */ | |
25395 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) | |
25396 | if (streq (opt->name, name)) | |
25397 | { | |
e74cfd16 PB |
25398 | mcpu_cpu_opt = &opt->value; |
25399 | selected_cpu = opt->value; | |
ee065d83 | 25400 | if (opt->canonical_name) |
5f4273c7 | 25401 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
25402 | else |
25403 | { | |
25404 | int i; | |
25405 | for (i = 0; opt->name[i]; i++) | |
25406 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
f3bad469 | 25407 | |
ee065d83 PB |
25408 | selected_cpu_name[i] = 0; |
25409 | } | |
e74cfd16 | 25410 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
25411 | *input_line_pointer = saved_char; |
25412 | demand_empty_rest_of_line (); | |
25413 | return; | |
25414 | } | |
25415 | as_bad (_("unknown cpu `%s'"), name); | |
25416 | *input_line_pointer = saved_char; | |
25417 | ignore_rest_of_line (); | |
25418 | } | |
25419 | ||
25420 | ||
25421 | /* Parse a .arch directive. */ | |
25422 | ||
25423 | static void | |
25424 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) | |
25425 | { | |
e74cfd16 | 25426 | const struct arm_arch_option_table *opt; |
ee065d83 PB |
25427 | char saved_char; |
25428 | char *name; | |
25429 | ||
25430 | name = input_line_pointer; | |
5f4273c7 | 25431 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
25432 | input_line_pointer++; |
25433 | saved_char = *input_line_pointer; | |
25434 | *input_line_pointer = 0; | |
25435 | ||
25436 | /* Skip the first "all" entry. */ | |
25437 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
25438 | if (streq (opt->name, name)) | |
25439 | { | |
e74cfd16 PB |
25440 | mcpu_cpu_opt = &opt->value; |
25441 | selected_cpu = opt->value; | |
5f4273c7 | 25442 | strcpy (selected_cpu_name, opt->name); |
e74cfd16 | 25443 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
25444 | *input_line_pointer = saved_char; |
25445 | demand_empty_rest_of_line (); | |
25446 | return; | |
25447 | } | |
25448 | ||
25449 | as_bad (_("unknown architecture `%s'\n"), name); | |
25450 | *input_line_pointer = saved_char; | |
25451 | ignore_rest_of_line (); | |
25452 | } | |
25453 | ||
25454 | ||
7a1d4c38 PB |
25455 | /* Parse a .object_arch directive. */ |
25456 | ||
25457 | static void | |
25458 | s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) | |
25459 | { | |
25460 | const struct arm_arch_option_table *opt; | |
25461 | char saved_char; | |
25462 | char *name; | |
25463 | ||
25464 | name = input_line_pointer; | |
5f4273c7 | 25465 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
7a1d4c38 PB |
25466 | input_line_pointer++; |
25467 | saved_char = *input_line_pointer; | |
25468 | *input_line_pointer = 0; | |
25469 | ||
25470 | /* Skip the first "all" entry. */ | |
25471 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
25472 | if (streq (opt->name, name)) | |
25473 | { | |
25474 | object_arch = &opt->value; | |
25475 | *input_line_pointer = saved_char; | |
25476 | demand_empty_rest_of_line (); | |
25477 | return; | |
25478 | } | |
25479 | ||
25480 | as_bad (_("unknown architecture `%s'\n"), name); | |
25481 | *input_line_pointer = saved_char; | |
25482 | ignore_rest_of_line (); | |
25483 | } | |
25484 | ||
69133863 MGD |
25485 | /* Parse a .arch_extension directive. */ |
25486 | ||
25487 | static void | |
25488 | s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED) | |
25489 | { | |
25490 | const struct arm_option_extension_value_table *opt; | |
25491 | char saved_char; | |
25492 | char *name; | |
25493 | int adding_value = 1; | |
25494 | ||
25495 | name = input_line_pointer; | |
25496 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) | |
25497 | input_line_pointer++; | |
25498 | saved_char = *input_line_pointer; | |
25499 | *input_line_pointer = 0; | |
25500 | ||
25501 | if (strlen (name) >= 2 | |
25502 | && strncmp (name, "no", 2) == 0) | |
25503 | { | |
25504 | adding_value = 0; | |
25505 | name += 2; | |
25506 | } | |
25507 | ||
25508 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
25509 | if (streq (opt->name, name)) | |
25510 | { | |
25511 | if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs)) | |
25512 | { | |
25513 | as_bad (_("architectural extension `%s' is not allowed for the " | |
25514 | "current base architecture"), name); | |
25515 | break; | |
25516 | } | |
25517 | ||
25518 | if (adding_value) | |
5a70a223 JB |
25519 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, |
25520 | opt->merge_value); | |
69133863 | 25521 | else |
5a70a223 | 25522 | ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->clear_value); |
69133863 MGD |
25523 | |
25524 | mcpu_cpu_opt = &selected_cpu; | |
25525 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
25526 | *input_line_pointer = saved_char; | |
25527 | demand_empty_rest_of_line (); | |
25528 | return; | |
25529 | } | |
25530 | ||
25531 | if (opt->name == NULL) | |
e673710a | 25532 | as_bad (_("unknown architecture extension `%s'\n"), name); |
69133863 MGD |
25533 | |
25534 | *input_line_pointer = saved_char; | |
25535 | ignore_rest_of_line (); | |
25536 | } | |
25537 | ||
ee065d83 PB |
25538 | /* Parse a .fpu directive. */ |
25539 | ||
25540 | static void | |
25541 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) | |
25542 | { | |
69133863 | 25543 | const struct arm_option_fpu_value_table *opt; |
ee065d83 PB |
25544 | char saved_char; |
25545 | char *name; | |
25546 | ||
25547 | name = input_line_pointer; | |
5f4273c7 | 25548 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
25549 | input_line_pointer++; |
25550 | saved_char = *input_line_pointer; | |
25551 | *input_line_pointer = 0; | |
5f4273c7 | 25552 | |
ee065d83 PB |
25553 | for (opt = arm_fpus; opt->name != NULL; opt++) |
25554 | if (streq (opt->name, name)) | |
25555 | { | |
e74cfd16 PB |
25556 | mfpu_opt = &opt->value; |
25557 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
ee065d83 PB |
25558 | *input_line_pointer = saved_char; |
25559 | demand_empty_rest_of_line (); | |
25560 | return; | |
25561 | } | |
25562 | ||
25563 | as_bad (_("unknown floating point format `%s'\n"), name); | |
25564 | *input_line_pointer = saved_char; | |
25565 | ignore_rest_of_line (); | |
25566 | } | |
ee065d83 | 25567 | |
794ba86a | 25568 | /* Copy symbol information. */ |
f31fef98 | 25569 | |
794ba86a DJ |
25570 | void |
25571 | arm_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
25572 | { | |
25573 | ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); | |
25574 | } | |
e04befd0 | 25575 | |
f31fef98 | 25576 | #ifdef OBJ_ELF |
e04befd0 AS |
25577 | /* Given a symbolic attribute NAME, return the proper integer value. |
25578 | Returns -1 if the attribute is not known. */ | |
f31fef98 | 25579 | |
e04befd0 AS |
25580 | int |
25581 | arm_convert_symbolic_attribute (const char *name) | |
25582 | { | |
f31fef98 NC |
25583 | static const struct |
25584 | { | |
25585 | const char * name; | |
25586 | const int tag; | |
25587 | } | |
25588 | attribute_table[] = | |
25589 | { | |
25590 | /* When you modify this table you should | |
25591 | also modify the list in doc/c-arm.texi. */ | |
e04befd0 | 25592 | #define T(tag) {#tag, tag} |
f31fef98 NC |
25593 | T (Tag_CPU_raw_name), |
25594 | T (Tag_CPU_name), | |
25595 | T (Tag_CPU_arch), | |
25596 | T (Tag_CPU_arch_profile), | |
25597 | T (Tag_ARM_ISA_use), | |
25598 | T (Tag_THUMB_ISA_use), | |
75375b3e | 25599 | T (Tag_FP_arch), |
f31fef98 NC |
25600 | T (Tag_VFP_arch), |
25601 | T (Tag_WMMX_arch), | |
25602 | T (Tag_Advanced_SIMD_arch), | |
25603 | T (Tag_PCS_config), | |
25604 | T (Tag_ABI_PCS_R9_use), | |
25605 | T (Tag_ABI_PCS_RW_data), | |
25606 | T (Tag_ABI_PCS_RO_data), | |
25607 | T (Tag_ABI_PCS_GOT_use), | |
25608 | T (Tag_ABI_PCS_wchar_t), | |
25609 | T (Tag_ABI_FP_rounding), | |
25610 | T (Tag_ABI_FP_denormal), | |
25611 | T (Tag_ABI_FP_exceptions), | |
25612 | T (Tag_ABI_FP_user_exceptions), | |
25613 | T (Tag_ABI_FP_number_model), | |
75375b3e | 25614 | T (Tag_ABI_align_needed), |
f31fef98 | 25615 | T (Tag_ABI_align8_needed), |
75375b3e | 25616 | T (Tag_ABI_align_preserved), |
f31fef98 NC |
25617 | T (Tag_ABI_align8_preserved), |
25618 | T (Tag_ABI_enum_size), | |
25619 | T (Tag_ABI_HardFP_use), | |
25620 | T (Tag_ABI_VFP_args), | |
25621 | T (Tag_ABI_WMMX_args), | |
25622 | T (Tag_ABI_optimization_goals), | |
25623 | T (Tag_ABI_FP_optimization_goals), | |
25624 | T (Tag_compatibility), | |
25625 | T (Tag_CPU_unaligned_access), | |
75375b3e | 25626 | T (Tag_FP_HP_extension), |
f31fef98 NC |
25627 | T (Tag_VFP_HP_extension), |
25628 | T (Tag_ABI_FP_16bit_format), | |
cd21e546 MGD |
25629 | T (Tag_MPextension_use), |
25630 | T (Tag_DIV_use), | |
f31fef98 NC |
25631 | T (Tag_nodefaults), |
25632 | T (Tag_also_compatible_with), | |
25633 | T (Tag_conformance), | |
25634 | T (Tag_T2EE_use), | |
25635 | T (Tag_Virtualization_use), | |
cd21e546 | 25636 | /* We deliberately do not include Tag_MPextension_use_legacy. */ |
e04befd0 | 25637 | #undef T |
f31fef98 | 25638 | }; |
e04befd0 AS |
25639 | unsigned int i; |
25640 | ||
25641 | if (name == NULL) | |
25642 | return -1; | |
25643 | ||
f31fef98 | 25644 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
c921be7d | 25645 | if (streq (name, attribute_table[i].name)) |
e04befd0 AS |
25646 | return attribute_table[i].tag; |
25647 | ||
25648 | return -1; | |
25649 | } | |
267bf995 RR |
25650 | |
25651 | ||
25652 | /* Apply sym value for relocations only in the case that | |
25653 | they are for local symbols and you have the respective | |
25654 | architectural feature for blx and simple switches. */ | |
25655 | int | |
25656 | arm_apply_sym_value (struct fix * fixP) | |
25657 | { | |
25658 | if (fixP->fx_addsy | |
25659 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
34e77a92 | 25660 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
267bf995 RR |
25661 | { |
25662 | switch (fixP->fx_r_type) | |
25663 | { | |
25664 | case BFD_RELOC_ARM_PCREL_BLX: | |
25665 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
25666 | if (ARM_IS_FUNC (fixP->fx_addsy)) | |
25667 | return 1; | |
25668 | break; | |
25669 | ||
25670 | case BFD_RELOC_ARM_PCREL_CALL: | |
25671 | case BFD_RELOC_THUMB_PCREL_BLX: | |
25672 | if (THUMB_IS_FUNC (fixP->fx_addsy)) | |
25673 | return 1; | |
25674 | break; | |
25675 | ||
25676 | default: | |
25677 | break; | |
25678 | } | |
25679 | ||
25680 | } | |
25681 | return 0; | |
25682 | } | |
f31fef98 | 25683 | #endif /* OBJ_ELF */ |