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b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
219d1afa | 2 | Copyright (C) 1994-2018 Free Software Foundation, Inc. |
b99bd4ef NC |
3 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) |
4 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 5 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
6 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
7 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
8 | |
9 | This file is part of GAS, the GNU Assembler. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 13 | the Free Software Foundation; either version 3, or (at your option) |
b99bd4ef NC |
14 | any later version. |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
19 | GNU General Public License for more details. |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
b99bd4ef | 25 | |
42a68e18 | 26 | #include "as.h" |
5287ad62 | 27 | #include <limits.h> |
037e8744 | 28 | #include <stdarg.h> |
c19d1205 | 29 | #define NO_RELOC 0 |
3882b010 | 30 | #include "safe-ctype.h" |
b99bd4ef NC |
31 | #include "subsegs.h" |
32 | #include "obstack.h" | |
3da1d841 | 33 | #include "libiberty.h" |
f263249b RE |
34 | #include "opcode/arm.h" |
35 | ||
b99bd4ef NC |
36 | #ifdef OBJ_ELF |
37 | #include "elf/arm.h" | |
a394c00f | 38 | #include "dw2gencfi.h" |
b99bd4ef NC |
39 | #endif |
40 | ||
f0927246 NC |
41 | #include "dwarf2dbg.h" |
42 | ||
7ed4c4c5 NC |
43 | #ifdef OBJ_ELF |
44 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
45 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
46 | ||
47 | /* This structure holds the unwinding state. */ | |
48 | ||
49 | static struct | |
50 | { | |
c19d1205 ZW |
51 | symbolS * proc_start; |
52 | symbolS * table_entry; | |
53 | symbolS * personality_routine; | |
54 | int personality_index; | |
7ed4c4c5 | 55 | /* The segment containing the function. */ |
c19d1205 ZW |
56 | segT saved_seg; |
57 | subsegT saved_subseg; | |
7ed4c4c5 NC |
58 | /* Opcodes generated from this function. */ |
59 | unsigned char * opcodes; | |
c19d1205 ZW |
60 | int opcode_count; |
61 | int opcode_alloc; | |
7ed4c4c5 | 62 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 63 | offsetT frame_size; |
7ed4c4c5 NC |
64 | /* We don't add stack adjustment opcodes immediately so that we can merge |
65 | multiple adjustments. We can also omit the final adjustment | |
66 | when using a frame pointer. */ | |
c19d1205 | 67 | offsetT pending_offset; |
7ed4c4c5 | 68 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
69 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
70 | offsetT fp_offset; | |
71 | int fp_reg; | |
7ed4c4c5 | 72 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 73 | unsigned fp_used:1; |
7ed4c4c5 | 74 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 75 | unsigned sp_restored:1; |
7ed4c4c5 NC |
76 | } unwind; |
77 | ||
18a20338 CL |
78 | /* Whether --fdpic was given. */ |
79 | static int arm_fdpic; | |
80 | ||
8b1ad454 NC |
81 | #endif /* OBJ_ELF */ |
82 | ||
4962c51a MS |
83 | /* Results from operand parsing worker functions. */ |
84 | ||
85 | typedef enum | |
86 | { | |
87 | PARSE_OPERAND_SUCCESS, | |
88 | PARSE_OPERAND_FAIL, | |
89 | PARSE_OPERAND_FAIL_NO_BACKTRACK | |
90 | } parse_operand_result; | |
91 | ||
33a392fb PB |
92 | enum arm_float_abi |
93 | { | |
94 | ARM_FLOAT_ABI_HARD, | |
95 | ARM_FLOAT_ABI_SOFTFP, | |
96 | ARM_FLOAT_ABI_SOFT | |
97 | }; | |
98 | ||
c19d1205 | 99 | /* Types of processor to assemble for. */ |
b99bd4ef | 100 | #ifndef CPU_DEFAULT |
8a59fff3 | 101 | /* The code that was here used to select a default CPU depending on compiler |
fa94de6b | 102 | pre-defines which were only present when doing native builds, thus |
8a59fff3 MGD |
103 | changing gas' default behaviour depending upon the build host. |
104 | ||
105 | If you have a target that requires a default CPU option then the you | |
106 | should define CPU_DEFAULT here. */ | |
b99bd4ef NC |
107 | #endif |
108 | ||
109 | #ifndef FPU_DEFAULT | |
c820d418 MM |
110 | # ifdef TE_LINUX |
111 | # define FPU_DEFAULT FPU_ARCH_FPA | |
112 | # elif defined (TE_NetBSD) | |
113 | # ifdef OBJ_ELF | |
114 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
115 | # else | |
116 | /* Legacy a.out format. */ | |
117 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
118 | # endif | |
4e7fd91e PB |
119 | # elif defined (TE_VXWORKS) |
120 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
121 | # else |
122 | /* For backwards compatibility, default to FPA. */ | |
123 | # define FPU_DEFAULT FPU_ARCH_FPA | |
124 | # endif | |
125 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 126 | |
c19d1205 | 127 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 128 | |
4d354d8b TP |
129 | /* Current set of feature bits available (CPU+FPU). Different from |
130 | selected_cpu + selected_fpu in case of autodetection since the CPU | |
131 | feature bits are then all set. */ | |
e74cfd16 | 132 | static arm_feature_set cpu_variant; |
4d354d8b TP |
133 | /* Feature bits used in each execution state. Used to set build attribute |
134 | (in particular Tag_*_ISA_use) in CPU autodetection mode. */ | |
e74cfd16 PB |
135 | static arm_feature_set arm_arch_used; |
136 | static arm_feature_set thumb_arch_used; | |
b99bd4ef | 137 | |
b99bd4ef | 138 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
139 | static int uses_apcs_26 = FALSE; |
140 | static int atpcs = FALSE; | |
b34976b6 AM |
141 | static int support_interwork = FALSE; |
142 | static int uses_apcs_float = FALSE; | |
c19d1205 | 143 | static int pic_code = FALSE; |
845b51d6 | 144 | static int fix_v4bx = FALSE; |
278df34e NS |
145 | /* Warn on using deprecated features. */ |
146 | static int warn_on_deprecated = TRUE; | |
147 | ||
2e6976a8 DG |
148 | /* Understand CodeComposer Studio assembly syntax. */ |
149 | bfd_boolean codecomposer_syntax = FALSE; | |
03b1477f RE |
150 | |
151 | /* Variables that we set while parsing command-line options. Once all | |
152 | options have been read we re-process these values to set the real | |
153 | assembly flags. */ | |
4d354d8b TP |
154 | |
155 | /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1 | |
156 | instead of -mcpu=arm1). */ | |
157 | static const arm_feature_set *legacy_cpu = NULL; | |
158 | static const arm_feature_set *legacy_fpu = NULL; | |
159 | ||
160 | /* CPU, extension and FPU feature bits selected by -mcpu. */ | |
161 | static const arm_feature_set *mcpu_cpu_opt = NULL; | |
162 | static arm_feature_set *mcpu_ext_opt = NULL; | |
163 | static const arm_feature_set *mcpu_fpu_opt = NULL; | |
164 | ||
165 | /* CPU, extension and FPU feature bits selected by -march. */ | |
166 | static const arm_feature_set *march_cpu_opt = NULL; | |
167 | static arm_feature_set *march_ext_opt = NULL; | |
168 | static const arm_feature_set *march_fpu_opt = NULL; | |
169 | ||
170 | /* Feature bits selected by -mfpu. */ | |
171 | static const arm_feature_set *mfpu_opt = NULL; | |
e74cfd16 PB |
172 | |
173 | /* Constants for known architecture features. */ | |
174 | static const arm_feature_set fpu_default = FPU_DEFAULT; | |
f85d59c3 | 175 | static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V1; |
e74cfd16 | 176 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; |
f85d59c3 KT |
177 | static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V3; |
178 | static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED = FPU_ARCH_NEON_V1; | |
e74cfd16 PB |
179 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; |
180 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; | |
69c9e028 | 181 | #ifdef OBJ_ELF |
e74cfd16 | 182 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; |
69c9e028 | 183 | #endif |
e74cfd16 PB |
184 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; |
185 | ||
186 | #ifdef CPU_DEFAULT | |
187 | static const arm_feature_set cpu_default = CPU_DEFAULT; | |
188 | #endif | |
189 | ||
823d2571 | 190 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1); |
4070243b | 191 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V2); |
823d2571 TG |
192 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S); |
193 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3); | |
194 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M); | |
195 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4); | |
196 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T); | |
197 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5); | |
e74cfd16 | 198 | static const arm_feature_set arm_ext_v4t_5 = |
823d2571 TG |
199 | ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5); |
200 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T); | |
201 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E); | |
202 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP); | |
203 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J); | |
204 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6); | |
205 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K); | |
206 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2); | |
823d2571 TG |
207 | static const arm_feature_set arm_ext_v6_notm = |
208 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM); | |
209 | static const arm_feature_set arm_ext_v6_dsp = | |
210 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP); | |
211 | static const arm_feature_set arm_ext_barrier = | |
212 | ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER); | |
213 | static const arm_feature_set arm_ext_msr = | |
214 | ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR); | |
215 | static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV); | |
216 | static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7); | |
217 | static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A); | |
218 | static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R); | |
69c9e028 | 219 | #ifdef OBJ_ELF |
e7d39ed3 | 220 | static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M); |
69c9e028 | 221 | #endif |
823d2571 | 222 | static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8); |
7e806470 | 223 | static const arm_feature_set arm_ext_m = |
173205ca | 224 | ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_V7M, |
16a1fa25 | 225 | ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN); |
823d2571 TG |
226 | static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP); |
227 | static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC); | |
228 | static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS); | |
229 | static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV); | |
230 | static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT); | |
ddfded2f | 231 | static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN); |
4ed7ed8d | 232 | static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M); |
16a1fa25 TP |
233 | static const arm_feature_set arm_ext_v8m_main = |
234 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN); | |
235 | /* Instructions in ARMv8-M only found in M profile architectures. */ | |
236 | static const arm_feature_set arm_ext_v8m_m_only = | |
237 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN); | |
ff8646ee TP |
238 | static const arm_feature_set arm_ext_v6t2_v8m = |
239 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M); | |
4ed7ed8d TP |
240 | /* Instructions shared between ARMv8-A and ARMv8-M. */ |
241 | static const arm_feature_set arm_ext_atomics = | |
242 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS); | |
69c9e028 | 243 | #ifdef OBJ_ELF |
15afaa63 TP |
244 | /* DSP instructions Tag_DSP_extension refers to. */ |
245 | static const arm_feature_set arm_ext_dsp = | |
246 | ARM_FEATURE_CORE_LOW (ARM_EXT_V5E | ARM_EXT_V5ExP | ARM_EXT_V6_DSP); | |
69c9e028 | 247 | #endif |
4d1464f2 MW |
248 | static const arm_feature_set arm_ext_ras = |
249 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS); | |
b8ec4e87 JW |
250 | /* FP16 instructions. */ |
251 | static const arm_feature_set arm_ext_fp16 = | |
252 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST); | |
01f48020 TC |
253 | static const arm_feature_set arm_ext_fp16_fml = |
254 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML); | |
dec41383 JW |
255 | static const arm_feature_set arm_ext_v8_2 = |
256 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A); | |
49e8a725 SN |
257 | static const arm_feature_set arm_ext_v8_3 = |
258 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A); | |
7fadb25d SD |
259 | static const arm_feature_set arm_ext_sb = |
260 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB); | |
dad0c3bf SD |
261 | static const arm_feature_set arm_ext_predres = |
262 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES); | |
e74cfd16 PB |
263 | |
264 | static const arm_feature_set arm_arch_any = ARM_ANY; | |
49fa50ef | 265 | #ifdef OBJ_ELF |
2c6b98ea | 266 | static const arm_feature_set fpu_any = FPU_ANY; |
49fa50ef | 267 | #endif |
f85d59c3 | 268 | static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1); |
e74cfd16 PB |
269 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; |
270 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; | |
271 | ||
2d447fca | 272 | static const arm_feature_set arm_cext_iwmmxt2 = |
823d2571 | 273 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2); |
e74cfd16 | 274 | static const arm_feature_set arm_cext_iwmmxt = |
823d2571 | 275 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT); |
e74cfd16 | 276 | static const arm_feature_set arm_cext_xscale = |
823d2571 | 277 | ARM_FEATURE_COPROC (ARM_CEXT_XSCALE); |
e74cfd16 | 278 | static const arm_feature_set arm_cext_maverick = |
823d2571 TG |
279 | ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK); |
280 | static const arm_feature_set fpu_fpa_ext_v1 = | |
281 | ARM_FEATURE_COPROC (FPU_FPA_EXT_V1); | |
282 | static const arm_feature_set fpu_fpa_ext_v2 = | |
283 | ARM_FEATURE_COPROC (FPU_FPA_EXT_V2); | |
e74cfd16 | 284 | static const arm_feature_set fpu_vfp_ext_v1xd = |
823d2571 TG |
285 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD); |
286 | static const arm_feature_set fpu_vfp_ext_v1 = | |
287 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V1); | |
288 | static const arm_feature_set fpu_vfp_ext_v2 = | |
289 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V2); | |
290 | static const arm_feature_set fpu_vfp_ext_v3xd = | |
291 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD); | |
292 | static const arm_feature_set fpu_vfp_ext_v3 = | |
293 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V3); | |
b1cc4aeb | 294 | static const arm_feature_set fpu_vfp_ext_d32 = |
823d2571 TG |
295 | ARM_FEATURE_COPROC (FPU_VFP_EXT_D32); |
296 | static const arm_feature_set fpu_neon_ext_v1 = | |
297 | ARM_FEATURE_COPROC (FPU_NEON_EXT_V1); | |
5287ad62 | 298 | static const arm_feature_set fpu_vfp_v3_or_neon_ext = |
823d2571 | 299 | ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); |
69c9e028 | 300 | #ifdef OBJ_ELF |
823d2571 TG |
301 | static const arm_feature_set fpu_vfp_fp16 = |
302 | ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16); | |
303 | static const arm_feature_set fpu_neon_ext_fma = | |
304 | ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA); | |
69c9e028 | 305 | #endif |
823d2571 TG |
306 | static const arm_feature_set fpu_vfp_ext_fma = |
307 | ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA); | |
bca38921 | 308 | static const arm_feature_set fpu_vfp_ext_armv8 = |
823d2571 | 309 | ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8); |
a715796b | 310 | static const arm_feature_set fpu_vfp_ext_armv8xd = |
823d2571 | 311 | ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD); |
bca38921 | 312 | static const arm_feature_set fpu_neon_ext_armv8 = |
823d2571 | 313 | ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8); |
bca38921 | 314 | static const arm_feature_set fpu_crypto_ext_armv8 = |
823d2571 | 315 | ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8); |
dd5181d5 | 316 | static const arm_feature_set crc_ext_armv8 = |
823d2571 | 317 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8); |
d6b4b13e | 318 | static const arm_feature_set fpu_neon_ext_v8_1 = |
643afb90 | 319 | ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA); |
c604a79a JW |
320 | static const arm_feature_set fpu_neon_ext_dotprod = |
321 | ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD); | |
e74cfd16 | 322 | |
33a392fb | 323 | static int mfloat_abi_opt = -1; |
4d354d8b TP |
324 | /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch |
325 | directive. */ | |
326 | static arm_feature_set selected_arch = ARM_ARCH_NONE; | |
327 | /* Extension feature bits selected by the last -mcpu/-march or .arch_extension | |
328 | directive. */ | |
329 | static arm_feature_set selected_ext = ARM_ARCH_NONE; | |
330 | /* Feature bits selected by the last -mcpu/-march or by the combination of the | |
331 | last .cpu/.arch directive .arch_extension directives since that | |
332 | directive. */ | |
e74cfd16 | 333 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; |
4d354d8b TP |
334 | /* FPU feature bits selected by the last -mfpu or .fpu directive. */ |
335 | static arm_feature_set selected_fpu = FPU_NONE; | |
336 | /* Feature bits selected by the last .object_arch directive. */ | |
337 | static arm_feature_set selected_object_arch = ARM_ARCH_NONE; | |
ee065d83 | 338 | /* Must be long enough to hold any of the names in arm_cpus. */ |
ef8e6722 | 339 | static char selected_cpu_name[20]; |
8d67f500 | 340 | |
aacf0b33 KT |
341 | extern FLONUM_TYPE generic_floating_point_number; |
342 | ||
8d67f500 NC |
343 | /* Return if no cpu was selected on command-line. */ |
344 | static bfd_boolean | |
345 | no_cpu_selected (void) | |
346 | { | |
823d2571 | 347 | return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none); |
8d67f500 NC |
348 | } |
349 | ||
7cc69913 | 350 | #ifdef OBJ_ELF |
deeaaff8 DJ |
351 | # ifdef EABI_DEFAULT |
352 | static int meabi_flags = EABI_DEFAULT; | |
353 | # else | |
d507cf36 | 354 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 355 | # endif |
e1da3f5b | 356 | |
ee3c0378 AS |
357 | static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; |
358 | ||
e1da3f5b | 359 | bfd_boolean |
5f4273c7 | 360 | arm_is_eabi (void) |
e1da3f5b PB |
361 | { |
362 | return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); | |
363 | } | |
7cc69913 | 364 | #endif |
b99bd4ef | 365 | |
b99bd4ef | 366 | #ifdef OBJ_ELF |
c19d1205 | 367 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
368 | symbolS * GOT_symbol; |
369 | #endif | |
370 | ||
b99bd4ef NC |
371 | /* 0: assemble for ARM, |
372 | 1: assemble for Thumb, | |
373 | 2: assemble for Thumb even though target CPU does not support thumb | |
374 | instructions. */ | |
375 | static int thumb_mode = 0; | |
8dc2430f NC |
376 | /* A value distinct from the possible values for thumb_mode that we |
377 | can use to record whether thumb_mode has been copied into the | |
378 | tc_frag_data field of a frag. */ | |
379 | #define MODE_RECORDED (1 << 4) | |
b99bd4ef | 380 | |
e07e6e58 NC |
381 | /* Specifies the intrinsic IT insn behavior mode. */ |
382 | enum implicit_it_mode | |
383 | { | |
384 | IMPLICIT_IT_MODE_NEVER = 0x00, | |
385 | IMPLICIT_IT_MODE_ARM = 0x01, | |
386 | IMPLICIT_IT_MODE_THUMB = 0x02, | |
387 | IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB) | |
388 | }; | |
389 | static int implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
390 | ||
c19d1205 ZW |
391 | /* If unified_syntax is true, we are processing the new unified |
392 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
393 | ||
394 | - Immediate operands do not require a # prefix. | |
395 | - Conditional affixes always appear at the end of the | |
396 | instruction. (For backward compatibility, those instructions | |
397 | that formerly had them in the middle, continue to accept them | |
398 | there.) | |
399 | - The IT instruction may appear, and if it does is validated | |
400 | against subsequent conditional affixes. It does not generate | |
401 | machine code. | |
402 | ||
403 | Important differences from the old Thumb mode: | |
404 | ||
405 | - Immediate operands do not require a # prefix. | |
406 | - Most of the V6T2 instructions are only available in unified mode. | |
407 | - The .N and .W suffixes are recognized and honored (it is an error | |
408 | if they cannot be honored). | |
409 | - All instructions set the flags if and only if they have an 's' affix. | |
410 | - Conditional affixes may be used. They are validated against | |
411 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
412 | conditional affix except in the scope of an IT instruction. */ | |
413 | ||
414 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef | 415 | |
bacebabc RM |
416 | /* An immediate operand can start with #, and ld*, st*, pld operands |
417 | can contain [ and ]. We need to tell APP not to elide whitespace | |
477330fc RM |
418 | before a [, which can appear as the first operand for pld. |
419 | Likewise, a { can appear as the first operand for push, pop, vld*, etc. */ | |
420 | const char arm_symbol_chars[] = "#[]{}"; | |
bacebabc | 421 | |
5287ad62 JB |
422 | enum neon_el_type |
423 | { | |
dcbf9037 | 424 | NT_invtype, |
5287ad62 JB |
425 | NT_untyped, |
426 | NT_integer, | |
427 | NT_float, | |
428 | NT_poly, | |
429 | NT_signed, | |
dcbf9037 | 430 | NT_unsigned |
5287ad62 JB |
431 | }; |
432 | ||
433 | struct neon_type_el | |
434 | { | |
435 | enum neon_el_type type; | |
436 | unsigned size; | |
437 | }; | |
438 | ||
439 | #define NEON_MAX_TYPE_ELS 4 | |
440 | ||
441 | struct neon_type | |
442 | { | |
443 | struct neon_type_el el[NEON_MAX_TYPE_ELS]; | |
444 | unsigned elems; | |
445 | }; | |
446 | ||
e07e6e58 NC |
447 | enum it_instruction_type |
448 | { | |
449 | OUTSIDE_IT_INSN, | |
450 | INSIDE_IT_INSN, | |
451 | INSIDE_IT_LAST_INSN, | |
452 | IF_INSIDE_IT_LAST_INSN, /* Either outside or inside; | |
477330fc | 453 | if inside, should be the last one. */ |
e07e6e58 | 454 | NEUTRAL_IT_INSN, /* This could be either inside or outside, |
477330fc | 455 | i.e. BKPT and NOP. */ |
e07e6e58 NC |
456 | IT_INSN /* The IT insn has been parsed. */ |
457 | }; | |
458 | ||
ad6cec43 MGD |
459 | /* The maximum number of operands we need. */ |
460 | #define ARM_IT_MAX_OPERANDS 6 | |
461 | ||
b99bd4ef NC |
462 | struct arm_it |
463 | { | |
c19d1205 | 464 | const char * error; |
b99bd4ef | 465 | unsigned long instruction; |
c19d1205 ZW |
466 | int size; |
467 | int size_req; | |
468 | int cond; | |
037e8744 JB |
469 | /* "uncond_value" is set to the value in place of the conditional field in |
470 | unconditional versions of the instruction, or -1 if nothing is | |
471 | appropriate. */ | |
472 | int uncond_value; | |
5287ad62 | 473 | struct neon_type vectype; |
88714cb8 DG |
474 | /* This does not indicate an actual NEON instruction, only that |
475 | the mnemonic accepts neon-style type suffixes. */ | |
476 | int is_neon; | |
0110f2b8 PB |
477 | /* Set to the opcode if the instruction needs relaxation. |
478 | Zero if the instruction is not relaxed. */ | |
479 | unsigned long relax; | |
b99bd4ef NC |
480 | struct |
481 | { | |
482 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
483 | expressionS exp; |
484 | int pc_rel; | |
b99bd4ef | 485 | } reloc; |
b99bd4ef | 486 | |
e07e6e58 NC |
487 | enum it_instruction_type it_insn_type; |
488 | ||
c19d1205 ZW |
489 | struct |
490 | { | |
491 | unsigned reg; | |
ca3f61f7 | 492 | signed int imm; |
dcbf9037 | 493 | struct neon_type_el vectype; |
ca3f61f7 NC |
494 | unsigned present : 1; /* Operand present. */ |
495 | unsigned isreg : 1; /* Operand was a register. */ | |
496 | unsigned immisreg : 1; /* .imm field is a second register. */ | |
5287ad62 JB |
497 | unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ |
498 | unsigned immisalign : 1; /* Immediate is an alignment specifier. */ | |
c96612cc | 499 | unsigned immisfloat : 1; /* Immediate was parsed as a float. */ |
5287ad62 JB |
500 | /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV |
501 | instructions. This allows us to disambiguate ARM <-> vector insns. */ | |
502 | unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ | |
037e8744 | 503 | unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ |
5287ad62 | 504 | unsigned isquad : 1; /* Operand is Neon quad-precision register. */ |
037e8744 | 505 | unsigned issingle : 1; /* Operand is VFP single-precision register. */ |
ca3f61f7 NC |
506 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ |
507 | unsigned writeback : 1; /* Operand has trailing ! */ | |
508 | unsigned preind : 1; /* Preindexed address. */ | |
509 | unsigned postind : 1; /* Postindexed address. */ | |
510 | unsigned negative : 1; /* Index register was negated. */ | |
511 | unsigned shifted : 1; /* Shift applied to operation. */ | |
512 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
ad6cec43 | 513 | } operands[ARM_IT_MAX_OPERANDS]; |
b99bd4ef NC |
514 | }; |
515 | ||
c19d1205 | 516 | static struct arm_it inst; |
b99bd4ef NC |
517 | |
518 | #define NUM_FLOAT_VALS 8 | |
519 | ||
05d2d07e | 520 | const char * fp_const[] = |
b99bd4ef NC |
521 | { |
522 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
523 | }; | |
524 | ||
c19d1205 | 525 | /* Number of littlenums required to hold an extended precision number. */ |
b99bd4ef NC |
526 | #define MAX_LITTLENUMS 6 |
527 | ||
528 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
529 | ||
530 | #define FAIL (-1) | |
531 | #define SUCCESS (0) | |
532 | ||
533 | #define SUFF_S 1 | |
534 | #define SUFF_D 2 | |
535 | #define SUFF_E 3 | |
536 | #define SUFF_P 4 | |
537 | ||
c19d1205 ZW |
538 | #define CP_T_X 0x00008000 |
539 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 540 | |
c19d1205 ZW |
541 | #define CONDS_BIT 0x00100000 |
542 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
543 | |
544 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
545 | ||
546 | struct asm_cond | |
547 | { | |
d3ce72d0 | 548 | const char * template_name; |
c921be7d | 549 | unsigned long value; |
b99bd4ef NC |
550 | }; |
551 | ||
c19d1205 | 552 | #define COND_ALWAYS 0xE |
b99bd4ef | 553 | |
b99bd4ef NC |
554 | struct asm_psr |
555 | { | |
d3ce72d0 | 556 | const char * template_name; |
c921be7d | 557 | unsigned long field; |
b99bd4ef NC |
558 | }; |
559 | ||
62b3e311 PB |
560 | struct asm_barrier_opt |
561 | { | |
e797f7e0 MGD |
562 | const char * template_name; |
563 | unsigned long value; | |
564 | const arm_feature_set arch; | |
62b3e311 PB |
565 | }; |
566 | ||
2d2255b5 | 567 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
568 | #define SPSR_BIT (1 << 22) |
569 | ||
c19d1205 ZW |
570 | /* The individual PSR flag bits. */ |
571 | #define PSR_c (1 << 16) | |
572 | #define PSR_x (1 << 17) | |
573 | #define PSR_s (1 << 18) | |
574 | #define PSR_f (1 << 19) | |
b99bd4ef | 575 | |
c19d1205 | 576 | struct reloc_entry |
bfae80f2 | 577 | { |
0198d5e6 | 578 | const char * name; |
c921be7d | 579 | bfd_reloc_code_real_type reloc; |
bfae80f2 RE |
580 | }; |
581 | ||
5287ad62 | 582 | enum vfp_reg_pos |
bfae80f2 | 583 | { |
5287ad62 JB |
584 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, |
585 | VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn | |
bfae80f2 RE |
586 | }; |
587 | ||
588 | enum vfp_ldstm_type | |
589 | { | |
590 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
591 | }; | |
592 | ||
dcbf9037 JB |
593 | /* Bits for DEFINED field in neon_typed_alias. */ |
594 | #define NTA_HASTYPE 1 | |
595 | #define NTA_HASINDEX 2 | |
596 | ||
597 | struct neon_typed_alias | |
598 | { | |
c921be7d NC |
599 | unsigned char defined; |
600 | unsigned char index; | |
601 | struct neon_type_el eltype; | |
dcbf9037 JB |
602 | }; |
603 | ||
c19d1205 | 604 | /* ARM register categories. This includes coprocessor numbers and various |
5aa75429 TP |
605 | architecture extensions' registers. Each entry should have an error message |
606 | in reg_expected_msgs below. */ | |
c19d1205 | 607 | enum arm_reg_type |
bfae80f2 | 608 | { |
c19d1205 ZW |
609 | REG_TYPE_RN, |
610 | REG_TYPE_CP, | |
611 | REG_TYPE_CN, | |
612 | REG_TYPE_FN, | |
613 | REG_TYPE_VFS, | |
614 | REG_TYPE_VFD, | |
5287ad62 | 615 | REG_TYPE_NQ, |
037e8744 | 616 | REG_TYPE_VFSD, |
5287ad62 | 617 | REG_TYPE_NDQ, |
dec41383 | 618 | REG_TYPE_NSD, |
037e8744 | 619 | REG_TYPE_NSDQ, |
c19d1205 ZW |
620 | REG_TYPE_VFC, |
621 | REG_TYPE_MVF, | |
622 | REG_TYPE_MVD, | |
623 | REG_TYPE_MVFX, | |
624 | REG_TYPE_MVDX, | |
625 | REG_TYPE_MVAX, | |
626 | REG_TYPE_DSPSC, | |
627 | REG_TYPE_MMXWR, | |
628 | REG_TYPE_MMXWC, | |
629 | REG_TYPE_MMXWCG, | |
630 | REG_TYPE_XSCALE, | |
90ec0d68 | 631 | REG_TYPE_RNB |
bfae80f2 RE |
632 | }; |
633 | ||
dcbf9037 JB |
634 | /* Structure for a hash table entry for a register. |
635 | If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra | |
636 | information which states whether a vector type or index is specified (for a | |
637 | register alias created with .dn or .qn). Otherwise NEON should be NULL. */ | |
6c43fab6 RE |
638 | struct reg_entry |
639 | { | |
c921be7d | 640 | const char * name; |
90ec0d68 | 641 | unsigned int number; |
c921be7d NC |
642 | unsigned char type; |
643 | unsigned char builtin; | |
644 | struct neon_typed_alias * neon; | |
6c43fab6 RE |
645 | }; |
646 | ||
c19d1205 | 647 | /* Diagnostics used when we don't get a register of the expected type. */ |
c921be7d | 648 | const char * const reg_expected_msgs[] = |
c19d1205 | 649 | { |
5aa75429 TP |
650 | [REG_TYPE_RN] = N_("ARM register expected"), |
651 | [REG_TYPE_CP] = N_("bad or missing co-processor number"), | |
652 | [REG_TYPE_CN] = N_("co-processor register expected"), | |
653 | [REG_TYPE_FN] = N_("FPA register expected"), | |
654 | [REG_TYPE_VFS] = N_("VFP single precision register expected"), | |
655 | [REG_TYPE_VFD] = N_("VFP/Neon double precision register expected"), | |
656 | [REG_TYPE_NQ] = N_("Neon quad precision register expected"), | |
657 | [REG_TYPE_VFSD] = N_("VFP single or double precision register expected"), | |
658 | [REG_TYPE_NDQ] = N_("Neon double or quad precision register expected"), | |
659 | [REG_TYPE_NSD] = N_("Neon single or double precision register expected"), | |
660 | [REG_TYPE_NSDQ] = N_("VFP single, double or Neon quad precision register" | |
661 | " expected"), | |
662 | [REG_TYPE_VFC] = N_("VFP system register expected"), | |
663 | [REG_TYPE_MVF] = N_("Maverick MVF register expected"), | |
664 | [REG_TYPE_MVD] = N_("Maverick MVD register expected"), | |
665 | [REG_TYPE_MVFX] = N_("Maverick MVFX register expected"), | |
666 | [REG_TYPE_MVDX] = N_("Maverick MVDX register expected"), | |
667 | [REG_TYPE_MVAX] = N_("Maverick MVAX register expected"), | |
668 | [REG_TYPE_DSPSC] = N_("Maverick DSPSC register expected"), | |
669 | [REG_TYPE_MMXWR] = N_("iWMMXt data register expected"), | |
670 | [REG_TYPE_MMXWC] = N_("iWMMXt control register expected"), | |
671 | [REG_TYPE_MMXWCG] = N_("iWMMXt scalar register expected"), | |
672 | [REG_TYPE_XSCALE] = N_("XScale accumulator register expected"), | |
673 | [REG_TYPE_RNB] = N_("") | |
6c43fab6 RE |
674 | }; |
675 | ||
c19d1205 | 676 | /* Some well known registers that we refer to directly elsewhere. */ |
bd340a04 | 677 | #define REG_R12 12 |
c19d1205 ZW |
678 | #define REG_SP 13 |
679 | #define REG_LR 14 | |
680 | #define REG_PC 15 | |
404ff6b5 | 681 | |
b99bd4ef NC |
682 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
683 | take 2: */ | |
c19d1205 | 684 | #define INSN_SIZE 4 |
b99bd4ef NC |
685 | |
686 | struct asm_opcode | |
687 | { | |
688 | /* Basic string to match. */ | |
d3ce72d0 | 689 | const char * template_name; |
c19d1205 ZW |
690 | |
691 | /* Parameters to instruction. */ | |
5be8be5d | 692 | unsigned int operands[8]; |
c19d1205 ZW |
693 | |
694 | /* Conditional tag - see opcode_lookup. */ | |
695 | unsigned int tag : 4; | |
b99bd4ef NC |
696 | |
697 | /* Basic instruction code. */ | |
c19d1205 | 698 | unsigned int avalue : 28; |
b99bd4ef | 699 | |
c19d1205 ZW |
700 | /* Thumb-format instruction code. */ |
701 | unsigned int tvalue; | |
b99bd4ef | 702 | |
90e4755a | 703 | /* Which architecture variant provides this instruction. */ |
c921be7d NC |
704 | const arm_feature_set * avariant; |
705 | const arm_feature_set * tvariant; | |
c19d1205 ZW |
706 | |
707 | /* Function to call to encode instruction in ARM format. */ | |
708 | void (* aencode) (void); | |
b99bd4ef | 709 | |
c19d1205 ZW |
710 | /* Function to call to encode instruction in Thumb format. */ |
711 | void (* tencode) (void); | |
b99bd4ef NC |
712 | }; |
713 | ||
a737bd4d NC |
714 | /* Defines for various bits that we will want to toggle. */ |
715 | #define INST_IMMEDIATE 0x02000000 | |
716 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 717 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
718 | #define SHIFT_BY_REG 0x00000010 |
719 | #define PRE_INDEX 0x01000000 | |
720 | #define INDEX_UP 0x00800000 | |
721 | #define WRITE_BACK 0x00200000 | |
722 | #define LDM_TYPE_2_OR_3 0x00400000 | |
a028a6f5 | 723 | #define CPSI_MMOD 0x00020000 |
90e4755a | 724 | |
a737bd4d NC |
725 | #define LITERAL_MASK 0xf000f000 |
726 | #define OPCODE_MASK 0xfe1fffff | |
727 | #define V4_STR_BIT 0x00000020 | |
8335d6aa | 728 | #define VLDR_VMOV_SAME 0x0040f000 |
90e4755a | 729 | |
efd81785 PB |
730 | #define T2_SUBS_PC_LR 0xf3de8f00 |
731 | ||
a737bd4d | 732 | #define DATA_OP_SHIFT 21 |
bada4342 | 733 | #define SBIT_SHIFT 20 |
90e4755a | 734 | |
ef8d22e6 PB |
735 | #define T2_OPCODE_MASK 0xfe1fffff |
736 | #define T2_DATA_OP_SHIFT 21 | |
bada4342 | 737 | #define T2_SBIT_SHIFT 20 |
ef8d22e6 | 738 | |
6530b175 NC |
739 | #define A_COND_MASK 0xf0000000 |
740 | #define A_PUSH_POP_OP_MASK 0x0fff0000 | |
741 | ||
742 | /* Opcodes for pushing/poping registers to/from the stack. */ | |
743 | #define A1_OPCODE_PUSH 0x092d0000 | |
744 | #define A2_OPCODE_PUSH 0x052d0004 | |
745 | #define A2_OPCODE_POP 0x049d0004 | |
746 | ||
a737bd4d NC |
747 | /* Codes to distinguish the arithmetic instructions. */ |
748 | #define OPCODE_AND 0 | |
749 | #define OPCODE_EOR 1 | |
750 | #define OPCODE_SUB 2 | |
751 | #define OPCODE_RSB 3 | |
752 | #define OPCODE_ADD 4 | |
753 | #define OPCODE_ADC 5 | |
754 | #define OPCODE_SBC 6 | |
755 | #define OPCODE_RSC 7 | |
756 | #define OPCODE_TST 8 | |
757 | #define OPCODE_TEQ 9 | |
758 | #define OPCODE_CMP 10 | |
759 | #define OPCODE_CMN 11 | |
760 | #define OPCODE_ORR 12 | |
761 | #define OPCODE_MOV 13 | |
762 | #define OPCODE_BIC 14 | |
763 | #define OPCODE_MVN 15 | |
90e4755a | 764 | |
ef8d22e6 PB |
765 | #define T2_OPCODE_AND 0 |
766 | #define T2_OPCODE_BIC 1 | |
767 | #define T2_OPCODE_ORR 2 | |
768 | #define T2_OPCODE_ORN 3 | |
769 | #define T2_OPCODE_EOR 4 | |
770 | #define T2_OPCODE_ADD 8 | |
771 | #define T2_OPCODE_ADC 10 | |
772 | #define T2_OPCODE_SBC 11 | |
773 | #define T2_OPCODE_SUB 13 | |
774 | #define T2_OPCODE_RSB 14 | |
775 | ||
a737bd4d NC |
776 | #define T_OPCODE_MUL 0x4340 |
777 | #define T_OPCODE_TST 0x4200 | |
778 | #define T_OPCODE_CMN 0x42c0 | |
779 | #define T_OPCODE_NEG 0x4240 | |
780 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 781 | |
a737bd4d NC |
782 | #define T_OPCODE_ADD_R3 0x1800 |
783 | #define T_OPCODE_SUB_R3 0x1a00 | |
784 | #define T_OPCODE_ADD_HI 0x4400 | |
785 | #define T_OPCODE_ADD_ST 0xb000 | |
786 | #define T_OPCODE_SUB_ST 0xb080 | |
787 | #define T_OPCODE_ADD_SP 0xa800 | |
788 | #define T_OPCODE_ADD_PC 0xa000 | |
789 | #define T_OPCODE_ADD_I8 0x3000 | |
790 | #define T_OPCODE_SUB_I8 0x3800 | |
791 | #define T_OPCODE_ADD_I3 0x1c00 | |
792 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 793 | |
a737bd4d NC |
794 | #define T_OPCODE_ASR_R 0x4100 |
795 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
796 | #define T_OPCODE_LSR_R 0x40c0 |
797 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
798 | #define T_OPCODE_ASR_I 0x1000 |
799 | #define T_OPCODE_LSL_I 0x0000 | |
800 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 801 | |
a737bd4d NC |
802 | #define T_OPCODE_MOV_I8 0x2000 |
803 | #define T_OPCODE_CMP_I8 0x2800 | |
804 | #define T_OPCODE_CMP_LR 0x4280 | |
805 | #define T_OPCODE_MOV_HR 0x4600 | |
806 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 807 | |
a737bd4d NC |
808 | #define T_OPCODE_LDR_PC 0x4800 |
809 | #define T_OPCODE_LDR_SP 0x9800 | |
810 | #define T_OPCODE_STR_SP 0x9000 | |
811 | #define T_OPCODE_LDR_IW 0x6800 | |
812 | #define T_OPCODE_STR_IW 0x6000 | |
813 | #define T_OPCODE_LDR_IH 0x8800 | |
814 | #define T_OPCODE_STR_IH 0x8000 | |
815 | #define T_OPCODE_LDR_IB 0x7800 | |
816 | #define T_OPCODE_STR_IB 0x7000 | |
817 | #define T_OPCODE_LDR_RW 0x5800 | |
818 | #define T_OPCODE_STR_RW 0x5000 | |
819 | #define T_OPCODE_LDR_RH 0x5a00 | |
820 | #define T_OPCODE_STR_RH 0x5200 | |
821 | #define T_OPCODE_LDR_RB 0x5c00 | |
822 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 823 | |
a737bd4d NC |
824 | #define T_OPCODE_PUSH 0xb400 |
825 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 826 | |
2fc8bdac | 827 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 828 | |
a737bd4d | 829 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 830 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 | 831 | #define THUMB_LOAD_BIT 0x0800 |
53365c0d | 832 | #define THUMB2_LOAD_BIT 0x00100000 |
c19d1205 ZW |
833 | |
834 | #define BAD_ARGS _("bad arguments to instruction") | |
fdfde340 | 835 | #define BAD_SP _("r13 not allowed here") |
c19d1205 ZW |
836 | #define BAD_PC _("r15 not allowed here") |
837 | #define BAD_COND _("instruction cannot be conditional") | |
838 | #define BAD_OVERLAP _("registers may not be the same") | |
839 | #define BAD_HIREG _("lo register required") | |
840 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
01cfc07f | 841 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); |
dfa9f0d5 PB |
842 | #define BAD_BRANCH _("branch must be last instruction in IT block") |
843 | #define BAD_NOT_IT _("instruction not allowed in IT block") | |
037e8744 | 844 | #define BAD_FPU _("selected FPU does not support instruction") |
e07e6e58 NC |
845 | #define BAD_OUT_IT _("thumb conditional instruction should be in IT block") |
846 | #define BAD_IT_COND _("incorrect condition in IT block") | |
847 | #define BAD_IT_IT _("IT falling in the range of a previous IT block") | |
921e5f0a | 848 | #define MISSING_FNSTART _("missing .fnstart before unwinding directive") |
5be8be5d DG |
849 | #define BAD_PC_ADDRESSING \ |
850 | _("cannot use register index with PC-relative addressing") | |
851 | #define BAD_PC_WRITEBACK \ | |
852 | _("cannot use writeback with PC-relative addressing") | |
9db2f6b4 RL |
853 | #define BAD_RANGE _("branch out of range") |
854 | #define BAD_FP16 _("selected processor does not support fp16 instruction") | |
dd5181d5 | 855 | #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour") |
a9f02af8 | 856 | #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only") |
c19d1205 | 857 | |
c921be7d NC |
858 | static struct hash_control * arm_ops_hsh; |
859 | static struct hash_control * arm_cond_hsh; | |
860 | static struct hash_control * arm_shift_hsh; | |
861 | static struct hash_control * arm_psr_hsh; | |
862 | static struct hash_control * arm_v7m_psr_hsh; | |
863 | static struct hash_control * arm_reg_hsh; | |
864 | static struct hash_control * arm_reloc_hsh; | |
865 | static struct hash_control * arm_barrier_opt_hsh; | |
b99bd4ef | 866 | |
b99bd4ef NC |
867 | /* Stuff needed to resolve the label ambiguity |
868 | As: | |
869 | ... | |
870 | label: <insn> | |
871 | may differ from: | |
872 | ... | |
873 | label: | |
5f4273c7 | 874 | <insn> */ |
b99bd4ef NC |
875 | |
876 | symbolS * last_label_seen; | |
b34976b6 | 877 | static int label_is_thumb_function_name = FALSE; |
e07e6e58 | 878 | |
3d0c9500 NC |
879 | /* Literal pool structure. Held on a per-section |
880 | and per-sub-section basis. */ | |
a737bd4d | 881 | |
c19d1205 | 882 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 883 | typedef struct literal_pool |
b99bd4ef | 884 | { |
c921be7d NC |
885 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
886 | unsigned int next_free_entry; | |
887 | unsigned int id; | |
888 | symbolS * symbol; | |
889 | segT section; | |
890 | subsegT sub_section; | |
a8040cf2 NC |
891 | #ifdef OBJ_ELF |
892 | struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE]; | |
893 | #endif | |
c921be7d | 894 | struct literal_pool * next; |
8335d6aa | 895 | unsigned int alignment; |
3d0c9500 | 896 | } literal_pool; |
b99bd4ef | 897 | |
3d0c9500 NC |
898 | /* Pointer to a linked list of literal pools. */ |
899 | literal_pool * list_of_pools = NULL; | |
e27ec89e | 900 | |
2e6976a8 DG |
901 | typedef enum asmfunc_states |
902 | { | |
903 | OUTSIDE_ASMFUNC, | |
904 | WAITING_ASMFUNC_NAME, | |
905 | WAITING_ENDASMFUNC | |
906 | } asmfunc_states; | |
907 | ||
908 | static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC; | |
909 | ||
e07e6e58 NC |
910 | #ifdef OBJ_ELF |
911 | # define now_it seg_info (now_seg)->tc_segment_info_data.current_it | |
912 | #else | |
913 | static struct current_it now_it; | |
914 | #endif | |
915 | ||
916 | static inline int | |
917 | now_it_compatible (int cond) | |
918 | { | |
919 | return (cond & ~1) == (now_it.cc & ~1); | |
920 | } | |
921 | ||
922 | static inline int | |
923 | conditional_insn (void) | |
924 | { | |
925 | return inst.cond != COND_ALWAYS; | |
926 | } | |
927 | ||
928 | static int in_it_block (void); | |
929 | ||
930 | static int handle_it_state (void); | |
931 | ||
932 | static void force_automatic_it_block_close (void); | |
933 | ||
c921be7d NC |
934 | static void it_fsm_post_encode (void); |
935 | ||
e07e6e58 NC |
936 | #define set_it_insn_type(type) \ |
937 | do \ | |
938 | { \ | |
939 | inst.it_insn_type = type; \ | |
940 | if (handle_it_state () == FAIL) \ | |
477330fc | 941 | return; \ |
e07e6e58 NC |
942 | } \ |
943 | while (0) | |
944 | ||
c921be7d NC |
945 | #define set_it_insn_type_nonvoid(type, failret) \ |
946 | do \ | |
947 | { \ | |
948 | inst.it_insn_type = type; \ | |
949 | if (handle_it_state () == FAIL) \ | |
477330fc | 950 | return failret; \ |
c921be7d NC |
951 | } \ |
952 | while(0) | |
953 | ||
e07e6e58 NC |
954 | #define set_it_insn_type_last() \ |
955 | do \ | |
956 | { \ | |
957 | if (inst.cond == COND_ALWAYS) \ | |
477330fc | 958 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \ |
e07e6e58 | 959 | else \ |
477330fc | 960 | set_it_insn_type (INSIDE_IT_LAST_INSN); \ |
e07e6e58 NC |
961 | } \ |
962 | while (0) | |
963 | ||
c19d1205 | 964 | /* Pure syntax. */ |
b99bd4ef | 965 | |
c19d1205 ZW |
966 | /* This array holds the chars that always start a comment. If the |
967 | pre-processor is disabled, these aren't very useful. */ | |
2e6976a8 | 968 | char arm_comment_chars[] = "@"; |
3d0c9500 | 969 | |
c19d1205 ZW |
970 | /* This array holds the chars that only start a comment at the beginning of |
971 | a line. If the line seems to have the form '# 123 filename' | |
972 | .line and .file directives will appear in the pre-processed output. */ | |
973 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
974 | first line of the input file. This is because the compiler outputs | |
975 | #NO_APP at the beginning of its output. */ | |
976 | /* Also note that comments like this one will always work. */ | |
977 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 978 | |
2e6976a8 | 979 | char arm_line_separator_chars[] = ";"; |
b99bd4ef | 980 | |
c19d1205 ZW |
981 | /* Chars that can be used to separate mant |
982 | from exp in floating point numbers. */ | |
983 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 984 | |
c19d1205 ZW |
985 | /* Chars that mean this number is a floating point constant. */ |
986 | /* As in 0f12.456 */ | |
987 | /* or 0d1.2345e12 */ | |
b99bd4ef | 988 | |
c19d1205 | 989 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 990 | |
c19d1205 ZW |
991 | /* Prefix characters that indicate the start of an immediate |
992 | value. */ | |
993 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 994 | |
c19d1205 ZW |
995 | /* Separator character handling. */ |
996 | ||
997 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
998 | ||
999 | static inline int | |
1000 | skip_past_char (char ** str, char c) | |
1001 | { | |
8ab8155f NC |
1002 | /* PR gas/14987: Allow for whitespace before the expected character. */ |
1003 | skip_whitespace (*str); | |
427d0db6 | 1004 | |
c19d1205 ZW |
1005 | if (**str == c) |
1006 | { | |
1007 | (*str)++; | |
1008 | return SUCCESS; | |
3d0c9500 | 1009 | } |
c19d1205 ZW |
1010 | else |
1011 | return FAIL; | |
1012 | } | |
c921be7d | 1013 | |
c19d1205 | 1014 | #define skip_past_comma(str) skip_past_char (str, ',') |
3d0c9500 | 1015 | |
c19d1205 ZW |
1016 | /* Arithmetic expressions (possibly involving symbols). */ |
1017 | ||
1018 | /* Return TRUE if anything in the expression is a bignum. */ | |
1019 | ||
0198d5e6 | 1020 | static bfd_boolean |
c19d1205 ZW |
1021 | walk_no_bignums (symbolS * sp) |
1022 | { | |
1023 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
0198d5e6 | 1024 | return TRUE; |
c19d1205 ZW |
1025 | |
1026 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 1027 | { |
c19d1205 ZW |
1028 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
1029 | || (symbol_get_value_expression (sp)->X_op_symbol | |
1030 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
1031 | } |
1032 | ||
0198d5e6 | 1033 | return FALSE; |
3d0c9500 NC |
1034 | } |
1035 | ||
0198d5e6 | 1036 | static bfd_boolean in_my_get_expression = FALSE; |
c19d1205 ZW |
1037 | |
1038 | /* Third argument to my_get_expression. */ | |
1039 | #define GE_NO_PREFIX 0 | |
1040 | #define GE_IMM_PREFIX 1 | |
1041 | #define GE_OPT_PREFIX 2 | |
5287ad62 JB |
1042 | /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) |
1043 | immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ | |
1044 | #define GE_OPT_PREFIX_BIG 3 | |
a737bd4d | 1045 | |
b99bd4ef | 1046 | static int |
c19d1205 | 1047 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 1048 | { |
c19d1205 | 1049 | char * save_in; |
b99bd4ef | 1050 | |
c19d1205 ZW |
1051 | /* In unified syntax, all prefixes are optional. */ |
1052 | if (unified_syntax) | |
5287ad62 | 1053 | prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode |
477330fc | 1054 | : GE_OPT_PREFIX; |
b99bd4ef | 1055 | |
c19d1205 | 1056 | switch (prefix_mode) |
b99bd4ef | 1057 | { |
c19d1205 ZW |
1058 | case GE_NO_PREFIX: break; |
1059 | case GE_IMM_PREFIX: | |
1060 | if (!is_immediate_prefix (**str)) | |
1061 | { | |
1062 | inst.error = _("immediate expression requires a # prefix"); | |
1063 | return FAIL; | |
1064 | } | |
1065 | (*str)++; | |
1066 | break; | |
1067 | case GE_OPT_PREFIX: | |
5287ad62 | 1068 | case GE_OPT_PREFIX_BIG: |
c19d1205 ZW |
1069 | if (is_immediate_prefix (**str)) |
1070 | (*str)++; | |
1071 | break; | |
0198d5e6 TC |
1072 | default: |
1073 | abort (); | |
c19d1205 | 1074 | } |
b99bd4ef | 1075 | |
c19d1205 | 1076 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 1077 | |
c19d1205 ZW |
1078 | save_in = input_line_pointer; |
1079 | input_line_pointer = *str; | |
0198d5e6 | 1080 | in_my_get_expression = TRUE; |
2ac93be7 | 1081 | expression (ep); |
0198d5e6 | 1082 | in_my_get_expression = FALSE; |
c19d1205 | 1083 | |
f86adc07 | 1084 | if (ep->X_op == O_illegal || ep->X_op == O_absent) |
b99bd4ef | 1085 | { |
f86adc07 | 1086 | /* We found a bad or missing expression in md_operand(). */ |
c19d1205 ZW |
1087 | *str = input_line_pointer; |
1088 | input_line_pointer = save_in; | |
1089 | if (inst.error == NULL) | |
f86adc07 NS |
1090 | inst.error = (ep->X_op == O_absent |
1091 | ? _("missing expression") :_("bad expression")); | |
c19d1205 ZW |
1092 | return 1; |
1093 | } | |
b99bd4ef | 1094 | |
c19d1205 ZW |
1095 | /* Get rid of any bignums now, so that we don't generate an error for which |
1096 | we can't establish a line number later on. Big numbers are never valid | |
1097 | in instructions, which is where this routine is always called. */ | |
5287ad62 JB |
1098 | if (prefix_mode != GE_OPT_PREFIX_BIG |
1099 | && (ep->X_op == O_big | |
477330fc | 1100 | || (ep->X_add_symbol |
5287ad62 | 1101 | && (walk_no_bignums (ep->X_add_symbol) |
477330fc | 1102 | || (ep->X_op_symbol |
5287ad62 | 1103 | && walk_no_bignums (ep->X_op_symbol)))))) |
c19d1205 ZW |
1104 | { |
1105 | inst.error = _("invalid constant"); | |
1106 | *str = input_line_pointer; | |
1107 | input_line_pointer = save_in; | |
1108 | return 1; | |
1109 | } | |
b99bd4ef | 1110 | |
c19d1205 ZW |
1111 | *str = input_line_pointer; |
1112 | input_line_pointer = save_in; | |
0198d5e6 | 1113 | return SUCCESS; |
b99bd4ef NC |
1114 | } |
1115 | ||
c19d1205 ZW |
1116 | /* Turn a string in input_line_pointer into a floating point constant |
1117 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
1118 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
1119 | returned, or NULL on OK. | |
b99bd4ef | 1120 | |
c19d1205 ZW |
1121 | Note that fp constants aren't represent in the normal way on the ARM. |
1122 | In big endian mode, things are as expected. However, in little endian | |
1123 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
1124 | within the words. For example, (double) 1.1 in big endian mode is | |
1125 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
1126 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 1127 | |
c19d1205 | 1128 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 1129 | |
6d4af3c2 | 1130 | const char * |
c19d1205 ZW |
1131 | md_atof (int type, char * litP, int * sizeP) |
1132 | { | |
1133 | int prec; | |
1134 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
1135 | char *t; | |
1136 | int i; | |
b99bd4ef | 1137 | |
c19d1205 ZW |
1138 | switch (type) |
1139 | { | |
1140 | case 'f': | |
1141 | case 'F': | |
1142 | case 's': | |
1143 | case 'S': | |
1144 | prec = 2; | |
1145 | break; | |
b99bd4ef | 1146 | |
c19d1205 ZW |
1147 | case 'd': |
1148 | case 'D': | |
1149 | case 'r': | |
1150 | case 'R': | |
1151 | prec = 4; | |
1152 | break; | |
b99bd4ef | 1153 | |
c19d1205 ZW |
1154 | case 'x': |
1155 | case 'X': | |
499ac353 | 1156 | prec = 5; |
c19d1205 | 1157 | break; |
b99bd4ef | 1158 | |
c19d1205 ZW |
1159 | case 'p': |
1160 | case 'P': | |
499ac353 | 1161 | prec = 5; |
c19d1205 | 1162 | break; |
a737bd4d | 1163 | |
c19d1205 ZW |
1164 | default: |
1165 | *sizeP = 0; | |
499ac353 | 1166 | return _("Unrecognized or unsupported floating point constant"); |
c19d1205 | 1167 | } |
b99bd4ef | 1168 | |
c19d1205 ZW |
1169 | t = atof_ieee (input_line_pointer, type, words); |
1170 | if (t) | |
1171 | input_line_pointer = t; | |
499ac353 | 1172 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
b99bd4ef | 1173 | |
c19d1205 ZW |
1174 | if (target_big_endian) |
1175 | { | |
1176 | for (i = 0; i < prec; i++) | |
1177 | { | |
499ac353 NC |
1178 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1179 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1180 | } |
1181 | } | |
1182 | else | |
1183 | { | |
e74cfd16 | 1184 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
c19d1205 ZW |
1185 | for (i = prec - 1; i >= 0; i--) |
1186 | { | |
499ac353 NC |
1187 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1188 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1189 | } |
1190 | else | |
1191 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
1192 | For an 8 byte float the order is 1 0 3 2. */ | |
1193 | for (i = 0; i < prec; i += 2) | |
1194 | { | |
499ac353 NC |
1195 | md_number_to_chars (litP, (valueT) words[i + 1], |
1196 | sizeof (LITTLENUM_TYPE)); | |
1197 | md_number_to_chars (litP + sizeof (LITTLENUM_TYPE), | |
1198 | (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
1199 | litP += 2 * sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1200 | } |
1201 | } | |
b99bd4ef | 1202 | |
499ac353 | 1203 | return NULL; |
c19d1205 | 1204 | } |
b99bd4ef | 1205 | |
c19d1205 ZW |
1206 | /* We handle all bad expressions here, so that we can report the faulty |
1207 | instruction in the error message. */ | |
0198d5e6 | 1208 | |
c19d1205 | 1209 | void |
91d6fa6a | 1210 | md_operand (expressionS * exp) |
c19d1205 ZW |
1211 | { |
1212 | if (in_my_get_expression) | |
91d6fa6a | 1213 | exp->X_op = O_illegal; |
b99bd4ef NC |
1214 | } |
1215 | ||
c19d1205 | 1216 | /* Immediate values. */ |
b99bd4ef | 1217 | |
0198d5e6 | 1218 | #ifdef OBJ_ELF |
c19d1205 ZW |
1219 | /* Generic immediate-value read function for use in directives. |
1220 | Accepts anything that 'expression' can fold to a constant. | |
1221 | *val receives the number. */ | |
0198d5e6 | 1222 | |
c19d1205 ZW |
1223 | static int |
1224 | immediate_for_directive (int *val) | |
b99bd4ef | 1225 | { |
c19d1205 ZW |
1226 | expressionS exp; |
1227 | exp.X_op = O_illegal; | |
b99bd4ef | 1228 | |
c19d1205 ZW |
1229 | if (is_immediate_prefix (*input_line_pointer)) |
1230 | { | |
1231 | input_line_pointer++; | |
1232 | expression (&exp); | |
1233 | } | |
b99bd4ef | 1234 | |
c19d1205 ZW |
1235 | if (exp.X_op != O_constant) |
1236 | { | |
1237 | as_bad (_("expected #constant")); | |
1238 | ignore_rest_of_line (); | |
1239 | return FAIL; | |
1240 | } | |
1241 | *val = exp.X_add_number; | |
1242 | return SUCCESS; | |
b99bd4ef | 1243 | } |
c19d1205 | 1244 | #endif |
b99bd4ef | 1245 | |
c19d1205 | 1246 | /* Register parsing. */ |
b99bd4ef | 1247 | |
c19d1205 ZW |
1248 | /* Generic register parser. CCP points to what should be the |
1249 | beginning of a register name. If it is indeed a valid register | |
1250 | name, advance CCP over it and return the reg_entry structure; | |
1251 | otherwise return NULL. Does not issue diagnostics. */ | |
1252 | ||
1253 | static struct reg_entry * | |
1254 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 1255 | { |
c19d1205 ZW |
1256 | char *start = *ccp; |
1257 | char *p; | |
1258 | struct reg_entry *reg; | |
b99bd4ef | 1259 | |
477330fc RM |
1260 | skip_whitespace (start); |
1261 | ||
c19d1205 ZW |
1262 | #ifdef REGISTER_PREFIX |
1263 | if (*start != REGISTER_PREFIX) | |
01cfc07f | 1264 | return NULL; |
c19d1205 ZW |
1265 | start++; |
1266 | #endif | |
1267 | #ifdef OPTIONAL_REGISTER_PREFIX | |
1268 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
1269 | start++; | |
1270 | #endif | |
b99bd4ef | 1271 | |
c19d1205 ZW |
1272 | p = start; |
1273 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
1274 | return NULL; | |
b99bd4ef | 1275 | |
c19d1205 ZW |
1276 | do |
1277 | p++; | |
1278 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
1279 | ||
1280 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
1281 | ||
1282 | if (!reg) | |
1283 | return NULL; | |
1284 | ||
1285 | *ccp = p; | |
1286 | return reg; | |
b99bd4ef NC |
1287 | } |
1288 | ||
1289 | static int | |
dcbf9037 | 1290 | arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, |
477330fc | 1291 | enum arm_reg_type type) |
b99bd4ef | 1292 | { |
c19d1205 ZW |
1293 | /* Alternative syntaxes are accepted for a few register classes. */ |
1294 | switch (type) | |
1295 | { | |
1296 | case REG_TYPE_MVF: | |
1297 | case REG_TYPE_MVD: | |
1298 | case REG_TYPE_MVFX: | |
1299 | case REG_TYPE_MVDX: | |
1300 | /* Generic coprocessor register names are allowed for these. */ | |
79134647 | 1301 | if (reg && reg->type == REG_TYPE_CN) |
c19d1205 ZW |
1302 | return reg->number; |
1303 | break; | |
69b97547 | 1304 | |
c19d1205 ZW |
1305 | case REG_TYPE_CP: |
1306 | /* For backward compatibility, a bare number is valid here. */ | |
1307 | { | |
1308 | unsigned long processor = strtoul (start, ccp, 10); | |
1309 | if (*ccp != start && processor <= 15) | |
1310 | return processor; | |
1311 | } | |
1a0670f3 | 1312 | /* Fall through. */ |
6057a28f | 1313 | |
c19d1205 ZW |
1314 | case REG_TYPE_MMXWC: |
1315 | /* WC includes WCG. ??? I'm not sure this is true for all | |
1316 | instructions that take WC registers. */ | |
79134647 | 1317 | if (reg && reg->type == REG_TYPE_MMXWCG) |
c19d1205 | 1318 | return reg->number; |
6057a28f | 1319 | break; |
c19d1205 | 1320 | |
6057a28f | 1321 | default: |
c19d1205 | 1322 | break; |
6057a28f NC |
1323 | } |
1324 | ||
dcbf9037 JB |
1325 | return FAIL; |
1326 | } | |
1327 | ||
1328 | /* As arm_reg_parse_multi, but the register must be of type TYPE, and the | |
1329 | return value is the register number or FAIL. */ | |
1330 | ||
1331 | static int | |
1332 | arm_reg_parse (char **ccp, enum arm_reg_type type) | |
1333 | { | |
1334 | char *start = *ccp; | |
1335 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
1336 | int ret; | |
1337 | ||
1338 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1339 | if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) | |
1340 | return FAIL; | |
1341 | ||
1342 | if (reg && reg->type == type) | |
1343 | return reg->number; | |
1344 | ||
1345 | if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) | |
1346 | return ret; | |
1347 | ||
c19d1205 ZW |
1348 | *ccp = start; |
1349 | return FAIL; | |
1350 | } | |
69b97547 | 1351 | |
dcbf9037 JB |
1352 | /* Parse a Neon type specifier. *STR should point at the leading '.' |
1353 | character. Does no verification at this stage that the type fits the opcode | |
1354 | properly. E.g., | |
1355 | ||
1356 | .i32.i32.s16 | |
1357 | .s32.f32 | |
1358 | .u16 | |
1359 | ||
1360 | Can all be legally parsed by this function. | |
1361 | ||
1362 | Fills in neon_type struct pointer with parsed information, and updates STR | |
1363 | to point after the parsed type specifier. Returns SUCCESS if this was a legal | |
1364 | type, FAIL if not. */ | |
1365 | ||
1366 | static int | |
1367 | parse_neon_type (struct neon_type *type, char **str) | |
1368 | { | |
1369 | char *ptr = *str; | |
1370 | ||
1371 | if (type) | |
1372 | type->elems = 0; | |
1373 | ||
1374 | while (type->elems < NEON_MAX_TYPE_ELS) | |
1375 | { | |
1376 | enum neon_el_type thistype = NT_untyped; | |
1377 | unsigned thissize = -1u; | |
1378 | ||
1379 | if (*ptr != '.') | |
1380 | break; | |
1381 | ||
1382 | ptr++; | |
1383 | ||
1384 | /* Just a size without an explicit type. */ | |
1385 | if (ISDIGIT (*ptr)) | |
1386 | goto parsesize; | |
1387 | ||
1388 | switch (TOLOWER (*ptr)) | |
1389 | { | |
1390 | case 'i': thistype = NT_integer; break; | |
1391 | case 'f': thistype = NT_float; break; | |
1392 | case 'p': thistype = NT_poly; break; | |
1393 | case 's': thistype = NT_signed; break; | |
1394 | case 'u': thistype = NT_unsigned; break; | |
477330fc RM |
1395 | case 'd': |
1396 | thistype = NT_float; | |
1397 | thissize = 64; | |
1398 | ptr++; | |
1399 | goto done; | |
dcbf9037 JB |
1400 | default: |
1401 | as_bad (_("unexpected character `%c' in type specifier"), *ptr); | |
1402 | return FAIL; | |
1403 | } | |
1404 | ||
1405 | ptr++; | |
1406 | ||
1407 | /* .f is an abbreviation for .f32. */ | |
1408 | if (thistype == NT_float && !ISDIGIT (*ptr)) | |
1409 | thissize = 32; | |
1410 | else | |
1411 | { | |
1412 | parsesize: | |
1413 | thissize = strtoul (ptr, &ptr, 10); | |
1414 | ||
1415 | if (thissize != 8 && thissize != 16 && thissize != 32 | |
477330fc RM |
1416 | && thissize != 64) |
1417 | { | |
1418 | as_bad (_("bad size %d in type specifier"), thissize); | |
dcbf9037 JB |
1419 | return FAIL; |
1420 | } | |
1421 | } | |
1422 | ||
037e8744 | 1423 | done: |
dcbf9037 | 1424 | if (type) |
477330fc RM |
1425 | { |
1426 | type->el[type->elems].type = thistype; | |
dcbf9037 JB |
1427 | type->el[type->elems].size = thissize; |
1428 | type->elems++; | |
1429 | } | |
1430 | } | |
1431 | ||
1432 | /* Empty/missing type is not a successful parse. */ | |
1433 | if (type->elems == 0) | |
1434 | return FAIL; | |
1435 | ||
1436 | *str = ptr; | |
1437 | ||
1438 | return SUCCESS; | |
1439 | } | |
1440 | ||
1441 | /* Errors may be set multiple times during parsing or bit encoding | |
1442 | (particularly in the Neon bits), but usually the earliest error which is set | |
1443 | will be the most meaningful. Avoid overwriting it with later (cascading) | |
1444 | errors by calling this function. */ | |
1445 | ||
1446 | static void | |
1447 | first_error (const char *err) | |
1448 | { | |
1449 | if (!inst.error) | |
1450 | inst.error = err; | |
1451 | } | |
1452 | ||
1453 | /* Parse a single type, e.g. ".s32", leading period included. */ | |
1454 | static int | |
1455 | parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) | |
1456 | { | |
1457 | char *str = *ccp; | |
1458 | struct neon_type optype; | |
1459 | ||
1460 | if (*str == '.') | |
1461 | { | |
1462 | if (parse_neon_type (&optype, &str) == SUCCESS) | |
477330fc RM |
1463 | { |
1464 | if (optype.elems == 1) | |
1465 | *vectype = optype.el[0]; | |
1466 | else | |
1467 | { | |
1468 | first_error (_("only one type should be specified for operand")); | |
1469 | return FAIL; | |
1470 | } | |
1471 | } | |
dcbf9037 | 1472 | else |
477330fc RM |
1473 | { |
1474 | first_error (_("vector type expected")); | |
1475 | return FAIL; | |
1476 | } | |
dcbf9037 JB |
1477 | } |
1478 | else | |
1479 | return FAIL; | |
5f4273c7 | 1480 | |
dcbf9037 | 1481 | *ccp = str; |
5f4273c7 | 1482 | |
dcbf9037 JB |
1483 | return SUCCESS; |
1484 | } | |
1485 | ||
1486 | /* Special meanings for indices (which have a range of 0-7), which will fit into | |
1487 | a 4-bit integer. */ | |
1488 | ||
1489 | #define NEON_ALL_LANES 15 | |
1490 | #define NEON_INTERLEAVE_LANES 14 | |
1491 | ||
1492 | /* Parse either a register or a scalar, with an optional type. Return the | |
1493 | register number, and optionally fill in the actual type of the register | |
1494 | when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and | |
1495 | type/index information in *TYPEINFO. */ | |
1496 | ||
1497 | static int | |
1498 | parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, | |
477330fc RM |
1499 | enum arm_reg_type *rtype, |
1500 | struct neon_typed_alias *typeinfo) | |
dcbf9037 JB |
1501 | { |
1502 | char *str = *ccp; | |
1503 | struct reg_entry *reg = arm_reg_parse_multi (&str); | |
1504 | struct neon_typed_alias atype; | |
1505 | struct neon_type_el parsetype; | |
1506 | ||
1507 | atype.defined = 0; | |
1508 | atype.index = -1; | |
1509 | atype.eltype.type = NT_invtype; | |
1510 | atype.eltype.size = -1; | |
1511 | ||
1512 | /* Try alternate syntax for some types of register. Note these are mutually | |
1513 | exclusive with the Neon syntax extensions. */ | |
1514 | if (reg == NULL) | |
1515 | { | |
1516 | int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); | |
1517 | if (altreg != FAIL) | |
477330fc | 1518 | *ccp = str; |
dcbf9037 | 1519 | if (typeinfo) |
477330fc | 1520 | *typeinfo = atype; |
dcbf9037 JB |
1521 | return altreg; |
1522 | } | |
1523 | ||
037e8744 JB |
1524 | /* Undo polymorphism when a set of register types may be accepted. */ |
1525 | if ((type == REG_TYPE_NDQ | |
1526 | && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) | |
1527 | || (type == REG_TYPE_VFSD | |
477330fc | 1528 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) |
037e8744 | 1529 | || (type == REG_TYPE_NSDQ |
477330fc RM |
1530 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD |
1531 | || reg->type == REG_TYPE_NQ)) | |
dec41383 JW |
1532 | || (type == REG_TYPE_NSD |
1533 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) | |
f512f76f NC |
1534 | || (type == REG_TYPE_MMXWC |
1535 | && (reg->type == REG_TYPE_MMXWCG))) | |
21d799b5 | 1536 | type = (enum arm_reg_type) reg->type; |
dcbf9037 JB |
1537 | |
1538 | if (type != reg->type) | |
1539 | return FAIL; | |
1540 | ||
1541 | if (reg->neon) | |
1542 | atype = *reg->neon; | |
5f4273c7 | 1543 | |
dcbf9037 JB |
1544 | if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) |
1545 | { | |
1546 | if ((atype.defined & NTA_HASTYPE) != 0) | |
477330fc RM |
1547 | { |
1548 | first_error (_("can't redefine type for operand")); | |
1549 | return FAIL; | |
1550 | } | |
dcbf9037 JB |
1551 | atype.defined |= NTA_HASTYPE; |
1552 | atype.eltype = parsetype; | |
1553 | } | |
5f4273c7 | 1554 | |
dcbf9037 JB |
1555 | if (skip_past_char (&str, '[') == SUCCESS) |
1556 | { | |
dec41383 JW |
1557 | if (type != REG_TYPE_VFD |
1558 | && !(type == REG_TYPE_VFS | |
1559 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_2))) | |
477330fc RM |
1560 | { |
1561 | first_error (_("only D registers may be indexed")); | |
1562 | return FAIL; | |
1563 | } | |
5f4273c7 | 1564 | |
dcbf9037 | 1565 | if ((atype.defined & NTA_HASINDEX) != 0) |
477330fc RM |
1566 | { |
1567 | first_error (_("can't change index for operand")); | |
1568 | return FAIL; | |
1569 | } | |
dcbf9037 JB |
1570 | |
1571 | atype.defined |= NTA_HASINDEX; | |
1572 | ||
1573 | if (skip_past_char (&str, ']') == SUCCESS) | |
477330fc | 1574 | atype.index = NEON_ALL_LANES; |
dcbf9037 | 1575 | else |
477330fc RM |
1576 | { |
1577 | expressionS exp; | |
dcbf9037 | 1578 | |
477330fc | 1579 | my_get_expression (&exp, &str, GE_NO_PREFIX); |
dcbf9037 | 1580 | |
477330fc RM |
1581 | if (exp.X_op != O_constant) |
1582 | { | |
1583 | first_error (_("constant expression required")); | |
1584 | return FAIL; | |
1585 | } | |
dcbf9037 | 1586 | |
477330fc RM |
1587 | if (skip_past_char (&str, ']') == FAIL) |
1588 | return FAIL; | |
dcbf9037 | 1589 | |
477330fc RM |
1590 | atype.index = exp.X_add_number; |
1591 | } | |
dcbf9037 | 1592 | } |
5f4273c7 | 1593 | |
dcbf9037 JB |
1594 | if (typeinfo) |
1595 | *typeinfo = atype; | |
5f4273c7 | 1596 | |
dcbf9037 JB |
1597 | if (rtype) |
1598 | *rtype = type; | |
5f4273c7 | 1599 | |
dcbf9037 | 1600 | *ccp = str; |
5f4273c7 | 1601 | |
dcbf9037 JB |
1602 | return reg->number; |
1603 | } | |
1604 | ||
1605 | /* Like arm_reg_parse, but allow allow the following extra features: | |
1606 | - If RTYPE is non-zero, return the (possibly restricted) type of the | |
1607 | register (e.g. Neon double or quad reg when either has been requested). | |
1608 | - If this is a Neon vector type with additional type information, fill | |
1609 | in the struct pointed to by VECTYPE (if non-NULL). | |
5f4273c7 | 1610 | This function will fault on encountering a scalar. */ |
dcbf9037 JB |
1611 | |
1612 | static int | |
1613 | arm_typed_reg_parse (char **ccp, enum arm_reg_type type, | |
477330fc | 1614 | enum arm_reg_type *rtype, struct neon_type_el *vectype) |
dcbf9037 JB |
1615 | { |
1616 | struct neon_typed_alias atype; | |
1617 | char *str = *ccp; | |
1618 | int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); | |
1619 | ||
1620 | if (reg == FAIL) | |
1621 | return FAIL; | |
1622 | ||
0855e32b NS |
1623 | /* Do not allow regname(... to parse as a register. */ |
1624 | if (*str == '(') | |
1625 | return FAIL; | |
1626 | ||
dcbf9037 JB |
1627 | /* Do not allow a scalar (reg+index) to parse as a register. */ |
1628 | if ((atype.defined & NTA_HASINDEX) != 0) | |
1629 | { | |
1630 | first_error (_("register operand expected, but got scalar")); | |
1631 | return FAIL; | |
1632 | } | |
1633 | ||
1634 | if (vectype) | |
1635 | *vectype = atype.eltype; | |
1636 | ||
1637 | *ccp = str; | |
1638 | ||
1639 | return reg; | |
1640 | } | |
1641 | ||
1642 | #define NEON_SCALAR_REG(X) ((X) >> 4) | |
1643 | #define NEON_SCALAR_INDEX(X) ((X) & 15) | |
1644 | ||
5287ad62 JB |
1645 | /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't |
1646 | have enough information to be able to do a good job bounds-checking. So, we | |
1647 | just do easy checks here, and do further checks later. */ | |
1648 | ||
1649 | static int | |
dcbf9037 | 1650 | parse_scalar (char **ccp, int elsize, struct neon_type_el *type) |
5287ad62 | 1651 | { |
dcbf9037 | 1652 | int reg; |
5287ad62 | 1653 | char *str = *ccp; |
dcbf9037 | 1654 | struct neon_typed_alias atype; |
dec41383 JW |
1655 | enum arm_reg_type reg_type = REG_TYPE_VFD; |
1656 | ||
1657 | if (elsize == 4) | |
1658 | reg_type = REG_TYPE_VFS; | |
5f4273c7 | 1659 | |
dec41383 | 1660 | reg = parse_typed_reg_or_scalar (&str, reg_type, NULL, &atype); |
5f4273c7 | 1661 | |
dcbf9037 | 1662 | if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) |
5287ad62 | 1663 | return FAIL; |
5f4273c7 | 1664 | |
dcbf9037 | 1665 | if (atype.index == NEON_ALL_LANES) |
5287ad62 | 1666 | { |
dcbf9037 | 1667 | first_error (_("scalar must have an index")); |
5287ad62 JB |
1668 | return FAIL; |
1669 | } | |
dcbf9037 | 1670 | else if (atype.index >= 64 / elsize) |
5287ad62 | 1671 | { |
dcbf9037 | 1672 | first_error (_("scalar index out of range")); |
5287ad62 JB |
1673 | return FAIL; |
1674 | } | |
5f4273c7 | 1675 | |
dcbf9037 JB |
1676 | if (type) |
1677 | *type = atype.eltype; | |
5f4273c7 | 1678 | |
5287ad62 | 1679 | *ccp = str; |
5f4273c7 | 1680 | |
dcbf9037 | 1681 | return reg * 16 + atype.index; |
5287ad62 JB |
1682 | } |
1683 | ||
c19d1205 | 1684 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
e07e6e58 | 1685 | |
c19d1205 ZW |
1686 | static long |
1687 | parse_reg_list (char ** strp) | |
1688 | { | |
1689 | char * str = * strp; | |
1690 | long range = 0; | |
1691 | int another_range; | |
a737bd4d | 1692 | |
c19d1205 ZW |
1693 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
1694 | do | |
6057a28f | 1695 | { |
477330fc RM |
1696 | skip_whitespace (str); |
1697 | ||
c19d1205 | 1698 | another_range = 0; |
a737bd4d | 1699 | |
c19d1205 ZW |
1700 | if (*str == '{') |
1701 | { | |
1702 | int in_range = 0; | |
1703 | int cur_reg = -1; | |
a737bd4d | 1704 | |
c19d1205 ZW |
1705 | str++; |
1706 | do | |
1707 | { | |
1708 | int reg; | |
6057a28f | 1709 | |
dcbf9037 | 1710 | if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) |
c19d1205 | 1711 | { |
dcbf9037 | 1712 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 ZW |
1713 | return FAIL; |
1714 | } | |
a737bd4d | 1715 | |
c19d1205 ZW |
1716 | if (in_range) |
1717 | { | |
1718 | int i; | |
a737bd4d | 1719 | |
c19d1205 ZW |
1720 | if (reg <= cur_reg) |
1721 | { | |
dcbf9037 | 1722 | first_error (_("bad range in register list")); |
c19d1205 ZW |
1723 | return FAIL; |
1724 | } | |
40a18ebd | 1725 | |
c19d1205 ZW |
1726 | for (i = cur_reg + 1; i < reg; i++) |
1727 | { | |
1728 | if (range & (1 << i)) | |
1729 | as_tsktsk | |
1730 | (_("Warning: duplicated register (r%d) in register list"), | |
1731 | i); | |
1732 | else | |
1733 | range |= 1 << i; | |
1734 | } | |
1735 | in_range = 0; | |
1736 | } | |
a737bd4d | 1737 | |
c19d1205 ZW |
1738 | if (range & (1 << reg)) |
1739 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
1740 | reg); | |
1741 | else if (reg <= cur_reg) | |
1742 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 1743 | |
c19d1205 ZW |
1744 | range |= 1 << reg; |
1745 | cur_reg = reg; | |
1746 | } | |
1747 | while (skip_past_comma (&str) != FAIL | |
1748 | || (in_range = 1, *str++ == '-')); | |
1749 | str--; | |
a737bd4d | 1750 | |
d996d970 | 1751 | if (skip_past_char (&str, '}') == FAIL) |
c19d1205 | 1752 | { |
dcbf9037 | 1753 | first_error (_("missing `}'")); |
c19d1205 ZW |
1754 | return FAIL; |
1755 | } | |
1756 | } | |
1757 | else | |
1758 | { | |
91d6fa6a | 1759 | expressionS exp; |
40a18ebd | 1760 | |
91d6fa6a | 1761 | if (my_get_expression (&exp, &str, GE_NO_PREFIX)) |
c19d1205 | 1762 | return FAIL; |
40a18ebd | 1763 | |
91d6fa6a | 1764 | if (exp.X_op == O_constant) |
c19d1205 | 1765 | { |
91d6fa6a NC |
1766 | if (exp.X_add_number |
1767 | != (exp.X_add_number & 0x0000ffff)) | |
c19d1205 ZW |
1768 | { |
1769 | inst.error = _("invalid register mask"); | |
1770 | return FAIL; | |
1771 | } | |
a737bd4d | 1772 | |
91d6fa6a | 1773 | if ((range & exp.X_add_number) != 0) |
c19d1205 | 1774 | { |
91d6fa6a | 1775 | int regno = range & exp.X_add_number; |
a737bd4d | 1776 | |
c19d1205 ZW |
1777 | regno &= -regno; |
1778 | regno = (1 << regno) - 1; | |
1779 | as_tsktsk | |
1780 | (_("Warning: duplicated register (r%d) in register list"), | |
1781 | regno); | |
1782 | } | |
a737bd4d | 1783 | |
91d6fa6a | 1784 | range |= exp.X_add_number; |
c19d1205 ZW |
1785 | } |
1786 | else | |
1787 | { | |
1788 | if (inst.reloc.type != 0) | |
1789 | { | |
1790 | inst.error = _("expression too complex"); | |
1791 | return FAIL; | |
1792 | } | |
a737bd4d | 1793 | |
91d6fa6a | 1794 | memcpy (&inst.reloc.exp, &exp, sizeof (expressionS)); |
c19d1205 ZW |
1795 | inst.reloc.type = BFD_RELOC_ARM_MULTI; |
1796 | inst.reloc.pc_rel = 0; | |
1797 | } | |
1798 | } | |
a737bd4d | 1799 | |
c19d1205 ZW |
1800 | if (*str == '|' || *str == '+') |
1801 | { | |
1802 | str++; | |
1803 | another_range = 1; | |
1804 | } | |
a737bd4d | 1805 | } |
c19d1205 | 1806 | while (another_range); |
a737bd4d | 1807 | |
c19d1205 ZW |
1808 | *strp = str; |
1809 | return range; | |
a737bd4d NC |
1810 | } |
1811 | ||
5287ad62 JB |
1812 | /* Types of registers in a list. */ |
1813 | ||
1814 | enum reg_list_els | |
1815 | { | |
1816 | REGLIST_VFP_S, | |
1817 | REGLIST_VFP_D, | |
1818 | REGLIST_NEON_D | |
1819 | }; | |
1820 | ||
c19d1205 ZW |
1821 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1822 | Otherwise return the number of registers, and set PBASE to the first | |
5287ad62 JB |
1823 | register. Parses registers of type ETYPE. |
1824 | If REGLIST_NEON_D is used, several syntax enhancements are enabled: | |
1825 | - Q registers can be used to specify pairs of D registers | |
1826 | - { } can be omitted from around a singleton register list | |
477330fc RM |
1827 | FIXME: This is not implemented, as it would require backtracking in |
1828 | some cases, e.g.: | |
1829 | vtbl.8 d3,d4,d5 | |
1830 | This could be done (the meaning isn't really ambiguous), but doesn't | |
1831 | fit in well with the current parsing framework. | |
dcbf9037 JB |
1832 | - 32 D registers may be used (also true for VFPv3). |
1833 | FIXME: Types are ignored in these register lists, which is probably a | |
1834 | bug. */ | |
6057a28f | 1835 | |
c19d1205 | 1836 | static int |
037e8744 | 1837 | parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) |
6057a28f | 1838 | { |
037e8744 | 1839 | char *str = *ccp; |
c19d1205 ZW |
1840 | int base_reg; |
1841 | int new_base; | |
21d799b5 | 1842 | enum arm_reg_type regtype = (enum arm_reg_type) 0; |
5287ad62 | 1843 | int max_regs = 0; |
c19d1205 ZW |
1844 | int count = 0; |
1845 | int warned = 0; | |
1846 | unsigned long mask = 0; | |
a737bd4d | 1847 | int i; |
6057a28f | 1848 | |
477330fc | 1849 | if (skip_past_char (&str, '{') == FAIL) |
5287ad62 JB |
1850 | { |
1851 | inst.error = _("expecting {"); | |
1852 | return FAIL; | |
1853 | } | |
6057a28f | 1854 | |
5287ad62 | 1855 | switch (etype) |
c19d1205 | 1856 | { |
5287ad62 | 1857 | case REGLIST_VFP_S: |
c19d1205 ZW |
1858 | regtype = REG_TYPE_VFS; |
1859 | max_regs = 32; | |
5287ad62 | 1860 | break; |
5f4273c7 | 1861 | |
5287ad62 JB |
1862 | case REGLIST_VFP_D: |
1863 | regtype = REG_TYPE_VFD; | |
b7fc2769 | 1864 | break; |
5f4273c7 | 1865 | |
b7fc2769 JB |
1866 | case REGLIST_NEON_D: |
1867 | regtype = REG_TYPE_NDQ; | |
1868 | break; | |
1869 | } | |
1870 | ||
1871 | if (etype != REGLIST_VFP_S) | |
1872 | { | |
b1cc4aeb PB |
1873 | /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */ |
1874 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) | |
477330fc RM |
1875 | { |
1876 | max_regs = 32; | |
1877 | if (thumb_mode) | |
1878 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
1879 | fpu_vfp_ext_d32); | |
1880 | else | |
1881 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
1882 | fpu_vfp_ext_d32); | |
1883 | } | |
5287ad62 | 1884 | else |
477330fc | 1885 | max_regs = 16; |
c19d1205 | 1886 | } |
6057a28f | 1887 | |
c19d1205 | 1888 | base_reg = max_regs; |
a737bd4d | 1889 | |
c19d1205 ZW |
1890 | do |
1891 | { | |
5287ad62 | 1892 | int setmask = 1, addregs = 1; |
dcbf9037 | 1893 | |
037e8744 | 1894 | new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); |
dcbf9037 | 1895 | |
c19d1205 | 1896 | if (new_base == FAIL) |
a737bd4d | 1897 | { |
dcbf9037 | 1898 | first_error (_(reg_expected_msgs[regtype])); |
c19d1205 ZW |
1899 | return FAIL; |
1900 | } | |
5f4273c7 | 1901 | |
b7fc2769 | 1902 | if (new_base >= max_regs) |
477330fc RM |
1903 | { |
1904 | first_error (_("register out of range in list")); | |
1905 | return FAIL; | |
1906 | } | |
5f4273c7 | 1907 | |
5287ad62 JB |
1908 | /* Note: a value of 2 * n is returned for the register Q<n>. */ |
1909 | if (regtype == REG_TYPE_NQ) | |
477330fc RM |
1910 | { |
1911 | setmask = 3; | |
1912 | addregs = 2; | |
1913 | } | |
5287ad62 | 1914 | |
c19d1205 ZW |
1915 | if (new_base < base_reg) |
1916 | base_reg = new_base; | |
a737bd4d | 1917 | |
5287ad62 | 1918 | if (mask & (setmask << new_base)) |
c19d1205 | 1919 | { |
dcbf9037 | 1920 | first_error (_("invalid register list")); |
c19d1205 | 1921 | return FAIL; |
a737bd4d | 1922 | } |
a737bd4d | 1923 | |
c19d1205 ZW |
1924 | if ((mask >> new_base) != 0 && ! warned) |
1925 | { | |
1926 | as_tsktsk (_("register list not in ascending order")); | |
1927 | warned = 1; | |
1928 | } | |
0bbf2aa4 | 1929 | |
5287ad62 JB |
1930 | mask |= setmask << new_base; |
1931 | count += addregs; | |
0bbf2aa4 | 1932 | |
037e8744 | 1933 | if (*str == '-') /* We have the start of a range expression */ |
c19d1205 ZW |
1934 | { |
1935 | int high_range; | |
0bbf2aa4 | 1936 | |
037e8744 | 1937 | str++; |
0bbf2aa4 | 1938 | |
037e8744 | 1939 | if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) |
477330fc | 1940 | == FAIL) |
c19d1205 ZW |
1941 | { |
1942 | inst.error = gettext (reg_expected_msgs[regtype]); | |
1943 | return FAIL; | |
1944 | } | |
0bbf2aa4 | 1945 | |
477330fc RM |
1946 | if (high_range >= max_regs) |
1947 | { | |
1948 | first_error (_("register out of range in list")); | |
1949 | return FAIL; | |
1950 | } | |
b7fc2769 | 1951 | |
477330fc RM |
1952 | if (regtype == REG_TYPE_NQ) |
1953 | high_range = high_range + 1; | |
5287ad62 | 1954 | |
c19d1205 ZW |
1955 | if (high_range <= new_base) |
1956 | { | |
1957 | inst.error = _("register range not in ascending order"); | |
1958 | return FAIL; | |
1959 | } | |
0bbf2aa4 | 1960 | |
5287ad62 | 1961 | for (new_base += addregs; new_base <= high_range; new_base += addregs) |
0bbf2aa4 | 1962 | { |
5287ad62 | 1963 | if (mask & (setmask << new_base)) |
0bbf2aa4 | 1964 | { |
c19d1205 ZW |
1965 | inst.error = _("invalid register list"); |
1966 | return FAIL; | |
0bbf2aa4 | 1967 | } |
c19d1205 | 1968 | |
5287ad62 JB |
1969 | mask |= setmask << new_base; |
1970 | count += addregs; | |
0bbf2aa4 | 1971 | } |
0bbf2aa4 | 1972 | } |
0bbf2aa4 | 1973 | } |
037e8744 | 1974 | while (skip_past_comma (&str) != FAIL); |
0bbf2aa4 | 1975 | |
037e8744 | 1976 | str++; |
0bbf2aa4 | 1977 | |
c19d1205 ZW |
1978 | /* Sanity check -- should have raised a parse error above. */ |
1979 | if (count == 0 || count > max_regs) | |
1980 | abort (); | |
1981 | ||
1982 | *pbase = base_reg; | |
1983 | ||
1984 | /* Final test -- the registers must be consecutive. */ | |
1985 | mask >>= base_reg; | |
1986 | for (i = 0; i < count; i++) | |
1987 | { | |
1988 | if ((mask & (1u << i)) == 0) | |
1989 | { | |
1990 | inst.error = _("non-contiguous register range"); | |
1991 | return FAIL; | |
1992 | } | |
1993 | } | |
1994 | ||
037e8744 JB |
1995 | *ccp = str; |
1996 | ||
c19d1205 | 1997 | return count; |
b99bd4ef NC |
1998 | } |
1999 | ||
dcbf9037 JB |
2000 | /* True if two alias types are the same. */ |
2001 | ||
c921be7d | 2002 | static bfd_boolean |
dcbf9037 JB |
2003 | neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) |
2004 | { | |
2005 | if (!a && !b) | |
c921be7d | 2006 | return TRUE; |
5f4273c7 | 2007 | |
dcbf9037 | 2008 | if (!a || !b) |
c921be7d | 2009 | return FALSE; |
dcbf9037 JB |
2010 | |
2011 | if (a->defined != b->defined) | |
c921be7d | 2012 | return FALSE; |
5f4273c7 | 2013 | |
dcbf9037 JB |
2014 | if ((a->defined & NTA_HASTYPE) != 0 |
2015 | && (a->eltype.type != b->eltype.type | |
477330fc | 2016 | || a->eltype.size != b->eltype.size)) |
c921be7d | 2017 | return FALSE; |
dcbf9037 JB |
2018 | |
2019 | if ((a->defined & NTA_HASINDEX) != 0 | |
2020 | && (a->index != b->index)) | |
c921be7d | 2021 | return FALSE; |
5f4273c7 | 2022 | |
c921be7d | 2023 | return TRUE; |
dcbf9037 JB |
2024 | } |
2025 | ||
5287ad62 JB |
2026 | /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. |
2027 | The base register is put in *PBASE. | |
dcbf9037 | 2028 | The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of |
5287ad62 JB |
2029 | the return value. |
2030 | The register stride (minus one) is put in bit 4 of the return value. | |
dcbf9037 JB |
2031 | Bits [6:5] encode the list length (minus one). |
2032 | The type of the list elements is put in *ELTYPE, if non-NULL. */ | |
5287ad62 | 2033 | |
5287ad62 | 2034 | #define NEON_LANE(X) ((X) & 0xf) |
dcbf9037 | 2035 | #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) |
5287ad62 JB |
2036 | #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) |
2037 | ||
2038 | static int | |
dcbf9037 | 2039 | parse_neon_el_struct_list (char **str, unsigned *pbase, |
477330fc | 2040 | struct neon_type_el *eltype) |
5287ad62 JB |
2041 | { |
2042 | char *ptr = *str; | |
2043 | int base_reg = -1; | |
2044 | int reg_incr = -1; | |
2045 | int count = 0; | |
2046 | int lane = -1; | |
2047 | int leading_brace = 0; | |
2048 | enum arm_reg_type rtype = REG_TYPE_NDQ; | |
20203fb9 NC |
2049 | const char *const incr_error = _("register stride must be 1 or 2"); |
2050 | const char *const type_error = _("mismatched element/structure types in list"); | |
dcbf9037 | 2051 | struct neon_typed_alias firsttype; |
f85d59c3 KT |
2052 | firsttype.defined = 0; |
2053 | firsttype.eltype.type = NT_invtype; | |
2054 | firsttype.eltype.size = -1; | |
2055 | firsttype.index = -1; | |
5f4273c7 | 2056 | |
5287ad62 JB |
2057 | if (skip_past_char (&ptr, '{') == SUCCESS) |
2058 | leading_brace = 1; | |
5f4273c7 | 2059 | |
5287ad62 JB |
2060 | do |
2061 | { | |
dcbf9037 JB |
2062 | struct neon_typed_alias atype; |
2063 | int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); | |
2064 | ||
5287ad62 | 2065 | if (getreg == FAIL) |
477330fc RM |
2066 | { |
2067 | first_error (_(reg_expected_msgs[rtype])); | |
2068 | return FAIL; | |
2069 | } | |
5f4273c7 | 2070 | |
5287ad62 | 2071 | if (base_reg == -1) |
477330fc RM |
2072 | { |
2073 | base_reg = getreg; | |
2074 | if (rtype == REG_TYPE_NQ) | |
2075 | { | |
2076 | reg_incr = 1; | |
2077 | } | |
2078 | firsttype = atype; | |
2079 | } | |
5287ad62 | 2080 | else if (reg_incr == -1) |
477330fc RM |
2081 | { |
2082 | reg_incr = getreg - base_reg; | |
2083 | if (reg_incr < 1 || reg_incr > 2) | |
2084 | { | |
2085 | first_error (_(incr_error)); | |
2086 | return FAIL; | |
2087 | } | |
2088 | } | |
5287ad62 | 2089 | else if (getreg != base_reg + reg_incr * count) |
477330fc RM |
2090 | { |
2091 | first_error (_(incr_error)); | |
2092 | return FAIL; | |
2093 | } | |
dcbf9037 | 2094 | |
c921be7d | 2095 | if (! neon_alias_types_same (&atype, &firsttype)) |
477330fc RM |
2096 | { |
2097 | first_error (_(type_error)); | |
2098 | return FAIL; | |
2099 | } | |
5f4273c7 | 2100 | |
5287ad62 | 2101 | /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list |
477330fc | 2102 | modes. */ |
5287ad62 | 2103 | if (ptr[0] == '-') |
477330fc RM |
2104 | { |
2105 | struct neon_typed_alias htype; | |
2106 | int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; | |
2107 | if (lane == -1) | |
2108 | lane = NEON_INTERLEAVE_LANES; | |
2109 | else if (lane != NEON_INTERLEAVE_LANES) | |
2110 | { | |
2111 | first_error (_(type_error)); | |
2112 | return FAIL; | |
2113 | } | |
2114 | if (reg_incr == -1) | |
2115 | reg_incr = 1; | |
2116 | else if (reg_incr != 1) | |
2117 | { | |
2118 | first_error (_("don't use Rn-Rm syntax with non-unit stride")); | |
2119 | return FAIL; | |
2120 | } | |
2121 | ptr++; | |
2122 | hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); | |
2123 | if (hireg == FAIL) | |
2124 | { | |
2125 | first_error (_(reg_expected_msgs[rtype])); | |
2126 | return FAIL; | |
2127 | } | |
2128 | if (! neon_alias_types_same (&htype, &firsttype)) | |
2129 | { | |
2130 | first_error (_(type_error)); | |
2131 | return FAIL; | |
2132 | } | |
2133 | count += hireg + dregs - getreg; | |
2134 | continue; | |
2135 | } | |
5f4273c7 | 2136 | |
5287ad62 JB |
2137 | /* If we're using Q registers, we can't use [] or [n] syntax. */ |
2138 | if (rtype == REG_TYPE_NQ) | |
477330fc RM |
2139 | { |
2140 | count += 2; | |
2141 | continue; | |
2142 | } | |
5f4273c7 | 2143 | |
dcbf9037 | 2144 | if ((atype.defined & NTA_HASINDEX) != 0) |
477330fc RM |
2145 | { |
2146 | if (lane == -1) | |
2147 | lane = atype.index; | |
2148 | else if (lane != atype.index) | |
2149 | { | |
2150 | first_error (_(type_error)); | |
2151 | return FAIL; | |
2152 | } | |
2153 | } | |
5287ad62 | 2154 | else if (lane == -1) |
477330fc | 2155 | lane = NEON_INTERLEAVE_LANES; |
5287ad62 | 2156 | else if (lane != NEON_INTERLEAVE_LANES) |
477330fc RM |
2157 | { |
2158 | first_error (_(type_error)); | |
2159 | return FAIL; | |
2160 | } | |
5287ad62 JB |
2161 | count++; |
2162 | } | |
2163 | while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); | |
5f4273c7 | 2164 | |
5287ad62 JB |
2165 | /* No lane set by [x]. We must be interleaving structures. */ |
2166 | if (lane == -1) | |
2167 | lane = NEON_INTERLEAVE_LANES; | |
5f4273c7 | 2168 | |
5287ad62 JB |
2169 | /* Sanity check. */ |
2170 | if (lane == -1 || base_reg == -1 || count < 1 || count > 4 | |
2171 | || (count > 1 && reg_incr == -1)) | |
2172 | { | |
dcbf9037 | 2173 | first_error (_("error parsing element/structure list")); |
5287ad62 JB |
2174 | return FAIL; |
2175 | } | |
2176 | ||
2177 | if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) | |
2178 | { | |
dcbf9037 | 2179 | first_error (_("expected }")); |
5287ad62 JB |
2180 | return FAIL; |
2181 | } | |
5f4273c7 | 2182 | |
5287ad62 JB |
2183 | if (reg_incr == -1) |
2184 | reg_incr = 1; | |
2185 | ||
dcbf9037 JB |
2186 | if (eltype) |
2187 | *eltype = firsttype.eltype; | |
2188 | ||
5287ad62 JB |
2189 | *pbase = base_reg; |
2190 | *str = ptr; | |
5f4273c7 | 2191 | |
5287ad62 JB |
2192 | return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); |
2193 | } | |
2194 | ||
c19d1205 ZW |
2195 | /* Parse an explicit relocation suffix on an expression. This is |
2196 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
2197 | arm_reloc_hsh contains no entries, so this function can only | |
2198 | succeed if there is no () after the word. Returns -1 on error, | |
2199 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
3da1d841 | 2200 | |
c19d1205 ZW |
2201 | static int |
2202 | parse_reloc (char **str) | |
b99bd4ef | 2203 | { |
c19d1205 ZW |
2204 | struct reloc_entry *r; |
2205 | char *p, *q; | |
b99bd4ef | 2206 | |
c19d1205 ZW |
2207 | if (**str != '(') |
2208 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 2209 | |
c19d1205 ZW |
2210 | p = *str + 1; |
2211 | q = p; | |
2212 | ||
2213 | while (*q && *q != ')' && *q != ',') | |
2214 | q++; | |
2215 | if (*q != ')') | |
2216 | return -1; | |
2217 | ||
21d799b5 NC |
2218 | if ((r = (struct reloc_entry *) |
2219 | hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
c19d1205 ZW |
2220 | return -1; |
2221 | ||
2222 | *str = q + 1; | |
2223 | return r->reloc; | |
b99bd4ef NC |
2224 | } |
2225 | ||
c19d1205 ZW |
2226 | /* Directives: register aliases. */ |
2227 | ||
dcbf9037 | 2228 | static struct reg_entry * |
90ec0d68 | 2229 | insert_reg_alias (char *str, unsigned number, int type) |
b99bd4ef | 2230 | { |
d3ce72d0 | 2231 | struct reg_entry *new_reg; |
c19d1205 | 2232 | const char *name; |
b99bd4ef | 2233 | |
d3ce72d0 | 2234 | if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0) |
c19d1205 | 2235 | { |
d3ce72d0 | 2236 | if (new_reg->builtin) |
c19d1205 | 2237 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); |
b99bd4ef | 2238 | |
c19d1205 ZW |
2239 | /* Only warn about a redefinition if it's not defined as the |
2240 | same register. */ | |
d3ce72d0 | 2241 | else if (new_reg->number != number || new_reg->type != type) |
c19d1205 | 2242 | as_warn (_("ignoring redefinition of register alias '%s'"), str); |
69b97547 | 2243 | |
d929913e | 2244 | return NULL; |
c19d1205 | 2245 | } |
b99bd4ef | 2246 | |
c19d1205 | 2247 | name = xstrdup (str); |
325801bd | 2248 | new_reg = XNEW (struct reg_entry); |
b99bd4ef | 2249 | |
d3ce72d0 NC |
2250 | new_reg->name = name; |
2251 | new_reg->number = number; | |
2252 | new_reg->type = type; | |
2253 | new_reg->builtin = FALSE; | |
2254 | new_reg->neon = NULL; | |
b99bd4ef | 2255 | |
d3ce72d0 | 2256 | if (hash_insert (arm_reg_hsh, name, (void *) new_reg)) |
c19d1205 | 2257 | abort (); |
5f4273c7 | 2258 | |
d3ce72d0 | 2259 | return new_reg; |
dcbf9037 JB |
2260 | } |
2261 | ||
2262 | static void | |
2263 | insert_neon_reg_alias (char *str, int number, int type, | |
477330fc | 2264 | struct neon_typed_alias *atype) |
dcbf9037 JB |
2265 | { |
2266 | struct reg_entry *reg = insert_reg_alias (str, number, type); | |
5f4273c7 | 2267 | |
dcbf9037 JB |
2268 | if (!reg) |
2269 | { | |
2270 | first_error (_("attempt to redefine typed alias")); | |
2271 | return; | |
2272 | } | |
5f4273c7 | 2273 | |
dcbf9037 JB |
2274 | if (atype) |
2275 | { | |
325801bd | 2276 | reg->neon = XNEW (struct neon_typed_alias); |
dcbf9037 JB |
2277 | *reg->neon = *atype; |
2278 | } | |
c19d1205 | 2279 | } |
b99bd4ef | 2280 | |
c19d1205 | 2281 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 2282 | |
c19d1205 | 2283 | new_register_name .req existing_register_name |
b99bd4ef | 2284 | |
c19d1205 | 2285 | If we find one, or if it looks sufficiently like one that we want to |
d929913e | 2286 | handle any error here, return TRUE. Otherwise return FALSE. */ |
b99bd4ef | 2287 | |
d929913e | 2288 | static bfd_boolean |
c19d1205 ZW |
2289 | create_register_alias (char * newname, char *p) |
2290 | { | |
2291 | struct reg_entry *old; | |
2292 | char *oldname, *nbuf; | |
2293 | size_t nlen; | |
b99bd4ef | 2294 | |
c19d1205 ZW |
2295 | /* The input scrubber ensures that whitespace after the mnemonic is |
2296 | collapsed to single spaces. */ | |
2297 | oldname = p; | |
2298 | if (strncmp (oldname, " .req ", 6) != 0) | |
d929913e | 2299 | return FALSE; |
b99bd4ef | 2300 | |
c19d1205 ZW |
2301 | oldname += 6; |
2302 | if (*oldname == '\0') | |
d929913e | 2303 | return FALSE; |
b99bd4ef | 2304 | |
21d799b5 | 2305 | old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname); |
c19d1205 | 2306 | if (!old) |
b99bd4ef | 2307 | { |
c19d1205 | 2308 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
d929913e | 2309 | return TRUE; |
b99bd4ef NC |
2310 | } |
2311 | ||
c19d1205 ZW |
2312 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2313 | the desired alias name, and p points to its end. If not, then | |
2314 | the desired alias name is in the global original_case_string. */ | |
2315 | #ifdef TC_CASE_SENSITIVE | |
2316 | nlen = p - newname; | |
2317 | #else | |
2318 | newname = original_case_string; | |
2319 | nlen = strlen (newname); | |
2320 | #endif | |
b99bd4ef | 2321 | |
29a2809e | 2322 | nbuf = xmemdup0 (newname, nlen); |
b99bd4ef | 2323 | |
c19d1205 ZW |
2324 | /* Create aliases under the new name as stated; an all-lowercase |
2325 | version of the new name; and an all-uppercase version of the new | |
2326 | name. */ | |
d929913e NC |
2327 | if (insert_reg_alias (nbuf, old->number, old->type) != NULL) |
2328 | { | |
2329 | for (p = nbuf; *p; p++) | |
2330 | *p = TOUPPER (*p); | |
c19d1205 | 2331 | |
d929913e NC |
2332 | if (strncmp (nbuf, newname, nlen)) |
2333 | { | |
2334 | /* If this attempt to create an additional alias fails, do not bother | |
2335 | trying to create the all-lower case alias. We will fail and issue | |
2336 | a second, duplicate error message. This situation arises when the | |
2337 | programmer does something like: | |
2338 | foo .req r0 | |
2339 | Foo .req r1 | |
2340 | The second .req creates the "Foo" alias but then fails to create | |
5f4273c7 | 2341 | the artificial FOO alias because it has already been created by the |
d929913e NC |
2342 | first .req. */ |
2343 | if (insert_reg_alias (nbuf, old->number, old->type) == NULL) | |
e1fa0163 NC |
2344 | { |
2345 | free (nbuf); | |
2346 | return TRUE; | |
2347 | } | |
d929913e | 2348 | } |
c19d1205 | 2349 | |
d929913e NC |
2350 | for (p = nbuf; *p; p++) |
2351 | *p = TOLOWER (*p); | |
c19d1205 | 2352 | |
d929913e NC |
2353 | if (strncmp (nbuf, newname, nlen)) |
2354 | insert_reg_alias (nbuf, old->number, old->type); | |
2355 | } | |
c19d1205 | 2356 | |
e1fa0163 | 2357 | free (nbuf); |
d929913e | 2358 | return TRUE; |
b99bd4ef NC |
2359 | } |
2360 | ||
dcbf9037 JB |
2361 | /* Create a Neon typed/indexed register alias using directives, e.g.: |
2362 | X .dn d5.s32[1] | |
2363 | Y .qn 6.s16 | |
2364 | Z .dn d7 | |
2365 | T .dn Z[0] | |
2366 | These typed registers can be used instead of the types specified after the | |
2367 | Neon mnemonic, so long as all operands given have types. Types can also be | |
2368 | specified directly, e.g.: | |
5f4273c7 | 2369 | vadd d0.s32, d1.s32, d2.s32 */ |
dcbf9037 | 2370 | |
c921be7d | 2371 | static bfd_boolean |
dcbf9037 JB |
2372 | create_neon_reg_alias (char *newname, char *p) |
2373 | { | |
2374 | enum arm_reg_type basetype; | |
2375 | struct reg_entry *basereg; | |
2376 | struct reg_entry mybasereg; | |
2377 | struct neon_type ntype; | |
2378 | struct neon_typed_alias typeinfo; | |
12d6b0b7 | 2379 | char *namebuf, *nameend ATTRIBUTE_UNUSED; |
dcbf9037 | 2380 | int namelen; |
5f4273c7 | 2381 | |
dcbf9037 JB |
2382 | typeinfo.defined = 0; |
2383 | typeinfo.eltype.type = NT_invtype; | |
2384 | typeinfo.eltype.size = -1; | |
2385 | typeinfo.index = -1; | |
5f4273c7 | 2386 | |
dcbf9037 | 2387 | nameend = p; |
5f4273c7 | 2388 | |
dcbf9037 JB |
2389 | if (strncmp (p, " .dn ", 5) == 0) |
2390 | basetype = REG_TYPE_VFD; | |
2391 | else if (strncmp (p, " .qn ", 5) == 0) | |
2392 | basetype = REG_TYPE_NQ; | |
2393 | else | |
c921be7d | 2394 | return FALSE; |
5f4273c7 | 2395 | |
dcbf9037 | 2396 | p += 5; |
5f4273c7 | 2397 | |
dcbf9037 | 2398 | if (*p == '\0') |
c921be7d | 2399 | return FALSE; |
5f4273c7 | 2400 | |
dcbf9037 JB |
2401 | basereg = arm_reg_parse_multi (&p); |
2402 | ||
2403 | if (basereg && basereg->type != basetype) | |
2404 | { | |
2405 | as_bad (_("bad type for register")); | |
c921be7d | 2406 | return FALSE; |
dcbf9037 JB |
2407 | } |
2408 | ||
2409 | if (basereg == NULL) | |
2410 | { | |
2411 | expressionS exp; | |
2412 | /* Try parsing as an integer. */ | |
2413 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
2414 | if (exp.X_op != O_constant) | |
477330fc RM |
2415 | { |
2416 | as_bad (_("expression must be constant")); | |
2417 | return FALSE; | |
2418 | } | |
dcbf9037 JB |
2419 | basereg = &mybasereg; |
2420 | basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 | |
477330fc | 2421 | : exp.X_add_number; |
dcbf9037 JB |
2422 | basereg->neon = 0; |
2423 | } | |
2424 | ||
2425 | if (basereg->neon) | |
2426 | typeinfo = *basereg->neon; | |
2427 | ||
2428 | if (parse_neon_type (&ntype, &p) == SUCCESS) | |
2429 | { | |
2430 | /* We got a type. */ | |
2431 | if (typeinfo.defined & NTA_HASTYPE) | |
477330fc RM |
2432 | { |
2433 | as_bad (_("can't redefine the type of a register alias")); | |
2434 | return FALSE; | |
2435 | } | |
5f4273c7 | 2436 | |
dcbf9037 JB |
2437 | typeinfo.defined |= NTA_HASTYPE; |
2438 | if (ntype.elems != 1) | |
477330fc RM |
2439 | { |
2440 | as_bad (_("you must specify a single type only")); | |
2441 | return FALSE; | |
2442 | } | |
dcbf9037 JB |
2443 | typeinfo.eltype = ntype.el[0]; |
2444 | } | |
5f4273c7 | 2445 | |
dcbf9037 JB |
2446 | if (skip_past_char (&p, '[') == SUCCESS) |
2447 | { | |
2448 | expressionS exp; | |
2449 | /* We got a scalar index. */ | |
5f4273c7 | 2450 | |
dcbf9037 | 2451 | if (typeinfo.defined & NTA_HASINDEX) |
477330fc RM |
2452 | { |
2453 | as_bad (_("can't redefine the index of a scalar alias")); | |
2454 | return FALSE; | |
2455 | } | |
5f4273c7 | 2456 | |
dcbf9037 | 2457 | my_get_expression (&exp, &p, GE_NO_PREFIX); |
5f4273c7 | 2458 | |
dcbf9037 | 2459 | if (exp.X_op != O_constant) |
477330fc RM |
2460 | { |
2461 | as_bad (_("scalar index must be constant")); | |
2462 | return FALSE; | |
2463 | } | |
5f4273c7 | 2464 | |
dcbf9037 JB |
2465 | typeinfo.defined |= NTA_HASINDEX; |
2466 | typeinfo.index = exp.X_add_number; | |
5f4273c7 | 2467 | |
dcbf9037 | 2468 | if (skip_past_char (&p, ']') == FAIL) |
477330fc RM |
2469 | { |
2470 | as_bad (_("expecting ]")); | |
2471 | return FALSE; | |
2472 | } | |
dcbf9037 JB |
2473 | } |
2474 | ||
15735687 NS |
2475 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2476 | the desired alias name, and p points to its end. If not, then | |
2477 | the desired alias name is in the global original_case_string. */ | |
2478 | #ifdef TC_CASE_SENSITIVE | |
dcbf9037 | 2479 | namelen = nameend - newname; |
15735687 NS |
2480 | #else |
2481 | newname = original_case_string; | |
2482 | namelen = strlen (newname); | |
2483 | #endif | |
2484 | ||
29a2809e | 2485 | namebuf = xmemdup0 (newname, namelen); |
5f4273c7 | 2486 | |
dcbf9037 | 2487 | insert_neon_reg_alias (namebuf, basereg->number, basetype, |
477330fc | 2488 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2489 | |
dcbf9037 JB |
2490 | /* Insert name in all uppercase. */ |
2491 | for (p = namebuf; *p; p++) | |
2492 | *p = TOUPPER (*p); | |
5f4273c7 | 2493 | |
dcbf9037 JB |
2494 | if (strncmp (namebuf, newname, namelen)) |
2495 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
477330fc | 2496 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2497 | |
dcbf9037 JB |
2498 | /* Insert name in all lowercase. */ |
2499 | for (p = namebuf; *p; p++) | |
2500 | *p = TOLOWER (*p); | |
5f4273c7 | 2501 | |
dcbf9037 JB |
2502 | if (strncmp (namebuf, newname, namelen)) |
2503 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
477330fc | 2504 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2505 | |
e1fa0163 | 2506 | free (namebuf); |
c921be7d | 2507 | return TRUE; |
dcbf9037 JB |
2508 | } |
2509 | ||
c19d1205 ZW |
2510 | /* Should never be called, as .req goes between the alias and the |
2511 | register name, not at the beginning of the line. */ | |
c921be7d | 2512 | |
b99bd4ef | 2513 | static void |
c19d1205 | 2514 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2515 | { |
c19d1205 ZW |
2516 | as_bad (_("invalid syntax for .req directive")); |
2517 | } | |
b99bd4ef | 2518 | |
dcbf9037 JB |
2519 | static void |
2520 | s_dn (int a ATTRIBUTE_UNUSED) | |
2521 | { | |
2522 | as_bad (_("invalid syntax for .dn directive")); | |
2523 | } | |
2524 | ||
2525 | static void | |
2526 | s_qn (int a ATTRIBUTE_UNUSED) | |
2527 | { | |
2528 | as_bad (_("invalid syntax for .qn directive")); | |
2529 | } | |
2530 | ||
c19d1205 ZW |
2531 | /* The .unreq directive deletes an alias which was previously defined |
2532 | by .req. For example: | |
b99bd4ef | 2533 | |
c19d1205 ZW |
2534 | my_alias .req r11 |
2535 | .unreq my_alias */ | |
b99bd4ef NC |
2536 | |
2537 | static void | |
c19d1205 | 2538 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2539 | { |
c19d1205 ZW |
2540 | char * name; |
2541 | char saved_char; | |
b99bd4ef | 2542 | |
c19d1205 ZW |
2543 | name = input_line_pointer; |
2544 | ||
2545 | while (*input_line_pointer != 0 | |
2546 | && *input_line_pointer != ' ' | |
2547 | && *input_line_pointer != '\n') | |
2548 | ++input_line_pointer; | |
2549 | ||
2550 | saved_char = *input_line_pointer; | |
2551 | *input_line_pointer = 0; | |
2552 | ||
2553 | if (!*name) | |
2554 | as_bad (_("invalid syntax for .unreq directive")); | |
2555 | else | |
2556 | { | |
21d799b5 | 2557 | struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh, |
477330fc | 2558 | name); |
c19d1205 ZW |
2559 | |
2560 | if (!reg) | |
2561 | as_bad (_("unknown register alias '%s'"), name); | |
2562 | else if (reg->builtin) | |
a1727c1a | 2563 | as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"), |
c19d1205 ZW |
2564 | name); |
2565 | else | |
2566 | { | |
d929913e NC |
2567 | char * p; |
2568 | char * nbuf; | |
2569 | ||
db0bc284 | 2570 | hash_delete (arm_reg_hsh, name, FALSE); |
c19d1205 | 2571 | free ((char *) reg->name); |
477330fc RM |
2572 | if (reg->neon) |
2573 | free (reg->neon); | |
c19d1205 | 2574 | free (reg); |
d929913e NC |
2575 | |
2576 | /* Also locate the all upper case and all lower case versions. | |
2577 | Do not complain if we cannot find one or the other as it | |
2578 | was probably deleted above. */ | |
5f4273c7 | 2579 | |
d929913e NC |
2580 | nbuf = strdup (name); |
2581 | for (p = nbuf; *p; p++) | |
2582 | *p = TOUPPER (*p); | |
21d799b5 | 2583 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2584 | if (reg) |
2585 | { | |
db0bc284 | 2586 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2587 | free ((char *) reg->name); |
2588 | if (reg->neon) | |
2589 | free (reg->neon); | |
2590 | free (reg); | |
2591 | } | |
2592 | ||
2593 | for (p = nbuf; *p; p++) | |
2594 | *p = TOLOWER (*p); | |
21d799b5 | 2595 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2596 | if (reg) |
2597 | { | |
db0bc284 | 2598 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2599 | free ((char *) reg->name); |
2600 | if (reg->neon) | |
2601 | free (reg->neon); | |
2602 | free (reg); | |
2603 | } | |
2604 | ||
2605 | free (nbuf); | |
c19d1205 ZW |
2606 | } |
2607 | } | |
b99bd4ef | 2608 | |
c19d1205 | 2609 | *input_line_pointer = saved_char; |
b99bd4ef NC |
2610 | demand_empty_rest_of_line (); |
2611 | } | |
2612 | ||
c19d1205 ZW |
2613 | /* Directives: Instruction set selection. */ |
2614 | ||
2615 | #ifdef OBJ_ELF | |
2616 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
2617 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
2618 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
2619 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
2620 | ||
cd000bff DJ |
2621 | /* Create a new mapping symbol for the transition to STATE. */ |
2622 | ||
2623 | static void | |
2624 | make_mapping_symbol (enum mstate state, valueT value, fragS *frag) | |
b99bd4ef | 2625 | { |
a737bd4d | 2626 | symbolS * symbolP; |
c19d1205 ZW |
2627 | const char * symname; |
2628 | int type; | |
b99bd4ef | 2629 | |
c19d1205 | 2630 | switch (state) |
b99bd4ef | 2631 | { |
c19d1205 ZW |
2632 | case MAP_DATA: |
2633 | symname = "$d"; | |
2634 | type = BSF_NO_FLAGS; | |
2635 | break; | |
2636 | case MAP_ARM: | |
2637 | symname = "$a"; | |
2638 | type = BSF_NO_FLAGS; | |
2639 | break; | |
2640 | case MAP_THUMB: | |
2641 | symname = "$t"; | |
2642 | type = BSF_NO_FLAGS; | |
2643 | break; | |
c19d1205 ZW |
2644 | default: |
2645 | abort (); | |
2646 | } | |
2647 | ||
cd000bff | 2648 | symbolP = symbol_new (symname, now_seg, value, frag); |
c19d1205 ZW |
2649 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; |
2650 | ||
2651 | switch (state) | |
2652 | { | |
2653 | case MAP_ARM: | |
2654 | THUMB_SET_FUNC (symbolP, 0); | |
2655 | ARM_SET_THUMB (symbolP, 0); | |
2656 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2657 | break; | |
2658 | ||
2659 | case MAP_THUMB: | |
2660 | THUMB_SET_FUNC (symbolP, 1); | |
2661 | ARM_SET_THUMB (symbolP, 1); | |
2662 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2663 | break; | |
2664 | ||
2665 | case MAP_DATA: | |
2666 | default: | |
cd000bff DJ |
2667 | break; |
2668 | } | |
2669 | ||
2670 | /* Save the mapping symbols for future reference. Also check that | |
2671 | we do not place two mapping symbols at the same offset within a | |
2672 | frag. We'll handle overlap between frags in | |
2de7820f JZ |
2673 | check_mapping_symbols. |
2674 | ||
2675 | If .fill or other data filling directive generates zero sized data, | |
2676 | the mapping symbol for the following code will have the same value | |
2677 | as the one generated for the data filling directive. In this case, | |
2678 | we replace the old symbol with the new one at the same address. */ | |
cd000bff DJ |
2679 | if (value == 0) |
2680 | { | |
2de7820f JZ |
2681 | if (frag->tc_frag_data.first_map != NULL) |
2682 | { | |
2683 | know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0); | |
2684 | symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP); | |
2685 | } | |
cd000bff DJ |
2686 | frag->tc_frag_data.first_map = symbolP; |
2687 | } | |
2688 | if (frag->tc_frag_data.last_map != NULL) | |
0f020cef JZ |
2689 | { |
2690 | know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP)); | |
0f020cef JZ |
2691 | if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP)) |
2692 | symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP); | |
2693 | } | |
cd000bff DJ |
2694 | frag->tc_frag_data.last_map = symbolP; |
2695 | } | |
2696 | ||
2697 | /* We must sometimes convert a region marked as code to data during | |
2698 | code alignment, if an odd number of bytes have to be padded. The | |
2699 | code mapping symbol is pushed to an aligned address. */ | |
2700 | ||
2701 | static void | |
2702 | insert_data_mapping_symbol (enum mstate state, | |
2703 | valueT value, fragS *frag, offsetT bytes) | |
2704 | { | |
2705 | /* If there was already a mapping symbol, remove it. */ | |
2706 | if (frag->tc_frag_data.last_map != NULL | |
2707 | && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value) | |
2708 | { | |
2709 | symbolS *symp = frag->tc_frag_data.last_map; | |
2710 | ||
2711 | if (value == 0) | |
2712 | { | |
2713 | know (frag->tc_frag_data.first_map == symp); | |
2714 | frag->tc_frag_data.first_map = NULL; | |
2715 | } | |
2716 | frag->tc_frag_data.last_map = NULL; | |
2717 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
c19d1205 | 2718 | } |
cd000bff DJ |
2719 | |
2720 | make_mapping_symbol (MAP_DATA, value, frag); | |
2721 | make_mapping_symbol (state, value + bytes, frag); | |
2722 | } | |
2723 | ||
2724 | static void mapping_state_2 (enum mstate state, int max_chars); | |
2725 | ||
2726 | /* Set the mapping state to STATE. Only call this when about to | |
2727 | emit some STATE bytes to the file. */ | |
2728 | ||
4e9aaefb | 2729 | #define TRANSITION(from, to) (mapstate == (from) && state == (to)) |
cd000bff DJ |
2730 | void |
2731 | mapping_state (enum mstate state) | |
2732 | { | |
940b5ce0 DJ |
2733 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2734 | ||
cd000bff DJ |
2735 | if (mapstate == state) |
2736 | /* The mapping symbol has already been emitted. | |
2737 | There is nothing else to do. */ | |
2738 | return; | |
49c62a33 NC |
2739 | |
2740 | if (state == MAP_ARM || state == MAP_THUMB) | |
2741 | /* PR gas/12931 | |
2742 | All ARM instructions require 4-byte alignment. | |
2743 | (Almost) all Thumb instructions require 2-byte alignment. | |
2744 | ||
2745 | When emitting instructions into any section, mark the section | |
2746 | appropriately. | |
2747 | ||
2748 | Some Thumb instructions are alignment-sensitive modulo 4 bytes, | |
2749 | but themselves require 2-byte alignment; this applies to some | |
33eaf5de | 2750 | PC- relative forms. However, these cases will involve implicit |
49c62a33 NC |
2751 | literal pool generation or an explicit .align >=2, both of |
2752 | which will cause the section to me marked with sufficient | |
2753 | alignment. Thus, we don't handle those cases here. */ | |
2754 | record_alignment (now_seg, state == MAP_ARM ? 2 : 1); | |
2755 | ||
2756 | if (TRANSITION (MAP_UNDEFINED, MAP_DATA)) | |
4e9aaefb | 2757 | /* This case will be evaluated later. */ |
cd000bff | 2758 | return; |
cd000bff DJ |
2759 | |
2760 | mapping_state_2 (state, 0); | |
cd000bff DJ |
2761 | } |
2762 | ||
2763 | /* Same as mapping_state, but MAX_CHARS bytes have already been | |
2764 | allocated. Put the mapping symbol that far back. */ | |
2765 | ||
2766 | static void | |
2767 | mapping_state_2 (enum mstate state, int max_chars) | |
2768 | { | |
940b5ce0 DJ |
2769 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2770 | ||
2771 | if (!SEG_NORMAL (now_seg)) | |
2772 | return; | |
2773 | ||
cd000bff DJ |
2774 | if (mapstate == state) |
2775 | /* The mapping symbol has already been emitted. | |
2776 | There is nothing else to do. */ | |
2777 | return; | |
2778 | ||
4e9aaefb SA |
2779 | if (TRANSITION (MAP_UNDEFINED, MAP_ARM) |
2780 | || TRANSITION (MAP_UNDEFINED, MAP_THUMB)) | |
2781 | { | |
2782 | struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root; | |
2783 | const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0); | |
2784 | ||
2785 | if (add_symbol) | |
2786 | make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); | |
2787 | } | |
2788 | ||
cd000bff DJ |
2789 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; |
2790 | make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); | |
c19d1205 | 2791 | } |
4e9aaefb | 2792 | #undef TRANSITION |
c19d1205 | 2793 | #else |
d3106081 NS |
2794 | #define mapping_state(x) ((void)0) |
2795 | #define mapping_state_2(x, y) ((void)0) | |
c19d1205 ZW |
2796 | #endif |
2797 | ||
2798 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
2799 | ||
4343666d | 2800 | #ifdef OBJ_COFF |
c19d1205 ZW |
2801 | static symbolS * |
2802 | find_real_start (symbolS * symbolP) | |
2803 | { | |
2804 | char * real_start; | |
2805 | const char * name = S_GET_NAME (symbolP); | |
2806 | symbolS * new_target; | |
2807 | ||
2808 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
2809 | #define STUB_NAME ".real_start_of" | |
2810 | ||
2811 | if (name == NULL) | |
2812 | abort (); | |
2813 | ||
37f6032b ZW |
2814 | /* The compiler may generate BL instructions to local labels because |
2815 | it needs to perform a branch to a far away location. These labels | |
2816 | do not have a corresponding ".real_start_of" label. We check | |
2817 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
2818 | the ".real_start_of" convention for nonlocal branches. */ | |
2819 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
2820 | return symbolP; |
2821 | ||
e1fa0163 | 2822 | real_start = concat (STUB_NAME, name, NULL); |
c19d1205 | 2823 | new_target = symbol_find (real_start); |
e1fa0163 | 2824 | free (real_start); |
c19d1205 ZW |
2825 | |
2826 | if (new_target == NULL) | |
2827 | { | |
bd3ba5d1 | 2828 | as_warn (_("Failed to find real start of function: %s\n"), name); |
c19d1205 ZW |
2829 | new_target = symbolP; |
2830 | } | |
2831 | ||
c19d1205 ZW |
2832 | return new_target; |
2833 | } | |
4343666d | 2834 | #endif |
c19d1205 ZW |
2835 | |
2836 | static void | |
2837 | opcode_select (int width) | |
2838 | { | |
2839 | switch (width) | |
2840 | { | |
2841 | case 16: | |
2842 | if (! thumb_mode) | |
2843 | { | |
e74cfd16 | 2844 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
c19d1205 ZW |
2845 | as_bad (_("selected processor does not support THUMB opcodes")); |
2846 | ||
2847 | thumb_mode = 1; | |
2848 | /* No need to force the alignment, since we will have been | |
2849 | coming from ARM mode, which is word-aligned. */ | |
2850 | record_alignment (now_seg, 1); | |
2851 | } | |
c19d1205 ZW |
2852 | break; |
2853 | ||
2854 | case 32: | |
2855 | if (thumb_mode) | |
2856 | { | |
e74cfd16 | 2857 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 ZW |
2858 | as_bad (_("selected processor does not support ARM opcodes")); |
2859 | ||
2860 | thumb_mode = 0; | |
2861 | ||
2862 | if (!need_pass_2) | |
2863 | frag_align (2, 0, 0); | |
2864 | ||
2865 | record_alignment (now_seg, 1); | |
2866 | } | |
c19d1205 ZW |
2867 | break; |
2868 | ||
2869 | default: | |
2870 | as_bad (_("invalid instruction size selected (%d)"), width); | |
2871 | } | |
2872 | } | |
2873 | ||
2874 | static void | |
2875 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
2876 | { | |
2877 | opcode_select (32); | |
2878 | demand_empty_rest_of_line (); | |
2879 | } | |
2880 | ||
2881 | static void | |
2882 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
2883 | { | |
2884 | opcode_select (16); | |
2885 | demand_empty_rest_of_line (); | |
2886 | } | |
2887 | ||
2888 | static void | |
2889 | s_code (int unused ATTRIBUTE_UNUSED) | |
2890 | { | |
2891 | int temp; | |
2892 | ||
2893 | temp = get_absolute_expression (); | |
2894 | switch (temp) | |
2895 | { | |
2896 | case 16: | |
2897 | case 32: | |
2898 | opcode_select (temp); | |
2899 | break; | |
2900 | ||
2901 | default: | |
2902 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
2903 | } | |
2904 | } | |
2905 | ||
2906 | static void | |
2907 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
2908 | { | |
2909 | /* If we are not already in thumb mode go into it, EVEN if | |
2910 | the target processor does not support thumb instructions. | |
2911 | This is used by gcc/config/arm/lib1funcs.asm for example | |
2912 | to compile interworking support functions even if the | |
2913 | target processor should not support interworking. */ | |
2914 | if (! thumb_mode) | |
2915 | { | |
2916 | thumb_mode = 2; | |
2917 | record_alignment (now_seg, 1); | |
2918 | } | |
2919 | ||
2920 | demand_empty_rest_of_line (); | |
2921 | } | |
2922 | ||
2923 | static void | |
2924 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
2925 | { | |
2926 | s_thumb (0); | |
2927 | ||
2928 | /* The following label is the name/address of the start of a Thumb function. | |
2929 | We need to know this for the interworking support. */ | |
2930 | label_is_thumb_function_name = TRUE; | |
2931 | } | |
2932 | ||
2933 | /* Perform a .set directive, but also mark the alias as | |
2934 | being a thumb function. */ | |
2935 | ||
2936 | static void | |
2937 | s_thumb_set (int equiv) | |
2938 | { | |
2939 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
2940 | We cannot just call that code as we need to get at the symbol that | |
2941 | is created. */ | |
2942 | char * name; | |
2943 | char delim; | |
2944 | char * end_name; | |
2945 | symbolS * symbolP; | |
2946 | ||
2947 | /* Especial apologies for the random logic: | |
2948 | This just grew, and could be parsed much more simply! | |
2949 | Dean - in haste. */ | |
d02603dc | 2950 | delim = get_symbol_name (& name); |
c19d1205 | 2951 | end_name = input_line_pointer; |
d02603dc | 2952 | (void) restore_line_pointer (delim); |
c19d1205 ZW |
2953 | |
2954 | if (*input_line_pointer != ',') | |
2955 | { | |
2956 | *end_name = 0; | |
2957 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
2958 | *end_name = delim; |
2959 | ignore_rest_of_line (); | |
2960 | return; | |
2961 | } | |
2962 | ||
2963 | input_line_pointer++; | |
2964 | *end_name = 0; | |
2965 | ||
2966 | if (name[0] == '.' && name[1] == '\0') | |
2967 | { | |
2968 | /* XXX - this should not happen to .thumb_set. */ | |
2969 | abort (); | |
2970 | } | |
2971 | ||
2972 | if ((symbolP = symbol_find (name)) == NULL | |
2973 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
2974 | { | |
2975 | #ifndef NO_LISTING | |
2976 | /* When doing symbol listings, play games with dummy fragments living | |
2977 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 2978 | for this symbol. */ |
b99bd4ef NC |
2979 | if (listing & LISTING_SYMBOLS) |
2980 | { | |
2981 | extern struct list_info_struct * listing_tail; | |
21d799b5 | 2982 | fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS)); |
b99bd4ef NC |
2983 | |
2984 | memset (dummy_frag, 0, sizeof (fragS)); | |
2985 | dummy_frag->fr_type = rs_fill; | |
2986 | dummy_frag->line = listing_tail; | |
2987 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
2988 | dummy_frag->fr_symbol = symbolP; | |
2989 | } | |
2990 | else | |
2991 | #endif | |
2992 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
2993 | ||
2994 | #ifdef OBJ_COFF | |
2995 | /* "set" symbols are local unless otherwise specified. */ | |
2996 | SF_SET_LOCAL (symbolP); | |
2997 | #endif /* OBJ_COFF */ | |
2998 | } /* Make a new symbol. */ | |
2999 | ||
3000 | symbol_table_insert (symbolP); | |
3001 | ||
3002 | * end_name = delim; | |
3003 | ||
3004 | if (equiv | |
3005 | && S_IS_DEFINED (symbolP) | |
3006 | && S_GET_SEGMENT (symbolP) != reg_section) | |
3007 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
3008 | ||
3009 | pseudo_set (symbolP); | |
3010 | ||
3011 | demand_empty_rest_of_line (); | |
3012 | ||
c19d1205 | 3013 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
3014 | |
3015 | THUMB_SET_FUNC (symbolP, 1); | |
3016 | ARM_SET_THUMB (symbolP, 1); | |
3017 | #if defined OBJ_ELF || defined OBJ_COFF | |
3018 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
3019 | #endif | |
3020 | } | |
3021 | ||
c19d1205 | 3022 | /* Directives: Mode selection. */ |
b99bd4ef | 3023 | |
c19d1205 ZW |
3024 | /* .syntax [unified|divided] - choose the new unified syntax |
3025 | (same for Arm and Thumb encoding, modulo slight differences in what | |
3026 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 3027 | static void |
c19d1205 | 3028 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 3029 | { |
c19d1205 ZW |
3030 | char *name, delim; |
3031 | ||
d02603dc | 3032 | delim = get_symbol_name (& name); |
c19d1205 ZW |
3033 | |
3034 | if (!strcasecmp (name, "unified")) | |
3035 | unified_syntax = TRUE; | |
3036 | else if (!strcasecmp (name, "divided")) | |
3037 | unified_syntax = FALSE; | |
3038 | else | |
3039 | { | |
3040 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
3041 | return; | |
3042 | } | |
d02603dc | 3043 | (void) restore_line_pointer (delim); |
b99bd4ef NC |
3044 | demand_empty_rest_of_line (); |
3045 | } | |
3046 | ||
c19d1205 ZW |
3047 | /* Directives: sectioning and alignment. */ |
3048 | ||
c19d1205 ZW |
3049 | static void |
3050 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 3051 | { |
c19d1205 ZW |
3052 | /* We don't support putting frags in the BSS segment, we fake it by |
3053 | marking in_bss, then looking at s_skip for clues. */ | |
3054 | subseg_set (bss_section, 0); | |
3055 | demand_empty_rest_of_line (); | |
cd000bff DJ |
3056 | |
3057 | #ifdef md_elf_section_change_hook | |
3058 | md_elf_section_change_hook (); | |
3059 | #endif | |
c19d1205 | 3060 | } |
b99bd4ef | 3061 | |
c19d1205 ZW |
3062 | static void |
3063 | s_even (int ignore ATTRIBUTE_UNUSED) | |
3064 | { | |
3065 | /* Never make frag if expect extra pass. */ | |
3066 | if (!need_pass_2) | |
3067 | frag_align (1, 0, 0); | |
b99bd4ef | 3068 | |
c19d1205 | 3069 | record_alignment (now_seg, 1); |
b99bd4ef | 3070 | |
c19d1205 | 3071 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3072 | } |
3073 | ||
2e6976a8 DG |
3074 | /* Directives: CodeComposer Studio. */ |
3075 | ||
3076 | /* .ref (for CodeComposer Studio syntax only). */ | |
3077 | static void | |
3078 | s_ccs_ref (int unused ATTRIBUTE_UNUSED) | |
3079 | { | |
3080 | if (codecomposer_syntax) | |
3081 | ignore_rest_of_line (); | |
3082 | else | |
3083 | as_bad (_(".ref pseudo-op only available with -mccs flag.")); | |
3084 | } | |
3085 | ||
3086 | /* If name is not NULL, then it is used for marking the beginning of a | |
2b0f3761 | 3087 | function, whereas if it is NULL then it means the function end. */ |
2e6976a8 DG |
3088 | static void |
3089 | asmfunc_debug (const char * name) | |
3090 | { | |
3091 | static const char * last_name = NULL; | |
3092 | ||
3093 | if (name != NULL) | |
3094 | { | |
3095 | gas_assert (last_name == NULL); | |
3096 | last_name = name; | |
3097 | ||
3098 | if (debug_type == DEBUG_STABS) | |
3099 | stabs_generate_asm_func (name, name); | |
3100 | } | |
3101 | else | |
3102 | { | |
3103 | gas_assert (last_name != NULL); | |
3104 | ||
3105 | if (debug_type == DEBUG_STABS) | |
3106 | stabs_generate_asm_endfunc (last_name, last_name); | |
3107 | ||
3108 | last_name = NULL; | |
3109 | } | |
3110 | } | |
3111 | ||
3112 | static void | |
3113 | s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED) | |
3114 | { | |
3115 | if (codecomposer_syntax) | |
3116 | { | |
3117 | switch (asmfunc_state) | |
3118 | { | |
3119 | case OUTSIDE_ASMFUNC: | |
3120 | asmfunc_state = WAITING_ASMFUNC_NAME; | |
3121 | break; | |
3122 | ||
3123 | case WAITING_ASMFUNC_NAME: | |
3124 | as_bad (_(".asmfunc repeated.")); | |
3125 | break; | |
3126 | ||
3127 | case WAITING_ENDASMFUNC: | |
3128 | as_bad (_(".asmfunc without function.")); | |
3129 | break; | |
3130 | } | |
3131 | demand_empty_rest_of_line (); | |
3132 | } | |
3133 | else | |
3134 | as_bad (_(".asmfunc pseudo-op only available with -mccs flag.")); | |
3135 | } | |
3136 | ||
3137 | static void | |
3138 | s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED) | |
3139 | { | |
3140 | if (codecomposer_syntax) | |
3141 | { | |
3142 | switch (asmfunc_state) | |
3143 | { | |
3144 | case OUTSIDE_ASMFUNC: | |
3145 | as_bad (_(".endasmfunc without a .asmfunc.")); | |
3146 | break; | |
3147 | ||
3148 | case WAITING_ASMFUNC_NAME: | |
3149 | as_bad (_(".endasmfunc without function.")); | |
3150 | break; | |
3151 | ||
3152 | case WAITING_ENDASMFUNC: | |
3153 | asmfunc_state = OUTSIDE_ASMFUNC; | |
3154 | asmfunc_debug (NULL); | |
3155 | break; | |
3156 | } | |
3157 | demand_empty_rest_of_line (); | |
3158 | } | |
3159 | else | |
3160 | as_bad (_(".endasmfunc pseudo-op only available with -mccs flag.")); | |
3161 | } | |
3162 | ||
3163 | static void | |
3164 | s_ccs_def (int name) | |
3165 | { | |
3166 | if (codecomposer_syntax) | |
3167 | s_globl (name); | |
3168 | else | |
3169 | as_bad (_(".def pseudo-op only available with -mccs flag.")); | |
3170 | } | |
3171 | ||
c19d1205 | 3172 | /* Directives: Literal pools. */ |
a737bd4d | 3173 | |
c19d1205 ZW |
3174 | static literal_pool * |
3175 | find_literal_pool (void) | |
a737bd4d | 3176 | { |
c19d1205 | 3177 | literal_pool * pool; |
a737bd4d | 3178 | |
c19d1205 | 3179 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 3180 | { |
c19d1205 ZW |
3181 | if (pool->section == now_seg |
3182 | && pool->sub_section == now_subseg) | |
3183 | break; | |
a737bd4d NC |
3184 | } |
3185 | ||
c19d1205 | 3186 | return pool; |
a737bd4d NC |
3187 | } |
3188 | ||
c19d1205 ZW |
3189 | static literal_pool * |
3190 | find_or_make_literal_pool (void) | |
a737bd4d | 3191 | { |
c19d1205 ZW |
3192 | /* Next literal pool ID number. */ |
3193 | static unsigned int latest_pool_num = 1; | |
3194 | literal_pool * pool; | |
a737bd4d | 3195 | |
c19d1205 | 3196 | pool = find_literal_pool (); |
a737bd4d | 3197 | |
c19d1205 | 3198 | if (pool == NULL) |
a737bd4d | 3199 | { |
c19d1205 | 3200 | /* Create a new pool. */ |
325801bd | 3201 | pool = XNEW (literal_pool); |
c19d1205 ZW |
3202 | if (! pool) |
3203 | return NULL; | |
a737bd4d | 3204 | |
c19d1205 ZW |
3205 | pool->next_free_entry = 0; |
3206 | pool->section = now_seg; | |
3207 | pool->sub_section = now_subseg; | |
3208 | pool->next = list_of_pools; | |
3209 | pool->symbol = NULL; | |
8335d6aa | 3210 | pool->alignment = 2; |
c19d1205 ZW |
3211 | |
3212 | /* Add it to the list. */ | |
3213 | list_of_pools = pool; | |
a737bd4d | 3214 | } |
a737bd4d | 3215 | |
c19d1205 ZW |
3216 | /* New pools, and emptied pools, will have a NULL symbol. */ |
3217 | if (pool->symbol == NULL) | |
a737bd4d | 3218 | { |
c19d1205 ZW |
3219 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
3220 | (valueT) 0, &zero_address_frag); | |
3221 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
3222 | } |
3223 | ||
c19d1205 ZW |
3224 | /* Done. */ |
3225 | return pool; | |
a737bd4d NC |
3226 | } |
3227 | ||
c19d1205 | 3228 | /* Add the literal in the global 'inst' |
5f4273c7 | 3229 | structure to the relevant literal pool. */ |
b99bd4ef NC |
3230 | |
3231 | static int | |
8335d6aa | 3232 | add_to_lit_pool (unsigned int nbytes) |
b99bd4ef | 3233 | { |
8335d6aa JW |
3234 | #define PADDING_SLOT 0x1 |
3235 | #define LIT_ENTRY_SIZE_MASK 0xFF | |
c19d1205 | 3236 | literal_pool * pool; |
8335d6aa JW |
3237 | unsigned int entry, pool_size = 0; |
3238 | bfd_boolean padding_slot_p = FALSE; | |
e56c722b | 3239 | unsigned imm1 = 0; |
8335d6aa JW |
3240 | unsigned imm2 = 0; |
3241 | ||
3242 | if (nbytes == 8) | |
3243 | { | |
3244 | imm1 = inst.operands[1].imm; | |
3245 | imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg | |
3246 | : inst.reloc.exp.X_unsigned ? 0 | |
2569ceb0 | 3247 | : ((bfd_int64_t) inst.operands[1].imm) >> 32); |
8335d6aa JW |
3248 | if (target_big_endian) |
3249 | { | |
3250 | imm1 = imm2; | |
3251 | imm2 = inst.operands[1].imm; | |
3252 | } | |
3253 | } | |
b99bd4ef | 3254 | |
c19d1205 ZW |
3255 | pool = find_or_make_literal_pool (); |
3256 | ||
3257 | /* Check if this literal value is already in the pool. */ | |
3258 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 3259 | { |
8335d6aa JW |
3260 | if (nbytes == 4) |
3261 | { | |
3262 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
3263 | && (inst.reloc.exp.X_op == O_constant) | |
3264 | && (pool->literals[entry].X_add_number | |
3265 | == inst.reloc.exp.X_add_number) | |
3266 | && (pool->literals[entry].X_md == nbytes) | |
3267 | && (pool->literals[entry].X_unsigned | |
3268 | == inst.reloc.exp.X_unsigned)) | |
3269 | break; | |
3270 | ||
3271 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
3272 | && (inst.reloc.exp.X_op == O_symbol) | |
3273 | && (pool->literals[entry].X_add_number | |
3274 | == inst.reloc.exp.X_add_number) | |
3275 | && (pool->literals[entry].X_add_symbol | |
3276 | == inst.reloc.exp.X_add_symbol) | |
3277 | && (pool->literals[entry].X_op_symbol | |
3278 | == inst.reloc.exp.X_op_symbol) | |
3279 | && (pool->literals[entry].X_md == nbytes)) | |
3280 | break; | |
3281 | } | |
3282 | else if ((nbytes == 8) | |
3283 | && !(pool_size & 0x7) | |
3284 | && ((entry + 1) != pool->next_free_entry) | |
3285 | && (pool->literals[entry].X_op == O_constant) | |
19f2f6a9 | 3286 | && (pool->literals[entry].X_add_number == (offsetT) imm1) |
8335d6aa JW |
3287 | && (pool->literals[entry].X_unsigned |
3288 | == inst.reloc.exp.X_unsigned) | |
3289 | && (pool->literals[entry + 1].X_op == O_constant) | |
19f2f6a9 | 3290 | && (pool->literals[entry + 1].X_add_number == (offsetT) imm2) |
8335d6aa JW |
3291 | && (pool->literals[entry + 1].X_unsigned |
3292 | == inst.reloc.exp.X_unsigned)) | |
c19d1205 ZW |
3293 | break; |
3294 | ||
8335d6aa JW |
3295 | padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT); |
3296 | if (padding_slot_p && (nbytes == 4)) | |
c19d1205 | 3297 | break; |
8335d6aa JW |
3298 | |
3299 | pool_size += 4; | |
b99bd4ef NC |
3300 | } |
3301 | ||
c19d1205 ZW |
3302 | /* Do we need to create a new entry? */ |
3303 | if (entry == pool->next_free_entry) | |
3304 | { | |
3305 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
3306 | { | |
3307 | inst.error = _("literal pool overflow"); | |
3308 | return FAIL; | |
3309 | } | |
3310 | ||
8335d6aa JW |
3311 | if (nbytes == 8) |
3312 | { | |
3313 | /* For 8-byte entries, we align to an 8-byte boundary, | |
3314 | and split it into two 4-byte entries, because on 32-bit | |
3315 | host, 8-byte constants are treated as big num, thus | |
3316 | saved in "generic_bignum" which will be overwritten | |
3317 | by later assignments. | |
3318 | ||
3319 | We also need to make sure there is enough space for | |
3320 | the split. | |
3321 | ||
3322 | We also check to make sure the literal operand is a | |
3323 | constant number. */ | |
19f2f6a9 JW |
3324 | if (!(inst.reloc.exp.X_op == O_constant |
3325 | || inst.reloc.exp.X_op == O_big)) | |
8335d6aa JW |
3326 | { |
3327 | inst.error = _("invalid type for literal pool"); | |
3328 | return FAIL; | |
3329 | } | |
3330 | else if (pool_size & 0x7) | |
3331 | { | |
3332 | if ((entry + 2) >= MAX_LITERAL_POOL_SIZE) | |
3333 | { | |
3334 | inst.error = _("literal pool overflow"); | |
3335 | return FAIL; | |
3336 | } | |
3337 | ||
3338 | pool->literals[entry] = inst.reloc.exp; | |
a6684f0d | 3339 | pool->literals[entry].X_op = O_constant; |
8335d6aa JW |
3340 | pool->literals[entry].X_add_number = 0; |
3341 | pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4; | |
3342 | pool->next_free_entry += 1; | |
3343 | pool_size += 4; | |
3344 | } | |
3345 | else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE) | |
3346 | { | |
3347 | inst.error = _("literal pool overflow"); | |
3348 | return FAIL; | |
3349 | } | |
3350 | ||
3351 | pool->literals[entry] = inst.reloc.exp; | |
3352 | pool->literals[entry].X_op = O_constant; | |
3353 | pool->literals[entry].X_add_number = imm1; | |
3354 | pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned; | |
3355 | pool->literals[entry++].X_md = 4; | |
3356 | pool->literals[entry] = inst.reloc.exp; | |
3357 | pool->literals[entry].X_op = O_constant; | |
3358 | pool->literals[entry].X_add_number = imm2; | |
3359 | pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned; | |
3360 | pool->literals[entry].X_md = 4; | |
3361 | pool->alignment = 3; | |
3362 | pool->next_free_entry += 1; | |
3363 | } | |
3364 | else | |
3365 | { | |
3366 | pool->literals[entry] = inst.reloc.exp; | |
3367 | pool->literals[entry].X_md = 4; | |
3368 | } | |
3369 | ||
a8040cf2 NC |
3370 | #ifdef OBJ_ELF |
3371 | /* PR ld/12974: Record the location of the first source line to reference | |
3372 | this entry in the literal pool. If it turns out during linking that the | |
3373 | symbol does not exist we will be able to give an accurate line number for | |
3374 | the (first use of the) missing reference. */ | |
3375 | if (debug_type == DEBUG_DWARF2) | |
3376 | dwarf2_where (pool->locs + entry); | |
3377 | #endif | |
c19d1205 ZW |
3378 | pool->next_free_entry += 1; |
3379 | } | |
8335d6aa JW |
3380 | else if (padding_slot_p) |
3381 | { | |
3382 | pool->literals[entry] = inst.reloc.exp; | |
3383 | pool->literals[entry].X_md = nbytes; | |
3384 | } | |
b99bd4ef | 3385 | |
c19d1205 | 3386 | inst.reloc.exp.X_op = O_symbol; |
8335d6aa | 3387 | inst.reloc.exp.X_add_number = pool_size; |
c19d1205 | 3388 | inst.reloc.exp.X_add_symbol = pool->symbol; |
b99bd4ef | 3389 | |
c19d1205 | 3390 | return SUCCESS; |
b99bd4ef NC |
3391 | } |
3392 | ||
2e6976a8 | 3393 | bfd_boolean |
2e57ce7b | 3394 | tc_start_label_without_colon (void) |
2e6976a8 DG |
3395 | { |
3396 | bfd_boolean ret = TRUE; | |
3397 | ||
3398 | if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME) | |
3399 | { | |
2e57ce7b | 3400 | const char *label = input_line_pointer; |
2e6976a8 DG |
3401 | |
3402 | while (!is_end_of_line[(int) label[-1]]) | |
3403 | --label; | |
3404 | ||
3405 | if (*label == '.') | |
3406 | { | |
3407 | as_bad (_("Invalid label '%s'"), label); | |
3408 | ret = FALSE; | |
3409 | } | |
3410 | ||
3411 | asmfunc_debug (label); | |
3412 | ||
3413 | asmfunc_state = WAITING_ENDASMFUNC; | |
3414 | } | |
3415 | ||
3416 | return ret; | |
3417 | } | |
3418 | ||
c19d1205 | 3419 | /* Can't use symbol_new here, so have to create a symbol and then at |
33eaf5de | 3420 | a later date assign it a value. That's what these functions do. */ |
e16bb312 | 3421 | |
c19d1205 ZW |
3422 | static void |
3423 | symbol_locate (symbolS * symbolP, | |
3424 | const char * name, /* It is copied, the caller can modify. */ | |
3425 | segT segment, /* Segment identifier (SEG_<something>). */ | |
3426 | valueT valu, /* Symbol value. */ | |
3427 | fragS * frag) /* Associated fragment. */ | |
3428 | { | |
e57e6ddc | 3429 | size_t name_length; |
c19d1205 | 3430 | char * preserved_copy_of_name; |
e16bb312 | 3431 | |
c19d1205 ZW |
3432 | name_length = strlen (name) + 1; /* +1 for \0. */ |
3433 | obstack_grow (¬es, name, name_length); | |
21d799b5 | 3434 | preserved_copy_of_name = (char *) obstack_finish (¬es); |
e16bb312 | 3435 | |
c19d1205 ZW |
3436 | #ifdef tc_canonicalize_symbol_name |
3437 | preserved_copy_of_name = | |
3438 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
3439 | #endif | |
b99bd4ef | 3440 | |
c19d1205 | 3441 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 3442 | |
c19d1205 ZW |
3443 | S_SET_SEGMENT (symbolP, segment); |
3444 | S_SET_VALUE (symbolP, valu); | |
3445 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 3446 | |
c19d1205 | 3447 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 3448 | |
c19d1205 ZW |
3449 | /* Link to end of symbol chain. */ |
3450 | { | |
3451 | extern int symbol_table_frozen; | |
b99bd4ef | 3452 | |
c19d1205 ZW |
3453 | if (symbol_table_frozen) |
3454 | abort (); | |
3455 | } | |
b99bd4ef | 3456 | |
c19d1205 | 3457 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 3458 | |
c19d1205 | 3459 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 3460 | |
c19d1205 ZW |
3461 | #ifdef tc_symbol_new_hook |
3462 | tc_symbol_new_hook (symbolP); | |
3463 | #endif | |
3464 | ||
3465 | #ifdef DEBUG_SYMS | |
3466 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
3467 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
3468 | } |
3469 | ||
c19d1205 ZW |
3470 | static void |
3471 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 3472 | { |
c19d1205 ZW |
3473 | unsigned int entry; |
3474 | literal_pool * pool; | |
3475 | char sym_name[20]; | |
b99bd4ef | 3476 | |
c19d1205 ZW |
3477 | pool = find_literal_pool (); |
3478 | if (pool == NULL | |
3479 | || pool->symbol == NULL | |
3480 | || pool->next_free_entry == 0) | |
3481 | return; | |
b99bd4ef | 3482 | |
c19d1205 ZW |
3483 | /* Align pool as you have word accesses. |
3484 | Only make a frag if we have to. */ | |
3485 | if (!need_pass_2) | |
8335d6aa | 3486 | frag_align (pool->alignment, 0, 0); |
b99bd4ef | 3487 | |
c19d1205 | 3488 | record_alignment (now_seg, 2); |
b99bd4ef | 3489 | |
aaca88ef | 3490 | #ifdef OBJ_ELF |
47fc6e36 WN |
3491 | seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA; |
3492 | make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now); | |
aaca88ef | 3493 | #endif |
c19d1205 | 3494 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 3495 | |
c19d1205 ZW |
3496 | symbol_locate (pool->symbol, sym_name, now_seg, |
3497 | (valueT) frag_now_fix (), frag_now); | |
3498 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 3499 | |
c19d1205 | 3500 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 3501 | |
c19d1205 ZW |
3502 | #if defined OBJ_COFF || defined OBJ_ELF |
3503 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
3504 | #endif | |
6c43fab6 | 3505 | |
c19d1205 | 3506 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
a8040cf2 NC |
3507 | { |
3508 | #ifdef OBJ_ELF | |
3509 | if (debug_type == DEBUG_DWARF2) | |
3510 | dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry); | |
3511 | #endif | |
3512 | /* First output the expression in the instruction to the pool. */ | |
8335d6aa JW |
3513 | emit_expr (&(pool->literals[entry]), |
3514 | pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK); | |
a8040cf2 | 3515 | } |
b99bd4ef | 3516 | |
c19d1205 ZW |
3517 | /* Mark the pool as empty. */ |
3518 | pool->next_free_entry = 0; | |
3519 | pool->symbol = NULL; | |
b99bd4ef NC |
3520 | } |
3521 | ||
c19d1205 ZW |
3522 | #ifdef OBJ_ELF |
3523 | /* Forward declarations for functions below, in the MD interface | |
3524 | section. */ | |
3525 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
3526 | static valueT create_unwind_entry (int); | |
3527 | static void start_unwind_section (const segT, int); | |
3528 | static void add_unwind_opcode (valueT, int); | |
3529 | static void flush_pending_unwind (void); | |
b99bd4ef | 3530 | |
c19d1205 | 3531 | /* Directives: Data. */ |
b99bd4ef | 3532 | |
c19d1205 ZW |
3533 | static void |
3534 | s_arm_elf_cons (int nbytes) | |
3535 | { | |
3536 | expressionS exp; | |
b99bd4ef | 3537 | |
c19d1205 ZW |
3538 | #ifdef md_flush_pending_output |
3539 | md_flush_pending_output (); | |
3540 | #endif | |
b99bd4ef | 3541 | |
c19d1205 | 3542 | if (is_it_end_of_statement ()) |
b99bd4ef | 3543 | { |
c19d1205 ZW |
3544 | demand_empty_rest_of_line (); |
3545 | return; | |
b99bd4ef NC |
3546 | } |
3547 | ||
c19d1205 ZW |
3548 | #ifdef md_cons_align |
3549 | md_cons_align (nbytes); | |
3550 | #endif | |
b99bd4ef | 3551 | |
c19d1205 ZW |
3552 | mapping_state (MAP_DATA); |
3553 | do | |
b99bd4ef | 3554 | { |
c19d1205 ZW |
3555 | int reloc; |
3556 | char *base = input_line_pointer; | |
b99bd4ef | 3557 | |
c19d1205 | 3558 | expression (& exp); |
b99bd4ef | 3559 | |
c19d1205 ZW |
3560 | if (exp.X_op != O_symbol) |
3561 | emit_expr (&exp, (unsigned int) nbytes); | |
3562 | else | |
3563 | { | |
3564 | char *before_reloc = input_line_pointer; | |
3565 | reloc = parse_reloc (&input_line_pointer); | |
3566 | if (reloc == -1) | |
3567 | { | |
3568 | as_bad (_("unrecognized relocation suffix")); | |
3569 | ignore_rest_of_line (); | |
3570 | return; | |
3571 | } | |
3572 | else if (reloc == BFD_RELOC_UNUSED) | |
3573 | emit_expr (&exp, (unsigned int) nbytes); | |
3574 | else | |
3575 | { | |
21d799b5 | 3576 | reloc_howto_type *howto = (reloc_howto_type *) |
477330fc RM |
3577 | bfd_reloc_type_lookup (stdoutput, |
3578 | (bfd_reloc_code_real_type) reloc); | |
c19d1205 | 3579 | int size = bfd_get_reloc_size (howto); |
b99bd4ef | 3580 | |
2fc8bdac ZW |
3581 | if (reloc == BFD_RELOC_ARM_PLT32) |
3582 | { | |
3583 | as_bad (_("(plt) is only valid on branch targets")); | |
3584 | reloc = BFD_RELOC_UNUSED; | |
3585 | size = 0; | |
3586 | } | |
3587 | ||
c19d1205 | 3588 | if (size > nbytes) |
992a06ee AM |
3589 | as_bad (ngettext ("%s relocations do not fit in %d byte", |
3590 | "%s relocations do not fit in %d bytes", | |
3591 | nbytes), | |
c19d1205 ZW |
3592 | howto->name, nbytes); |
3593 | else | |
3594 | { | |
3595 | /* We've parsed an expression stopping at O_symbol. | |
3596 | But there may be more expression left now that we | |
3597 | have parsed the relocation marker. Parse it again. | |
3598 | XXX Surely there is a cleaner way to do this. */ | |
3599 | char *p = input_line_pointer; | |
3600 | int offset; | |
325801bd | 3601 | char *save_buf = XNEWVEC (char, input_line_pointer - base); |
e1fa0163 | 3602 | |
c19d1205 ZW |
3603 | memcpy (save_buf, base, input_line_pointer - base); |
3604 | memmove (base + (input_line_pointer - before_reloc), | |
3605 | base, before_reloc - base); | |
3606 | ||
3607 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
3608 | expression (&exp); | |
3609 | memcpy (base, save_buf, p - base); | |
3610 | ||
3611 | offset = nbytes - size; | |
4b1a927e AM |
3612 | p = frag_more (nbytes); |
3613 | memset (p, 0, nbytes); | |
c19d1205 | 3614 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, |
21d799b5 | 3615 | size, &exp, 0, (enum bfd_reloc_code_real) reloc); |
e1fa0163 | 3616 | free (save_buf); |
c19d1205 ZW |
3617 | } |
3618 | } | |
3619 | } | |
b99bd4ef | 3620 | } |
c19d1205 | 3621 | while (*input_line_pointer++ == ','); |
b99bd4ef | 3622 | |
c19d1205 ZW |
3623 | /* Put terminator back into stream. */ |
3624 | input_line_pointer --; | |
3625 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
3626 | } |
3627 | ||
c921be7d NC |
3628 | /* Emit an expression containing a 32-bit thumb instruction. |
3629 | Implementation based on put_thumb32_insn. */ | |
3630 | ||
3631 | static void | |
3632 | emit_thumb32_expr (expressionS * exp) | |
3633 | { | |
3634 | expressionS exp_high = *exp; | |
3635 | ||
3636 | exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16; | |
3637 | emit_expr (& exp_high, (unsigned int) THUMB_SIZE); | |
3638 | exp->X_add_number &= 0xffff; | |
3639 | emit_expr (exp, (unsigned int) THUMB_SIZE); | |
3640 | } | |
3641 | ||
3642 | /* Guess the instruction size based on the opcode. */ | |
3643 | ||
3644 | static int | |
3645 | thumb_insn_size (int opcode) | |
3646 | { | |
3647 | if ((unsigned int) opcode < 0xe800u) | |
3648 | return 2; | |
3649 | else if ((unsigned int) opcode >= 0xe8000000u) | |
3650 | return 4; | |
3651 | else | |
3652 | return 0; | |
3653 | } | |
3654 | ||
3655 | static bfd_boolean | |
3656 | emit_insn (expressionS *exp, int nbytes) | |
3657 | { | |
3658 | int size = 0; | |
3659 | ||
3660 | if (exp->X_op == O_constant) | |
3661 | { | |
3662 | size = nbytes; | |
3663 | ||
3664 | if (size == 0) | |
3665 | size = thumb_insn_size (exp->X_add_number); | |
3666 | ||
3667 | if (size != 0) | |
3668 | { | |
3669 | if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu) | |
3670 | { | |
3671 | as_bad (_(".inst.n operand too big. "\ | |
3672 | "Use .inst.w instead")); | |
3673 | size = 0; | |
3674 | } | |
3675 | else | |
3676 | { | |
3677 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
3678 | set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0); | |
3679 | else | |
3680 | set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0); | |
3681 | ||
3682 | if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian) | |
3683 | emit_thumb32_expr (exp); | |
3684 | else | |
3685 | emit_expr (exp, (unsigned int) size); | |
3686 | ||
3687 | it_fsm_post_encode (); | |
3688 | } | |
3689 | } | |
3690 | else | |
3691 | as_bad (_("cannot determine Thumb instruction size. " \ | |
3692 | "Use .inst.n/.inst.w instead")); | |
3693 | } | |
3694 | else | |
3695 | as_bad (_("constant expression required")); | |
3696 | ||
3697 | return (size != 0); | |
3698 | } | |
3699 | ||
3700 | /* Like s_arm_elf_cons but do not use md_cons_align and | |
3701 | set the mapping state to MAP_ARM/MAP_THUMB. */ | |
3702 | ||
3703 | static void | |
3704 | s_arm_elf_inst (int nbytes) | |
3705 | { | |
3706 | if (is_it_end_of_statement ()) | |
3707 | { | |
3708 | demand_empty_rest_of_line (); | |
3709 | return; | |
3710 | } | |
3711 | ||
3712 | /* Calling mapping_state () here will not change ARM/THUMB, | |
3713 | but will ensure not to be in DATA state. */ | |
3714 | ||
3715 | if (thumb_mode) | |
3716 | mapping_state (MAP_THUMB); | |
3717 | else | |
3718 | { | |
3719 | if (nbytes != 0) | |
3720 | { | |
3721 | as_bad (_("width suffixes are invalid in ARM mode")); | |
3722 | ignore_rest_of_line (); | |
3723 | return; | |
3724 | } | |
3725 | ||
3726 | nbytes = 4; | |
3727 | ||
3728 | mapping_state (MAP_ARM); | |
3729 | } | |
3730 | ||
3731 | do | |
3732 | { | |
3733 | expressionS exp; | |
3734 | ||
3735 | expression (& exp); | |
3736 | ||
3737 | if (! emit_insn (& exp, nbytes)) | |
3738 | { | |
3739 | ignore_rest_of_line (); | |
3740 | return; | |
3741 | } | |
3742 | } | |
3743 | while (*input_line_pointer++ == ','); | |
3744 | ||
3745 | /* Put terminator back into stream. */ | |
3746 | input_line_pointer --; | |
3747 | demand_empty_rest_of_line (); | |
3748 | } | |
b99bd4ef | 3749 | |
c19d1205 | 3750 | /* Parse a .rel31 directive. */ |
b99bd4ef | 3751 | |
c19d1205 ZW |
3752 | static void |
3753 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
3754 | { | |
3755 | expressionS exp; | |
3756 | char *p; | |
3757 | valueT highbit; | |
b99bd4ef | 3758 | |
c19d1205 ZW |
3759 | highbit = 0; |
3760 | if (*input_line_pointer == '1') | |
3761 | highbit = 0x80000000; | |
3762 | else if (*input_line_pointer != '0') | |
3763 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 3764 | |
c19d1205 ZW |
3765 | input_line_pointer++; |
3766 | if (*input_line_pointer != ',') | |
3767 | as_bad (_("missing comma")); | |
3768 | input_line_pointer++; | |
b99bd4ef | 3769 | |
c19d1205 ZW |
3770 | #ifdef md_flush_pending_output |
3771 | md_flush_pending_output (); | |
3772 | #endif | |
b99bd4ef | 3773 | |
c19d1205 ZW |
3774 | #ifdef md_cons_align |
3775 | md_cons_align (4); | |
3776 | #endif | |
b99bd4ef | 3777 | |
c19d1205 | 3778 | mapping_state (MAP_DATA); |
b99bd4ef | 3779 | |
c19d1205 | 3780 | expression (&exp); |
b99bd4ef | 3781 | |
c19d1205 ZW |
3782 | p = frag_more (4); |
3783 | md_number_to_chars (p, highbit, 4); | |
3784 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
3785 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 3786 | |
c19d1205 | 3787 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3788 | } |
3789 | ||
c19d1205 | 3790 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 3791 | |
c19d1205 | 3792 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 3793 | |
c19d1205 ZW |
3794 | static void |
3795 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
3796 | { | |
3797 | demand_empty_rest_of_line (); | |
921e5f0a PB |
3798 | if (unwind.proc_start) |
3799 | { | |
c921be7d | 3800 | as_bad (_("duplicate .fnstart directive")); |
921e5f0a PB |
3801 | return; |
3802 | } | |
3803 | ||
c19d1205 ZW |
3804 | /* Mark the start of the function. */ |
3805 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 3806 | |
c19d1205 ZW |
3807 | /* Reset the rest of the unwind info. */ |
3808 | unwind.opcode_count = 0; | |
3809 | unwind.table_entry = NULL; | |
3810 | unwind.personality_routine = NULL; | |
3811 | unwind.personality_index = -1; | |
3812 | unwind.frame_size = 0; | |
3813 | unwind.fp_offset = 0; | |
fdfde340 | 3814 | unwind.fp_reg = REG_SP; |
c19d1205 ZW |
3815 | unwind.fp_used = 0; |
3816 | unwind.sp_restored = 0; | |
3817 | } | |
b99bd4ef | 3818 | |
b99bd4ef | 3819 | |
c19d1205 ZW |
3820 | /* Parse a handlerdata directive. Creates the exception handling table entry |
3821 | for the function. */ | |
b99bd4ef | 3822 | |
c19d1205 ZW |
3823 | static void |
3824 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
3825 | { | |
3826 | demand_empty_rest_of_line (); | |
921e5f0a | 3827 | if (!unwind.proc_start) |
c921be7d | 3828 | as_bad (MISSING_FNSTART); |
921e5f0a | 3829 | |
c19d1205 | 3830 | if (unwind.table_entry) |
6decc662 | 3831 | as_bad (_("duplicate .handlerdata directive")); |
f02232aa | 3832 | |
c19d1205 ZW |
3833 | create_unwind_entry (1); |
3834 | } | |
a737bd4d | 3835 | |
c19d1205 | 3836 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 3837 | |
c19d1205 ZW |
3838 | static void |
3839 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
3840 | { | |
3841 | long where; | |
3842 | char *ptr; | |
3843 | valueT val; | |
940b5ce0 | 3844 | unsigned int marked_pr_dependency; |
f02232aa | 3845 | |
c19d1205 | 3846 | demand_empty_rest_of_line (); |
f02232aa | 3847 | |
921e5f0a PB |
3848 | if (!unwind.proc_start) |
3849 | { | |
c921be7d | 3850 | as_bad (_(".fnend directive without .fnstart")); |
921e5f0a PB |
3851 | return; |
3852 | } | |
3853 | ||
c19d1205 ZW |
3854 | /* Add eh table entry. */ |
3855 | if (unwind.table_entry == NULL) | |
3856 | val = create_unwind_entry (0); | |
3857 | else | |
3858 | val = 0; | |
f02232aa | 3859 | |
c19d1205 ZW |
3860 | /* Add index table entry. This is two words. */ |
3861 | start_unwind_section (unwind.saved_seg, 1); | |
3862 | frag_align (2, 0, 0); | |
3863 | record_alignment (now_seg, 2); | |
b99bd4ef | 3864 | |
c19d1205 | 3865 | ptr = frag_more (8); |
5011093d | 3866 | memset (ptr, 0, 8); |
c19d1205 | 3867 | where = frag_now_fix () - 8; |
f02232aa | 3868 | |
c19d1205 ZW |
3869 | /* Self relative offset of the function start. */ |
3870 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
3871 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3872 | |
c19d1205 ZW |
3873 | /* Indicate dependency on EHABI-defined personality routines to the |
3874 | linker, if it hasn't been done already. */ | |
940b5ce0 DJ |
3875 | marked_pr_dependency |
3876 | = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency; | |
c19d1205 ZW |
3877 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 |
3878 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
3879 | { | |
5f4273c7 NC |
3880 | static const char *const name[] = |
3881 | { | |
3882 | "__aeabi_unwind_cpp_pr0", | |
3883 | "__aeabi_unwind_cpp_pr1", | |
3884 | "__aeabi_unwind_cpp_pr2" | |
3885 | }; | |
c19d1205 ZW |
3886 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); |
3887 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
c19d1205 | 3888 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency |
940b5ce0 | 3889 | |= 1 << unwind.personality_index; |
c19d1205 | 3890 | } |
f02232aa | 3891 | |
c19d1205 ZW |
3892 | if (val) |
3893 | /* Inline exception table entry. */ | |
3894 | md_number_to_chars (ptr + 4, val, 4); | |
3895 | else | |
3896 | /* Self relative offset of the table entry. */ | |
3897 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
3898 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3899 | |
c19d1205 ZW |
3900 | /* Restore the original section. */ |
3901 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
921e5f0a PB |
3902 | |
3903 | unwind.proc_start = NULL; | |
c19d1205 | 3904 | } |
f02232aa | 3905 | |
f02232aa | 3906 | |
c19d1205 | 3907 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 3908 | |
c19d1205 ZW |
3909 | static void |
3910 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
3911 | { | |
3912 | demand_empty_rest_of_line (); | |
921e5f0a | 3913 | if (!unwind.proc_start) |
c921be7d | 3914 | as_bad (MISSING_FNSTART); |
921e5f0a | 3915 | |
c19d1205 ZW |
3916 | if (unwind.personality_routine || unwind.personality_index != -1) |
3917 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 3918 | |
c19d1205 ZW |
3919 | unwind.personality_index = -2; |
3920 | } | |
b99bd4ef | 3921 | |
b99bd4ef | 3922 | |
c19d1205 | 3923 | /* Parse a personalityindex directive. */ |
b99bd4ef | 3924 | |
c19d1205 ZW |
3925 | static void |
3926 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
3927 | { | |
3928 | expressionS exp; | |
b99bd4ef | 3929 | |
921e5f0a | 3930 | if (!unwind.proc_start) |
c921be7d | 3931 | as_bad (MISSING_FNSTART); |
921e5f0a | 3932 | |
c19d1205 ZW |
3933 | if (unwind.personality_routine || unwind.personality_index != -1) |
3934 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 3935 | |
c19d1205 | 3936 | expression (&exp); |
b99bd4ef | 3937 | |
c19d1205 ZW |
3938 | if (exp.X_op != O_constant |
3939 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 3940 | { |
c19d1205 ZW |
3941 | as_bad (_("bad personality routine number")); |
3942 | ignore_rest_of_line (); | |
3943 | return; | |
b99bd4ef NC |
3944 | } |
3945 | ||
c19d1205 | 3946 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 3947 | |
c19d1205 ZW |
3948 | demand_empty_rest_of_line (); |
3949 | } | |
e16bb312 | 3950 | |
e16bb312 | 3951 | |
c19d1205 | 3952 | /* Parse a personality directive. */ |
e16bb312 | 3953 | |
c19d1205 ZW |
3954 | static void |
3955 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
3956 | { | |
3957 | char *name, *p, c; | |
a737bd4d | 3958 | |
921e5f0a | 3959 | if (!unwind.proc_start) |
c921be7d | 3960 | as_bad (MISSING_FNSTART); |
921e5f0a | 3961 | |
c19d1205 ZW |
3962 | if (unwind.personality_routine || unwind.personality_index != -1) |
3963 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 3964 | |
d02603dc | 3965 | c = get_symbol_name (& name); |
c19d1205 | 3966 | p = input_line_pointer; |
d02603dc NC |
3967 | if (c == '"') |
3968 | ++ input_line_pointer; | |
c19d1205 ZW |
3969 | unwind.personality_routine = symbol_find_or_make (name); |
3970 | *p = c; | |
3971 | demand_empty_rest_of_line (); | |
3972 | } | |
e16bb312 | 3973 | |
e16bb312 | 3974 | |
c19d1205 | 3975 | /* Parse a directive saving core registers. */ |
e16bb312 | 3976 | |
c19d1205 ZW |
3977 | static void |
3978 | s_arm_unwind_save_core (void) | |
e16bb312 | 3979 | { |
c19d1205 ZW |
3980 | valueT op; |
3981 | long range; | |
3982 | int n; | |
e16bb312 | 3983 | |
c19d1205 ZW |
3984 | range = parse_reg_list (&input_line_pointer); |
3985 | if (range == FAIL) | |
e16bb312 | 3986 | { |
c19d1205 ZW |
3987 | as_bad (_("expected register list")); |
3988 | ignore_rest_of_line (); | |
3989 | return; | |
3990 | } | |
e16bb312 | 3991 | |
c19d1205 | 3992 | demand_empty_rest_of_line (); |
e16bb312 | 3993 | |
c19d1205 ZW |
3994 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
3995 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
3996 | ip because it is clobbered by calls. */ | |
3997 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
3998 | && (range & 0x3000) == 0x1000) | |
3999 | { | |
4000 | unwind.opcode_count--; | |
4001 | unwind.sp_restored = 0; | |
4002 | range = (range | 0x2000) & ~0x1000; | |
4003 | unwind.pending_offset = 0; | |
4004 | } | |
e16bb312 | 4005 | |
01ae4198 DJ |
4006 | /* Pop r4-r15. */ |
4007 | if (range & 0xfff0) | |
c19d1205 | 4008 | { |
01ae4198 DJ |
4009 | /* See if we can use the short opcodes. These pop a block of up to 8 |
4010 | registers starting with r4, plus maybe r14. */ | |
4011 | for (n = 0; n < 8; n++) | |
4012 | { | |
4013 | /* Break at the first non-saved register. */ | |
4014 | if ((range & (1 << (n + 4))) == 0) | |
4015 | break; | |
4016 | } | |
4017 | /* See if there are any other bits set. */ | |
4018 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
4019 | { | |
4020 | /* Use the long form. */ | |
4021 | op = 0x8000 | ((range >> 4) & 0xfff); | |
4022 | add_unwind_opcode (op, 2); | |
4023 | } | |
0dd132b6 | 4024 | else |
01ae4198 DJ |
4025 | { |
4026 | /* Use the short form. */ | |
4027 | if (range & 0x4000) | |
4028 | op = 0xa8; /* Pop r14. */ | |
4029 | else | |
4030 | op = 0xa0; /* Do not pop r14. */ | |
4031 | op |= (n - 1); | |
4032 | add_unwind_opcode (op, 1); | |
4033 | } | |
c19d1205 | 4034 | } |
0dd132b6 | 4035 | |
c19d1205 ZW |
4036 | /* Pop r0-r3. */ |
4037 | if (range & 0xf) | |
4038 | { | |
4039 | op = 0xb100 | (range & 0xf); | |
4040 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
4041 | } |
4042 | ||
c19d1205 ZW |
4043 | /* Record the number of bytes pushed. */ |
4044 | for (n = 0; n < 16; n++) | |
4045 | { | |
4046 | if (range & (1 << n)) | |
4047 | unwind.frame_size += 4; | |
4048 | } | |
0dd132b6 NC |
4049 | } |
4050 | ||
c19d1205 ZW |
4051 | |
4052 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
4053 | |
4054 | static void | |
c19d1205 | 4055 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 4056 | { |
c19d1205 ZW |
4057 | expressionS exp; |
4058 | int num_regs; | |
4059 | valueT op; | |
b99bd4ef | 4060 | |
c19d1205 ZW |
4061 | /* Get Number of registers to transfer. */ |
4062 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4063 | expression (&exp); | |
4064 | else | |
4065 | exp.X_op = O_illegal; | |
b99bd4ef | 4066 | |
c19d1205 | 4067 | if (exp.X_op != O_constant) |
b99bd4ef | 4068 | { |
c19d1205 ZW |
4069 | as_bad (_("expected , <constant>")); |
4070 | ignore_rest_of_line (); | |
b99bd4ef NC |
4071 | return; |
4072 | } | |
4073 | ||
c19d1205 ZW |
4074 | num_regs = exp.X_add_number; |
4075 | ||
4076 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 4077 | { |
c19d1205 ZW |
4078 | as_bad (_("number of registers must be in the range [1:4]")); |
4079 | ignore_rest_of_line (); | |
b99bd4ef NC |
4080 | return; |
4081 | } | |
4082 | ||
c19d1205 | 4083 | demand_empty_rest_of_line (); |
b99bd4ef | 4084 | |
c19d1205 ZW |
4085 | if (reg == 4) |
4086 | { | |
4087 | /* Short form. */ | |
4088 | op = 0xb4 | (num_regs - 1); | |
4089 | add_unwind_opcode (op, 1); | |
4090 | } | |
b99bd4ef NC |
4091 | else |
4092 | { | |
c19d1205 ZW |
4093 | /* Long form. */ |
4094 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
4095 | add_unwind_opcode (op, 2); | |
b99bd4ef | 4096 | } |
c19d1205 | 4097 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
4098 | } |
4099 | ||
c19d1205 | 4100 | |
fa073d69 MS |
4101 | /* Parse a directive saving VFP registers for ARMv6 and above. */ |
4102 | ||
4103 | static void | |
4104 | s_arm_unwind_save_vfp_armv6 (void) | |
4105 | { | |
4106 | int count; | |
4107 | unsigned int start; | |
4108 | valueT op; | |
4109 | int num_vfpv3_regs = 0; | |
4110 | int num_regs_below_16; | |
4111 | ||
4112 | count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); | |
4113 | if (count == FAIL) | |
4114 | { | |
4115 | as_bad (_("expected register list")); | |
4116 | ignore_rest_of_line (); | |
4117 | return; | |
4118 | } | |
4119 | ||
4120 | demand_empty_rest_of_line (); | |
4121 | ||
4122 | /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather | |
4123 | than FSTMX/FLDMX-style ones). */ | |
4124 | ||
4125 | /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ | |
4126 | if (start >= 16) | |
4127 | num_vfpv3_regs = count; | |
4128 | else if (start + count > 16) | |
4129 | num_vfpv3_regs = start + count - 16; | |
4130 | ||
4131 | if (num_vfpv3_regs > 0) | |
4132 | { | |
4133 | int start_offset = start > 16 ? start - 16 : 0; | |
4134 | op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); | |
4135 | add_unwind_opcode (op, 2); | |
4136 | } | |
4137 | ||
4138 | /* Generate opcode for registers numbered in the range 0 .. 15. */ | |
4139 | num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; | |
9c2799c2 | 4140 | gas_assert (num_regs_below_16 + num_vfpv3_regs == count); |
fa073d69 MS |
4141 | if (num_regs_below_16 > 0) |
4142 | { | |
4143 | op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); | |
4144 | add_unwind_opcode (op, 2); | |
4145 | } | |
4146 | ||
4147 | unwind.frame_size += count * 8; | |
4148 | } | |
4149 | ||
4150 | ||
4151 | /* Parse a directive saving VFP registers for pre-ARMv6. */ | |
b99bd4ef NC |
4152 | |
4153 | static void | |
c19d1205 | 4154 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 4155 | { |
c19d1205 | 4156 | int count; |
ca3f61f7 | 4157 | unsigned int reg; |
c19d1205 | 4158 | valueT op; |
b99bd4ef | 4159 | |
5287ad62 | 4160 | count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); |
c19d1205 | 4161 | if (count == FAIL) |
b99bd4ef | 4162 | { |
c19d1205 ZW |
4163 | as_bad (_("expected register list")); |
4164 | ignore_rest_of_line (); | |
b99bd4ef NC |
4165 | return; |
4166 | } | |
4167 | ||
c19d1205 | 4168 | demand_empty_rest_of_line (); |
b99bd4ef | 4169 | |
c19d1205 | 4170 | if (reg == 8) |
b99bd4ef | 4171 | { |
c19d1205 ZW |
4172 | /* Short form. */ |
4173 | op = 0xb8 | (count - 1); | |
4174 | add_unwind_opcode (op, 1); | |
b99bd4ef | 4175 | } |
c19d1205 | 4176 | else |
b99bd4ef | 4177 | { |
c19d1205 ZW |
4178 | /* Long form. */ |
4179 | op = 0xb300 | (reg << 4) | (count - 1); | |
4180 | add_unwind_opcode (op, 2); | |
b99bd4ef | 4181 | } |
c19d1205 ZW |
4182 | unwind.frame_size += count * 8 + 4; |
4183 | } | |
b99bd4ef | 4184 | |
b99bd4ef | 4185 | |
c19d1205 ZW |
4186 | /* Parse a directive saving iWMMXt data registers. */ |
4187 | ||
4188 | static void | |
4189 | s_arm_unwind_save_mmxwr (void) | |
4190 | { | |
4191 | int reg; | |
4192 | int hi_reg; | |
4193 | int i; | |
4194 | unsigned mask = 0; | |
4195 | valueT op; | |
b99bd4ef | 4196 | |
c19d1205 ZW |
4197 | if (*input_line_pointer == '{') |
4198 | input_line_pointer++; | |
b99bd4ef | 4199 | |
c19d1205 | 4200 | do |
b99bd4ef | 4201 | { |
dcbf9037 | 4202 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 4203 | |
c19d1205 | 4204 | if (reg == FAIL) |
b99bd4ef | 4205 | { |
9b7132d3 | 4206 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 | 4207 | goto error; |
b99bd4ef NC |
4208 | } |
4209 | ||
c19d1205 ZW |
4210 | if (mask >> reg) |
4211 | as_tsktsk (_("register list not in ascending order")); | |
4212 | mask |= 1 << reg; | |
b99bd4ef | 4213 | |
c19d1205 ZW |
4214 | if (*input_line_pointer == '-') |
4215 | { | |
4216 | input_line_pointer++; | |
dcbf9037 | 4217 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
c19d1205 ZW |
4218 | if (hi_reg == FAIL) |
4219 | { | |
9b7132d3 | 4220 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 ZW |
4221 | goto error; |
4222 | } | |
4223 | else if (reg >= hi_reg) | |
4224 | { | |
4225 | as_bad (_("bad register range")); | |
4226 | goto error; | |
4227 | } | |
4228 | for (; reg < hi_reg; reg++) | |
4229 | mask |= 1 << reg; | |
4230 | } | |
4231 | } | |
4232 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 4233 | |
d996d970 | 4234 | skip_past_char (&input_line_pointer, '}'); |
b99bd4ef | 4235 | |
c19d1205 | 4236 | demand_empty_rest_of_line (); |
b99bd4ef | 4237 | |
708587a4 | 4238 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
4239 | the list. */ |
4240 | flush_pending_unwind (); | |
b99bd4ef | 4241 | |
c19d1205 | 4242 | for (i = 0; i < 16; i++) |
b99bd4ef | 4243 | { |
c19d1205 ZW |
4244 | if (mask & (1 << i)) |
4245 | unwind.frame_size += 8; | |
b99bd4ef NC |
4246 | } |
4247 | ||
c19d1205 ZW |
4248 | /* Attempt to combine with a previous opcode. We do this because gcc |
4249 | likes to output separate unwind directives for a single block of | |
4250 | registers. */ | |
4251 | if (unwind.opcode_count > 0) | |
b99bd4ef | 4252 | { |
c19d1205 ZW |
4253 | i = unwind.opcodes[unwind.opcode_count - 1]; |
4254 | if ((i & 0xf8) == 0xc0) | |
4255 | { | |
4256 | i &= 7; | |
4257 | /* Only merge if the blocks are contiguous. */ | |
4258 | if (i < 6) | |
4259 | { | |
4260 | if ((mask & 0xfe00) == (1 << 9)) | |
4261 | { | |
4262 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
4263 | unwind.opcode_count--; | |
4264 | } | |
4265 | } | |
4266 | else if (i == 6 && unwind.opcode_count >= 2) | |
4267 | { | |
4268 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
4269 | reg = i >> 4; | |
4270 | i &= 0xf; | |
b99bd4ef | 4271 | |
c19d1205 ZW |
4272 | op = 0xffff << (reg - 1); |
4273 | if (reg > 0 | |
87a1fd79 | 4274 | && ((mask & op) == (1u << (reg - 1)))) |
c19d1205 ZW |
4275 | { |
4276 | op = (1 << (reg + i + 1)) - 1; | |
4277 | op &= ~((1 << reg) - 1); | |
4278 | mask |= op; | |
4279 | unwind.opcode_count -= 2; | |
4280 | } | |
4281 | } | |
4282 | } | |
b99bd4ef NC |
4283 | } |
4284 | ||
c19d1205 ZW |
4285 | hi_reg = 15; |
4286 | /* We want to generate opcodes in the order the registers have been | |
4287 | saved, ie. descending order. */ | |
4288 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 4289 | { |
c19d1205 ZW |
4290 | /* Save registers in blocks. */ |
4291 | if (reg < 0 | |
4292 | || !(mask & (1 << reg))) | |
4293 | { | |
4294 | /* We found an unsaved reg. Generate opcodes to save the | |
5f4273c7 | 4295 | preceding block. */ |
c19d1205 ZW |
4296 | if (reg != hi_reg) |
4297 | { | |
4298 | if (reg == 9) | |
4299 | { | |
4300 | /* Short form. */ | |
4301 | op = 0xc0 | (hi_reg - 10); | |
4302 | add_unwind_opcode (op, 1); | |
4303 | } | |
4304 | else | |
4305 | { | |
4306 | /* Long form. */ | |
4307 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
4308 | add_unwind_opcode (op, 2); | |
4309 | } | |
4310 | } | |
4311 | hi_reg = reg - 1; | |
4312 | } | |
b99bd4ef NC |
4313 | } |
4314 | ||
c19d1205 ZW |
4315 | return; |
4316 | error: | |
4317 | ignore_rest_of_line (); | |
b99bd4ef NC |
4318 | } |
4319 | ||
4320 | static void | |
c19d1205 | 4321 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 4322 | { |
c19d1205 ZW |
4323 | int reg; |
4324 | int hi_reg; | |
4325 | unsigned mask = 0; | |
4326 | valueT op; | |
b99bd4ef | 4327 | |
c19d1205 ZW |
4328 | if (*input_line_pointer == '{') |
4329 | input_line_pointer++; | |
b99bd4ef | 4330 | |
477330fc RM |
4331 | skip_whitespace (input_line_pointer); |
4332 | ||
c19d1205 | 4333 | do |
b99bd4ef | 4334 | { |
dcbf9037 | 4335 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 4336 | |
c19d1205 ZW |
4337 | if (reg == FAIL) |
4338 | { | |
9b7132d3 | 4339 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4340 | goto error; |
4341 | } | |
b99bd4ef | 4342 | |
c19d1205 ZW |
4343 | reg -= 8; |
4344 | if (mask >> reg) | |
4345 | as_tsktsk (_("register list not in ascending order")); | |
4346 | mask |= 1 << reg; | |
b99bd4ef | 4347 | |
c19d1205 ZW |
4348 | if (*input_line_pointer == '-') |
4349 | { | |
4350 | input_line_pointer++; | |
dcbf9037 | 4351 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
c19d1205 ZW |
4352 | if (hi_reg == FAIL) |
4353 | { | |
9b7132d3 | 4354 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4355 | goto error; |
4356 | } | |
4357 | else if (reg >= hi_reg) | |
4358 | { | |
4359 | as_bad (_("bad register range")); | |
4360 | goto error; | |
4361 | } | |
4362 | for (; reg < hi_reg; reg++) | |
4363 | mask |= 1 << reg; | |
4364 | } | |
b99bd4ef | 4365 | } |
c19d1205 | 4366 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 4367 | |
d996d970 | 4368 | skip_past_char (&input_line_pointer, '}'); |
b99bd4ef | 4369 | |
c19d1205 ZW |
4370 | demand_empty_rest_of_line (); |
4371 | ||
708587a4 | 4372 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
4373 | the list. */ |
4374 | flush_pending_unwind (); | |
b99bd4ef | 4375 | |
c19d1205 | 4376 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 4377 | { |
c19d1205 ZW |
4378 | if (mask & (1 << reg)) |
4379 | unwind.frame_size += 4; | |
b99bd4ef | 4380 | } |
c19d1205 ZW |
4381 | op = 0xc700 | mask; |
4382 | add_unwind_opcode (op, 2); | |
4383 | return; | |
4384 | error: | |
4385 | ignore_rest_of_line (); | |
b99bd4ef NC |
4386 | } |
4387 | ||
c19d1205 | 4388 | |
fa073d69 MS |
4389 | /* Parse an unwind_save directive. |
4390 | If the argument is non-zero, this is a .vsave directive. */ | |
c19d1205 | 4391 | |
b99bd4ef | 4392 | static void |
fa073d69 | 4393 | s_arm_unwind_save (int arch_v6) |
b99bd4ef | 4394 | { |
c19d1205 ZW |
4395 | char *peek; |
4396 | struct reg_entry *reg; | |
4397 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 4398 | |
921e5f0a | 4399 | if (!unwind.proc_start) |
c921be7d | 4400 | as_bad (MISSING_FNSTART); |
921e5f0a | 4401 | |
c19d1205 ZW |
4402 | /* Figure out what sort of save we have. */ |
4403 | peek = input_line_pointer; | |
b99bd4ef | 4404 | |
c19d1205 | 4405 | if (*peek == '{') |
b99bd4ef | 4406 | { |
c19d1205 ZW |
4407 | had_brace = TRUE; |
4408 | peek++; | |
b99bd4ef NC |
4409 | } |
4410 | ||
c19d1205 | 4411 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 4412 | |
c19d1205 | 4413 | if (!reg) |
b99bd4ef | 4414 | { |
c19d1205 ZW |
4415 | as_bad (_("register expected")); |
4416 | ignore_rest_of_line (); | |
b99bd4ef NC |
4417 | return; |
4418 | } | |
4419 | ||
c19d1205 | 4420 | switch (reg->type) |
b99bd4ef | 4421 | { |
c19d1205 ZW |
4422 | case REG_TYPE_FN: |
4423 | if (had_brace) | |
4424 | { | |
4425 | as_bad (_("FPA .unwind_save does not take a register list")); | |
4426 | ignore_rest_of_line (); | |
4427 | return; | |
4428 | } | |
93ac2687 | 4429 | input_line_pointer = peek; |
c19d1205 | 4430 | s_arm_unwind_save_fpa (reg->number); |
b99bd4ef | 4431 | return; |
c19d1205 | 4432 | |
1f5afe1c NC |
4433 | case REG_TYPE_RN: |
4434 | s_arm_unwind_save_core (); | |
4435 | return; | |
4436 | ||
fa073d69 MS |
4437 | case REG_TYPE_VFD: |
4438 | if (arch_v6) | |
477330fc | 4439 | s_arm_unwind_save_vfp_armv6 (); |
fa073d69 | 4440 | else |
477330fc | 4441 | s_arm_unwind_save_vfp (); |
fa073d69 | 4442 | return; |
1f5afe1c NC |
4443 | |
4444 | case REG_TYPE_MMXWR: | |
4445 | s_arm_unwind_save_mmxwr (); | |
4446 | return; | |
4447 | ||
4448 | case REG_TYPE_MMXWCG: | |
4449 | s_arm_unwind_save_mmxwcg (); | |
4450 | return; | |
c19d1205 ZW |
4451 | |
4452 | default: | |
4453 | as_bad (_(".unwind_save does not support this kind of register")); | |
4454 | ignore_rest_of_line (); | |
b99bd4ef | 4455 | } |
c19d1205 | 4456 | } |
b99bd4ef | 4457 | |
b99bd4ef | 4458 | |
c19d1205 ZW |
4459 | /* Parse an unwind_movsp directive. */ |
4460 | ||
4461 | static void | |
4462 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
4463 | { | |
4464 | int reg; | |
4465 | valueT op; | |
4fa3602b | 4466 | int offset; |
c19d1205 | 4467 | |
921e5f0a | 4468 | if (!unwind.proc_start) |
c921be7d | 4469 | as_bad (MISSING_FNSTART); |
921e5f0a | 4470 | |
dcbf9037 | 4471 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 | 4472 | if (reg == FAIL) |
b99bd4ef | 4473 | { |
9b7132d3 | 4474 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 | 4475 | ignore_rest_of_line (); |
b99bd4ef NC |
4476 | return; |
4477 | } | |
4fa3602b PB |
4478 | |
4479 | /* Optional constant. */ | |
4480 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4481 | { | |
4482 | if (immediate_for_directive (&offset) == FAIL) | |
4483 | return; | |
4484 | } | |
4485 | else | |
4486 | offset = 0; | |
4487 | ||
c19d1205 | 4488 | demand_empty_rest_of_line (); |
b99bd4ef | 4489 | |
c19d1205 | 4490 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 4491 | { |
c19d1205 | 4492 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
4493 | return; |
4494 | } | |
4495 | ||
c19d1205 ZW |
4496 | if (unwind.fp_reg != REG_SP) |
4497 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 4498 | |
c19d1205 ZW |
4499 | /* Generate opcode to restore the value. */ |
4500 | op = 0x90 | reg; | |
4501 | add_unwind_opcode (op, 1); | |
4502 | ||
4503 | /* Record the information for later. */ | |
4504 | unwind.fp_reg = reg; | |
4fa3602b | 4505 | unwind.fp_offset = unwind.frame_size - offset; |
c19d1205 | 4506 | unwind.sp_restored = 1; |
b05fe5cf ZW |
4507 | } |
4508 | ||
c19d1205 ZW |
4509 | /* Parse an unwind_pad directive. */ |
4510 | ||
b05fe5cf | 4511 | static void |
c19d1205 | 4512 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 4513 | { |
c19d1205 | 4514 | int offset; |
b05fe5cf | 4515 | |
921e5f0a | 4516 | if (!unwind.proc_start) |
c921be7d | 4517 | as_bad (MISSING_FNSTART); |
921e5f0a | 4518 | |
c19d1205 ZW |
4519 | if (immediate_for_directive (&offset) == FAIL) |
4520 | return; | |
b99bd4ef | 4521 | |
c19d1205 ZW |
4522 | if (offset & 3) |
4523 | { | |
4524 | as_bad (_("stack increment must be multiple of 4")); | |
4525 | ignore_rest_of_line (); | |
4526 | return; | |
4527 | } | |
b99bd4ef | 4528 | |
c19d1205 ZW |
4529 | /* Don't generate any opcodes, just record the details for later. */ |
4530 | unwind.frame_size += offset; | |
4531 | unwind.pending_offset += offset; | |
4532 | ||
4533 | demand_empty_rest_of_line (); | |
4534 | } | |
4535 | ||
4536 | /* Parse an unwind_setfp directive. */ | |
4537 | ||
4538 | static void | |
4539 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 4540 | { |
c19d1205 ZW |
4541 | int sp_reg; |
4542 | int fp_reg; | |
4543 | int offset; | |
4544 | ||
921e5f0a | 4545 | if (!unwind.proc_start) |
c921be7d | 4546 | as_bad (MISSING_FNSTART); |
921e5f0a | 4547 | |
dcbf9037 | 4548 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 ZW |
4549 | if (skip_past_comma (&input_line_pointer) == FAIL) |
4550 | sp_reg = FAIL; | |
4551 | else | |
dcbf9037 | 4552 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
b99bd4ef | 4553 | |
c19d1205 ZW |
4554 | if (fp_reg == FAIL || sp_reg == FAIL) |
4555 | { | |
4556 | as_bad (_("expected <reg>, <reg>")); | |
4557 | ignore_rest_of_line (); | |
4558 | return; | |
4559 | } | |
b99bd4ef | 4560 | |
c19d1205 ZW |
4561 | /* Optional constant. */ |
4562 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4563 | { | |
4564 | if (immediate_for_directive (&offset) == FAIL) | |
4565 | return; | |
4566 | } | |
4567 | else | |
4568 | offset = 0; | |
a737bd4d | 4569 | |
c19d1205 | 4570 | demand_empty_rest_of_line (); |
a737bd4d | 4571 | |
fdfde340 | 4572 | if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) |
a737bd4d | 4573 | { |
c19d1205 ZW |
4574 | as_bad (_("register must be either sp or set by a previous" |
4575 | "unwind_movsp directive")); | |
4576 | return; | |
a737bd4d NC |
4577 | } |
4578 | ||
c19d1205 ZW |
4579 | /* Don't generate any opcodes, just record the information for later. */ |
4580 | unwind.fp_reg = fp_reg; | |
4581 | unwind.fp_used = 1; | |
fdfde340 | 4582 | if (sp_reg == REG_SP) |
c19d1205 ZW |
4583 | unwind.fp_offset = unwind.frame_size - offset; |
4584 | else | |
4585 | unwind.fp_offset -= offset; | |
a737bd4d NC |
4586 | } |
4587 | ||
c19d1205 ZW |
4588 | /* Parse an unwind_raw directive. */ |
4589 | ||
4590 | static void | |
4591 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 4592 | { |
c19d1205 | 4593 | expressionS exp; |
708587a4 | 4594 | /* This is an arbitrary limit. */ |
c19d1205 ZW |
4595 | unsigned char op[16]; |
4596 | int count; | |
a737bd4d | 4597 | |
921e5f0a | 4598 | if (!unwind.proc_start) |
c921be7d | 4599 | as_bad (MISSING_FNSTART); |
921e5f0a | 4600 | |
c19d1205 ZW |
4601 | expression (&exp); |
4602 | if (exp.X_op == O_constant | |
4603 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 4604 | { |
c19d1205 ZW |
4605 | unwind.frame_size += exp.X_add_number; |
4606 | expression (&exp); | |
4607 | } | |
4608 | else | |
4609 | exp.X_op = O_illegal; | |
a737bd4d | 4610 | |
c19d1205 ZW |
4611 | if (exp.X_op != O_constant) |
4612 | { | |
4613 | as_bad (_("expected <offset>, <opcode>")); | |
4614 | ignore_rest_of_line (); | |
4615 | return; | |
4616 | } | |
a737bd4d | 4617 | |
c19d1205 | 4618 | count = 0; |
a737bd4d | 4619 | |
c19d1205 ZW |
4620 | /* Parse the opcode. */ |
4621 | for (;;) | |
4622 | { | |
4623 | if (count >= 16) | |
4624 | { | |
4625 | as_bad (_("unwind opcode too long")); | |
4626 | ignore_rest_of_line (); | |
a737bd4d | 4627 | } |
c19d1205 | 4628 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 4629 | { |
c19d1205 ZW |
4630 | as_bad (_("invalid unwind opcode")); |
4631 | ignore_rest_of_line (); | |
4632 | return; | |
a737bd4d | 4633 | } |
c19d1205 | 4634 | op[count++] = exp.X_add_number; |
a737bd4d | 4635 | |
c19d1205 ZW |
4636 | /* Parse the next byte. */ |
4637 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
4638 | break; | |
a737bd4d | 4639 | |
c19d1205 ZW |
4640 | expression (&exp); |
4641 | } | |
b99bd4ef | 4642 | |
c19d1205 ZW |
4643 | /* Add the opcode bytes in reverse order. */ |
4644 | while (count--) | |
4645 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 4646 | |
c19d1205 | 4647 | demand_empty_rest_of_line (); |
b99bd4ef | 4648 | } |
ee065d83 PB |
4649 | |
4650 | ||
4651 | /* Parse a .eabi_attribute directive. */ | |
4652 | ||
4653 | static void | |
4654 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) | |
4655 | { | |
0420f52b | 4656 | int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC); |
ee3c0378 AS |
4657 | |
4658 | if (tag < NUM_KNOWN_OBJ_ATTRIBUTES) | |
4659 | attributes_set_explicitly[tag] = 1; | |
ee065d83 PB |
4660 | } |
4661 | ||
0855e32b NS |
4662 | /* Emit a tls fix for the symbol. */ |
4663 | ||
4664 | static void | |
4665 | s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED) | |
4666 | { | |
4667 | char *p; | |
4668 | expressionS exp; | |
4669 | #ifdef md_flush_pending_output | |
4670 | md_flush_pending_output (); | |
4671 | #endif | |
4672 | ||
4673 | #ifdef md_cons_align | |
4674 | md_cons_align (4); | |
4675 | #endif | |
4676 | ||
4677 | /* Since we're just labelling the code, there's no need to define a | |
4678 | mapping symbol. */ | |
4679 | expression (&exp); | |
4680 | p = obstack_next_free (&frchain_now->frch_obstack); | |
4681 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0, | |
4682 | thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
4683 | : BFD_RELOC_ARM_TLS_DESCSEQ); | |
4684 | } | |
cdf9ccec | 4685 | #endif /* OBJ_ELF */ |
0855e32b | 4686 | |
ee065d83 | 4687 | static void s_arm_arch (int); |
7a1d4c38 | 4688 | static void s_arm_object_arch (int); |
ee065d83 PB |
4689 | static void s_arm_cpu (int); |
4690 | static void s_arm_fpu (int); | |
69133863 | 4691 | static void s_arm_arch_extension (int); |
b99bd4ef | 4692 | |
f0927246 NC |
4693 | #ifdef TE_PE |
4694 | ||
4695 | static void | |
5f4273c7 | 4696 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
f0927246 NC |
4697 | { |
4698 | expressionS exp; | |
4699 | ||
4700 | do | |
4701 | { | |
4702 | expression (&exp); | |
4703 | if (exp.X_op == O_symbol) | |
4704 | exp.X_op = O_secrel; | |
4705 | ||
4706 | emit_expr (&exp, 4); | |
4707 | } | |
4708 | while (*input_line_pointer++ == ','); | |
4709 | ||
4710 | input_line_pointer--; | |
4711 | demand_empty_rest_of_line (); | |
4712 | } | |
4713 | #endif /* TE_PE */ | |
4714 | ||
c19d1205 ZW |
4715 | /* This table describes all the machine specific pseudo-ops the assembler |
4716 | has to support. The fields are: | |
4717 | pseudo-op name without dot | |
4718 | function to call to execute this pseudo-op | |
4719 | Integer arg to pass to the function. */ | |
b99bd4ef | 4720 | |
c19d1205 | 4721 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 4722 | { |
c19d1205 ZW |
4723 | /* Never called because '.req' does not start a line. */ |
4724 | { "req", s_req, 0 }, | |
dcbf9037 JB |
4725 | /* Following two are likewise never called. */ |
4726 | { "dn", s_dn, 0 }, | |
4727 | { "qn", s_qn, 0 }, | |
c19d1205 ZW |
4728 | { "unreq", s_unreq, 0 }, |
4729 | { "bss", s_bss, 0 }, | |
db2ed2e0 | 4730 | { "align", s_align_ptwo, 2 }, |
c19d1205 ZW |
4731 | { "arm", s_arm, 0 }, |
4732 | { "thumb", s_thumb, 0 }, | |
4733 | { "code", s_code, 0 }, | |
4734 | { "force_thumb", s_force_thumb, 0 }, | |
4735 | { "thumb_func", s_thumb_func, 0 }, | |
4736 | { "thumb_set", s_thumb_set, 0 }, | |
4737 | { "even", s_even, 0 }, | |
4738 | { "ltorg", s_ltorg, 0 }, | |
4739 | { "pool", s_ltorg, 0 }, | |
4740 | { "syntax", s_syntax, 0 }, | |
8463be01 PB |
4741 | { "cpu", s_arm_cpu, 0 }, |
4742 | { "arch", s_arm_arch, 0 }, | |
7a1d4c38 | 4743 | { "object_arch", s_arm_object_arch, 0 }, |
8463be01 | 4744 | { "fpu", s_arm_fpu, 0 }, |
69133863 | 4745 | { "arch_extension", s_arm_arch_extension, 0 }, |
c19d1205 | 4746 | #ifdef OBJ_ELF |
c921be7d NC |
4747 | { "word", s_arm_elf_cons, 4 }, |
4748 | { "long", s_arm_elf_cons, 4 }, | |
4749 | { "inst.n", s_arm_elf_inst, 2 }, | |
4750 | { "inst.w", s_arm_elf_inst, 4 }, | |
4751 | { "inst", s_arm_elf_inst, 0 }, | |
4752 | { "rel31", s_arm_rel31, 0 }, | |
c19d1205 ZW |
4753 | { "fnstart", s_arm_unwind_fnstart, 0 }, |
4754 | { "fnend", s_arm_unwind_fnend, 0 }, | |
4755 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
4756 | { "personality", s_arm_unwind_personality, 0 }, | |
4757 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
4758 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
4759 | { "save", s_arm_unwind_save, 0 }, | |
fa073d69 | 4760 | { "vsave", s_arm_unwind_save, 1 }, |
c19d1205 ZW |
4761 | { "movsp", s_arm_unwind_movsp, 0 }, |
4762 | { "pad", s_arm_unwind_pad, 0 }, | |
4763 | { "setfp", s_arm_unwind_setfp, 0 }, | |
4764 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
ee065d83 | 4765 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, |
0855e32b | 4766 | { "tlsdescseq", s_arm_tls_descseq, 0 }, |
c19d1205 ZW |
4767 | #else |
4768 | { "word", cons, 4}, | |
f0927246 NC |
4769 | |
4770 | /* These are used for dwarf. */ | |
4771 | {"2byte", cons, 2}, | |
4772 | {"4byte", cons, 4}, | |
4773 | {"8byte", cons, 8}, | |
4774 | /* These are used for dwarf2. */ | |
68d20676 | 4775 | { "file", dwarf2_directive_file, 0 }, |
f0927246 NC |
4776 | { "loc", dwarf2_directive_loc, 0 }, |
4777 | { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, | |
c19d1205 ZW |
4778 | #endif |
4779 | { "extend", float_cons, 'x' }, | |
4780 | { "ldouble", float_cons, 'x' }, | |
4781 | { "packed", float_cons, 'p' }, | |
f0927246 NC |
4782 | #ifdef TE_PE |
4783 | {"secrel32", pe_directive_secrel, 0}, | |
4784 | #endif | |
2e6976a8 DG |
4785 | |
4786 | /* These are for compatibility with CodeComposer Studio. */ | |
4787 | {"ref", s_ccs_ref, 0}, | |
4788 | {"def", s_ccs_def, 0}, | |
4789 | {"asmfunc", s_ccs_asmfunc, 0}, | |
4790 | {"endasmfunc", s_ccs_endasmfunc, 0}, | |
4791 | ||
c19d1205 ZW |
4792 | { 0, 0, 0 } |
4793 | }; | |
4794 | \f | |
4795 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 4796 | |
c19d1205 ZW |
4797 | /* Generic immediate-value read function for use in insn parsing. |
4798 | STR points to the beginning of the immediate (the leading #); | |
4799 | VAL receives the value; if the value is outside [MIN, MAX] | |
4800 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
4801 | optional. */ | |
b99bd4ef | 4802 | |
c19d1205 ZW |
4803 | static int |
4804 | parse_immediate (char **str, int *val, int min, int max, | |
4805 | bfd_boolean prefix_opt) | |
4806 | { | |
4807 | expressionS exp; | |
0198d5e6 | 4808 | |
c19d1205 ZW |
4809 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); |
4810 | if (exp.X_op != O_constant) | |
b99bd4ef | 4811 | { |
c19d1205 ZW |
4812 | inst.error = _("constant expression required"); |
4813 | return FAIL; | |
4814 | } | |
b99bd4ef | 4815 | |
c19d1205 ZW |
4816 | if (exp.X_add_number < min || exp.X_add_number > max) |
4817 | { | |
4818 | inst.error = _("immediate value out of range"); | |
4819 | return FAIL; | |
4820 | } | |
b99bd4ef | 4821 | |
c19d1205 ZW |
4822 | *val = exp.X_add_number; |
4823 | return SUCCESS; | |
4824 | } | |
b99bd4ef | 4825 | |
5287ad62 | 4826 | /* Less-generic immediate-value read function with the possibility of loading a |
036dc3f7 | 4827 | big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate |
5287ad62 JB |
4828 | instructions. Puts the result directly in inst.operands[i]. */ |
4829 | ||
4830 | static int | |
8335d6aa JW |
4831 | parse_big_immediate (char **str, int i, expressionS *in_exp, |
4832 | bfd_boolean allow_symbol_p) | |
5287ad62 JB |
4833 | { |
4834 | expressionS exp; | |
8335d6aa | 4835 | expressionS *exp_p = in_exp ? in_exp : &exp; |
5287ad62 JB |
4836 | char *ptr = *str; |
4837 | ||
8335d6aa | 4838 | my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG); |
5287ad62 | 4839 | |
8335d6aa | 4840 | if (exp_p->X_op == O_constant) |
036dc3f7 | 4841 | { |
8335d6aa | 4842 | inst.operands[i].imm = exp_p->X_add_number & 0xffffffff; |
036dc3f7 PB |
4843 | /* If we're on a 64-bit host, then a 64-bit number can be returned using |
4844 | O_constant. We have to be careful not to break compilation for | |
4845 | 32-bit X_add_number, though. */ | |
8335d6aa | 4846 | if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0) |
036dc3f7 | 4847 | { |
8335d6aa JW |
4848 | /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */ |
4849 | inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16) | |
4850 | & 0xffffffff); | |
036dc3f7 PB |
4851 | inst.operands[i].regisimm = 1; |
4852 | } | |
4853 | } | |
8335d6aa JW |
4854 | else if (exp_p->X_op == O_big |
4855 | && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32) | |
5287ad62 JB |
4856 | { |
4857 | unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; | |
95b75c01 | 4858 | |
5287ad62 | 4859 | /* Bignums have their least significant bits in |
477330fc RM |
4860 | generic_bignum[0]. Make sure we put 32 bits in imm and |
4861 | 32 bits in reg, in a (hopefully) portable way. */ | |
9c2799c2 | 4862 | gas_assert (parts != 0); |
95b75c01 NC |
4863 | |
4864 | /* Make sure that the number is not too big. | |
4865 | PR 11972: Bignums can now be sign-extended to the | |
4866 | size of a .octa so check that the out of range bits | |
4867 | are all zero or all one. */ | |
8335d6aa | 4868 | if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64) |
95b75c01 NC |
4869 | { |
4870 | LITTLENUM_TYPE m = -1; | |
4871 | ||
4872 | if (generic_bignum[parts * 2] != 0 | |
4873 | && generic_bignum[parts * 2] != m) | |
4874 | return FAIL; | |
4875 | ||
8335d6aa | 4876 | for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++) |
95b75c01 NC |
4877 | if (generic_bignum[j] != generic_bignum[j-1]) |
4878 | return FAIL; | |
4879 | } | |
4880 | ||
5287ad62 JB |
4881 | inst.operands[i].imm = 0; |
4882 | for (j = 0; j < parts; j++, idx++) | |
477330fc RM |
4883 | inst.operands[i].imm |= generic_bignum[idx] |
4884 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
5287ad62 JB |
4885 | inst.operands[i].reg = 0; |
4886 | for (j = 0; j < parts; j++, idx++) | |
477330fc RM |
4887 | inst.operands[i].reg |= generic_bignum[idx] |
4888 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
5287ad62 JB |
4889 | inst.operands[i].regisimm = 1; |
4890 | } | |
8335d6aa | 4891 | else if (!(exp_p->X_op == O_symbol && allow_symbol_p)) |
5287ad62 | 4892 | return FAIL; |
5f4273c7 | 4893 | |
5287ad62 JB |
4894 | *str = ptr; |
4895 | ||
4896 | return SUCCESS; | |
4897 | } | |
4898 | ||
c19d1205 ZW |
4899 | /* Returns the pseudo-register number of an FPA immediate constant, |
4900 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 4901 | |
c19d1205 ZW |
4902 | static int |
4903 | parse_fpa_immediate (char ** str) | |
4904 | { | |
4905 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4906 | char * save_in; | |
4907 | expressionS exp; | |
4908 | int i; | |
4909 | int j; | |
b99bd4ef | 4910 | |
c19d1205 ZW |
4911 | /* First try and match exact strings, this is to guarantee |
4912 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 4913 | |
c19d1205 ZW |
4914 | for (i = 0; fp_const[i]; i++) |
4915 | { | |
4916 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 4917 | { |
c19d1205 | 4918 | char *start = *str; |
b99bd4ef | 4919 | |
c19d1205 ZW |
4920 | *str += strlen (fp_const[i]); |
4921 | if (is_end_of_line[(unsigned char) **str]) | |
4922 | return i + 8; | |
4923 | *str = start; | |
4924 | } | |
4925 | } | |
b99bd4ef | 4926 | |
c19d1205 ZW |
4927 | /* Just because we didn't get a match doesn't mean that the constant |
4928 | isn't valid, just that it is in a format that we don't | |
4929 | automatically recognize. Try parsing it with the standard | |
4930 | expression routines. */ | |
b99bd4ef | 4931 | |
c19d1205 | 4932 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 4933 | |
c19d1205 ZW |
4934 | /* Look for a raw floating point number. */ |
4935 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
4936 | && is_end_of_line[(unsigned char) *save_in]) | |
4937 | { | |
4938 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4939 | { | |
4940 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 4941 | { |
c19d1205 ZW |
4942 | if (words[j] != fp_values[i][j]) |
4943 | break; | |
b99bd4ef NC |
4944 | } |
4945 | ||
c19d1205 | 4946 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 4947 | { |
c19d1205 ZW |
4948 | *str = save_in; |
4949 | return i + 8; | |
b99bd4ef NC |
4950 | } |
4951 | } | |
4952 | } | |
b99bd4ef | 4953 | |
c19d1205 ZW |
4954 | /* Try and parse a more complex expression, this will probably fail |
4955 | unless the code uses a floating point prefix (eg "0f"). */ | |
4956 | save_in = input_line_pointer; | |
4957 | input_line_pointer = *str; | |
4958 | if (expression (&exp) == absolute_section | |
4959 | && exp.X_op == O_big | |
4960 | && exp.X_add_number < 0) | |
4961 | { | |
4962 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
4963 | Ditto for 15. */ | |
ba592044 AM |
4964 | #define X_PRECISION 5 |
4965 | #define E_PRECISION 15L | |
4966 | if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0) | |
c19d1205 ZW |
4967 | { |
4968 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4969 | { | |
4970 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
4971 | { | |
4972 | if (words[j] != fp_values[i][j]) | |
4973 | break; | |
4974 | } | |
b99bd4ef | 4975 | |
c19d1205 ZW |
4976 | if (j == MAX_LITTLENUMS) |
4977 | { | |
4978 | *str = input_line_pointer; | |
4979 | input_line_pointer = save_in; | |
4980 | return i + 8; | |
4981 | } | |
4982 | } | |
4983 | } | |
b99bd4ef NC |
4984 | } |
4985 | ||
c19d1205 ZW |
4986 | *str = input_line_pointer; |
4987 | input_line_pointer = save_in; | |
4988 | inst.error = _("invalid FPA immediate expression"); | |
4989 | return FAIL; | |
b99bd4ef NC |
4990 | } |
4991 | ||
136da414 JB |
4992 | /* Returns 1 if a number has "quarter-precision" float format |
4993 | 0baBbbbbbc defgh000 00000000 00000000. */ | |
4994 | ||
4995 | static int | |
4996 | is_quarter_float (unsigned imm) | |
4997 | { | |
4998 | int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; | |
4999 | return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; | |
5000 | } | |
5001 | ||
aacf0b33 KT |
5002 | |
5003 | /* Detect the presence of a floating point or integer zero constant, | |
5004 | i.e. #0.0 or #0. */ | |
5005 | ||
5006 | static bfd_boolean | |
5007 | parse_ifimm_zero (char **in) | |
5008 | { | |
5009 | int error_code; | |
5010 | ||
5011 | if (!is_immediate_prefix (**in)) | |
3c6452ae TP |
5012 | { |
5013 | /* In unified syntax, all prefixes are optional. */ | |
5014 | if (!unified_syntax) | |
5015 | return FALSE; | |
5016 | } | |
5017 | else | |
5018 | ++*in; | |
0900a05b JW |
5019 | |
5020 | /* Accept #0x0 as a synonym for #0. */ | |
5021 | if (strncmp (*in, "0x", 2) == 0) | |
5022 | { | |
5023 | int val; | |
5024 | if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL) | |
5025 | return FALSE; | |
5026 | return TRUE; | |
5027 | } | |
5028 | ||
aacf0b33 KT |
5029 | error_code = atof_generic (in, ".", EXP_CHARS, |
5030 | &generic_floating_point_number); | |
5031 | ||
5032 | if (!error_code | |
5033 | && generic_floating_point_number.sign == '+' | |
5034 | && (generic_floating_point_number.low | |
5035 | > generic_floating_point_number.leader)) | |
5036 | return TRUE; | |
5037 | ||
5038 | return FALSE; | |
5039 | } | |
5040 | ||
136da414 JB |
5041 | /* Parse an 8-bit "quarter-precision" floating point number of the form: |
5042 | 0baBbbbbbc defgh000 00000000 00000000. | |
c96612cc JB |
5043 | The zero and minus-zero cases need special handling, since they can't be |
5044 | encoded in the "quarter-precision" float format, but can nonetheless be | |
5045 | loaded as integer constants. */ | |
136da414 JB |
5046 | |
5047 | static unsigned | |
5048 | parse_qfloat_immediate (char **ccp, int *immed) | |
5049 | { | |
5050 | char *str = *ccp; | |
c96612cc | 5051 | char *fpnum; |
136da414 | 5052 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
c96612cc | 5053 | int found_fpchar = 0; |
5f4273c7 | 5054 | |
136da414 | 5055 | skip_past_char (&str, '#'); |
5f4273c7 | 5056 | |
c96612cc JB |
5057 | /* We must not accidentally parse an integer as a floating-point number. Make |
5058 | sure that the value we parse is not an integer by checking for special | |
5059 | characters '.' or 'e'. | |
5060 | FIXME: This is a horrible hack, but doing better is tricky because type | |
5061 | information isn't in a very usable state at parse time. */ | |
5062 | fpnum = str; | |
5063 | skip_whitespace (fpnum); | |
5064 | ||
5065 | if (strncmp (fpnum, "0x", 2) == 0) | |
5066 | return FAIL; | |
5067 | else | |
5068 | { | |
5069 | for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) | |
477330fc RM |
5070 | if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') |
5071 | { | |
5072 | found_fpchar = 1; | |
5073 | break; | |
5074 | } | |
c96612cc JB |
5075 | |
5076 | if (!found_fpchar) | |
477330fc | 5077 | return FAIL; |
c96612cc | 5078 | } |
5f4273c7 | 5079 | |
136da414 JB |
5080 | if ((str = atof_ieee (str, 's', words)) != NULL) |
5081 | { | |
5082 | unsigned fpword = 0; | |
5083 | int i; | |
5f4273c7 | 5084 | |
136da414 JB |
5085 | /* Our FP word must be 32 bits (single-precision FP). */ |
5086 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) | |
477330fc RM |
5087 | { |
5088 | fpword <<= LITTLENUM_NUMBER_OF_BITS; | |
5089 | fpword |= words[i]; | |
5090 | } | |
5f4273c7 | 5091 | |
c96612cc | 5092 | if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) |
477330fc | 5093 | *immed = fpword; |
136da414 | 5094 | else |
477330fc | 5095 | return FAIL; |
136da414 JB |
5096 | |
5097 | *ccp = str; | |
5f4273c7 | 5098 | |
136da414 JB |
5099 | return SUCCESS; |
5100 | } | |
5f4273c7 | 5101 | |
136da414 JB |
5102 | return FAIL; |
5103 | } | |
5104 | ||
c19d1205 ZW |
5105 | /* Shift operands. */ |
5106 | enum shift_kind | |
b99bd4ef | 5107 | { |
c19d1205 ZW |
5108 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX |
5109 | }; | |
b99bd4ef | 5110 | |
c19d1205 ZW |
5111 | struct asm_shift_name |
5112 | { | |
5113 | const char *name; | |
5114 | enum shift_kind kind; | |
5115 | }; | |
b99bd4ef | 5116 | |
c19d1205 ZW |
5117 | /* Third argument to parse_shift. */ |
5118 | enum parse_shift_mode | |
5119 | { | |
5120 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
5121 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
5122 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
5123 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
5124 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
5125 | }; | |
b99bd4ef | 5126 | |
c19d1205 ZW |
5127 | /* Parse a <shift> specifier on an ARM data processing instruction. |
5128 | This has three forms: | |
b99bd4ef | 5129 | |
c19d1205 ZW |
5130 | (LSL|LSR|ASL|ASR|ROR) Rs |
5131 | (LSL|LSR|ASL|ASR|ROR) #imm | |
5132 | RRX | |
b99bd4ef | 5133 | |
c19d1205 ZW |
5134 | Note that ASL is assimilated to LSL in the instruction encoding, and |
5135 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 5136 | |
c19d1205 ZW |
5137 | static int |
5138 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 5139 | { |
c19d1205 ZW |
5140 | const struct asm_shift_name *shift_name; |
5141 | enum shift_kind shift; | |
5142 | char *s = *str; | |
5143 | char *p = s; | |
5144 | int reg; | |
b99bd4ef | 5145 | |
c19d1205 ZW |
5146 | for (p = *str; ISALPHA (*p); p++) |
5147 | ; | |
b99bd4ef | 5148 | |
c19d1205 | 5149 | if (p == *str) |
b99bd4ef | 5150 | { |
c19d1205 ZW |
5151 | inst.error = _("shift expression expected"); |
5152 | return FAIL; | |
b99bd4ef NC |
5153 | } |
5154 | ||
21d799b5 | 5155 | shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str, |
477330fc | 5156 | p - *str); |
c19d1205 ZW |
5157 | |
5158 | if (shift_name == NULL) | |
b99bd4ef | 5159 | { |
c19d1205 ZW |
5160 | inst.error = _("shift expression expected"); |
5161 | return FAIL; | |
b99bd4ef NC |
5162 | } |
5163 | ||
c19d1205 | 5164 | shift = shift_name->kind; |
b99bd4ef | 5165 | |
c19d1205 ZW |
5166 | switch (mode) |
5167 | { | |
5168 | case NO_SHIFT_RESTRICT: | |
5169 | case SHIFT_IMMEDIATE: break; | |
b99bd4ef | 5170 | |
c19d1205 ZW |
5171 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
5172 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
5173 | { | |
5174 | inst.error = _("'LSL' or 'ASR' required"); | |
5175 | return FAIL; | |
5176 | } | |
5177 | break; | |
b99bd4ef | 5178 | |
c19d1205 ZW |
5179 | case SHIFT_LSL_IMMEDIATE: |
5180 | if (shift != SHIFT_LSL) | |
5181 | { | |
5182 | inst.error = _("'LSL' required"); | |
5183 | return FAIL; | |
5184 | } | |
5185 | break; | |
b99bd4ef | 5186 | |
c19d1205 ZW |
5187 | case SHIFT_ASR_IMMEDIATE: |
5188 | if (shift != SHIFT_ASR) | |
5189 | { | |
5190 | inst.error = _("'ASR' required"); | |
5191 | return FAIL; | |
5192 | } | |
5193 | break; | |
b99bd4ef | 5194 | |
c19d1205 ZW |
5195 | default: abort (); |
5196 | } | |
b99bd4ef | 5197 | |
c19d1205 ZW |
5198 | if (shift != SHIFT_RRX) |
5199 | { | |
5200 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
5201 | skip_whitespace (p); | |
b99bd4ef | 5202 | |
c19d1205 | 5203 | if (mode == NO_SHIFT_RESTRICT |
dcbf9037 | 5204 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
5205 | { |
5206 | inst.operands[i].imm = reg; | |
5207 | inst.operands[i].immisreg = 1; | |
5208 | } | |
5209 | else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
5210 | return FAIL; | |
5211 | } | |
5212 | inst.operands[i].shift_kind = shift; | |
5213 | inst.operands[i].shifted = 1; | |
5214 | *str = p; | |
5215 | return SUCCESS; | |
b99bd4ef NC |
5216 | } |
5217 | ||
c19d1205 | 5218 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 5219 | |
c19d1205 ZW |
5220 | #<immediate> |
5221 | #<immediate>, <rotate> | |
5222 | <Rm> | |
5223 | <Rm>, <shift> | |
b99bd4ef | 5224 | |
c19d1205 ZW |
5225 | where <shift> is defined by parse_shift above, and <rotate> is a |
5226 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 5227 | is deferred to md_apply_fix. */ |
b99bd4ef | 5228 | |
c19d1205 ZW |
5229 | static int |
5230 | parse_shifter_operand (char **str, int i) | |
5231 | { | |
5232 | int value; | |
91d6fa6a | 5233 | expressionS exp; |
b99bd4ef | 5234 | |
dcbf9037 | 5235 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
5236 | { |
5237 | inst.operands[i].reg = value; | |
5238 | inst.operands[i].isreg = 1; | |
b99bd4ef | 5239 | |
c19d1205 ZW |
5240 | /* parse_shift will override this if appropriate */ |
5241 | inst.reloc.exp.X_op = O_constant; | |
5242 | inst.reloc.exp.X_add_number = 0; | |
b99bd4ef | 5243 | |
c19d1205 ZW |
5244 | if (skip_past_comma (str) == FAIL) |
5245 | return SUCCESS; | |
b99bd4ef | 5246 | |
c19d1205 ZW |
5247 | /* Shift operation on register. */ |
5248 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
5249 | } |
5250 | ||
c19d1205 ZW |
5251 | if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) |
5252 | return FAIL; | |
b99bd4ef | 5253 | |
c19d1205 | 5254 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 5255 | { |
c19d1205 | 5256 | /* #x, y -- ie explicit rotation by Y. */ |
91d6fa6a | 5257 | if (my_get_expression (&exp, str, GE_NO_PREFIX)) |
c19d1205 | 5258 | return FAIL; |
b99bd4ef | 5259 | |
91d6fa6a | 5260 | if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant) |
c19d1205 ZW |
5261 | { |
5262 | inst.error = _("constant expression expected"); | |
5263 | return FAIL; | |
5264 | } | |
b99bd4ef | 5265 | |
91d6fa6a | 5266 | value = exp.X_add_number; |
c19d1205 ZW |
5267 | if (value < 0 || value > 30 || value % 2 != 0) |
5268 | { | |
5269 | inst.error = _("invalid rotation"); | |
5270 | return FAIL; | |
5271 | } | |
5272 | if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) | |
5273 | { | |
5274 | inst.error = _("invalid constant"); | |
5275 | return FAIL; | |
5276 | } | |
09d92015 | 5277 | |
a415b1cd JB |
5278 | /* Encode as specified. */ |
5279 | inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7; | |
5280 | return SUCCESS; | |
09d92015 MM |
5281 | } |
5282 | ||
c19d1205 ZW |
5283 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; |
5284 | inst.reloc.pc_rel = 0; | |
5285 | return SUCCESS; | |
09d92015 MM |
5286 | } |
5287 | ||
4962c51a MS |
5288 | /* Group relocation information. Each entry in the table contains the |
5289 | textual name of the relocation as may appear in assembler source | |
5290 | and must end with a colon. | |
5291 | Along with this textual name are the relocation codes to be used if | |
5292 | the corresponding instruction is an ALU instruction (ADD or SUB only), | |
5293 | an LDR, an LDRS, or an LDC. */ | |
5294 | ||
5295 | struct group_reloc_table_entry | |
5296 | { | |
5297 | const char *name; | |
5298 | int alu_code; | |
5299 | int ldr_code; | |
5300 | int ldrs_code; | |
5301 | int ldc_code; | |
5302 | }; | |
5303 | ||
5304 | typedef enum | |
5305 | { | |
5306 | /* Varieties of non-ALU group relocation. */ | |
5307 | ||
5308 | GROUP_LDR, | |
5309 | GROUP_LDRS, | |
5310 | GROUP_LDC | |
5311 | } group_reloc_type; | |
5312 | ||
5313 | static struct group_reloc_table_entry group_reloc_table[] = | |
5314 | { /* Program counter relative: */ | |
5315 | { "pc_g0_nc", | |
5316 | BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ | |
5317 | 0, /* LDR */ | |
5318 | 0, /* LDRS */ | |
5319 | 0 }, /* LDC */ | |
5320 | { "pc_g0", | |
5321 | BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ | |
5322 | BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ | |
5323 | BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ | |
5324 | BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ | |
5325 | { "pc_g1_nc", | |
5326 | BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ | |
5327 | 0, /* LDR */ | |
5328 | 0, /* LDRS */ | |
5329 | 0 }, /* LDC */ | |
5330 | { "pc_g1", | |
5331 | BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ | |
5332 | BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ | |
5333 | BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ | |
5334 | BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ | |
5335 | { "pc_g2", | |
5336 | BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ | |
5337 | BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ | |
5338 | BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ | |
5339 | BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ | |
5340 | /* Section base relative */ | |
5341 | { "sb_g0_nc", | |
5342 | BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ | |
5343 | 0, /* LDR */ | |
5344 | 0, /* LDRS */ | |
5345 | 0 }, /* LDC */ | |
5346 | { "sb_g0", | |
5347 | BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ | |
5348 | BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ | |
5349 | BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ | |
5350 | BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ | |
5351 | { "sb_g1_nc", | |
5352 | BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ | |
5353 | 0, /* LDR */ | |
5354 | 0, /* LDRS */ | |
5355 | 0 }, /* LDC */ | |
5356 | { "sb_g1", | |
5357 | BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ | |
5358 | BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ | |
5359 | BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ | |
5360 | BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ | |
5361 | { "sb_g2", | |
5362 | BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ | |
5363 | BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ | |
5364 | BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ | |
72d98d16 MG |
5365 | BFD_RELOC_ARM_LDC_SB_G2 }, /* LDC */ |
5366 | /* Absolute thumb alu relocations. */ | |
5367 | { "lower0_7", | |
5368 | BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC,/* ALU. */ | |
5369 | 0, /* LDR. */ | |
5370 | 0, /* LDRS. */ | |
5371 | 0 }, /* LDC. */ | |
5372 | { "lower8_15", | |
5373 | BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC,/* ALU. */ | |
5374 | 0, /* LDR. */ | |
5375 | 0, /* LDRS. */ | |
5376 | 0 }, /* LDC. */ | |
5377 | { "upper0_7", | |
5378 | BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC,/* ALU. */ | |
5379 | 0, /* LDR. */ | |
5380 | 0, /* LDRS. */ | |
5381 | 0 }, /* LDC. */ | |
5382 | { "upper8_15", | |
5383 | BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC,/* ALU. */ | |
5384 | 0, /* LDR. */ | |
5385 | 0, /* LDRS. */ | |
5386 | 0 } }; /* LDC. */ | |
4962c51a MS |
5387 | |
5388 | /* Given the address of a pointer pointing to the textual name of a group | |
5389 | relocation as may appear in assembler source, attempt to find its details | |
5390 | in group_reloc_table. The pointer will be updated to the character after | |
5391 | the trailing colon. On failure, FAIL will be returned; SUCCESS | |
5392 | otherwise. On success, *entry will be updated to point at the relevant | |
5393 | group_reloc_table entry. */ | |
5394 | ||
5395 | static int | |
5396 | find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) | |
5397 | { | |
5398 | unsigned int i; | |
5399 | for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) | |
5400 | { | |
5401 | int length = strlen (group_reloc_table[i].name); | |
5402 | ||
5f4273c7 NC |
5403 | if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 |
5404 | && (*str)[length] == ':') | |
477330fc RM |
5405 | { |
5406 | *out = &group_reloc_table[i]; | |
5407 | *str += (length + 1); | |
5408 | return SUCCESS; | |
5409 | } | |
4962c51a MS |
5410 | } |
5411 | ||
5412 | return FAIL; | |
5413 | } | |
5414 | ||
5415 | /* Parse a <shifter_operand> for an ARM data processing instruction | |
5416 | (as for parse_shifter_operand) where group relocations are allowed: | |
5417 | ||
5418 | #<immediate> | |
5419 | #<immediate>, <rotate> | |
5420 | #:<group_reloc>:<expression> | |
5421 | <Rm> | |
5422 | <Rm>, <shift> | |
5423 | ||
5424 | where <group_reloc> is one of the strings defined in group_reloc_table. | |
5425 | The hashes are optional. | |
5426 | ||
5427 | Everything else is as for parse_shifter_operand. */ | |
5428 | ||
5429 | static parse_operand_result | |
5430 | parse_shifter_operand_group_reloc (char **str, int i) | |
5431 | { | |
5432 | /* Determine if we have the sequence of characters #: or just : | |
5433 | coming next. If we do, then we check for a group relocation. | |
5434 | If we don't, punt the whole lot to parse_shifter_operand. */ | |
5435 | ||
5436 | if (((*str)[0] == '#' && (*str)[1] == ':') | |
5437 | || (*str)[0] == ':') | |
5438 | { | |
5439 | struct group_reloc_table_entry *entry; | |
5440 | ||
5441 | if ((*str)[0] == '#') | |
477330fc | 5442 | (*str) += 2; |
4962c51a | 5443 | else |
477330fc | 5444 | (*str)++; |
4962c51a MS |
5445 | |
5446 | /* Try to parse a group relocation. Anything else is an error. */ | |
5447 | if (find_group_reloc_table_entry (str, &entry) == FAIL) | |
477330fc RM |
5448 | { |
5449 | inst.error = _("unknown group relocation"); | |
5450 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5451 | } | |
4962c51a MS |
5452 | |
5453 | /* We now have the group relocation table entry corresponding to | |
477330fc | 5454 | the name in the assembler source. Next, we parse the expression. */ |
4962c51a | 5455 | if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) |
477330fc | 5456 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; |
4962c51a MS |
5457 | |
5458 | /* Record the relocation type (always the ALU variant here). */ | |
21d799b5 | 5459 | inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code; |
9c2799c2 | 5460 | gas_assert (inst.reloc.type != 0); |
4962c51a MS |
5461 | |
5462 | return PARSE_OPERAND_SUCCESS; | |
5463 | } | |
5464 | else | |
5465 | return parse_shifter_operand (str, i) == SUCCESS | |
477330fc | 5466 | ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; |
4962c51a MS |
5467 | |
5468 | /* Never reached. */ | |
5469 | } | |
5470 | ||
8e560766 MGD |
5471 | /* Parse a Neon alignment expression. Information is written to |
5472 | inst.operands[i]. We assume the initial ':' has been skipped. | |
fa94de6b | 5473 | |
8e560766 MGD |
5474 | align .imm = align << 8, .immisalign=1, .preind=0 */ |
5475 | static parse_operand_result | |
5476 | parse_neon_alignment (char **str, int i) | |
5477 | { | |
5478 | char *p = *str; | |
5479 | expressionS exp; | |
5480 | ||
5481 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
5482 | ||
5483 | if (exp.X_op != O_constant) | |
5484 | { | |
5485 | inst.error = _("alignment must be constant"); | |
5486 | return PARSE_OPERAND_FAIL; | |
5487 | } | |
5488 | ||
5489 | inst.operands[i].imm = exp.X_add_number << 8; | |
5490 | inst.operands[i].immisalign = 1; | |
5491 | /* Alignments are not pre-indexes. */ | |
5492 | inst.operands[i].preind = 0; | |
5493 | ||
5494 | *str = p; | |
5495 | return PARSE_OPERAND_SUCCESS; | |
5496 | } | |
5497 | ||
c19d1205 ZW |
5498 | /* Parse all forms of an ARM address expression. Information is written |
5499 | to inst.operands[i] and/or inst.reloc. | |
09d92015 | 5500 | |
c19d1205 | 5501 | Preindexed addressing (.preind=1): |
09d92015 | 5502 | |
c19d1205 ZW |
5503 | [Rn, #offset] .reg=Rn .reloc.exp=offset |
5504 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5505 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5506 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5507 | |
c19d1205 | 5508 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 5509 | |
c19d1205 | 5510 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 5511 | |
c19d1205 ZW |
5512 | [Rn], #offset .reg=Rn .reloc.exp=offset |
5513 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5514 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5515 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5516 | |
c19d1205 | 5517 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 5518 | |
c19d1205 | 5519 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 5520 | |
c19d1205 | 5521 | Other: |
09d92015 | 5522 | |
c19d1205 ZW |
5523 | [Rn]{!} shorthand for [Rn,#0]{!} |
5524 | =immediate .isreg=0 .reloc.exp=immediate | |
5525 | label .reg=PC .reloc.pc_rel=1 .reloc.exp=label | |
09d92015 | 5526 | |
c19d1205 ZW |
5527 | It is the caller's responsibility to check for addressing modes not |
5528 | supported by the instruction, and to set inst.reloc.type. */ | |
5529 | ||
4962c51a MS |
5530 | static parse_operand_result |
5531 | parse_address_main (char **str, int i, int group_relocations, | |
477330fc | 5532 | group_reloc_type group_type) |
09d92015 | 5533 | { |
c19d1205 ZW |
5534 | char *p = *str; |
5535 | int reg; | |
09d92015 | 5536 | |
c19d1205 | 5537 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 5538 | { |
c19d1205 ZW |
5539 | if (skip_past_char (&p, '=') == FAIL) |
5540 | { | |
974da60d | 5541 | /* Bare address - translate to PC-relative offset. */ |
c19d1205 ZW |
5542 | inst.reloc.pc_rel = 1; |
5543 | inst.operands[i].reg = REG_PC; | |
5544 | inst.operands[i].isreg = 1; | |
5545 | inst.operands[i].preind = 1; | |
09d92015 | 5546 | |
8335d6aa JW |
5547 | if (my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX_BIG)) |
5548 | return PARSE_OPERAND_FAIL; | |
5549 | } | |
5550 | else if (parse_big_immediate (&p, i, &inst.reloc.exp, | |
5551 | /*allow_symbol_p=*/TRUE)) | |
4962c51a | 5552 | return PARSE_OPERAND_FAIL; |
09d92015 | 5553 | |
c19d1205 | 5554 | *str = p; |
4962c51a | 5555 | return PARSE_OPERAND_SUCCESS; |
09d92015 MM |
5556 | } |
5557 | ||
8ab8155f NC |
5558 | /* PR gas/14887: Allow for whitespace after the opening bracket. */ |
5559 | skip_whitespace (p); | |
5560 | ||
dcbf9037 | 5561 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
09d92015 | 5562 | { |
c19d1205 | 5563 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
4962c51a | 5564 | return PARSE_OPERAND_FAIL; |
09d92015 | 5565 | } |
c19d1205 ZW |
5566 | inst.operands[i].reg = reg; |
5567 | inst.operands[i].isreg = 1; | |
09d92015 | 5568 | |
c19d1205 | 5569 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5570 | { |
c19d1205 | 5571 | inst.operands[i].preind = 1; |
09d92015 | 5572 | |
c19d1205 ZW |
5573 | if (*p == '+') p++; |
5574 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
5575 | ||
dcbf9037 | 5576 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
09d92015 | 5577 | { |
c19d1205 ZW |
5578 | inst.operands[i].imm = reg; |
5579 | inst.operands[i].immisreg = 1; | |
5580 | ||
5581 | if (skip_past_comma (&p) == SUCCESS) | |
5582 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5583 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5584 | } |
5287ad62 | 5585 | else if (skip_past_char (&p, ':') == SUCCESS) |
8e560766 MGD |
5586 | { |
5587 | /* FIXME: '@' should be used here, but it's filtered out by generic | |
5588 | code before we get to see it here. This may be subject to | |
5589 | change. */ | |
5590 | parse_operand_result result = parse_neon_alignment (&p, i); | |
fa94de6b | 5591 | |
8e560766 MGD |
5592 | if (result != PARSE_OPERAND_SUCCESS) |
5593 | return result; | |
5594 | } | |
c19d1205 ZW |
5595 | else |
5596 | { | |
5597 | if (inst.operands[i].negative) | |
5598 | { | |
5599 | inst.operands[i].negative = 0; | |
5600 | p--; | |
5601 | } | |
4962c51a | 5602 | |
5f4273c7 NC |
5603 | if (group_relocations |
5604 | && ((*p == '#' && *(p + 1) == ':') || *p == ':')) | |
4962c51a MS |
5605 | { |
5606 | struct group_reloc_table_entry *entry; | |
5607 | ||
477330fc RM |
5608 | /* Skip over the #: or : sequence. */ |
5609 | if (*p == '#') | |
5610 | p += 2; | |
5611 | else | |
5612 | p++; | |
4962c51a MS |
5613 | |
5614 | /* Try to parse a group relocation. Anything else is an | |
477330fc | 5615 | error. */ |
4962c51a MS |
5616 | if (find_group_reloc_table_entry (&p, &entry) == FAIL) |
5617 | { | |
5618 | inst.error = _("unknown group relocation"); | |
5619 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5620 | } | |
5621 | ||
5622 | /* We now have the group relocation table entry corresponding to | |
5623 | the name in the assembler source. Next, we parse the | |
477330fc | 5624 | expression. */ |
4962c51a MS |
5625 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) |
5626 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5627 | ||
5628 | /* Record the relocation type. */ | |
477330fc RM |
5629 | switch (group_type) |
5630 | { | |
5631 | case GROUP_LDR: | |
5632 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code; | |
5633 | break; | |
4962c51a | 5634 | |
477330fc RM |
5635 | case GROUP_LDRS: |
5636 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code; | |
5637 | break; | |
4962c51a | 5638 | |
477330fc RM |
5639 | case GROUP_LDC: |
5640 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code; | |
5641 | break; | |
4962c51a | 5642 | |
477330fc RM |
5643 | default: |
5644 | gas_assert (0); | |
5645 | } | |
4962c51a | 5646 | |
477330fc | 5647 | if (inst.reloc.type == 0) |
4962c51a MS |
5648 | { |
5649 | inst.error = _("this group relocation is not allowed on this instruction"); | |
5650 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5651 | } | |
477330fc RM |
5652 | } |
5653 | else | |
26d97720 NS |
5654 | { |
5655 | char *q = p; | |
0198d5e6 | 5656 | |
26d97720 NS |
5657 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) |
5658 | return PARSE_OPERAND_FAIL; | |
5659 | /* If the offset is 0, find out if it's a +0 or -0. */ | |
5660 | if (inst.reloc.exp.X_op == O_constant | |
5661 | && inst.reloc.exp.X_add_number == 0) | |
5662 | { | |
5663 | skip_whitespace (q); | |
5664 | if (*q == '#') | |
5665 | { | |
5666 | q++; | |
5667 | skip_whitespace (q); | |
5668 | } | |
5669 | if (*q == '-') | |
5670 | inst.operands[i].negative = 1; | |
5671 | } | |
5672 | } | |
09d92015 MM |
5673 | } |
5674 | } | |
8e560766 MGD |
5675 | else if (skip_past_char (&p, ':') == SUCCESS) |
5676 | { | |
5677 | /* FIXME: '@' should be used here, but it's filtered out by generic code | |
5678 | before we get to see it here. This may be subject to change. */ | |
5679 | parse_operand_result result = parse_neon_alignment (&p, i); | |
fa94de6b | 5680 | |
8e560766 MGD |
5681 | if (result != PARSE_OPERAND_SUCCESS) |
5682 | return result; | |
5683 | } | |
09d92015 | 5684 | |
c19d1205 | 5685 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 5686 | { |
c19d1205 | 5687 | inst.error = _("']' expected"); |
4962c51a | 5688 | return PARSE_OPERAND_FAIL; |
09d92015 MM |
5689 | } |
5690 | ||
c19d1205 ZW |
5691 | if (skip_past_char (&p, '!') == SUCCESS) |
5692 | inst.operands[i].writeback = 1; | |
09d92015 | 5693 | |
c19d1205 | 5694 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5695 | { |
c19d1205 ZW |
5696 | if (skip_past_char (&p, '{') == SUCCESS) |
5697 | { | |
5698 | /* [Rn], {expr} - unindexed, with option */ | |
5699 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 5700 | 0, 255, TRUE) == FAIL) |
4962c51a | 5701 | return PARSE_OPERAND_FAIL; |
09d92015 | 5702 | |
c19d1205 ZW |
5703 | if (skip_past_char (&p, '}') == FAIL) |
5704 | { | |
5705 | inst.error = _("'}' expected at end of 'option' field"); | |
4962c51a | 5706 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5707 | } |
5708 | if (inst.operands[i].preind) | |
5709 | { | |
5710 | inst.error = _("cannot combine index with option"); | |
4962c51a | 5711 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5712 | } |
5713 | *str = p; | |
4962c51a | 5714 | return PARSE_OPERAND_SUCCESS; |
09d92015 | 5715 | } |
c19d1205 ZW |
5716 | else |
5717 | { | |
5718 | inst.operands[i].postind = 1; | |
5719 | inst.operands[i].writeback = 1; | |
09d92015 | 5720 | |
c19d1205 ZW |
5721 | if (inst.operands[i].preind) |
5722 | { | |
5723 | inst.error = _("cannot combine pre- and post-indexing"); | |
4962c51a | 5724 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5725 | } |
09d92015 | 5726 | |
c19d1205 ZW |
5727 | if (*p == '+') p++; |
5728 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 5729 | |
dcbf9037 | 5730 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 | 5731 | { |
477330fc RM |
5732 | /* We might be using the immediate for alignment already. If we |
5733 | are, OR the register number into the low-order bits. */ | |
5734 | if (inst.operands[i].immisalign) | |
5735 | inst.operands[i].imm |= reg; | |
5736 | else | |
5737 | inst.operands[i].imm = reg; | |
c19d1205 | 5738 | inst.operands[i].immisreg = 1; |
a737bd4d | 5739 | |
c19d1205 ZW |
5740 | if (skip_past_comma (&p) == SUCCESS) |
5741 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5742 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5743 | } |
5744 | else | |
5745 | { | |
26d97720 | 5746 | char *q = p; |
0198d5e6 | 5747 | |
c19d1205 ZW |
5748 | if (inst.operands[i].negative) |
5749 | { | |
5750 | inst.operands[i].negative = 0; | |
5751 | p--; | |
5752 | } | |
5753 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4962c51a | 5754 | return PARSE_OPERAND_FAIL; |
26d97720 NS |
5755 | /* If the offset is 0, find out if it's a +0 or -0. */ |
5756 | if (inst.reloc.exp.X_op == O_constant | |
5757 | && inst.reloc.exp.X_add_number == 0) | |
5758 | { | |
5759 | skip_whitespace (q); | |
5760 | if (*q == '#') | |
5761 | { | |
5762 | q++; | |
5763 | skip_whitespace (q); | |
5764 | } | |
5765 | if (*q == '-') | |
5766 | inst.operands[i].negative = 1; | |
5767 | } | |
c19d1205 ZW |
5768 | } |
5769 | } | |
a737bd4d NC |
5770 | } |
5771 | ||
c19d1205 ZW |
5772 | /* If at this point neither .preind nor .postind is set, we have a |
5773 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
5774 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
5775 | { | |
5776 | inst.operands[i].preind = 1; | |
5777 | inst.reloc.exp.X_op = O_constant; | |
5778 | inst.reloc.exp.X_add_number = 0; | |
5779 | } | |
5780 | *str = p; | |
4962c51a MS |
5781 | return PARSE_OPERAND_SUCCESS; |
5782 | } | |
5783 | ||
5784 | static int | |
5785 | parse_address (char **str, int i) | |
5786 | { | |
21d799b5 | 5787 | return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS |
477330fc | 5788 | ? SUCCESS : FAIL; |
4962c51a MS |
5789 | } |
5790 | ||
5791 | static parse_operand_result | |
5792 | parse_address_group_reloc (char **str, int i, group_reloc_type type) | |
5793 | { | |
5794 | return parse_address_main (str, i, 1, type); | |
a737bd4d NC |
5795 | } |
5796 | ||
b6895b4f PB |
5797 | /* Parse an operand for a MOVW or MOVT instruction. */ |
5798 | static int | |
5799 | parse_half (char **str) | |
5800 | { | |
5801 | char * p; | |
5f4273c7 | 5802 | |
b6895b4f PB |
5803 | p = *str; |
5804 | skip_past_char (&p, '#'); | |
5f4273c7 | 5805 | if (strncasecmp (p, ":lower16:", 9) == 0) |
b6895b4f PB |
5806 | inst.reloc.type = BFD_RELOC_ARM_MOVW; |
5807 | else if (strncasecmp (p, ":upper16:", 9) == 0) | |
5808 | inst.reloc.type = BFD_RELOC_ARM_MOVT; | |
5809 | ||
5810 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
5811 | { | |
5812 | p += 9; | |
5f4273c7 | 5813 | skip_whitespace (p); |
b6895b4f PB |
5814 | } |
5815 | ||
5816 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5817 | return FAIL; | |
5818 | ||
5819 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
5820 | { | |
5821 | if (inst.reloc.exp.X_op != O_constant) | |
5822 | { | |
5823 | inst.error = _("constant expression expected"); | |
5824 | return FAIL; | |
5825 | } | |
5826 | if (inst.reloc.exp.X_add_number < 0 | |
5827 | || inst.reloc.exp.X_add_number > 0xffff) | |
5828 | { | |
5829 | inst.error = _("immediate value out of range"); | |
5830 | return FAIL; | |
5831 | } | |
5832 | } | |
5833 | *str = p; | |
5834 | return SUCCESS; | |
5835 | } | |
5836 | ||
c19d1205 | 5837 | /* Miscellaneous. */ |
a737bd4d | 5838 | |
c19d1205 ZW |
5839 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
5840 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
5841 | static int | |
d2cd1205 | 5842 | parse_psr (char **str, bfd_boolean lhs) |
09d92015 | 5843 | { |
c19d1205 ZW |
5844 | char *p; |
5845 | unsigned long psr_field; | |
62b3e311 PB |
5846 | const struct asm_psr *psr; |
5847 | char *start; | |
d2cd1205 | 5848 | bfd_boolean is_apsr = FALSE; |
ac7f631b | 5849 | bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m); |
09d92015 | 5850 | |
a4482bb6 NC |
5851 | /* PR gas/12698: If the user has specified -march=all then m_profile will |
5852 | be TRUE, but we want to ignore it in this case as we are building for any | |
5853 | CPU type, including non-m variants. */ | |
823d2571 | 5854 | if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any)) |
a4482bb6 NC |
5855 | m_profile = FALSE; |
5856 | ||
c19d1205 ZW |
5857 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
5858 | feature for ease of use and backwards compatibility. */ | |
5859 | p = *str; | |
62b3e311 | 5860 | if (strncasecmp (p, "SPSR", 4) == 0) |
d2cd1205 JB |
5861 | { |
5862 | if (m_profile) | |
5863 | goto unsupported_psr; | |
fa94de6b | 5864 | |
d2cd1205 JB |
5865 | psr_field = SPSR_BIT; |
5866 | } | |
5867 | else if (strncasecmp (p, "CPSR", 4) == 0) | |
5868 | { | |
5869 | if (m_profile) | |
5870 | goto unsupported_psr; | |
5871 | ||
5872 | psr_field = 0; | |
5873 | } | |
5874 | else if (strncasecmp (p, "APSR", 4) == 0) | |
5875 | { | |
5876 | /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A | |
5877 | and ARMv7-R architecture CPUs. */ | |
5878 | is_apsr = TRUE; | |
5879 | psr_field = 0; | |
5880 | } | |
5881 | else if (m_profile) | |
62b3e311 PB |
5882 | { |
5883 | start = p; | |
5884 | do | |
5885 | p++; | |
5886 | while (ISALNUM (*p) || *p == '_'); | |
5887 | ||
d2cd1205 JB |
5888 | if (strncasecmp (start, "iapsr", 5) == 0 |
5889 | || strncasecmp (start, "eapsr", 5) == 0 | |
5890 | || strncasecmp (start, "xpsr", 4) == 0 | |
5891 | || strncasecmp (start, "psr", 3) == 0) | |
5892 | p = start + strcspn (start, "rR") + 1; | |
5893 | ||
21d799b5 | 5894 | psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start, |
477330fc | 5895 | p - start); |
d2cd1205 | 5896 | |
62b3e311 PB |
5897 | if (!psr) |
5898 | return FAIL; | |
09d92015 | 5899 | |
d2cd1205 JB |
5900 | /* If APSR is being written, a bitfield may be specified. Note that |
5901 | APSR itself is handled above. */ | |
5902 | if (psr->field <= 3) | |
5903 | { | |
5904 | psr_field = psr->field; | |
5905 | is_apsr = TRUE; | |
5906 | goto check_suffix; | |
5907 | } | |
5908 | ||
62b3e311 | 5909 | *str = p; |
d2cd1205 JB |
5910 | /* M-profile MSR instructions have the mask field set to "10", except |
5911 | *PSR variants which modify APSR, which may use a different mask (and | |
5912 | have been handled already). Do that by setting the PSR_f field | |
5913 | here. */ | |
5914 | return psr->field | (lhs ? PSR_f : 0); | |
62b3e311 | 5915 | } |
d2cd1205 JB |
5916 | else |
5917 | goto unsupported_psr; | |
09d92015 | 5918 | |
62b3e311 | 5919 | p += 4; |
d2cd1205 | 5920 | check_suffix: |
c19d1205 ZW |
5921 | if (*p == '_') |
5922 | { | |
5923 | /* A suffix follows. */ | |
c19d1205 ZW |
5924 | p++; |
5925 | start = p; | |
a737bd4d | 5926 | |
c19d1205 ZW |
5927 | do |
5928 | p++; | |
5929 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 5930 | |
d2cd1205 JB |
5931 | if (is_apsr) |
5932 | { | |
5933 | /* APSR uses a notation for bits, rather than fields. */ | |
5934 | unsigned int nzcvq_bits = 0; | |
5935 | unsigned int g_bit = 0; | |
5936 | char *bit; | |
fa94de6b | 5937 | |
d2cd1205 JB |
5938 | for (bit = start; bit != p; bit++) |
5939 | { | |
5940 | switch (TOLOWER (*bit)) | |
477330fc | 5941 | { |
d2cd1205 JB |
5942 | case 'n': |
5943 | nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01; | |
5944 | break; | |
5945 | ||
5946 | case 'z': | |
5947 | nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02; | |
5948 | break; | |
5949 | ||
5950 | case 'c': | |
5951 | nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04; | |
5952 | break; | |
5953 | ||
5954 | case 'v': | |
5955 | nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08; | |
5956 | break; | |
fa94de6b | 5957 | |
d2cd1205 JB |
5958 | case 'q': |
5959 | nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10; | |
5960 | break; | |
fa94de6b | 5961 | |
d2cd1205 JB |
5962 | case 'g': |
5963 | g_bit |= (g_bit & 0x1) ? 0x2 : 0x1; | |
5964 | break; | |
fa94de6b | 5965 | |
d2cd1205 JB |
5966 | default: |
5967 | inst.error = _("unexpected bit specified after APSR"); | |
5968 | return FAIL; | |
5969 | } | |
5970 | } | |
fa94de6b | 5971 | |
d2cd1205 JB |
5972 | if (nzcvq_bits == 0x1f) |
5973 | psr_field |= PSR_f; | |
fa94de6b | 5974 | |
d2cd1205 JB |
5975 | if (g_bit == 0x1) |
5976 | { | |
5977 | if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)) | |
477330fc | 5978 | { |
d2cd1205 JB |
5979 | inst.error = _("selected processor does not " |
5980 | "support DSP extension"); | |
5981 | return FAIL; | |
5982 | } | |
5983 | ||
5984 | psr_field |= PSR_s; | |
5985 | } | |
fa94de6b | 5986 | |
d2cd1205 JB |
5987 | if ((nzcvq_bits & 0x20) != 0 |
5988 | || (nzcvq_bits != 0x1f && nzcvq_bits != 0) | |
5989 | || (g_bit & 0x2) != 0) | |
5990 | { | |
5991 | inst.error = _("bad bitmask specified after APSR"); | |
5992 | return FAIL; | |
5993 | } | |
5994 | } | |
5995 | else | |
477330fc | 5996 | { |
d2cd1205 | 5997 | psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start, |
477330fc | 5998 | p - start); |
d2cd1205 | 5999 | if (!psr) |
477330fc | 6000 | goto error; |
a737bd4d | 6001 | |
d2cd1205 JB |
6002 | psr_field |= psr->field; |
6003 | } | |
a737bd4d | 6004 | } |
c19d1205 | 6005 | else |
a737bd4d | 6006 | { |
c19d1205 ZW |
6007 | if (ISALNUM (*p)) |
6008 | goto error; /* Garbage after "[CS]PSR". */ | |
6009 | ||
d2cd1205 | 6010 | /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This |
477330fc | 6011 | is deprecated, but allow it anyway. */ |
d2cd1205 JB |
6012 | if (is_apsr && lhs) |
6013 | { | |
6014 | psr_field |= PSR_f; | |
6015 | as_tsktsk (_("writing to APSR without specifying a bitmask is " | |
6016 | "deprecated")); | |
6017 | } | |
6018 | else if (!m_profile) | |
6019 | /* These bits are never right for M-profile devices: don't set them | |
6020 | (only code paths which read/write APSR reach here). */ | |
6021 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 6022 | } |
c19d1205 ZW |
6023 | *str = p; |
6024 | return psr_field; | |
a737bd4d | 6025 | |
d2cd1205 JB |
6026 | unsupported_psr: |
6027 | inst.error = _("selected processor does not support requested special " | |
6028 | "purpose register"); | |
6029 | return FAIL; | |
6030 | ||
c19d1205 ZW |
6031 | error: |
6032 | inst.error = _("flag for {c}psr instruction expected"); | |
6033 | return FAIL; | |
a737bd4d NC |
6034 | } |
6035 | ||
c19d1205 ZW |
6036 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
6037 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 6038 | |
c19d1205 ZW |
6039 | static int |
6040 | parse_cps_flags (char **str) | |
a737bd4d | 6041 | { |
c19d1205 ZW |
6042 | int val = 0; |
6043 | int saw_a_flag = 0; | |
6044 | char *s = *str; | |
a737bd4d | 6045 | |
c19d1205 ZW |
6046 | for (;;) |
6047 | switch (*s++) | |
6048 | { | |
6049 | case '\0': case ',': | |
6050 | goto done; | |
a737bd4d | 6051 | |
c19d1205 ZW |
6052 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
6053 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
6054 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 6055 | |
c19d1205 ZW |
6056 | default: |
6057 | inst.error = _("unrecognized CPS flag"); | |
6058 | return FAIL; | |
6059 | } | |
a737bd4d | 6060 | |
c19d1205 ZW |
6061 | done: |
6062 | if (saw_a_flag == 0) | |
a737bd4d | 6063 | { |
c19d1205 ZW |
6064 | inst.error = _("missing CPS flags"); |
6065 | return FAIL; | |
a737bd4d | 6066 | } |
a737bd4d | 6067 | |
c19d1205 ZW |
6068 | *str = s - 1; |
6069 | return val; | |
a737bd4d NC |
6070 | } |
6071 | ||
c19d1205 ZW |
6072 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
6073 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
6074 | |
6075 | static int | |
c19d1205 | 6076 | parse_endian_specifier (char **str) |
a737bd4d | 6077 | { |
c19d1205 ZW |
6078 | int little_endian; |
6079 | char *s = *str; | |
a737bd4d | 6080 | |
c19d1205 ZW |
6081 | if (strncasecmp (s, "BE", 2)) |
6082 | little_endian = 0; | |
6083 | else if (strncasecmp (s, "LE", 2)) | |
6084 | little_endian = 1; | |
6085 | else | |
a737bd4d | 6086 | { |
c19d1205 | 6087 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
6088 | return FAIL; |
6089 | } | |
6090 | ||
c19d1205 | 6091 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 6092 | { |
c19d1205 | 6093 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
6094 | return FAIL; |
6095 | } | |
6096 | ||
c19d1205 ZW |
6097 | *str = s + 2; |
6098 | return little_endian; | |
6099 | } | |
a737bd4d | 6100 | |
c19d1205 ZW |
6101 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
6102 | value suitable for poking into the rotate field of an sxt or sxta | |
6103 | instruction, or FAIL on error. */ | |
6104 | ||
6105 | static int | |
6106 | parse_ror (char **str) | |
6107 | { | |
6108 | int rot; | |
6109 | char *s = *str; | |
6110 | ||
6111 | if (strncasecmp (s, "ROR", 3) == 0) | |
6112 | s += 3; | |
6113 | else | |
a737bd4d | 6114 | { |
c19d1205 | 6115 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
6116 | return FAIL; |
6117 | } | |
c19d1205 ZW |
6118 | |
6119 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
6120 | return FAIL; | |
6121 | ||
6122 | switch (rot) | |
a737bd4d | 6123 | { |
c19d1205 ZW |
6124 | case 0: *str = s; return 0x0; |
6125 | case 8: *str = s; return 0x1; | |
6126 | case 16: *str = s; return 0x2; | |
6127 | case 24: *str = s; return 0x3; | |
6128 | ||
6129 | default: | |
6130 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
6131 | return FAIL; |
6132 | } | |
c19d1205 | 6133 | } |
a737bd4d | 6134 | |
c19d1205 ZW |
6135 | /* Parse a conditional code (from conds[] below). The value returned is in the |
6136 | range 0 .. 14, or FAIL. */ | |
6137 | static int | |
6138 | parse_cond (char **str) | |
6139 | { | |
c462b453 | 6140 | char *q; |
c19d1205 | 6141 | const struct asm_cond *c; |
c462b453 PB |
6142 | int n; |
6143 | /* Condition codes are always 2 characters, so matching up to | |
6144 | 3 characters is sufficient. */ | |
6145 | char cond[3]; | |
a737bd4d | 6146 | |
c462b453 PB |
6147 | q = *str; |
6148 | n = 0; | |
6149 | while (ISALPHA (*q) && n < 3) | |
6150 | { | |
e07e6e58 | 6151 | cond[n] = TOLOWER (*q); |
c462b453 PB |
6152 | q++; |
6153 | n++; | |
6154 | } | |
a737bd4d | 6155 | |
21d799b5 | 6156 | c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n); |
c19d1205 | 6157 | if (!c) |
a737bd4d | 6158 | { |
c19d1205 | 6159 | inst.error = _("condition required"); |
a737bd4d NC |
6160 | return FAIL; |
6161 | } | |
6162 | ||
c19d1205 ZW |
6163 | *str = q; |
6164 | return c->value; | |
6165 | } | |
6166 | ||
643afb90 MW |
6167 | /* Record a use of the given feature. */ |
6168 | static void | |
6169 | record_feature_use (const arm_feature_set *feature) | |
6170 | { | |
6171 | if (thumb_mode) | |
6172 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature); | |
6173 | else | |
6174 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature); | |
6175 | } | |
6176 | ||
4d354d8b TP |
6177 | /* If the given feature is currently allowed, mark it as used and return TRUE. |
6178 | Return FALSE otherwise. */ | |
e797f7e0 MGD |
6179 | static bfd_boolean |
6180 | mark_feature_used (const arm_feature_set *feature) | |
6181 | { | |
4d354d8b | 6182 | /* Ensure the option is currently allowed. */ |
e797f7e0 MGD |
6183 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature)) |
6184 | return FALSE; | |
6185 | ||
4d354d8b | 6186 | /* Add the appropriate architecture feature for the barrier option used. */ |
643afb90 | 6187 | record_feature_use (feature); |
e797f7e0 MGD |
6188 | |
6189 | return TRUE; | |
6190 | } | |
6191 | ||
62b3e311 PB |
6192 | /* Parse an option for a barrier instruction. Returns the encoding for the |
6193 | option, or FAIL. */ | |
6194 | static int | |
6195 | parse_barrier (char **str) | |
6196 | { | |
6197 | char *p, *q; | |
6198 | const struct asm_barrier_opt *o; | |
6199 | ||
6200 | p = q = *str; | |
6201 | while (ISALPHA (*q)) | |
6202 | q++; | |
6203 | ||
21d799b5 | 6204 | o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p, |
477330fc | 6205 | q - p); |
62b3e311 PB |
6206 | if (!o) |
6207 | return FAIL; | |
6208 | ||
e797f7e0 MGD |
6209 | if (!mark_feature_used (&o->arch)) |
6210 | return FAIL; | |
6211 | ||
62b3e311 PB |
6212 | *str = q; |
6213 | return o->value; | |
6214 | } | |
6215 | ||
92e90b6e PB |
6216 | /* Parse the operands of a table branch instruction. Similar to a memory |
6217 | operand. */ | |
6218 | static int | |
6219 | parse_tb (char **str) | |
6220 | { | |
6221 | char * p = *str; | |
6222 | int reg; | |
6223 | ||
6224 | if (skip_past_char (&p, '[') == FAIL) | |
ab1eb5fe PB |
6225 | { |
6226 | inst.error = _("'[' expected"); | |
6227 | return FAIL; | |
6228 | } | |
92e90b6e | 6229 | |
dcbf9037 | 6230 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
6231 | { |
6232 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
6233 | return FAIL; | |
6234 | } | |
6235 | inst.operands[0].reg = reg; | |
6236 | ||
6237 | if (skip_past_comma (&p) == FAIL) | |
ab1eb5fe PB |
6238 | { |
6239 | inst.error = _("',' expected"); | |
6240 | return FAIL; | |
6241 | } | |
5f4273c7 | 6242 | |
dcbf9037 | 6243 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
6244 | { |
6245 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
6246 | return FAIL; | |
6247 | } | |
6248 | inst.operands[0].imm = reg; | |
6249 | ||
6250 | if (skip_past_comma (&p) == SUCCESS) | |
6251 | { | |
6252 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
6253 | return FAIL; | |
6254 | if (inst.reloc.exp.X_add_number != 1) | |
6255 | { | |
6256 | inst.error = _("invalid shift"); | |
6257 | return FAIL; | |
6258 | } | |
6259 | inst.operands[0].shifted = 1; | |
6260 | } | |
6261 | ||
6262 | if (skip_past_char (&p, ']') == FAIL) | |
6263 | { | |
6264 | inst.error = _("']' expected"); | |
6265 | return FAIL; | |
6266 | } | |
6267 | *str = p; | |
6268 | return SUCCESS; | |
6269 | } | |
6270 | ||
5287ad62 JB |
6271 | /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more |
6272 | information on the types the operands can take and how they are encoded. | |
037e8744 JB |
6273 | Up to four operands may be read; this function handles setting the |
6274 | ".present" field for each read operand itself. | |
5287ad62 JB |
6275 | Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, |
6276 | else returns FAIL. */ | |
6277 | ||
6278 | static int | |
6279 | parse_neon_mov (char **str, int *which_operand) | |
6280 | { | |
6281 | int i = *which_operand, val; | |
6282 | enum arm_reg_type rtype; | |
6283 | char *ptr = *str; | |
dcbf9037 | 6284 | struct neon_type_el optype; |
5f4273c7 | 6285 | |
dcbf9037 | 6286 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
6287 | { |
6288 | /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ | |
6289 | inst.operands[i].reg = val; | |
6290 | inst.operands[i].isscalar = 1; | |
dcbf9037 | 6291 | inst.operands[i].vectype = optype; |
5287ad62 JB |
6292 | inst.operands[i++].present = 1; |
6293 | ||
6294 | if (skip_past_comma (&ptr) == FAIL) | |
477330fc | 6295 | goto wanted_comma; |
5f4273c7 | 6296 | |
dcbf9037 | 6297 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
477330fc | 6298 | goto wanted_arm; |
5f4273c7 | 6299 | |
5287ad62 JB |
6300 | inst.operands[i].reg = val; |
6301 | inst.operands[i].isreg = 1; | |
6302 | inst.operands[i].present = 1; | |
6303 | } | |
037e8744 | 6304 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) |
477330fc | 6305 | != FAIL) |
5287ad62 JB |
6306 | { |
6307 | /* Cases 0, 1, 2, 3, 5 (D only). */ | |
6308 | if (skip_past_comma (&ptr) == FAIL) | |
477330fc | 6309 | goto wanted_comma; |
5f4273c7 | 6310 | |
5287ad62 JB |
6311 | inst.operands[i].reg = val; |
6312 | inst.operands[i].isreg = 1; | |
6313 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
6314 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
6315 | inst.operands[i].isvec = 1; | |
dcbf9037 | 6316 | inst.operands[i].vectype = optype; |
5287ad62 JB |
6317 | inst.operands[i++].present = 1; |
6318 | ||
dcbf9037 | 6319 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
477330fc RM |
6320 | { |
6321 | /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. | |
6322 | Case 13: VMOV <Sd>, <Rm> */ | |
6323 | inst.operands[i].reg = val; | |
6324 | inst.operands[i].isreg = 1; | |
6325 | inst.operands[i].present = 1; | |
6326 | ||
6327 | if (rtype == REG_TYPE_NQ) | |
6328 | { | |
6329 | first_error (_("can't use Neon quad register here")); | |
6330 | return FAIL; | |
6331 | } | |
6332 | else if (rtype != REG_TYPE_VFS) | |
6333 | { | |
6334 | i++; | |
6335 | if (skip_past_comma (&ptr) == FAIL) | |
6336 | goto wanted_comma; | |
6337 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6338 | goto wanted_arm; | |
6339 | inst.operands[i].reg = val; | |
6340 | inst.operands[i].isreg = 1; | |
6341 | inst.operands[i].present = 1; | |
6342 | } | |
6343 | } | |
037e8744 | 6344 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, |
477330fc RM |
6345 | &optype)) != FAIL) |
6346 | { | |
6347 | /* Case 0: VMOV<c><q> <Qd>, <Qm> | |
6348 | Case 1: VMOV<c><q> <Dd>, <Dm> | |
6349 | Case 8: VMOV.F32 <Sd>, <Sm> | |
6350 | Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ | |
6351 | ||
6352 | inst.operands[i].reg = val; | |
6353 | inst.operands[i].isreg = 1; | |
6354 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
6355 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
6356 | inst.operands[i].isvec = 1; | |
6357 | inst.operands[i].vectype = optype; | |
6358 | inst.operands[i].present = 1; | |
6359 | ||
6360 | if (skip_past_comma (&ptr) == SUCCESS) | |
6361 | { | |
6362 | /* Case 15. */ | |
6363 | i++; | |
6364 | ||
6365 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6366 | goto wanted_arm; | |
6367 | ||
6368 | inst.operands[i].reg = val; | |
6369 | inst.operands[i].isreg = 1; | |
6370 | inst.operands[i++].present = 1; | |
6371 | ||
6372 | if (skip_past_comma (&ptr) == FAIL) | |
6373 | goto wanted_comma; | |
6374 | ||
6375 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6376 | goto wanted_arm; | |
6377 | ||
6378 | inst.operands[i].reg = val; | |
6379 | inst.operands[i].isreg = 1; | |
6380 | inst.operands[i].present = 1; | |
6381 | } | |
6382 | } | |
4641781c | 6383 | else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) |
477330fc RM |
6384 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> |
6385 | Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> | |
6386 | Case 10: VMOV.F32 <Sd>, #<imm> | |
6387 | Case 11: VMOV.F64 <Dd>, #<imm> */ | |
6388 | inst.operands[i].immisfloat = 1; | |
8335d6aa JW |
6389 | else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE) |
6390 | == SUCCESS) | |
477330fc RM |
6391 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> |
6392 | Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ | |
6393 | ; | |
5287ad62 | 6394 | else |
477330fc RM |
6395 | { |
6396 | first_error (_("expected <Rm> or <Dm> or <Qm> operand")); | |
6397 | return FAIL; | |
6398 | } | |
5287ad62 | 6399 | } |
dcbf9037 | 6400 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
6401 | { |
6402 | /* Cases 6, 7. */ | |
6403 | inst.operands[i].reg = val; | |
6404 | inst.operands[i].isreg = 1; | |
6405 | inst.operands[i++].present = 1; | |
5f4273c7 | 6406 | |
5287ad62 | 6407 | if (skip_past_comma (&ptr) == FAIL) |
477330fc | 6408 | goto wanted_comma; |
5f4273c7 | 6409 | |
dcbf9037 | 6410 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
477330fc RM |
6411 | { |
6412 | /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ | |
6413 | inst.operands[i].reg = val; | |
6414 | inst.operands[i].isscalar = 1; | |
6415 | inst.operands[i].present = 1; | |
6416 | inst.operands[i].vectype = optype; | |
6417 | } | |
dcbf9037 | 6418 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
477330fc RM |
6419 | { |
6420 | /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ | |
6421 | inst.operands[i].reg = val; | |
6422 | inst.operands[i].isreg = 1; | |
6423 | inst.operands[i++].present = 1; | |
6424 | ||
6425 | if (skip_past_comma (&ptr) == FAIL) | |
6426 | goto wanted_comma; | |
6427 | ||
6428 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) | |
6429 | == FAIL) | |
6430 | { | |
6431 | first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); | |
6432 | return FAIL; | |
6433 | } | |
6434 | ||
6435 | inst.operands[i].reg = val; | |
6436 | inst.operands[i].isreg = 1; | |
6437 | inst.operands[i].isvec = 1; | |
6438 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
6439 | inst.operands[i].vectype = optype; | |
6440 | inst.operands[i].present = 1; | |
6441 | ||
6442 | if (rtype == REG_TYPE_VFS) | |
6443 | { | |
6444 | /* Case 14. */ | |
6445 | i++; | |
6446 | if (skip_past_comma (&ptr) == FAIL) | |
6447 | goto wanted_comma; | |
6448 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, | |
6449 | &optype)) == FAIL) | |
6450 | { | |
6451 | first_error (_(reg_expected_msgs[REG_TYPE_VFS])); | |
6452 | return FAIL; | |
6453 | } | |
6454 | inst.operands[i].reg = val; | |
6455 | inst.operands[i].isreg = 1; | |
6456 | inst.operands[i].isvec = 1; | |
6457 | inst.operands[i].issingle = 1; | |
6458 | inst.operands[i].vectype = optype; | |
6459 | inst.operands[i].present = 1; | |
6460 | } | |
6461 | } | |
037e8744 | 6462 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) |
477330fc RM |
6463 | != FAIL) |
6464 | { | |
6465 | /* Case 13. */ | |
6466 | inst.operands[i].reg = val; | |
6467 | inst.operands[i].isreg = 1; | |
6468 | inst.operands[i].isvec = 1; | |
6469 | inst.operands[i].issingle = 1; | |
6470 | inst.operands[i].vectype = optype; | |
6471 | inst.operands[i].present = 1; | |
6472 | } | |
5287ad62 JB |
6473 | } |
6474 | else | |
6475 | { | |
dcbf9037 | 6476 | first_error (_("parse error")); |
5287ad62 JB |
6477 | return FAIL; |
6478 | } | |
6479 | ||
6480 | /* Successfully parsed the operands. Update args. */ | |
6481 | *which_operand = i; | |
6482 | *str = ptr; | |
6483 | return SUCCESS; | |
6484 | ||
5f4273c7 | 6485 | wanted_comma: |
dcbf9037 | 6486 | first_error (_("expected comma")); |
5287ad62 | 6487 | return FAIL; |
5f4273c7 NC |
6488 | |
6489 | wanted_arm: | |
dcbf9037 | 6490 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
5287ad62 | 6491 | return FAIL; |
5287ad62 JB |
6492 | } |
6493 | ||
5be8be5d DG |
6494 | /* Use this macro when the operand constraints are different |
6495 | for ARM and THUMB (e.g. ldrd). */ | |
6496 | #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \ | |
6497 | ((arm_operand) | ((thumb_operand) << 16)) | |
6498 | ||
c19d1205 ZW |
6499 | /* Matcher codes for parse_operands. */ |
6500 | enum operand_parse_code | |
6501 | { | |
6502 | OP_stop, /* end of line */ | |
6503 | ||
6504 | OP_RR, /* ARM register */ | |
6505 | OP_RRnpc, /* ARM register, not r15 */ | |
5be8be5d | 6506 | OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */ |
c19d1205 | 6507 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ |
fa94de6b | 6508 | OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback, |
55881a11 | 6509 | optional trailing ! */ |
c19d1205 ZW |
6510 | OP_RRw, /* ARM register, not r15, optional trailing ! */ |
6511 | OP_RCP, /* Coprocessor number */ | |
6512 | OP_RCN, /* Coprocessor register */ | |
6513 | OP_RF, /* FPA register */ | |
6514 | OP_RVS, /* VFP single precision register */ | |
5287ad62 JB |
6515 | OP_RVD, /* VFP double precision register (0..15) */ |
6516 | OP_RND, /* Neon double precision register (0..31) */ | |
6517 | OP_RNQ, /* Neon quad precision register */ | |
037e8744 | 6518 | OP_RVSD, /* VFP single or double precision register */ |
dec41383 | 6519 | OP_RNSD, /* Neon single or double precision register */ |
5287ad62 | 6520 | OP_RNDQ, /* Neon double or quad precision register */ |
037e8744 | 6521 | OP_RNSDQ, /* Neon single, double or quad precision register */ |
5287ad62 | 6522 | OP_RNSC, /* Neon scalar D[X] */ |
c19d1205 ZW |
6523 | OP_RVC, /* VFP control register */ |
6524 | OP_RMF, /* Maverick F register */ | |
6525 | OP_RMD, /* Maverick D register */ | |
6526 | OP_RMFX, /* Maverick FX register */ | |
6527 | OP_RMDX, /* Maverick DX register */ | |
6528 | OP_RMAX, /* Maverick AX register */ | |
6529 | OP_RMDS, /* Maverick DSPSC register */ | |
6530 | OP_RIWR, /* iWMMXt wR register */ | |
6531 | OP_RIWC, /* iWMMXt wC register */ | |
6532 | OP_RIWG, /* iWMMXt wCG register */ | |
6533 | OP_RXA, /* XScale accumulator register */ | |
6534 | ||
6535 | OP_REGLST, /* ARM register list */ | |
6536 | OP_VRSLST, /* VFP single-precision register list */ | |
6537 | OP_VRDLST, /* VFP double-precision register list */ | |
037e8744 | 6538 | OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ |
5287ad62 JB |
6539 | OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ |
6540 | OP_NSTRLST, /* Neon element/structure list */ | |
6541 | ||
5287ad62 | 6542 | OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ |
037e8744 | 6543 | OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ |
aacf0b33 | 6544 | OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */ |
5287ad62 | 6545 | OP_RR_RNSC, /* ARM reg or Neon scalar. */ |
dec41383 | 6546 | OP_RNSD_RNSC, /* Neon S or D reg, or Neon scalar. */ |
037e8744 | 6547 | OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ |
5287ad62 JB |
6548 | OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ |
6549 | OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ | |
6550 | OP_VMOV, /* Neon VMOV operands. */ | |
4316f0d2 | 6551 | OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */ |
5287ad62 | 6552 | OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ |
2d447fca | 6553 | OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ |
5287ad62 JB |
6554 | |
6555 | OP_I0, /* immediate zero */ | |
c19d1205 ZW |
6556 | OP_I7, /* immediate value 0 .. 7 */ |
6557 | OP_I15, /* 0 .. 15 */ | |
6558 | OP_I16, /* 1 .. 16 */ | |
5287ad62 | 6559 | OP_I16z, /* 0 .. 16 */ |
c19d1205 ZW |
6560 | OP_I31, /* 0 .. 31 */ |
6561 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
6562 | OP_I32, /* 1 .. 32 */ | |
5287ad62 JB |
6563 | OP_I32z, /* 0 .. 32 */ |
6564 | OP_I63, /* 0 .. 63 */ | |
c19d1205 | 6565 | OP_I63s, /* -64 .. 63 */ |
5287ad62 JB |
6566 | OP_I64, /* 1 .. 64 */ |
6567 | OP_I64z, /* 0 .. 64 */ | |
c19d1205 | 6568 | OP_I255, /* 0 .. 255 */ |
c19d1205 ZW |
6569 | |
6570 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
6571 | OP_I7b, /* 0 .. 7 */ | |
6572 | OP_I15b, /* 0 .. 15 */ | |
6573 | OP_I31b, /* 0 .. 31 */ | |
6574 | ||
6575 | OP_SH, /* shifter operand */ | |
4962c51a | 6576 | OP_SHG, /* shifter operand with possible group relocation */ |
c19d1205 | 6577 | OP_ADDR, /* Memory address expression (any mode) */ |
4962c51a MS |
6578 | OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ |
6579 | OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ | |
6580 | OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ | |
c19d1205 ZW |
6581 | OP_EXP, /* arbitrary expression */ |
6582 | OP_EXPi, /* same, with optional immediate prefix */ | |
6583 | OP_EXPr, /* same, with optional relocation suffix */ | |
b6895b4f | 6584 | OP_HALF, /* 0 .. 65535 or low/high reloc. */ |
c28eeff2 SN |
6585 | OP_IROT1, /* VCADD rotate immediate: 90, 270. */ |
6586 | OP_IROT2, /* VCMLA rotate immediate: 0, 90, 180, 270. */ | |
c19d1205 ZW |
6587 | |
6588 | OP_CPSF, /* CPS flags */ | |
6589 | OP_ENDI, /* Endianness specifier */ | |
d2cd1205 JB |
6590 | OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */ |
6591 | OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */ | |
c19d1205 | 6592 | OP_COND, /* conditional code */ |
92e90b6e | 6593 | OP_TB, /* Table branch. */ |
c19d1205 | 6594 | |
037e8744 JB |
6595 | OP_APSR_RR, /* ARM register or "APSR_nzcv". */ |
6596 | ||
c19d1205 | 6597 | OP_RRnpc_I0, /* ARM register or literal 0 */ |
33eaf5de | 6598 | OP_RR_EXr, /* ARM register or expression with opt. reloc stuff. */ |
c19d1205 ZW |
6599 | OP_RR_EXi, /* ARM register or expression with imm prefix */ |
6600 | OP_RF_IF, /* FPA register or immediate */ | |
6601 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
41adaa5c | 6602 | OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ |
c19d1205 ZW |
6603 | |
6604 | /* Optional operands. */ | |
6605 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
6606 | OP_oI31b, /* 0 .. 31 */ | |
5287ad62 | 6607 | OP_oI32b, /* 1 .. 32 */ |
5f1af56b | 6608 | OP_oI32z, /* 0 .. 32 */ |
c19d1205 ZW |
6609 | OP_oIffffb, /* 0 .. 65535 */ |
6610 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
6611 | ||
6612 | OP_oRR, /* ARM register */ | |
6613 | OP_oRRnpc, /* ARM register, not the PC */ | |
5be8be5d | 6614 | OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */ |
b6702015 | 6615 | OP_oRRw, /* ARM register, not r15, optional trailing ! */ |
5287ad62 JB |
6616 | OP_oRND, /* Optional Neon double precision register */ |
6617 | OP_oRNQ, /* Optional Neon quad precision register */ | |
6618 | OP_oRNDQ, /* Optional Neon double or quad precision register */ | |
037e8744 | 6619 | OP_oRNSDQ, /* Optional single, double or quad precision vector register */ |
c19d1205 ZW |
6620 | OP_oSHll, /* LSL immediate */ |
6621 | OP_oSHar, /* ASR immediate */ | |
6622 | OP_oSHllar, /* LSL or ASR immediate */ | |
6623 | OP_oROR, /* ROR 0/8/16/24 */ | |
52e7f43d | 6624 | OP_oBARRIER_I15, /* Option argument for a barrier instruction. */ |
c19d1205 | 6625 | |
5be8be5d DG |
6626 | /* Some pre-defined mixed (ARM/THUMB) operands. */ |
6627 | OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp), | |
6628 | OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp), | |
6629 | OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp), | |
6630 | ||
c19d1205 ZW |
6631 | OP_FIRST_OPTIONAL = OP_oI7b |
6632 | }; | |
a737bd4d | 6633 | |
c19d1205 ZW |
6634 | /* Generic instruction operand parser. This does no encoding and no |
6635 | semantic validation; it merely squirrels values away in the inst | |
6636 | structure. Returns SUCCESS or FAIL depending on whether the | |
6637 | specified grammar matched. */ | |
6638 | static int | |
5be8be5d | 6639 | parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) |
c19d1205 | 6640 | { |
5be8be5d | 6641 | unsigned const int *upat = pattern; |
c19d1205 ZW |
6642 | char *backtrack_pos = 0; |
6643 | const char *backtrack_error = 0; | |
99aad254 | 6644 | int i, val = 0, backtrack_index = 0; |
5287ad62 | 6645 | enum arm_reg_type rtype; |
4962c51a | 6646 | parse_operand_result result; |
5be8be5d | 6647 | unsigned int op_parse_code; |
c19d1205 | 6648 | |
e07e6e58 NC |
6649 | #define po_char_or_fail(chr) \ |
6650 | do \ | |
6651 | { \ | |
6652 | if (skip_past_char (&str, chr) == FAIL) \ | |
477330fc | 6653 | goto bad_args; \ |
e07e6e58 NC |
6654 | } \ |
6655 | while (0) | |
c19d1205 | 6656 | |
e07e6e58 NC |
6657 | #define po_reg_or_fail(regtype) \ |
6658 | do \ | |
dcbf9037 | 6659 | { \ |
e07e6e58 | 6660 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ |
477330fc | 6661 | & inst.operands[i].vectype); \ |
e07e6e58 | 6662 | if (val == FAIL) \ |
477330fc RM |
6663 | { \ |
6664 | first_error (_(reg_expected_msgs[regtype])); \ | |
6665 | goto failure; \ | |
6666 | } \ | |
e07e6e58 NC |
6667 | inst.operands[i].reg = val; \ |
6668 | inst.operands[i].isreg = 1; \ | |
6669 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6670 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6671 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
477330fc RM |
6672 | || rtype == REG_TYPE_VFD \ |
6673 | || rtype == REG_TYPE_NQ); \ | |
dcbf9037 | 6674 | } \ |
e07e6e58 NC |
6675 | while (0) |
6676 | ||
6677 | #define po_reg_or_goto(regtype, label) \ | |
6678 | do \ | |
6679 | { \ | |
6680 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ | |
6681 | & inst.operands[i].vectype); \ | |
6682 | if (val == FAIL) \ | |
6683 | goto label; \ | |
dcbf9037 | 6684 | \ |
e07e6e58 NC |
6685 | inst.operands[i].reg = val; \ |
6686 | inst.operands[i].isreg = 1; \ | |
6687 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6688 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6689 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
477330fc | 6690 | || rtype == REG_TYPE_VFD \ |
e07e6e58 NC |
6691 | || rtype == REG_TYPE_NQ); \ |
6692 | } \ | |
6693 | while (0) | |
6694 | ||
6695 | #define po_imm_or_fail(min, max, popt) \ | |
6696 | do \ | |
6697 | { \ | |
6698 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
6699 | goto failure; \ | |
6700 | inst.operands[i].imm = val; \ | |
6701 | } \ | |
6702 | while (0) | |
6703 | ||
6704 | #define po_scalar_or_goto(elsz, label) \ | |
6705 | do \ | |
6706 | { \ | |
6707 | val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \ | |
6708 | if (val == FAIL) \ | |
6709 | goto label; \ | |
6710 | inst.operands[i].reg = val; \ | |
6711 | inst.operands[i].isscalar = 1; \ | |
6712 | } \ | |
6713 | while (0) | |
6714 | ||
6715 | #define po_misc_or_fail(expr) \ | |
6716 | do \ | |
6717 | { \ | |
6718 | if (expr) \ | |
6719 | goto failure; \ | |
6720 | } \ | |
6721 | while (0) | |
6722 | ||
6723 | #define po_misc_or_fail_no_backtrack(expr) \ | |
6724 | do \ | |
6725 | { \ | |
6726 | result = expr; \ | |
6727 | if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \ | |
6728 | backtrack_pos = 0; \ | |
6729 | if (result != PARSE_OPERAND_SUCCESS) \ | |
6730 | goto failure; \ | |
6731 | } \ | |
6732 | while (0) | |
4962c51a | 6733 | |
52e7f43d RE |
6734 | #define po_barrier_or_imm(str) \ |
6735 | do \ | |
6736 | { \ | |
6737 | val = parse_barrier (&str); \ | |
ccb84d65 JB |
6738 | if (val == FAIL && ! ISALPHA (*str)) \ |
6739 | goto immediate; \ | |
6740 | if (val == FAIL \ | |
6741 | /* ISB can only take SY as an option. */ \ | |
6742 | || ((inst.instruction & 0xf0) == 0x60 \ | |
6743 | && val != 0xf)) \ | |
52e7f43d | 6744 | { \ |
ccb84d65 JB |
6745 | inst.error = _("invalid barrier type"); \ |
6746 | backtrack_pos = 0; \ | |
6747 | goto failure; \ | |
52e7f43d RE |
6748 | } \ |
6749 | } \ | |
6750 | while (0) | |
6751 | ||
c19d1205 ZW |
6752 | skip_whitespace (str); |
6753 | ||
6754 | for (i = 0; upat[i] != OP_stop; i++) | |
6755 | { | |
5be8be5d DG |
6756 | op_parse_code = upat[i]; |
6757 | if (op_parse_code >= 1<<16) | |
6758 | op_parse_code = thumb ? (op_parse_code >> 16) | |
6759 | : (op_parse_code & ((1<<16)-1)); | |
6760 | ||
6761 | if (op_parse_code >= OP_FIRST_OPTIONAL) | |
c19d1205 ZW |
6762 | { |
6763 | /* Remember where we are in case we need to backtrack. */ | |
9c2799c2 | 6764 | gas_assert (!backtrack_pos); |
c19d1205 ZW |
6765 | backtrack_pos = str; |
6766 | backtrack_error = inst.error; | |
6767 | backtrack_index = i; | |
6768 | } | |
6769 | ||
b6702015 | 6770 | if (i > 0 && (i > 1 || inst.operands[0].present)) |
c19d1205 ZW |
6771 | po_char_or_fail (','); |
6772 | ||
5be8be5d | 6773 | switch (op_parse_code) |
c19d1205 ZW |
6774 | { |
6775 | /* Registers */ | |
6776 | case OP_oRRnpc: | |
5be8be5d | 6777 | case OP_oRRnpcsp: |
c19d1205 | 6778 | case OP_RRnpc: |
5be8be5d | 6779 | case OP_RRnpcsp: |
c19d1205 ZW |
6780 | case OP_oRR: |
6781 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; | |
6782 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
6783 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
6784 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
6785 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
6786 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
477330fc | 6787 | case OP_oRND: |
5287ad62 | 6788 | case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; |
cd2cf30b PB |
6789 | case OP_RVC: |
6790 | po_reg_or_goto (REG_TYPE_VFC, coproc_reg); | |
6791 | break; | |
6792 | /* Also accept generic coprocessor regs for unknown registers. */ | |
6793 | coproc_reg: | |
6794 | po_reg_or_fail (REG_TYPE_CN); | |
6795 | break; | |
c19d1205 ZW |
6796 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; |
6797 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
6798 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
6799 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
6800 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
6801 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
6802 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
6803 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
6804 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
6805 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
477330fc | 6806 | case OP_oRNQ: |
5287ad62 | 6807 | case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; |
dec41383 | 6808 | case OP_RNSD: po_reg_or_fail (REG_TYPE_NSD); break; |
477330fc | 6809 | case OP_oRNDQ: |
5287ad62 | 6810 | case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; |
477330fc RM |
6811 | case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; |
6812 | case OP_oRNSDQ: | |
6813 | case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; | |
6814 | ||
6815 | /* Neon scalar. Using an element size of 8 means that some invalid | |
6816 | scalars are accepted here, so deal with those in later code. */ | |
6817 | case OP_RNSC: po_scalar_or_goto (8, failure); break; | |
6818 | ||
6819 | case OP_RNDQ_I0: | |
6820 | { | |
6821 | po_reg_or_goto (REG_TYPE_NDQ, try_imm0); | |
6822 | break; | |
6823 | try_imm0: | |
6824 | po_imm_or_fail (0, 0, TRUE); | |
6825 | } | |
6826 | break; | |
6827 | ||
6828 | case OP_RVSD_I0: | |
6829 | po_reg_or_goto (REG_TYPE_VFSD, try_imm0); | |
6830 | break; | |
6831 | ||
aacf0b33 KT |
6832 | case OP_RSVD_FI0: |
6833 | { | |
6834 | po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0); | |
6835 | break; | |
6836 | try_ifimm0: | |
6837 | if (parse_ifimm_zero (&str)) | |
6838 | inst.operands[i].imm = 0; | |
6839 | else | |
6840 | { | |
6841 | inst.error | |
6842 | = _("only floating point zero is allowed as immediate value"); | |
6843 | goto failure; | |
6844 | } | |
6845 | } | |
6846 | break; | |
6847 | ||
477330fc RM |
6848 | case OP_RR_RNSC: |
6849 | { | |
6850 | po_scalar_or_goto (8, try_rr); | |
6851 | break; | |
6852 | try_rr: | |
6853 | po_reg_or_fail (REG_TYPE_RN); | |
6854 | } | |
6855 | break; | |
6856 | ||
6857 | case OP_RNSDQ_RNSC: | |
6858 | { | |
6859 | po_scalar_or_goto (8, try_nsdq); | |
6860 | break; | |
6861 | try_nsdq: | |
6862 | po_reg_or_fail (REG_TYPE_NSDQ); | |
6863 | } | |
6864 | break; | |
6865 | ||
dec41383 JW |
6866 | case OP_RNSD_RNSC: |
6867 | { | |
6868 | po_scalar_or_goto (8, try_s_scalar); | |
6869 | break; | |
6870 | try_s_scalar: | |
6871 | po_scalar_or_goto (4, try_nsd); | |
6872 | break; | |
6873 | try_nsd: | |
6874 | po_reg_or_fail (REG_TYPE_NSD); | |
6875 | } | |
6876 | break; | |
6877 | ||
477330fc RM |
6878 | case OP_RNDQ_RNSC: |
6879 | { | |
6880 | po_scalar_or_goto (8, try_ndq); | |
6881 | break; | |
6882 | try_ndq: | |
6883 | po_reg_or_fail (REG_TYPE_NDQ); | |
6884 | } | |
6885 | break; | |
6886 | ||
6887 | case OP_RND_RNSC: | |
6888 | { | |
6889 | po_scalar_or_goto (8, try_vfd); | |
6890 | break; | |
6891 | try_vfd: | |
6892 | po_reg_or_fail (REG_TYPE_VFD); | |
6893 | } | |
6894 | break; | |
6895 | ||
6896 | case OP_VMOV: | |
6897 | /* WARNING: parse_neon_mov can move the operand counter, i. If we're | |
6898 | not careful then bad things might happen. */ | |
6899 | po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); | |
6900 | break; | |
6901 | ||
6902 | case OP_RNDQ_Ibig: | |
6903 | { | |
6904 | po_reg_or_goto (REG_TYPE_NDQ, try_immbig); | |
6905 | break; | |
6906 | try_immbig: | |
6907 | /* There's a possibility of getting a 64-bit immediate here, so | |
6908 | we need special handling. */ | |
8335d6aa JW |
6909 | if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE) |
6910 | == FAIL) | |
477330fc RM |
6911 | { |
6912 | inst.error = _("immediate value is out of range"); | |
6913 | goto failure; | |
6914 | } | |
6915 | } | |
6916 | break; | |
6917 | ||
6918 | case OP_RNDQ_I63b: | |
6919 | { | |
6920 | po_reg_or_goto (REG_TYPE_NDQ, try_shimm); | |
6921 | break; | |
6922 | try_shimm: | |
6923 | po_imm_or_fail (0, 63, TRUE); | |
6924 | } | |
6925 | break; | |
c19d1205 ZW |
6926 | |
6927 | case OP_RRnpcb: | |
6928 | po_char_or_fail ('['); | |
6929 | po_reg_or_fail (REG_TYPE_RN); | |
6930 | po_char_or_fail (']'); | |
6931 | break; | |
a737bd4d | 6932 | |
55881a11 | 6933 | case OP_RRnpctw: |
c19d1205 | 6934 | case OP_RRw: |
b6702015 | 6935 | case OP_oRRw: |
c19d1205 ZW |
6936 | po_reg_or_fail (REG_TYPE_RN); |
6937 | if (skip_past_char (&str, '!') == SUCCESS) | |
6938 | inst.operands[i].writeback = 1; | |
6939 | break; | |
6940 | ||
6941 | /* Immediates */ | |
6942 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
6943 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
6944 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
477330fc | 6945 | case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; |
c19d1205 ZW |
6946 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; |
6947 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
477330fc | 6948 | case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; |
c19d1205 | 6949 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; |
477330fc RM |
6950 | case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; |
6951 | case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; | |
6952 | case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; | |
c19d1205 | 6953 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; |
c19d1205 ZW |
6954 | |
6955 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
6956 | case OP_oI7b: | |
6957 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
6958 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
6959 | case OP_oI31b: | |
6960 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
477330fc RM |
6961 | case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; |
6962 | case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break; | |
c19d1205 ZW |
6963 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; |
6964 | ||
6965 | /* Immediate variants */ | |
6966 | case OP_oI255c: | |
6967 | po_char_or_fail ('{'); | |
6968 | po_imm_or_fail (0, 255, TRUE); | |
6969 | po_char_or_fail ('}'); | |
6970 | break; | |
6971 | ||
6972 | case OP_I31w: | |
6973 | /* The expression parser chokes on a trailing !, so we have | |
6974 | to find it first and zap it. */ | |
6975 | { | |
6976 | char *s = str; | |
6977 | while (*s && *s != ',') | |
6978 | s++; | |
6979 | if (s[-1] == '!') | |
6980 | { | |
6981 | s[-1] = '\0'; | |
6982 | inst.operands[i].writeback = 1; | |
6983 | } | |
6984 | po_imm_or_fail (0, 31, TRUE); | |
6985 | if (str == s - 1) | |
6986 | str = s; | |
6987 | } | |
6988 | break; | |
6989 | ||
6990 | /* Expressions */ | |
6991 | case OP_EXPi: EXPi: | |
6992 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6993 | GE_OPT_PREFIX)); | |
6994 | break; | |
6995 | ||
6996 | case OP_EXP: | |
6997 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6998 | GE_NO_PREFIX)); | |
6999 | break; | |
7000 | ||
7001 | case OP_EXPr: EXPr: | |
7002 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
7003 | GE_NO_PREFIX)); | |
7004 | if (inst.reloc.exp.X_op == O_symbol) | |
a737bd4d | 7005 | { |
c19d1205 ZW |
7006 | val = parse_reloc (&str); |
7007 | if (val == -1) | |
7008 | { | |
7009 | inst.error = _("unrecognized relocation suffix"); | |
7010 | goto failure; | |
7011 | } | |
7012 | else if (val != BFD_RELOC_UNUSED) | |
7013 | { | |
7014 | inst.operands[i].imm = val; | |
7015 | inst.operands[i].hasreloc = 1; | |
7016 | } | |
a737bd4d | 7017 | } |
c19d1205 | 7018 | break; |
a737bd4d | 7019 | |
b6895b4f PB |
7020 | /* Operand for MOVW or MOVT. */ |
7021 | case OP_HALF: | |
7022 | po_misc_or_fail (parse_half (&str)); | |
7023 | break; | |
7024 | ||
e07e6e58 | 7025 | /* Register or expression. */ |
c19d1205 ZW |
7026 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; |
7027 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 7028 | |
e07e6e58 | 7029 | /* Register or immediate. */ |
c19d1205 ZW |
7030 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; |
7031 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 7032 | |
c19d1205 ZW |
7033 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
7034 | IF: | |
7035 | if (!is_immediate_prefix (*str)) | |
7036 | goto bad_args; | |
7037 | str++; | |
7038 | val = parse_fpa_immediate (&str); | |
7039 | if (val == FAIL) | |
7040 | goto failure; | |
7041 | /* FPA immediates are encoded as registers 8-15. | |
7042 | parse_fpa_immediate has already applied the offset. */ | |
7043 | inst.operands[i].reg = val; | |
7044 | inst.operands[i].isreg = 1; | |
7045 | break; | |
09d92015 | 7046 | |
2d447fca JM |
7047 | case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; |
7048 | I32z: po_imm_or_fail (0, 32, FALSE); break; | |
7049 | ||
e07e6e58 | 7050 | /* Two kinds of register. */ |
c19d1205 ZW |
7051 | case OP_RIWR_RIWC: |
7052 | { | |
7053 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
97f87066 JM |
7054 | if (!rege |
7055 | || (rege->type != REG_TYPE_MMXWR | |
7056 | && rege->type != REG_TYPE_MMXWC | |
7057 | && rege->type != REG_TYPE_MMXWCG)) | |
c19d1205 ZW |
7058 | { |
7059 | inst.error = _("iWMMXt data or control register expected"); | |
7060 | goto failure; | |
7061 | } | |
7062 | inst.operands[i].reg = rege->number; | |
7063 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
7064 | } | |
7065 | break; | |
09d92015 | 7066 | |
41adaa5c JM |
7067 | case OP_RIWC_RIWG: |
7068 | { | |
7069 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
7070 | if (!rege | |
7071 | || (rege->type != REG_TYPE_MMXWC | |
7072 | && rege->type != REG_TYPE_MMXWCG)) | |
7073 | { | |
7074 | inst.error = _("iWMMXt control register expected"); | |
7075 | goto failure; | |
7076 | } | |
7077 | inst.operands[i].reg = rege->number; | |
7078 | inst.operands[i].isreg = 1; | |
7079 | } | |
7080 | break; | |
7081 | ||
c19d1205 ZW |
7082 | /* Misc */ |
7083 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
7084 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
7085 | case OP_oROR: val = parse_ror (&str); break; | |
c19d1205 | 7086 | case OP_COND: val = parse_cond (&str); break; |
52e7f43d RE |
7087 | case OP_oBARRIER_I15: |
7088 | po_barrier_or_imm (str); break; | |
7089 | immediate: | |
7090 | if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL) | |
477330fc | 7091 | goto failure; |
52e7f43d | 7092 | break; |
c19d1205 | 7093 | |
fa94de6b | 7094 | case OP_wPSR: |
d2cd1205 | 7095 | case OP_rPSR: |
90ec0d68 MGD |
7096 | po_reg_or_goto (REG_TYPE_RNB, try_psr); |
7097 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt)) | |
7098 | { | |
7099 | inst.error = _("Banked registers are not available with this " | |
7100 | "architecture."); | |
7101 | goto failure; | |
7102 | } | |
7103 | break; | |
d2cd1205 JB |
7104 | try_psr: |
7105 | val = parse_psr (&str, op_parse_code == OP_wPSR); | |
7106 | break; | |
037e8744 | 7107 | |
477330fc RM |
7108 | case OP_APSR_RR: |
7109 | po_reg_or_goto (REG_TYPE_RN, try_apsr); | |
7110 | break; | |
7111 | try_apsr: | |
7112 | /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS | |
7113 | instruction). */ | |
7114 | if (strncasecmp (str, "APSR_", 5) == 0) | |
7115 | { | |
7116 | unsigned found = 0; | |
7117 | str += 5; | |
7118 | while (found < 15) | |
7119 | switch (*str++) | |
7120 | { | |
7121 | case 'c': found = (found & 1) ? 16 : found | 1; break; | |
7122 | case 'n': found = (found & 2) ? 16 : found | 2; break; | |
7123 | case 'z': found = (found & 4) ? 16 : found | 4; break; | |
7124 | case 'v': found = (found & 8) ? 16 : found | 8; break; | |
7125 | default: found = 16; | |
7126 | } | |
7127 | if (found != 15) | |
7128 | goto failure; | |
7129 | inst.operands[i].isvec = 1; | |
f7c21dc7 NC |
7130 | /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */ |
7131 | inst.operands[i].reg = REG_PC; | |
477330fc RM |
7132 | } |
7133 | else | |
7134 | goto failure; | |
7135 | break; | |
037e8744 | 7136 | |
92e90b6e PB |
7137 | case OP_TB: |
7138 | po_misc_or_fail (parse_tb (&str)); | |
7139 | break; | |
7140 | ||
e07e6e58 | 7141 | /* Register lists. */ |
c19d1205 ZW |
7142 | case OP_REGLST: |
7143 | val = parse_reg_list (&str); | |
7144 | if (*str == '^') | |
7145 | { | |
5e0d7f77 | 7146 | inst.operands[i].writeback = 1; |
c19d1205 ZW |
7147 | str++; |
7148 | } | |
7149 | break; | |
09d92015 | 7150 | |
c19d1205 | 7151 | case OP_VRSLST: |
5287ad62 | 7152 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); |
c19d1205 | 7153 | break; |
09d92015 | 7154 | |
c19d1205 | 7155 | case OP_VRDLST: |
5287ad62 | 7156 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); |
c19d1205 | 7157 | break; |
a737bd4d | 7158 | |
477330fc RM |
7159 | case OP_VRSDLST: |
7160 | /* Allow Q registers too. */ | |
7161 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
7162 | REGLIST_NEON_D); | |
7163 | if (val == FAIL) | |
7164 | { | |
7165 | inst.error = NULL; | |
7166 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
7167 | REGLIST_VFP_S); | |
7168 | inst.operands[i].issingle = 1; | |
7169 | } | |
7170 | break; | |
7171 | ||
7172 | case OP_NRDLST: | |
7173 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
7174 | REGLIST_NEON_D); | |
7175 | break; | |
5287ad62 JB |
7176 | |
7177 | case OP_NSTRLST: | |
477330fc RM |
7178 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, |
7179 | &inst.operands[i].vectype); | |
7180 | break; | |
5287ad62 | 7181 | |
c19d1205 ZW |
7182 | /* Addressing modes */ |
7183 | case OP_ADDR: | |
7184 | po_misc_or_fail (parse_address (&str, i)); | |
7185 | break; | |
09d92015 | 7186 | |
4962c51a MS |
7187 | case OP_ADDRGLDR: |
7188 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7189 | parse_address_group_reloc (&str, i, GROUP_LDR)); |
4962c51a MS |
7190 | break; |
7191 | ||
7192 | case OP_ADDRGLDRS: | |
7193 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7194 | parse_address_group_reloc (&str, i, GROUP_LDRS)); |
4962c51a MS |
7195 | break; |
7196 | ||
7197 | case OP_ADDRGLDC: | |
7198 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7199 | parse_address_group_reloc (&str, i, GROUP_LDC)); |
4962c51a MS |
7200 | break; |
7201 | ||
c19d1205 ZW |
7202 | case OP_SH: |
7203 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
7204 | break; | |
09d92015 | 7205 | |
4962c51a MS |
7206 | case OP_SHG: |
7207 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7208 | parse_shifter_operand_group_reloc (&str, i)); |
4962c51a MS |
7209 | break; |
7210 | ||
c19d1205 ZW |
7211 | case OP_oSHll: |
7212 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
7213 | break; | |
09d92015 | 7214 | |
c19d1205 ZW |
7215 | case OP_oSHar: |
7216 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
7217 | break; | |
09d92015 | 7218 | |
c19d1205 ZW |
7219 | case OP_oSHllar: |
7220 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
7221 | break; | |
09d92015 | 7222 | |
c19d1205 | 7223 | default: |
5be8be5d | 7224 | as_fatal (_("unhandled operand code %d"), op_parse_code); |
c19d1205 | 7225 | } |
09d92015 | 7226 | |
c19d1205 ZW |
7227 | /* Various value-based sanity checks and shared operations. We |
7228 | do not signal immediate failures for the register constraints; | |
7229 | this allows a syntax error to take precedence. */ | |
5be8be5d | 7230 | switch (op_parse_code) |
c19d1205 ZW |
7231 | { |
7232 | case OP_oRRnpc: | |
7233 | case OP_RRnpc: | |
7234 | case OP_RRnpcb: | |
7235 | case OP_RRw: | |
b6702015 | 7236 | case OP_oRRw: |
c19d1205 ZW |
7237 | case OP_RRnpc_I0: |
7238 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
7239 | inst.error = BAD_PC; | |
7240 | break; | |
09d92015 | 7241 | |
5be8be5d DG |
7242 | case OP_oRRnpcsp: |
7243 | case OP_RRnpcsp: | |
7244 | if (inst.operands[i].isreg) | |
7245 | { | |
7246 | if (inst.operands[i].reg == REG_PC) | |
7247 | inst.error = BAD_PC; | |
5c8ed6a4 JW |
7248 | else if (inst.operands[i].reg == REG_SP |
7249 | /* The restriction on Rd/Rt/Rt2 on Thumb mode has been | |
7250 | relaxed since ARMv8-A. */ | |
7251 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
7252 | { | |
7253 | gas_assert (thumb); | |
7254 | inst.error = BAD_SP; | |
7255 | } | |
5be8be5d DG |
7256 | } |
7257 | break; | |
7258 | ||
55881a11 | 7259 | case OP_RRnpctw: |
fa94de6b RM |
7260 | if (inst.operands[i].isreg |
7261 | && inst.operands[i].reg == REG_PC | |
55881a11 MGD |
7262 | && (inst.operands[i].writeback || thumb)) |
7263 | inst.error = BAD_PC; | |
7264 | break; | |
7265 | ||
c19d1205 ZW |
7266 | case OP_CPSF: |
7267 | case OP_ENDI: | |
7268 | case OP_oROR: | |
d2cd1205 JB |
7269 | case OP_wPSR: |
7270 | case OP_rPSR: | |
c19d1205 | 7271 | case OP_COND: |
52e7f43d | 7272 | case OP_oBARRIER_I15: |
c19d1205 ZW |
7273 | case OP_REGLST: |
7274 | case OP_VRSLST: | |
7275 | case OP_VRDLST: | |
477330fc RM |
7276 | case OP_VRSDLST: |
7277 | case OP_NRDLST: | |
7278 | case OP_NSTRLST: | |
c19d1205 ZW |
7279 | if (val == FAIL) |
7280 | goto failure; | |
7281 | inst.operands[i].imm = val; | |
7282 | break; | |
a737bd4d | 7283 | |
c19d1205 ZW |
7284 | default: |
7285 | break; | |
7286 | } | |
09d92015 | 7287 | |
c19d1205 ZW |
7288 | /* If we get here, this operand was successfully parsed. */ |
7289 | inst.operands[i].present = 1; | |
7290 | continue; | |
09d92015 | 7291 | |
c19d1205 | 7292 | bad_args: |
09d92015 | 7293 | inst.error = BAD_ARGS; |
c19d1205 ZW |
7294 | |
7295 | failure: | |
7296 | if (!backtrack_pos) | |
d252fdde PB |
7297 | { |
7298 | /* The parse routine should already have set inst.error, but set a | |
5f4273c7 | 7299 | default here just in case. */ |
d252fdde PB |
7300 | if (!inst.error) |
7301 | inst.error = _("syntax error"); | |
7302 | return FAIL; | |
7303 | } | |
c19d1205 ZW |
7304 | |
7305 | /* Do not backtrack over a trailing optional argument that | |
7306 | absorbed some text. We will only fail again, with the | |
7307 | 'garbage following instruction' error message, which is | |
7308 | probably less helpful than the current one. */ | |
7309 | if (backtrack_index == i && backtrack_pos != str | |
7310 | && upat[i+1] == OP_stop) | |
d252fdde PB |
7311 | { |
7312 | if (!inst.error) | |
7313 | inst.error = _("syntax error"); | |
7314 | return FAIL; | |
7315 | } | |
c19d1205 ZW |
7316 | |
7317 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
7318 | str = backtrack_pos; | |
7319 | inst.error = backtrack_error; | |
7320 | inst.operands[backtrack_index].present = 0; | |
7321 | i = backtrack_index; | |
7322 | backtrack_pos = 0; | |
09d92015 | 7323 | } |
09d92015 | 7324 | |
c19d1205 ZW |
7325 | /* Check that we have parsed all the arguments. */ |
7326 | if (*str != '\0' && !inst.error) | |
7327 | inst.error = _("garbage following instruction"); | |
09d92015 | 7328 | |
c19d1205 | 7329 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
7330 | } |
7331 | ||
c19d1205 ZW |
7332 | #undef po_char_or_fail |
7333 | #undef po_reg_or_fail | |
7334 | #undef po_reg_or_goto | |
7335 | #undef po_imm_or_fail | |
5287ad62 | 7336 | #undef po_scalar_or_fail |
52e7f43d | 7337 | #undef po_barrier_or_imm |
e07e6e58 | 7338 | |
c19d1205 | 7339 | /* Shorthand macro for instruction encoding functions issuing errors. */ |
e07e6e58 NC |
7340 | #define constraint(expr, err) \ |
7341 | do \ | |
c19d1205 | 7342 | { \ |
e07e6e58 NC |
7343 | if (expr) \ |
7344 | { \ | |
7345 | inst.error = err; \ | |
7346 | return; \ | |
7347 | } \ | |
c19d1205 | 7348 | } \ |
e07e6e58 | 7349 | while (0) |
c19d1205 | 7350 | |
fdfde340 JM |
7351 | /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 |
7352 | instructions are unpredictable if these registers are used. This | |
5c8ed6a4 JW |
7353 | is the BadReg predicate in ARM's Thumb-2 documentation. |
7354 | ||
7355 | Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few | |
7356 | places, while the restriction on REG_SP was relaxed since ARMv8-A. */ | |
7357 | #define reject_bad_reg(reg) \ | |
7358 | do \ | |
7359 | if (reg == REG_PC) \ | |
7360 | { \ | |
7361 | inst.error = BAD_PC; \ | |
7362 | return; \ | |
7363 | } \ | |
7364 | else if (reg == REG_SP \ | |
7365 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \ | |
7366 | { \ | |
7367 | inst.error = BAD_SP; \ | |
7368 | return; \ | |
7369 | } \ | |
fdfde340 JM |
7370 | while (0) |
7371 | ||
94206790 MM |
7372 | /* If REG is R13 (the stack pointer), warn that its use is |
7373 | deprecated. */ | |
7374 | #define warn_deprecated_sp(reg) \ | |
7375 | do \ | |
7376 | if (warn_on_deprecated && reg == REG_SP) \ | |
5c3696f8 | 7377 | as_tsktsk (_("use of r13 is deprecated")); \ |
94206790 MM |
7378 | while (0) |
7379 | ||
c19d1205 ZW |
7380 | /* Functions for operand encoding. ARM, then Thumb. */ |
7381 | ||
d840c081 | 7382 | #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31)) |
c19d1205 | 7383 | |
9db2f6b4 RL |
7384 | /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding. |
7385 | ||
7386 | The only binary encoding difference is the Coprocessor number. Coprocessor | |
7387 | 9 is used for half-precision calculations or conversions. The format of the | |
2b0f3761 | 7388 | instruction is the same as the equivalent Coprocessor 10 instruction that |
9db2f6b4 RL |
7389 | exists for Single-Precision operation. */ |
7390 | ||
7391 | static void | |
7392 | do_scalar_fp16_v82_encode (void) | |
7393 | { | |
7394 | if (inst.cond != COND_ALWAYS) | |
7395 | as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional," | |
7396 | " the behaviour is UNPREDICTABLE")); | |
7397 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16), | |
7398 | _(BAD_FP16)); | |
7399 | ||
7400 | inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900; | |
7401 | mark_feature_used (&arm_ext_fp16); | |
7402 | } | |
7403 | ||
c19d1205 ZW |
7404 | /* If VAL can be encoded in the immediate field of an ARM instruction, |
7405 | return the encoded form. Otherwise, return FAIL. */ | |
7406 | ||
7407 | static unsigned int | |
7408 | encode_arm_immediate (unsigned int val) | |
09d92015 | 7409 | { |
c19d1205 ZW |
7410 | unsigned int a, i; |
7411 | ||
4f1d6205 L |
7412 | if (val <= 0xff) |
7413 | return val; | |
7414 | ||
7415 | for (i = 2; i < 32; i += 2) | |
c19d1205 ZW |
7416 | if ((a = rotate_left (val, i)) <= 0xff) |
7417 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
7418 | ||
7419 | return FAIL; | |
09d92015 MM |
7420 | } |
7421 | ||
c19d1205 ZW |
7422 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
7423 | return the encoded form. Otherwise, return FAIL. */ | |
7424 | static unsigned int | |
7425 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 7426 | { |
c19d1205 | 7427 | unsigned int a, i; |
09d92015 | 7428 | |
9c3c69f2 | 7429 | if (val <= 0xff) |
c19d1205 | 7430 | return val; |
a737bd4d | 7431 | |
9c3c69f2 | 7432 | for (i = 1; i <= 24; i++) |
09d92015 | 7433 | { |
9c3c69f2 PB |
7434 | a = val >> i; |
7435 | if ((val & ~(0xff << i)) == 0) | |
7436 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 7437 | } |
a737bd4d | 7438 | |
c19d1205 ZW |
7439 | a = val & 0xff; |
7440 | if (val == ((a << 16) | a)) | |
7441 | return 0x100 | a; | |
7442 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
7443 | return 0x300 | a; | |
09d92015 | 7444 | |
c19d1205 ZW |
7445 | a = val & 0xff00; |
7446 | if (val == ((a << 16) | a)) | |
7447 | return 0x200 | (a >> 8); | |
a737bd4d | 7448 | |
c19d1205 | 7449 | return FAIL; |
09d92015 | 7450 | } |
5287ad62 | 7451 | /* Encode a VFP SP or DP register number into inst.instruction. */ |
09d92015 MM |
7452 | |
7453 | static void | |
5287ad62 JB |
7454 | encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) |
7455 | { | |
7456 | if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) | |
7457 | && reg > 15) | |
7458 | { | |
b1cc4aeb | 7459 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) |
477330fc RM |
7460 | { |
7461 | if (thumb_mode) | |
7462 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
7463 | fpu_vfp_ext_d32); | |
7464 | else | |
7465 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
7466 | fpu_vfp_ext_d32); | |
7467 | } | |
5287ad62 | 7468 | else |
477330fc RM |
7469 | { |
7470 | first_error (_("D register out of range for selected VFP version")); | |
7471 | return; | |
7472 | } | |
5287ad62 JB |
7473 | } |
7474 | ||
c19d1205 | 7475 | switch (pos) |
09d92015 | 7476 | { |
c19d1205 ZW |
7477 | case VFP_REG_Sd: |
7478 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
7479 | break; | |
7480 | ||
7481 | case VFP_REG_Sn: | |
7482 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
7483 | break; | |
7484 | ||
7485 | case VFP_REG_Sm: | |
7486 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
7487 | break; | |
7488 | ||
5287ad62 JB |
7489 | case VFP_REG_Dd: |
7490 | inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); | |
7491 | break; | |
5f4273c7 | 7492 | |
5287ad62 JB |
7493 | case VFP_REG_Dn: |
7494 | inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); | |
7495 | break; | |
5f4273c7 | 7496 | |
5287ad62 JB |
7497 | case VFP_REG_Dm: |
7498 | inst.instruction |= (reg & 15) | ((reg >> 4) << 5); | |
7499 | break; | |
7500 | ||
c19d1205 ZW |
7501 | default: |
7502 | abort (); | |
09d92015 | 7503 | } |
09d92015 MM |
7504 | } |
7505 | ||
c19d1205 | 7506 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 7507 | if any, is handled by md_apply_fix. */ |
09d92015 | 7508 | static void |
c19d1205 | 7509 | encode_arm_shift (int i) |
09d92015 | 7510 | { |
008a97ef RL |
7511 | /* register-shifted register. */ |
7512 | if (inst.operands[i].immisreg) | |
7513 | { | |
bf355b69 MR |
7514 | int op_index; |
7515 | for (op_index = 0; op_index <= i; ++op_index) | |
008a97ef | 7516 | { |
5689c942 RL |
7517 | /* Check the operand only when it's presented. In pre-UAL syntax, |
7518 | if the destination register is the same as the first operand, two | |
7519 | register form of the instruction can be used. */ | |
bf355b69 MR |
7520 | if (inst.operands[op_index].present && inst.operands[op_index].isreg |
7521 | && inst.operands[op_index].reg == REG_PC) | |
008a97ef RL |
7522 | as_warn (UNPRED_REG ("r15")); |
7523 | } | |
7524 | ||
7525 | if (inst.operands[i].imm == REG_PC) | |
7526 | as_warn (UNPRED_REG ("r15")); | |
7527 | } | |
7528 | ||
c19d1205 ZW |
7529 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
7530 | inst.instruction |= SHIFT_ROR << 5; | |
7531 | else | |
09d92015 | 7532 | { |
c19d1205 ZW |
7533 | inst.instruction |= inst.operands[i].shift_kind << 5; |
7534 | if (inst.operands[i].immisreg) | |
7535 | { | |
7536 | inst.instruction |= SHIFT_BY_REG; | |
7537 | inst.instruction |= inst.operands[i].imm << 8; | |
7538 | } | |
7539 | else | |
7540 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
09d92015 | 7541 | } |
c19d1205 | 7542 | } |
09d92015 | 7543 | |
c19d1205 ZW |
7544 | static void |
7545 | encode_arm_shifter_operand (int i) | |
7546 | { | |
7547 | if (inst.operands[i].isreg) | |
09d92015 | 7548 | { |
c19d1205 ZW |
7549 | inst.instruction |= inst.operands[i].reg; |
7550 | encode_arm_shift (i); | |
09d92015 | 7551 | } |
c19d1205 | 7552 | else |
a415b1cd JB |
7553 | { |
7554 | inst.instruction |= INST_IMMEDIATE; | |
7555 | if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE) | |
7556 | inst.instruction |= inst.operands[i].imm; | |
7557 | } | |
09d92015 MM |
7558 | } |
7559 | ||
c19d1205 | 7560 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 7561 | static void |
c19d1205 | 7562 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 7563 | { |
2b2f5df9 NC |
7564 | /* PR 14260: |
7565 | Generate an error if the operand is not a register. */ | |
7566 | constraint (!inst.operands[i].isreg, | |
7567 | _("Instruction does not support =N addresses")); | |
7568 | ||
c19d1205 | 7569 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 7570 | |
c19d1205 | 7571 | if (inst.operands[i].preind) |
09d92015 | 7572 | { |
c19d1205 ZW |
7573 | if (is_t) |
7574 | { | |
7575 | inst.error = _("instruction does not accept preindexed addressing"); | |
7576 | return; | |
7577 | } | |
7578 | inst.instruction |= PRE_INDEX; | |
7579 | if (inst.operands[i].writeback) | |
7580 | inst.instruction |= WRITE_BACK; | |
09d92015 | 7581 | |
c19d1205 ZW |
7582 | } |
7583 | else if (inst.operands[i].postind) | |
7584 | { | |
9c2799c2 | 7585 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
7586 | if (is_t) |
7587 | inst.instruction |= WRITE_BACK; | |
7588 | } | |
7589 | else /* unindexed - only for coprocessor */ | |
09d92015 | 7590 | { |
c19d1205 | 7591 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
7592 | return; |
7593 | } | |
7594 | ||
c19d1205 ZW |
7595 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
7596 | && (((inst.instruction & 0x000f0000) >> 16) | |
7597 | == ((inst.instruction & 0x0000f000) >> 12))) | |
7598 | as_warn ((inst.instruction & LOAD_BIT) | |
7599 | ? _("destination register same as write-back base") | |
7600 | : _("source register same as write-back base")); | |
09d92015 MM |
7601 | } |
7602 | ||
c19d1205 ZW |
7603 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7604 | ARM-format mode 2 load or store instruction. If is_t is true, | |
7605 | reject forms that cannot be used with a T instruction (i.e. not | |
7606 | post-indexed). */ | |
a737bd4d | 7607 | static void |
c19d1205 | 7608 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 7609 | { |
5be8be5d DG |
7610 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
7611 | ||
c19d1205 | 7612 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 7613 | |
c19d1205 | 7614 | if (inst.operands[i].immisreg) |
09d92015 | 7615 | { |
5be8be5d DG |
7616 | constraint ((inst.operands[i].imm == REG_PC |
7617 | || (is_pc && inst.operands[i].writeback)), | |
7618 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
7619 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
7620 | inst.instruction |= inst.operands[i].imm; | |
7621 | if (!inst.operands[i].negative) | |
7622 | inst.instruction |= INDEX_UP; | |
7623 | if (inst.operands[i].shifted) | |
7624 | { | |
7625 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
7626 | inst.instruction |= SHIFT_ROR << 5; | |
7627 | else | |
7628 | { | |
7629 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
7630 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
7631 | } | |
7632 | } | |
09d92015 | 7633 | } |
c19d1205 | 7634 | else /* immediate offset in inst.reloc */ |
09d92015 | 7635 | { |
5be8be5d DG |
7636 | if (is_pc && !inst.reloc.pc_rel) |
7637 | { | |
7638 | const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0); | |
23a10334 JZ |
7639 | |
7640 | /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt | |
7641 | cannot use PC in addressing. | |
7642 | PC cannot be used in writeback addressing, either. */ | |
7643 | constraint ((is_t || inst.operands[i].writeback), | |
5be8be5d | 7644 | BAD_PC_ADDRESSING); |
23a10334 | 7645 | |
dc5ec521 | 7646 | /* Use of PC in str is deprecated for ARMv7. */ |
23a10334 JZ |
7647 | if (warn_on_deprecated |
7648 | && !is_load | |
7649 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) | |
5c3696f8 | 7650 | as_tsktsk (_("use of PC in this instruction is deprecated")); |
5be8be5d DG |
7651 | } |
7652 | ||
c19d1205 | 7653 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
26d97720 NS |
7654 | { |
7655 | /* Prefer + for zero encoded value. */ | |
7656 | if (!inst.operands[i].negative) | |
7657 | inst.instruction |= INDEX_UP; | |
7658 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
7659 | } | |
09d92015 | 7660 | } |
09d92015 MM |
7661 | } |
7662 | ||
c19d1205 ZW |
7663 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7664 | ARM-format mode 3 load or store instruction. Reject forms that | |
7665 | cannot be used with such instructions. If is_t is true, reject | |
7666 | forms that cannot be used with a T instruction (i.e. not | |
7667 | post-indexed). */ | |
7668 | static void | |
7669 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 7670 | { |
c19d1205 | 7671 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 7672 | { |
c19d1205 ZW |
7673 | inst.error = _("instruction does not accept scaled register index"); |
7674 | return; | |
09d92015 | 7675 | } |
a737bd4d | 7676 | |
c19d1205 | 7677 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 7678 | |
c19d1205 ZW |
7679 | if (inst.operands[i].immisreg) |
7680 | { | |
5be8be5d | 7681 | constraint ((inst.operands[i].imm == REG_PC |
eb9f3f00 | 7682 | || (is_t && inst.operands[i].reg == REG_PC)), |
5be8be5d | 7683 | BAD_PC_ADDRESSING); |
eb9f3f00 JB |
7684 | constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback, |
7685 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
7686 | inst.instruction |= inst.operands[i].imm; |
7687 | if (!inst.operands[i].negative) | |
7688 | inst.instruction |= INDEX_UP; | |
7689 | } | |
7690 | else /* immediate offset in inst.reloc */ | |
7691 | { | |
5be8be5d DG |
7692 | constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel |
7693 | && inst.operands[i].writeback), | |
7694 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
7695 | inst.instruction |= HWOFFSET_IMM; |
7696 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
26d97720 NS |
7697 | { |
7698 | /* Prefer + for zero encoded value. */ | |
7699 | if (!inst.operands[i].negative) | |
7700 | inst.instruction |= INDEX_UP; | |
7701 | ||
7702 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
7703 | } | |
c19d1205 | 7704 | } |
a737bd4d NC |
7705 | } |
7706 | ||
8335d6aa JW |
7707 | /* Write immediate bits [7:0] to the following locations: |
7708 | ||
7709 | |28/24|23 19|18 16|15 4|3 0| | |
7710 | | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| | |
7711 | ||
7712 | This function is used by VMOV/VMVN/VORR/VBIC. */ | |
7713 | ||
7714 | static void | |
7715 | neon_write_immbits (unsigned immbits) | |
7716 | { | |
7717 | inst.instruction |= immbits & 0xf; | |
7718 | inst.instruction |= ((immbits >> 4) & 0x7) << 16; | |
7719 | inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24); | |
7720 | } | |
7721 | ||
7722 | /* Invert low-order SIZE bits of XHI:XLO. */ | |
7723 | ||
7724 | static void | |
7725 | neon_invert_size (unsigned *xlo, unsigned *xhi, int size) | |
7726 | { | |
7727 | unsigned immlo = xlo ? *xlo : 0; | |
7728 | unsigned immhi = xhi ? *xhi : 0; | |
7729 | ||
7730 | switch (size) | |
7731 | { | |
7732 | case 8: | |
7733 | immlo = (~immlo) & 0xff; | |
7734 | break; | |
7735 | ||
7736 | case 16: | |
7737 | immlo = (~immlo) & 0xffff; | |
7738 | break; | |
7739 | ||
7740 | case 64: | |
7741 | immhi = (~immhi) & 0xffffffff; | |
7742 | /* fall through. */ | |
7743 | ||
7744 | case 32: | |
7745 | immlo = (~immlo) & 0xffffffff; | |
7746 | break; | |
7747 | ||
7748 | default: | |
7749 | abort (); | |
7750 | } | |
7751 | ||
7752 | if (xlo) | |
7753 | *xlo = immlo; | |
7754 | ||
7755 | if (xhi) | |
7756 | *xhi = immhi; | |
7757 | } | |
7758 | ||
7759 | /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits | |
7760 | A, B, C, D. */ | |
09d92015 | 7761 | |
c19d1205 | 7762 | static int |
8335d6aa | 7763 | neon_bits_same_in_bytes (unsigned imm) |
09d92015 | 7764 | { |
8335d6aa JW |
7765 | return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) |
7766 | && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) | |
7767 | && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) | |
7768 | && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); | |
7769 | } | |
a737bd4d | 7770 | |
8335d6aa | 7771 | /* For immediate of above form, return 0bABCD. */ |
09d92015 | 7772 | |
8335d6aa JW |
7773 | static unsigned |
7774 | neon_squash_bits (unsigned imm) | |
7775 | { | |
7776 | return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) | |
7777 | | ((imm & 0x01000000) >> 21); | |
7778 | } | |
7779 | ||
7780 | /* Compress quarter-float representation to 0b...000 abcdefgh. */ | |
7781 | ||
7782 | static unsigned | |
7783 | neon_qfloat_bits (unsigned imm) | |
7784 | { | |
7785 | return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); | |
7786 | } | |
7787 | ||
7788 | /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into | |
7789 | the instruction. *OP is passed as the initial value of the op field, and | |
7790 | may be set to a different value depending on the constant (i.e. | |
7791 | "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not | |
7792 | MVN). If the immediate looks like a repeated pattern then also | |
7793 | try smaller element sizes. */ | |
7794 | ||
7795 | static int | |
7796 | neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, | |
7797 | unsigned *immbits, int *op, int size, | |
7798 | enum neon_el_type type) | |
7799 | { | |
7800 | /* Only permit float immediates (including 0.0/-0.0) if the operand type is | |
7801 | float. */ | |
7802 | if (type == NT_float && !float_p) | |
7803 | return FAIL; | |
7804 | ||
7805 | if (type == NT_float && is_quarter_float (immlo) && immhi == 0) | |
09d92015 | 7806 | { |
8335d6aa JW |
7807 | if (size != 32 || *op == 1) |
7808 | return FAIL; | |
7809 | *immbits = neon_qfloat_bits (immlo); | |
7810 | return 0xf; | |
7811 | } | |
7812 | ||
7813 | if (size == 64) | |
7814 | { | |
7815 | if (neon_bits_same_in_bytes (immhi) | |
7816 | && neon_bits_same_in_bytes (immlo)) | |
c19d1205 | 7817 | { |
8335d6aa JW |
7818 | if (*op == 1) |
7819 | return FAIL; | |
7820 | *immbits = (neon_squash_bits (immhi) << 4) | |
7821 | | neon_squash_bits (immlo); | |
7822 | *op = 1; | |
7823 | return 0xe; | |
c19d1205 | 7824 | } |
a737bd4d | 7825 | |
8335d6aa JW |
7826 | if (immhi != immlo) |
7827 | return FAIL; | |
7828 | } | |
a737bd4d | 7829 | |
8335d6aa | 7830 | if (size >= 32) |
09d92015 | 7831 | { |
8335d6aa | 7832 | if (immlo == (immlo & 0x000000ff)) |
c19d1205 | 7833 | { |
8335d6aa JW |
7834 | *immbits = immlo; |
7835 | return 0x0; | |
c19d1205 | 7836 | } |
8335d6aa | 7837 | else if (immlo == (immlo & 0x0000ff00)) |
c19d1205 | 7838 | { |
8335d6aa JW |
7839 | *immbits = immlo >> 8; |
7840 | return 0x2; | |
c19d1205 | 7841 | } |
8335d6aa JW |
7842 | else if (immlo == (immlo & 0x00ff0000)) |
7843 | { | |
7844 | *immbits = immlo >> 16; | |
7845 | return 0x4; | |
7846 | } | |
7847 | else if (immlo == (immlo & 0xff000000)) | |
7848 | { | |
7849 | *immbits = immlo >> 24; | |
7850 | return 0x6; | |
7851 | } | |
7852 | else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) | |
7853 | { | |
7854 | *immbits = (immlo >> 8) & 0xff; | |
7855 | return 0xc; | |
7856 | } | |
7857 | else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) | |
7858 | { | |
7859 | *immbits = (immlo >> 16) & 0xff; | |
7860 | return 0xd; | |
7861 | } | |
7862 | ||
7863 | if ((immlo & 0xffff) != (immlo >> 16)) | |
7864 | return FAIL; | |
7865 | immlo &= 0xffff; | |
09d92015 | 7866 | } |
a737bd4d | 7867 | |
8335d6aa | 7868 | if (size >= 16) |
4962c51a | 7869 | { |
8335d6aa JW |
7870 | if (immlo == (immlo & 0x000000ff)) |
7871 | { | |
7872 | *immbits = immlo; | |
7873 | return 0x8; | |
7874 | } | |
7875 | else if (immlo == (immlo & 0x0000ff00)) | |
7876 | { | |
7877 | *immbits = immlo >> 8; | |
7878 | return 0xa; | |
7879 | } | |
7880 | ||
7881 | if ((immlo & 0xff) != (immlo >> 8)) | |
7882 | return FAIL; | |
7883 | immlo &= 0xff; | |
4962c51a MS |
7884 | } |
7885 | ||
8335d6aa JW |
7886 | if (immlo == (immlo & 0x000000ff)) |
7887 | { | |
7888 | /* Don't allow MVN with 8-bit immediate. */ | |
7889 | if (*op == 1) | |
7890 | return FAIL; | |
7891 | *immbits = immlo; | |
7892 | return 0xe; | |
7893 | } | |
26d97720 | 7894 | |
8335d6aa | 7895 | return FAIL; |
c19d1205 | 7896 | } |
a737bd4d | 7897 | |
5fc177c8 | 7898 | #if defined BFD_HOST_64_BIT |
ba592044 AM |
7899 | /* Returns TRUE if double precision value V may be cast |
7900 | to single precision without loss of accuracy. */ | |
7901 | ||
7902 | static bfd_boolean | |
5fc177c8 | 7903 | is_double_a_single (bfd_int64_t v) |
ba592044 | 7904 | { |
5fc177c8 | 7905 | int exp = (int)((v >> 52) & 0x7FF); |
8fe3f3d6 | 7906 | bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL); |
ba592044 AM |
7907 | |
7908 | return (exp == 0 || exp == 0x7FF | |
7909 | || (exp >= 1023 - 126 && exp <= 1023 + 127)) | |
7910 | && (mantissa & 0x1FFFFFFFl) == 0; | |
7911 | } | |
7912 | ||
3739860c | 7913 | /* Returns a double precision value casted to single precision |
ba592044 AM |
7914 | (ignoring the least significant bits in exponent and mantissa). */ |
7915 | ||
7916 | static int | |
5fc177c8 | 7917 | double_to_single (bfd_int64_t v) |
ba592044 AM |
7918 | { |
7919 | int sign = (int) ((v >> 63) & 1l); | |
5fc177c8 | 7920 | int exp = (int) ((v >> 52) & 0x7FF); |
8fe3f3d6 | 7921 | bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL); |
ba592044 AM |
7922 | |
7923 | if (exp == 0x7FF) | |
7924 | exp = 0xFF; | |
7925 | else | |
7926 | { | |
7927 | exp = exp - 1023 + 127; | |
7928 | if (exp >= 0xFF) | |
7929 | { | |
7930 | /* Infinity. */ | |
7931 | exp = 0x7F; | |
7932 | mantissa = 0; | |
7933 | } | |
7934 | else if (exp < 0) | |
7935 | { | |
7936 | /* No denormalized numbers. */ | |
7937 | exp = 0; | |
7938 | mantissa = 0; | |
7939 | } | |
7940 | } | |
7941 | mantissa >>= 29; | |
7942 | return (sign << 31) | (exp << 23) | mantissa; | |
7943 | } | |
5fc177c8 | 7944 | #endif /* BFD_HOST_64_BIT */ |
ba592044 | 7945 | |
8335d6aa JW |
7946 | enum lit_type |
7947 | { | |
7948 | CONST_THUMB, | |
7949 | CONST_ARM, | |
7950 | CONST_VEC | |
7951 | }; | |
7952 | ||
ba592044 AM |
7953 | static void do_vfp_nsyn_opcode (const char *); |
7954 | ||
c19d1205 ZW |
7955 | /* inst.reloc.exp describes an "=expr" load pseudo-operation. |
7956 | Determine whether it can be performed with a move instruction; if | |
7957 | it can, convert inst.instruction to that move instruction and | |
c921be7d NC |
7958 | return TRUE; if it can't, convert inst.instruction to a literal-pool |
7959 | load and return FALSE. If this is not a valid thing to do in the | |
7960 | current context, set inst.error and return TRUE. | |
a737bd4d | 7961 | |
c19d1205 ZW |
7962 | inst.operands[i] describes the destination register. */ |
7963 | ||
c921be7d | 7964 | static bfd_boolean |
8335d6aa | 7965 | move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3) |
c19d1205 | 7966 | { |
53365c0d | 7967 | unsigned long tbit; |
8335d6aa JW |
7968 | bfd_boolean thumb_p = (t == CONST_THUMB); |
7969 | bfd_boolean arm_p = (t == CONST_ARM); | |
53365c0d PB |
7970 | |
7971 | if (thumb_p) | |
7972 | tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; | |
7973 | else | |
7974 | tbit = LOAD_BIT; | |
7975 | ||
7976 | if ((inst.instruction & tbit) == 0) | |
09d92015 | 7977 | { |
c19d1205 | 7978 | inst.error = _("invalid pseudo operation"); |
c921be7d | 7979 | return TRUE; |
09d92015 | 7980 | } |
ba592044 | 7981 | |
8335d6aa JW |
7982 | if (inst.reloc.exp.X_op != O_constant |
7983 | && inst.reloc.exp.X_op != O_symbol | |
7984 | && inst.reloc.exp.X_op != O_big) | |
09d92015 MM |
7985 | { |
7986 | inst.error = _("constant expression expected"); | |
c921be7d | 7987 | return TRUE; |
09d92015 | 7988 | } |
ba592044 AM |
7989 | |
7990 | if (inst.reloc.exp.X_op == O_constant | |
7991 | || inst.reloc.exp.X_op == O_big) | |
8335d6aa | 7992 | { |
5fc177c8 NC |
7993 | #if defined BFD_HOST_64_BIT |
7994 | bfd_int64_t v; | |
7995 | #else | |
ba592044 | 7996 | offsetT v; |
5fc177c8 | 7997 | #endif |
ba592044 | 7998 | if (inst.reloc.exp.X_op == O_big) |
8335d6aa | 7999 | { |
ba592044 AM |
8000 | LITTLENUM_TYPE w[X_PRECISION]; |
8001 | LITTLENUM_TYPE * l; | |
8002 | ||
8003 | if (inst.reloc.exp.X_add_number == -1) | |
8335d6aa | 8004 | { |
ba592044 AM |
8005 | gen_to_words (w, X_PRECISION, E_PRECISION); |
8006 | l = w; | |
8007 | /* FIXME: Should we check words w[2..5] ? */ | |
8335d6aa | 8008 | } |
ba592044 AM |
8009 | else |
8010 | l = generic_bignum; | |
3739860c | 8011 | |
5fc177c8 NC |
8012 | #if defined BFD_HOST_64_BIT |
8013 | v = | |
8014 | ((((((((bfd_int64_t) l[3] & LITTLENUM_MASK) | |
8015 | << LITTLENUM_NUMBER_OF_BITS) | |
8016 | | ((bfd_int64_t) l[2] & LITTLENUM_MASK)) | |
8017 | << LITTLENUM_NUMBER_OF_BITS) | |
8018 | | ((bfd_int64_t) l[1] & LITTLENUM_MASK)) | |
8019 | << LITTLENUM_NUMBER_OF_BITS) | |
8020 | | ((bfd_int64_t) l[0] & LITTLENUM_MASK)); | |
8021 | #else | |
ba592044 AM |
8022 | v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS) |
8023 | | (l[0] & LITTLENUM_MASK); | |
5fc177c8 | 8024 | #endif |
8335d6aa | 8025 | } |
ba592044 AM |
8026 | else |
8027 | v = inst.reloc.exp.X_add_number; | |
8028 | ||
8029 | if (!inst.operands[i].issingle) | |
8335d6aa | 8030 | { |
12569877 | 8031 | if (thumb_p) |
8335d6aa | 8032 | { |
53445554 TP |
8033 | /* LDR should not use lead in a flag-setting instruction being |
8034 | chosen so we do not check whether movs can be used. */ | |
12569877 | 8035 | |
53445554 | 8036 | if ((ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2) |
ff8646ee | 8037 | || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)) |
53445554 TP |
8038 | && inst.operands[i].reg != 13 |
8039 | && inst.operands[i].reg != 15) | |
12569877 | 8040 | { |
fc289b0a TP |
8041 | /* Check if on thumb2 it can be done with a mov.w, mvn or |
8042 | movw instruction. */ | |
12569877 AM |
8043 | unsigned int newimm; |
8044 | bfd_boolean isNegated; | |
8045 | ||
8046 | newimm = encode_thumb32_immediate (v); | |
8047 | if (newimm != (unsigned int) FAIL) | |
8048 | isNegated = FALSE; | |
8049 | else | |
8050 | { | |
582cfe03 | 8051 | newimm = encode_thumb32_immediate (~v); |
12569877 AM |
8052 | if (newimm != (unsigned int) FAIL) |
8053 | isNegated = TRUE; | |
8054 | } | |
8055 | ||
fc289b0a TP |
8056 | /* The number can be loaded with a mov.w or mvn |
8057 | instruction. */ | |
ff8646ee TP |
8058 | if (newimm != (unsigned int) FAIL |
8059 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)) | |
12569877 | 8060 | { |
fc289b0a | 8061 | inst.instruction = (0xf04f0000 /* MOV.W. */ |
582cfe03 | 8062 | | (inst.operands[i].reg << 8)); |
fc289b0a | 8063 | /* Change to MOVN. */ |
582cfe03 | 8064 | inst.instruction |= (isNegated ? 0x200000 : 0); |
12569877 AM |
8065 | inst.instruction |= (newimm & 0x800) << 15; |
8066 | inst.instruction |= (newimm & 0x700) << 4; | |
8067 | inst.instruction |= (newimm & 0x0ff); | |
8068 | return TRUE; | |
8069 | } | |
fc289b0a | 8070 | /* The number can be loaded with a movw instruction. */ |
ff8646ee TP |
8071 | else if ((v & ~0xFFFF) == 0 |
8072 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)) | |
3739860c | 8073 | { |
582cfe03 | 8074 | int imm = v & 0xFFFF; |
12569877 | 8075 | |
582cfe03 | 8076 | inst.instruction = 0xf2400000; /* MOVW. */ |
12569877 AM |
8077 | inst.instruction |= (inst.operands[i].reg << 8); |
8078 | inst.instruction |= (imm & 0xf000) << 4; | |
8079 | inst.instruction |= (imm & 0x0800) << 15; | |
8080 | inst.instruction |= (imm & 0x0700) << 4; | |
8081 | inst.instruction |= (imm & 0x00ff); | |
8082 | return TRUE; | |
8083 | } | |
8084 | } | |
8335d6aa | 8085 | } |
12569877 | 8086 | else if (arm_p) |
ba592044 AM |
8087 | { |
8088 | int value = encode_arm_immediate (v); | |
12569877 | 8089 | |
ba592044 AM |
8090 | if (value != FAIL) |
8091 | { | |
8092 | /* This can be done with a mov instruction. */ | |
8093 | inst.instruction &= LITERAL_MASK; | |
8094 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
8095 | inst.instruction |= value & 0xfff; | |
8096 | return TRUE; | |
8097 | } | |
8335d6aa | 8098 | |
ba592044 AM |
8099 | value = encode_arm_immediate (~ v); |
8100 | if (value != FAIL) | |
8101 | { | |
8102 | /* This can be done with a mvn instruction. */ | |
8103 | inst.instruction &= LITERAL_MASK; | |
8104 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
8105 | inst.instruction |= value & 0xfff; | |
8106 | return TRUE; | |
8107 | } | |
8108 | } | |
934c2632 | 8109 | else if (t == CONST_VEC && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) |
8335d6aa | 8110 | { |
ba592044 AM |
8111 | int op = 0; |
8112 | unsigned immbits = 0; | |
8113 | unsigned immlo = inst.operands[1].imm; | |
8114 | unsigned immhi = inst.operands[1].regisimm | |
8115 | ? inst.operands[1].reg | |
8116 | : inst.reloc.exp.X_unsigned | |
8117 | ? 0 | |
8118 | : ((bfd_int64_t)((int) immlo)) >> 32; | |
8119 | int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits, | |
8120 | &op, 64, NT_invtype); | |
8121 | ||
8122 | if (cmode == FAIL) | |
8123 | { | |
8124 | neon_invert_size (&immlo, &immhi, 64); | |
8125 | op = !op; | |
8126 | cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits, | |
8127 | &op, 64, NT_invtype); | |
8128 | } | |
8129 | ||
8130 | if (cmode != FAIL) | |
8131 | { | |
8132 | inst.instruction = (inst.instruction & VLDR_VMOV_SAME) | |
8133 | | (1 << 23) | |
8134 | | (cmode << 8) | |
8135 | | (op << 5) | |
8136 | | (1 << 4); | |
8137 | ||
8138 | /* Fill other bits in vmov encoding for both thumb and arm. */ | |
8139 | if (thumb_mode) | |
eff0bc54 | 8140 | inst.instruction |= (0x7U << 29) | (0xF << 24); |
ba592044 | 8141 | else |
eff0bc54 | 8142 | inst.instruction |= (0xFU << 28) | (0x1 << 25); |
ba592044 AM |
8143 | neon_write_immbits (immbits); |
8144 | return TRUE; | |
8145 | } | |
8335d6aa JW |
8146 | } |
8147 | } | |
8335d6aa | 8148 | |
ba592044 AM |
8149 | if (t == CONST_VEC) |
8150 | { | |
8151 | /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */ | |
8152 | if (inst.operands[i].issingle | |
8153 | && is_quarter_float (inst.operands[1].imm) | |
8154 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd)) | |
8335d6aa | 8155 | { |
ba592044 AM |
8156 | inst.operands[1].imm = |
8157 | neon_qfloat_bits (v); | |
8158 | do_vfp_nsyn_opcode ("fconsts"); | |
8159 | return TRUE; | |
8335d6aa | 8160 | } |
5fc177c8 NC |
8161 | |
8162 | /* If our host does not support a 64-bit type then we cannot perform | |
8163 | the following optimization. This mean that there will be a | |
8164 | discrepancy between the output produced by an assembler built for | |
8165 | a 32-bit-only host and the output produced from a 64-bit host, but | |
8166 | this cannot be helped. */ | |
8167 | #if defined BFD_HOST_64_BIT | |
ba592044 AM |
8168 | else if (!inst.operands[1].issingle |
8169 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) | |
8335d6aa | 8170 | { |
ba592044 AM |
8171 | if (is_double_a_single (v) |
8172 | && is_quarter_float (double_to_single (v))) | |
8173 | { | |
8174 | inst.operands[1].imm = | |
8175 | neon_qfloat_bits (double_to_single (v)); | |
8176 | do_vfp_nsyn_opcode ("fconstd"); | |
8177 | return TRUE; | |
8178 | } | |
8335d6aa | 8179 | } |
5fc177c8 | 8180 | #endif |
8335d6aa JW |
8181 | } |
8182 | } | |
8183 | ||
8184 | if (add_to_lit_pool ((!inst.operands[i].isvec | |
8185 | || inst.operands[i].issingle) ? 4 : 8) == FAIL) | |
8186 | return TRUE; | |
8187 | ||
8188 | inst.operands[1].reg = REG_PC; | |
8189 | inst.operands[1].isreg = 1; | |
8190 | inst.operands[1].preind = 1; | |
8191 | inst.reloc.pc_rel = 1; | |
8192 | inst.reloc.type = (thumb_p | |
8193 | ? BFD_RELOC_ARM_THUMB_OFFSET | |
8194 | : (mode_3 | |
8195 | ? BFD_RELOC_ARM_HWLITERAL | |
8196 | : BFD_RELOC_ARM_LITERAL)); | |
8197 | return FALSE; | |
8198 | } | |
8199 | ||
8200 | /* inst.operands[i] was set up by parse_address. Encode it into an | |
8201 | ARM-format instruction. Reject all forms which cannot be encoded | |
8202 | into a coprocessor load/store instruction. If wb_ok is false, | |
8203 | reject use of writeback; if unind_ok is false, reject use of | |
8204 | unindexed addressing. If reloc_override is not 0, use it instead | |
8205 | of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one | |
8206 | (in which case it is preserved). */ | |
8207 | ||
8208 | static int | |
8209 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
8210 | { | |
8211 | if (!inst.operands[i].isreg) | |
8212 | { | |
99b2a2dd NC |
8213 | /* PR 18256 */ |
8214 | if (! inst.operands[0].isvec) | |
8215 | { | |
8216 | inst.error = _("invalid co-processor operand"); | |
8217 | return FAIL; | |
8218 | } | |
8335d6aa JW |
8219 | if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE)) |
8220 | return SUCCESS; | |
8221 | } | |
8222 | ||
8223 | inst.instruction |= inst.operands[i].reg << 16; | |
8224 | ||
8225 | gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); | |
8226 | ||
8227 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ | |
8228 | { | |
8229 | gas_assert (!inst.operands[i].writeback); | |
8230 | if (!unind_ok) | |
8231 | { | |
8232 | inst.error = _("instruction does not support unindexed addressing"); | |
8233 | return FAIL; | |
8234 | } | |
8235 | inst.instruction |= inst.operands[i].imm; | |
8236 | inst.instruction |= INDEX_UP; | |
8237 | return SUCCESS; | |
8238 | } | |
8239 | ||
8240 | if (inst.operands[i].preind) | |
8241 | inst.instruction |= PRE_INDEX; | |
8242 | ||
8243 | if (inst.operands[i].writeback) | |
09d92015 | 8244 | { |
8335d6aa | 8245 | if (inst.operands[i].reg == REG_PC) |
c19d1205 | 8246 | { |
8335d6aa JW |
8247 | inst.error = _("pc may not be used with write-back"); |
8248 | return FAIL; | |
c19d1205 | 8249 | } |
8335d6aa | 8250 | if (!wb_ok) |
c19d1205 | 8251 | { |
8335d6aa JW |
8252 | inst.error = _("instruction does not support writeback"); |
8253 | return FAIL; | |
c19d1205 | 8254 | } |
8335d6aa | 8255 | inst.instruction |= WRITE_BACK; |
09d92015 MM |
8256 | } |
8257 | ||
8335d6aa JW |
8258 | if (reloc_override) |
8259 | inst.reloc.type = (bfd_reloc_code_real_type) reloc_override; | |
8260 | else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC | |
8261 | || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) | |
8262 | && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) | |
c19d1205 | 8263 | { |
8335d6aa JW |
8264 | if (thumb_mode) |
8265 | inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; | |
8266 | else | |
8267 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; | |
c19d1205 | 8268 | } |
8335d6aa JW |
8269 | |
8270 | /* Prefer + for zero encoded value. */ | |
8271 | if (!inst.operands[i].negative) | |
8272 | inst.instruction |= INDEX_UP; | |
8273 | ||
8274 | return SUCCESS; | |
09d92015 MM |
8275 | } |
8276 | ||
5f4273c7 | 8277 | /* Functions for instruction encoding, sorted by sub-architecture. |
c19d1205 ZW |
8278 | First some generics; their names are taken from the conventional |
8279 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 8280 | |
a737bd4d | 8281 | static void |
c19d1205 | 8282 | do_noargs (void) |
09d92015 | 8283 | { |
c19d1205 | 8284 | } |
a737bd4d | 8285 | |
c19d1205 ZW |
8286 | static void |
8287 | do_rd (void) | |
8288 | { | |
8289 | inst.instruction |= inst.operands[0].reg << 12; | |
8290 | } | |
a737bd4d | 8291 | |
16a1fa25 TP |
8292 | static void |
8293 | do_rn (void) | |
8294 | { | |
8295 | inst.instruction |= inst.operands[0].reg << 16; | |
8296 | } | |
8297 | ||
c19d1205 ZW |
8298 | static void |
8299 | do_rd_rm (void) | |
8300 | { | |
8301 | inst.instruction |= inst.operands[0].reg << 12; | |
8302 | inst.instruction |= inst.operands[1].reg; | |
8303 | } | |
09d92015 | 8304 | |
9eb6c0f1 MGD |
8305 | static void |
8306 | do_rm_rn (void) | |
8307 | { | |
8308 | inst.instruction |= inst.operands[0].reg; | |
8309 | inst.instruction |= inst.operands[1].reg << 16; | |
8310 | } | |
8311 | ||
c19d1205 ZW |
8312 | static void |
8313 | do_rd_rn (void) | |
8314 | { | |
8315 | inst.instruction |= inst.operands[0].reg << 12; | |
8316 | inst.instruction |= inst.operands[1].reg << 16; | |
8317 | } | |
a737bd4d | 8318 | |
c19d1205 ZW |
8319 | static void |
8320 | do_rn_rd (void) | |
8321 | { | |
8322 | inst.instruction |= inst.operands[0].reg << 16; | |
8323 | inst.instruction |= inst.operands[1].reg << 12; | |
8324 | } | |
09d92015 | 8325 | |
4ed7ed8d TP |
8326 | static void |
8327 | do_tt (void) | |
8328 | { | |
8329 | inst.instruction |= inst.operands[0].reg << 8; | |
8330 | inst.instruction |= inst.operands[1].reg << 16; | |
8331 | } | |
8332 | ||
59d09be6 MGD |
8333 | static bfd_boolean |
8334 | check_obsolete (const arm_feature_set *feature, const char *msg) | |
8335 | { | |
8336 | if (ARM_CPU_IS_ANY (cpu_variant)) | |
8337 | { | |
5c3696f8 | 8338 | as_tsktsk ("%s", msg); |
59d09be6 MGD |
8339 | return TRUE; |
8340 | } | |
8341 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature)) | |
8342 | { | |
8343 | as_bad ("%s", msg); | |
8344 | return TRUE; | |
8345 | } | |
8346 | ||
8347 | return FALSE; | |
8348 | } | |
8349 | ||
c19d1205 ZW |
8350 | static void |
8351 | do_rd_rm_rn (void) | |
8352 | { | |
9a64e435 | 8353 | unsigned Rn = inst.operands[2].reg; |
708587a4 | 8354 | /* Enforce restrictions on SWP instruction. */ |
9a64e435 | 8355 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) |
56adecf4 DG |
8356 | { |
8357 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
8358 | _("Rn must not overlap other operands")); | |
8359 | ||
59d09be6 MGD |
8360 | /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7. |
8361 | */ | |
8362 | if (!check_obsolete (&arm_ext_v8, | |
8363 | _("swp{b} use is obsoleted for ARMv8 and later")) | |
8364 | && warn_on_deprecated | |
8365 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6)) | |
5c3696f8 | 8366 | as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7")); |
56adecf4 | 8367 | } |
59d09be6 | 8368 | |
c19d1205 ZW |
8369 | inst.instruction |= inst.operands[0].reg << 12; |
8370 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 8371 | inst.instruction |= Rn << 16; |
c19d1205 | 8372 | } |
09d92015 | 8373 | |
c19d1205 ZW |
8374 | static void |
8375 | do_rd_rn_rm (void) | |
8376 | { | |
8377 | inst.instruction |= inst.operands[0].reg << 12; | |
8378 | inst.instruction |= inst.operands[1].reg << 16; | |
8379 | inst.instruction |= inst.operands[2].reg; | |
8380 | } | |
a737bd4d | 8381 | |
c19d1205 ZW |
8382 | static void |
8383 | do_rm_rd_rn (void) | |
8384 | { | |
5be8be5d DG |
8385 | constraint ((inst.operands[2].reg == REG_PC), BAD_PC); |
8386 | constraint (((inst.reloc.exp.X_op != O_constant | |
8387 | && inst.reloc.exp.X_op != O_illegal) | |
8388 | || inst.reloc.exp.X_add_number != 0), | |
8389 | BAD_ADDR_MODE); | |
c19d1205 ZW |
8390 | inst.instruction |= inst.operands[0].reg; |
8391 | inst.instruction |= inst.operands[1].reg << 12; | |
8392 | inst.instruction |= inst.operands[2].reg << 16; | |
8393 | } | |
09d92015 | 8394 | |
c19d1205 ZW |
8395 | static void |
8396 | do_imm0 (void) | |
8397 | { | |
8398 | inst.instruction |= inst.operands[0].imm; | |
8399 | } | |
09d92015 | 8400 | |
c19d1205 ZW |
8401 | static void |
8402 | do_rd_cpaddr (void) | |
8403 | { | |
8404 | inst.instruction |= inst.operands[0].reg << 12; | |
8405 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 8406 | } |
a737bd4d | 8407 | |
c19d1205 ZW |
8408 | /* ARM instructions, in alphabetical order by function name (except |
8409 | that wrapper functions appear immediately after the function they | |
8410 | wrap). */ | |
09d92015 | 8411 | |
c19d1205 ZW |
8412 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
8413 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
8414 | |
8415 | static void | |
c19d1205 | 8416 | do_adr (void) |
09d92015 | 8417 | { |
c19d1205 | 8418 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 8419 | |
c19d1205 ZW |
8420 | /* Frag hacking will turn this into a sub instruction if the offset turns |
8421 | out to be negative. */ | |
8422 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
c19d1205 | 8423 | inst.reloc.pc_rel = 1; |
2fc8bdac | 8424 | inst.reloc.exp.X_add_number -= 8; |
52a86f84 | 8425 | |
fc6141f0 NC |
8426 | if (support_interwork |
8427 | && inst.reloc.exp.X_op == O_symbol | |
52a86f84 NC |
8428 | && inst.reloc.exp.X_add_symbol != NULL |
8429 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
8430 | && THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
fc6141f0 | 8431 | inst.reloc.exp.X_add_number |= 1; |
c19d1205 | 8432 | } |
b99bd4ef | 8433 | |
c19d1205 ZW |
8434 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
8435 | into a relative address of the form: | |
8436 | add rd, pc, #low(label-.-8)" | |
8437 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 8438 | |
c19d1205 ZW |
8439 | static void |
8440 | do_adrl (void) | |
8441 | { | |
8442 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 8443 | |
c19d1205 ZW |
8444 | /* Frag hacking will turn this into a sub instruction if the offset turns |
8445 | out to be negative. */ | |
8446 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
c19d1205 ZW |
8447 | inst.reloc.pc_rel = 1; |
8448 | inst.size = INSN_SIZE * 2; | |
2fc8bdac | 8449 | inst.reloc.exp.X_add_number -= 8; |
52a86f84 | 8450 | |
fc6141f0 NC |
8451 | if (support_interwork |
8452 | && inst.reloc.exp.X_op == O_symbol | |
52a86f84 NC |
8453 | && inst.reloc.exp.X_add_symbol != NULL |
8454 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
8455 | && THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
fc6141f0 | 8456 | inst.reloc.exp.X_add_number |= 1; |
b99bd4ef NC |
8457 | } |
8458 | ||
b99bd4ef | 8459 | static void |
c19d1205 | 8460 | do_arit (void) |
b99bd4ef | 8461 | { |
a9f02af8 MG |
8462 | constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC |
8463 | && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC , | |
8464 | THUMB1_RELOC_ONLY); | |
c19d1205 ZW |
8465 | if (!inst.operands[1].present) |
8466 | inst.operands[1].reg = inst.operands[0].reg; | |
8467 | inst.instruction |= inst.operands[0].reg << 12; | |
8468 | inst.instruction |= inst.operands[1].reg << 16; | |
8469 | encode_arm_shifter_operand (2); | |
8470 | } | |
b99bd4ef | 8471 | |
62b3e311 PB |
8472 | static void |
8473 | do_barrier (void) | |
8474 | { | |
8475 | if (inst.operands[0].present) | |
ccb84d65 | 8476 | inst.instruction |= inst.operands[0].imm; |
62b3e311 PB |
8477 | else |
8478 | inst.instruction |= 0xf; | |
8479 | } | |
8480 | ||
c19d1205 ZW |
8481 | static void |
8482 | do_bfc (void) | |
8483 | { | |
8484 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
8485 | constraint (msb > 32, _("bit-field extends past end of register")); | |
8486 | /* The instruction encoding stores the LSB and MSB, | |
8487 | not the LSB and width. */ | |
8488 | inst.instruction |= inst.operands[0].reg << 12; | |
8489 | inst.instruction |= inst.operands[1].imm << 7; | |
8490 | inst.instruction |= (msb - 1) << 16; | |
8491 | } | |
b99bd4ef | 8492 | |
c19d1205 ZW |
8493 | static void |
8494 | do_bfi (void) | |
8495 | { | |
8496 | unsigned int msb; | |
b99bd4ef | 8497 | |
c19d1205 ZW |
8498 | /* #0 in second position is alternative syntax for bfc, which is |
8499 | the same instruction but with REG_PC in the Rm field. */ | |
8500 | if (!inst.operands[1].isreg) | |
8501 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 8502 | |
c19d1205 ZW |
8503 | msb = inst.operands[2].imm + inst.operands[3].imm; |
8504 | constraint (msb > 32, _("bit-field extends past end of register")); | |
8505 | /* The instruction encoding stores the LSB and MSB, | |
8506 | not the LSB and width. */ | |
8507 | inst.instruction |= inst.operands[0].reg << 12; | |
8508 | inst.instruction |= inst.operands[1].reg; | |
8509 | inst.instruction |= inst.operands[2].imm << 7; | |
8510 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
8511 | } |
8512 | ||
b99bd4ef | 8513 | static void |
c19d1205 | 8514 | do_bfx (void) |
b99bd4ef | 8515 | { |
c19d1205 ZW |
8516 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
8517 | _("bit-field extends past end of register")); | |
8518 | inst.instruction |= inst.operands[0].reg << 12; | |
8519 | inst.instruction |= inst.operands[1].reg; | |
8520 | inst.instruction |= inst.operands[2].imm << 7; | |
8521 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
8522 | } | |
09d92015 | 8523 | |
c19d1205 ZW |
8524 | /* ARM V5 breakpoint instruction (argument parse) |
8525 | BKPT <16 bit unsigned immediate> | |
8526 | Instruction is not conditional. | |
8527 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
8528 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 8529 | |
c19d1205 ZW |
8530 | static void |
8531 | do_bkpt (void) | |
8532 | { | |
8533 | /* Top 12 of 16 bits to bits 19:8. */ | |
8534 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 8535 | |
c19d1205 ZW |
8536 | /* Bottom 4 of 16 bits to bits 3:0. */ |
8537 | inst.instruction |= inst.operands[0].imm & 0xf; | |
8538 | } | |
09d92015 | 8539 | |
c19d1205 ZW |
8540 | static void |
8541 | encode_branch (int default_reloc) | |
8542 | { | |
8543 | if (inst.operands[0].hasreloc) | |
8544 | { | |
0855e32b NS |
8545 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32 |
8546 | && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL, | |
8547 | _("the only valid suffixes here are '(plt)' and '(tlscall)'")); | |
8548 | inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32 | |
8549 | ? BFD_RELOC_ARM_PLT32 | |
8550 | : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL; | |
c19d1205 | 8551 | } |
b99bd4ef | 8552 | else |
9ae92b05 | 8553 | inst.reloc.type = (bfd_reloc_code_real_type) default_reloc; |
2fc8bdac | 8554 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
8555 | } |
8556 | ||
b99bd4ef | 8557 | static void |
c19d1205 | 8558 | do_branch (void) |
b99bd4ef | 8559 | { |
39b41c9c PB |
8560 | #ifdef OBJ_ELF |
8561 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
8562 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
8563 | else | |
8564 | #endif | |
8565 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
8566 | } | |
8567 | ||
8568 | static void | |
8569 | do_bl (void) | |
8570 | { | |
8571 | #ifdef OBJ_ELF | |
8572 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
8573 | { | |
8574 | if (inst.cond == COND_ALWAYS) | |
8575 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
8576 | else | |
8577 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
8578 | } | |
8579 | else | |
8580 | #endif | |
8581 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
c19d1205 | 8582 | } |
b99bd4ef | 8583 | |
c19d1205 ZW |
8584 | /* ARM V5 branch-link-exchange instruction (argument parse) |
8585 | BLX <target_addr> ie BLX(1) | |
8586 | BLX{<condition>} <Rm> ie BLX(2) | |
8587 | Unfortunately, there are two different opcodes for this mnemonic. | |
8588 | So, the insns[].value is not used, and the code here zaps values | |
8589 | into inst.instruction. | |
8590 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 8591 | |
c19d1205 ZW |
8592 | static void |
8593 | do_blx (void) | |
8594 | { | |
8595 | if (inst.operands[0].isreg) | |
b99bd4ef | 8596 | { |
c19d1205 ZW |
8597 | /* Arg is a register; the opcode provided by insns[] is correct. |
8598 | It is not illegal to do "blx pc", just useless. */ | |
8599 | if (inst.operands[0].reg == REG_PC) | |
8600 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 8601 | |
c19d1205 ZW |
8602 | inst.instruction |= inst.operands[0].reg; |
8603 | } | |
8604 | else | |
b99bd4ef | 8605 | { |
c19d1205 | 8606 | /* Arg is an address; this instruction cannot be executed |
267bf995 RR |
8607 | conditionally, and the opcode must be adjusted. |
8608 | We retain the BFD_RELOC_ARM_PCREL_BLX till the very end | |
8609 | where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */ | |
c19d1205 | 8610 | constraint (inst.cond != COND_ALWAYS, BAD_COND); |
2fc8bdac | 8611 | inst.instruction = 0xfa000000; |
267bf995 | 8612 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); |
b99bd4ef | 8613 | } |
c19d1205 ZW |
8614 | } |
8615 | ||
8616 | static void | |
8617 | do_bx (void) | |
8618 | { | |
845b51d6 PB |
8619 | bfd_boolean want_reloc; |
8620 | ||
c19d1205 ZW |
8621 | if (inst.operands[0].reg == REG_PC) |
8622 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 8623 | |
c19d1205 | 8624 | inst.instruction |= inst.operands[0].reg; |
845b51d6 PB |
8625 | /* Output R_ARM_V4BX relocations if is an EABI object that looks like |
8626 | it is for ARMv4t or earlier. */ | |
8627 | want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5); | |
4d354d8b TP |
8628 | if (!ARM_FEATURE_ZERO (selected_object_arch) |
8629 | && !ARM_CPU_HAS_FEATURE (selected_object_arch, arm_ext_v5)) | |
845b51d6 PB |
8630 | want_reloc = TRUE; |
8631 | ||
5ad34203 | 8632 | #ifdef OBJ_ELF |
845b51d6 | 8633 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
5ad34203 | 8634 | #endif |
584206db | 8635 | want_reloc = FALSE; |
845b51d6 PB |
8636 | |
8637 | if (want_reloc) | |
8638 | inst.reloc.type = BFD_RELOC_ARM_V4BX; | |
09d92015 MM |
8639 | } |
8640 | ||
c19d1205 ZW |
8641 | |
8642 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
8643 | |
8644 | static void | |
c19d1205 | 8645 | do_bxj (void) |
a737bd4d | 8646 | { |
c19d1205 ZW |
8647 | if (inst.operands[0].reg == REG_PC) |
8648 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
8649 | ||
8650 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
8651 | } |
8652 | ||
c19d1205 ZW |
8653 | /* Co-processor data operation: |
8654 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
8655 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
8656 | static void | |
8657 | do_cdp (void) | |
8658 | { | |
8659 | inst.instruction |= inst.operands[0].reg << 8; | |
8660 | inst.instruction |= inst.operands[1].imm << 20; | |
8661 | inst.instruction |= inst.operands[2].reg << 12; | |
8662 | inst.instruction |= inst.operands[3].reg << 16; | |
8663 | inst.instruction |= inst.operands[4].reg; | |
8664 | inst.instruction |= inst.operands[5].imm << 5; | |
8665 | } | |
a737bd4d NC |
8666 | |
8667 | static void | |
c19d1205 | 8668 | do_cmp (void) |
a737bd4d | 8669 | { |
c19d1205 ZW |
8670 | inst.instruction |= inst.operands[0].reg << 16; |
8671 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
8672 | } |
8673 | ||
c19d1205 ZW |
8674 | /* Transfer between coprocessor and ARM registers. |
8675 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
8676 | MRC2 | |
8677 | MCR{cond} | |
8678 | MCR2 | |
8679 | ||
8680 | No special properties. */ | |
09d92015 | 8681 | |
dcbd0d71 MGD |
8682 | struct deprecated_coproc_regs_s |
8683 | { | |
8684 | unsigned cp; | |
8685 | int opc1; | |
8686 | unsigned crn; | |
8687 | unsigned crm; | |
8688 | int opc2; | |
8689 | arm_feature_set deprecated; | |
8690 | arm_feature_set obsoleted; | |
8691 | const char *dep_msg; | |
8692 | const char *obs_msg; | |
8693 | }; | |
8694 | ||
8695 | #define DEPR_ACCESS_V8 \ | |
8696 | N_("This coprocessor register access is deprecated in ARMv8") | |
8697 | ||
8698 | /* Table of all deprecated coprocessor registers. */ | |
8699 | static struct deprecated_coproc_regs_s deprecated_coproc_regs[] = | |
8700 | { | |
8701 | {15, 0, 7, 10, 5, /* CP15DMB. */ | |
823d2571 | 8702 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
8703 | DEPR_ACCESS_V8, NULL}, |
8704 | {15, 0, 7, 10, 4, /* CP15DSB. */ | |
823d2571 | 8705 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
8706 | DEPR_ACCESS_V8, NULL}, |
8707 | {15, 0, 7, 5, 4, /* CP15ISB. */ | |
823d2571 | 8708 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
8709 | DEPR_ACCESS_V8, NULL}, |
8710 | {14, 6, 1, 0, 0, /* TEEHBR. */ | |
823d2571 | 8711 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
8712 | DEPR_ACCESS_V8, NULL}, |
8713 | {14, 6, 0, 0, 0, /* TEECR. */ | |
823d2571 | 8714 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
8715 | DEPR_ACCESS_V8, NULL}, |
8716 | }; | |
8717 | ||
8718 | #undef DEPR_ACCESS_V8 | |
8719 | ||
8720 | static const size_t deprecated_coproc_reg_count = | |
8721 | sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]); | |
8722 | ||
09d92015 | 8723 | static void |
c19d1205 | 8724 | do_co_reg (void) |
09d92015 | 8725 | { |
fdfde340 | 8726 | unsigned Rd; |
dcbd0d71 | 8727 | size_t i; |
fdfde340 JM |
8728 | |
8729 | Rd = inst.operands[2].reg; | |
8730 | if (thumb_mode) | |
8731 | { | |
8732 | if (inst.instruction == 0xee000010 | |
8733 | || inst.instruction == 0xfe000010) | |
8734 | /* MCR, MCR2 */ | |
8735 | reject_bad_reg (Rd); | |
5c8ed6a4 | 8736 | else if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
fdfde340 JM |
8737 | /* MRC, MRC2 */ |
8738 | constraint (Rd == REG_SP, BAD_SP); | |
8739 | } | |
8740 | else | |
8741 | { | |
8742 | /* MCR */ | |
8743 | if (inst.instruction == 0xe000010) | |
8744 | constraint (Rd == REG_PC, BAD_PC); | |
8745 | } | |
8746 | ||
dcbd0d71 MGD |
8747 | for (i = 0; i < deprecated_coproc_reg_count; ++i) |
8748 | { | |
8749 | const struct deprecated_coproc_regs_s *r = | |
8750 | deprecated_coproc_regs + i; | |
8751 | ||
8752 | if (inst.operands[0].reg == r->cp | |
8753 | && inst.operands[1].imm == r->opc1 | |
8754 | && inst.operands[3].reg == r->crn | |
8755 | && inst.operands[4].reg == r->crm | |
8756 | && inst.operands[5].imm == r->opc2) | |
8757 | { | |
b10bf8c5 | 8758 | if (! ARM_CPU_IS_ANY (cpu_variant) |
477330fc | 8759 | && warn_on_deprecated |
dcbd0d71 | 8760 | && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated)) |
5c3696f8 | 8761 | as_tsktsk ("%s", r->dep_msg); |
dcbd0d71 MGD |
8762 | } |
8763 | } | |
fdfde340 | 8764 | |
c19d1205 ZW |
8765 | inst.instruction |= inst.operands[0].reg << 8; |
8766 | inst.instruction |= inst.operands[1].imm << 21; | |
fdfde340 | 8767 | inst.instruction |= Rd << 12; |
c19d1205 ZW |
8768 | inst.instruction |= inst.operands[3].reg << 16; |
8769 | inst.instruction |= inst.operands[4].reg; | |
8770 | inst.instruction |= inst.operands[5].imm << 5; | |
8771 | } | |
09d92015 | 8772 | |
c19d1205 ZW |
8773 | /* Transfer between coprocessor register and pair of ARM registers. |
8774 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
8775 | MCRR2 | |
8776 | MRRC{cond} | |
8777 | MRRC2 | |
b99bd4ef | 8778 | |
c19d1205 | 8779 | Two XScale instructions are special cases of these: |
09d92015 | 8780 | |
c19d1205 ZW |
8781 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
8782 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 8783 | |
5f4273c7 | 8784 | Result unpredictable if Rd or Rn is R15. */ |
a737bd4d | 8785 | |
c19d1205 ZW |
8786 | static void |
8787 | do_co_reg2c (void) | |
8788 | { | |
fdfde340 JM |
8789 | unsigned Rd, Rn; |
8790 | ||
8791 | Rd = inst.operands[2].reg; | |
8792 | Rn = inst.operands[3].reg; | |
8793 | ||
8794 | if (thumb_mode) | |
8795 | { | |
8796 | reject_bad_reg (Rd); | |
8797 | reject_bad_reg (Rn); | |
8798 | } | |
8799 | else | |
8800 | { | |
8801 | constraint (Rd == REG_PC, BAD_PC); | |
8802 | constraint (Rn == REG_PC, BAD_PC); | |
8803 | } | |
8804 | ||
873f10f0 TC |
8805 | /* Only check the MRRC{2} variants. */ |
8806 | if ((inst.instruction & 0x0FF00000) == 0x0C500000) | |
8807 | { | |
8808 | /* If Rd == Rn, error that the operation is | |
8809 | unpredictable (example MRRC p3,#1,r1,r1,c4). */ | |
8810 | constraint (Rd == Rn, BAD_OVERLAP); | |
8811 | } | |
8812 | ||
c19d1205 ZW |
8813 | inst.instruction |= inst.operands[0].reg << 8; |
8814 | inst.instruction |= inst.operands[1].imm << 4; | |
fdfde340 JM |
8815 | inst.instruction |= Rd << 12; |
8816 | inst.instruction |= Rn << 16; | |
c19d1205 | 8817 | inst.instruction |= inst.operands[4].reg; |
b99bd4ef NC |
8818 | } |
8819 | ||
c19d1205 ZW |
8820 | static void |
8821 | do_cpsi (void) | |
8822 | { | |
8823 | inst.instruction |= inst.operands[0].imm << 6; | |
a028a6f5 PB |
8824 | if (inst.operands[1].present) |
8825 | { | |
8826 | inst.instruction |= CPSI_MMOD; | |
8827 | inst.instruction |= inst.operands[1].imm; | |
8828 | } | |
c19d1205 | 8829 | } |
b99bd4ef | 8830 | |
62b3e311 PB |
8831 | static void |
8832 | do_dbg (void) | |
8833 | { | |
8834 | inst.instruction |= inst.operands[0].imm; | |
8835 | } | |
8836 | ||
eea54501 MGD |
8837 | static void |
8838 | do_div (void) | |
8839 | { | |
8840 | unsigned Rd, Rn, Rm; | |
8841 | ||
8842 | Rd = inst.operands[0].reg; | |
8843 | Rn = (inst.operands[1].present | |
8844 | ? inst.operands[1].reg : Rd); | |
8845 | Rm = inst.operands[2].reg; | |
8846 | ||
8847 | constraint ((Rd == REG_PC), BAD_PC); | |
8848 | constraint ((Rn == REG_PC), BAD_PC); | |
8849 | constraint ((Rm == REG_PC), BAD_PC); | |
8850 | ||
8851 | inst.instruction |= Rd << 16; | |
8852 | inst.instruction |= Rn << 0; | |
8853 | inst.instruction |= Rm << 8; | |
8854 | } | |
8855 | ||
b99bd4ef | 8856 | static void |
c19d1205 | 8857 | do_it (void) |
b99bd4ef | 8858 | { |
c19d1205 | 8859 | /* There is no IT instruction in ARM mode. We |
e07e6e58 NC |
8860 | process it to do the validation as if in |
8861 | thumb mode, just in case the code gets | |
8862 | assembled for thumb using the unified syntax. */ | |
8863 | ||
c19d1205 | 8864 | inst.size = 0; |
e07e6e58 NC |
8865 | if (unified_syntax) |
8866 | { | |
8867 | set_it_insn_type (IT_INSN); | |
8868 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
8869 | now_it.cc = inst.operands[0].imm; | |
8870 | } | |
09d92015 | 8871 | } |
b99bd4ef | 8872 | |
6530b175 NC |
8873 | /* If there is only one register in the register list, |
8874 | then return its register number. Otherwise return -1. */ | |
8875 | static int | |
8876 | only_one_reg_in_list (int range) | |
8877 | { | |
8878 | int i = ffs (range) - 1; | |
8879 | return (i > 15 || range != (1 << i)) ? -1 : i; | |
8880 | } | |
8881 | ||
09d92015 | 8882 | static void |
6530b175 | 8883 | encode_ldmstm(int from_push_pop_mnem) |
ea6ef066 | 8884 | { |
c19d1205 ZW |
8885 | int base_reg = inst.operands[0].reg; |
8886 | int range = inst.operands[1].imm; | |
6530b175 | 8887 | int one_reg; |
ea6ef066 | 8888 | |
c19d1205 ZW |
8889 | inst.instruction |= base_reg << 16; |
8890 | inst.instruction |= range; | |
ea6ef066 | 8891 | |
c19d1205 ZW |
8892 | if (inst.operands[1].writeback) |
8893 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 8894 | |
c19d1205 | 8895 | if (inst.operands[0].writeback) |
ea6ef066 | 8896 | { |
c19d1205 ZW |
8897 | inst.instruction |= WRITE_BACK; |
8898 | /* Check for unpredictable uses of writeback. */ | |
8899 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 8900 | { |
c19d1205 ZW |
8901 | /* Not allowed in LDM type 2. */ |
8902 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
8903 | && ((range & (1 << REG_PC)) == 0)) | |
8904 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
8905 | /* Only allowed if base reg not in list for other types. */ | |
8906 | else if (range & (1 << base_reg)) | |
8907 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
8908 | } | |
8909 | else /* STM. */ | |
8910 | { | |
8911 | /* Not allowed for type 2. */ | |
8912 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
8913 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
8914 | /* Only allowed if base reg not in list, or first in list. */ | |
8915 | else if ((range & (1 << base_reg)) | |
8916 | && (range & ((1 << base_reg) - 1))) | |
8917 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 8918 | } |
ea6ef066 | 8919 | } |
6530b175 NC |
8920 | |
8921 | /* If PUSH/POP has only one register, then use the A2 encoding. */ | |
8922 | one_reg = only_one_reg_in_list (range); | |
8923 | if (from_push_pop_mnem && one_reg >= 0) | |
8924 | { | |
8925 | int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH; | |
8926 | ||
4f588891 NC |
8927 | if (is_push && one_reg == 13 /* SP */) |
8928 | /* PR 22483: The A2 encoding cannot be used when | |
8929 | pushing the stack pointer as this is UNPREDICTABLE. */ | |
8930 | return; | |
8931 | ||
6530b175 NC |
8932 | inst.instruction &= A_COND_MASK; |
8933 | inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP; | |
8934 | inst.instruction |= one_reg << 12; | |
8935 | } | |
8936 | } | |
8937 | ||
8938 | static void | |
8939 | do_ldmstm (void) | |
8940 | { | |
8941 | encode_ldmstm (/*from_push_pop_mnem=*/FALSE); | |
a737bd4d NC |
8942 | } |
8943 | ||
c19d1205 ZW |
8944 | /* ARMv5TE load-consecutive (argument parse) |
8945 | Mode is like LDRH. | |
8946 | ||
8947 | LDRccD R, mode | |
8948 | STRccD R, mode. */ | |
8949 | ||
a737bd4d | 8950 | static void |
c19d1205 | 8951 | do_ldrd (void) |
a737bd4d | 8952 | { |
c19d1205 | 8953 | constraint (inst.operands[0].reg % 2 != 0, |
c56791bb | 8954 | _("first transfer register must be even")); |
c19d1205 ZW |
8955 | constraint (inst.operands[1].present |
8956 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
c56791bb | 8957 | _("can only transfer two consecutive registers")); |
c19d1205 ZW |
8958 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); |
8959 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 8960 | |
c19d1205 ZW |
8961 | if (!inst.operands[1].present) |
8962 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
5f4273c7 | 8963 | |
c56791bb RE |
8964 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
8965 | register and the first register written; we have to diagnose | |
8966 | overlap between the base and the second register written here. */ | |
ea6ef066 | 8967 | |
c56791bb RE |
8968 | if (inst.operands[2].reg == inst.operands[1].reg |
8969 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
8970 | as_warn (_("base register written back, and overlaps " | |
8971 | "second transfer register")); | |
b05fe5cf | 8972 | |
c56791bb RE |
8973 | if (!(inst.instruction & V4_STR_BIT)) |
8974 | { | |
c19d1205 | 8975 | /* For an index-register load, the index register must not overlap the |
c56791bb RE |
8976 | destination (even if not write-back). */ |
8977 | if (inst.operands[2].immisreg | |
8978 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg | |
8979 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
8980 | as_warn (_("index register overlaps transfer register")); | |
b05fe5cf | 8981 | } |
c19d1205 ZW |
8982 | inst.instruction |= inst.operands[0].reg << 12; |
8983 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
8984 | } |
8985 | ||
8986 | static void | |
c19d1205 | 8987 | do_ldrex (void) |
b05fe5cf | 8988 | { |
c19d1205 ZW |
8989 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
8990 | || inst.operands[1].postind || inst.operands[1].writeback | |
8991 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
01cfc07f NC |
8992 | || inst.operands[1].negative |
8993 | /* This can arise if the programmer has written | |
8994 | strex rN, rM, foo | |
8995 | or if they have mistakenly used a register name as the last | |
8996 | operand, eg: | |
8997 | strex rN, rM, rX | |
8998 | It is very difficult to distinguish between these two cases | |
8999 | because "rX" might actually be a label. ie the register | |
9000 | name has been occluded by a symbol of the same name. So we | |
9001 | just generate a general 'bad addressing mode' type error | |
9002 | message and leave it up to the programmer to discover the | |
9003 | true cause and fix their mistake. */ | |
9004 | || (inst.operands[1].reg == REG_PC), | |
9005 | BAD_ADDR_MODE); | |
b05fe5cf | 9006 | |
c19d1205 ZW |
9007 | constraint (inst.reloc.exp.X_op != O_constant |
9008 | || inst.reloc.exp.X_add_number != 0, | |
9009 | _("offset must be zero in ARM encoding")); | |
b05fe5cf | 9010 | |
5be8be5d DG |
9011 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
9012 | ||
c19d1205 ZW |
9013 | inst.instruction |= inst.operands[0].reg << 12; |
9014 | inst.instruction |= inst.operands[1].reg << 16; | |
9015 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b05fe5cf ZW |
9016 | } |
9017 | ||
9018 | static void | |
c19d1205 | 9019 | do_ldrexd (void) |
b05fe5cf | 9020 | { |
c19d1205 ZW |
9021 | constraint (inst.operands[0].reg % 2 != 0, |
9022 | _("even register required")); | |
9023 | constraint (inst.operands[1].present | |
9024 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
9025 | _("can only load two consecutive registers")); | |
9026 | /* If op 1 were present and equal to PC, this function wouldn't | |
9027 | have been called in the first place. */ | |
9028 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 9029 | |
c19d1205 ZW |
9030 | inst.instruction |= inst.operands[0].reg << 12; |
9031 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
9032 | } |
9033 | ||
1be5fd2e NC |
9034 | /* In both ARM and thumb state 'ldr pc, #imm' with an immediate |
9035 | which is not a multiple of four is UNPREDICTABLE. */ | |
9036 | static void | |
9037 | check_ldr_r15_aligned (void) | |
9038 | { | |
9039 | constraint (!(inst.operands[1].immisreg) | |
9040 | && (inst.operands[0].reg == REG_PC | |
9041 | && inst.operands[1].reg == REG_PC | |
9042 | && (inst.reloc.exp.X_add_number & 0x3)), | |
de194d85 | 9043 | _("ldr to register 15 must be 4-byte aligned")); |
1be5fd2e NC |
9044 | } |
9045 | ||
b05fe5cf | 9046 | static void |
c19d1205 | 9047 | do_ldst (void) |
b05fe5cf | 9048 | { |
c19d1205 ZW |
9049 | inst.instruction |= inst.operands[0].reg << 12; |
9050 | if (!inst.operands[1].isreg) | |
8335d6aa | 9051 | if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE)) |
b05fe5cf | 9052 | return; |
c19d1205 | 9053 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
1be5fd2e | 9054 | check_ldr_r15_aligned (); |
b05fe5cf ZW |
9055 | } |
9056 | ||
9057 | static void | |
c19d1205 | 9058 | do_ldstt (void) |
b05fe5cf | 9059 | { |
c19d1205 ZW |
9060 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
9061 | reject [Rn,...]. */ | |
9062 | if (inst.operands[1].preind) | |
b05fe5cf | 9063 | { |
bd3ba5d1 NC |
9064 | constraint (inst.reloc.exp.X_op != O_constant |
9065 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 9066 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 9067 | |
c19d1205 ZW |
9068 | inst.operands[1].preind = 0; |
9069 | inst.operands[1].postind = 1; | |
9070 | inst.operands[1].writeback = 1; | |
b05fe5cf | 9071 | } |
c19d1205 ZW |
9072 | inst.instruction |= inst.operands[0].reg << 12; |
9073 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
9074 | } | |
b05fe5cf | 9075 | |
c19d1205 | 9076 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 9077 | |
c19d1205 ZW |
9078 | static void |
9079 | do_ldstv4 (void) | |
9080 | { | |
ff4a8d2b | 9081 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 ZW |
9082 | inst.instruction |= inst.operands[0].reg << 12; |
9083 | if (!inst.operands[1].isreg) | |
8335d6aa | 9084 | if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE)) |
b05fe5cf | 9085 | return; |
c19d1205 | 9086 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
9087 | } |
9088 | ||
9089 | static void | |
c19d1205 | 9090 | do_ldsttv4 (void) |
b05fe5cf | 9091 | { |
c19d1205 ZW |
9092 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
9093 | reject [Rn,...]. */ | |
9094 | if (inst.operands[1].preind) | |
b05fe5cf | 9095 | { |
bd3ba5d1 NC |
9096 | constraint (inst.reloc.exp.X_op != O_constant |
9097 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 9098 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 9099 | |
c19d1205 ZW |
9100 | inst.operands[1].preind = 0; |
9101 | inst.operands[1].postind = 1; | |
9102 | inst.operands[1].writeback = 1; | |
b05fe5cf | 9103 | } |
c19d1205 ZW |
9104 | inst.instruction |= inst.operands[0].reg << 12; |
9105 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
9106 | } | |
b05fe5cf | 9107 | |
c19d1205 ZW |
9108 | /* Co-processor register load/store. |
9109 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
9110 | static void | |
9111 | do_lstc (void) | |
9112 | { | |
9113 | inst.instruction |= inst.operands[0].reg << 8; | |
9114 | inst.instruction |= inst.operands[1].reg << 12; | |
9115 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
9116 | } |
9117 | ||
b05fe5cf | 9118 | static void |
c19d1205 | 9119 | do_mlas (void) |
b05fe5cf | 9120 | { |
8fb9d7b9 | 9121 | /* This restriction does not apply to mls (nor to mla in v6 or later). */ |
c19d1205 | 9122 | if (inst.operands[0].reg == inst.operands[1].reg |
8fb9d7b9 | 9123 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) |
c19d1205 | 9124 | && !(inst.instruction & 0x00400000)) |
8fb9d7b9 | 9125 | as_tsktsk (_("Rd and Rm should be different in mla")); |
b05fe5cf | 9126 | |
c19d1205 ZW |
9127 | inst.instruction |= inst.operands[0].reg << 16; |
9128 | inst.instruction |= inst.operands[1].reg; | |
9129 | inst.instruction |= inst.operands[2].reg << 8; | |
9130 | inst.instruction |= inst.operands[3].reg << 12; | |
c19d1205 | 9131 | } |
b05fe5cf | 9132 | |
c19d1205 ZW |
9133 | static void |
9134 | do_mov (void) | |
9135 | { | |
a9f02af8 MG |
9136 | constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC |
9137 | && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC , | |
9138 | THUMB1_RELOC_ONLY); | |
c19d1205 ZW |
9139 | inst.instruction |= inst.operands[0].reg << 12; |
9140 | encode_arm_shifter_operand (1); | |
9141 | } | |
b05fe5cf | 9142 | |
c19d1205 ZW |
9143 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
9144 | static void | |
9145 | do_mov16 (void) | |
9146 | { | |
b6895b4f PB |
9147 | bfd_vma imm; |
9148 | bfd_boolean top; | |
9149 | ||
9150 | top = (inst.instruction & 0x00400000) != 0; | |
9151 | constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, | |
33eaf5de | 9152 | _(":lower16: not allowed in this instruction")); |
b6895b4f | 9153 | constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, |
33eaf5de | 9154 | _(":upper16: not allowed in this instruction")); |
c19d1205 | 9155 | inst.instruction |= inst.operands[0].reg << 12; |
b6895b4f PB |
9156 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
9157 | { | |
9158 | imm = inst.reloc.exp.X_add_number; | |
9159 | /* The value is in two pieces: 0:11, 16:19. */ | |
9160 | inst.instruction |= (imm & 0x00000fff); | |
9161 | inst.instruction |= (imm & 0x0000f000) << 4; | |
9162 | } | |
b05fe5cf | 9163 | } |
b99bd4ef | 9164 | |
037e8744 JB |
9165 | static int |
9166 | do_vfp_nsyn_mrs (void) | |
9167 | { | |
9168 | if (inst.operands[0].isvec) | |
9169 | { | |
9170 | if (inst.operands[1].reg != 1) | |
477330fc | 9171 | first_error (_("operand 1 must be FPSCR")); |
037e8744 JB |
9172 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); |
9173 | memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); | |
9174 | do_vfp_nsyn_opcode ("fmstat"); | |
9175 | } | |
9176 | else if (inst.operands[1].isvec) | |
9177 | do_vfp_nsyn_opcode ("fmrx"); | |
9178 | else | |
9179 | return FAIL; | |
5f4273c7 | 9180 | |
037e8744 JB |
9181 | return SUCCESS; |
9182 | } | |
9183 | ||
9184 | static int | |
9185 | do_vfp_nsyn_msr (void) | |
9186 | { | |
9187 | if (inst.operands[0].isvec) | |
9188 | do_vfp_nsyn_opcode ("fmxr"); | |
9189 | else | |
9190 | return FAIL; | |
9191 | ||
9192 | return SUCCESS; | |
9193 | } | |
9194 | ||
f7c21dc7 NC |
9195 | static void |
9196 | do_vmrs (void) | |
9197 | { | |
9198 | unsigned Rt = inst.operands[0].reg; | |
fa94de6b | 9199 | |
16d02dc9 | 9200 | if (thumb_mode && Rt == REG_SP) |
f7c21dc7 NC |
9201 | { |
9202 | inst.error = BAD_SP; | |
9203 | return; | |
9204 | } | |
9205 | ||
40c7d507 RR |
9206 | /* MVFR2 is only valid at ARMv8-A. */ |
9207 | if (inst.operands[1].reg == 5) | |
9208 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
9209 | _(BAD_FPU)); | |
9210 | ||
f7c21dc7 | 9211 | /* APSR_ sets isvec. All other refs to PC are illegal. */ |
16d02dc9 | 9212 | if (!inst.operands[0].isvec && Rt == REG_PC) |
f7c21dc7 NC |
9213 | { |
9214 | inst.error = BAD_PC; | |
9215 | return; | |
9216 | } | |
9217 | ||
16d02dc9 JB |
9218 | /* If we get through parsing the register name, we just insert the number |
9219 | generated into the instruction without further validation. */ | |
9220 | inst.instruction |= (inst.operands[1].reg << 16); | |
f7c21dc7 NC |
9221 | inst.instruction |= (Rt << 12); |
9222 | } | |
9223 | ||
9224 | static void | |
9225 | do_vmsr (void) | |
9226 | { | |
9227 | unsigned Rt = inst.operands[1].reg; | |
fa94de6b | 9228 | |
f7c21dc7 NC |
9229 | if (thumb_mode) |
9230 | reject_bad_reg (Rt); | |
9231 | else if (Rt == REG_PC) | |
9232 | { | |
9233 | inst.error = BAD_PC; | |
9234 | return; | |
9235 | } | |
9236 | ||
40c7d507 RR |
9237 | /* MVFR2 is only valid for ARMv8-A. */ |
9238 | if (inst.operands[0].reg == 5) | |
9239 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
9240 | _(BAD_FPU)); | |
9241 | ||
16d02dc9 JB |
9242 | /* If we get through parsing the register name, we just insert the number |
9243 | generated into the instruction without further validation. */ | |
9244 | inst.instruction |= (inst.operands[0].reg << 16); | |
f7c21dc7 NC |
9245 | inst.instruction |= (Rt << 12); |
9246 | } | |
9247 | ||
b99bd4ef | 9248 | static void |
c19d1205 | 9249 | do_mrs (void) |
b99bd4ef | 9250 | { |
90ec0d68 MGD |
9251 | unsigned br; |
9252 | ||
037e8744 JB |
9253 | if (do_vfp_nsyn_mrs () == SUCCESS) |
9254 | return; | |
9255 | ||
ff4a8d2b | 9256 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 | 9257 | inst.instruction |= inst.operands[0].reg << 12; |
90ec0d68 MGD |
9258 | |
9259 | if (inst.operands[1].isreg) | |
9260 | { | |
9261 | br = inst.operands[1].reg; | |
806ab1c0 | 9262 | if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf0000)) |
90ec0d68 MGD |
9263 | as_bad (_("bad register for mrs")); |
9264 | } | |
9265 | else | |
9266 | { | |
9267 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ | |
9268 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
9269 | != (PSR_c|PSR_f), | |
d2cd1205 | 9270 | _("'APSR', 'CPSR' or 'SPSR' expected")); |
90ec0d68 MGD |
9271 | br = (15<<16) | (inst.operands[1].imm & SPSR_BIT); |
9272 | } | |
9273 | ||
9274 | inst.instruction |= br; | |
c19d1205 | 9275 | } |
b99bd4ef | 9276 | |
c19d1205 ZW |
9277 | /* Two possible forms: |
9278 | "{C|S}PSR_<field>, Rm", | |
9279 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 9280 | |
c19d1205 ZW |
9281 | static void |
9282 | do_msr (void) | |
9283 | { | |
037e8744 JB |
9284 | if (do_vfp_nsyn_msr () == SUCCESS) |
9285 | return; | |
9286 | ||
c19d1205 ZW |
9287 | inst.instruction |= inst.operands[0].imm; |
9288 | if (inst.operands[1].isreg) | |
9289 | inst.instruction |= inst.operands[1].reg; | |
9290 | else | |
b99bd4ef | 9291 | { |
c19d1205 ZW |
9292 | inst.instruction |= INST_IMMEDIATE; |
9293 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
9294 | inst.reloc.pc_rel = 0; | |
b99bd4ef | 9295 | } |
b99bd4ef NC |
9296 | } |
9297 | ||
c19d1205 ZW |
9298 | static void |
9299 | do_mul (void) | |
a737bd4d | 9300 | { |
ff4a8d2b NC |
9301 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
9302 | ||
c19d1205 ZW |
9303 | if (!inst.operands[2].present) |
9304 | inst.operands[2].reg = inst.operands[0].reg; | |
9305 | inst.instruction |= inst.operands[0].reg << 16; | |
9306 | inst.instruction |= inst.operands[1].reg; | |
9307 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 9308 | |
8fb9d7b9 MS |
9309 | if (inst.operands[0].reg == inst.operands[1].reg |
9310 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
9311 | as_tsktsk (_("Rd and Rm should be different in mul")); | |
a737bd4d NC |
9312 | } |
9313 | ||
c19d1205 ZW |
9314 | /* Long Multiply Parser |
9315 | UMULL RdLo, RdHi, Rm, Rs | |
9316 | SMULL RdLo, RdHi, Rm, Rs | |
9317 | UMLAL RdLo, RdHi, Rm, Rs | |
9318 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
9319 | |
9320 | static void | |
c19d1205 | 9321 | do_mull (void) |
b99bd4ef | 9322 | { |
c19d1205 ZW |
9323 | inst.instruction |= inst.operands[0].reg << 12; |
9324 | inst.instruction |= inst.operands[1].reg << 16; | |
9325 | inst.instruction |= inst.operands[2].reg; | |
9326 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 9327 | |
682b27ad PB |
9328 | /* rdhi and rdlo must be different. */ |
9329 | if (inst.operands[0].reg == inst.operands[1].reg) | |
9330 | as_tsktsk (_("rdhi and rdlo must be different")); | |
9331 | ||
9332 | /* rdhi, rdlo and rm must all be different before armv6. */ | |
9333 | if ((inst.operands[0].reg == inst.operands[2].reg | |
c19d1205 | 9334 | || inst.operands[1].reg == inst.operands[2].reg) |
682b27ad | 9335 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) |
c19d1205 ZW |
9336 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); |
9337 | } | |
b99bd4ef | 9338 | |
c19d1205 ZW |
9339 | static void |
9340 | do_nop (void) | |
9341 | { | |
e7495e45 NS |
9342 | if (inst.operands[0].present |
9343 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k)) | |
c19d1205 ZW |
9344 | { |
9345 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
9346 | inst.instruction &= 0xf0000000; | |
e7495e45 NS |
9347 | inst.instruction |= 0x0320f000; |
9348 | if (inst.operands[0].present) | |
9349 | inst.instruction |= inst.operands[0].imm; | |
c19d1205 | 9350 | } |
b99bd4ef NC |
9351 | } |
9352 | ||
c19d1205 ZW |
9353 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
9354 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
9355 | Condition defaults to COND_ALWAYS. | |
9356 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
9357 | |
9358 | static void | |
c19d1205 | 9359 | do_pkhbt (void) |
b99bd4ef | 9360 | { |
c19d1205 ZW |
9361 | inst.instruction |= inst.operands[0].reg << 12; |
9362 | inst.instruction |= inst.operands[1].reg << 16; | |
9363 | inst.instruction |= inst.operands[2].reg; | |
9364 | if (inst.operands[3].present) | |
9365 | encode_arm_shift (3); | |
9366 | } | |
b99bd4ef | 9367 | |
c19d1205 | 9368 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 9369 | |
c19d1205 ZW |
9370 | static void |
9371 | do_pkhtb (void) | |
9372 | { | |
9373 | if (!inst.operands[3].present) | |
b99bd4ef | 9374 | { |
c19d1205 ZW |
9375 | /* If the shift specifier is omitted, turn the instruction |
9376 | into pkhbt rd, rm, rn. */ | |
9377 | inst.instruction &= 0xfff00010; | |
9378 | inst.instruction |= inst.operands[0].reg << 12; | |
9379 | inst.instruction |= inst.operands[1].reg; | |
9380 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
9381 | } |
9382 | else | |
9383 | { | |
c19d1205 ZW |
9384 | inst.instruction |= inst.operands[0].reg << 12; |
9385 | inst.instruction |= inst.operands[1].reg << 16; | |
9386 | inst.instruction |= inst.operands[2].reg; | |
9387 | encode_arm_shift (3); | |
b99bd4ef NC |
9388 | } |
9389 | } | |
9390 | ||
c19d1205 | 9391 | /* ARMv5TE: Preload-Cache |
60e5ef9f | 9392 | MP Extensions: Preload for write |
c19d1205 | 9393 | |
60e5ef9f | 9394 | PLD(W) <addr_mode> |
c19d1205 ZW |
9395 | |
9396 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
9397 | |
9398 | static void | |
c19d1205 | 9399 | do_pld (void) |
b99bd4ef | 9400 | { |
c19d1205 ZW |
9401 | constraint (!inst.operands[0].isreg, |
9402 | _("'[' expected after PLD mnemonic")); | |
9403 | constraint (inst.operands[0].postind, | |
9404 | _("post-indexed expression used in preload instruction")); | |
9405 | constraint (inst.operands[0].writeback, | |
9406 | _("writeback used in preload instruction")); | |
9407 | constraint (!inst.operands[0].preind, | |
9408 | _("unindexed addressing used in preload instruction")); | |
c19d1205 ZW |
9409 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
9410 | } | |
b99bd4ef | 9411 | |
62b3e311 PB |
9412 | /* ARMv7: PLI <addr_mode> */ |
9413 | static void | |
9414 | do_pli (void) | |
9415 | { | |
9416 | constraint (!inst.operands[0].isreg, | |
9417 | _("'[' expected after PLI mnemonic")); | |
9418 | constraint (inst.operands[0].postind, | |
9419 | _("post-indexed expression used in preload instruction")); | |
9420 | constraint (inst.operands[0].writeback, | |
9421 | _("writeback used in preload instruction")); | |
9422 | constraint (!inst.operands[0].preind, | |
9423 | _("unindexed addressing used in preload instruction")); | |
9424 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
9425 | inst.instruction &= ~PRE_INDEX; | |
9426 | } | |
9427 | ||
c19d1205 ZW |
9428 | static void |
9429 | do_push_pop (void) | |
9430 | { | |
5e0d7f77 MP |
9431 | constraint (inst.operands[0].writeback, |
9432 | _("push/pop do not support {reglist}^")); | |
c19d1205 ZW |
9433 | inst.operands[1] = inst.operands[0]; |
9434 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
9435 | inst.operands[0].isreg = 1; | |
9436 | inst.operands[0].writeback = 1; | |
9437 | inst.operands[0].reg = REG_SP; | |
6530b175 | 9438 | encode_ldmstm (/*from_push_pop_mnem=*/TRUE); |
c19d1205 | 9439 | } |
b99bd4ef | 9440 | |
c19d1205 ZW |
9441 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
9442 | word at the specified address and the following word | |
9443 | respectively. | |
9444 | Unconditionally executed. | |
9445 | Error if Rn is R15. */ | |
b99bd4ef | 9446 | |
c19d1205 ZW |
9447 | static void |
9448 | do_rfe (void) | |
9449 | { | |
9450 | inst.instruction |= inst.operands[0].reg << 16; | |
9451 | if (inst.operands[0].writeback) | |
9452 | inst.instruction |= WRITE_BACK; | |
9453 | } | |
b99bd4ef | 9454 | |
c19d1205 | 9455 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 9456 | |
c19d1205 ZW |
9457 | static void |
9458 | do_ssat (void) | |
9459 | { | |
9460 | inst.instruction |= inst.operands[0].reg << 12; | |
9461 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
9462 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 9463 | |
c19d1205 ZW |
9464 | if (inst.operands[3].present) |
9465 | encode_arm_shift (3); | |
b99bd4ef NC |
9466 | } |
9467 | ||
c19d1205 | 9468 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
9469 | |
9470 | static void | |
c19d1205 | 9471 | do_usat (void) |
b99bd4ef | 9472 | { |
c19d1205 ZW |
9473 | inst.instruction |= inst.operands[0].reg << 12; |
9474 | inst.instruction |= inst.operands[1].imm << 16; | |
9475 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 9476 | |
c19d1205 ZW |
9477 | if (inst.operands[3].present) |
9478 | encode_arm_shift (3); | |
b99bd4ef NC |
9479 | } |
9480 | ||
c19d1205 | 9481 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
9482 | |
9483 | static void | |
c19d1205 | 9484 | do_ssat16 (void) |
09d92015 | 9485 | { |
c19d1205 ZW |
9486 | inst.instruction |= inst.operands[0].reg << 12; |
9487 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
9488 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
9489 | } |
9490 | ||
c19d1205 ZW |
9491 | static void |
9492 | do_usat16 (void) | |
a737bd4d | 9493 | { |
c19d1205 ZW |
9494 | inst.instruction |= inst.operands[0].reg << 12; |
9495 | inst.instruction |= inst.operands[1].imm << 16; | |
9496 | inst.instruction |= inst.operands[2].reg; | |
9497 | } | |
a737bd4d | 9498 | |
c19d1205 ZW |
9499 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
9500 | preserving the other bits. | |
a737bd4d | 9501 | |
c19d1205 ZW |
9502 | setend <endian_specifier>, where <endian_specifier> is either |
9503 | BE or LE. */ | |
a737bd4d | 9504 | |
c19d1205 ZW |
9505 | static void |
9506 | do_setend (void) | |
9507 | { | |
12e37cbc MGD |
9508 | if (warn_on_deprecated |
9509 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
5c3696f8 | 9510 | as_tsktsk (_("setend use is deprecated for ARMv8")); |
12e37cbc | 9511 | |
c19d1205 ZW |
9512 | if (inst.operands[0].imm) |
9513 | inst.instruction |= 0x200; | |
a737bd4d NC |
9514 | } |
9515 | ||
9516 | static void | |
c19d1205 | 9517 | do_shift (void) |
a737bd4d | 9518 | { |
c19d1205 ZW |
9519 | unsigned int Rm = (inst.operands[1].present |
9520 | ? inst.operands[1].reg | |
9521 | : inst.operands[0].reg); | |
a737bd4d | 9522 | |
c19d1205 ZW |
9523 | inst.instruction |= inst.operands[0].reg << 12; |
9524 | inst.instruction |= Rm; | |
9525 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 9526 | { |
c19d1205 ZW |
9527 | inst.instruction |= inst.operands[2].reg << 8; |
9528 | inst.instruction |= SHIFT_BY_REG; | |
94342ec3 NC |
9529 | /* PR 12854: Error on extraneous shifts. */ |
9530 | constraint (inst.operands[2].shifted, | |
9531 | _("extraneous shift as part of operand to shift insn")); | |
a737bd4d NC |
9532 | } |
9533 | else | |
c19d1205 | 9534 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
9535 | } |
9536 | ||
09d92015 | 9537 | static void |
3eb17e6b | 9538 | do_smc (void) |
09d92015 | 9539 | { |
3eb17e6b | 9540 | inst.reloc.type = BFD_RELOC_ARM_SMC; |
c19d1205 | 9541 | inst.reloc.pc_rel = 0; |
09d92015 MM |
9542 | } |
9543 | ||
90ec0d68 MGD |
9544 | static void |
9545 | do_hvc (void) | |
9546 | { | |
9547 | inst.reloc.type = BFD_RELOC_ARM_HVC; | |
9548 | inst.reloc.pc_rel = 0; | |
9549 | } | |
9550 | ||
09d92015 | 9551 | static void |
c19d1205 | 9552 | do_swi (void) |
09d92015 | 9553 | { |
c19d1205 ZW |
9554 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
9555 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
9556 | } |
9557 | ||
ddfded2f MW |
9558 | static void |
9559 | do_setpan (void) | |
9560 | { | |
9561 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan), | |
9562 | _("selected processor does not support SETPAN instruction")); | |
9563 | ||
9564 | inst.instruction |= ((inst.operands[0].imm & 1) << 9); | |
9565 | } | |
9566 | ||
9567 | static void | |
9568 | do_t_setpan (void) | |
9569 | { | |
9570 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan), | |
9571 | _("selected processor does not support SETPAN instruction")); | |
9572 | ||
9573 | inst.instruction |= (inst.operands[0].imm << 3); | |
9574 | } | |
9575 | ||
c19d1205 ZW |
9576 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
9577 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
9578 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
9579 | Error if any register is R15. */ | |
e16bb312 | 9580 | |
c19d1205 ZW |
9581 | static void |
9582 | do_smla (void) | |
e16bb312 | 9583 | { |
c19d1205 ZW |
9584 | inst.instruction |= inst.operands[0].reg << 16; |
9585 | inst.instruction |= inst.operands[1].reg; | |
9586 | inst.instruction |= inst.operands[2].reg << 8; | |
9587 | inst.instruction |= inst.operands[3].reg << 12; | |
9588 | } | |
a737bd4d | 9589 | |
c19d1205 ZW |
9590 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
9591 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
9592 | Error if any register is R15. | |
9593 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 9594 | |
c19d1205 ZW |
9595 | static void |
9596 | do_smlal (void) | |
9597 | { | |
9598 | inst.instruction |= inst.operands[0].reg << 12; | |
9599 | inst.instruction |= inst.operands[1].reg << 16; | |
9600 | inst.instruction |= inst.operands[2].reg; | |
9601 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 9602 | |
c19d1205 ZW |
9603 | if (inst.operands[0].reg == inst.operands[1].reg) |
9604 | as_tsktsk (_("rdhi and rdlo must be different")); | |
9605 | } | |
a737bd4d | 9606 | |
c19d1205 ZW |
9607 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
9608 | SMULxy{cond} Rd,Rm,Rs | |
9609 | Error if any register is R15. */ | |
a737bd4d | 9610 | |
c19d1205 ZW |
9611 | static void |
9612 | do_smul (void) | |
9613 | { | |
9614 | inst.instruction |= inst.operands[0].reg << 16; | |
9615 | inst.instruction |= inst.operands[1].reg; | |
9616 | inst.instruction |= inst.operands[2].reg << 8; | |
9617 | } | |
a737bd4d | 9618 | |
b6702015 PB |
9619 | /* ARM V6 srs (argument parse). The variable fields in the encoding are |
9620 | the same for both ARM and Thumb-2. */ | |
a737bd4d | 9621 | |
c19d1205 ZW |
9622 | static void |
9623 | do_srs (void) | |
9624 | { | |
b6702015 PB |
9625 | int reg; |
9626 | ||
9627 | if (inst.operands[0].present) | |
9628 | { | |
9629 | reg = inst.operands[0].reg; | |
fdfde340 | 9630 | constraint (reg != REG_SP, _("SRS base register must be r13")); |
b6702015 PB |
9631 | } |
9632 | else | |
fdfde340 | 9633 | reg = REG_SP; |
b6702015 PB |
9634 | |
9635 | inst.instruction |= reg << 16; | |
9636 | inst.instruction |= inst.operands[1].imm; | |
9637 | if (inst.operands[0].writeback || inst.operands[1].writeback) | |
c19d1205 ZW |
9638 | inst.instruction |= WRITE_BACK; |
9639 | } | |
a737bd4d | 9640 | |
c19d1205 | 9641 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 9642 | |
c19d1205 ZW |
9643 | static void |
9644 | do_strex (void) | |
9645 | { | |
9646 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
9647 | || inst.operands[2].postind || inst.operands[2].writeback | |
9648 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
01cfc07f NC |
9649 | || inst.operands[2].negative |
9650 | /* See comment in do_ldrex(). */ | |
9651 | || (inst.operands[2].reg == REG_PC), | |
9652 | BAD_ADDR_MODE); | |
a737bd4d | 9653 | |
c19d1205 ZW |
9654 | constraint (inst.operands[0].reg == inst.operands[1].reg |
9655 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 9656 | |
c19d1205 ZW |
9657 | constraint (inst.reloc.exp.X_op != O_constant |
9658 | || inst.reloc.exp.X_add_number != 0, | |
9659 | _("offset must be zero in ARM encoding")); | |
a737bd4d | 9660 | |
c19d1205 ZW |
9661 | inst.instruction |= inst.operands[0].reg << 12; |
9662 | inst.instruction |= inst.operands[1].reg; | |
9663 | inst.instruction |= inst.operands[2].reg << 16; | |
9664 | inst.reloc.type = BFD_RELOC_UNUSED; | |
e16bb312 NC |
9665 | } |
9666 | ||
877807f8 NC |
9667 | static void |
9668 | do_t_strexbh (void) | |
9669 | { | |
9670 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
9671 | || inst.operands[2].postind || inst.operands[2].writeback | |
9672 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
9673 | || inst.operands[2].negative, | |
9674 | BAD_ADDR_MODE); | |
9675 | ||
9676 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
9677 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
9678 | ||
9679 | do_rm_rd_rn (); | |
9680 | } | |
9681 | ||
e16bb312 | 9682 | static void |
c19d1205 | 9683 | do_strexd (void) |
e16bb312 | 9684 | { |
c19d1205 ZW |
9685 | constraint (inst.operands[1].reg % 2 != 0, |
9686 | _("even register required")); | |
9687 | constraint (inst.operands[2].present | |
9688 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
9689 | _("can only store two consecutive registers")); | |
9690 | /* If op 2 were present and equal to PC, this function wouldn't | |
9691 | have been called in the first place. */ | |
9692 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 9693 | |
c19d1205 ZW |
9694 | constraint (inst.operands[0].reg == inst.operands[1].reg |
9695 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
9696 | || inst.operands[0].reg == inst.operands[3].reg, | |
9697 | BAD_OVERLAP); | |
e16bb312 | 9698 | |
c19d1205 ZW |
9699 | inst.instruction |= inst.operands[0].reg << 12; |
9700 | inst.instruction |= inst.operands[1].reg; | |
9701 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
9702 | } |
9703 | ||
9eb6c0f1 MGD |
9704 | /* ARM V8 STRL. */ |
9705 | static void | |
4b8c8c02 | 9706 | do_stlex (void) |
9eb6c0f1 MGD |
9707 | { |
9708 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
9709 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
9710 | ||
9711 | do_rd_rm_rn (); | |
9712 | } | |
9713 | ||
9714 | static void | |
4b8c8c02 | 9715 | do_t_stlex (void) |
9eb6c0f1 MGD |
9716 | { |
9717 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
9718 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
9719 | ||
9720 | do_rm_rd_rn (); | |
9721 | } | |
9722 | ||
c19d1205 ZW |
9723 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
9724 | extends it to 32-bits, and adds the result to a value in another | |
9725 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
9726 | before extracting the 16-bit value. | |
9727 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
9728 | Condition defaults to COND_ALWAYS. | |
9729 | Error if any register uses R15. */ | |
9730 | ||
e16bb312 | 9731 | static void |
c19d1205 | 9732 | do_sxtah (void) |
e16bb312 | 9733 | { |
c19d1205 ZW |
9734 | inst.instruction |= inst.operands[0].reg << 12; |
9735 | inst.instruction |= inst.operands[1].reg << 16; | |
9736 | inst.instruction |= inst.operands[2].reg; | |
9737 | inst.instruction |= inst.operands[3].imm << 10; | |
9738 | } | |
e16bb312 | 9739 | |
c19d1205 | 9740 | /* ARM V6 SXTH. |
e16bb312 | 9741 | |
c19d1205 ZW |
9742 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
9743 | Condition defaults to COND_ALWAYS. | |
9744 | Error if any register uses R15. */ | |
e16bb312 NC |
9745 | |
9746 | static void | |
c19d1205 | 9747 | do_sxth (void) |
e16bb312 | 9748 | { |
c19d1205 ZW |
9749 | inst.instruction |= inst.operands[0].reg << 12; |
9750 | inst.instruction |= inst.operands[1].reg; | |
9751 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 9752 | } |
c19d1205 ZW |
9753 | \f |
9754 | /* VFP instructions. In a logical order: SP variant first, monad | |
9755 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
9756 | |
9757 | static void | |
c19d1205 | 9758 | do_vfp_sp_monadic (void) |
e16bb312 | 9759 | { |
5287ad62 JB |
9760 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
9761 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
9762 | } |
9763 | ||
9764 | static void | |
c19d1205 | 9765 | do_vfp_sp_dyadic (void) |
e16bb312 | 9766 | { |
5287ad62 JB |
9767 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
9768 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
9769 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
9770 | } |
9771 | ||
9772 | static void | |
c19d1205 | 9773 | do_vfp_sp_compare_z (void) |
e16bb312 | 9774 | { |
5287ad62 | 9775 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
9776 | } |
9777 | ||
9778 | static void | |
c19d1205 | 9779 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 9780 | { |
5287ad62 JB |
9781 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
9782 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
9783 | } |
9784 | ||
9785 | static void | |
c19d1205 | 9786 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 9787 | { |
5287ad62 JB |
9788 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
9789 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
e16bb312 NC |
9790 | } |
9791 | ||
9792 | static void | |
c19d1205 | 9793 | do_vfp_reg_from_sp (void) |
e16bb312 | 9794 | { |
c19d1205 | 9795 | inst.instruction |= inst.operands[0].reg << 12; |
5287ad62 | 9796 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); |
e16bb312 NC |
9797 | } |
9798 | ||
9799 | static void | |
c19d1205 | 9800 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 9801 | { |
c19d1205 ZW |
9802 | constraint (inst.operands[2].imm != 2, |
9803 | _("only two consecutive VFP SP registers allowed here")); | |
9804 | inst.instruction |= inst.operands[0].reg << 12; | |
9805 | inst.instruction |= inst.operands[1].reg << 16; | |
5287ad62 | 9806 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); |
e16bb312 NC |
9807 | } |
9808 | ||
9809 | static void | |
c19d1205 | 9810 | do_vfp_sp_from_reg (void) |
e16bb312 | 9811 | { |
5287ad62 | 9812 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); |
c19d1205 | 9813 | inst.instruction |= inst.operands[1].reg << 12; |
e16bb312 NC |
9814 | } |
9815 | ||
9816 | static void | |
c19d1205 | 9817 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 9818 | { |
c19d1205 ZW |
9819 | constraint (inst.operands[0].imm != 2, |
9820 | _("only two consecutive VFP SP registers allowed here")); | |
5287ad62 | 9821 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); |
c19d1205 ZW |
9822 | inst.instruction |= inst.operands[1].reg << 12; |
9823 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
9824 | } |
9825 | ||
9826 | static void | |
c19d1205 | 9827 | do_vfp_sp_ldst (void) |
e16bb312 | 9828 | { |
5287ad62 | 9829 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
c19d1205 | 9830 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
9831 | } |
9832 | ||
9833 | static void | |
c19d1205 | 9834 | do_vfp_dp_ldst (void) |
e16bb312 | 9835 | { |
5287ad62 | 9836 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
c19d1205 | 9837 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
9838 | } |
9839 | ||
c19d1205 | 9840 | |
e16bb312 | 9841 | static void |
c19d1205 | 9842 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 9843 | { |
c19d1205 ZW |
9844 | if (inst.operands[0].writeback) |
9845 | inst.instruction |= WRITE_BACK; | |
9846 | else | |
9847 | constraint (ldstm_type != VFP_LDSTMIA, | |
9848 | _("this addressing mode requires base-register writeback")); | |
9849 | inst.instruction |= inst.operands[0].reg << 16; | |
5287ad62 | 9850 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); |
c19d1205 | 9851 | inst.instruction |= inst.operands[1].imm; |
e16bb312 NC |
9852 | } |
9853 | ||
9854 | static void | |
c19d1205 | 9855 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 9856 | { |
c19d1205 | 9857 | int count; |
e16bb312 | 9858 | |
c19d1205 ZW |
9859 | if (inst.operands[0].writeback) |
9860 | inst.instruction |= WRITE_BACK; | |
9861 | else | |
9862 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
9863 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 9864 | |
c19d1205 | 9865 | inst.instruction |= inst.operands[0].reg << 16; |
5287ad62 | 9866 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
e16bb312 | 9867 | |
c19d1205 ZW |
9868 | count = inst.operands[1].imm << 1; |
9869 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
9870 | count += 1; | |
e16bb312 | 9871 | |
c19d1205 | 9872 | inst.instruction |= count; |
e16bb312 NC |
9873 | } |
9874 | ||
9875 | static void | |
c19d1205 | 9876 | do_vfp_sp_ldstmia (void) |
e16bb312 | 9877 | { |
c19d1205 | 9878 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
9879 | } |
9880 | ||
9881 | static void | |
c19d1205 | 9882 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 9883 | { |
c19d1205 | 9884 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
9885 | } |
9886 | ||
9887 | static void | |
c19d1205 | 9888 | do_vfp_dp_ldstmia (void) |
e16bb312 | 9889 | { |
c19d1205 | 9890 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
9891 | } |
9892 | ||
9893 | static void | |
c19d1205 | 9894 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 9895 | { |
c19d1205 | 9896 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
9897 | } |
9898 | ||
9899 | static void | |
c19d1205 | 9900 | do_vfp_xp_ldstmia (void) |
e16bb312 | 9901 | { |
c19d1205 ZW |
9902 | vfp_dp_ldstm (VFP_LDSTMIAX); |
9903 | } | |
e16bb312 | 9904 | |
c19d1205 ZW |
9905 | static void |
9906 | do_vfp_xp_ldstmdb (void) | |
9907 | { | |
9908 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 9909 | } |
5287ad62 JB |
9910 | |
9911 | static void | |
9912 | do_vfp_dp_rd_rm (void) | |
9913 | { | |
9914 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9915 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
9916 | } | |
9917 | ||
9918 | static void | |
9919 | do_vfp_dp_rn_rd (void) | |
9920 | { | |
9921 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); | |
9922 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
9923 | } | |
9924 | ||
9925 | static void | |
9926 | do_vfp_dp_rd_rn (void) | |
9927 | { | |
9928 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9929 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
9930 | } | |
9931 | ||
9932 | static void | |
9933 | do_vfp_dp_rd_rn_rm (void) | |
9934 | { | |
9935 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9936 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
9937 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); | |
9938 | } | |
9939 | ||
9940 | static void | |
9941 | do_vfp_dp_rd (void) | |
9942 | { | |
9943 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9944 | } | |
9945 | ||
9946 | static void | |
9947 | do_vfp_dp_rm_rd_rn (void) | |
9948 | { | |
9949 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); | |
9950 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
9951 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); | |
9952 | } | |
9953 | ||
9954 | /* VFPv3 instructions. */ | |
9955 | static void | |
9956 | do_vfp_sp_const (void) | |
9957 | { | |
9958 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
00249aaa PB |
9959 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
9960 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
9961 | } |
9962 | ||
9963 | static void | |
9964 | do_vfp_dp_const (void) | |
9965 | { | |
9966 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
00249aaa PB |
9967 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
9968 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
9969 | } |
9970 | ||
9971 | static void | |
9972 | vfp_conv (int srcsize) | |
9973 | { | |
5f1af56b MGD |
9974 | int immbits = srcsize - inst.operands[1].imm; |
9975 | ||
fa94de6b RM |
9976 | if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize)) |
9977 | { | |
5f1af56b | 9978 | /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16. |
477330fc | 9979 | i.e. immbits must be in range 0 - 16. */ |
5f1af56b MGD |
9980 | inst.error = _("immediate value out of range, expected range [0, 16]"); |
9981 | return; | |
9982 | } | |
fa94de6b | 9983 | else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize)) |
5f1af56b MGD |
9984 | { |
9985 | /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32. | |
477330fc | 9986 | i.e. immbits must be in range 0 - 31. */ |
5f1af56b MGD |
9987 | inst.error = _("immediate value out of range, expected range [1, 32]"); |
9988 | return; | |
9989 | } | |
9990 | ||
5287ad62 JB |
9991 | inst.instruction |= (immbits & 1) << 5; |
9992 | inst.instruction |= (immbits >> 1); | |
9993 | } | |
9994 | ||
9995 | static void | |
9996 | do_vfp_sp_conv_16 (void) | |
9997 | { | |
9998 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
9999 | vfp_conv (16); | |
10000 | } | |
10001 | ||
10002 | static void | |
10003 | do_vfp_dp_conv_16 (void) | |
10004 | { | |
10005 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
10006 | vfp_conv (16); | |
10007 | } | |
10008 | ||
10009 | static void | |
10010 | do_vfp_sp_conv_32 (void) | |
10011 | { | |
10012 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
10013 | vfp_conv (32); | |
10014 | } | |
10015 | ||
10016 | static void | |
10017 | do_vfp_dp_conv_32 (void) | |
10018 | { | |
10019 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
10020 | vfp_conv (32); | |
10021 | } | |
c19d1205 ZW |
10022 | \f |
10023 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 10024 | |
c19d1205 ZW |
10025 | static void |
10026 | do_fpa_cmp (void) | |
10027 | { | |
10028 | inst.instruction |= inst.operands[0].reg << 16; | |
10029 | inst.instruction |= inst.operands[1].reg; | |
10030 | } | |
b99bd4ef NC |
10031 | |
10032 | static void | |
c19d1205 | 10033 | do_fpa_ldmstm (void) |
b99bd4ef | 10034 | { |
c19d1205 ZW |
10035 | inst.instruction |= inst.operands[0].reg << 12; |
10036 | switch (inst.operands[1].imm) | |
10037 | { | |
10038 | case 1: inst.instruction |= CP_T_X; break; | |
10039 | case 2: inst.instruction |= CP_T_Y; break; | |
10040 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
10041 | case 4: break; | |
10042 | default: abort (); | |
10043 | } | |
b99bd4ef | 10044 | |
c19d1205 ZW |
10045 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
10046 | { | |
10047 | /* The instruction specified "ea" or "fd", so we can only accept | |
10048 | [Rn]{!}. The instruction does not really support stacking or | |
10049 | unstacking, so we have to emulate these by setting appropriate | |
10050 | bits and offsets. */ | |
10051 | constraint (inst.reloc.exp.X_op != O_constant | |
10052 | || inst.reloc.exp.X_add_number != 0, | |
10053 | _("this instruction does not support indexing")); | |
b99bd4ef | 10054 | |
c19d1205 ZW |
10055 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
10056 | inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; | |
b99bd4ef | 10057 | |
c19d1205 ZW |
10058 | if (!(inst.instruction & INDEX_UP)) |
10059 | inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; | |
b99bd4ef | 10060 | |
c19d1205 ZW |
10061 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
10062 | { | |
10063 | inst.operands[2].preind = 0; | |
10064 | inst.operands[2].postind = 1; | |
10065 | } | |
10066 | } | |
b99bd4ef | 10067 | |
c19d1205 | 10068 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 10069 | } |
c19d1205 ZW |
10070 | \f |
10071 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 10072 | |
c19d1205 ZW |
10073 | static void |
10074 | do_iwmmxt_tandorc (void) | |
10075 | { | |
10076 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
10077 | } | |
b99bd4ef | 10078 | |
c19d1205 ZW |
10079 | static void |
10080 | do_iwmmxt_textrc (void) | |
10081 | { | |
10082 | inst.instruction |= inst.operands[0].reg << 12; | |
10083 | inst.instruction |= inst.operands[1].imm; | |
10084 | } | |
b99bd4ef NC |
10085 | |
10086 | static void | |
c19d1205 | 10087 | do_iwmmxt_textrm (void) |
b99bd4ef | 10088 | { |
c19d1205 ZW |
10089 | inst.instruction |= inst.operands[0].reg << 12; |
10090 | inst.instruction |= inst.operands[1].reg << 16; | |
10091 | inst.instruction |= inst.operands[2].imm; | |
10092 | } | |
b99bd4ef | 10093 | |
c19d1205 ZW |
10094 | static void |
10095 | do_iwmmxt_tinsr (void) | |
10096 | { | |
10097 | inst.instruction |= inst.operands[0].reg << 16; | |
10098 | inst.instruction |= inst.operands[1].reg << 12; | |
10099 | inst.instruction |= inst.operands[2].imm; | |
10100 | } | |
b99bd4ef | 10101 | |
c19d1205 ZW |
10102 | static void |
10103 | do_iwmmxt_tmia (void) | |
10104 | { | |
10105 | inst.instruction |= inst.operands[0].reg << 5; | |
10106 | inst.instruction |= inst.operands[1].reg; | |
10107 | inst.instruction |= inst.operands[2].reg << 12; | |
10108 | } | |
b99bd4ef | 10109 | |
c19d1205 ZW |
10110 | static void |
10111 | do_iwmmxt_waligni (void) | |
10112 | { | |
10113 | inst.instruction |= inst.operands[0].reg << 12; | |
10114 | inst.instruction |= inst.operands[1].reg << 16; | |
10115 | inst.instruction |= inst.operands[2].reg; | |
10116 | inst.instruction |= inst.operands[3].imm << 20; | |
10117 | } | |
b99bd4ef | 10118 | |
2d447fca JM |
10119 | static void |
10120 | do_iwmmxt_wmerge (void) | |
10121 | { | |
10122 | inst.instruction |= inst.operands[0].reg << 12; | |
10123 | inst.instruction |= inst.operands[1].reg << 16; | |
10124 | inst.instruction |= inst.operands[2].reg; | |
10125 | inst.instruction |= inst.operands[3].imm << 21; | |
10126 | } | |
10127 | ||
c19d1205 ZW |
10128 | static void |
10129 | do_iwmmxt_wmov (void) | |
10130 | { | |
10131 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
10132 | inst.instruction |= inst.operands[0].reg << 12; | |
10133 | inst.instruction |= inst.operands[1].reg << 16; | |
10134 | inst.instruction |= inst.operands[1].reg; | |
10135 | } | |
b99bd4ef | 10136 | |
c19d1205 ZW |
10137 | static void |
10138 | do_iwmmxt_wldstbh (void) | |
10139 | { | |
8f06b2d8 | 10140 | int reloc; |
c19d1205 | 10141 | inst.instruction |= inst.operands[0].reg << 12; |
8f06b2d8 PB |
10142 | if (thumb_mode) |
10143 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
10144 | else | |
10145 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
10146 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
10147 | } |
10148 | ||
c19d1205 ZW |
10149 | static void |
10150 | do_iwmmxt_wldstw (void) | |
10151 | { | |
10152 | /* RIWR_RIWC clears .isreg for a control register. */ | |
10153 | if (!inst.operands[0].isreg) | |
10154 | { | |
10155 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
10156 | inst.instruction |= 0xf0000000; | |
10157 | } | |
b99bd4ef | 10158 | |
c19d1205 ZW |
10159 | inst.instruction |= inst.operands[0].reg << 12; |
10160 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
10161 | } | |
b99bd4ef NC |
10162 | |
10163 | static void | |
c19d1205 | 10164 | do_iwmmxt_wldstd (void) |
b99bd4ef | 10165 | { |
c19d1205 | 10166 | inst.instruction |= inst.operands[0].reg << 12; |
2d447fca JM |
10167 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) |
10168 | && inst.operands[1].immisreg) | |
10169 | { | |
10170 | inst.instruction &= ~0x1a000ff; | |
eff0bc54 | 10171 | inst.instruction |= (0xfU << 28); |
2d447fca JM |
10172 | if (inst.operands[1].preind) |
10173 | inst.instruction |= PRE_INDEX; | |
10174 | if (!inst.operands[1].negative) | |
10175 | inst.instruction |= INDEX_UP; | |
10176 | if (inst.operands[1].writeback) | |
10177 | inst.instruction |= WRITE_BACK; | |
10178 | inst.instruction |= inst.operands[1].reg << 16; | |
10179 | inst.instruction |= inst.reloc.exp.X_add_number << 4; | |
10180 | inst.instruction |= inst.operands[1].imm; | |
10181 | } | |
10182 | else | |
10183 | encode_arm_cp_address (1, TRUE, FALSE, 0); | |
c19d1205 | 10184 | } |
b99bd4ef | 10185 | |
c19d1205 ZW |
10186 | static void |
10187 | do_iwmmxt_wshufh (void) | |
10188 | { | |
10189 | inst.instruction |= inst.operands[0].reg << 12; | |
10190 | inst.instruction |= inst.operands[1].reg << 16; | |
10191 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
10192 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
10193 | } | |
b99bd4ef | 10194 | |
c19d1205 ZW |
10195 | static void |
10196 | do_iwmmxt_wzero (void) | |
10197 | { | |
10198 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
10199 | inst.instruction |= inst.operands[0].reg; | |
10200 | inst.instruction |= inst.operands[0].reg << 12; | |
10201 | inst.instruction |= inst.operands[0].reg << 16; | |
10202 | } | |
2d447fca JM |
10203 | |
10204 | static void | |
10205 | do_iwmmxt_wrwrwr_or_imm5 (void) | |
10206 | { | |
10207 | if (inst.operands[2].isreg) | |
10208 | do_rd_rn_rm (); | |
10209 | else { | |
10210 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), | |
10211 | _("immediate operand requires iWMMXt2")); | |
10212 | do_rd_rn (); | |
10213 | if (inst.operands[2].imm == 0) | |
10214 | { | |
10215 | switch ((inst.instruction >> 20) & 0xf) | |
10216 | { | |
10217 | case 4: | |
10218 | case 5: | |
10219 | case 6: | |
5f4273c7 | 10220 | case 7: |
2d447fca JM |
10221 | /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ |
10222 | inst.operands[2].imm = 16; | |
10223 | inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); | |
10224 | break; | |
10225 | case 8: | |
10226 | case 9: | |
10227 | case 10: | |
10228 | case 11: | |
10229 | /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ | |
10230 | inst.operands[2].imm = 32; | |
10231 | inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); | |
10232 | break; | |
10233 | case 12: | |
10234 | case 13: | |
10235 | case 14: | |
10236 | case 15: | |
10237 | { | |
10238 | /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ | |
10239 | unsigned long wrn; | |
10240 | wrn = (inst.instruction >> 16) & 0xf; | |
10241 | inst.instruction &= 0xff0fff0f; | |
10242 | inst.instruction |= wrn; | |
10243 | /* Bail out here; the instruction is now assembled. */ | |
10244 | return; | |
10245 | } | |
10246 | } | |
10247 | } | |
10248 | /* Map 32 -> 0, etc. */ | |
10249 | inst.operands[2].imm &= 0x1f; | |
eff0bc54 | 10250 | inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); |
2d447fca JM |
10251 | } |
10252 | } | |
c19d1205 ZW |
10253 | \f |
10254 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
10255 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 10256 | |
c19d1205 | 10257 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 10258 | |
c19d1205 ZW |
10259 | static void |
10260 | do_mav_triple (void) | |
10261 | { | |
10262 | inst.instruction |= inst.operands[0].reg << 16; | |
10263 | inst.instruction |= inst.operands[1].reg; | |
10264 | inst.instruction |= inst.operands[2].reg << 12; | |
10265 | } | |
b99bd4ef | 10266 | |
c19d1205 ZW |
10267 | /* Insns like "foo W,X,Y,Z". |
10268 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 10269 | |
c19d1205 ZW |
10270 | static void |
10271 | do_mav_quad (void) | |
10272 | { | |
10273 | inst.instruction |= inst.operands[0].reg << 5; | |
10274 | inst.instruction |= inst.operands[1].reg << 12; | |
10275 | inst.instruction |= inst.operands[2].reg << 16; | |
10276 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
10277 | } |
10278 | ||
c19d1205 ZW |
10279 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
10280 | static void | |
10281 | do_mav_dspsc (void) | |
a737bd4d | 10282 | { |
c19d1205 ZW |
10283 | inst.instruction |= inst.operands[1].reg << 12; |
10284 | } | |
a737bd4d | 10285 | |
c19d1205 ZW |
10286 | /* Maverick shift immediate instructions. |
10287 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
10288 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 10289 | |
c19d1205 ZW |
10290 | static void |
10291 | do_mav_shift (void) | |
10292 | { | |
10293 | int imm = inst.operands[2].imm; | |
a737bd4d | 10294 | |
c19d1205 ZW |
10295 | inst.instruction |= inst.operands[0].reg << 12; |
10296 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 10297 | |
c19d1205 ZW |
10298 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
10299 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
10300 | Bit 4 should be 0. */ | |
10301 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 10302 | |
c19d1205 ZW |
10303 | inst.instruction |= imm; |
10304 | } | |
10305 | \f | |
10306 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 10307 | |
c19d1205 ZW |
10308 | /* Xscale multiply-accumulate (argument parse) |
10309 | MIAcc acc0,Rm,Rs | |
10310 | MIAPHcc acc0,Rm,Rs | |
10311 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 10312 | |
c19d1205 ZW |
10313 | static void |
10314 | do_xsc_mia (void) | |
10315 | { | |
10316 | inst.instruction |= inst.operands[1].reg; | |
10317 | inst.instruction |= inst.operands[2].reg << 12; | |
10318 | } | |
a737bd4d | 10319 | |
c19d1205 | 10320 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 10321 | |
c19d1205 | 10322 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 10323 | |
c19d1205 ZW |
10324 | static void |
10325 | do_xsc_mar (void) | |
10326 | { | |
10327 | inst.instruction |= inst.operands[1].reg << 12; | |
10328 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
10329 | } |
10330 | ||
c19d1205 | 10331 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 10332 | |
c19d1205 | 10333 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
10334 | |
10335 | static void | |
c19d1205 | 10336 | do_xsc_mra (void) |
b99bd4ef | 10337 | { |
c19d1205 ZW |
10338 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
10339 | inst.instruction |= inst.operands[0].reg << 12; | |
10340 | inst.instruction |= inst.operands[1].reg << 16; | |
10341 | } | |
10342 | \f | |
10343 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 10344 | |
c19d1205 ZW |
10345 | /* inst.operands[i] is a shifted-register operand; encode |
10346 | it into inst.instruction in the format used by Thumb32. */ | |
10347 | ||
10348 | static void | |
10349 | encode_thumb32_shifted_operand (int i) | |
10350 | { | |
10351 | unsigned int value = inst.reloc.exp.X_add_number; | |
10352 | unsigned int shift = inst.operands[i].shift_kind; | |
b99bd4ef | 10353 | |
9c3c69f2 PB |
10354 | constraint (inst.operands[i].immisreg, |
10355 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
10356 | inst.instruction |= inst.operands[i].reg; |
10357 | if (shift == SHIFT_RRX) | |
10358 | inst.instruction |= SHIFT_ROR << 4; | |
10359 | else | |
b99bd4ef | 10360 | { |
c19d1205 ZW |
10361 | constraint (inst.reloc.exp.X_op != O_constant, |
10362 | _("expression too complex")); | |
10363 | ||
10364 | constraint (value > 32 | |
10365 | || (value == 32 && (shift == SHIFT_LSL | |
10366 | || shift == SHIFT_ROR)), | |
10367 | _("shift expression is too large")); | |
10368 | ||
10369 | if (value == 0) | |
10370 | shift = SHIFT_LSL; | |
10371 | else if (value == 32) | |
10372 | value = 0; | |
10373 | ||
10374 | inst.instruction |= shift << 4; | |
10375 | inst.instruction |= (value & 0x1c) << 10; | |
10376 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 10377 | } |
c19d1205 | 10378 | } |
b99bd4ef | 10379 | |
b99bd4ef | 10380 | |
c19d1205 ZW |
10381 | /* inst.operands[i] was set up by parse_address. Encode it into a |
10382 | Thumb32 format load or store instruction. Reject forms that cannot | |
10383 | be used with such instructions. If is_t is true, reject forms that | |
10384 | cannot be used with a T instruction; if is_d is true, reject forms | |
5be8be5d DG |
10385 | that cannot be used with a D instruction. If it is a store insn, |
10386 | reject PC in Rn. */ | |
b99bd4ef | 10387 | |
c19d1205 ZW |
10388 | static void |
10389 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
10390 | { | |
5be8be5d | 10391 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
c19d1205 ZW |
10392 | |
10393 | constraint (!inst.operands[i].isreg, | |
53365c0d | 10394 | _("Instruction does not support =N addresses")); |
b99bd4ef | 10395 | |
c19d1205 ZW |
10396 | inst.instruction |= inst.operands[i].reg << 16; |
10397 | if (inst.operands[i].immisreg) | |
b99bd4ef | 10398 | { |
5be8be5d | 10399 | constraint (is_pc, BAD_PC_ADDRESSING); |
c19d1205 ZW |
10400 | constraint (is_t || is_d, _("cannot use register index with this instruction")); |
10401 | constraint (inst.operands[i].negative, | |
10402 | _("Thumb does not support negative register indexing")); | |
10403 | constraint (inst.operands[i].postind, | |
10404 | _("Thumb does not support register post-indexing")); | |
10405 | constraint (inst.operands[i].writeback, | |
10406 | _("Thumb does not support register indexing with writeback")); | |
10407 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
10408 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 10409 | |
f40d1643 | 10410 | inst.instruction |= inst.operands[i].imm; |
c19d1205 | 10411 | if (inst.operands[i].shifted) |
b99bd4ef | 10412 | { |
c19d1205 ZW |
10413 | constraint (inst.reloc.exp.X_op != O_constant, |
10414 | _("expression too complex")); | |
9c3c69f2 PB |
10415 | constraint (inst.reloc.exp.X_add_number < 0 |
10416 | || inst.reloc.exp.X_add_number > 3, | |
c19d1205 | 10417 | _("shift out of range")); |
9c3c69f2 | 10418 | inst.instruction |= inst.reloc.exp.X_add_number << 4; |
c19d1205 ZW |
10419 | } |
10420 | inst.reloc.type = BFD_RELOC_UNUSED; | |
10421 | } | |
10422 | else if (inst.operands[i].preind) | |
10423 | { | |
5be8be5d | 10424 | constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK); |
f40d1643 | 10425 | constraint (is_t && inst.operands[i].writeback, |
c19d1205 | 10426 | _("cannot use writeback with this instruction")); |
4755303e WN |
10427 | constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0), |
10428 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
10429 | |
10430 | if (is_d) | |
10431 | { | |
10432 | inst.instruction |= 0x01000000; | |
10433 | if (inst.operands[i].writeback) | |
10434 | inst.instruction |= 0x00200000; | |
b99bd4ef | 10435 | } |
c19d1205 | 10436 | else |
b99bd4ef | 10437 | { |
c19d1205 ZW |
10438 | inst.instruction |= 0x00000c00; |
10439 | if (inst.operands[i].writeback) | |
10440 | inst.instruction |= 0x00000100; | |
b99bd4ef | 10441 | } |
c19d1205 | 10442 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 10443 | } |
c19d1205 | 10444 | else if (inst.operands[i].postind) |
b99bd4ef | 10445 | { |
9c2799c2 | 10446 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
10447 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); |
10448 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
10449 | ||
10450 | if (is_d) | |
10451 | inst.instruction |= 0x00200000; | |
10452 | else | |
10453 | inst.instruction |= 0x00000900; | |
10454 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
10455 | } | |
10456 | else /* unindexed - only for coprocessor */ | |
10457 | inst.error = _("instruction does not accept unindexed addressing"); | |
10458 | } | |
10459 | ||
10460 | /* Table of Thumb instructions which exist in both 16- and 32-bit | |
10461 | encodings (the latter only in post-V6T2 cores). The index is the | |
10462 | value used in the insns table below. When there is more than one | |
10463 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
10464 | holds variant (1). |
10465 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 | 10466 | #define T16_32_TAB \ |
21d799b5 NC |
10467 | X(_adc, 4140, eb400000), \ |
10468 | X(_adcs, 4140, eb500000), \ | |
10469 | X(_add, 1c00, eb000000), \ | |
10470 | X(_adds, 1c00, eb100000), \ | |
10471 | X(_addi, 0000, f1000000), \ | |
10472 | X(_addis, 0000, f1100000), \ | |
10473 | X(_add_pc,000f, f20f0000), \ | |
10474 | X(_add_sp,000d, f10d0000), \ | |
10475 | X(_adr, 000f, f20f0000), \ | |
10476 | X(_and, 4000, ea000000), \ | |
10477 | X(_ands, 4000, ea100000), \ | |
10478 | X(_asr, 1000, fa40f000), \ | |
10479 | X(_asrs, 1000, fa50f000), \ | |
10480 | X(_b, e000, f000b000), \ | |
10481 | X(_bcond, d000, f0008000), \ | |
10482 | X(_bic, 4380, ea200000), \ | |
10483 | X(_bics, 4380, ea300000), \ | |
10484 | X(_cmn, 42c0, eb100f00), \ | |
10485 | X(_cmp, 2800, ebb00f00), \ | |
10486 | X(_cpsie, b660, f3af8400), \ | |
10487 | X(_cpsid, b670, f3af8600), \ | |
10488 | X(_cpy, 4600, ea4f0000), \ | |
10489 | X(_dec_sp,80dd, f1ad0d00), \ | |
10490 | X(_eor, 4040, ea800000), \ | |
10491 | X(_eors, 4040, ea900000), \ | |
10492 | X(_inc_sp,00dd, f10d0d00), \ | |
10493 | X(_ldmia, c800, e8900000), \ | |
10494 | X(_ldr, 6800, f8500000), \ | |
10495 | X(_ldrb, 7800, f8100000), \ | |
10496 | X(_ldrh, 8800, f8300000), \ | |
10497 | X(_ldrsb, 5600, f9100000), \ | |
10498 | X(_ldrsh, 5e00, f9300000), \ | |
10499 | X(_ldr_pc,4800, f85f0000), \ | |
10500 | X(_ldr_pc2,4800, f85f0000), \ | |
10501 | X(_ldr_sp,9800, f85d0000), \ | |
10502 | X(_lsl, 0000, fa00f000), \ | |
10503 | X(_lsls, 0000, fa10f000), \ | |
10504 | X(_lsr, 0800, fa20f000), \ | |
10505 | X(_lsrs, 0800, fa30f000), \ | |
10506 | X(_mov, 2000, ea4f0000), \ | |
10507 | X(_movs, 2000, ea5f0000), \ | |
10508 | X(_mul, 4340, fb00f000), \ | |
10509 | X(_muls, 4340, ffffffff), /* no 32b muls */ \ | |
10510 | X(_mvn, 43c0, ea6f0000), \ | |
10511 | X(_mvns, 43c0, ea7f0000), \ | |
10512 | X(_neg, 4240, f1c00000), /* rsb #0 */ \ | |
10513 | X(_negs, 4240, f1d00000), /* rsbs #0 */ \ | |
10514 | X(_orr, 4300, ea400000), \ | |
10515 | X(_orrs, 4300, ea500000), \ | |
10516 | X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \ | |
10517 | X(_push, b400, e92d0000), /* stmdb sp!,... */ \ | |
10518 | X(_rev, ba00, fa90f080), \ | |
10519 | X(_rev16, ba40, fa90f090), \ | |
10520 | X(_revsh, bac0, fa90f0b0), \ | |
10521 | X(_ror, 41c0, fa60f000), \ | |
10522 | X(_rors, 41c0, fa70f000), \ | |
10523 | X(_sbc, 4180, eb600000), \ | |
10524 | X(_sbcs, 4180, eb700000), \ | |
10525 | X(_stmia, c000, e8800000), \ | |
10526 | X(_str, 6000, f8400000), \ | |
10527 | X(_strb, 7000, f8000000), \ | |
10528 | X(_strh, 8000, f8200000), \ | |
10529 | X(_str_sp,9000, f84d0000), \ | |
10530 | X(_sub, 1e00, eba00000), \ | |
10531 | X(_subs, 1e00, ebb00000), \ | |
10532 | X(_subi, 8000, f1a00000), \ | |
10533 | X(_subis, 8000, f1b00000), \ | |
10534 | X(_sxtb, b240, fa4ff080), \ | |
10535 | X(_sxth, b200, fa0ff080), \ | |
10536 | X(_tst, 4200, ea100f00), \ | |
10537 | X(_uxtb, b2c0, fa5ff080), \ | |
10538 | X(_uxth, b280, fa1ff080), \ | |
10539 | X(_nop, bf00, f3af8000), \ | |
10540 | X(_yield, bf10, f3af8001), \ | |
10541 | X(_wfe, bf20, f3af8002), \ | |
10542 | X(_wfi, bf30, f3af8003), \ | |
53c4b28b | 10543 | X(_sev, bf40, f3af8004), \ |
74db7efb NC |
10544 | X(_sevl, bf50, f3af8005), \ |
10545 | X(_udf, de00, f7f0a000) | |
c19d1205 ZW |
10546 | |
10547 | /* To catch errors in encoding functions, the codes are all offset by | |
10548 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
10549 | as 16-bit instructions. */ | |
21d799b5 | 10550 | #define X(a,b,c) T_MNEM##a |
c19d1205 ZW |
10551 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; |
10552 | #undef X | |
10553 | ||
10554 | #define X(a,b,c) 0x##b | |
10555 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
10556 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
10557 | #undef X | |
10558 | ||
10559 | #define X(a,b,c) 0x##c | |
10560 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
c921be7d NC |
10561 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) |
10562 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
c19d1205 ZW |
10563 | #undef X |
10564 | #undef T16_32_TAB | |
10565 | ||
10566 | /* Thumb instruction encoders, in alphabetical order. */ | |
10567 | ||
92e90b6e | 10568 | /* ADDW or SUBW. */ |
c921be7d | 10569 | |
92e90b6e PB |
10570 | static void |
10571 | do_t_add_sub_w (void) | |
10572 | { | |
10573 | int Rd, Rn; | |
10574 | ||
10575 | Rd = inst.operands[0].reg; | |
10576 | Rn = inst.operands[1].reg; | |
10577 | ||
539d4391 NC |
10578 | /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this |
10579 | is the SP-{plus,minus}-immediate form of the instruction. */ | |
10580 | if (Rn == REG_SP) | |
10581 | constraint (Rd == REG_PC, BAD_PC); | |
10582 | else | |
10583 | reject_bad_reg (Rd); | |
fdfde340 | 10584 | |
92e90b6e PB |
10585 | inst.instruction |= (Rn << 16) | (Rd << 8); |
10586 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
10587 | } | |
10588 | ||
c19d1205 | 10589 | /* Parse an add or subtract instruction. We get here with inst.instruction |
33eaf5de | 10590 | equaling any of THUMB_OPCODE_add, adds, sub, or subs. */ |
c19d1205 ZW |
10591 | |
10592 | static void | |
10593 | do_t_add_sub (void) | |
10594 | { | |
10595 | int Rd, Rs, Rn; | |
10596 | ||
10597 | Rd = inst.operands[0].reg; | |
10598 | Rs = (inst.operands[1].present | |
10599 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
10600 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
10601 | ||
e07e6e58 NC |
10602 | if (Rd == REG_PC) |
10603 | set_it_insn_type_last (); | |
10604 | ||
c19d1205 ZW |
10605 | if (unified_syntax) |
10606 | { | |
0110f2b8 PB |
10607 | bfd_boolean flags; |
10608 | bfd_boolean narrow; | |
10609 | int opcode; | |
10610 | ||
10611 | flags = (inst.instruction == T_MNEM_adds | |
10612 | || inst.instruction == T_MNEM_subs); | |
10613 | if (flags) | |
e07e6e58 | 10614 | narrow = !in_it_block (); |
0110f2b8 | 10615 | else |
e07e6e58 | 10616 | narrow = in_it_block (); |
c19d1205 | 10617 | if (!inst.operands[2].isreg) |
b99bd4ef | 10618 | { |
16805f35 PB |
10619 | int add; |
10620 | ||
5c8ed6a4 JW |
10621 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
10622 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); | |
fdfde340 | 10623 | |
16805f35 PB |
10624 | add = (inst.instruction == T_MNEM_add |
10625 | || inst.instruction == T_MNEM_adds); | |
0110f2b8 PB |
10626 | opcode = 0; |
10627 | if (inst.size_req != 4) | |
10628 | { | |
0110f2b8 | 10629 | /* Attempt to use a narrow opcode, with relaxation if |
477330fc | 10630 | appropriate. */ |
0110f2b8 PB |
10631 | if (Rd == REG_SP && Rs == REG_SP && !flags) |
10632 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
10633 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
10634 | opcode = T_MNEM_add_sp; | |
10635 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
10636 | opcode = T_MNEM_add_pc; | |
10637 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
10638 | { | |
10639 | if (flags) | |
10640 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
10641 | else | |
10642 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
10643 | } | |
10644 | if (opcode) | |
10645 | { | |
10646 | inst.instruction = THUMB_OP16(opcode); | |
10647 | inst.instruction |= (Rd << 4) | Rs; | |
72d98d16 MG |
10648 | if (inst.reloc.type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC |
10649 | || inst.reloc.type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) | |
a9f02af8 MG |
10650 | { |
10651 | if (inst.size_req == 2) | |
10652 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
10653 | else | |
10654 | inst.relax = opcode; | |
10655 | } | |
0110f2b8 PB |
10656 | } |
10657 | else | |
10658 | constraint (inst.size_req == 2, BAD_HIREG); | |
10659 | } | |
10660 | if (inst.size_req == 4 | |
10661 | || (inst.size_req != 2 && !opcode)) | |
10662 | { | |
a9f02af8 MG |
10663 | constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC |
10664 | && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC , | |
10665 | THUMB1_RELOC_ONLY); | |
efd81785 PB |
10666 | if (Rd == REG_PC) |
10667 | { | |
fdfde340 | 10668 | constraint (add, BAD_PC); |
efd81785 PB |
10669 | constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, |
10670 | _("only SUBS PC, LR, #const allowed")); | |
10671 | constraint (inst.reloc.exp.X_op != O_constant, | |
10672 | _("expression too complex")); | |
10673 | constraint (inst.reloc.exp.X_add_number < 0 | |
10674 | || inst.reloc.exp.X_add_number > 0xff, | |
10675 | _("immediate value out of range")); | |
10676 | inst.instruction = T2_SUBS_PC_LR | |
10677 | | inst.reloc.exp.X_add_number; | |
10678 | inst.reloc.type = BFD_RELOC_UNUSED; | |
10679 | return; | |
10680 | } | |
10681 | else if (Rs == REG_PC) | |
16805f35 PB |
10682 | { |
10683 | /* Always use addw/subw. */ | |
10684 | inst.instruction = add ? 0xf20f0000 : 0xf2af0000; | |
10685 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
10686 | } | |
10687 | else | |
10688 | { | |
10689 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10690 | inst.instruction = (inst.instruction & 0xe1ffffff) | |
10691 | | 0x10000000; | |
10692 | if (flags) | |
10693 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10694 | else | |
10695 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; | |
10696 | } | |
dc4503c6 PB |
10697 | inst.instruction |= Rd << 8; |
10698 | inst.instruction |= Rs << 16; | |
0110f2b8 | 10699 | } |
b99bd4ef | 10700 | } |
c19d1205 ZW |
10701 | else |
10702 | { | |
5f4cb198 NC |
10703 | unsigned int value = inst.reloc.exp.X_add_number; |
10704 | unsigned int shift = inst.operands[2].shift_kind; | |
10705 | ||
c19d1205 ZW |
10706 | Rn = inst.operands[2].reg; |
10707 | /* See if we can do this with a 16-bit instruction. */ | |
10708 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
10709 | { | |
e27ec89e PB |
10710 | if (Rd > 7 || Rs > 7 || Rn > 7) |
10711 | narrow = FALSE; | |
10712 | ||
10713 | if (narrow) | |
c19d1205 | 10714 | { |
e27ec89e PB |
10715 | inst.instruction = ((inst.instruction == T_MNEM_adds |
10716 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
10717 | ? T_OPCODE_ADD_R3 |
10718 | : T_OPCODE_SUB_R3); | |
10719 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
10720 | return; | |
10721 | } | |
b99bd4ef | 10722 | |
7e806470 | 10723 | if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) |
c19d1205 | 10724 | { |
7e806470 PB |
10725 | /* Thumb-1 cores (except v6-M) require at least one high |
10726 | register in a narrow non flag setting add. */ | |
10727 | if (Rd > 7 || Rn > 7 | |
10728 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2) | |
10729 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr)) | |
c19d1205 | 10730 | { |
7e806470 PB |
10731 | if (Rd == Rn) |
10732 | { | |
10733 | Rn = Rs; | |
10734 | Rs = Rd; | |
10735 | } | |
c19d1205 ZW |
10736 | inst.instruction = T_OPCODE_ADD_HI; |
10737 | inst.instruction |= (Rd & 8) << 4; | |
10738 | inst.instruction |= (Rd & 7); | |
10739 | inst.instruction |= Rn << 3; | |
10740 | return; | |
10741 | } | |
c19d1205 ZW |
10742 | } |
10743 | } | |
c921be7d | 10744 | |
fdfde340 | 10745 | constraint (Rd == REG_PC, BAD_PC); |
5c8ed6a4 JW |
10746 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
10747 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); | |
fdfde340 JM |
10748 | constraint (Rs == REG_PC, BAD_PC); |
10749 | reject_bad_reg (Rn); | |
10750 | ||
c19d1205 ZW |
10751 | /* If we get here, it can't be done in 16 bits. */ |
10752 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
10753 | _("shift must be constant")); | |
10754 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10755 | inst.instruction |= Rd << 8; | |
10756 | inst.instruction |= Rs << 16; | |
5f4cb198 NC |
10757 | constraint (Rd == REG_SP && Rs == REG_SP && value > 3, |
10758 | _("shift value over 3 not allowed in thumb mode")); | |
10759 | constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL, | |
10760 | _("only LSL shift allowed in thumb mode")); | |
c19d1205 ZW |
10761 | encode_thumb32_shifted_operand (2); |
10762 | } | |
10763 | } | |
10764 | else | |
10765 | { | |
10766 | constraint (inst.instruction == T_MNEM_adds | |
10767 | || inst.instruction == T_MNEM_subs, | |
10768 | BAD_THUMB32); | |
b99bd4ef | 10769 | |
c19d1205 | 10770 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 10771 | { |
c19d1205 ZW |
10772 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
10773 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
10774 | BAD_HIREG); | |
10775 | ||
10776 | inst.instruction = (inst.instruction == T_MNEM_add | |
10777 | ? 0x0000 : 0x8000); | |
10778 | inst.instruction |= (Rd << 4) | Rs; | |
10779 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
b99bd4ef NC |
10780 | return; |
10781 | } | |
10782 | ||
c19d1205 ZW |
10783 | Rn = inst.operands[2].reg; |
10784 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 10785 | |
c19d1205 ZW |
10786 | /* We now have Rd, Rs, and Rn set to registers. */ |
10787 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 10788 | { |
c19d1205 ZW |
10789 | /* Can't do this for SUB. */ |
10790 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
10791 | inst.instruction = T_OPCODE_ADD_HI; | |
10792 | inst.instruction |= (Rd & 8) << 4; | |
10793 | inst.instruction |= (Rd & 7); | |
10794 | if (Rs == Rd) | |
10795 | inst.instruction |= Rn << 3; | |
10796 | else if (Rn == Rd) | |
10797 | inst.instruction |= Rs << 3; | |
10798 | else | |
10799 | constraint (1, _("dest must overlap one source register")); | |
10800 | } | |
10801 | else | |
10802 | { | |
10803 | inst.instruction = (inst.instruction == T_MNEM_add | |
10804 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
10805 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 10806 | } |
b99bd4ef | 10807 | } |
b99bd4ef NC |
10808 | } |
10809 | ||
c19d1205 ZW |
10810 | static void |
10811 | do_t_adr (void) | |
10812 | { | |
fdfde340 JM |
10813 | unsigned Rd; |
10814 | ||
10815 | Rd = inst.operands[0].reg; | |
10816 | reject_bad_reg (Rd); | |
10817 | ||
10818 | if (unified_syntax && inst.size_req == 0 && Rd <= 7) | |
0110f2b8 PB |
10819 | { |
10820 | /* Defer to section relaxation. */ | |
10821 | inst.relax = inst.instruction; | |
10822 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 | 10823 | inst.instruction |= Rd << 4; |
0110f2b8 PB |
10824 | } |
10825 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 10826 | { |
0110f2b8 | 10827 | /* Generate a 32-bit opcode. */ |
e9f89963 | 10828 | inst.instruction = THUMB_OP32 (inst.instruction); |
fdfde340 | 10829 | inst.instruction |= Rd << 8; |
e9f89963 PB |
10830 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; |
10831 | inst.reloc.pc_rel = 1; | |
10832 | } | |
10833 | else | |
10834 | { | |
0110f2b8 | 10835 | /* Generate a 16-bit opcode. */ |
e9f89963 PB |
10836 | inst.instruction = THUMB_OP16 (inst.instruction); |
10837 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
10838 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
10839 | inst.reloc.pc_rel = 1; | |
fdfde340 | 10840 | inst.instruction |= Rd << 4; |
e9f89963 | 10841 | } |
52a86f84 NC |
10842 | |
10843 | if (inst.reloc.exp.X_op == O_symbol | |
10844 | && inst.reloc.exp.X_add_symbol != NULL | |
10845 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
10846 | && THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
10847 | inst.reloc.exp.X_add_number += 1; | |
c19d1205 | 10848 | } |
b99bd4ef | 10849 | |
c19d1205 ZW |
10850 | /* Arithmetic instructions for which there is just one 16-bit |
10851 | instruction encoding, and it allows only two low registers. | |
10852 | For maximal compatibility with ARM syntax, we allow three register | |
10853 | operands even when Thumb-32 instructions are not available, as long | |
10854 | as the first two are identical. For instance, both "sbc r0,r1" and | |
10855 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 10856 | static void |
c19d1205 | 10857 | do_t_arit3 (void) |
b99bd4ef | 10858 | { |
c19d1205 | 10859 | int Rd, Rs, Rn; |
b99bd4ef | 10860 | |
c19d1205 ZW |
10861 | Rd = inst.operands[0].reg; |
10862 | Rs = (inst.operands[1].present | |
10863 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
10864 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
10865 | Rn = inst.operands[2].reg; | |
b99bd4ef | 10866 | |
fdfde340 JM |
10867 | reject_bad_reg (Rd); |
10868 | reject_bad_reg (Rs); | |
10869 | if (inst.operands[2].isreg) | |
10870 | reject_bad_reg (Rn); | |
10871 | ||
c19d1205 | 10872 | if (unified_syntax) |
b99bd4ef | 10873 | { |
c19d1205 ZW |
10874 | if (!inst.operands[2].isreg) |
10875 | { | |
10876 | /* For an immediate, we always generate a 32-bit opcode; | |
10877 | section relaxation will shrink it later if possible. */ | |
10878 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10879 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
10880 | inst.instruction |= Rd << 8; | |
10881 | inst.instruction |= Rs << 16; | |
10882 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10883 | } | |
10884 | else | |
10885 | { | |
e27ec89e PB |
10886 | bfd_boolean narrow; |
10887 | ||
c19d1205 | 10888 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 10889 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 10890 | narrow = !in_it_block (); |
e27ec89e | 10891 | else |
e07e6e58 | 10892 | narrow = in_it_block (); |
e27ec89e PB |
10893 | |
10894 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
10895 | narrow = FALSE; | |
10896 | if (inst.operands[2].shifted) | |
10897 | narrow = FALSE; | |
10898 | if (inst.size_req == 4) | |
10899 | narrow = FALSE; | |
10900 | ||
10901 | if (narrow | |
c19d1205 ZW |
10902 | && Rd == Rs) |
10903 | { | |
10904 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10905 | inst.instruction |= Rd; | |
10906 | inst.instruction |= Rn << 3; | |
10907 | return; | |
10908 | } | |
b99bd4ef | 10909 | |
c19d1205 ZW |
10910 | /* If we get here, it can't be done in 16 bits. */ |
10911 | constraint (inst.operands[2].shifted | |
10912 | && inst.operands[2].immisreg, | |
10913 | _("shift must be constant")); | |
10914 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10915 | inst.instruction |= Rd << 8; | |
10916 | inst.instruction |= Rs << 16; | |
10917 | encode_thumb32_shifted_operand (2); | |
10918 | } | |
a737bd4d | 10919 | } |
c19d1205 | 10920 | else |
b99bd4ef | 10921 | { |
c19d1205 ZW |
10922 | /* On its face this is a lie - the instruction does set the |
10923 | flags. However, the only supported mnemonic in this mode | |
10924 | says it doesn't. */ | |
10925 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 10926 | |
c19d1205 ZW |
10927 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
10928 | _("unshifted register required")); | |
10929 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
10930 | constraint (Rd != Rs, | |
10931 | _("dest and source1 must be the same register")); | |
a737bd4d | 10932 | |
c19d1205 ZW |
10933 | inst.instruction = THUMB_OP16 (inst.instruction); |
10934 | inst.instruction |= Rd; | |
10935 | inst.instruction |= Rn << 3; | |
b99bd4ef | 10936 | } |
a737bd4d | 10937 | } |
b99bd4ef | 10938 | |
c19d1205 ZW |
10939 | /* Similarly, but for instructions where the arithmetic operation is |
10940 | commutative, so we can allow either of them to be different from | |
10941 | the destination operand in a 16-bit instruction. For instance, all | |
10942 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
10943 | accepted. */ | |
10944 | static void | |
10945 | do_t_arit3c (void) | |
a737bd4d | 10946 | { |
c19d1205 | 10947 | int Rd, Rs, Rn; |
b99bd4ef | 10948 | |
c19d1205 ZW |
10949 | Rd = inst.operands[0].reg; |
10950 | Rs = (inst.operands[1].present | |
10951 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
10952 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
10953 | Rn = inst.operands[2].reg; | |
c921be7d | 10954 | |
fdfde340 JM |
10955 | reject_bad_reg (Rd); |
10956 | reject_bad_reg (Rs); | |
10957 | if (inst.operands[2].isreg) | |
10958 | reject_bad_reg (Rn); | |
a737bd4d | 10959 | |
c19d1205 | 10960 | if (unified_syntax) |
a737bd4d | 10961 | { |
c19d1205 | 10962 | if (!inst.operands[2].isreg) |
b99bd4ef | 10963 | { |
c19d1205 ZW |
10964 | /* For an immediate, we always generate a 32-bit opcode; |
10965 | section relaxation will shrink it later if possible. */ | |
10966 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10967 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
10968 | inst.instruction |= Rd << 8; | |
10969 | inst.instruction |= Rs << 16; | |
10970 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 10971 | } |
c19d1205 | 10972 | else |
a737bd4d | 10973 | { |
e27ec89e PB |
10974 | bfd_boolean narrow; |
10975 | ||
c19d1205 | 10976 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 10977 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 10978 | narrow = !in_it_block (); |
e27ec89e | 10979 | else |
e07e6e58 | 10980 | narrow = in_it_block (); |
e27ec89e PB |
10981 | |
10982 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
10983 | narrow = FALSE; | |
10984 | if (inst.operands[2].shifted) | |
10985 | narrow = FALSE; | |
10986 | if (inst.size_req == 4) | |
10987 | narrow = FALSE; | |
10988 | ||
10989 | if (narrow) | |
a737bd4d | 10990 | { |
c19d1205 | 10991 | if (Rd == Rs) |
a737bd4d | 10992 | { |
c19d1205 ZW |
10993 | inst.instruction = THUMB_OP16 (inst.instruction); |
10994 | inst.instruction |= Rd; | |
10995 | inst.instruction |= Rn << 3; | |
10996 | return; | |
a737bd4d | 10997 | } |
c19d1205 | 10998 | if (Rd == Rn) |
a737bd4d | 10999 | { |
c19d1205 ZW |
11000 | inst.instruction = THUMB_OP16 (inst.instruction); |
11001 | inst.instruction |= Rd; | |
11002 | inst.instruction |= Rs << 3; | |
11003 | return; | |
a737bd4d NC |
11004 | } |
11005 | } | |
c19d1205 ZW |
11006 | |
11007 | /* If we get here, it can't be done in 16 bits. */ | |
11008 | constraint (inst.operands[2].shifted | |
11009 | && inst.operands[2].immisreg, | |
11010 | _("shift must be constant")); | |
11011 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11012 | inst.instruction |= Rd << 8; | |
11013 | inst.instruction |= Rs << 16; | |
11014 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 11015 | } |
b99bd4ef | 11016 | } |
c19d1205 ZW |
11017 | else |
11018 | { | |
11019 | /* On its face this is a lie - the instruction does set the | |
11020 | flags. However, the only supported mnemonic in this mode | |
11021 | says it doesn't. */ | |
11022 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 11023 | |
c19d1205 ZW |
11024 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
11025 | _("unshifted register required")); | |
11026 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
11027 | ||
11028 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11029 | inst.instruction |= Rd; | |
11030 | ||
11031 | if (Rd == Rs) | |
11032 | inst.instruction |= Rn << 3; | |
11033 | else if (Rd == Rn) | |
11034 | inst.instruction |= Rs << 3; | |
11035 | else | |
11036 | constraint (1, _("dest must overlap one source register")); | |
11037 | } | |
a737bd4d NC |
11038 | } |
11039 | ||
c19d1205 ZW |
11040 | static void |
11041 | do_t_bfc (void) | |
a737bd4d | 11042 | { |
fdfde340 | 11043 | unsigned Rd; |
c19d1205 ZW |
11044 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
11045 | constraint (msb > 32, _("bit-field extends past end of register")); | |
11046 | /* The instruction encoding stores the LSB and MSB, | |
11047 | not the LSB and width. */ | |
fdfde340 JM |
11048 | Rd = inst.operands[0].reg; |
11049 | reject_bad_reg (Rd); | |
11050 | inst.instruction |= Rd << 8; | |
c19d1205 ZW |
11051 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; |
11052 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
11053 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
11054 | } |
11055 | ||
c19d1205 ZW |
11056 | static void |
11057 | do_t_bfi (void) | |
b99bd4ef | 11058 | { |
fdfde340 | 11059 | int Rd, Rn; |
c19d1205 | 11060 | unsigned int msb; |
b99bd4ef | 11061 | |
fdfde340 JM |
11062 | Rd = inst.operands[0].reg; |
11063 | reject_bad_reg (Rd); | |
11064 | ||
c19d1205 ZW |
11065 | /* #0 in second position is alternative syntax for bfc, which is |
11066 | the same instruction but with REG_PC in the Rm field. */ | |
11067 | if (!inst.operands[1].isreg) | |
fdfde340 JM |
11068 | Rn = REG_PC; |
11069 | else | |
11070 | { | |
11071 | Rn = inst.operands[1].reg; | |
11072 | reject_bad_reg (Rn); | |
11073 | } | |
b99bd4ef | 11074 | |
c19d1205 ZW |
11075 | msb = inst.operands[2].imm + inst.operands[3].imm; |
11076 | constraint (msb > 32, _("bit-field extends past end of register")); | |
11077 | /* The instruction encoding stores the LSB and MSB, | |
11078 | not the LSB and width. */ | |
fdfde340 JM |
11079 | inst.instruction |= Rd << 8; |
11080 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
11081 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
11082 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
11083 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
11084 | } |
11085 | ||
c19d1205 ZW |
11086 | static void |
11087 | do_t_bfx (void) | |
b99bd4ef | 11088 | { |
fdfde340 JM |
11089 | unsigned Rd, Rn; |
11090 | ||
11091 | Rd = inst.operands[0].reg; | |
11092 | Rn = inst.operands[1].reg; | |
11093 | ||
11094 | reject_bad_reg (Rd); | |
11095 | reject_bad_reg (Rn); | |
11096 | ||
c19d1205 ZW |
11097 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
11098 | _("bit-field extends past end of register")); | |
fdfde340 JM |
11099 | inst.instruction |= Rd << 8; |
11100 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
11101 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
11102 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
11103 | inst.instruction |= inst.operands[3].imm - 1; | |
11104 | } | |
b99bd4ef | 11105 | |
c19d1205 ZW |
11106 | /* ARM V5 Thumb BLX (argument parse) |
11107 | BLX <target_addr> which is BLX(1) | |
11108 | BLX <Rm> which is BLX(2) | |
11109 | Unfortunately, there are two different opcodes for this mnemonic. | |
11110 | So, the insns[].value is not used, and the code here zaps values | |
11111 | into inst.instruction. | |
b99bd4ef | 11112 | |
c19d1205 ZW |
11113 | ??? How to take advantage of the additional two bits of displacement |
11114 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 11115 | |
c19d1205 ZW |
11116 | static void |
11117 | do_t_blx (void) | |
11118 | { | |
e07e6e58 NC |
11119 | set_it_insn_type_last (); |
11120 | ||
c19d1205 | 11121 | if (inst.operands[0].isreg) |
fdfde340 JM |
11122 | { |
11123 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); | |
11124 | /* We have a register, so this is BLX(2). */ | |
11125 | inst.instruction |= inst.operands[0].reg << 3; | |
11126 | } | |
b99bd4ef NC |
11127 | else |
11128 | { | |
c19d1205 | 11129 | /* No register. This must be BLX(1). */ |
2fc8bdac | 11130 | inst.instruction = 0xf000e800; |
0855e32b | 11131 | encode_branch (BFD_RELOC_THUMB_PCREL_BLX); |
b99bd4ef NC |
11132 | } |
11133 | } | |
11134 | ||
c19d1205 ZW |
11135 | static void |
11136 | do_t_branch (void) | |
b99bd4ef | 11137 | { |
0110f2b8 | 11138 | int opcode; |
dfa9f0d5 | 11139 | int cond; |
2fe88214 | 11140 | bfd_reloc_code_real_type reloc; |
dfa9f0d5 | 11141 | |
e07e6e58 NC |
11142 | cond = inst.cond; |
11143 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); | |
11144 | ||
11145 | if (in_it_block ()) | |
dfa9f0d5 PB |
11146 | { |
11147 | /* Conditional branches inside IT blocks are encoded as unconditional | |
477330fc | 11148 | branches. */ |
dfa9f0d5 | 11149 | cond = COND_ALWAYS; |
dfa9f0d5 PB |
11150 | } |
11151 | else | |
11152 | cond = inst.cond; | |
11153 | ||
11154 | if (cond != COND_ALWAYS) | |
0110f2b8 PB |
11155 | opcode = T_MNEM_bcond; |
11156 | else | |
11157 | opcode = inst.instruction; | |
11158 | ||
12d6b0b7 RS |
11159 | if (unified_syntax |
11160 | && (inst.size_req == 4 | |
10960bfb PB |
11161 | || (inst.size_req != 2 |
11162 | && (inst.operands[0].hasreloc | |
11163 | || inst.reloc.exp.X_op == O_constant)))) | |
c19d1205 | 11164 | { |
0110f2b8 | 11165 | inst.instruction = THUMB_OP32(opcode); |
dfa9f0d5 | 11166 | if (cond == COND_ALWAYS) |
9ae92b05 | 11167 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
11168 | else |
11169 | { | |
ff8646ee TP |
11170 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2), |
11171 | _("selected architecture does not support " | |
11172 | "wide conditional branch instruction")); | |
11173 | ||
9c2799c2 | 11174 | gas_assert (cond != 0xF); |
dfa9f0d5 | 11175 | inst.instruction |= cond << 22; |
9ae92b05 | 11176 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH20; |
c19d1205 ZW |
11177 | } |
11178 | } | |
b99bd4ef NC |
11179 | else |
11180 | { | |
0110f2b8 | 11181 | inst.instruction = THUMB_OP16(opcode); |
dfa9f0d5 | 11182 | if (cond == COND_ALWAYS) |
9ae92b05 | 11183 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH12; |
c19d1205 | 11184 | else |
b99bd4ef | 11185 | { |
dfa9f0d5 | 11186 | inst.instruction |= cond << 8; |
9ae92b05 | 11187 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 11188 | } |
0110f2b8 PB |
11189 | /* Allow section relaxation. */ |
11190 | if (unified_syntax && inst.size_req != 2) | |
11191 | inst.relax = opcode; | |
b99bd4ef | 11192 | } |
9ae92b05 | 11193 | inst.reloc.type = reloc; |
c19d1205 | 11194 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
11195 | } |
11196 | ||
8884b720 | 11197 | /* Actually do the work for Thumb state bkpt and hlt. The only difference |
bacebabc | 11198 | between the two is the maximum immediate allowed - which is passed in |
8884b720 | 11199 | RANGE. */ |
b99bd4ef | 11200 | static void |
8884b720 | 11201 | do_t_bkpt_hlt1 (int range) |
b99bd4ef | 11202 | { |
dfa9f0d5 PB |
11203 | constraint (inst.cond != COND_ALWAYS, |
11204 | _("instruction is always unconditional")); | |
c19d1205 | 11205 | if (inst.operands[0].present) |
b99bd4ef | 11206 | { |
8884b720 | 11207 | constraint (inst.operands[0].imm > range, |
c19d1205 ZW |
11208 | _("immediate value out of range")); |
11209 | inst.instruction |= inst.operands[0].imm; | |
b99bd4ef | 11210 | } |
8884b720 MGD |
11211 | |
11212 | set_it_insn_type (NEUTRAL_IT_INSN); | |
11213 | } | |
11214 | ||
11215 | static void | |
11216 | do_t_hlt (void) | |
11217 | { | |
11218 | do_t_bkpt_hlt1 (63); | |
11219 | } | |
11220 | ||
11221 | static void | |
11222 | do_t_bkpt (void) | |
11223 | { | |
11224 | do_t_bkpt_hlt1 (255); | |
b99bd4ef NC |
11225 | } |
11226 | ||
11227 | static void | |
c19d1205 | 11228 | do_t_branch23 (void) |
b99bd4ef | 11229 | { |
e07e6e58 | 11230 | set_it_insn_type_last (); |
0855e32b | 11231 | encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23); |
fa94de6b | 11232 | |
0855e32b NS |
11233 | /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in |
11234 | this file. We used to simply ignore the PLT reloc type here -- | |
11235 | the branch encoding is now needed to deal with TLSCALL relocs. | |
11236 | So if we see a PLT reloc now, put it back to how it used to be to | |
11237 | keep the preexisting behaviour. */ | |
11238 | if (inst.reloc.type == BFD_RELOC_ARM_PLT32) | |
11239 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
90e4755a | 11240 | |
4343666d | 11241 | #if defined(OBJ_COFF) |
c19d1205 ZW |
11242 | /* If the destination of the branch is a defined symbol which does not have |
11243 | the THUMB_FUNC attribute, then we must be calling a function which has | |
11244 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
11245 | function and change the branch to refer to that function instead. */ | |
11246 | if ( inst.reloc.exp.X_op == O_symbol | |
11247 | && inst.reloc.exp.X_add_symbol != NULL | |
11248 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
11249 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
11250 | inst.reloc.exp.X_add_symbol = | |
11251 | find_real_start (inst.reloc.exp.X_add_symbol); | |
4343666d | 11252 | #endif |
90e4755a RE |
11253 | } |
11254 | ||
11255 | static void | |
c19d1205 | 11256 | do_t_bx (void) |
90e4755a | 11257 | { |
e07e6e58 | 11258 | set_it_insn_type_last (); |
c19d1205 ZW |
11259 | inst.instruction |= inst.operands[0].reg << 3; |
11260 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
11261 | should cause the alignment to be checked once it is known. This is | |
11262 | because BX PC only works if the instruction is word aligned. */ | |
11263 | } | |
90e4755a | 11264 | |
c19d1205 ZW |
11265 | static void |
11266 | do_t_bxj (void) | |
11267 | { | |
fdfde340 | 11268 | int Rm; |
90e4755a | 11269 | |
e07e6e58 | 11270 | set_it_insn_type_last (); |
fdfde340 JM |
11271 | Rm = inst.operands[0].reg; |
11272 | reject_bad_reg (Rm); | |
11273 | inst.instruction |= Rm << 16; | |
90e4755a RE |
11274 | } |
11275 | ||
11276 | static void | |
c19d1205 | 11277 | do_t_clz (void) |
90e4755a | 11278 | { |
fdfde340 JM |
11279 | unsigned Rd; |
11280 | unsigned Rm; | |
11281 | ||
11282 | Rd = inst.operands[0].reg; | |
11283 | Rm = inst.operands[1].reg; | |
11284 | ||
11285 | reject_bad_reg (Rd); | |
11286 | reject_bad_reg (Rm); | |
11287 | ||
11288 | inst.instruction |= Rd << 8; | |
11289 | inst.instruction |= Rm << 16; | |
11290 | inst.instruction |= Rm; | |
c19d1205 | 11291 | } |
90e4755a | 11292 | |
91d8b670 JG |
11293 | static void |
11294 | do_t_csdb (void) | |
11295 | { | |
11296 | set_it_insn_type (OUTSIDE_IT_INSN); | |
11297 | } | |
11298 | ||
dfa9f0d5 PB |
11299 | static void |
11300 | do_t_cps (void) | |
11301 | { | |
e07e6e58 | 11302 | set_it_insn_type (OUTSIDE_IT_INSN); |
dfa9f0d5 PB |
11303 | inst.instruction |= inst.operands[0].imm; |
11304 | } | |
11305 | ||
c19d1205 ZW |
11306 | static void |
11307 | do_t_cpsi (void) | |
11308 | { | |
e07e6e58 | 11309 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 | 11310 | if (unified_syntax |
62b3e311 PB |
11311 | && (inst.operands[1].present || inst.size_req == 4) |
11312 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) | |
90e4755a | 11313 | { |
c19d1205 ZW |
11314 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
11315 | inst.instruction = 0xf3af8000; | |
11316 | inst.instruction |= imod << 9; | |
11317 | inst.instruction |= inst.operands[0].imm << 5; | |
11318 | if (inst.operands[1].present) | |
11319 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 11320 | } |
c19d1205 | 11321 | else |
90e4755a | 11322 | { |
62b3e311 PB |
11323 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) |
11324 | && (inst.operands[0].imm & 4), | |
11325 | _("selected processor does not support 'A' form " | |
11326 | "of this instruction")); | |
11327 | constraint (inst.operands[1].present || inst.size_req == 4, | |
c19d1205 ZW |
11328 | _("Thumb does not support the 2-argument " |
11329 | "form of this instruction")); | |
11330 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 11331 | } |
90e4755a RE |
11332 | } |
11333 | ||
c19d1205 ZW |
11334 | /* THUMB CPY instruction (argument parse). */ |
11335 | ||
90e4755a | 11336 | static void |
c19d1205 | 11337 | do_t_cpy (void) |
90e4755a | 11338 | { |
c19d1205 | 11339 | if (inst.size_req == 4) |
90e4755a | 11340 | { |
c19d1205 ZW |
11341 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
11342 | inst.instruction |= inst.operands[0].reg << 8; | |
11343 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 11344 | } |
c19d1205 | 11345 | else |
90e4755a | 11346 | { |
c19d1205 ZW |
11347 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
11348 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
11349 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 11350 | } |
90e4755a RE |
11351 | } |
11352 | ||
90e4755a | 11353 | static void |
25fe350b | 11354 | do_t_cbz (void) |
90e4755a | 11355 | { |
e07e6e58 | 11356 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
11357 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
11358 | inst.instruction |= inst.operands[0].reg; | |
11359 | inst.reloc.pc_rel = 1; | |
11360 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
11361 | } | |
90e4755a | 11362 | |
62b3e311 PB |
11363 | static void |
11364 | do_t_dbg (void) | |
11365 | { | |
11366 | inst.instruction |= inst.operands[0].imm; | |
11367 | } | |
11368 | ||
11369 | static void | |
11370 | do_t_div (void) | |
11371 | { | |
fdfde340 JM |
11372 | unsigned Rd, Rn, Rm; |
11373 | ||
11374 | Rd = inst.operands[0].reg; | |
11375 | Rn = (inst.operands[1].present | |
11376 | ? inst.operands[1].reg : Rd); | |
11377 | Rm = inst.operands[2].reg; | |
11378 | ||
11379 | reject_bad_reg (Rd); | |
11380 | reject_bad_reg (Rn); | |
11381 | reject_bad_reg (Rm); | |
11382 | ||
11383 | inst.instruction |= Rd << 8; | |
11384 | inst.instruction |= Rn << 16; | |
11385 | inst.instruction |= Rm; | |
62b3e311 PB |
11386 | } |
11387 | ||
c19d1205 ZW |
11388 | static void |
11389 | do_t_hint (void) | |
11390 | { | |
11391 | if (unified_syntax && inst.size_req == 4) | |
11392 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11393 | else | |
11394 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11395 | } | |
90e4755a | 11396 | |
c19d1205 ZW |
11397 | static void |
11398 | do_t_it (void) | |
11399 | { | |
11400 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e | 11401 | |
e07e6e58 NC |
11402 | set_it_insn_type (IT_INSN); |
11403 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
11404 | now_it.cc = cond; | |
5a01bb1d | 11405 | now_it.warn_deprecated = FALSE; |
e27ec89e PB |
11406 | |
11407 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 11408 | if ((cond & 0x1) == 0x0) |
90e4755a | 11409 | { |
c19d1205 | 11410 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 11411 | |
c19d1205 | 11412 | if ((mask & 0x7) == 0) |
5a01bb1d MGD |
11413 | { |
11414 | /* No conversion needed. */ | |
11415 | now_it.block_length = 1; | |
11416 | } | |
c19d1205 | 11417 | else if ((mask & 0x3) == 0) |
5a01bb1d MGD |
11418 | { |
11419 | mask ^= 0x8; | |
11420 | now_it.block_length = 2; | |
11421 | } | |
e27ec89e | 11422 | else if ((mask & 0x1) == 0) |
5a01bb1d MGD |
11423 | { |
11424 | mask ^= 0xC; | |
11425 | now_it.block_length = 3; | |
11426 | } | |
c19d1205 | 11427 | else |
5a01bb1d MGD |
11428 | { |
11429 | mask ^= 0xE; | |
11430 | now_it.block_length = 4; | |
11431 | } | |
90e4755a | 11432 | |
e27ec89e PB |
11433 | inst.instruction &= 0xfff0; |
11434 | inst.instruction |= mask; | |
c19d1205 | 11435 | } |
90e4755a | 11436 | |
c19d1205 ZW |
11437 | inst.instruction |= cond << 4; |
11438 | } | |
90e4755a | 11439 | |
3c707909 PB |
11440 | /* Helper function used for both push/pop and ldm/stm. */ |
11441 | static void | |
11442 | encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) | |
11443 | { | |
11444 | bfd_boolean load; | |
11445 | ||
11446 | load = (inst.instruction & (1 << 20)) != 0; | |
11447 | ||
11448 | if (mask & (1 << 13)) | |
11449 | inst.error = _("SP not allowed in register list"); | |
1e5b0379 NC |
11450 | |
11451 | if ((mask & (1 << base)) != 0 | |
11452 | && writeback) | |
11453 | inst.error = _("having the base register in the register list when " | |
11454 | "using write back is UNPREDICTABLE"); | |
11455 | ||
3c707909 PB |
11456 | if (load) |
11457 | { | |
e07e6e58 | 11458 | if (mask & (1 << 15)) |
477330fc RM |
11459 | { |
11460 | if (mask & (1 << 14)) | |
11461 | inst.error = _("LR and PC should not both be in register list"); | |
11462 | else | |
11463 | set_it_insn_type_last (); | |
11464 | } | |
3c707909 PB |
11465 | } |
11466 | else | |
11467 | { | |
11468 | if (mask & (1 << 15)) | |
11469 | inst.error = _("PC not allowed in register list"); | |
3c707909 PB |
11470 | } |
11471 | ||
11472 | if ((mask & (mask - 1)) == 0) | |
11473 | { | |
11474 | /* Single register transfers implemented as str/ldr. */ | |
11475 | if (writeback) | |
11476 | { | |
11477 | if (inst.instruction & (1 << 23)) | |
11478 | inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ | |
11479 | else | |
11480 | inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ | |
11481 | } | |
11482 | else | |
11483 | { | |
11484 | if (inst.instruction & (1 << 23)) | |
11485 | inst.instruction = 0x00800000; /* ia -> [base] */ | |
11486 | else | |
11487 | inst.instruction = 0x00000c04; /* db -> [base, #-4] */ | |
11488 | } | |
11489 | ||
11490 | inst.instruction |= 0xf8400000; | |
11491 | if (load) | |
11492 | inst.instruction |= 0x00100000; | |
11493 | ||
5f4273c7 | 11494 | mask = ffs (mask) - 1; |
3c707909 PB |
11495 | mask <<= 12; |
11496 | } | |
11497 | else if (writeback) | |
11498 | inst.instruction |= WRITE_BACK; | |
11499 | ||
11500 | inst.instruction |= mask; | |
11501 | inst.instruction |= base << 16; | |
11502 | } | |
11503 | ||
c19d1205 ZW |
11504 | static void |
11505 | do_t_ldmstm (void) | |
11506 | { | |
11507 | /* This really doesn't seem worth it. */ | |
11508 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
11509 | _("expression too complex")); | |
11510 | constraint (inst.operands[1].writeback, | |
11511 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 11512 | |
c19d1205 ZW |
11513 | if (unified_syntax) |
11514 | { | |
3c707909 PB |
11515 | bfd_boolean narrow; |
11516 | unsigned mask; | |
11517 | ||
11518 | narrow = FALSE; | |
c19d1205 ZW |
11519 | /* See if we can use a 16-bit instruction. */ |
11520 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
11521 | && inst.size_req != 4 | |
3c707909 | 11522 | && !(inst.operands[1].imm & ~0xff)) |
90e4755a | 11523 | { |
3c707909 | 11524 | mask = 1 << inst.operands[0].reg; |
90e4755a | 11525 | |
eab4f823 | 11526 | if (inst.operands[0].reg <= 7) |
90e4755a | 11527 | { |
3c707909 | 11528 | if (inst.instruction == T_MNEM_stmia |
eab4f823 MGD |
11529 | ? inst.operands[0].writeback |
11530 | : (inst.operands[0].writeback | |
11531 | == !(inst.operands[1].imm & mask))) | |
477330fc | 11532 | { |
eab4f823 MGD |
11533 | if (inst.instruction == T_MNEM_stmia |
11534 | && (inst.operands[1].imm & mask) | |
11535 | && (inst.operands[1].imm & (mask - 1))) | |
11536 | as_warn (_("value stored for r%d is UNKNOWN"), | |
11537 | inst.operands[0].reg); | |
3c707909 | 11538 | |
eab4f823 MGD |
11539 | inst.instruction = THUMB_OP16 (inst.instruction); |
11540 | inst.instruction |= inst.operands[0].reg << 8; | |
11541 | inst.instruction |= inst.operands[1].imm; | |
11542 | narrow = TRUE; | |
11543 | } | |
11544 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
11545 | { | |
11546 | /* This means 1 register in reg list one of 3 situations: | |
11547 | 1. Instruction is stmia, but without writeback. | |
11548 | 2. lmdia without writeback, but with Rn not in | |
477330fc | 11549 | reglist. |
eab4f823 MGD |
11550 | 3. ldmia with writeback, but with Rn in reglist. |
11551 | Case 3 is UNPREDICTABLE behaviour, so we handle | |
11552 | case 1 and 2 which can be converted into a 16-bit | |
11553 | str or ldr. The SP cases are handled below. */ | |
11554 | unsigned long opcode; | |
11555 | /* First, record an error for Case 3. */ | |
11556 | if (inst.operands[1].imm & mask | |
11557 | && inst.operands[0].writeback) | |
fa94de6b | 11558 | inst.error = |
eab4f823 MGD |
11559 | _("having the base register in the register list when " |
11560 | "using write back is UNPREDICTABLE"); | |
fa94de6b RM |
11561 | |
11562 | opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str | |
eab4f823 MGD |
11563 | : T_MNEM_ldr); |
11564 | inst.instruction = THUMB_OP16 (opcode); | |
11565 | inst.instruction |= inst.operands[0].reg << 3; | |
11566 | inst.instruction |= (ffs (inst.operands[1].imm)-1); | |
11567 | narrow = TRUE; | |
11568 | } | |
90e4755a | 11569 | } |
eab4f823 | 11570 | else if (inst.operands[0] .reg == REG_SP) |
90e4755a | 11571 | { |
eab4f823 MGD |
11572 | if (inst.operands[0].writeback) |
11573 | { | |
fa94de6b | 11574 | inst.instruction = |
eab4f823 | 11575 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
477330fc | 11576 | ? T_MNEM_push : T_MNEM_pop); |
eab4f823 | 11577 | inst.instruction |= inst.operands[1].imm; |
477330fc | 11578 | narrow = TRUE; |
eab4f823 MGD |
11579 | } |
11580 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
11581 | { | |
fa94de6b | 11582 | inst.instruction = |
eab4f823 | 11583 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
477330fc | 11584 | ? T_MNEM_str_sp : T_MNEM_ldr_sp); |
eab4f823 | 11585 | inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8); |
477330fc | 11586 | narrow = TRUE; |
eab4f823 | 11587 | } |
90e4755a | 11588 | } |
3c707909 PB |
11589 | } |
11590 | ||
11591 | if (!narrow) | |
11592 | { | |
c19d1205 ZW |
11593 | if (inst.instruction < 0xffff) |
11594 | inst.instruction = THUMB_OP32 (inst.instruction); | |
3c707909 | 11595 | |
5f4273c7 NC |
11596 | encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm, |
11597 | inst.operands[0].writeback); | |
90e4755a RE |
11598 | } |
11599 | } | |
c19d1205 | 11600 | else |
90e4755a | 11601 | { |
c19d1205 ZW |
11602 | constraint (inst.operands[0].reg > 7 |
11603 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
1198ca51 PB |
11604 | constraint (inst.instruction != T_MNEM_ldmia |
11605 | && inst.instruction != T_MNEM_stmia, | |
11606 | _("Thumb-2 instruction only valid in unified syntax")); | |
c19d1205 | 11607 | if (inst.instruction == T_MNEM_stmia) |
f03698e6 | 11608 | { |
c19d1205 ZW |
11609 | if (!inst.operands[0].writeback) |
11610 | as_warn (_("this instruction will write back the base register")); | |
11611 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
11612 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
1e5b0379 | 11613 | as_warn (_("value stored for r%d is UNKNOWN"), |
c19d1205 | 11614 | inst.operands[0].reg); |
f03698e6 | 11615 | } |
c19d1205 | 11616 | else |
90e4755a | 11617 | { |
c19d1205 ZW |
11618 | if (!inst.operands[0].writeback |
11619 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
11620 | as_warn (_("this instruction will write back the base register")); | |
11621 | else if (inst.operands[0].writeback | |
11622 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
11623 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
11624 | } |
11625 | ||
c19d1205 ZW |
11626 | inst.instruction = THUMB_OP16 (inst.instruction); |
11627 | inst.instruction |= inst.operands[0].reg << 8; | |
11628 | inst.instruction |= inst.operands[1].imm; | |
11629 | } | |
11630 | } | |
e28cd48c | 11631 | |
c19d1205 ZW |
11632 | static void |
11633 | do_t_ldrex (void) | |
11634 | { | |
11635 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
11636 | || inst.operands[1].postind || inst.operands[1].writeback | |
11637 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
11638 | || inst.operands[1].negative, | |
01cfc07f | 11639 | BAD_ADDR_MODE); |
e28cd48c | 11640 | |
5be8be5d DG |
11641 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
11642 | ||
c19d1205 ZW |
11643 | inst.instruction |= inst.operands[0].reg << 12; |
11644 | inst.instruction |= inst.operands[1].reg << 16; | |
11645 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
11646 | } | |
e28cd48c | 11647 | |
c19d1205 ZW |
11648 | static void |
11649 | do_t_ldrexd (void) | |
11650 | { | |
11651 | if (!inst.operands[1].present) | |
1cac9012 | 11652 | { |
c19d1205 ZW |
11653 | constraint (inst.operands[0].reg == REG_LR, |
11654 | _("r14 not allowed as first register " | |
11655 | "when second register is omitted")); | |
11656 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 11657 | } |
c19d1205 ZW |
11658 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
11659 | BAD_OVERLAP); | |
b99bd4ef | 11660 | |
c19d1205 ZW |
11661 | inst.instruction |= inst.operands[0].reg << 12; |
11662 | inst.instruction |= inst.operands[1].reg << 8; | |
11663 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
11664 | } |
11665 | ||
11666 | static void | |
c19d1205 | 11667 | do_t_ldst (void) |
b99bd4ef | 11668 | { |
0110f2b8 PB |
11669 | unsigned long opcode; |
11670 | int Rn; | |
11671 | ||
e07e6e58 NC |
11672 | if (inst.operands[0].isreg |
11673 | && !inst.operands[0].preind | |
11674 | && inst.operands[0].reg == REG_PC) | |
11675 | set_it_insn_type_last (); | |
11676 | ||
0110f2b8 | 11677 | opcode = inst.instruction; |
c19d1205 | 11678 | if (unified_syntax) |
b99bd4ef | 11679 | { |
53365c0d PB |
11680 | if (!inst.operands[1].isreg) |
11681 | { | |
11682 | if (opcode <= 0xffff) | |
11683 | inst.instruction = THUMB_OP32 (opcode); | |
8335d6aa | 11684 | if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE)) |
53365c0d PB |
11685 | return; |
11686 | } | |
0110f2b8 PB |
11687 | if (inst.operands[1].isreg |
11688 | && !inst.operands[1].writeback | |
c19d1205 ZW |
11689 | && !inst.operands[1].shifted && !inst.operands[1].postind |
11690 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
11691 | && opcode <= 0xffff |
11692 | && inst.size_req != 4) | |
c19d1205 | 11693 | { |
0110f2b8 PB |
11694 | /* Insn may have a 16-bit form. */ |
11695 | Rn = inst.operands[1].reg; | |
11696 | if (inst.operands[1].immisreg) | |
11697 | { | |
11698 | inst.instruction = THUMB_OP16 (opcode); | |
5f4273c7 | 11699 | /* [Rn, Rik] */ |
0110f2b8 PB |
11700 | if (Rn <= 7 && inst.operands[1].imm <= 7) |
11701 | goto op16; | |
5be8be5d DG |
11702 | else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str) |
11703 | reject_bad_reg (inst.operands[1].imm); | |
0110f2b8 PB |
11704 | } |
11705 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
11706 | && opcode != T_MNEM_ldrsb) | |
11707 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
11708 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
11709 | { | |
11710 | /* [Rn, #const] */ | |
11711 | if (Rn > 7) | |
11712 | { | |
11713 | if (Rn == REG_PC) | |
11714 | { | |
11715 | if (inst.reloc.pc_rel) | |
11716 | opcode = T_MNEM_ldr_pc2; | |
11717 | else | |
11718 | opcode = T_MNEM_ldr_pc; | |
11719 | } | |
11720 | else | |
11721 | { | |
11722 | if (opcode == T_MNEM_ldr) | |
11723 | opcode = T_MNEM_ldr_sp; | |
11724 | else | |
11725 | opcode = T_MNEM_str_sp; | |
11726 | } | |
11727 | inst.instruction = inst.operands[0].reg << 8; | |
11728 | } | |
11729 | else | |
11730 | { | |
11731 | inst.instruction = inst.operands[0].reg; | |
11732 | inst.instruction |= inst.operands[1].reg << 3; | |
11733 | } | |
11734 | inst.instruction |= THUMB_OP16 (opcode); | |
11735 | if (inst.size_req == 2) | |
11736 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
11737 | else | |
11738 | inst.relax = opcode; | |
11739 | return; | |
11740 | } | |
c19d1205 | 11741 | } |
0110f2b8 | 11742 | /* Definitely a 32-bit variant. */ |
5be8be5d | 11743 | |
8d67f500 NC |
11744 | /* Warning for Erratum 752419. */ |
11745 | if (opcode == T_MNEM_ldr | |
11746 | && inst.operands[0].reg == REG_SP | |
11747 | && inst.operands[1].writeback == 1 | |
11748 | && !inst.operands[1].immisreg) | |
11749 | { | |
11750 | if (no_cpu_selected () | |
11751 | || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7) | |
477330fc RM |
11752 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a) |
11753 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r))) | |
8d67f500 NC |
11754 | as_warn (_("This instruction may be unpredictable " |
11755 | "if executed on M-profile cores " | |
11756 | "with interrupts enabled.")); | |
11757 | } | |
11758 | ||
5be8be5d | 11759 | /* Do some validations regarding addressing modes. */ |
1be5fd2e | 11760 | if (inst.operands[1].immisreg) |
5be8be5d DG |
11761 | reject_bad_reg (inst.operands[1].imm); |
11762 | ||
1be5fd2e NC |
11763 | constraint (inst.operands[1].writeback == 1 |
11764 | && inst.operands[0].reg == inst.operands[1].reg, | |
11765 | BAD_OVERLAP); | |
11766 | ||
0110f2b8 | 11767 | inst.instruction = THUMB_OP32 (opcode); |
c19d1205 ZW |
11768 | inst.instruction |= inst.operands[0].reg << 12; |
11769 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
1be5fd2e | 11770 | check_ldr_r15_aligned (); |
b99bd4ef NC |
11771 | return; |
11772 | } | |
11773 | ||
c19d1205 ZW |
11774 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
11775 | ||
11776 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 11777 | { |
c19d1205 ZW |
11778 | /* Only [Rn,Rm] is acceptable. */ |
11779 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
11780 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
11781 | || inst.operands[1].postind || inst.operands[1].shifted | |
11782 | || inst.operands[1].negative, | |
11783 | _("Thumb does not support this addressing mode")); | |
11784 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11785 | goto op16; | |
b99bd4ef | 11786 | } |
5f4273c7 | 11787 | |
c19d1205 ZW |
11788 | inst.instruction = THUMB_OP16 (inst.instruction); |
11789 | if (!inst.operands[1].isreg) | |
8335d6aa | 11790 | if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE)) |
c19d1205 | 11791 | return; |
b99bd4ef | 11792 | |
c19d1205 ZW |
11793 | constraint (!inst.operands[1].preind |
11794 | || inst.operands[1].shifted | |
11795 | || inst.operands[1].writeback, | |
11796 | _("Thumb does not support this addressing mode")); | |
11797 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 11798 | { |
c19d1205 ZW |
11799 | constraint (inst.instruction & 0x0600, |
11800 | _("byte or halfword not valid for base register")); | |
11801 | constraint (inst.operands[1].reg == REG_PC | |
11802 | && !(inst.instruction & THUMB_LOAD_BIT), | |
11803 | _("r15 based store not allowed")); | |
11804 | constraint (inst.operands[1].immisreg, | |
11805 | _("invalid base register for register offset")); | |
b99bd4ef | 11806 | |
c19d1205 ZW |
11807 | if (inst.operands[1].reg == REG_PC) |
11808 | inst.instruction = T_OPCODE_LDR_PC; | |
11809 | else if (inst.instruction & THUMB_LOAD_BIT) | |
11810 | inst.instruction = T_OPCODE_LDR_SP; | |
11811 | else | |
11812 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 11813 | |
c19d1205 ZW |
11814 | inst.instruction |= inst.operands[0].reg << 8; |
11815 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
11816 | return; | |
11817 | } | |
90e4755a | 11818 | |
c19d1205 ZW |
11819 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
11820 | if (!inst.operands[1].immisreg) | |
11821 | { | |
11822 | /* Immediate offset. */ | |
11823 | inst.instruction |= inst.operands[0].reg; | |
11824 | inst.instruction |= inst.operands[1].reg << 3; | |
11825 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
11826 | return; | |
11827 | } | |
90e4755a | 11828 | |
c19d1205 ZW |
11829 | /* Register offset. */ |
11830 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
11831 | constraint (inst.operands[1].negative, | |
11832 | _("Thumb does not support this addressing mode")); | |
90e4755a | 11833 | |
c19d1205 ZW |
11834 | op16: |
11835 | switch (inst.instruction) | |
11836 | { | |
11837 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
11838 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
11839 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
11840 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
11841 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
11842 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
11843 | case 0x5600 /* ldrsb */: | |
11844 | case 0x5e00 /* ldrsh */: break; | |
11845 | default: abort (); | |
11846 | } | |
90e4755a | 11847 | |
c19d1205 ZW |
11848 | inst.instruction |= inst.operands[0].reg; |
11849 | inst.instruction |= inst.operands[1].reg << 3; | |
11850 | inst.instruction |= inst.operands[1].imm << 6; | |
11851 | } | |
90e4755a | 11852 | |
c19d1205 ZW |
11853 | static void |
11854 | do_t_ldstd (void) | |
11855 | { | |
11856 | if (!inst.operands[1].present) | |
b99bd4ef | 11857 | { |
c19d1205 ZW |
11858 | inst.operands[1].reg = inst.operands[0].reg + 1; |
11859 | constraint (inst.operands[0].reg == REG_LR, | |
11860 | _("r14 not allowed here")); | |
bd340a04 | 11861 | constraint (inst.operands[0].reg == REG_R12, |
477330fc | 11862 | _("r12 not allowed here")); |
b99bd4ef | 11863 | } |
bd340a04 MGD |
11864 | |
11865 | if (inst.operands[2].writeback | |
11866 | && (inst.operands[0].reg == inst.operands[2].reg | |
11867 | || inst.operands[1].reg == inst.operands[2].reg)) | |
11868 | as_warn (_("base register written back, and overlaps " | |
477330fc | 11869 | "one of transfer registers")); |
bd340a04 | 11870 | |
c19d1205 ZW |
11871 | inst.instruction |= inst.operands[0].reg << 12; |
11872 | inst.instruction |= inst.operands[1].reg << 8; | |
11873 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
b99bd4ef NC |
11874 | } |
11875 | ||
c19d1205 ZW |
11876 | static void |
11877 | do_t_ldstt (void) | |
11878 | { | |
11879 | inst.instruction |= inst.operands[0].reg << 12; | |
11880 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
11881 | } | |
a737bd4d | 11882 | |
b99bd4ef | 11883 | static void |
c19d1205 | 11884 | do_t_mla (void) |
b99bd4ef | 11885 | { |
fdfde340 | 11886 | unsigned Rd, Rn, Rm, Ra; |
c921be7d | 11887 | |
fdfde340 JM |
11888 | Rd = inst.operands[0].reg; |
11889 | Rn = inst.operands[1].reg; | |
11890 | Rm = inst.operands[2].reg; | |
11891 | Ra = inst.operands[3].reg; | |
11892 | ||
11893 | reject_bad_reg (Rd); | |
11894 | reject_bad_reg (Rn); | |
11895 | reject_bad_reg (Rm); | |
11896 | reject_bad_reg (Ra); | |
11897 | ||
11898 | inst.instruction |= Rd << 8; | |
11899 | inst.instruction |= Rn << 16; | |
11900 | inst.instruction |= Rm; | |
11901 | inst.instruction |= Ra << 12; | |
c19d1205 | 11902 | } |
b99bd4ef | 11903 | |
c19d1205 ZW |
11904 | static void |
11905 | do_t_mlal (void) | |
11906 | { | |
fdfde340 JM |
11907 | unsigned RdLo, RdHi, Rn, Rm; |
11908 | ||
11909 | RdLo = inst.operands[0].reg; | |
11910 | RdHi = inst.operands[1].reg; | |
11911 | Rn = inst.operands[2].reg; | |
11912 | Rm = inst.operands[3].reg; | |
11913 | ||
11914 | reject_bad_reg (RdLo); | |
11915 | reject_bad_reg (RdHi); | |
11916 | reject_bad_reg (Rn); | |
11917 | reject_bad_reg (Rm); | |
11918 | ||
11919 | inst.instruction |= RdLo << 12; | |
11920 | inst.instruction |= RdHi << 8; | |
11921 | inst.instruction |= Rn << 16; | |
11922 | inst.instruction |= Rm; | |
c19d1205 | 11923 | } |
b99bd4ef | 11924 | |
c19d1205 ZW |
11925 | static void |
11926 | do_t_mov_cmp (void) | |
11927 | { | |
fdfde340 JM |
11928 | unsigned Rn, Rm; |
11929 | ||
11930 | Rn = inst.operands[0].reg; | |
11931 | Rm = inst.operands[1].reg; | |
11932 | ||
e07e6e58 NC |
11933 | if (Rn == REG_PC) |
11934 | set_it_insn_type_last (); | |
11935 | ||
c19d1205 | 11936 | if (unified_syntax) |
b99bd4ef | 11937 | { |
c19d1205 ZW |
11938 | int r0off = (inst.instruction == T_MNEM_mov |
11939 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 11940 | unsigned long opcode; |
3d388997 PB |
11941 | bfd_boolean narrow; |
11942 | bfd_boolean low_regs; | |
11943 | ||
fdfde340 | 11944 | low_regs = (Rn <= 7 && Rm <= 7); |
0110f2b8 | 11945 | opcode = inst.instruction; |
e07e6e58 | 11946 | if (in_it_block ()) |
0110f2b8 | 11947 | narrow = opcode != T_MNEM_movs; |
3d388997 | 11948 | else |
0110f2b8 | 11949 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
11950 | if (inst.size_req == 4 |
11951 | || inst.operands[1].shifted) | |
11952 | narrow = FALSE; | |
11953 | ||
efd81785 PB |
11954 | /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ |
11955 | if (opcode == T_MNEM_movs && inst.operands[1].isreg | |
11956 | && !inst.operands[1].shifted | |
fdfde340 JM |
11957 | && Rn == REG_PC |
11958 | && Rm == REG_LR) | |
efd81785 PB |
11959 | { |
11960 | inst.instruction = T2_SUBS_PC_LR; | |
11961 | return; | |
11962 | } | |
11963 | ||
fdfde340 JM |
11964 | if (opcode == T_MNEM_cmp) |
11965 | { | |
11966 | constraint (Rn == REG_PC, BAD_PC); | |
94206790 MM |
11967 | if (narrow) |
11968 | { | |
11969 | /* In the Thumb-2 ISA, use of R13 as Rm is deprecated, | |
11970 | but valid. */ | |
11971 | warn_deprecated_sp (Rm); | |
11972 | /* R15 was documented as a valid choice for Rm in ARMv6, | |
11973 | but as UNPREDICTABLE in ARMv7. ARM's proprietary | |
11974 | tools reject R15, so we do too. */ | |
11975 | constraint (Rm == REG_PC, BAD_PC); | |
11976 | } | |
11977 | else | |
11978 | reject_bad_reg (Rm); | |
fdfde340 JM |
11979 | } |
11980 | else if (opcode == T_MNEM_mov | |
11981 | || opcode == T_MNEM_movs) | |
11982 | { | |
11983 | if (inst.operands[1].isreg) | |
11984 | { | |
11985 | if (opcode == T_MNEM_movs) | |
11986 | { | |
11987 | reject_bad_reg (Rn); | |
11988 | reject_bad_reg (Rm); | |
11989 | } | |
76fa04a4 MGD |
11990 | else if (narrow) |
11991 | { | |
11992 | /* This is mov.n. */ | |
11993 | if ((Rn == REG_SP || Rn == REG_PC) | |
11994 | && (Rm == REG_SP || Rm == REG_PC)) | |
11995 | { | |
5c3696f8 | 11996 | as_tsktsk (_("Use of r%u as a source register is " |
76fa04a4 MGD |
11997 | "deprecated when r%u is the destination " |
11998 | "register."), Rm, Rn); | |
11999 | } | |
12000 | } | |
12001 | else | |
12002 | { | |
12003 | /* This is mov.w. */ | |
12004 | constraint (Rn == REG_PC, BAD_PC); | |
12005 | constraint (Rm == REG_PC, BAD_PC); | |
5c8ed6a4 JW |
12006 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
12007 | constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); | |
76fa04a4 | 12008 | } |
fdfde340 JM |
12009 | } |
12010 | else | |
12011 | reject_bad_reg (Rn); | |
12012 | } | |
12013 | ||
c19d1205 ZW |
12014 | if (!inst.operands[1].isreg) |
12015 | { | |
0110f2b8 | 12016 | /* Immediate operand. */ |
e07e6e58 | 12017 | if (!in_it_block () && opcode == T_MNEM_mov) |
0110f2b8 PB |
12018 | narrow = 0; |
12019 | if (low_regs && narrow) | |
12020 | { | |
12021 | inst.instruction = THUMB_OP16 (opcode); | |
fdfde340 | 12022 | inst.instruction |= Rn << 8; |
a9f02af8 MG |
12023 | if (inst.reloc.type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC |
12024 | || inst.reloc.type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) | |
72d98d16 | 12025 | { |
a9f02af8 | 12026 | if (inst.size_req == 2) |
72d98d16 | 12027 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; |
a9f02af8 MG |
12028 | else |
12029 | inst.relax = opcode; | |
72d98d16 | 12030 | } |
0110f2b8 PB |
12031 | } |
12032 | else | |
12033 | { | |
a9f02af8 MG |
12034 | constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC |
12035 | && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC , | |
12036 | THUMB1_RELOC_ONLY); | |
12037 | ||
0110f2b8 PB |
12038 | inst.instruction = THUMB_OP32 (inst.instruction); |
12039 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 12040 | inst.instruction |= Rn << r0off; |
0110f2b8 PB |
12041 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
12042 | } | |
c19d1205 | 12043 | } |
728ca7c9 PB |
12044 | else if (inst.operands[1].shifted && inst.operands[1].immisreg |
12045 | && (inst.instruction == T_MNEM_mov | |
12046 | || inst.instruction == T_MNEM_movs)) | |
12047 | { | |
12048 | /* Register shifts are encoded as separate shift instructions. */ | |
12049 | bfd_boolean flags = (inst.instruction == T_MNEM_movs); | |
12050 | ||
e07e6e58 | 12051 | if (in_it_block ()) |
728ca7c9 PB |
12052 | narrow = !flags; |
12053 | else | |
12054 | narrow = flags; | |
12055 | ||
12056 | if (inst.size_req == 4) | |
12057 | narrow = FALSE; | |
12058 | ||
12059 | if (!low_regs || inst.operands[1].imm > 7) | |
12060 | narrow = FALSE; | |
12061 | ||
fdfde340 | 12062 | if (Rn != Rm) |
728ca7c9 PB |
12063 | narrow = FALSE; |
12064 | ||
12065 | switch (inst.operands[1].shift_kind) | |
12066 | { | |
12067 | case SHIFT_LSL: | |
12068 | opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); | |
12069 | break; | |
12070 | case SHIFT_ASR: | |
12071 | opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); | |
12072 | break; | |
12073 | case SHIFT_LSR: | |
12074 | opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); | |
12075 | break; | |
12076 | case SHIFT_ROR: | |
12077 | opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); | |
12078 | break; | |
12079 | default: | |
5f4273c7 | 12080 | abort (); |
728ca7c9 PB |
12081 | } |
12082 | ||
12083 | inst.instruction = opcode; | |
12084 | if (narrow) | |
12085 | { | |
fdfde340 | 12086 | inst.instruction |= Rn; |
728ca7c9 PB |
12087 | inst.instruction |= inst.operands[1].imm << 3; |
12088 | } | |
12089 | else | |
12090 | { | |
12091 | if (flags) | |
12092 | inst.instruction |= CONDS_BIT; | |
12093 | ||
fdfde340 JM |
12094 | inst.instruction |= Rn << 8; |
12095 | inst.instruction |= Rm << 16; | |
728ca7c9 PB |
12096 | inst.instruction |= inst.operands[1].imm; |
12097 | } | |
12098 | } | |
3d388997 | 12099 | else if (!narrow) |
c19d1205 | 12100 | { |
728ca7c9 PB |
12101 | /* Some mov with immediate shift have narrow variants. |
12102 | Register shifts are handled above. */ | |
12103 | if (low_regs && inst.operands[1].shifted | |
12104 | && (inst.instruction == T_MNEM_mov | |
12105 | || inst.instruction == T_MNEM_movs)) | |
12106 | { | |
e07e6e58 | 12107 | if (in_it_block ()) |
728ca7c9 PB |
12108 | narrow = (inst.instruction == T_MNEM_mov); |
12109 | else | |
12110 | narrow = (inst.instruction == T_MNEM_movs); | |
12111 | } | |
12112 | ||
12113 | if (narrow) | |
12114 | { | |
12115 | switch (inst.operands[1].shift_kind) | |
12116 | { | |
12117 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
12118 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
12119 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; | |
12120 | default: narrow = FALSE; break; | |
12121 | } | |
12122 | } | |
12123 | ||
12124 | if (narrow) | |
12125 | { | |
fdfde340 JM |
12126 | inst.instruction |= Rn; |
12127 | inst.instruction |= Rm << 3; | |
728ca7c9 PB |
12128 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
12129 | } | |
12130 | else | |
12131 | { | |
12132 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 12133 | inst.instruction |= Rn << r0off; |
728ca7c9 PB |
12134 | encode_thumb32_shifted_operand (1); |
12135 | } | |
c19d1205 ZW |
12136 | } |
12137 | else | |
12138 | switch (inst.instruction) | |
12139 | { | |
12140 | case T_MNEM_mov: | |
837b3435 | 12141 | /* In v4t or v5t a move of two lowregs produces unpredictable |
c6400f8a MGD |
12142 | results. Don't allow this. */ |
12143 | if (low_regs) | |
12144 | { | |
12145 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6), | |
12146 | "MOV Rd, Rs with two low registers is not " | |
12147 | "permitted on this architecture"); | |
fa94de6b | 12148 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
c6400f8a MGD |
12149 | arm_ext_v6); |
12150 | } | |
12151 | ||
c19d1205 | 12152 | inst.instruction = T_OPCODE_MOV_HR; |
fdfde340 JM |
12153 | inst.instruction |= (Rn & 0x8) << 4; |
12154 | inst.instruction |= (Rn & 0x7); | |
12155 | inst.instruction |= Rm << 3; | |
c19d1205 | 12156 | break; |
b99bd4ef | 12157 | |
c19d1205 ZW |
12158 | case T_MNEM_movs: |
12159 | /* We know we have low registers at this point. | |
941a8a52 MGD |
12160 | Generate LSLS Rd, Rs, #0. */ |
12161 | inst.instruction = T_OPCODE_LSL_I; | |
fdfde340 JM |
12162 | inst.instruction |= Rn; |
12163 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
12164 | break; |
12165 | ||
12166 | case T_MNEM_cmp: | |
3d388997 | 12167 | if (low_regs) |
c19d1205 ZW |
12168 | { |
12169 | inst.instruction = T_OPCODE_CMP_LR; | |
fdfde340 JM |
12170 | inst.instruction |= Rn; |
12171 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
12172 | } |
12173 | else | |
12174 | { | |
12175 | inst.instruction = T_OPCODE_CMP_HR; | |
fdfde340 JM |
12176 | inst.instruction |= (Rn & 0x8) << 4; |
12177 | inst.instruction |= (Rn & 0x7); | |
12178 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
12179 | } |
12180 | break; | |
12181 | } | |
b99bd4ef NC |
12182 | return; |
12183 | } | |
12184 | ||
c19d1205 | 12185 | inst.instruction = THUMB_OP16 (inst.instruction); |
539d4391 NC |
12186 | |
12187 | /* PR 10443: Do not silently ignore shifted operands. */ | |
12188 | constraint (inst.operands[1].shifted, | |
12189 | _("shifts in CMP/MOV instructions are only supported in unified syntax")); | |
12190 | ||
c19d1205 | 12191 | if (inst.operands[1].isreg) |
b99bd4ef | 12192 | { |
fdfde340 | 12193 | if (Rn < 8 && Rm < 8) |
b99bd4ef | 12194 | { |
c19d1205 ZW |
12195 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
12196 | since a MOV instruction produces unpredictable results. */ | |
12197 | if (inst.instruction == T_OPCODE_MOV_I8) | |
12198 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 12199 | else |
c19d1205 | 12200 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 12201 | |
fdfde340 JM |
12202 | inst.instruction |= Rn; |
12203 | inst.instruction |= Rm << 3; | |
b99bd4ef NC |
12204 | } |
12205 | else | |
12206 | { | |
c19d1205 ZW |
12207 | if (inst.instruction == T_OPCODE_MOV_I8) |
12208 | inst.instruction = T_OPCODE_MOV_HR; | |
12209 | else | |
12210 | inst.instruction = T_OPCODE_CMP_HR; | |
12211 | do_t_cpy (); | |
b99bd4ef NC |
12212 | } |
12213 | } | |
c19d1205 | 12214 | else |
b99bd4ef | 12215 | { |
fdfde340 | 12216 | constraint (Rn > 7, |
c19d1205 | 12217 | _("only lo regs allowed with immediate")); |
fdfde340 | 12218 | inst.instruction |= Rn << 8; |
c19d1205 ZW |
12219 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; |
12220 | } | |
12221 | } | |
b99bd4ef | 12222 | |
c19d1205 ZW |
12223 | static void |
12224 | do_t_mov16 (void) | |
12225 | { | |
fdfde340 | 12226 | unsigned Rd; |
b6895b4f PB |
12227 | bfd_vma imm; |
12228 | bfd_boolean top; | |
12229 | ||
12230 | top = (inst.instruction & 0x00800000) != 0; | |
12231 | if (inst.reloc.type == BFD_RELOC_ARM_MOVW) | |
12232 | { | |
33eaf5de | 12233 | constraint (top, _(":lower16: not allowed in this instruction")); |
b6895b4f PB |
12234 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; |
12235 | } | |
12236 | else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) | |
12237 | { | |
33eaf5de | 12238 | constraint (!top, _(":upper16: not allowed in this instruction")); |
b6895b4f PB |
12239 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; |
12240 | } | |
12241 | ||
fdfde340 JM |
12242 | Rd = inst.operands[0].reg; |
12243 | reject_bad_reg (Rd); | |
12244 | ||
12245 | inst.instruction |= Rd << 8; | |
b6895b4f PB |
12246 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
12247 | { | |
12248 | imm = inst.reloc.exp.X_add_number; | |
12249 | inst.instruction |= (imm & 0xf000) << 4; | |
12250 | inst.instruction |= (imm & 0x0800) << 15; | |
12251 | inst.instruction |= (imm & 0x0700) << 4; | |
12252 | inst.instruction |= (imm & 0x00ff); | |
12253 | } | |
c19d1205 | 12254 | } |
b99bd4ef | 12255 | |
c19d1205 ZW |
12256 | static void |
12257 | do_t_mvn_tst (void) | |
12258 | { | |
fdfde340 | 12259 | unsigned Rn, Rm; |
c921be7d | 12260 | |
fdfde340 JM |
12261 | Rn = inst.operands[0].reg; |
12262 | Rm = inst.operands[1].reg; | |
12263 | ||
12264 | if (inst.instruction == T_MNEM_cmp | |
12265 | || inst.instruction == T_MNEM_cmn) | |
12266 | constraint (Rn == REG_PC, BAD_PC); | |
12267 | else | |
12268 | reject_bad_reg (Rn); | |
12269 | reject_bad_reg (Rm); | |
12270 | ||
c19d1205 ZW |
12271 | if (unified_syntax) |
12272 | { | |
12273 | int r0off = (inst.instruction == T_MNEM_mvn | |
12274 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
12275 | bfd_boolean narrow; |
12276 | ||
12277 | if (inst.size_req == 4 | |
12278 | || inst.instruction > 0xffff | |
12279 | || inst.operands[1].shifted | |
fdfde340 | 12280 | || Rn > 7 || Rm > 7) |
3d388997 | 12281 | narrow = FALSE; |
fe8b4cc3 KT |
12282 | else if (inst.instruction == T_MNEM_cmn |
12283 | || inst.instruction == T_MNEM_tst) | |
3d388997 PB |
12284 | narrow = TRUE; |
12285 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 12286 | narrow = !in_it_block (); |
3d388997 | 12287 | else |
e07e6e58 | 12288 | narrow = in_it_block (); |
3d388997 | 12289 | |
c19d1205 | 12290 | if (!inst.operands[1].isreg) |
b99bd4ef | 12291 | { |
c19d1205 ZW |
12292 | /* For an immediate, we always generate a 32-bit opcode; |
12293 | section relaxation will shrink it later if possible. */ | |
12294 | if (inst.instruction < 0xffff) | |
12295 | inst.instruction = THUMB_OP32 (inst.instruction); | |
12296 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 12297 | inst.instruction |= Rn << r0off; |
c19d1205 | 12298 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
b99bd4ef | 12299 | } |
c19d1205 | 12300 | else |
b99bd4ef | 12301 | { |
c19d1205 | 12302 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 12303 | if (narrow) |
b99bd4ef | 12304 | { |
c19d1205 | 12305 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
12306 | inst.instruction |= Rn; |
12307 | inst.instruction |= Rm << 3; | |
b99bd4ef | 12308 | } |
c19d1205 | 12309 | else |
b99bd4ef | 12310 | { |
c19d1205 ZW |
12311 | constraint (inst.operands[1].shifted |
12312 | && inst.operands[1].immisreg, | |
12313 | _("shift must be constant")); | |
12314 | if (inst.instruction < 0xffff) | |
12315 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 12316 | inst.instruction |= Rn << r0off; |
c19d1205 | 12317 | encode_thumb32_shifted_operand (1); |
b99bd4ef | 12318 | } |
b99bd4ef NC |
12319 | } |
12320 | } | |
12321 | else | |
12322 | { | |
c19d1205 ZW |
12323 | constraint (inst.instruction > 0xffff |
12324 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
12325 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
12326 | _("unshifted register required")); | |
fdfde340 | 12327 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 12328 | BAD_HIREG); |
b99bd4ef | 12329 | |
c19d1205 | 12330 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
12331 | inst.instruction |= Rn; |
12332 | inst.instruction |= Rm << 3; | |
b99bd4ef | 12333 | } |
b99bd4ef NC |
12334 | } |
12335 | ||
b05fe5cf | 12336 | static void |
c19d1205 | 12337 | do_t_mrs (void) |
b05fe5cf | 12338 | { |
fdfde340 | 12339 | unsigned Rd; |
037e8744 JB |
12340 | |
12341 | if (do_vfp_nsyn_mrs () == SUCCESS) | |
12342 | return; | |
12343 | ||
90ec0d68 MGD |
12344 | Rd = inst.operands[0].reg; |
12345 | reject_bad_reg (Rd); | |
12346 | inst.instruction |= Rd << 8; | |
12347 | ||
12348 | if (inst.operands[1].isreg) | |
62b3e311 | 12349 | { |
90ec0d68 MGD |
12350 | unsigned br = inst.operands[1].reg; |
12351 | if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000)) | |
12352 | as_bad (_("bad register for mrs")); | |
12353 | ||
12354 | inst.instruction |= br & (0xf << 16); | |
12355 | inst.instruction |= (br & 0x300) >> 4; | |
12356 | inst.instruction |= (br & SPSR_BIT) >> 2; | |
62b3e311 PB |
12357 | } |
12358 | else | |
12359 | { | |
90ec0d68 | 12360 | int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
5f4273c7 | 12361 | |
d2cd1205 | 12362 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
1a43faaf NC |
12363 | { |
12364 | /* PR gas/12698: The constraint is only applied for m_profile. | |
12365 | If the user has specified -march=all, we want to ignore it as | |
12366 | we are building for any CPU type, including non-m variants. */ | |
823d2571 TG |
12367 | bfd_boolean m_profile = |
12368 | !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any); | |
1a43faaf NC |
12369 | constraint ((flags != 0) && m_profile, _("selected processor does " |
12370 | "not support requested special purpose register")); | |
12371 | } | |
90ec0d68 | 12372 | else |
d2cd1205 JB |
12373 | /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile |
12374 | devices). */ | |
12375 | constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), | |
12376 | _("'APSR', 'CPSR' or 'SPSR' expected")); | |
fdfde340 | 12377 | |
90ec0d68 MGD |
12378 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
12379 | inst.instruction |= inst.operands[1].imm & 0xff; | |
12380 | inst.instruction |= 0xf0000; | |
12381 | } | |
c19d1205 | 12382 | } |
b05fe5cf | 12383 | |
c19d1205 ZW |
12384 | static void |
12385 | do_t_msr (void) | |
12386 | { | |
62b3e311 | 12387 | int flags; |
fdfde340 | 12388 | unsigned Rn; |
62b3e311 | 12389 | |
037e8744 JB |
12390 | if (do_vfp_nsyn_msr () == SUCCESS) |
12391 | return; | |
12392 | ||
c19d1205 ZW |
12393 | constraint (!inst.operands[1].isreg, |
12394 | _("Thumb encoding does not support an immediate here")); | |
90ec0d68 MGD |
12395 | |
12396 | if (inst.operands[0].isreg) | |
12397 | flags = (int)(inst.operands[0].reg); | |
12398 | else | |
12399 | flags = inst.operands[0].imm; | |
12400 | ||
d2cd1205 | 12401 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
62b3e311 | 12402 | { |
d2cd1205 JB |
12403 | int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
12404 | ||
1a43faaf | 12405 | /* PR gas/12698: The constraint is only applied for m_profile. |
477330fc RM |
12406 | If the user has specified -march=all, we want to ignore it as |
12407 | we are building for any CPU type, including non-m variants. */ | |
823d2571 TG |
12408 | bfd_boolean m_profile = |
12409 | !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any); | |
1a43faaf | 12410 | constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) |
477330fc RM |
12411 | && (bits & ~(PSR_s | PSR_f)) != 0) |
12412 | || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) | |
12413 | && bits != PSR_f)) && m_profile, | |
12414 | _("selected processor does not support requested special " | |
12415 | "purpose register")); | |
62b3e311 PB |
12416 | } |
12417 | else | |
d2cd1205 JB |
12418 | constraint ((flags & 0xff) != 0, _("selected processor does not support " |
12419 | "requested special purpose register")); | |
c921be7d | 12420 | |
fdfde340 JM |
12421 | Rn = inst.operands[1].reg; |
12422 | reject_bad_reg (Rn); | |
12423 | ||
62b3e311 | 12424 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
90ec0d68 MGD |
12425 | inst.instruction |= (flags & 0xf0000) >> 8; |
12426 | inst.instruction |= (flags & 0x300) >> 4; | |
62b3e311 | 12427 | inst.instruction |= (flags & 0xff); |
fdfde340 | 12428 | inst.instruction |= Rn << 16; |
c19d1205 | 12429 | } |
b05fe5cf | 12430 | |
c19d1205 ZW |
12431 | static void |
12432 | do_t_mul (void) | |
12433 | { | |
17828f45 | 12434 | bfd_boolean narrow; |
fdfde340 | 12435 | unsigned Rd, Rn, Rm; |
17828f45 | 12436 | |
c19d1205 ZW |
12437 | if (!inst.operands[2].present) |
12438 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 12439 | |
fdfde340 JM |
12440 | Rd = inst.operands[0].reg; |
12441 | Rn = inst.operands[1].reg; | |
12442 | Rm = inst.operands[2].reg; | |
12443 | ||
17828f45 | 12444 | if (unified_syntax) |
b05fe5cf | 12445 | { |
17828f45 | 12446 | if (inst.size_req == 4 |
fdfde340 JM |
12447 | || (Rd != Rn |
12448 | && Rd != Rm) | |
12449 | || Rn > 7 | |
12450 | || Rm > 7) | |
17828f45 JM |
12451 | narrow = FALSE; |
12452 | else if (inst.instruction == T_MNEM_muls) | |
e07e6e58 | 12453 | narrow = !in_it_block (); |
17828f45 | 12454 | else |
e07e6e58 | 12455 | narrow = in_it_block (); |
b05fe5cf | 12456 | } |
c19d1205 | 12457 | else |
b05fe5cf | 12458 | { |
17828f45 | 12459 | constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); |
fdfde340 | 12460 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 12461 | BAD_HIREG); |
17828f45 JM |
12462 | narrow = TRUE; |
12463 | } | |
b05fe5cf | 12464 | |
17828f45 JM |
12465 | if (narrow) |
12466 | { | |
12467 | /* 16-bit MULS/Conditional MUL. */ | |
c19d1205 | 12468 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 | 12469 | inst.instruction |= Rd; |
b05fe5cf | 12470 | |
fdfde340 JM |
12471 | if (Rd == Rn) |
12472 | inst.instruction |= Rm << 3; | |
12473 | else if (Rd == Rm) | |
12474 | inst.instruction |= Rn << 3; | |
c19d1205 ZW |
12475 | else |
12476 | constraint (1, _("dest must overlap one source register")); | |
12477 | } | |
17828f45 JM |
12478 | else |
12479 | { | |
e07e6e58 NC |
12480 | constraint (inst.instruction != T_MNEM_mul, |
12481 | _("Thumb-2 MUL must not set flags")); | |
17828f45 JM |
12482 | /* 32-bit MUL. */ |
12483 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
12484 | inst.instruction |= Rd << 8; |
12485 | inst.instruction |= Rn << 16; | |
12486 | inst.instruction |= Rm << 0; | |
12487 | ||
12488 | reject_bad_reg (Rd); | |
12489 | reject_bad_reg (Rn); | |
12490 | reject_bad_reg (Rm); | |
17828f45 | 12491 | } |
c19d1205 | 12492 | } |
b05fe5cf | 12493 | |
c19d1205 ZW |
12494 | static void |
12495 | do_t_mull (void) | |
12496 | { | |
fdfde340 | 12497 | unsigned RdLo, RdHi, Rn, Rm; |
b05fe5cf | 12498 | |
fdfde340 JM |
12499 | RdLo = inst.operands[0].reg; |
12500 | RdHi = inst.operands[1].reg; | |
12501 | Rn = inst.operands[2].reg; | |
12502 | Rm = inst.operands[3].reg; | |
12503 | ||
12504 | reject_bad_reg (RdLo); | |
12505 | reject_bad_reg (RdHi); | |
12506 | reject_bad_reg (Rn); | |
12507 | reject_bad_reg (Rm); | |
12508 | ||
12509 | inst.instruction |= RdLo << 12; | |
12510 | inst.instruction |= RdHi << 8; | |
12511 | inst.instruction |= Rn << 16; | |
12512 | inst.instruction |= Rm; | |
12513 | ||
12514 | if (RdLo == RdHi) | |
c19d1205 ZW |
12515 | as_tsktsk (_("rdhi and rdlo must be different")); |
12516 | } | |
b05fe5cf | 12517 | |
c19d1205 ZW |
12518 | static void |
12519 | do_t_nop (void) | |
12520 | { | |
e07e6e58 NC |
12521 | set_it_insn_type (NEUTRAL_IT_INSN); |
12522 | ||
c19d1205 ZW |
12523 | if (unified_syntax) |
12524 | { | |
12525 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 12526 | { |
c19d1205 ZW |
12527 | inst.instruction = THUMB_OP32 (inst.instruction); |
12528 | inst.instruction |= inst.operands[0].imm; | |
12529 | } | |
12530 | else | |
12531 | { | |
bc2d1808 NC |
12532 | /* PR9722: Check for Thumb2 availability before |
12533 | generating a thumb2 nop instruction. */ | |
afa62d5e | 12534 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
bc2d1808 NC |
12535 | { |
12536 | inst.instruction = THUMB_OP16 (inst.instruction); | |
12537 | inst.instruction |= inst.operands[0].imm << 4; | |
12538 | } | |
12539 | else | |
12540 | inst.instruction = 0x46c0; | |
c19d1205 ZW |
12541 | } |
12542 | } | |
12543 | else | |
12544 | { | |
12545 | constraint (inst.operands[0].present, | |
12546 | _("Thumb does not support NOP with hints")); | |
12547 | inst.instruction = 0x46c0; | |
12548 | } | |
12549 | } | |
b05fe5cf | 12550 | |
c19d1205 ZW |
12551 | static void |
12552 | do_t_neg (void) | |
12553 | { | |
12554 | if (unified_syntax) | |
12555 | { | |
3d388997 PB |
12556 | bfd_boolean narrow; |
12557 | ||
12558 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 12559 | narrow = !in_it_block (); |
3d388997 | 12560 | else |
e07e6e58 | 12561 | narrow = in_it_block (); |
3d388997 PB |
12562 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
12563 | narrow = FALSE; | |
12564 | if (inst.size_req == 4) | |
12565 | narrow = FALSE; | |
12566 | ||
12567 | if (!narrow) | |
c19d1205 ZW |
12568 | { |
12569 | inst.instruction = THUMB_OP32 (inst.instruction); | |
12570 | inst.instruction |= inst.operands[0].reg << 8; | |
12571 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
12572 | } |
12573 | else | |
12574 | { | |
c19d1205 ZW |
12575 | inst.instruction = THUMB_OP16 (inst.instruction); |
12576 | inst.instruction |= inst.operands[0].reg; | |
12577 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
12578 | } |
12579 | } | |
12580 | else | |
12581 | { | |
c19d1205 ZW |
12582 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
12583 | BAD_HIREG); | |
12584 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
12585 | ||
12586 | inst.instruction = THUMB_OP16 (inst.instruction); | |
12587 | inst.instruction |= inst.operands[0].reg; | |
12588 | inst.instruction |= inst.operands[1].reg << 3; | |
12589 | } | |
12590 | } | |
12591 | ||
1c444d06 JM |
12592 | static void |
12593 | do_t_orn (void) | |
12594 | { | |
12595 | unsigned Rd, Rn; | |
12596 | ||
12597 | Rd = inst.operands[0].reg; | |
12598 | Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; | |
12599 | ||
fdfde340 JM |
12600 | reject_bad_reg (Rd); |
12601 | /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ | |
12602 | reject_bad_reg (Rn); | |
12603 | ||
1c444d06 JM |
12604 | inst.instruction |= Rd << 8; |
12605 | inst.instruction |= Rn << 16; | |
12606 | ||
12607 | if (!inst.operands[2].isreg) | |
12608 | { | |
12609 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
12610 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
12611 | } | |
12612 | else | |
12613 | { | |
12614 | unsigned Rm; | |
12615 | ||
12616 | Rm = inst.operands[2].reg; | |
fdfde340 | 12617 | reject_bad_reg (Rm); |
1c444d06 JM |
12618 | |
12619 | constraint (inst.operands[2].shifted | |
12620 | && inst.operands[2].immisreg, | |
12621 | _("shift must be constant")); | |
12622 | encode_thumb32_shifted_operand (2); | |
12623 | } | |
12624 | } | |
12625 | ||
c19d1205 ZW |
12626 | static void |
12627 | do_t_pkhbt (void) | |
12628 | { | |
fdfde340 JM |
12629 | unsigned Rd, Rn, Rm; |
12630 | ||
12631 | Rd = inst.operands[0].reg; | |
12632 | Rn = inst.operands[1].reg; | |
12633 | Rm = inst.operands[2].reg; | |
12634 | ||
12635 | reject_bad_reg (Rd); | |
12636 | reject_bad_reg (Rn); | |
12637 | reject_bad_reg (Rm); | |
12638 | ||
12639 | inst.instruction |= Rd << 8; | |
12640 | inst.instruction |= Rn << 16; | |
12641 | inst.instruction |= Rm; | |
c19d1205 ZW |
12642 | if (inst.operands[3].present) |
12643 | { | |
12644 | unsigned int val = inst.reloc.exp.X_add_number; | |
12645 | constraint (inst.reloc.exp.X_op != O_constant, | |
12646 | _("expression too complex")); | |
12647 | inst.instruction |= (val & 0x1c) << 10; | |
12648 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 12649 | } |
c19d1205 | 12650 | } |
b05fe5cf | 12651 | |
c19d1205 ZW |
12652 | static void |
12653 | do_t_pkhtb (void) | |
12654 | { | |
12655 | if (!inst.operands[3].present) | |
1ef52f49 NC |
12656 | { |
12657 | unsigned Rtmp; | |
12658 | ||
12659 | inst.instruction &= ~0x00000020; | |
12660 | ||
12661 | /* PR 10168. Swap the Rm and Rn registers. */ | |
12662 | Rtmp = inst.operands[1].reg; | |
12663 | inst.operands[1].reg = inst.operands[2].reg; | |
12664 | inst.operands[2].reg = Rtmp; | |
12665 | } | |
c19d1205 | 12666 | do_t_pkhbt (); |
b05fe5cf ZW |
12667 | } |
12668 | ||
c19d1205 ZW |
12669 | static void |
12670 | do_t_pld (void) | |
12671 | { | |
fdfde340 JM |
12672 | if (inst.operands[0].immisreg) |
12673 | reject_bad_reg (inst.operands[0].imm); | |
12674 | ||
c19d1205 ZW |
12675 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); |
12676 | } | |
b05fe5cf | 12677 | |
c19d1205 ZW |
12678 | static void |
12679 | do_t_push_pop (void) | |
b99bd4ef | 12680 | { |
e9f89963 | 12681 | unsigned mask; |
5f4273c7 | 12682 | |
c19d1205 ZW |
12683 | constraint (inst.operands[0].writeback, |
12684 | _("push/pop do not support {reglist}^")); | |
12685 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
12686 | _("expression too complex")); | |
b99bd4ef | 12687 | |
e9f89963 | 12688 | mask = inst.operands[0].imm; |
d3bfe16e | 12689 | if (inst.size_req != 4 && (mask & ~0xff) == 0) |
3c707909 | 12690 | inst.instruction = THUMB_OP16 (inst.instruction) | mask; |
d3bfe16e | 12691 | else if (inst.size_req != 4 |
c6025a80 | 12692 | && (mask & ~0xff) == (1U << (inst.instruction == T_MNEM_push |
d3bfe16e | 12693 | ? REG_LR : REG_PC))) |
b99bd4ef | 12694 | { |
c19d1205 ZW |
12695 | inst.instruction = THUMB_OP16 (inst.instruction); |
12696 | inst.instruction |= THUMB_PP_PC_LR; | |
3c707909 | 12697 | inst.instruction |= mask & 0xff; |
c19d1205 ZW |
12698 | } |
12699 | else if (unified_syntax) | |
12700 | { | |
3c707909 | 12701 | inst.instruction = THUMB_OP32 (inst.instruction); |
5f4273c7 | 12702 | encode_thumb2_ldmstm (13, mask, TRUE); |
c19d1205 ZW |
12703 | } |
12704 | else | |
12705 | { | |
12706 | inst.error = _("invalid register list to push/pop instruction"); | |
12707 | return; | |
12708 | } | |
c19d1205 | 12709 | } |
b99bd4ef | 12710 | |
c19d1205 ZW |
12711 | static void |
12712 | do_t_rbit (void) | |
12713 | { | |
fdfde340 JM |
12714 | unsigned Rd, Rm; |
12715 | ||
12716 | Rd = inst.operands[0].reg; | |
12717 | Rm = inst.operands[1].reg; | |
12718 | ||
12719 | reject_bad_reg (Rd); | |
12720 | reject_bad_reg (Rm); | |
12721 | ||
12722 | inst.instruction |= Rd << 8; | |
12723 | inst.instruction |= Rm << 16; | |
12724 | inst.instruction |= Rm; | |
c19d1205 | 12725 | } |
b99bd4ef | 12726 | |
c19d1205 ZW |
12727 | static void |
12728 | do_t_rev (void) | |
12729 | { | |
fdfde340 JM |
12730 | unsigned Rd, Rm; |
12731 | ||
12732 | Rd = inst.operands[0].reg; | |
12733 | Rm = inst.operands[1].reg; | |
12734 | ||
12735 | reject_bad_reg (Rd); | |
12736 | reject_bad_reg (Rm); | |
12737 | ||
12738 | if (Rd <= 7 && Rm <= 7 | |
c19d1205 ZW |
12739 | && inst.size_req != 4) |
12740 | { | |
12741 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 JM |
12742 | inst.instruction |= Rd; |
12743 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
12744 | } |
12745 | else if (unified_syntax) | |
12746 | { | |
12747 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
12748 | inst.instruction |= Rd << 8; |
12749 | inst.instruction |= Rm << 16; | |
12750 | inst.instruction |= Rm; | |
c19d1205 ZW |
12751 | } |
12752 | else | |
12753 | inst.error = BAD_HIREG; | |
12754 | } | |
b99bd4ef | 12755 | |
1c444d06 JM |
12756 | static void |
12757 | do_t_rrx (void) | |
12758 | { | |
12759 | unsigned Rd, Rm; | |
12760 | ||
12761 | Rd = inst.operands[0].reg; | |
12762 | Rm = inst.operands[1].reg; | |
12763 | ||
fdfde340 JM |
12764 | reject_bad_reg (Rd); |
12765 | reject_bad_reg (Rm); | |
c921be7d | 12766 | |
1c444d06 JM |
12767 | inst.instruction |= Rd << 8; |
12768 | inst.instruction |= Rm; | |
12769 | } | |
12770 | ||
c19d1205 ZW |
12771 | static void |
12772 | do_t_rsb (void) | |
12773 | { | |
fdfde340 | 12774 | unsigned Rd, Rs; |
b99bd4ef | 12775 | |
c19d1205 ZW |
12776 | Rd = inst.operands[0].reg; |
12777 | Rs = (inst.operands[1].present | |
12778 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
12779 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 12780 | |
fdfde340 JM |
12781 | reject_bad_reg (Rd); |
12782 | reject_bad_reg (Rs); | |
12783 | if (inst.operands[2].isreg) | |
12784 | reject_bad_reg (inst.operands[2].reg); | |
12785 | ||
c19d1205 ZW |
12786 | inst.instruction |= Rd << 8; |
12787 | inst.instruction |= Rs << 16; | |
12788 | if (!inst.operands[2].isreg) | |
12789 | { | |
026d3abb PB |
12790 | bfd_boolean narrow; |
12791 | ||
12792 | if ((inst.instruction & 0x00100000) != 0) | |
e07e6e58 | 12793 | narrow = !in_it_block (); |
026d3abb | 12794 | else |
e07e6e58 | 12795 | narrow = in_it_block (); |
026d3abb PB |
12796 | |
12797 | if (Rd > 7 || Rs > 7) | |
12798 | narrow = FALSE; | |
12799 | ||
12800 | if (inst.size_req == 4 || !unified_syntax) | |
12801 | narrow = FALSE; | |
12802 | ||
12803 | if (inst.reloc.exp.X_op != O_constant | |
12804 | || inst.reloc.exp.X_add_number != 0) | |
12805 | narrow = FALSE; | |
12806 | ||
12807 | /* Turn rsb #0 into 16-bit neg. We should probably do this via | |
477330fc | 12808 | relaxation, but it doesn't seem worth the hassle. */ |
026d3abb PB |
12809 | if (narrow) |
12810 | { | |
12811 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12812 | inst.instruction = THUMB_OP16 (T_MNEM_negs); | |
12813 | inst.instruction |= Rs << 3; | |
12814 | inst.instruction |= Rd; | |
12815 | } | |
12816 | else | |
12817 | { | |
12818 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
12819 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
12820 | } | |
c19d1205 ZW |
12821 | } |
12822 | else | |
12823 | encode_thumb32_shifted_operand (2); | |
12824 | } | |
b99bd4ef | 12825 | |
c19d1205 ZW |
12826 | static void |
12827 | do_t_setend (void) | |
12828 | { | |
12e37cbc MGD |
12829 | if (warn_on_deprecated |
12830 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
5c3696f8 | 12831 | as_tsktsk (_("setend use is deprecated for ARMv8")); |
12e37cbc | 12832 | |
e07e6e58 | 12833 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
12834 | if (inst.operands[0].imm) |
12835 | inst.instruction |= 0x8; | |
12836 | } | |
b99bd4ef | 12837 | |
c19d1205 ZW |
12838 | static void |
12839 | do_t_shift (void) | |
12840 | { | |
12841 | if (!inst.operands[1].present) | |
12842 | inst.operands[1].reg = inst.operands[0].reg; | |
12843 | ||
12844 | if (unified_syntax) | |
12845 | { | |
3d388997 PB |
12846 | bfd_boolean narrow; |
12847 | int shift_kind; | |
12848 | ||
12849 | switch (inst.instruction) | |
12850 | { | |
12851 | case T_MNEM_asr: | |
12852 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
12853 | case T_MNEM_lsl: | |
12854 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
12855 | case T_MNEM_lsr: | |
12856 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
12857 | case T_MNEM_ror: | |
12858 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
12859 | default: abort (); | |
12860 | } | |
12861 | ||
12862 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 12863 | narrow = !in_it_block (); |
3d388997 | 12864 | else |
e07e6e58 | 12865 | narrow = in_it_block (); |
3d388997 PB |
12866 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
12867 | narrow = FALSE; | |
12868 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
12869 | narrow = FALSE; | |
12870 | if (inst.operands[2].isreg | |
12871 | && (inst.operands[1].reg != inst.operands[0].reg | |
12872 | || inst.operands[2].reg > 7)) | |
12873 | narrow = FALSE; | |
12874 | if (inst.size_req == 4) | |
12875 | narrow = FALSE; | |
12876 | ||
fdfde340 JM |
12877 | reject_bad_reg (inst.operands[0].reg); |
12878 | reject_bad_reg (inst.operands[1].reg); | |
c921be7d | 12879 | |
3d388997 | 12880 | if (!narrow) |
c19d1205 ZW |
12881 | { |
12882 | if (inst.operands[2].isreg) | |
b99bd4ef | 12883 | { |
fdfde340 | 12884 | reject_bad_reg (inst.operands[2].reg); |
c19d1205 ZW |
12885 | inst.instruction = THUMB_OP32 (inst.instruction); |
12886 | inst.instruction |= inst.operands[0].reg << 8; | |
12887 | inst.instruction |= inst.operands[1].reg << 16; | |
12888 | inst.instruction |= inst.operands[2].reg; | |
94342ec3 NC |
12889 | |
12890 | /* PR 12854: Error on extraneous shifts. */ | |
12891 | constraint (inst.operands[2].shifted, | |
12892 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
12893 | } |
12894 | else | |
12895 | { | |
12896 | inst.operands[1].shifted = 1; | |
3d388997 | 12897 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
12898 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
12899 | ? T_MNEM_movs : T_MNEM_mov); | |
12900 | inst.instruction |= inst.operands[0].reg << 8; | |
12901 | encode_thumb32_shifted_operand (1); | |
12902 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
12903 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef NC |
12904 | } |
12905 | } | |
12906 | else | |
12907 | { | |
c19d1205 | 12908 | if (inst.operands[2].isreg) |
b99bd4ef | 12909 | { |
3d388997 | 12910 | switch (shift_kind) |
b99bd4ef | 12911 | { |
3d388997 PB |
12912 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
12913 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
12914 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
12915 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 12916 | default: abort (); |
b99bd4ef | 12917 | } |
5f4273c7 | 12918 | |
c19d1205 ZW |
12919 | inst.instruction |= inst.operands[0].reg; |
12920 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
12921 | |
12922 | /* PR 12854: Error on extraneous shifts. */ | |
12923 | constraint (inst.operands[2].shifted, | |
12924 | _("extraneous shift as part of operand to shift insn")); | |
b99bd4ef NC |
12925 | } |
12926 | else | |
12927 | { | |
3d388997 | 12928 | switch (shift_kind) |
b99bd4ef | 12929 | { |
3d388997 PB |
12930 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
12931 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
12932 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 12933 | default: abort (); |
b99bd4ef | 12934 | } |
c19d1205 ZW |
12935 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
12936 | inst.instruction |= inst.operands[0].reg; | |
12937 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
12938 | } |
12939 | } | |
c19d1205 ZW |
12940 | } |
12941 | else | |
12942 | { | |
12943 | constraint (inst.operands[0].reg > 7 | |
12944 | || inst.operands[1].reg > 7, BAD_HIREG); | |
12945 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 12946 | |
c19d1205 ZW |
12947 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
12948 | { | |
12949 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
12950 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
12951 | _("source1 and dest must be same register")); | |
b99bd4ef | 12952 | |
c19d1205 ZW |
12953 | switch (inst.instruction) |
12954 | { | |
12955 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
12956 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
12957 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
12958 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
12959 | default: abort (); | |
12960 | } | |
5f4273c7 | 12961 | |
c19d1205 ZW |
12962 | inst.instruction |= inst.operands[0].reg; |
12963 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
12964 | |
12965 | /* PR 12854: Error on extraneous shifts. */ | |
12966 | constraint (inst.operands[2].shifted, | |
12967 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
12968 | } |
12969 | else | |
b99bd4ef | 12970 | { |
c19d1205 ZW |
12971 | switch (inst.instruction) |
12972 | { | |
12973 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
12974 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
12975 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
12976 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
12977 | default: abort (); | |
12978 | } | |
12979 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
12980 | inst.instruction |= inst.operands[0].reg; | |
12981 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
12982 | } |
12983 | } | |
b99bd4ef NC |
12984 | } |
12985 | ||
12986 | static void | |
c19d1205 | 12987 | do_t_simd (void) |
b99bd4ef | 12988 | { |
fdfde340 JM |
12989 | unsigned Rd, Rn, Rm; |
12990 | ||
12991 | Rd = inst.operands[0].reg; | |
12992 | Rn = inst.operands[1].reg; | |
12993 | Rm = inst.operands[2].reg; | |
12994 | ||
12995 | reject_bad_reg (Rd); | |
12996 | reject_bad_reg (Rn); | |
12997 | reject_bad_reg (Rm); | |
12998 | ||
12999 | inst.instruction |= Rd << 8; | |
13000 | inst.instruction |= Rn << 16; | |
13001 | inst.instruction |= Rm; | |
c19d1205 | 13002 | } |
b99bd4ef | 13003 | |
03ee1b7f NC |
13004 | static void |
13005 | do_t_simd2 (void) | |
13006 | { | |
13007 | unsigned Rd, Rn, Rm; | |
13008 | ||
13009 | Rd = inst.operands[0].reg; | |
13010 | Rm = inst.operands[1].reg; | |
13011 | Rn = inst.operands[2].reg; | |
13012 | ||
13013 | reject_bad_reg (Rd); | |
13014 | reject_bad_reg (Rn); | |
13015 | reject_bad_reg (Rm); | |
13016 | ||
13017 | inst.instruction |= Rd << 8; | |
13018 | inst.instruction |= Rn << 16; | |
13019 | inst.instruction |= Rm; | |
13020 | } | |
13021 | ||
c19d1205 | 13022 | static void |
3eb17e6b | 13023 | do_t_smc (void) |
c19d1205 ZW |
13024 | { |
13025 | unsigned int value = inst.reloc.exp.X_add_number; | |
f4c65163 MGD |
13026 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a), |
13027 | _("SMC is not permitted on this architecture")); | |
c19d1205 ZW |
13028 | constraint (inst.reloc.exp.X_op != O_constant, |
13029 | _("expression too complex")); | |
13030 | inst.reloc.type = BFD_RELOC_UNUSED; | |
13031 | inst.instruction |= (value & 0xf000) >> 12; | |
13032 | inst.instruction |= (value & 0x0ff0); | |
13033 | inst.instruction |= (value & 0x000f) << 16; | |
24382199 NC |
13034 | /* PR gas/15623: SMC instructions must be last in an IT block. */ |
13035 | set_it_insn_type_last (); | |
c19d1205 | 13036 | } |
b99bd4ef | 13037 | |
90ec0d68 MGD |
13038 | static void |
13039 | do_t_hvc (void) | |
13040 | { | |
13041 | unsigned int value = inst.reloc.exp.X_add_number; | |
13042 | ||
13043 | inst.reloc.type = BFD_RELOC_UNUSED; | |
13044 | inst.instruction |= (value & 0x0fff); | |
13045 | inst.instruction |= (value & 0xf000) << 4; | |
13046 | } | |
13047 | ||
c19d1205 | 13048 | static void |
3a21c15a | 13049 | do_t_ssat_usat (int bias) |
c19d1205 | 13050 | { |
fdfde340 JM |
13051 | unsigned Rd, Rn; |
13052 | ||
13053 | Rd = inst.operands[0].reg; | |
13054 | Rn = inst.operands[2].reg; | |
13055 | ||
13056 | reject_bad_reg (Rd); | |
13057 | reject_bad_reg (Rn); | |
13058 | ||
13059 | inst.instruction |= Rd << 8; | |
3a21c15a | 13060 | inst.instruction |= inst.operands[1].imm - bias; |
fdfde340 | 13061 | inst.instruction |= Rn << 16; |
b99bd4ef | 13062 | |
c19d1205 | 13063 | if (inst.operands[3].present) |
b99bd4ef | 13064 | { |
3a21c15a NC |
13065 | offsetT shift_amount = inst.reloc.exp.X_add_number; |
13066 | ||
13067 | inst.reloc.type = BFD_RELOC_UNUSED; | |
13068 | ||
c19d1205 ZW |
13069 | constraint (inst.reloc.exp.X_op != O_constant, |
13070 | _("expression too complex")); | |
b99bd4ef | 13071 | |
3a21c15a | 13072 | if (shift_amount != 0) |
6189168b | 13073 | { |
3a21c15a NC |
13074 | constraint (shift_amount > 31, |
13075 | _("shift expression is too large")); | |
13076 | ||
c19d1205 | 13077 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
3a21c15a NC |
13078 | inst.instruction |= 0x00200000; /* sh bit. */ |
13079 | ||
13080 | inst.instruction |= (shift_amount & 0x1c) << 10; | |
13081 | inst.instruction |= (shift_amount & 0x03) << 6; | |
6189168b NC |
13082 | } |
13083 | } | |
b99bd4ef | 13084 | } |
c921be7d | 13085 | |
3a21c15a NC |
13086 | static void |
13087 | do_t_ssat (void) | |
13088 | { | |
13089 | do_t_ssat_usat (1); | |
13090 | } | |
b99bd4ef | 13091 | |
0dd132b6 | 13092 | static void |
c19d1205 | 13093 | do_t_ssat16 (void) |
0dd132b6 | 13094 | { |
fdfde340 JM |
13095 | unsigned Rd, Rn; |
13096 | ||
13097 | Rd = inst.operands[0].reg; | |
13098 | Rn = inst.operands[2].reg; | |
13099 | ||
13100 | reject_bad_reg (Rd); | |
13101 | reject_bad_reg (Rn); | |
13102 | ||
13103 | inst.instruction |= Rd << 8; | |
c19d1205 | 13104 | inst.instruction |= inst.operands[1].imm - 1; |
fdfde340 | 13105 | inst.instruction |= Rn << 16; |
c19d1205 | 13106 | } |
0dd132b6 | 13107 | |
c19d1205 ZW |
13108 | static void |
13109 | do_t_strex (void) | |
13110 | { | |
13111 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
13112 | || inst.operands[2].postind || inst.operands[2].writeback | |
13113 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
13114 | || inst.operands[2].negative, | |
01cfc07f | 13115 | BAD_ADDR_MODE); |
0dd132b6 | 13116 | |
5be8be5d DG |
13117 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
13118 | ||
c19d1205 ZW |
13119 | inst.instruction |= inst.operands[0].reg << 8; |
13120 | inst.instruction |= inst.operands[1].reg << 12; | |
13121 | inst.instruction |= inst.operands[2].reg << 16; | |
13122 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
0dd132b6 NC |
13123 | } |
13124 | ||
b99bd4ef | 13125 | static void |
c19d1205 | 13126 | do_t_strexd (void) |
b99bd4ef | 13127 | { |
c19d1205 ZW |
13128 | if (!inst.operands[2].present) |
13129 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 13130 | |
c19d1205 ZW |
13131 | constraint (inst.operands[0].reg == inst.operands[1].reg |
13132 | || inst.operands[0].reg == inst.operands[2].reg | |
f8a8e9d6 | 13133 | || inst.operands[0].reg == inst.operands[3].reg, |
c19d1205 | 13134 | BAD_OVERLAP); |
b99bd4ef | 13135 | |
c19d1205 ZW |
13136 | inst.instruction |= inst.operands[0].reg; |
13137 | inst.instruction |= inst.operands[1].reg << 12; | |
13138 | inst.instruction |= inst.operands[2].reg << 8; | |
13139 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
13140 | } |
13141 | ||
13142 | static void | |
c19d1205 | 13143 | do_t_sxtah (void) |
b99bd4ef | 13144 | { |
fdfde340 JM |
13145 | unsigned Rd, Rn, Rm; |
13146 | ||
13147 | Rd = inst.operands[0].reg; | |
13148 | Rn = inst.operands[1].reg; | |
13149 | Rm = inst.operands[2].reg; | |
13150 | ||
13151 | reject_bad_reg (Rd); | |
13152 | reject_bad_reg (Rn); | |
13153 | reject_bad_reg (Rm); | |
13154 | ||
13155 | inst.instruction |= Rd << 8; | |
13156 | inst.instruction |= Rn << 16; | |
13157 | inst.instruction |= Rm; | |
c19d1205 ZW |
13158 | inst.instruction |= inst.operands[3].imm << 4; |
13159 | } | |
b99bd4ef | 13160 | |
c19d1205 ZW |
13161 | static void |
13162 | do_t_sxth (void) | |
13163 | { | |
fdfde340 JM |
13164 | unsigned Rd, Rm; |
13165 | ||
13166 | Rd = inst.operands[0].reg; | |
13167 | Rm = inst.operands[1].reg; | |
13168 | ||
13169 | reject_bad_reg (Rd); | |
13170 | reject_bad_reg (Rm); | |
c921be7d NC |
13171 | |
13172 | if (inst.instruction <= 0xffff | |
13173 | && inst.size_req != 4 | |
fdfde340 | 13174 | && Rd <= 7 && Rm <= 7 |
c19d1205 | 13175 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) |
b99bd4ef | 13176 | { |
c19d1205 | 13177 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
13178 | inst.instruction |= Rd; |
13179 | inst.instruction |= Rm << 3; | |
b99bd4ef | 13180 | } |
c19d1205 | 13181 | else if (unified_syntax) |
b99bd4ef | 13182 | { |
c19d1205 ZW |
13183 | if (inst.instruction <= 0xffff) |
13184 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
13185 | inst.instruction |= Rd << 8; |
13186 | inst.instruction |= Rm; | |
c19d1205 | 13187 | inst.instruction |= inst.operands[2].imm << 4; |
b99bd4ef | 13188 | } |
c19d1205 | 13189 | else |
b99bd4ef | 13190 | { |
c19d1205 ZW |
13191 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
13192 | _("Thumb encoding does not support rotation")); | |
13193 | constraint (1, BAD_HIREG); | |
b99bd4ef | 13194 | } |
c19d1205 | 13195 | } |
b99bd4ef | 13196 | |
c19d1205 ZW |
13197 | static void |
13198 | do_t_swi (void) | |
13199 | { | |
13200 | inst.reloc.type = BFD_RELOC_ARM_SWI; | |
13201 | } | |
b99bd4ef | 13202 | |
92e90b6e PB |
13203 | static void |
13204 | do_t_tb (void) | |
13205 | { | |
fdfde340 | 13206 | unsigned Rn, Rm; |
92e90b6e PB |
13207 | int half; |
13208 | ||
13209 | half = (inst.instruction & 0x10) != 0; | |
e07e6e58 | 13210 | set_it_insn_type_last (); |
dfa9f0d5 PB |
13211 | constraint (inst.operands[0].immisreg, |
13212 | _("instruction requires register index")); | |
fdfde340 JM |
13213 | |
13214 | Rn = inst.operands[0].reg; | |
13215 | Rm = inst.operands[0].imm; | |
c921be7d | 13216 | |
5c8ed6a4 JW |
13217 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
13218 | constraint (Rn == REG_SP, BAD_SP); | |
fdfde340 JM |
13219 | reject_bad_reg (Rm); |
13220 | ||
92e90b6e PB |
13221 | constraint (!half && inst.operands[0].shifted, |
13222 | _("instruction does not allow shifted index")); | |
fdfde340 | 13223 | inst.instruction |= (Rn << 16) | Rm; |
92e90b6e PB |
13224 | } |
13225 | ||
74db7efb NC |
13226 | static void |
13227 | do_t_udf (void) | |
13228 | { | |
13229 | if (!inst.operands[0].present) | |
13230 | inst.operands[0].imm = 0; | |
13231 | ||
13232 | if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4) | |
13233 | { | |
13234 | constraint (inst.size_req == 2, | |
13235 | _("immediate value out of range")); | |
13236 | inst.instruction = THUMB_OP32 (inst.instruction); | |
13237 | inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4; | |
13238 | inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0; | |
13239 | } | |
13240 | else | |
13241 | { | |
13242 | inst.instruction = THUMB_OP16 (inst.instruction); | |
13243 | inst.instruction |= inst.operands[0].imm; | |
13244 | } | |
13245 | ||
13246 | set_it_insn_type (NEUTRAL_IT_INSN); | |
13247 | } | |
13248 | ||
13249 | ||
c19d1205 ZW |
13250 | static void |
13251 | do_t_usat (void) | |
13252 | { | |
3a21c15a | 13253 | do_t_ssat_usat (0); |
b99bd4ef NC |
13254 | } |
13255 | ||
13256 | static void | |
c19d1205 | 13257 | do_t_usat16 (void) |
b99bd4ef | 13258 | { |
fdfde340 JM |
13259 | unsigned Rd, Rn; |
13260 | ||
13261 | Rd = inst.operands[0].reg; | |
13262 | Rn = inst.operands[2].reg; | |
13263 | ||
13264 | reject_bad_reg (Rd); | |
13265 | reject_bad_reg (Rn); | |
13266 | ||
13267 | inst.instruction |= Rd << 8; | |
c19d1205 | 13268 | inst.instruction |= inst.operands[1].imm; |
fdfde340 | 13269 | inst.instruction |= Rn << 16; |
b99bd4ef | 13270 | } |
c19d1205 | 13271 | |
5287ad62 | 13272 | /* Neon instruction encoder helpers. */ |
5f4273c7 | 13273 | |
5287ad62 | 13274 | /* Encodings for the different types for various Neon opcodes. */ |
b99bd4ef | 13275 | |
5287ad62 JB |
13276 | /* An "invalid" code for the following tables. */ |
13277 | #define N_INV -1u | |
13278 | ||
13279 | struct neon_tab_entry | |
b99bd4ef | 13280 | { |
5287ad62 JB |
13281 | unsigned integer; |
13282 | unsigned float_or_poly; | |
13283 | unsigned scalar_or_imm; | |
13284 | }; | |
5f4273c7 | 13285 | |
5287ad62 JB |
13286 | /* Map overloaded Neon opcodes to their respective encodings. */ |
13287 | #define NEON_ENC_TAB \ | |
13288 | X(vabd, 0x0000700, 0x1200d00, N_INV), \ | |
13289 | X(vmax, 0x0000600, 0x0000f00, N_INV), \ | |
13290 | X(vmin, 0x0000610, 0x0200f00, N_INV), \ | |
13291 | X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ | |
13292 | X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ | |
13293 | X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ | |
13294 | X(vadd, 0x0000800, 0x0000d00, N_INV), \ | |
13295 | X(vsub, 0x1000800, 0x0200d00, N_INV), \ | |
13296 | X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ | |
13297 | X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ | |
13298 | X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ | |
13299 | /* Register variants of the following two instructions are encoded as | |
e07e6e58 | 13300 | vcge / vcgt with the operands reversed. */ \ |
92559b5b PB |
13301 | X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ |
13302 | X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ | |
62f3b8c8 PB |
13303 | X(vfma, N_INV, 0x0000c10, N_INV), \ |
13304 | X(vfms, N_INV, 0x0200c10, N_INV), \ | |
5287ad62 JB |
13305 | X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ |
13306 | X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ | |
13307 | X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ | |
13308 | X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ | |
13309 | X(vmlal, 0x0800800, N_INV, 0x0800240), \ | |
13310 | X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ | |
13311 | X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ | |
13312 | X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ | |
13313 | X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ | |
13314 | X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ | |
13315 | X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ | |
d6b4b13e MW |
13316 | X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \ |
13317 | X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \ | |
5287ad62 JB |
13318 | X(vshl, 0x0000400, N_INV, 0x0800510), \ |
13319 | X(vqshl, 0x0000410, N_INV, 0x0800710), \ | |
13320 | X(vand, 0x0000110, N_INV, 0x0800030), \ | |
13321 | X(vbic, 0x0100110, N_INV, 0x0800030), \ | |
13322 | X(veor, 0x1000110, N_INV, N_INV), \ | |
13323 | X(vorn, 0x0300110, N_INV, 0x0800010), \ | |
13324 | X(vorr, 0x0200110, N_INV, 0x0800010), \ | |
13325 | X(vmvn, 0x1b00580, N_INV, 0x0800030), \ | |
13326 | X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ | |
13327 | X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ | |
13328 | X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ | |
13329 | X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ | |
13330 | X(vst1, 0x0000000, 0x0800000, N_INV), \ | |
13331 | X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ | |
13332 | X(vst2, 0x0000100, 0x0800100, N_INV), \ | |
13333 | X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ | |
13334 | X(vst3, 0x0000200, 0x0800200, N_INV), \ | |
13335 | X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ | |
13336 | X(vst4, 0x0000300, 0x0800300, N_INV), \ | |
13337 | X(vmovn, 0x1b20200, N_INV, N_INV), \ | |
13338 | X(vtrn, 0x1b20080, N_INV, N_INV), \ | |
13339 | X(vqmovn, 0x1b20200, N_INV, N_INV), \ | |
037e8744 JB |
13340 | X(vqmovun, 0x1b20240, N_INV, N_INV), \ |
13341 | X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ | |
e6655fda PB |
13342 | X(vnmla, 0xe100a40, 0xe100b40, N_INV), \ |
13343 | X(vnmls, 0xe100a00, 0xe100b00, N_INV), \ | |
62f3b8c8 PB |
13344 | X(vfnma, 0xe900a40, 0xe900b40, N_INV), \ |
13345 | X(vfnms, 0xe900a00, 0xe900b00, N_INV), \ | |
037e8744 JB |
13346 | X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ |
13347 | X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ | |
13348 | X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ | |
33399f07 MGD |
13349 | X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \ |
13350 | X(vseleq, 0xe000a00, N_INV, N_INV), \ | |
13351 | X(vselvs, 0xe100a00, N_INV, N_INV), \ | |
13352 | X(vselge, 0xe200a00, N_INV, N_INV), \ | |
73924fbc MGD |
13353 | X(vselgt, 0xe300a00, N_INV, N_INV), \ |
13354 | X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \ | |
7e8e6784 | 13355 | X(vminnm, 0xe800a40, 0x3200f10, N_INV), \ |
30bdf752 MGD |
13356 | X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \ |
13357 | X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \ | |
91ff7894 | 13358 | X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \ |
48adcd8e | 13359 | X(aes, 0x3b00300, N_INV, N_INV), \ |
3c9017d2 MGD |
13360 | X(sha3op, 0x2000c00, N_INV, N_INV), \ |
13361 | X(sha1h, 0x3b902c0, N_INV, N_INV), \ | |
13362 | X(sha2op, 0x3ba0380, N_INV, N_INV) | |
5287ad62 JB |
13363 | |
13364 | enum neon_opc | |
13365 | { | |
13366 | #define X(OPC,I,F,S) N_MNEM_##OPC | |
13367 | NEON_ENC_TAB | |
13368 | #undef X | |
13369 | }; | |
b99bd4ef | 13370 | |
5287ad62 JB |
13371 | static const struct neon_tab_entry neon_enc_tab[] = |
13372 | { | |
13373 | #define X(OPC,I,F,S) { (I), (F), (S) } | |
13374 | NEON_ENC_TAB | |
13375 | #undef X | |
13376 | }; | |
b99bd4ef | 13377 | |
88714cb8 DG |
13378 | /* Do not use these macros; instead, use NEON_ENCODE defined below. */ |
13379 | #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
13380 | #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
13381 | #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
13382 | #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
13383 | #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
13384 | #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
13385 | #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
13386 | #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
13387 | #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
13388 | #define NEON_ENC_SINGLE_(X) \ | |
037e8744 | 13389 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) |
88714cb8 | 13390 | #define NEON_ENC_DOUBLE_(X) \ |
037e8744 | 13391 | ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) |
33399f07 MGD |
13392 | #define NEON_ENC_FPV8_(X) \ |
13393 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000)) | |
5287ad62 | 13394 | |
88714cb8 DG |
13395 | #define NEON_ENCODE(type, inst) \ |
13396 | do \ | |
13397 | { \ | |
13398 | inst.instruction = NEON_ENC_##type##_ (inst.instruction); \ | |
13399 | inst.is_neon = 1; \ | |
13400 | } \ | |
13401 | while (0) | |
13402 | ||
13403 | #define check_neon_suffixes \ | |
13404 | do \ | |
13405 | { \ | |
13406 | if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \ | |
13407 | { \ | |
13408 | as_bad (_("invalid neon suffix for non neon instruction")); \ | |
13409 | return; \ | |
13410 | } \ | |
13411 | } \ | |
13412 | while (0) | |
13413 | ||
037e8744 JB |
13414 | /* Define shapes for instruction operands. The following mnemonic characters |
13415 | are used in this table: | |
5287ad62 | 13416 | |
037e8744 | 13417 | F - VFP S<n> register |
5287ad62 JB |
13418 | D - Neon D<n> register |
13419 | Q - Neon Q<n> register | |
13420 | I - Immediate | |
13421 | S - Scalar | |
13422 | R - ARM register | |
13423 | L - D<n> register list | |
5f4273c7 | 13424 | |
037e8744 JB |
13425 | This table is used to generate various data: |
13426 | - enumerations of the form NS_DDR to be used as arguments to | |
13427 | neon_select_shape. | |
13428 | - a table classifying shapes into single, double, quad, mixed. | |
5f4273c7 | 13429 | - a table used to drive neon_select_shape. */ |
b99bd4ef | 13430 | |
037e8744 JB |
13431 | #define NEON_SHAPE_DEF \ |
13432 | X(3, (D, D, D), DOUBLE), \ | |
13433 | X(3, (Q, Q, Q), QUAD), \ | |
13434 | X(3, (D, D, I), DOUBLE), \ | |
13435 | X(3, (Q, Q, I), QUAD), \ | |
13436 | X(3, (D, D, S), DOUBLE), \ | |
13437 | X(3, (Q, Q, S), QUAD), \ | |
13438 | X(2, (D, D), DOUBLE), \ | |
13439 | X(2, (Q, Q), QUAD), \ | |
13440 | X(2, (D, S), DOUBLE), \ | |
13441 | X(2, (Q, S), QUAD), \ | |
13442 | X(2, (D, R), DOUBLE), \ | |
13443 | X(2, (Q, R), QUAD), \ | |
13444 | X(2, (D, I), DOUBLE), \ | |
13445 | X(2, (Q, I), QUAD), \ | |
13446 | X(3, (D, L, D), DOUBLE), \ | |
13447 | X(2, (D, Q), MIXED), \ | |
13448 | X(2, (Q, D), MIXED), \ | |
13449 | X(3, (D, Q, I), MIXED), \ | |
13450 | X(3, (Q, D, I), MIXED), \ | |
13451 | X(3, (Q, D, D), MIXED), \ | |
13452 | X(3, (D, Q, Q), MIXED), \ | |
13453 | X(3, (Q, Q, D), MIXED), \ | |
13454 | X(3, (Q, D, S), MIXED), \ | |
13455 | X(3, (D, Q, S), MIXED), \ | |
13456 | X(4, (D, D, D, I), DOUBLE), \ | |
13457 | X(4, (Q, Q, Q, I), QUAD), \ | |
c28eeff2 SN |
13458 | X(4, (D, D, S, I), DOUBLE), \ |
13459 | X(4, (Q, Q, S, I), QUAD), \ | |
037e8744 JB |
13460 | X(2, (F, F), SINGLE), \ |
13461 | X(3, (F, F, F), SINGLE), \ | |
13462 | X(2, (F, I), SINGLE), \ | |
13463 | X(2, (F, D), MIXED), \ | |
13464 | X(2, (D, F), MIXED), \ | |
13465 | X(3, (F, F, I), MIXED), \ | |
13466 | X(4, (R, R, F, F), SINGLE), \ | |
13467 | X(4, (F, F, R, R), SINGLE), \ | |
13468 | X(3, (D, R, R), DOUBLE), \ | |
13469 | X(3, (R, R, D), DOUBLE), \ | |
13470 | X(2, (S, R), SINGLE), \ | |
13471 | X(2, (R, S), SINGLE), \ | |
13472 | X(2, (F, R), SINGLE), \ | |
d54af2d0 RL |
13473 | X(2, (R, F), SINGLE), \ |
13474 | /* Half float shape supported so far. */\ | |
13475 | X (2, (H, D), MIXED), \ | |
13476 | X (2, (D, H), MIXED), \ | |
13477 | X (2, (H, F), MIXED), \ | |
13478 | X (2, (F, H), MIXED), \ | |
13479 | X (2, (H, H), HALF), \ | |
13480 | X (2, (H, R), HALF), \ | |
13481 | X (2, (R, H), HALF), \ | |
13482 | X (2, (H, I), HALF), \ | |
13483 | X (3, (H, H, H), HALF), \ | |
13484 | X (3, (H, F, I), MIXED), \ | |
dec41383 JW |
13485 | X (3, (F, H, I), MIXED), \ |
13486 | X (3, (D, H, H), MIXED), \ | |
13487 | X (3, (D, H, S), MIXED) | |
037e8744 JB |
13488 | |
13489 | #define S2(A,B) NS_##A##B | |
13490 | #define S3(A,B,C) NS_##A##B##C | |
13491 | #define S4(A,B,C,D) NS_##A##B##C##D | |
13492 | ||
13493 | #define X(N, L, C) S##N L | |
13494 | ||
5287ad62 JB |
13495 | enum neon_shape |
13496 | { | |
037e8744 JB |
13497 | NEON_SHAPE_DEF, |
13498 | NS_NULL | |
5287ad62 | 13499 | }; |
b99bd4ef | 13500 | |
037e8744 JB |
13501 | #undef X |
13502 | #undef S2 | |
13503 | #undef S3 | |
13504 | #undef S4 | |
13505 | ||
13506 | enum neon_shape_class | |
13507 | { | |
d54af2d0 | 13508 | SC_HALF, |
037e8744 JB |
13509 | SC_SINGLE, |
13510 | SC_DOUBLE, | |
13511 | SC_QUAD, | |
13512 | SC_MIXED | |
13513 | }; | |
13514 | ||
13515 | #define X(N, L, C) SC_##C | |
13516 | ||
13517 | static enum neon_shape_class neon_shape_class[] = | |
13518 | { | |
13519 | NEON_SHAPE_DEF | |
13520 | }; | |
13521 | ||
13522 | #undef X | |
13523 | ||
13524 | enum neon_shape_el | |
13525 | { | |
d54af2d0 | 13526 | SE_H, |
037e8744 JB |
13527 | SE_F, |
13528 | SE_D, | |
13529 | SE_Q, | |
13530 | SE_I, | |
13531 | SE_S, | |
13532 | SE_R, | |
13533 | SE_L | |
13534 | }; | |
13535 | ||
13536 | /* Register widths of above. */ | |
13537 | static unsigned neon_shape_el_size[] = | |
13538 | { | |
d54af2d0 | 13539 | 16, |
037e8744 JB |
13540 | 32, |
13541 | 64, | |
13542 | 128, | |
13543 | 0, | |
13544 | 32, | |
13545 | 32, | |
13546 | 0 | |
13547 | }; | |
13548 | ||
13549 | struct neon_shape_info | |
13550 | { | |
13551 | unsigned els; | |
13552 | enum neon_shape_el el[NEON_MAX_TYPE_ELS]; | |
13553 | }; | |
13554 | ||
13555 | #define S2(A,B) { SE_##A, SE_##B } | |
13556 | #define S3(A,B,C) { SE_##A, SE_##B, SE_##C } | |
13557 | #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } | |
13558 | ||
13559 | #define X(N, L, C) { N, S##N L } | |
13560 | ||
13561 | static struct neon_shape_info neon_shape_tab[] = | |
13562 | { | |
13563 | NEON_SHAPE_DEF | |
13564 | }; | |
13565 | ||
13566 | #undef X | |
13567 | #undef S2 | |
13568 | #undef S3 | |
13569 | #undef S4 | |
13570 | ||
5287ad62 JB |
13571 | /* Bit masks used in type checking given instructions. |
13572 | 'N_EQK' means the type must be the same as (or based on in some way) the key | |
13573 | type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is | |
13574 | set, various other bits can be set as well in order to modify the meaning of | |
13575 | the type constraint. */ | |
13576 | ||
13577 | enum neon_type_mask | |
13578 | { | |
8e79c3df CM |
13579 | N_S8 = 0x0000001, |
13580 | N_S16 = 0x0000002, | |
13581 | N_S32 = 0x0000004, | |
13582 | N_S64 = 0x0000008, | |
13583 | N_U8 = 0x0000010, | |
13584 | N_U16 = 0x0000020, | |
13585 | N_U32 = 0x0000040, | |
13586 | N_U64 = 0x0000080, | |
13587 | N_I8 = 0x0000100, | |
13588 | N_I16 = 0x0000200, | |
13589 | N_I32 = 0x0000400, | |
13590 | N_I64 = 0x0000800, | |
13591 | N_8 = 0x0001000, | |
13592 | N_16 = 0x0002000, | |
13593 | N_32 = 0x0004000, | |
13594 | N_64 = 0x0008000, | |
13595 | N_P8 = 0x0010000, | |
13596 | N_P16 = 0x0020000, | |
13597 | N_F16 = 0x0040000, | |
13598 | N_F32 = 0x0080000, | |
13599 | N_F64 = 0x0100000, | |
4f51b4bd | 13600 | N_P64 = 0x0200000, |
c921be7d NC |
13601 | N_KEY = 0x1000000, /* Key element (main type specifier). */ |
13602 | N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */ | |
8e79c3df | 13603 | N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ |
91ff7894 | 13604 | N_UNT = 0x8000000, /* Must be explicitly untyped. */ |
c921be7d NC |
13605 | N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */ |
13606 | N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */ | |
13607 | N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */ | |
13608 | N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */ | |
13609 | N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */ | |
13610 | N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */ | |
13611 | N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */ | |
5287ad62 | 13612 | N_UTYP = 0, |
4f51b4bd | 13613 | N_MAX_NONSPECIAL = N_P64 |
5287ad62 JB |
13614 | }; |
13615 | ||
dcbf9037 JB |
13616 | #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) |
13617 | ||
5287ad62 JB |
13618 | #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) |
13619 | #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) | |
13620 | #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) | |
cc933301 JW |
13621 | #define N_S_32 (N_S8 | N_S16 | N_S32) |
13622 | #define N_F_16_32 (N_F16 | N_F32) | |
13623 | #define N_SUF_32 (N_SU_32 | N_F_16_32) | |
5287ad62 | 13624 | #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) |
cc933301 | 13625 | #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32) |
d54af2d0 | 13626 | #define N_F_ALL (N_F16 | N_F32 | N_F64) |
5287ad62 JB |
13627 | |
13628 | /* Pass this as the first type argument to neon_check_type to ignore types | |
13629 | altogether. */ | |
13630 | #define N_IGNORE_TYPE (N_KEY | N_EQK) | |
13631 | ||
037e8744 JB |
13632 | /* Select a "shape" for the current instruction (describing register types or |
13633 | sizes) from a list of alternatives. Return NS_NULL if the current instruction | |
13634 | doesn't fit. For non-polymorphic shapes, checking is usually done as a | |
13635 | function of operand parsing, so this function doesn't need to be called. | |
13636 | Shapes should be listed in order of decreasing length. */ | |
5287ad62 JB |
13637 | |
13638 | static enum neon_shape | |
037e8744 | 13639 | neon_select_shape (enum neon_shape shape, ...) |
5287ad62 | 13640 | { |
037e8744 JB |
13641 | va_list ap; |
13642 | enum neon_shape first_shape = shape; | |
5287ad62 JB |
13643 | |
13644 | /* Fix missing optional operands. FIXME: we don't know at this point how | |
13645 | many arguments we should have, so this makes the assumption that we have | |
13646 | > 1. This is true of all current Neon opcodes, I think, but may not be | |
13647 | true in the future. */ | |
13648 | if (!inst.operands[1].present) | |
13649 | inst.operands[1] = inst.operands[0]; | |
13650 | ||
037e8744 | 13651 | va_start (ap, shape); |
5f4273c7 | 13652 | |
21d799b5 | 13653 | for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int)) |
037e8744 JB |
13654 | { |
13655 | unsigned j; | |
13656 | int matches = 1; | |
13657 | ||
13658 | for (j = 0; j < neon_shape_tab[shape].els; j++) | |
477330fc RM |
13659 | { |
13660 | if (!inst.operands[j].present) | |
13661 | { | |
13662 | matches = 0; | |
13663 | break; | |
13664 | } | |
13665 | ||
13666 | switch (neon_shape_tab[shape].el[j]) | |
13667 | { | |
d54af2d0 RL |
13668 | /* If a .f16, .16, .u16, .s16 type specifier is given over |
13669 | a VFP single precision register operand, it's essentially | |
13670 | means only half of the register is used. | |
13671 | ||
13672 | If the type specifier is given after the mnemonics, the | |
13673 | information is stored in inst.vectype. If the type specifier | |
13674 | is given after register operand, the information is stored | |
13675 | in inst.operands[].vectype. | |
13676 | ||
13677 | When there is only one type specifier, and all the register | |
13678 | operands are the same type of hardware register, the type | |
13679 | specifier applies to all register operands. | |
13680 | ||
13681 | If no type specifier is given, the shape is inferred from | |
13682 | operand information. | |
13683 | ||
13684 | for example: | |
13685 | vadd.f16 s0, s1, s2: NS_HHH | |
13686 | vabs.f16 s0, s1: NS_HH | |
13687 | vmov.f16 s0, r1: NS_HR | |
13688 | vmov.f16 r0, s1: NS_RH | |
13689 | vcvt.f16 r0, s1: NS_RH | |
13690 | vcvt.f16.s32 s2, s2, #29: NS_HFI | |
13691 | vcvt.f16.s32 s2, s2: NS_HF | |
13692 | */ | |
13693 | case SE_H: | |
13694 | if (!(inst.operands[j].isreg | |
13695 | && inst.operands[j].isvec | |
13696 | && inst.operands[j].issingle | |
13697 | && !inst.operands[j].isquad | |
13698 | && ((inst.vectype.elems == 1 | |
13699 | && inst.vectype.el[0].size == 16) | |
13700 | || (inst.vectype.elems > 1 | |
13701 | && inst.vectype.el[j].size == 16) | |
13702 | || (inst.vectype.elems == 0 | |
13703 | && inst.operands[j].vectype.type != NT_invtype | |
13704 | && inst.operands[j].vectype.size == 16)))) | |
13705 | matches = 0; | |
13706 | break; | |
13707 | ||
477330fc RM |
13708 | case SE_F: |
13709 | if (!(inst.operands[j].isreg | |
13710 | && inst.operands[j].isvec | |
13711 | && inst.operands[j].issingle | |
d54af2d0 RL |
13712 | && !inst.operands[j].isquad |
13713 | && ((inst.vectype.elems == 1 && inst.vectype.el[0].size == 32) | |
13714 | || (inst.vectype.elems > 1 && inst.vectype.el[j].size == 32) | |
13715 | || (inst.vectype.elems == 0 | |
13716 | && (inst.operands[j].vectype.size == 32 | |
13717 | || inst.operands[j].vectype.type == NT_invtype))))) | |
477330fc RM |
13718 | matches = 0; |
13719 | break; | |
13720 | ||
13721 | case SE_D: | |
13722 | if (!(inst.operands[j].isreg | |
13723 | && inst.operands[j].isvec | |
13724 | && !inst.operands[j].isquad | |
13725 | && !inst.operands[j].issingle)) | |
13726 | matches = 0; | |
13727 | break; | |
13728 | ||
13729 | case SE_R: | |
13730 | if (!(inst.operands[j].isreg | |
13731 | && !inst.operands[j].isvec)) | |
13732 | matches = 0; | |
13733 | break; | |
13734 | ||
13735 | case SE_Q: | |
13736 | if (!(inst.operands[j].isreg | |
13737 | && inst.operands[j].isvec | |
13738 | && inst.operands[j].isquad | |
13739 | && !inst.operands[j].issingle)) | |
13740 | matches = 0; | |
13741 | break; | |
13742 | ||
13743 | case SE_I: | |
13744 | if (!(!inst.operands[j].isreg | |
13745 | && !inst.operands[j].isscalar)) | |
13746 | matches = 0; | |
13747 | break; | |
13748 | ||
13749 | case SE_S: | |
13750 | if (!(!inst.operands[j].isreg | |
13751 | && inst.operands[j].isscalar)) | |
13752 | matches = 0; | |
13753 | break; | |
13754 | ||
13755 | case SE_L: | |
13756 | break; | |
13757 | } | |
3fde54a2 JZ |
13758 | if (!matches) |
13759 | break; | |
477330fc | 13760 | } |
ad6cec43 MGD |
13761 | if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present)) |
13762 | /* We've matched all the entries in the shape table, and we don't | |
13763 | have any left over operands which have not been matched. */ | |
477330fc | 13764 | break; |
037e8744 | 13765 | } |
5f4273c7 | 13766 | |
037e8744 | 13767 | va_end (ap); |
5287ad62 | 13768 | |
037e8744 JB |
13769 | if (shape == NS_NULL && first_shape != NS_NULL) |
13770 | first_error (_("invalid instruction shape")); | |
5287ad62 | 13771 | |
037e8744 JB |
13772 | return shape; |
13773 | } | |
5287ad62 | 13774 | |
037e8744 JB |
13775 | /* True if SHAPE is predominantly a quadword operation (most of the time, this |
13776 | means the Q bit should be set). */ | |
13777 | ||
13778 | static int | |
13779 | neon_quad (enum neon_shape shape) | |
13780 | { | |
13781 | return neon_shape_class[shape] == SC_QUAD; | |
5287ad62 | 13782 | } |
037e8744 | 13783 | |
5287ad62 JB |
13784 | static void |
13785 | neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, | |
477330fc | 13786 | unsigned *g_size) |
5287ad62 JB |
13787 | { |
13788 | /* Allow modification to be made to types which are constrained to be | |
13789 | based on the key element, based on bits set alongside N_EQK. */ | |
13790 | if ((typebits & N_EQK) != 0) | |
13791 | { | |
13792 | if ((typebits & N_HLF) != 0) | |
13793 | *g_size /= 2; | |
13794 | else if ((typebits & N_DBL) != 0) | |
13795 | *g_size *= 2; | |
13796 | if ((typebits & N_SGN) != 0) | |
13797 | *g_type = NT_signed; | |
13798 | else if ((typebits & N_UNS) != 0) | |
477330fc | 13799 | *g_type = NT_unsigned; |
5287ad62 | 13800 | else if ((typebits & N_INT) != 0) |
477330fc | 13801 | *g_type = NT_integer; |
5287ad62 | 13802 | else if ((typebits & N_FLT) != 0) |
477330fc | 13803 | *g_type = NT_float; |
dcbf9037 | 13804 | else if ((typebits & N_SIZ) != 0) |
477330fc | 13805 | *g_type = NT_untyped; |
5287ad62 JB |
13806 | } |
13807 | } | |
5f4273c7 | 13808 | |
5287ad62 JB |
13809 | /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" |
13810 | operand type, i.e. the single type specified in a Neon instruction when it | |
13811 | is the only one given. */ | |
13812 | ||
13813 | static struct neon_type_el | |
13814 | neon_type_promote (struct neon_type_el *key, unsigned thisarg) | |
13815 | { | |
13816 | struct neon_type_el dest = *key; | |
5f4273c7 | 13817 | |
9c2799c2 | 13818 | gas_assert ((thisarg & N_EQK) != 0); |
5f4273c7 | 13819 | |
5287ad62 JB |
13820 | neon_modify_type_size (thisarg, &dest.type, &dest.size); |
13821 | ||
13822 | return dest; | |
13823 | } | |
13824 | ||
13825 | /* Convert Neon type and size into compact bitmask representation. */ | |
13826 | ||
13827 | static enum neon_type_mask | |
13828 | type_chk_of_el_type (enum neon_el_type type, unsigned size) | |
13829 | { | |
13830 | switch (type) | |
13831 | { | |
13832 | case NT_untyped: | |
13833 | switch (size) | |
477330fc RM |
13834 | { |
13835 | case 8: return N_8; | |
13836 | case 16: return N_16; | |
13837 | case 32: return N_32; | |
13838 | case 64: return N_64; | |
13839 | default: ; | |
13840 | } | |
5287ad62 JB |
13841 | break; |
13842 | ||
13843 | case NT_integer: | |
13844 | switch (size) | |
477330fc RM |
13845 | { |
13846 | case 8: return N_I8; | |
13847 | case 16: return N_I16; | |
13848 | case 32: return N_I32; | |
13849 | case 64: return N_I64; | |
13850 | default: ; | |
13851 | } | |
5287ad62 JB |
13852 | break; |
13853 | ||
13854 | case NT_float: | |
037e8744 | 13855 | switch (size) |
477330fc | 13856 | { |
8e79c3df | 13857 | case 16: return N_F16; |
477330fc RM |
13858 | case 32: return N_F32; |
13859 | case 64: return N_F64; | |
13860 | default: ; | |
13861 | } | |
5287ad62 JB |
13862 | break; |
13863 | ||
13864 | case NT_poly: | |
13865 | switch (size) | |
477330fc RM |
13866 | { |
13867 | case 8: return N_P8; | |
13868 | case 16: return N_P16; | |
4f51b4bd | 13869 | case 64: return N_P64; |
477330fc RM |
13870 | default: ; |
13871 | } | |
5287ad62 JB |
13872 | break; |
13873 | ||
13874 | case NT_signed: | |
13875 | switch (size) | |
477330fc RM |
13876 | { |
13877 | case 8: return N_S8; | |
13878 | case 16: return N_S16; | |
13879 | case 32: return N_S32; | |
13880 | case 64: return N_S64; | |
13881 | default: ; | |
13882 | } | |
5287ad62 JB |
13883 | break; |
13884 | ||
13885 | case NT_unsigned: | |
13886 | switch (size) | |
477330fc RM |
13887 | { |
13888 | case 8: return N_U8; | |
13889 | case 16: return N_U16; | |
13890 | case 32: return N_U32; | |
13891 | case 64: return N_U64; | |
13892 | default: ; | |
13893 | } | |
5287ad62 JB |
13894 | break; |
13895 | ||
13896 | default: ; | |
13897 | } | |
5f4273c7 | 13898 | |
5287ad62 JB |
13899 | return N_UTYP; |
13900 | } | |
13901 | ||
13902 | /* Convert compact Neon bitmask type representation to a type and size. Only | |
13903 | handles the case where a single bit is set in the mask. */ | |
13904 | ||
dcbf9037 | 13905 | static int |
5287ad62 | 13906 | el_type_of_type_chk (enum neon_el_type *type, unsigned *size, |
477330fc | 13907 | enum neon_type_mask mask) |
5287ad62 | 13908 | { |
dcbf9037 JB |
13909 | if ((mask & N_EQK) != 0) |
13910 | return FAIL; | |
13911 | ||
5287ad62 JB |
13912 | if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) |
13913 | *size = 8; | |
c70a8987 | 13914 | else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0) |
5287ad62 | 13915 | *size = 16; |
dcbf9037 | 13916 | else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) |
5287ad62 | 13917 | *size = 32; |
4f51b4bd | 13918 | else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0) |
5287ad62 | 13919 | *size = 64; |
dcbf9037 JB |
13920 | else |
13921 | return FAIL; | |
13922 | ||
5287ad62 JB |
13923 | if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) |
13924 | *type = NT_signed; | |
dcbf9037 | 13925 | else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) |
5287ad62 | 13926 | *type = NT_unsigned; |
dcbf9037 | 13927 | else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) |
5287ad62 | 13928 | *type = NT_integer; |
dcbf9037 | 13929 | else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) |
5287ad62 | 13930 | *type = NT_untyped; |
4f51b4bd | 13931 | else if ((mask & (N_P8 | N_P16 | N_P64)) != 0) |
5287ad62 | 13932 | *type = NT_poly; |
d54af2d0 | 13933 | else if ((mask & (N_F_ALL)) != 0) |
5287ad62 | 13934 | *type = NT_float; |
dcbf9037 JB |
13935 | else |
13936 | return FAIL; | |
5f4273c7 | 13937 | |
dcbf9037 | 13938 | return SUCCESS; |
5287ad62 JB |
13939 | } |
13940 | ||
13941 | /* Modify a bitmask of allowed types. This is only needed for type | |
13942 | relaxation. */ | |
13943 | ||
13944 | static unsigned | |
13945 | modify_types_allowed (unsigned allowed, unsigned mods) | |
13946 | { | |
13947 | unsigned size; | |
13948 | enum neon_el_type type; | |
13949 | unsigned destmask; | |
13950 | int i; | |
5f4273c7 | 13951 | |
5287ad62 | 13952 | destmask = 0; |
5f4273c7 | 13953 | |
5287ad62 JB |
13954 | for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) |
13955 | { | |
21d799b5 | 13956 | if (el_type_of_type_chk (&type, &size, |
477330fc RM |
13957 | (enum neon_type_mask) (allowed & i)) == SUCCESS) |
13958 | { | |
13959 | neon_modify_type_size (mods, &type, &size); | |
13960 | destmask |= type_chk_of_el_type (type, size); | |
13961 | } | |
5287ad62 | 13962 | } |
5f4273c7 | 13963 | |
5287ad62 JB |
13964 | return destmask; |
13965 | } | |
13966 | ||
13967 | /* Check type and return type classification. | |
13968 | The manual states (paraphrase): If one datatype is given, it indicates the | |
13969 | type given in: | |
13970 | - the second operand, if there is one | |
13971 | - the operand, if there is no second operand | |
13972 | - the result, if there are no operands. | |
13973 | This isn't quite good enough though, so we use a concept of a "key" datatype | |
13974 | which is set on a per-instruction basis, which is the one which matters when | |
13975 | only one data type is written. | |
13976 | Note: this function has side-effects (e.g. filling in missing operands). All | |
037e8744 | 13977 | Neon instructions should call it before performing bit encoding. */ |
5287ad62 JB |
13978 | |
13979 | static struct neon_type_el | |
13980 | neon_check_type (unsigned els, enum neon_shape ns, ...) | |
13981 | { | |
13982 | va_list ap; | |
13983 | unsigned i, pass, key_el = 0; | |
13984 | unsigned types[NEON_MAX_TYPE_ELS]; | |
13985 | enum neon_el_type k_type = NT_invtype; | |
13986 | unsigned k_size = -1u; | |
13987 | struct neon_type_el badtype = {NT_invtype, -1}; | |
13988 | unsigned key_allowed = 0; | |
13989 | ||
13990 | /* Optional registers in Neon instructions are always (not) in operand 1. | |
13991 | Fill in the missing operand here, if it was omitted. */ | |
13992 | if (els > 1 && !inst.operands[1].present) | |
13993 | inst.operands[1] = inst.operands[0]; | |
13994 | ||
13995 | /* Suck up all the varargs. */ | |
13996 | va_start (ap, ns); | |
13997 | for (i = 0; i < els; i++) | |
13998 | { | |
13999 | unsigned thisarg = va_arg (ap, unsigned); | |
14000 | if (thisarg == N_IGNORE_TYPE) | |
477330fc RM |
14001 | { |
14002 | va_end (ap); | |
14003 | return badtype; | |
14004 | } | |
5287ad62 JB |
14005 | types[i] = thisarg; |
14006 | if ((thisarg & N_KEY) != 0) | |
477330fc | 14007 | key_el = i; |
5287ad62 JB |
14008 | } |
14009 | va_end (ap); | |
14010 | ||
dcbf9037 JB |
14011 | if (inst.vectype.elems > 0) |
14012 | for (i = 0; i < els; i++) | |
14013 | if (inst.operands[i].vectype.type != NT_invtype) | |
477330fc RM |
14014 | { |
14015 | first_error (_("types specified in both the mnemonic and operands")); | |
14016 | return badtype; | |
14017 | } | |
dcbf9037 | 14018 | |
5287ad62 JB |
14019 | /* Duplicate inst.vectype elements here as necessary. |
14020 | FIXME: No idea if this is exactly the same as the ARM assembler, | |
14021 | particularly when an insn takes one register and one non-register | |
14022 | operand. */ | |
14023 | if (inst.vectype.elems == 1 && els > 1) | |
14024 | { | |
14025 | unsigned j; | |
14026 | inst.vectype.elems = els; | |
14027 | inst.vectype.el[key_el] = inst.vectype.el[0]; | |
14028 | for (j = 0; j < els; j++) | |
477330fc RM |
14029 | if (j != key_el) |
14030 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
14031 | types[j]); | |
dcbf9037 JB |
14032 | } |
14033 | else if (inst.vectype.elems == 0 && els > 0) | |
14034 | { | |
14035 | unsigned j; | |
14036 | /* No types were given after the mnemonic, so look for types specified | |
477330fc RM |
14037 | after each operand. We allow some flexibility here; as long as the |
14038 | "key" operand has a type, we can infer the others. */ | |
dcbf9037 | 14039 | for (j = 0; j < els; j++) |
477330fc RM |
14040 | if (inst.operands[j].vectype.type != NT_invtype) |
14041 | inst.vectype.el[j] = inst.operands[j].vectype; | |
dcbf9037 JB |
14042 | |
14043 | if (inst.operands[key_el].vectype.type != NT_invtype) | |
477330fc RM |
14044 | { |
14045 | for (j = 0; j < els; j++) | |
14046 | if (inst.operands[j].vectype.type == NT_invtype) | |
14047 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
14048 | types[j]); | |
14049 | } | |
dcbf9037 | 14050 | else |
477330fc RM |
14051 | { |
14052 | first_error (_("operand types can't be inferred")); | |
14053 | return badtype; | |
14054 | } | |
5287ad62 JB |
14055 | } |
14056 | else if (inst.vectype.elems != els) | |
14057 | { | |
dcbf9037 | 14058 | first_error (_("type specifier has the wrong number of parts")); |
5287ad62 JB |
14059 | return badtype; |
14060 | } | |
14061 | ||
14062 | for (pass = 0; pass < 2; pass++) | |
14063 | { | |
14064 | for (i = 0; i < els; i++) | |
477330fc RM |
14065 | { |
14066 | unsigned thisarg = types[i]; | |
14067 | unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) | |
14068 | ? modify_types_allowed (key_allowed, thisarg) : thisarg; | |
14069 | enum neon_el_type g_type = inst.vectype.el[i].type; | |
14070 | unsigned g_size = inst.vectype.el[i].size; | |
14071 | ||
14072 | /* Decay more-specific signed & unsigned types to sign-insensitive | |
5287ad62 | 14073 | integer types if sign-specific variants are unavailable. */ |
477330fc | 14074 | if ((g_type == NT_signed || g_type == NT_unsigned) |
5287ad62 JB |
14075 | && (types_allowed & N_SU_ALL) == 0) |
14076 | g_type = NT_integer; | |
14077 | ||
477330fc | 14078 | /* If only untyped args are allowed, decay any more specific types to |
5287ad62 JB |
14079 | them. Some instructions only care about signs for some element |
14080 | sizes, so handle that properly. */ | |
477330fc | 14081 | if (((types_allowed & N_UNT) == 0) |
91ff7894 MGD |
14082 | && ((g_size == 8 && (types_allowed & N_8) != 0) |
14083 | || (g_size == 16 && (types_allowed & N_16) != 0) | |
14084 | || (g_size == 32 && (types_allowed & N_32) != 0) | |
14085 | || (g_size == 64 && (types_allowed & N_64) != 0))) | |
5287ad62 JB |
14086 | g_type = NT_untyped; |
14087 | ||
477330fc RM |
14088 | if (pass == 0) |
14089 | { | |
14090 | if ((thisarg & N_KEY) != 0) | |
14091 | { | |
14092 | k_type = g_type; | |
14093 | k_size = g_size; | |
14094 | key_allowed = thisarg & ~N_KEY; | |
cc933301 JW |
14095 | |
14096 | /* Check architecture constraint on FP16 extension. */ | |
14097 | if (k_size == 16 | |
14098 | && k_type == NT_float | |
14099 | && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)) | |
14100 | { | |
14101 | inst.error = _(BAD_FP16); | |
14102 | return badtype; | |
14103 | } | |
477330fc RM |
14104 | } |
14105 | } | |
14106 | else | |
14107 | { | |
14108 | if ((thisarg & N_VFP) != 0) | |
14109 | { | |
14110 | enum neon_shape_el regshape; | |
14111 | unsigned regwidth, match; | |
99b253c5 NC |
14112 | |
14113 | /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */ | |
14114 | if (ns == NS_NULL) | |
14115 | { | |
14116 | first_error (_("invalid instruction shape")); | |
14117 | return badtype; | |
14118 | } | |
477330fc RM |
14119 | regshape = neon_shape_tab[ns].el[i]; |
14120 | regwidth = neon_shape_el_size[regshape]; | |
14121 | ||
14122 | /* In VFP mode, operands must match register widths. If we | |
14123 | have a key operand, use its width, else use the width of | |
14124 | the current operand. */ | |
14125 | if (k_size != -1u) | |
14126 | match = k_size; | |
14127 | else | |
14128 | match = g_size; | |
14129 | ||
9db2f6b4 RL |
14130 | /* FP16 will use a single precision register. */ |
14131 | if (regwidth == 32 && match == 16) | |
14132 | { | |
14133 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)) | |
14134 | match = regwidth; | |
14135 | else | |
14136 | { | |
14137 | inst.error = _(BAD_FP16); | |
14138 | return badtype; | |
14139 | } | |
14140 | } | |
14141 | ||
477330fc RM |
14142 | if (regwidth != match) |
14143 | { | |
14144 | first_error (_("operand size must match register width")); | |
14145 | return badtype; | |
14146 | } | |
14147 | } | |
14148 | ||
14149 | if ((thisarg & N_EQK) == 0) | |
14150 | { | |
14151 | unsigned given_type = type_chk_of_el_type (g_type, g_size); | |
14152 | ||
14153 | if ((given_type & types_allowed) == 0) | |
14154 | { | |
14155 | first_error (_("bad type in Neon instruction")); | |
14156 | return badtype; | |
14157 | } | |
14158 | } | |
14159 | else | |
14160 | { | |
14161 | enum neon_el_type mod_k_type = k_type; | |
14162 | unsigned mod_k_size = k_size; | |
14163 | neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); | |
14164 | if (g_type != mod_k_type || g_size != mod_k_size) | |
14165 | { | |
14166 | first_error (_("inconsistent types in Neon instruction")); | |
14167 | return badtype; | |
14168 | } | |
14169 | } | |
14170 | } | |
14171 | } | |
5287ad62 JB |
14172 | } |
14173 | ||
14174 | return inst.vectype.el[key_el]; | |
14175 | } | |
14176 | ||
037e8744 | 14177 | /* Neon-style VFP instruction forwarding. */ |
5287ad62 | 14178 | |
037e8744 JB |
14179 | /* Thumb VFP instructions have 0xE in the condition field. */ |
14180 | ||
14181 | static void | |
14182 | do_vfp_cond_or_thumb (void) | |
5287ad62 | 14183 | { |
88714cb8 DG |
14184 | inst.is_neon = 1; |
14185 | ||
5287ad62 | 14186 | if (thumb_mode) |
037e8744 | 14187 | inst.instruction |= 0xe0000000; |
5287ad62 | 14188 | else |
037e8744 | 14189 | inst.instruction |= inst.cond << 28; |
5287ad62 JB |
14190 | } |
14191 | ||
037e8744 JB |
14192 | /* Look up and encode a simple mnemonic, for use as a helper function for the |
14193 | Neon-style VFP syntax. This avoids duplication of bits of the insns table, | |
14194 | etc. It is assumed that operand parsing has already been done, and that the | |
14195 | operands are in the form expected by the given opcode (this isn't necessarily | |
14196 | the same as the form in which they were parsed, hence some massaging must | |
14197 | take place before this function is called). | |
14198 | Checks current arch version against that in the looked-up opcode. */ | |
5287ad62 | 14199 | |
037e8744 JB |
14200 | static void |
14201 | do_vfp_nsyn_opcode (const char *opname) | |
5287ad62 | 14202 | { |
037e8744 | 14203 | const struct asm_opcode *opcode; |
5f4273c7 | 14204 | |
21d799b5 | 14205 | opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname); |
5287ad62 | 14206 | |
037e8744 JB |
14207 | if (!opcode) |
14208 | abort (); | |
5287ad62 | 14209 | |
037e8744 | 14210 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, |
477330fc RM |
14211 | thumb_mode ? *opcode->tvariant : *opcode->avariant), |
14212 | _(BAD_FPU)); | |
5287ad62 | 14213 | |
88714cb8 DG |
14214 | inst.is_neon = 1; |
14215 | ||
037e8744 JB |
14216 | if (thumb_mode) |
14217 | { | |
14218 | inst.instruction = opcode->tvalue; | |
14219 | opcode->tencode (); | |
14220 | } | |
14221 | else | |
14222 | { | |
14223 | inst.instruction = (inst.cond << 28) | opcode->avalue; | |
14224 | opcode->aencode (); | |
14225 | } | |
14226 | } | |
5287ad62 JB |
14227 | |
14228 | static void | |
037e8744 | 14229 | do_vfp_nsyn_add_sub (enum neon_shape rs) |
5287ad62 | 14230 | { |
037e8744 JB |
14231 | int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; |
14232 | ||
9db2f6b4 | 14233 | if (rs == NS_FFF || rs == NS_HHH) |
037e8744 JB |
14234 | { |
14235 | if (is_add) | |
477330fc | 14236 | do_vfp_nsyn_opcode ("fadds"); |
037e8744 | 14237 | else |
477330fc | 14238 | do_vfp_nsyn_opcode ("fsubs"); |
9db2f6b4 RL |
14239 | |
14240 | /* ARMv8.2 fp16 instruction. */ | |
14241 | if (rs == NS_HHH) | |
14242 | do_scalar_fp16_v82_encode (); | |
037e8744 JB |
14243 | } |
14244 | else | |
14245 | { | |
14246 | if (is_add) | |
477330fc | 14247 | do_vfp_nsyn_opcode ("faddd"); |
037e8744 | 14248 | else |
477330fc | 14249 | do_vfp_nsyn_opcode ("fsubd"); |
037e8744 JB |
14250 | } |
14251 | } | |
14252 | ||
14253 | /* Check operand types to see if this is a VFP instruction, and if so call | |
14254 | PFN (). */ | |
14255 | ||
14256 | static int | |
14257 | try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) | |
14258 | { | |
14259 | enum neon_shape rs; | |
14260 | struct neon_type_el et; | |
14261 | ||
14262 | switch (args) | |
14263 | { | |
14264 | case 2: | |
9db2f6b4 RL |
14265 | rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL); |
14266 | et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP); | |
037e8744 | 14267 | break; |
5f4273c7 | 14268 | |
037e8744 | 14269 | case 3: |
9db2f6b4 RL |
14270 | rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL); |
14271 | et = neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
14272 | N_F_ALL | N_KEY | N_VFP); | |
037e8744 JB |
14273 | break; |
14274 | ||
14275 | default: | |
14276 | abort (); | |
14277 | } | |
14278 | ||
14279 | if (et.type != NT_invtype) | |
14280 | { | |
14281 | pfn (rs); | |
14282 | return SUCCESS; | |
14283 | } | |
037e8744 | 14284 | |
99b253c5 | 14285 | inst.error = NULL; |
037e8744 JB |
14286 | return FAIL; |
14287 | } | |
14288 | ||
14289 | static void | |
14290 | do_vfp_nsyn_mla_mls (enum neon_shape rs) | |
14291 | { | |
14292 | int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; | |
5f4273c7 | 14293 | |
9db2f6b4 | 14294 | if (rs == NS_FFF || rs == NS_HHH) |
037e8744 JB |
14295 | { |
14296 | if (is_mla) | |
477330fc | 14297 | do_vfp_nsyn_opcode ("fmacs"); |
037e8744 | 14298 | else |
477330fc | 14299 | do_vfp_nsyn_opcode ("fnmacs"); |
9db2f6b4 RL |
14300 | |
14301 | /* ARMv8.2 fp16 instruction. */ | |
14302 | if (rs == NS_HHH) | |
14303 | do_scalar_fp16_v82_encode (); | |
037e8744 JB |
14304 | } |
14305 | else | |
14306 | { | |
14307 | if (is_mla) | |
477330fc | 14308 | do_vfp_nsyn_opcode ("fmacd"); |
037e8744 | 14309 | else |
477330fc | 14310 | do_vfp_nsyn_opcode ("fnmacd"); |
037e8744 JB |
14311 | } |
14312 | } | |
14313 | ||
62f3b8c8 PB |
14314 | static void |
14315 | do_vfp_nsyn_fma_fms (enum neon_shape rs) | |
14316 | { | |
14317 | int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma; | |
14318 | ||
9db2f6b4 | 14319 | if (rs == NS_FFF || rs == NS_HHH) |
62f3b8c8 PB |
14320 | { |
14321 | if (is_fma) | |
477330fc | 14322 | do_vfp_nsyn_opcode ("ffmas"); |
62f3b8c8 | 14323 | else |
477330fc | 14324 | do_vfp_nsyn_opcode ("ffnmas"); |
9db2f6b4 RL |
14325 | |
14326 | /* ARMv8.2 fp16 instruction. */ | |
14327 | if (rs == NS_HHH) | |
14328 | do_scalar_fp16_v82_encode (); | |
62f3b8c8 PB |
14329 | } |
14330 | else | |
14331 | { | |
14332 | if (is_fma) | |
477330fc | 14333 | do_vfp_nsyn_opcode ("ffmad"); |
62f3b8c8 | 14334 | else |
477330fc | 14335 | do_vfp_nsyn_opcode ("ffnmad"); |
62f3b8c8 PB |
14336 | } |
14337 | } | |
14338 | ||
037e8744 JB |
14339 | static void |
14340 | do_vfp_nsyn_mul (enum neon_shape rs) | |
14341 | { | |
9db2f6b4 RL |
14342 | if (rs == NS_FFF || rs == NS_HHH) |
14343 | { | |
14344 | do_vfp_nsyn_opcode ("fmuls"); | |
14345 | ||
14346 | /* ARMv8.2 fp16 instruction. */ | |
14347 | if (rs == NS_HHH) | |
14348 | do_scalar_fp16_v82_encode (); | |
14349 | } | |
037e8744 JB |
14350 | else |
14351 | do_vfp_nsyn_opcode ("fmuld"); | |
14352 | } | |
14353 | ||
14354 | static void | |
14355 | do_vfp_nsyn_abs_neg (enum neon_shape rs) | |
14356 | { | |
14357 | int is_neg = (inst.instruction & 0x80) != 0; | |
9db2f6b4 | 14358 | neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_VFP | N_KEY); |
037e8744 | 14359 | |
9db2f6b4 | 14360 | if (rs == NS_FF || rs == NS_HH) |
037e8744 JB |
14361 | { |
14362 | if (is_neg) | |
477330fc | 14363 | do_vfp_nsyn_opcode ("fnegs"); |
037e8744 | 14364 | else |
477330fc | 14365 | do_vfp_nsyn_opcode ("fabss"); |
9db2f6b4 RL |
14366 | |
14367 | /* ARMv8.2 fp16 instruction. */ | |
14368 | if (rs == NS_HH) | |
14369 | do_scalar_fp16_v82_encode (); | |
037e8744 JB |
14370 | } |
14371 | else | |
14372 | { | |
14373 | if (is_neg) | |
477330fc | 14374 | do_vfp_nsyn_opcode ("fnegd"); |
037e8744 | 14375 | else |
477330fc | 14376 | do_vfp_nsyn_opcode ("fabsd"); |
037e8744 JB |
14377 | } |
14378 | } | |
14379 | ||
14380 | /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision | |
14381 | insns belong to Neon, and are handled elsewhere. */ | |
14382 | ||
14383 | static void | |
14384 | do_vfp_nsyn_ldm_stm (int is_dbmode) | |
14385 | { | |
14386 | int is_ldm = (inst.instruction & (1 << 20)) != 0; | |
14387 | if (is_ldm) | |
14388 | { | |
14389 | if (is_dbmode) | |
477330fc | 14390 | do_vfp_nsyn_opcode ("fldmdbs"); |
037e8744 | 14391 | else |
477330fc | 14392 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 JB |
14393 | } |
14394 | else | |
14395 | { | |
14396 | if (is_dbmode) | |
477330fc | 14397 | do_vfp_nsyn_opcode ("fstmdbs"); |
037e8744 | 14398 | else |
477330fc | 14399 | do_vfp_nsyn_opcode ("fstmias"); |
037e8744 JB |
14400 | } |
14401 | } | |
14402 | ||
037e8744 JB |
14403 | static void |
14404 | do_vfp_nsyn_sqrt (void) | |
14405 | { | |
9db2f6b4 RL |
14406 | enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL); |
14407 | neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP); | |
5f4273c7 | 14408 | |
9db2f6b4 RL |
14409 | if (rs == NS_FF || rs == NS_HH) |
14410 | { | |
14411 | do_vfp_nsyn_opcode ("fsqrts"); | |
14412 | ||
14413 | /* ARMv8.2 fp16 instruction. */ | |
14414 | if (rs == NS_HH) | |
14415 | do_scalar_fp16_v82_encode (); | |
14416 | } | |
037e8744 JB |
14417 | else |
14418 | do_vfp_nsyn_opcode ("fsqrtd"); | |
14419 | } | |
14420 | ||
14421 | static void | |
14422 | do_vfp_nsyn_div (void) | |
14423 | { | |
9db2f6b4 | 14424 | enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL); |
037e8744 | 14425 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, |
9db2f6b4 | 14426 | N_F_ALL | N_KEY | N_VFP); |
5f4273c7 | 14427 | |
9db2f6b4 RL |
14428 | if (rs == NS_FFF || rs == NS_HHH) |
14429 | { | |
14430 | do_vfp_nsyn_opcode ("fdivs"); | |
14431 | ||
14432 | /* ARMv8.2 fp16 instruction. */ | |
14433 | if (rs == NS_HHH) | |
14434 | do_scalar_fp16_v82_encode (); | |
14435 | } | |
037e8744 JB |
14436 | else |
14437 | do_vfp_nsyn_opcode ("fdivd"); | |
14438 | } | |
14439 | ||
14440 | static void | |
14441 | do_vfp_nsyn_nmul (void) | |
14442 | { | |
9db2f6b4 | 14443 | enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL); |
037e8744 | 14444 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, |
9db2f6b4 | 14445 | N_F_ALL | N_KEY | N_VFP); |
5f4273c7 | 14446 | |
9db2f6b4 | 14447 | if (rs == NS_FFF || rs == NS_HHH) |
037e8744 | 14448 | { |
88714cb8 | 14449 | NEON_ENCODE (SINGLE, inst); |
037e8744 | 14450 | do_vfp_sp_dyadic (); |
9db2f6b4 RL |
14451 | |
14452 | /* ARMv8.2 fp16 instruction. */ | |
14453 | if (rs == NS_HHH) | |
14454 | do_scalar_fp16_v82_encode (); | |
037e8744 JB |
14455 | } |
14456 | else | |
14457 | { | |
88714cb8 | 14458 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
14459 | do_vfp_dp_rd_rn_rm (); |
14460 | } | |
14461 | do_vfp_cond_or_thumb (); | |
9db2f6b4 | 14462 | |
037e8744 JB |
14463 | } |
14464 | ||
14465 | static void | |
14466 | do_vfp_nsyn_cmp (void) | |
14467 | { | |
9db2f6b4 | 14468 | enum neon_shape rs; |
037e8744 JB |
14469 | if (inst.operands[1].isreg) |
14470 | { | |
9db2f6b4 RL |
14471 | rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL); |
14472 | neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP); | |
5f4273c7 | 14473 | |
9db2f6b4 | 14474 | if (rs == NS_FF || rs == NS_HH) |
477330fc RM |
14475 | { |
14476 | NEON_ENCODE (SINGLE, inst); | |
14477 | do_vfp_sp_monadic (); | |
14478 | } | |
037e8744 | 14479 | else |
477330fc RM |
14480 | { |
14481 | NEON_ENCODE (DOUBLE, inst); | |
14482 | do_vfp_dp_rd_rm (); | |
14483 | } | |
037e8744 JB |
14484 | } |
14485 | else | |
14486 | { | |
9db2f6b4 RL |
14487 | rs = neon_select_shape (NS_HI, NS_FI, NS_DI, NS_NULL); |
14488 | neon_check_type (2, rs, N_F_ALL | N_KEY | N_VFP, N_EQK); | |
037e8744 JB |
14489 | |
14490 | switch (inst.instruction & 0x0fffffff) | |
477330fc RM |
14491 | { |
14492 | case N_MNEM_vcmp: | |
14493 | inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; | |
14494 | break; | |
14495 | case N_MNEM_vcmpe: | |
14496 | inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; | |
14497 | break; | |
14498 | default: | |
14499 | abort (); | |
14500 | } | |
5f4273c7 | 14501 | |
9db2f6b4 | 14502 | if (rs == NS_FI || rs == NS_HI) |
477330fc RM |
14503 | { |
14504 | NEON_ENCODE (SINGLE, inst); | |
14505 | do_vfp_sp_compare_z (); | |
14506 | } | |
037e8744 | 14507 | else |
477330fc RM |
14508 | { |
14509 | NEON_ENCODE (DOUBLE, inst); | |
14510 | do_vfp_dp_rd (); | |
14511 | } | |
037e8744 JB |
14512 | } |
14513 | do_vfp_cond_or_thumb (); | |
9db2f6b4 RL |
14514 | |
14515 | /* ARMv8.2 fp16 instruction. */ | |
14516 | if (rs == NS_HI || rs == NS_HH) | |
14517 | do_scalar_fp16_v82_encode (); | |
037e8744 JB |
14518 | } |
14519 | ||
14520 | static void | |
14521 | nsyn_insert_sp (void) | |
14522 | { | |
14523 | inst.operands[1] = inst.operands[0]; | |
14524 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
fdfde340 | 14525 | inst.operands[0].reg = REG_SP; |
037e8744 JB |
14526 | inst.operands[0].isreg = 1; |
14527 | inst.operands[0].writeback = 1; | |
14528 | inst.operands[0].present = 1; | |
14529 | } | |
14530 | ||
14531 | static void | |
14532 | do_vfp_nsyn_push (void) | |
14533 | { | |
14534 | nsyn_insert_sp (); | |
b126985e NC |
14535 | |
14536 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
14537 | _("register list must contain at least 1 and at most 16 " | |
14538 | "registers")); | |
14539 | ||
037e8744 JB |
14540 | if (inst.operands[1].issingle) |
14541 | do_vfp_nsyn_opcode ("fstmdbs"); | |
14542 | else | |
14543 | do_vfp_nsyn_opcode ("fstmdbd"); | |
14544 | } | |
14545 | ||
14546 | static void | |
14547 | do_vfp_nsyn_pop (void) | |
14548 | { | |
14549 | nsyn_insert_sp (); | |
b126985e NC |
14550 | |
14551 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
14552 | _("register list must contain at least 1 and at most 16 " | |
14553 | "registers")); | |
14554 | ||
037e8744 | 14555 | if (inst.operands[1].issingle) |
22b5b651 | 14556 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 | 14557 | else |
22b5b651 | 14558 | do_vfp_nsyn_opcode ("fldmiad"); |
037e8744 JB |
14559 | } |
14560 | ||
14561 | /* Fix up Neon data-processing instructions, ORing in the correct bits for | |
14562 | ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ | |
14563 | ||
88714cb8 DG |
14564 | static void |
14565 | neon_dp_fixup (struct arm_it* insn) | |
037e8744 | 14566 | { |
88714cb8 DG |
14567 | unsigned int i = insn->instruction; |
14568 | insn->is_neon = 1; | |
14569 | ||
037e8744 JB |
14570 | if (thumb_mode) |
14571 | { | |
14572 | /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ | |
14573 | if (i & (1 << 24)) | |
477330fc | 14574 | i |= 1 << 28; |
5f4273c7 | 14575 | |
037e8744 | 14576 | i &= ~(1 << 24); |
5f4273c7 | 14577 | |
037e8744 JB |
14578 | i |= 0xef000000; |
14579 | } | |
14580 | else | |
14581 | i |= 0xf2000000; | |
5f4273c7 | 14582 | |
88714cb8 | 14583 | insn->instruction = i; |
037e8744 JB |
14584 | } |
14585 | ||
14586 | /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 | |
14587 | (0, 1, 2, 3). */ | |
14588 | ||
14589 | static unsigned | |
14590 | neon_logbits (unsigned x) | |
14591 | { | |
14592 | return ffs (x) - 4; | |
14593 | } | |
14594 | ||
14595 | #define LOW4(R) ((R) & 0xf) | |
14596 | #define HI1(R) (((R) >> 4) & 1) | |
14597 | ||
14598 | /* Encode insns with bit pattern: | |
14599 | ||
14600 | |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
14601 | | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | | |
5f4273c7 | 14602 | |
037e8744 JB |
14603 | SIZE is passed in bits. -1 means size field isn't changed, in case it has a |
14604 | different meaning for some instruction. */ | |
14605 | ||
14606 | static void | |
14607 | neon_three_same (int isquad, int ubit, int size) | |
14608 | { | |
14609 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14610 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14611 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14612 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14613 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14614 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14615 | inst.instruction |= (isquad != 0) << 6; | |
14616 | inst.instruction |= (ubit != 0) << 24; | |
14617 | if (size != -1) | |
14618 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 14619 | |
88714cb8 | 14620 | neon_dp_fixup (&inst); |
037e8744 JB |
14621 | } |
14622 | ||
14623 | /* Encode instructions of the form: | |
14624 | ||
14625 | |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| | |
14626 | | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | | |
5287ad62 JB |
14627 | |
14628 | Don't write size if SIZE == -1. */ | |
14629 | ||
14630 | static void | |
14631 | neon_two_same (int qbit, int ubit, int size) | |
14632 | { | |
14633 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14634 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14635 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14636 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14637 | inst.instruction |= (qbit != 0) << 6; | |
14638 | inst.instruction |= (ubit != 0) << 24; | |
14639 | ||
14640 | if (size != -1) | |
14641 | inst.instruction |= neon_logbits (size) << 18; | |
14642 | ||
88714cb8 | 14643 | neon_dp_fixup (&inst); |
5287ad62 JB |
14644 | } |
14645 | ||
14646 | /* Neon instruction encoders, in approximate order of appearance. */ | |
14647 | ||
14648 | static void | |
14649 | do_neon_dyadic_i_su (void) | |
14650 | { | |
037e8744 | 14651 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14652 | struct neon_type_el et = neon_check_type (3, rs, |
14653 | N_EQK, N_EQK, N_SU_32 | N_KEY); | |
037e8744 | 14654 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14655 | } |
14656 | ||
14657 | static void | |
14658 | do_neon_dyadic_i64_su (void) | |
14659 | { | |
037e8744 | 14660 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14661 | struct neon_type_el et = neon_check_type (3, rs, |
14662 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
037e8744 | 14663 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14664 | } |
14665 | ||
14666 | static void | |
14667 | neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, | |
477330fc | 14668 | unsigned immbits) |
5287ad62 JB |
14669 | { |
14670 | unsigned size = et.size >> 3; | |
14671 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14672 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14673 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14674 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14675 | inst.instruction |= (isquad != 0) << 6; | |
14676 | inst.instruction |= immbits << 16; | |
14677 | inst.instruction |= (size >> 3) << 7; | |
14678 | inst.instruction |= (size & 0x7) << 19; | |
14679 | if (write_ubit) | |
14680 | inst.instruction |= (uval != 0) << 24; | |
14681 | ||
88714cb8 | 14682 | neon_dp_fixup (&inst); |
5287ad62 JB |
14683 | } |
14684 | ||
14685 | static void | |
14686 | do_neon_shl_imm (void) | |
14687 | { | |
14688 | if (!inst.operands[2].isreg) | |
14689 | { | |
037e8744 | 14690 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 14691 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); |
cb3b1e65 JB |
14692 | int imm = inst.operands[2].imm; |
14693 | ||
14694 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
14695 | _("immediate out of range for shift")); | |
88714cb8 | 14696 | NEON_ENCODE (IMMED, inst); |
cb3b1e65 | 14697 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
14698 | } |
14699 | else | |
14700 | { | |
037e8744 | 14701 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14702 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14703 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); |
627907b7 JB |
14704 | unsigned int tmp; |
14705 | ||
14706 | /* VSHL/VQSHL 3-register variants have syntax such as: | |
477330fc RM |
14707 | vshl.xx Dd, Dm, Dn |
14708 | whereas other 3-register operations encoded by neon_three_same have | |
14709 | syntax like: | |
14710 | vadd.xx Dd, Dn, Dm | |
14711 | (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg | |
14712 | here. */ | |
627907b7 JB |
14713 | tmp = inst.operands[2].reg; |
14714 | inst.operands[2].reg = inst.operands[1].reg; | |
14715 | inst.operands[1].reg = tmp; | |
88714cb8 | 14716 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14717 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14718 | } |
14719 | } | |
14720 | ||
14721 | static void | |
14722 | do_neon_qshl_imm (void) | |
14723 | { | |
14724 | if (!inst.operands[2].isreg) | |
14725 | { | |
037e8744 | 14726 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 14727 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
cb3b1e65 | 14728 | int imm = inst.operands[2].imm; |
627907b7 | 14729 | |
cb3b1e65 JB |
14730 | constraint (imm < 0 || (unsigned)imm >= et.size, |
14731 | _("immediate out of range for shift")); | |
88714cb8 | 14732 | NEON_ENCODE (IMMED, inst); |
cb3b1e65 | 14733 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm); |
5287ad62 JB |
14734 | } |
14735 | else | |
14736 | { | |
037e8744 | 14737 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14738 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14739 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); |
627907b7 JB |
14740 | unsigned int tmp; |
14741 | ||
14742 | /* See note in do_neon_shl_imm. */ | |
14743 | tmp = inst.operands[2].reg; | |
14744 | inst.operands[2].reg = inst.operands[1].reg; | |
14745 | inst.operands[1].reg = tmp; | |
88714cb8 | 14746 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14747 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14748 | } |
14749 | } | |
14750 | ||
627907b7 JB |
14751 | static void |
14752 | do_neon_rshl (void) | |
14753 | { | |
14754 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
14755 | struct neon_type_el et = neon_check_type (3, rs, | |
14756 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
14757 | unsigned int tmp; | |
14758 | ||
14759 | tmp = inst.operands[2].reg; | |
14760 | inst.operands[2].reg = inst.operands[1].reg; | |
14761 | inst.operands[1].reg = tmp; | |
14762 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
14763 | } | |
14764 | ||
5287ad62 JB |
14765 | static int |
14766 | neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) | |
14767 | { | |
036dc3f7 PB |
14768 | /* Handle .I8 pseudo-instructions. */ |
14769 | if (size == 8) | |
5287ad62 | 14770 | { |
5287ad62 | 14771 | /* Unfortunately, this will make everything apart from zero out-of-range. |
477330fc RM |
14772 | FIXME is this the intended semantics? There doesn't seem much point in |
14773 | accepting .I8 if so. */ | |
5287ad62 JB |
14774 | immediate |= immediate << 8; |
14775 | size = 16; | |
036dc3f7 PB |
14776 | } |
14777 | ||
14778 | if (size >= 32) | |
14779 | { | |
14780 | if (immediate == (immediate & 0x000000ff)) | |
14781 | { | |
14782 | *immbits = immediate; | |
14783 | return 0x1; | |
14784 | } | |
14785 | else if (immediate == (immediate & 0x0000ff00)) | |
14786 | { | |
14787 | *immbits = immediate >> 8; | |
14788 | return 0x3; | |
14789 | } | |
14790 | else if (immediate == (immediate & 0x00ff0000)) | |
14791 | { | |
14792 | *immbits = immediate >> 16; | |
14793 | return 0x5; | |
14794 | } | |
14795 | else if (immediate == (immediate & 0xff000000)) | |
14796 | { | |
14797 | *immbits = immediate >> 24; | |
14798 | return 0x7; | |
14799 | } | |
14800 | if ((immediate & 0xffff) != (immediate >> 16)) | |
14801 | goto bad_immediate; | |
14802 | immediate &= 0xffff; | |
5287ad62 JB |
14803 | } |
14804 | ||
14805 | if (immediate == (immediate & 0x000000ff)) | |
14806 | { | |
14807 | *immbits = immediate; | |
036dc3f7 | 14808 | return 0x9; |
5287ad62 JB |
14809 | } |
14810 | else if (immediate == (immediate & 0x0000ff00)) | |
14811 | { | |
14812 | *immbits = immediate >> 8; | |
036dc3f7 | 14813 | return 0xb; |
5287ad62 JB |
14814 | } |
14815 | ||
14816 | bad_immediate: | |
dcbf9037 | 14817 | first_error (_("immediate value out of range")); |
5287ad62 JB |
14818 | return FAIL; |
14819 | } | |
14820 | ||
5287ad62 JB |
14821 | static void |
14822 | do_neon_logic (void) | |
14823 | { | |
14824 | if (inst.operands[2].present && inst.operands[2].isreg) | |
14825 | { | |
037e8744 | 14826 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14827 | neon_check_type (3, rs, N_IGNORE_TYPE); |
14828 | /* U bit and size field were set as part of the bitmask. */ | |
88714cb8 | 14829 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14830 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14831 | } |
14832 | else | |
14833 | { | |
4316f0d2 DG |
14834 | const int three_ops_form = (inst.operands[2].present |
14835 | && !inst.operands[2].isreg); | |
14836 | const int immoperand = (three_ops_form ? 2 : 1); | |
14837 | enum neon_shape rs = (three_ops_form | |
14838 | ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL) | |
14839 | : neon_select_shape (NS_DI, NS_QI, NS_NULL)); | |
037e8744 | 14840 | struct neon_type_el et = neon_check_type (2, rs, |
477330fc | 14841 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); |
21d799b5 | 14842 | enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff; |
5287ad62 JB |
14843 | unsigned immbits; |
14844 | int cmode; | |
5f4273c7 | 14845 | |
5287ad62 | 14846 | if (et.type == NT_invtype) |
477330fc | 14847 | return; |
5f4273c7 | 14848 | |
4316f0d2 DG |
14849 | if (three_ops_form) |
14850 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
14851 | _("first and second operands shall be the same register")); | |
14852 | ||
88714cb8 | 14853 | NEON_ENCODE (IMMED, inst); |
5287ad62 | 14854 | |
4316f0d2 | 14855 | immbits = inst.operands[immoperand].imm; |
036dc3f7 PB |
14856 | if (et.size == 64) |
14857 | { | |
14858 | /* .i64 is a pseudo-op, so the immediate must be a repeating | |
14859 | pattern. */ | |
4316f0d2 DG |
14860 | if (immbits != (inst.operands[immoperand].regisimm ? |
14861 | inst.operands[immoperand].reg : 0)) | |
036dc3f7 PB |
14862 | { |
14863 | /* Set immbits to an invalid constant. */ | |
14864 | immbits = 0xdeadbeef; | |
14865 | } | |
14866 | } | |
14867 | ||
5287ad62 | 14868 | switch (opcode) |
477330fc RM |
14869 | { |
14870 | case N_MNEM_vbic: | |
14871 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14872 | break; | |
14873 | ||
14874 | case N_MNEM_vorr: | |
14875 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14876 | break; | |
14877 | ||
14878 | case N_MNEM_vand: | |
14879 | /* Pseudo-instruction for VBIC. */ | |
14880 | neon_invert_size (&immbits, 0, et.size); | |
14881 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14882 | break; | |
14883 | ||
14884 | case N_MNEM_vorn: | |
14885 | /* Pseudo-instruction for VORR. */ | |
14886 | neon_invert_size (&immbits, 0, et.size); | |
14887 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14888 | break; | |
14889 | ||
14890 | default: | |
14891 | abort (); | |
14892 | } | |
5287ad62 JB |
14893 | |
14894 | if (cmode == FAIL) | |
477330fc | 14895 | return; |
5287ad62 | 14896 | |
037e8744 | 14897 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14898 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14899 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14900 | inst.instruction |= cmode << 8; | |
14901 | neon_write_immbits (immbits); | |
5f4273c7 | 14902 | |
88714cb8 | 14903 | neon_dp_fixup (&inst); |
5287ad62 JB |
14904 | } |
14905 | } | |
14906 | ||
14907 | static void | |
14908 | do_neon_bitfield (void) | |
14909 | { | |
037e8744 | 14910 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 14911 | neon_check_type (3, rs, N_IGNORE_TYPE); |
037e8744 | 14912 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14913 | } |
14914 | ||
14915 | static void | |
dcbf9037 | 14916 | neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, |
477330fc | 14917 | unsigned destbits) |
5287ad62 | 14918 | { |
037e8744 | 14919 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 14920 | struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, |
477330fc | 14921 | types | N_KEY); |
5287ad62 JB |
14922 | if (et.type == NT_float) |
14923 | { | |
88714cb8 | 14924 | NEON_ENCODE (FLOAT, inst); |
cc933301 | 14925 | neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1); |
5287ad62 JB |
14926 | } |
14927 | else | |
14928 | { | |
88714cb8 | 14929 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14930 | neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); |
5287ad62 JB |
14931 | } |
14932 | } | |
14933 | ||
14934 | static void | |
14935 | do_neon_dyadic_if_su (void) | |
14936 | { | |
dcbf9037 | 14937 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
14938 | } |
14939 | ||
14940 | static void | |
14941 | do_neon_dyadic_if_su_d (void) | |
14942 | { | |
14943 | /* This version only allow D registers, but that constraint is enforced during | |
14944 | operand parsing so we don't need to do anything extra here. */ | |
dcbf9037 | 14945 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
14946 | } |
14947 | ||
5287ad62 JB |
14948 | static void |
14949 | do_neon_dyadic_if_i_d (void) | |
14950 | { | |
428e3f1f PB |
14951 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
14952 | affected if we specify unsigned args. */ | |
14953 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
5287ad62 JB |
14954 | } |
14955 | ||
037e8744 JB |
14956 | enum vfp_or_neon_is_neon_bits |
14957 | { | |
14958 | NEON_CHECK_CC = 1, | |
73924fbc MGD |
14959 | NEON_CHECK_ARCH = 2, |
14960 | NEON_CHECK_ARCH8 = 4 | |
037e8744 JB |
14961 | }; |
14962 | ||
14963 | /* Call this function if an instruction which may have belonged to the VFP or | |
14964 | Neon instruction sets, but turned out to be a Neon instruction (due to the | |
14965 | operand types involved, etc.). We have to check and/or fix-up a couple of | |
14966 | things: | |
14967 | ||
14968 | - Make sure the user hasn't attempted to make a Neon instruction | |
14969 | conditional. | |
14970 | - Alter the value in the condition code field if necessary. | |
14971 | - Make sure that the arch supports Neon instructions. | |
14972 | ||
14973 | Which of these operations take place depends on bits from enum | |
14974 | vfp_or_neon_is_neon_bits. | |
14975 | ||
14976 | WARNING: This function has side effects! If NEON_CHECK_CC is used and the | |
14977 | current instruction's condition is COND_ALWAYS, the condition field is | |
14978 | changed to inst.uncond_value. This is necessary because instructions shared | |
14979 | between VFP and Neon may be conditional for the VFP variants only, and the | |
14980 | unconditional Neon version must have, e.g., 0xF in the condition field. */ | |
14981 | ||
14982 | static int | |
14983 | vfp_or_neon_is_neon (unsigned check) | |
14984 | { | |
14985 | /* Conditions are always legal in Thumb mode (IT blocks). */ | |
14986 | if (!thumb_mode && (check & NEON_CHECK_CC)) | |
14987 | { | |
14988 | if (inst.cond != COND_ALWAYS) | |
477330fc RM |
14989 | { |
14990 | first_error (_(BAD_COND)); | |
14991 | return FAIL; | |
14992 | } | |
037e8744 | 14993 | if (inst.uncond_value != -1) |
477330fc | 14994 | inst.instruction |= inst.uncond_value << 28; |
037e8744 | 14995 | } |
5f4273c7 | 14996 | |
037e8744 | 14997 | if ((check & NEON_CHECK_ARCH) |
73924fbc MGD |
14998 | && !mark_feature_used (&fpu_neon_ext_v1)) |
14999 | { | |
15000 | first_error (_(BAD_FPU)); | |
15001 | return FAIL; | |
15002 | } | |
15003 | ||
15004 | if ((check & NEON_CHECK_ARCH8) | |
15005 | && !mark_feature_used (&fpu_neon_ext_armv8)) | |
037e8744 JB |
15006 | { |
15007 | first_error (_(BAD_FPU)); | |
15008 | return FAIL; | |
15009 | } | |
5f4273c7 | 15010 | |
037e8744 JB |
15011 | return SUCCESS; |
15012 | } | |
15013 | ||
5287ad62 JB |
15014 | static void |
15015 | do_neon_addsub_if_i (void) | |
15016 | { | |
037e8744 JB |
15017 | if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) |
15018 | return; | |
15019 | ||
15020 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
15021 | return; | |
15022 | ||
5287ad62 JB |
15023 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
15024 | affected if we specify unsigned args. */ | |
dcbf9037 | 15025 | neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); |
5287ad62 JB |
15026 | } |
15027 | ||
15028 | /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the | |
15029 | result to be: | |
15030 | V<op> A,B (A is operand 0, B is operand 2) | |
15031 | to mean: | |
15032 | V<op> A,B,A | |
15033 | not: | |
15034 | V<op> A,B,B | |
15035 | so handle that case specially. */ | |
15036 | ||
15037 | static void | |
15038 | neon_exchange_operands (void) | |
15039 | { | |
5287ad62 JB |
15040 | if (inst.operands[1].present) |
15041 | { | |
e1fa0163 NC |
15042 | void *scratch = xmalloc (sizeof (inst.operands[0])); |
15043 | ||
5287ad62 JB |
15044 | /* Swap operands[1] and operands[2]. */ |
15045 | memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); | |
15046 | inst.operands[1] = inst.operands[2]; | |
15047 | memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); | |
e1fa0163 | 15048 | free (scratch); |
5287ad62 JB |
15049 | } |
15050 | else | |
15051 | { | |
15052 | inst.operands[1] = inst.operands[2]; | |
15053 | inst.operands[2] = inst.operands[0]; | |
15054 | } | |
15055 | } | |
15056 | ||
15057 | static void | |
15058 | neon_compare (unsigned regtypes, unsigned immtypes, int invert) | |
15059 | { | |
15060 | if (inst.operands[2].isreg) | |
15061 | { | |
15062 | if (invert) | |
477330fc | 15063 | neon_exchange_operands (); |
dcbf9037 | 15064 | neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); |
5287ad62 JB |
15065 | } |
15066 | else | |
15067 | { | |
037e8744 | 15068 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
dcbf9037 | 15069 | struct neon_type_el et = neon_check_type (2, rs, |
477330fc | 15070 | N_EQK | N_SIZ, immtypes | N_KEY); |
5287ad62 | 15071 | |
88714cb8 | 15072 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
15073 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15074 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15075 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15076 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 15077 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
15078 | inst.instruction |= (et.type == NT_float) << 10; |
15079 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 15080 | |
88714cb8 | 15081 | neon_dp_fixup (&inst); |
5287ad62 JB |
15082 | } |
15083 | } | |
15084 | ||
15085 | static void | |
15086 | do_neon_cmp (void) | |
15087 | { | |
cc933301 | 15088 | neon_compare (N_SUF_32, N_S_32 | N_F_16_32, FALSE); |
5287ad62 JB |
15089 | } |
15090 | ||
15091 | static void | |
15092 | do_neon_cmp_inv (void) | |
15093 | { | |
cc933301 | 15094 | neon_compare (N_SUF_32, N_S_32 | N_F_16_32, TRUE); |
5287ad62 JB |
15095 | } |
15096 | ||
15097 | static void | |
15098 | do_neon_ceq (void) | |
15099 | { | |
15100 | neon_compare (N_IF_32, N_IF_32, FALSE); | |
15101 | } | |
15102 | ||
15103 | /* For multiply instructions, we have the possibility of 16-bit or 32-bit | |
15104 | scalars, which are encoded in 5 bits, M : Rm. | |
15105 | For 16-bit scalars, the register is encoded in Rm[2:0] and the index in | |
15106 | M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the | |
c604a79a JW |
15107 | index in M. |
15108 | ||
15109 | Dot Product instructions are similar to multiply instructions except elsize | |
15110 | should always be 32. | |
15111 | ||
15112 | This function translates SCALAR, which is GAS's internal encoding of indexed | |
15113 | scalar register, to raw encoding. There is also register and index range | |
15114 | check based on ELSIZE. */ | |
5287ad62 JB |
15115 | |
15116 | static unsigned | |
15117 | neon_scalar_for_mul (unsigned scalar, unsigned elsize) | |
15118 | { | |
dcbf9037 JB |
15119 | unsigned regno = NEON_SCALAR_REG (scalar); |
15120 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
5287ad62 JB |
15121 | |
15122 | switch (elsize) | |
15123 | { | |
15124 | case 16: | |
15125 | if (regno > 7 || elno > 3) | |
477330fc | 15126 | goto bad_scalar; |
5287ad62 | 15127 | return regno | (elno << 3); |
5f4273c7 | 15128 | |
5287ad62 JB |
15129 | case 32: |
15130 | if (regno > 15 || elno > 1) | |
477330fc | 15131 | goto bad_scalar; |
5287ad62 JB |
15132 | return regno | (elno << 4); |
15133 | ||
15134 | default: | |
15135 | bad_scalar: | |
dcbf9037 | 15136 | first_error (_("scalar out of range for multiply instruction")); |
5287ad62 JB |
15137 | } |
15138 | ||
15139 | return 0; | |
15140 | } | |
15141 | ||
15142 | /* Encode multiply / multiply-accumulate scalar instructions. */ | |
15143 | ||
15144 | static void | |
15145 | neon_mul_mac (struct neon_type_el et, int ubit) | |
15146 | { | |
dcbf9037 JB |
15147 | unsigned scalar; |
15148 | ||
15149 | /* Give a more helpful error message if we have an invalid type. */ | |
15150 | if (et.type == NT_invtype) | |
15151 | return; | |
5f4273c7 | 15152 | |
dcbf9037 | 15153 | scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); |
5287ad62 JB |
15154 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15155 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15156 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15157 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15158 | inst.instruction |= LOW4 (scalar); | |
15159 | inst.instruction |= HI1 (scalar) << 5; | |
15160 | inst.instruction |= (et.type == NT_float) << 8; | |
15161 | inst.instruction |= neon_logbits (et.size) << 20; | |
15162 | inst.instruction |= (ubit != 0) << 24; | |
15163 | ||
88714cb8 | 15164 | neon_dp_fixup (&inst); |
5287ad62 JB |
15165 | } |
15166 | ||
15167 | static void | |
15168 | do_neon_mac_maybe_scalar (void) | |
15169 | { | |
037e8744 JB |
15170 | if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) |
15171 | return; | |
15172 | ||
15173 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
15174 | return; | |
15175 | ||
5287ad62 JB |
15176 | if (inst.operands[2].isscalar) |
15177 | { | |
037e8744 | 15178 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 | 15179 | struct neon_type_el et = neon_check_type (3, rs, |
589a7d88 | 15180 | N_EQK, N_EQK, N_I16 | N_I32 | N_F_16_32 | N_KEY); |
88714cb8 | 15181 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 15182 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
15183 | } |
15184 | else | |
428e3f1f PB |
15185 | { |
15186 | /* The "untyped" case can't happen. Do this to stop the "U" bit being | |
15187 | affected if we specify unsigned args. */ | |
15188 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
15189 | } | |
5287ad62 JB |
15190 | } |
15191 | ||
62f3b8c8 PB |
15192 | static void |
15193 | do_neon_fmac (void) | |
15194 | { | |
15195 | if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS) | |
15196 | return; | |
15197 | ||
15198 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
15199 | return; | |
15200 | ||
15201 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
15202 | } | |
15203 | ||
5287ad62 JB |
15204 | static void |
15205 | do_neon_tst (void) | |
15206 | { | |
037e8744 | 15207 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
15208 | struct neon_type_el et = neon_check_type (3, rs, |
15209 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
037e8744 | 15210 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
15211 | } |
15212 | ||
15213 | /* VMUL with 3 registers allows the P8 type. The scalar version supports the | |
15214 | same types as the MAC equivalents. The polynomial type for this instruction | |
15215 | is encoded the same as the integer type. */ | |
15216 | ||
15217 | static void | |
15218 | do_neon_mul (void) | |
15219 | { | |
037e8744 JB |
15220 | if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) |
15221 | return; | |
15222 | ||
15223 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
15224 | return; | |
15225 | ||
5287ad62 JB |
15226 | if (inst.operands[2].isscalar) |
15227 | do_neon_mac_maybe_scalar (); | |
15228 | else | |
cc933301 | 15229 | neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F16 | N_F32 | N_P8, 0); |
5287ad62 JB |
15230 | } |
15231 | ||
15232 | static void | |
15233 | do_neon_qdmulh (void) | |
15234 | { | |
15235 | if (inst.operands[2].isscalar) | |
15236 | { | |
037e8744 | 15237 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 | 15238 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 15239 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); |
88714cb8 | 15240 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 15241 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
15242 | } |
15243 | else | |
15244 | { | |
037e8744 | 15245 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 15246 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 15247 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); |
88714cb8 | 15248 | NEON_ENCODE (INTEGER, inst); |
5287ad62 | 15249 | /* The U bit (rounding) comes from bit mask. */ |
037e8744 | 15250 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
15251 | } |
15252 | } | |
15253 | ||
643afb90 MW |
15254 | static void |
15255 | do_neon_qrdmlah (void) | |
15256 | { | |
15257 | /* Check we're on the correct architecture. */ | |
15258 | if (!mark_feature_used (&fpu_neon_ext_armv8)) | |
15259 | inst.error = | |
15260 | _("instruction form not available on this architecture."); | |
15261 | else if (!mark_feature_used (&fpu_neon_ext_v8_1)) | |
15262 | { | |
15263 | as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD.")); | |
15264 | record_feature_use (&fpu_neon_ext_v8_1); | |
15265 | } | |
15266 | ||
15267 | if (inst.operands[2].isscalar) | |
15268 | { | |
15269 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); | |
15270 | struct neon_type_el et = neon_check_type (3, rs, | |
15271 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
15272 | NEON_ENCODE (SCALAR, inst); | |
15273 | neon_mul_mac (et, neon_quad (rs)); | |
15274 | } | |
15275 | else | |
15276 | { | |
15277 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
15278 | struct neon_type_el et = neon_check_type (3, rs, | |
15279 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
15280 | NEON_ENCODE (INTEGER, inst); | |
15281 | /* The U bit (rounding) comes from bit mask. */ | |
15282 | neon_three_same (neon_quad (rs), 0, et.size); | |
15283 | } | |
15284 | } | |
15285 | ||
5287ad62 JB |
15286 | static void |
15287 | do_neon_fcmp_absolute (void) | |
15288 | { | |
037e8744 | 15289 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
cc933301 JW |
15290 | struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK, |
15291 | N_F_16_32 | N_KEY); | |
5287ad62 | 15292 | /* Size field comes from bit mask. */ |
cc933301 | 15293 | neon_three_same (neon_quad (rs), 1, et.size == 16 ? (int) et.size : -1); |
5287ad62 JB |
15294 | } |
15295 | ||
15296 | static void | |
15297 | do_neon_fcmp_absolute_inv (void) | |
15298 | { | |
15299 | neon_exchange_operands (); | |
15300 | do_neon_fcmp_absolute (); | |
15301 | } | |
15302 | ||
15303 | static void | |
15304 | do_neon_step (void) | |
15305 | { | |
037e8744 | 15306 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
cc933301 JW |
15307 | struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK, |
15308 | N_F_16_32 | N_KEY); | |
15309 | neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1); | |
5287ad62 JB |
15310 | } |
15311 | ||
15312 | static void | |
15313 | do_neon_abs_neg (void) | |
15314 | { | |
037e8744 JB |
15315 | enum neon_shape rs; |
15316 | struct neon_type_el et; | |
5f4273c7 | 15317 | |
037e8744 JB |
15318 | if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) |
15319 | return; | |
15320 | ||
15321 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
15322 | return; | |
15323 | ||
15324 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
cc933301 | 15325 | et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY); |
5f4273c7 | 15326 | |
5287ad62 JB |
15327 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15328 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15329 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15330 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 15331 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
15332 | inst.instruction |= (et.type == NT_float) << 10; |
15333 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 15334 | |
88714cb8 | 15335 | neon_dp_fixup (&inst); |
5287ad62 JB |
15336 | } |
15337 | ||
15338 | static void | |
15339 | do_neon_sli (void) | |
15340 | { | |
037e8744 | 15341 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
15342 | struct neon_type_el et = neon_check_type (2, rs, |
15343 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
15344 | int imm = inst.operands[2].imm; | |
15345 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
477330fc | 15346 | _("immediate out of range for insert")); |
037e8744 | 15347 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
15348 | } |
15349 | ||
15350 | static void | |
15351 | do_neon_sri (void) | |
15352 | { | |
037e8744 | 15353 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
15354 | struct neon_type_el et = neon_check_type (2, rs, |
15355 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
15356 | int imm = inst.operands[2].imm; | |
15357 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 15358 | _("immediate out of range for insert")); |
037e8744 | 15359 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); |
5287ad62 JB |
15360 | } |
15361 | ||
15362 | static void | |
15363 | do_neon_qshlu_imm (void) | |
15364 | { | |
037e8744 | 15365 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
15366 | struct neon_type_el et = neon_check_type (2, rs, |
15367 | N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); | |
15368 | int imm = inst.operands[2].imm; | |
15369 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
477330fc | 15370 | _("immediate out of range for shift")); |
5287ad62 JB |
15371 | /* Only encodes the 'U present' variant of the instruction. |
15372 | In this case, signed types have OP (bit 8) set to 0. | |
15373 | Unsigned types have OP set to 1. */ | |
15374 | inst.instruction |= (et.type == NT_unsigned) << 8; | |
15375 | /* The rest of the bits are the same as other immediate shifts. */ | |
037e8744 | 15376 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
15377 | } |
15378 | ||
15379 | static void | |
15380 | do_neon_qmovn (void) | |
15381 | { | |
15382 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
15383 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
15384 | /* Saturating move where operands can be signed or unsigned, and the | |
15385 | destination has the same signedness. */ | |
88714cb8 | 15386 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
15387 | if (et.type == NT_unsigned) |
15388 | inst.instruction |= 0xc0; | |
15389 | else | |
15390 | inst.instruction |= 0x80; | |
15391 | neon_two_same (0, 1, et.size / 2); | |
15392 | } | |
15393 | ||
15394 | static void | |
15395 | do_neon_qmovun (void) | |
15396 | { | |
15397 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
15398 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
15399 | /* Saturating move with unsigned results. Operands must be signed. */ | |
88714cb8 | 15400 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
15401 | neon_two_same (0, 1, et.size / 2); |
15402 | } | |
15403 | ||
15404 | static void | |
15405 | do_neon_rshift_sat_narrow (void) | |
15406 | { | |
15407 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
15408 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
15409 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
15410 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
15411 | int imm = inst.operands[2].imm; | |
15412 | /* This gets the bounds check, size encoding and immediate bits calculation | |
15413 | right. */ | |
15414 | et.size /= 2; | |
5f4273c7 | 15415 | |
5287ad62 JB |
15416 | /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for |
15417 | VQMOVN.I<size> <Dd>, <Qm>. */ | |
15418 | if (imm == 0) | |
15419 | { | |
15420 | inst.operands[2].present = 0; | |
15421 | inst.instruction = N_MNEM_vqmovn; | |
15422 | do_neon_qmovn (); | |
15423 | return; | |
15424 | } | |
5f4273c7 | 15425 | |
5287ad62 | 15426 | constraint (imm < 1 || (unsigned)imm > et.size, |
477330fc | 15427 | _("immediate out of range")); |
5287ad62 JB |
15428 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); |
15429 | } | |
15430 | ||
15431 | static void | |
15432 | do_neon_rshift_sat_narrow_u (void) | |
15433 | { | |
15434 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
15435 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
15436 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
15437 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
15438 | int imm = inst.operands[2].imm; | |
15439 | /* This gets the bounds check, size encoding and immediate bits calculation | |
15440 | right. */ | |
15441 | et.size /= 2; | |
15442 | ||
15443 | /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for | |
15444 | VQMOVUN.I<size> <Dd>, <Qm>. */ | |
15445 | if (imm == 0) | |
15446 | { | |
15447 | inst.operands[2].present = 0; | |
15448 | inst.instruction = N_MNEM_vqmovun; | |
15449 | do_neon_qmovun (); | |
15450 | return; | |
15451 | } | |
15452 | ||
15453 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 15454 | _("immediate out of range")); |
5287ad62 JB |
15455 | /* FIXME: The manual is kind of unclear about what value U should have in |
15456 | VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it | |
15457 | must be 1. */ | |
15458 | neon_imm_shift (TRUE, 1, 0, et, et.size - imm); | |
15459 | } | |
15460 | ||
15461 | static void | |
15462 | do_neon_movn (void) | |
15463 | { | |
15464 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
15465 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
88714cb8 | 15466 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
15467 | neon_two_same (0, 1, et.size / 2); |
15468 | } | |
15469 | ||
15470 | static void | |
15471 | do_neon_rshift_narrow (void) | |
15472 | { | |
15473 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
15474 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
15475 | int imm = inst.operands[2].imm; | |
15476 | /* This gets the bounds check, size encoding and immediate bits calculation | |
15477 | right. */ | |
15478 | et.size /= 2; | |
5f4273c7 | 15479 | |
5287ad62 JB |
15480 | /* If immediate is zero then we are a pseudo-instruction for |
15481 | VMOVN.I<size> <Dd>, <Qm> */ | |
15482 | if (imm == 0) | |
15483 | { | |
15484 | inst.operands[2].present = 0; | |
15485 | inst.instruction = N_MNEM_vmovn; | |
15486 | do_neon_movn (); | |
15487 | return; | |
15488 | } | |
5f4273c7 | 15489 | |
5287ad62 | 15490 | constraint (imm < 1 || (unsigned)imm > et.size, |
477330fc | 15491 | _("immediate out of range for narrowing operation")); |
5287ad62 JB |
15492 | neon_imm_shift (FALSE, 0, 0, et, et.size - imm); |
15493 | } | |
15494 | ||
15495 | static void | |
15496 | do_neon_shll (void) | |
15497 | { | |
15498 | /* FIXME: Type checking when lengthening. */ | |
15499 | struct neon_type_el et = neon_check_type (2, NS_QDI, | |
15500 | N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); | |
15501 | unsigned imm = inst.operands[2].imm; | |
15502 | ||
15503 | if (imm == et.size) | |
15504 | { | |
15505 | /* Maximum shift variant. */ | |
88714cb8 | 15506 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
15507 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15508 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15509 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15510 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15511 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 15512 | |
88714cb8 | 15513 | neon_dp_fixup (&inst); |
5287ad62 JB |
15514 | } |
15515 | else | |
15516 | { | |
15517 | /* A more-specific type check for non-max versions. */ | |
15518 | et = neon_check_type (2, NS_QDI, | |
477330fc | 15519 | N_EQK | N_DBL, N_SU_32 | N_KEY); |
88714cb8 | 15520 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
15521 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); |
15522 | } | |
15523 | } | |
15524 | ||
037e8744 | 15525 | /* Check the various types for the VCVT instruction, and return which version |
5287ad62 JB |
15526 | the current instruction is. */ |
15527 | ||
6b9a8b67 MGD |
15528 | #define CVT_FLAVOUR_VAR \ |
15529 | CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \ | |
15530 | CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \ | |
15531 | CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \ | |
15532 | CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \ | |
15533 | /* Half-precision conversions. */ \ | |
cc933301 JW |
15534 | CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \ |
15535 | CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \ | |
15536 | CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \ | |
15537 | CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \ | |
6b9a8b67 MGD |
15538 | CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \ |
15539 | CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \ | |
9db2f6b4 RL |
15540 | /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \ |
15541 | Compared with single/double precision variants, only the co-processor \ | |
15542 | field is different, so the encoding flow is reused here. */ \ | |
15543 | CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \ | |
15544 | CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \ | |
15545 | CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\ | |
15546 | CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\ | |
6b9a8b67 MGD |
15547 | /* VFP instructions. */ \ |
15548 | CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \ | |
15549 | CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \ | |
15550 | CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \ | |
15551 | CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \ | |
15552 | CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \ | |
15553 | CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \ | |
15554 | /* VFP instructions with bitshift. */ \ | |
15555 | CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \ | |
15556 | CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \ | |
15557 | CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \ | |
15558 | CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \ | |
15559 | CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \ | |
15560 | CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \ | |
15561 | CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \ | |
15562 | CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL) | |
15563 | ||
15564 | #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \ | |
15565 | neon_cvt_flavour_##C, | |
15566 | ||
15567 | /* The different types of conversions we can do. */ | |
15568 | enum neon_cvt_flavour | |
15569 | { | |
15570 | CVT_FLAVOUR_VAR | |
15571 | neon_cvt_flavour_invalid, | |
15572 | neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64 | |
15573 | }; | |
15574 | ||
15575 | #undef CVT_VAR | |
15576 | ||
15577 | static enum neon_cvt_flavour | |
15578 | get_neon_cvt_flavour (enum neon_shape rs) | |
5287ad62 | 15579 | { |
6b9a8b67 MGD |
15580 | #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \ |
15581 | et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \ | |
15582 | if (et.type != NT_invtype) \ | |
15583 | { \ | |
15584 | inst.error = NULL; \ | |
15585 | return (neon_cvt_flavour_##C); \ | |
5287ad62 | 15586 | } |
6b9a8b67 | 15587 | |
5287ad62 | 15588 | struct neon_type_el et; |
037e8744 | 15589 | unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF |
477330fc | 15590 | || rs == NS_FF) ? N_VFP : 0; |
037e8744 JB |
15591 | /* The instruction versions which take an immediate take one register |
15592 | argument, which is extended to the width of the full register. Thus the | |
15593 | "source" and "destination" registers must have the same width. Hack that | |
15594 | here by making the size equal to the key (wider, in this case) operand. */ | |
15595 | unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; | |
5f4273c7 | 15596 | |
6b9a8b67 MGD |
15597 | CVT_FLAVOUR_VAR; |
15598 | ||
15599 | return neon_cvt_flavour_invalid; | |
5287ad62 JB |
15600 | #undef CVT_VAR |
15601 | } | |
15602 | ||
7e8e6784 MGD |
15603 | enum neon_cvt_mode |
15604 | { | |
15605 | neon_cvt_mode_a, | |
15606 | neon_cvt_mode_n, | |
15607 | neon_cvt_mode_p, | |
15608 | neon_cvt_mode_m, | |
15609 | neon_cvt_mode_z, | |
30bdf752 MGD |
15610 | neon_cvt_mode_x, |
15611 | neon_cvt_mode_r | |
7e8e6784 MGD |
15612 | }; |
15613 | ||
037e8744 JB |
15614 | /* Neon-syntax VFP conversions. */ |
15615 | ||
5287ad62 | 15616 | static void |
6b9a8b67 | 15617 | do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour) |
5287ad62 | 15618 | { |
037e8744 | 15619 | const char *opname = 0; |
5f4273c7 | 15620 | |
d54af2d0 RL |
15621 | if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI |
15622 | || rs == NS_FHI || rs == NS_HFI) | |
5287ad62 | 15623 | { |
037e8744 JB |
15624 | /* Conversions with immediate bitshift. */ |
15625 | const char *enc[] = | |
477330fc | 15626 | { |
6b9a8b67 MGD |
15627 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN, |
15628 | CVT_FLAVOUR_VAR | |
15629 | NULL | |
15630 | #undef CVT_VAR | |
477330fc | 15631 | }; |
037e8744 | 15632 | |
6b9a8b67 | 15633 | if (flavour < (int) ARRAY_SIZE (enc)) |
477330fc RM |
15634 | { |
15635 | opname = enc[flavour]; | |
15636 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
15637 | _("operands 0 and 1 must be the same register")); | |
15638 | inst.operands[1] = inst.operands[2]; | |
15639 | memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); | |
15640 | } | |
5287ad62 JB |
15641 | } |
15642 | else | |
15643 | { | |
037e8744 JB |
15644 | /* Conversions without bitshift. */ |
15645 | const char *enc[] = | |
477330fc | 15646 | { |
6b9a8b67 MGD |
15647 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN, |
15648 | CVT_FLAVOUR_VAR | |
15649 | NULL | |
15650 | #undef CVT_VAR | |
477330fc | 15651 | }; |
037e8744 | 15652 | |
6b9a8b67 | 15653 | if (flavour < (int) ARRAY_SIZE (enc)) |
477330fc | 15654 | opname = enc[flavour]; |
037e8744 JB |
15655 | } |
15656 | ||
15657 | if (opname) | |
15658 | do_vfp_nsyn_opcode (opname); | |
9db2f6b4 RL |
15659 | |
15660 | /* ARMv8.2 fp16 VCVT instruction. */ | |
15661 | if (flavour == neon_cvt_flavour_s32_f16 | |
15662 | || flavour == neon_cvt_flavour_u32_f16 | |
15663 | || flavour == neon_cvt_flavour_f16_u32 | |
15664 | || flavour == neon_cvt_flavour_f16_s32) | |
15665 | do_scalar_fp16_v82_encode (); | |
037e8744 JB |
15666 | } |
15667 | ||
15668 | static void | |
15669 | do_vfp_nsyn_cvtz (void) | |
15670 | { | |
d54af2d0 | 15671 | enum neon_shape rs = neon_select_shape (NS_FH, NS_FF, NS_FD, NS_NULL); |
6b9a8b67 | 15672 | enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs); |
037e8744 JB |
15673 | const char *enc[] = |
15674 | { | |
6b9a8b67 MGD |
15675 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN, |
15676 | CVT_FLAVOUR_VAR | |
15677 | NULL | |
15678 | #undef CVT_VAR | |
037e8744 JB |
15679 | }; |
15680 | ||
6b9a8b67 | 15681 | if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) |
037e8744 JB |
15682 | do_vfp_nsyn_opcode (enc[flavour]); |
15683 | } | |
f31fef98 | 15684 | |
037e8744 | 15685 | static void |
bacebabc | 15686 | do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour, |
7e8e6784 MGD |
15687 | enum neon_cvt_mode mode) |
15688 | { | |
15689 | int sz, op; | |
15690 | int rm; | |
15691 | ||
a715796b TG |
15692 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
15693 | D register operands. */ | |
15694 | if (flavour == neon_cvt_flavour_s32_f64 | |
15695 | || flavour == neon_cvt_flavour_u32_f64) | |
15696 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
15697 | _(BAD_FPU)); | |
15698 | ||
9db2f6b4 RL |
15699 | if (flavour == neon_cvt_flavour_s32_f16 |
15700 | || flavour == neon_cvt_flavour_u32_f16) | |
15701 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16), | |
15702 | _(BAD_FP16)); | |
15703 | ||
7e8e6784 MGD |
15704 | set_it_insn_type (OUTSIDE_IT_INSN); |
15705 | ||
15706 | switch (flavour) | |
15707 | { | |
15708 | case neon_cvt_flavour_s32_f64: | |
15709 | sz = 1; | |
827f64ff | 15710 | op = 1; |
7e8e6784 MGD |
15711 | break; |
15712 | case neon_cvt_flavour_s32_f32: | |
15713 | sz = 0; | |
15714 | op = 1; | |
15715 | break; | |
9db2f6b4 RL |
15716 | case neon_cvt_flavour_s32_f16: |
15717 | sz = 0; | |
15718 | op = 1; | |
15719 | break; | |
7e8e6784 MGD |
15720 | case neon_cvt_flavour_u32_f64: |
15721 | sz = 1; | |
15722 | op = 0; | |
15723 | break; | |
15724 | case neon_cvt_flavour_u32_f32: | |
15725 | sz = 0; | |
15726 | op = 0; | |
15727 | break; | |
9db2f6b4 RL |
15728 | case neon_cvt_flavour_u32_f16: |
15729 | sz = 0; | |
15730 | op = 0; | |
15731 | break; | |
7e8e6784 MGD |
15732 | default: |
15733 | first_error (_("invalid instruction shape")); | |
15734 | return; | |
15735 | } | |
15736 | ||
15737 | switch (mode) | |
15738 | { | |
15739 | case neon_cvt_mode_a: rm = 0; break; | |
15740 | case neon_cvt_mode_n: rm = 1; break; | |
15741 | case neon_cvt_mode_p: rm = 2; break; | |
15742 | case neon_cvt_mode_m: rm = 3; break; | |
15743 | default: first_error (_("invalid rounding mode")); return; | |
15744 | } | |
15745 | ||
15746 | NEON_ENCODE (FPV8, inst); | |
15747 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
15748 | encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm); | |
15749 | inst.instruction |= sz << 8; | |
9db2f6b4 RL |
15750 | |
15751 | /* ARMv8.2 fp16 VCVT instruction. */ | |
15752 | if (flavour == neon_cvt_flavour_s32_f16 | |
15753 | ||flavour == neon_cvt_flavour_u32_f16) | |
15754 | do_scalar_fp16_v82_encode (); | |
7e8e6784 MGD |
15755 | inst.instruction |= op << 7; |
15756 | inst.instruction |= rm << 16; | |
15757 | inst.instruction |= 0xf0000000; | |
15758 | inst.is_neon = TRUE; | |
15759 | } | |
15760 | ||
15761 | static void | |
15762 | do_neon_cvt_1 (enum neon_cvt_mode mode) | |
037e8744 JB |
15763 | { |
15764 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, | |
d54af2d0 RL |
15765 | NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, |
15766 | NS_FH, NS_HF, NS_FHI, NS_HFI, | |
15767 | NS_NULL); | |
6b9a8b67 | 15768 | enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs); |
037e8744 | 15769 | |
cc933301 JW |
15770 | if (flavour == neon_cvt_flavour_invalid) |
15771 | return; | |
15772 | ||
e3e535bc | 15773 | /* PR11109: Handle round-to-zero for VCVT conversions. */ |
7e8e6784 | 15774 | if (mode == neon_cvt_mode_z |
e3e535bc | 15775 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2) |
cc933301 JW |
15776 | && (flavour == neon_cvt_flavour_s16_f16 |
15777 | || flavour == neon_cvt_flavour_u16_f16 | |
15778 | || flavour == neon_cvt_flavour_s32_f32 | |
bacebabc RM |
15779 | || flavour == neon_cvt_flavour_u32_f32 |
15780 | || flavour == neon_cvt_flavour_s32_f64 | |
6b9a8b67 | 15781 | || flavour == neon_cvt_flavour_u32_f64) |
e3e535bc NC |
15782 | && (rs == NS_FD || rs == NS_FF)) |
15783 | { | |
15784 | do_vfp_nsyn_cvtz (); | |
15785 | return; | |
15786 | } | |
15787 | ||
9db2f6b4 RL |
15788 | /* ARMv8.2 fp16 VCVT conversions. */ |
15789 | if (mode == neon_cvt_mode_z | |
15790 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16) | |
15791 | && (flavour == neon_cvt_flavour_s32_f16 | |
15792 | || flavour == neon_cvt_flavour_u32_f16) | |
15793 | && (rs == NS_FH)) | |
15794 | { | |
15795 | do_vfp_nsyn_cvtz (); | |
15796 | do_scalar_fp16_v82_encode (); | |
15797 | return; | |
15798 | } | |
15799 | ||
037e8744 | 15800 | /* VFP rather than Neon conversions. */ |
6b9a8b67 | 15801 | if (flavour >= neon_cvt_flavour_first_fp) |
037e8744 | 15802 | { |
7e8e6784 MGD |
15803 | if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z) |
15804 | do_vfp_nsyn_cvt (rs, flavour); | |
15805 | else | |
15806 | do_vfp_nsyn_cvt_fpv8 (flavour, mode); | |
15807 | ||
037e8744 JB |
15808 | return; |
15809 | } | |
15810 | ||
15811 | switch (rs) | |
15812 | { | |
15813 | case NS_DDI: | |
15814 | case NS_QQI: | |
15815 | { | |
477330fc | 15816 | unsigned immbits; |
cc933301 JW |
15817 | unsigned enctab[] = {0x0000100, 0x1000100, 0x0, 0x1000000, |
15818 | 0x0000100, 0x1000100, 0x0, 0x1000000}; | |
35997600 | 15819 | |
477330fc RM |
15820 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
15821 | return; | |
037e8744 | 15822 | |
477330fc RM |
15823 | /* Fixed-point conversion with #0 immediate is encoded as an |
15824 | integer conversion. */ | |
15825 | if (inst.operands[2].present && inst.operands[2].imm == 0) | |
15826 | goto int_encode; | |
477330fc RM |
15827 | NEON_ENCODE (IMMED, inst); |
15828 | if (flavour != neon_cvt_flavour_invalid) | |
15829 | inst.instruction |= enctab[flavour]; | |
15830 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15831 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15832 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15833 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15834 | inst.instruction |= neon_quad (rs) << 6; | |
15835 | inst.instruction |= 1 << 21; | |
cc933301 JW |
15836 | if (flavour < neon_cvt_flavour_s16_f16) |
15837 | { | |
15838 | inst.instruction |= 1 << 21; | |
15839 | immbits = 32 - inst.operands[2].imm; | |
15840 | inst.instruction |= immbits << 16; | |
15841 | } | |
15842 | else | |
15843 | { | |
15844 | inst.instruction |= 3 << 20; | |
15845 | immbits = 16 - inst.operands[2].imm; | |
15846 | inst.instruction |= immbits << 16; | |
15847 | inst.instruction &= ~(1 << 9); | |
15848 | } | |
477330fc RM |
15849 | |
15850 | neon_dp_fixup (&inst); | |
037e8744 JB |
15851 | } |
15852 | break; | |
15853 | ||
15854 | case NS_DD: | |
15855 | case NS_QQ: | |
7e8e6784 MGD |
15856 | if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z) |
15857 | { | |
15858 | NEON_ENCODE (FLOAT, inst); | |
15859 | set_it_insn_type (OUTSIDE_IT_INSN); | |
15860 | ||
15861 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL) | |
15862 | return; | |
15863 | ||
15864 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15865 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15866 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15867 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15868 | inst.instruction |= neon_quad (rs) << 6; | |
cc933301 JW |
15869 | inst.instruction |= (flavour == neon_cvt_flavour_u16_f16 |
15870 | || flavour == neon_cvt_flavour_u32_f32) << 7; | |
7e8e6784 | 15871 | inst.instruction |= mode << 8; |
cc933301 JW |
15872 | if (flavour == neon_cvt_flavour_u16_f16 |
15873 | || flavour == neon_cvt_flavour_s16_f16) | |
15874 | /* Mask off the original size bits and reencode them. */ | |
15875 | inst.instruction = ((inst.instruction & 0xfff3ffff) | (1 << 18)); | |
15876 | ||
7e8e6784 MGD |
15877 | if (thumb_mode) |
15878 | inst.instruction |= 0xfc000000; | |
15879 | else | |
15880 | inst.instruction |= 0xf0000000; | |
15881 | } | |
15882 | else | |
15883 | { | |
037e8744 | 15884 | int_encode: |
7e8e6784 | 15885 | { |
cc933301 JW |
15886 | unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080, |
15887 | 0x100, 0x180, 0x0, 0x080}; | |
037e8744 | 15888 | |
7e8e6784 | 15889 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 15890 | |
7e8e6784 MGD |
15891 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
15892 | return; | |
037e8744 | 15893 | |
7e8e6784 MGD |
15894 | if (flavour != neon_cvt_flavour_invalid) |
15895 | inst.instruction |= enctab[flavour]; | |
037e8744 | 15896 | |
7e8e6784 MGD |
15897 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15898 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15899 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15900 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15901 | inst.instruction |= neon_quad (rs) << 6; | |
cc933301 JW |
15902 | if (flavour >= neon_cvt_flavour_s16_f16 |
15903 | && flavour <= neon_cvt_flavour_f16_u16) | |
15904 | /* Half precision. */ | |
15905 | inst.instruction |= 1 << 18; | |
15906 | else | |
15907 | inst.instruction |= 2 << 18; | |
037e8744 | 15908 | |
7e8e6784 MGD |
15909 | neon_dp_fixup (&inst); |
15910 | } | |
15911 | } | |
15912 | break; | |
037e8744 | 15913 | |
8e79c3df CM |
15914 | /* Half-precision conversions for Advanced SIMD -- neon. */ |
15915 | case NS_QD: | |
15916 | case NS_DQ: | |
bc52d49c MM |
15917 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
15918 | return; | |
8e79c3df CM |
15919 | |
15920 | if ((rs == NS_DQ) | |
15921 | && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) | |
15922 | { | |
15923 | as_bad (_("operand size must match register width")); | |
15924 | break; | |
15925 | } | |
15926 | ||
15927 | if ((rs == NS_QD) | |
15928 | && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) | |
15929 | { | |
15930 | as_bad (_("operand size must match register width")); | |
15931 | break; | |
15932 | } | |
15933 | ||
15934 | if (rs == NS_DQ) | |
477330fc | 15935 | inst.instruction = 0x3b60600; |
8e79c3df CM |
15936 | else |
15937 | inst.instruction = 0x3b60700; | |
15938 | ||
15939 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15940 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15941 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15942 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
88714cb8 | 15943 | neon_dp_fixup (&inst); |
8e79c3df CM |
15944 | break; |
15945 | ||
037e8744 JB |
15946 | default: |
15947 | /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ | |
7e8e6784 MGD |
15948 | if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z) |
15949 | do_vfp_nsyn_cvt (rs, flavour); | |
15950 | else | |
15951 | do_vfp_nsyn_cvt_fpv8 (flavour, mode); | |
5287ad62 | 15952 | } |
5287ad62 JB |
15953 | } |
15954 | ||
e3e535bc NC |
15955 | static void |
15956 | do_neon_cvtr (void) | |
15957 | { | |
7e8e6784 | 15958 | do_neon_cvt_1 (neon_cvt_mode_x); |
e3e535bc NC |
15959 | } |
15960 | ||
15961 | static void | |
15962 | do_neon_cvt (void) | |
15963 | { | |
7e8e6784 MGD |
15964 | do_neon_cvt_1 (neon_cvt_mode_z); |
15965 | } | |
15966 | ||
15967 | static void | |
15968 | do_neon_cvta (void) | |
15969 | { | |
15970 | do_neon_cvt_1 (neon_cvt_mode_a); | |
15971 | } | |
15972 | ||
15973 | static void | |
15974 | do_neon_cvtn (void) | |
15975 | { | |
15976 | do_neon_cvt_1 (neon_cvt_mode_n); | |
15977 | } | |
15978 | ||
15979 | static void | |
15980 | do_neon_cvtp (void) | |
15981 | { | |
15982 | do_neon_cvt_1 (neon_cvt_mode_p); | |
15983 | } | |
15984 | ||
15985 | static void | |
15986 | do_neon_cvtm (void) | |
15987 | { | |
15988 | do_neon_cvt_1 (neon_cvt_mode_m); | |
e3e535bc NC |
15989 | } |
15990 | ||
8e79c3df | 15991 | static void |
c70a8987 | 15992 | do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double) |
8e79c3df | 15993 | { |
c70a8987 MGD |
15994 | if (is_double) |
15995 | mark_feature_used (&fpu_vfp_ext_armv8); | |
8e79c3df | 15996 | |
c70a8987 MGD |
15997 | encode_arm_vfp_reg (inst.operands[0].reg, |
15998 | (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd); | |
15999 | encode_arm_vfp_reg (inst.operands[1].reg, | |
16000 | (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm); | |
16001 | inst.instruction |= to ? 0x10000 : 0; | |
16002 | inst.instruction |= t ? 0x80 : 0; | |
16003 | inst.instruction |= is_double ? 0x100 : 0; | |
16004 | do_vfp_cond_or_thumb (); | |
16005 | } | |
8e79c3df | 16006 | |
c70a8987 MGD |
16007 | static void |
16008 | do_neon_cvttb_1 (bfd_boolean t) | |
16009 | { | |
d54af2d0 RL |
16010 | enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD, |
16011 | NS_DF, NS_DH, NS_NULL); | |
8e79c3df | 16012 | |
c70a8987 MGD |
16013 | if (rs == NS_NULL) |
16014 | return; | |
16015 | else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype) | |
16016 | { | |
16017 | inst.error = NULL; | |
16018 | do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE); | |
16019 | } | |
16020 | else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype) | |
16021 | { | |
16022 | inst.error = NULL; | |
16023 | do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE); | |
16024 | } | |
16025 | else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype) | |
16026 | { | |
a715796b TG |
16027 | /* The VCVTB and VCVTT instructions with D-register operands |
16028 | don't work for SP only targets. */ | |
16029 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
16030 | _(BAD_FPU)); | |
16031 | ||
c70a8987 MGD |
16032 | inst.error = NULL; |
16033 | do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE); | |
16034 | } | |
16035 | else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype) | |
16036 | { | |
a715796b TG |
16037 | /* The VCVTB and VCVTT instructions with D-register operands |
16038 | don't work for SP only targets. */ | |
16039 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
16040 | _(BAD_FPU)); | |
16041 | ||
c70a8987 MGD |
16042 | inst.error = NULL; |
16043 | do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE); | |
16044 | } | |
16045 | else | |
16046 | return; | |
16047 | } | |
16048 | ||
16049 | static void | |
16050 | do_neon_cvtb (void) | |
16051 | { | |
16052 | do_neon_cvttb_1 (FALSE); | |
8e79c3df CM |
16053 | } |
16054 | ||
16055 | ||
16056 | static void | |
16057 | do_neon_cvtt (void) | |
16058 | { | |
c70a8987 | 16059 | do_neon_cvttb_1 (TRUE); |
8e79c3df CM |
16060 | } |
16061 | ||
5287ad62 JB |
16062 | static void |
16063 | neon_move_immediate (void) | |
16064 | { | |
037e8744 JB |
16065 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
16066 | struct neon_type_el et = neon_check_type (2, rs, | |
16067 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
5287ad62 | 16068 | unsigned immlo, immhi = 0, immbits; |
c96612cc | 16069 | int op, cmode, float_p; |
5287ad62 | 16070 | |
037e8744 | 16071 | constraint (et.type == NT_invtype, |
477330fc | 16072 | _("operand size must be specified for immediate VMOV")); |
037e8744 | 16073 | |
5287ad62 JB |
16074 | /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ |
16075 | op = (inst.instruction & (1 << 5)) != 0; | |
16076 | ||
16077 | immlo = inst.operands[1].imm; | |
16078 | if (inst.operands[1].regisimm) | |
16079 | immhi = inst.operands[1].reg; | |
16080 | ||
16081 | constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, | |
477330fc | 16082 | _("immediate has bits set outside the operand size")); |
5287ad62 | 16083 | |
c96612cc JB |
16084 | float_p = inst.operands[1].immisfloat; |
16085 | ||
16086 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, | |
477330fc | 16087 | et.size, et.type)) == FAIL) |
5287ad62 JB |
16088 | { |
16089 | /* Invert relevant bits only. */ | |
16090 | neon_invert_size (&immlo, &immhi, et.size); | |
16091 | /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable | |
477330fc RM |
16092 | with one or the other; those cases are caught by |
16093 | neon_cmode_for_move_imm. */ | |
5287ad62 | 16094 | op = !op; |
c96612cc JB |
16095 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, |
16096 | &op, et.size, et.type)) == FAIL) | |
477330fc RM |
16097 | { |
16098 | first_error (_("immediate out of range")); | |
16099 | return; | |
16100 | } | |
5287ad62 JB |
16101 | } |
16102 | ||
16103 | inst.instruction &= ~(1 << 5); | |
16104 | inst.instruction |= op << 5; | |
16105 | ||
16106 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16107 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
037e8744 | 16108 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
16109 | inst.instruction |= cmode << 8; |
16110 | ||
16111 | neon_write_immbits (immbits); | |
16112 | } | |
16113 | ||
16114 | static void | |
16115 | do_neon_mvn (void) | |
16116 | { | |
16117 | if (inst.operands[1].isreg) | |
16118 | { | |
037e8744 | 16119 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5f4273c7 | 16120 | |
88714cb8 | 16121 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
16122 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
16123 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16124 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16125 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 16126 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
16127 | } |
16128 | else | |
16129 | { | |
88714cb8 | 16130 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
16131 | neon_move_immediate (); |
16132 | } | |
16133 | ||
88714cb8 | 16134 | neon_dp_fixup (&inst); |
5287ad62 JB |
16135 | } |
16136 | ||
16137 | /* Encode instructions of form: | |
16138 | ||
16139 | |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
5f4273c7 | 16140 | | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */ |
5287ad62 JB |
16141 | |
16142 | static void | |
16143 | neon_mixed_length (struct neon_type_el et, unsigned size) | |
16144 | { | |
16145 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16146 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16147 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16148 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16149 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16150 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
16151 | inst.instruction |= (et.type == NT_unsigned) << 24; | |
16152 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 16153 | |
88714cb8 | 16154 | neon_dp_fixup (&inst); |
5287ad62 JB |
16155 | } |
16156 | ||
16157 | static void | |
16158 | do_neon_dyadic_long (void) | |
16159 | { | |
16160 | /* FIXME: Type checking for lengthening op. */ | |
16161 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
16162 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
16163 | neon_mixed_length (et, et.size); | |
16164 | } | |
16165 | ||
16166 | static void | |
16167 | do_neon_abal (void) | |
16168 | { | |
16169 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
16170 | N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
16171 | neon_mixed_length (et, et.size); | |
16172 | } | |
16173 | ||
16174 | static void | |
16175 | neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) | |
16176 | { | |
16177 | if (inst.operands[2].isscalar) | |
16178 | { | |
dcbf9037 | 16179 | struct neon_type_el et = neon_check_type (3, NS_QDS, |
477330fc | 16180 | N_EQK | N_DBL, N_EQK, regtypes | N_KEY); |
88714cb8 | 16181 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
16182 | neon_mul_mac (et, et.type == NT_unsigned); |
16183 | } | |
16184 | else | |
16185 | { | |
16186 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
477330fc | 16187 | N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); |
88714cb8 | 16188 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
16189 | neon_mixed_length (et, et.size); |
16190 | } | |
16191 | } | |
16192 | ||
16193 | static void | |
16194 | do_neon_mac_maybe_scalar_long (void) | |
16195 | { | |
16196 | neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); | |
16197 | } | |
16198 | ||
dec41383 JW |
16199 | /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's |
16200 | internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */ | |
16201 | ||
16202 | static unsigned | |
16203 | neon_scalar_for_fmac_fp16_long (unsigned scalar, unsigned quad_p) | |
16204 | { | |
16205 | unsigned regno = NEON_SCALAR_REG (scalar); | |
16206 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
16207 | ||
16208 | if (quad_p) | |
16209 | { | |
16210 | if (regno > 7 || elno > 3) | |
16211 | goto bad_scalar; | |
16212 | ||
16213 | return ((regno & 0x7) | |
16214 | | ((elno & 0x1) << 3) | |
16215 | | (((elno >> 1) & 0x1) << 5)); | |
16216 | } | |
16217 | else | |
16218 | { | |
16219 | if (regno > 15 || elno > 1) | |
16220 | goto bad_scalar; | |
16221 | ||
16222 | return (((regno & 0x1) << 5) | |
16223 | | ((regno >> 1) & 0x7) | |
16224 | | ((elno & 0x1) << 3)); | |
16225 | } | |
16226 | ||
16227 | bad_scalar: | |
16228 | first_error (_("scalar out of range for multiply instruction")); | |
16229 | return 0; | |
16230 | } | |
16231 | ||
16232 | static void | |
16233 | do_neon_fmac_maybe_scalar_long (int subtype) | |
16234 | { | |
16235 | enum neon_shape rs; | |
16236 | int high8; | |
16237 | /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size" | |
16238 | field (bits[21:20]) has different meaning. For scalar index variant, it's | |
16239 | used to differentiate add and subtract, otherwise it's with fixed value | |
16240 | 0x2. */ | |
16241 | int size = -1; | |
16242 | ||
16243 | if (inst.cond != COND_ALWAYS) | |
16244 | as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the " | |
16245 | "behaviour is UNPREDICTABLE")); | |
16246 | ||
01f48020 | 16247 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16_fml), |
dec41383 JW |
16248 | _(BAD_FP16)); |
16249 | ||
16250 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8), | |
16251 | _(BAD_FPU)); | |
16252 | ||
16253 | /* vfmal/vfmsl are in three-same D/Q register format or the third operand can | |
16254 | be a scalar index register. */ | |
16255 | if (inst.operands[2].isscalar) | |
16256 | { | |
16257 | high8 = 0xfe000000; | |
16258 | if (subtype) | |
16259 | size = 16; | |
16260 | rs = neon_select_shape (NS_DHS, NS_QDS, NS_NULL); | |
16261 | } | |
16262 | else | |
16263 | { | |
16264 | high8 = 0xfc000000; | |
16265 | size = 32; | |
16266 | if (subtype) | |
16267 | inst.instruction |= (0x1 << 23); | |
16268 | rs = neon_select_shape (NS_DHH, NS_QDD, NS_NULL); | |
16269 | } | |
16270 | ||
16271 | neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16); | |
16272 | ||
16273 | /* "opcode" from template has included "ubit", so simply pass 0 here. Also, | |
16274 | the "S" bit in size field has been reused to differentiate vfmal and vfmsl, | |
16275 | so we simply pass -1 as size. */ | |
16276 | unsigned quad_p = (rs == NS_QDD || rs == NS_QDS); | |
16277 | neon_three_same (quad_p, 0, size); | |
16278 | ||
16279 | /* Undo neon_dp_fixup. Redo the high eight bits. */ | |
16280 | inst.instruction &= 0x00ffffff; | |
16281 | inst.instruction |= high8; | |
16282 | ||
16283 | #define LOW1(R) ((R) & 0x1) | |
16284 | #define HI4(R) (((R) >> 1) & 0xf) | |
16285 | /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on | |
16286 | whether the instruction is in Q form and whether Vm is a scalar indexed | |
16287 | operand. */ | |
16288 | if (inst.operands[2].isscalar) | |
16289 | { | |
16290 | unsigned rm | |
16291 | = neon_scalar_for_fmac_fp16_long (inst.operands[2].reg, quad_p); | |
16292 | inst.instruction &= 0xffffffd0; | |
16293 | inst.instruction |= rm; | |
16294 | ||
16295 | if (!quad_p) | |
16296 | { | |
16297 | /* Redo Rn as well. */ | |
16298 | inst.instruction &= 0xfff0ff7f; | |
16299 | inst.instruction |= HI4 (inst.operands[1].reg) << 16; | |
16300 | inst.instruction |= LOW1 (inst.operands[1].reg) << 7; | |
16301 | } | |
16302 | } | |
16303 | else if (!quad_p) | |
16304 | { | |
16305 | /* Redo Rn and Rm. */ | |
16306 | inst.instruction &= 0xfff0ff50; | |
16307 | inst.instruction |= HI4 (inst.operands[1].reg) << 16; | |
16308 | inst.instruction |= LOW1 (inst.operands[1].reg) << 7; | |
16309 | inst.instruction |= HI4 (inst.operands[2].reg); | |
16310 | inst.instruction |= LOW1 (inst.operands[2].reg) << 5; | |
16311 | } | |
16312 | } | |
16313 | ||
16314 | static void | |
16315 | do_neon_vfmal (void) | |
16316 | { | |
16317 | return do_neon_fmac_maybe_scalar_long (0); | |
16318 | } | |
16319 | ||
16320 | static void | |
16321 | do_neon_vfmsl (void) | |
16322 | { | |
16323 | return do_neon_fmac_maybe_scalar_long (1); | |
16324 | } | |
16325 | ||
5287ad62 JB |
16326 | static void |
16327 | do_neon_dyadic_wide (void) | |
16328 | { | |
16329 | struct neon_type_el et = neon_check_type (3, NS_QQD, | |
16330 | N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); | |
16331 | neon_mixed_length (et, et.size); | |
16332 | } | |
16333 | ||
16334 | static void | |
16335 | do_neon_dyadic_narrow (void) | |
16336 | { | |
16337 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
16338 | N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); | |
428e3f1f PB |
16339 | /* Operand sign is unimportant, and the U bit is part of the opcode, |
16340 | so force the operand type to integer. */ | |
16341 | et.type = NT_integer; | |
5287ad62 JB |
16342 | neon_mixed_length (et, et.size / 2); |
16343 | } | |
16344 | ||
16345 | static void | |
16346 | do_neon_mul_sat_scalar_long (void) | |
16347 | { | |
16348 | neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); | |
16349 | } | |
16350 | ||
16351 | static void | |
16352 | do_neon_vmull (void) | |
16353 | { | |
16354 | if (inst.operands[2].isscalar) | |
16355 | do_neon_mac_maybe_scalar_long (); | |
16356 | else | |
16357 | { | |
16358 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
477330fc | 16359 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY); |
4f51b4bd | 16360 | |
5287ad62 | 16361 | if (et.type == NT_poly) |
477330fc | 16362 | NEON_ENCODE (POLY, inst); |
5287ad62 | 16363 | else |
477330fc | 16364 | NEON_ENCODE (INTEGER, inst); |
4f51b4bd MGD |
16365 | |
16366 | /* For polynomial encoding the U bit must be zero, and the size must | |
16367 | be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non | |
16368 | obviously, as 0b10). */ | |
16369 | if (et.size == 64) | |
16370 | { | |
16371 | /* Check we're on the correct architecture. */ | |
16372 | if (!mark_feature_used (&fpu_crypto_ext_armv8)) | |
16373 | inst.error = | |
16374 | _("Instruction form not available on this architecture."); | |
16375 | ||
16376 | et.size = 32; | |
16377 | } | |
16378 | ||
5287ad62 JB |
16379 | neon_mixed_length (et, et.size); |
16380 | } | |
16381 | } | |
16382 | ||
16383 | static void | |
16384 | do_neon_ext (void) | |
16385 | { | |
037e8744 | 16386 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
5287ad62 JB |
16387 | struct neon_type_el et = neon_check_type (3, rs, |
16388 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
16389 | unsigned imm = (inst.operands[3].imm * et.size) / 8; | |
35997600 NC |
16390 | |
16391 | constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), | |
16392 | _("shift out of range")); | |
5287ad62 JB |
16393 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
16394 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16395 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16396 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16397 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16398 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
037e8744 | 16399 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 | 16400 | inst.instruction |= imm << 8; |
5f4273c7 | 16401 | |
88714cb8 | 16402 | neon_dp_fixup (&inst); |
5287ad62 JB |
16403 | } |
16404 | ||
16405 | static void | |
16406 | do_neon_rev (void) | |
16407 | { | |
037e8744 | 16408 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16409 | struct neon_type_el et = neon_check_type (2, rs, |
16410 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
16411 | unsigned op = (inst.instruction >> 7) & 3; | |
16412 | /* N (width of reversed regions) is encoded as part of the bitmask. We | |
16413 | extract it here to check the elements to be reversed are smaller. | |
16414 | Otherwise we'd get a reserved instruction. */ | |
16415 | unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; | |
9c2799c2 | 16416 | gas_assert (elsize != 0); |
5287ad62 | 16417 | constraint (et.size >= elsize, |
477330fc | 16418 | _("elements must be smaller than reversal region")); |
037e8744 | 16419 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16420 | } |
16421 | ||
16422 | static void | |
16423 | do_neon_dup (void) | |
16424 | { | |
16425 | if (inst.operands[1].isscalar) | |
16426 | { | |
037e8744 | 16427 | enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); |
dcbf9037 | 16428 | struct neon_type_el et = neon_check_type (2, rs, |
477330fc | 16429 | N_EQK, N_8 | N_16 | N_32 | N_KEY); |
5287ad62 | 16430 | unsigned sizebits = et.size >> 3; |
dcbf9037 | 16431 | unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); |
5287ad62 | 16432 | int logsize = neon_logbits (et.size); |
dcbf9037 | 16433 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; |
037e8744 JB |
16434 | |
16435 | if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) | |
477330fc | 16436 | return; |
037e8744 | 16437 | |
88714cb8 | 16438 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
16439 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
16440 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16441 | inst.instruction |= LOW4 (dm); | |
16442 | inst.instruction |= HI1 (dm) << 5; | |
037e8744 | 16443 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
16444 | inst.instruction |= x << 17; |
16445 | inst.instruction |= sizebits << 16; | |
5f4273c7 | 16446 | |
88714cb8 | 16447 | neon_dp_fixup (&inst); |
5287ad62 JB |
16448 | } |
16449 | else | |
16450 | { | |
037e8744 JB |
16451 | enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); |
16452 | struct neon_type_el et = neon_check_type (2, rs, | |
477330fc | 16453 | N_8 | N_16 | N_32 | N_KEY, N_EQK); |
5287ad62 | 16454 | /* Duplicate ARM register to lanes of vector. */ |
88714cb8 | 16455 | NEON_ENCODE (ARMREG, inst); |
5287ad62 | 16456 | switch (et.size) |
477330fc RM |
16457 | { |
16458 | case 8: inst.instruction |= 0x400000; break; | |
16459 | case 16: inst.instruction |= 0x000020; break; | |
16460 | case 32: inst.instruction |= 0x000000; break; | |
16461 | default: break; | |
16462 | } | |
5287ad62 JB |
16463 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; |
16464 | inst.instruction |= LOW4 (inst.operands[0].reg) << 16; | |
16465 | inst.instruction |= HI1 (inst.operands[0].reg) << 7; | |
037e8744 | 16466 | inst.instruction |= neon_quad (rs) << 21; |
5287ad62 | 16467 | /* The encoding for this instruction is identical for the ARM and Thumb |
477330fc | 16468 | variants, except for the condition field. */ |
037e8744 | 16469 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
16470 | } |
16471 | } | |
16472 | ||
16473 | /* VMOV has particularly many variations. It can be one of: | |
16474 | 0. VMOV<c><q> <Qd>, <Qm> | |
16475 | 1. VMOV<c><q> <Dd>, <Dm> | |
16476 | (Register operations, which are VORR with Rm = Rn.) | |
16477 | 2. VMOV<c><q>.<dt> <Qd>, #<imm> | |
16478 | 3. VMOV<c><q>.<dt> <Dd>, #<imm> | |
16479 | (Immediate loads.) | |
16480 | 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> | |
16481 | (ARM register to scalar.) | |
16482 | 5. VMOV<c><q> <Dm>, <Rd>, <Rn> | |
16483 | (Two ARM registers to vector.) | |
16484 | 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> | |
16485 | (Scalar to ARM register.) | |
16486 | 7. VMOV<c><q> <Rd>, <Rn>, <Dm> | |
16487 | (Vector to two ARM registers.) | |
037e8744 JB |
16488 | 8. VMOV.F32 <Sd>, <Sm> |
16489 | 9. VMOV.F64 <Dd>, <Dm> | |
16490 | (VFP register moves.) | |
16491 | 10. VMOV.F32 <Sd>, #imm | |
16492 | 11. VMOV.F64 <Dd>, #imm | |
16493 | (VFP float immediate load.) | |
16494 | 12. VMOV <Rd>, <Sm> | |
16495 | (VFP single to ARM reg.) | |
16496 | 13. VMOV <Sd>, <Rm> | |
16497 | (ARM reg to VFP single.) | |
16498 | 14. VMOV <Rd>, <Re>, <Sn>, <Sm> | |
16499 | (Two ARM regs to two VFP singles.) | |
16500 | 15. VMOV <Sd>, <Se>, <Rn>, <Rm> | |
16501 | (Two VFP singles to two ARM regs.) | |
5f4273c7 | 16502 | |
037e8744 JB |
16503 | These cases can be disambiguated using neon_select_shape, except cases 1/9 |
16504 | and 3/11 which depend on the operand type too. | |
5f4273c7 | 16505 | |
5287ad62 | 16506 | All the encoded bits are hardcoded by this function. |
5f4273c7 | 16507 | |
b7fc2769 JB |
16508 | Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). |
16509 | Cases 5, 7 may be used with VFPv2 and above. | |
5f4273c7 | 16510 | |
5287ad62 | 16511 | FIXME: Some of the checking may be a bit sloppy (in a couple of cases you |
5f4273c7 | 16512 | can specify a type where it doesn't make sense to, and is ignored). */ |
5287ad62 JB |
16513 | |
16514 | static void | |
16515 | do_neon_mov (void) | |
16516 | { | |
037e8744 | 16517 | enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, |
9db2f6b4 RL |
16518 | NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, |
16519 | NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, | |
16520 | NS_HR, NS_RH, NS_HI, NS_NULL); | |
037e8744 JB |
16521 | struct neon_type_el et; |
16522 | const char *ldconst = 0; | |
5287ad62 | 16523 | |
037e8744 | 16524 | switch (rs) |
5287ad62 | 16525 | { |
037e8744 JB |
16526 | case NS_DD: /* case 1/9. */ |
16527 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
16528 | /* It is not an error here if no type is given. */ | |
16529 | inst.error = NULL; | |
16530 | if (et.type == NT_float && et.size == 64) | |
477330fc RM |
16531 | { |
16532 | do_vfp_nsyn_opcode ("fcpyd"); | |
16533 | break; | |
16534 | } | |
037e8744 | 16535 | /* fall through. */ |
5287ad62 | 16536 | |
037e8744 JB |
16537 | case NS_QQ: /* case 0/1. */ |
16538 | { | |
477330fc RM |
16539 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
16540 | return; | |
16541 | /* The architecture manual I have doesn't explicitly state which | |
16542 | value the U bit should have for register->register moves, but | |
16543 | the equivalent VORR instruction has U = 0, so do that. */ | |
16544 | inst.instruction = 0x0200110; | |
16545 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16546 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16547 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16548 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
16549 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16550 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16551 | inst.instruction |= neon_quad (rs) << 6; | |
16552 | ||
16553 | neon_dp_fixup (&inst); | |
037e8744 JB |
16554 | } |
16555 | break; | |
5f4273c7 | 16556 | |
037e8744 JB |
16557 | case NS_DI: /* case 3/11. */ |
16558 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
16559 | inst.error = NULL; | |
16560 | if (et.type == NT_float && et.size == 64) | |
477330fc RM |
16561 | { |
16562 | /* case 11 (fconstd). */ | |
16563 | ldconst = "fconstd"; | |
16564 | goto encode_fconstd; | |
16565 | } | |
037e8744 JB |
16566 | /* fall through. */ |
16567 | ||
16568 | case NS_QI: /* case 2/3. */ | |
16569 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
477330fc | 16570 | return; |
037e8744 JB |
16571 | inst.instruction = 0x0800010; |
16572 | neon_move_immediate (); | |
88714cb8 | 16573 | neon_dp_fixup (&inst); |
5287ad62 | 16574 | break; |
5f4273c7 | 16575 | |
037e8744 JB |
16576 | case NS_SR: /* case 4. */ |
16577 | { | |
477330fc RM |
16578 | unsigned bcdebits = 0; |
16579 | int logsize; | |
16580 | unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); | |
16581 | unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); | |
037e8744 | 16582 | |
05ac0ffb JB |
16583 | /* .<size> is optional here, defaulting to .32. */ |
16584 | if (inst.vectype.elems == 0 | |
16585 | && inst.operands[0].vectype.type == NT_invtype | |
16586 | && inst.operands[1].vectype.type == NT_invtype) | |
16587 | { | |
16588 | inst.vectype.el[0].type = NT_untyped; | |
16589 | inst.vectype.el[0].size = 32; | |
16590 | inst.vectype.elems = 1; | |
16591 | } | |
16592 | ||
477330fc RM |
16593 | et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK); |
16594 | logsize = neon_logbits (et.size); | |
16595 | ||
16596 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), | |
16597 | _(BAD_FPU)); | |
16598 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
16599 | && et.size != 32, _(BAD_FPU)); | |
16600 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
16601 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
16602 | ||
16603 | switch (et.size) | |
16604 | { | |
16605 | case 8: bcdebits = 0x8; break; | |
16606 | case 16: bcdebits = 0x1; break; | |
16607 | case 32: bcdebits = 0x0; break; | |
16608 | default: ; | |
16609 | } | |
16610 | ||
16611 | bcdebits |= x << logsize; | |
16612 | ||
16613 | inst.instruction = 0xe000b10; | |
16614 | do_vfp_cond_or_thumb (); | |
16615 | inst.instruction |= LOW4 (dn) << 16; | |
16616 | inst.instruction |= HI1 (dn) << 7; | |
16617 | inst.instruction |= inst.operands[1].reg << 12; | |
16618 | inst.instruction |= (bcdebits & 3) << 5; | |
16619 | inst.instruction |= (bcdebits >> 2) << 21; | |
037e8744 JB |
16620 | } |
16621 | break; | |
5f4273c7 | 16622 | |
037e8744 | 16623 | case NS_DRR: /* case 5 (fmdrr). */ |
b7fc2769 | 16624 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), |
477330fc | 16625 | _(BAD_FPU)); |
b7fc2769 | 16626 | |
037e8744 JB |
16627 | inst.instruction = 0xc400b10; |
16628 | do_vfp_cond_or_thumb (); | |
16629 | inst.instruction |= LOW4 (inst.operands[0].reg); | |
16630 | inst.instruction |= HI1 (inst.operands[0].reg) << 5; | |
16631 | inst.instruction |= inst.operands[1].reg << 12; | |
16632 | inst.instruction |= inst.operands[2].reg << 16; | |
16633 | break; | |
5f4273c7 | 16634 | |
037e8744 JB |
16635 | case NS_RS: /* case 6. */ |
16636 | { | |
477330fc RM |
16637 | unsigned logsize; |
16638 | unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); | |
16639 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); | |
16640 | unsigned abcdebits = 0; | |
037e8744 | 16641 | |
05ac0ffb JB |
16642 | /* .<dt> is optional here, defaulting to .32. */ |
16643 | if (inst.vectype.elems == 0 | |
16644 | && inst.operands[0].vectype.type == NT_invtype | |
16645 | && inst.operands[1].vectype.type == NT_invtype) | |
16646 | { | |
16647 | inst.vectype.el[0].type = NT_untyped; | |
16648 | inst.vectype.el[0].size = 32; | |
16649 | inst.vectype.elems = 1; | |
16650 | } | |
16651 | ||
91d6fa6a NC |
16652 | et = neon_check_type (2, NS_NULL, |
16653 | N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); | |
477330fc RM |
16654 | logsize = neon_logbits (et.size); |
16655 | ||
16656 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), | |
16657 | _(BAD_FPU)); | |
16658 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
16659 | && et.size != 32, _(BAD_FPU)); | |
16660 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
16661 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
16662 | ||
16663 | switch (et.size) | |
16664 | { | |
16665 | case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; | |
16666 | case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; | |
16667 | case 32: abcdebits = 0x00; break; | |
16668 | default: ; | |
16669 | } | |
16670 | ||
16671 | abcdebits |= x << logsize; | |
16672 | inst.instruction = 0xe100b10; | |
16673 | do_vfp_cond_or_thumb (); | |
16674 | inst.instruction |= LOW4 (dn) << 16; | |
16675 | inst.instruction |= HI1 (dn) << 7; | |
16676 | inst.instruction |= inst.operands[0].reg << 12; | |
16677 | inst.instruction |= (abcdebits & 3) << 5; | |
16678 | inst.instruction |= (abcdebits >> 2) << 21; | |
037e8744 JB |
16679 | } |
16680 | break; | |
5f4273c7 | 16681 | |
037e8744 JB |
16682 | case NS_RRD: /* case 7 (fmrrd). */ |
16683 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), | |
477330fc | 16684 | _(BAD_FPU)); |
037e8744 JB |
16685 | |
16686 | inst.instruction = 0xc500b10; | |
16687 | do_vfp_cond_or_thumb (); | |
16688 | inst.instruction |= inst.operands[0].reg << 12; | |
16689 | inst.instruction |= inst.operands[1].reg << 16; | |
16690 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16691 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
16692 | break; | |
5f4273c7 | 16693 | |
037e8744 JB |
16694 | case NS_FF: /* case 8 (fcpys). */ |
16695 | do_vfp_nsyn_opcode ("fcpys"); | |
16696 | break; | |
5f4273c7 | 16697 | |
9db2f6b4 | 16698 | case NS_HI: |
037e8744 JB |
16699 | case NS_FI: /* case 10 (fconsts). */ |
16700 | ldconst = "fconsts"; | |
4ef4710f | 16701 | encode_fconstd: |
58ed5c38 TC |
16702 | if (!inst.operands[1].immisfloat) |
16703 | { | |
4ef4710f | 16704 | unsigned new_imm; |
58ed5c38 | 16705 | /* Immediate has to fit in 8 bits so float is enough. */ |
4ef4710f NC |
16706 | float imm = (float) inst.operands[1].imm; |
16707 | memcpy (&new_imm, &imm, sizeof (float)); | |
16708 | /* But the assembly may have been written to provide an integer | |
16709 | bit pattern that equates to a float, so check that the | |
16710 | conversion has worked. */ | |
16711 | if (is_quarter_float (new_imm)) | |
16712 | { | |
16713 | if (is_quarter_float (inst.operands[1].imm)) | |
16714 | as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)")); | |
16715 | ||
16716 | inst.operands[1].imm = new_imm; | |
16717 | inst.operands[1].immisfloat = 1; | |
16718 | } | |
58ed5c38 TC |
16719 | } |
16720 | ||
037e8744 | 16721 | if (is_quarter_float (inst.operands[1].imm)) |
477330fc RM |
16722 | { |
16723 | inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); | |
16724 | do_vfp_nsyn_opcode (ldconst); | |
9db2f6b4 RL |
16725 | |
16726 | /* ARMv8.2 fp16 vmov.f16 instruction. */ | |
16727 | if (rs == NS_HI) | |
16728 | do_scalar_fp16_v82_encode (); | |
477330fc | 16729 | } |
5287ad62 | 16730 | else |
477330fc | 16731 | first_error (_("immediate out of range")); |
037e8744 | 16732 | break; |
5f4273c7 | 16733 | |
9db2f6b4 | 16734 | case NS_RH: |
037e8744 JB |
16735 | case NS_RF: /* case 12 (fmrs). */ |
16736 | do_vfp_nsyn_opcode ("fmrs"); | |
9db2f6b4 RL |
16737 | /* ARMv8.2 fp16 vmov.f16 instruction. */ |
16738 | if (rs == NS_RH) | |
16739 | do_scalar_fp16_v82_encode (); | |
037e8744 | 16740 | break; |
5f4273c7 | 16741 | |
9db2f6b4 | 16742 | case NS_HR: |
037e8744 JB |
16743 | case NS_FR: /* case 13 (fmsr). */ |
16744 | do_vfp_nsyn_opcode ("fmsr"); | |
9db2f6b4 RL |
16745 | /* ARMv8.2 fp16 vmov.f16 instruction. */ |
16746 | if (rs == NS_HR) | |
16747 | do_scalar_fp16_v82_encode (); | |
037e8744 | 16748 | break; |
5f4273c7 | 16749 | |
037e8744 JB |
16750 | /* The encoders for the fmrrs and fmsrr instructions expect three operands |
16751 | (one of which is a list), but we have parsed four. Do some fiddling to | |
16752 | make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 | |
16753 | expect. */ | |
16754 | case NS_RRFF: /* case 14 (fmrrs). */ | |
16755 | constraint (inst.operands[3].reg != inst.operands[2].reg + 1, | |
477330fc | 16756 | _("VFP registers must be adjacent")); |
037e8744 JB |
16757 | inst.operands[2].imm = 2; |
16758 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
16759 | do_vfp_nsyn_opcode ("fmrrs"); | |
16760 | break; | |
5f4273c7 | 16761 | |
037e8744 JB |
16762 | case NS_FFRR: /* case 15 (fmsrr). */ |
16763 | constraint (inst.operands[1].reg != inst.operands[0].reg + 1, | |
477330fc | 16764 | _("VFP registers must be adjacent")); |
037e8744 JB |
16765 | inst.operands[1] = inst.operands[2]; |
16766 | inst.operands[2] = inst.operands[3]; | |
16767 | inst.operands[0].imm = 2; | |
16768 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
16769 | do_vfp_nsyn_opcode ("fmsrr"); | |
5287ad62 | 16770 | break; |
5f4273c7 | 16771 | |
4c261dff NC |
16772 | case NS_NULL: |
16773 | /* neon_select_shape has determined that the instruction | |
16774 | shape is wrong and has already set the error message. */ | |
16775 | break; | |
16776 | ||
5287ad62 JB |
16777 | default: |
16778 | abort (); | |
16779 | } | |
16780 | } | |
16781 | ||
16782 | static void | |
16783 | do_neon_rshift_round_imm (void) | |
16784 | { | |
037e8744 | 16785 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
16786 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
16787 | int imm = inst.operands[2].imm; | |
16788 | ||
16789 | /* imm == 0 case is encoded as VMOV for V{R}SHR. */ | |
16790 | if (imm == 0) | |
16791 | { | |
16792 | inst.operands[2].present = 0; | |
16793 | do_neon_mov (); | |
16794 | return; | |
16795 | } | |
16796 | ||
16797 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 16798 | _("immediate out of range for shift")); |
037e8744 | 16799 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
477330fc | 16800 | et.size - imm); |
5287ad62 JB |
16801 | } |
16802 | ||
9db2f6b4 RL |
16803 | static void |
16804 | do_neon_movhf (void) | |
16805 | { | |
16806 | enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL); | |
16807 | constraint (rs != NS_HH, _("invalid suffix")); | |
16808 | ||
16809 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
16810 | _(BAD_FPU)); | |
16811 | ||
7bdf778b ASDV |
16812 | if (inst.cond != COND_ALWAYS) |
16813 | { | |
16814 | if (thumb_mode) | |
16815 | { | |
16816 | as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional," | |
16817 | " the behaviour is UNPREDICTABLE")); | |
16818 | } | |
16819 | else | |
16820 | { | |
16821 | inst.error = BAD_COND; | |
16822 | return; | |
16823 | } | |
16824 | } | |
16825 | ||
9db2f6b4 RL |
16826 | do_vfp_sp_monadic (); |
16827 | ||
16828 | inst.is_neon = 1; | |
16829 | inst.instruction |= 0xf0000000; | |
16830 | } | |
16831 | ||
5287ad62 JB |
16832 | static void |
16833 | do_neon_movl (void) | |
16834 | { | |
16835 | struct neon_type_el et = neon_check_type (2, NS_QD, | |
16836 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
16837 | unsigned sizebits = et.size >> 3; | |
16838 | inst.instruction |= sizebits << 19; | |
16839 | neon_two_same (0, et.type == NT_unsigned, -1); | |
16840 | } | |
16841 | ||
16842 | static void | |
16843 | do_neon_trn (void) | |
16844 | { | |
037e8744 | 16845 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16846 | struct neon_type_el et = neon_check_type (2, rs, |
16847 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
88714cb8 | 16848 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 16849 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16850 | } |
16851 | ||
16852 | static void | |
16853 | do_neon_zip_uzp (void) | |
16854 | { | |
037e8744 | 16855 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16856 | struct neon_type_el et = neon_check_type (2, rs, |
16857 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
16858 | if (rs == NS_DD && et.size == 32) | |
16859 | { | |
16860 | /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ | |
16861 | inst.instruction = N_MNEM_vtrn; | |
16862 | do_neon_trn (); | |
16863 | return; | |
16864 | } | |
037e8744 | 16865 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16866 | } |
16867 | ||
16868 | static void | |
16869 | do_neon_sat_abs_neg (void) | |
16870 | { | |
037e8744 | 16871 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16872 | struct neon_type_el et = neon_check_type (2, rs, |
16873 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 16874 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16875 | } |
16876 | ||
16877 | static void | |
16878 | do_neon_pair_long (void) | |
16879 | { | |
037e8744 | 16880 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16881 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); |
16882 | /* Unsigned is encoded in OP field (bit 7) for these instruction. */ | |
16883 | inst.instruction |= (et.type == NT_unsigned) << 7; | |
037e8744 | 16884 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16885 | } |
16886 | ||
16887 | static void | |
16888 | do_neon_recip_est (void) | |
16889 | { | |
037e8744 | 16890 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 | 16891 | struct neon_type_el et = neon_check_type (2, rs, |
cc933301 | 16892 | N_EQK | N_FLT, N_F_16_32 | N_U32 | N_KEY); |
5287ad62 | 16893 | inst.instruction |= (et.type == NT_float) << 8; |
037e8744 | 16894 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16895 | } |
16896 | ||
16897 | static void | |
16898 | do_neon_cls (void) | |
16899 | { | |
037e8744 | 16900 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16901 | struct neon_type_el et = neon_check_type (2, rs, |
16902 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 16903 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16904 | } |
16905 | ||
16906 | static void | |
16907 | do_neon_clz (void) | |
16908 | { | |
037e8744 | 16909 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16910 | struct neon_type_el et = neon_check_type (2, rs, |
16911 | N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); | |
037e8744 | 16912 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16913 | } |
16914 | ||
16915 | static void | |
16916 | do_neon_cnt (void) | |
16917 | { | |
037e8744 | 16918 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16919 | struct neon_type_el et = neon_check_type (2, rs, |
16920 | N_EQK | N_INT, N_8 | N_KEY); | |
037e8744 | 16921 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16922 | } |
16923 | ||
16924 | static void | |
16925 | do_neon_swp (void) | |
16926 | { | |
037e8744 JB |
16927 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
16928 | neon_two_same (neon_quad (rs), 1, -1); | |
5287ad62 JB |
16929 | } |
16930 | ||
16931 | static void | |
16932 | do_neon_tbl_tbx (void) | |
16933 | { | |
16934 | unsigned listlenbits; | |
dcbf9037 | 16935 | neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); |
5f4273c7 | 16936 | |
5287ad62 JB |
16937 | if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) |
16938 | { | |
dcbf9037 | 16939 | first_error (_("bad list length for table lookup")); |
5287ad62 JB |
16940 | return; |
16941 | } | |
5f4273c7 | 16942 | |
5287ad62 JB |
16943 | listlenbits = inst.operands[1].imm - 1; |
16944 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16945 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16946 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16947 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16948 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16949 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
16950 | inst.instruction |= listlenbits << 8; | |
5f4273c7 | 16951 | |
88714cb8 | 16952 | neon_dp_fixup (&inst); |
5287ad62 JB |
16953 | } |
16954 | ||
16955 | static void | |
16956 | do_neon_ldm_stm (void) | |
16957 | { | |
16958 | /* P, U and L bits are part of bitmask. */ | |
16959 | int is_dbmode = (inst.instruction & (1 << 24)) != 0; | |
16960 | unsigned offsetbits = inst.operands[1].imm * 2; | |
16961 | ||
037e8744 JB |
16962 | if (inst.operands[1].issingle) |
16963 | { | |
16964 | do_vfp_nsyn_ldm_stm (is_dbmode); | |
16965 | return; | |
16966 | } | |
16967 | ||
5287ad62 | 16968 | constraint (is_dbmode && !inst.operands[0].writeback, |
477330fc | 16969 | _("writeback (!) must be used for VLDMDB and VSTMDB")); |
5287ad62 JB |
16970 | |
16971 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
477330fc RM |
16972 | _("register list must contain at least 1 and at most 16 " |
16973 | "registers")); | |
5287ad62 JB |
16974 | |
16975 | inst.instruction |= inst.operands[0].reg << 16; | |
16976 | inst.instruction |= inst.operands[0].writeback << 21; | |
16977 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
16978 | inst.instruction |= HI1 (inst.operands[1].reg) << 22; | |
16979 | ||
16980 | inst.instruction |= offsetbits; | |
5f4273c7 | 16981 | |
037e8744 | 16982 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
16983 | } |
16984 | ||
16985 | static void | |
16986 | do_neon_ldr_str (void) | |
16987 | { | |
5287ad62 | 16988 | int is_ldr = (inst.instruction & (1 << 20)) != 0; |
5f4273c7 | 16989 | |
6844b2c2 MGD |
16990 | /* Use of PC in vstr in ARM mode is deprecated in ARMv7. |
16991 | And is UNPREDICTABLE in thumb mode. */ | |
fa94de6b | 16992 | if (!is_ldr |
6844b2c2 | 16993 | && inst.operands[1].reg == REG_PC |
ba86b375 | 16994 | && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode)) |
6844b2c2 | 16995 | { |
94dcf8bf | 16996 | if (thumb_mode) |
6844b2c2 | 16997 | inst.error = _("Use of PC here is UNPREDICTABLE"); |
94dcf8bf | 16998 | else if (warn_on_deprecated) |
5c3696f8 | 16999 | as_tsktsk (_("Use of PC here is deprecated")); |
6844b2c2 MGD |
17000 | } |
17001 | ||
037e8744 JB |
17002 | if (inst.operands[0].issingle) |
17003 | { | |
cd2f129f | 17004 | if (is_ldr) |
477330fc | 17005 | do_vfp_nsyn_opcode ("flds"); |
cd2f129f | 17006 | else |
477330fc | 17007 | do_vfp_nsyn_opcode ("fsts"); |
9db2f6b4 RL |
17008 | |
17009 | /* ARMv8.2 vldr.16/vstr.16 instruction. */ | |
17010 | if (inst.vectype.el[0].size == 16) | |
17011 | do_scalar_fp16_v82_encode (); | |
5287ad62 JB |
17012 | } |
17013 | else | |
5287ad62 | 17014 | { |
cd2f129f | 17015 | if (is_ldr) |
477330fc | 17016 | do_vfp_nsyn_opcode ("fldd"); |
5287ad62 | 17017 | else |
477330fc | 17018 | do_vfp_nsyn_opcode ("fstd"); |
5287ad62 | 17019 | } |
5287ad62 JB |
17020 | } |
17021 | ||
17022 | /* "interleave" version also handles non-interleaving register VLD1/VST1 | |
17023 | instructions. */ | |
17024 | ||
17025 | static void | |
17026 | do_neon_ld_st_interleave (void) | |
17027 | { | |
037e8744 | 17028 | struct neon_type_el et = neon_check_type (1, NS_NULL, |
477330fc | 17029 | N_8 | N_16 | N_32 | N_64); |
5287ad62 JB |
17030 | unsigned alignbits = 0; |
17031 | unsigned idx; | |
17032 | /* The bits in this table go: | |
17033 | 0: register stride of one (0) or two (1) | |
17034 | 1,2: register list length, minus one (1, 2, 3, 4). | |
17035 | 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). | |
17036 | We use -1 for invalid entries. */ | |
17037 | const int typetable[] = | |
17038 | { | |
17039 | 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ | |
17040 | -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ | |
17041 | -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ | |
17042 | -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ | |
17043 | }; | |
17044 | int typebits; | |
17045 | ||
dcbf9037 JB |
17046 | if (et.type == NT_invtype) |
17047 | return; | |
17048 | ||
5287ad62 JB |
17049 | if (inst.operands[1].immisalign) |
17050 | switch (inst.operands[1].imm >> 8) | |
17051 | { | |
17052 | case 64: alignbits = 1; break; | |
17053 | case 128: | |
477330fc | 17054 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2 |
e23c0ad8 | 17055 | && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
477330fc RM |
17056 | goto bad_alignment; |
17057 | alignbits = 2; | |
17058 | break; | |
5287ad62 | 17059 | case 256: |
477330fc RM |
17060 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
17061 | goto bad_alignment; | |
17062 | alignbits = 3; | |
17063 | break; | |
5287ad62 JB |
17064 | default: |
17065 | bad_alignment: | |
477330fc RM |
17066 | first_error (_("bad alignment")); |
17067 | return; | |
5287ad62 JB |
17068 | } |
17069 | ||
17070 | inst.instruction |= alignbits << 4; | |
17071 | inst.instruction |= neon_logbits (et.size) << 6; | |
17072 | ||
17073 | /* Bits [4:6] of the immediate in a list specifier encode register stride | |
17074 | (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of | |
17075 | VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look | |
17076 | up the right value for "type" in a table based on this value and the given | |
17077 | list style, then stick it back. */ | |
17078 | idx = ((inst.operands[0].imm >> 4) & 7) | |
477330fc | 17079 | | (((inst.instruction >> 8) & 3) << 3); |
5287ad62 JB |
17080 | |
17081 | typebits = typetable[idx]; | |
5f4273c7 | 17082 | |
5287ad62 | 17083 | constraint (typebits == -1, _("bad list type for instruction")); |
1d50d57c WN |
17084 | constraint (((inst.instruction >> 8) & 3) && et.size == 64, |
17085 | _("bad element type for instruction")); | |
5287ad62 JB |
17086 | |
17087 | inst.instruction &= ~0xf00; | |
17088 | inst.instruction |= typebits << 8; | |
17089 | } | |
17090 | ||
17091 | /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. | |
17092 | *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 | |
17093 | otherwise. The variable arguments are a list of pairs of legal (size, align) | |
17094 | values, terminated with -1. */ | |
17095 | ||
17096 | static int | |
aa8a0863 | 17097 | neon_alignment_bit (int size, int align, int *do_alignment, ...) |
5287ad62 JB |
17098 | { |
17099 | va_list ap; | |
17100 | int result = FAIL, thissize, thisalign; | |
5f4273c7 | 17101 | |
5287ad62 JB |
17102 | if (!inst.operands[1].immisalign) |
17103 | { | |
aa8a0863 | 17104 | *do_alignment = 0; |
5287ad62 JB |
17105 | return SUCCESS; |
17106 | } | |
5f4273c7 | 17107 | |
aa8a0863 | 17108 | va_start (ap, do_alignment); |
5287ad62 JB |
17109 | |
17110 | do | |
17111 | { | |
17112 | thissize = va_arg (ap, int); | |
17113 | if (thissize == -1) | |
477330fc | 17114 | break; |
5287ad62 JB |
17115 | thisalign = va_arg (ap, int); |
17116 | ||
17117 | if (size == thissize && align == thisalign) | |
477330fc | 17118 | result = SUCCESS; |
5287ad62 JB |
17119 | } |
17120 | while (result != SUCCESS); | |
17121 | ||
17122 | va_end (ap); | |
17123 | ||
17124 | if (result == SUCCESS) | |
aa8a0863 | 17125 | *do_alignment = 1; |
5287ad62 | 17126 | else |
dcbf9037 | 17127 | first_error (_("unsupported alignment for instruction")); |
5f4273c7 | 17128 | |
5287ad62 JB |
17129 | return result; |
17130 | } | |
17131 | ||
17132 | static void | |
17133 | do_neon_ld_st_lane (void) | |
17134 | { | |
037e8744 | 17135 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
aa8a0863 | 17136 | int align_good, do_alignment = 0; |
5287ad62 JB |
17137 | int logsize = neon_logbits (et.size); |
17138 | int align = inst.operands[1].imm >> 8; | |
17139 | int n = (inst.instruction >> 8) & 3; | |
17140 | int max_el = 64 / et.size; | |
5f4273c7 | 17141 | |
dcbf9037 JB |
17142 | if (et.type == NT_invtype) |
17143 | return; | |
5f4273c7 | 17144 | |
5287ad62 | 17145 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, |
477330fc | 17146 | _("bad list length")); |
5287ad62 | 17147 | constraint (NEON_LANE (inst.operands[0].imm) >= max_el, |
477330fc | 17148 | _("scalar index out of range")); |
5287ad62 | 17149 | constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 |
477330fc RM |
17150 | && et.size == 8, |
17151 | _("stride of 2 unavailable when element size is 8")); | |
5f4273c7 | 17152 | |
5287ad62 JB |
17153 | switch (n) |
17154 | { | |
17155 | case 0: /* VLD1 / VST1. */ | |
aa8a0863 | 17156 | align_good = neon_alignment_bit (et.size, align, &do_alignment, 16, 16, |
477330fc | 17157 | 32, 32, -1); |
5287ad62 | 17158 | if (align_good == FAIL) |
477330fc | 17159 | return; |
aa8a0863 | 17160 | if (do_alignment) |
477330fc RM |
17161 | { |
17162 | unsigned alignbits = 0; | |
17163 | switch (et.size) | |
17164 | { | |
17165 | case 16: alignbits = 0x1; break; | |
17166 | case 32: alignbits = 0x3; break; | |
17167 | default: ; | |
17168 | } | |
17169 | inst.instruction |= alignbits << 4; | |
17170 | } | |
5287ad62 JB |
17171 | break; |
17172 | ||
17173 | case 1: /* VLD2 / VST2. */ | |
aa8a0863 TS |
17174 | align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 16, |
17175 | 16, 32, 32, 64, -1); | |
5287ad62 | 17176 | if (align_good == FAIL) |
477330fc | 17177 | return; |
aa8a0863 | 17178 | if (do_alignment) |
477330fc | 17179 | inst.instruction |= 1 << 4; |
5287ad62 JB |
17180 | break; |
17181 | ||
17182 | case 2: /* VLD3 / VST3. */ | |
17183 | constraint (inst.operands[1].immisalign, | |
477330fc | 17184 | _("can't use alignment with this instruction")); |
5287ad62 JB |
17185 | break; |
17186 | ||
17187 | case 3: /* VLD4 / VST4. */ | |
aa8a0863 | 17188 | align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32, |
477330fc | 17189 | 16, 64, 32, 64, 32, 128, -1); |
5287ad62 | 17190 | if (align_good == FAIL) |
477330fc | 17191 | return; |
aa8a0863 | 17192 | if (do_alignment) |
477330fc RM |
17193 | { |
17194 | unsigned alignbits = 0; | |
17195 | switch (et.size) | |
17196 | { | |
17197 | case 8: alignbits = 0x1; break; | |
17198 | case 16: alignbits = 0x1; break; | |
17199 | case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; | |
17200 | default: ; | |
17201 | } | |
17202 | inst.instruction |= alignbits << 4; | |
17203 | } | |
5287ad62 JB |
17204 | break; |
17205 | ||
17206 | default: ; | |
17207 | } | |
17208 | ||
17209 | /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ | |
17210 | if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
17211 | inst.instruction |= 1 << (4 + logsize); | |
5f4273c7 | 17212 | |
5287ad62 JB |
17213 | inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); |
17214 | inst.instruction |= logsize << 10; | |
17215 | } | |
17216 | ||
17217 | /* Encode single n-element structure to all lanes VLD<n> instructions. */ | |
17218 | ||
17219 | static void | |
17220 | do_neon_ld_dup (void) | |
17221 | { | |
037e8744 | 17222 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
aa8a0863 | 17223 | int align_good, do_alignment = 0; |
5287ad62 | 17224 | |
dcbf9037 JB |
17225 | if (et.type == NT_invtype) |
17226 | return; | |
17227 | ||
5287ad62 JB |
17228 | switch ((inst.instruction >> 8) & 3) |
17229 | { | |
17230 | case 0: /* VLD1. */ | |
9c2799c2 | 17231 | gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); |
5287ad62 | 17232 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, |
aa8a0863 | 17233 | &do_alignment, 16, 16, 32, 32, -1); |
5287ad62 | 17234 | if (align_good == FAIL) |
477330fc | 17235 | return; |
5287ad62 | 17236 | switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) |
477330fc RM |
17237 | { |
17238 | case 1: break; | |
17239 | case 2: inst.instruction |= 1 << 5; break; | |
17240 | default: first_error (_("bad list length")); return; | |
17241 | } | |
5287ad62 JB |
17242 | inst.instruction |= neon_logbits (et.size) << 6; |
17243 | break; | |
17244 | ||
17245 | case 1: /* VLD2. */ | |
17246 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, | |
aa8a0863 TS |
17247 | &do_alignment, 8, 16, 16, 32, 32, 64, |
17248 | -1); | |
5287ad62 | 17249 | if (align_good == FAIL) |
477330fc | 17250 | return; |
5287ad62 | 17251 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, |
477330fc | 17252 | _("bad list length")); |
5287ad62 | 17253 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) |
477330fc | 17254 | inst.instruction |= 1 << 5; |
5287ad62 JB |
17255 | inst.instruction |= neon_logbits (et.size) << 6; |
17256 | break; | |
17257 | ||
17258 | case 2: /* VLD3. */ | |
17259 | constraint (inst.operands[1].immisalign, | |
477330fc | 17260 | _("can't use alignment with this instruction")); |
5287ad62 | 17261 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, |
477330fc | 17262 | _("bad list length")); |
5287ad62 | 17263 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) |
477330fc | 17264 | inst.instruction |= 1 << 5; |
5287ad62 JB |
17265 | inst.instruction |= neon_logbits (et.size) << 6; |
17266 | break; | |
17267 | ||
17268 | case 3: /* VLD4. */ | |
17269 | { | |
477330fc | 17270 | int align = inst.operands[1].imm >> 8; |
aa8a0863 | 17271 | align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32, |
477330fc RM |
17272 | 16, 64, 32, 64, 32, 128, -1); |
17273 | if (align_good == FAIL) | |
17274 | return; | |
17275 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, | |
17276 | _("bad list length")); | |
17277 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
17278 | inst.instruction |= 1 << 5; | |
17279 | if (et.size == 32 && align == 128) | |
17280 | inst.instruction |= 0x3 << 6; | |
17281 | else | |
17282 | inst.instruction |= neon_logbits (et.size) << 6; | |
5287ad62 JB |
17283 | } |
17284 | break; | |
17285 | ||
17286 | default: ; | |
17287 | } | |
17288 | ||
aa8a0863 | 17289 | inst.instruction |= do_alignment << 4; |
5287ad62 JB |
17290 | } |
17291 | ||
17292 | /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those | |
17293 | apart from bits [11:4]. */ | |
17294 | ||
17295 | static void | |
17296 | do_neon_ldx_stx (void) | |
17297 | { | |
b1a769ed DG |
17298 | if (inst.operands[1].isreg) |
17299 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); | |
17300 | ||
5287ad62 JB |
17301 | switch (NEON_LANE (inst.operands[0].imm)) |
17302 | { | |
17303 | case NEON_INTERLEAVE_LANES: | |
88714cb8 | 17304 | NEON_ENCODE (INTERLV, inst); |
5287ad62 JB |
17305 | do_neon_ld_st_interleave (); |
17306 | break; | |
5f4273c7 | 17307 | |
5287ad62 | 17308 | case NEON_ALL_LANES: |
88714cb8 | 17309 | NEON_ENCODE (DUP, inst); |
2d51fb74 JB |
17310 | if (inst.instruction == N_INV) |
17311 | { | |
17312 | first_error ("only loads support such operands"); | |
17313 | break; | |
17314 | } | |
5287ad62 JB |
17315 | do_neon_ld_dup (); |
17316 | break; | |
5f4273c7 | 17317 | |
5287ad62 | 17318 | default: |
88714cb8 | 17319 | NEON_ENCODE (LANE, inst); |
5287ad62 JB |
17320 | do_neon_ld_st_lane (); |
17321 | } | |
17322 | ||
17323 | /* L bit comes from bit mask. */ | |
17324 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
17325 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17326 | inst.instruction |= inst.operands[1].reg << 16; | |
5f4273c7 | 17327 | |
5287ad62 JB |
17328 | if (inst.operands[1].postind) |
17329 | { | |
17330 | int postreg = inst.operands[1].imm & 0xf; | |
17331 | constraint (!inst.operands[1].immisreg, | |
477330fc | 17332 | _("post-index must be a register")); |
5287ad62 | 17333 | constraint (postreg == 0xd || postreg == 0xf, |
477330fc | 17334 | _("bad register for post-index")); |
5287ad62 JB |
17335 | inst.instruction |= postreg; |
17336 | } | |
4f2374c7 | 17337 | else |
5287ad62 | 17338 | { |
4f2374c7 WN |
17339 | constraint (inst.operands[1].immisreg, BAD_ADDR_MODE); |
17340 | constraint (inst.reloc.exp.X_op != O_constant | |
17341 | || inst.reloc.exp.X_add_number != 0, | |
17342 | BAD_ADDR_MODE); | |
17343 | ||
17344 | if (inst.operands[1].writeback) | |
17345 | { | |
17346 | inst.instruction |= 0xd; | |
17347 | } | |
17348 | else | |
17349 | inst.instruction |= 0xf; | |
5287ad62 | 17350 | } |
5f4273c7 | 17351 | |
5287ad62 JB |
17352 | if (thumb_mode) |
17353 | inst.instruction |= 0xf9000000; | |
17354 | else | |
17355 | inst.instruction |= 0xf4000000; | |
17356 | } | |
33399f07 MGD |
17357 | |
17358 | /* FP v8. */ | |
17359 | static void | |
17360 | do_vfp_nsyn_fpv8 (enum neon_shape rs) | |
17361 | { | |
a715796b TG |
17362 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
17363 | D register operands. */ | |
17364 | if (neon_shape_class[rs] == SC_DOUBLE) | |
17365 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
17366 | _(BAD_FPU)); | |
17367 | ||
33399f07 MGD |
17368 | NEON_ENCODE (FPV8, inst); |
17369 | ||
9db2f6b4 RL |
17370 | if (rs == NS_FFF || rs == NS_HHH) |
17371 | { | |
17372 | do_vfp_sp_dyadic (); | |
17373 | ||
17374 | /* ARMv8.2 fp16 instruction. */ | |
17375 | if (rs == NS_HHH) | |
17376 | do_scalar_fp16_v82_encode (); | |
17377 | } | |
33399f07 MGD |
17378 | else |
17379 | do_vfp_dp_rd_rn_rm (); | |
17380 | ||
17381 | if (rs == NS_DDD) | |
17382 | inst.instruction |= 0x100; | |
17383 | ||
17384 | inst.instruction |= 0xf0000000; | |
17385 | } | |
17386 | ||
17387 | static void | |
17388 | do_vsel (void) | |
17389 | { | |
17390 | set_it_insn_type (OUTSIDE_IT_INSN); | |
17391 | ||
17392 | if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS) | |
17393 | first_error (_("invalid instruction shape")); | |
17394 | } | |
17395 | ||
73924fbc MGD |
17396 | static void |
17397 | do_vmaxnm (void) | |
17398 | { | |
17399 | set_it_insn_type (OUTSIDE_IT_INSN); | |
17400 | ||
17401 | if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS) | |
17402 | return; | |
17403 | ||
17404 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL) | |
17405 | return; | |
17406 | ||
cc933301 | 17407 | neon_dyadic_misc (NT_untyped, N_F_16_32, 0); |
73924fbc MGD |
17408 | } |
17409 | ||
30bdf752 MGD |
17410 | static void |
17411 | do_vrint_1 (enum neon_cvt_mode mode) | |
17412 | { | |
9db2f6b4 | 17413 | enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_QQ, NS_NULL); |
30bdf752 MGD |
17414 | struct neon_type_el et; |
17415 | ||
17416 | if (rs == NS_NULL) | |
17417 | return; | |
17418 | ||
a715796b TG |
17419 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
17420 | D register operands. */ | |
17421 | if (neon_shape_class[rs] == SC_DOUBLE) | |
17422 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
17423 | _(BAD_FPU)); | |
17424 | ||
9db2f6b4 RL |
17425 | et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY |
17426 | | N_VFP); | |
30bdf752 MGD |
17427 | if (et.type != NT_invtype) |
17428 | { | |
17429 | /* VFP encodings. */ | |
17430 | if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n | |
17431 | || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m) | |
17432 | set_it_insn_type (OUTSIDE_IT_INSN); | |
17433 | ||
17434 | NEON_ENCODE (FPV8, inst); | |
9db2f6b4 | 17435 | if (rs == NS_FF || rs == NS_HH) |
30bdf752 MGD |
17436 | do_vfp_sp_monadic (); |
17437 | else | |
17438 | do_vfp_dp_rd_rm (); | |
17439 | ||
17440 | switch (mode) | |
17441 | { | |
17442 | case neon_cvt_mode_r: inst.instruction |= 0x00000000; break; | |
17443 | case neon_cvt_mode_z: inst.instruction |= 0x00000080; break; | |
17444 | case neon_cvt_mode_x: inst.instruction |= 0x00010000; break; | |
17445 | case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break; | |
17446 | case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break; | |
17447 | case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break; | |
17448 | case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break; | |
17449 | default: abort (); | |
17450 | } | |
17451 | ||
17452 | inst.instruction |= (rs == NS_DD) << 8; | |
17453 | do_vfp_cond_or_thumb (); | |
9db2f6b4 RL |
17454 | |
17455 | /* ARMv8.2 fp16 vrint instruction. */ | |
17456 | if (rs == NS_HH) | |
17457 | do_scalar_fp16_v82_encode (); | |
30bdf752 MGD |
17458 | } |
17459 | else | |
17460 | { | |
17461 | /* Neon encodings (or something broken...). */ | |
17462 | inst.error = NULL; | |
cc933301 | 17463 | et = neon_check_type (2, rs, N_EQK, N_F_16_32 | N_KEY); |
30bdf752 MGD |
17464 | |
17465 | if (et.type == NT_invtype) | |
17466 | return; | |
17467 | ||
17468 | set_it_insn_type (OUTSIDE_IT_INSN); | |
17469 | NEON_ENCODE (FLOAT, inst); | |
17470 | ||
17471 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL) | |
17472 | return; | |
17473 | ||
17474 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
17475 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17476 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
17477 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
17478 | inst.instruction |= neon_quad (rs) << 6; | |
cc933301 JW |
17479 | /* Mask off the original size bits and reencode them. */ |
17480 | inst.instruction = ((inst.instruction & 0xfff3ffff) | |
17481 | | neon_logbits (et.size) << 18); | |
17482 | ||
30bdf752 MGD |
17483 | switch (mode) |
17484 | { | |
17485 | case neon_cvt_mode_z: inst.instruction |= 3 << 7; break; | |
17486 | case neon_cvt_mode_x: inst.instruction |= 1 << 7; break; | |
17487 | case neon_cvt_mode_a: inst.instruction |= 2 << 7; break; | |
17488 | case neon_cvt_mode_n: inst.instruction |= 0 << 7; break; | |
17489 | case neon_cvt_mode_p: inst.instruction |= 7 << 7; break; | |
17490 | case neon_cvt_mode_m: inst.instruction |= 5 << 7; break; | |
17491 | case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break; | |
17492 | default: abort (); | |
17493 | } | |
17494 | ||
17495 | if (thumb_mode) | |
17496 | inst.instruction |= 0xfc000000; | |
17497 | else | |
17498 | inst.instruction |= 0xf0000000; | |
17499 | } | |
17500 | } | |
17501 | ||
17502 | static void | |
17503 | do_vrintx (void) | |
17504 | { | |
17505 | do_vrint_1 (neon_cvt_mode_x); | |
17506 | } | |
17507 | ||
17508 | static void | |
17509 | do_vrintz (void) | |
17510 | { | |
17511 | do_vrint_1 (neon_cvt_mode_z); | |
17512 | } | |
17513 | ||
17514 | static void | |
17515 | do_vrintr (void) | |
17516 | { | |
17517 | do_vrint_1 (neon_cvt_mode_r); | |
17518 | } | |
17519 | ||
17520 | static void | |
17521 | do_vrinta (void) | |
17522 | { | |
17523 | do_vrint_1 (neon_cvt_mode_a); | |
17524 | } | |
17525 | ||
17526 | static void | |
17527 | do_vrintn (void) | |
17528 | { | |
17529 | do_vrint_1 (neon_cvt_mode_n); | |
17530 | } | |
17531 | ||
17532 | static void | |
17533 | do_vrintp (void) | |
17534 | { | |
17535 | do_vrint_1 (neon_cvt_mode_p); | |
17536 | } | |
17537 | ||
17538 | static void | |
17539 | do_vrintm (void) | |
17540 | { | |
17541 | do_vrint_1 (neon_cvt_mode_m); | |
17542 | } | |
17543 | ||
c28eeff2 SN |
17544 | static unsigned |
17545 | neon_scalar_for_vcmla (unsigned opnd, unsigned elsize) | |
17546 | { | |
17547 | unsigned regno = NEON_SCALAR_REG (opnd); | |
17548 | unsigned elno = NEON_SCALAR_INDEX (opnd); | |
17549 | ||
17550 | if (elsize == 16 && elno < 2 && regno < 16) | |
17551 | return regno | (elno << 4); | |
17552 | else if (elsize == 32 && elno == 0) | |
17553 | return regno; | |
17554 | ||
17555 | first_error (_("scalar out of range")); | |
17556 | return 0; | |
17557 | } | |
17558 | ||
17559 | static void | |
17560 | do_vcmla (void) | |
17561 | { | |
17562 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8), | |
17563 | _(BAD_FPU)); | |
17564 | constraint (inst.reloc.exp.X_op != O_constant, _("expression too complex")); | |
17565 | unsigned rot = inst.reloc.exp.X_add_number; | |
17566 | constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270, | |
17567 | _("immediate out of range")); | |
17568 | rot /= 90; | |
17569 | if (inst.operands[2].isscalar) | |
17570 | { | |
17571 | enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL); | |
17572 | unsigned size = neon_check_type (3, rs, N_EQK, N_EQK, | |
17573 | N_KEY | N_F16 | N_F32).size; | |
17574 | unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size); | |
17575 | inst.is_neon = 1; | |
17576 | inst.instruction = 0xfe000800; | |
17577 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
17578 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17579 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
17580 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
17581 | inst.instruction |= LOW4 (m); | |
17582 | inst.instruction |= HI1 (m) << 5; | |
17583 | inst.instruction |= neon_quad (rs) << 6; | |
17584 | inst.instruction |= rot << 20; | |
17585 | inst.instruction |= (size == 32) << 23; | |
17586 | } | |
17587 | else | |
17588 | { | |
17589 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); | |
17590 | unsigned size = neon_check_type (3, rs, N_EQK, N_EQK, | |
17591 | N_KEY | N_F16 | N_F32).size; | |
17592 | neon_three_same (neon_quad (rs), 0, -1); | |
17593 | inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */ | |
17594 | inst.instruction |= 0xfc200800; | |
17595 | inst.instruction |= rot << 23; | |
17596 | inst.instruction |= (size == 32) << 20; | |
17597 | } | |
17598 | } | |
17599 | ||
17600 | static void | |
17601 | do_vcadd (void) | |
17602 | { | |
17603 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8), | |
17604 | _(BAD_FPU)); | |
17605 | constraint (inst.reloc.exp.X_op != O_constant, _("expression too complex")); | |
17606 | unsigned rot = inst.reloc.exp.X_add_number; | |
17607 | constraint (rot != 90 && rot != 270, _("immediate out of range")); | |
17608 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); | |
17609 | unsigned size = neon_check_type (3, rs, N_EQK, N_EQK, | |
17610 | N_KEY | N_F16 | N_F32).size; | |
17611 | neon_three_same (neon_quad (rs), 0, -1); | |
17612 | inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */ | |
17613 | inst.instruction |= 0xfc800800; | |
17614 | inst.instruction |= (rot == 270) << 24; | |
17615 | inst.instruction |= (size == 32) << 20; | |
17616 | } | |
17617 | ||
c604a79a JW |
17618 | /* Dot Product instructions encoding support. */ |
17619 | ||
17620 | static void | |
17621 | do_neon_dotproduct (int unsigned_p) | |
17622 | { | |
17623 | enum neon_shape rs; | |
17624 | unsigned scalar_oprd2 = 0; | |
17625 | int high8; | |
17626 | ||
17627 | if (inst.cond != COND_ALWAYS) | |
17628 | as_warn (_("Dot Product instructions cannot be conditional, the behaviour " | |
17629 | "is UNPREDICTABLE")); | |
17630 | ||
17631 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8), | |
17632 | _(BAD_FPU)); | |
17633 | ||
17634 | /* Dot Product instructions are in three-same D/Q register format or the third | |
17635 | operand can be a scalar index register. */ | |
17636 | if (inst.operands[2].isscalar) | |
17637 | { | |
17638 | scalar_oprd2 = neon_scalar_for_mul (inst.operands[2].reg, 32); | |
17639 | high8 = 0xfe000000; | |
17640 | rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); | |
17641 | } | |
17642 | else | |
17643 | { | |
17644 | high8 = 0xfc000000; | |
17645 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
17646 | } | |
17647 | ||
17648 | if (unsigned_p) | |
17649 | neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_U8); | |
17650 | else | |
17651 | neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_S8); | |
17652 | ||
17653 | /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot | |
17654 | Product instruction, so we pass 0 as the "ubit" parameter. And the | |
17655 | "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */ | |
17656 | neon_three_same (neon_quad (rs), 0, 32); | |
17657 | ||
17658 | /* Undo neon_dp_fixup. Dot Product instructions are using a slightly | |
17659 | different NEON three-same encoding. */ | |
17660 | inst.instruction &= 0x00ffffff; | |
17661 | inst.instruction |= high8; | |
17662 | /* Encode 'U' bit which indicates signedness. */ | |
17663 | inst.instruction |= (unsigned_p ? 1 : 0) << 4; | |
17664 | /* Re-encode operand2 if it's indexed scalar operand. What has been encoded | |
17665 | from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not | |
17666 | the instruction encoding. */ | |
17667 | if (inst.operands[2].isscalar) | |
17668 | { | |
17669 | inst.instruction &= 0xffffffd0; | |
17670 | inst.instruction |= LOW4 (scalar_oprd2); | |
17671 | inst.instruction |= HI1 (scalar_oprd2) << 5; | |
17672 | } | |
17673 | } | |
17674 | ||
17675 | /* Dot Product instructions for signed integer. */ | |
17676 | ||
17677 | static void | |
17678 | do_neon_dotproduct_s (void) | |
17679 | { | |
17680 | return do_neon_dotproduct (0); | |
17681 | } | |
17682 | ||
17683 | /* Dot Product instructions for unsigned integer. */ | |
17684 | ||
17685 | static void | |
17686 | do_neon_dotproduct_u (void) | |
17687 | { | |
17688 | return do_neon_dotproduct (1); | |
17689 | } | |
17690 | ||
91ff7894 MGD |
17691 | /* Crypto v1 instructions. */ |
17692 | static void | |
17693 | do_crypto_2op_1 (unsigned elttype, int op) | |
17694 | { | |
17695 | set_it_insn_type (OUTSIDE_IT_INSN); | |
17696 | ||
17697 | if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type | |
17698 | == NT_invtype) | |
17699 | return; | |
17700 | ||
17701 | inst.error = NULL; | |
17702 | ||
17703 | NEON_ENCODE (INTEGER, inst); | |
17704 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
17705 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17706 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
17707 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
17708 | if (op != -1) | |
17709 | inst.instruction |= op << 6; | |
17710 | ||
17711 | if (thumb_mode) | |
17712 | inst.instruction |= 0xfc000000; | |
17713 | else | |
17714 | inst.instruction |= 0xf0000000; | |
17715 | } | |
17716 | ||
48adcd8e MGD |
17717 | static void |
17718 | do_crypto_3op_1 (int u, int op) | |
17719 | { | |
17720 | set_it_insn_type (OUTSIDE_IT_INSN); | |
17721 | ||
17722 | if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT, | |
17723 | N_32 | N_UNT | N_KEY).type == NT_invtype) | |
17724 | return; | |
17725 | ||
17726 | inst.error = NULL; | |
17727 | ||
17728 | NEON_ENCODE (INTEGER, inst); | |
17729 | neon_three_same (1, u, 8 << op); | |
17730 | } | |
17731 | ||
91ff7894 MGD |
17732 | static void |
17733 | do_aese (void) | |
17734 | { | |
17735 | do_crypto_2op_1 (N_8, 0); | |
17736 | } | |
17737 | ||
17738 | static void | |
17739 | do_aesd (void) | |
17740 | { | |
17741 | do_crypto_2op_1 (N_8, 1); | |
17742 | } | |
17743 | ||
17744 | static void | |
17745 | do_aesmc (void) | |
17746 | { | |
17747 | do_crypto_2op_1 (N_8, 2); | |
17748 | } | |
17749 | ||
17750 | static void | |
17751 | do_aesimc (void) | |
17752 | { | |
17753 | do_crypto_2op_1 (N_8, 3); | |
17754 | } | |
17755 | ||
48adcd8e MGD |
17756 | static void |
17757 | do_sha1c (void) | |
17758 | { | |
17759 | do_crypto_3op_1 (0, 0); | |
17760 | } | |
17761 | ||
17762 | static void | |
17763 | do_sha1p (void) | |
17764 | { | |
17765 | do_crypto_3op_1 (0, 1); | |
17766 | } | |
17767 | ||
17768 | static void | |
17769 | do_sha1m (void) | |
17770 | { | |
17771 | do_crypto_3op_1 (0, 2); | |
17772 | } | |
17773 | ||
17774 | static void | |
17775 | do_sha1su0 (void) | |
17776 | { | |
17777 | do_crypto_3op_1 (0, 3); | |
17778 | } | |
91ff7894 | 17779 | |
48adcd8e MGD |
17780 | static void |
17781 | do_sha256h (void) | |
17782 | { | |
17783 | do_crypto_3op_1 (1, 0); | |
17784 | } | |
17785 | ||
17786 | static void | |
17787 | do_sha256h2 (void) | |
17788 | { | |
17789 | do_crypto_3op_1 (1, 1); | |
17790 | } | |
17791 | ||
17792 | static void | |
17793 | do_sha256su1 (void) | |
17794 | { | |
17795 | do_crypto_3op_1 (1, 2); | |
17796 | } | |
3c9017d2 MGD |
17797 | |
17798 | static void | |
17799 | do_sha1h (void) | |
17800 | { | |
17801 | do_crypto_2op_1 (N_32, -1); | |
17802 | } | |
17803 | ||
17804 | static void | |
17805 | do_sha1su1 (void) | |
17806 | { | |
17807 | do_crypto_2op_1 (N_32, 0); | |
17808 | } | |
17809 | ||
17810 | static void | |
17811 | do_sha256su0 (void) | |
17812 | { | |
17813 | do_crypto_2op_1 (N_32, 1); | |
17814 | } | |
dd5181d5 KT |
17815 | |
17816 | static void | |
17817 | do_crc32_1 (unsigned int poly, unsigned int sz) | |
17818 | { | |
17819 | unsigned int Rd = inst.operands[0].reg; | |
17820 | unsigned int Rn = inst.operands[1].reg; | |
17821 | unsigned int Rm = inst.operands[2].reg; | |
17822 | ||
17823 | set_it_insn_type (OUTSIDE_IT_INSN); | |
17824 | inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12); | |
17825 | inst.instruction |= LOW4 (Rn) << 16; | |
17826 | inst.instruction |= LOW4 (Rm); | |
17827 | inst.instruction |= sz << (thumb_mode ? 4 : 21); | |
17828 | inst.instruction |= poly << (thumb_mode ? 20 : 9); | |
17829 | ||
17830 | if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC) | |
17831 | as_warn (UNPRED_REG ("r15")); | |
dd5181d5 KT |
17832 | } |
17833 | ||
17834 | static void | |
17835 | do_crc32b (void) | |
17836 | { | |
17837 | do_crc32_1 (0, 0); | |
17838 | } | |
17839 | ||
17840 | static void | |
17841 | do_crc32h (void) | |
17842 | { | |
17843 | do_crc32_1 (0, 1); | |
17844 | } | |
17845 | ||
17846 | static void | |
17847 | do_crc32w (void) | |
17848 | { | |
17849 | do_crc32_1 (0, 2); | |
17850 | } | |
17851 | ||
17852 | static void | |
17853 | do_crc32cb (void) | |
17854 | { | |
17855 | do_crc32_1 (1, 0); | |
17856 | } | |
17857 | ||
17858 | static void | |
17859 | do_crc32ch (void) | |
17860 | { | |
17861 | do_crc32_1 (1, 1); | |
17862 | } | |
17863 | ||
17864 | static void | |
17865 | do_crc32cw (void) | |
17866 | { | |
17867 | do_crc32_1 (1, 2); | |
17868 | } | |
17869 | ||
49e8a725 SN |
17870 | static void |
17871 | do_vjcvt (void) | |
17872 | { | |
17873 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
17874 | _(BAD_FPU)); | |
17875 | neon_check_type (2, NS_FD, N_S32, N_F64); | |
17876 | do_vfp_sp_dp_cvt (); | |
17877 | do_vfp_cond_or_thumb (); | |
17878 | } | |
17879 | ||
5287ad62 JB |
17880 | \f |
17881 | /* Overall per-instruction processing. */ | |
17882 | ||
17883 | /* We need to be able to fix up arbitrary expressions in some statements. | |
17884 | This is so that we can handle symbols that are an arbitrary distance from | |
17885 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
17886 | which returns part of an address in a form which will be valid for | |
17887 | a data instruction. We do this by pushing the expression into a symbol | |
17888 | in the expr_section, and creating a fix for that. */ | |
17889 | ||
17890 | static void | |
17891 | fix_new_arm (fragS * frag, | |
17892 | int where, | |
17893 | short int size, | |
17894 | expressionS * exp, | |
17895 | int pc_rel, | |
17896 | int reloc) | |
17897 | { | |
17898 | fixS * new_fix; | |
17899 | ||
17900 | switch (exp->X_op) | |
17901 | { | |
17902 | case O_constant: | |
6e7ce2cd PB |
17903 | if (pc_rel) |
17904 | { | |
17905 | /* Create an absolute valued symbol, so we have something to | |
477330fc RM |
17906 | refer to in the object file. Unfortunately for us, gas's |
17907 | generic expression parsing will already have folded out | |
17908 | any use of .set foo/.type foo %function that may have | |
17909 | been used to set type information of the target location, | |
17910 | that's being specified symbolically. We have to presume | |
17911 | the user knows what they are doing. */ | |
6e7ce2cd PB |
17912 | char name[16 + 8]; |
17913 | symbolS *symbol; | |
17914 | ||
17915 | sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number); | |
17916 | ||
17917 | symbol = symbol_find_or_make (name); | |
17918 | S_SET_SEGMENT (symbol, absolute_section); | |
17919 | symbol_set_frag (symbol, &zero_address_frag); | |
17920 | S_SET_VALUE (symbol, exp->X_add_number); | |
17921 | exp->X_op = O_symbol; | |
17922 | exp->X_add_symbol = symbol; | |
17923 | exp->X_add_number = 0; | |
17924 | } | |
17925 | /* FALLTHROUGH */ | |
5287ad62 JB |
17926 | case O_symbol: |
17927 | case O_add: | |
17928 | case O_subtract: | |
21d799b5 | 17929 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, |
477330fc | 17930 | (enum bfd_reloc_code_real) reloc); |
5287ad62 JB |
17931 | break; |
17932 | ||
17933 | default: | |
21d799b5 | 17934 | new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0, |
477330fc | 17935 | pc_rel, (enum bfd_reloc_code_real) reloc); |
5287ad62 JB |
17936 | break; |
17937 | } | |
17938 | ||
17939 | /* Mark whether the fix is to a THUMB instruction, or an ARM | |
17940 | instruction. */ | |
17941 | new_fix->tc_fix_data = thumb_mode; | |
17942 | } | |
17943 | ||
17944 | /* Create a frg for an instruction requiring relaxation. */ | |
17945 | static void | |
17946 | output_relax_insn (void) | |
17947 | { | |
17948 | char * to; | |
17949 | symbolS *sym; | |
0110f2b8 PB |
17950 | int offset; |
17951 | ||
6e1cb1a6 PB |
17952 | /* The size of the instruction is unknown, so tie the debug info to the |
17953 | start of the instruction. */ | |
17954 | dwarf2_emit_insn (0); | |
6e1cb1a6 | 17955 | |
0110f2b8 PB |
17956 | switch (inst.reloc.exp.X_op) |
17957 | { | |
17958 | case O_symbol: | |
17959 | sym = inst.reloc.exp.X_add_symbol; | |
17960 | offset = inst.reloc.exp.X_add_number; | |
17961 | break; | |
17962 | case O_constant: | |
17963 | sym = NULL; | |
17964 | offset = inst.reloc.exp.X_add_number; | |
17965 | break; | |
17966 | default: | |
17967 | sym = make_expr_symbol (&inst.reloc.exp); | |
17968 | offset = 0; | |
17969 | break; | |
17970 | } | |
17971 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
17972 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
17973 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
0110f2b8 PB |
17974 | } |
17975 | ||
17976 | /* Write a 32-bit thumb instruction to buf. */ | |
17977 | static void | |
17978 | put_thumb32_insn (char * buf, unsigned long insn) | |
17979 | { | |
17980 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
17981 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
17982 | } | |
17983 | ||
b99bd4ef | 17984 | static void |
c19d1205 | 17985 | output_inst (const char * str) |
b99bd4ef | 17986 | { |
c19d1205 | 17987 | char * to = NULL; |
b99bd4ef | 17988 | |
c19d1205 | 17989 | if (inst.error) |
b99bd4ef | 17990 | { |
c19d1205 | 17991 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
17992 | return; |
17993 | } | |
5f4273c7 NC |
17994 | if (inst.relax) |
17995 | { | |
17996 | output_relax_insn (); | |
0110f2b8 | 17997 | return; |
5f4273c7 | 17998 | } |
c19d1205 ZW |
17999 | if (inst.size == 0) |
18000 | return; | |
b99bd4ef | 18001 | |
c19d1205 | 18002 | to = frag_more (inst.size); |
8dc2430f NC |
18003 | /* PR 9814: Record the thumb mode into the current frag so that we know |
18004 | what type of NOP padding to use, if necessary. We override any previous | |
18005 | setting so that if the mode has changed then the NOPS that we use will | |
18006 | match the encoding of the last instruction in the frag. */ | |
cd000bff | 18007 | frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
c19d1205 ZW |
18008 | |
18009 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 18010 | { |
9c2799c2 | 18011 | gas_assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 18012 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 18013 | } |
c19d1205 | 18014 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 18015 | { |
9c2799c2 | 18016 | gas_assert (inst.size == (2 * INSN_SIZE)); |
c19d1205 ZW |
18017 | md_number_to_chars (to, inst.instruction, INSN_SIZE); |
18018 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 18019 | } |
c19d1205 ZW |
18020 | else |
18021 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 18022 | |
c19d1205 ZW |
18023 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
18024 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
18025 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
18026 | inst.reloc.type); | |
b99bd4ef | 18027 | |
c19d1205 | 18028 | dwarf2_emit_insn (inst.size); |
c19d1205 | 18029 | } |
b99bd4ef | 18030 | |
e07e6e58 NC |
18031 | static char * |
18032 | output_it_inst (int cond, int mask, char * to) | |
18033 | { | |
18034 | unsigned long instruction = 0xbf00; | |
18035 | ||
18036 | mask &= 0xf; | |
18037 | instruction |= mask; | |
18038 | instruction |= cond << 4; | |
18039 | ||
18040 | if (to == NULL) | |
18041 | { | |
18042 | to = frag_more (2); | |
18043 | #ifdef OBJ_ELF | |
18044 | dwarf2_emit_insn (2); | |
18045 | #endif | |
18046 | } | |
18047 | ||
18048 | md_number_to_chars (to, instruction, 2); | |
18049 | ||
18050 | return to; | |
18051 | } | |
18052 | ||
c19d1205 ZW |
18053 | /* Tag values used in struct asm_opcode's tag field. */ |
18054 | enum opcode_tag | |
18055 | { | |
18056 | OT_unconditional, /* Instruction cannot be conditionalized. | |
18057 | The ARM condition field is still 0xE. */ | |
18058 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
18059 | and carries 0xF in its ARM condition field. */ | |
18060 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
037e8744 | 18061 | OT_csuffixF, /* Some forms of the instruction take a conditional |
477330fc RM |
18062 | suffix, others place 0xF where the condition field |
18063 | would be. */ | |
c19d1205 ZW |
18064 | OT_cinfix3, /* Instruction takes a conditional infix, |
18065 | beginning at character index 3. (In | |
18066 | unified mode, it becomes a suffix.) */ | |
088fa78e KH |
18067 | OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for |
18068 | tsts, cmps, cmns, and teqs. */ | |
e3cb604e PB |
18069 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
18070 | character index 3, even in unified mode. Used for | |
18071 | legacy instructions where suffix and infix forms | |
18072 | may be ambiguous. */ | |
c19d1205 | 18073 | OT_csuf_or_in3, /* Instruction takes either a conditional |
e3cb604e | 18074 | suffix or an infix at character index 3. */ |
c19d1205 ZW |
18075 | OT_odd_infix_unc, /* This is the unconditional variant of an |
18076 | instruction that takes a conditional infix | |
18077 | at an unusual position. In unified mode, | |
18078 | this variant will accept a suffix. */ | |
18079 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
18080 | are the conditional variants of instructions that | |
18081 | take conditional infixes in unusual positions. | |
18082 | The infix appears at character index | |
18083 | (tag - OT_odd_infix_0). These are not accepted | |
18084 | in unified mode. */ | |
18085 | }; | |
b99bd4ef | 18086 | |
c19d1205 ZW |
18087 | /* Subroutine of md_assemble, responsible for looking up the primary |
18088 | opcode from the mnemonic the user wrote. STR points to the | |
18089 | beginning of the mnemonic. | |
18090 | ||
18091 | This is not simply a hash table lookup, because of conditional | |
18092 | variants. Most instructions have conditional variants, which are | |
18093 | expressed with a _conditional affix_ to the mnemonic. If we were | |
18094 | to encode each conditional variant as a literal string in the opcode | |
18095 | table, it would have approximately 20,000 entries. | |
18096 | ||
18097 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
18098 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
18099 | instructions take the affix as an infix, notably the s-variants of | |
18100 | the arithmetic instructions. Of those instructions, all but six | |
18101 | have the infix appear after the third character of the mnemonic. | |
18102 | ||
18103 | Accordingly, the algorithm for looking up primary opcodes given | |
18104 | an identifier is: | |
18105 | ||
18106 | 1. Look up the identifier in the opcode table. | |
18107 | If we find a match, go to step U. | |
18108 | ||
18109 | 2. Look up the last two characters of the identifier in the | |
18110 | conditions table. If we find a match, look up the first N-2 | |
18111 | characters of the identifier in the opcode table. If we | |
18112 | find a match, go to step CE. | |
18113 | ||
18114 | 3. Look up the fourth and fifth characters of the identifier in | |
18115 | the conditions table. If we find a match, extract those | |
18116 | characters from the identifier, and look up the remaining | |
18117 | characters in the opcode table. If we find a match, go | |
18118 | to step CM. | |
18119 | ||
18120 | 4. Fail. | |
18121 | ||
18122 | U. Examine the tag field of the opcode structure, in case this is | |
18123 | one of the six instructions with its conditional infix in an | |
18124 | unusual place. If it is, the tag tells us where to find the | |
18125 | infix; look it up in the conditions table and set inst.cond | |
18126 | accordingly. Otherwise, this is an unconditional instruction. | |
18127 | Again set inst.cond accordingly. Return the opcode structure. | |
18128 | ||
18129 | CE. Examine the tag field to make sure this is an instruction that | |
18130 | should receive a conditional suffix. If it is not, fail. | |
18131 | Otherwise, set inst.cond from the suffix we already looked up, | |
18132 | and return the opcode structure. | |
18133 | ||
18134 | CM. Examine the tag field to make sure this is an instruction that | |
18135 | should receive a conditional infix after the third character. | |
18136 | If it is not, fail. Otherwise, undo the edits to the current | |
18137 | line of input and proceed as for case CE. */ | |
18138 | ||
18139 | static const struct asm_opcode * | |
18140 | opcode_lookup (char **str) | |
18141 | { | |
18142 | char *end, *base; | |
18143 | char *affix; | |
18144 | const struct asm_opcode *opcode; | |
18145 | const struct asm_cond *cond; | |
e3cb604e | 18146 | char save[2]; |
c19d1205 ZW |
18147 | |
18148 | /* Scan up to the end of the mnemonic, which must end in white space, | |
721a8186 | 18149 | '.' (in unified mode, or for Neon/VFP instructions), or end of string. */ |
c19d1205 | 18150 | for (base = end = *str; *end != '\0'; end++) |
721a8186 | 18151 | if (*end == ' ' || *end == '.') |
c19d1205 | 18152 | break; |
b99bd4ef | 18153 | |
c19d1205 | 18154 | if (end == base) |
c921be7d | 18155 | return NULL; |
b99bd4ef | 18156 | |
5287ad62 | 18157 | /* Handle a possible width suffix and/or Neon type suffix. */ |
c19d1205 | 18158 | if (end[0] == '.') |
b99bd4ef | 18159 | { |
5287ad62 | 18160 | int offset = 2; |
5f4273c7 | 18161 | |
267d2029 | 18162 | /* The .w and .n suffixes are only valid if the unified syntax is in |
477330fc | 18163 | use. */ |
267d2029 | 18164 | if (unified_syntax && end[1] == 'w') |
c19d1205 | 18165 | inst.size_req = 4; |
267d2029 | 18166 | else if (unified_syntax && end[1] == 'n') |
c19d1205 ZW |
18167 | inst.size_req = 2; |
18168 | else | |
477330fc | 18169 | offset = 0; |
5287ad62 JB |
18170 | |
18171 | inst.vectype.elems = 0; | |
18172 | ||
18173 | *str = end + offset; | |
b99bd4ef | 18174 | |
5f4273c7 | 18175 | if (end[offset] == '.') |
5287ad62 | 18176 | { |
267d2029 | 18177 | /* See if we have a Neon type suffix (possible in either unified or |
477330fc RM |
18178 | non-unified ARM syntax mode). */ |
18179 | if (parse_neon_type (&inst.vectype, str) == FAIL) | |
c921be7d | 18180 | return NULL; |
477330fc | 18181 | } |
5287ad62 | 18182 | else if (end[offset] != '\0' && end[offset] != ' ') |
477330fc | 18183 | return NULL; |
b99bd4ef | 18184 | } |
c19d1205 ZW |
18185 | else |
18186 | *str = end; | |
b99bd4ef | 18187 | |
c19d1205 | 18188 | /* Look for unaffixed or special-case affixed mnemonic. */ |
21d799b5 | 18189 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
477330fc | 18190 | end - base); |
c19d1205 | 18191 | if (opcode) |
b99bd4ef | 18192 | { |
c19d1205 ZW |
18193 | /* step U */ |
18194 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 18195 | { |
c19d1205 ZW |
18196 | inst.cond = COND_ALWAYS; |
18197 | return opcode; | |
b99bd4ef | 18198 | } |
b99bd4ef | 18199 | |
278df34e | 18200 | if (warn_on_deprecated && unified_syntax) |
5c3696f8 | 18201 | as_tsktsk (_("conditional infixes are deprecated in unified syntax")); |
c19d1205 | 18202 | affix = base + (opcode->tag - OT_odd_infix_0); |
21d799b5 | 18203 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
9c2799c2 | 18204 | gas_assert (cond); |
b99bd4ef | 18205 | |
c19d1205 ZW |
18206 | inst.cond = cond->value; |
18207 | return opcode; | |
18208 | } | |
b99bd4ef | 18209 | |
c19d1205 ZW |
18210 | /* Cannot have a conditional suffix on a mnemonic of less than two |
18211 | characters. */ | |
18212 | if (end - base < 3) | |
c921be7d | 18213 | return NULL; |
b99bd4ef | 18214 | |
c19d1205 ZW |
18215 | /* Look for suffixed mnemonic. */ |
18216 | affix = end - 2; | |
21d799b5 NC |
18217 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
18218 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, | |
477330fc | 18219 | affix - base); |
c19d1205 ZW |
18220 | if (opcode && cond) |
18221 | { | |
18222 | /* step CE */ | |
18223 | switch (opcode->tag) | |
18224 | { | |
e3cb604e PB |
18225 | case OT_cinfix3_legacy: |
18226 | /* Ignore conditional suffixes matched on infix only mnemonics. */ | |
18227 | break; | |
18228 | ||
c19d1205 | 18229 | case OT_cinfix3: |
088fa78e | 18230 | case OT_cinfix3_deprecated: |
c19d1205 ZW |
18231 | case OT_odd_infix_unc: |
18232 | if (!unified_syntax) | |
0198d5e6 | 18233 | return NULL; |
1a0670f3 | 18234 | /* Fall through. */ |
c19d1205 ZW |
18235 | |
18236 | case OT_csuffix: | |
477330fc | 18237 | case OT_csuffixF: |
c19d1205 ZW |
18238 | case OT_csuf_or_in3: |
18239 | inst.cond = cond->value; | |
18240 | return opcode; | |
18241 | ||
18242 | case OT_unconditional: | |
18243 | case OT_unconditionalF: | |
dfa9f0d5 | 18244 | if (thumb_mode) |
c921be7d | 18245 | inst.cond = cond->value; |
dfa9f0d5 PB |
18246 | else |
18247 | { | |
c921be7d | 18248 | /* Delayed diagnostic. */ |
dfa9f0d5 PB |
18249 | inst.error = BAD_COND; |
18250 | inst.cond = COND_ALWAYS; | |
18251 | } | |
c19d1205 | 18252 | return opcode; |
b99bd4ef | 18253 | |
c19d1205 | 18254 | default: |
c921be7d | 18255 | return NULL; |
c19d1205 ZW |
18256 | } |
18257 | } | |
b99bd4ef | 18258 | |
c19d1205 ZW |
18259 | /* Cannot have a usual-position infix on a mnemonic of less than |
18260 | six characters (five would be a suffix). */ | |
18261 | if (end - base < 6) | |
c921be7d | 18262 | return NULL; |
b99bd4ef | 18263 | |
c19d1205 ZW |
18264 | /* Look for infixed mnemonic in the usual position. */ |
18265 | affix = base + 3; | |
21d799b5 | 18266 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
e3cb604e | 18267 | if (!cond) |
c921be7d | 18268 | return NULL; |
e3cb604e PB |
18269 | |
18270 | memcpy (save, affix, 2); | |
18271 | memmove (affix, affix + 2, (end - affix) - 2); | |
21d799b5 | 18272 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
477330fc | 18273 | (end - base) - 2); |
e3cb604e PB |
18274 | memmove (affix + 2, affix, (end - affix) - 2); |
18275 | memcpy (affix, save, 2); | |
18276 | ||
088fa78e KH |
18277 | if (opcode |
18278 | && (opcode->tag == OT_cinfix3 | |
18279 | || opcode->tag == OT_cinfix3_deprecated | |
18280 | || opcode->tag == OT_csuf_or_in3 | |
18281 | || opcode->tag == OT_cinfix3_legacy)) | |
b99bd4ef | 18282 | { |
c921be7d | 18283 | /* Step CM. */ |
278df34e | 18284 | if (warn_on_deprecated && unified_syntax |
088fa78e KH |
18285 | && (opcode->tag == OT_cinfix3 |
18286 | || opcode->tag == OT_cinfix3_deprecated)) | |
5c3696f8 | 18287 | as_tsktsk (_("conditional infixes are deprecated in unified syntax")); |
c19d1205 ZW |
18288 | |
18289 | inst.cond = cond->value; | |
18290 | return opcode; | |
b99bd4ef NC |
18291 | } |
18292 | ||
c921be7d | 18293 | return NULL; |
b99bd4ef NC |
18294 | } |
18295 | ||
e07e6e58 NC |
18296 | /* This function generates an initial IT instruction, leaving its block |
18297 | virtually open for the new instructions. Eventually, | |
18298 | the mask will be updated by now_it_add_mask () each time | |
18299 | a new instruction needs to be included in the IT block. | |
18300 | Finally, the block is closed with close_automatic_it_block (). | |
18301 | The block closure can be requested either from md_assemble (), | |
18302 | a tencode (), or due to a label hook. */ | |
18303 | ||
18304 | static void | |
18305 | new_automatic_it_block (int cond) | |
18306 | { | |
18307 | now_it.state = AUTOMATIC_IT_BLOCK; | |
18308 | now_it.mask = 0x18; | |
18309 | now_it.cc = cond; | |
18310 | now_it.block_length = 1; | |
cd000bff | 18311 | mapping_state (MAP_THUMB); |
e07e6e58 | 18312 | now_it.insn = output_it_inst (cond, now_it.mask, NULL); |
5a01bb1d MGD |
18313 | now_it.warn_deprecated = FALSE; |
18314 | now_it.insn_cond = TRUE; | |
e07e6e58 NC |
18315 | } |
18316 | ||
18317 | /* Close an automatic IT block. | |
18318 | See comments in new_automatic_it_block (). */ | |
18319 | ||
18320 | static void | |
18321 | close_automatic_it_block (void) | |
18322 | { | |
18323 | now_it.mask = 0x10; | |
18324 | now_it.block_length = 0; | |
18325 | } | |
18326 | ||
18327 | /* Update the mask of the current automatically-generated IT | |
18328 | instruction. See comments in new_automatic_it_block (). */ | |
18329 | ||
18330 | static void | |
18331 | now_it_add_mask (int cond) | |
18332 | { | |
18333 | #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit))) | |
18334 | #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \ | |
477330fc | 18335 | | ((bitvalue) << (nbit))) |
e07e6e58 | 18336 | const int resulting_bit = (cond & 1); |
c921be7d | 18337 | |
e07e6e58 NC |
18338 | now_it.mask &= 0xf; |
18339 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
477330fc RM |
18340 | resulting_bit, |
18341 | (5 - now_it.block_length)); | |
e07e6e58 | 18342 | now_it.mask = SET_BIT_VALUE (now_it.mask, |
477330fc RM |
18343 | 1, |
18344 | ((5 - now_it.block_length) - 1) ); | |
e07e6e58 NC |
18345 | output_it_inst (now_it.cc, now_it.mask, now_it.insn); |
18346 | ||
18347 | #undef CLEAR_BIT | |
18348 | #undef SET_BIT_VALUE | |
e07e6e58 NC |
18349 | } |
18350 | ||
18351 | /* The IT blocks handling machinery is accessed through the these functions: | |
18352 | it_fsm_pre_encode () from md_assemble () | |
18353 | set_it_insn_type () optional, from the tencode functions | |
18354 | set_it_insn_type_last () ditto | |
18355 | in_it_block () ditto | |
18356 | it_fsm_post_encode () from md_assemble () | |
33eaf5de | 18357 | force_automatic_it_block_close () from label handling functions |
e07e6e58 NC |
18358 | |
18359 | Rationale: | |
18360 | 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), | |
477330fc RM |
18361 | initializing the IT insn type with a generic initial value depending |
18362 | on the inst.condition. | |
e07e6e58 | 18363 | 2) During the tencode function, two things may happen: |
477330fc RM |
18364 | a) The tencode function overrides the IT insn type by |
18365 | calling either set_it_insn_type (type) or set_it_insn_type_last (). | |
18366 | b) The tencode function queries the IT block state by | |
18367 | calling in_it_block () (i.e. to determine narrow/not narrow mode). | |
18368 | ||
18369 | Both set_it_insn_type and in_it_block run the internal FSM state | |
18370 | handling function (handle_it_state), because: a) setting the IT insn | |
18371 | type may incur in an invalid state (exiting the function), | |
18372 | and b) querying the state requires the FSM to be updated. | |
18373 | Specifically we want to avoid creating an IT block for conditional | |
18374 | branches, so it_fsm_pre_encode is actually a guess and we can't | |
18375 | determine whether an IT block is required until the tencode () routine | |
18376 | has decided what type of instruction this actually it. | |
18377 | Because of this, if set_it_insn_type and in_it_block have to be used, | |
18378 | set_it_insn_type has to be called first. | |
18379 | ||
18380 | set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that | |
18381 | determines the insn IT type depending on the inst.cond code. | |
18382 | When a tencode () routine encodes an instruction that can be | |
18383 | either outside an IT block, or, in the case of being inside, has to be | |
18384 | the last one, set_it_insn_type_last () will determine the proper | |
18385 | IT instruction type based on the inst.cond code. Otherwise, | |
18386 | set_it_insn_type can be called for overriding that logic or | |
18387 | for covering other cases. | |
18388 | ||
18389 | Calling handle_it_state () may not transition the IT block state to | |
2b0f3761 | 18390 | OUTSIDE_IT_BLOCK immediately, since the (current) state could be |
477330fc RM |
18391 | still queried. Instead, if the FSM determines that the state should |
18392 | be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed | |
18393 | after the tencode () function: that's what it_fsm_post_encode () does. | |
18394 | ||
18395 | Since in_it_block () calls the state handling function to get an | |
18396 | updated state, an error may occur (due to invalid insns combination). | |
18397 | In that case, inst.error is set. | |
18398 | Therefore, inst.error has to be checked after the execution of | |
18399 | the tencode () routine. | |
e07e6e58 NC |
18400 | |
18401 | 3) Back in md_assemble(), it_fsm_post_encode () is called to commit | |
477330fc RM |
18402 | any pending state change (if any) that didn't take place in |
18403 | handle_it_state () as explained above. */ | |
e07e6e58 NC |
18404 | |
18405 | static void | |
18406 | it_fsm_pre_encode (void) | |
18407 | { | |
18408 | if (inst.cond != COND_ALWAYS) | |
18409 | inst.it_insn_type = INSIDE_IT_INSN; | |
18410 | else | |
18411 | inst.it_insn_type = OUTSIDE_IT_INSN; | |
18412 | ||
18413 | now_it.state_handled = 0; | |
18414 | } | |
18415 | ||
18416 | /* IT state FSM handling function. */ | |
18417 | ||
18418 | static int | |
18419 | handle_it_state (void) | |
18420 | { | |
18421 | now_it.state_handled = 1; | |
5a01bb1d | 18422 | now_it.insn_cond = FALSE; |
e07e6e58 NC |
18423 | |
18424 | switch (now_it.state) | |
18425 | { | |
18426 | case OUTSIDE_IT_BLOCK: | |
18427 | switch (inst.it_insn_type) | |
18428 | { | |
18429 | case OUTSIDE_IT_INSN: | |
18430 | break; | |
18431 | ||
18432 | case INSIDE_IT_INSN: | |
18433 | case INSIDE_IT_LAST_INSN: | |
18434 | if (thumb_mode == 0) | |
18435 | { | |
c921be7d | 18436 | if (unified_syntax |
e07e6e58 NC |
18437 | && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM)) |
18438 | as_tsktsk (_("Warning: conditional outside an IT block"\ | |
18439 | " for Thumb.")); | |
18440 | } | |
18441 | else | |
18442 | { | |
18443 | if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB) | |
fc289b0a | 18444 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)) |
e07e6e58 NC |
18445 | { |
18446 | /* Automatically generate the IT instruction. */ | |
18447 | new_automatic_it_block (inst.cond); | |
18448 | if (inst.it_insn_type == INSIDE_IT_LAST_INSN) | |
18449 | close_automatic_it_block (); | |
18450 | } | |
18451 | else | |
18452 | { | |
18453 | inst.error = BAD_OUT_IT; | |
18454 | return FAIL; | |
18455 | } | |
18456 | } | |
18457 | break; | |
18458 | ||
18459 | case IF_INSIDE_IT_LAST_INSN: | |
18460 | case NEUTRAL_IT_INSN: | |
18461 | break; | |
18462 | ||
18463 | case IT_INSN: | |
18464 | now_it.state = MANUAL_IT_BLOCK; | |
18465 | now_it.block_length = 0; | |
18466 | break; | |
18467 | } | |
18468 | break; | |
18469 | ||
18470 | case AUTOMATIC_IT_BLOCK: | |
18471 | /* Three things may happen now: | |
18472 | a) We should increment current it block size; | |
18473 | b) We should close current it block (closing insn or 4 insns); | |
18474 | c) We should close current it block and start a new one (due | |
18475 | to incompatible conditions or | |
18476 | 4 insns-length block reached). */ | |
18477 | ||
18478 | switch (inst.it_insn_type) | |
18479 | { | |
18480 | case OUTSIDE_IT_INSN: | |
2b0f3761 | 18481 | /* The closure of the block shall happen immediately, |
e07e6e58 NC |
18482 | so any in_it_block () call reports the block as closed. */ |
18483 | force_automatic_it_block_close (); | |
18484 | break; | |
18485 | ||
18486 | case INSIDE_IT_INSN: | |
18487 | case INSIDE_IT_LAST_INSN: | |
18488 | case IF_INSIDE_IT_LAST_INSN: | |
18489 | now_it.block_length++; | |
18490 | ||
18491 | if (now_it.block_length > 4 | |
18492 | || !now_it_compatible (inst.cond)) | |
18493 | { | |
18494 | force_automatic_it_block_close (); | |
18495 | if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN) | |
18496 | new_automatic_it_block (inst.cond); | |
18497 | } | |
18498 | else | |
18499 | { | |
5a01bb1d | 18500 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
18501 | now_it_add_mask (inst.cond); |
18502 | } | |
18503 | ||
18504 | if (now_it.state == AUTOMATIC_IT_BLOCK | |
18505 | && (inst.it_insn_type == INSIDE_IT_LAST_INSN | |
18506 | || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN)) | |
18507 | close_automatic_it_block (); | |
18508 | break; | |
18509 | ||
18510 | case NEUTRAL_IT_INSN: | |
18511 | now_it.block_length++; | |
5a01bb1d | 18512 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
18513 | |
18514 | if (now_it.block_length > 4) | |
18515 | force_automatic_it_block_close (); | |
18516 | else | |
18517 | now_it_add_mask (now_it.cc & 1); | |
18518 | break; | |
18519 | ||
18520 | case IT_INSN: | |
18521 | close_automatic_it_block (); | |
18522 | now_it.state = MANUAL_IT_BLOCK; | |
18523 | break; | |
18524 | } | |
18525 | break; | |
18526 | ||
18527 | case MANUAL_IT_BLOCK: | |
18528 | { | |
18529 | /* Check conditional suffixes. */ | |
18530 | const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1; | |
18531 | int is_last; | |
18532 | now_it.mask <<= 1; | |
18533 | now_it.mask &= 0x1f; | |
18534 | is_last = (now_it.mask == 0x10); | |
5a01bb1d | 18535 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
18536 | |
18537 | switch (inst.it_insn_type) | |
18538 | { | |
18539 | case OUTSIDE_IT_INSN: | |
18540 | inst.error = BAD_NOT_IT; | |
18541 | return FAIL; | |
18542 | ||
18543 | case INSIDE_IT_INSN: | |
18544 | if (cond != inst.cond) | |
18545 | { | |
18546 | inst.error = BAD_IT_COND; | |
18547 | return FAIL; | |
18548 | } | |
18549 | break; | |
18550 | ||
18551 | case INSIDE_IT_LAST_INSN: | |
18552 | case IF_INSIDE_IT_LAST_INSN: | |
18553 | if (cond != inst.cond) | |
18554 | { | |
18555 | inst.error = BAD_IT_COND; | |
18556 | return FAIL; | |
18557 | } | |
18558 | if (!is_last) | |
18559 | { | |
18560 | inst.error = BAD_BRANCH; | |
18561 | return FAIL; | |
18562 | } | |
18563 | break; | |
18564 | ||
18565 | case NEUTRAL_IT_INSN: | |
18566 | /* The BKPT instruction is unconditional even in an IT block. */ | |
18567 | break; | |
18568 | ||
18569 | case IT_INSN: | |
18570 | inst.error = BAD_IT_IT; | |
18571 | return FAIL; | |
18572 | } | |
18573 | } | |
18574 | break; | |
18575 | } | |
18576 | ||
18577 | return SUCCESS; | |
18578 | } | |
18579 | ||
5a01bb1d MGD |
18580 | struct depr_insn_mask |
18581 | { | |
18582 | unsigned long pattern; | |
18583 | unsigned long mask; | |
18584 | const char* description; | |
18585 | }; | |
18586 | ||
18587 | /* List of 16-bit instruction patterns deprecated in an IT block in | |
18588 | ARMv8. */ | |
18589 | static const struct depr_insn_mask depr_it_insns[] = { | |
18590 | { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") }, | |
18591 | { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") }, | |
18592 | { 0xa000, 0xb800, N_("ADR") }, | |
18593 | { 0x4800, 0xf800, N_("Literal loads") }, | |
18594 | { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") }, | |
18595 | { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") }, | |
c8de034b JW |
18596 | /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue' |
18597 | field in asm_opcode. 'tvalue' is used at the stage this check happen. */ | |
18598 | { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") }, | |
5a01bb1d MGD |
18599 | { 0, 0, NULL } |
18600 | }; | |
18601 | ||
e07e6e58 NC |
18602 | static void |
18603 | it_fsm_post_encode (void) | |
18604 | { | |
18605 | int is_last; | |
18606 | ||
18607 | if (!now_it.state_handled) | |
18608 | handle_it_state (); | |
18609 | ||
5a01bb1d MGD |
18610 | if (now_it.insn_cond |
18611 | && !now_it.warn_deprecated | |
18612 | && warn_on_deprecated | |
df9909b8 TP |
18613 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8) |
18614 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m)) | |
5a01bb1d MGD |
18615 | { |
18616 | if (inst.instruction >= 0x10000) | |
18617 | { | |
5c3696f8 | 18618 | as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are " |
df9909b8 | 18619 | "performance deprecated in ARMv8-A and ARMv8-R")); |
5a01bb1d MGD |
18620 | now_it.warn_deprecated = TRUE; |
18621 | } | |
18622 | else | |
18623 | { | |
18624 | const struct depr_insn_mask *p = depr_it_insns; | |
18625 | ||
18626 | while (p->mask != 0) | |
18627 | { | |
18628 | if ((inst.instruction & p->mask) == p->pattern) | |
18629 | { | |
df9909b8 TP |
18630 | as_tsktsk (_("IT blocks containing 16-bit Thumb " |
18631 | "instructions of the following class are " | |
18632 | "performance deprecated in ARMv8-A and " | |
18633 | "ARMv8-R: %s"), p->description); | |
5a01bb1d MGD |
18634 | now_it.warn_deprecated = TRUE; |
18635 | break; | |
18636 | } | |
18637 | ||
18638 | ++p; | |
18639 | } | |
18640 | } | |
18641 | ||
18642 | if (now_it.block_length > 1) | |
18643 | { | |
5c3696f8 | 18644 | as_tsktsk (_("IT blocks containing more than one conditional " |
df9909b8 TP |
18645 | "instruction are performance deprecated in ARMv8-A and " |
18646 | "ARMv8-R")); | |
5a01bb1d MGD |
18647 | now_it.warn_deprecated = TRUE; |
18648 | } | |
18649 | } | |
18650 | ||
e07e6e58 NC |
18651 | is_last = (now_it.mask == 0x10); |
18652 | if (is_last) | |
18653 | { | |
18654 | now_it.state = OUTSIDE_IT_BLOCK; | |
18655 | now_it.mask = 0; | |
18656 | } | |
18657 | } | |
18658 | ||
18659 | static void | |
18660 | force_automatic_it_block_close (void) | |
18661 | { | |
18662 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
18663 | { | |
18664 | close_automatic_it_block (); | |
18665 | now_it.state = OUTSIDE_IT_BLOCK; | |
18666 | now_it.mask = 0; | |
18667 | } | |
18668 | } | |
18669 | ||
18670 | static int | |
18671 | in_it_block (void) | |
18672 | { | |
18673 | if (!now_it.state_handled) | |
18674 | handle_it_state (); | |
18675 | ||
18676 | return now_it.state != OUTSIDE_IT_BLOCK; | |
18677 | } | |
18678 | ||
ff8646ee TP |
18679 | /* Whether OPCODE only has T32 encoding. Since this function is only used by |
18680 | t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed | |
18681 | here, hence the "known" in the function name. */ | |
fc289b0a TP |
18682 | |
18683 | static bfd_boolean | |
ff8646ee | 18684 | known_t32_only_insn (const struct asm_opcode *opcode) |
fc289b0a TP |
18685 | { |
18686 | /* Original Thumb-1 wide instruction. */ | |
18687 | if (opcode->tencode == do_t_blx | |
18688 | || opcode->tencode == do_t_branch23 | |
18689 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) | |
18690 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)) | |
18691 | return TRUE; | |
18692 | ||
16a1fa25 TP |
18693 | /* Wide-only instruction added to ARMv8-M Baseline. */ |
18694 | if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m_m_only) | |
ff8646ee TP |
18695 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics) |
18696 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m) | |
18697 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div)) | |
18698 | return TRUE; | |
18699 | ||
18700 | return FALSE; | |
18701 | } | |
18702 | ||
18703 | /* Whether wide instruction variant can be used if available for a valid OPCODE | |
18704 | in ARCH. */ | |
18705 | ||
18706 | static bfd_boolean | |
18707 | t32_insn_ok (arm_feature_set arch, const struct asm_opcode *opcode) | |
18708 | { | |
18709 | if (known_t32_only_insn (opcode)) | |
18710 | return TRUE; | |
18711 | ||
18712 | /* Instruction with narrow and wide encoding added to ARMv8-M. Availability | |
18713 | of variant T3 of B.W is checked in do_t_branch. */ | |
18714 | if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m) | |
18715 | && opcode->tencode == do_t_branch) | |
18716 | return TRUE; | |
18717 | ||
bada4342 JW |
18718 | /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */ |
18719 | if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m) | |
18720 | && opcode->tencode == do_t_mov_cmp | |
18721 | /* Make sure CMP instruction is not affected. */ | |
18722 | && opcode->aencode == do_mov) | |
18723 | return TRUE; | |
18724 | ||
ff8646ee TP |
18725 | /* Wide instruction variants of all instructions with narrow *and* wide |
18726 | variants become available with ARMv6t2. Other opcodes are either | |
18727 | narrow-only or wide-only and are thus available if OPCODE is valid. */ | |
18728 | if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v6t2)) | |
18729 | return TRUE; | |
18730 | ||
18731 | /* OPCODE with narrow only instruction variant or wide variant not | |
18732 | available. */ | |
fc289b0a TP |
18733 | return FALSE; |
18734 | } | |
18735 | ||
c19d1205 ZW |
18736 | void |
18737 | md_assemble (char *str) | |
b99bd4ef | 18738 | { |
c19d1205 ZW |
18739 | char *p = str; |
18740 | const struct asm_opcode * opcode; | |
b99bd4ef | 18741 | |
c19d1205 ZW |
18742 | /* Align the previous label if needed. */ |
18743 | if (last_label_seen != NULL) | |
b99bd4ef | 18744 | { |
c19d1205 ZW |
18745 | symbol_set_frag (last_label_seen, frag_now); |
18746 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
18747 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
18748 | } |
18749 | ||
c19d1205 ZW |
18750 | memset (&inst, '\0', sizeof (inst)); |
18751 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 18752 | |
c19d1205 ZW |
18753 | opcode = opcode_lookup (&p); |
18754 | if (!opcode) | |
b99bd4ef | 18755 | { |
c19d1205 | 18756 | /* It wasn't an instruction, but it might be a register alias of |
dcbf9037 | 18757 | the form alias .req reg, or a Neon .dn/.qn directive. */ |
c921be7d | 18758 | if (! create_register_alias (str, p) |
477330fc | 18759 | && ! create_neon_reg_alias (str, p)) |
c19d1205 | 18760 | as_bad (_("bad instruction `%s'"), str); |
b99bd4ef | 18761 | |
b99bd4ef NC |
18762 | return; |
18763 | } | |
18764 | ||
278df34e | 18765 | if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated) |
5c3696f8 | 18766 | as_tsktsk (_("s suffix on comparison instruction is deprecated")); |
088fa78e | 18767 | |
037e8744 JB |
18768 | /* The value which unconditional instructions should have in place of the |
18769 | condition field. */ | |
18770 | inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; | |
18771 | ||
c19d1205 | 18772 | if (thumb_mode) |
b99bd4ef | 18773 | { |
e74cfd16 | 18774 | arm_feature_set variant; |
8f06b2d8 PB |
18775 | |
18776 | variant = cpu_variant; | |
18777 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
e74cfd16 PB |
18778 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
18779 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); | |
c19d1205 | 18780 | /* Check that this instruction is supported for this CPU. */ |
62b3e311 PB |
18781 | if (!opcode->tvariant |
18782 | || (thumb_mode == 1 | |
18783 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) | |
b99bd4ef | 18784 | { |
173205ca TP |
18785 | if (opcode->tencode == do_t_swi) |
18786 | as_bad (_("SVC is not permitted on this architecture")); | |
18787 | else | |
18788 | as_bad (_("selected processor does not support `%s' in Thumb mode"), str); | |
b99bd4ef NC |
18789 | return; |
18790 | } | |
c19d1205 ZW |
18791 | if (inst.cond != COND_ALWAYS && !unified_syntax |
18792 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 18793 | { |
c19d1205 | 18794 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
18795 | return; |
18796 | } | |
18797 | ||
fc289b0a TP |
18798 | /* Two things are addressed here: |
18799 | 1) Implicit require narrow instructions on Thumb-1. | |
18800 | This avoids relaxation accidentally introducing Thumb-2 | |
18801 | instructions. | |
18802 | 2) Reject wide instructions in non Thumb-2 cores. | |
18803 | ||
18804 | Only instructions with narrow and wide variants need to be handled | |
18805 | but selecting all non wide-only instructions is easier. */ | |
18806 | if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) | |
ff8646ee | 18807 | && !t32_insn_ok (variant, opcode)) |
076d447c | 18808 | { |
fc289b0a TP |
18809 | if (inst.size_req == 0) |
18810 | inst.size_req = 2; | |
18811 | else if (inst.size_req == 4) | |
752d5da4 | 18812 | { |
ff8646ee TP |
18813 | if (ARM_CPU_HAS_FEATURE (variant, arm_ext_v8m)) |
18814 | as_bad (_("selected processor does not support 32bit wide " | |
18815 | "variant of instruction `%s'"), str); | |
18816 | else | |
18817 | as_bad (_("selected processor does not support `%s' in " | |
18818 | "Thumb-2 mode"), str); | |
fc289b0a | 18819 | return; |
752d5da4 | 18820 | } |
076d447c PB |
18821 | } |
18822 | ||
c19d1205 ZW |
18823 | inst.instruction = opcode->tvalue; |
18824 | ||
5be8be5d | 18825 | if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE)) |
477330fc RM |
18826 | { |
18827 | /* Prepare the it_insn_type for those encodings that don't set | |
18828 | it. */ | |
18829 | it_fsm_pre_encode (); | |
c19d1205 | 18830 | |
477330fc | 18831 | opcode->tencode (); |
e07e6e58 | 18832 | |
477330fc RM |
18833 | it_fsm_post_encode (); |
18834 | } | |
e27ec89e | 18835 | |
0110f2b8 | 18836 | if (!(inst.error || inst.relax)) |
b99bd4ef | 18837 | { |
9c2799c2 | 18838 | gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
c19d1205 ZW |
18839 | inst.size = (inst.instruction > 0xffff ? 4 : 2); |
18840 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 18841 | { |
c19d1205 | 18842 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
18843 | return; |
18844 | } | |
18845 | } | |
076d447c PB |
18846 | |
18847 | /* Something has gone badly wrong if we try to relax a fixed size | |
477330fc | 18848 | instruction. */ |
9c2799c2 | 18849 | gas_assert (inst.size_req == 0 || !inst.relax); |
076d447c | 18850 | |
e74cfd16 PB |
18851 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
18852 | *opcode->tvariant); | |
ee065d83 | 18853 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
fc289b0a TP |
18854 | set those bits when Thumb-2 32-bit instructions are seen. The impact |
18855 | of relaxable instructions will be considered later after we finish all | |
18856 | relaxation. */ | |
ff8646ee TP |
18857 | if (ARM_FEATURE_CORE_EQUAL (cpu_variant, arm_arch_any)) |
18858 | variant = arm_arch_none; | |
18859 | else | |
18860 | variant = cpu_variant; | |
18861 | if (inst.size == 4 && !t32_insn_ok (variant, opcode)) | |
e74cfd16 PB |
18862 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
18863 | arm_ext_v6t2); | |
cd000bff | 18864 | |
88714cb8 DG |
18865 | check_neon_suffixes; |
18866 | ||
cd000bff | 18867 | if (!inst.error) |
c877a2f2 NC |
18868 | { |
18869 | mapping_state (MAP_THUMB); | |
18870 | } | |
c19d1205 | 18871 | } |
3e9e4fcf | 18872 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 | 18873 | { |
845b51d6 PB |
18874 | bfd_boolean is_bx; |
18875 | ||
18876 | /* bx is allowed on v5 cores, and sometimes on v4 cores. */ | |
18877 | is_bx = (opcode->aencode == do_bx); | |
18878 | ||
c19d1205 | 18879 | /* Check that this instruction is supported for this CPU. */ |
845b51d6 PB |
18880 | if (!(is_bx && fix_v4bx) |
18881 | && !(opcode->avariant && | |
18882 | ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))) | |
b99bd4ef | 18883 | { |
84b52b66 | 18884 | as_bad (_("selected processor does not support `%s' in ARM mode"), str); |
c19d1205 | 18885 | return; |
b99bd4ef | 18886 | } |
c19d1205 | 18887 | if (inst.size_req) |
b99bd4ef | 18888 | { |
c19d1205 ZW |
18889 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
18890 | return; | |
b99bd4ef NC |
18891 | } |
18892 | ||
c19d1205 ZW |
18893 | inst.instruction = opcode->avalue; |
18894 | if (opcode->tag == OT_unconditionalF) | |
eff0bc54 | 18895 | inst.instruction |= 0xFU << 28; |
c19d1205 ZW |
18896 | else |
18897 | inst.instruction |= inst.cond << 28; | |
18898 | inst.size = INSN_SIZE; | |
5be8be5d | 18899 | if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE)) |
477330fc RM |
18900 | { |
18901 | it_fsm_pre_encode (); | |
18902 | opcode->aencode (); | |
18903 | it_fsm_post_encode (); | |
18904 | } | |
ee065d83 | 18905 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
477330fc | 18906 | on a hypothetical non-thumb v5 core. */ |
845b51d6 | 18907 | if (is_bx) |
e74cfd16 | 18908 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); |
ee065d83 | 18909 | else |
e74cfd16 PB |
18910 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
18911 | *opcode->avariant); | |
88714cb8 DG |
18912 | |
18913 | check_neon_suffixes; | |
18914 | ||
cd000bff | 18915 | if (!inst.error) |
c877a2f2 NC |
18916 | { |
18917 | mapping_state (MAP_ARM); | |
18918 | } | |
b99bd4ef | 18919 | } |
3e9e4fcf JB |
18920 | else |
18921 | { | |
18922 | as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " | |
18923 | "-- `%s'"), str); | |
18924 | return; | |
18925 | } | |
c19d1205 ZW |
18926 | output_inst (str); |
18927 | } | |
b99bd4ef | 18928 | |
e07e6e58 NC |
18929 | static void |
18930 | check_it_blocks_finished (void) | |
18931 | { | |
18932 | #ifdef OBJ_ELF | |
18933 | asection *sect; | |
18934 | ||
18935 | for (sect = stdoutput->sections; sect != NULL; sect = sect->next) | |
18936 | if (seg_info (sect)->tc_segment_info_data.current_it.state | |
18937 | == MANUAL_IT_BLOCK) | |
18938 | { | |
18939 | as_warn (_("section '%s' finished with an open IT block."), | |
18940 | sect->name); | |
18941 | } | |
18942 | #else | |
18943 | if (now_it.state == MANUAL_IT_BLOCK) | |
18944 | as_warn (_("file finished with an open IT block.")); | |
18945 | #endif | |
18946 | } | |
18947 | ||
c19d1205 ZW |
18948 | /* Various frobbings of labels and their addresses. */ |
18949 | ||
18950 | void | |
18951 | arm_start_line_hook (void) | |
18952 | { | |
18953 | last_label_seen = NULL; | |
b99bd4ef NC |
18954 | } |
18955 | ||
c19d1205 ZW |
18956 | void |
18957 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 18958 | { |
c19d1205 | 18959 | last_label_seen = sym; |
b99bd4ef | 18960 | |
c19d1205 | 18961 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 18962 | |
c19d1205 ZW |
18963 | #if defined OBJ_COFF || defined OBJ_ELF |
18964 | ARM_SET_INTERWORK (sym, support_interwork); | |
18965 | #endif | |
b99bd4ef | 18966 | |
e07e6e58 NC |
18967 | force_automatic_it_block_close (); |
18968 | ||
5f4273c7 | 18969 | /* Note - do not allow local symbols (.Lxxx) to be labelled |
c19d1205 ZW |
18970 | as Thumb functions. This is because these labels, whilst |
18971 | they exist inside Thumb code, are not the entry points for | |
18972 | possible ARM->Thumb calls. Also, these labels can be used | |
18973 | as part of a computed goto or switch statement. eg gcc | |
18974 | can generate code that looks like this: | |
b99bd4ef | 18975 | |
c19d1205 ZW |
18976 | ldr r2, [pc, .Laaa] |
18977 | lsl r3, r3, #2 | |
18978 | ldr r2, [r3, r2] | |
18979 | mov pc, r2 | |
b99bd4ef | 18980 | |
c19d1205 ZW |
18981 | .Lbbb: .word .Lxxx |
18982 | .Lccc: .word .Lyyy | |
18983 | ..etc... | |
18984 | .Laaa: .word Lbbb | |
b99bd4ef | 18985 | |
c19d1205 ZW |
18986 | The first instruction loads the address of the jump table. |
18987 | The second instruction converts a table index into a byte offset. | |
18988 | The third instruction gets the jump address out of the table. | |
18989 | The fourth instruction performs the jump. | |
b99bd4ef | 18990 | |
c19d1205 ZW |
18991 | If the address stored at .Laaa is that of a symbol which has the |
18992 | Thumb_Func bit set, then the linker will arrange for this address | |
18993 | to have the bottom bit set, which in turn would mean that the | |
18994 | address computation performed by the third instruction would end | |
18995 | up with the bottom bit set. Since the ARM is capable of unaligned | |
18996 | word loads, the instruction would then load the incorrect address | |
18997 | out of the jump table, and chaos would ensue. */ | |
18998 | if (label_is_thumb_function_name | |
18999 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
19000 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 19001 | { |
c19d1205 ZW |
19002 | /* When the address of a Thumb function is taken the bottom |
19003 | bit of that address should be set. This will allow | |
19004 | interworking between Arm and Thumb functions to work | |
19005 | correctly. */ | |
b99bd4ef | 19006 | |
c19d1205 | 19007 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 19008 | |
c19d1205 | 19009 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 19010 | } |
07a53e5c | 19011 | |
07a53e5c | 19012 | dwarf2_emit_label (sym); |
b99bd4ef NC |
19013 | } |
19014 | ||
c921be7d | 19015 | bfd_boolean |
c19d1205 | 19016 | arm_data_in_code (void) |
b99bd4ef | 19017 | { |
c19d1205 | 19018 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 19019 | { |
c19d1205 ZW |
19020 | *input_line_pointer = '/'; |
19021 | input_line_pointer += 5; | |
19022 | *input_line_pointer = 0; | |
c921be7d | 19023 | return TRUE; |
b99bd4ef NC |
19024 | } |
19025 | ||
c921be7d | 19026 | return FALSE; |
b99bd4ef NC |
19027 | } |
19028 | ||
c19d1205 ZW |
19029 | char * |
19030 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 19031 | { |
c19d1205 | 19032 | int len; |
b99bd4ef | 19033 | |
c19d1205 ZW |
19034 | if (thumb_mode && (len = strlen (name)) > 5 |
19035 | && streq (name + len - 5, "/data")) | |
19036 | *(name + len - 5) = 0; | |
b99bd4ef | 19037 | |
c19d1205 | 19038 | return name; |
b99bd4ef | 19039 | } |
c19d1205 ZW |
19040 | \f |
19041 | /* Table of all register names defined by default. The user can | |
19042 | define additional names with .req. Note that all register names | |
19043 | should appear in both upper and lowercase variants. Some registers | |
19044 | also have mixed-case names. */ | |
b99bd4ef | 19045 | |
dcbf9037 | 19046 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } |
c19d1205 | 19047 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) |
5287ad62 | 19048 | #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) |
c19d1205 ZW |
19049 | #define REGSET(p,t) \ |
19050 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
19051 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
19052 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
19053 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
5287ad62 JB |
19054 | #define REGSETH(p,t) \ |
19055 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ | |
19056 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ | |
19057 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ | |
19058 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) | |
19059 | #define REGSET2(p,t) \ | |
19060 | REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ | |
19061 | REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ | |
19062 | REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ | |
19063 | REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) | |
90ec0d68 MGD |
19064 | #define SPLRBANK(base,bank,t) \ |
19065 | REGDEF(lr_##bank, 768|((base+0)<<16), t), \ | |
19066 | REGDEF(sp_##bank, 768|((base+1)<<16), t), \ | |
19067 | REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \ | |
19068 | REGDEF(LR_##bank, 768|((base+0)<<16), t), \ | |
19069 | REGDEF(SP_##bank, 768|((base+1)<<16), t), \ | |
19070 | REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t) | |
7ed4c4c5 | 19071 | |
c19d1205 | 19072 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 19073 | { |
c19d1205 ZW |
19074 | /* ARM integer registers. */ |
19075 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 19076 | |
c19d1205 ZW |
19077 | /* ATPCS synonyms. */ |
19078 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
19079 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
19080 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 19081 | |
c19d1205 ZW |
19082 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
19083 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
19084 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 19085 | |
c19d1205 ZW |
19086 | /* Well-known aliases. */ |
19087 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
19088 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
19089 | ||
19090 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
19091 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
19092 | ||
19093 | /* Coprocessor numbers. */ | |
19094 | REGSET(p, CP), REGSET(P, CP), | |
19095 | ||
19096 | /* Coprocessor register numbers. The "cr" variants are for backward | |
19097 | compatibility. */ | |
19098 | REGSET(c, CN), REGSET(C, CN), | |
19099 | REGSET(cr, CN), REGSET(CR, CN), | |
19100 | ||
90ec0d68 MGD |
19101 | /* ARM banked registers. */ |
19102 | REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB), | |
19103 | REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB), | |
19104 | REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB), | |
19105 | REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB), | |
19106 | REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB), | |
19107 | REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB), | |
19108 | REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB), | |
19109 | ||
19110 | REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB), | |
19111 | REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB), | |
19112 | REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB), | |
19113 | REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB), | |
19114 | REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB), | |
1472d06f | 19115 | REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB), |
90ec0d68 MGD |
19116 | REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB), |
19117 | REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB), | |
19118 | ||
19119 | SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB), | |
19120 | SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB), | |
19121 | SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB), | |
19122 | SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB), | |
19123 | SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB), | |
19124 | REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB), | |
19125 | REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB), | |
fa94de6b | 19126 | REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB), |
90ec0d68 MGD |
19127 | REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB), |
19128 | ||
c19d1205 ZW |
19129 | /* FPA registers. */ |
19130 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
19131 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
19132 | ||
19133 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
19134 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
19135 | ||
19136 | /* VFP SP registers. */ | |
5287ad62 JB |
19137 | REGSET(s,VFS), REGSET(S,VFS), |
19138 | REGSETH(s,VFS), REGSETH(S,VFS), | |
c19d1205 ZW |
19139 | |
19140 | /* VFP DP Registers. */ | |
5287ad62 JB |
19141 | REGSET(d,VFD), REGSET(D,VFD), |
19142 | /* Extra Neon DP registers. */ | |
19143 | REGSETH(d,VFD), REGSETH(D,VFD), | |
19144 | ||
19145 | /* Neon QP registers. */ | |
19146 | REGSET2(q,NQ), REGSET2(Q,NQ), | |
c19d1205 ZW |
19147 | |
19148 | /* VFP control registers. */ | |
19149 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
19150 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
cd2cf30b PB |
19151 | REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), |
19152 | REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), | |
19153 | REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), | |
19154 | REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), | |
40c7d507 | 19155 | REGDEF(mvfr2,5,VFC), REGDEF(MVFR2,5,VFC), |
c19d1205 ZW |
19156 | |
19157 | /* Maverick DSP coprocessor registers. */ | |
19158 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
19159 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
19160 | ||
19161 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
19162 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
19163 | REGDEF(dspsc,0,DSPSC), | |
19164 | ||
19165 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
19166 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
19167 | REGDEF(DSPSC,0,DSPSC), | |
19168 | ||
19169 | /* iWMMXt data registers - p0, c0-15. */ | |
19170 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
19171 | ||
19172 | /* iWMMXt control registers - p1, c0-3. */ | |
19173 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
19174 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
19175 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
19176 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
19177 | ||
19178 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
19179 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
19180 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
19181 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
19182 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
19183 | ||
19184 | /* XScale accumulator registers. */ | |
19185 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
19186 | }; | |
19187 | #undef REGDEF | |
19188 | #undef REGNUM | |
19189 | #undef REGSET | |
7ed4c4c5 | 19190 | |
c19d1205 ZW |
19191 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
19192 | within psr_required_here. */ | |
19193 | static const struct asm_psr psrs[] = | |
19194 | { | |
19195 | /* Backward compatibility notation. Note that "all" is no longer | |
19196 | truly all possible PSR bits. */ | |
19197 | {"all", PSR_c | PSR_f}, | |
19198 | {"flg", PSR_f}, | |
19199 | {"ctl", PSR_c}, | |
19200 | ||
19201 | /* Individual flags. */ | |
19202 | {"f", PSR_f}, | |
19203 | {"c", PSR_c}, | |
19204 | {"x", PSR_x}, | |
19205 | {"s", PSR_s}, | |
59b42a0d | 19206 | |
c19d1205 ZW |
19207 | /* Combinations of flags. */ |
19208 | {"fs", PSR_f | PSR_s}, | |
19209 | {"fx", PSR_f | PSR_x}, | |
19210 | {"fc", PSR_f | PSR_c}, | |
19211 | {"sf", PSR_s | PSR_f}, | |
19212 | {"sx", PSR_s | PSR_x}, | |
19213 | {"sc", PSR_s | PSR_c}, | |
19214 | {"xf", PSR_x | PSR_f}, | |
19215 | {"xs", PSR_x | PSR_s}, | |
19216 | {"xc", PSR_x | PSR_c}, | |
19217 | {"cf", PSR_c | PSR_f}, | |
19218 | {"cs", PSR_c | PSR_s}, | |
19219 | {"cx", PSR_c | PSR_x}, | |
19220 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
19221 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
19222 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
19223 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
19224 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
19225 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
19226 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
19227 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
19228 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
19229 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
19230 | {"scf", PSR_s | PSR_c | PSR_f}, | |
19231 | {"scx", PSR_s | PSR_c | PSR_x}, | |
19232 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
19233 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
19234 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
19235 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
19236 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
19237 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
19238 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
19239 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
19240 | {"csf", PSR_c | PSR_s | PSR_f}, | |
19241 | {"csx", PSR_c | PSR_s | PSR_x}, | |
19242 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
19243 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
19244 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
19245 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
19246 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
19247 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
19248 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
19249 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
19250 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
19251 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
19252 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
19253 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
19254 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
19255 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
19256 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
19257 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
19258 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
19259 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
19260 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
19261 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
19262 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
19263 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
19264 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
19265 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
19266 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
19267 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
19268 | }; | |
19269 | ||
62b3e311 PB |
19270 | /* Table of V7M psr names. */ |
19271 | static const struct asm_psr v7m_psrs[] = | |
19272 | { | |
1a336194 TP |
19273 | {"apsr", 0x0 }, {"APSR", 0x0 }, |
19274 | {"iapsr", 0x1 }, {"IAPSR", 0x1 }, | |
19275 | {"eapsr", 0x2 }, {"EAPSR", 0x2 }, | |
19276 | {"psr", 0x3 }, {"PSR", 0x3 }, | |
19277 | {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 }, | |
19278 | {"ipsr", 0x5 }, {"IPSR", 0x5 }, | |
19279 | {"epsr", 0x6 }, {"EPSR", 0x6 }, | |
19280 | {"iepsr", 0x7 }, {"IEPSR", 0x7 }, | |
19281 | {"msp", 0x8 }, {"MSP", 0x8 }, | |
19282 | {"psp", 0x9 }, {"PSP", 0x9 }, | |
19283 | {"msplim", 0xa }, {"MSPLIM", 0xa }, | |
19284 | {"psplim", 0xb }, {"PSPLIM", 0xb }, | |
19285 | {"primask", 0x10}, {"PRIMASK", 0x10}, | |
19286 | {"basepri", 0x11}, {"BASEPRI", 0x11}, | |
19287 | {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12}, | |
1a336194 TP |
19288 | {"faultmask", 0x13}, {"FAULTMASK", 0x13}, |
19289 | {"control", 0x14}, {"CONTROL", 0x14}, | |
19290 | {"msp_ns", 0x88}, {"MSP_NS", 0x88}, | |
19291 | {"psp_ns", 0x89}, {"PSP_NS", 0x89}, | |
19292 | {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a}, | |
19293 | {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b}, | |
19294 | {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90}, | |
19295 | {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91}, | |
19296 | {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93}, | |
19297 | {"control_ns", 0x94}, {"CONTROL_NS", 0x94}, | |
19298 | {"sp_ns", 0x98}, {"SP_NS", 0x98 } | |
62b3e311 PB |
19299 | }; |
19300 | ||
c19d1205 ZW |
19301 | /* Table of all shift-in-operand names. */ |
19302 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 19303 | { |
c19d1205 ZW |
19304 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
19305 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
19306 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
19307 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
19308 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
19309 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } | |
19310 | }; | |
b99bd4ef | 19311 | |
c19d1205 ZW |
19312 | /* Table of all explicit relocation names. */ |
19313 | #ifdef OBJ_ELF | |
19314 | static struct reloc_entry reloc_names[] = | |
19315 | { | |
19316 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
19317 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
19318 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
19319 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
19320 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
19321 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
19322 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
19323 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
19324 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
19325 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
b43420e6 | 19326 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}, |
0855e32b NS |
19327 | { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL}, |
19328 | { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC}, | |
477330fc | 19329 | { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC}, |
0855e32b | 19330 | { "tlscall", BFD_RELOC_ARM_TLS_CALL}, |
477330fc | 19331 | { "TLSCALL", BFD_RELOC_ARM_TLS_CALL}, |
0855e32b | 19332 | { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ}, |
188fd7ae CL |
19333 | { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}, |
19334 | { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC }, | |
19335 | { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC }, | |
19336 | { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC }, | |
19337 | { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC }, | |
19338 | { "funcdesc", BFD_RELOC_ARM_FUNCDESC }, | |
5c5a4843 CL |
19339 | { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC }, |
19340 | { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC }, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC }, | |
19341 | { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC }, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC }, | |
19342 | { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC }, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC }, | |
c19d1205 ZW |
19343 | }; |
19344 | #endif | |
b99bd4ef | 19345 | |
c19d1205 ZW |
19346 | /* Table of all conditional affixes. 0xF is not defined as a condition code. */ |
19347 | static const struct asm_cond conds[] = | |
19348 | { | |
19349 | {"eq", 0x0}, | |
19350 | {"ne", 0x1}, | |
19351 | {"cs", 0x2}, {"hs", 0x2}, | |
19352 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
19353 | {"mi", 0x4}, | |
19354 | {"pl", 0x5}, | |
19355 | {"vs", 0x6}, | |
19356 | {"vc", 0x7}, | |
19357 | {"hi", 0x8}, | |
19358 | {"ls", 0x9}, | |
19359 | {"ge", 0xa}, | |
19360 | {"lt", 0xb}, | |
19361 | {"gt", 0xc}, | |
19362 | {"le", 0xd}, | |
19363 | {"al", 0xe} | |
19364 | }; | |
bfae80f2 | 19365 | |
e797f7e0 | 19366 | #define UL_BARRIER(L,U,CODE,FEAT) \ |
823d2571 TG |
19367 | { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \ |
19368 | { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) } | |
e797f7e0 | 19369 | |
62b3e311 PB |
19370 | static struct asm_barrier_opt barrier_opt_names[] = |
19371 | { | |
e797f7e0 MGD |
19372 | UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER), |
19373 | UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER), | |
19374 | UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8), | |
19375 | UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER), | |
19376 | UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER), | |
19377 | UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER), | |
19378 | UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER), | |
19379 | UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8), | |
19380 | UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER), | |
19381 | UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER), | |
19382 | UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER), | |
19383 | UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER), | |
19384 | UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8), | |
19385 | UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER), | |
19386 | UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER), | |
19387 | UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8) | |
62b3e311 PB |
19388 | }; |
19389 | ||
e797f7e0 MGD |
19390 | #undef UL_BARRIER |
19391 | ||
c19d1205 ZW |
19392 | /* Table of ARM-format instructions. */ |
19393 | ||
19394 | /* Macros for gluing together operand strings. N.B. In all cases | |
19395 | other than OPS0, the trailing OP_stop comes from default | |
19396 | zero-initialization of the unspecified elements of the array. */ | |
19397 | #define OPS0() { OP_stop, } | |
19398 | #define OPS1(a) { OP_##a, } | |
19399 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
19400 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
19401 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
19402 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
19403 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
19404 | ||
5be8be5d DG |
19405 | /* These macros are similar to the OPSn, but do not prepend the OP_ prefix. |
19406 | This is useful when mixing operands for ARM and THUMB, i.e. using the | |
19407 | MIX_ARM_THUMB_OPERANDS macro. | |
19408 | In order to use these macros, prefix the number of operands with _ | |
19409 | e.g. _3. */ | |
19410 | #define OPS_1(a) { a, } | |
19411 | #define OPS_2(a,b) { a,b, } | |
19412 | #define OPS_3(a,b,c) { a,b,c, } | |
19413 | #define OPS_4(a,b,c,d) { a,b,c,d, } | |
19414 | #define OPS_5(a,b,c,d,e) { a,b,c,d,e, } | |
19415 | #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, } | |
19416 | ||
c19d1205 ZW |
19417 | /* These macros abstract out the exact format of the mnemonic table and |
19418 | save some repeated characters. */ | |
19419 | ||
19420 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
19421 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 19422 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 19423 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
19424 | |
19425 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
19426 | a T_MNEM_xyz enumerator. */ | |
19427 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
e07e6e58 | 19428 | TxCE (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 19429 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 19430 | TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
19431 | |
19432 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
19433 | infix after the third character. */ | |
19434 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 19435 | { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 19436 | THUMB_VARIANT, do_##ae, do_##te } |
088fa78e | 19437 | #define TxC3w(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 19438 | { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ |
088fa78e | 19439 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 | 19440 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 19441 | TxC3 (mnem, aop, 0x##top, nops, ops, ae, te) |
088fa78e | 19442 | #define TC3w(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 19443 | TxC3w (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 19444 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 19445 | TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
088fa78e | 19446 | #define tC3w(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 19447 | TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 | 19448 | |
c19d1205 | 19449 | /* Mnemonic that cannot be conditionalized. The ARM condition-code |
dfa9f0d5 PB |
19450 | field is still 0xE. Many of the Thumb variants can be executed |
19451 | conditionally, so this is checked separately. */ | |
c19d1205 | 19452 | #define TUE(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 19453 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 19454 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 | 19455 | |
dd5181d5 KT |
19456 | /* Same as TUE but the encoding function for ARM and Thumb modes is the same. |
19457 | Used by mnemonics that have very minimal differences in the encoding for | |
19458 | ARM and Thumb variants and can be handled in a common function. */ | |
19459 | #define TUEc(mnem, op, top, nops, ops, en) \ | |
19460 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ | |
19461 | THUMB_VARIANT, do_##en, do_##en } | |
19462 | ||
c19d1205 ZW |
19463 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM |
19464 | condition code field. */ | |
19465 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 19466 | { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 19467 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
19468 | |
19469 | /* ARM-only variants of all the above. */ | |
6a86118a | 19470 | #define CE(mnem, op, nops, ops, ae) \ |
21d799b5 | 19471 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
6a86118a NC |
19472 | |
19473 | #define C3(mnem, op, nops, ops, ae) \ | |
19474 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
19475 | ||
cf3cf39d TP |
19476 | /* Thumb-only variants of TCE and TUE. */ |
19477 | #define ToC(mnem, top, nops, ops, te) \ | |
19478 | { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \ | |
19479 | do_##te } | |
cf3cf39d TP |
19480 | |
19481 | #define ToU(mnem, top, nops, ops, te) \ | |
19482 | { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \ | |
19483 | NULL, do_##te } | |
cf3cf39d | 19484 | |
e3cb604e PB |
19485 | /* Legacy mnemonics that always have conditional infix after the third |
19486 | character. */ | |
19487 | #define CL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 19488 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
19489 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
19490 | ||
8f06b2d8 PB |
19491 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
19492 | #define cCE(mnem, op, nops, ops, ae) \ | |
21d799b5 | 19493 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 19494 | |
e3cb604e PB |
19495 | /* Legacy coprocessor instructions where conditional infix and conditional |
19496 | suffix are ambiguous. For consistency this includes all FPA instructions, | |
19497 | not just the potentially ambiguous ones. */ | |
19498 | #define cCL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 19499 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
19500 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
19501 | ||
19502 | /* Coprocessor, takes either a suffix or a position-3 infix | |
19503 | (for an FPA corner case). */ | |
19504 | #define C3E(mnem, op, nops, ops, ae) \ | |
21d799b5 | 19505 | { mnem, OPS##nops ops, OT_csuf_or_in3, \ |
e3cb604e | 19506 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 19507 | |
6a86118a | 19508 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
21d799b5 NC |
19509 | { m1 #m2 m3, OPS##nops ops, \ |
19510 | sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ | |
6a86118a NC |
19511 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
19512 | ||
19513 | #define CM(m1, m2, op, nops, ops, ae) \ | |
e07e6e58 NC |
19514 | xCM_ (m1, , m2, op, nops, ops, ae), \ |
19515 | xCM_ (m1, eq, m2, op, nops, ops, ae), \ | |
19516 | xCM_ (m1, ne, m2, op, nops, ops, ae), \ | |
19517 | xCM_ (m1, cs, m2, op, nops, ops, ae), \ | |
19518 | xCM_ (m1, hs, m2, op, nops, ops, ae), \ | |
19519 | xCM_ (m1, cc, m2, op, nops, ops, ae), \ | |
19520 | xCM_ (m1, ul, m2, op, nops, ops, ae), \ | |
19521 | xCM_ (m1, lo, m2, op, nops, ops, ae), \ | |
19522 | xCM_ (m1, mi, m2, op, nops, ops, ae), \ | |
19523 | xCM_ (m1, pl, m2, op, nops, ops, ae), \ | |
19524 | xCM_ (m1, vs, m2, op, nops, ops, ae), \ | |
19525 | xCM_ (m1, vc, m2, op, nops, ops, ae), \ | |
19526 | xCM_ (m1, hi, m2, op, nops, ops, ae), \ | |
19527 | xCM_ (m1, ls, m2, op, nops, ops, ae), \ | |
19528 | xCM_ (m1, ge, m2, op, nops, ops, ae), \ | |
19529 | xCM_ (m1, lt, m2, op, nops, ops, ae), \ | |
19530 | xCM_ (m1, gt, m2, op, nops, ops, ae), \ | |
19531 | xCM_ (m1, le, m2, op, nops, ops, ae), \ | |
19532 | xCM_ (m1, al, m2, op, nops, ops, ae) | |
6a86118a NC |
19533 | |
19534 | #define UE(mnem, op, nops, ops, ae) \ | |
19535 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
19536 | ||
19537 | #define UF(mnem, op, nops, ops, ae) \ | |
19538 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
19539 | ||
5287ad62 JB |
19540 | /* Neon data-processing. ARM versions are unconditional with cond=0xf. |
19541 | The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we | |
19542 | use the same encoding function for each. */ | |
19543 | #define NUF(mnem, op, nops, ops, enc) \ | |
19544 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ | |
19545 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } | |
19546 | ||
19547 | /* Neon data processing, version which indirects through neon_enc_tab for | |
19548 | the various overloaded versions of opcodes. */ | |
19549 | #define nUF(mnem, op, nops, ops, enc) \ | |
21d799b5 | 19550 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
19551 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
19552 | ||
19553 | /* Neon insn with conditional suffix for the ARM version, non-overloaded | |
19554 | version. */ | |
037e8744 JB |
19555 | #define NCE_tag(mnem, op, nops, ops, enc, tag) \ |
19556 | { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ | |
5287ad62 JB |
19557 | THUMB_VARIANT, do_##enc, do_##enc } |
19558 | ||
037e8744 | 19559 | #define NCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 19560 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
19561 | |
19562 | #define NCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 19563 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 19564 | |
5287ad62 | 19565 | /* Neon insn with conditional suffix for the ARM version, overloaded types. */ |
037e8744 | 19566 | #define nCE_tag(mnem, op, nops, ops, enc, tag) \ |
21d799b5 | 19567 | { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
19568 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
19569 | ||
037e8744 | 19570 | #define nCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 19571 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
19572 | |
19573 | #define nCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 19574 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 19575 | |
c19d1205 ZW |
19576 | #define do_0 0 |
19577 | ||
c19d1205 | 19578 | static const struct asm_opcode insns[] = |
bfae80f2 | 19579 | { |
74db7efb NC |
19580 | #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */ |
19581 | #define THUMB_VARIANT & arm_ext_v4t | |
21d799b5 NC |
19582 | tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c), |
19583 | tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
19584 | tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
19585 | tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
19586 | tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
19587 | tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
19588 | tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub), | |
19589 | tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub), | |
19590 | tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c), | |
19591 | tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
19592 | tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
19593 | tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
19594 | tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
19595 | tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
19596 | tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3), | |
19597 | tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3), | |
c19d1205 ZW |
19598 | |
19599 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
19600 | for setting PSR flag bits. They are obsolete in V6 and do not | |
19601 | have Thumb equivalents. */ | |
21d799b5 NC |
19602 | tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), |
19603 | tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), | |
19604 | CL("tstp", 110f000, 2, (RR, SH), cmp), | |
19605 | tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
19606 | tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
19607 | CL("cmpp", 150f000, 2, (RR, SH), cmp), | |
19608 | tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
19609 | tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
19610 | CL("cmnp", 170f000, 2, (RR, SH), cmp), | |
19611 | ||
19612 | tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp), | |
72d98d16 | 19613 | tC3("movs", 1b00000, _movs, 2, (RR, SHG), mov, t_mov_cmp), |
21d799b5 NC |
19614 | tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst), |
19615 | tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst), | |
19616 | ||
19617 | tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
5be8be5d DG |
19618 | tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), |
19619 | tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR, | |
19620 | OP_RRnpc), | |
19621 | OP_ADDRGLDR),ldst, t_ldst), | |
19622 | tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), | |
21d799b5 NC |
19623 | |
19624 | tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
19625 | tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
19626 | tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
19627 | tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
19628 | tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
19629 | tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
19630 | ||
21d799b5 NC |
19631 | tCE("b", a000000, _b, 1, (EXPr), branch, t_branch), |
19632 | TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23), | |
bfae80f2 | 19633 | |
c19d1205 | 19634 | /* Pseudo ops. */ |
21d799b5 | 19635 | tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac | 19636 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
21d799b5 | 19637 | tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop), |
74db7efb | 19638 | tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf), |
c19d1205 ZW |
19639 | |
19640 | /* Thumb-compatibility pseudo ops. */ | |
21d799b5 NC |
19641 | tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift), |
19642 | tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift), | |
19643 | tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift), | |
19644 | tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
19645 | tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift), | |
19646 | tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift), | |
19647 | tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift), | |
19648 | tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift), | |
19649 | tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg), | |
19650 | tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg), | |
19651 | tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop), | |
19652 | tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop), | |
c19d1205 | 19653 | |
16a4cf17 | 19654 | /* These may simplify to neg. */ |
21d799b5 NC |
19655 | TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), |
19656 | TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
16a4cf17 | 19657 | |
173205ca TP |
19658 | #undef THUMB_VARIANT |
19659 | #define THUMB_VARIANT & arm_ext_os | |
19660 | ||
19661 | TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi), | |
19662 | TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi), | |
19663 | ||
c921be7d NC |
19664 | #undef THUMB_VARIANT |
19665 | #define THUMB_VARIANT & arm_ext_v6 | |
19666 | ||
21d799b5 | 19667 | TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
19668 | |
19669 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
c921be7d NC |
19670 | #undef THUMB_VARIANT |
19671 | #define THUMB_VARIANT & arm_ext_v6t2 | |
19672 | ||
21d799b5 NC |
19673 | TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
19674 | TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
19675 | CL("teqp", 130f000, 2, (RR, SH), cmp), | |
c19d1205 | 19676 | |
5be8be5d DG |
19677 | TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), |
19678 | TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
19679 | TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt), | |
19680 | TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
c19d1205 | 19681 | |
21d799b5 NC |
19682 | TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
19683 | TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 19684 | |
21d799b5 NC |
19685 | TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
19686 | TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
19687 | |
19688 | /* V1 instructions with no Thumb analogue at all. */ | |
21d799b5 | 19689 | CE("rsc", 0e00000, 3, (RR, oRR, SH), arit), |
c19d1205 ZW |
19690 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), |
19691 | ||
19692 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
19693 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
19694 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
19695 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
19696 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
19697 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
19698 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
19699 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
19700 | ||
c921be7d NC |
19701 | #undef ARM_VARIANT |
19702 | #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */ | |
19703 | #undef THUMB_VARIANT | |
19704 | #define THUMB_VARIANT & arm_ext_v4t | |
19705 | ||
21d799b5 NC |
19706 | tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
19707 | tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
c19d1205 | 19708 | |
c921be7d NC |
19709 | #undef THUMB_VARIANT |
19710 | #define THUMB_VARIANT & arm_ext_v6t2 | |
19711 | ||
21d799b5 | 19712 | TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
c19d1205 ZW |
19713 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), |
19714 | ||
19715 | /* Generic coprocessor instructions. */ | |
21d799b5 NC |
19716 | TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), |
19717 | TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
19718 | TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
19719 | TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
19720 | TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
19721 | TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
db472d6f | 19722 | TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), |
c19d1205 | 19723 | |
c921be7d NC |
19724 | #undef ARM_VARIANT |
19725 | #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */ | |
19726 | ||
21d799b5 | 19727 | CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
c19d1205 ZW |
19728 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
19729 | ||
c921be7d NC |
19730 | #undef ARM_VARIANT |
19731 | #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */ | |
19732 | #undef THUMB_VARIANT | |
19733 | #define THUMB_VARIANT & arm_ext_msr | |
19734 | ||
d2cd1205 JB |
19735 | TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs), |
19736 | TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr), | |
c19d1205 | 19737 | |
c921be7d NC |
19738 | #undef ARM_VARIANT |
19739 | #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */ | |
19740 | #undef THUMB_VARIANT | |
19741 | #define THUMB_VARIANT & arm_ext_v6t2 | |
19742 | ||
21d799b5 NC |
19743 | TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
19744 | CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
19745 | TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
19746 | CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
19747 | TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
19748 | CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
19749 | TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
19750 | CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
c19d1205 | 19751 | |
c921be7d NC |
19752 | #undef ARM_VARIANT |
19753 | #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */ | |
19754 | #undef THUMB_VARIANT | |
19755 | #define THUMB_VARIANT & arm_ext_v4t | |
19756 | ||
5be8be5d DG |
19757 | tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
19758 | tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
19759 | tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
19760 | tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
56c0a61f RE |
19761 | tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
19762 | tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
c19d1205 | 19763 | |
c921be7d NC |
19764 | #undef ARM_VARIANT |
19765 | #define ARM_VARIANT & arm_ext_v4t_5 | |
19766 | ||
c19d1205 ZW |
19767 | /* ARM Architecture 4T. */ |
19768 | /* Note: bx (and blx) are required on V5, even if the processor does | |
19769 | not support Thumb. */ | |
21d799b5 | 19770 | TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx), |
c19d1205 | 19771 | |
c921be7d NC |
19772 | #undef ARM_VARIANT |
19773 | #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */ | |
19774 | #undef THUMB_VARIANT | |
19775 | #define THUMB_VARIANT & arm_ext_v5t | |
19776 | ||
c19d1205 ZW |
19777 | /* Note: blx has 2 variants; the .value coded here is for |
19778 | BLX(2). Only this variant has conditional execution. */ | |
21d799b5 NC |
19779 | TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx), |
19780 | TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
c19d1205 | 19781 | |
c921be7d NC |
19782 | #undef THUMB_VARIANT |
19783 | #define THUMB_VARIANT & arm_ext_v6t2 | |
19784 | ||
21d799b5 NC |
19785 | TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
19786 | TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
19787 | TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
19788 | TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
19789 | TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
19790 | TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
19791 | TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
19792 | TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
c19d1205 | 19793 | |
c921be7d | 19794 | #undef ARM_VARIANT |
74db7efb NC |
19795 | #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */ |
19796 | #undef THUMB_VARIANT | |
19797 | #define THUMB_VARIANT & arm_ext_v5exp | |
c921be7d | 19798 | |
21d799b5 NC |
19799 | TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
19800 | TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
19801 | TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
19802 | TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 19803 | |
21d799b5 NC |
19804 | TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
19805 | TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 19806 | |
21d799b5 NC |
19807 | TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), |
19808 | TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
19809 | TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
19810 | TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
c19d1205 | 19811 | |
21d799b5 NC |
19812 | TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
19813 | TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
19814 | TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
19815 | TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 19816 | |
21d799b5 NC |
19817 | TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
19818 | TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 19819 | |
03ee1b7f NC |
19820 | TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), |
19821 | TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
19822 | TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
19823 | TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
c19d1205 | 19824 | |
c921be7d | 19825 | #undef ARM_VARIANT |
74db7efb NC |
19826 | #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */ |
19827 | #undef THUMB_VARIANT | |
19828 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 19829 | |
21d799b5 | 19830 | TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld), |
5be8be5d DG |
19831 | TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS), |
19832 | ldrd, t_ldstd), | |
19833 | TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp, | |
19834 | ADDRGLDRS), ldrd, t_ldstd), | |
c19d1205 | 19835 | |
21d799b5 NC |
19836 | TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
19837 | TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
c19d1205 | 19838 | |
c921be7d NC |
19839 | #undef ARM_VARIANT |
19840 | #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */ | |
19841 | ||
21d799b5 | 19842 | TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
c19d1205 | 19843 | |
c921be7d NC |
19844 | #undef ARM_VARIANT |
19845 | #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */ | |
19846 | #undef THUMB_VARIANT | |
19847 | #define THUMB_VARIANT & arm_ext_v6 | |
19848 | ||
21d799b5 NC |
19849 | TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
19850 | TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
19851 | tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
19852 | tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
19853 | tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
19854 | tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
19855 | tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
19856 | tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
19857 | tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
19858 | TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend), | |
c19d1205 | 19859 | |
c921be7d | 19860 | #undef THUMB_VARIANT |
ff8646ee | 19861 | #define THUMB_VARIANT & arm_ext_v6t2_v8m |
c921be7d | 19862 | |
5be8be5d DG |
19863 | TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex), |
19864 | TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
19865 | strex, t_strex), | |
ff8646ee TP |
19866 | #undef THUMB_VARIANT |
19867 | #define THUMB_VARIANT & arm_ext_v6t2 | |
19868 | ||
21d799b5 NC |
19869 | TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
19870 | TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
62b3e311 | 19871 | |
21d799b5 NC |
19872 | TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), |
19873 | TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
62b3e311 | 19874 | |
9e3c6df6 | 19875 | /* ARM V6 not included in V7M. */ |
c921be7d NC |
19876 | #undef THUMB_VARIANT |
19877 | #define THUMB_VARIANT & arm_ext_v6_notm | |
9e3c6df6 | 19878 | TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
d709e4e6 | 19879 | TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
9e3c6df6 PB |
19880 | UF(rfeib, 9900a00, 1, (RRw), rfe), |
19881 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
19882 | TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
19883 | TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
d709e4e6 RE |
19884 | UF(rfefa, 8100a00, 1, (RRw), rfe), |
19885 | TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
19886 | UF(rfeed, 9900a00, 1, (RRw), rfe), | |
9e3c6df6 | 19887 | TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), |
d709e4e6 RE |
19888 | TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), |
19889 | TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), | |
9e3c6df6 | 19890 | UF(srsib, 9c00500, 2, (oRRw, I31w), srs), |
d709e4e6 | 19891 | UF(srsfa, 9c00500, 2, (oRRw, I31w), srs), |
9e3c6df6 | 19892 | UF(srsda, 8400500, 2, (oRRw, I31w), srs), |
d709e4e6 | 19893 | UF(srsed, 8400500, 2, (oRRw, I31w), srs), |
9e3c6df6 | 19894 | TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), |
d709e4e6 | 19895 | TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), |
941c9cad | 19896 | TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps), |
c921be7d | 19897 | |
9e3c6df6 PB |
19898 | /* ARM V6 not included in V7M (eg. integer SIMD). */ |
19899 | #undef THUMB_VARIANT | |
19900 | #define THUMB_VARIANT & arm_ext_v6_dsp | |
21d799b5 NC |
19901 | TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), |
19902 | TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
19903 | TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19904 | TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19905 | TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 19906 | /* Old name for QASX. */ |
74db7efb | 19907 | TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 | 19908 | TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 19909 | /* Old name for QSAX. */ |
74db7efb | 19910 | TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
19911 | TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
19912 | TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19913 | TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19914 | TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19915 | TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 19916 | /* Old name for SASX. */ |
74db7efb | 19917 | TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
19918 | TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
19919 | TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 19920 | TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 19921 | /* Old name for SHASX. */ |
21d799b5 | 19922 | TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
74db7efb | 19923 | TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 19924 | /* Old name for SHSAX. */ |
21d799b5 NC |
19925 | TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
19926 | TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19927 | TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19928 | TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 19929 | /* Old name for SSAX. */ |
74db7efb | 19930 | TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
19931 | TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
19932 | TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19933 | TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19934 | TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19935 | TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 19936 | /* Old name for UASX. */ |
74db7efb | 19937 | TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
19938 | TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
19939 | TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 19940 | TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 19941 | /* Old name for UHASX. */ |
21d799b5 NC |
19942 | TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
19943 | TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 19944 | /* Old name for UHSAX. */ |
21d799b5 NC |
19945 | TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
19946 | TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19947 | TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19948 | TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19949 | TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 19950 | TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 19951 | /* Old name for UQASX. */ |
21d799b5 NC |
19952 | TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
19953 | TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 19954 | /* Old name for UQSAX. */ |
21d799b5 NC |
19955 | TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
19956 | TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19957 | TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19958 | TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19959 | TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 19960 | /* Old name for USAX. */ |
74db7efb | 19961 | TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 | 19962 | TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
19963 | TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
19964 | TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
19965 | TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
19966 | TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
19967 | TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
19968 | TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
19969 | TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
19970 | TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
19971 | TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19972 | TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
19973 | TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
19974 | TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
19975 | TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
19976 | TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
19977 | TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
19978 | TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
19979 | TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
19980 | TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
19981 | TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
19982 | TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
19983 | TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
19984 | TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
19985 | TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
19986 | TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
19987 | TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
19988 | TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
19989 | TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
21d799b5 NC |
19990 | TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), |
19991 | TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
19992 | TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
19993 | TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
19994 | TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), | |
c19d1205 | 19995 | |
c921be7d NC |
19996 | #undef ARM_VARIANT |
19997 | #define ARM_VARIANT & arm_ext_v6k | |
19998 | #undef THUMB_VARIANT | |
19999 | #define THUMB_VARIANT & arm_ext_v6k | |
20000 | ||
21d799b5 NC |
20001 | tCE("yield", 320f001, _yield, 0, (), noargs, t_hint), |
20002 | tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint), | |
20003 | tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint), | |
20004 | tCE("sev", 320f004, _sev, 0, (), noargs, t_hint), | |
c19d1205 | 20005 | |
c921be7d NC |
20006 | #undef THUMB_VARIANT |
20007 | #define THUMB_VARIANT & arm_ext_v6_notm | |
5be8be5d DG |
20008 | TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb), |
20009 | ldrexd, t_ldrexd), | |
20010 | TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp, | |
20011 | RRnpcb), strexd, t_strexd), | |
ebdca51a | 20012 | |
c921be7d | 20013 | #undef THUMB_VARIANT |
ff8646ee | 20014 | #define THUMB_VARIANT & arm_ext_v6t2_v8m |
5be8be5d DG |
20015 | TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb), |
20016 | rd_rn, rd_rn), | |
20017 | TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb), | |
20018 | rd_rn, rd_rn), | |
20019 | TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
877807f8 | 20020 | strex, t_strexbh), |
5be8be5d | 20021 | TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), |
877807f8 | 20022 | strex, t_strexbh), |
21d799b5 | 20023 | TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs), |
c19d1205 | 20024 | |
c921be7d | 20025 | #undef ARM_VARIANT |
f4c65163 | 20026 | #define ARM_VARIANT & arm_ext_sec |
74db7efb | 20027 | #undef THUMB_VARIANT |
f4c65163 | 20028 | #define THUMB_VARIANT & arm_ext_sec |
c921be7d | 20029 | |
21d799b5 | 20030 | TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 | 20031 | |
90ec0d68 MGD |
20032 | #undef ARM_VARIANT |
20033 | #define ARM_VARIANT & arm_ext_virt | |
20034 | #undef THUMB_VARIANT | |
20035 | #define THUMB_VARIANT & arm_ext_virt | |
20036 | ||
20037 | TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc), | |
20038 | TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs), | |
20039 | ||
ddfded2f MW |
20040 | #undef ARM_VARIANT |
20041 | #define ARM_VARIANT & arm_ext_pan | |
20042 | #undef THUMB_VARIANT | |
20043 | #define THUMB_VARIANT & arm_ext_pan | |
20044 | ||
20045 | TUF("setpan", 1100000, b610, 1, (I7), setpan, t_setpan), | |
20046 | ||
c921be7d | 20047 | #undef ARM_VARIANT |
74db7efb | 20048 | #define ARM_VARIANT & arm_ext_v6t2 |
f4c65163 MGD |
20049 | #undef THUMB_VARIANT |
20050 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 20051 | |
21d799b5 NC |
20052 | TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
20053 | TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
20054 | TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
20055 | TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
c19d1205 | 20056 | |
21d799b5 | 20057 | TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
21d799b5 | 20058 | TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), |
c19d1205 | 20059 | |
5be8be5d DG |
20060 | TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), |
20061 | TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
20062 | TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
20063 | TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
c19d1205 | 20064 | |
91d8b670 JG |
20065 | #undef ARM_VARIANT |
20066 | #define ARM_VARIANT & arm_ext_v3 | |
20067 | #undef THUMB_VARIANT | |
20068 | #define THUMB_VARIANT & arm_ext_v6t2 | |
20069 | ||
20070 | TUE("csdb", 320f014, f3af8014, 0, (), noargs, t_csdb), | |
c597cc3d SD |
20071 | TUF("ssbb", 57ff040, f3bf8f40, 0, (), noargs, t_csdb), |
20072 | TUF("pssbb", 57ff044, f3bf8f44, 0, (), noargs, t_csdb), | |
91d8b670 JG |
20073 | |
20074 | #undef ARM_VARIANT | |
20075 | #define ARM_VARIANT & arm_ext_v6t2 | |
ff8646ee TP |
20076 | #undef THUMB_VARIANT |
20077 | #define THUMB_VARIANT & arm_ext_v6t2_v8m | |
20078 | TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), | |
20079 | TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), | |
20080 | ||
bf3eeda7 | 20081 | /* Thumb-only instructions. */ |
74db7efb | 20082 | #undef ARM_VARIANT |
bf3eeda7 NS |
20083 | #define ARM_VARIANT NULL |
20084 | TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz), | |
20085 | TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz), | |
c921be7d NC |
20086 | |
20087 | /* ARM does not really have an IT instruction, so always allow it. | |
20088 | The opcode is copied from Thumb in order to allow warnings in | |
20089 | -mimplicit-it=[never | arm] modes. */ | |
20090 | #undef ARM_VARIANT | |
20091 | #define ARM_VARIANT & arm_ext_v1 | |
ff8646ee TP |
20092 | #undef THUMB_VARIANT |
20093 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 20094 | |
21d799b5 NC |
20095 | TUE("it", bf08, bf08, 1, (COND), it, t_it), |
20096 | TUE("itt", bf0c, bf0c, 1, (COND), it, t_it), | |
20097 | TUE("ite", bf04, bf04, 1, (COND), it, t_it), | |
20098 | TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it), | |
20099 | TUE("itet", bf06, bf06, 1, (COND), it, t_it), | |
20100 | TUE("itte", bf0a, bf0a, 1, (COND), it, t_it), | |
20101 | TUE("itee", bf02, bf02, 1, (COND), it, t_it), | |
20102 | TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it), | |
20103 | TUE("itett", bf07, bf07, 1, (COND), it, t_it), | |
20104 | TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it), | |
20105 | TUE("iteet", bf03, bf03, 1, (COND), it, t_it), | |
20106 | TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it), | |
20107 | TUE("itete", bf05, bf05, 1, (COND), it, t_it), | |
20108 | TUE("ittee", bf09, bf09, 1, (COND), it, t_it), | |
20109 | TUE("iteee", bf01, bf01, 1, (COND), it, t_it), | |
1c444d06 | 20110 | /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */ |
21d799b5 NC |
20111 | TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx), |
20112 | TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx), | |
c19d1205 | 20113 | |
92e90b6e | 20114 | /* Thumb2 only instructions. */ |
c921be7d NC |
20115 | #undef ARM_VARIANT |
20116 | #define ARM_VARIANT NULL | |
92e90b6e | 20117 | |
21d799b5 NC |
20118 | TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), |
20119 | TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
20120 | TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn), | |
20121 | TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn), | |
20122 | TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb), | |
20123 | TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb), | |
92e90b6e | 20124 | |
eea54501 MGD |
20125 | /* Hardware division instructions. */ |
20126 | #undef ARM_VARIANT | |
20127 | #define ARM_VARIANT & arm_ext_adiv | |
c921be7d NC |
20128 | #undef THUMB_VARIANT |
20129 | #define THUMB_VARIANT & arm_ext_div | |
20130 | ||
eea54501 MGD |
20131 | TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div), |
20132 | TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div), | |
62b3e311 | 20133 | |
7e806470 | 20134 | /* ARM V6M/V7 instructions. */ |
c921be7d NC |
20135 | #undef ARM_VARIANT |
20136 | #define ARM_VARIANT & arm_ext_barrier | |
20137 | #undef THUMB_VARIANT | |
20138 | #define THUMB_VARIANT & arm_ext_barrier | |
20139 | ||
ccb84d65 JB |
20140 | TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier), |
20141 | TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier), | |
20142 | TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier), | |
7e806470 | 20143 | |
62b3e311 | 20144 | /* ARM V7 instructions. */ |
c921be7d NC |
20145 | #undef ARM_VARIANT |
20146 | #define ARM_VARIANT & arm_ext_v7 | |
20147 | #undef THUMB_VARIANT | |
20148 | #define THUMB_VARIANT & arm_ext_v7 | |
20149 | ||
21d799b5 NC |
20150 | TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld), |
20151 | TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), | |
62b3e311 | 20152 | |
74db7efb | 20153 | #undef ARM_VARIANT |
60e5ef9f | 20154 | #define ARM_VARIANT & arm_ext_mp |
74db7efb | 20155 | #undef THUMB_VARIANT |
60e5ef9f MGD |
20156 | #define THUMB_VARIANT & arm_ext_mp |
20157 | ||
20158 | TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld), | |
20159 | ||
53c4b28b MGD |
20160 | /* AArchv8 instructions. */ |
20161 | #undef ARM_VARIANT | |
20162 | #define ARM_VARIANT & arm_ext_v8 | |
4ed7ed8d TP |
20163 | |
20164 | /* Instructions shared between armv8-a and armv8-m. */ | |
53c4b28b | 20165 | #undef THUMB_VARIANT |
4ed7ed8d | 20166 | #define THUMB_VARIANT & arm_ext_atomics |
53c4b28b | 20167 | |
4ed7ed8d TP |
20168 | TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), |
20169 | TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
20170 | TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
20171 | TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
20172 | TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
20173 | TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
4b8c8c02 | 20174 | TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), |
4b8c8c02 RE |
20175 | TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn), |
20176 | TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
20177 | TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb), | |
20178 | stlex, t_stlex), | |
4b8c8c02 RE |
20179 | TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb), |
20180 | stlex, t_stlex), | |
20181 | TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb), | |
20182 | stlex, t_stlex), | |
4ed7ed8d TP |
20183 | #undef THUMB_VARIANT |
20184 | #define THUMB_VARIANT & arm_ext_v8 | |
53c4b28b | 20185 | |
4ed7ed8d TP |
20186 | tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint), |
20187 | TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt), | |
20188 | TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb), | |
20189 | ldrexd, t_ldrexd), | |
20190 | TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), | |
20191 | strexd, t_strexd), | |
8884b720 | 20192 | /* ARMv8 T32 only. */ |
74db7efb | 20193 | #undef ARM_VARIANT |
b79f7053 MGD |
20194 | #define ARM_VARIANT NULL |
20195 | TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs), | |
20196 | TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs), | |
20197 | TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs), | |
20198 | ||
33399f07 MGD |
20199 | /* FP for ARMv8. */ |
20200 | #undef ARM_VARIANT | |
a715796b | 20201 | #define ARM_VARIANT & fpu_vfp_ext_armv8xd |
33399f07 | 20202 | #undef THUMB_VARIANT |
a715796b | 20203 | #define THUMB_VARIANT & fpu_vfp_ext_armv8xd |
33399f07 MGD |
20204 | |
20205 | nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel), | |
20206 | nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel), | |
20207 | nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel), | |
20208 | nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel), | |
73924fbc MGD |
20209 | nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm), |
20210 | nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm), | |
7e8e6784 MGD |
20211 | nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta), |
20212 | nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn), | |
20213 | nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp), | |
20214 | nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm), | |
30bdf752 MGD |
20215 | nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr), |
20216 | nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz), | |
20217 | nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx), | |
20218 | nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta), | |
20219 | nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn), | |
20220 | nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp), | |
20221 | nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm), | |
33399f07 | 20222 | |
91ff7894 MGD |
20223 | /* Crypto v1 extensions. */ |
20224 | #undef ARM_VARIANT | |
20225 | #define ARM_VARIANT & fpu_crypto_ext_armv8 | |
20226 | #undef THUMB_VARIANT | |
20227 | #define THUMB_VARIANT & fpu_crypto_ext_armv8 | |
20228 | ||
20229 | nUF(aese, _aes, 2, (RNQ, RNQ), aese), | |
20230 | nUF(aesd, _aes, 2, (RNQ, RNQ), aesd), | |
20231 | nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc), | |
20232 | nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc), | |
48adcd8e MGD |
20233 | nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c), |
20234 | nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p), | |
20235 | nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m), | |
20236 | nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0), | |
20237 | nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h), | |
20238 | nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2), | |
20239 | nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1), | |
3c9017d2 MGD |
20240 | nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h), |
20241 | nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1), | |
20242 | nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0), | |
91ff7894 | 20243 | |
dd5181d5 | 20244 | #undef ARM_VARIANT |
74db7efb | 20245 | #define ARM_VARIANT & crc_ext_armv8 |
dd5181d5 KT |
20246 | #undef THUMB_VARIANT |
20247 | #define THUMB_VARIANT & crc_ext_armv8 | |
20248 | TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b), | |
20249 | TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h), | |
20250 | TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w), | |
20251 | TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb), | |
20252 | TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch), | |
20253 | TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw), | |
20254 | ||
105bde57 MW |
20255 | /* ARMv8.2 RAS extension. */ |
20256 | #undef ARM_VARIANT | |
4d1464f2 | 20257 | #define ARM_VARIANT & arm_ext_ras |
105bde57 | 20258 | #undef THUMB_VARIANT |
4d1464f2 | 20259 | #define THUMB_VARIANT & arm_ext_ras |
105bde57 MW |
20260 | TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs), |
20261 | ||
49e8a725 SN |
20262 | #undef ARM_VARIANT |
20263 | #define ARM_VARIANT & arm_ext_v8_3 | |
20264 | #undef THUMB_VARIANT | |
20265 | #define THUMB_VARIANT & arm_ext_v8_3 | |
20266 | NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt), | |
c28eeff2 SN |
20267 | NUF (vcmla, 0, 4, (RNDQ, RNDQ, RNDQ_RNSC, EXPi), vcmla), |
20268 | NUF (vcadd, 0, 4, (RNDQ, RNDQ, RNDQ, EXPi), vcadd), | |
49e8a725 | 20269 | |
c604a79a JW |
20270 | #undef ARM_VARIANT |
20271 | #define ARM_VARIANT & fpu_neon_ext_dotprod | |
20272 | #undef THUMB_VARIANT | |
20273 | #define THUMB_VARIANT & fpu_neon_ext_dotprod | |
20274 | NUF (vsdot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_s), | |
20275 | NUF (vudot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_u), | |
20276 | ||
c921be7d NC |
20277 | #undef ARM_VARIANT |
20278 | #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ | |
53c4b28b MGD |
20279 | #undef THUMB_VARIANT |
20280 | #define THUMB_VARIANT NULL | |
c921be7d | 20281 | |
21d799b5 NC |
20282 | cCE("wfs", e200110, 1, (RR), rd), |
20283 | cCE("rfs", e300110, 1, (RR), rd), | |
20284 | cCE("wfc", e400110, 1, (RR), rd), | |
20285 | cCE("rfc", e500110, 1, (RR), rd), | |
20286 | ||
20287 | cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
20288 | cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
20289 | cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
20290 | cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
20291 | ||
20292 | cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
20293 | cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
20294 | cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
20295 | cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
20296 | ||
20297 | cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm), | |
20298 | cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm), | |
20299 | cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm), | |
20300 | cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm), | |
20301 | cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm), | |
20302 | cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm), | |
20303 | cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm), | |
20304 | cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm), | |
20305 | cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm), | |
20306 | cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm), | |
20307 | cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm), | |
20308 | cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm), | |
20309 | ||
20310 | cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm), | |
20311 | cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm), | |
20312 | cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm), | |
20313 | cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm), | |
20314 | cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm), | |
20315 | cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm), | |
20316 | cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm), | |
20317 | cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm), | |
20318 | cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm), | |
20319 | cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm), | |
20320 | cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm), | |
20321 | cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm), | |
20322 | ||
20323 | cCL("abss", e208100, 2, (RF, RF_IF), rd_rm), | |
20324 | cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm), | |
20325 | cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm), | |
20326 | cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm), | |
20327 | cCL("absd", e208180, 2, (RF, RF_IF), rd_rm), | |
20328 | cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm), | |
20329 | cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm), | |
20330 | cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm), | |
20331 | cCL("abse", e288100, 2, (RF, RF_IF), rd_rm), | |
20332 | cCL("absep", e288120, 2, (RF, RF_IF), rd_rm), | |
20333 | cCL("absem", e288140, 2, (RF, RF_IF), rd_rm), | |
20334 | cCL("absez", e288160, 2, (RF, RF_IF), rd_rm), | |
20335 | ||
20336 | cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm), | |
20337 | cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm), | |
20338 | cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm), | |
20339 | cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm), | |
20340 | cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm), | |
20341 | cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm), | |
20342 | cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm), | |
20343 | cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm), | |
20344 | cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm), | |
20345 | cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm), | |
20346 | cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm), | |
20347 | cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm), | |
20348 | ||
20349 | cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm), | |
20350 | cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm), | |
20351 | cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm), | |
20352 | cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm), | |
20353 | cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm), | |
20354 | cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm), | |
20355 | cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm), | |
20356 | cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm), | |
20357 | cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm), | |
20358 | cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm), | |
20359 | cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm), | |
20360 | cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm), | |
20361 | ||
20362 | cCL("logs", e508100, 2, (RF, RF_IF), rd_rm), | |
20363 | cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm), | |
20364 | cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm), | |
20365 | cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm), | |
20366 | cCL("logd", e508180, 2, (RF, RF_IF), rd_rm), | |
20367 | cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm), | |
20368 | cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm), | |
20369 | cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm), | |
20370 | cCL("loge", e588100, 2, (RF, RF_IF), rd_rm), | |
20371 | cCL("logep", e588120, 2, (RF, RF_IF), rd_rm), | |
20372 | cCL("logem", e588140, 2, (RF, RF_IF), rd_rm), | |
20373 | cCL("logez", e588160, 2, (RF, RF_IF), rd_rm), | |
20374 | ||
20375 | cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm), | |
20376 | cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm), | |
20377 | cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm), | |
20378 | cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm), | |
20379 | cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm), | |
20380 | cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm), | |
20381 | cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm), | |
20382 | cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm), | |
20383 | cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm), | |
20384 | cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm), | |
20385 | cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm), | |
20386 | cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm), | |
20387 | ||
20388 | cCL("exps", e708100, 2, (RF, RF_IF), rd_rm), | |
20389 | cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm), | |
20390 | cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm), | |
20391 | cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm), | |
20392 | cCL("expd", e708180, 2, (RF, RF_IF), rd_rm), | |
20393 | cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm), | |
20394 | cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm), | |
20395 | cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm), | |
20396 | cCL("expe", e788100, 2, (RF, RF_IF), rd_rm), | |
20397 | cCL("expep", e788120, 2, (RF, RF_IF), rd_rm), | |
20398 | cCL("expem", e788140, 2, (RF, RF_IF), rd_rm), | |
20399 | cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm), | |
20400 | ||
20401 | cCL("sins", e808100, 2, (RF, RF_IF), rd_rm), | |
20402 | cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm), | |
20403 | cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm), | |
20404 | cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm), | |
20405 | cCL("sind", e808180, 2, (RF, RF_IF), rd_rm), | |
20406 | cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm), | |
20407 | cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm), | |
20408 | cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm), | |
20409 | cCL("sine", e888100, 2, (RF, RF_IF), rd_rm), | |
20410 | cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm), | |
20411 | cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm), | |
20412 | cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm), | |
20413 | ||
20414 | cCL("coss", e908100, 2, (RF, RF_IF), rd_rm), | |
20415 | cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm), | |
20416 | cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm), | |
20417 | cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm), | |
20418 | cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm), | |
20419 | cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm), | |
20420 | cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm), | |
20421 | cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm), | |
20422 | cCL("cose", e988100, 2, (RF, RF_IF), rd_rm), | |
20423 | cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm), | |
20424 | cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm), | |
20425 | cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm), | |
20426 | ||
20427 | cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm), | |
20428 | cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm), | |
20429 | cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm), | |
20430 | cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm), | |
20431 | cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm), | |
20432 | cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm), | |
20433 | cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm), | |
20434 | cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm), | |
20435 | cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm), | |
20436 | cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm), | |
20437 | cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm), | |
20438 | cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm), | |
20439 | ||
20440 | cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm), | |
20441 | cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm), | |
20442 | cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm), | |
20443 | cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm), | |
20444 | cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm), | |
20445 | cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm), | |
20446 | cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm), | |
20447 | cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm), | |
20448 | cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm), | |
20449 | cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm), | |
20450 | cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm), | |
20451 | cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm), | |
20452 | ||
20453 | cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm), | |
20454 | cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm), | |
20455 | cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm), | |
20456 | cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm), | |
20457 | cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm), | |
20458 | cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm), | |
20459 | cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm), | |
20460 | cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm), | |
20461 | cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm), | |
20462 | cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm), | |
20463 | cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm), | |
20464 | cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm), | |
20465 | ||
20466 | cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm), | |
20467 | cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm), | |
20468 | cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm), | |
20469 | cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm), | |
20470 | cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm), | |
20471 | cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm), | |
20472 | cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm), | |
20473 | cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm), | |
20474 | cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm), | |
20475 | cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm), | |
20476 | cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm), | |
20477 | cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm), | |
20478 | ||
20479 | cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm), | |
20480 | cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm), | |
20481 | cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm), | |
20482 | cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm), | |
20483 | cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm), | |
20484 | cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm), | |
20485 | cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm), | |
20486 | cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm), | |
20487 | cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm), | |
20488 | cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm), | |
20489 | cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm), | |
20490 | cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm), | |
20491 | ||
20492 | cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm), | |
20493 | cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm), | |
20494 | cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm), | |
20495 | cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm), | |
20496 | cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm), | |
20497 | cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm), | |
20498 | cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm), | |
20499 | cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm), | |
20500 | cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm), | |
20501 | cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm), | |
20502 | cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm), | |
20503 | cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm), | |
20504 | ||
20505 | cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20506 | cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20507 | cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20508 | cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20509 | cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20510 | cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20511 | cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20512 | cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20513 | cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20514 | cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20515 | cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20516 | cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20517 | ||
20518 | cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20519 | cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20520 | cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20521 | cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20522 | cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20523 | cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20524 | cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20525 | cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20526 | cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20527 | cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20528 | cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20529 | cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20530 | ||
20531 | cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20532 | cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20533 | cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20534 | cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20535 | cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20536 | cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20537 | cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20538 | cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20539 | cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20540 | cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20541 | cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20542 | cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20543 | ||
20544 | cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20545 | cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20546 | cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20547 | cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20548 | cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20549 | cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20550 | cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20551 | cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20552 | cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20553 | cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20554 | cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20555 | cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20556 | ||
20557 | cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20558 | cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20559 | cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20560 | cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20561 | cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20562 | cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20563 | cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20564 | cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20565 | cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20566 | cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20567 | cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20568 | cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20569 | ||
20570 | cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20571 | cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20572 | cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20573 | cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20574 | cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20575 | cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20576 | cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20577 | cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20578 | cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20579 | cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20580 | cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20581 | cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20582 | ||
20583 | cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20584 | cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20585 | cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20586 | cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20587 | cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20588 | cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20589 | cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20590 | cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20591 | cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20592 | cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20593 | cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20594 | cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20595 | ||
20596 | cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20597 | cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20598 | cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20599 | cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20600 | cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20601 | cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20602 | cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20603 | cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20604 | cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20605 | cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20606 | cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20607 | cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20608 | ||
20609 | cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20610 | cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20611 | cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20612 | cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20613 | cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20614 | cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20615 | cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20616 | cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20617 | cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20618 | cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20619 | cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20620 | cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20621 | ||
20622 | cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20623 | cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20624 | cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20625 | cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20626 | cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20627 | cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20628 | cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20629 | cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20630 | cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20631 | cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20632 | cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20633 | cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20634 | ||
20635 | cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20636 | cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20637 | cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20638 | cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20639 | cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20640 | cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20641 | cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20642 | cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20643 | cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20644 | cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20645 | cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20646 | cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20647 | ||
20648 | cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20649 | cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20650 | cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20651 | cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20652 | cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20653 | cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20654 | cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20655 | cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20656 | cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20657 | cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20658 | cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20659 | cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20660 | ||
20661 | cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20662 | cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20663 | cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20664 | cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20665 | cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20666 | cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20667 | cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20668 | cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20669 | cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20670 | cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20671 | cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20672 | cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
20673 | ||
20674 | cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp), | |
20675 | C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp), | |
20676 | cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp), | |
20677 | C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp), | |
20678 | ||
20679 | cCL("flts", e000110, 2, (RF, RR), rn_rd), | |
20680 | cCL("fltsp", e000130, 2, (RF, RR), rn_rd), | |
20681 | cCL("fltsm", e000150, 2, (RF, RR), rn_rd), | |
20682 | cCL("fltsz", e000170, 2, (RF, RR), rn_rd), | |
20683 | cCL("fltd", e000190, 2, (RF, RR), rn_rd), | |
20684 | cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd), | |
20685 | cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd), | |
20686 | cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd), | |
20687 | cCL("flte", e080110, 2, (RF, RR), rn_rd), | |
20688 | cCL("fltep", e080130, 2, (RF, RR), rn_rd), | |
20689 | cCL("fltem", e080150, 2, (RF, RR), rn_rd), | |
20690 | cCL("fltez", e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 20691 | |
c19d1205 ZW |
20692 | /* The implementation of the FIX instruction is broken on some |
20693 | assemblers, in that it accepts a precision specifier as well as a | |
20694 | rounding specifier, despite the fact that this is meaningless. | |
20695 | To be more compatible, we accept it as well, though of course it | |
20696 | does not set any bits. */ | |
21d799b5 NC |
20697 | cCE("fix", e100110, 2, (RR, RF), rd_rm), |
20698 | cCL("fixp", e100130, 2, (RR, RF), rd_rm), | |
20699 | cCL("fixm", e100150, 2, (RR, RF), rd_rm), | |
20700 | cCL("fixz", e100170, 2, (RR, RF), rd_rm), | |
20701 | cCL("fixsp", e100130, 2, (RR, RF), rd_rm), | |
20702 | cCL("fixsm", e100150, 2, (RR, RF), rd_rm), | |
20703 | cCL("fixsz", e100170, 2, (RR, RF), rd_rm), | |
20704 | cCL("fixdp", e100130, 2, (RR, RF), rd_rm), | |
20705 | cCL("fixdm", e100150, 2, (RR, RF), rd_rm), | |
20706 | cCL("fixdz", e100170, 2, (RR, RF), rd_rm), | |
20707 | cCL("fixep", e100130, 2, (RR, RF), rd_rm), | |
20708 | cCL("fixem", e100150, 2, (RR, RF), rd_rm), | |
20709 | cCL("fixez", e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 20710 | |
c19d1205 | 20711 | /* Instructions that were new with the real FPA, call them V2. */ |
c921be7d NC |
20712 | #undef ARM_VARIANT |
20713 | #define ARM_VARIANT & fpu_fpa_ext_v2 | |
20714 | ||
21d799b5 NC |
20715 | cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
20716 | cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
20717 | cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
20718 | cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
20719 | cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
20720 | cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 | 20721 | |
c921be7d NC |
20722 | #undef ARM_VARIANT |
20723 | #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ | |
20724 | ||
c19d1205 | 20725 | /* Moves and type conversions. */ |
21d799b5 NC |
20726 | cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
20727 | cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
20728 | cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
20729 | cCE("fmstat", ef1fa10, 0, (), noargs), | |
7465e07a NC |
20730 | cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs), |
20731 | cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr), | |
21d799b5 NC |
20732 | cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), |
20733 | cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
20734 | cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
20735 | cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
20736 | cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
20737 | cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
20738 | cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn), | |
20739 | cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
20740 | |
20741 | /* Memory operations. */ | |
21d799b5 NC |
20742 | cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), |
20743 | cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), | |
55881a11 MGD |
20744 | cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), |
20745 | cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
20746 | cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
20747 | cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
20748 | cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
20749 | cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
20750 | cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
20751 | cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
20752 | cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
20753 | cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
20754 | cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
20755 | cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
20756 | cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
20757 | cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
20758 | cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
20759 | cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 20760 | |
c19d1205 | 20761 | /* Monadic operations. */ |
21d799b5 NC |
20762 | cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
20763 | cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
20764 | cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
20765 | |
20766 | /* Dyadic operations. */ | |
21d799b5 NC |
20767 | cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
20768 | cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
20769 | cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
20770 | cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
20771 | cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
20772 | cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
20773 | cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
20774 | cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
20775 | cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 20776 | |
c19d1205 | 20777 | /* Comparisons. */ |
21d799b5 NC |
20778 | cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
20779 | cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z), | |
20780 | cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
20781 | cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 20782 | |
62f3b8c8 PB |
20783 | /* Double precision load/store are still present on single precision |
20784 | implementations. */ | |
20785 | cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
20786 | cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
55881a11 MGD |
20787 | cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), |
20788 | cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
20789 | cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
20790 | cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
20791 | cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
20792 | cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
20793 | cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
20794 | cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
62f3b8c8 | 20795 | |
c921be7d NC |
20796 | #undef ARM_VARIANT |
20797 | #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ | |
20798 | ||
c19d1205 | 20799 | /* Moves and type conversions. */ |
21d799b5 NC |
20800 | cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
20801 | cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
20802 | cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
20803 | cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
20804 | cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
20805 | cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
20806 | cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
20807 | cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
20808 | cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
20809 | cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
20810 | cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
20811 | cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
20812 | cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 | 20813 | |
c19d1205 | 20814 | /* Monadic operations. */ |
21d799b5 NC |
20815 | cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
20816 | cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), | |
20817 | cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
c19d1205 ZW |
20818 | |
20819 | /* Dyadic operations. */ | |
21d799b5 NC |
20820 | cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
20821 | cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
20822 | cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
20823 | cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
20824 | cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
20825 | cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
20826 | cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
20827 | cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
20828 | cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
b99bd4ef | 20829 | |
c19d1205 | 20830 | /* Comparisons. */ |
21d799b5 NC |
20831 | cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
20832 | cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd), | |
20833 | cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
20834 | cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd), | |
c19d1205 | 20835 | |
c921be7d NC |
20836 | #undef ARM_VARIANT |
20837 | #define ARM_VARIANT & fpu_vfp_ext_v2 | |
20838 | ||
21d799b5 NC |
20839 | cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
20840 | cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
20841 | cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), | |
20842 | cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), | |
5287ad62 | 20843 | |
037e8744 JB |
20844 | /* Instructions which may belong to either the Neon or VFP instruction sets. |
20845 | Individual encoder functions perform additional architecture checks. */ | |
c921be7d NC |
20846 | #undef ARM_VARIANT |
20847 | #define ARM_VARIANT & fpu_vfp_ext_v1xd | |
20848 | #undef THUMB_VARIANT | |
20849 | #define THUMB_VARIANT & fpu_vfp_ext_v1xd | |
20850 | ||
037e8744 JB |
20851 | /* These mnemonics are unique to VFP. */ |
20852 | NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), | |
20853 | NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), | |
21d799b5 NC |
20854 | nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
20855 | nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
20856 | nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
aacf0b33 KT |
20857 | nCE(vcmp, _vcmp, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp), |
20858 | nCE(vcmpe, _vcmpe, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp), | |
037e8744 JB |
20859 | NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), |
20860 | NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), | |
20861 | NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), | |
20862 | ||
20863 | /* Mnemonics shared by Neon and VFP. */ | |
21d799b5 NC |
20864 | nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), |
20865 | nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
20866 | nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
037e8744 | 20867 | |
21d799b5 NC |
20868 | nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), |
20869 | nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), | |
037e8744 JB |
20870 | |
20871 | NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
20872 | NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
20873 | ||
55881a11 MGD |
20874 | NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
20875 | NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
20876 | NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
20877 | NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
20878 | NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
20879 | NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
4962c51a MS |
20880 | NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), |
20881 | NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), | |
037e8744 | 20882 | |
5f1af56b | 20883 | nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt), |
e3e535bc | 20884 | nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr), |
c70a8987 MGD |
20885 | NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb), |
20886 | NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt), | |
f31fef98 | 20887 | |
037e8744 JB |
20888 | |
20889 | /* NOTE: All VMOV encoding is special-cased! */ | |
20890 | NCE(vmov, 0, 1, (VMOV), neon_mov), | |
20891 | NCE(vmovq, 0, 1, (VMOV), neon_mov), | |
20892 | ||
9db2f6b4 RL |
20893 | #undef ARM_VARIANT |
20894 | #define ARM_VARIANT & arm_ext_fp16 | |
20895 | #undef THUMB_VARIANT | |
20896 | #define THUMB_VARIANT & arm_ext_fp16 | |
20897 | /* New instructions added from v8.2, allowing the extraction and insertion of | |
20898 | the upper 16 bits of a 32-bit vector register. */ | |
20899 | NCE (vmovx, eb00a40, 2, (RVS, RVS), neon_movhf), | |
20900 | NCE (vins, eb00ac0, 2, (RVS, RVS), neon_movhf), | |
20901 | ||
dec41383 JW |
20902 | /* New backported fma/fms instructions optional in v8.2. */ |
20903 | NCE (vfmal, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmal), | |
20904 | NCE (vfmsl, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmsl), | |
20905 | ||
c921be7d NC |
20906 | #undef THUMB_VARIANT |
20907 | #define THUMB_VARIANT & fpu_neon_ext_v1 | |
20908 | #undef ARM_VARIANT | |
20909 | #define ARM_VARIANT & fpu_neon_ext_v1 | |
20910 | ||
5287ad62 JB |
20911 | /* Data processing with three registers of the same length. */ |
20912 | /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ | |
20913 | NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), | |
20914 | NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), | |
20915 | NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
20916 | NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
20917 | NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
20918 | NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
20919 | NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
20920 | NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
20921 | /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ | |
20922 | NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
20923 | NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
20924 | NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
20925 | NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
627907b7 JB |
20926 | NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), |
20927 | NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
20928 | NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), | |
20929 | NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
5287ad62 JB |
20930 | /* If not immediate, fall back to neon_dyadic_i64_su. |
20931 | shl_imm should accept I8 I16 I32 I64, | |
20932 | qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ | |
21d799b5 NC |
20933 | nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), |
20934 | nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), | |
20935 | nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), | |
20936 | nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), | |
5287ad62 | 20937 | /* Logic ops, types optional & ignored. */ |
4316f0d2 DG |
20938 | nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), |
20939 | nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
20940 | nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
20941 | nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
20942 | nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
20943 | nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
20944 | nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
20945 | nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
20946 | nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), | |
20947 | nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic), | |
5287ad62 JB |
20948 | /* Bitfield ops, untyped. */ |
20949 | NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
20950 | NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
20951 | NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
20952 | NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
20953 | NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
20954 | NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
cc933301 | 20955 | /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */ |
21d799b5 NC |
20956 | nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), |
20957 | nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
20958 | nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
20959 | nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
20960 | nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
20961 | nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
5287ad62 JB |
20962 | /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall |
20963 | back to neon_dyadic_if_su. */ | |
21d799b5 NC |
20964 | nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), |
20965 | nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
20966 | nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), | |
20967 | nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
20968 | nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
20969 | nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
20970 | nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
20971 | nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
428e3f1f | 20972 | /* Comparison. Type I8 I16 I32 F32. */ |
21d799b5 NC |
20973 | nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), |
20974 | nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), | |
5287ad62 | 20975 | /* As above, D registers only. */ |
21d799b5 NC |
20976 | nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), |
20977 | nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), | |
5287ad62 | 20978 | /* Int and float variants, signedness unimportant. */ |
21d799b5 NC |
20979 | nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
20980 | nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), | |
20981 | nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), | |
5287ad62 | 20982 | /* Add/sub take types I8 I16 I32 I64 F32. */ |
21d799b5 NC |
20983 | nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
20984 | nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), | |
5287ad62 JB |
20985 | /* vtst takes sizes 8, 16, 32. */ |
20986 | NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), | |
20987 | NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), | |
20988 | /* VMUL takes I8 I16 I32 F32 P8. */ | |
21d799b5 | 20989 | nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), |
5287ad62 | 20990 | /* VQD{R}MULH takes S16 S32. */ |
21d799b5 NC |
20991 | nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), |
20992 | nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
20993 | nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
20994 | nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
5287ad62 JB |
20995 | NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), |
20996 | NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
20997 | NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), | |
20998 | NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
92559b5b PB |
20999 | NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), |
21000 | NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
21001 | NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), | |
21002 | NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
5287ad62 JB |
21003 | NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), |
21004 | NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
21005 | NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), | |
21006 | NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
d6b4b13e | 21007 | /* ARM v8.1 extension. */ |
643afb90 MW |
21008 | nUF (vqrdmlah, _vqrdmlah, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah), |
21009 | nUF (vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah), | |
21010 | nUF (vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah), | |
21011 | nUF (vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah), | |
5287ad62 JB |
21012 | |
21013 | /* Two address, int/float. Types S8 S16 S32 F32. */ | |
5287ad62 | 21014 | NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), |
5287ad62 JB |
21015 | NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), |
21016 | ||
21017 | /* Data processing with two registers and a shift amount. */ | |
21018 | /* Right shifts, and variants with rounding. | |
21019 | Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ | |
21020 | NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
21021 | NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
21022 | NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
21023 | NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
21024 | NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
21025 | NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
21026 | NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
21027 | NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
21028 | /* Shift and insert. Sizes accepted 8 16 32 64. */ | |
21029 | NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), | |
21030 | NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), | |
21031 | NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), | |
21032 | NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), | |
21033 | /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ | |
21034 | NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), | |
21035 | NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), | |
21036 | /* Right shift immediate, saturating & narrowing, with rounding variants. | |
21037 | Types accepted S16 S32 S64 U16 U32 U64. */ | |
21038 | NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
21039 | NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
21040 | /* As above, unsigned. Types accepted S16 S32 S64. */ | |
21041 | NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
21042 | NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
21043 | /* Right shift narrowing. Types accepted I16 I32 I64. */ | |
21044 | NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
21045 | NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
21046 | /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ | |
21d799b5 | 21047 | nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll), |
5287ad62 | 21048 | /* CVT with optional immediate for fixed-point variant. */ |
21d799b5 | 21049 | nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), |
b7fc2769 | 21050 | |
4316f0d2 DG |
21051 | nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn), |
21052 | nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn), | |
5287ad62 JB |
21053 | |
21054 | /* Data processing, three registers of different lengths. */ | |
21055 | /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ | |
21056 | NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), | |
21057 | NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), | |
21058 | NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), | |
21059 | NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), | |
21060 | /* If not scalar, fall back to neon_dyadic_long. | |
21061 | Vector types as above, scalar types S16 S32 U16 U32. */ | |
21d799b5 NC |
21062 | nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), |
21063 | nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), | |
5287ad62 JB |
21064 | /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ |
21065 | NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
21066 | NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
21067 | /* Dyadic, narrowing insns. Types I16 I32 I64. */ | |
21068 | NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
21069 | NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
21070 | NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
21071 | NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
21072 | /* Saturating doubling multiplies. Types S16 S32. */ | |
21d799b5 NC |
21073 | nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), |
21074 | nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
21075 | nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
5287ad62 JB |
21076 | /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types |
21077 | S16 S32 U16 U32. */ | |
21d799b5 | 21078 | nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), |
5287ad62 JB |
21079 | |
21080 | /* Extract. Size 8. */ | |
3b8d421e PB |
21081 | NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), |
21082 | NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), | |
5287ad62 JB |
21083 | |
21084 | /* Two registers, miscellaneous. */ | |
21085 | /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ | |
21086 | NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), | |
21087 | NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), | |
21088 | NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), | |
21089 | NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), | |
21090 | NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), | |
21091 | NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), | |
21092 | /* Vector replicate. Sizes 8 16 32. */ | |
21d799b5 NC |
21093 | nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup), |
21094 | nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup), | |
5287ad62 JB |
21095 | /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ |
21096 | NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), | |
21097 | /* VMOVN. Types I16 I32 I64. */ | |
21d799b5 | 21098 | nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn), |
5287ad62 | 21099 | /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ |
21d799b5 | 21100 | nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn), |
5287ad62 | 21101 | /* VQMOVUN. Types S16 S32 S64. */ |
21d799b5 | 21102 | nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun), |
5287ad62 JB |
21103 | /* VZIP / VUZP. Sizes 8 16 32. */ |
21104 | NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
21105 | NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), | |
21106 | NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
21107 | NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), | |
21108 | /* VQABS / VQNEG. Types S8 S16 S32. */ | |
21109 | NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
21110 | NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
21111 | NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
21112 | NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
21113 | /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ | |
21114 | NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), | |
21115 | NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), | |
21116 | NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), | |
21117 | NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), | |
cc933301 | 21118 | /* Reciprocal estimates. Types U32 F16 F32. */ |
5287ad62 JB |
21119 | NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), |
21120 | NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), | |
21121 | NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), | |
21122 | NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), | |
21123 | /* VCLS. Types S8 S16 S32. */ | |
21124 | NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), | |
21125 | NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), | |
21126 | /* VCLZ. Types I8 I16 I32. */ | |
21127 | NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), | |
21128 | NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), | |
21129 | /* VCNT. Size 8. */ | |
21130 | NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), | |
21131 | NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), | |
21132 | /* Two address, untyped. */ | |
21133 | NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), | |
21134 | NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), | |
21135 | /* VTRN. Sizes 8 16 32. */ | |
21d799b5 NC |
21136 | nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn), |
21137 | nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn), | |
5287ad62 JB |
21138 | |
21139 | /* Table lookup. Size 8. */ | |
21140 | NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
21141 | NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
21142 | ||
c921be7d NC |
21143 | #undef THUMB_VARIANT |
21144 | #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext | |
21145 | #undef ARM_VARIANT | |
21146 | #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext | |
21147 | ||
5287ad62 | 21148 | /* Neon element/structure load/store. */ |
21d799b5 NC |
21149 | nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), |
21150 | nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
21151 | nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
21152 | nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
21153 | nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
21154 | nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
21155 | nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
21156 | nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
5287ad62 | 21157 | |
c921be7d | 21158 | #undef THUMB_VARIANT |
74db7efb NC |
21159 | #define THUMB_VARIANT & fpu_vfp_ext_v3xd |
21160 | #undef ARM_VARIANT | |
21161 | #define ARM_VARIANT & fpu_vfp_ext_v3xd | |
62f3b8c8 PB |
21162 | cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const), |
21163 | cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
21164 | cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
21165 | cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
21166 | cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
21167 | cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
21168 | cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
21169 | cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
21170 | cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
21171 | ||
74db7efb | 21172 | #undef THUMB_VARIANT |
c921be7d NC |
21173 | #define THUMB_VARIANT & fpu_vfp_ext_v3 |
21174 | #undef ARM_VARIANT | |
21175 | #define ARM_VARIANT & fpu_vfp_ext_v3 | |
21176 | ||
21d799b5 | 21177 | cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const), |
21d799b5 | 21178 | cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 21179 | cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 21180 | cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 21181 | cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 21182 | cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 21183 | cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 21184 | cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 21185 | cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
c19d1205 | 21186 | |
74db7efb NC |
21187 | #undef ARM_VARIANT |
21188 | #define ARM_VARIANT & fpu_vfp_ext_fma | |
21189 | #undef THUMB_VARIANT | |
21190 | #define THUMB_VARIANT & fpu_vfp_ext_fma | |
62f3b8c8 PB |
21191 | /* Mnemonics shared by Neon and VFP. These are included in the |
21192 | VFP FMA variant; NEON and VFP FMA always includes the NEON | |
21193 | FMA instructions. */ | |
21194 | nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
21195 | nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
21196 | /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas; | |
21197 | the v form should always be used. */ | |
21198 | cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
21199 | cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
21200 | cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
21201 | cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
21202 | nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
21203 | nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
21204 | ||
5287ad62 | 21205 | #undef THUMB_VARIANT |
c921be7d NC |
21206 | #undef ARM_VARIANT |
21207 | #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */ | |
21208 | ||
21d799b5 NC |
21209 | cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
21210 | cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
21211 | cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
21212 | cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
21213 | cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
21214 | cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
21215 | cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
21216 | cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 | 21217 | |
c921be7d NC |
21218 | #undef ARM_VARIANT |
21219 | #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */ | |
21220 | ||
21d799b5 NC |
21221 | cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc), |
21222 | cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc), | |
21223 | cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc), | |
21224 | cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd), | |
21225 | cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd), | |
21226 | cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd), | |
21227 | cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc), | |
21228 | cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc), | |
21229 | cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc), | |
74db7efb NC |
21230 | cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), |
21231 | cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
21232 | cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
21233 | cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
21234 | cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
21235 | cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
21d799b5 NC |
21236 | cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), |
21237 | cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
21238 | cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
21239 | cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd), | |
21240 | cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn), | |
21241 | cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
21242 | cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
21243 | cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
21244 | cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
21245 | cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
21246 | cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
74db7efb NC |
21247 | cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn), |
21248 | cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn), | |
21249 | cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn), | |
21d799b5 NC |
21250 | cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn), |
21251 | cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm), | |
21252 | cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc), | |
21253 | cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc), | |
21254 | cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc), | |
21255 | cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn), | |
21256 | cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn), | |
21257 | cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn), | |
21258 | cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21259 | cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21260 | cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21261 | cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21262 | cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21263 | cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21264 | cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21265 | cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21266 | cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21267 | cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
74db7efb NC |
21268 | cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
21269 | cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21270 | cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21271 | cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
21272 | cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
21273 | cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21274 | cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21275 | cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21276 | cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21277 | cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21278 | cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21279 | cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21280 | cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
74db7efb NC |
21281 | cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
21282 | cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21283 | cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21284 | cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21285 | cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21286 | cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
21287 | cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), |
21288 | cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
21289 | cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
21290 | cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
21291 | cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21292 | cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21293 | cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21294 | cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21295 | cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21296 | cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21297 | cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21298 | cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21299 | cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21300 | cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21301 | cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21302 | cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21303 | cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21304 | cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21305 | cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21306 | cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21307 | cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21308 | cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21309 | cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
21310 | cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21311 | cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21312 | cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21313 | cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21314 | cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
74db7efb NC |
21315 | cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
21316 | cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21317 | cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21318 | cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21319 | cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21320 | cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
21321 | cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
21322 | cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
21323 | cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
21324 | cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
21325 | cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
21326 | cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
21327 | cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21328 | cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21329 | cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21330 | cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21331 | cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
21332 | cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
21333 | cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
21334 | cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
21335 | cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
21336 | cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
21337 | cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
21338 | cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
21339 | cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
21340 | cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
21341 | cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
21342 | cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
21343 | cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
21344 | cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
21345 | cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
21346 | cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
21347 | cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
21348 | cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
21349 | cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
21350 | cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
21351 | cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
21352 | cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
21353 | cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
21354 | cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21355 | cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21356 | cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21357 | cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21358 | cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21359 | cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21360 | cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21361 | cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21362 | cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21363 | cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn), | |
21364 | cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn), | |
21365 | cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn), | |
21366 | cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn), | |
21367 | cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn), | |
21368 | cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn), | |
21369 | cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21370 | cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21371 | cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21372 | cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn), | |
21373 | cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn), | |
21374 | cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn), | |
21375 | cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn), | |
21376 | cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn), | |
21377 | cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn), | |
21378 | cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21379 | cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21380 | cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21381 | cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21382 | cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 | 21383 | |
c921be7d NC |
21384 | #undef ARM_VARIANT |
21385 | #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ | |
21386 | ||
21d799b5 NC |
21387 | cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc), |
21388 | cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc), | |
21389 | cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc), | |
21390 | cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn), | |
21391 | cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn), | |
21392 | cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn), | |
21393 | cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21394 | cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21395 | cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21396 | cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21397 | cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21398 | cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21399 | cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21400 | cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21401 | cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21402 | cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21403 | cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21404 | cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21405 | cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21406 | cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21407 | cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), | |
21408 | cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21409 | cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21410 | cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21411 | cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21412 | cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21413 | cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21414 | cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21415 | cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21416 | cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21417 | cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21418 | cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21419 | cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21420 | cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21421 | cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21422 | cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21423 | cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21424 | cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21425 | cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21426 | cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21427 | cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21428 | cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21429 | cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21430 | cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21431 | cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21432 | cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21433 | cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21434 | cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21435 | cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21436 | cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21437 | cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21438 | cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21439 | cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21440 | cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21441 | cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21442 | cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21443 | cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
2d447fca | 21444 | |
c921be7d NC |
21445 | #undef ARM_VARIANT |
21446 | #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */ | |
21447 | ||
21d799b5 NC |
21448 | cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), |
21449 | cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
21450 | cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
21451 | cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
21452 | cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), | |
21453 | cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
21454 | cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
21455 | cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
21456 | cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd), | |
21457 | cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn), | |
21458 | cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd), | |
21459 | cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn), | |
21460 | cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd), | |
21461 | cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn), | |
74db7efb NC |
21462 | cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd), |
21463 | cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn), | |
21464 | cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd), | |
21465 | cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn), | |
21466 | cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn), | |
21467 | cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn), | |
21468 | cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn), | |
21469 | cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn), | |
21470 | cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn), | |
21471 | cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn), | |
21d799b5 NC |
21472 | cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn), |
21473 | cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn), | |
21474 | cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn), | |
21475 | cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn), | |
74db7efb NC |
21476 | cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc), |
21477 | cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd), | |
21d799b5 NC |
21478 | cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn), |
21479 | cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn), | |
21480 | cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn), | |
21481 | cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn), | |
74db7efb NC |
21482 | cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn), |
21483 | cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn), | |
21484 | cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn), | |
21485 | cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn), | |
21486 | cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn), | |
21487 | cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn), | |
21d799b5 NC |
21488 | cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn), |
21489 | cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn), | |
74db7efb NC |
21490 | cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple), |
21491 | cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
21d799b5 NC |
21492 | cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift), |
21493 | cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
21494 | cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
21495 | cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
21496 | cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
21497 | cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
21498 | cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn), | |
21499 | cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn), | |
21500 | cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn), | |
21501 | cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn), | |
21502 | cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
21503 | cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
21504 | cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
21505 | cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
21506 | cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
21507 | cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
21508 | cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn), | |
21509 | cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn), | |
21510 | cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn), | |
21511 | cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn), | |
21512 | cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
21513 | cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
21514 | cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
21515 | cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
21516 | cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
21517 | cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
21518 | cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
21519 | cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
74db7efb NC |
21520 | cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), |
21521 | cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
21d799b5 NC |
21522 | cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), |
21523 | cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
4ed7ed8d | 21524 | |
7fadb25d SD |
21525 | /* ARMv8.5-A instructions. */ |
21526 | #undef ARM_VARIANT | |
21527 | #define ARM_VARIANT & arm_ext_sb | |
21528 | #undef THUMB_VARIANT | |
21529 | #define THUMB_VARIANT & arm_ext_sb | |
21530 | TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs), | |
21531 | ||
dad0c3bf SD |
21532 | #undef ARM_VARIANT |
21533 | #define ARM_VARIANT & arm_ext_predres | |
21534 | #undef THUMB_VARIANT | |
21535 | #define THUMB_VARIANT & arm_ext_predres | |
21536 | CE("cfprctx", e070f93, 1, (RRnpc), rd), | |
21537 | CE("dvprctx", e070fb3, 1, (RRnpc), rd), | |
21538 | CE("cpprctx", e070ff3, 1, (RRnpc), rd), | |
21539 | ||
16a1fa25 | 21540 | /* ARMv8-M instructions. */ |
4ed7ed8d TP |
21541 | #undef ARM_VARIANT |
21542 | #define ARM_VARIANT NULL | |
21543 | #undef THUMB_VARIANT | |
21544 | #define THUMB_VARIANT & arm_ext_v8m | |
cf3cf39d TP |
21545 | ToU("sg", e97fe97f, 0, (), noargs), |
21546 | ToC("blxns", 4784, 1, (RRnpc), t_blx), | |
21547 | ToC("bxns", 4704, 1, (RRnpc), t_bx), | |
21548 | ToC("tt", e840f000, 2, (RRnpc, RRnpc), tt), | |
21549 | ToC("ttt", e840f040, 2, (RRnpc, RRnpc), tt), | |
21550 | ToC("tta", e840f080, 2, (RRnpc, RRnpc), tt), | |
21551 | ToC("ttat", e840f0c0, 2, (RRnpc, RRnpc), tt), | |
16a1fa25 TP |
21552 | |
21553 | /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the | |
21554 | instructions behave as nop if no VFP is present. */ | |
21555 | #undef THUMB_VARIANT | |
21556 | #define THUMB_VARIANT & arm_ext_v8m_main | |
cf3cf39d TP |
21557 | ToC("vlldm", ec300a00, 1, (RRnpc), rn), |
21558 | ToC("vlstm", ec200a00, 1, (RRnpc), rn), | |
c19d1205 ZW |
21559 | }; |
21560 | #undef ARM_VARIANT | |
21561 | #undef THUMB_VARIANT | |
21562 | #undef TCE | |
c19d1205 ZW |
21563 | #undef TUE |
21564 | #undef TUF | |
21565 | #undef TCC | |
8f06b2d8 | 21566 | #undef cCE |
e3cb604e PB |
21567 | #undef cCL |
21568 | #undef C3E | |
c19d1205 ZW |
21569 | #undef CE |
21570 | #undef CM | |
21571 | #undef UE | |
21572 | #undef UF | |
21573 | #undef UT | |
5287ad62 JB |
21574 | #undef NUF |
21575 | #undef nUF | |
21576 | #undef NCE | |
21577 | #undef nCE | |
c19d1205 ZW |
21578 | #undef OPS0 |
21579 | #undef OPS1 | |
21580 | #undef OPS2 | |
21581 | #undef OPS3 | |
21582 | #undef OPS4 | |
21583 | #undef OPS5 | |
21584 | #undef OPS6 | |
21585 | #undef do_0 | |
21586 | \f | |
21587 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 21588 | |
c19d1205 ZW |
21589 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
21590 | for use in the a.out file, and stores them in the array pointed to by buf. | |
21591 | This knows about the endian-ness of the target machine and does | |
21592 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
21593 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
21594 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 21595 | |
c19d1205 ZW |
21596 | void |
21597 | md_number_to_chars (char * buf, valueT val, int n) | |
21598 | { | |
21599 | if (target_big_endian) | |
21600 | number_to_chars_bigendian (buf, val, n); | |
21601 | else | |
21602 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
21603 | } |
21604 | ||
c19d1205 ZW |
21605 | static valueT |
21606 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 21607 | { |
c19d1205 ZW |
21608 | valueT result = 0; |
21609 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 21610 | |
c19d1205 | 21611 | if (target_big_endian) |
b99bd4ef | 21612 | { |
c19d1205 ZW |
21613 | while (n--) |
21614 | { | |
21615 | result <<= 8; | |
21616 | result |= (*where++ & 255); | |
21617 | } | |
b99bd4ef | 21618 | } |
c19d1205 | 21619 | else |
b99bd4ef | 21620 | { |
c19d1205 ZW |
21621 | while (n--) |
21622 | { | |
21623 | result <<= 8; | |
21624 | result |= (where[n] & 255); | |
21625 | } | |
bfae80f2 | 21626 | } |
b99bd4ef | 21627 | |
c19d1205 | 21628 | return result; |
bfae80f2 | 21629 | } |
b99bd4ef | 21630 | |
c19d1205 | 21631 | /* MD interface: Sections. */ |
b99bd4ef | 21632 | |
fa94de6b RM |
21633 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
21634 | that an rs_machine_dependent frag may reach. */ | |
21635 | ||
21636 | unsigned int | |
21637 | arm_frag_max_var (fragS *fragp) | |
21638 | { | |
21639 | /* We only use rs_machine_dependent for variable-size Thumb instructions, | |
21640 | which are either THUMB_SIZE (2) or INSN_SIZE (4). | |
21641 | ||
21642 | Note that we generate relaxable instructions even for cases that don't | |
21643 | really need it, like an immediate that's a trivial constant. So we're | |
21644 | overestimating the instruction size for some of those cases. Rather | |
21645 | than putting more intelligence here, it would probably be better to | |
21646 | avoid generating a relaxation frag in the first place when it can be | |
21647 | determined up front that a short instruction will suffice. */ | |
21648 | ||
21649 | gas_assert (fragp->fr_type == rs_machine_dependent); | |
21650 | return INSN_SIZE; | |
21651 | } | |
21652 | ||
0110f2b8 PB |
21653 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
21654 | 2 bytes. */ | |
21655 | ||
c19d1205 | 21656 | int |
0110f2b8 | 21657 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
21658 | segT segtype ATTRIBUTE_UNUSED) |
21659 | { | |
0110f2b8 PB |
21660 | fragp->fr_var = 2; |
21661 | return 2; | |
21662 | } | |
21663 | ||
21664 | /* Convert a machine dependent frag. */ | |
21665 | ||
21666 | void | |
21667 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
21668 | { | |
21669 | unsigned long insn; | |
21670 | unsigned long old_op; | |
21671 | char *buf; | |
21672 | expressionS exp; | |
21673 | fixS *fixp; | |
21674 | int reloc_type; | |
21675 | int pc_rel; | |
21676 | int opcode; | |
21677 | ||
21678 | buf = fragp->fr_literal + fragp->fr_fix; | |
21679 | ||
21680 | old_op = bfd_get_16(abfd, buf); | |
5f4273c7 NC |
21681 | if (fragp->fr_symbol) |
21682 | { | |
0110f2b8 PB |
21683 | exp.X_op = O_symbol; |
21684 | exp.X_add_symbol = fragp->fr_symbol; | |
5f4273c7 NC |
21685 | } |
21686 | else | |
21687 | { | |
0110f2b8 | 21688 | exp.X_op = O_constant; |
5f4273c7 | 21689 | } |
0110f2b8 PB |
21690 | exp.X_add_number = fragp->fr_offset; |
21691 | opcode = fragp->fr_subtype; | |
21692 | switch (opcode) | |
21693 | { | |
21694 | case T_MNEM_ldr_pc: | |
21695 | case T_MNEM_ldr_pc2: | |
21696 | case T_MNEM_ldr_sp: | |
21697 | case T_MNEM_str_sp: | |
21698 | case T_MNEM_ldr: | |
21699 | case T_MNEM_ldrb: | |
21700 | case T_MNEM_ldrh: | |
21701 | case T_MNEM_str: | |
21702 | case T_MNEM_strb: | |
21703 | case T_MNEM_strh: | |
21704 | if (fragp->fr_var == 4) | |
21705 | { | |
5f4273c7 | 21706 | insn = THUMB_OP32 (opcode); |
0110f2b8 PB |
21707 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) |
21708 | { | |
21709 | insn |= (old_op & 0x700) << 4; | |
21710 | } | |
21711 | else | |
21712 | { | |
21713 | insn |= (old_op & 7) << 12; | |
21714 | insn |= (old_op & 0x38) << 13; | |
21715 | } | |
21716 | insn |= 0x00000c00; | |
21717 | put_thumb32_insn (buf, insn); | |
21718 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
21719 | } | |
21720 | else | |
21721 | { | |
21722 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
21723 | } | |
21724 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
21725 | break; | |
21726 | case T_MNEM_adr: | |
21727 | if (fragp->fr_var == 4) | |
21728 | { | |
21729 | insn = THUMB_OP32 (opcode); | |
21730 | insn |= (old_op & 0xf0) << 4; | |
21731 | put_thumb32_insn (buf, insn); | |
21732 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
21733 | } | |
21734 | else | |
21735 | { | |
21736 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
21737 | exp.X_add_number -= 4; | |
21738 | } | |
21739 | pc_rel = 1; | |
21740 | break; | |
21741 | case T_MNEM_mov: | |
21742 | case T_MNEM_movs: | |
21743 | case T_MNEM_cmp: | |
21744 | case T_MNEM_cmn: | |
21745 | if (fragp->fr_var == 4) | |
21746 | { | |
21747 | int r0off = (opcode == T_MNEM_mov | |
21748 | || opcode == T_MNEM_movs) ? 0 : 8; | |
21749 | insn = THUMB_OP32 (opcode); | |
21750 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
21751 | insn |= (old_op & 0x700) << r0off; | |
21752 | put_thumb32_insn (buf, insn); | |
21753 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
21754 | } | |
21755 | else | |
21756 | { | |
21757 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
21758 | } | |
21759 | pc_rel = 0; | |
21760 | break; | |
21761 | case T_MNEM_b: | |
21762 | if (fragp->fr_var == 4) | |
21763 | { | |
21764 | insn = THUMB_OP32(opcode); | |
21765 | put_thumb32_insn (buf, insn); | |
21766 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
21767 | } | |
21768 | else | |
21769 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
21770 | pc_rel = 1; | |
21771 | break; | |
21772 | case T_MNEM_bcond: | |
21773 | if (fragp->fr_var == 4) | |
21774 | { | |
21775 | insn = THUMB_OP32(opcode); | |
21776 | insn |= (old_op & 0xf00) << 14; | |
21777 | put_thumb32_insn (buf, insn); | |
21778 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
21779 | } | |
21780 | else | |
21781 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
21782 | pc_rel = 1; | |
21783 | break; | |
21784 | case T_MNEM_add_sp: | |
21785 | case T_MNEM_add_pc: | |
21786 | case T_MNEM_inc_sp: | |
21787 | case T_MNEM_dec_sp: | |
21788 | if (fragp->fr_var == 4) | |
21789 | { | |
21790 | /* ??? Choose between add and addw. */ | |
21791 | insn = THUMB_OP32 (opcode); | |
21792 | insn |= (old_op & 0xf0) << 4; | |
21793 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
21794 | if (opcode == T_MNEM_add_pc) |
21795 | reloc_type = BFD_RELOC_ARM_T32_IMM12; | |
21796 | else | |
21797 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
0110f2b8 PB |
21798 | } |
21799 | else | |
21800 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
21801 | pc_rel = 0; | |
21802 | break; | |
21803 | ||
21804 | case T_MNEM_addi: | |
21805 | case T_MNEM_addis: | |
21806 | case T_MNEM_subi: | |
21807 | case T_MNEM_subis: | |
21808 | if (fragp->fr_var == 4) | |
21809 | { | |
21810 | insn = THUMB_OP32 (opcode); | |
21811 | insn |= (old_op & 0xf0) << 4; | |
21812 | insn |= (old_op & 0xf) << 16; | |
21813 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
21814 | if (insn & (1 << 20)) |
21815 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
21816 | else | |
21817 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
0110f2b8 PB |
21818 | } |
21819 | else | |
21820 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
21821 | pc_rel = 0; | |
21822 | break; | |
21823 | default: | |
5f4273c7 | 21824 | abort (); |
0110f2b8 PB |
21825 | } |
21826 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
21d799b5 | 21827 | (enum bfd_reloc_code_real) reloc_type); |
0110f2b8 PB |
21828 | fixp->fx_file = fragp->fr_file; |
21829 | fixp->fx_line = fragp->fr_line; | |
21830 | fragp->fr_fix += fragp->fr_var; | |
3cfdb781 TG |
21831 | |
21832 | /* Set whether we use thumb-2 ISA based on final relaxation results. */ | |
21833 | if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected () | |
21834 | && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2)) | |
21835 | ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2); | |
0110f2b8 PB |
21836 | } |
21837 | ||
21838 | /* Return the size of a relaxable immediate operand instruction. | |
21839 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
21840 | static int | |
21841 | relax_immediate (fragS *fragp, int size, int shift) | |
21842 | { | |
21843 | offsetT offset; | |
21844 | offsetT mask; | |
21845 | offsetT low; | |
21846 | ||
21847 | /* ??? Should be able to do better than this. */ | |
21848 | if (fragp->fr_symbol) | |
21849 | return 4; | |
21850 | ||
21851 | low = (1 << shift) - 1; | |
21852 | mask = (1 << (shift + size)) - (1 << shift); | |
21853 | offset = fragp->fr_offset; | |
21854 | /* Force misaligned offsets to 32-bit variant. */ | |
21855 | if (offset & low) | |
5e77afaa | 21856 | return 4; |
0110f2b8 PB |
21857 | if (offset & ~mask) |
21858 | return 4; | |
21859 | return 2; | |
21860 | } | |
21861 | ||
5e77afaa PB |
21862 | /* Get the address of a symbol during relaxation. */ |
21863 | static addressT | |
5f4273c7 | 21864 | relaxed_symbol_addr (fragS *fragp, long stretch) |
5e77afaa PB |
21865 | { |
21866 | fragS *sym_frag; | |
21867 | addressT addr; | |
21868 | symbolS *sym; | |
21869 | ||
21870 | sym = fragp->fr_symbol; | |
21871 | sym_frag = symbol_get_frag (sym); | |
21872 | know (S_GET_SEGMENT (sym) != absolute_section | |
21873 | || sym_frag == &zero_address_frag); | |
21874 | addr = S_GET_VALUE (sym) + fragp->fr_offset; | |
21875 | ||
21876 | /* If frag has yet to be reached on this pass, assume it will | |
21877 | move by STRETCH just as we did. If this is not so, it will | |
21878 | be because some frag between grows, and that will force | |
21879 | another pass. */ | |
21880 | ||
21881 | if (stretch != 0 | |
21882 | && sym_frag->relax_marker != fragp->relax_marker) | |
4396b686 PB |
21883 | { |
21884 | fragS *f; | |
21885 | ||
21886 | /* Adjust stretch for any alignment frag. Note that if have | |
21887 | been expanding the earlier code, the symbol may be | |
21888 | defined in what appears to be an earlier frag. FIXME: | |
21889 | This doesn't handle the fr_subtype field, which specifies | |
21890 | a maximum number of bytes to skip when doing an | |
21891 | alignment. */ | |
21892 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
21893 | { | |
21894 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
21895 | { | |
21896 | if (stretch < 0) | |
21897 | stretch = - ((- stretch) | |
21898 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
21899 | else | |
21900 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
21901 | if (stretch == 0) | |
21902 | break; | |
21903 | } | |
21904 | } | |
21905 | if (f != NULL) | |
21906 | addr += stretch; | |
21907 | } | |
5e77afaa PB |
21908 | |
21909 | return addr; | |
21910 | } | |
21911 | ||
0110f2b8 PB |
21912 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative |
21913 | load. */ | |
21914 | static int | |
5e77afaa | 21915 | relax_adr (fragS *fragp, asection *sec, long stretch) |
0110f2b8 PB |
21916 | { |
21917 | addressT addr; | |
21918 | offsetT val; | |
21919 | ||
21920 | /* Assume worst case for symbols not known to be in the same section. */ | |
974da60d NC |
21921 | if (fragp->fr_symbol == NULL |
21922 | || !S_IS_DEFINED (fragp->fr_symbol) | |
77db8e2e NC |
21923 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
21924 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
21925 | return 4; |
21926 | ||
5f4273c7 | 21927 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
21928 | addr = fragp->fr_address + fragp->fr_fix; |
21929 | addr = (addr + 4) & ~3; | |
5e77afaa | 21930 | /* Force misaligned targets to 32-bit variant. */ |
0110f2b8 | 21931 | if (val & 3) |
5e77afaa | 21932 | return 4; |
0110f2b8 PB |
21933 | val -= addr; |
21934 | if (val < 0 || val > 1020) | |
21935 | return 4; | |
21936 | return 2; | |
21937 | } | |
21938 | ||
21939 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
21940 | static int | |
21941 | relax_addsub (fragS *fragp, asection *sec) | |
21942 | { | |
21943 | char *buf; | |
21944 | int op; | |
21945 | ||
21946 | buf = fragp->fr_literal + fragp->fr_fix; | |
21947 | op = bfd_get_16(sec->owner, buf); | |
21948 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
21949 | return relax_immediate (fragp, 8, 0); | |
21950 | else | |
21951 | return relax_immediate (fragp, 3, 0); | |
21952 | } | |
21953 | ||
e83a675f RE |
21954 | /* Return TRUE iff the definition of symbol S could be pre-empted |
21955 | (overridden) at link or load time. */ | |
21956 | static bfd_boolean | |
21957 | symbol_preemptible (symbolS *s) | |
21958 | { | |
21959 | /* Weak symbols can always be pre-empted. */ | |
21960 | if (S_IS_WEAK (s)) | |
21961 | return TRUE; | |
21962 | ||
21963 | /* Non-global symbols cannot be pre-empted. */ | |
21964 | if (! S_IS_EXTERNAL (s)) | |
21965 | return FALSE; | |
21966 | ||
21967 | #ifdef OBJ_ELF | |
21968 | /* In ELF, a global symbol can be marked protected, or private. In that | |
21969 | case it can't be pre-empted (other definitions in the same link unit | |
21970 | would violate the ODR). */ | |
21971 | if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT) | |
21972 | return FALSE; | |
21973 | #endif | |
21974 | ||
21975 | /* Other global symbols might be pre-empted. */ | |
21976 | return TRUE; | |
21977 | } | |
0110f2b8 PB |
21978 | |
21979 | /* Return the size of a relaxable branch instruction. BITS is the | |
21980 | size of the offset field in the narrow instruction. */ | |
21981 | ||
21982 | static int | |
5e77afaa | 21983 | relax_branch (fragS *fragp, asection *sec, int bits, long stretch) |
0110f2b8 PB |
21984 | { |
21985 | addressT addr; | |
21986 | offsetT val; | |
21987 | offsetT limit; | |
21988 | ||
21989 | /* Assume worst case for symbols not known to be in the same section. */ | |
5f4273c7 | 21990 | if (!S_IS_DEFINED (fragp->fr_symbol) |
77db8e2e NC |
21991 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
21992 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
21993 | return 4; |
21994 | ||
267bf995 | 21995 | #ifdef OBJ_ELF |
e83a675f | 21996 | /* A branch to a function in ARM state will require interworking. */ |
267bf995 RR |
21997 | if (S_IS_DEFINED (fragp->fr_symbol) |
21998 | && ARM_IS_FUNC (fragp->fr_symbol)) | |
21999 | return 4; | |
e83a675f | 22000 | #endif |
0d9b4b55 | 22001 | |
e83a675f | 22002 | if (symbol_preemptible (fragp->fr_symbol)) |
0d9b4b55 | 22003 | return 4; |
267bf995 | 22004 | |
5f4273c7 | 22005 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
22006 | addr = fragp->fr_address + fragp->fr_fix + 4; |
22007 | val -= addr; | |
22008 | ||
22009 | /* Offset is a signed value *2 */ | |
22010 | limit = 1 << bits; | |
22011 | if (val >= limit || val < -limit) | |
22012 | return 4; | |
22013 | return 2; | |
22014 | } | |
22015 | ||
22016 | ||
22017 | /* Relax a machine dependent frag. This returns the amount by which | |
22018 | the current size of the frag should change. */ | |
22019 | ||
22020 | int | |
5e77afaa | 22021 | arm_relax_frag (asection *sec, fragS *fragp, long stretch) |
0110f2b8 PB |
22022 | { |
22023 | int oldsize; | |
22024 | int newsize; | |
22025 | ||
22026 | oldsize = fragp->fr_var; | |
22027 | switch (fragp->fr_subtype) | |
22028 | { | |
22029 | case T_MNEM_ldr_pc2: | |
5f4273c7 | 22030 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
22031 | break; |
22032 | case T_MNEM_ldr_pc: | |
22033 | case T_MNEM_ldr_sp: | |
22034 | case T_MNEM_str_sp: | |
5f4273c7 | 22035 | newsize = relax_immediate (fragp, 8, 2); |
0110f2b8 PB |
22036 | break; |
22037 | case T_MNEM_ldr: | |
22038 | case T_MNEM_str: | |
5f4273c7 | 22039 | newsize = relax_immediate (fragp, 5, 2); |
0110f2b8 PB |
22040 | break; |
22041 | case T_MNEM_ldrh: | |
22042 | case T_MNEM_strh: | |
5f4273c7 | 22043 | newsize = relax_immediate (fragp, 5, 1); |
0110f2b8 PB |
22044 | break; |
22045 | case T_MNEM_ldrb: | |
22046 | case T_MNEM_strb: | |
5f4273c7 | 22047 | newsize = relax_immediate (fragp, 5, 0); |
0110f2b8 PB |
22048 | break; |
22049 | case T_MNEM_adr: | |
5f4273c7 | 22050 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
22051 | break; |
22052 | case T_MNEM_mov: | |
22053 | case T_MNEM_movs: | |
22054 | case T_MNEM_cmp: | |
22055 | case T_MNEM_cmn: | |
5f4273c7 | 22056 | newsize = relax_immediate (fragp, 8, 0); |
0110f2b8 PB |
22057 | break; |
22058 | case T_MNEM_b: | |
5f4273c7 | 22059 | newsize = relax_branch (fragp, sec, 11, stretch); |
0110f2b8 PB |
22060 | break; |
22061 | case T_MNEM_bcond: | |
5f4273c7 | 22062 | newsize = relax_branch (fragp, sec, 8, stretch); |
0110f2b8 PB |
22063 | break; |
22064 | case T_MNEM_add_sp: | |
22065 | case T_MNEM_add_pc: | |
22066 | newsize = relax_immediate (fragp, 8, 2); | |
22067 | break; | |
22068 | case T_MNEM_inc_sp: | |
22069 | case T_MNEM_dec_sp: | |
22070 | newsize = relax_immediate (fragp, 7, 2); | |
22071 | break; | |
22072 | case T_MNEM_addi: | |
22073 | case T_MNEM_addis: | |
22074 | case T_MNEM_subi: | |
22075 | case T_MNEM_subis: | |
22076 | newsize = relax_addsub (fragp, sec); | |
22077 | break; | |
22078 | default: | |
5f4273c7 | 22079 | abort (); |
0110f2b8 | 22080 | } |
5e77afaa PB |
22081 | |
22082 | fragp->fr_var = newsize; | |
22083 | /* Freeze wide instructions that are at or before the same location as | |
22084 | in the previous pass. This avoids infinite loops. | |
5f4273c7 NC |
22085 | Don't freeze them unconditionally because targets may be artificially |
22086 | misaligned by the expansion of preceding frags. */ | |
5e77afaa | 22087 | if (stretch <= 0 && newsize > 2) |
0110f2b8 | 22088 | { |
0110f2b8 | 22089 | md_convert_frag (sec->owner, sec, fragp); |
5f4273c7 | 22090 | frag_wane (fragp); |
0110f2b8 | 22091 | } |
5e77afaa | 22092 | |
0110f2b8 | 22093 | return newsize - oldsize; |
c19d1205 | 22094 | } |
b99bd4ef | 22095 | |
c19d1205 | 22096 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 22097 | |
c19d1205 ZW |
22098 | valueT |
22099 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
22100 | valueT size) | |
22101 | { | |
6844c0cc | 22102 | return size; |
bfae80f2 | 22103 | } |
b99bd4ef | 22104 | |
c19d1205 ZW |
22105 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
22106 | of an rs_align_code fragment. */ | |
22107 | ||
22108 | void | |
22109 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 22110 | { |
d9235011 | 22111 | static unsigned char const arm_noop[2][2][4] = |
e7495e45 NS |
22112 | { |
22113 | { /* ARMv1 */ | |
22114 | {0x00, 0x00, 0xa0, 0xe1}, /* LE */ | |
22115 | {0xe1, 0xa0, 0x00, 0x00}, /* BE */ | |
22116 | }, | |
22117 | { /* ARMv6k */ | |
22118 | {0x00, 0xf0, 0x20, 0xe3}, /* LE */ | |
22119 | {0xe3, 0x20, 0xf0, 0x00}, /* BE */ | |
22120 | }, | |
22121 | }; | |
d9235011 | 22122 | static unsigned char const thumb_noop[2][2][2] = |
e7495e45 NS |
22123 | { |
22124 | { /* Thumb-1 */ | |
22125 | {0xc0, 0x46}, /* LE */ | |
22126 | {0x46, 0xc0}, /* BE */ | |
22127 | }, | |
22128 | { /* Thumb-2 */ | |
22129 | {0x00, 0xbf}, /* LE */ | |
22130 | {0xbf, 0x00} /* BE */ | |
22131 | } | |
22132 | }; | |
d9235011 | 22133 | static unsigned char const wide_thumb_noop[2][4] = |
e7495e45 NS |
22134 | { /* Wide Thumb-2 */ |
22135 | {0xaf, 0xf3, 0x00, 0x80}, /* LE */ | |
22136 | {0xf3, 0xaf, 0x80, 0x00}, /* BE */ | |
22137 | }; | |
c921be7d | 22138 | |
e7495e45 | 22139 | unsigned bytes, fix, noop_size; |
c19d1205 | 22140 | char * p; |
d9235011 TS |
22141 | const unsigned char * noop; |
22142 | const unsigned char *narrow_noop = NULL; | |
cd000bff DJ |
22143 | #ifdef OBJ_ELF |
22144 | enum mstate state; | |
22145 | #endif | |
bfae80f2 | 22146 | |
c19d1205 | 22147 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
22148 | return; |
22149 | ||
c19d1205 ZW |
22150 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
22151 | p = fragP->fr_literal + fragP->fr_fix; | |
22152 | fix = 0; | |
bfae80f2 | 22153 | |
c19d1205 ZW |
22154 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
22155 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 22156 | |
cd000bff | 22157 | gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0); |
8dc2430f | 22158 | |
cd000bff | 22159 | if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED)) |
a737bd4d | 22160 | { |
7f78eb34 JW |
22161 | if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0] |
22162 | ? selected_cpu : arm_arch_none, arm_ext_v6t2)) | |
e7495e45 NS |
22163 | { |
22164 | narrow_noop = thumb_noop[1][target_big_endian]; | |
22165 | noop = wide_thumb_noop[target_big_endian]; | |
22166 | } | |
c19d1205 | 22167 | else |
e7495e45 NS |
22168 | noop = thumb_noop[0][target_big_endian]; |
22169 | noop_size = 2; | |
cd000bff DJ |
22170 | #ifdef OBJ_ELF |
22171 | state = MAP_THUMB; | |
22172 | #endif | |
7ed4c4c5 NC |
22173 | } |
22174 | else | |
22175 | { | |
7f78eb34 JW |
22176 | noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0] |
22177 | ? selected_cpu : arm_arch_none, | |
22178 | arm_ext_v6k) != 0] | |
e7495e45 NS |
22179 | [target_big_endian]; |
22180 | noop_size = 4; | |
cd000bff DJ |
22181 | #ifdef OBJ_ELF |
22182 | state = MAP_ARM; | |
22183 | #endif | |
7ed4c4c5 | 22184 | } |
c921be7d | 22185 | |
e7495e45 | 22186 | fragP->fr_var = noop_size; |
c921be7d | 22187 | |
c19d1205 | 22188 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 22189 | { |
c19d1205 | 22190 | fix = bytes & (noop_size - 1); |
cd000bff DJ |
22191 | #ifdef OBJ_ELF |
22192 | insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix); | |
22193 | #endif | |
c19d1205 ZW |
22194 | memset (p, 0, fix); |
22195 | p += fix; | |
22196 | bytes -= fix; | |
a737bd4d | 22197 | } |
a737bd4d | 22198 | |
e7495e45 NS |
22199 | if (narrow_noop) |
22200 | { | |
22201 | if (bytes & noop_size) | |
22202 | { | |
22203 | /* Insert a narrow noop. */ | |
22204 | memcpy (p, narrow_noop, noop_size); | |
22205 | p += noop_size; | |
22206 | bytes -= noop_size; | |
22207 | fix += noop_size; | |
22208 | } | |
22209 | ||
22210 | /* Use wide noops for the remainder */ | |
22211 | noop_size = 4; | |
22212 | } | |
22213 | ||
c19d1205 | 22214 | while (bytes >= noop_size) |
a737bd4d | 22215 | { |
c19d1205 ZW |
22216 | memcpy (p, noop, noop_size); |
22217 | p += noop_size; | |
22218 | bytes -= noop_size; | |
22219 | fix += noop_size; | |
a737bd4d NC |
22220 | } |
22221 | ||
c19d1205 | 22222 | fragP->fr_fix += fix; |
a737bd4d NC |
22223 | } |
22224 | ||
c19d1205 ZW |
22225 | /* Called from md_do_align. Used to create an alignment |
22226 | frag in a code section. */ | |
22227 | ||
22228 | void | |
22229 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 22230 | { |
c19d1205 | 22231 | char * p; |
7ed4c4c5 | 22232 | |
c19d1205 | 22233 | /* We assume that there will never be a requirement |
6ec8e702 | 22234 | to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */ |
c19d1205 | 22235 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) |
6ec8e702 NC |
22236 | { |
22237 | char err_msg[128]; | |
22238 | ||
fa94de6b | 22239 | sprintf (err_msg, |
477330fc RM |
22240 | _("alignments greater than %d bytes not supported in .text sections."), |
22241 | MAX_MEM_FOR_RS_ALIGN_CODE + 1); | |
20203fb9 | 22242 | as_fatal ("%s", err_msg); |
6ec8e702 | 22243 | } |
bfae80f2 | 22244 | |
c19d1205 ZW |
22245 | p = frag_var (rs_align_code, |
22246 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
22247 | 1, | |
22248 | (relax_substateT) max, | |
22249 | (symbolS *) NULL, | |
22250 | (offsetT) n, | |
22251 | (char *) NULL); | |
22252 | *p = 0; | |
22253 | } | |
bfae80f2 | 22254 | |
8dc2430f NC |
22255 | /* Perform target specific initialisation of a frag. |
22256 | Note - despite the name this initialisation is not done when the frag | |
22257 | is created, but only when its type is assigned. A frag can be created | |
22258 | and used a long time before its type is set, so beware of assuming that | |
33eaf5de | 22259 | this initialisation is performed first. */ |
bfae80f2 | 22260 | |
cd000bff DJ |
22261 | #ifndef OBJ_ELF |
22262 | void | |
22263 | arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED) | |
22264 | { | |
22265 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
2e98972e | 22266 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
cd000bff DJ |
22267 | } |
22268 | ||
22269 | #else /* OBJ_ELF is defined. */ | |
c19d1205 | 22270 | void |
cd000bff | 22271 | arm_init_frag (fragS * fragP, int max_chars) |
c19d1205 | 22272 | { |
e8d84ca1 | 22273 | bfd_boolean frag_thumb_mode; |
b968d18a | 22274 | |
8dc2430f NC |
22275 | /* If the current ARM vs THUMB mode has not already |
22276 | been recorded into this frag then do so now. */ | |
cd000bff | 22277 | if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0) |
b968d18a JW |
22278 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
22279 | ||
e8d84ca1 NC |
22280 | /* PR 21809: Do not set a mapping state for debug sections |
22281 | - it just confuses other tools. */ | |
22282 | if (bfd_get_section_flags (NULL, now_seg) & SEC_DEBUGGING) | |
22283 | return; | |
22284 | ||
b968d18a | 22285 | frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED; |
cd000bff | 22286 | |
f9c1b181 RL |
22287 | /* Record a mapping symbol for alignment frags. We will delete this |
22288 | later if the alignment ends up empty. */ | |
22289 | switch (fragP->fr_type) | |
22290 | { | |
22291 | case rs_align: | |
22292 | case rs_align_test: | |
22293 | case rs_fill: | |
22294 | mapping_state_2 (MAP_DATA, max_chars); | |
22295 | break; | |
22296 | case rs_align_code: | |
b968d18a | 22297 | mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars); |
f9c1b181 RL |
22298 | break; |
22299 | default: | |
22300 | break; | |
cd000bff | 22301 | } |
bfae80f2 RE |
22302 | } |
22303 | ||
c19d1205 ZW |
22304 | /* When we change sections we need to issue a new mapping symbol. */ |
22305 | ||
22306 | void | |
22307 | arm_elf_change_section (void) | |
bfae80f2 | 22308 | { |
c19d1205 ZW |
22309 | /* Link an unlinked unwind index table section to the .text section. */ |
22310 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
22311 | && elf_linked_to_section (now_seg) == NULL) | |
22312 | elf_linked_to_section (now_seg) = text_section; | |
bfae80f2 RE |
22313 | } |
22314 | ||
c19d1205 ZW |
22315 | int |
22316 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 22317 | { |
c19d1205 ZW |
22318 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
22319 | return SHT_ARM_EXIDX; | |
e45d0630 | 22320 | |
c19d1205 ZW |
22321 | return -1; |
22322 | } | |
22323 | \f | |
22324 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 22325 | |
c19d1205 | 22326 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 22327 | |
5f4273c7 | 22328 | /* Generate any deferred unwind frame offset. */ |
e45d0630 | 22329 | |
bfae80f2 | 22330 | static void |
c19d1205 | 22331 | flush_pending_unwind (void) |
bfae80f2 | 22332 | { |
c19d1205 | 22333 | offsetT offset; |
bfae80f2 | 22334 | |
c19d1205 ZW |
22335 | offset = unwind.pending_offset; |
22336 | unwind.pending_offset = 0; | |
22337 | if (offset != 0) | |
22338 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
22339 | } |
22340 | ||
c19d1205 ZW |
22341 | /* Add an opcode to this list for this function. Two-byte opcodes should |
22342 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
22343 | order. */ | |
22344 | ||
bfae80f2 | 22345 | static void |
c19d1205 | 22346 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 22347 | { |
c19d1205 ZW |
22348 | /* Add any deferred stack adjustment. */ |
22349 | if (unwind.pending_offset) | |
22350 | flush_pending_unwind (); | |
bfae80f2 | 22351 | |
c19d1205 | 22352 | unwind.sp_restored = 0; |
bfae80f2 | 22353 | |
c19d1205 | 22354 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 22355 | { |
c19d1205 ZW |
22356 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
22357 | if (unwind.opcodes) | |
325801bd TS |
22358 | unwind.opcodes = XRESIZEVEC (unsigned char, unwind.opcodes, |
22359 | unwind.opcode_alloc); | |
c19d1205 | 22360 | else |
325801bd | 22361 | unwind.opcodes = XNEWVEC (unsigned char, unwind.opcode_alloc); |
bfae80f2 | 22362 | } |
c19d1205 | 22363 | while (length > 0) |
bfae80f2 | 22364 | { |
c19d1205 ZW |
22365 | length--; |
22366 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
22367 | op >>= 8; | |
22368 | unwind.opcode_count++; | |
bfae80f2 | 22369 | } |
bfae80f2 RE |
22370 | } |
22371 | ||
c19d1205 ZW |
22372 | /* Add unwind opcodes to adjust the stack pointer. */ |
22373 | ||
bfae80f2 | 22374 | static void |
c19d1205 | 22375 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 22376 | { |
c19d1205 | 22377 | valueT op; |
bfae80f2 | 22378 | |
c19d1205 | 22379 | if (offset > 0x200) |
bfae80f2 | 22380 | { |
c19d1205 ZW |
22381 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
22382 | char bytes[5]; | |
22383 | int n; | |
22384 | valueT o; | |
bfae80f2 | 22385 | |
c19d1205 ZW |
22386 | /* Long form: 0xb2, uleb128. */ |
22387 | /* This might not fit in a word so add the individual bytes, | |
22388 | remembering the list is built in reverse order. */ | |
22389 | o = (valueT) ((offset - 0x204) >> 2); | |
22390 | if (o == 0) | |
22391 | add_unwind_opcode (0, 1); | |
bfae80f2 | 22392 | |
c19d1205 ZW |
22393 | /* Calculate the uleb128 encoding of the offset. */ |
22394 | n = 0; | |
22395 | while (o) | |
22396 | { | |
22397 | bytes[n] = o & 0x7f; | |
22398 | o >>= 7; | |
22399 | if (o) | |
22400 | bytes[n] |= 0x80; | |
22401 | n++; | |
22402 | } | |
22403 | /* Add the insn. */ | |
22404 | for (; n; n--) | |
22405 | add_unwind_opcode (bytes[n - 1], 1); | |
22406 | add_unwind_opcode (0xb2, 1); | |
22407 | } | |
22408 | else if (offset > 0x100) | |
bfae80f2 | 22409 | { |
c19d1205 ZW |
22410 | /* Two short opcodes. */ |
22411 | add_unwind_opcode (0x3f, 1); | |
22412 | op = (offset - 0x104) >> 2; | |
22413 | add_unwind_opcode (op, 1); | |
bfae80f2 | 22414 | } |
c19d1205 ZW |
22415 | else if (offset > 0) |
22416 | { | |
22417 | /* Short opcode. */ | |
22418 | op = (offset - 4) >> 2; | |
22419 | add_unwind_opcode (op, 1); | |
22420 | } | |
22421 | else if (offset < 0) | |
bfae80f2 | 22422 | { |
c19d1205 ZW |
22423 | offset = -offset; |
22424 | while (offset > 0x100) | |
bfae80f2 | 22425 | { |
c19d1205 ZW |
22426 | add_unwind_opcode (0x7f, 1); |
22427 | offset -= 0x100; | |
bfae80f2 | 22428 | } |
c19d1205 ZW |
22429 | op = ((offset - 4) >> 2) | 0x40; |
22430 | add_unwind_opcode (op, 1); | |
bfae80f2 | 22431 | } |
bfae80f2 RE |
22432 | } |
22433 | ||
c19d1205 | 22434 | /* Finish the list of unwind opcodes for this function. */ |
0198d5e6 | 22435 | |
c19d1205 ZW |
22436 | static void |
22437 | finish_unwind_opcodes (void) | |
bfae80f2 | 22438 | { |
c19d1205 | 22439 | valueT op; |
bfae80f2 | 22440 | |
c19d1205 | 22441 | if (unwind.fp_used) |
bfae80f2 | 22442 | { |
708587a4 | 22443 | /* Adjust sp as necessary. */ |
c19d1205 ZW |
22444 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; |
22445 | flush_pending_unwind (); | |
bfae80f2 | 22446 | |
c19d1205 ZW |
22447 | /* After restoring sp from the frame pointer. */ |
22448 | op = 0x90 | unwind.fp_reg; | |
22449 | add_unwind_opcode (op, 1); | |
22450 | } | |
22451 | else | |
22452 | flush_pending_unwind (); | |
bfae80f2 RE |
22453 | } |
22454 | ||
bfae80f2 | 22455 | |
c19d1205 ZW |
22456 | /* Start an exception table entry. If idx is nonzero this is an index table |
22457 | entry. */ | |
bfae80f2 RE |
22458 | |
22459 | static void | |
c19d1205 | 22460 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 22461 | { |
c19d1205 ZW |
22462 | const char * text_name; |
22463 | const char * prefix; | |
22464 | const char * prefix_once; | |
22465 | const char * group_name; | |
c19d1205 | 22466 | char * sec_name; |
c19d1205 ZW |
22467 | int type; |
22468 | int flags; | |
22469 | int linkonce; | |
bfae80f2 | 22470 | |
c19d1205 | 22471 | if (idx) |
bfae80f2 | 22472 | { |
c19d1205 ZW |
22473 | prefix = ELF_STRING_ARM_unwind; |
22474 | prefix_once = ELF_STRING_ARM_unwind_once; | |
22475 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 22476 | } |
c19d1205 | 22477 | else |
bfae80f2 | 22478 | { |
c19d1205 ZW |
22479 | prefix = ELF_STRING_ARM_unwind_info; |
22480 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
22481 | type = SHT_PROGBITS; | |
bfae80f2 RE |
22482 | } |
22483 | ||
c19d1205 ZW |
22484 | text_name = segment_name (text_seg); |
22485 | if (streq (text_name, ".text")) | |
22486 | text_name = ""; | |
22487 | ||
22488 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
22489 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 22490 | { |
c19d1205 ZW |
22491 | prefix = prefix_once; |
22492 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
22493 | } |
22494 | ||
29a2809e | 22495 | sec_name = concat (prefix, text_name, (char *) NULL); |
bfae80f2 | 22496 | |
c19d1205 ZW |
22497 | flags = SHF_ALLOC; |
22498 | linkonce = 0; | |
22499 | group_name = 0; | |
bfae80f2 | 22500 | |
c19d1205 ZW |
22501 | /* Handle COMDAT group. */ |
22502 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 22503 | { |
c19d1205 ZW |
22504 | group_name = elf_group_name (text_seg); |
22505 | if (group_name == NULL) | |
22506 | { | |
bd3ba5d1 | 22507 | as_bad (_("Group section `%s' has no group signature"), |
c19d1205 ZW |
22508 | segment_name (text_seg)); |
22509 | ignore_rest_of_line (); | |
22510 | return; | |
22511 | } | |
22512 | flags |= SHF_GROUP; | |
22513 | linkonce = 1; | |
bfae80f2 RE |
22514 | } |
22515 | ||
a91e1603 L |
22516 | obj_elf_change_section (sec_name, type, 0, flags, 0, group_name, |
22517 | linkonce, 0); | |
bfae80f2 | 22518 | |
5f4273c7 | 22519 | /* Set the section link for index tables. */ |
c19d1205 ZW |
22520 | if (idx) |
22521 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
22522 | } |
22523 | ||
bfae80f2 | 22524 | |
c19d1205 ZW |
22525 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
22526 | personality routine data. Returns zero, or the index table value for | |
cad0da33 | 22527 | an inline entry. */ |
c19d1205 ZW |
22528 | |
22529 | static valueT | |
22530 | create_unwind_entry (int have_data) | |
bfae80f2 | 22531 | { |
c19d1205 ZW |
22532 | int size; |
22533 | addressT where; | |
22534 | char *ptr; | |
22535 | /* The current word of data. */ | |
22536 | valueT data; | |
22537 | /* The number of bytes left in this word. */ | |
22538 | int n; | |
bfae80f2 | 22539 | |
c19d1205 | 22540 | finish_unwind_opcodes (); |
bfae80f2 | 22541 | |
c19d1205 ZW |
22542 | /* Remember the current text section. */ |
22543 | unwind.saved_seg = now_seg; | |
22544 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 22545 | |
c19d1205 | 22546 | start_unwind_section (now_seg, 0); |
bfae80f2 | 22547 | |
c19d1205 | 22548 | if (unwind.personality_routine == NULL) |
bfae80f2 | 22549 | { |
c19d1205 ZW |
22550 | if (unwind.personality_index == -2) |
22551 | { | |
22552 | if (have_data) | |
5f4273c7 | 22553 | as_bad (_("handlerdata in cantunwind frame")); |
c19d1205 ZW |
22554 | return 1; /* EXIDX_CANTUNWIND. */ |
22555 | } | |
bfae80f2 | 22556 | |
c19d1205 ZW |
22557 | /* Use a default personality routine if none is specified. */ |
22558 | if (unwind.personality_index == -1) | |
22559 | { | |
22560 | if (unwind.opcode_count > 3) | |
22561 | unwind.personality_index = 1; | |
22562 | else | |
22563 | unwind.personality_index = 0; | |
22564 | } | |
bfae80f2 | 22565 | |
c19d1205 ZW |
22566 | /* Space for the personality routine entry. */ |
22567 | if (unwind.personality_index == 0) | |
22568 | { | |
22569 | if (unwind.opcode_count > 3) | |
22570 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 22571 | |
c19d1205 ZW |
22572 | if (!have_data) |
22573 | { | |
22574 | /* All the data is inline in the index table. */ | |
22575 | data = 0x80; | |
22576 | n = 3; | |
22577 | while (unwind.opcode_count > 0) | |
22578 | { | |
22579 | unwind.opcode_count--; | |
22580 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
22581 | n--; | |
22582 | } | |
bfae80f2 | 22583 | |
c19d1205 ZW |
22584 | /* Pad with "finish" opcodes. */ |
22585 | while (n--) | |
22586 | data = (data << 8) | 0xb0; | |
bfae80f2 | 22587 | |
c19d1205 ZW |
22588 | return data; |
22589 | } | |
22590 | size = 0; | |
22591 | } | |
22592 | else | |
22593 | /* We get two opcodes "free" in the first word. */ | |
22594 | size = unwind.opcode_count - 2; | |
22595 | } | |
22596 | else | |
5011093d | 22597 | { |
cad0da33 NC |
22598 | /* PR 16765: Missing or misplaced unwind directives can trigger this. */ |
22599 | if (unwind.personality_index != -1) | |
22600 | { | |
22601 | as_bad (_("attempt to recreate an unwind entry")); | |
22602 | return 1; | |
22603 | } | |
5011093d NC |
22604 | |
22605 | /* An extra byte is required for the opcode count. */ | |
22606 | size = unwind.opcode_count + 1; | |
22607 | } | |
bfae80f2 | 22608 | |
c19d1205 ZW |
22609 | size = (size + 3) >> 2; |
22610 | if (size > 0xff) | |
22611 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 22612 | |
c19d1205 ZW |
22613 | frag_align (2, 0, 0); |
22614 | record_alignment (now_seg, 2); | |
22615 | unwind.table_entry = expr_build_dot (); | |
22616 | ||
22617 | /* Allocate the table entry. */ | |
22618 | ptr = frag_more ((size << 2) + 4); | |
74929e7b NC |
22619 | /* PR 13449: Zero the table entries in case some of them are not used. */ |
22620 | memset (ptr, 0, (size << 2) + 4); | |
c19d1205 | 22621 | where = frag_now_fix () - ((size << 2) + 4); |
bfae80f2 | 22622 | |
c19d1205 | 22623 | switch (unwind.personality_index) |
bfae80f2 | 22624 | { |
c19d1205 ZW |
22625 | case -1: |
22626 | /* ??? Should this be a PLT generating relocation? */ | |
22627 | /* Custom personality routine. */ | |
22628 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
22629 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 22630 | |
c19d1205 ZW |
22631 | where += 4; |
22632 | ptr += 4; | |
bfae80f2 | 22633 | |
c19d1205 | 22634 | /* Set the first byte to the number of additional words. */ |
5011093d | 22635 | data = size > 0 ? size - 1 : 0; |
c19d1205 ZW |
22636 | n = 3; |
22637 | break; | |
bfae80f2 | 22638 | |
c19d1205 ZW |
22639 | /* ABI defined personality routines. */ |
22640 | case 0: | |
22641 | /* Three opcodes bytes are packed into the first word. */ | |
22642 | data = 0x80; | |
22643 | n = 3; | |
22644 | break; | |
bfae80f2 | 22645 | |
c19d1205 ZW |
22646 | case 1: |
22647 | case 2: | |
22648 | /* The size and first two opcode bytes go in the first word. */ | |
22649 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
22650 | n = 2; | |
22651 | break; | |
bfae80f2 | 22652 | |
c19d1205 ZW |
22653 | default: |
22654 | /* Should never happen. */ | |
22655 | abort (); | |
22656 | } | |
bfae80f2 | 22657 | |
c19d1205 ZW |
22658 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
22659 | time. */ | |
22660 | while (unwind.opcode_count > 0) | |
22661 | { | |
22662 | if (n == 0) | |
22663 | { | |
22664 | md_number_to_chars (ptr, data, 4); | |
22665 | ptr += 4; | |
22666 | n = 4; | |
22667 | data = 0; | |
22668 | } | |
22669 | unwind.opcode_count--; | |
22670 | n--; | |
22671 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
22672 | } | |
22673 | ||
22674 | /* Finish off the last word. */ | |
22675 | if (n < 4) | |
22676 | { | |
22677 | /* Pad with "finish" opcodes. */ | |
22678 | while (n--) | |
22679 | data = (data << 8) | 0xb0; | |
22680 | ||
22681 | md_number_to_chars (ptr, data, 4); | |
22682 | } | |
22683 | ||
22684 | if (!have_data) | |
22685 | { | |
22686 | /* Add an empty descriptor if there is no user-specified data. */ | |
22687 | ptr = frag_more (4); | |
22688 | md_number_to_chars (ptr, 0, 4); | |
22689 | } | |
22690 | ||
22691 | return 0; | |
bfae80f2 RE |
22692 | } |
22693 | ||
f0927246 NC |
22694 | |
22695 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
22696 | ||
22697 | void | |
22698 | tc_arm_frame_initial_instructions (void) | |
22699 | { | |
22700 | cfi_add_CFA_def_cfa (REG_SP, 0); | |
22701 | } | |
22702 | #endif /* OBJ_ELF */ | |
22703 | ||
c19d1205 ZW |
22704 | /* Convert REGNAME to a DWARF-2 register number. */ |
22705 | ||
22706 | int | |
1df69f4f | 22707 | tc_arm_regname_to_dw2regnum (char *regname) |
bfae80f2 | 22708 | { |
1df69f4f | 22709 | int reg = arm_reg_parse (®name, REG_TYPE_RN); |
1f5afe1c NC |
22710 | if (reg != FAIL) |
22711 | return reg; | |
c19d1205 | 22712 | |
1f5afe1c NC |
22713 | /* PR 16694: Allow VFP registers as well. */ |
22714 | reg = arm_reg_parse (®name, REG_TYPE_VFS); | |
22715 | if (reg != FAIL) | |
22716 | return 64 + reg; | |
c19d1205 | 22717 | |
1f5afe1c NC |
22718 | reg = arm_reg_parse (®name, REG_TYPE_VFD); |
22719 | if (reg != FAIL) | |
22720 | return reg + 256; | |
22721 | ||
0198d5e6 | 22722 | return FAIL; |
bfae80f2 RE |
22723 | } |
22724 | ||
f0927246 | 22725 | #ifdef TE_PE |
c19d1205 | 22726 | void |
f0927246 | 22727 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
bfae80f2 | 22728 | { |
91d6fa6a | 22729 | expressionS exp; |
bfae80f2 | 22730 | |
91d6fa6a NC |
22731 | exp.X_op = O_secrel; |
22732 | exp.X_add_symbol = symbol; | |
22733 | exp.X_add_number = 0; | |
22734 | emit_expr (&exp, size); | |
f0927246 NC |
22735 | } |
22736 | #endif | |
bfae80f2 | 22737 | |
c19d1205 | 22738 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 22739 | |
2fc8bdac ZW |
22740 | /* Return the address within the segment that a PC-relative fixup is |
22741 | relative to. For ARM, PC-relative fixups applied to instructions | |
22742 | are generally relative to the location of the fixup plus 8 bytes. | |
22743 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
22744 | require special handling. */ | |
bfae80f2 | 22745 | |
c19d1205 | 22746 | long |
2fc8bdac | 22747 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 22748 | { |
2fc8bdac ZW |
22749 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
22750 | ||
22751 | /* If this is pc-relative and we are going to emit a relocation | |
22752 | then we just want to put out any pipeline compensation that the linker | |
53baae48 NC |
22753 | will need. Otherwise we want to use the calculated base. |
22754 | For WinCE we skip the bias for externals as well, since this | |
22755 | is how the MS ARM-CE assembler behaves and we want to be compatible. */ | |
5f4273c7 | 22756 | if (fixP->fx_pcrel |
2fc8bdac | 22757 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) |
53baae48 NC |
22758 | || (arm_force_relocation (fixP) |
22759 | #ifdef TE_WINCE | |
22760 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
22761 | #endif | |
22762 | ))) | |
2fc8bdac | 22763 | base = 0; |
bfae80f2 | 22764 | |
267bf995 | 22765 | |
c19d1205 | 22766 | switch (fixP->fx_r_type) |
bfae80f2 | 22767 | { |
2fc8bdac ZW |
22768 | /* PC relative addressing on the Thumb is slightly odd as the |
22769 | bottom two bits of the PC are forced to zero for the | |
22770 | calculation. This happens *after* application of the | |
22771 | pipeline offset. However, Thumb adrl already adjusts for | |
22772 | this, so we need not do it again. */ | |
c19d1205 | 22773 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 22774 | return base & ~3; |
c19d1205 ZW |
22775 | |
22776 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
22777 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 22778 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 22779 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 22780 | return (base + 4) & ~3; |
c19d1205 | 22781 | |
2fc8bdac ZW |
22782 | /* Thumb branches are simply offset by +4. */ |
22783 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
22784 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
22785 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
22786 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
2fc8bdac | 22787 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac | 22788 | return base + 4; |
bfae80f2 | 22789 | |
267bf995 | 22790 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
486499d0 CL |
22791 | if (fixP->fx_addsy |
22792 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 22793 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 | 22794 | && ARM_IS_FUNC (fixP->fx_addsy) |
477330fc RM |
22795 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) |
22796 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
267bf995 RR |
22797 | return base + 4; |
22798 | ||
00adf2d4 JB |
22799 | /* BLX is like branches above, but forces the low two bits of PC to |
22800 | zero. */ | |
486499d0 CL |
22801 | case BFD_RELOC_THUMB_PCREL_BLX: |
22802 | if (fixP->fx_addsy | |
22803 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 22804 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
22805 | && THUMB_IS_FUNC (fixP->fx_addsy) |
22806 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
22807 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
00adf2d4 JB |
22808 | return (base + 4) & ~3; |
22809 | ||
2fc8bdac ZW |
22810 | /* ARM mode branches are offset by +8. However, the Windows CE |
22811 | loader expects the relocation not to take this into account. */ | |
267bf995 | 22812 | case BFD_RELOC_ARM_PCREL_BLX: |
486499d0 CL |
22813 | if (fixP->fx_addsy |
22814 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 22815 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
22816 | && ARM_IS_FUNC (fixP->fx_addsy) |
22817 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
22818 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 22819 | return base + 8; |
267bf995 | 22820 | |
486499d0 CL |
22821 | case BFD_RELOC_ARM_PCREL_CALL: |
22822 | if (fixP->fx_addsy | |
22823 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 22824 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
22825 | && THUMB_IS_FUNC (fixP->fx_addsy) |
22826 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
22827 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 22828 | return base + 8; |
267bf995 | 22829 | |
2fc8bdac | 22830 | case BFD_RELOC_ARM_PCREL_BRANCH: |
39b41c9c | 22831 | case BFD_RELOC_ARM_PCREL_JUMP: |
2fc8bdac | 22832 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 22833 | #ifdef TE_WINCE |
5f4273c7 | 22834 | /* When handling fixups immediately, because we have already |
477330fc | 22835 | discovered the value of a symbol, or the address of the frag involved |
53baae48 | 22836 | we must account for the offset by +8, as the OS loader will never see the reloc. |
477330fc RM |
22837 | see fixup_segment() in write.c |
22838 | The S_IS_EXTERNAL test handles the case of global symbols. | |
22839 | Those need the calculated base, not just the pipe compensation the linker will need. */ | |
53baae48 NC |
22840 | if (fixP->fx_pcrel |
22841 | && fixP->fx_addsy != NULL | |
22842 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
22843 | && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) | |
22844 | return base + 8; | |
2fc8bdac | 22845 | return base; |
c19d1205 | 22846 | #else |
2fc8bdac | 22847 | return base + 8; |
c19d1205 | 22848 | #endif |
2fc8bdac | 22849 | |
267bf995 | 22850 | |
2fc8bdac ZW |
22851 | /* ARM mode loads relative to PC are also offset by +8. Unlike |
22852 | branches, the Windows CE loader *does* expect the relocation | |
22853 | to take this into account. */ | |
22854 | case BFD_RELOC_ARM_OFFSET_IMM: | |
22855 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
22856 | case BFD_RELOC_ARM_HWLITERAL: | |
22857 | case BFD_RELOC_ARM_LITERAL: | |
22858 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
22859 | return base + 8; | |
22860 | ||
22861 | ||
22862 | /* Other PC-relative relocations are un-offset. */ | |
22863 | default: | |
22864 | return base; | |
22865 | } | |
bfae80f2 RE |
22866 | } |
22867 | ||
8b2d793c NC |
22868 | static bfd_boolean flag_warn_syms = TRUE; |
22869 | ||
ae8714c2 NC |
22870 | bfd_boolean |
22871 | arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name) | |
bfae80f2 | 22872 | { |
8b2d793c NC |
22873 | /* PR 18347 - Warn if the user attempts to create a symbol with the same |
22874 | name as an ARM instruction. Whilst strictly speaking it is allowed, it | |
22875 | does mean that the resulting code might be very confusing to the reader. | |
22876 | Also this warning can be triggered if the user omits an operand before | |
22877 | an immediate address, eg: | |
22878 | ||
22879 | LDR =foo | |
22880 | ||
22881 | GAS treats this as an assignment of the value of the symbol foo to a | |
22882 | symbol LDR, and so (without this code) it will not issue any kind of | |
22883 | warning or error message. | |
22884 | ||
22885 | Note - ARM instructions are case-insensitive but the strings in the hash | |
22886 | table are all stored in lower case, so we must first ensure that name is | |
ae8714c2 NC |
22887 | lower case too. */ |
22888 | if (flag_warn_syms && arm_ops_hsh) | |
8b2d793c NC |
22889 | { |
22890 | char * nbuf = strdup (name); | |
22891 | char * p; | |
22892 | ||
22893 | for (p = nbuf; *p; p++) | |
22894 | *p = TOLOWER (*p); | |
22895 | if (hash_find (arm_ops_hsh, nbuf) != NULL) | |
22896 | { | |
22897 | static struct hash_control * already_warned = NULL; | |
22898 | ||
22899 | if (already_warned == NULL) | |
22900 | already_warned = hash_new (); | |
22901 | /* Only warn about the symbol once. To keep the code | |
22902 | simple we let hash_insert do the lookup for us. */ | |
22903 | if (hash_insert (already_warned, name, NULL) == NULL) | |
ae8714c2 | 22904 | as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name); |
8b2d793c NC |
22905 | } |
22906 | else | |
22907 | free (nbuf); | |
22908 | } | |
3739860c | 22909 | |
ae8714c2 NC |
22910 | return FALSE; |
22911 | } | |
22912 | ||
22913 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. | |
22914 | Otherwise we have no need to default values of symbols. */ | |
22915 | ||
22916 | symbolS * | |
22917 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
22918 | { | |
22919 | #ifdef OBJ_ELF | |
22920 | if (name[0] == '_' && name[1] == 'G' | |
22921 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
22922 | { | |
22923 | if (!GOT_symbol) | |
22924 | { | |
22925 | if (symbol_find (name)) | |
22926 | as_bad (_("GOT already in the symbol table")); | |
22927 | ||
22928 | GOT_symbol = symbol_new (name, undefined_section, | |
22929 | (valueT) 0, & zero_address_frag); | |
22930 | } | |
22931 | ||
22932 | return GOT_symbol; | |
22933 | } | |
22934 | #endif | |
22935 | ||
c921be7d | 22936 | return NULL; |
bfae80f2 RE |
22937 | } |
22938 | ||
55cf6793 | 22939 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
22940 | computed as two separate immediate values, added together. We |
22941 | already know that this value cannot be computed by just one ARM | |
22942 | instruction. */ | |
22943 | ||
22944 | static unsigned int | |
22945 | validate_immediate_twopart (unsigned int val, | |
22946 | unsigned int * highpart) | |
bfae80f2 | 22947 | { |
c19d1205 ZW |
22948 | unsigned int a; |
22949 | unsigned int i; | |
bfae80f2 | 22950 | |
c19d1205 ZW |
22951 | for (i = 0; i < 32; i += 2) |
22952 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
22953 | { | |
22954 | if (a & 0xff00) | |
22955 | { | |
22956 | if (a & ~ 0xffff) | |
22957 | continue; | |
22958 | * highpart = (a >> 8) | ((i + 24) << 7); | |
22959 | } | |
22960 | else if (a & 0xff0000) | |
22961 | { | |
22962 | if (a & 0xff000000) | |
22963 | continue; | |
22964 | * highpart = (a >> 16) | ((i + 16) << 7); | |
22965 | } | |
22966 | else | |
22967 | { | |
9c2799c2 | 22968 | gas_assert (a & 0xff000000); |
c19d1205 ZW |
22969 | * highpart = (a >> 24) | ((i + 8) << 7); |
22970 | } | |
bfae80f2 | 22971 | |
c19d1205 ZW |
22972 | return (a & 0xff) | (i << 7); |
22973 | } | |
bfae80f2 | 22974 | |
c19d1205 | 22975 | return FAIL; |
bfae80f2 RE |
22976 | } |
22977 | ||
c19d1205 ZW |
22978 | static int |
22979 | validate_offset_imm (unsigned int val, int hwse) | |
22980 | { | |
22981 | if ((hwse && val > 255) || val > 4095) | |
22982 | return FAIL; | |
22983 | return val; | |
22984 | } | |
bfae80f2 | 22985 | |
55cf6793 | 22986 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
22987 | negative immediate constant by altering the instruction. A bit of |
22988 | a hack really. | |
22989 | MOV <-> MVN | |
22990 | AND <-> BIC | |
22991 | ADC <-> SBC | |
22992 | by inverting the second operand, and | |
22993 | ADD <-> SUB | |
22994 | CMP <-> CMN | |
22995 | by negating the second operand. */ | |
bfae80f2 | 22996 | |
c19d1205 ZW |
22997 | static int |
22998 | negate_data_op (unsigned long * instruction, | |
22999 | unsigned long value) | |
bfae80f2 | 23000 | { |
c19d1205 ZW |
23001 | int op, new_inst; |
23002 | unsigned long negated, inverted; | |
bfae80f2 | 23003 | |
c19d1205 ZW |
23004 | negated = encode_arm_immediate (-value); |
23005 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 23006 | |
c19d1205 ZW |
23007 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
23008 | switch (op) | |
bfae80f2 | 23009 | { |
c19d1205 ZW |
23010 | /* First negates. */ |
23011 | case OPCODE_SUB: /* ADD <-> SUB */ | |
23012 | new_inst = OPCODE_ADD; | |
23013 | value = negated; | |
23014 | break; | |
bfae80f2 | 23015 | |
c19d1205 ZW |
23016 | case OPCODE_ADD: |
23017 | new_inst = OPCODE_SUB; | |
23018 | value = negated; | |
23019 | break; | |
bfae80f2 | 23020 | |
c19d1205 ZW |
23021 | case OPCODE_CMP: /* CMP <-> CMN */ |
23022 | new_inst = OPCODE_CMN; | |
23023 | value = negated; | |
23024 | break; | |
bfae80f2 | 23025 | |
c19d1205 ZW |
23026 | case OPCODE_CMN: |
23027 | new_inst = OPCODE_CMP; | |
23028 | value = negated; | |
23029 | break; | |
bfae80f2 | 23030 | |
c19d1205 ZW |
23031 | /* Now Inverted ops. */ |
23032 | case OPCODE_MOV: /* MOV <-> MVN */ | |
23033 | new_inst = OPCODE_MVN; | |
23034 | value = inverted; | |
23035 | break; | |
bfae80f2 | 23036 | |
c19d1205 ZW |
23037 | case OPCODE_MVN: |
23038 | new_inst = OPCODE_MOV; | |
23039 | value = inverted; | |
23040 | break; | |
bfae80f2 | 23041 | |
c19d1205 ZW |
23042 | case OPCODE_AND: /* AND <-> BIC */ |
23043 | new_inst = OPCODE_BIC; | |
23044 | value = inverted; | |
23045 | break; | |
bfae80f2 | 23046 | |
c19d1205 ZW |
23047 | case OPCODE_BIC: |
23048 | new_inst = OPCODE_AND; | |
23049 | value = inverted; | |
23050 | break; | |
bfae80f2 | 23051 | |
c19d1205 ZW |
23052 | case OPCODE_ADC: /* ADC <-> SBC */ |
23053 | new_inst = OPCODE_SBC; | |
23054 | value = inverted; | |
23055 | break; | |
bfae80f2 | 23056 | |
c19d1205 ZW |
23057 | case OPCODE_SBC: |
23058 | new_inst = OPCODE_ADC; | |
23059 | value = inverted; | |
23060 | break; | |
bfae80f2 | 23061 | |
c19d1205 ZW |
23062 | /* We cannot do anything. */ |
23063 | default: | |
23064 | return FAIL; | |
b99bd4ef NC |
23065 | } |
23066 | ||
c19d1205 ZW |
23067 | if (value == (unsigned) FAIL) |
23068 | return FAIL; | |
23069 | ||
23070 | *instruction &= OPCODE_MASK; | |
23071 | *instruction |= new_inst << DATA_OP_SHIFT; | |
23072 | return value; | |
b99bd4ef NC |
23073 | } |
23074 | ||
ef8d22e6 PB |
23075 | /* Like negate_data_op, but for Thumb-2. */ |
23076 | ||
23077 | static unsigned int | |
16dd5e42 | 23078 | thumb32_negate_data_op (offsetT *instruction, unsigned int value) |
ef8d22e6 PB |
23079 | { |
23080 | int op, new_inst; | |
23081 | int rd; | |
16dd5e42 | 23082 | unsigned int negated, inverted; |
ef8d22e6 PB |
23083 | |
23084 | negated = encode_thumb32_immediate (-value); | |
23085 | inverted = encode_thumb32_immediate (~value); | |
23086 | ||
23087 | rd = (*instruction >> 8) & 0xf; | |
23088 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; | |
23089 | switch (op) | |
23090 | { | |
23091 | /* ADD <-> SUB. Includes CMP <-> CMN. */ | |
23092 | case T2_OPCODE_SUB: | |
23093 | new_inst = T2_OPCODE_ADD; | |
23094 | value = negated; | |
23095 | break; | |
23096 | ||
23097 | case T2_OPCODE_ADD: | |
23098 | new_inst = T2_OPCODE_SUB; | |
23099 | value = negated; | |
23100 | break; | |
23101 | ||
23102 | /* ORR <-> ORN. Includes MOV <-> MVN. */ | |
23103 | case T2_OPCODE_ORR: | |
23104 | new_inst = T2_OPCODE_ORN; | |
23105 | value = inverted; | |
23106 | break; | |
23107 | ||
23108 | case T2_OPCODE_ORN: | |
23109 | new_inst = T2_OPCODE_ORR; | |
23110 | value = inverted; | |
23111 | break; | |
23112 | ||
23113 | /* AND <-> BIC. TST has no inverted equivalent. */ | |
23114 | case T2_OPCODE_AND: | |
23115 | new_inst = T2_OPCODE_BIC; | |
23116 | if (rd == 15) | |
23117 | value = FAIL; | |
23118 | else | |
23119 | value = inverted; | |
23120 | break; | |
23121 | ||
23122 | case T2_OPCODE_BIC: | |
23123 | new_inst = T2_OPCODE_AND; | |
23124 | value = inverted; | |
23125 | break; | |
23126 | ||
23127 | /* ADC <-> SBC */ | |
23128 | case T2_OPCODE_ADC: | |
23129 | new_inst = T2_OPCODE_SBC; | |
23130 | value = inverted; | |
23131 | break; | |
23132 | ||
23133 | case T2_OPCODE_SBC: | |
23134 | new_inst = T2_OPCODE_ADC; | |
23135 | value = inverted; | |
23136 | break; | |
23137 | ||
23138 | /* We cannot do anything. */ | |
23139 | default: | |
23140 | return FAIL; | |
23141 | } | |
23142 | ||
16dd5e42 | 23143 | if (value == (unsigned int)FAIL) |
ef8d22e6 PB |
23144 | return FAIL; |
23145 | ||
23146 | *instruction &= T2_OPCODE_MASK; | |
23147 | *instruction |= new_inst << T2_DATA_OP_SHIFT; | |
23148 | return value; | |
23149 | } | |
23150 | ||
8f06b2d8 | 23151 | /* Read a 32-bit thumb instruction from buf. */ |
0198d5e6 | 23152 | |
8f06b2d8 PB |
23153 | static unsigned long |
23154 | get_thumb32_insn (char * buf) | |
23155 | { | |
23156 | unsigned long insn; | |
23157 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
23158 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
23159 | ||
23160 | return insn; | |
23161 | } | |
23162 | ||
a8bc6c78 PB |
23163 | /* We usually want to set the low bit on the address of thumb function |
23164 | symbols. In particular .word foo - . should have the low bit set. | |
23165 | Generic code tries to fold the difference of two symbols to | |
23166 | a constant. Prevent this and force a relocation when the first symbols | |
23167 | is a thumb function. */ | |
c921be7d NC |
23168 | |
23169 | bfd_boolean | |
a8bc6c78 PB |
23170 | arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) |
23171 | { | |
23172 | if (op == O_subtract | |
23173 | && l->X_op == O_symbol | |
23174 | && r->X_op == O_symbol | |
23175 | && THUMB_IS_FUNC (l->X_add_symbol)) | |
23176 | { | |
23177 | l->X_op = O_subtract; | |
23178 | l->X_op_symbol = r->X_add_symbol; | |
23179 | l->X_add_number -= r->X_add_number; | |
c921be7d | 23180 | return TRUE; |
a8bc6c78 | 23181 | } |
c921be7d | 23182 | |
a8bc6c78 | 23183 | /* Process as normal. */ |
c921be7d | 23184 | return FALSE; |
a8bc6c78 PB |
23185 | } |
23186 | ||
4a42ebbc RR |
23187 | /* Encode Thumb2 unconditional branches and calls. The encoding |
23188 | for the 2 are identical for the immediate values. */ | |
23189 | ||
23190 | static void | |
23191 | encode_thumb2_b_bl_offset (char * buf, offsetT value) | |
23192 | { | |
23193 | #define T2I1I2MASK ((1 << 13) | (1 << 11)) | |
23194 | offsetT newval; | |
23195 | offsetT newval2; | |
23196 | addressT S, I1, I2, lo, hi; | |
23197 | ||
23198 | S = (value >> 24) & 0x01; | |
23199 | I1 = (value >> 23) & 0x01; | |
23200 | I2 = (value >> 22) & 0x01; | |
23201 | hi = (value >> 12) & 0x3ff; | |
fa94de6b | 23202 | lo = (value >> 1) & 0x7ff; |
4a42ebbc RR |
23203 | newval = md_chars_to_number (buf, THUMB_SIZE); |
23204 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
23205 | newval |= (S << 10) | hi; | |
23206 | newval2 &= ~T2I1I2MASK; | |
23207 | newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK; | |
23208 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
23209 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
23210 | } | |
23211 | ||
c19d1205 | 23212 | void |
55cf6793 | 23213 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
23214 | valueT * valP, |
23215 | segT seg) | |
23216 | { | |
23217 | offsetT value = * valP; | |
23218 | offsetT newval; | |
23219 | unsigned int newimm; | |
23220 | unsigned long temp; | |
23221 | int sign; | |
23222 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 23223 | |
9c2799c2 | 23224 | gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 23225 | |
c19d1205 | 23226 | /* Note whether this will delete the relocation. */ |
4962c51a | 23227 | |
c19d1205 ZW |
23228 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) |
23229 | fixP->fx_done = 1; | |
b99bd4ef | 23230 | |
adbaf948 | 23231 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
5f4273c7 | 23232 | consistency with the behaviour on 32-bit hosts. Remember value |
adbaf948 ZW |
23233 | for emit_reloc. */ |
23234 | value &= 0xffffffff; | |
23235 | value ^= 0x80000000; | |
5f4273c7 | 23236 | value -= 0x80000000; |
adbaf948 ZW |
23237 | |
23238 | *valP = value; | |
c19d1205 | 23239 | fixP->fx_addnumber = value; |
b99bd4ef | 23240 | |
adbaf948 ZW |
23241 | /* Same treatment for fixP->fx_offset. */ |
23242 | fixP->fx_offset &= 0xffffffff; | |
23243 | fixP->fx_offset ^= 0x80000000; | |
23244 | fixP->fx_offset -= 0x80000000; | |
23245 | ||
c19d1205 | 23246 | switch (fixP->fx_r_type) |
b99bd4ef | 23247 | { |
c19d1205 ZW |
23248 | case BFD_RELOC_NONE: |
23249 | /* This will need to go in the object file. */ | |
23250 | fixP->fx_done = 0; | |
23251 | break; | |
b99bd4ef | 23252 | |
c19d1205 ZW |
23253 | case BFD_RELOC_ARM_IMMEDIATE: |
23254 | /* We claim that this fixup has been processed here, | |
23255 | even if in fact we generate an error because we do | |
23256 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
23257 | fixP->fx_done = 1; | |
b99bd4ef | 23258 | |
77db8e2e | 23259 | if (fixP->fx_addsy) |
b99bd4ef | 23260 | { |
77db8e2e | 23261 | const char *msg = 0; |
b99bd4ef | 23262 | |
77db8e2e NC |
23263 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
23264 | msg = _("undefined symbol %s used as an immediate value"); | |
23265 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
23266 | msg = _("symbol %s is in a different section"); | |
23267 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
23268 | msg = _("symbol %s is weak and may be overridden later"); | |
23269 | ||
23270 | if (msg) | |
23271 | { | |
23272 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23273 | msg, S_GET_NAME (fixP->fx_addsy)); | |
23274 | break; | |
23275 | } | |
42e5fcbf AS |
23276 | } |
23277 | ||
c19d1205 ZW |
23278 | temp = md_chars_to_number (buf, INSN_SIZE); |
23279 | ||
5e73442d SL |
23280 | /* If the offset is negative, we should use encoding A2 for ADR. */ |
23281 | if ((temp & 0xfff0000) == 0x28f0000 && value < 0) | |
23282 | newimm = negate_data_op (&temp, value); | |
23283 | else | |
23284 | { | |
23285 | newimm = encode_arm_immediate (value); | |
23286 | ||
23287 | /* If the instruction will fail, see if we can fix things up by | |
23288 | changing the opcode. */ | |
23289 | if (newimm == (unsigned int) FAIL) | |
23290 | newimm = negate_data_op (&temp, value); | |
bada4342 JW |
23291 | /* MOV accepts both ARM modified immediate (A1 encoding) and |
23292 | UINT16 (A2 encoding) when possible, MOVW only accepts UINT16. | |
23293 | When disassembling, MOV is preferred when there is no encoding | |
23294 | overlap. */ | |
23295 | if (newimm == (unsigned int) FAIL | |
23296 | && ((temp >> DATA_OP_SHIFT) & 0xf) == OPCODE_MOV | |
23297 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2) | |
23298 | && !((temp >> SBIT_SHIFT) & 0x1) | |
23299 | && value >= 0 && value <= 0xffff) | |
23300 | { | |
23301 | /* Clear bits[23:20] to change encoding from A1 to A2. */ | |
23302 | temp &= 0xff0fffff; | |
23303 | /* Encoding high 4bits imm. Code below will encode the remaining | |
23304 | low 12bits. */ | |
23305 | temp |= (value & 0x0000f000) << 4; | |
23306 | newimm = value & 0x00000fff; | |
23307 | } | |
5e73442d SL |
23308 | } |
23309 | ||
23310 | if (newimm == (unsigned int) FAIL) | |
b99bd4ef | 23311 | { |
c19d1205 ZW |
23312 | as_bad_where (fixP->fx_file, fixP->fx_line, |
23313 | _("invalid constant (%lx) after fixup"), | |
23314 | (unsigned long) value); | |
23315 | break; | |
b99bd4ef | 23316 | } |
b99bd4ef | 23317 | |
c19d1205 ZW |
23318 | newimm |= (temp & 0xfffff000); |
23319 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
23320 | break; | |
b99bd4ef | 23321 | |
c19d1205 ZW |
23322 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
23323 | { | |
23324 | unsigned int highpart = 0; | |
23325 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 23326 | |
77db8e2e | 23327 | if (fixP->fx_addsy) |
42e5fcbf | 23328 | { |
77db8e2e | 23329 | const char *msg = 0; |
42e5fcbf | 23330 | |
77db8e2e NC |
23331 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
23332 | msg = _("undefined symbol %s used as an immediate value"); | |
23333 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
23334 | msg = _("symbol %s is in a different section"); | |
23335 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
23336 | msg = _("symbol %s is weak and may be overridden later"); | |
42e5fcbf | 23337 | |
77db8e2e NC |
23338 | if (msg) |
23339 | { | |
23340 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23341 | msg, S_GET_NAME (fixP->fx_addsy)); | |
23342 | break; | |
23343 | } | |
23344 | } | |
fa94de6b | 23345 | |
c19d1205 ZW |
23346 | newimm = encode_arm_immediate (value); |
23347 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 23348 | |
c19d1205 ZW |
23349 | /* If the instruction will fail, see if we can fix things up by |
23350 | changing the opcode. */ | |
23351 | if (newimm == (unsigned int) FAIL | |
23352 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
23353 | { | |
23354 | /* No ? OK - try using two ADD instructions to generate | |
23355 | the value. */ | |
23356 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 23357 | |
c19d1205 ZW |
23358 | /* Yes - then make sure that the second instruction is |
23359 | also an add. */ | |
23360 | if (newimm != (unsigned int) FAIL) | |
23361 | newinsn = temp; | |
23362 | /* Still No ? Try using a negated value. */ | |
23363 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
23364 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
23365 | /* Otherwise - give up. */ | |
23366 | else | |
23367 | { | |
23368 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23369 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
23370 | (long) value); | |
23371 | break; | |
23372 | } | |
b99bd4ef | 23373 | |
c19d1205 ZW |
23374 | /* Replace the first operand in the 2nd instruction (which |
23375 | is the PC) with the destination register. We have | |
23376 | already added in the PC in the first instruction and we | |
23377 | do not want to do it again. */ | |
23378 | newinsn &= ~ 0xf0000; | |
23379 | newinsn |= ((newinsn & 0x0f000) << 4); | |
23380 | } | |
b99bd4ef | 23381 | |
c19d1205 ZW |
23382 | newimm |= (temp & 0xfffff000); |
23383 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 23384 | |
c19d1205 ZW |
23385 | highpart |= (newinsn & 0xfffff000); |
23386 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
23387 | } | |
23388 | break; | |
b99bd4ef | 23389 | |
c19d1205 | 23390 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
23391 | if (!fixP->fx_done && seg->use_rela_p) |
23392 | value = 0; | |
1a0670f3 | 23393 | /* Fall through. */ |
00a97672 | 23394 | |
c19d1205 | 23395 | case BFD_RELOC_ARM_LITERAL: |
26d97720 | 23396 | sign = value > 0; |
b99bd4ef | 23397 | |
c19d1205 ZW |
23398 | if (value < 0) |
23399 | value = - value; | |
b99bd4ef | 23400 | |
c19d1205 | 23401 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 23402 | { |
c19d1205 ZW |
23403 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
23404 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23405 | _("invalid literal constant: pool needs to be closer")); | |
23406 | else | |
23407 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23408 | _("bad immediate value for offset (%ld)"), | |
23409 | (long) value); | |
23410 | break; | |
f03698e6 RE |
23411 | } |
23412 | ||
c19d1205 | 23413 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
23414 | if (value == 0) |
23415 | newval &= 0xfffff000; | |
23416 | else | |
23417 | { | |
23418 | newval &= 0xff7ff000; | |
23419 | newval |= value | (sign ? INDEX_UP : 0); | |
23420 | } | |
c19d1205 ZW |
23421 | md_number_to_chars (buf, newval, INSN_SIZE); |
23422 | break; | |
b99bd4ef | 23423 | |
c19d1205 ZW |
23424 | case BFD_RELOC_ARM_OFFSET_IMM8: |
23425 | case BFD_RELOC_ARM_HWLITERAL: | |
26d97720 | 23426 | sign = value > 0; |
b99bd4ef | 23427 | |
c19d1205 ZW |
23428 | if (value < 0) |
23429 | value = - value; | |
b99bd4ef | 23430 | |
c19d1205 | 23431 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 23432 | { |
c19d1205 ZW |
23433 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
23434 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23435 | _("invalid literal constant: pool needs to be closer")); | |
23436 | else | |
427d0db6 RM |
23437 | as_bad_where (fixP->fx_file, fixP->fx_line, |
23438 | _("bad immediate value for 8-bit offset (%ld)"), | |
23439 | (long) value); | |
c19d1205 | 23440 | break; |
b99bd4ef NC |
23441 | } |
23442 | ||
c19d1205 | 23443 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
23444 | if (value == 0) |
23445 | newval &= 0xfffff0f0; | |
23446 | else | |
23447 | { | |
23448 | newval &= 0xff7ff0f0; | |
23449 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
23450 | } | |
c19d1205 ZW |
23451 | md_number_to_chars (buf, newval, INSN_SIZE); |
23452 | break; | |
b99bd4ef | 23453 | |
c19d1205 ZW |
23454 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
23455 | if (value < 0 || value > 1020 || value % 4 != 0) | |
23456 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23457 | _("bad immediate value for offset (%ld)"), (long) value); | |
23458 | value /= 4; | |
b99bd4ef | 23459 | |
c19d1205 | 23460 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
23461 | newval |= value; |
23462 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
23463 | break; | |
b99bd4ef | 23464 | |
c19d1205 ZW |
23465 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
23466 | /* This is a complicated relocation used for all varieties of Thumb32 | |
23467 | load/store instruction with immediate offset: | |
23468 | ||
23469 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
477330fc | 23470 | *4, optional writeback(W) |
c19d1205 ZW |
23471 | (doubleword load/store) |
23472 | ||
23473 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
23474 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
23475 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
23476 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
23477 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
23478 | ||
23479 | Uppercase letters indicate bits that are already encoded at | |
23480 | this point. Lowercase letters are our problem. For the | |
23481 | second block of instructions, the secondary opcode nybble | |
23482 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
23483 | a PC-relative operation. */ | |
23484 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
23485 | newval <<= 16; | |
23486 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 23487 | |
c19d1205 | 23488 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 23489 | { |
c19d1205 ZW |
23490 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
23491 | if (value >= 0) | |
23492 | newval |= (1 << 23); | |
23493 | else | |
23494 | value = -value; | |
23495 | if (value % 4 != 0) | |
23496 | { | |
23497 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23498 | _("offset not a multiple of 4")); | |
23499 | break; | |
23500 | } | |
23501 | value /= 4; | |
216d22bc | 23502 | if (value > 0xff) |
c19d1205 ZW |
23503 | { |
23504 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23505 | _("offset out of range")); | |
23506 | break; | |
23507 | } | |
23508 | newval &= ~0xff; | |
b99bd4ef | 23509 | } |
c19d1205 | 23510 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 23511 | { |
c19d1205 ZW |
23512 | /* PC-relative, 12-bit offset. */ |
23513 | if (value >= 0) | |
23514 | newval |= (1 << 23); | |
23515 | else | |
23516 | value = -value; | |
216d22bc | 23517 | if (value > 0xfff) |
c19d1205 ZW |
23518 | { |
23519 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23520 | _("offset out of range")); | |
23521 | break; | |
23522 | } | |
23523 | newval &= ~0xfff; | |
b99bd4ef | 23524 | } |
c19d1205 | 23525 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 23526 | { |
c19d1205 ZW |
23527 | /* Writeback: 8-bit, +/- offset. */ |
23528 | if (value >= 0) | |
23529 | newval |= (1 << 9); | |
23530 | else | |
23531 | value = -value; | |
216d22bc | 23532 | if (value > 0xff) |
c19d1205 ZW |
23533 | { |
23534 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23535 | _("offset out of range")); | |
23536 | break; | |
23537 | } | |
23538 | newval &= ~0xff; | |
b99bd4ef | 23539 | } |
c19d1205 | 23540 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 23541 | { |
c19d1205 | 23542 | /* T-instruction: positive 8-bit offset. */ |
216d22bc | 23543 | if (value < 0 || value > 0xff) |
b99bd4ef | 23544 | { |
c19d1205 ZW |
23545 | as_bad_where (fixP->fx_file, fixP->fx_line, |
23546 | _("offset out of range")); | |
23547 | break; | |
b99bd4ef | 23548 | } |
c19d1205 ZW |
23549 | newval &= ~0xff; |
23550 | newval |= value; | |
b99bd4ef NC |
23551 | } |
23552 | else | |
b99bd4ef | 23553 | { |
c19d1205 ZW |
23554 | /* Positive 12-bit or negative 8-bit offset. */ |
23555 | int limit; | |
23556 | if (value >= 0) | |
b99bd4ef | 23557 | { |
c19d1205 ZW |
23558 | newval |= (1 << 23); |
23559 | limit = 0xfff; | |
23560 | } | |
23561 | else | |
23562 | { | |
23563 | value = -value; | |
23564 | limit = 0xff; | |
23565 | } | |
23566 | if (value > limit) | |
23567 | { | |
23568 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23569 | _("offset out of range")); | |
23570 | break; | |
b99bd4ef | 23571 | } |
c19d1205 | 23572 | newval &= ~limit; |
b99bd4ef | 23573 | } |
b99bd4ef | 23574 | |
c19d1205 ZW |
23575 | newval |= value; |
23576 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
23577 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
23578 | break; | |
404ff6b5 | 23579 | |
c19d1205 ZW |
23580 | case BFD_RELOC_ARM_SHIFT_IMM: |
23581 | newval = md_chars_to_number (buf, INSN_SIZE); | |
23582 | if (((unsigned long) value) > 32 | |
23583 | || (value == 32 | |
23584 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
23585 | { | |
23586 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23587 | _("shift expression is too large")); | |
23588 | break; | |
23589 | } | |
404ff6b5 | 23590 | |
c19d1205 ZW |
23591 | if (value == 0) |
23592 | /* Shifts of zero must be done as lsl. */ | |
23593 | newval &= ~0x60; | |
23594 | else if (value == 32) | |
23595 | value = 0; | |
23596 | newval &= 0xfffff07f; | |
23597 | newval |= (value & 0x1f) << 7; | |
23598 | md_number_to_chars (buf, newval, INSN_SIZE); | |
23599 | break; | |
404ff6b5 | 23600 | |
c19d1205 | 23601 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
16805f35 | 23602 | case BFD_RELOC_ARM_T32_ADD_IMM: |
92e90b6e | 23603 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 23604 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
23605 | /* We claim that this fixup has been processed here, |
23606 | even if in fact we generate an error because we do | |
23607 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
23608 | fixP->fx_done = 1; | |
404ff6b5 | 23609 | |
c19d1205 ZW |
23610 | if (fixP->fx_addsy |
23611 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
23612 | { | |
23613 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23614 | _("undefined symbol %s used as an immediate value"), | |
23615 | S_GET_NAME (fixP->fx_addsy)); | |
23616 | break; | |
23617 | } | |
404ff6b5 | 23618 | |
c19d1205 ZW |
23619 | newval = md_chars_to_number (buf, THUMB_SIZE); |
23620 | newval <<= 16; | |
23621 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 23622 | |
16805f35 | 23623 | newimm = FAIL; |
bada4342 JW |
23624 | if ((fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
23625 | /* ARMv8-M Baseline MOV will reach here, but it doesn't support | |
23626 | Thumb2 modified immediate encoding (T2). */ | |
23627 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)) | |
16805f35 | 23628 | || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) |
ef8d22e6 PB |
23629 | { |
23630 | newimm = encode_thumb32_immediate (value); | |
23631 | if (newimm == (unsigned int) FAIL) | |
23632 | newimm = thumb32_negate_data_op (&newval, value); | |
23633 | } | |
bada4342 | 23634 | if (newimm == (unsigned int) FAIL) |
92e90b6e | 23635 | { |
bada4342 | 23636 | if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE) |
e9f89963 | 23637 | { |
bada4342 JW |
23638 | /* Turn add/sum into addw/subw. */ |
23639 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
23640 | newval = (newval & 0xfeffffff) | 0x02000000; | |
23641 | /* No flat 12-bit imm encoding for addsw/subsw. */ | |
23642 | if ((newval & 0x00100000) == 0) | |
40f246e3 | 23643 | { |
bada4342 JW |
23644 | /* 12 bit immediate for addw/subw. */ |
23645 | if (value < 0) | |
23646 | { | |
23647 | value = -value; | |
23648 | newval ^= 0x00a00000; | |
23649 | } | |
23650 | if (value > 0xfff) | |
23651 | newimm = (unsigned int) FAIL; | |
23652 | else | |
23653 | newimm = value; | |
23654 | } | |
23655 | } | |
23656 | else | |
23657 | { | |
23658 | /* MOV accepts both Thumb2 modified immediate (T2 encoding) and | |
23659 | UINT16 (T3 encoding), MOVW only accepts UINT16. When | |
23660 | disassembling, MOV is preferred when there is no encoding | |
db7bf105 | 23661 | overlap. */ |
bada4342 | 23662 | if (((newval >> T2_DATA_OP_SHIFT) & 0xf) == T2_OPCODE_ORR |
db7bf105 NC |
23663 | /* NOTE: MOV uses the ORR opcode in Thumb 2 mode |
23664 | but with the Rn field [19:16] set to 1111. */ | |
23665 | && (((newval >> 16) & 0xf) == 0xf) | |
bada4342 JW |
23666 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m) |
23667 | && !((newval >> T2_SBIT_SHIFT) & 0x1) | |
db7bf105 | 23668 | && value >= 0 && value <= 0xffff) |
bada4342 JW |
23669 | { |
23670 | /* Toggle bit[25] to change encoding from T2 to T3. */ | |
23671 | newval ^= 1 << 25; | |
23672 | /* Clear bits[19:16]. */ | |
23673 | newval &= 0xfff0ffff; | |
23674 | /* Encoding high 4bits imm. Code below will encode the | |
23675 | remaining low 12bits. */ | |
23676 | newval |= (value & 0x0000f000) << 4; | |
23677 | newimm = value & 0x00000fff; | |
40f246e3 | 23678 | } |
e9f89963 | 23679 | } |
92e90b6e | 23680 | } |
cc8a6dd0 | 23681 | |
c19d1205 | 23682 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 23683 | { |
c19d1205 ZW |
23684 | as_bad_where (fixP->fx_file, fixP->fx_line, |
23685 | _("invalid constant (%lx) after fixup"), | |
23686 | (unsigned long) value); | |
23687 | break; | |
3631a3c8 NC |
23688 | } |
23689 | ||
c19d1205 ZW |
23690 | newval |= (newimm & 0x800) << 15; |
23691 | newval |= (newimm & 0x700) << 4; | |
23692 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 23693 | |
c19d1205 ZW |
23694 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
23695 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
23696 | break; | |
a737bd4d | 23697 | |
3eb17e6b | 23698 | case BFD_RELOC_ARM_SMC: |
c19d1205 ZW |
23699 | if (((unsigned long) value) > 0xffff) |
23700 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3eb17e6b | 23701 | _("invalid smc expression")); |
2fc8bdac | 23702 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
23703 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
23704 | md_number_to_chars (buf, newval, INSN_SIZE); | |
23705 | break; | |
a737bd4d | 23706 | |
90ec0d68 MGD |
23707 | case BFD_RELOC_ARM_HVC: |
23708 | if (((unsigned long) value) > 0xffff) | |
23709 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23710 | _("invalid hvc expression")); | |
23711 | newval = md_chars_to_number (buf, INSN_SIZE); | |
23712 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); | |
23713 | md_number_to_chars (buf, newval, INSN_SIZE); | |
23714 | break; | |
23715 | ||
c19d1205 | 23716 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 23717 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
23718 | { |
23719 | if (((unsigned long) value) > 0xff) | |
23720 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23721 | _("invalid swi expression")); | |
2fc8bdac | 23722 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
23723 | newval |= value; |
23724 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
23725 | } | |
23726 | else | |
23727 | { | |
23728 | if (((unsigned long) value) > 0x00ffffff) | |
23729 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23730 | _("invalid swi expression")); | |
2fc8bdac | 23731 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
23732 | newval |= value; |
23733 | md_number_to_chars (buf, newval, INSN_SIZE); | |
23734 | } | |
23735 | break; | |
a737bd4d | 23736 | |
c19d1205 ZW |
23737 | case BFD_RELOC_ARM_MULTI: |
23738 | if (((unsigned long) value) > 0xffff) | |
23739 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23740 | _("invalid expression in load/store multiple")); | |
23741 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
23742 | md_number_to_chars (buf, newval, INSN_SIZE); | |
23743 | break; | |
a737bd4d | 23744 | |
c19d1205 | 23745 | #ifdef OBJ_ELF |
39b41c9c | 23746 | case BFD_RELOC_ARM_PCREL_CALL: |
267bf995 RR |
23747 | |
23748 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
23749 | && fixP->fx_addsy | |
34e77a92 | 23750 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
23751 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
23752 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
23753 | /* Flip the bl to blx. This is a simple flip | |
23754 | bit here because we generate PCREL_CALL for | |
23755 | unconditional bls. */ | |
23756 | { | |
23757 | newval = md_chars_to_number (buf, INSN_SIZE); | |
23758 | newval = newval | 0x10000000; | |
23759 | md_number_to_chars (buf, newval, INSN_SIZE); | |
23760 | temp = 1; | |
23761 | fixP->fx_done = 1; | |
23762 | } | |
39b41c9c PB |
23763 | else |
23764 | temp = 3; | |
23765 | goto arm_branch_common; | |
23766 | ||
23767 | case BFD_RELOC_ARM_PCREL_JUMP: | |
267bf995 RR |
23768 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
23769 | && fixP->fx_addsy | |
34e77a92 | 23770 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
23771 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
23772 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
23773 | { | |
23774 | /* This would map to a bl<cond>, b<cond>, | |
23775 | b<always> to a Thumb function. We | |
23776 | need to force a relocation for this particular | |
23777 | case. */ | |
23778 | newval = md_chars_to_number (buf, INSN_SIZE); | |
23779 | fixP->fx_done = 0; | |
23780 | } | |
1a0670f3 | 23781 | /* Fall through. */ |
267bf995 | 23782 | |
2fc8bdac | 23783 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 23784 | #endif |
39b41c9c PB |
23785 | case BFD_RELOC_ARM_PCREL_BRANCH: |
23786 | temp = 3; | |
23787 | goto arm_branch_common; | |
a737bd4d | 23788 | |
39b41c9c | 23789 | case BFD_RELOC_ARM_PCREL_BLX: |
267bf995 | 23790 | |
39b41c9c | 23791 | temp = 1; |
267bf995 RR |
23792 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
23793 | && fixP->fx_addsy | |
34e77a92 | 23794 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
23795 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
23796 | && ARM_IS_FUNC (fixP->fx_addsy)) | |
23797 | { | |
23798 | /* Flip the blx to a bl and warn. */ | |
23799 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
23800 | newval = 0xeb000000; | |
23801 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
23802 | _("blx to '%s' an ARM ISA state function changed to bl"), | |
23803 | name); | |
23804 | md_number_to_chars (buf, newval, INSN_SIZE); | |
23805 | temp = 3; | |
23806 | fixP->fx_done = 1; | |
23807 | } | |
23808 | ||
23809 | #ifdef OBJ_ELF | |
23810 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
477330fc | 23811 | fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL; |
267bf995 RR |
23812 | #endif |
23813 | ||
39b41c9c | 23814 | arm_branch_common: |
c19d1205 | 23815 | /* We are going to store value (shifted right by two) in the |
39b41c9c PB |
23816 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
23817 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must | |
de194d85 | 23818 | also be clear. */ |
39b41c9c | 23819 | if (value & temp) |
c19d1205 | 23820 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
23821 | _("misaligned branch destination")); |
23822 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
23823 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
08f10d51 | 23824 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 23825 | |
2fc8bdac | 23826 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 23827 | { |
2fc8bdac ZW |
23828 | newval = md_chars_to_number (buf, INSN_SIZE); |
23829 | newval |= (value >> 2) & 0x00ffffff; | |
7ae2971b PB |
23830 | /* Set the H bit on BLX instructions. */ |
23831 | if (temp == 1) | |
23832 | { | |
23833 | if (value & 2) | |
23834 | newval |= 0x01000000; | |
23835 | else | |
23836 | newval &= ~0x01000000; | |
23837 | } | |
2fc8bdac | 23838 | md_number_to_chars (buf, newval, INSN_SIZE); |
c19d1205 | 23839 | } |
c19d1205 | 23840 | break; |
a737bd4d | 23841 | |
25fe350b MS |
23842 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ |
23843 | /* CBZ can only branch forward. */ | |
a737bd4d | 23844 | |
738755b0 | 23845 | /* Attempts to use CBZ to branch to the next instruction |
477330fc RM |
23846 | (which, strictly speaking, are prohibited) will be turned into |
23847 | no-ops. | |
738755b0 MS |
23848 | |
23849 | FIXME: It may be better to remove the instruction completely and | |
23850 | perform relaxation. */ | |
23851 | if (value == -2) | |
2fc8bdac ZW |
23852 | { |
23853 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
738755b0 | 23854 | newval = 0xbf00; /* NOP encoding T1 */ |
2fc8bdac ZW |
23855 | md_number_to_chars (buf, newval, THUMB_SIZE); |
23856 | } | |
738755b0 MS |
23857 | else |
23858 | { | |
23859 | if (value & ~0x7e) | |
08f10d51 | 23860 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
738755b0 | 23861 | |
477330fc | 23862 | if (fixP->fx_done || !seg->use_rela_p) |
738755b0 MS |
23863 | { |
23864 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
23865 | newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); | |
23866 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
23867 | } | |
23868 | } | |
c19d1205 | 23869 | break; |
a737bd4d | 23870 | |
c19d1205 | 23871 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac | 23872 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
08f10d51 | 23873 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 23874 | |
2fc8bdac ZW |
23875 | if (fixP->fx_done || !seg->use_rela_p) |
23876 | { | |
23877 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
23878 | newval |= (value & 0x1ff) >> 1; | |
23879 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
23880 | } | |
c19d1205 | 23881 | break; |
a737bd4d | 23882 | |
c19d1205 | 23883 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac | 23884 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
08f10d51 | 23885 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 23886 | |
2fc8bdac ZW |
23887 | if (fixP->fx_done || !seg->use_rela_p) |
23888 | { | |
23889 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
23890 | newval |= (value & 0xfff) >> 1; | |
23891 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
23892 | } | |
c19d1205 | 23893 | break; |
a737bd4d | 23894 | |
c19d1205 | 23895 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
267bf995 RR |
23896 | if (fixP->fx_addsy |
23897 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 23898 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
23899 | && ARM_IS_FUNC (fixP->fx_addsy) |
23900 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
23901 | { | |
23902 | /* Force a relocation for a branch 20 bits wide. */ | |
23903 | fixP->fx_done = 0; | |
23904 | } | |
08f10d51 | 23905 | if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff)) |
2fc8bdac ZW |
23906 | as_bad_where (fixP->fx_file, fixP->fx_line, |
23907 | _("conditional branch out of range")); | |
404ff6b5 | 23908 | |
2fc8bdac ZW |
23909 | if (fixP->fx_done || !seg->use_rela_p) |
23910 | { | |
23911 | offsetT newval2; | |
23912 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 23913 | |
2fc8bdac ZW |
23914 | S = (value & 0x00100000) >> 20; |
23915 | J2 = (value & 0x00080000) >> 19; | |
23916 | J1 = (value & 0x00040000) >> 18; | |
23917 | hi = (value & 0x0003f000) >> 12; | |
23918 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 23919 | |
2fc8bdac ZW |
23920 | newval = md_chars_to_number (buf, THUMB_SIZE); |
23921 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
23922 | newval |= (S << 10) | hi; | |
23923 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
23924 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
23925 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
23926 | } | |
c19d1205 | 23927 | break; |
6c43fab6 | 23928 | |
c19d1205 | 23929 | case BFD_RELOC_THUMB_PCREL_BLX: |
267bf995 RR |
23930 | /* If there is a blx from a thumb state function to |
23931 | another thumb function flip this to a bl and warn | |
23932 | about it. */ | |
23933 | ||
23934 | if (fixP->fx_addsy | |
34e77a92 | 23935 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
23936 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
23937 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
23938 | { | |
23939 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
23940 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
23941 | _("blx to Thumb func '%s' from Thumb ISA state changed to bl"), | |
23942 | name); | |
23943 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
23944 | newval = newval | 0x1000; | |
23945 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
23946 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
23947 | fixP->fx_done = 1; | |
23948 | } | |
23949 | ||
23950 | ||
23951 | goto thumb_bl_common; | |
23952 | ||
c19d1205 | 23953 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
267bf995 RR |
23954 | /* A bl from Thumb state ISA to an internal ARM state function |
23955 | is converted to a blx. */ | |
23956 | if (fixP->fx_addsy | |
23957 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 23958 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
23959 | && ARM_IS_FUNC (fixP->fx_addsy) |
23960 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
23961 | { | |
23962 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
23963 | newval = newval & ~0x1000; | |
23964 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
23965 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX; | |
23966 | fixP->fx_done = 1; | |
23967 | } | |
23968 | ||
23969 | thumb_bl_common: | |
23970 | ||
2fc8bdac ZW |
23971 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
23972 | /* For a BLX instruction, make sure that the relocation is rounded up | |
23973 | to a word boundary. This follows the semantics of the instruction | |
23974 | which specifies that bit 1 of the target address will come from bit | |
23975 | 1 of the base address. */ | |
d406f3e4 JB |
23976 | value = (value + 3) & ~ 3; |
23977 | ||
23978 | #ifdef OBJ_ELF | |
23979 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 | |
23980 | && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) | |
23981 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
23982 | #endif | |
404ff6b5 | 23983 | |
2b2f5df9 NC |
23984 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
23985 | { | |
fc289b0a | 23986 | if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))) |
2b2f5df9 NC |
23987 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
23988 | else if ((value & ~0x1ffffff) | |
23989 | && ((value & ~0x1ffffff) != ~0x1ffffff)) | |
23990 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23991 | _("Thumb2 branch out of range")); | |
23992 | } | |
4a42ebbc RR |
23993 | |
23994 | if (fixP->fx_done || !seg->use_rela_p) | |
23995 | encode_thumb2_b_bl_offset (buf, value); | |
23996 | ||
c19d1205 | 23997 | break; |
404ff6b5 | 23998 | |
c19d1205 | 23999 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
08f10d51 NC |
24000 | if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff)) |
24001 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); | |
6c43fab6 | 24002 | |
2fc8bdac | 24003 | if (fixP->fx_done || !seg->use_rela_p) |
4a42ebbc | 24004 | encode_thumb2_b_bl_offset (buf, value); |
6c43fab6 | 24005 | |
2fc8bdac | 24006 | break; |
a737bd4d | 24007 | |
2fc8bdac ZW |
24008 | case BFD_RELOC_8: |
24009 | if (fixP->fx_done || !seg->use_rela_p) | |
4b1a927e | 24010 | *buf = value; |
c19d1205 | 24011 | break; |
a737bd4d | 24012 | |
c19d1205 | 24013 | case BFD_RELOC_16: |
2fc8bdac | 24014 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 24015 | md_number_to_chars (buf, value, 2); |
c19d1205 | 24016 | break; |
a737bd4d | 24017 | |
c19d1205 | 24018 | #ifdef OBJ_ELF |
0855e32b NS |
24019 | case BFD_RELOC_ARM_TLS_CALL: |
24020 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
24021 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
24022 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
0855e32b | 24023 | case BFD_RELOC_ARM_TLS_GOTDESC: |
c19d1205 ZW |
24024 | case BFD_RELOC_ARM_TLS_GD32: |
24025 | case BFD_RELOC_ARM_TLS_LE32: | |
24026 | case BFD_RELOC_ARM_TLS_IE32: | |
24027 | case BFD_RELOC_ARM_TLS_LDM32: | |
24028 | case BFD_RELOC_ARM_TLS_LDO32: | |
24029 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
4b1a927e | 24030 | break; |
6c43fab6 | 24031 | |
5c5a4843 CL |
24032 | /* Same handling as above, but with the arm_fdpic guard. */ |
24033 | case BFD_RELOC_ARM_TLS_GD32_FDPIC: | |
24034 | case BFD_RELOC_ARM_TLS_IE32_FDPIC: | |
24035 | case BFD_RELOC_ARM_TLS_LDM32_FDPIC: | |
24036 | if (arm_fdpic) | |
24037 | { | |
24038 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
24039 | } | |
24040 | else | |
24041 | { | |
24042 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24043 | _("Relocation supported only in FDPIC mode")); | |
24044 | } | |
24045 | break; | |
24046 | ||
c19d1205 ZW |
24047 | case BFD_RELOC_ARM_GOT32: |
24048 | case BFD_RELOC_ARM_GOTOFF: | |
c19d1205 | 24049 | break; |
b43420e6 NC |
24050 | |
24051 | case BFD_RELOC_ARM_GOT_PREL: | |
24052 | if (fixP->fx_done || !seg->use_rela_p) | |
477330fc | 24053 | md_number_to_chars (buf, value, 4); |
b43420e6 NC |
24054 | break; |
24055 | ||
9a6f4e97 NS |
24056 | case BFD_RELOC_ARM_TARGET2: |
24057 | /* TARGET2 is not partial-inplace, so we need to write the | |
477330fc RM |
24058 | addend here for REL targets, because it won't be written out |
24059 | during reloc processing later. */ | |
9a6f4e97 NS |
24060 | if (fixP->fx_done || !seg->use_rela_p) |
24061 | md_number_to_chars (buf, fixP->fx_offset, 4); | |
24062 | break; | |
188fd7ae CL |
24063 | |
24064 | /* Relocations for FDPIC. */ | |
24065 | case BFD_RELOC_ARM_GOTFUNCDESC: | |
24066 | case BFD_RELOC_ARM_GOTOFFFUNCDESC: | |
24067 | case BFD_RELOC_ARM_FUNCDESC: | |
24068 | if (arm_fdpic) | |
24069 | { | |
24070 | if (fixP->fx_done || !seg->use_rela_p) | |
24071 | md_number_to_chars (buf, 0, 4); | |
24072 | } | |
24073 | else | |
24074 | { | |
24075 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24076 | _("Relocation supported only in FDPIC mode")); | |
24077 | } | |
24078 | break; | |
c19d1205 | 24079 | #endif |
6c43fab6 | 24080 | |
c19d1205 ZW |
24081 | case BFD_RELOC_RVA: |
24082 | case BFD_RELOC_32: | |
24083 | case BFD_RELOC_ARM_TARGET1: | |
24084 | case BFD_RELOC_ARM_ROSEGREL32: | |
24085 | case BFD_RELOC_ARM_SBREL32: | |
24086 | case BFD_RELOC_32_PCREL: | |
f0927246 NC |
24087 | #ifdef TE_PE |
24088 | case BFD_RELOC_32_SECREL: | |
24089 | #endif | |
2fc8bdac | 24090 | if (fixP->fx_done || !seg->use_rela_p) |
53baae48 NC |
24091 | #ifdef TE_WINCE |
24092 | /* For WinCE we only do this for pcrel fixups. */ | |
24093 | if (fixP->fx_done || fixP->fx_pcrel) | |
24094 | #endif | |
24095 | md_number_to_chars (buf, value, 4); | |
c19d1205 | 24096 | break; |
6c43fab6 | 24097 | |
c19d1205 ZW |
24098 | #ifdef OBJ_ELF |
24099 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 24100 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
24101 | { |
24102 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
24103 | if ((value ^ (value >> 1)) & 0x40000000) | |
24104 | { | |
24105 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24106 | _("rel31 relocation overflow")); | |
24107 | } | |
24108 | newval |= value & 0x7fffffff; | |
24109 | md_number_to_chars (buf, newval, 4); | |
24110 | } | |
24111 | break; | |
c19d1205 | 24112 | #endif |
a737bd4d | 24113 | |
c19d1205 | 24114 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 24115 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
9db2f6b4 RL |
24116 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM) |
24117 | newval = md_chars_to_number (buf, INSN_SIZE); | |
24118 | else | |
24119 | newval = get_thumb32_insn (buf); | |
24120 | if ((newval & 0x0f200f00) == 0x0d000900) | |
24121 | { | |
24122 | /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic | |
24123 | has permitted values that are multiples of 2, in the range 0 | |
24124 | to 510. */ | |
24125 | if (value < -510 || value > 510 || (value & 1)) | |
24126 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24127 | _("co-processor offset out of range")); | |
24128 | } | |
24129 | else if (value < -1023 || value > 1023 || (value & 3)) | |
c19d1205 ZW |
24130 | as_bad_where (fixP->fx_file, fixP->fx_line, |
24131 | _("co-processor offset out of range")); | |
24132 | cp_off_common: | |
26d97720 | 24133 | sign = value > 0; |
c19d1205 ZW |
24134 | if (value < 0) |
24135 | value = -value; | |
8f06b2d8 PB |
24136 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
24137 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
24138 | newval = md_chars_to_number (buf, INSN_SIZE); | |
24139 | else | |
24140 | newval = get_thumb32_insn (buf); | |
26d97720 NS |
24141 | if (value == 0) |
24142 | newval &= 0xffffff00; | |
24143 | else | |
24144 | { | |
24145 | newval &= 0xff7fff00; | |
9db2f6b4 RL |
24146 | if ((newval & 0x0f200f00) == 0x0d000900) |
24147 | { | |
24148 | /* This is a fp16 vstr/vldr. | |
24149 | ||
24150 | It requires the immediate offset in the instruction is shifted | |
24151 | left by 1 to be a half-word offset. | |
24152 | ||
24153 | Here, left shift by 1 first, and later right shift by 2 | |
24154 | should get the right offset. */ | |
24155 | value <<= 1; | |
24156 | } | |
26d97720 NS |
24157 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); |
24158 | } | |
8f06b2d8 PB |
24159 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
24160 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
24161 | md_number_to_chars (buf, newval, INSN_SIZE); | |
24162 | else | |
24163 | put_thumb32_insn (buf, newval); | |
c19d1205 | 24164 | break; |
a737bd4d | 24165 | |
c19d1205 | 24166 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 24167 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
24168 | if (value < -255 || value > 255) |
24169 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24170 | _("co-processor offset out of range")); | |
df7849c5 | 24171 | value *= 4; |
c19d1205 | 24172 | goto cp_off_common; |
6c43fab6 | 24173 | |
c19d1205 ZW |
24174 | case BFD_RELOC_ARM_THUMB_OFFSET: |
24175 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
24176 | /* Exactly what ranges, and where the offset is inserted depends | |
24177 | on the type of instruction, we can establish this from the | |
24178 | top 4 bits. */ | |
24179 | switch (newval >> 12) | |
24180 | { | |
24181 | case 4: /* PC load. */ | |
24182 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
24183 | forced to zero for these loads; md_pcrel_from has already | |
24184 | compensated for this. */ | |
24185 | if (value & 3) | |
24186 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24187 | _("invalid offset, target not word aligned (0x%08lX)"), | |
0359e808 NC |
24188 | (((unsigned long) fixP->fx_frag->fr_address |
24189 | + (unsigned long) fixP->fx_where) & ~3) | |
24190 | + (unsigned long) value); | |
a737bd4d | 24191 | |
c19d1205 ZW |
24192 | if (value & ~0x3fc) |
24193 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24194 | _("invalid offset, value too big (0x%08lX)"), | |
24195 | (long) value); | |
a737bd4d | 24196 | |
c19d1205 ZW |
24197 | newval |= value >> 2; |
24198 | break; | |
a737bd4d | 24199 | |
c19d1205 ZW |
24200 | case 9: /* SP load/store. */ |
24201 | if (value & ~0x3fc) | |
24202 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24203 | _("invalid offset, value too big (0x%08lX)"), | |
24204 | (long) value); | |
24205 | newval |= value >> 2; | |
24206 | break; | |
6c43fab6 | 24207 | |
c19d1205 ZW |
24208 | case 6: /* Word load/store. */ |
24209 | if (value & ~0x7c) | |
24210 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24211 | _("invalid offset, value too big (0x%08lX)"), | |
24212 | (long) value); | |
24213 | newval |= value << 4; /* 6 - 2. */ | |
24214 | break; | |
a737bd4d | 24215 | |
c19d1205 ZW |
24216 | case 7: /* Byte load/store. */ |
24217 | if (value & ~0x1f) | |
24218 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24219 | _("invalid offset, value too big (0x%08lX)"), | |
24220 | (long) value); | |
24221 | newval |= value << 6; | |
24222 | break; | |
a737bd4d | 24223 | |
c19d1205 ZW |
24224 | case 8: /* Halfword load/store. */ |
24225 | if (value & ~0x3e) | |
24226 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24227 | _("invalid offset, value too big (0x%08lX)"), | |
24228 | (long) value); | |
24229 | newval |= value << 5; /* 6 - 1. */ | |
24230 | break; | |
a737bd4d | 24231 | |
c19d1205 ZW |
24232 | default: |
24233 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24234 | "Unable to process relocation for thumb opcode: %lx", | |
24235 | (unsigned long) newval); | |
24236 | break; | |
24237 | } | |
24238 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
24239 | break; | |
a737bd4d | 24240 | |
c19d1205 ZW |
24241 | case BFD_RELOC_ARM_THUMB_ADD: |
24242 | /* This is a complicated relocation, since we use it for all of | |
24243 | the following immediate relocations: | |
a737bd4d | 24244 | |
c19d1205 ZW |
24245 | 3bit ADD/SUB |
24246 | 8bit ADD/SUB | |
24247 | 9bit ADD/SUB SP word-aligned | |
24248 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 24249 | |
c19d1205 ZW |
24250 | The type of instruction being processed is encoded in the |
24251 | instruction field: | |
a737bd4d | 24252 | |
c19d1205 ZW |
24253 | 0x8000 SUB |
24254 | 0x00F0 Rd | |
24255 | 0x000F Rs | |
24256 | */ | |
24257 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
24258 | { | |
24259 | int rd = (newval >> 4) & 0xf; | |
24260 | int rs = newval & 0xf; | |
24261 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 24262 | |
c19d1205 ZW |
24263 | /* Check for HI regs, only very restricted cases allowed: |
24264 | Adjusting SP, and using PC or SP to get an address. */ | |
24265 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
24266 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
24267 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24268 | _("invalid Hi register with immediate")); | |
a737bd4d | 24269 | |
c19d1205 ZW |
24270 | /* If value is negative, choose the opposite instruction. */ |
24271 | if (value < 0) | |
24272 | { | |
24273 | value = -value; | |
24274 | subtract = !subtract; | |
24275 | if (value < 0) | |
24276 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24277 | _("immediate value out of range")); | |
24278 | } | |
a737bd4d | 24279 | |
c19d1205 ZW |
24280 | if (rd == REG_SP) |
24281 | { | |
75c11999 | 24282 | if (value & ~0x1fc) |
c19d1205 ZW |
24283 | as_bad_where (fixP->fx_file, fixP->fx_line, |
24284 | _("invalid immediate for stack address calculation")); | |
24285 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
24286 | newval |= value >> 2; | |
24287 | } | |
24288 | else if (rs == REG_PC || rs == REG_SP) | |
24289 | { | |
c12d2c9d NC |
24290 | /* PR gas/18541. If the addition is for a defined symbol |
24291 | within range of an ADR instruction then accept it. */ | |
24292 | if (subtract | |
24293 | && value == 4 | |
24294 | && fixP->fx_addsy != NULL) | |
24295 | { | |
24296 | subtract = 0; | |
24297 | ||
24298 | if (! S_IS_DEFINED (fixP->fx_addsy) | |
24299 | || S_GET_SEGMENT (fixP->fx_addsy) != seg | |
24300 | || S_IS_WEAK (fixP->fx_addsy)) | |
24301 | { | |
24302 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24303 | _("address calculation needs a strongly defined nearby symbol")); | |
24304 | } | |
24305 | else | |
24306 | { | |
24307 | offsetT v = fixP->fx_where + fixP->fx_frag->fr_address; | |
24308 | ||
24309 | /* Round up to the next 4-byte boundary. */ | |
24310 | if (v & 3) | |
24311 | v = (v + 3) & ~ 3; | |
24312 | else | |
24313 | v += 4; | |
24314 | v = S_GET_VALUE (fixP->fx_addsy) - v; | |
24315 | ||
24316 | if (v & ~0x3fc) | |
24317 | { | |
24318 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24319 | _("symbol too far away")); | |
24320 | } | |
24321 | else | |
24322 | { | |
24323 | fixP->fx_done = 1; | |
24324 | value = v; | |
24325 | } | |
24326 | } | |
24327 | } | |
24328 | ||
c19d1205 ZW |
24329 | if (subtract || value & ~0x3fc) |
24330 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24331 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
5fc177c8 | 24332 | (unsigned long) (subtract ? - value : value)); |
c19d1205 ZW |
24333 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); |
24334 | newval |= rd << 8; | |
24335 | newval |= value >> 2; | |
24336 | } | |
24337 | else if (rs == rd) | |
24338 | { | |
24339 | if (value & ~0xff) | |
24340 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24341 | _("immediate value out of range")); | |
24342 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
24343 | newval |= (rd << 8) | value; | |
24344 | } | |
24345 | else | |
24346 | { | |
24347 | if (value & ~0x7) | |
24348 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24349 | _("immediate value out of range")); | |
24350 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
24351 | newval |= rd | (rs << 3) | (value << 6); | |
24352 | } | |
24353 | } | |
24354 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
24355 | break; | |
a737bd4d | 24356 | |
c19d1205 ZW |
24357 | case BFD_RELOC_ARM_THUMB_IMM: |
24358 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
24359 | if (value < 0 || value > 255) | |
24360 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
4e6e072b | 24361 | _("invalid immediate: %ld is out of range"), |
c19d1205 ZW |
24362 | (long) value); |
24363 | newval |= value; | |
24364 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
24365 | break; | |
a737bd4d | 24366 | |
c19d1205 ZW |
24367 | case BFD_RELOC_ARM_THUMB_SHIFT: |
24368 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
24369 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
24370 | temp = newval & 0xf800; | |
24371 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
24372 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24373 | _("invalid shift value: %ld"), (long) value); | |
24374 | /* Shifts of zero must be encoded as LSL. */ | |
24375 | if (value == 0) | |
24376 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
24377 | /* Shifts of 32 are encoded as zero. */ | |
24378 | else if (value == 32) | |
24379 | value = 0; | |
24380 | newval |= value << 6; | |
24381 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
24382 | break; | |
a737bd4d | 24383 | |
c19d1205 ZW |
24384 | case BFD_RELOC_VTABLE_INHERIT: |
24385 | case BFD_RELOC_VTABLE_ENTRY: | |
24386 | fixP->fx_done = 0; | |
24387 | return; | |
6c43fab6 | 24388 | |
b6895b4f PB |
24389 | case BFD_RELOC_ARM_MOVW: |
24390 | case BFD_RELOC_ARM_MOVT: | |
24391 | case BFD_RELOC_ARM_THUMB_MOVW: | |
24392 | case BFD_RELOC_ARM_THUMB_MOVT: | |
24393 | if (fixP->fx_done || !seg->use_rela_p) | |
24394 | { | |
24395 | /* REL format relocations are limited to a 16-bit addend. */ | |
24396 | if (!fixP->fx_done) | |
24397 | { | |
39623e12 | 24398 | if (value < -0x8000 || value > 0x7fff) |
b6895b4f | 24399 | as_bad_where (fixP->fx_file, fixP->fx_line, |
ff5075ca | 24400 | _("offset out of range")); |
b6895b4f PB |
24401 | } |
24402 | else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
24403 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
24404 | { | |
24405 | value >>= 16; | |
24406 | } | |
24407 | ||
24408 | if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
24409 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
24410 | { | |
24411 | newval = get_thumb32_insn (buf); | |
24412 | newval &= 0xfbf08f00; | |
24413 | newval |= (value & 0xf000) << 4; | |
24414 | newval |= (value & 0x0800) << 15; | |
24415 | newval |= (value & 0x0700) << 4; | |
24416 | newval |= (value & 0x00ff); | |
24417 | put_thumb32_insn (buf, newval); | |
24418 | } | |
24419 | else | |
24420 | { | |
24421 | newval = md_chars_to_number (buf, 4); | |
24422 | newval &= 0xfff0f000; | |
24423 | newval |= value & 0x0fff; | |
24424 | newval |= (value & 0xf000) << 4; | |
24425 | md_number_to_chars (buf, newval, 4); | |
24426 | } | |
24427 | } | |
24428 | return; | |
24429 | ||
72d98d16 MG |
24430 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC: |
24431 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC: | |
24432 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC: | |
24433 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC: | |
24434 | gas_assert (!fixP->fx_done); | |
24435 | { | |
24436 | bfd_vma insn; | |
24437 | bfd_boolean is_mov; | |
24438 | bfd_vma encoded_addend = value; | |
24439 | ||
24440 | /* Check that addend can be encoded in instruction. */ | |
24441 | if (!seg->use_rela_p && (value < 0 || value > 255)) | |
24442 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24443 | _("the offset 0x%08lX is not representable"), | |
24444 | (unsigned long) encoded_addend); | |
24445 | ||
24446 | /* Extract the instruction. */ | |
24447 | insn = md_chars_to_number (buf, THUMB_SIZE); | |
24448 | is_mov = (insn & 0xf800) == 0x2000; | |
24449 | ||
24450 | /* Encode insn. */ | |
24451 | if (is_mov) | |
24452 | { | |
24453 | if (!seg->use_rela_p) | |
24454 | insn |= encoded_addend; | |
24455 | } | |
24456 | else | |
24457 | { | |
24458 | int rd, rs; | |
24459 | ||
24460 | /* Extract the instruction. */ | |
24461 | /* Encoding is the following | |
24462 | 0x8000 SUB | |
24463 | 0x00F0 Rd | |
24464 | 0x000F Rs | |
24465 | */ | |
24466 | /* The following conditions must be true : | |
24467 | - ADD | |
24468 | - Rd == Rs | |
24469 | - Rd <= 7 | |
24470 | */ | |
24471 | rd = (insn >> 4) & 0xf; | |
24472 | rs = insn & 0xf; | |
24473 | if ((insn & 0x8000) || (rd != rs) || rd > 7) | |
24474 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24475 | _("Unable to process relocation for thumb opcode: %lx"), | |
24476 | (unsigned long) insn); | |
24477 | ||
24478 | /* Encode as ADD immediate8 thumb 1 code. */ | |
24479 | insn = 0x3000 | (rd << 8); | |
24480 | ||
24481 | /* Place the encoded addend into the first 8 bits of the | |
24482 | instruction. */ | |
24483 | if (!seg->use_rela_p) | |
24484 | insn |= encoded_addend; | |
24485 | } | |
24486 | ||
24487 | /* Update the instruction. */ | |
24488 | md_number_to_chars (buf, insn, THUMB_SIZE); | |
24489 | } | |
24490 | break; | |
24491 | ||
4962c51a MS |
24492 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
24493 | case BFD_RELOC_ARM_ALU_PC_G0: | |
24494 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
24495 | case BFD_RELOC_ARM_ALU_PC_G1: | |
24496 | case BFD_RELOC_ARM_ALU_PC_G2: | |
24497 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
24498 | case BFD_RELOC_ARM_ALU_SB_G0: | |
24499 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
24500 | case BFD_RELOC_ARM_ALU_SB_G1: | |
24501 | case BFD_RELOC_ARM_ALU_SB_G2: | |
9c2799c2 | 24502 | gas_assert (!fixP->fx_done); |
4962c51a MS |
24503 | if (!seg->use_rela_p) |
24504 | { | |
477330fc RM |
24505 | bfd_vma insn; |
24506 | bfd_vma encoded_addend; | |
24507 | bfd_vma addend_abs = abs (value); | |
24508 | ||
24509 | /* Check that the absolute value of the addend can be | |
24510 | expressed as an 8-bit constant plus a rotation. */ | |
24511 | encoded_addend = encode_arm_immediate (addend_abs); | |
24512 | if (encoded_addend == (unsigned int) FAIL) | |
4962c51a | 24513 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
24514 | _("the offset 0x%08lX is not representable"), |
24515 | (unsigned long) addend_abs); | |
24516 | ||
24517 | /* Extract the instruction. */ | |
24518 | insn = md_chars_to_number (buf, INSN_SIZE); | |
24519 | ||
24520 | /* If the addend is positive, use an ADD instruction. | |
24521 | Otherwise use a SUB. Take care not to destroy the S bit. */ | |
24522 | insn &= 0xff1fffff; | |
24523 | if (value < 0) | |
24524 | insn |= 1 << 22; | |
24525 | else | |
24526 | insn |= 1 << 23; | |
24527 | ||
24528 | /* Place the encoded addend into the first 12 bits of the | |
24529 | instruction. */ | |
24530 | insn &= 0xfffff000; | |
24531 | insn |= encoded_addend; | |
24532 | ||
24533 | /* Update the instruction. */ | |
24534 | md_number_to_chars (buf, insn, INSN_SIZE); | |
4962c51a MS |
24535 | } |
24536 | break; | |
24537 | ||
24538 | case BFD_RELOC_ARM_LDR_PC_G0: | |
24539 | case BFD_RELOC_ARM_LDR_PC_G1: | |
24540 | case BFD_RELOC_ARM_LDR_PC_G2: | |
24541 | case BFD_RELOC_ARM_LDR_SB_G0: | |
24542 | case BFD_RELOC_ARM_LDR_SB_G1: | |
24543 | case BFD_RELOC_ARM_LDR_SB_G2: | |
9c2799c2 | 24544 | gas_assert (!fixP->fx_done); |
4962c51a | 24545 | if (!seg->use_rela_p) |
477330fc RM |
24546 | { |
24547 | bfd_vma insn; | |
24548 | bfd_vma addend_abs = abs (value); | |
4962c51a | 24549 | |
477330fc RM |
24550 | /* Check that the absolute value of the addend can be |
24551 | encoded in 12 bits. */ | |
24552 | if (addend_abs >= 0x1000) | |
4962c51a | 24553 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
24554 | _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), |
24555 | (unsigned long) addend_abs); | |
24556 | ||
24557 | /* Extract the instruction. */ | |
24558 | insn = md_chars_to_number (buf, INSN_SIZE); | |
24559 | ||
24560 | /* If the addend is negative, clear bit 23 of the instruction. | |
24561 | Otherwise set it. */ | |
24562 | if (value < 0) | |
24563 | insn &= ~(1 << 23); | |
24564 | else | |
24565 | insn |= 1 << 23; | |
24566 | ||
24567 | /* Place the absolute value of the addend into the first 12 bits | |
24568 | of the instruction. */ | |
24569 | insn &= 0xfffff000; | |
24570 | insn |= addend_abs; | |
24571 | ||
24572 | /* Update the instruction. */ | |
24573 | md_number_to_chars (buf, insn, INSN_SIZE); | |
24574 | } | |
4962c51a MS |
24575 | break; |
24576 | ||
24577 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
24578 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
24579 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
24580 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
24581 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
24582 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
9c2799c2 | 24583 | gas_assert (!fixP->fx_done); |
4962c51a | 24584 | if (!seg->use_rela_p) |
477330fc RM |
24585 | { |
24586 | bfd_vma insn; | |
24587 | bfd_vma addend_abs = abs (value); | |
4962c51a | 24588 | |
477330fc RM |
24589 | /* Check that the absolute value of the addend can be |
24590 | encoded in 8 bits. */ | |
24591 | if (addend_abs >= 0x100) | |
4962c51a | 24592 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
24593 | _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), |
24594 | (unsigned long) addend_abs); | |
24595 | ||
24596 | /* Extract the instruction. */ | |
24597 | insn = md_chars_to_number (buf, INSN_SIZE); | |
24598 | ||
24599 | /* If the addend is negative, clear bit 23 of the instruction. | |
24600 | Otherwise set it. */ | |
24601 | if (value < 0) | |
24602 | insn &= ~(1 << 23); | |
24603 | else | |
24604 | insn |= 1 << 23; | |
24605 | ||
24606 | /* Place the first four bits of the absolute value of the addend | |
24607 | into the first 4 bits of the instruction, and the remaining | |
24608 | four into bits 8 .. 11. */ | |
24609 | insn &= 0xfffff0f0; | |
24610 | insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); | |
24611 | ||
24612 | /* Update the instruction. */ | |
24613 | md_number_to_chars (buf, insn, INSN_SIZE); | |
24614 | } | |
4962c51a MS |
24615 | break; |
24616 | ||
24617 | case BFD_RELOC_ARM_LDC_PC_G0: | |
24618 | case BFD_RELOC_ARM_LDC_PC_G1: | |
24619 | case BFD_RELOC_ARM_LDC_PC_G2: | |
24620 | case BFD_RELOC_ARM_LDC_SB_G0: | |
24621 | case BFD_RELOC_ARM_LDC_SB_G1: | |
24622 | case BFD_RELOC_ARM_LDC_SB_G2: | |
9c2799c2 | 24623 | gas_assert (!fixP->fx_done); |
4962c51a | 24624 | if (!seg->use_rela_p) |
477330fc RM |
24625 | { |
24626 | bfd_vma insn; | |
24627 | bfd_vma addend_abs = abs (value); | |
4962c51a | 24628 | |
477330fc RM |
24629 | /* Check that the absolute value of the addend is a multiple of |
24630 | four and, when divided by four, fits in 8 bits. */ | |
24631 | if (addend_abs & 0x3) | |
4962c51a | 24632 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
24633 | _("bad offset 0x%08lX (must be word-aligned)"), |
24634 | (unsigned long) addend_abs); | |
4962c51a | 24635 | |
477330fc | 24636 | if ((addend_abs >> 2) > 0xff) |
4962c51a | 24637 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
24638 | _("bad offset 0x%08lX (must be an 8-bit number of words)"), |
24639 | (unsigned long) addend_abs); | |
24640 | ||
24641 | /* Extract the instruction. */ | |
24642 | insn = md_chars_to_number (buf, INSN_SIZE); | |
24643 | ||
24644 | /* If the addend is negative, clear bit 23 of the instruction. | |
24645 | Otherwise set it. */ | |
24646 | if (value < 0) | |
24647 | insn &= ~(1 << 23); | |
24648 | else | |
24649 | insn |= 1 << 23; | |
24650 | ||
24651 | /* Place the addend (divided by four) into the first eight | |
24652 | bits of the instruction. */ | |
24653 | insn &= 0xfffffff0; | |
24654 | insn |= addend_abs >> 2; | |
24655 | ||
24656 | /* Update the instruction. */ | |
24657 | md_number_to_chars (buf, insn, INSN_SIZE); | |
24658 | } | |
4962c51a MS |
24659 | break; |
24660 | ||
845b51d6 PB |
24661 | case BFD_RELOC_ARM_V4BX: |
24662 | /* This will need to go in the object file. */ | |
24663 | fixP->fx_done = 0; | |
24664 | break; | |
24665 | ||
c19d1205 ZW |
24666 | case BFD_RELOC_UNUSED: |
24667 | default: | |
24668 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
24669 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
24670 | } | |
6c43fab6 RE |
24671 | } |
24672 | ||
c19d1205 ZW |
24673 | /* Translate internal representation of relocation info to BFD target |
24674 | format. */ | |
a737bd4d | 24675 | |
c19d1205 | 24676 | arelent * |
00a97672 | 24677 | tc_gen_reloc (asection *section, fixS *fixp) |
a737bd4d | 24678 | { |
c19d1205 ZW |
24679 | arelent * reloc; |
24680 | bfd_reloc_code_real_type code; | |
a737bd4d | 24681 | |
325801bd | 24682 | reloc = XNEW (arelent); |
a737bd4d | 24683 | |
325801bd | 24684 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
c19d1205 ZW |
24685 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
24686 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 24687 | |
2fc8bdac | 24688 | if (fixp->fx_pcrel) |
00a97672 RS |
24689 | { |
24690 | if (section->use_rela_p) | |
24691 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
24692 | else | |
24693 | fixp->fx_offset = reloc->address; | |
24694 | } | |
c19d1205 | 24695 | reloc->addend = fixp->fx_offset; |
a737bd4d | 24696 | |
c19d1205 | 24697 | switch (fixp->fx_r_type) |
a737bd4d | 24698 | { |
c19d1205 ZW |
24699 | case BFD_RELOC_8: |
24700 | if (fixp->fx_pcrel) | |
24701 | { | |
24702 | code = BFD_RELOC_8_PCREL; | |
24703 | break; | |
24704 | } | |
1a0670f3 | 24705 | /* Fall through. */ |
a737bd4d | 24706 | |
c19d1205 ZW |
24707 | case BFD_RELOC_16: |
24708 | if (fixp->fx_pcrel) | |
24709 | { | |
24710 | code = BFD_RELOC_16_PCREL; | |
24711 | break; | |
24712 | } | |
1a0670f3 | 24713 | /* Fall through. */ |
6c43fab6 | 24714 | |
c19d1205 ZW |
24715 | case BFD_RELOC_32: |
24716 | if (fixp->fx_pcrel) | |
24717 | { | |
24718 | code = BFD_RELOC_32_PCREL; | |
24719 | break; | |
24720 | } | |
1a0670f3 | 24721 | /* Fall through. */ |
a737bd4d | 24722 | |
b6895b4f PB |
24723 | case BFD_RELOC_ARM_MOVW: |
24724 | if (fixp->fx_pcrel) | |
24725 | { | |
24726 | code = BFD_RELOC_ARM_MOVW_PCREL; | |
24727 | break; | |
24728 | } | |
1a0670f3 | 24729 | /* Fall through. */ |
b6895b4f PB |
24730 | |
24731 | case BFD_RELOC_ARM_MOVT: | |
24732 | if (fixp->fx_pcrel) | |
24733 | { | |
24734 | code = BFD_RELOC_ARM_MOVT_PCREL; | |
24735 | break; | |
24736 | } | |
1a0670f3 | 24737 | /* Fall through. */ |
b6895b4f PB |
24738 | |
24739 | case BFD_RELOC_ARM_THUMB_MOVW: | |
24740 | if (fixp->fx_pcrel) | |
24741 | { | |
24742 | code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; | |
24743 | break; | |
24744 | } | |
1a0670f3 | 24745 | /* Fall through. */ |
b6895b4f PB |
24746 | |
24747 | case BFD_RELOC_ARM_THUMB_MOVT: | |
24748 | if (fixp->fx_pcrel) | |
24749 | { | |
24750 | code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; | |
24751 | break; | |
24752 | } | |
1a0670f3 | 24753 | /* Fall through. */ |
b6895b4f | 24754 | |
c19d1205 ZW |
24755 | case BFD_RELOC_NONE: |
24756 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
24757 | case BFD_RELOC_ARM_PCREL_BLX: | |
24758 | case BFD_RELOC_RVA: | |
24759 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
24760 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
24761 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
24762 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
24763 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
24764 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
c19d1205 ZW |
24765 | case BFD_RELOC_VTABLE_ENTRY: |
24766 | case BFD_RELOC_VTABLE_INHERIT: | |
f0927246 NC |
24767 | #ifdef TE_PE |
24768 | case BFD_RELOC_32_SECREL: | |
24769 | #endif | |
c19d1205 ZW |
24770 | code = fixp->fx_r_type; |
24771 | break; | |
a737bd4d | 24772 | |
00adf2d4 JB |
24773 | case BFD_RELOC_THUMB_PCREL_BLX: |
24774 | #ifdef OBJ_ELF | |
24775 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
24776 | code = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
24777 | else | |
24778 | #endif | |
24779 | code = BFD_RELOC_THUMB_PCREL_BLX; | |
24780 | break; | |
24781 | ||
c19d1205 ZW |
24782 | case BFD_RELOC_ARM_LITERAL: |
24783 | case BFD_RELOC_ARM_HWLITERAL: | |
24784 | /* If this is called then the a literal has | |
24785 | been referenced across a section boundary. */ | |
24786 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
24787 | _("literal referenced across section boundary")); | |
24788 | return NULL; | |
a737bd4d | 24789 | |
c19d1205 | 24790 | #ifdef OBJ_ELF |
0855e32b NS |
24791 | case BFD_RELOC_ARM_TLS_CALL: |
24792 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
24793 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
24794 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
c19d1205 ZW |
24795 | case BFD_RELOC_ARM_GOT32: |
24796 | case BFD_RELOC_ARM_GOTOFF: | |
b43420e6 | 24797 | case BFD_RELOC_ARM_GOT_PREL: |
c19d1205 ZW |
24798 | case BFD_RELOC_ARM_PLT32: |
24799 | case BFD_RELOC_ARM_TARGET1: | |
24800 | case BFD_RELOC_ARM_ROSEGREL32: | |
24801 | case BFD_RELOC_ARM_SBREL32: | |
24802 | case BFD_RELOC_ARM_PREL31: | |
24803 | case BFD_RELOC_ARM_TARGET2: | |
c19d1205 | 24804 | case BFD_RELOC_ARM_TLS_LDO32: |
39b41c9c PB |
24805 | case BFD_RELOC_ARM_PCREL_CALL: |
24806 | case BFD_RELOC_ARM_PCREL_JUMP: | |
4962c51a MS |
24807 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
24808 | case BFD_RELOC_ARM_ALU_PC_G0: | |
24809 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
24810 | case BFD_RELOC_ARM_ALU_PC_G1: | |
24811 | case BFD_RELOC_ARM_ALU_PC_G2: | |
24812 | case BFD_RELOC_ARM_LDR_PC_G0: | |
24813 | case BFD_RELOC_ARM_LDR_PC_G1: | |
24814 | case BFD_RELOC_ARM_LDR_PC_G2: | |
24815 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
24816 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
24817 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
24818 | case BFD_RELOC_ARM_LDC_PC_G0: | |
24819 | case BFD_RELOC_ARM_LDC_PC_G1: | |
24820 | case BFD_RELOC_ARM_LDC_PC_G2: | |
24821 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
24822 | case BFD_RELOC_ARM_ALU_SB_G0: | |
24823 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
24824 | case BFD_RELOC_ARM_ALU_SB_G1: | |
24825 | case BFD_RELOC_ARM_ALU_SB_G2: | |
24826 | case BFD_RELOC_ARM_LDR_SB_G0: | |
24827 | case BFD_RELOC_ARM_LDR_SB_G1: | |
24828 | case BFD_RELOC_ARM_LDR_SB_G2: | |
24829 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
24830 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
24831 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
24832 | case BFD_RELOC_ARM_LDC_SB_G0: | |
24833 | case BFD_RELOC_ARM_LDC_SB_G1: | |
24834 | case BFD_RELOC_ARM_LDC_SB_G2: | |
845b51d6 | 24835 | case BFD_RELOC_ARM_V4BX: |
72d98d16 MG |
24836 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC: |
24837 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC: | |
24838 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC: | |
24839 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC: | |
188fd7ae CL |
24840 | case BFD_RELOC_ARM_GOTFUNCDESC: |
24841 | case BFD_RELOC_ARM_GOTOFFFUNCDESC: | |
24842 | case BFD_RELOC_ARM_FUNCDESC: | |
c19d1205 ZW |
24843 | code = fixp->fx_r_type; |
24844 | break; | |
a737bd4d | 24845 | |
0855e32b | 24846 | case BFD_RELOC_ARM_TLS_GOTDESC: |
c19d1205 | 24847 | case BFD_RELOC_ARM_TLS_GD32: |
5c5a4843 | 24848 | case BFD_RELOC_ARM_TLS_GD32_FDPIC: |
75c11999 | 24849 | case BFD_RELOC_ARM_TLS_LE32: |
c19d1205 | 24850 | case BFD_RELOC_ARM_TLS_IE32: |
5c5a4843 | 24851 | case BFD_RELOC_ARM_TLS_IE32_FDPIC: |
c19d1205 | 24852 | case BFD_RELOC_ARM_TLS_LDM32: |
5c5a4843 | 24853 | case BFD_RELOC_ARM_TLS_LDM32_FDPIC: |
c19d1205 ZW |
24854 | /* BFD will include the symbol's address in the addend. |
24855 | But we don't want that, so subtract it out again here. */ | |
24856 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
24857 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
24858 | code = fixp->fx_r_type; | |
24859 | break; | |
24860 | #endif | |
a737bd4d | 24861 | |
c19d1205 ZW |
24862 | case BFD_RELOC_ARM_IMMEDIATE: |
24863 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
24864 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
24865 | return NULL; | |
a737bd4d | 24866 | |
c19d1205 ZW |
24867 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
24868 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
24869 | _("ADRL used for a symbol not defined in the same file")); | |
24870 | return NULL; | |
a737bd4d | 24871 | |
c19d1205 | 24872 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
24873 | if (section->use_rela_p) |
24874 | { | |
24875 | code = fixp->fx_r_type; | |
24876 | break; | |
24877 | } | |
24878 | ||
c19d1205 ZW |
24879 | if (fixp->fx_addsy != NULL |
24880 | && !S_IS_DEFINED (fixp->fx_addsy) | |
24881 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 24882 | { |
c19d1205 ZW |
24883 | as_bad_where (fixp->fx_file, fixp->fx_line, |
24884 | _("undefined local label `%s'"), | |
24885 | S_GET_NAME (fixp->fx_addsy)); | |
24886 | return NULL; | |
a737bd4d NC |
24887 | } |
24888 | ||
c19d1205 ZW |
24889 | as_bad_where (fixp->fx_file, fixp->fx_line, |
24890 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
24891 | return NULL; | |
a737bd4d | 24892 | |
c19d1205 ZW |
24893 | default: |
24894 | { | |
e0471c16 | 24895 | const char * type; |
6c43fab6 | 24896 | |
c19d1205 ZW |
24897 | switch (fixp->fx_r_type) |
24898 | { | |
24899 | case BFD_RELOC_NONE: type = "NONE"; break; | |
24900 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
24901 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 24902 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
24903 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
24904 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
24905 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
db187cb9 | 24906 | case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break; |
8f06b2d8 | 24907 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
24908 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
24909 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
24910 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
24911 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
24912 | default: type = _("<unknown>"); break; | |
24913 | } | |
24914 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
24915 | _("cannot represent %s relocation in this object file format"), | |
24916 | type); | |
24917 | return NULL; | |
24918 | } | |
a737bd4d | 24919 | } |
6c43fab6 | 24920 | |
c19d1205 ZW |
24921 | #ifdef OBJ_ELF |
24922 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
24923 | && GOT_symbol | |
24924 | && fixp->fx_addsy == GOT_symbol) | |
24925 | { | |
24926 | code = BFD_RELOC_ARM_GOTPC; | |
24927 | reloc->addend = fixp->fx_offset = reloc->address; | |
24928 | } | |
24929 | #endif | |
6c43fab6 | 24930 | |
c19d1205 | 24931 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 24932 | |
c19d1205 ZW |
24933 | if (reloc->howto == NULL) |
24934 | { | |
24935 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
24936 | _("cannot represent %s relocation in this object file format"), | |
24937 | bfd_get_reloc_code_name (code)); | |
24938 | return NULL; | |
24939 | } | |
6c43fab6 | 24940 | |
c19d1205 ZW |
24941 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
24942 | vtable entry to be used in the relocation's section offset. */ | |
24943 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
24944 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 24945 | |
c19d1205 | 24946 | return reloc; |
6c43fab6 RE |
24947 | } |
24948 | ||
c19d1205 | 24949 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 24950 | |
c19d1205 ZW |
24951 | void |
24952 | cons_fix_new_arm (fragS * frag, | |
24953 | int where, | |
24954 | int size, | |
62ebcb5c AM |
24955 | expressionS * exp, |
24956 | bfd_reloc_code_real_type reloc) | |
6c43fab6 | 24957 | { |
c19d1205 | 24958 | int pcrel = 0; |
6c43fab6 | 24959 | |
c19d1205 ZW |
24960 | /* Pick a reloc. |
24961 | FIXME: @@ Should look at CPU word size. */ | |
24962 | switch (size) | |
24963 | { | |
24964 | case 1: | |
62ebcb5c | 24965 | reloc = BFD_RELOC_8; |
c19d1205 ZW |
24966 | break; |
24967 | case 2: | |
62ebcb5c | 24968 | reloc = BFD_RELOC_16; |
c19d1205 ZW |
24969 | break; |
24970 | case 4: | |
24971 | default: | |
62ebcb5c | 24972 | reloc = BFD_RELOC_32; |
c19d1205 ZW |
24973 | break; |
24974 | case 8: | |
62ebcb5c | 24975 | reloc = BFD_RELOC_64; |
c19d1205 ZW |
24976 | break; |
24977 | } | |
6c43fab6 | 24978 | |
f0927246 NC |
24979 | #ifdef TE_PE |
24980 | if (exp->X_op == O_secrel) | |
24981 | { | |
24982 | exp->X_op = O_symbol; | |
62ebcb5c | 24983 | reloc = BFD_RELOC_32_SECREL; |
f0927246 NC |
24984 | } |
24985 | #endif | |
24986 | ||
62ebcb5c | 24987 | fix_new_exp (frag, where, size, exp, pcrel, reloc); |
c19d1205 | 24988 | } |
6c43fab6 | 24989 | |
4343666d | 24990 | #if defined (OBJ_COFF) |
c19d1205 ZW |
24991 | void |
24992 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 24993 | { |
c19d1205 ZW |
24994 | /* If the destination of the branch is a defined symbol which does not have |
24995 | the THUMB_FUNC attribute, then we must be calling a function which has | |
24996 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
24997 | function and change the branch to refer to that function instead. */ | |
24998 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
24999 | && fixP->fx_addsy != NULL | |
25000 | && S_IS_DEFINED (fixP->fx_addsy) | |
25001 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 25002 | { |
c19d1205 | 25003 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 25004 | } |
c19d1205 ZW |
25005 | } |
25006 | #endif | |
6c43fab6 | 25007 | |
267bf995 | 25008 | |
c19d1205 ZW |
25009 | int |
25010 | arm_force_relocation (struct fix * fixp) | |
25011 | { | |
25012 | #if defined (OBJ_COFF) && defined (TE_PE) | |
25013 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
25014 | return 1; | |
25015 | #endif | |
6c43fab6 | 25016 | |
267bf995 RR |
25017 | /* In case we have a call or a branch to a function in ARM ISA mode from |
25018 | a thumb function or vice-versa force the relocation. These relocations | |
25019 | are cleared off for some cores that might have blx and simple transformations | |
25020 | are possible. */ | |
25021 | ||
25022 | #ifdef OBJ_ELF | |
25023 | switch (fixp->fx_r_type) | |
25024 | { | |
25025 | case BFD_RELOC_ARM_PCREL_JUMP: | |
25026 | case BFD_RELOC_ARM_PCREL_CALL: | |
25027 | case BFD_RELOC_THUMB_PCREL_BLX: | |
25028 | if (THUMB_IS_FUNC (fixp->fx_addsy)) | |
25029 | return 1; | |
25030 | break; | |
25031 | ||
25032 | case BFD_RELOC_ARM_PCREL_BLX: | |
25033 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
25034 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
25035 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
25036 | if (ARM_IS_FUNC (fixp->fx_addsy)) | |
25037 | return 1; | |
25038 | break; | |
25039 | ||
25040 | default: | |
25041 | break; | |
25042 | } | |
25043 | #endif | |
25044 | ||
b5884301 PB |
25045 | /* Resolve these relocations even if the symbol is extern or weak. |
25046 | Technically this is probably wrong due to symbol preemption. | |
25047 | In practice these relocations do not have enough range to be useful | |
25048 | at dynamic link time, and some code (e.g. in the Linux kernel) | |
25049 | expects these references to be resolved. */ | |
c19d1205 ZW |
25050 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE |
25051 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
b5884301 | 25052 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8 |
0110f2b8 | 25053 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
b5884301 PB |
25054 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
25055 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2 | |
25056 | || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET | |
16805f35 | 25057 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM |
0110f2b8 PB |
25058 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
25059 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
b5884301 PB |
25060 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM |
25061 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12 | |
25062 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM | |
25063 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2) | |
c19d1205 | 25064 | return 0; |
a737bd4d | 25065 | |
4962c51a MS |
25066 | /* Always leave these relocations for the linker. */ |
25067 | if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
25068 | && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
25069 | || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
25070 | return 1; | |
25071 | ||
f0291e4c PB |
25072 | /* Always generate relocations against function symbols. */ |
25073 | if (fixp->fx_r_type == BFD_RELOC_32 | |
25074 | && fixp->fx_addsy | |
25075 | && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) | |
25076 | return 1; | |
25077 | ||
c19d1205 | 25078 | return generic_force_reloc (fixp); |
404ff6b5 AH |
25079 | } |
25080 | ||
0ffdc86c | 25081 | #if defined (OBJ_ELF) || defined (OBJ_COFF) |
e28387c3 PB |
25082 | /* Relocations against function names must be left unadjusted, |
25083 | so that the linker can use this information to generate interworking | |
25084 | stubs. The MIPS version of this function | |
c19d1205 ZW |
25085 | also prevents relocations that are mips-16 specific, but I do not |
25086 | know why it does this. | |
404ff6b5 | 25087 | |
c19d1205 ZW |
25088 | FIXME: |
25089 | There is one other problem that ought to be addressed here, but | |
25090 | which currently is not: Taking the address of a label (rather | |
25091 | than a function) and then later jumping to that address. Such | |
25092 | addresses also ought to have their bottom bit set (assuming that | |
25093 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 25094 | |
c19d1205 ZW |
25095 | bfd_boolean |
25096 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 25097 | { |
c19d1205 ZW |
25098 | if (fixP->fx_addsy == NULL) |
25099 | return 1; | |
404ff6b5 | 25100 | |
e28387c3 PB |
25101 | /* Preserve relocations against symbols with function type. */ |
25102 | if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) | |
c921be7d | 25103 | return FALSE; |
e28387c3 | 25104 | |
c19d1205 ZW |
25105 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
25106 | && fixP->fx_subsy == NULL) | |
c921be7d | 25107 | return FALSE; |
a737bd4d | 25108 | |
c19d1205 ZW |
25109 | /* We need the symbol name for the VTABLE entries. */ |
25110 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
25111 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
c921be7d | 25112 | return FALSE; |
404ff6b5 | 25113 | |
c19d1205 ZW |
25114 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
25115 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
25116 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
25117 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
25118 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
5c5a4843 | 25119 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32_FDPIC |
c19d1205 ZW |
25120 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 |
25121 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
5c5a4843 | 25122 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32_FDPIC |
c19d1205 | 25123 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 |
5c5a4843 | 25124 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32_FDPIC |
c19d1205 | 25125 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 |
0855e32b NS |
25126 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC |
25127 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL | |
25128 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL | |
25129 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ | |
25130 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
c19d1205 | 25131 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) |
c921be7d | 25132 | return FALSE; |
a737bd4d | 25133 | |
4962c51a MS |
25134 | /* Similarly for group relocations. */ |
25135 | if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
25136 | && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
25137 | || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
c921be7d | 25138 | return FALSE; |
4962c51a | 25139 | |
79947c54 CD |
25140 | /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */ |
25141 | if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW | |
25142 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
25143 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL | |
25144 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL | |
25145 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
25146 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT | |
25147 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL | |
25148 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL) | |
c921be7d | 25149 | return FALSE; |
79947c54 | 25150 | |
72d98d16 MG |
25151 | /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited |
25152 | offsets, so keep these symbols. */ | |
25153 | if (fixP->fx_r_type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC | |
25154 | && fixP->fx_r_type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) | |
25155 | return FALSE; | |
25156 | ||
c921be7d | 25157 | return TRUE; |
a737bd4d | 25158 | } |
0ffdc86c NC |
25159 | #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ |
25160 | ||
25161 | #ifdef OBJ_ELF | |
c19d1205 ZW |
25162 | const char * |
25163 | elf32_arm_target_format (void) | |
404ff6b5 | 25164 | { |
c19d1205 ZW |
25165 | #ifdef TE_SYMBIAN |
25166 | return (target_big_endian | |
25167 | ? "elf32-bigarm-symbian" | |
25168 | : "elf32-littlearm-symbian"); | |
25169 | #elif defined (TE_VXWORKS) | |
25170 | return (target_big_endian | |
25171 | ? "elf32-bigarm-vxworks" | |
25172 | : "elf32-littlearm-vxworks"); | |
b38cadfb NC |
25173 | #elif defined (TE_NACL) |
25174 | return (target_big_endian | |
25175 | ? "elf32-bigarm-nacl" | |
25176 | : "elf32-littlearm-nacl"); | |
c19d1205 | 25177 | #else |
18a20338 CL |
25178 | if (arm_fdpic) |
25179 | { | |
25180 | if (target_big_endian) | |
25181 | return "elf32-bigarm-fdpic"; | |
25182 | else | |
25183 | return "elf32-littlearm-fdpic"; | |
25184 | } | |
c19d1205 | 25185 | else |
18a20338 CL |
25186 | { |
25187 | if (target_big_endian) | |
25188 | return "elf32-bigarm"; | |
25189 | else | |
25190 | return "elf32-littlearm"; | |
25191 | } | |
c19d1205 | 25192 | #endif |
404ff6b5 AH |
25193 | } |
25194 | ||
c19d1205 ZW |
25195 | void |
25196 | armelf_frob_symbol (symbolS * symp, | |
25197 | int * puntp) | |
404ff6b5 | 25198 | { |
c19d1205 ZW |
25199 | elf_frob_symbol (symp, puntp); |
25200 | } | |
25201 | #endif | |
404ff6b5 | 25202 | |
c19d1205 | 25203 | /* MD interface: Finalization. */ |
a737bd4d | 25204 | |
c19d1205 ZW |
25205 | void |
25206 | arm_cleanup (void) | |
25207 | { | |
25208 | literal_pool * pool; | |
a737bd4d | 25209 | |
e07e6e58 NC |
25210 | /* Ensure that all the IT blocks are properly closed. */ |
25211 | check_it_blocks_finished (); | |
25212 | ||
c19d1205 ZW |
25213 | for (pool = list_of_pools; pool; pool = pool->next) |
25214 | { | |
5f4273c7 | 25215 | /* Put it at the end of the relevant section. */ |
c19d1205 ZW |
25216 | subseg_set (pool->section, pool->sub_section); |
25217 | #ifdef OBJ_ELF | |
25218 | arm_elf_change_section (); | |
25219 | #endif | |
25220 | s_ltorg (0); | |
25221 | } | |
404ff6b5 AH |
25222 | } |
25223 | ||
cd000bff DJ |
25224 | #ifdef OBJ_ELF |
25225 | /* Remove any excess mapping symbols generated for alignment frags in | |
25226 | SEC. We may have created a mapping symbol before a zero byte | |
25227 | alignment; remove it if there's a mapping symbol after the | |
25228 | alignment. */ | |
25229 | static void | |
25230 | check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, | |
25231 | void *dummy ATTRIBUTE_UNUSED) | |
25232 | { | |
25233 | segment_info_type *seginfo = seg_info (sec); | |
25234 | fragS *fragp; | |
25235 | ||
25236 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
25237 | return; | |
25238 | ||
25239 | for (fragp = seginfo->frchainP->frch_root; | |
25240 | fragp != NULL; | |
25241 | fragp = fragp->fr_next) | |
25242 | { | |
25243 | symbolS *sym = fragp->tc_frag_data.last_map; | |
25244 | fragS *next = fragp->fr_next; | |
25245 | ||
25246 | /* Variable-sized frags have been converted to fixed size by | |
25247 | this point. But if this was variable-sized to start with, | |
25248 | there will be a fixed-size frag after it. So don't handle | |
25249 | next == NULL. */ | |
25250 | if (sym == NULL || next == NULL) | |
25251 | continue; | |
25252 | ||
25253 | if (S_GET_VALUE (sym) < next->fr_address) | |
25254 | /* Not at the end of this frag. */ | |
25255 | continue; | |
25256 | know (S_GET_VALUE (sym) == next->fr_address); | |
25257 | ||
25258 | do | |
25259 | { | |
25260 | if (next->tc_frag_data.first_map != NULL) | |
25261 | { | |
25262 | /* Next frag starts with a mapping symbol. Discard this | |
25263 | one. */ | |
25264 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
25265 | break; | |
25266 | } | |
25267 | ||
25268 | if (next->fr_next == NULL) | |
25269 | { | |
25270 | /* This mapping symbol is at the end of the section. Discard | |
25271 | it. */ | |
25272 | know (next->fr_fix == 0 && next->fr_var == 0); | |
25273 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
25274 | break; | |
25275 | } | |
25276 | ||
25277 | /* As long as we have empty frags without any mapping symbols, | |
25278 | keep looking. */ | |
25279 | /* If the next frag is non-empty and does not start with a | |
25280 | mapping symbol, then this mapping symbol is required. */ | |
25281 | if (next->fr_address != next->fr_next->fr_address) | |
25282 | break; | |
25283 | ||
25284 | next = next->fr_next; | |
25285 | } | |
25286 | while (next != NULL); | |
25287 | } | |
25288 | } | |
25289 | #endif | |
25290 | ||
c19d1205 ZW |
25291 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
25292 | ARM ones. */ | |
404ff6b5 | 25293 | |
c19d1205 ZW |
25294 | void |
25295 | arm_adjust_symtab (void) | |
404ff6b5 | 25296 | { |
c19d1205 ZW |
25297 | #ifdef OBJ_COFF |
25298 | symbolS * sym; | |
404ff6b5 | 25299 | |
c19d1205 ZW |
25300 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
25301 | { | |
25302 | if (ARM_IS_THUMB (sym)) | |
25303 | { | |
25304 | if (THUMB_IS_FUNC (sym)) | |
25305 | { | |
25306 | /* Mark the symbol as a Thumb function. */ | |
25307 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
25308 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
25309 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 25310 | |
c19d1205 ZW |
25311 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
25312 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
25313 | else | |
25314 | as_bad (_("%s: unexpected function type: %d"), | |
25315 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
25316 | } | |
25317 | else switch (S_GET_STORAGE_CLASS (sym)) | |
25318 | { | |
25319 | case C_EXT: | |
25320 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
25321 | break; | |
25322 | case C_STAT: | |
25323 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
25324 | break; | |
25325 | case C_LABEL: | |
25326 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
25327 | break; | |
25328 | default: | |
25329 | /* Do nothing. */ | |
25330 | break; | |
25331 | } | |
25332 | } | |
a737bd4d | 25333 | |
c19d1205 ZW |
25334 | if (ARM_IS_INTERWORK (sym)) |
25335 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 25336 | } |
c19d1205 ZW |
25337 | #endif |
25338 | #ifdef OBJ_ELF | |
25339 | symbolS * sym; | |
25340 | char bind; | |
404ff6b5 | 25341 | |
c19d1205 | 25342 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 25343 | { |
c19d1205 ZW |
25344 | if (ARM_IS_THUMB (sym)) |
25345 | { | |
25346 | elf_symbol_type * elf_sym; | |
404ff6b5 | 25347 | |
c19d1205 ZW |
25348 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
25349 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 25350 | |
b0796911 PB |
25351 | if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, |
25352 | BFD_ARM_SPECIAL_SYM_TYPE_ANY)) | |
c19d1205 ZW |
25353 | { |
25354 | /* If it's a .thumb_func, declare it as so, | |
25355 | otherwise tag label as .code 16. */ | |
25356 | if (THUMB_IS_FUNC (sym)) | |
39d911fc TP |
25357 | ARM_SET_SYM_BRANCH_TYPE (elf_sym->internal_elf_sym.st_target_internal, |
25358 | ST_BRANCH_TO_THUMB); | |
3ba67470 | 25359 | else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
c19d1205 ZW |
25360 | elf_sym->internal_elf_sym.st_info = |
25361 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
25362 | } | |
25363 | } | |
25364 | } | |
cd000bff DJ |
25365 | |
25366 | /* Remove any overlapping mapping symbols generated by alignment frags. */ | |
25367 | bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); | |
709001e9 MM |
25368 | /* Now do generic ELF adjustments. */ |
25369 | elf_adjust_symtab (); | |
c19d1205 | 25370 | #endif |
404ff6b5 AH |
25371 | } |
25372 | ||
c19d1205 | 25373 | /* MD interface: Initialization. */ |
404ff6b5 | 25374 | |
a737bd4d | 25375 | static void |
c19d1205 | 25376 | set_constant_flonums (void) |
a737bd4d | 25377 | { |
c19d1205 | 25378 | int i; |
404ff6b5 | 25379 | |
c19d1205 ZW |
25380 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
25381 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
25382 | abort (); | |
a737bd4d | 25383 | } |
404ff6b5 | 25384 | |
3e9e4fcf JB |
25385 | /* Auto-select Thumb mode if it's the only available instruction set for the |
25386 | given architecture. */ | |
25387 | ||
25388 | static void | |
25389 | autoselect_thumb_from_cpu_variant (void) | |
25390 | { | |
25391 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) | |
25392 | opcode_select (16); | |
25393 | } | |
25394 | ||
c19d1205 ZW |
25395 | void |
25396 | md_begin (void) | |
a737bd4d | 25397 | { |
c19d1205 ZW |
25398 | unsigned mach; |
25399 | unsigned int i; | |
404ff6b5 | 25400 | |
c19d1205 ZW |
25401 | if ( (arm_ops_hsh = hash_new ()) == NULL |
25402 | || (arm_cond_hsh = hash_new ()) == NULL | |
25403 | || (arm_shift_hsh = hash_new ()) == NULL | |
25404 | || (arm_psr_hsh = hash_new ()) == NULL | |
62b3e311 | 25405 | || (arm_v7m_psr_hsh = hash_new ()) == NULL |
c19d1205 | 25406 | || (arm_reg_hsh = hash_new ()) == NULL |
62b3e311 PB |
25407 | || (arm_reloc_hsh = hash_new ()) == NULL |
25408 | || (arm_barrier_opt_hsh = hash_new ()) == NULL) | |
c19d1205 ZW |
25409 | as_fatal (_("virtual memory exhausted")); |
25410 | ||
25411 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
d3ce72d0 | 25412 | hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i)); |
c19d1205 | 25413 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) |
d3ce72d0 | 25414 | hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i)); |
c19d1205 | 25415 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) |
5a49b8ac | 25416 | hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i)); |
c19d1205 | 25417 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 25418 | hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i)); |
62b3e311 | 25419 | for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 25420 | hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name, |
477330fc | 25421 | (void *) (v7m_psrs + i)); |
c19d1205 | 25422 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) |
5a49b8ac | 25423 | hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); |
62b3e311 PB |
25424 | for (i = 0; |
25425 | i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); | |
25426 | i++) | |
d3ce72d0 | 25427 | hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name, |
5a49b8ac | 25428 | (void *) (barrier_opt_names + i)); |
c19d1205 | 25429 | #ifdef OBJ_ELF |
3da1d841 NC |
25430 | for (i = 0; i < ARRAY_SIZE (reloc_names); i++) |
25431 | { | |
25432 | struct reloc_entry * entry = reloc_names + i; | |
25433 | ||
25434 | if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32) | |
25435 | /* This makes encode_branch() use the EABI versions of this relocation. */ | |
25436 | entry->reloc = BFD_RELOC_UNUSED; | |
25437 | ||
25438 | hash_insert (arm_reloc_hsh, entry->name, (void *) entry); | |
25439 | } | |
c19d1205 ZW |
25440 | #endif |
25441 | ||
25442 | set_constant_flonums (); | |
404ff6b5 | 25443 | |
c19d1205 ZW |
25444 | /* Set the cpu variant based on the command-line options. We prefer |
25445 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
25446 | -mfpu= over any other way of setting the floating point unit. | |
25447 | Use of legacy options with new options are faulted. */ | |
e74cfd16 | 25448 | if (legacy_cpu) |
404ff6b5 | 25449 | { |
e74cfd16 | 25450 | if (mcpu_cpu_opt || march_cpu_opt) |
c19d1205 ZW |
25451 | as_bad (_("use of old and new-style options to set CPU type")); |
25452 | ||
4d354d8b | 25453 | selected_arch = *legacy_cpu; |
404ff6b5 | 25454 | } |
4d354d8b TP |
25455 | else if (mcpu_cpu_opt) |
25456 | { | |
25457 | selected_arch = *mcpu_cpu_opt; | |
25458 | selected_ext = *mcpu_ext_opt; | |
25459 | } | |
25460 | else if (march_cpu_opt) | |
c168ce07 | 25461 | { |
4d354d8b TP |
25462 | selected_arch = *march_cpu_opt; |
25463 | selected_ext = *march_ext_opt; | |
c168ce07 | 25464 | } |
4d354d8b | 25465 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext); |
404ff6b5 | 25466 | |
e74cfd16 | 25467 | if (legacy_fpu) |
c19d1205 | 25468 | { |
e74cfd16 | 25469 | if (mfpu_opt) |
c19d1205 | 25470 | as_bad (_("use of old and new-style options to set FPU type")); |
03b1477f | 25471 | |
4d354d8b | 25472 | selected_fpu = *legacy_fpu; |
03b1477f | 25473 | } |
4d354d8b TP |
25474 | else if (mfpu_opt) |
25475 | selected_fpu = *mfpu_opt; | |
25476 | else | |
03b1477f | 25477 | { |
45eb4c1b NS |
25478 | #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \ |
25479 | || defined (TE_NetBSD) || defined (TE_VXWORKS)) | |
39c2da32 RE |
25480 | /* Some environments specify a default FPU. If they don't, infer it |
25481 | from the processor. */ | |
e74cfd16 | 25482 | if (mcpu_fpu_opt) |
4d354d8b | 25483 | selected_fpu = *mcpu_fpu_opt; |
e7da50fa | 25484 | else if (march_fpu_opt) |
4d354d8b | 25485 | selected_fpu = *march_fpu_opt; |
39c2da32 | 25486 | #else |
4d354d8b | 25487 | selected_fpu = fpu_default; |
39c2da32 | 25488 | #endif |
03b1477f RE |
25489 | } |
25490 | ||
4d354d8b | 25491 | if (ARM_FEATURE_ZERO (selected_fpu)) |
03b1477f | 25492 | { |
4d354d8b TP |
25493 | if (!no_cpu_selected ()) |
25494 | selected_fpu = fpu_default; | |
03b1477f | 25495 | else |
4d354d8b | 25496 | selected_fpu = fpu_arch_fpa; |
03b1477f RE |
25497 | } |
25498 | ||
ee065d83 | 25499 | #ifdef CPU_DEFAULT |
4d354d8b | 25500 | if (ARM_FEATURE_ZERO (selected_arch)) |
ee065d83 | 25501 | { |
4d354d8b TP |
25502 | selected_arch = cpu_default; |
25503 | selected_cpu = selected_arch; | |
ee065d83 | 25504 | } |
4d354d8b | 25505 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); |
e74cfd16 | 25506 | #else |
4d354d8b TP |
25507 | /* Autodection of feature mode: allow all features in cpu_variant but leave |
25508 | selected_cpu unset. It will be set in aeabi_set_public_attributes () | |
25509 | after all instruction have been processed and we can decide what CPU | |
25510 | should be selected. */ | |
25511 | if (ARM_FEATURE_ZERO (selected_arch)) | |
25512 | ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu); | |
ee065d83 | 25513 | else |
4d354d8b | 25514 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); |
ee065d83 | 25515 | #endif |
03b1477f | 25516 | |
3e9e4fcf JB |
25517 | autoselect_thumb_from_cpu_variant (); |
25518 | ||
e74cfd16 | 25519 | arm_arch_used = thumb_arch_used = arm_arch_none; |
ee065d83 | 25520 | |
f17c130b | 25521 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 25522 | { |
7cc69913 NC |
25523 | unsigned int flags = 0; |
25524 | ||
25525 | #if defined OBJ_ELF | |
25526 | flags = meabi_flags; | |
d507cf36 PB |
25527 | |
25528 | switch (meabi_flags) | |
33a392fb | 25529 | { |
d507cf36 | 25530 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 25531 | #endif |
d507cf36 PB |
25532 | /* Set the flags in the private structure. */ |
25533 | if (uses_apcs_26) flags |= F_APCS26; | |
25534 | if (support_interwork) flags |= F_INTERWORK; | |
25535 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 25536 | if (pic_code) flags |= F_PIC; |
e74cfd16 | 25537 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
7cc69913 NC |
25538 | flags |= F_SOFT_FLOAT; |
25539 | ||
d507cf36 PB |
25540 | switch (mfloat_abi_opt) |
25541 | { | |
25542 | case ARM_FLOAT_ABI_SOFT: | |
25543 | case ARM_FLOAT_ABI_SOFTFP: | |
25544 | flags |= F_SOFT_FLOAT; | |
25545 | break; | |
33a392fb | 25546 | |
d507cf36 PB |
25547 | case ARM_FLOAT_ABI_HARD: |
25548 | if (flags & F_SOFT_FLOAT) | |
25549 | as_bad (_("hard-float conflicts with specified fpu")); | |
25550 | break; | |
25551 | } | |
03b1477f | 25552 | |
e74cfd16 PB |
25553 | /* Using pure-endian doubles (even if soft-float). */ |
25554 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
7cc69913 | 25555 | flags |= F_VFP_FLOAT; |
f17c130b | 25556 | |
fde78edd | 25557 | #if defined OBJ_ELF |
e74cfd16 | 25558 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
d507cf36 | 25559 | flags |= EF_ARM_MAVERICK_FLOAT; |
d507cf36 PB |
25560 | break; |
25561 | ||
8cb51566 | 25562 | case EF_ARM_EABI_VER4: |
3a4a14e9 | 25563 | case EF_ARM_EABI_VER5: |
c19d1205 | 25564 | /* No additional flags to set. */ |
d507cf36 PB |
25565 | break; |
25566 | ||
25567 | default: | |
25568 | abort (); | |
25569 | } | |
7cc69913 | 25570 | #endif |
b99bd4ef NC |
25571 | bfd_set_private_flags (stdoutput, flags); |
25572 | ||
25573 | /* We have run out flags in the COFF header to encode the | |
25574 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 25575 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
25576 | if (atpcs) |
25577 | { | |
25578 | asection * sec; | |
25579 | ||
25580 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
25581 | ||
25582 | if (sec != NULL) | |
25583 | { | |
25584 | bfd_set_section_flags | |
25585 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
25586 | bfd_set_section_size (stdoutput, sec, 0); | |
25587 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
25588 | } | |
25589 | } | |
7cc69913 | 25590 | } |
f17c130b | 25591 | #endif |
b99bd4ef NC |
25592 | |
25593 | /* Record the CPU type as well. */ | |
2d447fca JM |
25594 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) |
25595 | mach = bfd_mach_arm_iWMMXt2; | |
25596 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) | |
e16bb312 | 25597 | mach = bfd_mach_arm_iWMMXt; |
e74cfd16 | 25598 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
b99bd4ef | 25599 | mach = bfd_mach_arm_XScale; |
e74cfd16 | 25600 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
fde78edd | 25601 | mach = bfd_mach_arm_ep9312; |
e74cfd16 | 25602 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
b99bd4ef | 25603 | mach = bfd_mach_arm_5TE; |
e74cfd16 | 25604 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
b99bd4ef | 25605 | { |
e74cfd16 | 25606 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
25607 | mach = bfd_mach_arm_5T; |
25608 | else | |
25609 | mach = bfd_mach_arm_5; | |
25610 | } | |
e74cfd16 | 25611 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
b99bd4ef | 25612 | { |
e74cfd16 | 25613 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
25614 | mach = bfd_mach_arm_4T; |
25615 | else | |
25616 | mach = bfd_mach_arm_4; | |
25617 | } | |
e74cfd16 | 25618 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
b99bd4ef | 25619 | mach = bfd_mach_arm_3M; |
e74cfd16 PB |
25620 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
25621 | mach = bfd_mach_arm_3; | |
25622 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) | |
25623 | mach = bfd_mach_arm_2a; | |
25624 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) | |
25625 | mach = bfd_mach_arm_2; | |
25626 | else | |
25627 | mach = bfd_mach_arm_unknown; | |
b99bd4ef NC |
25628 | |
25629 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
25630 | } | |
25631 | ||
c19d1205 | 25632 | /* Command line processing. */ |
b99bd4ef | 25633 | |
c19d1205 ZW |
25634 | /* md_parse_option |
25635 | Invocation line includes a switch not recognized by the base assembler. | |
25636 | See if it's a processor-specific option. | |
b99bd4ef | 25637 | |
c19d1205 ZW |
25638 | This routine is somewhat complicated by the need for backwards |
25639 | compatibility (since older releases of gcc can't be changed). | |
25640 | The new options try to make the interface as compatible as | |
25641 | possible with GCC. | |
b99bd4ef | 25642 | |
c19d1205 | 25643 | New options (supported) are: |
b99bd4ef | 25644 | |
c19d1205 ZW |
25645 | -mcpu=<cpu name> Assemble for selected processor |
25646 | -march=<architecture name> Assemble for selected architecture | |
25647 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
25648 | -EB/-mbig-endian Big-endian | |
25649 | -EL/-mlittle-endian Little-endian | |
25650 | -k Generate PIC code | |
25651 | -mthumb Start in Thumb mode | |
25652 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 25653 | |
278df34e | 25654 | -m[no-]warn-deprecated Warn about deprecated features |
8b2d793c | 25655 | -m[no-]warn-syms Warn when symbols match instructions |
267bf995 | 25656 | |
c19d1205 | 25657 | For now we will also provide support for: |
b99bd4ef | 25658 | |
c19d1205 ZW |
25659 | -mapcs-32 32-bit Program counter |
25660 | -mapcs-26 26-bit Program counter | |
25661 | -macps-float Floats passed in FP registers | |
25662 | -mapcs-reentrant Reentrant code | |
25663 | -matpcs | |
25664 | (sometime these will probably be replaced with -mapcs=<list of options> | |
25665 | and -matpcs=<list of options>) | |
b99bd4ef | 25666 | |
c19d1205 ZW |
25667 | The remaining options are only supported for back-wards compatibility. |
25668 | Cpu variants, the arm part is optional: | |
25669 | -m[arm]1 Currently not supported. | |
25670 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
25671 | -m[arm]3 Arm 3 processor | |
25672 | -m[arm]6[xx], Arm 6 processors | |
25673 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
25674 | -m[arm]8[10] Arm 8 processors | |
25675 | -m[arm]9[20][tdmi] Arm 9 processors | |
25676 | -mstrongarm[110[0]] StrongARM processors | |
25677 | -mxscale XScale processors | |
25678 | -m[arm]v[2345[t[e]]] Arm architectures | |
25679 | -mall All (except the ARM1) | |
25680 | FP variants: | |
25681 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
25682 | -mfpe-old (No float load/store multiples) | |
25683 | -mvfpxd VFP Single precision | |
25684 | -mvfp All VFP | |
25685 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 25686 | |
c19d1205 ZW |
25687 | The following CPU names are recognized: |
25688 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
25689 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
25690 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
25691 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
25692 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
25693 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
25694 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 25695 | |
c19d1205 | 25696 | */ |
b99bd4ef | 25697 | |
c19d1205 | 25698 | const char * md_shortopts = "m:k"; |
b99bd4ef | 25699 | |
c19d1205 ZW |
25700 | #ifdef ARM_BI_ENDIAN |
25701 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
25702 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 25703 | #else |
c19d1205 ZW |
25704 | #if TARGET_BYTES_BIG_ENDIAN |
25705 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 25706 | #else |
c19d1205 ZW |
25707 | #define OPTION_EL (OPTION_MD_BASE + 1) |
25708 | #endif | |
b99bd4ef | 25709 | #endif |
845b51d6 | 25710 | #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2) |
18a20338 | 25711 | #define OPTION_FDPIC (OPTION_MD_BASE + 3) |
b99bd4ef | 25712 | |
c19d1205 | 25713 | struct option md_longopts[] = |
b99bd4ef | 25714 | { |
c19d1205 ZW |
25715 | #ifdef OPTION_EB |
25716 | {"EB", no_argument, NULL, OPTION_EB}, | |
25717 | #endif | |
25718 | #ifdef OPTION_EL | |
25719 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 25720 | #endif |
845b51d6 | 25721 | {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, |
18a20338 CL |
25722 | #ifdef OBJ_ELF |
25723 | {"fdpic", no_argument, NULL, OPTION_FDPIC}, | |
25724 | #endif | |
c19d1205 ZW |
25725 | {NULL, no_argument, NULL, 0} |
25726 | }; | |
b99bd4ef | 25727 | |
c19d1205 | 25728 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 25729 | |
c19d1205 | 25730 | struct arm_option_table |
b99bd4ef | 25731 | { |
0198d5e6 TC |
25732 | const char * option; /* Option name to match. */ |
25733 | const char * help; /* Help information. */ | |
25734 | int * var; /* Variable to change. */ | |
25735 | int value; /* What to change it to. */ | |
25736 | const char * deprecated; /* If non-null, print this message. */ | |
c19d1205 | 25737 | }; |
b99bd4ef | 25738 | |
c19d1205 ZW |
25739 | struct arm_option_table arm_opts[] = |
25740 | { | |
25741 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
25742 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
25743 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
25744 | &support_interwork, 1, NULL}, | |
25745 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
25746 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
25747 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
25748 | 1, NULL}, | |
25749 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
25750 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
25751 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
25752 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
25753 | NULL}, | |
b99bd4ef | 25754 | |
c19d1205 ZW |
25755 | /* These are recognized by the assembler, but have no affect on code. */ |
25756 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
25757 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
278df34e NS |
25758 | |
25759 | {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL}, | |
25760 | {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"), | |
25761 | &warn_on_deprecated, 0, NULL}, | |
8b2d793c NC |
25762 | {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL}, |
25763 | {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL}, | |
e74cfd16 PB |
25764 | {NULL, NULL, NULL, 0, NULL} |
25765 | }; | |
25766 | ||
25767 | struct arm_legacy_option_table | |
25768 | { | |
0198d5e6 TC |
25769 | const char * option; /* Option name to match. */ |
25770 | const arm_feature_set ** var; /* Variable to change. */ | |
25771 | const arm_feature_set value; /* What to change it to. */ | |
25772 | const char * deprecated; /* If non-null, print this message. */ | |
e74cfd16 | 25773 | }; |
b99bd4ef | 25774 | |
e74cfd16 PB |
25775 | const struct arm_legacy_option_table arm_legacy_opts[] = |
25776 | { | |
c19d1205 ZW |
25777 | /* DON'T add any new processors to this list -- we want the whole list |
25778 | to go away... Add them to the processors table instead. */ | |
e74cfd16 PB |
25779 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
25780 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
25781 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
25782 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
25783 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
25784 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
25785 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
25786 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
25787 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
25788 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
25789 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
25790 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
25791 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
25792 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
25793 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
25794 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
25795 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
25796 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
25797 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
25798 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
25799 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
25800 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
25801 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
25802 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
25803 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
25804 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
25805 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
25806 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
25807 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
25808 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
25809 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
25810 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
25811 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
25812 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
25813 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
25814 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
25815 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
25816 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
25817 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
25818 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
25819 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
25820 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
25821 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
25822 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
25823 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
25824 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
25825 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
25826 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
25827 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
25828 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
25829 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
25830 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
25831 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
25832 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
25833 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
25834 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
25835 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
25836 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
25837 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
25838 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
25839 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
25840 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
25841 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
25842 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
25843 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
25844 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
25845 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
25846 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
25847 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
25848 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, | |
c19d1205 | 25849 | N_("use -mcpu=strongarm110")}, |
e74cfd16 | 25850 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 25851 | N_("use -mcpu=strongarm1100")}, |
e74cfd16 | 25852 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 25853 | N_("use -mcpu=strongarm1110")}, |
e74cfd16 PB |
25854 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
25855 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
25856 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 25857 | |
c19d1205 | 25858 | /* Architecture variants -- don't add any more to this list either. */ |
e74cfd16 PB |
25859 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
25860 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
25861 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
25862 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
25863 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
25864 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
25865 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
25866 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
25867 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
25868 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
25869 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
25870 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
25871 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
25872 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
25873 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
25874 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
25875 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
25876 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 25877 | |
c19d1205 | 25878 | /* Floating point variants -- don't add any more to this list either. */ |
0198d5e6 TC |
25879 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
25880 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
25881 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
25882 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, | |
c19d1205 | 25883 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
7ed4c4c5 | 25884 | |
e74cfd16 | 25885 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
c19d1205 | 25886 | }; |
7ed4c4c5 | 25887 | |
c19d1205 | 25888 | struct arm_cpu_option_table |
7ed4c4c5 | 25889 | { |
0198d5e6 TC |
25890 | const char * name; |
25891 | size_t name_len; | |
25892 | const arm_feature_set value; | |
25893 | const arm_feature_set ext; | |
c19d1205 ZW |
25894 | /* For some CPUs we assume an FPU unless the user explicitly sets |
25895 | -mfpu=... */ | |
0198d5e6 | 25896 | const arm_feature_set default_fpu; |
ee065d83 PB |
25897 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
25898 | case. */ | |
0198d5e6 | 25899 | const char * canonical_name; |
c19d1205 | 25900 | }; |
7ed4c4c5 | 25901 | |
c19d1205 ZW |
25902 | /* This list should, at a minimum, contain all the cpu names |
25903 | recognized by GCC. */ | |
996b5569 | 25904 | #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN } |
0198d5e6 | 25905 | |
e74cfd16 | 25906 | static const struct arm_cpu_option_table arm_cpus[] = |
c19d1205 | 25907 | { |
996b5569 TP |
25908 | ARM_CPU_OPT ("all", NULL, ARM_ANY, |
25909 | ARM_ARCH_NONE, | |
25910 | FPU_ARCH_FPA), | |
25911 | ARM_CPU_OPT ("arm1", NULL, ARM_ARCH_V1, | |
25912 | ARM_ARCH_NONE, | |
25913 | FPU_ARCH_FPA), | |
25914 | ARM_CPU_OPT ("arm2", NULL, ARM_ARCH_V2, | |
25915 | ARM_ARCH_NONE, | |
25916 | FPU_ARCH_FPA), | |
25917 | ARM_CPU_OPT ("arm250", NULL, ARM_ARCH_V2S, | |
25918 | ARM_ARCH_NONE, | |
25919 | FPU_ARCH_FPA), | |
25920 | ARM_CPU_OPT ("arm3", NULL, ARM_ARCH_V2S, | |
25921 | ARM_ARCH_NONE, | |
25922 | FPU_ARCH_FPA), | |
25923 | ARM_CPU_OPT ("arm6", NULL, ARM_ARCH_V3, | |
25924 | ARM_ARCH_NONE, | |
25925 | FPU_ARCH_FPA), | |
25926 | ARM_CPU_OPT ("arm60", NULL, ARM_ARCH_V3, | |
25927 | ARM_ARCH_NONE, | |
25928 | FPU_ARCH_FPA), | |
25929 | ARM_CPU_OPT ("arm600", NULL, ARM_ARCH_V3, | |
25930 | ARM_ARCH_NONE, | |
25931 | FPU_ARCH_FPA), | |
25932 | ARM_CPU_OPT ("arm610", NULL, ARM_ARCH_V3, | |
25933 | ARM_ARCH_NONE, | |
25934 | FPU_ARCH_FPA), | |
25935 | ARM_CPU_OPT ("arm620", NULL, ARM_ARCH_V3, | |
25936 | ARM_ARCH_NONE, | |
25937 | FPU_ARCH_FPA), | |
25938 | ARM_CPU_OPT ("arm7", NULL, ARM_ARCH_V3, | |
25939 | ARM_ARCH_NONE, | |
25940 | FPU_ARCH_FPA), | |
25941 | ARM_CPU_OPT ("arm7m", NULL, ARM_ARCH_V3M, | |
25942 | ARM_ARCH_NONE, | |
25943 | FPU_ARCH_FPA), | |
25944 | ARM_CPU_OPT ("arm7d", NULL, ARM_ARCH_V3, | |
25945 | ARM_ARCH_NONE, | |
25946 | FPU_ARCH_FPA), | |
25947 | ARM_CPU_OPT ("arm7dm", NULL, ARM_ARCH_V3M, | |
25948 | ARM_ARCH_NONE, | |
25949 | FPU_ARCH_FPA), | |
25950 | ARM_CPU_OPT ("arm7di", NULL, ARM_ARCH_V3, | |
25951 | ARM_ARCH_NONE, | |
25952 | FPU_ARCH_FPA), | |
25953 | ARM_CPU_OPT ("arm7dmi", NULL, ARM_ARCH_V3M, | |
25954 | ARM_ARCH_NONE, | |
25955 | FPU_ARCH_FPA), | |
25956 | ARM_CPU_OPT ("arm70", NULL, ARM_ARCH_V3, | |
25957 | ARM_ARCH_NONE, | |
25958 | FPU_ARCH_FPA), | |
25959 | ARM_CPU_OPT ("arm700", NULL, ARM_ARCH_V3, | |
25960 | ARM_ARCH_NONE, | |
25961 | FPU_ARCH_FPA), | |
25962 | ARM_CPU_OPT ("arm700i", NULL, ARM_ARCH_V3, | |
25963 | ARM_ARCH_NONE, | |
25964 | FPU_ARCH_FPA), | |
25965 | ARM_CPU_OPT ("arm710", NULL, ARM_ARCH_V3, | |
25966 | ARM_ARCH_NONE, | |
25967 | FPU_ARCH_FPA), | |
25968 | ARM_CPU_OPT ("arm710t", NULL, ARM_ARCH_V4T, | |
25969 | ARM_ARCH_NONE, | |
25970 | FPU_ARCH_FPA), | |
25971 | ARM_CPU_OPT ("arm720", NULL, ARM_ARCH_V3, | |
25972 | ARM_ARCH_NONE, | |
25973 | FPU_ARCH_FPA), | |
25974 | ARM_CPU_OPT ("arm720t", NULL, ARM_ARCH_V4T, | |
25975 | ARM_ARCH_NONE, | |
25976 | FPU_ARCH_FPA), | |
25977 | ARM_CPU_OPT ("arm740t", NULL, ARM_ARCH_V4T, | |
25978 | ARM_ARCH_NONE, | |
25979 | FPU_ARCH_FPA), | |
25980 | ARM_CPU_OPT ("arm710c", NULL, ARM_ARCH_V3, | |
25981 | ARM_ARCH_NONE, | |
25982 | FPU_ARCH_FPA), | |
25983 | ARM_CPU_OPT ("arm7100", NULL, ARM_ARCH_V3, | |
25984 | ARM_ARCH_NONE, | |
25985 | FPU_ARCH_FPA), | |
25986 | ARM_CPU_OPT ("arm7500", NULL, ARM_ARCH_V3, | |
25987 | ARM_ARCH_NONE, | |
25988 | FPU_ARCH_FPA), | |
25989 | ARM_CPU_OPT ("arm7500fe", NULL, ARM_ARCH_V3, | |
25990 | ARM_ARCH_NONE, | |
25991 | FPU_ARCH_FPA), | |
25992 | ARM_CPU_OPT ("arm7t", NULL, ARM_ARCH_V4T, | |
25993 | ARM_ARCH_NONE, | |
25994 | FPU_ARCH_FPA), | |
25995 | ARM_CPU_OPT ("arm7tdmi", NULL, ARM_ARCH_V4T, | |
25996 | ARM_ARCH_NONE, | |
25997 | FPU_ARCH_FPA), | |
25998 | ARM_CPU_OPT ("arm7tdmi-s", NULL, ARM_ARCH_V4T, | |
25999 | ARM_ARCH_NONE, | |
26000 | FPU_ARCH_FPA), | |
26001 | ARM_CPU_OPT ("arm8", NULL, ARM_ARCH_V4, | |
26002 | ARM_ARCH_NONE, | |
26003 | FPU_ARCH_FPA), | |
26004 | ARM_CPU_OPT ("arm810", NULL, ARM_ARCH_V4, | |
26005 | ARM_ARCH_NONE, | |
26006 | FPU_ARCH_FPA), | |
26007 | ARM_CPU_OPT ("strongarm", NULL, ARM_ARCH_V4, | |
26008 | ARM_ARCH_NONE, | |
26009 | FPU_ARCH_FPA), | |
26010 | ARM_CPU_OPT ("strongarm1", NULL, ARM_ARCH_V4, | |
26011 | ARM_ARCH_NONE, | |
26012 | FPU_ARCH_FPA), | |
26013 | ARM_CPU_OPT ("strongarm110", NULL, ARM_ARCH_V4, | |
26014 | ARM_ARCH_NONE, | |
26015 | FPU_ARCH_FPA), | |
26016 | ARM_CPU_OPT ("strongarm1100", NULL, ARM_ARCH_V4, | |
26017 | ARM_ARCH_NONE, | |
26018 | FPU_ARCH_FPA), | |
26019 | ARM_CPU_OPT ("strongarm1110", NULL, ARM_ARCH_V4, | |
26020 | ARM_ARCH_NONE, | |
26021 | FPU_ARCH_FPA), | |
26022 | ARM_CPU_OPT ("arm9", NULL, ARM_ARCH_V4T, | |
26023 | ARM_ARCH_NONE, | |
26024 | FPU_ARCH_FPA), | |
26025 | ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T, | |
26026 | ARM_ARCH_NONE, | |
26027 | FPU_ARCH_FPA), | |
26028 | ARM_CPU_OPT ("arm920t", NULL, ARM_ARCH_V4T, | |
26029 | ARM_ARCH_NONE, | |
26030 | FPU_ARCH_FPA), | |
26031 | ARM_CPU_OPT ("arm922t", NULL, ARM_ARCH_V4T, | |
26032 | ARM_ARCH_NONE, | |
26033 | FPU_ARCH_FPA), | |
26034 | ARM_CPU_OPT ("arm940t", NULL, ARM_ARCH_V4T, | |
26035 | ARM_ARCH_NONE, | |
26036 | FPU_ARCH_FPA), | |
26037 | ARM_CPU_OPT ("arm9tdmi", NULL, ARM_ARCH_V4T, | |
26038 | ARM_ARCH_NONE, | |
26039 | FPU_ARCH_FPA), | |
26040 | ARM_CPU_OPT ("fa526", NULL, ARM_ARCH_V4, | |
26041 | ARM_ARCH_NONE, | |
26042 | FPU_ARCH_FPA), | |
26043 | ARM_CPU_OPT ("fa626", NULL, ARM_ARCH_V4, | |
26044 | ARM_ARCH_NONE, | |
26045 | FPU_ARCH_FPA), | |
26046 | ||
c19d1205 ZW |
26047 | /* For V5 or later processors we default to using VFP; but the user |
26048 | should really set the FPU type explicitly. */ | |
996b5569 TP |
26049 | ARM_CPU_OPT ("arm9e-r0", NULL, ARM_ARCH_V5TExP, |
26050 | ARM_ARCH_NONE, | |
26051 | FPU_ARCH_VFP_V2), | |
26052 | ARM_CPU_OPT ("arm9e", NULL, ARM_ARCH_V5TE, | |
26053 | ARM_ARCH_NONE, | |
26054 | FPU_ARCH_VFP_V2), | |
26055 | ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ, | |
26056 | ARM_ARCH_NONE, | |
26057 | FPU_ARCH_VFP_V2), | |
26058 | ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ, | |
26059 | ARM_ARCH_NONE, | |
26060 | FPU_ARCH_VFP_V2), | |
26061 | ARM_CPU_OPT ("arm926ej-s", NULL, ARM_ARCH_V5TEJ, | |
26062 | ARM_ARCH_NONE, | |
26063 | FPU_ARCH_VFP_V2), | |
26064 | ARM_CPU_OPT ("arm946e-r0", NULL, ARM_ARCH_V5TExP, | |
26065 | ARM_ARCH_NONE, | |
26066 | FPU_ARCH_VFP_V2), | |
26067 | ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE, | |
26068 | ARM_ARCH_NONE, | |
26069 | FPU_ARCH_VFP_V2), | |
26070 | ARM_CPU_OPT ("arm946e-s", NULL, ARM_ARCH_V5TE, | |
26071 | ARM_ARCH_NONE, | |
26072 | FPU_ARCH_VFP_V2), | |
26073 | ARM_CPU_OPT ("arm966e-r0", NULL, ARM_ARCH_V5TExP, | |
26074 | ARM_ARCH_NONE, | |
26075 | FPU_ARCH_VFP_V2), | |
26076 | ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE, | |
26077 | ARM_ARCH_NONE, | |
26078 | FPU_ARCH_VFP_V2), | |
26079 | ARM_CPU_OPT ("arm966e-s", NULL, ARM_ARCH_V5TE, | |
26080 | ARM_ARCH_NONE, | |
26081 | FPU_ARCH_VFP_V2), | |
26082 | ARM_CPU_OPT ("arm968e-s", NULL, ARM_ARCH_V5TE, | |
26083 | ARM_ARCH_NONE, | |
26084 | FPU_ARCH_VFP_V2), | |
26085 | ARM_CPU_OPT ("arm10t", NULL, ARM_ARCH_V5T, | |
26086 | ARM_ARCH_NONE, | |
26087 | FPU_ARCH_VFP_V1), | |
26088 | ARM_CPU_OPT ("arm10tdmi", NULL, ARM_ARCH_V5T, | |
26089 | ARM_ARCH_NONE, | |
26090 | FPU_ARCH_VFP_V1), | |
26091 | ARM_CPU_OPT ("arm10e", NULL, ARM_ARCH_V5TE, | |
26092 | ARM_ARCH_NONE, | |
26093 | FPU_ARCH_VFP_V2), | |
26094 | ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE, | |
26095 | ARM_ARCH_NONE, | |
26096 | FPU_ARCH_VFP_V2), | |
26097 | ARM_CPU_OPT ("arm1020t", NULL, ARM_ARCH_V5T, | |
26098 | ARM_ARCH_NONE, | |
26099 | FPU_ARCH_VFP_V1), | |
26100 | ARM_CPU_OPT ("arm1020e", NULL, ARM_ARCH_V5TE, | |
26101 | ARM_ARCH_NONE, | |
26102 | FPU_ARCH_VFP_V2), | |
26103 | ARM_CPU_OPT ("arm1022e", NULL, ARM_ARCH_V5TE, | |
26104 | ARM_ARCH_NONE, | |
26105 | FPU_ARCH_VFP_V2), | |
26106 | ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ, | |
26107 | ARM_ARCH_NONE, | |
26108 | FPU_ARCH_VFP_V2), | |
26109 | ARM_CPU_OPT ("arm1026ej-s", NULL, ARM_ARCH_V5TEJ, | |
26110 | ARM_ARCH_NONE, | |
26111 | FPU_ARCH_VFP_V2), | |
26112 | ARM_CPU_OPT ("fa606te", NULL, ARM_ARCH_V5TE, | |
26113 | ARM_ARCH_NONE, | |
26114 | FPU_ARCH_VFP_V2), | |
26115 | ARM_CPU_OPT ("fa616te", NULL, ARM_ARCH_V5TE, | |
26116 | ARM_ARCH_NONE, | |
26117 | FPU_ARCH_VFP_V2), | |
26118 | ARM_CPU_OPT ("fa626te", NULL, ARM_ARCH_V5TE, | |
26119 | ARM_ARCH_NONE, | |
26120 | FPU_ARCH_VFP_V2), | |
26121 | ARM_CPU_OPT ("fmp626", NULL, ARM_ARCH_V5TE, | |
26122 | ARM_ARCH_NONE, | |
26123 | FPU_ARCH_VFP_V2), | |
26124 | ARM_CPU_OPT ("fa726te", NULL, ARM_ARCH_V5TE, | |
26125 | ARM_ARCH_NONE, | |
26126 | FPU_ARCH_VFP_V2), | |
26127 | ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6, | |
26128 | ARM_ARCH_NONE, | |
26129 | FPU_NONE), | |
26130 | ARM_CPU_OPT ("arm1136j-s", NULL, ARM_ARCH_V6, | |
26131 | ARM_ARCH_NONE, | |
26132 | FPU_NONE), | |
26133 | ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6, | |
26134 | ARM_ARCH_NONE, | |
26135 | FPU_ARCH_VFP_V2), | |
26136 | ARM_CPU_OPT ("arm1136jf-s", NULL, ARM_ARCH_V6, | |
26137 | ARM_ARCH_NONE, | |
26138 | FPU_ARCH_VFP_V2), | |
26139 | ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K, | |
26140 | ARM_ARCH_NONE, | |
26141 | FPU_ARCH_VFP_V2), | |
26142 | ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K, | |
26143 | ARM_ARCH_NONE, | |
26144 | FPU_NONE), | |
26145 | ARM_CPU_OPT ("arm1156t2-s", NULL, ARM_ARCH_V6T2, | |
26146 | ARM_ARCH_NONE, | |
26147 | FPU_NONE), | |
26148 | ARM_CPU_OPT ("arm1156t2f-s", NULL, ARM_ARCH_V6T2, | |
26149 | ARM_ARCH_NONE, | |
26150 | FPU_ARCH_VFP_V2), | |
26151 | ARM_CPU_OPT ("arm1176jz-s", NULL, ARM_ARCH_V6KZ, | |
26152 | ARM_ARCH_NONE, | |
26153 | FPU_NONE), | |
26154 | ARM_CPU_OPT ("arm1176jzf-s", NULL, ARM_ARCH_V6KZ, | |
26155 | ARM_ARCH_NONE, | |
26156 | FPU_ARCH_VFP_V2), | |
26157 | ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A, | |
26158 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), | |
26159 | FPU_NONE), | |
26160 | ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE, | |
26161 | ARM_ARCH_NONE, | |
26162 | FPU_ARCH_NEON_VFP_V4), | |
26163 | ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A, | |
26164 | ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), | |
26165 | ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)), | |
26166 | ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A, | |
26167 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), | |
26168 | ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)), | |
26169 | ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE, | |
26170 | ARM_ARCH_NONE, | |
26171 | FPU_ARCH_NEON_VFP_V4), | |
26172 | ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE, | |
26173 | ARM_ARCH_NONE, | |
26174 | FPU_ARCH_NEON_VFP_V4), | |
26175 | ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE, | |
26176 | ARM_ARCH_NONE, | |
26177 | FPU_ARCH_NEON_VFP_V4), | |
26178 | ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A, | |
26179 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
26180 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
26181 | ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A, | |
26182 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
26183 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
26184 | ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A, | |
26185 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
26186 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
15a7695f JG |
26187 | ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A, |
26188 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), | |
0198d5e6 | 26189 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), |
996b5569 TP |
26190 | ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A, |
26191 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
26192 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
26193 | ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A, | |
26194 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
26195 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
26196 | ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A, | |
26197 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
26198 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
15a7695f JG |
26199 | ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A, |
26200 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), | |
0198d5e6 | 26201 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), |
7ebd1359 | 26202 | ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A, |
26203 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), | |
26204 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), | |
996b5569 TP |
26205 | ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R, |
26206 | ARM_ARCH_NONE, | |
26207 | FPU_NONE), | |
26208 | ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R, | |
26209 | ARM_ARCH_NONE, | |
26210 | FPU_ARCH_VFP_V3D16), | |
26211 | ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R, | |
26212 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), | |
26213 | FPU_NONE), | |
26214 | ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R, | |
26215 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), | |
26216 | FPU_ARCH_VFP_V3D16), | |
26217 | ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R, | |
26218 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), | |
26219 | FPU_ARCH_VFP_V3D16), | |
0cda1e19 TP |
26220 | ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R, |
26221 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
26222 | FPU_ARCH_NEON_VFP_ARMV8), | |
996b5569 TP |
26223 | ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN, |
26224 | ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), | |
26225 | FPU_NONE), | |
26226 | ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE, | |
26227 | ARM_ARCH_NONE, | |
26228 | FPU_NONE), | |
26229 | ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM, | |
26230 | ARM_ARCH_NONE, | |
26231 | FPU_NONE), | |
26232 | ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM, | |
26233 | ARM_ARCH_NONE, | |
26234 | FPU_NONE), | |
26235 | ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M, | |
26236 | ARM_ARCH_NONE, | |
26237 | FPU_NONE), | |
26238 | ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM, | |
26239 | ARM_ARCH_NONE, | |
26240 | FPU_NONE), | |
26241 | ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM, | |
26242 | ARM_ARCH_NONE, | |
26243 | FPU_NONE), | |
26244 | ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM, | |
26245 | ARM_ARCH_NONE, | |
26246 | FPU_NONE), | |
26247 | ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A, | |
26248 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
26249 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
6b21c2bf | 26250 | |
c19d1205 | 26251 | /* ??? XSCALE is really an architecture. */ |
996b5569 TP |
26252 | ARM_CPU_OPT ("xscale", NULL, ARM_ARCH_XSCALE, |
26253 | ARM_ARCH_NONE, | |
26254 | FPU_ARCH_VFP_V2), | |
26255 | ||
c19d1205 | 26256 | /* ??? iwmmxt is not a processor. */ |
996b5569 TP |
26257 | ARM_CPU_OPT ("iwmmxt", NULL, ARM_ARCH_IWMMXT, |
26258 | ARM_ARCH_NONE, | |
26259 | FPU_ARCH_VFP_V2), | |
26260 | ARM_CPU_OPT ("iwmmxt2", NULL, ARM_ARCH_IWMMXT2, | |
26261 | ARM_ARCH_NONE, | |
26262 | FPU_ARCH_VFP_V2), | |
26263 | ARM_CPU_OPT ("i80200", NULL, ARM_ARCH_XSCALE, | |
26264 | ARM_ARCH_NONE, | |
26265 | FPU_ARCH_VFP_V2), | |
26266 | ||
0198d5e6 | 26267 | /* Maverick. */ |
996b5569 TP |
26268 | ARM_CPU_OPT ("ep9312", "ARM920T", |
26269 | ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), | |
26270 | ARM_ARCH_NONE, FPU_ARCH_MAVERICK), | |
26271 | ||
da4339ed | 26272 | /* Marvell processors. */ |
996b5569 TP |
26273 | ARM_CPU_OPT ("marvell-pj4", NULL, ARM_ARCH_V7A, |
26274 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), | |
26275 | FPU_ARCH_VFP_V3D16), | |
26276 | ARM_CPU_OPT ("marvell-whitney", NULL, ARM_ARCH_V7A, | |
26277 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), | |
26278 | FPU_ARCH_NEON_VFP_V4), | |
da4339ed | 26279 | |
996b5569 TP |
26280 | /* APM X-Gene family. */ |
26281 | ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A, | |
26282 | ARM_ARCH_NONE, | |
26283 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
26284 | ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A, | |
26285 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
26286 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
26287 | ||
26288 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL } | |
c19d1205 | 26289 | }; |
f3bad469 | 26290 | #undef ARM_CPU_OPT |
7ed4c4c5 | 26291 | |
c19d1205 | 26292 | struct arm_arch_option_table |
7ed4c4c5 | 26293 | { |
0198d5e6 TC |
26294 | const char * name; |
26295 | size_t name_len; | |
26296 | const arm_feature_set value; | |
26297 | const arm_feature_set default_fpu; | |
c19d1205 | 26298 | }; |
7ed4c4c5 | 26299 | |
c19d1205 ZW |
26300 | /* This list should, at a minimum, contain all the architecture names |
26301 | recognized by GCC. */ | |
f3bad469 | 26302 | #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF } |
0198d5e6 | 26303 | |
e74cfd16 | 26304 | static const struct arm_arch_option_table arm_archs[] = |
c19d1205 | 26305 | { |
497d849d TP |
26306 | ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA), |
26307 | ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA), | |
26308 | ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA), | |
26309 | ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
26310 | ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
26311 | ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA), | |
26312 | ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA), | |
26313 | ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA), | |
26314 | ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA), | |
26315 | ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA), | |
26316 | ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA), | |
26317 | ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP), | |
26318 | ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP), | |
26319 | ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP), | |
26320 | ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP), | |
26321 | ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP), | |
26322 | ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP), | |
26323 | ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP), | |
26324 | ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP), | |
26325 | ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP), | |
26326 | ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP), | |
f33026a9 MW |
26327 | /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is |
26328 | kept to preserve existing behaviour. */ | |
497d849d TP |
26329 | ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ, FPU_ARCH_VFP), |
26330 | ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ, FPU_ARCH_VFP), | |
26331 | ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP), | |
26332 | ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP), | |
26333 | ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP), | |
f33026a9 MW |
26334 | /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is |
26335 | kept to preserve existing behaviour. */ | |
497d849d TP |
26336 | ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP), |
26337 | ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP), | |
26338 | ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP), | |
26339 | ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP), | |
26340 | ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP), | |
c450d570 PB |
26341 | /* The official spelling of the ARMv7 profile variants is the dashed form. |
26342 | Accept the non-dashed form for compatibility with old toolchains. */ | |
497d849d TP |
26343 | ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP), |
26344 | ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP), | |
26345 | ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP), | |
26346 | ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP), | |
26347 | ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP), | |
26348 | ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP), | |
26349 | ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP), | |
26350 | ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP), | |
26351 | ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP), | |
26352 | ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP), | |
26353 | ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP), | |
26354 | ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP), | |
26355 | ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP), | |
26356 | ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A, FPU_ARCH_VFP), | |
26357 | ARM_ARCH_OPT ("armv8-r", ARM_ARCH_V8R, FPU_ARCH_VFP), | |
26358 | ARM_ARCH_OPT ("armv8.4-a", ARM_ARCH_V8_4A, FPU_ARCH_VFP), | |
26359 | ARM_ARCH_OPT ("armv8.5-a", ARM_ARCH_V8_5A, FPU_ARCH_VFP), | |
26360 | ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP), | |
26361 | ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP), | |
26362 | ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2, FPU_ARCH_VFP), | |
f3bad469 | 26363 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } |
c19d1205 | 26364 | }; |
f3bad469 | 26365 | #undef ARM_ARCH_OPT |
7ed4c4c5 | 26366 | |
69133863 | 26367 | /* ISA extensions in the co-processor and main instruction set space. */ |
0198d5e6 | 26368 | |
69133863 | 26369 | struct arm_option_extension_value_table |
c19d1205 | 26370 | { |
0198d5e6 TC |
26371 | const char * name; |
26372 | size_t name_len; | |
26373 | const arm_feature_set merge_value; | |
26374 | const arm_feature_set clear_value; | |
d942732e TP |
26375 | /* List of architectures for which an extension is available. ARM_ARCH_NONE |
26376 | indicates that an extension is available for all architectures while | |
26377 | ARM_ANY marks an empty entry. */ | |
0198d5e6 | 26378 | const arm_feature_set allowed_archs[2]; |
c19d1205 | 26379 | }; |
7ed4c4c5 | 26380 | |
0198d5e6 TC |
26381 | /* The following table must be in alphabetical order with a NULL last entry. */ |
26382 | ||
d942732e TP |
26383 | #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } } |
26384 | #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} } | |
0198d5e6 | 26385 | |
69133863 | 26386 | static const struct arm_option_extension_value_table arm_extensions[] = |
c19d1205 | 26387 | { |
823d2571 TG |
26388 | ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8), |
26389 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
bca38921 | 26390 | ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
823d2571 TG |
26391 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8), |
26392 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
c604a79a JW |
26393 | ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8, |
26394 | ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), | |
26395 | ARM_ARCH_V8_2A), | |
15afaa63 TP |
26396 | ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), |
26397 | ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), | |
26398 | ARM_FEATURE_CORE (ARM_EXT_V7M, ARM_EXT2_V8M)), | |
823d2571 TG |
26399 | ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8), |
26400 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
b8ec4e87 JW |
26401 | ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
26402 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), | |
26403 | ARM_ARCH_V8_2A), | |
01f48020 TC |
26404 | ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST |
26405 | | ARM_EXT2_FP16_FML), | |
26406 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | |
26407 | | ARM_EXT2_FP16_FML), | |
26408 | ARM_ARCH_V8_2A), | |
d942732e | 26409 | ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV), |
823d2571 | 26410 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV), |
d942732e TP |
26411 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A), |
26412 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)), | |
3d030cdb TP |
26413 | /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of |
26414 | Thumb divide instruction. Due to this having the same name as the | |
26415 | previous entry, this will be ignored when doing command-line parsing and | |
26416 | only considered by build attribute selection code. */ | |
26417 | ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), | |
26418 | ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), | |
26419 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7)), | |
823d2571 | 26420 | ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), |
d942732e | 26421 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ARCH_NONE), |
823d2571 | 26422 | ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), |
d942732e | 26423 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ARCH_NONE), |
823d2571 | 26424 | ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), |
d942732e TP |
26425 | ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ARCH_NONE), |
26426 | ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP), | |
823d2571 | 26427 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP), |
d942732e TP |
26428 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A), |
26429 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)), | |
823d2571 TG |
26430 | ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS), |
26431 | ARM_FEATURE_CORE_LOW (ARM_EXT_OS), | |
26432 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)), | |
ddfded2f MW |
26433 | ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), |
26434 | ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0), | |
ced40572 | 26435 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)), |
dad0c3bf SD |
26436 | ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES), |
26437 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES), | |
26438 | ARM_ARCH_V8A), | |
4d1464f2 MW |
26439 | ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), |
26440 | ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0), | |
ced40572 | 26441 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)), |
643afb90 MW |
26442 | ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1, |
26443 | ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA), | |
ced40572 | 26444 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)), |
7fadb25d SD |
26445 | ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), |
26446 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), | |
26447 | ARM_ARCH_V8A), | |
d942732e | 26448 | ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), |
823d2571 | 26449 | ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), |
d942732e TP |
26450 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), |
26451 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)), | |
643afb90 MW |
26452 | ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8, |
26453 | ARM_FEATURE_COPROC (FPU_NEON_ARMV8), | |
26454 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
823d2571 TG |
26455 | ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV |
26456 | | ARM_EXT_DIV), | |
26457 | ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), | |
26458 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)), | |
26459 | ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), | |
d942732e TP |
26460 | ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ARCH_NONE), |
26461 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, { ARM_ARCH_NONE, ARM_ARCH_NONE } } | |
69133863 | 26462 | }; |
f3bad469 | 26463 | #undef ARM_EXT_OPT |
69133863 MGD |
26464 | |
26465 | /* ISA floating-point and Advanced SIMD extensions. */ | |
26466 | struct arm_option_fpu_value_table | |
26467 | { | |
0198d5e6 TC |
26468 | const char * name; |
26469 | const arm_feature_set value; | |
c19d1205 | 26470 | }; |
7ed4c4c5 | 26471 | |
c19d1205 ZW |
26472 | /* This list should, at a minimum, contain all the fpu names |
26473 | recognized by GCC. */ | |
69133863 | 26474 | static const struct arm_option_fpu_value_table arm_fpus[] = |
c19d1205 ZW |
26475 | { |
26476 | {"softfpa", FPU_NONE}, | |
26477 | {"fpe", FPU_ARCH_FPE}, | |
26478 | {"fpe2", FPU_ARCH_FPE}, | |
26479 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
26480 | {"fpa", FPU_ARCH_FPA}, | |
26481 | {"fpa10", FPU_ARCH_FPA}, | |
26482 | {"fpa11", FPU_ARCH_FPA}, | |
26483 | {"arm7500fe", FPU_ARCH_FPA}, | |
26484 | {"softvfp", FPU_ARCH_VFP}, | |
26485 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
26486 | {"vfp", FPU_ARCH_VFP_V2}, | |
26487 | {"vfp9", FPU_ARCH_VFP_V2}, | |
d5e0ba9c | 26488 | {"vfp3", FPU_ARCH_VFP_V3}, /* Undocumented, use vfpv3. */ |
c19d1205 ZW |
26489 | {"vfp10", FPU_ARCH_VFP_V2}, |
26490 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
26491 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
b1cc4aeb PB |
26492 | {"vfpv2", FPU_ARCH_VFP_V2}, |
26493 | {"vfpv3", FPU_ARCH_VFP_V3}, | |
62f3b8c8 | 26494 | {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16}, |
b1cc4aeb | 26495 | {"vfpv3-d16", FPU_ARCH_VFP_V3D16}, |
62f3b8c8 PB |
26496 | {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16}, |
26497 | {"vfpv3xd", FPU_ARCH_VFP_V3xD}, | |
26498 | {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16}, | |
c19d1205 ZW |
26499 | {"arm1020t", FPU_ARCH_VFP_V1}, |
26500 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
d5e0ba9c | 26501 | {"arm1136jfs", FPU_ARCH_VFP_V2}, /* Undocumented, use arm1136jf-s. */ |
c19d1205 ZW |
26502 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, |
26503 | {"maverick", FPU_ARCH_MAVERICK}, | |
d5e0ba9c | 26504 | {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
d3375ddd | 26505 | {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
8e79c3df | 26506 | {"neon-fp16", FPU_ARCH_NEON_FP16}, |
62f3b8c8 PB |
26507 | {"vfpv4", FPU_ARCH_VFP_V4}, |
26508 | {"vfpv4-d16", FPU_ARCH_VFP_V4D16}, | |
ada65aa3 | 26509 | {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16}, |
a715796b TG |
26510 | {"fpv5-d16", FPU_ARCH_VFP_V5D16}, |
26511 | {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16}, | |
62f3b8c8 | 26512 | {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4}, |
bca38921 MGD |
26513 | {"fp-armv8", FPU_ARCH_VFP_ARMV8}, |
26514 | {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8}, | |
26515 | {"crypto-neon-fp-armv8", | |
26516 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8}, | |
d6b4b13e | 26517 | {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1}, |
081e4c7d MW |
26518 | {"crypto-neon-fp-armv8.1", |
26519 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1}, | |
e74cfd16 PB |
26520 | {NULL, ARM_ARCH_NONE} |
26521 | }; | |
26522 | ||
26523 | struct arm_option_value_table | |
26524 | { | |
e0471c16 | 26525 | const char *name; |
e74cfd16 | 26526 | long value; |
c19d1205 | 26527 | }; |
7ed4c4c5 | 26528 | |
e74cfd16 | 26529 | static const struct arm_option_value_table arm_float_abis[] = |
c19d1205 ZW |
26530 | { |
26531 | {"hard", ARM_FLOAT_ABI_HARD}, | |
26532 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
26533 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
e74cfd16 | 26534 | {NULL, 0} |
c19d1205 | 26535 | }; |
7ed4c4c5 | 26536 | |
c19d1205 | 26537 | #ifdef OBJ_ELF |
3a4a14e9 | 26538 | /* We only know how to output GNU and ver 4/5 (AAELF) formats. */ |
e74cfd16 | 26539 | static const struct arm_option_value_table arm_eabis[] = |
c19d1205 ZW |
26540 | { |
26541 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
26542 | {"4", EF_ARM_EABI_VER4}, | |
3a4a14e9 | 26543 | {"5", EF_ARM_EABI_VER5}, |
e74cfd16 | 26544 | {NULL, 0} |
c19d1205 ZW |
26545 | }; |
26546 | #endif | |
7ed4c4c5 | 26547 | |
c19d1205 ZW |
26548 | struct arm_long_option_table |
26549 | { | |
0198d5e6 | 26550 | const char * option; /* Substring to match. */ |
e0471c16 | 26551 | const char * help; /* Help information. */ |
17b9d67d | 26552 | int (* func) (const char * subopt); /* Function to decode sub-option. */ |
e0471c16 | 26553 | const char * deprecated; /* If non-null, print this message. */ |
c19d1205 | 26554 | }; |
7ed4c4c5 | 26555 | |
c921be7d | 26556 | static bfd_boolean |
c168ce07 | 26557 | arm_parse_extension (const char *str, const arm_feature_set *opt_set, |
4d354d8b | 26558 | arm_feature_set *ext_set) |
7ed4c4c5 | 26559 | { |
69133863 | 26560 | /* We insist on extensions being specified in alphabetical order, and with |
fa94de6b RM |
26561 | extensions being added before being removed. We achieve this by having |
26562 | the global ARM_EXTENSIONS table in alphabetical order, and using the | |
69133863 | 26563 | ADDING_VALUE variable to indicate whether we are adding an extension (1) |
fa94de6b | 26564 | or removing it (0) and only allowing it to change in the order |
69133863 MGD |
26565 | -1 -> 1 -> 0. */ |
26566 | const struct arm_option_extension_value_table * opt = NULL; | |
d942732e | 26567 | const arm_feature_set arm_any = ARM_ANY; |
69133863 MGD |
26568 | int adding_value = -1; |
26569 | ||
c19d1205 | 26570 | while (str != NULL && *str != 0) |
7ed4c4c5 | 26571 | { |
82b8a785 | 26572 | const char *ext; |
f3bad469 | 26573 | size_t len; |
7ed4c4c5 | 26574 | |
c19d1205 ZW |
26575 | if (*str != '+') |
26576 | { | |
26577 | as_bad (_("invalid architectural extension")); | |
c921be7d | 26578 | return FALSE; |
c19d1205 | 26579 | } |
7ed4c4c5 | 26580 | |
c19d1205 ZW |
26581 | str++; |
26582 | ext = strchr (str, '+'); | |
7ed4c4c5 | 26583 | |
c19d1205 | 26584 | if (ext != NULL) |
f3bad469 | 26585 | len = ext - str; |
c19d1205 | 26586 | else |
f3bad469 | 26587 | len = strlen (str); |
7ed4c4c5 | 26588 | |
f3bad469 | 26589 | if (len >= 2 && strncmp (str, "no", 2) == 0) |
69133863 MGD |
26590 | { |
26591 | if (adding_value != 0) | |
26592 | { | |
26593 | adding_value = 0; | |
26594 | opt = arm_extensions; | |
26595 | } | |
26596 | ||
f3bad469 | 26597 | len -= 2; |
69133863 MGD |
26598 | str += 2; |
26599 | } | |
f3bad469 | 26600 | else if (len > 0) |
69133863 MGD |
26601 | { |
26602 | if (adding_value == -1) | |
26603 | { | |
26604 | adding_value = 1; | |
26605 | opt = arm_extensions; | |
26606 | } | |
26607 | else if (adding_value != 1) | |
26608 | { | |
26609 | as_bad (_("must specify extensions to add before specifying " | |
26610 | "those to remove")); | |
26611 | return FALSE; | |
26612 | } | |
26613 | } | |
26614 | ||
f3bad469 | 26615 | if (len == 0) |
c19d1205 ZW |
26616 | { |
26617 | as_bad (_("missing architectural extension")); | |
c921be7d | 26618 | return FALSE; |
c19d1205 | 26619 | } |
7ed4c4c5 | 26620 | |
69133863 MGD |
26621 | gas_assert (adding_value != -1); |
26622 | gas_assert (opt != NULL); | |
26623 | ||
26624 | /* Scan over the options table trying to find an exact match. */ | |
26625 | for (; opt->name != NULL; opt++) | |
f3bad469 | 26626 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 26627 | { |
d942732e TP |
26628 | int i, nb_allowed_archs = |
26629 | sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]); | |
69133863 | 26630 | /* Check we can apply the extension to this architecture. */ |
d942732e TP |
26631 | for (i = 0; i < nb_allowed_archs; i++) |
26632 | { | |
26633 | /* Empty entry. */ | |
26634 | if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any)) | |
26635 | continue; | |
c168ce07 | 26636 | if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *opt_set)) |
d942732e TP |
26637 | break; |
26638 | } | |
26639 | if (i == nb_allowed_archs) | |
69133863 MGD |
26640 | { |
26641 | as_bad (_("extension does not apply to the base architecture")); | |
26642 | return FALSE; | |
26643 | } | |
26644 | ||
26645 | /* Add or remove the extension. */ | |
26646 | if (adding_value) | |
4d354d8b | 26647 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value); |
69133863 | 26648 | else |
4d354d8b | 26649 | ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value); |
69133863 | 26650 | |
3d030cdb TP |
26651 | /* Allowing Thumb division instructions for ARMv7 in autodetection |
26652 | rely on this break so that duplicate extensions (extensions | |
26653 | with the same name as a previous extension in the list) are not | |
26654 | considered for command-line parsing. */ | |
c19d1205 ZW |
26655 | break; |
26656 | } | |
7ed4c4c5 | 26657 | |
c19d1205 ZW |
26658 | if (opt->name == NULL) |
26659 | { | |
69133863 MGD |
26660 | /* Did we fail to find an extension because it wasn't specified in |
26661 | alphabetical order, or because it does not exist? */ | |
26662 | ||
26663 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
f3bad469 | 26664 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
69133863 MGD |
26665 | break; |
26666 | ||
26667 | if (opt->name == NULL) | |
26668 | as_bad (_("unknown architectural extension `%s'"), str); | |
26669 | else | |
26670 | as_bad (_("architectural extensions must be specified in " | |
26671 | "alphabetical order")); | |
26672 | ||
c921be7d | 26673 | return FALSE; |
c19d1205 | 26674 | } |
69133863 MGD |
26675 | else |
26676 | { | |
26677 | /* We should skip the extension we've just matched the next time | |
26678 | round. */ | |
26679 | opt++; | |
26680 | } | |
7ed4c4c5 | 26681 | |
c19d1205 ZW |
26682 | str = ext; |
26683 | }; | |
7ed4c4c5 | 26684 | |
c921be7d | 26685 | return TRUE; |
c19d1205 | 26686 | } |
7ed4c4c5 | 26687 | |
c921be7d | 26688 | static bfd_boolean |
17b9d67d | 26689 | arm_parse_cpu (const char *str) |
7ed4c4c5 | 26690 | { |
f3bad469 | 26691 | const struct arm_cpu_option_table *opt; |
82b8a785 | 26692 | const char *ext = strchr (str, '+'); |
f3bad469 | 26693 | size_t len; |
7ed4c4c5 | 26694 | |
c19d1205 | 26695 | if (ext != NULL) |
f3bad469 | 26696 | len = ext - str; |
7ed4c4c5 | 26697 | else |
f3bad469 | 26698 | len = strlen (str); |
7ed4c4c5 | 26699 | |
f3bad469 | 26700 | if (len == 0) |
7ed4c4c5 | 26701 | { |
c19d1205 | 26702 | as_bad (_("missing cpu name `%s'"), str); |
c921be7d | 26703 | return FALSE; |
7ed4c4c5 NC |
26704 | } |
26705 | ||
c19d1205 | 26706 | for (opt = arm_cpus; opt->name != NULL; opt++) |
f3bad469 | 26707 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 26708 | { |
c168ce07 | 26709 | mcpu_cpu_opt = &opt->value; |
4d354d8b TP |
26710 | if (mcpu_ext_opt == NULL) |
26711 | mcpu_ext_opt = XNEW (arm_feature_set); | |
26712 | *mcpu_ext_opt = opt->ext; | |
e74cfd16 | 26713 | mcpu_fpu_opt = &opt->default_fpu; |
ee065d83 | 26714 | if (opt->canonical_name) |
ef8e6722 JW |
26715 | { |
26716 | gas_assert (sizeof selected_cpu_name > strlen (opt->canonical_name)); | |
26717 | strcpy (selected_cpu_name, opt->canonical_name); | |
26718 | } | |
ee065d83 PB |
26719 | else |
26720 | { | |
f3bad469 | 26721 | size_t i; |
c921be7d | 26722 | |
ef8e6722 JW |
26723 | if (len >= sizeof selected_cpu_name) |
26724 | len = (sizeof selected_cpu_name) - 1; | |
26725 | ||
f3bad469 | 26726 | for (i = 0; i < len; i++) |
ee065d83 PB |
26727 | selected_cpu_name[i] = TOUPPER (opt->name[i]); |
26728 | selected_cpu_name[i] = 0; | |
26729 | } | |
7ed4c4c5 | 26730 | |
c19d1205 | 26731 | if (ext != NULL) |
4d354d8b | 26732 | return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt); |
7ed4c4c5 | 26733 | |
c921be7d | 26734 | return TRUE; |
c19d1205 | 26735 | } |
7ed4c4c5 | 26736 | |
c19d1205 | 26737 | as_bad (_("unknown cpu `%s'"), str); |
c921be7d | 26738 | return FALSE; |
7ed4c4c5 NC |
26739 | } |
26740 | ||
c921be7d | 26741 | static bfd_boolean |
17b9d67d | 26742 | arm_parse_arch (const char *str) |
7ed4c4c5 | 26743 | { |
e74cfd16 | 26744 | const struct arm_arch_option_table *opt; |
82b8a785 | 26745 | const char *ext = strchr (str, '+'); |
f3bad469 | 26746 | size_t len; |
7ed4c4c5 | 26747 | |
c19d1205 | 26748 | if (ext != NULL) |
f3bad469 | 26749 | len = ext - str; |
7ed4c4c5 | 26750 | else |
f3bad469 | 26751 | len = strlen (str); |
7ed4c4c5 | 26752 | |
f3bad469 | 26753 | if (len == 0) |
7ed4c4c5 | 26754 | { |
c19d1205 | 26755 | as_bad (_("missing architecture name `%s'"), str); |
c921be7d | 26756 | return FALSE; |
7ed4c4c5 NC |
26757 | } |
26758 | ||
c19d1205 | 26759 | for (opt = arm_archs; opt->name != NULL; opt++) |
f3bad469 | 26760 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 26761 | { |
e74cfd16 | 26762 | march_cpu_opt = &opt->value; |
4d354d8b TP |
26763 | if (march_ext_opt == NULL) |
26764 | march_ext_opt = XNEW (arm_feature_set); | |
26765 | *march_ext_opt = arm_arch_none; | |
e74cfd16 | 26766 | march_fpu_opt = &opt->default_fpu; |
5f4273c7 | 26767 | strcpy (selected_cpu_name, opt->name); |
7ed4c4c5 | 26768 | |
c19d1205 | 26769 | if (ext != NULL) |
4d354d8b | 26770 | return arm_parse_extension (ext, march_cpu_opt, march_ext_opt); |
7ed4c4c5 | 26771 | |
c921be7d | 26772 | return TRUE; |
c19d1205 ZW |
26773 | } |
26774 | ||
26775 | as_bad (_("unknown architecture `%s'\n"), str); | |
c921be7d | 26776 | return FALSE; |
7ed4c4c5 | 26777 | } |
eb043451 | 26778 | |
c921be7d | 26779 | static bfd_boolean |
17b9d67d | 26780 | arm_parse_fpu (const char * str) |
c19d1205 | 26781 | { |
69133863 | 26782 | const struct arm_option_fpu_value_table * opt; |
b99bd4ef | 26783 | |
c19d1205 ZW |
26784 | for (opt = arm_fpus; opt->name != NULL; opt++) |
26785 | if (streq (opt->name, str)) | |
26786 | { | |
e74cfd16 | 26787 | mfpu_opt = &opt->value; |
c921be7d | 26788 | return TRUE; |
c19d1205 | 26789 | } |
b99bd4ef | 26790 | |
c19d1205 | 26791 | as_bad (_("unknown floating point format `%s'\n"), str); |
c921be7d | 26792 | return FALSE; |
c19d1205 ZW |
26793 | } |
26794 | ||
c921be7d | 26795 | static bfd_boolean |
17b9d67d | 26796 | arm_parse_float_abi (const char * str) |
b99bd4ef | 26797 | { |
e74cfd16 | 26798 | const struct arm_option_value_table * opt; |
b99bd4ef | 26799 | |
c19d1205 ZW |
26800 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
26801 | if (streq (opt->name, str)) | |
26802 | { | |
26803 | mfloat_abi_opt = opt->value; | |
c921be7d | 26804 | return TRUE; |
c19d1205 | 26805 | } |
cc8a6dd0 | 26806 | |
c19d1205 | 26807 | as_bad (_("unknown floating point abi `%s'\n"), str); |
c921be7d | 26808 | return FALSE; |
c19d1205 | 26809 | } |
b99bd4ef | 26810 | |
c19d1205 | 26811 | #ifdef OBJ_ELF |
c921be7d | 26812 | static bfd_boolean |
17b9d67d | 26813 | arm_parse_eabi (const char * str) |
c19d1205 | 26814 | { |
e74cfd16 | 26815 | const struct arm_option_value_table *opt; |
cc8a6dd0 | 26816 | |
c19d1205 ZW |
26817 | for (opt = arm_eabis; opt->name != NULL; opt++) |
26818 | if (streq (opt->name, str)) | |
26819 | { | |
26820 | meabi_flags = opt->value; | |
c921be7d | 26821 | return TRUE; |
c19d1205 ZW |
26822 | } |
26823 | as_bad (_("unknown EABI `%s'\n"), str); | |
c921be7d | 26824 | return FALSE; |
c19d1205 ZW |
26825 | } |
26826 | #endif | |
cc8a6dd0 | 26827 | |
c921be7d | 26828 | static bfd_boolean |
17b9d67d | 26829 | arm_parse_it_mode (const char * str) |
e07e6e58 | 26830 | { |
c921be7d | 26831 | bfd_boolean ret = TRUE; |
e07e6e58 NC |
26832 | |
26833 | if (streq ("arm", str)) | |
26834 | implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
26835 | else if (streq ("thumb", str)) | |
26836 | implicit_it_mode = IMPLICIT_IT_MODE_THUMB; | |
26837 | else if (streq ("always", str)) | |
26838 | implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS; | |
26839 | else if (streq ("never", str)) | |
26840 | implicit_it_mode = IMPLICIT_IT_MODE_NEVER; | |
26841 | else | |
26842 | { | |
26843 | as_bad (_("unknown implicit IT mode `%s', should be "\ | |
477330fc | 26844 | "arm, thumb, always, or never."), str); |
c921be7d | 26845 | ret = FALSE; |
e07e6e58 NC |
26846 | } |
26847 | ||
26848 | return ret; | |
26849 | } | |
26850 | ||
2e6976a8 | 26851 | static bfd_boolean |
17b9d67d | 26852 | arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED) |
2e6976a8 DG |
26853 | { |
26854 | codecomposer_syntax = TRUE; | |
26855 | arm_comment_chars[0] = ';'; | |
26856 | arm_line_separator_chars[0] = 0; | |
26857 | return TRUE; | |
26858 | } | |
26859 | ||
c19d1205 ZW |
26860 | struct arm_long_option_table arm_long_opts[] = |
26861 | { | |
26862 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
26863 | arm_parse_cpu, NULL}, | |
26864 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
26865 | arm_parse_arch, NULL}, | |
26866 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
26867 | arm_parse_fpu, NULL}, | |
26868 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
26869 | arm_parse_float_abi, NULL}, | |
26870 | #ifdef OBJ_ELF | |
7fac0536 | 26871 | {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"), |
c19d1205 ZW |
26872 | arm_parse_eabi, NULL}, |
26873 | #endif | |
e07e6e58 NC |
26874 | {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"), |
26875 | arm_parse_it_mode, NULL}, | |
2e6976a8 DG |
26876 | {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"), |
26877 | arm_ccs_mode, NULL}, | |
c19d1205 ZW |
26878 | {NULL, NULL, 0, NULL} |
26879 | }; | |
cc8a6dd0 | 26880 | |
c19d1205 | 26881 | int |
17b9d67d | 26882 | md_parse_option (int c, const char * arg) |
c19d1205 ZW |
26883 | { |
26884 | struct arm_option_table *opt; | |
e74cfd16 | 26885 | const struct arm_legacy_option_table *fopt; |
c19d1205 | 26886 | struct arm_long_option_table *lopt; |
b99bd4ef | 26887 | |
c19d1205 | 26888 | switch (c) |
b99bd4ef | 26889 | { |
c19d1205 ZW |
26890 | #ifdef OPTION_EB |
26891 | case OPTION_EB: | |
26892 | target_big_endian = 1; | |
26893 | break; | |
26894 | #endif | |
cc8a6dd0 | 26895 | |
c19d1205 ZW |
26896 | #ifdef OPTION_EL |
26897 | case OPTION_EL: | |
26898 | target_big_endian = 0; | |
26899 | break; | |
26900 | #endif | |
b99bd4ef | 26901 | |
845b51d6 PB |
26902 | case OPTION_FIX_V4BX: |
26903 | fix_v4bx = TRUE; | |
26904 | break; | |
26905 | ||
18a20338 CL |
26906 | #ifdef OBJ_ELF |
26907 | case OPTION_FDPIC: | |
26908 | arm_fdpic = TRUE; | |
26909 | break; | |
26910 | #endif /* OBJ_ELF */ | |
26911 | ||
c19d1205 ZW |
26912 | case 'a': |
26913 | /* Listing option. Just ignore these, we don't support additional | |
26914 | ones. */ | |
26915 | return 0; | |
b99bd4ef | 26916 | |
c19d1205 ZW |
26917 | default: |
26918 | for (opt = arm_opts; opt->option != NULL; opt++) | |
26919 | { | |
26920 | if (c == opt->option[0] | |
26921 | && ((arg == NULL && opt->option[1] == 0) | |
26922 | || streq (arg, opt->option + 1))) | |
26923 | { | |
c19d1205 | 26924 | /* If the option is deprecated, tell the user. */ |
278df34e | 26925 | if (warn_on_deprecated && opt->deprecated != NULL) |
c19d1205 ZW |
26926 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
26927 | arg ? arg : "", _(opt->deprecated)); | |
b99bd4ef | 26928 | |
c19d1205 ZW |
26929 | if (opt->var != NULL) |
26930 | *opt->var = opt->value; | |
cc8a6dd0 | 26931 | |
c19d1205 ZW |
26932 | return 1; |
26933 | } | |
26934 | } | |
b99bd4ef | 26935 | |
e74cfd16 PB |
26936 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
26937 | { | |
26938 | if (c == fopt->option[0] | |
26939 | && ((arg == NULL && fopt->option[1] == 0) | |
26940 | || streq (arg, fopt->option + 1))) | |
26941 | { | |
e74cfd16 | 26942 | /* If the option is deprecated, tell the user. */ |
278df34e | 26943 | if (warn_on_deprecated && fopt->deprecated != NULL) |
e74cfd16 PB |
26944 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
26945 | arg ? arg : "", _(fopt->deprecated)); | |
e74cfd16 PB |
26946 | |
26947 | if (fopt->var != NULL) | |
26948 | *fopt->var = &fopt->value; | |
26949 | ||
26950 | return 1; | |
26951 | } | |
26952 | } | |
26953 | ||
c19d1205 ZW |
26954 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
26955 | { | |
26956 | /* These options are expected to have an argument. */ | |
26957 | if (c == lopt->option[0] | |
26958 | && arg != NULL | |
26959 | && strncmp (arg, lopt->option + 1, | |
26960 | strlen (lopt->option + 1)) == 0) | |
26961 | { | |
c19d1205 | 26962 | /* If the option is deprecated, tell the user. */ |
278df34e | 26963 | if (warn_on_deprecated && lopt->deprecated != NULL) |
c19d1205 ZW |
26964 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, |
26965 | _(lopt->deprecated)); | |
b99bd4ef | 26966 | |
c19d1205 ZW |
26967 | /* Call the sup-option parser. */ |
26968 | return lopt->func (arg + strlen (lopt->option) - 1); | |
26969 | } | |
26970 | } | |
a737bd4d | 26971 | |
c19d1205 ZW |
26972 | return 0; |
26973 | } | |
a394c00f | 26974 | |
c19d1205 ZW |
26975 | return 1; |
26976 | } | |
a394c00f | 26977 | |
c19d1205 ZW |
26978 | void |
26979 | md_show_usage (FILE * fp) | |
a394c00f | 26980 | { |
c19d1205 ZW |
26981 | struct arm_option_table *opt; |
26982 | struct arm_long_option_table *lopt; | |
a394c00f | 26983 | |
c19d1205 | 26984 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 26985 | |
c19d1205 ZW |
26986 | for (opt = arm_opts; opt->option != NULL; opt++) |
26987 | if (opt->help != NULL) | |
26988 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 26989 | |
c19d1205 ZW |
26990 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
26991 | if (lopt->help != NULL) | |
26992 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 26993 | |
c19d1205 ZW |
26994 | #ifdef OPTION_EB |
26995 | fprintf (fp, _("\ | |
26996 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
26997 | #endif |
26998 | ||
c19d1205 ZW |
26999 | #ifdef OPTION_EL |
27000 | fprintf (fp, _("\ | |
27001 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 27002 | #endif |
845b51d6 PB |
27003 | |
27004 | fprintf (fp, _("\ | |
27005 | --fix-v4bx Allow BX in ARMv4 code\n")); | |
18a20338 CL |
27006 | |
27007 | #ifdef OBJ_ELF | |
27008 | fprintf (fp, _("\ | |
27009 | --fdpic generate an FDPIC object file\n")); | |
27010 | #endif /* OBJ_ELF */ | |
c19d1205 | 27011 | } |
ee065d83 | 27012 | |
ee065d83 | 27013 | #ifdef OBJ_ELF |
0198d5e6 | 27014 | |
62b3e311 PB |
27015 | typedef struct |
27016 | { | |
27017 | int val; | |
27018 | arm_feature_set flags; | |
27019 | } cpu_arch_ver_table; | |
27020 | ||
2c6b98ea TP |
27021 | /* Mapping from CPU features to EABI CPU arch values. Table must be sorted |
27022 | chronologically for architectures, with an exception for ARMv6-M and | |
27023 | ARMv6S-M due to legacy reasons. No new architecture should have a | |
27024 | special case. This allows for build attribute selection results to be | |
27025 | stable when new architectures are added. */ | |
62b3e311 PB |
27026 | static const cpu_arch_ver_table cpu_arch_ver[] = |
27027 | { | |
c0c468d5 TP |
27028 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1}, |
27029 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2}, | |
27030 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S}, | |
27031 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3}, | |
27032 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M}, | |
27033 | {TAG_CPU_ARCH_V4, ARM_ARCH_V4xM}, | |
27034 | {TAG_CPU_ARCH_V4, ARM_ARCH_V4}, | |
27035 | {TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM}, | |
27036 | {TAG_CPU_ARCH_V4T, ARM_ARCH_V4T}, | |
27037 | {TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM}, | |
27038 | {TAG_CPU_ARCH_V5T, ARM_ARCH_V5}, | |
27039 | {TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM}, | |
27040 | {TAG_CPU_ARCH_V5T, ARM_ARCH_V5T}, | |
27041 | {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP}, | |
27042 | {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE}, | |
27043 | {TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ}, | |
27044 | {TAG_CPU_ARCH_V6, ARM_ARCH_V6}, | |
27045 | {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z}, | |
27046 | {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ}, | |
27047 | {TAG_CPU_ARCH_V6K, ARM_ARCH_V6K}, | |
27048 | {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2}, | |
27049 | {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2}, | |
27050 | {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2}, | |
27051 | {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2}, | |
2c6b98ea TP |
27052 | |
27053 | /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as | |
27054 | always selected build attributes to match those of ARMv6-M | |
27055 | (resp. ARMv6S-M). However, due to these architectures being a strict | |
27056 | subset of ARMv7-M in terms of instructions available, ARMv7-M attributes | |
27057 | would be selected when fully respecting chronology of architectures. | |
27058 | It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and | |
27059 | move them before ARMv7 architectures. */ | |
c0c468d5 TP |
27060 | {TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M}, |
27061 | {TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM}, | |
27062 | ||
27063 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7}, | |
27064 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7A}, | |
27065 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7R}, | |
27066 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7M}, | |
27067 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7VE}, | |
27068 | {TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM}, | |
27069 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8A}, | |
27070 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A}, | |
27071 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A}, | |
27072 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A}, | |
27073 | {TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE}, | |
27074 | {TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN}, | |
27075 | {TAG_CPU_ARCH_V8R, ARM_ARCH_V8R}, | |
27076 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A}, | |
23f233a5 | 27077 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A}, |
c0c468d5 | 27078 | {-1, ARM_ARCH_NONE} |
62b3e311 PB |
27079 | }; |
27080 | ||
ee3c0378 | 27081 | /* Set an attribute if it has not already been set by the user. */ |
0198d5e6 | 27082 | |
ee3c0378 AS |
27083 | static void |
27084 | aeabi_set_attribute_int (int tag, int value) | |
27085 | { | |
27086 | if (tag < 1 | |
27087 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
27088 | || !attributes_set_explicitly[tag]) | |
27089 | bfd_elf_add_proc_attr_int (stdoutput, tag, value); | |
27090 | } | |
27091 | ||
27092 | static void | |
27093 | aeabi_set_attribute_string (int tag, const char *value) | |
27094 | { | |
27095 | if (tag < 1 | |
27096 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
27097 | || !attributes_set_explicitly[tag]) | |
27098 | bfd_elf_add_proc_attr_string (stdoutput, tag, value); | |
27099 | } | |
27100 | ||
2c6b98ea TP |
27101 | /* Return whether features in the *NEEDED feature set are available via |
27102 | extensions for the architecture whose feature set is *ARCH_FSET. */ | |
0198d5e6 | 27103 | |
2c6b98ea TP |
27104 | static bfd_boolean |
27105 | have_ext_for_needed_feat_p (const arm_feature_set *arch_fset, | |
27106 | const arm_feature_set *needed) | |
27107 | { | |
27108 | int i, nb_allowed_archs; | |
27109 | arm_feature_set ext_fset; | |
27110 | const struct arm_option_extension_value_table *opt; | |
27111 | ||
27112 | ext_fset = arm_arch_none; | |
27113 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
27114 | { | |
27115 | /* Extension does not provide any feature we need. */ | |
27116 | if (!ARM_CPU_HAS_FEATURE (*needed, opt->merge_value)) | |
27117 | continue; | |
27118 | ||
27119 | nb_allowed_archs = | |
27120 | sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]); | |
27121 | for (i = 0; i < nb_allowed_archs; i++) | |
27122 | { | |
27123 | /* Empty entry. */ | |
27124 | if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_arch_any)) | |
27125 | break; | |
27126 | ||
27127 | /* Extension is available, add it. */ | |
27128 | if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *arch_fset)) | |
27129 | ARM_MERGE_FEATURE_SETS (ext_fset, ext_fset, opt->merge_value); | |
27130 | } | |
27131 | } | |
27132 | ||
27133 | /* Can we enable all features in *needed? */ | |
27134 | return ARM_FSET_CPU_SUBSET (*needed, ext_fset); | |
27135 | } | |
27136 | ||
27137 | /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for | |
27138 | a given architecture feature set *ARCH_EXT_FSET including extension feature | |
27139 | set *EXT_FSET. Selection logic used depend on EXACT_MATCH: | |
27140 | - if true, check for an exact match of the architecture modulo extensions; | |
27141 | - otherwise, select build attribute value of the first superset | |
27142 | architecture released so that results remains stable when new architectures | |
27143 | are added. | |
27144 | For -march/-mcpu=all the build attribute value of the most featureful | |
27145 | architecture is returned. Tag_CPU_arch_profile result is returned in | |
27146 | PROFILE. */ | |
0198d5e6 | 27147 | |
2c6b98ea TP |
27148 | static int |
27149 | get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset, | |
27150 | const arm_feature_set *ext_fset, | |
27151 | char *profile, int exact_match) | |
27152 | { | |
27153 | arm_feature_set arch_fset; | |
27154 | const cpu_arch_ver_table *p_ver, *p_ver_ret = NULL; | |
27155 | ||
27156 | /* Select most featureful architecture with all its extensions if building | |
27157 | for -march=all as the feature sets used to set build attributes. */ | |
27158 | if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any)) | |
27159 | { | |
27160 | /* Force revisiting of decision for each new architecture. */ | |
27161 | gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8M_MAIN); | |
27162 | *profile = 'A'; | |
27163 | return TAG_CPU_ARCH_V8; | |
27164 | } | |
27165 | ||
27166 | ARM_CLEAR_FEATURE (arch_fset, *arch_ext_fset, *ext_fset); | |
27167 | ||
27168 | for (p_ver = cpu_arch_ver; p_ver->val != -1; p_ver++) | |
27169 | { | |
27170 | arm_feature_set known_arch_fset; | |
27171 | ||
27172 | ARM_CLEAR_FEATURE (known_arch_fset, p_ver->flags, fpu_any); | |
27173 | if (exact_match) | |
27174 | { | |
27175 | /* Base architecture match user-specified architecture and | |
27176 | extensions, eg. ARMv6S-M matching -march=armv6-m+os. */ | |
27177 | if (ARM_FEATURE_EQUAL (*arch_ext_fset, known_arch_fset)) | |
27178 | { | |
27179 | p_ver_ret = p_ver; | |
27180 | goto found; | |
27181 | } | |
27182 | /* Base architecture match user-specified architecture only | |
27183 | (eg. ARMv6-M in the same case as above). Record it in case we | |
27184 | find a match with above condition. */ | |
27185 | else if (p_ver_ret == NULL | |
27186 | && ARM_FEATURE_EQUAL (arch_fset, known_arch_fset)) | |
27187 | p_ver_ret = p_ver; | |
27188 | } | |
27189 | else | |
27190 | { | |
27191 | ||
27192 | /* Architecture has all features wanted. */ | |
27193 | if (ARM_FSET_CPU_SUBSET (arch_fset, known_arch_fset)) | |
27194 | { | |
27195 | arm_feature_set added_fset; | |
27196 | ||
27197 | /* Compute features added by this architecture over the one | |
27198 | recorded in p_ver_ret. */ | |
27199 | if (p_ver_ret != NULL) | |
27200 | ARM_CLEAR_FEATURE (added_fset, known_arch_fset, | |
27201 | p_ver_ret->flags); | |
27202 | /* First architecture that match incl. with extensions, or the | |
27203 | only difference in features over the recorded match is | |
27204 | features that were optional and are now mandatory. */ | |
27205 | if (p_ver_ret == NULL | |
27206 | || ARM_FSET_CPU_SUBSET (added_fset, arch_fset)) | |
27207 | { | |
27208 | p_ver_ret = p_ver; | |
27209 | goto found; | |
27210 | } | |
27211 | } | |
27212 | else if (p_ver_ret == NULL) | |
27213 | { | |
27214 | arm_feature_set needed_ext_fset; | |
27215 | ||
27216 | ARM_CLEAR_FEATURE (needed_ext_fset, arch_fset, known_arch_fset); | |
27217 | ||
27218 | /* Architecture has all features needed when using some | |
27219 | extensions. Record it and continue searching in case there | |
27220 | exist an architecture providing all needed features without | |
27221 | the need for extensions (eg. ARMv6S-M Vs ARMv6-M with | |
27222 | OS extension). */ | |
27223 | if (have_ext_for_needed_feat_p (&known_arch_fset, | |
27224 | &needed_ext_fset)) | |
27225 | p_ver_ret = p_ver; | |
27226 | } | |
27227 | } | |
27228 | } | |
27229 | ||
27230 | if (p_ver_ret == NULL) | |
27231 | return -1; | |
27232 | ||
27233 | found: | |
27234 | /* Tag_CPU_arch_profile. */ | |
27235 | if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7a) | |
27236 | || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8) | |
27237 | || (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_atomics) | |
27238 | && !ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8m_m_only))) | |
27239 | *profile = 'A'; | |
27240 | else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7r)) | |
27241 | *profile = 'R'; | |
27242 | else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_m)) | |
27243 | *profile = 'M'; | |
27244 | else | |
27245 | *profile = '\0'; | |
27246 | return p_ver_ret->val; | |
27247 | } | |
27248 | ||
ee065d83 | 27249 | /* Set the public EABI object attributes. */ |
0198d5e6 | 27250 | |
c168ce07 | 27251 | static void |
ee065d83 PB |
27252 | aeabi_set_public_attributes (void) |
27253 | { | |
b90d5ba0 | 27254 | char profile = '\0'; |
2c6b98ea | 27255 | int arch = -1; |
90ec0d68 | 27256 | int virt_sec = 0; |
bca38921 | 27257 | int fp16_optional = 0; |
2c6b98ea TP |
27258 | int skip_exact_match = 0; |
27259 | arm_feature_set flags, flags_arch, flags_ext; | |
ee065d83 | 27260 | |
54bab281 TP |
27261 | /* Autodetection mode, choose the architecture based the instructions |
27262 | actually used. */ | |
27263 | if (no_cpu_selected ()) | |
27264 | { | |
27265 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); | |
ddd7f988 | 27266 | |
54bab281 TP |
27267 | if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)) |
27268 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1); | |
ddd7f988 | 27269 | |
54bab281 TP |
27270 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any)) |
27271 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t); | |
ddd7f988 | 27272 | |
54bab281 | 27273 | /* Code run during relaxation relies on selected_cpu being set. */ |
4d354d8b TP |
27274 | ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any); |
27275 | flags_ext = arm_arch_none; | |
27276 | ARM_CLEAR_FEATURE (selected_arch, flags_arch, flags_ext); | |
27277 | selected_ext = flags_ext; | |
54bab281 TP |
27278 | selected_cpu = flags; |
27279 | } | |
27280 | /* Otherwise, choose the architecture based on the capabilities of the | |
27281 | requested cpu. */ | |
27282 | else | |
4d354d8b TP |
27283 | { |
27284 | ARM_MERGE_FEATURE_SETS (flags_arch, selected_arch, selected_ext); | |
27285 | ARM_CLEAR_FEATURE (flags_arch, flags_arch, fpu_any); | |
27286 | flags_ext = selected_ext; | |
27287 | flags = selected_cpu; | |
27288 | } | |
27289 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_fpu); | |
7f78eb34 | 27290 | |
ddd7f988 | 27291 | /* Allow the user to override the reported architecture. */ |
4d354d8b | 27292 | if (!ARM_FEATURE_ZERO (selected_object_arch)) |
7a1d4c38 | 27293 | { |
4d354d8b | 27294 | ARM_CLEAR_FEATURE (flags_arch, selected_object_arch, fpu_any); |
2c6b98ea | 27295 | flags_ext = arm_arch_none; |
7a1d4c38 | 27296 | } |
2c6b98ea | 27297 | else |
4d354d8b | 27298 | skip_exact_match = ARM_FEATURE_EQUAL (selected_cpu, arm_arch_any); |
2c6b98ea TP |
27299 | |
27300 | /* When this function is run again after relaxation has happened there is no | |
27301 | way to determine whether an architecture or CPU was specified by the user: | |
27302 | - selected_cpu is set above for relaxation to work; | |
27303 | - march_cpu_opt is not set if only -mcpu or .cpu is used; | |
27304 | - mcpu_cpu_opt is set to arm_arch_any for autodetection. | |
27305 | Therefore, if not in -march=all case we first try an exact match and fall | |
27306 | back to autodetection. */ | |
27307 | if (!skip_exact_match) | |
27308 | arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 1); | |
27309 | if (arch == -1) | |
27310 | arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 0); | |
27311 | if (arch == -1) | |
27312 | as_bad (_("no architecture contains all the instructions used\n")); | |
9e3c6df6 | 27313 | |
ee065d83 PB |
27314 | /* Tag_CPU_name. */ |
27315 | if (selected_cpu_name[0]) | |
27316 | { | |
91d6fa6a | 27317 | char *q; |
ee065d83 | 27318 | |
91d6fa6a NC |
27319 | q = selected_cpu_name; |
27320 | if (strncmp (q, "armv", 4) == 0) | |
ee065d83 PB |
27321 | { |
27322 | int i; | |
5f4273c7 | 27323 | |
91d6fa6a NC |
27324 | q += 4; |
27325 | for (i = 0; q[i]; i++) | |
27326 | q[i] = TOUPPER (q[i]); | |
ee065d83 | 27327 | } |
91d6fa6a | 27328 | aeabi_set_attribute_string (Tag_CPU_name, q); |
ee065d83 | 27329 | } |
62f3b8c8 | 27330 | |
ee065d83 | 27331 | /* Tag_CPU_arch. */ |
ee3c0378 | 27332 | aeabi_set_attribute_int (Tag_CPU_arch, arch); |
62f3b8c8 | 27333 | |
62b3e311 | 27334 | /* Tag_CPU_arch_profile. */ |
69239280 MGD |
27335 | if (profile != '\0') |
27336 | aeabi_set_attribute_int (Tag_CPU_arch_profile, profile); | |
62f3b8c8 | 27337 | |
15afaa63 | 27338 | /* Tag_DSP_extension. */ |
4d354d8b | 27339 | if (ARM_CPU_HAS_FEATURE (selected_ext, arm_ext_dsp)) |
6c290d53 | 27340 | aeabi_set_attribute_int (Tag_DSP_extension, 1); |
15afaa63 | 27341 | |
2c6b98ea | 27342 | ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any); |
ee065d83 | 27343 | /* Tag_ARM_ISA_use. */ |
ee3c0378 | 27344 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) |
2c6b98ea | 27345 | || ARM_FEATURE_ZERO (flags_arch)) |
ee3c0378 | 27346 | aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); |
62f3b8c8 | 27347 | |
ee065d83 | 27348 | /* Tag_THUMB_ISA_use. */ |
ee3c0378 | 27349 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) |
2c6b98ea | 27350 | || ARM_FEATURE_ZERO (flags_arch)) |
4ed7ed8d TP |
27351 | { |
27352 | int thumb_isa_use; | |
27353 | ||
27354 | if (!ARM_CPU_HAS_FEATURE (flags, arm_ext_v8) | |
16a1fa25 | 27355 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only)) |
4ed7ed8d TP |
27356 | thumb_isa_use = 3; |
27357 | else if (ARM_CPU_HAS_FEATURE (flags, arm_arch_t2)) | |
27358 | thumb_isa_use = 2; | |
27359 | else | |
27360 | thumb_isa_use = 1; | |
27361 | aeabi_set_attribute_int (Tag_THUMB_ISA_use, thumb_isa_use); | |
27362 | } | |
62f3b8c8 | 27363 | |
ee065d83 | 27364 | /* Tag_VFP_arch. */ |
a715796b TG |
27365 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd)) |
27366 | aeabi_set_attribute_int (Tag_VFP_arch, | |
27367 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
27368 | ? 7 : 8); | |
bca38921 | 27369 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma)) |
62f3b8c8 PB |
27370 | aeabi_set_attribute_int (Tag_VFP_arch, |
27371 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
27372 | ? 5 : 6); | |
27373 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) | |
bca38921 MGD |
27374 | { |
27375 | fp16_optional = 1; | |
27376 | aeabi_set_attribute_int (Tag_VFP_arch, 3); | |
27377 | } | |
ada65aa3 | 27378 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd)) |
bca38921 MGD |
27379 | { |
27380 | aeabi_set_attribute_int (Tag_VFP_arch, 4); | |
27381 | fp16_optional = 1; | |
27382 | } | |
ee3c0378 AS |
27383 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) |
27384 | aeabi_set_attribute_int (Tag_VFP_arch, 2); | |
27385 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) | |
477330fc | 27386 | || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)) |
ee3c0378 | 27387 | aeabi_set_attribute_int (Tag_VFP_arch, 1); |
62f3b8c8 | 27388 | |
4547cb56 NC |
27389 | /* Tag_ABI_HardFP_use. */ |
27390 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd) | |
27391 | && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)) | |
27392 | aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1); | |
27393 | ||
ee065d83 | 27394 | /* Tag_WMMX_arch. */ |
ee3c0378 AS |
27395 | if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2)) |
27396 | aeabi_set_attribute_int (Tag_WMMX_arch, 2); | |
27397 | else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt)) | |
27398 | aeabi_set_attribute_int (Tag_WMMX_arch, 1); | |
62f3b8c8 | 27399 | |
ee3c0378 | 27400 | /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ |
9411fd44 MW |
27401 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v8_1)) |
27402 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 4); | |
27403 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8)) | |
bca38921 MGD |
27404 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3); |
27405 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) | |
27406 | { | |
27407 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)) | |
27408 | { | |
27409 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2); | |
27410 | } | |
27411 | else | |
27412 | { | |
27413 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1); | |
27414 | fp16_optional = 1; | |
27415 | } | |
27416 | } | |
fa94de6b | 27417 | |
ee3c0378 | 27418 | /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ |
bca38921 | 27419 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional) |
ee3c0378 | 27420 | aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); |
4547cb56 | 27421 | |
69239280 MGD |
27422 | /* Tag_DIV_use. |
27423 | ||
27424 | We set Tag_DIV_use to two when integer divide instructions have been used | |
27425 | in ARM state, or when Thumb integer divide instructions have been used, | |
27426 | but we have no architecture profile set, nor have we any ARM instructions. | |
27427 | ||
4ed7ed8d TP |
27428 | For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied |
27429 | by the base architecture. | |
bca38921 | 27430 | |
69239280 | 27431 | For new architectures we will have to check these tests. */ |
ced40572 | 27432 | gas_assert (arch <= TAG_CPU_ARCH_V8M_MAIN); |
4ed7ed8d TP |
27433 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8) |
27434 | || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m)) | |
bca38921 MGD |
27435 | aeabi_set_attribute_int (Tag_DIV_use, 0); |
27436 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv) | |
27437 | || (profile == '\0' | |
27438 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_div) | |
27439 | && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))) | |
eea54501 | 27440 | aeabi_set_attribute_int (Tag_DIV_use, 2); |
60e5ef9f MGD |
27441 | |
27442 | /* Tag_MP_extension_use. */ | |
27443 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp)) | |
27444 | aeabi_set_attribute_int (Tag_MPextension_use, 1); | |
f4c65163 MGD |
27445 | |
27446 | /* Tag Virtualization_use. */ | |
27447 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec)) | |
90ec0d68 MGD |
27448 | virt_sec |= 1; |
27449 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt)) | |
27450 | virt_sec |= 2; | |
27451 | if (virt_sec != 0) | |
27452 | aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec); | |
ee065d83 PB |
27453 | } |
27454 | ||
c168ce07 TP |
27455 | /* Post relaxation hook. Recompute ARM attributes now that relaxation is |
27456 | finished and free extension feature bits which will not be used anymore. */ | |
0198d5e6 | 27457 | |
c168ce07 TP |
27458 | void |
27459 | arm_md_post_relax (void) | |
27460 | { | |
27461 | aeabi_set_public_attributes (); | |
4d354d8b TP |
27462 | XDELETE (mcpu_ext_opt); |
27463 | mcpu_ext_opt = NULL; | |
27464 | XDELETE (march_ext_opt); | |
27465 | march_ext_opt = NULL; | |
c168ce07 TP |
27466 | } |
27467 | ||
104d59d1 | 27468 | /* Add the default contents for the .ARM.attributes section. */ |
0198d5e6 | 27469 | |
ee065d83 PB |
27470 | void |
27471 | arm_md_end (void) | |
27472 | { | |
ee065d83 PB |
27473 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
27474 | return; | |
27475 | ||
27476 | aeabi_set_public_attributes (); | |
ee065d83 | 27477 | } |
8463be01 | 27478 | #endif /* OBJ_ELF */ |
ee065d83 | 27479 | |
ee065d83 PB |
27480 | /* Parse a .cpu directive. */ |
27481 | ||
27482 | static void | |
27483 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) | |
27484 | { | |
e74cfd16 | 27485 | const struct arm_cpu_option_table *opt; |
ee065d83 PB |
27486 | char *name; |
27487 | char saved_char; | |
27488 | ||
27489 | name = input_line_pointer; | |
5f4273c7 | 27490 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
27491 | input_line_pointer++; |
27492 | saved_char = *input_line_pointer; | |
27493 | *input_line_pointer = 0; | |
27494 | ||
27495 | /* Skip the first "all" entry. */ | |
27496 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) | |
27497 | if (streq (opt->name, name)) | |
27498 | { | |
4d354d8b TP |
27499 | selected_arch = opt->value; |
27500 | selected_ext = opt->ext; | |
27501 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext); | |
ee065d83 | 27502 | if (opt->canonical_name) |
5f4273c7 | 27503 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
27504 | else |
27505 | { | |
27506 | int i; | |
27507 | for (i = 0; opt->name[i]; i++) | |
27508 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
f3bad469 | 27509 | |
ee065d83 PB |
27510 | selected_cpu_name[i] = 0; |
27511 | } | |
4d354d8b TP |
27512 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); |
27513 | ||
ee065d83 PB |
27514 | *input_line_pointer = saved_char; |
27515 | demand_empty_rest_of_line (); | |
27516 | return; | |
27517 | } | |
27518 | as_bad (_("unknown cpu `%s'"), name); | |
27519 | *input_line_pointer = saved_char; | |
27520 | ignore_rest_of_line (); | |
27521 | } | |
27522 | ||
ee065d83 PB |
27523 | /* Parse a .arch directive. */ |
27524 | ||
27525 | static void | |
27526 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) | |
27527 | { | |
e74cfd16 | 27528 | const struct arm_arch_option_table *opt; |
ee065d83 PB |
27529 | char saved_char; |
27530 | char *name; | |
27531 | ||
27532 | name = input_line_pointer; | |
5f4273c7 | 27533 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
27534 | input_line_pointer++; |
27535 | saved_char = *input_line_pointer; | |
27536 | *input_line_pointer = 0; | |
27537 | ||
27538 | /* Skip the first "all" entry. */ | |
27539 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
27540 | if (streq (opt->name, name)) | |
27541 | { | |
4d354d8b TP |
27542 | selected_arch = opt->value; |
27543 | selected_ext = arm_arch_none; | |
27544 | selected_cpu = selected_arch; | |
5f4273c7 | 27545 | strcpy (selected_cpu_name, opt->name); |
4d354d8b | 27546 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); |
ee065d83 PB |
27547 | *input_line_pointer = saved_char; |
27548 | demand_empty_rest_of_line (); | |
27549 | return; | |
27550 | } | |
27551 | ||
27552 | as_bad (_("unknown architecture `%s'\n"), name); | |
27553 | *input_line_pointer = saved_char; | |
27554 | ignore_rest_of_line (); | |
27555 | } | |
27556 | ||
7a1d4c38 PB |
27557 | /* Parse a .object_arch directive. */ |
27558 | ||
27559 | static void | |
27560 | s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) | |
27561 | { | |
27562 | const struct arm_arch_option_table *opt; | |
27563 | char saved_char; | |
27564 | char *name; | |
27565 | ||
27566 | name = input_line_pointer; | |
5f4273c7 | 27567 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
7a1d4c38 PB |
27568 | input_line_pointer++; |
27569 | saved_char = *input_line_pointer; | |
27570 | *input_line_pointer = 0; | |
27571 | ||
27572 | /* Skip the first "all" entry. */ | |
27573 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
27574 | if (streq (opt->name, name)) | |
27575 | { | |
4d354d8b | 27576 | selected_object_arch = opt->value; |
7a1d4c38 PB |
27577 | *input_line_pointer = saved_char; |
27578 | demand_empty_rest_of_line (); | |
27579 | return; | |
27580 | } | |
27581 | ||
27582 | as_bad (_("unknown architecture `%s'\n"), name); | |
27583 | *input_line_pointer = saved_char; | |
27584 | ignore_rest_of_line (); | |
27585 | } | |
27586 | ||
69133863 MGD |
27587 | /* Parse a .arch_extension directive. */ |
27588 | ||
27589 | static void | |
27590 | s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED) | |
27591 | { | |
27592 | const struct arm_option_extension_value_table *opt; | |
27593 | char saved_char; | |
27594 | char *name; | |
27595 | int adding_value = 1; | |
27596 | ||
27597 | name = input_line_pointer; | |
27598 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) | |
27599 | input_line_pointer++; | |
27600 | saved_char = *input_line_pointer; | |
27601 | *input_line_pointer = 0; | |
27602 | ||
27603 | if (strlen (name) >= 2 | |
27604 | && strncmp (name, "no", 2) == 0) | |
27605 | { | |
27606 | adding_value = 0; | |
27607 | name += 2; | |
27608 | } | |
27609 | ||
27610 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
27611 | if (streq (opt->name, name)) | |
27612 | { | |
d942732e TP |
27613 | int i, nb_allowed_archs = |
27614 | sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[i]); | |
27615 | for (i = 0; i < nb_allowed_archs; i++) | |
27616 | { | |
27617 | /* Empty entry. */ | |
4d354d8b | 27618 | if (ARM_CPU_IS_ANY (opt->allowed_archs[i])) |
d942732e | 27619 | continue; |
4d354d8b | 27620 | if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], selected_arch)) |
d942732e TP |
27621 | break; |
27622 | } | |
27623 | ||
27624 | if (i == nb_allowed_archs) | |
69133863 MGD |
27625 | { |
27626 | as_bad (_("architectural extension `%s' is not allowed for the " | |
27627 | "current base architecture"), name); | |
27628 | break; | |
27629 | } | |
27630 | ||
27631 | if (adding_value) | |
4d354d8b | 27632 | ARM_MERGE_FEATURE_SETS (selected_ext, selected_ext, |
5a70a223 | 27633 | opt->merge_value); |
69133863 | 27634 | else |
4d354d8b | 27635 | ARM_CLEAR_FEATURE (selected_ext, selected_ext, opt->clear_value); |
69133863 | 27636 | |
4d354d8b TP |
27637 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext); |
27638 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); | |
69133863 MGD |
27639 | *input_line_pointer = saved_char; |
27640 | demand_empty_rest_of_line (); | |
3d030cdb TP |
27641 | /* Allowing Thumb division instructions for ARMv7 in autodetection rely |
27642 | on this return so that duplicate extensions (extensions with the | |
27643 | same name as a previous extension in the list) are not considered | |
27644 | for command-line parsing. */ | |
69133863 MGD |
27645 | return; |
27646 | } | |
27647 | ||
27648 | if (opt->name == NULL) | |
e673710a | 27649 | as_bad (_("unknown architecture extension `%s'\n"), name); |
69133863 MGD |
27650 | |
27651 | *input_line_pointer = saved_char; | |
27652 | ignore_rest_of_line (); | |
27653 | } | |
27654 | ||
ee065d83 PB |
27655 | /* Parse a .fpu directive. */ |
27656 | ||
27657 | static void | |
27658 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) | |
27659 | { | |
69133863 | 27660 | const struct arm_option_fpu_value_table *opt; |
ee065d83 PB |
27661 | char saved_char; |
27662 | char *name; | |
27663 | ||
27664 | name = input_line_pointer; | |
5f4273c7 | 27665 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
27666 | input_line_pointer++; |
27667 | saved_char = *input_line_pointer; | |
27668 | *input_line_pointer = 0; | |
5f4273c7 | 27669 | |
ee065d83 PB |
27670 | for (opt = arm_fpus; opt->name != NULL; opt++) |
27671 | if (streq (opt->name, name)) | |
27672 | { | |
4d354d8b TP |
27673 | selected_fpu = opt->value; |
27674 | #ifndef CPU_DEFAULT | |
27675 | if (no_cpu_selected ()) | |
27676 | ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu); | |
27677 | else | |
27678 | #endif | |
27679 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); | |
ee065d83 PB |
27680 | *input_line_pointer = saved_char; |
27681 | demand_empty_rest_of_line (); | |
27682 | return; | |
27683 | } | |
27684 | ||
27685 | as_bad (_("unknown floating point format `%s'\n"), name); | |
27686 | *input_line_pointer = saved_char; | |
27687 | ignore_rest_of_line (); | |
27688 | } | |
ee065d83 | 27689 | |
794ba86a | 27690 | /* Copy symbol information. */ |
f31fef98 | 27691 | |
794ba86a DJ |
27692 | void |
27693 | arm_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
27694 | { | |
27695 | ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); | |
27696 | } | |
e04befd0 | 27697 | |
f31fef98 | 27698 | #ifdef OBJ_ELF |
e04befd0 AS |
27699 | /* Given a symbolic attribute NAME, return the proper integer value. |
27700 | Returns -1 if the attribute is not known. */ | |
f31fef98 | 27701 | |
e04befd0 AS |
27702 | int |
27703 | arm_convert_symbolic_attribute (const char *name) | |
27704 | { | |
f31fef98 NC |
27705 | static const struct |
27706 | { | |
27707 | const char * name; | |
27708 | const int tag; | |
27709 | } | |
27710 | attribute_table[] = | |
27711 | { | |
27712 | /* When you modify this table you should | |
27713 | also modify the list in doc/c-arm.texi. */ | |
e04befd0 | 27714 | #define T(tag) {#tag, tag} |
f31fef98 NC |
27715 | T (Tag_CPU_raw_name), |
27716 | T (Tag_CPU_name), | |
27717 | T (Tag_CPU_arch), | |
27718 | T (Tag_CPU_arch_profile), | |
27719 | T (Tag_ARM_ISA_use), | |
27720 | T (Tag_THUMB_ISA_use), | |
75375b3e | 27721 | T (Tag_FP_arch), |
f31fef98 NC |
27722 | T (Tag_VFP_arch), |
27723 | T (Tag_WMMX_arch), | |
27724 | T (Tag_Advanced_SIMD_arch), | |
27725 | T (Tag_PCS_config), | |
27726 | T (Tag_ABI_PCS_R9_use), | |
27727 | T (Tag_ABI_PCS_RW_data), | |
27728 | T (Tag_ABI_PCS_RO_data), | |
27729 | T (Tag_ABI_PCS_GOT_use), | |
27730 | T (Tag_ABI_PCS_wchar_t), | |
27731 | T (Tag_ABI_FP_rounding), | |
27732 | T (Tag_ABI_FP_denormal), | |
27733 | T (Tag_ABI_FP_exceptions), | |
27734 | T (Tag_ABI_FP_user_exceptions), | |
27735 | T (Tag_ABI_FP_number_model), | |
75375b3e | 27736 | T (Tag_ABI_align_needed), |
f31fef98 | 27737 | T (Tag_ABI_align8_needed), |
75375b3e | 27738 | T (Tag_ABI_align_preserved), |
f31fef98 NC |
27739 | T (Tag_ABI_align8_preserved), |
27740 | T (Tag_ABI_enum_size), | |
27741 | T (Tag_ABI_HardFP_use), | |
27742 | T (Tag_ABI_VFP_args), | |
27743 | T (Tag_ABI_WMMX_args), | |
27744 | T (Tag_ABI_optimization_goals), | |
27745 | T (Tag_ABI_FP_optimization_goals), | |
27746 | T (Tag_compatibility), | |
27747 | T (Tag_CPU_unaligned_access), | |
75375b3e | 27748 | T (Tag_FP_HP_extension), |
f31fef98 NC |
27749 | T (Tag_VFP_HP_extension), |
27750 | T (Tag_ABI_FP_16bit_format), | |
cd21e546 MGD |
27751 | T (Tag_MPextension_use), |
27752 | T (Tag_DIV_use), | |
f31fef98 NC |
27753 | T (Tag_nodefaults), |
27754 | T (Tag_also_compatible_with), | |
27755 | T (Tag_conformance), | |
27756 | T (Tag_T2EE_use), | |
27757 | T (Tag_Virtualization_use), | |
15afaa63 | 27758 | T (Tag_DSP_extension), |
cd21e546 | 27759 | /* We deliberately do not include Tag_MPextension_use_legacy. */ |
e04befd0 | 27760 | #undef T |
f31fef98 | 27761 | }; |
e04befd0 AS |
27762 | unsigned int i; |
27763 | ||
27764 | if (name == NULL) | |
27765 | return -1; | |
27766 | ||
f31fef98 | 27767 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
c921be7d | 27768 | if (streq (name, attribute_table[i].name)) |
e04befd0 AS |
27769 | return attribute_table[i].tag; |
27770 | ||
27771 | return -1; | |
27772 | } | |
267bf995 | 27773 | |
93ef582d NC |
27774 | /* Apply sym value for relocations only in the case that they are for |
27775 | local symbols in the same segment as the fixup and you have the | |
27776 | respective architectural feature for blx and simple switches. */ | |
0198d5e6 | 27777 | |
267bf995 | 27778 | int |
93ef582d | 27779 | arm_apply_sym_value (struct fix * fixP, segT this_seg) |
267bf995 RR |
27780 | { |
27781 | if (fixP->fx_addsy | |
27782 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
93ef582d NC |
27783 | /* PR 17444: If the local symbol is in a different section then a reloc |
27784 | will always be generated for it, so applying the symbol value now | |
27785 | will result in a double offset being stored in the relocation. */ | |
27786 | && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg) | |
34e77a92 | 27787 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
267bf995 RR |
27788 | { |
27789 | switch (fixP->fx_r_type) | |
27790 | { | |
27791 | case BFD_RELOC_ARM_PCREL_BLX: | |
27792 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
27793 | if (ARM_IS_FUNC (fixP->fx_addsy)) | |
27794 | return 1; | |
27795 | break; | |
27796 | ||
27797 | case BFD_RELOC_ARM_PCREL_CALL: | |
27798 | case BFD_RELOC_THUMB_PCREL_BLX: | |
27799 | if (THUMB_IS_FUNC (fixP->fx_addsy)) | |
93ef582d | 27800 | return 1; |
267bf995 RR |
27801 | break; |
27802 | ||
27803 | default: | |
27804 | break; | |
27805 | } | |
27806 | ||
27807 | } | |
27808 | return 0; | |
27809 | } | |
f31fef98 | 27810 | #endif /* OBJ_ELF */ |