[binutils, Arm] Add support for conditional instructions in Armv8.1-M Mainline
[deliverable/binutils-gdb.git] / gas / config / tc-arm.c
CommitLineData
b99bd4ef 1/* tc-arm.c -- Assemble for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
b99bd4ef
NC
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
22d9c8c5 5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
34920d91
NC
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
b99bd4ef
NC
8
9 This file is part of GAS, the GNU Assembler.
10
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
ec2655a6 13 the Free Software Foundation; either version 3, or (at your option)
b99bd4ef
NC
14 any later version.
15
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
c19d1205 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
b99bd4ef
NC
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
699d2810
NC
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 02110-1301, USA. */
b99bd4ef 25
42a68e18 26#include "as.h"
5287ad62 27#include <limits.h>
037e8744 28#include <stdarg.h>
c19d1205 29#define NO_RELOC 0
3882b010 30#include "safe-ctype.h"
b99bd4ef
NC
31#include "subsegs.h"
32#include "obstack.h"
3da1d841 33#include "libiberty.h"
f263249b
RE
34#include "opcode/arm.h"
35
b99bd4ef
NC
36#ifdef OBJ_ELF
37#include "elf/arm.h"
a394c00f 38#include "dw2gencfi.h"
b99bd4ef
NC
39#endif
40
f0927246
NC
41#include "dwarf2dbg.h"
42
7ed4c4c5
NC
43#ifdef OBJ_ELF
44/* Must be at least the size of the largest unwind opcode (currently two). */
45#define ARM_OPCODE_CHUNK_SIZE 8
46
47/* This structure holds the unwinding state. */
48
49static struct
50{
c19d1205
ZW
51 symbolS * proc_start;
52 symbolS * table_entry;
53 symbolS * personality_routine;
54 int personality_index;
7ed4c4c5 55 /* The segment containing the function. */
c19d1205
ZW
56 segT saved_seg;
57 subsegT saved_subseg;
7ed4c4c5
NC
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes;
c19d1205
ZW
60 int opcode_count;
61 int opcode_alloc;
7ed4c4c5 62 /* The number of bytes pushed to the stack. */
c19d1205 63 offsetT frame_size;
7ed4c4c5
NC
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
c19d1205 67 offsetT pending_offset;
7ed4c4c5 68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
c19d1205
ZW
69 hold the reg+offset to use when restoring sp from a frame pointer. */
70 offsetT fp_offset;
71 int fp_reg;
7ed4c4c5 72 /* Nonzero if an unwind_setfp directive has been seen. */
c19d1205 73 unsigned fp_used:1;
7ed4c4c5 74 /* Nonzero if the last opcode restores sp from fp_reg. */
c19d1205 75 unsigned sp_restored:1;
7ed4c4c5
NC
76} unwind;
77
18a20338
CL
78/* Whether --fdpic was given. */
79static int arm_fdpic;
80
8b1ad454
NC
81#endif /* OBJ_ELF */
82
4962c51a
MS
83/* Results from operand parsing worker functions. */
84
85typedef enum
86{
87 PARSE_OPERAND_SUCCESS,
88 PARSE_OPERAND_FAIL,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90} parse_operand_result;
91
33a392fb
PB
92enum arm_float_abi
93{
94 ARM_FLOAT_ABI_HARD,
95 ARM_FLOAT_ABI_SOFTFP,
96 ARM_FLOAT_ABI_SOFT
97};
98
c19d1205 99/* Types of processor to assemble for. */
b99bd4ef 100#ifndef CPU_DEFAULT
8a59fff3 101/* The code that was here used to select a default CPU depending on compiler
fa94de6b 102 pre-defines which were only present when doing native builds, thus
8a59fff3
MGD
103 changing gas' default behaviour depending upon the build host.
104
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
b99bd4ef
NC
107#endif
108
109#ifndef FPU_DEFAULT
c820d418
MM
110# ifdef TE_LINUX
111# define FPU_DEFAULT FPU_ARCH_FPA
112# elif defined (TE_NetBSD)
113# ifdef OBJ_ELF
114# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115# else
116 /* Legacy a.out format. */
117# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118# endif
4e7fd91e
PB
119# elif defined (TE_VXWORKS)
120# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
c820d418
MM
121# else
122 /* For backwards compatibility, default to FPA. */
123# define FPU_DEFAULT FPU_ARCH_FPA
124# endif
125#endif /* ifndef FPU_DEFAULT */
b99bd4ef 126
c19d1205 127#define streq(a, b) (strcmp (a, b) == 0)
b99bd4ef 128
4d354d8b
TP
129/* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
e74cfd16 132static arm_feature_set cpu_variant;
4d354d8b
TP
133/* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
e74cfd16
PB
135static arm_feature_set arm_arch_used;
136static arm_feature_set thumb_arch_used;
b99bd4ef 137
b99bd4ef 138/* Flags stored in private area of BFD structure. */
c19d1205
ZW
139static int uses_apcs_26 = FALSE;
140static int atpcs = FALSE;
b34976b6
AM
141static int support_interwork = FALSE;
142static int uses_apcs_float = FALSE;
c19d1205 143static int pic_code = FALSE;
845b51d6 144static int fix_v4bx = FALSE;
278df34e
NS
145/* Warn on using deprecated features. */
146static int warn_on_deprecated = TRUE;
147
2e6976a8
DG
148/* Understand CodeComposer Studio assembly syntax. */
149bfd_boolean codecomposer_syntax = FALSE;
03b1477f
RE
150
151/* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
153 assembly flags. */
4d354d8b
TP
154
155/* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157static const arm_feature_set *legacy_cpu = NULL;
158static const arm_feature_set *legacy_fpu = NULL;
159
160/* CPU, extension and FPU feature bits selected by -mcpu. */
161static const arm_feature_set *mcpu_cpu_opt = NULL;
162static arm_feature_set *mcpu_ext_opt = NULL;
163static const arm_feature_set *mcpu_fpu_opt = NULL;
164
165/* CPU, extension and FPU feature bits selected by -march. */
166static const arm_feature_set *march_cpu_opt = NULL;
167static arm_feature_set *march_ext_opt = NULL;
168static const arm_feature_set *march_fpu_opt = NULL;
169
170/* Feature bits selected by -mfpu. */
171static const arm_feature_set *mfpu_opt = NULL;
e74cfd16
PB
172
173/* Constants for known architecture features. */
174static const arm_feature_set fpu_default = FPU_DEFAULT;
f85d59c3 175static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V1;
e74cfd16 176static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
f85d59c3
KT
177static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V3;
178static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED = FPU_ARCH_NEON_V1;
e74cfd16
PB
179static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
180static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
69c9e028 181#ifdef OBJ_ELF
e74cfd16 182static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
69c9e028 183#endif
e74cfd16
PB
184static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
185
186#ifdef CPU_DEFAULT
187static const arm_feature_set cpu_default = CPU_DEFAULT;
188#endif
189
823d2571 190static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
4070243b 191static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V2);
823d2571
TG
192static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S);
193static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3);
194static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M);
195static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4);
196static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T);
197static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5);
e74cfd16 198static const arm_feature_set arm_ext_v4t_5 =
823d2571
TG
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5);
200static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T);
201static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E);
202static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP);
203static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J);
204static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
205static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K);
206static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2);
55e8aae7
SP
207/* Only for compatability of hint instructions. */
208static const arm_feature_set arm_ext_v6k_v6t2 =
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K | ARM_EXT_V6T2);
823d2571
TG
210static const arm_feature_set arm_ext_v6_notm =
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM);
212static const arm_feature_set arm_ext_v6_dsp =
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP);
214static const arm_feature_set arm_ext_barrier =
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER);
216static const arm_feature_set arm_ext_msr =
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR);
218static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV);
219static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7);
220static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A);
221static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R);
69c9e028 222#ifdef OBJ_ELF
e7d39ed3 223static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);
69c9e028 224#endif
823d2571 225static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8);
7e806470 226static const arm_feature_set arm_ext_m =
173205ca 227 ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_V7M,
16a1fa25 228 ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
823d2571
TG
229static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP);
230static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC);
231static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS);
232static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV);
233static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT);
ddfded2f 234static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN);
4ed7ed8d 235static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M);
16a1fa25
TP
236static const arm_feature_set arm_ext_v8m_main =
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN);
e12437dc
AV
238static const arm_feature_set arm_ext_v8_1m_main =
239ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
16a1fa25
TP
240/* Instructions in ARMv8-M only found in M profile architectures. */
241static const arm_feature_set arm_ext_v8m_m_only =
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
ff8646ee
TP
243static const arm_feature_set arm_ext_v6t2_v8m =
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M);
4ed7ed8d
TP
245/* Instructions shared between ARMv8-A and ARMv8-M. */
246static const arm_feature_set arm_ext_atomics =
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS);
69c9e028 248#ifdef OBJ_ELF
15afaa63
TP
249/* DSP instructions Tag_DSP_extension refers to. */
250static const arm_feature_set arm_ext_dsp =
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E | ARM_EXT_V5ExP | ARM_EXT_V6_DSP);
69c9e028 252#endif
4d1464f2
MW
253static const arm_feature_set arm_ext_ras =
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS);
b8ec4e87
JW
255/* FP16 instructions. */
256static const arm_feature_set arm_ext_fp16 =
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
01f48020
TC
258static const arm_feature_set arm_ext_fp16_fml =
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML);
dec41383
JW
260static const arm_feature_set arm_ext_v8_2 =
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A);
49e8a725
SN
262static const arm_feature_set arm_ext_v8_3 =
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A);
7fadb25d
SD
264static const arm_feature_set arm_ext_sb =
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB);
dad0c3bf
SD
266static const arm_feature_set arm_ext_predres =
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES);
e74cfd16
PB
268
269static const arm_feature_set arm_arch_any = ARM_ANY;
49fa50ef 270#ifdef OBJ_ELF
2c6b98ea 271static const arm_feature_set fpu_any = FPU_ANY;
49fa50ef 272#endif
f85d59c3 273static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1);
e74cfd16
PB
274static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
275static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
276
2d447fca 277static const arm_feature_set arm_cext_iwmmxt2 =
823d2571 278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2);
e74cfd16 279static const arm_feature_set arm_cext_iwmmxt =
823d2571 280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT);
e74cfd16 281static const arm_feature_set arm_cext_xscale =
823d2571 282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE);
e74cfd16 283static const arm_feature_set arm_cext_maverick =
823d2571
TG
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK);
285static const arm_feature_set fpu_fpa_ext_v1 =
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1);
287static const arm_feature_set fpu_fpa_ext_v2 =
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2);
e74cfd16 289static const arm_feature_set fpu_vfp_ext_v1xd =
823d2571
TG
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD);
291static const arm_feature_set fpu_vfp_ext_v1 =
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1);
293static const arm_feature_set fpu_vfp_ext_v2 =
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2);
295static const arm_feature_set fpu_vfp_ext_v3xd =
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD);
297static const arm_feature_set fpu_vfp_ext_v3 =
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3);
b1cc4aeb 299static const arm_feature_set fpu_vfp_ext_d32 =
823d2571
TG
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32);
301static const arm_feature_set fpu_neon_ext_v1 =
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1);
5287ad62 303static const arm_feature_set fpu_vfp_v3_or_neon_ext =
823d2571 304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
a7ad558c
AV
305static const arm_feature_set mve_ext =
306 ARM_FEATURE_COPROC (FPU_MVE);
307static const arm_feature_set mve_fp_ext =
308 ARM_FEATURE_COPROC (FPU_MVE_FP);
69c9e028 309#ifdef OBJ_ELF
823d2571
TG
310static const arm_feature_set fpu_vfp_fp16 =
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16);
312static const arm_feature_set fpu_neon_ext_fma =
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA);
69c9e028 314#endif
823d2571
TG
315static const arm_feature_set fpu_vfp_ext_fma =
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA);
bca38921 317static const arm_feature_set fpu_vfp_ext_armv8 =
823d2571 318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8);
a715796b 319static const arm_feature_set fpu_vfp_ext_armv8xd =
823d2571 320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD);
bca38921 321static const arm_feature_set fpu_neon_ext_armv8 =
823d2571 322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8);
bca38921 323static const arm_feature_set fpu_crypto_ext_armv8 =
823d2571 324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8);
dd5181d5 325static const arm_feature_set crc_ext_armv8 =
823d2571 326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8);
d6b4b13e 327static const arm_feature_set fpu_neon_ext_v8_1 =
643afb90 328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA);
c604a79a
JW
329static const arm_feature_set fpu_neon_ext_dotprod =
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD);
e74cfd16 331
33a392fb 332static int mfloat_abi_opt = -1;
4d354d8b
TP
333/* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
334 directive. */
335static arm_feature_set selected_arch = ARM_ARCH_NONE;
336/* Extension feature bits selected by the last -mcpu/-march or .arch_extension
337 directive. */
338static arm_feature_set selected_ext = ARM_ARCH_NONE;
339/* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
341 directive. */
e74cfd16 342static arm_feature_set selected_cpu = ARM_ARCH_NONE;
4d354d8b
TP
343/* FPU feature bits selected by the last -mfpu or .fpu directive. */
344static arm_feature_set selected_fpu = FPU_NONE;
345/* Feature bits selected by the last .object_arch directive. */
346static arm_feature_set selected_object_arch = ARM_ARCH_NONE;
ee065d83 347/* Must be long enough to hold any of the names in arm_cpus. */
ef8e6722 348static char selected_cpu_name[20];
8d67f500 349
aacf0b33
KT
350extern FLONUM_TYPE generic_floating_point_number;
351
8d67f500
NC
352/* Return if no cpu was selected on command-line. */
353static bfd_boolean
354no_cpu_selected (void)
355{
823d2571 356 return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none);
8d67f500
NC
357}
358
7cc69913 359#ifdef OBJ_ELF
deeaaff8
DJ
360# ifdef EABI_DEFAULT
361static int meabi_flags = EABI_DEFAULT;
362# else
d507cf36 363static int meabi_flags = EF_ARM_EABI_UNKNOWN;
deeaaff8 364# endif
e1da3f5b 365
ee3c0378
AS
366static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
367
e1da3f5b 368bfd_boolean
5f4273c7 369arm_is_eabi (void)
e1da3f5b
PB
370{
371 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
372}
7cc69913 373#endif
b99bd4ef 374
b99bd4ef 375#ifdef OBJ_ELF
c19d1205 376/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
b99bd4ef
NC
377symbolS * GOT_symbol;
378#endif
379
b99bd4ef
NC
380/* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
383 instructions. */
384static int thumb_mode = 0;
8dc2430f
NC
385/* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388#define MODE_RECORDED (1 << 4)
b99bd4ef 389
e07e6e58
NC
390/* Specifies the intrinsic IT insn behavior mode. */
391enum implicit_it_mode
392{
393 IMPLICIT_IT_MODE_NEVER = 0x00,
394 IMPLICIT_IT_MODE_ARM = 0x01,
395 IMPLICIT_IT_MODE_THUMB = 0x02,
396 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
397};
398static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
399
c19d1205
ZW
400/* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
402
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
407 there.)
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
410 machine code.
411
412 Important differences from the old Thumb mode:
413
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
422
423static bfd_boolean unified_syntax = FALSE;
b99bd4ef 424
bacebabc
RM
425/* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
477330fc
RM
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429const char arm_symbol_chars[] = "#[]{}";
bacebabc 430
5287ad62
JB
431enum neon_el_type
432{
dcbf9037 433 NT_invtype,
5287ad62
JB
434 NT_untyped,
435 NT_integer,
436 NT_float,
437 NT_poly,
438 NT_signed,
dcbf9037 439 NT_unsigned
5287ad62
JB
440};
441
442struct neon_type_el
443{
444 enum neon_el_type type;
445 unsigned size;
446};
447
448#define NEON_MAX_TYPE_ELS 4
449
450struct neon_type
451{
452 struct neon_type_el el[NEON_MAX_TYPE_ELS];
453 unsigned elems;
454};
455
5ee91343 456enum pred_instruction_type
e07e6e58 457{
5ee91343
AV
458 OUTSIDE_PRED_INSN,
459 INSIDE_VPT_INSN,
e07e6e58
NC
460 INSIDE_IT_INSN,
461 INSIDE_IT_LAST_INSN,
462 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
477330fc 463 if inside, should be the last one. */
e07e6e58 464 NEUTRAL_IT_INSN, /* This could be either inside or outside,
477330fc 465 i.e. BKPT and NOP. */
5ee91343
AV
466 IT_INSN, /* The IT insn has been parsed. */
467 VPT_INSN, /* The VPT/VPST insn has been parsed. */
35c228db 468 MVE_OUTSIDE_PRED_INSN , /* Instruction to indicate a MVE instruction without
5ee91343 469 a predication code. */
35c228db 470 MVE_UNPREDICABLE_INSN /* MVE instruction that is non-predicable. */
e07e6e58
NC
471};
472
ad6cec43
MGD
473/* The maximum number of operands we need. */
474#define ARM_IT_MAX_OPERANDS 6
e2b0ab59 475#define ARM_IT_MAX_RELOCS 3
ad6cec43 476
b99bd4ef
NC
477struct arm_it
478{
c19d1205 479 const char * error;
b99bd4ef 480 unsigned long instruction;
c19d1205
ZW
481 int size;
482 int size_req;
483 int cond;
037e8744
JB
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
486 appropriate. */
487 int uncond_value;
5287ad62 488 struct neon_type vectype;
88714cb8
DG
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
491 int is_neon;
0110f2b8
PB
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
494 unsigned long relax;
b99bd4ef
NC
495 struct
496 {
497 bfd_reloc_code_real_type type;
c19d1205
ZW
498 expressionS exp;
499 int pc_rel;
e2b0ab59 500 } relocs[ARM_IT_MAX_RELOCS];
b99bd4ef 501
5ee91343 502 enum pred_instruction_type pred_insn_type;
e07e6e58 503
c19d1205
ZW
504 struct
505 {
506 unsigned reg;
ca3f61f7 507 signed int imm;
dcbf9037 508 struct neon_type_el vectype;
ca3f61f7
NC
509 unsigned present : 1; /* Operand present. */
510 unsigned isreg : 1; /* Operand was a register. */
f5f10c66
AV
511 unsigned immisreg : 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
57785aa2
AV
513 unsigned isscalar : 2; /* Operand is a (SIMD) scalar:
514 0) not scalar,
515 1) Neon scalar,
516 2) MVE scalar. */
5287ad62 517 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
c96612cc 518 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
5287ad62
JB
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
037e8744 522 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
5ee91343 523 unsigned isquad : 1; /* Operand is SIMD quad register. */
037e8744 524 unsigned issingle : 1; /* Operand is VFP single-precision register. */
1b883319 525 unsigned iszr : 1; /* Operand is ZR register. */
ca3f61f7
NC
526 unsigned hasreloc : 1; /* Operand has relocation suffix. */
527 unsigned writeback : 1; /* Operand has trailing ! */
528 unsigned preind : 1; /* Preindexed address. */
529 unsigned postind : 1; /* Postindexed address. */
530 unsigned negative : 1; /* Index register was negated. */
531 unsigned shifted : 1; /* Shift applied to operation. */
532 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
ad6cec43 533 } operands[ARM_IT_MAX_OPERANDS];
b99bd4ef
NC
534};
535
c19d1205 536static struct arm_it inst;
b99bd4ef
NC
537
538#define NUM_FLOAT_VALS 8
539
05d2d07e 540const char * fp_const[] =
b99bd4ef
NC
541{
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
543};
544
b99bd4ef
NC
545LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
546
547#define FAIL (-1)
548#define SUCCESS (0)
549
550#define SUFF_S 1
551#define SUFF_D 2
552#define SUFF_E 3
553#define SUFF_P 4
554
c19d1205
ZW
555#define CP_T_X 0x00008000
556#define CP_T_Y 0x00400000
b99bd4ef 557
c19d1205
ZW
558#define CONDS_BIT 0x00100000
559#define LOAD_BIT 0x00100000
b99bd4ef
NC
560
561#define DOUBLE_LOAD_FLAG 0x00000001
562
563struct asm_cond
564{
d3ce72d0 565 const char * template_name;
c921be7d 566 unsigned long value;
b99bd4ef
NC
567};
568
c19d1205 569#define COND_ALWAYS 0xE
b99bd4ef 570
b99bd4ef
NC
571struct asm_psr
572{
d3ce72d0 573 const char * template_name;
c921be7d 574 unsigned long field;
b99bd4ef
NC
575};
576
62b3e311
PB
577struct asm_barrier_opt
578{
e797f7e0
MGD
579 const char * template_name;
580 unsigned long value;
581 const arm_feature_set arch;
62b3e311
PB
582};
583
2d2255b5 584/* The bit that distinguishes CPSR and SPSR. */
b99bd4ef
NC
585#define SPSR_BIT (1 << 22)
586
c19d1205
ZW
587/* The individual PSR flag bits. */
588#define PSR_c (1 << 16)
589#define PSR_x (1 << 17)
590#define PSR_s (1 << 18)
591#define PSR_f (1 << 19)
b99bd4ef 592
c19d1205 593struct reloc_entry
bfae80f2 594{
0198d5e6 595 const char * name;
c921be7d 596 bfd_reloc_code_real_type reloc;
bfae80f2
RE
597};
598
5287ad62 599enum vfp_reg_pos
bfae80f2 600{
5287ad62
JB
601 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
602 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
bfae80f2
RE
603};
604
605enum vfp_ldstm_type
606{
607 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
608};
609
dcbf9037
JB
610/* Bits for DEFINED field in neon_typed_alias. */
611#define NTA_HASTYPE 1
612#define NTA_HASINDEX 2
613
614struct neon_typed_alias
615{
c921be7d
NC
616 unsigned char defined;
617 unsigned char index;
618 struct neon_type_el eltype;
dcbf9037
JB
619};
620
c19d1205 621/* ARM register categories. This includes coprocessor numbers and various
5aa75429
TP
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
c19d1205 624enum arm_reg_type
bfae80f2 625{
c19d1205
ZW
626 REG_TYPE_RN,
627 REG_TYPE_CP,
628 REG_TYPE_CN,
629 REG_TYPE_FN,
630 REG_TYPE_VFS,
631 REG_TYPE_VFD,
5287ad62 632 REG_TYPE_NQ,
037e8744 633 REG_TYPE_VFSD,
5287ad62 634 REG_TYPE_NDQ,
dec41383 635 REG_TYPE_NSD,
037e8744 636 REG_TYPE_NSDQ,
c19d1205
ZW
637 REG_TYPE_VFC,
638 REG_TYPE_MVF,
639 REG_TYPE_MVD,
640 REG_TYPE_MVFX,
641 REG_TYPE_MVDX,
642 REG_TYPE_MVAX,
5ee91343 643 REG_TYPE_MQ,
c19d1205
ZW
644 REG_TYPE_DSPSC,
645 REG_TYPE_MMXWR,
646 REG_TYPE_MMXWC,
647 REG_TYPE_MMXWCG,
648 REG_TYPE_XSCALE,
5ee91343 649 REG_TYPE_RNB,
1b883319 650 REG_TYPE_ZR
bfae80f2
RE
651};
652
dcbf9037
JB
653/* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
6c43fab6
RE
657struct reg_entry
658{
c921be7d 659 const char * name;
90ec0d68 660 unsigned int number;
c921be7d
NC
661 unsigned char type;
662 unsigned char builtin;
663 struct neon_typed_alias * neon;
6c43fab6
RE
664};
665
c19d1205 666/* Diagnostics used when we don't get a register of the expected type. */
c921be7d 667const char * const reg_expected_msgs[] =
c19d1205 668{
5aa75429
TP
669 [REG_TYPE_RN] = N_("ARM register expected"),
670 [REG_TYPE_CP] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN] = N_("co-processor register expected"),
672 [REG_TYPE_FN] = N_("FPA register expected"),
673 [REG_TYPE_VFS] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ] = N_("VFP single, double or Neon quad precision register"
680 " expected"),
681 [REG_TYPE_VFC] = N_("VFP system register expected"),
682 [REG_TYPE_MVF] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE] = N_("XScale accumulator register expected"),
5ee91343 692 [REG_TYPE_MQ] = N_("MVE vector register expected"),
5aa75429 693 [REG_TYPE_RNB] = N_("")
6c43fab6
RE
694};
695
c19d1205 696/* Some well known registers that we refer to directly elsewhere. */
bd340a04 697#define REG_R12 12
c19d1205
ZW
698#define REG_SP 13
699#define REG_LR 14
700#define REG_PC 15
404ff6b5 701
b99bd4ef
NC
702/* ARM instructions take 4bytes in the object file, Thumb instructions
703 take 2: */
c19d1205 704#define INSN_SIZE 4
b99bd4ef
NC
705
706struct asm_opcode
707{
708 /* Basic string to match. */
d3ce72d0 709 const char * template_name;
c19d1205
ZW
710
711 /* Parameters to instruction. */
5be8be5d 712 unsigned int operands[8];
c19d1205
ZW
713
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag : 4;
b99bd4ef
NC
716
717 /* Basic instruction code. */
a302e574 718 unsigned int avalue;
b99bd4ef 719
c19d1205
ZW
720 /* Thumb-format instruction code. */
721 unsigned int tvalue;
b99bd4ef 722
90e4755a 723 /* Which architecture variant provides this instruction. */
c921be7d
NC
724 const arm_feature_set * avariant;
725 const arm_feature_set * tvariant;
c19d1205
ZW
726
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode) (void);
b99bd4ef 729
c19d1205
ZW
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode) (void);
5ee91343
AV
732
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred : 1;
b99bd4ef
NC
735};
736
a737bd4d
NC
737/* Defines for various bits that we will want to toggle. */
738#define INST_IMMEDIATE 0x02000000
739#define OFFSET_REG 0x02000000
c19d1205 740#define HWOFFSET_IMM 0x00400000
a737bd4d
NC
741#define SHIFT_BY_REG 0x00000010
742#define PRE_INDEX 0x01000000
743#define INDEX_UP 0x00800000
744#define WRITE_BACK 0x00200000
745#define LDM_TYPE_2_OR_3 0x00400000
a028a6f5 746#define CPSI_MMOD 0x00020000
90e4755a 747
a737bd4d
NC
748#define LITERAL_MASK 0xf000f000
749#define OPCODE_MASK 0xfe1fffff
750#define V4_STR_BIT 0x00000020
8335d6aa 751#define VLDR_VMOV_SAME 0x0040f000
90e4755a 752
efd81785
PB
753#define T2_SUBS_PC_LR 0xf3de8f00
754
a737bd4d 755#define DATA_OP_SHIFT 21
bada4342 756#define SBIT_SHIFT 20
90e4755a 757
ef8d22e6
PB
758#define T2_OPCODE_MASK 0xfe1fffff
759#define T2_DATA_OP_SHIFT 21
bada4342 760#define T2_SBIT_SHIFT 20
ef8d22e6 761
6530b175
NC
762#define A_COND_MASK 0xf0000000
763#define A_PUSH_POP_OP_MASK 0x0fff0000
764
765/* Opcodes for pushing/poping registers to/from the stack. */
766#define A1_OPCODE_PUSH 0x092d0000
767#define A2_OPCODE_PUSH 0x052d0004
768#define A2_OPCODE_POP 0x049d0004
769
a737bd4d
NC
770/* Codes to distinguish the arithmetic instructions. */
771#define OPCODE_AND 0
772#define OPCODE_EOR 1
773#define OPCODE_SUB 2
774#define OPCODE_RSB 3
775#define OPCODE_ADD 4
776#define OPCODE_ADC 5
777#define OPCODE_SBC 6
778#define OPCODE_RSC 7
779#define OPCODE_TST 8
780#define OPCODE_TEQ 9
781#define OPCODE_CMP 10
782#define OPCODE_CMN 11
783#define OPCODE_ORR 12
784#define OPCODE_MOV 13
785#define OPCODE_BIC 14
786#define OPCODE_MVN 15
90e4755a 787
ef8d22e6
PB
788#define T2_OPCODE_AND 0
789#define T2_OPCODE_BIC 1
790#define T2_OPCODE_ORR 2
791#define T2_OPCODE_ORN 3
792#define T2_OPCODE_EOR 4
793#define T2_OPCODE_ADD 8
794#define T2_OPCODE_ADC 10
795#define T2_OPCODE_SBC 11
796#define T2_OPCODE_SUB 13
797#define T2_OPCODE_RSB 14
798
a737bd4d
NC
799#define T_OPCODE_MUL 0x4340
800#define T_OPCODE_TST 0x4200
801#define T_OPCODE_CMN 0x42c0
802#define T_OPCODE_NEG 0x4240
803#define T_OPCODE_MVN 0x43c0
90e4755a 804
a737bd4d
NC
805#define T_OPCODE_ADD_R3 0x1800
806#define T_OPCODE_SUB_R3 0x1a00
807#define T_OPCODE_ADD_HI 0x4400
808#define T_OPCODE_ADD_ST 0xb000
809#define T_OPCODE_SUB_ST 0xb080
810#define T_OPCODE_ADD_SP 0xa800
811#define T_OPCODE_ADD_PC 0xa000
812#define T_OPCODE_ADD_I8 0x3000
813#define T_OPCODE_SUB_I8 0x3800
814#define T_OPCODE_ADD_I3 0x1c00
815#define T_OPCODE_SUB_I3 0x1e00
b99bd4ef 816
a737bd4d
NC
817#define T_OPCODE_ASR_R 0x4100
818#define T_OPCODE_LSL_R 0x4080
c19d1205
ZW
819#define T_OPCODE_LSR_R 0x40c0
820#define T_OPCODE_ROR_R 0x41c0
a737bd4d
NC
821#define T_OPCODE_ASR_I 0x1000
822#define T_OPCODE_LSL_I 0x0000
823#define T_OPCODE_LSR_I 0x0800
b99bd4ef 824
a737bd4d
NC
825#define T_OPCODE_MOV_I8 0x2000
826#define T_OPCODE_CMP_I8 0x2800
827#define T_OPCODE_CMP_LR 0x4280
828#define T_OPCODE_MOV_HR 0x4600
829#define T_OPCODE_CMP_HR 0x4500
b99bd4ef 830
a737bd4d
NC
831#define T_OPCODE_LDR_PC 0x4800
832#define T_OPCODE_LDR_SP 0x9800
833#define T_OPCODE_STR_SP 0x9000
834#define T_OPCODE_LDR_IW 0x6800
835#define T_OPCODE_STR_IW 0x6000
836#define T_OPCODE_LDR_IH 0x8800
837#define T_OPCODE_STR_IH 0x8000
838#define T_OPCODE_LDR_IB 0x7800
839#define T_OPCODE_STR_IB 0x7000
840#define T_OPCODE_LDR_RW 0x5800
841#define T_OPCODE_STR_RW 0x5000
842#define T_OPCODE_LDR_RH 0x5a00
843#define T_OPCODE_STR_RH 0x5200
844#define T_OPCODE_LDR_RB 0x5c00
845#define T_OPCODE_STR_RB 0x5400
c9b604bd 846
a737bd4d
NC
847#define T_OPCODE_PUSH 0xb400
848#define T_OPCODE_POP 0xbc00
b99bd4ef 849
2fc8bdac 850#define T_OPCODE_BRANCH 0xe000
b99bd4ef 851
a737bd4d 852#define THUMB_SIZE 2 /* Size of thumb instruction. */
a737bd4d 853#define THUMB_PP_PC_LR 0x0100
c19d1205 854#define THUMB_LOAD_BIT 0x0800
53365c0d 855#define THUMB2_LOAD_BIT 0x00100000
c19d1205 856
5ee91343 857#define BAD_SYNTAX _("syntax error")
c19d1205 858#define BAD_ARGS _("bad arguments to instruction")
fdfde340 859#define BAD_SP _("r13 not allowed here")
c19d1205 860#define BAD_PC _("r15 not allowed here")
a302e574
AV
861#define BAD_ODD _("Odd register not allowed here")
862#define BAD_EVEN _("Even register not allowed here")
c19d1205
ZW
863#define BAD_COND _("instruction cannot be conditional")
864#define BAD_OVERLAP _("registers may not be the same")
865#define BAD_HIREG _("lo register required")
866#define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
35c228db 867#define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
dfa9f0d5 868#define BAD_BRANCH _("branch must be last instruction in IT block")
e12437dc 869#define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
dfa9f0d5 870#define BAD_NOT_IT _("instruction not allowed in IT block")
5ee91343 871#define BAD_NOT_VPT _("instruction missing MVE vector predication code")
037e8744 872#define BAD_FPU _("selected FPU does not support instruction")
e07e6e58 873#define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
5ee91343
AV
874#define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
e07e6e58 876#define BAD_IT_COND _("incorrect condition in IT block")
5ee91343 877#define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
e07e6e58 878#define BAD_IT_IT _("IT falling in the range of a previous IT block")
921e5f0a 879#define MISSING_FNSTART _("missing .fnstart before unwinding directive")
5be8be5d
DG
880#define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882#define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
9db2f6b4
RL
884#define BAD_RANGE _("branch out of range")
885#define BAD_FP16 _("selected processor does not support fp16 instruction")
dd5181d5 886#define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
a9f02af8 887#define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
5ee91343
AV
888#define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
889 "block")
890#define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
891 "block")
892#define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
893 " operand")
894#define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
895 " operand")
a302e574 896#define BAD_SIMD_TYPE _("bad type in SIMD instruction")
886e1c73
AV
897#define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900#define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
35c228db 902#define BAD_EL_TYPE _("bad element type for instruction")
1b883319 903#define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
c19d1205 904
c921be7d
NC
905static struct hash_control * arm_ops_hsh;
906static struct hash_control * arm_cond_hsh;
5ee91343 907static struct hash_control * arm_vcond_hsh;
c921be7d
NC
908static struct hash_control * arm_shift_hsh;
909static struct hash_control * arm_psr_hsh;
910static struct hash_control * arm_v7m_psr_hsh;
911static struct hash_control * arm_reg_hsh;
912static struct hash_control * arm_reloc_hsh;
913static struct hash_control * arm_barrier_opt_hsh;
b99bd4ef 914
b99bd4ef
NC
915/* Stuff needed to resolve the label ambiguity
916 As:
917 ...
918 label: <insn>
919 may differ from:
920 ...
921 label:
5f4273c7 922 <insn> */
b99bd4ef
NC
923
924symbolS * last_label_seen;
b34976b6 925static int label_is_thumb_function_name = FALSE;
e07e6e58 926
3d0c9500
NC
927/* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
a737bd4d 929
c19d1205 930#define MAX_LITERAL_POOL_SIZE 1024
3d0c9500 931typedef struct literal_pool
b99bd4ef 932{
c921be7d
NC
933 expressionS literals [MAX_LITERAL_POOL_SIZE];
934 unsigned int next_free_entry;
935 unsigned int id;
936 symbolS * symbol;
937 segT section;
938 subsegT sub_section;
a8040cf2
NC
939#ifdef OBJ_ELF
940 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
941#endif
c921be7d 942 struct literal_pool * next;
8335d6aa 943 unsigned int alignment;
3d0c9500 944} literal_pool;
b99bd4ef 945
3d0c9500
NC
946/* Pointer to a linked list of literal pools. */
947literal_pool * list_of_pools = NULL;
e27ec89e 948
2e6976a8
DG
949typedef enum asmfunc_states
950{
951 OUTSIDE_ASMFUNC,
952 WAITING_ASMFUNC_NAME,
953 WAITING_ENDASMFUNC
954} asmfunc_states;
955
956static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC;
957
e07e6e58 958#ifdef OBJ_ELF
5ee91343 959# define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
e07e6e58 960#else
5ee91343 961static struct current_pred now_pred;
e07e6e58
NC
962#endif
963
964static inline int
5ee91343 965now_pred_compatible (int cond)
e07e6e58 966{
5ee91343 967 return (cond & ~1) == (now_pred.cc & ~1);
e07e6e58
NC
968}
969
970static inline int
971conditional_insn (void)
972{
973 return inst.cond != COND_ALWAYS;
974}
975
5ee91343 976static int in_pred_block (void);
e07e6e58 977
5ee91343 978static int handle_pred_state (void);
e07e6e58
NC
979
980static void force_automatic_it_block_close (void);
981
c921be7d
NC
982static void it_fsm_post_encode (void);
983
5ee91343 984#define set_pred_insn_type(type) \
e07e6e58
NC
985 do \
986 { \
5ee91343
AV
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
477330fc 989 return; \
e07e6e58
NC
990 } \
991 while (0)
992
5ee91343 993#define set_pred_insn_type_nonvoid(type, failret) \
c921be7d
NC
994 do \
995 { \
5ee91343
AV
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
477330fc 998 return failret; \
c921be7d
NC
999 } \
1000 while(0)
1001
5ee91343 1002#define set_pred_insn_type_last() \
e07e6e58
NC
1003 do \
1004 { \
1005 if (inst.cond == COND_ALWAYS) \
5ee91343 1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
e07e6e58 1007 else \
5ee91343 1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
e07e6e58
NC
1009 } \
1010 while (0)
1011
e39c1607
SD
1012/* Toggle value[pos]. */
1013#define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1014
c19d1205 1015/* Pure syntax. */
b99bd4ef 1016
c19d1205
ZW
1017/* This array holds the chars that always start a comment. If the
1018 pre-processor is disabled, these aren't very useful. */
2e6976a8 1019char arm_comment_chars[] = "@";
3d0c9500 1020
c19d1205
ZW
1021/* This array holds the chars that only start a comment at the beginning of
1022 a line. If the line seems to have the form '# 123 filename'
1023 .line and .file directives will appear in the pre-processed output. */
1024/* Note that input_file.c hand checks for '#' at the beginning of the
1025 first line of the input file. This is because the compiler outputs
1026 #NO_APP at the beginning of its output. */
1027/* Also note that comments like this one will always work. */
1028const char line_comment_chars[] = "#";
3d0c9500 1029
2e6976a8 1030char arm_line_separator_chars[] = ";";
b99bd4ef 1031
c19d1205
ZW
1032/* Chars that can be used to separate mant
1033 from exp in floating point numbers. */
1034const char EXP_CHARS[] = "eE";
3d0c9500 1035
c19d1205
ZW
1036/* Chars that mean this number is a floating point constant. */
1037/* As in 0f12.456 */
1038/* or 0d1.2345e12 */
b99bd4ef 1039
c19d1205 1040const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
3d0c9500 1041
c19d1205
ZW
1042/* Prefix characters that indicate the start of an immediate
1043 value. */
1044#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
3d0c9500 1045
c19d1205
ZW
1046/* Separator character handling. */
1047
1048#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1049
1050static inline int
1051skip_past_char (char ** str, char c)
1052{
8ab8155f
NC
1053 /* PR gas/14987: Allow for whitespace before the expected character. */
1054 skip_whitespace (*str);
427d0db6 1055
c19d1205
ZW
1056 if (**str == c)
1057 {
1058 (*str)++;
1059 return SUCCESS;
3d0c9500 1060 }
c19d1205
ZW
1061 else
1062 return FAIL;
1063}
c921be7d 1064
c19d1205 1065#define skip_past_comma(str) skip_past_char (str, ',')
3d0c9500 1066
c19d1205
ZW
1067/* Arithmetic expressions (possibly involving symbols). */
1068
1069/* Return TRUE if anything in the expression is a bignum. */
1070
0198d5e6 1071static bfd_boolean
c19d1205
ZW
1072walk_no_bignums (symbolS * sp)
1073{
1074 if (symbol_get_value_expression (sp)->X_op == O_big)
0198d5e6 1075 return TRUE;
c19d1205
ZW
1076
1077 if (symbol_get_value_expression (sp)->X_add_symbol)
3d0c9500 1078 {
c19d1205
ZW
1079 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
1080 || (symbol_get_value_expression (sp)->X_op_symbol
1081 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
3d0c9500
NC
1082 }
1083
0198d5e6 1084 return FALSE;
3d0c9500
NC
1085}
1086
0198d5e6 1087static bfd_boolean in_my_get_expression = FALSE;
c19d1205
ZW
1088
1089/* Third argument to my_get_expression. */
1090#define GE_NO_PREFIX 0
1091#define GE_IMM_PREFIX 1
1092#define GE_OPT_PREFIX 2
5287ad62
JB
1093/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1094 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1095#define GE_OPT_PREFIX_BIG 3
a737bd4d 1096
b99bd4ef 1097static int
c19d1205 1098my_get_expression (expressionS * ep, char ** str, int prefix_mode)
b99bd4ef 1099{
c19d1205 1100 char * save_in;
b99bd4ef 1101
c19d1205
ZW
1102 /* In unified syntax, all prefixes are optional. */
1103 if (unified_syntax)
5287ad62 1104 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
477330fc 1105 : GE_OPT_PREFIX;
b99bd4ef 1106
c19d1205 1107 switch (prefix_mode)
b99bd4ef 1108 {
c19d1205
ZW
1109 case GE_NO_PREFIX: break;
1110 case GE_IMM_PREFIX:
1111 if (!is_immediate_prefix (**str))
1112 {
1113 inst.error = _("immediate expression requires a # prefix");
1114 return FAIL;
1115 }
1116 (*str)++;
1117 break;
1118 case GE_OPT_PREFIX:
5287ad62 1119 case GE_OPT_PREFIX_BIG:
c19d1205
ZW
1120 if (is_immediate_prefix (**str))
1121 (*str)++;
1122 break;
0198d5e6
TC
1123 default:
1124 abort ();
c19d1205 1125 }
b99bd4ef 1126
c19d1205 1127 memset (ep, 0, sizeof (expressionS));
b99bd4ef 1128
c19d1205
ZW
1129 save_in = input_line_pointer;
1130 input_line_pointer = *str;
0198d5e6 1131 in_my_get_expression = TRUE;
2ac93be7 1132 expression (ep);
0198d5e6 1133 in_my_get_expression = FALSE;
c19d1205 1134
f86adc07 1135 if (ep->X_op == O_illegal || ep->X_op == O_absent)
b99bd4ef 1136 {
f86adc07 1137 /* We found a bad or missing expression in md_operand(). */
c19d1205
ZW
1138 *str = input_line_pointer;
1139 input_line_pointer = save_in;
1140 if (inst.error == NULL)
f86adc07
NS
1141 inst.error = (ep->X_op == O_absent
1142 ? _("missing expression") :_("bad expression"));
c19d1205
ZW
1143 return 1;
1144 }
b99bd4ef 1145
c19d1205
ZW
1146 /* Get rid of any bignums now, so that we don't generate an error for which
1147 we can't establish a line number later on. Big numbers are never valid
1148 in instructions, which is where this routine is always called. */
5287ad62
JB
1149 if (prefix_mode != GE_OPT_PREFIX_BIG
1150 && (ep->X_op == O_big
477330fc 1151 || (ep->X_add_symbol
5287ad62 1152 && (walk_no_bignums (ep->X_add_symbol)
477330fc 1153 || (ep->X_op_symbol
5287ad62 1154 && walk_no_bignums (ep->X_op_symbol))))))
c19d1205
ZW
1155 {
1156 inst.error = _("invalid constant");
1157 *str = input_line_pointer;
1158 input_line_pointer = save_in;
1159 return 1;
1160 }
b99bd4ef 1161
c19d1205
ZW
1162 *str = input_line_pointer;
1163 input_line_pointer = save_in;
0198d5e6 1164 return SUCCESS;
b99bd4ef
NC
1165}
1166
c19d1205
ZW
1167/* Turn a string in input_line_pointer into a floating point constant
1168 of type TYPE, and store the appropriate bytes in *LITP. The number
1169 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1170 returned, or NULL on OK.
b99bd4ef 1171
c19d1205
ZW
1172 Note that fp constants aren't represent in the normal way on the ARM.
1173 In big endian mode, things are as expected. However, in little endian
1174 mode fp constants are big-endian word-wise, and little-endian byte-wise
1175 within the words. For example, (double) 1.1 in big endian mode is
1176 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1177 the byte sequence 99 99 f1 3f 9a 99 99 99.
b99bd4ef 1178
c19d1205 1179 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
b99bd4ef 1180
6d4af3c2 1181const char *
c19d1205
ZW
1182md_atof (int type, char * litP, int * sizeP)
1183{
1184 int prec;
1185 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1186 char *t;
1187 int i;
b99bd4ef 1188
c19d1205
ZW
1189 switch (type)
1190 {
1191 case 'f':
1192 case 'F':
1193 case 's':
1194 case 'S':
1195 prec = 2;
1196 break;
b99bd4ef 1197
c19d1205
ZW
1198 case 'd':
1199 case 'D':
1200 case 'r':
1201 case 'R':
1202 prec = 4;
1203 break;
b99bd4ef 1204
c19d1205
ZW
1205 case 'x':
1206 case 'X':
499ac353 1207 prec = 5;
c19d1205 1208 break;
b99bd4ef 1209
c19d1205
ZW
1210 case 'p':
1211 case 'P':
499ac353 1212 prec = 5;
c19d1205 1213 break;
a737bd4d 1214
c19d1205
ZW
1215 default:
1216 *sizeP = 0;
499ac353 1217 return _("Unrecognized or unsupported floating point constant");
c19d1205 1218 }
b99bd4ef 1219
c19d1205
ZW
1220 t = atof_ieee (input_line_pointer, type, words);
1221 if (t)
1222 input_line_pointer = t;
499ac353 1223 *sizeP = prec * sizeof (LITTLENUM_TYPE);
b99bd4ef 1224
c19d1205
ZW
1225 if (target_big_endian)
1226 {
1227 for (i = 0; i < prec; i++)
1228 {
499ac353
NC
1229 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1230 litP += sizeof (LITTLENUM_TYPE);
c19d1205
ZW
1231 }
1232 }
1233 else
1234 {
e74cfd16 1235 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
c19d1205
ZW
1236 for (i = prec - 1; i >= 0; i--)
1237 {
499ac353
NC
1238 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1239 litP += sizeof (LITTLENUM_TYPE);
c19d1205
ZW
1240 }
1241 else
1242 /* For a 4 byte float the order of elements in `words' is 1 0.
1243 For an 8 byte float the order is 1 0 3 2. */
1244 for (i = 0; i < prec; i += 2)
1245 {
499ac353
NC
1246 md_number_to_chars (litP, (valueT) words[i + 1],
1247 sizeof (LITTLENUM_TYPE));
1248 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1249 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1250 litP += 2 * sizeof (LITTLENUM_TYPE);
c19d1205
ZW
1251 }
1252 }
b99bd4ef 1253
499ac353 1254 return NULL;
c19d1205 1255}
b99bd4ef 1256
c19d1205
ZW
1257/* We handle all bad expressions here, so that we can report the faulty
1258 instruction in the error message. */
0198d5e6 1259
c19d1205 1260void
91d6fa6a 1261md_operand (expressionS * exp)
c19d1205
ZW
1262{
1263 if (in_my_get_expression)
91d6fa6a 1264 exp->X_op = O_illegal;
b99bd4ef
NC
1265}
1266
c19d1205 1267/* Immediate values. */
b99bd4ef 1268
0198d5e6 1269#ifdef OBJ_ELF
c19d1205
ZW
1270/* Generic immediate-value read function for use in directives.
1271 Accepts anything that 'expression' can fold to a constant.
1272 *val receives the number. */
0198d5e6 1273
c19d1205
ZW
1274static int
1275immediate_for_directive (int *val)
b99bd4ef 1276{
c19d1205
ZW
1277 expressionS exp;
1278 exp.X_op = O_illegal;
b99bd4ef 1279
c19d1205
ZW
1280 if (is_immediate_prefix (*input_line_pointer))
1281 {
1282 input_line_pointer++;
1283 expression (&exp);
1284 }
b99bd4ef 1285
c19d1205
ZW
1286 if (exp.X_op != O_constant)
1287 {
1288 as_bad (_("expected #constant"));
1289 ignore_rest_of_line ();
1290 return FAIL;
1291 }
1292 *val = exp.X_add_number;
1293 return SUCCESS;
b99bd4ef 1294}
c19d1205 1295#endif
b99bd4ef 1296
c19d1205 1297/* Register parsing. */
b99bd4ef 1298
c19d1205
ZW
1299/* Generic register parser. CCP points to what should be the
1300 beginning of a register name. If it is indeed a valid register
1301 name, advance CCP over it and return the reg_entry structure;
1302 otherwise return NULL. Does not issue diagnostics. */
1303
1304static struct reg_entry *
1305arm_reg_parse_multi (char **ccp)
b99bd4ef 1306{
c19d1205
ZW
1307 char *start = *ccp;
1308 char *p;
1309 struct reg_entry *reg;
b99bd4ef 1310
477330fc
RM
1311 skip_whitespace (start);
1312
c19d1205
ZW
1313#ifdef REGISTER_PREFIX
1314 if (*start != REGISTER_PREFIX)
01cfc07f 1315 return NULL;
c19d1205
ZW
1316 start++;
1317#endif
1318#ifdef OPTIONAL_REGISTER_PREFIX
1319 if (*start == OPTIONAL_REGISTER_PREFIX)
1320 start++;
1321#endif
b99bd4ef 1322
c19d1205
ZW
1323 p = start;
1324 if (!ISALPHA (*p) || !is_name_beginner (*p))
1325 return NULL;
b99bd4ef 1326
c19d1205
ZW
1327 do
1328 p++;
1329 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1330
1331 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1332
1333 if (!reg)
1334 return NULL;
1335
1336 *ccp = p;
1337 return reg;
b99bd4ef
NC
1338}
1339
1340static int
dcbf9037 1341arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
477330fc 1342 enum arm_reg_type type)
b99bd4ef 1343{
c19d1205
ZW
1344 /* Alternative syntaxes are accepted for a few register classes. */
1345 switch (type)
1346 {
1347 case REG_TYPE_MVF:
1348 case REG_TYPE_MVD:
1349 case REG_TYPE_MVFX:
1350 case REG_TYPE_MVDX:
1351 /* Generic coprocessor register names are allowed for these. */
79134647 1352 if (reg && reg->type == REG_TYPE_CN)
c19d1205
ZW
1353 return reg->number;
1354 break;
69b97547 1355
c19d1205
ZW
1356 case REG_TYPE_CP:
1357 /* For backward compatibility, a bare number is valid here. */
1358 {
1359 unsigned long processor = strtoul (start, ccp, 10);
1360 if (*ccp != start && processor <= 15)
1361 return processor;
1362 }
1a0670f3 1363 /* Fall through. */
6057a28f 1364
c19d1205
ZW
1365 case REG_TYPE_MMXWC:
1366 /* WC includes WCG. ??? I'm not sure this is true for all
1367 instructions that take WC registers. */
79134647 1368 if (reg && reg->type == REG_TYPE_MMXWCG)
c19d1205 1369 return reg->number;
6057a28f 1370 break;
c19d1205 1371
6057a28f 1372 default:
c19d1205 1373 break;
6057a28f
NC
1374 }
1375
dcbf9037
JB
1376 return FAIL;
1377}
1378
1379/* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1380 return value is the register number or FAIL. */
1381
1382static int
1383arm_reg_parse (char **ccp, enum arm_reg_type type)
1384{
1385 char *start = *ccp;
1386 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1387 int ret;
1388
1389 /* Do not allow a scalar (reg+index) to parse as a register. */
1390 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1391 return FAIL;
1392
1393 if (reg && reg->type == type)
1394 return reg->number;
1395
1396 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1397 return ret;
1398
c19d1205
ZW
1399 *ccp = start;
1400 return FAIL;
1401}
69b97547 1402
dcbf9037
JB
1403/* Parse a Neon type specifier. *STR should point at the leading '.'
1404 character. Does no verification at this stage that the type fits the opcode
1405 properly. E.g.,
1406
1407 .i32.i32.s16
1408 .s32.f32
1409 .u16
1410
1411 Can all be legally parsed by this function.
1412
1413 Fills in neon_type struct pointer with parsed information, and updates STR
1414 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1415 type, FAIL if not. */
1416
1417static int
1418parse_neon_type (struct neon_type *type, char **str)
1419{
1420 char *ptr = *str;
1421
1422 if (type)
1423 type->elems = 0;
1424
1425 while (type->elems < NEON_MAX_TYPE_ELS)
1426 {
1427 enum neon_el_type thistype = NT_untyped;
1428 unsigned thissize = -1u;
1429
1430 if (*ptr != '.')
1431 break;
1432
1433 ptr++;
1434
1435 /* Just a size without an explicit type. */
1436 if (ISDIGIT (*ptr))
1437 goto parsesize;
1438
1439 switch (TOLOWER (*ptr))
1440 {
1441 case 'i': thistype = NT_integer; break;
1442 case 'f': thistype = NT_float; break;
1443 case 'p': thistype = NT_poly; break;
1444 case 's': thistype = NT_signed; break;
1445 case 'u': thistype = NT_unsigned; break;
477330fc
RM
1446 case 'd':
1447 thistype = NT_float;
1448 thissize = 64;
1449 ptr++;
1450 goto done;
dcbf9037
JB
1451 default:
1452 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1453 return FAIL;
1454 }
1455
1456 ptr++;
1457
1458 /* .f is an abbreviation for .f32. */
1459 if (thistype == NT_float && !ISDIGIT (*ptr))
1460 thissize = 32;
1461 else
1462 {
1463 parsesize:
1464 thissize = strtoul (ptr, &ptr, 10);
1465
1466 if (thissize != 8 && thissize != 16 && thissize != 32
477330fc
RM
1467 && thissize != 64)
1468 {
1469 as_bad (_("bad size %d in type specifier"), thissize);
dcbf9037
JB
1470 return FAIL;
1471 }
1472 }
1473
037e8744 1474 done:
dcbf9037 1475 if (type)
477330fc
RM
1476 {
1477 type->el[type->elems].type = thistype;
dcbf9037
JB
1478 type->el[type->elems].size = thissize;
1479 type->elems++;
1480 }
1481 }
1482
1483 /* Empty/missing type is not a successful parse. */
1484 if (type->elems == 0)
1485 return FAIL;
1486
1487 *str = ptr;
1488
1489 return SUCCESS;
1490}
1491
1492/* Errors may be set multiple times during parsing or bit encoding
1493 (particularly in the Neon bits), but usually the earliest error which is set
1494 will be the most meaningful. Avoid overwriting it with later (cascading)
1495 errors by calling this function. */
1496
1497static void
1498first_error (const char *err)
1499{
1500 if (!inst.error)
1501 inst.error = err;
1502}
1503
1504/* Parse a single type, e.g. ".s32", leading period included. */
1505static int
1506parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1507{
1508 char *str = *ccp;
1509 struct neon_type optype;
1510
1511 if (*str == '.')
1512 {
1513 if (parse_neon_type (&optype, &str) == SUCCESS)
477330fc
RM
1514 {
1515 if (optype.elems == 1)
1516 *vectype = optype.el[0];
1517 else
1518 {
1519 first_error (_("only one type should be specified for operand"));
1520 return FAIL;
1521 }
1522 }
dcbf9037 1523 else
477330fc
RM
1524 {
1525 first_error (_("vector type expected"));
1526 return FAIL;
1527 }
dcbf9037
JB
1528 }
1529 else
1530 return FAIL;
5f4273c7 1531
dcbf9037 1532 *ccp = str;
5f4273c7 1533
dcbf9037
JB
1534 return SUCCESS;
1535}
1536
1537/* Special meanings for indices (which have a range of 0-7), which will fit into
1538 a 4-bit integer. */
1539
1540#define NEON_ALL_LANES 15
1541#define NEON_INTERLEAVE_LANES 14
1542
5ee91343
AV
1543/* Record a use of the given feature. */
1544static void
1545record_feature_use (const arm_feature_set *feature)
1546{
1547 if (thumb_mode)
1548 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
1549 else
1550 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
1551}
1552
1553/* If the given feature available in the selected CPU, mark it as used.
1554 Returns TRUE iff feature is available. */
1555static bfd_boolean
1556mark_feature_used (const arm_feature_set *feature)
1557{
886e1c73
AV
1558
1559 /* Do not support the use of MVE only instructions when in auto-detection or
1560 -march=all. */
1561 if (((feature == &mve_ext) || (feature == &mve_fp_ext))
1562 && ARM_CPU_IS_ANY (cpu_variant))
1563 {
1564 first_error (BAD_MVE_AUTO);
1565 return FALSE;
1566 }
5ee91343
AV
1567 /* Ensure the option is valid on the current architecture. */
1568 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
1569 return FALSE;
1570
1571 /* Add the appropriate architecture feature for the barrier option used.
1572 */
1573 record_feature_use (feature);
1574
1575 return TRUE;
1576}
1577
dcbf9037
JB
1578/* Parse either a register or a scalar, with an optional type. Return the
1579 register number, and optionally fill in the actual type of the register
1580 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1581 type/index information in *TYPEINFO. */
1582
1583static int
1584parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
477330fc
RM
1585 enum arm_reg_type *rtype,
1586 struct neon_typed_alias *typeinfo)
dcbf9037
JB
1587{
1588 char *str = *ccp;
1589 struct reg_entry *reg = arm_reg_parse_multi (&str);
1590 struct neon_typed_alias atype;
1591 struct neon_type_el parsetype;
1592
1593 atype.defined = 0;
1594 atype.index = -1;
1595 atype.eltype.type = NT_invtype;
1596 atype.eltype.size = -1;
1597
1598 /* Try alternate syntax for some types of register. Note these are mutually
1599 exclusive with the Neon syntax extensions. */
1600 if (reg == NULL)
1601 {
1602 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1603 if (altreg != FAIL)
477330fc 1604 *ccp = str;
dcbf9037 1605 if (typeinfo)
477330fc 1606 *typeinfo = atype;
dcbf9037
JB
1607 return altreg;
1608 }
1609
037e8744
JB
1610 /* Undo polymorphism when a set of register types may be accepted. */
1611 if ((type == REG_TYPE_NDQ
1612 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1613 || (type == REG_TYPE_VFSD
477330fc 1614 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
037e8744 1615 || (type == REG_TYPE_NSDQ
477330fc
RM
1616 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1617 || reg->type == REG_TYPE_NQ))
dec41383
JW
1618 || (type == REG_TYPE_NSD
1619 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
f512f76f
NC
1620 || (type == REG_TYPE_MMXWC
1621 && (reg->type == REG_TYPE_MMXWCG)))
21d799b5 1622 type = (enum arm_reg_type) reg->type;
dcbf9037 1623
5ee91343
AV
1624 if (type == REG_TYPE_MQ)
1625 {
1626 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
1627 return FAIL;
1628
1629 if (!reg || reg->type != REG_TYPE_NQ)
1630 return FAIL;
1631
1632 if (reg->number > 14 && !mark_feature_used (&fpu_vfp_ext_d32))
1633 {
1634 first_error (_("expected MVE register [q0..q7]"));
1635 return FAIL;
1636 }
1637 type = REG_TYPE_NQ;
1638 }
1639 else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
1640 && (type == REG_TYPE_NQ))
1641 return FAIL;
1642
1643
dcbf9037
JB
1644 if (type != reg->type)
1645 return FAIL;
1646
1647 if (reg->neon)
1648 atype = *reg->neon;
5f4273c7 1649
dcbf9037
JB
1650 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1651 {
1652 if ((atype.defined & NTA_HASTYPE) != 0)
477330fc
RM
1653 {
1654 first_error (_("can't redefine type for operand"));
1655 return FAIL;
1656 }
dcbf9037
JB
1657 atype.defined |= NTA_HASTYPE;
1658 atype.eltype = parsetype;
1659 }
5f4273c7 1660
dcbf9037
JB
1661 if (skip_past_char (&str, '[') == SUCCESS)
1662 {
dec41383
JW
1663 if (type != REG_TYPE_VFD
1664 && !(type == REG_TYPE_VFS
57785aa2
AV
1665 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_2))
1666 && !(type == REG_TYPE_NQ
1667 && ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)))
477330fc 1668 {
57785aa2
AV
1669 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
1670 first_error (_("only D and Q registers may be indexed"));
1671 else
1672 first_error (_("only D registers may be indexed"));
477330fc
RM
1673 return FAIL;
1674 }
5f4273c7 1675
dcbf9037 1676 if ((atype.defined & NTA_HASINDEX) != 0)
477330fc
RM
1677 {
1678 first_error (_("can't change index for operand"));
1679 return FAIL;
1680 }
dcbf9037
JB
1681
1682 atype.defined |= NTA_HASINDEX;
1683
1684 if (skip_past_char (&str, ']') == SUCCESS)
477330fc 1685 atype.index = NEON_ALL_LANES;
dcbf9037 1686 else
477330fc
RM
1687 {
1688 expressionS exp;
dcbf9037 1689
477330fc 1690 my_get_expression (&exp, &str, GE_NO_PREFIX);
dcbf9037 1691
477330fc
RM
1692 if (exp.X_op != O_constant)
1693 {
1694 first_error (_("constant expression required"));
1695 return FAIL;
1696 }
dcbf9037 1697
477330fc
RM
1698 if (skip_past_char (&str, ']') == FAIL)
1699 return FAIL;
dcbf9037 1700
477330fc
RM
1701 atype.index = exp.X_add_number;
1702 }
dcbf9037 1703 }
5f4273c7 1704
dcbf9037
JB
1705 if (typeinfo)
1706 *typeinfo = atype;
5f4273c7 1707
dcbf9037
JB
1708 if (rtype)
1709 *rtype = type;
5f4273c7 1710
dcbf9037 1711 *ccp = str;
5f4273c7 1712
dcbf9037
JB
1713 return reg->number;
1714}
1715
efd6b359 1716/* Like arm_reg_parse, but also allow the following extra features:
dcbf9037
JB
1717 - If RTYPE is non-zero, return the (possibly restricted) type of the
1718 register (e.g. Neon double or quad reg when either has been requested).
1719 - If this is a Neon vector type with additional type information, fill
1720 in the struct pointed to by VECTYPE (if non-NULL).
5f4273c7 1721 This function will fault on encountering a scalar. */
dcbf9037
JB
1722
1723static int
1724arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
477330fc 1725 enum arm_reg_type *rtype, struct neon_type_el *vectype)
dcbf9037
JB
1726{
1727 struct neon_typed_alias atype;
1728 char *str = *ccp;
1729 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1730
1731 if (reg == FAIL)
1732 return FAIL;
1733
0855e32b
NS
1734 /* Do not allow regname(... to parse as a register. */
1735 if (*str == '(')
1736 return FAIL;
1737
dcbf9037
JB
1738 /* Do not allow a scalar (reg+index) to parse as a register. */
1739 if ((atype.defined & NTA_HASINDEX) != 0)
1740 {
1741 first_error (_("register operand expected, but got scalar"));
1742 return FAIL;
1743 }
1744
1745 if (vectype)
1746 *vectype = atype.eltype;
1747
1748 *ccp = str;
1749
1750 return reg;
1751}
1752
1753#define NEON_SCALAR_REG(X) ((X) >> 4)
1754#define NEON_SCALAR_INDEX(X) ((X) & 15)
1755
5287ad62
JB
1756/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1757 have enough information to be able to do a good job bounds-checking. So, we
1758 just do easy checks here, and do further checks later. */
1759
1760static int
57785aa2
AV
1761parse_scalar (char **ccp, int elsize, struct neon_type_el *type, enum
1762 arm_reg_type reg_type)
5287ad62 1763{
dcbf9037 1764 int reg;
5287ad62 1765 char *str = *ccp;
dcbf9037 1766 struct neon_typed_alias atype;
57785aa2 1767 unsigned reg_size;
5f4273c7 1768
dec41383 1769 reg = parse_typed_reg_or_scalar (&str, reg_type, NULL, &atype);
5f4273c7 1770
57785aa2
AV
1771 switch (reg_type)
1772 {
1773 case REG_TYPE_VFS:
1774 reg_size = 32;
1775 break;
1776 case REG_TYPE_VFD:
1777 reg_size = 64;
1778 break;
1779 case REG_TYPE_MQ:
1780 reg_size = 128;
1781 break;
1782 default:
1783 gas_assert (0);
1784 return FAIL;
1785 }
1786
dcbf9037 1787 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
5287ad62 1788 return FAIL;
5f4273c7 1789
57785aa2 1790 if (reg_type != REG_TYPE_MQ && atype.index == NEON_ALL_LANES)
5287ad62 1791 {
dcbf9037 1792 first_error (_("scalar must have an index"));
5287ad62
JB
1793 return FAIL;
1794 }
57785aa2 1795 else if (atype.index >= reg_size / elsize)
5287ad62 1796 {
dcbf9037 1797 first_error (_("scalar index out of range"));
5287ad62
JB
1798 return FAIL;
1799 }
5f4273c7 1800
dcbf9037
JB
1801 if (type)
1802 *type = atype.eltype;
5f4273c7 1803
5287ad62 1804 *ccp = str;
5f4273c7 1805
dcbf9037 1806 return reg * 16 + atype.index;
5287ad62
JB
1807}
1808
4b5a202f
AV
1809/* Types of registers in a list. */
1810
1811enum reg_list_els
1812{
1813 REGLIST_RN,
1814 REGLIST_CLRM,
1815 REGLIST_VFP_S,
efd6b359 1816 REGLIST_VFP_S_VPR,
4b5a202f 1817 REGLIST_VFP_D,
efd6b359 1818 REGLIST_VFP_D_VPR,
4b5a202f
AV
1819 REGLIST_NEON_D
1820};
1821
c19d1205 1822/* Parse an ARM register list. Returns the bitmask, or FAIL. */
e07e6e58 1823
c19d1205 1824static long
4b5a202f 1825parse_reg_list (char ** strp, enum reg_list_els etype)
c19d1205 1826{
4b5a202f
AV
1827 char *str = *strp;
1828 long range = 0;
1829 int another_range;
1830
1831 gas_assert (etype == REGLIST_RN || etype == REGLIST_CLRM);
a737bd4d 1832
c19d1205
ZW
1833 /* We come back here if we get ranges concatenated by '+' or '|'. */
1834 do
6057a28f 1835 {
477330fc
RM
1836 skip_whitespace (str);
1837
c19d1205 1838 another_range = 0;
a737bd4d 1839
c19d1205
ZW
1840 if (*str == '{')
1841 {
1842 int in_range = 0;
1843 int cur_reg = -1;
a737bd4d 1844
c19d1205
ZW
1845 str++;
1846 do
1847 {
1848 int reg;
4b5a202f
AV
1849 const char apsr_str[] = "apsr";
1850 int apsr_str_len = strlen (apsr_str);
6057a28f 1851
4b5a202f
AV
1852 reg = arm_reg_parse (&str, REGLIST_RN);
1853 if (etype == REGLIST_CLRM)
c19d1205 1854 {
4b5a202f
AV
1855 if (reg == REG_SP || reg == REG_PC)
1856 reg = FAIL;
1857 else if (reg == FAIL
1858 && !strncasecmp (str, apsr_str, apsr_str_len)
1859 && !ISALPHA (*(str + apsr_str_len)))
1860 {
1861 reg = 15;
1862 str += apsr_str_len;
1863 }
1864
1865 if (reg == FAIL)
1866 {
1867 first_error (_("r0-r12, lr or APSR expected"));
1868 return FAIL;
1869 }
1870 }
1871 else /* etype == REGLIST_RN. */
1872 {
1873 if (reg == FAIL)
1874 {
1875 first_error (_(reg_expected_msgs[REGLIST_RN]));
1876 return FAIL;
1877 }
c19d1205 1878 }
a737bd4d 1879
c19d1205
ZW
1880 if (in_range)
1881 {
1882 int i;
a737bd4d 1883
c19d1205
ZW
1884 if (reg <= cur_reg)
1885 {
dcbf9037 1886 first_error (_("bad range in register list"));
c19d1205
ZW
1887 return FAIL;
1888 }
40a18ebd 1889
c19d1205
ZW
1890 for (i = cur_reg + 1; i < reg; i++)
1891 {
1892 if (range & (1 << i))
1893 as_tsktsk
1894 (_("Warning: duplicated register (r%d) in register list"),
1895 i);
1896 else
1897 range |= 1 << i;
1898 }
1899 in_range = 0;
1900 }
a737bd4d 1901
c19d1205
ZW
1902 if (range & (1 << reg))
1903 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1904 reg);
1905 else if (reg <= cur_reg)
1906 as_tsktsk (_("Warning: register range not in ascending order"));
a737bd4d 1907
c19d1205
ZW
1908 range |= 1 << reg;
1909 cur_reg = reg;
1910 }
1911 while (skip_past_comma (&str) != FAIL
1912 || (in_range = 1, *str++ == '-'));
1913 str--;
a737bd4d 1914
d996d970 1915 if (skip_past_char (&str, '}') == FAIL)
c19d1205 1916 {
dcbf9037 1917 first_error (_("missing `}'"));
c19d1205
ZW
1918 return FAIL;
1919 }
1920 }
4b5a202f 1921 else if (etype == REGLIST_RN)
c19d1205 1922 {
91d6fa6a 1923 expressionS exp;
40a18ebd 1924
91d6fa6a 1925 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
c19d1205 1926 return FAIL;
40a18ebd 1927
91d6fa6a 1928 if (exp.X_op == O_constant)
c19d1205 1929 {
91d6fa6a
NC
1930 if (exp.X_add_number
1931 != (exp.X_add_number & 0x0000ffff))
c19d1205
ZW
1932 {
1933 inst.error = _("invalid register mask");
1934 return FAIL;
1935 }
a737bd4d 1936
91d6fa6a 1937 if ((range & exp.X_add_number) != 0)
c19d1205 1938 {
91d6fa6a 1939 int regno = range & exp.X_add_number;
a737bd4d 1940
c19d1205
ZW
1941 regno &= -regno;
1942 regno = (1 << regno) - 1;
1943 as_tsktsk
1944 (_("Warning: duplicated register (r%d) in register list"),
1945 regno);
1946 }
a737bd4d 1947
91d6fa6a 1948 range |= exp.X_add_number;
c19d1205
ZW
1949 }
1950 else
1951 {
e2b0ab59 1952 if (inst.relocs[0].type != 0)
c19d1205
ZW
1953 {
1954 inst.error = _("expression too complex");
1955 return FAIL;
1956 }
a737bd4d 1957
e2b0ab59
AV
1958 memcpy (&inst.relocs[0].exp, &exp, sizeof (expressionS));
1959 inst.relocs[0].type = BFD_RELOC_ARM_MULTI;
1960 inst.relocs[0].pc_rel = 0;
c19d1205
ZW
1961 }
1962 }
a737bd4d 1963
c19d1205
ZW
1964 if (*str == '|' || *str == '+')
1965 {
1966 str++;
1967 another_range = 1;
1968 }
a737bd4d 1969 }
c19d1205 1970 while (another_range);
a737bd4d 1971
c19d1205
ZW
1972 *strp = str;
1973 return range;
a737bd4d
NC
1974}
1975
c19d1205
ZW
1976/* Parse a VFP register list. If the string is invalid return FAIL.
1977 Otherwise return the number of registers, and set PBASE to the first
5287ad62
JB
1978 register. Parses registers of type ETYPE.
1979 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1980 - Q registers can be used to specify pairs of D registers
1981 - { } can be omitted from around a singleton register list
477330fc
RM
1982 FIXME: This is not implemented, as it would require backtracking in
1983 some cases, e.g.:
1984 vtbl.8 d3,d4,d5
1985 This could be done (the meaning isn't really ambiguous), but doesn't
1986 fit in well with the current parsing framework.
dcbf9037
JB
1987 - 32 D registers may be used (also true for VFPv3).
1988 FIXME: Types are ignored in these register lists, which is probably a
1989 bug. */
6057a28f 1990
c19d1205 1991static int
efd6b359
AV
1992parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype,
1993 bfd_boolean *partial_match)
6057a28f 1994{
037e8744 1995 char *str = *ccp;
c19d1205
ZW
1996 int base_reg;
1997 int new_base;
21d799b5 1998 enum arm_reg_type regtype = (enum arm_reg_type) 0;
5287ad62 1999 int max_regs = 0;
c19d1205
ZW
2000 int count = 0;
2001 int warned = 0;
2002 unsigned long mask = 0;
a737bd4d 2003 int i;
efd6b359
AV
2004 bfd_boolean vpr_seen = FALSE;
2005 bfd_boolean expect_vpr =
2006 (etype == REGLIST_VFP_S_VPR) || (etype == REGLIST_VFP_D_VPR);
6057a28f 2007
477330fc 2008 if (skip_past_char (&str, '{') == FAIL)
5287ad62
JB
2009 {
2010 inst.error = _("expecting {");
2011 return FAIL;
2012 }
6057a28f 2013
5287ad62 2014 switch (etype)
c19d1205 2015 {
5287ad62 2016 case REGLIST_VFP_S:
efd6b359 2017 case REGLIST_VFP_S_VPR:
c19d1205
ZW
2018 regtype = REG_TYPE_VFS;
2019 max_regs = 32;
5287ad62 2020 break;
5f4273c7 2021
5287ad62 2022 case REGLIST_VFP_D:
efd6b359 2023 case REGLIST_VFP_D_VPR:
5287ad62 2024 regtype = REG_TYPE_VFD;
b7fc2769 2025 break;
5f4273c7 2026
b7fc2769
JB
2027 case REGLIST_NEON_D:
2028 regtype = REG_TYPE_NDQ;
2029 break;
4b5a202f
AV
2030
2031 default:
2032 gas_assert (0);
b7fc2769
JB
2033 }
2034
efd6b359 2035 if (etype != REGLIST_VFP_S && etype != REGLIST_VFP_S_VPR)
b7fc2769 2036 {
b1cc4aeb
PB
2037 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2038 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
477330fc
RM
2039 {
2040 max_regs = 32;
2041 if (thumb_mode)
2042 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
2043 fpu_vfp_ext_d32);
2044 else
2045 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
2046 fpu_vfp_ext_d32);
2047 }
5287ad62 2048 else
477330fc 2049 max_regs = 16;
c19d1205 2050 }
6057a28f 2051
c19d1205 2052 base_reg = max_regs;
efd6b359 2053 *partial_match = FALSE;
a737bd4d 2054
c19d1205
ZW
2055 do
2056 {
5287ad62 2057 int setmask = 1, addregs = 1;
efd6b359
AV
2058 const char vpr_str[] = "vpr";
2059 int vpr_str_len = strlen (vpr_str);
dcbf9037 2060
037e8744 2061 new_base = arm_typed_reg_parse (&str, regtype, &regtype, NULL);
dcbf9037 2062
efd6b359
AV
2063 if (expect_vpr)
2064 {
2065 if (new_base == FAIL
2066 && !strncasecmp (str, vpr_str, vpr_str_len)
2067 && !ISALPHA (*(str + vpr_str_len))
2068 && !vpr_seen)
2069 {
2070 vpr_seen = TRUE;
2071 str += vpr_str_len;
2072 if (count == 0)
2073 base_reg = 0; /* Canonicalize VPR only on d0 with 0 regs. */
2074 }
2075 else if (vpr_seen)
2076 {
2077 first_error (_("VPR expected last"));
2078 return FAIL;
2079 }
2080 else if (new_base == FAIL)
2081 {
2082 if (regtype == REG_TYPE_VFS)
2083 first_error (_("VFP single precision register or VPR "
2084 "expected"));
2085 else /* regtype == REG_TYPE_VFD. */
2086 first_error (_("VFP/Neon double precision register or VPR "
2087 "expected"));
2088 return FAIL;
2089 }
2090 }
2091 else if (new_base == FAIL)
a737bd4d 2092 {
dcbf9037 2093 first_error (_(reg_expected_msgs[regtype]));
c19d1205
ZW
2094 return FAIL;
2095 }
5f4273c7 2096
efd6b359
AV
2097 *partial_match = TRUE;
2098 if (vpr_seen)
2099 continue;
2100
b7fc2769 2101 if (new_base >= max_regs)
477330fc
RM
2102 {
2103 first_error (_("register out of range in list"));
2104 return FAIL;
2105 }
5f4273c7 2106
5287ad62
JB
2107 /* Note: a value of 2 * n is returned for the register Q<n>. */
2108 if (regtype == REG_TYPE_NQ)
477330fc
RM
2109 {
2110 setmask = 3;
2111 addregs = 2;
2112 }
5287ad62 2113
c19d1205
ZW
2114 if (new_base < base_reg)
2115 base_reg = new_base;
a737bd4d 2116
5287ad62 2117 if (mask & (setmask << new_base))
c19d1205 2118 {
dcbf9037 2119 first_error (_("invalid register list"));
c19d1205 2120 return FAIL;
a737bd4d 2121 }
a737bd4d 2122
efd6b359 2123 if ((mask >> new_base) != 0 && ! warned && !vpr_seen)
c19d1205
ZW
2124 {
2125 as_tsktsk (_("register list not in ascending order"));
2126 warned = 1;
2127 }
0bbf2aa4 2128
5287ad62
JB
2129 mask |= setmask << new_base;
2130 count += addregs;
0bbf2aa4 2131
037e8744 2132 if (*str == '-') /* We have the start of a range expression */
c19d1205
ZW
2133 {
2134 int high_range;
0bbf2aa4 2135
037e8744 2136 str++;
0bbf2aa4 2137
037e8744 2138 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
477330fc 2139 == FAIL)
c19d1205
ZW
2140 {
2141 inst.error = gettext (reg_expected_msgs[regtype]);
2142 return FAIL;
2143 }
0bbf2aa4 2144
477330fc
RM
2145 if (high_range >= max_regs)
2146 {
2147 first_error (_("register out of range in list"));
2148 return FAIL;
2149 }
b7fc2769 2150
477330fc
RM
2151 if (regtype == REG_TYPE_NQ)
2152 high_range = high_range + 1;
5287ad62 2153
c19d1205
ZW
2154 if (high_range <= new_base)
2155 {
2156 inst.error = _("register range not in ascending order");
2157 return FAIL;
2158 }
0bbf2aa4 2159
5287ad62 2160 for (new_base += addregs; new_base <= high_range; new_base += addregs)
0bbf2aa4 2161 {
5287ad62 2162 if (mask & (setmask << new_base))
0bbf2aa4 2163 {
c19d1205
ZW
2164 inst.error = _("invalid register list");
2165 return FAIL;
0bbf2aa4 2166 }
c19d1205 2167
5287ad62
JB
2168 mask |= setmask << new_base;
2169 count += addregs;
0bbf2aa4 2170 }
0bbf2aa4 2171 }
0bbf2aa4 2172 }
037e8744 2173 while (skip_past_comma (&str) != FAIL);
0bbf2aa4 2174
037e8744 2175 str++;
0bbf2aa4 2176
c19d1205 2177 /* Sanity check -- should have raised a parse error above. */
efd6b359 2178 if ((!vpr_seen && count == 0) || count > max_regs)
c19d1205
ZW
2179 abort ();
2180
2181 *pbase = base_reg;
2182
efd6b359
AV
2183 if (expect_vpr && !vpr_seen)
2184 {
2185 first_error (_("VPR expected last"));
2186 return FAIL;
2187 }
2188
c19d1205
ZW
2189 /* Final test -- the registers must be consecutive. */
2190 mask >>= base_reg;
2191 for (i = 0; i < count; i++)
2192 {
2193 if ((mask & (1u << i)) == 0)
2194 {
2195 inst.error = _("non-contiguous register range");
2196 return FAIL;
2197 }
2198 }
2199
037e8744
JB
2200 *ccp = str;
2201
c19d1205 2202 return count;
b99bd4ef
NC
2203}
2204
dcbf9037
JB
2205/* True if two alias types are the same. */
2206
c921be7d 2207static bfd_boolean
dcbf9037
JB
2208neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
2209{
2210 if (!a && !b)
c921be7d 2211 return TRUE;
5f4273c7 2212
dcbf9037 2213 if (!a || !b)
c921be7d 2214 return FALSE;
dcbf9037
JB
2215
2216 if (a->defined != b->defined)
c921be7d 2217 return FALSE;
5f4273c7 2218
dcbf9037
JB
2219 if ((a->defined & NTA_HASTYPE) != 0
2220 && (a->eltype.type != b->eltype.type
477330fc 2221 || a->eltype.size != b->eltype.size))
c921be7d 2222 return FALSE;
dcbf9037
JB
2223
2224 if ((a->defined & NTA_HASINDEX) != 0
2225 && (a->index != b->index))
c921be7d 2226 return FALSE;
5f4273c7 2227
c921be7d 2228 return TRUE;
dcbf9037
JB
2229}
2230
5287ad62
JB
2231/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2232 The base register is put in *PBASE.
dcbf9037 2233 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
5287ad62
JB
2234 the return value.
2235 The register stride (minus one) is put in bit 4 of the return value.
dcbf9037
JB
2236 Bits [6:5] encode the list length (minus one).
2237 The type of the list elements is put in *ELTYPE, if non-NULL. */
5287ad62 2238
5287ad62 2239#define NEON_LANE(X) ((X) & 0xf)
dcbf9037 2240#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
5287ad62
JB
2241#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2242
2243static int
dcbf9037 2244parse_neon_el_struct_list (char **str, unsigned *pbase,
35c228db 2245 int mve,
477330fc 2246 struct neon_type_el *eltype)
5287ad62
JB
2247{
2248 char *ptr = *str;
2249 int base_reg = -1;
2250 int reg_incr = -1;
2251 int count = 0;
2252 int lane = -1;
2253 int leading_brace = 0;
2254 enum arm_reg_type rtype = REG_TYPE_NDQ;
35c228db
AV
2255 const char *const incr_error = mve ? _("register stride must be 1") :
2256 _("register stride must be 1 or 2");
20203fb9 2257 const char *const type_error = _("mismatched element/structure types in list");
dcbf9037 2258 struct neon_typed_alias firsttype;
f85d59c3
KT
2259 firsttype.defined = 0;
2260 firsttype.eltype.type = NT_invtype;
2261 firsttype.eltype.size = -1;
2262 firsttype.index = -1;
5f4273c7 2263
5287ad62
JB
2264 if (skip_past_char (&ptr, '{') == SUCCESS)
2265 leading_brace = 1;
5f4273c7 2266
5287ad62
JB
2267 do
2268 {
dcbf9037 2269 struct neon_typed_alias atype;
35c228db
AV
2270 if (mve)
2271 rtype = REG_TYPE_MQ;
dcbf9037
JB
2272 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
2273
5287ad62 2274 if (getreg == FAIL)
477330fc
RM
2275 {
2276 first_error (_(reg_expected_msgs[rtype]));
2277 return FAIL;
2278 }
5f4273c7 2279
5287ad62 2280 if (base_reg == -1)
477330fc
RM
2281 {
2282 base_reg = getreg;
2283 if (rtype == REG_TYPE_NQ)
2284 {
2285 reg_incr = 1;
2286 }
2287 firsttype = atype;
2288 }
5287ad62 2289 else if (reg_incr == -1)
477330fc
RM
2290 {
2291 reg_incr = getreg - base_reg;
2292 if (reg_incr < 1 || reg_incr > 2)
2293 {
2294 first_error (_(incr_error));
2295 return FAIL;
2296 }
2297 }
5287ad62 2298 else if (getreg != base_reg + reg_incr * count)
477330fc
RM
2299 {
2300 first_error (_(incr_error));
2301 return FAIL;
2302 }
dcbf9037 2303
c921be7d 2304 if (! neon_alias_types_same (&atype, &firsttype))
477330fc
RM
2305 {
2306 first_error (_(type_error));
2307 return FAIL;
2308 }
5f4273c7 2309
5287ad62 2310 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
477330fc 2311 modes. */
5287ad62 2312 if (ptr[0] == '-')
477330fc
RM
2313 {
2314 struct neon_typed_alias htype;
2315 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
2316 if (lane == -1)
2317 lane = NEON_INTERLEAVE_LANES;
2318 else if (lane != NEON_INTERLEAVE_LANES)
2319 {
2320 first_error (_(type_error));
2321 return FAIL;
2322 }
2323 if (reg_incr == -1)
2324 reg_incr = 1;
2325 else if (reg_incr != 1)
2326 {
2327 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2328 return FAIL;
2329 }
2330 ptr++;
2331 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2332 if (hireg == FAIL)
2333 {
2334 first_error (_(reg_expected_msgs[rtype]));
2335 return FAIL;
2336 }
2337 if (! neon_alias_types_same (&htype, &firsttype))
2338 {
2339 first_error (_(type_error));
2340 return FAIL;
2341 }
2342 count += hireg + dregs - getreg;
2343 continue;
2344 }
5f4273c7 2345
5287ad62
JB
2346 /* If we're using Q registers, we can't use [] or [n] syntax. */
2347 if (rtype == REG_TYPE_NQ)
477330fc
RM
2348 {
2349 count += 2;
2350 continue;
2351 }
5f4273c7 2352
dcbf9037 2353 if ((atype.defined & NTA_HASINDEX) != 0)
477330fc
RM
2354 {
2355 if (lane == -1)
2356 lane = atype.index;
2357 else if (lane != atype.index)
2358 {
2359 first_error (_(type_error));
2360 return FAIL;
2361 }
2362 }
5287ad62 2363 else if (lane == -1)
477330fc 2364 lane = NEON_INTERLEAVE_LANES;
5287ad62 2365 else if (lane != NEON_INTERLEAVE_LANES)
477330fc
RM
2366 {
2367 first_error (_(type_error));
2368 return FAIL;
2369 }
5287ad62
JB
2370 count++;
2371 }
2372 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
5f4273c7 2373
5287ad62
JB
2374 /* No lane set by [x]. We must be interleaving structures. */
2375 if (lane == -1)
2376 lane = NEON_INTERLEAVE_LANES;
5f4273c7 2377
5287ad62 2378 /* Sanity check. */
35c228db 2379 if (lane == -1 || base_reg == -1 || count < 1 || (!mve && count > 4)
5287ad62
JB
2380 || (count > 1 && reg_incr == -1))
2381 {
dcbf9037 2382 first_error (_("error parsing element/structure list"));
5287ad62
JB
2383 return FAIL;
2384 }
2385
2386 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2387 {
dcbf9037 2388 first_error (_("expected }"));
5287ad62
JB
2389 return FAIL;
2390 }
5f4273c7 2391
5287ad62
JB
2392 if (reg_incr == -1)
2393 reg_incr = 1;
2394
dcbf9037
JB
2395 if (eltype)
2396 *eltype = firsttype.eltype;
2397
5287ad62
JB
2398 *pbase = base_reg;
2399 *str = ptr;
5f4273c7 2400
5287ad62
JB
2401 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2402}
2403
c19d1205
ZW
2404/* Parse an explicit relocation suffix on an expression. This is
2405 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2406 arm_reloc_hsh contains no entries, so this function can only
2407 succeed if there is no () after the word. Returns -1 on error,
2408 BFD_RELOC_UNUSED if there wasn't any suffix. */
3da1d841 2409
c19d1205
ZW
2410static int
2411parse_reloc (char **str)
b99bd4ef 2412{
c19d1205
ZW
2413 struct reloc_entry *r;
2414 char *p, *q;
b99bd4ef 2415
c19d1205
ZW
2416 if (**str != '(')
2417 return BFD_RELOC_UNUSED;
b99bd4ef 2418
c19d1205
ZW
2419 p = *str + 1;
2420 q = p;
2421
2422 while (*q && *q != ')' && *q != ',')
2423 q++;
2424 if (*q != ')')
2425 return -1;
2426
21d799b5
NC
2427 if ((r = (struct reloc_entry *)
2428 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
c19d1205
ZW
2429 return -1;
2430
2431 *str = q + 1;
2432 return r->reloc;
b99bd4ef
NC
2433}
2434
c19d1205
ZW
2435/* Directives: register aliases. */
2436
dcbf9037 2437static struct reg_entry *
90ec0d68 2438insert_reg_alias (char *str, unsigned number, int type)
b99bd4ef 2439{
d3ce72d0 2440 struct reg_entry *new_reg;
c19d1205 2441 const char *name;
b99bd4ef 2442
d3ce72d0 2443 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
c19d1205 2444 {
d3ce72d0 2445 if (new_reg->builtin)
c19d1205 2446 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
b99bd4ef 2447
c19d1205
ZW
2448 /* Only warn about a redefinition if it's not defined as the
2449 same register. */
d3ce72d0 2450 else if (new_reg->number != number || new_reg->type != type)
c19d1205 2451 as_warn (_("ignoring redefinition of register alias '%s'"), str);
69b97547 2452
d929913e 2453 return NULL;
c19d1205 2454 }
b99bd4ef 2455
c19d1205 2456 name = xstrdup (str);
325801bd 2457 new_reg = XNEW (struct reg_entry);
b99bd4ef 2458
d3ce72d0
NC
2459 new_reg->name = name;
2460 new_reg->number = number;
2461 new_reg->type = type;
2462 new_reg->builtin = FALSE;
2463 new_reg->neon = NULL;
b99bd4ef 2464
d3ce72d0 2465 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
c19d1205 2466 abort ();
5f4273c7 2467
d3ce72d0 2468 return new_reg;
dcbf9037
JB
2469}
2470
2471static void
2472insert_neon_reg_alias (char *str, int number, int type,
477330fc 2473 struct neon_typed_alias *atype)
dcbf9037
JB
2474{
2475 struct reg_entry *reg = insert_reg_alias (str, number, type);
5f4273c7 2476
dcbf9037
JB
2477 if (!reg)
2478 {
2479 first_error (_("attempt to redefine typed alias"));
2480 return;
2481 }
5f4273c7 2482
dcbf9037
JB
2483 if (atype)
2484 {
325801bd 2485 reg->neon = XNEW (struct neon_typed_alias);
dcbf9037
JB
2486 *reg->neon = *atype;
2487 }
c19d1205 2488}
b99bd4ef 2489
c19d1205 2490/* Look for the .req directive. This is of the form:
b99bd4ef 2491
c19d1205 2492 new_register_name .req existing_register_name
b99bd4ef 2493
c19d1205 2494 If we find one, or if it looks sufficiently like one that we want to
d929913e 2495 handle any error here, return TRUE. Otherwise return FALSE. */
b99bd4ef 2496
d929913e 2497static bfd_boolean
c19d1205
ZW
2498create_register_alias (char * newname, char *p)
2499{
2500 struct reg_entry *old;
2501 char *oldname, *nbuf;
2502 size_t nlen;
b99bd4ef 2503
c19d1205
ZW
2504 /* The input scrubber ensures that whitespace after the mnemonic is
2505 collapsed to single spaces. */
2506 oldname = p;
2507 if (strncmp (oldname, " .req ", 6) != 0)
d929913e 2508 return FALSE;
b99bd4ef 2509
c19d1205
ZW
2510 oldname += 6;
2511 if (*oldname == '\0')
d929913e 2512 return FALSE;
b99bd4ef 2513
21d799b5 2514 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
c19d1205 2515 if (!old)
b99bd4ef 2516 {
c19d1205 2517 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
d929913e 2518 return TRUE;
b99bd4ef
NC
2519 }
2520
c19d1205
ZW
2521 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2522 the desired alias name, and p points to its end. If not, then
2523 the desired alias name is in the global original_case_string. */
2524#ifdef TC_CASE_SENSITIVE
2525 nlen = p - newname;
2526#else
2527 newname = original_case_string;
2528 nlen = strlen (newname);
2529#endif
b99bd4ef 2530
29a2809e 2531 nbuf = xmemdup0 (newname, nlen);
b99bd4ef 2532
c19d1205
ZW
2533 /* Create aliases under the new name as stated; an all-lowercase
2534 version of the new name; and an all-uppercase version of the new
2535 name. */
d929913e
NC
2536 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2537 {
2538 for (p = nbuf; *p; p++)
2539 *p = TOUPPER (*p);
c19d1205 2540
d929913e
NC
2541 if (strncmp (nbuf, newname, nlen))
2542 {
2543 /* If this attempt to create an additional alias fails, do not bother
2544 trying to create the all-lower case alias. We will fail and issue
2545 a second, duplicate error message. This situation arises when the
2546 programmer does something like:
2547 foo .req r0
2548 Foo .req r1
2549 The second .req creates the "Foo" alias but then fails to create
5f4273c7 2550 the artificial FOO alias because it has already been created by the
d929913e
NC
2551 first .req. */
2552 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
e1fa0163
NC
2553 {
2554 free (nbuf);
2555 return TRUE;
2556 }
d929913e 2557 }
c19d1205 2558
d929913e
NC
2559 for (p = nbuf; *p; p++)
2560 *p = TOLOWER (*p);
c19d1205 2561
d929913e
NC
2562 if (strncmp (nbuf, newname, nlen))
2563 insert_reg_alias (nbuf, old->number, old->type);
2564 }
c19d1205 2565
e1fa0163 2566 free (nbuf);
d929913e 2567 return TRUE;
b99bd4ef
NC
2568}
2569
dcbf9037
JB
2570/* Create a Neon typed/indexed register alias using directives, e.g.:
2571 X .dn d5.s32[1]
2572 Y .qn 6.s16
2573 Z .dn d7
2574 T .dn Z[0]
2575 These typed registers can be used instead of the types specified after the
2576 Neon mnemonic, so long as all operands given have types. Types can also be
2577 specified directly, e.g.:
5f4273c7 2578 vadd d0.s32, d1.s32, d2.s32 */
dcbf9037 2579
c921be7d 2580static bfd_boolean
dcbf9037
JB
2581create_neon_reg_alias (char *newname, char *p)
2582{
2583 enum arm_reg_type basetype;
2584 struct reg_entry *basereg;
2585 struct reg_entry mybasereg;
2586 struct neon_type ntype;
2587 struct neon_typed_alias typeinfo;
12d6b0b7 2588 char *namebuf, *nameend ATTRIBUTE_UNUSED;
dcbf9037 2589 int namelen;
5f4273c7 2590
dcbf9037
JB
2591 typeinfo.defined = 0;
2592 typeinfo.eltype.type = NT_invtype;
2593 typeinfo.eltype.size = -1;
2594 typeinfo.index = -1;
5f4273c7 2595
dcbf9037 2596 nameend = p;
5f4273c7 2597
dcbf9037
JB
2598 if (strncmp (p, " .dn ", 5) == 0)
2599 basetype = REG_TYPE_VFD;
2600 else if (strncmp (p, " .qn ", 5) == 0)
2601 basetype = REG_TYPE_NQ;
2602 else
c921be7d 2603 return FALSE;
5f4273c7 2604
dcbf9037 2605 p += 5;
5f4273c7 2606
dcbf9037 2607 if (*p == '\0')
c921be7d 2608 return FALSE;
5f4273c7 2609
dcbf9037
JB
2610 basereg = arm_reg_parse_multi (&p);
2611
2612 if (basereg && basereg->type != basetype)
2613 {
2614 as_bad (_("bad type for register"));
c921be7d 2615 return FALSE;
dcbf9037
JB
2616 }
2617
2618 if (basereg == NULL)
2619 {
2620 expressionS exp;
2621 /* Try parsing as an integer. */
2622 my_get_expression (&exp, &p, GE_NO_PREFIX);
2623 if (exp.X_op != O_constant)
477330fc
RM
2624 {
2625 as_bad (_("expression must be constant"));
2626 return FALSE;
2627 }
dcbf9037
JB
2628 basereg = &mybasereg;
2629 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
477330fc 2630 : exp.X_add_number;
dcbf9037
JB
2631 basereg->neon = 0;
2632 }
2633
2634 if (basereg->neon)
2635 typeinfo = *basereg->neon;
2636
2637 if (parse_neon_type (&ntype, &p) == SUCCESS)
2638 {
2639 /* We got a type. */
2640 if (typeinfo.defined & NTA_HASTYPE)
477330fc
RM
2641 {
2642 as_bad (_("can't redefine the type of a register alias"));
2643 return FALSE;
2644 }
5f4273c7 2645
dcbf9037
JB
2646 typeinfo.defined |= NTA_HASTYPE;
2647 if (ntype.elems != 1)
477330fc
RM
2648 {
2649 as_bad (_("you must specify a single type only"));
2650 return FALSE;
2651 }
dcbf9037
JB
2652 typeinfo.eltype = ntype.el[0];
2653 }
5f4273c7 2654
dcbf9037
JB
2655 if (skip_past_char (&p, '[') == SUCCESS)
2656 {
2657 expressionS exp;
2658 /* We got a scalar index. */
5f4273c7 2659
dcbf9037 2660 if (typeinfo.defined & NTA_HASINDEX)
477330fc
RM
2661 {
2662 as_bad (_("can't redefine the index of a scalar alias"));
2663 return FALSE;
2664 }
5f4273c7 2665
dcbf9037 2666 my_get_expression (&exp, &p, GE_NO_PREFIX);
5f4273c7 2667
dcbf9037 2668 if (exp.X_op != O_constant)
477330fc
RM
2669 {
2670 as_bad (_("scalar index must be constant"));
2671 return FALSE;
2672 }
5f4273c7 2673
dcbf9037
JB
2674 typeinfo.defined |= NTA_HASINDEX;
2675 typeinfo.index = exp.X_add_number;
5f4273c7 2676
dcbf9037 2677 if (skip_past_char (&p, ']') == FAIL)
477330fc
RM
2678 {
2679 as_bad (_("expecting ]"));
2680 return FALSE;
2681 }
dcbf9037
JB
2682 }
2683
15735687
NS
2684 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2685 the desired alias name, and p points to its end. If not, then
2686 the desired alias name is in the global original_case_string. */
2687#ifdef TC_CASE_SENSITIVE
dcbf9037 2688 namelen = nameend - newname;
15735687
NS
2689#else
2690 newname = original_case_string;
2691 namelen = strlen (newname);
2692#endif
2693
29a2809e 2694 namebuf = xmemdup0 (newname, namelen);
5f4273c7 2695
dcbf9037 2696 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2697 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2698
dcbf9037
JB
2699 /* Insert name in all uppercase. */
2700 for (p = namebuf; *p; p++)
2701 *p = TOUPPER (*p);
5f4273c7 2702
dcbf9037
JB
2703 if (strncmp (namebuf, newname, namelen))
2704 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2705 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2706
dcbf9037
JB
2707 /* Insert name in all lowercase. */
2708 for (p = namebuf; *p; p++)
2709 *p = TOLOWER (*p);
5f4273c7 2710
dcbf9037
JB
2711 if (strncmp (namebuf, newname, namelen))
2712 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2713 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2714
e1fa0163 2715 free (namebuf);
c921be7d 2716 return TRUE;
dcbf9037
JB
2717}
2718
c19d1205
ZW
2719/* Should never be called, as .req goes between the alias and the
2720 register name, not at the beginning of the line. */
c921be7d 2721
b99bd4ef 2722static void
c19d1205 2723s_req (int a ATTRIBUTE_UNUSED)
b99bd4ef 2724{
c19d1205
ZW
2725 as_bad (_("invalid syntax for .req directive"));
2726}
b99bd4ef 2727
dcbf9037
JB
2728static void
2729s_dn (int a ATTRIBUTE_UNUSED)
2730{
2731 as_bad (_("invalid syntax for .dn directive"));
2732}
2733
2734static void
2735s_qn (int a ATTRIBUTE_UNUSED)
2736{
2737 as_bad (_("invalid syntax for .qn directive"));
2738}
2739
c19d1205
ZW
2740/* The .unreq directive deletes an alias which was previously defined
2741 by .req. For example:
b99bd4ef 2742
c19d1205
ZW
2743 my_alias .req r11
2744 .unreq my_alias */
b99bd4ef
NC
2745
2746static void
c19d1205 2747s_unreq (int a ATTRIBUTE_UNUSED)
b99bd4ef 2748{
c19d1205
ZW
2749 char * name;
2750 char saved_char;
b99bd4ef 2751
c19d1205
ZW
2752 name = input_line_pointer;
2753
2754 while (*input_line_pointer != 0
2755 && *input_line_pointer != ' '
2756 && *input_line_pointer != '\n')
2757 ++input_line_pointer;
2758
2759 saved_char = *input_line_pointer;
2760 *input_line_pointer = 0;
2761
2762 if (!*name)
2763 as_bad (_("invalid syntax for .unreq directive"));
2764 else
2765 {
21d799b5 2766 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
477330fc 2767 name);
c19d1205
ZW
2768
2769 if (!reg)
2770 as_bad (_("unknown register alias '%s'"), name);
2771 else if (reg->builtin)
a1727c1a 2772 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
c19d1205
ZW
2773 name);
2774 else
2775 {
d929913e
NC
2776 char * p;
2777 char * nbuf;
2778
db0bc284 2779 hash_delete (arm_reg_hsh, name, FALSE);
c19d1205 2780 free ((char *) reg->name);
477330fc
RM
2781 if (reg->neon)
2782 free (reg->neon);
c19d1205 2783 free (reg);
d929913e
NC
2784
2785 /* Also locate the all upper case and all lower case versions.
2786 Do not complain if we cannot find one or the other as it
2787 was probably deleted above. */
5f4273c7 2788
d929913e
NC
2789 nbuf = strdup (name);
2790 for (p = nbuf; *p; p++)
2791 *p = TOUPPER (*p);
21d799b5 2792 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
d929913e
NC
2793 if (reg)
2794 {
db0bc284 2795 hash_delete (arm_reg_hsh, nbuf, FALSE);
d929913e
NC
2796 free ((char *) reg->name);
2797 if (reg->neon)
2798 free (reg->neon);
2799 free (reg);
2800 }
2801
2802 for (p = nbuf; *p; p++)
2803 *p = TOLOWER (*p);
21d799b5 2804 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
d929913e
NC
2805 if (reg)
2806 {
db0bc284 2807 hash_delete (arm_reg_hsh, nbuf, FALSE);
d929913e
NC
2808 free ((char *) reg->name);
2809 if (reg->neon)
2810 free (reg->neon);
2811 free (reg);
2812 }
2813
2814 free (nbuf);
c19d1205
ZW
2815 }
2816 }
b99bd4ef 2817
c19d1205 2818 *input_line_pointer = saved_char;
b99bd4ef
NC
2819 demand_empty_rest_of_line ();
2820}
2821
c19d1205
ZW
2822/* Directives: Instruction set selection. */
2823
2824#ifdef OBJ_ELF
2825/* This code is to handle mapping symbols as defined in the ARM ELF spec.
2826 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2827 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2828 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2829
cd000bff
DJ
2830/* Create a new mapping symbol for the transition to STATE. */
2831
2832static void
2833make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
b99bd4ef 2834{
a737bd4d 2835 symbolS * symbolP;
c19d1205
ZW
2836 const char * symname;
2837 int type;
b99bd4ef 2838
c19d1205 2839 switch (state)
b99bd4ef 2840 {
c19d1205
ZW
2841 case MAP_DATA:
2842 symname = "$d";
2843 type = BSF_NO_FLAGS;
2844 break;
2845 case MAP_ARM:
2846 symname = "$a";
2847 type = BSF_NO_FLAGS;
2848 break;
2849 case MAP_THUMB:
2850 symname = "$t";
2851 type = BSF_NO_FLAGS;
2852 break;
c19d1205
ZW
2853 default:
2854 abort ();
2855 }
2856
cd000bff 2857 symbolP = symbol_new (symname, now_seg, value, frag);
c19d1205
ZW
2858 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2859
2860 switch (state)
2861 {
2862 case MAP_ARM:
2863 THUMB_SET_FUNC (symbolP, 0);
2864 ARM_SET_THUMB (symbolP, 0);
2865 ARM_SET_INTERWORK (symbolP, support_interwork);
2866 break;
2867
2868 case MAP_THUMB:
2869 THUMB_SET_FUNC (symbolP, 1);
2870 ARM_SET_THUMB (symbolP, 1);
2871 ARM_SET_INTERWORK (symbolP, support_interwork);
2872 break;
2873
2874 case MAP_DATA:
2875 default:
cd000bff
DJ
2876 break;
2877 }
2878
2879 /* Save the mapping symbols for future reference. Also check that
2880 we do not place two mapping symbols at the same offset within a
2881 frag. We'll handle overlap between frags in
2de7820f
JZ
2882 check_mapping_symbols.
2883
2884 If .fill or other data filling directive generates zero sized data,
2885 the mapping symbol for the following code will have the same value
2886 as the one generated for the data filling directive. In this case,
2887 we replace the old symbol with the new one at the same address. */
cd000bff
DJ
2888 if (value == 0)
2889 {
2de7820f
JZ
2890 if (frag->tc_frag_data.first_map != NULL)
2891 {
2892 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2893 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2894 }
cd000bff
DJ
2895 frag->tc_frag_data.first_map = symbolP;
2896 }
2897 if (frag->tc_frag_data.last_map != NULL)
0f020cef
JZ
2898 {
2899 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
0f020cef
JZ
2900 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2901 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2902 }
cd000bff
DJ
2903 frag->tc_frag_data.last_map = symbolP;
2904}
2905
2906/* We must sometimes convert a region marked as code to data during
2907 code alignment, if an odd number of bytes have to be padded. The
2908 code mapping symbol is pushed to an aligned address. */
2909
2910static void
2911insert_data_mapping_symbol (enum mstate state,
2912 valueT value, fragS *frag, offsetT bytes)
2913{
2914 /* If there was already a mapping symbol, remove it. */
2915 if (frag->tc_frag_data.last_map != NULL
2916 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2917 {
2918 symbolS *symp = frag->tc_frag_data.last_map;
2919
2920 if (value == 0)
2921 {
2922 know (frag->tc_frag_data.first_map == symp);
2923 frag->tc_frag_data.first_map = NULL;
2924 }
2925 frag->tc_frag_data.last_map = NULL;
2926 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
c19d1205 2927 }
cd000bff
DJ
2928
2929 make_mapping_symbol (MAP_DATA, value, frag);
2930 make_mapping_symbol (state, value + bytes, frag);
2931}
2932
2933static void mapping_state_2 (enum mstate state, int max_chars);
2934
2935/* Set the mapping state to STATE. Only call this when about to
2936 emit some STATE bytes to the file. */
2937
4e9aaefb 2938#define TRANSITION(from, to) (mapstate == (from) && state == (to))
cd000bff
DJ
2939void
2940mapping_state (enum mstate state)
2941{
940b5ce0
DJ
2942 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2943
cd000bff
DJ
2944 if (mapstate == state)
2945 /* The mapping symbol has already been emitted.
2946 There is nothing else to do. */
2947 return;
49c62a33
NC
2948
2949 if (state == MAP_ARM || state == MAP_THUMB)
2950 /* PR gas/12931
2951 All ARM instructions require 4-byte alignment.
2952 (Almost) all Thumb instructions require 2-byte alignment.
2953
2954 When emitting instructions into any section, mark the section
2955 appropriately.
2956
2957 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2958 but themselves require 2-byte alignment; this applies to some
33eaf5de 2959 PC- relative forms. However, these cases will involve implicit
49c62a33
NC
2960 literal pool generation or an explicit .align >=2, both of
2961 which will cause the section to me marked with sufficient
2962 alignment. Thus, we don't handle those cases here. */
2963 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2964
2965 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
4e9aaefb 2966 /* This case will be evaluated later. */
cd000bff 2967 return;
cd000bff
DJ
2968
2969 mapping_state_2 (state, 0);
cd000bff
DJ
2970}
2971
2972/* Same as mapping_state, but MAX_CHARS bytes have already been
2973 allocated. Put the mapping symbol that far back. */
2974
2975static void
2976mapping_state_2 (enum mstate state, int max_chars)
2977{
940b5ce0
DJ
2978 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2979
2980 if (!SEG_NORMAL (now_seg))
2981 return;
2982
cd000bff
DJ
2983 if (mapstate == state)
2984 /* The mapping symbol has already been emitted.
2985 There is nothing else to do. */
2986 return;
2987
4e9aaefb
SA
2988 if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2989 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2990 {
2991 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2992 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2993
2994 if (add_symbol)
2995 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2996 }
2997
cd000bff
DJ
2998 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2999 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
c19d1205 3000}
4e9aaefb 3001#undef TRANSITION
c19d1205 3002#else
d3106081
NS
3003#define mapping_state(x) ((void)0)
3004#define mapping_state_2(x, y) ((void)0)
c19d1205
ZW
3005#endif
3006
3007/* Find the real, Thumb encoded start of a Thumb function. */
3008
4343666d 3009#ifdef OBJ_COFF
c19d1205
ZW
3010static symbolS *
3011find_real_start (symbolS * symbolP)
3012{
3013 char * real_start;
3014 const char * name = S_GET_NAME (symbolP);
3015 symbolS * new_target;
3016
3017 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3018#define STUB_NAME ".real_start_of"
3019
3020 if (name == NULL)
3021 abort ();
3022
37f6032b
ZW
3023 /* The compiler may generate BL instructions to local labels because
3024 it needs to perform a branch to a far away location. These labels
3025 do not have a corresponding ".real_start_of" label. We check
3026 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3027 the ".real_start_of" convention for nonlocal branches. */
3028 if (S_IS_LOCAL (symbolP) || name[0] == '.')
c19d1205
ZW
3029 return symbolP;
3030
e1fa0163 3031 real_start = concat (STUB_NAME, name, NULL);
c19d1205 3032 new_target = symbol_find (real_start);
e1fa0163 3033 free (real_start);
c19d1205
ZW
3034
3035 if (new_target == NULL)
3036 {
bd3ba5d1 3037 as_warn (_("Failed to find real start of function: %s\n"), name);
c19d1205
ZW
3038 new_target = symbolP;
3039 }
3040
c19d1205
ZW
3041 return new_target;
3042}
4343666d 3043#endif
c19d1205
ZW
3044
3045static void
3046opcode_select (int width)
3047{
3048 switch (width)
3049 {
3050 case 16:
3051 if (! thumb_mode)
3052 {
e74cfd16 3053 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
c19d1205
ZW
3054 as_bad (_("selected processor does not support THUMB opcodes"));
3055
3056 thumb_mode = 1;
3057 /* No need to force the alignment, since we will have been
3058 coming from ARM mode, which is word-aligned. */
3059 record_alignment (now_seg, 1);
3060 }
c19d1205
ZW
3061 break;
3062
3063 case 32:
3064 if (thumb_mode)
3065 {
e74cfd16 3066 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
c19d1205
ZW
3067 as_bad (_("selected processor does not support ARM opcodes"));
3068
3069 thumb_mode = 0;
3070
3071 if (!need_pass_2)
3072 frag_align (2, 0, 0);
3073
3074 record_alignment (now_seg, 1);
3075 }
c19d1205
ZW
3076 break;
3077
3078 default:
3079 as_bad (_("invalid instruction size selected (%d)"), width);
3080 }
3081}
3082
3083static void
3084s_arm (int ignore ATTRIBUTE_UNUSED)
3085{
3086 opcode_select (32);
3087 demand_empty_rest_of_line ();
3088}
3089
3090static void
3091s_thumb (int ignore ATTRIBUTE_UNUSED)
3092{
3093 opcode_select (16);
3094 demand_empty_rest_of_line ();
3095}
3096
3097static void
3098s_code (int unused ATTRIBUTE_UNUSED)
3099{
3100 int temp;
3101
3102 temp = get_absolute_expression ();
3103 switch (temp)
3104 {
3105 case 16:
3106 case 32:
3107 opcode_select (temp);
3108 break;
3109
3110 default:
3111 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
3112 }
3113}
3114
3115static void
3116s_force_thumb (int ignore ATTRIBUTE_UNUSED)
3117{
3118 /* If we are not already in thumb mode go into it, EVEN if
3119 the target processor does not support thumb instructions.
3120 This is used by gcc/config/arm/lib1funcs.asm for example
3121 to compile interworking support functions even if the
3122 target processor should not support interworking. */
3123 if (! thumb_mode)
3124 {
3125 thumb_mode = 2;
3126 record_alignment (now_seg, 1);
3127 }
3128
3129 demand_empty_rest_of_line ();
3130}
3131
3132static void
3133s_thumb_func (int ignore ATTRIBUTE_UNUSED)
3134{
3135 s_thumb (0);
3136
3137 /* The following label is the name/address of the start of a Thumb function.
3138 We need to know this for the interworking support. */
3139 label_is_thumb_function_name = TRUE;
3140}
3141
3142/* Perform a .set directive, but also mark the alias as
3143 being a thumb function. */
3144
3145static void
3146s_thumb_set (int equiv)
3147{
3148 /* XXX the following is a duplicate of the code for s_set() in read.c
3149 We cannot just call that code as we need to get at the symbol that
3150 is created. */
3151 char * name;
3152 char delim;
3153 char * end_name;
3154 symbolS * symbolP;
3155
3156 /* Especial apologies for the random logic:
3157 This just grew, and could be parsed much more simply!
3158 Dean - in haste. */
d02603dc 3159 delim = get_symbol_name (& name);
c19d1205 3160 end_name = input_line_pointer;
d02603dc 3161 (void) restore_line_pointer (delim);
c19d1205
ZW
3162
3163 if (*input_line_pointer != ',')
3164 {
3165 *end_name = 0;
3166 as_bad (_("expected comma after name \"%s\""), name);
b99bd4ef
NC
3167 *end_name = delim;
3168 ignore_rest_of_line ();
3169 return;
3170 }
3171
3172 input_line_pointer++;
3173 *end_name = 0;
3174
3175 if (name[0] == '.' && name[1] == '\0')
3176 {
3177 /* XXX - this should not happen to .thumb_set. */
3178 abort ();
3179 }
3180
3181 if ((symbolP = symbol_find (name)) == NULL
3182 && (symbolP = md_undefined_symbol (name)) == NULL)
3183 {
3184#ifndef NO_LISTING
3185 /* When doing symbol listings, play games with dummy fragments living
3186 outside the normal fragment chain to record the file and line info
c19d1205 3187 for this symbol. */
b99bd4ef
NC
3188 if (listing & LISTING_SYMBOLS)
3189 {
3190 extern struct list_info_struct * listing_tail;
21d799b5 3191 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
b99bd4ef
NC
3192
3193 memset (dummy_frag, 0, sizeof (fragS));
3194 dummy_frag->fr_type = rs_fill;
3195 dummy_frag->line = listing_tail;
3196 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
3197 dummy_frag->fr_symbol = symbolP;
3198 }
3199 else
3200#endif
3201 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
3202
3203#ifdef OBJ_COFF
3204 /* "set" symbols are local unless otherwise specified. */
3205 SF_SET_LOCAL (symbolP);
3206#endif /* OBJ_COFF */
3207 } /* Make a new symbol. */
3208
3209 symbol_table_insert (symbolP);
3210
3211 * end_name = delim;
3212
3213 if (equiv
3214 && S_IS_DEFINED (symbolP)
3215 && S_GET_SEGMENT (symbolP) != reg_section)
3216 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
3217
3218 pseudo_set (symbolP);
3219
3220 demand_empty_rest_of_line ();
3221
c19d1205 3222 /* XXX Now we come to the Thumb specific bit of code. */
b99bd4ef
NC
3223
3224 THUMB_SET_FUNC (symbolP, 1);
3225 ARM_SET_THUMB (symbolP, 1);
3226#if defined OBJ_ELF || defined OBJ_COFF
3227 ARM_SET_INTERWORK (symbolP, support_interwork);
3228#endif
3229}
3230
c19d1205 3231/* Directives: Mode selection. */
b99bd4ef 3232
c19d1205
ZW
3233/* .syntax [unified|divided] - choose the new unified syntax
3234 (same for Arm and Thumb encoding, modulo slight differences in what
3235 can be represented) or the old divergent syntax for each mode. */
b99bd4ef 3236static void
c19d1205 3237s_syntax (int unused ATTRIBUTE_UNUSED)
b99bd4ef 3238{
c19d1205
ZW
3239 char *name, delim;
3240
d02603dc 3241 delim = get_symbol_name (& name);
c19d1205
ZW
3242
3243 if (!strcasecmp (name, "unified"))
3244 unified_syntax = TRUE;
3245 else if (!strcasecmp (name, "divided"))
3246 unified_syntax = FALSE;
3247 else
3248 {
3249 as_bad (_("unrecognized syntax mode \"%s\""), name);
3250 return;
3251 }
d02603dc 3252 (void) restore_line_pointer (delim);
b99bd4ef
NC
3253 demand_empty_rest_of_line ();
3254}
3255
c19d1205
ZW
3256/* Directives: sectioning and alignment. */
3257
c19d1205
ZW
3258static void
3259s_bss (int ignore ATTRIBUTE_UNUSED)
b99bd4ef 3260{
c19d1205
ZW
3261 /* We don't support putting frags in the BSS segment, we fake it by
3262 marking in_bss, then looking at s_skip for clues. */
3263 subseg_set (bss_section, 0);
3264 demand_empty_rest_of_line ();
cd000bff
DJ
3265
3266#ifdef md_elf_section_change_hook
3267 md_elf_section_change_hook ();
3268#endif
c19d1205 3269}
b99bd4ef 3270
c19d1205
ZW
3271static void
3272s_even (int ignore ATTRIBUTE_UNUSED)
3273{
3274 /* Never make frag if expect extra pass. */
3275 if (!need_pass_2)
3276 frag_align (1, 0, 0);
b99bd4ef 3277
c19d1205 3278 record_alignment (now_seg, 1);
b99bd4ef 3279
c19d1205 3280 demand_empty_rest_of_line ();
b99bd4ef
NC
3281}
3282
2e6976a8
DG
3283/* Directives: CodeComposer Studio. */
3284
3285/* .ref (for CodeComposer Studio syntax only). */
3286static void
3287s_ccs_ref (int unused ATTRIBUTE_UNUSED)
3288{
3289 if (codecomposer_syntax)
3290 ignore_rest_of_line ();
3291 else
3292 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3293}
3294
3295/* If name is not NULL, then it is used for marking the beginning of a
2b0f3761 3296 function, whereas if it is NULL then it means the function end. */
2e6976a8
DG
3297static void
3298asmfunc_debug (const char * name)
3299{
3300 static const char * last_name = NULL;
3301
3302 if (name != NULL)
3303 {
3304 gas_assert (last_name == NULL);
3305 last_name = name;
3306
3307 if (debug_type == DEBUG_STABS)
3308 stabs_generate_asm_func (name, name);
3309 }
3310 else
3311 {
3312 gas_assert (last_name != NULL);
3313
3314 if (debug_type == DEBUG_STABS)
3315 stabs_generate_asm_endfunc (last_name, last_name);
3316
3317 last_name = NULL;
3318 }
3319}
3320
3321static void
3322s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED)
3323{
3324 if (codecomposer_syntax)
3325 {
3326 switch (asmfunc_state)
3327 {
3328 case OUTSIDE_ASMFUNC:
3329 asmfunc_state = WAITING_ASMFUNC_NAME;
3330 break;
3331
3332 case WAITING_ASMFUNC_NAME:
3333 as_bad (_(".asmfunc repeated."));
3334 break;
3335
3336 case WAITING_ENDASMFUNC:
3337 as_bad (_(".asmfunc without function."));
3338 break;
3339 }
3340 demand_empty_rest_of_line ();
3341 }
3342 else
3343 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3344}
3345
3346static void
3347s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED)
3348{
3349 if (codecomposer_syntax)
3350 {
3351 switch (asmfunc_state)
3352 {
3353 case OUTSIDE_ASMFUNC:
3354 as_bad (_(".endasmfunc without a .asmfunc."));
3355 break;
3356
3357 case WAITING_ASMFUNC_NAME:
3358 as_bad (_(".endasmfunc without function."));
3359 break;
3360
3361 case WAITING_ENDASMFUNC:
3362 asmfunc_state = OUTSIDE_ASMFUNC;
3363 asmfunc_debug (NULL);
3364 break;
3365 }
3366 demand_empty_rest_of_line ();
3367 }
3368 else
3369 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3370}
3371
3372static void
3373s_ccs_def (int name)
3374{
3375 if (codecomposer_syntax)
3376 s_globl (name);
3377 else
3378 as_bad (_(".def pseudo-op only available with -mccs flag."));
3379}
3380
c19d1205 3381/* Directives: Literal pools. */
a737bd4d 3382
c19d1205
ZW
3383static literal_pool *
3384find_literal_pool (void)
a737bd4d 3385{
c19d1205 3386 literal_pool * pool;
a737bd4d 3387
c19d1205 3388 for (pool = list_of_pools; pool != NULL; pool = pool->next)
a737bd4d 3389 {
c19d1205
ZW
3390 if (pool->section == now_seg
3391 && pool->sub_section == now_subseg)
3392 break;
a737bd4d
NC
3393 }
3394
c19d1205 3395 return pool;
a737bd4d
NC
3396}
3397
c19d1205
ZW
3398static literal_pool *
3399find_or_make_literal_pool (void)
a737bd4d 3400{
c19d1205
ZW
3401 /* Next literal pool ID number. */
3402 static unsigned int latest_pool_num = 1;
3403 literal_pool * pool;
a737bd4d 3404
c19d1205 3405 pool = find_literal_pool ();
a737bd4d 3406
c19d1205 3407 if (pool == NULL)
a737bd4d 3408 {
c19d1205 3409 /* Create a new pool. */
325801bd 3410 pool = XNEW (literal_pool);
c19d1205
ZW
3411 if (! pool)
3412 return NULL;
a737bd4d 3413
c19d1205
ZW
3414 pool->next_free_entry = 0;
3415 pool->section = now_seg;
3416 pool->sub_section = now_subseg;
3417 pool->next = list_of_pools;
3418 pool->symbol = NULL;
8335d6aa 3419 pool->alignment = 2;
c19d1205
ZW
3420
3421 /* Add it to the list. */
3422 list_of_pools = pool;
a737bd4d 3423 }
a737bd4d 3424
c19d1205
ZW
3425 /* New pools, and emptied pools, will have a NULL symbol. */
3426 if (pool->symbol == NULL)
a737bd4d 3427 {
c19d1205
ZW
3428 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3429 (valueT) 0, &zero_address_frag);
3430 pool->id = latest_pool_num ++;
a737bd4d
NC
3431 }
3432
c19d1205
ZW
3433 /* Done. */
3434 return pool;
a737bd4d
NC
3435}
3436
c19d1205 3437/* Add the literal in the global 'inst'
5f4273c7 3438 structure to the relevant literal pool. */
b99bd4ef
NC
3439
3440static int
8335d6aa 3441add_to_lit_pool (unsigned int nbytes)
b99bd4ef 3442{
8335d6aa
JW
3443#define PADDING_SLOT 0x1
3444#define LIT_ENTRY_SIZE_MASK 0xFF
c19d1205 3445 literal_pool * pool;
8335d6aa
JW
3446 unsigned int entry, pool_size = 0;
3447 bfd_boolean padding_slot_p = FALSE;
e56c722b 3448 unsigned imm1 = 0;
8335d6aa
JW
3449 unsigned imm2 = 0;
3450
3451 if (nbytes == 8)
3452 {
3453 imm1 = inst.operands[1].imm;
3454 imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg
e2b0ab59 3455 : inst.relocs[0].exp.X_unsigned ? 0
2569ceb0 3456 : ((bfd_int64_t) inst.operands[1].imm) >> 32);
8335d6aa
JW
3457 if (target_big_endian)
3458 {
3459 imm1 = imm2;
3460 imm2 = inst.operands[1].imm;
3461 }
3462 }
b99bd4ef 3463
c19d1205
ZW
3464 pool = find_or_make_literal_pool ();
3465
3466 /* Check if this literal value is already in the pool. */
3467 for (entry = 0; entry < pool->next_free_entry; entry ++)
b99bd4ef 3468 {
8335d6aa
JW
3469 if (nbytes == 4)
3470 {
e2b0ab59
AV
3471 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3472 && (inst.relocs[0].exp.X_op == O_constant)
8335d6aa 3473 && (pool->literals[entry].X_add_number
e2b0ab59 3474 == inst.relocs[0].exp.X_add_number)
8335d6aa
JW
3475 && (pool->literals[entry].X_md == nbytes)
3476 && (pool->literals[entry].X_unsigned
e2b0ab59 3477 == inst.relocs[0].exp.X_unsigned))
8335d6aa
JW
3478 break;
3479
e2b0ab59
AV
3480 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3481 && (inst.relocs[0].exp.X_op == O_symbol)
8335d6aa 3482 && (pool->literals[entry].X_add_number
e2b0ab59 3483 == inst.relocs[0].exp.X_add_number)
8335d6aa 3484 && (pool->literals[entry].X_add_symbol
e2b0ab59 3485 == inst.relocs[0].exp.X_add_symbol)
8335d6aa 3486 && (pool->literals[entry].X_op_symbol
e2b0ab59 3487 == inst.relocs[0].exp.X_op_symbol)
8335d6aa
JW
3488 && (pool->literals[entry].X_md == nbytes))
3489 break;
3490 }
3491 else if ((nbytes == 8)
3492 && !(pool_size & 0x7)
3493 && ((entry + 1) != pool->next_free_entry)
3494 && (pool->literals[entry].X_op == O_constant)
19f2f6a9 3495 && (pool->literals[entry].X_add_number == (offsetT) imm1)
8335d6aa 3496 && (pool->literals[entry].X_unsigned
e2b0ab59 3497 == inst.relocs[0].exp.X_unsigned)
8335d6aa 3498 && (pool->literals[entry + 1].X_op == O_constant)
19f2f6a9 3499 && (pool->literals[entry + 1].X_add_number == (offsetT) imm2)
8335d6aa 3500 && (pool->literals[entry + 1].X_unsigned
e2b0ab59 3501 == inst.relocs[0].exp.X_unsigned))
c19d1205
ZW
3502 break;
3503
8335d6aa
JW
3504 padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT);
3505 if (padding_slot_p && (nbytes == 4))
c19d1205 3506 break;
8335d6aa
JW
3507
3508 pool_size += 4;
b99bd4ef
NC
3509 }
3510
c19d1205
ZW
3511 /* Do we need to create a new entry? */
3512 if (entry == pool->next_free_entry)
3513 {
3514 if (entry >= MAX_LITERAL_POOL_SIZE)
3515 {
3516 inst.error = _("literal pool overflow");
3517 return FAIL;
3518 }
3519
8335d6aa
JW
3520 if (nbytes == 8)
3521 {
3522 /* For 8-byte entries, we align to an 8-byte boundary,
3523 and split it into two 4-byte entries, because on 32-bit
3524 host, 8-byte constants are treated as big num, thus
3525 saved in "generic_bignum" which will be overwritten
3526 by later assignments.
3527
3528 We also need to make sure there is enough space for
3529 the split.
3530
3531 We also check to make sure the literal operand is a
3532 constant number. */
e2b0ab59
AV
3533 if (!(inst.relocs[0].exp.X_op == O_constant
3534 || inst.relocs[0].exp.X_op == O_big))
8335d6aa
JW
3535 {
3536 inst.error = _("invalid type for literal pool");
3537 return FAIL;
3538 }
3539 else if (pool_size & 0x7)
3540 {
3541 if ((entry + 2) >= MAX_LITERAL_POOL_SIZE)
3542 {
3543 inst.error = _("literal pool overflow");
3544 return FAIL;
3545 }
3546
e2b0ab59 3547 pool->literals[entry] = inst.relocs[0].exp;
a6684f0d 3548 pool->literals[entry].X_op = O_constant;
8335d6aa
JW
3549 pool->literals[entry].X_add_number = 0;
3550 pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4;
3551 pool->next_free_entry += 1;
3552 pool_size += 4;
3553 }
3554 else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE)
3555 {
3556 inst.error = _("literal pool overflow");
3557 return FAIL;
3558 }
3559
e2b0ab59 3560 pool->literals[entry] = inst.relocs[0].exp;
8335d6aa
JW
3561 pool->literals[entry].X_op = O_constant;
3562 pool->literals[entry].X_add_number = imm1;
e2b0ab59 3563 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
8335d6aa 3564 pool->literals[entry++].X_md = 4;
e2b0ab59 3565 pool->literals[entry] = inst.relocs[0].exp;
8335d6aa
JW
3566 pool->literals[entry].X_op = O_constant;
3567 pool->literals[entry].X_add_number = imm2;
e2b0ab59 3568 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
8335d6aa
JW
3569 pool->literals[entry].X_md = 4;
3570 pool->alignment = 3;
3571 pool->next_free_entry += 1;
3572 }
3573 else
3574 {
e2b0ab59 3575 pool->literals[entry] = inst.relocs[0].exp;
8335d6aa
JW
3576 pool->literals[entry].X_md = 4;
3577 }
3578
a8040cf2
NC
3579#ifdef OBJ_ELF
3580 /* PR ld/12974: Record the location of the first source line to reference
3581 this entry in the literal pool. If it turns out during linking that the
3582 symbol does not exist we will be able to give an accurate line number for
3583 the (first use of the) missing reference. */
3584 if (debug_type == DEBUG_DWARF2)
3585 dwarf2_where (pool->locs + entry);
3586#endif
c19d1205
ZW
3587 pool->next_free_entry += 1;
3588 }
8335d6aa
JW
3589 else if (padding_slot_p)
3590 {
e2b0ab59 3591 pool->literals[entry] = inst.relocs[0].exp;
8335d6aa
JW
3592 pool->literals[entry].X_md = nbytes;
3593 }
b99bd4ef 3594
e2b0ab59
AV
3595 inst.relocs[0].exp.X_op = O_symbol;
3596 inst.relocs[0].exp.X_add_number = pool_size;
3597 inst.relocs[0].exp.X_add_symbol = pool->symbol;
b99bd4ef 3598
c19d1205 3599 return SUCCESS;
b99bd4ef
NC
3600}
3601
2e6976a8 3602bfd_boolean
2e57ce7b 3603tc_start_label_without_colon (void)
2e6976a8
DG
3604{
3605 bfd_boolean ret = TRUE;
3606
3607 if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME)
3608 {
2e57ce7b 3609 const char *label = input_line_pointer;
2e6976a8
DG
3610
3611 while (!is_end_of_line[(int) label[-1]])
3612 --label;
3613
3614 if (*label == '.')
3615 {
3616 as_bad (_("Invalid label '%s'"), label);
3617 ret = FALSE;
3618 }
3619
3620 asmfunc_debug (label);
3621
3622 asmfunc_state = WAITING_ENDASMFUNC;
3623 }
3624
3625 return ret;
3626}
3627
c19d1205 3628/* Can't use symbol_new here, so have to create a symbol and then at
33eaf5de 3629 a later date assign it a value. That's what these functions do. */
e16bb312 3630
c19d1205
ZW
3631static void
3632symbol_locate (symbolS * symbolP,
3633 const char * name, /* It is copied, the caller can modify. */
3634 segT segment, /* Segment identifier (SEG_<something>). */
3635 valueT valu, /* Symbol value. */
3636 fragS * frag) /* Associated fragment. */
3637{
e57e6ddc 3638 size_t name_length;
c19d1205 3639 char * preserved_copy_of_name;
e16bb312 3640
c19d1205
ZW
3641 name_length = strlen (name) + 1; /* +1 for \0. */
3642 obstack_grow (&notes, name, name_length);
21d799b5 3643 preserved_copy_of_name = (char *) obstack_finish (&notes);
e16bb312 3644
c19d1205
ZW
3645#ifdef tc_canonicalize_symbol_name
3646 preserved_copy_of_name =
3647 tc_canonicalize_symbol_name (preserved_copy_of_name);
3648#endif
b99bd4ef 3649
c19d1205 3650 S_SET_NAME (symbolP, preserved_copy_of_name);
b99bd4ef 3651
c19d1205
ZW
3652 S_SET_SEGMENT (symbolP, segment);
3653 S_SET_VALUE (symbolP, valu);
3654 symbol_clear_list_pointers (symbolP);
b99bd4ef 3655
c19d1205 3656 symbol_set_frag (symbolP, frag);
b99bd4ef 3657
c19d1205
ZW
3658 /* Link to end of symbol chain. */
3659 {
3660 extern int symbol_table_frozen;
b99bd4ef 3661
c19d1205
ZW
3662 if (symbol_table_frozen)
3663 abort ();
3664 }
b99bd4ef 3665
c19d1205 3666 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
b99bd4ef 3667
c19d1205 3668 obj_symbol_new_hook (symbolP);
b99bd4ef 3669
c19d1205
ZW
3670#ifdef tc_symbol_new_hook
3671 tc_symbol_new_hook (symbolP);
3672#endif
3673
3674#ifdef DEBUG_SYMS
3675 verify_symbol_chain (symbol_rootP, symbol_lastP);
3676#endif /* DEBUG_SYMS */
b99bd4ef
NC
3677}
3678
c19d1205
ZW
3679static void
3680s_ltorg (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 3681{
c19d1205
ZW
3682 unsigned int entry;
3683 literal_pool * pool;
3684 char sym_name[20];
b99bd4ef 3685
c19d1205
ZW
3686 pool = find_literal_pool ();
3687 if (pool == NULL
3688 || pool->symbol == NULL
3689 || pool->next_free_entry == 0)
3690 return;
b99bd4ef 3691
c19d1205
ZW
3692 /* Align pool as you have word accesses.
3693 Only make a frag if we have to. */
3694 if (!need_pass_2)
8335d6aa 3695 frag_align (pool->alignment, 0, 0);
b99bd4ef 3696
c19d1205 3697 record_alignment (now_seg, 2);
b99bd4ef 3698
aaca88ef 3699#ifdef OBJ_ELF
47fc6e36
WN
3700 seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA;
3701 make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now);
aaca88ef 3702#endif
c19d1205 3703 sprintf (sym_name, "$$lit_\002%x", pool->id);
b99bd4ef 3704
c19d1205
ZW
3705 symbol_locate (pool->symbol, sym_name, now_seg,
3706 (valueT) frag_now_fix (), frag_now);
3707 symbol_table_insert (pool->symbol);
b99bd4ef 3708
c19d1205 3709 ARM_SET_THUMB (pool->symbol, thumb_mode);
b99bd4ef 3710
c19d1205
ZW
3711#if defined OBJ_COFF || defined OBJ_ELF
3712 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3713#endif
6c43fab6 3714
c19d1205 3715 for (entry = 0; entry < pool->next_free_entry; entry ++)
a8040cf2
NC
3716 {
3717#ifdef OBJ_ELF
3718 if (debug_type == DEBUG_DWARF2)
3719 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3720#endif
3721 /* First output the expression in the instruction to the pool. */
8335d6aa
JW
3722 emit_expr (&(pool->literals[entry]),
3723 pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK);
a8040cf2 3724 }
b99bd4ef 3725
c19d1205
ZW
3726 /* Mark the pool as empty. */
3727 pool->next_free_entry = 0;
3728 pool->symbol = NULL;
b99bd4ef
NC
3729}
3730
c19d1205
ZW
3731#ifdef OBJ_ELF
3732/* Forward declarations for functions below, in the MD interface
3733 section. */
3734static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3735static valueT create_unwind_entry (int);
3736static void start_unwind_section (const segT, int);
3737static void add_unwind_opcode (valueT, int);
3738static void flush_pending_unwind (void);
b99bd4ef 3739
c19d1205 3740/* Directives: Data. */
b99bd4ef 3741
c19d1205
ZW
3742static void
3743s_arm_elf_cons (int nbytes)
3744{
3745 expressionS exp;
b99bd4ef 3746
c19d1205
ZW
3747#ifdef md_flush_pending_output
3748 md_flush_pending_output ();
3749#endif
b99bd4ef 3750
c19d1205 3751 if (is_it_end_of_statement ())
b99bd4ef 3752 {
c19d1205
ZW
3753 demand_empty_rest_of_line ();
3754 return;
b99bd4ef
NC
3755 }
3756
c19d1205
ZW
3757#ifdef md_cons_align
3758 md_cons_align (nbytes);
3759#endif
b99bd4ef 3760
c19d1205
ZW
3761 mapping_state (MAP_DATA);
3762 do
b99bd4ef 3763 {
c19d1205
ZW
3764 int reloc;
3765 char *base = input_line_pointer;
b99bd4ef 3766
c19d1205 3767 expression (& exp);
b99bd4ef 3768
c19d1205
ZW
3769 if (exp.X_op != O_symbol)
3770 emit_expr (&exp, (unsigned int) nbytes);
3771 else
3772 {
3773 char *before_reloc = input_line_pointer;
3774 reloc = parse_reloc (&input_line_pointer);
3775 if (reloc == -1)
3776 {
3777 as_bad (_("unrecognized relocation suffix"));
3778 ignore_rest_of_line ();
3779 return;
3780 }
3781 else if (reloc == BFD_RELOC_UNUSED)
3782 emit_expr (&exp, (unsigned int) nbytes);
3783 else
3784 {
21d799b5 3785 reloc_howto_type *howto = (reloc_howto_type *)
477330fc
RM
3786 bfd_reloc_type_lookup (stdoutput,
3787 (bfd_reloc_code_real_type) reloc);
c19d1205 3788 int size = bfd_get_reloc_size (howto);
b99bd4ef 3789
2fc8bdac
ZW
3790 if (reloc == BFD_RELOC_ARM_PLT32)
3791 {
3792 as_bad (_("(plt) is only valid on branch targets"));
3793 reloc = BFD_RELOC_UNUSED;
3794 size = 0;
3795 }
3796
c19d1205 3797 if (size > nbytes)
992a06ee
AM
3798 as_bad (ngettext ("%s relocations do not fit in %d byte",
3799 "%s relocations do not fit in %d bytes",
3800 nbytes),
c19d1205
ZW
3801 howto->name, nbytes);
3802 else
3803 {
3804 /* We've parsed an expression stopping at O_symbol.
3805 But there may be more expression left now that we
3806 have parsed the relocation marker. Parse it again.
3807 XXX Surely there is a cleaner way to do this. */
3808 char *p = input_line_pointer;
3809 int offset;
325801bd 3810 char *save_buf = XNEWVEC (char, input_line_pointer - base);
e1fa0163 3811
c19d1205
ZW
3812 memcpy (save_buf, base, input_line_pointer - base);
3813 memmove (base + (input_line_pointer - before_reloc),
3814 base, before_reloc - base);
3815
3816 input_line_pointer = base + (input_line_pointer-before_reloc);
3817 expression (&exp);
3818 memcpy (base, save_buf, p - base);
3819
3820 offset = nbytes - size;
4b1a927e
AM
3821 p = frag_more (nbytes);
3822 memset (p, 0, nbytes);
c19d1205 3823 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
21d799b5 3824 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
e1fa0163 3825 free (save_buf);
c19d1205
ZW
3826 }
3827 }
3828 }
b99bd4ef 3829 }
c19d1205 3830 while (*input_line_pointer++ == ',');
b99bd4ef 3831
c19d1205
ZW
3832 /* Put terminator back into stream. */
3833 input_line_pointer --;
3834 demand_empty_rest_of_line ();
b99bd4ef
NC
3835}
3836
c921be7d
NC
3837/* Emit an expression containing a 32-bit thumb instruction.
3838 Implementation based on put_thumb32_insn. */
3839
3840static void
3841emit_thumb32_expr (expressionS * exp)
3842{
3843 expressionS exp_high = *exp;
3844
3845 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3846 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3847 exp->X_add_number &= 0xffff;
3848 emit_expr (exp, (unsigned int) THUMB_SIZE);
3849}
3850
3851/* Guess the instruction size based on the opcode. */
3852
3853static int
3854thumb_insn_size (int opcode)
3855{
3856 if ((unsigned int) opcode < 0xe800u)
3857 return 2;
3858 else if ((unsigned int) opcode >= 0xe8000000u)
3859 return 4;
3860 else
3861 return 0;
3862}
3863
3864static bfd_boolean
3865emit_insn (expressionS *exp, int nbytes)
3866{
3867 int size = 0;
3868
3869 if (exp->X_op == O_constant)
3870 {
3871 size = nbytes;
3872
3873 if (size == 0)
3874 size = thumb_insn_size (exp->X_add_number);
3875
3876 if (size != 0)
3877 {
3878 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3879 {
3880 as_bad (_(".inst.n operand too big. "\
3881 "Use .inst.w instead"));
3882 size = 0;
3883 }
3884 else
3885 {
5ee91343
AV
3886 if (now_pred.state == AUTOMATIC_PRED_BLOCK)
3887 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN, 0);
c921be7d 3888 else
5ee91343 3889 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
c921be7d
NC
3890
3891 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3892 emit_thumb32_expr (exp);
3893 else
3894 emit_expr (exp, (unsigned int) size);
3895
3896 it_fsm_post_encode ();
3897 }
3898 }
3899 else
3900 as_bad (_("cannot determine Thumb instruction size. " \
3901 "Use .inst.n/.inst.w instead"));
3902 }
3903 else
3904 as_bad (_("constant expression required"));
3905
3906 return (size != 0);
3907}
3908
3909/* Like s_arm_elf_cons but do not use md_cons_align and
3910 set the mapping state to MAP_ARM/MAP_THUMB. */
3911
3912static void
3913s_arm_elf_inst (int nbytes)
3914{
3915 if (is_it_end_of_statement ())
3916 {
3917 demand_empty_rest_of_line ();
3918 return;
3919 }
3920
3921 /* Calling mapping_state () here will not change ARM/THUMB,
3922 but will ensure not to be in DATA state. */
3923
3924 if (thumb_mode)
3925 mapping_state (MAP_THUMB);
3926 else
3927 {
3928 if (nbytes != 0)
3929 {
3930 as_bad (_("width suffixes are invalid in ARM mode"));
3931 ignore_rest_of_line ();
3932 return;
3933 }
3934
3935 nbytes = 4;
3936
3937 mapping_state (MAP_ARM);
3938 }
3939
3940 do
3941 {
3942 expressionS exp;
3943
3944 expression (& exp);
3945
3946 if (! emit_insn (& exp, nbytes))
3947 {
3948 ignore_rest_of_line ();
3949 return;
3950 }
3951 }
3952 while (*input_line_pointer++ == ',');
3953
3954 /* Put terminator back into stream. */
3955 input_line_pointer --;
3956 demand_empty_rest_of_line ();
3957}
b99bd4ef 3958
c19d1205 3959/* Parse a .rel31 directive. */
b99bd4ef 3960
c19d1205
ZW
3961static void
3962s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3963{
3964 expressionS exp;
3965 char *p;
3966 valueT highbit;
b99bd4ef 3967
c19d1205
ZW
3968 highbit = 0;
3969 if (*input_line_pointer == '1')
3970 highbit = 0x80000000;
3971 else if (*input_line_pointer != '0')
3972 as_bad (_("expected 0 or 1"));
b99bd4ef 3973
c19d1205
ZW
3974 input_line_pointer++;
3975 if (*input_line_pointer != ',')
3976 as_bad (_("missing comma"));
3977 input_line_pointer++;
b99bd4ef 3978
c19d1205
ZW
3979#ifdef md_flush_pending_output
3980 md_flush_pending_output ();
3981#endif
b99bd4ef 3982
c19d1205
ZW
3983#ifdef md_cons_align
3984 md_cons_align (4);
3985#endif
b99bd4ef 3986
c19d1205 3987 mapping_state (MAP_DATA);
b99bd4ef 3988
c19d1205 3989 expression (&exp);
b99bd4ef 3990
c19d1205
ZW
3991 p = frag_more (4);
3992 md_number_to_chars (p, highbit, 4);
3993 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3994 BFD_RELOC_ARM_PREL31);
b99bd4ef 3995
c19d1205 3996 demand_empty_rest_of_line ();
b99bd4ef
NC
3997}
3998
c19d1205 3999/* Directives: AEABI stack-unwind tables. */
b99bd4ef 4000
c19d1205 4001/* Parse an unwind_fnstart directive. Simply records the current location. */
b99bd4ef 4002
c19d1205
ZW
4003static void
4004s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
4005{
4006 demand_empty_rest_of_line ();
921e5f0a
PB
4007 if (unwind.proc_start)
4008 {
c921be7d 4009 as_bad (_("duplicate .fnstart directive"));
921e5f0a
PB
4010 return;
4011 }
4012
c19d1205
ZW
4013 /* Mark the start of the function. */
4014 unwind.proc_start = expr_build_dot ();
b99bd4ef 4015
c19d1205
ZW
4016 /* Reset the rest of the unwind info. */
4017 unwind.opcode_count = 0;
4018 unwind.table_entry = NULL;
4019 unwind.personality_routine = NULL;
4020 unwind.personality_index = -1;
4021 unwind.frame_size = 0;
4022 unwind.fp_offset = 0;
fdfde340 4023 unwind.fp_reg = REG_SP;
c19d1205
ZW
4024 unwind.fp_used = 0;
4025 unwind.sp_restored = 0;
4026}
b99bd4ef 4027
b99bd4ef 4028
c19d1205
ZW
4029/* Parse a handlerdata directive. Creates the exception handling table entry
4030 for the function. */
b99bd4ef 4031
c19d1205
ZW
4032static void
4033s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
4034{
4035 demand_empty_rest_of_line ();
921e5f0a 4036 if (!unwind.proc_start)
c921be7d 4037 as_bad (MISSING_FNSTART);
921e5f0a 4038
c19d1205 4039 if (unwind.table_entry)
6decc662 4040 as_bad (_("duplicate .handlerdata directive"));
f02232aa 4041
c19d1205
ZW
4042 create_unwind_entry (1);
4043}
a737bd4d 4044
c19d1205 4045/* Parse an unwind_fnend directive. Generates the index table entry. */
b99bd4ef 4046
c19d1205
ZW
4047static void
4048s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
4049{
4050 long where;
4051 char *ptr;
4052 valueT val;
940b5ce0 4053 unsigned int marked_pr_dependency;
f02232aa 4054
c19d1205 4055 demand_empty_rest_of_line ();
f02232aa 4056
921e5f0a
PB
4057 if (!unwind.proc_start)
4058 {
c921be7d 4059 as_bad (_(".fnend directive without .fnstart"));
921e5f0a
PB
4060 return;
4061 }
4062
c19d1205
ZW
4063 /* Add eh table entry. */
4064 if (unwind.table_entry == NULL)
4065 val = create_unwind_entry (0);
4066 else
4067 val = 0;
f02232aa 4068
c19d1205
ZW
4069 /* Add index table entry. This is two words. */
4070 start_unwind_section (unwind.saved_seg, 1);
4071 frag_align (2, 0, 0);
4072 record_alignment (now_seg, 2);
b99bd4ef 4073
c19d1205 4074 ptr = frag_more (8);
5011093d 4075 memset (ptr, 0, 8);
c19d1205 4076 where = frag_now_fix () - 8;
f02232aa 4077
c19d1205
ZW
4078 /* Self relative offset of the function start. */
4079 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
4080 BFD_RELOC_ARM_PREL31);
f02232aa 4081
c19d1205
ZW
4082 /* Indicate dependency on EHABI-defined personality routines to the
4083 linker, if it hasn't been done already. */
940b5ce0
DJ
4084 marked_pr_dependency
4085 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
c19d1205
ZW
4086 if (unwind.personality_index >= 0 && unwind.personality_index < 3
4087 && !(marked_pr_dependency & (1 << unwind.personality_index)))
4088 {
5f4273c7
NC
4089 static const char *const name[] =
4090 {
4091 "__aeabi_unwind_cpp_pr0",
4092 "__aeabi_unwind_cpp_pr1",
4093 "__aeabi_unwind_cpp_pr2"
4094 };
c19d1205
ZW
4095 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
4096 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
c19d1205 4097 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
940b5ce0 4098 |= 1 << unwind.personality_index;
c19d1205 4099 }
f02232aa 4100
c19d1205
ZW
4101 if (val)
4102 /* Inline exception table entry. */
4103 md_number_to_chars (ptr + 4, val, 4);
4104 else
4105 /* Self relative offset of the table entry. */
4106 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
4107 BFD_RELOC_ARM_PREL31);
f02232aa 4108
c19d1205
ZW
4109 /* Restore the original section. */
4110 subseg_set (unwind.saved_seg, unwind.saved_subseg);
921e5f0a
PB
4111
4112 unwind.proc_start = NULL;
c19d1205 4113}
f02232aa 4114
f02232aa 4115
c19d1205 4116/* Parse an unwind_cantunwind directive. */
b99bd4ef 4117
c19d1205
ZW
4118static void
4119s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
4120{
4121 demand_empty_rest_of_line ();
921e5f0a 4122 if (!unwind.proc_start)
c921be7d 4123 as_bad (MISSING_FNSTART);
921e5f0a 4124
c19d1205
ZW
4125 if (unwind.personality_routine || unwind.personality_index != -1)
4126 as_bad (_("personality routine specified for cantunwind frame"));
b99bd4ef 4127
c19d1205
ZW
4128 unwind.personality_index = -2;
4129}
b99bd4ef 4130
b99bd4ef 4131
c19d1205 4132/* Parse a personalityindex directive. */
b99bd4ef 4133
c19d1205
ZW
4134static void
4135s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
4136{
4137 expressionS exp;
b99bd4ef 4138
921e5f0a 4139 if (!unwind.proc_start)
c921be7d 4140 as_bad (MISSING_FNSTART);
921e5f0a 4141
c19d1205
ZW
4142 if (unwind.personality_routine || unwind.personality_index != -1)
4143 as_bad (_("duplicate .personalityindex directive"));
b99bd4ef 4144
c19d1205 4145 expression (&exp);
b99bd4ef 4146
c19d1205
ZW
4147 if (exp.X_op != O_constant
4148 || exp.X_add_number < 0 || exp.X_add_number > 15)
b99bd4ef 4149 {
c19d1205
ZW
4150 as_bad (_("bad personality routine number"));
4151 ignore_rest_of_line ();
4152 return;
b99bd4ef
NC
4153 }
4154
c19d1205 4155 unwind.personality_index = exp.X_add_number;
b99bd4ef 4156
c19d1205
ZW
4157 demand_empty_rest_of_line ();
4158}
e16bb312 4159
e16bb312 4160
c19d1205 4161/* Parse a personality directive. */
e16bb312 4162
c19d1205
ZW
4163static void
4164s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
4165{
4166 char *name, *p, c;
a737bd4d 4167
921e5f0a 4168 if (!unwind.proc_start)
c921be7d 4169 as_bad (MISSING_FNSTART);
921e5f0a 4170
c19d1205
ZW
4171 if (unwind.personality_routine || unwind.personality_index != -1)
4172 as_bad (_("duplicate .personality directive"));
a737bd4d 4173
d02603dc 4174 c = get_symbol_name (& name);
c19d1205 4175 p = input_line_pointer;
d02603dc
NC
4176 if (c == '"')
4177 ++ input_line_pointer;
c19d1205
ZW
4178 unwind.personality_routine = symbol_find_or_make (name);
4179 *p = c;
4180 demand_empty_rest_of_line ();
4181}
e16bb312 4182
e16bb312 4183
c19d1205 4184/* Parse a directive saving core registers. */
e16bb312 4185
c19d1205
ZW
4186static void
4187s_arm_unwind_save_core (void)
e16bb312 4188{
c19d1205
ZW
4189 valueT op;
4190 long range;
4191 int n;
e16bb312 4192
4b5a202f 4193 range = parse_reg_list (&input_line_pointer, REGLIST_RN);
c19d1205 4194 if (range == FAIL)
e16bb312 4195 {
c19d1205
ZW
4196 as_bad (_("expected register list"));
4197 ignore_rest_of_line ();
4198 return;
4199 }
e16bb312 4200
c19d1205 4201 demand_empty_rest_of_line ();
e16bb312 4202
c19d1205
ZW
4203 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4204 into .unwind_save {..., sp...}. We aren't bothered about the value of
4205 ip because it is clobbered by calls. */
4206 if (unwind.sp_restored && unwind.fp_reg == 12
4207 && (range & 0x3000) == 0x1000)
4208 {
4209 unwind.opcode_count--;
4210 unwind.sp_restored = 0;
4211 range = (range | 0x2000) & ~0x1000;
4212 unwind.pending_offset = 0;
4213 }
e16bb312 4214
01ae4198
DJ
4215 /* Pop r4-r15. */
4216 if (range & 0xfff0)
c19d1205 4217 {
01ae4198
DJ
4218 /* See if we can use the short opcodes. These pop a block of up to 8
4219 registers starting with r4, plus maybe r14. */
4220 for (n = 0; n < 8; n++)
4221 {
4222 /* Break at the first non-saved register. */
4223 if ((range & (1 << (n + 4))) == 0)
4224 break;
4225 }
4226 /* See if there are any other bits set. */
4227 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
4228 {
4229 /* Use the long form. */
4230 op = 0x8000 | ((range >> 4) & 0xfff);
4231 add_unwind_opcode (op, 2);
4232 }
0dd132b6 4233 else
01ae4198
DJ
4234 {
4235 /* Use the short form. */
4236 if (range & 0x4000)
4237 op = 0xa8; /* Pop r14. */
4238 else
4239 op = 0xa0; /* Do not pop r14. */
4240 op |= (n - 1);
4241 add_unwind_opcode (op, 1);
4242 }
c19d1205 4243 }
0dd132b6 4244
c19d1205
ZW
4245 /* Pop r0-r3. */
4246 if (range & 0xf)
4247 {
4248 op = 0xb100 | (range & 0xf);
4249 add_unwind_opcode (op, 2);
0dd132b6
NC
4250 }
4251
c19d1205
ZW
4252 /* Record the number of bytes pushed. */
4253 for (n = 0; n < 16; n++)
4254 {
4255 if (range & (1 << n))
4256 unwind.frame_size += 4;
4257 }
0dd132b6
NC
4258}
4259
c19d1205
ZW
4260
4261/* Parse a directive saving FPA registers. */
b99bd4ef
NC
4262
4263static void
c19d1205 4264s_arm_unwind_save_fpa (int reg)
b99bd4ef 4265{
c19d1205
ZW
4266 expressionS exp;
4267 int num_regs;
4268 valueT op;
b99bd4ef 4269
c19d1205
ZW
4270 /* Get Number of registers to transfer. */
4271 if (skip_past_comma (&input_line_pointer) != FAIL)
4272 expression (&exp);
4273 else
4274 exp.X_op = O_illegal;
b99bd4ef 4275
c19d1205 4276 if (exp.X_op != O_constant)
b99bd4ef 4277 {
c19d1205
ZW
4278 as_bad (_("expected , <constant>"));
4279 ignore_rest_of_line ();
b99bd4ef
NC
4280 return;
4281 }
4282
c19d1205
ZW
4283 num_regs = exp.X_add_number;
4284
4285 if (num_regs < 1 || num_regs > 4)
b99bd4ef 4286 {
c19d1205
ZW
4287 as_bad (_("number of registers must be in the range [1:4]"));
4288 ignore_rest_of_line ();
b99bd4ef
NC
4289 return;
4290 }
4291
c19d1205 4292 demand_empty_rest_of_line ();
b99bd4ef 4293
c19d1205
ZW
4294 if (reg == 4)
4295 {
4296 /* Short form. */
4297 op = 0xb4 | (num_regs - 1);
4298 add_unwind_opcode (op, 1);
4299 }
b99bd4ef
NC
4300 else
4301 {
c19d1205
ZW
4302 /* Long form. */
4303 op = 0xc800 | (reg << 4) | (num_regs - 1);
4304 add_unwind_opcode (op, 2);
b99bd4ef 4305 }
c19d1205 4306 unwind.frame_size += num_regs * 12;
b99bd4ef
NC
4307}
4308
c19d1205 4309
fa073d69
MS
4310/* Parse a directive saving VFP registers for ARMv6 and above. */
4311
4312static void
4313s_arm_unwind_save_vfp_armv6 (void)
4314{
4315 int count;
4316 unsigned int start;
4317 valueT op;
4318 int num_vfpv3_regs = 0;
4319 int num_regs_below_16;
efd6b359 4320 bfd_boolean partial_match;
fa073d69 4321
efd6b359
AV
4322 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D,
4323 &partial_match);
fa073d69
MS
4324 if (count == FAIL)
4325 {
4326 as_bad (_("expected register list"));
4327 ignore_rest_of_line ();
4328 return;
4329 }
4330
4331 demand_empty_rest_of_line ();
4332
4333 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4334 than FSTMX/FLDMX-style ones). */
4335
4336 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4337 if (start >= 16)
4338 num_vfpv3_regs = count;
4339 else if (start + count > 16)
4340 num_vfpv3_regs = start + count - 16;
4341
4342 if (num_vfpv3_regs > 0)
4343 {
4344 int start_offset = start > 16 ? start - 16 : 0;
4345 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
4346 add_unwind_opcode (op, 2);
4347 }
4348
4349 /* Generate opcode for registers numbered in the range 0 .. 15. */
4350 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
9c2799c2 4351 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
fa073d69
MS
4352 if (num_regs_below_16 > 0)
4353 {
4354 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
4355 add_unwind_opcode (op, 2);
4356 }
4357
4358 unwind.frame_size += count * 8;
4359}
4360
4361
4362/* Parse a directive saving VFP registers for pre-ARMv6. */
b99bd4ef
NC
4363
4364static void
c19d1205 4365s_arm_unwind_save_vfp (void)
b99bd4ef 4366{
c19d1205 4367 int count;
ca3f61f7 4368 unsigned int reg;
c19d1205 4369 valueT op;
efd6b359 4370 bfd_boolean partial_match;
b99bd4ef 4371
efd6b359
AV
4372 count = parse_vfp_reg_list (&input_line_pointer, &reg, REGLIST_VFP_D,
4373 &partial_match);
c19d1205 4374 if (count == FAIL)
b99bd4ef 4375 {
c19d1205
ZW
4376 as_bad (_("expected register list"));
4377 ignore_rest_of_line ();
b99bd4ef
NC
4378 return;
4379 }
4380
c19d1205 4381 demand_empty_rest_of_line ();
b99bd4ef 4382
c19d1205 4383 if (reg == 8)
b99bd4ef 4384 {
c19d1205
ZW
4385 /* Short form. */
4386 op = 0xb8 | (count - 1);
4387 add_unwind_opcode (op, 1);
b99bd4ef 4388 }
c19d1205 4389 else
b99bd4ef 4390 {
c19d1205
ZW
4391 /* Long form. */
4392 op = 0xb300 | (reg << 4) | (count - 1);
4393 add_unwind_opcode (op, 2);
b99bd4ef 4394 }
c19d1205
ZW
4395 unwind.frame_size += count * 8 + 4;
4396}
b99bd4ef 4397
b99bd4ef 4398
c19d1205
ZW
4399/* Parse a directive saving iWMMXt data registers. */
4400
4401static void
4402s_arm_unwind_save_mmxwr (void)
4403{
4404 int reg;
4405 int hi_reg;
4406 int i;
4407 unsigned mask = 0;
4408 valueT op;
b99bd4ef 4409
c19d1205
ZW
4410 if (*input_line_pointer == '{')
4411 input_line_pointer++;
b99bd4ef 4412
c19d1205 4413 do
b99bd4ef 4414 {
dcbf9037 4415 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
b99bd4ef 4416
c19d1205 4417 if (reg == FAIL)
b99bd4ef 4418 {
9b7132d3 4419 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
c19d1205 4420 goto error;
b99bd4ef
NC
4421 }
4422
c19d1205
ZW
4423 if (mask >> reg)
4424 as_tsktsk (_("register list not in ascending order"));
4425 mask |= 1 << reg;
b99bd4ef 4426
c19d1205
ZW
4427 if (*input_line_pointer == '-')
4428 {
4429 input_line_pointer++;
dcbf9037 4430 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
c19d1205
ZW
4431 if (hi_reg == FAIL)
4432 {
9b7132d3 4433 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
c19d1205
ZW
4434 goto error;
4435 }
4436 else if (reg >= hi_reg)
4437 {
4438 as_bad (_("bad register range"));
4439 goto error;
4440 }
4441 for (; reg < hi_reg; reg++)
4442 mask |= 1 << reg;
4443 }
4444 }
4445 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 4446
d996d970 4447 skip_past_char (&input_line_pointer, '}');
b99bd4ef 4448
c19d1205 4449 demand_empty_rest_of_line ();
b99bd4ef 4450
708587a4 4451 /* Generate any deferred opcodes because we're going to be looking at
c19d1205
ZW
4452 the list. */
4453 flush_pending_unwind ();
b99bd4ef 4454
c19d1205 4455 for (i = 0; i < 16; i++)
b99bd4ef 4456 {
c19d1205
ZW
4457 if (mask & (1 << i))
4458 unwind.frame_size += 8;
b99bd4ef
NC
4459 }
4460
c19d1205
ZW
4461 /* Attempt to combine with a previous opcode. We do this because gcc
4462 likes to output separate unwind directives for a single block of
4463 registers. */
4464 if (unwind.opcode_count > 0)
b99bd4ef 4465 {
c19d1205
ZW
4466 i = unwind.opcodes[unwind.opcode_count - 1];
4467 if ((i & 0xf8) == 0xc0)
4468 {
4469 i &= 7;
4470 /* Only merge if the blocks are contiguous. */
4471 if (i < 6)
4472 {
4473 if ((mask & 0xfe00) == (1 << 9))
4474 {
4475 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
4476 unwind.opcode_count--;
4477 }
4478 }
4479 else if (i == 6 && unwind.opcode_count >= 2)
4480 {
4481 i = unwind.opcodes[unwind.opcode_count - 2];
4482 reg = i >> 4;
4483 i &= 0xf;
b99bd4ef 4484
c19d1205
ZW
4485 op = 0xffff << (reg - 1);
4486 if (reg > 0
87a1fd79 4487 && ((mask & op) == (1u << (reg - 1))))
c19d1205
ZW
4488 {
4489 op = (1 << (reg + i + 1)) - 1;
4490 op &= ~((1 << reg) - 1);
4491 mask |= op;
4492 unwind.opcode_count -= 2;
4493 }
4494 }
4495 }
b99bd4ef
NC
4496 }
4497
c19d1205
ZW
4498 hi_reg = 15;
4499 /* We want to generate opcodes in the order the registers have been
4500 saved, ie. descending order. */
4501 for (reg = 15; reg >= -1; reg--)
b99bd4ef 4502 {
c19d1205
ZW
4503 /* Save registers in blocks. */
4504 if (reg < 0
4505 || !(mask & (1 << reg)))
4506 {
4507 /* We found an unsaved reg. Generate opcodes to save the
5f4273c7 4508 preceding block. */
c19d1205
ZW
4509 if (reg != hi_reg)
4510 {
4511 if (reg == 9)
4512 {
4513 /* Short form. */
4514 op = 0xc0 | (hi_reg - 10);
4515 add_unwind_opcode (op, 1);
4516 }
4517 else
4518 {
4519 /* Long form. */
4520 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4521 add_unwind_opcode (op, 2);
4522 }
4523 }
4524 hi_reg = reg - 1;
4525 }
b99bd4ef
NC
4526 }
4527
c19d1205
ZW
4528 return;
4529error:
4530 ignore_rest_of_line ();
b99bd4ef
NC
4531}
4532
4533static void
c19d1205 4534s_arm_unwind_save_mmxwcg (void)
b99bd4ef 4535{
c19d1205
ZW
4536 int reg;
4537 int hi_reg;
4538 unsigned mask = 0;
4539 valueT op;
b99bd4ef 4540
c19d1205
ZW
4541 if (*input_line_pointer == '{')
4542 input_line_pointer++;
b99bd4ef 4543
477330fc
RM
4544 skip_whitespace (input_line_pointer);
4545
c19d1205 4546 do
b99bd4ef 4547 {
dcbf9037 4548 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
b99bd4ef 4549
c19d1205
ZW
4550 if (reg == FAIL)
4551 {
9b7132d3 4552 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
c19d1205
ZW
4553 goto error;
4554 }
b99bd4ef 4555
c19d1205
ZW
4556 reg -= 8;
4557 if (mask >> reg)
4558 as_tsktsk (_("register list not in ascending order"));
4559 mask |= 1 << reg;
b99bd4ef 4560
c19d1205
ZW
4561 if (*input_line_pointer == '-')
4562 {
4563 input_line_pointer++;
dcbf9037 4564 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
c19d1205
ZW
4565 if (hi_reg == FAIL)
4566 {
9b7132d3 4567 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
c19d1205
ZW
4568 goto error;
4569 }
4570 else if (reg >= hi_reg)
4571 {
4572 as_bad (_("bad register range"));
4573 goto error;
4574 }
4575 for (; reg < hi_reg; reg++)
4576 mask |= 1 << reg;
4577 }
b99bd4ef 4578 }
c19d1205 4579 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 4580
d996d970 4581 skip_past_char (&input_line_pointer, '}');
b99bd4ef 4582
c19d1205
ZW
4583 demand_empty_rest_of_line ();
4584
708587a4 4585 /* Generate any deferred opcodes because we're going to be looking at
c19d1205
ZW
4586 the list. */
4587 flush_pending_unwind ();
b99bd4ef 4588
c19d1205 4589 for (reg = 0; reg < 16; reg++)
b99bd4ef 4590 {
c19d1205
ZW
4591 if (mask & (1 << reg))
4592 unwind.frame_size += 4;
b99bd4ef 4593 }
c19d1205
ZW
4594 op = 0xc700 | mask;
4595 add_unwind_opcode (op, 2);
4596 return;
4597error:
4598 ignore_rest_of_line ();
b99bd4ef
NC
4599}
4600
c19d1205 4601
fa073d69
MS
4602/* Parse an unwind_save directive.
4603 If the argument is non-zero, this is a .vsave directive. */
c19d1205 4604
b99bd4ef 4605static void
fa073d69 4606s_arm_unwind_save (int arch_v6)
b99bd4ef 4607{
c19d1205
ZW
4608 char *peek;
4609 struct reg_entry *reg;
4610 bfd_boolean had_brace = FALSE;
b99bd4ef 4611
921e5f0a 4612 if (!unwind.proc_start)
c921be7d 4613 as_bad (MISSING_FNSTART);
921e5f0a 4614
c19d1205
ZW
4615 /* Figure out what sort of save we have. */
4616 peek = input_line_pointer;
b99bd4ef 4617
c19d1205 4618 if (*peek == '{')
b99bd4ef 4619 {
c19d1205
ZW
4620 had_brace = TRUE;
4621 peek++;
b99bd4ef
NC
4622 }
4623
c19d1205 4624 reg = arm_reg_parse_multi (&peek);
b99bd4ef 4625
c19d1205 4626 if (!reg)
b99bd4ef 4627 {
c19d1205
ZW
4628 as_bad (_("register expected"));
4629 ignore_rest_of_line ();
b99bd4ef
NC
4630 return;
4631 }
4632
c19d1205 4633 switch (reg->type)
b99bd4ef 4634 {
c19d1205
ZW
4635 case REG_TYPE_FN:
4636 if (had_brace)
4637 {
4638 as_bad (_("FPA .unwind_save does not take a register list"));
4639 ignore_rest_of_line ();
4640 return;
4641 }
93ac2687 4642 input_line_pointer = peek;
c19d1205 4643 s_arm_unwind_save_fpa (reg->number);
b99bd4ef 4644 return;
c19d1205 4645
1f5afe1c
NC
4646 case REG_TYPE_RN:
4647 s_arm_unwind_save_core ();
4648 return;
4649
fa073d69
MS
4650 case REG_TYPE_VFD:
4651 if (arch_v6)
477330fc 4652 s_arm_unwind_save_vfp_armv6 ();
fa073d69 4653 else
477330fc 4654 s_arm_unwind_save_vfp ();
fa073d69 4655 return;
1f5afe1c
NC
4656
4657 case REG_TYPE_MMXWR:
4658 s_arm_unwind_save_mmxwr ();
4659 return;
4660
4661 case REG_TYPE_MMXWCG:
4662 s_arm_unwind_save_mmxwcg ();
4663 return;
c19d1205
ZW
4664
4665 default:
4666 as_bad (_(".unwind_save does not support this kind of register"));
4667 ignore_rest_of_line ();
b99bd4ef 4668 }
c19d1205 4669}
b99bd4ef 4670
b99bd4ef 4671
c19d1205
ZW
4672/* Parse an unwind_movsp directive. */
4673
4674static void
4675s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4676{
4677 int reg;
4678 valueT op;
4fa3602b 4679 int offset;
c19d1205 4680
921e5f0a 4681 if (!unwind.proc_start)
c921be7d 4682 as_bad (MISSING_FNSTART);
921e5f0a 4683
dcbf9037 4684 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
c19d1205 4685 if (reg == FAIL)
b99bd4ef 4686 {
9b7132d3 4687 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
c19d1205 4688 ignore_rest_of_line ();
b99bd4ef
NC
4689 return;
4690 }
4fa3602b
PB
4691
4692 /* Optional constant. */
4693 if (skip_past_comma (&input_line_pointer) != FAIL)
4694 {
4695 if (immediate_for_directive (&offset) == FAIL)
4696 return;
4697 }
4698 else
4699 offset = 0;
4700
c19d1205 4701 demand_empty_rest_of_line ();
b99bd4ef 4702
c19d1205 4703 if (reg == REG_SP || reg == REG_PC)
b99bd4ef 4704 {
c19d1205 4705 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
b99bd4ef
NC
4706 return;
4707 }
4708
c19d1205
ZW
4709 if (unwind.fp_reg != REG_SP)
4710 as_bad (_("unexpected .unwind_movsp directive"));
b99bd4ef 4711
c19d1205
ZW
4712 /* Generate opcode to restore the value. */
4713 op = 0x90 | reg;
4714 add_unwind_opcode (op, 1);
4715
4716 /* Record the information for later. */
4717 unwind.fp_reg = reg;
4fa3602b 4718 unwind.fp_offset = unwind.frame_size - offset;
c19d1205 4719 unwind.sp_restored = 1;
b05fe5cf
ZW
4720}
4721
c19d1205
ZW
4722/* Parse an unwind_pad directive. */
4723
b05fe5cf 4724static void
c19d1205 4725s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
b05fe5cf 4726{
c19d1205 4727 int offset;
b05fe5cf 4728
921e5f0a 4729 if (!unwind.proc_start)
c921be7d 4730 as_bad (MISSING_FNSTART);
921e5f0a 4731
c19d1205
ZW
4732 if (immediate_for_directive (&offset) == FAIL)
4733 return;
b99bd4ef 4734
c19d1205
ZW
4735 if (offset & 3)
4736 {
4737 as_bad (_("stack increment must be multiple of 4"));
4738 ignore_rest_of_line ();
4739 return;
4740 }
b99bd4ef 4741
c19d1205
ZW
4742 /* Don't generate any opcodes, just record the details for later. */
4743 unwind.frame_size += offset;
4744 unwind.pending_offset += offset;
4745
4746 demand_empty_rest_of_line ();
4747}
4748
4749/* Parse an unwind_setfp directive. */
4750
4751static void
4752s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 4753{
c19d1205
ZW
4754 int sp_reg;
4755 int fp_reg;
4756 int offset;
4757
921e5f0a 4758 if (!unwind.proc_start)
c921be7d 4759 as_bad (MISSING_FNSTART);
921e5f0a 4760
dcbf9037 4761 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
c19d1205
ZW
4762 if (skip_past_comma (&input_line_pointer) == FAIL)
4763 sp_reg = FAIL;
4764 else
dcbf9037 4765 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
b99bd4ef 4766
c19d1205
ZW
4767 if (fp_reg == FAIL || sp_reg == FAIL)
4768 {
4769 as_bad (_("expected <reg>, <reg>"));
4770 ignore_rest_of_line ();
4771 return;
4772 }
b99bd4ef 4773
c19d1205
ZW
4774 /* Optional constant. */
4775 if (skip_past_comma (&input_line_pointer) != FAIL)
4776 {
4777 if (immediate_for_directive (&offset) == FAIL)
4778 return;
4779 }
4780 else
4781 offset = 0;
a737bd4d 4782
c19d1205 4783 demand_empty_rest_of_line ();
a737bd4d 4784
fdfde340 4785 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
a737bd4d 4786 {
c19d1205
ZW
4787 as_bad (_("register must be either sp or set by a previous"
4788 "unwind_movsp directive"));
4789 return;
a737bd4d
NC
4790 }
4791
c19d1205
ZW
4792 /* Don't generate any opcodes, just record the information for later. */
4793 unwind.fp_reg = fp_reg;
4794 unwind.fp_used = 1;
fdfde340 4795 if (sp_reg == REG_SP)
c19d1205
ZW
4796 unwind.fp_offset = unwind.frame_size - offset;
4797 else
4798 unwind.fp_offset -= offset;
a737bd4d
NC
4799}
4800
c19d1205
ZW
4801/* Parse an unwind_raw directive. */
4802
4803static void
4804s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
a737bd4d 4805{
c19d1205 4806 expressionS exp;
708587a4 4807 /* This is an arbitrary limit. */
c19d1205
ZW
4808 unsigned char op[16];
4809 int count;
a737bd4d 4810
921e5f0a 4811 if (!unwind.proc_start)
c921be7d 4812 as_bad (MISSING_FNSTART);
921e5f0a 4813
c19d1205
ZW
4814 expression (&exp);
4815 if (exp.X_op == O_constant
4816 && skip_past_comma (&input_line_pointer) != FAIL)
a737bd4d 4817 {
c19d1205
ZW
4818 unwind.frame_size += exp.X_add_number;
4819 expression (&exp);
4820 }
4821 else
4822 exp.X_op = O_illegal;
a737bd4d 4823
c19d1205
ZW
4824 if (exp.X_op != O_constant)
4825 {
4826 as_bad (_("expected <offset>, <opcode>"));
4827 ignore_rest_of_line ();
4828 return;
4829 }
a737bd4d 4830
c19d1205 4831 count = 0;
a737bd4d 4832
c19d1205
ZW
4833 /* Parse the opcode. */
4834 for (;;)
4835 {
4836 if (count >= 16)
4837 {
4838 as_bad (_("unwind opcode too long"));
4839 ignore_rest_of_line ();
a737bd4d 4840 }
c19d1205 4841 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
a737bd4d 4842 {
c19d1205
ZW
4843 as_bad (_("invalid unwind opcode"));
4844 ignore_rest_of_line ();
4845 return;
a737bd4d 4846 }
c19d1205 4847 op[count++] = exp.X_add_number;
a737bd4d 4848
c19d1205
ZW
4849 /* Parse the next byte. */
4850 if (skip_past_comma (&input_line_pointer) == FAIL)
4851 break;
a737bd4d 4852
c19d1205
ZW
4853 expression (&exp);
4854 }
b99bd4ef 4855
c19d1205
ZW
4856 /* Add the opcode bytes in reverse order. */
4857 while (count--)
4858 add_unwind_opcode (op[count], 1);
b99bd4ef 4859
c19d1205 4860 demand_empty_rest_of_line ();
b99bd4ef 4861}
ee065d83
PB
4862
4863
4864/* Parse a .eabi_attribute directive. */
4865
4866static void
4867s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4868{
0420f52b 4869 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
ee3c0378 4870
3076e594 4871 if (tag >= 0 && tag < NUM_KNOWN_OBJ_ATTRIBUTES)
ee3c0378 4872 attributes_set_explicitly[tag] = 1;
ee065d83
PB
4873}
4874
0855e32b
NS
4875/* Emit a tls fix for the symbol. */
4876
4877static void
4878s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4879{
4880 char *p;
4881 expressionS exp;
4882#ifdef md_flush_pending_output
4883 md_flush_pending_output ();
4884#endif
4885
4886#ifdef md_cons_align
4887 md_cons_align (4);
4888#endif
4889
4890 /* Since we're just labelling the code, there's no need to define a
4891 mapping symbol. */
4892 expression (&exp);
4893 p = obstack_next_free (&frchain_now->frch_obstack);
4894 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4895 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4896 : BFD_RELOC_ARM_TLS_DESCSEQ);
4897}
cdf9ccec 4898#endif /* OBJ_ELF */
0855e32b 4899
ee065d83 4900static void s_arm_arch (int);
7a1d4c38 4901static void s_arm_object_arch (int);
ee065d83
PB
4902static void s_arm_cpu (int);
4903static void s_arm_fpu (int);
69133863 4904static void s_arm_arch_extension (int);
b99bd4ef 4905
f0927246
NC
4906#ifdef TE_PE
4907
4908static void
5f4273c7 4909pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
f0927246
NC
4910{
4911 expressionS exp;
4912
4913 do
4914 {
4915 expression (&exp);
4916 if (exp.X_op == O_symbol)
4917 exp.X_op = O_secrel;
4918
4919 emit_expr (&exp, 4);
4920 }
4921 while (*input_line_pointer++ == ',');
4922
4923 input_line_pointer--;
4924 demand_empty_rest_of_line ();
4925}
4926#endif /* TE_PE */
4927
c19d1205
ZW
4928/* This table describes all the machine specific pseudo-ops the assembler
4929 has to support. The fields are:
4930 pseudo-op name without dot
4931 function to call to execute this pseudo-op
4932 Integer arg to pass to the function. */
b99bd4ef 4933
c19d1205 4934const pseudo_typeS md_pseudo_table[] =
b99bd4ef 4935{
c19d1205
ZW
4936 /* Never called because '.req' does not start a line. */
4937 { "req", s_req, 0 },
dcbf9037
JB
4938 /* Following two are likewise never called. */
4939 { "dn", s_dn, 0 },
4940 { "qn", s_qn, 0 },
c19d1205
ZW
4941 { "unreq", s_unreq, 0 },
4942 { "bss", s_bss, 0 },
db2ed2e0 4943 { "align", s_align_ptwo, 2 },
c19d1205
ZW
4944 { "arm", s_arm, 0 },
4945 { "thumb", s_thumb, 0 },
4946 { "code", s_code, 0 },
4947 { "force_thumb", s_force_thumb, 0 },
4948 { "thumb_func", s_thumb_func, 0 },
4949 { "thumb_set", s_thumb_set, 0 },
4950 { "even", s_even, 0 },
4951 { "ltorg", s_ltorg, 0 },
4952 { "pool", s_ltorg, 0 },
4953 { "syntax", s_syntax, 0 },
8463be01
PB
4954 { "cpu", s_arm_cpu, 0 },
4955 { "arch", s_arm_arch, 0 },
7a1d4c38 4956 { "object_arch", s_arm_object_arch, 0 },
8463be01 4957 { "fpu", s_arm_fpu, 0 },
69133863 4958 { "arch_extension", s_arm_arch_extension, 0 },
c19d1205 4959#ifdef OBJ_ELF
c921be7d
NC
4960 { "word", s_arm_elf_cons, 4 },
4961 { "long", s_arm_elf_cons, 4 },
4962 { "inst.n", s_arm_elf_inst, 2 },
4963 { "inst.w", s_arm_elf_inst, 4 },
4964 { "inst", s_arm_elf_inst, 0 },
4965 { "rel31", s_arm_rel31, 0 },
c19d1205
ZW
4966 { "fnstart", s_arm_unwind_fnstart, 0 },
4967 { "fnend", s_arm_unwind_fnend, 0 },
4968 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4969 { "personality", s_arm_unwind_personality, 0 },
4970 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4971 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4972 { "save", s_arm_unwind_save, 0 },
fa073d69 4973 { "vsave", s_arm_unwind_save, 1 },
c19d1205
ZW
4974 { "movsp", s_arm_unwind_movsp, 0 },
4975 { "pad", s_arm_unwind_pad, 0 },
4976 { "setfp", s_arm_unwind_setfp, 0 },
4977 { "unwind_raw", s_arm_unwind_raw, 0 },
ee065d83 4978 { "eabi_attribute", s_arm_eabi_attribute, 0 },
0855e32b 4979 { "tlsdescseq", s_arm_tls_descseq, 0 },
c19d1205
ZW
4980#else
4981 { "word", cons, 4},
f0927246
NC
4982
4983 /* These are used for dwarf. */
4984 {"2byte", cons, 2},
4985 {"4byte", cons, 4},
4986 {"8byte", cons, 8},
4987 /* These are used for dwarf2. */
68d20676 4988 { "file", dwarf2_directive_file, 0 },
f0927246
NC
4989 { "loc", dwarf2_directive_loc, 0 },
4990 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
c19d1205
ZW
4991#endif
4992 { "extend", float_cons, 'x' },
4993 { "ldouble", float_cons, 'x' },
4994 { "packed", float_cons, 'p' },
f0927246
NC
4995#ifdef TE_PE
4996 {"secrel32", pe_directive_secrel, 0},
4997#endif
2e6976a8
DG
4998
4999 /* These are for compatibility with CodeComposer Studio. */
5000 {"ref", s_ccs_ref, 0},
5001 {"def", s_ccs_def, 0},
5002 {"asmfunc", s_ccs_asmfunc, 0},
5003 {"endasmfunc", s_ccs_endasmfunc, 0},
5004
c19d1205
ZW
5005 { 0, 0, 0 }
5006};
5007\f
5008/* Parser functions used exclusively in instruction operands. */
b99bd4ef 5009
c19d1205
ZW
5010/* Generic immediate-value read function for use in insn parsing.
5011 STR points to the beginning of the immediate (the leading #);
5012 VAL receives the value; if the value is outside [MIN, MAX]
5013 issue an error. PREFIX_OPT is true if the immediate prefix is
5014 optional. */
b99bd4ef 5015
c19d1205
ZW
5016static int
5017parse_immediate (char **str, int *val, int min, int max,
5018 bfd_boolean prefix_opt)
5019{
5020 expressionS exp;
0198d5e6 5021
c19d1205
ZW
5022 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
5023 if (exp.X_op != O_constant)
b99bd4ef 5024 {
c19d1205
ZW
5025 inst.error = _("constant expression required");
5026 return FAIL;
5027 }
b99bd4ef 5028
c19d1205
ZW
5029 if (exp.X_add_number < min || exp.X_add_number > max)
5030 {
5031 inst.error = _("immediate value out of range");
5032 return FAIL;
5033 }
b99bd4ef 5034
c19d1205
ZW
5035 *val = exp.X_add_number;
5036 return SUCCESS;
5037}
b99bd4ef 5038
5287ad62 5039/* Less-generic immediate-value read function with the possibility of loading a
036dc3f7 5040 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5287ad62
JB
5041 instructions. Puts the result directly in inst.operands[i]. */
5042
5043static int
8335d6aa
JW
5044parse_big_immediate (char **str, int i, expressionS *in_exp,
5045 bfd_boolean allow_symbol_p)
5287ad62
JB
5046{
5047 expressionS exp;
8335d6aa 5048 expressionS *exp_p = in_exp ? in_exp : &exp;
5287ad62
JB
5049 char *ptr = *str;
5050
8335d6aa 5051 my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG);
5287ad62 5052
8335d6aa 5053 if (exp_p->X_op == O_constant)
036dc3f7 5054 {
8335d6aa 5055 inst.operands[i].imm = exp_p->X_add_number & 0xffffffff;
036dc3f7
PB
5056 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5057 O_constant. We have to be careful not to break compilation for
5058 32-bit X_add_number, though. */
8335d6aa 5059 if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0)
036dc3f7 5060 {
8335d6aa
JW
5061 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5062 inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16)
5063 & 0xffffffff);
036dc3f7
PB
5064 inst.operands[i].regisimm = 1;
5065 }
5066 }
8335d6aa
JW
5067 else if (exp_p->X_op == O_big
5068 && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32)
5287ad62
JB
5069 {
5070 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
95b75c01 5071
5287ad62 5072 /* Bignums have their least significant bits in
477330fc
RM
5073 generic_bignum[0]. Make sure we put 32 bits in imm and
5074 32 bits in reg, in a (hopefully) portable way. */
9c2799c2 5075 gas_assert (parts != 0);
95b75c01
NC
5076
5077 /* Make sure that the number is not too big.
5078 PR 11972: Bignums can now be sign-extended to the
5079 size of a .octa so check that the out of range bits
5080 are all zero or all one. */
8335d6aa 5081 if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64)
95b75c01
NC
5082 {
5083 LITTLENUM_TYPE m = -1;
5084
5085 if (generic_bignum[parts * 2] != 0
5086 && generic_bignum[parts * 2] != m)
5087 return FAIL;
5088
8335d6aa 5089 for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++)
95b75c01
NC
5090 if (generic_bignum[j] != generic_bignum[j-1])
5091 return FAIL;
5092 }
5093
5287ad62
JB
5094 inst.operands[i].imm = 0;
5095 for (j = 0; j < parts; j++, idx++)
477330fc
RM
5096 inst.operands[i].imm |= generic_bignum[idx]
5097 << (LITTLENUM_NUMBER_OF_BITS * j);
5287ad62
JB
5098 inst.operands[i].reg = 0;
5099 for (j = 0; j < parts; j++, idx++)
477330fc
RM
5100 inst.operands[i].reg |= generic_bignum[idx]
5101 << (LITTLENUM_NUMBER_OF_BITS * j);
5287ad62
JB
5102 inst.operands[i].regisimm = 1;
5103 }
8335d6aa 5104 else if (!(exp_p->X_op == O_symbol && allow_symbol_p))
5287ad62 5105 return FAIL;
5f4273c7 5106
5287ad62
JB
5107 *str = ptr;
5108
5109 return SUCCESS;
5110}
5111
c19d1205
ZW
5112/* Returns the pseudo-register number of an FPA immediate constant,
5113 or FAIL if there isn't a valid constant here. */
b99bd4ef 5114
c19d1205
ZW
5115static int
5116parse_fpa_immediate (char ** str)
5117{
5118 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5119 char * save_in;
5120 expressionS exp;
5121 int i;
5122 int j;
b99bd4ef 5123
c19d1205
ZW
5124 /* First try and match exact strings, this is to guarantee
5125 that some formats will work even for cross assembly. */
b99bd4ef 5126
c19d1205
ZW
5127 for (i = 0; fp_const[i]; i++)
5128 {
5129 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
b99bd4ef 5130 {
c19d1205 5131 char *start = *str;
b99bd4ef 5132
c19d1205
ZW
5133 *str += strlen (fp_const[i]);
5134 if (is_end_of_line[(unsigned char) **str])
5135 return i + 8;
5136 *str = start;
5137 }
5138 }
b99bd4ef 5139
c19d1205
ZW
5140 /* Just because we didn't get a match doesn't mean that the constant
5141 isn't valid, just that it is in a format that we don't
5142 automatically recognize. Try parsing it with the standard
5143 expression routines. */
b99bd4ef 5144
c19d1205 5145 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
b99bd4ef 5146
c19d1205
ZW
5147 /* Look for a raw floating point number. */
5148 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
5149 && is_end_of_line[(unsigned char) *save_in])
5150 {
5151 for (i = 0; i < NUM_FLOAT_VALS; i++)
5152 {
5153 for (j = 0; j < MAX_LITTLENUMS; j++)
b99bd4ef 5154 {
c19d1205
ZW
5155 if (words[j] != fp_values[i][j])
5156 break;
b99bd4ef
NC
5157 }
5158
c19d1205 5159 if (j == MAX_LITTLENUMS)
b99bd4ef 5160 {
c19d1205
ZW
5161 *str = save_in;
5162 return i + 8;
b99bd4ef
NC
5163 }
5164 }
5165 }
b99bd4ef 5166
c19d1205
ZW
5167 /* Try and parse a more complex expression, this will probably fail
5168 unless the code uses a floating point prefix (eg "0f"). */
5169 save_in = input_line_pointer;
5170 input_line_pointer = *str;
5171 if (expression (&exp) == absolute_section
5172 && exp.X_op == O_big
5173 && exp.X_add_number < 0)
5174 {
5175 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5176 Ditto for 15. */
ba592044
AM
5177#define X_PRECISION 5
5178#define E_PRECISION 15L
5179 if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0)
c19d1205
ZW
5180 {
5181 for (i = 0; i < NUM_FLOAT_VALS; i++)
5182 {
5183 for (j = 0; j < MAX_LITTLENUMS; j++)
5184 {
5185 if (words[j] != fp_values[i][j])
5186 break;
5187 }
b99bd4ef 5188
c19d1205
ZW
5189 if (j == MAX_LITTLENUMS)
5190 {
5191 *str = input_line_pointer;
5192 input_line_pointer = save_in;
5193 return i + 8;
5194 }
5195 }
5196 }
b99bd4ef
NC
5197 }
5198
c19d1205
ZW
5199 *str = input_line_pointer;
5200 input_line_pointer = save_in;
5201 inst.error = _("invalid FPA immediate expression");
5202 return FAIL;
b99bd4ef
NC
5203}
5204
136da414
JB
5205/* Returns 1 if a number has "quarter-precision" float format
5206 0baBbbbbbc defgh000 00000000 00000000. */
5207
5208static int
5209is_quarter_float (unsigned imm)
5210{
5211 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
5212 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
5213}
5214
aacf0b33
KT
5215
5216/* Detect the presence of a floating point or integer zero constant,
5217 i.e. #0.0 or #0. */
5218
5219static bfd_boolean
5220parse_ifimm_zero (char **in)
5221{
5222 int error_code;
5223
5224 if (!is_immediate_prefix (**in))
3c6452ae
TP
5225 {
5226 /* In unified syntax, all prefixes are optional. */
5227 if (!unified_syntax)
5228 return FALSE;
5229 }
5230 else
5231 ++*in;
0900a05b
JW
5232
5233 /* Accept #0x0 as a synonym for #0. */
5234 if (strncmp (*in, "0x", 2) == 0)
5235 {
5236 int val;
5237 if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL)
5238 return FALSE;
5239 return TRUE;
5240 }
5241
aacf0b33
KT
5242 error_code = atof_generic (in, ".", EXP_CHARS,
5243 &generic_floating_point_number);
5244
5245 if (!error_code
5246 && generic_floating_point_number.sign == '+'
5247 && (generic_floating_point_number.low
5248 > generic_floating_point_number.leader))
5249 return TRUE;
5250
5251 return FALSE;
5252}
5253
136da414
JB
5254/* Parse an 8-bit "quarter-precision" floating point number of the form:
5255 0baBbbbbbc defgh000 00000000 00000000.
c96612cc
JB
5256 The zero and minus-zero cases need special handling, since they can't be
5257 encoded in the "quarter-precision" float format, but can nonetheless be
5258 loaded as integer constants. */
136da414
JB
5259
5260static unsigned
5261parse_qfloat_immediate (char **ccp, int *immed)
5262{
5263 char *str = *ccp;
c96612cc 5264 char *fpnum;
136da414 5265 LITTLENUM_TYPE words[MAX_LITTLENUMS];
c96612cc 5266 int found_fpchar = 0;
5f4273c7 5267
136da414 5268 skip_past_char (&str, '#');
5f4273c7 5269
c96612cc
JB
5270 /* We must not accidentally parse an integer as a floating-point number. Make
5271 sure that the value we parse is not an integer by checking for special
5272 characters '.' or 'e'.
5273 FIXME: This is a horrible hack, but doing better is tricky because type
5274 information isn't in a very usable state at parse time. */
5275 fpnum = str;
5276 skip_whitespace (fpnum);
5277
5278 if (strncmp (fpnum, "0x", 2) == 0)
5279 return FAIL;
5280 else
5281 {
5282 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
477330fc
RM
5283 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
5284 {
5285 found_fpchar = 1;
5286 break;
5287 }
c96612cc
JB
5288
5289 if (!found_fpchar)
477330fc 5290 return FAIL;
c96612cc 5291 }
5f4273c7 5292
136da414
JB
5293 if ((str = atof_ieee (str, 's', words)) != NULL)
5294 {
5295 unsigned fpword = 0;
5296 int i;
5f4273c7 5297
136da414
JB
5298 /* Our FP word must be 32 bits (single-precision FP). */
5299 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
477330fc
RM
5300 {
5301 fpword <<= LITTLENUM_NUMBER_OF_BITS;
5302 fpword |= words[i];
5303 }
5f4273c7 5304
c96612cc 5305 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
477330fc 5306 *immed = fpword;
136da414 5307 else
477330fc 5308 return FAIL;
136da414
JB
5309
5310 *ccp = str;
5f4273c7 5311
136da414
JB
5312 return SUCCESS;
5313 }
5f4273c7 5314
136da414
JB
5315 return FAIL;
5316}
5317
c19d1205
ZW
5318/* Shift operands. */
5319enum shift_kind
b99bd4ef 5320{
f5f10c66 5321 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX, SHIFT_UXTW
c19d1205 5322};
b99bd4ef 5323
c19d1205
ZW
5324struct asm_shift_name
5325{
5326 const char *name;
5327 enum shift_kind kind;
5328};
b99bd4ef 5329
c19d1205
ZW
5330/* Third argument to parse_shift. */
5331enum parse_shift_mode
5332{
5333 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
5334 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
5335 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
5336 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
5337 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
f5f10c66 5338 SHIFT_UXTW_IMMEDIATE /* Shift must be UXTW immediate. */
c19d1205 5339};
b99bd4ef 5340
c19d1205
ZW
5341/* Parse a <shift> specifier on an ARM data processing instruction.
5342 This has three forms:
b99bd4ef 5343
c19d1205
ZW
5344 (LSL|LSR|ASL|ASR|ROR) Rs
5345 (LSL|LSR|ASL|ASR|ROR) #imm
5346 RRX
b99bd4ef 5347
c19d1205
ZW
5348 Note that ASL is assimilated to LSL in the instruction encoding, and
5349 RRX to ROR #0 (which cannot be written as such). */
b99bd4ef 5350
c19d1205
ZW
5351static int
5352parse_shift (char **str, int i, enum parse_shift_mode mode)
b99bd4ef 5353{
c19d1205
ZW
5354 const struct asm_shift_name *shift_name;
5355 enum shift_kind shift;
5356 char *s = *str;
5357 char *p = s;
5358 int reg;
b99bd4ef 5359
c19d1205
ZW
5360 for (p = *str; ISALPHA (*p); p++)
5361 ;
b99bd4ef 5362
c19d1205 5363 if (p == *str)
b99bd4ef 5364 {
c19d1205
ZW
5365 inst.error = _("shift expression expected");
5366 return FAIL;
b99bd4ef
NC
5367 }
5368
21d799b5 5369 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
477330fc 5370 p - *str);
c19d1205
ZW
5371
5372 if (shift_name == NULL)
b99bd4ef 5373 {
c19d1205
ZW
5374 inst.error = _("shift expression expected");
5375 return FAIL;
b99bd4ef
NC
5376 }
5377
c19d1205 5378 shift = shift_name->kind;
b99bd4ef 5379
c19d1205
ZW
5380 switch (mode)
5381 {
5382 case NO_SHIFT_RESTRICT:
f5f10c66
AV
5383 case SHIFT_IMMEDIATE:
5384 if (shift == SHIFT_UXTW)
5385 {
5386 inst.error = _("'UXTW' not allowed here");
5387 return FAIL;
5388 }
5389 break;
b99bd4ef 5390
c19d1205
ZW
5391 case SHIFT_LSL_OR_ASR_IMMEDIATE:
5392 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
5393 {
5394 inst.error = _("'LSL' or 'ASR' required");
5395 return FAIL;
5396 }
5397 break;
b99bd4ef 5398
c19d1205
ZW
5399 case SHIFT_LSL_IMMEDIATE:
5400 if (shift != SHIFT_LSL)
5401 {
5402 inst.error = _("'LSL' required");
5403 return FAIL;
5404 }
5405 break;
b99bd4ef 5406
c19d1205
ZW
5407 case SHIFT_ASR_IMMEDIATE:
5408 if (shift != SHIFT_ASR)
5409 {
5410 inst.error = _("'ASR' required");
5411 return FAIL;
5412 }
5413 break;
f5f10c66
AV
5414 case SHIFT_UXTW_IMMEDIATE:
5415 if (shift != SHIFT_UXTW)
5416 {
5417 inst.error = _("'UXTW' required");
5418 return FAIL;
5419 }
5420 break;
b99bd4ef 5421
c19d1205
ZW
5422 default: abort ();
5423 }
b99bd4ef 5424
c19d1205
ZW
5425 if (shift != SHIFT_RRX)
5426 {
5427 /* Whitespace can appear here if the next thing is a bare digit. */
5428 skip_whitespace (p);
b99bd4ef 5429
c19d1205 5430 if (mode == NO_SHIFT_RESTRICT
dcbf9037 5431 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
c19d1205
ZW
5432 {
5433 inst.operands[i].imm = reg;
5434 inst.operands[i].immisreg = 1;
5435 }
e2b0ab59 5436 else if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
c19d1205
ZW
5437 return FAIL;
5438 }
5439 inst.operands[i].shift_kind = shift;
5440 inst.operands[i].shifted = 1;
5441 *str = p;
5442 return SUCCESS;
b99bd4ef
NC
5443}
5444
c19d1205 5445/* Parse a <shifter_operand> for an ARM data processing instruction:
b99bd4ef 5446
c19d1205
ZW
5447 #<immediate>
5448 #<immediate>, <rotate>
5449 <Rm>
5450 <Rm>, <shift>
b99bd4ef 5451
c19d1205
ZW
5452 where <shift> is defined by parse_shift above, and <rotate> is a
5453 multiple of 2 between 0 and 30. Validation of immediate operands
55cf6793 5454 is deferred to md_apply_fix. */
b99bd4ef 5455
c19d1205
ZW
5456static int
5457parse_shifter_operand (char **str, int i)
5458{
5459 int value;
91d6fa6a 5460 expressionS exp;
b99bd4ef 5461
dcbf9037 5462 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
c19d1205
ZW
5463 {
5464 inst.operands[i].reg = value;
5465 inst.operands[i].isreg = 1;
b99bd4ef 5466
c19d1205 5467 /* parse_shift will override this if appropriate */
e2b0ab59
AV
5468 inst.relocs[0].exp.X_op = O_constant;
5469 inst.relocs[0].exp.X_add_number = 0;
b99bd4ef 5470
c19d1205
ZW
5471 if (skip_past_comma (str) == FAIL)
5472 return SUCCESS;
b99bd4ef 5473
c19d1205
ZW
5474 /* Shift operation on register. */
5475 return parse_shift (str, i, NO_SHIFT_RESTRICT);
b99bd4ef
NC
5476 }
5477
e2b0ab59 5478 if (my_get_expression (&inst.relocs[0].exp, str, GE_IMM_PREFIX))
c19d1205 5479 return FAIL;
b99bd4ef 5480
c19d1205 5481 if (skip_past_comma (str) == SUCCESS)
b99bd4ef 5482 {
c19d1205 5483 /* #x, y -- ie explicit rotation by Y. */
91d6fa6a 5484 if (my_get_expression (&exp, str, GE_NO_PREFIX))
c19d1205 5485 return FAIL;
b99bd4ef 5486
e2b0ab59 5487 if (exp.X_op != O_constant || inst.relocs[0].exp.X_op != O_constant)
c19d1205
ZW
5488 {
5489 inst.error = _("constant expression expected");
5490 return FAIL;
5491 }
b99bd4ef 5492
91d6fa6a 5493 value = exp.X_add_number;
c19d1205
ZW
5494 if (value < 0 || value > 30 || value % 2 != 0)
5495 {
5496 inst.error = _("invalid rotation");
5497 return FAIL;
5498 }
e2b0ab59
AV
5499 if (inst.relocs[0].exp.X_add_number < 0
5500 || inst.relocs[0].exp.X_add_number > 255)
c19d1205
ZW
5501 {
5502 inst.error = _("invalid constant");
5503 return FAIL;
5504 }
09d92015 5505
a415b1cd 5506 /* Encode as specified. */
e2b0ab59 5507 inst.operands[i].imm = inst.relocs[0].exp.X_add_number | value << 7;
a415b1cd 5508 return SUCCESS;
09d92015
MM
5509 }
5510
e2b0ab59
AV
5511 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
5512 inst.relocs[0].pc_rel = 0;
c19d1205 5513 return SUCCESS;
09d92015
MM
5514}
5515
4962c51a
MS
5516/* Group relocation information. Each entry in the table contains the
5517 textual name of the relocation as may appear in assembler source
5518 and must end with a colon.
5519 Along with this textual name are the relocation codes to be used if
5520 the corresponding instruction is an ALU instruction (ADD or SUB only),
5521 an LDR, an LDRS, or an LDC. */
5522
5523struct group_reloc_table_entry
5524{
5525 const char *name;
5526 int alu_code;
5527 int ldr_code;
5528 int ldrs_code;
5529 int ldc_code;
5530};
5531
5532typedef enum
5533{
5534 /* Varieties of non-ALU group relocation. */
5535
5536 GROUP_LDR,
5537 GROUP_LDRS,
35c228db
AV
5538 GROUP_LDC,
5539 GROUP_MVE
4962c51a
MS
5540} group_reloc_type;
5541
5542static struct group_reloc_table_entry group_reloc_table[] =
5543 { /* Program counter relative: */
5544 { "pc_g0_nc",
5545 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
5546 0, /* LDR */
5547 0, /* LDRS */
5548 0 }, /* LDC */
5549 { "pc_g0",
5550 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
5551 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
5552 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
5553 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
5554 { "pc_g1_nc",
5555 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
5556 0, /* LDR */
5557 0, /* LDRS */
5558 0 }, /* LDC */
5559 { "pc_g1",
5560 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
5561 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
5562 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
5563 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
5564 { "pc_g2",
5565 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
5566 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
5567 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
5568 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
5569 /* Section base relative */
5570 { "sb_g0_nc",
5571 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
5572 0, /* LDR */
5573 0, /* LDRS */
5574 0 }, /* LDC */
5575 { "sb_g0",
5576 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
5577 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
5578 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
5579 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
5580 { "sb_g1_nc",
5581 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
5582 0, /* LDR */
5583 0, /* LDRS */
5584 0 }, /* LDC */
5585 { "sb_g1",
5586 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
5587 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
5588 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5589 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5590 { "sb_g2",
5591 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5592 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5593 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
72d98d16
MG
5594 BFD_RELOC_ARM_LDC_SB_G2 }, /* LDC */
5595 /* Absolute thumb alu relocations. */
5596 { "lower0_7",
5597 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC,/* ALU. */
5598 0, /* LDR. */
5599 0, /* LDRS. */
5600 0 }, /* LDC. */
5601 { "lower8_15",
5602 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC,/* ALU. */
5603 0, /* LDR. */
5604 0, /* LDRS. */
5605 0 }, /* LDC. */
5606 { "upper0_7",
5607 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC,/* ALU. */
5608 0, /* LDR. */
5609 0, /* LDRS. */
5610 0 }, /* LDC. */
5611 { "upper8_15",
5612 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC,/* ALU. */
5613 0, /* LDR. */
5614 0, /* LDRS. */
5615 0 } }; /* LDC. */
4962c51a
MS
5616
5617/* Given the address of a pointer pointing to the textual name of a group
5618 relocation as may appear in assembler source, attempt to find its details
5619 in group_reloc_table. The pointer will be updated to the character after
5620 the trailing colon. On failure, FAIL will be returned; SUCCESS
5621 otherwise. On success, *entry will be updated to point at the relevant
5622 group_reloc_table entry. */
5623
5624static int
5625find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5626{
5627 unsigned int i;
5628 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5629 {
5630 int length = strlen (group_reloc_table[i].name);
5631
5f4273c7
NC
5632 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5633 && (*str)[length] == ':')
477330fc
RM
5634 {
5635 *out = &group_reloc_table[i];
5636 *str += (length + 1);
5637 return SUCCESS;
5638 }
4962c51a
MS
5639 }
5640
5641 return FAIL;
5642}
5643
5644/* Parse a <shifter_operand> for an ARM data processing instruction
5645 (as for parse_shifter_operand) where group relocations are allowed:
5646
5647 #<immediate>
5648 #<immediate>, <rotate>
5649 #:<group_reloc>:<expression>
5650 <Rm>
5651 <Rm>, <shift>
5652
5653 where <group_reloc> is one of the strings defined in group_reloc_table.
5654 The hashes are optional.
5655
5656 Everything else is as for parse_shifter_operand. */
5657
5658static parse_operand_result
5659parse_shifter_operand_group_reloc (char **str, int i)
5660{
5661 /* Determine if we have the sequence of characters #: or just :
5662 coming next. If we do, then we check for a group relocation.
5663 If we don't, punt the whole lot to parse_shifter_operand. */
5664
5665 if (((*str)[0] == '#' && (*str)[1] == ':')
5666 || (*str)[0] == ':')
5667 {
5668 struct group_reloc_table_entry *entry;
5669
5670 if ((*str)[0] == '#')
477330fc 5671 (*str) += 2;
4962c51a 5672 else
477330fc 5673 (*str)++;
4962c51a
MS
5674
5675 /* Try to parse a group relocation. Anything else is an error. */
5676 if (find_group_reloc_table_entry (str, &entry) == FAIL)
477330fc
RM
5677 {
5678 inst.error = _("unknown group relocation");
5679 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5680 }
4962c51a
MS
5681
5682 /* We now have the group relocation table entry corresponding to
477330fc 5683 the name in the assembler source. Next, we parse the expression. */
e2b0ab59 5684 if (my_get_expression (&inst.relocs[0].exp, str, GE_NO_PREFIX))
477330fc 5685 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4962c51a
MS
5686
5687 /* Record the relocation type (always the ALU variant here). */
e2b0ab59
AV
5688 inst.relocs[0].type = (bfd_reloc_code_real_type) entry->alu_code;
5689 gas_assert (inst.relocs[0].type != 0);
4962c51a
MS
5690
5691 return PARSE_OPERAND_SUCCESS;
5692 }
5693 else
5694 return parse_shifter_operand (str, i) == SUCCESS
477330fc 5695 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
4962c51a
MS
5696
5697 /* Never reached. */
5698}
5699
8e560766
MGD
5700/* Parse a Neon alignment expression. Information is written to
5701 inst.operands[i]. We assume the initial ':' has been skipped.
fa94de6b 5702
8e560766
MGD
5703 align .imm = align << 8, .immisalign=1, .preind=0 */
5704static parse_operand_result
5705parse_neon_alignment (char **str, int i)
5706{
5707 char *p = *str;
5708 expressionS exp;
5709
5710 my_get_expression (&exp, &p, GE_NO_PREFIX);
5711
5712 if (exp.X_op != O_constant)
5713 {
5714 inst.error = _("alignment must be constant");
5715 return PARSE_OPERAND_FAIL;
5716 }
5717
5718 inst.operands[i].imm = exp.X_add_number << 8;
5719 inst.operands[i].immisalign = 1;
5720 /* Alignments are not pre-indexes. */
5721 inst.operands[i].preind = 0;
5722
5723 *str = p;
5724 return PARSE_OPERAND_SUCCESS;
5725}
5726
c19d1205 5727/* Parse all forms of an ARM address expression. Information is written
e2b0ab59 5728 to inst.operands[i] and/or inst.relocs[0].
09d92015 5729
c19d1205 5730 Preindexed addressing (.preind=1):
09d92015 5731
e2b0ab59 5732 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
c19d1205
ZW
5733 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5734 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
e2b0ab59 5735 .shift_kind=shift .relocs[0].exp=shift_imm
09d92015 5736
c19d1205 5737 These three may have a trailing ! which causes .writeback to be set also.
09d92015 5738
c19d1205 5739 Postindexed addressing (.postind=1, .writeback=1):
09d92015 5740
e2b0ab59 5741 [Rn], #offset .reg=Rn .relocs[0].exp=offset
c19d1205
ZW
5742 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5743 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
e2b0ab59 5744 .shift_kind=shift .relocs[0].exp=shift_imm
09d92015 5745
c19d1205 5746 Unindexed addressing (.preind=0, .postind=0):
09d92015 5747
c19d1205 5748 [Rn], {option} .reg=Rn .imm=option .immisreg=0
09d92015 5749
c19d1205 5750 Other:
09d92015 5751
c19d1205 5752 [Rn]{!} shorthand for [Rn,#0]{!}
e2b0ab59
AV
5753 =immediate .isreg=0 .relocs[0].exp=immediate
5754 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
09d92015 5755
c19d1205 5756 It is the caller's responsibility to check for addressing modes not
e2b0ab59 5757 supported by the instruction, and to set inst.relocs[0].type. */
c19d1205 5758
4962c51a
MS
5759static parse_operand_result
5760parse_address_main (char **str, int i, int group_relocations,
477330fc 5761 group_reloc_type group_type)
09d92015 5762{
c19d1205
ZW
5763 char *p = *str;
5764 int reg;
09d92015 5765
c19d1205 5766 if (skip_past_char (&p, '[') == FAIL)
09d92015 5767 {
c19d1205
ZW
5768 if (skip_past_char (&p, '=') == FAIL)
5769 {
974da60d 5770 /* Bare address - translate to PC-relative offset. */
e2b0ab59 5771 inst.relocs[0].pc_rel = 1;
c19d1205
ZW
5772 inst.operands[i].reg = REG_PC;
5773 inst.operands[i].isreg = 1;
5774 inst.operands[i].preind = 1;
09d92015 5775
e2b0ab59 5776 if (my_get_expression (&inst.relocs[0].exp, &p, GE_OPT_PREFIX_BIG))
8335d6aa
JW
5777 return PARSE_OPERAND_FAIL;
5778 }
e2b0ab59 5779 else if (parse_big_immediate (&p, i, &inst.relocs[0].exp,
8335d6aa 5780 /*allow_symbol_p=*/TRUE))
4962c51a 5781 return PARSE_OPERAND_FAIL;
09d92015 5782
c19d1205 5783 *str = p;
4962c51a 5784 return PARSE_OPERAND_SUCCESS;
09d92015
MM
5785 }
5786
8ab8155f
NC
5787 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5788 skip_whitespace (p);
5789
f5f10c66
AV
5790 if (group_type == GROUP_MVE)
5791 {
5792 enum arm_reg_type rtype = REG_TYPE_MQ;
5793 struct neon_type_el et;
5794 if ((reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
5795 {
5796 inst.operands[i].isquad = 1;
5797 }
5798 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5799 {
5800 inst.error = BAD_ADDR_MODE;
5801 return PARSE_OPERAND_FAIL;
5802 }
5803 }
5804 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
09d92015 5805 {
35c228db
AV
5806 if (group_type == GROUP_MVE)
5807 inst.error = BAD_ADDR_MODE;
5808 else
5809 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
4962c51a 5810 return PARSE_OPERAND_FAIL;
09d92015 5811 }
c19d1205
ZW
5812 inst.operands[i].reg = reg;
5813 inst.operands[i].isreg = 1;
09d92015 5814
c19d1205 5815 if (skip_past_comma (&p) == SUCCESS)
09d92015 5816 {
c19d1205 5817 inst.operands[i].preind = 1;
09d92015 5818
c19d1205
ZW
5819 if (*p == '+') p++;
5820 else if (*p == '-') p++, inst.operands[i].negative = 1;
5821
f5f10c66
AV
5822 enum arm_reg_type rtype = REG_TYPE_MQ;
5823 struct neon_type_el et;
5824 if (group_type == GROUP_MVE
5825 && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
5826 {
5827 inst.operands[i].immisreg = 2;
5828 inst.operands[i].imm = reg;
5829
5830 if (skip_past_comma (&p) == SUCCESS)
5831 {
5832 if (parse_shift (&p, i, SHIFT_UXTW_IMMEDIATE) == SUCCESS)
5833 {
5834 inst.operands[i].imm |= inst.relocs[0].exp.X_add_number << 5;
5835 inst.relocs[0].exp.X_add_number = 0;
5836 }
5837 else
5838 return PARSE_OPERAND_FAIL;
5839 }
5840 }
5841 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
09d92015 5842 {
c19d1205
ZW
5843 inst.operands[i].imm = reg;
5844 inst.operands[i].immisreg = 1;
5845
5846 if (skip_past_comma (&p) == SUCCESS)
5847 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4962c51a 5848 return PARSE_OPERAND_FAIL;
c19d1205 5849 }
5287ad62 5850 else if (skip_past_char (&p, ':') == SUCCESS)
8e560766
MGD
5851 {
5852 /* FIXME: '@' should be used here, but it's filtered out by generic
5853 code before we get to see it here. This may be subject to
5854 change. */
5855 parse_operand_result result = parse_neon_alignment (&p, i);
fa94de6b 5856
8e560766
MGD
5857 if (result != PARSE_OPERAND_SUCCESS)
5858 return result;
5859 }
c19d1205
ZW
5860 else
5861 {
5862 if (inst.operands[i].negative)
5863 {
5864 inst.operands[i].negative = 0;
5865 p--;
5866 }
4962c51a 5867
5f4273c7
NC
5868 if (group_relocations
5869 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
4962c51a
MS
5870 {
5871 struct group_reloc_table_entry *entry;
5872
477330fc
RM
5873 /* Skip over the #: or : sequence. */
5874 if (*p == '#')
5875 p += 2;
5876 else
5877 p++;
4962c51a
MS
5878
5879 /* Try to parse a group relocation. Anything else is an
477330fc 5880 error. */
4962c51a
MS
5881 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5882 {
5883 inst.error = _("unknown group relocation");
5884 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5885 }
5886
5887 /* We now have the group relocation table entry corresponding to
5888 the name in the assembler source. Next, we parse the
477330fc 5889 expression. */
e2b0ab59 5890 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
4962c51a
MS
5891 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5892
5893 /* Record the relocation type. */
477330fc
RM
5894 switch (group_type)
5895 {
5896 case GROUP_LDR:
e2b0ab59
AV
5897 inst.relocs[0].type
5898 = (bfd_reloc_code_real_type) entry->ldr_code;
477330fc 5899 break;
4962c51a 5900
477330fc 5901 case GROUP_LDRS:
e2b0ab59
AV
5902 inst.relocs[0].type
5903 = (bfd_reloc_code_real_type) entry->ldrs_code;
477330fc 5904 break;
4962c51a 5905
477330fc 5906 case GROUP_LDC:
e2b0ab59
AV
5907 inst.relocs[0].type
5908 = (bfd_reloc_code_real_type) entry->ldc_code;
477330fc 5909 break;
4962c51a 5910
477330fc
RM
5911 default:
5912 gas_assert (0);
5913 }
4962c51a 5914
e2b0ab59 5915 if (inst.relocs[0].type == 0)
4962c51a
MS
5916 {
5917 inst.error = _("this group relocation is not allowed on this instruction");
5918 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5919 }
477330fc
RM
5920 }
5921 else
26d97720
NS
5922 {
5923 char *q = p;
0198d5e6 5924
e2b0ab59 5925 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
26d97720
NS
5926 return PARSE_OPERAND_FAIL;
5927 /* If the offset is 0, find out if it's a +0 or -0. */
e2b0ab59
AV
5928 if (inst.relocs[0].exp.X_op == O_constant
5929 && inst.relocs[0].exp.X_add_number == 0)
26d97720
NS
5930 {
5931 skip_whitespace (q);
5932 if (*q == '#')
5933 {
5934 q++;
5935 skip_whitespace (q);
5936 }
5937 if (*q == '-')
5938 inst.operands[i].negative = 1;
5939 }
5940 }
09d92015
MM
5941 }
5942 }
8e560766
MGD
5943 else if (skip_past_char (&p, ':') == SUCCESS)
5944 {
5945 /* FIXME: '@' should be used here, but it's filtered out by generic code
5946 before we get to see it here. This may be subject to change. */
5947 parse_operand_result result = parse_neon_alignment (&p, i);
fa94de6b 5948
8e560766
MGD
5949 if (result != PARSE_OPERAND_SUCCESS)
5950 return result;
5951 }
09d92015 5952
c19d1205 5953 if (skip_past_char (&p, ']') == FAIL)
09d92015 5954 {
c19d1205 5955 inst.error = _("']' expected");
4962c51a 5956 return PARSE_OPERAND_FAIL;
09d92015
MM
5957 }
5958
c19d1205
ZW
5959 if (skip_past_char (&p, '!') == SUCCESS)
5960 inst.operands[i].writeback = 1;
09d92015 5961
c19d1205 5962 else if (skip_past_comma (&p) == SUCCESS)
09d92015 5963 {
c19d1205
ZW
5964 if (skip_past_char (&p, '{') == SUCCESS)
5965 {
5966 /* [Rn], {expr} - unindexed, with option */
5967 if (parse_immediate (&p, &inst.operands[i].imm,
ca3f61f7 5968 0, 255, TRUE) == FAIL)
4962c51a 5969 return PARSE_OPERAND_FAIL;
09d92015 5970
c19d1205
ZW
5971 if (skip_past_char (&p, '}') == FAIL)
5972 {
5973 inst.error = _("'}' expected at end of 'option' field");
4962c51a 5974 return PARSE_OPERAND_FAIL;
c19d1205
ZW
5975 }
5976 if (inst.operands[i].preind)
5977 {
5978 inst.error = _("cannot combine index with option");
4962c51a 5979 return PARSE_OPERAND_FAIL;
c19d1205
ZW
5980 }
5981 *str = p;
4962c51a 5982 return PARSE_OPERAND_SUCCESS;
09d92015 5983 }
c19d1205
ZW
5984 else
5985 {
5986 inst.operands[i].postind = 1;
5987 inst.operands[i].writeback = 1;
09d92015 5988
c19d1205
ZW
5989 if (inst.operands[i].preind)
5990 {
5991 inst.error = _("cannot combine pre- and post-indexing");
4962c51a 5992 return PARSE_OPERAND_FAIL;
c19d1205 5993 }
09d92015 5994
c19d1205
ZW
5995 if (*p == '+') p++;
5996 else if (*p == '-') p++, inst.operands[i].negative = 1;
a737bd4d 5997
f5f10c66
AV
5998 enum arm_reg_type rtype = REG_TYPE_MQ;
5999 struct neon_type_el et;
6000 if (group_type == GROUP_MVE
6001 && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
6002 {
6003 inst.operands[i].immisreg = 2;
6004 inst.operands[i].imm = reg;
6005 }
6006 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
c19d1205 6007 {
477330fc
RM
6008 /* We might be using the immediate for alignment already. If we
6009 are, OR the register number into the low-order bits. */
6010 if (inst.operands[i].immisalign)
6011 inst.operands[i].imm |= reg;
6012 else
6013 inst.operands[i].imm = reg;
c19d1205 6014 inst.operands[i].immisreg = 1;
a737bd4d 6015
c19d1205
ZW
6016 if (skip_past_comma (&p) == SUCCESS)
6017 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4962c51a 6018 return PARSE_OPERAND_FAIL;
c19d1205
ZW
6019 }
6020 else
6021 {
26d97720 6022 char *q = p;
0198d5e6 6023
c19d1205
ZW
6024 if (inst.operands[i].negative)
6025 {
6026 inst.operands[i].negative = 0;
6027 p--;
6028 }
e2b0ab59 6029 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
4962c51a 6030 return PARSE_OPERAND_FAIL;
26d97720 6031 /* If the offset is 0, find out if it's a +0 or -0. */
e2b0ab59
AV
6032 if (inst.relocs[0].exp.X_op == O_constant
6033 && inst.relocs[0].exp.X_add_number == 0)
26d97720
NS
6034 {
6035 skip_whitespace (q);
6036 if (*q == '#')
6037 {
6038 q++;
6039 skip_whitespace (q);
6040 }
6041 if (*q == '-')
6042 inst.operands[i].negative = 1;
6043 }
c19d1205
ZW
6044 }
6045 }
a737bd4d
NC
6046 }
6047
c19d1205
ZW
6048 /* If at this point neither .preind nor .postind is set, we have a
6049 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6050 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
6051 {
6052 inst.operands[i].preind = 1;
e2b0ab59
AV
6053 inst.relocs[0].exp.X_op = O_constant;
6054 inst.relocs[0].exp.X_add_number = 0;
c19d1205
ZW
6055 }
6056 *str = p;
4962c51a
MS
6057 return PARSE_OPERAND_SUCCESS;
6058}
6059
6060static int
6061parse_address (char **str, int i)
6062{
21d799b5 6063 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
477330fc 6064 ? SUCCESS : FAIL;
4962c51a
MS
6065}
6066
6067static parse_operand_result
6068parse_address_group_reloc (char **str, int i, group_reloc_type type)
6069{
6070 return parse_address_main (str, i, 1, type);
a737bd4d
NC
6071}
6072
b6895b4f
PB
6073/* Parse an operand for a MOVW or MOVT instruction. */
6074static int
6075parse_half (char **str)
6076{
6077 char * p;
5f4273c7 6078
b6895b4f
PB
6079 p = *str;
6080 skip_past_char (&p, '#');
5f4273c7 6081 if (strncasecmp (p, ":lower16:", 9) == 0)
e2b0ab59 6082 inst.relocs[0].type = BFD_RELOC_ARM_MOVW;
b6895b4f 6083 else if (strncasecmp (p, ":upper16:", 9) == 0)
e2b0ab59 6084 inst.relocs[0].type = BFD_RELOC_ARM_MOVT;
b6895b4f 6085
e2b0ab59 6086 if (inst.relocs[0].type != BFD_RELOC_UNUSED)
b6895b4f
PB
6087 {
6088 p += 9;
5f4273c7 6089 skip_whitespace (p);
b6895b4f
PB
6090 }
6091
e2b0ab59 6092 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
b6895b4f
PB
6093 return FAIL;
6094
e2b0ab59 6095 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
b6895b4f 6096 {
e2b0ab59 6097 if (inst.relocs[0].exp.X_op != O_constant)
b6895b4f
PB
6098 {
6099 inst.error = _("constant expression expected");
6100 return FAIL;
6101 }
e2b0ab59
AV
6102 if (inst.relocs[0].exp.X_add_number < 0
6103 || inst.relocs[0].exp.X_add_number > 0xffff)
b6895b4f
PB
6104 {
6105 inst.error = _("immediate value out of range");
6106 return FAIL;
6107 }
6108 }
6109 *str = p;
6110 return SUCCESS;
6111}
6112
c19d1205 6113/* Miscellaneous. */
a737bd4d 6114
c19d1205
ZW
6115/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6116 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6117static int
d2cd1205 6118parse_psr (char **str, bfd_boolean lhs)
09d92015 6119{
c19d1205
ZW
6120 char *p;
6121 unsigned long psr_field;
62b3e311
PB
6122 const struct asm_psr *psr;
6123 char *start;
d2cd1205 6124 bfd_boolean is_apsr = FALSE;
ac7f631b 6125 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
09d92015 6126
a4482bb6
NC
6127 /* PR gas/12698: If the user has specified -march=all then m_profile will
6128 be TRUE, but we want to ignore it in this case as we are building for any
6129 CPU type, including non-m variants. */
823d2571 6130 if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
a4482bb6
NC
6131 m_profile = FALSE;
6132
c19d1205
ZW
6133 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6134 feature for ease of use and backwards compatibility. */
6135 p = *str;
62b3e311 6136 if (strncasecmp (p, "SPSR", 4) == 0)
d2cd1205
JB
6137 {
6138 if (m_profile)
6139 goto unsupported_psr;
fa94de6b 6140
d2cd1205
JB
6141 psr_field = SPSR_BIT;
6142 }
6143 else if (strncasecmp (p, "CPSR", 4) == 0)
6144 {
6145 if (m_profile)
6146 goto unsupported_psr;
6147
6148 psr_field = 0;
6149 }
6150 else if (strncasecmp (p, "APSR", 4) == 0)
6151 {
6152 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6153 and ARMv7-R architecture CPUs. */
6154 is_apsr = TRUE;
6155 psr_field = 0;
6156 }
6157 else if (m_profile)
62b3e311
PB
6158 {
6159 start = p;
6160 do
6161 p++;
6162 while (ISALNUM (*p) || *p == '_');
6163
d2cd1205
JB
6164 if (strncasecmp (start, "iapsr", 5) == 0
6165 || strncasecmp (start, "eapsr", 5) == 0
6166 || strncasecmp (start, "xpsr", 4) == 0
6167 || strncasecmp (start, "psr", 3) == 0)
6168 p = start + strcspn (start, "rR") + 1;
6169
21d799b5 6170 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
477330fc 6171 p - start);
d2cd1205 6172
62b3e311
PB
6173 if (!psr)
6174 return FAIL;
09d92015 6175
d2cd1205
JB
6176 /* If APSR is being written, a bitfield may be specified. Note that
6177 APSR itself is handled above. */
6178 if (psr->field <= 3)
6179 {
6180 psr_field = psr->field;
6181 is_apsr = TRUE;
6182 goto check_suffix;
6183 }
6184
62b3e311 6185 *str = p;
d2cd1205
JB
6186 /* M-profile MSR instructions have the mask field set to "10", except
6187 *PSR variants which modify APSR, which may use a different mask (and
6188 have been handled already). Do that by setting the PSR_f field
6189 here. */
6190 return psr->field | (lhs ? PSR_f : 0);
62b3e311 6191 }
d2cd1205
JB
6192 else
6193 goto unsupported_psr;
09d92015 6194
62b3e311 6195 p += 4;
d2cd1205 6196check_suffix:
c19d1205
ZW
6197 if (*p == '_')
6198 {
6199 /* A suffix follows. */
c19d1205
ZW
6200 p++;
6201 start = p;
a737bd4d 6202
c19d1205
ZW
6203 do
6204 p++;
6205 while (ISALNUM (*p) || *p == '_');
a737bd4d 6206
d2cd1205
JB
6207 if (is_apsr)
6208 {
6209 /* APSR uses a notation for bits, rather than fields. */
6210 unsigned int nzcvq_bits = 0;
6211 unsigned int g_bit = 0;
6212 char *bit;
fa94de6b 6213
d2cd1205
JB
6214 for (bit = start; bit != p; bit++)
6215 {
6216 switch (TOLOWER (*bit))
477330fc 6217 {
d2cd1205
JB
6218 case 'n':
6219 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
6220 break;
6221
6222 case 'z':
6223 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
6224 break;
6225
6226 case 'c':
6227 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
6228 break;
6229
6230 case 'v':
6231 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
6232 break;
fa94de6b 6233
d2cd1205
JB
6234 case 'q':
6235 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
6236 break;
fa94de6b 6237
d2cd1205
JB
6238 case 'g':
6239 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
6240 break;
fa94de6b 6241
d2cd1205
JB
6242 default:
6243 inst.error = _("unexpected bit specified after APSR");
6244 return FAIL;
6245 }
6246 }
fa94de6b 6247
d2cd1205
JB
6248 if (nzcvq_bits == 0x1f)
6249 psr_field |= PSR_f;
fa94de6b 6250
d2cd1205
JB
6251 if (g_bit == 0x1)
6252 {
6253 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
477330fc 6254 {
d2cd1205
JB
6255 inst.error = _("selected processor does not "
6256 "support DSP extension");
6257 return FAIL;
6258 }
6259
6260 psr_field |= PSR_s;
6261 }
fa94de6b 6262
d2cd1205
JB
6263 if ((nzcvq_bits & 0x20) != 0
6264 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
6265 || (g_bit & 0x2) != 0)
6266 {
6267 inst.error = _("bad bitmask specified after APSR");
6268 return FAIL;
6269 }
6270 }
6271 else
477330fc 6272 {
d2cd1205 6273 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
477330fc 6274 p - start);
d2cd1205 6275 if (!psr)
477330fc 6276 goto error;
a737bd4d 6277
d2cd1205
JB
6278 psr_field |= psr->field;
6279 }
a737bd4d 6280 }
c19d1205 6281 else
a737bd4d 6282 {
c19d1205
ZW
6283 if (ISALNUM (*p))
6284 goto error; /* Garbage after "[CS]PSR". */
6285
d2cd1205 6286 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
477330fc 6287 is deprecated, but allow it anyway. */
d2cd1205
JB
6288 if (is_apsr && lhs)
6289 {
6290 psr_field |= PSR_f;
6291 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6292 "deprecated"));
6293 }
6294 else if (!m_profile)
6295 /* These bits are never right for M-profile devices: don't set them
6296 (only code paths which read/write APSR reach here). */
6297 psr_field |= (PSR_c | PSR_f);
a737bd4d 6298 }
c19d1205
ZW
6299 *str = p;
6300 return psr_field;
a737bd4d 6301
d2cd1205
JB
6302 unsupported_psr:
6303 inst.error = _("selected processor does not support requested special "
6304 "purpose register");
6305 return FAIL;
6306
c19d1205
ZW
6307 error:
6308 inst.error = _("flag for {c}psr instruction expected");
6309 return FAIL;
a737bd4d
NC
6310}
6311
32c36c3c
AV
6312static int
6313parse_sys_vldr_vstr (char **str)
6314{
6315 unsigned i;
6316 int val = FAIL;
6317 struct {
6318 const char *name;
6319 int regl;
6320 int regh;
6321 } sysregs[] = {
6322 {"FPSCR", 0x1, 0x0},
6323 {"FPSCR_nzcvqc", 0x2, 0x0},
6324 {"VPR", 0x4, 0x1},
6325 {"P0", 0x5, 0x1},
6326 {"FPCXTNS", 0x6, 0x1},
6327 {"FPCXTS", 0x7, 0x1}
6328 };
6329 char *op_end = strchr (*str, ',');
6330 size_t op_strlen = op_end - *str;
6331
6332 for (i = 0; i < sizeof (sysregs) / sizeof (sysregs[0]); i++)
6333 {
6334 if (!strncmp (*str, sysregs[i].name, op_strlen))
6335 {
6336 val = sysregs[i].regl | (sysregs[i].regh << 3);
6337 *str = op_end;
6338 break;
6339 }
6340 }
6341
6342 return val;
6343}
6344
c19d1205
ZW
6345/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6346 value suitable for splatting into the AIF field of the instruction. */
a737bd4d 6347
c19d1205
ZW
6348static int
6349parse_cps_flags (char **str)
a737bd4d 6350{
c19d1205
ZW
6351 int val = 0;
6352 int saw_a_flag = 0;
6353 char *s = *str;
a737bd4d 6354
c19d1205
ZW
6355 for (;;)
6356 switch (*s++)
6357 {
6358 case '\0': case ',':
6359 goto done;
a737bd4d 6360
c19d1205
ZW
6361 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
6362 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
6363 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
a737bd4d 6364
c19d1205
ZW
6365 default:
6366 inst.error = _("unrecognized CPS flag");
6367 return FAIL;
6368 }
a737bd4d 6369
c19d1205
ZW
6370 done:
6371 if (saw_a_flag == 0)
a737bd4d 6372 {
c19d1205
ZW
6373 inst.error = _("missing CPS flags");
6374 return FAIL;
a737bd4d 6375 }
a737bd4d 6376
c19d1205
ZW
6377 *str = s - 1;
6378 return val;
a737bd4d
NC
6379}
6380
c19d1205
ZW
6381/* Parse an endian specifier ("BE" or "LE", case insensitive);
6382 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
a737bd4d
NC
6383
6384static int
c19d1205 6385parse_endian_specifier (char **str)
a737bd4d 6386{
c19d1205
ZW
6387 int little_endian;
6388 char *s = *str;
a737bd4d 6389
c19d1205
ZW
6390 if (strncasecmp (s, "BE", 2))
6391 little_endian = 0;
6392 else if (strncasecmp (s, "LE", 2))
6393 little_endian = 1;
6394 else
a737bd4d 6395 {
c19d1205 6396 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC
6397 return FAIL;
6398 }
6399
c19d1205 6400 if (ISALNUM (s[2]) || s[2] == '_')
a737bd4d 6401 {
c19d1205 6402 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC
6403 return FAIL;
6404 }
6405
c19d1205
ZW
6406 *str = s + 2;
6407 return little_endian;
6408}
a737bd4d 6409
c19d1205
ZW
6410/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6411 value suitable for poking into the rotate field of an sxt or sxta
6412 instruction, or FAIL on error. */
6413
6414static int
6415parse_ror (char **str)
6416{
6417 int rot;
6418 char *s = *str;
6419
6420 if (strncasecmp (s, "ROR", 3) == 0)
6421 s += 3;
6422 else
a737bd4d 6423 {
c19d1205 6424 inst.error = _("missing rotation field after comma");
a737bd4d
NC
6425 return FAIL;
6426 }
c19d1205
ZW
6427
6428 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
6429 return FAIL;
6430
6431 switch (rot)
a737bd4d 6432 {
c19d1205
ZW
6433 case 0: *str = s; return 0x0;
6434 case 8: *str = s; return 0x1;
6435 case 16: *str = s; return 0x2;
6436 case 24: *str = s; return 0x3;
6437
6438 default:
6439 inst.error = _("rotation can only be 0, 8, 16, or 24");
a737bd4d
NC
6440 return FAIL;
6441 }
c19d1205 6442}
a737bd4d 6443
c19d1205
ZW
6444/* Parse a conditional code (from conds[] below). The value returned is in the
6445 range 0 .. 14, or FAIL. */
6446static int
6447parse_cond (char **str)
6448{
c462b453 6449 char *q;
c19d1205 6450 const struct asm_cond *c;
c462b453
PB
6451 int n;
6452 /* Condition codes are always 2 characters, so matching up to
6453 3 characters is sufficient. */
6454 char cond[3];
a737bd4d 6455
c462b453
PB
6456 q = *str;
6457 n = 0;
6458 while (ISALPHA (*q) && n < 3)
6459 {
e07e6e58 6460 cond[n] = TOLOWER (*q);
c462b453
PB
6461 q++;
6462 n++;
6463 }
a737bd4d 6464
21d799b5 6465 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
c19d1205 6466 if (!c)
a737bd4d 6467 {
c19d1205 6468 inst.error = _("condition required");
a737bd4d
NC
6469 return FAIL;
6470 }
6471
c19d1205
ZW
6472 *str = q;
6473 return c->value;
6474}
6475
62b3e311
PB
6476/* Parse an option for a barrier instruction. Returns the encoding for the
6477 option, or FAIL. */
6478static int
6479parse_barrier (char **str)
6480{
6481 char *p, *q;
6482 const struct asm_barrier_opt *o;
6483
6484 p = q = *str;
6485 while (ISALPHA (*q))
6486 q++;
6487
21d799b5 6488 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
477330fc 6489 q - p);
62b3e311
PB
6490 if (!o)
6491 return FAIL;
6492
e797f7e0
MGD
6493 if (!mark_feature_used (&o->arch))
6494 return FAIL;
6495
62b3e311
PB
6496 *str = q;
6497 return o->value;
6498}
6499
92e90b6e
PB
6500/* Parse the operands of a table branch instruction. Similar to a memory
6501 operand. */
6502static int
6503parse_tb (char **str)
6504{
6505 char * p = *str;
6506 int reg;
6507
6508 if (skip_past_char (&p, '[') == FAIL)
ab1eb5fe
PB
6509 {
6510 inst.error = _("'[' expected");
6511 return FAIL;
6512 }
92e90b6e 6513
dcbf9037 6514 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
92e90b6e
PB
6515 {
6516 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6517 return FAIL;
6518 }
6519 inst.operands[0].reg = reg;
6520
6521 if (skip_past_comma (&p) == FAIL)
ab1eb5fe
PB
6522 {
6523 inst.error = _("',' expected");
6524 return FAIL;
6525 }
5f4273c7 6526
dcbf9037 6527 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
92e90b6e
PB
6528 {
6529 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6530 return FAIL;
6531 }
6532 inst.operands[0].imm = reg;
6533
6534 if (skip_past_comma (&p) == SUCCESS)
6535 {
6536 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
6537 return FAIL;
e2b0ab59 6538 if (inst.relocs[0].exp.X_add_number != 1)
92e90b6e
PB
6539 {
6540 inst.error = _("invalid shift");
6541 return FAIL;
6542 }
6543 inst.operands[0].shifted = 1;
6544 }
6545
6546 if (skip_past_char (&p, ']') == FAIL)
6547 {
6548 inst.error = _("']' expected");
6549 return FAIL;
6550 }
6551 *str = p;
6552 return SUCCESS;
6553}
6554
5287ad62
JB
6555/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6556 information on the types the operands can take and how they are encoded.
037e8744
JB
6557 Up to four operands may be read; this function handles setting the
6558 ".present" field for each read operand itself.
5287ad62
JB
6559 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6560 else returns FAIL. */
6561
6562static int
6563parse_neon_mov (char **str, int *which_operand)
6564{
6565 int i = *which_operand, val;
6566 enum arm_reg_type rtype;
6567 char *ptr = *str;
dcbf9037 6568 struct neon_type_el optype;
5f4273c7 6569
57785aa2
AV
6570 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6571 {
6572 /* Cases 17 or 19. */
6573 inst.operands[i].reg = val;
6574 inst.operands[i].isvec = 1;
6575 inst.operands[i].isscalar = 2;
6576 inst.operands[i].vectype = optype;
6577 inst.operands[i++].present = 1;
6578
6579 if (skip_past_comma (&ptr) == FAIL)
6580 goto wanted_comma;
6581
6582 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6583 {
6584 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6585 inst.operands[i].reg = val;
6586 inst.operands[i].isreg = 1;
6587 inst.operands[i].present = 1;
6588 }
6589 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6590 {
6591 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6592 inst.operands[i].reg = val;
6593 inst.operands[i].isvec = 1;
6594 inst.operands[i].isscalar = 2;
6595 inst.operands[i].vectype = optype;
6596 inst.operands[i++].present = 1;
6597
6598 if (skip_past_comma (&ptr) == FAIL)
6599 goto wanted_comma;
6600
6601 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6602 goto wanted_arm;
6603
6604 inst.operands[i].reg = val;
6605 inst.operands[i].isreg = 1;
6606 inst.operands[i++].present = 1;
6607
6608 if (skip_past_comma (&ptr) == FAIL)
6609 goto wanted_comma;
6610
6611 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6612 goto wanted_arm;
6613
6614 inst.operands[i].reg = val;
6615 inst.operands[i].isreg = 1;
6616 inst.operands[i].present = 1;
6617 }
6618 else
6619 {
6620 first_error (_("expected ARM or MVE vector register"));
6621 return FAIL;
6622 }
6623 }
6624 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL)
5287ad62
JB
6625 {
6626 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6627 inst.operands[i].reg = val;
6628 inst.operands[i].isscalar = 1;
dcbf9037 6629 inst.operands[i].vectype = optype;
5287ad62
JB
6630 inst.operands[i++].present = 1;
6631
6632 if (skip_past_comma (&ptr) == FAIL)
477330fc 6633 goto wanted_comma;
5f4273c7 6634
dcbf9037 6635 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
477330fc 6636 goto wanted_arm;
5f4273c7 6637
5287ad62
JB
6638 inst.operands[i].reg = val;
6639 inst.operands[i].isreg = 1;
6640 inst.operands[i].present = 1;
6641 }
57785aa2
AV
6642 else if (((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
6643 != FAIL)
6644 || ((val = arm_typed_reg_parse (&ptr, REG_TYPE_MQ, &rtype, &optype))
6645 != FAIL))
5287ad62
JB
6646 {
6647 /* Cases 0, 1, 2, 3, 5 (D only). */
6648 if (skip_past_comma (&ptr) == FAIL)
477330fc 6649 goto wanted_comma;
5f4273c7 6650
5287ad62
JB
6651 inst.operands[i].reg = val;
6652 inst.operands[i].isreg = 1;
6653 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
037e8744
JB
6654 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6655 inst.operands[i].isvec = 1;
dcbf9037 6656 inst.operands[i].vectype = optype;
5287ad62
JB
6657 inst.operands[i++].present = 1;
6658
dcbf9037 6659 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
477330fc
RM
6660 {
6661 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6662 Case 13: VMOV <Sd>, <Rm> */
6663 inst.operands[i].reg = val;
6664 inst.operands[i].isreg = 1;
6665 inst.operands[i].present = 1;
6666
6667 if (rtype == REG_TYPE_NQ)
6668 {
6669 first_error (_("can't use Neon quad register here"));
6670 return FAIL;
6671 }
6672 else if (rtype != REG_TYPE_VFS)
6673 {
6674 i++;
6675 if (skip_past_comma (&ptr) == FAIL)
6676 goto wanted_comma;
6677 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6678 goto wanted_arm;
6679 inst.operands[i].reg = val;
6680 inst.operands[i].isreg = 1;
6681 inst.operands[i].present = 1;
6682 }
6683 }
037e8744 6684 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
477330fc
RM
6685 &optype)) != FAIL)
6686 {
6687 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6688 Case 1: VMOV<c><q> <Dd>, <Dm>
6689 Case 8: VMOV.F32 <Sd>, <Sm>
6690 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6691
6692 inst.operands[i].reg = val;
6693 inst.operands[i].isreg = 1;
6694 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6695 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6696 inst.operands[i].isvec = 1;
6697 inst.operands[i].vectype = optype;
6698 inst.operands[i].present = 1;
6699
6700 if (skip_past_comma (&ptr) == SUCCESS)
6701 {
6702 /* Case 15. */
6703 i++;
6704
6705 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6706 goto wanted_arm;
6707
6708 inst.operands[i].reg = val;
6709 inst.operands[i].isreg = 1;
6710 inst.operands[i++].present = 1;
6711
6712 if (skip_past_comma (&ptr) == FAIL)
6713 goto wanted_comma;
6714
6715 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6716 goto wanted_arm;
6717
6718 inst.operands[i].reg = val;
6719 inst.operands[i].isreg = 1;
6720 inst.operands[i].present = 1;
6721 }
6722 }
4641781c 6723 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
477330fc
RM
6724 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6725 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6726 Case 10: VMOV.F32 <Sd>, #<imm>
6727 Case 11: VMOV.F64 <Dd>, #<imm> */
6728 inst.operands[i].immisfloat = 1;
8335d6aa
JW
6729 else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE)
6730 == SUCCESS)
477330fc
RM
6731 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6732 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6733 ;
5287ad62 6734 else
477330fc
RM
6735 {
6736 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6737 return FAIL;
6738 }
5287ad62 6739 }
dcbf9037 6740 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5287ad62 6741 {
57785aa2 6742 /* Cases 6, 7, 16, 18. */
5287ad62
JB
6743 inst.operands[i].reg = val;
6744 inst.operands[i].isreg = 1;
6745 inst.operands[i++].present = 1;
5f4273c7 6746
5287ad62 6747 if (skip_past_comma (&ptr) == FAIL)
477330fc 6748 goto wanted_comma;
5f4273c7 6749
57785aa2
AV
6750 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6751 {
6752 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6753 inst.operands[i].reg = val;
6754 inst.operands[i].isscalar = 2;
6755 inst.operands[i].present = 1;
6756 inst.operands[i].vectype = optype;
6757 }
6758 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL)
477330fc
RM
6759 {
6760 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6761 inst.operands[i].reg = val;
6762 inst.operands[i].isscalar = 1;
6763 inst.operands[i].present = 1;
6764 inst.operands[i].vectype = optype;
6765 }
dcbf9037 6766 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
477330fc 6767 {
477330fc
RM
6768 inst.operands[i].reg = val;
6769 inst.operands[i].isreg = 1;
6770 inst.operands[i++].present = 1;
6771
6772 if (skip_past_comma (&ptr) == FAIL)
6773 goto wanted_comma;
6774
6775 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
57785aa2 6776 != FAIL)
477330fc 6777 {
57785aa2 6778 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
477330fc 6779
477330fc
RM
6780 inst.operands[i].reg = val;
6781 inst.operands[i].isreg = 1;
6782 inst.operands[i].isvec = 1;
57785aa2 6783 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
477330fc
RM
6784 inst.operands[i].vectype = optype;
6785 inst.operands[i].present = 1;
57785aa2
AV
6786
6787 if (rtype == REG_TYPE_VFS)
6788 {
6789 /* Case 14. */
6790 i++;
6791 if (skip_past_comma (&ptr) == FAIL)
6792 goto wanted_comma;
6793 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6794 &optype)) == FAIL)
6795 {
6796 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6797 return FAIL;
6798 }
6799 inst.operands[i].reg = val;
6800 inst.operands[i].isreg = 1;
6801 inst.operands[i].isvec = 1;
6802 inst.operands[i].issingle = 1;
6803 inst.operands[i].vectype = optype;
6804 inst.operands[i].present = 1;
6805 }
6806 }
6807 else
6808 {
6809 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ))
6810 != FAIL)
6811 {
6812 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6813 inst.operands[i].reg = val;
6814 inst.operands[i].isvec = 1;
6815 inst.operands[i].isscalar = 2;
6816 inst.operands[i].vectype = optype;
6817 inst.operands[i++].present = 1;
6818
6819 if (skip_past_comma (&ptr) == FAIL)
6820 goto wanted_comma;
6821
6822 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ))
6823 == FAIL)
6824 {
6825 first_error (_(reg_expected_msgs[REG_TYPE_MQ]));
6826 return FAIL;
6827 }
6828 inst.operands[i].reg = val;
6829 inst.operands[i].isvec = 1;
6830 inst.operands[i].isscalar = 2;
6831 inst.operands[i].vectype = optype;
6832 inst.operands[i].present = 1;
6833 }
6834 else
6835 {
6836 first_error (_("VFP single, double or MVE vector register"
6837 " expected"));
6838 return FAIL;
6839 }
477330fc
RM
6840 }
6841 }
037e8744 6842 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
477330fc
RM
6843 != FAIL)
6844 {
6845 /* Case 13. */
6846 inst.operands[i].reg = val;
6847 inst.operands[i].isreg = 1;
6848 inst.operands[i].isvec = 1;
6849 inst.operands[i].issingle = 1;
6850 inst.operands[i].vectype = optype;
6851 inst.operands[i].present = 1;
6852 }
5287ad62
JB
6853 }
6854 else
6855 {
dcbf9037 6856 first_error (_("parse error"));
5287ad62
JB
6857 return FAIL;
6858 }
6859
6860 /* Successfully parsed the operands. Update args. */
6861 *which_operand = i;
6862 *str = ptr;
6863 return SUCCESS;
6864
5f4273c7 6865 wanted_comma:
dcbf9037 6866 first_error (_("expected comma"));
5287ad62 6867 return FAIL;
5f4273c7
NC
6868
6869 wanted_arm:
dcbf9037 6870 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
5287ad62 6871 return FAIL;
5287ad62
JB
6872}
6873
5be8be5d
DG
6874/* Use this macro when the operand constraints are different
6875 for ARM and THUMB (e.g. ldrd). */
6876#define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6877 ((arm_operand) | ((thumb_operand) << 16))
6878
c19d1205
ZW
6879/* Matcher codes for parse_operands. */
6880enum operand_parse_code
6881{
6882 OP_stop, /* end of line */
6883
6884 OP_RR, /* ARM register */
6885 OP_RRnpc, /* ARM register, not r15 */
5be8be5d 6886 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
c19d1205 6887 OP_RRnpcb, /* ARM register, not r15, in square brackets */
fa94de6b 6888 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
55881a11 6889 optional trailing ! */
c19d1205
ZW
6890 OP_RRw, /* ARM register, not r15, optional trailing ! */
6891 OP_RCP, /* Coprocessor number */
6892 OP_RCN, /* Coprocessor register */
6893 OP_RF, /* FPA register */
6894 OP_RVS, /* VFP single precision register */
5287ad62
JB
6895 OP_RVD, /* VFP double precision register (0..15) */
6896 OP_RND, /* Neon double precision register (0..31) */
5ee91343
AV
6897 OP_RNDMQ, /* Neon double precision (0..31) or MVE vector register. */
6898 OP_RNDMQR, /* Neon double precision (0..31), MVE vector or ARM register.
6899 */
5287ad62 6900 OP_RNQ, /* Neon quad precision register */
5ee91343 6901 OP_RNQMQ, /* Neon quad or MVE vector register. */
037e8744 6902 OP_RVSD, /* VFP single or double precision register */
1b883319 6903 OP_RVSD_COND, /* VFP single, double precision register or condition code. */
dd9634d9 6904 OP_RVSDMQ, /* VFP single, double precision or MVE vector register. */
dec41383 6905 OP_RNSD, /* Neon single or double precision register */
5287ad62 6906 OP_RNDQ, /* Neon double or quad precision register */
5ee91343 6907 OP_RNDQMQ, /* Neon double, quad or MVE vector register. */
7df54120 6908 OP_RNDQMQR, /* Neon double, quad, MVE vector or ARM register. */
037e8744 6909 OP_RNSDQ, /* Neon single, double or quad precision register */
5287ad62 6910 OP_RNSC, /* Neon scalar D[X] */
c19d1205
ZW
6911 OP_RVC, /* VFP control register */
6912 OP_RMF, /* Maverick F register */
6913 OP_RMD, /* Maverick D register */
6914 OP_RMFX, /* Maverick FX register */
6915 OP_RMDX, /* Maverick DX register */
6916 OP_RMAX, /* Maverick AX register */
6917 OP_RMDS, /* Maverick DSPSC register */
6918 OP_RIWR, /* iWMMXt wR register */
6919 OP_RIWC, /* iWMMXt wC register */
6920 OP_RIWG, /* iWMMXt wCG register */
6921 OP_RXA, /* XScale accumulator register */
6922
5ee91343
AV
6923 OP_RNSDQMQ, /* Neon single, double or quad register or MVE vector register
6924 */
6925 OP_RNSDQMQR, /* Neon single, double or quad register, MVE vector register or
6926 GPR (no SP/SP) */
a302e574 6927 OP_RMQ, /* MVE vector register. */
1b883319 6928 OP_RMQRZ, /* MVE vector or ARM register including ZR. */
35d1cfc2 6929 OP_RMQRR, /* MVE vector or ARM register. */
a302e574 6930
60f993ce
AV
6931 /* New operands for Armv8.1-M Mainline. */
6932 OP_LR, /* ARM LR register */
a302e574
AV
6933 OP_RRe, /* ARM register, only even numbered. */
6934 OP_RRo, /* ARM register, only odd numbered, not r13 or r15. */
60f993ce 6935 OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */
e39c1607 6936 OP_RR_ZR, /* ARM register or ZR but no PC */
60f993ce 6937
c19d1205 6938 OP_REGLST, /* ARM register list */
4b5a202f 6939 OP_CLRMLST, /* CLRM register list */
c19d1205
ZW
6940 OP_VRSLST, /* VFP single-precision register list */
6941 OP_VRDLST, /* VFP double-precision register list */
037e8744 6942 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
5287ad62
JB
6943 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6944 OP_NSTRLST, /* Neon element/structure list */
efd6b359 6945 OP_VRSDVLST, /* VFP single or double-precision register list and VPR */
35c228db
AV
6946 OP_MSTRLST2, /* MVE vector list with two elements. */
6947 OP_MSTRLST4, /* MVE vector list with four elements. */
5287ad62 6948
5287ad62 6949 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
037e8744 6950 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
aacf0b33 6951 OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */
1b883319
AV
6952 OP_RSVDMQ_FI0, /* VFP S, D, MVE vector register or floating point immediate
6953 zero. */
5287ad62 6954 OP_RR_RNSC, /* ARM reg or Neon scalar. */
dec41383 6955 OP_RNSD_RNSC, /* Neon S or D reg, or Neon scalar. */
037e8744 6956 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
886e1c73
AV
6957 OP_RNSDQ_RNSC_MQ, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
6958 */
a8465a06
AV
6959 OP_RNSDQ_RNSC_MQ_RR, /* Vector S, D or Q reg, or MVE vector reg , or Neon
6960 scalar, or ARM register. */
5287ad62 6961 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
42b16635
AV
6962 OP_RNDQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, or ARM register. */
6963 OP_RNDQMQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
6964 register. */
5d281bf0 6965 OP_RNDQMQ_RNSC, /* Neon D, Q or MVE vector reg, or Neon scalar. */
5287ad62
JB
6966 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6967 OP_VMOV, /* Neon VMOV operands. */
4316f0d2 6968 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
f601a00c
AV
6969 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
6970 OP_RNDQMQ_Ibig,
5287ad62 6971 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
5150f0d8
AV
6972 OP_RNDQMQ_I63b_RR, /* Neon D or Q reg, immediate for shift, MVE vector or
6973 ARM register. */
2d447fca 6974 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
32c36c3c 6975 OP_VLDR, /* VLDR operand. */
5287ad62
JB
6976
6977 OP_I0, /* immediate zero */
c19d1205
ZW
6978 OP_I7, /* immediate value 0 .. 7 */
6979 OP_I15, /* 0 .. 15 */
6980 OP_I16, /* 1 .. 16 */
5287ad62 6981 OP_I16z, /* 0 .. 16 */
c19d1205
ZW
6982 OP_I31, /* 0 .. 31 */
6983 OP_I31w, /* 0 .. 31, optional trailing ! */
6984 OP_I32, /* 1 .. 32 */
5287ad62
JB
6985 OP_I32z, /* 0 .. 32 */
6986 OP_I63, /* 0 .. 63 */
c19d1205 6987 OP_I63s, /* -64 .. 63 */
5287ad62
JB
6988 OP_I64, /* 1 .. 64 */
6989 OP_I64z, /* 0 .. 64 */
c19d1205 6990 OP_I255, /* 0 .. 255 */
c19d1205
ZW
6991
6992 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6993 OP_I7b, /* 0 .. 7 */
6994 OP_I15b, /* 0 .. 15 */
6995 OP_I31b, /* 0 .. 31 */
6996
6997 OP_SH, /* shifter operand */
4962c51a 6998 OP_SHG, /* shifter operand with possible group relocation */
c19d1205 6999 OP_ADDR, /* Memory address expression (any mode) */
35c228db 7000 OP_ADDRMVE, /* Memory address expression for MVE's VSTR/VLDR. */
4962c51a
MS
7001 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
7002 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
7003 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
c19d1205
ZW
7004 OP_EXP, /* arbitrary expression */
7005 OP_EXPi, /* same, with optional immediate prefix */
7006 OP_EXPr, /* same, with optional relocation suffix */
e2b0ab59 7007 OP_EXPs, /* same, with optional non-first operand relocation suffix */
b6895b4f 7008 OP_HALF, /* 0 .. 65535 or low/high reloc. */
c28eeff2
SN
7009 OP_IROT1, /* VCADD rotate immediate: 90, 270. */
7010 OP_IROT2, /* VCMLA rotate immediate: 0, 90, 180, 270. */
c19d1205
ZW
7011
7012 OP_CPSF, /* CPS flags */
7013 OP_ENDI, /* Endianness specifier */
d2cd1205
JB
7014 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
7015 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
c19d1205 7016 OP_COND, /* conditional code */
92e90b6e 7017 OP_TB, /* Table branch. */
c19d1205 7018
037e8744
JB
7019 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
7020
c19d1205 7021 OP_RRnpc_I0, /* ARM register or literal 0 */
33eaf5de 7022 OP_RR_EXr, /* ARM register or expression with opt. reloc stuff. */
c19d1205
ZW
7023 OP_RR_EXi, /* ARM register or expression with imm prefix */
7024 OP_RF_IF, /* FPA register or immediate */
7025 OP_RIWR_RIWC, /* iWMMXt R or C reg */
41adaa5c 7026 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
c19d1205
ZW
7027
7028 /* Optional operands. */
7029 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
7030 OP_oI31b, /* 0 .. 31 */
5287ad62 7031 OP_oI32b, /* 1 .. 32 */
5f1af56b 7032 OP_oI32z, /* 0 .. 32 */
c19d1205
ZW
7033 OP_oIffffb, /* 0 .. 65535 */
7034 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
7035
7036 OP_oRR, /* ARM register */
60f993ce 7037 OP_oLR, /* ARM LR register */
c19d1205 7038 OP_oRRnpc, /* ARM register, not the PC */
5be8be5d 7039 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
b6702015 7040 OP_oRRw, /* ARM register, not r15, optional trailing ! */
5287ad62
JB
7041 OP_oRND, /* Optional Neon double precision register */
7042 OP_oRNQ, /* Optional Neon quad precision register */
5ee91343 7043 OP_oRNDQMQ, /* Optional Neon double, quad or MVE vector register. */
5287ad62 7044 OP_oRNDQ, /* Optional Neon double or quad precision register */
037e8744 7045 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
5ee91343
AV
7046 OP_oRNSDQMQ, /* Optional single, double or quad register or MVE vector
7047 register. */
c19d1205
ZW
7048 OP_oSHll, /* LSL immediate */
7049 OP_oSHar, /* ASR immediate */
7050 OP_oSHllar, /* LSL or ASR immediate */
7051 OP_oROR, /* ROR 0/8/16/24 */
52e7f43d 7052 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
c19d1205 7053
1b883319
AV
7054 OP_oRMQRZ, /* optional MVE vector or ARM register including ZR. */
7055
5be8be5d
DG
7056 /* Some pre-defined mixed (ARM/THUMB) operands. */
7057 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
7058 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
7059 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
7060
c19d1205
ZW
7061 OP_FIRST_OPTIONAL = OP_oI7b
7062};
a737bd4d 7063
c19d1205
ZW
7064/* Generic instruction operand parser. This does no encoding and no
7065 semantic validation; it merely squirrels values away in the inst
7066 structure. Returns SUCCESS or FAIL depending on whether the
7067 specified grammar matched. */
7068static int
5be8be5d 7069parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
c19d1205 7070{
5be8be5d 7071 unsigned const int *upat = pattern;
c19d1205
ZW
7072 char *backtrack_pos = 0;
7073 const char *backtrack_error = 0;
99aad254 7074 int i, val = 0, backtrack_index = 0;
5287ad62 7075 enum arm_reg_type rtype;
4962c51a 7076 parse_operand_result result;
5be8be5d 7077 unsigned int op_parse_code;
efd6b359 7078 bfd_boolean partial_match;
c19d1205 7079
e07e6e58
NC
7080#define po_char_or_fail(chr) \
7081 do \
7082 { \
7083 if (skip_past_char (&str, chr) == FAIL) \
477330fc 7084 goto bad_args; \
e07e6e58
NC
7085 } \
7086 while (0)
c19d1205 7087
e07e6e58
NC
7088#define po_reg_or_fail(regtype) \
7089 do \
dcbf9037 7090 { \
e07e6e58 7091 val = arm_typed_reg_parse (& str, regtype, & rtype, \
477330fc 7092 & inst.operands[i].vectype); \
e07e6e58 7093 if (val == FAIL) \
477330fc
RM
7094 { \
7095 first_error (_(reg_expected_msgs[regtype])); \
7096 goto failure; \
7097 } \
e07e6e58
NC
7098 inst.operands[i].reg = val; \
7099 inst.operands[i].isreg = 1; \
7100 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7101 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7102 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
477330fc
RM
7103 || rtype == REG_TYPE_VFD \
7104 || rtype == REG_TYPE_NQ); \
1b883319 7105 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
dcbf9037 7106 } \
e07e6e58
NC
7107 while (0)
7108
7109#define po_reg_or_goto(regtype, label) \
7110 do \
7111 { \
7112 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7113 & inst.operands[i].vectype); \
7114 if (val == FAIL) \
7115 goto label; \
dcbf9037 7116 \
e07e6e58
NC
7117 inst.operands[i].reg = val; \
7118 inst.operands[i].isreg = 1; \
7119 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7120 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7121 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
477330fc 7122 || rtype == REG_TYPE_VFD \
e07e6e58 7123 || rtype == REG_TYPE_NQ); \
1b883319 7124 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
e07e6e58
NC
7125 } \
7126 while (0)
7127
7128#define po_imm_or_fail(min, max, popt) \
7129 do \
7130 { \
7131 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7132 goto failure; \
7133 inst.operands[i].imm = val; \
7134 } \
7135 while (0)
7136
57785aa2 7137#define po_scalar_or_goto(elsz, label, reg_type) \
e07e6e58
NC
7138 do \
7139 { \
57785aa2
AV
7140 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7141 reg_type); \
e07e6e58
NC
7142 if (val == FAIL) \
7143 goto label; \
7144 inst.operands[i].reg = val; \
7145 inst.operands[i].isscalar = 1; \
7146 } \
7147 while (0)
7148
7149#define po_misc_or_fail(expr) \
7150 do \
7151 { \
7152 if (expr) \
7153 goto failure; \
7154 } \
7155 while (0)
7156
7157#define po_misc_or_fail_no_backtrack(expr) \
7158 do \
7159 { \
7160 result = expr; \
7161 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7162 backtrack_pos = 0; \
7163 if (result != PARSE_OPERAND_SUCCESS) \
7164 goto failure; \
7165 } \
7166 while (0)
4962c51a 7167
52e7f43d
RE
7168#define po_barrier_or_imm(str) \
7169 do \
7170 { \
7171 val = parse_barrier (&str); \
ccb84d65
JB
7172 if (val == FAIL && ! ISALPHA (*str)) \
7173 goto immediate; \
7174 if (val == FAIL \
7175 /* ISB can only take SY as an option. */ \
7176 || ((inst.instruction & 0xf0) == 0x60 \
7177 && val != 0xf)) \
52e7f43d 7178 { \
ccb84d65
JB
7179 inst.error = _("invalid barrier type"); \
7180 backtrack_pos = 0; \
7181 goto failure; \
52e7f43d
RE
7182 } \
7183 } \
7184 while (0)
7185
c19d1205
ZW
7186 skip_whitespace (str);
7187
7188 for (i = 0; upat[i] != OP_stop; i++)
7189 {
5be8be5d
DG
7190 op_parse_code = upat[i];
7191 if (op_parse_code >= 1<<16)
7192 op_parse_code = thumb ? (op_parse_code >> 16)
7193 : (op_parse_code & ((1<<16)-1));
7194
7195 if (op_parse_code >= OP_FIRST_OPTIONAL)
c19d1205
ZW
7196 {
7197 /* Remember where we are in case we need to backtrack. */
c19d1205
ZW
7198 backtrack_pos = str;
7199 backtrack_error = inst.error;
7200 backtrack_index = i;
7201 }
7202
b6702015 7203 if (i > 0 && (i > 1 || inst.operands[0].present))
c19d1205
ZW
7204 po_char_or_fail (',');
7205
5be8be5d 7206 switch (op_parse_code)
c19d1205
ZW
7207 {
7208 /* Registers */
7209 case OP_oRRnpc:
5be8be5d 7210 case OP_oRRnpcsp:
c19d1205 7211 case OP_RRnpc:
5be8be5d 7212 case OP_RRnpcsp:
c19d1205 7213 case OP_oRR:
a302e574
AV
7214 case OP_RRe:
7215 case OP_RRo:
60f993ce
AV
7216 case OP_LR:
7217 case OP_oLR:
c19d1205
ZW
7218 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
7219 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
7220 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
7221 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
7222 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
7223 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
477330fc 7224 case OP_oRND:
5ee91343
AV
7225 case OP_RNDMQR:
7226 po_reg_or_goto (REG_TYPE_RN, try_rndmq);
7227 break;
7228 try_rndmq:
7229 case OP_RNDMQ:
7230 po_reg_or_goto (REG_TYPE_MQ, try_rnd);
7231 break;
7232 try_rnd:
5287ad62 7233 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
cd2cf30b
PB
7234 case OP_RVC:
7235 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
7236 break;
7237 /* Also accept generic coprocessor regs for unknown registers. */
7238 coproc_reg:
7239 po_reg_or_fail (REG_TYPE_CN);
7240 break;
c19d1205
ZW
7241 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
7242 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
7243 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
7244 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
7245 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
7246 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
7247 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
7248 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
7249 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
7250 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
477330fc 7251 case OP_oRNQ:
5ee91343
AV
7252 case OP_RNQMQ:
7253 po_reg_or_goto (REG_TYPE_MQ, try_nq);
7254 break;
7255 try_nq:
5287ad62 7256 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
dec41383 7257 case OP_RNSD: po_reg_or_fail (REG_TYPE_NSD); break;
7df54120
AV
7258 case OP_RNDQMQR:
7259 po_reg_or_goto (REG_TYPE_RN, try_rndqmq);
7260 break;
7261 try_rndqmq:
5ee91343
AV
7262 case OP_oRNDQMQ:
7263 case OP_RNDQMQ:
7264 po_reg_or_goto (REG_TYPE_MQ, try_rndq);
7265 break;
7266 try_rndq:
477330fc 7267 case OP_oRNDQ:
5287ad62 7268 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
dd9634d9
AV
7269 case OP_RVSDMQ:
7270 po_reg_or_goto (REG_TYPE_MQ, try_rvsd);
7271 break;
7272 try_rvsd:
477330fc 7273 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
1b883319
AV
7274 case OP_RVSD_COND:
7275 po_reg_or_goto (REG_TYPE_VFSD, try_cond);
7276 break;
477330fc
RM
7277 case OP_oRNSDQ:
7278 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
5ee91343
AV
7279 case OP_RNSDQMQR:
7280 po_reg_or_goto (REG_TYPE_RN, try_mq);
7281 break;
7282 try_mq:
7283 case OP_oRNSDQMQ:
7284 case OP_RNSDQMQ:
7285 po_reg_or_goto (REG_TYPE_MQ, try_nsdq2);
7286 break;
7287 try_nsdq2:
7288 po_reg_or_fail (REG_TYPE_NSDQ);
7289 inst.error = 0;
7290 break;
35d1cfc2
AV
7291 case OP_RMQRR:
7292 po_reg_or_goto (REG_TYPE_RN, try_rmq);
7293 break;
7294 try_rmq:
a302e574
AV
7295 case OP_RMQ:
7296 po_reg_or_fail (REG_TYPE_MQ);
7297 break;
477330fc
RM
7298 /* Neon scalar. Using an element size of 8 means that some invalid
7299 scalars are accepted here, so deal with those in later code. */
57785aa2 7300 case OP_RNSC: po_scalar_or_goto (8, failure, REG_TYPE_VFD); break;
477330fc
RM
7301
7302 case OP_RNDQ_I0:
7303 {
7304 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
7305 break;
7306 try_imm0:
7307 po_imm_or_fail (0, 0, TRUE);
7308 }
7309 break;
7310
7311 case OP_RVSD_I0:
7312 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
7313 break;
7314
1b883319
AV
7315 case OP_RSVDMQ_FI0:
7316 po_reg_or_goto (REG_TYPE_MQ, try_rsvd_fi0);
7317 break;
7318 try_rsvd_fi0:
aacf0b33
KT
7319 case OP_RSVD_FI0:
7320 {
7321 po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0);
7322 break;
7323 try_ifimm0:
7324 if (parse_ifimm_zero (&str))
7325 inst.operands[i].imm = 0;
7326 else
7327 {
7328 inst.error
7329 = _("only floating point zero is allowed as immediate value");
7330 goto failure;
7331 }
7332 }
7333 break;
7334
477330fc
RM
7335 case OP_RR_RNSC:
7336 {
57785aa2 7337 po_scalar_or_goto (8, try_rr, REG_TYPE_VFD);
477330fc
RM
7338 break;
7339 try_rr:
7340 po_reg_or_fail (REG_TYPE_RN);
7341 }
7342 break;
7343
a8465a06
AV
7344 case OP_RNSDQ_RNSC_MQ_RR:
7345 po_reg_or_goto (REG_TYPE_RN, try_rnsdq_rnsc_mq);
7346 break;
7347 try_rnsdq_rnsc_mq:
886e1c73
AV
7348 case OP_RNSDQ_RNSC_MQ:
7349 po_reg_or_goto (REG_TYPE_MQ, try_rnsdq_rnsc);
7350 break;
7351 try_rnsdq_rnsc:
477330fc
RM
7352 case OP_RNSDQ_RNSC:
7353 {
57785aa2
AV
7354 po_scalar_or_goto (8, try_nsdq, REG_TYPE_VFD);
7355 inst.error = 0;
477330fc
RM
7356 break;
7357 try_nsdq:
7358 po_reg_or_fail (REG_TYPE_NSDQ);
57785aa2 7359 inst.error = 0;
477330fc
RM
7360 }
7361 break;
7362
dec41383
JW
7363 case OP_RNSD_RNSC:
7364 {
57785aa2 7365 po_scalar_or_goto (8, try_s_scalar, REG_TYPE_VFD);
dec41383
JW
7366 break;
7367 try_s_scalar:
57785aa2 7368 po_scalar_or_goto (4, try_nsd, REG_TYPE_VFS);
dec41383
JW
7369 break;
7370 try_nsd:
7371 po_reg_or_fail (REG_TYPE_NSD);
7372 }
7373 break;
7374
42b16635
AV
7375 case OP_RNDQMQ_RNSC_RR:
7376 po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc_rr);
7377 break;
7378 try_rndq_rnsc_rr:
7379 case OP_RNDQ_RNSC_RR:
7380 po_reg_or_goto (REG_TYPE_RN, try_rndq_rnsc);
7381 break;
5d281bf0
AV
7382 case OP_RNDQMQ_RNSC:
7383 po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc);
7384 break;
7385 try_rndq_rnsc:
477330fc
RM
7386 case OP_RNDQ_RNSC:
7387 {
57785aa2 7388 po_scalar_or_goto (8, try_ndq, REG_TYPE_VFD);
477330fc
RM
7389 break;
7390 try_ndq:
7391 po_reg_or_fail (REG_TYPE_NDQ);
7392 }
7393 break;
7394
7395 case OP_RND_RNSC:
7396 {
57785aa2 7397 po_scalar_or_goto (8, try_vfd, REG_TYPE_VFD);
477330fc
RM
7398 break;
7399 try_vfd:
7400 po_reg_or_fail (REG_TYPE_VFD);
7401 }
7402 break;
7403
7404 case OP_VMOV:
7405 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7406 not careful then bad things might happen. */
7407 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
7408 break;
7409
f601a00c
AV
7410 case OP_RNDQMQ_Ibig:
7411 po_reg_or_goto (REG_TYPE_MQ, try_rndq_ibig);
7412 break;
7413 try_rndq_ibig:
477330fc
RM
7414 case OP_RNDQ_Ibig:
7415 {
7416 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
7417 break;
7418 try_immbig:
7419 /* There's a possibility of getting a 64-bit immediate here, so
7420 we need special handling. */
8335d6aa
JW
7421 if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE)
7422 == FAIL)
477330fc
RM
7423 {
7424 inst.error = _("immediate value is out of range");
7425 goto failure;
7426 }
7427 }
7428 break;
7429
5150f0d8
AV
7430 case OP_RNDQMQ_I63b_RR:
7431 po_reg_or_goto (REG_TYPE_MQ, try_rndq_i63b_rr);
7432 break;
7433 try_rndq_i63b_rr:
7434 po_reg_or_goto (REG_TYPE_RN, try_rndq_i63b);
7435 break;
7436 try_rndq_i63b:
477330fc
RM
7437 case OP_RNDQ_I63b:
7438 {
7439 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
7440 break;
7441 try_shimm:
7442 po_imm_or_fail (0, 63, TRUE);
7443 }
7444 break;
c19d1205
ZW
7445
7446 case OP_RRnpcb:
7447 po_char_or_fail ('[');
7448 po_reg_or_fail (REG_TYPE_RN);
7449 po_char_or_fail (']');
7450 break;
a737bd4d 7451
55881a11 7452 case OP_RRnpctw:
c19d1205 7453 case OP_RRw:
b6702015 7454 case OP_oRRw:
c19d1205
ZW
7455 po_reg_or_fail (REG_TYPE_RN);
7456 if (skip_past_char (&str, '!') == SUCCESS)
7457 inst.operands[i].writeback = 1;
7458 break;
7459
7460 /* Immediates */
7461 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
7462 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
7463 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
477330fc 7464 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
c19d1205
ZW
7465 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
7466 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
477330fc 7467 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
c19d1205 7468 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
477330fc
RM
7469 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
7470 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
7471 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
c19d1205 7472 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
c19d1205
ZW
7473
7474 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
7475 case OP_oI7b:
7476 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
7477 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
7478 case OP_oI31b:
7479 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
477330fc
RM
7480 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
7481 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
c19d1205
ZW
7482 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
7483
7484 /* Immediate variants */
7485 case OP_oI255c:
7486 po_char_or_fail ('{');
7487 po_imm_or_fail (0, 255, TRUE);
7488 po_char_or_fail ('}');
7489 break;
7490
7491 case OP_I31w:
7492 /* The expression parser chokes on a trailing !, so we have
7493 to find it first and zap it. */
7494 {
7495 char *s = str;
7496 while (*s && *s != ',')
7497 s++;
7498 if (s[-1] == '!')
7499 {
7500 s[-1] = '\0';
7501 inst.operands[i].writeback = 1;
7502 }
7503 po_imm_or_fail (0, 31, TRUE);
7504 if (str == s - 1)
7505 str = s;
7506 }
7507 break;
7508
7509 /* Expressions */
7510 case OP_EXPi: EXPi:
e2b0ab59 7511 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
c19d1205
ZW
7512 GE_OPT_PREFIX));
7513 break;
7514
7515 case OP_EXP:
e2b0ab59 7516 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
c19d1205
ZW
7517 GE_NO_PREFIX));
7518 break;
7519
7520 case OP_EXPr: EXPr:
e2b0ab59 7521 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
c19d1205 7522 GE_NO_PREFIX));
e2b0ab59 7523 if (inst.relocs[0].exp.X_op == O_symbol)
a737bd4d 7524 {
c19d1205
ZW
7525 val = parse_reloc (&str);
7526 if (val == -1)
7527 {
7528 inst.error = _("unrecognized relocation suffix");
7529 goto failure;
7530 }
7531 else if (val != BFD_RELOC_UNUSED)
7532 {
7533 inst.operands[i].imm = val;
7534 inst.operands[i].hasreloc = 1;
7535 }
a737bd4d 7536 }
c19d1205 7537 break;
a737bd4d 7538
e2b0ab59
AV
7539 case OP_EXPs:
7540 po_misc_or_fail (my_get_expression (&inst.relocs[i].exp, &str,
7541 GE_NO_PREFIX));
7542 if (inst.relocs[i].exp.X_op == O_symbol)
7543 {
7544 inst.operands[i].hasreloc = 1;
7545 }
7546 else if (inst.relocs[i].exp.X_op == O_constant)
7547 {
7548 inst.operands[i].imm = inst.relocs[i].exp.X_add_number;
7549 inst.operands[i].hasreloc = 0;
7550 }
7551 break;
7552
b6895b4f
PB
7553 /* Operand for MOVW or MOVT. */
7554 case OP_HALF:
7555 po_misc_or_fail (parse_half (&str));
7556 break;
7557
e07e6e58 7558 /* Register or expression. */
c19d1205
ZW
7559 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
7560 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
a737bd4d 7561
e07e6e58 7562 /* Register or immediate. */
c19d1205
ZW
7563 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
7564 I0: po_imm_or_fail (0, 0, FALSE); break;
a737bd4d 7565
23d00a41
SD
7566 case OP_RRnpcsp_I32: po_reg_or_goto (REG_TYPE_RN, I32); break;
7567 I32: po_imm_or_fail (1, 32, FALSE); break;
7568
c19d1205
ZW
7569 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
7570 IF:
7571 if (!is_immediate_prefix (*str))
7572 goto bad_args;
7573 str++;
7574 val = parse_fpa_immediate (&str);
7575 if (val == FAIL)
7576 goto failure;
7577 /* FPA immediates are encoded as registers 8-15.
7578 parse_fpa_immediate has already applied the offset. */
7579 inst.operands[i].reg = val;
7580 inst.operands[i].isreg = 1;
7581 break;
09d92015 7582
2d447fca
JM
7583 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
7584 I32z: po_imm_or_fail (0, 32, FALSE); break;
7585
e07e6e58 7586 /* Two kinds of register. */
c19d1205
ZW
7587 case OP_RIWR_RIWC:
7588 {
7589 struct reg_entry *rege = arm_reg_parse_multi (&str);
97f87066
JM
7590 if (!rege
7591 || (rege->type != REG_TYPE_MMXWR
7592 && rege->type != REG_TYPE_MMXWC
7593 && rege->type != REG_TYPE_MMXWCG))
c19d1205
ZW
7594 {
7595 inst.error = _("iWMMXt data or control register expected");
7596 goto failure;
7597 }
7598 inst.operands[i].reg = rege->number;
7599 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
7600 }
7601 break;
09d92015 7602
41adaa5c
JM
7603 case OP_RIWC_RIWG:
7604 {
7605 struct reg_entry *rege = arm_reg_parse_multi (&str);
7606 if (!rege
7607 || (rege->type != REG_TYPE_MMXWC
7608 && rege->type != REG_TYPE_MMXWCG))
7609 {
7610 inst.error = _("iWMMXt control register expected");
7611 goto failure;
7612 }
7613 inst.operands[i].reg = rege->number;
7614 inst.operands[i].isreg = 1;
7615 }
7616 break;
7617
c19d1205
ZW
7618 /* Misc */
7619 case OP_CPSF: val = parse_cps_flags (&str); break;
7620 case OP_ENDI: val = parse_endian_specifier (&str); break;
7621 case OP_oROR: val = parse_ror (&str); break;
1b883319 7622 try_cond:
c19d1205 7623 case OP_COND: val = parse_cond (&str); break;
52e7f43d
RE
7624 case OP_oBARRIER_I15:
7625 po_barrier_or_imm (str); break;
7626 immediate:
7627 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
477330fc 7628 goto failure;
52e7f43d 7629 break;
c19d1205 7630
fa94de6b 7631 case OP_wPSR:
d2cd1205 7632 case OP_rPSR:
90ec0d68
MGD
7633 po_reg_or_goto (REG_TYPE_RNB, try_psr);
7634 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
7635 {
7636 inst.error = _("Banked registers are not available with this "
7637 "architecture.");
7638 goto failure;
7639 }
7640 break;
d2cd1205
JB
7641 try_psr:
7642 val = parse_psr (&str, op_parse_code == OP_wPSR);
7643 break;
037e8744 7644
32c36c3c
AV
7645 case OP_VLDR:
7646 po_reg_or_goto (REG_TYPE_VFSD, try_sysreg);
7647 break;
7648 try_sysreg:
7649 val = parse_sys_vldr_vstr (&str);
7650 break;
7651
477330fc
RM
7652 case OP_APSR_RR:
7653 po_reg_or_goto (REG_TYPE_RN, try_apsr);
7654 break;
7655 try_apsr:
7656 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7657 instruction). */
7658 if (strncasecmp (str, "APSR_", 5) == 0)
7659 {
7660 unsigned found = 0;
7661 str += 5;
7662 while (found < 15)
7663 switch (*str++)
7664 {
7665 case 'c': found = (found & 1) ? 16 : found | 1; break;
7666 case 'n': found = (found & 2) ? 16 : found | 2; break;
7667 case 'z': found = (found & 4) ? 16 : found | 4; break;
7668 case 'v': found = (found & 8) ? 16 : found | 8; break;
7669 default: found = 16;
7670 }
7671 if (found != 15)
7672 goto failure;
7673 inst.operands[i].isvec = 1;
f7c21dc7
NC
7674 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7675 inst.operands[i].reg = REG_PC;
477330fc
RM
7676 }
7677 else
7678 goto failure;
7679 break;
037e8744 7680
92e90b6e
PB
7681 case OP_TB:
7682 po_misc_or_fail (parse_tb (&str));
7683 break;
7684
e07e6e58 7685 /* Register lists. */
c19d1205 7686 case OP_REGLST:
4b5a202f 7687 val = parse_reg_list (&str, REGLIST_RN);
c19d1205
ZW
7688 if (*str == '^')
7689 {
5e0d7f77 7690 inst.operands[i].writeback = 1;
c19d1205
ZW
7691 str++;
7692 }
7693 break;
09d92015 7694
4b5a202f
AV
7695 case OP_CLRMLST:
7696 val = parse_reg_list (&str, REGLIST_CLRM);
7697 break;
7698
c19d1205 7699 case OP_VRSLST:
efd6b359
AV
7700 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S,
7701 &partial_match);
c19d1205 7702 break;
09d92015 7703
c19d1205 7704 case OP_VRDLST:
efd6b359
AV
7705 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D,
7706 &partial_match);
c19d1205 7707 break;
a737bd4d 7708
477330fc
RM
7709 case OP_VRSDLST:
7710 /* Allow Q registers too. */
7711 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
efd6b359 7712 REGLIST_NEON_D, &partial_match);
477330fc
RM
7713 if (val == FAIL)
7714 {
7715 inst.error = NULL;
7716 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
efd6b359
AV
7717 REGLIST_VFP_S, &partial_match);
7718 inst.operands[i].issingle = 1;
7719 }
7720 break;
7721
7722 case OP_VRSDVLST:
7723 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7724 REGLIST_VFP_D_VPR, &partial_match);
7725 if (val == FAIL && !partial_match)
7726 {
7727 inst.error = NULL;
7728 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7729 REGLIST_VFP_S_VPR, &partial_match);
477330fc
RM
7730 inst.operands[i].issingle = 1;
7731 }
7732 break;
7733
7734 case OP_NRDLST:
7735 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
efd6b359 7736 REGLIST_NEON_D, &partial_match);
477330fc 7737 break;
5287ad62 7738
35c228db
AV
7739 case OP_MSTRLST4:
7740 case OP_MSTRLST2:
7741 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7742 1, &inst.operands[i].vectype);
7743 if (val != (((op_parse_code == OP_MSTRLST2) ? 3 : 7) << 5 | 0xe))
7744 goto failure;
7745 break;
5287ad62 7746 case OP_NSTRLST:
477330fc 7747 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
35c228db 7748 0, &inst.operands[i].vectype);
477330fc 7749 break;
5287ad62 7750
c19d1205 7751 /* Addressing modes */
35c228db
AV
7752 case OP_ADDRMVE:
7753 po_misc_or_fail (parse_address_group_reloc (&str, i, GROUP_MVE));
7754 break;
7755
c19d1205
ZW
7756 case OP_ADDR:
7757 po_misc_or_fail (parse_address (&str, i));
7758 break;
09d92015 7759
4962c51a
MS
7760 case OP_ADDRGLDR:
7761 po_misc_or_fail_no_backtrack (
477330fc 7762 parse_address_group_reloc (&str, i, GROUP_LDR));
4962c51a
MS
7763 break;
7764
7765 case OP_ADDRGLDRS:
7766 po_misc_or_fail_no_backtrack (
477330fc 7767 parse_address_group_reloc (&str, i, GROUP_LDRS));
4962c51a
MS
7768 break;
7769
7770 case OP_ADDRGLDC:
7771 po_misc_or_fail_no_backtrack (
477330fc 7772 parse_address_group_reloc (&str, i, GROUP_LDC));
4962c51a
MS
7773 break;
7774
c19d1205
ZW
7775 case OP_SH:
7776 po_misc_or_fail (parse_shifter_operand (&str, i));
7777 break;
09d92015 7778
4962c51a
MS
7779 case OP_SHG:
7780 po_misc_or_fail_no_backtrack (
477330fc 7781 parse_shifter_operand_group_reloc (&str, i));
4962c51a
MS
7782 break;
7783
c19d1205
ZW
7784 case OP_oSHll:
7785 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
7786 break;
09d92015 7787
c19d1205
ZW
7788 case OP_oSHar:
7789 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
7790 break;
09d92015 7791
c19d1205
ZW
7792 case OP_oSHllar:
7793 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
7794 break;
09d92015 7795
1b883319
AV
7796 case OP_RMQRZ:
7797 case OP_oRMQRZ:
7798 po_reg_or_goto (REG_TYPE_MQ, try_rr_zr);
7799 break;
e39c1607
SD
7800
7801 case OP_RR_ZR:
1b883319
AV
7802 try_rr_zr:
7803 po_reg_or_goto (REG_TYPE_RN, ZR);
7804 break;
7805 ZR:
7806 po_reg_or_fail (REG_TYPE_ZR);
7807 break;
7808
c19d1205 7809 default:
5be8be5d 7810 as_fatal (_("unhandled operand code %d"), op_parse_code);
c19d1205 7811 }
09d92015 7812
c19d1205
ZW
7813 /* Various value-based sanity checks and shared operations. We
7814 do not signal immediate failures for the register constraints;
7815 this allows a syntax error to take precedence. */
5be8be5d 7816 switch (op_parse_code)
c19d1205
ZW
7817 {
7818 case OP_oRRnpc:
7819 case OP_RRnpc:
7820 case OP_RRnpcb:
7821 case OP_RRw:
b6702015 7822 case OP_oRRw:
c19d1205
ZW
7823 case OP_RRnpc_I0:
7824 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
7825 inst.error = BAD_PC;
7826 break;
09d92015 7827
5be8be5d
DG
7828 case OP_oRRnpcsp:
7829 case OP_RRnpcsp:
23d00a41 7830 case OP_RRnpcsp_I32:
5be8be5d
DG
7831 if (inst.operands[i].isreg)
7832 {
7833 if (inst.operands[i].reg == REG_PC)
7834 inst.error = BAD_PC;
5c8ed6a4
JW
7835 else if (inst.operands[i].reg == REG_SP
7836 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7837 relaxed since ARMv8-A. */
7838 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
7839 {
7840 gas_assert (thumb);
7841 inst.error = BAD_SP;
7842 }
5be8be5d
DG
7843 }
7844 break;
7845
55881a11 7846 case OP_RRnpctw:
fa94de6b
RM
7847 if (inst.operands[i].isreg
7848 && inst.operands[i].reg == REG_PC
55881a11
MGD
7849 && (inst.operands[i].writeback || thumb))
7850 inst.error = BAD_PC;
7851 break;
7852
1b883319 7853 case OP_RVSD_COND:
32c36c3c
AV
7854 case OP_VLDR:
7855 if (inst.operands[i].isreg)
7856 break;
7857 /* fall through. */
1b883319 7858
c19d1205
ZW
7859 case OP_CPSF:
7860 case OP_ENDI:
7861 case OP_oROR:
d2cd1205
JB
7862 case OP_wPSR:
7863 case OP_rPSR:
c19d1205 7864 case OP_COND:
52e7f43d 7865 case OP_oBARRIER_I15:
c19d1205 7866 case OP_REGLST:
4b5a202f 7867 case OP_CLRMLST:
c19d1205
ZW
7868 case OP_VRSLST:
7869 case OP_VRDLST:
477330fc 7870 case OP_VRSDLST:
efd6b359 7871 case OP_VRSDVLST:
477330fc
RM
7872 case OP_NRDLST:
7873 case OP_NSTRLST:
35c228db
AV
7874 case OP_MSTRLST2:
7875 case OP_MSTRLST4:
c19d1205
ZW
7876 if (val == FAIL)
7877 goto failure;
7878 inst.operands[i].imm = val;
7879 break;
a737bd4d 7880
60f993ce
AV
7881 case OP_LR:
7882 case OP_oLR:
7883 if (inst.operands[i].reg != REG_LR)
7884 inst.error = _("operand must be LR register");
7885 break;
7886
1b883319
AV
7887 case OP_RMQRZ:
7888 case OP_oRMQRZ:
e39c1607 7889 case OP_RR_ZR:
1b883319
AV
7890 if (!inst.operands[i].iszr && inst.operands[i].reg == REG_PC)
7891 inst.error = BAD_PC;
7892 break;
7893
a302e574
AV
7894 case OP_RRe:
7895 if (inst.operands[i].isreg
7896 && (inst.operands[i].reg & 0x00000001) != 0)
7897 inst.error = BAD_ODD;
7898 break;
7899
7900 case OP_RRo:
7901 if (inst.operands[i].isreg)
7902 {
7903 if ((inst.operands[i].reg & 0x00000001) != 1)
7904 inst.error = BAD_EVEN;
7905 else if (inst.operands[i].reg == REG_SP)
7906 as_tsktsk (MVE_BAD_SP);
7907 else if (inst.operands[i].reg == REG_PC)
7908 inst.error = BAD_PC;
7909 }
7910 break;
7911
c19d1205
ZW
7912 default:
7913 break;
7914 }
09d92015 7915
c19d1205
ZW
7916 /* If we get here, this operand was successfully parsed. */
7917 inst.operands[i].present = 1;
7918 continue;
09d92015 7919
c19d1205 7920 bad_args:
09d92015 7921 inst.error = BAD_ARGS;
c19d1205
ZW
7922
7923 failure:
7924 if (!backtrack_pos)
d252fdde
PB
7925 {
7926 /* The parse routine should already have set inst.error, but set a
5f4273c7 7927 default here just in case. */
d252fdde 7928 if (!inst.error)
5ee91343 7929 inst.error = BAD_SYNTAX;
d252fdde
PB
7930 return FAIL;
7931 }
c19d1205
ZW
7932
7933 /* Do not backtrack over a trailing optional argument that
7934 absorbed some text. We will only fail again, with the
7935 'garbage following instruction' error message, which is
7936 probably less helpful than the current one. */
7937 if (backtrack_index == i && backtrack_pos != str
7938 && upat[i+1] == OP_stop)
d252fdde
PB
7939 {
7940 if (!inst.error)
5ee91343 7941 inst.error = BAD_SYNTAX;
d252fdde
PB
7942 return FAIL;
7943 }
c19d1205
ZW
7944
7945 /* Try again, skipping the optional argument at backtrack_pos. */
7946 str = backtrack_pos;
7947 inst.error = backtrack_error;
7948 inst.operands[backtrack_index].present = 0;
7949 i = backtrack_index;
7950 backtrack_pos = 0;
09d92015 7951 }
09d92015 7952
c19d1205
ZW
7953 /* Check that we have parsed all the arguments. */
7954 if (*str != '\0' && !inst.error)
7955 inst.error = _("garbage following instruction");
09d92015 7956
c19d1205 7957 return inst.error ? FAIL : SUCCESS;
09d92015
MM
7958}
7959
c19d1205
ZW
7960#undef po_char_or_fail
7961#undef po_reg_or_fail
7962#undef po_reg_or_goto
7963#undef po_imm_or_fail
5287ad62 7964#undef po_scalar_or_fail
52e7f43d 7965#undef po_barrier_or_imm
e07e6e58 7966
c19d1205 7967/* Shorthand macro for instruction encoding functions issuing errors. */
e07e6e58
NC
7968#define constraint(expr, err) \
7969 do \
c19d1205 7970 { \
e07e6e58
NC
7971 if (expr) \
7972 { \
7973 inst.error = err; \
7974 return; \
7975 } \
c19d1205 7976 } \
e07e6e58 7977 while (0)
c19d1205 7978
fdfde340
JM
7979/* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7980 instructions are unpredictable if these registers are used. This
5c8ed6a4
JW
7981 is the BadReg predicate in ARM's Thumb-2 documentation.
7982
7983 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7984 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7985#define reject_bad_reg(reg) \
7986 do \
7987 if (reg == REG_PC) \
7988 { \
7989 inst.error = BAD_PC; \
7990 return; \
7991 } \
7992 else if (reg == REG_SP \
7993 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7994 { \
7995 inst.error = BAD_SP; \
7996 return; \
7997 } \
fdfde340
JM
7998 while (0)
7999
94206790
MM
8000/* If REG is R13 (the stack pointer), warn that its use is
8001 deprecated. */
8002#define warn_deprecated_sp(reg) \
8003 do \
8004 if (warn_on_deprecated && reg == REG_SP) \
5c3696f8 8005 as_tsktsk (_("use of r13 is deprecated")); \
94206790
MM
8006 while (0)
8007
c19d1205
ZW
8008/* Functions for operand encoding. ARM, then Thumb. */
8009
d840c081 8010#define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
c19d1205 8011
9db2f6b4
RL
8012/* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8013
8014 The only binary encoding difference is the Coprocessor number. Coprocessor
8015 9 is used for half-precision calculations or conversions. The format of the
2b0f3761 8016 instruction is the same as the equivalent Coprocessor 10 instruction that
9db2f6b4
RL
8017 exists for Single-Precision operation. */
8018
8019static void
8020do_scalar_fp16_v82_encode (void)
8021{
5ee91343 8022 if (inst.cond < COND_ALWAYS)
9db2f6b4
RL
8023 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8024 " the behaviour is UNPREDICTABLE"));
8025 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
8026 _(BAD_FP16));
8027
8028 inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900;
8029 mark_feature_used (&arm_ext_fp16);
8030}
8031
c19d1205
ZW
8032/* If VAL can be encoded in the immediate field of an ARM instruction,
8033 return the encoded form. Otherwise, return FAIL. */
8034
8035static unsigned int
8036encode_arm_immediate (unsigned int val)
09d92015 8037{
c19d1205
ZW
8038 unsigned int a, i;
8039
4f1d6205
L
8040 if (val <= 0xff)
8041 return val;
8042
8043 for (i = 2; i < 32; i += 2)
c19d1205
ZW
8044 if ((a = rotate_left (val, i)) <= 0xff)
8045 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
8046
8047 return FAIL;
09d92015
MM
8048}
8049
c19d1205
ZW
8050/* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8051 return the encoded form. Otherwise, return FAIL. */
8052static unsigned int
8053encode_thumb32_immediate (unsigned int val)
09d92015 8054{
c19d1205 8055 unsigned int a, i;
09d92015 8056
9c3c69f2 8057 if (val <= 0xff)
c19d1205 8058 return val;
a737bd4d 8059
9c3c69f2 8060 for (i = 1; i <= 24; i++)
09d92015 8061 {
9c3c69f2
PB
8062 a = val >> i;
8063 if ((val & ~(0xff << i)) == 0)
8064 return ((val >> i) & 0x7f) | ((32 - i) << 7);
09d92015 8065 }
a737bd4d 8066
c19d1205
ZW
8067 a = val & 0xff;
8068 if (val == ((a << 16) | a))
8069 return 0x100 | a;
8070 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
8071 return 0x300 | a;
09d92015 8072
c19d1205
ZW
8073 a = val & 0xff00;
8074 if (val == ((a << 16) | a))
8075 return 0x200 | (a >> 8);
a737bd4d 8076
c19d1205 8077 return FAIL;
09d92015 8078}
5287ad62 8079/* Encode a VFP SP or DP register number into inst.instruction. */
09d92015
MM
8080
8081static void
5287ad62
JB
8082encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
8083{
8084 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
8085 && reg > 15)
8086 {
b1cc4aeb 8087 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
477330fc
RM
8088 {
8089 if (thumb_mode)
8090 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
8091 fpu_vfp_ext_d32);
8092 else
8093 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
8094 fpu_vfp_ext_d32);
8095 }
5287ad62 8096 else
477330fc
RM
8097 {
8098 first_error (_("D register out of range for selected VFP version"));
8099 return;
8100 }
5287ad62
JB
8101 }
8102
c19d1205 8103 switch (pos)
09d92015 8104 {
c19d1205
ZW
8105 case VFP_REG_Sd:
8106 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
8107 break;
8108
8109 case VFP_REG_Sn:
8110 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
8111 break;
8112
8113 case VFP_REG_Sm:
8114 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
8115 break;
8116
5287ad62
JB
8117 case VFP_REG_Dd:
8118 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
8119 break;
5f4273c7 8120
5287ad62
JB
8121 case VFP_REG_Dn:
8122 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
8123 break;
5f4273c7 8124
5287ad62
JB
8125 case VFP_REG_Dm:
8126 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
8127 break;
8128
c19d1205
ZW
8129 default:
8130 abort ();
09d92015 8131 }
09d92015
MM
8132}
8133
c19d1205 8134/* Encode a <shift> in an ARM-format instruction. The immediate,
55cf6793 8135 if any, is handled by md_apply_fix. */
09d92015 8136static void
c19d1205 8137encode_arm_shift (int i)
09d92015 8138{
008a97ef
RL
8139 /* register-shifted register. */
8140 if (inst.operands[i].immisreg)
8141 {
bf355b69
MR
8142 int op_index;
8143 for (op_index = 0; op_index <= i; ++op_index)
008a97ef 8144 {
5689c942
RL
8145 /* Check the operand only when it's presented. In pre-UAL syntax,
8146 if the destination register is the same as the first operand, two
8147 register form of the instruction can be used. */
bf355b69
MR
8148 if (inst.operands[op_index].present && inst.operands[op_index].isreg
8149 && inst.operands[op_index].reg == REG_PC)
008a97ef
RL
8150 as_warn (UNPRED_REG ("r15"));
8151 }
8152
8153 if (inst.operands[i].imm == REG_PC)
8154 as_warn (UNPRED_REG ("r15"));
8155 }
8156
c19d1205
ZW
8157 if (inst.operands[i].shift_kind == SHIFT_RRX)
8158 inst.instruction |= SHIFT_ROR << 5;
8159 else
09d92015 8160 {
c19d1205
ZW
8161 inst.instruction |= inst.operands[i].shift_kind << 5;
8162 if (inst.operands[i].immisreg)
8163 {
8164 inst.instruction |= SHIFT_BY_REG;
8165 inst.instruction |= inst.operands[i].imm << 8;
8166 }
8167 else
e2b0ab59 8168 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
09d92015 8169 }
c19d1205 8170}
09d92015 8171
c19d1205
ZW
8172static void
8173encode_arm_shifter_operand (int i)
8174{
8175 if (inst.operands[i].isreg)
09d92015 8176 {
c19d1205
ZW
8177 inst.instruction |= inst.operands[i].reg;
8178 encode_arm_shift (i);
09d92015 8179 }
c19d1205 8180 else
a415b1cd
JB
8181 {
8182 inst.instruction |= INST_IMMEDIATE;
e2b0ab59 8183 if (inst.relocs[0].type != BFD_RELOC_ARM_IMMEDIATE)
a415b1cd
JB
8184 inst.instruction |= inst.operands[i].imm;
8185 }
09d92015
MM
8186}
8187
c19d1205 8188/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
09d92015 8189static void
c19d1205 8190encode_arm_addr_mode_common (int i, bfd_boolean is_t)
09d92015 8191{
2b2f5df9
NC
8192 /* PR 14260:
8193 Generate an error if the operand is not a register. */
8194 constraint (!inst.operands[i].isreg,
8195 _("Instruction does not support =N addresses"));
8196
c19d1205 8197 inst.instruction |= inst.operands[i].reg << 16;
a737bd4d 8198
c19d1205 8199 if (inst.operands[i].preind)
09d92015 8200 {
c19d1205
ZW
8201 if (is_t)
8202 {
8203 inst.error = _("instruction does not accept preindexed addressing");
8204 return;
8205 }
8206 inst.instruction |= PRE_INDEX;
8207 if (inst.operands[i].writeback)
8208 inst.instruction |= WRITE_BACK;
09d92015 8209
c19d1205
ZW
8210 }
8211 else if (inst.operands[i].postind)
8212 {
9c2799c2 8213 gas_assert (inst.operands[i].writeback);
c19d1205
ZW
8214 if (is_t)
8215 inst.instruction |= WRITE_BACK;
8216 }
8217 else /* unindexed - only for coprocessor */
09d92015 8218 {
c19d1205 8219 inst.error = _("instruction does not accept unindexed addressing");
09d92015
MM
8220 return;
8221 }
8222
c19d1205
ZW
8223 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
8224 && (((inst.instruction & 0x000f0000) >> 16)
8225 == ((inst.instruction & 0x0000f000) >> 12)))
8226 as_warn ((inst.instruction & LOAD_BIT)
8227 ? _("destination register same as write-back base")
8228 : _("source register same as write-back base"));
09d92015
MM
8229}
8230
c19d1205
ZW
8231/* inst.operands[i] was set up by parse_address. Encode it into an
8232 ARM-format mode 2 load or store instruction. If is_t is true,
8233 reject forms that cannot be used with a T instruction (i.e. not
8234 post-indexed). */
a737bd4d 8235static void
c19d1205 8236encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
09d92015 8237{
5be8be5d
DG
8238 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
8239
c19d1205 8240 encode_arm_addr_mode_common (i, is_t);
a737bd4d 8241
c19d1205 8242 if (inst.operands[i].immisreg)
09d92015 8243 {
5be8be5d
DG
8244 constraint ((inst.operands[i].imm == REG_PC
8245 || (is_pc && inst.operands[i].writeback)),
8246 BAD_PC_ADDRESSING);
c19d1205
ZW
8247 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
8248 inst.instruction |= inst.operands[i].imm;
8249 if (!inst.operands[i].negative)
8250 inst.instruction |= INDEX_UP;
8251 if (inst.operands[i].shifted)
8252 {
8253 if (inst.operands[i].shift_kind == SHIFT_RRX)
8254 inst.instruction |= SHIFT_ROR << 5;
8255 else
8256 {
8257 inst.instruction |= inst.operands[i].shift_kind << 5;
e2b0ab59 8258 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
c19d1205
ZW
8259 }
8260 }
09d92015 8261 }
e2b0ab59 8262 else /* immediate offset in inst.relocs[0] */
09d92015 8263 {
e2b0ab59 8264 if (is_pc && !inst.relocs[0].pc_rel)
5be8be5d
DG
8265 {
8266 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
23a10334
JZ
8267
8268 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8269 cannot use PC in addressing.
8270 PC cannot be used in writeback addressing, either. */
8271 constraint ((is_t || inst.operands[i].writeback),
5be8be5d 8272 BAD_PC_ADDRESSING);
23a10334 8273
dc5ec521 8274 /* Use of PC in str is deprecated for ARMv7. */
23a10334
JZ
8275 if (warn_on_deprecated
8276 && !is_load
8277 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
5c3696f8 8278 as_tsktsk (_("use of PC in this instruction is deprecated"));
5be8be5d
DG
8279 }
8280
e2b0ab59 8281 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
26d97720
NS
8282 {
8283 /* Prefer + for zero encoded value. */
8284 if (!inst.operands[i].negative)
8285 inst.instruction |= INDEX_UP;
e2b0ab59 8286 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM;
26d97720 8287 }
09d92015 8288 }
09d92015
MM
8289}
8290
c19d1205
ZW
8291/* inst.operands[i] was set up by parse_address. Encode it into an
8292 ARM-format mode 3 load or store instruction. Reject forms that
8293 cannot be used with such instructions. If is_t is true, reject
8294 forms that cannot be used with a T instruction (i.e. not
8295 post-indexed). */
8296static void
8297encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
09d92015 8298{
c19d1205 8299 if (inst.operands[i].immisreg && inst.operands[i].shifted)
09d92015 8300 {
c19d1205
ZW
8301 inst.error = _("instruction does not accept scaled register index");
8302 return;
09d92015 8303 }
a737bd4d 8304
c19d1205 8305 encode_arm_addr_mode_common (i, is_t);
a737bd4d 8306
c19d1205
ZW
8307 if (inst.operands[i].immisreg)
8308 {
5be8be5d 8309 constraint ((inst.operands[i].imm == REG_PC
eb9f3f00 8310 || (is_t && inst.operands[i].reg == REG_PC)),
5be8be5d 8311 BAD_PC_ADDRESSING);
eb9f3f00
JB
8312 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
8313 BAD_PC_WRITEBACK);
c19d1205
ZW
8314 inst.instruction |= inst.operands[i].imm;
8315 if (!inst.operands[i].negative)
8316 inst.instruction |= INDEX_UP;
8317 }
e2b0ab59 8318 else /* immediate offset in inst.relocs[0] */
c19d1205 8319 {
e2b0ab59 8320 constraint ((inst.operands[i].reg == REG_PC && !inst.relocs[0].pc_rel
5be8be5d
DG
8321 && inst.operands[i].writeback),
8322 BAD_PC_WRITEBACK);
c19d1205 8323 inst.instruction |= HWOFFSET_IMM;
e2b0ab59 8324 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
26d97720
NS
8325 {
8326 /* Prefer + for zero encoded value. */
8327 if (!inst.operands[i].negative)
8328 inst.instruction |= INDEX_UP;
8329
e2b0ab59 8330 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM8;
26d97720 8331 }
c19d1205 8332 }
a737bd4d
NC
8333}
8334
8335d6aa
JW
8335/* Write immediate bits [7:0] to the following locations:
8336
8337 |28/24|23 19|18 16|15 4|3 0|
8338 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8339
8340 This function is used by VMOV/VMVN/VORR/VBIC. */
8341
8342static void
8343neon_write_immbits (unsigned immbits)
8344{
8345 inst.instruction |= immbits & 0xf;
8346 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
8347 inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24);
8348}
8349
8350/* Invert low-order SIZE bits of XHI:XLO. */
8351
8352static void
8353neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
8354{
8355 unsigned immlo = xlo ? *xlo : 0;
8356 unsigned immhi = xhi ? *xhi : 0;
8357
8358 switch (size)
8359 {
8360 case 8:
8361 immlo = (~immlo) & 0xff;
8362 break;
8363
8364 case 16:
8365 immlo = (~immlo) & 0xffff;
8366 break;
8367
8368 case 64:
8369 immhi = (~immhi) & 0xffffffff;
8370 /* fall through. */
8371
8372 case 32:
8373 immlo = (~immlo) & 0xffffffff;
8374 break;
8375
8376 default:
8377 abort ();
8378 }
8379
8380 if (xlo)
8381 *xlo = immlo;
8382
8383 if (xhi)
8384 *xhi = immhi;
8385}
8386
8387/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8388 A, B, C, D. */
09d92015 8389
c19d1205 8390static int
8335d6aa 8391neon_bits_same_in_bytes (unsigned imm)
09d92015 8392{
8335d6aa
JW
8393 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
8394 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
8395 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
8396 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
8397}
a737bd4d 8398
8335d6aa 8399/* For immediate of above form, return 0bABCD. */
09d92015 8400
8335d6aa
JW
8401static unsigned
8402neon_squash_bits (unsigned imm)
8403{
8404 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
8405 | ((imm & 0x01000000) >> 21);
8406}
8407
8408/* Compress quarter-float representation to 0b...000 abcdefgh. */
8409
8410static unsigned
8411neon_qfloat_bits (unsigned imm)
8412{
8413 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
8414}
8415
8416/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8417 the instruction. *OP is passed as the initial value of the op field, and
8418 may be set to a different value depending on the constant (i.e.
8419 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8420 MVN). If the immediate looks like a repeated pattern then also
8421 try smaller element sizes. */
8422
8423static int
8424neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
8425 unsigned *immbits, int *op, int size,
8426 enum neon_el_type type)
8427{
8428 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8429 float. */
8430 if (type == NT_float && !float_p)
8431 return FAIL;
8432
8433 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
09d92015 8434 {
8335d6aa
JW
8435 if (size != 32 || *op == 1)
8436 return FAIL;
8437 *immbits = neon_qfloat_bits (immlo);
8438 return 0xf;
8439 }
8440
8441 if (size == 64)
8442 {
8443 if (neon_bits_same_in_bytes (immhi)
8444 && neon_bits_same_in_bytes (immlo))
c19d1205 8445 {
8335d6aa
JW
8446 if (*op == 1)
8447 return FAIL;
8448 *immbits = (neon_squash_bits (immhi) << 4)
8449 | neon_squash_bits (immlo);
8450 *op = 1;
8451 return 0xe;
c19d1205 8452 }
a737bd4d 8453
8335d6aa
JW
8454 if (immhi != immlo)
8455 return FAIL;
8456 }
a737bd4d 8457
8335d6aa 8458 if (size >= 32)
09d92015 8459 {
8335d6aa 8460 if (immlo == (immlo & 0x000000ff))
c19d1205 8461 {
8335d6aa
JW
8462 *immbits = immlo;
8463 return 0x0;
c19d1205 8464 }
8335d6aa 8465 else if (immlo == (immlo & 0x0000ff00))
c19d1205 8466 {
8335d6aa
JW
8467 *immbits = immlo >> 8;
8468 return 0x2;
c19d1205 8469 }
8335d6aa
JW
8470 else if (immlo == (immlo & 0x00ff0000))
8471 {
8472 *immbits = immlo >> 16;
8473 return 0x4;
8474 }
8475 else if (immlo == (immlo & 0xff000000))
8476 {
8477 *immbits = immlo >> 24;
8478 return 0x6;
8479 }
8480 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
8481 {
8482 *immbits = (immlo >> 8) & 0xff;
8483 return 0xc;
8484 }
8485 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
8486 {
8487 *immbits = (immlo >> 16) & 0xff;
8488 return 0xd;
8489 }
8490
8491 if ((immlo & 0xffff) != (immlo >> 16))
8492 return FAIL;
8493 immlo &= 0xffff;
09d92015 8494 }
a737bd4d 8495
8335d6aa 8496 if (size >= 16)
4962c51a 8497 {
8335d6aa
JW
8498 if (immlo == (immlo & 0x000000ff))
8499 {
8500 *immbits = immlo;
8501 return 0x8;
8502 }
8503 else if (immlo == (immlo & 0x0000ff00))
8504 {
8505 *immbits = immlo >> 8;
8506 return 0xa;
8507 }
8508
8509 if ((immlo & 0xff) != (immlo >> 8))
8510 return FAIL;
8511 immlo &= 0xff;
4962c51a
MS
8512 }
8513
8335d6aa
JW
8514 if (immlo == (immlo & 0x000000ff))
8515 {
8516 /* Don't allow MVN with 8-bit immediate. */
8517 if (*op == 1)
8518 return FAIL;
8519 *immbits = immlo;
8520 return 0xe;
8521 }
26d97720 8522
8335d6aa 8523 return FAIL;
c19d1205 8524}
a737bd4d 8525
5fc177c8 8526#if defined BFD_HOST_64_BIT
ba592044
AM
8527/* Returns TRUE if double precision value V may be cast
8528 to single precision without loss of accuracy. */
8529
8530static bfd_boolean
5fc177c8 8531is_double_a_single (bfd_int64_t v)
ba592044 8532{
5fc177c8 8533 int exp = (int)((v >> 52) & 0x7FF);
8fe3f3d6 8534 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
ba592044
AM
8535
8536 return (exp == 0 || exp == 0x7FF
8537 || (exp >= 1023 - 126 && exp <= 1023 + 127))
8538 && (mantissa & 0x1FFFFFFFl) == 0;
8539}
8540
3739860c 8541/* Returns a double precision value casted to single precision
ba592044
AM
8542 (ignoring the least significant bits in exponent and mantissa). */
8543
8544static int
5fc177c8 8545double_to_single (bfd_int64_t v)
ba592044
AM
8546{
8547 int sign = (int) ((v >> 63) & 1l);
5fc177c8 8548 int exp = (int) ((v >> 52) & 0x7FF);
8fe3f3d6 8549 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
ba592044
AM
8550
8551 if (exp == 0x7FF)
8552 exp = 0xFF;
8553 else
8554 {
8555 exp = exp - 1023 + 127;
8556 if (exp >= 0xFF)
8557 {
8558 /* Infinity. */
8559 exp = 0x7F;
8560 mantissa = 0;
8561 }
8562 else if (exp < 0)
8563 {
8564 /* No denormalized numbers. */
8565 exp = 0;
8566 mantissa = 0;
8567 }
8568 }
8569 mantissa >>= 29;
8570 return (sign << 31) | (exp << 23) | mantissa;
8571}
5fc177c8 8572#endif /* BFD_HOST_64_BIT */
ba592044 8573
8335d6aa
JW
8574enum lit_type
8575{
8576 CONST_THUMB,
8577 CONST_ARM,
8578 CONST_VEC
8579};
8580
ba592044
AM
8581static void do_vfp_nsyn_opcode (const char *);
8582
e2b0ab59 8583/* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
c19d1205
ZW
8584 Determine whether it can be performed with a move instruction; if
8585 it can, convert inst.instruction to that move instruction and
c921be7d
NC
8586 return TRUE; if it can't, convert inst.instruction to a literal-pool
8587 load and return FALSE. If this is not a valid thing to do in the
8588 current context, set inst.error and return TRUE.
a737bd4d 8589
c19d1205
ZW
8590 inst.operands[i] describes the destination register. */
8591
c921be7d 8592static bfd_boolean
8335d6aa 8593move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
c19d1205 8594{
53365c0d 8595 unsigned long tbit;
8335d6aa
JW
8596 bfd_boolean thumb_p = (t == CONST_THUMB);
8597 bfd_boolean arm_p = (t == CONST_ARM);
53365c0d
PB
8598
8599 if (thumb_p)
8600 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
8601 else
8602 tbit = LOAD_BIT;
8603
8604 if ((inst.instruction & tbit) == 0)
09d92015 8605 {
c19d1205 8606 inst.error = _("invalid pseudo operation");
c921be7d 8607 return TRUE;
09d92015 8608 }
ba592044 8609
e2b0ab59
AV
8610 if (inst.relocs[0].exp.X_op != O_constant
8611 && inst.relocs[0].exp.X_op != O_symbol
8612 && inst.relocs[0].exp.X_op != O_big)
09d92015
MM
8613 {
8614 inst.error = _("constant expression expected");
c921be7d 8615 return TRUE;
09d92015 8616 }
ba592044 8617
e2b0ab59
AV
8618 if (inst.relocs[0].exp.X_op == O_constant
8619 || inst.relocs[0].exp.X_op == O_big)
8335d6aa 8620 {
5fc177c8
NC
8621#if defined BFD_HOST_64_BIT
8622 bfd_int64_t v;
8623#else
ba592044 8624 offsetT v;
5fc177c8 8625#endif
e2b0ab59 8626 if (inst.relocs[0].exp.X_op == O_big)
8335d6aa 8627 {
ba592044
AM
8628 LITTLENUM_TYPE w[X_PRECISION];
8629 LITTLENUM_TYPE * l;
8630
e2b0ab59 8631 if (inst.relocs[0].exp.X_add_number == -1)
8335d6aa 8632 {
ba592044
AM
8633 gen_to_words (w, X_PRECISION, E_PRECISION);
8634 l = w;
8635 /* FIXME: Should we check words w[2..5] ? */
8335d6aa 8636 }
ba592044
AM
8637 else
8638 l = generic_bignum;
3739860c 8639
5fc177c8
NC
8640#if defined BFD_HOST_64_BIT
8641 v =
8642 ((((((((bfd_int64_t) l[3] & LITTLENUM_MASK)
8643 << LITTLENUM_NUMBER_OF_BITS)
8644 | ((bfd_int64_t) l[2] & LITTLENUM_MASK))
8645 << LITTLENUM_NUMBER_OF_BITS)
8646 | ((bfd_int64_t) l[1] & LITTLENUM_MASK))
8647 << LITTLENUM_NUMBER_OF_BITS)
8648 | ((bfd_int64_t) l[0] & LITTLENUM_MASK));
8649#else
ba592044
AM
8650 v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS)
8651 | (l[0] & LITTLENUM_MASK);
5fc177c8 8652#endif
8335d6aa 8653 }
ba592044 8654 else
e2b0ab59 8655 v = inst.relocs[0].exp.X_add_number;
ba592044
AM
8656
8657 if (!inst.operands[i].issingle)
8335d6aa 8658 {
12569877 8659 if (thumb_p)
8335d6aa 8660 {
53445554
TP
8661 /* LDR should not use lead in a flag-setting instruction being
8662 chosen so we do not check whether movs can be used. */
12569877 8663
53445554 8664 if ((ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
ff8646ee 8665 || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
53445554
TP
8666 && inst.operands[i].reg != 13
8667 && inst.operands[i].reg != 15)
12569877 8668 {
fc289b0a
TP
8669 /* Check if on thumb2 it can be done with a mov.w, mvn or
8670 movw instruction. */
12569877
AM
8671 unsigned int newimm;
8672 bfd_boolean isNegated;
8673
8674 newimm = encode_thumb32_immediate (v);
8675 if (newimm != (unsigned int) FAIL)
8676 isNegated = FALSE;
8677 else
8678 {
582cfe03 8679 newimm = encode_thumb32_immediate (~v);
12569877
AM
8680 if (newimm != (unsigned int) FAIL)
8681 isNegated = TRUE;
8682 }
8683
fc289b0a
TP
8684 /* The number can be loaded with a mov.w or mvn
8685 instruction. */
ff8646ee
TP
8686 if (newimm != (unsigned int) FAIL
8687 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
12569877 8688 {
fc289b0a 8689 inst.instruction = (0xf04f0000 /* MOV.W. */
582cfe03 8690 | (inst.operands[i].reg << 8));
fc289b0a 8691 /* Change to MOVN. */
582cfe03 8692 inst.instruction |= (isNegated ? 0x200000 : 0);
12569877
AM
8693 inst.instruction |= (newimm & 0x800) << 15;
8694 inst.instruction |= (newimm & 0x700) << 4;
8695 inst.instruction |= (newimm & 0x0ff);
8696 return TRUE;
8697 }
fc289b0a 8698 /* The number can be loaded with a movw instruction. */
ff8646ee
TP
8699 else if ((v & ~0xFFFF) == 0
8700 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
3739860c 8701 {
582cfe03 8702 int imm = v & 0xFFFF;
12569877 8703
582cfe03 8704 inst.instruction = 0xf2400000; /* MOVW. */
12569877
AM
8705 inst.instruction |= (inst.operands[i].reg << 8);
8706 inst.instruction |= (imm & 0xf000) << 4;
8707 inst.instruction |= (imm & 0x0800) << 15;
8708 inst.instruction |= (imm & 0x0700) << 4;
8709 inst.instruction |= (imm & 0x00ff);
8fe9a076
AV
8710 /* In case this replacement is being done on Armv8-M
8711 Baseline we need to make sure to disable the
8712 instruction size check, as otherwise GAS will reject
8713 the use of this T32 instruction. */
8714 inst.size_req = 0;
12569877
AM
8715 return TRUE;
8716 }
8717 }
8335d6aa 8718 }
12569877 8719 else if (arm_p)
ba592044
AM
8720 {
8721 int value = encode_arm_immediate (v);
12569877 8722
ba592044
AM
8723 if (value != FAIL)
8724 {
8725 /* This can be done with a mov instruction. */
8726 inst.instruction &= LITERAL_MASK;
8727 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
8728 inst.instruction |= value & 0xfff;
8729 return TRUE;
8730 }
8335d6aa 8731
ba592044
AM
8732 value = encode_arm_immediate (~ v);
8733 if (value != FAIL)
8734 {
8735 /* This can be done with a mvn instruction. */
8736 inst.instruction &= LITERAL_MASK;
8737 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
8738 inst.instruction |= value & 0xfff;
8739 return TRUE;
8740 }
8741 }
934c2632 8742 else if (t == CONST_VEC && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
8335d6aa 8743 {
ba592044
AM
8744 int op = 0;
8745 unsigned immbits = 0;
8746 unsigned immlo = inst.operands[1].imm;
8747 unsigned immhi = inst.operands[1].regisimm
8748 ? inst.operands[1].reg
e2b0ab59 8749 : inst.relocs[0].exp.X_unsigned
ba592044
AM
8750 ? 0
8751 : ((bfd_int64_t)((int) immlo)) >> 32;
8752 int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8753 &op, 64, NT_invtype);
8754
8755 if (cmode == FAIL)
8756 {
8757 neon_invert_size (&immlo, &immhi, 64);
8758 op = !op;
8759 cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8760 &op, 64, NT_invtype);
8761 }
8762
8763 if (cmode != FAIL)
8764 {
8765 inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
8766 | (1 << 23)
8767 | (cmode << 8)
8768 | (op << 5)
8769 | (1 << 4);
8770
8771 /* Fill other bits in vmov encoding for both thumb and arm. */
8772 if (thumb_mode)
eff0bc54 8773 inst.instruction |= (0x7U << 29) | (0xF << 24);
ba592044 8774 else
eff0bc54 8775 inst.instruction |= (0xFU << 28) | (0x1 << 25);
ba592044
AM
8776 neon_write_immbits (immbits);
8777 return TRUE;
8778 }
8335d6aa
JW
8779 }
8780 }
8335d6aa 8781
ba592044
AM
8782 if (t == CONST_VEC)
8783 {
8784 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8785 if (inst.operands[i].issingle
8786 && is_quarter_float (inst.operands[1].imm)
8787 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd))
8335d6aa 8788 {
ba592044
AM
8789 inst.operands[1].imm =
8790 neon_qfloat_bits (v);
8791 do_vfp_nsyn_opcode ("fconsts");
8792 return TRUE;
8335d6aa 8793 }
5fc177c8
NC
8794
8795 /* If our host does not support a 64-bit type then we cannot perform
8796 the following optimization. This mean that there will be a
8797 discrepancy between the output produced by an assembler built for
8798 a 32-bit-only host and the output produced from a 64-bit host, but
8799 this cannot be helped. */
8800#if defined BFD_HOST_64_BIT
ba592044
AM
8801 else if (!inst.operands[1].issingle
8802 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
8335d6aa 8803 {
ba592044
AM
8804 if (is_double_a_single (v)
8805 && is_quarter_float (double_to_single (v)))
8806 {
8807 inst.operands[1].imm =
8808 neon_qfloat_bits (double_to_single (v));
8809 do_vfp_nsyn_opcode ("fconstd");
8810 return TRUE;
8811 }
8335d6aa 8812 }
5fc177c8 8813#endif
8335d6aa
JW
8814 }
8815 }
8816
8817 if (add_to_lit_pool ((!inst.operands[i].isvec
8818 || inst.operands[i].issingle) ? 4 : 8) == FAIL)
8819 return TRUE;
8820
8821 inst.operands[1].reg = REG_PC;
8822 inst.operands[1].isreg = 1;
8823 inst.operands[1].preind = 1;
e2b0ab59
AV
8824 inst.relocs[0].pc_rel = 1;
8825 inst.relocs[0].type = (thumb_p
8335d6aa
JW
8826 ? BFD_RELOC_ARM_THUMB_OFFSET
8827 : (mode_3
8828 ? BFD_RELOC_ARM_HWLITERAL
8829 : BFD_RELOC_ARM_LITERAL));
8830 return FALSE;
8831}
8832
8833/* inst.operands[i] was set up by parse_address. Encode it into an
8834 ARM-format instruction. Reject all forms which cannot be encoded
8835 into a coprocessor load/store instruction. If wb_ok is false,
8836 reject use of writeback; if unind_ok is false, reject use of
8837 unindexed addressing. If reloc_override is not 0, use it instead
8838 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8839 (in which case it is preserved). */
8840
8841static int
8842encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
8843{
8844 if (!inst.operands[i].isreg)
8845 {
99b2a2dd
NC
8846 /* PR 18256 */
8847 if (! inst.operands[0].isvec)
8848 {
8849 inst.error = _("invalid co-processor operand");
8850 return FAIL;
8851 }
8335d6aa
JW
8852 if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE))
8853 return SUCCESS;
8854 }
8855
8856 inst.instruction |= inst.operands[i].reg << 16;
8857
8858 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
8859
8860 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
8861 {
8862 gas_assert (!inst.operands[i].writeback);
8863 if (!unind_ok)
8864 {
8865 inst.error = _("instruction does not support unindexed addressing");
8866 return FAIL;
8867 }
8868 inst.instruction |= inst.operands[i].imm;
8869 inst.instruction |= INDEX_UP;
8870 return SUCCESS;
8871 }
8872
8873 if (inst.operands[i].preind)
8874 inst.instruction |= PRE_INDEX;
8875
8876 if (inst.operands[i].writeback)
09d92015 8877 {
8335d6aa 8878 if (inst.operands[i].reg == REG_PC)
c19d1205 8879 {
8335d6aa
JW
8880 inst.error = _("pc may not be used with write-back");
8881 return FAIL;
c19d1205 8882 }
8335d6aa 8883 if (!wb_ok)
c19d1205 8884 {
8335d6aa
JW
8885 inst.error = _("instruction does not support writeback");
8886 return FAIL;
c19d1205 8887 }
8335d6aa 8888 inst.instruction |= WRITE_BACK;
09d92015
MM
8889 }
8890
8335d6aa 8891 if (reloc_override)
e2b0ab59
AV
8892 inst.relocs[0].type = (bfd_reloc_code_real_type) reloc_override;
8893 else if ((inst.relocs[0].type < BFD_RELOC_ARM_ALU_PC_G0_NC
8894 || inst.relocs[0].type > BFD_RELOC_ARM_LDC_SB_G2)
8895 && inst.relocs[0].type != BFD_RELOC_ARM_LDR_PC_G0)
c19d1205 8896 {
8335d6aa 8897 if (thumb_mode)
e2b0ab59 8898 inst.relocs[0].type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
8335d6aa 8899 else
e2b0ab59 8900 inst.relocs[0].type = BFD_RELOC_ARM_CP_OFF_IMM;
c19d1205 8901 }
8335d6aa
JW
8902
8903 /* Prefer + for zero encoded value. */
8904 if (!inst.operands[i].negative)
8905 inst.instruction |= INDEX_UP;
8906
8907 return SUCCESS;
09d92015
MM
8908}
8909
5f4273c7 8910/* Functions for instruction encoding, sorted by sub-architecture.
c19d1205
ZW
8911 First some generics; their names are taken from the conventional
8912 bit positions for register arguments in ARM format instructions. */
09d92015 8913
a737bd4d 8914static void
c19d1205 8915do_noargs (void)
09d92015 8916{
c19d1205 8917}
a737bd4d 8918
c19d1205
ZW
8919static void
8920do_rd (void)
8921{
8922 inst.instruction |= inst.operands[0].reg << 12;
8923}
a737bd4d 8924
16a1fa25
TP
8925static void
8926do_rn (void)
8927{
8928 inst.instruction |= inst.operands[0].reg << 16;
8929}
8930
c19d1205
ZW
8931static void
8932do_rd_rm (void)
8933{
8934 inst.instruction |= inst.operands[0].reg << 12;
8935 inst.instruction |= inst.operands[1].reg;
8936}
09d92015 8937
9eb6c0f1
MGD
8938static void
8939do_rm_rn (void)
8940{
8941 inst.instruction |= inst.operands[0].reg;
8942 inst.instruction |= inst.operands[1].reg << 16;
8943}
8944
c19d1205
ZW
8945static void
8946do_rd_rn (void)
8947{
8948 inst.instruction |= inst.operands[0].reg << 12;
8949 inst.instruction |= inst.operands[1].reg << 16;
8950}
a737bd4d 8951
c19d1205
ZW
8952static void
8953do_rn_rd (void)
8954{
8955 inst.instruction |= inst.operands[0].reg << 16;
8956 inst.instruction |= inst.operands[1].reg << 12;
8957}
09d92015 8958
4ed7ed8d
TP
8959static void
8960do_tt (void)
8961{
8962 inst.instruction |= inst.operands[0].reg << 8;
8963 inst.instruction |= inst.operands[1].reg << 16;
8964}
8965
59d09be6
MGD
8966static bfd_boolean
8967check_obsolete (const arm_feature_set *feature, const char *msg)
8968{
8969 if (ARM_CPU_IS_ANY (cpu_variant))
8970 {
5c3696f8 8971 as_tsktsk ("%s", msg);
59d09be6
MGD
8972 return TRUE;
8973 }
8974 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
8975 {
8976 as_bad ("%s", msg);
8977 return TRUE;
8978 }
8979
8980 return FALSE;
8981}
8982
c19d1205
ZW
8983static void
8984do_rd_rm_rn (void)
8985{
9a64e435 8986 unsigned Rn = inst.operands[2].reg;
708587a4 8987 /* Enforce restrictions on SWP instruction. */
9a64e435 8988 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
56adecf4
DG
8989 {
8990 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
8991 _("Rn must not overlap other operands"));
8992
59d09be6
MGD
8993 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8994 */
8995 if (!check_obsolete (&arm_ext_v8,
8996 _("swp{b} use is obsoleted for ARMv8 and later"))
8997 && warn_on_deprecated
8998 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
5c3696f8 8999 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
56adecf4 9000 }
59d09be6 9001
c19d1205
ZW
9002 inst.instruction |= inst.operands[0].reg << 12;
9003 inst.instruction |= inst.operands[1].reg;
9a64e435 9004 inst.instruction |= Rn << 16;
c19d1205 9005}
09d92015 9006
c19d1205
ZW
9007static void
9008do_rd_rn_rm (void)
9009{
9010 inst.instruction |= inst.operands[0].reg << 12;
9011 inst.instruction |= inst.operands[1].reg << 16;
9012 inst.instruction |= inst.operands[2].reg;
9013}
a737bd4d 9014
c19d1205
ZW
9015static void
9016do_rm_rd_rn (void)
9017{
5be8be5d 9018 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
e2b0ab59
AV
9019 constraint (((inst.relocs[0].exp.X_op != O_constant
9020 && inst.relocs[0].exp.X_op != O_illegal)
9021 || inst.relocs[0].exp.X_add_number != 0),
5be8be5d 9022 BAD_ADDR_MODE);
c19d1205
ZW
9023 inst.instruction |= inst.operands[0].reg;
9024 inst.instruction |= inst.operands[1].reg << 12;
9025 inst.instruction |= inst.operands[2].reg << 16;
9026}
09d92015 9027
c19d1205
ZW
9028static void
9029do_imm0 (void)
9030{
9031 inst.instruction |= inst.operands[0].imm;
9032}
09d92015 9033
c19d1205
ZW
9034static void
9035do_rd_cpaddr (void)
9036{
9037 inst.instruction |= inst.operands[0].reg << 12;
9038 encode_arm_cp_address (1, TRUE, TRUE, 0);
09d92015 9039}
a737bd4d 9040
c19d1205
ZW
9041/* ARM instructions, in alphabetical order by function name (except
9042 that wrapper functions appear immediately after the function they
9043 wrap). */
09d92015 9044
c19d1205
ZW
9045/* This is a pseudo-op of the form "adr rd, label" to be converted
9046 into a relative address of the form "add rd, pc, #label-.-8". */
09d92015
MM
9047
9048static void
c19d1205 9049do_adr (void)
09d92015 9050{
c19d1205 9051 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 9052
c19d1205
ZW
9053 /* Frag hacking will turn this into a sub instruction if the offset turns
9054 out to be negative. */
e2b0ab59
AV
9055 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
9056 inst.relocs[0].pc_rel = 1;
9057 inst.relocs[0].exp.X_add_number -= 8;
52a86f84 9058
fc6141f0 9059 if (support_interwork
e2b0ab59
AV
9060 && inst.relocs[0].exp.X_op == O_symbol
9061 && inst.relocs[0].exp.X_add_symbol != NULL
9062 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9063 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9064 inst.relocs[0].exp.X_add_number |= 1;
c19d1205 9065}
b99bd4ef 9066
c19d1205
ZW
9067/* This is a pseudo-op of the form "adrl rd, label" to be converted
9068 into a relative address of the form:
9069 add rd, pc, #low(label-.-8)"
9070 add rd, rd, #high(label-.-8)" */
b99bd4ef 9071
c19d1205
ZW
9072static void
9073do_adrl (void)
9074{
9075 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 9076
c19d1205
ZW
9077 /* Frag hacking will turn this into a sub instruction if the offset turns
9078 out to be negative. */
e2b0ab59
AV
9079 inst.relocs[0].type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
9080 inst.relocs[0].pc_rel = 1;
c19d1205 9081 inst.size = INSN_SIZE * 2;
e2b0ab59 9082 inst.relocs[0].exp.X_add_number -= 8;
52a86f84 9083
fc6141f0 9084 if (support_interwork
e2b0ab59
AV
9085 && inst.relocs[0].exp.X_op == O_symbol
9086 && inst.relocs[0].exp.X_add_symbol != NULL
9087 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9088 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9089 inst.relocs[0].exp.X_add_number |= 1;
b99bd4ef
NC
9090}
9091
b99bd4ef 9092static void
c19d1205 9093do_arit (void)
b99bd4ef 9094{
e2b0ab59
AV
9095 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9096 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
a9f02af8 9097 THUMB1_RELOC_ONLY);
c19d1205
ZW
9098 if (!inst.operands[1].present)
9099 inst.operands[1].reg = inst.operands[0].reg;
9100 inst.instruction |= inst.operands[0].reg << 12;
9101 inst.instruction |= inst.operands[1].reg << 16;
9102 encode_arm_shifter_operand (2);
9103}
b99bd4ef 9104
62b3e311
PB
9105static void
9106do_barrier (void)
9107{
9108 if (inst.operands[0].present)
ccb84d65 9109 inst.instruction |= inst.operands[0].imm;
62b3e311
PB
9110 else
9111 inst.instruction |= 0xf;
9112}
9113
c19d1205
ZW
9114static void
9115do_bfc (void)
9116{
9117 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9118 constraint (msb > 32, _("bit-field extends past end of register"));
9119 /* The instruction encoding stores the LSB and MSB,
9120 not the LSB and width. */
9121 inst.instruction |= inst.operands[0].reg << 12;
9122 inst.instruction |= inst.operands[1].imm << 7;
9123 inst.instruction |= (msb - 1) << 16;
9124}
b99bd4ef 9125
c19d1205
ZW
9126static void
9127do_bfi (void)
9128{
9129 unsigned int msb;
b99bd4ef 9130
c19d1205
ZW
9131 /* #0 in second position is alternative syntax for bfc, which is
9132 the same instruction but with REG_PC in the Rm field. */
9133 if (!inst.operands[1].isreg)
9134 inst.operands[1].reg = REG_PC;
b99bd4ef 9135
c19d1205
ZW
9136 msb = inst.operands[2].imm + inst.operands[3].imm;
9137 constraint (msb > 32, _("bit-field extends past end of register"));
9138 /* The instruction encoding stores the LSB and MSB,
9139 not the LSB and width. */
9140 inst.instruction |= inst.operands[0].reg << 12;
9141 inst.instruction |= inst.operands[1].reg;
9142 inst.instruction |= inst.operands[2].imm << 7;
9143 inst.instruction |= (msb - 1) << 16;
b99bd4ef
NC
9144}
9145
b99bd4ef 9146static void
c19d1205 9147do_bfx (void)
b99bd4ef 9148{
c19d1205
ZW
9149 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9150 _("bit-field extends past end of register"));
9151 inst.instruction |= inst.operands[0].reg << 12;
9152 inst.instruction |= inst.operands[1].reg;
9153 inst.instruction |= inst.operands[2].imm << 7;
9154 inst.instruction |= (inst.operands[3].imm - 1) << 16;
9155}
09d92015 9156
c19d1205
ZW
9157/* ARM V5 breakpoint instruction (argument parse)
9158 BKPT <16 bit unsigned immediate>
9159 Instruction is not conditional.
9160 The bit pattern given in insns[] has the COND_ALWAYS condition,
9161 and it is an error if the caller tried to override that. */
b99bd4ef 9162
c19d1205
ZW
9163static void
9164do_bkpt (void)
9165{
9166 /* Top 12 of 16 bits to bits 19:8. */
9167 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
09d92015 9168
c19d1205
ZW
9169 /* Bottom 4 of 16 bits to bits 3:0. */
9170 inst.instruction |= inst.operands[0].imm & 0xf;
9171}
09d92015 9172
c19d1205
ZW
9173static void
9174encode_branch (int default_reloc)
9175{
9176 if (inst.operands[0].hasreloc)
9177 {
0855e32b
NS
9178 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
9179 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
9180 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
e2b0ab59 9181 inst.relocs[0].type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
0855e32b
NS
9182 ? BFD_RELOC_ARM_PLT32
9183 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
c19d1205 9184 }
b99bd4ef 9185 else
e2b0ab59
AV
9186 inst.relocs[0].type = (bfd_reloc_code_real_type) default_reloc;
9187 inst.relocs[0].pc_rel = 1;
b99bd4ef
NC
9188}
9189
b99bd4ef 9190static void
c19d1205 9191do_branch (void)
b99bd4ef 9192{
39b41c9c
PB
9193#ifdef OBJ_ELF
9194 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
9195 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
9196 else
9197#endif
9198 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
9199}
9200
9201static void
9202do_bl (void)
9203{
9204#ifdef OBJ_ELF
9205 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
9206 {
9207 if (inst.cond == COND_ALWAYS)
9208 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
9209 else
9210 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
9211 }
9212 else
9213#endif
9214 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
c19d1205 9215}
b99bd4ef 9216
c19d1205
ZW
9217/* ARM V5 branch-link-exchange instruction (argument parse)
9218 BLX <target_addr> ie BLX(1)
9219 BLX{<condition>} <Rm> ie BLX(2)
9220 Unfortunately, there are two different opcodes for this mnemonic.
9221 So, the insns[].value is not used, and the code here zaps values
9222 into inst.instruction.
9223 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
b99bd4ef 9224
c19d1205
ZW
9225static void
9226do_blx (void)
9227{
9228 if (inst.operands[0].isreg)
b99bd4ef 9229 {
c19d1205
ZW
9230 /* Arg is a register; the opcode provided by insns[] is correct.
9231 It is not illegal to do "blx pc", just useless. */
9232 if (inst.operands[0].reg == REG_PC)
9233 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
b99bd4ef 9234
c19d1205
ZW
9235 inst.instruction |= inst.operands[0].reg;
9236 }
9237 else
b99bd4ef 9238 {
c19d1205 9239 /* Arg is an address; this instruction cannot be executed
267bf995
RR
9240 conditionally, and the opcode must be adjusted.
9241 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9242 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
c19d1205 9243 constraint (inst.cond != COND_ALWAYS, BAD_COND);
2fc8bdac 9244 inst.instruction = 0xfa000000;
267bf995 9245 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
b99bd4ef 9246 }
c19d1205
ZW
9247}
9248
9249static void
9250do_bx (void)
9251{
845b51d6
PB
9252 bfd_boolean want_reloc;
9253
c19d1205
ZW
9254 if (inst.operands[0].reg == REG_PC)
9255 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
b99bd4ef 9256
c19d1205 9257 inst.instruction |= inst.operands[0].reg;
845b51d6
PB
9258 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9259 it is for ARMv4t or earlier. */
9260 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
4d354d8b
TP
9261 if (!ARM_FEATURE_ZERO (selected_object_arch)
9262 && !ARM_CPU_HAS_FEATURE (selected_object_arch, arm_ext_v5))
845b51d6
PB
9263 want_reloc = TRUE;
9264
5ad34203 9265#ifdef OBJ_ELF
845b51d6 9266 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
5ad34203 9267#endif
584206db 9268 want_reloc = FALSE;
845b51d6
PB
9269
9270 if (want_reloc)
e2b0ab59 9271 inst.relocs[0].type = BFD_RELOC_ARM_V4BX;
09d92015
MM
9272}
9273
c19d1205
ZW
9274
9275/* ARM v5TEJ. Jump to Jazelle code. */
a737bd4d
NC
9276
9277static void
c19d1205 9278do_bxj (void)
a737bd4d 9279{
c19d1205
ZW
9280 if (inst.operands[0].reg == REG_PC)
9281 as_tsktsk (_("use of r15 in bxj is not really useful"));
9282
9283 inst.instruction |= inst.operands[0].reg;
a737bd4d
NC
9284}
9285
c19d1205
ZW
9286/* Co-processor data operation:
9287 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9288 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9289static void
9290do_cdp (void)
9291{
9292 inst.instruction |= inst.operands[0].reg << 8;
9293 inst.instruction |= inst.operands[1].imm << 20;
9294 inst.instruction |= inst.operands[2].reg << 12;
9295 inst.instruction |= inst.operands[3].reg << 16;
9296 inst.instruction |= inst.operands[4].reg;
9297 inst.instruction |= inst.operands[5].imm << 5;
9298}
a737bd4d
NC
9299
9300static void
c19d1205 9301do_cmp (void)
a737bd4d 9302{
c19d1205
ZW
9303 inst.instruction |= inst.operands[0].reg << 16;
9304 encode_arm_shifter_operand (1);
a737bd4d
NC
9305}
9306
c19d1205
ZW
9307/* Transfer between coprocessor and ARM registers.
9308 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9309 MRC2
9310 MCR{cond}
9311 MCR2
9312
9313 No special properties. */
09d92015 9314
dcbd0d71
MGD
9315struct deprecated_coproc_regs_s
9316{
9317 unsigned cp;
9318 int opc1;
9319 unsigned crn;
9320 unsigned crm;
9321 int opc2;
9322 arm_feature_set deprecated;
9323 arm_feature_set obsoleted;
9324 const char *dep_msg;
9325 const char *obs_msg;
9326};
9327
9328#define DEPR_ACCESS_V8 \
9329 N_("This coprocessor register access is deprecated in ARMv8")
9330
9331/* Table of all deprecated coprocessor registers. */
9332static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
9333{
9334 {15, 0, 7, 10, 5, /* CP15DMB. */
823d2571 9335 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD
9336 DEPR_ACCESS_V8, NULL},
9337 {15, 0, 7, 10, 4, /* CP15DSB. */
823d2571 9338 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD
9339 DEPR_ACCESS_V8, NULL},
9340 {15, 0, 7, 5, 4, /* CP15ISB. */
823d2571 9341 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD
9342 DEPR_ACCESS_V8, NULL},
9343 {14, 6, 1, 0, 0, /* TEEHBR. */
823d2571 9344 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD
9345 DEPR_ACCESS_V8, NULL},
9346 {14, 6, 0, 0, 0, /* TEECR. */
823d2571 9347 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD
9348 DEPR_ACCESS_V8, NULL},
9349};
9350
9351#undef DEPR_ACCESS_V8
9352
9353static const size_t deprecated_coproc_reg_count =
9354 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
9355
09d92015 9356static void
c19d1205 9357do_co_reg (void)
09d92015 9358{
fdfde340 9359 unsigned Rd;
dcbd0d71 9360 size_t i;
fdfde340
JM
9361
9362 Rd = inst.operands[2].reg;
9363 if (thumb_mode)
9364 {
9365 if (inst.instruction == 0xee000010
9366 || inst.instruction == 0xfe000010)
9367 /* MCR, MCR2 */
9368 reject_bad_reg (Rd);
5c8ed6a4 9369 else if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
fdfde340
JM
9370 /* MRC, MRC2 */
9371 constraint (Rd == REG_SP, BAD_SP);
9372 }
9373 else
9374 {
9375 /* MCR */
9376 if (inst.instruction == 0xe000010)
9377 constraint (Rd == REG_PC, BAD_PC);
9378 }
9379
dcbd0d71
MGD
9380 for (i = 0; i < deprecated_coproc_reg_count; ++i)
9381 {
9382 const struct deprecated_coproc_regs_s *r =
9383 deprecated_coproc_regs + i;
9384
9385 if (inst.operands[0].reg == r->cp
9386 && inst.operands[1].imm == r->opc1
9387 && inst.operands[3].reg == r->crn
9388 && inst.operands[4].reg == r->crm
9389 && inst.operands[5].imm == r->opc2)
9390 {
b10bf8c5 9391 if (! ARM_CPU_IS_ANY (cpu_variant)
477330fc 9392 && warn_on_deprecated
dcbd0d71 9393 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
5c3696f8 9394 as_tsktsk ("%s", r->dep_msg);
dcbd0d71
MGD
9395 }
9396 }
fdfde340 9397
c19d1205
ZW
9398 inst.instruction |= inst.operands[0].reg << 8;
9399 inst.instruction |= inst.operands[1].imm << 21;
fdfde340 9400 inst.instruction |= Rd << 12;
c19d1205
ZW
9401 inst.instruction |= inst.operands[3].reg << 16;
9402 inst.instruction |= inst.operands[4].reg;
9403 inst.instruction |= inst.operands[5].imm << 5;
9404}
09d92015 9405
c19d1205
ZW
9406/* Transfer between coprocessor register and pair of ARM registers.
9407 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9408 MCRR2
9409 MRRC{cond}
9410 MRRC2
b99bd4ef 9411
c19d1205 9412 Two XScale instructions are special cases of these:
09d92015 9413
c19d1205
ZW
9414 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9415 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
b99bd4ef 9416
5f4273c7 9417 Result unpredictable if Rd or Rn is R15. */
a737bd4d 9418
c19d1205
ZW
9419static void
9420do_co_reg2c (void)
9421{
fdfde340
JM
9422 unsigned Rd, Rn;
9423
9424 Rd = inst.operands[2].reg;
9425 Rn = inst.operands[3].reg;
9426
9427 if (thumb_mode)
9428 {
9429 reject_bad_reg (Rd);
9430 reject_bad_reg (Rn);
9431 }
9432 else
9433 {
9434 constraint (Rd == REG_PC, BAD_PC);
9435 constraint (Rn == REG_PC, BAD_PC);
9436 }
9437
873f10f0
TC
9438 /* Only check the MRRC{2} variants. */
9439 if ((inst.instruction & 0x0FF00000) == 0x0C500000)
9440 {
9441 /* If Rd == Rn, error that the operation is
9442 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9443 constraint (Rd == Rn, BAD_OVERLAP);
9444 }
9445
c19d1205
ZW
9446 inst.instruction |= inst.operands[0].reg << 8;
9447 inst.instruction |= inst.operands[1].imm << 4;
fdfde340
JM
9448 inst.instruction |= Rd << 12;
9449 inst.instruction |= Rn << 16;
c19d1205 9450 inst.instruction |= inst.operands[4].reg;
b99bd4ef
NC
9451}
9452
c19d1205
ZW
9453static void
9454do_cpsi (void)
9455{
9456 inst.instruction |= inst.operands[0].imm << 6;
a028a6f5
PB
9457 if (inst.operands[1].present)
9458 {
9459 inst.instruction |= CPSI_MMOD;
9460 inst.instruction |= inst.operands[1].imm;
9461 }
c19d1205 9462}
b99bd4ef 9463
62b3e311
PB
9464static void
9465do_dbg (void)
9466{
9467 inst.instruction |= inst.operands[0].imm;
9468}
9469
eea54501
MGD
9470static void
9471do_div (void)
9472{
9473 unsigned Rd, Rn, Rm;
9474
9475 Rd = inst.operands[0].reg;
9476 Rn = (inst.operands[1].present
9477 ? inst.operands[1].reg : Rd);
9478 Rm = inst.operands[2].reg;
9479
9480 constraint ((Rd == REG_PC), BAD_PC);
9481 constraint ((Rn == REG_PC), BAD_PC);
9482 constraint ((Rm == REG_PC), BAD_PC);
9483
9484 inst.instruction |= Rd << 16;
9485 inst.instruction |= Rn << 0;
9486 inst.instruction |= Rm << 8;
9487}
9488
b99bd4ef 9489static void
c19d1205 9490do_it (void)
b99bd4ef 9491{
c19d1205 9492 /* There is no IT instruction in ARM mode. We
e07e6e58
NC
9493 process it to do the validation as if in
9494 thumb mode, just in case the code gets
9495 assembled for thumb using the unified syntax. */
9496
c19d1205 9497 inst.size = 0;
e07e6e58
NC
9498 if (unified_syntax)
9499 {
5ee91343
AV
9500 set_pred_insn_type (IT_INSN);
9501 now_pred.mask = (inst.instruction & 0xf) | 0x10;
9502 now_pred.cc = inst.operands[0].imm;
e07e6e58 9503 }
09d92015 9504}
b99bd4ef 9505
6530b175
NC
9506/* If there is only one register in the register list,
9507 then return its register number. Otherwise return -1. */
9508static int
9509only_one_reg_in_list (int range)
9510{
9511 int i = ffs (range) - 1;
9512 return (i > 15 || range != (1 << i)) ? -1 : i;
9513}
9514
09d92015 9515static void
6530b175 9516encode_ldmstm(int from_push_pop_mnem)
ea6ef066 9517{
c19d1205
ZW
9518 int base_reg = inst.operands[0].reg;
9519 int range = inst.operands[1].imm;
6530b175 9520 int one_reg;
ea6ef066 9521
c19d1205
ZW
9522 inst.instruction |= base_reg << 16;
9523 inst.instruction |= range;
ea6ef066 9524
c19d1205
ZW
9525 if (inst.operands[1].writeback)
9526 inst.instruction |= LDM_TYPE_2_OR_3;
09d92015 9527
c19d1205 9528 if (inst.operands[0].writeback)
ea6ef066 9529 {
c19d1205
ZW
9530 inst.instruction |= WRITE_BACK;
9531 /* Check for unpredictable uses of writeback. */
9532 if (inst.instruction & LOAD_BIT)
09d92015 9533 {
c19d1205
ZW
9534 /* Not allowed in LDM type 2. */
9535 if ((inst.instruction & LDM_TYPE_2_OR_3)
9536 && ((range & (1 << REG_PC)) == 0))
9537 as_warn (_("writeback of base register is UNPREDICTABLE"));
9538 /* Only allowed if base reg not in list for other types. */
9539 else if (range & (1 << base_reg))
9540 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9541 }
9542 else /* STM. */
9543 {
9544 /* Not allowed for type 2. */
9545 if (inst.instruction & LDM_TYPE_2_OR_3)
9546 as_warn (_("writeback of base register is UNPREDICTABLE"));
9547 /* Only allowed if base reg not in list, or first in list. */
9548 else if ((range & (1 << base_reg))
9549 && (range & ((1 << base_reg) - 1)))
9550 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
09d92015 9551 }
ea6ef066 9552 }
6530b175
NC
9553
9554 /* If PUSH/POP has only one register, then use the A2 encoding. */
9555 one_reg = only_one_reg_in_list (range);
9556 if (from_push_pop_mnem && one_reg >= 0)
9557 {
9558 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
9559
4f588891
NC
9560 if (is_push && one_reg == 13 /* SP */)
9561 /* PR 22483: The A2 encoding cannot be used when
9562 pushing the stack pointer as this is UNPREDICTABLE. */
9563 return;
9564
6530b175
NC
9565 inst.instruction &= A_COND_MASK;
9566 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
9567 inst.instruction |= one_reg << 12;
9568 }
9569}
9570
9571static void
9572do_ldmstm (void)
9573{
9574 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
a737bd4d
NC
9575}
9576
c19d1205
ZW
9577/* ARMv5TE load-consecutive (argument parse)
9578 Mode is like LDRH.
9579
9580 LDRccD R, mode
9581 STRccD R, mode. */
9582
a737bd4d 9583static void
c19d1205 9584do_ldrd (void)
a737bd4d 9585{
c19d1205 9586 constraint (inst.operands[0].reg % 2 != 0,
c56791bb 9587 _("first transfer register must be even"));
c19d1205
ZW
9588 constraint (inst.operands[1].present
9589 && inst.operands[1].reg != inst.operands[0].reg + 1,
c56791bb 9590 _("can only transfer two consecutive registers"));
c19d1205
ZW
9591 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
9592 constraint (!inst.operands[2].isreg, _("'[' expected"));
a737bd4d 9593
c19d1205
ZW
9594 if (!inst.operands[1].present)
9595 inst.operands[1].reg = inst.operands[0].reg + 1;
5f4273c7 9596
c56791bb
RE
9597 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9598 register and the first register written; we have to diagnose
9599 overlap between the base and the second register written here. */
ea6ef066 9600
c56791bb
RE
9601 if (inst.operands[2].reg == inst.operands[1].reg
9602 && (inst.operands[2].writeback || inst.operands[2].postind))
9603 as_warn (_("base register written back, and overlaps "
9604 "second transfer register"));
b05fe5cf 9605
c56791bb
RE
9606 if (!(inst.instruction & V4_STR_BIT))
9607 {
c19d1205 9608 /* For an index-register load, the index register must not overlap the
c56791bb
RE
9609 destination (even if not write-back). */
9610 if (inst.operands[2].immisreg
9611 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
9612 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
9613 as_warn (_("index register overlaps transfer register"));
b05fe5cf 9614 }
c19d1205
ZW
9615 inst.instruction |= inst.operands[0].reg << 12;
9616 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
b05fe5cf
ZW
9617}
9618
9619static void
c19d1205 9620do_ldrex (void)
b05fe5cf 9621{
c19d1205
ZW
9622 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
9623 || inst.operands[1].postind || inst.operands[1].writeback
9624 || inst.operands[1].immisreg || inst.operands[1].shifted
01cfc07f
NC
9625 || inst.operands[1].negative
9626 /* This can arise if the programmer has written
9627 strex rN, rM, foo
9628 or if they have mistakenly used a register name as the last
9629 operand, eg:
9630 strex rN, rM, rX
9631 It is very difficult to distinguish between these two cases
9632 because "rX" might actually be a label. ie the register
9633 name has been occluded by a symbol of the same name. So we
9634 just generate a general 'bad addressing mode' type error
9635 message and leave it up to the programmer to discover the
9636 true cause and fix their mistake. */
9637 || (inst.operands[1].reg == REG_PC),
9638 BAD_ADDR_MODE);
b05fe5cf 9639
e2b0ab59
AV
9640 constraint (inst.relocs[0].exp.X_op != O_constant
9641 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 9642 _("offset must be zero in ARM encoding"));
b05fe5cf 9643
5be8be5d
DG
9644 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
9645
c19d1205
ZW
9646 inst.instruction |= inst.operands[0].reg << 12;
9647 inst.instruction |= inst.operands[1].reg << 16;
e2b0ab59 9648 inst.relocs[0].type = BFD_RELOC_UNUSED;
b05fe5cf
ZW
9649}
9650
9651static void
c19d1205 9652do_ldrexd (void)
b05fe5cf 9653{
c19d1205
ZW
9654 constraint (inst.operands[0].reg % 2 != 0,
9655 _("even register required"));
9656 constraint (inst.operands[1].present
9657 && inst.operands[1].reg != inst.operands[0].reg + 1,
9658 _("can only load two consecutive registers"));
9659 /* If op 1 were present and equal to PC, this function wouldn't
9660 have been called in the first place. */
9661 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
b05fe5cf 9662
c19d1205
ZW
9663 inst.instruction |= inst.operands[0].reg << 12;
9664 inst.instruction |= inst.operands[2].reg << 16;
b05fe5cf
ZW
9665}
9666
1be5fd2e
NC
9667/* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9668 which is not a multiple of four is UNPREDICTABLE. */
9669static void
9670check_ldr_r15_aligned (void)
9671{
9672 constraint (!(inst.operands[1].immisreg)
9673 && (inst.operands[0].reg == REG_PC
9674 && inst.operands[1].reg == REG_PC
e2b0ab59 9675 && (inst.relocs[0].exp.X_add_number & 0x3)),
de194d85 9676 _("ldr to register 15 must be 4-byte aligned"));
1be5fd2e
NC
9677}
9678
b05fe5cf 9679static void
c19d1205 9680do_ldst (void)
b05fe5cf 9681{
c19d1205
ZW
9682 inst.instruction |= inst.operands[0].reg << 12;
9683 if (!inst.operands[1].isreg)
8335d6aa 9684 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE))
b05fe5cf 9685 return;
c19d1205 9686 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
1be5fd2e 9687 check_ldr_r15_aligned ();
b05fe5cf
ZW
9688}
9689
9690static void
c19d1205 9691do_ldstt (void)
b05fe5cf 9692{
c19d1205
ZW
9693 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9694 reject [Rn,...]. */
9695 if (inst.operands[1].preind)
b05fe5cf 9696 {
e2b0ab59
AV
9697 constraint (inst.relocs[0].exp.X_op != O_constant
9698 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 9699 _("this instruction requires a post-indexed address"));
b05fe5cf 9700
c19d1205
ZW
9701 inst.operands[1].preind = 0;
9702 inst.operands[1].postind = 1;
9703 inst.operands[1].writeback = 1;
b05fe5cf 9704 }
c19d1205
ZW
9705 inst.instruction |= inst.operands[0].reg << 12;
9706 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
9707}
b05fe5cf 9708
c19d1205 9709/* Halfword and signed-byte load/store operations. */
b05fe5cf 9710
c19d1205
ZW
9711static void
9712do_ldstv4 (void)
9713{
ff4a8d2b 9714 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
c19d1205
ZW
9715 inst.instruction |= inst.operands[0].reg << 12;
9716 if (!inst.operands[1].isreg)
8335d6aa 9717 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE))
b05fe5cf 9718 return;
c19d1205 9719 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
b05fe5cf
ZW
9720}
9721
9722static void
c19d1205 9723do_ldsttv4 (void)
b05fe5cf 9724{
c19d1205
ZW
9725 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9726 reject [Rn,...]. */
9727 if (inst.operands[1].preind)
b05fe5cf 9728 {
e2b0ab59
AV
9729 constraint (inst.relocs[0].exp.X_op != O_constant
9730 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 9731 _("this instruction requires a post-indexed address"));
b05fe5cf 9732
c19d1205
ZW
9733 inst.operands[1].preind = 0;
9734 inst.operands[1].postind = 1;
9735 inst.operands[1].writeback = 1;
b05fe5cf 9736 }
c19d1205
ZW
9737 inst.instruction |= inst.operands[0].reg << 12;
9738 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
9739}
b05fe5cf 9740
c19d1205
ZW
9741/* Co-processor register load/store.
9742 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9743static void
9744do_lstc (void)
9745{
9746 inst.instruction |= inst.operands[0].reg << 8;
9747 inst.instruction |= inst.operands[1].reg << 12;
9748 encode_arm_cp_address (2, TRUE, TRUE, 0);
b05fe5cf
ZW
9749}
9750
b05fe5cf 9751static void
c19d1205 9752do_mlas (void)
b05fe5cf 9753{
8fb9d7b9 9754 /* This restriction does not apply to mls (nor to mla in v6 or later). */
c19d1205 9755 if (inst.operands[0].reg == inst.operands[1].reg
8fb9d7b9 9756 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
c19d1205 9757 && !(inst.instruction & 0x00400000))
8fb9d7b9 9758 as_tsktsk (_("Rd and Rm should be different in mla"));
b05fe5cf 9759
c19d1205
ZW
9760 inst.instruction |= inst.operands[0].reg << 16;
9761 inst.instruction |= inst.operands[1].reg;
9762 inst.instruction |= inst.operands[2].reg << 8;
9763 inst.instruction |= inst.operands[3].reg << 12;
c19d1205 9764}
b05fe5cf 9765
c19d1205
ZW
9766static void
9767do_mov (void)
9768{
e2b0ab59
AV
9769 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9770 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
a9f02af8 9771 THUMB1_RELOC_ONLY);
c19d1205
ZW
9772 inst.instruction |= inst.operands[0].reg << 12;
9773 encode_arm_shifter_operand (1);
9774}
b05fe5cf 9775
c19d1205
ZW
9776/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9777static void
9778do_mov16 (void)
9779{
b6895b4f
PB
9780 bfd_vma imm;
9781 bfd_boolean top;
9782
9783 top = (inst.instruction & 0x00400000) != 0;
e2b0ab59 9784 constraint (top && inst.relocs[0].type == BFD_RELOC_ARM_MOVW,
33eaf5de 9785 _(":lower16: not allowed in this instruction"));
e2b0ab59 9786 constraint (!top && inst.relocs[0].type == BFD_RELOC_ARM_MOVT,
33eaf5de 9787 _(":upper16: not allowed in this instruction"));
c19d1205 9788 inst.instruction |= inst.operands[0].reg << 12;
e2b0ab59 9789 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
b6895b4f 9790 {
e2b0ab59 9791 imm = inst.relocs[0].exp.X_add_number;
b6895b4f
PB
9792 /* The value is in two pieces: 0:11, 16:19. */
9793 inst.instruction |= (imm & 0x00000fff);
9794 inst.instruction |= (imm & 0x0000f000) << 4;
9795 }
b05fe5cf 9796}
b99bd4ef 9797
037e8744
JB
9798static int
9799do_vfp_nsyn_mrs (void)
9800{
9801 if (inst.operands[0].isvec)
9802 {
9803 if (inst.operands[1].reg != 1)
477330fc 9804 first_error (_("operand 1 must be FPSCR"));
037e8744
JB
9805 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
9806 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
9807 do_vfp_nsyn_opcode ("fmstat");
9808 }
9809 else if (inst.operands[1].isvec)
9810 do_vfp_nsyn_opcode ("fmrx");
9811 else
9812 return FAIL;
5f4273c7 9813
037e8744
JB
9814 return SUCCESS;
9815}
9816
9817static int
9818do_vfp_nsyn_msr (void)
9819{
9820 if (inst.operands[0].isvec)
9821 do_vfp_nsyn_opcode ("fmxr");
9822 else
9823 return FAIL;
9824
9825 return SUCCESS;
9826}
9827
f7c21dc7
NC
9828static void
9829do_vmrs (void)
9830{
9831 unsigned Rt = inst.operands[0].reg;
fa94de6b 9832
16d02dc9 9833 if (thumb_mode && Rt == REG_SP)
f7c21dc7
NC
9834 {
9835 inst.error = BAD_SP;
9836 return;
9837 }
9838
40c7d507
RR
9839 /* MVFR2 is only valid at ARMv8-A. */
9840 if (inst.operands[1].reg == 5)
9841 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
9842 _(BAD_FPU));
9843
f7c21dc7 9844 /* APSR_ sets isvec. All other refs to PC are illegal. */
16d02dc9 9845 if (!inst.operands[0].isvec && Rt == REG_PC)
f7c21dc7
NC
9846 {
9847 inst.error = BAD_PC;
9848 return;
9849 }
9850
16d02dc9
JB
9851 /* If we get through parsing the register name, we just insert the number
9852 generated into the instruction without further validation. */
9853 inst.instruction |= (inst.operands[1].reg << 16);
f7c21dc7
NC
9854 inst.instruction |= (Rt << 12);
9855}
9856
9857static void
9858do_vmsr (void)
9859{
9860 unsigned Rt = inst.operands[1].reg;
fa94de6b 9861
f7c21dc7
NC
9862 if (thumb_mode)
9863 reject_bad_reg (Rt);
9864 else if (Rt == REG_PC)
9865 {
9866 inst.error = BAD_PC;
9867 return;
9868 }
9869
40c7d507
RR
9870 /* MVFR2 is only valid for ARMv8-A. */
9871 if (inst.operands[0].reg == 5)
9872 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
9873 _(BAD_FPU));
9874
16d02dc9
JB
9875 /* If we get through parsing the register name, we just insert the number
9876 generated into the instruction without further validation. */
9877 inst.instruction |= (inst.operands[0].reg << 16);
f7c21dc7
NC
9878 inst.instruction |= (Rt << 12);
9879}
9880
b99bd4ef 9881static void
c19d1205 9882do_mrs (void)
b99bd4ef 9883{
90ec0d68
MGD
9884 unsigned br;
9885
037e8744
JB
9886 if (do_vfp_nsyn_mrs () == SUCCESS)
9887 return;
9888
ff4a8d2b 9889 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
c19d1205 9890 inst.instruction |= inst.operands[0].reg << 12;
90ec0d68
MGD
9891
9892 if (inst.operands[1].isreg)
9893 {
9894 br = inst.operands[1].reg;
806ab1c0 9895 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf0000))
90ec0d68
MGD
9896 as_bad (_("bad register for mrs"));
9897 }
9898 else
9899 {
9900 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9901 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
9902 != (PSR_c|PSR_f),
d2cd1205 9903 _("'APSR', 'CPSR' or 'SPSR' expected"));
90ec0d68
MGD
9904 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
9905 }
9906
9907 inst.instruction |= br;
c19d1205 9908}
b99bd4ef 9909
c19d1205
ZW
9910/* Two possible forms:
9911 "{C|S}PSR_<field>, Rm",
9912 "{C|S}PSR_f, #expression". */
b99bd4ef 9913
c19d1205
ZW
9914static void
9915do_msr (void)
9916{
037e8744
JB
9917 if (do_vfp_nsyn_msr () == SUCCESS)
9918 return;
9919
c19d1205
ZW
9920 inst.instruction |= inst.operands[0].imm;
9921 if (inst.operands[1].isreg)
9922 inst.instruction |= inst.operands[1].reg;
9923 else
b99bd4ef 9924 {
c19d1205 9925 inst.instruction |= INST_IMMEDIATE;
e2b0ab59
AV
9926 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
9927 inst.relocs[0].pc_rel = 0;
b99bd4ef 9928 }
b99bd4ef
NC
9929}
9930
c19d1205
ZW
9931static void
9932do_mul (void)
a737bd4d 9933{
ff4a8d2b
NC
9934 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
9935
c19d1205
ZW
9936 if (!inst.operands[2].present)
9937 inst.operands[2].reg = inst.operands[0].reg;
9938 inst.instruction |= inst.operands[0].reg << 16;
9939 inst.instruction |= inst.operands[1].reg;
9940 inst.instruction |= inst.operands[2].reg << 8;
a737bd4d 9941
8fb9d7b9
MS
9942 if (inst.operands[0].reg == inst.operands[1].reg
9943 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
9944 as_tsktsk (_("Rd and Rm should be different in mul"));
a737bd4d
NC
9945}
9946
c19d1205
ZW
9947/* Long Multiply Parser
9948 UMULL RdLo, RdHi, Rm, Rs
9949 SMULL RdLo, RdHi, Rm, Rs
9950 UMLAL RdLo, RdHi, Rm, Rs
9951 SMLAL RdLo, RdHi, Rm, Rs. */
b99bd4ef
NC
9952
9953static void
c19d1205 9954do_mull (void)
b99bd4ef 9955{
c19d1205
ZW
9956 inst.instruction |= inst.operands[0].reg << 12;
9957 inst.instruction |= inst.operands[1].reg << 16;
9958 inst.instruction |= inst.operands[2].reg;
9959 inst.instruction |= inst.operands[3].reg << 8;
b99bd4ef 9960
682b27ad
PB
9961 /* rdhi and rdlo must be different. */
9962 if (inst.operands[0].reg == inst.operands[1].reg)
9963 as_tsktsk (_("rdhi and rdlo must be different"));
9964
9965 /* rdhi, rdlo and rm must all be different before armv6. */
9966 if ((inst.operands[0].reg == inst.operands[2].reg
c19d1205 9967 || inst.operands[1].reg == inst.operands[2].reg)
682b27ad 9968 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
c19d1205
ZW
9969 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9970}
b99bd4ef 9971
c19d1205
ZW
9972static void
9973do_nop (void)
9974{
e7495e45
NS
9975 if (inst.operands[0].present
9976 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
c19d1205
ZW
9977 {
9978 /* Architectural NOP hints are CPSR sets with no bits selected. */
9979 inst.instruction &= 0xf0000000;
e7495e45
NS
9980 inst.instruction |= 0x0320f000;
9981 if (inst.operands[0].present)
9982 inst.instruction |= inst.operands[0].imm;
c19d1205 9983 }
b99bd4ef
NC
9984}
9985
c19d1205
ZW
9986/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9987 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9988 Condition defaults to COND_ALWAYS.
9989 Error if Rd, Rn or Rm are R15. */
b99bd4ef
NC
9990
9991static void
c19d1205 9992do_pkhbt (void)
b99bd4ef 9993{
c19d1205
ZW
9994 inst.instruction |= inst.operands[0].reg << 12;
9995 inst.instruction |= inst.operands[1].reg << 16;
9996 inst.instruction |= inst.operands[2].reg;
9997 if (inst.operands[3].present)
9998 encode_arm_shift (3);
9999}
b99bd4ef 10000
c19d1205 10001/* ARM V6 PKHTB (Argument Parse). */
b99bd4ef 10002
c19d1205
ZW
10003static void
10004do_pkhtb (void)
10005{
10006 if (!inst.operands[3].present)
b99bd4ef 10007 {
c19d1205
ZW
10008 /* If the shift specifier is omitted, turn the instruction
10009 into pkhbt rd, rm, rn. */
10010 inst.instruction &= 0xfff00010;
10011 inst.instruction |= inst.operands[0].reg << 12;
10012 inst.instruction |= inst.operands[1].reg;
10013 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC
10014 }
10015 else
10016 {
c19d1205
ZW
10017 inst.instruction |= inst.operands[0].reg << 12;
10018 inst.instruction |= inst.operands[1].reg << 16;
10019 inst.instruction |= inst.operands[2].reg;
10020 encode_arm_shift (3);
b99bd4ef
NC
10021 }
10022}
10023
c19d1205 10024/* ARMv5TE: Preload-Cache
60e5ef9f 10025 MP Extensions: Preload for write
c19d1205 10026
60e5ef9f 10027 PLD(W) <addr_mode>
c19d1205
ZW
10028
10029 Syntactically, like LDR with B=1, W=0, L=1. */
b99bd4ef
NC
10030
10031static void
c19d1205 10032do_pld (void)
b99bd4ef 10033{
c19d1205
ZW
10034 constraint (!inst.operands[0].isreg,
10035 _("'[' expected after PLD mnemonic"));
10036 constraint (inst.operands[0].postind,
10037 _("post-indexed expression used in preload instruction"));
10038 constraint (inst.operands[0].writeback,
10039 _("writeback used in preload instruction"));
10040 constraint (!inst.operands[0].preind,
10041 _("unindexed addressing used in preload instruction"));
c19d1205
ZW
10042 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
10043}
b99bd4ef 10044
62b3e311
PB
10045/* ARMv7: PLI <addr_mode> */
10046static void
10047do_pli (void)
10048{
10049 constraint (!inst.operands[0].isreg,
10050 _("'[' expected after PLI mnemonic"));
10051 constraint (inst.operands[0].postind,
10052 _("post-indexed expression used in preload instruction"));
10053 constraint (inst.operands[0].writeback,
10054 _("writeback used in preload instruction"));
10055 constraint (!inst.operands[0].preind,
10056 _("unindexed addressing used in preload instruction"));
10057 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
10058 inst.instruction &= ~PRE_INDEX;
10059}
10060
c19d1205
ZW
10061static void
10062do_push_pop (void)
10063{
5e0d7f77
MP
10064 constraint (inst.operands[0].writeback,
10065 _("push/pop do not support {reglist}^"));
c19d1205
ZW
10066 inst.operands[1] = inst.operands[0];
10067 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
10068 inst.operands[0].isreg = 1;
10069 inst.operands[0].writeback = 1;
10070 inst.operands[0].reg = REG_SP;
6530b175 10071 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
c19d1205 10072}
b99bd4ef 10073
c19d1205
ZW
10074/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10075 word at the specified address and the following word
10076 respectively.
10077 Unconditionally executed.
10078 Error if Rn is R15. */
b99bd4ef 10079
c19d1205
ZW
10080static void
10081do_rfe (void)
10082{
10083 inst.instruction |= inst.operands[0].reg << 16;
10084 if (inst.operands[0].writeback)
10085 inst.instruction |= WRITE_BACK;
10086}
b99bd4ef 10087
c19d1205 10088/* ARM V6 ssat (argument parse). */
b99bd4ef 10089
c19d1205
ZW
10090static void
10091do_ssat (void)
10092{
10093 inst.instruction |= inst.operands[0].reg << 12;
10094 inst.instruction |= (inst.operands[1].imm - 1) << 16;
10095 inst.instruction |= inst.operands[2].reg;
b99bd4ef 10096
c19d1205
ZW
10097 if (inst.operands[3].present)
10098 encode_arm_shift (3);
b99bd4ef
NC
10099}
10100
c19d1205 10101/* ARM V6 usat (argument parse). */
b99bd4ef
NC
10102
10103static void
c19d1205 10104do_usat (void)
b99bd4ef 10105{
c19d1205
ZW
10106 inst.instruction |= inst.operands[0].reg << 12;
10107 inst.instruction |= inst.operands[1].imm << 16;
10108 inst.instruction |= inst.operands[2].reg;
b99bd4ef 10109
c19d1205
ZW
10110 if (inst.operands[3].present)
10111 encode_arm_shift (3);
b99bd4ef
NC
10112}
10113
c19d1205 10114/* ARM V6 ssat16 (argument parse). */
09d92015
MM
10115
10116static void
c19d1205 10117do_ssat16 (void)
09d92015 10118{
c19d1205
ZW
10119 inst.instruction |= inst.operands[0].reg << 12;
10120 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
10121 inst.instruction |= inst.operands[2].reg;
09d92015
MM
10122}
10123
c19d1205
ZW
10124static void
10125do_usat16 (void)
a737bd4d 10126{
c19d1205
ZW
10127 inst.instruction |= inst.operands[0].reg << 12;
10128 inst.instruction |= inst.operands[1].imm << 16;
10129 inst.instruction |= inst.operands[2].reg;
10130}
a737bd4d 10131
c19d1205
ZW
10132/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10133 preserving the other bits.
a737bd4d 10134
c19d1205
ZW
10135 setend <endian_specifier>, where <endian_specifier> is either
10136 BE or LE. */
a737bd4d 10137
c19d1205
ZW
10138static void
10139do_setend (void)
10140{
12e37cbc
MGD
10141 if (warn_on_deprecated
10142 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
5c3696f8 10143 as_tsktsk (_("setend use is deprecated for ARMv8"));
12e37cbc 10144
c19d1205
ZW
10145 if (inst.operands[0].imm)
10146 inst.instruction |= 0x200;
a737bd4d
NC
10147}
10148
10149static void
c19d1205 10150do_shift (void)
a737bd4d 10151{
c19d1205
ZW
10152 unsigned int Rm = (inst.operands[1].present
10153 ? inst.operands[1].reg
10154 : inst.operands[0].reg);
a737bd4d 10155
c19d1205
ZW
10156 inst.instruction |= inst.operands[0].reg << 12;
10157 inst.instruction |= Rm;
10158 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
a737bd4d 10159 {
c19d1205
ZW
10160 inst.instruction |= inst.operands[2].reg << 8;
10161 inst.instruction |= SHIFT_BY_REG;
94342ec3
NC
10162 /* PR 12854: Error on extraneous shifts. */
10163 constraint (inst.operands[2].shifted,
10164 _("extraneous shift as part of operand to shift insn"));
a737bd4d
NC
10165 }
10166 else
e2b0ab59 10167 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
a737bd4d
NC
10168}
10169
09d92015 10170static void
3eb17e6b 10171do_smc (void)
09d92015 10172{
e2b0ab59
AV
10173 inst.relocs[0].type = BFD_RELOC_ARM_SMC;
10174 inst.relocs[0].pc_rel = 0;
09d92015
MM
10175}
10176
90ec0d68
MGD
10177static void
10178do_hvc (void)
10179{
e2b0ab59
AV
10180 inst.relocs[0].type = BFD_RELOC_ARM_HVC;
10181 inst.relocs[0].pc_rel = 0;
90ec0d68
MGD
10182}
10183
09d92015 10184static void
c19d1205 10185do_swi (void)
09d92015 10186{
e2b0ab59
AV
10187 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
10188 inst.relocs[0].pc_rel = 0;
09d92015
MM
10189}
10190
ddfded2f
MW
10191static void
10192do_setpan (void)
10193{
10194 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
10195 _("selected processor does not support SETPAN instruction"));
10196
10197 inst.instruction |= ((inst.operands[0].imm & 1) << 9);
10198}
10199
10200static void
10201do_t_setpan (void)
10202{
10203 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
10204 _("selected processor does not support SETPAN instruction"));
10205
10206 inst.instruction |= (inst.operands[0].imm << 3);
10207}
10208
c19d1205
ZW
10209/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10210 SMLAxy{cond} Rd,Rm,Rs,Rn
10211 SMLAWy{cond} Rd,Rm,Rs,Rn
10212 Error if any register is R15. */
e16bb312 10213
c19d1205
ZW
10214static void
10215do_smla (void)
e16bb312 10216{
c19d1205
ZW
10217 inst.instruction |= inst.operands[0].reg << 16;
10218 inst.instruction |= inst.operands[1].reg;
10219 inst.instruction |= inst.operands[2].reg << 8;
10220 inst.instruction |= inst.operands[3].reg << 12;
10221}
a737bd4d 10222
c19d1205
ZW
10223/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10224 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10225 Error if any register is R15.
10226 Warning if Rdlo == Rdhi. */
a737bd4d 10227
c19d1205
ZW
10228static void
10229do_smlal (void)
10230{
10231 inst.instruction |= inst.operands[0].reg << 12;
10232 inst.instruction |= inst.operands[1].reg << 16;
10233 inst.instruction |= inst.operands[2].reg;
10234 inst.instruction |= inst.operands[3].reg << 8;
a737bd4d 10235
c19d1205
ZW
10236 if (inst.operands[0].reg == inst.operands[1].reg)
10237 as_tsktsk (_("rdhi and rdlo must be different"));
10238}
a737bd4d 10239
c19d1205
ZW
10240/* ARM V5E (El Segundo) signed-multiply (argument parse)
10241 SMULxy{cond} Rd,Rm,Rs
10242 Error if any register is R15. */
a737bd4d 10243
c19d1205
ZW
10244static void
10245do_smul (void)
10246{
10247 inst.instruction |= inst.operands[0].reg << 16;
10248 inst.instruction |= inst.operands[1].reg;
10249 inst.instruction |= inst.operands[2].reg << 8;
10250}
a737bd4d 10251
b6702015
PB
10252/* ARM V6 srs (argument parse). The variable fields in the encoding are
10253 the same for both ARM and Thumb-2. */
a737bd4d 10254
c19d1205
ZW
10255static void
10256do_srs (void)
10257{
b6702015
PB
10258 int reg;
10259
10260 if (inst.operands[0].present)
10261 {
10262 reg = inst.operands[0].reg;
fdfde340 10263 constraint (reg != REG_SP, _("SRS base register must be r13"));
b6702015
PB
10264 }
10265 else
fdfde340 10266 reg = REG_SP;
b6702015
PB
10267
10268 inst.instruction |= reg << 16;
10269 inst.instruction |= inst.operands[1].imm;
10270 if (inst.operands[0].writeback || inst.operands[1].writeback)
c19d1205
ZW
10271 inst.instruction |= WRITE_BACK;
10272}
a737bd4d 10273
c19d1205 10274/* ARM V6 strex (argument parse). */
a737bd4d 10275
c19d1205
ZW
10276static void
10277do_strex (void)
10278{
10279 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10280 || inst.operands[2].postind || inst.operands[2].writeback
10281 || inst.operands[2].immisreg || inst.operands[2].shifted
01cfc07f
NC
10282 || inst.operands[2].negative
10283 /* See comment in do_ldrex(). */
10284 || (inst.operands[2].reg == REG_PC),
10285 BAD_ADDR_MODE);
a737bd4d 10286
c19d1205
ZW
10287 constraint (inst.operands[0].reg == inst.operands[1].reg
10288 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
a737bd4d 10289
e2b0ab59
AV
10290 constraint (inst.relocs[0].exp.X_op != O_constant
10291 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 10292 _("offset must be zero in ARM encoding"));
a737bd4d 10293
c19d1205
ZW
10294 inst.instruction |= inst.operands[0].reg << 12;
10295 inst.instruction |= inst.operands[1].reg;
10296 inst.instruction |= inst.operands[2].reg << 16;
e2b0ab59 10297 inst.relocs[0].type = BFD_RELOC_UNUSED;
e16bb312
NC
10298}
10299
877807f8
NC
10300static void
10301do_t_strexbh (void)
10302{
10303 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10304 || inst.operands[2].postind || inst.operands[2].writeback
10305 || inst.operands[2].immisreg || inst.operands[2].shifted
10306 || inst.operands[2].negative,
10307 BAD_ADDR_MODE);
10308
10309 constraint (inst.operands[0].reg == inst.operands[1].reg
10310 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10311
10312 do_rm_rd_rn ();
10313}
10314
e16bb312 10315static void
c19d1205 10316do_strexd (void)
e16bb312 10317{
c19d1205
ZW
10318 constraint (inst.operands[1].reg % 2 != 0,
10319 _("even register required"));
10320 constraint (inst.operands[2].present
10321 && inst.operands[2].reg != inst.operands[1].reg + 1,
10322 _("can only store two consecutive registers"));
10323 /* If op 2 were present and equal to PC, this function wouldn't
10324 have been called in the first place. */
10325 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
e16bb312 10326
c19d1205
ZW
10327 constraint (inst.operands[0].reg == inst.operands[1].reg
10328 || inst.operands[0].reg == inst.operands[1].reg + 1
10329 || inst.operands[0].reg == inst.operands[3].reg,
10330 BAD_OVERLAP);
e16bb312 10331
c19d1205
ZW
10332 inst.instruction |= inst.operands[0].reg << 12;
10333 inst.instruction |= inst.operands[1].reg;
10334 inst.instruction |= inst.operands[3].reg << 16;
e16bb312
NC
10335}
10336
9eb6c0f1
MGD
10337/* ARM V8 STRL. */
10338static void
4b8c8c02 10339do_stlex (void)
9eb6c0f1
MGD
10340{
10341 constraint (inst.operands[0].reg == inst.operands[1].reg
10342 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10343
10344 do_rd_rm_rn ();
10345}
10346
10347static void
4b8c8c02 10348do_t_stlex (void)
9eb6c0f1
MGD
10349{
10350 constraint (inst.operands[0].reg == inst.operands[1].reg
10351 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10352
10353 do_rm_rd_rn ();
10354}
10355
c19d1205
ZW
10356/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10357 extends it to 32-bits, and adds the result to a value in another
10358 register. You can specify a rotation by 0, 8, 16, or 24 bits
10359 before extracting the 16-bit value.
10360 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10361 Condition defaults to COND_ALWAYS.
10362 Error if any register uses R15. */
10363
e16bb312 10364static void
c19d1205 10365do_sxtah (void)
e16bb312 10366{
c19d1205
ZW
10367 inst.instruction |= inst.operands[0].reg << 12;
10368 inst.instruction |= inst.operands[1].reg << 16;
10369 inst.instruction |= inst.operands[2].reg;
10370 inst.instruction |= inst.operands[3].imm << 10;
10371}
e16bb312 10372
c19d1205 10373/* ARM V6 SXTH.
e16bb312 10374
c19d1205
ZW
10375 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10376 Condition defaults to COND_ALWAYS.
10377 Error if any register uses R15. */
e16bb312
NC
10378
10379static void
c19d1205 10380do_sxth (void)
e16bb312 10381{
c19d1205
ZW
10382 inst.instruction |= inst.operands[0].reg << 12;
10383 inst.instruction |= inst.operands[1].reg;
10384 inst.instruction |= inst.operands[2].imm << 10;
e16bb312 10385}
c19d1205
ZW
10386\f
10387/* VFP instructions. In a logical order: SP variant first, monad
10388 before dyad, arithmetic then move then load/store. */
e16bb312
NC
10389
10390static void
c19d1205 10391do_vfp_sp_monadic (void)
e16bb312 10392{
57785aa2
AV
10393 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10394 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10395 _(BAD_FPU));
10396
5287ad62
JB
10397 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10398 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC
10399}
10400
10401static void
c19d1205 10402do_vfp_sp_dyadic (void)
e16bb312 10403{
5287ad62
JB
10404 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10405 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
10406 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC
10407}
10408
10409static void
c19d1205 10410do_vfp_sp_compare_z (void)
e16bb312 10411{
5287ad62 10412 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
e16bb312
NC
10413}
10414
10415static void
c19d1205 10416do_vfp_dp_sp_cvt (void)
e16bb312 10417{
5287ad62
JB
10418 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10419 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC
10420}
10421
10422static void
c19d1205 10423do_vfp_sp_dp_cvt (void)
e16bb312 10424{
5287ad62
JB
10425 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10426 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
e16bb312
NC
10427}
10428
10429static void
c19d1205 10430do_vfp_reg_from_sp (void)
e16bb312 10431{
57785aa2
AV
10432 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10433 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10434 _(BAD_FPU));
10435
c19d1205 10436 inst.instruction |= inst.operands[0].reg << 12;
5287ad62 10437 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
e16bb312
NC
10438}
10439
10440static void
c19d1205 10441do_vfp_reg2_from_sp2 (void)
e16bb312 10442{
c19d1205
ZW
10443 constraint (inst.operands[2].imm != 2,
10444 _("only two consecutive VFP SP registers allowed here"));
10445 inst.instruction |= inst.operands[0].reg << 12;
10446 inst.instruction |= inst.operands[1].reg << 16;
5287ad62 10447 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC
10448}
10449
10450static void
c19d1205 10451do_vfp_sp_from_reg (void)
e16bb312 10452{
57785aa2
AV
10453 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10454 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10455 _(BAD_FPU));
10456
5287ad62 10457 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
c19d1205 10458 inst.instruction |= inst.operands[1].reg << 12;
e16bb312
NC
10459}
10460
10461static void
c19d1205 10462do_vfp_sp2_from_reg2 (void)
e16bb312 10463{
c19d1205
ZW
10464 constraint (inst.operands[0].imm != 2,
10465 _("only two consecutive VFP SP registers allowed here"));
5287ad62 10466 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
c19d1205
ZW
10467 inst.instruction |= inst.operands[1].reg << 12;
10468 inst.instruction |= inst.operands[2].reg << 16;
e16bb312
NC
10469}
10470
10471static void
c19d1205 10472do_vfp_sp_ldst (void)
e16bb312 10473{
5287ad62 10474 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
c19d1205 10475 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC
10476}
10477
10478static void
c19d1205 10479do_vfp_dp_ldst (void)
e16bb312 10480{
5287ad62 10481 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
c19d1205 10482 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC
10483}
10484
c19d1205 10485
e16bb312 10486static void
c19d1205 10487vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 10488{
c19d1205
ZW
10489 if (inst.operands[0].writeback)
10490 inst.instruction |= WRITE_BACK;
10491 else
10492 constraint (ldstm_type != VFP_LDSTMIA,
10493 _("this addressing mode requires base-register writeback"));
10494 inst.instruction |= inst.operands[0].reg << 16;
5287ad62 10495 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
c19d1205 10496 inst.instruction |= inst.operands[1].imm;
e16bb312
NC
10497}
10498
10499static void
c19d1205 10500vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 10501{
c19d1205 10502 int count;
e16bb312 10503
c19d1205
ZW
10504 if (inst.operands[0].writeback)
10505 inst.instruction |= WRITE_BACK;
10506 else
10507 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
10508 _("this addressing mode requires base-register writeback"));
e16bb312 10509
c19d1205 10510 inst.instruction |= inst.operands[0].reg << 16;
5287ad62 10511 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
e16bb312 10512
c19d1205
ZW
10513 count = inst.operands[1].imm << 1;
10514 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
10515 count += 1;
e16bb312 10516
c19d1205 10517 inst.instruction |= count;
e16bb312
NC
10518}
10519
10520static void
c19d1205 10521do_vfp_sp_ldstmia (void)
e16bb312 10522{
c19d1205 10523 vfp_sp_ldstm (VFP_LDSTMIA);
e16bb312
NC
10524}
10525
10526static void
c19d1205 10527do_vfp_sp_ldstmdb (void)
e16bb312 10528{
c19d1205 10529 vfp_sp_ldstm (VFP_LDSTMDB);
e16bb312
NC
10530}
10531
10532static void
c19d1205 10533do_vfp_dp_ldstmia (void)
e16bb312 10534{
c19d1205 10535 vfp_dp_ldstm (VFP_LDSTMIA);
e16bb312
NC
10536}
10537
10538static void
c19d1205 10539do_vfp_dp_ldstmdb (void)
e16bb312 10540{
c19d1205 10541 vfp_dp_ldstm (VFP_LDSTMDB);
e16bb312
NC
10542}
10543
10544static void
c19d1205 10545do_vfp_xp_ldstmia (void)
e16bb312 10546{
c19d1205
ZW
10547 vfp_dp_ldstm (VFP_LDSTMIAX);
10548}
e16bb312 10549
c19d1205
ZW
10550static void
10551do_vfp_xp_ldstmdb (void)
10552{
10553 vfp_dp_ldstm (VFP_LDSTMDBX);
e16bb312 10554}
5287ad62
JB
10555
10556static void
10557do_vfp_dp_rd_rm (void)
10558{
57785aa2
AV
10559 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
10560 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10561 _(BAD_FPU));
10562
5287ad62
JB
10563 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10564 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
10565}
10566
10567static void
10568do_vfp_dp_rn_rd (void)
10569{
10570 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
10571 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10572}
10573
10574static void
10575do_vfp_dp_rd_rn (void)
10576{
10577 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10578 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10579}
10580
10581static void
10582do_vfp_dp_rd_rn_rm (void)
10583{
57785aa2
AV
10584 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
10585 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10586 _(BAD_FPU));
10587
5287ad62
JB
10588 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10589 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10590 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
10591}
10592
10593static void
10594do_vfp_dp_rd (void)
10595{
10596 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10597}
10598
10599static void
10600do_vfp_dp_rm_rd_rn (void)
10601{
57785aa2
AV
10602 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
10603 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10604 _(BAD_FPU));
10605
5287ad62
JB
10606 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
10607 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10608 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
10609}
10610
10611/* VFPv3 instructions. */
10612static void
10613do_vfp_sp_const (void)
10614{
10615 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
00249aaa
PB
10616 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10617 inst.instruction |= (inst.operands[1].imm & 0x0f);
5287ad62
JB
10618}
10619
10620static void
10621do_vfp_dp_const (void)
10622{
10623 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
00249aaa
PB
10624 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10625 inst.instruction |= (inst.operands[1].imm & 0x0f);
5287ad62
JB
10626}
10627
10628static void
10629vfp_conv (int srcsize)
10630{
5f1af56b
MGD
10631 int immbits = srcsize - inst.operands[1].imm;
10632
fa94de6b
RM
10633 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
10634 {
5f1af56b 10635 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
477330fc 10636 i.e. immbits must be in range 0 - 16. */
5f1af56b
MGD
10637 inst.error = _("immediate value out of range, expected range [0, 16]");
10638 return;
10639 }
fa94de6b 10640 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
5f1af56b
MGD
10641 {
10642 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
477330fc 10643 i.e. immbits must be in range 0 - 31. */
5f1af56b
MGD
10644 inst.error = _("immediate value out of range, expected range [1, 32]");
10645 return;
10646 }
10647
5287ad62
JB
10648 inst.instruction |= (immbits & 1) << 5;
10649 inst.instruction |= (immbits >> 1);
10650}
10651
10652static void
10653do_vfp_sp_conv_16 (void)
10654{
10655 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10656 vfp_conv (16);
10657}
10658
10659static void
10660do_vfp_dp_conv_16 (void)
10661{
10662 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10663 vfp_conv (16);
10664}
10665
10666static void
10667do_vfp_sp_conv_32 (void)
10668{
10669 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10670 vfp_conv (32);
10671}
10672
10673static void
10674do_vfp_dp_conv_32 (void)
10675{
10676 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10677 vfp_conv (32);
10678}
c19d1205
ZW
10679\f
10680/* FPA instructions. Also in a logical order. */
e16bb312 10681
c19d1205
ZW
10682static void
10683do_fpa_cmp (void)
10684{
10685 inst.instruction |= inst.operands[0].reg << 16;
10686 inst.instruction |= inst.operands[1].reg;
10687}
b99bd4ef
NC
10688
10689static void
c19d1205 10690do_fpa_ldmstm (void)
b99bd4ef 10691{
c19d1205
ZW
10692 inst.instruction |= inst.operands[0].reg << 12;
10693 switch (inst.operands[1].imm)
10694 {
10695 case 1: inst.instruction |= CP_T_X; break;
10696 case 2: inst.instruction |= CP_T_Y; break;
10697 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
10698 case 4: break;
10699 default: abort ();
10700 }
b99bd4ef 10701
c19d1205
ZW
10702 if (inst.instruction & (PRE_INDEX | INDEX_UP))
10703 {
10704 /* The instruction specified "ea" or "fd", so we can only accept
10705 [Rn]{!}. The instruction does not really support stacking or
10706 unstacking, so we have to emulate these by setting appropriate
10707 bits and offsets. */
e2b0ab59
AV
10708 constraint (inst.relocs[0].exp.X_op != O_constant
10709 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 10710 _("this instruction does not support indexing"));
b99bd4ef 10711
c19d1205 10712 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
e2b0ab59 10713 inst.relocs[0].exp.X_add_number = 12 * inst.operands[1].imm;
b99bd4ef 10714
c19d1205 10715 if (!(inst.instruction & INDEX_UP))
e2b0ab59 10716 inst.relocs[0].exp.X_add_number = -inst.relocs[0].exp.X_add_number;
b99bd4ef 10717
c19d1205
ZW
10718 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
10719 {
10720 inst.operands[2].preind = 0;
10721 inst.operands[2].postind = 1;
10722 }
10723 }
b99bd4ef 10724
c19d1205 10725 encode_arm_cp_address (2, TRUE, TRUE, 0);
b99bd4ef 10726}
c19d1205
ZW
10727\f
10728/* iWMMXt instructions: strictly in alphabetical order. */
b99bd4ef 10729
c19d1205
ZW
10730static void
10731do_iwmmxt_tandorc (void)
10732{
10733 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
10734}
b99bd4ef 10735
c19d1205
ZW
10736static void
10737do_iwmmxt_textrc (void)
10738{
10739 inst.instruction |= inst.operands[0].reg << 12;
10740 inst.instruction |= inst.operands[1].imm;
10741}
b99bd4ef
NC
10742
10743static void
c19d1205 10744do_iwmmxt_textrm (void)
b99bd4ef 10745{
c19d1205
ZW
10746 inst.instruction |= inst.operands[0].reg << 12;
10747 inst.instruction |= inst.operands[1].reg << 16;
10748 inst.instruction |= inst.operands[2].imm;
10749}
b99bd4ef 10750
c19d1205
ZW
10751static void
10752do_iwmmxt_tinsr (void)
10753{
10754 inst.instruction |= inst.operands[0].reg << 16;
10755 inst.instruction |= inst.operands[1].reg << 12;
10756 inst.instruction |= inst.operands[2].imm;
10757}
b99bd4ef 10758
c19d1205
ZW
10759static void
10760do_iwmmxt_tmia (void)
10761{
10762 inst.instruction |= inst.operands[0].reg << 5;
10763 inst.instruction |= inst.operands[1].reg;
10764 inst.instruction |= inst.operands[2].reg << 12;
10765}
b99bd4ef 10766
c19d1205
ZW
10767static void
10768do_iwmmxt_waligni (void)
10769{
10770 inst.instruction |= inst.operands[0].reg << 12;
10771 inst.instruction |= inst.operands[1].reg << 16;
10772 inst.instruction |= inst.operands[2].reg;
10773 inst.instruction |= inst.operands[3].imm << 20;
10774}
b99bd4ef 10775
2d447fca
JM
10776static void
10777do_iwmmxt_wmerge (void)
10778{
10779 inst.instruction |= inst.operands[0].reg << 12;
10780 inst.instruction |= inst.operands[1].reg << 16;
10781 inst.instruction |= inst.operands[2].reg;
10782 inst.instruction |= inst.operands[3].imm << 21;
10783}
10784
c19d1205
ZW
10785static void
10786do_iwmmxt_wmov (void)
10787{
10788 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10789 inst.instruction |= inst.operands[0].reg << 12;
10790 inst.instruction |= inst.operands[1].reg << 16;
10791 inst.instruction |= inst.operands[1].reg;
10792}
b99bd4ef 10793
c19d1205
ZW
10794static void
10795do_iwmmxt_wldstbh (void)
10796{
8f06b2d8 10797 int reloc;
c19d1205 10798 inst.instruction |= inst.operands[0].reg << 12;
8f06b2d8
PB
10799 if (thumb_mode)
10800 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
10801 else
10802 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
10803 encode_arm_cp_address (1, TRUE, FALSE, reloc);
b99bd4ef
NC
10804}
10805
c19d1205
ZW
10806static void
10807do_iwmmxt_wldstw (void)
10808{
10809 /* RIWR_RIWC clears .isreg for a control register. */
10810 if (!inst.operands[0].isreg)
10811 {
10812 constraint (inst.cond != COND_ALWAYS, BAD_COND);
10813 inst.instruction |= 0xf0000000;
10814 }
b99bd4ef 10815
c19d1205
ZW
10816 inst.instruction |= inst.operands[0].reg << 12;
10817 encode_arm_cp_address (1, TRUE, TRUE, 0);
10818}
b99bd4ef
NC
10819
10820static void
c19d1205 10821do_iwmmxt_wldstd (void)
b99bd4ef 10822{
c19d1205 10823 inst.instruction |= inst.operands[0].reg << 12;
2d447fca
JM
10824 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
10825 && inst.operands[1].immisreg)
10826 {
10827 inst.instruction &= ~0x1a000ff;
eff0bc54 10828 inst.instruction |= (0xfU << 28);
2d447fca
JM
10829 if (inst.operands[1].preind)
10830 inst.instruction |= PRE_INDEX;
10831 if (!inst.operands[1].negative)
10832 inst.instruction |= INDEX_UP;
10833 if (inst.operands[1].writeback)
10834 inst.instruction |= WRITE_BACK;
10835 inst.instruction |= inst.operands[1].reg << 16;
e2b0ab59 10836 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
2d447fca
JM
10837 inst.instruction |= inst.operands[1].imm;
10838 }
10839 else
10840 encode_arm_cp_address (1, TRUE, FALSE, 0);
c19d1205 10841}
b99bd4ef 10842
c19d1205
ZW
10843static void
10844do_iwmmxt_wshufh (void)
10845{
10846 inst.instruction |= inst.operands[0].reg << 12;
10847 inst.instruction |= inst.operands[1].reg << 16;
10848 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
10849 inst.instruction |= (inst.operands[2].imm & 0x0f);
10850}
b99bd4ef 10851
c19d1205
ZW
10852static void
10853do_iwmmxt_wzero (void)
10854{
10855 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10856 inst.instruction |= inst.operands[0].reg;
10857 inst.instruction |= inst.operands[0].reg << 12;
10858 inst.instruction |= inst.operands[0].reg << 16;
10859}
2d447fca
JM
10860
10861static void
10862do_iwmmxt_wrwrwr_or_imm5 (void)
10863{
10864 if (inst.operands[2].isreg)
10865 do_rd_rn_rm ();
10866 else {
10867 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
10868 _("immediate operand requires iWMMXt2"));
10869 do_rd_rn ();
10870 if (inst.operands[2].imm == 0)
10871 {
10872 switch ((inst.instruction >> 20) & 0xf)
10873 {
10874 case 4:
10875 case 5:
10876 case 6:
5f4273c7 10877 case 7:
2d447fca
JM
10878 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10879 inst.operands[2].imm = 16;
10880 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
10881 break;
10882 case 8:
10883 case 9:
10884 case 10:
10885 case 11:
10886 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10887 inst.operands[2].imm = 32;
10888 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
10889 break;
10890 case 12:
10891 case 13:
10892 case 14:
10893 case 15:
10894 {
10895 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10896 unsigned long wrn;
10897 wrn = (inst.instruction >> 16) & 0xf;
10898 inst.instruction &= 0xff0fff0f;
10899 inst.instruction |= wrn;
10900 /* Bail out here; the instruction is now assembled. */
10901 return;
10902 }
10903 }
10904 }
10905 /* Map 32 -> 0, etc. */
10906 inst.operands[2].imm &= 0x1f;
eff0bc54 10907 inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
2d447fca
JM
10908 }
10909}
c19d1205
ZW
10910\f
10911/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10912 operations first, then control, shift, and load/store. */
b99bd4ef 10913
c19d1205 10914/* Insns like "foo X,Y,Z". */
b99bd4ef 10915
c19d1205
ZW
10916static void
10917do_mav_triple (void)
10918{
10919 inst.instruction |= inst.operands[0].reg << 16;
10920 inst.instruction |= inst.operands[1].reg;
10921 inst.instruction |= inst.operands[2].reg << 12;
10922}
b99bd4ef 10923
c19d1205
ZW
10924/* Insns like "foo W,X,Y,Z".
10925 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
a737bd4d 10926
c19d1205
ZW
10927static void
10928do_mav_quad (void)
10929{
10930 inst.instruction |= inst.operands[0].reg << 5;
10931 inst.instruction |= inst.operands[1].reg << 12;
10932 inst.instruction |= inst.operands[2].reg << 16;
10933 inst.instruction |= inst.operands[3].reg;
a737bd4d
NC
10934}
10935
c19d1205
ZW
10936/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10937static void
10938do_mav_dspsc (void)
a737bd4d 10939{
c19d1205
ZW
10940 inst.instruction |= inst.operands[1].reg << 12;
10941}
a737bd4d 10942
c19d1205
ZW
10943/* Maverick shift immediate instructions.
10944 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10945 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
a737bd4d 10946
c19d1205
ZW
10947static void
10948do_mav_shift (void)
10949{
10950 int imm = inst.operands[2].imm;
a737bd4d 10951
c19d1205
ZW
10952 inst.instruction |= inst.operands[0].reg << 12;
10953 inst.instruction |= inst.operands[1].reg << 16;
a737bd4d 10954
c19d1205
ZW
10955 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10956 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10957 Bit 4 should be 0. */
10958 imm = (imm & 0xf) | ((imm & 0x70) << 1);
a737bd4d 10959
c19d1205
ZW
10960 inst.instruction |= imm;
10961}
10962\f
10963/* XScale instructions. Also sorted arithmetic before move. */
a737bd4d 10964
c19d1205
ZW
10965/* Xscale multiply-accumulate (argument parse)
10966 MIAcc acc0,Rm,Rs
10967 MIAPHcc acc0,Rm,Rs
10968 MIAxycc acc0,Rm,Rs. */
a737bd4d 10969
c19d1205
ZW
10970static void
10971do_xsc_mia (void)
10972{
10973 inst.instruction |= inst.operands[1].reg;
10974 inst.instruction |= inst.operands[2].reg << 12;
10975}
a737bd4d 10976
c19d1205 10977/* Xscale move-accumulator-register (argument parse)
a737bd4d 10978
c19d1205 10979 MARcc acc0,RdLo,RdHi. */
b99bd4ef 10980
c19d1205
ZW
10981static void
10982do_xsc_mar (void)
10983{
10984 inst.instruction |= inst.operands[1].reg << 12;
10985 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC
10986}
10987
c19d1205 10988/* Xscale move-register-accumulator (argument parse)
b99bd4ef 10989
c19d1205 10990 MRAcc RdLo,RdHi,acc0. */
b99bd4ef
NC
10991
10992static void
c19d1205 10993do_xsc_mra (void)
b99bd4ef 10994{
c19d1205
ZW
10995 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
10996 inst.instruction |= inst.operands[0].reg << 12;
10997 inst.instruction |= inst.operands[1].reg << 16;
10998}
10999\f
11000/* Encoding functions relevant only to Thumb. */
b99bd4ef 11001
c19d1205
ZW
11002/* inst.operands[i] is a shifted-register operand; encode
11003 it into inst.instruction in the format used by Thumb32. */
11004
11005static void
11006encode_thumb32_shifted_operand (int i)
11007{
e2b0ab59 11008 unsigned int value = inst.relocs[0].exp.X_add_number;
c19d1205 11009 unsigned int shift = inst.operands[i].shift_kind;
b99bd4ef 11010
9c3c69f2
PB
11011 constraint (inst.operands[i].immisreg,
11012 _("shift by register not allowed in thumb mode"));
c19d1205
ZW
11013 inst.instruction |= inst.operands[i].reg;
11014 if (shift == SHIFT_RRX)
11015 inst.instruction |= SHIFT_ROR << 4;
11016 else
b99bd4ef 11017 {
e2b0ab59 11018 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205
ZW
11019 _("expression too complex"));
11020
11021 constraint (value > 32
11022 || (value == 32 && (shift == SHIFT_LSL
11023 || shift == SHIFT_ROR)),
11024 _("shift expression is too large"));
11025
11026 if (value == 0)
11027 shift = SHIFT_LSL;
11028 else if (value == 32)
11029 value = 0;
11030
11031 inst.instruction |= shift << 4;
11032 inst.instruction |= (value & 0x1c) << 10;
11033 inst.instruction |= (value & 0x03) << 6;
b99bd4ef 11034 }
c19d1205 11035}
b99bd4ef 11036
b99bd4ef 11037
c19d1205
ZW
11038/* inst.operands[i] was set up by parse_address. Encode it into a
11039 Thumb32 format load or store instruction. Reject forms that cannot
11040 be used with such instructions. If is_t is true, reject forms that
11041 cannot be used with a T instruction; if is_d is true, reject forms
5be8be5d
DG
11042 that cannot be used with a D instruction. If it is a store insn,
11043 reject PC in Rn. */
b99bd4ef 11044
c19d1205
ZW
11045static void
11046encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
11047{
5be8be5d 11048 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
c19d1205
ZW
11049
11050 constraint (!inst.operands[i].isreg,
53365c0d 11051 _("Instruction does not support =N addresses"));
b99bd4ef 11052
c19d1205
ZW
11053 inst.instruction |= inst.operands[i].reg << 16;
11054 if (inst.operands[i].immisreg)
b99bd4ef 11055 {
5be8be5d 11056 constraint (is_pc, BAD_PC_ADDRESSING);
c19d1205
ZW
11057 constraint (is_t || is_d, _("cannot use register index with this instruction"));
11058 constraint (inst.operands[i].negative,
11059 _("Thumb does not support negative register indexing"));
11060 constraint (inst.operands[i].postind,
11061 _("Thumb does not support register post-indexing"));
11062 constraint (inst.operands[i].writeback,
11063 _("Thumb does not support register indexing with writeback"));
11064 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
11065 _("Thumb supports only LSL in shifted register indexing"));
b99bd4ef 11066
f40d1643 11067 inst.instruction |= inst.operands[i].imm;
c19d1205 11068 if (inst.operands[i].shifted)
b99bd4ef 11069 {
e2b0ab59 11070 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205 11071 _("expression too complex"));
e2b0ab59
AV
11072 constraint (inst.relocs[0].exp.X_add_number < 0
11073 || inst.relocs[0].exp.X_add_number > 3,
c19d1205 11074 _("shift out of range"));
e2b0ab59 11075 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
c19d1205 11076 }
e2b0ab59 11077 inst.relocs[0].type = BFD_RELOC_UNUSED;
c19d1205
ZW
11078 }
11079 else if (inst.operands[i].preind)
11080 {
5be8be5d 11081 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
f40d1643 11082 constraint (is_t && inst.operands[i].writeback,
c19d1205 11083 _("cannot use writeback with this instruction"));
4755303e
WN
11084 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
11085 BAD_PC_ADDRESSING);
c19d1205
ZW
11086
11087 if (is_d)
11088 {
11089 inst.instruction |= 0x01000000;
11090 if (inst.operands[i].writeback)
11091 inst.instruction |= 0x00200000;
b99bd4ef 11092 }
c19d1205 11093 else
b99bd4ef 11094 {
c19d1205
ZW
11095 inst.instruction |= 0x00000c00;
11096 if (inst.operands[i].writeback)
11097 inst.instruction |= 0x00000100;
b99bd4ef 11098 }
e2b0ab59 11099 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
b99bd4ef 11100 }
c19d1205 11101 else if (inst.operands[i].postind)
b99bd4ef 11102 {
9c2799c2 11103 gas_assert (inst.operands[i].writeback);
c19d1205
ZW
11104 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
11105 constraint (is_t, _("cannot use post-indexing with this instruction"));
11106
11107 if (is_d)
11108 inst.instruction |= 0x00200000;
11109 else
11110 inst.instruction |= 0x00000900;
e2b0ab59 11111 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
c19d1205
ZW
11112 }
11113 else /* unindexed - only for coprocessor */
11114 inst.error = _("instruction does not accept unindexed addressing");
11115}
11116
e39c1607 11117/* Table of Thumb instructions which exist in 16- and/or 32-bit
c19d1205
ZW
11118 encodings (the latter only in post-V6T2 cores). The index is the
11119 value used in the insns table below. When there is more than one
11120 possible 16-bit encoding for the instruction, this table always
0110f2b8
PB
11121 holds variant (1).
11122 Also contains several pseudo-instructions used during relaxation. */
c19d1205 11123#define T16_32_TAB \
21d799b5
NC
11124 X(_adc, 4140, eb400000), \
11125 X(_adcs, 4140, eb500000), \
11126 X(_add, 1c00, eb000000), \
11127 X(_adds, 1c00, eb100000), \
11128 X(_addi, 0000, f1000000), \
11129 X(_addis, 0000, f1100000), \
11130 X(_add_pc,000f, f20f0000), \
11131 X(_add_sp,000d, f10d0000), \
11132 X(_adr, 000f, f20f0000), \
11133 X(_and, 4000, ea000000), \
11134 X(_ands, 4000, ea100000), \
11135 X(_asr, 1000, fa40f000), \
11136 X(_asrs, 1000, fa50f000), \
11137 X(_b, e000, f000b000), \
11138 X(_bcond, d000, f0008000), \
4389b29a 11139 X(_bf, 0000, f040e001), \
f6b2b12d 11140 X(_bfcsel,0000, f000e001), \
f1c7f421 11141 X(_bfx, 0000, f060e001), \
65d1bc05 11142 X(_bfl, 0000, f000c001), \
f1c7f421 11143 X(_bflx, 0000, f070e001), \
21d799b5
NC
11144 X(_bic, 4380, ea200000), \
11145 X(_bics, 4380, ea300000), \
e39c1607
SD
11146 X(_cinc, 0000, ea509000), \
11147 X(_cinv, 0000, ea50a000), \
21d799b5
NC
11148 X(_cmn, 42c0, eb100f00), \
11149 X(_cmp, 2800, ebb00f00), \
e39c1607 11150 X(_cneg, 0000, ea50b000), \
21d799b5
NC
11151 X(_cpsie, b660, f3af8400), \
11152 X(_cpsid, b670, f3af8600), \
11153 X(_cpy, 4600, ea4f0000), \
e39c1607
SD
11154 X(_csel, 0000, ea508000), \
11155 X(_cset, 0000, ea5f900f), \
11156 X(_csetm, 0000, ea5fa00f), \
11157 X(_csinc, 0000, ea509000), \
11158 X(_csinv, 0000, ea50a000), \
11159 X(_csneg, 0000, ea50b000), \
21d799b5 11160 X(_dec_sp,80dd, f1ad0d00), \
60f993ce 11161 X(_dls, 0000, f040e001), \
1f6234a3 11162 X(_dlstp, 0000, f000e001), \
21d799b5
NC
11163 X(_eor, 4040, ea800000), \
11164 X(_eors, 4040, ea900000), \
11165 X(_inc_sp,00dd, f10d0d00), \
1f6234a3 11166 X(_lctp, 0000, f00fe001), \
21d799b5
NC
11167 X(_ldmia, c800, e8900000), \
11168 X(_ldr, 6800, f8500000), \
11169 X(_ldrb, 7800, f8100000), \
11170 X(_ldrh, 8800, f8300000), \
11171 X(_ldrsb, 5600, f9100000), \
11172 X(_ldrsh, 5e00, f9300000), \
11173 X(_ldr_pc,4800, f85f0000), \
11174 X(_ldr_pc2,4800, f85f0000), \
11175 X(_ldr_sp,9800, f85d0000), \
60f993ce 11176 X(_le, 0000, f00fc001), \
1f6234a3 11177 X(_letp, 0000, f01fc001), \
21d799b5
NC
11178 X(_lsl, 0000, fa00f000), \
11179 X(_lsls, 0000, fa10f000), \
11180 X(_lsr, 0800, fa20f000), \
11181 X(_lsrs, 0800, fa30f000), \
11182 X(_mov, 2000, ea4f0000), \
11183 X(_movs, 2000, ea5f0000), \
11184 X(_mul, 4340, fb00f000), \
11185 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11186 X(_mvn, 43c0, ea6f0000), \
11187 X(_mvns, 43c0, ea7f0000), \
11188 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11189 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11190 X(_orr, 4300, ea400000), \
11191 X(_orrs, 4300, ea500000), \
11192 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11193 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11194 X(_rev, ba00, fa90f080), \
11195 X(_rev16, ba40, fa90f090), \
11196 X(_revsh, bac0, fa90f0b0), \
11197 X(_ror, 41c0, fa60f000), \
11198 X(_rors, 41c0, fa70f000), \
11199 X(_sbc, 4180, eb600000), \
11200 X(_sbcs, 4180, eb700000), \
11201 X(_stmia, c000, e8800000), \
11202 X(_str, 6000, f8400000), \
11203 X(_strb, 7000, f8000000), \
11204 X(_strh, 8000, f8200000), \
11205 X(_str_sp,9000, f84d0000), \
11206 X(_sub, 1e00, eba00000), \
11207 X(_subs, 1e00, ebb00000), \
11208 X(_subi, 8000, f1a00000), \
11209 X(_subis, 8000, f1b00000), \
11210 X(_sxtb, b240, fa4ff080), \
11211 X(_sxth, b200, fa0ff080), \
11212 X(_tst, 4200, ea100f00), \
11213 X(_uxtb, b2c0, fa5ff080), \
11214 X(_uxth, b280, fa1ff080), \
11215 X(_nop, bf00, f3af8000), \
11216 X(_yield, bf10, f3af8001), \
11217 X(_wfe, bf20, f3af8002), \
11218 X(_wfi, bf30, f3af8003), \
60f993ce 11219 X(_wls, 0000, f040c001), \
1f6234a3 11220 X(_wlstp, 0000, f000c001), \
53c4b28b 11221 X(_sev, bf40, f3af8004), \
74db7efb
NC
11222 X(_sevl, bf50, f3af8005), \
11223 X(_udf, de00, f7f0a000)
c19d1205
ZW
11224
11225/* To catch errors in encoding functions, the codes are all offset by
11226 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11227 as 16-bit instructions. */
21d799b5 11228#define X(a,b,c) T_MNEM##a
c19d1205
ZW
11229enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
11230#undef X
11231
11232#define X(a,b,c) 0x##b
11233static const unsigned short thumb_op16[] = { T16_32_TAB };
11234#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11235#undef X
11236
11237#define X(a,b,c) 0x##c
11238static const unsigned int thumb_op32[] = { T16_32_TAB };
c921be7d
NC
11239#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11240#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
c19d1205
ZW
11241#undef X
11242#undef T16_32_TAB
11243
11244/* Thumb instruction encoders, in alphabetical order. */
11245
92e90b6e 11246/* ADDW or SUBW. */
c921be7d 11247
92e90b6e
PB
11248static void
11249do_t_add_sub_w (void)
11250{
11251 int Rd, Rn;
11252
11253 Rd = inst.operands[0].reg;
11254 Rn = inst.operands[1].reg;
11255
539d4391
NC
11256 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11257 is the SP-{plus,minus}-immediate form of the instruction. */
11258 if (Rn == REG_SP)
11259 constraint (Rd == REG_PC, BAD_PC);
11260 else
11261 reject_bad_reg (Rd);
fdfde340 11262
92e90b6e 11263 inst.instruction |= (Rn << 16) | (Rd << 8);
e2b0ab59 11264 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
92e90b6e
PB
11265}
11266
c19d1205 11267/* Parse an add or subtract instruction. We get here with inst.instruction
33eaf5de 11268 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
c19d1205
ZW
11269
11270static void
11271do_t_add_sub (void)
11272{
11273 int Rd, Rs, Rn;
11274
11275 Rd = inst.operands[0].reg;
11276 Rs = (inst.operands[1].present
11277 ? inst.operands[1].reg /* Rd, Rs, foo */
11278 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11279
e07e6e58 11280 if (Rd == REG_PC)
5ee91343 11281 set_pred_insn_type_last ();
e07e6e58 11282
c19d1205
ZW
11283 if (unified_syntax)
11284 {
0110f2b8
PB
11285 bfd_boolean flags;
11286 bfd_boolean narrow;
11287 int opcode;
11288
11289 flags = (inst.instruction == T_MNEM_adds
11290 || inst.instruction == T_MNEM_subs);
11291 if (flags)
5ee91343 11292 narrow = !in_pred_block ();
0110f2b8 11293 else
5ee91343 11294 narrow = in_pred_block ();
c19d1205 11295 if (!inst.operands[2].isreg)
b99bd4ef 11296 {
16805f35
PB
11297 int add;
11298
5c8ed6a4
JW
11299 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11300 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
fdfde340 11301
16805f35
PB
11302 add = (inst.instruction == T_MNEM_add
11303 || inst.instruction == T_MNEM_adds);
0110f2b8
PB
11304 opcode = 0;
11305 if (inst.size_req != 4)
11306 {
0110f2b8 11307 /* Attempt to use a narrow opcode, with relaxation if
477330fc 11308 appropriate. */
0110f2b8
PB
11309 if (Rd == REG_SP && Rs == REG_SP && !flags)
11310 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
11311 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
11312 opcode = T_MNEM_add_sp;
11313 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
11314 opcode = T_MNEM_add_pc;
11315 else if (Rd <= 7 && Rs <= 7 && narrow)
11316 {
11317 if (flags)
11318 opcode = add ? T_MNEM_addis : T_MNEM_subis;
11319 else
11320 opcode = add ? T_MNEM_addi : T_MNEM_subi;
11321 }
11322 if (opcode)
11323 {
11324 inst.instruction = THUMB_OP16(opcode);
11325 inst.instruction |= (Rd << 4) | Rs;
e2b0ab59
AV
11326 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11327 || (inst.relocs[0].type
11328 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC))
a9f02af8
MG
11329 {
11330 if (inst.size_req == 2)
e2b0ab59 11331 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
a9f02af8
MG
11332 else
11333 inst.relax = opcode;
11334 }
0110f2b8
PB
11335 }
11336 else
11337 constraint (inst.size_req == 2, BAD_HIREG);
11338 }
11339 if (inst.size_req == 4
11340 || (inst.size_req != 2 && !opcode))
11341 {
e2b0ab59
AV
11342 constraint ((inst.relocs[0].type
11343 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
11344 && (inst.relocs[0].type
11345 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
a9f02af8 11346 THUMB1_RELOC_ONLY);
efd81785
PB
11347 if (Rd == REG_PC)
11348 {
fdfde340 11349 constraint (add, BAD_PC);
efd81785
PB
11350 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
11351 _("only SUBS PC, LR, #const allowed"));
e2b0ab59 11352 constraint (inst.relocs[0].exp.X_op != O_constant,
efd81785 11353 _("expression too complex"));
e2b0ab59
AV
11354 constraint (inst.relocs[0].exp.X_add_number < 0
11355 || inst.relocs[0].exp.X_add_number > 0xff,
efd81785
PB
11356 _("immediate value out of range"));
11357 inst.instruction = T2_SUBS_PC_LR
e2b0ab59
AV
11358 | inst.relocs[0].exp.X_add_number;
11359 inst.relocs[0].type = BFD_RELOC_UNUSED;
efd81785
PB
11360 return;
11361 }
11362 else if (Rs == REG_PC)
16805f35
PB
11363 {
11364 /* Always use addw/subw. */
11365 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
e2b0ab59 11366 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
16805f35
PB
11367 }
11368 else
11369 {
11370 inst.instruction = THUMB_OP32 (inst.instruction);
11371 inst.instruction = (inst.instruction & 0xe1ffffff)
11372 | 0x10000000;
11373 if (flags)
e2b0ab59 11374 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
16805f35 11375 else
e2b0ab59 11376 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_IMM;
16805f35 11377 }
dc4503c6
PB
11378 inst.instruction |= Rd << 8;
11379 inst.instruction |= Rs << 16;
0110f2b8 11380 }
b99bd4ef 11381 }
c19d1205
ZW
11382 else
11383 {
e2b0ab59 11384 unsigned int value = inst.relocs[0].exp.X_add_number;
5f4cb198
NC
11385 unsigned int shift = inst.operands[2].shift_kind;
11386
c19d1205
ZW
11387 Rn = inst.operands[2].reg;
11388 /* See if we can do this with a 16-bit instruction. */
11389 if (!inst.operands[2].shifted && inst.size_req != 4)
11390 {
e27ec89e
PB
11391 if (Rd > 7 || Rs > 7 || Rn > 7)
11392 narrow = FALSE;
11393
11394 if (narrow)
c19d1205 11395 {
e27ec89e
PB
11396 inst.instruction = ((inst.instruction == T_MNEM_adds
11397 || inst.instruction == T_MNEM_add)
c19d1205
ZW
11398 ? T_OPCODE_ADD_R3
11399 : T_OPCODE_SUB_R3);
11400 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11401 return;
11402 }
b99bd4ef 11403
7e806470 11404 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
c19d1205 11405 {
7e806470
PB
11406 /* Thumb-1 cores (except v6-M) require at least one high
11407 register in a narrow non flag setting add. */
11408 if (Rd > 7 || Rn > 7
11409 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
11410 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
c19d1205 11411 {
7e806470
PB
11412 if (Rd == Rn)
11413 {
11414 Rn = Rs;
11415 Rs = Rd;
11416 }
c19d1205
ZW
11417 inst.instruction = T_OPCODE_ADD_HI;
11418 inst.instruction |= (Rd & 8) << 4;
11419 inst.instruction |= (Rd & 7);
11420 inst.instruction |= Rn << 3;
11421 return;
11422 }
c19d1205
ZW
11423 }
11424 }
c921be7d 11425
fdfde340 11426 constraint (Rd == REG_PC, BAD_PC);
5c8ed6a4
JW
11427 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11428 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
fdfde340
JM
11429 constraint (Rs == REG_PC, BAD_PC);
11430 reject_bad_reg (Rn);
11431
c19d1205
ZW
11432 /* If we get here, it can't be done in 16 bits. */
11433 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
11434 _("shift must be constant"));
11435 inst.instruction = THUMB_OP32 (inst.instruction);
11436 inst.instruction |= Rd << 8;
11437 inst.instruction |= Rs << 16;
5f4cb198
NC
11438 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
11439 _("shift value over 3 not allowed in thumb mode"));
11440 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
11441 _("only LSL shift allowed in thumb mode"));
c19d1205
ZW
11442 encode_thumb32_shifted_operand (2);
11443 }
11444 }
11445 else
11446 {
11447 constraint (inst.instruction == T_MNEM_adds
11448 || inst.instruction == T_MNEM_subs,
11449 BAD_THUMB32);
b99bd4ef 11450
c19d1205 11451 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
b99bd4ef 11452 {
c19d1205
ZW
11453 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
11454 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
11455 BAD_HIREG);
11456
11457 inst.instruction = (inst.instruction == T_MNEM_add
11458 ? 0x0000 : 0x8000);
11459 inst.instruction |= (Rd << 4) | Rs;
e2b0ab59 11460 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
b99bd4ef
NC
11461 return;
11462 }
11463
c19d1205
ZW
11464 Rn = inst.operands[2].reg;
11465 constraint (inst.operands[2].shifted, _("unshifted register required"));
b99bd4ef 11466
c19d1205
ZW
11467 /* We now have Rd, Rs, and Rn set to registers. */
11468 if (Rd > 7 || Rs > 7 || Rn > 7)
b99bd4ef 11469 {
c19d1205
ZW
11470 /* Can't do this for SUB. */
11471 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
11472 inst.instruction = T_OPCODE_ADD_HI;
11473 inst.instruction |= (Rd & 8) << 4;
11474 inst.instruction |= (Rd & 7);
11475 if (Rs == Rd)
11476 inst.instruction |= Rn << 3;
11477 else if (Rn == Rd)
11478 inst.instruction |= Rs << 3;
11479 else
11480 constraint (1, _("dest must overlap one source register"));
11481 }
11482 else
11483 {
11484 inst.instruction = (inst.instruction == T_MNEM_add
11485 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
11486 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
b99bd4ef 11487 }
b99bd4ef 11488 }
b99bd4ef
NC
11489}
11490
c19d1205
ZW
11491static void
11492do_t_adr (void)
11493{
fdfde340
JM
11494 unsigned Rd;
11495
11496 Rd = inst.operands[0].reg;
11497 reject_bad_reg (Rd);
11498
11499 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
0110f2b8
PB
11500 {
11501 /* Defer to section relaxation. */
11502 inst.relax = inst.instruction;
11503 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340 11504 inst.instruction |= Rd << 4;
0110f2b8
PB
11505 }
11506 else if (unified_syntax && inst.size_req != 2)
e9f89963 11507 {
0110f2b8 11508 /* Generate a 32-bit opcode. */
e9f89963 11509 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 11510 inst.instruction |= Rd << 8;
e2b0ab59
AV
11511 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_PC12;
11512 inst.relocs[0].pc_rel = 1;
e9f89963
PB
11513 }
11514 else
11515 {
0110f2b8 11516 /* Generate a 16-bit opcode. */
e9f89963 11517 inst.instruction = THUMB_OP16 (inst.instruction);
e2b0ab59
AV
11518 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11519 inst.relocs[0].exp.X_add_number -= 4; /* PC relative adjust. */
11520 inst.relocs[0].pc_rel = 1;
fdfde340 11521 inst.instruction |= Rd << 4;
e9f89963 11522 }
52a86f84 11523
e2b0ab59
AV
11524 if (inst.relocs[0].exp.X_op == O_symbol
11525 && inst.relocs[0].exp.X_add_symbol != NULL
11526 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
11527 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
11528 inst.relocs[0].exp.X_add_number += 1;
c19d1205 11529}
b99bd4ef 11530
c19d1205
ZW
11531/* Arithmetic instructions for which there is just one 16-bit
11532 instruction encoding, and it allows only two low registers.
11533 For maximal compatibility with ARM syntax, we allow three register
11534 operands even when Thumb-32 instructions are not available, as long
11535 as the first two are identical. For instance, both "sbc r0,r1" and
11536 "sbc r0,r0,r1" are allowed. */
b99bd4ef 11537static void
c19d1205 11538do_t_arit3 (void)
b99bd4ef 11539{
c19d1205 11540 int Rd, Rs, Rn;
b99bd4ef 11541
c19d1205
ZW
11542 Rd = inst.operands[0].reg;
11543 Rs = (inst.operands[1].present
11544 ? inst.operands[1].reg /* Rd, Rs, foo */
11545 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11546 Rn = inst.operands[2].reg;
b99bd4ef 11547
fdfde340
JM
11548 reject_bad_reg (Rd);
11549 reject_bad_reg (Rs);
11550 if (inst.operands[2].isreg)
11551 reject_bad_reg (Rn);
11552
c19d1205 11553 if (unified_syntax)
b99bd4ef 11554 {
c19d1205
ZW
11555 if (!inst.operands[2].isreg)
11556 {
11557 /* For an immediate, we always generate a 32-bit opcode;
11558 section relaxation will shrink it later if possible. */
11559 inst.instruction = THUMB_OP32 (inst.instruction);
11560 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11561 inst.instruction |= Rd << 8;
11562 inst.instruction |= Rs << 16;
e2b0ab59 11563 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
c19d1205
ZW
11564 }
11565 else
11566 {
e27ec89e
PB
11567 bfd_boolean narrow;
11568
c19d1205 11569 /* See if we can do this with a 16-bit instruction. */
e27ec89e 11570 if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 11571 narrow = !in_pred_block ();
e27ec89e 11572 else
5ee91343 11573 narrow = in_pred_block ();
e27ec89e
PB
11574
11575 if (Rd > 7 || Rn > 7 || Rs > 7)
11576 narrow = FALSE;
11577 if (inst.operands[2].shifted)
11578 narrow = FALSE;
11579 if (inst.size_req == 4)
11580 narrow = FALSE;
11581
11582 if (narrow
c19d1205
ZW
11583 && Rd == Rs)
11584 {
11585 inst.instruction = THUMB_OP16 (inst.instruction);
11586 inst.instruction |= Rd;
11587 inst.instruction |= Rn << 3;
11588 return;
11589 }
b99bd4ef 11590
c19d1205
ZW
11591 /* If we get here, it can't be done in 16 bits. */
11592 constraint (inst.operands[2].shifted
11593 && inst.operands[2].immisreg,
11594 _("shift must be constant"));
11595 inst.instruction = THUMB_OP32 (inst.instruction);
11596 inst.instruction |= Rd << 8;
11597 inst.instruction |= Rs << 16;
11598 encode_thumb32_shifted_operand (2);
11599 }
a737bd4d 11600 }
c19d1205 11601 else
b99bd4ef 11602 {
c19d1205
ZW
11603 /* On its face this is a lie - the instruction does set the
11604 flags. However, the only supported mnemonic in this mode
11605 says it doesn't. */
11606 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 11607
c19d1205
ZW
11608 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11609 _("unshifted register required"));
11610 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
11611 constraint (Rd != Rs,
11612 _("dest and source1 must be the same register"));
a737bd4d 11613
c19d1205
ZW
11614 inst.instruction = THUMB_OP16 (inst.instruction);
11615 inst.instruction |= Rd;
11616 inst.instruction |= Rn << 3;
b99bd4ef 11617 }
a737bd4d 11618}
b99bd4ef 11619
c19d1205
ZW
11620/* Similarly, but for instructions where the arithmetic operation is
11621 commutative, so we can allow either of them to be different from
11622 the destination operand in a 16-bit instruction. For instance, all
11623 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11624 accepted. */
11625static void
11626do_t_arit3c (void)
a737bd4d 11627{
c19d1205 11628 int Rd, Rs, Rn;
b99bd4ef 11629
c19d1205
ZW
11630 Rd = inst.operands[0].reg;
11631 Rs = (inst.operands[1].present
11632 ? inst.operands[1].reg /* Rd, Rs, foo */
11633 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11634 Rn = inst.operands[2].reg;
c921be7d 11635
fdfde340
JM
11636 reject_bad_reg (Rd);
11637 reject_bad_reg (Rs);
11638 if (inst.operands[2].isreg)
11639 reject_bad_reg (Rn);
a737bd4d 11640
c19d1205 11641 if (unified_syntax)
a737bd4d 11642 {
c19d1205 11643 if (!inst.operands[2].isreg)
b99bd4ef 11644 {
c19d1205
ZW
11645 /* For an immediate, we always generate a 32-bit opcode;
11646 section relaxation will shrink it later if possible. */
11647 inst.instruction = THUMB_OP32 (inst.instruction);
11648 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11649 inst.instruction |= Rd << 8;
11650 inst.instruction |= Rs << 16;
e2b0ab59 11651 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 11652 }
c19d1205 11653 else
a737bd4d 11654 {
e27ec89e
PB
11655 bfd_boolean narrow;
11656
c19d1205 11657 /* See if we can do this with a 16-bit instruction. */
e27ec89e 11658 if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 11659 narrow = !in_pred_block ();
e27ec89e 11660 else
5ee91343 11661 narrow = in_pred_block ();
e27ec89e
PB
11662
11663 if (Rd > 7 || Rn > 7 || Rs > 7)
11664 narrow = FALSE;
11665 if (inst.operands[2].shifted)
11666 narrow = FALSE;
11667 if (inst.size_req == 4)
11668 narrow = FALSE;
11669
11670 if (narrow)
a737bd4d 11671 {
c19d1205 11672 if (Rd == Rs)
a737bd4d 11673 {
c19d1205
ZW
11674 inst.instruction = THUMB_OP16 (inst.instruction);
11675 inst.instruction |= Rd;
11676 inst.instruction |= Rn << 3;
11677 return;
a737bd4d 11678 }
c19d1205 11679 if (Rd == Rn)
a737bd4d 11680 {
c19d1205
ZW
11681 inst.instruction = THUMB_OP16 (inst.instruction);
11682 inst.instruction |= Rd;
11683 inst.instruction |= Rs << 3;
11684 return;
a737bd4d
NC
11685 }
11686 }
c19d1205
ZW
11687
11688 /* If we get here, it can't be done in 16 bits. */
11689 constraint (inst.operands[2].shifted
11690 && inst.operands[2].immisreg,
11691 _("shift must be constant"));
11692 inst.instruction = THUMB_OP32 (inst.instruction);
11693 inst.instruction |= Rd << 8;
11694 inst.instruction |= Rs << 16;
11695 encode_thumb32_shifted_operand (2);
a737bd4d 11696 }
b99bd4ef 11697 }
c19d1205
ZW
11698 else
11699 {
11700 /* On its face this is a lie - the instruction does set the
11701 flags. However, the only supported mnemonic in this mode
11702 says it doesn't. */
11703 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 11704
c19d1205
ZW
11705 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11706 _("unshifted register required"));
11707 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
11708
11709 inst.instruction = THUMB_OP16 (inst.instruction);
11710 inst.instruction |= Rd;
11711
11712 if (Rd == Rs)
11713 inst.instruction |= Rn << 3;
11714 else if (Rd == Rn)
11715 inst.instruction |= Rs << 3;
11716 else
11717 constraint (1, _("dest must overlap one source register"));
11718 }
a737bd4d
NC
11719}
11720
c19d1205
ZW
11721static void
11722do_t_bfc (void)
a737bd4d 11723{
fdfde340 11724 unsigned Rd;
c19d1205
ZW
11725 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
11726 constraint (msb > 32, _("bit-field extends past end of register"));
11727 /* The instruction encoding stores the LSB and MSB,
11728 not the LSB and width. */
fdfde340
JM
11729 Rd = inst.operands[0].reg;
11730 reject_bad_reg (Rd);
11731 inst.instruction |= Rd << 8;
c19d1205
ZW
11732 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
11733 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
11734 inst.instruction |= msb - 1;
b99bd4ef
NC
11735}
11736
c19d1205
ZW
11737static void
11738do_t_bfi (void)
b99bd4ef 11739{
fdfde340 11740 int Rd, Rn;
c19d1205 11741 unsigned int msb;
b99bd4ef 11742
fdfde340
JM
11743 Rd = inst.operands[0].reg;
11744 reject_bad_reg (Rd);
11745
c19d1205
ZW
11746 /* #0 in second position is alternative syntax for bfc, which is
11747 the same instruction but with REG_PC in the Rm field. */
11748 if (!inst.operands[1].isreg)
fdfde340
JM
11749 Rn = REG_PC;
11750 else
11751 {
11752 Rn = inst.operands[1].reg;
11753 reject_bad_reg (Rn);
11754 }
b99bd4ef 11755
c19d1205
ZW
11756 msb = inst.operands[2].imm + inst.operands[3].imm;
11757 constraint (msb > 32, _("bit-field extends past end of register"));
11758 /* The instruction encoding stores the LSB and MSB,
11759 not the LSB and width. */
fdfde340
JM
11760 inst.instruction |= Rd << 8;
11761 inst.instruction |= Rn << 16;
c19d1205
ZW
11762 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
11763 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
11764 inst.instruction |= msb - 1;
b99bd4ef
NC
11765}
11766
c19d1205
ZW
11767static void
11768do_t_bfx (void)
b99bd4ef 11769{
fdfde340
JM
11770 unsigned Rd, Rn;
11771
11772 Rd = inst.operands[0].reg;
11773 Rn = inst.operands[1].reg;
11774
11775 reject_bad_reg (Rd);
11776 reject_bad_reg (Rn);
11777
c19d1205
ZW
11778 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
11779 _("bit-field extends past end of register"));
fdfde340
JM
11780 inst.instruction |= Rd << 8;
11781 inst.instruction |= Rn << 16;
c19d1205
ZW
11782 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
11783 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
11784 inst.instruction |= inst.operands[3].imm - 1;
11785}
b99bd4ef 11786
c19d1205
ZW
11787/* ARM V5 Thumb BLX (argument parse)
11788 BLX <target_addr> which is BLX(1)
11789 BLX <Rm> which is BLX(2)
11790 Unfortunately, there are two different opcodes for this mnemonic.
11791 So, the insns[].value is not used, and the code here zaps values
11792 into inst.instruction.
b99bd4ef 11793
c19d1205
ZW
11794 ??? How to take advantage of the additional two bits of displacement
11795 available in Thumb32 mode? Need new relocation? */
b99bd4ef 11796
c19d1205
ZW
11797static void
11798do_t_blx (void)
11799{
5ee91343 11800 set_pred_insn_type_last ();
e07e6e58 11801
c19d1205 11802 if (inst.operands[0].isreg)
fdfde340
JM
11803 {
11804 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
11805 /* We have a register, so this is BLX(2). */
11806 inst.instruction |= inst.operands[0].reg << 3;
11807 }
b99bd4ef
NC
11808 else
11809 {
c19d1205 11810 /* No register. This must be BLX(1). */
2fc8bdac 11811 inst.instruction = 0xf000e800;
0855e32b 11812 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
b99bd4ef
NC
11813 }
11814}
11815
c19d1205
ZW
11816static void
11817do_t_branch (void)
b99bd4ef 11818{
0110f2b8 11819 int opcode;
dfa9f0d5 11820 int cond;
2fe88214 11821 bfd_reloc_code_real_type reloc;
dfa9f0d5 11822
e07e6e58 11823 cond = inst.cond;
5ee91343 11824 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN);
e07e6e58 11825
5ee91343 11826 if (in_pred_block ())
dfa9f0d5
PB
11827 {
11828 /* Conditional branches inside IT blocks are encoded as unconditional
477330fc 11829 branches. */
dfa9f0d5 11830 cond = COND_ALWAYS;
dfa9f0d5
PB
11831 }
11832 else
11833 cond = inst.cond;
11834
11835 if (cond != COND_ALWAYS)
0110f2b8
PB
11836 opcode = T_MNEM_bcond;
11837 else
11838 opcode = inst.instruction;
11839
12d6b0b7
RS
11840 if (unified_syntax
11841 && (inst.size_req == 4
10960bfb
PB
11842 || (inst.size_req != 2
11843 && (inst.operands[0].hasreloc
e2b0ab59 11844 || inst.relocs[0].exp.X_op == O_constant))))
c19d1205 11845 {
0110f2b8 11846 inst.instruction = THUMB_OP32(opcode);
dfa9f0d5 11847 if (cond == COND_ALWAYS)
9ae92b05 11848 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
c19d1205
ZW
11849 else
11850 {
ff8646ee
TP
11851 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2),
11852 _("selected architecture does not support "
11853 "wide conditional branch instruction"));
11854
9c2799c2 11855 gas_assert (cond != 0xF);
dfa9f0d5 11856 inst.instruction |= cond << 22;
9ae92b05 11857 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
c19d1205
ZW
11858 }
11859 }
b99bd4ef
NC
11860 else
11861 {
0110f2b8 11862 inst.instruction = THUMB_OP16(opcode);
dfa9f0d5 11863 if (cond == COND_ALWAYS)
9ae92b05 11864 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
c19d1205 11865 else
b99bd4ef 11866 {
dfa9f0d5 11867 inst.instruction |= cond << 8;
9ae92b05 11868 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
b99bd4ef 11869 }
0110f2b8
PB
11870 /* Allow section relaxation. */
11871 if (unified_syntax && inst.size_req != 2)
11872 inst.relax = opcode;
b99bd4ef 11873 }
e2b0ab59
AV
11874 inst.relocs[0].type = reloc;
11875 inst.relocs[0].pc_rel = 1;
b99bd4ef
NC
11876}
11877
8884b720 11878/* Actually do the work for Thumb state bkpt and hlt. The only difference
bacebabc 11879 between the two is the maximum immediate allowed - which is passed in
8884b720 11880 RANGE. */
b99bd4ef 11881static void
8884b720 11882do_t_bkpt_hlt1 (int range)
b99bd4ef 11883{
dfa9f0d5
PB
11884 constraint (inst.cond != COND_ALWAYS,
11885 _("instruction is always unconditional"));
c19d1205 11886 if (inst.operands[0].present)
b99bd4ef 11887 {
8884b720 11888 constraint (inst.operands[0].imm > range,
c19d1205
ZW
11889 _("immediate value out of range"));
11890 inst.instruction |= inst.operands[0].imm;
b99bd4ef 11891 }
8884b720 11892
5ee91343 11893 set_pred_insn_type (NEUTRAL_IT_INSN);
8884b720
MGD
11894}
11895
11896static void
11897do_t_hlt (void)
11898{
11899 do_t_bkpt_hlt1 (63);
11900}
11901
11902static void
11903do_t_bkpt (void)
11904{
11905 do_t_bkpt_hlt1 (255);
b99bd4ef
NC
11906}
11907
11908static void
c19d1205 11909do_t_branch23 (void)
b99bd4ef 11910{
5ee91343 11911 set_pred_insn_type_last ();
0855e32b 11912 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
fa94de6b 11913
0855e32b
NS
11914 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11915 this file. We used to simply ignore the PLT reloc type here --
11916 the branch encoding is now needed to deal with TLSCALL relocs.
11917 So if we see a PLT reloc now, put it back to how it used to be to
11918 keep the preexisting behaviour. */
e2b0ab59
AV
11919 if (inst.relocs[0].type == BFD_RELOC_ARM_PLT32)
11920 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH23;
90e4755a 11921
4343666d 11922#if defined(OBJ_COFF)
c19d1205
ZW
11923 /* If the destination of the branch is a defined symbol which does not have
11924 the THUMB_FUNC attribute, then we must be calling a function which has
11925 the (interfacearm) attribute. We look for the Thumb entry point to that
11926 function and change the branch to refer to that function instead. */
e2b0ab59
AV
11927 if ( inst.relocs[0].exp.X_op == O_symbol
11928 && inst.relocs[0].exp.X_add_symbol != NULL
11929 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
11930 && ! THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
11931 inst.relocs[0].exp.X_add_symbol
11932 = find_real_start (inst.relocs[0].exp.X_add_symbol);
4343666d 11933#endif
90e4755a
RE
11934}
11935
11936static void
c19d1205 11937do_t_bx (void)
90e4755a 11938{
5ee91343 11939 set_pred_insn_type_last ();
c19d1205
ZW
11940 inst.instruction |= inst.operands[0].reg << 3;
11941 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11942 should cause the alignment to be checked once it is known. This is
11943 because BX PC only works if the instruction is word aligned. */
11944}
90e4755a 11945
c19d1205
ZW
11946static void
11947do_t_bxj (void)
11948{
fdfde340 11949 int Rm;
90e4755a 11950
5ee91343 11951 set_pred_insn_type_last ();
fdfde340
JM
11952 Rm = inst.operands[0].reg;
11953 reject_bad_reg (Rm);
11954 inst.instruction |= Rm << 16;
90e4755a
RE
11955}
11956
11957static void
c19d1205 11958do_t_clz (void)
90e4755a 11959{
fdfde340
JM
11960 unsigned Rd;
11961 unsigned Rm;
11962
11963 Rd = inst.operands[0].reg;
11964 Rm = inst.operands[1].reg;
11965
11966 reject_bad_reg (Rd);
11967 reject_bad_reg (Rm);
11968
11969 inst.instruction |= Rd << 8;
11970 inst.instruction |= Rm << 16;
11971 inst.instruction |= Rm;
c19d1205 11972}
90e4755a 11973
e39c1607
SD
11974/* For the Armv8.1-M conditional instructions. */
11975static void
11976do_t_cond (void)
11977{
11978 unsigned Rd, Rn, Rm;
11979 signed int cond;
11980
11981 constraint (inst.cond != COND_ALWAYS, BAD_COND);
11982
11983 Rd = inst.operands[0].reg;
11984 switch (inst.instruction)
11985 {
11986 case T_MNEM_csinc:
11987 case T_MNEM_csinv:
11988 case T_MNEM_csneg:
11989 case T_MNEM_csel:
11990 Rn = inst.operands[1].reg;
11991 Rm = inst.operands[2].reg;
11992 cond = inst.operands[3].imm;
11993 constraint (Rn == REG_SP, BAD_SP);
11994 constraint (Rm == REG_SP, BAD_SP);
11995 break;
11996
11997 case T_MNEM_cinc:
11998 case T_MNEM_cinv:
11999 case T_MNEM_cneg:
12000 Rn = inst.operands[1].reg;
12001 cond = inst.operands[2].imm;
12002 /* Invert the last bit to invert the cond. */
12003 cond = TOGGLE_BIT (cond, 0);
12004 constraint (Rn == REG_SP, BAD_SP);
12005 Rm = Rn;
12006 break;
12007
12008 case T_MNEM_csetm:
12009 case T_MNEM_cset:
12010 cond = inst.operands[1].imm;
12011 /* Invert the last bit to invert the cond. */
12012 cond = TOGGLE_BIT (cond, 0);
12013 Rn = REG_PC;
12014 Rm = REG_PC;
12015 break;
12016
12017 default: abort ();
12018 }
12019
12020 set_pred_insn_type (OUTSIDE_PRED_INSN);
12021 inst.instruction = THUMB_OP32 (inst.instruction);
12022 inst.instruction |= Rd << 8;
12023 inst.instruction |= Rn << 16;
12024 inst.instruction |= Rm;
12025 inst.instruction |= cond << 4;
12026}
12027
91d8b670
JG
12028static void
12029do_t_csdb (void)
12030{
5ee91343 12031 set_pred_insn_type (OUTSIDE_PRED_INSN);
91d8b670
JG
12032}
12033
dfa9f0d5
PB
12034static void
12035do_t_cps (void)
12036{
5ee91343 12037 set_pred_insn_type (OUTSIDE_PRED_INSN);
dfa9f0d5
PB
12038 inst.instruction |= inst.operands[0].imm;
12039}
12040
c19d1205
ZW
12041static void
12042do_t_cpsi (void)
12043{
5ee91343 12044 set_pred_insn_type (OUTSIDE_PRED_INSN);
c19d1205 12045 if (unified_syntax
62b3e311
PB
12046 && (inst.operands[1].present || inst.size_req == 4)
12047 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
90e4755a 12048 {
c19d1205
ZW
12049 unsigned int imod = (inst.instruction & 0x0030) >> 4;
12050 inst.instruction = 0xf3af8000;
12051 inst.instruction |= imod << 9;
12052 inst.instruction |= inst.operands[0].imm << 5;
12053 if (inst.operands[1].present)
12054 inst.instruction |= 0x100 | inst.operands[1].imm;
90e4755a 12055 }
c19d1205 12056 else
90e4755a 12057 {
62b3e311
PB
12058 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
12059 && (inst.operands[0].imm & 4),
12060 _("selected processor does not support 'A' form "
12061 "of this instruction"));
12062 constraint (inst.operands[1].present || inst.size_req == 4,
c19d1205
ZW
12063 _("Thumb does not support the 2-argument "
12064 "form of this instruction"));
12065 inst.instruction |= inst.operands[0].imm;
90e4755a 12066 }
90e4755a
RE
12067}
12068
c19d1205
ZW
12069/* THUMB CPY instruction (argument parse). */
12070
90e4755a 12071static void
c19d1205 12072do_t_cpy (void)
90e4755a 12073{
c19d1205 12074 if (inst.size_req == 4)
90e4755a 12075 {
c19d1205
ZW
12076 inst.instruction = THUMB_OP32 (T_MNEM_mov);
12077 inst.instruction |= inst.operands[0].reg << 8;
12078 inst.instruction |= inst.operands[1].reg;
90e4755a 12079 }
c19d1205 12080 else
90e4755a 12081 {
c19d1205
ZW
12082 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
12083 inst.instruction |= (inst.operands[0].reg & 0x7);
12084 inst.instruction |= inst.operands[1].reg << 3;
90e4755a 12085 }
90e4755a
RE
12086}
12087
90e4755a 12088static void
25fe350b 12089do_t_cbz (void)
90e4755a 12090{
5ee91343 12091 set_pred_insn_type (OUTSIDE_PRED_INSN);
c19d1205
ZW
12092 constraint (inst.operands[0].reg > 7, BAD_HIREG);
12093 inst.instruction |= inst.operands[0].reg;
e2b0ab59
AV
12094 inst.relocs[0].pc_rel = 1;
12095 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH7;
c19d1205 12096}
90e4755a 12097
62b3e311
PB
12098static void
12099do_t_dbg (void)
12100{
12101 inst.instruction |= inst.operands[0].imm;
12102}
12103
12104static void
12105do_t_div (void)
12106{
fdfde340
JM
12107 unsigned Rd, Rn, Rm;
12108
12109 Rd = inst.operands[0].reg;
12110 Rn = (inst.operands[1].present
12111 ? inst.operands[1].reg : Rd);
12112 Rm = inst.operands[2].reg;
12113
12114 reject_bad_reg (Rd);
12115 reject_bad_reg (Rn);
12116 reject_bad_reg (Rm);
12117
12118 inst.instruction |= Rd << 8;
12119 inst.instruction |= Rn << 16;
12120 inst.instruction |= Rm;
62b3e311
PB
12121}
12122
c19d1205
ZW
12123static void
12124do_t_hint (void)
12125{
12126 if (unified_syntax && inst.size_req == 4)
12127 inst.instruction = THUMB_OP32 (inst.instruction);
12128 else
12129 inst.instruction = THUMB_OP16 (inst.instruction);
12130}
90e4755a 12131
c19d1205
ZW
12132static void
12133do_t_it (void)
12134{
12135 unsigned int cond = inst.operands[0].imm;
e27ec89e 12136
5ee91343
AV
12137 set_pred_insn_type (IT_INSN);
12138 now_pred.mask = (inst.instruction & 0xf) | 0x10;
12139 now_pred.cc = cond;
12140 now_pred.warn_deprecated = FALSE;
12141 now_pred.type = SCALAR_PRED;
e27ec89e
PB
12142
12143 /* If the condition is a negative condition, invert the mask. */
c19d1205 12144 if ((cond & 0x1) == 0x0)
90e4755a 12145 {
c19d1205 12146 unsigned int mask = inst.instruction & 0x000f;
90e4755a 12147
c19d1205 12148 if ((mask & 0x7) == 0)
5a01bb1d
MGD
12149 {
12150 /* No conversion needed. */
5ee91343 12151 now_pred.block_length = 1;
5a01bb1d 12152 }
c19d1205 12153 else if ((mask & 0x3) == 0)
5a01bb1d
MGD
12154 {
12155 mask ^= 0x8;
5ee91343 12156 now_pred.block_length = 2;
5a01bb1d 12157 }
e27ec89e 12158 else if ((mask & 0x1) == 0)
5a01bb1d
MGD
12159 {
12160 mask ^= 0xC;
5ee91343 12161 now_pred.block_length = 3;
5a01bb1d 12162 }
c19d1205 12163 else
5a01bb1d
MGD
12164 {
12165 mask ^= 0xE;
5ee91343 12166 now_pred.block_length = 4;
5a01bb1d 12167 }
90e4755a 12168
e27ec89e
PB
12169 inst.instruction &= 0xfff0;
12170 inst.instruction |= mask;
c19d1205 12171 }
90e4755a 12172
c19d1205
ZW
12173 inst.instruction |= cond << 4;
12174}
90e4755a 12175
3c707909
PB
12176/* Helper function used for both push/pop and ldm/stm. */
12177static void
4b5a202f
AV
12178encode_thumb2_multi (bfd_boolean do_io, int base, unsigned mask,
12179 bfd_boolean writeback)
3c707909 12180{
4b5a202f 12181 bfd_boolean load, store;
3c707909 12182
4b5a202f
AV
12183 gas_assert (base != -1 || !do_io);
12184 load = do_io && ((inst.instruction & (1 << 20)) != 0);
12185 store = do_io && !load;
3c707909
PB
12186
12187 if (mask & (1 << 13))
12188 inst.error = _("SP not allowed in register list");
1e5b0379 12189
4b5a202f 12190 if (do_io && (mask & (1 << base)) != 0
1e5b0379
NC
12191 && writeback)
12192 inst.error = _("having the base register in the register list when "
12193 "using write back is UNPREDICTABLE");
12194
3c707909
PB
12195 if (load)
12196 {
e07e6e58 12197 if (mask & (1 << 15))
477330fc
RM
12198 {
12199 if (mask & (1 << 14))
12200 inst.error = _("LR and PC should not both be in register list");
12201 else
5ee91343 12202 set_pred_insn_type_last ();
477330fc 12203 }
3c707909 12204 }
4b5a202f 12205 else if (store)
3c707909
PB
12206 {
12207 if (mask & (1 << 15))
12208 inst.error = _("PC not allowed in register list");
3c707909
PB
12209 }
12210
4b5a202f 12211 if (do_io && ((mask & (mask - 1)) == 0))
3c707909
PB
12212 {
12213 /* Single register transfers implemented as str/ldr. */
12214 if (writeback)
12215 {
12216 if (inst.instruction & (1 << 23))
12217 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
12218 else
12219 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
12220 }
12221 else
12222 {
12223 if (inst.instruction & (1 << 23))
12224 inst.instruction = 0x00800000; /* ia -> [base] */
12225 else
12226 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
12227 }
12228
12229 inst.instruction |= 0xf8400000;
12230 if (load)
12231 inst.instruction |= 0x00100000;
12232
5f4273c7 12233 mask = ffs (mask) - 1;
3c707909
PB
12234 mask <<= 12;
12235 }
12236 else if (writeback)
12237 inst.instruction |= WRITE_BACK;
12238
12239 inst.instruction |= mask;
4b5a202f
AV
12240 if (do_io)
12241 inst.instruction |= base << 16;
3c707909
PB
12242}
12243
c19d1205
ZW
12244static void
12245do_t_ldmstm (void)
12246{
12247 /* This really doesn't seem worth it. */
e2b0ab59 12248 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
c19d1205
ZW
12249 _("expression too complex"));
12250 constraint (inst.operands[1].writeback,
12251 _("Thumb load/store multiple does not support {reglist}^"));
90e4755a 12252
c19d1205
ZW
12253 if (unified_syntax)
12254 {
3c707909
PB
12255 bfd_boolean narrow;
12256 unsigned mask;
12257
12258 narrow = FALSE;
c19d1205
ZW
12259 /* See if we can use a 16-bit instruction. */
12260 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
12261 && inst.size_req != 4
3c707909 12262 && !(inst.operands[1].imm & ~0xff))
90e4755a 12263 {
3c707909 12264 mask = 1 << inst.operands[0].reg;
90e4755a 12265
eab4f823 12266 if (inst.operands[0].reg <= 7)
90e4755a 12267 {
3c707909 12268 if (inst.instruction == T_MNEM_stmia
eab4f823
MGD
12269 ? inst.operands[0].writeback
12270 : (inst.operands[0].writeback
12271 == !(inst.operands[1].imm & mask)))
477330fc 12272 {
eab4f823
MGD
12273 if (inst.instruction == T_MNEM_stmia
12274 && (inst.operands[1].imm & mask)
12275 && (inst.operands[1].imm & (mask - 1)))
12276 as_warn (_("value stored for r%d is UNKNOWN"),
12277 inst.operands[0].reg);
3c707909 12278
eab4f823
MGD
12279 inst.instruction = THUMB_OP16 (inst.instruction);
12280 inst.instruction |= inst.operands[0].reg << 8;
12281 inst.instruction |= inst.operands[1].imm;
12282 narrow = TRUE;
12283 }
12284 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
12285 {
12286 /* This means 1 register in reg list one of 3 situations:
12287 1. Instruction is stmia, but without writeback.
12288 2. lmdia without writeback, but with Rn not in
477330fc 12289 reglist.
eab4f823
MGD
12290 3. ldmia with writeback, but with Rn in reglist.
12291 Case 3 is UNPREDICTABLE behaviour, so we handle
12292 case 1 and 2 which can be converted into a 16-bit
12293 str or ldr. The SP cases are handled below. */
12294 unsigned long opcode;
12295 /* First, record an error for Case 3. */
12296 if (inst.operands[1].imm & mask
12297 && inst.operands[0].writeback)
fa94de6b 12298 inst.error =
eab4f823
MGD
12299 _("having the base register in the register list when "
12300 "using write back is UNPREDICTABLE");
fa94de6b
RM
12301
12302 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
eab4f823
MGD
12303 : T_MNEM_ldr);
12304 inst.instruction = THUMB_OP16 (opcode);
12305 inst.instruction |= inst.operands[0].reg << 3;
12306 inst.instruction |= (ffs (inst.operands[1].imm)-1);
12307 narrow = TRUE;
12308 }
90e4755a 12309 }
eab4f823 12310 else if (inst.operands[0] .reg == REG_SP)
90e4755a 12311 {
eab4f823
MGD
12312 if (inst.operands[0].writeback)
12313 {
fa94de6b 12314 inst.instruction =
eab4f823 12315 THUMB_OP16 (inst.instruction == T_MNEM_stmia
477330fc 12316 ? T_MNEM_push : T_MNEM_pop);
eab4f823 12317 inst.instruction |= inst.operands[1].imm;
477330fc 12318 narrow = TRUE;
eab4f823
MGD
12319 }
12320 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
12321 {
fa94de6b 12322 inst.instruction =
eab4f823 12323 THUMB_OP16 (inst.instruction == T_MNEM_stmia
477330fc 12324 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
eab4f823 12325 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
477330fc 12326 narrow = TRUE;
eab4f823 12327 }
90e4755a 12328 }
3c707909
PB
12329 }
12330
12331 if (!narrow)
12332 {
c19d1205
ZW
12333 if (inst.instruction < 0xffff)
12334 inst.instruction = THUMB_OP32 (inst.instruction);
3c707909 12335
4b5a202f
AV
12336 encode_thumb2_multi (TRUE /* do_io */, inst.operands[0].reg,
12337 inst.operands[1].imm,
12338 inst.operands[0].writeback);
90e4755a
RE
12339 }
12340 }
c19d1205 12341 else
90e4755a 12342 {
c19d1205
ZW
12343 constraint (inst.operands[0].reg > 7
12344 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
1198ca51
PB
12345 constraint (inst.instruction != T_MNEM_ldmia
12346 && inst.instruction != T_MNEM_stmia,
12347 _("Thumb-2 instruction only valid in unified syntax"));
c19d1205 12348 if (inst.instruction == T_MNEM_stmia)
f03698e6 12349 {
c19d1205
ZW
12350 if (!inst.operands[0].writeback)
12351 as_warn (_("this instruction will write back the base register"));
12352 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
12353 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
1e5b0379 12354 as_warn (_("value stored for r%d is UNKNOWN"),
c19d1205 12355 inst.operands[0].reg);
f03698e6 12356 }
c19d1205 12357 else
90e4755a 12358 {
c19d1205
ZW
12359 if (!inst.operands[0].writeback
12360 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
12361 as_warn (_("this instruction will write back the base register"));
12362 else if (inst.operands[0].writeback
12363 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
12364 as_warn (_("this instruction will not write back the base register"));
90e4755a
RE
12365 }
12366
c19d1205
ZW
12367 inst.instruction = THUMB_OP16 (inst.instruction);
12368 inst.instruction |= inst.operands[0].reg << 8;
12369 inst.instruction |= inst.operands[1].imm;
12370 }
12371}
e28cd48c 12372
c19d1205
ZW
12373static void
12374do_t_ldrex (void)
12375{
12376 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
12377 || inst.operands[1].postind || inst.operands[1].writeback
12378 || inst.operands[1].immisreg || inst.operands[1].shifted
12379 || inst.operands[1].negative,
01cfc07f 12380 BAD_ADDR_MODE);
e28cd48c 12381
5be8be5d
DG
12382 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
12383
c19d1205
ZW
12384 inst.instruction |= inst.operands[0].reg << 12;
12385 inst.instruction |= inst.operands[1].reg << 16;
e2b0ab59 12386 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
c19d1205 12387}
e28cd48c 12388
c19d1205
ZW
12389static void
12390do_t_ldrexd (void)
12391{
12392 if (!inst.operands[1].present)
1cac9012 12393 {
c19d1205
ZW
12394 constraint (inst.operands[0].reg == REG_LR,
12395 _("r14 not allowed as first register "
12396 "when second register is omitted"));
12397 inst.operands[1].reg = inst.operands[0].reg + 1;
b99bd4ef 12398 }
c19d1205
ZW
12399 constraint (inst.operands[0].reg == inst.operands[1].reg,
12400 BAD_OVERLAP);
b99bd4ef 12401
c19d1205
ZW
12402 inst.instruction |= inst.operands[0].reg << 12;
12403 inst.instruction |= inst.operands[1].reg << 8;
12404 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC
12405}
12406
12407static void
c19d1205 12408do_t_ldst (void)
b99bd4ef 12409{
0110f2b8
PB
12410 unsigned long opcode;
12411 int Rn;
12412
e07e6e58
NC
12413 if (inst.operands[0].isreg
12414 && !inst.operands[0].preind
12415 && inst.operands[0].reg == REG_PC)
5ee91343 12416 set_pred_insn_type_last ();
e07e6e58 12417
0110f2b8 12418 opcode = inst.instruction;
c19d1205 12419 if (unified_syntax)
b99bd4ef 12420 {
53365c0d
PB
12421 if (!inst.operands[1].isreg)
12422 {
12423 if (opcode <= 0xffff)
12424 inst.instruction = THUMB_OP32 (opcode);
8335d6aa 12425 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
53365c0d
PB
12426 return;
12427 }
0110f2b8
PB
12428 if (inst.operands[1].isreg
12429 && !inst.operands[1].writeback
c19d1205
ZW
12430 && !inst.operands[1].shifted && !inst.operands[1].postind
12431 && !inst.operands[1].negative && inst.operands[0].reg <= 7
0110f2b8
PB
12432 && opcode <= 0xffff
12433 && inst.size_req != 4)
c19d1205 12434 {
0110f2b8
PB
12435 /* Insn may have a 16-bit form. */
12436 Rn = inst.operands[1].reg;
12437 if (inst.operands[1].immisreg)
12438 {
12439 inst.instruction = THUMB_OP16 (opcode);
5f4273c7 12440 /* [Rn, Rik] */
0110f2b8
PB
12441 if (Rn <= 7 && inst.operands[1].imm <= 7)
12442 goto op16;
5be8be5d
DG
12443 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
12444 reject_bad_reg (inst.operands[1].imm);
0110f2b8
PB
12445 }
12446 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
12447 && opcode != T_MNEM_ldrsb)
12448 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
12449 || (Rn == REG_SP && opcode == T_MNEM_str))
12450 {
12451 /* [Rn, #const] */
12452 if (Rn > 7)
12453 {
12454 if (Rn == REG_PC)
12455 {
e2b0ab59 12456 if (inst.relocs[0].pc_rel)
0110f2b8
PB
12457 opcode = T_MNEM_ldr_pc2;
12458 else
12459 opcode = T_MNEM_ldr_pc;
12460 }
12461 else
12462 {
12463 if (opcode == T_MNEM_ldr)
12464 opcode = T_MNEM_ldr_sp;
12465 else
12466 opcode = T_MNEM_str_sp;
12467 }
12468 inst.instruction = inst.operands[0].reg << 8;
12469 }
12470 else
12471 {
12472 inst.instruction = inst.operands[0].reg;
12473 inst.instruction |= inst.operands[1].reg << 3;
12474 }
12475 inst.instruction |= THUMB_OP16 (opcode);
12476 if (inst.size_req == 2)
e2b0ab59 12477 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
0110f2b8
PB
12478 else
12479 inst.relax = opcode;
12480 return;
12481 }
c19d1205 12482 }
0110f2b8 12483 /* Definitely a 32-bit variant. */
5be8be5d 12484
8d67f500
NC
12485 /* Warning for Erratum 752419. */
12486 if (opcode == T_MNEM_ldr
12487 && inst.operands[0].reg == REG_SP
12488 && inst.operands[1].writeback == 1
12489 && !inst.operands[1].immisreg)
12490 {
12491 if (no_cpu_selected ()
12492 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
477330fc
RM
12493 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
12494 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
8d67f500
NC
12495 as_warn (_("This instruction may be unpredictable "
12496 "if executed on M-profile cores "
12497 "with interrupts enabled."));
12498 }
12499
5be8be5d 12500 /* Do some validations regarding addressing modes. */
1be5fd2e 12501 if (inst.operands[1].immisreg)
5be8be5d
DG
12502 reject_bad_reg (inst.operands[1].imm);
12503
1be5fd2e
NC
12504 constraint (inst.operands[1].writeback == 1
12505 && inst.operands[0].reg == inst.operands[1].reg,
12506 BAD_OVERLAP);
12507
0110f2b8 12508 inst.instruction = THUMB_OP32 (opcode);
c19d1205
ZW
12509 inst.instruction |= inst.operands[0].reg << 12;
12510 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
1be5fd2e 12511 check_ldr_r15_aligned ();
b99bd4ef
NC
12512 return;
12513 }
12514
c19d1205
ZW
12515 constraint (inst.operands[0].reg > 7, BAD_HIREG);
12516
12517 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
b99bd4ef 12518 {
c19d1205
ZW
12519 /* Only [Rn,Rm] is acceptable. */
12520 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
12521 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
12522 || inst.operands[1].postind || inst.operands[1].shifted
12523 || inst.operands[1].negative,
12524 _("Thumb does not support this addressing mode"));
12525 inst.instruction = THUMB_OP16 (inst.instruction);
12526 goto op16;
b99bd4ef 12527 }
5f4273c7 12528
c19d1205
ZW
12529 inst.instruction = THUMB_OP16 (inst.instruction);
12530 if (!inst.operands[1].isreg)
8335d6aa 12531 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
c19d1205 12532 return;
b99bd4ef 12533
c19d1205
ZW
12534 constraint (!inst.operands[1].preind
12535 || inst.operands[1].shifted
12536 || inst.operands[1].writeback,
12537 _("Thumb does not support this addressing mode"));
12538 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
90e4755a 12539 {
c19d1205
ZW
12540 constraint (inst.instruction & 0x0600,
12541 _("byte or halfword not valid for base register"));
12542 constraint (inst.operands[1].reg == REG_PC
12543 && !(inst.instruction & THUMB_LOAD_BIT),
12544 _("r15 based store not allowed"));
12545 constraint (inst.operands[1].immisreg,
12546 _("invalid base register for register offset"));
b99bd4ef 12547
c19d1205
ZW
12548 if (inst.operands[1].reg == REG_PC)
12549 inst.instruction = T_OPCODE_LDR_PC;
12550 else if (inst.instruction & THUMB_LOAD_BIT)
12551 inst.instruction = T_OPCODE_LDR_SP;
12552 else
12553 inst.instruction = T_OPCODE_STR_SP;
b99bd4ef 12554
c19d1205 12555 inst.instruction |= inst.operands[0].reg << 8;
e2b0ab59 12556 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
c19d1205
ZW
12557 return;
12558 }
90e4755a 12559
c19d1205
ZW
12560 constraint (inst.operands[1].reg > 7, BAD_HIREG);
12561 if (!inst.operands[1].immisreg)
12562 {
12563 /* Immediate offset. */
12564 inst.instruction |= inst.operands[0].reg;
12565 inst.instruction |= inst.operands[1].reg << 3;
e2b0ab59 12566 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
c19d1205
ZW
12567 return;
12568 }
90e4755a 12569
c19d1205
ZW
12570 /* Register offset. */
12571 constraint (inst.operands[1].imm > 7, BAD_HIREG);
12572 constraint (inst.operands[1].negative,
12573 _("Thumb does not support this addressing mode"));
90e4755a 12574
c19d1205
ZW
12575 op16:
12576 switch (inst.instruction)
12577 {
12578 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
12579 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
12580 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
12581 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
12582 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
12583 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
12584 case 0x5600 /* ldrsb */:
12585 case 0x5e00 /* ldrsh */: break;
12586 default: abort ();
12587 }
90e4755a 12588
c19d1205
ZW
12589 inst.instruction |= inst.operands[0].reg;
12590 inst.instruction |= inst.operands[1].reg << 3;
12591 inst.instruction |= inst.operands[1].imm << 6;
12592}
90e4755a 12593
c19d1205
ZW
12594static void
12595do_t_ldstd (void)
12596{
12597 if (!inst.operands[1].present)
b99bd4ef 12598 {
c19d1205
ZW
12599 inst.operands[1].reg = inst.operands[0].reg + 1;
12600 constraint (inst.operands[0].reg == REG_LR,
12601 _("r14 not allowed here"));
bd340a04 12602 constraint (inst.operands[0].reg == REG_R12,
477330fc 12603 _("r12 not allowed here"));
b99bd4ef 12604 }
bd340a04
MGD
12605
12606 if (inst.operands[2].writeback
12607 && (inst.operands[0].reg == inst.operands[2].reg
12608 || inst.operands[1].reg == inst.operands[2].reg))
12609 as_warn (_("base register written back, and overlaps "
477330fc 12610 "one of transfer registers"));
bd340a04 12611
c19d1205
ZW
12612 inst.instruction |= inst.operands[0].reg << 12;
12613 inst.instruction |= inst.operands[1].reg << 8;
12614 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
b99bd4ef
NC
12615}
12616
c19d1205
ZW
12617static void
12618do_t_ldstt (void)
12619{
12620 inst.instruction |= inst.operands[0].reg << 12;
12621 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
12622}
a737bd4d 12623
b99bd4ef 12624static void
c19d1205 12625do_t_mla (void)
b99bd4ef 12626{
fdfde340 12627 unsigned Rd, Rn, Rm, Ra;
c921be7d 12628
fdfde340
JM
12629 Rd = inst.operands[0].reg;
12630 Rn = inst.operands[1].reg;
12631 Rm = inst.operands[2].reg;
12632 Ra = inst.operands[3].reg;
12633
12634 reject_bad_reg (Rd);
12635 reject_bad_reg (Rn);
12636 reject_bad_reg (Rm);
12637 reject_bad_reg (Ra);
12638
12639 inst.instruction |= Rd << 8;
12640 inst.instruction |= Rn << 16;
12641 inst.instruction |= Rm;
12642 inst.instruction |= Ra << 12;
c19d1205 12643}
b99bd4ef 12644
c19d1205
ZW
12645static void
12646do_t_mlal (void)
12647{
fdfde340
JM
12648 unsigned RdLo, RdHi, Rn, Rm;
12649
12650 RdLo = inst.operands[0].reg;
12651 RdHi = inst.operands[1].reg;
12652 Rn = inst.operands[2].reg;
12653 Rm = inst.operands[3].reg;
12654
12655 reject_bad_reg (RdLo);
12656 reject_bad_reg (RdHi);
12657 reject_bad_reg (Rn);
12658 reject_bad_reg (Rm);
12659
12660 inst.instruction |= RdLo << 12;
12661 inst.instruction |= RdHi << 8;
12662 inst.instruction |= Rn << 16;
12663 inst.instruction |= Rm;
c19d1205 12664}
b99bd4ef 12665
c19d1205
ZW
12666static void
12667do_t_mov_cmp (void)
12668{
fdfde340
JM
12669 unsigned Rn, Rm;
12670
12671 Rn = inst.operands[0].reg;
12672 Rm = inst.operands[1].reg;
12673
e07e6e58 12674 if (Rn == REG_PC)
5ee91343 12675 set_pred_insn_type_last ();
e07e6e58 12676
c19d1205 12677 if (unified_syntax)
b99bd4ef 12678 {
c19d1205
ZW
12679 int r0off = (inst.instruction == T_MNEM_mov
12680 || inst.instruction == T_MNEM_movs) ? 8 : 16;
0110f2b8 12681 unsigned long opcode;
3d388997
PB
12682 bfd_boolean narrow;
12683 bfd_boolean low_regs;
12684
fdfde340 12685 low_regs = (Rn <= 7 && Rm <= 7);
0110f2b8 12686 opcode = inst.instruction;
5ee91343 12687 if (in_pred_block ())
0110f2b8 12688 narrow = opcode != T_MNEM_movs;
3d388997 12689 else
0110f2b8 12690 narrow = opcode != T_MNEM_movs || low_regs;
3d388997
PB
12691 if (inst.size_req == 4
12692 || inst.operands[1].shifted)
12693 narrow = FALSE;
12694
efd81785
PB
12695 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12696 if (opcode == T_MNEM_movs && inst.operands[1].isreg
12697 && !inst.operands[1].shifted
fdfde340
JM
12698 && Rn == REG_PC
12699 && Rm == REG_LR)
efd81785
PB
12700 {
12701 inst.instruction = T2_SUBS_PC_LR;
12702 return;
12703 }
12704
fdfde340
JM
12705 if (opcode == T_MNEM_cmp)
12706 {
12707 constraint (Rn == REG_PC, BAD_PC);
94206790
MM
12708 if (narrow)
12709 {
12710 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12711 but valid. */
12712 warn_deprecated_sp (Rm);
12713 /* R15 was documented as a valid choice for Rm in ARMv6,
12714 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12715 tools reject R15, so we do too. */
12716 constraint (Rm == REG_PC, BAD_PC);
12717 }
12718 else
12719 reject_bad_reg (Rm);
fdfde340
JM
12720 }
12721 else if (opcode == T_MNEM_mov
12722 || opcode == T_MNEM_movs)
12723 {
12724 if (inst.operands[1].isreg)
12725 {
12726 if (opcode == T_MNEM_movs)
12727 {
12728 reject_bad_reg (Rn);
12729 reject_bad_reg (Rm);
12730 }
76fa04a4
MGD
12731 else if (narrow)
12732 {
12733 /* This is mov.n. */
12734 if ((Rn == REG_SP || Rn == REG_PC)
12735 && (Rm == REG_SP || Rm == REG_PC))
12736 {
5c3696f8 12737 as_tsktsk (_("Use of r%u as a source register is "
76fa04a4
MGD
12738 "deprecated when r%u is the destination "
12739 "register."), Rm, Rn);
12740 }
12741 }
12742 else
12743 {
12744 /* This is mov.w. */
12745 constraint (Rn == REG_PC, BAD_PC);
12746 constraint (Rm == REG_PC, BAD_PC);
5c8ed6a4
JW
12747 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
12748 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
76fa04a4 12749 }
fdfde340
JM
12750 }
12751 else
12752 reject_bad_reg (Rn);
12753 }
12754
c19d1205
ZW
12755 if (!inst.operands[1].isreg)
12756 {
0110f2b8 12757 /* Immediate operand. */
5ee91343 12758 if (!in_pred_block () && opcode == T_MNEM_mov)
0110f2b8
PB
12759 narrow = 0;
12760 if (low_regs && narrow)
12761 {
12762 inst.instruction = THUMB_OP16 (opcode);
fdfde340 12763 inst.instruction |= Rn << 8;
e2b0ab59
AV
12764 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12765 || inst.relocs[0].type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
72d98d16 12766 {
a9f02af8 12767 if (inst.size_req == 2)
e2b0ab59 12768 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
a9f02af8
MG
12769 else
12770 inst.relax = opcode;
72d98d16 12771 }
0110f2b8
PB
12772 }
12773 else
12774 {
e2b0ab59
AV
12775 constraint ((inst.relocs[0].type
12776 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
12777 && (inst.relocs[0].type
12778 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
a9f02af8
MG
12779 THUMB1_RELOC_ONLY);
12780
0110f2b8
PB
12781 inst.instruction = THUMB_OP32 (inst.instruction);
12782 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
fdfde340 12783 inst.instruction |= Rn << r0off;
e2b0ab59 12784 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
0110f2b8 12785 }
c19d1205 12786 }
728ca7c9
PB
12787 else if (inst.operands[1].shifted && inst.operands[1].immisreg
12788 && (inst.instruction == T_MNEM_mov
12789 || inst.instruction == T_MNEM_movs))
12790 {
12791 /* Register shifts are encoded as separate shift instructions. */
12792 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
12793
5ee91343 12794 if (in_pred_block ())
728ca7c9
PB
12795 narrow = !flags;
12796 else
12797 narrow = flags;
12798
12799 if (inst.size_req == 4)
12800 narrow = FALSE;
12801
12802 if (!low_regs || inst.operands[1].imm > 7)
12803 narrow = FALSE;
12804
fdfde340 12805 if (Rn != Rm)
728ca7c9
PB
12806 narrow = FALSE;
12807
12808 switch (inst.operands[1].shift_kind)
12809 {
12810 case SHIFT_LSL:
12811 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
12812 break;
12813 case SHIFT_ASR:
12814 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
12815 break;
12816 case SHIFT_LSR:
12817 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
12818 break;
12819 case SHIFT_ROR:
12820 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
12821 break;
12822 default:
5f4273c7 12823 abort ();
728ca7c9
PB
12824 }
12825
12826 inst.instruction = opcode;
12827 if (narrow)
12828 {
fdfde340 12829 inst.instruction |= Rn;
728ca7c9
PB
12830 inst.instruction |= inst.operands[1].imm << 3;
12831 }
12832 else
12833 {
12834 if (flags)
12835 inst.instruction |= CONDS_BIT;
12836
fdfde340
JM
12837 inst.instruction |= Rn << 8;
12838 inst.instruction |= Rm << 16;
728ca7c9
PB
12839 inst.instruction |= inst.operands[1].imm;
12840 }
12841 }
3d388997 12842 else if (!narrow)
c19d1205 12843 {
728ca7c9
PB
12844 /* Some mov with immediate shift have narrow variants.
12845 Register shifts are handled above. */
12846 if (low_regs && inst.operands[1].shifted
12847 && (inst.instruction == T_MNEM_mov
12848 || inst.instruction == T_MNEM_movs))
12849 {
5ee91343 12850 if (in_pred_block ())
728ca7c9
PB
12851 narrow = (inst.instruction == T_MNEM_mov);
12852 else
12853 narrow = (inst.instruction == T_MNEM_movs);
12854 }
12855
12856 if (narrow)
12857 {
12858 switch (inst.operands[1].shift_kind)
12859 {
12860 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
12861 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
12862 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
12863 default: narrow = FALSE; break;
12864 }
12865 }
12866
12867 if (narrow)
12868 {
fdfde340
JM
12869 inst.instruction |= Rn;
12870 inst.instruction |= Rm << 3;
e2b0ab59 12871 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
728ca7c9
PB
12872 }
12873 else
12874 {
12875 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 12876 inst.instruction |= Rn << r0off;
728ca7c9
PB
12877 encode_thumb32_shifted_operand (1);
12878 }
c19d1205
ZW
12879 }
12880 else
12881 switch (inst.instruction)
12882 {
12883 case T_MNEM_mov:
837b3435 12884 /* In v4t or v5t a move of two lowregs produces unpredictable
c6400f8a
MGD
12885 results. Don't allow this. */
12886 if (low_regs)
12887 {
12888 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
12889 "MOV Rd, Rs with two low registers is not "
12890 "permitted on this architecture");
fa94de6b 12891 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
c6400f8a
MGD
12892 arm_ext_v6);
12893 }
12894
c19d1205 12895 inst.instruction = T_OPCODE_MOV_HR;
fdfde340
JM
12896 inst.instruction |= (Rn & 0x8) << 4;
12897 inst.instruction |= (Rn & 0x7);
12898 inst.instruction |= Rm << 3;
c19d1205 12899 break;
b99bd4ef 12900
c19d1205
ZW
12901 case T_MNEM_movs:
12902 /* We know we have low registers at this point.
941a8a52
MGD
12903 Generate LSLS Rd, Rs, #0. */
12904 inst.instruction = T_OPCODE_LSL_I;
fdfde340
JM
12905 inst.instruction |= Rn;
12906 inst.instruction |= Rm << 3;
c19d1205
ZW
12907 break;
12908
12909 case T_MNEM_cmp:
3d388997 12910 if (low_regs)
c19d1205
ZW
12911 {
12912 inst.instruction = T_OPCODE_CMP_LR;
fdfde340
JM
12913 inst.instruction |= Rn;
12914 inst.instruction |= Rm << 3;
c19d1205
ZW
12915 }
12916 else
12917 {
12918 inst.instruction = T_OPCODE_CMP_HR;
fdfde340
JM
12919 inst.instruction |= (Rn & 0x8) << 4;
12920 inst.instruction |= (Rn & 0x7);
12921 inst.instruction |= Rm << 3;
c19d1205
ZW
12922 }
12923 break;
12924 }
b99bd4ef
NC
12925 return;
12926 }
12927
c19d1205 12928 inst.instruction = THUMB_OP16 (inst.instruction);
539d4391
NC
12929
12930 /* PR 10443: Do not silently ignore shifted operands. */
12931 constraint (inst.operands[1].shifted,
12932 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12933
c19d1205 12934 if (inst.operands[1].isreg)
b99bd4ef 12935 {
fdfde340 12936 if (Rn < 8 && Rm < 8)
b99bd4ef 12937 {
c19d1205
ZW
12938 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12939 since a MOV instruction produces unpredictable results. */
12940 if (inst.instruction == T_OPCODE_MOV_I8)
12941 inst.instruction = T_OPCODE_ADD_I3;
b99bd4ef 12942 else
c19d1205 12943 inst.instruction = T_OPCODE_CMP_LR;
b99bd4ef 12944
fdfde340
JM
12945 inst.instruction |= Rn;
12946 inst.instruction |= Rm << 3;
b99bd4ef
NC
12947 }
12948 else
12949 {
c19d1205
ZW
12950 if (inst.instruction == T_OPCODE_MOV_I8)
12951 inst.instruction = T_OPCODE_MOV_HR;
12952 else
12953 inst.instruction = T_OPCODE_CMP_HR;
12954 do_t_cpy ();
b99bd4ef
NC
12955 }
12956 }
c19d1205 12957 else
b99bd4ef 12958 {
fdfde340 12959 constraint (Rn > 7,
c19d1205 12960 _("only lo regs allowed with immediate"));
fdfde340 12961 inst.instruction |= Rn << 8;
e2b0ab59 12962 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
c19d1205
ZW
12963 }
12964}
b99bd4ef 12965
c19d1205
ZW
12966static void
12967do_t_mov16 (void)
12968{
fdfde340 12969 unsigned Rd;
b6895b4f
PB
12970 bfd_vma imm;
12971 bfd_boolean top;
12972
12973 top = (inst.instruction & 0x00800000) != 0;
e2b0ab59 12974 if (inst.relocs[0].type == BFD_RELOC_ARM_MOVW)
b6895b4f 12975 {
33eaf5de 12976 constraint (top, _(":lower16: not allowed in this instruction"));
e2b0ab59 12977 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVW;
b6895b4f 12978 }
e2b0ab59 12979 else if (inst.relocs[0].type == BFD_RELOC_ARM_MOVT)
b6895b4f 12980 {
33eaf5de 12981 constraint (!top, _(":upper16: not allowed in this instruction"));
e2b0ab59 12982 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVT;
b6895b4f
PB
12983 }
12984
fdfde340
JM
12985 Rd = inst.operands[0].reg;
12986 reject_bad_reg (Rd);
12987
12988 inst.instruction |= Rd << 8;
e2b0ab59 12989 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
b6895b4f 12990 {
e2b0ab59 12991 imm = inst.relocs[0].exp.X_add_number;
b6895b4f
PB
12992 inst.instruction |= (imm & 0xf000) << 4;
12993 inst.instruction |= (imm & 0x0800) << 15;
12994 inst.instruction |= (imm & 0x0700) << 4;
12995 inst.instruction |= (imm & 0x00ff);
12996 }
c19d1205 12997}
b99bd4ef 12998
c19d1205
ZW
12999static void
13000do_t_mvn_tst (void)
13001{
fdfde340 13002 unsigned Rn, Rm;
c921be7d 13003
fdfde340
JM
13004 Rn = inst.operands[0].reg;
13005 Rm = inst.operands[1].reg;
13006
13007 if (inst.instruction == T_MNEM_cmp
13008 || inst.instruction == T_MNEM_cmn)
13009 constraint (Rn == REG_PC, BAD_PC);
13010 else
13011 reject_bad_reg (Rn);
13012 reject_bad_reg (Rm);
13013
c19d1205
ZW
13014 if (unified_syntax)
13015 {
13016 int r0off = (inst.instruction == T_MNEM_mvn
13017 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
3d388997
PB
13018 bfd_boolean narrow;
13019
13020 if (inst.size_req == 4
13021 || inst.instruction > 0xffff
13022 || inst.operands[1].shifted
fdfde340 13023 || Rn > 7 || Rm > 7)
3d388997 13024 narrow = FALSE;
fe8b4cc3
KT
13025 else if (inst.instruction == T_MNEM_cmn
13026 || inst.instruction == T_MNEM_tst)
3d388997
PB
13027 narrow = TRUE;
13028 else if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 13029 narrow = !in_pred_block ();
3d388997 13030 else
5ee91343 13031 narrow = in_pred_block ();
3d388997 13032
c19d1205 13033 if (!inst.operands[1].isreg)
b99bd4ef 13034 {
c19d1205
ZW
13035 /* For an immediate, we always generate a 32-bit opcode;
13036 section relaxation will shrink it later if possible. */
13037 if (inst.instruction < 0xffff)
13038 inst.instruction = THUMB_OP32 (inst.instruction);
13039 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
fdfde340 13040 inst.instruction |= Rn << r0off;
e2b0ab59 13041 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 13042 }
c19d1205 13043 else
b99bd4ef 13044 {
c19d1205 13045 /* See if we can do this with a 16-bit instruction. */
3d388997 13046 if (narrow)
b99bd4ef 13047 {
c19d1205 13048 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM
13049 inst.instruction |= Rn;
13050 inst.instruction |= Rm << 3;
b99bd4ef 13051 }
c19d1205 13052 else
b99bd4ef 13053 {
c19d1205
ZW
13054 constraint (inst.operands[1].shifted
13055 && inst.operands[1].immisreg,
13056 _("shift must be constant"));
13057 if (inst.instruction < 0xffff)
13058 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 13059 inst.instruction |= Rn << r0off;
c19d1205 13060 encode_thumb32_shifted_operand (1);
b99bd4ef 13061 }
b99bd4ef
NC
13062 }
13063 }
13064 else
13065 {
c19d1205
ZW
13066 constraint (inst.instruction > 0xffff
13067 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
13068 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
13069 _("unshifted register required"));
fdfde340 13070 constraint (Rn > 7 || Rm > 7,
c19d1205 13071 BAD_HIREG);
b99bd4ef 13072
c19d1205 13073 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM
13074 inst.instruction |= Rn;
13075 inst.instruction |= Rm << 3;
b99bd4ef 13076 }
b99bd4ef
NC
13077}
13078
b05fe5cf 13079static void
c19d1205 13080do_t_mrs (void)
b05fe5cf 13081{
fdfde340 13082 unsigned Rd;
037e8744
JB
13083
13084 if (do_vfp_nsyn_mrs () == SUCCESS)
13085 return;
13086
90ec0d68
MGD
13087 Rd = inst.operands[0].reg;
13088 reject_bad_reg (Rd);
13089 inst.instruction |= Rd << 8;
13090
13091 if (inst.operands[1].isreg)
62b3e311 13092 {
90ec0d68
MGD
13093 unsigned br = inst.operands[1].reg;
13094 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
13095 as_bad (_("bad register for mrs"));
13096
13097 inst.instruction |= br & (0xf << 16);
13098 inst.instruction |= (br & 0x300) >> 4;
13099 inst.instruction |= (br & SPSR_BIT) >> 2;
62b3e311
PB
13100 }
13101 else
13102 {
90ec0d68 13103 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
5f4273c7 13104
d2cd1205 13105 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
1a43faaf
NC
13106 {
13107 /* PR gas/12698: The constraint is only applied for m_profile.
13108 If the user has specified -march=all, we want to ignore it as
13109 we are building for any CPU type, including non-m variants. */
823d2571
TG
13110 bfd_boolean m_profile =
13111 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
1a43faaf
NC
13112 constraint ((flags != 0) && m_profile, _("selected processor does "
13113 "not support requested special purpose register"));
13114 }
90ec0d68 13115 else
d2cd1205
JB
13116 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13117 devices). */
13118 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
13119 _("'APSR', 'CPSR' or 'SPSR' expected"));
fdfde340 13120
90ec0d68
MGD
13121 inst.instruction |= (flags & SPSR_BIT) >> 2;
13122 inst.instruction |= inst.operands[1].imm & 0xff;
13123 inst.instruction |= 0xf0000;
13124 }
c19d1205 13125}
b05fe5cf 13126
c19d1205
ZW
13127static void
13128do_t_msr (void)
13129{
62b3e311 13130 int flags;
fdfde340 13131 unsigned Rn;
62b3e311 13132
037e8744
JB
13133 if (do_vfp_nsyn_msr () == SUCCESS)
13134 return;
13135
c19d1205
ZW
13136 constraint (!inst.operands[1].isreg,
13137 _("Thumb encoding does not support an immediate here"));
90ec0d68
MGD
13138
13139 if (inst.operands[0].isreg)
13140 flags = (int)(inst.operands[0].reg);
13141 else
13142 flags = inst.operands[0].imm;
13143
d2cd1205 13144 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
62b3e311 13145 {
d2cd1205
JB
13146 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
13147
1a43faaf 13148 /* PR gas/12698: The constraint is only applied for m_profile.
477330fc
RM
13149 If the user has specified -march=all, we want to ignore it as
13150 we are building for any CPU type, including non-m variants. */
823d2571
TG
13151 bfd_boolean m_profile =
13152 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
1a43faaf 13153 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
477330fc
RM
13154 && (bits & ~(PSR_s | PSR_f)) != 0)
13155 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
13156 && bits != PSR_f)) && m_profile,
13157 _("selected processor does not support requested special "
13158 "purpose register"));
62b3e311
PB
13159 }
13160 else
d2cd1205
JB
13161 constraint ((flags & 0xff) != 0, _("selected processor does not support "
13162 "requested special purpose register"));
c921be7d 13163
fdfde340
JM
13164 Rn = inst.operands[1].reg;
13165 reject_bad_reg (Rn);
13166
62b3e311 13167 inst.instruction |= (flags & SPSR_BIT) >> 2;
90ec0d68
MGD
13168 inst.instruction |= (flags & 0xf0000) >> 8;
13169 inst.instruction |= (flags & 0x300) >> 4;
62b3e311 13170 inst.instruction |= (flags & 0xff);
fdfde340 13171 inst.instruction |= Rn << 16;
c19d1205 13172}
b05fe5cf 13173
c19d1205
ZW
13174static void
13175do_t_mul (void)
13176{
17828f45 13177 bfd_boolean narrow;
fdfde340 13178 unsigned Rd, Rn, Rm;
17828f45 13179
c19d1205
ZW
13180 if (!inst.operands[2].present)
13181 inst.operands[2].reg = inst.operands[0].reg;
b05fe5cf 13182
fdfde340
JM
13183 Rd = inst.operands[0].reg;
13184 Rn = inst.operands[1].reg;
13185 Rm = inst.operands[2].reg;
13186
17828f45 13187 if (unified_syntax)
b05fe5cf 13188 {
17828f45 13189 if (inst.size_req == 4
fdfde340
JM
13190 || (Rd != Rn
13191 && Rd != Rm)
13192 || Rn > 7
13193 || Rm > 7)
17828f45
JM
13194 narrow = FALSE;
13195 else if (inst.instruction == T_MNEM_muls)
5ee91343 13196 narrow = !in_pred_block ();
17828f45 13197 else
5ee91343 13198 narrow = in_pred_block ();
b05fe5cf 13199 }
c19d1205 13200 else
b05fe5cf 13201 {
17828f45 13202 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
fdfde340 13203 constraint (Rn > 7 || Rm > 7,
c19d1205 13204 BAD_HIREG);
17828f45
JM
13205 narrow = TRUE;
13206 }
b05fe5cf 13207
17828f45
JM
13208 if (narrow)
13209 {
13210 /* 16-bit MULS/Conditional MUL. */
c19d1205 13211 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340 13212 inst.instruction |= Rd;
b05fe5cf 13213
fdfde340
JM
13214 if (Rd == Rn)
13215 inst.instruction |= Rm << 3;
13216 else if (Rd == Rm)
13217 inst.instruction |= Rn << 3;
c19d1205
ZW
13218 else
13219 constraint (1, _("dest must overlap one source register"));
13220 }
17828f45
JM
13221 else
13222 {
e07e6e58
NC
13223 constraint (inst.instruction != T_MNEM_mul,
13224 _("Thumb-2 MUL must not set flags"));
17828f45
JM
13225 /* 32-bit MUL. */
13226 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM
13227 inst.instruction |= Rd << 8;
13228 inst.instruction |= Rn << 16;
13229 inst.instruction |= Rm << 0;
13230
13231 reject_bad_reg (Rd);
13232 reject_bad_reg (Rn);
13233 reject_bad_reg (Rm);
17828f45 13234 }
c19d1205 13235}
b05fe5cf 13236
c19d1205
ZW
13237static void
13238do_t_mull (void)
13239{
fdfde340 13240 unsigned RdLo, RdHi, Rn, Rm;
b05fe5cf 13241
fdfde340
JM
13242 RdLo = inst.operands[0].reg;
13243 RdHi = inst.operands[1].reg;
13244 Rn = inst.operands[2].reg;
13245 Rm = inst.operands[3].reg;
13246
13247 reject_bad_reg (RdLo);
13248 reject_bad_reg (RdHi);
13249 reject_bad_reg (Rn);
13250 reject_bad_reg (Rm);
13251
13252 inst.instruction |= RdLo << 12;
13253 inst.instruction |= RdHi << 8;
13254 inst.instruction |= Rn << 16;
13255 inst.instruction |= Rm;
13256
13257 if (RdLo == RdHi)
c19d1205
ZW
13258 as_tsktsk (_("rdhi and rdlo must be different"));
13259}
b05fe5cf 13260
c19d1205
ZW
13261static void
13262do_t_nop (void)
13263{
5ee91343 13264 set_pred_insn_type (NEUTRAL_IT_INSN);
e07e6e58 13265
c19d1205
ZW
13266 if (unified_syntax)
13267 {
13268 if (inst.size_req == 4 || inst.operands[0].imm > 15)
b05fe5cf 13269 {
c19d1205
ZW
13270 inst.instruction = THUMB_OP32 (inst.instruction);
13271 inst.instruction |= inst.operands[0].imm;
13272 }
13273 else
13274 {
bc2d1808
NC
13275 /* PR9722: Check for Thumb2 availability before
13276 generating a thumb2 nop instruction. */
afa62d5e 13277 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
bc2d1808
NC
13278 {
13279 inst.instruction = THUMB_OP16 (inst.instruction);
13280 inst.instruction |= inst.operands[0].imm << 4;
13281 }
13282 else
13283 inst.instruction = 0x46c0;
c19d1205
ZW
13284 }
13285 }
13286 else
13287 {
13288 constraint (inst.operands[0].present,
13289 _("Thumb does not support NOP with hints"));
13290 inst.instruction = 0x46c0;
13291 }
13292}
b05fe5cf 13293
c19d1205
ZW
13294static void
13295do_t_neg (void)
13296{
13297 if (unified_syntax)
13298 {
3d388997
PB
13299 bfd_boolean narrow;
13300
13301 if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 13302 narrow = !in_pred_block ();
3d388997 13303 else
5ee91343 13304 narrow = in_pred_block ();
3d388997
PB
13305 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13306 narrow = FALSE;
13307 if (inst.size_req == 4)
13308 narrow = FALSE;
13309
13310 if (!narrow)
c19d1205
ZW
13311 {
13312 inst.instruction = THUMB_OP32 (inst.instruction);
13313 inst.instruction |= inst.operands[0].reg << 8;
13314 inst.instruction |= inst.operands[1].reg << 16;
b05fe5cf
ZW
13315 }
13316 else
13317 {
c19d1205
ZW
13318 inst.instruction = THUMB_OP16 (inst.instruction);
13319 inst.instruction |= inst.operands[0].reg;
13320 inst.instruction |= inst.operands[1].reg << 3;
b05fe5cf
ZW
13321 }
13322 }
13323 else
13324 {
c19d1205
ZW
13325 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
13326 BAD_HIREG);
13327 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
13328
13329 inst.instruction = THUMB_OP16 (inst.instruction);
13330 inst.instruction |= inst.operands[0].reg;
13331 inst.instruction |= inst.operands[1].reg << 3;
13332 }
13333}
13334
1c444d06
JM
13335static void
13336do_t_orn (void)
13337{
13338 unsigned Rd, Rn;
13339
13340 Rd = inst.operands[0].reg;
13341 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
13342
fdfde340
JM
13343 reject_bad_reg (Rd);
13344 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13345 reject_bad_reg (Rn);
13346
1c444d06
JM
13347 inst.instruction |= Rd << 8;
13348 inst.instruction |= Rn << 16;
13349
13350 if (!inst.operands[2].isreg)
13351 {
13352 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
e2b0ab59 13353 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
1c444d06
JM
13354 }
13355 else
13356 {
13357 unsigned Rm;
13358
13359 Rm = inst.operands[2].reg;
fdfde340 13360 reject_bad_reg (Rm);
1c444d06
JM
13361
13362 constraint (inst.operands[2].shifted
13363 && inst.operands[2].immisreg,
13364 _("shift must be constant"));
13365 encode_thumb32_shifted_operand (2);
13366 }
13367}
13368
c19d1205
ZW
13369static void
13370do_t_pkhbt (void)
13371{
fdfde340
JM
13372 unsigned Rd, Rn, Rm;
13373
13374 Rd = inst.operands[0].reg;
13375 Rn = inst.operands[1].reg;
13376 Rm = inst.operands[2].reg;
13377
13378 reject_bad_reg (Rd);
13379 reject_bad_reg (Rn);
13380 reject_bad_reg (Rm);
13381
13382 inst.instruction |= Rd << 8;
13383 inst.instruction |= Rn << 16;
13384 inst.instruction |= Rm;
c19d1205
ZW
13385 if (inst.operands[3].present)
13386 {
e2b0ab59
AV
13387 unsigned int val = inst.relocs[0].exp.X_add_number;
13388 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205
ZW
13389 _("expression too complex"));
13390 inst.instruction |= (val & 0x1c) << 10;
13391 inst.instruction |= (val & 0x03) << 6;
b05fe5cf 13392 }
c19d1205 13393}
b05fe5cf 13394
c19d1205
ZW
13395static void
13396do_t_pkhtb (void)
13397{
13398 if (!inst.operands[3].present)
1ef52f49
NC
13399 {
13400 unsigned Rtmp;
13401
13402 inst.instruction &= ~0x00000020;
13403
13404 /* PR 10168. Swap the Rm and Rn registers. */
13405 Rtmp = inst.operands[1].reg;
13406 inst.operands[1].reg = inst.operands[2].reg;
13407 inst.operands[2].reg = Rtmp;
13408 }
c19d1205 13409 do_t_pkhbt ();
b05fe5cf
ZW
13410}
13411
c19d1205
ZW
13412static void
13413do_t_pld (void)
13414{
fdfde340
JM
13415 if (inst.operands[0].immisreg)
13416 reject_bad_reg (inst.operands[0].imm);
13417
c19d1205
ZW
13418 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
13419}
b05fe5cf 13420
c19d1205
ZW
13421static void
13422do_t_push_pop (void)
b99bd4ef 13423{
e9f89963 13424 unsigned mask;
5f4273c7 13425
c19d1205
ZW
13426 constraint (inst.operands[0].writeback,
13427 _("push/pop do not support {reglist}^"));
e2b0ab59 13428 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
c19d1205 13429 _("expression too complex"));
b99bd4ef 13430
e9f89963 13431 mask = inst.operands[0].imm;
d3bfe16e 13432 if (inst.size_req != 4 && (mask & ~0xff) == 0)
3c707909 13433 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
d3bfe16e 13434 else if (inst.size_req != 4
c6025a80 13435 && (mask & ~0xff) == (1U << (inst.instruction == T_MNEM_push
d3bfe16e 13436 ? REG_LR : REG_PC)))
b99bd4ef 13437 {
c19d1205
ZW
13438 inst.instruction = THUMB_OP16 (inst.instruction);
13439 inst.instruction |= THUMB_PP_PC_LR;
3c707909 13440 inst.instruction |= mask & 0xff;
c19d1205
ZW
13441 }
13442 else if (unified_syntax)
13443 {
3c707909 13444 inst.instruction = THUMB_OP32 (inst.instruction);
4b5a202f
AV
13445 encode_thumb2_multi (TRUE /* do_io */, 13, mask, TRUE);
13446 }
13447 else
13448 {
13449 inst.error = _("invalid register list to push/pop instruction");
13450 return;
c19d1205 13451 }
4b5a202f
AV
13452}
13453
13454static void
13455do_t_clrm (void)
13456{
13457 if (unified_syntax)
13458 encode_thumb2_multi (FALSE /* do_io */, -1, inst.operands[0].imm, FALSE);
c19d1205
ZW
13459 else
13460 {
13461 inst.error = _("invalid register list to push/pop instruction");
13462 return;
13463 }
c19d1205 13464}
b99bd4ef 13465
efd6b359
AV
13466static void
13467do_t_vscclrm (void)
13468{
13469 if (inst.operands[0].issingle)
13470 {
13471 inst.instruction |= (inst.operands[0].reg & 0x1) << 22;
13472 inst.instruction |= (inst.operands[0].reg & 0x1e) << 11;
13473 inst.instruction |= inst.operands[0].imm;
13474 }
13475 else
13476 {
13477 inst.instruction |= (inst.operands[0].reg & 0x10) << 18;
13478 inst.instruction |= (inst.operands[0].reg & 0xf) << 12;
13479 inst.instruction |= 1 << 8;
13480 inst.instruction |= inst.operands[0].imm << 1;
13481 }
13482}
13483
c19d1205
ZW
13484static void
13485do_t_rbit (void)
13486{
fdfde340
JM
13487 unsigned Rd, Rm;
13488
13489 Rd = inst.operands[0].reg;
13490 Rm = inst.operands[1].reg;
13491
13492 reject_bad_reg (Rd);
13493 reject_bad_reg (Rm);
13494
13495 inst.instruction |= Rd << 8;
13496 inst.instruction |= Rm << 16;
13497 inst.instruction |= Rm;
c19d1205 13498}
b99bd4ef 13499
c19d1205
ZW
13500static void
13501do_t_rev (void)
13502{
fdfde340
JM
13503 unsigned Rd, Rm;
13504
13505 Rd = inst.operands[0].reg;
13506 Rm = inst.operands[1].reg;
13507
13508 reject_bad_reg (Rd);
13509 reject_bad_reg (Rm);
13510
13511 if (Rd <= 7 && Rm <= 7
c19d1205
ZW
13512 && inst.size_req != 4)
13513 {
13514 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM
13515 inst.instruction |= Rd;
13516 inst.instruction |= Rm << 3;
c19d1205
ZW
13517 }
13518 else if (unified_syntax)
13519 {
13520 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM
13521 inst.instruction |= Rd << 8;
13522 inst.instruction |= Rm << 16;
13523 inst.instruction |= Rm;
c19d1205
ZW
13524 }
13525 else
13526 inst.error = BAD_HIREG;
13527}
b99bd4ef 13528
1c444d06
JM
13529static void
13530do_t_rrx (void)
13531{
13532 unsigned Rd, Rm;
13533
13534 Rd = inst.operands[0].reg;
13535 Rm = inst.operands[1].reg;
13536
fdfde340
JM
13537 reject_bad_reg (Rd);
13538 reject_bad_reg (Rm);
c921be7d 13539
1c444d06
JM
13540 inst.instruction |= Rd << 8;
13541 inst.instruction |= Rm;
13542}
13543
c19d1205
ZW
13544static void
13545do_t_rsb (void)
13546{
fdfde340 13547 unsigned Rd, Rs;
b99bd4ef 13548
c19d1205
ZW
13549 Rd = inst.operands[0].reg;
13550 Rs = (inst.operands[1].present
13551 ? inst.operands[1].reg /* Rd, Rs, foo */
13552 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
b99bd4ef 13553
fdfde340
JM
13554 reject_bad_reg (Rd);
13555 reject_bad_reg (Rs);
13556 if (inst.operands[2].isreg)
13557 reject_bad_reg (inst.operands[2].reg);
13558
c19d1205
ZW
13559 inst.instruction |= Rd << 8;
13560 inst.instruction |= Rs << 16;
13561 if (!inst.operands[2].isreg)
13562 {
026d3abb
PB
13563 bfd_boolean narrow;
13564
13565 if ((inst.instruction & 0x00100000) != 0)
5ee91343 13566 narrow = !in_pred_block ();
026d3abb 13567 else
5ee91343 13568 narrow = in_pred_block ();
026d3abb
PB
13569
13570 if (Rd > 7 || Rs > 7)
13571 narrow = FALSE;
13572
13573 if (inst.size_req == 4 || !unified_syntax)
13574 narrow = FALSE;
13575
e2b0ab59
AV
13576 if (inst.relocs[0].exp.X_op != O_constant
13577 || inst.relocs[0].exp.X_add_number != 0)
026d3abb
PB
13578 narrow = FALSE;
13579
13580 /* Turn rsb #0 into 16-bit neg. We should probably do this via
477330fc 13581 relaxation, but it doesn't seem worth the hassle. */
026d3abb
PB
13582 if (narrow)
13583 {
e2b0ab59 13584 inst.relocs[0].type = BFD_RELOC_UNUSED;
026d3abb
PB
13585 inst.instruction = THUMB_OP16 (T_MNEM_negs);
13586 inst.instruction |= Rs << 3;
13587 inst.instruction |= Rd;
13588 }
13589 else
13590 {
13591 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
e2b0ab59 13592 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
026d3abb 13593 }
c19d1205
ZW
13594 }
13595 else
13596 encode_thumb32_shifted_operand (2);
13597}
b99bd4ef 13598
c19d1205
ZW
13599static void
13600do_t_setend (void)
13601{
12e37cbc
MGD
13602 if (warn_on_deprecated
13603 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
5c3696f8 13604 as_tsktsk (_("setend use is deprecated for ARMv8"));
12e37cbc 13605
5ee91343 13606 set_pred_insn_type (OUTSIDE_PRED_INSN);
c19d1205
ZW
13607 if (inst.operands[0].imm)
13608 inst.instruction |= 0x8;
13609}
b99bd4ef 13610
c19d1205
ZW
13611static void
13612do_t_shift (void)
13613{
13614 if (!inst.operands[1].present)
13615 inst.operands[1].reg = inst.operands[0].reg;
13616
13617 if (unified_syntax)
13618 {
3d388997
PB
13619 bfd_boolean narrow;
13620 int shift_kind;
13621
13622 switch (inst.instruction)
13623 {
13624 case T_MNEM_asr:
13625 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
13626 case T_MNEM_lsl:
13627 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
13628 case T_MNEM_lsr:
13629 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
13630 case T_MNEM_ror:
13631 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
13632 default: abort ();
13633 }
13634
13635 if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 13636 narrow = !in_pred_block ();
3d388997 13637 else
5ee91343 13638 narrow = in_pred_block ();
3d388997
PB
13639 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13640 narrow = FALSE;
13641 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
13642 narrow = FALSE;
13643 if (inst.operands[2].isreg
13644 && (inst.operands[1].reg != inst.operands[0].reg
13645 || inst.operands[2].reg > 7))
13646 narrow = FALSE;
13647 if (inst.size_req == 4)
13648 narrow = FALSE;
13649
fdfde340
JM
13650 reject_bad_reg (inst.operands[0].reg);
13651 reject_bad_reg (inst.operands[1].reg);
c921be7d 13652
3d388997 13653 if (!narrow)
c19d1205
ZW
13654 {
13655 if (inst.operands[2].isreg)
b99bd4ef 13656 {
fdfde340 13657 reject_bad_reg (inst.operands[2].reg);
c19d1205
ZW
13658 inst.instruction = THUMB_OP32 (inst.instruction);
13659 inst.instruction |= inst.operands[0].reg << 8;
13660 inst.instruction |= inst.operands[1].reg << 16;
13661 inst.instruction |= inst.operands[2].reg;
94342ec3
NC
13662
13663 /* PR 12854: Error on extraneous shifts. */
13664 constraint (inst.operands[2].shifted,
13665 _("extraneous shift as part of operand to shift insn"));
c19d1205
ZW
13666 }
13667 else
13668 {
13669 inst.operands[1].shifted = 1;
3d388997 13670 inst.operands[1].shift_kind = shift_kind;
c19d1205
ZW
13671 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
13672 ? T_MNEM_movs : T_MNEM_mov);
13673 inst.instruction |= inst.operands[0].reg << 8;
13674 encode_thumb32_shifted_operand (1);
13675 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
e2b0ab59 13676 inst.relocs[0].type = BFD_RELOC_UNUSED;
b99bd4ef
NC
13677 }
13678 }
13679 else
13680 {
c19d1205 13681 if (inst.operands[2].isreg)
b99bd4ef 13682 {
3d388997 13683 switch (shift_kind)
b99bd4ef 13684 {
3d388997
PB
13685 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
13686 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
13687 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
13688 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
c19d1205 13689 default: abort ();
b99bd4ef 13690 }
5f4273c7 13691
c19d1205
ZW
13692 inst.instruction |= inst.operands[0].reg;
13693 inst.instruction |= inst.operands[2].reg << 3;
af199b06
NC
13694
13695 /* PR 12854: Error on extraneous shifts. */
13696 constraint (inst.operands[2].shifted,
13697 _("extraneous shift as part of operand to shift insn"));
b99bd4ef
NC
13698 }
13699 else
13700 {
3d388997 13701 switch (shift_kind)
b99bd4ef 13702 {
3d388997
PB
13703 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
13704 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
13705 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
c19d1205 13706 default: abort ();
b99bd4ef 13707 }
e2b0ab59 13708 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
c19d1205
ZW
13709 inst.instruction |= inst.operands[0].reg;
13710 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC
13711 }
13712 }
c19d1205
ZW
13713 }
13714 else
13715 {
13716 constraint (inst.operands[0].reg > 7
13717 || inst.operands[1].reg > 7, BAD_HIREG);
13718 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
b99bd4ef 13719
c19d1205
ZW
13720 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
13721 {
13722 constraint (inst.operands[2].reg > 7, BAD_HIREG);
13723 constraint (inst.operands[0].reg != inst.operands[1].reg,
13724 _("source1 and dest must be same register"));
b99bd4ef 13725
c19d1205
ZW
13726 switch (inst.instruction)
13727 {
13728 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
13729 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
13730 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
13731 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
13732 default: abort ();
13733 }
5f4273c7 13734
c19d1205
ZW
13735 inst.instruction |= inst.operands[0].reg;
13736 inst.instruction |= inst.operands[2].reg << 3;
af199b06
NC
13737
13738 /* PR 12854: Error on extraneous shifts. */
13739 constraint (inst.operands[2].shifted,
13740 _("extraneous shift as part of operand to shift insn"));
c19d1205
ZW
13741 }
13742 else
b99bd4ef 13743 {
c19d1205
ZW
13744 switch (inst.instruction)
13745 {
13746 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
13747 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
13748 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
13749 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
13750 default: abort ();
13751 }
e2b0ab59 13752 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
c19d1205
ZW
13753 inst.instruction |= inst.operands[0].reg;
13754 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC
13755 }
13756 }
b99bd4ef
NC
13757}
13758
13759static void
c19d1205 13760do_t_simd (void)
b99bd4ef 13761{
fdfde340
JM
13762 unsigned Rd, Rn, Rm;
13763
13764 Rd = inst.operands[0].reg;
13765 Rn = inst.operands[1].reg;
13766 Rm = inst.operands[2].reg;
13767
13768 reject_bad_reg (Rd);
13769 reject_bad_reg (Rn);
13770 reject_bad_reg (Rm);
13771
13772 inst.instruction |= Rd << 8;
13773 inst.instruction |= Rn << 16;
13774 inst.instruction |= Rm;
c19d1205 13775}
b99bd4ef 13776
03ee1b7f
NC
13777static void
13778do_t_simd2 (void)
13779{
13780 unsigned Rd, Rn, Rm;
13781
13782 Rd = inst.operands[0].reg;
13783 Rm = inst.operands[1].reg;
13784 Rn = inst.operands[2].reg;
13785
13786 reject_bad_reg (Rd);
13787 reject_bad_reg (Rn);
13788 reject_bad_reg (Rm);
13789
13790 inst.instruction |= Rd << 8;
13791 inst.instruction |= Rn << 16;
13792 inst.instruction |= Rm;
13793}
13794
c19d1205 13795static void
3eb17e6b 13796do_t_smc (void)
c19d1205 13797{
e2b0ab59 13798 unsigned int value = inst.relocs[0].exp.X_add_number;
f4c65163
MGD
13799 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
13800 _("SMC is not permitted on this architecture"));
e2b0ab59 13801 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205 13802 _("expression too complex"));
e2b0ab59 13803 inst.relocs[0].type = BFD_RELOC_UNUSED;
c19d1205
ZW
13804 inst.instruction |= (value & 0xf000) >> 12;
13805 inst.instruction |= (value & 0x0ff0);
13806 inst.instruction |= (value & 0x000f) << 16;
24382199 13807 /* PR gas/15623: SMC instructions must be last in an IT block. */
5ee91343 13808 set_pred_insn_type_last ();
c19d1205 13809}
b99bd4ef 13810
90ec0d68
MGD
13811static void
13812do_t_hvc (void)
13813{
e2b0ab59 13814 unsigned int value = inst.relocs[0].exp.X_add_number;
90ec0d68 13815
e2b0ab59 13816 inst.relocs[0].type = BFD_RELOC_UNUSED;
90ec0d68
MGD
13817 inst.instruction |= (value & 0x0fff);
13818 inst.instruction |= (value & 0xf000) << 4;
13819}
13820
c19d1205 13821static void
3a21c15a 13822do_t_ssat_usat (int bias)
c19d1205 13823{
fdfde340
JM
13824 unsigned Rd, Rn;
13825
13826 Rd = inst.operands[0].reg;
13827 Rn = inst.operands[2].reg;
13828
13829 reject_bad_reg (Rd);
13830 reject_bad_reg (Rn);
13831
13832 inst.instruction |= Rd << 8;
3a21c15a 13833 inst.instruction |= inst.operands[1].imm - bias;
fdfde340 13834 inst.instruction |= Rn << 16;
b99bd4ef 13835
c19d1205 13836 if (inst.operands[3].present)
b99bd4ef 13837 {
e2b0ab59 13838 offsetT shift_amount = inst.relocs[0].exp.X_add_number;
3a21c15a 13839
e2b0ab59 13840 inst.relocs[0].type = BFD_RELOC_UNUSED;
3a21c15a 13841
e2b0ab59 13842 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205 13843 _("expression too complex"));
b99bd4ef 13844
3a21c15a 13845 if (shift_amount != 0)
6189168b 13846 {
3a21c15a
NC
13847 constraint (shift_amount > 31,
13848 _("shift expression is too large"));
13849
c19d1205 13850 if (inst.operands[3].shift_kind == SHIFT_ASR)
3a21c15a
NC
13851 inst.instruction |= 0x00200000; /* sh bit. */
13852
13853 inst.instruction |= (shift_amount & 0x1c) << 10;
13854 inst.instruction |= (shift_amount & 0x03) << 6;
6189168b
NC
13855 }
13856 }
b99bd4ef 13857}
c921be7d 13858
3a21c15a
NC
13859static void
13860do_t_ssat (void)
13861{
13862 do_t_ssat_usat (1);
13863}
b99bd4ef 13864
0dd132b6 13865static void
c19d1205 13866do_t_ssat16 (void)
0dd132b6 13867{
fdfde340
JM
13868 unsigned Rd, Rn;
13869
13870 Rd = inst.operands[0].reg;
13871 Rn = inst.operands[2].reg;
13872
13873 reject_bad_reg (Rd);
13874 reject_bad_reg (Rn);
13875
13876 inst.instruction |= Rd << 8;
c19d1205 13877 inst.instruction |= inst.operands[1].imm - 1;
fdfde340 13878 inst.instruction |= Rn << 16;
c19d1205 13879}
0dd132b6 13880
c19d1205
ZW
13881static void
13882do_t_strex (void)
13883{
13884 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
13885 || inst.operands[2].postind || inst.operands[2].writeback
13886 || inst.operands[2].immisreg || inst.operands[2].shifted
13887 || inst.operands[2].negative,
01cfc07f 13888 BAD_ADDR_MODE);
0dd132b6 13889
5be8be5d
DG
13890 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
13891
c19d1205
ZW
13892 inst.instruction |= inst.operands[0].reg << 8;
13893 inst.instruction |= inst.operands[1].reg << 12;
13894 inst.instruction |= inst.operands[2].reg << 16;
e2b0ab59 13895 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
0dd132b6
NC
13896}
13897
b99bd4ef 13898static void
c19d1205 13899do_t_strexd (void)
b99bd4ef 13900{
c19d1205
ZW
13901 if (!inst.operands[2].present)
13902 inst.operands[2].reg = inst.operands[1].reg + 1;
b99bd4ef 13903
c19d1205
ZW
13904 constraint (inst.operands[0].reg == inst.operands[1].reg
13905 || inst.operands[0].reg == inst.operands[2].reg
f8a8e9d6 13906 || inst.operands[0].reg == inst.operands[3].reg,
c19d1205 13907 BAD_OVERLAP);
b99bd4ef 13908
c19d1205
ZW
13909 inst.instruction |= inst.operands[0].reg;
13910 inst.instruction |= inst.operands[1].reg << 12;
13911 inst.instruction |= inst.operands[2].reg << 8;
13912 inst.instruction |= inst.operands[3].reg << 16;
b99bd4ef
NC
13913}
13914
13915static void
c19d1205 13916do_t_sxtah (void)
b99bd4ef 13917{
fdfde340
JM
13918 unsigned Rd, Rn, Rm;
13919
13920 Rd = inst.operands[0].reg;
13921 Rn = inst.operands[1].reg;
13922 Rm = inst.operands[2].reg;
13923
13924 reject_bad_reg (Rd);
13925 reject_bad_reg (Rn);
13926 reject_bad_reg (Rm);
13927
13928 inst.instruction |= Rd << 8;
13929 inst.instruction |= Rn << 16;
13930 inst.instruction |= Rm;
c19d1205
ZW
13931 inst.instruction |= inst.operands[3].imm << 4;
13932}
b99bd4ef 13933
c19d1205
ZW
13934static void
13935do_t_sxth (void)
13936{
fdfde340
JM
13937 unsigned Rd, Rm;
13938
13939 Rd = inst.operands[0].reg;
13940 Rm = inst.operands[1].reg;
13941
13942 reject_bad_reg (Rd);
13943 reject_bad_reg (Rm);
c921be7d
NC
13944
13945 if (inst.instruction <= 0xffff
13946 && inst.size_req != 4
fdfde340 13947 && Rd <= 7 && Rm <= 7
c19d1205 13948 && (!inst.operands[2].present || inst.operands[2].imm == 0))
b99bd4ef 13949 {
c19d1205 13950 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM
13951 inst.instruction |= Rd;
13952 inst.instruction |= Rm << 3;
b99bd4ef 13953 }
c19d1205 13954 else if (unified_syntax)
b99bd4ef 13955 {
c19d1205
ZW
13956 if (inst.instruction <= 0xffff)
13957 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM
13958 inst.instruction |= Rd << 8;
13959 inst.instruction |= Rm;
c19d1205 13960 inst.instruction |= inst.operands[2].imm << 4;
b99bd4ef 13961 }
c19d1205 13962 else
b99bd4ef 13963 {
c19d1205
ZW
13964 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
13965 _("Thumb encoding does not support rotation"));
13966 constraint (1, BAD_HIREG);
b99bd4ef 13967 }
c19d1205 13968}
b99bd4ef 13969
c19d1205
ZW
13970static void
13971do_t_swi (void)
13972{
e2b0ab59 13973 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
c19d1205 13974}
b99bd4ef 13975
92e90b6e
PB
13976static void
13977do_t_tb (void)
13978{
fdfde340 13979 unsigned Rn, Rm;
92e90b6e
PB
13980 int half;
13981
13982 half = (inst.instruction & 0x10) != 0;
5ee91343 13983 set_pred_insn_type_last ();
dfa9f0d5
PB
13984 constraint (inst.operands[0].immisreg,
13985 _("instruction requires register index"));
fdfde340
JM
13986
13987 Rn = inst.operands[0].reg;
13988 Rm = inst.operands[0].imm;
c921be7d 13989
5c8ed6a4
JW
13990 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
13991 constraint (Rn == REG_SP, BAD_SP);
fdfde340
JM
13992 reject_bad_reg (Rm);
13993
92e90b6e
PB
13994 constraint (!half && inst.operands[0].shifted,
13995 _("instruction does not allow shifted index"));
fdfde340 13996 inst.instruction |= (Rn << 16) | Rm;
92e90b6e
PB
13997}
13998
74db7efb
NC
13999static void
14000do_t_udf (void)
14001{
14002 if (!inst.operands[0].present)
14003 inst.operands[0].imm = 0;
14004
14005 if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)
14006 {
14007 constraint (inst.size_req == 2,
14008 _("immediate value out of range"));
14009 inst.instruction = THUMB_OP32 (inst.instruction);
14010 inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;
14011 inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;
14012 }
14013 else
14014 {
14015 inst.instruction = THUMB_OP16 (inst.instruction);
14016 inst.instruction |= inst.operands[0].imm;
14017 }
14018
5ee91343 14019 set_pred_insn_type (NEUTRAL_IT_INSN);
74db7efb
NC
14020}
14021
14022
c19d1205
ZW
14023static void
14024do_t_usat (void)
14025{
3a21c15a 14026 do_t_ssat_usat (0);
b99bd4ef
NC
14027}
14028
14029static void
c19d1205 14030do_t_usat16 (void)
b99bd4ef 14031{
fdfde340
JM
14032 unsigned Rd, Rn;
14033
14034 Rd = inst.operands[0].reg;
14035 Rn = inst.operands[2].reg;
14036
14037 reject_bad_reg (Rd);
14038 reject_bad_reg (Rn);
14039
14040 inst.instruction |= Rd << 8;
c19d1205 14041 inst.instruction |= inst.operands[1].imm;
fdfde340 14042 inst.instruction |= Rn << 16;
b99bd4ef 14043}
c19d1205 14044
e12437dc
AV
14045/* Checking the range of the branch offset (VAL) with NBITS bits
14046 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14047static int
14048v8_1_branch_value_check (int val, int nbits, int is_signed)
14049{
14050 gas_assert (nbits > 0 && nbits <= 32);
14051 if (is_signed)
14052 {
14053 int cmp = (1 << (nbits - 1));
14054 if ((val < -cmp) || (val >= cmp) || (val & 0x01))
14055 return FAIL;
14056 }
14057 else
14058 {
14059 if ((val <= 0) || (val >= (1 << nbits)) || (val & 0x1))
14060 return FAIL;
14061 }
14062 return SUCCESS;
14063}
14064
4389b29a
AV
14065/* For branches in Armv8.1-M Mainline. */
14066static void
14067do_t_branch_future (void)
14068{
14069 unsigned long insn = inst.instruction;
14070
14071 inst.instruction = THUMB_OP32 (inst.instruction);
14072 if (inst.operands[0].hasreloc == 0)
14073 {
14074 if (v8_1_branch_value_check (inst.operands[0].imm, 5, FALSE) == FAIL)
14075 as_bad (BAD_BRANCH_OFF);
14076
14077 inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23;
14078 }
14079 else
14080 {
14081 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH5;
14082 inst.relocs[0].pc_rel = 1;
14083 }
14084
14085 switch (insn)
14086 {
14087 case T_MNEM_bf:
14088 if (inst.operands[1].hasreloc == 0)
14089 {
14090 int val = inst.operands[1].imm;
14091 if (v8_1_branch_value_check (inst.operands[1].imm, 17, TRUE) == FAIL)
14092 as_bad (BAD_BRANCH_OFF);
14093
14094 int immA = (val & 0x0001f000) >> 12;
14095 int immB = (val & 0x00000ffc) >> 2;
14096 int immC = (val & 0x00000002) >> 1;
14097 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14098 }
14099 else
14100 {
14101 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF17;
14102 inst.relocs[1].pc_rel = 1;
14103 }
14104 break;
14105
65d1bc05
AV
14106 case T_MNEM_bfl:
14107 if (inst.operands[1].hasreloc == 0)
14108 {
14109 int val = inst.operands[1].imm;
14110 if (v8_1_branch_value_check (inst.operands[1].imm, 19, TRUE) == FAIL)
14111 as_bad (BAD_BRANCH_OFF);
14112
14113 int immA = (val & 0x0007f000) >> 12;
14114 int immB = (val & 0x00000ffc) >> 2;
14115 int immC = (val & 0x00000002) >> 1;
14116 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14117 }
14118 else
14119 {
14120 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF19;
14121 inst.relocs[1].pc_rel = 1;
14122 }
14123 break;
14124
f6b2b12d
AV
14125 case T_MNEM_bfcsel:
14126 /* Operand 1. */
14127 if (inst.operands[1].hasreloc == 0)
14128 {
14129 int val = inst.operands[1].imm;
14130 int immA = (val & 0x00001000) >> 12;
14131 int immB = (val & 0x00000ffc) >> 2;
14132 int immC = (val & 0x00000002) >> 1;
14133 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14134 }
14135 else
14136 {
14137 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF13;
14138 inst.relocs[1].pc_rel = 1;
14139 }
14140
14141 /* Operand 2. */
14142 if (inst.operands[2].hasreloc == 0)
14143 {
14144 constraint ((inst.operands[0].hasreloc != 0), BAD_ARGS);
14145 int val2 = inst.operands[2].imm;
14146 int val0 = inst.operands[0].imm & 0x1f;
14147 int diff = val2 - val0;
14148 if (diff == 4)
14149 inst.instruction |= 1 << 17; /* T bit. */
14150 else if (diff != 2)
14151 as_bad (_("out of range label-relative fixup value"));
14152 }
14153 else
14154 {
14155 constraint ((inst.operands[0].hasreloc == 0), BAD_ARGS);
14156 inst.relocs[2].type = BFD_RELOC_THUMB_PCREL_BFCSEL;
14157 inst.relocs[2].pc_rel = 1;
14158 }
14159
14160 /* Operand 3. */
14161 constraint (inst.cond != COND_ALWAYS, BAD_COND);
14162 inst.instruction |= (inst.operands[3].imm & 0xf) << 18;
14163 break;
14164
f1c7f421
AV
14165 case T_MNEM_bfx:
14166 case T_MNEM_bflx:
14167 inst.instruction |= inst.operands[1].reg << 16;
14168 break;
14169
4389b29a
AV
14170 default: abort ();
14171 }
14172}
14173
60f993ce
AV
14174/* Helper function for do_t_loloop to handle relocations. */
14175static void
14176v8_1_loop_reloc (int is_le)
14177{
14178 if (inst.relocs[0].exp.X_op == O_constant)
14179 {
14180 int value = inst.relocs[0].exp.X_add_number;
14181 value = (is_le) ? -value : value;
14182
14183 if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
14184 as_bad (BAD_BRANCH_OFF);
14185
14186 int imml, immh;
14187
14188 immh = (value & 0x00000ffc) >> 2;
14189 imml = (value & 0x00000002) >> 1;
14190
14191 inst.instruction |= (imml << 11) | (immh << 1);
14192 }
14193 else
14194 {
14195 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_LOOP12;
14196 inst.relocs[0].pc_rel = 1;
14197 }
14198}
14199
23d00a41
SD
14200/* For shifts in MVE. */
14201static void
14202do_mve_scalar_shift (void)
14203{
14204 if (!inst.operands[2].present)
14205 {
14206 inst.operands[2] = inst.operands[1];
14207 inst.operands[1].reg = 0xf;
14208 }
14209
14210 inst.instruction |= inst.operands[0].reg << 16;
14211 inst.instruction |= inst.operands[1].reg << 8;
14212
14213 if (inst.operands[2].isreg)
14214 {
14215 /* Assuming Rm is already checked not to be 11x1. */
14216 constraint (inst.operands[2].reg == inst.operands[0].reg, BAD_OVERLAP);
14217 constraint (inst.operands[2].reg == inst.operands[1].reg, BAD_OVERLAP);
14218 inst.instruction |= inst.operands[2].reg << 12;
14219 }
14220 else
14221 {
14222 /* Assuming imm is already checked as [1,32]. */
14223 unsigned int value = inst.operands[2].imm;
14224 inst.instruction |= (value & 0x1c) << 10;
14225 inst.instruction |= (value & 0x03) << 6;
14226 /* Change last 4 bits from 0xd to 0xf. */
14227 inst.instruction |= 0x2;
14228 }
14229}
14230
a302e574
AV
14231/* MVE instruction encoder helpers. */
14232#define M_MNEM_vabav 0xee800f01
14233#define M_MNEM_vmladav 0xeef00e00
14234#define M_MNEM_vmladava 0xeef00e20
14235#define M_MNEM_vmladavx 0xeef01e00
14236#define M_MNEM_vmladavax 0xeef01e20
14237#define M_MNEM_vmlsdav 0xeef00e01
14238#define M_MNEM_vmlsdava 0xeef00e21
14239#define M_MNEM_vmlsdavx 0xeef01e01
14240#define M_MNEM_vmlsdavax 0xeef01e21
886e1c73
AV
14241#define M_MNEM_vmullt 0xee011e00
14242#define M_MNEM_vmullb 0xee010e00
35c228db
AV
14243#define M_MNEM_vst20 0xfc801e00
14244#define M_MNEM_vst21 0xfc801e20
14245#define M_MNEM_vst40 0xfc801e01
14246#define M_MNEM_vst41 0xfc801e21
14247#define M_MNEM_vst42 0xfc801e41
14248#define M_MNEM_vst43 0xfc801e61
14249#define M_MNEM_vld20 0xfc901e00
14250#define M_MNEM_vld21 0xfc901e20
14251#define M_MNEM_vld40 0xfc901e01
14252#define M_MNEM_vld41 0xfc901e21
14253#define M_MNEM_vld42 0xfc901e41
14254#define M_MNEM_vld43 0xfc901e61
f5f10c66
AV
14255#define M_MNEM_vstrb 0xec000e00
14256#define M_MNEM_vstrh 0xec000e10
14257#define M_MNEM_vstrw 0xec000e40
14258#define M_MNEM_vstrd 0xec000e50
14259#define M_MNEM_vldrb 0xec100e00
14260#define M_MNEM_vldrh 0xec100e10
14261#define M_MNEM_vldrw 0xec100e40
14262#define M_MNEM_vldrd 0xec100e50
57785aa2
AV
14263#define M_MNEM_vmovlt 0xeea01f40
14264#define M_MNEM_vmovlb 0xeea00f40
14265#define M_MNEM_vmovnt 0xfe311e81
14266#define M_MNEM_vmovnb 0xfe310e81
c2dafc2a
AV
14267#define M_MNEM_vadc 0xee300f00
14268#define M_MNEM_vadci 0xee301f00
14269#define M_MNEM_vbrsr 0xfe011e60
26c1e780
AV
14270#define M_MNEM_vaddlv 0xee890f00
14271#define M_MNEM_vaddlva 0xee890f20
14272#define M_MNEM_vaddv 0xeef10f00
14273#define M_MNEM_vaddva 0xeef10f20
b409bdb6
AV
14274#define M_MNEM_vddup 0xee011f6e
14275#define M_MNEM_vdwdup 0xee011f60
14276#define M_MNEM_vidup 0xee010f6e
14277#define M_MNEM_viwdup 0xee010f60
13ccd4c0
AV
14278#define M_MNEM_vmaxv 0xeee20f00
14279#define M_MNEM_vmaxav 0xeee00f00
14280#define M_MNEM_vminv 0xeee20f80
14281#define M_MNEM_vminav 0xeee00f80
93925576
AV
14282#define M_MNEM_vmlaldav 0xee800e00
14283#define M_MNEM_vmlaldava 0xee800e20
14284#define M_MNEM_vmlaldavx 0xee801e00
14285#define M_MNEM_vmlaldavax 0xee801e20
14286#define M_MNEM_vmlsldav 0xee800e01
14287#define M_MNEM_vmlsldava 0xee800e21
14288#define M_MNEM_vmlsldavx 0xee801e01
14289#define M_MNEM_vmlsldavax 0xee801e21
14290#define M_MNEM_vrmlaldavhx 0xee801f00
14291#define M_MNEM_vrmlaldavhax 0xee801f20
14292#define M_MNEM_vrmlsldavh 0xfe800e01
14293#define M_MNEM_vrmlsldavha 0xfe800e21
14294#define M_MNEM_vrmlsldavhx 0xfe801e01
14295#define M_MNEM_vrmlsldavhax 0xfe801e21
1be7aba3
AV
14296#define M_MNEM_vqmovnt 0xee331e01
14297#define M_MNEM_vqmovnb 0xee330e01
14298#define M_MNEM_vqmovunt 0xee311e81
14299#define M_MNEM_vqmovunb 0xee310e81
4aa88b50
AV
14300#define M_MNEM_vshrnt 0xee801fc1
14301#define M_MNEM_vshrnb 0xee800fc1
14302#define M_MNEM_vrshrnt 0xfe801fc1
14303#define M_MNEM_vqshrnt 0xee801f40
14304#define M_MNEM_vqshrnb 0xee800f40
14305#define M_MNEM_vqshrunt 0xee801fc0
14306#define M_MNEM_vqshrunb 0xee800fc0
14307#define M_MNEM_vrshrnb 0xfe800fc1
14308#define M_MNEM_vqrshrnt 0xee801f41
14309#define M_MNEM_vqrshrnb 0xee800f41
14310#define M_MNEM_vqrshrunt 0xfe801fc0
14311#define M_MNEM_vqrshrunb 0xfe800fc0
a302e574 14312
5287ad62 14313/* Neon instruction encoder helpers. */
5f4273c7 14314
5287ad62 14315/* Encodings for the different types for various Neon opcodes. */
b99bd4ef 14316
5287ad62
JB
14317/* An "invalid" code for the following tables. */
14318#define N_INV -1u
14319
14320struct neon_tab_entry
b99bd4ef 14321{
5287ad62
JB
14322 unsigned integer;
14323 unsigned float_or_poly;
14324 unsigned scalar_or_imm;
14325};
5f4273c7 14326
5287ad62
JB
14327/* Map overloaded Neon opcodes to their respective encodings. */
14328#define NEON_ENC_TAB \
14329 X(vabd, 0x0000700, 0x1200d00, N_INV), \
5ee91343 14330 X(vabdl, 0x0800700, N_INV, N_INV), \
5287ad62
JB
14331 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14332 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14333 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14334 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14335 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14336 X(vadd, 0x0000800, 0x0000d00, N_INV), \
5ee91343 14337 X(vaddl, 0x0800000, N_INV, N_INV), \
5287ad62 14338 X(vsub, 0x1000800, 0x0200d00, N_INV), \
5ee91343 14339 X(vsubl, 0x0800200, N_INV, N_INV), \
5287ad62
JB
14340 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14341 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14342 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14343 /* Register variants of the following two instructions are encoded as
e07e6e58 14344 vcge / vcgt with the operands reversed. */ \
92559b5b
PB
14345 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14346 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
62f3b8c8
PB
14347 X(vfma, N_INV, 0x0000c10, N_INV), \
14348 X(vfms, N_INV, 0x0200c10, N_INV), \
5287ad62
JB
14349 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14350 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14351 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14352 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14353 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14354 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14355 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14356 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14357 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14358 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14359 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
d6b4b13e
MW
14360 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14361 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
5287ad62
JB
14362 X(vshl, 0x0000400, N_INV, 0x0800510), \
14363 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14364 X(vand, 0x0000110, N_INV, 0x0800030), \
14365 X(vbic, 0x0100110, N_INV, 0x0800030), \
14366 X(veor, 0x1000110, N_INV, N_INV), \
14367 X(vorn, 0x0300110, N_INV, 0x0800010), \
14368 X(vorr, 0x0200110, N_INV, 0x0800010), \
14369 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14370 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14371 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14372 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14373 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14374 X(vst1, 0x0000000, 0x0800000, N_INV), \
14375 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14376 X(vst2, 0x0000100, 0x0800100, N_INV), \
14377 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14378 X(vst3, 0x0000200, 0x0800200, N_INV), \
14379 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14380 X(vst4, 0x0000300, 0x0800300, N_INV), \
14381 X(vmovn, 0x1b20200, N_INV, N_INV), \
14382 X(vtrn, 0x1b20080, N_INV, N_INV), \
14383 X(vqmovn, 0x1b20200, N_INV, N_INV), \
037e8744
JB
14384 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14385 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
e6655fda
PB
14386 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14387 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
62f3b8c8
PB
14388 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14389 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
037e8744
JB
14390 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14391 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14392 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
33399f07
MGD
14393 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14394 X(vseleq, 0xe000a00, N_INV, N_INV), \
14395 X(vselvs, 0xe100a00, N_INV, N_INV), \
14396 X(vselge, 0xe200a00, N_INV, N_INV), \
73924fbc
MGD
14397 X(vselgt, 0xe300a00, N_INV, N_INV), \
14398 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
7e8e6784 14399 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
30bdf752
MGD
14400 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14401 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
91ff7894 14402 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
48adcd8e 14403 X(aes, 0x3b00300, N_INV, N_INV), \
3c9017d2
MGD
14404 X(sha3op, 0x2000c00, N_INV, N_INV), \
14405 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14406 X(sha2op, 0x3ba0380, N_INV, N_INV)
5287ad62
JB
14407
14408enum neon_opc
14409{
14410#define X(OPC,I,F,S) N_MNEM_##OPC
14411NEON_ENC_TAB
14412#undef X
14413};
b99bd4ef 14414
5287ad62
JB
14415static const struct neon_tab_entry neon_enc_tab[] =
14416{
14417#define X(OPC,I,F,S) { (I), (F), (S) }
14418NEON_ENC_TAB
14419#undef X
14420};
b99bd4ef 14421
88714cb8
DG
14422/* Do not use these macros; instead, use NEON_ENCODE defined below. */
14423#define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14424#define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14425#define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14426#define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14427#define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14428#define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14429#define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14430#define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14431#define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14432#define NEON_ENC_SINGLE_(X) \
037e8744 14433 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
88714cb8 14434#define NEON_ENC_DOUBLE_(X) \
037e8744 14435 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
33399f07
MGD
14436#define NEON_ENC_FPV8_(X) \
14437 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
5287ad62 14438
88714cb8
DG
14439#define NEON_ENCODE(type, inst) \
14440 do \
14441 { \
14442 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14443 inst.is_neon = 1; \
14444 } \
14445 while (0)
14446
14447#define check_neon_suffixes \
14448 do \
14449 { \
14450 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14451 { \
14452 as_bad (_("invalid neon suffix for non neon instruction")); \
14453 return; \
14454 } \
14455 } \
14456 while (0)
14457
037e8744
JB
14458/* Define shapes for instruction operands. The following mnemonic characters
14459 are used in this table:
5287ad62 14460
037e8744 14461 F - VFP S<n> register
5287ad62
JB
14462 D - Neon D<n> register
14463 Q - Neon Q<n> register
14464 I - Immediate
14465 S - Scalar
14466 R - ARM register
14467 L - D<n> register list
5f4273c7 14468
037e8744
JB
14469 This table is used to generate various data:
14470 - enumerations of the form NS_DDR to be used as arguments to
14471 neon_select_shape.
14472 - a table classifying shapes into single, double, quad, mixed.
5f4273c7 14473 - a table used to drive neon_select_shape. */
b99bd4ef 14474
037e8744 14475#define NEON_SHAPE_DEF \
93925576 14476 X(4, (R, R, Q, Q), QUAD), \
b409bdb6 14477 X(4, (Q, R, R, I), QUAD), \
57785aa2
AV
14478 X(4, (R, R, S, S), QUAD), \
14479 X(4, (S, S, R, R), QUAD), \
b409bdb6 14480 X(3, (Q, R, I), QUAD), \
1b883319
AV
14481 X(3, (I, Q, Q), QUAD), \
14482 X(3, (I, Q, R), QUAD), \
a302e574 14483 X(3, (R, Q, Q), QUAD), \
037e8744
JB
14484 X(3, (D, D, D), DOUBLE), \
14485 X(3, (Q, Q, Q), QUAD), \
14486 X(3, (D, D, I), DOUBLE), \
14487 X(3, (Q, Q, I), QUAD), \
14488 X(3, (D, D, S), DOUBLE), \
14489 X(3, (Q, Q, S), QUAD), \
5ee91343 14490 X(3, (Q, Q, R), QUAD), \
26c1e780
AV
14491 X(3, (R, R, Q), QUAD), \
14492 X(2, (R, Q), QUAD), \
037e8744
JB
14493 X(2, (D, D), DOUBLE), \
14494 X(2, (Q, Q), QUAD), \
14495 X(2, (D, S), DOUBLE), \
14496 X(2, (Q, S), QUAD), \
14497 X(2, (D, R), DOUBLE), \
14498 X(2, (Q, R), QUAD), \
14499 X(2, (D, I), DOUBLE), \
14500 X(2, (Q, I), QUAD), \
14501 X(3, (D, L, D), DOUBLE), \
14502 X(2, (D, Q), MIXED), \
14503 X(2, (Q, D), MIXED), \
14504 X(3, (D, Q, I), MIXED), \
14505 X(3, (Q, D, I), MIXED), \
14506 X(3, (Q, D, D), MIXED), \
14507 X(3, (D, Q, Q), MIXED), \
14508 X(3, (Q, Q, D), MIXED), \
14509 X(3, (Q, D, S), MIXED), \
14510 X(3, (D, Q, S), MIXED), \
14511 X(4, (D, D, D, I), DOUBLE), \
14512 X(4, (Q, Q, Q, I), QUAD), \
c28eeff2
SN
14513 X(4, (D, D, S, I), DOUBLE), \
14514 X(4, (Q, Q, S, I), QUAD), \
037e8744
JB
14515 X(2, (F, F), SINGLE), \
14516 X(3, (F, F, F), SINGLE), \
14517 X(2, (F, I), SINGLE), \
14518 X(2, (F, D), MIXED), \
14519 X(2, (D, F), MIXED), \
14520 X(3, (F, F, I), MIXED), \
14521 X(4, (R, R, F, F), SINGLE), \
14522 X(4, (F, F, R, R), SINGLE), \
14523 X(3, (D, R, R), DOUBLE), \
14524 X(3, (R, R, D), DOUBLE), \
14525 X(2, (S, R), SINGLE), \
14526 X(2, (R, S), SINGLE), \
14527 X(2, (F, R), SINGLE), \
d54af2d0 14528 X(2, (R, F), SINGLE), \
1f6234a3
AV
14529/* Used for MVE tail predicated loop instructions. */\
14530 X(2, (R, R), QUAD), \
d54af2d0
RL
14531/* Half float shape supported so far. */\
14532 X (2, (H, D), MIXED), \
14533 X (2, (D, H), MIXED), \
14534 X (2, (H, F), MIXED), \
14535 X (2, (F, H), MIXED), \
14536 X (2, (H, H), HALF), \
14537 X (2, (H, R), HALF), \
14538 X (2, (R, H), HALF), \
14539 X (2, (H, I), HALF), \
14540 X (3, (H, H, H), HALF), \
14541 X (3, (H, F, I), MIXED), \
dec41383
JW
14542 X (3, (F, H, I), MIXED), \
14543 X (3, (D, H, H), MIXED), \
14544 X (3, (D, H, S), MIXED)
037e8744
JB
14545
14546#define S2(A,B) NS_##A##B
14547#define S3(A,B,C) NS_##A##B##C
14548#define S4(A,B,C,D) NS_##A##B##C##D
14549
14550#define X(N, L, C) S##N L
14551
5287ad62
JB
14552enum neon_shape
14553{
037e8744
JB
14554 NEON_SHAPE_DEF,
14555 NS_NULL
5287ad62 14556};
b99bd4ef 14557
037e8744
JB
14558#undef X
14559#undef S2
14560#undef S3
14561#undef S4
14562
14563enum neon_shape_class
14564{
d54af2d0 14565 SC_HALF,
037e8744
JB
14566 SC_SINGLE,
14567 SC_DOUBLE,
14568 SC_QUAD,
14569 SC_MIXED
14570};
14571
14572#define X(N, L, C) SC_##C
14573
14574static enum neon_shape_class neon_shape_class[] =
14575{
14576 NEON_SHAPE_DEF
14577};
14578
14579#undef X
14580
14581enum neon_shape_el
14582{
d54af2d0 14583 SE_H,
037e8744
JB
14584 SE_F,
14585 SE_D,
14586 SE_Q,
14587 SE_I,
14588 SE_S,
14589 SE_R,
14590 SE_L
14591};
14592
14593/* Register widths of above. */
14594static unsigned neon_shape_el_size[] =
14595{
d54af2d0 14596 16,
037e8744
JB
14597 32,
14598 64,
14599 128,
14600 0,
14601 32,
14602 32,
14603 0
14604};
14605
14606struct neon_shape_info
14607{
14608 unsigned els;
14609 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
14610};
14611
14612#define S2(A,B) { SE_##A, SE_##B }
14613#define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14614#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14615
14616#define X(N, L, C) { N, S##N L }
14617
14618static struct neon_shape_info neon_shape_tab[] =
14619{
14620 NEON_SHAPE_DEF
14621};
14622
14623#undef X
14624#undef S2
14625#undef S3
14626#undef S4
14627
5287ad62
JB
14628/* Bit masks used in type checking given instructions.
14629 'N_EQK' means the type must be the same as (or based on in some way) the key
14630 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14631 set, various other bits can be set as well in order to modify the meaning of
14632 the type constraint. */
14633
14634enum neon_type_mask
14635{
8e79c3df
CM
14636 N_S8 = 0x0000001,
14637 N_S16 = 0x0000002,
14638 N_S32 = 0x0000004,
14639 N_S64 = 0x0000008,
14640 N_U8 = 0x0000010,
14641 N_U16 = 0x0000020,
14642 N_U32 = 0x0000040,
14643 N_U64 = 0x0000080,
14644 N_I8 = 0x0000100,
14645 N_I16 = 0x0000200,
14646 N_I32 = 0x0000400,
14647 N_I64 = 0x0000800,
14648 N_8 = 0x0001000,
14649 N_16 = 0x0002000,
14650 N_32 = 0x0004000,
14651 N_64 = 0x0008000,
14652 N_P8 = 0x0010000,
14653 N_P16 = 0x0020000,
14654 N_F16 = 0x0040000,
14655 N_F32 = 0x0080000,
14656 N_F64 = 0x0100000,
4f51b4bd 14657 N_P64 = 0x0200000,
c921be7d
NC
14658 N_KEY = 0x1000000, /* Key element (main type specifier). */
14659 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
8e79c3df 14660 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
91ff7894 14661 N_UNT = 0x8000000, /* Must be explicitly untyped. */
c921be7d
NC
14662 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
14663 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
14664 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14665 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14666 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14667 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
14668 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
5287ad62 14669 N_UTYP = 0,
4f51b4bd 14670 N_MAX_NONSPECIAL = N_P64
5287ad62
JB
14671};
14672
dcbf9037
JB
14673#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14674
5287ad62
JB
14675#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14676#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14677#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
cc933301
JW
14678#define N_S_32 (N_S8 | N_S16 | N_S32)
14679#define N_F_16_32 (N_F16 | N_F32)
14680#define N_SUF_32 (N_SU_32 | N_F_16_32)
5287ad62 14681#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
cc933301 14682#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
d54af2d0 14683#define N_F_ALL (N_F16 | N_F32 | N_F64)
5ee91343
AV
14684#define N_I_MVE (N_I8 | N_I16 | N_I32)
14685#define N_F_MVE (N_F16 | N_F32)
14686#define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
5287ad62
JB
14687
14688/* Pass this as the first type argument to neon_check_type to ignore types
14689 altogether. */
14690#define N_IGNORE_TYPE (N_KEY | N_EQK)
14691
037e8744
JB
14692/* Select a "shape" for the current instruction (describing register types or
14693 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14694 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14695 function of operand parsing, so this function doesn't need to be called.
14696 Shapes should be listed in order of decreasing length. */
5287ad62
JB
14697
14698static enum neon_shape
037e8744 14699neon_select_shape (enum neon_shape shape, ...)
5287ad62 14700{
037e8744
JB
14701 va_list ap;
14702 enum neon_shape first_shape = shape;
5287ad62
JB
14703
14704 /* Fix missing optional operands. FIXME: we don't know at this point how
14705 many arguments we should have, so this makes the assumption that we have
14706 > 1. This is true of all current Neon opcodes, I think, but may not be
14707 true in the future. */
14708 if (!inst.operands[1].present)
14709 inst.operands[1] = inst.operands[0];
14710
037e8744 14711 va_start (ap, shape);
5f4273c7 14712
21d799b5 14713 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
037e8744
JB
14714 {
14715 unsigned j;
14716 int matches = 1;
14717
14718 for (j = 0; j < neon_shape_tab[shape].els; j++)
477330fc
RM
14719 {
14720 if (!inst.operands[j].present)
14721 {
14722 matches = 0;
14723 break;
14724 }
14725
14726 switch (neon_shape_tab[shape].el[j])
14727 {
d54af2d0
RL
14728 /* If a .f16, .16, .u16, .s16 type specifier is given over
14729 a VFP single precision register operand, it's essentially
14730 means only half of the register is used.
14731
14732 If the type specifier is given after the mnemonics, the
14733 information is stored in inst.vectype. If the type specifier
14734 is given after register operand, the information is stored
14735 in inst.operands[].vectype.
14736
14737 When there is only one type specifier, and all the register
14738 operands are the same type of hardware register, the type
14739 specifier applies to all register operands.
14740
14741 If no type specifier is given, the shape is inferred from
14742 operand information.
14743
14744 for example:
14745 vadd.f16 s0, s1, s2: NS_HHH
14746 vabs.f16 s0, s1: NS_HH
14747 vmov.f16 s0, r1: NS_HR
14748 vmov.f16 r0, s1: NS_RH
14749 vcvt.f16 r0, s1: NS_RH
14750 vcvt.f16.s32 s2, s2, #29: NS_HFI
14751 vcvt.f16.s32 s2, s2: NS_HF
14752 */
14753 case SE_H:
14754 if (!(inst.operands[j].isreg
14755 && inst.operands[j].isvec
14756 && inst.operands[j].issingle
14757 && !inst.operands[j].isquad
14758 && ((inst.vectype.elems == 1
14759 && inst.vectype.el[0].size == 16)
14760 || (inst.vectype.elems > 1
14761 && inst.vectype.el[j].size == 16)
14762 || (inst.vectype.elems == 0
14763 && inst.operands[j].vectype.type != NT_invtype
14764 && inst.operands[j].vectype.size == 16))))
14765 matches = 0;
14766 break;
14767
477330fc
RM
14768 case SE_F:
14769 if (!(inst.operands[j].isreg
14770 && inst.operands[j].isvec
14771 && inst.operands[j].issingle
d54af2d0
RL
14772 && !inst.operands[j].isquad
14773 && ((inst.vectype.elems == 1 && inst.vectype.el[0].size == 32)
14774 || (inst.vectype.elems > 1 && inst.vectype.el[j].size == 32)
14775 || (inst.vectype.elems == 0
14776 && (inst.operands[j].vectype.size == 32
14777 || inst.operands[j].vectype.type == NT_invtype)))))
477330fc
RM
14778 matches = 0;
14779 break;
14780
14781 case SE_D:
14782 if (!(inst.operands[j].isreg
14783 && inst.operands[j].isvec
14784 && !inst.operands[j].isquad
14785 && !inst.operands[j].issingle))
14786 matches = 0;
14787 break;
14788
14789 case SE_R:
14790 if (!(inst.operands[j].isreg
14791 && !inst.operands[j].isvec))
14792 matches = 0;
14793 break;
14794
14795 case SE_Q:
14796 if (!(inst.operands[j].isreg
14797 && inst.operands[j].isvec
14798 && inst.operands[j].isquad
14799 && !inst.operands[j].issingle))
14800 matches = 0;
14801 break;
14802
14803 case SE_I:
14804 if (!(!inst.operands[j].isreg
14805 && !inst.operands[j].isscalar))
14806 matches = 0;
14807 break;
14808
14809 case SE_S:
14810 if (!(!inst.operands[j].isreg
14811 && inst.operands[j].isscalar))
14812 matches = 0;
14813 break;
14814
14815 case SE_L:
14816 break;
14817 }
3fde54a2
JZ
14818 if (!matches)
14819 break;
477330fc 14820 }
ad6cec43
MGD
14821 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
14822 /* We've matched all the entries in the shape table, and we don't
14823 have any left over operands which have not been matched. */
477330fc 14824 break;
037e8744 14825 }
5f4273c7 14826
037e8744 14827 va_end (ap);
5287ad62 14828
037e8744
JB
14829 if (shape == NS_NULL && first_shape != NS_NULL)
14830 first_error (_("invalid instruction shape"));
5287ad62 14831
037e8744
JB
14832 return shape;
14833}
5287ad62 14834
037e8744
JB
14835/* True if SHAPE is predominantly a quadword operation (most of the time, this
14836 means the Q bit should be set). */
14837
14838static int
14839neon_quad (enum neon_shape shape)
14840{
14841 return neon_shape_class[shape] == SC_QUAD;
5287ad62 14842}
037e8744 14843
5287ad62
JB
14844static void
14845neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
477330fc 14846 unsigned *g_size)
5287ad62
JB
14847{
14848 /* Allow modification to be made to types which are constrained to be
14849 based on the key element, based on bits set alongside N_EQK. */
14850 if ((typebits & N_EQK) != 0)
14851 {
14852 if ((typebits & N_HLF) != 0)
14853 *g_size /= 2;
14854 else if ((typebits & N_DBL) != 0)
14855 *g_size *= 2;
14856 if ((typebits & N_SGN) != 0)
14857 *g_type = NT_signed;
14858 else if ((typebits & N_UNS) != 0)
477330fc 14859 *g_type = NT_unsigned;
5287ad62 14860 else if ((typebits & N_INT) != 0)
477330fc 14861 *g_type = NT_integer;
5287ad62 14862 else if ((typebits & N_FLT) != 0)
477330fc 14863 *g_type = NT_float;
dcbf9037 14864 else if ((typebits & N_SIZ) != 0)
477330fc 14865 *g_type = NT_untyped;
5287ad62
JB
14866 }
14867}
5f4273c7 14868
5287ad62
JB
14869/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14870 operand type, i.e. the single type specified in a Neon instruction when it
14871 is the only one given. */
14872
14873static struct neon_type_el
14874neon_type_promote (struct neon_type_el *key, unsigned thisarg)
14875{
14876 struct neon_type_el dest = *key;
5f4273c7 14877
9c2799c2 14878 gas_assert ((thisarg & N_EQK) != 0);
5f4273c7 14879
5287ad62
JB
14880 neon_modify_type_size (thisarg, &dest.type, &dest.size);
14881
14882 return dest;
14883}
14884
14885/* Convert Neon type and size into compact bitmask representation. */
14886
14887static enum neon_type_mask
14888type_chk_of_el_type (enum neon_el_type type, unsigned size)
14889{
14890 switch (type)
14891 {
14892 case NT_untyped:
14893 switch (size)
477330fc
RM
14894 {
14895 case 8: return N_8;
14896 case 16: return N_16;
14897 case 32: return N_32;
14898 case 64: return N_64;
14899 default: ;
14900 }
5287ad62
JB
14901 break;
14902
14903 case NT_integer:
14904 switch (size)
477330fc
RM
14905 {
14906 case 8: return N_I8;
14907 case 16: return N_I16;
14908 case 32: return N_I32;
14909 case 64: return N_I64;
14910 default: ;
14911 }
5287ad62
JB
14912 break;
14913
14914 case NT_float:
037e8744 14915 switch (size)
477330fc 14916 {
8e79c3df 14917 case 16: return N_F16;
477330fc
RM
14918 case 32: return N_F32;
14919 case 64: return N_F64;
14920 default: ;
14921 }
5287ad62
JB
14922 break;
14923
14924 case NT_poly:
14925 switch (size)
477330fc
RM
14926 {
14927 case 8: return N_P8;
14928 case 16: return N_P16;
4f51b4bd 14929 case 64: return N_P64;
477330fc
RM
14930 default: ;
14931 }
5287ad62
JB
14932 break;
14933
14934 case NT_signed:
14935 switch (size)
477330fc
RM
14936 {
14937 case 8: return N_S8;
14938 case 16: return N_S16;
14939 case 32: return N_S32;
14940 case 64: return N_S64;
14941 default: ;
14942 }
5287ad62
JB
14943 break;
14944
14945 case NT_unsigned:
14946 switch (size)
477330fc
RM
14947 {
14948 case 8: return N_U8;
14949 case 16: return N_U16;
14950 case 32: return N_U32;
14951 case 64: return N_U64;
14952 default: ;
14953 }
5287ad62
JB
14954 break;
14955
14956 default: ;
14957 }
5f4273c7 14958
5287ad62
JB
14959 return N_UTYP;
14960}
14961
14962/* Convert compact Neon bitmask type representation to a type and size. Only
14963 handles the case where a single bit is set in the mask. */
14964
dcbf9037 14965static int
5287ad62 14966el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
477330fc 14967 enum neon_type_mask mask)
5287ad62 14968{
dcbf9037
JB
14969 if ((mask & N_EQK) != 0)
14970 return FAIL;
14971
5287ad62
JB
14972 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
14973 *size = 8;
c70a8987 14974 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
5287ad62 14975 *size = 16;
dcbf9037 14976 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
5287ad62 14977 *size = 32;
4f51b4bd 14978 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
5287ad62 14979 *size = 64;
dcbf9037
JB
14980 else
14981 return FAIL;
14982
5287ad62
JB
14983 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
14984 *type = NT_signed;
dcbf9037 14985 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
5287ad62 14986 *type = NT_unsigned;
dcbf9037 14987 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
5287ad62 14988 *type = NT_integer;
dcbf9037 14989 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
5287ad62 14990 *type = NT_untyped;
4f51b4bd 14991 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
5287ad62 14992 *type = NT_poly;
d54af2d0 14993 else if ((mask & (N_F_ALL)) != 0)
5287ad62 14994 *type = NT_float;
dcbf9037
JB
14995 else
14996 return FAIL;
5f4273c7 14997
dcbf9037 14998 return SUCCESS;
5287ad62
JB
14999}
15000
15001/* Modify a bitmask of allowed types. This is only needed for type
15002 relaxation. */
15003
15004static unsigned
15005modify_types_allowed (unsigned allowed, unsigned mods)
15006{
15007 unsigned size;
15008 enum neon_el_type type;
15009 unsigned destmask;
15010 int i;
5f4273c7 15011
5287ad62 15012 destmask = 0;
5f4273c7 15013
5287ad62
JB
15014 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
15015 {
21d799b5 15016 if (el_type_of_type_chk (&type, &size,
477330fc
RM
15017 (enum neon_type_mask) (allowed & i)) == SUCCESS)
15018 {
15019 neon_modify_type_size (mods, &type, &size);
15020 destmask |= type_chk_of_el_type (type, size);
15021 }
5287ad62 15022 }
5f4273c7 15023
5287ad62
JB
15024 return destmask;
15025}
15026
15027/* Check type and return type classification.
15028 The manual states (paraphrase): If one datatype is given, it indicates the
15029 type given in:
15030 - the second operand, if there is one
15031 - the operand, if there is no second operand
15032 - the result, if there are no operands.
15033 This isn't quite good enough though, so we use a concept of a "key" datatype
15034 which is set on a per-instruction basis, which is the one which matters when
15035 only one data type is written.
15036 Note: this function has side-effects (e.g. filling in missing operands). All
037e8744 15037 Neon instructions should call it before performing bit encoding. */
5287ad62
JB
15038
15039static struct neon_type_el
15040neon_check_type (unsigned els, enum neon_shape ns, ...)
15041{
15042 va_list ap;
15043 unsigned i, pass, key_el = 0;
15044 unsigned types[NEON_MAX_TYPE_ELS];
15045 enum neon_el_type k_type = NT_invtype;
15046 unsigned k_size = -1u;
15047 struct neon_type_el badtype = {NT_invtype, -1};
15048 unsigned key_allowed = 0;
15049
15050 /* Optional registers in Neon instructions are always (not) in operand 1.
15051 Fill in the missing operand here, if it was omitted. */
15052 if (els > 1 && !inst.operands[1].present)
15053 inst.operands[1] = inst.operands[0];
15054
15055 /* Suck up all the varargs. */
15056 va_start (ap, ns);
15057 for (i = 0; i < els; i++)
15058 {
15059 unsigned thisarg = va_arg (ap, unsigned);
15060 if (thisarg == N_IGNORE_TYPE)
477330fc
RM
15061 {
15062 va_end (ap);
15063 return badtype;
15064 }
5287ad62
JB
15065 types[i] = thisarg;
15066 if ((thisarg & N_KEY) != 0)
477330fc 15067 key_el = i;
5287ad62
JB
15068 }
15069 va_end (ap);
15070
dcbf9037
JB
15071 if (inst.vectype.elems > 0)
15072 for (i = 0; i < els; i++)
15073 if (inst.operands[i].vectype.type != NT_invtype)
477330fc
RM
15074 {
15075 first_error (_("types specified in both the mnemonic and operands"));
15076 return badtype;
15077 }
dcbf9037 15078
5287ad62
JB
15079 /* Duplicate inst.vectype elements here as necessary.
15080 FIXME: No idea if this is exactly the same as the ARM assembler,
15081 particularly when an insn takes one register and one non-register
15082 operand. */
15083 if (inst.vectype.elems == 1 && els > 1)
15084 {
15085 unsigned j;
15086 inst.vectype.elems = els;
15087 inst.vectype.el[key_el] = inst.vectype.el[0];
15088 for (j = 0; j < els; j++)
477330fc
RM
15089 if (j != key_el)
15090 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
15091 types[j]);
dcbf9037
JB
15092 }
15093 else if (inst.vectype.elems == 0 && els > 0)
15094 {
15095 unsigned j;
15096 /* No types were given after the mnemonic, so look for types specified
477330fc
RM
15097 after each operand. We allow some flexibility here; as long as the
15098 "key" operand has a type, we can infer the others. */
dcbf9037 15099 for (j = 0; j < els; j++)
477330fc
RM
15100 if (inst.operands[j].vectype.type != NT_invtype)
15101 inst.vectype.el[j] = inst.operands[j].vectype;
dcbf9037
JB
15102
15103 if (inst.operands[key_el].vectype.type != NT_invtype)
477330fc
RM
15104 {
15105 for (j = 0; j < els; j++)
15106 if (inst.operands[j].vectype.type == NT_invtype)
15107 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
15108 types[j]);
15109 }
dcbf9037 15110 else
477330fc
RM
15111 {
15112 first_error (_("operand types can't be inferred"));
15113 return badtype;
15114 }
5287ad62
JB
15115 }
15116 else if (inst.vectype.elems != els)
15117 {
dcbf9037 15118 first_error (_("type specifier has the wrong number of parts"));
5287ad62
JB
15119 return badtype;
15120 }
15121
15122 for (pass = 0; pass < 2; pass++)
15123 {
15124 for (i = 0; i < els; i++)
477330fc
RM
15125 {
15126 unsigned thisarg = types[i];
15127 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
15128 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
15129 enum neon_el_type g_type = inst.vectype.el[i].type;
15130 unsigned g_size = inst.vectype.el[i].size;
15131
15132 /* Decay more-specific signed & unsigned types to sign-insensitive
5287ad62 15133 integer types if sign-specific variants are unavailable. */
477330fc 15134 if ((g_type == NT_signed || g_type == NT_unsigned)
5287ad62
JB
15135 && (types_allowed & N_SU_ALL) == 0)
15136 g_type = NT_integer;
15137
477330fc 15138 /* If only untyped args are allowed, decay any more specific types to
5287ad62
JB
15139 them. Some instructions only care about signs for some element
15140 sizes, so handle that properly. */
477330fc 15141 if (((types_allowed & N_UNT) == 0)
91ff7894
MGD
15142 && ((g_size == 8 && (types_allowed & N_8) != 0)
15143 || (g_size == 16 && (types_allowed & N_16) != 0)
15144 || (g_size == 32 && (types_allowed & N_32) != 0)
15145 || (g_size == 64 && (types_allowed & N_64) != 0)))
5287ad62
JB
15146 g_type = NT_untyped;
15147
477330fc
RM
15148 if (pass == 0)
15149 {
15150 if ((thisarg & N_KEY) != 0)
15151 {
15152 k_type = g_type;
15153 k_size = g_size;
15154 key_allowed = thisarg & ~N_KEY;
cc933301
JW
15155
15156 /* Check architecture constraint on FP16 extension. */
15157 if (k_size == 16
15158 && k_type == NT_float
15159 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
15160 {
15161 inst.error = _(BAD_FP16);
15162 return badtype;
15163 }
477330fc
RM
15164 }
15165 }
15166 else
15167 {
15168 if ((thisarg & N_VFP) != 0)
15169 {
15170 enum neon_shape_el regshape;
15171 unsigned regwidth, match;
99b253c5
NC
15172
15173 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15174 if (ns == NS_NULL)
15175 {
15176 first_error (_("invalid instruction shape"));
15177 return badtype;
15178 }
477330fc
RM
15179 regshape = neon_shape_tab[ns].el[i];
15180 regwidth = neon_shape_el_size[regshape];
15181
15182 /* In VFP mode, operands must match register widths. If we
15183 have a key operand, use its width, else use the width of
15184 the current operand. */
15185 if (k_size != -1u)
15186 match = k_size;
15187 else
15188 match = g_size;
15189
9db2f6b4
RL
15190 /* FP16 will use a single precision register. */
15191 if (regwidth == 32 && match == 16)
15192 {
15193 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
15194 match = regwidth;
15195 else
15196 {
15197 inst.error = _(BAD_FP16);
15198 return badtype;
15199 }
15200 }
15201
477330fc
RM
15202 if (regwidth != match)
15203 {
15204 first_error (_("operand size must match register width"));
15205 return badtype;
15206 }
15207 }
15208
15209 if ((thisarg & N_EQK) == 0)
15210 {
15211 unsigned given_type = type_chk_of_el_type (g_type, g_size);
15212
15213 if ((given_type & types_allowed) == 0)
15214 {
a302e574 15215 first_error (BAD_SIMD_TYPE);
477330fc
RM
15216 return badtype;
15217 }
15218 }
15219 else
15220 {
15221 enum neon_el_type mod_k_type = k_type;
15222 unsigned mod_k_size = k_size;
15223 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
15224 if (g_type != mod_k_type || g_size != mod_k_size)
15225 {
15226 first_error (_("inconsistent types in Neon instruction"));
15227 return badtype;
15228 }
15229 }
15230 }
15231 }
5287ad62
JB
15232 }
15233
15234 return inst.vectype.el[key_el];
15235}
15236
037e8744 15237/* Neon-style VFP instruction forwarding. */
5287ad62 15238
037e8744
JB
15239/* Thumb VFP instructions have 0xE in the condition field. */
15240
15241static void
15242do_vfp_cond_or_thumb (void)
5287ad62 15243{
88714cb8
DG
15244 inst.is_neon = 1;
15245
5287ad62 15246 if (thumb_mode)
037e8744 15247 inst.instruction |= 0xe0000000;
5287ad62 15248 else
037e8744 15249 inst.instruction |= inst.cond << 28;
5287ad62
JB
15250}
15251
037e8744
JB
15252/* Look up and encode a simple mnemonic, for use as a helper function for the
15253 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15254 etc. It is assumed that operand parsing has already been done, and that the
15255 operands are in the form expected by the given opcode (this isn't necessarily
15256 the same as the form in which they were parsed, hence some massaging must
15257 take place before this function is called).
15258 Checks current arch version against that in the looked-up opcode. */
5287ad62 15259
037e8744
JB
15260static void
15261do_vfp_nsyn_opcode (const char *opname)
5287ad62 15262{
037e8744 15263 const struct asm_opcode *opcode;
5f4273c7 15264
21d799b5 15265 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
5287ad62 15266
037e8744
JB
15267 if (!opcode)
15268 abort ();
5287ad62 15269
037e8744 15270 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
477330fc
RM
15271 thumb_mode ? *opcode->tvariant : *opcode->avariant),
15272 _(BAD_FPU));
5287ad62 15273
88714cb8
DG
15274 inst.is_neon = 1;
15275
037e8744
JB
15276 if (thumb_mode)
15277 {
15278 inst.instruction = opcode->tvalue;
15279 opcode->tencode ();
15280 }
15281 else
15282 {
15283 inst.instruction = (inst.cond << 28) | opcode->avalue;
15284 opcode->aencode ();
15285 }
15286}
5287ad62
JB
15287
15288static void
037e8744 15289do_vfp_nsyn_add_sub (enum neon_shape rs)
5287ad62 15290{
037e8744
JB
15291 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
15292
9db2f6b4 15293 if (rs == NS_FFF || rs == NS_HHH)
037e8744
JB
15294 {
15295 if (is_add)
477330fc 15296 do_vfp_nsyn_opcode ("fadds");
037e8744 15297 else
477330fc 15298 do_vfp_nsyn_opcode ("fsubs");
9db2f6b4
RL
15299
15300 /* ARMv8.2 fp16 instruction. */
15301 if (rs == NS_HHH)
15302 do_scalar_fp16_v82_encode ();
037e8744
JB
15303 }
15304 else
15305 {
15306 if (is_add)
477330fc 15307 do_vfp_nsyn_opcode ("faddd");
037e8744 15308 else
477330fc 15309 do_vfp_nsyn_opcode ("fsubd");
037e8744
JB
15310 }
15311}
15312
15313/* Check operand types to see if this is a VFP instruction, and if so call
15314 PFN (). */
15315
15316static int
15317try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
15318{
15319 enum neon_shape rs;
15320 struct neon_type_el et;
15321
15322 switch (args)
15323 {
15324 case 2:
9db2f6b4
RL
15325 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15326 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
037e8744 15327 break;
5f4273c7 15328
037e8744 15329 case 3:
9db2f6b4
RL
15330 rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
15331 et = neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
15332 N_F_ALL | N_KEY | N_VFP);
037e8744
JB
15333 break;
15334
15335 default:
15336 abort ();
15337 }
15338
15339 if (et.type != NT_invtype)
15340 {
15341 pfn (rs);
15342 return SUCCESS;
15343 }
037e8744 15344
99b253c5 15345 inst.error = NULL;
037e8744
JB
15346 return FAIL;
15347}
15348
15349static void
15350do_vfp_nsyn_mla_mls (enum neon_shape rs)
15351{
15352 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
5f4273c7 15353
9db2f6b4 15354 if (rs == NS_FFF || rs == NS_HHH)
037e8744
JB
15355 {
15356 if (is_mla)
477330fc 15357 do_vfp_nsyn_opcode ("fmacs");
037e8744 15358 else
477330fc 15359 do_vfp_nsyn_opcode ("fnmacs");
9db2f6b4
RL
15360
15361 /* ARMv8.2 fp16 instruction. */
15362 if (rs == NS_HHH)
15363 do_scalar_fp16_v82_encode ();
037e8744
JB
15364 }
15365 else
15366 {
15367 if (is_mla)
477330fc 15368 do_vfp_nsyn_opcode ("fmacd");
037e8744 15369 else
477330fc 15370 do_vfp_nsyn_opcode ("fnmacd");
037e8744
JB
15371 }
15372}
15373
62f3b8c8
PB
15374static void
15375do_vfp_nsyn_fma_fms (enum neon_shape rs)
15376{
15377 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
15378
9db2f6b4 15379 if (rs == NS_FFF || rs == NS_HHH)
62f3b8c8
PB
15380 {
15381 if (is_fma)
477330fc 15382 do_vfp_nsyn_opcode ("ffmas");
62f3b8c8 15383 else
477330fc 15384 do_vfp_nsyn_opcode ("ffnmas");
9db2f6b4
RL
15385
15386 /* ARMv8.2 fp16 instruction. */
15387 if (rs == NS_HHH)
15388 do_scalar_fp16_v82_encode ();
62f3b8c8
PB
15389 }
15390 else
15391 {
15392 if (is_fma)
477330fc 15393 do_vfp_nsyn_opcode ("ffmad");
62f3b8c8 15394 else
477330fc 15395 do_vfp_nsyn_opcode ("ffnmad");
62f3b8c8
PB
15396 }
15397}
15398
037e8744
JB
15399static void
15400do_vfp_nsyn_mul (enum neon_shape rs)
15401{
9db2f6b4
RL
15402 if (rs == NS_FFF || rs == NS_HHH)
15403 {
15404 do_vfp_nsyn_opcode ("fmuls");
15405
15406 /* ARMv8.2 fp16 instruction. */
15407 if (rs == NS_HHH)
15408 do_scalar_fp16_v82_encode ();
15409 }
037e8744
JB
15410 else
15411 do_vfp_nsyn_opcode ("fmuld");
15412}
15413
15414static void
15415do_vfp_nsyn_abs_neg (enum neon_shape rs)
15416{
15417 int is_neg = (inst.instruction & 0x80) != 0;
9db2f6b4 15418 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_VFP | N_KEY);
037e8744 15419
9db2f6b4 15420 if (rs == NS_FF || rs == NS_HH)
037e8744
JB
15421 {
15422 if (is_neg)
477330fc 15423 do_vfp_nsyn_opcode ("fnegs");
037e8744 15424 else
477330fc 15425 do_vfp_nsyn_opcode ("fabss");
9db2f6b4
RL
15426
15427 /* ARMv8.2 fp16 instruction. */
15428 if (rs == NS_HH)
15429 do_scalar_fp16_v82_encode ();
037e8744
JB
15430 }
15431 else
15432 {
15433 if (is_neg)
477330fc 15434 do_vfp_nsyn_opcode ("fnegd");
037e8744 15435 else
477330fc 15436 do_vfp_nsyn_opcode ("fabsd");
037e8744
JB
15437 }
15438}
15439
15440/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15441 insns belong to Neon, and are handled elsewhere. */
15442
15443static void
15444do_vfp_nsyn_ldm_stm (int is_dbmode)
15445{
15446 int is_ldm = (inst.instruction & (1 << 20)) != 0;
15447 if (is_ldm)
15448 {
15449 if (is_dbmode)
477330fc 15450 do_vfp_nsyn_opcode ("fldmdbs");
037e8744 15451 else
477330fc 15452 do_vfp_nsyn_opcode ("fldmias");
037e8744
JB
15453 }
15454 else
15455 {
15456 if (is_dbmode)
477330fc 15457 do_vfp_nsyn_opcode ("fstmdbs");
037e8744 15458 else
477330fc 15459 do_vfp_nsyn_opcode ("fstmias");
037e8744
JB
15460 }
15461}
15462
037e8744
JB
15463static void
15464do_vfp_nsyn_sqrt (void)
15465{
9db2f6b4
RL
15466 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15467 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
5f4273c7 15468
9db2f6b4
RL
15469 if (rs == NS_FF || rs == NS_HH)
15470 {
15471 do_vfp_nsyn_opcode ("fsqrts");
15472
15473 /* ARMv8.2 fp16 instruction. */
15474 if (rs == NS_HH)
15475 do_scalar_fp16_v82_encode ();
15476 }
037e8744
JB
15477 else
15478 do_vfp_nsyn_opcode ("fsqrtd");
15479}
15480
15481static void
15482do_vfp_nsyn_div (void)
15483{
9db2f6b4 15484 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
037e8744 15485 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
9db2f6b4 15486 N_F_ALL | N_KEY | N_VFP);
5f4273c7 15487
9db2f6b4
RL
15488 if (rs == NS_FFF || rs == NS_HHH)
15489 {
15490 do_vfp_nsyn_opcode ("fdivs");
15491
15492 /* ARMv8.2 fp16 instruction. */
15493 if (rs == NS_HHH)
15494 do_scalar_fp16_v82_encode ();
15495 }
037e8744
JB
15496 else
15497 do_vfp_nsyn_opcode ("fdivd");
15498}
15499
15500static void
15501do_vfp_nsyn_nmul (void)
15502{
9db2f6b4 15503 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
037e8744 15504 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
9db2f6b4 15505 N_F_ALL | N_KEY | N_VFP);
5f4273c7 15506
9db2f6b4 15507 if (rs == NS_FFF || rs == NS_HHH)
037e8744 15508 {
88714cb8 15509 NEON_ENCODE (SINGLE, inst);
037e8744 15510 do_vfp_sp_dyadic ();
9db2f6b4
RL
15511
15512 /* ARMv8.2 fp16 instruction. */
15513 if (rs == NS_HHH)
15514 do_scalar_fp16_v82_encode ();
037e8744
JB
15515 }
15516 else
15517 {
88714cb8 15518 NEON_ENCODE (DOUBLE, inst);
037e8744
JB
15519 do_vfp_dp_rd_rn_rm ();
15520 }
15521 do_vfp_cond_or_thumb ();
9db2f6b4 15522
037e8744
JB
15523}
15524
1b883319
AV
15525/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15526 (0, 1, 2, 3). */
15527
15528static unsigned
15529neon_logbits (unsigned x)
15530{
15531 return ffs (x) - 4;
15532}
15533
15534#define LOW4(R) ((R) & 0xf)
15535#define HI1(R) (((R) >> 4) & 1)
15536
15537static unsigned
15538mve_get_vcmp_vpt_cond (struct neon_type_el et)
15539{
15540 switch (et.type)
15541 {
15542 default:
15543 first_error (BAD_EL_TYPE);
15544 return 0;
15545 case NT_float:
15546 switch (inst.operands[0].imm)
15547 {
15548 default:
15549 first_error (_("invalid condition"));
15550 return 0;
15551 case 0x0:
15552 /* eq. */
15553 return 0;
15554 case 0x1:
15555 /* ne. */
15556 return 1;
15557 case 0xa:
15558 /* ge/ */
15559 return 4;
15560 case 0xb:
15561 /* lt. */
15562 return 5;
15563 case 0xc:
15564 /* gt. */
15565 return 6;
15566 case 0xd:
15567 /* le. */
15568 return 7;
15569 }
15570 case NT_integer:
15571 /* only accept eq and ne. */
15572 if (inst.operands[0].imm > 1)
15573 {
15574 first_error (_("invalid condition"));
15575 return 0;
15576 }
15577 return inst.operands[0].imm;
15578 case NT_unsigned:
15579 if (inst.operands[0].imm == 0x2)
15580 return 2;
15581 else if (inst.operands[0].imm == 0x8)
15582 return 3;
15583 else
15584 {
15585 first_error (_("invalid condition"));
15586 return 0;
15587 }
15588 case NT_signed:
15589 switch (inst.operands[0].imm)
15590 {
15591 default:
15592 first_error (_("invalid condition"));
15593 return 0;
15594 case 0xa:
15595 /* ge. */
15596 return 4;
15597 case 0xb:
15598 /* lt. */
15599 return 5;
15600 case 0xc:
15601 /* gt. */
15602 return 6;
15603 case 0xd:
15604 /* le. */
15605 return 7;
15606 }
15607 }
15608 /* Should be unreachable. */
15609 abort ();
15610}
15611
15612static void
15613do_mve_vpt (void)
15614{
15615 /* We are dealing with a vector predicated block. */
15616 if (inst.operands[0].present)
15617 {
15618 enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL);
15619 struct neon_type_el et
15620 = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32,
15621 N_EQK);
15622
15623 unsigned fcond = mve_get_vcmp_vpt_cond (et);
15624
15625 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
15626
15627 if (et.type == NT_invtype)
15628 return;
15629
15630 if (et.type == NT_float)
15631 {
15632 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
15633 BAD_FPU);
15634 constraint (et.size != 16 && et.size != 32, BAD_EL_TYPE);
15635 inst.instruction |= (et.size == 16) << 28;
15636 inst.instruction |= 0x3 << 20;
15637 }
15638 else
15639 {
15640 constraint (et.size != 8 && et.size != 16 && et.size != 32,
15641 BAD_EL_TYPE);
15642 inst.instruction |= 1 << 28;
15643 inst.instruction |= neon_logbits (et.size) << 20;
15644 }
15645
15646 if (inst.operands[2].isquad)
15647 {
15648 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15649 inst.instruction |= LOW4 (inst.operands[2].reg);
15650 inst.instruction |= (fcond & 0x2) >> 1;
15651 }
15652 else
15653 {
15654 if (inst.operands[2].reg == REG_SP)
15655 as_tsktsk (MVE_BAD_SP);
15656 inst.instruction |= 1 << 6;
15657 inst.instruction |= (fcond & 0x2) << 4;
15658 inst.instruction |= inst.operands[2].reg;
15659 }
15660 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15661 inst.instruction |= (fcond & 0x4) << 10;
15662 inst.instruction |= (fcond & 0x1) << 7;
15663
15664 }
15665 set_pred_insn_type (VPT_INSN);
15666 now_pred.cc = 0;
15667 now_pred.mask = ((inst.instruction & 0x00400000) >> 19)
15668 | ((inst.instruction & 0xe000) >> 13);
15669 now_pred.warn_deprecated = FALSE;
15670 now_pred.type = VECTOR_PRED;
15671 inst.is_neon = 1;
15672}
15673
15674static void
15675do_mve_vcmp (void)
15676{
15677 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
15678 if (!inst.operands[1].isreg || !inst.operands[1].isquad)
15679 first_error (_(reg_expected_msgs[REG_TYPE_MQ]));
15680 if (!inst.operands[2].present)
15681 first_error (_("MVE vector or ARM register expected"));
15682 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
15683
15684 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15685 if ((inst.instruction & 0xffffffff) == N_MNEM_vcmpe
15686 && inst.operands[1].isquad)
15687 {
15688 inst.instruction = N_MNEM_vcmp;
15689 inst.cond = 0x10;
15690 }
15691
15692 if (inst.cond > COND_ALWAYS)
15693 inst.pred_insn_type = INSIDE_VPT_INSN;
15694 else
15695 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15696
15697 enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL);
15698 struct neon_type_el et
15699 = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32,
15700 N_EQK);
15701
15702 constraint (rs == NS_IQR && inst.operands[2].reg == REG_PC
15703 && !inst.operands[2].iszr, BAD_PC);
15704
15705 unsigned fcond = mve_get_vcmp_vpt_cond (et);
15706
15707 inst.instruction = 0xee010f00;
15708 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15709 inst.instruction |= (fcond & 0x4) << 10;
15710 inst.instruction |= (fcond & 0x1) << 7;
15711 if (et.type == NT_float)
15712 {
15713 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
15714 BAD_FPU);
15715 inst.instruction |= (et.size == 16) << 28;
15716 inst.instruction |= 0x3 << 20;
15717 }
15718 else
15719 {
15720 inst.instruction |= 1 << 28;
15721 inst.instruction |= neon_logbits (et.size) << 20;
15722 }
15723 if (inst.operands[2].isquad)
15724 {
15725 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15726 inst.instruction |= (fcond & 0x2) >> 1;
15727 inst.instruction |= LOW4 (inst.operands[2].reg);
15728 }
15729 else
15730 {
15731 if (inst.operands[2].reg == REG_SP)
15732 as_tsktsk (MVE_BAD_SP);
15733 inst.instruction |= 1 << 6;
15734 inst.instruction |= (fcond & 0x2) << 4;
15735 inst.instruction |= inst.operands[2].reg;
15736 }
15737
15738 inst.is_neon = 1;
15739 return;
15740}
15741
935295b5
AV
15742static void
15743do_mve_vmaxa_vmina (void)
15744{
15745 if (inst.cond > COND_ALWAYS)
15746 inst.pred_insn_type = INSIDE_VPT_INSN;
15747 else
15748 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15749
15750 enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
15751 struct neon_type_el et
15752 = neon_check_type (2, rs, N_EQK, N_KEY | N_S8 | N_S16 | N_S32);
15753
15754 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15755 inst.instruction |= neon_logbits (et.size) << 18;
15756 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15757 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15758 inst.instruction |= LOW4 (inst.operands[1].reg);
15759 inst.is_neon = 1;
15760}
15761
f30ee27c
AV
15762static void
15763do_mve_vfmas (void)
15764{
15765 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
15766 struct neon_type_el et
15767 = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK, N_EQK);
15768
15769 if (inst.cond > COND_ALWAYS)
15770 inst.pred_insn_type = INSIDE_VPT_INSN;
15771 else
15772 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15773
15774 if (inst.operands[2].reg == REG_SP)
15775 as_tsktsk (MVE_BAD_SP);
15776 else if (inst.operands[2].reg == REG_PC)
15777 as_tsktsk (MVE_BAD_PC);
15778
15779 inst.instruction |= (et.size == 16) << 28;
15780 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15781 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15782 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15783 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15784 inst.instruction |= inst.operands[2].reg;
15785 inst.is_neon = 1;
15786}
15787
b409bdb6
AV
15788static void
15789do_mve_viddup (void)
15790{
15791 if (inst.cond > COND_ALWAYS)
15792 inst.pred_insn_type = INSIDE_VPT_INSN;
15793 else
15794 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15795
15796 unsigned imm = inst.relocs[0].exp.X_add_number;
15797 constraint (imm != 1 && imm != 2 && imm != 4 && imm != 8,
15798 _("immediate must be either 1, 2, 4 or 8"));
15799
15800 enum neon_shape rs;
15801 struct neon_type_el et;
15802 unsigned Rm;
15803 if (inst.instruction == M_MNEM_vddup || inst.instruction == M_MNEM_vidup)
15804 {
15805 rs = neon_select_shape (NS_QRI, NS_NULL);
15806 et = neon_check_type (2, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK);
15807 Rm = 7;
15808 }
15809 else
15810 {
15811 constraint ((inst.operands[2].reg % 2) != 1, BAD_EVEN);
15812 if (inst.operands[2].reg == REG_SP)
15813 as_tsktsk (MVE_BAD_SP);
15814 else if (inst.operands[2].reg == REG_PC)
15815 first_error (BAD_PC);
15816
15817 rs = neon_select_shape (NS_QRRI, NS_NULL);
15818 et = neon_check_type (3, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK, N_EQK);
15819 Rm = inst.operands[2].reg >> 1;
15820 }
15821 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15822 inst.instruction |= neon_logbits (et.size) << 20;
15823 inst.instruction |= inst.operands[1].reg << 16;
15824 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15825 inst.instruction |= (imm > 2) << 7;
15826 inst.instruction |= Rm << 1;
15827 inst.instruction |= (imm == 2 || imm == 8);
15828 inst.is_neon = 1;
15829}
15830
2d78f95b
AV
15831static void
15832do_mve_vmlas (void)
15833{
15834 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
15835 struct neon_type_el et
15836 = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
15837
15838 if (inst.operands[2].reg == REG_PC)
15839 as_tsktsk (MVE_BAD_PC);
15840 else if (inst.operands[2].reg == REG_SP)
15841 as_tsktsk (MVE_BAD_SP);
15842
15843 if (inst.cond > COND_ALWAYS)
15844 inst.pred_insn_type = INSIDE_VPT_INSN;
15845 else
15846 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15847
15848 inst.instruction |= (et.type == NT_unsigned) << 28;
15849 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15850 inst.instruction |= neon_logbits (et.size) << 20;
15851 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15852 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15853 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15854 inst.instruction |= inst.operands[2].reg;
15855 inst.is_neon = 1;
15856}
15857
acca5630
AV
15858static void
15859do_mve_vshll (void)
15860{
15861 struct neon_type_el et
15862 = neon_check_type (2, NS_QQI, N_EQK, N_S8 | N_U8 | N_S16 | N_U16 | N_KEY);
15863
15864 if (inst.cond > COND_ALWAYS)
15865 inst.pred_insn_type = INSIDE_VPT_INSN;
15866 else
15867 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15868
15869 int imm = inst.operands[2].imm;
15870 constraint (imm < 1 || (unsigned)imm > et.size,
15871 _("immediate value out of range"));
15872
15873 if ((unsigned)imm == et.size)
15874 {
15875 inst.instruction |= neon_logbits (et.size) << 18;
15876 inst.instruction |= 0x110001;
15877 }
15878 else
15879 {
15880 inst.instruction |= (et.size + imm) << 16;
15881 inst.instruction |= 0x800140;
15882 }
15883
15884 inst.instruction |= (et.type == NT_unsigned) << 28;
15885 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15886 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15887 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15888 inst.instruction |= LOW4 (inst.operands[1].reg);
15889 inst.is_neon = 1;
15890}
15891
15892static void
15893do_mve_vshlc (void)
15894{
15895 if (inst.cond > COND_ALWAYS)
15896 inst.pred_insn_type = INSIDE_VPT_INSN;
15897 else
15898 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15899
15900 if (inst.operands[1].reg == REG_PC)
15901 as_tsktsk (MVE_BAD_PC);
15902 else if (inst.operands[1].reg == REG_SP)
15903 as_tsktsk (MVE_BAD_SP);
15904
15905 int imm = inst.operands[2].imm;
15906 constraint (imm < 1 || imm > 32, _("immediate value out of range"));
15907
15908 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15909 inst.instruction |= (imm & 0x1f) << 16;
15910 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15911 inst.instruction |= inst.operands[1].reg;
15912 inst.is_neon = 1;
15913}
15914
4aa88b50
AV
15915static void
15916do_mve_vshrn (void)
15917{
15918 unsigned types;
15919 switch (inst.instruction)
15920 {
15921 case M_MNEM_vshrnt:
15922 case M_MNEM_vshrnb:
15923 case M_MNEM_vrshrnt:
15924 case M_MNEM_vrshrnb:
15925 types = N_I16 | N_I32;
15926 break;
15927 case M_MNEM_vqshrnt:
15928 case M_MNEM_vqshrnb:
15929 case M_MNEM_vqrshrnt:
15930 case M_MNEM_vqrshrnb:
15931 types = N_U16 | N_U32 | N_S16 | N_S32;
15932 break;
15933 case M_MNEM_vqshrunt:
15934 case M_MNEM_vqshrunb:
15935 case M_MNEM_vqrshrunt:
15936 case M_MNEM_vqrshrunb:
15937 types = N_S16 | N_S32;
15938 break;
15939 default:
15940 abort ();
15941 }
15942
15943 struct neon_type_el et = neon_check_type (2, NS_QQI, N_EQK, types | N_KEY);
15944
15945 if (inst.cond > COND_ALWAYS)
15946 inst.pred_insn_type = INSIDE_VPT_INSN;
15947 else
15948 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15949
15950 unsigned Qd = inst.operands[0].reg;
15951 unsigned Qm = inst.operands[1].reg;
15952 unsigned imm = inst.operands[2].imm;
15953 constraint (imm < 1 || ((unsigned) imm) > (et.size / 2),
15954 et.size == 16
15955 ? _("immediate operand expected in the range [1,8]")
15956 : _("immediate operand expected in the range [1,16]"));
15957
15958 inst.instruction |= (et.type == NT_unsigned) << 28;
15959 inst.instruction |= HI1 (Qd) << 22;
15960 inst.instruction |= (et.size - imm) << 16;
15961 inst.instruction |= LOW4 (Qd) << 12;
15962 inst.instruction |= HI1 (Qm) << 5;
15963 inst.instruction |= LOW4 (Qm);
15964 inst.is_neon = 1;
15965}
15966
1be7aba3
AV
15967static void
15968do_mve_vqmovn (void)
15969{
15970 struct neon_type_el et;
15971 if (inst.instruction == M_MNEM_vqmovnt
15972 || inst.instruction == M_MNEM_vqmovnb)
15973 et = neon_check_type (2, NS_QQ, N_EQK,
15974 N_U16 | N_U32 | N_S16 | N_S32 | N_KEY);
15975 else
15976 et = neon_check_type (2, NS_QQ, N_EQK, N_S16 | N_S32 | N_KEY);
15977
15978 if (inst.cond > COND_ALWAYS)
15979 inst.pred_insn_type = INSIDE_VPT_INSN;
15980 else
15981 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15982
15983 inst.instruction |= (et.type == NT_unsigned) << 28;
15984 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15985 inst.instruction |= (et.size == 32) << 18;
15986 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15987 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15988 inst.instruction |= LOW4 (inst.operands[1].reg);
15989 inst.is_neon = 1;
15990}
15991
3063888e
AV
15992static void
15993do_mve_vpsel (void)
15994{
15995 neon_select_shape (NS_QQQ, NS_NULL);
15996
15997 if (inst.cond > COND_ALWAYS)
15998 inst.pred_insn_type = INSIDE_VPT_INSN;
15999 else
16000 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16001
16002 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16003 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16004 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16005 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16006 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16007 inst.instruction |= LOW4 (inst.operands[2].reg);
16008 inst.is_neon = 1;
16009}
16010
16011static void
16012do_mve_vpnot (void)
16013{
16014 if (inst.cond > COND_ALWAYS)
16015 inst.pred_insn_type = INSIDE_VPT_INSN;
16016 else
16017 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16018}
16019
935295b5
AV
16020static void
16021do_mve_vmaxnma_vminnma (void)
16022{
16023 enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
16024 struct neon_type_el et
16025 = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
16026
16027 if (inst.cond > COND_ALWAYS)
16028 inst.pred_insn_type = INSIDE_VPT_INSN;
16029 else
16030 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16031
16032 inst.instruction |= (et.size == 16) << 28;
16033 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16034 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16035 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16036 inst.instruction |= LOW4 (inst.operands[1].reg);
16037 inst.is_neon = 1;
16038}
16039
5d281bf0
AV
16040static void
16041do_mve_vcmul (void)
16042{
16043 enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
16044 struct neon_type_el et
16045 = neon_check_type (3, rs, N_EQK, N_EQK, N_F_MVE | N_KEY);
16046
16047 if (inst.cond > COND_ALWAYS)
16048 inst.pred_insn_type = INSIDE_VPT_INSN;
16049 else
16050 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16051
16052 unsigned rot = inst.relocs[0].exp.X_add_number;
16053 constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
16054 _("immediate out of range"));
16055
16056 if (et.size == 32 && (inst.operands[0].reg == inst.operands[1].reg
16057 || inst.operands[0].reg == inst.operands[2].reg))
16058 as_tsktsk (BAD_MVE_SRCDEST);
16059
16060 inst.instruction |= (et.size == 32) << 28;
16061 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16062 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16063 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16064 inst.instruction |= (rot > 90) << 12;
16065 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16066 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16067 inst.instruction |= LOW4 (inst.operands[2].reg);
16068 inst.instruction |= (rot == 90 || rot == 270);
16069 inst.is_neon = 1;
16070}
16071
1f6234a3
AV
16072/* To handle the Low Overhead Loop instructions
16073 in Armv8.1-M Mainline and MVE. */
16074static void
16075do_t_loloop (void)
16076{
16077 unsigned long insn = inst.instruction;
16078
16079 inst.instruction = THUMB_OP32 (inst.instruction);
16080
16081 if (insn == T_MNEM_lctp)
16082 return;
16083
16084 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN);
16085
16086 if (insn == T_MNEM_wlstp || insn == T_MNEM_dlstp)
16087 {
16088 struct neon_type_el et
16089 = neon_check_type (2, NS_RR, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
16090 inst.instruction |= neon_logbits (et.size) << 20;
16091 inst.is_neon = 1;
16092 }
16093
16094 switch (insn)
16095 {
16096 case T_MNEM_letp:
16097 constraint (!inst.operands[0].present,
16098 _("expected LR"));
16099 /* fall through. */
16100 case T_MNEM_le:
16101 /* le <label>. */
16102 if (!inst.operands[0].present)
16103 inst.instruction |= 1 << 21;
16104
16105 v8_1_loop_reloc (TRUE);
16106 break;
16107
16108 case T_MNEM_wls:
16109 case T_MNEM_wlstp:
16110 v8_1_loop_reloc (FALSE);
16111 /* fall through. */
16112 case T_MNEM_dlstp:
16113 case T_MNEM_dls:
16114 constraint (inst.operands[1].isreg != 1, BAD_ARGS);
16115
16116 if (insn == T_MNEM_wlstp || insn == T_MNEM_dlstp)
16117 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
16118 else if (inst.operands[1].reg == REG_PC)
16119 as_tsktsk (MVE_BAD_PC);
16120 if (inst.operands[1].reg == REG_SP)
16121 as_tsktsk (MVE_BAD_SP);
16122
16123 inst.instruction |= (inst.operands[1].reg << 16);
16124 break;
16125
16126 default:
16127 abort ();
16128 }
16129}
16130
16131
037e8744
JB
16132static void
16133do_vfp_nsyn_cmp (void)
16134{
9db2f6b4 16135 enum neon_shape rs;
1b883319
AV
16136 if (!inst.operands[0].isreg)
16137 {
16138 do_mve_vcmp ();
16139 return;
16140 }
16141 else
16142 {
16143 constraint (inst.operands[2].present, BAD_SYNTAX);
16144 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd),
16145 BAD_FPU);
16146 }
16147
037e8744
JB
16148 if (inst.operands[1].isreg)
16149 {
9db2f6b4
RL
16150 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
16151 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
5f4273c7 16152
9db2f6b4 16153 if (rs == NS_FF || rs == NS_HH)
477330fc
RM
16154 {
16155 NEON_ENCODE (SINGLE, inst);
16156 do_vfp_sp_monadic ();
16157 }
037e8744 16158 else
477330fc
RM
16159 {
16160 NEON_ENCODE (DOUBLE, inst);
16161 do_vfp_dp_rd_rm ();
16162 }
037e8744
JB
16163 }
16164 else
16165 {
9db2f6b4
RL
16166 rs = neon_select_shape (NS_HI, NS_FI, NS_DI, NS_NULL);
16167 neon_check_type (2, rs, N_F_ALL | N_KEY | N_VFP, N_EQK);
037e8744
JB
16168
16169 switch (inst.instruction & 0x0fffffff)
477330fc
RM
16170 {
16171 case N_MNEM_vcmp:
16172 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
16173 break;
16174 case N_MNEM_vcmpe:
16175 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
16176 break;
16177 default:
16178 abort ();
16179 }
5f4273c7 16180
9db2f6b4 16181 if (rs == NS_FI || rs == NS_HI)
477330fc
RM
16182 {
16183 NEON_ENCODE (SINGLE, inst);
16184 do_vfp_sp_compare_z ();
16185 }
037e8744 16186 else
477330fc
RM
16187 {
16188 NEON_ENCODE (DOUBLE, inst);
16189 do_vfp_dp_rd ();
16190 }
037e8744
JB
16191 }
16192 do_vfp_cond_or_thumb ();
9db2f6b4
RL
16193
16194 /* ARMv8.2 fp16 instruction. */
16195 if (rs == NS_HI || rs == NS_HH)
16196 do_scalar_fp16_v82_encode ();
037e8744
JB
16197}
16198
16199static void
16200nsyn_insert_sp (void)
16201{
16202 inst.operands[1] = inst.operands[0];
16203 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
fdfde340 16204 inst.operands[0].reg = REG_SP;
037e8744
JB
16205 inst.operands[0].isreg = 1;
16206 inst.operands[0].writeback = 1;
16207 inst.operands[0].present = 1;
16208}
16209
16210static void
16211do_vfp_nsyn_push (void)
16212{
16213 nsyn_insert_sp ();
b126985e
NC
16214
16215 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
16216 _("register list must contain at least 1 and at most 16 "
16217 "registers"));
16218
037e8744
JB
16219 if (inst.operands[1].issingle)
16220 do_vfp_nsyn_opcode ("fstmdbs");
16221 else
16222 do_vfp_nsyn_opcode ("fstmdbd");
16223}
16224
16225static void
16226do_vfp_nsyn_pop (void)
16227{
16228 nsyn_insert_sp ();
b126985e
NC
16229
16230 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
16231 _("register list must contain at least 1 and at most 16 "
16232 "registers"));
16233
037e8744 16234 if (inst.operands[1].issingle)
22b5b651 16235 do_vfp_nsyn_opcode ("fldmias");
037e8744 16236 else
22b5b651 16237 do_vfp_nsyn_opcode ("fldmiad");
037e8744
JB
16238}
16239
16240/* Fix up Neon data-processing instructions, ORing in the correct bits for
16241 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16242
88714cb8
DG
16243static void
16244neon_dp_fixup (struct arm_it* insn)
037e8744 16245{
88714cb8
DG
16246 unsigned int i = insn->instruction;
16247 insn->is_neon = 1;
16248
037e8744
JB
16249 if (thumb_mode)
16250 {
16251 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16252 if (i & (1 << 24))
477330fc 16253 i |= 1 << 28;
5f4273c7 16254
037e8744 16255 i &= ~(1 << 24);
5f4273c7 16256
037e8744
JB
16257 i |= 0xef000000;
16258 }
16259 else
16260 i |= 0xf2000000;
5f4273c7 16261
88714cb8 16262 insn->instruction = i;
037e8744
JB
16263}
16264
5ee91343 16265static void
7df54120 16266mve_encode_qqr (int size, int U, int fp)
5ee91343
AV
16267{
16268 if (inst.operands[2].reg == REG_SP)
16269 as_tsktsk (MVE_BAD_SP);
16270 else if (inst.operands[2].reg == REG_PC)
16271 as_tsktsk (MVE_BAD_PC);
16272
16273 if (fp)
16274 {
16275 /* vadd. */
16276 if (((unsigned)inst.instruction) == 0xd00)
16277 inst.instruction = 0xee300f40;
16278 /* vsub. */
16279 else if (((unsigned)inst.instruction) == 0x200d00)
16280 inst.instruction = 0xee301f40;
a8465a06
AV
16281 /* vmul. */
16282 else if (((unsigned)inst.instruction) == 0x1000d10)
16283 inst.instruction = 0xee310e60;
5ee91343
AV
16284
16285 /* Setting size which is 1 for F16 and 0 for F32. */
16286 inst.instruction |= (size == 16) << 28;
16287 }
16288 else
16289 {
16290 /* vadd. */
16291 if (((unsigned)inst.instruction) == 0x800)
16292 inst.instruction = 0xee010f40;
16293 /* vsub. */
16294 else if (((unsigned)inst.instruction) == 0x1000800)
16295 inst.instruction = 0xee011f40;
7df54120
AV
16296 /* vhadd. */
16297 else if (((unsigned)inst.instruction) == 0)
16298 inst.instruction = 0xee000f40;
16299 /* vhsub. */
16300 else if (((unsigned)inst.instruction) == 0x200)
16301 inst.instruction = 0xee001f40;
a8465a06
AV
16302 /* vmla. */
16303 else if (((unsigned)inst.instruction) == 0x900)
16304 inst.instruction = 0xee010e40;
16305 /* vmul. */
16306 else if (((unsigned)inst.instruction) == 0x910)
16307 inst.instruction = 0xee011e60;
16308 /* vqadd. */
16309 else if (((unsigned)inst.instruction) == 0x10)
16310 inst.instruction = 0xee000f60;
16311 /* vqsub. */
16312 else if (((unsigned)inst.instruction) == 0x210)
16313 inst.instruction = 0xee001f60;
42b16635
AV
16314 /* vqrdmlah. */
16315 else if (((unsigned)inst.instruction) == 0x3000b10)
16316 inst.instruction = 0xee000e40;
16317 /* vqdmulh. */
16318 else if (((unsigned)inst.instruction) == 0x0000b00)
16319 inst.instruction = 0xee010e60;
16320 /* vqrdmulh. */
16321 else if (((unsigned)inst.instruction) == 0x1000b00)
16322 inst.instruction = 0xfe010e60;
7df54120
AV
16323
16324 /* Set U-bit. */
16325 inst.instruction |= U << 28;
16326
5ee91343
AV
16327 /* Setting bits for size. */
16328 inst.instruction |= neon_logbits (size) << 20;
16329 }
16330 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16331 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16332 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16333 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16334 inst.instruction |= inst.operands[2].reg;
16335 inst.is_neon = 1;
16336}
16337
a302e574
AV
16338static void
16339mve_encode_rqq (unsigned bit28, unsigned size)
16340{
16341 inst.instruction |= bit28 << 28;
16342 inst.instruction |= neon_logbits (size) << 20;
16343 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16344 inst.instruction |= inst.operands[0].reg << 12;
16345 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16346 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16347 inst.instruction |= LOW4 (inst.operands[2].reg);
16348 inst.is_neon = 1;
16349}
16350
886e1c73
AV
16351static void
16352mve_encode_qqq (int ubit, int size)
16353{
16354
16355 inst.instruction |= (ubit != 0) << 28;
16356 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16357 inst.instruction |= neon_logbits (size) << 20;
16358 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16359 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16360 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16361 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16362 inst.instruction |= LOW4 (inst.operands[2].reg);
16363
16364 inst.is_neon = 1;
16365}
16366
26c1e780
AV
16367static void
16368mve_encode_rq (unsigned bit28, unsigned size)
16369{
16370 inst.instruction |= bit28 << 28;
16371 inst.instruction |= neon_logbits (size) << 18;
16372 inst.instruction |= inst.operands[0].reg << 12;
16373 inst.instruction |= LOW4 (inst.operands[1].reg);
16374 inst.is_neon = 1;
16375}
886e1c73 16376
93925576
AV
16377static void
16378mve_encode_rrqq (unsigned U, unsigned size)
16379{
16380 constraint (inst.operands[3].reg > 14, MVE_BAD_QREG);
16381
16382 inst.instruction |= U << 28;
16383 inst.instruction |= (inst.operands[1].reg >> 1) << 20;
16384 inst.instruction |= LOW4 (inst.operands[2].reg) << 16;
16385 inst.instruction |= (size == 32) << 16;
16386 inst.instruction |= inst.operands[0].reg << 12;
16387 inst.instruction |= HI1 (inst.operands[2].reg) << 7;
16388 inst.instruction |= inst.operands[3].reg;
16389 inst.is_neon = 1;
16390}
16391
037e8744
JB
16392/* Encode insns with bit pattern:
16393
16394 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16395 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
5f4273c7 16396
037e8744
JB
16397 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16398 different meaning for some instruction. */
16399
16400static void
16401neon_three_same (int isquad, int ubit, int size)
16402{
16403 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16404 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16405 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16406 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16407 inst.instruction |= LOW4 (inst.operands[2].reg);
16408 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16409 inst.instruction |= (isquad != 0) << 6;
16410 inst.instruction |= (ubit != 0) << 24;
16411 if (size != -1)
16412 inst.instruction |= neon_logbits (size) << 20;
5f4273c7 16413
88714cb8 16414 neon_dp_fixup (&inst);
037e8744
JB
16415}
16416
16417/* Encode instructions of the form:
16418
16419 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16420 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
5287ad62
JB
16421
16422 Don't write size if SIZE == -1. */
16423
16424static void
16425neon_two_same (int qbit, int ubit, int size)
16426{
16427 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16428 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16429 inst.instruction |= LOW4 (inst.operands[1].reg);
16430 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16431 inst.instruction |= (qbit != 0) << 6;
16432 inst.instruction |= (ubit != 0) << 24;
16433
16434 if (size != -1)
16435 inst.instruction |= neon_logbits (size) << 18;
16436
88714cb8 16437 neon_dp_fixup (&inst);
5287ad62
JB
16438}
16439
7df54120
AV
16440enum vfp_or_neon_is_neon_bits
16441{
16442NEON_CHECK_CC = 1,
16443NEON_CHECK_ARCH = 2,
16444NEON_CHECK_ARCH8 = 4
16445};
16446
16447/* Call this function if an instruction which may have belonged to the VFP or
16448 Neon instruction sets, but turned out to be a Neon instruction (due to the
16449 operand types involved, etc.). We have to check and/or fix-up a couple of
16450 things:
16451
16452 - Make sure the user hasn't attempted to make a Neon instruction
16453 conditional.
16454 - Alter the value in the condition code field if necessary.
16455 - Make sure that the arch supports Neon instructions.
16456
16457 Which of these operations take place depends on bits from enum
16458 vfp_or_neon_is_neon_bits.
16459
16460 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16461 current instruction's condition is COND_ALWAYS, the condition field is
16462 changed to inst.uncond_value. This is necessary because instructions shared
16463 between VFP and Neon may be conditional for the VFP variants only, and the
16464 unconditional Neon version must have, e.g., 0xF in the condition field. */
16465
16466static int
16467vfp_or_neon_is_neon (unsigned check)
16468{
16469/* Conditions are always legal in Thumb mode (IT blocks). */
16470if (!thumb_mode && (check & NEON_CHECK_CC))
16471 {
16472 if (inst.cond != COND_ALWAYS)
16473 {
16474 first_error (_(BAD_COND));
16475 return FAIL;
16476 }
16477 if (inst.uncond_value != -1)
16478 inst.instruction |= inst.uncond_value << 28;
16479 }
16480
16481
16482 if (((check & NEON_CHECK_ARCH) && !mark_feature_used (&fpu_neon_ext_v1))
16483 || ((check & NEON_CHECK_ARCH8)
16484 && !mark_feature_used (&fpu_neon_ext_armv8)))
16485 {
16486 first_error (_(BAD_FPU));
16487 return FAIL;
16488 }
16489
16490return SUCCESS;
16491}
16492
64c350f2
AV
16493
16494/* Return TRUE if the SIMD instruction is available for the current
16495 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16496 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16497 vfp_or_neon_is_neon for the NEON specific checks. */
16498
16499static bfd_boolean
7df54120
AV
16500check_simd_pred_availability (int fp, unsigned check)
16501{
16502if (inst.cond > COND_ALWAYS)
16503 {
16504 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16505 {
16506 inst.error = BAD_FPU;
64c350f2 16507 return FALSE;
7df54120
AV
16508 }
16509 inst.pred_insn_type = INSIDE_VPT_INSN;
16510 }
16511else if (inst.cond < COND_ALWAYS)
16512 {
16513 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16514 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16515 else if (vfp_or_neon_is_neon (check) == FAIL)
64c350f2 16516 return FALSE;
7df54120
AV
16517 }
16518else
16519 {
16520 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fp ? mve_fp_ext : mve_ext)
16521 && vfp_or_neon_is_neon (check) == FAIL)
64c350f2 16522 return FALSE;
7df54120
AV
16523
16524 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16525 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16526 }
64c350f2 16527return TRUE;
7df54120
AV
16528}
16529
5287ad62
JB
16530/* Neon instruction encoders, in approximate order of appearance. */
16531
16532static void
16533do_neon_dyadic_i_su (void)
16534{
64c350f2 16535 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
7df54120
AV
16536 return;
16537
16538 enum neon_shape rs;
16539 struct neon_type_el et;
16540 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16541 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
16542 else
16543 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16544
16545 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_32 | N_KEY);
16546
16547
16548 if (rs != NS_QQR)
16549 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16550 else
16551 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
5287ad62
JB
16552}
16553
16554static void
16555do_neon_dyadic_i64_su (void)
16556{
64c350f2 16557 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
a8465a06
AV
16558 return;
16559 enum neon_shape rs;
16560 struct neon_type_el et;
16561 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16562 {
16563 rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
16564 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
16565 }
16566 else
16567 {
16568 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16569 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY);
16570 }
16571 if (rs == NS_QQR)
16572 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
16573 else
16574 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB
16575}
16576
16577static void
16578neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
477330fc 16579 unsigned immbits)
5287ad62
JB
16580{
16581 unsigned size = et.size >> 3;
16582 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16583 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16584 inst.instruction |= LOW4 (inst.operands[1].reg);
16585 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16586 inst.instruction |= (isquad != 0) << 6;
16587 inst.instruction |= immbits << 16;
16588 inst.instruction |= (size >> 3) << 7;
16589 inst.instruction |= (size & 0x7) << 19;
16590 if (write_ubit)
16591 inst.instruction |= (uval != 0) << 24;
16592
88714cb8 16593 neon_dp_fixup (&inst);
5287ad62
JB
16594}
16595
16596static void
5150f0d8 16597do_neon_shl (void)
5287ad62 16598{
64c350f2 16599 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
5150f0d8
AV
16600 return;
16601
5287ad62
JB
16602 if (!inst.operands[2].isreg)
16603 {
5150f0d8
AV
16604 enum neon_shape rs;
16605 struct neon_type_el et;
16606 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16607 {
16608 rs = neon_select_shape (NS_QQI, NS_NULL);
16609 et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_MVE);
16610 }
16611 else
16612 {
16613 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16614 et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
16615 }
cb3b1e65
JB
16616 int imm = inst.operands[2].imm;
16617
16618 constraint (imm < 0 || (unsigned)imm >= et.size,
16619 _("immediate out of range for shift"));
88714cb8 16620 NEON_ENCODE (IMMED, inst);
cb3b1e65 16621 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB
16622 }
16623 else
16624 {
5150f0d8
AV
16625 enum neon_shape rs;
16626 struct neon_type_el et;
16627 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16628 {
16629 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
16630 et = neon_check_type (3, rs, N_EQK, N_SU_MVE | N_KEY, N_EQK | N_EQK);
16631 }
16632 else
16633 {
16634 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16635 et = neon_check_type (3, rs, N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
16636 }
16637
16638
16639 if (rs == NS_QQR)
16640 {
16641 constraint (inst.operands[0].reg != inst.operands[1].reg,
16642 _("invalid instruction shape"));
16643 if (inst.operands[2].reg == REG_SP)
16644 as_tsktsk (MVE_BAD_SP);
16645 else if (inst.operands[2].reg == REG_PC)
16646 as_tsktsk (MVE_BAD_PC);
16647
16648 inst.instruction = 0xee311e60;
16649 inst.instruction |= (et.type == NT_unsigned) << 28;
16650 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16651 inst.instruction |= neon_logbits (et.size) << 18;
16652 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16653 inst.instruction |= inst.operands[2].reg;
16654 inst.is_neon = 1;
16655 }
16656 else
16657 {
16658 unsigned int tmp;
16659
16660 /* VSHL/VQSHL 3-register variants have syntax such as:
16661 vshl.xx Dd, Dm, Dn
16662 whereas other 3-register operations encoded by neon_three_same have
16663 syntax like:
16664 vadd.xx Dd, Dn, Dm
16665 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
16666 operands[2].reg here. */
16667 tmp = inst.operands[2].reg;
16668 inst.operands[2].reg = inst.operands[1].reg;
16669 inst.operands[1].reg = tmp;
16670 NEON_ENCODE (INTEGER, inst);
16671 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16672 }
5287ad62
JB
16673 }
16674}
16675
16676static void
5150f0d8 16677do_neon_qshl (void)
5287ad62 16678{
64c350f2 16679 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
5150f0d8
AV
16680 return;
16681
5287ad62
JB
16682 if (!inst.operands[2].isreg)
16683 {
5150f0d8
AV
16684 enum neon_shape rs;
16685 struct neon_type_el et;
16686 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16687 {
16688 rs = neon_select_shape (NS_QQI, NS_NULL);
16689 et = neon_check_type (2, rs, N_EQK, N_KEY | N_SU_MVE);
16690 }
16691 else
16692 {
16693 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16694 et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
16695 }
cb3b1e65 16696 int imm = inst.operands[2].imm;
627907b7 16697
cb3b1e65
JB
16698 constraint (imm < 0 || (unsigned)imm >= et.size,
16699 _("immediate out of range for shift"));
88714cb8 16700 NEON_ENCODE (IMMED, inst);
cb3b1e65 16701 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm);
5287ad62
JB
16702 }
16703 else
16704 {
5150f0d8
AV
16705 enum neon_shape rs;
16706 struct neon_type_el et;
627907b7 16707
5150f0d8
AV
16708 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16709 {
16710 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
16711 et = neon_check_type (3, rs, N_EQK, N_SU_MVE | N_KEY, N_EQK | N_EQK);
16712 }
16713 else
16714 {
16715 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16716 et = neon_check_type (3, rs, N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
16717 }
16718
16719 if (rs == NS_QQR)
16720 {
16721 constraint (inst.operands[0].reg != inst.operands[1].reg,
16722 _("invalid instruction shape"));
16723 if (inst.operands[2].reg == REG_SP)
16724 as_tsktsk (MVE_BAD_SP);
16725 else if (inst.operands[2].reg == REG_PC)
16726 as_tsktsk (MVE_BAD_PC);
16727
16728 inst.instruction = 0xee311ee0;
16729 inst.instruction |= (et.type == NT_unsigned) << 28;
16730 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16731 inst.instruction |= neon_logbits (et.size) << 18;
16732 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16733 inst.instruction |= inst.operands[2].reg;
16734 inst.is_neon = 1;
16735 }
16736 else
16737 {
16738 unsigned int tmp;
16739
16740 /* See note in do_neon_shl. */
16741 tmp = inst.operands[2].reg;
16742 inst.operands[2].reg = inst.operands[1].reg;
16743 inst.operands[1].reg = tmp;
16744 NEON_ENCODE (INTEGER, inst);
16745 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16746 }
5287ad62
JB
16747 }
16748}
16749
627907b7
JB
16750static void
16751do_neon_rshl (void)
16752{
64c350f2 16753 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
1be7aba3
AV
16754 return;
16755
16756 enum neon_shape rs;
16757 struct neon_type_el et;
16758 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16759 {
16760 rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
16761 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
16762 }
16763 else
16764 {
16765 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16766 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY);
16767 }
16768
627907b7
JB
16769 unsigned int tmp;
16770
1be7aba3
AV
16771 if (rs == NS_QQR)
16772 {
16773 if (inst.operands[2].reg == REG_PC)
16774 as_tsktsk (MVE_BAD_PC);
16775 else if (inst.operands[2].reg == REG_SP)
16776 as_tsktsk (MVE_BAD_SP);
16777
16778 constraint (inst.operands[0].reg != inst.operands[1].reg,
16779 _("invalid instruction shape"));
16780
16781 if (inst.instruction == 0x0000510)
16782 /* We are dealing with vqrshl. */
16783 inst.instruction = 0xee331ee0;
16784 else
16785 /* We are dealing with vrshl. */
16786 inst.instruction = 0xee331e60;
16787
16788 inst.instruction |= (et.type == NT_unsigned) << 28;
16789 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16790 inst.instruction |= neon_logbits (et.size) << 18;
16791 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16792 inst.instruction |= inst.operands[2].reg;
16793 inst.is_neon = 1;
16794 }
16795 else
16796 {
16797 tmp = inst.operands[2].reg;
16798 inst.operands[2].reg = inst.operands[1].reg;
16799 inst.operands[1].reg = tmp;
16800 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16801 }
627907b7
JB
16802}
16803
5287ad62
JB
16804static int
16805neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
16806{
036dc3f7
PB
16807 /* Handle .I8 pseudo-instructions. */
16808 if (size == 8)
5287ad62 16809 {
5287ad62 16810 /* Unfortunately, this will make everything apart from zero out-of-range.
477330fc
RM
16811 FIXME is this the intended semantics? There doesn't seem much point in
16812 accepting .I8 if so. */
5287ad62
JB
16813 immediate |= immediate << 8;
16814 size = 16;
036dc3f7
PB
16815 }
16816
16817 if (size >= 32)
16818 {
16819 if (immediate == (immediate & 0x000000ff))
16820 {
16821 *immbits = immediate;
16822 return 0x1;
16823 }
16824 else if (immediate == (immediate & 0x0000ff00))
16825 {
16826 *immbits = immediate >> 8;
16827 return 0x3;
16828 }
16829 else if (immediate == (immediate & 0x00ff0000))
16830 {
16831 *immbits = immediate >> 16;
16832 return 0x5;
16833 }
16834 else if (immediate == (immediate & 0xff000000))
16835 {
16836 *immbits = immediate >> 24;
16837 return 0x7;
16838 }
16839 if ((immediate & 0xffff) != (immediate >> 16))
16840 goto bad_immediate;
16841 immediate &= 0xffff;
5287ad62
JB
16842 }
16843
16844 if (immediate == (immediate & 0x000000ff))
16845 {
16846 *immbits = immediate;
036dc3f7 16847 return 0x9;
5287ad62
JB
16848 }
16849 else if (immediate == (immediate & 0x0000ff00))
16850 {
16851 *immbits = immediate >> 8;
036dc3f7 16852 return 0xb;
5287ad62
JB
16853 }
16854
16855 bad_immediate:
dcbf9037 16856 first_error (_("immediate value out of range"));
5287ad62
JB
16857 return FAIL;
16858}
16859
5287ad62
JB
16860static void
16861do_neon_logic (void)
16862{
16863 if (inst.operands[2].present && inst.operands[2].isreg)
16864 {
037e8744 16865 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
f601a00c 16866 if (rs == NS_QQQ
64c350f2
AV
16867 && !check_simd_pred_availability (FALSE,
16868 NEON_CHECK_ARCH | NEON_CHECK_CC))
f601a00c
AV
16869 return;
16870 else if (rs != NS_QQQ
16871 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
16872 first_error (BAD_FPU);
16873
5287ad62
JB
16874 neon_check_type (3, rs, N_IGNORE_TYPE);
16875 /* U bit and size field were set as part of the bitmask. */
88714cb8 16876 NEON_ENCODE (INTEGER, inst);
037e8744 16877 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB
16878 }
16879 else
16880 {
4316f0d2
DG
16881 const int three_ops_form = (inst.operands[2].present
16882 && !inst.operands[2].isreg);
16883 const int immoperand = (three_ops_form ? 2 : 1);
16884 enum neon_shape rs = (three_ops_form
16885 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
16886 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
f601a00c
AV
16887 /* Because neon_select_shape makes the second operand a copy of the first
16888 if the second operand is not present. */
16889 if (rs == NS_QQI
64c350f2
AV
16890 && !check_simd_pred_availability (FALSE,
16891 NEON_CHECK_ARCH | NEON_CHECK_CC))
f601a00c
AV
16892 return;
16893 else if (rs != NS_QQI
16894 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
16895 first_error (BAD_FPU);
16896
16897 struct neon_type_el et;
16898 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16899 et = neon_check_type (2, rs, N_I32 | N_I16 | N_KEY, N_EQK);
16900 else
16901 et = neon_check_type (2, rs, N_I8 | N_I16 | N_I32 | N_I64 | N_F32
16902 | N_KEY, N_EQK);
16903
16904 if (et.type == NT_invtype)
16905 return;
21d799b5 16906 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
5287ad62
JB
16907 unsigned immbits;
16908 int cmode;
5f4273c7 16909
5f4273c7 16910
4316f0d2
DG
16911 if (three_ops_form)
16912 constraint (inst.operands[0].reg != inst.operands[1].reg,
16913 _("first and second operands shall be the same register"));
16914
88714cb8 16915 NEON_ENCODE (IMMED, inst);
5287ad62 16916
4316f0d2 16917 immbits = inst.operands[immoperand].imm;
036dc3f7
PB
16918 if (et.size == 64)
16919 {
16920 /* .i64 is a pseudo-op, so the immediate must be a repeating
16921 pattern. */
4316f0d2
DG
16922 if (immbits != (inst.operands[immoperand].regisimm ?
16923 inst.operands[immoperand].reg : 0))
036dc3f7
PB
16924 {
16925 /* Set immbits to an invalid constant. */
16926 immbits = 0xdeadbeef;
16927 }
16928 }
16929
5287ad62 16930 switch (opcode)
477330fc
RM
16931 {
16932 case N_MNEM_vbic:
16933 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
16934 break;
16935
16936 case N_MNEM_vorr:
16937 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
16938 break;
16939
16940 case N_MNEM_vand:
16941 /* Pseudo-instruction for VBIC. */
16942 neon_invert_size (&immbits, 0, et.size);
16943 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
16944 break;
16945
16946 case N_MNEM_vorn:
16947 /* Pseudo-instruction for VORR. */
16948 neon_invert_size (&immbits, 0, et.size);
16949 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
16950 break;
16951
16952 default:
16953 abort ();
16954 }
5287ad62
JB
16955
16956 if (cmode == FAIL)
477330fc 16957 return;
5287ad62 16958
037e8744 16959 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB
16960 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16961 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16962 inst.instruction |= cmode << 8;
16963 neon_write_immbits (immbits);
5f4273c7 16964
88714cb8 16965 neon_dp_fixup (&inst);
5287ad62
JB
16966 }
16967}
16968
16969static void
16970do_neon_bitfield (void)
16971{
037e8744 16972 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
dcbf9037 16973 neon_check_type (3, rs, N_IGNORE_TYPE);
037e8744 16974 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB
16975}
16976
16977static void
dcbf9037 16978neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
477330fc 16979 unsigned destbits)
5287ad62 16980{
5ee91343 16981 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
dcbf9037 16982 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
477330fc 16983 types | N_KEY);
5287ad62
JB
16984 if (et.type == NT_float)
16985 {
88714cb8 16986 NEON_ENCODE (FLOAT, inst);
5ee91343 16987 if (rs == NS_QQR)
7df54120 16988 mve_encode_qqr (et.size, 0, 1);
5ee91343
AV
16989 else
16990 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
5287ad62
JB
16991 }
16992 else
16993 {
88714cb8 16994 NEON_ENCODE (INTEGER, inst);
5ee91343 16995 if (rs == NS_QQR)
a8465a06 16996 mve_encode_qqr (et.size, et.type == ubit_meaning, 0);
5ee91343
AV
16997 else
16998 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
5287ad62
JB
16999 }
17000}
17001
5287ad62
JB
17002
17003static void
17004do_neon_dyadic_if_su_d (void)
17005{
17006 /* This version only allow D registers, but that constraint is enforced during
17007 operand parsing so we don't need to do anything extra here. */
dcbf9037 17008 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
5287ad62
JB
17009}
17010
5287ad62
JB
17011static void
17012do_neon_dyadic_if_i_d (void)
17013{
428e3f1f
PB
17014 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17015 affected if we specify unsigned args. */
17016 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
5287ad62
JB
17017}
17018
f5f10c66
AV
17019static void
17020do_mve_vstr_vldr_QI (int size, int elsize, int load)
17021{
17022 constraint (size < 32, BAD_ADDR_MODE);
17023 constraint (size != elsize, BAD_EL_TYPE);
17024 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
17025 constraint (!inst.operands[1].preind, BAD_ADDR_MODE);
17026 constraint (load && inst.operands[0].reg == inst.operands[1].reg,
17027 _("destination register and offset register may not be the"
17028 " same"));
17029
17030 int imm = inst.relocs[0].exp.X_add_number;
17031 int add = 1;
17032 if (imm < 0)
17033 {
17034 add = 0;
17035 imm = -imm;
17036 }
17037 constraint ((imm % (size / 8) != 0)
17038 || imm > (0x7f << neon_logbits (size)),
17039 (size == 32) ? _("immediate must be a multiple of 4 in the"
17040 " range of +/-[0,508]")
17041 : _("immediate must be a multiple of 8 in the"
17042 " range of +/-[0,1016]"));
17043 inst.instruction |= 0x11 << 24;
17044 inst.instruction |= add << 23;
17045 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17046 inst.instruction |= inst.operands[1].writeback << 21;
17047 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17048 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17049 inst.instruction |= 1 << 12;
17050 inst.instruction |= (size == 64) << 8;
17051 inst.instruction &= 0xffffff00;
17052 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
17053 inst.instruction |= imm >> neon_logbits (size);
17054}
17055
17056static void
17057do_mve_vstr_vldr_RQ (int size, int elsize, int load)
17058{
17059 unsigned os = inst.operands[1].imm >> 5;
17060 constraint (os != 0 && size == 8,
17061 _("can not shift offsets when accessing less than half-word"));
17062 constraint (os && os != neon_logbits (size),
17063 _("shift immediate must be 1, 2 or 3 for half-word, word"
17064 " or double-word accesses respectively"));
17065 if (inst.operands[1].reg == REG_PC)
17066 as_tsktsk (MVE_BAD_PC);
17067
17068 switch (size)
17069 {
17070 case 8:
17071 constraint (elsize >= 64, BAD_EL_TYPE);
17072 break;
17073 case 16:
17074 constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
17075 break;
17076 case 32:
17077 case 64:
17078 constraint (elsize != size, BAD_EL_TYPE);
17079 break;
17080 default:
17081 break;
17082 }
17083 constraint (inst.operands[1].writeback || !inst.operands[1].preind,
17084 BAD_ADDR_MODE);
17085 if (load)
17086 {
17087 constraint (inst.operands[0].reg == (inst.operands[1].imm & 0x1f),
17088 _("destination register and offset register may not be"
17089 " the same"));
17090 constraint (size == elsize && inst.vectype.el[0].type != NT_unsigned,
17091 BAD_EL_TYPE);
17092 constraint (inst.vectype.el[0].type != NT_unsigned
17093 && inst.vectype.el[0].type != NT_signed, BAD_EL_TYPE);
17094 inst.instruction |= (inst.vectype.el[0].type == NT_unsigned) << 28;
17095 }
17096 else
17097 {
17098 constraint (inst.vectype.el[0].type != NT_untyped, BAD_EL_TYPE);
17099 }
17100
17101 inst.instruction |= 1 << 23;
17102 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17103 inst.instruction |= inst.operands[1].reg << 16;
17104 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17105 inst.instruction |= neon_logbits (elsize) << 7;
17106 inst.instruction |= HI1 (inst.operands[1].imm) << 5;
17107 inst.instruction |= LOW4 (inst.operands[1].imm);
17108 inst.instruction |= !!os;
17109}
17110
17111static void
17112do_mve_vstr_vldr_RI (int size, int elsize, int load)
17113{
17114 enum neon_el_type type = inst.vectype.el[0].type;
17115
17116 constraint (size >= 64, BAD_ADDR_MODE);
17117 switch (size)
17118 {
17119 case 16:
17120 constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
17121 break;
17122 case 32:
17123 constraint (elsize != size, BAD_EL_TYPE);
17124 break;
17125 default:
17126 break;
17127 }
17128 if (load)
17129 {
17130 constraint (elsize != size && type != NT_unsigned
17131 && type != NT_signed, BAD_EL_TYPE);
17132 }
17133 else
17134 {
17135 constraint (elsize != size && type != NT_untyped, BAD_EL_TYPE);
17136 }
17137
17138 int imm = inst.relocs[0].exp.X_add_number;
17139 int add = 1;
17140 if (imm < 0)
17141 {
17142 add = 0;
17143 imm = -imm;
17144 }
17145
17146 if ((imm % (size / 8) != 0) || imm > (0x7f << neon_logbits (size)))
17147 {
17148 switch (size)
17149 {
17150 case 8:
17151 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17152 break;
17153 case 16:
17154 constraint (1, _("immediate must be a multiple of 2 in the"
17155 " range of +/-[0,254]"));
17156 break;
17157 case 32:
17158 constraint (1, _("immediate must be a multiple of 4 in the"
17159 " range of +/-[0,508]"));
17160 break;
17161 }
17162 }
17163
17164 if (size != elsize)
17165 {
17166 constraint (inst.operands[1].reg > 7, BAD_HIREG);
17167 constraint (inst.operands[0].reg > 14,
17168 _("MVE vector register in the range [Q0..Q7] expected"));
17169 inst.instruction |= (load && type == NT_unsigned) << 28;
17170 inst.instruction |= (size == 16) << 19;
17171 inst.instruction |= neon_logbits (elsize) << 7;
17172 }
17173 else
17174 {
17175 if (inst.operands[1].reg == REG_PC)
17176 as_tsktsk (MVE_BAD_PC);
17177 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
17178 as_tsktsk (MVE_BAD_SP);
17179 inst.instruction |= 1 << 12;
17180 inst.instruction |= neon_logbits (size) << 7;
17181 }
17182 inst.instruction |= inst.operands[1].preind << 24;
17183 inst.instruction |= add << 23;
17184 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17185 inst.instruction |= inst.operands[1].writeback << 21;
17186 inst.instruction |= inst.operands[1].reg << 16;
17187 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17188 inst.instruction &= 0xffffff80;
17189 inst.instruction |= imm >> neon_logbits (size);
17190
17191}
17192
17193static void
17194do_mve_vstr_vldr (void)
17195{
17196 unsigned size;
17197 int load = 0;
17198
17199 if (inst.cond > COND_ALWAYS)
17200 inst.pred_insn_type = INSIDE_VPT_INSN;
17201 else
17202 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17203
17204 switch (inst.instruction)
17205 {
17206 default:
17207 gas_assert (0);
17208 break;
17209 case M_MNEM_vldrb:
17210 load = 1;
17211 /* fall through. */
17212 case M_MNEM_vstrb:
17213 size = 8;
17214 break;
17215 case M_MNEM_vldrh:
17216 load = 1;
17217 /* fall through. */
17218 case M_MNEM_vstrh:
17219 size = 16;
17220 break;
17221 case M_MNEM_vldrw:
17222 load = 1;
17223 /* fall through. */
17224 case M_MNEM_vstrw:
17225 size = 32;
17226 break;
17227 case M_MNEM_vldrd:
17228 load = 1;
17229 /* fall through. */
17230 case M_MNEM_vstrd:
17231 size = 64;
17232 break;
17233 }
17234 unsigned elsize = inst.vectype.el[0].size;
17235
17236 if (inst.operands[1].isquad)
17237 {
17238 /* We are dealing with [Q, imm]{!} cases. */
17239 do_mve_vstr_vldr_QI (size, elsize, load);
17240 }
17241 else
17242 {
17243 if (inst.operands[1].immisreg == 2)
17244 {
17245 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17246 do_mve_vstr_vldr_RQ (size, elsize, load);
17247 }
17248 else if (!inst.operands[1].immisreg)
17249 {
17250 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17251 do_mve_vstr_vldr_RI (size, elsize, load);
17252 }
17253 else
17254 constraint (1, BAD_ADDR_MODE);
17255 }
17256
17257 inst.is_neon = 1;
17258}
17259
35c228db
AV
17260static void
17261do_mve_vst_vld (void)
17262{
17263 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17264 return;
17265
17266 constraint (!inst.operands[1].preind || inst.relocs[0].exp.X_add_symbol != 0
17267 || inst.relocs[0].exp.X_add_number != 0
17268 || inst.operands[1].immisreg != 0,
17269 BAD_ADDR_MODE);
17270 constraint (inst.vectype.el[0].size > 32, BAD_EL_TYPE);
17271 if (inst.operands[1].reg == REG_PC)
17272 as_tsktsk (MVE_BAD_PC);
17273 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
17274 as_tsktsk (MVE_BAD_SP);
17275
17276
17277 /* These instructions are one of the "exceptions" mentioned in
17278 handle_pred_state. They are MVE instructions that are not VPT compatible
17279 and do not accept a VPT code, thus appending such a code is a syntax
17280 error. */
17281 if (inst.cond > COND_ALWAYS)
17282 first_error (BAD_SYNTAX);
17283 /* If we append a scalar condition code we can set this to
17284 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17285 else if (inst.cond < COND_ALWAYS)
17286 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17287 else
17288 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
17289
17290 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17291 inst.instruction |= inst.operands[1].writeback << 21;
17292 inst.instruction |= inst.operands[1].reg << 16;
17293 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17294 inst.instruction |= neon_logbits (inst.vectype.el[0].size) << 7;
17295 inst.is_neon = 1;
17296}
17297
26c1e780
AV
17298static void
17299do_mve_vaddlv (void)
17300{
17301 enum neon_shape rs = neon_select_shape (NS_RRQ, NS_NULL);
17302 struct neon_type_el et
17303 = neon_check_type (3, rs, N_EQK, N_EQK, N_S32 | N_U32 | N_KEY);
17304
17305 if (et.type == NT_invtype)
17306 first_error (BAD_EL_TYPE);
17307
17308 if (inst.cond > COND_ALWAYS)
17309 inst.pred_insn_type = INSIDE_VPT_INSN;
17310 else
17311 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17312
17313 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
17314
17315 inst.instruction |= (et.type == NT_unsigned) << 28;
17316 inst.instruction |= inst.operands[1].reg << 19;
17317 inst.instruction |= inst.operands[0].reg << 12;
17318 inst.instruction |= inst.operands[2].reg;
17319 inst.is_neon = 1;
17320}
17321
5287ad62 17322static void
5ee91343 17323do_neon_dyadic_if_su (void)
5287ad62 17324{
5ee91343
AV
17325 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
17326 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
17327 N_SUF_32 | N_KEY);
17328
935295b5
AV
17329 constraint ((inst.instruction == ((unsigned) N_MNEM_vmax)
17330 || inst.instruction == ((unsigned) N_MNEM_vmin))
17331 && et.type == NT_float
17332 && !ARM_CPU_HAS_FEATURE (cpu_variant,fpu_neon_ext_v1), BAD_FPU);
17333
64c350f2
AV
17334 if (!check_simd_pred_availability (et.type == NT_float,
17335 NEON_CHECK_ARCH | NEON_CHECK_CC))
037e8744
JB
17336 return;
17337
5ee91343
AV
17338 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
17339}
17340
17341static void
17342do_neon_addsub_if_i (void)
17343{
17344 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
17345 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
037e8744
JB
17346 return;
17347
5ee91343
AV
17348 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
17349 struct neon_type_el et = neon_check_type (3, rs, N_EQK,
17350 N_EQK, N_IF_32 | N_I64 | N_KEY);
17351
17352 constraint (rs == NS_QQR && et.size == 64, BAD_FPU);
17353 /* If we are parsing Q registers and the element types match MVE, which NEON
17354 also supports, then we must check whether this is an instruction that can
17355 be used by both MVE/NEON. This distinction can be made based on whether
17356 they are predicated or not. */
17357 if ((rs == NS_QQQ || rs == NS_QQR) && et.size != 64)
17358 {
64c350f2
AV
17359 if (!check_simd_pred_availability (et.type == NT_float,
17360 NEON_CHECK_ARCH | NEON_CHECK_CC))
5ee91343
AV
17361 return;
17362 }
17363 else
17364 {
17365 /* If they are either in a D register or are using an unsupported. */
17366 if (rs != NS_QQR
17367 && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
17368 return;
17369 }
17370
5287ad62
JB
17371 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17372 affected if we specify unsigned args. */
dcbf9037 17373 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
5287ad62
JB
17374}
17375
17376/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17377 result to be:
17378 V<op> A,B (A is operand 0, B is operand 2)
17379 to mean:
17380 V<op> A,B,A
17381 not:
17382 V<op> A,B,B
17383 so handle that case specially. */
17384
17385static void
17386neon_exchange_operands (void)
17387{
5287ad62
JB
17388 if (inst.operands[1].present)
17389 {
e1fa0163
NC
17390 void *scratch = xmalloc (sizeof (inst.operands[0]));
17391
5287ad62
JB
17392 /* Swap operands[1] and operands[2]. */
17393 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
17394 inst.operands[1] = inst.operands[2];
17395 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
e1fa0163 17396 free (scratch);
5287ad62
JB
17397 }
17398 else
17399 {
17400 inst.operands[1] = inst.operands[2];
17401 inst.operands[2] = inst.operands[0];
17402 }
17403}
17404
17405static void
17406neon_compare (unsigned regtypes, unsigned immtypes, int invert)
17407{
17408 if (inst.operands[2].isreg)
17409 {
17410 if (invert)
477330fc 17411 neon_exchange_operands ();
dcbf9037 17412 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
5287ad62
JB
17413 }
17414 else
17415 {
037e8744 17416 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
dcbf9037 17417 struct neon_type_el et = neon_check_type (2, rs,
477330fc 17418 N_EQK | N_SIZ, immtypes | N_KEY);
5287ad62 17419
88714cb8 17420 NEON_ENCODE (IMMED, inst);
5287ad62
JB
17421 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17422 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17423 inst.instruction |= LOW4 (inst.operands[1].reg);
17424 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 17425 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB
17426 inst.instruction |= (et.type == NT_float) << 10;
17427 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 17428
88714cb8 17429 neon_dp_fixup (&inst);
5287ad62
JB
17430 }
17431}
17432
17433static void
17434do_neon_cmp (void)
17435{
cc933301 17436 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, FALSE);
5287ad62
JB
17437}
17438
17439static void
17440do_neon_cmp_inv (void)
17441{
cc933301 17442 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, TRUE);
5287ad62
JB
17443}
17444
17445static void
17446do_neon_ceq (void)
17447{
17448 neon_compare (N_IF_32, N_IF_32, FALSE);
17449}
17450
17451/* For multiply instructions, we have the possibility of 16-bit or 32-bit
17452 scalars, which are encoded in 5 bits, M : Rm.
17453 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17454 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
c604a79a
JW
17455 index in M.
17456
17457 Dot Product instructions are similar to multiply instructions except elsize
17458 should always be 32.
17459
17460 This function translates SCALAR, which is GAS's internal encoding of indexed
17461 scalar register, to raw encoding. There is also register and index range
17462 check based on ELSIZE. */
5287ad62
JB
17463
17464static unsigned
17465neon_scalar_for_mul (unsigned scalar, unsigned elsize)
17466{
dcbf9037
JB
17467 unsigned regno = NEON_SCALAR_REG (scalar);
17468 unsigned elno = NEON_SCALAR_INDEX (scalar);
5287ad62
JB
17469
17470 switch (elsize)
17471 {
17472 case 16:
17473 if (regno > 7 || elno > 3)
477330fc 17474 goto bad_scalar;
5287ad62 17475 return regno | (elno << 3);
5f4273c7 17476
5287ad62
JB
17477 case 32:
17478 if (regno > 15 || elno > 1)
477330fc 17479 goto bad_scalar;
5287ad62
JB
17480 return regno | (elno << 4);
17481
17482 default:
17483 bad_scalar:
dcbf9037 17484 first_error (_("scalar out of range for multiply instruction"));
5287ad62
JB
17485 }
17486
17487 return 0;
17488}
17489
17490/* Encode multiply / multiply-accumulate scalar instructions. */
17491
17492static void
17493neon_mul_mac (struct neon_type_el et, int ubit)
17494{
dcbf9037
JB
17495 unsigned scalar;
17496
17497 /* Give a more helpful error message if we have an invalid type. */
17498 if (et.type == NT_invtype)
17499 return;
5f4273c7 17500
dcbf9037 17501 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
5287ad62
JB
17502 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17503 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17504 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17505 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
17506 inst.instruction |= LOW4 (scalar);
17507 inst.instruction |= HI1 (scalar) << 5;
17508 inst.instruction |= (et.type == NT_float) << 8;
17509 inst.instruction |= neon_logbits (et.size) << 20;
17510 inst.instruction |= (ubit != 0) << 24;
17511
88714cb8 17512 neon_dp_fixup (&inst);
5287ad62
JB
17513}
17514
17515static void
17516do_neon_mac_maybe_scalar (void)
17517{
037e8744
JB
17518 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
17519 return;
17520
64c350f2 17521 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
037e8744
JB
17522 return;
17523
5287ad62
JB
17524 if (inst.operands[2].isscalar)
17525 {
a8465a06 17526 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
037e8744 17527 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
5287ad62 17528 struct neon_type_el et = neon_check_type (3, rs,
589a7d88 17529 N_EQK, N_EQK, N_I16 | N_I32 | N_F_16_32 | N_KEY);
88714cb8 17530 NEON_ENCODE (SCALAR, inst);
037e8744 17531 neon_mul_mac (et, neon_quad (rs));
5287ad62 17532 }
a8465a06
AV
17533 else if (!inst.operands[2].isvec)
17534 {
17535 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17536
17537 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
17538 neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
17539
17540 neon_dyadic_misc (NT_unsigned, N_SU_MVE, 0);
17541 }
5287ad62 17542 else
428e3f1f 17543 {
a8465a06 17544 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
428e3f1f
PB
17545 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17546 affected if we specify unsigned args. */
17547 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
17548 }
5287ad62
JB
17549}
17550
62f3b8c8
PB
17551static void
17552do_neon_fmac (void)
17553{
d58196e0
AV
17554 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_fma)
17555 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
62f3b8c8
PB
17556 return;
17557
64c350f2 17558 if (!check_simd_pred_availability (TRUE, NEON_CHECK_CC | NEON_CHECK_ARCH))
62f3b8c8
PB
17559 return;
17560
d58196e0
AV
17561 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
17562 {
17563 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
17564 struct neon_type_el et = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK,
17565 N_EQK);
17566
17567 if (rs == NS_QQR)
17568 {
17569 if (inst.operands[2].reg == REG_SP)
17570 as_tsktsk (MVE_BAD_SP);
17571 else if (inst.operands[2].reg == REG_PC)
17572 as_tsktsk (MVE_BAD_PC);
17573
17574 inst.instruction = 0xee310e40;
17575 inst.instruction |= (et.size == 16) << 28;
17576 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17577 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17578 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17579 inst.instruction |= HI1 (inst.operands[1].reg) << 6;
17580 inst.instruction |= inst.operands[2].reg;
17581 inst.is_neon = 1;
17582 return;
17583 }
17584 }
17585 else
17586 {
17587 constraint (!inst.operands[2].isvec, BAD_FPU);
17588 }
17589
62f3b8c8
PB
17590 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
17591}
17592
5287ad62
JB
17593static void
17594do_neon_tst (void)
17595{
037e8744 17596 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB
17597 struct neon_type_el et = neon_check_type (3, rs,
17598 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
037e8744 17599 neon_three_same (neon_quad (rs), 0, et.size);
5287ad62
JB
17600}
17601
17602/* VMUL with 3 registers allows the P8 type. The scalar version supports the
17603 same types as the MAC equivalents. The polynomial type for this instruction
17604 is encoded the same as the integer type. */
17605
17606static void
17607do_neon_mul (void)
17608{
037e8744
JB
17609 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
17610 return;
17611
64c350f2 17612 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
037e8744
JB
17613 return;
17614
5287ad62 17615 if (inst.operands[2].isscalar)
a8465a06
AV
17616 {
17617 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17618 do_neon_mac_maybe_scalar ();
17619 }
5287ad62 17620 else
a8465a06
AV
17621 {
17622 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17623 {
17624 enum neon_shape rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
17625 struct neon_type_el et
17626 = neon_check_type (3, rs, N_EQK, N_EQK, N_I_MVE | N_F_MVE | N_KEY);
17627 if (et.type == NT_float)
17628 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
17629 BAD_FPU);
17630
17631 neon_dyadic_misc (NT_float, N_I_MVE | N_F_MVE, 0);
17632 }
17633 else
17634 {
17635 constraint (!inst.operands[2].isvec, BAD_FPU);
17636 neon_dyadic_misc (NT_poly,
17637 N_I8 | N_I16 | N_I32 | N_F16 | N_F32 | N_P8, 0);
17638 }
17639 }
5287ad62
JB
17640}
17641
17642static void
17643do_neon_qdmulh (void)
17644{
64c350f2 17645 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
42b16635
AV
17646 return;
17647
5287ad62
JB
17648 if (inst.operands[2].isscalar)
17649 {
42b16635 17650 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
037e8744 17651 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
5287ad62 17652 struct neon_type_el et = neon_check_type (3, rs,
477330fc 17653 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
88714cb8 17654 NEON_ENCODE (SCALAR, inst);
037e8744 17655 neon_mul_mac (et, neon_quad (rs));
5287ad62
JB
17656 }
17657 else
17658 {
42b16635
AV
17659 enum neon_shape rs;
17660 struct neon_type_el et;
17661 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17662 {
17663 rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
17664 et = neon_check_type (3, rs,
17665 N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
17666 }
17667 else
17668 {
17669 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17670 et = neon_check_type (3, rs,
17671 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
17672 }
17673
88714cb8 17674 NEON_ENCODE (INTEGER, inst);
42b16635
AV
17675 if (rs == NS_QQR)
17676 mve_encode_qqr (et.size, 0, 0);
17677 else
17678 /* The U bit (rounding) comes from bit mask. */
17679 neon_three_same (neon_quad (rs), 0, et.size);
5287ad62
JB
17680 }
17681}
17682
26c1e780
AV
17683static void
17684do_mve_vaddv (void)
17685{
17686 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
17687 struct neon_type_el et
17688 = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
17689
17690 if (et.type == NT_invtype)
17691 first_error (BAD_EL_TYPE);
17692
17693 if (inst.cond > COND_ALWAYS)
17694 inst.pred_insn_type = INSIDE_VPT_INSN;
17695 else
17696 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17697
17698 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
17699
17700 mve_encode_rq (et.type == NT_unsigned, et.size);
17701}
17702
7df54120
AV
17703static void
17704do_mve_vhcadd (void)
17705{
17706 enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
17707 struct neon_type_el et
17708 = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
17709
17710 if (inst.cond > COND_ALWAYS)
17711 inst.pred_insn_type = INSIDE_VPT_INSN;
17712 else
17713 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17714
17715 unsigned rot = inst.relocs[0].exp.X_add_number;
17716 constraint (rot != 90 && rot != 270, _("immediate out of range"));
17717
17718 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
17719 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17720 "operand makes instruction UNPREDICTABLE"));
17721
17722 mve_encode_qqq (0, et.size);
17723 inst.instruction |= (rot == 270) << 12;
17724 inst.is_neon = 1;
17725}
17726
35d1cfc2
AV
17727static void
17728do_mve_vqdmull (void)
17729{
17730 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
17731 struct neon_type_el et
17732 = neon_check_type (3, rs, N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
17733
17734 if (et.size == 32
17735 && (inst.operands[0].reg == inst.operands[1].reg
17736 || (rs == NS_QQQ && inst.operands[0].reg == inst.operands[2].reg)))
17737 as_tsktsk (BAD_MVE_SRCDEST);
17738
17739 if (inst.cond > COND_ALWAYS)
17740 inst.pred_insn_type = INSIDE_VPT_INSN;
17741 else
17742 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17743
17744 if (rs == NS_QQQ)
17745 {
17746 mve_encode_qqq (et.size == 32, 64);
17747 inst.instruction |= 1;
17748 }
17749 else
17750 {
17751 mve_encode_qqr (64, et.size == 32, 0);
17752 inst.instruction |= 0x3 << 5;
17753 }
17754}
17755
c2dafc2a
AV
17756static void
17757do_mve_vadc (void)
17758{
17759 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
17760 struct neon_type_el et
17761 = neon_check_type (3, rs, N_KEY | N_I32, N_EQK, N_EQK);
17762
17763 if (et.type == NT_invtype)
17764 first_error (BAD_EL_TYPE);
17765
17766 if (inst.cond > COND_ALWAYS)
17767 inst.pred_insn_type = INSIDE_VPT_INSN;
17768 else
17769 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17770
17771 mve_encode_qqq (0, 64);
17772}
17773
17774static void
17775do_mve_vbrsr (void)
17776{
17777 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
17778 struct neon_type_el et
17779 = neon_check_type (3, rs, N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
17780
17781 if (inst.cond > COND_ALWAYS)
17782 inst.pred_insn_type = INSIDE_VPT_INSN;
17783 else
17784 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17785
7df54120 17786 mve_encode_qqr (et.size, 0, 0);
c2dafc2a
AV
17787}
17788
17789static void
17790do_mve_vsbc (void)
17791{
17792 neon_check_type (3, NS_QQQ, N_EQK, N_EQK, N_I32 | N_KEY);
17793
17794 if (inst.cond > COND_ALWAYS)
17795 inst.pred_insn_type = INSIDE_VPT_INSN;
17796 else
17797 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17798
17799 mve_encode_qqq (1, 64);
17800}
17801
2d78f95b
AV
17802static void
17803do_mve_vmulh (void)
17804{
17805 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
17806 struct neon_type_el et
17807 = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
17808
17809 if (inst.cond > COND_ALWAYS)
17810 inst.pred_insn_type = INSIDE_VPT_INSN;
17811 else
17812 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17813
17814 mve_encode_qqq (et.type == NT_unsigned, et.size);
17815}
17816
42b16635
AV
17817static void
17818do_mve_vqdmlah (void)
17819{
17820 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
17821 struct neon_type_el et
17822 = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
17823
17824 if (inst.cond > COND_ALWAYS)
17825 inst.pred_insn_type = INSIDE_VPT_INSN;
17826 else
17827 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17828
17829 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
17830}
8b8b22a4
AV
17831
17832static void
17833do_mve_vqdmladh (void)
17834{
17835 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
17836 struct neon_type_el et
17837 = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
17838
17839 if (inst.cond > COND_ALWAYS)
17840 inst.pred_insn_type = INSIDE_VPT_INSN;
17841 else
17842 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17843
17844 if (et.size == 32
17845 && (inst.operands[0].reg == inst.operands[1].reg
17846 || inst.operands[0].reg == inst.operands[2].reg))
17847 as_tsktsk (BAD_MVE_SRCDEST);
17848
17849 mve_encode_qqq (0, et.size);
17850}
17851
17852
886e1c73
AV
17853static void
17854do_mve_vmull (void)
17855{
17856
17857 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_DDS,
17858 NS_QQS, NS_QQQ, NS_QQR, NS_NULL);
17859 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
17860 && inst.cond == COND_ALWAYS
17861 && ((unsigned)inst.instruction) == M_MNEM_vmullt)
17862 {
17863 if (rs == NS_QQQ)
17864 {
17865
17866 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
17867 N_SUF_32 | N_F64 | N_P8
17868 | N_P16 | N_I_MVE | N_KEY);
17869 if (((et.type == NT_poly) && et.size == 8
17870 && ARM_CPU_IS_ANY (cpu_variant))
17871 || (et.type == NT_integer) || (et.type == NT_float))
17872 goto neon_vmul;
17873 }
17874 else
17875 goto neon_vmul;
17876 }
17877
17878 constraint (rs != NS_QQQ, BAD_FPU);
17879 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
17880 N_SU_32 | N_P8 | N_P16 | N_KEY);
17881
17882 /* We are dealing with MVE's vmullt. */
17883 if (et.size == 32
17884 && (inst.operands[0].reg == inst.operands[1].reg
17885 || inst.operands[0].reg == inst.operands[2].reg))
17886 as_tsktsk (BAD_MVE_SRCDEST);
17887
17888 if (inst.cond > COND_ALWAYS)
17889 inst.pred_insn_type = INSIDE_VPT_INSN;
17890 else
17891 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17892
17893 if (et.type == NT_poly)
17894 mve_encode_qqq (neon_logbits (et.size), 64);
17895 else
17896 mve_encode_qqq (et.type == NT_unsigned, et.size);
17897
17898 return;
17899
17900neon_vmul:
17901 inst.instruction = N_MNEM_vmul;
17902 inst.cond = 0xb;
17903 if (thumb_mode)
17904 inst.pred_insn_type = INSIDE_IT_INSN;
17905 do_neon_mul ();
17906}
17907
a302e574
AV
17908static void
17909do_mve_vabav (void)
17910{
17911 enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
17912
17913 if (rs == NS_NULL)
17914 return;
17915
17916 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17917 return;
17918
17919 struct neon_type_el et = neon_check_type (2, NS_NULL, N_EQK, N_KEY | N_S8
17920 | N_S16 | N_S32 | N_U8 | N_U16
17921 | N_U32);
17922
17923 if (inst.cond > COND_ALWAYS)
17924 inst.pred_insn_type = INSIDE_VPT_INSN;
17925 else
17926 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17927
17928 mve_encode_rqq (et.type == NT_unsigned, et.size);
17929}
17930
17931static void
17932do_mve_vmladav (void)
17933{
17934 enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
17935 struct neon_type_el et = neon_check_type (3, rs,
17936 N_EQK, N_EQK, N_SU_MVE | N_KEY);
17937
17938 if (et.type == NT_unsigned
17939 && (inst.instruction == M_MNEM_vmladavx
17940 || inst.instruction == M_MNEM_vmladavax
17941 || inst.instruction == M_MNEM_vmlsdav
17942 || inst.instruction == M_MNEM_vmlsdava
17943 || inst.instruction == M_MNEM_vmlsdavx
17944 || inst.instruction == M_MNEM_vmlsdavax))
17945 first_error (BAD_SIMD_TYPE);
17946
17947 constraint (inst.operands[2].reg > 14,
17948 _("MVE vector register in the range [Q0..Q7] expected"));
17949
17950 if (inst.cond > COND_ALWAYS)
17951 inst.pred_insn_type = INSIDE_VPT_INSN;
17952 else
17953 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17954
17955 if (inst.instruction == M_MNEM_vmlsdav
17956 || inst.instruction == M_MNEM_vmlsdava
17957 || inst.instruction == M_MNEM_vmlsdavx
17958 || inst.instruction == M_MNEM_vmlsdavax)
17959 inst.instruction |= (et.size == 8) << 28;
17960 else
17961 inst.instruction |= (et.size == 8) << 8;
17962
17963 mve_encode_rqq (et.type == NT_unsigned, 64);
17964 inst.instruction |= (et.size == 32) << 16;
17965}
17966
93925576
AV
17967static void
17968do_mve_vmlaldav (void)
17969{
17970 enum neon_shape rs = neon_select_shape (NS_RRQQ, NS_NULL);
17971 struct neon_type_el et
17972 = neon_check_type (4, rs, N_EQK, N_EQK, N_EQK,
17973 N_S16 | N_S32 | N_U16 | N_U32 | N_KEY);
17974
17975 if (et.type == NT_unsigned
17976 && (inst.instruction == M_MNEM_vmlsldav
17977 || inst.instruction == M_MNEM_vmlsldava
17978 || inst.instruction == M_MNEM_vmlsldavx
17979 || inst.instruction == M_MNEM_vmlsldavax))
17980 first_error (BAD_SIMD_TYPE);
17981
17982 if (inst.cond > COND_ALWAYS)
17983 inst.pred_insn_type = INSIDE_VPT_INSN;
17984 else
17985 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17986
17987 mve_encode_rrqq (et.type == NT_unsigned, et.size);
17988}
17989
17990static void
17991do_mve_vrmlaldavh (void)
17992{
17993 struct neon_type_el et;
17994 if (inst.instruction == M_MNEM_vrmlsldavh
17995 || inst.instruction == M_MNEM_vrmlsldavha
17996 || inst.instruction == M_MNEM_vrmlsldavhx
17997 || inst.instruction == M_MNEM_vrmlsldavhax)
17998 {
17999 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
18000 if (inst.operands[1].reg == REG_SP)
18001 as_tsktsk (MVE_BAD_SP);
18002 }
18003 else
18004 {
18005 if (inst.instruction == M_MNEM_vrmlaldavhx
18006 || inst.instruction == M_MNEM_vrmlaldavhax)
18007 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
18008 else
18009 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK,
18010 N_U32 | N_S32 | N_KEY);
18011 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18012 with vmax/min instructions, making the use of SP in assembly really
18013 nonsensical, so instead of issuing a warning like we do for other uses
18014 of SP for the odd register operand we error out. */
18015 constraint (inst.operands[1].reg == REG_SP, BAD_SP);
18016 }
18017
18018 /* Make sure we still check the second operand is an odd one and that PC is
18019 disallowed. This because we are parsing for any GPR operand, to be able
18020 to distinguish between giving a warning or an error for SP as described
18021 above. */
18022 constraint ((inst.operands[1].reg % 2) != 1, BAD_EVEN);
18023 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
18024
18025 if (inst.cond > COND_ALWAYS)
18026 inst.pred_insn_type = INSIDE_VPT_INSN;
18027 else
18028 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18029
18030 mve_encode_rrqq (et.type == NT_unsigned, 0);
18031}
18032
18033
8cd78170
AV
18034static void
18035do_mve_vmaxnmv (void)
18036{
18037 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
18038 struct neon_type_el et
18039 = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
18040
18041 if (inst.cond > COND_ALWAYS)
18042 inst.pred_insn_type = INSIDE_VPT_INSN;
18043 else
18044 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18045
18046 if (inst.operands[0].reg == REG_SP)
18047 as_tsktsk (MVE_BAD_SP);
18048 else if (inst.operands[0].reg == REG_PC)
18049 as_tsktsk (MVE_BAD_PC);
18050
18051 mve_encode_rq (et.size == 16, 64);
18052}
18053
13ccd4c0
AV
18054static void
18055do_mve_vmaxv (void)
18056{
18057 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
18058 struct neon_type_el et;
18059
18060 if (inst.instruction == M_MNEM_vmaxv || inst.instruction == M_MNEM_vminv)
18061 et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY);
18062 else
18063 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18064
18065 if (inst.cond > COND_ALWAYS)
18066 inst.pred_insn_type = INSIDE_VPT_INSN;
18067 else
18068 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18069
18070 if (inst.operands[0].reg == REG_SP)
18071 as_tsktsk (MVE_BAD_SP);
18072 else if (inst.operands[0].reg == REG_PC)
18073 as_tsktsk (MVE_BAD_PC);
18074
18075 mve_encode_rq (et.type == NT_unsigned, et.size);
18076}
18077
18078
643afb90
MW
18079static void
18080do_neon_qrdmlah (void)
18081{
64c350f2 18082 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
42b16635
AV
18083 return;
18084 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
643afb90 18085 {
42b16635
AV
18086 /* Check we're on the correct architecture. */
18087 if (!mark_feature_used (&fpu_neon_ext_armv8))
18088 inst.error
18089 = _("instruction form not available on this architecture.");
18090 else if (!mark_feature_used (&fpu_neon_ext_v8_1))
18091 {
18092 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18093 record_feature_use (&fpu_neon_ext_v8_1);
18094 }
18095 if (inst.operands[2].isscalar)
18096 {
18097 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
18098 struct neon_type_el et = neon_check_type (3, rs,
18099 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18100 NEON_ENCODE (SCALAR, inst);
18101 neon_mul_mac (et, neon_quad (rs));
18102 }
18103 else
18104 {
18105 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
18106 struct neon_type_el et = neon_check_type (3, rs,
18107 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18108 NEON_ENCODE (INTEGER, inst);
18109 /* The U bit (rounding) comes from bit mask. */
18110 neon_three_same (neon_quad (rs), 0, et.size);
18111 }
643afb90
MW
18112 }
18113 else
18114 {
42b16635
AV
18115 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
18116 struct neon_type_el et
18117 = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
18118
643afb90 18119 NEON_ENCODE (INTEGER, inst);
42b16635 18120 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
643afb90
MW
18121 }
18122}
18123
5287ad62
JB
18124static void
18125do_neon_fcmp_absolute (void)
18126{
037e8744 18127 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
cc933301
JW
18128 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
18129 N_F_16_32 | N_KEY);
5287ad62 18130 /* Size field comes from bit mask. */
cc933301 18131 neon_three_same (neon_quad (rs), 1, et.size == 16 ? (int) et.size : -1);
5287ad62
JB
18132}
18133
18134static void
18135do_neon_fcmp_absolute_inv (void)
18136{
18137 neon_exchange_operands ();
18138 do_neon_fcmp_absolute ();
18139}
18140
18141static void
18142do_neon_step (void)
18143{
037e8744 18144 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
cc933301
JW
18145 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
18146 N_F_16_32 | N_KEY);
18147 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
5287ad62
JB
18148}
18149
18150static void
18151do_neon_abs_neg (void)
18152{
037e8744
JB
18153 enum neon_shape rs;
18154 struct neon_type_el et;
5f4273c7 18155
037e8744
JB
18156 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
18157 return;
18158
037e8744 18159 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
cc933301 18160 et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY);
5f4273c7 18161
64c350f2
AV
18162 if (!check_simd_pred_availability (et.type == NT_float,
18163 NEON_CHECK_ARCH | NEON_CHECK_CC))
485dee97
AV
18164 return;
18165
5287ad62
JB
18166 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18167 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18168 inst.instruction |= LOW4 (inst.operands[1].reg);
18169 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 18170 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB
18171 inst.instruction |= (et.type == NT_float) << 10;
18172 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 18173
88714cb8 18174 neon_dp_fixup (&inst);
5287ad62
JB
18175}
18176
18177static void
18178do_neon_sli (void)
18179{
64c350f2 18180 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
4401c241
AV
18181 return;
18182
18183 enum neon_shape rs;
18184 struct neon_type_el et;
18185 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18186 {
18187 rs = neon_select_shape (NS_QQI, NS_NULL);
18188 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY);
18189 }
18190 else
18191 {
18192 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18193 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
18194 }
18195
18196
5287ad62
JB
18197 int imm = inst.operands[2].imm;
18198 constraint (imm < 0 || (unsigned)imm >= et.size,
477330fc 18199 _("immediate out of range for insert"));
037e8744 18200 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB
18201}
18202
18203static void
18204do_neon_sri (void)
18205{
64c350f2 18206 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
4401c241
AV
18207 return;
18208
18209 enum neon_shape rs;
18210 struct neon_type_el et;
18211 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18212 {
18213 rs = neon_select_shape (NS_QQI, NS_NULL);
18214 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY);
18215 }
18216 else
18217 {
18218 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18219 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
18220 }
18221
5287ad62
JB
18222 int imm = inst.operands[2].imm;
18223 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 18224 _("immediate out of range for insert"));
037e8744 18225 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
5287ad62
JB
18226}
18227
18228static void
18229do_neon_qshlu_imm (void)
18230{
64c350f2 18231 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
5150f0d8
AV
18232 return;
18233
18234 enum neon_shape rs;
18235 struct neon_type_el et;
18236 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18237 {
18238 rs = neon_select_shape (NS_QQI, NS_NULL);
18239 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18240 }
18241 else
18242 {
18243 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18244 et = neon_check_type (2, rs, N_EQK | N_UNS,
18245 N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
18246 }
18247
5287ad62
JB
18248 int imm = inst.operands[2].imm;
18249 constraint (imm < 0 || (unsigned)imm >= et.size,
477330fc 18250 _("immediate out of range for shift"));
5287ad62
JB
18251 /* Only encodes the 'U present' variant of the instruction.
18252 In this case, signed types have OP (bit 8) set to 0.
18253 Unsigned types have OP set to 1. */
18254 inst.instruction |= (et.type == NT_unsigned) << 8;
18255 /* The rest of the bits are the same as other immediate shifts. */
037e8744 18256 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB
18257}
18258
18259static void
18260do_neon_qmovn (void)
18261{
18262 struct neon_type_el et = neon_check_type (2, NS_DQ,
18263 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
18264 /* Saturating move where operands can be signed or unsigned, and the
18265 destination has the same signedness. */
88714cb8 18266 NEON_ENCODE (INTEGER, inst);
5287ad62
JB
18267 if (et.type == NT_unsigned)
18268 inst.instruction |= 0xc0;
18269 else
18270 inst.instruction |= 0x80;
18271 neon_two_same (0, 1, et.size / 2);
18272}
18273
18274static void
18275do_neon_qmovun (void)
18276{
18277 struct neon_type_el et = neon_check_type (2, NS_DQ,
18278 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
18279 /* Saturating move with unsigned results. Operands must be signed. */
88714cb8 18280 NEON_ENCODE (INTEGER, inst);
5287ad62
JB
18281 neon_two_same (0, 1, et.size / 2);
18282}
18283
18284static void
18285do_neon_rshift_sat_narrow (void)
18286{
18287 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18288 or unsigned. If operands are unsigned, results must also be unsigned. */
18289 struct neon_type_el et = neon_check_type (2, NS_DQI,
18290 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
18291 int imm = inst.operands[2].imm;
18292 /* This gets the bounds check, size encoding and immediate bits calculation
18293 right. */
18294 et.size /= 2;
5f4273c7 18295
5287ad62
JB
18296 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18297 VQMOVN.I<size> <Dd>, <Qm>. */
18298 if (imm == 0)
18299 {
18300 inst.operands[2].present = 0;
18301 inst.instruction = N_MNEM_vqmovn;
18302 do_neon_qmovn ();
18303 return;
18304 }
5f4273c7 18305
5287ad62 18306 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 18307 _("immediate out of range"));
5287ad62
JB
18308 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
18309}
18310
18311static void
18312do_neon_rshift_sat_narrow_u (void)
18313{
18314 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18315 or unsigned. If operands are unsigned, results must also be unsigned. */
18316 struct neon_type_el et = neon_check_type (2, NS_DQI,
18317 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
18318 int imm = inst.operands[2].imm;
18319 /* This gets the bounds check, size encoding and immediate bits calculation
18320 right. */
18321 et.size /= 2;
18322
18323 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18324 VQMOVUN.I<size> <Dd>, <Qm>. */
18325 if (imm == 0)
18326 {
18327 inst.operands[2].present = 0;
18328 inst.instruction = N_MNEM_vqmovun;
18329 do_neon_qmovun ();
18330 return;
18331 }
18332
18333 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 18334 _("immediate out of range"));
5287ad62
JB
18335 /* FIXME: The manual is kind of unclear about what value U should have in
18336 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18337 must be 1. */
18338 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
18339}
18340
18341static void
18342do_neon_movn (void)
18343{
18344 struct neon_type_el et = neon_check_type (2, NS_DQ,
18345 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
88714cb8 18346 NEON_ENCODE (INTEGER, inst);
5287ad62
JB
18347 neon_two_same (0, 1, et.size / 2);
18348}
18349
18350static void
18351do_neon_rshift_narrow (void)
18352{
18353 struct neon_type_el et = neon_check_type (2, NS_DQI,
18354 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
18355 int imm = inst.operands[2].imm;
18356 /* This gets the bounds check, size encoding and immediate bits calculation
18357 right. */
18358 et.size /= 2;
5f4273c7 18359
5287ad62
JB
18360 /* If immediate is zero then we are a pseudo-instruction for
18361 VMOVN.I<size> <Dd>, <Qm> */
18362 if (imm == 0)
18363 {
18364 inst.operands[2].present = 0;
18365 inst.instruction = N_MNEM_vmovn;
18366 do_neon_movn ();
18367 return;
18368 }
5f4273c7 18369
5287ad62 18370 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 18371 _("immediate out of range for narrowing operation"));
5287ad62
JB
18372 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
18373}
18374
18375static void
18376do_neon_shll (void)
18377{
18378 /* FIXME: Type checking when lengthening. */
18379 struct neon_type_el et = neon_check_type (2, NS_QDI,
18380 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
18381 unsigned imm = inst.operands[2].imm;
18382
18383 if (imm == et.size)
18384 {
18385 /* Maximum shift variant. */
88714cb8 18386 NEON_ENCODE (INTEGER, inst);
5287ad62
JB
18387 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18388 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18389 inst.instruction |= LOW4 (inst.operands[1].reg);
18390 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18391 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 18392
88714cb8 18393 neon_dp_fixup (&inst);
5287ad62
JB
18394 }
18395 else
18396 {
18397 /* A more-specific type check for non-max versions. */
18398 et = neon_check_type (2, NS_QDI,
477330fc 18399 N_EQK | N_DBL, N_SU_32 | N_KEY);
88714cb8 18400 NEON_ENCODE (IMMED, inst);
5287ad62
JB
18401 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
18402 }
18403}
18404
037e8744 18405/* Check the various types for the VCVT instruction, and return which version
5287ad62
JB
18406 the current instruction is. */
18407
6b9a8b67
MGD
18408#define CVT_FLAVOUR_VAR \
18409 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18410 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18411 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18412 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18413 /* Half-precision conversions. */ \
cc933301
JW
18414 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18415 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18416 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18417 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
6b9a8b67
MGD
18418 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18419 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
9db2f6b4
RL
18420 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18421 Compared with single/double precision variants, only the co-processor \
18422 field is different, so the encoding flow is reused here. */ \
18423 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18424 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18425 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18426 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
6b9a8b67
MGD
18427 /* VFP instructions. */ \
18428 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18429 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18430 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18431 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18432 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18433 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18434 /* VFP instructions with bitshift. */ \
18435 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18436 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18437 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18438 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18439 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18440 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18441 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18442 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18443
18444#define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18445 neon_cvt_flavour_##C,
18446
18447/* The different types of conversions we can do. */
18448enum neon_cvt_flavour
18449{
18450 CVT_FLAVOUR_VAR
18451 neon_cvt_flavour_invalid,
18452 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
18453};
18454
18455#undef CVT_VAR
18456
18457static enum neon_cvt_flavour
18458get_neon_cvt_flavour (enum neon_shape rs)
5287ad62 18459{
6b9a8b67
MGD
18460#define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18461 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18462 if (et.type != NT_invtype) \
18463 { \
18464 inst.error = NULL; \
18465 return (neon_cvt_flavour_##C); \
5287ad62 18466 }
6b9a8b67 18467
5287ad62 18468 struct neon_type_el et;
037e8744 18469 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
477330fc 18470 || rs == NS_FF) ? N_VFP : 0;
037e8744
JB
18471 /* The instruction versions which take an immediate take one register
18472 argument, which is extended to the width of the full register. Thus the
18473 "source" and "destination" registers must have the same width. Hack that
18474 here by making the size equal to the key (wider, in this case) operand. */
18475 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
5f4273c7 18476
6b9a8b67
MGD
18477 CVT_FLAVOUR_VAR;
18478
18479 return neon_cvt_flavour_invalid;
5287ad62
JB
18480#undef CVT_VAR
18481}
18482
7e8e6784
MGD
18483enum neon_cvt_mode
18484{
18485 neon_cvt_mode_a,
18486 neon_cvt_mode_n,
18487 neon_cvt_mode_p,
18488 neon_cvt_mode_m,
18489 neon_cvt_mode_z,
30bdf752
MGD
18490 neon_cvt_mode_x,
18491 neon_cvt_mode_r
7e8e6784
MGD
18492};
18493
037e8744
JB
18494/* Neon-syntax VFP conversions. */
18495
5287ad62 18496static void
6b9a8b67 18497do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
5287ad62 18498{
037e8744 18499 const char *opname = 0;
5f4273c7 18500
d54af2d0
RL
18501 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI
18502 || rs == NS_FHI || rs == NS_HFI)
5287ad62 18503 {
037e8744
JB
18504 /* Conversions with immediate bitshift. */
18505 const char *enc[] =
477330fc 18506 {
6b9a8b67
MGD
18507#define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18508 CVT_FLAVOUR_VAR
18509 NULL
18510#undef CVT_VAR
477330fc 18511 };
037e8744 18512
6b9a8b67 18513 if (flavour < (int) ARRAY_SIZE (enc))
477330fc
RM
18514 {
18515 opname = enc[flavour];
18516 constraint (inst.operands[0].reg != inst.operands[1].reg,
18517 _("operands 0 and 1 must be the same register"));
18518 inst.operands[1] = inst.operands[2];
18519 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
18520 }
5287ad62
JB
18521 }
18522 else
18523 {
037e8744
JB
18524 /* Conversions without bitshift. */
18525 const char *enc[] =
477330fc 18526 {
6b9a8b67
MGD
18527#define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18528 CVT_FLAVOUR_VAR
18529 NULL
18530#undef CVT_VAR
477330fc 18531 };
037e8744 18532
6b9a8b67 18533 if (flavour < (int) ARRAY_SIZE (enc))
477330fc 18534 opname = enc[flavour];
037e8744
JB
18535 }
18536
18537 if (opname)
18538 do_vfp_nsyn_opcode (opname);
9db2f6b4
RL
18539
18540 /* ARMv8.2 fp16 VCVT instruction. */
18541 if (flavour == neon_cvt_flavour_s32_f16
18542 || flavour == neon_cvt_flavour_u32_f16
18543 || flavour == neon_cvt_flavour_f16_u32
18544 || flavour == neon_cvt_flavour_f16_s32)
18545 do_scalar_fp16_v82_encode ();
037e8744
JB
18546}
18547
18548static void
18549do_vfp_nsyn_cvtz (void)
18550{
d54af2d0 18551 enum neon_shape rs = neon_select_shape (NS_FH, NS_FF, NS_FD, NS_NULL);
6b9a8b67 18552 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
037e8744
JB
18553 const char *enc[] =
18554 {
6b9a8b67
MGD
18555#define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18556 CVT_FLAVOUR_VAR
18557 NULL
18558#undef CVT_VAR
037e8744
JB
18559 };
18560
6b9a8b67 18561 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
037e8744
JB
18562 do_vfp_nsyn_opcode (enc[flavour]);
18563}
f31fef98 18564
037e8744 18565static void
bacebabc 18566do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
7e8e6784
MGD
18567 enum neon_cvt_mode mode)
18568{
18569 int sz, op;
18570 int rm;
18571
a715796b
TG
18572 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18573 D register operands. */
18574 if (flavour == neon_cvt_flavour_s32_f64
18575 || flavour == neon_cvt_flavour_u32_f64)
18576 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
18577 _(BAD_FPU));
18578
9db2f6b4
RL
18579 if (flavour == neon_cvt_flavour_s32_f16
18580 || flavour == neon_cvt_flavour_u32_f16)
18581 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
18582 _(BAD_FP16));
18583
5ee91343 18584 set_pred_insn_type (OUTSIDE_PRED_INSN);
7e8e6784
MGD
18585
18586 switch (flavour)
18587 {
18588 case neon_cvt_flavour_s32_f64:
18589 sz = 1;
827f64ff 18590 op = 1;
7e8e6784
MGD
18591 break;
18592 case neon_cvt_flavour_s32_f32:
18593 sz = 0;
18594 op = 1;
18595 break;
9db2f6b4
RL
18596 case neon_cvt_flavour_s32_f16:
18597 sz = 0;
18598 op = 1;
18599 break;
7e8e6784
MGD
18600 case neon_cvt_flavour_u32_f64:
18601 sz = 1;
18602 op = 0;
18603 break;
18604 case neon_cvt_flavour_u32_f32:
18605 sz = 0;
18606 op = 0;
18607 break;
9db2f6b4
RL
18608 case neon_cvt_flavour_u32_f16:
18609 sz = 0;
18610 op = 0;
18611 break;
7e8e6784
MGD
18612 default:
18613 first_error (_("invalid instruction shape"));
18614 return;
18615 }
18616
18617 switch (mode)
18618 {
18619 case neon_cvt_mode_a: rm = 0; break;
18620 case neon_cvt_mode_n: rm = 1; break;
18621 case neon_cvt_mode_p: rm = 2; break;
18622 case neon_cvt_mode_m: rm = 3; break;
18623 default: first_error (_("invalid rounding mode")); return;
18624 }
18625
18626 NEON_ENCODE (FPV8, inst);
18627 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
18628 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
18629 inst.instruction |= sz << 8;
9db2f6b4
RL
18630
18631 /* ARMv8.2 fp16 VCVT instruction. */
18632 if (flavour == neon_cvt_flavour_s32_f16
18633 ||flavour == neon_cvt_flavour_u32_f16)
18634 do_scalar_fp16_v82_encode ();
7e8e6784
MGD
18635 inst.instruction |= op << 7;
18636 inst.instruction |= rm << 16;
18637 inst.instruction |= 0xf0000000;
18638 inst.is_neon = TRUE;
18639}
18640
18641static void
18642do_neon_cvt_1 (enum neon_cvt_mode mode)
037e8744
JB
18643{
18644 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
d54af2d0
RL
18645 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ,
18646 NS_FH, NS_HF, NS_FHI, NS_HFI,
18647 NS_NULL);
6b9a8b67 18648 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
037e8744 18649
cc933301
JW
18650 if (flavour == neon_cvt_flavour_invalid)
18651 return;
18652
e3e535bc 18653 /* PR11109: Handle round-to-zero for VCVT conversions. */
7e8e6784 18654 if (mode == neon_cvt_mode_z
e3e535bc 18655 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
cc933301
JW
18656 && (flavour == neon_cvt_flavour_s16_f16
18657 || flavour == neon_cvt_flavour_u16_f16
18658 || flavour == neon_cvt_flavour_s32_f32
bacebabc
RM
18659 || flavour == neon_cvt_flavour_u32_f32
18660 || flavour == neon_cvt_flavour_s32_f64
6b9a8b67 18661 || flavour == neon_cvt_flavour_u32_f64)
e3e535bc
NC
18662 && (rs == NS_FD || rs == NS_FF))
18663 {
18664 do_vfp_nsyn_cvtz ();
18665 return;
18666 }
18667
9db2f6b4
RL
18668 /* ARMv8.2 fp16 VCVT conversions. */
18669 if (mode == neon_cvt_mode_z
18670 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)
18671 && (flavour == neon_cvt_flavour_s32_f16
18672 || flavour == neon_cvt_flavour_u32_f16)
18673 && (rs == NS_FH))
18674 {
18675 do_vfp_nsyn_cvtz ();
18676 do_scalar_fp16_v82_encode ();
18677 return;
18678 }
18679
037e8744 18680 /* VFP rather than Neon conversions. */
6b9a8b67 18681 if (flavour >= neon_cvt_flavour_first_fp)
037e8744 18682 {
7e8e6784
MGD
18683 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
18684 do_vfp_nsyn_cvt (rs, flavour);
18685 else
18686 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
18687
037e8744
JB
18688 return;
18689 }
18690
18691 switch (rs)
18692 {
037e8744 18693 case NS_QQI:
dd9634d9
AV
18694 if (mode == neon_cvt_mode_z
18695 && (flavour == neon_cvt_flavour_f16_s16
18696 || flavour == neon_cvt_flavour_f16_u16
18697 || flavour == neon_cvt_flavour_s16_f16
18698 || flavour == neon_cvt_flavour_u16_f16
18699 || flavour == neon_cvt_flavour_f32_u32
18700 || flavour == neon_cvt_flavour_f32_s32
18701 || flavour == neon_cvt_flavour_s32_f32
18702 || flavour == neon_cvt_flavour_u32_f32))
18703 {
64c350f2
AV
18704 if (!check_simd_pred_availability (TRUE,
18705 NEON_CHECK_CC | NEON_CHECK_ARCH))
dd9634d9
AV
18706 return;
18707 }
18708 else if (mode == neon_cvt_mode_n)
18709 {
18710 /* We are dealing with vcvt with the 'ne' condition. */
18711 inst.cond = 0x1;
18712 inst.instruction = N_MNEM_vcvt;
18713 do_neon_cvt_1 (neon_cvt_mode_z);
18714 return;
18715 }
18716 /* fall through. */
18717 case NS_DDI:
037e8744 18718 {
477330fc 18719 unsigned immbits;
cc933301
JW
18720 unsigned enctab[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
18721 0x0000100, 0x1000100, 0x0, 0x1000000};
35997600 18722
dd9634d9
AV
18723 if ((rs != NS_QQI || !ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
18724 && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
18725 return;
18726
18727 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
18728 {
18729 constraint (inst.operands[2].present && inst.operands[2].imm == 0,
18730 _("immediate value out of range"));
18731 switch (flavour)
18732 {
18733 case neon_cvt_flavour_f16_s16:
18734 case neon_cvt_flavour_f16_u16:
18735 case neon_cvt_flavour_s16_f16:
18736 case neon_cvt_flavour_u16_f16:
18737 constraint (inst.operands[2].imm > 16,
18738 _("immediate value out of range"));
18739 break;
18740 case neon_cvt_flavour_f32_u32:
18741 case neon_cvt_flavour_f32_s32:
18742 case neon_cvt_flavour_s32_f32:
18743 case neon_cvt_flavour_u32_f32:
18744 constraint (inst.operands[2].imm > 32,
18745 _("immediate value out of range"));
18746 break;
18747 default:
18748 inst.error = BAD_FPU;
18749 return;
18750 }
18751 }
037e8744 18752
477330fc
RM
18753 /* Fixed-point conversion with #0 immediate is encoded as an
18754 integer conversion. */
18755 if (inst.operands[2].present && inst.operands[2].imm == 0)
18756 goto int_encode;
477330fc
RM
18757 NEON_ENCODE (IMMED, inst);
18758 if (flavour != neon_cvt_flavour_invalid)
18759 inst.instruction |= enctab[flavour];
18760 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18761 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18762 inst.instruction |= LOW4 (inst.operands[1].reg);
18763 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18764 inst.instruction |= neon_quad (rs) << 6;
18765 inst.instruction |= 1 << 21;
cc933301
JW
18766 if (flavour < neon_cvt_flavour_s16_f16)
18767 {
18768 inst.instruction |= 1 << 21;
18769 immbits = 32 - inst.operands[2].imm;
18770 inst.instruction |= immbits << 16;
18771 }
18772 else
18773 {
18774 inst.instruction |= 3 << 20;
18775 immbits = 16 - inst.operands[2].imm;
18776 inst.instruction |= immbits << 16;
18777 inst.instruction &= ~(1 << 9);
18778 }
477330fc
RM
18779
18780 neon_dp_fixup (&inst);
037e8744
JB
18781 }
18782 break;
18783
037e8744 18784 case NS_QQ:
dd9634d9
AV
18785 if ((mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
18786 || mode == neon_cvt_mode_m || mode == neon_cvt_mode_p)
18787 && (flavour == neon_cvt_flavour_s16_f16
18788 || flavour == neon_cvt_flavour_u16_f16
18789 || flavour == neon_cvt_flavour_s32_f32
18790 || flavour == neon_cvt_flavour_u32_f32))
18791 {
64c350f2
AV
18792 if (!check_simd_pred_availability (TRUE,
18793 NEON_CHECK_CC | NEON_CHECK_ARCH8))
dd9634d9
AV
18794 return;
18795 }
18796 else if (mode == neon_cvt_mode_z
18797 && (flavour == neon_cvt_flavour_f16_s16
18798 || flavour == neon_cvt_flavour_f16_u16
18799 || flavour == neon_cvt_flavour_s16_f16
18800 || flavour == neon_cvt_flavour_u16_f16
18801 || flavour == neon_cvt_flavour_f32_u32
18802 || flavour == neon_cvt_flavour_f32_s32
18803 || flavour == neon_cvt_flavour_s32_f32
18804 || flavour == neon_cvt_flavour_u32_f32))
18805 {
64c350f2
AV
18806 if (!check_simd_pred_availability (TRUE,
18807 NEON_CHECK_CC | NEON_CHECK_ARCH))
dd9634d9
AV
18808 return;
18809 }
18810 /* fall through. */
18811 case NS_DD:
7e8e6784
MGD
18812 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
18813 {
7e8e6784 18814
dd9634d9 18815 NEON_ENCODE (FLOAT, inst);
64c350f2
AV
18816 if (!check_simd_pred_availability (TRUE,
18817 NEON_CHECK_CC | NEON_CHECK_ARCH8))
7e8e6784
MGD
18818 return;
18819
18820 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18821 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18822 inst.instruction |= LOW4 (inst.operands[1].reg);
18823 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18824 inst.instruction |= neon_quad (rs) << 6;
cc933301
JW
18825 inst.instruction |= (flavour == neon_cvt_flavour_u16_f16
18826 || flavour == neon_cvt_flavour_u32_f32) << 7;
7e8e6784 18827 inst.instruction |= mode << 8;
cc933301
JW
18828 if (flavour == neon_cvt_flavour_u16_f16
18829 || flavour == neon_cvt_flavour_s16_f16)
18830 /* Mask off the original size bits and reencode them. */
18831 inst.instruction = ((inst.instruction & 0xfff3ffff) | (1 << 18));
18832
7e8e6784
MGD
18833 if (thumb_mode)
18834 inst.instruction |= 0xfc000000;
18835 else
18836 inst.instruction |= 0xf0000000;
18837 }
18838 else
18839 {
037e8744 18840 int_encode:
7e8e6784 18841 {
cc933301
JW
18842 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080,
18843 0x100, 0x180, 0x0, 0x080};
037e8744 18844
7e8e6784 18845 NEON_ENCODE (INTEGER, inst);
037e8744 18846
dd9634d9
AV
18847 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
18848 {
18849 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
18850 return;
18851 }
037e8744 18852
7e8e6784
MGD
18853 if (flavour != neon_cvt_flavour_invalid)
18854 inst.instruction |= enctab[flavour];
037e8744 18855
7e8e6784
MGD
18856 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18857 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18858 inst.instruction |= LOW4 (inst.operands[1].reg);
18859 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18860 inst.instruction |= neon_quad (rs) << 6;
cc933301
JW
18861 if (flavour >= neon_cvt_flavour_s16_f16
18862 && flavour <= neon_cvt_flavour_f16_u16)
18863 /* Half precision. */
18864 inst.instruction |= 1 << 18;
18865 else
18866 inst.instruction |= 2 << 18;
037e8744 18867
7e8e6784
MGD
18868 neon_dp_fixup (&inst);
18869 }
18870 }
18871 break;
037e8744 18872
8e79c3df
CM
18873 /* Half-precision conversions for Advanced SIMD -- neon. */
18874 case NS_QD:
18875 case NS_DQ:
bc52d49c
MM
18876 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
18877 return;
8e79c3df
CM
18878
18879 if ((rs == NS_DQ)
18880 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
18881 {
18882 as_bad (_("operand size must match register width"));
18883 break;
18884 }
18885
18886 if ((rs == NS_QD)
18887 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
18888 {
18889 as_bad (_("operand size must match register width"));
18890 break;
18891 }
18892
18893 if (rs == NS_DQ)
477330fc 18894 inst.instruction = 0x3b60600;
8e79c3df
CM
18895 else
18896 inst.instruction = 0x3b60700;
18897
18898 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18899 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18900 inst.instruction |= LOW4 (inst.operands[1].reg);
18901 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
88714cb8 18902 neon_dp_fixup (&inst);
8e79c3df
CM
18903 break;
18904
037e8744
JB
18905 default:
18906 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
7e8e6784
MGD
18907 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
18908 do_vfp_nsyn_cvt (rs, flavour);
18909 else
18910 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
5287ad62 18911 }
5287ad62
JB
18912}
18913
e3e535bc
NC
18914static void
18915do_neon_cvtr (void)
18916{
7e8e6784 18917 do_neon_cvt_1 (neon_cvt_mode_x);
e3e535bc
NC
18918}
18919
18920static void
18921do_neon_cvt (void)
18922{
7e8e6784
MGD
18923 do_neon_cvt_1 (neon_cvt_mode_z);
18924}
18925
18926static void
18927do_neon_cvta (void)
18928{
18929 do_neon_cvt_1 (neon_cvt_mode_a);
18930}
18931
18932static void
18933do_neon_cvtn (void)
18934{
18935 do_neon_cvt_1 (neon_cvt_mode_n);
18936}
18937
18938static void
18939do_neon_cvtp (void)
18940{
18941 do_neon_cvt_1 (neon_cvt_mode_p);
18942}
18943
18944static void
18945do_neon_cvtm (void)
18946{
18947 do_neon_cvt_1 (neon_cvt_mode_m);
e3e535bc
NC
18948}
18949
8e79c3df 18950static void
c70a8987 18951do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
8e79c3df 18952{
c70a8987
MGD
18953 if (is_double)
18954 mark_feature_used (&fpu_vfp_ext_armv8);
8e79c3df 18955
c70a8987
MGD
18956 encode_arm_vfp_reg (inst.operands[0].reg,
18957 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
18958 encode_arm_vfp_reg (inst.operands[1].reg,
18959 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
18960 inst.instruction |= to ? 0x10000 : 0;
18961 inst.instruction |= t ? 0x80 : 0;
18962 inst.instruction |= is_double ? 0x100 : 0;
18963 do_vfp_cond_or_thumb ();
18964}
8e79c3df 18965
c70a8987
MGD
18966static void
18967do_neon_cvttb_1 (bfd_boolean t)
18968{
d54af2d0 18969 enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD,
dd9634d9 18970 NS_DF, NS_DH, NS_QQ, NS_QQI, NS_NULL);
8e79c3df 18971
c70a8987
MGD
18972 if (rs == NS_NULL)
18973 return;
dd9634d9
AV
18974 else if (rs == NS_QQ || rs == NS_QQI)
18975 {
18976 int single_to_half = 0;
64c350f2 18977 if (!check_simd_pred_availability (TRUE, NEON_CHECK_ARCH))
dd9634d9
AV
18978 return;
18979
18980 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
18981
18982 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
18983 && (flavour == neon_cvt_flavour_u16_f16
18984 || flavour == neon_cvt_flavour_s16_f16
18985 || flavour == neon_cvt_flavour_f16_s16
18986 || flavour == neon_cvt_flavour_f16_u16
18987 || flavour == neon_cvt_flavour_u32_f32
18988 || flavour == neon_cvt_flavour_s32_f32
18989 || flavour == neon_cvt_flavour_f32_s32
18990 || flavour == neon_cvt_flavour_f32_u32))
18991 {
18992 inst.cond = 0xf;
18993 inst.instruction = N_MNEM_vcvt;
18994 set_pred_insn_type (INSIDE_VPT_INSN);
18995 do_neon_cvt_1 (neon_cvt_mode_z);
18996 return;
18997 }
18998 else if (rs == NS_QQ && flavour == neon_cvt_flavour_f32_f16)
18999 single_to_half = 1;
19000 else if (rs == NS_QQ && flavour != neon_cvt_flavour_f16_f32)
19001 {
19002 first_error (BAD_FPU);
19003 return;
19004 }
19005
19006 inst.instruction = 0xee3f0e01;
19007 inst.instruction |= single_to_half << 28;
19008 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19009 inst.instruction |= LOW4 (inst.operands[0].reg) << 13;
19010 inst.instruction |= t << 12;
19011 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19012 inst.instruction |= LOW4 (inst.operands[1].reg) << 1;
19013 inst.is_neon = 1;
19014 }
c70a8987
MGD
19015 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
19016 {
19017 inst.error = NULL;
19018 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
19019 }
19020 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
19021 {
19022 inst.error = NULL;
19023 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
19024 }
19025 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
19026 {
a715796b
TG
19027 /* The VCVTB and VCVTT instructions with D-register operands
19028 don't work for SP only targets. */
19029 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
19030 _(BAD_FPU));
19031
c70a8987
MGD
19032 inst.error = NULL;
19033 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
19034 }
19035 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
19036 {
a715796b
TG
19037 /* The VCVTB and VCVTT instructions with D-register operands
19038 don't work for SP only targets. */
19039 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
19040 _(BAD_FPU));
19041
c70a8987
MGD
19042 inst.error = NULL;
19043 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
19044 }
19045 else
19046 return;
19047}
19048
19049static void
19050do_neon_cvtb (void)
19051{
19052 do_neon_cvttb_1 (FALSE);
8e79c3df
CM
19053}
19054
19055
19056static void
19057do_neon_cvtt (void)
19058{
c70a8987 19059 do_neon_cvttb_1 (TRUE);
8e79c3df
CM
19060}
19061
5287ad62
JB
19062static void
19063neon_move_immediate (void)
19064{
037e8744
JB
19065 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
19066 struct neon_type_el et = neon_check_type (2, rs,
19067 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
5287ad62 19068 unsigned immlo, immhi = 0, immbits;
c96612cc 19069 int op, cmode, float_p;
5287ad62 19070
037e8744 19071 constraint (et.type == NT_invtype,
477330fc 19072 _("operand size must be specified for immediate VMOV"));
037e8744 19073
5287ad62
JB
19074 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19075 op = (inst.instruction & (1 << 5)) != 0;
19076
19077 immlo = inst.operands[1].imm;
19078 if (inst.operands[1].regisimm)
19079 immhi = inst.operands[1].reg;
19080
19081 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
477330fc 19082 _("immediate has bits set outside the operand size"));
5287ad62 19083
c96612cc
JB
19084 float_p = inst.operands[1].immisfloat;
19085
19086 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
477330fc 19087 et.size, et.type)) == FAIL)
5287ad62
JB
19088 {
19089 /* Invert relevant bits only. */
19090 neon_invert_size (&immlo, &immhi, et.size);
19091 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
477330fc
RM
19092 with one or the other; those cases are caught by
19093 neon_cmode_for_move_imm. */
5287ad62 19094 op = !op;
c96612cc
JB
19095 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
19096 &op, et.size, et.type)) == FAIL)
477330fc
RM
19097 {
19098 first_error (_("immediate out of range"));
19099 return;
19100 }
5287ad62
JB
19101 }
19102
19103 inst.instruction &= ~(1 << 5);
19104 inst.instruction |= op << 5;
19105
19106 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19107 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
037e8744 19108 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB
19109 inst.instruction |= cmode << 8;
19110
19111 neon_write_immbits (immbits);
19112}
19113
19114static void
19115do_neon_mvn (void)
19116{
64c350f2 19117 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
1a186d29
AV
19118 return;
19119
5287ad62
JB
19120 if (inst.operands[1].isreg)
19121 {
1a186d29
AV
19122 enum neon_shape rs;
19123 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19124 rs = neon_select_shape (NS_QQ, NS_NULL);
19125 else
19126 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5f4273c7 19127
88714cb8 19128 NEON_ENCODE (INTEGER, inst);
5287ad62
JB
19129 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19130 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19131 inst.instruction |= LOW4 (inst.operands[1].reg);
19132 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 19133 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB
19134 }
19135 else
19136 {
88714cb8 19137 NEON_ENCODE (IMMED, inst);
5287ad62
JB
19138 neon_move_immediate ();
19139 }
19140
88714cb8 19141 neon_dp_fixup (&inst);
1a186d29
AV
19142
19143 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19144 {
19145 constraint (!inst.operands[1].isreg && !inst.operands[0].isquad, BAD_FPU);
19146 constraint ((inst.instruction & 0xd00) == 0xd00,
19147 _("immediate value out of range"));
19148 }
5287ad62
JB
19149}
19150
19151/* Encode instructions of form:
19152
19153 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
5f4273c7 19154 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
5287ad62
JB
19155
19156static void
19157neon_mixed_length (struct neon_type_el et, unsigned size)
19158{
19159 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19160 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19161 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19162 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19163 inst.instruction |= LOW4 (inst.operands[2].reg);
19164 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
19165 inst.instruction |= (et.type == NT_unsigned) << 24;
19166 inst.instruction |= neon_logbits (size) << 20;
5f4273c7 19167
88714cb8 19168 neon_dp_fixup (&inst);
5287ad62
JB
19169}
19170
19171static void
19172do_neon_dyadic_long (void)
19173{
5ee91343
AV
19174 enum neon_shape rs = neon_select_shape (NS_QDD, NS_QQQ, NS_QQR, NS_NULL);
19175 if (rs == NS_QDD)
19176 {
19177 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH | NEON_CHECK_CC) == FAIL)
19178 return;
19179
19180 NEON_ENCODE (INTEGER, inst);
19181 /* FIXME: Type checking for lengthening op. */
19182 struct neon_type_el et = neon_check_type (3, NS_QDD,
19183 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
19184 neon_mixed_length (et, et.size);
19185 }
19186 else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19187 && (inst.cond == 0xf || inst.cond == 0x10))
19188 {
19189 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19190 in an IT block with le/lt conditions. */
19191
19192 if (inst.cond == 0xf)
19193 inst.cond = 0xb;
19194 else if (inst.cond == 0x10)
19195 inst.cond = 0xd;
19196
19197 inst.pred_insn_type = INSIDE_IT_INSN;
19198
19199 if (inst.instruction == N_MNEM_vaddl)
19200 {
19201 inst.instruction = N_MNEM_vadd;
19202 do_neon_addsub_if_i ();
19203 }
19204 else if (inst.instruction == N_MNEM_vsubl)
19205 {
19206 inst.instruction = N_MNEM_vsub;
19207 do_neon_addsub_if_i ();
19208 }
19209 else if (inst.instruction == N_MNEM_vabdl)
19210 {
19211 inst.instruction = N_MNEM_vabd;
19212 do_neon_dyadic_if_su ();
19213 }
19214 }
19215 else
19216 first_error (BAD_FPU);
5287ad62
JB
19217}
19218
19219static void
19220do_neon_abal (void)
19221{
19222 struct neon_type_el et = neon_check_type (3, NS_QDD,
19223 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
19224 neon_mixed_length (et, et.size);
19225}
19226
19227static void
19228neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
19229{
19230 if (inst.operands[2].isscalar)
19231 {
dcbf9037 19232 struct neon_type_el et = neon_check_type (3, NS_QDS,
477330fc 19233 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
88714cb8 19234 NEON_ENCODE (SCALAR, inst);
5287ad62
JB
19235 neon_mul_mac (et, et.type == NT_unsigned);
19236 }
19237 else
19238 {
19239 struct neon_type_el et = neon_check_type (3, NS_QDD,
477330fc 19240 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
88714cb8 19241 NEON_ENCODE (INTEGER, inst);
5287ad62
JB
19242 neon_mixed_length (et, et.size);
19243 }
19244}
19245
19246static void
19247do_neon_mac_maybe_scalar_long (void)
19248{
19249 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
19250}
19251
dec41383
JW
19252/* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19253 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19254
19255static unsigned
19256neon_scalar_for_fmac_fp16_long (unsigned scalar, unsigned quad_p)
19257{
19258 unsigned regno = NEON_SCALAR_REG (scalar);
19259 unsigned elno = NEON_SCALAR_INDEX (scalar);
19260
19261 if (quad_p)
19262 {
19263 if (regno > 7 || elno > 3)
19264 goto bad_scalar;
19265
19266 return ((regno & 0x7)
19267 | ((elno & 0x1) << 3)
19268 | (((elno >> 1) & 0x1) << 5));
19269 }
19270 else
19271 {
19272 if (regno > 15 || elno > 1)
19273 goto bad_scalar;
19274
19275 return (((regno & 0x1) << 5)
19276 | ((regno >> 1) & 0x7)
19277 | ((elno & 0x1) << 3));
19278 }
19279
19280bad_scalar:
19281 first_error (_("scalar out of range for multiply instruction"));
19282 return 0;
19283}
19284
19285static void
19286do_neon_fmac_maybe_scalar_long (int subtype)
19287{
19288 enum neon_shape rs;
19289 int high8;
19290 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19291 field (bits[21:20]) has different meaning. For scalar index variant, it's
19292 used to differentiate add and subtract, otherwise it's with fixed value
19293 0x2. */
19294 int size = -1;
19295
19296 if (inst.cond != COND_ALWAYS)
19297 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19298 "behaviour is UNPREDICTABLE"));
19299
01f48020 19300 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16_fml),
dec41383
JW
19301 _(BAD_FP16));
19302
19303 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
19304 _(BAD_FPU));
19305
19306 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19307 be a scalar index register. */
19308 if (inst.operands[2].isscalar)
19309 {
19310 high8 = 0xfe000000;
19311 if (subtype)
19312 size = 16;
19313 rs = neon_select_shape (NS_DHS, NS_QDS, NS_NULL);
19314 }
19315 else
19316 {
19317 high8 = 0xfc000000;
19318 size = 32;
19319 if (subtype)
19320 inst.instruction |= (0x1 << 23);
19321 rs = neon_select_shape (NS_DHH, NS_QDD, NS_NULL);
19322 }
19323
19324 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16);
19325
19326 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19327 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19328 so we simply pass -1 as size. */
19329 unsigned quad_p = (rs == NS_QDD || rs == NS_QDS);
19330 neon_three_same (quad_p, 0, size);
19331
19332 /* Undo neon_dp_fixup. Redo the high eight bits. */
19333 inst.instruction &= 0x00ffffff;
19334 inst.instruction |= high8;
19335
19336#define LOW1(R) ((R) & 0x1)
19337#define HI4(R) (((R) >> 1) & 0xf)
19338 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19339 whether the instruction is in Q form and whether Vm is a scalar indexed
19340 operand. */
19341 if (inst.operands[2].isscalar)
19342 {
19343 unsigned rm
19344 = neon_scalar_for_fmac_fp16_long (inst.operands[2].reg, quad_p);
19345 inst.instruction &= 0xffffffd0;
19346 inst.instruction |= rm;
19347
19348 if (!quad_p)
19349 {
19350 /* Redo Rn as well. */
19351 inst.instruction &= 0xfff0ff7f;
19352 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
19353 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
19354 }
19355 }
19356 else if (!quad_p)
19357 {
19358 /* Redo Rn and Rm. */
19359 inst.instruction &= 0xfff0ff50;
19360 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
19361 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
19362 inst.instruction |= HI4 (inst.operands[2].reg);
19363 inst.instruction |= LOW1 (inst.operands[2].reg) << 5;
19364 }
19365}
19366
19367static void
19368do_neon_vfmal (void)
19369{
19370 return do_neon_fmac_maybe_scalar_long (0);
19371}
19372
19373static void
19374do_neon_vfmsl (void)
19375{
19376 return do_neon_fmac_maybe_scalar_long (1);
19377}
19378
5287ad62
JB
19379static void
19380do_neon_dyadic_wide (void)
19381{
19382 struct neon_type_el et = neon_check_type (3, NS_QQD,
19383 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
19384 neon_mixed_length (et, et.size);
19385}
19386
19387static void
19388do_neon_dyadic_narrow (void)
19389{
19390 struct neon_type_el et = neon_check_type (3, NS_QDD,
19391 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
428e3f1f
PB
19392 /* Operand sign is unimportant, and the U bit is part of the opcode,
19393 so force the operand type to integer. */
19394 et.type = NT_integer;
5287ad62
JB
19395 neon_mixed_length (et, et.size / 2);
19396}
19397
19398static void
19399do_neon_mul_sat_scalar_long (void)
19400{
19401 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
19402}
19403
19404static void
19405do_neon_vmull (void)
19406{
19407 if (inst.operands[2].isscalar)
19408 do_neon_mac_maybe_scalar_long ();
19409 else
19410 {
19411 struct neon_type_el et = neon_check_type (3, NS_QDD,
477330fc 19412 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
4f51b4bd 19413
5287ad62 19414 if (et.type == NT_poly)
477330fc 19415 NEON_ENCODE (POLY, inst);
5287ad62 19416 else
477330fc 19417 NEON_ENCODE (INTEGER, inst);
4f51b4bd
MGD
19418
19419 /* For polynomial encoding the U bit must be zero, and the size must
19420 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19421 obviously, as 0b10). */
19422 if (et.size == 64)
19423 {
19424 /* Check we're on the correct architecture. */
19425 if (!mark_feature_used (&fpu_crypto_ext_armv8))
19426 inst.error =
19427 _("Instruction form not available on this architecture.");
19428
19429 et.size = 32;
19430 }
19431
5287ad62
JB
19432 neon_mixed_length (et, et.size);
19433 }
19434}
19435
19436static void
19437do_neon_ext (void)
19438{
037e8744 19439 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
5287ad62
JB
19440 struct neon_type_el et = neon_check_type (3, rs,
19441 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
19442 unsigned imm = (inst.operands[3].imm * et.size) / 8;
35997600
NC
19443
19444 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
19445 _("shift out of range"));
5287ad62
JB
19446 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19447 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19448 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19449 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19450 inst.instruction |= LOW4 (inst.operands[2].reg);
19451 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
037e8744 19452 inst.instruction |= neon_quad (rs) << 6;
5287ad62 19453 inst.instruction |= imm << 8;
5f4273c7 19454
88714cb8 19455 neon_dp_fixup (&inst);
5287ad62
JB
19456}
19457
19458static void
19459do_neon_rev (void)
19460{
64c350f2 19461 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
4401c241
AV
19462 return;
19463
19464 enum neon_shape rs;
19465 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19466 rs = neon_select_shape (NS_QQ, NS_NULL);
19467 else
19468 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19469
5287ad62
JB
19470 struct neon_type_el et = neon_check_type (2, rs,
19471 N_EQK, N_8 | N_16 | N_32 | N_KEY);
4401c241 19472
5287ad62
JB
19473 unsigned op = (inst.instruction >> 7) & 3;
19474 /* N (width of reversed regions) is encoded as part of the bitmask. We
19475 extract it here to check the elements to be reversed are smaller.
19476 Otherwise we'd get a reserved instruction. */
19477 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
4401c241
AV
19478
19479 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) && elsize == 64
19480 && inst.operands[0].reg == inst.operands[1].reg)
19481 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19482 " operands makes instruction UNPREDICTABLE"));
19483
9c2799c2 19484 gas_assert (elsize != 0);
5287ad62 19485 constraint (et.size >= elsize,
477330fc 19486 _("elements must be smaller than reversal region"));
037e8744 19487 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
19488}
19489
19490static void
19491do_neon_dup (void)
19492{
19493 if (inst.operands[1].isscalar)
19494 {
b409bdb6
AV
19495 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
19496 BAD_FPU);
037e8744 19497 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
dcbf9037 19498 struct neon_type_el et = neon_check_type (2, rs,
477330fc 19499 N_EQK, N_8 | N_16 | N_32 | N_KEY);
5287ad62 19500 unsigned sizebits = et.size >> 3;
dcbf9037 19501 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
5287ad62 19502 int logsize = neon_logbits (et.size);
dcbf9037 19503 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
037e8744
JB
19504
19505 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
477330fc 19506 return;
037e8744 19507
88714cb8 19508 NEON_ENCODE (SCALAR, inst);
5287ad62
JB
19509 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19510 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19511 inst.instruction |= LOW4 (dm);
19512 inst.instruction |= HI1 (dm) << 5;
037e8744 19513 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB
19514 inst.instruction |= x << 17;
19515 inst.instruction |= sizebits << 16;
5f4273c7 19516
88714cb8 19517 neon_dp_fixup (&inst);
5287ad62
JB
19518 }
19519 else
19520 {
037e8744
JB
19521 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
19522 struct neon_type_el et = neon_check_type (2, rs,
477330fc 19523 N_8 | N_16 | N_32 | N_KEY, N_EQK);
b409bdb6
AV
19524 if (rs == NS_QR)
19525 {
64c350f2 19526 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH))
b409bdb6
AV
19527 return;
19528 }
19529 else
19530 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
19531 BAD_FPU);
19532
19533 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19534 {
19535 if (inst.operands[1].reg == REG_SP)
19536 as_tsktsk (MVE_BAD_SP);
19537 else if (inst.operands[1].reg == REG_PC)
19538 as_tsktsk (MVE_BAD_PC);
19539 }
19540
5287ad62 19541 /* Duplicate ARM register to lanes of vector. */
88714cb8 19542 NEON_ENCODE (ARMREG, inst);
5287ad62 19543 switch (et.size)
477330fc
RM
19544 {
19545 case 8: inst.instruction |= 0x400000; break;
19546 case 16: inst.instruction |= 0x000020; break;
19547 case 32: inst.instruction |= 0x000000; break;
19548 default: break;
19549 }
5287ad62
JB
19550 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
19551 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
19552 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
037e8744 19553 inst.instruction |= neon_quad (rs) << 21;
5287ad62 19554 /* The encoding for this instruction is identical for the ARM and Thumb
477330fc 19555 variants, except for the condition field. */
037e8744 19556 do_vfp_cond_or_thumb ();
5287ad62
JB
19557 }
19558}
19559
57785aa2
AV
19560static void
19561do_mve_mov (int toQ)
19562{
19563 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19564 return;
19565 if (inst.cond > COND_ALWAYS)
19566 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
19567
19568 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3;
19569 if (toQ)
19570 {
19571 Q0 = 0;
19572 Q1 = 1;
19573 Rt = 2;
19574 Rt2 = 3;
19575 }
19576
19577 constraint (inst.operands[Q0].reg != inst.operands[Q1].reg + 2,
19578 _("Index one must be [2,3] and index two must be two less than"
19579 " index one."));
19580 constraint (inst.operands[Rt].reg == inst.operands[Rt2].reg,
19581 _("General purpose registers may not be the same"));
19582 constraint (inst.operands[Rt].reg == REG_SP
19583 || inst.operands[Rt2].reg == REG_SP,
19584 BAD_SP);
19585 constraint (inst.operands[Rt].reg == REG_PC
19586 || inst.operands[Rt2].reg == REG_PC,
19587 BAD_PC);
19588
19589 inst.instruction = 0xec000f00;
19590 inst.instruction |= HI1 (inst.operands[Q1].reg / 32) << 23;
19591 inst.instruction |= !!toQ << 20;
19592 inst.instruction |= inst.operands[Rt2].reg << 16;
19593 inst.instruction |= LOW4 (inst.operands[Q1].reg / 32) << 13;
19594 inst.instruction |= (inst.operands[Q1].reg % 4) << 4;
19595 inst.instruction |= inst.operands[Rt].reg;
19596}
19597
19598static void
19599do_mve_movn (void)
19600{
19601 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19602 return;
19603
19604 if (inst.cond > COND_ALWAYS)
19605 inst.pred_insn_type = INSIDE_VPT_INSN;
19606 else
19607 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
19608
19609 struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_I16 | N_I32
19610 | N_KEY);
19611
19612 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19613 inst.instruction |= (neon_logbits (et.size) - 1) << 18;
19614 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19615 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19616 inst.instruction |= LOW4 (inst.operands[1].reg);
19617 inst.is_neon = 1;
19618
19619}
19620
5287ad62
JB
19621/* VMOV has particularly many variations. It can be one of:
19622 0. VMOV<c><q> <Qd>, <Qm>
19623 1. VMOV<c><q> <Dd>, <Dm>
19624 (Register operations, which are VORR with Rm = Rn.)
19625 2. VMOV<c><q>.<dt> <Qd>, #<imm>
19626 3. VMOV<c><q>.<dt> <Dd>, #<imm>
19627 (Immediate loads.)
19628 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
19629 (ARM register to scalar.)
19630 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
19631 (Two ARM registers to vector.)
19632 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
19633 (Scalar to ARM register.)
19634 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
19635 (Vector to two ARM registers.)
037e8744
JB
19636 8. VMOV.F32 <Sd>, <Sm>
19637 9. VMOV.F64 <Dd>, <Dm>
19638 (VFP register moves.)
19639 10. VMOV.F32 <Sd>, #imm
19640 11. VMOV.F64 <Dd>, #imm
19641 (VFP float immediate load.)
19642 12. VMOV <Rd>, <Sm>
19643 (VFP single to ARM reg.)
19644 13. VMOV <Sd>, <Rm>
19645 (ARM reg to VFP single.)
19646 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
19647 (Two ARM regs to two VFP singles.)
19648 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
19649 (Two VFP singles to two ARM regs.)
57785aa2
AV
19650 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
19651 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
19652 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
19653 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
5f4273c7 19654
037e8744
JB
19655 These cases can be disambiguated using neon_select_shape, except cases 1/9
19656 and 3/11 which depend on the operand type too.
5f4273c7 19657
5287ad62 19658 All the encoded bits are hardcoded by this function.
5f4273c7 19659
b7fc2769
JB
19660 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
19661 Cases 5, 7 may be used with VFPv2 and above.
5f4273c7 19662
5287ad62 19663 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
5f4273c7 19664 can specify a type where it doesn't make sense to, and is ignored). */
5287ad62
JB
19665
19666static void
19667do_neon_mov (void)
19668{
57785aa2
AV
19669 enum neon_shape rs = neon_select_shape (NS_RRSS, NS_SSRR, NS_RRFF, NS_FFRR,
19670 NS_DRR, NS_RRD, NS_QQ, NS_DD, NS_QI,
19671 NS_DI, NS_SR, NS_RS, NS_FF, NS_FI,
19672 NS_RF, NS_FR, NS_HR, NS_RH, NS_HI,
19673 NS_NULL);
037e8744
JB
19674 struct neon_type_el et;
19675 const char *ldconst = 0;
5287ad62 19676
037e8744 19677 switch (rs)
5287ad62 19678 {
037e8744
JB
19679 case NS_DD: /* case 1/9. */
19680 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
19681 /* It is not an error here if no type is given. */
19682 inst.error = NULL;
19683 if (et.type == NT_float && et.size == 64)
477330fc
RM
19684 {
19685 do_vfp_nsyn_opcode ("fcpyd");
19686 break;
19687 }
037e8744 19688 /* fall through. */
5287ad62 19689
037e8744
JB
19690 case NS_QQ: /* case 0/1. */
19691 {
64c350f2
AV
19692 if (!check_simd_pred_availability (FALSE,
19693 NEON_CHECK_CC | NEON_CHECK_ARCH))
477330fc
RM
19694 return;
19695 /* The architecture manual I have doesn't explicitly state which
19696 value the U bit should have for register->register moves, but
19697 the equivalent VORR instruction has U = 0, so do that. */
19698 inst.instruction = 0x0200110;
19699 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19700 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19701 inst.instruction |= LOW4 (inst.operands[1].reg);
19702 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19703 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19704 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19705 inst.instruction |= neon_quad (rs) << 6;
19706
19707 neon_dp_fixup (&inst);
037e8744
JB
19708 }
19709 break;
5f4273c7 19710
037e8744
JB
19711 case NS_DI: /* case 3/11. */
19712 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
19713 inst.error = NULL;
19714 if (et.type == NT_float && et.size == 64)
477330fc
RM
19715 {
19716 /* case 11 (fconstd). */
19717 ldconst = "fconstd";
19718 goto encode_fconstd;
19719 }
037e8744
JB
19720 /* fall through. */
19721
19722 case NS_QI: /* case 2/3. */
64c350f2
AV
19723 if (!check_simd_pred_availability (FALSE,
19724 NEON_CHECK_CC | NEON_CHECK_ARCH))
477330fc 19725 return;
037e8744
JB
19726 inst.instruction = 0x0800010;
19727 neon_move_immediate ();
88714cb8 19728 neon_dp_fixup (&inst);
5287ad62 19729 break;
5f4273c7 19730
037e8744
JB
19731 case NS_SR: /* case 4. */
19732 {
477330fc
RM
19733 unsigned bcdebits = 0;
19734 int logsize;
19735 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
19736 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
037e8744 19737
05ac0ffb
JB
19738 /* .<size> is optional here, defaulting to .32. */
19739 if (inst.vectype.elems == 0
19740 && inst.operands[0].vectype.type == NT_invtype
19741 && inst.operands[1].vectype.type == NT_invtype)
19742 {
19743 inst.vectype.el[0].type = NT_untyped;
19744 inst.vectype.el[0].size = 32;
19745 inst.vectype.elems = 1;
19746 }
19747
477330fc
RM
19748 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
19749 logsize = neon_logbits (et.size);
19750
57785aa2
AV
19751 if (et.size != 32)
19752 {
19753 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19754 && vfp_or_neon_is_neon (NEON_CHECK_ARCH) == FAIL)
19755 return;
19756 }
19757 else
19758 {
19759 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
19760 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19761 _(BAD_FPU));
19762 }
19763
19764 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19765 {
19766 if (inst.operands[1].reg == REG_SP)
19767 as_tsktsk (MVE_BAD_SP);
19768 else if (inst.operands[1].reg == REG_PC)
19769 as_tsktsk (MVE_BAD_PC);
19770 }
19771 unsigned size = inst.operands[0].isscalar == 1 ? 64 : 128;
19772
477330fc 19773 constraint (et.type == NT_invtype, _("bad type for scalar"));
57785aa2
AV
19774 constraint (x >= size / et.size, _("scalar index out of range"));
19775
477330fc
RM
19776
19777 switch (et.size)
19778 {
19779 case 8: bcdebits = 0x8; break;
19780 case 16: bcdebits = 0x1; break;
19781 case 32: bcdebits = 0x0; break;
19782 default: ;
19783 }
19784
57785aa2 19785 bcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize;
477330fc
RM
19786
19787 inst.instruction = 0xe000b10;
19788 do_vfp_cond_or_thumb ();
19789 inst.instruction |= LOW4 (dn) << 16;
19790 inst.instruction |= HI1 (dn) << 7;
19791 inst.instruction |= inst.operands[1].reg << 12;
19792 inst.instruction |= (bcdebits & 3) << 5;
57785aa2
AV
19793 inst.instruction |= ((bcdebits >> 2) & 3) << 21;
19794 inst.instruction |= (x >> (3-logsize)) << 16;
037e8744
JB
19795 }
19796 break;
5f4273c7 19797
037e8744 19798 case NS_DRR: /* case 5 (fmdrr). */
57785aa2
AV
19799 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
19800 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
477330fc 19801 _(BAD_FPU));
b7fc2769 19802
037e8744
JB
19803 inst.instruction = 0xc400b10;
19804 do_vfp_cond_or_thumb ();
19805 inst.instruction |= LOW4 (inst.operands[0].reg);
19806 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
19807 inst.instruction |= inst.operands[1].reg << 12;
19808 inst.instruction |= inst.operands[2].reg << 16;
19809 break;
5f4273c7 19810
037e8744
JB
19811 case NS_RS: /* case 6. */
19812 {
477330fc
RM
19813 unsigned logsize;
19814 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
19815 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
19816 unsigned abcdebits = 0;
037e8744 19817
05ac0ffb
JB
19818 /* .<dt> is optional here, defaulting to .32. */
19819 if (inst.vectype.elems == 0
19820 && inst.operands[0].vectype.type == NT_invtype
19821 && inst.operands[1].vectype.type == NT_invtype)
19822 {
19823 inst.vectype.el[0].type = NT_untyped;
19824 inst.vectype.el[0].size = 32;
19825 inst.vectype.elems = 1;
19826 }
19827
91d6fa6a
NC
19828 et = neon_check_type (2, NS_NULL,
19829 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
477330fc
RM
19830 logsize = neon_logbits (et.size);
19831
57785aa2
AV
19832 if (et.size != 32)
19833 {
19834 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19835 && vfp_or_neon_is_neon (NEON_CHECK_CC
19836 | NEON_CHECK_ARCH) == FAIL)
19837 return;
19838 }
19839 else
19840 {
19841 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
19842 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19843 _(BAD_FPU));
19844 }
19845
19846 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19847 {
19848 if (inst.operands[0].reg == REG_SP)
19849 as_tsktsk (MVE_BAD_SP);
19850 else if (inst.operands[0].reg == REG_PC)
19851 as_tsktsk (MVE_BAD_PC);
19852 }
19853
19854 unsigned size = inst.operands[1].isscalar == 1 ? 64 : 128;
19855
477330fc 19856 constraint (et.type == NT_invtype, _("bad type for scalar"));
57785aa2 19857 constraint (x >= size / et.size, _("scalar index out of range"));
477330fc
RM
19858
19859 switch (et.size)
19860 {
19861 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
19862 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
19863 case 32: abcdebits = 0x00; break;
19864 default: ;
19865 }
19866
57785aa2 19867 abcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize;
477330fc
RM
19868 inst.instruction = 0xe100b10;
19869 do_vfp_cond_or_thumb ();
19870 inst.instruction |= LOW4 (dn) << 16;
19871 inst.instruction |= HI1 (dn) << 7;
19872 inst.instruction |= inst.operands[0].reg << 12;
19873 inst.instruction |= (abcdebits & 3) << 5;
19874 inst.instruction |= (abcdebits >> 2) << 21;
57785aa2 19875 inst.instruction |= (x >> (3-logsize)) << 16;
037e8744
JB
19876 }
19877 break;
5f4273c7 19878
037e8744 19879 case NS_RRD: /* case 7 (fmrrd). */
57785aa2
AV
19880 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
19881 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
477330fc 19882 _(BAD_FPU));
037e8744
JB
19883
19884 inst.instruction = 0xc500b10;
19885 do_vfp_cond_or_thumb ();
19886 inst.instruction |= inst.operands[0].reg << 12;
19887 inst.instruction |= inst.operands[1].reg << 16;
19888 inst.instruction |= LOW4 (inst.operands[2].reg);
19889 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
19890 break;
5f4273c7 19891
037e8744
JB
19892 case NS_FF: /* case 8 (fcpys). */
19893 do_vfp_nsyn_opcode ("fcpys");
19894 break;
5f4273c7 19895
9db2f6b4 19896 case NS_HI:
037e8744
JB
19897 case NS_FI: /* case 10 (fconsts). */
19898 ldconst = "fconsts";
4ef4710f 19899 encode_fconstd:
58ed5c38
TC
19900 if (!inst.operands[1].immisfloat)
19901 {
4ef4710f 19902 unsigned new_imm;
58ed5c38 19903 /* Immediate has to fit in 8 bits so float is enough. */
4ef4710f
NC
19904 float imm = (float) inst.operands[1].imm;
19905 memcpy (&new_imm, &imm, sizeof (float));
19906 /* But the assembly may have been written to provide an integer
19907 bit pattern that equates to a float, so check that the
19908 conversion has worked. */
19909 if (is_quarter_float (new_imm))
19910 {
19911 if (is_quarter_float (inst.operands[1].imm))
19912 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
19913
19914 inst.operands[1].imm = new_imm;
19915 inst.operands[1].immisfloat = 1;
19916 }
58ed5c38
TC
19917 }
19918
037e8744 19919 if (is_quarter_float (inst.operands[1].imm))
477330fc
RM
19920 {
19921 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
19922 do_vfp_nsyn_opcode (ldconst);
9db2f6b4
RL
19923
19924 /* ARMv8.2 fp16 vmov.f16 instruction. */
19925 if (rs == NS_HI)
19926 do_scalar_fp16_v82_encode ();
477330fc 19927 }
5287ad62 19928 else
477330fc 19929 first_error (_("immediate out of range"));
037e8744 19930 break;
5f4273c7 19931
9db2f6b4 19932 case NS_RH:
037e8744
JB
19933 case NS_RF: /* case 12 (fmrs). */
19934 do_vfp_nsyn_opcode ("fmrs");
9db2f6b4
RL
19935 /* ARMv8.2 fp16 vmov.f16 instruction. */
19936 if (rs == NS_RH)
19937 do_scalar_fp16_v82_encode ();
037e8744 19938 break;
5f4273c7 19939
9db2f6b4 19940 case NS_HR:
037e8744
JB
19941 case NS_FR: /* case 13 (fmsr). */
19942 do_vfp_nsyn_opcode ("fmsr");
9db2f6b4
RL
19943 /* ARMv8.2 fp16 vmov.f16 instruction. */
19944 if (rs == NS_HR)
19945 do_scalar_fp16_v82_encode ();
037e8744 19946 break;
5f4273c7 19947
57785aa2
AV
19948 case NS_RRSS:
19949 do_mve_mov (0);
19950 break;
19951 case NS_SSRR:
19952 do_mve_mov (1);
19953 break;
19954
037e8744
JB
19955 /* The encoders for the fmrrs and fmsrr instructions expect three operands
19956 (one of which is a list), but we have parsed four. Do some fiddling to
19957 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
19958 expect. */
19959 case NS_RRFF: /* case 14 (fmrrs). */
57785aa2
AV
19960 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
19961 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19962 _(BAD_FPU));
037e8744 19963 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
477330fc 19964 _("VFP registers must be adjacent"));
037e8744
JB
19965 inst.operands[2].imm = 2;
19966 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
19967 do_vfp_nsyn_opcode ("fmrrs");
19968 break;
5f4273c7 19969
037e8744 19970 case NS_FFRR: /* case 15 (fmsrr). */
57785aa2
AV
19971 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
19972 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19973 _(BAD_FPU));
037e8744 19974 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
477330fc 19975 _("VFP registers must be adjacent"));
037e8744
JB
19976 inst.operands[1] = inst.operands[2];
19977 inst.operands[2] = inst.operands[3];
19978 inst.operands[0].imm = 2;
19979 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
19980 do_vfp_nsyn_opcode ("fmsrr");
5287ad62 19981 break;
5f4273c7 19982
4c261dff
NC
19983 case NS_NULL:
19984 /* neon_select_shape has determined that the instruction
19985 shape is wrong and has already set the error message. */
19986 break;
19987
5287ad62
JB
19988 default:
19989 abort ();
19990 }
19991}
19992
57785aa2
AV
19993static void
19994do_mve_movl (void)
19995{
19996 if (!(inst.operands[0].present && inst.operands[0].isquad
19997 && inst.operands[1].present && inst.operands[1].isquad
19998 && !inst.operands[2].present))
19999 {
20000 inst.instruction = 0;
20001 inst.cond = 0xb;
20002 if (thumb_mode)
20003 set_pred_insn_type (INSIDE_IT_INSN);
20004 do_neon_mov ();
20005 return;
20006 }
20007
20008 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20009 return;
20010
20011 if (inst.cond != COND_ALWAYS)
20012 inst.pred_insn_type = INSIDE_VPT_INSN;
20013
20014 struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_S8 | N_U8
20015 | N_S16 | N_U16 | N_KEY);
20016
20017 inst.instruction |= (et.type == NT_unsigned) << 28;
20018 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20019 inst.instruction |= (neon_logbits (et.size) + 1) << 19;
20020 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20021 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20022 inst.instruction |= LOW4 (inst.operands[1].reg);
20023 inst.is_neon = 1;
20024}
20025
5287ad62
JB
20026static void
20027do_neon_rshift_round_imm (void)
20028{
64c350f2 20029 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
4401c241
AV
20030 return;
20031
20032 enum neon_shape rs;
20033 struct neon_type_el et;
20034
20035 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20036 {
20037 rs = neon_select_shape (NS_QQI, NS_NULL);
20038 et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY);
20039 }
20040 else
20041 {
20042 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
20043 et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
20044 }
5287ad62
JB
20045 int imm = inst.operands[2].imm;
20046
20047 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20048 if (imm == 0)
20049 {
20050 inst.operands[2].present = 0;
20051 do_neon_mov ();
20052 return;
20053 }
20054
20055 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 20056 _("immediate out of range for shift"));
037e8744 20057 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
477330fc 20058 et.size - imm);
5287ad62
JB
20059}
20060
9db2f6b4
RL
20061static void
20062do_neon_movhf (void)
20063{
20064 enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL);
20065 constraint (rs != NS_HH, _("invalid suffix"));
20066
7bdf778b
ASDV
20067 if (inst.cond != COND_ALWAYS)
20068 {
20069 if (thumb_mode)
20070 {
20071 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20072 " the behaviour is UNPREDICTABLE"));
20073 }
20074 else
20075 {
20076 inst.error = BAD_COND;
20077 return;
20078 }
20079 }
20080
9db2f6b4
RL
20081 do_vfp_sp_monadic ();
20082
20083 inst.is_neon = 1;
20084 inst.instruction |= 0xf0000000;
20085}
20086
5287ad62
JB
20087static void
20088do_neon_movl (void)
20089{
20090 struct neon_type_el et = neon_check_type (2, NS_QD,
20091 N_EQK | N_DBL, N_SU_32 | N_KEY);
20092 unsigned sizebits = et.size >> 3;
20093 inst.instruction |= sizebits << 19;
20094 neon_two_same (0, et.type == NT_unsigned, -1);
20095}
20096
20097static void
20098do_neon_trn (void)
20099{
037e8744 20100 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
20101 struct neon_type_el et = neon_check_type (2, rs,
20102 N_EQK, N_8 | N_16 | N_32 | N_KEY);
88714cb8 20103 NEON_ENCODE (INTEGER, inst);
037e8744 20104 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
20105}
20106
20107static void
20108do_neon_zip_uzp (void)
20109{
037e8744 20110 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
20111 struct neon_type_el et = neon_check_type (2, rs,
20112 N_EQK, N_8 | N_16 | N_32 | N_KEY);
20113 if (rs == NS_DD && et.size == 32)
20114 {
20115 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20116 inst.instruction = N_MNEM_vtrn;
20117 do_neon_trn ();
20118 return;
20119 }
037e8744 20120 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
20121}
20122
20123static void
20124do_neon_sat_abs_neg (void)
20125{
64c350f2 20126 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
1a186d29
AV
20127 return;
20128
20129 enum neon_shape rs;
20130 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20131 rs = neon_select_shape (NS_QQ, NS_NULL);
20132 else
20133 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
20134 struct neon_type_el et = neon_check_type (2, rs,
20135 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
037e8744 20136 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
20137}
20138
20139static void
20140do_neon_pair_long (void)
20141{
037e8744 20142 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
20143 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
20144 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20145 inst.instruction |= (et.type == NT_unsigned) << 7;
037e8744 20146 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
20147}
20148
20149static void
20150do_neon_recip_est (void)
20151{
037e8744 20152 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62 20153 struct neon_type_el et = neon_check_type (2, rs,
cc933301 20154 N_EQK | N_FLT, N_F_16_32 | N_U32 | N_KEY);
5287ad62 20155 inst.instruction |= (et.type == NT_float) << 8;
037e8744 20156 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
20157}
20158
20159static void
20160do_neon_cls (void)
20161{
64c350f2 20162 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
f30ee27c
AV
20163 return;
20164
20165 enum neon_shape rs;
20166 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20167 rs = neon_select_shape (NS_QQ, NS_NULL);
20168 else
20169 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20170
5287ad62
JB
20171 struct neon_type_el et = neon_check_type (2, rs,
20172 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
037e8744 20173 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
20174}
20175
20176static void
20177do_neon_clz (void)
20178{
64c350f2 20179 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
f30ee27c
AV
20180 return;
20181
20182 enum neon_shape rs;
20183 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20184 rs = neon_select_shape (NS_QQ, NS_NULL);
20185 else
20186 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20187
5287ad62
JB
20188 struct neon_type_el et = neon_check_type (2, rs,
20189 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
037e8744 20190 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
20191}
20192
20193static void
20194do_neon_cnt (void)
20195{
037e8744 20196 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
20197 struct neon_type_el et = neon_check_type (2, rs,
20198 N_EQK | N_INT, N_8 | N_KEY);
037e8744 20199 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
20200}
20201
20202static void
20203do_neon_swp (void)
20204{
037e8744
JB
20205 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20206 neon_two_same (neon_quad (rs), 1, -1);
5287ad62
JB
20207}
20208
20209static void
20210do_neon_tbl_tbx (void)
20211{
20212 unsigned listlenbits;
dcbf9037 20213 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
5f4273c7 20214
5287ad62
JB
20215 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
20216 {
dcbf9037 20217 first_error (_("bad list length for table lookup"));
5287ad62
JB
20218 return;
20219 }
5f4273c7 20220
5287ad62
JB
20221 listlenbits = inst.operands[1].imm - 1;
20222 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20223 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20224 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20225 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
20226 inst.instruction |= LOW4 (inst.operands[2].reg);
20227 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
20228 inst.instruction |= listlenbits << 8;
5f4273c7 20229
88714cb8 20230 neon_dp_fixup (&inst);
5287ad62
JB
20231}
20232
20233static void
20234do_neon_ldm_stm (void)
20235{
20236 /* P, U and L bits are part of bitmask. */
20237 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
20238 unsigned offsetbits = inst.operands[1].imm * 2;
20239
037e8744
JB
20240 if (inst.operands[1].issingle)
20241 {
20242 do_vfp_nsyn_ldm_stm (is_dbmode);
20243 return;
20244 }
20245
5287ad62 20246 constraint (is_dbmode && !inst.operands[0].writeback,
477330fc 20247 _("writeback (!) must be used for VLDMDB and VSTMDB"));
5287ad62
JB
20248
20249 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
477330fc
RM
20250 _("register list must contain at least 1 and at most 16 "
20251 "registers"));
5287ad62
JB
20252
20253 inst.instruction |= inst.operands[0].reg << 16;
20254 inst.instruction |= inst.operands[0].writeback << 21;
20255 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
20256 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
20257
20258 inst.instruction |= offsetbits;
5f4273c7 20259
037e8744 20260 do_vfp_cond_or_thumb ();
5287ad62
JB
20261}
20262
20263static void
20264do_neon_ldr_str (void)
20265{
5287ad62 20266 int is_ldr = (inst.instruction & (1 << 20)) != 0;
5f4273c7 20267
6844b2c2
MGD
20268 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20269 And is UNPREDICTABLE in thumb mode. */
fa94de6b 20270 if (!is_ldr
6844b2c2 20271 && inst.operands[1].reg == REG_PC
ba86b375 20272 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
6844b2c2 20273 {
94dcf8bf 20274 if (thumb_mode)
6844b2c2 20275 inst.error = _("Use of PC here is UNPREDICTABLE");
94dcf8bf 20276 else if (warn_on_deprecated)
5c3696f8 20277 as_tsktsk (_("Use of PC here is deprecated"));
6844b2c2
MGD
20278 }
20279
037e8744
JB
20280 if (inst.operands[0].issingle)
20281 {
cd2f129f 20282 if (is_ldr)
477330fc 20283 do_vfp_nsyn_opcode ("flds");
cd2f129f 20284 else
477330fc 20285 do_vfp_nsyn_opcode ("fsts");
9db2f6b4
RL
20286
20287 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20288 if (inst.vectype.el[0].size == 16)
20289 do_scalar_fp16_v82_encode ();
5287ad62
JB
20290 }
20291 else
5287ad62 20292 {
cd2f129f 20293 if (is_ldr)
477330fc 20294 do_vfp_nsyn_opcode ("fldd");
5287ad62 20295 else
477330fc 20296 do_vfp_nsyn_opcode ("fstd");
5287ad62 20297 }
5287ad62
JB
20298}
20299
32c36c3c
AV
20300static void
20301do_t_vldr_vstr_sysreg (void)
20302{
20303 int fp_vldr_bitno = 20, sysreg_vldr_bitno = 20;
20304 bfd_boolean is_vldr = ((inst.instruction & (1 << fp_vldr_bitno)) != 0);
20305
20306 /* Use of PC is UNPREDICTABLE. */
20307 if (inst.operands[1].reg == REG_PC)
20308 inst.error = _("Use of PC here is UNPREDICTABLE");
20309
20310 if (inst.operands[1].immisreg)
20311 inst.error = _("instruction does not accept register index");
20312
20313 if (!inst.operands[1].isreg)
20314 inst.error = _("instruction does not accept PC-relative addressing");
20315
20316 if (abs (inst.operands[1].imm) >= (1 << 7))
20317 inst.error = _("immediate value out of range");
20318
20319 inst.instruction = 0xec000f80;
20320 if (is_vldr)
20321 inst.instruction |= 1 << sysreg_vldr_bitno;
20322 encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM);
20323 inst.instruction |= (inst.operands[0].imm & 0x7) << 13;
20324 inst.instruction |= (inst.operands[0].imm & 0x8) << 19;
20325}
20326
20327static void
20328do_vldr_vstr (void)
20329{
20330 bfd_boolean sysreg_op = !inst.operands[0].isreg;
20331
20332 /* VLDR/VSTR (System Register). */
20333 if (sysreg_op)
20334 {
20335 if (!mark_feature_used (&arm_ext_v8_1m_main))
20336 as_bad (_("Instruction not permitted on this architecture"));
20337
20338 do_t_vldr_vstr_sysreg ();
20339 }
20340 /* VLDR/VSTR. */
20341 else
20342 {
20343 if (!mark_feature_used (&fpu_vfp_ext_v1xd))
20344 as_bad (_("Instruction not permitted on this architecture"));
20345 do_neon_ldr_str ();
20346 }
20347}
20348
5287ad62
JB
20349/* "interleave" version also handles non-interleaving register VLD1/VST1
20350 instructions. */
20351
20352static void
20353do_neon_ld_st_interleave (void)
20354{
037e8744 20355 struct neon_type_el et = neon_check_type (1, NS_NULL,
477330fc 20356 N_8 | N_16 | N_32 | N_64);
5287ad62
JB
20357 unsigned alignbits = 0;
20358 unsigned idx;
20359 /* The bits in this table go:
20360 0: register stride of one (0) or two (1)
20361 1,2: register list length, minus one (1, 2, 3, 4).
20362 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20363 We use -1 for invalid entries. */
20364 const int typetable[] =
20365 {
20366 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20367 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20368 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20369 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20370 };
20371 int typebits;
20372
dcbf9037
JB
20373 if (et.type == NT_invtype)
20374 return;
20375
5287ad62
JB
20376 if (inst.operands[1].immisalign)
20377 switch (inst.operands[1].imm >> 8)
20378 {
20379 case 64: alignbits = 1; break;
20380 case 128:
477330fc 20381 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
e23c0ad8 20382 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
477330fc
RM
20383 goto bad_alignment;
20384 alignbits = 2;
20385 break;
5287ad62 20386 case 256:
477330fc
RM
20387 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
20388 goto bad_alignment;
20389 alignbits = 3;
20390 break;
5287ad62
JB
20391 default:
20392 bad_alignment:
477330fc
RM
20393 first_error (_("bad alignment"));
20394 return;
5287ad62
JB
20395 }
20396
20397 inst.instruction |= alignbits << 4;
20398 inst.instruction |= neon_logbits (et.size) << 6;
20399
20400 /* Bits [4:6] of the immediate in a list specifier encode register stride
20401 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20402 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20403 up the right value for "type" in a table based on this value and the given
20404 list style, then stick it back. */
20405 idx = ((inst.operands[0].imm >> 4) & 7)
477330fc 20406 | (((inst.instruction >> 8) & 3) << 3);
5287ad62
JB
20407
20408 typebits = typetable[idx];
5f4273c7 20409
5287ad62 20410 constraint (typebits == -1, _("bad list type for instruction"));
1d50d57c 20411 constraint (((inst.instruction >> 8) & 3) && et.size == 64,
35c228db 20412 BAD_EL_TYPE);
5287ad62
JB
20413
20414 inst.instruction &= ~0xf00;
20415 inst.instruction |= typebits << 8;
20416}
20417
20418/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20419 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20420 otherwise. The variable arguments are a list of pairs of legal (size, align)
20421 values, terminated with -1. */
20422
20423static int
aa8a0863 20424neon_alignment_bit (int size, int align, int *do_alignment, ...)
5287ad62
JB
20425{
20426 va_list ap;
20427 int result = FAIL, thissize, thisalign;
5f4273c7 20428
5287ad62
JB
20429 if (!inst.operands[1].immisalign)
20430 {
aa8a0863 20431 *do_alignment = 0;
5287ad62
JB
20432 return SUCCESS;
20433 }
5f4273c7 20434
aa8a0863 20435 va_start (ap, do_alignment);
5287ad62
JB
20436
20437 do
20438 {
20439 thissize = va_arg (ap, int);
20440 if (thissize == -1)
477330fc 20441 break;
5287ad62
JB
20442 thisalign = va_arg (ap, int);
20443
20444 if (size == thissize && align == thisalign)
477330fc 20445 result = SUCCESS;
5287ad62
JB
20446 }
20447 while (result != SUCCESS);
20448
20449 va_end (ap);
20450
20451 if (result == SUCCESS)
aa8a0863 20452 *do_alignment = 1;
5287ad62 20453 else
dcbf9037 20454 first_error (_("unsupported alignment for instruction"));
5f4273c7 20455
5287ad62
JB
20456 return result;
20457}
20458
20459static void
20460do_neon_ld_st_lane (void)
20461{
037e8744 20462 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
aa8a0863 20463 int align_good, do_alignment = 0;
5287ad62
JB
20464 int logsize = neon_logbits (et.size);
20465 int align = inst.operands[1].imm >> 8;
20466 int n = (inst.instruction >> 8) & 3;
20467 int max_el = 64 / et.size;
5f4273c7 20468
dcbf9037
JB
20469 if (et.type == NT_invtype)
20470 return;
5f4273c7 20471
5287ad62 20472 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
477330fc 20473 _("bad list length"));
5287ad62 20474 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
477330fc 20475 _("scalar index out of range"));
5287ad62 20476 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
477330fc
RM
20477 && et.size == 8,
20478 _("stride of 2 unavailable when element size is 8"));
5f4273c7 20479
5287ad62
JB
20480 switch (n)
20481 {
20482 case 0: /* VLD1 / VST1. */
aa8a0863 20483 align_good = neon_alignment_bit (et.size, align, &do_alignment, 16, 16,
477330fc 20484 32, 32, -1);
5287ad62 20485 if (align_good == FAIL)
477330fc 20486 return;
aa8a0863 20487 if (do_alignment)
477330fc
RM
20488 {
20489 unsigned alignbits = 0;
20490 switch (et.size)
20491 {
20492 case 16: alignbits = 0x1; break;
20493 case 32: alignbits = 0x3; break;
20494 default: ;
20495 }
20496 inst.instruction |= alignbits << 4;
20497 }
5287ad62
JB
20498 break;
20499
20500 case 1: /* VLD2 / VST2. */
aa8a0863
TS
20501 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 16,
20502 16, 32, 32, 64, -1);
5287ad62 20503 if (align_good == FAIL)
477330fc 20504 return;
aa8a0863 20505 if (do_alignment)
477330fc 20506 inst.instruction |= 1 << 4;
5287ad62
JB
20507 break;
20508
20509 case 2: /* VLD3 / VST3. */
20510 constraint (inst.operands[1].immisalign,
477330fc 20511 _("can't use alignment with this instruction"));
5287ad62
JB
20512 break;
20513
20514 case 3: /* VLD4 / VST4. */
aa8a0863 20515 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
477330fc 20516 16, 64, 32, 64, 32, 128, -1);
5287ad62 20517 if (align_good == FAIL)
477330fc 20518 return;
aa8a0863 20519 if (do_alignment)
477330fc
RM
20520 {
20521 unsigned alignbits = 0;
20522 switch (et.size)
20523 {
20524 case 8: alignbits = 0x1; break;
20525 case 16: alignbits = 0x1; break;
20526 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
20527 default: ;
20528 }
20529 inst.instruction |= alignbits << 4;
20530 }
5287ad62
JB
20531 break;
20532
20533 default: ;
20534 }
20535
20536 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
20537 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
20538 inst.instruction |= 1 << (4 + logsize);
5f4273c7 20539
5287ad62
JB
20540 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
20541 inst.instruction |= logsize << 10;
20542}
20543
20544/* Encode single n-element structure to all lanes VLD<n> instructions. */
20545
20546static void
20547do_neon_ld_dup (void)
20548{
037e8744 20549 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
aa8a0863 20550 int align_good, do_alignment = 0;
5287ad62 20551
dcbf9037
JB
20552 if (et.type == NT_invtype)
20553 return;
20554
5287ad62
JB
20555 switch ((inst.instruction >> 8) & 3)
20556 {
20557 case 0: /* VLD1. */
9c2799c2 20558 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
5287ad62 20559 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
aa8a0863 20560 &do_alignment, 16, 16, 32, 32, -1);
5287ad62 20561 if (align_good == FAIL)
477330fc 20562 return;
5287ad62 20563 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
477330fc
RM
20564 {
20565 case 1: break;
20566 case 2: inst.instruction |= 1 << 5; break;
20567 default: first_error (_("bad list length")); return;
20568 }
5287ad62
JB
20569 inst.instruction |= neon_logbits (et.size) << 6;
20570 break;
20571
20572 case 1: /* VLD2. */
20573 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
aa8a0863
TS
20574 &do_alignment, 8, 16, 16, 32, 32, 64,
20575 -1);
5287ad62 20576 if (align_good == FAIL)
477330fc 20577 return;
5287ad62 20578 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
477330fc 20579 _("bad list length"));
5287ad62 20580 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
477330fc 20581 inst.instruction |= 1 << 5;
5287ad62
JB
20582 inst.instruction |= neon_logbits (et.size) << 6;
20583 break;
20584
20585 case 2: /* VLD3. */
20586 constraint (inst.operands[1].immisalign,
477330fc 20587 _("can't use alignment with this instruction"));
5287ad62 20588 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
477330fc 20589 _("bad list length"));
5287ad62 20590 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
477330fc 20591 inst.instruction |= 1 << 5;
5287ad62
JB
20592 inst.instruction |= neon_logbits (et.size) << 6;
20593 break;
20594
20595 case 3: /* VLD4. */
20596 {
477330fc 20597 int align = inst.operands[1].imm >> 8;
aa8a0863 20598 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
477330fc
RM
20599 16, 64, 32, 64, 32, 128, -1);
20600 if (align_good == FAIL)
20601 return;
20602 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
20603 _("bad list length"));
20604 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
20605 inst.instruction |= 1 << 5;
20606 if (et.size == 32 && align == 128)
20607 inst.instruction |= 0x3 << 6;
20608 else
20609 inst.instruction |= neon_logbits (et.size) << 6;
5287ad62
JB
20610 }
20611 break;
20612
20613 default: ;
20614 }
20615
aa8a0863 20616 inst.instruction |= do_alignment << 4;
5287ad62
JB
20617}
20618
20619/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
20620 apart from bits [11:4]. */
20621
20622static void
20623do_neon_ldx_stx (void)
20624{
b1a769ed
DG
20625 if (inst.operands[1].isreg)
20626 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
20627
5287ad62
JB
20628 switch (NEON_LANE (inst.operands[0].imm))
20629 {
20630 case NEON_INTERLEAVE_LANES:
88714cb8 20631 NEON_ENCODE (INTERLV, inst);
5287ad62
JB
20632 do_neon_ld_st_interleave ();
20633 break;
5f4273c7 20634
5287ad62 20635 case NEON_ALL_LANES:
88714cb8 20636 NEON_ENCODE (DUP, inst);
2d51fb74
JB
20637 if (inst.instruction == N_INV)
20638 {
20639 first_error ("only loads support such operands");
20640 break;
20641 }
5287ad62
JB
20642 do_neon_ld_dup ();
20643 break;
5f4273c7 20644
5287ad62 20645 default:
88714cb8 20646 NEON_ENCODE (LANE, inst);
5287ad62
JB
20647 do_neon_ld_st_lane ();
20648 }
20649
20650 /* L bit comes from bit mask. */
20651 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20652 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20653 inst.instruction |= inst.operands[1].reg << 16;
5f4273c7 20654
5287ad62
JB
20655 if (inst.operands[1].postind)
20656 {
20657 int postreg = inst.operands[1].imm & 0xf;
20658 constraint (!inst.operands[1].immisreg,
477330fc 20659 _("post-index must be a register"));
5287ad62 20660 constraint (postreg == 0xd || postreg == 0xf,
477330fc 20661 _("bad register for post-index"));
5287ad62
JB
20662 inst.instruction |= postreg;
20663 }
4f2374c7 20664 else
5287ad62 20665 {
4f2374c7 20666 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
e2b0ab59
AV
20667 constraint (inst.relocs[0].exp.X_op != O_constant
20668 || inst.relocs[0].exp.X_add_number != 0,
4f2374c7
WN
20669 BAD_ADDR_MODE);
20670
20671 if (inst.operands[1].writeback)
20672 {
20673 inst.instruction |= 0xd;
20674 }
20675 else
20676 inst.instruction |= 0xf;
5287ad62 20677 }
5f4273c7 20678
5287ad62
JB
20679 if (thumb_mode)
20680 inst.instruction |= 0xf9000000;
20681 else
20682 inst.instruction |= 0xf4000000;
20683}
33399f07
MGD
20684
20685/* FP v8. */
20686static void
20687do_vfp_nsyn_fpv8 (enum neon_shape rs)
20688{
a715796b
TG
20689 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20690 D register operands. */
20691 if (neon_shape_class[rs] == SC_DOUBLE)
20692 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
20693 _(BAD_FPU));
20694
33399f07
MGD
20695 NEON_ENCODE (FPV8, inst);
20696
9db2f6b4
RL
20697 if (rs == NS_FFF || rs == NS_HHH)
20698 {
20699 do_vfp_sp_dyadic ();
20700
20701 /* ARMv8.2 fp16 instruction. */
20702 if (rs == NS_HHH)
20703 do_scalar_fp16_v82_encode ();
20704 }
33399f07
MGD
20705 else
20706 do_vfp_dp_rd_rn_rm ();
20707
20708 if (rs == NS_DDD)
20709 inst.instruction |= 0x100;
20710
20711 inst.instruction |= 0xf0000000;
20712}
20713
20714static void
20715do_vsel (void)
20716{
5ee91343 20717 set_pred_insn_type (OUTSIDE_PRED_INSN);
33399f07
MGD
20718
20719 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
20720 first_error (_("invalid instruction shape"));
20721}
20722
73924fbc
MGD
20723static void
20724do_vmaxnm (void)
20725{
935295b5
AV
20726 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20727 set_pred_insn_type (OUTSIDE_PRED_INSN);
73924fbc
MGD
20728
20729 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
20730 return;
20731
64c350f2 20732 if (!check_simd_pred_availability (TRUE, NEON_CHECK_CC | NEON_CHECK_ARCH8))
73924fbc
MGD
20733 return;
20734
cc933301 20735 neon_dyadic_misc (NT_untyped, N_F_16_32, 0);
73924fbc
MGD
20736}
20737
30bdf752
MGD
20738static void
20739do_vrint_1 (enum neon_cvt_mode mode)
20740{
9db2f6b4 20741 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_QQ, NS_NULL);
30bdf752
MGD
20742 struct neon_type_el et;
20743
20744 if (rs == NS_NULL)
20745 return;
20746
a715796b
TG
20747 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20748 D register operands. */
20749 if (neon_shape_class[rs] == SC_DOUBLE)
20750 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
20751 _(BAD_FPU));
20752
9db2f6b4
RL
20753 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY
20754 | N_VFP);
30bdf752
MGD
20755 if (et.type != NT_invtype)
20756 {
20757 /* VFP encodings. */
20758 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
20759 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
5ee91343 20760 set_pred_insn_type (OUTSIDE_PRED_INSN);
30bdf752
MGD
20761
20762 NEON_ENCODE (FPV8, inst);
9db2f6b4 20763 if (rs == NS_FF || rs == NS_HH)
30bdf752
MGD
20764 do_vfp_sp_monadic ();
20765 else
20766 do_vfp_dp_rd_rm ();
20767
20768 switch (mode)
20769 {
20770 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
20771 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
20772 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
20773 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
20774 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
20775 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
20776 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
20777 default: abort ();
20778 }
20779
20780 inst.instruction |= (rs == NS_DD) << 8;
20781 do_vfp_cond_or_thumb ();
9db2f6b4
RL
20782
20783 /* ARMv8.2 fp16 vrint instruction. */
20784 if (rs == NS_HH)
20785 do_scalar_fp16_v82_encode ();
30bdf752
MGD
20786 }
20787 else
20788 {
20789 /* Neon encodings (or something broken...). */
20790 inst.error = NULL;
cc933301 20791 et = neon_check_type (2, rs, N_EQK, N_F_16_32 | N_KEY);
30bdf752
MGD
20792
20793 if (et.type == NT_invtype)
20794 return;
20795
64c350f2
AV
20796 if (!check_simd_pred_availability (TRUE,
20797 NEON_CHECK_CC | NEON_CHECK_ARCH8))
30bdf752
MGD
20798 return;
20799
a710b305
AV
20800 NEON_ENCODE (FLOAT, inst);
20801
30bdf752
MGD
20802 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20803 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20804 inst.instruction |= LOW4 (inst.operands[1].reg);
20805 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20806 inst.instruction |= neon_quad (rs) << 6;
cc933301
JW
20807 /* Mask off the original size bits and reencode them. */
20808 inst.instruction = ((inst.instruction & 0xfff3ffff)
20809 | neon_logbits (et.size) << 18);
20810
30bdf752
MGD
20811 switch (mode)
20812 {
20813 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
20814 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
20815 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
20816 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
20817 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
20818 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
20819 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
20820 default: abort ();
20821 }
20822
20823 if (thumb_mode)
20824 inst.instruction |= 0xfc000000;
20825 else
20826 inst.instruction |= 0xf0000000;
20827 }
20828}
20829
20830static void
20831do_vrintx (void)
20832{
20833 do_vrint_1 (neon_cvt_mode_x);
20834}
20835
20836static void
20837do_vrintz (void)
20838{
20839 do_vrint_1 (neon_cvt_mode_z);
20840}
20841
20842static void
20843do_vrintr (void)
20844{
20845 do_vrint_1 (neon_cvt_mode_r);
20846}
20847
20848static void
20849do_vrinta (void)
20850{
20851 do_vrint_1 (neon_cvt_mode_a);
20852}
20853
20854static void
20855do_vrintn (void)
20856{
20857 do_vrint_1 (neon_cvt_mode_n);
20858}
20859
20860static void
20861do_vrintp (void)
20862{
20863 do_vrint_1 (neon_cvt_mode_p);
20864}
20865
20866static void
20867do_vrintm (void)
20868{
20869 do_vrint_1 (neon_cvt_mode_m);
20870}
20871
c28eeff2
SN
20872static unsigned
20873neon_scalar_for_vcmla (unsigned opnd, unsigned elsize)
20874{
20875 unsigned regno = NEON_SCALAR_REG (opnd);
20876 unsigned elno = NEON_SCALAR_INDEX (opnd);
20877
20878 if (elsize == 16 && elno < 2 && regno < 16)
20879 return regno | (elno << 4);
20880 else if (elsize == 32 && elno == 0)
20881 return regno;
20882
20883 first_error (_("scalar out of range"));
20884 return 0;
20885}
20886
20887static void
20888do_vcmla (void)
20889{
5d281bf0
AV
20890 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)
20891 && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
20892 || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
e2b0ab59
AV
20893 constraint (inst.relocs[0].exp.X_op != O_constant,
20894 _("expression too complex"));
20895 unsigned rot = inst.relocs[0].exp.X_add_number;
c28eeff2
SN
20896 constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
20897 _("immediate out of range"));
20898 rot /= 90;
5d281bf0 20899
64c350f2
AV
20900 if (!check_simd_pred_availability (TRUE,
20901 NEON_CHECK_ARCH8 | NEON_CHECK_CC))
5d281bf0
AV
20902 return;
20903
c28eeff2
SN
20904 if (inst.operands[2].isscalar)
20905 {
5d281bf0
AV
20906 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
20907 first_error (_("invalid instruction shape"));
c28eeff2
SN
20908 enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL);
20909 unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
20910 N_KEY | N_F16 | N_F32).size;
20911 unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size);
20912 inst.is_neon = 1;
20913 inst.instruction = 0xfe000800;
20914 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20915 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20916 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20917 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
20918 inst.instruction |= LOW4 (m);
20919 inst.instruction |= HI1 (m) << 5;
20920 inst.instruction |= neon_quad (rs) << 6;
20921 inst.instruction |= rot << 20;
20922 inst.instruction |= (size == 32) << 23;
20923 }
20924 else
20925 {
5d281bf0
AV
20926 enum neon_shape rs;
20927 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
20928 rs = neon_select_shape (NS_QQQI, NS_NULL);
20929 else
20930 rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
20931
c28eeff2
SN
20932 unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
20933 N_KEY | N_F16 | N_F32).size;
5d281bf0
AV
20934 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) && size == 32
20935 && (inst.operands[0].reg == inst.operands[1].reg
20936 || inst.operands[0].reg == inst.operands[2].reg))
20937 as_tsktsk (BAD_MVE_SRCDEST);
20938
c28eeff2
SN
20939 neon_three_same (neon_quad (rs), 0, -1);
20940 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
20941 inst.instruction |= 0xfc200800;
20942 inst.instruction |= rot << 23;
20943 inst.instruction |= (size == 32) << 20;
20944 }
20945}
20946
20947static void
20948do_vcadd (void)
20949{
5d281bf0
AV
20950 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
20951 && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
20952 || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
e2b0ab59
AV
20953 constraint (inst.relocs[0].exp.X_op != O_constant,
20954 _("expression too complex"));
5d281bf0 20955
e2b0ab59 20956 unsigned rot = inst.relocs[0].exp.X_add_number;
c28eeff2 20957 constraint (rot != 90 && rot != 270, _("immediate out of range"));
5d281bf0
AV
20958 enum neon_shape rs;
20959 struct neon_type_el et;
20960 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20961 {
20962 rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
20963 et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32);
20964 }
20965 else
20966 {
20967 rs = neon_select_shape (NS_QQQI, NS_NULL);
20968 et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32 | N_I8
20969 | N_I16 | N_I32);
20970 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
20971 as_tsktsk (_("Warning: 32-bit element size and same first and third "
20972 "operand makes instruction UNPREDICTABLE"));
20973 }
20974
20975 if (et.type == NT_invtype)
20976 return;
20977
64c350f2
AV
20978 if (!check_simd_pred_availability (et.type == NT_float,
20979 NEON_CHECK_ARCH8 | NEON_CHECK_CC))
5d281bf0
AV
20980 return;
20981
20982 if (et.type == NT_float)
20983 {
20984 neon_three_same (neon_quad (rs), 0, -1);
20985 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
20986 inst.instruction |= 0xfc800800;
20987 inst.instruction |= (rot == 270) << 24;
20988 inst.instruction |= (et.size == 32) << 20;
20989 }
20990 else
20991 {
20992 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
20993 inst.instruction = 0xfe000f00;
20994 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20995 inst.instruction |= neon_logbits (et.size) << 20;
20996 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20997 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20998 inst.instruction |= (rot == 270) << 12;
20999 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
21000 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
21001 inst.instruction |= LOW4 (inst.operands[2].reg);
21002 inst.is_neon = 1;
21003 }
c28eeff2
SN
21004}
21005
c604a79a
JW
21006/* Dot Product instructions encoding support. */
21007
21008static void
21009do_neon_dotproduct (int unsigned_p)
21010{
21011 enum neon_shape rs;
21012 unsigned scalar_oprd2 = 0;
21013 int high8;
21014
21015 if (inst.cond != COND_ALWAYS)
21016 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21017 "is UNPREDICTABLE"));
21018
21019 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
21020 _(BAD_FPU));
21021
21022 /* Dot Product instructions are in three-same D/Q register format or the third
21023 operand can be a scalar index register. */
21024 if (inst.operands[2].isscalar)
21025 {
21026 scalar_oprd2 = neon_scalar_for_mul (inst.operands[2].reg, 32);
21027 high8 = 0xfe000000;
21028 rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
21029 }
21030 else
21031 {
21032 high8 = 0xfc000000;
21033 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
21034 }
21035
21036 if (unsigned_p)
21037 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_U8);
21038 else
21039 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_S8);
21040
21041 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21042 Product instruction, so we pass 0 as the "ubit" parameter. And the
21043 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21044 neon_three_same (neon_quad (rs), 0, 32);
21045
21046 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21047 different NEON three-same encoding. */
21048 inst.instruction &= 0x00ffffff;
21049 inst.instruction |= high8;
21050 /* Encode 'U' bit which indicates signedness. */
21051 inst.instruction |= (unsigned_p ? 1 : 0) << 4;
21052 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21053 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21054 the instruction encoding. */
21055 if (inst.operands[2].isscalar)
21056 {
21057 inst.instruction &= 0xffffffd0;
21058 inst.instruction |= LOW4 (scalar_oprd2);
21059 inst.instruction |= HI1 (scalar_oprd2) << 5;
21060 }
21061}
21062
21063/* Dot Product instructions for signed integer. */
21064
21065static void
21066do_neon_dotproduct_s (void)
21067{
21068 return do_neon_dotproduct (0);
21069}
21070
21071/* Dot Product instructions for unsigned integer. */
21072
21073static void
21074do_neon_dotproduct_u (void)
21075{
21076 return do_neon_dotproduct (1);
21077}
21078
91ff7894
MGD
21079/* Crypto v1 instructions. */
21080static void
21081do_crypto_2op_1 (unsigned elttype, int op)
21082{
5ee91343 21083 set_pred_insn_type (OUTSIDE_PRED_INSN);
91ff7894
MGD
21084
21085 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
21086 == NT_invtype)
21087 return;
21088
21089 inst.error = NULL;
21090
21091 NEON_ENCODE (INTEGER, inst);
21092 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21093 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21094 inst.instruction |= LOW4 (inst.operands[1].reg);
21095 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
21096 if (op != -1)
21097 inst.instruction |= op << 6;
21098
21099 if (thumb_mode)
21100 inst.instruction |= 0xfc000000;
21101 else
21102 inst.instruction |= 0xf0000000;
21103}
21104
48adcd8e
MGD
21105static void
21106do_crypto_3op_1 (int u, int op)
21107{
5ee91343 21108 set_pred_insn_type (OUTSIDE_PRED_INSN);
48adcd8e
MGD
21109
21110 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
21111 N_32 | N_UNT | N_KEY).type == NT_invtype)
21112 return;
21113
21114 inst.error = NULL;
21115
21116 NEON_ENCODE (INTEGER, inst);
21117 neon_three_same (1, u, 8 << op);
21118}
21119
91ff7894
MGD
21120static void
21121do_aese (void)
21122{
21123 do_crypto_2op_1 (N_8, 0);
21124}
21125
21126static void
21127do_aesd (void)
21128{
21129 do_crypto_2op_1 (N_8, 1);
21130}
21131
21132static void
21133do_aesmc (void)
21134{
21135 do_crypto_2op_1 (N_8, 2);
21136}
21137
21138static void
21139do_aesimc (void)
21140{
21141 do_crypto_2op_1 (N_8, 3);
21142}
21143
48adcd8e
MGD
21144static void
21145do_sha1c (void)
21146{
21147 do_crypto_3op_1 (0, 0);
21148}
21149
21150static void
21151do_sha1p (void)
21152{
21153 do_crypto_3op_1 (0, 1);
21154}
21155
21156static void
21157do_sha1m (void)
21158{
21159 do_crypto_3op_1 (0, 2);
21160}
21161
21162static void
21163do_sha1su0 (void)
21164{
21165 do_crypto_3op_1 (0, 3);
21166}
91ff7894 21167
48adcd8e
MGD
21168static void
21169do_sha256h (void)
21170{
21171 do_crypto_3op_1 (1, 0);
21172}
21173
21174static void
21175do_sha256h2 (void)
21176{
21177 do_crypto_3op_1 (1, 1);
21178}
21179
21180static void
21181do_sha256su1 (void)
21182{
21183 do_crypto_3op_1 (1, 2);
21184}
3c9017d2
MGD
21185
21186static void
21187do_sha1h (void)
21188{
21189 do_crypto_2op_1 (N_32, -1);
21190}
21191
21192static void
21193do_sha1su1 (void)
21194{
21195 do_crypto_2op_1 (N_32, 0);
21196}
21197
21198static void
21199do_sha256su0 (void)
21200{
21201 do_crypto_2op_1 (N_32, 1);
21202}
dd5181d5
KT
21203
21204static void
21205do_crc32_1 (unsigned int poly, unsigned int sz)
21206{
21207 unsigned int Rd = inst.operands[0].reg;
21208 unsigned int Rn = inst.operands[1].reg;
21209 unsigned int Rm = inst.operands[2].reg;
21210
5ee91343 21211 set_pred_insn_type (OUTSIDE_PRED_INSN);
dd5181d5
KT
21212 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
21213 inst.instruction |= LOW4 (Rn) << 16;
21214 inst.instruction |= LOW4 (Rm);
21215 inst.instruction |= sz << (thumb_mode ? 4 : 21);
21216 inst.instruction |= poly << (thumb_mode ? 20 : 9);
21217
21218 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
21219 as_warn (UNPRED_REG ("r15"));
dd5181d5
KT
21220}
21221
21222static void
21223do_crc32b (void)
21224{
21225 do_crc32_1 (0, 0);
21226}
21227
21228static void
21229do_crc32h (void)
21230{
21231 do_crc32_1 (0, 1);
21232}
21233
21234static void
21235do_crc32w (void)
21236{
21237 do_crc32_1 (0, 2);
21238}
21239
21240static void
21241do_crc32cb (void)
21242{
21243 do_crc32_1 (1, 0);
21244}
21245
21246static void
21247do_crc32ch (void)
21248{
21249 do_crc32_1 (1, 1);
21250}
21251
21252static void
21253do_crc32cw (void)
21254{
21255 do_crc32_1 (1, 2);
21256}
21257
49e8a725
SN
21258static void
21259do_vjcvt (void)
21260{
21261 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
21262 _(BAD_FPU));
21263 neon_check_type (2, NS_FD, N_S32, N_F64);
21264 do_vfp_sp_dp_cvt ();
21265 do_vfp_cond_or_thumb ();
21266}
21267
5287ad62
JB
21268\f
21269/* Overall per-instruction processing. */
21270
21271/* We need to be able to fix up arbitrary expressions in some statements.
21272 This is so that we can handle symbols that are an arbitrary distance from
21273 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
21274 which returns part of an address in a form which will be valid for
21275 a data instruction. We do this by pushing the expression into a symbol
21276 in the expr_section, and creating a fix for that. */
21277
21278static void
21279fix_new_arm (fragS * frag,
21280 int where,
21281 short int size,
21282 expressionS * exp,
21283 int pc_rel,
21284 int reloc)
21285{
21286 fixS * new_fix;
21287
21288 switch (exp->X_op)
21289 {
21290 case O_constant:
6e7ce2cd
PB
21291 if (pc_rel)
21292 {
21293 /* Create an absolute valued symbol, so we have something to
477330fc
RM
21294 refer to in the object file. Unfortunately for us, gas's
21295 generic expression parsing will already have folded out
21296 any use of .set foo/.type foo %function that may have
21297 been used to set type information of the target location,
21298 that's being specified symbolically. We have to presume
21299 the user knows what they are doing. */
6e7ce2cd
PB
21300 char name[16 + 8];
21301 symbolS *symbol;
21302
21303 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
21304
21305 symbol = symbol_find_or_make (name);
21306 S_SET_SEGMENT (symbol, absolute_section);
21307 symbol_set_frag (symbol, &zero_address_frag);
21308 S_SET_VALUE (symbol, exp->X_add_number);
21309 exp->X_op = O_symbol;
21310 exp->X_add_symbol = symbol;
21311 exp->X_add_number = 0;
21312 }
21313 /* FALLTHROUGH */
5287ad62
JB
21314 case O_symbol:
21315 case O_add:
21316 case O_subtract:
21d799b5 21317 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
477330fc 21318 (enum bfd_reloc_code_real) reloc);
5287ad62
JB
21319 break;
21320
21321 default:
21d799b5 21322 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
477330fc 21323 pc_rel, (enum bfd_reloc_code_real) reloc);
5287ad62
JB
21324 break;
21325 }
21326
21327 /* Mark whether the fix is to a THUMB instruction, or an ARM
21328 instruction. */
21329 new_fix->tc_fix_data = thumb_mode;
21330}
21331
21332/* Create a frg for an instruction requiring relaxation. */
21333static void
21334output_relax_insn (void)
21335{
21336 char * to;
21337 symbolS *sym;
0110f2b8
PB
21338 int offset;
21339
6e1cb1a6
PB
21340 /* The size of the instruction is unknown, so tie the debug info to the
21341 start of the instruction. */
21342 dwarf2_emit_insn (0);
6e1cb1a6 21343
e2b0ab59 21344 switch (inst.relocs[0].exp.X_op)
0110f2b8
PB
21345 {
21346 case O_symbol:
e2b0ab59
AV
21347 sym = inst.relocs[0].exp.X_add_symbol;
21348 offset = inst.relocs[0].exp.X_add_number;
0110f2b8
PB
21349 break;
21350 case O_constant:
21351 sym = NULL;
e2b0ab59 21352 offset = inst.relocs[0].exp.X_add_number;
0110f2b8
PB
21353 break;
21354 default:
e2b0ab59 21355 sym = make_expr_symbol (&inst.relocs[0].exp);
0110f2b8
PB
21356 offset = 0;
21357 break;
21358 }
21359 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
21360 inst.relax, sym, offset, NULL/*offset, opcode*/);
21361 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
0110f2b8
PB
21362}
21363
21364/* Write a 32-bit thumb instruction to buf. */
21365static void
21366put_thumb32_insn (char * buf, unsigned long insn)
21367{
21368 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
21369 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
21370}
21371
b99bd4ef 21372static void
c19d1205 21373output_inst (const char * str)
b99bd4ef 21374{
c19d1205 21375 char * to = NULL;
b99bd4ef 21376
c19d1205 21377 if (inst.error)
b99bd4ef 21378 {
c19d1205 21379 as_bad ("%s -- `%s'", inst.error, str);
b99bd4ef
NC
21380 return;
21381 }
5f4273c7
NC
21382 if (inst.relax)
21383 {
21384 output_relax_insn ();
0110f2b8 21385 return;
5f4273c7 21386 }
c19d1205
ZW
21387 if (inst.size == 0)
21388 return;
b99bd4ef 21389
c19d1205 21390 to = frag_more (inst.size);
8dc2430f
NC
21391 /* PR 9814: Record the thumb mode into the current frag so that we know
21392 what type of NOP padding to use, if necessary. We override any previous
21393 setting so that if the mode has changed then the NOPS that we use will
21394 match the encoding of the last instruction in the frag. */
cd000bff 21395 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
c19d1205
ZW
21396
21397 if (thumb_mode && (inst.size > THUMB_SIZE))
b99bd4ef 21398 {
9c2799c2 21399 gas_assert (inst.size == (2 * THUMB_SIZE));
0110f2b8 21400 put_thumb32_insn (to, inst.instruction);
b99bd4ef 21401 }
c19d1205 21402 else if (inst.size > INSN_SIZE)
b99bd4ef 21403 {
9c2799c2 21404 gas_assert (inst.size == (2 * INSN_SIZE));
c19d1205
ZW
21405 md_number_to_chars (to, inst.instruction, INSN_SIZE);
21406 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
b99bd4ef 21407 }
c19d1205
ZW
21408 else
21409 md_number_to_chars (to, inst.instruction, inst.size);
b99bd4ef 21410
e2b0ab59
AV
21411 int r;
21412 for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
21413 {
21414 if (inst.relocs[r].type != BFD_RELOC_UNUSED)
21415 fix_new_arm (frag_now, to - frag_now->fr_literal,
21416 inst.size, & inst.relocs[r].exp, inst.relocs[r].pc_rel,
21417 inst.relocs[r].type);
21418 }
b99bd4ef 21419
c19d1205 21420 dwarf2_emit_insn (inst.size);
c19d1205 21421}
b99bd4ef 21422
e07e6e58
NC
21423static char *
21424output_it_inst (int cond, int mask, char * to)
21425{
21426 unsigned long instruction = 0xbf00;
21427
21428 mask &= 0xf;
21429 instruction |= mask;
21430 instruction |= cond << 4;
21431
21432 if (to == NULL)
21433 {
21434 to = frag_more (2);
21435#ifdef OBJ_ELF
21436 dwarf2_emit_insn (2);
21437#endif
21438 }
21439
21440 md_number_to_chars (to, instruction, 2);
21441
21442 return to;
21443}
21444
c19d1205
ZW
21445/* Tag values used in struct asm_opcode's tag field. */
21446enum opcode_tag
21447{
21448 OT_unconditional, /* Instruction cannot be conditionalized.
21449 The ARM condition field is still 0xE. */
21450 OT_unconditionalF, /* Instruction cannot be conditionalized
21451 and carries 0xF in its ARM condition field. */
21452 OT_csuffix, /* Instruction takes a conditional suffix. */
5ee91343
AV
21453 OT_csuffixF, /* Some forms of the instruction take a scalar
21454 conditional suffix, others place 0xF where the
21455 condition field would be, others take a vector
21456 conditional suffix. */
c19d1205
ZW
21457 OT_cinfix3, /* Instruction takes a conditional infix,
21458 beginning at character index 3. (In
21459 unified mode, it becomes a suffix.) */
088fa78e
KH
21460 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
21461 tsts, cmps, cmns, and teqs. */
e3cb604e
PB
21462 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
21463 character index 3, even in unified mode. Used for
21464 legacy instructions where suffix and infix forms
21465 may be ambiguous. */
c19d1205 21466 OT_csuf_or_in3, /* Instruction takes either a conditional
e3cb604e 21467 suffix or an infix at character index 3. */
c19d1205
ZW
21468 OT_odd_infix_unc, /* This is the unconditional variant of an
21469 instruction that takes a conditional infix
21470 at an unusual position. In unified mode,
21471 this variant will accept a suffix. */
21472 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
21473 are the conditional variants of instructions that
21474 take conditional infixes in unusual positions.
21475 The infix appears at character index
21476 (tag - OT_odd_infix_0). These are not accepted
21477 in unified mode. */
21478};
b99bd4ef 21479
c19d1205
ZW
21480/* Subroutine of md_assemble, responsible for looking up the primary
21481 opcode from the mnemonic the user wrote. STR points to the
21482 beginning of the mnemonic.
21483
21484 This is not simply a hash table lookup, because of conditional
21485 variants. Most instructions have conditional variants, which are
21486 expressed with a _conditional affix_ to the mnemonic. If we were
21487 to encode each conditional variant as a literal string in the opcode
21488 table, it would have approximately 20,000 entries.
21489
21490 Most mnemonics take this affix as a suffix, and in unified syntax,
21491 'most' is upgraded to 'all'. However, in the divided syntax, some
21492 instructions take the affix as an infix, notably the s-variants of
21493 the arithmetic instructions. Of those instructions, all but six
21494 have the infix appear after the third character of the mnemonic.
21495
21496 Accordingly, the algorithm for looking up primary opcodes given
21497 an identifier is:
21498
21499 1. Look up the identifier in the opcode table.
21500 If we find a match, go to step U.
21501
21502 2. Look up the last two characters of the identifier in the
21503 conditions table. If we find a match, look up the first N-2
21504 characters of the identifier in the opcode table. If we
21505 find a match, go to step CE.
21506
21507 3. Look up the fourth and fifth characters of the identifier in
21508 the conditions table. If we find a match, extract those
21509 characters from the identifier, and look up the remaining
21510 characters in the opcode table. If we find a match, go
21511 to step CM.
21512
21513 4. Fail.
21514
21515 U. Examine the tag field of the opcode structure, in case this is
21516 one of the six instructions with its conditional infix in an
21517 unusual place. If it is, the tag tells us where to find the
21518 infix; look it up in the conditions table and set inst.cond
21519 accordingly. Otherwise, this is an unconditional instruction.
21520 Again set inst.cond accordingly. Return the opcode structure.
21521
21522 CE. Examine the tag field to make sure this is an instruction that
21523 should receive a conditional suffix. If it is not, fail.
21524 Otherwise, set inst.cond from the suffix we already looked up,
21525 and return the opcode structure.
21526
21527 CM. Examine the tag field to make sure this is an instruction that
21528 should receive a conditional infix after the third character.
21529 If it is not, fail. Otherwise, undo the edits to the current
21530 line of input and proceed as for case CE. */
21531
21532static const struct asm_opcode *
21533opcode_lookup (char **str)
21534{
21535 char *end, *base;
21536 char *affix;
21537 const struct asm_opcode *opcode;
21538 const struct asm_cond *cond;
e3cb604e 21539 char save[2];
c19d1205
ZW
21540
21541 /* Scan up to the end of the mnemonic, which must end in white space,
721a8186 21542 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
c19d1205 21543 for (base = end = *str; *end != '\0'; end++)
721a8186 21544 if (*end == ' ' || *end == '.')
c19d1205 21545 break;
b99bd4ef 21546
c19d1205 21547 if (end == base)
c921be7d 21548 return NULL;
b99bd4ef 21549
5287ad62 21550 /* Handle a possible width suffix and/or Neon type suffix. */
c19d1205 21551 if (end[0] == '.')
b99bd4ef 21552 {
5287ad62 21553 int offset = 2;
5f4273c7 21554
267d2029 21555 /* The .w and .n suffixes are only valid if the unified syntax is in
477330fc 21556 use. */
267d2029 21557 if (unified_syntax && end[1] == 'w')
c19d1205 21558 inst.size_req = 4;
267d2029 21559 else if (unified_syntax && end[1] == 'n')
c19d1205
ZW
21560 inst.size_req = 2;
21561 else
477330fc 21562 offset = 0;
5287ad62
JB
21563
21564 inst.vectype.elems = 0;
21565
21566 *str = end + offset;
b99bd4ef 21567
5f4273c7 21568 if (end[offset] == '.')
5287ad62 21569 {
267d2029 21570 /* See if we have a Neon type suffix (possible in either unified or
477330fc
RM
21571 non-unified ARM syntax mode). */
21572 if (parse_neon_type (&inst.vectype, str) == FAIL)
c921be7d 21573 return NULL;
477330fc 21574 }
5287ad62 21575 else if (end[offset] != '\0' && end[offset] != ' ')
477330fc 21576 return NULL;
b99bd4ef 21577 }
c19d1205
ZW
21578 else
21579 *str = end;
b99bd4ef 21580
c19d1205 21581 /* Look for unaffixed or special-case affixed mnemonic. */
21d799b5 21582 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
477330fc 21583 end - base);
c19d1205 21584 if (opcode)
b99bd4ef 21585 {
c19d1205
ZW
21586 /* step U */
21587 if (opcode->tag < OT_odd_infix_0)
b99bd4ef 21588 {
c19d1205
ZW
21589 inst.cond = COND_ALWAYS;
21590 return opcode;
b99bd4ef 21591 }
b99bd4ef 21592
278df34e 21593 if (warn_on_deprecated && unified_syntax)
5c3696f8 21594 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
c19d1205 21595 affix = base + (opcode->tag - OT_odd_infix_0);
21d799b5 21596 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
9c2799c2 21597 gas_assert (cond);
b99bd4ef 21598
c19d1205
ZW
21599 inst.cond = cond->value;
21600 return opcode;
21601 }
5ee91343
AV
21602 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
21603 {
21604 /* Cannot have a conditional suffix on a mnemonic of less than a character.
21605 */
21606 if (end - base < 2)
21607 return NULL;
21608 affix = end - 1;
21609 cond = (const struct asm_cond *) hash_find_n (arm_vcond_hsh, affix, 1);
21610 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
21611 affix - base);
21612 /* If this opcode can not be vector predicated then don't accept it with a
21613 vector predication code. */
21614 if (opcode && !opcode->mayBeVecPred)
21615 opcode = NULL;
21616 }
21617 if (!opcode || !cond)
21618 {
21619 /* Cannot have a conditional suffix on a mnemonic of less than two
21620 characters. */
21621 if (end - base < 3)
21622 return NULL;
b99bd4ef 21623
5ee91343
AV
21624 /* Look for suffixed mnemonic. */
21625 affix = end - 2;
21626 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
21627 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
21628 affix - base);
21629 }
b99bd4ef 21630
c19d1205
ZW
21631 if (opcode && cond)
21632 {
21633 /* step CE */
21634 switch (opcode->tag)
21635 {
e3cb604e
PB
21636 case OT_cinfix3_legacy:
21637 /* Ignore conditional suffixes matched on infix only mnemonics. */
21638 break;
21639
c19d1205 21640 case OT_cinfix3:
088fa78e 21641 case OT_cinfix3_deprecated:
c19d1205
ZW
21642 case OT_odd_infix_unc:
21643 if (!unified_syntax)
0198d5e6 21644 return NULL;
1a0670f3 21645 /* Fall through. */
c19d1205
ZW
21646
21647 case OT_csuffix:
477330fc 21648 case OT_csuffixF:
c19d1205
ZW
21649 case OT_csuf_or_in3:
21650 inst.cond = cond->value;
21651 return opcode;
21652
21653 case OT_unconditional:
21654 case OT_unconditionalF:
dfa9f0d5 21655 if (thumb_mode)
c921be7d 21656 inst.cond = cond->value;
dfa9f0d5
PB
21657 else
21658 {
c921be7d 21659 /* Delayed diagnostic. */
dfa9f0d5
PB
21660 inst.error = BAD_COND;
21661 inst.cond = COND_ALWAYS;
21662 }
c19d1205 21663 return opcode;
b99bd4ef 21664
c19d1205 21665 default:
c921be7d 21666 return NULL;
c19d1205
ZW
21667 }
21668 }
b99bd4ef 21669
c19d1205
ZW
21670 /* Cannot have a usual-position infix on a mnemonic of less than
21671 six characters (five would be a suffix). */
21672 if (end - base < 6)
c921be7d 21673 return NULL;
b99bd4ef 21674
c19d1205
ZW
21675 /* Look for infixed mnemonic in the usual position. */
21676 affix = base + 3;
21d799b5 21677 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
e3cb604e 21678 if (!cond)
c921be7d 21679 return NULL;
e3cb604e
PB
21680
21681 memcpy (save, affix, 2);
21682 memmove (affix, affix + 2, (end - affix) - 2);
21d799b5 21683 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
477330fc 21684 (end - base) - 2);
e3cb604e
PB
21685 memmove (affix + 2, affix, (end - affix) - 2);
21686 memcpy (affix, save, 2);
21687
088fa78e
KH
21688 if (opcode
21689 && (opcode->tag == OT_cinfix3
21690 || opcode->tag == OT_cinfix3_deprecated
21691 || opcode->tag == OT_csuf_or_in3
21692 || opcode->tag == OT_cinfix3_legacy))
b99bd4ef 21693 {
c921be7d 21694 /* Step CM. */
278df34e 21695 if (warn_on_deprecated && unified_syntax
088fa78e
KH
21696 && (opcode->tag == OT_cinfix3
21697 || opcode->tag == OT_cinfix3_deprecated))
5c3696f8 21698 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
c19d1205
ZW
21699
21700 inst.cond = cond->value;
21701 return opcode;
b99bd4ef
NC
21702 }
21703
c921be7d 21704 return NULL;
b99bd4ef
NC
21705}
21706
e07e6e58
NC
21707/* This function generates an initial IT instruction, leaving its block
21708 virtually open for the new instructions. Eventually,
5ee91343 21709 the mask will be updated by now_pred_add_mask () each time
e07e6e58
NC
21710 a new instruction needs to be included in the IT block.
21711 Finally, the block is closed with close_automatic_it_block ().
21712 The block closure can be requested either from md_assemble (),
21713 a tencode (), or due to a label hook. */
21714
21715static void
21716new_automatic_it_block (int cond)
21717{
5ee91343
AV
21718 now_pred.state = AUTOMATIC_PRED_BLOCK;
21719 now_pred.mask = 0x18;
21720 now_pred.cc = cond;
21721 now_pred.block_length = 1;
cd000bff 21722 mapping_state (MAP_THUMB);
5ee91343
AV
21723 now_pred.insn = output_it_inst (cond, now_pred.mask, NULL);
21724 now_pred.warn_deprecated = FALSE;
21725 now_pred.insn_cond = TRUE;
e07e6e58
NC
21726}
21727
21728/* Close an automatic IT block.
21729 See comments in new_automatic_it_block (). */
21730
21731static void
21732close_automatic_it_block (void)
21733{
5ee91343
AV
21734 now_pred.mask = 0x10;
21735 now_pred.block_length = 0;
e07e6e58
NC
21736}
21737
21738/* Update the mask of the current automatically-generated IT
21739 instruction. See comments in new_automatic_it_block (). */
21740
21741static void
5ee91343 21742now_pred_add_mask (int cond)
e07e6e58
NC
21743{
21744#define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
21745#define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
477330fc 21746 | ((bitvalue) << (nbit)))
e07e6e58 21747 const int resulting_bit = (cond & 1);
c921be7d 21748
5ee91343
AV
21749 now_pred.mask &= 0xf;
21750 now_pred.mask = SET_BIT_VALUE (now_pred.mask,
477330fc 21751 resulting_bit,
5ee91343
AV
21752 (5 - now_pred.block_length));
21753 now_pred.mask = SET_BIT_VALUE (now_pred.mask,
477330fc 21754 1,
5ee91343
AV
21755 ((5 - now_pred.block_length) - 1));
21756 output_it_inst (now_pred.cc, now_pred.mask, now_pred.insn);
e07e6e58
NC
21757
21758#undef CLEAR_BIT
21759#undef SET_BIT_VALUE
e07e6e58
NC
21760}
21761
21762/* The IT blocks handling machinery is accessed through the these functions:
21763 it_fsm_pre_encode () from md_assemble ()
5ee91343
AV
21764 set_pred_insn_type () optional, from the tencode functions
21765 set_pred_insn_type_last () ditto
21766 in_pred_block () ditto
e07e6e58 21767 it_fsm_post_encode () from md_assemble ()
33eaf5de 21768 force_automatic_it_block_close () from label handling functions
e07e6e58
NC
21769
21770 Rationale:
21771 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
477330fc
RM
21772 initializing the IT insn type with a generic initial value depending
21773 on the inst.condition.
e07e6e58 21774 2) During the tencode function, two things may happen:
477330fc 21775 a) The tencode function overrides the IT insn type by
5ee91343
AV
21776 calling either set_pred_insn_type (type) or
21777 set_pred_insn_type_last ().
477330fc 21778 b) The tencode function queries the IT block state by
5ee91343 21779 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
477330fc 21780
5ee91343
AV
21781 Both set_pred_insn_type and in_pred_block run the internal FSM state
21782 handling function (handle_pred_state), because: a) setting the IT insn
477330fc
RM
21783 type may incur in an invalid state (exiting the function),
21784 and b) querying the state requires the FSM to be updated.
21785 Specifically we want to avoid creating an IT block for conditional
21786 branches, so it_fsm_pre_encode is actually a guess and we can't
21787 determine whether an IT block is required until the tencode () routine
21788 has decided what type of instruction this actually it.
5ee91343
AV
21789 Because of this, if set_pred_insn_type and in_pred_block have to be
21790 used, set_pred_insn_type has to be called first.
477330fc 21791
5ee91343
AV
21792 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
21793 that determines the insn IT type depending on the inst.cond code.
477330fc
RM
21794 When a tencode () routine encodes an instruction that can be
21795 either outside an IT block, or, in the case of being inside, has to be
5ee91343 21796 the last one, set_pred_insn_type_last () will determine the proper
477330fc 21797 IT instruction type based on the inst.cond code. Otherwise,
5ee91343 21798 set_pred_insn_type can be called for overriding that logic or
477330fc
RM
21799 for covering other cases.
21800
5ee91343
AV
21801 Calling handle_pred_state () may not transition the IT block state to
21802 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
477330fc 21803 still queried. Instead, if the FSM determines that the state should
5ee91343 21804 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
477330fc
RM
21805 after the tencode () function: that's what it_fsm_post_encode () does.
21806
5ee91343 21807 Since in_pred_block () calls the state handling function to get an
477330fc
RM
21808 updated state, an error may occur (due to invalid insns combination).
21809 In that case, inst.error is set.
21810 Therefore, inst.error has to be checked after the execution of
21811 the tencode () routine.
e07e6e58
NC
21812
21813 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
477330fc 21814 any pending state change (if any) that didn't take place in
5ee91343 21815 handle_pred_state () as explained above. */
e07e6e58
NC
21816
21817static void
21818it_fsm_pre_encode (void)
21819{
21820 if (inst.cond != COND_ALWAYS)
5ee91343 21821 inst.pred_insn_type = INSIDE_IT_INSN;
e07e6e58 21822 else
5ee91343 21823 inst.pred_insn_type = OUTSIDE_PRED_INSN;
e07e6e58 21824
5ee91343 21825 now_pred.state_handled = 0;
e07e6e58
NC
21826}
21827
21828/* IT state FSM handling function. */
5ee91343
AV
21829/* MVE instructions and non-MVE instructions are handled differently because of
21830 the introduction of VPT blocks.
21831 Specifications say that any non-MVE instruction inside a VPT block is
21832 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
21833 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
35c228db 21834 few exceptions we have MVE_UNPREDICABLE_INSN.
5ee91343
AV
21835 The error messages provided depending on the different combinations possible
21836 are described in the cases below:
21837 For 'most' MVE instructions:
21838 1) In an IT block, with an IT code: syntax error
21839 2) In an IT block, with a VPT code: error: must be in a VPT block
21840 3) In an IT block, with no code: warning: UNPREDICTABLE
21841 4) In a VPT block, with an IT code: syntax error
21842 5) In a VPT block, with a VPT code: OK!
21843 6) In a VPT block, with no code: error: missing code
21844 7) Outside a pred block, with an IT code: error: syntax error
21845 8) Outside a pred block, with a VPT code: error: should be in a VPT block
21846 9) Outside a pred block, with no code: OK!
21847 For non-MVE instructions:
21848 10) In an IT block, with an IT code: OK!
21849 11) In an IT block, with a VPT code: syntax error
21850 12) In an IT block, with no code: error: missing code
21851 13) In a VPT block, with an IT code: error: should be in an IT block
21852 14) In a VPT block, with a VPT code: syntax error
21853 15) In a VPT block, with no code: UNPREDICTABLE
21854 16) Outside a pred block, with an IT code: error: should be in an IT block
21855 17) Outside a pred block, with a VPT code: syntax error
21856 18) Outside a pred block, with no code: OK!
21857 */
21858
e07e6e58
NC
21859
21860static int
5ee91343 21861handle_pred_state (void)
e07e6e58 21862{
5ee91343
AV
21863 now_pred.state_handled = 1;
21864 now_pred.insn_cond = FALSE;
e07e6e58 21865
5ee91343 21866 switch (now_pred.state)
e07e6e58 21867 {
5ee91343
AV
21868 case OUTSIDE_PRED_BLOCK:
21869 switch (inst.pred_insn_type)
e07e6e58 21870 {
35c228db 21871 case MVE_UNPREDICABLE_INSN:
5ee91343
AV
21872 case MVE_OUTSIDE_PRED_INSN:
21873 if (inst.cond < COND_ALWAYS)
21874 {
21875 /* Case 7: Outside a pred block, with an IT code: error: syntax
21876 error. */
21877 inst.error = BAD_SYNTAX;
21878 return FAIL;
21879 }
21880 /* Case 9: Outside a pred block, with no code: OK! */
21881 break;
21882 case OUTSIDE_PRED_INSN:
21883 if (inst.cond > COND_ALWAYS)
21884 {
21885 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21886 */
21887 inst.error = BAD_SYNTAX;
21888 return FAIL;
21889 }
21890 /* Case 18: Outside a pred block, with no code: OK! */
e07e6e58
NC
21891 break;
21892
5ee91343
AV
21893 case INSIDE_VPT_INSN:
21894 /* Case 8: Outside a pred block, with a VPT code: error: should be in
21895 a VPT block. */
21896 inst.error = BAD_OUT_VPT;
21897 return FAIL;
21898
e07e6e58
NC
21899 case INSIDE_IT_INSN:
21900 case INSIDE_IT_LAST_INSN:
5ee91343 21901 if (inst.cond < COND_ALWAYS)
e07e6e58 21902 {
5ee91343
AV
21903 /* Case 16: Outside a pred block, with an IT code: error: should
21904 be in an IT block. */
21905 if (thumb_mode == 0)
e07e6e58 21906 {
5ee91343
AV
21907 if (unified_syntax
21908 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
21909 as_tsktsk (_("Warning: conditional outside an IT block"\
21910 " for Thumb."));
e07e6e58
NC
21911 }
21912 else
21913 {
5ee91343
AV
21914 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
21915 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
21916 {
21917 /* Automatically generate the IT instruction. */
21918 new_automatic_it_block (inst.cond);
21919 if (inst.pred_insn_type == INSIDE_IT_LAST_INSN)
21920 close_automatic_it_block ();
21921 }
21922 else
21923 {
21924 inst.error = BAD_OUT_IT;
21925 return FAIL;
21926 }
e07e6e58 21927 }
5ee91343 21928 break;
e07e6e58 21929 }
5ee91343
AV
21930 else if (inst.cond > COND_ALWAYS)
21931 {
21932 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21933 */
21934 inst.error = BAD_SYNTAX;
21935 return FAIL;
21936 }
21937 else
21938 gas_assert (0);
e07e6e58
NC
21939 case IF_INSIDE_IT_LAST_INSN:
21940 case NEUTRAL_IT_INSN:
21941 break;
21942
5ee91343
AV
21943 case VPT_INSN:
21944 if (inst.cond != COND_ALWAYS)
21945 first_error (BAD_SYNTAX);
21946 now_pred.state = MANUAL_PRED_BLOCK;
21947 now_pred.block_length = 0;
21948 now_pred.type = VECTOR_PRED;
21949 now_pred.cc = 0;
21950 break;
e07e6e58 21951 case IT_INSN:
5ee91343
AV
21952 now_pred.state = MANUAL_PRED_BLOCK;
21953 now_pred.block_length = 0;
21954 now_pred.type = SCALAR_PRED;
e07e6e58
NC
21955 break;
21956 }
21957 break;
21958
5ee91343 21959 case AUTOMATIC_PRED_BLOCK:
e07e6e58
NC
21960 /* Three things may happen now:
21961 a) We should increment current it block size;
21962 b) We should close current it block (closing insn or 4 insns);
21963 c) We should close current it block and start a new one (due
21964 to incompatible conditions or
21965 4 insns-length block reached). */
21966
5ee91343 21967 switch (inst.pred_insn_type)
e07e6e58 21968 {
5ee91343
AV
21969 case INSIDE_VPT_INSN:
21970 case VPT_INSN:
35c228db 21971 case MVE_UNPREDICABLE_INSN:
5ee91343
AV
21972 case MVE_OUTSIDE_PRED_INSN:
21973 gas_assert (0);
21974 case OUTSIDE_PRED_INSN:
2b0f3761 21975 /* The closure of the block shall happen immediately,
5ee91343 21976 so any in_pred_block () call reports the block as closed. */
e07e6e58
NC
21977 force_automatic_it_block_close ();
21978 break;
21979
21980 case INSIDE_IT_INSN:
21981 case INSIDE_IT_LAST_INSN:
21982 case IF_INSIDE_IT_LAST_INSN:
5ee91343 21983 now_pred.block_length++;
e07e6e58 21984
5ee91343
AV
21985 if (now_pred.block_length > 4
21986 || !now_pred_compatible (inst.cond))
e07e6e58
NC
21987 {
21988 force_automatic_it_block_close ();
5ee91343 21989 if (inst.pred_insn_type != IF_INSIDE_IT_LAST_INSN)
e07e6e58
NC
21990 new_automatic_it_block (inst.cond);
21991 }
21992 else
21993 {
5ee91343
AV
21994 now_pred.insn_cond = TRUE;
21995 now_pred_add_mask (inst.cond);
e07e6e58
NC
21996 }
21997
5ee91343
AV
21998 if (now_pred.state == AUTOMATIC_PRED_BLOCK
21999 && (inst.pred_insn_type == INSIDE_IT_LAST_INSN
22000 || inst.pred_insn_type == IF_INSIDE_IT_LAST_INSN))
e07e6e58
NC
22001 close_automatic_it_block ();
22002 break;
22003
22004 case NEUTRAL_IT_INSN:
5ee91343
AV
22005 now_pred.block_length++;
22006 now_pred.insn_cond = TRUE;
e07e6e58 22007
5ee91343 22008 if (now_pred.block_length > 4)
e07e6e58
NC
22009 force_automatic_it_block_close ();
22010 else
5ee91343 22011 now_pred_add_mask (now_pred.cc & 1);
e07e6e58
NC
22012 break;
22013
22014 case IT_INSN:
22015 close_automatic_it_block ();
5ee91343 22016 now_pred.state = MANUAL_PRED_BLOCK;
e07e6e58
NC
22017 break;
22018 }
22019 break;
22020
5ee91343 22021 case MANUAL_PRED_BLOCK:
e07e6e58 22022 {
5ee91343
AV
22023 int cond, is_last;
22024 if (now_pred.type == SCALAR_PRED)
e07e6e58 22025 {
5ee91343
AV
22026 /* Check conditional suffixes. */
22027 cond = now_pred.cc ^ ((now_pred.mask >> 4) & 1) ^ 1;
22028 now_pred.mask <<= 1;
22029 now_pred.mask &= 0x1f;
22030 is_last = (now_pred.mask == 0x10);
22031 }
22032 else
22033 {
22034 now_pred.cc ^= (now_pred.mask >> 4);
22035 cond = now_pred.cc + 0xf;
22036 now_pred.mask <<= 1;
22037 now_pred.mask &= 0x1f;
22038 is_last = now_pred.mask == 0x10;
22039 }
22040 now_pred.insn_cond = TRUE;
e07e6e58 22041
5ee91343
AV
22042 switch (inst.pred_insn_type)
22043 {
22044 case OUTSIDE_PRED_INSN:
22045 if (now_pred.type == SCALAR_PRED)
22046 {
22047 if (inst.cond == COND_ALWAYS)
22048 {
22049 /* Case 12: In an IT block, with no code: error: missing
22050 code. */
22051 inst.error = BAD_NOT_IT;
22052 return FAIL;
22053 }
22054 else if (inst.cond > COND_ALWAYS)
22055 {
22056 /* Case 11: In an IT block, with a VPT code: syntax error.
22057 */
22058 inst.error = BAD_SYNTAX;
22059 return FAIL;
22060 }
22061 else if (thumb_mode)
22062 {
22063 /* This is for some special cases where a non-MVE
22064 instruction is not allowed in an IT block, such as cbz,
22065 but are put into one with a condition code.
22066 You could argue this should be a syntax error, but we
22067 gave the 'not allowed in IT block' diagnostic in the
22068 past so we will keep doing so. */
22069 inst.error = BAD_NOT_IT;
22070 return FAIL;
22071 }
22072 break;
22073 }
22074 else
22075 {
22076 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
22077 as_tsktsk (MVE_NOT_VPT);
22078 return SUCCESS;
22079 }
22080 case MVE_OUTSIDE_PRED_INSN:
22081 if (now_pred.type == SCALAR_PRED)
22082 {
22083 if (inst.cond == COND_ALWAYS)
22084 {
22085 /* Case 3: In an IT block, with no code: warning:
22086 UNPREDICTABLE. */
22087 as_tsktsk (MVE_NOT_IT);
22088 return SUCCESS;
22089 }
22090 else if (inst.cond < COND_ALWAYS)
22091 {
22092 /* Case 1: In an IT block, with an IT code: syntax error.
22093 */
22094 inst.error = BAD_SYNTAX;
22095 return FAIL;
22096 }
22097 else
22098 gas_assert (0);
22099 }
22100 else
22101 {
22102 if (inst.cond < COND_ALWAYS)
22103 {
22104 /* Case 4: In a VPT block, with an IT code: syntax error.
22105 */
22106 inst.error = BAD_SYNTAX;
22107 return FAIL;
22108 }
22109 else if (inst.cond == COND_ALWAYS)
22110 {
22111 /* Case 6: In a VPT block, with no code: error: missing
22112 code. */
22113 inst.error = BAD_NOT_VPT;
22114 return FAIL;
22115 }
22116 else
22117 {
22118 gas_assert (0);
22119 }
22120 }
35c228db
AV
22121 case MVE_UNPREDICABLE_INSN:
22122 as_tsktsk (now_pred.type == SCALAR_PRED ? MVE_NOT_IT : MVE_NOT_VPT);
22123 return SUCCESS;
e07e6e58 22124 case INSIDE_IT_INSN:
5ee91343 22125 if (inst.cond > COND_ALWAYS)
e07e6e58 22126 {
5ee91343
AV
22127 /* Case 11: In an IT block, with a VPT code: syntax error. */
22128 /* Case 14: In a VPT block, with a VPT code: syntax error. */
22129 inst.error = BAD_SYNTAX;
22130 return FAIL;
22131 }
22132 else if (now_pred.type == SCALAR_PRED)
22133 {
22134 /* Case 10: In an IT block, with an IT code: OK! */
22135 if (cond != inst.cond)
22136 {
22137 inst.error = now_pred.type == SCALAR_PRED ? BAD_IT_COND :
22138 BAD_VPT_COND;
22139 return FAIL;
22140 }
22141 }
22142 else
22143 {
22144 /* Case 13: In a VPT block, with an IT code: error: should be
22145 in an IT block. */
22146 inst.error = BAD_OUT_IT;
e07e6e58
NC
22147 return FAIL;
22148 }
22149 break;
22150
5ee91343
AV
22151 case INSIDE_VPT_INSN:
22152 if (now_pred.type == SCALAR_PRED)
22153 {
22154 /* Case 2: In an IT block, with a VPT code: error: must be in a
22155 VPT block. */
22156 inst.error = BAD_OUT_VPT;
22157 return FAIL;
22158 }
22159 /* Case 5: In a VPT block, with a VPT code: OK! */
22160 else if (cond != inst.cond)
22161 {
22162 inst.error = BAD_VPT_COND;
22163 return FAIL;
22164 }
22165 break;
e07e6e58
NC
22166 case INSIDE_IT_LAST_INSN:
22167 case IF_INSIDE_IT_LAST_INSN:
5ee91343
AV
22168 if (now_pred.type == VECTOR_PRED || inst.cond > COND_ALWAYS)
22169 {
22170 /* Case 4: In a VPT block, with an IT code: syntax error. */
22171 /* Case 11: In an IT block, with a VPT code: syntax error. */
22172 inst.error = BAD_SYNTAX;
22173 return FAIL;
22174 }
22175 else if (cond != inst.cond)
e07e6e58
NC
22176 {
22177 inst.error = BAD_IT_COND;
22178 return FAIL;
22179 }
22180 if (!is_last)
22181 {
22182 inst.error = BAD_BRANCH;
22183 return FAIL;
22184 }
22185 break;
22186
22187 case NEUTRAL_IT_INSN:
5ee91343
AV
22188 /* The BKPT instruction is unconditional even in a IT or VPT
22189 block. */
e07e6e58
NC
22190 break;
22191
22192 case IT_INSN:
5ee91343
AV
22193 if (now_pred.type == SCALAR_PRED)
22194 {
22195 inst.error = BAD_IT_IT;
22196 return FAIL;
22197 }
22198 /* fall through. */
22199 case VPT_INSN:
22200 if (inst.cond == COND_ALWAYS)
22201 {
22202 /* Executing a VPT/VPST instruction inside an IT block or a
22203 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
22204 */
22205 if (now_pred.type == SCALAR_PRED)
22206 as_tsktsk (MVE_NOT_IT);
22207 else
22208 as_tsktsk (MVE_NOT_VPT);
22209 return SUCCESS;
22210 }
22211 else
22212 {
22213 /* VPT/VPST do not accept condition codes. */
22214 inst.error = BAD_SYNTAX;
22215 return FAIL;
22216 }
e07e6e58 22217 }
5ee91343 22218 }
e07e6e58
NC
22219 break;
22220 }
22221
22222 return SUCCESS;
22223}
22224
5a01bb1d
MGD
22225struct depr_insn_mask
22226{
22227 unsigned long pattern;
22228 unsigned long mask;
22229 const char* description;
22230};
22231
22232/* List of 16-bit instruction patterns deprecated in an IT block in
22233 ARMv8. */
22234static const struct depr_insn_mask depr_it_insns[] = {
22235 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
22236 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
22237 { 0xa000, 0xb800, N_("ADR") },
22238 { 0x4800, 0xf800, N_("Literal loads") },
22239 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
22240 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
c8de034b
JW
22241 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
22242 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
22243 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
5a01bb1d
MGD
22244 { 0, 0, NULL }
22245};
22246
e07e6e58
NC
22247static void
22248it_fsm_post_encode (void)
22249{
22250 int is_last;
22251
5ee91343
AV
22252 if (!now_pred.state_handled)
22253 handle_pred_state ();
e07e6e58 22254
5ee91343
AV
22255 if (now_pred.insn_cond
22256 && !now_pred.warn_deprecated
5a01bb1d 22257 && warn_on_deprecated
df9909b8
TP
22258 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)
22259 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m))
5a01bb1d
MGD
22260 {
22261 if (inst.instruction >= 0x10000)
22262 {
5c3696f8 22263 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
df9909b8 22264 "performance deprecated in ARMv8-A and ARMv8-R"));
5ee91343 22265 now_pred.warn_deprecated = TRUE;
5a01bb1d
MGD
22266 }
22267 else
22268 {
22269 const struct depr_insn_mask *p = depr_it_insns;
22270
22271 while (p->mask != 0)
22272 {
22273 if ((inst.instruction & p->mask) == p->pattern)
22274 {
df9909b8
TP
22275 as_tsktsk (_("IT blocks containing 16-bit Thumb "
22276 "instructions of the following class are "
22277 "performance deprecated in ARMv8-A and "
22278 "ARMv8-R: %s"), p->description);
5ee91343 22279 now_pred.warn_deprecated = TRUE;
5a01bb1d
MGD
22280 break;
22281 }
22282
22283 ++p;
22284 }
22285 }
22286
5ee91343 22287 if (now_pred.block_length > 1)
5a01bb1d 22288 {
5c3696f8 22289 as_tsktsk (_("IT blocks containing more than one conditional "
df9909b8
TP
22290 "instruction are performance deprecated in ARMv8-A and "
22291 "ARMv8-R"));
5ee91343 22292 now_pred.warn_deprecated = TRUE;
5a01bb1d
MGD
22293 }
22294 }
22295
5ee91343
AV
22296 is_last = (now_pred.mask == 0x10);
22297 if (is_last)
22298 {
22299 now_pred.state = OUTSIDE_PRED_BLOCK;
22300 now_pred.mask = 0;
22301 }
e07e6e58
NC
22302}
22303
22304static void
22305force_automatic_it_block_close (void)
22306{
5ee91343 22307 if (now_pred.state == AUTOMATIC_PRED_BLOCK)
e07e6e58
NC
22308 {
22309 close_automatic_it_block ();
5ee91343
AV
22310 now_pred.state = OUTSIDE_PRED_BLOCK;
22311 now_pred.mask = 0;
e07e6e58
NC
22312 }
22313}
22314
22315static int
5ee91343 22316in_pred_block (void)
e07e6e58 22317{
5ee91343
AV
22318 if (!now_pred.state_handled)
22319 handle_pred_state ();
e07e6e58 22320
5ee91343 22321 return now_pred.state != OUTSIDE_PRED_BLOCK;
e07e6e58
NC
22322}
22323
ff8646ee
TP
22324/* Whether OPCODE only has T32 encoding. Since this function is only used by
22325 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
22326 here, hence the "known" in the function name. */
fc289b0a
TP
22327
22328static bfd_boolean
ff8646ee 22329known_t32_only_insn (const struct asm_opcode *opcode)
fc289b0a
TP
22330{
22331 /* Original Thumb-1 wide instruction. */
22332 if (opcode->tencode == do_t_blx
22333 || opcode->tencode == do_t_branch23
22334 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
22335 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))
22336 return TRUE;
22337
16a1fa25
TP
22338 /* Wide-only instruction added to ARMv8-M Baseline. */
22339 if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m_m_only)
ff8646ee
TP
22340 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics)
22341 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m)
22342 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div))
22343 return TRUE;
22344
22345 return FALSE;
22346}
22347
22348/* Whether wide instruction variant can be used if available for a valid OPCODE
22349 in ARCH. */
22350
22351static bfd_boolean
22352t32_insn_ok (arm_feature_set arch, const struct asm_opcode *opcode)
22353{
22354 if (known_t32_only_insn (opcode))
22355 return TRUE;
22356
22357 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
22358 of variant T3 of B.W is checked in do_t_branch. */
22359 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
22360 && opcode->tencode == do_t_branch)
22361 return TRUE;
22362
bada4342
JW
22363 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
22364 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
22365 && opcode->tencode == do_t_mov_cmp
22366 /* Make sure CMP instruction is not affected. */
22367 && opcode->aencode == do_mov)
22368 return TRUE;
22369
ff8646ee
TP
22370 /* Wide instruction variants of all instructions with narrow *and* wide
22371 variants become available with ARMv6t2. Other opcodes are either
22372 narrow-only or wide-only and are thus available if OPCODE is valid. */
22373 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v6t2))
22374 return TRUE;
22375
22376 /* OPCODE with narrow only instruction variant or wide variant not
22377 available. */
fc289b0a
TP
22378 return FALSE;
22379}
22380
c19d1205
ZW
22381void
22382md_assemble (char *str)
b99bd4ef 22383{
c19d1205
ZW
22384 char *p = str;
22385 const struct asm_opcode * opcode;
b99bd4ef 22386
c19d1205
ZW
22387 /* Align the previous label if needed. */
22388 if (last_label_seen != NULL)
b99bd4ef 22389 {
c19d1205
ZW
22390 symbol_set_frag (last_label_seen, frag_now);
22391 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
22392 S_SET_SEGMENT (last_label_seen, now_seg);
b99bd4ef
NC
22393 }
22394
c19d1205 22395 memset (&inst, '\0', sizeof (inst));
e2b0ab59
AV
22396 int r;
22397 for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
22398 inst.relocs[r].type = BFD_RELOC_UNUSED;
b99bd4ef 22399
c19d1205
ZW
22400 opcode = opcode_lookup (&p);
22401 if (!opcode)
b99bd4ef 22402 {
c19d1205 22403 /* It wasn't an instruction, but it might be a register alias of
dcbf9037 22404 the form alias .req reg, or a Neon .dn/.qn directive. */
c921be7d 22405 if (! create_register_alias (str, p)
477330fc 22406 && ! create_neon_reg_alias (str, p))
c19d1205 22407 as_bad (_("bad instruction `%s'"), str);
b99bd4ef 22408
b99bd4ef
NC
22409 return;
22410 }
22411
278df34e 22412 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
5c3696f8 22413 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
088fa78e 22414
037e8744
JB
22415 /* The value which unconditional instructions should have in place of the
22416 condition field. */
22417 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
22418
c19d1205 22419 if (thumb_mode)
b99bd4ef 22420 {
e74cfd16 22421 arm_feature_set variant;
8f06b2d8
PB
22422
22423 variant = cpu_variant;
22424 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
e74cfd16
PB
22425 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
22426 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
c19d1205 22427 /* Check that this instruction is supported for this CPU. */
62b3e311
PB
22428 if (!opcode->tvariant
22429 || (thumb_mode == 1
22430 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
b99bd4ef 22431 {
173205ca
TP
22432 if (opcode->tencode == do_t_swi)
22433 as_bad (_("SVC is not permitted on this architecture"));
22434 else
22435 as_bad (_("selected processor does not support `%s' in Thumb mode"), str);
b99bd4ef
NC
22436 return;
22437 }
c19d1205
ZW
22438 if (inst.cond != COND_ALWAYS && !unified_syntax
22439 && opcode->tencode != do_t_branch)
b99bd4ef 22440 {
c19d1205 22441 as_bad (_("Thumb does not support conditional execution"));
b99bd4ef
NC
22442 return;
22443 }
22444
fc289b0a
TP
22445 /* Two things are addressed here:
22446 1) Implicit require narrow instructions on Thumb-1.
22447 This avoids relaxation accidentally introducing Thumb-2
22448 instructions.
22449 2) Reject wide instructions in non Thumb-2 cores.
22450
22451 Only instructions with narrow and wide variants need to be handled
22452 but selecting all non wide-only instructions is easier. */
22453 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)
ff8646ee 22454 && !t32_insn_ok (variant, opcode))
076d447c 22455 {
fc289b0a
TP
22456 if (inst.size_req == 0)
22457 inst.size_req = 2;
22458 else if (inst.size_req == 4)
752d5da4 22459 {
ff8646ee
TP
22460 if (ARM_CPU_HAS_FEATURE (variant, arm_ext_v8m))
22461 as_bad (_("selected processor does not support 32bit wide "
22462 "variant of instruction `%s'"), str);
22463 else
22464 as_bad (_("selected processor does not support `%s' in "
22465 "Thumb-2 mode"), str);
fc289b0a 22466 return;
752d5da4 22467 }
076d447c
PB
22468 }
22469
c19d1205
ZW
22470 inst.instruction = opcode->tvalue;
22471
5be8be5d 22472 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
477330fc 22473 {
5ee91343 22474 /* Prepare the pred_insn_type for those encodings that don't set
477330fc
RM
22475 it. */
22476 it_fsm_pre_encode ();
c19d1205 22477
477330fc 22478 opcode->tencode ();
e07e6e58 22479
477330fc
RM
22480 it_fsm_post_encode ();
22481 }
e27ec89e 22482
0110f2b8 22483 if (!(inst.error || inst.relax))
b99bd4ef 22484 {
9c2799c2 22485 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
c19d1205
ZW
22486 inst.size = (inst.instruction > 0xffff ? 4 : 2);
22487 if (inst.size_req && inst.size_req != inst.size)
b99bd4ef 22488 {
c19d1205 22489 as_bad (_("cannot honor width suffix -- `%s'"), str);
b99bd4ef
NC
22490 return;
22491 }
22492 }
076d447c
PB
22493
22494 /* Something has gone badly wrong if we try to relax a fixed size
477330fc 22495 instruction. */
9c2799c2 22496 gas_assert (inst.size_req == 0 || !inst.relax);
076d447c 22497
e74cfd16
PB
22498 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
22499 *opcode->tvariant);
ee065d83 22500 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
fc289b0a
TP
22501 set those bits when Thumb-2 32-bit instructions are seen. The impact
22502 of relaxable instructions will be considered later after we finish all
22503 relaxation. */
ff8646ee
TP
22504 if (ARM_FEATURE_CORE_EQUAL (cpu_variant, arm_arch_any))
22505 variant = arm_arch_none;
22506 else
22507 variant = cpu_variant;
22508 if (inst.size == 4 && !t32_insn_ok (variant, opcode))
e74cfd16
PB
22509 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
22510 arm_ext_v6t2);
cd000bff 22511
88714cb8
DG
22512 check_neon_suffixes;
22513
cd000bff 22514 if (!inst.error)
c877a2f2
NC
22515 {
22516 mapping_state (MAP_THUMB);
22517 }
c19d1205 22518 }
3e9e4fcf 22519 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
c19d1205 22520 {
845b51d6
PB
22521 bfd_boolean is_bx;
22522
22523 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
22524 is_bx = (opcode->aencode == do_bx);
22525
c19d1205 22526 /* Check that this instruction is supported for this CPU. */
845b51d6
PB
22527 if (!(is_bx && fix_v4bx)
22528 && !(opcode->avariant &&
22529 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
b99bd4ef 22530 {
84b52b66 22531 as_bad (_("selected processor does not support `%s' in ARM mode"), str);
c19d1205 22532 return;
b99bd4ef 22533 }
c19d1205 22534 if (inst.size_req)
b99bd4ef 22535 {
c19d1205
ZW
22536 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
22537 return;
b99bd4ef
NC
22538 }
22539
c19d1205
ZW
22540 inst.instruction = opcode->avalue;
22541 if (opcode->tag == OT_unconditionalF)
eff0bc54 22542 inst.instruction |= 0xFU << 28;
c19d1205
ZW
22543 else
22544 inst.instruction |= inst.cond << 28;
22545 inst.size = INSN_SIZE;
5be8be5d 22546 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
477330fc
RM
22547 {
22548 it_fsm_pre_encode ();
22549 opcode->aencode ();
22550 it_fsm_post_encode ();
22551 }
ee065d83 22552 /* Arm mode bx is marked as both v4T and v5 because it's still required
477330fc 22553 on a hypothetical non-thumb v5 core. */
845b51d6 22554 if (is_bx)
e74cfd16 22555 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
ee065d83 22556 else
e74cfd16
PB
22557 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
22558 *opcode->avariant);
88714cb8
DG
22559
22560 check_neon_suffixes;
22561
cd000bff 22562 if (!inst.error)
c877a2f2
NC
22563 {
22564 mapping_state (MAP_ARM);
22565 }
b99bd4ef 22566 }
3e9e4fcf
JB
22567 else
22568 {
22569 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
22570 "-- `%s'"), str);
22571 return;
22572 }
c19d1205
ZW
22573 output_inst (str);
22574}
b99bd4ef 22575
e07e6e58 22576static void
5ee91343 22577check_pred_blocks_finished (void)
e07e6e58
NC
22578{
22579#ifdef OBJ_ELF
22580 asection *sect;
22581
22582 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
5ee91343
AV
22583 if (seg_info (sect)->tc_segment_info_data.current_pred.state
22584 == MANUAL_PRED_BLOCK)
e07e6e58 22585 {
5ee91343
AV
22586 if (now_pred.type == SCALAR_PRED)
22587 as_warn (_("section '%s' finished with an open IT block."),
22588 sect->name);
22589 else
22590 as_warn (_("section '%s' finished with an open VPT/VPST block."),
22591 sect->name);
e07e6e58
NC
22592 }
22593#else
5ee91343
AV
22594 if (now_pred.state == MANUAL_PRED_BLOCK)
22595 {
22596 if (now_pred.type == SCALAR_PRED)
22597 as_warn (_("file finished with an open IT block."));
22598 else
22599 as_warn (_("file finished with an open VPT/VPST block."));
22600 }
e07e6e58
NC
22601#endif
22602}
22603
c19d1205
ZW
22604/* Various frobbings of labels and their addresses. */
22605
22606void
22607arm_start_line_hook (void)
22608{
22609 last_label_seen = NULL;
b99bd4ef
NC
22610}
22611
c19d1205
ZW
22612void
22613arm_frob_label (symbolS * sym)
b99bd4ef 22614{
c19d1205 22615 last_label_seen = sym;
b99bd4ef 22616
c19d1205 22617 ARM_SET_THUMB (sym, thumb_mode);
b99bd4ef 22618
c19d1205
ZW
22619#if defined OBJ_COFF || defined OBJ_ELF
22620 ARM_SET_INTERWORK (sym, support_interwork);
22621#endif
b99bd4ef 22622
e07e6e58
NC
22623 force_automatic_it_block_close ();
22624
5f4273c7 22625 /* Note - do not allow local symbols (.Lxxx) to be labelled
c19d1205
ZW
22626 as Thumb functions. This is because these labels, whilst
22627 they exist inside Thumb code, are not the entry points for
22628 possible ARM->Thumb calls. Also, these labels can be used
22629 as part of a computed goto or switch statement. eg gcc
22630 can generate code that looks like this:
b99bd4ef 22631
c19d1205
ZW
22632 ldr r2, [pc, .Laaa]
22633 lsl r3, r3, #2
22634 ldr r2, [r3, r2]
22635 mov pc, r2
b99bd4ef 22636
c19d1205
ZW
22637 .Lbbb: .word .Lxxx
22638 .Lccc: .word .Lyyy
22639 ..etc...
22640 .Laaa: .word Lbbb
b99bd4ef 22641
c19d1205
ZW
22642 The first instruction loads the address of the jump table.
22643 The second instruction converts a table index into a byte offset.
22644 The third instruction gets the jump address out of the table.
22645 The fourth instruction performs the jump.
b99bd4ef 22646
c19d1205
ZW
22647 If the address stored at .Laaa is that of a symbol which has the
22648 Thumb_Func bit set, then the linker will arrange for this address
22649 to have the bottom bit set, which in turn would mean that the
22650 address computation performed by the third instruction would end
22651 up with the bottom bit set. Since the ARM is capable of unaligned
22652 word loads, the instruction would then load the incorrect address
22653 out of the jump table, and chaos would ensue. */
22654 if (label_is_thumb_function_name
22655 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
22656 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
b99bd4ef 22657 {
c19d1205
ZW
22658 /* When the address of a Thumb function is taken the bottom
22659 bit of that address should be set. This will allow
22660 interworking between Arm and Thumb functions to work
22661 correctly. */
b99bd4ef 22662
c19d1205 22663 THUMB_SET_FUNC (sym, 1);
b99bd4ef 22664
c19d1205 22665 label_is_thumb_function_name = FALSE;
b99bd4ef 22666 }
07a53e5c 22667
07a53e5c 22668 dwarf2_emit_label (sym);
b99bd4ef
NC
22669}
22670
c921be7d 22671bfd_boolean
c19d1205 22672arm_data_in_code (void)
b99bd4ef 22673{
c19d1205 22674 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
b99bd4ef 22675 {
c19d1205
ZW
22676 *input_line_pointer = '/';
22677 input_line_pointer += 5;
22678 *input_line_pointer = 0;
c921be7d 22679 return TRUE;
b99bd4ef
NC
22680 }
22681
c921be7d 22682 return FALSE;
b99bd4ef
NC
22683}
22684
c19d1205
ZW
22685char *
22686arm_canonicalize_symbol_name (char * name)
b99bd4ef 22687{
c19d1205 22688 int len;
b99bd4ef 22689
c19d1205
ZW
22690 if (thumb_mode && (len = strlen (name)) > 5
22691 && streq (name + len - 5, "/data"))
22692 *(name + len - 5) = 0;
b99bd4ef 22693
c19d1205 22694 return name;
b99bd4ef 22695}
c19d1205
ZW
22696\f
22697/* Table of all register names defined by default. The user can
22698 define additional names with .req. Note that all register names
22699 should appear in both upper and lowercase variants. Some registers
22700 also have mixed-case names. */
b99bd4ef 22701
dcbf9037 22702#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
c19d1205 22703#define REGNUM(p,n,t) REGDEF(p##n, n, t)
5287ad62 22704#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
c19d1205
ZW
22705#define REGSET(p,t) \
22706 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
22707 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
22708 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
22709 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
5287ad62
JB
22710#define REGSETH(p,t) \
22711 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
22712 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
22713 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
22714 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
22715#define REGSET2(p,t) \
22716 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
22717 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
22718 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
22719 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
90ec0d68
MGD
22720#define SPLRBANK(base,bank,t) \
22721 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
22722 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
22723 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
22724 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
22725 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
22726 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
7ed4c4c5 22727
c19d1205 22728static const struct reg_entry reg_names[] =
7ed4c4c5 22729{
c19d1205
ZW
22730 /* ARM integer registers. */
22731 REGSET(r, RN), REGSET(R, RN),
7ed4c4c5 22732
c19d1205
ZW
22733 /* ATPCS synonyms. */
22734 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
22735 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
22736 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
7ed4c4c5 22737
c19d1205
ZW
22738 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
22739 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
22740 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
7ed4c4c5 22741
c19d1205
ZW
22742 /* Well-known aliases. */
22743 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
22744 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
22745
22746 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
22747 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
22748
1b883319
AV
22749 /* Defining the new Zero register from ARMv8.1-M. */
22750 REGDEF(zr,15,ZR),
22751 REGDEF(ZR,15,ZR),
22752
c19d1205
ZW
22753 /* Coprocessor numbers. */
22754 REGSET(p, CP), REGSET(P, CP),
22755
22756 /* Coprocessor register numbers. The "cr" variants are for backward
22757 compatibility. */
22758 REGSET(c, CN), REGSET(C, CN),
22759 REGSET(cr, CN), REGSET(CR, CN),
22760
90ec0d68
MGD
22761 /* ARM banked registers. */
22762 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
22763 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
22764 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
22765 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
22766 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
22767 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
22768 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
22769
22770 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
22771 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
22772 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
22773 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
22774 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
1472d06f 22775 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
90ec0d68
MGD
22776 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
22777 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
22778
22779 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
22780 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
22781 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
22782 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
22783 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
22784 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
22785 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
fa94de6b 22786 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
90ec0d68
MGD
22787 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
22788
c19d1205
ZW
22789 /* FPA registers. */
22790 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
22791 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
22792
22793 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
22794 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
22795
22796 /* VFP SP registers. */
5287ad62
JB
22797 REGSET(s,VFS), REGSET(S,VFS),
22798 REGSETH(s,VFS), REGSETH(S,VFS),
c19d1205
ZW
22799
22800 /* VFP DP Registers. */
5287ad62
JB
22801 REGSET(d,VFD), REGSET(D,VFD),
22802 /* Extra Neon DP registers. */
22803 REGSETH(d,VFD), REGSETH(D,VFD),
22804
22805 /* Neon QP registers. */
22806 REGSET2(q,NQ), REGSET2(Q,NQ),
c19d1205
ZW
22807
22808 /* VFP control registers. */
22809 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
22810 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
cd2cf30b
PB
22811 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
22812 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
22813 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
22814 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
40c7d507 22815 REGDEF(mvfr2,5,VFC), REGDEF(MVFR2,5,VFC),
c19d1205
ZW
22816
22817 /* Maverick DSP coprocessor registers. */
22818 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
22819 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
22820
22821 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
22822 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
22823 REGDEF(dspsc,0,DSPSC),
22824
22825 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
22826 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
22827 REGDEF(DSPSC,0,DSPSC),
22828
22829 /* iWMMXt data registers - p0, c0-15. */
22830 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
22831
22832 /* iWMMXt control registers - p1, c0-3. */
22833 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
22834 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
22835 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
22836 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
22837
22838 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
22839 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
22840 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
22841 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
22842 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
22843
22844 /* XScale accumulator registers. */
22845 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
22846};
22847#undef REGDEF
22848#undef REGNUM
22849#undef REGSET
7ed4c4c5 22850
c19d1205
ZW
22851/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
22852 within psr_required_here. */
22853static const struct asm_psr psrs[] =
22854{
22855 /* Backward compatibility notation. Note that "all" is no longer
22856 truly all possible PSR bits. */
22857 {"all", PSR_c | PSR_f},
22858 {"flg", PSR_f},
22859 {"ctl", PSR_c},
22860
22861 /* Individual flags. */
22862 {"f", PSR_f},
22863 {"c", PSR_c},
22864 {"x", PSR_x},
22865 {"s", PSR_s},
59b42a0d 22866
c19d1205
ZW
22867 /* Combinations of flags. */
22868 {"fs", PSR_f | PSR_s},
22869 {"fx", PSR_f | PSR_x},
22870 {"fc", PSR_f | PSR_c},
22871 {"sf", PSR_s | PSR_f},
22872 {"sx", PSR_s | PSR_x},
22873 {"sc", PSR_s | PSR_c},
22874 {"xf", PSR_x | PSR_f},
22875 {"xs", PSR_x | PSR_s},
22876 {"xc", PSR_x | PSR_c},
22877 {"cf", PSR_c | PSR_f},
22878 {"cs", PSR_c | PSR_s},
22879 {"cx", PSR_c | PSR_x},
22880 {"fsx", PSR_f | PSR_s | PSR_x},
22881 {"fsc", PSR_f | PSR_s | PSR_c},
22882 {"fxs", PSR_f | PSR_x | PSR_s},
22883 {"fxc", PSR_f | PSR_x | PSR_c},
22884 {"fcs", PSR_f | PSR_c | PSR_s},
22885 {"fcx", PSR_f | PSR_c | PSR_x},
22886 {"sfx", PSR_s | PSR_f | PSR_x},
22887 {"sfc", PSR_s | PSR_f | PSR_c},
22888 {"sxf", PSR_s | PSR_x | PSR_f},
22889 {"sxc", PSR_s | PSR_x | PSR_c},
22890 {"scf", PSR_s | PSR_c | PSR_f},
22891 {"scx", PSR_s | PSR_c | PSR_x},
22892 {"xfs", PSR_x | PSR_f | PSR_s},
22893 {"xfc", PSR_x | PSR_f | PSR_c},
22894 {"xsf", PSR_x | PSR_s | PSR_f},
22895 {"xsc", PSR_x | PSR_s | PSR_c},
22896 {"xcf", PSR_x | PSR_c | PSR_f},
22897 {"xcs", PSR_x | PSR_c | PSR_s},
22898 {"cfs", PSR_c | PSR_f | PSR_s},
22899 {"cfx", PSR_c | PSR_f | PSR_x},
22900 {"csf", PSR_c | PSR_s | PSR_f},
22901 {"csx", PSR_c | PSR_s | PSR_x},
22902 {"cxf", PSR_c | PSR_x | PSR_f},
22903 {"cxs", PSR_c | PSR_x | PSR_s},
22904 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
22905 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
22906 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
22907 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
22908 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
22909 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
22910 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
22911 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
22912 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
22913 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
22914 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
22915 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
22916 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
22917 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
22918 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
22919 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
22920 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
22921 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
22922 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
22923 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
22924 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
22925 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
22926 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
22927 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
22928};
22929
62b3e311
PB
22930/* Table of V7M psr names. */
22931static const struct asm_psr v7m_psrs[] =
22932{
1a336194
TP
22933 {"apsr", 0x0 }, {"APSR", 0x0 },
22934 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
22935 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
22936 {"psr", 0x3 }, {"PSR", 0x3 },
22937 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
22938 {"ipsr", 0x5 }, {"IPSR", 0x5 },
22939 {"epsr", 0x6 }, {"EPSR", 0x6 },
22940 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
22941 {"msp", 0x8 }, {"MSP", 0x8 },
22942 {"psp", 0x9 }, {"PSP", 0x9 },
22943 {"msplim", 0xa }, {"MSPLIM", 0xa },
22944 {"psplim", 0xb }, {"PSPLIM", 0xb },
22945 {"primask", 0x10}, {"PRIMASK", 0x10},
22946 {"basepri", 0x11}, {"BASEPRI", 0x11},
22947 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
1a336194
TP
22948 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
22949 {"control", 0x14}, {"CONTROL", 0x14},
22950 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
22951 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
22952 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
22953 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
22954 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
22955 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
22956 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
22957 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
22958 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
62b3e311
PB
22959};
22960
c19d1205
ZW
22961/* Table of all shift-in-operand names. */
22962static const struct asm_shift_name shift_names [] =
b99bd4ef 22963{
c19d1205
ZW
22964 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
22965 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
22966 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
22967 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
22968 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
f5f10c66
AV
22969 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX },
22970 { "uxtw", SHIFT_UXTW}, { "UXTW", SHIFT_UXTW}
c19d1205 22971};
b99bd4ef 22972
c19d1205
ZW
22973/* Table of all explicit relocation names. */
22974#ifdef OBJ_ELF
22975static struct reloc_entry reloc_names[] =
22976{
22977 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
22978 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
22979 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
22980 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
22981 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
22982 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
22983 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
22984 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
22985 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
22986 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
b43420e6 22987 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
0855e32b
NS
22988 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
22989 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
477330fc 22990 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
0855e32b 22991 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
477330fc 22992 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
0855e32b 22993 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
188fd7ae
CL
22994 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ},
22995 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC },
22996 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC },
22997 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC },
22998 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC },
22999 { "funcdesc", BFD_RELOC_ARM_FUNCDESC },
5c5a4843
CL
23000 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC },
23001 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC }, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC },
23002 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC }, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC },
23003 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC }, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC },
c19d1205
ZW
23004};
23005#endif
b99bd4ef 23006
5ee91343 23007/* Table of all conditional affixes. */
c19d1205
ZW
23008static const struct asm_cond conds[] =
23009{
23010 {"eq", 0x0},
23011 {"ne", 0x1},
23012 {"cs", 0x2}, {"hs", 0x2},
23013 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
23014 {"mi", 0x4},
23015 {"pl", 0x5},
23016 {"vs", 0x6},
23017 {"vc", 0x7},
23018 {"hi", 0x8},
23019 {"ls", 0x9},
23020 {"ge", 0xa},
23021 {"lt", 0xb},
23022 {"gt", 0xc},
23023 {"le", 0xd},
23024 {"al", 0xe}
23025};
5ee91343
AV
23026static const struct asm_cond vconds[] =
23027{
23028 {"t", 0xf},
23029 {"e", 0x10}
23030};
bfae80f2 23031
e797f7e0 23032#define UL_BARRIER(L,U,CODE,FEAT) \
823d2571
TG
23033 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
23034 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
e797f7e0 23035
62b3e311
PB
23036static struct asm_barrier_opt barrier_opt_names[] =
23037{
e797f7e0
MGD
23038 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
23039 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
23040 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
23041 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
23042 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
23043 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
23044 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
23045 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
23046 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
23047 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
23048 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
23049 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
23050 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
23051 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
23052 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
23053 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
62b3e311
PB
23054};
23055
e797f7e0
MGD
23056#undef UL_BARRIER
23057
c19d1205
ZW
23058/* Table of ARM-format instructions. */
23059
23060/* Macros for gluing together operand strings. N.B. In all cases
23061 other than OPS0, the trailing OP_stop comes from default
23062 zero-initialization of the unspecified elements of the array. */
23063#define OPS0() { OP_stop, }
23064#define OPS1(a) { OP_##a, }
23065#define OPS2(a,b) { OP_##a,OP_##b, }
23066#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
23067#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
23068#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
23069#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
23070
5be8be5d
DG
23071/* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
23072 This is useful when mixing operands for ARM and THUMB, i.e. using the
23073 MIX_ARM_THUMB_OPERANDS macro.
23074 In order to use these macros, prefix the number of operands with _
23075 e.g. _3. */
23076#define OPS_1(a) { a, }
23077#define OPS_2(a,b) { a,b, }
23078#define OPS_3(a,b,c) { a,b,c, }
23079#define OPS_4(a,b,c,d) { a,b,c,d, }
23080#define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
23081#define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
23082
c19d1205
ZW
23083/* These macros abstract out the exact format of the mnemonic table and
23084 save some repeated characters. */
23085
23086/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
23087#define TxCE(mnem, op, top, nops, ops, ae, te) \
21d799b5 23088 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
5ee91343 23089 THUMB_VARIANT, do_##ae, do_##te, 0 }
c19d1205
ZW
23090
23091/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
23092 a T_MNEM_xyz enumerator. */
23093#define TCE(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 23094 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
c19d1205 23095#define tCE(mnem, aop, top, nops, ops, ae, te) \
21d799b5 23096 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
c19d1205
ZW
23097
23098/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
23099 infix after the third character. */
23100#define TxC3(mnem, op, top, nops, ops, ae, te) \
21d799b5 23101 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
5ee91343 23102 THUMB_VARIANT, do_##ae, do_##te, 0 }
088fa78e 23103#define TxC3w(mnem, op, top, nops, ops, ae, te) \
21d799b5 23104 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
5ee91343 23105 THUMB_VARIANT, do_##ae, do_##te, 0 }
c19d1205 23106#define TC3(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 23107 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
088fa78e 23108#define TC3w(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 23109 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
c19d1205 23110#define tC3(mnem, aop, top, nops, ops, ae, te) \
21d799b5 23111 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
088fa78e 23112#define tC3w(mnem, aop, top, nops, ops, ae, te) \
21d799b5 23113 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
c19d1205 23114
c19d1205 23115/* Mnemonic that cannot be conditionalized. The ARM condition-code
dfa9f0d5
PB
23116 field is still 0xE. Many of the Thumb variants can be executed
23117 conditionally, so this is checked separately. */
c19d1205 23118#define TUE(mnem, op, top, nops, ops, ae, te) \
21d799b5 23119 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
5ee91343 23120 THUMB_VARIANT, do_##ae, do_##te, 0 }
c19d1205 23121
dd5181d5
KT
23122/* Same as TUE but the encoding function for ARM and Thumb modes is the same.
23123 Used by mnemonics that have very minimal differences in the encoding for
23124 ARM and Thumb variants and can be handled in a common function. */
23125#define TUEc(mnem, op, top, nops, ops, en) \
23126 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
5ee91343 23127 THUMB_VARIANT, do_##en, do_##en, 0 }
dd5181d5 23128
c19d1205
ZW
23129/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
23130 condition code field. */
23131#define TUF(mnem, op, top, nops, ops, ae, te) \
21d799b5 23132 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
5ee91343 23133 THUMB_VARIANT, do_##ae, do_##te, 0 }
c19d1205
ZW
23134
23135/* ARM-only variants of all the above. */
6a86118a 23136#define CE(mnem, op, nops, ops, ae) \
5ee91343 23137 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a
NC
23138
23139#define C3(mnem, op, nops, ops, ae) \
5ee91343 23140 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a 23141
cf3cf39d
TP
23142/* Thumb-only variants of TCE and TUE. */
23143#define ToC(mnem, top, nops, ops, te) \
23144 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
5ee91343 23145 do_##te, 0 }
cf3cf39d
TP
23146
23147#define ToU(mnem, top, nops, ops, te) \
23148 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
5ee91343 23149 NULL, do_##te, 0 }
cf3cf39d 23150
4389b29a
AV
23151/* T_MNEM_xyz enumerator variants of ToC. */
23152#define toC(mnem, top, nops, ops, te) \
23153 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
5ee91343 23154 do_##te, 0 }
4389b29a 23155
f6b2b12d
AV
23156/* T_MNEM_xyz enumerator variants of ToU. */
23157#define toU(mnem, top, nops, ops, te) \
23158 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
5ee91343 23159 NULL, do_##te, 0 }
f6b2b12d 23160
e3cb604e
PB
23161/* Legacy mnemonics that always have conditional infix after the third
23162 character. */
23163#define CL(mnem, op, nops, ops, ae) \
21d799b5 23164 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
5ee91343 23165 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
e3cb604e 23166
8f06b2d8
PB
23167/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
23168#define cCE(mnem, op, nops, ops, ae) \
5ee91343 23169 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
8f06b2d8 23170
57785aa2
AV
23171/* mov instructions that are shared between coprocessor and MVE. */
23172#define mcCE(mnem, op, nops, ops, ae) \
23173 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
23174
e3cb604e
PB
23175/* Legacy coprocessor instructions where conditional infix and conditional
23176 suffix are ambiguous. For consistency this includes all FPA instructions,
23177 not just the potentially ambiguous ones. */
23178#define cCL(mnem, op, nops, ops, ae) \
21d799b5 23179 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
5ee91343 23180 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
e3cb604e
PB
23181
23182/* Coprocessor, takes either a suffix or a position-3 infix
23183 (for an FPA corner case). */
23184#define C3E(mnem, op, nops, ops, ae) \
21d799b5 23185 { mnem, OPS##nops ops, OT_csuf_or_in3, \
5ee91343 23186 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
8f06b2d8 23187
6a86118a 23188#define xCM_(m1, m2, m3, op, nops, ops, ae) \
21d799b5
NC
23189 { m1 #m2 m3, OPS##nops ops, \
23190 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
5ee91343 23191 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a
NC
23192
23193#define CM(m1, m2, op, nops, ops, ae) \
e07e6e58
NC
23194 xCM_ (m1, , m2, op, nops, ops, ae), \
23195 xCM_ (m1, eq, m2, op, nops, ops, ae), \
23196 xCM_ (m1, ne, m2, op, nops, ops, ae), \
23197 xCM_ (m1, cs, m2, op, nops, ops, ae), \
23198 xCM_ (m1, hs, m2, op, nops, ops, ae), \
23199 xCM_ (m1, cc, m2, op, nops, ops, ae), \
23200 xCM_ (m1, ul, m2, op, nops, ops, ae), \
23201 xCM_ (m1, lo, m2, op, nops, ops, ae), \
23202 xCM_ (m1, mi, m2, op, nops, ops, ae), \
23203 xCM_ (m1, pl, m2, op, nops, ops, ae), \
23204 xCM_ (m1, vs, m2, op, nops, ops, ae), \
23205 xCM_ (m1, vc, m2, op, nops, ops, ae), \
23206 xCM_ (m1, hi, m2, op, nops, ops, ae), \
23207 xCM_ (m1, ls, m2, op, nops, ops, ae), \
23208 xCM_ (m1, ge, m2, op, nops, ops, ae), \
23209 xCM_ (m1, lt, m2, op, nops, ops, ae), \
23210 xCM_ (m1, gt, m2, op, nops, ops, ae), \
23211 xCM_ (m1, le, m2, op, nops, ops, ae), \
23212 xCM_ (m1, al, m2, op, nops, ops, ae)
6a86118a
NC
23213
23214#define UE(mnem, op, nops, ops, ae) \
5ee91343 23215 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a
NC
23216
23217#define UF(mnem, op, nops, ops, ae) \
5ee91343 23218 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a 23219
5287ad62
JB
23220/* Neon data-processing. ARM versions are unconditional with cond=0xf.
23221 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
23222 use the same encoding function for each. */
23223#define NUF(mnem, op, nops, ops, enc) \
23224 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
5ee91343 23225 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
5287ad62
JB
23226
23227/* Neon data processing, version which indirects through neon_enc_tab for
23228 the various overloaded versions of opcodes. */
23229#define nUF(mnem, op, nops, ops, enc) \
21d799b5 23230 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
5ee91343 23231 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
5287ad62
JB
23232
23233/* Neon insn with conditional suffix for the ARM version, non-overloaded
23234 version. */
5ee91343 23235#define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
037e8744 23236 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
5ee91343 23237 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
5287ad62 23238
037e8744 23239#define NCE(mnem, op, nops, ops, enc) \
5ee91343 23240 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
037e8744
JB
23241
23242#define NCEF(mnem, op, nops, ops, enc) \
5ee91343 23243 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
037e8744 23244
5287ad62 23245/* Neon insn with conditional suffix for the ARM version, overloaded types. */
5ee91343 23246#define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
21d799b5 23247 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
5ee91343 23248 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
5287ad62 23249
037e8744 23250#define nCE(mnem, op, nops, ops, enc) \
5ee91343 23251 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
037e8744
JB
23252
23253#define nCEF(mnem, op, nops, ops, enc) \
5ee91343
AV
23254 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23255
23256/* */
23257#define mCEF(mnem, op, nops, ops, enc) \
a302e574 23258 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
5ee91343
AV
23259 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23260
23261
23262/* nCEF but for MVE predicated instructions. */
23263#define mnCEF(mnem, op, nops, ops, enc) \
23264 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23265
23266/* nCE but for MVE predicated instructions. */
23267#define mnCE(mnem, op, nops, ops, enc) \
23268 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
037e8744 23269
5ee91343
AV
23270/* NUF but for potentially MVE predicated instructions. */
23271#define MNUF(mnem, op, nops, ops, enc) \
23272 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23273 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23274
23275/* nUF but for potentially MVE predicated instructions. */
23276#define mnUF(mnem, op, nops, ops, enc) \
23277 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23278 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23279
23280/* ToC but for potentially MVE predicated instructions. */
23281#define mToC(mnem, top, nops, ops, te) \
23282 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23283 do_##te, 1 }
23284
23285/* NCE but for MVE predicated instructions. */
23286#define MNCE(mnem, op, nops, ops, enc) \
23287 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23288
23289/* NCEF but for MVE predicated instructions. */
23290#define MNCEF(mnem, op, nops, ops, enc) \
23291 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
c19d1205
ZW
23292#define do_0 0
23293
c19d1205 23294static const struct asm_opcode insns[] =
bfae80f2 23295{
74db7efb
NC
23296#define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
23297#define THUMB_VARIANT & arm_ext_v4t
21d799b5
NC
23298 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
23299 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
23300 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
23301 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
23302 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
23303 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
23304 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
23305 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
23306 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
23307 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
23308 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
23309 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
23310 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
23311 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
23312 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
23313 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
c19d1205
ZW
23314
23315 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
23316 for setting PSR flag bits. They are obsolete in V6 and do not
23317 have Thumb equivalents. */
21d799b5
NC
23318 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
23319 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
23320 CL("tstp", 110f000, 2, (RR, SH), cmp),
23321 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
23322 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
23323 CL("cmpp", 150f000, 2, (RR, SH), cmp),
23324 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
23325 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
23326 CL("cmnp", 170f000, 2, (RR, SH), cmp),
23327
23328 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
72d98d16 23329 tC3("movs", 1b00000, _movs, 2, (RR, SHG), mov, t_mov_cmp),
21d799b5
NC
23330 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
23331 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
23332
23333 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
5be8be5d
DG
23334 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
23335 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
23336 OP_RRnpc),
23337 OP_ADDRGLDR),ldst, t_ldst),
23338 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
21d799b5
NC
23339
23340 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23341 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23342 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23343 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23344 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23345 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23346
21d799b5
NC
23347 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
23348 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
bfae80f2 23349
c19d1205 23350 /* Pseudo ops. */
21d799b5 23351 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
2fc8bdac 23352 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
21d799b5 23353 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
74db7efb 23354 tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf),
c19d1205
ZW
23355
23356 /* Thumb-compatibility pseudo ops. */
21d799b5
NC
23357 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
23358 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
23359 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
23360 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
23361 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
23362 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
23363 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
23364 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
23365 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
23366 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
23367 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
23368 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
c19d1205 23369
16a4cf17 23370 /* These may simplify to neg. */
21d799b5
NC
23371 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
23372 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
16a4cf17 23373
173205ca
TP
23374#undef THUMB_VARIANT
23375#define THUMB_VARIANT & arm_ext_os
23376
23377 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
23378 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
23379
c921be7d
NC
23380#undef THUMB_VARIANT
23381#define THUMB_VARIANT & arm_ext_v6
23382
21d799b5 23383 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
c19d1205
ZW
23384
23385 /* V1 instructions with no Thumb analogue prior to V6T2. */
c921be7d
NC
23386#undef THUMB_VARIANT
23387#define THUMB_VARIANT & arm_ext_v6t2
23388
21d799b5
NC
23389 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
23390 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
23391 CL("teqp", 130f000, 2, (RR, SH), cmp),
c19d1205 23392
5be8be5d
DG
23393 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
23394 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
23395 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
23396 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
c19d1205 23397
21d799b5
NC
23398 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23399 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205 23400
21d799b5
NC
23401 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23402 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205
ZW
23403
23404 /* V1 instructions with no Thumb analogue at all. */
21d799b5 23405 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
c19d1205
ZW
23406 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
23407
23408 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
23409 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
23410 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
23411 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
23412 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
23413 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
23414 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
23415 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
23416
c921be7d
NC
23417#undef ARM_VARIANT
23418#define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
23419#undef THUMB_VARIANT
23420#define THUMB_VARIANT & arm_ext_v4t
23421
21d799b5
NC
23422 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
23423 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
c19d1205 23424
c921be7d
NC
23425#undef THUMB_VARIANT
23426#define THUMB_VARIANT & arm_ext_v6t2
23427
21d799b5 23428 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
c19d1205
ZW
23429 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
23430
23431 /* Generic coprocessor instructions. */
21d799b5
NC
23432 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
23433 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23434 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23435 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23436 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23437 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
db472d6f 23438 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
c19d1205 23439
c921be7d
NC
23440#undef ARM_VARIANT
23441#define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
23442
21d799b5 23443 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
c19d1205
ZW
23444 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
23445
c921be7d
NC
23446#undef ARM_VARIANT
23447#define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
23448#undef THUMB_VARIANT
23449#define THUMB_VARIANT & arm_ext_msr
23450
d2cd1205
JB
23451 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
23452 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
c19d1205 23453
c921be7d
NC
23454#undef ARM_VARIANT
23455#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
23456#undef THUMB_VARIANT
23457#define THUMB_VARIANT & arm_ext_v6t2
23458
21d799b5
NC
23459 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
23460 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
23461 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
23462 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
23463 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
23464 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
23465 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
23466 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
c19d1205 23467
c921be7d
NC
23468#undef ARM_VARIANT
23469#define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
23470#undef THUMB_VARIANT
23471#define THUMB_VARIANT & arm_ext_v4t
23472
5be8be5d
DG
23473 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
23474 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
23475 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
23476 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
56c0a61f
RE
23477 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
23478 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
c19d1205 23479
c921be7d
NC
23480#undef ARM_VARIANT
23481#define ARM_VARIANT & arm_ext_v4t_5
23482
c19d1205
ZW
23483 /* ARM Architecture 4T. */
23484 /* Note: bx (and blx) are required on V5, even if the processor does
23485 not support Thumb. */
21d799b5 23486 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
c19d1205 23487
c921be7d
NC
23488#undef ARM_VARIANT
23489#define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
23490#undef THUMB_VARIANT
23491#define THUMB_VARIANT & arm_ext_v5t
23492
c19d1205
ZW
23493 /* Note: blx has 2 variants; the .value coded here is for
23494 BLX(2). Only this variant has conditional execution. */
21d799b5
NC
23495 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
23496 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
c19d1205 23497
c921be7d
NC
23498#undef THUMB_VARIANT
23499#define THUMB_VARIANT & arm_ext_v6t2
23500
21d799b5
NC
23501 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
23502 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23503 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23504 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23505 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23506 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
23507 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
23508 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
c19d1205 23509
c921be7d 23510#undef ARM_VARIANT
74db7efb
NC
23511#define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
23512#undef THUMB_VARIANT
23513#define THUMB_VARIANT & arm_ext_v5exp
c921be7d 23514
21d799b5
NC
23515 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
23516 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
23517 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
23518 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
c19d1205 23519
21d799b5
NC
23520 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
23521 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
c19d1205 23522
21d799b5
NC
23523 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
23524 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
23525 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
23526 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
c19d1205 23527
21d799b5
NC
23528 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23529 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23530 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23531 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
c19d1205 23532
21d799b5
NC
23533 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23534 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
c19d1205 23535
03ee1b7f
NC
23536 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
23537 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
23538 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
23539 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
c19d1205 23540
c921be7d 23541#undef ARM_VARIANT
74db7efb
NC
23542#define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
23543#undef THUMB_VARIANT
23544#define THUMB_VARIANT & arm_ext_v6t2
c921be7d 23545
21d799b5 23546 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
5be8be5d
DG
23547 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
23548 ldrd, t_ldstd),
23549 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
23550 ADDRGLDRS), ldrd, t_ldstd),
c19d1205 23551
21d799b5
NC
23552 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
23553 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
c19d1205 23554
c921be7d
NC
23555#undef ARM_VARIANT
23556#define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
23557
21d799b5 23558 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
c19d1205 23559
c921be7d
NC
23560#undef ARM_VARIANT
23561#define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
23562#undef THUMB_VARIANT
23563#define THUMB_VARIANT & arm_ext_v6
23564
21d799b5
NC
23565 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
23566 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
23567 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
23568 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
23569 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
23570 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23571 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23572 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23573 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23574 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
c19d1205 23575
c921be7d 23576#undef THUMB_VARIANT
ff8646ee 23577#define THUMB_VARIANT & arm_ext_v6t2_v8m
c921be7d 23578
5be8be5d
DG
23579 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
23580 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
23581 strex, t_strex),
ff8646ee
TP
23582#undef THUMB_VARIANT
23583#define THUMB_VARIANT & arm_ext_v6t2
23584
21d799b5
NC
23585 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
23586 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
62b3e311 23587
21d799b5
NC
23588 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
23589 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
62b3e311 23590
9e3c6df6 23591/* ARM V6 not included in V7M. */
c921be7d
NC
23592#undef THUMB_VARIANT
23593#define THUMB_VARIANT & arm_ext_v6_notm
9e3c6df6 23594 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
d709e4e6 23595 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
9e3c6df6
PB
23596 UF(rfeib, 9900a00, 1, (RRw), rfe),
23597 UF(rfeda, 8100a00, 1, (RRw), rfe),
23598 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
23599 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
d709e4e6
RE
23600 UF(rfefa, 8100a00, 1, (RRw), rfe),
23601 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
23602 UF(rfeed, 9900a00, 1, (RRw), rfe),
9e3c6df6 23603 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
d709e4e6
RE
23604 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
23605 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
9e3c6df6 23606 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
d709e4e6 23607 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
9e3c6df6 23608 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
d709e4e6 23609 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
9e3c6df6 23610 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
d709e4e6 23611 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
941c9cad 23612 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
c921be7d 23613
9e3c6df6
PB
23614/* ARM V6 not included in V7M (eg. integer SIMD). */
23615#undef THUMB_VARIANT
23616#define THUMB_VARIANT & arm_ext_v6_dsp
21d799b5
NC
23617 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
23618 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
23619 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23620 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23621 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23622 /* Old name for QASX. */
74db7efb 23623 TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5 23624 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23625 /* Old name for QSAX. */
74db7efb 23626 TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC
23627 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23628 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23629 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23630 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23631 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23632 /* Old name for SASX. */
74db7efb 23633 TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC
23634 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23635 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 23636 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23637 /* Old name for SHASX. */
21d799b5 23638 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 23639 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23640 /* Old name for SHSAX. */
21d799b5
NC
23641 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23642 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23643 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23644 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23645 /* Old name for SSAX. */
74db7efb 23646 TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC
23647 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23648 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23649 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23650 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23651 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23652 /* Old name for UASX. */
74db7efb 23653 TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC
23654 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23655 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 23656 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23657 /* Old name for UHASX. */
21d799b5
NC
23658 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23659 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23660 /* Old name for UHSAX. */
21d799b5
NC
23661 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23662 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23663 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23664 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23665 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 23666 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23667 /* Old name for UQASX. */
21d799b5
NC
23668 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23669 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23670 /* Old name for UQSAX. */
21d799b5
NC
23671 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23672 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23673 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23674 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23675 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23676 /* Old name for USAX. */
74db7efb 23677 TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5 23678 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC
23679 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23680 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23681 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23682 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23683 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23684 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23685 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23686 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23687 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23688 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23689 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23690 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
23691 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
23692 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23693 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23694 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
23695 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
23696 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23697 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23698 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23699 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23700 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23701 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23702 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23703 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23704 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23705 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
21d799b5
NC
23706 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
23707 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
23708 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23709 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23710 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
c19d1205 23711
c921be7d 23712#undef ARM_VARIANT
55e8aae7 23713#define ARM_VARIANT & arm_ext_v6k_v6t2
c921be7d 23714#undef THUMB_VARIANT
55e8aae7 23715#define THUMB_VARIANT & arm_ext_v6k_v6t2
c921be7d 23716
21d799b5
NC
23717 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
23718 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
23719 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
23720 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
c19d1205 23721
c921be7d
NC
23722#undef THUMB_VARIANT
23723#define THUMB_VARIANT & arm_ext_v6_notm
5be8be5d
DG
23724 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
23725 ldrexd, t_ldrexd),
23726 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
23727 RRnpcb), strexd, t_strexd),
ebdca51a 23728
c921be7d 23729#undef THUMB_VARIANT
ff8646ee 23730#define THUMB_VARIANT & arm_ext_v6t2_v8m
5be8be5d
DG
23731 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
23732 rd_rn, rd_rn),
23733 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
23734 rd_rn, rd_rn),
23735 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
877807f8 23736 strex, t_strexbh),
5be8be5d 23737 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
877807f8 23738 strex, t_strexbh),
21d799b5 23739 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
c19d1205 23740
c921be7d 23741#undef ARM_VARIANT
f4c65163 23742#define ARM_VARIANT & arm_ext_sec
74db7efb 23743#undef THUMB_VARIANT
f4c65163 23744#define THUMB_VARIANT & arm_ext_sec
c921be7d 23745
21d799b5 23746 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
c19d1205 23747
90ec0d68
MGD
23748#undef ARM_VARIANT
23749#define ARM_VARIANT & arm_ext_virt
23750#undef THUMB_VARIANT
23751#define THUMB_VARIANT & arm_ext_virt
23752
23753 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
23754 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
23755
ddfded2f
MW
23756#undef ARM_VARIANT
23757#define ARM_VARIANT & arm_ext_pan
23758#undef THUMB_VARIANT
23759#define THUMB_VARIANT & arm_ext_pan
23760
23761 TUF("setpan", 1100000, b610, 1, (I7), setpan, t_setpan),
23762
c921be7d 23763#undef ARM_VARIANT
74db7efb 23764#define ARM_VARIANT & arm_ext_v6t2
f4c65163
MGD
23765#undef THUMB_VARIANT
23766#define THUMB_VARIANT & arm_ext_v6t2
c921be7d 23767
21d799b5
NC
23768 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
23769 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
23770 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
23771 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
c19d1205 23772
21d799b5 23773 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
21d799b5 23774 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
c19d1205 23775
5be8be5d
DG
23776 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
23777 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
23778 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
23779 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
c19d1205 23780
91d8b670
JG
23781#undef ARM_VARIANT
23782#define ARM_VARIANT & arm_ext_v3
23783#undef THUMB_VARIANT
23784#define THUMB_VARIANT & arm_ext_v6t2
23785
23786 TUE("csdb", 320f014, f3af8014, 0, (), noargs, t_csdb),
c597cc3d
SD
23787 TUF("ssbb", 57ff040, f3bf8f40, 0, (), noargs, t_csdb),
23788 TUF("pssbb", 57ff044, f3bf8f44, 0, (), noargs, t_csdb),
91d8b670
JG
23789
23790#undef ARM_VARIANT
23791#define ARM_VARIANT & arm_ext_v6t2
ff8646ee
TP
23792#undef THUMB_VARIANT
23793#define THUMB_VARIANT & arm_ext_v6t2_v8m
23794 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
23795 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
23796
bf3eeda7 23797 /* Thumb-only instructions. */
74db7efb 23798#undef ARM_VARIANT
bf3eeda7
NS
23799#define ARM_VARIANT NULL
23800 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
23801 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
c921be7d
NC
23802
23803 /* ARM does not really have an IT instruction, so always allow it.
23804 The opcode is copied from Thumb in order to allow warnings in
23805 -mimplicit-it=[never | arm] modes. */
23806#undef ARM_VARIANT
23807#define ARM_VARIANT & arm_ext_v1
ff8646ee
TP
23808#undef THUMB_VARIANT
23809#define THUMB_VARIANT & arm_ext_v6t2
c921be7d 23810
21d799b5
NC
23811 TUE("it", bf08, bf08, 1, (COND), it, t_it),
23812 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
23813 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
23814 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
23815 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
23816 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
23817 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
23818 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
23819 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
23820 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
23821 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
23822 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
23823 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
23824 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
23825 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
1c444d06 23826 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
21d799b5
NC
23827 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
23828 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
c19d1205 23829
92e90b6e 23830 /* Thumb2 only instructions. */
c921be7d
NC
23831#undef ARM_VARIANT
23832#define ARM_VARIANT NULL
92e90b6e 23833
21d799b5
NC
23834 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
23835 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
23836 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
23837 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
23838 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
23839 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
92e90b6e 23840
eea54501
MGD
23841 /* Hardware division instructions. */
23842#undef ARM_VARIANT
23843#define ARM_VARIANT & arm_ext_adiv
c921be7d
NC
23844#undef THUMB_VARIANT
23845#define THUMB_VARIANT & arm_ext_div
23846
eea54501
MGD
23847 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
23848 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
62b3e311 23849
7e806470 23850 /* ARM V6M/V7 instructions. */
c921be7d
NC
23851#undef ARM_VARIANT
23852#define ARM_VARIANT & arm_ext_barrier
23853#undef THUMB_VARIANT
23854#define THUMB_VARIANT & arm_ext_barrier
23855
ccb84d65
JB
23856 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
23857 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
23858 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
7e806470 23859
62b3e311 23860 /* ARM V7 instructions. */
c921be7d
NC
23861#undef ARM_VARIANT
23862#define ARM_VARIANT & arm_ext_v7
23863#undef THUMB_VARIANT
23864#define THUMB_VARIANT & arm_ext_v7
23865
21d799b5
NC
23866 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
23867 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
62b3e311 23868
74db7efb 23869#undef ARM_VARIANT
60e5ef9f 23870#define ARM_VARIANT & arm_ext_mp
74db7efb 23871#undef THUMB_VARIANT
60e5ef9f
MGD
23872#define THUMB_VARIANT & arm_ext_mp
23873
23874 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
23875
53c4b28b
MGD
23876 /* AArchv8 instructions. */
23877#undef ARM_VARIANT
23878#define ARM_VARIANT & arm_ext_v8
4ed7ed8d
TP
23879
23880/* Instructions shared between armv8-a and armv8-m. */
53c4b28b 23881#undef THUMB_VARIANT
4ed7ed8d 23882#define THUMB_VARIANT & arm_ext_atomics
53c4b28b 23883
4ed7ed8d
TP
23884 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
23885 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
23886 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
23887 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
23888 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
23889 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
4b8c8c02 23890 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
4b8c8c02
RE
23891 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
23892 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
23893 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
23894 stlex, t_stlex),
4b8c8c02
RE
23895 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
23896 stlex, t_stlex),
23897 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
23898 stlex, t_stlex),
4ed7ed8d
TP
23899#undef THUMB_VARIANT
23900#define THUMB_VARIANT & arm_ext_v8
53c4b28b 23901
4ed7ed8d 23902 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
4ed7ed8d
TP
23903 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
23904 ldrexd, t_ldrexd),
23905 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
23906 strexd, t_strexd),
f7dd2fb2
TC
23907
23908/* Defined in V8 but is in undefined encoding space for earlier
23909 architectures. However earlier architectures are required to treat
23910 this instuction as a semihosting trap as well. Hence while not explicitly
23911 defined as such, it is in fact correct to define the instruction for all
23912 architectures. */
23913#undef THUMB_VARIANT
23914#define THUMB_VARIANT & arm_ext_v1
23915#undef ARM_VARIANT
23916#define ARM_VARIANT & arm_ext_v1
23917 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
23918
8884b720 23919 /* ARMv8 T32 only. */
74db7efb 23920#undef ARM_VARIANT
b79f7053
MGD
23921#define ARM_VARIANT NULL
23922 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
23923 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
23924 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
23925
33399f07
MGD
23926 /* FP for ARMv8. */
23927#undef ARM_VARIANT
a715796b 23928#define ARM_VARIANT & fpu_vfp_ext_armv8xd
33399f07 23929#undef THUMB_VARIANT
a715796b 23930#define THUMB_VARIANT & fpu_vfp_ext_armv8xd
33399f07
MGD
23931
23932 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
23933 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
23934 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
23935 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
30bdf752 23936 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
a710b305
AV
23937 mnCE(vrintz, _vrintr, 2, (RNSDQMQ, oRNSDQMQ), vrintz),
23938 mnCE(vrintx, _vrintr, 2, (RNSDQMQ, oRNSDQMQ), vrintx),
23939 mnUF(vrinta, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrinta),
23940 mnUF(vrintn, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintn),
23941 mnUF(vrintp, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintp),
23942 mnUF(vrintm, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintm),
33399f07 23943
91ff7894
MGD
23944 /* Crypto v1 extensions. */
23945#undef ARM_VARIANT
23946#define ARM_VARIANT & fpu_crypto_ext_armv8
23947#undef THUMB_VARIANT
23948#define THUMB_VARIANT & fpu_crypto_ext_armv8
23949
23950 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
23951 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
23952 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
23953 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
48adcd8e
MGD
23954 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
23955 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
23956 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
23957 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
23958 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
23959 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
23960 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
3c9017d2
MGD
23961 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
23962 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
23963 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
91ff7894 23964
dd5181d5 23965#undef ARM_VARIANT
74db7efb 23966#define ARM_VARIANT & crc_ext_armv8
dd5181d5
KT
23967#undef THUMB_VARIANT
23968#define THUMB_VARIANT & crc_ext_armv8
23969 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
23970 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
23971 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
23972 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
23973 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
23974 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
23975
105bde57
MW
23976 /* ARMv8.2 RAS extension. */
23977#undef ARM_VARIANT
4d1464f2 23978#define ARM_VARIANT & arm_ext_ras
105bde57 23979#undef THUMB_VARIANT
4d1464f2 23980#define THUMB_VARIANT & arm_ext_ras
105bde57
MW
23981 TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs),
23982
49e8a725
SN
23983#undef ARM_VARIANT
23984#define ARM_VARIANT & arm_ext_v8_3
23985#undef THUMB_VARIANT
23986#define THUMB_VARIANT & arm_ext_v8_3
23987 NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt),
23988
c604a79a
JW
23989#undef ARM_VARIANT
23990#define ARM_VARIANT & fpu_neon_ext_dotprod
23991#undef THUMB_VARIANT
23992#define THUMB_VARIANT & fpu_neon_ext_dotprod
23993 NUF (vsdot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_s),
23994 NUF (vudot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_u),
23995
c921be7d
NC
23996#undef ARM_VARIANT
23997#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
53c4b28b
MGD
23998#undef THUMB_VARIANT
23999#define THUMB_VARIANT NULL
c921be7d 24000
21d799b5
NC
24001 cCE("wfs", e200110, 1, (RR), rd),
24002 cCE("rfs", e300110, 1, (RR), rd),
24003 cCE("wfc", e400110, 1, (RR), rd),
24004 cCE("rfc", e500110, 1, (RR), rd),
24005
24006 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
24007 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
24008 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
24009 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
24010
24011 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
24012 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
24013 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
24014 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
24015
24016 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
24017 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
24018 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
24019 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
24020 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
24021 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
24022 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
24023 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
24024 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
24025 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
24026 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
24027 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
24028
24029 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
24030 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
24031 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
24032 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
24033 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
24034 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
24035 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
24036 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
24037 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
24038 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
24039 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
24040 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
24041
24042 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
24043 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
24044 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
24045 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
24046 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
24047 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
24048 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
24049 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
24050 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
24051 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
24052 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
24053 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
24054
24055 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
24056 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
24057 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
24058 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
24059 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
24060 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
24061 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
24062 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
24063 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
24064 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
24065 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
24066 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
24067
24068 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
24069 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
24070 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
24071 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
24072 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
24073 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
24074 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
24075 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
24076 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
24077 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
24078 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
24079 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
24080
24081 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
24082 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
24083 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
24084 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
24085 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
24086 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
24087 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
24088 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
24089 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
24090 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
24091 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
24092 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
24093
24094 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
24095 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
24096 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
24097 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
24098 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
24099 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
24100 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
24101 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
24102 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
24103 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
24104 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
24105 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
24106
24107 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
24108 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
24109 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
24110 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
24111 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
24112 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
24113 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
24114 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
24115 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
24116 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
24117 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
24118 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
24119
24120 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
24121 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
24122 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
24123 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
24124 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
24125 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
24126 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
24127 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
24128 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
24129 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
24130 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
24131 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
24132
24133 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
24134 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
24135 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
24136 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
24137 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
24138 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
24139 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
24140 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
24141 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
24142 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
24143 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
24144 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
24145
24146 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
24147 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
24148 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
24149 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
24150 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
24151 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
24152 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
24153 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
24154 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
24155 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
24156 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
24157 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
24158
24159 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
24160 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
24161 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
24162 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
24163 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
24164 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
24165 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
24166 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
24167 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
24168 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
24169 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
24170 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
24171
24172 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
24173 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
24174 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
24175 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
24176 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
24177 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
24178 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
24179 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
24180 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
24181 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
24182 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
24183 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
24184
24185 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
24186 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
24187 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
24188 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
24189 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
24190 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
24191 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
24192 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
24193 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
24194 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
24195 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
24196 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
24197
24198 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
24199 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
24200 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
24201 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
24202 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
24203 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
24204 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
24205 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
24206 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
24207 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
24208 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
24209 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
24210
24211 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
24212 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
24213 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
24214 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
24215 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
24216 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
24217 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
24218 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
24219 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
24220 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
24221 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
24222 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
24223
24224 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
24225 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
24226 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
24227 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
24228 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
24229 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24230 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24231 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24232 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
24233 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
24234 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
24235 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
24236
24237 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
24238 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
24239 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
24240 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
24241 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
24242 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24243 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24244 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24245 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
24246 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
24247 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
24248 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
24249
24250 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
24251 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
24252 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
24253 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
24254 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
24255 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24256 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24257 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24258 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
24259 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
24260 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
24261 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
24262
24263 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
24264 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
24265 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
24266 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
24267 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
24268 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24269 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24270 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24271 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
24272 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
24273 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
24274 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
24275
24276 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
24277 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
24278 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
24279 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
24280 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
24281 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24282 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24283 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24284 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
24285 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
24286 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
24287 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
24288
24289 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
24290 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
24291 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
24292 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
24293 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
24294 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24295 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24296 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24297 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
24298 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
24299 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
24300 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
24301
24302 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
24303 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
24304 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
24305 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
24306 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
24307 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24308 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24309 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24310 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
24311 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
24312 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
24313 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
24314
24315 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
24316 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
24317 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
24318 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
24319 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
24320 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24321 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24322 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24323 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
24324 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
24325 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
24326 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
24327
24328 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
24329 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
24330 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
24331 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
24332 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
24333 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24334 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24335 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24336 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
24337 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
24338 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
24339 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
24340
24341 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
24342 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
24343 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
24344 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
24345 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
24346 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24347 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24348 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24349 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
24350 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
24351 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
24352 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
24353
24354 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
24355 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
24356 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
24357 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
24358 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
24359 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24360 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24361 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24362 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
24363 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
24364 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
24365 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
24366
24367 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
24368 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
24369 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
24370 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
24371 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
24372 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24373 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24374 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24375 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
24376 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
24377 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
24378 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
24379
24380 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
24381 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
24382 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
24383 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
24384 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
24385 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24386 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24387 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24388 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
24389 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
24390 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
24391 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
24392
24393 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
24394 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
24395 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
24396 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
24397
24398 cCL("flts", e000110, 2, (RF, RR), rn_rd),
24399 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
24400 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
24401 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
24402 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
24403 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
24404 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
24405 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
24406 cCL("flte", e080110, 2, (RF, RR), rn_rd),
24407 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
24408 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
24409 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
b99bd4ef 24410
c19d1205
ZW
24411 /* The implementation of the FIX instruction is broken on some
24412 assemblers, in that it accepts a precision specifier as well as a
24413 rounding specifier, despite the fact that this is meaningless.
24414 To be more compatible, we accept it as well, though of course it
24415 does not set any bits. */
21d799b5
NC
24416 cCE("fix", e100110, 2, (RR, RF), rd_rm),
24417 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
24418 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
24419 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
24420 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
24421 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
24422 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
24423 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
24424 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
24425 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
24426 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
24427 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
24428 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
bfae80f2 24429
c19d1205 24430 /* Instructions that were new with the real FPA, call them V2. */
c921be7d
NC
24431#undef ARM_VARIANT
24432#define ARM_VARIANT & fpu_fpa_ext_v2
24433
21d799b5
NC
24434 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24435 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24436 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24437 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24438 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24439 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
c19d1205 24440
c921be7d
NC
24441#undef ARM_VARIANT
24442#define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
24443
c19d1205 24444 /* Moves and type conversions. */
21d799b5 24445 cCE("fmstat", ef1fa10, 0, (), noargs),
7465e07a
NC
24446 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
24447 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
21d799b5
NC
24448 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
24449 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
24450 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
24451 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
24452 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
24453 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
24454 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
24455 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
c19d1205
ZW
24456
24457 /* Memory operations. */
21d799b5
NC
24458 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
24459 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
55881a11
MGD
24460 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
24461 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
24462 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
24463 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
24464 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
24465 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
24466 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
24467 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
24468 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
24469 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
24470 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
24471 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
24472 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
24473 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
24474 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
24475 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
bfae80f2 24476
c19d1205 24477 /* Monadic operations. */
21d799b5
NC
24478 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
24479 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
24480 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
c19d1205
ZW
24481
24482 /* Dyadic operations. */
21d799b5
NC
24483 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24484 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24485 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24486 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24487 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24488 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24489 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24490 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24491 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
b99bd4ef 24492
c19d1205 24493 /* Comparisons. */
21d799b5
NC
24494 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
24495 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
24496 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
24497 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
b99bd4ef 24498
62f3b8c8
PB
24499 /* Double precision load/store are still present on single precision
24500 implementations. */
24501 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
24502 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
55881a11
MGD
24503 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
24504 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
24505 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
24506 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
24507 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
24508 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
24509 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
24510 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
62f3b8c8 24511
c921be7d
NC
24512#undef ARM_VARIANT
24513#define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
24514
c19d1205 24515 /* Moves and type conversions. */
21d799b5
NC
24516 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
24517 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
24518 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
24519 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
24520 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
24521 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
24522 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
24523 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
24524 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
24525 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
24526 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
24527 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
c19d1205 24528
c19d1205 24529 /* Monadic operations. */
21d799b5
NC
24530 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
24531 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
24532 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
c19d1205
ZW
24533
24534 /* Dyadic operations. */
21d799b5
NC
24535 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24536 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24537 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24538 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24539 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24540 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24541 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24542 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24543 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
b99bd4ef 24544
c19d1205 24545 /* Comparisons. */
21d799b5
NC
24546 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
24547 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
24548 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
24549 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
c19d1205 24550
037e8744
JB
24551/* Instructions which may belong to either the Neon or VFP instruction sets.
24552 Individual encoder functions perform additional architecture checks. */
c921be7d
NC
24553#undef ARM_VARIANT
24554#define ARM_VARIANT & fpu_vfp_ext_v1xd
24555#undef THUMB_VARIANT
24556#define THUMB_VARIANT & fpu_vfp_ext_v1xd
24557
037e8744
JB
24558 /* These mnemonics are unique to VFP. */
24559 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
24560 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
21d799b5
NC
24561 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
24562 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
24563 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
037e8744
JB
24564 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
24565 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
24566 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
24567
24568 /* Mnemonics shared by Neon and VFP. */
21d799b5 24569 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
037e8744 24570
55881a11
MGD
24571 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24572 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24573 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24574 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24575 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24576 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
037e8744 24577
dd9634d9 24578 mnCEF(vcvt, _vcvt, 3, (RNSDQMQ, RNSDQMQ, oI32z), neon_cvt),
e3e535bc 24579 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
dd9634d9
AV
24580 MNCEF(vcvtb, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtb),
24581 MNCEF(vcvtt, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtt),
f31fef98 24582
037e8744
JB
24583
24584 /* NOTE: All VMOV encoding is special-cased! */
037e8744
JB
24585 NCE(vmovq, 0, 1, (VMOV), neon_mov),
24586
32c36c3c
AV
24587#undef THUMB_VARIANT
24588/* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
24589 by different feature bits. Since we are setting the Thumb guard, we can
24590 require Thumb-1 which makes it a nop guard and set the right feature bit in
24591 do_vldr_vstr (). */
24592#define THUMB_VARIANT & arm_ext_v4t
24593 NCE(vldr, d100b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
24594 NCE(vstr, d000b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
24595
9db2f6b4
RL
24596#undef ARM_VARIANT
24597#define ARM_VARIANT & arm_ext_fp16
24598#undef THUMB_VARIANT
24599#define THUMB_VARIANT & arm_ext_fp16
24600 /* New instructions added from v8.2, allowing the extraction and insertion of
24601 the upper 16 bits of a 32-bit vector register. */
24602 NCE (vmovx, eb00a40, 2, (RVS, RVS), neon_movhf),
24603 NCE (vins, eb00ac0, 2, (RVS, RVS), neon_movhf),
24604
dec41383
JW
24605 /* New backported fma/fms instructions optional in v8.2. */
24606 NCE (vfmal, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmal),
24607 NCE (vfmsl, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmsl),
24608
c921be7d
NC
24609#undef THUMB_VARIANT
24610#define THUMB_VARIANT & fpu_neon_ext_v1
24611#undef ARM_VARIANT
24612#define ARM_VARIANT & fpu_neon_ext_v1
24613
5287ad62
JB
24614 /* Data processing with three registers of the same length. */
24615 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
24616 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
24617 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
5287ad62 24618 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
5287ad62 24619 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
5287ad62
JB
24620 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
24621 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
5287ad62 24622 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
5287ad62 24623 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
627907b7 24624 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
627907b7 24625 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
5287ad62 24626 /* If not immediate, fall back to neon_dyadic_i64_su.
5150f0d8
AV
24627 shl should accept I8 I16 I32 I64,
24628 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
24629 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl),
24630 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl),
5287ad62 24631 /* Logic ops, types optional & ignored. */
4316f0d2 24632 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
4316f0d2 24633 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
4316f0d2 24634 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
4316f0d2 24635 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
4316f0d2 24636 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
5287ad62
JB
24637 /* Bitfield ops, untyped. */
24638 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
24639 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
24640 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
24641 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
24642 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
24643 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
cc933301 24644 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
21d799b5 24645 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
21d799b5 24646 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
21d799b5 24647 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
5287ad62
JB
24648 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
24649 back to neon_dyadic_if_su. */
21d799b5
NC
24650 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
24651 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
24652 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
24653 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
24654 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
24655 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
24656 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
24657 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
428e3f1f 24658 /* Comparison. Type I8 I16 I32 F32. */
21d799b5
NC
24659 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
24660 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
5287ad62 24661 /* As above, D registers only. */
21d799b5
NC
24662 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
24663 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
5287ad62 24664 /* Int and float variants, signedness unimportant. */
21d799b5
NC
24665 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
24666 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
24667 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
5287ad62 24668 /* Add/sub take types I8 I16 I32 I64 F32. */
21d799b5
NC
24669 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
24670 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
5287ad62
JB
24671 /* vtst takes sizes 8, 16, 32. */
24672 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
24673 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
24674 /* VMUL takes I8 I16 I32 F32 P8. */
21d799b5 24675 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
5287ad62 24676 /* VQD{R}MULH takes S16 S32. */
21d799b5 24677 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
21d799b5 24678 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
5287ad62
JB
24679 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
24680 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
24681 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
24682 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
92559b5b
PB
24683 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
24684 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
24685 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
24686 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
5287ad62
JB
24687 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
24688 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
24689 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
24690 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
d6b4b13e 24691 /* ARM v8.1 extension. */
643afb90
MW
24692 nUF (vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
24693 nUF (vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
24694 nUF (vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
5287ad62
JB
24695
24696 /* Two address, int/float. Types S8 S16 S32 F32. */
5287ad62 24697 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
5287ad62
JB
24698 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
24699
24700 /* Data processing with two registers and a shift amount. */
24701 /* Right shifts, and variants with rounding.
24702 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
5287ad62 24703 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
5287ad62
JB
24704 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
24705 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
24706 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
24707 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
24708 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
24709 /* Shift and insert. Sizes accepted 8 16 32 64. */
5287ad62 24710 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
5287ad62
JB
24711 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
24712 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
5287ad62
JB
24713 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
24714 /* Right shift immediate, saturating & narrowing, with rounding variants.
24715 Types accepted S16 S32 S64 U16 U32 U64. */
24716 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
24717 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
24718 /* As above, unsigned. Types accepted S16 S32 S64. */
24719 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
24720 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
24721 /* Right shift narrowing. Types accepted I16 I32 I64. */
24722 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
24723 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
24724 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
21d799b5 24725 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
5287ad62 24726 /* CVT with optional immediate for fixed-point variant. */
21d799b5 24727 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
b7fc2769 24728
4316f0d2 24729 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
5287ad62
JB
24730
24731 /* Data processing, three registers of different lengths. */
24732 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
24733 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
5287ad62
JB
24734 /* If not scalar, fall back to neon_dyadic_long.
24735 Vector types as above, scalar types S16 S32 U16 U32. */
21d799b5
NC
24736 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
24737 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
5287ad62
JB
24738 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
24739 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
24740 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
24741 /* Dyadic, narrowing insns. Types I16 I32 I64. */
24742 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24743 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24744 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24745 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24746 /* Saturating doubling multiplies. Types S16 S32. */
21d799b5
NC
24747 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
24748 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
24749 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
5287ad62
JB
24750 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
24751 S16 S32 U16 U32. */
21d799b5 24752 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
5287ad62
JB
24753
24754 /* Extract. Size 8. */
3b8d421e
PB
24755 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
24756 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
5287ad62
JB
24757
24758 /* Two registers, miscellaneous. */
24759 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
5287ad62 24760 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
5287ad62 24761 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
5287ad62
JB
24762 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
24763 /* Vector replicate. Sizes 8 16 32. */
21d799b5 24764 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
5287ad62
JB
24765 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
24766 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
24767 /* VMOVN. Types I16 I32 I64. */
21d799b5 24768 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
5287ad62 24769 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21d799b5 24770 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
5287ad62 24771 /* VQMOVUN. Types S16 S32 S64. */
21d799b5 24772 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
5287ad62
JB
24773 /* VZIP / VUZP. Sizes 8 16 32. */
24774 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
24775 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
24776 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
24777 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
24778 /* VQABS / VQNEG. Types S8 S16 S32. */
5287ad62 24779 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
5287ad62
JB
24780 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
24781 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
24782 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
24783 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
24784 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
24785 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
cc933301 24786 /* Reciprocal estimates. Types U32 F16 F32. */
5287ad62
JB
24787 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
24788 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
24789 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
24790 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
24791 /* VCLS. Types S8 S16 S32. */
5287ad62
JB
24792 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
24793 /* VCLZ. Types I8 I16 I32. */
5287ad62
JB
24794 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
24795 /* VCNT. Size 8. */
24796 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
24797 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
24798 /* Two address, untyped. */
24799 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
24800 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
24801 /* VTRN. Sizes 8 16 32. */
21d799b5
NC
24802 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
24803 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
5287ad62
JB
24804
24805 /* Table lookup. Size 8. */
24806 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
24807 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
24808
c921be7d
NC
24809#undef THUMB_VARIANT
24810#define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
24811#undef ARM_VARIANT
24812#define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
24813
5287ad62 24814 /* Neon element/structure load/store. */
21d799b5
NC
24815 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
24816 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
24817 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
24818 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
24819 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
24820 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
24821 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
24822 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
5287ad62 24823
c921be7d 24824#undef THUMB_VARIANT
74db7efb
NC
24825#define THUMB_VARIANT & fpu_vfp_ext_v3xd
24826#undef ARM_VARIANT
24827#define ARM_VARIANT & fpu_vfp_ext_v3xd
62f3b8c8
PB
24828 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
24829 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
24830 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
24831 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
24832 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
24833 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
24834 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
24835 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
24836 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
24837
74db7efb 24838#undef THUMB_VARIANT
c921be7d
NC
24839#define THUMB_VARIANT & fpu_vfp_ext_v3
24840#undef ARM_VARIANT
24841#define ARM_VARIANT & fpu_vfp_ext_v3
24842
21d799b5 24843 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
21d799b5 24844 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 24845 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 24846 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 24847 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 24848 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 24849 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 24850 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 24851 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
c19d1205 24852
74db7efb
NC
24853#undef ARM_VARIANT
24854#define ARM_VARIANT & fpu_vfp_ext_fma
24855#undef THUMB_VARIANT
24856#define THUMB_VARIANT & fpu_vfp_ext_fma
d58196e0 24857 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
62f3b8c8
PB
24858 VFP FMA variant; NEON and VFP FMA always includes the NEON
24859 FMA instructions. */
d58196e0
AV
24860 mnCEF(vfma, _vfma, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_fmac),
24861 mnCEF(vfms, _vfms, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), neon_fmac),
24862
62f3b8c8
PB
24863 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
24864 the v form should always be used. */
24865 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24866 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24867 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24868 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24869 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
24870 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
24871
5287ad62 24872#undef THUMB_VARIANT
c921be7d
NC
24873#undef ARM_VARIANT
24874#define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
24875
21d799b5
NC
24876 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24877 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24878 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24879 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24880 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24881 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24882 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
24883 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
c19d1205 24884
c921be7d
NC
24885#undef ARM_VARIANT
24886#define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
24887
21d799b5
NC
24888 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
24889 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
24890 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
24891 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
24892 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
24893 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
24894 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
24895 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
24896 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
74db7efb
NC
24897 cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
24898 cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
24899 cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
24900 cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
24901 cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
24902 cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
21d799b5
NC
24903 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
24904 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
24905 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
24906 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
24907 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
24908 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24909 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24910 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24911 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24912 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24913 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
74db7efb
NC
24914 cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn),
24915 cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn),
24916 cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn),
21d799b5
NC
24917 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
24918 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
24919 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
24920 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
24921 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
24922 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
24923 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
24924 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
24925 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24926 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24927 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24928 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24929 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24930 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24931 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24932 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24933 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24934 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
74db7efb
NC
24935 cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24936 cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24937 cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24938 cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21d799b5
NC
24939 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24940 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24941 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24942 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24943 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24944 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24945 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24946 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24947 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
74db7efb
NC
24948 cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24949 cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24950 cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24951 cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24952 cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24953 cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21d799b5
NC
24954 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
24955 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
24956 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
24957 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
24958 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24959 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24960 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24961 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24962 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24963 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24964 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24965 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24966 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24967 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24968 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24969 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24970 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24971 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24972 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24973 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24974 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24975 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24976 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
24977 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24978 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24979 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24980 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24981 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
74db7efb
NC
24982 cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24983 cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24984 cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24985 cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24986 cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24987 cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21d799b5
NC
24988 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24989 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24990 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24991 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24992 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24993 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24994 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24995 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24996 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24997 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24998 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
24999 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25000 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25001 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25002 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25003 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25004 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25005 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25006 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25007 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25008 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25009 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25010 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25011 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25012 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25013 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25014 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25015 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25016 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25017 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
25018 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
25019 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
25020 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
25021 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25022 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25023 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25024 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25025 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25026 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25027 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25028 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25029 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25030 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
25031 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
25032 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
25033 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
25034 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
25035 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
25036 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25037 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25038 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25039 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
25040 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
25041 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
25042 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
25043 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
25044 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
25045 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25046 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25047 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25048 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25049 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
c19d1205 25050
c921be7d
NC
25051#undef ARM_VARIANT
25052#define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
25053
21d799b5
NC
25054 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
25055 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
25056 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
25057 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
25058 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
25059 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
25060 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25061 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25062 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25063 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25064 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25065 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25066 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25067 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25068 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25069 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25070 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25071 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25072 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25073 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25074 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
25075 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25076 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25077 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25078 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25079 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25080 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25081 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25082 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25083 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25084 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25085 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25086 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25087 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25088 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25089 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25090 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25091 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25092 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25093 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25094 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25095 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25096 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25097 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25098 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25099 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25100 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25101 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25102 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25103 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25104 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25105 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25106 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25107 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25108 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25109 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25110 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
2d447fca 25111
c921be7d
NC
25112#undef ARM_VARIANT
25113#define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
25114
21d799b5
NC
25115 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
25116 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
25117 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
25118 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
25119 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
25120 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
25121 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
25122 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
25123 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
25124 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
25125 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
25126 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
25127 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
25128 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
74db7efb
NC
25129 cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd),
25130 cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn),
25131 cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd),
25132 cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn),
25133 cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn),
25134 cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn),
25135 cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn),
25136 cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn),
25137 cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn),
25138 cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn),
21d799b5
NC
25139 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
25140 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
25141 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
25142 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
74db7efb
NC
25143 cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc),
25144 cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd),
21d799b5
NC
25145 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
25146 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
25147 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
25148 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
74db7efb
NC
25149 cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn),
25150 cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn),
25151 cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn),
25152 cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn),
25153 cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn),
25154 cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn),
21d799b5
NC
25155 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
25156 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
74db7efb
NC
25157 cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple),
25158 cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple),
21d799b5
NC
25159 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
25160 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
25161 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
25162 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
25163 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
25164 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
25165 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
25166 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
25167 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
25168 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
25169 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
25170 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
25171 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
25172 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
25173 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
25174 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
25175 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
25176 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
25177 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
25178 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
25179 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
25180 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
25181 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
25182 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
25183 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
25184 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
25185 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
25186 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
74db7efb
NC
25187 cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
25188 cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
21d799b5
NC
25189 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
25190 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
4ed7ed8d 25191
7fadb25d
SD
25192 /* ARMv8.5-A instructions. */
25193#undef ARM_VARIANT
25194#define ARM_VARIANT & arm_ext_sb
25195#undef THUMB_VARIANT
25196#define THUMB_VARIANT & arm_ext_sb
25197 TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs),
25198
dad0c3bf
SD
25199#undef ARM_VARIANT
25200#define ARM_VARIANT & arm_ext_predres
25201#undef THUMB_VARIANT
25202#define THUMB_VARIANT & arm_ext_predres
25203 CE("cfprctx", e070f93, 1, (RRnpc), rd),
25204 CE("dvprctx", e070fb3, 1, (RRnpc), rd),
25205 CE("cpprctx", e070ff3, 1, (RRnpc), rd),
25206
16a1fa25 25207 /* ARMv8-M instructions. */
4ed7ed8d
TP
25208#undef ARM_VARIANT
25209#define ARM_VARIANT NULL
25210#undef THUMB_VARIANT
25211#define THUMB_VARIANT & arm_ext_v8m
cf3cf39d
TP
25212 ToU("sg", e97fe97f, 0, (), noargs),
25213 ToC("blxns", 4784, 1, (RRnpc), t_blx),
25214 ToC("bxns", 4704, 1, (RRnpc), t_bx),
25215 ToC("tt", e840f000, 2, (RRnpc, RRnpc), tt),
25216 ToC("ttt", e840f040, 2, (RRnpc, RRnpc), tt),
25217 ToC("tta", e840f080, 2, (RRnpc, RRnpc), tt),
25218 ToC("ttat", e840f0c0, 2, (RRnpc, RRnpc), tt),
16a1fa25
TP
25219
25220 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
25221 instructions behave as nop if no VFP is present. */
25222#undef THUMB_VARIANT
25223#define THUMB_VARIANT & arm_ext_v8m_main
cf3cf39d
TP
25224 ToC("vlldm", ec300a00, 1, (RRnpc), rn),
25225 ToC("vlstm", ec200a00, 1, (RRnpc), rn),
4389b29a
AV
25226
25227 /* Armv8.1-M Mainline instructions. */
25228#undef THUMB_VARIANT
25229#define THUMB_VARIANT & arm_ext_v8_1m_main
e39c1607
SD
25230 toU("cinc", _cinc, 3, (RRnpcsp, RR_ZR, COND), t_cond),
25231 toU("cinv", _cinv, 3, (RRnpcsp, RR_ZR, COND), t_cond),
25232 toU("cneg", _cneg, 3, (RRnpcsp, RR_ZR, COND), t_cond),
25233 toU("csel", _csel, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
25234 toU("csetm", _csetm, 2, (RRnpcsp, COND), t_cond),
25235 toU("cset", _cset, 2, (RRnpcsp, COND), t_cond),
25236 toU("csinc", _csinc, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
25237 toU("csinv", _csinv, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
25238 toU("csneg", _csneg, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
25239
4389b29a 25240 toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
f6b2b12d 25241 toU("bfcsel", _bfcsel, 4, (EXPs, EXPs, EXPs, COND), t_branch_future),
f1c7f421 25242 toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future),
65d1bc05 25243 toC("bfl", _bfl, 2, (EXPs, EXPs), t_branch_future),
f1c7f421 25244 toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future),
60f993ce
AV
25245
25246 toU("dls", _dls, 2, (LR, RRnpcsp), t_loloop),
25247 toU("wls", _wls, 3, (LR, RRnpcsp, EXP), t_loloop),
25248 toU("le", _le, 2, (oLR, EXP), t_loloop),
4b5a202f 25249
efd6b359 25250 ToC("clrm", e89f0000, 1, (CLRMLST), t_clrm),
5ee91343
AV
25251 ToC("vscclrm", ec9f0a00, 1, (VRSDVLST), t_vscclrm),
25252
25253#undef THUMB_VARIANT
25254#define THUMB_VARIANT & mve_ext
23d00a41
SD
25255 ToC("lsll", ea50010d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift),
25256 ToC("lsrl", ea50011f, 3, (RRe, RRo, I32), mve_scalar_shift),
25257 ToC("asrl", ea50012d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift),
25258 ToC("uqrshll", ea51010d, 3, (RRe, RRo, RRnpcsp), mve_scalar_shift),
25259 ToC("sqrshrl", ea51012d, 3, (RRe, RRo, RRnpcsp), mve_scalar_shift),
25260 ToC("uqshll", ea51010f, 3, (RRe, RRo, I32), mve_scalar_shift),
25261 ToC("urshrl", ea51011f, 3, (RRe, RRo, I32), mve_scalar_shift),
25262 ToC("srshrl", ea51012f, 3, (RRe, RRo, I32), mve_scalar_shift),
25263 ToC("sqshll", ea51013f, 3, (RRe, RRo, I32), mve_scalar_shift),
25264 ToC("uqrshl", ea500f0d, 2, (RRnpcsp, RRnpcsp), mve_scalar_shift),
25265 ToC("sqrshr", ea500f2d, 2, (RRnpcsp, RRnpcsp), mve_scalar_shift),
25266 ToC("uqshl", ea500f0f, 2, (RRnpcsp, I32), mve_scalar_shift),
25267 ToC("urshr", ea500f1f, 2, (RRnpcsp, I32), mve_scalar_shift),
25268 ToC("srshr", ea500f2f, 2, (RRnpcsp, I32), mve_scalar_shift),
25269 ToC("sqshl", ea500f3f, 2, (RRnpcsp, I32), mve_scalar_shift),
1b883319
AV
25270
25271 ToC("vpt", ee410f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25272 ToC("vptt", ee018f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25273 ToC("vpte", ee418f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25274 ToC("vpttt", ee014f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25275 ToC("vptte", ee01cf00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25276 ToC("vptet", ee41cf00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25277 ToC("vptee", ee414f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25278 ToC("vptttt", ee012f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25279 ToC("vpttte", ee016f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25280 ToC("vpttet", ee01ef00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25281 ToC("vpttee", ee01af00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25282 ToC("vptett", ee41af00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25283 ToC("vptete", ee41ef00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25284 ToC("vpteet", ee416f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25285 ToC("vpteee", ee412f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25286
5ee91343
AV
25287 ToC("vpst", fe710f4d, 0, (), mve_vpt),
25288 ToC("vpstt", fe318f4d, 0, (), mve_vpt),
25289 ToC("vpste", fe718f4d, 0, (), mve_vpt),
25290 ToC("vpsttt", fe314f4d, 0, (), mve_vpt),
25291 ToC("vpstte", fe31cf4d, 0, (), mve_vpt),
25292 ToC("vpstet", fe71cf4d, 0, (), mve_vpt),
25293 ToC("vpstee", fe714f4d, 0, (), mve_vpt),
25294 ToC("vpstttt", fe312f4d, 0, (), mve_vpt),
25295 ToC("vpsttte", fe316f4d, 0, (), mve_vpt),
25296 ToC("vpsttet", fe31ef4d, 0, (), mve_vpt),
25297 ToC("vpsttee", fe31af4d, 0, (), mve_vpt),
25298 ToC("vpstett", fe71af4d, 0, (), mve_vpt),
25299 ToC("vpstete", fe71ef4d, 0, (), mve_vpt),
25300 ToC("vpsteet", fe716f4d, 0, (), mve_vpt),
25301 ToC("vpsteee", fe712f4d, 0, (), mve_vpt),
25302
a302e574 25303 /* MVE and MVE FP only. */
7df54120 25304 mToC("vhcadd", ee000f00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vhcadd),
c2dafc2a
AV
25305 mCEF(vadc, _vadc, 3, (RMQ, RMQ, RMQ), mve_vadc),
25306 mCEF(vadci, _vadci, 3, (RMQ, RMQ, RMQ), mve_vadc),
25307 mToC("vsbc", fe300f00, 3, (RMQ, RMQ, RMQ), mve_vsbc),
25308 mToC("vsbci", fe301f00, 3, (RMQ, RMQ, RMQ), mve_vsbc),
886e1c73 25309 mCEF(vmullb, _vmullb, 3, (RMQ, RMQ, RMQ), mve_vmull),
a302e574
AV
25310 mCEF(vabav, _vabav, 3, (RRnpcsp, RMQ, RMQ), mve_vabav),
25311 mCEF(vmladav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
25312 mCEF(vmladava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav),
25313 mCEF(vmladavx, _vmladavx, 3, (RRe, RMQ, RMQ), mve_vmladav),
25314 mCEF(vmladavax, _vmladavax, 3, (RRe, RMQ, RMQ), mve_vmladav),
25315 mCEF(vmlav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
25316 mCEF(vmlava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav),
25317 mCEF(vmlsdav, _vmlsdav, 3, (RRe, RMQ, RMQ), mve_vmladav),
25318 mCEF(vmlsdava, _vmlsdava, 3, (RRe, RMQ, RMQ), mve_vmladav),
25319 mCEF(vmlsdavx, _vmlsdavx, 3, (RRe, RMQ, RMQ), mve_vmladav),
25320 mCEF(vmlsdavax, _vmlsdavax, 3, (RRe, RMQ, RMQ), mve_vmladav),
25321
35c228db
AV
25322 mCEF(vst20, _vst20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
25323 mCEF(vst21, _vst21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
25324 mCEF(vst40, _vst40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25325 mCEF(vst41, _vst41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25326 mCEF(vst42, _vst42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25327 mCEF(vst43, _vst43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25328 mCEF(vld20, _vld20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
25329 mCEF(vld21, _vld21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
25330 mCEF(vld40, _vld40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25331 mCEF(vld41, _vld41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25332 mCEF(vld42, _vld42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25333 mCEF(vld43, _vld43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
f5f10c66
AV
25334 mCEF(vstrb, _vstrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25335 mCEF(vstrh, _vstrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25336 mCEF(vstrw, _vstrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25337 mCEF(vstrd, _vstrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25338 mCEF(vldrb, _vldrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25339 mCEF(vldrh, _vldrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25340 mCEF(vldrw, _vldrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25341 mCEF(vldrd, _vldrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
35c228db 25342
57785aa2
AV
25343 mCEF(vmovnt, _vmovnt, 2, (RMQ, RMQ), mve_movn),
25344 mCEF(vmovnb, _vmovnb, 2, (RMQ, RMQ), mve_movn),
c2dafc2a 25345 mCEF(vbrsr, _vbrsr, 3, (RMQ, RMQ, RR), mve_vbrsr),
26c1e780
AV
25346 mCEF(vaddlv, _vaddlv, 3, (RRe, RRo, RMQ), mve_vaddlv),
25347 mCEF(vaddlva, _vaddlva, 3, (RRe, RRo, RMQ), mve_vaddlv),
25348 mCEF(vaddv, _vaddv, 2, (RRe, RMQ), mve_vaddv),
25349 mCEF(vaddva, _vaddva, 2, (RRe, RMQ), mve_vaddv),
b409bdb6
AV
25350 mCEF(vddup, _vddup, 3, (RMQ, RRe, EXPi), mve_viddup),
25351 mCEF(vdwdup, _vdwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
25352 mCEF(vidup, _vidup, 3, (RMQ, RRe, EXPi), mve_viddup),
25353 mCEF(viwdup, _viwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
935295b5
AV
25354 mToC("vmaxa", ee330e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
25355 mToC("vmina", ee331e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
13ccd4c0
AV
25356 mCEF(vmaxv, _vmaxv, 2, (RR, RMQ), mve_vmaxv),
25357 mCEF(vmaxav, _vmaxav, 2, (RR, RMQ), mve_vmaxv),
25358 mCEF(vminv, _vminv, 2, (RR, RMQ), mve_vmaxv),
25359 mCEF(vminav, _vminav, 2, (RR, RMQ), mve_vmaxv),
57785aa2 25360
93925576
AV
25361 mCEF(vmlaldav, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25362 mCEF(vmlaldava, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25363 mCEF(vmlaldavx, _vmlaldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25364 mCEF(vmlaldavax, _vmlaldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25365 mCEF(vmlalv, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25366 mCEF(vmlalva, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25367 mCEF(vmlsldav, _vmlsldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25368 mCEF(vmlsldava, _vmlsldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25369 mCEF(vmlsldavx, _vmlsldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25370 mCEF(vmlsldavax, _vmlsldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25371 mToC("vrmlaldavh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25372 mToC("vrmlaldavha",ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25373 mCEF(vrmlaldavhx, _vrmlaldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25374 mCEF(vrmlaldavhax, _vrmlaldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25375 mToC("vrmlalvh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25376 mToC("vrmlalvha", ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25377 mCEF(vrmlsldavh, _vrmlsldavh, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25378 mCEF(vrmlsldavha, _vrmlsldavha, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25379 mCEF(vrmlsldavhx, _vrmlsldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25380 mCEF(vrmlsldavhax, _vrmlsldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25381
2d78f95b
AV
25382 mToC("vmlas", ee011e40, 3, (RMQ, RMQ, RR), mve_vmlas),
25383 mToC("vmulh", ee010e01, 3, (RMQ, RMQ, RMQ), mve_vmulh),
25384 mToC("vrmulh", ee011e01, 3, (RMQ, RMQ, RMQ), mve_vmulh),
3063888e
AV
25385 mToC("vpnot", fe310f4d, 0, (), mve_vpnot),
25386 mToC("vpsel", fe310f01, 3, (RMQ, RMQ, RMQ), mve_vpsel),
2d78f95b 25387
8b8b22a4
AV
25388 mToC("vqdmladh", ee000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25389 mToC("vqdmladhx", ee001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25390 mToC("vqrdmladh", ee000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25391 mToC("vqrdmladhx",ee001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25392 mToC("vqdmlsdh", fe000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25393 mToC("vqdmlsdhx", fe001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25394 mToC("vqrdmlsdh", fe000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25395 mToC("vqrdmlsdhx",fe001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
42b16635
AV
25396 mToC("vqdmlah", ee000e60, 3, (RMQ, RMQ, RR), mve_vqdmlah),
25397 mToC("vqdmlash", ee001e60, 3, (RMQ, RMQ, RR), mve_vqdmlah),
25398 mToC("vqrdmlash", ee001e40, 3, (RMQ, RMQ, RR), mve_vqdmlah),
35d1cfc2
AV
25399 mToC("vqdmullt", ee301f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull),
25400 mToC("vqdmullb", ee300f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull),
1be7aba3
AV
25401 mCEF(vqmovnt, _vqmovnt, 2, (RMQ, RMQ), mve_vqmovn),
25402 mCEF(vqmovnb, _vqmovnb, 2, (RMQ, RMQ), mve_vqmovn),
25403 mCEF(vqmovunt, _vqmovunt, 2, (RMQ, RMQ), mve_vqmovn),
25404 mCEF(vqmovunb, _vqmovunb, 2, (RMQ, RMQ), mve_vqmovn),
8b8b22a4 25405
4aa88b50
AV
25406 mCEF(vshrnt, _vshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25407 mCEF(vshrnb, _vshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25408 mCEF(vrshrnt, _vrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25409 mCEF(vrshrnb, _vrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25410 mCEF(vqshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25411 mCEF(vqshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25412 mCEF(vqshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25413 mCEF(vqshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25414 mCEF(vqrshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25415 mCEF(vqrshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25416 mCEF(vqrshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25417 mCEF(vqrshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25418
acca5630
AV
25419 mToC("vshlc", eea00fc0, 3, (RMQ, RR, I32z), mve_vshlc),
25420 mToC("vshllt", ee201e00, 3, (RMQ, RMQ, I32), mve_vshll),
25421 mToC("vshllb", ee200e00, 3, (RMQ, RMQ, I32), mve_vshll),
25422
1f6234a3
AV
25423 toU("dlstp", _dlstp, 2, (LR, RR), t_loloop),
25424 toU("wlstp", _wlstp, 3, (LR, RR, EXP), t_loloop),
25425 toU("letp", _letp, 2, (LR, EXP), t_loloop),
25426 toU("lctp", _lctp, 0, (), t_loloop),
25427
5d281bf0
AV
25428#undef THUMB_VARIANT
25429#define THUMB_VARIANT & mve_fp_ext
25430 mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
f30ee27c 25431 mToC("vfmas", ee311e40, 3, (RMQ, RMQ, RR), mve_vfmas),
935295b5
AV
25432 mToC("vmaxnma", ee3f0e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
25433 mToC("vminnma", ee3f1e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
8cd78170
AV
25434 mToC("vmaxnmv", eeee0f00, 2, (RR, RMQ), mve_vmaxnmv),
25435 mToC("vmaxnmav",eeec0f00, 2, (RR, RMQ), mve_vmaxnmv),
25436 mToC("vminnmv", eeee0f80, 2, (RR, RMQ), mve_vmaxnmv),
25437 mToC("vminnmav",eeec0f80, 2, (RR, RMQ), mve_vmaxnmv),
5d281bf0 25438
5ee91343 25439#undef ARM_VARIANT
57785aa2 25440#define ARM_VARIANT & fpu_vfp_ext_v1
5ee91343
AV
25441#undef THUMB_VARIANT
25442#define THUMB_VARIANT & arm_ext_v6t2
a8465a06
AV
25443 mnCEF(vmla, _vmla, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mac_maybe_scalar),
25444 mnCEF(vmul, _vmul, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mul),
5ee91343 25445
57785aa2
AV
25446 mcCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
25447
25448#undef ARM_VARIANT
25449#define ARM_VARIANT & fpu_vfp_ext_v1xd
25450
25451 MNCE(vmov, 0, 1, (VMOV), neon_mov),
25452 mcCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
25453 mcCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
25454 mcCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
25455
886e1c73
AV
25456 mCEF(vmullt, _vmullt, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ), mve_vmull),
25457 mnCEF(vadd, _vadd, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
25458 mnCEF(vsub, _vsub, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
5ee91343 25459
485dee97
AV
25460 MNCEF(vabs, 1b10300, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
25461 MNCEF(vneg, 1b10380, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
25462
57785aa2
AV
25463 mCEF(vmovlt, _vmovlt, 1, (VMOV), mve_movl),
25464 mCEF(vmovlb, _vmovlb, 1, (VMOV), mve_movl),
25465
1b883319
AV
25466 mnCE(vcmp, _vcmp, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp),
25467 mnCE(vcmpe, _vcmpe, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp),
25468
57785aa2
AV
25469#undef ARM_VARIANT
25470#define ARM_VARIANT & fpu_vfp_ext_v2
25471
25472 mcCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
25473 mcCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
25474 mcCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
25475 mcCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
25476
dd9634d9
AV
25477#undef ARM_VARIANT
25478#define ARM_VARIANT & fpu_vfp_ext_armv8xd
25479 mnUF(vcvta, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvta),
25480 mnUF(vcvtp, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtp),
25481 mnUF(vcvtn, _vcvta, 3, (RNSDQMQ, oRNSDQMQ, oI32z), neon_cvtn),
25482 mnUF(vcvtm, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtm),
935295b5
AV
25483 mnUF(vmaxnm, _vmaxnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
25484 mnUF(vminnm, _vminnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
dd9634d9
AV
25485
25486#undef ARM_VARIANT
5ee91343 25487#define ARM_VARIANT & fpu_neon_ext_v1
f601a00c 25488 mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
5ee91343
AV
25489 mnUF(vabdl, _vabdl, 3, (RNQMQ, RNDMQ, RNDMQ), neon_dyadic_long),
25490 mnUF(vaddl, _vaddl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
25491 mnUF(vsubl, _vsubl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
f601a00c
AV
25492 mnUF(vand, _vand, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
25493 mnUF(vbic, _vbic, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
25494 mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
25495 mnUF(vorn, _vorn, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
25496 mnUF(veor, _veor, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_logic),
f30ee27c
AV
25497 MNUF(vcls, 1b00400, 2, (RNDQMQ, RNDQMQ), neon_cls),
25498 MNUF(vclz, 1b00480, 2, (RNDQMQ, RNDQMQ), neon_clz),
b409bdb6 25499 mnCE(vdup, _vdup, 2, (RNDQMQ, RR_RNSC), neon_dup),
7df54120
AV
25500 MNUF(vhadd, 00000000, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
25501 MNUF(vrhadd, 00000100, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_i_su),
25502 MNUF(vhsub, 00000200, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
935295b5
AV
25503 mnUF(vmin, _vmin, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
25504 mnUF(vmax, _vmax, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
a8465a06
AV
25505 MNUF(vqadd, 0000010, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su),
25506 MNUF(vqsub, 0000210, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su),
1a186d29
AV
25507 mnUF(vmvn, _vmvn, 2, (RNDQMQ, RNDQMQ_Ibig), neon_mvn),
25508 MNUF(vqabs, 1b00700, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg),
25509 MNUF(vqneg, 1b00780, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg),
42b16635
AV
25510 mnUF(vqrdmlah, _vqrdmlah,3, (RNDQMQ, oRNDQMQ, RNDQ_RNSC_RR), neon_qrdmlah),
25511 mnUF(vqdmulh, _vqdmulh, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
25512 mnUF(vqrdmulh, _vqrdmulh,3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
1be7aba3
AV
25513 MNUF(vqrshl, 0000510, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
25514 MNUF(vrshl, 0000500, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
4401c241
AV
25515 MNUF(vshr, 0800010, 3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm),
25516 MNUF(vrshr, 0800210, 3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm),
25517 MNUF(vsli, 1800510, 3, (RNDQMQ, oRNDQMQ, I63), neon_sli),
25518 MNUF(vsri, 1800410, 3, (RNDQMQ, oRNDQMQ, I64z), neon_sri),
25519 MNUF(vrev64, 1b00000, 2, (RNDQMQ, RNDQMQ), neon_rev),
25520 MNUF(vrev32, 1b00080, 2, (RNDQMQ, RNDQMQ), neon_rev),
25521 MNUF(vrev16, 1b00100, 2, (RNDQMQ, RNDQMQ), neon_rev),
5150f0d8
AV
25522 mnUF(vshl, _vshl, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_I63b_RR), neon_shl),
25523 mnUF(vqshl, _vqshl, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_I63b_RR), neon_qshl),
25524 MNUF(vqshlu, 1800610, 3, (RNDQMQ, oRNDQMQ, I63), neon_qshlu_imm),
5d281bf0
AV
25525
25526#undef ARM_VARIANT
25527#define ARM_VARIANT & arm_ext_v8_3
25528#undef THUMB_VARIANT
25529#define THUMB_VARIANT & arm_ext_v6t2_v8m
25530 MNUF (vcadd, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ, EXPi), vcadd),
25531 MNUF (vcmla, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ_RNSC, EXPi), vcmla),
c19d1205
ZW
25532};
25533#undef ARM_VARIANT
25534#undef THUMB_VARIANT
25535#undef TCE
c19d1205
ZW
25536#undef TUE
25537#undef TUF
25538#undef TCC
8f06b2d8 25539#undef cCE
e3cb604e
PB
25540#undef cCL
25541#undef C3E
4389b29a 25542#undef C3
c19d1205
ZW
25543#undef CE
25544#undef CM
4389b29a 25545#undef CL
c19d1205
ZW
25546#undef UE
25547#undef UF
25548#undef UT
5287ad62
JB
25549#undef NUF
25550#undef nUF
25551#undef NCE
25552#undef nCE
c19d1205
ZW
25553#undef OPS0
25554#undef OPS1
25555#undef OPS2
25556#undef OPS3
25557#undef OPS4
25558#undef OPS5
25559#undef OPS6
25560#undef do_0
4389b29a
AV
25561#undef ToC
25562#undef toC
25563#undef ToU
f6b2b12d 25564#undef toU
c19d1205
ZW
25565\f
25566/* MD interface: bits in the object file. */
bfae80f2 25567
c19d1205
ZW
25568/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
25569 for use in the a.out file, and stores them in the array pointed to by buf.
25570 This knows about the endian-ness of the target machine and does
25571 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
25572 2 (short) and 4 (long) Floating numbers are put out as a series of
25573 LITTLENUMS (shorts, here at least). */
b99bd4ef 25574
c19d1205
ZW
25575void
25576md_number_to_chars (char * buf, valueT val, int n)
25577{
25578 if (target_big_endian)
25579 number_to_chars_bigendian (buf, val, n);
25580 else
25581 number_to_chars_littleendian (buf, val, n);
bfae80f2
RE
25582}
25583
c19d1205
ZW
25584static valueT
25585md_chars_to_number (char * buf, int n)
bfae80f2 25586{
c19d1205
ZW
25587 valueT result = 0;
25588 unsigned char * where = (unsigned char *) buf;
bfae80f2 25589
c19d1205 25590 if (target_big_endian)
b99bd4ef 25591 {
c19d1205
ZW
25592 while (n--)
25593 {
25594 result <<= 8;
25595 result |= (*where++ & 255);
25596 }
b99bd4ef 25597 }
c19d1205 25598 else
b99bd4ef 25599 {
c19d1205
ZW
25600 while (n--)
25601 {
25602 result <<= 8;
25603 result |= (where[n] & 255);
25604 }
bfae80f2 25605 }
b99bd4ef 25606
c19d1205 25607 return result;
bfae80f2 25608}
b99bd4ef 25609
c19d1205 25610/* MD interface: Sections. */
b99bd4ef 25611
fa94de6b
RM
25612/* Calculate the maximum variable size (i.e., excluding fr_fix)
25613 that an rs_machine_dependent frag may reach. */
25614
25615unsigned int
25616arm_frag_max_var (fragS *fragp)
25617{
25618 /* We only use rs_machine_dependent for variable-size Thumb instructions,
25619 which are either THUMB_SIZE (2) or INSN_SIZE (4).
25620
25621 Note that we generate relaxable instructions even for cases that don't
25622 really need it, like an immediate that's a trivial constant. So we're
25623 overestimating the instruction size for some of those cases. Rather
25624 than putting more intelligence here, it would probably be better to
25625 avoid generating a relaxation frag in the first place when it can be
25626 determined up front that a short instruction will suffice. */
25627
25628 gas_assert (fragp->fr_type == rs_machine_dependent);
25629 return INSN_SIZE;
25630}
25631
0110f2b8
PB
25632/* Estimate the size of a frag before relaxing. Assume everything fits in
25633 2 bytes. */
25634
c19d1205 25635int
0110f2b8 25636md_estimate_size_before_relax (fragS * fragp,
c19d1205
ZW
25637 segT segtype ATTRIBUTE_UNUSED)
25638{
0110f2b8
PB
25639 fragp->fr_var = 2;
25640 return 2;
25641}
25642
25643/* Convert a machine dependent frag. */
25644
25645void
25646md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
25647{
25648 unsigned long insn;
25649 unsigned long old_op;
25650 char *buf;
25651 expressionS exp;
25652 fixS *fixp;
25653 int reloc_type;
25654 int pc_rel;
25655 int opcode;
25656
25657 buf = fragp->fr_literal + fragp->fr_fix;
25658
25659 old_op = bfd_get_16(abfd, buf);
5f4273c7
NC
25660 if (fragp->fr_symbol)
25661 {
0110f2b8
PB
25662 exp.X_op = O_symbol;
25663 exp.X_add_symbol = fragp->fr_symbol;
5f4273c7
NC
25664 }
25665 else
25666 {
0110f2b8 25667 exp.X_op = O_constant;
5f4273c7 25668 }
0110f2b8
PB
25669 exp.X_add_number = fragp->fr_offset;
25670 opcode = fragp->fr_subtype;
25671 switch (opcode)
25672 {
25673 case T_MNEM_ldr_pc:
25674 case T_MNEM_ldr_pc2:
25675 case T_MNEM_ldr_sp:
25676 case T_MNEM_str_sp:
25677 case T_MNEM_ldr:
25678 case T_MNEM_ldrb:
25679 case T_MNEM_ldrh:
25680 case T_MNEM_str:
25681 case T_MNEM_strb:
25682 case T_MNEM_strh:
25683 if (fragp->fr_var == 4)
25684 {
5f4273c7 25685 insn = THUMB_OP32 (opcode);
0110f2b8
PB
25686 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
25687 {
25688 insn |= (old_op & 0x700) << 4;
25689 }
25690 else
25691 {
25692 insn |= (old_op & 7) << 12;
25693 insn |= (old_op & 0x38) << 13;
25694 }
25695 insn |= 0x00000c00;
25696 put_thumb32_insn (buf, insn);
25697 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
25698 }
25699 else
25700 {
25701 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
25702 }
25703 pc_rel = (opcode == T_MNEM_ldr_pc2);
25704 break;
25705 case T_MNEM_adr:
25706 if (fragp->fr_var == 4)
25707 {
25708 insn = THUMB_OP32 (opcode);
25709 insn |= (old_op & 0xf0) << 4;
25710 put_thumb32_insn (buf, insn);
25711 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
25712 }
25713 else
25714 {
25715 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
25716 exp.X_add_number -= 4;
25717 }
25718 pc_rel = 1;
25719 break;
25720 case T_MNEM_mov:
25721 case T_MNEM_movs:
25722 case T_MNEM_cmp:
25723 case T_MNEM_cmn:
25724 if (fragp->fr_var == 4)
25725 {
25726 int r0off = (opcode == T_MNEM_mov
25727 || opcode == T_MNEM_movs) ? 0 : 8;
25728 insn = THUMB_OP32 (opcode);
25729 insn = (insn & 0xe1ffffff) | 0x10000000;
25730 insn |= (old_op & 0x700) << r0off;
25731 put_thumb32_insn (buf, insn);
25732 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
25733 }
25734 else
25735 {
25736 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
25737 }
25738 pc_rel = 0;
25739 break;
25740 case T_MNEM_b:
25741 if (fragp->fr_var == 4)
25742 {
25743 insn = THUMB_OP32(opcode);
25744 put_thumb32_insn (buf, insn);
25745 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
25746 }
25747 else
25748 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
25749 pc_rel = 1;
25750 break;
25751 case T_MNEM_bcond:
25752 if (fragp->fr_var == 4)
25753 {
25754 insn = THUMB_OP32(opcode);
25755 insn |= (old_op & 0xf00) << 14;
25756 put_thumb32_insn (buf, insn);
25757 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
25758 }
25759 else
25760 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
25761 pc_rel = 1;
25762 break;
25763 case T_MNEM_add_sp:
25764 case T_MNEM_add_pc:
25765 case T_MNEM_inc_sp:
25766 case T_MNEM_dec_sp:
25767 if (fragp->fr_var == 4)
25768 {
25769 /* ??? Choose between add and addw. */
25770 insn = THUMB_OP32 (opcode);
25771 insn |= (old_op & 0xf0) << 4;
25772 put_thumb32_insn (buf, insn);
16805f35
PB
25773 if (opcode == T_MNEM_add_pc)
25774 reloc_type = BFD_RELOC_ARM_T32_IMM12;
25775 else
25776 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
0110f2b8
PB
25777 }
25778 else
25779 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
25780 pc_rel = 0;
25781 break;
25782
25783 case T_MNEM_addi:
25784 case T_MNEM_addis:
25785 case T_MNEM_subi:
25786 case T_MNEM_subis:
25787 if (fragp->fr_var == 4)
25788 {
25789 insn = THUMB_OP32 (opcode);
25790 insn |= (old_op & 0xf0) << 4;
25791 insn |= (old_op & 0xf) << 16;
25792 put_thumb32_insn (buf, insn);
16805f35
PB
25793 if (insn & (1 << 20))
25794 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
25795 else
25796 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
0110f2b8
PB
25797 }
25798 else
25799 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
25800 pc_rel = 0;
25801 break;
25802 default:
5f4273c7 25803 abort ();
0110f2b8
PB
25804 }
25805 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
21d799b5 25806 (enum bfd_reloc_code_real) reloc_type);
0110f2b8
PB
25807 fixp->fx_file = fragp->fr_file;
25808 fixp->fx_line = fragp->fr_line;
25809 fragp->fr_fix += fragp->fr_var;
3cfdb781
TG
25810
25811 /* Set whether we use thumb-2 ISA based on final relaxation results. */
25812 if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected ()
25813 && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2))
25814 ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2);
0110f2b8
PB
25815}
25816
25817/* Return the size of a relaxable immediate operand instruction.
25818 SHIFT and SIZE specify the form of the allowable immediate. */
25819static int
25820relax_immediate (fragS *fragp, int size, int shift)
25821{
25822 offsetT offset;
25823 offsetT mask;
25824 offsetT low;
25825
25826 /* ??? Should be able to do better than this. */
25827 if (fragp->fr_symbol)
25828 return 4;
25829
25830 low = (1 << shift) - 1;
25831 mask = (1 << (shift + size)) - (1 << shift);
25832 offset = fragp->fr_offset;
25833 /* Force misaligned offsets to 32-bit variant. */
25834 if (offset & low)
5e77afaa 25835 return 4;
0110f2b8
PB
25836 if (offset & ~mask)
25837 return 4;
25838 return 2;
25839}
25840
5e77afaa
PB
25841/* Get the address of a symbol during relaxation. */
25842static addressT
5f4273c7 25843relaxed_symbol_addr (fragS *fragp, long stretch)
5e77afaa
PB
25844{
25845 fragS *sym_frag;
25846 addressT addr;
25847 symbolS *sym;
25848
25849 sym = fragp->fr_symbol;
25850 sym_frag = symbol_get_frag (sym);
25851 know (S_GET_SEGMENT (sym) != absolute_section
25852 || sym_frag == &zero_address_frag);
25853 addr = S_GET_VALUE (sym) + fragp->fr_offset;
25854
25855 /* If frag has yet to be reached on this pass, assume it will
25856 move by STRETCH just as we did. If this is not so, it will
25857 be because some frag between grows, and that will force
25858 another pass. */
25859
25860 if (stretch != 0
25861 && sym_frag->relax_marker != fragp->relax_marker)
4396b686
PB
25862 {
25863 fragS *f;
25864
25865 /* Adjust stretch for any alignment frag. Note that if have
25866 been expanding the earlier code, the symbol may be
25867 defined in what appears to be an earlier frag. FIXME:
25868 This doesn't handle the fr_subtype field, which specifies
25869 a maximum number of bytes to skip when doing an
25870 alignment. */
25871 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
25872 {
25873 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
25874 {
25875 if (stretch < 0)
25876 stretch = - ((- stretch)
25877 & ~ ((1 << (int) f->fr_offset) - 1));
25878 else
25879 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
25880 if (stretch == 0)
25881 break;
25882 }
25883 }
25884 if (f != NULL)
25885 addr += stretch;
25886 }
5e77afaa
PB
25887
25888 return addr;
25889}
25890
0110f2b8
PB
25891/* Return the size of a relaxable adr pseudo-instruction or PC-relative
25892 load. */
25893static int
5e77afaa 25894relax_adr (fragS *fragp, asection *sec, long stretch)
0110f2b8
PB
25895{
25896 addressT addr;
25897 offsetT val;
25898
25899 /* Assume worst case for symbols not known to be in the same section. */
974da60d
NC
25900 if (fragp->fr_symbol == NULL
25901 || !S_IS_DEFINED (fragp->fr_symbol)
77db8e2e
NC
25902 || sec != S_GET_SEGMENT (fragp->fr_symbol)
25903 || S_IS_WEAK (fragp->fr_symbol))
0110f2b8
PB
25904 return 4;
25905
5f4273c7 25906 val = relaxed_symbol_addr (fragp, stretch);
0110f2b8
PB
25907 addr = fragp->fr_address + fragp->fr_fix;
25908 addr = (addr + 4) & ~3;
5e77afaa 25909 /* Force misaligned targets to 32-bit variant. */
0110f2b8 25910 if (val & 3)
5e77afaa 25911 return 4;
0110f2b8
PB
25912 val -= addr;
25913 if (val < 0 || val > 1020)
25914 return 4;
25915 return 2;
25916}
25917
25918/* Return the size of a relaxable add/sub immediate instruction. */
25919static int
25920relax_addsub (fragS *fragp, asection *sec)
25921{
25922 char *buf;
25923 int op;
25924
25925 buf = fragp->fr_literal + fragp->fr_fix;
25926 op = bfd_get_16(sec->owner, buf);
25927 if ((op & 0xf) == ((op >> 4) & 0xf))
25928 return relax_immediate (fragp, 8, 0);
25929 else
25930 return relax_immediate (fragp, 3, 0);
25931}
25932
e83a675f
RE
25933/* Return TRUE iff the definition of symbol S could be pre-empted
25934 (overridden) at link or load time. */
25935static bfd_boolean
25936symbol_preemptible (symbolS *s)
25937{
25938 /* Weak symbols can always be pre-empted. */
25939 if (S_IS_WEAK (s))
25940 return TRUE;
25941
25942 /* Non-global symbols cannot be pre-empted. */
25943 if (! S_IS_EXTERNAL (s))
25944 return FALSE;
25945
25946#ifdef OBJ_ELF
25947 /* In ELF, a global symbol can be marked protected, or private. In that
25948 case it can't be pre-empted (other definitions in the same link unit
25949 would violate the ODR). */
25950 if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
25951 return FALSE;
25952#endif
25953
25954 /* Other global symbols might be pre-empted. */
25955 return TRUE;
25956}
0110f2b8
PB
25957
25958/* Return the size of a relaxable branch instruction. BITS is the
25959 size of the offset field in the narrow instruction. */
25960
25961static int
5e77afaa 25962relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
0110f2b8
PB
25963{
25964 addressT addr;
25965 offsetT val;
25966 offsetT limit;
25967
25968 /* Assume worst case for symbols not known to be in the same section. */
5f4273c7 25969 if (!S_IS_DEFINED (fragp->fr_symbol)
77db8e2e
NC
25970 || sec != S_GET_SEGMENT (fragp->fr_symbol)
25971 || S_IS_WEAK (fragp->fr_symbol))
0110f2b8
PB
25972 return 4;
25973
267bf995 25974#ifdef OBJ_ELF
e83a675f 25975 /* A branch to a function in ARM state will require interworking. */
267bf995
RR
25976 if (S_IS_DEFINED (fragp->fr_symbol)
25977 && ARM_IS_FUNC (fragp->fr_symbol))
25978 return 4;
e83a675f 25979#endif
0d9b4b55 25980
e83a675f 25981 if (symbol_preemptible (fragp->fr_symbol))
0d9b4b55 25982 return 4;
267bf995 25983
5f4273c7 25984 val = relaxed_symbol_addr (fragp, stretch);
0110f2b8
PB
25985 addr = fragp->fr_address + fragp->fr_fix + 4;
25986 val -= addr;
25987
25988 /* Offset is a signed value *2 */
25989 limit = 1 << bits;
25990 if (val >= limit || val < -limit)
25991 return 4;
25992 return 2;
25993}
25994
25995
25996/* Relax a machine dependent frag. This returns the amount by which
25997 the current size of the frag should change. */
25998
25999int
5e77afaa 26000arm_relax_frag (asection *sec, fragS *fragp, long stretch)
0110f2b8
PB
26001{
26002 int oldsize;
26003 int newsize;
26004
26005 oldsize = fragp->fr_var;
26006 switch (fragp->fr_subtype)
26007 {
26008 case T_MNEM_ldr_pc2:
5f4273c7 26009 newsize = relax_adr (fragp, sec, stretch);
0110f2b8
PB
26010 break;
26011 case T_MNEM_ldr_pc:
26012 case T_MNEM_ldr_sp:
26013 case T_MNEM_str_sp:
5f4273c7 26014 newsize = relax_immediate (fragp, 8, 2);
0110f2b8
PB
26015 break;
26016 case T_MNEM_ldr:
26017 case T_MNEM_str:
5f4273c7 26018 newsize = relax_immediate (fragp, 5, 2);
0110f2b8
PB
26019 break;
26020 case T_MNEM_ldrh:
26021 case T_MNEM_strh:
5f4273c7 26022 newsize = relax_immediate (fragp, 5, 1);
0110f2b8
PB
26023 break;
26024 case T_MNEM_ldrb:
26025 case T_MNEM_strb:
5f4273c7 26026 newsize = relax_immediate (fragp, 5, 0);
0110f2b8
PB
26027 break;
26028 case T_MNEM_adr:
5f4273c7 26029 newsize = relax_adr (fragp, sec, stretch);
0110f2b8
PB
26030 break;
26031 case T_MNEM_mov:
26032 case T_MNEM_movs:
26033 case T_MNEM_cmp:
26034 case T_MNEM_cmn:
5f4273c7 26035 newsize = relax_immediate (fragp, 8, 0);
0110f2b8
PB
26036 break;
26037 case T_MNEM_b:
5f4273c7 26038 newsize = relax_branch (fragp, sec, 11, stretch);
0110f2b8
PB
26039 break;
26040 case T_MNEM_bcond:
5f4273c7 26041 newsize = relax_branch (fragp, sec, 8, stretch);
0110f2b8
PB
26042 break;
26043 case T_MNEM_add_sp:
26044 case T_MNEM_add_pc:
26045 newsize = relax_immediate (fragp, 8, 2);
26046 break;
26047 case T_MNEM_inc_sp:
26048 case T_MNEM_dec_sp:
26049 newsize = relax_immediate (fragp, 7, 2);
26050 break;
26051 case T_MNEM_addi:
26052 case T_MNEM_addis:
26053 case T_MNEM_subi:
26054 case T_MNEM_subis:
26055 newsize = relax_addsub (fragp, sec);
26056 break;
26057 default:
5f4273c7 26058 abort ();
0110f2b8 26059 }
5e77afaa
PB
26060
26061 fragp->fr_var = newsize;
26062 /* Freeze wide instructions that are at or before the same location as
26063 in the previous pass. This avoids infinite loops.
5f4273c7
NC
26064 Don't freeze them unconditionally because targets may be artificially
26065 misaligned by the expansion of preceding frags. */
5e77afaa 26066 if (stretch <= 0 && newsize > 2)
0110f2b8 26067 {
0110f2b8 26068 md_convert_frag (sec->owner, sec, fragp);
5f4273c7 26069 frag_wane (fragp);
0110f2b8 26070 }
5e77afaa 26071
0110f2b8 26072 return newsize - oldsize;
c19d1205 26073}
b99bd4ef 26074
c19d1205 26075/* Round up a section size to the appropriate boundary. */
b99bd4ef 26076
c19d1205
ZW
26077valueT
26078md_section_align (segT segment ATTRIBUTE_UNUSED,
26079 valueT size)
26080{
6844c0cc 26081 return size;
bfae80f2 26082}
b99bd4ef 26083
c19d1205
ZW
26084/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
26085 of an rs_align_code fragment. */
26086
26087void
26088arm_handle_align (fragS * fragP)
bfae80f2 26089{
d9235011 26090 static unsigned char const arm_noop[2][2][4] =
e7495e45
NS
26091 {
26092 { /* ARMv1 */
26093 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
26094 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
26095 },
26096 { /* ARMv6k */
26097 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
26098 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
26099 },
26100 };
d9235011 26101 static unsigned char const thumb_noop[2][2][2] =
e7495e45
NS
26102 {
26103 { /* Thumb-1 */
26104 {0xc0, 0x46}, /* LE */
26105 {0x46, 0xc0}, /* BE */
26106 },
26107 { /* Thumb-2 */
26108 {0x00, 0xbf}, /* LE */
26109 {0xbf, 0x00} /* BE */
26110 }
26111 };
d9235011 26112 static unsigned char const wide_thumb_noop[2][4] =
e7495e45
NS
26113 { /* Wide Thumb-2 */
26114 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
26115 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
26116 };
c921be7d 26117
e7495e45 26118 unsigned bytes, fix, noop_size;
c19d1205 26119 char * p;
d9235011
TS
26120 const unsigned char * noop;
26121 const unsigned char *narrow_noop = NULL;
cd000bff
DJ
26122#ifdef OBJ_ELF
26123 enum mstate state;
26124#endif
bfae80f2 26125
c19d1205 26126 if (fragP->fr_type != rs_align_code)
bfae80f2
RE
26127 return;
26128
c19d1205
ZW
26129 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
26130 p = fragP->fr_literal + fragP->fr_fix;
26131 fix = 0;
bfae80f2 26132
c19d1205
ZW
26133 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
26134 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
bfae80f2 26135
cd000bff 26136 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
8dc2430f 26137
cd000bff 26138 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
a737bd4d 26139 {
7f78eb34
JW
26140 if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
26141 ? selected_cpu : arm_arch_none, arm_ext_v6t2))
e7495e45
NS
26142 {
26143 narrow_noop = thumb_noop[1][target_big_endian];
26144 noop = wide_thumb_noop[target_big_endian];
26145 }
c19d1205 26146 else
e7495e45
NS
26147 noop = thumb_noop[0][target_big_endian];
26148 noop_size = 2;
cd000bff
DJ
26149#ifdef OBJ_ELF
26150 state = MAP_THUMB;
26151#endif
7ed4c4c5
NC
26152 }
26153 else
26154 {
7f78eb34
JW
26155 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
26156 ? selected_cpu : arm_arch_none,
26157 arm_ext_v6k) != 0]
e7495e45
NS
26158 [target_big_endian];
26159 noop_size = 4;
cd000bff
DJ
26160#ifdef OBJ_ELF
26161 state = MAP_ARM;
26162#endif
7ed4c4c5 26163 }
c921be7d 26164
e7495e45 26165 fragP->fr_var = noop_size;
c921be7d 26166
c19d1205 26167 if (bytes & (noop_size - 1))
7ed4c4c5 26168 {
c19d1205 26169 fix = bytes & (noop_size - 1);
cd000bff
DJ
26170#ifdef OBJ_ELF
26171 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
26172#endif
c19d1205
ZW
26173 memset (p, 0, fix);
26174 p += fix;
26175 bytes -= fix;
a737bd4d 26176 }
a737bd4d 26177
e7495e45
NS
26178 if (narrow_noop)
26179 {
26180 if (bytes & noop_size)
26181 {
26182 /* Insert a narrow noop. */
26183 memcpy (p, narrow_noop, noop_size);
26184 p += noop_size;
26185 bytes -= noop_size;
26186 fix += noop_size;
26187 }
26188
26189 /* Use wide noops for the remainder */
26190 noop_size = 4;
26191 }
26192
c19d1205 26193 while (bytes >= noop_size)
a737bd4d 26194 {
c19d1205
ZW
26195 memcpy (p, noop, noop_size);
26196 p += noop_size;
26197 bytes -= noop_size;
26198 fix += noop_size;
a737bd4d
NC
26199 }
26200
c19d1205 26201 fragP->fr_fix += fix;
a737bd4d
NC
26202}
26203
c19d1205
ZW
26204/* Called from md_do_align. Used to create an alignment
26205 frag in a code section. */
26206
26207void
26208arm_frag_align_code (int n, int max)
bfae80f2 26209{
c19d1205 26210 char * p;
7ed4c4c5 26211
c19d1205 26212 /* We assume that there will never be a requirement
6ec8e702 26213 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
c19d1205 26214 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
6ec8e702
NC
26215 {
26216 char err_msg[128];
26217
fa94de6b 26218 sprintf (err_msg,
477330fc
RM
26219 _("alignments greater than %d bytes not supported in .text sections."),
26220 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
20203fb9 26221 as_fatal ("%s", err_msg);
6ec8e702 26222 }
bfae80f2 26223
c19d1205
ZW
26224 p = frag_var (rs_align_code,
26225 MAX_MEM_FOR_RS_ALIGN_CODE,
26226 1,
26227 (relax_substateT) max,
26228 (symbolS *) NULL,
26229 (offsetT) n,
26230 (char *) NULL);
26231 *p = 0;
26232}
bfae80f2 26233
8dc2430f
NC
26234/* Perform target specific initialisation of a frag.
26235 Note - despite the name this initialisation is not done when the frag
26236 is created, but only when its type is assigned. A frag can be created
26237 and used a long time before its type is set, so beware of assuming that
33eaf5de 26238 this initialisation is performed first. */
bfae80f2 26239
cd000bff
DJ
26240#ifndef OBJ_ELF
26241void
26242arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
26243{
26244 /* Record whether this frag is in an ARM or a THUMB area. */
2e98972e 26245 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
cd000bff
DJ
26246}
26247
26248#else /* OBJ_ELF is defined. */
c19d1205 26249void
cd000bff 26250arm_init_frag (fragS * fragP, int max_chars)
c19d1205 26251{
e8d84ca1 26252 bfd_boolean frag_thumb_mode;
b968d18a 26253
8dc2430f
NC
26254 /* If the current ARM vs THUMB mode has not already
26255 been recorded into this frag then do so now. */
cd000bff 26256 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
b968d18a
JW
26257 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
26258
e8d84ca1
NC
26259 /* PR 21809: Do not set a mapping state for debug sections
26260 - it just confuses other tools. */
26261 if (bfd_get_section_flags (NULL, now_seg) & SEC_DEBUGGING)
26262 return;
26263
b968d18a 26264 frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED;
cd000bff 26265
f9c1b181
RL
26266 /* Record a mapping symbol for alignment frags. We will delete this
26267 later if the alignment ends up empty. */
26268 switch (fragP->fr_type)
26269 {
26270 case rs_align:
26271 case rs_align_test:
26272 case rs_fill:
26273 mapping_state_2 (MAP_DATA, max_chars);
26274 break;
26275 case rs_align_code:
b968d18a 26276 mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
f9c1b181
RL
26277 break;
26278 default:
26279 break;
cd000bff 26280 }
bfae80f2
RE
26281}
26282
c19d1205
ZW
26283/* When we change sections we need to issue a new mapping symbol. */
26284
26285void
26286arm_elf_change_section (void)
bfae80f2 26287{
c19d1205
ZW
26288 /* Link an unlinked unwind index table section to the .text section. */
26289 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
26290 && elf_linked_to_section (now_seg) == NULL)
26291 elf_linked_to_section (now_seg) = text_section;
bfae80f2
RE
26292}
26293
c19d1205
ZW
26294int
26295arm_elf_section_type (const char * str, size_t len)
e45d0630 26296{
c19d1205
ZW
26297 if (len == 5 && strncmp (str, "exidx", 5) == 0)
26298 return SHT_ARM_EXIDX;
e45d0630 26299
c19d1205
ZW
26300 return -1;
26301}
26302\f
26303/* Code to deal with unwinding tables. */
e45d0630 26304
c19d1205 26305static void add_unwind_adjustsp (offsetT);
e45d0630 26306
5f4273c7 26307/* Generate any deferred unwind frame offset. */
e45d0630 26308
bfae80f2 26309static void
c19d1205 26310flush_pending_unwind (void)
bfae80f2 26311{
c19d1205 26312 offsetT offset;
bfae80f2 26313
c19d1205
ZW
26314 offset = unwind.pending_offset;
26315 unwind.pending_offset = 0;
26316 if (offset != 0)
26317 add_unwind_adjustsp (offset);
bfae80f2
RE
26318}
26319
c19d1205
ZW
26320/* Add an opcode to this list for this function. Two-byte opcodes should
26321 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
26322 order. */
26323
bfae80f2 26324static void
c19d1205 26325add_unwind_opcode (valueT op, int length)
bfae80f2 26326{
c19d1205
ZW
26327 /* Add any deferred stack adjustment. */
26328 if (unwind.pending_offset)
26329 flush_pending_unwind ();
bfae80f2 26330
c19d1205 26331 unwind.sp_restored = 0;
bfae80f2 26332
c19d1205 26333 if (unwind.opcode_count + length > unwind.opcode_alloc)
bfae80f2 26334 {
c19d1205
ZW
26335 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
26336 if (unwind.opcodes)
325801bd
TS
26337 unwind.opcodes = XRESIZEVEC (unsigned char, unwind.opcodes,
26338 unwind.opcode_alloc);
c19d1205 26339 else
325801bd 26340 unwind.opcodes = XNEWVEC (unsigned char, unwind.opcode_alloc);
bfae80f2 26341 }
c19d1205 26342 while (length > 0)
bfae80f2 26343 {
c19d1205
ZW
26344 length--;
26345 unwind.opcodes[unwind.opcode_count] = op & 0xff;
26346 op >>= 8;
26347 unwind.opcode_count++;
bfae80f2 26348 }
bfae80f2
RE
26349}
26350
c19d1205
ZW
26351/* Add unwind opcodes to adjust the stack pointer. */
26352
bfae80f2 26353static void
c19d1205 26354add_unwind_adjustsp (offsetT offset)
bfae80f2 26355{
c19d1205 26356 valueT op;
bfae80f2 26357
c19d1205 26358 if (offset > 0x200)
bfae80f2 26359 {
c19d1205
ZW
26360 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
26361 char bytes[5];
26362 int n;
26363 valueT o;
bfae80f2 26364
c19d1205
ZW
26365 /* Long form: 0xb2, uleb128. */
26366 /* This might not fit in a word so add the individual bytes,
26367 remembering the list is built in reverse order. */
26368 o = (valueT) ((offset - 0x204) >> 2);
26369 if (o == 0)
26370 add_unwind_opcode (0, 1);
bfae80f2 26371
c19d1205
ZW
26372 /* Calculate the uleb128 encoding of the offset. */
26373 n = 0;
26374 while (o)
26375 {
26376 bytes[n] = o & 0x7f;
26377 o >>= 7;
26378 if (o)
26379 bytes[n] |= 0x80;
26380 n++;
26381 }
26382 /* Add the insn. */
26383 for (; n; n--)
26384 add_unwind_opcode (bytes[n - 1], 1);
26385 add_unwind_opcode (0xb2, 1);
26386 }
26387 else if (offset > 0x100)
bfae80f2 26388 {
c19d1205
ZW
26389 /* Two short opcodes. */
26390 add_unwind_opcode (0x3f, 1);
26391 op = (offset - 0x104) >> 2;
26392 add_unwind_opcode (op, 1);
bfae80f2 26393 }
c19d1205
ZW
26394 else if (offset > 0)
26395 {
26396 /* Short opcode. */
26397 op = (offset - 4) >> 2;
26398 add_unwind_opcode (op, 1);
26399 }
26400 else if (offset < 0)
bfae80f2 26401 {
c19d1205
ZW
26402 offset = -offset;
26403 while (offset > 0x100)
bfae80f2 26404 {
c19d1205
ZW
26405 add_unwind_opcode (0x7f, 1);
26406 offset -= 0x100;
bfae80f2 26407 }
c19d1205
ZW
26408 op = ((offset - 4) >> 2) | 0x40;
26409 add_unwind_opcode (op, 1);
bfae80f2 26410 }
bfae80f2
RE
26411}
26412
c19d1205 26413/* Finish the list of unwind opcodes for this function. */
0198d5e6 26414
c19d1205
ZW
26415static void
26416finish_unwind_opcodes (void)
bfae80f2 26417{
c19d1205 26418 valueT op;
bfae80f2 26419
c19d1205 26420 if (unwind.fp_used)
bfae80f2 26421 {
708587a4 26422 /* Adjust sp as necessary. */
c19d1205
ZW
26423 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
26424 flush_pending_unwind ();
bfae80f2 26425
c19d1205
ZW
26426 /* After restoring sp from the frame pointer. */
26427 op = 0x90 | unwind.fp_reg;
26428 add_unwind_opcode (op, 1);
26429 }
26430 else
26431 flush_pending_unwind ();
bfae80f2
RE
26432}
26433
bfae80f2 26434
c19d1205
ZW
26435/* Start an exception table entry. If idx is nonzero this is an index table
26436 entry. */
bfae80f2
RE
26437
26438static void
c19d1205 26439start_unwind_section (const segT text_seg, int idx)
bfae80f2 26440{
c19d1205
ZW
26441 const char * text_name;
26442 const char * prefix;
26443 const char * prefix_once;
26444 const char * group_name;
c19d1205 26445 char * sec_name;
c19d1205
ZW
26446 int type;
26447 int flags;
26448 int linkonce;
bfae80f2 26449
c19d1205 26450 if (idx)
bfae80f2 26451 {
c19d1205
ZW
26452 prefix = ELF_STRING_ARM_unwind;
26453 prefix_once = ELF_STRING_ARM_unwind_once;
26454 type = SHT_ARM_EXIDX;
bfae80f2 26455 }
c19d1205 26456 else
bfae80f2 26457 {
c19d1205
ZW
26458 prefix = ELF_STRING_ARM_unwind_info;
26459 prefix_once = ELF_STRING_ARM_unwind_info_once;
26460 type = SHT_PROGBITS;
bfae80f2
RE
26461 }
26462
c19d1205
ZW
26463 text_name = segment_name (text_seg);
26464 if (streq (text_name, ".text"))
26465 text_name = "";
26466
26467 if (strncmp (text_name, ".gnu.linkonce.t.",
26468 strlen (".gnu.linkonce.t.")) == 0)
bfae80f2 26469 {
c19d1205
ZW
26470 prefix = prefix_once;
26471 text_name += strlen (".gnu.linkonce.t.");
bfae80f2
RE
26472 }
26473
29a2809e 26474 sec_name = concat (prefix, text_name, (char *) NULL);
bfae80f2 26475
c19d1205
ZW
26476 flags = SHF_ALLOC;
26477 linkonce = 0;
26478 group_name = 0;
bfae80f2 26479
c19d1205
ZW
26480 /* Handle COMDAT group. */
26481 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
bfae80f2 26482 {
c19d1205
ZW
26483 group_name = elf_group_name (text_seg);
26484 if (group_name == NULL)
26485 {
bd3ba5d1 26486 as_bad (_("Group section `%s' has no group signature"),
c19d1205
ZW
26487 segment_name (text_seg));
26488 ignore_rest_of_line ();
26489 return;
26490 }
26491 flags |= SHF_GROUP;
26492 linkonce = 1;
bfae80f2
RE
26493 }
26494
a91e1603
L
26495 obj_elf_change_section (sec_name, type, 0, flags, 0, group_name,
26496 linkonce, 0);
bfae80f2 26497
5f4273c7 26498 /* Set the section link for index tables. */
c19d1205
ZW
26499 if (idx)
26500 elf_linked_to_section (now_seg) = text_seg;
bfae80f2
RE
26501}
26502
bfae80f2 26503
c19d1205
ZW
26504/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
26505 personality routine data. Returns zero, or the index table value for
cad0da33 26506 an inline entry. */
c19d1205
ZW
26507
26508static valueT
26509create_unwind_entry (int have_data)
bfae80f2 26510{
c19d1205
ZW
26511 int size;
26512 addressT where;
26513 char *ptr;
26514 /* The current word of data. */
26515 valueT data;
26516 /* The number of bytes left in this word. */
26517 int n;
bfae80f2 26518
c19d1205 26519 finish_unwind_opcodes ();
bfae80f2 26520
c19d1205
ZW
26521 /* Remember the current text section. */
26522 unwind.saved_seg = now_seg;
26523 unwind.saved_subseg = now_subseg;
bfae80f2 26524
c19d1205 26525 start_unwind_section (now_seg, 0);
bfae80f2 26526
c19d1205 26527 if (unwind.personality_routine == NULL)
bfae80f2 26528 {
c19d1205
ZW
26529 if (unwind.personality_index == -2)
26530 {
26531 if (have_data)
5f4273c7 26532 as_bad (_("handlerdata in cantunwind frame"));
c19d1205
ZW
26533 return 1; /* EXIDX_CANTUNWIND. */
26534 }
bfae80f2 26535
c19d1205
ZW
26536 /* Use a default personality routine if none is specified. */
26537 if (unwind.personality_index == -1)
26538 {
26539 if (unwind.opcode_count > 3)
26540 unwind.personality_index = 1;
26541 else
26542 unwind.personality_index = 0;
26543 }
bfae80f2 26544
c19d1205
ZW
26545 /* Space for the personality routine entry. */
26546 if (unwind.personality_index == 0)
26547 {
26548 if (unwind.opcode_count > 3)
26549 as_bad (_("too many unwind opcodes for personality routine 0"));
bfae80f2 26550
c19d1205
ZW
26551 if (!have_data)
26552 {
26553 /* All the data is inline in the index table. */
26554 data = 0x80;
26555 n = 3;
26556 while (unwind.opcode_count > 0)
26557 {
26558 unwind.opcode_count--;
26559 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
26560 n--;
26561 }
bfae80f2 26562
c19d1205
ZW
26563 /* Pad with "finish" opcodes. */
26564 while (n--)
26565 data = (data << 8) | 0xb0;
bfae80f2 26566
c19d1205
ZW
26567 return data;
26568 }
26569 size = 0;
26570 }
26571 else
26572 /* We get two opcodes "free" in the first word. */
26573 size = unwind.opcode_count - 2;
26574 }
26575 else
5011093d 26576 {
cad0da33
NC
26577 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
26578 if (unwind.personality_index != -1)
26579 {
26580 as_bad (_("attempt to recreate an unwind entry"));
26581 return 1;
26582 }
5011093d
NC
26583
26584 /* An extra byte is required for the opcode count. */
26585 size = unwind.opcode_count + 1;
26586 }
bfae80f2 26587
c19d1205
ZW
26588 size = (size + 3) >> 2;
26589 if (size > 0xff)
26590 as_bad (_("too many unwind opcodes"));
bfae80f2 26591
c19d1205
ZW
26592 frag_align (2, 0, 0);
26593 record_alignment (now_seg, 2);
26594 unwind.table_entry = expr_build_dot ();
26595
26596 /* Allocate the table entry. */
26597 ptr = frag_more ((size << 2) + 4);
74929e7b
NC
26598 /* PR 13449: Zero the table entries in case some of them are not used. */
26599 memset (ptr, 0, (size << 2) + 4);
c19d1205 26600 where = frag_now_fix () - ((size << 2) + 4);
bfae80f2 26601
c19d1205 26602 switch (unwind.personality_index)
bfae80f2 26603 {
c19d1205
ZW
26604 case -1:
26605 /* ??? Should this be a PLT generating relocation? */
26606 /* Custom personality routine. */
26607 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
26608 BFD_RELOC_ARM_PREL31);
bfae80f2 26609
c19d1205
ZW
26610 where += 4;
26611 ptr += 4;
bfae80f2 26612
c19d1205 26613 /* Set the first byte to the number of additional words. */
5011093d 26614 data = size > 0 ? size - 1 : 0;
c19d1205
ZW
26615 n = 3;
26616 break;
bfae80f2 26617
c19d1205
ZW
26618 /* ABI defined personality routines. */
26619 case 0:
26620 /* Three opcodes bytes are packed into the first word. */
26621 data = 0x80;
26622 n = 3;
26623 break;
bfae80f2 26624
c19d1205
ZW
26625 case 1:
26626 case 2:
26627 /* The size and first two opcode bytes go in the first word. */
26628 data = ((0x80 + unwind.personality_index) << 8) | size;
26629 n = 2;
26630 break;
bfae80f2 26631
c19d1205
ZW
26632 default:
26633 /* Should never happen. */
26634 abort ();
26635 }
bfae80f2 26636
c19d1205
ZW
26637 /* Pack the opcodes into words (MSB first), reversing the list at the same
26638 time. */
26639 while (unwind.opcode_count > 0)
26640 {
26641 if (n == 0)
26642 {
26643 md_number_to_chars (ptr, data, 4);
26644 ptr += 4;
26645 n = 4;
26646 data = 0;
26647 }
26648 unwind.opcode_count--;
26649 n--;
26650 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
26651 }
26652
26653 /* Finish off the last word. */
26654 if (n < 4)
26655 {
26656 /* Pad with "finish" opcodes. */
26657 while (n--)
26658 data = (data << 8) | 0xb0;
26659
26660 md_number_to_chars (ptr, data, 4);
26661 }
26662
26663 if (!have_data)
26664 {
26665 /* Add an empty descriptor if there is no user-specified data. */
26666 ptr = frag_more (4);
26667 md_number_to_chars (ptr, 0, 4);
26668 }
26669
26670 return 0;
bfae80f2
RE
26671}
26672
f0927246
NC
26673
26674/* Initialize the DWARF-2 unwind information for this procedure. */
26675
26676void
26677tc_arm_frame_initial_instructions (void)
26678{
26679 cfi_add_CFA_def_cfa (REG_SP, 0);
26680}
26681#endif /* OBJ_ELF */
26682
c19d1205
ZW
26683/* Convert REGNAME to a DWARF-2 register number. */
26684
26685int
1df69f4f 26686tc_arm_regname_to_dw2regnum (char *regname)
bfae80f2 26687{
1df69f4f 26688 int reg = arm_reg_parse (&regname, REG_TYPE_RN);
1f5afe1c
NC
26689 if (reg != FAIL)
26690 return reg;
c19d1205 26691
1f5afe1c
NC
26692 /* PR 16694: Allow VFP registers as well. */
26693 reg = arm_reg_parse (&regname, REG_TYPE_VFS);
26694 if (reg != FAIL)
26695 return 64 + reg;
c19d1205 26696
1f5afe1c
NC
26697 reg = arm_reg_parse (&regname, REG_TYPE_VFD);
26698 if (reg != FAIL)
26699 return reg + 256;
26700
0198d5e6 26701 return FAIL;
bfae80f2
RE
26702}
26703
f0927246 26704#ifdef TE_PE
c19d1205 26705void
f0927246 26706tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
bfae80f2 26707{
91d6fa6a 26708 expressionS exp;
bfae80f2 26709
91d6fa6a
NC
26710 exp.X_op = O_secrel;
26711 exp.X_add_symbol = symbol;
26712 exp.X_add_number = 0;
26713 emit_expr (&exp, size);
f0927246
NC
26714}
26715#endif
bfae80f2 26716
c19d1205 26717/* MD interface: Symbol and relocation handling. */
bfae80f2 26718
2fc8bdac
ZW
26719/* Return the address within the segment that a PC-relative fixup is
26720 relative to. For ARM, PC-relative fixups applied to instructions
26721 are generally relative to the location of the fixup plus 8 bytes.
26722 Thumb branches are offset by 4, and Thumb loads relative to PC
26723 require special handling. */
bfae80f2 26724
c19d1205 26725long
2fc8bdac 26726md_pcrel_from_section (fixS * fixP, segT seg)
bfae80f2 26727{
2fc8bdac
ZW
26728 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
26729
26730 /* If this is pc-relative and we are going to emit a relocation
26731 then we just want to put out any pipeline compensation that the linker
53baae48
NC
26732 will need. Otherwise we want to use the calculated base.
26733 For WinCE we skip the bias for externals as well, since this
26734 is how the MS ARM-CE assembler behaves and we want to be compatible. */
5f4273c7 26735 if (fixP->fx_pcrel
2fc8bdac 26736 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
53baae48
NC
26737 || (arm_force_relocation (fixP)
26738#ifdef TE_WINCE
26739 && !S_IS_EXTERNAL (fixP->fx_addsy)
26740#endif
26741 )))
2fc8bdac 26742 base = 0;
bfae80f2 26743
267bf995 26744
c19d1205 26745 switch (fixP->fx_r_type)
bfae80f2 26746 {
2fc8bdac
ZW
26747 /* PC relative addressing on the Thumb is slightly odd as the
26748 bottom two bits of the PC are forced to zero for the
26749 calculation. This happens *after* application of the
26750 pipeline offset. However, Thumb adrl already adjusts for
26751 this, so we need not do it again. */
c19d1205 26752 case BFD_RELOC_ARM_THUMB_ADD:
2fc8bdac 26753 return base & ~3;
c19d1205
ZW
26754
26755 case BFD_RELOC_ARM_THUMB_OFFSET:
26756 case BFD_RELOC_ARM_T32_OFFSET_IMM:
e9f89963 26757 case BFD_RELOC_ARM_T32_ADD_PC12:
8f06b2d8 26758 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
2fc8bdac 26759 return (base + 4) & ~3;
c19d1205 26760
2fc8bdac 26761 /* Thumb branches are simply offset by +4. */
e12437dc 26762 case BFD_RELOC_THUMB_PCREL_BRANCH5:
2fc8bdac
ZW
26763 case BFD_RELOC_THUMB_PCREL_BRANCH7:
26764 case BFD_RELOC_THUMB_PCREL_BRANCH9:
26765 case BFD_RELOC_THUMB_PCREL_BRANCH12:
26766 case BFD_RELOC_THUMB_PCREL_BRANCH20:
2fc8bdac 26767 case BFD_RELOC_THUMB_PCREL_BRANCH25:
f6b2b12d 26768 case BFD_RELOC_THUMB_PCREL_BFCSEL:
e5d6e09e 26769 case BFD_RELOC_ARM_THUMB_BF17:
1caf72a5 26770 case BFD_RELOC_ARM_THUMB_BF19:
1889da70 26771 case BFD_RELOC_ARM_THUMB_BF13:
60f993ce 26772 case BFD_RELOC_ARM_THUMB_LOOP12:
2fc8bdac 26773 return base + 4;
bfae80f2 26774
267bf995 26775 case BFD_RELOC_THUMB_PCREL_BRANCH23:
486499d0
CL
26776 if (fixP->fx_addsy
26777 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 26778 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995 26779 && ARM_IS_FUNC (fixP->fx_addsy)
477330fc
RM
26780 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
26781 base = fixP->fx_where + fixP->fx_frag->fr_address;
267bf995
RR
26782 return base + 4;
26783
00adf2d4
JB
26784 /* BLX is like branches above, but forces the low two bits of PC to
26785 zero. */
486499d0
CL
26786 case BFD_RELOC_THUMB_PCREL_BLX:
26787 if (fixP->fx_addsy
26788 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 26789 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM
26790 && THUMB_IS_FUNC (fixP->fx_addsy)
26791 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
26792 base = fixP->fx_where + fixP->fx_frag->fr_address;
00adf2d4
JB
26793 return (base + 4) & ~3;
26794
2fc8bdac
ZW
26795 /* ARM mode branches are offset by +8. However, the Windows CE
26796 loader expects the relocation not to take this into account. */
267bf995 26797 case BFD_RELOC_ARM_PCREL_BLX:
486499d0
CL
26798 if (fixP->fx_addsy
26799 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 26800 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM
26801 && ARM_IS_FUNC (fixP->fx_addsy)
26802 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
26803 base = fixP->fx_where + fixP->fx_frag->fr_address;
486499d0 26804 return base + 8;
267bf995 26805
486499d0
CL
26806 case BFD_RELOC_ARM_PCREL_CALL:
26807 if (fixP->fx_addsy
26808 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 26809 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM
26810 && THUMB_IS_FUNC (fixP->fx_addsy)
26811 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
26812 base = fixP->fx_where + fixP->fx_frag->fr_address;
486499d0 26813 return base + 8;
267bf995 26814
2fc8bdac 26815 case BFD_RELOC_ARM_PCREL_BRANCH:
39b41c9c 26816 case BFD_RELOC_ARM_PCREL_JUMP:
2fc8bdac 26817 case BFD_RELOC_ARM_PLT32:
c19d1205 26818#ifdef TE_WINCE
5f4273c7 26819 /* When handling fixups immediately, because we have already
477330fc 26820 discovered the value of a symbol, or the address of the frag involved
53baae48 26821 we must account for the offset by +8, as the OS loader will never see the reloc.
477330fc
RM
26822 see fixup_segment() in write.c
26823 The S_IS_EXTERNAL test handles the case of global symbols.
26824 Those need the calculated base, not just the pipe compensation the linker will need. */
53baae48
NC
26825 if (fixP->fx_pcrel
26826 && fixP->fx_addsy != NULL
26827 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
26828 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
26829 return base + 8;
2fc8bdac 26830 return base;
c19d1205 26831#else
2fc8bdac 26832 return base + 8;
c19d1205 26833#endif
2fc8bdac 26834
267bf995 26835
2fc8bdac
ZW
26836 /* ARM mode loads relative to PC are also offset by +8. Unlike
26837 branches, the Windows CE loader *does* expect the relocation
26838 to take this into account. */
26839 case BFD_RELOC_ARM_OFFSET_IMM:
26840 case BFD_RELOC_ARM_OFFSET_IMM8:
26841 case BFD_RELOC_ARM_HWLITERAL:
26842 case BFD_RELOC_ARM_LITERAL:
26843 case BFD_RELOC_ARM_CP_OFF_IMM:
26844 return base + 8;
26845
26846
26847 /* Other PC-relative relocations are un-offset. */
26848 default:
26849 return base;
26850 }
bfae80f2
RE
26851}
26852
8b2d793c
NC
26853static bfd_boolean flag_warn_syms = TRUE;
26854
ae8714c2
NC
26855bfd_boolean
26856arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name)
bfae80f2 26857{
8b2d793c
NC
26858 /* PR 18347 - Warn if the user attempts to create a symbol with the same
26859 name as an ARM instruction. Whilst strictly speaking it is allowed, it
26860 does mean that the resulting code might be very confusing to the reader.
26861 Also this warning can be triggered if the user omits an operand before
26862 an immediate address, eg:
26863
26864 LDR =foo
26865
26866 GAS treats this as an assignment of the value of the symbol foo to a
26867 symbol LDR, and so (without this code) it will not issue any kind of
26868 warning or error message.
26869
26870 Note - ARM instructions are case-insensitive but the strings in the hash
26871 table are all stored in lower case, so we must first ensure that name is
ae8714c2
NC
26872 lower case too. */
26873 if (flag_warn_syms && arm_ops_hsh)
8b2d793c
NC
26874 {
26875 char * nbuf = strdup (name);
26876 char * p;
26877
26878 for (p = nbuf; *p; p++)
26879 *p = TOLOWER (*p);
26880 if (hash_find (arm_ops_hsh, nbuf) != NULL)
26881 {
26882 static struct hash_control * already_warned = NULL;
26883
26884 if (already_warned == NULL)
26885 already_warned = hash_new ();
26886 /* Only warn about the symbol once. To keep the code
26887 simple we let hash_insert do the lookup for us. */
3076e594 26888 if (hash_insert (already_warned, nbuf, NULL) == NULL)
ae8714c2 26889 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name);
8b2d793c
NC
26890 }
26891 else
26892 free (nbuf);
26893 }
3739860c 26894
ae8714c2
NC
26895 return FALSE;
26896}
26897
26898/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
26899 Otherwise we have no need to default values of symbols. */
26900
26901symbolS *
26902md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
26903{
26904#ifdef OBJ_ELF
26905 if (name[0] == '_' && name[1] == 'G'
26906 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
26907 {
26908 if (!GOT_symbol)
26909 {
26910 if (symbol_find (name))
26911 as_bad (_("GOT already in the symbol table"));
26912
26913 GOT_symbol = symbol_new (name, undefined_section,
26914 (valueT) 0, & zero_address_frag);
26915 }
26916
26917 return GOT_symbol;
26918 }
26919#endif
26920
c921be7d 26921 return NULL;
bfae80f2
RE
26922}
26923
55cf6793 26924/* Subroutine of md_apply_fix. Check to see if an immediate can be
c19d1205
ZW
26925 computed as two separate immediate values, added together. We
26926 already know that this value cannot be computed by just one ARM
26927 instruction. */
26928
26929static unsigned int
26930validate_immediate_twopart (unsigned int val,
26931 unsigned int * highpart)
bfae80f2 26932{
c19d1205
ZW
26933 unsigned int a;
26934 unsigned int i;
bfae80f2 26935
c19d1205
ZW
26936 for (i = 0; i < 32; i += 2)
26937 if (((a = rotate_left (val, i)) & 0xff) != 0)
26938 {
26939 if (a & 0xff00)
26940 {
26941 if (a & ~ 0xffff)
26942 continue;
26943 * highpart = (a >> 8) | ((i + 24) << 7);
26944 }
26945 else if (a & 0xff0000)
26946 {
26947 if (a & 0xff000000)
26948 continue;
26949 * highpart = (a >> 16) | ((i + 16) << 7);
26950 }
26951 else
26952 {
9c2799c2 26953 gas_assert (a & 0xff000000);
c19d1205
ZW
26954 * highpart = (a >> 24) | ((i + 8) << 7);
26955 }
bfae80f2 26956
c19d1205
ZW
26957 return (a & 0xff) | (i << 7);
26958 }
bfae80f2 26959
c19d1205 26960 return FAIL;
bfae80f2
RE
26961}
26962
c19d1205
ZW
26963static int
26964validate_offset_imm (unsigned int val, int hwse)
26965{
26966 if ((hwse && val > 255) || val > 4095)
26967 return FAIL;
26968 return val;
26969}
bfae80f2 26970
55cf6793 26971/* Subroutine of md_apply_fix. Do those data_ops which can take a
c19d1205
ZW
26972 negative immediate constant by altering the instruction. A bit of
26973 a hack really.
26974 MOV <-> MVN
26975 AND <-> BIC
26976 ADC <-> SBC
26977 by inverting the second operand, and
26978 ADD <-> SUB
26979 CMP <-> CMN
26980 by negating the second operand. */
bfae80f2 26981
c19d1205
ZW
26982static int
26983negate_data_op (unsigned long * instruction,
26984 unsigned long value)
bfae80f2 26985{
c19d1205
ZW
26986 int op, new_inst;
26987 unsigned long negated, inverted;
bfae80f2 26988
c19d1205
ZW
26989 negated = encode_arm_immediate (-value);
26990 inverted = encode_arm_immediate (~value);
bfae80f2 26991
c19d1205
ZW
26992 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
26993 switch (op)
bfae80f2 26994 {
c19d1205
ZW
26995 /* First negates. */
26996 case OPCODE_SUB: /* ADD <-> SUB */
26997 new_inst = OPCODE_ADD;
26998 value = negated;
26999 break;
bfae80f2 27000
c19d1205
ZW
27001 case OPCODE_ADD:
27002 new_inst = OPCODE_SUB;
27003 value = negated;
27004 break;
bfae80f2 27005
c19d1205
ZW
27006 case OPCODE_CMP: /* CMP <-> CMN */
27007 new_inst = OPCODE_CMN;
27008 value = negated;
27009 break;
bfae80f2 27010
c19d1205
ZW
27011 case OPCODE_CMN:
27012 new_inst = OPCODE_CMP;
27013 value = negated;
27014 break;
bfae80f2 27015
c19d1205
ZW
27016 /* Now Inverted ops. */
27017 case OPCODE_MOV: /* MOV <-> MVN */
27018 new_inst = OPCODE_MVN;
27019 value = inverted;
27020 break;
bfae80f2 27021
c19d1205
ZW
27022 case OPCODE_MVN:
27023 new_inst = OPCODE_MOV;
27024 value = inverted;
27025 break;
bfae80f2 27026
c19d1205
ZW
27027 case OPCODE_AND: /* AND <-> BIC */
27028 new_inst = OPCODE_BIC;
27029 value = inverted;
27030 break;
bfae80f2 27031
c19d1205
ZW
27032 case OPCODE_BIC:
27033 new_inst = OPCODE_AND;
27034 value = inverted;
27035 break;
bfae80f2 27036
c19d1205
ZW
27037 case OPCODE_ADC: /* ADC <-> SBC */
27038 new_inst = OPCODE_SBC;
27039 value = inverted;
27040 break;
bfae80f2 27041
c19d1205
ZW
27042 case OPCODE_SBC:
27043 new_inst = OPCODE_ADC;
27044 value = inverted;
27045 break;
bfae80f2 27046
c19d1205
ZW
27047 /* We cannot do anything. */
27048 default:
27049 return FAIL;
b99bd4ef
NC
27050 }
27051
c19d1205
ZW
27052 if (value == (unsigned) FAIL)
27053 return FAIL;
27054
27055 *instruction &= OPCODE_MASK;
27056 *instruction |= new_inst << DATA_OP_SHIFT;
27057 return value;
b99bd4ef
NC
27058}
27059
ef8d22e6
PB
27060/* Like negate_data_op, but for Thumb-2. */
27061
27062static unsigned int
16dd5e42 27063thumb32_negate_data_op (offsetT *instruction, unsigned int value)
ef8d22e6
PB
27064{
27065 int op, new_inst;
27066 int rd;
16dd5e42 27067 unsigned int negated, inverted;
ef8d22e6
PB
27068
27069 negated = encode_thumb32_immediate (-value);
27070 inverted = encode_thumb32_immediate (~value);
27071
27072 rd = (*instruction >> 8) & 0xf;
27073 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
27074 switch (op)
27075 {
27076 /* ADD <-> SUB. Includes CMP <-> CMN. */
27077 case T2_OPCODE_SUB:
27078 new_inst = T2_OPCODE_ADD;
27079 value = negated;
27080 break;
27081
27082 case T2_OPCODE_ADD:
27083 new_inst = T2_OPCODE_SUB;
27084 value = negated;
27085 break;
27086
27087 /* ORR <-> ORN. Includes MOV <-> MVN. */
27088 case T2_OPCODE_ORR:
27089 new_inst = T2_OPCODE_ORN;
27090 value = inverted;
27091 break;
27092
27093 case T2_OPCODE_ORN:
27094 new_inst = T2_OPCODE_ORR;
27095 value = inverted;
27096 break;
27097
27098 /* AND <-> BIC. TST has no inverted equivalent. */
27099 case T2_OPCODE_AND:
27100 new_inst = T2_OPCODE_BIC;
27101 if (rd == 15)
27102 value = FAIL;
27103 else
27104 value = inverted;
27105 break;
27106
27107 case T2_OPCODE_BIC:
27108 new_inst = T2_OPCODE_AND;
27109 value = inverted;
27110 break;
27111
27112 /* ADC <-> SBC */
27113 case T2_OPCODE_ADC:
27114 new_inst = T2_OPCODE_SBC;
27115 value = inverted;
27116 break;
27117
27118 case T2_OPCODE_SBC:
27119 new_inst = T2_OPCODE_ADC;
27120 value = inverted;
27121 break;
27122
27123 /* We cannot do anything. */
27124 default:
27125 return FAIL;
27126 }
27127
16dd5e42 27128 if (value == (unsigned int)FAIL)
ef8d22e6
PB
27129 return FAIL;
27130
27131 *instruction &= T2_OPCODE_MASK;
27132 *instruction |= new_inst << T2_DATA_OP_SHIFT;
27133 return value;
27134}
27135
8f06b2d8 27136/* Read a 32-bit thumb instruction from buf. */
0198d5e6 27137
8f06b2d8
PB
27138static unsigned long
27139get_thumb32_insn (char * buf)
27140{
27141 unsigned long insn;
27142 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
27143 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27144
27145 return insn;
27146}
27147
a8bc6c78
PB
27148/* We usually want to set the low bit on the address of thumb function
27149 symbols. In particular .word foo - . should have the low bit set.
27150 Generic code tries to fold the difference of two symbols to
27151 a constant. Prevent this and force a relocation when the first symbols
27152 is a thumb function. */
c921be7d
NC
27153
27154bfd_boolean
a8bc6c78
PB
27155arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
27156{
27157 if (op == O_subtract
27158 && l->X_op == O_symbol
27159 && r->X_op == O_symbol
27160 && THUMB_IS_FUNC (l->X_add_symbol))
27161 {
27162 l->X_op = O_subtract;
27163 l->X_op_symbol = r->X_add_symbol;
27164 l->X_add_number -= r->X_add_number;
c921be7d 27165 return TRUE;
a8bc6c78 27166 }
c921be7d 27167
a8bc6c78 27168 /* Process as normal. */
c921be7d 27169 return FALSE;
a8bc6c78
PB
27170}
27171
4a42ebbc
RR
27172/* Encode Thumb2 unconditional branches and calls. The encoding
27173 for the 2 are identical for the immediate values. */
27174
27175static void
27176encode_thumb2_b_bl_offset (char * buf, offsetT value)
27177{
27178#define T2I1I2MASK ((1 << 13) | (1 << 11))
27179 offsetT newval;
27180 offsetT newval2;
27181 addressT S, I1, I2, lo, hi;
27182
27183 S = (value >> 24) & 0x01;
27184 I1 = (value >> 23) & 0x01;
27185 I2 = (value >> 22) & 0x01;
27186 hi = (value >> 12) & 0x3ff;
fa94de6b 27187 lo = (value >> 1) & 0x7ff;
4a42ebbc
RR
27188 newval = md_chars_to_number (buf, THUMB_SIZE);
27189 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27190 newval |= (S << 10) | hi;
27191 newval2 &= ~T2I1I2MASK;
27192 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
27193 md_number_to_chars (buf, newval, THUMB_SIZE);
27194 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
27195}
27196
c19d1205 27197void
55cf6793 27198md_apply_fix (fixS * fixP,
c19d1205
ZW
27199 valueT * valP,
27200 segT seg)
27201{
27202 offsetT value = * valP;
27203 offsetT newval;
27204 unsigned int newimm;
27205 unsigned long temp;
27206 int sign;
27207 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
b99bd4ef 27208
9c2799c2 27209 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
b99bd4ef 27210
c19d1205 27211 /* Note whether this will delete the relocation. */
4962c51a 27212
c19d1205
ZW
27213 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
27214 fixP->fx_done = 1;
b99bd4ef 27215
adbaf948 27216 /* On a 64-bit host, silently truncate 'value' to 32 bits for
5f4273c7 27217 consistency with the behaviour on 32-bit hosts. Remember value
adbaf948
ZW
27218 for emit_reloc. */
27219 value &= 0xffffffff;
27220 value ^= 0x80000000;
5f4273c7 27221 value -= 0x80000000;
adbaf948
ZW
27222
27223 *valP = value;
c19d1205 27224 fixP->fx_addnumber = value;
b99bd4ef 27225
adbaf948
ZW
27226 /* Same treatment for fixP->fx_offset. */
27227 fixP->fx_offset &= 0xffffffff;
27228 fixP->fx_offset ^= 0x80000000;
27229 fixP->fx_offset -= 0x80000000;
27230
c19d1205 27231 switch (fixP->fx_r_type)
b99bd4ef 27232 {
c19d1205
ZW
27233 case BFD_RELOC_NONE:
27234 /* This will need to go in the object file. */
27235 fixP->fx_done = 0;
27236 break;
b99bd4ef 27237
c19d1205
ZW
27238 case BFD_RELOC_ARM_IMMEDIATE:
27239 /* We claim that this fixup has been processed here,
27240 even if in fact we generate an error because we do
27241 not have a reloc for it, so tc_gen_reloc will reject it. */
27242 fixP->fx_done = 1;
b99bd4ef 27243
77db8e2e 27244 if (fixP->fx_addsy)
b99bd4ef 27245 {
77db8e2e 27246 const char *msg = 0;
b99bd4ef 27247
77db8e2e
NC
27248 if (! S_IS_DEFINED (fixP->fx_addsy))
27249 msg = _("undefined symbol %s used as an immediate value");
27250 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
27251 msg = _("symbol %s is in a different section");
27252 else if (S_IS_WEAK (fixP->fx_addsy))
27253 msg = _("symbol %s is weak and may be overridden later");
27254
27255 if (msg)
27256 {
27257 as_bad_where (fixP->fx_file, fixP->fx_line,
27258 msg, S_GET_NAME (fixP->fx_addsy));
27259 break;
27260 }
42e5fcbf
AS
27261 }
27262
c19d1205
ZW
27263 temp = md_chars_to_number (buf, INSN_SIZE);
27264
5e73442d
SL
27265 /* If the offset is negative, we should use encoding A2 for ADR. */
27266 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
27267 newimm = negate_data_op (&temp, value);
27268 else
27269 {
27270 newimm = encode_arm_immediate (value);
27271
27272 /* If the instruction will fail, see if we can fix things up by
27273 changing the opcode. */
27274 if (newimm == (unsigned int) FAIL)
27275 newimm = negate_data_op (&temp, value);
bada4342
JW
27276 /* MOV accepts both ARM modified immediate (A1 encoding) and
27277 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
27278 When disassembling, MOV is preferred when there is no encoding
27279 overlap. */
27280 if (newimm == (unsigned int) FAIL
27281 && ((temp >> DATA_OP_SHIFT) & 0xf) == OPCODE_MOV
27282 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
27283 && !((temp >> SBIT_SHIFT) & 0x1)
27284 && value >= 0 && value <= 0xffff)
27285 {
27286 /* Clear bits[23:20] to change encoding from A1 to A2. */
27287 temp &= 0xff0fffff;
27288 /* Encoding high 4bits imm. Code below will encode the remaining
27289 low 12bits. */
27290 temp |= (value & 0x0000f000) << 4;
27291 newimm = value & 0x00000fff;
27292 }
5e73442d
SL
27293 }
27294
27295 if (newimm == (unsigned int) FAIL)
b99bd4ef 27296 {
c19d1205
ZW
27297 as_bad_where (fixP->fx_file, fixP->fx_line,
27298 _("invalid constant (%lx) after fixup"),
27299 (unsigned long) value);
27300 break;
b99bd4ef 27301 }
b99bd4ef 27302
c19d1205
ZW
27303 newimm |= (temp & 0xfffff000);
27304 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
27305 break;
b99bd4ef 27306
c19d1205
ZW
27307 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
27308 {
27309 unsigned int highpart = 0;
27310 unsigned int newinsn = 0xe1a00000; /* nop. */
b99bd4ef 27311
77db8e2e 27312 if (fixP->fx_addsy)
42e5fcbf 27313 {
77db8e2e 27314 const char *msg = 0;
42e5fcbf 27315
77db8e2e
NC
27316 if (! S_IS_DEFINED (fixP->fx_addsy))
27317 msg = _("undefined symbol %s used as an immediate value");
27318 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
27319 msg = _("symbol %s is in a different section");
27320 else if (S_IS_WEAK (fixP->fx_addsy))
27321 msg = _("symbol %s is weak and may be overridden later");
42e5fcbf 27322
77db8e2e
NC
27323 if (msg)
27324 {
27325 as_bad_where (fixP->fx_file, fixP->fx_line,
27326 msg, S_GET_NAME (fixP->fx_addsy));
27327 break;
27328 }
27329 }
fa94de6b 27330
c19d1205
ZW
27331 newimm = encode_arm_immediate (value);
27332 temp = md_chars_to_number (buf, INSN_SIZE);
b99bd4ef 27333
c19d1205
ZW
27334 /* If the instruction will fail, see if we can fix things up by
27335 changing the opcode. */
27336 if (newimm == (unsigned int) FAIL
27337 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
27338 {
27339 /* No ? OK - try using two ADD instructions to generate
27340 the value. */
27341 newimm = validate_immediate_twopart (value, & highpart);
b99bd4ef 27342
c19d1205
ZW
27343 /* Yes - then make sure that the second instruction is
27344 also an add. */
27345 if (newimm != (unsigned int) FAIL)
27346 newinsn = temp;
27347 /* Still No ? Try using a negated value. */
27348 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
27349 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
27350 /* Otherwise - give up. */
27351 else
27352 {
27353 as_bad_where (fixP->fx_file, fixP->fx_line,
27354 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
27355 (long) value);
27356 break;
27357 }
b99bd4ef 27358
c19d1205
ZW
27359 /* Replace the first operand in the 2nd instruction (which
27360 is the PC) with the destination register. We have
27361 already added in the PC in the first instruction and we
27362 do not want to do it again. */
27363 newinsn &= ~ 0xf0000;
27364 newinsn |= ((newinsn & 0x0f000) << 4);
27365 }
b99bd4ef 27366
c19d1205
ZW
27367 newimm |= (temp & 0xfffff000);
27368 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
b99bd4ef 27369
c19d1205
ZW
27370 highpart |= (newinsn & 0xfffff000);
27371 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
27372 }
27373 break;
b99bd4ef 27374
c19d1205 27375 case BFD_RELOC_ARM_OFFSET_IMM:
00a97672
RS
27376 if (!fixP->fx_done && seg->use_rela_p)
27377 value = 0;
1a0670f3 27378 /* Fall through. */
00a97672 27379
c19d1205 27380 case BFD_RELOC_ARM_LITERAL:
26d97720 27381 sign = value > 0;
b99bd4ef 27382
c19d1205
ZW
27383 if (value < 0)
27384 value = - value;
b99bd4ef 27385
c19d1205 27386 if (validate_offset_imm (value, 0) == FAIL)
f03698e6 27387 {
c19d1205
ZW
27388 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
27389 as_bad_where (fixP->fx_file, fixP->fx_line,
27390 _("invalid literal constant: pool needs to be closer"));
27391 else
27392 as_bad_where (fixP->fx_file, fixP->fx_line,
27393 _("bad immediate value for offset (%ld)"),
27394 (long) value);
27395 break;
f03698e6
RE
27396 }
27397
c19d1205 27398 newval = md_chars_to_number (buf, INSN_SIZE);
26d97720
NS
27399 if (value == 0)
27400 newval &= 0xfffff000;
27401 else
27402 {
27403 newval &= 0xff7ff000;
27404 newval |= value | (sign ? INDEX_UP : 0);
27405 }
c19d1205
ZW
27406 md_number_to_chars (buf, newval, INSN_SIZE);
27407 break;
b99bd4ef 27408
c19d1205
ZW
27409 case BFD_RELOC_ARM_OFFSET_IMM8:
27410 case BFD_RELOC_ARM_HWLITERAL:
26d97720 27411 sign = value > 0;
b99bd4ef 27412
c19d1205
ZW
27413 if (value < 0)
27414 value = - value;
b99bd4ef 27415
c19d1205 27416 if (validate_offset_imm (value, 1) == FAIL)
b99bd4ef 27417 {
c19d1205
ZW
27418 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
27419 as_bad_where (fixP->fx_file, fixP->fx_line,
27420 _("invalid literal constant: pool needs to be closer"));
27421 else
427d0db6
RM
27422 as_bad_where (fixP->fx_file, fixP->fx_line,
27423 _("bad immediate value for 8-bit offset (%ld)"),
27424 (long) value);
c19d1205 27425 break;
b99bd4ef
NC
27426 }
27427
c19d1205 27428 newval = md_chars_to_number (buf, INSN_SIZE);
26d97720
NS
27429 if (value == 0)
27430 newval &= 0xfffff0f0;
27431 else
27432 {
27433 newval &= 0xff7ff0f0;
27434 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
27435 }
c19d1205
ZW
27436 md_number_to_chars (buf, newval, INSN_SIZE);
27437 break;
b99bd4ef 27438
c19d1205
ZW
27439 case BFD_RELOC_ARM_T32_OFFSET_U8:
27440 if (value < 0 || value > 1020 || value % 4 != 0)
27441 as_bad_where (fixP->fx_file, fixP->fx_line,
27442 _("bad immediate value for offset (%ld)"), (long) value);
27443 value /= 4;
b99bd4ef 27444
c19d1205 27445 newval = md_chars_to_number (buf+2, THUMB_SIZE);
c19d1205
ZW
27446 newval |= value;
27447 md_number_to_chars (buf+2, newval, THUMB_SIZE);
27448 break;
b99bd4ef 27449
c19d1205
ZW
27450 case BFD_RELOC_ARM_T32_OFFSET_IMM:
27451 /* This is a complicated relocation used for all varieties of Thumb32
27452 load/store instruction with immediate offset:
27453
27454 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
477330fc 27455 *4, optional writeback(W)
c19d1205
ZW
27456 (doubleword load/store)
27457
27458 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
27459 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
27460 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
27461 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
27462 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
27463
27464 Uppercase letters indicate bits that are already encoded at
27465 this point. Lowercase letters are our problem. For the
27466 second block of instructions, the secondary opcode nybble
27467 (bits 8..11) is present, and bit 23 is zero, even if this is
27468 a PC-relative operation. */
27469 newval = md_chars_to_number (buf, THUMB_SIZE);
27470 newval <<= 16;
27471 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
b99bd4ef 27472
c19d1205 27473 if ((newval & 0xf0000000) == 0xe0000000)
b99bd4ef 27474 {
c19d1205
ZW
27475 /* Doubleword load/store: 8-bit offset, scaled by 4. */
27476 if (value >= 0)
27477 newval |= (1 << 23);
27478 else
27479 value = -value;
27480 if (value % 4 != 0)
27481 {
27482 as_bad_where (fixP->fx_file, fixP->fx_line,
27483 _("offset not a multiple of 4"));
27484 break;
27485 }
27486 value /= 4;
216d22bc 27487 if (value > 0xff)
c19d1205
ZW
27488 {
27489 as_bad_where (fixP->fx_file, fixP->fx_line,
27490 _("offset out of range"));
27491 break;
27492 }
27493 newval &= ~0xff;
b99bd4ef 27494 }
c19d1205 27495 else if ((newval & 0x000f0000) == 0x000f0000)
b99bd4ef 27496 {
c19d1205
ZW
27497 /* PC-relative, 12-bit offset. */
27498 if (value >= 0)
27499 newval |= (1 << 23);
27500 else
27501 value = -value;
216d22bc 27502 if (value > 0xfff)
c19d1205
ZW
27503 {
27504 as_bad_where (fixP->fx_file, fixP->fx_line,
27505 _("offset out of range"));
27506 break;
27507 }
27508 newval &= ~0xfff;
b99bd4ef 27509 }
c19d1205 27510 else if ((newval & 0x00000100) == 0x00000100)
b99bd4ef 27511 {
c19d1205
ZW
27512 /* Writeback: 8-bit, +/- offset. */
27513 if (value >= 0)
27514 newval |= (1 << 9);
27515 else
27516 value = -value;
216d22bc 27517 if (value > 0xff)
c19d1205
ZW
27518 {
27519 as_bad_where (fixP->fx_file, fixP->fx_line,
27520 _("offset out of range"));
27521 break;
27522 }
27523 newval &= ~0xff;
b99bd4ef 27524 }
c19d1205 27525 else if ((newval & 0x00000f00) == 0x00000e00)
b99bd4ef 27526 {
c19d1205 27527 /* T-instruction: positive 8-bit offset. */
216d22bc 27528 if (value < 0 || value > 0xff)
b99bd4ef 27529 {
c19d1205
ZW
27530 as_bad_where (fixP->fx_file, fixP->fx_line,
27531 _("offset out of range"));
27532 break;
b99bd4ef 27533 }
c19d1205
ZW
27534 newval &= ~0xff;
27535 newval |= value;
b99bd4ef
NC
27536 }
27537 else
b99bd4ef 27538 {
c19d1205
ZW
27539 /* Positive 12-bit or negative 8-bit offset. */
27540 int limit;
27541 if (value >= 0)
b99bd4ef 27542 {
c19d1205
ZW
27543 newval |= (1 << 23);
27544 limit = 0xfff;
27545 }
27546 else
27547 {
27548 value = -value;
27549 limit = 0xff;
27550 }
27551 if (value > limit)
27552 {
27553 as_bad_where (fixP->fx_file, fixP->fx_line,
27554 _("offset out of range"));
27555 break;
b99bd4ef 27556 }
c19d1205 27557 newval &= ~limit;
b99bd4ef 27558 }
b99bd4ef 27559
c19d1205
ZW
27560 newval |= value;
27561 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
27562 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
27563 break;
404ff6b5 27564
c19d1205
ZW
27565 case BFD_RELOC_ARM_SHIFT_IMM:
27566 newval = md_chars_to_number (buf, INSN_SIZE);
27567 if (((unsigned long) value) > 32
27568 || (value == 32
27569 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
27570 {
27571 as_bad_where (fixP->fx_file, fixP->fx_line,
27572 _("shift expression is too large"));
27573 break;
27574 }
404ff6b5 27575
c19d1205
ZW
27576 if (value == 0)
27577 /* Shifts of zero must be done as lsl. */
27578 newval &= ~0x60;
27579 else if (value == 32)
27580 value = 0;
27581 newval &= 0xfffff07f;
27582 newval |= (value & 0x1f) << 7;
27583 md_number_to_chars (buf, newval, INSN_SIZE);
27584 break;
404ff6b5 27585
c19d1205 27586 case BFD_RELOC_ARM_T32_IMMEDIATE:
16805f35 27587 case BFD_RELOC_ARM_T32_ADD_IMM:
92e90b6e 27588 case BFD_RELOC_ARM_T32_IMM12:
e9f89963 27589 case BFD_RELOC_ARM_T32_ADD_PC12:
c19d1205
ZW
27590 /* We claim that this fixup has been processed here,
27591 even if in fact we generate an error because we do
27592 not have a reloc for it, so tc_gen_reloc will reject it. */
27593 fixP->fx_done = 1;
404ff6b5 27594
c19d1205
ZW
27595 if (fixP->fx_addsy
27596 && ! S_IS_DEFINED (fixP->fx_addsy))
27597 {
27598 as_bad_where (fixP->fx_file, fixP->fx_line,
27599 _("undefined symbol %s used as an immediate value"),
27600 S_GET_NAME (fixP->fx_addsy));
27601 break;
27602 }
404ff6b5 27603
c19d1205
ZW
27604 newval = md_chars_to_number (buf, THUMB_SIZE);
27605 newval <<= 16;
27606 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
404ff6b5 27607
16805f35 27608 newimm = FAIL;
bada4342
JW
27609 if ((fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
27610 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
27611 Thumb2 modified immediate encoding (T2). */
27612 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
16805f35 27613 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
ef8d22e6
PB
27614 {
27615 newimm = encode_thumb32_immediate (value);
27616 if (newimm == (unsigned int) FAIL)
27617 newimm = thumb32_negate_data_op (&newval, value);
27618 }
bada4342 27619 if (newimm == (unsigned int) FAIL)
92e90b6e 27620 {
bada4342 27621 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE)
e9f89963 27622 {
bada4342
JW
27623 /* Turn add/sum into addw/subw. */
27624 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
27625 newval = (newval & 0xfeffffff) | 0x02000000;
27626 /* No flat 12-bit imm encoding for addsw/subsw. */
27627 if ((newval & 0x00100000) == 0)
40f246e3 27628 {
bada4342
JW
27629 /* 12 bit immediate for addw/subw. */
27630 if (value < 0)
27631 {
27632 value = -value;
27633 newval ^= 0x00a00000;
27634 }
27635 if (value > 0xfff)
27636 newimm = (unsigned int) FAIL;
27637 else
27638 newimm = value;
27639 }
27640 }
27641 else
27642 {
27643 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
27644 UINT16 (T3 encoding), MOVW only accepts UINT16. When
27645 disassembling, MOV is preferred when there is no encoding
db7bf105 27646 overlap. */
bada4342 27647 if (((newval >> T2_DATA_OP_SHIFT) & 0xf) == T2_OPCODE_ORR
db7bf105
NC
27648 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
27649 but with the Rn field [19:16] set to 1111. */
27650 && (((newval >> 16) & 0xf) == 0xf)
bada4342
JW
27651 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)
27652 && !((newval >> T2_SBIT_SHIFT) & 0x1)
db7bf105 27653 && value >= 0 && value <= 0xffff)
bada4342
JW
27654 {
27655 /* Toggle bit[25] to change encoding from T2 to T3. */
27656 newval ^= 1 << 25;
27657 /* Clear bits[19:16]. */
27658 newval &= 0xfff0ffff;
27659 /* Encoding high 4bits imm. Code below will encode the
27660 remaining low 12bits. */
27661 newval |= (value & 0x0000f000) << 4;
27662 newimm = value & 0x00000fff;
40f246e3 27663 }
e9f89963 27664 }
92e90b6e 27665 }
cc8a6dd0 27666
c19d1205 27667 if (newimm == (unsigned int)FAIL)
3631a3c8 27668 {
c19d1205
ZW
27669 as_bad_where (fixP->fx_file, fixP->fx_line,
27670 _("invalid constant (%lx) after fixup"),
27671 (unsigned long) value);
27672 break;
3631a3c8
NC
27673 }
27674
c19d1205
ZW
27675 newval |= (newimm & 0x800) << 15;
27676 newval |= (newimm & 0x700) << 4;
27677 newval |= (newimm & 0x0ff);
cc8a6dd0 27678
c19d1205
ZW
27679 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
27680 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
27681 break;
a737bd4d 27682
3eb17e6b 27683 case BFD_RELOC_ARM_SMC:
c19d1205
ZW
27684 if (((unsigned long) value) > 0xffff)
27685 as_bad_where (fixP->fx_file, fixP->fx_line,
3eb17e6b 27686 _("invalid smc expression"));
2fc8bdac 27687 newval = md_chars_to_number (buf, INSN_SIZE);
c19d1205
ZW
27688 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
27689 md_number_to_chars (buf, newval, INSN_SIZE);
27690 break;
a737bd4d 27691
90ec0d68
MGD
27692 case BFD_RELOC_ARM_HVC:
27693 if (((unsigned long) value) > 0xffff)
27694 as_bad_where (fixP->fx_file, fixP->fx_line,
27695 _("invalid hvc expression"));
27696 newval = md_chars_to_number (buf, INSN_SIZE);
27697 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
27698 md_number_to_chars (buf, newval, INSN_SIZE);
27699 break;
27700
c19d1205 27701 case BFD_RELOC_ARM_SWI:
adbaf948 27702 if (fixP->tc_fix_data != 0)
c19d1205
ZW
27703 {
27704 if (((unsigned long) value) > 0xff)
27705 as_bad_where (fixP->fx_file, fixP->fx_line,
27706 _("invalid swi expression"));
2fc8bdac 27707 newval = md_chars_to_number (buf, THUMB_SIZE);
c19d1205
ZW
27708 newval |= value;
27709 md_number_to_chars (buf, newval, THUMB_SIZE);
27710 }
27711 else
27712 {
27713 if (((unsigned long) value) > 0x00ffffff)
27714 as_bad_where (fixP->fx_file, fixP->fx_line,
27715 _("invalid swi expression"));
2fc8bdac 27716 newval = md_chars_to_number (buf, INSN_SIZE);
c19d1205
ZW
27717 newval |= value;
27718 md_number_to_chars (buf, newval, INSN_SIZE);
27719 }
27720 break;
a737bd4d 27721
c19d1205
ZW
27722 case BFD_RELOC_ARM_MULTI:
27723 if (((unsigned long) value) > 0xffff)
27724 as_bad_where (fixP->fx_file, fixP->fx_line,
27725 _("invalid expression in load/store multiple"));
27726 newval = value | md_chars_to_number (buf, INSN_SIZE);
27727 md_number_to_chars (buf, newval, INSN_SIZE);
27728 break;
a737bd4d 27729
c19d1205 27730#ifdef OBJ_ELF
39b41c9c 27731 case BFD_RELOC_ARM_PCREL_CALL:
267bf995
RR
27732
27733 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
27734 && fixP->fx_addsy
34e77a92 27735 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR
27736 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27737 && THUMB_IS_FUNC (fixP->fx_addsy))
27738 /* Flip the bl to blx. This is a simple flip
27739 bit here because we generate PCREL_CALL for
27740 unconditional bls. */
27741 {
27742 newval = md_chars_to_number (buf, INSN_SIZE);
27743 newval = newval | 0x10000000;
27744 md_number_to_chars (buf, newval, INSN_SIZE);
27745 temp = 1;
27746 fixP->fx_done = 1;
27747 }
39b41c9c
PB
27748 else
27749 temp = 3;
27750 goto arm_branch_common;
27751
27752 case BFD_RELOC_ARM_PCREL_JUMP:
267bf995
RR
27753 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
27754 && fixP->fx_addsy
34e77a92 27755 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR
27756 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27757 && THUMB_IS_FUNC (fixP->fx_addsy))
27758 {
27759 /* This would map to a bl<cond>, b<cond>,
27760 b<always> to a Thumb function. We
27761 need to force a relocation for this particular
27762 case. */
27763 newval = md_chars_to_number (buf, INSN_SIZE);
27764 fixP->fx_done = 0;
27765 }
1a0670f3 27766 /* Fall through. */
267bf995 27767
2fc8bdac 27768 case BFD_RELOC_ARM_PLT32:
c19d1205 27769#endif
39b41c9c
PB
27770 case BFD_RELOC_ARM_PCREL_BRANCH:
27771 temp = 3;
27772 goto arm_branch_common;
a737bd4d 27773
39b41c9c 27774 case BFD_RELOC_ARM_PCREL_BLX:
267bf995 27775
39b41c9c 27776 temp = 1;
267bf995
RR
27777 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
27778 && fixP->fx_addsy
34e77a92 27779 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR
27780 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27781 && ARM_IS_FUNC (fixP->fx_addsy))
27782 {
27783 /* Flip the blx to a bl and warn. */
27784 const char *name = S_GET_NAME (fixP->fx_addsy);
27785 newval = 0xeb000000;
27786 as_warn_where (fixP->fx_file, fixP->fx_line,
27787 _("blx to '%s' an ARM ISA state function changed to bl"),
27788 name);
27789 md_number_to_chars (buf, newval, INSN_SIZE);
27790 temp = 3;
27791 fixP->fx_done = 1;
27792 }
27793
27794#ifdef OBJ_ELF
27795 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
477330fc 27796 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
267bf995
RR
27797#endif
27798
39b41c9c 27799 arm_branch_common:
c19d1205 27800 /* We are going to store value (shifted right by two) in the
39b41c9c
PB
27801 instruction, in a 24 bit, signed field. Bits 26 through 32 either
27802 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
de194d85 27803 also be clear. */
39b41c9c 27804 if (value & temp)
c19d1205 27805 as_bad_where (fixP->fx_file, fixP->fx_line,
2fc8bdac
ZW
27806 _("misaligned branch destination"));
27807 if ((value & (offsetT)0xfe000000) != (offsetT)0
27808 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
08f10d51 27809 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 27810
2fc8bdac 27811 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 27812 {
2fc8bdac
ZW
27813 newval = md_chars_to_number (buf, INSN_SIZE);
27814 newval |= (value >> 2) & 0x00ffffff;
7ae2971b
PB
27815 /* Set the H bit on BLX instructions. */
27816 if (temp == 1)
27817 {
27818 if (value & 2)
27819 newval |= 0x01000000;
27820 else
27821 newval &= ~0x01000000;
27822 }
2fc8bdac 27823 md_number_to_chars (buf, newval, INSN_SIZE);
c19d1205 27824 }
c19d1205 27825 break;
a737bd4d 27826
25fe350b
MS
27827 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
27828 /* CBZ can only branch forward. */
a737bd4d 27829
738755b0 27830 /* Attempts to use CBZ to branch to the next instruction
477330fc
RM
27831 (which, strictly speaking, are prohibited) will be turned into
27832 no-ops.
738755b0
MS
27833
27834 FIXME: It may be better to remove the instruction completely and
27835 perform relaxation. */
27836 if (value == -2)
2fc8bdac
ZW
27837 {
27838 newval = md_chars_to_number (buf, THUMB_SIZE);
738755b0 27839 newval = 0xbf00; /* NOP encoding T1 */
2fc8bdac
ZW
27840 md_number_to_chars (buf, newval, THUMB_SIZE);
27841 }
738755b0
MS
27842 else
27843 {
27844 if (value & ~0x7e)
08f10d51 27845 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
738755b0 27846
477330fc 27847 if (fixP->fx_done || !seg->use_rela_p)
738755b0
MS
27848 {
27849 newval = md_chars_to_number (buf, THUMB_SIZE);
27850 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
27851 md_number_to_chars (buf, newval, THUMB_SIZE);
27852 }
27853 }
c19d1205 27854 break;
a737bd4d 27855
c19d1205 27856 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
2fc8bdac 27857 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
08f10d51 27858 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 27859
2fc8bdac
ZW
27860 if (fixP->fx_done || !seg->use_rela_p)
27861 {
27862 newval = md_chars_to_number (buf, THUMB_SIZE);
27863 newval |= (value & 0x1ff) >> 1;
27864 md_number_to_chars (buf, newval, THUMB_SIZE);
27865 }
c19d1205 27866 break;
a737bd4d 27867
c19d1205 27868 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
2fc8bdac 27869 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
08f10d51 27870 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 27871
2fc8bdac
ZW
27872 if (fixP->fx_done || !seg->use_rela_p)
27873 {
27874 newval = md_chars_to_number (buf, THUMB_SIZE);
27875 newval |= (value & 0xfff) >> 1;
27876 md_number_to_chars (buf, newval, THUMB_SIZE);
27877 }
c19d1205 27878 break;
a737bd4d 27879
c19d1205 27880 case BFD_RELOC_THUMB_PCREL_BRANCH20:
267bf995
RR
27881 if (fixP->fx_addsy
27882 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 27883 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR
27884 && ARM_IS_FUNC (fixP->fx_addsy)
27885 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27886 {
27887 /* Force a relocation for a branch 20 bits wide. */
27888 fixP->fx_done = 0;
27889 }
08f10d51 27890 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
2fc8bdac
ZW
27891 as_bad_where (fixP->fx_file, fixP->fx_line,
27892 _("conditional branch out of range"));
404ff6b5 27893
2fc8bdac
ZW
27894 if (fixP->fx_done || !seg->use_rela_p)
27895 {
27896 offsetT newval2;
27897 addressT S, J1, J2, lo, hi;
404ff6b5 27898
2fc8bdac
ZW
27899 S = (value & 0x00100000) >> 20;
27900 J2 = (value & 0x00080000) >> 19;
27901 J1 = (value & 0x00040000) >> 18;
27902 hi = (value & 0x0003f000) >> 12;
27903 lo = (value & 0x00000ffe) >> 1;
6c43fab6 27904
2fc8bdac
ZW
27905 newval = md_chars_to_number (buf, THUMB_SIZE);
27906 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27907 newval |= (S << 10) | hi;
27908 newval2 |= (J1 << 13) | (J2 << 11) | lo;
27909 md_number_to_chars (buf, newval, THUMB_SIZE);
27910 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
27911 }
c19d1205 27912 break;
6c43fab6 27913
c19d1205 27914 case BFD_RELOC_THUMB_PCREL_BLX:
267bf995
RR
27915 /* If there is a blx from a thumb state function to
27916 another thumb function flip this to a bl and warn
27917 about it. */
27918
27919 if (fixP->fx_addsy
34e77a92 27920 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR
27921 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27922 && THUMB_IS_FUNC (fixP->fx_addsy))
27923 {
27924 const char *name = S_GET_NAME (fixP->fx_addsy);
27925 as_warn_where (fixP->fx_file, fixP->fx_line,
27926 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
27927 name);
27928 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27929 newval = newval | 0x1000;
27930 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
27931 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
27932 fixP->fx_done = 1;
27933 }
27934
27935
27936 goto thumb_bl_common;
27937
c19d1205 27938 case BFD_RELOC_THUMB_PCREL_BRANCH23:
267bf995
RR
27939 /* A bl from Thumb state ISA to an internal ARM state function
27940 is converted to a blx. */
27941 if (fixP->fx_addsy
27942 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 27943 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR
27944 && ARM_IS_FUNC (fixP->fx_addsy)
27945 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27946 {
27947 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27948 newval = newval & ~0x1000;
27949 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
27950 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
27951 fixP->fx_done = 1;
27952 }
27953
27954 thumb_bl_common:
27955
2fc8bdac
ZW
27956 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
27957 /* For a BLX instruction, make sure that the relocation is rounded up
27958 to a word boundary. This follows the semantics of the instruction
27959 which specifies that bit 1 of the target address will come from bit
27960 1 of the base address. */
d406f3e4
JB
27961 value = (value + 3) & ~ 3;
27962
27963#ifdef OBJ_ELF
27964 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
27965 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
27966 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
27967#endif
404ff6b5 27968
2b2f5df9
NC
27969 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
27970 {
fc289b0a 27971 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)))
2b2f5df9
NC
27972 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
27973 else if ((value & ~0x1ffffff)
27974 && ((value & ~0x1ffffff) != ~0x1ffffff))
27975 as_bad_where (fixP->fx_file, fixP->fx_line,
27976 _("Thumb2 branch out of range"));
27977 }
4a42ebbc
RR
27978
27979 if (fixP->fx_done || !seg->use_rela_p)
27980 encode_thumb2_b_bl_offset (buf, value);
27981
c19d1205 27982 break;
404ff6b5 27983
c19d1205 27984 case BFD_RELOC_THUMB_PCREL_BRANCH25:
08f10d51
NC
27985 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
27986 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
6c43fab6 27987
2fc8bdac 27988 if (fixP->fx_done || !seg->use_rela_p)
4a42ebbc 27989 encode_thumb2_b_bl_offset (buf, value);
6c43fab6 27990
2fc8bdac 27991 break;
a737bd4d 27992
2fc8bdac
ZW
27993 case BFD_RELOC_8:
27994 if (fixP->fx_done || !seg->use_rela_p)
4b1a927e 27995 *buf = value;
c19d1205 27996 break;
a737bd4d 27997
c19d1205 27998 case BFD_RELOC_16:
2fc8bdac 27999 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 28000 md_number_to_chars (buf, value, 2);
c19d1205 28001 break;
a737bd4d 28002
c19d1205 28003#ifdef OBJ_ELF
0855e32b
NS
28004 case BFD_RELOC_ARM_TLS_CALL:
28005 case BFD_RELOC_ARM_THM_TLS_CALL:
28006 case BFD_RELOC_ARM_TLS_DESCSEQ:
28007 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
0855e32b 28008 case BFD_RELOC_ARM_TLS_GOTDESC:
c19d1205
ZW
28009 case BFD_RELOC_ARM_TLS_GD32:
28010 case BFD_RELOC_ARM_TLS_LE32:
28011 case BFD_RELOC_ARM_TLS_IE32:
28012 case BFD_RELOC_ARM_TLS_LDM32:
28013 case BFD_RELOC_ARM_TLS_LDO32:
28014 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4b1a927e 28015 break;
6c43fab6 28016
5c5a4843
CL
28017 /* Same handling as above, but with the arm_fdpic guard. */
28018 case BFD_RELOC_ARM_TLS_GD32_FDPIC:
28019 case BFD_RELOC_ARM_TLS_IE32_FDPIC:
28020 case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
28021 if (arm_fdpic)
28022 {
28023 S_SET_THREAD_LOCAL (fixP->fx_addsy);
28024 }
28025 else
28026 {
28027 as_bad_where (fixP->fx_file, fixP->fx_line,
28028 _("Relocation supported only in FDPIC mode"));
28029 }
28030 break;
28031
c19d1205
ZW
28032 case BFD_RELOC_ARM_GOT32:
28033 case BFD_RELOC_ARM_GOTOFF:
c19d1205 28034 break;
b43420e6
NC
28035
28036 case BFD_RELOC_ARM_GOT_PREL:
28037 if (fixP->fx_done || !seg->use_rela_p)
477330fc 28038 md_number_to_chars (buf, value, 4);
b43420e6
NC
28039 break;
28040
9a6f4e97
NS
28041 case BFD_RELOC_ARM_TARGET2:
28042 /* TARGET2 is not partial-inplace, so we need to write the
477330fc
RM
28043 addend here for REL targets, because it won't be written out
28044 during reloc processing later. */
9a6f4e97
NS
28045 if (fixP->fx_done || !seg->use_rela_p)
28046 md_number_to_chars (buf, fixP->fx_offset, 4);
28047 break;
188fd7ae
CL
28048
28049 /* Relocations for FDPIC. */
28050 case BFD_RELOC_ARM_GOTFUNCDESC:
28051 case BFD_RELOC_ARM_GOTOFFFUNCDESC:
28052 case BFD_RELOC_ARM_FUNCDESC:
28053 if (arm_fdpic)
28054 {
28055 if (fixP->fx_done || !seg->use_rela_p)
28056 md_number_to_chars (buf, 0, 4);
28057 }
28058 else
28059 {
28060 as_bad_where (fixP->fx_file, fixP->fx_line,
28061 _("Relocation supported only in FDPIC mode"));
28062 }
28063 break;
c19d1205 28064#endif
6c43fab6 28065
c19d1205
ZW
28066 case BFD_RELOC_RVA:
28067 case BFD_RELOC_32:
28068 case BFD_RELOC_ARM_TARGET1:
28069 case BFD_RELOC_ARM_ROSEGREL32:
28070 case BFD_RELOC_ARM_SBREL32:
28071 case BFD_RELOC_32_PCREL:
f0927246
NC
28072#ifdef TE_PE
28073 case BFD_RELOC_32_SECREL:
28074#endif
2fc8bdac 28075 if (fixP->fx_done || !seg->use_rela_p)
53baae48
NC
28076#ifdef TE_WINCE
28077 /* For WinCE we only do this for pcrel fixups. */
28078 if (fixP->fx_done || fixP->fx_pcrel)
28079#endif
28080 md_number_to_chars (buf, value, 4);
c19d1205 28081 break;
6c43fab6 28082
c19d1205
ZW
28083#ifdef OBJ_ELF
28084 case BFD_RELOC_ARM_PREL31:
2fc8bdac 28085 if (fixP->fx_done || !seg->use_rela_p)
c19d1205
ZW
28086 {
28087 newval = md_chars_to_number (buf, 4) & 0x80000000;
28088 if ((value ^ (value >> 1)) & 0x40000000)
28089 {
28090 as_bad_where (fixP->fx_file, fixP->fx_line,
28091 _("rel31 relocation overflow"));
28092 }
28093 newval |= value & 0x7fffffff;
28094 md_number_to_chars (buf, newval, 4);
28095 }
28096 break;
c19d1205 28097#endif
a737bd4d 28098
c19d1205 28099 case BFD_RELOC_ARM_CP_OFF_IMM:
8f06b2d8 28100 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
32c36c3c 28101 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM:
9db2f6b4
RL
28102 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM)
28103 newval = md_chars_to_number (buf, INSN_SIZE);
28104 else
28105 newval = get_thumb32_insn (buf);
28106 if ((newval & 0x0f200f00) == 0x0d000900)
28107 {
28108 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
28109 has permitted values that are multiples of 2, in the range 0
28110 to 510. */
28111 if (value < -510 || value > 510 || (value & 1))
28112 as_bad_where (fixP->fx_file, fixP->fx_line,
28113 _("co-processor offset out of range"));
28114 }
32c36c3c
AV
28115 else if ((newval & 0xfe001f80) == 0xec000f80)
28116 {
28117 if (value < -511 || value > 512 || (value & 3))
28118 as_bad_where (fixP->fx_file, fixP->fx_line,
28119 _("co-processor offset out of range"));
28120 }
9db2f6b4 28121 else if (value < -1023 || value > 1023 || (value & 3))
c19d1205
ZW
28122 as_bad_where (fixP->fx_file, fixP->fx_line,
28123 _("co-processor offset out of range"));
28124 cp_off_common:
26d97720 28125 sign = value > 0;
c19d1205
ZW
28126 if (value < 0)
28127 value = -value;
8f06b2d8
PB
28128 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
28129 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
28130 newval = md_chars_to_number (buf, INSN_SIZE);
28131 else
28132 newval = get_thumb32_insn (buf);
26d97720 28133 if (value == 0)
32c36c3c
AV
28134 {
28135 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
28136 newval &= 0xffffff80;
28137 else
28138 newval &= 0xffffff00;
28139 }
26d97720
NS
28140 else
28141 {
32c36c3c
AV
28142 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
28143 newval &= 0xff7fff80;
28144 else
28145 newval &= 0xff7fff00;
9db2f6b4
RL
28146 if ((newval & 0x0f200f00) == 0x0d000900)
28147 {
28148 /* This is a fp16 vstr/vldr.
28149
28150 It requires the immediate offset in the instruction is shifted
28151 left by 1 to be a half-word offset.
28152
28153 Here, left shift by 1 first, and later right shift by 2
28154 should get the right offset. */
28155 value <<= 1;
28156 }
26d97720
NS
28157 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
28158 }
8f06b2d8
PB
28159 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
28160 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
28161 md_number_to_chars (buf, newval, INSN_SIZE);
28162 else
28163 put_thumb32_insn (buf, newval);
c19d1205 28164 break;
a737bd4d 28165
c19d1205 28166 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
8f06b2d8 28167 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
c19d1205
ZW
28168 if (value < -255 || value > 255)
28169 as_bad_where (fixP->fx_file, fixP->fx_line,
28170 _("co-processor offset out of range"));
df7849c5 28171 value *= 4;
c19d1205 28172 goto cp_off_common;
6c43fab6 28173
c19d1205
ZW
28174 case BFD_RELOC_ARM_THUMB_OFFSET:
28175 newval = md_chars_to_number (buf, THUMB_SIZE);
28176 /* Exactly what ranges, and where the offset is inserted depends
28177 on the type of instruction, we can establish this from the
28178 top 4 bits. */
28179 switch (newval >> 12)
28180 {
28181 case 4: /* PC load. */
28182 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
28183 forced to zero for these loads; md_pcrel_from has already
28184 compensated for this. */
28185 if (value & 3)
28186 as_bad_where (fixP->fx_file, fixP->fx_line,
28187 _("invalid offset, target not word aligned (0x%08lX)"),
0359e808
NC
28188 (((unsigned long) fixP->fx_frag->fr_address
28189 + (unsigned long) fixP->fx_where) & ~3)
28190 + (unsigned long) value);
a737bd4d 28191
c19d1205
ZW
28192 if (value & ~0x3fc)
28193 as_bad_where (fixP->fx_file, fixP->fx_line,
28194 _("invalid offset, value too big (0x%08lX)"),
28195 (long) value);
a737bd4d 28196
c19d1205
ZW
28197 newval |= value >> 2;
28198 break;
a737bd4d 28199
c19d1205
ZW
28200 case 9: /* SP load/store. */
28201 if (value & ~0x3fc)
28202 as_bad_where (fixP->fx_file, fixP->fx_line,
28203 _("invalid offset, value too big (0x%08lX)"),
28204 (long) value);
28205 newval |= value >> 2;
28206 break;
6c43fab6 28207
c19d1205
ZW
28208 case 6: /* Word load/store. */
28209 if (value & ~0x7c)
28210 as_bad_where (fixP->fx_file, fixP->fx_line,
28211 _("invalid offset, value too big (0x%08lX)"),
28212 (long) value);
28213 newval |= value << 4; /* 6 - 2. */
28214 break;
a737bd4d 28215
c19d1205
ZW
28216 case 7: /* Byte load/store. */
28217 if (value & ~0x1f)
28218 as_bad_where (fixP->fx_file, fixP->fx_line,
28219 _("invalid offset, value too big (0x%08lX)"),
28220 (long) value);
28221 newval |= value << 6;
28222 break;
a737bd4d 28223
c19d1205
ZW
28224 case 8: /* Halfword load/store. */
28225 if (value & ~0x3e)
28226 as_bad_where (fixP->fx_file, fixP->fx_line,
28227 _("invalid offset, value too big (0x%08lX)"),
28228 (long) value);
28229 newval |= value << 5; /* 6 - 1. */
28230 break;
a737bd4d 28231
c19d1205
ZW
28232 default:
28233 as_bad_where (fixP->fx_file, fixP->fx_line,
28234 "Unable to process relocation for thumb opcode: %lx",
28235 (unsigned long) newval);
28236 break;
28237 }
28238 md_number_to_chars (buf, newval, THUMB_SIZE);
28239 break;
a737bd4d 28240
c19d1205
ZW
28241 case BFD_RELOC_ARM_THUMB_ADD:
28242 /* This is a complicated relocation, since we use it for all of
28243 the following immediate relocations:
a737bd4d 28244
c19d1205
ZW
28245 3bit ADD/SUB
28246 8bit ADD/SUB
28247 9bit ADD/SUB SP word-aligned
28248 10bit ADD PC/SP word-aligned
a737bd4d 28249
c19d1205
ZW
28250 The type of instruction being processed is encoded in the
28251 instruction field:
a737bd4d 28252
c19d1205
ZW
28253 0x8000 SUB
28254 0x00F0 Rd
28255 0x000F Rs
28256 */
28257 newval = md_chars_to_number (buf, THUMB_SIZE);
28258 {
28259 int rd = (newval >> 4) & 0xf;
28260 int rs = newval & 0xf;
28261 int subtract = !!(newval & 0x8000);
a737bd4d 28262
c19d1205
ZW
28263 /* Check for HI regs, only very restricted cases allowed:
28264 Adjusting SP, and using PC or SP to get an address. */
28265 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
28266 || (rs > 7 && rs != REG_SP && rs != REG_PC))
28267 as_bad_where (fixP->fx_file, fixP->fx_line,
28268 _("invalid Hi register with immediate"));
a737bd4d 28269
c19d1205
ZW
28270 /* If value is negative, choose the opposite instruction. */
28271 if (value < 0)
28272 {
28273 value = -value;
28274 subtract = !subtract;
28275 if (value < 0)
28276 as_bad_where (fixP->fx_file, fixP->fx_line,
28277 _("immediate value out of range"));
28278 }
a737bd4d 28279
c19d1205
ZW
28280 if (rd == REG_SP)
28281 {
75c11999 28282 if (value & ~0x1fc)
c19d1205
ZW
28283 as_bad_where (fixP->fx_file, fixP->fx_line,
28284 _("invalid immediate for stack address calculation"));
28285 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
28286 newval |= value >> 2;
28287 }
28288 else if (rs == REG_PC || rs == REG_SP)
28289 {
c12d2c9d
NC
28290 /* PR gas/18541. If the addition is for a defined symbol
28291 within range of an ADR instruction then accept it. */
28292 if (subtract
28293 && value == 4
28294 && fixP->fx_addsy != NULL)
28295 {
28296 subtract = 0;
28297
28298 if (! S_IS_DEFINED (fixP->fx_addsy)
28299 || S_GET_SEGMENT (fixP->fx_addsy) != seg
28300 || S_IS_WEAK (fixP->fx_addsy))
28301 {
28302 as_bad_where (fixP->fx_file, fixP->fx_line,
28303 _("address calculation needs a strongly defined nearby symbol"));
28304 }
28305 else
28306 {
28307 offsetT v = fixP->fx_where + fixP->fx_frag->fr_address;
28308
28309 /* Round up to the next 4-byte boundary. */
28310 if (v & 3)
28311 v = (v + 3) & ~ 3;
28312 else
28313 v += 4;
28314 v = S_GET_VALUE (fixP->fx_addsy) - v;
28315
28316 if (v & ~0x3fc)
28317 {
28318 as_bad_where (fixP->fx_file, fixP->fx_line,
28319 _("symbol too far away"));
28320 }
28321 else
28322 {
28323 fixP->fx_done = 1;
28324 value = v;
28325 }
28326 }
28327 }
28328
c19d1205
ZW
28329 if (subtract || value & ~0x3fc)
28330 as_bad_where (fixP->fx_file, fixP->fx_line,
28331 _("invalid immediate for address calculation (value = 0x%08lX)"),
5fc177c8 28332 (unsigned long) (subtract ? - value : value));
c19d1205
ZW
28333 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
28334 newval |= rd << 8;
28335 newval |= value >> 2;
28336 }
28337 else if (rs == rd)
28338 {
28339 if (value & ~0xff)
28340 as_bad_where (fixP->fx_file, fixP->fx_line,
28341 _("immediate value out of range"));
28342 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
28343 newval |= (rd << 8) | value;
28344 }
28345 else
28346 {
28347 if (value & ~0x7)
28348 as_bad_where (fixP->fx_file, fixP->fx_line,
28349 _("immediate value out of range"));
28350 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
28351 newval |= rd | (rs << 3) | (value << 6);
28352 }
28353 }
28354 md_number_to_chars (buf, newval, THUMB_SIZE);
28355 break;
a737bd4d 28356
c19d1205
ZW
28357 case BFD_RELOC_ARM_THUMB_IMM:
28358 newval = md_chars_to_number (buf, THUMB_SIZE);
28359 if (value < 0 || value > 255)
28360 as_bad_where (fixP->fx_file, fixP->fx_line,
4e6e072b 28361 _("invalid immediate: %ld is out of range"),
c19d1205
ZW
28362 (long) value);
28363 newval |= value;
28364 md_number_to_chars (buf, newval, THUMB_SIZE);
28365 break;
a737bd4d 28366
c19d1205
ZW
28367 case BFD_RELOC_ARM_THUMB_SHIFT:
28368 /* 5bit shift value (0..32). LSL cannot take 32. */
28369 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
28370 temp = newval & 0xf800;
28371 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
28372 as_bad_where (fixP->fx_file, fixP->fx_line,
28373 _("invalid shift value: %ld"), (long) value);
28374 /* Shifts of zero must be encoded as LSL. */
28375 if (value == 0)
28376 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
28377 /* Shifts of 32 are encoded as zero. */
28378 else if (value == 32)
28379 value = 0;
28380 newval |= value << 6;
28381 md_number_to_chars (buf, newval, THUMB_SIZE);
28382 break;
a737bd4d 28383
c19d1205
ZW
28384 case BFD_RELOC_VTABLE_INHERIT:
28385 case BFD_RELOC_VTABLE_ENTRY:
28386 fixP->fx_done = 0;
28387 return;
6c43fab6 28388
b6895b4f
PB
28389 case BFD_RELOC_ARM_MOVW:
28390 case BFD_RELOC_ARM_MOVT:
28391 case BFD_RELOC_ARM_THUMB_MOVW:
28392 case BFD_RELOC_ARM_THUMB_MOVT:
28393 if (fixP->fx_done || !seg->use_rela_p)
28394 {
28395 /* REL format relocations are limited to a 16-bit addend. */
28396 if (!fixP->fx_done)
28397 {
39623e12 28398 if (value < -0x8000 || value > 0x7fff)
b6895b4f 28399 as_bad_where (fixP->fx_file, fixP->fx_line,
ff5075ca 28400 _("offset out of range"));
b6895b4f
PB
28401 }
28402 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
28403 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
28404 {
28405 value >>= 16;
28406 }
28407
28408 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
28409 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
28410 {
28411 newval = get_thumb32_insn (buf);
28412 newval &= 0xfbf08f00;
28413 newval |= (value & 0xf000) << 4;
28414 newval |= (value & 0x0800) << 15;
28415 newval |= (value & 0x0700) << 4;
28416 newval |= (value & 0x00ff);
28417 put_thumb32_insn (buf, newval);
28418 }
28419 else
28420 {
28421 newval = md_chars_to_number (buf, 4);
28422 newval &= 0xfff0f000;
28423 newval |= value & 0x0fff;
28424 newval |= (value & 0xf000) << 4;
28425 md_number_to_chars (buf, newval, 4);
28426 }
28427 }
28428 return;
28429
72d98d16
MG
28430 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
28431 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
28432 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
28433 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
28434 gas_assert (!fixP->fx_done);
28435 {
28436 bfd_vma insn;
28437 bfd_boolean is_mov;
28438 bfd_vma encoded_addend = value;
28439
28440 /* Check that addend can be encoded in instruction. */
28441 if (!seg->use_rela_p && (value < 0 || value > 255))
28442 as_bad_where (fixP->fx_file, fixP->fx_line,
28443 _("the offset 0x%08lX is not representable"),
28444 (unsigned long) encoded_addend);
28445
28446 /* Extract the instruction. */
28447 insn = md_chars_to_number (buf, THUMB_SIZE);
28448 is_mov = (insn & 0xf800) == 0x2000;
28449
28450 /* Encode insn. */
28451 if (is_mov)
28452 {
28453 if (!seg->use_rela_p)
28454 insn |= encoded_addend;
28455 }
28456 else
28457 {
28458 int rd, rs;
28459
28460 /* Extract the instruction. */
28461 /* Encoding is the following
28462 0x8000 SUB
28463 0x00F0 Rd
28464 0x000F Rs
28465 */
28466 /* The following conditions must be true :
28467 - ADD
28468 - Rd == Rs
28469 - Rd <= 7
28470 */
28471 rd = (insn >> 4) & 0xf;
28472 rs = insn & 0xf;
28473 if ((insn & 0x8000) || (rd != rs) || rd > 7)
28474 as_bad_where (fixP->fx_file, fixP->fx_line,
28475 _("Unable to process relocation for thumb opcode: %lx"),
28476 (unsigned long) insn);
28477
28478 /* Encode as ADD immediate8 thumb 1 code. */
28479 insn = 0x3000 | (rd << 8);
28480
28481 /* Place the encoded addend into the first 8 bits of the
28482 instruction. */
28483 if (!seg->use_rela_p)
28484 insn |= encoded_addend;
28485 }
28486
28487 /* Update the instruction. */
28488 md_number_to_chars (buf, insn, THUMB_SIZE);
28489 }
28490 break;
28491
4962c51a
MS
28492 case BFD_RELOC_ARM_ALU_PC_G0_NC:
28493 case BFD_RELOC_ARM_ALU_PC_G0:
28494 case BFD_RELOC_ARM_ALU_PC_G1_NC:
28495 case BFD_RELOC_ARM_ALU_PC_G1:
28496 case BFD_RELOC_ARM_ALU_PC_G2:
28497 case BFD_RELOC_ARM_ALU_SB_G0_NC:
28498 case BFD_RELOC_ARM_ALU_SB_G0:
28499 case BFD_RELOC_ARM_ALU_SB_G1_NC:
28500 case BFD_RELOC_ARM_ALU_SB_G1:
28501 case BFD_RELOC_ARM_ALU_SB_G2:
9c2799c2 28502 gas_assert (!fixP->fx_done);
4962c51a
MS
28503 if (!seg->use_rela_p)
28504 {
477330fc
RM
28505 bfd_vma insn;
28506 bfd_vma encoded_addend;
3ca4a8ec 28507 bfd_vma addend_abs = llabs (value);
477330fc
RM
28508
28509 /* Check that the absolute value of the addend can be
28510 expressed as an 8-bit constant plus a rotation. */
28511 encoded_addend = encode_arm_immediate (addend_abs);
28512 if (encoded_addend == (unsigned int) FAIL)
4962c51a 28513 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM
28514 _("the offset 0x%08lX is not representable"),
28515 (unsigned long) addend_abs);
28516
28517 /* Extract the instruction. */
28518 insn = md_chars_to_number (buf, INSN_SIZE);
28519
28520 /* If the addend is positive, use an ADD instruction.
28521 Otherwise use a SUB. Take care not to destroy the S bit. */
28522 insn &= 0xff1fffff;
28523 if (value < 0)
28524 insn |= 1 << 22;
28525 else
28526 insn |= 1 << 23;
28527
28528 /* Place the encoded addend into the first 12 bits of the
28529 instruction. */
28530 insn &= 0xfffff000;
28531 insn |= encoded_addend;
28532
28533 /* Update the instruction. */
28534 md_number_to_chars (buf, insn, INSN_SIZE);
4962c51a
MS
28535 }
28536 break;
28537
28538 case BFD_RELOC_ARM_LDR_PC_G0:
28539 case BFD_RELOC_ARM_LDR_PC_G1:
28540 case BFD_RELOC_ARM_LDR_PC_G2:
28541 case BFD_RELOC_ARM_LDR_SB_G0:
28542 case BFD_RELOC_ARM_LDR_SB_G1:
28543 case BFD_RELOC_ARM_LDR_SB_G2:
9c2799c2 28544 gas_assert (!fixP->fx_done);
4962c51a 28545 if (!seg->use_rela_p)
477330fc
RM
28546 {
28547 bfd_vma insn;
3ca4a8ec 28548 bfd_vma addend_abs = llabs (value);
4962c51a 28549
477330fc
RM
28550 /* Check that the absolute value of the addend can be
28551 encoded in 12 bits. */
28552 if (addend_abs >= 0x1000)
4962c51a 28553 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM
28554 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
28555 (unsigned long) addend_abs);
28556
28557 /* Extract the instruction. */
28558 insn = md_chars_to_number (buf, INSN_SIZE);
28559
28560 /* If the addend is negative, clear bit 23 of the instruction.
28561 Otherwise set it. */
28562 if (value < 0)
28563 insn &= ~(1 << 23);
28564 else
28565 insn |= 1 << 23;
28566
28567 /* Place the absolute value of the addend into the first 12 bits
28568 of the instruction. */
28569 insn &= 0xfffff000;
28570 insn |= addend_abs;
28571
28572 /* Update the instruction. */
28573 md_number_to_chars (buf, insn, INSN_SIZE);
28574 }
4962c51a
MS
28575 break;
28576
28577 case BFD_RELOC_ARM_LDRS_PC_G0:
28578 case BFD_RELOC_ARM_LDRS_PC_G1:
28579 case BFD_RELOC_ARM_LDRS_PC_G2:
28580 case BFD_RELOC_ARM_LDRS_SB_G0:
28581 case BFD_RELOC_ARM_LDRS_SB_G1:
28582 case BFD_RELOC_ARM_LDRS_SB_G2:
9c2799c2 28583 gas_assert (!fixP->fx_done);
4962c51a 28584 if (!seg->use_rela_p)
477330fc
RM
28585 {
28586 bfd_vma insn;
3ca4a8ec 28587 bfd_vma addend_abs = llabs (value);
4962c51a 28588
477330fc
RM
28589 /* Check that the absolute value of the addend can be
28590 encoded in 8 bits. */
28591 if (addend_abs >= 0x100)
4962c51a 28592 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM
28593 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
28594 (unsigned long) addend_abs);
28595
28596 /* Extract the instruction. */
28597 insn = md_chars_to_number (buf, INSN_SIZE);
28598
28599 /* If the addend is negative, clear bit 23 of the instruction.
28600 Otherwise set it. */
28601 if (value < 0)
28602 insn &= ~(1 << 23);
28603 else
28604 insn |= 1 << 23;
28605
28606 /* Place the first four bits of the absolute value of the addend
28607 into the first 4 bits of the instruction, and the remaining
28608 four into bits 8 .. 11. */
28609 insn &= 0xfffff0f0;
28610 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
28611
28612 /* Update the instruction. */
28613 md_number_to_chars (buf, insn, INSN_SIZE);
28614 }
4962c51a
MS
28615 break;
28616
28617 case BFD_RELOC_ARM_LDC_PC_G0:
28618 case BFD_RELOC_ARM_LDC_PC_G1:
28619 case BFD_RELOC_ARM_LDC_PC_G2:
28620 case BFD_RELOC_ARM_LDC_SB_G0:
28621 case BFD_RELOC_ARM_LDC_SB_G1:
28622 case BFD_RELOC_ARM_LDC_SB_G2:
9c2799c2 28623 gas_assert (!fixP->fx_done);
4962c51a 28624 if (!seg->use_rela_p)
477330fc
RM
28625 {
28626 bfd_vma insn;
3ca4a8ec 28627 bfd_vma addend_abs = llabs (value);
4962c51a 28628
477330fc
RM
28629 /* Check that the absolute value of the addend is a multiple of
28630 four and, when divided by four, fits in 8 bits. */
28631 if (addend_abs & 0x3)
4962c51a 28632 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM
28633 _("bad offset 0x%08lX (must be word-aligned)"),
28634 (unsigned long) addend_abs);
4962c51a 28635
477330fc 28636 if ((addend_abs >> 2) > 0xff)
4962c51a 28637 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM
28638 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
28639 (unsigned long) addend_abs);
28640
28641 /* Extract the instruction. */
28642 insn = md_chars_to_number (buf, INSN_SIZE);
28643
28644 /* If the addend is negative, clear bit 23 of the instruction.
28645 Otherwise set it. */
28646 if (value < 0)
28647 insn &= ~(1 << 23);
28648 else
28649 insn |= 1 << 23;
28650
28651 /* Place the addend (divided by four) into the first eight
28652 bits of the instruction. */
28653 insn &= 0xfffffff0;
28654 insn |= addend_abs >> 2;
28655
28656 /* Update the instruction. */
28657 md_number_to_chars (buf, insn, INSN_SIZE);
28658 }
4962c51a
MS
28659 break;
28660
e12437dc
AV
28661 case BFD_RELOC_THUMB_PCREL_BRANCH5:
28662 if (fixP->fx_addsy
28663 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28664 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28665 && ARM_IS_FUNC (fixP->fx_addsy)
28666 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28667 {
28668 /* Force a relocation for a branch 5 bits wide. */
28669 fixP->fx_done = 0;
28670 }
28671 if (v8_1_branch_value_check (value, 5, FALSE) == FAIL)
28672 as_bad_where (fixP->fx_file, fixP->fx_line,
28673 BAD_BRANCH_OFF);
28674
28675 if (fixP->fx_done || !seg->use_rela_p)
28676 {
28677 addressT boff = value >> 1;
28678
28679 newval = md_chars_to_number (buf, THUMB_SIZE);
28680 newval |= (boff << 7);
28681 md_number_to_chars (buf, newval, THUMB_SIZE);
28682 }
28683 break;
28684
f6b2b12d
AV
28685 case BFD_RELOC_THUMB_PCREL_BFCSEL:
28686 if (fixP->fx_addsy
28687 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28688 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28689 && ARM_IS_FUNC (fixP->fx_addsy)
28690 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28691 {
28692 fixP->fx_done = 0;
28693 }
28694 if ((value & ~0x7f) && ((value & ~0x3f) != ~0x3f))
28695 as_bad_where (fixP->fx_file, fixP->fx_line,
28696 _("branch out of range"));
28697
28698 if (fixP->fx_done || !seg->use_rela_p)
28699 {
28700 newval = md_chars_to_number (buf, THUMB_SIZE);
28701
28702 addressT boff = ((newval & 0x0780) >> 7) << 1;
28703 addressT diff = value - boff;
28704
28705 if (diff == 4)
28706 {
28707 newval |= 1 << 1; /* T bit. */
28708 }
28709 else if (diff != 2)
28710 {
28711 as_bad_where (fixP->fx_file, fixP->fx_line,
28712 _("out of range label-relative fixup value"));
28713 }
28714 md_number_to_chars (buf, newval, THUMB_SIZE);
28715 }
28716 break;
28717
e5d6e09e
AV
28718 case BFD_RELOC_ARM_THUMB_BF17:
28719 if (fixP->fx_addsy
28720 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28721 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28722 && ARM_IS_FUNC (fixP->fx_addsy)
28723 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28724 {
28725 /* Force a relocation for a branch 17 bits wide. */
28726 fixP->fx_done = 0;
28727 }
28728
28729 if (v8_1_branch_value_check (value, 17, TRUE) == FAIL)
28730 as_bad_where (fixP->fx_file, fixP->fx_line,
28731 BAD_BRANCH_OFF);
28732
28733 if (fixP->fx_done || !seg->use_rela_p)
28734 {
28735 offsetT newval2;
28736 addressT immA, immB, immC;
28737
28738 immA = (value & 0x0001f000) >> 12;
28739 immB = (value & 0x00000ffc) >> 2;
28740 immC = (value & 0x00000002) >> 1;
28741
28742 newval = md_chars_to_number (buf, THUMB_SIZE);
28743 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28744 newval |= immA;
28745 newval2 |= (immC << 11) | (immB << 1);
28746 md_number_to_chars (buf, newval, THUMB_SIZE);
28747 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
28748 }
28749 break;
28750
1caf72a5
AV
28751 case BFD_RELOC_ARM_THUMB_BF19:
28752 if (fixP->fx_addsy
28753 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28754 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28755 && ARM_IS_FUNC (fixP->fx_addsy)
28756 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28757 {
28758 /* Force a relocation for a branch 19 bits wide. */
28759 fixP->fx_done = 0;
28760 }
28761
28762 if (v8_1_branch_value_check (value, 19, TRUE) == FAIL)
28763 as_bad_where (fixP->fx_file, fixP->fx_line,
28764 BAD_BRANCH_OFF);
28765
28766 if (fixP->fx_done || !seg->use_rela_p)
28767 {
28768 offsetT newval2;
28769 addressT immA, immB, immC;
28770
28771 immA = (value & 0x0007f000) >> 12;
28772 immB = (value & 0x00000ffc) >> 2;
28773 immC = (value & 0x00000002) >> 1;
28774
28775 newval = md_chars_to_number (buf, THUMB_SIZE);
28776 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28777 newval |= immA;
28778 newval2 |= (immC << 11) | (immB << 1);
28779 md_number_to_chars (buf, newval, THUMB_SIZE);
28780 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
28781 }
28782 break;
28783
1889da70
AV
28784 case BFD_RELOC_ARM_THUMB_BF13:
28785 if (fixP->fx_addsy
28786 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28787 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28788 && ARM_IS_FUNC (fixP->fx_addsy)
28789 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28790 {
28791 /* Force a relocation for a branch 13 bits wide. */
28792 fixP->fx_done = 0;
28793 }
28794
28795 if (v8_1_branch_value_check (value, 13, TRUE) == FAIL)
28796 as_bad_where (fixP->fx_file, fixP->fx_line,
28797 BAD_BRANCH_OFF);
28798
28799 if (fixP->fx_done || !seg->use_rela_p)
28800 {
28801 offsetT newval2;
28802 addressT immA, immB, immC;
28803
28804 immA = (value & 0x00001000) >> 12;
28805 immB = (value & 0x00000ffc) >> 2;
28806 immC = (value & 0x00000002) >> 1;
28807
28808 newval = md_chars_to_number (buf, THUMB_SIZE);
28809 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28810 newval |= immA;
28811 newval2 |= (immC << 11) | (immB << 1);
28812 md_number_to_chars (buf, newval, THUMB_SIZE);
28813 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
28814 }
28815 break;
28816
60f993ce
AV
28817 case BFD_RELOC_ARM_THUMB_LOOP12:
28818 if (fixP->fx_addsy
28819 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28820 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28821 && ARM_IS_FUNC (fixP->fx_addsy)
28822 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28823 {
28824 /* Force a relocation for a branch 12 bits wide. */
28825 fixP->fx_done = 0;
28826 }
28827
28828 bfd_vma insn = get_thumb32_insn (buf);
1f6234a3 28829 /* le lr, <label>, le <label> or letp lr, <label> */
60f993ce 28830 if (((insn & 0xffffffff) == 0xf00fc001)
1f6234a3
AV
28831 || ((insn & 0xffffffff) == 0xf02fc001)
28832 || ((insn & 0xffffffff) == 0xf01fc001))
60f993ce
AV
28833 value = -value;
28834
28835 if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
28836 as_bad_where (fixP->fx_file, fixP->fx_line,
28837 BAD_BRANCH_OFF);
28838 if (fixP->fx_done || !seg->use_rela_p)
28839 {
28840 addressT imml, immh;
28841
28842 immh = (value & 0x00000ffc) >> 2;
28843 imml = (value & 0x00000002) >> 1;
28844
28845 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28846 newval |= (imml << 11) | (immh << 1);
28847 md_number_to_chars (buf + THUMB_SIZE, newval, THUMB_SIZE);
28848 }
28849 break;
28850
845b51d6
PB
28851 case BFD_RELOC_ARM_V4BX:
28852 /* This will need to go in the object file. */
28853 fixP->fx_done = 0;
28854 break;
28855
c19d1205
ZW
28856 case BFD_RELOC_UNUSED:
28857 default:
28858 as_bad_where (fixP->fx_file, fixP->fx_line,
28859 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
28860 }
6c43fab6
RE
28861}
28862
c19d1205
ZW
28863/* Translate internal representation of relocation info to BFD target
28864 format. */
a737bd4d 28865
c19d1205 28866arelent *
00a97672 28867tc_gen_reloc (asection *section, fixS *fixp)
a737bd4d 28868{
c19d1205
ZW
28869 arelent * reloc;
28870 bfd_reloc_code_real_type code;
a737bd4d 28871
325801bd 28872 reloc = XNEW (arelent);
a737bd4d 28873
325801bd 28874 reloc->sym_ptr_ptr = XNEW (asymbol *);
c19d1205
ZW
28875 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
28876 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
a737bd4d 28877
2fc8bdac 28878 if (fixp->fx_pcrel)
00a97672
RS
28879 {
28880 if (section->use_rela_p)
28881 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
28882 else
28883 fixp->fx_offset = reloc->address;
28884 }
c19d1205 28885 reloc->addend = fixp->fx_offset;
a737bd4d 28886
c19d1205 28887 switch (fixp->fx_r_type)
a737bd4d 28888 {
c19d1205
ZW
28889 case BFD_RELOC_8:
28890 if (fixp->fx_pcrel)
28891 {
28892 code = BFD_RELOC_8_PCREL;
28893 break;
28894 }
1a0670f3 28895 /* Fall through. */
a737bd4d 28896
c19d1205
ZW
28897 case BFD_RELOC_16:
28898 if (fixp->fx_pcrel)
28899 {
28900 code = BFD_RELOC_16_PCREL;
28901 break;
28902 }
1a0670f3 28903 /* Fall through. */
6c43fab6 28904
c19d1205
ZW
28905 case BFD_RELOC_32:
28906 if (fixp->fx_pcrel)
28907 {
28908 code = BFD_RELOC_32_PCREL;
28909 break;
28910 }
1a0670f3 28911 /* Fall through. */
a737bd4d 28912
b6895b4f
PB
28913 case BFD_RELOC_ARM_MOVW:
28914 if (fixp->fx_pcrel)
28915 {
28916 code = BFD_RELOC_ARM_MOVW_PCREL;
28917 break;
28918 }
1a0670f3 28919 /* Fall through. */
b6895b4f
PB
28920
28921 case BFD_RELOC_ARM_MOVT:
28922 if (fixp->fx_pcrel)
28923 {
28924 code = BFD_RELOC_ARM_MOVT_PCREL;
28925 break;
28926 }
1a0670f3 28927 /* Fall through. */
b6895b4f
PB
28928
28929 case BFD_RELOC_ARM_THUMB_MOVW:
28930 if (fixp->fx_pcrel)
28931 {
28932 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
28933 break;
28934 }
1a0670f3 28935 /* Fall through. */
b6895b4f
PB
28936
28937 case BFD_RELOC_ARM_THUMB_MOVT:
28938 if (fixp->fx_pcrel)
28939 {
28940 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
28941 break;
28942 }
1a0670f3 28943 /* Fall through. */
b6895b4f 28944
c19d1205
ZW
28945 case BFD_RELOC_NONE:
28946 case BFD_RELOC_ARM_PCREL_BRANCH:
28947 case BFD_RELOC_ARM_PCREL_BLX:
28948 case BFD_RELOC_RVA:
28949 case BFD_RELOC_THUMB_PCREL_BRANCH7:
28950 case BFD_RELOC_THUMB_PCREL_BRANCH9:
28951 case BFD_RELOC_THUMB_PCREL_BRANCH12:
28952 case BFD_RELOC_THUMB_PCREL_BRANCH20:
28953 case BFD_RELOC_THUMB_PCREL_BRANCH23:
28954 case BFD_RELOC_THUMB_PCREL_BRANCH25:
c19d1205
ZW
28955 case BFD_RELOC_VTABLE_ENTRY:
28956 case BFD_RELOC_VTABLE_INHERIT:
f0927246
NC
28957#ifdef TE_PE
28958 case BFD_RELOC_32_SECREL:
28959#endif
c19d1205
ZW
28960 code = fixp->fx_r_type;
28961 break;
a737bd4d 28962
00adf2d4
JB
28963 case BFD_RELOC_THUMB_PCREL_BLX:
28964#ifdef OBJ_ELF
28965 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
28966 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
28967 else
28968#endif
28969 code = BFD_RELOC_THUMB_PCREL_BLX;
28970 break;
28971
c19d1205
ZW
28972 case BFD_RELOC_ARM_LITERAL:
28973 case BFD_RELOC_ARM_HWLITERAL:
28974 /* If this is called then the a literal has
28975 been referenced across a section boundary. */
28976 as_bad_where (fixp->fx_file, fixp->fx_line,
28977 _("literal referenced across section boundary"));
28978 return NULL;
a737bd4d 28979
c19d1205 28980#ifdef OBJ_ELF
0855e32b
NS
28981 case BFD_RELOC_ARM_TLS_CALL:
28982 case BFD_RELOC_ARM_THM_TLS_CALL:
28983 case BFD_RELOC_ARM_TLS_DESCSEQ:
28984 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
c19d1205
ZW
28985 case BFD_RELOC_ARM_GOT32:
28986 case BFD_RELOC_ARM_GOTOFF:
b43420e6 28987 case BFD_RELOC_ARM_GOT_PREL:
c19d1205
ZW
28988 case BFD_RELOC_ARM_PLT32:
28989 case BFD_RELOC_ARM_TARGET1:
28990 case BFD_RELOC_ARM_ROSEGREL32:
28991 case BFD_RELOC_ARM_SBREL32:
28992 case BFD_RELOC_ARM_PREL31:
28993 case BFD_RELOC_ARM_TARGET2:
c19d1205 28994 case BFD_RELOC_ARM_TLS_LDO32:
39b41c9c
PB
28995 case BFD_RELOC_ARM_PCREL_CALL:
28996 case BFD_RELOC_ARM_PCREL_JUMP:
4962c51a
MS
28997 case BFD_RELOC_ARM_ALU_PC_G0_NC:
28998 case BFD_RELOC_ARM_ALU_PC_G0:
28999 case BFD_RELOC_ARM_ALU_PC_G1_NC:
29000 case BFD_RELOC_ARM_ALU_PC_G1:
29001 case BFD_RELOC_ARM_ALU_PC_G2:
29002 case BFD_RELOC_ARM_LDR_PC_G0:
29003 case BFD_RELOC_ARM_LDR_PC_G1:
29004 case BFD_RELOC_ARM_LDR_PC_G2:
29005 case BFD_RELOC_ARM_LDRS_PC_G0:
29006 case BFD_RELOC_ARM_LDRS_PC_G1:
29007 case BFD_RELOC_ARM_LDRS_PC_G2:
29008 case BFD_RELOC_ARM_LDC_PC_G0:
29009 case BFD_RELOC_ARM_LDC_PC_G1:
29010 case BFD_RELOC_ARM_LDC_PC_G2:
29011 case BFD_RELOC_ARM_ALU_SB_G0_NC:
29012 case BFD_RELOC_ARM_ALU_SB_G0:
29013 case BFD_RELOC_ARM_ALU_SB_G1_NC:
29014 case BFD_RELOC_ARM_ALU_SB_G1:
29015 case BFD_RELOC_ARM_ALU_SB_G2:
29016 case BFD_RELOC_ARM_LDR_SB_G0:
29017 case BFD_RELOC_ARM_LDR_SB_G1:
29018 case BFD_RELOC_ARM_LDR_SB_G2:
29019 case BFD_RELOC_ARM_LDRS_SB_G0:
29020 case BFD_RELOC_ARM_LDRS_SB_G1:
29021 case BFD_RELOC_ARM_LDRS_SB_G2:
29022 case BFD_RELOC_ARM_LDC_SB_G0:
29023 case BFD_RELOC_ARM_LDC_SB_G1:
29024 case BFD_RELOC_ARM_LDC_SB_G2:
845b51d6 29025 case BFD_RELOC_ARM_V4BX:
72d98d16
MG
29026 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
29027 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
29028 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
29029 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
188fd7ae
CL
29030 case BFD_RELOC_ARM_GOTFUNCDESC:
29031 case BFD_RELOC_ARM_GOTOFFFUNCDESC:
29032 case BFD_RELOC_ARM_FUNCDESC:
e5d6e09e 29033 case BFD_RELOC_ARM_THUMB_BF17:
1caf72a5 29034 case BFD_RELOC_ARM_THUMB_BF19:
1889da70 29035 case BFD_RELOC_ARM_THUMB_BF13:
c19d1205
ZW
29036 code = fixp->fx_r_type;
29037 break;
a737bd4d 29038
0855e32b 29039 case BFD_RELOC_ARM_TLS_GOTDESC:
c19d1205 29040 case BFD_RELOC_ARM_TLS_GD32:
5c5a4843 29041 case BFD_RELOC_ARM_TLS_GD32_FDPIC:
75c11999 29042 case BFD_RELOC_ARM_TLS_LE32:
c19d1205 29043 case BFD_RELOC_ARM_TLS_IE32:
5c5a4843 29044 case BFD_RELOC_ARM_TLS_IE32_FDPIC:
c19d1205 29045 case BFD_RELOC_ARM_TLS_LDM32:
5c5a4843 29046 case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
c19d1205
ZW
29047 /* BFD will include the symbol's address in the addend.
29048 But we don't want that, so subtract it out again here. */
29049 if (!S_IS_COMMON (fixp->fx_addsy))
29050 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
29051 code = fixp->fx_r_type;
29052 break;
29053#endif
a737bd4d 29054
c19d1205
ZW
29055 case BFD_RELOC_ARM_IMMEDIATE:
29056 as_bad_where (fixp->fx_file, fixp->fx_line,
29057 _("internal relocation (type: IMMEDIATE) not fixed up"));
29058 return NULL;
a737bd4d 29059
c19d1205
ZW
29060 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
29061 as_bad_where (fixp->fx_file, fixp->fx_line,
29062 _("ADRL used for a symbol not defined in the same file"));
29063 return NULL;
a737bd4d 29064
e12437dc 29065 case BFD_RELOC_THUMB_PCREL_BRANCH5:
f6b2b12d 29066 case BFD_RELOC_THUMB_PCREL_BFCSEL:
60f993ce 29067 case BFD_RELOC_ARM_THUMB_LOOP12:
e12437dc
AV
29068 as_bad_where (fixp->fx_file, fixp->fx_line,
29069 _("%s used for a symbol not defined in the same file"),
29070 bfd_get_reloc_code_name (fixp->fx_r_type));
29071 return NULL;
29072
c19d1205 29073 case BFD_RELOC_ARM_OFFSET_IMM:
00a97672
RS
29074 if (section->use_rela_p)
29075 {
29076 code = fixp->fx_r_type;
29077 break;
29078 }
29079
c19d1205
ZW
29080 if (fixp->fx_addsy != NULL
29081 && !S_IS_DEFINED (fixp->fx_addsy)
29082 && S_IS_LOCAL (fixp->fx_addsy))
a737bd4d 29083 {
c19d1205
ZW
29084 as_bad_where (fixp->fx_file, fixp->fx_line,
29085 _("undefined local label `%s'"),
29086 S_GET_NAME (fixp->fx_addsy));
29087 return NULL;
a737bd4d
NC
29088 }
29089
c19d1205
ZW
29090 as_bad_where (fixp->fx_file, fixp->fx_line,
29091 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
29092 return NULL;
a737bd4d 29093
c19d1205
ZW
29094 default:
29095 {
e0471c16 29096 const char * type;
6c43fab6 29097
c19d1205
ZW
29098 switch (fixp->fx_r_type)
29099 {
29100 case BFD_RELOC_NONE: type = "NONE"; break;
29101 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
29102 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
3eb17e6b 29103 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
c19d1205
ZW
29104 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
29105 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
29106 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
db187cb9 29107 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
8f06b2d8 29108 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
c19d1205
ZW
29109 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
29110 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
29111 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
29112 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
29113 default: type = _("<unknown>"); break;
29114 }
29115 as_bad_where (fixp->fx_file, fixp->fx_line,
29116 _("cannot represent %s relocation in this object file format"),
29117 type);
29118 return NULL;
29119 }
a737bd4d 29120 }
6c43fab6 29121
c19d1205
ZW
29122#ifdef OBJ_ELF
29123 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
29124 && GOT_symbol
29125 && fixp->fx_addsy == GOT_symbol)
29126 {
29127 code = BFD_RELOC_ARM_GOTPC;
29128 reloc->addend = fixp->fx_offset = reloc->address;
29129 }
29130#endif
6c43fab6 29131
c19d1205 29132 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6c43fab6 29133
c19d1205
ZW
29134 if (reloc->howto == NULL)
29135 {
29136 as_bad_where (fixp->fx_file, fixp->fx_line,
29137 _("cannot represent %s relocation in this object file format"),
29138 bfd_get_reloc_code_name (code));
29139 return NULL;
29140 }
6c43fab6 29141
c19d1205
ZW
29142 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
29143 vtable entry to be used in the relocation's section offset. */
29144 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
29145 reloc->address = fixp->fx_offset;
6c43fab6 29146
c19d1205 29147 return reloc;
6c43fab6
RE
29148}
29149
c19d1205 29150/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6c43fab6 29151
c19d1205
ZW
29152void
29153cons_fix_new_arm (fragS * frag,
29154 int where,
29155 int size,
62ebcb5c
AM
29156 expressionS * exp,
29157 bfd_reloc_code_real_type reloc)
6c43fab6 29158{
c19d1205 29159 int pcrel = 0;
6c43fab6 29160
c19d1205
ZW
29161 /* Pick a reloc.
29162 FIXME: @@ Should look at CPU word size. */
29163 switch (size)
29164 {
29165 case 1:
62ebcb5c 29166 reloc = BFD_RELOC_8;
c19d1205
ZW
29167 break;
29168 case 2:
62ebcb5c 29169 reloc = BFD_RELOC_16;
c19d1205
ZW
29170 break;
29171 case 4:
29172 default:
62ebcb5c 29173 reloc = BFD_RELOC_32;
c19d1205
ZW
29174 break;
29175 case 8:
62ebcb5c 29176 reloc = BFD_RELOC_64;
c19d1205
ZW
29177 break;
29178 }
6c43fab6 29179
f0927246
NC
29180#ifdef TE_PE
29181 if (exp->X_op == O_secrel)
29182 {
29183 exp->X_op = O_symbol;
62ebcb5c 29184 reloc = BFD_RELOC_32_SECREL;
f0927246
NC
29185 }
29186#endif
29187
62ebcb5c 29188 fix_new_exp (frag, where, size, exp, pcrel, reloc);
c19d1205 29189}
6c43fab6 29190
4343666d 29191#if defined (OBJ_COFF)
c19d1205
ZW
29192void
29193arm_validate_fix (fixS * fixP)
6c43fab6 29194{
c19d1205
ZW
29195 /* If the destination of the branch is a defined symbol which does not have
29196 the THUMB_FUNC attribute, then we must be calling a function which has
29197 the (interfacearm) attribute. We look for the Thumb entry point to that
29198 function and change the branch to refer to that function instead. */
29199 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
29200 && fixP->fx_addsy != NULL
29201 && S_IS_DEFINED (fixP->fx_addsy)
29202 && ! THUMB_IS_FUNC (fixP->fx_addsy))
6c43fab6 29203 {
c19d1205 29204 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
6c43fab6 29205 }
c19d1205
ZW
29206}
29207#endif
6c43fab6 29208
267bf995 29209
c19d1205
ZW
29210int
29211arm_force_relocation (struct fix * fixp)
29212{
29213#if defined (OBJ_COFF) && defined (TE_PE)
29214 if (fixp->fx_r_type == BFD_RELOC_RVA)
29215 return 1;
29216#endif
6c43fab6 29217
267bf995
RR
29218 /* In case we have a call or a branch to a function in ARM ISA mode from
29219 a thumb function or vice-versa force the relocation. These relocations
29220 are cleared off for some cores that might have blx and simple transformations
29221 are possible. */
29222
29223#ifdef OBJ_ELF
29224 switch (fixp->fx_r_type)
29225 {
29226 case BFD_RELOC_ARM_PCREL_JUMP:
29227 case BFD_RELOC_ARM_PCREL_CALL:
29228 case BFD_RELOC_THUMB_PCREL_BLX:
29229 if (THUMB_IS_FUNC (fixp->fx_addsy))
29230 return 1;
29231 break;
29232
29233 case BFD_RELOC_ARM_PCREL_BLX:
29234 case BFD_RELOC_THUMB_PCREL_BRANCH25:
29235 case BFD_RELOC_THUMB_PCREL_BRANCH20:
29236 case BFD_RELOC_THUMB_PCREL_BRANCH23:
29237 if (ARM_IS_FUNC (fixp->fx_addsy))
29238 return 1;
29239 break;
29240
29241 default:
29242 break;
29243 }
29244#endif
29245
b5884301
PB
29246 /* Resolve these relocations even if the symbol is extern or weak.
29247 Technically this is probably wrong due to symbol preemption.
29248 In practice these relocations do not have enough range to be useful
29249 at dynamic link time, and some code (e.g. in the Linux kernel)
29250 expects these references to be resolved. */
c19d1205
ZW
29251 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
29252 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
b5884301 29253 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
0110f2b8 29254 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
b5884301
PB
29255 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
29256 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
29257 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
16805f35 29258 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
0110f2b8
PB
29259 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
29260 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
b5884301
PB
29261 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
29262 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
29263 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
29264 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
c19d1205 29265 return 0;
a737bd4d 29266
4962c51a
MS
29267 /* Always leave these relocations for the linker. */
29268 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
29269 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
29270 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
29271 return 1;
29272
f0291e4c
PB
29273 /* Always generate relocations against function symbols. */
29274 if (fixp->fx_r_type == BFD_RELOC_32
29275 && fixp->fx_addsy
29276 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
29277 return 1;
29278
c19d1205 29279 return generic_force_reloc (fixp);
404ff6b5
AH
29280}
29281
0ffdc86c 29282#if defined (OBJ_ELF) || defined (OBJ_COFF)
e28387c3
PB
29283/* Relocations against function names must be left unadjusted,
29284 so that the linker can use this information to generate interworking
29285 stubs. The MIPS version of this function
c19d1205
ZW
29286 also prevents relocations that are mips-16 specific, but I do not
29287 know why it does this.
404ff6b5 29288
c19d1205
ZW
29289 FIXME:
29290 There is one other problem that ought to be addressed here, but
29291 which currently is not: Taking the address of a label (rather
29292 than a function) and then later jumping to that address. Such
29293 addresses also ought to have their bottom bit set (assuming that
29294 they reside in Thumb code), but at the moment they will not. */
404ff6b5 29295
c19d1205
ZW
29296bfd_boolean
29297arm_fix_adjustable (fixS * fixP)
404ff6b5 29298{
c19d1205
ZW
29299 if (fixP->fx_addsy == NULL)
29300 return 1;
404ff6b5 29301
e28387c3
PB
29302 /* Preserve relocations against symbols with function type. */
29303 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
c921be7d 29304 return FALSE;
e28387c3 29305
c19d1205
ZW
29306 if (THUMB_IS_FUNC (fixP->fx_addsy)
29307 && fixP->fx_subsy == NULL)
c921be7d 29308 return FALSE;
a737bd4d 29309
c19d1205
ZW
29310 /* We need the symbol name for the VTABLE entries. */
29311 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
29312 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
c921be7d 29313 return FALSE;
404ff6b5 29314
c19d1205
ZW
29315 /* Don't allow symbols to be discarded on GOT related relocs. */
29316 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
29317 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
29318 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
29319 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
5c5a4843 29320 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32_FDPIC
c19d1205
ZW
29321 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
29322 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
5c5a4843 29323 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32_FDPIC
c19d1205 29324 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
5c5a4843 29325 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32_FDPIC
c19d1205 29326 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
0855e32b
NS
29327 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
29328 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
29329 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
29330 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
29331 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
c19d1205 29332 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
c921be7d 29333 return FALSE;
a737bd4d 29334
4962c51a
MS
29335 /* Similarly for group relocations. */
29336 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
29337 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
29338 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
c921be7d 29339 return FALSE;
4962c51a 29340
79947c54
CD
29341 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
29342 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
29343 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
29344 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
29345 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
29346 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
29347 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
29348 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
29349 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
c921be7d 29350 return FALSE;
79947c54 29351
72d98d16
MG
29352 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
29353 offsets, so keep these symbols. */
29354 if (fixP->fx_r_type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
29355 && fixP->fx_r_type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
29356 return FALSE;
29357
c921be7d 29358 return TRUE;
a737bd4d 29359}
0ffdc86c
NC
29360#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
29361
29362#ifdef OBJ_ELF
c19d1205
ZW
29363const char *
29364elf32_arm_target_format (void)
404ff6b5 29365{
c19d1205
ZW
29366#ifdef TE_SYMBIAN
29367 return (target_big_endian
29368 ? "elf32-bigarm-symbian"
29369 : "elf32-littlearm-symbian");
29370#elif defined (TE_VXWORKS)
29371 return (target_big_endian
29372 ? "elf32-bigarm-vxworks"
29373 : "elf32-littlearm-vxworks");
b38cadfb
NC
29374#elif defined (TE_NACL)
29375 return (target_big_endian
29376 ? "elf32-bigarm-nacl"
29377 : "elf32-littlearm-nacl");
c19d1205 29378#else
18a20338
CL
29379 if (arm_fdpic)
29380 {
29381 if (target_big_endian)
29382 return "elf32-bigarm-fdpic";
29383 else
29384 return "elf32-littlearm-fdpic";
29385 }
c19d1205 29386 else
18a20338
CL
29387 {
29388 if (target_big_endian)
29389 return "elf32-bigarm";
29390 else
29391 return "elf32-littlearm";
29392 }
c19d1205 29393#endif
404ff6b5
AH
29394}
29395
c19d1205
ZW
29396void
29397armelf_frob_symbol (symbolS * symp,
29398 int * puntp)
404ff6b5 29399{
c19d1205
ZW
29400 elf_frob_symbol (symp, puntp);
29401}
29402#endif
404ff6b5 29403
c19d1205 29404/* MD interface: Finalization. */
a737bd4d 29405
c19d1205
ZW
29406void
29407arm_cleanup (void)
29408{
29409 literal_pool * pool;
a737bd4d 29410
5ee91343
AV
29411 /* Ensure that all the predication blocks are properly closed. */
29412 check_pred_blocks_finished ();
e07e6e58 29413
c19d1205
ZW
29414 for (pool = list_of_pools; pool; pool = pool->next)
29415 {
5f4273c7 29416 /* Put it at the end of the relevant section. */
c19d1205
ZW
29417 subseg_set (pool->section, pool->sub_section);
29418#ifdef OBJ_ELF
29419 arm_elf_change_section ();
29420#endif
29421 s_ltorg (0);
29422 }
404ff6b5
AH
29423}
29424
cd000bff
DJ
29425#ifdef OBJ_ELF
29426/* Remove any excess mapping symbols generated for alignment frags in
29427 SEC. We may have created a mapping symbol before a zero byte
29428 alignment; remove it if there's a mapping symbol after the
29429 alignment. */
29430static void
29431check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
29432 void *dummy ATTRIBUTE_UNUSED)
29433{
29434 segment_info_type *seginfo = seg_info (sec);
29435 fragS *fragp;
29436
29437 if (seginfo == NULL || seginfo->frchainP == NULL)
29438 return;
29439
29440 for (fragp = seginfo->frchainP->frch_root;
29441 fragp != NULL;
29442 fragp = fragp->fr_next)
29443 {
29444 symbolS *sym = fragp->tc_frag_data.last_map;
29445 fragS *next = fragp->fr_next;
29446
29447 /* Variable-sized frags have been converted to fixed size by
29448 this point. But if this was variable-sized to start with,
29449 there will be a fixed-size frag after it. So don't handle
29450 next == NULL. */
29451 if (sym == NULL || next == NULL)
29452 continue;
29453
29454 if (S_GET_VALUE (sym) < next->fr_address)
29455 /* Not at the end of this frag. */
29456 continue;
29457 know (S_GET_VALUE (sym) == next->fr_address);
29458
29459 do
29460 {
29461 if (next->tc_frag_data.first_map != NULL)
29462 {
29463 /* Next frag starts with a mapping symbol. Discard this
29464 one. */
29465 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
29466 break;
29467 }
29468
29469 if (next->fr_next == NULL)
29470 {
29471 /* This mapping symbol is at the end of the section. Discard
29472 it. */
29473 know (next->fr_fix == 0 && next->fr_var == 0);
29474 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
29475 break;
29476 }
29477
29478 /* As long as we have empty frags without any mapping symbols,
29479 keep looking. */
29480 /* If the next frag is non-empty and does not start with a
29481 mapping symbol, then this mapping symbol is required. */
29482 if (next->fr_address != next->fr_next->fr_address)
29483 break;
29484
29485 next = next->fr_next;
29486 }
29487 while (next != NULL);
29488 }
29489}
29490#endif
29491
c19d1205
ZW
29492/* Adjust the symbol table. This marks Thumb symbols as distinct from
29493 ARM ones. */
404ff6b5 29494
c19d1205
ZW
29495void
29496arm_adjust_symtab (void)
404ff6b5 29497{
c19d1205
ZW
29498#ifdef OBJ_COFF
29499 symbolS * sym;
404ff6b5 29500
c19d1205
ZW
29501 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
29502 {
29503 if (ARM_IS_THUMB (sym))
29504 {
29505 if (THUMB_IS_FUNC (sym))
29506 {
29507 /* Mark the symbol as a Thumb function. */
29508 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
29509 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
29510 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
404ff6b5 29511
c19d1205
ZW
29512 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
29513 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
29514 else
29515 as_bad (_("%s: unexpected function type: %d"),
29516 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
29517 }
29518 else switch (S_GET_STORAGE_CLASS (sym))
29519 {
29520 case C_EXT:
29521 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
29522 break;
29523 case C_STAT:
29524 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
29525 break;
29526 case C_LABEL:
29527 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
29528 break;
29529 default:
29530 /* Do nothing. */
29531 break;
29532 }
29533 }
a737bd4d 29534
c19d1205
ZW
29535 if (ARM_IS_INTERWORK (sym))
29536 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
404ff6b5 29537 }
c19d1205
ZW
29538#endif
29539#ifdef OBJ_ELF
29540 symbolS * sym;
29541 char bind;
404ff6b5 29542
c19d1205 29543 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
404ff6b5 29544 {
c19d1205
ZW
29545 if (ARM_IS_THUMB (sym))
29546 {
29547 elf_symbol_type * elf_sym;
404ff6b5 29548
c19d1205
ZW
29549 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
29550 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
404ff6b5 29551
b0796911
PB
29552 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
29553 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
c19d1205
ZW
29554 {
29555 /* If it's a .thumb_func, declare it as so,
29556 otherwise tag label as .code 16. */
29557 if (THUMB_IS_FUNC (sym))
39d911fc
TP
29558 ARM_SET_SYM_BRANCH_TYPE (elf_sym->internal_elf_sym.st_target_internal,
29559 ST_BRANCH_TO_THUMB);
3ba67470 29560 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
c19d1205
ZW
29561 elf_sym->internal_elf_sym.st_info =
29562 ELF_ST_INFO (bind, STT_ARM_16BIT);
29563 }
29564 }
29565 }
cd000bff
DJ
29566
29567 /* Remove any overlapping mapping symbols generated by alignment frags. */
29568 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
709001e9
MM
29569 /* Now do generic ELF adjustments. */
29570 elf_adjust_symtab ();
c19d1205 29571#endif
404ff6b5
AH
29572}
29573
c19d1205 29574/* MD interface: Initialization. */
404ff6b5 29575
a737bd4d 29576static void
c19d1205 29577set_constant_flonums (void)
a737bd4d 29578{
c19d1205 29579 int i;
404ff6b5 29580
c19d1205
ZW
29581 for (i = 0; i < NUM_FLOAT_VALS; i++)
29582 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
29583 abort ();
a737bd4d 29584}
404ff6b5 29585
3e9e4fcf
JB
29586/* Auto-select Thumb mode if it's the only available instruction set for the
29587 given architecture. */
29588
29589static void
29590autoselect_thumb_from_cpu_variant (void)
29591{
29592 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
29593 opcode_select (16);
29594}
29595
c19d1205
ZW
29596void
29597md_begin (void)
a737bd4d 29598{
c19d1205
ZW
29599 unsigned mach;
29600 unsigned int i;
404ff6b5 29601
c19d1205
ZW
29602 if ( (arm_ops_hsh = hash_new ()) == NULL
29603 || (arm_cond_hsh = hash_new ()) == NULL
5ee91343 29604 || (arm_vcond_hsh = hash_new ()) == NULL
c19d1205
ZW
29605 || (arm_shift_hsh = hash_new ()) == NULL
29606 || (arm_psr_hsh = hash_new ()) == NULL
62b3e311 29607 || (arm_v7m_psr_hsh = hash_new ()) == NULL
c19d1205 29608 || (arm_reg_hsh = hash_new ()) == NULL
62b3e311
PB
29609 || (arm_reloc_hsh = hash_new ()) == NULL
29610 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
c19d1205
ZW
29611 as_fatal (_("virtual memory exhausted"));
29612
29613 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
d3ce72d0 29614 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
c19d1205 29615 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
d3ce72d0 29616 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
5ee91343
AV
29617 for (i = 0; i < sizeof (vconds) / sizeof (struct asm_cond); i++)
29618 hash_insert (arm_vcond_hsh, vconds[i].template_name, (void *) (vconds + i));
c19d1205 29619 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
5a49b8ac 29620 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
c19d1205 29621 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
d3ce72d0 29622 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
62b3e311 29623 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
d3ce72d0 29624 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
477330fc 29625 (void *) (v7m_psrs + i));
c19d1205 29626 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
5a49b8ac 29627 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
62b3e311
PB
29628 for (i = 0;
29629 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
29630 i++)
d3ce72d0 29631 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
5a49b8ac 29632 (void *) (barrier_opt_names + i));
c19d1205 29633#ifdef OBJ_ELF
3da1d841
NC
29634 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
29635 {
29636 struct reloc_entry * entry = reloc_names + i;
29637
29638 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
29639 /* This makes encode_branch() use the EABI versions of this relocation. */
29640 entry->reloc = BFD_RELOC_UNUSED;
29641
29642 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
29643 }
c19d1205
ZW
29644#endif
29645
29646 set_constant_flonums ();
404ff6b5 29647
c19d1205
ZW
29648 /* Set the cpu variant based on the command-line options. We prefer
29649 -mcpu= over -march= if both are set (as for GCC); and we prefer
29650 -mfpu= over any other way of setting the floating point unit.
29651 Use of legacy options with new options are faulted. */
e74cfd16 29652 if (legacy_cpu)
404ff6b5 29653 {
e74cfd16 29654 if (mcpu_cpu_opt || march_cpu_opt)
c19d1205
ZW
29655 as_bad (_("use of old and new-style options to set CPU type"));
29656
4d354d8b 29657 selected_arch = *legacy_cpu;
404ff6b5 29658 }
4d354d8b
TP
29659 else if (mcpu_cpu_opt)
29660 {
29661 selected_arch = *mcpu_cpu_opt;
29662 selected_ext = *mcpu_ext_opt;
29663 }
29664 else if (march_cpu_opt)
c168ce07 29665 {
4d354d8b
TP
29666 selected_arch = *march_cpu_opt;
29667 selected_ext = *march_ext_opt;
c168ce07 29668 }
4d354d8b 29669 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
404ff6b5 29670
e74cfd16 29671 if (legacy_fpu)
c19d1205 29672 {
e74cfd16 29673 if (mfpu_opt)
c19d1205 29674 as_bad (_("use of old and new-style options to set FPU type"));
03b1477f 29675
4d354d8b 29676 selected_fpu = *legacy_fpu;
03b1477f 29677 }
4d354d8b
TP
29678 else if (mfpu_opt)
29679 selected_fpu = *mfpu_opt;
29680 else
03b1477f 29681 {
45eb4c1b
NS
29682#if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
29683 || defined (TE_NetBSD) || defined (TE_VXWORKS))
39c2da32
RE
29684 /* Some environments specify a default FPU. If they don't, infer it
29685 from the processor. */
e74cfd16 29686 if (mcpu_fpu_opt)
4d354d8b 29687 selected_fpu = *mcpu_fpu_opt;
e7da50fa 29688 else if (march_fpu_opt)
4d354d8b 29689 selected_fpu = *march_fpu_opt;
39c2da32 29690#else
4d354d8b 29691 selected_fpu = fpu_default;
39c2da32 29692#endif
03b1477f
RE
29693 }
29694
4d354d8b 29695 if (ARM_FEATURE_ZERO (selected_fpu))
03b1477f 29696 {
4d354d8b
TP
29697 if (!no_cpu_selected ())
29698 selected_fpu = fpu_default;
03b1477f 29699 else
4d354d8b 29700 selected_fpu = fpu_arch_fpa;
03b1477f
RE
29701 }
29702
ee065d83 29703#ifdef CPU_DEFAULT
4d354d8b 29704 if (ARM_FEATURE_ZERO (selected_arch))
ee065d83 29705 {
4d354d8b
TP
29706 selected_arch = cpu_default;
29707 selected_cpu = selected_arch;
ee065d83 29708 }
4d354d8b 29709 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
e74cfd16 29710#else
4d354d8b
TP
29711 /* Autodection of feature mode: allow all features in cpu_variant but leave
29712 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
29713 after all instruction have been processed and we can decide what CPU
29714 should be selected. */
29715 if (ARM_FEATURE_ZERO (selected_arch))
29716 ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
ee065d83 29717 else
4d354d8b 29718 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
ee065d83 29719#endif
03b1477f 29720
3e9e4fcf
JB
29721 autoselect_thumb_from_cpu_variant ();
29722
e74cfd16 29723 arm_arch_used = thumb_arch_used = arm_arch_none;
ee065d83 29724
f17c130b 29725#if defined OBJ_COFF || defined OBJ_ELF
b99bd4ef 29726 {
7cc69913
NC
29727 unsigned int flags = 0;
29728
29729#if defined OBJ_ELF
29730 flags = meabi_flags;
d507cf36
PB
29731
29732 switch (meabi_flags)
33a392fb 29733 {
d507cf36 29734 case EF_ARM_EABI_UNKNOWN:
7cc69913 29735#endif
d507cf36
PB
29736 /* Set the flags in the private structure. */
29737 if (uses_apcs_26) flags |= F_APCS26;
29738 if (support_interwork) flags |= F_INTERWORK;
29739 if (uses_apcs_float) flags |= F_APCS_FLOAT;
c19d1205 29740 if (pic_code) flags |= F_PIC;
e74cfd16 29741 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
7cc69913
NC
29742 flags |= F_SOFT_FLOAT;
29743
d507cf36
PB
29744 switch (mfloat_abi_opt)
29745 {
29746 case ARM_FLOAT_ABI_SOFT:
29747 case ARM_FLOAT_ABI_SOFTFP:
29748 flags |= F_SOFT_FLOAT;
29749 break;
33a392fb 29750
d507cf36
PB
29751 case ARM_FLOAT_ABI_HARD:
29752 if (flags & F_SOFT_FLOAT)
29753 as_bad (_("hard-float conflicts with specified fpu"));
29754 break;
29755 }
03b1477f 29756
e74cfd16
PB
29757 /* Using pure-endian doubles (even if soft-float). */
29758 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
7cc69913 29759 flags |= F_VFP_FLOAT;
f17c130b 29760
fde78edd 29761#if defined OBJ_ELF
e74cfd16 29762 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
d507cf36 29763 flags |= EF_ARM_MAVERICK_FLOAT;
d507cf36
PB
29764 break;
29765
8cb51566 29766 case EF_ARM_EABI_VER4:
3a4a14e9 29767 case EF_ARM_EABI_VER5:
c19d1205 29768 /* No additional flags to set. */
d507cf36
PB
29769 break;
29770
29771 default:
29772 abort ();
29773 }
7cc69913 29774#endif
b99bd4ef
NC
29775 bfd_set_private_flags (stdoutput, flags);
29776
29777 /* We have run out flags in the COFF header to encode the
29778 status of ATPCS support, so instead we create a dummy,
c19d1205 29779 empty, debug section called .arm.atpcs. */
b99bd4ef
NC
29780 if (atpcs)
29781 {
29782 asection * sec;
29783
29784 sec = bfd_make_section (stdoutput, ".arm.atpcs");
29785
29786 if (sec != NULL)
29787 {
29788 bfd_set_section_flags
29789 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
29790 bfd_set_section_size (stdoutput, sec, 0);
29791 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
29792 }
29793 }
7cc69913 29794 }
f17c130b 29795#endif
b99bd4ef
NC
29796
29797 /* Record the CPU type as well. */
2d447fca
JM
29798 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
29799 mach = bfd_mach_arm_iWMMXt2;
29800 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
e16bb312 29801 mach = bfd_mach_arm_iWMMXt;
e74cfd16 29802 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
b99bd4ef 29803 mach = bfd_mach_arm_XScale;
e74cfd16 29804 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
fde78edd 29805 mach = bfd_mach_arm_ep9312;
e74cfd16 29806 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
b99bd4ef 29807 mach = bfd_mach_arm_5TE;
e74cfd16 29808 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
b99bd4ef 29809 {
e74cfd16 29810 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
b99bd4ef
NC
29811 mach = bfd_mach_arm_5T;
29812 else
29813 mach = bfd_mach_arm_5;
29814 }
e74cfd16 29815 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
b99bd4ef 29816 {
e74cfd16 29817 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
b99bd4ef
NC
29818 mach = bfd_mach_arm_4T;
29819 else
29820 mach = bfd_mach_arm_4;
29821 }
e74cfd16 29822 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
b99bd4ef 29823 mach = bfd_mach_arm_3M;
e74cfd16
PB
29824 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
29825 mach = bfd_mach_arm_3;
29826 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
29827 mach = bfd_mach_arm_2a;
29828 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
29829 mach = bfd_mach_arm_2;
29830 else
29831 mach = bfd_mach_arm_unknown;
b99bd4ef
NC
29832
29833 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
29834}
29835
c19d1205 29836/* Command line processing. */
b99bd4ef 29837
c19d1205
ZW
29838/* md_parse_option
29839 Invocation line includes a switch not recognized by the base assembler.
29840 See if it's a processor-specific option.
b99bd4ef 29841
c19d1205
ZW
29842 This routine is somewhat complicated by the need for backwards
29843 compatibility (since older releases of gcc can't be changed).
29844 The new options try to make the interface as compatible as
29845 possible with GCC.
b99bd4ef 29846
c19d1205 29847 New options (supported) are:
b99bd4ef 29848
c19d1205
ZW
29849 -mcpu=<cpu name> Assemble for selected processor
29850 -march=<architecture name> Assemble for selected architecture
29851 -mfpu=<fpu architecture> Assemble for selected FPU.
29852 -EB/-mbig-endian Big-endian
29853 -EL/-mlittle-endian Little-endian
29854 -k Generate PIC code
29855 -mthumb Start in Thumb mode
29856 -mthumb-interwork Code supports ARM/Thumb interworking
b99bd4ef 29857
278df34e 29858 -m[no-]warn-deprecated Warn about deprecated features
8b2d793c 29859 -m[no-]warn-syms Warn when symbols match instructions
267bf995 29860
c19d1205 29861 For now we will also provide support for:
b99bd4ef 29862
c19d1205
ZW
29863 -mapcs-32 32-bit Program counter
29864 -mapcs-26 26-bit Program counter
29865 -macps-float Floats passed in FP registers
29866 -mapcs-reentrant Reentrant code
29867 -matpcs
29868 (sometime these will probably be replaced with -mapcs=<list of options>
29869 and -matpcs=<list of options>)
b99bd4ef 29870
c19d1205
ZW
29871 The remaining options are only supported for back-wards compatibility.
29872 Cpu variants, the arm part is optional:
29873 -m[arm]1 Currently not supported.
29874 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
29875 -m[arm]3 Arm 3 processor
29876 -m[arm]6[xx], Arm 6 processors
29877 -m[arm]7[xx][t][[d]m] Arm 7 processors
29878 -m[arm]8[10] Arm 8 processors
29879 -m[arm]9[20][tdmi] Arm 9 processors
29880 -mstrongarm[110[0]] StrongARM processors
29881 -mxscale XScale processors
29882 -m[arm]v[2345[t[e]]] Arm architectures
29883 -mall All (except the ARM1)
29884 FP variants:
29885 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
29886 -mfpe-old (No float load/store multiples)
29887 -mvfpxd VFP Single precision
29888 -mvfp All VFP
29889 -mno-fpu Disable all floating point instructions
b99bd4ef 29890
c19d1205
ZW
29891 The following CPU names are recognized:
29892 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
29893 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
29894 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
29895 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
29896 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
29897 arm10t arm10e, arm1020t, arm1020e, arm10200e,
29898 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
b99bd4ef 29899
c19d1205 29900 */
b99bd4ef 29901
c19d1205 29902const char * md_shortopts = "m:k";
b99bd4ef 29903
c19d1205
ZW
29904#ifdef ARM_BI_ENDIAN
29905#define OPTION_EB (OPTION_MD_BASE + 0)
29906#define OPTION_EL (OPTION_MD_BASE + 1)
b99bd4ef 29907#else
c19d1205
ZW
29908#if TARGET_BYTES_BIG_ENDIAN
29909#define OPTION_EB (OPTION_MD_BASE + 0)
b99bd4ef 29910#else
c19d1205
ZW
29911#define OPTION_EL (OPTION_MD_BASE + 1)
29912#endif
b99bd4ef 29913#endif
845b51d6 29914#define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
18a20338 29915#define OPTION_FDPIC (OPTION_MD_BASE + 3)
b99bd4ef 29916
c19d1205 29917struct option md_longopts[] =
b99bd4ef 29918{
c19d1205
ZW
29919#ifdef OPTION_EB
29920 {"EB", no_argument, NULL, OPTION_EB},
29921#endif
29922#ifdef OPTION_EL
29923 {"EL", no_argument, NULL, OPTION_EL},
b99bd4ef 29924#endif
845b51d6 29925 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
18a20338
CL
29926#ifdef OBJ_ELF
29927 {"fdpic", no_argument, NULL, OPTION_FDPIC},
29928#endif
c19d1205
ZW
29929 {NULL, no_argument, NULL, 0}
29930};
b99bd4ef 29931
c19d1205 29932size_t md_longopts_size = sizeof (md_longopts);
b99bd4ef 29933
c19d1205 29934struct arm_option_table
b99bd4ef 29935{
0198d5e6
TC
29936 const char * option; /* Option name to match. */
29937 const char * help; /* Help information. */
29938 int * var; /* Variable to change. */
29939 int value; /* What to change it to. */
29940 const char * deprecated; /* If non-null, print this message. */
c19d1205 29941};
b99bd4ef 29942
c19d1205
ZW
29943struct arm_option_table arm_opts[] =
29944{
29945 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
29946 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
29947 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
29948 &support_interwork, 1, NULL},
29949 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
29950 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
29951 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
29952 1, NULL},
29953 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
29954 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
29955 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
29956 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
29957 NULL},
b99bd4ef 29958
c19d1205
ZW
29959 /* These are recognized by the assembler, but have no affect on code. */
29960 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
29961 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
278df34e
NS
29962
29963 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
29964 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
29965 &warn_on_deprecated, 0, NULL},
8b2d793c
NC
29966 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL},
29967 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL},
e74cfd16
PB
29968 {NULL, NULL, NULL, 0, NULL}
29969};
29970
29971struct arm_legacy_option_table
29972{
0198d5e6
TC
29973 const char * option; /* Option name to match. */
29974 const arm_feature_set ** var; /* Variable to change. */
29975 const arm_feature_set value; /* What to change it to. */
29976 const char * deprecated; /* If non-null, print this message. */
e74cfd16 29977};
b99bd4ef 29978
e74cfd16
PB
29979const struct arm_legacy_option_table arm_legacy_opts[] =
29980{
c19d1205
ZW
29981 /* DON'T add any new processors to this list -- we want the whole list
29982 to go away... Add them to the processors table instead. */
e74cfd16
PB
29983 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
29984 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
29985 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
29986 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
29987 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
29988 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
29989 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
29990 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
29991 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
29992 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
29993 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
29994 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
29995 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
29996 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
29997 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
29998 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
29999 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
30000 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
30001 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
30002 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
30003 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
30004 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
30005 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
30006 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
30007 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
30008 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
30009 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
30010 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
30011 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
30012 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
30013 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
30014 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
30015 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
30016 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
30017 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
30018 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
30019 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
30020 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
30021 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
30022 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
30023 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
30024 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
30025 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
30026 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
30027 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
30028 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
30029 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
30030 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
30031 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
30032 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
30033 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
30034 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
30035 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
30036 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
30037 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
30038 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
30039 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
30040 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
30041 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
30042 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
30043 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
30044 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
30045 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
30046 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
30047 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
30048 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
30049 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
30050 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
30051 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
30052 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
c19d1205 30053 N_("use -mcpu=strongarm110")},
e74cfd16 30054 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
c19d1205 30055 N_("use -mcpu=strongarm1100")},
e74cfd16 30056 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
c19d1205 30057 N_("use -mcpu=strongarm1110")},
e74cfd16
PB
30058 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
30059 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
30060 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
7ed4c4c5 30061
c19d1205 30062 /* Architecture variants -- don't add any more to this list either. */
e74cfd16
PB
30063 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
30064 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
30065 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
30066 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
30067 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
30068 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
30069 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
30070 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
30071 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
30072 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
30073 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
30074 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
30075 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
30076 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
30077 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
30078 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
30079 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
30080 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
7ed4c4c5 30081
c19d1205 30082 /* Floating point variants -- don't add any more to this list either. */
0198d5e6
TC
30083 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
30084 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
30085 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
30086 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
c19d1205 30087 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
7ed4c4c5 30088
e74cfd16 30089 {NULL, NULL, ARM_ARCH_NONE, NULL}
c19d1205 30090};
7ed4c4c5 30091
c19d1205 30092struct arm_cpu_option_table
7ed4c4c5 30093{
0198d5e6
TC
30094 const char * name;
30095 size_t name_len;
30096 const arm_feature_set value;
30097 const arm_feature_set ext;
c19d1205
ZW
30098 /* For some CPUs we assume an FPU unless the user explicitly sets
30099 -mfpu=... */
0198d5e6 30100 const arm_feature_set default_fpu;
ee065d83
PB
30101 /* The canonical name of the CPU, or NULL to use NAME converted to upper
30102 case. */
0198d5e6 30103 const char * canonical_name;
c19d1205 30104};
7ed4c4c5 30105
c19d1205
ZW
30106/* This list should, at a minimum, contain all the cpu names
30107 recognized by GCC. */
996b5569 30108#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
0198d5e6 30109
e74cfd16 30110static const struct arm_cpu_option_table arm_cpus[] =
c19d1205 30111{
996b5569
TP
30112 ARM_CPU_OPT ("all", NULL, ARM_ANY,
30113 ARM_ARCH_NONE,
30114 FPU_ARCH_FPA),
30115 ARM_CPU_OPT ("arm1", NULL, ARM_ARCH_V1,
30116 ARM_ARCH_NONE,
30117 FPU_ARCH_FPA),
30118 ARM_CPU_OPT ("arm2", NULL, ARM_ARCH_V2,
30119 ARM_ARCH_NONE,
30120 FPU_ARCH_FPA),
30121 ARM_CPU_OPT ("arm250", NULL, ARM_ARCH_V2S,
30122 ARM_ARCH_NONE,
30123 FPU_ARCH_FPA),
30124 ARM_CPU_OPT ("arm3", NULL, ARM_ARCH_V2S,
30125 ARM_ARCH_NONE,
30126 FPU_ARCH_FPA),
30127 ARM_CPU_OPT ("arm6", NULL, ARM_ARCH_V3,
30128 ARM_ARCH_NONE,
30129 FPU_ARCH_FPA),
30130 ARM_CPU_OPT ("arm60", NULL, ARM_ARCH_V3,
30131 ARM_ARCH_NONE,
30132 FPU_ARCH_FPA),
30133 ARM_CPU_OPT ("arm600", NULL, ARM_ARCH_V3,
30134 ARM_ARCH_NONE,
30135 FPU_ARCH_FPA),
30136 ARM_CPU_OPT ("arm610", NULL, ARM_ARCH_V3,
30137 ARM_ARCH_NONE,
30138 FPU_ARCH_FPA),
30139 ARM_CPU_OPT ("arm620", NULL, ARM_ARCH_V3,
30140 ARM_ARCH_NONE,
30141 FPU_ARCH_FPA),
30142 ARM_CPU_OPT ("arm7", NULL, ARM_ARCH_V3,
30143 ARM_ARCH_NONE,
30144 FPU_ARCH_FPA),
30145 ARM_CPU_OPT ("arm7m", NULL, ARM_ARCH_V3M,
30146 ARM_ARCH_NONE,
30147 FPU_ARCH_FPA),
30148 ARM_CPU_OPT ("arm7d", NULL, ARM_ARCH_V3,
30149 ARM_ARCH_NONE,
30150 FPU_ARCH_FPA),
30151 ARM_CPU_OPT ("arm7dm", NULL, ARM_ARCH_V3M,
30152 ARM_ARCH_NONE,
30153 FPU_ARCH_FPA),
30154 ARM_CPU_OPT ("arm7di", NULL, ARM_ARCH_V3,
30155 ARM_ARCH_NONE,
30156 FPU_ARCH_FPA),
30157 ARM_CPU_OPT ("arm7dmi", NULL, ARM_ARCH_V3M,
30158 ARM_ARCH_NONE,
30159 FPU_ARCH_FPA),
30160 ARM_CPU_OPT ("arm70", NULL, ARM_ARCH_V3,
30161 ARM_ARCH_NONE,
30162 FPU_ARCH_FPA),
30163 ARM_CPU_OPT ("arm700", NULL, ARM_ARCH_V3,
30164 ARM_ARCH_NONE,
30165 FPU_ARCH_FPA),
30166 ARM_CPU_OPT ("arm700i", NULL, ARM_ARCH_V3,
30167 ARM_ARCH_NONE,
30168 FPU_ARCH_FPA),
30169 ARM_CPU_OPT ("arm710", NULL, ARM_ARCH_V3,
30170 ARM_ARCH_NONE,
30171 FPU_ARCH_FPA),
30172 ARM_CPU_OPT ("arm710t", NULL, ARM_ARCH_V4T,
30173 ARM_ARCH_NONE,
30174 FPU_ARCH_FPA),
30175 ARM_CPU_OPT ("arm720", NULL, ARM_ARCH_V3,
30176 ARM_ARCH_NONE,
30177 FPU_ARCH_FPA),
30178 ARM_CPU_OPT ("arm720t", NULL, ARM_ARCH_V4T,
30179 ARM_ARCH_NONE,
30180 FPU_ARCH_FPA),
30181 ARM_CPU_OPT ("arm740t", NULL, ARM_ARCH_V4T,
30182 ARM_ARCH_NONE,
30183 FPU_ARCH_FPA),
30184 ARM_CPU_OPT ("arm710c", NULL, ARM_ARCH_V3,
30185 ARM_ARCH_NONE,
30186 FPU_ARCH_FPA),
30187 ARM_CPU_OPT ("arm7100", NULL, ARM_ARCH_V3,
30188 ARM_ARCH_NONE,
30189 FPU_ARCH_FPA),
30190 ARM_CPU_OPT ("arm7500", NULL, ARM_ARCH_V3,
30191 ARM_ARCH_NONE,
30192 FPU_ARCH_FPA),
30193 ARM_CPU_OPT ("arm7500fe", NULL, ARM_ARCH_V3,
30194 ARM_ARCH_NONE,
30195 FPU_ARCH_FPA),
30196 ARM_CPU_OPT ("arm7t", NULL, ARM_ARCH_V4T,
30197 ARM_ARCH_NONE,
30198 FPU_ARCH_FPA),
30199 ARM_CPU_OPT ("arm7tdmi", NULL, ARM_ARCH_V4T,
30200 ARM_ARCH_NONE,
30201 FPU_ARCH_FPA),
30202 ARM_CPU_OPT ("arm7tdmi-s", NULL, ARM_ARCH_V4T,
30203 ARM_ARCH_NONE,
30204 FPU_ARCH_FPA),
30205 ARM_CPU_OPT ("arm8", NULL, ARM_ARCH_V4,
30206 ARM_ARCH_NONE,
30207 FPU_ARCH_FPA),
30208 ARM_CPU_OPT ("arm810", NULL, ARM_ARCH_V4,
30209 ARM_ARCH_NONE,
30210 FPU_ARCH_FPA),
30211 ARM_CPU_OPT ("strongarm", NULL, ARM_ARCH_V4,
30212 ARM_ARCH_NONE,
30213 FPU_ARCH_FPA),
30214 ARM_CPU_OPT ("strongarm1", NULL, ARM_ARCH_V4,
30215 ARM_ARCH_NONE,
30216 FPU_ARCH_FPA),
30217 ARM_CPU_OPT ("strongarm110", NULL, ARM_ARCH_V4,
30218 ARM_ARCH_NONE,
30219 FPU_ARCH_FPA),
30220 ARM_CPU_OPT ("strongarm1100", NULL, ARM_ARCH_V4,
30221 ARM_ARCH_NONE,
30222 FPU_ARCH_FPA),
30223 ARM_CPU_OPT ("strongarm1110", NULL, ARM_ARCH_V4,
30224 ARM_ARCH_NONE,
30225 FPU_ARCH_FPA),
30226 ARM_CPU_OPT ("arm9", NULL, ARM_ARCH_V4T,
30227 ARM_ARCH_NONE,
30228 FPU_ARCH_FPA),
30229 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T,
30230 ARM_ARCH_NONE,
30231 FPU_ARCH_FPA),
30232 ARM_CPU_OPT ("arm920t", NULL, ARM_ARCH_V4T,
30233 ARM_ARCH_NONE,
30234 FPU_ARCH_FPA),
30235 ARM_CPU_OPT ("arm922t", NULL, ARM_ARCH_V4T,
30236 ARM_ARCH_NONE,
30237 FPU_ARCH_FPA),
30238 ARM_CPU_OPT ("arm940t", NULL, ARM_ARCH_V4T,
30239 ARM_ARCH_NONE,
30240 FPU_ARCH_FPA),
30241 ARM_CPU_OPT ("arm9tdmi", NULL, ARM_ARCH_V4T,
30242 ARM_ARCH_NONE,
30243 FPU_ARCH_FPA),
30244 ARM_CPU_OPT ("fa526", NULL, ARM_ARCH_V4,
30245 ARM_ARCH_NONE,
30246 FPU_ARCH_FPA),
30247 ARM_CPU_OPT ("fa626", NULL, ARM_ARCH_V4,
30248 ARM_ARCH_NONE,
30249 FPU_ARCH_FPA),
30250
c19d1205
ZW
30251 /* For V5 or later processors we default to using VFP; but the user
30252 should really set the FPU type explicitly. */
996b5569
TP
30253 ARM_CPU_OPT ("arm9e-r0", NULL, ARM_ARCH_V5TExP,
30254 ARM_ARCH_NONE,
30255 FPU_ARCH_VFP_V2),
30256 ARM_CPU_OPT ("arm9e", NULL, ARM_ARCH_V5TE,
30257 ARM_ARCH_NONE,
30258 FPU_ARCH_VFP_V2),
30259 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ,
30260 ARM_ARCH_NONE,
30261 FPU_ARCH_VFP_V2),
30262 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ,
30263 ARM_ARCH_NONE,
30264 FPU_ARCH_VFP_V2),
30265 ARM_CPU_OPT ("arm926ej-s", NULL, ARM_ARCH_V5TEJ,
30266 ARM_ARCH_NONE,
30267 FPU_ARCH_VFP_V2),
30268 ARM_CPU_OPT ("arm946e-r0", NULL, ARM_ARCH_V5TExP,
30269 ARM_ARCH_NONE,
30270 FPU_ARCH_VFP_V2),
30271 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE,
30272 ARM_ARCH_NONE,
30273 FPU_ARCH_VFP_V2),
30274 ARM_CPU_OPT ("arm946e-s", NULL, ARM_ARCH_V5TE,
30275 ARM_ARCH_NONE,
30276 FPU_ARCH_VFP_V2),
30277 ARM_CPU_OPT ("arm966e-r0", NULL, ARM_ARCH_V5TExP,
30278 ARM_ARCH_NONE,
30279 FPU_ARCH_VFP_V2),
30280 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE,
30281 ARM_ARCH_NONE,
30282 FPU_ARCH_VFP_V2),
30283 ARM_CPU_OPT ("arm966e-s", NULL, ARM_ARCH_V5TE,
30284 ARM_ARCH_NONE,
30285 FPU_ARCH_VFP_V2),
30286 ARM_CPU_OPT ("arm968e-s", NULL, ARM_ARCH_V5TE,
30287 ARM_ARCH_NONE,
30288 FPU_ARCH_VFP_V2),
30289 ARM_CPU_OPT ("arm10t", NULL, ARM_ARCH_V5T,
30290 ARM_ARCH_NONE,
30291 FPU_ARCH_VFP_V1),
30292 ARM_CPU_OPT ("arm10tdmi", NULL, ARM_ARCH_V5T,
30293 ARM_ARCH_NONE,
30294 FPU_ARCH_VFP_V1),
30295 ARM_CPU_OPT ("arm10e", NULL, ARM_ARCH_V5TE,
30296 ARM_ARCH_NONE,
30297 FPU_ARCH_VFP_V2),
30298 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE,
30299 ARM_ARCH_NONE,
30300 FPU_ARCH_VFP_V2),
30301 ARM_CPU_OPT ("arm1020t", NULL, ARM_ARCH_V5T,
30302 ARM_ARCH_NONE,
30303 FPU_ARCH_VFP_V1),
30304 ARM_CPU_OPT ("arm1020e", NULL, ARM_ARCH_V5TE,
30305 ARM_ARCH_NONE,
30306 FPU_ARCH_VFP_V2),
30307 ARM_CPU_OPT ("arm1022e", NULL, ARM_ARCH_V5TE,
30308 ARM_ARCH_NONE,
30309 FPU_ARCH_VFP_V2),
30310 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ,
30311 ARM_ARCH_NONE,
30312 FPU_ARCH_VFP_V2),
30313 ARM_CPU_OPT ("arm1026ej-s", NULL, ARM_ARCH_V5TEJ,
30314 ARM_ARCH_NONE,
30315 FPU_ARCH_VFP_V2),
30316 ARM_CPU_OPT ("fa606te", NULL, ARM_ARCH_V5TE,
30317 ARM_ARCH_NONE,
30318 FPU_ARCH_VFP_V2),
30319 ARM_CPU_OPT ("fa616te", NULL, ARM_ARCH_V5TE,
30320 ARM_ARCH_NONE,
30321 FPU_ARCH_VFP_V2),
30322 ARM_CPU_OPT ("fa626te", NULL, ARM_ARCH_V5TE,
30323 ARM_ARCH_NONE,
30324 FPU_ARCH_VFP_V2),
30325 ARM_CPU_OPT ("fmp626", NULL, ARM_ARCH_V5TE,
30326 ARM_ARCH_NONE,
30327 FPU_ARCH_VFP_V2),
30328 ARM_CPU_OPT ("fa726te", NULL, ARM_ARCH_V5TE,
30329 ARM_ARCH_NONE,
30330 FPU_ARCH_VFP_V2),
30331 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6,
30332 ARM_ARCH_NONE,
30333 FPU_NONE),
30334 ARM_CPU_OPT ("arm1136j-s", NULL, ARM_ARCH_V6,
30335 ARM_ARCH_NONE,
30336 FPU_NONE),
30337 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6,
30338 ARM_ARCH_NONE,
30339 FPU_ARCH_VFP_V2),
30340 ARM_CPU_OPT ("arm1136jf-s", NULL, ARM_ARCH_V6,
30341 ARM_ARCH_NONE,
30342 FPU_ARCH_VFP_V2),
30343 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K,
30344 ARM_ARCH_NONE,
30345 FPU_ARCH_VFP_V2),
30346 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K,
30347 ARM_ARCH_NONE,
30348 FPU_NONE),
30349 ARM_CPU_OPT ("arm1156t2-s", NULL, ARM_ARCH_V6T2,
30350 ARM_ARCH_NONE,
30351 FPU_NONE),
30352 ARM_CPU_OPT ("arm1156t2f-s", NULL, ARM_ARCH_V6T2,
30353 ARM_ARCH_NONE,
30354 FPU_ARCH_VFP_V2),
30355 ARM_CPU_OPT ("arm1176jz-s", NULL, ARM_ARCH_V6KZ,
30356 ARM_ARCH_NONE,
30357 FPU_NONE),
30358 ARM_CPU_OPT ("arm1176jzf-s", NULL, ARM_ARCH_V6KZ,
30359 ARM_ARCH_NONE,
30360 FPU_ARCH_VFP_V2),
30361 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A,
30362 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
30363 FPU_NONE),
30364 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE,
30365 ARM_ARCH_NONE,
30366 FPU_ARCH_NEON_VFP_V4),
30367 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A,
30368 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
30369 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
30370 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A,
30371 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
30372 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
30373 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE,
30374 ARM_ARCH_NONE,
30375 FPU_ARCH_NEON_VFP_V4),
30376 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE,
30377 ARM_ARCH_NONE,
30378 FPU_ARCH_NEON_VFP_V4),
30379 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE,
30380 ARM_ARCH_NONE,
30381 FPU_ARCH_NEON_VFP_V4),
30382 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A,
30383 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30384 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30385 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A,
30386 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30387 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30388 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A,
30389 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30390 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
15a7695f
JG
30391 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A,
30392 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0198d5e6 30393 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
996b5569
TP
30394 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A,
30395 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30396 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30397 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A,
30398 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30399 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30400 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A,
30401 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30402 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
15a7695f
JG
30403 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A,
30404 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0198d5e6 30405 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
7ebd1359 30406 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A,
30407 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30408 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
ef8df4ca
KT
30409 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A,
30410 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30411 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
996b5569
TP
30412 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R,
30413 ARM_ARCH_NONE,
30414 FPU_NONE),
30415 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R,
30416 ARM_ARCH_NONE,
30417 FPU_ARCH_VFP_V3D16),
30418 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R,
30419 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
30420 FPU_NONE),
30421 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R,
30422 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
30423 FPU_ARCH_VFP_V3D16),
30424 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R,
30425 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
30426 FPU_ARCH_VFP_V3D16),
0cda1e19
TP
30427 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R,
30428 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30429 FPU_ARCH_NEON_VFP_ARMV8),
996b5569
TP
30430 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN,
30431 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30432 FPU_NONE),
30433 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE,
30434 ARM_ARCH_NONE,
30435 FPU_NONE),
30436 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM,
30437 ARM_ARCH_NONE,
30438 FPU_NONE),
30439 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM,
30440 ARM_ARCH_NONE,
30441 FPU_NONE),
30442 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M,
30443 ARM_ARCH_NONE,
30444 FPU_NONE),
30445 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM,
30446 ARM_ARCH_NONE,
30447 FPU_NONE),
30448 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM,
30449 ARM_ARCH_NONE,
30450 FPU_NONE),
30451 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM,
30452 ARM_ARCH_NONE,
30453 FPU_NONE),
30454 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A,
30455 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30456 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
83f43c83
KT
30457 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A,
30458 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30459 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
c19d1205 30460 /* ??? XSCALE is really an architecture. */
996b5569
TP
30461 ARM_CPU_OPT ("xscale", NULL, ARM_ARCH_XSCALE,
30462 ARM_ARCH_NONE,
30463 FPU_ARCH_VFP_V2),
30464
c19d1205 30465 /* ??? iwmmxt is not a processor. */
996b5569
TP
30466 ARM_CPU_OPT ("iwmmxt", NULL, ARM_ARCH_IWMMXT,
30467 ARM_ARCH_NONE,
30468 FPU_ARCH_VFP_V2),
30469 ARM_CPU_OPT ("iwmmxt2", NULL, ARM_ARCH_IWMMXT2,
30470 ARM_ARCH_NONE,
30471 FPU_ARCH_VFP_V2),
30472 ARM_CPU_OPT ("i80200", NULL, ARM_ARCH_XSCALE,
30473 ARM_ARCH_NONE,
30474 FPU_ARCH_VFP_V2),
30475
0198d5e6 30476 /* Maverick. */
996b5569
TP
30477 ARM_CPU_OPT ("ep9312", "ARM920T",
30478 ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
30479 ARM_ARCH_NONE, FPU_ARCH_MAVERICK),
30480
da4339ed 30481 /* Marvell processors. */
996b5569
TP
30482 ARM_CPU_OPT ("marvell-pj4", NULL, ARM_ARCH_V7A,
30483 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
30484 FPU_ARCH_VFP_V3D16),
30485 ARM_CPU_OPT ("marvell-whitney", NULL, ARM_ARCH_V7A,
30486 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
30487 FPU_ARCH_NEON_VFP_V4),
da4339ed 30488
996b5569
TP
30489 /* APM X-Gene family. */
30490 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A,
30491 ARM_ARCH_NONE,
30492 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30493 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A,
30494 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30495 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30496
30497 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
c19d1205 30498};
f3bad469 30499#undef ARM_CPU_OPT
7ed4c4c5 30500
34ef62f4
AV
30501struct arm_ext_table
30502{
30503 const char * name;
30504 size_t name_len;
30505 const arm_feature_set merge;
30506 const arm_feature_set clear;
30507};
30508
c19d1205 30509struct arm_arch_option_table
7ed4c4c5 30510{
34ef62f4
AV
30511 const char * name;
30512 size_t name_len;
30513 const arm_feature_set value;
30514 const arm_feature_set default_fpu;
30515 const struct arm_ext_table * ext_table;
30516};
30517
30518/* Used to add support for +E and +noE extension. */
30519#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
30520/* Used to add support for a +E extension. */
30521#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
30522/* Used to add support for a +noE extension. */
30523#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
30524
30525#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
30526 ~0 & ~FPU_ENDIAN_PURE)
30527
30528static const struct arm_ext_table armv5te_ext_table[] =
30529{
30530 ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP),
30531 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30532};
30533
30534static const struct arm_ext_table armv7_ext_table[] =
30535{
30536 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
30537 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30538};
30539
30540static const struct arm_ext_table armv7ve_ext_table[] =
30541{
30542 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16, ALL_FP),
30543 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16),
30544 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
30545 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
30546 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
30547 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16), /* Alias for +fp. */
30548 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
30549
30550 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4,
30551 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
30552
30553 /* Aliases for +simd. */
30554 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
30555
30556 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
30557 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
30558 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
30559
30560 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30561};
30562
30563static const struct arm_ext_table armv7a_ext_table[] =
30564{
30565 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
30566 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */
30567 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
30568 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
30569 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
30570 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16),
30571 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
30572
30573 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1,
30574 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
30575
30576 /* Aliases for +simd. */
30577 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
30578 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
30579
30580 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
30581 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
30582
30583 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP)),
30584 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC)),
30585 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30586};
30587
30588static const struct arm_ext_table armv7r_ext_table[] =
30589{
30590 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD),
30591 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD), /* Alias for +fp.sp. */
30592 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
30593 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */
30594 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16),
30595 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
30596 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
30597 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV)),
30598 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30599};
30600
30601static const struct arm_ext_table armv7em_ext_table[] =
30602{
30603 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16, ALL_FP),
30604 /* Alias for +fp, used to be known as fpv4-sp-d16. */
30605 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16),
30606 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16),
30607 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
30608 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16),
30609 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30610};
30611
30612static const struct arm_ext_table armv8a_ext_table[] =
30613{
30614 ARM_ADD ("crc", ARCH_CRC_ARMV8),
30615 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
30616 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
30617 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30618
30619 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30620 should use the +simd option to turn on FP. */
30621 ARM_REMOVE ("fp", ALL_FP),
30622 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
30623 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
30624 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30625};
30626
30627
30628static const struct arm_ext_table armv81a_ext_table[] =
30629{
30630 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
30631 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
30632 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30633
30634 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30635 should use the +simd option to turn on FP. */
30636 ARM_REMOVE ("fp", ALL_FP),
30637 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
30638 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
30639 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30640};
30641
30642static const struct arm_ext_table armv82a_ext_table[] =
30643{
30644 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
30645 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16),
30646 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML),
30647 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
30648 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30649 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
30650
30651 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30652 should use the +simd option to turn on FP. */
30653 ARM_REMOVE ("fp", ALL_FP),
30654 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
30655 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
30656 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30657};
30658
30659static const struct arm_ext_table armv84a_ext_table[] =
30660{
30661 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
30662 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
30663 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
30664 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30665
30666 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30667 should use the +simd option to turn on FP. */
30668 ARM_REMOVE ("fp", ALL_FP),
30669 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
30670 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
30671 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30672};
30673
30674static const struct arm_ext_table armv85a_ext_table[] =
30675{
30676 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
30677 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
30678 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
30679 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30680
30681 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30682 should use the +simd option to turn on FP. */
30683 ARM_REMOVE ("fp", ALL_FP),
30684 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30685};
30686
30687static const struct arm_ext_table armv8m_main_ext_table[] =
30688{
30689 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30690 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)),
30691 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16, ALL_FP),
30692 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
30693 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30694};
30695
e0991585
AV
30696static const struct arm_ext_table armv8_1m_main_ext_table[] =
30697{
30698 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30699 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)),
30700 ARM_EXT ("fp",
30701 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
30702 FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
30703 ALL_FP),
30704 ARM_ADD ("fp.dp",
30705 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
30706 FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
a7ad558c
AV
30707 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE),
30708 ARM_FEATURE_COPROC (FPU_MVE | FPU_MVE_FP)),
30709 ARM_ADD ("mve.fp",
30710 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
30711 FPU_MVE | FPU_MVE_FP | FPU_VFP_V5_SP_D16 |
30712 FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
e0991585
AV
30713 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30714};
30715
34ef62f4
AV
30716static const struct arm_ext_table armv8r_ext_table[] =
30717{
30718 ARM_ADD ("crc", ARCH_CRC_ARMV8),
30719 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
30720 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
30721 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30722 ARM_REMOVE ("fp", ALL_FP),
30723 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16),
30724 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
c19d1205 30725};
7ed4c4c5 30726
c19d1205
ZW
30727/* This list should, at a minimum, contain all the architecture names
30728 recognized by GCC. */
34ef62f4
AV
30729#define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
30730#define ARM_ARCH_OPT2(N, V, DF, ext) \
30731 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
0198d5e6 30732
e74cfd16 30733static const struct arm_arch_option_table arm_archs[] =
c19d1205 30734{
497d849d
TP
30735 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
30736 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
30737 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
30738 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
30739 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
30740 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
30741 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
30742 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
30743 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
30744 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
30745 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
30746 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
30747 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
30748 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
34ef62f4
AV
30749 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP, armv5te),
30750 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP, armv5te),
30751 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP, armv5te),
30752 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te),
30753 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te),
30754 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP, armv5te),
30755 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP, armv5te),
f33026a9
MW
30756 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
30757 kept to preserve existing behaviour. */
34ef62f4
AV
30758 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te),
30759 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te),
30760 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP, armv5te),
30761 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP, armv5te),
30762 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP, armv5te),
f33026a9
MW
30763 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
30764 kept to preserve existing behaviour. */
34ef62f4
AV
30765 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te),
30766 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te),
497d849d
TP
30767 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
30768 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
34ef62f4 30769 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP, armv7),
c450d570
PB
30770 /* The official spelling of the ARMv7 profile variants is the dashed form.
30771 Accept the non-dashed form for compatibility with old toolchains. */
34ef62f4
AV
30772 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a),
30773 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP, armv7ve),
30774 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r),
497d849d 30775 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
34ef62f4
AV
30776 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a),
30777 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r),
497d849d 30778 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
34ef62f4 30779 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP, armv7em),
497d849d 30780 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP),
34ef62f4
AV
30781 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP,
30782 armv8m_main),
e0991585
AV
30783 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN, FPU_ARCH_VFP,
30784 armv8_1m_main),
34ef62f4
AV
30785 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP, armv8a),
30786 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP, armv81a),
30787 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP, armv82a),
30788 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A, FPU_ARCH_VFP, armv82a),
30789 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R, FPU_ARCH_VFP, armv8r),
30790 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A, FPU_ARCH_VFP, armv84a),
30791 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A, FPU_ARCH_VFP, armv85a),
497d849d
TP
30792 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
30793 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
30794 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2, FPU_ARCH_VFP),
34ef62f4 30795 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
c19d1205 30796};
f3bad469 30797#undef ARM_ARCH_OPT
7ed4c4c5 30798
69133863 30799/* ISA extensions in the co-processor and main instruction set space. */
0198d5e6 30800
69133863 30801struct arm_option_extension_value_table
c19d1205 30802{
0198d5e6
TC
30803 const char * name;
30804 size_t name_len;
30805 const arm_feature_set merge_value;
30806 const arm_feature_set clear_value;
d942732e
TP
30807 /* List of architectures for which an extension is available. ARM_ARCH_NONE
30808 indicates that an extension is available for all architectures while
30809 ARM_ANY marks an empty entry. */
0198d5e6 30810 const arm_feature_set allowed_archs[2];
c19d1205 30811};
7ed4c4c5 30812
0198d5e6
TC
30813/* The following table must be in alphabetical order with a NULL last entry. */
30814
d942732e
TP
30815#define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
30816#define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
0198d5e6 30817
34ef62f4
AV
30818/* DEPRECATED: Refrain from using this table to add any new extensions, instead
30819 use the context sensitive approach using arm_ext_table's. */
69133863 30820static const struct arm_option_extension_value_table arm_extensions[] =
c19d1205 30821{
823d2571
TG
30822 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30823 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
bca38921 30824 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
823d2571
TG
30825 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8),
30826 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
c604a79a
JW
30827 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8,
30828 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
30829 ARM_ARCH_V8_2A),
15afaa63
TP
30830 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30831 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30832 ARM_FEATURE_CORE (ARM_EXT_V7M, ARM_EXT2_V8M)),
823d2571
TG
30833 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8),
30834 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
b8ec4e87
JW
30835 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30836 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30837 ARM_ARCH_V8_2A),
01f48020
TC
30838 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30839 | ARM_EXT2_FP16_FML),
30840 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30841 | ARM_EXT2_FP16_FML),
30842 ARM_ARCH_V8_2A),
d942732e 30843 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
823d2571 30844 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
d942732e
TP
30845 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
30846 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
3d030cdb
TP
30847 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
30848 Thumb divide instruction. Due to this having the same name as the
30849 previous entry, this will be ignored when doing command-line parsing and
30850 only considered by build attribute selection code. */
30851 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
30852 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
30853 ARM_FEATURE_CORE_LOW (ARM_EXT_V7)),
823d2571 30854 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
d942732e 30855 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ARCH_NONE),
823d2571 30856 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2),
d942732e 30857 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ARCH_NONE),
823d2571 30858 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
d942732e
TP
30859 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ARCH_NONE),
30860 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
823d2571 30861 ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
d942732e
TP
30862 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
30863 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
823d2571
TG
30864 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
30865 ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
30866 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)),
ddfded2f
MW
30867 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
30868 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0),
ced40572 30869 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
dad0c3bf
SD
30870 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
30871 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
30872 ARM_ARCH_V8A),
4d1464f2
MW
30873 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
30874 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0),
ced40572 30875 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
643afb90
MW
30876 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1,
30877 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
ced40572 30878 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
7fadb25d
SD
30879 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
30880 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
30881 ARM_ARCH_V8A),
d942732e 30882 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
823d2571 30883 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
d942732e
TP
30884 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
30885 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
643afb90
MW
30886 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
30887 ARM_FEATURE_COPROC (FPU_NEON_ARMV8),
30888 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
823d2571
TG
30889 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV
30890 | ARM_EXT_DIV),
30891 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
30892 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
30893 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
d942732e
TP
30894 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ARCH_NONE),
30895 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, { ARM_ARCH_NONE, ARM_ARCH_NONE } }
69133863 30896};
f3bad469 30897#undef ARM_EXT_OPT
69133863
MGD
30898
30899/* ISA floating-point and Advanced SIMD extensions. */
30900struct arm_option_fpu_value_table
30901{
0198d5e6
TC
30902 const char * name;
30903 const arm_feature_set value;
c19d1205 30904};
7ed4c4c5 30905
c19d1205
ZW
30906/* This list should, at a minimum, contain all the fpu names
30907 recognized by GCC. */
69133863 30908static const struct arm_option_fpu_value_table arm_fpus[] =
c19d1205
ZW
30909{
30910 {"softfpa", FPU_NONE},
30911 {"fpe", FPU_ARCH_FPE},
30912 {"fpe2", FPU_ARCH_FPE},
30913 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
30914 {"fpa", FPU_ARCH_FPA},
30915 {"fpa10", FPU_ARCH_FPA},
30916 {"fpa11", FPU_ARCH_FPA},
30917 {"arm7500fe", FPU_ARCH_FPA},
30918 {"softvfp", FPU_ARCH_VFP},
30919 {"softvfp+vfp", FPU_ARCH_VFP_V2},
30920 {"vfp", FPU_ARCH_VFP_V2},
30921 {"vfp9", FPU_ARCH_VFP_V2},
d5e0ba9c 30922 {"vfp3", FPU_ARCH_VFP_V3}, /* Undocumented, use vfpv3. */
c19d1205
ZW
30923 {"vfp10", FPU_ARCH_VFP_V2},
30924 {"vfp10-r0", FPU_ARCH_VFP_V1},
30925 {"vfpxd", FPU_ARCH_VFP_V1xD},
b1cc4aeb
PB
30926 {"vfpv2", FPU_ARCH_VFP_V2},
30927 {"vfpv3", FPU_ARCH_VFP_V3},
62f3b8c8 30928 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
b1cc4aeb 30929 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
62f3b8c8
PB
30930 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
30931 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
30932 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
c19d1205
ZW
30933 {"arm1020t", FPU_ARCH_VFP_V1},
30934 {"arm1020e", FPU_ARCH_VFP_V2},
d5e0ba9c 30935 {"arm1136jfs", FPU_ARCH_VFP_V2}, /* Undocumented, use arm1136jf-s. */
c19d1205
ZW
30936 {"arm1136jf-s", FPU_ARCH_VFP_V2},
30937 {"maverick", FPU_ARCH_MAVERICK},
d5e0ba9c 30938 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
d3375ddd 30939 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
8e79c3df 30940 {"neon-fp16", FPU_ARCH_NEON_FP16},
62f3b8c8
PB
30941 {"vfpv4", FPU_ARCH_VFP_V4},
30942 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
ada65aa3 30943 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
a715796b
TG
30944 {"fpv5-d16", FPU_ARCH_VFP_V5D16},
30945 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16},
62f3b8c8 30946 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
bca38921
MGD
30947 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
30948 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
30949 {"crypto-neon-fp-armv8",
30950 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
d6b4b13e 30951 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1},
081e4c7d
MW
30952 {"crypto-neon-fp-armv8.1",
30953 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1},
e74cfd16
PB
30954 {NULL, ARM_ARCH_NONE}
30955};
30956
30957struct arm_option_value_table
30958{
e0471c16 30959 const char *name;
e74cfd16 30960 long value;
c19d1205 30961};
7ed4c4c5 30962
e74cfd16 30963static const struct arm_option_value_table arm_float_abis[] =
c19d1205
ZW
30964{
30965 {"hard", ARM_FLOAT_ABI_HARD},
30966 {"softfp", ARM_FLOAT_ABI_SOFTFP},
30967 {"soft", ARM_FLOAT_ABI_SOFT},
e74cfd16 30968 {NULL, 0}
c19d1205 30969};
7ed4c4c5 30970
c19d1205 30971#ifdef OBJ_ELF
3a4a14e9 30972/* We only know how to output GNU and ver 4/5 (AAELF) formats. */
e74cfd16 30973static const struct arm_option_value_table arm_eabis[] =
c19d1205
ZW
30974{
30975 {"gnu", EF_ARM_EABI_UNKNOWN},
30976 {"4", EF_ARM_EABI_VER4},
3a4a14e9 30977 {"5", EF_ARM_EABI_VER5},
e74cfd16 30978 {NULL, 0}
c19d1205
ZW
30979};
30980#endif
7ed4c4c5 30981
c19d1205
ZW
30982struct arm_long_option_table
30983{
0198d5e6 30984 const char * option; /* Substring to match. */
e0471c16 30985 const char * help; /* Help information. */
17b9d67d 30986 int (* func) (const char * subopt); /* Function to decode sub-option. */
e0471c16 30987 const char * deprecated; /* If non-null, print this message. */
c19d1205 30988};
7ed4c4c5 30989
c921be7d 30990static bfd_boolean
c168ce07 30991arm_parse_extension (const char *str, const arm_feature_set *opt_set,
34ef62f4
AV
30992 arm_feature_set *ext_set,
30993 const struct arm_ext_table *ext_table)
7ed4c4c5 30994{
69133863 30995 /* We insist on extensions being specified in alphabetical order, and with
fa94de6b
RM
30996 extensions being added before being removed. We achieve this by having
30997 the global ARM_EXTENSIONS table in alphabetical order, and using the
69133863 30998 ADDING_VALUE variable to indicate whether we are adding an extension (1)
fa94de6b 30999 or removing it (0) and only allowing it to change in the order
69133863
MGD
31000 -1 -> 1 -> 0. */
31001 const struct arm_option_extension_value_table * opt = NULL;
d942732e 31002 const arm_feature_set arm_any = ARM_ANY;
69133863
MGD
31003 int adding_value = -1;
31004
c19d1205 31005 while (str != NULL && *str != 0)
7ed4c4c5 31006 {
82b8a785 31007 const char *ext;
f3bad469 31008 size_t len;
7ed4c4c5 31009
c19d1205
ZW
31010 if (*str != '+')
31011 {
31012 as_bad (_("invalid architectural extension"));
c921be7d 31013 return FALSE;
c19d1205 31014 }
7ed4c4c5 31015
c19d1205
ZW
31016 str++;
31017 ext = strchr (str, '+');
7ed4c4c5 31018
c19d1205 31019 if (ext != NULL)
f3bad469 31020 len = ext - str;
c19d1205 31021 else
f3bad469 31022 len = strlen (str);
7ed4c4c5 31023
f3bad469 31024 if (len >= 2 && strncmp (str, "no", 2) == 0)
69133863
MGD
31025 {
31026 if (adding_value != 0)
31027 {
31028 adding_value = 0;
31029 opt = arm_extensions;
31030 }
31031
f3bad469 31032 len -= 2;
69133863
MGD
31033 str += 2;
31034 }
f3bad469 31035 else if (len > 0)
69133863
MGD
31036 {
31037 if (adding_value == -1)
31038 {
31039 adding_value = 1;
31040 opt = arm_extensions;
31041 }
31042 else if (adding_value != 1)
31043 {
31044 as_bad (_("must specify extensions to add before specifying "
31045 "those to remove"));
31046 return FALSE;
31047 }
31048 }
31049
f3bad469 31050 if (len == 0)
c19d1205
ZW
31051 {
31052 as_bad (_("missing architectural extension"));
c921be7d 31053 return FALSE;
c19d1205 31054 }
7ed4c4c5 31055
69133863
MGD
31056 gas_assert (adding_value != -1);
31057 gas_assert (opt != NULL);
31058
34ef62f4
AV
31059 if (ext_table != NULL)
31060 {
31061 const struct arm_ext_table * ext_opt = ext_table;
31062 bfd_boolean found = FALSE;
31063 for (; ext_opt->name != NULL; ext_opt++)
31064 if (ext_opt->name_len == len
31065 && strncmp (ext_opt->name, str, len) == 0)
31066 {
31067 if (adding_value)
31068 {
31069 if (ARM_FEATURE_ZERO (ext_opt->merge))
31070 /* TODO: Option not supported. When we remove the
31071 legacy table this case should error out. */
31072 continue;
31073
31074 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, ext_opt->merge);
31075 }
31076 else
31077 {
31078 if (ARM_FEATURE_ZERO (ext_opt->clear))
31079 /* TODO: Option not supported. When we remove the
31080 legacy table this case should error out. */
31081 continue;
31082 ARM_CLEAR_FEATURE (*ext_set, *ext_set, ext_opt->clear);
31083 }
31084 found = TRUE;
31085 break;
31086 }
31087 if (found)
31088 {
31089 str = ext;
31090 continue;
31091 }
31092 }
31093
69133863
MGD
31094 /* Scan over the options table trying to find an exact match. */
31095 for (; opt->name != NULL; opt++)
f3bad469 31096 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 31097 {
d942732e
TP
31098 int i, nb_allowed_archs =
31099 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
69133863 31100 /* Check we can apply the extension to this architecture. */
d942732e
TP
31101 for (i = 0; i < nb_allowed_archs; i++)
31102 {
31103 /* Empty entry. */
31104 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any))
31105 continue;
c168ce07 31106 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *opt_set))
d942732e
TP
31107 break;
31108 }
31109 if (i == nb_allowed_archs)
69133863
MGD
31110 {
31111 as_bad (_("extension does not apply to the base architecture"));
31112 return FALSE;
31113 }
31114
31115 /* Add or remove the extension. */
31116 if (adding_value)
4d354d8b 31117 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value);
69133863 31118 else
4d354d8b 31119 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value);
69133863 31120
3d030cdb
TP
31121 /* Allowing Thumb division instructions for ARMv7 in autodetection
31122 rely on this break so that duplicate extensions (extensions
31123 with the same name as a previous extension in the list) are not
31124 considered for command-line parsing. */
c19d1205
ZW
31125 break;
31126 }
7ed4c4c5 31127
c19d1205
ZW
31128 if (opt->name == NULL)
31129 {
69133863
MGD
31130 /* Did we fail to find an extension because it wasn't specified in
31131 alphabetical order, or because it does not exist? */
31132
31133 for (opt = arm_extensions; opt->name != NULL; opt++)
f3bad469 31134 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
69133863
MGD
31135 break;
31136
31137 if (opt->name == NULL)
31138 as_bad (_("unknown architectural extension `%s'"), str);
31139 else
31140 as_bad (_("architectural extensions must be specified in "
31141 "alphabetical order"));
31142
c921be7d 31143 return FALSE;
c19d1205 31144 }
69133863
MGD
31145 else
31146 {
31147 /* We should skip the extension we've just matched the next time
31148 round. */
31149 opt++;
31150 }
7ed4c4c5 31151
c19d1205
ZW
31152 str = ext;
31153 };
7ed4c4c5 31154
c921be7d 31155 return TRUE;
c19d1205 31156}
7ed4c4c5 31157
c921be7d 31158static bfd_boolean
17b9d67d 31159arm_parse_cpu (const char *str)
7ed4c4c5 31160{
f3bad469 31161 const struct arm_cpu_option_table *opt;
82b8a785 31162 const char *ext = strchr (str, '+');
f3bad469 31163 size_t len;
7ed4c4c5 31164
c19d1205 31165 if (ext != NULL)
f3bad469 31166 len = ext - str;
7ed4c4c5 31167 else
f3bad469 31168 len = strlen (str);
7ed4c4c5 31169
f3bad469 31170 if (len == 0)
7ed4c4c5 31171 {
c19d1205 31172 as_bad (_("missing cpu name `%s'"), str);
c921be7d 31173 return FALSE;
7ed4c4c5
NC
31174 }
31175
c19d1205 31176 for (opt = arm_cpus; opt->name != NULL; opt++)
f3bad469 31177 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 31178 {
c168ce07 31179 mcpu_cpu_opt = &opt->value;
4d354d8b
TP
31180 if (mcpu_ext_opt == NULL)
31181 mcpu_ext_opt = XNEW (arm_feature_set);
31182 *mcpu_ext_opt = opt->ext;
e74cfd16 31183 mcpu_fpu_opt = &opt->default_fpu;
ee065d83 31184 if (opt->canonical_name)
ef8e6722
JW
31185 {
31186 gas_assert (sizeof selected_cpu_name > strlen (opt->canonical_name));
31187 strcpy (selected_cpu_name, opt->canonical_name);
31188 }
ee065d83
PB
31189 else
31190 {
f3bad469 31191 size_t i;
c921be7d 31192
ef8e6722
JW
31193 if (len >= sizeof selected_cpu_name)
31194 len = (sizeof selected_cpu_name) - 1;
31195
f3bad469 31196 for (i = 0; i < len; i++)
ee065d83
PB
31197 selected_cpu_name[i] = TOUPPER (opt->name[i]);
31198 selected_cpu_name[i] = 0;
31199 }
7ed4c4c5 31200
c19d1205 31201 if (ext != NULL)
34ef62f4 31202 return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL);
7ed4c4c5 31203
c921be7d 31204 return TRUE;
c19d1205 31205 }
7ed4c4c5 31206
c19d1205 31207 as_bad (_("unknown cpu `%s'"), str);
c921be7d 31208 return FALSE;
7ed4c4c5
NC
31209}
31210
c921be7d 31211static bfd_boolean
17b9d67d 31212arm_parse_arch (const char *str)
7ed4c4c5 31213{
e74cfd16 31214 const struct arm_arch_option_table *opt;
82b8a785 31215 const char *ext = strchr (str, '+');
f3bad469 31216 size_t len;
7ed4c4c5 31217
c19d1205 31218 if (ext != NULL)
f3bad469 31219 len = ext - str;
7ed4c4c5 31220 else
f3bad469 31221 len = strlen (str);
7ed4c4c5 31222
f3bad469 31223 if (len == 0)
7ed4c4c5 31224 {
c19d1205 31225 as_bad (_("missing architecture name `%s'"), str);
c921be7d 31226 return FALSE;
7ed4c4c5
NC
31227 }
31228
c19d1205 31229 for (opt = arm_archs; opt->name != NULL; opt++)
f3bad469 31230 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 31231 {
e74cfd16 31232 march_cpu_opt = &opt->value;
4d354d8b
TP
31233 if (march_ext_opt == NULL)
31234 march_ext_opt = XNEW (arm_feature_set);
31235 *march_ext_opt = arm_arch_none;
e74cfd16 31236 march_fpu_opt = &opt->default_fpu;
5f4273c7 31237 strcpy (selected_cpu_name, opt->name);
7ed4c4c5 31238
c19d1205 31239 if (ext != NULL)
34ef62f4
AV
31240 return arm_parse_extension (ext, march_cpu_opt, march_ext_opt,
31241 opt->ext_table);
7ed4c4c5 31242
c921be7d 31243 return TRUE;
c19d1205
ZW
31244 }
31245
31246 as_bad (_("unknown architecture `%s'\n"), str);
c921be7d 31247 return FALSE;
7ed4c4c5 31248}
eb043451 31249
c921be7d 31250static bfd_boolean
17b9d67d 31251arm_parse_fpu (const char * str)
c19d1205 31252{
69133863 31253 const struct arm_option_fpu_value_table * opt;
b99bd4ef 31254
c19d1205
ZW
31255 for (opt = arm_fpus; opt->name != NULL; opt++)
31256 if (streq (opt->name, str))
31257 {
e74cfd16 31258 mfpu_opt = &opt->value;
c921be7d 31259 return TRUE;
c19d1205 31260 }
b99bd4ef 31261
c19d1205 31262 as_bad (_("unknown floating point format `%s'\n"), str);
c921be7d 31263 return FALSE;
c19d1205
ZW
31264}
31265
c921be7d 31266static bfd_boolean
17b9d67d 31267arm_parse_float_abi (const char * str)
b99bd4ef 31268{
e74cfd16 31269 const struct arm_option_value_table * opt;
b99bd4ef 31270
c19d1205
ZW
31271 for (opt = arm_float_abis; opt->name != NULL; opt++)
31272 if (streq (opt->name, str))
31273 {
31274 mfloat_abi_opt = opt->value;
c921be7d 31275 return TRUE;
c19d1205 31276 }
cc8a6dd0 31277
c19d1205 31278 as_bad (_("unknown floating point abi `%s'\n"), str);
c921be7d 31279 return FALSE;
c19d1205 31280}
b99bd4ef 31281
c19d1205 31282#ifdef OBJ_ELF
c921be7d 31283static bfd_boolean
17b9d67d 31284arm_parse_eabi (const char * str)
c19d1205 31285{
e74cfd16 31286 const struct arm_option_value_table *opt;
cc8a6dd0 31287
c19d1205
ZW
31288 for (opt = arm_eabis; opt->name != NULL; opt++)
31289 if (streq (opt->name, str))
31290 {
31291 meabi_flags = opt->value;
c921be7d 31292 return TRUE;
c19d1205
ZW
31293 }
31294 as_bad (_("unknown EABI `%s'\n"), str);
c921be7d 31295 return FALSE;
c19d1205
ZW
31296}
31297#endif
cc8a6dd0 31298
c921be7d 31299static bfd_boolean
17b9d67d 31300arm_parse_it_mode (const char * str)
e07e6e58 31301{
c921be7d 31302 bfd_boolean ret = TRUE;
e07e6e58
NC
31303
31304 if (streq ("arm", str))
31305 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
31306 else if (streq ("thumb", str))
31307 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
31308 else if (streq ("always", str))
31309 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
31310 else if (streq ("never", str))
31311 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
31312 else
31313 {
31314 as_bad (_("unknown implicit IT mode `%s', should be "\
477330fc 31315 "arm, thumb, always, or never."), str);
c921be7d 31316 ret = FALSE;
e07e6e58
NC
31317 }
31318
31319 return ret;
31320}
31321
2e6976a8 31322static bfd_boolean
17b9d67d 31323arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED)
2e6976a8
DG
31324{
31325 codecomposer_syntax = TRUE;
31326 arm_comment_chars[0] = ';';
31327 arm_line_separator_chars[0] = 0;
31328 return TRUE;
31329}
31330
c19d1205
ZW
31331struct arm_long_option_table arm_long_opts[] =
31332{
31333 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
31334 arm_parse_cpu, NULL},
31335 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
31336 arm_parse_arch, NULL},
31337 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
31338 arm_parse_fpu, NULL},
31339 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
31340 arm_parse_float_abi, NULL},
31341#ifdef OBJ_ELF
7fac0536 31342 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
c19d1205
ZW
31343 arm_parse_eabi, NULL},
31344#endif
e07e6e58
NC
31345 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
31346 arm_parse_it_mode, NULL},
2e6976a8
DG
31347 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
31348 arm_ccs_mode, NULL},
c19d1205
ZW
31349 {NULL, NULL, 0, NULL}
31350};
cc8a6dd0 31351
c19d1205 31352int
17b9d67d 31353md_parse_option (int c, const char * arg)
c19d1205
ZW
31354{
31355 struct arm_option_table *opt;
e74cfd16 31356 const struct arm_legacy_option_table *fopt;
c19d1205 31357 struct arm_long_option_table *lopt;
b99bd4ef 31358
c19d1205 31359 switch (c)
b99bd4ef 31360 {
c19d1205
ZW
31361#ifdef OPTION_EB
31362 case OPTION_EB:
31363 target_big_endian = 1;
31364 break;
31365#endif
cc8a6dd0 31366
c19d1205
ZW
31367#ifdef OPTION_EL
31368 case OPTION_EL:
31369 target_big_endian = 0;
31370 break;
31371#endif
b99bd4ef 31372
845b51d6
PB
31373 case OPTION_FIX_V4BX:
31374 fix_v4bx = TRUE;
31375 break;
31376
18a20338
CL
31377#ifdef OBJ_ELF
31378 case OPTION_FDPIC:
31379 arm_fdpic = TRUE;
31380 break;
31381#endif /* OBJ_ELF */
31382
c19d1205
ZW
31383 case 'a':
31384 /* Listing option. Just ignore these, we don't support additional
31385 ones. */
31386 return 0;
b99bd4ef 31387
c19d1205
ZW
31388 default:
31389 for (opt = arm_opts; opt->option != NULL; opt++)
31390 {
31391 if (c == opt->option[0]
31392 && ((arg == NULL && opt->option[1] == 0)
31393 || streq (arg, opt->option + 1)))
31394 {
c19d1205 31395 /* If the option is deprecated, tell the user. */
278df34e 31396 if (warn_on_deprecated && opt->deprecated != NULL)
c19d1205
ZW
31397 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
31398 arg ? arg : "", _(opt->deprecated));
b99bd4ef 31399
c19d1205
ZW
31400 if (opt->var != NULL)
31401 *opt->var = opt->value;
cc8a6dd0 31402
c19d1205
ZW
31403 return 1;
31404 }
31405 }
b99bd4ef 31406
e74cfd16
PB
31407 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
31408 {
31409 if (c == fopt->option[0]
31410 && ((arg == NULL && fopt->option[1] == 0)
31411 || streq (arg, fopt->option + 1)))
31412 {
e74cfd16 31413 /* If the option is deprecated, tell the user. */
278df34e 31414 if (warn_on_deprecated && fopt->deprecated != NULL)
e74cfd16
PB
31415 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
31416 arg ? arg : "", _(fopt->deprecated));
e74cfd16
PB
31417
31418 if (fopt->var != NULL)
31419 *fopt->var = &fopt->value;
31420
31421 return 1;
31422 }
31423 }
31424
c19d1205
ZW
31425 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
31426 {
31427 /* These options are expected to have an argument. */
31428 if (c == lopt->option[0]
31429 && arg != NULL
31430 && strncmp (arg, lopt->option + 1,
31431 strlen (lopt->option + 1)) == 0)
31432 {
c19d1205 31433 /* If the option is deprecated, tell the user. */
278df34e 31434 if (warn_on_deprecated && lopt->deprecated != NULL)
c19d1205
ZW
31435 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
31436 _(lopt->deprecated));
b99bd4ef 31437
c19d1205
ZW
31438 /* Call the sup-option parser. */
31439 return lopt->func (arg + strlen (lopt->option) - 1);
31440 }
31441 }
a737bd4d 31442
c19d1205
ZW
31443 return 0;
31444 }
a394c00f 31445
c19d1205
ZW
31446 return 1;
31447}
a394c00f 31448
c19d1205
ZW
31449void
31450md_show_usage (FILE * fp)
a394c00f 31451{
c19d1205
ZW
31452 struct arm_option_table *opt;
31453 struct arm_long_option_table *lopt;
a394c00f 31454
c19d1205 31455 fprintf (fp, _(" ARM-specific assembler options:\n"));
a394c00f 31456
c19d1205
ZW
31457 for (opt = arm_opts; opt->option != NULL; opt++)
31458 if (opt->help != NULL)
31459 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
a394c00f 31460
c19d1205
ZW
31461 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
31462 if (lopt->help != NULL)
31463 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
a394c00f 31464
c19d1205
ZW
31465#ifdef OPTION_EB
31466 fprintf (fp, _("\
31467 -EB assemble code for a big-endian cpu\n"));
a394c00f
NC
31468#endif
31469
c19d1205
ZW
31470#ifdef OPTION_EL
31471 fprintf (fp, _("\
31472 -EL assemble code for a little-endian cpu\n"));
a737bd4d 31473#endif
845b51d6
PB
31474
31475 fprintf (fp, _("\
31476 --fix-v4bx Allow BX in ARMv4 code\n"));
18a20338
CL
31477
31478#ifdef OBJ_ELF
31479 fprintf (fp, _("\
31480 --fdpic generate an FDPIC object file\n"));
31481#endif /* OBJ_ELF */
c19d1205 31482}
ee065d83 31483
ee065d83 31484#ifdef OBJ_ELF
0198d5e6 31485
62b3e311
PB
31486typedef struct
31487{
31488 int val;
31489 arm_feature_set flags;
31490} cpu_arch_ver_table;
31491
2c6b98ea
TP
31492/* Mapping from CPU features to EABI CPU arch values. Table must be sorted
31493 chronologically for architectures, with an exception for ARMv6-M and
31494 ARMv6S-M due to legacy reasons. No new architecture should have a
31495 special case. This allows for build attribute selection results to be
31496 stable when new architectures are added. */
62b3e311
PB
31497static const cpu_arch_ver_table cpu_arch_ver[] =
31498{
031254f2
AV
31499 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1},
31500 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2},
31501 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S},
31502 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3},
31503 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M},
31504 {TAG_CPU_ARCH_V4, ARM_ARCH_V4xM},
31505 {TAG_CPU_ARCH_V4, ARM_ARCH_V4},
31506 {TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM},
31507 {TAG_CPU_ARCH_V4T, ARM_ARCH_V4T},
31508 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM},
31509 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5},
31510 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM},
31511 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5T},
31512 {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP},
31513 {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE},
31514 {TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ},
31515 {TAG_CPU_ARCH_V6, ARM_ARCH_V6},
31516 {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z},
31517 {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ},
31518 {TAG_CPU_ARCH_V6K, ARM_ARCH_V6K},
31519 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2},
31520 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2},
31521 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2},
31522 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2},
2c6b98ea
TP
31523
31524 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
31525 always selected build attributes to match those of ARMv6-M
31526 (resp. ARMv6S-M). However, due to these architectures being a strict
31527 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
31528 would be selected when fully respecting chronology of architectures.
31529 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
31530 move them before ARMv7 architectures. */
031254f2
AV
31531 {TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M},
31532 {TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM},
31533
31534 {TAG_CPU_ARCH_V7, ARM_ARCH_V7},
31535 {TAG_CPU_ARCH_V7, ARM_ARCH_V7A},
31536 {TAG_CPU_ARCH_V7, ARM_ARCH_V7R},
31537 {TAG_CPU_ARCH_V7, ARM_ARCH_V7M},
31538 {TAG_CPU_ARCH_V7, ARM_ARCH_V7VE},
31539 {TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM},
31540 {TAG_CPU_ARCH_V8, ARM_ARCH_V8A},
31541 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A},
31542 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A},
31543 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A},
31544 {TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE},
31545 {TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN},
31546 {TAG_CPU_ARCH_V8R, ARM_ARCH_V8R},
31547 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A},
31548 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A},
31549 {TAG_CPU_ARCH_V8_1M_MAIN, ARM_ARCH_V8_1M_MAIN},
31550 {-1, ARM_ARCH_NONE}
62b3e311
PB
31551};
31552
ee3c0378 31553/* Set an attribute if it has not already been set by the user. */
0198d5e6 31554
ee3c0378
AS
31555static void
31556aeabi_set_attribute_int (int tag, int value)
31557{
31558 if (tag < 1
31559 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
31560 || !attributes_set_explicitly[tag])
31561 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
31562}
31563
31564static void
31565aeabi_set_attribute_string (int tag, const char *value)
31566{
31567 if (tag < 1
31568 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
31569 || !attributes_set_explicitly[tag])
31570 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
31571}
31572
2c6b98ea
TP
31573/* Return whether features in the *NEEDED feature set are available via
31574 extensions for the architecture whose feature set is *ARCH_FSET. */
0198d5e6 31575
2c6b98ea
TP
31576static bfd_boolean
31577have_ext_for_needed_feat_p (const arm_feature_set *arch_fset,
31578 const arm_feature_set *needed)
31579{
31580 int i, nb_allowed_archs;
31581 arm_feature_set ext_fset;
31582 const struct arm_option_extension_value_table *opt;
31583
31584 ext_fset = arm_arch_none;
31585 for (opt = arm_extensions; opt->name != NULL; opt++)
31586 {
31587 /* Extension does not provide any feature we need. */
31588 if (!ARM_CPU_HAS_FEATURE (*needed, opt->merge_value))
31589 continue;
31590
31591 nb_allowed_archs =
31592 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
31593 for (i = 0; i < nb_allowed_archs; i++)
31594 {
31595 /* Empty entry. */
31596 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_arch_any))
31597 break;
31598
31599 /* Extension is available, add it. */
31600 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *arch_fset))
31601 ARM_MERGE_FEATURE_SETS (ext_fset, ext_fset, opt->merge_value);
31602 }
31603 }
31604
31605 /* Can we enable all features in *needed? */
31606 return ARM_FSET_CPU_SUBSET (*needed, ext_fset);
31607}
31608
31609/* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
31610 a given architecture feature set *ARCH_EXT_FSET including extension feature
31611 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
31612 - if true, check for an exact match of the architecture modulo extensions;
31613 - otherwise, select build attribute value of the first superset
31614 architecture released so that results remains stable when new architectures
31615 are added.
31616 For -march/-mcpu=all the build attribute value of the most featureful
31617 architecture is returned. Tag_CPU_arch_profile result is returned in
31618 PROFILE. */
0198d5e6 31619
2c6b98ea
TP
31620static int
31621get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset,
31622 const arm_feature_set *ext_fset,
31623 char *profile, int exact_match)
31624{
31625 arm_feature_set arch_fset;
31626 const cpu_arch_ver_table *p_ver, *p_ver_ret = NULL;
31627
31628 /* Select most featureful architecture with all its extensions if building
31629 for -march=all as the feature sets used to set build attributes. */
31630 if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any))
31631 {
31632 /* Force revisiting of decision for each new architecture. */
031254f2 31633 gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8_1M_MAIN);
2c6b98ea
TP
31634 *profile = 'A';
31635 return TAG_CPU_ARCH_V8;
31636 }
31637
31638 ARM_CLEAR_FEATURE (arch_fset, *arch_ext_fset, *ext_fset);
31639
31640 for (p_ver = cpu_arch_ver; p_ver->val != -1; p_ver++)
31641 {
31642 arm_feature_set known_arch_fset;
31643
31644 ARM_CLEAR_FEATURE (known_arch_fset, p_ver->flags, fpu_any);
31645 if (exact_match)
31646 {
31647 /* Base architecture match user-specified architecture and
31648 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
31649 if (ARM_FEATURE_EQUAL (*arch_ext_fset, known_arch_fset))
31650 {
31651 p_ver_ret = p_ver;
31652 goto found;
31653 }
31654 /* Base architecture match user-specified architecture only
31655 (eg. ARMv6-M in the same case as above). Record it in case we
31656 find a match with above condition. */
31657 else if (p_ver_ret == NULL
31658 && ARM_FEATURE_EQUAL (arch_fset, known_arch_fset))
31659 p_ver_ret = p_ver;
31660 }
31661 else
31662 {
31663
31664 /* Architecture has all features wanted. */
31665 if (ARM_FSET_CPU_SUBSET (arch_fset, known_arch_fset))
31666 {
31667 arm_feature_set added_fset;
31668
31669 /* Compute features added by this architecture over the one
31670 recorded in p_ver_ret. */
31671 if (p_ver_ret != NULL)
31672 ARM_CLEAR_FEATURE (added_fset, known_arch_fset,
31673 p_ver_ret->flags);
31674 /* First architecture that match incl. with extensions, or the
31675 only difference in features over the recorded match is
31676 features that were optional and are now mandatory. */
31677 if (p_ver_ret == NULL
31678 || ARM_FSET_CPU_SUBSET (added_fset, arch_fset))
31679 {
31680 p_ver_ret = p_ver;
31681 goto found;
31682 }
31683 }
31684 else if (p_ver_ret == NULL)
31685 {
31686 arm_feature_set needed_ext_fset;
31687
31688 ARM_CLEAR_FEATURE (needed_ext_fset, arch_fset, known_arch_fset);
31689
31690 /* Architecture has all features needed when using some
31691 extensions. Record it and continue searching in case there
31692 exist an architecture providing all needed features without
31693 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
31694 OS extension). */
31695 if (have_ext_for_needed_feat_p (&known_arch_fset,
31696 &needed_ext_fset))
31697 p_ver_ret = p_ver;
31698 }
31699 }
31700 }
31701
31702 if (p_ver_ret == NULL)
31703 return -1;
31704
31705found:
31706 /* Tag_CPU_arch_profile. */
31707 if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7a)
31708 || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8)
31709 || (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_atomics)
31710 && !ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8m_m_only)))
31711 *profile = 'A';
31712 else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7r))
31713 *profile = 'R';
31714 else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_m))
31715 *profile = 'M';
31716 else
31717 *profile = '\0';
31718 return p_ver_ret->val;
31719}
31720
ee065d83 31721/* Set the public EABI object attributes. */
0198d5e6 31722
c168ce07 31723static void
ee065d83
PB
31724aeabi_set_public_attributes (void)
31725{
b90d5ba0 31726 char profile = '\0';
2c6b98ea 31727 int arch = -1;
90ec0d68 31728 int virt_sec = 0;
bca38921 31729 int fp16_optional = 0;
2c6b98ea
TP
31730 int skip_exact_match = 0;
31731 arm_feature_set flags, flags_arch, flags_ext;
ee065d83 31732
54bab281
TP
31733 /* Autodetection mode, choose the architecture based the instructions
31734 actually used. */
31735 if (no_cpu_selected ())
31736 {
31737 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
ddd7f988 31738
54bab281
TP
31739 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
31740 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
ddd7f988 31741
54bab281
TP
31742 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
31743 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
ddd7f988 31744
54bab281 31745 /* Code run during relaxation relies on selected_cpu being set. */
4d354d8b
TP
31746 ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
31747 flags_ext = arm_arch_none;
31748 ARM_CLEAR_FEATURE (selected_arch, flags_arch, flags_ext);
31749 selected_ext = flags_ext;
54bab281
TP
31750 selected_cpu = flags;
31751 }
31752 /* Otherwise, choose the architecture based on the capabilities of the
31753 requested cpu. */
31754 else
4d354d8b
TP
31755 {
31756 ARM_MERGE_FEATURE_SETS (flags_arch, selected_arch, selected_ext);
31757 ARM_CLEAR_FEATURE (flags_arch, flags_arch, fpu_any);
31758 flags_ext = selected_ext;
31759 flags = selected_cpu;
31760 }
31761 ARM_MERGE_FEATURE_SETS (flags, flags, selected_fpu);
7f78eb34 31762
ddd7f988 31763 /* Allow the user to override the reported architecture. */
4d354d8b 31764 if (!ARM_FEATURE_ZERO (selected_object_arch))
7a1d4c38 31765 {
4d354d8b 31766 ARM_CLEAR_FEATURE (flags_arch, selected_object_arch, fpu_any);
2c6b98ea 31767 flags_ext = arm_arch_none;
7a1d4c38 31768 }
2c6b98ea 31769 else
4d354d8b 31770 skip_exact_match = ARM_FEATURE_EQUAL (selected_cpu, arm_arch_any);
2c6b98ea
TP
31771
31772 /* When this function is run again after relaxation has happened there is no
31773 way to determine whether an architecture or CPU was specified by the user:
31774 - selected_cpu is set above for relaxation to work;
31775 - march_cpu_opt is not set if only -mcpu or .cpu is used;
31776 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
31777 Therefore, if not in -march=all case we first try an exact match and fall
31778 back to autodetection. */
31779 if (!skip_exact_match)
31780 arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 1);
31781 if (arch == -1)
31782 arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 0);
31783 if (arch == -1)
31784 as_bad (_("no architecture contains all the instructions used\n"));
9e3c6df6 31785
ee065d83
PB
31786 /* Tag_CPU_name. */
31787 if (selected_cpu_name[0])
31788 {
91d6fa6a 31789 char *q;
ee065d83 31790
91d6fa6a
NC
31791 q = selected_cpu_name;
31792 if (strncmp (q, "armv", 4) == 0)
ee065d83
PB
31793 {
31794 int i;
5f4273c7 31795
91d6fa6a
NC
31796 q += 4;
31797 for (i = 0; q[i]; i++)
31798 q[i] = TOUPPER (q[i]);
ee065d83 31799 }
91d6fa6a 31800 aeabi_set_attribute_string (Tag_CPU_name, q);
ee065d83 31801 }
62f3b8c8 31802
ee065d83 31803 /* Tag_CPU_arch. */
ee3c0378 31804 aeabi_set_attribute_int (Tag_CPU_arch, arch);
62f3b8c8 31805
62b3e311 31806 /* Tag_CPU_arch_profile. */
69239280
MGD
31807 if (profile != '\0')
31808 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
62f3b8c8 31809
15afaa63 31810 /* Tag_DSP_extension. */
4d354d8b 31811 if (ARM_CPU_HAS_FEATURE (selected_ext, arm_ext_dsp))
6c290d53 31812 aeabi_set_attribute_int (Tag_DSP_extension, 1);
15afaa63 31813
2c6b98ea 31814 ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
ee065d83 31815 /* Tag_ARM_ISA_use. */
ee3c0378 31816 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
2c6b98ea 31817 || ARM_FEATURE_ZERO (flags_arch))
ee3c0378 31818 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
62f3b8c8 31819
ee065d83 31820 /* Tag_THUMB_ISA_use. */
ee3c0378 31821 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
2c6b98ea 31822 || ARM_FEATURE_ZERO (flags_arch))
4ed7ed8d
TP
31823 {
31824 int thumb_isa_use;
31825
31826 if (!ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
16a1fa25 31827 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only))
4ed7ed8d
TP
31828 thumb_isa_use = 3;
31829 else if (ARM_CPU_HAS_FEATURE (flags, arm_arch_t2))
31830 thumb_isa_use = 2;
31831 else
31832 thumb_isa_use = 1;
31833 aeabi_set_attribute_int (Tag_THUMB_ISA_use, thumb_isa_use);
31834 }
62f3b8c8 31835
ee065d83 31836 /* Tag_VFP_arch. */
a715796b
TG
31837 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd))
31838 aeabi_set_attribute_int (Tag_VFP_arch,
31839 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
31840 ? 7 : 8);
bca38921 31841 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
62f3b8c8
PB
31842 aeabi_set_attribute_int (Tag_VFP_arch,
31843 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
31844 ? 5 : 6);
31845 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
bca38921
MGD
31846 {
31847 fp16_optional = 1;
31848 aeabi_set_attribute_int (Tag_VFP_arch, 3);
31849 }
ada65aa3 31850 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
bca38921
MGD
31851 {
31852 aeabi_set_attribute_int (Tag_VFP_arch, 4);
31853 fp16_optional = 1;
31854 }
ee3c0378
AS
31855 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
31856 aeabi_set_attribute_int (Tag_VFP_arch, 2);
31857 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
477330fc 31858 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
ee3c0378 31859 aeabi_set_attribute_int (Tag_VFP_arch, 1);
62f3b8c8 31860
4547cb56
NC
31861 /* Tag_ABI_HardFP_use. */
31862 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
31863 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
31864 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
31865
ee065d83 31866 /* Tag_WMMX_arch. */
ee3c0378
AS
31867 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
31868 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
31869 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
31870 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
62f3b8c8 31871
ee3c0378 31872 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
9411fd44
MW
31873 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v8_1))
31874 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 4);
31875 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
bca38921
MGD
31876 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
31877 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
31878 {
31879 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
31880 {
31881 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
31882 }
31883 else
31884 {
31885 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
31886 fp16_optional = 1;
31887 }
31888 }
fa94de6b 31889
a7ad558c
AV
31890 if (ARM_CPU_HAS_FEATURE (flags, mve_fp_ext))
31891 aeabi_set_attribute_int (Tag_MVE_arch, 2);
31892 else if (ARM_CPU_HAS_FEATURE (flags, mve_ext))
31893 aeabi_set_attribute_int (Tag_MVE_arch, 1);
31894
ee3c0378 31895 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
bca38921 31896 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
ee3c0378 31897 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
4547cb56 31898
69239280
MGD
31899 /* Tag_DIV_use.
31900
31901 We set Tag_DIV_use to two when integer divide instructions have been used
31902 in ARM state, or when Thumb integer divide instructions have been used,
31903 but we have no architecture profile set, nor have we any ARM instructions.
31904
4ed7ed8d
TP
31905 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
31906 by the base architecture.
bca38921 31907
69239280 31908 For new architectures we will have to check these tests. */
031254f2 31909 gas_assert (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
4ed7ed8d
TP
31910 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
31911 || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
bca38921
MGD
31912 aeabi_set_attribute_int (Tag_DIV_use, 0);
31913 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
31914 || (profile == '\0'
31915 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
31916 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
eea54501 31917 aeabi_set_attribute_int (Tag_DIV_use, 2);
60e5ef9f
MGD
31918
31919 /* Tag_MP_extension_use. */
31920 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
31921 aeabi_set_attribute_int (Tag_MPextension_use, 1);
f4c65163
MGD
31922
31923 /* Tag Virtualization_use. */
31924 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
90ec0d68
MGD
31925 virt_sec |= 1;
31926 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
31927 virt_sec |= 2;
31928 if (virt_sec != 0)
31929 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
ee065d83
PB
31930}
31931
c168ce07
TP
31932/* Post relaxation hook. Recompute ARM attributes now that relaxation is
31933 finished and free extension feature bits which will not be used anymore. */
0198d5e6 31934
c168ce07
TP
31935void
31936arm_md_post_relax (void)
31937{
31938 aeabi_set_public_attributes ();
4d354d8b
TP
31939 XDELETE (mcpu_ext_opt);
31940 mcpu_ext_opt = NULL;
31941 XDELETE (march_ext_opt);
31942 march_ext_opt = NULL;
c168ce07
TP
31943}
31944
104d59d1 31945/* Add the default contents for the .ARM.attributes section. */
0198d5e6 31946
ee065d83
PB
31947void
31948arm_md_end (void)
31949{
ee065d83
PB
31950 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
31951 return;
31952
31953 aeabi_set_public_attributes ();
ee065d83 31954}
8463be01 31955#endif /* OBJ_ELF */
ee065d83 31956
ee065d83
PB
31957/* Parse a .cpu directive. */
31958
31959static void
31960s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
31961{
e74cfd16 31962 const struct arm_cpu_option_table *opt;
ee065d83
PB
31963 char *name;
31964 char saved_char;
31965
31966 name = input_line_pointer;
5f4273c7 31967 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB
31968 input_line_pointer++;
31969 saved_char = *input_line_pointer;
31970 *input_line_pointer = 0;
31971
31972 /* Skip the first "all" entry. */
31973 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
31974 if (streq (opt->name, name))
31975 {
4d354d8b
TP
31976 selected_arch = opt->value;
31977 selected_ext = opt->ext;
31978 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
ee065d83 31979 if (opt->canonical_name)
5f4273c7 31980 strcpy (selected_cpu_name, opt->canonical_name);
ee065d83
PB
31981 else
31982 {
31983 int i;
31984 for (i = 0; opt->name[i]; i++)
31985 selected_cpu_name[i] = TOUPPER (opt->name[i]);
f3bad469 31986
ee065d83
PB
31987 selected_cpu_name[i] = 0;
31988 }
4d354d8b
TP
31989 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
31990
ee065d83
PB
31991 *input_line_pointer = saved_char;
31992 demand_empty_rest_of_line ();
31993 return;
31994 }
31995 as_bad (_("unknown cpu `%s'"), name);
31996 *input_line_pointer = saved_char;
31997 ignore_rest_of_line ();
31998}
31999
ee065d83
PB
32000/* Parse a .arch directive. */
32001
32002static void
32003s_arm_arch (int ignored ATTRIBUTE_UNUSED)
32004{
e74cfd16 32005 const struct arm_arch_option_table *opt;
ee065d83
PB
32006 char saved_char;
32007 char *name;
32008
32009 name = input_line_pointer;
5f4273c7 32010 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB
32011 input_line_pointer++;
32012 saved_char = *input_line_pointer;
32013 *input_line_pointer = 0;
32014
32015 /* Skip the first "all" entry. */
32016 for (opt = arm_archs + 1; opt->name != NULL; opt++)
32017 if (streq (opt->name, name))
32018 {
4d354d8b
TP
32019 selected_arch = opt->value;
32020 selected_ext = arm_arch_none;
32021 selected_cpu = selected_arch;
5f4273c7 32022 strcpy (selected_cpu_name, opt->name);
4d354d8b 32023 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
ee065d83
PB
32024 *input_line_pointer = saved_char;
32025 demand_empty_rest_of_line ();
32026 return;
32027 }
32028
32029 as_bad (_("unknown architecture `%s'\n"), name);
32030 *input_line_pointer = saved_char;
32031 ignore_rest_of_line ();
32032}
32033
7a1d4c38
PB
32034/* Parse a .object_arch directive. */
32035
32036static void
32037s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
32038{
32039 const struct arm_arch_option_table *opt;
32040 char saved_char;
32041 char *name;
32042
32043 name = input_line_pointer;
5f4273c7 32044 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
7a1d4c38
PB
32045 input_line_pointer++;
32046 saved_char = *input_line_pointer;
32047 *input_line_pointer = 0;
32048
32049 /* Skip the first "all" entry. */
32050 for (opt = arm_archs + 1; opt->name != NULL; opt++)
32051 if (streq (opt->name, name))
32052 {
4d354d8b 32053 selected_object_arch = opt->value;
7a1d4c38
PB
32054 *input_line_pointer = saved_char;
32055 demand_empty_rest_of_line ();
32056 return;
32057 }
32058
32059 as_bad (_("unknown architecture `%s'\n"), name);
32060 *input_line_pointer = saved_char;
32061 ignore_rest_of_line ();
32062}
32063
69133863
MGD
32064/* Parse a .arch_extension directive. */
32065
32066static void
32067s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
32068{
32069 const struct arm_option_extension_value_table *opt;
32070 char saved_char;
32071 char *name;
32072 int adding_value = 1;
32073
32074 name = input_line_pointer;
32075 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
32076 input_line_pointer++;
32077 saved_char = *input_line_pointer;
32078 *input_line_pointer = 0;
32079
32080 if (strlen (name) >= 2
32081 && strncmp (name, "no", 2) == 0)
32082 {
32083 adding_value = 0;
32084 name += 2;
32085 }
32086
32087 for (opt = arm_extensions; opt->name != NULL; opt++)
32088 if (streq (opt->name, name))
32089 {
d942732e
TP
32090 int i, nb_allowed_archs =
32091 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[i]);
32092 for (i = 0; i < nb_allowed_archs; i++)
32093 {
32094 /* Empty entry. */
4d354d8b 32095 if (ARM_CPU_IS_ANY (opt->allowed_archs[i]))
d942732e 32096 continue;
4d354d8b 32097 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], selected_arch))
d942732e
TP
32098 break;
32099 }
32100
32101 if (i == nb_allowed_archs)
69133863
MGD
32102 {
32103 as_bad (_("architectural extension `%s' is not allowed for the "
32104 "current base architecture"), name);
32105 break;
32106 }
32107
32108 if (adding_value)
4d354d8b 32109 ARM_MERGE_FEATURE_SETS (selected_ext, selected_ext,
5a70a223 32110 opt->merge_value);
69133863 32111 else
4d354d8b 32112 ARM_CLEAR_FEATURE (selected_ext, selected_ext, opt->clear_value);
69133863 32113
4d354d8b
TP
32114 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
32115 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
69133863
MGD
32116 *input_line_pointer = saved_char;
32117 demand_empty_rest_of_line ();
3d030cdb
TP
32118 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
32119 on this return so that duplicate extensions (extensions with the
32120 same name as a previous extension in the list) are not considered
32121 for command-line parsing. */
69133863
MGD
32122 return;
32123 }
32124
32125 if (opt->name == NULL)
e673710a 32126 as_bad (_("unknown architecture extension `%s'\n"), name);
69133863
MGD
32127
32128 *input_line_pointer = saved_char;
32129 ignore_rest_of_line ();
32130}
32131
ee065d83
PB
32132/* Parse a .fpu directive. */
32133
32134static void
32135s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
32136{
69133863 32137 const struct arm_option_fpu_value_table *opt;
ee065d83
PB
32138 char saved_char;
32139 char *name;
32140
32141 name = input_line_pointer;
5f4273c7 32142 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB
32143 input_line_pointer++;
32144 saved_char = *input_line_pointer;
32145 *input_line_pointer = 0;
5f4273c7 32146
ee065d83
PB
32147 for (opt = arm_fpus; opt->name != NULL; opt++)
32148 if (streq (opt->name, name))
32149 {
4d354d8b
TP
32150 selected_fpu = opt->value;
32151#ifndef CPU_DEFAULT
32152 if (no_cpu_selected ())
32153 ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
32154 else
32155#endif
32156 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
ee065d83
PB
32157 *input_line_pointer = saved_char;
32158 demand_empty_rest_of_line ();
32159 return;
32160 }
32161
32162 as_bad (_("unknown floating point format `%s'\n"), name);
32163 *input_line_pointer = saved_char;
32164 ignore_rest_of_line ();
32165}
ee065d83 32166
794ba86a 32167/* Copy symbol information. */
f31fef98 32168
794ba86a
DJ
32169void
32170arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
32171{
32172 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
32173}
e04befd0 32174
f31fef98 32175#ifdef OBJ_ELF
e04befd0
AS
32176/* Given a symbolic attribute NAME, return the proper integer value.
32177 Returns -1 if the attribute is not known. */
f31fef98 32178
e04befd0
AS
32179int
32180arm_convert_symbolic_attribute (const char *name)
32181{
f31fef98
NC
32182 static const struct
32183 {
32184 const char * name;
32185 const int tag;
32186 }
32187 attribute_table[] =
32188 {
32189 /* When you modify this table you should
32190 also modify the list in doc/c-arm.texi. */
e04befd0 32191#define T(tag) {#tag, tag}
f31fef98
NC
32192 T (Tag_CPU_raw_name),
32193 T (Tag_CPU_name),
32194 T (Tag_CPU_arch),
32195 T (Tag_CPU_arch_profile),
32196 T (Tag_ARM_ISA_use),
32197 T (Tag_THUMB_ISA_use),
75375b3e 32198 T (Tag_FP_arch),
f31fef98
NC
32199 T (Tag_VFP_arch),
32200 T (Tag_WMMX_arch),
32201 T (Tag_Advanced_SIMD_arch),
32202 T (Tag_PCS_config),
32203 T (Tag_ABI_PCS_R9_use),
32204 T (Tag_ABI_PCS_RW_data),
32205 T (Tag_ABI_PCS_RO_data),
32206 T (Tag_ABI_PCS_GOT_use),
32207 T (Tag_ABI_PCS_wchar_t),
32208 T (Tag_ABI_FP_rounding),
32209 T (Tag_ABI_FP_denormal),
32210 T (Tag_ABI_FP_exceptions),
32211 T (Tag_ABI_FP_user_exceptions),
32212 T (Tag_ABI_FP_number_model),
75375b3e 32213 T (Tag_ABI_align_needed),
f31fef98 32214 T (Tag_ABI_align8_needed),
75375b3e 32215 T (Tag_ABI_align_preserved),
f31fef98
NC
32216 T (Tag_ABI_align8_preserved),
32217 T (Tag_ABI_enum_size),
32218 T (Tag_ABI_HardFP_use),
32219 T (Tag_ABI_VFP_args),
32220 T (Tag_ABI_WMMX_args),
32221 T (Tag_ABI_optimization_goals),
32222 T (Tag_ABI_FP_optimization_goals),
32223 T (Tag_compatibility),
32224 T (Tag_CPU_unaligned_access),
75375b3e 32225 T (Tag_FP_HP_extension),
f31fef98
NC
32226 T (Tag_VFP_HP_extension),
32227 T (Tag_ABI_FP_16bit_format),
cd21e546
MGD
32228 T (Tag_MPextension_use),
32229 T (Tag_DIV_use),
f31fef98
NC
32230 T (Tag_nodefaults),
32231 T (Tag_also_compatible_with),
32232 T (Tag_conformance),
32233 T (Tag_T2EE_use),
32234 T (Tag_Virtualization_use),
15afaa63 32235 T (Tag_DSP_extension),
a7ad558c 32236 T (Tag_MVE_arch),
cd21e546 32237 /* We deliberately do not include Tag_MPextension_use_legacy. */
e04befd0 32238#undef T
f31fef98 32239 };
e04befd0
AS
32240 unsigned int i;
32241
32242 if (name == NULL)
32243 return -1;
32244
f31fef98 32245 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
c921be7d 32246 if (streq (name, attribute_table[i].name))
e04befd0
AS
32247 return attribute_table[i].tag;
32248
32249 return -1;
32250}
267bf995 32251
93ef582d
NC
32252/* Apply sym value for relocations only in the case that they are for
32253 local symbols in the same segment as the fixup and you have the
32254 respective architectural feature for blx and simple switches. */
0198d5e6 32255
267bf995 32256int
93ef582d 32257arm_apply_sym_value (struct fix * fixP, segT this_seg)
267bf995
RR
32258{
32259 if (fixP->fx_addsy
32260 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
93ef582d
NC
32261 /* PR 17444: If the local symbol is in a different section then a reloc
32262 will always be generated for it, so applying the symbol value now
32263 will result in a double offset being stored in the relocation. */
32264 && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg)
34e77a92 32265 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
267bf995
RR
32266 {
32267 switch (fixP->fx_r_type)
32268 {
32269 case BFD_RELOC_ARM_PCREL_BLX:
32270 case BFD_RELOC_THUMB_PCREL_BRANCH23:
32271 if (ARM_IS_FUNC (fixP->fx_addsy))
32272 return 1;
32273 break;
32274
32275 case BFD_RELOC_ARM_PCREL_CALL:
32276 case BFD_RELOC_THUMB_PCREL_BLX:
32277 if (THUMB_IS_FUNC (fixP->fx_addsy))
93ef582d 32278 return 1;
267bf995
RR
32279 break;
32280
32281 default:
32282 break;
32283 }
32284
32285 }
32286 return 0;
32287}
f31fef98 32288#endif /* OBJ_ELF */
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