2005-09-30 Paul Brook <paul@codesourcery.com>
[deliverable/binutils-gdb.git] / gas / config / tc-arm.c
CommitLineData
b99bd4ef 1/* tc-arm.c -- Assemble for the ARM
f17c130b
AM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005
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4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
22d9c8c5 7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
34920d91
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8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
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10
11 This file is part of GAS, the GNU Assembler.
12
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
16 any later version.
17
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
c19d1205 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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NC
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
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25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
26 02110-1301, USA. */
b99bd4ef 27
b99bd4ef 28#include <string.h>
c19d1205 29#define NO_RELOC 0
b99bd4ef 30#include "as.h"
3882b010 31#include "safe-ctype.h"
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32
33/* Need TARGET_CPU. */
34#include "config.h"
35#include "subsegs.h"
36#include "obstack.h"
37#include "symbols.h"
38#include "listing.h"
39
f263249b
RE
40#include "opcode/arm.h"
41
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42#ifdef OBJ_ELF
43#include "elf/arm.h"
44#include "dwarf2dbg.h"
a394c00f 45#include "dw2gencfi.h"
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46#endif
47
7ed4c4c5 48/* XXX Set this to 1 after the next binutils release. */
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49#define WARN_DEPRECATED 0
50
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51#ifdef OBJ_ELF
52/* Must be at least the size of the largest unwind opcode (currently two). */
53#define ARM_OPCODE_CHUNK_SIZE 8
54
55/* This structure holds the unwinding state. */
56
57static struct
58{
c19d1205
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59 symbolS * proc_start;
60 symbolS * table_entry;
61 symbolS * personality_routine;
62 int personality_index;
7ed4c4c5 63 /* The segment containing the function. */
c19d1205
ZW
64 segT saved_seg;
65 subsegT saved_subseg;
7ed4c4c5
NC
66 /* Opcodes generated from this function. */
67 unsigned char * opcodes;
c19d1205
ZW
68 int opcode_count;
69 int opcode_alloc;
7ed4c4c5 70 /* The number of bytes pushed to the stack. */
c19d1205 71 offsetT frame_size;
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NC
72 /* We don't add stack adjustment opcodes immediately so that we can merge
73 multiple adjustments. We can also omit the final adjustment
74 when using a frame pointer. */
c19d1205 75 offsetT pending_offset;
7ed4c4c5 76 /* These two fields are set by both unwind_movsp and unwind_setfp. They
c19d1205
ZW
77 hold the reg+offset to use when restoring sp from a frame pointer. */
78 offsetT fp_offset;
79 int fp_reg;
7ed4c4c5 80 /* Nonzero if an unwind_setfp directive has been seen. */
c19d1205 81 unsigned fp_used:1;
7ed4c4c5 82 /* Nonzero if the last opcode restores sp from fp_reg. */
c19d1205 83 unsigned sp_restored:1;
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NC
84} unwind;
85
84798bd6
JB
86/* Bit N indicates that an R_ARM_NONE relocation has been output for
87 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
88 emitted only once per section, to save unnecessary bloat. */
89static unsigned int marked_pr_dependency = 0;
90
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NC
91#endif /* OBJ_ELF */
92
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93enum arm_float_abi
94{
95 ARM_FLOAT_ABI_HARD,
96 ARM_FLOAT_ABI_SOFTFP,
97 ARM_FLOAT_ABI_SOFT
98};
99
c19d1205 100/* Types of processor to assemble for. */
b89dddec
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101#define ARM_1 ARM_ARCH_V1
102#define ARM_2 ARM_ARCH_V2
103#define ARM_3 ARM_ARCH_V2S
104#define ARM_250 ARM_ARCH_V2S
105#define ARM_6 ARM_ARCH_V3
106#define ARM_7 ARM_ARCH_V3
107#define ARM_8 ARM_ARCH_V4
108#define ARM_9 ARM_ARCH_V4T
109#define ARM_STRONG ARM_ARCH_V4
c19d1205 110#define ARM_CPU_MASK 0x0000000f /* XXX? */
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111
112#ifndef CPU_DEFAULT
113#if defined __XSCALE__
b89dddec 114#define CPU_DEFAULT (ARM_ARCH_XSCALE)
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115#else
116#if defined __thumb__
c19d1205 117#define CPU_DEFAULT (ARM_ARCH_V5T)
b99bd4ef 118#else
c19d1205 119#define CPU_DEFAULT ARM_ANY
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120#endif
121#endif
122#endif
123
124#ifndef FPU_DEFAULT
c820d418
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125# ifdef TE_LINUX
126# define FPU_DEFAULT FPU_ARCH_FPA
127# elif defined (TE_NetBSD)
128# ifdef OBJ_ELF
129# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
130# else
131 /* Legacy a.out format. */
132# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
133# endif
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134# elif defined (TE_VXWORKS)
135# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
c820d418
MM
136# else
137 /* For backwards compatibility, default to FPA. */
138# define FPU_DEFAULT FPU_ARCH_FPA
139# endif
140#endif /* ifndef FPU_DEFAULT */
b99bd4ef 141
c19d1205 142#define streq(a, b) (strcmp (a, b) == 0)
b99bd4ef 143
03b1477f 144static unsigned long cpu_variant;
b99bd4ef 145
b99bd4ef 146/* Flags stored in private area of BFD structure. */
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147static int uses_apcs_26 = FALSE;
148static int atpcs = FALSE;
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149static int support_interwork = FALSE;
150static int uses_apcs_float = FALSE;
c19d1205 151static int pic_code = FALSE;
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152
153/* Variables that we set while parsing command-line options. Once all
154 options have been read we re-process these values to set the real
155 assembly flags. */
156static int legacy_cpu = -1;
157static int legacy_fpu = -1;
158
159static int mcpu_cpu_opt = -1;
160static int mcpu_fpu_opt = -1;
161static int march_cpu_opt = -1;
162static int march_fpu_opt = -1;
163static int mfpu_opt = -1;
33a392fb 164static int mfloat_abi_opt = -1;
7cc69913 165#ifdef OBJ_ELF
deeaaff8
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166# ifdef EABI_DEFAULT
167static int meabi_flags = EABI_DEFAULT;
168# else
d507cf36 169static int meabi_flags = EF_ARM_EABI_UNKNOWN;
deeaaff8 170# endif
7cc69913 171#endif
b99bd4ef 172
b99bd4ef 173#ifdef OBJ_ELF
c19d1205 174/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
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175symbolS * GOT_symbol;
176#endif
177
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178/* 0: assemble for ARM,
179 1: assemble for Thumb,
180 2: assemble for Thumb even though target CPU does not support thumb
181 instructions. */
182static int thumb_mode = 0;
183
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184/* If unified_syntax is true, we are processing the new unified
185 ARM/Thumb syntax. Important differences from the old ARM mode:
186
187 - Immediate operands do not require a # prefix.
188 - Conditional affixes always appear at the end of the
189 instruction. (For backward compatibility, those instructions
190 that formerly had them in the middle, continue to accept them
191 there.)
192 - The IT instruction may appear, and if it does is validated
193 against subsequent conditional affixes. It does not generate
194 machine code.
195
196 Important differences from the old Thumb mode:
197
198 - Immediate operands do not require a # prefix.
199 - Most of the V6T2 instructions are only available in unified mode.
200 - The .N and .W suffixes are recognized and honored (it is an error
201 if they cannot be honored).
202 - All instructions set the flags if and only if they have an 's' affix.
203 - Conditional affixes may be used. They are validated against
204 preceding IT instructions. Unlike ARM mode, you cannot use a
205 conditional affix except in the scope of an IT instruction. */
206
207static bfd_boolean unified_syntax = FALSE;
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208
209struct arm_it
210{
c19d1205 211 const char * error;
b99bd4ef 212 unsigned long instruction;
c19d1205
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213 int size;
214 int size_req;
215 int cond;
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216 /* Set to the opcode if the instruction needs relaxation.
217 Zero if the instruction is not relaxed. */
218 unsigned long relax;
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219 struct
220 {
221 bfd_reloc_code_real_type type;
c19d1205
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222 expressionS exp;
223 int pc_rel;
b99bd4ef 224 } reloc;
b99bd4ef 225
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226 struct
227 {
228 unsigned reg;
ca3f61f7
NC
229 signed int imm;
230 unsigned present : 1; /* Operand present. */
231 unsigned isreg : 1; /* Operand was a register. */
232 unsigned immisreg : 1; /* .imm field is a second register. */
233 unsigned hasreloc : 1; /* Operand has relocation suffix. */
234 unsigned writeback : 1; /* Operand has trailing ! */
235 unsigned preind : 1; /* Preindexed address. */
236 unsigned postind : 1; /* Postindexed address. */
237 unsigned negative : 1; /* Index register was negated. */
238 unsigned shifted : 1; /* Shift applied to operation. */
239 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
c19d1205 240 } operands[6];
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241};
242
c19d1205 243static struct arm_it inst;
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244
245#define NUM_FLOAT_VALS 8
246
05d2d07e 247const char * fp_const[] =
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248{
249 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
250};
251
c19d1205 252/* Number of littlenums required to hold an extended precision number. */
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253#define MAX_LITTLENUMS 6
254
255LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
256
257#define FAIL (-1)
258#define SUCCESS (0)
259
260#define SUFF_S 1
261#define SUFF_D 2
262#define SUFF_E 3
263#define SUFF_P 4
264
c19d1205
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265#define CP_T_X 0x00008000
266#define CP_T_Y 0x00400000
b99bd4ef 267
c19d1205
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268#define CONDS_BIT 0x00100000
269#define LOAD_BIT 0x00100000
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270
271#define DOUBLE_LOAD_FLAG 0x00000001
272
273struct asm_cond
274{
c19d1205 275 const char * template;
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276 unsigned long value;
277};
278
c19d1205 279#define COND_ALWAYS 0xE
b99bd4ef 280
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281struct asm_psr
282{
b34976b6 283 const char *template;
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284 unsigned long field;
285};
286
2d2255b5 287/* The bit that distinguishes CPSR and SPSR. */
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288#define SPSR_BIT (1 << 22)
289
c19d1205
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290/* The individual PSR flag bits. */
291#define PSR_c (1 << 16)
292#define PSR_x (1 << 17)
293#define PSR_s (1 << 18)
294#define PSR_f (1 << 19)
b99bd4ef 295
c19d1205 296struct reloc_entry
bfae80f2 297{
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298 char *name;
299 bfd_reloc_code_real_type reloc;
bfae80f2
RE
300};
301
302enum vfp_sp_reg_pos
303{
304 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn
305};
306
307enum vfp_ldstm_type
308{
309 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
310};
311
c19d1205
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312/* ARM register categories. This includes coprocessor numbers and various
313 architecture extensions' registers. */
314enum arm_reg_type
bfae80f2 315{
c19d1205
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316 REG_TYPE_RN,
317 REG_TYPE_CP,
318 REG_TYPE_CN,
319 REG_TYPE_FN,
320 REG_TYPE_VFS,
321 REG_TYPE_VFD,
322 REG_TYPE_VFC,
323 REG_TYPE_MVF,
324 REG_TYPE_MVD,
325 REG_TYPE_MVFX,
326 REG_TYPE_MVDX,
327 REG_TYPE_MVAX,
328 REG_TYPE_DSPSC,
329 REG_TYPE_MMXWR,
330 REG_TYPE_MMXWC,
331 REG_TYPE_MMXWCG,
332 REG_TYPE_XSCALE,
bfae80f2
RE
333};
334
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RE
335/* Structure for a hash table entry for a register. */
336struct reg_entry
337{
c19d1205
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338 const char *name;
339 unsigned char number;
340 unsigned char type;
341 unsigned char builtin;
6c43fab6
RE
342};
343
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344/* Diagnostics used when we don't get a register of the expected type. */
345const char *const reg_expected_msgs[] =
346{
347 N_("ARM register expected"),
348 N_("bad or missing co-processor number"),
349 N_("co-processor register expected"),
350 N_("FPA register expected"),
351 N_("VFP single precision register expected"),
352 N_("VFP double precision register expected"),
353 N_("VFP system register expected"),
354 N_("Maverick MVF register expected"),
355 N_("Maverick MVD register expected"),
356 N_("Maverick MVFX register expected"),
357 N_("Maverick MVDX register expected"),
358 N_("Maverick MVAX register expected"),
359 N_("Maverick DSPSC register expected"),
360 N_("iWMMXt data register expected"),
361 N_("iWMMXt control register expected"),
362 N_("iWMMXt scalar register expected"),
363 N_("XScale accumulator register expected"),
6c43fab6
RE
364};
365
c19d1205
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366/* Some well known registers that we refer to directly elsewhere. */
367#define REG_SP 13
368#define REG_LR 14
369#define REG_PC 15
404ff6b5 370
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371/* ARM instructions take 4bytes in the object file, Thumb instructions
372 take 2: */
c19d1205 373#define INSN_SIZE 4
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374
375struct asm_opcode
376{
377 /* Basic string to match. */
c19d1205
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378 const char *template;
379
380 /* Parameters to instruction. */
381 unsigned char operands[8];
382
383 /* Conditional tag - see opcode_lookup. */
384 unsigned int tag : 4;
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NC
385
386 /* Basic instruction code. */
c19d1205 387 unsigned int avalue : 28;
b99bd4ef 388
c19d1205
ZW
389 /* Thumb-format instruction code. */
390 unsigned int tvalue;
b99bd4ef 391
90e4755a 392 /* Which architecture variant provides this instruction. */
c19d1205
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393 unsigned long avariant;
394 unsigned long tvariant;
395
396 /* Function to call to encode instruction in ARM format. */
397 void (* aencode) (void);
b99bd4ef 398
c19d1205
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399 /* Function to call to encode instruction in Thumb format. */
400 void (* tencode) (void);
b99bd4ef
NC
401};
402
a737bd4d
NC
403/* Defines for various bits that we will want to toggle. */
404#define INST_IMMEDIATE 0x02000000
405#define OFFSET_REG 0x02000000
c19d1205 406#define HWOFFSET_IMM 0x00400000
a737bd4d
NC
407#define SHIFT_BY_REG 0x00000010
408#define PRE_INDEX 0x01000000
409#define INDEX_UP 0x00800000
410#define WRITE_BACK 0x00200000
411#define LDM_TYPE_2_OR_3 0x00400000
90e4755a 412
a737bd4d
NC
413#define LITERAL_MASK 0xf000f000
414#define OPCODE_MASK 0xfe1fffff
415#define V4_STR_BIT 0x00000020
90e4755a 416
a737bd4d 417#define DATA_OP_SHIFT 21
90e4755a 418
a737bd4d
NC
419/* Codes to distinguish the arithmetic instructions. */
420#define OPCODE_AND 0
421#define OPCODE_EOR 1
422#define OPCODE_SUB 2
423#define OPCODE_RSB 3
424#define OPCODE_ADD 4
425#define OPCODE_ADC 5
426#define OPCODE_SBC 6
427#define OPCODE_RSC 7
428#define OPCODE_TST 8
429#define OPCODE_TEQ 9
430#define OPCODE_CMP 10
431#define OPCODE_CMN 11
432#define OPCODE_ORR 12
433#define OPCODE_MOV 13
434#define OPCODE_BIC 14
435#define OPCODE_MVN 15
90e4755a 436
a737bd4d
NC
437#define T_OPCODE_MUL 0x4340
438#define T_OPCODE_TST 0x4200
439#define T_OPCODE_CMN 0x42c0
440#define T_OPCODE_NEG 0x4240
441#define T_OPCODE_MVN 0x43c0
90e4755a 442
a737bd4d
NC
443#define T_OPCODE_ADD_R3 0x1800
444#define T_OPCODE_SUB_R3 0x1a00
445#define T_OPCODE_ADD_HI 0x4400
446#define T_OPCODE_ADD_ST 0xb000
447#define T_OPCODE_SUB_ST 0xb080
448#define T_OPCODE_ADD_SP 0xa800
449#define T_OPCODE_ADD_PC 0xa000
450#define T_OPCODE_ADD_I8 0x3000
451#define T_OPCODE_SUB_I8 0x3800
452#define T_OPCODE_ADD_I3 0x1c00
453#define T_OPCODE_SUB_I3 0x1e00
b99bd4ef 454
a737bd4d
NC
455#define T_OPCODE_ASR_R 0x4100
456#define T_OPCODE_LSL_R 0x4080
c19d1205
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457#define T_OPCODE_LSR_R 0x40c0
458#define T_OPCODE_ROR_R 0x41c0
a737bd4d
NC
459#define T_OPCODE_ASR_I 0x1000
460#define T_OPCODE_LSL_I 0x0000
461#define T_OPCODE_LSR_I 0x0800
b99bd4ef 462
a737bd4d
NC
463#define T_OPCODE_MOV_I8 0x2000
464#define T_OPCODE_CMP_I8 0x2800
465#define T_OPCODE_CMP_LR 0x4280
466#define T_OPCODE_MOV_HR 0x4600
467#define T_OPCODE_CMP_HR 0x4500
b99bd4ef 468
a737bd4d
NC
469#define T_OPCODE_LDR_PC 0x4800
470#define T_OPCODE_LDR_SP 0x9800
471#define T_OPCODE_STR_SP 0x9000
472#define T_OPCODE_LDR_IW 0x6800
473#define T_OPCODE_STR_IW 0x6000
474#define T_OPCODE_LDR_IH 0x8800
475#define T_OPCODE_STR_IH 0x8000
476#define T_OPCODE_LDR_IB 0x7800
477#define T_OPCODE_STR_IB 0x7000
478#define T_OPCODE_LDR_RW 0x5800
479#define T_OPCODE_STR_RW 0x5000
480#define T_OPCODE_LDR_RH 0x5a00
481#define T_OPCODE_STR_RH 0x5200
482#define T_OPCODE_LDR_RB 0x5c00
483#define T_OPCODE_STR_RB 0x5400
c9b604bd 484
a737bd4d
NC
485#define T_OPCODE_PUSH 0xb400
486#define T_OPCODE_POP 0xbc00
b99bd4ef 487
2fc8bdac 488#define T_OPCODE_BRANCH 0xe000
b99bd4ef 489
a737bd4d 490#define THUMB_SIZE 2 /* Size of thumb instruction. */
a737bd4d 491#define THUMB_PP_PC_LR 0x0100
c19d1205
ZW
492#define THUMB_LOAD_BIT 0x0800
493
494#define BAD_ARGS _("bad arguments to instruction")
495#define BAD_PC _("r15 not allowed here")
496#define BAD_COND _("instruction cannot be conditional")
497#define BAD_OVERLAP _("registers may not be the same")
498#define BAD_HIREG _("lo register required")
499#define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
500
501static struct hash_control *arm_ops_hsh;
502static struct hash_control *arm_cond_hsh;
503static struct hash_control *arm_shift_hsh;
504static struct hash_control *arm_psr_hsh;
505static struct hash_control *arm_reg_hsh;
506static struct hash_control *arm_reloc_hsh;
b99bd4ef 507
b99bd4ef
NC
508/* Stuff needed to resolve the label ambiguity
509 As:
510 ...
511 label: <insn>
512 may differ from:
513 ...
514 label:
c19d1205 515 <insn>
b99bd4ef
NC
516*/
517
518symbolS * last_label_seen;
b34976b6 519static int label_is_thumb_function_name = FALSE;
a737bd4d 520\f
3d0c9500
NC
521/* Literal pool structure. Held on a per-section
522 and per-sub-section basis. */
a737bd4d 523
c19d1205 524#define MAX_LITERAL_POOL_SIZE 1024
3d0c9500 525typedef struct literal_pool
b99bd4ef 526{
c19d1205
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527 expressionS literals [MAX_LITERAL_POOL_SIZE];
528 unsigned int next_free_entry;
529 unsigned int id;
530 symbolS * symbol;
531 segT section;
532 subsegT sub_section;
61b5f74b 533 struct literal_pool * next;
3d0c9500 534} literal_pool;
b99bd4ef 535
3d0c9500
NC
536/* Pointer to a linked list of literal pools. */
537literal_pool * list_of_pools = NULL;
e27ec89e
PB
538
539/* State variables for IT block handling. */
540static bfd_boolean current_it_mask = 0;
541static int current_cc;
542
c19d1205
ZW
543\f
544/* Pure syntax. */
b99bd4ef 545
c19d1205
ZW
546/* This array holds the chars that always start a comment. If the
547 pre-processor is disabled, these aren't very useful. */
548const char comment_chars[] = "@";
3d0c9500 549
c19d1205
ZW
550/* This array holds the chars that only start a comment at the beginning of
551 a line. If the line seems to have the form '# 123 filename'
552 .line and .file directives will appear in the pre-processed output. */
553/* Note that input_file.c hand checks for '#' at the beginning of the
554 first line of the input file. This is because the compiler outputs
555 #NO_APP at the beginning of its output. */
556/* Also note that comments like this one will always work. */
557const char line_comment_chars[] = "#";
3d0c9500 558
c19d1205 559const char line_separator_chars[] = ";";
b99bd4ef 560
c19d1205
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561/* Chars that can be used to separate mant
562 from exp in floating point numbers. */
563const char EXP_CHARS[] = "eE";
3d0c9500 564
c19d1205
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565/* Chars that mean this number is a floating point constant. */
566/* As in 0f12.456 */
567/* or 0d1.2345e12 */
b99bd4ef 568
c19d1205 569const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
3d0c9500 570
c19d1205
ZW
571/* Prefix characters that indicate the start of an immediate
572 value. */
573#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
3d0c9500 574
c19d1205
ZW
575/* Separator character handling. */
576
577#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
578
579static inline int
580skip_past_char (char ** str, char c)
581{
582 if (**str == c)
583 {
584 (*str)++;
585 return SUCCESS;
3d0c9500 586 }
c19d1205
ZW
587 else
588 return FAIL;
589}
590#define skip_past_comma(str) skip_past_char (str, ',')
3d0c9500 591
c19d1205
ZW
592/* Arithmetic expressions (possibly involving symbols). */
593
594/* Return TRUE if anything in the expression is a bignum. */
595
596static int
597walk_no_bignums (symbolS * sp)
598{
599 if (symbol_get_value_expression (sp)->X_op == O_big)
600 return 1;
601
602 if (symbol_get_value_expression (sp)->X_add_symbol)
3d0c9500 603 {
c19d1205
ZW
604 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
605 || (symbol_get_value_expression (sp)->X_op_symbol
606 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
3d0c9500
NC
607 }
608
c19d1205 609 return 0;
3d0c9500
NC
610}
611
c19d1205
ZW
612static int in_my_get_expression = 0;
613
614/* Third argument to my_get_expression. */
615#define GE_NO_PREFIX 0
616#define GE_IMM_PREFIX 1
617#define GE_OPT_PREFIX 2
a737bd4d 618
b99bd4ef 619static int
c19d1205 620my_get_expression (expressionS * ep, char ** str, int prefix_mode)
b99bd4ef 621{
c19d1205
ZW
622 char * save_in;
623 segT seg;
b99bd4ef 624
c19d1205
ZW
625 /* In unified syntax, all prefixes are optional. */
626 if (unified_syntax)
627 prefix_mode = GE_OPT_PREFIX;
b99bd4ef 628
c19d1205 629 switch (prefix_mode)
b99bd4ef 630 {
c19d1205
ZW
631 case GE_NO_PREFIX: break;
632 case GE_IMM_PREFIX:
633 if (!is_immediate_prefix (**str))
634 {
635 inst.error = _("immediate expression requires a # prefix");
636 return FAIL;
637 }
638 (*str)++;
639 break;
640 case GE_OPT_PREFIX:
641 if (is_immediate_prefix (**str))
642 (*str)++;
643 break;
644 default: abort ();
645 }
b99bd4ef 646
c19d1205 647 memset (ep, 0, sizeof (expressionS));
b99bd4ef 648
c19d1205
ZW
649 save_in = input_line_pointer;
650 input_line_pointer = *str;
651 in_my_get_expression = 1;
652 seg = expression (ep);
653 in_my_get_expression = 0;
654
655 if (ep->X_op == O_illegal)
b99bd4ef 656 {
c19d1205
ZW
657 /* We found a bad expression in md_operand(). */
658 *str = input_line_pointer;
659 input_line_pointer = save_in;
660 if (inst.error == NULL)
661 inst.error = _("bad expression");
662 return 1;
663 }
b99bd4ef 664
c19d1205
ZW
665#ifdef OBJ_AOUT
666 if (seg != absolute_section
667 && seg != text_section
668 && seg != data_section
669 && seg != bss_section
670 && seg != undefined_section)
671 {
672 inst.error = _("bad segment");
673 *str = input_line_pointer;
674 input_line_pointer = save_in;
675 return 1;
b99bd4ef 676 }
c19d1205 677#endif
b99bd4ef 678
c19d1205
ZW
679 /* Get rid of any bignums now, so that we don't generate an error for which
680 we can't establish a line number later on. Big numbers are never valid
681 in instructions, which is where this routine is always called. */
682 if (ep->X_op == O_big
683 || (ep->X_add_symbol
684 && (walk_no_bignums (ep->X_add_symbol)
685 || (ep->X_op_symbol
686 && walk_no_bignums (ep->X_op_symbol)))))
687 {
688 inst.error = _("invalid constant");
689 *str = input_line_pointer;
690 input_line_pointer = save_in;
691 return 1;
692 }
b99bd4ef 693
c19d1205
ZW
694 *str = input_line_pointer;
695 input_line_pointer = save_in;
696 return 0;
b99bd4ef
NC
697}
698
c19d1205
ZW
699/* Turn a string in input_line_pointer into a floating point constant
700 of type TYPE, and store the appropriate bytes in *LITP. The number
701 of LITTLENUMS emitted is stored in *SIZEP. An error message is
702 returned, or NULL on OK.
b99bd4ef 703
c19d1205
ZW
704 Note that fp constants aren't represent in the normal way on the ARM.
705 In big endian mode, things are as expected. However, in little endian
706 mode fp constants are big-endian word-wise, and little-endian byte-wise
707 within the words. For example, (double) 1.1 in big endian mode is
708 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
709 the byte sequence 99 99 f1 3f 9a 99 99 99.
b99bd4ef 710
c19d1205 711 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
b99bd4ef 712
c19d1205
ZW
713char *
714md_atof (int type, char * litP, int * sizeP)
715{
716 int prec;
717 LITTLENUM_TYPE words[MAX_LITTLENUMS];
718 char *t;
719 int i;
b99bd4ef 720
c19d1205
ZW
721 switch (type)
722 {
723 case 'f':
724 case 'F':
725 case 's':
726 case 'S':
727 prec = 2;
728 break;
b99bd4ef 729
c19d1205
ZW
730 case 'd':
731 case 'D':
732 case 'r':
733 case 'R':
734 prec = 4;
735 break;
b99bd4ef 736
c19d1205
ZW
737 case 'x':
738 case 'X':
739 prec = 6;
740 break;
b99bd4ef 741
c19d1205
ZW
742 case 'p':
743 case 'P':
744 prec = 6;
745 break;
a737bd4d 746
c19d1205
ZW
747 default:
748 *sizeP = 0;
749 return _("bad call to MD_ATOF()");
750 }
b99bd4ef 751
c19d1205
ZW
752 t = atof_ieee (input_line_pointer, type, words);
753 if (t)
754 input_line_pointer = t;
755 *sizeP = prec * 2;
b99bd4ef 756
c19d1205
ZW
757 if (target_big_endian)
758 {
759 for (i = 0; i < prec; i++)
760 {
761 md_number_to_chars (litP, (valueT) words[i], 2);
762 litP += 2;
763 }
764 }
765 else
766 {
767 if (cpu_variant & FPU_ARCH_VFP)
768 for (i = prec - 1; i >= 0; i--)
769 {
770 md_number_to_chars (litP, (valueT) words[i], 2);
771 litP += 2;
772 }
773 else
774 /* For a 4 byte float the order of elements in `words' is 1 0.
775 For an 8 byte float the order is 1 0 3 2. */
776 for (i = 0; i < prec; i += 2)
777 {
778 md_number_to_chars (litP, (valueT) words[i + 1], 2);
779 md_number_to_chars (litP + 2, (valueT) words[i], 2);
780 litP += 4;
781 }
782 }
b99bd4ef 783
c19d1205
ZW
784 return 0;
785}
b99bd4ef 786
c19d1205
ZW
787/* We handle all bad expressions here, so that we can report the faulty
788 instruction in the error message. */
789void
790md_operand (expressionS * expr)
791{
792 if (in_my_get_expression)
793 expr->X_op = O_illegal;
b99bd4ef
NC
794}
795
c19d1205 796/* Immediate values. */
b99bd4ef 797
c19d1205
ZW
798/* Generic immediate-value read function for use in directives.
799 Accepts anything that 'expression' can fold to a constant.
800 *val receives the number. */
801#ifdef OBJ_ELF
802static int
803immediate_for_directive (int *val)
b99bd4ef 804{
c19d1205
ZW
805 expressionS exp;
806 exp.X_op = O_illegal;
b99bd4ef 807
c19d1205
ZW
808 if (is_immediate_prefix (*input_line_pointer))
809 {
810 input_line_pointer++;
811 expression (&exp);
812 }
b99bd4ef 813
c19d1205
ZW
814 if (exp.X_op != O_constant)
815 {
816 as_bad (_("expected #constant"));
817 ignore_rest_of_line ();
818 return FAIL;
819 }
820 *val = exp.X_add_number;
821 return SUCCESS;
b99bd4ef 822}
c19d1205 823#endif
b99bd4ef 824
c19d1205 825/* Register parsing. */
b99bd4ef 826
c19d1205
ZW
827/* Generic register parser. CCP points to what should be the
828 beginning of a register name. If it is indeed a valid register
829 name, advance CCP over it and return the reg_entry structure;
830 otherwise return NULL. Does not issue diagnostics. */
831
832static struct reg_entry *
833arm_reg_parse_multi (char **ccp)
b99bd4ef 834{
c19d1205
ZW
835 char *start = *ccp;
836 char *p;
837 struct reg_entry *reg;
b99bd4ef 838
c19d1205
ZW
839#ifdef REGISTER_PREFIX
840 if (*start != REGISTER_PREFIX)
841 return FAIL;
842 start++;
843#endif
844#ifdef OPTIONAL_REGISTER_PREFIX
845 if (*start == OPTIONAL_REGISTER_PREFIX)
846 start++;
847#endif
b99bd4ef 848
c19d1205
ZW
849 p = start;
850 if (!ISALPHA (*p) || !is_name_beginner (*p))
851 return NULL;
b99bd4ef 852
c19d1205
ZW
853 do
854 p++;
855 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
856
857 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
858
859 if (!reg)
860 return NULL;
861
862 *ccp = p;
863 return reg;
b99bd4ef
NC
864}
865
c19d1205
ZW
866/* As above, but the register must be of type TYPE, and the return
867 value is the register number or NULL. */
868
b99bd4ef 869static int
c19d1205 870arm_reg_parse (char **ccp, enum arm_reg_type type)
b99bd4ef 871{
c19d1205
ZW
872 char *start = *ccp;
873 struct reg_entry *reg = arm_reg_parse_multi (ccp);
b99bd4ef 874
c19d1205
ZW
875 if (reg && reg->type == type)
876 return reg->number;
6057a28f 877
c19d1205
ZW
878 /* Alternative syntaxes are accepted for a few register classes. */
879 switch (type)
880 {
881 case REG_TYPE_MVF:
882 case REG_TYPE_MVD:
883 case REG_TYPE_MVFX:
884 case REG_TYPE_MVDX:
885 /* Generic coprocessor register names are allowed for these. */
886 if (reg->type == REG_TYPE_CN)
887 return reg->number;
888 break;
69b97547 889
c19d1205
ZW
890 case REG_TYPE_CP:
891 /* For backward compatibility, a bare number is valid here. */
892 {
893 unsigned long processor = strtoul (start, ccp, 10);
894 if (*ccp != start && processor <= 15)
895 return processor;
896 }
6057a28f 897
c19d1205
ZW
898 case REG_TYPE_MMXWC:
899 /* WC includes WCG. ??? I'm not sure this is true for all
900 instructions that take WC registers. */
901 if (reg->type == REG_TYPE_MMXWCG)
902 return reg->number;
6057a28f 903 break;
c19d1205 904
6057a28f 905 default:
c19d1205 906 break;
6057a28f
NC
907 }
908
c19d1205
ZW
909 *ccp = start;
910 return FAIL;
911}
69b97547 912
c19d1205
ZW
913/* Parse an ARM register list. Returns the bitmask, or FAIL. */
914static long
915parse_reg_list (char ** strp)
916{
917 char * str = * strp;
918 long range = 0;
919 int another_range;
a737bd4d 920
c19d1205
ZW
921 /* We come back here if we get ranges concatenated by '+' or '|'. */
922 do
6057a28f 923 {
c19d1205 924 another_range = 0;
a737bd4d 925
c19d1205
ZW
926 if (*str == '{')
927 {
928 int in_range = 0;
929 int cur_reg = -1;
a737bd4d 930
c19d1205
ZW
931 str++;
932 do
933 {
934 int reg;
6057a28f 935
c19d1205
ZW
936 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
937 {
938 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
939 return FAIL;
940 }
a737bd4d 941
c19d1205
ZW
942 if (in_range)
943 {
944 int i;
a737bd4d 945
c19d1205
ZW
946 if (reg <= cur_reg)
947 {
948 inst.error = _("bad range in register list");
949 return FAIL;
950 }
40a18ebd 951
c19d1205
ZW
952 for (i = cur_reg + 1; i < reg; i++)
953 {
954 if (range & (1 << i))
955 as_tsktsk
956 (_("Warning: duplicated register (r%d) in register list"),
957 i);
958 else
959 range |= 1 << i;
960 }
961 in_range = 0;
962 }
a737bd4d 963
c19d1205
ZW
964 if (range & (1 << reg))
965 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
966 reg);
967 else if (reg <= cur_reg)
968 as_tsktsk (_("Warning: register range not in ascending order"));
a737bd4d 969
c19d1205
ZW
970 range |= 1 << reg;
971 cur_reg = reg;
972 }
973 while (skip_past_comma (&str) != FAIL
974 || (in_range = 1, *str++ == '-'));
975 str--;
a737bd4d 976
c19d1205
ZW
977 if (*str++ != '}')
978 {
979 inst.error = _("missing `}'");
980 return FAIL;
981 }
982 }
983 else
984 {
985 expressionS expr;
40a18ebd 986
c19d1205
ZW
987 if (my_get_expression (&expr, &str, GE_NO_PREFIX))
988 return FAIL;
40a18ebd 989
c19d1205
ZW
990 if (expr.X_op == O_constant)
991 {
992 if (expr.X_add_number
993 != (expr.X_add_number & 0x0000ffff))
994 {
995 inst.error = _("invalid register mask");
996 return FAIL;
997 }
a737bd4d 998
c19d1205
ZW
999 if ((range & expr.X_add_number) != 0)
1000 {
1001 int regno = range & expr.X_add_number;
a737bd4d 1002
c19d1205
ZW
1003 regno &= -regno;
1004 regno = (1 << regno) - 1;
1005 as_tsktsk
1006 (_("Warning: duplicated register (r%d) in register list"),
1007 regno);
1008 }
a737bd4d 1009
c19d1205
ZW
1010 range |= expr.X_add_number;
1011 }
1012 else
1013 {
1014 if (inst.reloc.type != 0)
1015 {
1016 inst.error = _("expression too complex");
1017 return FAIL;
1018 }
a737bd4d 1019
c19d1205
ZW
1020 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
1021 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1022 inst.reloc.pc_rel = 0;
1023 }
1024 }
a737bd4d 1025
c19d1205
ZW
1026 if (*str == '|' || *str == '+')
1027 {
1028 str++;
1029 another_range = 1;
1030 }
a737bd4d 1031 }
c19d1205 1032 while (another_range);
a737bd4d 1033
c19d1205
ZW
1034 *strp = str;
1035 return range;
a737bd4d
NC
1036}
1037
c19d1205
ZW
1038/* Parse a VFP register list. If the string is invalid return FAIL.
1039 Otherwise return the number of registers, and set PBASE to the first
1040 register. Double precision registers are matched if DP is nonzero. */
6057a28f 1041
c19d1205 1042static int
ca3f61f7 1043parse_vfp_reg_list (char **str, unsigned int *pbase, int dp)
6057a28f 1044{
c19d1205
ZW
1045 int base_reg;
1046 int new_base;
1047 int regtype;
1048 int max_regs;
1049 int count = 0;
1050 int warned = 0;
1051 unsigned long mask = 0;
a737bd4d 1052 int i;
6057a28f 1053
c19d1205
ZW
1054 if (**str != '{')
1055 return FAIL;
6057a28f 1056
c19d1205 1057 (*str)++;
6057a28f 1058
c19d1205 1059 if (dp)
a737bd4d 1060 {
c19d1205
ZW
1061 regtype = REG_TYPE_VFD;
1062 max_regs = 16;
1063 }
1064 else
1065 {
1066 regtype = REG_TYPE_VFS;
1067 max_regs = 32;
1068 }
6057a28f 1069
c19d1205 1070 base_reg = max_regs;
a737bd4d 1071
c19d1205
ZW
1072 do
1073 {
1074 new_base = arm_reg_parse (str, regtype);
1075 if (new_base == FAIL)
a737bd4d 1076 {
c19d1205
ZW
1077 inst.error = gettext (reg_expected_msgs[regtype]);
1078 return FAIL;
1079 }
a737bd4d 1080
c19d1205
ZW
1081 if (new_base < base_reg)
1082 base_reg = new_base;
a737bd4d 1083
c19d1205
ZW
1084 if (mask & (1 << new_base))
1085 {
1086 inst.error = _("invalid register list");
1087 return FAIL;
a737bd4d 1088 }
a737bd4d 1089
c19d1205
ZW
1090 if ((mask >> new_base) != 0 && ! warned)
1091 {
1092 as_tsktsk (_("register list not in ascending order"));
1093 warned = 1;
1094 }
0bbf2aa4 1095
c19d1205
ZW
1096 mask |= 1 << new_base;
1097 count++;
0bbf2aa4 1098
c19d1205
ZW
1099 if (**str == '-') /* We have the start of a range expression */
1100 {
1101 int high_range;
0bbf2aa4 1102
c19d1205 1103 (*str)++;
0bbf2aa4 1104
c19d1205
ZW
1105 if ((high_range = arm_reg_parse (str, regtype)) == FAIL)
1106 {
1107 inst.error = gettext (reg_expected_msgs[regtype]);
1108 return FAIL;
1109 }
0bbf2aa4 1110
c19d1205
ZW
1111 if (high_range <= new_base)
1112 {
1113 inst.error = _("register range not in ascending order");
1114 return FAIL;
1115 }
0bbf2aa4 1116
c19d1205 1117 for (new_base++; new_base <= high_range; new_base++)
0bbf2aa4 1118 {
c19d1205 1119 if (mask & (1 << new_base))
0bbf2aa4 1120 {
c19d1205
ZW
1121 inst.error = _("invalid register list");
1122 return FAIL;
0bbf2aa4 1123 }
c19d1205
ZW
1124
1125 mask |= 1 << new_base;
1126 count++;
0bbf2aa4 1127 }
0bbf2aa4 1128 }
0bbf2aa4 1129 }
c19d1205 1130 while (skip_past_comma (str) != FAIL);
0bbf2aa4 1131
c19d1205 1132 (*str)++;
0bbf2aa4 1133
c19d1205
ZW
1134 /* Sanity check -- should have raised a parse error above. */
1135 if (count == 0 || count > max_regs)
1136 abort ();
1137
1138 *pbase = base_reg;
1139
1140 /* Final test -- the registers must be consecutive. */
1141 mask >>= base_reg;
1142 for (i = 0; i < count; i++)
1143 {
1144 if ((mask & (1u << i)) == 0)
1145 {
1146 inst.error = _("non-contiguous register range");
1147 return FAIL;
1148 }
1149 }
1150
1151 return count;
b99bd4ef
NC
1152}
1153
c19d1205
ZW
1154/* Parse an explicit relocation suffix on an expression. This is
1155 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1156 arm_reloc_hsh contains no entries, so this function can only
1157 succeed if there is no () after the word. Returns -1 on error,
1158 BFD_RELOC_UNUSED if there wasn't any suffix. */
1159static int
1160parse_reloc (char **str)
b99bd4ef 1161{
c19d1205
ZW
1162 struct reloc_entry *r;
1163 char *p, *q;
b99bd4ef 1164
c19d1205
ZW
1165 if (**str != '(')
1166 return BFD_RELOC_UNUSED;
b99bd4ef 1167
c19d1205
ZW
1168 p = *str + 1;
1169 q = p;
1170
1171 while (*q && *q != ')' && *q != ',')
1172 q++;
1173 if (*q != ')')
1174 return -1;
1175
1176 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
1177 return -1;
1178
1179 *str = q + 1;
1180 return r->reloc;
b99bd4ef
NC
1181}
1182
c19d1205
ZW
1183/* Directives: register aliases. */
1184
b99bd4ef 1185static void
c19d1205 1186insert_reg_alias (char *str, int number, int type)
b99bd4ef 1187{
c19d1205
ZW
1188 struct reg_entry *new;
1189 const char *name;
b99bd4ef 1190
c19d1205
ZW
1191 if ((new = hash_find (arm_reg_hsh, str)) != 0)
1192 {
1193 if (new->builtin)
1194 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
b99bd4ef 1195
c19d1205
ZW
1196 /* Only warn about a redefinition if it's not defined as the
1197 same register. */
1198 else if (new->number != number || new->type != type)
1199 as_warn (_("ignoring redefinition of register alias '%s'"), str);
69b97547 1200
c19d1205
ZW
1201 return;
1202 }
b99bd4ef 1203
c19d1205
ZW
1204 name = xstrdup (str);
1205 new = xmalloc (sizeof (struct reg_entry));
b99bd4ef 1206
c19d1205
ZW
1207 new->name = name;
1208 new->number = number;
1209 new->type = type;
1210 new->builtin = FALSE;
b99bd4ef 1211
c19d1205
ZW
1212 if (hash_insert (arm_reg_hsh, name, (PTR) new))
1213 abort ();
1214}
b99bd4ef 1215
c19d1205 1216/* Look for the .req directive. This is of the form:
b99bd4ef 1217
c19d1205 1218 new_register_name .req existing_register_name
b99bd4ef 1219
c19d1205
ZW
1220 If we find one, or if it looks sufficiently like one that we want to
1221 handle any error here, return non-zero. Otherwise return zero. */
b99bd4ef 1222
c19d1205
ZW
1223static int
1224create_register_alias (char * newname, char *p)
1225{
1226 struct reg_entry *old;
1227 char *oldname, *nbuf;
1228 size_t nlen;
b99bd4ef 1229
c19d1205
ZW
1230 /* The input scrubber ensures that whitespace after the mnemonic is
1231 collapsed to single spaces. */
1232 oldname = p;
1233 if (strncmp (oldname, " .req ", 6) != 0)
1234 return 0;
b99bd4ef 1235
c19d1205
ZW
1236 oldname += 6;
1237 if (*oldname == '\0')
1238 return 0;
b99bd4ef 1239
c19d1205
ZW
1240 old = hash_find (arm_reg_hsh, oldname);
1241 if (!old)
b99bd4ef 1242 {
c19d1205
ZW
1243 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
1244 return 1;
b99bd4ef
NC
1245 }
1246
c19d1205
ZW
1247 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1248 the desired alias name, and p points to its end. If not, then
1249 the desired alias name is in the global original_case_string. */
1250#ifdef TC_CASE_SENSITIVE
1251 nlen = p - newname;
1252#else
1253 newname = original_case_string;
1254 nlen = strlen (newname);
1255#endif
b99bd4ef 1256
c19d1205
ZW
1257 nbuf = alloca (nlen + 1);
1258 memcpy (nbuf, newname, nlen);
1259 nbuf[nlen] = '\0';
b99bd4ef 1260
c19d1205
ZW
1261 /* Create aliases under the new name as stated; an all-lowercase
1262 version of the new name; and an all-uppercase version of the new
1263 name. */
1264 insert_reg_alias (nbuf, old->number, old->type);
b99bd4ef 1265
c19d1205
ZW
1266 for (p = nbuf; *p; p++)
1267 *p = TOUPPER (*p);
1268
1269 if (strncmp (nbuf, newname, nlen))
1270 insert_reg_alias (nbuf, old->number, old->type);
1271
1272 for (p = nbuf; *p; p++)
1273 *p = TOLOWER (*p);
1274
1275 if (strncmp (nbuf, newname, nlen))
1276 insert_reg_alias (nbuf, old->number, old->type);
1277
1278 return 1;
b99bd4ef
NC
1279}
1280
c19d1205
ZW
1281/* Should never be called, as .req goes between the alias and the
1282 register name, not at the beginning of the line. */
b99bd4ef 1283static void
c19d1205 1284s_req (int a ATTRIBUTE_UNUSED)
b99bd4ef 1285{
c19d1205
ZW
1286 as_bad (_("invalid syntax for .req directive"));
1287}
b99bd4ef 1288
c19d1205
ZW
1289/* The .unreq directive deletes an alias which was previously defined
1290 by .req. For example:
b99bd4ef 1291
c19d1205
ZW
1292 my_alias .req r11
1293 .unreq my_alias */
b99bd4ef
NC
1294
1295static void
c19d1205 1296s_unreq (int a ATTRIBUTE_UNUSED)
b99bd4ef 1297{
c19d1205
ZW
1298 char * name;
1299 char saved_char;
b99bd4ef 1300
c19d1205
ZW
1301 name = input_line_pointer;
1302
1303 while (*input_line_pointer != 0
1304 && *input_line_pointer != ' '
1305 && *input_line_pointer != '\n')
1306 ++input_line_pointer;
1307
1308 saved_char = *input_line_pointer;
1309 *input_line_pointer = 0;
1310
1311 if (!*name)
1312 as_bad (_("invalid syntax for .unreq directive"));
1313 else
1314 {
1315 struct reg_entry *reg = hash_find (arm_reg_hsh, name);
1316
1317 if (!reg)
1318 as_bad (_("unknown register alias '%s'"), name);
1319 else if (reg->builtin)
1320 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1321 name);
1322 else
1323 {
1324 hash_delete (arm_reg_hsh, name);
1325 free ((char *) reg->name);
1326 free (reg);
1327 }
1328 }
b99bd4ef 1329
c19d1205 1330 *input_line_pointer = saved_char;
b99bd4ef
NC
1331 demand_empty_rest_of_line ();
1332}
1333
c19d1205
ZW
1334/* Directives: Instruction set selection. */
1335
1336#ifdef OBJ_ELF
1337/* This code is to handle mapping symbols as defined in the ARM ELF spec.
1338 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
1339 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1340 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1341
1342static enum mstate mapstate = MAP_UNDEFINED;
b99bd4ef
NC
1343
1344static void
c19d1205 1345mapping_state (enum mstate state)
b99bd4ef 1346{
a737bd4d 1347 symbolS * symbolP;
c19d1205
ZW
1348 const char * symname;
1349 int type;
b99bd4ef 1350
c19d1205
ZW
1351 if (mapstate == state)
1352 /* The mapping symbol has already been emitted.
1353 There is nothing else to do. */
1354 return;
b99bd4ef 1355
c19d1205 1356 mapstate = state;
b99bd4ef 1357
c19d1205 1358 switch (state)
b99bd4ef 1359 {
c19d1205
ZW
1360 case MAP_DATA:
1361 symname = "$d";
1362 type = BSF_NO_FLAGS;
1363 break;
1364 case MAP_ARM:
1365 symname = "$a";
1366 type = BSF_NO_FLAGS;
1367 break;
1368 case MAP_THUMB:
1369 symname = "$t";
1370 type = BSF_NO_FLAGS;
1371 break;
1372 case MAP_UNDEFINED:
1373 return;
1374 default:
1375 abort ();
1376 }
1377
1378 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
1379
1380 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
1381 symbol_table_insert (symbolP);
1382 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
1383
1384 switch (state)
1385 {
1386 case MAP_ARM:
1387 THUMB_SET_FUNC (symbolP, 0);
1388 ARM_SET_THUMB (symbolP, 0);
1389 ARM_SET_INTERWORK (symbolP, support_interwork);
1390 break;
1391
1392 case MAP_THUMB:
1393 THUMB_SET_FUNC (symbolP, 1);
1394 ARM_SET_THUMB (symbolP, 1);
1395 ARM_SET_INTERWORK (symbolP, support_interwork);
1396 break;
1397
1398 case MAP_DATA:
1399 default:
1400 return;
1401 }
1402}
1403#else
1404#define mapping_state(x) /* nothing */
1405#endif
1406
1407/* Find the real, Thumb encoded start of a Thumb function. */
1408
1409static symbolS *
1410find_real_start (symbolS * symbolP)
1411{
1412 char * real_start;
1413 const char * name = S_GET_NAME (symbolP);
1414 symbolS * new_target;
1415
1416 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
1417#define STUB_NAME ".real_start_of"
1418
1419 if (name == NULL)
1420 abort ();
1421
37f6032b
ZW
1422 /* The compiler may generate BL instructions to local labels because
1423 it needs to perform a branch to a far away location. These labels
1424 do not have a corresponding ".real_start_of" label. We check
1425 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
1426 the ".real_start_of" convention for nonlocal branches. */
1427 if (S_IS_LOCAL (symbolP) || name[0] == '.')
c19d1205
ZW
1428 return symbolP;
1429
37f6032b 1430 real_start = ACONCAT ((STUB_NAME, name, NULL));
c19d1205
ZW
1431 new_target = symbol_find (real_start);
1432
1433 if (new_target == NULL)
1434 {
1435 as_warn ("Failed to find real start of function: %s\n", name);
1436 new_target = symbolP;
1437 }
1438
c19d1205
ZW
1439 return new_target;
1440}
1441
1442static void
1443opcode_select (int width)
1444{
1445 switch (width)
1446 {
1447 case 16:
1448 if (! thumb_mode)
1449 {
1450 if (! (cpu_variant & ARM_EXT_V4T))
1451 as_bad (_("selected processor does not support THUMB opcodes"));
1452
1453 thumb_mode = 1;
1454 /* No need to force the alignment, since we will have been
1455 coming from ARM mode, which is word-aligned. */
1456 record_alignment (now_seg, 1);
1457 }
1458 mapping_state (MAP_THUMB);
1459 break;
1460
1461 case 32:
1462 if (thumb_mode)
1463 {
1464 if ((cpu_variant & ARM_ALL) == ARM_EXT_V4T)
1465 as_bad (_("selected processor does not support ARM opcodes"));
1466
1467 thumb_mode = 0;
1468
1469 if (!need_pass_2)
1470 frag_align (2, 0, 0);
1471
1472 record_alignment (now_seg, 1);
1473 }
1474 mapping_state (MAP_ARM);
1475 break;
1476
1477 default:
1478 as_bad (_("invalid instruction size selected (%d)"), width);
1479 }
1480}
1481
1482static void
1483s_arm (int ignore ATTRIBUTE_UNUSED)
1484{
1485 opcode_select (32);
1486 demand_empty_rest_of_line ();
1487}
1488
1489static void
1490s_thumb (int ignore ATTRIBUTE_UNUSED)
1491{
1492 opcode_select (16);
1493 demand_empty_rest_of_line ();
1494}
1495
1496static void
1497s_code (int unused ATTRIBUTE_UNUSED)
1498{
1499 int temp;
1500
1501 temp = get_absolute_expression ();
1502 switch (temp)
1503 {
1504 case 16:
1505 case 32:
1506 opcode_select (temp);
1507 break;
1508
1509 default:
1510 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1511 }
1512}
1513
1514static void
1515s_force_thumb (int ignore ATTRIBUTE_UNUSED)
1516{
1517 /* If we are not already in thumb mode go into it, EVEN if
1518 the target processor does not support thumb instructions.
1519 This is used by gcc/config/arm/lib1funcs.asm for example
1520 to compile interworking support functions even if the
1521 target processor should not support interworking. */
1522 if (! thumb_mode)
1523 {
1524 thumb_mode = 2;
1525 record_alignment (now_seg, 1);
1526 }
1527
1528 demand_empty_rest_of_line ();
1529}
1530
1531static void
1532s_thumb_func (int ignore ATTRIBUTE_UNUSED)
1533{
1534 s_thumb (0);
1535
1536 /* The following label is the name/address of the start of a Thumb function.
1537 We need to know this for the interworking support. */
1538 label_is_thumb_function_name = TRUE;
1539}
1540
1541/* Perform a .set directive, but also mark the alias as
1542 being a thumb function. */
1543
1544static void
1545s_thumb_set (int equiv)
1546{
1547 /* XXX the following is a duplicate of the code for s_set() in read.c
1548 We cannot just call that code as we need to get at the symbol that
1549 is created. */
1550 char * name;
1551 char delim;
1552 char * end_name;
1553 symbolS * symbolP;
1554
1555 /* Especial apologies for the random logic:
1556 This just grew, and could be parsed much more simply!
1557 Dean - in haste. */
1558 name = input_line_pointer;
1559 delim = get_symbol_end ();
1560 end_name = input_line_pointer;
1561 *end_name = delim;
1562
1563 if (*input_line_pointer != ',')
1564 {
1565 *end_name = 0;
1566 as_bad (_("expected comma after name \"%s\""), name);
b99bd4ef
NC
1567 *end_name = delim;
1568 ignore_rest_of_line ();
1569 return;
1570 }
1571
1572 input_line_pointer++;
1573 *end_name = 0;
1574
1575 if (name[0] == '.' && name[1] == '\0')
1576 {
1577 /* XXX - this should not happen to .thumb_set. */
1578 abort ();
1579 }
1580
1581 if ((symbolP = symbol_find (name)) == NULL
1582 && (symbolP = md_undefined_symbol (name)) == NULL)
1583 {
1584#ifndef NO_LISTING
1585 /* When doing symbol listings, play games with dummy fragments living
1586 outside the normal fragment chain to record the file and line info
c19d1205 1587 for this symbol. */
b99bd4ef
NC
1588 if (listing & LISTING_SYMBOLS)
1589 {
1590 extern struct list_info_struct * listing_tail;
a737bd4d 1591 fragS * dummy_frag = xmalloc (sizeof (fragS));
b99bd4ef
NC
1592
1593 memset (dummy_frag, 0, sizeof (fragS));
1594 dummy_frag->fr_type = rs_fill;
1595 dummy_frag->line = listing_tail;
1596 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1597 dummy_frag->fr_symbol = symbolP;
1598 }
1599 else
1600#endif
1601 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1602
1603#ifdef OBJ_COFF
1604 /* "set" symbols are local unless otherwise specified. */
1605 SF_SET_LOCAL (symbolP);
1606#endif /* OBJ_COFF */
1607 } /* Make a new symbol. */
1608
1609 symbol_table_insert (symbolP);
1610
1611 * end_name = delim;
1612
1613 if (equiv
1614 && S_IS_DEFINED (symbolP)
1615 && S_GET_SEGMENT (symbolP) != reg_section)
1616 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1617
1618 pseudo_set (symbolP);
1619
1620 demand_empty_rest_of_line ();
1621
c19d1205 1622 /* XXX Now we come to the Thumb specific bit of code. */
b99bd4ef
NC
1623
1624 THUMB_SET_FUNC (symbolP, 1);
1625 ARM_SET_THUMB (symbolP, 1);
1626#if defined OBJ_ELF || defined OBJ_COFF
1627 ARM_SET_INTERWORK (symbolP, support_interwork);
1628#endif
1629}
1630
c19d1205 1631/* Directives: Mode selection. */
b99bd4ef 1632
c19d1205
ZW
1633/* .syntax [unified|divided] - choose the new unified syntax
1634 (same for Arm and Thumb encoding, modulo slight differences in what
1635 can be represented) or the old divergent syntax for each mode. */
b99bd4ef 1636static void
c19d1205 1637s_syntax (int unused ATTRIBUTE_UNUSED)
b99bd4ef 1638{
c19d1205
ZW
1639 char *name, delim;
1640
1641 name = input_line_pointer;
1642 delim = get_symbol_end ();
1643
1644 if (!strcasecmp (name, "unified"))
1645 unified_syntax = TRUE;
1646 else if (!strcasecmp (name, "divided"))
1647 unified_syntax = FALSE;
1648 else
1649 {
1650 as_bad (_("unrecognized syntax mode \"%s\""), name);
1651 return;
1652 }
1653 *input_line_pointer = delim;
b99bd4ef
NC
1654 demand_empty_rest_of_line ();
1655}
1656
c19d1205
ZW
1657/* Directives: sectioning and alignment. */
1658
1659/* Same as s_align_ptwo but align 0 => align 2. */
1660
b99bd4ef 1661static void
c19d1205 1662s_align (int unused ATTRIBUTE_UNUSED)
b99bd4ef 1663{
a737bd4d 1664 int temp;
c19d1205
ZW
1665 long temp_fill;
1666 long max_alignment = 15;
b99bd4ef
NC
1667
1668 temp = get_absolute_expression ();
c19d1205
ZW
1669 if (temp > max_alignment)
1670 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
1671 else if (temp < 0)
b99bd4ef 1672 {
c19d1205
ZW
1673 as_bad (_("alignment negative. 0 assumed."));
1674 temp = 0;
1675 }
b99bd4ef 1676
c19d1205
ZW
1677 if (*input_line_pointer == ',')
1678 {
1679 input_line_pointer++;
1680 temp_fill = get_absolute_expression ();
b99bd4ef 1681 }
c19d1205
ZW
1682 else
1683 temp_fill = 0;
b99bd4ef 1684
c19d1205
ZW
1685 if (!temp)
1686 temp = 2;
b99bd4ef 1687
c19d1205
ZW
1688 /* Only make a frag if we HAVE to. */
1689 if (temp && !need_pass_2)
1690 frag_align (temp, (int) temp_fill, 0);
1691 demand_empty_rest_of_line ();
1692
1693 record_alignment (now_seg, temp);
b99bd4ef
NC
1694}
1695
c19d1205
ZW
1696static void
1697s_bss (int ignore ATTRIBUTE_UNUSED)
b99bd4ef 1698{
c19d1205
ZW
1699 /* We don't support putting frags in the BSS segment, we fake it by
1700 marking in_bss, then looking at s_skip for clues. */
1701 subseg_set (bss_section, 0);
1702 demand_empty_rest_of_line ();
1703 mapping_state (MAP_DATA);
1704}
b99bd4ef 1705
c19d1205
ZW
1706static void
1707s_even (int ignore ATTRIBUTE_UNUSED)
1708{
1709 /* Never make frag if expect extra pass. */
1710 if (!need_pass_2)
1711 frag_align (1, 0, 0);
b99bd4ef 1712
c19d1205 1713 record_alignment (now_seg, 1);
b99bd4ef 1714
c19d1205 1715 demand_empty_rest_of_line ();
b99bd4ef
NC
1716}
1717
c19d1205 1718/* Directives: Literal pools. */
a737bd4d 1719
c19d1205
ZW
1720static literal_pool *
1721find_literal_pool (void)
a737bd4d 1722{
c19d1205 1723 literal_pool * pool;
a737bd4d 1724
c19d1205 1725 for (pool = list_of_pools; pool != NULL; pool = pool->next)
a737bd4d 1726 {
c19d1205
ZW
1727 if (pool->section == now_seg
1728 && pool->sub_section == now_subseg)
1729 break;
a737bd4d
NC
1730 }
1731
c19d1205 1732 return pool;
a737bd4d
NC
1733}
1734
c19d1205
ZW
1735static literal_pool *
1736find_or_make_literal_pool (void)
a737bd4d 1737{
c19d1205
ZW
1738 /* Next literal pool ID number. */
1739 static unsigned int latest_pool_num = 1;
1740 literal_pool * pool;
a737bd4d 1741
c19d1205 1742 pool = find_literal_pool ();
a737bd4d 1743
c19d1205 1744 if (pool == NULL)
a737bd4d 1745 {
c19d1205
ZW
1746 /* Create a new pool. */
1747 pool = xmalloc (sizeof (* pool));
1748 if (! pool)
1749 return NULL;
a737bd4d 1750
c19d1205
ZW
1751 pool->next_free_entry = 0;
1752 pool->section = now_seg;
1753 pool->sub_section = now_subseg;
1754 pool->next = list_of_pools;
1755 pool->symbol = NULL;
1756
1757 /* Add it to the list. */
1758 list_of_pools = pool;
a737bd4d 1759 }
a737bd4d 1760
c19d1205
ZW
1761 /* New pools, and emptied pools, will have a NULL symbol. */
1762 if (pool->symbol == NULL)
a737bd4d 1763 {
c19d1205
ZW
1764 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
1765 (valueT) 0, &zero_address_frag);
1766 pool->id = latest_pool_num ++;
a737bd4d
NC
1767 }
1768
c19d1205
ZW
1769 /* Done. */
1770 return pool;
a737bd4d
NC
1771}
1772
c19d1205
ZW
1773/* Add the literal in the global 'inst'
1774 structure to the relevent literal pool. */
b99bd4ef
NC
1775
1776static int
c19d1205 1777add_to_lit_pool (void)
b99bd4ef 1778{
c19d1205
ZW
1779 literal_pool * pool;
1780 unsigned int entry;
b99bd4ef 1781
c19d1205
ZW
1782 pool = find_or_make_literal_pool ();
1783
1784 /* Check if this literal value is already in the pool. */
1785 for (entry = 0; entry < pool->next_free_entry; entry ++)
b99bd4ef 1786 {
c19d1205
ZW
1787 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1788 && (inst.reloc.exp.X_op == O_constant)
1789 && (pool->literals[entry].X_add_number
1790 == inst.reloc.exp.X_add_number)
1791 && (pool->literals[entry].X_unsigned
1792 == inst.reloc.exp.X_unsigned))
1793 break;
1794
1795 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1796 && (inst.reloc.exp.X_op == O_symbol)
1797 && (pool->literals[entry].X_add_number
1798 == inst.reloc.exp.X_add_number)
1799 && (pool->literals[entry].X_add_symbol
1800 == inst.reloc.exp.X_add_symbol)
1801 && (pool->literals[entry].X_op_symbol
1802 == inst.reloc.exp.X_op_symbol))
1803 break;
b99bd4ef
NC
1804 }
1805
c19d1205
ZW
1806 /* Do we need to create a new entry? */
1807 if (entry == pool->next_free_entry)
1808 {
1809 if (entry >= MAX_LITERAL_POOL_SIZE)
1810 {
1811 inst.error = _("literal pool overflow");
1812 return FAIL;
1813 }
1814
1815 pool->literals[entry] = inst.reloc.exp;
1816 pool->next_free_entry += 1;
1817 }
b99bd4ef 1818
c19d1205
ZW
1819 inst.reloc.exp.X_op = O_symbol;
1820 inst.reloc.exp.X_add_number = ((int) entry) * 4;
1821 inst.reloc.exp.X_add_symbol = pool->symbol;
b99bd4ef 1822
c19d1205 1823 return SUCCESS;
b99bd4ef
NC
1824}
1825
c19d1205
ZW
1826/* Can't use symbol_new here, so have to create a symbol and then at
1827 a later date assign it a value. Thats what these functions do. */
e16bb312 1828
c19d1205
ZW
1829static void
1830symbol_locate (symbolS * symbolP,
1831 const char * name, /* It is copied, the caller can modify. */
1832 segT segment, /* Segment identifier (SEG_<something>). */
1833 valueT valu, /* Symbol value. */
1834 fragS * frag) /* Associated fragment. */
1835{
1836 unsigned int name_length;
1837 char * preserved_copy_of_name;
e16bb312 1838
c19d1205
ZW
1839 name_length = strlen (name) + 1; /* +1 for \0. */
1840 obstack_grow (&notes, name, name_length);
1841 preserved_copy_of_name = obstack_finish (&notes);
e16bb312 1842
c19d1205
ZW
1843#ifdef tc_canonicalize_symbol_name
1844 preserved_copy_of_name =
1845 tc_canonicalize_symbol_name (preserved_copy_of_name);
1846#endif
b99bd4ef 1847
c19d1205 1848 S_SET_NAME (symbolP, preserved_copy_of_name);
b99bd4ef 1849
c19d1205
ZW
1850 S_SET_SEGMENT (symbolP, segment);
1851 S_SET_VALUE (symbolP, valu);
1852 symbol_clear_list_pointers (symbolP);
b99bd4ef 1853
c19d1205 1854 symbol_set_frag (symbolP, frag);
b99bd4ef 1855
c19d1205
ZW
1856 /* Link to end of symbol chain. */
1857 {
1858 extern int symbol_table_frozen;
b99bd4ef 1859
c19d1205
ZW
1860 if (symbol_table_frozen)
1861 abort ();
1862 }
b99bd4ef 1863
c19d1205 1864 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
b99bd4ef 1865
c19d1205 1866 obj_symbol_new_hook (symbolP);
b99bd4ef 1867
c19d1205
ZW
1868#ifdef tc_symbol_new_hook
1869 tc_symbol_new_hook (symbolP);
1870#endif
1871
1872#ifdef DEBUG_SYMS
1873 verify_symbol_chain (symbol_rootP, symbol_lastP);
1874#endif /* DEBUG_SYMS */
b99bd4ef
NC
1875}
1876
b99bd4ef 1877
c19d1205
ZW
1878static void
1879s_ltorg (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 1880{
c19d1205
ZW
1881 unsigned int entry;
1882 literal_pool * pool;
1883 char sym_name[20];
b99bd4ef 1884
c19d1205
ZW
1885 pool = find_literal_pool ();
1886 if (pool == NULL
1887 || pool->symbol == NULL
1888 || pool->next_free_entry == 0)
1889 return;
b99bd4ef 1890
c19d1205 1891 mapping_state (MAP_DATA);
b99bd4ef 1892
c19d1205
ZW
1893 /* Align pool as you have word accesses.
1894 Only make a frag if we have to. */
1895 if (!need_pass_2)
1896 frag_align (2, 0, 0);
b99bd4ef 1897
c19d1205 1898 record_alignment (now_seg, 2);
b99bd4ef 1899
c19d1205 1900 sprintf (sym_name, "$$lit_\002%x", pool->id);
b99bd4ef 1901
c19d1205
ZW
1902 symbol_locate (pool->symbol, sym_name, now_seg,
1903 (valueT) frag_now_fix (), frag_now);
1904 symbol_table_insert (pool->symbol);
b99bd4ef 1905
c19d1205 1906 ARM_SET_THUMB (pool->symbol, thumb_mode);
b99bd4ef 1907
c19d1205
ZW
1908#if defined OBJ_COFF || defined OBJ_ELF
1909 ARM_SET_INTERWORK (pool->symbol, support_interwork);
1910#endif
6c43fab6 1911
c19d1205
ZW
1912 for (entry = 0; entry < pool->next_free_entry; entry ++)
1913 /* First output the expression in the instruction to the pool. */
1914 emit_expr (&(pool->literals[entry]), 4); /* .word */
b99bd4ef 1915
c19d1205
ZW
1916 /* Mark the pool as empty. */
1917 pool->next_free_entry = 0;
1918 pool->symbol = NULL;
b99bd4ef
NC
1919}
1920
c19d1205
ZW
1921#ifdef OBJ_ELF
1922/* Forward declarations for functions below, in the MD interface
1923 section. */
1924static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
1925static valueT create_unwind_entry (int);
1926static void start_unwind_section (const segT, int);
1927static void add_unwind_opcode (valueT, int);
1928static void flush_pending_unwind (void);
b99bd4ef 1929
c19d1205 1930/* Directives: Data. */
b99bd4ef 1931
c19d1205
ZW
1932static void
1933s_arm_elf_cons (int nbytes)
1934{
1935 expressionS exp;
b99bd4ef 1936
c19d1205
ZW
1937#ifdef md_flush_pending_output
1938 md_flush_pending_output ();
1939#endif
b99bd4ef 1940
c19d1205 1941 if (is_it_end_of_statement ())
b99bd4ef 1942 {
c19d1205
ZW
1943 demand_empty_rest_of_line ();
1944 return;
b99bd4ef
NC
1945 }
1946
c19d1205
ZW
1947#ifdef md_cons_align
1948 md_cons_align (nbytes);
1949#endif
b99bd4ef 1950
c19d1205
ZW
1951 mapping_state (MAP_DATA);
1952 do
b99bd4ef 1953 {
c19d1205
ZW
1954 int reloc;
1955 char *base = input_line_pointer;
b99bd4ef 1956
c19d1205 1957 expression (& exp);
b99bd4ef 1958
c19d1205
ZW
1959 if (exp.X_op != O_symbol)
1960 emit_expr (&exp, (unsigned int) nbytes);
1961 else
1962 {
1963 char *before_reloc = input_line_pointer;
1964 reloc = parse_reloc (&input_line_pointer);
1965 if (reloc == -1)
1966 {
1967 as_bad (_("unrecognized relocation suffix"));
1968 ignore_rest_of_line ();
1969 return;
1970 }
1971 else if (reloc == BFD_RELOC_UNUSED)
1972 emit_expr (&exp, (unsigned int) nbytes);
1973 else
1974 {
1975 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
1976 int size = bfd_get_reloc_size (howto);
b99bd4ef 1977
2fc8bdac
ZW
1978 if (reloc == BFD_RELOC_ARM_PLT32)
1979 {
1980 as_bad (_("(plt) is only valid on branch targets"));
1981 reloc = BFD_RELOC_UNUSED;
1982 size = 0;
1983 }
1984
c19d1205 1985 if (size > nbytes)
2fc8bdac 1986 as_bad (_("%s relocations do not fit in %d bytes"),
c19d1205
ZW
1987 howto->name, nbytes);
1988 else
1989 {
1990 /* We've parsed an expression stopping at O_symbol.
1991 But there may be more expression left now that we
1992 have parsed the relocation marker. Parse it again.
1993 XXX Surely there is a cleaner way to do this. */
1994 char *p = input_line_pointer;
1995 int offset;
1996 char *save_buf = alloca (input_line_pointer - base);
1997 memcpy (save_buf, base, input_line_pointer - base);
1998 memmove (base + (input_line_pointer - before_reloc),
1999 base, before_reloc - base);
2000
2001 input_line_pointer = base + (input_line_pointer-before_reloc);
2002 expression (&exp);
2003 memcpy (base, save_buf, p - base);
2004
2005 offset = nbytes - size;
2006 p = frag_more ((int) nbytes);
2007 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
2008 size, &exp, 0, reloc);
2009 }
2010 }
2011 }
b99bd4ef 2012 }
c19d1205 2013 while (*input_line_pointer++ == ',');
b99bd4ef 2014
c19d1205
ZW
2015 /* Put terminator back into stream. */
2016 input_line_pointer --;
2017 demand_empty_rest_of_line ();
b99bd4ef
NC
2018}
2019
b99bd4ef 2020
c19d1205 2021/* Parse a .rel31 directive. */
b99bd4ef 2022
c19d1205
ZW
2023static void
2024s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
2025{
2026 expressionS exp;
2027 char *p;
2028 valueT highbit;
b99bd4ef 2029
c19d1205
ZW
2030 highbit = 0;
2031 if (*input_line_pointer == '1')
2032 highbit = 0x80000000;
2033 else if (*input_line_pointer != '0')
2034 as_bad (_("expected 0 or 1"));
b99bd4ef 2035
c19d1205
ZW
2036 input_line_pointer++;
2037 if (*input_line_pointer != ',')
2038 as_bad (_("missing comma"));
2039 input_line_pointer++;
b99bd4ef 2040
c19d1205
ZW
2041#ifdef md_flush_pending_output
2042 md_flush_pending_output ();
2043#endif
b99bd4ef 2044
c19d1205
ZW
2045#ifdef md_cons_align
2046 md_cons_align (4);
2047#endif
b99bd4ef 2048
c19d1205 2049 mapping_state (MAP_DATA);
b99bd4ef 2050
c19d1205 2051 expression (&exp);
b99bd4ef 2052
c19d1205
ZW
2053 p = frag_more (4);
2054 md_number_to_chars (p, highbit, 4);
2055 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
2056 BFD_RELOC_ARM_PREL31);
b99bd4ef 2057
c19d1205 2058 demand_empty_rest_of_line ();
b99bd4ef
NC
2059}
2060
c19d1205 2061/* Directives: AEABI stack-unwind tables. */
b99bd4ef 2062
c19d1205 2063/* Parse an unwind_fnstart directive. Simply records the current location. */
b99bd4ef 2064
c19d1205
ZW
2065static void
2066s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
2067{
2068 demand_empty_rest_of_line ();
2069 /* Mark the start of the function. */
2070 unwind.proc_start = expr_build_dot ();
b99bd4ef 2071
c19d1205
ZW
2072 /* Reset the rest of the unwind info. */
2073 unwind.opcode_count = 0;
2074 unwind.table_entry = NULL;
2075 unwind.personality_routine = NULL;
2076 unwind.personality_index = -1;
2077 unwind.frame_size = 0;
2078 unwind.fp_offset = 0;
2079 unwind.fp_reg = 13;
2080 unwind.fp_used = 0;
2081 unwind.sp_restored = 0;
2082}
b99bd4ef 2083
b99bd4ef 2084
c19d1205
ZW
2085/* Parse a handlerdata directive. Creates the exception handling table entry
2086 for the function. */
b99bd4ef 2087
c19d1205
ZW
2088static void
2089s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
2090{
2091 demand_empty_rest_of_line ();
2092 if (unwind.table_entry)
2093 as_bad (_("dupicate .handlerdata directive"));
f02232aa 2094
c19d1205
ZW
2095 create_unwind_entry (1);
2096}
a737bd4d 2097
c19d1205 2098/* Parse an unwind_fnend directive. Generates the index table entry. */
b99bd4ef 2099
c19d1205
ZW
2100static void
2101s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
2102{
2103 long where;
2104 char *ptr;
2105 valueT val;
f02232aa 2106
c19d1205 2107 demand_empty_rest_of_line ();
f02232aa 2108
c19d1205
ZW
2109 /* Add eh table entry. */
2110 if (unwind.table_entry == NULL)
2111 val = create_unwind_entry (0);
2112 else
2113 val = 0;
f02232aa 2114
c19d1205
ZW
2115 /* Add index table entry. This is two words. */
2116 start_unwind_section (unwind.saved_seg, 1);
2117 frag_align (2, 0, 0);
2118 record_alignment (now_seg, 2);
b99bd4ef 2119
c19d1205
ZW
2120 ptr = frag_more (8);
2121 where = frag_now_fix () - 8;
f02232aa 2122
c19d1205
ZW
2123 /* Self relative offset of the function start. */
2124 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
2125 BFD_RELOC_ARM_PREL31);
f02232aa 2126
c19d1205
ZW
2127 /* Indicate dependency on EHABI-defined personality routines to the
2128 linker, if it hasn't been done already. */
2129 if (unwind.personality_index >= 0 && unwind.personality_index < 3
2130 && !(marked_pr_dependency & (1 << unwind.personality_index)))
2131 {
2132 static const char *const name[] = {
2133 "__aeabi_unwind_cpp_pr0",
2134 "__aeabi_unwind_cpp_pr1",
2135 "__aeabi_unwind_cpp_pr2"
2136 };
2137 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
2138 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
2139 marked_pr_dependency |= 1 << unwind.personality_index;
2140 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
2141 = marked_pr_dependency;
2142 }
f02232aa 2143
c19d1205
ZW
2144 if (val)
2145 /* Inline exception table entry. */
2146 md_number_to_chars (ptr + 4, val, 4);
2147 else
2148 /* Self relative offset of the table entry. */
2149 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
2150 BFD_RELOC_ARM_PREL31);
f02232aa 2151
c19d1205
ZW
2152 /* Restore the original section. */
2153 subseg_set (unwind.saved_seg, unwind.saved_subseg);
2154}
f02232aa 2155
f02232aa 2156
c19d1205 2157/* Parse an unwind_cantunwind directive. */
b99bd4ef 2158
c19d1205
ZW
2159static void
2160s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
2161{
2162 demand_empty_rest_of_line ();
2163 if (unwind.personality_routine || unwind.personality_index != -1)
2164 as_bad (_("personality routine specified for cantunwind frame"));
b99bd4ef 2165
c19d1205
ZW
2166 unwind.personality_index = -2;
2167}
b99bd4ef 2168
b99bd4ef 2169
c19d1205 2170/* Parse a personalityindex directive. */
b99bd4ef 2171
c19d1205
ZW
2172static void
2173s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
2174{
2175 expressionS exp;
b99bd4ef 2176
c19d1205
ZW
2177 if (unwind.personality_routine || unwind.personality_index != -1)
2178 as_bad (_("duplicate .personalityindex directive"));
b99bd4ef 2179
c19d1205 2180 expression (&exp);
b99bd4ef 2181
c19d1205
ZW
2182 if (exp.X_op != O_constant
2183 || exp.X_add_number < 0 || exp.X_add_number > 15)
b99bd4ef 2184 {
c19d1205
ZW
2185 as_bad (_("bad personality routine number"));
2186 ignore_rest_of_line ();
2187 return;
b99bd4ef
NC
2188 }
2189
c19d1205 2190 unwind.personality_index = exp.X_add_number;
b99bd4ef 2191
c19d1205
ZW
2192 demand_empty_rest_of_line ();
2193}
e16bb312 2194
e16bb312 2195
c19d1205 2196/* Parse a personality directive. */
e16bb312 2197
c19d1205
ZW
2198static void
2199s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
2200{
2201 char *name, *p, c;
a737bd4d 2202
c19d1205
ZW
2203 if (unwind.personality_routine || unwind.personality_index != -1)
2204 as_bad (_("duplicate .personality directive"));
a737bd4d 2205
c19d1205
ZW
2206 name = input_line_pointer;
2207 c = get_symbol_end ();
2208 p = input_line_pointer;
2209 unwind.personality_routine = symbol_find_or_make (name);
2210 *p = c;
2211 demand_empty_rest_of_line ();
2212}
e16bb312 2213
e16bb312 2214
c19d1205 2215/* Parse a directive saving core registers. */
e16bb312 2216
c19d1205
ZW
2217static void
2218s_arm_unwind_save_core (void)
e16bb312 2219{
c19d1205
ZW
2220 valueT op;
2221 long range;
2222 int n;
e16bb312 2223
c19d1205
ZW
2224 range = parse_reg_list (&input_line_pointer);
2225 if (range == FAIL)
e16bb312 2226 {
c19d1205
ZW
2227 as_bad (_("expected register list"));
2228 ignore_rest_of_line ();
2229 return;
2230 }
e16bb312 2231
c19d1205 2232 demand_empty_rest_of_line ();
e16bb312 2233
c19d1205
ZW
2234 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
2235 into .unwind_save {..., sp...}. We aren't bothered about the value of
2236 ip because it is clobbered by calls. */
2237 if (unwind.sp_restored && unwind.fp_reg == 12
2238 && (range & 0x3000) == 0x1000)
2239 {
2240 unwind.opcode_count--;
2241 unwind.sp_restored = 0;
2242 range = (range | 0x2000) & ~0x1000;
2243 unwind.pending_offset = 0;
2244 }
e16bb312 2245
c19d1205
ZW
2246 /* See if we can use the short opcodes. These pop a block of upto 8
2247 registers starting with r4, plus maybe r14. */
2248 for (n = 0; n < 8; n++)
2249 {
2250 /* Break at the first non-saved register. */
2251 if ((range & (1 << (n + 4))) == 0)
2252 break;
e16bb312 2253 }
c19d1205
ZW
2254 /* See if there are any other bits set. */
2255 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
e16bb312 2256 {
c19d1205
ZW
2257 /* Use the long form. */
2258 op = 0x8000 | ((range >> 4) & 0xfff);
2259 add_unwind_opcode (op, 2);
e16bb312 2260 }
c19d1205 2261 else
0dd132b6 2262 {
c19d1205
ZW
2263 /* Use the short form. */
2264 if (range & 0x4000)
2265 op = 0xa8; /* Pop r14. */
0dd132b6 2266 else
c19d1205
ZW
2267 op = 0xa0; /* Do not pop r14. */
2268 op |= (n - 1);
2269 add_unwind_opcode (op, 1);
2270 }
0dd132b6 2271
c19d1205
ZW
2272 /* Pop r0-r3. */
2273 if (range & 0xf)
2274 {
2275 op = 0xb100 | (range & 0xf);
2276 add_unwind_opcode (op, 2);
0dd132b6
NC
2277 }
2278
c19d1205
ZW
2279 /* Record the number of bytes pushed. */
2280 for (n = 0; n < 16; n++)
2281 {
2282 if (range & (1 << n))
2283 unwind.frame_size += 4;
2284 }
0dd132b6
NC
2285}
2286
c19d1205
ZW
2287
2288/* Parse a directive saving FPA registers. */
b99bd4ef
NC
2289
2290static void
c19d1205 2291s_arm_unwind_save_fpa (int reg)
b99bd4ef 2292{
c19d1205
ZW
2293 expressionS exp;
2294 int num_regs;
2295 valueT op;
b99bd4ef 2296
c19d1205
ZW
2297 /* Get Number of registers to transfer. */
2298 if (skip_past_comma (&input_line_pointer) != FAIL)
2299 expression (&exp);
2300 else
2301 exp.X_op = O_illegal;
b99bd4ef 2302
c19d1205 2303 if (exp.X_op != O_constant)
b99bd4ef 2304 {
c19d1205
ZW
2305 as_bad (_("expected , <constant>"));
2306 ignore_rest_of_line ();
b99bd4ef
NC
2307 return;
2308 }
2309
c19d1205
ZW
2310 num_regs = exp.X_add_number;
2311
2312 if (num_regs < 1 || num_regs > 4)
b99bd4ef 2313 {
c19d1205
ZW
2314 as_bad (_("number of registers must be in the range [1:4]"));
2315 ignore_rest_of_line ();
b99bd4ef
NC
2316 return;
2317 }
2318
c19d1205 2319 demand_empty_rest_of_line ();
b99bd4ef 2320
c19d1205
ZW
2321 if (reg == 4)
2322 {
2323 /* Short form. */
2324 op = 0xb4 | (num_regs - 1);
2325 add_unwind_opcode (op, 1);
2326 }
b99bd4ef
NC
2327 else
2328 {
c19d1205
ZW
2329 /* Long form. */
2330 op = 0xc800 | (reg << 4) | (num_regs - 1);
2331 add_unwind_opcode (op, 2);
b99bd4ef 2332 }
c19d1205 2333 unwind.frame_size += num_regs * 12;
b99bd4ef
NC
2334}
2335
c19d1205
ZW
2336
2337/* Parse a directive saving VFP registers. */
b99bd4ef
NC
2338
2339static void
c19d1205 2340s_arm_unwind_save_vfp (void)
b99bd4ef 2341{
c19d1205 2342 int count;
ca3f61f7 2343 unsigned int reg;
c19d1205 2344 valueT op;
b99bd4ef 2345
c19d1205
ZW
2346 count = parse_vfp_reg_list (&input_line_pointer, &reg, 1);
2347 if (count == FAIL)
b99bd4ef 2348 {
c19d1205
ZW
2349 as_bad (_("expected register list"));
2350 ignore_rest_of_line ();
b99bd4ef
NC
2351 return;
2352 }
2353
c19d1205 2354 demand_empty_rest_of_line ();
b99bd4ef 2355
c19d1205 2356 if (reg == 8)
b99bd4ef 2357 {
c19d1205
ZW
2358 /* Short form. */
2359 op = 0xb8 | (count - 1);
2360 add_unwind_opcode (op, 1);
b99bd4ef 2361 }
c19d1205 2362 else
b99bd4ef 2363 {
c19d1205
ZW
2364 /* Long form. */
2365 op = 0xb300 | (reg << 4) | (count - 1);
2366 add_unwind_opcode (op, 2);
b99bd4ef 2367 }
c19d1205
ZW
2368 unwind.frame_size += count * 8 + 4;
2369}
b99bd4ef 2370
b99bd4ef 2371
c19d1205
ZW
2372/* Parse a directive saving iWMMXt data registers. */
2373
2374static void
2375s_arm_unwind_save_mmxwr (void)
2376{
2377 int reg;
2378 int hi_reg;
2379 int i;
2380 unsigned mask = 0;
2381 valueT op;
b99bd4ef 2382
c19d1205
ZW
2383 if (*input_line_pointer == '{')
2384 input_line_pointer++;
b99bd4ef 2385
c19d1205 2386 do
b99bd4ef 2387 {
c19d1205 2388 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
b99bd4ef 2389
c19d1205 2390 if (reg == FAIL)
b99bd4ef 2391 {
c19d1205
ZW
2392 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2393 goto error;
b99bd4ef
NC
2394 }
2395
c19d1205
ZW
2396 if (mask >> reg)
2397 as_tsktsk (_("register list not in ascending order"));
2398 mask |= 1 << reg;
b99bd4ef 2399
c19d1205
ZW
2400 if (*input_line_pointer == '-')
2401 {
2402 input_line_pointer++;
2403 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
2404 if (hi_reg == FAIL)
2405 {
2406 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2407 goto error;
2408 }
2409 else if (reg >= hi_reg)
2410 {
2411 as_bad (_("bad register range"));
2412 goto error;
2413 }
2414 for (; reg < hi_reg; reg++)
2415 mask |= 1 << reg;
2416 }
2417 }
2418 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 2419
c19d1205
ZW
2420 if (*input_line_pointer == '}')
2421 input_line_pointer++;
b99bd4ef 2422
c19d1205 2423 demand_empty_rest_of_line ();
b99bd4ef 2424
c19d1205
ZW
2425 /* Generate any deferred opcodes becuuse we're going to be looking at
2426 the list. */
2427 flush_pending_unwind ();
b99bd4ef 2428
c19d1205 2429 for (i = 0; i < 16; i++)
b99bd4ef 2430 {
c19d1205
ZW
2431 if (mask & (1 << i))
2432 unwind.frame_size += 8;
b99bd4ef
NC
2433 }
2434
c19d1205
ZW
2435 /* Attempt to combine with a previous opcode. We do this because gcc
2436 likes to output separate unwind directives for a single block of
2437 registers. */
2438 if (unwind.opcode_count > 0)
b99bd4ef 2439 {
c19d1205
ZW
2440 i = unwind.opcodes[unwind.opcode_count - 1];
2441 if ((i & 0xf8) == 0xc0)
2442 {
2443 i &= 7;
2444 /* Only merge if the blocks are contiguous. */
2445 if (i < 6)
2446 {
2447 if ((mask & 0xfe00) == (1 << 9))
2448 {
2449 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
2450 unwind.opcode_count--;
2451 }
2452 }
2453 else if (i == 6 && unwind.opcode_count >= 2)
2454 {
2455 i = unwind.opcodes[unwind.opcode_count - 2];
2456 reg = i >> 4;
2457 i &= 0xf;
b99bd4ef 2458
c19d1205
ZW
2459 op = 0xffff << (reg - 1);
2460 if (reg > 0
2461 || ((mask & op) == (1u << (reg - 1))))
2462 {
2463 op = (1 << (reg + i + 1)) - 1;
2464 op &= ~((1 << reg) - 1);
2465 mask |= op;
2466 unwind.opcode_count -= 2;
2467 }
2468 }
2469 }
b99bd4ef
NC
2470 }
2471
c19d1205
ZW
2472 hi_reg = 15;
2473 /* We want to generate opcodes in the order the registers have been
2474 saved, ie. descending order. */
2475 for (reg = 15; reg >= -1; reg--)
b99bd4ef 2476 {
c19d1205
ZW
2477 /* Save registers in blocks. */
2478 if (reg < 0
2479 || !(mask & (1 << reg)))
2480 {
2481 /* We found an unsaved reg. Generate opcodes to save the
2482 preceeding block. */
2483 if (reg != hi_reg)
2484 {
2485 if (reg == 9)
2486 {
2487 /* Short form. */
2488 op = 0xc0 | (hi_reg - 10);
2489 add_unwind_opcode (op, 1);
2490 }
2491 else
2492 {
2493 /* Long form. */
2494 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
2495 add_unwind_opcode (op, 2);
2496 }
2497 }
2498 hi_reg = reg - 1;
2499 }
b99bd4ef
NC
2500 }
2501
c19d1205
ZW
2502 return;
2503error:
2504 ignore_rest_of_line ();
b99bd4ef
NC
2505}
2506
2507static void
c19d1205 2508s_arm_unwind_save_mmxwcg (void)
b99bd4ef 2509{
c19d1205
ZW
2510 int reg;
2511 int hi_reg;
2512 unsigned mask = 0;
2513 valueT op;
b99bd4ef 2514
c19d1205
ZW
2515 if (*input_line_pointer == '{')
2516 input_line_pointer++;
b99bd4ef 2517
c19d1205 2518 do
b99bd4ef 2519 {
c19d1205 2520 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
b99bd4ef 2521
c19d1205
ZW
2522 if (reg == FAIL)
2523 {
2524 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2525 goto error;
2526 }
b99bd4ef 2527
c19d1205
ZW
2528 reg -= 8;
2529 if (mask >> reg)
2530 as_tsktsk (_("register list not in ascending order"));
2531 mask |= 1 << reg;
b99bd4ef 2532
c19d1205
ZW
2533 if (*input_line_pointer == '-')
2534 {
2535 input_line_pointer++;
2536 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
2537 if (hi_reg == FAIL)
2538 {
2539 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2540 goto error;
2541 }
2542 else if (reg >= hi_reg)
2543 {
2544 as_bad (_("bad register range"));
2545 goto error;
2546 }
2547 for (; reg < hi_reg; reg++)
2548 mask |= 1 << reg;
2549 }
b99bd4ef 2550 }
c19d1205 2551 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 2552
c19d1205
ZW
2553 if (*input_line_pointer == '}')
2554 input_line_pointer++;
b99bd4ef 2555
c19d1205
ZW
2556 demand_empty_rest_of_line ();
2557
2558 /* Generate any deferred opcodes becuuse we're going to be looking at
2559 the list. */
2560 flush_pending_unwind ();
b99bd4ef 2561
c19d1205 2562 for (reg = 0; reg < 16; reg++)
b99bd4ef 2563 {
c19d1205
ZW
2564 if (mask & (1 << reg))
2565 unwind.frame_size += 4;
b99bd4ef 2566 }
c19d1205
ZW
2567 op = 0xc700 | mask;
2568 add_unwind_opcode (op, 2);
2569 return;
2570error:
2571 ignore_rest_of_line ();
b99bd4ef
NC
2572}
2573
c19d1205
ZW
2574
2575/* Parse an unwind_save directive. */
2576
b99bd4ef 2577static void
c19d1205 2578s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 2579{
c19d1205
ZW
2580 char *peek;
2581 struct reg_entry *reg;
2582 bfd_boolean had_brace = FALSE;
b99bd4ef 2583
c19d1205
ZW
2584 /* Figure out what sort of save we have. */
2585 peek = input_line_pointer;
b99bd4ef 2586
c19d1205 2587 if (*peek == '{')
b99bd4ef 2588 {
c19d1205
ZW
2589 had_brace = TRUE;
2590 peek++;
b99bd4ef
NC
2591 }
2592
c19d1205 2593 reg = arm_reg_parse_multi (&peek);
b99bd4ef 2594
c19d1205 2595 if (!reg)
b99bd4ef 2596 {
c19d1205
ZW
2597 as_bad (_("register expected"));
2598 ignore_rest_of_line ();
b99bd4ef
NC
2599 return;
2600 }
2601
c19d1205 2602 switch (reg->type)
b99bd4ef 2603 {
c19d1205
ZW
2604 case REG_TYPE_FN:
2605 if (had_brace)
2606 {
2607 as_bad (_("FPA .unwind_save does not take a register list"));
2608 ignore_rest_of_line ();
2609 return;
2610 }
2611 s_arm_unwind_save_fpa (reg->number);
b99bd4ef 2612 return;
c19d1205
ZW
2613
2614 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
2615 case REG_TYPE_VFD: s_arm_unwind_save_vfp (); return;
2616 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
2617 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
2618
2619 default:
2620 as_bad (_(".unwind_save does not support this kind of register"));
2621 ignore_rest_of_line ();
b99bd4ef 2622 }
c19d1205 2623}
b99bd4ef 2624
b99bd4ef 2625
c19d1205
ZW
2626/* Parse an unwind_movsp directive. */
2627
2628static void
2629s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
2630{
2631 int reg;
2632 valueT op;
2633
2634 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2635 if (reg == FAIL)
b99bd4ef 2636 {
c19d1205
ZW
2637 as_bad (_(reg_expected_msgs[REG_TYPE_RN]));
2638 ignore_rest_of_line ();
b99bd4ef
NC
2639 return;
2640 }
c19d1205 2641 demand_empty_rest_of_line ();
b99bd4ef 2642
c19d1205 2643 if (reg == REG_SP || reg == REG_PC)
b99bd4ef 2644 {
c19d1205 2645 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
b99bd4ef
NC
2646 return;
2647 }
2648
c19d1205
ZW
2649 if (unwind.fp_reg != REG_SP)
2650 as_bad (_("unexpected .unwind_movsp directive"));
b99bd4ef 2651
c19d1205
ZW
2652 /* Generate opcode to restore the value. */
2653 op = 0x90 | reg;
2654 add_unwind_opcode (op, 1);
2655
2656 /* Record the information for later. */
2657 unwind.fp_reg = reg;
2658 unwind.fp_offset = unwind.frame_size;
2659 unwind.sp_restored = 1;
b05fe5cf
ZW
2660}
2661
c19d1205
ZW
2662/* Parse an unwind_pad directive. */
2663
b05fe5cf 2664static void
c19d1205 2665s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
b05fe5cf 2666{
c19d1205 2667 int offset;
b05fe5cf 2668
c19d1205
ZW
2669 if (immediate_for_directive (&offset) == FAIL)
2670 return;
b99bd4ef 2671
c19d1205
ZW
2672 if (offset & 3)
2673 {
2674 as_bad (_("stack increment must be multiple of 4"));
2675 ignore_rest_of_line ();
2676 return;
2677 }
b99bd4ef 2678
c19d1205
ZW
2679 /* Don't generate any opcodes, just record the details for later. */
2680 unwind.frame_size += offset;
2681 unwind.pending_offset += offset;
2682
2683 demand_empty_rest_of_line ();
2684}
2685
2686/* Parse an unwind_setfp directive. */
2687
2688static void
2689s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 2690{
c19d1205
ZW
2691 int sp_reg;
2692 int fp_reg;
2693 int offset;
2694
2695 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2696 if (skip_past_comma (&input_line_pointer) == FAIL)
2697 sp_reg = FAIL;
2698 else
2699 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
b99bd4ef 2700
c19d1205
ZW
2701 if (fp_reg == FAIL || sp_reg == FAIL)
2702 {
2703 as_bad (_("expected <reg>, <reg>"));
2704 ignore_rest_of_line ();
2705 return;
2706 }
b99bd4ef 2707
c19d1205
ZW
2708 /* Optional constant. */
2709 if (skip_past_comma (&input_line_pointer) != FAIL)
2710 {
2711 if (immediate_for_directive (&offset) == FAIL)
2712 return;
2713 }
2714 else
2715 offset = 0;
a737bd4d 2716
c19d1205 2717 demand_empty_rest_of_line ();
a737bd4d 2718
c19d1205 2719 if (sp_reg != 13 && sp_reg != unwind.fp_reg)
a737bd4d 2720 {
c19d1205
ZW
2721 as_bad (_("register must be either sp or set by a previous"
2722 "unwind_movsp directive"));
2723 return;
a737bd4d
NC
2724 }
2725
c19d1205
ZW
2726 /* Don't generate any opcodes, just record the information for later. */
2727 unwind.fp_reg = fp_reg;
2728 unwind.fp_used = 1;
2729 if (sp_reg == 13)
2730 unwind.fp_offset = unwind.frame_size - offset;
2731 else
2732 unwind.fp_offset -= offset;
a737bd4d
NC
2733}
2734
c19d1205
ZW
2735/* Parse an unwind_raw directive. */
2736
2737static void
2738s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
a737bd4d 2739{
c19d1205
ZW
2740 expressionS exp;
2741 /* This is an arbitary limit. */
2742 unsigned char op[16];
2743 int count;
a737bd4d 2744
c19d1205
ZW
2745 expression (&exp);
2746 if (exp.X_op == O_constant
2747 && skip_past_comma (&input_line_pointer) != FAIL)
a737bd4d 2748 {
c19d1205
ZW
2749 unwind.frame_size += exp.X_add_number;
2750 expression (&exp);
2751 }
2752 else
2753 exp.X_op = O_illegal;
a737bd4d 2754
c19d1205
ZW
2755 if (exp.X_op != O_constant)
2756 {
2757 as_bad (_("expected <offset>, <opcode>"));
2758 ignore_rest_of_line ();
2759 return;
2760 }
a737bd4d 2761
c19d1205 2762 count = 0;
a737bd4d 2763
c19d1205
ZW
2764 /* Parse the opcode. */
2765 for (;;)
2766 {
2767 if (count >= 16)
2768 {
2769 as_bad (_("unwind opcode too long"));
2770 ignore_rest_of_line ();
a737bd4d 2771 }
c19d1205 2772 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
a737bd4d 2773 {
c19d1205
ZW
2774 as_bad (_("invalid unwind opcode"));
2775 ignore_rest_of_line ();
2776 return;
a737bd4d 2777 }
c19d1205 2778 op[count++] = exp.X_add_number;
a737bd4d 2779
c19d1205
ZW
2780 /* Parse the next byte. */
2781 if (skip_past_comma (&input_line_pointer) == FAIL)
2782 break;
a737bd4d 2783
c19d1205
ZW
2784 expression (&exp);
2785 }
b99bd4ef 2786
c19d1205
ZW
2787 /* Add the opcode bytes in reverse order. */
2788 while (count--)
2789 add_unwind_opcode (op[count], 1);
b99bd4ef 2790
c19d1205 2791 demand_empty_rest_of_line ();
b99bd4ef 2792}
c19d1205 2793#endif /* OBJ_ELF */
b99bd4ef 2794
c19d1205
ZW
2795/* This table describes all the machine specific pseudo-ops the assembler
2796 has to support. The fields are:
2797 pseudo-op name without dot
2798 function to call to execute this pseudo-op
2799 Integer arg to pass to the function. */
b99bd4ef 2800
c19d1205 2801const pseudo_typeS md_pseudo_table[] =
b99bd4ef 2802{
c19d1205
ZW
2803 /* Never called because '.req' does not start a line. */
2804 { "req", s_req, 0 },
2805 { "unreq", s_unreq, 0 },
2806 { "bss", s_bss, 0 },
2807 { "align", s_align, 0 },
2808 { "arm", s_arm, 0 },
2809 { "thumb", s_thumb, 0 },
2810 { "code", s_code, 0 },
2811 { "force_thumb", s_force_thumb, 0 },
2812 { "thumb_func", s_thumb_func, 0 },
2813 { "thumb_set", s_thumb_set, 0 },
2814 { "even", s_even, 0 },
2815 { "ltorg", s_ltorg, 0 },
2816 { "pool", s_ltorg, 0 },
2817 { "syntax", s_syntax, 0 },
2818#ifdef OBJ_ELF
2819 { "word", s_arm_elf_cons, 4 },
2820 { "long", s_arm_elf_cons, 4 },
2821 { "rel31", s_arm_rel31, 0 },
2822 { "fnstart", s_arm_unwind_fnstart, 0 },
2823 { "fnend", s_arm_unwind_fnend, 0 },
2824 { "cantunwind", s_arm_unwind_cantunwind, 0 },
2825 { "personality", s_arm_unwind_personality, 0 },
2826 { "personalityindex", s_arm_unwind_personalityindex, 0 },
2827 { "handlerdata", s_arm_unwind_handlerdata, 0 },
2828 { "save", s_arm_unwind_save, 0 },
2829 { "movsp", s_arm_unwind_movsp, 0 },
2830 { "pad", s_arm_unwind_pad, 0 },
2831 { "setfp", s_arm_unwind_setfp, 0 },
2832 { "unwind_raw", s_arm_unwind_raw, 0 },
2833#else
2834 { "word", cons, 4},
2835#endif
2836 { "extend", float_cons, 'x' },
2837 { "ldouble", float_cons, 'x' },
2838 { "packed", float_cons, 'p' },
2839 { 0, 0, 0 }
2840};
2841\f
2842/* Parser functions used exclusively in instruction operands. */
b99bd4ef 2843
c19d1205
ZW
2844/* Generic immediate-value read function for use in insn parsing.
2845 STR points to the beginning of the immediate (the leading #);
2846 VAL receives the value; if the value is outside [MIN, MAX]
2847 issue an error. PREFIX_OPT is true if the immediate prefix is
2848 optional. */
b99bd4ef 2849
c19d1205
ZW
2850static int
2851parse_immediate (char **str, int *val, int min, int max,
2852 bfd_boolean prefix_opt)
2853{
2854 expressionS exp;
2855 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
2856 if (exp.X_op != O_constant)
b99bd4ef 2857 {
c19d1205
ZW
2858 inst.error = _("constant expression required");
2859 return FAIL;
2860 }
b99bd4ef 2861
c19d1205
ZW
2862 if (exp.X_add_number < min || exp.X_add_number > max)
2863 {
2864 inst.error = _("immediate value out of range");
2865 return FAIL;
2866 }
b99bd4ef 2867
c19d1205
ZW
2868 *val = exp.X_add_number;
2869 return SUCCESS;
2870}
b99bd4ef 2871
c19d1205
ZW
2872/* Returns the pseudo-register number of an FPA immediate constant,
2873 or FAIL if there isn't a valid constant here. */
b99bd4ef 2874
c19d1205
ZW
2875static int
2876parse_fpa_immediate (char ** str)
2877{
2878 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2879 char * save_in;
2880 expressionS exp;
2881 int i;
2882 int j;
b99bd4ef 2883
c19d1205
ZW
2884 /* First try and match exact strings, this is to guarantee
2885 that some formats will work even for cross assembly. */
b99bd4ef 2886
c19d1205
ZW
2887 for (i = 0; fp_const[i]; i++)
2888 {
2889 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
b99bd4ef 2890 {
c19d1205 2891 char *start = *str;
b99bd4ef 2892
c19d1205
ZW
2893 *str += strlen (fp_const[i]);
2894 if (is_end_of_line[(unsigned char) **str])
2895 return i + 8;
2896 *str = start;
2897 }
2898 }
b99bd4ef 2899
c19d1205
ZW
2900 /* Just because we didn't get a match doesn't mean that the constant
2901 isn't valid, just that it is in a format that we don't
2902 automatically recognize. Try parsing it with the standard
2903 expression routines. */
b99bd4ef 2904
c19d1205 2905 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
b99bd4ef 2906
c19d1205
ZW
2907 /* Look for a raw floating point number. */
2908 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
2909 && is_end_of_line[(unsigned char) *save_in])
2910 {
2911 for (i = 0; i < NUM_FLOAT_VALS; i++)
2912 {
2913 for (j = 0; j < MAX_LITTLENUMS; j++)
b99bd4ef 2914 {
c19d1205
ZW
2915 if (words[j] != fp_values[i][j])
2916 break;
b99bd4ef
NC
2917 }
2918
c19d1205 2919 if (j == MAX_LITTLENUMS)
b99bd4ef 2920 {
c19d1205
ZW
2921 *str = save_in;
2922 return i + 8;
b99bd4ef
NC
2923 }
2924 }
2925 }
b99bd4ef 2926
c19d1205
ZW
2927 /* Try and parse a more complex expression, this will probably fail
2928 unless the code uses a floating point prefix (eg "0f"). */
2929 save_in = input_line_pointer;
2930 input_line_pointer = *str;
2931 if (expression (&exp) == absolute_section
2932 && exp.X_op == O_big
2933 && exp.X_add_number < 0)
2934 {
2935 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2936 Ditto for 15. */
2937 if (gen_to_words (words, 5, (long) 15) == 0)
2938 {
2939 for (i = 0; i < NUM_FLOAT_VALS; i++)
2940 {
2941 for (j = 0; j < MAX_LITTLENUMS; j++)
2942 {
2943 if (words[j] != fp_values[i][j])
2944 break;
2945 }
b99bd4ef 2946
c19d1205
ZW
2947 if (j == MAX_LITTLENUMS)
2948 {
2949 *str = input_line_pointer;
2950 input_line_pointer = save_in;
2951 return i + 8;
2952 }
2953 }
2954 }
b99bd4ef
NC
2955 }
2956
c19d1205
ZW
2957 *str = input_line_pointer;
2958 input_line_pointer = save_in;
2959 inst.error = _("invalid FPA immediate expression");
2960 return FAIL;
b99bd4ef
NC
2961}
2962
c19d1205
ZW
2963/* Shift operands. */
2964enum shift_kind
b99bd4ef 2965{
c19d1205
ZW
2966 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
2967};
b99bd4ef 2968
c19d1205
ZW
2969struct asm_shift_name
2970{
2971 const char *name;
2972 enum shift_kind kind;
2973};
b99bd4ef 2974
c19d1205
ZW
2975/* Third argument to parse_shift. */
2976enum parse_shift_mode
2977{
2978 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
2979 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
2980 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
2981 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
2982 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
2983};
b99bd4ef 2984
c19d1205
ZW
2985/* Parse a <shift> specifier on an ARM data processing instruction.
2986 This has three forms:
b99bd4ef 2987
c19d1205
ZW
2988 (LSL|LSR|ASL|ASR|ROR) Rs
2989 (LSL|LSR|ASL|ASR|ROR) #imm
2990 RRX
b99bd4ef 2991
c19d1205
ZW
2992 Note that ASL is assimilated to LSL in the instruction encoding, and
2993 RRX to ROR #0 (which cannot be written as such). */
b99bd4ef 2994
c19d1205
ZW
2995static int
2996parse_shift (char **str, int i, enum parse_shift_mode mode)
b99bd4ef 2997{
c19d1205
ZW
2998 const struct asm_shift_name *shift_name;
2999 enum shift_kind shift;
3000 char *s = *str;
3001 char *p = s;
3002 int reg;
b99bd4ef 3003
c19d1205
ZW
3004 for (p = *str; ISALPHA (*p); p++)
3005 ;
b99bd4ef 3006
c19d1205 3007 if (p == *str)
b99bd4ef 3008 {
c19d1205
ZW
3009 inst.error = _("shift expression expected");
3010 return FAIL;
b99bd4ef
NC
3011 }
3012
c19d1205
ZW
3013 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str);
3014
3015 if (shift_name == NULL)
b99bd4ef 3016 {
c19d1205
ZW
3017 inst.error = _("shift expression expected");
3018 return FAIL;
b99bd4ef
NC
3019 }
3020
c19d1205 3021 shift = shift_name->kind;
b99bd4ef 3022
c19d1205
ZW
3023 switch (mode)
3024 {
3025 case NO_SHIFT_RESTRICT:
3026 case SHIFT_IMMEDIATE: break;
b99bd4ef 3027
c19d1205
ZW
3028 case SHIFT_LSL_OR_ASR_IMMEDIATE:
3029 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
3030 {
3031 inst.error = _("'LSL' or 'ASR' required");
3032 return FAIL;
3033 }
3034 break;
b99bd4ef 3035
c19d1205
ZW
3036 case SHIFT_LSL_IMMEDIATE:
3037 if (shift != SHIFT_LSL)
3038 {
3039 inst.error = _("'LSL' required");
3040 return FAIL;
3041 }
3042 break;
b99bd4ef 3043
c19d1205
ZW
3044 case SHIFT_ASR_IMMEDIATE:
3045 if (shift != SHIFT_ASR)
3046 {
3047 inst.error = _("'ASR' required");
3048 return FAIL;
3049 }
3050 break;
b99bd4ef 3051
c19d1205
ZW
3052 default: abort ();
3053 }
b99bd4ef 3054
c19d1205
ZW
3055 if (shift != SHIFT_RRX)
3056 {
3057 /* Whitespace can appear here if the next thing is a bare digit. */
3058 skip_whitespace (p);
b99bd4ef 3059
c19d1205
ZW
3060 if (mode == NO_SHIFT_RESTRICT
3061 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3062 {
3063 inst.operands[i].imm = reg;
3064 inst.operands[i].immisreg = 1;
3065 }
3066 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3067 return FAIL;
3068 }
3069 inst.operands[i].shift_kind = shift;
3070 inst.operands[i].shifted = 1;
3071 *str = p;
3072 return SUCCESS;
b99bd4ef
NC
3073}
3074
c19d1205 3075/* Parse a <shifter_operand> for an ARM data processing instruction:
b99bd4ef 3076
c19d1205
ZW
3077 #<immediate>
3078 #<immediate>, <rotate>
3079 <Rm>
3080 <Rm>, <shift>
b99bd4ef 3081
c19d1205
ZW
3082 where <shift> is defined by parse_shift above, and <rotate> is a
3083 multiple of 2 between 0 and 30. Validation of immediate operands
55cf6793 3084 is deferred to md_apply_fix. */
b99bd4ef 3085
c19d1205
ZW
3086static int
3087parse_shifter_operand (char **str, int i)
3088{
3089 int value;
3090 expressionS expr;
b99bd4ef 3091
c19d1205
ZW
3092 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
3093 {
3094 inst.operands[i].reg = value;
3095 inst.operands[i].isreg = 1;
b99bd4ef 3096
c19d1205
ZW
3097 /* parse_shift will override this if appropriate */
3098 inst.reloc.exp.X_op = O_constant;
3099 inst.reloc.exp.X_add_number = 0;
b99bd4ef 3100
c19d1205
ZW
3101 if (skip_past_comma (str) == FAIL)
3102 return SUCCESS;
b99bd4ef 3103
c19d1205
ZW
3104 /* Shift operation on register. */
3105 return parse_shift (str, i, NO_SHIFT_RESTRICT);
b99bd4ef
NC
3106 }
3107
c19d1205
ZW
3108 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
3109 return FAIL;
b99bd4ef 3110
c19d1205 3111 if (skip_past_comma (str) == SUCCESS)
b99bd4ef 3112 {
c19d1205
ZW
3113 /* #x, y -- ie explicit rotation by Y. */
3114 if (my_get_expression (&expr, str, GE_NO_PREFIX))
3115 return FAIL;
b99bd4ef 3116
c19d1205
ZW
3117 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
3118 {
3119 inst.error = _("constant expression expected");
3120 return FAIL;
3121 }
b99bd4ef 3122
c19d1205
ZW
3123 value = expr.X_add_number;
3124 if (value < 0 || value > 30 || value % 2 != 0)
3125 {
3126 inst.error = _("invalid rotation");
3127 return FAIL;
3128 }
3129 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
3130 {
3131 inst.error = _("invalid constant");
3132 return FAIL;
3133 }
09d92015 3134
55cf6793 3135 /* Convert to decoded value. md_apply_fix will put it back. */
c19d1205
ZW
3136 inst.reloc.exp.X_add_number
3137 = (((inst.reloc.exp.X_add_number << (32 - value))
3138 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
09d92015
MM
3139 }
3140
c19d1205
ZW
3141 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
3142 inst.reloc.pc_rel = 0;
3143 return SUCCESS;
09d92015
MM
3144}
3145
c19d1205
ZW
3146/* Parse all forms of an ARM address expression. Information is written
3147 to inst.operands[i] and/or inst.reloc.
09d92015 3148
c19d1205 3149 Preindexed addressing (.preind=1):
09d92015 3150
c19d1205
ZW
3151 [Rn, #offset] .reg=Rn .reloc.exp=offset
3152 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3153 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3154 .shift_kind=shift .reloc.exp=shift_imm
09d92015 3155
c19d1205 3156 These three may have a trailing ! which causes .writeback to be set also.
09d92015 3157
c19d1205 3158 Postindexed addressing (.postind=1, .writeback=1):
09d92015 3159
c19d1205
ZW
3160 [Rn], #offset .reg=Rn .reloc.exp=offset
3161 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3162 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3163 .shift_kind=shift .reloc.exp=shift_imm
09d92015 3164
c19d1205 3165 Unindexed addressing (.preind=0, .postind=0):
09d92015 3166
c19d1205 3167 [Rn], {option} .reg=Rn .imm=option .immisreg=0
09d92015 3168
c19d1205 3169 Other:
09d92015 3170
c19d1205
ZW
3171 [Rn]{!} shorthand for [Rn,#0]{!}
3172 =immediate .isreg=0 .reloc.exp=immediate
3173 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
09d92015 3174
c19d1205
ZW
3175 It is the caller's responsibility to check for addressing modes not
3176 supported by the instruction, and to set inst.reloc.type. */
3177
3178static int
3179parse_address (char **str, int i)
09d92015 3180{
c19d1205
ZW
3181 char *p = *str;
3182 int reg;
09d92015 3183
c19d1205 3184 if (skip_past_char (&p, '[') == FAIL)
09d92015 3185 {
c19d1205
ZW
3186 if (skip_past_char (&p, '=') == FAIL)
3187 {
3188 /* bare address - translate to PC-relative offset */
3189 inst.reloc.pc_rel = 1;
3190 inst.operands[i].reg = REG_PC;
3191 inst.operands[i].isreg = 1;
3192 inst.operands[i].preind = 1;
3193 }
3194 /* else a load-constant pseudo op, no special treatment needed here */
09d92015 3195
c19d1205
ZW
3196 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
3197 return FAIL;
09d92015 3198
c19d1205
ZW
3199 *str = p;
3200 return SUCCESS;
09d92015
MM
3201 }
3202
c19d1205 3203 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
09d92015 3204 {
c19d1205
ZW
3205 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3206 return FAIL;
09d92015 3207 }
c19d1205
ZW
3208 inst.operands[i].reg = reg;
3209 inst.operands[i].isreg = 1;
09d92015 3210
c19d1205 3211 if (skip_past_comma (&p) == SUCCESS)
09d92015 3212 {
c19d1205 3213 inst.operands[i].preind = 1;
09d92015 3214
c19d1205
ZW
3215 if (*p == '+') p++;
3216 else if (*p == '-') p++, inst.operands[i].negative = 1;
3217
3218 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
09d92015 3219 {
c19d1205
ZW
3220 inst.operands[i].imm = reg;
3221 inst.operands[i].immisreg = 1;
3222
3223 if (skip_past_comma (&p) == SUCCESS)
3224 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3225 return FAIL;
3226 }
3227 else
3228 {
3229 if (inst.operands[i].negative)
3230 {
3231 inst.operands[i].negative = 0;
3232 p--;
3233 }
3234 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3235 return FAIL;
09d92015
MM
3236 }
3237 }
3238
c19d1205 3239 if (skip_past_char (&p, ']') == FAIL)
09d92015 3240 {
c19d1205
ZW
3241 inst.error = _("']' expected");
3242 return FAIL;
09d92015
MM
3243 }
3244
c19d1205
ZW
3245 if (skip_past_char (&p, '!') == SUCCESS)
3246 inst.operands[i].writeback = 1;
09d92015 3247
c19d1205 3248 else if (skip_past_comma (&p) == SUCCESS)
09d92015 3249 {
c19d1205
ZW
3250 if (skip_past_char (&p, '{') == SUCCESS)
3251 {
3252 /* [Rn], {expr} - unindexed, with option */
3253 if (parse_immediate (&p, &inst.operands[i].imm,
ca3f61f7 3254 0, 255, TRUE) == FAIL)
c19d1205 3255 return FAIL;
09d92015 3256
c19d1205
ZW
3257 if (skip_past_char (&p, '}') == FAIL)
3258 {
3259 inst.error = _("'}' expected at end of 'option' field");
3260 return FAIL;
3261 }
3262 if (inst.operands[i].preind)
3263 {
3264 inst.error = _("cannot combine index with option");
3265 return FAIL;
3266 }
3267 *str = p;
3268 return SUCCESS;
09d92015 3269 }
c19d1205
ZW
3270 else
3271 {
3272 inst.operands[i].postind = 1;
3273 inst.operands[i].writeback = 1;
09d92015 3274
c19d1205
ZW
3275 if (inst.operands[i].preind)
3276 {
3277 inst.error = _("cannot combine pre- and post-indexing");
3278 return FAIL;
3279 }
09d92015 3280
c19d1205
ZW
3281 if (*p == '+') p++;
3282 else if (*p == '-') p++, inst.operands[i].negative = 1;
a737bd4d 3283
c19d1205
ZW
3284 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3285 {
3286 inst.operands[i].imm = reg;
3287 inst.operands[i].immisreg = 1;
a737bd4d 3288
c19d1205
ZW
3289 if (skip_past_comma (&p) == SUCCESS)
3290 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3291 return FAIL;
3292 }
3293 else
3294 {
3295 if (inst.operands[i].negative)
3296 {
3297 inst.operands[i].negative = 0;
3298 p--;
3299 }
3300 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3301 return FAIL;
3302 }
3303 }
a737bd4d
NC
3304 }
3305
c19d1205
ZW
3306 /* If at this point neither .preind nor .postind is set, we have a
3307 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
3308 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
3309 {
3310 inst.operands[i].preind = 1;
3311 inst.reloc.exp.X_op = O_constant;
3312 inst.reloc.exp.X_add_number = 0;
3313 }
3314 *str = p;
3315 return SUCCESS;
a737bd4d
NC
3316}
3317
c19d1205 3318/* Miscellaneous. */
a737bd4d 3319
c19d1205
ZW
3320/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
3321 or a bitmask suitable to be or-ed into the ARM msr instruction. */
3322static int
3323parse_psr (char **str)
09d92015 3324{
c19d1205
ZW
3325 char *p;
3326 unsigned long psr_field;
09d92015 3327
c19d1205
ZW
3328 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
3329 feature for ease of use and backwards compatibility. */
3330 p = *str;
3331 if (*p == 's' || *p == 'S')
3332 psr_field = SPSR_BIT;
3333 else if (*p == 'c' || *p == 'C')
3334 psr_field = 0;
3335 else
3336 goto error;
09d92015 3337
c19d1205
ZW
3338 p++;
3339 if (strncasecmp (p, "PSR", 3) != 0)
3340 goto error;
3341 p += 3;
09d92015 3342
c19d1205
ZW
3343 if (*p == '_')
3344 {
3345 /* A suffix follows. */
3346 const struct asm_psr *psr;
3347 char *start;
a737bd4d 3348
c19d1205
ZW
3349 p++;
3350 start = p;
a737bd4d 3351
c19d1205
ZW
3352 do
3353 p++;
3354 while (ISALNUM (*p) || *p == '_');
a737bd4d 3355
c19d1205
ZW
3356 psr = hash_find_n (arm_psr_hsh, start, p - start);
3357 if (!psr)
3358 goto error;
a737bd4d 3359
c19d1205 3360 psr_field |= psr->field;
a737bd4d 3361 }
c19d1205 3362 else
a737bd4d 3363 {
c19d1205
ZW
3364 if (ISALNUM (*p))
3365 goto error; /* Garbage after "[CS]PSR". */
3366
3367 psr_field |= (PSR_c | PSR_f);
a737bd4d 3368 }
c19d1205
ZW
3369 *str = p;
3370 return psr_field;
a737bd4d 3371
c19d1205
ZW
3372 error:
3373 inst.error = _("flag for {c}psr instruction expected");
3374 return FAIL;
a737bd4d
NC
3375}
3376
c19d1205
ZW
3377/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
3378 value suitable for splatting into the AIF field of the instruction. */
a737bd4d 3379
c19d1205
ZW
3380static int
3381parse_cps_flags (char **str)
a737bd4d 3382{
c19d1205
ZW
3383 int val = 0;
3384 int saw_a_flag = 0;
3385 char *s = *str;
a737bd4d 3386
c19d1205
ZW
3387 for (;;)
3388 switch (*s++)
3389 {
3390 case '\0': case ',':
3391 goto done;
a737bd4d 3392
c19d1205
ZW
3393 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
3394 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
3395 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
a737bd4d 3396
c19d1205
ZW
3397 default:
3398 inst.error = _("unrecognized CPS flag");
3399 return FAIL;
3400 }
a737bd4d 3401
c19d1205
ZW
3402 done:
3403 if (saw_a_flag == 0)
a737bd4d 3404 {
c19d1205
ZW
3405 inst.error = _("missing CPS flags");
3406 return FAIL;
a737bd4d 3407 }
a737bd4d 3408
c19d1205
ZW
3409 *str = s - 1;
3410 return val;
a737bd4d
NC
3411}
3412
c19d1205
ZW
3413/* Parse an endian specifier ("BE" or "LE", case insensitive);
3414 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
a737bd4d
NC
3415
3416static int
c19d1205 3417parse_endian_specifier (char **str)
a737bd4d 3418{
c19d1205
ZW
3419 int little_endian;
3420 char *s = *str;
a737bd4d 3421
c19d1205
ZW
3422 if (strncasecmp (s, "BE", 2))
3423 little_endian = 0;
3424 else if (strncasecmp (s, "LE", 2))
3425 little_endian = 1;
3426 else
a737bd4d 3427 {
c19d1205 3428 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC
3429 return FAIL;
3430 }
3431
c19d1205 3432 if (ISALNUM (s[2]) || s[2] == '_')
a737bd4d 3433 {
c19d1205 3434 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC
3435 return FAIL;
3436 }
3437
c19d1205
ZW
3438 *str = s + 2;
3439 return little_endian;
3440}
a737bd4d 3441
c19d1205
ZW
3442/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
3443 value suitable for poking into the rotate field of an sxt or sxta
3444 instruction, or FAIL on error. */
3445
3446static int
3447parse_ror (char **str)
3448{
3449 int rot;
3450 char *s = *str;
3451
3452 if (strncasecmp (s, "ROR", 3) == 0)
3453 s += 3;
3454 else
a737bd4d 3455 {
c19d1205 3456 inst.error = _("missing rotation field after comma");
a737bd4d
NC
3457 return FAIL;
3458 }
c19d1205
ZW
3459
3460 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
3461 return FAIL;
3462
3463 switch (rot)
a737bd4d 3464 {
c19d1205
ZW
3465 case 0: *str = s; return 0x0;
3466 case 8: *str = s; return 0x1;
3467 case 16: *str = s; return 0x2;
3468 case 24: *str = s; return 0x3;
3469
3470 default:
3471 inst.error = _("rotation can only be 0, 8, 16, or 24");
a737bd4d
NC
3472 return FAIL;
3473 }
c19d1205 3474}
a737bd4d 3475
c19d1205
ZW
3476/* Parse a conditional code (from conds[] below). The value returned is in the
3477 range 0 .. 14, or FAIL. */
3478static int
3479parse_cond (char **str)
3480{
3481 char *p, *q;
3482 const struct asm_cond *c;
a737bd4d 3483
c19d1205
ZW
3484 p = q = *str;
3485 while (ISALPHA (*q))
3486 q++;
a737bd4d 3487
c19d1205
ZW
3488 c = hash_find_n (arm_cond_hsh, p, q - p);
3489 if (!c)
a737bd4d 3490 {
c19d1205 3491 inst.error = _("condition required");
a737bd4d
NC
3492 return FAIL;
3493 }
3494
c19d1205
ZW
3495 *str = q;
3496 return c->value;
3497}
3498
92e90b6e
PB
3499/* Parse the operands of a table branch instruction. Similar to a memory
3500 operand. */
3501static int
3502parse_tb (char **str)
3503{
3504 char * p = *str;
3505 int reg;
3506
3507 if (skip_past_char (&p, '[') == FAIL)
3508 return FAIL;
3509
3510 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3511 {
3512 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3513 return FAIL;
3514 }
3515 inst.operands[0].reg = reg;
3516
3517 if (skip_past_comma (&p) == FAIL)
3518 return FAIL;
3519
3520 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3521 {
3522 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3523 return FAIL;
3524 }
3525 inst.operands[0].imm = reg;
3526
3527 if (skip_past_comma (&p) == SUCCESS)
3528 {
3529 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
3530 return FAIL;
3531 if (inst.reloc.exp.X_add_number != 1)
3532 {
3533 inst.error = _("invalid shift");
3534 return FAIL;
3535 }
3536 inst.operands[0].shifted = 1;
3537 }
3538
3539 if (skip_past_char (&p, ']') == FAIL)
3540 {
3541 inst.error = _("']' expected");
3542 return FAIL;
3543 }
3544 *str = p;
3545 return SUCCESS;
3546}
3547
c19d1205
ZW
3548/* Matcher codes for parse_operands. */
3549enum operand_parse_code
3550{
3551 OP_stop, /* end of line */
3552
3553 OP_RR, /* ARM register */
3554 OP_RRnpc, /* ARM register, not r15 */
3555 OP_RRnpcb, /* ARM register, not r15, in square brackets */
3556 OP_RRw, /* ARM register, not r15, optional trailing ! */
3557 OP_RCP, /* Coprocessor number */
3558 OP_RCN, /* Coprocessor register */
3559 OP_RF, /* FPA register */
3560 OP_RVS, /* VFP single precision register */
3561 OP_RVD, /* VFP double precision register */
3562 OP_RVC, /* VFP control register */
3563 OP_RMF, /* Maverick F register */
3564 OP_RMD, /* Maverick D register */
3565 OP_RMFX, /* Maverick FX register */
3566 OP_RMDX, /* Maverick DX register */
3567 OP_RMAX, /* Maverick AX register */
3568 OP_RMDS, /* Maverick DSPSC register */
3569 OP_RIWR, /* iWMMXt wR register */
3570 OP_RIWC, /* iWMMXt wC register */
3571 OP_RIWG, /* iWMMXt wCG register */
3572 OP_RXA, /* XScale accumulator register */
3573
3574 OP_REGLST, /* ARM register list */
3575 OP_VRSLST, /* VFP single-precision register list */
3576 OP_VRDLST, /* VFP double-precision register list */
3577
3578 OP_I7, /* immediate value 0 .. 7 */
3579 OP_I15, /* 0 .. 15 */
3580 OP_I16, /* 1 .. 16 */
3581 OP_I31, /* 0 .. 31 */
3582 OP_I31w, /* 0 .. 31, optional trailing ! */
3583 OP_I32, /* 1 .. 32 */
3584 OP_I63s, /* -64 .. 63 */
3585 OP_I255, /* 0 .. 255 */
3586 OP_Iffff, /* 0 .. 65535 */
3587
3588 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
3589 OP_I7b, /* 0 .. 7 */
3590 OP_I15b, /* 0 .. 15 */
3591 OP_I31b, /* 0 .. 31 */
3592
3593 OP_SH, /* shifter operand */
3594 OP_ADDR, /* Memory address expression (any mode) */
3595 OP_EXP, /* arbitrary expression */
3596 OP_EXPi, /* same, with optional immediate prefix */
3597 OP_EXPr, /* same, with optional relocation suffix */
3598
3599 OP_CPSF, /* CPS flags */
3600 OP_ENDI, /* Endianness specifier */
3601 OP_PSR, /* CPSR/SPSR mask for msr */
3602 OP_COND, /* conditional code */
92e90b6e 3603 OP_TB, /* Table branch. */
c19d1205
ZW
3604
3605 OP_RRnpc_I0, /* ARM register or literal 0 */
3606 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
3607 OP_RR_EXi, /* ARM register or expression with imm prefix */
3608 OP_RF_IF, /* FPA register or immediate */
3609 OP_RIWR_RIWC, /* iWMMXt R or C reg */
3610
3611 /* Optional operands. */
3612 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
3613 OP_oI31b, /* 0 .. 31 */
3614 OP_oIffffb, /* 0 .. 65535 */
3615 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
3616
3617 OP_oRR, /* ARM register */
3618 OP_oRRnpc, /* ARM register, not the PC */
3619 OP_oSHll, /* LSL immediate */
3620 OP_oSHar, /* ASR immediate */
3621 OP_oSHllar, /* LSL or ASR immediate */
3622 OP_oROR, /* ROR 0/8/16/24 */
3623
3624 OP_FIRST_OPTIONAL = OP_oI7b
3625};
a737bd4d 3626
c19d1205
ZW
3627/* Generic instruction operand parser. This does no encoding and no
3628 semantic validation; it merely squirrels values away in the inst
3629 structure. Returns SUCCESS or FAIL depending on whether the
3630 specified grammar matched. */
3631static int
ca3f61f7 3632parse_operands (char *str, const unsigned char *pattern)
c19d1205
ZW
3633{
3634 unsigned const char *upat = pattern;
3635 char *backtrack_pos = 0;
3636 const char *backtrack_error = 0;
3637 int i, val, backtrack_index = 0;
3638
3639#define po_char_or_fail(chr) do { \
3640 if (skip_past_char (&str, chr) == FAIL) \
3641 goto bad_args; \
3642} while (0)
3643
3644#define po_reg_or_fail(regtype) do { \
3645 val = arm_reg_parse (&str, regtype); \
3646 if (val == FAIL) \
3647 { \
3648 inst.error = _(reg_expected_msgs[regtype]); \
3649 goto failure; \
3650 } \
3651 inst.operands[i].reg = val; \
3652 inst.operands[i].isreg = 1; \
3653} while (0)
3654
3655#define po_reg_or_goto(regtype, label) do { \
3656 val = arm_reg_parse (&str, regtype); \
3657 if (val == FAIL) \
3658 goto label; \
3659 \
3660 inst.operands[i].reg = val; \
3661 inst.operands[i].isreg = 1; \
3662} while (0)
3663
3664#define po_imm_or_fail(min, max, popt) do { \
3665 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
3666 goto failure; \
3667 inst.operands[i].imm = val; \
3668} while (0)
3669
3670#define po_misc_or_fail(expr) do { \
3671 if (expr) \
3672 goto failure; \
3673} while (0)
3674
3675 skip_whitespace (str);
3676
3677 for (i = 0; upat[i] != OP_stop; i++)
3678 {
3679 if (upat[i] >= OP_FIRST_OPTIONAL)
3680 {
3681 /* Remember where we are in case we need to backtrack. */
3682 assert (!backtrack_pos);
3683 backtrack_pos = str;
3684 backtrack_error = inst.error;
3685 backtrack_index = i;
3686 }
3687
3688 if (i > 0)
3689 po_char_or_fail (',');
3690
3691 switch (upat[i])
3692 {
3693 /* Registers */
3694 case OP_oRRnpc:
3695 case OP_RRnpc:
3696 case OP_oRR:
3697 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
3698 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
3699 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
3700 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
3701 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
3702 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
3703 case OP_RVC: po_reg_or_fail (REG_TYPE_VFC); break;
3704 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
3705 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
3706 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
3707 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
3708 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
3709 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
3710 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
3711 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
3712 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
3713 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
3714
3715 case OP_RRnpcb:
3716 po_char_or_fail ('[');
3717 po_reg_or_fail (REG_TYPE_RN);
3718 po_char_or_fail (']');
3719 break;
a737bd4d 3720
c19d1205
ZW
3721 case OP_RRw:
3722 po_reg_or_fail (REG_TYPE_RN);
3723 if (skip_past_char (&str, '!') == SUCCESS)
3724 inst.operands[i].writeback = 1;
3725 break;
3726
3727 /* Immediates */
3728 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
3729 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
3730 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
3731 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
3732 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
3733 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
3734 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
3735 case OP_Iffff: po_imm_or_fail ( 0, 0xffff, FALSE); break;
3736
3737 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
3738 case OP_oI7b:
3739 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
3740 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
3741 case OP_oI31b:
3742 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
3743 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
3744
3745 /* Immediate variants */
3746 case OP_oI255c:
3747 po_char_or_fail ('{');
3748 po_imm_or_fail (0, 255, TRUE);
3749 po_char_or_fail ('}');
3750 break;
3751
3752 case OP_I31w:
3753 /* The expression parser chokes on a trailing !, so we have
3754 to find it first and zap it. */
3755 {
3756 char *s = str;
3757 while (*s && *s != ',')
3758 s++;
3759 if (s[-1] == '!')
3760 {
3761 s[-1] = '\0';
3762 inst.operands[i].writeback = 1;
3763 }
3764 po_imm_or_fail (0, 31, TRUE);
3765 if (str == s - 1)
3766 str = s;
3767 }
3768 break;
3769
3770 /* Expressions */
3771 case OP_EXPi: EXPi:
3772 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3773 GE_OPT_PREFIX));
3774 break;
3775
3776 case OP_EXP:
3777 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3778 GE_NO_PREFIX));
3779 break;
3780
3781 case OP_EXPr: EXPr:
3782 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3783 GE_NO_PREFIX));
3784 if (inst.reloc.exp.X_op == O_symbol)
a737bd4d 3785 {
c19d1205
ZW
3786 val = parse_reloc (&str);
3787 if (val == -1)
3788 {
3789 inst.error = _("unrecognized relocation suffix");
3790 goto failure;
3791 }
3792 else if (val != BFD_RELOC_UNUSED)
3793 {
3794 inst.operands[i].imm = val;
3795 inst.operands[i].hasreloc = 1;
3796 }
a737bd4d 3797 }
c19d1205 3798 break;
a737bd4d 3799
c19d1205
ZW
3800 /* Register or expression */
3801 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
3802 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
a737bd4d 3803
c19d1205
ZW
3804 /* Register or immediate */
3805 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
3806 I0: po_imm_or_fail (0, 0, FALSE); break;
a737bd4d 3807
c19d1205
ZW
3808 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
3809 IF:
3810 if (!is_immediate_prefix (*str))
3811 goto bad_args;
3812 str++;
3813 val = parse_fpa_immediate (&str);
3814 if (val == FAIL)
3815 goto failure;
3816 /* FPA immediates are encoded as registers 8-15.
3817 parse_fpa_immediate has already applied the offset. */
3818 inst.operands[i].reg = val;
3819 inst.operands[i].isreg = 1;
3820 break;
09d92015 3821
c19d1205
ZW
3822 /* Two kinds of register */
3823 case OP_RIWR_RIWC:
3824 {
3825 struct reg_entry *rege = arm_reg_parse_multi (&str);
3826 if (rege->type != REG_TYPE_MMXWR
3827 && rege->type != REG_TYPE_MMXWC
3828 && rege->type != REG_TYPE_MMXWCG)
3829 {
3830 inst.error = _("iWMMXt data or control register expected");
3831 goto failure;
3832 }
3833 inst.operands[i].reg = rege->number;
3834 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
3835 }
3836 break;
09d92015 3837
c19d1205
ZW
3838 /* Misc */
3839 case OP_CPSF: val = parse_cps_flags (&str); break;
3840 case OP_ENDI: val = parse_endian_specifier (&str); break;
3841 case OP_oROR: val = parse_ror (&str); break;
3842 case OP_PSR: val = parse_psr (&str); break;
3843 case OP_COND: val = parse_cond (&str); break;
3844
92e90b6e
PB
3845 case OP_TB:
3846 po_misc_or_fail (parse_tb (&str));
3847 break;
3848
c19d1205
ZW
3849 /* Register lists */
3850 case OP_REGLST:
3851 val = parse_reg_list (&str);
3852 if (*str == '^')
3853 {
3854 inst.operands[1].writeback = 1;
3855 str++;
3856 }
3857 break;
09d92015 3858
c19d1205
ZW
3859 case OP_VRSLST:
3860 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 0);
3861 break;
09d92015 3862
c19d1205
ZW
3863 case OP_VRDLST:
3864 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 1);
3865 break;
a737bd4d 3866
c19d1205
ZW
3867 /* Addressing modes */
3868 case OP_ADDR:
3869 po_misc_or_fail (parse_address (&str, i));
3870 break;
09d92015 3871
c19d1205
ZW
3872 case OP_SH:
3873 po_misc_or_fail (parse_shifter_operand (&str, i));
3874 break;
09d92015 3875
c19d1205
ZW
3876 case OP_oSHll:
3877 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
3878 break;
09d92015 3879
c19d1205
ZW
3880 case OP_oSHar:
3881 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
3882 break;
09d92015 3883
c19d1205
ZW
3884 case OP_oSHllar:
3885 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
3886 break;
09d92015 3887
c19d1205
ZW
3888 default:
3889 as_fatal ("unhandled operand code %d", upat[i]);
3890 }
09d92015 3891
c19d1205
ZW
3892 /* Various value-based sanity checks and shared operations. We
3893 do not signal immediate failures for the register constraints;
3894 this allows a syntax error to take precedence. */
3895 switch (upat[i])
3896 {
3897 case OP_oRRnpc:
3898 case OP_RRnpc:
3899 case OP_RRnpcb:
3900 case OP_RRw:
3901 case OP_RRnpc_I0:
3902 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
3903 inst.error = BAD_PC;
3904 break;
09d92015 3905
c19d1205
ZW
3906 case OP_CPSF:
3907 case OP_ENDI:
3908 case OP_oROR:
3909 case OP_PSR:
3910 case OP_COND:
3911 case OP_REGLST:
3912 case OP_VRSLST:
3913 case OP_VRDLST:
3914 if (val == FAIL)
3915 goto failure;
3916 inst.operands[i].imm = val;
3917 break;
a737bd4d 3918
c19d1205
ZW
3919 default:
3920 break;
3921 }
09d92015 3922
c19d1205
ZW
3923 /* If we get here, this operand was successfully parsed. */
3924 inst.operands[i].present = 1;
3925 continue;
09d92015 3926
c19d1205 3927 bad_args:
09d92015 3928 inst.error = BAD_ARGS;
c19d1205
ZW
3929
3930 failure:
3931 if (!backtrack_pos)
3932 return FAIL;
3933
3934 /* Do not backtrack over a trailing optional argument that
3935 absorbed some text. We will only fail again, with the
3936 'garbage following instruction' error message, which is
3937 probably less helpful than the current one. */
3938 if (backtrack_index == i && backtrack_pos != str
3939 && upat[i+1] == OP_stop)
3940 return FAIL;
3941
3942 /* Try again, skipping the optional argument at backtrack_pos. */
3943 str = backtrack_pos;
3944 inst.error = backtrack_error;
3945 inst.operands[backtrack_index].present = 0;
3946 i = backtrack_index;
3947 backtrack_pos = 0;
09d92015 3948 }
09d92015 3949
c19d1205
ZW
3950 /* Check that we have parsed all the arguments. */
3951 if (*str != '\0' && !inst.error)
3952 inst.error = _("garbage following instruction");
09d92015 3953
c19d1205 3954 return inst.error ? FAIL : SUCCESS;
09d92015
MM
3955}
3956
c19d1205
ZW
3957#undef po_char_or_fail
3958#undef po_reg_or_fail
3959#undef po_reg_or_goto
3960#undef po_imm_or_fail
3961\f
3962/* Shorthand macro for instruction encoding functions issuing errors. */
3963#define constraint(expr, err) do { \
3964 if (expr) \
3965 { \
3966 inst.error = err; \
3967 return; \
3968 } \
3969} while (0)
3970
3971/* Functions for operand encoding. ARM, then Thumb. */
3972
3973#define rotate_left(v, n) (v << n | v >> (32 - n))
3974
3975/* If VAL can be encoded in the immediate field of an ARM instruction,
3976 return the encoded form. Otherwise, return FAIL. */
3977
3978static unsigned int
3979encode_arm_immediate (unsigned int val)
09d92015 3980{
c19d1205
ZW
3981 unsigned int a, i;
3982
3983 for (i = 0; i < 32; i += 2)
3984 if ((a = rotate_left (val, i)) <= 0xff)
3985 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
3986
3987 return FAIL;
09d92015
MM
3988}
3989
c19d1205
ZW
3990/* If VAL can be encoded in the immediate field of a Thumb32 instruction,
3991 return the encoded form. Otherwise, return FAIL. */
3992static unsigned int
3993encode_thumb32_immediate (unsigned int val)
09d92015 3994{
c19d1205 3995 unsigned int a, i;
09d92015 3996
9c3c69f2 3997 if (val <= 0xff)
c19d1205 3998 return val;
a737bd4d 3999
9c3c69f2 4000 for (i = 1; i <= 24; i++)
09d92015 4001 {
9c3c69f2
PB
4002 a = val >> i;
4003 if ((val & ~(0xff << i)) == 0)
4004 return ((val >> i) & 0x7f) | ((32 - i) << 7);
09d92015 4005 }
a737bd4d 4006
c19d1205
ZW
4007 a = val & 0xff;
4008 if (val == ((a << 16) | a))
4009 return 0x100 | a;
4010 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
4011 return 0x300 | a;
09d92015 4012
c19d1205
ZW
4013 a = val & 0xff00;
4014 if (val == ((a << 16) | a))
4015 return 0x200 | (a >> 8);
a737bd4d 4016
c19d1205 4017 return FAIL;
09d92015 4018}
c19d1205 4019/* Encode a VFP SP register number into inst.instruction. */
09d92015
MM
4020
4021static void
c19d1205 4022encode_arm_vfp_sp_reg (int reg, enum vfp_sp_reg_pos pos)
09d92015 4023{
c19d1205 4024 switch (pos)
09d92015 4025 {
c19d1205
ZW
4026 case VFP_REG_Sd:
4027 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
4028 break;
4029
4030 case VFP_REG_Sn:
4031 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
4032 break;
4033
4034 case VFP_REG_Sm:
4035 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
4036 break;
4037
4038 default:
4039 abort ();
09d92015 4040 }
09d92015
MM
4041}
4042
c19d1205 4043/* Encode a <shift> in an ARM-format instruction. The immediate,
55cf6793 4044 if any, is handled by md_apply_fix. */
09d92015 4045static void
c19d1205 4046encode_arm_shift (int i)
09d92015 4047{
c19d1205
ZW
4048 if (inst.operands[i].shift_kind == SHIFT_RRX)
4049 inst.instruction |= SHIFT_ROR << 5;
4050 else
09d92015 4051 {
c19d1205
ZW
4052 inst.instruction |= inst.operands[i].shift_kind << 5;
4053 if (inst.operands[i].immisreg)
4054 {
4055 inst.instruction |= SHIFT_BY_REG;
4056 inst.instruction |= inst.operands[i].imm << 8;
4057 }
4058 else
4059 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
09d92015 4060 }
c19d1205 4061}
09d92015 4062
c19d1205
ZW
4063static void
4064encode_arm_shifter_operand (int i)
4065{
4066 if (inst.operands[i].isreg)
09d92015 4067 {
c19d1205
ZW
4068 inst.instruction |= inst.operands[i].reg;
4069 encode_arm_shift (i);
09d92015 4070 }
c19d1205
ZW
4071 else
4072 inst.instruction |= INST_IMMEDIATE;
09d92015
MM
4073}
4074
c19d1205 4075/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
09d92015 4076static void
c19d1205 4077encode_arm_addr_mode_common (int i, bfd_boolean is_t)
09d92015 4078{
c19d1205
ZW
4079 assert (inst.operands[i].isreg);
4080 inst.instruction |= inst.operands[i].reg << 16;
a737bd4d 4081
c19d1205 4082 if (inst.operands[i].preind)
09d92015 4083 {
c19d1205
ZW
4084 if (is_t)
4085 {
4086 inst.error = _("instruction does not accept preindexed addressing");
4087 return;
4088 }
4089 inst.instruction |= PRE_INDEX;
4090 if (inst.operands[i].writeback)
4091 inst.instruction |= WRITE_BACK;
09d92015 4092
c19d1205
ZW
4093 }
4094 else if (inst.operands[i].postind)
4095 {
4096 assert (inst.operands[i].writeback);
4097 if (is_t)
4098 inst.instruction |= WRITE_BACK;
4099 }
4100 else /* unindexed - only for coprocessor */
09d92015 4101 {
c19d1205 4102 inst.error = _("instruction does not accept unindexed addressing");
09d92015
MM
4103 return;
4104 }
4105
c19d1205
ZW
4106 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
4107 && (((inst.instruction & 0x000f0000) >> 16)
4108 == ((inst.instruction & 0x0000f000) >> 12)))
4109 as_warn ((inst.instruction & LOAD_BIT)
4110 ? _("destination register same as write-back base")
4111 : _("source register same as write-back base"));
09d92015
MM
4112}
4113
c19d1205
ZW
4114/* inst.operands[i] was set up by parse_address. Encode it into an
4115 ARM-format mode 2 load or store instruction. If is_t is true,
4116 reject forms that cannot be used with a T instruction (i.e. not
4117 post-indexed). */
a737bd4d 4118static void
c19d1205 4119encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
09d92015 4120{
c19d1205 4121 encode_arm_addr_mode_common (i, is_t);
a737bd4d 4122
c19d1205 4123 if (inst.operands[i].immisreg)
09d92015 4124 {
c19d1205
ZW
4125 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
4126 inst.instruction |= inst.operands[i].imm;
4127 if (!inst.operands[i].negative)
4128 inst.instruction |= INDEX_UP;
4129 if (inst.operands[i].shifted)
4130 {
4131 if (inst.operands[i].shift_kind == SHIFT_RRX)
4132 inst.instruction |= SHIFT_ROR << 5;
4133 else
4134 {
4135 inst.instruction |= inst.operands[i].shift_kind << 5;
4136 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
4137 }
4138 }
09d92015 4139 }
c19d1205 4140 else /* immediate offset in inst.reloc */
09d92015 4141 {
c19d1205
ZW
4142 if (inst.reloc.type == BFD_RELOC_UNUSED)
4143 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
09d92015 4144 }
09d92015
MM
4145}
4146
c19d1205
ZW
4147/* inst.operands[i] was set up by parse_address. Encode it into an
4148 ARM-format mode 3 load or store instruction. Reject forms that
4149 cannot be used with such instructions. If is_t is true, reject
4150 forms that cannot be used with a T instruction (i.e. not
4151 post-indexed). */
4152static void
4153encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
09d92015 4154{
c19d1205 4155 if (inst.operands[i].immisreg && inst.operands[i].shifted)
09d92015 4156 {
c19d1205
ZW
4157 inst.error = _("instruction does not accept scaled register index");
4158 return;
09d92015 4159 }
a737bd4d 4160
c19d1205 4161 encode_arm_addr_mode_common (i, is_t);
a737bd4d 4162
c19d1205
ZW
4163 if (inst.operands[i].immisreg)
4164 {
4165 inst.instruction |= inst.operands[i].imm;
4166 if (!inst.operands[i].negative)
4167 inst.instruction |= INDEX_UP;
4168 }
4169 else /* immediate offset in inst.reloc */
4170 {
4171 inst.instruction |= HWOFFSET_IMM;
4172 if (inst.reloc.type == BFD_RELOC_UNUSED)
4173 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
c19d1205 4174 }
a737bd4d
NC
4175}
4176
c19d1205
ZW
4177/* inst.operands[i] was set up by parse_address. Encode it into an
4178 ARM-format instruction. Reject all forms which cannot be encoded
4179 into a coprocessor load/store instruction. If wb_ok is false,
4180 reject use of writeback; if unind_ok is false, reject use of
4181 unindexed addressing. If reloc_override is not 0, use it instead
4182 of BFD_ARM_CP_OFF_IMM. */
09d92015 4183
c19d1205
ZW
4184static int
4185encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
09d92015 4186{
c19d1205 4187 inst.instruction |= inst.operands[i].reg << 16;
a737bd4d 4188
c19d1205 4189 assert (!(inst.operands[i].preind && inst.operands[i].postind));
09d92015 4190
c19d1205 4191 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
09d92015 4192 {
c19d1205
ZW
4193 assert (!inst.operands[i].writeback);
4194 if (!unind_ok)
4195 {
4196 inst.error = _("instruction does not support unindexed addressing");
4197 return FAIL;
4198 }
4199 inst.instruction |= inst.operands[i].imm;
4200 inst.instruction |= INDEX_UP;
4201 return SUCCESS;
09d92015 4202 }
a737bd4d 4203
c19d1205
ZW
4204 if (inst.operands[i].preind)
4205 inst.instruction |= PRE_INDEX;
a737bd4d 4206
c19d1205 4207 if (inst.operands[i].writeback)
09d92015 4208 {
c19d1205
ZW
4209 if (inst.operands[i].reg == REG_PC)
4210 {
4211 inst.error = _("pc may not be used with write-back");
4212 return FAIL;
4213 }
4214 if (!wb_ok)
4215 {
4216 inst.error = _("instruction does not support writeback");
4217 return FAIL;
4218 }
4219 inst.instruction |= WRITE_BACK;
09d92015 4220 }
a737bd4d 4221
c19d1205
ZW
4222 if (reloc_override)
4223 inst.reloc.type = reloc_override;
8f06b2d8
PB
4224 else if (thumb_mode)
4225 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
09d92015 4226 else
c19d1205 4227 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
c19d1205
ZW
4228 return SUCCESS;
4229}
a737bd4d 4230
c19d1205
ZW
4231/* inst.reloc.exp describes an "=expr" load pseudo-operation.
4232 Determine whether it can be performed with a move instruction; if
4233 it can, convert inst.instruction to that move instruction and
4234 return 1; if it can't, convert inst.instruction to a literal-pool
4235 load and return 0. If this is not a valid thing to do in the
4236 current context, set inst.error and return 1.
a737bd4d 4237
c19d1205
ZW
4238 inst.operands[i] describes the destination register. */
4239
4240static int
4241move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
4242{
4243 if ((inst.instruction & (thumb_p ? THUMB_LOAD_BIT : LOAD_BIT)) == 0)
09d92015 4244 {
c19d1205
ZW
4245 inst.error = _("invalid pseudo operation");
4246 return 1;
09d92015 4247 }
c19d1205 4248 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
09d92015
MM
4249 {
4250 inst.error = _("constant expression expected");
c19d1205 4251 return 1;
09d92015 4252 }
c19d1205 4253 if (inst.reloc.exp.X_op == O_constant)
09d92015 4254 {
c19d1205
ZW
4255 if (thumb_p)
4256 {
4257 if ((inst.reloc.exp.X_add_number & ~0xFF) == 0)
4258 {
4259 /* This can be done with a mov(1) instruction. */
4260 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
4261 inst.instruction |= inst.reloc.exp.X_add_number;
4262 return 1;
4263 }
4264 }
4265 else
4266 {
4267 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
4268 if (value != FAIL)
4269 {
4270 /* This can be done with a mov instruction. */
4271 inst.instruction &= LITERAL_MASK;
4272 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
4273 inst.instruction |= value & 0xfff;
4274 return 1;
4275 }
09d92015 4276
c19d1205
ZW
4277 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
4278 if (value != FAIL)
4279 {
4280 /* This can be done with a mvn instruction. */
4281 inst.instruction &= LITERAL_MASK;
4282 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
4283 inst.instruction |= value & 0xfff;
4284 return 1;
4285 }
4286 }
09d92015
MM
4287 }
4288
c19d1205
ZW
4289 if (add_to_lit_pool () == FAIL)
4290 {
4291 inst.error = _("literal pool insertion failed");
4292 return 1;
4293 }
4294 inst.operands[1].reg = REG_PC;
4295 inst.operands[1].isreg = 1;
4296 inst.operands[1].preind = 1;
4297 inst.reloc.pc_rel = 1;
4298 inst.reloc.type = (thumb_p
4299 ? BFD_RELOC_ARM_THUMB_OFFSET
4300 : (mode_3
4301 ? BFD_RELOC_ARM_HWLITERAL
4302 : BFD_RELOC_ARM_LITERAL));
4303 return 0;
09d92015
MM
4304}
4305
c19d1205
ZW
4306/* Functions for instruction encoding, sorted by subarchitecture.
4307 First some generics; their names are taken from the conventional
4308 bit positions for register arguments in ARM format instructions. */
09d92015 4309
a737bd4d 4310static void
c19d1205 4311do_noargs (void)
09d92015 4312{
c19d1205 4313}
a737bd4d 4314
c19d1205
ZW
4315static void
4316do_rd (void)
4317{
4318 inst.instruction |= inst.operands[0].reg << 12;
4319}
a737bd4d 4320
c19d1205
ZW
4321static void
4322do_rd_rm (void)
4323{
4324 inst.instruction |= inst.operands[0].reg << 12;
4325 inst.instruction |= inst.operands[1].reg;
4326}
09d92015 4327
c19d1205
ZW
4328static void
4329do_rd_rn (void)
4330{
4331 inst.instruction |= inst.operands[0].reg << 12;
4332 inst.instruction |= inst.operands[1].reg << 16;
4333}
a737bd4d 4334
c19d1205
ZW
4335static void
4336do_rn_rd (void)
4337{
4338 inst.instruction |= inst.operands[0].reg << 16;
4339 inst.instruction |= inst.operands[1].reg << 12;
4340}
09d92015 4341
c19d1205
ZW
4342static void
4343do_rd_rm_rn (void)
4344{
9a64e435
PB
4345 unsigned Rn = inst.operands[2].reg;
4346 /* Enforce resutrictions on SWP instruction. */
4347 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
4348 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
4349 _("Rn must not overlap other operands"));
c19d1205
ZW
4350 inst.instruction |= inst.operands[0].reg << 12;
4351 inst.instruction |= inst.operands[1].reg;
9a64e435 4352 inst.instruction |= Rn << 16;
c19d1205 4353}
09d92015 4354
c19d1205
ZW
4355static void
4356do_rd_rn_rm (void)
4357{
4358 inst.instruction |= inst.operands[0].reg << 12;
4359 inst.instruction |= inst.operands[1].reg << 16;
4360 inst.instruction |= inst.operands[2].reg;
4361}
a737bd4d 4362
c19d1205
ZW
4363static void
4364do_rm_rd_rn (void)
4365{
4366 inst.instruction |= inst.operands[0].reg;
4367 inst.instruction |= inst.operands[1].reg << 12;
4368 inst.instruction |= inst.operands[2].reg << 16;
4369}
09d92015 4370
c19d1205
ZW
4371static void
4372do_imm0 (void)
4373{
4374 inst.instruction |= inst.operands[0].imm;
4375}
09d92015 4376
c19d1205
ZW
4377static void
4378do_rd_cpaddr (void)
4379{
4380 inst.instruction |= inst.operands[0].reg << 12;
4381 encode_arm_cp_address (1, TRUE, TRUE, 0);
09d92015 4382}
a737bd4d 4383
c19d1205
ZW
4384/* ARM instructions, in alphabetical order by function name (except
4385 that wrapper functions appear immediately after the function they
4386 wrap). */
09d92015 4387
c19d1205
ZW
4388/* This is a pseudo-op of the form "adr rd, label" to be converted
4389 into a relative address of the form "add rd, pc, #label-.-8". */
09d92015
MM
4390
4391static void
c19d1205 4392do_adr (void)
09d92015 4393{
c19d1205 4394 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 4395
c19d1205
ZW
4396 /* Frag hacking will turn this into a sub instruction if the offset turns
4397 out to be negative. */
4398 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
c19d1205 4399 inst.reloc.pc_rel = 1;
2fc8bdac 4400 inst.reloc.exp.X_add_number -= 8;
c19d1205 4401}
b99bd4ef 4402
c19d1205
ZW
4403/* This is a pseudo-op of the form "adrl rd, label" to be converted
4404 into a relative address of the form:
4405 add rd, pc, #low(label-.-8)"
4406 add rd, rd, #high(label-.-8)" */
b99bd4ef 4407
c19d1205
ZW
4408static void
4409do_adrl (void)
4410{
4411 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 4412
c19d1205
ZW
4413 /* Frag hacking will turn this into a sub instruction if the offset turns
4414 out to be negative. */
4415 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
c19d1205
ZW
4416 inst.reloc.pc_rel = 1;
4417 inst.size = INSN_SIZE * 2;
2fc8bdac 4418 inst.reloc.exp.X_add_number -= 8;
b99bd4ef
NC
4419}
4420
b99bd4ef 4421static void
c19d1205 4422do_arit (void)
b99bd4ef 4423{
c19d1205
ZW
4424 if (!inst.operands[1].present)
4425 inst.operands[1].reg = inst.operands[0].reg;
4426 inst.instruction |= inst.operands[0].reg << 12;
4427 inst.instruction |= inst.operands[1].reg << 16;
4428 encode_arm_shifter_operand (2);
4429}
b99bd4ef 4430
c19d1205
ZW
4431static void
4432do_bfc (void)
4433{
4434 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
4435 constraint (msb > 32, _("bit-field extends past end of register"));
4436 /* The instruction encoding stores the LSB and MSB,
4437 not the LSB and width. */
4438 inst.instruction |= inst.operands[0].reg << 12;
4439 inst.instruction |= inst.operands[1].imm << 7;
4440 inst.instruction |= (msb - 1) << 16;
4441}
b99bd4ef 4442
c19d1205
ZW
4443static void
4444do_bfi (void)
4445{
4446 unsigned int msb;
b99bd4ef 4447
c19d1205
ZW
4448 /* #0 in second position is alternative syntax for bfc, which is
4449 the same instruction but with REG_PC in the Rm field. */
4450 if (!inst.operands[1].isreg)
4451 inst.operands[1].reg = REG_PC;
b99bd4ef 4452
c19d1205
ZW
4453 msb = inst.operands[2].imm + inst.operands[3].imm;
4454 constraint (msb > 32, _("bit-field extends past end of register"));
4455 /* The instruction encoding stores the LSB and MSB,
4456 not the LSB and width. */
4457 inst.instruction |= inst.operands[0].reg << 12;
4458 inst.instruction |= inst.operands[1].reg;
4459 inst.instruction |= inst.operands[2].imm << 7;
4460 inst.instruction |= (msb - 1) << 16;
b99bd4ef
NC
4461}
4462
b99bd4ef 4463static void
c19d1205 4464do_bfx (void)
b99bd4ef 4465{
c19d1205
ZW
4466 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
4467 _("bit-field extends past end of register"));
4468 inst.instruction |= inst.operands[0].reg << 12;
4469 inst.instruction |= inst.operands[1].reg;
4470 inst.instruction |= inst.operands[2].imm << 7;
4471 inst.instruction |= (inst.operands[3].imm - 1) << 16;
4472}
09d92015 4473
c19d1205
ZW
4474/* ARM V5 breakpoint instruction (argument parse)
4475 BKPT <16 bit unsigned immediate>
4476 Instruction is not conditional.
4477 The bit pattern given in insns[] has the COND_ALWAYS condition,
4478 and it is an error if the caller tried to override that. */
b99bd4ef 4479
c19d1205
ZW
4480static void
4481do_bkpt (void)
4482{
4483 /* Top 12 of 16 bits to bits 19:8. */
4484 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
09d92015 4485
c19d1205
ZW
4486 /* Bottom 4 of 16 bits to bits 3:0. */
4487 inst.instruction |= inst.operands[0].imm & 0xf;
4488}
09d92015 4489
c19d1205
ZW
4490static void
4491encode_branch (int default_reloc)
4492{
4493 if (inst.operands[0].hasreloc)
4494 {
4495 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
4496 _("the only suffix valid here is '(plt)'"));
4497 inst.reloc.type = BFD_RELOC_ARM_PLT32;
c19d1205 4498 }
b99bd4ef 4499 else
c19d1205
ZW
4500 {
4501 inst.reloc.type = default_reloc;
c19d1205 4502 }
2fc8bdac 4503 inst.reloc.pc_rel = 1;
b99bd4ef
NC
4504}
4505
b99bd4ef 4506static void
c19d1205 4507do_branch (void)
b99bd4ef 4508{
c19d1205
ZW
4509 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
4510}
b99bd4ef 4511
c19d1205
ZW
4512/* ARM V5 branch-link-exchange instruction (argument parse)
4513 BLX <target_addr> ie BLX(1)
4514 BLX{<condition>} <Rm> ie BLX(2)
4515 Unfortunately, there are two different opcodes for this mnemonic.
4516 So, the insns[].value is not used, and the code here zaps values
4517 into inst.instruction.
4518 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
b99bd4ef 4519
c19d1205
ZW
4520static void
4521do_blx (void)
4522{
4523 if (inst.operands[0].isreg)
b99bd4ef 4524 {
c19d1205
ZW
4525 /* Arg is a register; the opcode provided by insns[] is correct.
4526 It is not illegal to do "blx pc", just useless. */
4527 if (inst.operands[0].reg == REG_PC)
4528 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
b99bd4ef 4529
c19d1205
ZW
4530 inst.instruction |= inst.operands[0].reg;
4531 }
4532 else
b99bd4ef 4533 {
c19d1205
ZW
4534 /* Arg is an address; this instruction cannot be executed
4535 conditionally, and the opcode must be adjusted. */
4536 constraint (inst.cond != COND_ALWAYS, BAD_COND);
2fc8bdac 4537 inst.instruction = 0xfa000000;
c19d1205 4538 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
b99bd4ef 4539 }
c19d1205
ZW
4540}
4541
4542static void
4543do_bx (void)
4544{
4545 if (inst.operands[0].reg == REG_PC)
4546 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
b99bd4ef 4547
c19d1205 4548 inst.instruction |= inst.operands[0].reg;
09d92015
MM
4549}
4550
c19d1205
ZW
4551
4552/* ARM v5TEJ. Jump to Jazelle code. */
a737bd4d
NC
4553
4554static void
c19d1205 4555do_bxj (void)
a737bd4d 4556{
c19d1205
ZW
4557 if (inst.operands[0].reg == REG_PC)
4558 as_tsktsk (_("use of r15 in bxj is not really useful"));
4559
4560 inst.instruction |= inst.operands[0].reg;
a737bd4d
NC
4561}
4562
c19d1205
ZW
4563/* Co-processor data operation:
4564 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
4565 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
4566static void
4567do_cdp (void)
4568{
4569 inst.instruction |= inst.operands[0].reg << 8;
4570 inst.instruction |= inst.operands[1].imm << 20;
4571 inst.instruction |= inst.operands[2].reg << 12;
4572 inst.instruction |= inst.operands[3].reg << 16;
4573 inst.instruction |= inst.operands[4].reg;
4574 inst.instruction |= inst.operands[5].imm << 5;
4575}
a737bd4d
NC
4576
4577static void
c19d1205 4578do_cmp (void)
a737bd4d 4579{
c19d1205
ZW
4580 inst.instruction |= inst.operands[0].reg << 16;
4581 encode_arm_shifter_operand (1);
a737bd4d
NC
4582}
4583
c19d1205
ZW
4584/* Transfer between coprocessor and ARM registers.
4585 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
4586 MRC2
4587 MCR{cond}
4588 MCR2
4589
4590 No special properties. */
09d92015
MM
4591
4592static void
c19d1205 4593do_co_reg (void)
09d92015 4594{
c19d1205
ZW
4595 inst.instruction |= inst.operands[0].reg << 8;
4596 inst.instruction |= inst.operands[1].imm << 21;
4597 inst.instruction |= inst.operands[2].reg << 12;
4598 inst.instruction |= inst.operands[3].reg << 16;
4599 inst.instruction |= inst.operands[4].reg;
4600 inst.instruction |= inst.operands[5].imm << 5;
4601}
09d92015 4602
c19d1205
ZW
4603/* Transfer between coprocessor register and pair of ARM registers.
4604 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
4605 MCRR2
4606 MRRC{cond}
4607 MRRC2
b99bd4ef 4608
c19d1205 4609 Two XScale instructions are special cases of these:
09d92015 4610
c19d1205
ZW
4611 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
4612 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
b99bd4ef 4613
c19d1205 4614 Result unpredicatable if Rd or Rn is R15. */
a737bd4d 4615
c19d1205
ZW
4616static void
4617do_co_reg2c (void)
4618{
4619 inst.instruction |= inst.operands[0].reg << 8;
4620 inst.instruction |= inst.operands[1].imm << 4;
4621 inst.instruction |= inst.operands[2].reg << 12;
4622 inst.instruction |= inst.operands[3].reg << 16;
4623 inst.instruction |= inst.operands[4].reg;
b99bd4ef
NC
4624}
4625
c19d1205
ZW
4626static void
4627do_cpsi (void)
4628{
4629 inst.instruction |= inst.operands[0].imm << 6;
4630 inst.instruction |= inst.operands[1].imm;
4631}
b99bd4ef
NC
4632
4633static void
c19d1205 4634do_it (void)
b99bd4ef 4635{
c19d1205
ZW
4636 /* There is no IT instruction in ARM mode. We
4637 process it but do not generate code for it. */
4638 inst.size = 0;
09d92015 4639}
b99bd4ef 4640
09d92015 4641static void
c19d1205 4642do_ldmstm (void)
ea6ef066 4643{
c19d1205
ZW
4644 int base_reg = inst.operands[0].reg;
4645 int range = inst.operands[1].imm;
ea6ef066 4646
c19d1205
ZW
4647 inst.instruction |= base_reg << 16;
4648 inst.instruction |= range;
ea6ef066 4649
c19d1205
ZW
4650 if (inst.operands[1].writeback)
4651 inst.instruction |= LDM_TYPE_2_OR_3;
09d92015 4652
c19d1205 4653 if (inst.operands[0].writeback)
ea6ef066 4654 {
c19d1205
ZW
4655 inst.instruction |= WRITE_BACK;
4656 /* Check for unpredictable uses of writeback. */
4657 if (inst.instruction & LOAD_BIT)
09d92015 4658 {
c19d1205
ZW
4659 /* Not allowed in LDM type 2. */
4660 if ((inst.instruction & LDM_TYPE_2_OR_3)
4661 && ((range & (1 << REG_PC)) == 0))
4662 as_warn (_("writeback of base register is UNPREDICTABLE"));
4663 /* Only allowed if base reg not in list for other types. */
4664 else if (range & (1 << base_reg))
4665 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
4666 }
4667 else /* STM. */
4668 {
4669 /* Not allowed for type 2. */
4670 if (inst.instruction & LDM_TYPE_2_OR_3)
4671 as_warn (_("writeback of base register is UNPREDICTABLE"));
4672 /* Only allowed if base reg not in list, or first in list. */
4673 else if ((range & (1 << base_reg))
4674 && (range & ((1 << base_reg) - 1)))
4675 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
09d92015 4676 }
ea6ef066 4677 }
a737bd4d
NC
4678}
4679
c19d1205
ZW
4680/* ARMv5TE load-consecutive (argument parse)
4681 Mode is like LDRH.
4682
4683 LDRccD R, mode
4684 STRccD R, mode. */
4685
a737bd4d 4686static void
c19d1205 4687do_ldrd (void)
a737bd4d 4688{
c19d1205
ZW
4689 constraint (inst.operands[0].reg % 2 != 0,
4690 _("first destination register must be even"));
4691 constraint (inst.operands[1].present
4692 && inst.operands[1].reg != inst.operands[0].reg + 1,
4693 _("can only load two consecutive registers"));
4694 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
4695 constraint (!inst.operands[2].isreg, _("'[' expected"));
a737bd4d 4696
c19d1205
ZW
4697 if (!inst.operands[1].present)
4698 inst.operands[1].reg = inst.operands[0].reg + 1;
4699
4700 if (inst.instruction & LOAD_BIT)
a737bd4d 4701 {
c19d1205
ZW
4702 /* encode_arm_addr_mode_3 will diagnose overlap between the base
4703 register and the first register written; we have to diagnose
4704 overlap between the base and the second register written here. */
ea6ef066 4705
c19d1205
ZW
4706 if (inst.operands[2].reg == inst.operands[1].reg
4707 && (inst.operands[2].writeback || inst.operands[2].postind))
4708 as_warn (_("base register written back, and overlaps "
4709 "second destination register"));
b05fe5cf 4710
c19d1205
ZW
4711 /* For an index-register load, the index register must not overlap the
4712 destination (even if not write-back). */
4713 else if (inst.operands[2].immisreg
ca3f61f7
NC
4714 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
4715 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
c19d1205 4716 as_warn (_("index register overlaps destination register"));
b05fe5cf 4717 }
c19d1205
ZW
4718
4719 inst.instruction |= inst.operands[0].reg << 12;
4720 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
b05fe5cf
ZW
4721}
4722
4723static void
c19d1205 4724do_ldrex (void)
b05fe5cf 4725{
c19d1205
ZW
4726 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
4727 || inst.operands[1].postind || inst.operands[1].writeback
4728 || inst.operands[1].immisreg || inst.operands[1].shifted
4729 || inst.operands[1].negative,
4730 _("instruction does not accept this addressing mode"));
b05fe5cf 4731
c19d1205 4732 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
b05fe5cf 4733
c19d1205
ZW
4734 constraint (inst.reloc.exp.X_op != O_constant
4735 || inst.reloc.exp.X_add_number != 0,
4736 _("offset must be zero in ARM encoding"));
b05fe5cf 4737
c19d1205
ZW
4738 inst.instruction |= inst.operands[0].reg << 12;
4739 inst.instruction |= inst.operands[1].reg << 16;
4740 inst.reloc.type = BFD_RELOC_UNUSED;
b05fe5cf
ZW
4741}
4742
4743static void
c19d1205 4744do_ldrexd (void)
b05fe5cf 4745{
c19d1205
ZW
4746 constraint (inst.operands[0].reg % 2 != 0,
4747 _("even register required"));
4748 constraint (inst.operands[1].present
4749 && inst.operands[1].reg != inst.operands[0].reg + 1,
4750 _("can only load two consecutive registers"));
4751 /* If op 1 were present and equal to PC, this function wouldn't
4752 have been called in the first place. */
4753 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
b05fe5cf 4754
c19d1205
ZW
4755 inst.instruction |= inst.operands[0].reg << 12;
4756 inst.instruction |= inst.operands[2].reg << 16;
b05fe5cf
ZW
4757}
4758
4759static void
c19d1205 4760do_ldst (void)
b05fe5cf 4761{
c19d1205
ZW
4762 inst.instruction |= inst.operands[0].reg << 12;
4763 if (!inst.operands[1].isreg)
4764 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
b05fe5cf 4765 return;
c19d1205 4766 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
b05fe5cf
ZW
4767}
4768
4769static void
c19d1205 4770do_ldstt (void)
b05fe5cf 4771{
c19d1205
ZW
4772 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4773 reject [Rn,...]. */
4774 if (inst.operands[1].preind)
b05fe5cf 4775 {
c19d1205
ZW
4776 constraint (inst.reloc.exp.X_op != O_constant ||
4777 inst.reloc.exp.X_add_number != 0,
4778 _("this instruction requires a post-indexed address"));
b05fe5cf 4779
c19d1205
ZW
4780 inst.operands[1].preind = 0;
4781 inst.operands[1].postind = 1;
4782 inst.operands[1].writeback = 1;
b05fe5cf 4783 }
c19d1205
ZW
4784 inst.instruction |= inst.operands[0].reg << 12;
4785 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
4786}
b05fe5cf 4787
c19d1205 4788/* Halfword and signed-byte load/store operations. */
b05fe5cf 4789
c19d1205
ZW
4790static void
4791do_ldstv4 (void)
4792{
4793 inst.instruction |= inst.operands[0].reg << 12;
4794 if (!inst.operands[1].isreg)
4795 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
b05fe5cf 4796 return;
c19d1205 4797 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
b05fe5cf
ZW
4798}
4799
4800static void
c19d1205 4801do_ldsttv4 (void)
b05fe5cf 4802{
c19d1205
ZW
4803 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4804 reject [Rn,...]. */
4805 if (inst.operands[1].preind)
b05fe5cf 4806 {
c19d1205
ZW
4807 constraint (inst.reloc.exp.X_op != O_constant ||
4808 inst.reloc.exp.X_add_number != 0,
4809 _("this instruction requires a post-indexed address"));
b05fe5cf 4810
c19d1205
ZW
4811 inst.operands[1].preind = 0;
4812 inst.operands[1].postind = 1;
4813 inst.operands[1].writeback = 1;
b05fe5cf 4814 }
c19d1205
ZW
4815 inst.instruction |= inst.operands[0].reg << 12;
4816 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
4817}
b05fe5cf 4818
c19d1205
ZW
4819/* Co-processor register load/store.
4820 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
4821static void
4822do_lstc (void)
4823{
4824 inst.instruction |= inst.operands[0].reg << 8;
4825 inst.instruction |= inst.operands[1].reg << 12;
4826 encode_arm_cp_address (2, TRUE, TRUE, 0);
b05fe5cf
ZW
4827}
4828
b05fe5cf 4829static void
c19d1205 4830do_mlas (void)
b05fe5cf 4831{
c19d1205
ZW
4832 /* This restriction does not apply to mls (nor to mla in v6, but
4833 that's hard to detect at present). */
4834 if (inst.operands[0].reg == inst.operands[1].reg
4835 && !(inst.instruction & 0x00400000))
4836 as_tsktsk (_("rd and rm should be different in mla"));
b05fe5cf 4837
c19d1205
ZW
4838 inst.instruction |= inst.operands[0].reg << 16;
4839 inst.instruction |= inst.operands[1].reg;
4840 inst.instruction |= inst.operands[2].reg << 8;
4841 inst.instruction |= inst.operands[3].reg << 12;
b05fe5cf 4842
c19d1205 4843}
b05fe5cf 4844
c19d1205
ZW
4845static void
4846do_mov (void)
4847{
4848 inst.instruction |= inst.operands[0].reg << 12;
4849 encode_arm_shifter_operand (1);
4850}
b05fe5cf 4851
c19d1205
ZW
4852/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
4853static void
4854do_mov16 (void)
4855{
4856 inst.instruction |= inst.operands[0].reg << 12;
b05fe5cf 4857 /* The value is in two pieces: 0:11, 16:19. */
c19d1205
ZW
4858 inst.instruction |= (inst.operands[1].imm & 0x00000fff);
4859 inst.instruction |= (inst.operands[1].imm & 0x0000f000) << 4;
b05fe5cf 4860}
b99bd4ef
NC
4861
4862static void
c19d1205 4863do_mrs (void)
b99bd4ef 4864{
c19d1205
ZW
4865 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
4866 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
4867 != (PSR_c|PSR_f),
4868 _("'CPSR' or 'SPSR' expected"));
4869 inst.instruction |= inst.operands[0].reg << 12;
4870 inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
4871}
b99bd4ef 4872
c19d1205
ZW
4873/* Two possible forms:
4874 "{C|S}PSR_<field>, Rm",
4875 "{C|S}PSR_f, #expression". */
b99bd4ef 4876
c19d1205
ZW
4877static void
4878do_msr (void)
4879{
4880 inst.instruction |= inst.operands[0].imm;
4881 if (inst.operands[1].isreg)
4882 inst.instruction |= inst.operands[1].reg;
4883 else
b99bd4ef 4884 {
c19d1205
ZW
4885 inst.instruction |= INST_IMMEDIATE;
4886 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4887 inst.reloc.pc_rel = 0;
b99bd4ef 4888 }
b99bd4ef
NC
4889}
4890
c19d1205
ZW
4891static void
4892do_mul (void)
a737bd4d 4893{
c19d1205
ZW
4894 if (!inst.operands[2].present)
4895 inst.operands[2].reg = inst.operands[0].reg;
4896 inst.instruction |= inst.operands[0].reg << 16;
4897 inst.instruction |= inst.operands[1].reg;
4898 inst.instruction |= inst.operands[2].reg << 8;
a737bd4d 4899
c19d1205
ZW
4900 if (inst.operands[0].reg == inst.operands[1].reg)
4901 as_tsktsk (_("rd and rm should be different in mul"));
a737bd4d
NC
4902}
4903
c19d1205
ZW
4904/* Long Multiply Parser
4905 UMULL RdLo, RdHi, Rm, Rs
4906 SMULL RdLo, RdHi, Rm, Rs
4907 UMLAL RdLo, RdHi, Rm, Rs
4908 SMLAL RdLo, RdHi, Rm, Rs. */
b99bd4ef
NC
4909
4910static void
c19d1205 4911do_mull (void)
b99bd4ef 4912{
c19d1205
ZW
4913 inst.instruction |= inst.operands[0].reg << 12;
4914 inst.instruction |= inst.operands[1].reg << 16;
4915 inst.instruction |= inst.operands[2].reg;
4916 inst.instruction |= inst.operands[3].reg << 8;
b99bd4ef 4917
c19d1205
ZW
4918 /* rdhi, rdlo and rm must all be different. */
4919 if (inst.operands[0].reg == inst.operands[1].reg
4920 || inst.operands[0].reg == inst.operands[2].reg
4921 || inst.operands[1].reg == inst.operands[2].reg)
4922 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
4923}
b99bd4ef 4924
c19d1205
ZW
4925static void
4926do_nop (void)
4927{
4928 if (inst.operands[0].present)
4929 {
4930 /* Architectural NOP hints are CPSR sets with no bits selected. */
4931 inst.instruction &= 0xf0000000;
4932 inst.instruction |= 0x0320f000 + inst.operands[0].imm;
4933 }
b99bd4ef
NC
4934}
4935
c19d1205
ZW
4936/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
4937 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
4938 Condition defaults to COND_ALWAYS.
4939 Error if Rd, Rn or Rm are R15. */
b99bd4ef
NC
4940
4941static void
c19d1205 4942do_pkhbt (void)
b99bd4ef 4943{
c19d1205
ZW
4944 inst.instruction |= inst.operands[0].reg << 12;
4945 inst.instruction |= inst.operands[1].reg << 16;
4946 inst.instruction |= inst.operands[2].reg;
4947 if (inst.operands[3].present)
4948 encode_arm_shift (3);
4949}
b99bd4ef 4950
c19d1205 4951/* ARM V6 PKHTB (Argument Parse). */
b99bd4ef 4952
c19d1205
ZW
4953static void
4954do_pkhtb (void)
4955{
4956 if (!inst.operands[3].present)
b99bd4ef 4957 {
c19d1205
ZW
4958 /* If the shift specifier is omitted, turn the instruction
4959 into pkhbt rd, rm, rn. */
4960 inst.instruction &= 0xfff00010;
4961 inst.instruction |= inst.operands[0].reg << 12;
4962 inst.instruction |= inst.operands[1].reg;
4963 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC
4964 }
4965 else
4966 {
c19d1205
ZW
4967 inst.instruction |= inst.operands[0].reg << 12;
4968 inst.instruction |= inst.operands[1].reg << 16;
4969 inst.instruction |= inst.operands[2].reg;
4970 encode_arm_shift (3);
b99bd4ef
NC
4971 }
4972}
4973
c19d1205
ZW
4974/* ARMv5TE: Preload-Cache
4975
4976 PLD <addr_mode>
4977
4978 Syntactically, like LDR with B=1, W=0, L=1. */
b99bd4ef
NC
4979
4980static void
c19d1205 4981do_pld (void)
b99bd4ef 4982{
c19d1205
ZW
4983 constraint (!inst.operands[0].isreg,
4984 _("'[' expected after PLD mnemonic"));
4985 constraint (inst.operands[0].postind,
4986 _("post-indexed expression used in preload instruction"));
4987 constraint (inst.operands[0].writeback,
4988 _("writeback used in preload instruction"));
4989 constraint (!inst.operands[0].preind,
4990 _("unindexed addressing used in preload instruction"));
4991 inst.instruction |= inst.operands[0].reg;
4992 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
4993}
b99bd4ef 4994
c19d1205
ZW
4995static void
4996do_push_pop (void)
4997{
4998 inst.operands[1] = inst.operands[0];
4999 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
5000 inst.operands[0].isreg = 1;
5001 inst.operands[0].writeback = 1;
5002 inst.operands[0].reg = REG_SP;
5003 do_ldmstm ();
5004}
b99bd4ef 5005
c19d1205
ZW
5006/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
5007 word at the specified address and the following word
5008 respectively.
5009 Unconditionally executed.
5010 Error if Rn is R15. */
b99bd4ef 5011
c19d1205
ZW
5012static void
5013do_rfe (void)
5014{
5015 inst.instruction |= inst.operands[0].reg << 16;
5016 if (inst.operands[0].writeback)
5017 inst.instruction |= WRITE_BACK;
5018}
b99bd4ef 5019
c19d1205 5020/* ARM V6 ssat (argument parse). */
b99bd4ef 5021
c19d1205
ZW
5022static void
5023do_ssat (void)
5024{
5025 inst.instruction |= inst.operands[0].reg << 12;
5026 inst.instruction |= (inst.operands[1].imm - 1) << 16;
5027 inst.instruction |= inst.operands[2].reg;
b99bd4ef 5028
c19d1205
ZW
5029 if (inst.operands[3].present)
5030 encode_arm_shift (3);
b99bd4ef
NC
5031}
5032
c19d1205 5033/* ARM V6 usat (argument parse). */
b99bd4ef
NC
5034
5035static void
c19d1205 5036do_usat (void)
b99bd4ef 5037{
c19d1205
ZW
5038 inst.instruction |= inst.operands[0].reg << 12;
5039 inst.instruction |= inst.operands[1].imm << 16;
5040 inst.instruction |= inst.operands[2].reg;
b99bd4ef 5041
c19d1205
ZW
5042 if (inst.operands[3].present)
5043 encode_arm_shift (3);
b99bd4ef
NC
5044}
5045
c19d1205 5046/* ARM V6 ssat16 (argument parse). */
09d92015
MM
5047
5048static void
c19d1205 5049do_ssat16 (void)
09d92015 5050{
c19d1205
ZW
5051 inst.instruction |= inst.operands[0].reg << 12;
5052 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
5053 inst.instruction |= inst.operands[2].reg;
09d92015
MM
5054}
5055
c19d1205
ZW
5056static void
5057do_usat16 (void)
a737bd4d 5058{
c19d1205
ZW
5059 inst.instruction |= inst.operands[0].reg << 12;
5060 inst.instruction |= inst.operands[1].imm << 16;
5061 inst.instruction |= inst.operands[2].reg;
5062}
a737bd4d 5063
c19d1205
ZW
5064/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
5065 preserving the other bits.
a737bd4d 5066
c19d1205
ZW
5067 setend <endian_specifier>, where <endian_specifier> is either
5068 BE or LE. */
a737bd4d 5069
c19d1205
ZW
5070static void
5071do_setend (void)
5072{
5073 if (inst.operands[0].imm)
5074 inst.instruction |= 0x200;
a737bd4d
NC
5075}
5076
5077static void
c19d1205 5078do_shift (void)
a737bd4d 5079{
c19d1205
ZW
5080 unsigned int Rm = (inst.operands[1].present
5081 ? inst.operands[1].reg
5082 : inst.operands[0].reg);
a737bd4d 5083
c19d1205
ZW
5084 inst.instruction |= inst.operands[0].reg << 12;
5085 inst.instruction |= Rm;
5086 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
a737bd4d 5087 {
c19d1205
ZW
5088 constraint (inst.operands[0].reg != Rm,
5089 _("source1 and dest must be same register"));
5090 inst.instruction |= inst.operands[2].reg << 8;
5091 inst.instruction |= SHIFT_BY_REG;
a737bd4d
NC
5092 }
5093 else
c19d1205 5094 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
a737bd4d
NC
5095}
5096
09d92015 5097static void
3eb17e6b 5098do_smc (void)
09d92015 5099{
3eb17e6b 5100 inst.reloc.type = BFD_RELOC_ARM_SMC;
c19d1205 5101 inst.reloc.pc_rel = 0;
09d92015
MM
5102}
5103
09d92015 5104static void
c19d1205 5105do_swi (void)
09d92015 5106{
c19d1205
ZW
5107 inst.reloc.type = BFD_RELOC_ARM_SWI;
5108 inst.reloc.pc_rel = 0;
09d92015
MM
5109}
5110
c19d1205
ZW
5111/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
5112 SMLAxy{cond} Rd,Rm,Rs,Rn
5113 SMLAWy{cond} Rd,Rm,Rs,Rn
5114 Error if any register is R15. */
e16bb312 5115
c19d1205
ZW
5116static void
5117do_smla (void)
e16bb312 5118{
c19d1205
ZW
5119 inst.instruction |= inst.operands[0].reg << 16;
5120 inst.instruction |= inst.operands[1].reg;
5121 inst.instruction |= inst.operands[2].reg << 8;
5122 inst.instruction |= inst.operands[3].reg << 12;
5123}
a737bd4d 5124
c19d1205
ZW
5125/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
5126 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
5127 Error if any register is R15.
5128 Warning if Rdlo == Rdhi. */
a737bd4d 5129
c19d1205
ZW
5130static void
5131do_smlal (void)
5132{
5133 inst.instruction |= inst.operands[0].reg << 12;
5134 inst.instruction |= inst.operands[1].reg << 16;
5135 inst.instruction |= inst.operands[2].reg;
5136 inst.instruction |= inst.operands[3].reg << 8;
a737bd4d 5137
c19d1205
ZW
5138 if (inst.operands[0].reg == inst.operands[1].reg)
5139 as_tsktsk (_("rdhi and rdlo must be different"));
5140}
a737bd4d 5141
c19d1205
ZW
5142/* ARM V5E (El Segundo) signed-multiply (argument parse)
5143 SMULxy{cond} Rd,Rm,Rs
5144 Error if any register is R15. */
a737bd4d 5145
c19d1205
ZW
5146static void
5147do_smul (void)
5148{
5149 inst.instruction |= inst.operands[0].reg << 16;
5150 inst.instruction |= inst.operands[1].reg;
5151 inst.instruction |= inst.operands[2].reg << 8;
5152}
a737bd4d 5153
c19d1205 5154/* ARM V6 srs (argument parse). */
a737bd4d 5155
c19d1205
ZW
5156static void
5157do_srs (void)
5158{
5159 inst.instruction |= inst.operands[0].imm;
5160 if (inst.operands[0].writeback)
5161 inst.instruction |= WRITE_BACK;
5162}
a737bd4d 5163
c19d1205 5164/* ARM V6 strex (argument parse). */
a737bd4d 5165
c19d1205
ZW
5166static void
5167do_strex (void)
5168{
5169 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
5170 || inst.operands[2].postind || inst.operands[2].writeback
5171 || inst.operands[2].immisreg || inst.operands[2].shifted
5172 || inst.operands[2].negative,
5173 _("instruction does not accept this addressing mode"));
e16bb312 5174
c19d1205 5175 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
a737bd4d 5176
c19d1205
ZW
5177 constraint (inst.operands[0].reg == inst.operands[1].reg
5178 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
a737bd4d 5179
c19d1205
ZW
5180 constraint (inst.reloc.exp.X_op != O_constant
5181 || inst.reloc.exp.X_add_number != 0,
5182 _("offset must be zero in ARM encoding"));
a737bd4d 5183
c19d1205
ZW
5184 inst.instruction |= inst.operands[0].reg << 12;
5185 inst.instruction |= inst.operands[1].reg;
5186 inst.instruction |= inst.operands[2].reg << 16;
5187 inst.reloc.type = BFD_RELOC_UNUSED;
e16bb312
NC
5188}
5189
5190static void
c19d1205 5191do_strexd (void)
e16bb312 5192{
c19d1205
ZW
5193 constraint (inst.operands[1].reg % 2 != 0,
5194 _("even register required"));
5195 constraint (inst.operands[2].present
5196 && inst.operands[2].reg != inst.operands[1].reg + 1,
5197 _("can only store two consecutive registers"));
5198 /* If op 2 were present and equal to PC, this function wouldn't
5199 have been called in the first place. */
5200 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
e16bb312 5201
c19d1205
ZW
5202 constraint (inst.operands[0].reg == inst.operands[1].reg
5203 || inst.operands[0].reg == inst.operands[1].reg + 1
5204 || inst.operands[0].reg == inst.operands[3].reg,
5205 BAD_OVERLAP);
e16bb312 5206
c19d1205
ZW
5207 inst.instruction |= inst.operands[0].reg << 12;
5208 inst.instruction |= inst.operands[1].reg;
5209 inst.instruction |= inst.operands[3].reg << 16;
e16bb312
NC
5210}
5211
c19d1205
ZW
5212/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
5213 extends it to 32-bits, and adds the result to a value in another
5214 register. You can specify a rotation by 0, 8, 16, or 24 bits
5215 before extracting the 16-bit value.
5216 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
5217 Condition defaults to COND_ALWAYS.
5218 Error if any register uses R15. */
5219
e16bb312 5220static void
c19d1205 5221do_sxtah (void)
e16bb312 5222{
c19d1205
ZW
5223 inst.instruction |= inst.operands[0].reg << 12;
5224 inst.instruction |= inst.operands[1].reg << 16;
5225 inst.instruction |= inst.operands[2].reg;
5226 inst.instruction |= inst.operands[3].imm << 10;
5227}
e16bb312 5228
c19d1205 5229/* ARM V6 SXTH.
e16bb312 5230
c19d1205
ZW
5231 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
5232 Condition defaults to COND_ALWAYS.
5233 Error if any register uses R15. */
e16bb312
NC
5234
5235static void
c19d1205 5236do_sxth (void)
e16bb312 5237{
c19d1205
ZW
5238 inst.instruction |= inst.operands[0].reg << 12;
5239 inst.instruction |= inst.operands[1].reg;
5240 inst.instruction |= inst.operands[2].imm << 10;
e16bb312 5241}
c19d1205
ZW
5242\f
5243/* VFP instructions. In a logical order: SP variant first, monad
5244 before dyad, arithmetic then move then load/store. */
e16bb312
NC
5245
5246static void
c19d1205 5247do_vfp_sp_monadic (void)
e16bb312 5248{
c19d1205
ZW
5249 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5250 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC
5251}
5252
5253static void
c19d1205 5254do_vfp_sp_dyadic (void)
e16bb312 5255{
c19d1205
ZW
5256 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5257 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
5258 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC
5259}
5260
5261static void
c19d1205 5262do_vfp_sp_compare_z (void)
e16bb312 5263{
c19d1205 5264 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
e16bb312
NC
5265}
5266
5267static void
c19d1205 5268do_vfp_dp_sp_cvt (void)
e16bb312 5269{
c19d1205
ZW
5270 inst.instruction |= inst.operands[0].reg << 12;
5271 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC
5272}
5273
5274static void
c19d1205 5275do_vfp_sp_dp_cvt (void)
e16bb312 5276{
c19d1205
ZW
5277 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5278 inst.instruction |= inst.operands[1].reg;
e16bb312
NC
5279}
5280
5281static void
c19d1205 5282do_vfp_reg_from_sp (void)
e16bb312 5283{
c19d1205
ZW
5284 inst.instruction |= inst.operands[0].reg << 12;
5285 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
e16bb312
NC
5286}
5287
5288static void
c19d1205 5289do_vfp_reg2_from_sp2 (void)
e16bb312 5290{
c19d1205
ZW
5291 constraint (inst.operands[2].imm != 2,
5292 _("only two consecutive VFP SP registers allowed here"));
5293 inst.instruction |= inst.operands[0].reg << 12;
5294 inst.instruction |= inst.operands[1].reg << 16;
5295 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC
5296}
5297
5298static void
c19d1205 5299do_vfp_sp_from_reg (void)
e16bb312 5300{
c19d1205
ZW
5301 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sn);
5302 inst.instruction |= inst.operands[1].reg << 12;
e16bb312
NC
5303}
5304
5305static void
c19d1205 5306do_vfp_sp2_from_reg2 (void)
e16bb312 5307{
c19d1205
ZW
5308 constraint (inst.operands[0].imm != 2,
5309 _("only two consecutive VFP SP registers allowed here"));
5310 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sm);
5311 inst.instruction |= inst.operands[1].reg << 12;
5312 inst.instruction |= inst.operands[2].reg << 16;
e16bb312
NC
5313}
5314
5315static void
c19d1205 5316do_vfp_sp_ldst (void)
e16bb312 5317{
c19d1205
ZW
5318 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5319 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC
5320}
5321
5322static void
c19d1205 5323do_vfp_dp_ldst (void)
e16bb312 5324{
c19d1205
ZW
5325 inst.instruction |= inst.operands[0].reg << 12;
5326 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC
5327}
5328
c19d1205 5329
e16bb312 5330static void
c19d1205 5331vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 5332{
c19d1205
ZW
5333 if (inst.operands[0].writeback)
5334 inst.instruction |= WRITE_BACK;
5335 else
5336 constraint (ldstm_type != VFP_LDSTMIA,
5337 _("this addressing mode requires base-register writeback"));
5338 inst.instruction |= inst.operands[0].reg << 16;
5339 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sd);
5340 inst.instruction |= inst.operands[1].imm;
e16bb312
NC
5341}
5342
5343static void
c19d1205 5344vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 5345{
c19d1205 5346 int count;
e16bb312 5347
c19d1205
ZW
5348 if (inst.operands[0].writeback)
5349 inst.instruction |= WRITE_BACK;
5350 else
5351 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
5352 _("this addressing mode requires base-register writeback"));
e16bb312 5353
c19d1205
ZW
5354 inst.instruction |= inst.operands[0].reg << 16;
5355 inst.instruction |= inst.operands[1].reg << 12;
e16bb312 5356
c19d1205
ZW
5357 count = inst.operands[1].imm << 1;
5358 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
5359 count += 1;
e16bb312 5360
c19d1205 5361 inst.instruction |= count;
e16bb312
NC
5362}
5363
5364static void
c19d1205 5365do_vfp_sp_ldstmia (void)
e16bb312 5366{
c19d1205 5367 vfp_sp_ldstm (VFP_LDSTMIA);
e16bb312
NC
5368}
5369
5370static void
c19d1205 5371do_vfp_sp_ldstmdb (void)
e16bb312 5372{
c19d1205 5373 vfp_sp_ldstm (VFP_LDSTMDB);
e16bb312
NC
5374}
5375
5376static void
c19d1205 5377do_vfp_dp_ldstmia (void)
e16bb312 5378{
c19d1205 5379 vfp_dp_ldstm (VFP_LDSTMIA);
e16bb312
NC
5380}
5381
5382static void
c19d1205 5383do_vfp_dp_ldstmdb (void)
e16bb312 5384{
c19d1205 5385 vfp_dp_ldstm (VFP_LDSTMDB);
e16bb312
NC
5386}
5387
5388static void
c19d1205 5389do_vfp_xp_ldstmia (void)
e16bb312 5390{
c19d1205
ZW
5391 vfp_dp_ldstm (VFP_LDSTMIAX);
5392}
e16bb312 5393
c19d1205
ZW
5394static void
5395do_vfp_xp_ldstmdb (void)
5396{
5397 vfp_dp_ldstm (VFP_LDSTMDBX);
e16bb312 5398}
c19d1205
ZW
5399\f
5400/* FPA instructions. Also in a logical order. */
e16bb312 5401
c19d1205
ZW
5402static void
5403do_fpa_cmp (void)
5404{
5405 inst.instruction |= inst.operands[0].reg << 16;
5406 inst.instruction |= inst.operands[1].reg;
5407}
b99bd4ef
NC
5408
5409static void
c19d1205 5410do_fpa_ldmstm (void)
b99bd4ef 5411{
c19d1205
ZW
5412 inst.instruction |= inst.operands[0].reg << 12;
5413 switch (inst.operands[1].imm)
5414 {
5415 case 1: inst.instruction |= CP_T_X; break;
5416 case 2: inst.instruction |= CP_T_Y; break;
5417 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
5418 case 4: break;
5419 default: abort ();
5420 }
b99bd4ef 5421
c19d1205
ZW
5422 if (inst.instruction & (PRE_INDEX | INDEX_UP))
5423 {
5424 /* The instruction specified "ea" or "fd", so we can only accept
5425 [Rn]{!}. The instruction does not really support stacking or
5426 unstacking, so we have to emulate these by setting appropriate
5427 bits and offsets. */
5428 constraint (inst.reloc.exp.X_op != O_constant
5429 || inst.reloc.exp.X_add_number != 0,
5430 _("this instruction does not support indexing"));
b99bd4ef 5431
c19d1205
ZW
5432 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
5433 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
b99bd4ef 5434
c19d1205
ZW
5435 if (!(inst.instruction & INDEX_UP))
5436 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
b99bd4ef 5437
c19d1205
ZW
5438 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
5439 {
5440 inst.operands[2].preind = 0;
5441 inst.operands[2].postind = 1;
5442 }
5443 }
b99bd4ef 5444
c19d1205 5445 encode_arm_cp_address (2, TRUE, TRUE, 0);
b99bd4ef 5446}
c19d1205
ZW
5447\f
5448/* iWMMXt instructions: strictly in alphabetical order. */
b99bd4ef 5449
c19d1205
ZW
5450static void
5451do_iwmmxt_tandorc (void)
5452{
5453 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
5454}
b99bd4ef 5455
c19d1205
ZW
5456static void
5457do_iwmmxt_textrc (void)
5458{
5459 inst.instruction |= inst.operands[0].reg << 12;
5460 inst.instruction |= inst.operands[1].imm;
5461}
b99bd4ef
NC
5462
5463static void
c19d1205 5464do_iwmmxt_textrm (void)
b99bd4ef 5465{
c19d1205
ZW
5466 inst.instruction |= inst.operands[0].reg << 12;
5467 inst.instruction |= inst.operands[1].reg << 16;
5468 inst.instruction |= inst.operands[2].imm;
5469}
b99bd4ef 5470
c19d1205
ZW
5471static void
5472do_iwmmxt_tinsr (void)
5473{
5474 inst.instruction |= inst.operands[0].reg << 16;
5475 inst.instruction |= inst.operands[1].reg << 12;
5476 inst.instruction |= inst.operands[2].imm;
5477}
b99bd4ef 5478
c19d1205
ZW
5479static void
5480do_iwmmxt_tmia (void)
5481{
5482 inst.instruction |= inst.operands[0].reg << 5;
5483 inst.instruction |= inst.operands[1].reg;
5484 inst.instruction |= inst.operands[2].reg << 12;
5485}
b99bd4ef 5486
c19d1205
ZW
5487static void
5488do_iwmmxt_waligni (void)
5489{
5490 inst.instruction |= inst.operands[0].reg << 12;
5491 inst.instruction |= inst.operands[1].reg << 16;
5492 inst.instruction |= inst.operands[2].reg;
5493 inst.instruction |= inst.operands[3].imm << 20;
5494}
b99bd4ef 5495
c19d1205
ZW
5496static void
5497do_iwmmxt_wmov (void)
5498{
5499 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
5500 inst.instruction |= inst.operands[0].reg << 12;
5501 inst.instruction |= inst.operands[1].reg << 16;
5502 inst.instruction |= inst.operands[1].reg;
5503}
b99bd4ef 5504
c19d1205
ZW
5505static void
5506do_iwmmxt_wldstbh (void)
5507{
8f06b2d8 5508 int reloc;
c19d1205
ZW
5509 inst.instruction |= inst.operands[0].reg << 12;
5510 inst.reloc.exp.X_add_number *= 4;
8f06b2d8
PB
5511 if (thumb_mode)
5512 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
5513 else
5514 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
5515 encode_arm_cp_address (1, TRUE, FALSE, reloc);
b99bd4ef
NC
5516}
5517
c19d1205
ZW
5518static void
5519do_iwmmxt_wldstw (void)
5520{
5521 /* RIWR_RIWC clears .isreg for a control register. */
5522 if (!inst.operands[0].isreg)
5523 {
5524 constraint (inst.cond != COND_ALWAYS, BAD_COND);
5525 inst.instruction |= 0xf0000000;
5526 }
b99bd4ef 5527
c19d1205
ZW
5528 inst.instruction |= inst.operands[0].reg << 12;
5529 encode_arm_cp_address (1, TRUE, TRUE, 0);
5530}
b99bd4ef
NC
5531
5532static void
c19d1205 5533do_iwmmxt_wldstd (void)
b99bd4ef 5534{
c19d1205 5535 inst.instruction |= inst.operands[0].reg << 12;
f2184508 5536 encode_arm_cp_address (1, TRUE, FALSE, 0);
c19d1205 5537}
b99bd4ef 5538
c19d1205
ZW
5539static void
5540do_iwmmxt_wshufh (void)
5541{
5542 inst.instruction |= inst.operands[0].reg << 12;
5543 inst.instruction |= inst.operands[1].reg << 16;
5544 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
5545 inst.instruction |= (inst.operands[2].imm & 0x0f);
5546}
b99bd4ef 5547
c19d1205
ZW
5548static void
5549do_iwmmxt_wzero (void)
5550{
5551 /* WZERO reg is an alias for WANDN reg, reg, reg. */
5552 inst.instruction |= inst.operands[0].reg;
5553 inst.instruction |= inst.operands[0].reg << 12;
5554 inst.instruction |= inst.operands[0].reg << 16;
5555}
5556\f
5557/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
5558 operations first, then control, shift, and load/store. */
b99bd4ef 5559
c19d1205 5560/* Insns like "foo X,Y,Z". */
b99bd4ef 5561
c19d1205
ZW
5562static void
5563do_mav_triple (void)
5564{
5565 inst.instruction |= inst.operands[0].reg << 16;
5566 inst.instruction |= inst.operands[1].reg;
5567 inst.instruction |= inst.operands[2].reg << 12;
5568}
b99bd4ef 5569
c19d1205
ZW
5570/* Insns like "foo W,X,Y,Z".
5571 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
a737bd4d 5572
c19d1205
ZW
5573static void
5574do_mav_quad (void)
5575{
5576 inst.instruction |= inst.operands[0].reg << 5;
5577 inst.instruction |= inst.operands[1].reg << 12;
5578 inst.instruction |= inst.operands[2].reg << 16;
5579 inst.instruction |= inst.operands[3].reg;
a737bd4d
NC
5580}
5581
c19d1205
ZW
5582/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
5583static void
5584do_mav_dspsc (void)
a737bd4d 5585{
c19d1205
ZW
5586 inst.instruction |= inst.operands[1].reg << 12;
5587}
a737bd4d 5588
c19d1205
ZW
5589/* Maverick shift immediate instructions.
5590 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
5591 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
a737bd4d 5592
c19d1205
ZW
5593static void
5594do_mav_shift (void)
5595{
5596 int imm = inst.operands[2].imm;
a737bd4d 5597
c19d1205
ZW
5598 inst.instruction |= inst.operands[0].reg << 12;
5599 inst.instruction |= inst.operands[1].reg << 16;
a737bd4d 5600
c19d1205
ZW
5601 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
5602 Bits 5-7 of the insn should have bits 4-6 of the immediate.
5603 Bit 4 should be 0. */
5604 imm = (imm & 0xf) | ((imm & 0x70) << 1);
a737bd4d 5605
c19d1205
ZW
5606 inst.instruction |= imm;
5607}
5608\f
5609/* XScale instructions. Also sorted arithmetic before move. */
a737bd4d 5610
c19d1205
ZW
5611/* Xscale multiply-accumulate (argument parse)
5612 MIAcc acc0,Rm,Rs
5613 MIAPHcc acc0,Rm,Rs
5614 MIAxycc acc0,Rm,Rs. */
a737bd4d 5615
c19d1205
ZW
5616static void
5617do_xsc_mia (void)
5618{
5619 inst.instruction |= inst.operands[1].reg;
5620 inst.instruction |= inst.operands[2].reg << 12;
5621}
a737bd4d 5622
c19d1205 5623/* Xscale move-accumulator-register (argument parse)
a737bd4d 5624
c19d1205 5625 MARcc acc0,RdLo,RdHi. */
b99bd4ef 5626
c19d1205
ZW
5627static void
5628do_xsc_mar (void)
5629{
5630 inst.instruction |= inst.operands[1].reg << 12;
5631 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC
5632}
5633
c19d1205 5634/* Xscale move-register-accumulator (argument parse)
b99bd4ef 5635
c19d1205 5636 MRAcc RdLo,RdHi,acc0. */
b99bd4ef
NC
5637
5638static void
c19d1205 5639do_xsc_mra (void)
b99bd4ef 5640{
c19d1205
ZW
5641 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
5642 inst.instruction |= inst.operands[0].reg << 12;
5643 inst.instruction |= inst.operands[1].reg << 16;
5644}
5645\f
5646/* Encoding functions relevant only to Thumb. */
b99bd4ef 5647
c19d1205
ZW
5648/* inst.operands[i] is a shifted-register operand; encode
5649 it into inst.instruction in the format used by Thumb32. */
5650
5651static void
5652encode_thumb32_shifted_operand (int i)
5653{
5654 unsigned int value = inst.reloc.exp.X_add_number;
5655 unsigned int shift = inst.operands[i].shift_kind;
b99bd4ef 5656
9c3c69f2
PB
5657 constraint (inst.operands[i].immisreg,
5658 _("shift by register not allowed in thumb mode"));
c19d1205
ZW
5659 inst.instruction |= inst.operands[i].reg;
5660 if (shift == SHIFT_RRX)
5661 inst.instruction |= SHIFT_ROR << 4;
5662 else
b99bd4ef 5663 {
c19d1205
ZW
5664 constraint (inst.reloc.exp.X_op != O_constant,
5665 _("expression too complex"));
5666
5667 constraint (value > 32
5668 || (value == 32 && (shift == SHIFT_LSL
5669 || shift == SHIFT_ROR)),
5670 _("shift expression is too large"));
5671
5672 if (value == 0)
5673 shift = SHIFT_LSL;
5674 else if (value == 32)
5675 value = 0;
5676
5677 inst.instruction |= shift << 4;
5678 inst.instruction |= (value & 0x1c) << 10;
5679 inst.instruction |= (value & 0x03) << 6;
b99bd4ef 5680 }
c19d1205 5681}
b99bd4ef 5682
b99bd4ef 5683
c19d1205
ZW
5684/* inst.operands[i] was set up by parse_address. Encode it into a
5685 Thumb32 format load or store instruction. Reject forms that cannot
5686 be used with such instructions. If is_t is true, reject forms that
5687 cannot be used with a T instruction; if is_d is true, reject forms
5688 that cannot be used with a D instruction. */
b99bd4ef 5689
c19d1205
ZW
5690static void
5691encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
5692{
5693 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
5694
5695 constraint (!inst.operands[i].isreg,
5696 _("Thumb does not support the ldr =N pseudo-operation"));
b99bd4ef 5697
c19d1205
ZW
5698 inst.instruction |= inst.operands[i].reg << 16;
5699 if (inst.operands[i].immisreg)
b99bd4ef 5700 {
c19d1205
ZW
5701 constraint (is_pc, _("cannot use register index with PC-relative addressing"));
5702 constraint (is_t || is_d, _("cannot use register index with this instruction"));
5703 constraint (inst.operands[i].negative,
5704 _("Thumb does not support negative register indexing"));
5705 constraint (inst.operands[i].postind,
5706 _("Thumb does not support register post-indexing"));
5707 constraint (inst.operands[i].writeback,
5708 _("Thumb does not support register indexing with writeback"));
5709 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
5710 _("Thumb supports only LSL in shifted register indexing"));
b99bd4ef 5711
c19d1205
ZW
5712 inst.instruction |= inst.operands[1].imm;
5713 if (inst.operands[i].shifted)
b99bd4ef 5714 {
c19d1205
ZW
5715 constraint (inst.reloc.exp.X_op != O_constant,
5716 _("expression too complex"));
9c3c69f2
PB
5717 constraint (inst.reloc.exp.X_add_number < 0
5718 || inst.reloc.exp.X_add_number > 3,
c19d1205 5719 _("shift out of range"));
9c3c69f2 5720 inst.instruction |= inst.reloc.exp.X_add_number << 4;
c19d1205
ZW
5721 }
5722 inst.reloc.type = BFD_RELOC_UNUSED;
5723 }
5724 else if (inst.operands[i].preind)
5725 {
5726 constraint (is_pc && inst.operands[i].writeback,
5727 _("cannot use writeback with PC-relative addressing"));
5728 constraint (is_t && inst.operands[1].writeback,
5729 _("cannot use writeback with this instruction"));
5730
5731 if (is_d)
5732 {
5733 inst.instruction |= 0x01000000;
5734 if (inst.operands[i].writeback)
5735 inst.instruction |= 0x00200000;
b99bd4ef 5736 }
c19d1205 5737 else
b99bd4ef 5738 {
c19d1205
ZW
5739 inst.instruction |= 0x00000c00;
5740 if (inst.operands[i].writeback)
5741 inst.instruction |= 0x00000100;
b99bd4ef 5742 }
c19d1205 5743 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
b99bd4ef 5744 }
c19d1205 5745 else if (inst.operands[i].postind)
b99bd4ef 5746 {
c19d1205
ZW
5747 assert (inst.operands[i].writeback);
5748 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
5749 constraint (is_t, _("cannot use post-indexing with this instruction"));
5750
5751 if (is_d)
5752 inst.instruction |= 0x00200000;
5753 else
5754 inst.instruction |= 0x00000900;
5755 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
5756 }
5757 else /* unindexed - only for coprocessor */
5758 inst.error = _("instruction does not accept unindexed addressing");
5759}
5760
5761/* Table of Thumb instructions which exist in both 16- and 32-bit
5762 encodings (the latter only in post-V6T2 cores). The index is the
5763 value used in the insns table below. When there is more than one
5764 possible 16-bit encoding for the instruction, this table always
0110f2b8
PB
5765 holds variant (1).
5766 Also contains several pseudo-instructions used during relaxation. */
c19d1205
ZW
5767#define T16_32_TAB \
5768 X(adc, 4140, eb400000), \
5769 X(adcs, 4140, eb500000), \
5770 X(add, 1c00, eb000000), \
5771 X(adds, 1c00, eb100000), \
0110f2b8
PB
5772 X(addi, 0000, f1000000), \
5773 X(addis, 0000, f1100000), \
5774 X(add_pc,000f, f20f0000), \
5775 X(add_sp,000d, f10d0000), \
e9f89963 5776 X(adr, 000f, f20f0000), \
c19d1205
ZW
5777 X(and, 4000, ea000000), \
5778 X(ands, 4000, ea100000), \
5779 X(asr, 1000, fa40f000), \
5780 X(asrs, 1000, fa50f000), \
0110f2b8
PB
5781 X(b, e000, f000b000), \
5782 X(bcond, d000, f0008000), \
c19d1205
ZW
5783 X(bic, 4380, ea200000), \
5784 X(bics, 4380, ea300000), \
5785 X(cmn, 42c0, eb100f00), \
5786 X(cmp, 2800, ebb00f00), \
5787 X(cpsie, b660, f3af8400), \
5788 X(cpsid, b670, f3af8600), \
5789 X(cpy, 4600, ea4f0000), \
0110f2b8 5790 X(dec_sp,80dd, f1bd0d00), \
c19d1205
ZW
5791 X(eor, 4040, ea800000), \
5792 X(eors, 4040, ea900000), \
0110f2b8 5793 X(inc_sp,00dd, f10d0d00), \
c19d1205
ZW
5794 X(ldmia, c800, e8900000), \
5795 X(ldr, 6800, f8500000), \
5796 X(ldrb, 7800, f8100000), \
5797 X(ldrh, 8800, f8300000), \
5798 X(ldrsb, 5600, f9100000), \
5799 X(ldrsh, 5e00, f9300000), \
0110f2b8
PB
5800 X(ldr_pc,4800, f85f0000), \
5801 X(ldr_pc2,4800, f85f0000), \
5802 X(ldr_sp,9800, f85d0000), \
c19d1205
ZW
5803 X(lsl, 0000, fa00f000), \
5804 X(lsls, 0000, fa10f000), \
5805 X(lsr, 0800, fa20f000), \
5806 X(lsrs, 0800, fa30f000), \
5807 X(mov, 2000, ea4f0000), \
5808 X(movs, 2000, ea5f0000), \
5809 X(mul, 4340, fb00f000), \
5810 X(muls, 4340, ffffffff), /* no 32b muls */ \
5811 X(mvn, 43c0, ea6f0000), \
5812 X(mvns, 43c0, ea7f0000), \
5813 X(neg, 4240, f1c00000), /* rsb #0 */ \
5814 X(negs, 4240, f1d00000), /* rsbs #0 */ \
5815 X(orr, 4300, ea400000), \
5816 X(orrs, 4300, ea500000), \
e9f89963
PB
5817 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
5818 X(push, b400, e92d0000), /* stmdb sp!,... */ \
c19d1205
ZW
5819 X(rev, ba00, fa90f080), \
5820 X(rev16, ba40, fa90f090), \
5821 X(revsh, bac0, fa90f0b0), \
5822 X(ror, 41c0, fa60f000), \
5823 X(rors, 41c0, fa70f000), \
5824 X(sbc, 4180, eb600000), \
5825 X(sbcs, 4180, eb700000), \
5826 X(stmia, c000, e8800000), \
5827 X(str, 6000, f8400000), \
5828 X(strb, 7000, f8000000), \
5829 X(strh, 8000, f8200000), \
0110f2b8 5830 X(str_sp,9000, f84d0000), \
c19d1205
ZW
5831 X(sub, 1e00, eba00000), \
5832 X(subs, 1e00, ebb00000), \
0110f2b8
PB
5833 X(subi, 8000, f1a00000), \
5834 X(subis, 8000, f1b00000), \
c19d1205
ZW
5835 X(sxtb, b240, fa4ff080), \
5836 X(sxth, b200, fa0ff080), \
5837 X(tst, 4200, ea100f00), \
5838 X(uxtb, b2c0, fa5ff080), \
5839 X(uxth, b280, fa1ff080), \
5840 X(nop, bf00, f3af8000), \
5841 X(yield, bf10, f3af8001), \
5842 X(wfe, bf20, f3af8002), \
5843 X(wfi, bf30, f3af8003), \
5844 X(sev, bf40, f3af9004), /* typo, 8004? */
5845
5846/* To catch errors in encoding functions, the codes are all offset by
5847 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
5848 as 16-bit instructions. */
5849#define X(a,b,c) T_MNEM_##a
5850enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
5851#undef X
5852
5853#define X(a,b,c) 0x##b
5854static const unsigned short thumb_op16[] = { T16_32_TAB };
5855#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
5856#undef X
5857
5858#define X(a,b,c) 0x##c
5859static const unsigned int thumb_op32[] = { T16_32_TAB };
5860#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
5861#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
5862#undef X
5863#undef T16_32_TAB
5864
5865/* Thumb instruction encoders, in alphabetical order. */
5866
92e90b6e
PB
5867/* ADDW or SUBW. */
5868static void
5869do_t_add_sub_w (void)
5870{
5871 int Rd, Rn;
5872
5873 Rd = inst.operands[0].reg;
5874 Rn = inst.operands[1].reg;
5875
5876 constraint (Rd == 15, _("PC not allowed as destination"));
5877 inst.instruction |= (Rn << 16) | (Rd << 8);
5878 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
5879}
5880
c19d1205
ZW
5881/* Parse an add or subtract instruction. We get here with inst.instruction
5882 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
5883
5884static void
5885do_t_add_sub (void)
5886{
5887 int Rd, Rs, Rn;
5888
5889 Rd = inst.operands[0].reg;
5890 Rs = (inst.operands[1].present
5891 ? inst.operands[1].reg /* Rd, Rs, foo */
5892 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
5893
5894 if (unified_syntax)
5895 {
0110f2b8
PB
5896 bfd_boolean flags;
5897 bfd_boolean narrow;
5898 int opcode;
5899
5900 flags = (inst.instruction == T_MNEM_adds
5901 || inst.instruction == T_MNEM_subs);
5902 if (flags)
5903 narrow = (current_it_mask == 0);
5904 else
5905 narrow = (current_it_mask != 0);
c19d1205 5906 if (!inst.operands[2].isreg)
b99bd4ef 5907 {
0110f2b8
PB
5908 opcode = 0;
5909 if (inst.size_req != 4)
5910 {
5911 int add;
5912
5913 add = (inst.instruction == T_MNEM_add
5914 || inst.instruction == T_MNEM_adds);
5915 /* Attempt to use a narrow opcode, with relaxation if
5916 appropriate. */
5917 if (Rd == REG_SP && Rs == REG_SP && !flags)
5918 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
5919 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
5920 opcode = T_MNEM_add_sp;
5921 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
5922 opcode = T_MNEM_add_pc;
5923 else if (Rd <= 7 && Rs <= 7 && narrow)
5924 {
5925 if (flags)
5926 opcode = add ? T_MNEM_addis : T_MNEM_subis;
5927 else
5928 opcode = add ? T_MNEM_addi : T_MNEM_subi;
5929 }
5930 if (opcode)
5931 {
5932 inst.instruction = THUMB_OP16(opcode);
5933 inst.instruction |= (Rd << 4) | Rs;
5934 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
5935 if (inst.size_req != 2)
5936 inst.relax = opcode;
5937 }
5938 else
5939 constraint (inst.size_req == 2, BAD_HIREG);
5940 }
5941 if (inst.size_req == 4
5942 || (inst.size_req != 2 && !opcode))
5943 {
5944 /* ??? Convert large immediates to addw/subw. */
5945 inst.instruction = THUMB_OP32 (inst.instruction);
5946 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
5947 inst.instruction |= inst.operands[0].reg << 8;
5948 inst.instruction |= inst.operands[1].reg << 16;
5949 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
5950 }
b99bd4ef 5951 }
c19d1205
ZW
5952 else
5953 {
5954 Rn = inst.operands[2].reg;
5955 /* See if we can do this with a 16-bit instruction. */
5956 if (!inst.operands[2].shifted && inst.size_req != 4)
5957 {
e27ec89e
PB
5958 if (Rd > 7 || Rs > 7 || Rn > 7)
5959 narrow = FALSE;
5960
5961 if (narrow)
c19d1205 5962 {
e27ec89e
PB
5963 inst.instruction = ((inst.instruction == T_MNEM_adds
5964 || inst.instruction == T_MNEM_add)
c19d1205
ZW
5965 ? T_OPCODE_ADD_R3
5966 : T_OPCODE_SUB_R3);
5967 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
5968 return;
5969 }
b99bd4ef 5970
c19d1205
ZW
5971 if (inst.instruction == T_MNEM_add)
5972 {
5973 if (Rd == Rs)
5974 {
5975 inst.instruction = T_OPCODE_ADD_HI;
5976 inst.instruction |= (Rd & 8) << 4;
5977 inst.instruction |= (Rd & 7);
5978 inst.instruction |= Rn << 3;
5979 return;
5980 }
5981 /* ... because addition is commutative! */
5982 else if (Rd == Rn)
5983 {
5984 inst.instruction = T_OPCODE_ADD_HI;
5985 inst.instruction |= (Rd & 8) << 4;
5986 inst.instruction |= (Rd & 7);
5987 inst.instruction |= Rs << 3;
5988 return;
5989 }
5990 }
5991 }
5992 /* If we get here, it can't be done in 16 bits. */
5993 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
5994 _("shift must be constant"));
5995 inst.instruction = THUMB_OP32 (inst.instruction);
5996 inst.instruction |= Rd << 8;
5997 inst.instruction |= Rs << 16;
5998 encode_thumb32_shifted_operand (2);
5999 }
6000 }
6001 else
6002 {
6003 constraint (inst.instruction == T_MNEM_adds
6004 || inst.instruction == T_MNEM_subs,
6005 BAD_THUMB32);
b99bd4ef 6006
c19d1205 6007 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
b99bd4ef 6008 {
c19d1205
ZW
6009 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
6010 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
6011 BAD_HIREG);
6012
6013 inst.instruction = (inst.instruction == T_MNEM_add
6014 ? 0x0000 : 0x8000);
6015 inst.instruction |= (Rd << 4) | Rs;
6016 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
b99bd4ef
NC
6017 return;
6018 }
6019
c19d1205
ZW
6020 Rn = inst.operands[2].reg;
6021 constraint (inst.operands[2].shifted, _("unshifted register required"));
b99bd4ef 6022
c19d1205
ZW
6023 /* We now have Rd, Rs, and Rn set to registers. */
6024 if (Rd > 7 || Rs > 7 || Rn > 7)
b99bd4ef 6025 {
c19d1205
ZW
6026 /* Can't do this for SUB. */
6027 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
6028 inst.instruction = T_OPCODE_ADD_HI;
6029 inst.instruction |= (Rd & 8) << 4;
6030 inst.instruction |= (Rd & 7);
6031 if (Rs == Rd)
6032 inst.instruction |= Rn << 3;
6033 else if (Rn == Rd)
6034 inst.instruction |= Rs << 3;
6035 else
6036 constraint (1, _("dest must overlap one source register"));
6037 }
6038 else
6039 {
6040 inst.instruction = (inst.instruction == T_MNEM_add
6041 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
6042 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
b99bd4ef 6043 }
b99bd4ef 6044 }
b99bd4ef
NC
6045}
6046
c19d1205
ZW
6047static void
6048do_t_adr (void)
6049{
0110f2b8
PB
6050 if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7)
6051 {
6052 /* Defer to section relaxation. */
6053 inst.relax = inst.instruction;
6054 inst.instruction = THUMB_OP16 (inst.instruction);
6055 inst.instruction |= inst.operands[0].reg << 4;
6056 }
6057 else if (unified_syntax && inst.size_req != 2)
e9f89963 6058 {
0110f2b8 6059 /* Generate a 32-bit opcode. */
e9f89963
PB
6060 inst.instruction = THUMB_OP32 (inst.instruction);
6061 inst.instruction |= inst.operands[0].reg << 8;
6062 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
6063 inst.reloc.pc_rel = 1;
6064 }
6065 else
6066 {
0110f2b8 6067 /* Generate a 16-bit opcode. */
e9f89963
PB
6068 inst.instruction = THUMB_OP16 (inst.instruction);
6069 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
6070 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
6071 inst.reloc.pc_rel = 1;
b99bd4ef 6072
e9f89963
PB
6073 inst.instruction |= inst.operands[0].reg << 4;
6074 }
c19d1205 6075}
b99bd4ef 6076
c19d1205
ZW
6077/* Arithmetic instructions for which there is just one 16-bit
6078 instruction encoding, and it allows only two low registers.
6079 For maximal compatibility with ARM syntax, we allow three register
6080 operands even when Thumb-32 instructions are not available, as long
6081 as the first two are identical. For instance, both "sbc r0,r1" and
6082 "sbc r0,r0,r1" are allowed. */
b99bd4ef 6083static void
c19d1205 6084do_t_arit3 (void)
b99bd4ef 6085{
c19d1205 6086 int Rd, Rs, Rn;
b99bd4ef 6087
c19d1205
ZW
6088 Rd = inst.operands[0].reg;
6089 Rs = (inst.operands[1].present
6090 ? inst.operands[1].reg /* Rd, Rs, foo */
6091 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6092 Rn = inst.operands[2].reg;
b99bd4ef 6093
c19d1205 6094 if (unified_syntax)
b99bd4ef 6095 {
c19d1205
ZW
6096 if (!inst.operands[2].isreg)
6097 {
6098 /* For an immediate, we always generate a 32-bit opcode;
6099 section relaxation will shrink it later if possible. */
6100 inst.instruction = THUMB_OP32 (inst.instruction);
6101 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6102 inst.instruction |= Rd << 8;
6103 inst.instruction |= Rs << 16;
6104 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6105 }
6106 else
6107 {
e27ec89e
PB
6108 bfd_boolean narrow;
6109
c19d1205 6110 /* See if we can do this with a 16-bit instruction. */
e27ec89e
PB
6111 if (THUMB_SETS_FLAGS (inst.instruction))
6112 narrow = current_it_mask == 0;
6113 else
6114 narrow = current_it_mask != 0;
6115
6116 if (Rd > 7 || Rn > 7 || Rs > 7)
6117 narrow = FALSE;
6118 if (inst.operands[2].shifted)
6119 narrow = FALSE;
6120 if (inst.size_req == 4)
6121 narrow = FALSE;
6122
6123 if (narrow
c19d1205
ZW
6124 && Rd == Rs)
6125 {
6126 inst.instruction = THUMB_OP16 (inst.instruction);
6127 inst.instruction |= Rd;
6128 inst.instruction |= Rn << 3;
6129 return;
6130 }
b99bd4ef 6131
c19d1205
ZW
6132 /* If we get here, it can't be done in 16 bits. */
6133 constraint (inst.operands[2].shifted
6134 && inst.operands[2].immisreg,
6135 _("shift must be constant"));
6136 inst.instruction = THUMB_OP32 (inst.instruction);
6137 inst.instruction |= Rd << 8;
6138 inst.instruction |= Rs << 16;
6139 encode_thumb32_shifted_operand (2);
6140 }
a737bd4d 6141 }
c19d1205 6142 else
b99bd4ef 6143 {
c19d1205
ZW
6144 /* On its face this is a lie - the instruction does set the
6145 flags. However, the only supported mnemonic in this mode
6146 says it doesn't. */
6147 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 6148
c19d1205
ZW
6149 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
6150 _("unshifted register required"));
6151 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
6152 constraint (Rd != Rs,
6153 _("dest and source1 must be the same register"));
a737bd4d 6154
c19d1205
ZW
6155 inst.instruction = THUMB_OP16 (inst.instruction);
6156 inst.instruction |= Rd;
6157 inst.instruction |= Rn << 3;
b99bd4ef 6158 }
a737bd4d 6159}
b99bd4ef 6160
c19d1205
ZW
6161/* Similarly, but for instructions where the arithmetic operation is
6162 commutative, so we can allow either of them to be different from
6163 the destination operand in a 16-bit instruction. For instance, all
6164 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
6165 accepted. */
6166static void
6167do_t_arit3c (void)
a737bd4d 6168{
c19d1205 6169 int Rd, Rs, Rn;
b99bd4ef 6170
c19d1205
ZW
6171 Rd = inst.operands[0].reg;
6172 Rs = (inst.operands[1].present
6173 ? inst.operands[1].reg /* Rd, Rs, foo */
6174 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6175 Rn = inst.operands[2].reg;
a737bd4d 6176
c19d1205 6177 if (unified_syntax)
a737bd4d 6178 {
c19d1205 6179 if (!inst.operands[2].isreg)
b99bd4ef 6180 {
c19d1205
ZW
6181 /* For an immediate, we always generate a 32-bit opcode;
6182 section relaxation will shrink it later if possible. */
6183 inst.instruction = THUMB_OP32 (inst.instruction);
6184 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6185 inst.instruction |= Rd << 8;
6186 inst.instruction |= Rs << 16;
6187 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 6188 }
c19d1205 6189 else
a737bd4d 6190 {
e27ec89e
PB
6191 bfd_boolean narrow;
6192
c19d1205 6193 /* See if we can do this with a 16-bit instruction. */
e27ec89e
PB
6194 if (THUMB_SETS_FLAGS (inst.instruction))
6195 narrow = current_it_mask == 0;
6196 else
6197 narrow = current_it_mask != 0;
6198
6199 if (Rd > 7 || Rn > 7 || Rs > 7)
6200 narrow = FALSE;
6201 if (inst.operands[2].shifted)
6202 narrow = FALSE;
6203 if (inst.size_req == 4)
6204 narrow = FALSE;
6205
6206 if (narrow)
a737bd4d 6207 {
c19d1205 6208 if (Rd == Rs)
a737bd4d 6209 {
c19d1205
ZW
6210 inst.instruction = THUMB_OP16 (inst.instruction);
6211 inst.instruction |= Rd;
6212 inst.instruction |= Rn << 3;
6213 return;
a737bd4d 6214 }
c19d1205 6215 if (Rd == Rn)
a737bd4d 6216 {
c19d1205
ZW
6217 inst.instruction = THUMB_OP16 (inst.instruction);
6218 inst.instruction |= Rd;
6219 inst.instruction |= Rs << 3;
6220 return;
a737bd4d
NC
6221 }
6222 }
c19d1205
ZW
6223
6224 /* If we get here, it can't be done in 16 bits. */
6225 constraint (inst.operands[2].shifted
6226 && inst.operands[2].immisreg,
6227 _("shift must be constant"));
6228 inst.instruction = THUMB_OP32 (inst.instruction);
6229 inst.instruction |= Rd << 8;
6230 inst.instruction |= Rs << 16;
6231 encode_thumb32_shifted_operand (2);
a737bd4d 6232 }
b99bd4ef 6233 }
c19d1205
ZW
6234 else
6235 {
6236 /* On its face this is a lie - the instruction does set the
6237 flags. However, the only supported mnemonic in this mode
6238 says it doesn't. */
6239 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 6240
c19d1205
ZW
6241 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
6242 _("unshifted register required"));
6243 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
6244
6245 inst.instruction = THUMB_OP16 (inst.instruction);
6246 inst.instruction |= Rd;
6247
6248 if (Rd == Rs)
6249 inst.instruction |= Rn << 3;
6250 else if (Rd == Rn)
6251 inst.instruction |= Rs << 3;
6252 else
6253 constraint (1, _("dest must overlap one source register"));
6254 }
a737bd4d
NC
6255}
6256
c19d1205
ZW
6257static void
6258do_t_bfc (void)
a737bd4d 6259{
c19d1205
ZW
6260 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
6261 constraint (msb > 32, _("bit-field extends past end of register"));
6262 /* The instruction encoding stores the LSB and MSB,
6263 not the LSB and width. */
6264 inst.instruction |= inst.operands[0].reg << 8;
6265 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
6266 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
6267 inst.instruction |= msb - 1;
b99bd4ef
NC
6268}
6269
c19d1205
ZW
6270static void
6271do_t_bfi (void)
b99bd4ef 6272{
c19d1205 6273 unsigned int msb;
b99bd4ef 6274
c19d1205
ZW
6275 /* #0 in second position is alternative syntax for bfc, which is
6276 the same instruction but with REG_PC in the Rm field. */
6277 if (!inst.operands[1].isreg)
6278 inst.operands[1].reg = REG_PC;
b99bd4ef 6279
c19d1205
ZW
6280 msb = inst.operands[2].imm + inst.operands[3].imm;
6281 constraint (msb > 32, _("bit-field extends past end of register"));
6282 /* The instruction encoding stores the LSB and MSB,
6283 not the LSB and width. */
6284 inst.instruction |= inst.operands[0].reg << 8;
6285 inst.instruction |= inst.operands[1].reg << 16;
6286 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6287 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6288 inst.instruction |= msb - 1;
b99bd4ef
NC
6289}
6290
c19d1205
ZW
6291static void
6292do_t_bfx (void)
b99bd4ef 6293{
c19d1205
ZW
6294 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
6295 _("bit-field extends past end of register"));
6296 inst.instruction |= inst.operands[0].reg << 8;
6297 inst.instruction |= inst.operands[1].reg << 16;
6298 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6299 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6300 inst.instruction |= inst.operands[3].imm - 1;
6301}
b99bd4ef 6302
c19d1205
ZW
6303/* ARM V5 Thumb BLX (argument parse)
6304 BLX <target_addr> which is BLX(1)
6305 BLX <Rm> which is BLX(2)
6306 Unfortunately, there are two different opcodes for this mnemonic.
6307 So, the insns[].value is not used, and the code here zaps values
6308 into inst.instruction.
b99bd4ef 6309
c19d1205
ZW
6310 ??? How to take advantage of the additional two bits of displacement
6311 available in Thumb32 mode? Need new relocation? */
b99bd4ef 6312
c19d1205
ZW
6313static void
6314do_t_blx (void)
6315{
6316 if (inst.operands[0].isreg)
6317 /* We have a register, so this is BLX(2). */
6318 inst.instruction |= inst.operands[0].reg << 3;
b99bd4ef
NC
6319 else
6320 {
c19d1205 6321 /* No register. This must be BLX(1). */
2fc8bdac 6322 inst.instruction = 0xf000e800;
c19d1205
ZW
6323 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
6324 inst.reloc.pc_rel = 1;
b99bd4ef
NC
6325 }
6326}
6327
c19d1205
ZW
6328static void
6329do_t_branch (void)
b99bd4ef 6330{
0110f2b8
PB
6331 int opcode;
6332 if (inst.cond != COND_ALWAYS)
6333 opcode = T_MNEM_bcond;
6334 else
6335 opcode = inst.instruction;
6336
6337 if (unified_syntax && inst.size_req == 4)
c19d1205 6338 {
0110f2b8 6339 inst.instruction = THUMB_OP32(opcode);
c19d1205 6340 if (inst.cond == COND_ALWAYS)
0110f2b8 6341 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
c19d1205
ZW
6342 else
6343 {
6344 assert (inst.cond != 0xF);
0110f2b8 6345 inst.instruction |= inst.cond << 22;
c19d1205
ZW
6346 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
6347 }
6348 }
b99bd4ef
NC
6349 else
6350 {
0110f2b8 6351 inst.instruction = THUMB_OP16(opcode);
c19d1205
ZW
6352 if (inst.cond == COND_ALWAYS)
6353 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
6354 else
b99bd4ef 6355 {
0110f2b8 6356 inst.instruction |= inst.cond << 8;
c19d1205 6357 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
b99bd4ef 6358 }
0110f2b8
PB
6359 /* Allow section relaxation. */
6360 if (unified_syntax && inst.size_req != 2)
6361 inst.relax = opcode;
b99bd4ef 6362 }
c19d1205
ZW
6363
6364 inst.reloc.pc_rel = 1;
b99bd4ef
NC
6365}
6366
6367static void
c19d1205 6368do_t_bkpt (void)
b99bd4ef 6369{
c19d1205 6370 if (inst.operands[0].present)
b99bd4ef 6371 {
c19d1205
ZW
6372 constraint (inst.operands[0].imm > 255,
6373 _("immediate value out of range"));
6374 inst.instruction |= inst.operands[0].imm;
b99bd4ef 6375 }
b99bd4ef
NC
6376}
6377
6378static void
c19d1205 6379do_t_branch23 (void)
b99bd4ef 6380{
c19d1205 6381 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
90e4755a
RE
6382 inst.reloc.pc_rel = 1;
6383
c19d1205
ZW
6384 /* If the destination of the branch is a defined symbol which does not have
6385 the THUMB_FUNC attribute, then we must be calling a function which has
6386 the (interfacearm) attribute. We look for the Thumb entry point to that
6387 function and change the branch to refer to that function instead. */
6388 if ( inst.reloc.exp.X_op == O_symbol
6389 && inst.reloc.exp.X_add_symbol != NULL
6390 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
6391 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
6392 inst.reloc.exp.X_add_symbol =
6393 find_real_start (inst.reloc.exp.X_add_symbol);
90e4755a
RE
6394}
6395
6396static void
c19d1205 6397do_t_bx (void)
90e4755a 6398{
c19d1205
ZW
6399 inst.instruction |= inst.operands[0].reg << 3;
6400 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
6401 should cause the alignment to be checked once it is known. This is
6402 because BX PC only works if the instruction is word aligned. */
6403}
90e4755a 6404
c19d1205
ZW
6405static void
6406do_t_bxj (void)
6407{
6408 if (inst.operands[0].reg == REG_PC)
6409 as_tsktsk (_("use of r15 in bxj is not really useful"));
90e4755a 6410
c19d1205 6411 inst.instruction |= inst.operands[0].reg << 16;
90e4755a
RE
6412}
6413
6414static void
c19d1205 6415do_t_clz (void)
90e4755a 6416{
c19d1205
ZW
6417 inst.instruction |= inst.operands[0].reg << 8;
6418 inst.instruction |= inst.operands[1].reg << 16;
6419 inst.instruction |= inst.operands[1].reg;
6420}
90e4755a 6421
c19d1205
ZW
6422static void
6423do_t_cpsi (void)
6424{
6425 if (unified_syntax
6426 && (inst.operands[1].present || inst.size_req == 4))
90e4755a 6427 {
c19d1205
ZW
6428 unsigned int imod = (inst.instruction & 0x0030) >> 4;
6429 inst.instruction = 0xf3af8000;
6430 inst.instruction |= imod << 9;
6431 inst.instruction |= inst.operands[0].imm << 5;
6432 if (inst.operands[1].present)
6433 inst.instruction |= 0x100 | inst.operands[1].imm;
90e4755a 6434 }
c19d1205 6435 else
90e4755a 6436 {
c19d1205
ZW
6437 constraint (inst.operands[1].present,
6438 _("Thumb does not support the 2-argument "
6439 "form of this instruction"));
6440 inst.instruction |= inst.operands[0].imm;
90e4755a 6441 }
90e4755a
RE
6442}
6443
c19d1205
ZW
6444/* THUMB CPY instruction (argument parse). */
6445
90e4755a 6446static void
c19d1205 6447do_t_cpy (void)
90e4755a 6448{
c19d1205 6449 if (inst.size_req == 4)
90e4755a 6450 {
c19d1205
ZW
6451 inst.instruction = THUMB_OP32 (T_MNEM_mov);
6452 inst.instruction |= inst.operands[0].reg << 8;
6453 inst.instruction |= inst.operands[1].reg;
90e4755a 6454 }
c19d1205 6455 else
90e4755a 6456 {
c19d1205
ZW
6457 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6458 inst.instruction |= (inst.operands[0].reg & 0x7);
6459 inst.instruction |= inst.operands[1].reg << 3;
90e4755a 6460 }
90e4755a
RE
6461}
6462
90e4755a 6463static void
c19d1205 6464do_t_czb (void)
90e4755a 6465{
c19d1205
ZW
6466 constraint (inst.operands[0].reg > 7, BAD_HIREG);
6467 inst.instruction |= inst.operands[0].reg;
6468 inst.reloc.pc_rel = 1;
6469 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
6470}
90e4755a 6471
c19d1205
ZW
6472static void
6473do_t_hint (void)
6474{
6475 if (unified_syntax && inst.size_req == 4)
6476 inst.instruction = THUMB_OP32 (inst.instruction);
6477 else
6478 inst.instruction = THUMB_OP16 (inst.instruction);
6479}
90e4755a 6480
c19d1205
ZW
6481static void
6482do_t_it (void)
6483{
6484 unsigned int cond = inst.operands[0].imm;
e27ec89e
PB
6485
6486 current_it_mask = (inst.instruction & 0xf) | 0x10;
6487 current_cc = cond;
6488
6489 /* If the condition is a negative condition, invert the mask. */
c19d1205 6490 if ((cond & 0x1) == 0x0)
90e4755a 6491 {
c19d1205 6492 unsigned int mask = inst.instruction & 0x000f;
90e4755a 6493
c19d1205
ZW
6494 if ((mask & 0x7) == 0)
6495 /* no conversion needed */;
6496 else if ((mask & 0x3) == 0)
e27ec89e
PB
6497 mask ^= 0x8;
6498 else if ((mask & 0x1) == 0)
6499 mask ^= 0xC;
c19d1205 6500 else
e27ec89e 6501 mask ^= 0xE;
90e4755a 6502
e27ec89e
PB
6503 inst.instruction &= 0xfff0;
6504 inst.instruction |= mask;
c19d1205 6505 }
90e4755a 6506
c19d1205
ZW
6507 inst.instruction |= cond << 4;
6508}
90e4755a 6509
c19d1205
ZW
6510static void
6511do_t_ldmstm (void)
6512{
6513 /* This really doesn't seem worth it. */
6514 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
6515 _("expression too complex"));
6516 constraint (inst.operands[1].writeback,
6517 _("Thumb load/store multiple does not support {reglist}^"));
90e4755a 6518
c19d1205
ZW
6519 if (unified_syntax)
6520 {
6521 /* See if we can use a 16-bit instruction. */
6522 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
6523 && inst.size_req != 4
6524 && inst.operands[0].reg <= 7
6525 && !(inst.operands[1].imm & ~0xff)
6526 && (inst.instruction == T_MNEM_stmia
6527 ? inst.operands[0].writeback
6528 : (inst.operands[0].writeback
6529 == !(inst.operands[1].imm & (1 << inst.operands[0].reg)))))
90e4755a 6530 {
c19d1205
ZW
6531 if (inst.instruction == T_MNEM_stmia
6532 && (inst.operands[1].imm & (1 << inst.operands[0].reg))
6533 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6534 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6535 inst.operands[0].reg);
90e4755a 6536
c19d1205
ZW
6537 inst.instruction = THUMB_OP16 (inst.instruction);
6538 inst.instruction |= inst.operands[0].reg << 8;
6539 inst.instruction |= inst.operands[1].imm;
6540 }
6541 else
6542 {
6543 if (inst.operands[1].imm & (1 << 13))
6544 as_warn (_("SP should not be in register list"));
6545 if (inst.instruction == T_MNEM_stmia)
90e4755a 6546 {
c19d1205
ZW
6547 if (inst.operands[1].imm & (1 << 15))
6548 as_warn (_("PC should not be in register list"));
6549 if (inst.operands[1].imm & (1 << inst.operands[0].reg))
6550 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6551 inst.operands[0].reg);
90e4755a
RE
6552 }
6553 else
6554 {
c19d1205
ZW
6555 if (inst.operands[1].imm & (1 << 14)
6556 && inst.operands[1].imm & (1 << 15))
6557 as_warn (_("LR and PC should not both be in register list"));
6558 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6559 && inst.operands[0].writeback)
6560 as_warn (_("base register should not be in register list "
6561 "when written back"));
90e4755a 6562 }
c19d1205
ZW
6563 if (inst.instruction < 0xffff)
6564 inst.instruction = THUMB_OP32 (inst.instruction);
6565 inst.instruction |= inst.operands[0].reg << 16;
6566 inst.instruction |= inst.operands[1].imm;
6567 if (inst.operands[0].writeback)
6568 inst.instruction |= WRITE_BACK;
90e4755a
RE
6569 }
6570 }
c19d1205 6571 else
90e4755a 6572 {
c19d1205
ZW
6573 constraint (inst.operands[0].reg > 7
6574 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
6575 if (inst.instruction == T_MNEM_stmia)
f03698e6 6576 {
c19d1205
ZW
6577 if (!inst.operands[0].writeback)
6578 as_warn (_("this instruction will write back the base register"));
6579 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6580 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6581 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6582 inst.operands[0].reg);
f03698e6 6583 }
c19d1205 6584 else
90e4755a 6585 {
c19d1205
ZW
6586 if (!inst.operands[0].writeback
6587 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
6588 as_warn (_("this instruction will write back the base register"));
6589 else if (inst.operands[0].writeback
6590 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
6591 as_warn (_("this instruction will not write back the base register"));
90e4755a
RE
6592 }
6593
c19d1205
ZW
6594 inst.instruction = THUMB_OP16 (inst.instruction);
6595 inst.instruction |= inst.operands[0].reg << 8;
6596 inst.instruction |= inst.operands[1].imm;
6597 }
6598}
e28cd48c 6599
c19d1205
ZW
6600static void
6601do_t_ldrex (void)
6602{
6603 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
6604 || inst.operands[1].postind || inst.operands[1].writeback
6605 || inst.operands[1].immisreg || inst.operands[1].shifted
6606 || inst.operands[1].negative,
6607 _("instruction does not accept this addressing mode"));
e28cd48c 6608
c19d1205
ZW
6609 inst.instruction |= inst.operands[0].reg << 12;
6610 inst.instruction |= inst.operands[1].reg << 16;
6611 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
6612}
e28cd48c 6613
c19d1205
ZW
6614static void
6615do_t_ldrexd (void)
6616{
6617 if (!inst.operands[1].present)
1cac9012 6618 {
c19d1205
ZW
6619 constraint (inst.operands[0].reg == REG_LR,
6620 _("r14 not allowed as first register "
6621 "when second register is omitted"));
6622 inst.operands[1].reg = inst.operands[0].reg + 1;
b99bd4ef 6623 }
c19d1205
ZW
6624 constraint (inst.operands[0].reg == inst.operands[1].reg,
6625 BAD_OVERLAP);
b99bd4ef 6626
c19d1205
ZW
6627 inst.instruction |= inst.operands[0].reg << 12;
6628 inst.instruction |= inst.operands[1].reg << 8;
6629 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC
6630}
6631
6632static void
c19d1205 6633do_t_ldst (void)
b99bd4ef 6634{
0110f2b8
PB
6635 unsigned long opcode;
6636 int Rn;
6637
6638 opcode = inst.instruction;
c19d1205 6639 if (unified_syntax)
b99bd4ef 6640 {
0110f2b8
PB
6641 if (inst.operands[1].isreg
6642 && !inst.operands[1].writeback
c19d1205
ZW
6643 && !inst.operands[1].shifted && !inst.operands[1].postind
6644 && !inst.operands[1].negative && inst.operands[0].reg <= 7
0110f2b8
PB
6645 && opcode <= 0xffff
6646 && inst.size_req != 4)
c19d1205 6647 {
0110f2b8
PB
6648 /* Insn may have a 16-bit form. */
6649 Rn = inst.operands[1].reg;
6650 if (inst.operands[1].immisreg)
6651 {
6652 inst.instruction = THUMB_OP16 (opcode);
6653 /* [Rn, Ri] */
6654 if (Rn <= 7 && inst.operands[1].imm <= 7)
6655 goto op16;
6656 }
6657 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
6658 && opcode != T_MNEM_ldrsb)
6659 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
6660 || (Rn == REG_SP && opcode == T_MNEM_str))
6661 {
6662 /* [Rn, #const] */
6663 if (Rn > 7)
6664 {
6665 if (Rn == REG_PC)
6666 {
6667 if (inst.reloc.pc_rel)
6668 opcode = T_MNEM_ldr_pc2;
6669 else
6670 opcode = T_MNEM_ldr_pc;
6671 }
6672 else
6673 {
6674 if (opcode == T_MNEM_ldr)
6675 opcode = T_MNEM_ldr_sp;
6676 else
6677 opcode = T_MNEM_str_sp;
6678 }
6679 inst.instruction = inst.operands[0].reg << 8;
6680 }
6681 else
6682 {
6683 inst.instruction = inst.operands[0].reg;
6684 inst.instruction |= inst.operands[1].reg << 3;
6685 }
6686 inst.instruction |= THUMB_OP16 (opcode);
6687 if (inst.size_req == 2)
6688 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6689 else
6690 inst.relax = opcode;
6691 return;
6692 }
c19d1205 6693 }
0110f2b8
PB
6694 /* Definitely a 32-bit variant. */
6695 inst.instruction = THUMB_OP32 (opcode);
c19d1205
ZW
6696 inst.instruction |= inst.operands[0].reg << 12;
6697 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
b99bd4ef
NC
6698 return;
6699 }
6700
c19d1205
ZW
6701 constraint (inst.operands[0].reg > 7, BAD_HIREG);
6702
6703 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
b99bd4ef 6704 {
c19d1205
ZW
6705 /* Only [Rn,Rm] is acceptable. */
6706 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
6707 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
6708 || inst.operands[1].postind || inst.operands[1].shifted
6709 || inst.operands[1].negative,
6710 _("Thumb does not support this addressing mode"));
6711 inst.instruction = THUMB_OP16 (inst.instruction);
6712 goto op16;
b99bd4ef 6713 }
c19d1205
ZW
6714
6715 inst.instruction = THUMB_OP16 (inst.instruction);
6716 if (!inst.operands[1].isreg)
6717 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
6718 return;
b99bd4ef 6719
c19d1205
ZW
6720 constraint (!inst.operands[1].preind
6721 || inst.operands[1].shifted
6722 || inst.operands[1].writeback,
6723 _("Thumb does not support this addressing mode"));
6724 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
90e4755a 6725 {
c19d1205
ZW
6726 constraint (inst.instruction & 0x0600,
6727 _("byte or halfword not valid for base register"));
6728 constraint (inst.operands[1].reg == REG_PC
6729 && !(inst.instruction & THUMB_LOAD_BIT),
6730 _("r15 based store not allowed"));
6731 constraint (inst.operands[1].immisreg,
6732 _("invalid base register for register offset"));
b99bd4ef 6733
c19d1205
ZW
6734 if (inst.operands[1].reg == REG_PC)
6735 inst.instruction = T_OPCODE_LDR_PC;
6736 else if (inst.instruction & THUMB_LOAD_BIT)
6737 inst.instruction = T_OPCODE_LDR_SP;
6738 else
6739 inst.instruction = T_OPCODE_STR_SP;
b99bd4ef 6740
c19d1205
ZW
6741 inst.instruction |= inst.operands[0].reg << 8;
6742 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6743 return;
6744 }
90e4755a 6745
c19d1205
ZW
6746 constraint (inst.operands[1].reg > 7, BAD_HIREG);
6747 if (!inst.operands[1].immisreg)
6748 {
6749 /* Immediate offset. */
6750 inst.instruction |= inst.operands[0].reg;
6751 inst.instruction |= inst.operands[1].reg << 3;
6752 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6753 return;
6754 }
90e4755a 6755
c19d1205
ZW
6756 /* Register offset. */
6757 constraint (inst.operands[1].imm > 7, BAD_HIREG);
6758 constraint (inst.operands[1].negative,
6759 _("Thumb does not support this addressing mode"));
90e4755a 6760
c19d1205
ZW
6761 op16:
6762 switch (inst.instruction)
6763 {
6764 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
6765 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
6766 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
6767 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
6768 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
6769 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
6770 case 0x5600 /* ldrsb */:
6771 case 0x5e00 /* ldrsh */: break;
6772 default: abort ();
6773 }
90e4755a 6774
c19d1205
ZW
6775 inst.instruction |= inst.operands[0].reg;
6776 inst.instruction |= inst.operands[1].reg << 3;
6777 inst.instruction |= inst.operands[1].imm << 6;
6778}
90e4755a 6779
c19d1205
ZW
6780static void
6781do_t_ldstd (void)
6782{
6783 if (!inst.operands[1].present)
b99bd4ef 6784 {
c19d1205
ZW
6785 inst.operands[1].reg = inst.operands[0].reg + 1;
6786 constraint (inst.operands[0].reg == REG_LR,
6787 _("r14 not allowed here"));
b99bd4ef 6788 }
c19d1205
ZW
6789 inst.instruction |= inst.operands[0].reg << 12;
6790 inst.instruction |= inst.operands[1].reg << 8;
6791 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
6792
b99bd4ef
NC
6793}
6794
c19d1205
ZW
6795static void
6796do_t_ldstt (void)
6797{
6798 inst.instruction |= inst.operands[0].reg << 12;
6799 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
6800}
a737bd4d 6801
b99bd4ef 6802static void
c19d1205 6803do_t_mla (void)
b99bd4ef 6804{
c19d1205
ZW
6805 inst.instruction |= inst.operands[0].reg << 8;
6806 inst.instruction |= inst.operands[1].reg << 16;
6807 inst.instruction |= inst.operands[2].reg;
6808 inst.instruction |= inst.operands[3].reg << 12;
6809}
b99bd4ef 6810
c19d1205
ZW
6811static void
6812do_t_mlal (void)
6813{
6814 inst.instruction |= inst.operands[0].reg << 12;
6815 inst.instruction |= inst.operands[1].reg << 8;
6816 inst.instruction |= inst.operands[2].reg << 16;
6817 inst.instruction |= inst.operands[3].reg;
6818}
b99bd4ef 6819
c19d1205
ZW
6820static void
6821do_t_mov_cmp (void)
6822{
6823 if (unified_syntax)
b99bd4ef 6824 {
c19d1205
ZW
6825 int r0off = (inst.instruction == T_MNEM_mov
6826 || inst.instruction == T_MNEM_movs) ? 8 : 16;
0110f2b8 6827 unsigned long opcode;
3d388997
PB
6828 bfd_boolean narrow;
6829 bfd_boolean low_regs;
6830
6831 low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7);
0110f2b8 6832 opcode = inst.instruction;
3d388997 6833 if (current_it_mask)
0110f2b8 6834 narrow = opcode != T_MNEM_movs;
3d388997 6835 else
0110f2b8 6836 narrow = opcode != T_MNEM_movs || low_regs;
3d388997
PB
6837 if (inst.size_req == 4
6838 || inst.operands[1].shifted)
6839 narrow = FALSE;
6840
c19d1205
ZW
6841 if (!inst.operands[1].isreg)
6842 {
0110f2b8
PB
6843 /* Immediate operand. */
6844 if (current_it_mask == 0 && opcode == T_MNEM_mov)
6845 narrow = 0;
6846 if (low_regs && narrow)
6847 {
6848 inst.instruction = THUMB_OP16 (opcode);
6849 inst.instruction |= inst.operands[0].reg << 8;
6850 if (inst.size_req == 2)
6851 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
6852 else
6853 inst.relax = opcode;
6854 }
6855 else
6856 {
6857 inst.instruction = THUMB_OP32 (inst.instruction);
6858 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6859 inst.instruction |= inst.operands[0].reg << r0off;
6860 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6861 }
c19d1205 6862 }
3d388997 6863 else if (!narrow)
c19d1205
ZW
6864 {
6865 inst.instruction = THUMB_OP32 (inst.instruction);
6866 inst.instruction |= inst.operands[0].reg << r0off;
6867 encode_thumb32_shifted_operand (1);
6868 }
6869 else
6870 switch (inst.instruction)
6871 {
6872 case T_MNEM_mov:
6873 inst.instruction = T_OPCODE_MOV_HR;
6874 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6875 inst.instruction |= (inst.operands[0].reg & 0x7);
6876 inst.instruction |= inst.operands[1].reg << 3;
6877 break;
b99bd4ef 6878
c19d1205
ZW
6879 case T_MNEM_movs:
6880 /* We know we have low registers at this point.
6881 Generate ADD Rd, Rs, #0. */
6882 inst.instruction = T_OPCODE_ADD_I3;
6883 inst.instruction |= inst.operands[0].reg;
6884 inst.instruction |= inst.operands[1].reg << 3;
6885 break;
6886
6887 case T_MNEM_cmp:
3d388997 6888 if (low_regs)
c19d1205
ZW
6889 {
6890 inst.instruction = T_OPCODE_CMP_LR;
6891 inst.instruction |= inst.operands[0].reg;
6892 inst.instruction |= inst.operands[1].reg << 3;
6893 }
6894 else
6895 {
6896 inst.instruction = T_OPCODE_CMP_HR;
6897 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6898 inst.instruction |= (inst.operands[0].reg & 0x7);
6899 inst.instruction |= inst.operands[1].reg << 3;
6900 }
6901 break;
6902 }
b99bd4ef
NC
6903 return;
6904 }
6905
c19d1205
ZW
6906 inst.instruction = THUMB_OP16 (inst.instruction);
6907 if (inst.operands[1].isreg)
b99bd4ef 6908 {
c19d1205 6909 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
b99bd4ef 6910 {
c19d1205
ZW
6911 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
6912 since a MOV instruction produces unpredictable results. */
6913 if (inst.instruction == T_OPCODE_MOV_I8)
6914 inst.instruction = T_OPCODE_ADD_I3;
b99bd4ef 6915 else
c19d1205 6916 inst.instruction = T_OPCODE_CMP_LR;
b99bd4ef 6917
c19d1205
ZW
6918 inst.instruction |= inst.operands[0].reg;
6919 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC
6920 }
6921 else
6922 {
c19d1205
ZW
6923 if (inst.instruction == T_OPCODE_MOV_I8)
6924 inst.instruction = T_OPCODE_MOV_HR;
6925 else
6926 inst.instruction = T_OPCODE_CMP_HR;
6927 do_t_cpy ();
b99bd4ef
NC
6928 }
6929 }
c19d1205 6930 else
b99bd4ef 6931 {
c19d1205
ZW
6932 constraint (inst.operands[0].reg > 7,
6933 _("only lo regs allowed with immediate"));
6934 inst.instruction |= inst.operands[0].reg << 8;
6935 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
6936 }
6937}
b99bd4ef 6938
c19d1205
ZW
6939static void
6940do_t_mov16 (void)
6941{
6942 inst.instruction |= inst.operands[0].reg << 8;
6943 inst.instruction |= (inst.operands[1].imm & 0xf000) << 4;
6944 inst.instruction |= (inst.operands[1].imm & 0x0800) << 15;
6945 inst.instruction |= (inst.operands[1].imm & 0x0700) << 4;
6946 inst.instruction |= (inst.operands[1].imm & 0x00ff);
6947}
b99bd4ef 6948
c19d1205
ZW
6949static void
6950do_t_mvn_tst (void)
6951{
6952 if (unified_syntax)
6953 {
6954 int r0off = (inst.instruction == T_MNEM_mvn
6955 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
3d388997
PB
6956 bfd_boolean narrow;
6957
6958 if (inst.size_req == 4
6959 || inst.instruction > 0xffff
6960 || inst.operands[1].shifted
6961 || inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
6962 narrow = FALSE;
6963 else if (inst.instruction == T_MNEM_cmn)
6964 narrow = TRUE;
6965 else if (THUMB_SETS_FLAGS (inst.instruction))
6966 narrow = (current_it_mask == 0);
6967 else
6968 narrow = (current_it_mask != 0);
6969
c19d1205 6970 if (!inst.operands[1].isreg)
b99bd4ef 6971 {
c19d1205
ZW
6972 /* For an immediate, we always generate a 32-bit opcode;
6973 section relaxation will shrink it later if possible. */
6974 if (inst.instruction < 0xffff)
6975 inst.instruction = THUMB_OP32 (inst.instruction);
6976 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6977 inst.instruction |= inst.operands[0].reg << r0off;
6978 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 6979 }
c19d1205 6980 else
b99bd4ef 6981 {
c19d1205 6982 /* See if we can do this with a 16-bit instruction. */
3d388997 6983 if (narrow)
b99bd4ef 6984 {
c19d1205
ZW
6985 inst.instruction = THUMB_OP16 (inst.instruction);
6986 inst.instruction |= inst.operands[0].reg;
6987 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef 6988 }
c19d1205 6989 else
b99bd4ef 6990 {
c19d1205
ZW
6991 constraint (inst.operands[1].shifted
6992 && inst.operands[1].immisreg,
6993 _("shift must be constant"));
6994 if (inst.instruction < 0xffff)
6995 inst.instruction = THUMB_OP32 (inst.instruction);
6996 inst.instruction |= inst.operands[0].reg << r0off;
6997 encode_thumb32_shifted_operand (1);
b99bd4ef 6998 }
b99bd4ef
NC
6999 }
7000 }
7001 else
7002 {
c19d1205
ZW
7003 constraint (inst.instruction > 0xffff
7004 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
7005 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
7006 _("unshifted register required"));
7007 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
7008 BAD_HIREG);
b99bd4ef 7009
c19d1205
ZW
7010 inst.instruction = THUMB_OP16 (inst.instruction);
7011 inst.instruction |= inst.operands[0].reg;
7012 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef 7013 }
b99bd4ef
NC
7014}
7015
b05fe5cf 7016static void
c19d1205 7017do_t_mrs (void)
b05fe5cf 7018{
c19d1205
ZW
7019 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7020 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
7021 != (PSR_c|PSR_f),
7022 _("'CPSR' or 'SPSR' expected"));
7023 inst.instruction |= inst.operands[0].reg << 8;
7024 inst.instruction |= (inst.operands[1].imm & SPSR_BIT) >> 2;
7025}
b05fe5cf 7026
c19d1205
ZW
7027static void
7028do_t_msr (void)
7029{
7030 constraint (!inst.operands[1].isreg,
7031 _("Thumb encoding does not support an immediate here"));
7032 inst.instruction |= (inst.operands[0].imm & SPSR_BIT) >> 2;
7033 inst.instruction |= (inst.operands[0].imm & ~SPSR_BIT) >> 8;
7034 inst.instruction |= inst.operands[1].reg << 16;
7035}
b05fe5cf 7036
c19d1205
ZW
7037static void
7038do_t_mul (void)
7039{
7040 if (!inst.operands[2].present)
7041 inst.operands[2].reg = inst.operands[0].reg;
b05fe5cf 7042
c19d1205
ZW
7043 /* There is no 32-bit MULS and no 16-bit MUL. */
7044 if (unified_syntax && inst.instruction == T_MNEM_mul)
b05fe5cf 7045 {
c19d1205
ZW
7046 inst.instruction = THUMB_OP32 (inst.instruction);
7047 inst.instruction |= inst.operands[0].reg << 8;
7048 inst.instruction |= inst.operands[1].reg << 16;
7049 inst.instruction |= inst.operands[2].reg << 0;
b05fe5cf 7050 }
c19d1205 7051 else
b05fe5cf 7052 {
c19d1205
ZW
7053 constraint (!unified_syntax
7054 && inst.instruction == T_MNEM_muls, BAD_THUMB32);
7055 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
7056 BAD_HIREG);
b05fe5cf 7057
c19d1205
ZW
7058 inst.instruction = THUMB_OP16 (inst.instruction);
7059 inst.instruction |= inst.operands[0].reg;
b05fe5cf 7060
c19d1205
ZW
7061 if (inst.operands[0].reg == inst.operands[1].reg)
7062 inst.instruction |= inst.operands[2].reg << 3;
7063 else if (inst.operands[0].reg == inst.operands[2].reg)
7064 inst.instruction |= inst.operands[1].reg << 3;
7065 else
7066 constraint (1, _("dest must overlap one source register"));
7067 }
7068}
b05fe5cf 7069
c19d1205
ZW
7070static void
7071do_t_mull (void)
7072{
7073 inst.instruction |= inst.operands[0].reg << 12;
7074 inst.instruction |= inst.operands[1].reg << 8;
7075 inst.instruction |= inst.operands[2].reg << 16;
7076 inst.instruction |= inst.operands[3].reg;
b05fe5cf 7077
c19d1205
ZW
7078 if (inst.operands[0].reg == inst.operands[1].reg)
7079 as_tsktsk (_("rdhi and rdlo must be different"));
7080}
b05fe5cf 7081
c19d1205
ZW
7082static void
7083do_t_nop (void)
7084{
7085 if (unified_syntax)
7086 {
7087 if (inst.size_req == 4 || inst.operands[0].imm > 15)
b05fe5cf 7088 {
c19d1205
ZW
7089 inst.instruction = THUMB_OP32 (inst.instruction);
7090 inst.instruction |= inst.operands[0].imm;
7091 }
7092 else
7093 {
7094 inst.instruction = THUMB_OP16 (inst.instruction);
7095 inst.instruction |= inst.operands[0].imm << 4;
7096 }
7097 }
7098 else
7099 {
7100 constraint (inst.operands[0].present,
7101 _("Thumb does not support NOP with hints"));
7102 inst.instruction = 0x46c0;
7103 }
7104}
b05fe5cf 7105
c19d1205
ZW
7106static void
7107do_t_neg (void)
7108{
7109 if (unified_syntax)
7110 {
3d388997
PB
7111 bfd_boolean narrow;
7112
7113 if (THUMB_SETS_FLAGS (inst.instruction))
7114 narrow = (current_it_mask == 0);
7115 else
7116 narrow = (current_it_mask != 0);
7117 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
7118 narrow = FALSE;
7119 if (inst.size_req == 4)
7120 narrow = FALSE;
7121
7122 if (!narrow)
c19d1205
ZW
7123 {
7124 inst.instruction = THUMB_OP32 (inst.instruction);
7125 inst.instruction |= inst.operands[0].reg << 8;
7126 inst.instruction |= inst.operands[1].reg << 16;
b05fe5cf
ZW
7127 }
7128 else
7129 {
c19d1205
ZW
7130 inst.instruction = THUMB_OP16 (inst.instruction);
7131 inst.instruction |= inst.operands[0].reg;
7132 inst.instruction |= inst.operands[1].reg << 3;
b05fe5cf
ZW
7133 }
7134 }
7135 else
7136 {
c19d1205
ZW
7137 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
7138 BAD_HIREG);
7139 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
7140
7141 inst.instruction = THUMB_OP16 (inst.instruction);
7142 inst.instruction |= inst.operands[0].reg;
7143 inst.instruction |= inst.operands[1].reg << 3;
7144 }
7145}
7146
7147static void
7148do_t_pkhbt (void)
7149{
7150 inst.instruction |= inst.operands[0].reg << 8;
7151 inst.instruction |= inst.operands[1].reg << 16;
7152 inst.instruction |= inst.operands[2].reg;
7153 if (inst.operands[3].present)
7154 {
7155 unsigned int val = inst.reloc.exp.X_add_number;
7156 constraint (inst.reloc.exp.X_op != O_constant,
7157 _("expression too complex"));
7158 inst.instruction |= (val & 0x1c) << 10;
7159 inst.instruction |= (val & 0x03) << 6;
b05fe5cf 7160 }
c19d1205 7161}
b05fe5cf 7162
c19d1205
ZW
7163static void
7164do_t_pkhtb (void)
7165{
7166 if (!inst.operands[3].present)
7167 inst.instruction &= ~0x00000020;
7168 do_t_pkhbt ();
b05fe5cf
ZW
7169}
7170
c19d1205
ZW
7171static void
7172do_t_pld (void)
7173{
7174 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
7175}
b05fe5cf 7176
c19d1205
ZW
7177static void
7178do_t_push_pop (void)
b99bd4ef 7179{
e9f89963
PB
7180 unsigned mask;
7181
c19d1205
ZW
7182 constraint (inst.operands[0].writeback,
7183 _("push/pop do not support {reglist}^"));
7184 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
7185 _("expression too complex"));
b99bd4ef 7186
e9f89963
PB
7187 mask = inst.operands[0].imm;
7188 if ((mask & ~0xff) == 0)
c19d1205
ZW
7189 inst.instruction = THUMB_OP16 (inst.instruction);
7190 else if ((inst.instruction == T_MNEM_push
e9f89963 7191 && (mask & ~0xff) == 1 << REG_LR)
c19d1205 7192 || (inst.instruction == T_MNEM_pop
e9f89963 7193 && (mask & ~0xff) == 1 << REG_PC))
b99bd4ef 7194 {
c19d1205
ZW
7195 inst.instruction = THUMB_OP16 (inst.instruction);
7196 inst.instruction |= THUMB_PP_PC_LR;
e9f89963 7197 mask &= 0xff;
c19d1205
ZW
7198 }
7199 else if (unified_syntax)
7200 {
e9f89963
PB
7201 if (mask & (1 << 13))
7202 inst.error = _("SP not allowed in register list");
c19d1205 7203 if (inst.instruction == T_MNEM_push)
b99bd4ef 7204 {
e9f89963
PB
7205 if (mask & (1 << 15))
7206 inst.error = _("PC not allowed in register list");
c19d1205
ZW
7207 }
7208 else
7209 {
e9f89963
PB
7210 if (mask & (1 << 14)
7211 && mask & (1 << 15))
7212 inst.error = _("LR and PC should not both be in register list");
c19d1205 7213 }
e9f89963
PB
7214 if ((mask & (mask - 1)) == 0)
7215 {
7216 /* Single register push/pop implemented as str/ldr. */
7217 if (inst.instruction == T_MNEM_push)
7218 inst.instruction = 0xf84d0d04; /* str reg, [sp, #-4]! */
7219 else
7220 inst.instruction = 0xf85d0b04; /* ldr reg, [sp], #4 */
7221 mask = ffs(mask) - 1;
7222 mask <<= 12;
7223 }
7224 else
7225 inst.instruction = THUMB_OP32 (inst.instruction);
c19d1205
ZW
7226 }
7227 else
7228 {
7229 inst.error = _("invalid register list to push/pop instruction");
7230 return;
7231 }
b99bd4ef 7232
e9f89963 7233 inst.instruction |= mask;
c19d1205 7234}
b99bd4ef 7235
c19d1205
ZW
7236static void
7237do_t_rbit (void)
7238{
7239 inst.instruction |= inst.operands[0].reg << 8;
7240 inst.instruction |= inst.operands[1].reg << 16;
7241}
b99bd4ef 7242
c19d1205
ZW
7243static void
7244do_t_rev (void)
7245{
7246 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
7247 && inst.size_req != 4)
7248 {
7249 inst.instruction = THUMB_OP16 (inst.instruction);
7250 inst.instruction |= inst.operands[0].reg;
7251 inst.instruction |= inst.operands[1].reg << 3;
7252 }
7253 else if (unified_syntax)
7254 {
7255 inst.instruction = THUMB_OP32 (inst.instruction);
7256 inst.instruction |= inst.operands[0].reg << 8;
7257 inst.instruction |= inst.operands[1].reg << 16;
7258 inst.instruction |= inst.operands[1].reg;
7259 }
7260 else
7261 inst.error = BAD_HIREG;
7262}
b99bd4ef 7263
c19d1205
ZW
7264static void
7265do_t_rsb (void)
7266{
7267 int Rd, Rs;
b99bd4ef 7268
c19d1205
ZW
7269 Rd = inst.operands[0].reg;
7270 Rs = (inst.operands[1].present
7271 ? inst.operands[1].reg /* Rd, Rs, foo */
7272 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
b99bd4ef 7273
c19d1205
ZW
7274 inst.instruction |= Rd << 8;
7275 inst.instruction |= Rs << 16;
7276 if (!inst.operands[2].isreg)
7277 {
7278 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
7279 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
7280 }
7281 else
7282 encode_thumb32_shifted_operand (2);
7283}
b99bd4ef 7284
c19d1205
ZW
7285static void
7286do_t_setend (void)
7287{
7288 if (inst.operands[0].imm)
7289 inst.instruction |= 0x8;
7290}
b99bd4ef 7291
c19d1205
ZW
7292static void
7293do_t_shift (void)
7294{
7295 if (!inst.operands[1].present)
7296 inst.operands[1].reg = inst.operands[0].reg;
7297
7298 if (unified_syntax)
7299 {
3d388997
PB
7300 bfd_boolean narrow;
7301 int shift_kind;
7302
7303 switch (inst.instruction)
7304 {
7305 case T_MNEM_asr:
7306 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
7307 case T_MNEM_lsl:
7308 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
7309 case T_MNEM_lsr:
7310 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
7311 case T_MNEM_ror:
7312 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
7313 default: abort ();
7314 }
7315
7316 if (THUMB_SETS_FLAGS (inst.instruction))
7317 narrow = (current_it_mask == 0);
7318 else
7319 narrow = (current_it_mask != 0);
7320 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
7321 narrow = FALSE;
7322 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
7323 narrow = FALSE;
7324 if (inst.operands[2].isreg
7325 && (inst.operands[1].reg != inst.operands[0].reg
7326 || inst.operands[2].reg > 7))
7327 narrow = FALSE;
7328 if (inst.size_req == 4)
7329 narrow = FALSE;
7330
7331 if (!narrow)
c19d1205
ZW
7332 {
7333 if (inst.operands[2].isreg)
b99bd4ef 7334 {
c19d1205
ZW
7335 inst.instruction = THUMB_OP32 (inst.instruction);
7336 inst.instruction |= inst.operands[0].reg << 8;
7337 inst.instruction |= inst.operands[1].reg << 16;
7338 inst.instruction |= inst.operands[2].reg;
7339 }
7340 else
7341 {
7342 inst.operands[1].shifted = 1;
3d388997 7343 inst.operands[1].shift_kind = shift_kind;
c19d1205
ZW
7344 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
7345 ? T_MNEM_movs : T_MNEM_mov);
7346 inst.instruction |= inst.operands[0].reg << 8;
7347 encode_thumb32_shifted_operand (1);
7348 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
7349 inst.reloc.type = BFD_RELOC_UNUSED;
b99bd4ef
NC
7350 }
7351 }
7352 else
7353 {
c19d1205 7354 if (inst.operands[2].isreg)
b99bd4ef 7355 {
3d388997 7356 switch (shift_kind)
b99bd4ef 7357 {
3d388997
PB
7358 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
7359 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
7360 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
7361 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
c19d1205 7362 default: abort ();
b99bd4ef 7363 }
c19d1205
ZW
7364
7365 inst.instruction |= inst.operands[0].reg;
7366 inst.instruction |= inst.operands[2].reg << 3;
b99bd4ef
NC
7367 }
7368 else
7369 {
3d388997 7370 switch (shift_kind)
b99bd4ef 7371 {
3d388997
PB
7372 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
7373 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
7374 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
c19d1205 7375 default: abort ();
b99bd4ef 7376 }
c19d1205
ZW
7377 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7378 inst.instruction |= inst.operands[0].reg;
7379 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC
7380 }
7381 }
c19d1205
ZW
7382 }
7383 else
7384 {
7385 constraint (inst.operands[0].reg > 7
7386 || inst.operands[1].reg > 7, BAD_HIREG);
7387 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
b99bd4ef 7388
c19d1205
ZW
7389 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
7390 {
7391 constraint (inst.operands[2].reg > 7, BAD_HIREG);
7392 constraint (inst.operands[0].reg != inst.operands[1].reg,
7393 _("source1 and dest must be same register"));
b99bd4ef 7394
c19d1205
ZW
7395 switch (inst.instruction)
7396 {
7397 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
7398 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
7399 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
7400 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
7401 default: abort ();
7402 }
7403
7404 inst.instruction |= inst.operands[0].reg;
7405 inst.instruction |= inst.operands[2].reg << 3;
7406 }
7407 else
b99bd4ef 7408 {
c19d1205
ZW
7409 switch (inst.instruction)
7410 {
7411 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
7412 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
7413 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
7414 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
7415 default: abort ();
7416 }
7417 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7418 inst.instruction |= inst.operands[0].reg;
7419 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC
7420 }
7421 }
b99bd4ef
NC
7422}
7423
7424static void
c19d1205 7425do_t_simd (void)
b99bd4ef 7426{
c19d1205
ZW
7427 inst.instruction |= inst.operands[0].reg << 8;
7428 inst.instruction |= inst.operands[1].reg << 16;
7429 inst.instruction |= inst.operands[2].reg;
7430}
b99bd4ef 7431
c19d1205 7432static void
3eb17e6b 7433do_t_smc (void)
c19d1205
ZW
7434{
7435 unsigned int value = inst.reloc.exp.X_add_number;
7436 constraint (inst.reloc.exp.X_op != O_constant,
7437 _("expression too complex"));
7438 inst.reloc.type = BFD_RELOC_UNUSED;
7439 inst.instruction |= (value & 0xf000) >> 12;
7440 inst.instruction |= (value & 0x0ff0);
7441 inst.instruction |= (value & 0x000f) << 16;
7442}
b99bd4ef 7443
c19d1205
ZW
7444static void
7445do_t_ssat (void)
7446{
7447 inst.instruction |= inst.operands[0].reg << 8;
7448 inst.instruction |= inst.operands[1].imm - 1;
7449 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef 7450
c19d1205 7451 if (inst.operands[3].present)
b99bd4ef 7452 {
c19d1205
ZW
7453 constraint (inst.reloc.exp.X_op != O_constant,
7454 _("expression too complex"));
b99bd4ef 7455
c19d1205 7456 if (inst.reloc.exp.X_add_number != 0)
6189168b 7457 {
c19d1205
ZW
7458 if (inst.operands[3].shift_kind == SHIFT_ASR)
7459 inst.instruction |= 0x00200000; /* sh bit */
7460 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7461 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
6189168b 7462 }
c19d1205 7463 inst.reloc.type = BFD_RELOC_UNUSED;
6189168b 7464 }
b99bd4ef
NC
7465}
7466
0dd132b6 7467static void
c19d1205 7468do_t_ssat16 (void)
0dd132b6 7469{
c19d1205
ZW
7470 inst.instruction |= inst.operands[0].reg << 8;
7471 inst.instruction |= inst.operands[1].imm - 1;
7472 inst.instruction |= inst.operands[2].reg << 16;
7473}
0dd132b6 7474
c19d1205
ZW
7475static void
7476do_t_strex (void)
7477{
7478 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
7479 || inst.operands[2].postind || inst.operands[2].writeback
7480 || inst.operands[2].immisreg || inst.operands[2].shifted
7481 || inst.operands[2].negative,
7482 _("instruction does not accept this addressing mode"));
0dd132b6 7483
c19d1205
ZW
7484 inst.instruction |= inst.operands[0].reg << 8;
7485 inst.instruction |= inst.operands[1].reg << 12;
7486 inst.instruction |= inst.operands[2].reg << 16;
7487 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
0dd132b6
NC
7488}
7489
b99bd4ef 7490static void
c19d1205 7491do_t_strexd (void)
b99bd4ef 7492{
c19d1205
ZW
7493 if (!inst.operands[2].present)
7494 inst.operands[2].reg = inst.operands[1].reg + 1;
b99bd4ef 7495
c19d1205
ZW
7496 constraint (inst.operands[0].reg == inst.operands[1].reg
7497 || inst.operands[0].reg == inst.operands[2].reg
7498 || inst.operands[0].reg == inst.operands[3].reg
7499 || inst.operands[1].reg == inst.operands[2].reg,
7500 BAD_OVERLAP);
b99bd4ef 7501
c19d1205
ZW
7502 inst.instruction |= inst.operands[0].reg;
7503 inst.instruction |= inst.operands[1].reg << 12;
7504 inst.instruction |= inst.operands[2].reg << 8;
7505 inst.instruction |= inst.operands[3].reg << 16;
b99bd4ef
NC
7506}
7507
7508static void
c19d1205 7509do_t_sxtah (void)
b99bd4ef 7510{
c19d1205
ZW
7511 inst.instruction |= inst.operands[0].reg << 8;
7512 inst.instruction |= inst.operands[1].reg << 16;
7513 inst.instruction |= inst.operands[2].reg;
7514 inst.instruction |= inst.operands[3].imm << 4;
7515}
b99bd4ef 7516
c19d1205
ZW
7517static void
7518do_t_sxth (void)
7519{
7520 if (inst.instruction <= 0xffff && inst.size_req != 4
7521 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
7522 && (!inst.operands[2].present || inst.operands[2].imm == 0))
b99bd4ef 7523 {
c19d1205
ZW
7524 inst.instruction = THUMB_OP16 (inst.instruction);
7525 inst.instruction |= inst.operands[0].reg;
7526 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef 7527 }
c19d1205 7528 else if (unified_syntax)
b99bd4ef 7529 {
c19d1205
ZW
7530 if (inst.instruction <= 0xffff)
7531 inst.instruction = THUMB_OP32 (inst.instruction);
7532 inst.instruction |= inst.operands[0].reg << 8;
7533 inst.instruction |= inst.operands[1].reg;
7534 inst.instruction |= inst.operands[2].imm << 4;
b99bd4ef 7535 }
c19d1205 7536 else
b99bd4ef 7537 {
c19d1205
ZW
7538 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
7539 _("Thumb encoding does not support rotation"));
7540 constraint (1, BAD_HIREG);
b99bd4ef 7541 }
c19d1205 7542}
b99bd4ef 7543
c19d1205
ZW
7544static void
7545do_t_swi (void)
7546{
7547 inst.reloc.type = BFD_RELOC_ARM_SWI;
7548}
b99bd4ef 7549
92e90b6e
PB
7550static void
7551do_t_tb (void)
7552{
7553 int half;
7554
7555 half = (inst.instruction & 0x10) != 0;
7556 constraint (inst.operands[0].imm == 15,
7557 _("PC is not a valid index register"));
7558 constraint (!half && inst.operands[0].shifted,
7559 _("instruction does not allow shifted index"));
7560 constraint (half && !inst.operands[0].shifted,
7561 _("instruction requires shifted index"));
7562 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm;
7563}
7564
c19d1205
ZW
7565static void
7566do_t_usat (void)
7567{
7568 inst.instruction |= inst.operands[0].reg << 8;
7569 inst.instruction |= inst.operands[1].imm;
7570 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef 7571
c19d1205 7572 if (inst.operands[3].present)
b99bd4ef 7573 {
c19d1205
ZW
7574 constraint (inst.reloc.exp.X_op != O_constant,
7575 _("expression too complex"));
7576 if (inst.reloc.exp.X_add_number != 0)
7577 {
7578 if (inst.operands[3].shift_kind == SHIFT_ASR)
7579 inst.instruction |= 0x00200000; /* sh bit */
b99bd4ef 7580
c19d1205
ZW
7581 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7582 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
7583 }
7584 inst.reloc.type = BFD_RELOC_UNUSED;
b99bd4ef 7585 }
b99bd4ef
NC
7586}
7587
7588static void
c19d1205 7589do_t_usat16 (void)
b99bd4ef 7590{
c19d1205
ZW
7591 inst.instruction |= inst.operands[0].reg << 8;
7592 inst.instruction |= inst.operands[1].imm;
7593 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef 7594}
c19d1205
ZW
7595\f
7596/* Overall per-instruction processing. */
7597
7598/* We need to be able to fix up arbitrary expressions in some statements.
7599 This is so that we can handle symbols that are an arbitrary distance from
7600 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
7601 which returns part of an address in a form which will be valid for
7602 a data instruction. We do this by pushing the expression into a symbol
7603 in the expr_section, and creating a fix for that. */
b99bd4ef
NC
7604
7605static void
c19d1205
ZW
7606fix_new_arm (fragS * frag,
7607 int where,
7608 short int size,
7609 expressionS * exp,
7610 int pc_rel,
7611 int reloc)
b99bd4ef 7612{
c19d1205 7613 fixS * new_fix;
b99bd4ef 7614
c19d1205 7615 switch (exp->X_op)
b99bd4ef 7616 {
c19d1205
ZW
7617 case O_constant:
7618 case O_symbol:
7619 case O_add:
7620 case O_subtract:
7621 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
7622 break;
b99bd4ef 7623
c19d1205
ZW
7624 default:
7625 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
7626 pc_rel, reloc);
7627 break;
b99bd4ef
NC
7628 }
7629
c19d1205
ZW
7630 /* Mark whether the fix is to a THUMB instruction, or an ARM
7631 instruction. */
adbaf948 7632 new_fix->tc_fix_data = thumb_mode;
b99bd4ef
NC
7633}
7634
0110f2b8
PB
7635/* Create a frg for an instruction requiring relaxation. */
7636static void
7637output_relax_insn (void)
7638{
7639 char * to;
7640 symbolS *sym;
7641 int offset;
7642
7643 switch (inst.reloc.exp.X_op)
7644 {
7645 case O_symbol:
7646 sym = inst.reloc.exp.X_add_symbol;
7647 offset = inst.reloc.exp.X_add_number;
7648 break;
7649 case O_constant:
7650 sym = NULL;
7651 offset = inst.reloc.exp.X_add_number;
7652 break;
7653 default:
7654 sym = make_expr_symbol (&inst.reloc.exp);
7655 offset = 0;
7656 break;
7657 }
7658 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
7659 inst.relax, sym, offset, NULL/*offset, opcode*/);
7660 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
7661
7662#ifdef OBJ_ELF
7663 dwarf2_emit_insn (INSN_SIZE);
7664#endif
7665}
7666
7667/* Write a 32-bit thumb instruction to buf. */
7668static void
7669put_thumb32_insn (char * buf, unsigned long insn)
7670{
7671 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
7672 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
7673}
7674
b99bd4ef 7675static void
c19d1205 7676output_inst (const char * str)
b99bd4ef 7677{
c19d1205 7678 char * to = NULL;
b99bd4ef 7679
c19d1205 7680 if (inst.error)
b99bd4ef 7681 {
c19d1205 7682 as_bad ("%s -- `%s'", inst.error, str);
b99bd4ef
NC
7683 return;
7684 }
0110f2b8
PB
7685 if (inst.relax) {
7686 output_relax_insn();
7687 return;
7688 }
c19d1205
ZW
7689 if (inst.size == 0)
7690 return;
b99bd4ef 7691
c19d1205
ZW
7692 to = frag_more (inst.size);
7693
7694 if (thumb_mode && (inst.size > THUMB_SIZE))
b99bd4ef 7695 {
c19d1205 7696 assert (inst.size == (2 * THUMB_SIZE));
0110f2b8 7697 put_thumb32_insn (to, inst.instruction);
b99bd4ef 7698 }
c19d1205 7699 else if (inst.size > INSN_SIZE)
b99bd4ef 7700 {
c19d1205
ZW
7701 assert (inst.size == (2 * INSN_SIZE));
7702 md_number_to_chars (to, inst.instruction, INSN_SIZE);
7703 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
b99bd4ef 7704 }
c19d1205
ZW
7705 else
7706 md_number_to_chars (to, inst.instruction, inst.size);
b99bd4ef 7707
c19d1205
ZW
7708 if (inst.reloc.type != BFD_RELOC_UNUSED)
7709 fix_new_arm (frag_now, to - frag_now->fr_literal,
7710 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
7711 inst.reloc.type);
b99bd4ef 7712
c19d1205
ZW
7713#ifdef OBJ_ELF
7714 dwarf2_emit_insn (inst.size);
7715#endif
7716}
b99bd4ef 7717
c19d1205
ZW
7718/* Tag values used in struct asm_opcode's tag field. */
7719enum opcode_tag
7720{
7721 OT_unconditional, /* Instruction cannot be conditionalized.
7722 The ARM condition field is still 0xE. */
7723 OT_unconditionalF, /* Instruction cannot be conditionalized
7724 and carries 0xF in its ARM condition field. */
7725 OT_csuffix, /* Instruction takes a conditional suffix. */
7726 OT_cinfix3, /* Instruction takes a conditional infix,
7727 beginning at character index 3. (In
7728 unified mode, it becomes a suffix.) */
e3cb604e
PB
7729 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
7730 character index 3, even in unified mode. Used for
7731 legacy instructions where suffix and infix forms
7732 may be ambiguous. */
c19d1205 7733 OT_csuf_or_in3, /* Instruction takes either a conditional
e3cb604e 7734 suffix or an infix at character index 3. */
c19d1205
ZW
7735 OT_odd_infix_unc, /* This is the unconditional variant of an
7736 instruction that takes a conditional infix
7737 at an unusual position. In unified mode,
7738 this variant will accept a suffix. */
7739 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
7740 are the conditional variants of instructions that
7741 take conditional infixes in unusual positions.
7742 The infix appears at character index
7743 (tag - OT_odd_infix_0). These are not accepted
7744 in unified mode. */
7745};
b99bd4ef 7746
c19d1205
ZW
7747/* Subroutine of md_assemble, responsible for looking up the primary
7748 opcode from the mnemonic the user wrote. STR points to the
7749 beginning of the mnemonic.
7750
7751 This is not simply a hash table lookup, because of conditional
7752 variants. Most instructions have conditional variants, which are
7753 expressed with a _conditional affix_ to the mnemonic. If we were
7754 to encode each conditional variant as a literal string in the opcode
7755 table, it would have approximately 20,000 entries.
7756
7757 Most mnemonics take this affix as a suffix, and in unified syntax,
7758 'most' is upgraded to 'all'. However, in the divided syntax, some
7759 instructions take the affix as an infix, notably the s-variants of
7760 the arithmetic instructions. Of those instructions, all but six
7761 have the infix appear after the third character of the mnemonic.
7762
7763 Accordingly, the algorithm for looking up primary opcodes given
7764 an identifier is:
7765
7766 1. Look up the identifier in the opcode table.
7767 If we find a match, go to step U.
7768
7769 2. Look up the last two characters of the identifier in the
7770 conditions table. If we find a match, look up the first N-2
7771 characters of the identifier in the opcode table. If we
7772 find a match, go to step CE.
7773
7774 3. Look up the fourth and fifth characters of the identifier in
7775 the conditions table. If we find a match, extract those
7776 characters from the identifier, and look up the remaining
7777 characters in the opcode table. If we find a match, go
7778 to step CM.
7779
7780 4. Fail.
7781
7782 U. Examine the tag field of the opcode structure, in case this is
7783 one of the six instructions with its conditional infix in an
7784 unusual place. If it is, the tag tells us where to find the
7785 infix; look it up in the conditions table and set inst.cond
7786 accordingly. Otherwise, this is an unconditional instruction.
7787 Again set inst.cond accordingly. Return the opcode structure.
7788
7789 CE. Examine the tag field to make sure this is an instruction that
7790 should receive a conditional suffix. If it is not, fail.
7791 Otherwise, set inst.cond from the suffix we already looked up,
7792 and return the opcode structure.
7793
7794 CM. Examine the tag field to make sure this is an instruction that
7795 should receive a conditional infix after the third character.
7796 If it is not, fail. Otherwise, undo the edits to the current
7797 line of input and proceed as for case CE. */
7798
7799static const struct asm_opcode *
7800opcode_lookup (char **str)
7801{
7802 char *end, *base;
7803 char *affix;
7804 const struct asm_opcode *opcode;
7805 const struct asm_cond *cond;
e3cb604e 7806 char save[2];
c19d1205
ZW
7807
7808 /* Scan up to the end of the mnemonic, which must end in white space,
7809 '.' (in unified mode only), or end of string. */
7810 for (base = end = *str; *end != '\0'; end++)
7811 if (*end == ' ' || (unified_syntax && *end == '.'))
7812 break;
b99bd4ef 7813
c19d1205
ZW
7814 if (end == base)
7815 return 0;
b99bd4ef 7816
c19d1205
ZW
7817 /* Handle a possible width suffix. */
7818 if (end[0] == '.')
b99bd4ef 7819 {
c19d1205
ZW
7820 if (end[1] == 'w' && (end[2] == ' ' || end[2] == '\0'))
7821 inst.size_req = 4;
7822 else if (end[1] == 'n' && (end[2] == ' ' || end[2] == '\0'))
7823 inst.size_req = 2;
7824 else
7825 return 0;
b99bd4ef 7826
c19d1205 7827 *str = end + 2;
b99bd4ef 7828 }
c19d1205
ZW
7829 else
7830 *str = end;
b99bd4ef 7831
c19d1205
ZW
7832 /* Look for unaffixed or special-case affixed mnemonic. */
7833 opcode = hash_find_n (arm_ops_hsh, base, end - base);
7834 if (opcode)
b99bd4ef 7835 {
c19d1205
ZW
7836 /* step U */
7837 if (opcode->tag < OT_odd_infix_0)
b99bd4ef 7838 {
c19d1205
ZW
7839 inst.cond = COND_ALWAYS;
7840 return opcode;
b99bd4ef 7841 }
b99bd4ef 7842
c19d1205
ZW
7843 if (unified_syntax)
7844 as_warn (_("conditional infixes are deprecated in unified syntax"));
7845 affix = base + (opcode->tag - OT_odd_infix_0);
7846 cond = hash_find_n (arm_cond_hsh, affix, 2);
7847 assert (cond);
b99bd4ef 7848
c19d1205
ZW
7849 inst.cond = cond->value;
7850 return opcode;
7851 }
b99bd4ef 7852
c19d1205
ZW
7853 /* Cannot have a conditional suffix on a mnemonic of less than two
7854 characters. */
7855 if (end - base < 3)
7856 return 0;
b99bd4ef 7857
c19d1205
ZW
7858 /* Look for suffixed mnemonic. */
7859 affix = end - 2;
7860 cond = hash_find_n (arm_cond_hsh, affix, 2);
7861 opcode = hash_find_n (arm_ops_hsh, base, affix - base);
7862 if (opcode && cond)
7863 {
7864 /* step CE */
7865 switch (opcode->tag)
7866 {
e3cb604e
PB
7867 case OT_cinfix3_legacy:
7868 /* Ignore conditional suffixes matched on infix only mnemonics. */
7869 break;
7870
c19d1205
ZW
7871 case OT_cinfix3:
7872 case OT_odd_infix_unc:
7873 if (!unified_syntax)
e3cb604e 7874 return 0;
c19d1205
ZW
7875 /* else fall through */
7876
7877 case OT_csuffix:
7878 case OT_csuf_or_in3:
7879 inst.cond = cond->value;
7880 return opcode;
7881
7882 case OT_unconditional:
7883 case OT_unconditionalF:
7884 /* delayed diagnostic */
7885 inst.error = BAD_COND;
7886 inst.cond = COND_ALWAYS;
7887 return opcode;
b99bd4ef 7888
c19d1205
ZW
7889 default:
7890 return 0;
7891 }
7892 }
b99bd4ef 7893
c19d1205
ZW
7894 /* Cannot have a usual-position infix on a mnemonic of less than
7895 six characters (five would be a suffix). */
7896 if (end - base < 6)
7897 return 0;
b99bd4ef 7898
c19d1205
ZW
7899 /* Look for infixed mnemonic in the usual position. */
7900 affix = base + 3;
7901 cond = hash_find_n (arm_cond_hsh, affix, 2);
e3cb604e
PB
7902 if (!cond)
7903 return 0;
7904
7905 memcpy (save, affix, 2);
7906 memmove (affix, affix + 2, (end - affix) - 2);
7907 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2);
7908 memmove (affix + 2, affix, (end - affix) - 2);
7909 memcpy (affix, save, 2);
7910
7911 if (opcode && (opcode->tag == OT_cinfix3 || opcode->tag == OT_csuf_or_in3
7912 || opcode->tag == OT_cinfix3_legacy))
b99bd4ef 7913 {
c19d1205 7914 /* step CM */
e3cb604e 7915 if (unified_syntax && opcode->tag == OT_cinfix3)
c19d1205
ZW
7916 as_warn (_("conditional infixes are deprecated in unified syntax"));
7917
7918 inst.cond = cond->value;
7919 return opcode;
b99bd4ef
NC
7920 }
7921
c19d1205 7922 return 0;
b99bd4ef
NC
7923}
7924
c19d1205
ZW
7925void
7926md_assemble (char *str)
b99bd4ef 7927{
c19d1205
ZW
7928 char *p = str;
7929 const struct asm_opcode * opcode;
b99bd4ef 7930
c19d1205
ZW
7931 /* Align the previous label if needed. */
7932 if (last_label_seen != NULL)
b99bd4ef 7933 {
c19d1205
ZW
7934 symbol_set_frag (last_label_seen, frag_now);
7935 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
7936 S_SET_SEGMENT (last_label_seen, now_seg);
b99bd4ef
NC
7937 }
7938
c19d1205
ZW
7939 memset (&inst, '\0', sizeof (inst));
7940 inst.reloc.type = BFD_RELOC_UNUSED;
b99bd4ef 7941
c19d1205
ZW
7942 opcode = opcode_lookup (&p);
7943 if (!opcode)
b99bd4ef 7944 {
c19d1205
ZW
7945 /* It wasn't an instruction, but it might be a register alias of
7946 the form alias .req reg. */
7947 if (!create_register_alias (str, p))
7948 as_bad (_("bad instruction `%s'"), str);
b99bd4ef 7949
b99bd4ef
NC
7950 return;
7951 }
7952
c19d1205 7953 if (thumb_mode)
b99bd4ef 7954 {
8f06b2d8
PB
7955 unsigned long variant;
7956
7957 variant = cpu_variant;
7958 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
7959 if ((variant & ARM_EXT_V6T2) == 0)
7960 variant &= ARM_ANY;
c19d1205 7961 /* Check that this instruction is supported for this CPU. */
8f06b2d8 7962 if (thumb_mode == 1 && (opcode->tvariant & variant) == 0)
b99bd4ef 7963 {
c19d1205 7964 as_bad (_("selected processor does not support `%s'"), str);
b99bd4ef
NC
7965 return;
7966 }
c19d1205
ZW
7967 if (inst.cond != COND_ALWAYS && !unified_syntax
7968 && opcode->tencode != do_t_branch)
b99bd4ef 7969 {
c19d1205 7970 as_bad (_("Thumb does not support conditional execution"));
b99bd4ef
NC
7971 return;
7972 }
7973
e27ec89e
PB
7974 /* Check conditional suffixes. */
7975 if (current_it_mask)
7976 {
7977 int cond;
7978 cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1;
7979 if (cond != inst.cond)
7980 {
7981 as_bad (_("incorrect condition in IT block"));
7982 return;
7983 }
7984 current_it_mask <<= 1;
7985 current_it_mask &= 0x1f;
7986 }
7987 else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch)
7988 {
7989 as_bad (_("thumb conditional instrunction not in IT block"));
7990 return;
7991 }
7992
c19d1205
ZW
7993 mapping_state (MAP_THUMB);
7994 inst.instruction = opcode->tvalue;
7995
7996 if (!parse_operands (p, opcode->operands))
7997 opcode->tencode ();
7998
e27ec89e
PB
7999 /* Clear current_it_mask at the end of an IT block. */
8000 if (current_it_mask == 0x10)
8001 current_it_mask = 0;
8002
0110f2b8 8003 if (!(inst.error || inst.relax))
b99bd4ef 8004 {
c19d1205
ZW
8005 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
8006 inst.size = (inst.instruction > 0xffff ? 4 : 2);
8007 if (inst.size_req && inst.size_req != inst.size)
b99bd4ef 8008 {
c19d1205 8009 as_bad (_("cannot honor width suffix -- `%s'"), str);
b99bd4ef
NC
8010 return;
8011 }
8012 }
c19d1205
ZW
8013 }
8014 else
8015 {
8016 /* Check that this instruction is supported for this CPU. */
8017 if ((opcode->avariant & cpu_variant) == 0)
b99bd4ef 8018 {
c19d1205
ZW
8019 as_bad (_("selected processor does not support `%s'"), str);
8020 return;
b99bd4ef 8021 }
c19d1205 8022 if (inst.size_req)
b99bd4ef 8023 {
c19d1205
ZW
8024 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
8025 return;
b99bd4ef
NC
8026 }
8027
c19d1205
ZW
8028 mapping_state (MAP_ARM);
8029 inst.instruction = opcode->avalue;
8030 if (opcode->tag == OT_unconditionalF)
8031 inst.instruction |= 0xF << 28;
8032 else
8033 inst.instruction |= inst.cond << 28;
8034 inst.size = INSN_SIZE;
8035 if (!parse_operands (p, opcode->operands))
8036 opcode->aencode ();
b99bd4ef 8037 }
c19d1205
ZW
8038 output_inst (str);
8039}
b99bd4ef 8040
c19d1205
ZW
8041/* Various frobbings of labels and their addresses. */
8042
8043void
8044arm_start_line_hook (void)
8045{
8046 last_label_seen = NULL;
b99bd4ef
NC
8047}
8048
c19d1205
ZW
8049void
8050arm_frob_label (symbolS * sym)
b99bd4ef 8051{
c19d1205 8052 last_label_seen = sym;
b99bd4ef 8053
c19d1205 8054 ARM_SET_THUMB (sym, thumb_mode);
b99bd4ef 8055
c19d1205
ZW
8056#if defined OBJ_COFF || defined OBJ_ELF
8057 ARM_SET_INTERWORK (sym, support_interwork);
8058#endif
b99bd4ef 8059
c19d1205
ZW
8060 /* Note - do not allow local symbols (.Lxxx) to be labeled
8061 as Thumb functions. This is because these labels, whilst
8062 they exist inside Thumb code, are not the entry points for
8063 possible ARM->Thumb calls. Also, these labels can be used
8064 as part of a computed goto or switch statement. eg gcc
8065 can generate code that looks like this:
b99bd4ef 8066
c19d1205
ZW
8067 ldr r2, [pc, .Laaa]
8068 lsl r3, r3, #2
8069 ldr r2, [r3, r2]
8070 mov pc, r2
b99bd4ef 8071
c19d1205
ZW
8072 .Lbbb: .word .Lxxx
8073 .Lccc: .word .Lyyy
8074 ..etc...
8075 .Laaa: .word Lbbb
b99bd4ef 8076
c19d1205
ZW
8077 The first instruction loads the address of the jump table.
8078 The second instruction converts a table index into a byte offset.
8079 The third instruction gets the jump address out of the table.
8080 The fourth instruction performs the jump.
b99bd4ef 8081
c19d1205
ZW
8082 If the address stored at .Laaa is that of a symbol which has the
8083 Thumb_Func bit set, then the linker will arrange for this address
8084 to have the bottom bit set, which in turn would mean that the
8085 address computation performed by the third instruction would end
8086 up with the bottom bit set. Since the ARM is capable of unaligned
8087 word loads, the instruction would then load the incorrect address
8088 out of the jump table, and chaos would ensue. */
8089 if (label_is_thumb_function_name
8090 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
8091 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
b99bd4ef 8092 {
c19d1205
ZW
8093 /* When the address of a Thumb function is taken the bottom
8094 bit of that address should be set. This will allow
8095 interworking between Arm and Thumb functions to work
8096 correctly. */
b99bd4ef 8097
c19d1205 8098 THUMB_SET_FUNC (sym, 1);
b99bd4ef 8099
c19d1205 8100 label_is_thumb_function_name = FALSE;
b99bd4ef 8101 }
07a53e5c
RH
8102
8103#ifdef OBJ_ELF
8104 dwarf2_emit_label (sym);
8105#endif
b99bd4ef
NC
8106}
8107
c19d1205
ZW
8108int
8109arm_data_in_code (void)
b99bd4ef 8110{
c19d1205 8111 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
b99bd4ef 8112 {
c19d1205
ZW
8113 *input_line_pointer = '/';
8114 input_line_pointer += 5;
8115 *input_line_pointer = 0;
8116 return 1;
b99bd4ef
NC
8117 }
8118
c19d1205 8119 return 0;
b99bd4ef
NC
8120}
8121
c19d1205
ZW
8122char *
8123arm_canonicalize_symbol_name (char * name)
b99bd4ef 8124{
c19d1205 8125 int len;
b99bd4ef 8126
c19d1205
ZW
8127 if (thumb_mode && (len = strlen (name)) > 5
8128 && streq (name + len - 5, "/data"))
8129 *(name + len - 5) = 0;
b99bd4ef 8130
c19d1205 8131 return name;
b99bd4ef 8132}
c19d1205
ZW
8133\f
8134/* Table of all register names defined by default. The user can
8135 define additional names with .req. Note that all register names
8136 should appear in both upper and lowercase variants. Some registers
8137 also have mixed-case names. */
b99bd4ef 8138
c19d1205
ZW
8139#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
8140#define REGNUM(p,n,t) REGDEF(p##n, n, t)
8141#define REGSET(p,t) \
8142 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8143 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8144 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8145 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7ed4c4c5 8146
c19d1205 8147static const struct reg_entry reg_names[] =
7ed4c4c5 8148{
c19d1205
ZW
8149 /* ARM integer registers. */
8150 REGSET(r, RN), REGSET(R, RN),
7ed4c4c5 8151
c19d1205
ZW
8152 /* ATPCS synonyms. */
8153 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
8154 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
8155 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
7ed4c4c5 8156
c19d1205
ZW
8157 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
8158 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
8159 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
7ed4c4c5 8160
c19d1205
ZW
8161 /* Well-known aliases. */
8162 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
8163 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
8164
8165 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
8166 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
8167
8168 /* Coprocessor numbers. */
8169 REGSET(p, CP), REGSET(P, CP),
8170
8171 /* Coprocessor register numbers. The "cr" variants are for backward
8172 compatibility. */
8173 REGSET(c, CN), REGSET(C, CN),
8174 REGSET(cr, CN), REGSET(CR, CN),
8175
8176 /* FPA registers. */
8177 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
8178 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
8179
8180 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
8181 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
8182
8183 /* VFP SP registers. */
8184 REGSET(s,VFS),
8185 REGNUM(s,16,VFS), REGNUM(s,17,VFS), REGNUM(s,18,VFS), REGNUM(s,19,VFS),
8186 REGNUM(s,20,VFS), REGNUM(s,21,VFS), REGNUM(s,22,VFS), REGNUM(s,23,VFS),
8187 REGNUM(s,24,VFS), REGNUM(s,25,VFS), REGNUM(s,26,VFS), REGNUM(s,27,VFS),
8188 REGNUM(s,28,VFS), REGNUM(s,29,VFS), REGNUM(s,30,VFS), REGNUM(s,31,VFS),
8189
8190 REGSET(S,VFS),
8191 REGNUM(S,16,VFS), REGNUM(S,17,VFS), REGNUM(S,18,VFS), REGNUM(S,19,VFS),
8192 REGNUM(S,20,VFS), REGNUM(S,21,VFS), REGNUM(S,22,VFS), REGNUM(S,23,VFS),
8193 REGNUM(S,24,VFS), REGNUM(S,25,VFS), REGNUM(S,26,VFS), REGNUM(S,27,VFS),
8194 REGNUM(S,28,VFS), REGNUM(S,29,VFS), REGNUM(S,30,VFS), REGNUM(S,31,VFS),
8195
8196 /* VFP DP Registers. */
8197 REGSET(d,VFD), REGSET(D,VFS),
8198
8199 /* VFP control registers. */
8200 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
8201 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
8202
8203 /* Maverick DSP coprocessor registers. */
8204 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
8205 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
8206
8207 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
8208 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
8209 REGDEF(dspsc,0,DSPSC),
8210
8211 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
8212 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
8213 REGDEF(DSPSC,0,DSPSC),
8214
8215 /* iWMMXt data registers - p0, c0-15. */
8216 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
8217
8218 /* iWMMXt control registers - p1, c0-3. */
8219 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
8220 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
8221 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
8222 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
8223
8224 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
8225 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
8226 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
8227 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
8228 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
8229
8230 /* XScale accumulator registers. */
8231 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
8232};
8233#undef REGDEF
8234#undef REGNUM
8235#undef REGSET
7ed4c4c5 8236
c19d1205
ZW
8237/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
8238 within psr_required_here. */
8239static const struct asm_psr psrs[] =
8240{
8241 /* Backward compatibility notation. Note that "all" is no longer
8242 truly all possible PSR bits. */
8243 {"all", PSR_c | PSR_f},
8244 {"flg", PSR_f},
8245 {"ctl", PSR_c},
8246
8247 /* Individual flags. */
8248 {"f", PSR_f},
8249 {"c", PSR_c},
8250 {"x", PSR_x},
8251 {"s", PSR_s},
8252 /* Combinations of flags. */
8253 {"fs", PSR_f | PSR_s},
8254 {"fx", PSR_f | PSR_x},
8255 {"fc", PSR_f | PSR_c},
8256 {"sf", PSR_s | PSR_f},
8257 {"sx", PSR_s | PSR_x},
8258 {"sc", PSR_s | PSR_c},
8259 {"xf", PSR_x | PSR_f},
8260 {"xs", PSR_x | PSR_s},
8261 {"xc", PSR_x | PSR_c},
8262 {"cf", PSR_c | PSR_f},
8263 {"cs", PSR_c | PSR_s},
8264 {"cx", PSR_c | PSR_x},
8265 {"fsx", PSR_f | PSR_s | PSR_x},
8266 {"fsc", PSR_f | PSR_s | PSR_c},
8267 {"fxs", PSR_f | PSR_x | PSR_s},
8268 {"fxc", PSR_f | PSR_x | PSR_c},
8269 {"fcs", PSR_f | PSR_c | PSR_s},
8270 {"fcx", PSR_f | PSR_c | PSR_x},
8271 {"sfx", PSR_s | PSR_f | PSR_x},
8272 {"sfc", PSR_s | PSR_f | PSR_c},
8273 {"sxf", PSR_s | PSR_x | PSR_f},
8274 {"sxc", PSR_s | PSR_x | PSR_c},
8275 {"scf", PSR_s | PSR_c | PSR_f},
8276 {"scx", PSR_s | PSR_c | PSR_x},
8277 {"xfs", PSR_x | PSR_f | PSR_s},
8278 {"xfc", PSR_x | PSR_f | PSR_c},
8279 {"xsf", PSR_x | PSR_s | PSR_f},
8280 {"xsc", PSR_x | PSR_s | PSR_c},
8281 {"xcf", PSR_x | PSR_c | PSR_f},
8282 {"xcs", PSR_x | PSR_c | PSR_s},
8283 {"cfs", PSR_c | PSR_f | PSR_s},
8284 {"cfx", PSR_c | PSR_f | PSR_x},
8285 {"csf", PSR_c | PSR_s | PSR_f},
8286 {"csx", PSR_c | PSR_s | PSR_x},
8287 {"cxf", PSR_c | PSR_x | PSR_f},
8288 {"cxs", PSR_c | PSR_x | PSR_s},
8289 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
8290 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
8291 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
8292 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
8293 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
8294 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
8295 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
8296 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
8297 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
8298 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
8299 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
8300 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
8301 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
8302 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
8303 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
8304 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
8305 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
8306 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
8307 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
8308 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
8309 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
8310 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
8311 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
8312 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
8313};
8314
8315/* Table of all shift-in-operand names. */
8316static const struct asm_shift_name shift_names [] =
b99bd4ef 8317{
c19d1205
ZW
8318 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
8319 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
8320 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
8321 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
8322 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
8323 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
8324};
b99bd4ef 8325
c19d1205
ZW
8326/* Table of all explicit relocation names. */
8327#ifdef OBJ_ELF
8328static struct reloc_entry reloc_names[] =
8329{
8330 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
8331 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
8332 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
8333 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
8334 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
8335 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
8336 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
8337 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
8338 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
8339 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
8340 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}
8341};
8342#endif
b99bd4ef 8343
c19d1205
ZW
8344/* Table of all conditional affixes. 0xF is not defined as a condition code. */
8345static const struct asm_cond conds[] =
8346{
8347 {"eq", 0x0},
8348 {"ne", 0x1},
8349 {"cs", 0x2}, {"hs", 0x2},
8350 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
8351 {"mi", 0x4},
8352 {"pl", 0x5},
8353 {"vs", 0x6},
8354 {"vc", 0x7},
8355 {"hi", 0x8},
8356 {"ls", 0x9},
8357 {"ge", 0xa},
8358 {"lt", 0xb},
8359 {"gt", 0xc},
8360 {"le", 0xd},
8361 {"al", 0xe}
8362};
bfae80f2 8363
c19d1205
ZW
8364/* Table of ARM-format instructions. */
8365
8366/* Macros for gluing together operand strings. N.B. In all cases
8367 other than OPS0, the trailing OP_stop comes from default
8368 zero-initialization of the unspecified elements of the array. */
8369#define OPS0() { OP_stop, }
8370#define OPS1(a) { OP_##a, }
8371#define OPS2(a,b) { OP_##a,OP_##b, }
8372#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
8373#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
8374#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
8375#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
8376
8377/* These macros abstract out the exact format of the mnemonic table and
8378 save some repeated characters. */
8379
8380/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
8381#define TxCE(mnem, op, top, nops, ops, ae, te) \
8382 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
1887dd22 8383 THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW
8384
8385/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
8386 a T_MNEM_xyz enumerator. */
8387#define TCE(mnem, aop, top, nops, ops, ae, te) \
8388 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
8389#define tCE(mnem, aop, top, nops, ops, ae, te) \
8390 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8391
8392/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
8393 infix after the third character. */
8394#define TxC3(mnem, op, top, nops, ops, ae, te) \
8395 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
1887dd22 8396 THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW
8397#define TC3(mnem, aop, top, nops, ops, ae, te) \
8398 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
8399#define tC3(mnem, aop, top, nops, ops, ae, te) \
8400 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8401
8402/* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
8403 appear in the condition table. */
8404#define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
8405 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
1887dd22 8406 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW
8407
8408#define TxCM(m1, m2, op, top, nops, ops, ae, te) \
8409 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
8410 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
8411 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
8412 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
8413 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
8414 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
8415 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
8416 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
8417 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
8418 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
8419 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
8420 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
8421 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
8422 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
8423 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
8424 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
8425 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
8426 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
8427 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
8428
8429#define TCM(m1,m2, aop, top, nops, ops, ae, te) \
8430 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
8431#define tCM(m1,m2, aop, top, nops, ops, ae, te) \
8432 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
8433
8434/* Mnemonic that cannot be conditionalized. The ARM condition-code
8435 field is still 0xE. */
8436#define TUE(mnem, op, top, nops, ops, ae, te) \
8437 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
1887dd22 8438 THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW
8439
8440/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
8441 condition code field. */
8442#define TUF(mnem, op, top, nops, ops, ae, te) \
8443 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
1887dd22 8444 THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW
8445
8446/* ARM-only variants of all the above. */
6a86118a
NC
8447#define CE(mnem, op, nops, ops, ae) \
8448 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8449
8450#define C3(mnem, op, nops, ops, ae) \
8451 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8452
e3cb604e
PB
8453/* Legacy mnemonics that always have conditional infix after the third
8454 character. */
8455#define CL(mnem, op, nops, ops, ae) \
8456 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
8457 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8458
8f06b2d8
PB
8459/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
8460#define cCE(mnem, op, nops, ops, ae) \
8461 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8462
e3cb604e
PB
8463/* Legacy coprocessor instructions where conditional infix and conditional
8464 suffix are ambiguous. For consistency this includes all FPA instructions,
8465 not just the potentially ambiguous ones. */
8466#define cCL(mnem, op, nops, ops, ae) \
8467 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
8468 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8469
8470/* Coprocessor, takes either a suffix or a position-3 infix
8471 (for an FPA corner case). */
8472#define C3E(mnem, op, nops, ops, ae) \
8473 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
8474 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8f06b2d8 8475
6a86118a
NC
8476#define xCM_(m1, m2, m3, op, nops, ops, ae) \
8477 { #m1 #m2 #m3, OPS##nops ops, \
8478 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8479 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8480
8481#define CM(m1, m2, op, nops, ops, ae) \
8482 xCM_(m1, , m2, op, nops, ops, ae), \
8483 xCM_(m1, eq, m2, op, nops, ops, ae), \
8484 xCM_(m1, ne, m2, op, nops, ops, ae), \
8485 xCM_(m1, cs, m2, op, nops, ops, ae), \
8486 xCM_(m1, hs, m2, op, nops, ops, ae), \
8487 xCM_(m1, cc, m2, op, nops, ops, ae), \
8488 xCM_(m1, ul, m2, op, nops, ops, ae), \
8489 xCM_(m1, lo, m2, op, nops, ops, ae), \
8490 xCM_(m1, mi, m2, op, nops, ops, ae), \
8491 xCM_(m1, pl, m2, op, nops, ops, ae), \
8492 xCM_(m1, vs, m2, op, nops, ops, ae), \
8493 xCM_(m1, vc, m2, op, nops, ops, ae), \
8494 xCM_(m1, hi, m2, op, nops, ops, ae), \
8495 xCM_(m1, ls, m2, op, nops, ops, ae), \
8496 xCM_(m1, ge, m2, op, nops, ops, ae), \
8497 xCM_(m1, lt, m2, op, nops, ops, ae), \
8498 xCM_(m1, gt, m2, op, nops, ops, ae), \
8499 xCM_(m1, le, m2, op, nops, ops, ae), \
8500 xCM_(m1, al, m2, op, nops, ops, ae)
8501
8502#define UE(mnem, op, nops, ops, ae) \
8503 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8504
8505#define UF(mnem, op, nops, ops, ae) \
8506 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8507
c19d1205
ZW
8508#define do_0 0
8509
8510/* Thumb-only, unconditional. */
8511#define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
8512
c19d1205 8513static const struct asm_opcode insns[] =
bfae80f2 8514{
c19d1205
ZW
8515#define ARM_VARIANT ARM_EXT_V1 /* Core ARM Instructions. */
8516#define THUMB_VARIANT ARM_EXT_V4T
8517 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c),
8518 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c),
8519 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c),
8520 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c),
8521 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub),
8522 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub),
8523 tCE(add, 0800000, add, 3, (RR, oRR, SH), arit, t_add_sub),
8524 tC3(adds, 0900000, adds, 3, (RR, oRR, SH), arit, t_add_sub),
8525 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c),
8526 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c),
8527 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3),
8528 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3),
8529 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c),
8530 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c),
8531 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3),
8532 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3),
8533
8534 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
8535 for setting PSR flag bits. They are obsolete in V6 and do not
8536 have Thumb equivalents. */
8537 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
8538 tC3(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
e3cb604e 8539 CL(tstp, 110f000, 2, (RR, SH), cmp),
c19d1205
ZW
8540 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
8541 tC3(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
e3cb604e 8542 CL(cmpp, 150f000, 2, (RR, SH), cmp),
c19d1205
ZW
8543 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
8544 tC3(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
e3cb604e 8545 CL(cmnp, 170f000, 2, (RR, SH), cmp),
c19d1205
ZW
8546
8547 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp),
8548 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp),
8549 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst),
8550 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst),
8551
8552 tCE(ldr, 4100000, ldr, 2, (RR, ADDR), ldst, t_ldst),
8553 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDR), ldst, t_ldst),
8554 tCE(str, 4000000, str, 2, (RR, ADDR), ldst, t_ldst),
8555 tC3(strb, 4400000, strb, 2, (RR, ADDR), ldst, t_ldst),
8556
8557 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8558 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8559 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8560 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8561
8562 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi),
0110f2b8 8563 tCE(b, a000000, b, 1, (EXPr), branch, t_branch),
2fc8bdac 8564 TCE(bl, b000000, f000f800, 1, (EXPr), branch, t_branch23),
bfae80f2 8565
c19d1205 8566 /* Pseudo ops. */
e9f89963 8567 tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr),
2fc8bdac
ZW
8568 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
8569 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop),
c19d1205
ZW
8570
8571 /* Thumb-compatibility pseudo ops. */
8572 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift),
8573 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift),
8574 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift),
8575 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift),
8576 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift),
2fc8bdac 8577 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift),
c19d1205
ZW
8578 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift),
8579 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift),
8580 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg),
8581 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg),
8582 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop),
8583 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop),
8584
8585#undef THUMB_VARIANT
8586#define THUMB_VARIANT ARM_EXT_V6
2fc8bdac 8587 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
c19d1205
ZW
8588
8589 /* V1 instructions with no Thumb analogue prior to V6T2. */
8590#undef THUMB_VARIANT
8591#define THUMB_VARIANT ARM_EXT_V6T2
8592 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
8593 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
8594 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
8595 TC3(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
e3cb604e 8596 CL(teqp, 130f000, 2, (RR, SH), cmp),
c19d1205
ZW
8597
8598 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt),
8599 TC3(ldrbt, 4700000, f8300e00, 2, (RR, ADDR), ldstt, t_ldstt),
8600 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt),
8601 TC3(strbt, 4600000, f8200e00, 2, (RR, ADDR), ldstt, t_ldstt),
8602
9c3c69f2
PB
8603 TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8604 TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205 8605
9c3c69f2
PB
8606 TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8607 TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205
ZW
8608
8609 /* V1 instructions with no Thumb analogue at all. */
8610 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit),
8611 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
8612
8613 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
8614 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
8615 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
8616 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
8617 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
8618 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
8619 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
8620 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
8621
8622#undef ARM_VARIANT
8623#define ARM_VARIANT ARM_EXT_V2 /* ARM 2 - multiplies. */
8624#undef THUMB_VARIANT
8625#define THUMB_VARIANT ARM_EXT_V4T
8626 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
8627 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
8628
8629#undef THUMB_VARIANT
8630#define THUMB_VARIANT ARM_EXT_V6T2
8631 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
8632 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
8633
8634 /* Generic coprocessor instructions. */
8635 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
8636 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDR), lstc, lstc),
8637 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDR), lstc, lstc),
8638 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDR), lstc, lstc),
8639 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDR), lstc, lstc),
8640 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8641 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8642
8643#undef ARM_VARIANT
8644#define ARM_VARIANT ARM_EXT_V2S /* ARM 3 - swp instructions. */
8645 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
8646 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
8647
8648#undef ARM_VARIANT
8649#define ARM_VARIANT ARM_EXT_V3 /* ARM 6 Status register instructions. */
8650 TCE(mrs, 10f0000, f3ef8000, 2, (RR, PSR), mrs, t_mrs),
8651 TCE(msr, 120f000, f3808000, 2, (PSR, RR_EXi), msr, t_msr),
8652
8653#undef ARM_VARIANT
8654#define ARM_VARIANT ARM_EXT_V3M /* ARM 7M long multiplies. */
8655 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8656 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8657 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8658 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8659 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8660 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8661 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8662 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8663
8664#undef ARM_VARIANT
8665#define ARM_VARIANT ARM_EXT_V4 /* ARM Architecture 4. */
8666#undef THUMB_VARIANT
8667#define THUMB_VARIANT ARM_EXT_V4T
8668 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDR), ldstv4, t_ldst),
8669 tC3(strh, 00000b0, strh, 2, (RR, ADDR), ldstv4, t_ldst),
8670 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
8671 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
8672 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
8673 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
8674
8675#undef ARM_VARIANT
8676#define ARM_VARIANT ARM_EXT_V4T|ARM_EXT_V5
8677 /* ARM Architecture 4T. */
8678 /* Note: bx (and blx) are required on V5, even if the processor does
8679 not support Thumb. */
8680 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx),
8681
8682#undef ARM_VARIANT
8683#define ARM_VARIANT ARM_EXT_V5 /* ARM Architecture 5T. */
8684#undef THUMB_VARIANT
8685#define THUMB_VARIANT ARM_EXT_V5T
8686 /* Note: blx has 2 variants; the .value coded here is for
8687 BLX(2). Only this variant has conditional execution. */
8688 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
8689 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
8690
8691#undef THUMB_VARIANT
8692#define THUMB_VARIANT ARM_EXT_V6T2
8693 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
8694 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDR), lstc, lstc),
8695 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDR), lstc, lstc),
8696 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDR), lstc, lstc),
8697 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDR), lstc, lstc),
8698 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
8699 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8700 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8701
8702#undef ARM_VARIANT
8703#define ARM_VARIANT ARM_EXT_V5ExP /* ARM Architecture 5TExP. */
8704 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8705 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8706 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8707 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8708
8709 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8710 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8711
8712 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8713 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8714 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8715 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8716
8717 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8718 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8719 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8720 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8721
8722 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8723 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8724
8725 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8726 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8727 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8728 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8729
8730#undef ARM_VARIANT
8731#define ARM_VARIANT ARM_EXT_V5E /* ARM Architecture 5TE. */
8732 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld),
8733 TC3(ldrd, 00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
8734 TC3(strd, 00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
8735
8736 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8737 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8738
8739#undef ARM_VARIANT
8740#define ARM_VARIANT ARM_EXT_V5J /* ARM Architecture 5TEJ. */
8741 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
8742
8743#undef ARM_VARIANT
8744#define ARM_VARIANT ARM_EXT_V6 /* ARM V6. */
8745#undef THUMB_VARIANT
8746#define THUMB_VARIANT ARM_EXT_V6
8747 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
8748 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
8749 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8750 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8751 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8752 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8753 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8754 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8755 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8756 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend),
8757
8758#undef THUMB_VARIANT
8759#define THUMB_VARIANT ARM_EXT_V6T2
8760 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, imm0),
8761 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex),
8762 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8763 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8764 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
8765 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
8766 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8767 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8768 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8769 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8770 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8771 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8772 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8773 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8774 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8775 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8776 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8777 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8778 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8779 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8780 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8781 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8782 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8783 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8784 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8785 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8786 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8787 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8788 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8789 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8790 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8791 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8792 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8793 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8794 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8795 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8796 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8797 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8798 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8799 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8800 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8801 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8802 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe),
8803 UF(rfeib, 9900a00, 1, (RRw), rfe),
8804 UF(rfeda, 8100a00, 1, (RRw), rfe),
8805 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe),
8806 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe),
8807 UF(rfefa, 9900a00, 1, (RRw), rfe),
8808 UF(rfeea, 8100a00, 1, (RRw), rfe),
8809 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe),
8810 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8811 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8812 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8813 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8814 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8815 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8816 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8817 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8818 TCE(sel, 68000b0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8819 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8820 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8821 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8822 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8823 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8824 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8825 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8826 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8827 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8828 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8829 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8830 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8831 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8832 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8833 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8834 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8835 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8836 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8837 TUF(srsia, 8cd0500, e980c000, 1, (I31w), srs, srs),
8838 UF(srsib, 9cd0500, 1, (I31w), srs),
8839 UF(srsda, 84d0500, 1, (I31w), srs),
8840 TUF(srsdb, 94d0500, e800c000, 1, (I31w), srs, srs),
8841 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
8842 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
8843 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex),
8844 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
8845 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8846 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8847 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
8848 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
8849
8850#undef ARM_VARIANT
8851#define ARM_VARIANT ARM_EXT_V6K
8852#undef THUMB_VARIANT
8853#define THUMB_VARIANT ARM_EXT_V6K
8854 tCE(yield, 320f001, yield, 0, (), noargs, t_hint),
8855 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint),
8856 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint),
8857 tCE(sev, 320f004, sev, 0, (), noargs, t_hint),
8858
8859#undef THUMB_VARIANT
8860#define THUMB_VARIANT ARM_EXT_V6T2
8861 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
8862 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
8863 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd),
8864 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
8865 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
8866 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd),
8867 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
8868
8869#undef ARM_VARIANT
8870#define ARM_VARIANT ARM_EXT_V6Z
3eb17e6b 8871 TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc),
c19d1205
ZW
8872
8873#undef ARM_VARIANT
8874#define ARM_VARIANT ARM_EXT_V6T2
8875 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
8876 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
8877 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
8878 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
8879
8880 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
8881 TCE(movw, 3000000, f2400000, 2, (RRnpc, Iffff), mov16, t_mov16),
8882 TCE(movt, 3400000, f2c00000, 2, (RRnpc, Iffff), mov16, t_mov16),
8883 TCE(rbit, 3ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
8884
8885 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8886 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8887 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8888 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8889
8890 UT(cbnz, b900, 2, (RR, EXP), t_czb),
8891 UT(cbz, b100, 2, (RR, EXP), t_czb),
8892 /* ARM does not really have an IT instruction. */
8893 TUE(it, 0, bf08, 1, (COND), it, t_it),
8894 TUE(itt, 0, bf0c, 1, (COND), it, t_it),
8895 TUE(ite, 0, bf04, 1, (COND), it, t_it),
8896 TUE(ittt, 0, bf0e, 1, (COND), it, t_it),
8897 TUE(itet, 0, bf06, 1, (COND), it, t_it),
8898 TUE(itte, 0, bf0a, 1, (COND), it, t_it),
8899 TUE(itee, 0, bf02, 1, (COND), it, t_it),
8900 TUE(itttt, 0, bf0f, 1, (COND), it, t_it),
8901 TUE(itett, 0, bf07, 1, (COND), it, t_it),
8902 TUE(ittet, 0, bf0b, 1, (COND), it, t_it),
8903 TUE(iteet, 0, bf03, 1, (COND), it, t_it),
8904 TUE(ittte, 0, bf0d, 1, (COND), it, t_it),
8905 TUE(itete, 0, bf05, 1, (COND), it, t_it),
8906 TUE(ittee, 0, bf09, 1, (COND), it, t_it),
8907 TUE(iteee, 0, bf01, 1, (COND), it, t_it),
8908
92e90b6e
PB
8909 /* Thumb2 only instructions. */
8910#undef ARM_VARIANT
8911#define ARM_VARIANT 0
8912
8913 TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
8914 TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
8915 TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb),
8916 TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb),
8917
c19d1205
ZW
8918#undef ARM_VARIANT
8919#define ARM_VARIANT FPU_FPA_EXT_V1 /* Core FPA instruction set (V1). */
8f06b2d8
PB
8920 cCE(wfs, e200110, 1, (RR), rd),
8921 cCE(rfs, e300110, 1, (RR), rd),
8922 cCE(wfc, e400110, 1, (RR), rd),
8923 cCE(rfc, e500110, 1, (RR), rd),
8924
e3cb604e
PB
8925 cCL(ldfs, c100100, 2, (RF, ADDR), rd_cpaddr),
8926 cCL(ldfd, c108100, 2, (RF, ADDR), rd_cpaddr),
8927 cCL(ldfe, c500100, 2, (RF, ADDR), rd_cpaddr),
8928 cCL(ldfp, c508100, 2, (RF, ADDR), rd_cpaddr),
8929
8930 cCL(stfs, c000100, 2, (RF, ADDR), rd_cpaddr),
8931 cCL(stfd, c008100, 2, (RF, ADDR), rd_cpaddr),
8932 cCL(stfe, c400100, 2, (RF, ADDR), rd_cpaddr),
8933 cCL(stfp, c408100, 2, (RF, ADDR), rd_cpaddr),
8934
8935 cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm),
8936 cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm),
8937 cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm),
8938 cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm),
8939 cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm),
8940 cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm),
8941 cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm),
8942 cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm),
8943 cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm),
8944 cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm),
8945 cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm),
8946 cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm),
8947
8948 cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm),
8949 cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm),
8950 cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm),
8951 cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm),
8952 cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm),
8953 cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm),
8954 cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm),
8955 cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm),
8956 cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm),
8957 cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm),
8958 cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm),
8959 cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm),
8960
8961 cCL(abss, e208100, 2, (RF, RF_IF), rd_rm),
8962 cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm),
8963 cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm),
8964 cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm),
8965 cCL(absd, e208180, 2, (RF, RF_IF), rd_rm),
8966 cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm),
8967 cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm),
8968 cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm),
8969 cCL(abse, e288100, 2, (RF, RF_IF), rd_rm),
8970 cCL(absep, e288120, 2, (RF, RF_IF), rd_rm),
8971 cCL(absem, e288140, 2, (RF, RF_IF), rd_rm),
8972 cCL(absez, e288160, 2, (RF, RF_IF), rd_rm),
8973
8974 cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm),
8975 cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm),
8976 cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm),
8977 cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm),
8978 cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm),
8979 cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm),
8980 cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm),
8981 cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm),
8982 cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm),
8983 cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm),
8984 cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm),
8985 cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm),
8986
8987 cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm),
8988 cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm),
8989 cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm),
8990 cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm),
8991 cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm),
8992 cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm),
8993 cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm),
8994 cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm),
8995 cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm),
8996 cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm),
8997 cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm),
8998 cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm),
8999
9000 cCL(logs, e508100, 2, (RF, RF_IF), rd_rm),
9001 cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm),
9002 cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm),
9003 cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm),
9004 cCL(logd, e508180, 2, (RF, RF_IF), rd_rm),
9005 cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm),
9006 cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm),
9007 cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm),
9008 cCL(loge, e588100, 2, (RF, RF_IF), rd_rm),
9009 cCL(logep, e588120, 2, (RF, RF_IF), rd_rm),
9010 cCL(logem, e588140, 2, (RF, RF_IF), rd_rm),
9011 cCL(logez, e588160, 2, (RF, RF_IF), rd_rm),
9012
9013 cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm),
9014 cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm),
9015 cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm),
9016 cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm),
9017 cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm),
9018 cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm),
9019 cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm),
9020 cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm),
9021 cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm),
9022 cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm),
9023 cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm),
9024 cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm),
9025
9026 cCL(exps, e708100, 2, (RF, RF_IF), rd_rm),
9027 cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm),
9028 cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm),
9029 cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm),
9030 cCL(expd, e708180, 2, (RF, RF_IF), rd_rm),
9031 cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm),
9032 cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm),
9033 cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm),
9034 cCL(expe, e788100, 2, (RF, RF_IF), rd_rm),
9035 cCL(expep, e788120, 2, (RF, RF_IF), rd_rm),
9036 cCL(expem, e788140, 2, (RF, RF_IF), rd_rm),
9037 cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm),
9038
9039 cCL(sins, e808100, 2, (RF, RF_IF), rd_rm),
9040 cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm),
9041 cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm),
9042 cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm),
9043 cCL(sind, e808180, 2, (RF, RF_IF), rd_rm),
9044 cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm),
9045 cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm),
9046 cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm),
9047 cCL(sine, e888100, 2, (RF, RF_IF), rd_rm),
9048 cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm),
9049 cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm),
9050 cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm),
9051
9052 cCL(coss, e908100, 2, (RF, RF_IF), rd_rm),
9053 cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm),
9054 cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm),
9055 cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm),
9056 cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm),
9057 cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm),
9058 cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm),
9059 cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm),
9060 cCL(cose, e988100, 2, (RF, RF_IF), rd_rm),
9061 cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm),
9062 cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm),
9063 cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm),
9064
9065 cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm),
9066 cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm),
9067 cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm),
9068 cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm),
9069 cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm),
9070 cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm),
9071 cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm),
9072 cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm),
9073 cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm),
9074 cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm),
9075 cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm),
9076 cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm),
9077
9078 cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm),
9079 cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm),
9080 cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm),
9081 cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm),
9082 cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm),
9083 cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm),
9084 cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm),
9085 cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm),
9086 cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm),
9087 cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm),
9088 cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm),
9089 cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm),
9090
9091 cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm),
9092 cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm),
9093 cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm),
9094 cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm),
9095 cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm),
9096 cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm),
9097 cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm),
9098 cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm),
9099 cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm),
9100 cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm),
9101 cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm),
9102 cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm),
9103
9104 cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm),
9105 cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm),
9106 cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm),
9107 cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm),
9108 cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm),
9109 cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm),
9110 cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm),
9111 cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm),
9112 cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm),
9113 cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm),
9114 cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm),
9115 cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm),
9116
9117 cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm),
9118 cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm),
9119 cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm),
9120 cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm),
9121 cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm),
9122 cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm),
9123 cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm),
9124 cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm),
9125 cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm),
9126 cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm),
9127 cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm),
9128 cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm),
9129
9130 cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm),
9131 cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm),
9132 cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm),
9133 cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm),
9134 cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm),
9135 cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm),
9136 cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm),
9137 cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm),
9138 cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm),
9139 cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm),
9140 cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm),
9141 cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm),
9142
9143 cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
9144 cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
9145 cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
9146 cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
9147 cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
9148 cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9149 cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9150 cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9151 cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
9152 cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
9153 cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
9154 cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
9155
9156 cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
9157 cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
9158 cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
9159 cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
9160 cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
9161 cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9162 cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9163 cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9164 cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
9165 cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
9166 cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
9167 cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
9168
9169 cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
9170 cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
9171 cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
9172 cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
9173 cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
9174 cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9175 cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9176 cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9177 cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
9178 cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
9179 cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
9180 cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
9181
9182 cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
9183 cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
9184 cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
9185 cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
9186 cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
9187 cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9188 cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9189 cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9190 cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
9191 cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
9192 cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
9193 cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
9194
9195 cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
9196 cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
9197 cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
9198 cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
9199 cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
9200 cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9201 cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9202 cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9203 cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
9204 cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
9205 cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
9206 cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
9207
9208 cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
9209 cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
9210 cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
9211 cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
9212 cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
9213 cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9214 cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9215 cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9216 cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
9217 cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
9218 cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
9219 cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
9220
9221 cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
9222 cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
9223 cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
9224 cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
9225 cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
9226 cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9227 cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9228 cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9229 cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
9230 cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
9231 cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
9232 cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
9233
9234 cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
9235 cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
9236 cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
9237 cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
9238 cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
9239 cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9240 cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9241 cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9242 cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
9243 cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
9244 cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
9245 cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
9246
9247 cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
9248 cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
9249 cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
9250 cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
9251 cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
9252 cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9253 cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9254 cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9255 cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
9256 cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
9257 cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
9258 cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
9259
9260 cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
9261 cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
9262 cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
9263 cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
9264 cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
9265 cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9266 cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9267 cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9268 cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
9269 cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
9270 cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
9271 cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
9272
9273 cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9274 cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9275 cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9276 cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9277 cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9278 cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9279 cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9280 cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9281 cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9282 cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9283 cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9284 cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9285
9286 cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9287 cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9288 cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9289 cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9290 cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9291 cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9292 cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9293 cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9294 cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9295 cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9296 cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9297 cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9298
9299 cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9300 cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9301 cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9302 cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9303 cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9304 cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9305 cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9306 cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9307 cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9308 cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9309 cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9310 cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
8f06b2d8
PB
9311
9312 cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
c19d1205 9313 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
8f06b2d8 9314 cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
c19d1205
ZW
9315 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
9316
e3cb604e
PB
9317 cCL(flts, e000110, 2, (RF, RR), rn_rd),
9318 cCL(fltsp, e000130, 2, (RF, RR), rn_rd),
9319 cCL(fltsm, e000150, 2, (RF, RR), rn_rd),
9320 cCL(fltsz, e000170, 2, (RF, RR), rn_rd),
9321 cCL(fltd, e000190, 2, (RF, RR), rn_rd),
9322 cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd),
9323 cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd),
9324 cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd),
9325 cCL(flte, e080110, 2, (RF, RR), rn_rd),
9326 cCL(fltep, e080130, 2, (RF, RR), rn_rd),
9327 cCL(fltem, e080150, 2, (RF, RR), rn_rd),
9328 cCL(fltez, e080170, 2, (RF, RR), rn_rd),
b99bd4ef 9329
c19d1205
ZW
9330 /* The implementation of the FIX instruction is broken on some
9331 assemblers, in that it accepts a precision specifier as well as a
9332 rounding specifier, despite the fact that this is meaningless.
9333 To be more compatible, we accept it as well, though of course it
9334 does not set any bits. */
8f06b2d8 9335 cCE(fix, e100110, 2, (RR, RF), rd_rm),
e3cb604e
PB
9336 cCL(fixp, e100130, 2, (RR, RF), rd_rm),
9337 cCL(fixm, e100150, 2, (RR, RF), rd_rm),
9338 cCL(fixz, e100170, 2, (RR, RF), rd_rm),
9339 cCL(fixsp, e100130, 2, (RR, RF), rd_rm),
9340 cCL(fixsm, e100150, 2, (RR, RF), rd_rm),
9341 cCL(fixsz, e100170, 2, (RR, RF), rd_rm),
9342 cCL(fixdp, e100130, 2, (RR, RF), rd_rm),
9343 cCL(fixdm, e100150, 2, (RR, RF), rd_rm),
9344 cCL(fixdz, e100170, 2, (RR, RF), rd_rm),
9345 cCL(fixep, e100130, 2, (RR, RF), rd_rm),
9346 cCL(fixem, e100150, 2, (RR, RF), rd_rm),
9347 cCL(fixez, e100170, 2, (RR, RF), rd_rm),
bfae80f2 9348
c19d1205
ZW
9349 /* Instructions that were new with the real FPA, call them V2. */
9350#undef ARM_VARIANT
9351#define ARM_VARIANT FPU_FPA_EXT_V2
8f06b2d8 9352 cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
e3cb604e
PB
9353 cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9354 cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
8f06b2d8 9355 cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
e3cb604e
PB
9356 cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9357 cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
c19d1205
ZW
9358
9359#undef ARM_VARIANT
9360#define ARM_VARIANT FPU_VFP_EXT_V1xD /* VFP V1xD (single precision). */
9361 /* Moves and type conversions. */
8f06b2d8
PB
9362 cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
9363 cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
9364 cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
9365 cCE(fmstat, ef1fa10, 0, (), noargs),
9366 cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
9367 cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
9368 cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
9369 cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
9370 cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
9371 cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
9372 cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn),
9373 cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd),
c19d1205
ZW
9374
9375 /* Memory operations. */
8f06b2d8
PB
9376 cCE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst),
9377 cCE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst),
9378 cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9379 cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9380 cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9381 cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9382 cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9383 cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9384 cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9385 cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9386 cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9387 cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9388 cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9389 cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9390 cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9391 cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9392 cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9393 cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
bfae80f2 9394
c19d1205 9395 /* Monadic operations. */
8f06b2d8
PB
9396 cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
9397 cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
9398 cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
c19d1205
ZW
9399
9400 /* Dyadic operations. */
8f06b2d8
PB
9401 cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9402 cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9403 cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9404 cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9405 cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9406 cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9407 cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9408 cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9409 cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
b99bd4ef 9410
c19d1205 9411 /* Comparisons. */
8f06b2d8
PB
9412 cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
9413 cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
9414 cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
9415 cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
b99bd4ef 9416
c19d1205
ZW
9417#undef ARM_VARIANT
9418#define ARM_VARIANT FPU_VFP_EXT_V1 /* VFP V1 (Double precision). */
9419 /* Moves and type conversions. */
8f06b2d8
PB
9420 cCE(fcpyd, eb00b40, 2, (RVD, RVD), rd_rm),
9421 cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
9422 cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9423 cCE(fmdhr, e200b10, 2, (RVD, RR), rn_rd),
9424 cCE(fmdlr, e000b10, 2, (RVD, RR), rn_rd),
9425 cCE(fmrdh, e300b10, 2, (RR, RVD), rd_rn),
9426 cCE(fmrdl, e100b10, 2, (RR, RVD), rd_rn),
9427 cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
9428 cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
9429 cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
9430 cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9431 cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
9432 cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
c19d1205
ZW
9433
9434 /* Memory operations. */
8f06b2d8
PB
9435 cCE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst),
9436 cCE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst),
9437 cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9438 cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9439 cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9440 cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9441 cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9442 cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9443 cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9444 cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
b99bd4ef 9445
c19d1205 9446 /* Monadic operations. */
8f06b2d8
PB
9447 cCE(fabsd, eb00bc0, 2, (RVD, RVD), rd_rm),
9448 cCE(fnegd, eb10b40, 2, (RVD, RVD), rd_rm),
9449 cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), rd_rm),
c19d1205
ZW
9450
9451 /* Dyadic operations. */
8f06b2d8
PB
9452 cCE(faddd, e300b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9453 cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9454 cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9455 cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9456 cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9457 cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9458 cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9459 cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9460 cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), rd_rn_rm),
b99bd4ef 9461
c19d1205 9462 /* Comparisons. */
8f06b2d8
PB
9463 cCE(fcmpd, eb40b40, 2, (RVD, RVD), rd_rm),
9464 cCE(fcmpzd, eb50b40, 1, (RVD), rd),
9465 cCE(fcmped, eb40bc0, 2, (RVD, RVD), rd_rm),
9466 cCE(fcmpezd, eb50bc0, 1, (RVD), rd),
c19d1205
ZW
9467
9468#undef ARM_VARIANT
9469#define ARM_VARIANT FPU_VFP_EXT_V2
8f06b2d8
PB
9470 cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
9471 cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
9472 cCE(fmdrr, c400b10, 3, (RVD, RR, RR), rm_rd_rn),
9473 cCE(fmrrd, c500b10, 3, (RR, RR, RVD), rd_rn_rm),
c19d1205
ZW
9474
9475#undef ARM_VARIANT
9476#define ARM_VARIANT ARM_CEXT_XSCALE /* Intel XScale extensions. */
8f06b2d8
PB
9477 cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9478 cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9479 cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9480 cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9481 cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9482 cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9483 cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
9484 cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
c19d1205
ZW
9485
9486#undef ARM_VARIANT
9487#define ARM_VARIANT ARM_CEXT_IWMMXT /* Intel Wireless MMX technology. */
8f06b2d8
PB
9488 cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
9489 cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
9490 cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
9491 cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd),
9492 cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd),
9493 cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd),
9494 cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
9495 cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
9496 cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
9497 cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9498 cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9499 cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9500 cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9501 cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9502 cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9503 cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9504 cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9505 cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9506 cCE(tmcr, e000110, 2, (RIWC, RR), rn_rd),
9507 cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn),
9508 cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9509 cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9510 cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9511 cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9512 cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9513 cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9514 cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn),
9515 cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn),
9516 cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn),
9517 cCE(tmrc, e100110, 2, (RR, RIWC), rd_rn),
9518 cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm),
9519 cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
9520 cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
9521 cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
9522 cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn),
9523 cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn),
9524 cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn),
9525 cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9526 cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9527 cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9528 cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9529 cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9530 cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9531 cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9532 cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9533 cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9534 cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
9535 cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9536 cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9537 cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9538 cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9539 cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9540 cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9541 cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9542 cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9543 cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9544 cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9545 cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9546 cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9547 cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9548 cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9549 cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9550 cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9551 cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9552 cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9553 cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9554 cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9555 cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9556 cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
9557 cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
9558 cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9559 cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9560 cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9561 cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9562 cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9563 cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9564 cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9565 cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9566 cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9567 cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9568 cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9569 cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9570 cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9571 cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9572 cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9573 cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9574 cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9575 cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9576 cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
9577 cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9578 cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9579 cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9580 cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9581 cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9582 cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9583 cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9584 cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9585 cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9586 cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9587 cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9588 cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9589 cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9590 cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9591 cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9592 cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9593 cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9594 cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9595 cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9596 cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9597 cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9598 cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
9599 cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9600 cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9601 cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9602 cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9603 cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9604 cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9605 cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9606 cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9607 cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9608 cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9609 cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9610 cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9611 cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9612 cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9613 cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9614 cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9615 cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9616 cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9617 cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9618 cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9619 cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
9620 cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
9621 cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9622 cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9623 cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9624 cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9625 cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9626 cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9627 cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9628 cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9629 cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9630 cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn),
9631 cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn),
9632 cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn),
9633 cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn),
9634 cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn),
9635 cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn),
9636 cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9637 cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9638 cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9639 cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn),
9640 cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn),
9641 cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn),
9642 cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn),
9643 cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn),
9644 cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn),
9645 cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9646 cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9647 cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9648 cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9649 cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
c19d1205
ZW
9650
9651#undef ARM_VARIANT
9652#define ARM_VARIANT ARM_CEXT_MAVERICK /* Cirrus Maverick instructions. */
8f06b2d8
PB
9653 cCE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr),
9654 cCE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr),
9655 cCE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr),
9656 cCE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr),
9657 cCE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr),
9658 cCE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr),
9659 cCE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr),
9660 cCE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr),
9661 cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd),
9662 cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn),
9663 cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd),
9664 cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn),
9665 cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd),
9666 cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn),
9667 cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd),
9668 cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn),
9669 cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd),
9670 cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn),
9671 cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn),
9672 cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn),
9673 cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn),
9674 cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn),
9675 cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn),
9676 cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn),
9677 cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn),
9678 cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn),
9679 cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn),
9680 cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn),
9681 cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc),
9682 cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd),
9683 cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn),
9684 cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn),
9685 cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn),
9686 cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn),
9687 cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn),
9688 cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn),
9689 cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn),
9690 cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn),
9691 cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn),
9692 cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn),
9693 cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn),
9694 cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn),
9695 cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple),
9696 cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple),
9697 cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
9698 cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
9699 cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm),
9700 cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
9701 cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
9702 cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
9703 cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn),
9704 cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn),
9705 cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn),
9706 cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn),
9707 cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
9708 cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
9709 cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
9710 cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
9711 cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
9712 cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
9713 cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn),
9714 cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn),
9715 cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn),
9716 cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn),
9717 cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9718 cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9719 cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9720 cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9721 cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9722 cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9723 cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9724 cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9725 cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
9726 cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
9727 cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
9728 cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
c19d1205
ZW
9729};
9730#undef ARM_VARIANT
9731#undef THUMB_VARIANT
9732#undef TCE
9733#undef TCM
9734#undef TUE
9735#undef TUF
9736#undef TCC
8f06b2d8 9737#undef cCE
e3cb604e
PB
9738#undef cCL
9739#undef C3E
c19d1205
ZW
9740#undef CE
9741#undef CM
9742#undef UE
9743#undef UF
9744#undef UT
9745#undef OPS0
9746#undef OPS1
9747#undef OPS2
9748#undef OPS3
9749#undef OPS4
9750#undef OPS5
9751#undef OPS6
9752#undef do_0
9753\f
9754/* MD interface: bits in the object file. */
bfae80f2 9755
c19d1205
ZW
9756/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
9757 for use in the a.out file, and stores them in the array pointed to by buf.
9758 This knows about the endian-ness of the target machine and does
9759 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
9760 2 (short) and 4 (long) Floating numbers are put out as a series of
9761 LITTLENUMS (shorts, here at least). */
b99bd4ef 9762
c19d1205
ZW
9763void
9764md_number_to_chars (char * buf, valueT val, int n)
9765{
9766 if (target_big_endian)
9767 number_to_chars_bigendian (buf, val, n);
9768 else
9769 number_to_chars_littleendian (buf, val, n);
bfae80f2
RE
9770}
9771
c19d1205
ZW
9772static valueT
9773md_chars_to_number (char * buf, int n)
bfae80f2 9774{
c19d1205
ZW
9775 valueT result = 0;
9776 unsigned char * where = (unsigned char *) buf;
bfae80f2 9777
c19d1205 9778 if (target_big_endian)
b99bd4ef 9779 {
c19d1205
ZW
9780 while (n--)
9781 {
9782 result <<= 8;
9783 result |= (*where++ & 255);
9784 }
b99bd4ef 9785 }
c19d1205 9786 else
b99bd4ef 9787 {
c19d1205
ZW
9788 while (n--)
9789 {
9790 result <<= 8;
9791 result |= (where[n] & 255);
9792 }
bfae80f2 9793 }
b99bd4ef 9794
c19d1205 9795 return result;
bfae80f2 9796}
b99bd4ef 9797
c19d1205 9798/* MD interface: Sections. */
b99bd4ef 9799
0110f2b8
PB
9800/* Estimate the size of a frag before relaxing. Assume everything fits in
9801 2 bytes. */
9802
c19d1205 9803int
0110f2b8 9804md_estimate_size_before_relax (fragS * fragp,
c19d1205
ZW
9805 segT segtype ATTRIBUTE_UNUSED)
9806{
0110f2b8
PB
9807 fragp->fr_var = 2;
9808 return 2;
9809}
9810
9811/* Convert a machine dependent frag. */
9812
9813void
9814md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
9815{
9816 unsigned long insn;
9817 unsigned long old_op;
9818 char *buf;
9819 expressionS exp;
9820 fixS *fixp;
9821 int reloc_type;
9822 int pc_rel;
9823 int opcode;
9824
9825 buf = fragp->fr_literal + fragp->fr_fix;
9826
9827 old_op = bfd_get_16(abfd, buf);
9828 if (fragp->fr_symbol) {
9829 exp.X_op = O_symbol;
9830 exp.X_add_symbol = fragp->fr_symbol;
9831 } else {
9832 exp.X_op = O_constant;
9833 }
9834 exp.X_add_number = fragp->fr_offset;
9835 opcode = fragp->fr_subtype;
9836 switch (opcode)
9837 {
9838 case T_MNEM_ldr_pc:
9839 case T_MNEM_ldr_pc2:
9840 case T_MNEM_ldr_sp:
9841 case T_MNEM_str_sp:
9842 case T_MNEM_ldr:
9843 case T_MNEM_ldrb:
9844 case T_MNEM_ldrh:
9845 case T_MNEM_str:
9846 case T_MNEM_strb:
9847 case T_MNEM_strh:
9848 if (fragp->fr_var == 4)
9849 {
9850 insn = THUMB_OP32(opcode);
9851 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
9852 {
9853 insn |= (old_op & 0x700) << 4;
9854 }
9855 else
9856 {
9857 insn |= (old_op & 7) << 12;
9858 insn |= (old_op & 0x38) << 13;
9859 }
9860 insn |= 0x00000c00;
9861 put_thumb32_insn (buf, insn);
9862 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9863 }
9864 else
9865 {
9866 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
9867 }
9868 pc_rel = (opcode == T_MNEM_ldr_pc2);
9869 break;
9870 case T_MNEM_adr:
9871 if (fragp->fr_var == 4)
9872 {
9873 insn = THUMB_OP32 (opcode);
9874 insn |= (old_op & 0xf0) << 4;
9875 put_thumb32_insn (buf, insn);
9876 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
9877 }
9878 else
9879 {
9880 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
9881 exp.X_add_number -= 4;
9882 }
9883 pc_rel = 1;
9884 break;
9885 case T_MNEM_mov:
9886 case T_MNEM_movs:
9887 case T_MNEM_cmp:
9888 case T_MNEM_cmn:
9889 if (fragp->fr_var == 4)
9890 {
9891 int r0off = (opcode == T_MNEM_mov
9892 || opcode == T_MNEM_movs) ? 0 : 8;
9893 insn = THUMB_OP32 (opcode);
9894 insn = (insn & 0xe1ffffff) | 0x10000000;
9895 insn |= (old_op & 0x700) << r0off;
9896 put_thumb32_insn (buf, insn);
9897 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
9898 }
9899 else
9900 {
9901 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
9902 }
9903 pc_rel = 0;
9904 break;
9905 case T_MNEM_b:
9906 if (fragp->fr_var == 4)
9907 {
9908 insn = THUMB_OP32(opcode);
9909 put_thumb32_insn (buf, insn);
9910 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
9911 }
9912 else
9913 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
9914 pc_rel = 1;
9915 break;
9916 case T_MNEM_bcond:
9917 if (fragp->fr_var == 4)
9918 {
9919 insn = THUMB_OP32(opcode);
9920 insn |= (old_op & 0xf00) << 14;
9921 put_thumb32_insn (buf, insn);
9922 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
9923 }
9924 else
9925 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
9926 pc_rel = 1;
9927 break;
9928 case T_MNEM_add_sp:
9929 case T_MNEM_add_pc:
9930 case T_MNEM_inc_sp:
9931 case T_MNEM_dec_sp:
9932 if (fragp->fr_var == 4)
9933 {
9934 /* ??? Choose between add and addw. */
9935 insn = THUMB_OP32 (opcode);
9936 insn |= (old_op & 0xf0) << 4;
9937 put_thumb32_insn (buf, insn);
9938 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
9939 }
9940 else
9941 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
9942 pc_rel = 0;
9943 break;
9944
9945 case T_MNEM_addi:
9946 case T_MNEM_addis:
9947 case T_MNEM_subi:
9948 case T_MNEM_subis:
9949 if (fragp->fr_var == 4)
9950 {
9951 insn = THUMB_OP32 (opcode);
9952 insn |= (old_op & 0xf0) << 4;
9953 insn |= (old_op & 0xf) << 16;
9954 put_thumb32_insn (buf, insn);
9955 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
9956 }
9957 else
9958 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
9959 pc_rel = 0;
9960 break;
9961 default:
9962 abort();
9963 }
9964 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
9965 reloc_type);
9966 fixp->fx_file = fragp->fr_file;
9967 fixp->fx_line = fragp->fr_line;
9968 fragp->fr_fix += fragp->fr_var;
9969}
9970
9971/* Return the size of a relaxable immediate operand instruction.
9972 SHIFT and SIZE specify the form of the allowable immediate. */
9973static int
9974relax_immediate (fragS *fragp, int size, int shift)
9975{
9976 offsetT offset;
9977 offsetT mask;
9978 offsetT low;
9979
9980 /* ??? Should be able to do better than this. */
9981 if (fragp->fr_symbol)
9982 return 4;
9983
9984 low = (1 << shift) - 1;
9985 mask = (1 << (shift + size)) - (1 << shift);
9986 offset = fragp->fr_offset;
9987 /* Force misaligned offsets to 32-bit variant. */
9988 if (offset & low)
9989 return -4;
9990 if (offset & ~mask)
9991 return 4;
9992 return 2;
9993}
9994
9995/* Return the size of a relaxable adr pseudo-instruction or PC-relative
9996 load. */
9997static int
9998relax_adr (fragS *fragp, asection *sec)
9999{
10000 addressT addr;
10001 offsetT val;
10002
10003 /* Assume worst case for symbols not known to be in the same section. */
10004 if (!S_IS_DEFINED(fragp->fr_symbol)
10005 || sec != S_GET_SEGMENT (fragp->fr_symbol))
10006 return 4;
10007
10008 val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
10009 addr = fragp->fr_address + fragp->fr_fix;
10010 addr = (addr + 4) & ~3;
10011 /* Fix the insn as the 4-byte version if the target address is not
10012 sufficiently aligned. This is prevents an infinite loop when two
10013 instructions have contradictory range/alignment requirements. */
10014 if (val & 3)
10015 return -4;
10016 val -= addr;
10017 if (val < 0 || val > 1020)
10018 return 4;
10019 return 2;
10020}
10021
10022/* Return the size of a relaxable add/sub immediate instruction. */
10023static int
10024relax_addsub (fragS *fragp, asection *sec)
10025{
10026 char *buf;
10027 int op;
10028
10029 buf = fragp->fr_literal + fragp->fr_fix;
10030 op = bfd_get_16(sec->owner, buf);
10031 if ((op & 0xf) == ((op >> 4) & 0xf))
10032 return relax_immediate (fragp, 8, 0);
10033 else
10034 return relax_immediate (fragp, 3, 0);
10035}
10036
10037
10038/* Return the size of a relaxable branch instruction. BITS is the
10039 size of the offset field in the narrow instruction. */
10040
10041static int
10042relax_branch (fragS *fragp, asection *sec, int bits)
10043{
10044 addressT addr;
10045 offsetT val;
10046 offsetT limit;
10047
10048 /* Assume worst case for symbols not known to be in the same section. */
10049 if (!S_IS_DEFINED(fragp->fr_symbol)
10050 || sec != S_GET_SEGMENT (fragp->fr_symbol))
10051 return 4;
10052
10053 val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
10054 addr = fragp->fr_address + fragp->fr_fix + 4;
10055 val -= addr;
10056
10057 /* Offset is a signed value *2 */
10058 limit = 1 << bits;
10059 if (val >= limit || val < -limit)
10060 return 4;
10061 return 2;
10062}
10063
10064
10065/* Relax a machine dependent frag. This returns the amount by which
10066 the current size of the frag should change. */
10067
10068int
10069arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
10070{
10071 int oldsize;
10072 int newsize;
10073
10074 oldsize = fragp->fr_var;
10075 switch (fragp->fr_subtype)
10076 {
10077 case T_MNEM_ldr_pc2:
10078 newsize = relax_adr(fragp, sec);
10079 break;
10080 case T_MNEM_ldr_pc:
10081 case T_MNEM_ldr_sp:
10082 case T_MNEM_str_sp:
10083 newsize = relax_immediate(fragp, 8, 2);
10084 break;
10085 case T_MNEM_ldr:
10086 case T_MNEM_str:
10087 newsize = relax_immediate(fragp, 5, 2);
10088 break;
10089 case T_MNEM_ldrh:
10090 case T_MNEM_strh:
10091 newsize = relax_immediate(fragp, 5, 1);
10092 break;
10093 case T_MNEM_ldrb:
10094 case T_MNEM_strb:
10095 newsize = relax_immediate(fragp, 5, 0);
10096 break;
10097 case T_MNEM_adr:
10098 newsize = relax_adr(fragp, sec);
10099 break;
10100 case T_MNEM_mov:
10101 case T_MNEM_movs:
10102 case T_MNEM_cmp:
10103 case T_MNEM_cmn:
10104 newsize = relax_immediate(fragp, 8, 0);
10105 break;
10106 case T_MNEM_b:
10107 newsize = relax_branch(fragp, sec, 11);
10108 break;
10109 case T_MNEM_bcond:
10110 newsize = relax_branch(fragp, sec, 8);
10111 break;
10112 case T_MNEM_add_sp:
10113 case T_MNEM_add_pc:
10114 newsize = relax_immediate (fragp, 8, 2);
10115 break;
10116 case T_MNEM_inc_sp:
10117 case T_MNEM_dec_sp:
10118 newsize = relax_immediate (fragp, 7, 2);
10119 break;
10120 case T_MNEM_addi:
10121 case T_MNEM_addis:
10122 case T_MNEM_subi:
10123 case T_MNEM_subis:
10124 newsize = relax_addsub (fragp, sec);
10125 break;
10126 default:
10127 abort();
10128 }
10129 if (newsize < 0)
10130 {
10131 fragp->fr_var = -newsize;
10132 md_convert_frag (sec->owner, sec, fragp);
10133 frag_wane(fragp);
10134 return -(newsize + oldsize);
10135 }
10136 fragp->fr_var = newsize;
10137 return newsize - oldsize;
c19d1205 10138}
b99bd4ef 10139
c19d1205 10140/* Round up a section size to the appropriate boundary. */
b99bd4ef 10141
c19d1205
ZW
10142valueT
10143md_section_align (segT segment ATTRIBUTE_UNUSED,
10144 valueT size)
10145{
10146#ifdef OBJ_ELF
10147 return size;
10148#else
10149 /* Round all sects to multiple of 4. */
10150 return (size + 3) & ~3;
10151#endif
bfae80f2 10152}
b99bd4ef 10153
c19d1205
ZW
10154/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10155 of an rs_align_code fragment. */
10156
10157void
10158arm_handle_align (fragS * fragP)
bfae80f2 10159{
c19d1205
ZW
10160 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
10161 static char const thumb_noop[2] = { 0xc0, 0x46 };
10162 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
10163 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
10164
10165 int bytes, fix, noop_size;
10166 char * p;
10167 const char * noop;
bfae80f2 10168
c19d1205 10169 if (fragP->fr_type != rs_align_code)
bfae80f2
RE
10170 return;
10171
c19d1205
ZW
10172 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
10173 p = fragP->fr_literal + fragP->fr_fix;
10174 fix = 0;
bfae80f2 10175
c19d1205
ZW
10176 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
10177 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
bfae80f2 10178
c19d1205 10179 if (fragP->tc_frag_data)
a737bd4d 10180 {
c19d1205
ZW
10181 if (target_big_endian)
10182 noop = thumb_bigend_noop;
10183 else
10184 noop = thumb_noop;
10185 noop_size = sizeof (thumb_noop);
7ed4c4c5
NC
10186 }
10187 else
10188 {
c19d1205
ZW
10189 if (target_big_endian)
10190 noop = arm_bigend_noop;
10191 else
10192 noop = arm_noop;
10193 noop_size = sizeof (arm_noop);
7ed4c4c5 10194 }
a737bd4d 10195
c19d1205 10196 if (bytes & (noop_size - 1))
7ed4c4c5 10197 {
c19d1205
ZW
10198 fix = bytes & (noop_size - 1);
10199 memset (p, 0, fix);
10200 p += fix;
10201 bytes -= fix;
a737bd4d 10202 }
a737bd4d 10203
c19d1205 10204 while (bytes >= noop_size)
a737bd4d 10205 {
c19d1205
ZW
10206 memcpy (p, noop, noop_size);
10207 p += noop_size;
10208 bytes -= noop_size;
10209 fix += noop_size;
a737bd4d
NC
10210 }
10211
c19d1205
ZW
10212 fragP->fr_fix += fix;
10213 fragP->fr_var = noop_size;
a737bd4d
NC
10214}
10215
c19d1205
ZW
10216/* Called from md_do_align. Used to create an alignment
10217 frag in a code section. */
10218
10219void
10220arm_frag_align_code (int n, int max)
bfae80f2 10221{
c19d1205 10222 char * p;
7ed4c4c5 10223
c19d1205
ZW
10224 /* We assume that there will never be a requirement
10225 to support alignments greater than 32 bytes. */
10226 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
10227 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
bfae80f2 10228
c19d1205
ZW
10229 p = frag_var (rs_align_code,
10230 MAX_MEM_FOR_RS_ALIGN_CODE,
10231 1,
10232 (relax_substateT) max,
10233 (symbolS *) NULL,
10234 (offsetT) n,
10235 (char *) NULL);
10236 *p = 0;
10237}
bfae80f2 10238
c19d1205 10239/* Perform target specific initialisation of a frag. */
bfae80f2 10240
c19d1205
ZW
10241void
10242arm_init_frag (fragS * fragP)
10243{
10244 /* Record whether this frag is in an ARM or a THUMB area. */
10245 fragP->tc_frag_data = thumb_mode;
bfae80f2
RE
10246}
10247
c19d1205
ZW
10248#ifdef OBJ_ELF
10249/* When we change sections we need to issue a new mapping symbol. */
10250
10251void
10252arm_elf_change_section (void)
bfae80f2 10253{
c19d1205
ZW
10254 flagword flags;
10255 segment_info_type *seginfo;
bfae80f2 10256
c19d1205
ZW
10257 /* Link an unlinked unwind index table section to the .text section. */
10258 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
10259 && elf_linked_to_section (now_seg) == NULL)
10260 elf_linked_to_section (now_seg) = text_section;
10261
10262 if (!SEG_NORMAL (now_seg))
bfae80f2
RE
10263 return;
10264
c19d1205
ZW
10265 flags = bfd_get_section_flags (stdoutput, now_seg);
10266
10267 /* We can ignore sections that only contain debug info. */
10268 if ((flags & SEC_ALLOC) == 0)
10269 return;
bfae80f2 10270
c19d1205
ZW
10271 seginfo = seg_info (now_seg);
10272 mapstate = seginfo->tc_segment_info_data.mapstate;
10273 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency;
bfae80f2
RE
10274}
10275
c19d1205
ZW
10276int
10277arm_elf_section_type (const char * str, size_t len)
e45d0630 10278{
c19d1205
ZW
10279 if (len == 5 && strncmp (str, "exidx", 5) == 0)
10280 return SHT_ARM_EXIDX;
e45d0630 10281
c19d1205
ZW
10282 return -1;
10283}
10284\f
10285/* Code to deal with unwinding tables. */
e45d0630 10286
c19d1205 10287static void add_unwind_adjustsp (offsetT);
e45d0630 10288
c19d1205 10289/* Cenerate and deferred unwind frame offset. */
e45d0630 10290
bfae80f2 10291static void
c19d1205 10292flush_pending_unwind (void)
bfae80f2 10293{
c19d1205 10294 offsetT offset;
bfae80f2 10295
c19d1205
ZW
10296 offset = unwind.pending_offset;
10297 unwind.pending_offset = 0;
10298 if (offset != 0)
10299 add_unwind_adjustsp (offset);
bfae80f2
RE
10300}
10301
c19d1205
ZW
10302/* Add an opcode to this list for this function. Two-byte opcodes should
10303 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
10304 order. */
10305
bfae80f2 10306static void
c19d1205 10307add_unwind_opcode (valueT op, int length)
bfae80f2 10308{
c19d1205
ZW
10309 /* Add any deferred stack adjustment. */
10310 if (unwind.pending_offset)
10311 flush_pending_unwind ();
bfae80f2 10312
c19d1205 10313 unwind.sp_restored = 0;
bfae80f2 10314
c19d1205 10315 if (unwind.opcode_count + length > unwind.opcode_alloc)
bfae80f2 10316 {
c19d1205
ZW
10317 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
10318 if (unwind.opcodes)
10319 unwind.opcodes = xrealloc (unwind.opcodes,
10320 unwind.opcode_alloc);
10321 else
10322 unwind.opcodes = xmalloc (unwind.opcode_alloc);
bfae80f2 10323 }
c19d1205 10324 while (length > 0)
bfae80f2 10325 {
c19d1205
ZW
10326 length--;
10327 unwind.opcodes[unwind.opcode_count] = op & 0xff;
10328 op >>= 8;
10329 unwind.opcode_count++;
bfae80f2 10330 }
bfae80f2
RE
10331}
10332
c19d1205
ZW
10333/* Add unwind opcodes to adjust the stack pointer. */
10334
bfae80f2 10335static void
c19d1205 10336add_unwind_adjustsp (offsetT offset)
bfae80f2 10337{
c19d1205 10338 valueT op;
bfae80f2 10339
c19d1205 10340 if (offset > 0x200)
bfae80f2 10341 {
c19d1205
ZW
10342 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
10343 char bytes[5];
10344 int n;
10345 valueT o;
bfae80f2 10346
c19d1205
ZW
10347 /* Long form: 0xb2, uleb128. */
10348 /* This might not fit in a word so add the individual bytes,
10349 remembering the list is built in reverse order. */
10350 o = (valueT) ((offset - 0x204) >> 2);
10351 if (o == 0)
10352 add_unwind_opcode (0, 1);
bfae80f2 10353
c19d1205
ZW
10354 /* Calculate the uleb128 encoding of the offset. */
10355 n = 0;
10356 while (o)
10357 {
10358 bytes[n] = o & 0x7f;
10359 o >>= 7;
10360 if (o)
10361 bytes[n] |= 0x80;
10362 n++;
10363 }
10364 /* Add the insn. */
10365 for (; n; n--)
10366 add_unwind_opcode (bytes[n - 1], 1);
10367 add_unwind_opcode (0xb2, 1);
10368 }
10369 else if (offset > 0x100)
bfae80f2 10370 {
c19d1205
ZW
10371 /* Two short opcodes. */
10372 add_unwind_opcode (0x3f, 1);
10373 op = (offset - 0x104) >> 2;
10374 add_unwind_opcode (op, 1);
bfae80f2 10375 }
c19d1205
ZW
10376 else if (offset > 0)
10377 {
10378 /* Short opcode. */
10379 op = (offset - 4) >> 2;
10380 add_unwind_opcode (op, 1);
10381 }
10382 else if (offset < 0)
bfae80f2 10383 {
c19d1205
ZW
10384 offset = -offset;
10385 while (offset > 0x100)
bfae80f2 10386 {
c19d1205
ZW
10387 add_unwind_opcode (0x7f, 1);
10388 offset -= 0x100;
bfae80f2 10389 }
c19d1205
ZW
10390 op = ((offset - 4) >> 2) | 0x40;
10391 add_unwind_opcode (op, 1);
bfae80f2 10392 }
bfae80f2
RE
10393}
10394
c19d1205
ZW
10395/* Finish the list of unwind opcodes for this function. */
10396static void
10397finish_unwind_opcodes (void)
bfae80f2 10398{
c19d1205 10399 valueT op;
bfae80f2 10400
c19d1205 10401 if (unwind.fp_used)
bfae80f2 10402 {
c19d1205
ZW
10403 /* Adjust sp as neccessary. */
10404 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
10405 flush_pending_unwind ();
bfae80f2 10406
c19d1205
ZW
10407 /* After restoring sp from the frame pointer. */
10408 op = 0x90 | unwind.fp_reg;
10409 add_unwind_opcode (op, 1);
10410 }
10411 else
10412 flush_pending_unwind ();
bfae80f2
RE
10413}
10414
bfae80f2 10415
c19d1205
ZW
10416/* Start an exception table entry. If idx is nonzero this is an index table
10417 entry. */
bfae80f2
RE
10418
10419static void
c19d1205 10420start_unwind_section (const segT text_seg, int idx)
bfae80f2 10421{
c19d1205
ZW
10422 const char * text_name;
10423 const char * prefix;
10424 const char * prefix_once;
10425 const char * group_name;
10426 size_t prefix_len;
10427 size_t text_len;
10428 char * sec_name;
10429 size_t sec_name_len;
10430 int type;
10431 int flags;
10432 int linkonce;
bfae80f2 10433
c19d1205 10434 if (idx)
bfae80f2 10435 {
c19d1205
ZW
10436 prefix = ELF_STRING_ARM_unwind;
10437 prefix_once = ELF_STRING_ARM_unwind_once;
10438 type = SHT_ARM_EXIDX;
bfae80f2 10439 }
c19d1205 10440 else
bfae80f2 10441 {
c19d1205
ZW
10442 prefix = ELF_STRING_ARM_unwind_info;
10443 prefix_once = ELF_STRING_ARM_unwind_info_once;
10444 type = SHT_PROGBITS;
bfae80f2
RE
10445 }
10446
c19d1205
ZW
10447 text_name = segment_name (text_seg);
10448 if (streq (text_name, ".text"))
10449 text_name = "";
10450
10451 if (strncmp (text_name, ".gnu.linkonce.t.",
10452 strlen (".gnu.linkonce.t.")) == 0)
bfae80f2 10453 {
c19d1205
ZW
10454 prefix = prefix_once;
10455 text_name += strlen (".gnu.linkonce.t.");
bfae80f2
RE
10456 }
10457
c19d1205
ZW
10458 prefix_len = strlen (prefix);
10459 text_len = strlen (text_name);
10460 sec_name_len = prefix_len + text_len;
10461 sec_name = xmalloc (sec_name_len + 1);
10462 memcpy (sec_name, prefix, prefix_len);
10463 memcpy (sec_name + prefix_len, text_name, text_len);
10464 sec_name[prefix_len + text_len] = '\0';
bfae80f2 10465
c19d1205
ZW
10466 flags = SHF_ALLOC;
10467 linkonce = 0;
10468 group_name = 0;
bfae80f2 10469
c19d1205
ZW
10470 /* Handle COMDAT group. */
10471 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
bfae80f2 10472 {
c19d1205
ZW
10473 group_name = elf_group_name (text_seg);
10474 if (group_name == NULL)
10475 {
10476 as_bad ("Group section `%s' has no group signature",
10477 segment_name (text_seg));
10478 ignore_rest_of_line ();
10479 return;
10480 }
10481 flags |= SHF_GROUP;
10482 linkonce = 1;
bfae80f2
RE
10483 }
10484
c19d1205 10485 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
bfae80f2 10486
c19d1205
ZW
10487 /* Set the setion link for index tables. */
10488 if (idx)
10489 elf_linked_to_section (now_seg) = text_seg;
bfae80f2
RE
10490}
10491
bfae80f2 10492
c19d1205
ZW
10493/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
10494 personality routine data. Returns zero, or the index table value for
10495 and inline entry. */
10496
10497static valueT
10498create_unwind_entry (int have_data)
bfae80f2 10499{
c19d1205
ZW
10500 int size;
10501 addressT where;
10502 char *ptr;
10503 /* The current word of data. */
10504 valueT data;
10505 /* The number of bytes left in this word. */
10506 int n;
bfae80f2 10507
c19d1205 10508 finish_unwind_opcodes ();
bfae80f2 10509
c19d1205
ZW
10510 /* Remember the current text section. */
10511 unwind.saved_seg = now_seg;
10512 unwind.saved_subseg = now_subseg;
bfae80f2 10513
c19d1205 10514 start_unwind_section (now_seg, 0);
bfae80f2 10515
c19d1205 10516 if (unwind.personality_routine == NULL)
bfae80f2 10517 {
c19d1205
ZW
10518 if (unwind.personality_index == -2)
10519 {
10520 if (have_data)
10521 as_bad (_("handerdata in cantunwind frame"));
10522 return 1; /* EXIDX_CANTUNWIND. */
10523 }
bfae80f2 10524
c19d1205
ZW
10525 /* Use a default personality routine if none is specified. */
10526 if (unwind.personality_index == -1)
10527 {
10528 if (unwind.opcode_count > 3)
10529 unwind.personality_index = 1;
10530 else
10531 unwind.personality_index = 0;
10532 }
bfae80f2 10533
c19d1205
ZW
10534 /* Space for the personality routine entry. */
10535 if (unwind.personality_index == 0)
10536 {
10537 if (unwind.opcode_count > 3)
10538 as_bad (_("too many unwind opcodes for personality routine 0"));
bfae80f2 10539
c19d1205
ZW
10540 if (!have_data)
10541 {
10542 /* All the data is inline in the index table. */
10543 data = 0x80;
10544 n = 3;
10545 while (unwind.opcode_count > 0)
10546 {
10547 unwind.opcode_count--;
10548 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
10549 n--;
10550 }
bfae80f2 10551
c19d1205
ZW
10552 /* Pad with "finish" opcodes. */
10553 while (n--)
10554 data = (data << 8) | 0xb0;
bfae80f2 10555
c19d1205
ZW
10556 return data;
10557 }
10558 size = 0;
10559 }
10560 else
10561 /* We get two opcodes "free" in the first word. */
10562 size = unwind.opcode_count - 2;
10563 }
10564 else
10565 /* An extra byte is required for the opcode count. */
10566 size = unwind.opcode_count + 1;
bfae80f2 10567
c19d1205
ZW
10568 size = (size + 3) >> 2;
10569 if (size > 0xff)
10570 as_bad (_("too many unwind opcodes"));
bfae80f2 10571
c19d1205
ZW
10572 frag_align (2, 0, 0);
10573 record_alignment (now_seg, 2);
10574 unwind.table_entry = expr_build_dot ();
10575
10576 /* Allocate the table entry. */
10577 ptr = frag_more ((size << 2) + 4);
10578 where = frag_now_fix () - ((size << 2) + 4);
bfae80f2 10579
c19d1205 10580 switch (unwind.personality_index)
bfae80f2 10581 {
c19d1205
ZW
10582 case -1:
10583 /* ??? Should this be a PLT generating relocation? */
10584 /* Custom personality routine. */
10585 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
10586 BFD_RELOC_ARM_PREL31);
bfae80f2 10587
c19d1205
ZW
10588 where += 4;
10589 ptr += 4;
bfae80f2 10590
c19d1205
ZW
10591 /* Set the first byte to the number of additional words. */
10592 data = size - 1;
10593 n = 3;
10594 break;
bfae80f2 10595
c19d1205
ZW
10596 /* ABI defined personality routines. */
10597 case 0:
10598 /* Three opcodes bytes are packed into the first word. */
10599 data = 0x80;
10600 n = 3;
10601 break;
bfae80f2 10602
c19d1205
ZW
10603 case 1:
10604 case 2:
10605 /* The size and first two opcode bytes go in the first word. */
10606 data = ((0x80 + unwind.personality_index) << 8) | size;
10607 n = 2;
10608 break;
bfae80f2 10609
c19d1205
ZW
10610 default:
10611 /* Should never happen. */
10612 abort ();
10613 }
bfae80f2 10614
c19d1205
ZW
10615 /* Pack the opcodes into words (MSB first), reversing the list at the same
10616 time. */
10617 while (unwind.opcode_count > 0)
10618 {
10619 if (n == 0)
10620 {
10621 md_number_to_chars (ptr, data, 4);
10622 ptr += 4;
10623 n = 4;
10624 data = 0;
10625 }
10626 unwind.opcode_count--;
10627 n--;
10628 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
10629 }
10630
10631 /* Finish off the last word. */
10632 if (n < 4)
10633 {
10634 /* Pad with "finish" opcodes. */
10635 while (n--)
10636 data = (data << 8) | 0xb0;
10637
10638 md_number_to_chars (ptr, data, 4);
10639 }
10640
10641 if (!have_data)
10642 {
10643 /* Add an empty descriptor if there is no user-specified data. */
10644 ptr = frag_more (4);
10645 md_number_to_chars (ptr, 0, 4);
10646 }
10647
10648 return 0;
bfae80f2
RE
10649}
10650
c19d1205
ZW
10651/* Convert REGNAME to a DWARF-2 register number. */
10652
10653int
10654tc_arm_regname_to_dw2regnum (const char *regname)
bfae80f2 10655{
c19d1205
ZW
10656 int reg = arm_reg_parse ((char **) &regname, REG_TYPE_RN);
10657
10658 if (reg == FAIL)
10659 return -1;
10660
10661 return reg;
bfae80f2
RE
10662}
10663
c19d1205
ZW
10664/* Initialize the DWARF-2 unwind information for this procedure. */
10665
10666void
10667tc_arm_frame_initial_instructions (void)
bfae80f2 10668{
c19d1205 10669 cfi_add_CFA_def_cfa (REG_SP, 0);
bfae80f2 10670}
c19d1205 10671#endif /* OBJ_ELF */
bfae80f2 10672
bfae80f2 10673
c19d1205 10674/* MD interface: Symbol and relocation handling. */
bfae80f2 10675
2fc8bdac
ZW
10676/* Return the address within the segment that a PC-relative fixup is
10677 relative to. For ARM, PC-relative fixups applied to instructions
10678 are generally relative to the location of the fixup plus 8 bytes.
10679 Thumb branches are offset by 4, and Thumb loads relative to PC
10680 require special handling. */
bfae80f2 10681
c19d1205 10682long
2fc8bdac 10683md_pcrel_from_section (fixS * fixP, segT seg)
bfae80f2 10684{
2fc8bdac
ZW
10685 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
10686
10687 /* If this is pc-relative and we are going to emit a relocation
10688 then we just want to put out any pipeline compensation that the linker
10689 will need. Otherwise we want to use the calculated base. */
10690 if (fixP->fx_pcrel
10691 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
10692 || arm_force_relocation (fixP)))
10693 base = 0;
bfae80f2 10694
c19d1205 10695 switch (fixP->fx_r_type)
bfae80f2 10696 {
2fc8bdac
ZW
10697 /* PC relative addressing on the Thumb is slightly odd as the
10698 bottom two bits of the PC are forced to zero for the
10699 calculation. This happens *after* application of the
10700 pipeline offset. However, Thumb adrl already adjusts for
10701 this, so we need not do it again. */
c19d1205 10702 case BFD_RELOC_ARM_THUMB_ADD:
2fc8bdac 10703 return base & ~3;
c19d1205
ZW
10704
10705 case BFD_RELOC_ARM_THUMB_OFFSET:
10706 case BFD_RELOC_ARM_T32_OFFSET_IMM:
e9f89963 10707 case BFD_RELOC_ARM_T32_ADD_PC12:
8f06b2d8 10708 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
2fc8bdac 10709 return (base + 4) & ~3;
c19d1205 10710
2fc8bdac
ZW
10711 /* Thumb branches are simply offset by +4. */
10712 case BFD_RELOC_THUMB_PCREL_BRANCH7:
10713 case BFD_RELOC_THUMB_PCREL_BRANCH9:
10714 case BFD_RELOC_THUMB_PCREL_BRANCH12:
10715 case BFD_RELOC_THUMB_PCREL_BRANCH20:
10716 case BFD_RELOC_THUMB_PCREL_BRANCH23:
10717 case BFD_RELOC_THUMB_PCREL_BRANCH25:
10718 case BFD_RELOC_THUMB_PCREL_BLX:
10719 return base + 4;
bfae80f2 10720
2fc8bdac
ZW
10721 /* ARM mode branches are offset by +8. However, the Windows CE
10722 loader expects the relocation not to take this into account. */
10723 case BFD_RELOC_ARM_PCREL_BRANCH:
10724 case BFD_RELOC_ARM_PCREL_BLX:
10725 case BFD_RELOC_ARM_PLT32:
c19d1205 10726#ifdef TE_WINCE
2fc8bdac 10727 return base;
c19d1205 10728#else
2fc8bdac 10729 return base + 8;
c19d1205 10730#endif
2fc8bdac
ZW
10731
10732 /* ARM mode loads relative to PC are also offset by +8. Unlike
10733 branches, the Windows CE loader *does* expect the relocation
10734 to take this into account. */
10735 case BFD_RELOC_ARM_OFFSET_IMM:
10736 case BFD_RELOC_ARM_OFFSET_IMM8:
10737 case BFD_RELOC_ARM_HWLITERAL:
10738 case BFD_RELOC_ARM_LITERAL:
10739 case BFD_RELOC_ARM_CP_OFF_IMM:
10740 return base + 8;
10741
10742
10743 /* Other PC-relative relocations are un-offset. */
10744 default:
10745 return base;
10746 }
bfae80f2
RE
10747}
10748
c19d1205
ZW
10749/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
10750 Otherwise we have no need to default values of symbols. */
10751
10752symbolS *
10753md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
bfae80f2 10754{
c19d1205
ZW
10755#ifdef OBJ_ELF
10756 if (name[0] == '_' && name[1] == 'G'
10757 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
10758 {
10759 if (!GOT_symbol)
10760 {
10761 if (symbol_find (name))
10762 as_bad ("GOT already in the symbol table");
bfae80f2 10763
c19d1205
ZW
10764 GOT_symbol = symbol_new (name, undefined_section,
10765 (valueT) 0, & zero_address_frag);
10766 }
bfae80f2 10767
c19d1205 10768 return GOT_symbol;
bfae80f2 10769 }
c19d1205 10770#endif
bfae80f2 10771
c19d1205 10772 return 0;
bfae80f2
RE
10773}
10774
55cf6793 10775/* Subroutine of md_apply_fix. Check to see if an immediate can be
c19d1205
ZW
10776 computed as two separate immediate values, added together. We
10777 already know that this value cannot be computed by just one ARM
10778 instruction. */
10779
10780static unsigned int
10781validate_immediate_twopart (unsigned int val,
10782 unsigned int * highpart)
bfae80f2 10783{
c19d1205
ZW
10784 unsigned int a;
10785 unsigned int i;
bfae80f2 10786
c19d1205
ZW
10787 for (i = 0; i < 32; i += 2)
10788 if (((a = rotate_left (val, i)) & 0xff) != 0)
10789 {
10790 if (a & 0xff00)
10791 {
10792 if (a & ~ 0xffff)
10793 continue;
10794 * highpart = (a >> 8) | ((i + 24) << 7);
10795 }
10796 else if (a & 0xff0000)
10797 {
10798 if (a & 0xff000000)
10799 continue;
10800 * highpart = (a >> 16) | ((i + 16) << 7);
10801 }
10802 else
10803 {
10804 assert (a & 0xff000000);
10805 * highpart = (a >> 24) | ((i + 8) << 7);
10806 }
bfae80f2 10807
c19d1205
ZW
10808 return (a & 0xff) | (i << 7);
10809 }
bfae80f2 10810
c19d1205 10811 return FAIL;
bfae80f2
RE
10812}
10813
c19d1205
ZW
10814static int
10815validate_offset_imm (unsigned int val, int hwse)
10816{
10817 if ((hwse && val > 255) || val > 4095)
10818 return FAIL;
10819 return val;
10820}
bfae80f2 10821
55cf6793 10822/* Subroutine of md_apply_fix. Do those data_ops which can take a
c19d1205
ZW
10823 negative immediate constant by altering the instruction. A bit of
10824 a hack really.
10825 MOV <-> MVN
10826 AND <-> BIC
10827 ADC <-> SBC
10828 by inverting the second operand, and
10829 ADD <-> SUB
10830 CMP <-> CMN
10831 by negating the second operand. */
bfae80f2 10832
c19d1205
ZW
10833static int
10834negate_data_op (unsigned long * instruction,
10835 unsigned long value)
bfae80f2 10836{
c19d1205
ZW
10837 int op, new_inst;
10838 unsigned long negated, inverted;
bfae80f2 10839
c19d1205
ZW
10840 negated = encode_arm_immediate (-value);
10841 inverted = encode_arm_immediate (~value);
bfae80f2 10842
c19d1205
ZW
10843 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
10844 switch (op)
bfae80f2 10845 {
c19d1205
ZW
10846 /* First negates. */
10847 case OPCODE_SUB: /* ADD <-> SUB */
10848 new_inst = OPCODE_ADD;
10849 value = negated;
10850 break;
bfae80f2 10851
c19d1205
ZW
10852 case OPCODE_ADD:
10853 new_inst = OPCODE_SUB;
10854 value = negated;
10855 break;
bfae80f2 10856
c19d1205
ZW
10857 case OPCODE_CMP: /* CMP <-> CMN */
10858 new_inst = OPCODE_CMN;
10859 value = negated;
10860 break;
bfae80f2 10861
c19d1205
ZW
10862 case OPCODE_CMN:
10863 new_inst = OPCODE_CMP;
10864 value = negated;
10865 break;
bfae80f2 10866
c19d1205
ZW
10867 /* Now Inverted ops. */
10868 case OPCODE_MOV: /* MOV <-> MVN */
10869 new_inst = OPCODE_MVN;
10870 value = inverted;
10871 break;
bfae80f2 10872
c19d1205
ZW
10873 case OPCODE_MVN:
10874 new_inst = OPCODE_MOV;
10875 value = inverted;
10876 break;
bfae80f2 10877
c19d1205
ZW
10878 case OPCODE_AND: /* AND <-> BIC */
10879 new_inst = OPCODE_BIC;
10880 value = inverted;
10881 break;
bfae80f2 10882
c19d1205
ZW
10883 case OPCODE_BIC:
10884 new_inst = OPCODE_AND;
10885 value = inverted;
10886 break;
bfae80f2 10887
c19d1205
ZW
10888 case OPCODE_ADC: /* ADC <-> SBC */
10889 new_inst = OPCODE_SBC;
10890 value = inverted;
10891 break;
bfae80f2 10892
c19d1205
ZW
10893 case OPCODE_SBC:
10894 new_inst = OPCODE_ADC;
10895 value = inverted;
10896 break;
bfae80f2 10897
c19d1205
ZW
10898 /* We cannot do anything. */
10899 default:
10900 return FAIL;
b99bd4ef
NC
10901 }
10902
c19d1205
ZW
10903 if (value == (unsigned) FAIL)
10904 return FAIL;
10905
10906 *instruction &= OPCODE_MASK;
10907 *instruction |= new_inst << DATA_OP_SHIFT;
10908 return value;
b99bd4ef
NC
10909}
10910
8f06b2d8
PB
10911/* Read a 32-bit thumb instruction from buf. */
10912static unsigned long
10913get_thumb32_insn (char * buf)
10914{
10915 unsigned long insn;
10916 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
10917 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
10918
10919 return insn;
10920}
10921
c19d1205 10922void
55cf6793 10923md_apply_fix (fixS * fixP,
c19d1205
ZW
10924 valueT * valP,
10925 segT seg)
10926{
10927 offsetT value = * valP;
10928 offsetT newval;
10929 unsigned int newimm;
10930 unsigned long temp;
10931 int sign;
10932 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
b99bd4ef 10933
c19d1205 10934 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
b99bd4ef 10935
c19d1205
ZW
10936 /* Note whether this will delete the relocation. */
10937 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
10938 fixP->fx_done = 1;
b99bd4ef 10939
adbaf948
ZW
10940 /* On a 64-bit host, silently truncate 'value' to 32 bits for
10941 consistency with the behavior on 32-bit hosts. Remember value
10942 for emit_reloc. */
10943 value &= 0xffffffff;
10944 value ^= 0x80000000;
10945 value -= 0x80000000;
10946
10947 *valP = value;
c19d1205 10948 fixP->fx_addnumber = value;
b99bd4ef 10949
adbaf948
ZW
10950 /* Same treatment for fixP->fx_offset. */
10951 fixP->fx_offset &= 0xffffffff;
10952 fixP->fx_offset ^= 0x80000000;
10953 fixP->fx_offset -= 0x80000000;
10954
c19d1205 10955 switch (fixP->fx_r_type)
b99bd4ef 10956 {
c19d1205
ZW
10957 case BFD_RELOC_NONE:
10958 /* This will need to go in the object file. */
10959 fixP->fx_done = 0;
10960 break;
b99bd4ef 10961
c19d1205
ZW
10962 case BFD_RELOC_ARM_IMMEDIATE:
10963 /* We claim that this fixup has been processed here,
10964 even if in fact we generate an error because we do
10965 not have a reloc for it, so tc_gen_reloc will reject it. */
10966 fixP->fx_done = 1;
b99bd4ef 10967
c19d1205
ZW
10968 if (fixP->fx_addsy
10969 && ! S_IS_DEFINED (fixP->fx_addsy))
b99bd4ef 10970 {
c19d1205
ZW
10971 as_bad_where (fixP->fx_file, fixP->fx_line,
10972 _("undefined symbol %s used as an immediate value"),
10973 S_GET_NAME (fixP->fx_addsy));
10974 break;
b99bd4ef
NC
10975 }
10976
c19d1205
ZW
10977 newimm = encode_arm_immediate (value);
10978 temp = md_chars_to_number (buf, INSN_SIZE);
10979
10980 /* If the instruction will fail, see if we can fix things up by
10981 changing the opcode. */
10982 if (newimm == (unsigned int) FAIL
10983 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
b99bd4ef 10984 {
c19d1205
ZW
10985 as_bad_where (fixP->fx_file, fixP->fx_line,
10986 _("invalid constant (%lx) after fixup"),
10987 (unsigned long) value);
10988 break;
b99bd4ef 10989 }
b99bd4ef 10990
c19d1205
ZW
10991 newimm |= (temp & 0xfffff000);
10992 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
10993 break;
b99bd4ef 10994
c19d1205
ZW
10995 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
10996 {
10997 unsigned int highpart = 0;
10998 unsigned int newinsn = 0xe1a00000; /* nop. */
b99bd4ef 10999
c19d1205
ZW
11000 newimm = encode_arm_immediate (value);
11001 temp = md_chars_to_number (buf, INSN_SIZE);
b99bd4ef 11002
c19d1205
ZW
11003 /* If the instruction will fail, see if we can fix things up by
11004 changing the opcode. */
11005 if (newimm == (unsigned int) FAIL
11006 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
11007 {
11008 /* No ? OK - try using two ADD instructions to generate
11009 the value. */
11010 newimm = validate_immediate_twopart (value, & highpart);
b99bd4ef 11011
c19d1205
ZW
11012 /* Yes - then make sure that the second instruction is
11013 also an add. */
11014 if (newimm != (unsigned int) FAIL)
11015 newinsn = temp;
11016 /* Still No ? Try using a negated value. */
11017 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
11018 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
11019 /* Otherwise - give up. */
11020 else
11021 {
11022 as_bad_where (fixP->fx_file, fixP->fx_line,
11023 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
11024 (long) value);
11025 break;
11026 }
b99bd4ef 11027
c19d1205
ZW
11028 /* Replace the first operand in the 2nd instruction (which
11029 is the PC) with the destination register. We have
11030 already added in the PC in the first instruction and we
11031 do not want to do it again. */
11032 newinsn &= ~ 0xf0000;
11033 newinsn |= ((newinsn & 0x0f000) << 4);
11034 }
b99bd4ef 11035
c19d1205
ZW
11036 newimm |= (temp & 0xfffff000);
11037 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
b99bd4ef 11038
c19d1205
ZW
11039 highpart |= (newinsn & 0xfffff000);
11040 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
11041 }
11042 break;
b99bd4ef 11043
c19d1205
ZW
11044 case BFD_RELOC_ARM_OFFSET_IMM:
11045 case BFD_RELOC_ARM_LITERAL:
11046 sign = value >= 0;
b99bd4ef 11047
c19d1205
ZW
11048 if (value < 0)
11049 value = - value;
b99bd4ef 11050
c19d1205 11051 if (validate_offset_imm (value, 0) == FAIL)
f03698e6 11052 {
c19d1205
ZW
11053 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
11054 as_bad_where (fixP->fx_file, fixP->fx_line,
11055 _("invalid literal constant: pool needs to be closer"));
11056 else
11057 as_bad_where (fixP->fx_file, fixP->fx_line,
11058 _("bad immediate value for offset (%ld)"),
11059 (long) value);
11060 break;
f03698e6
RE
11061 }
11062
c19d1205
ZW
11063 newval = md_chars_to_number (buf, INSN_SIZE);
11064 newval &= 0xff7ff000;
11065 newval |= value | (sign ? INDEX_UP : 0);
11066 md_number_to_chars (buf, newval, INSN_SIZE);
11067 break;
b99bd4ef 11068
c19d1205
ZW
11069 case BFD_RELOC_ARM_OFFSET_IMM8:
11070 case BFD_RELOC_ARM_HWLITERAL:
11071 sign = value >= 0;
b99bd4ef 11072
c19d1205
ZW
11073 if (value < 0)
11074 value = - value;
b99bd4ef 11075
c19d1205 11076 if (validate_offset_imm (value, 1) == FAIL)
b99bd4ef 11077 {
c19d1205
ZW
11078 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
11079 as_bad_where (fixP->fx_file, fixP->fx_line,
11080 _("invalid literal constant: pool needs to be closer"));
11081 else
11082 as_bad (_("bad immediate value for half-word offset (%ld)"),
11083 (long) value);
11084 break;
b99bd4ef
NC
11085 }
11086
c19d1205
ZW
11087 newval = md_chars_to_number (buf, INSN_SIZE);
11088 newval &= 0xff7ff0f0;
11089 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
11090 md_number_to_chars (buf, newval, INSN_SIZE);
11091 break;
b99bd4ef 11092
c19d1205
ZW
11093 case BFD_RELOC_ARM_T32_OFFSET_U8:
11094 if (value < 0 || value > 1020 || value % 4 != 0)
11095 as_bad_where (fixP->fx_file, fixP->fx_line,
11096 _("bad immediate value for offset (%ld)"), (long) value);
11097 value /= 4;
b99bd4ef 11098
c19d1205 11099 newval = md_chars_to_number (buf+2, THUMB_SIZE);
c19d1205
ZW
11100 newval |= value;
11101 md_number_to_chars (buf+2, newval, THUMB_SIZE);
11102 break;
b99bd4ef 11103
c19d1205
ZW
11104 case BFD_RELOC_ARM_T32_OFFSET_IMM:
11105 /* This is a complicated relocation used for all varieties of Thumb32
11106 load/store instruction with immediate offset:
11107
11108 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
11109 *4, optional writeback(W)
11110 (doubleword load/store)
11111
11112 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
11113 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
11114 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
11115 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
11116 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
11117
11118 Uppercase letters indicate bits that are already encoded at
11119 this point. Lowercase letters are our problem. For the
11120 second block of instructions, the secondary opcode nybble
11121 (bits 8..11) is present, and bit 23 is zero, even if this is
11122 a PC-relative operation. */
11123 newval = md_chars_to_number (buf, THUMB_SIZE);
11124 newval <<= 16;
11125 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
b99bd4ef 11126
c19d1205 11127 if ((newval & 0xf0000000) == 0xe0000000)
b99bd4ef 11128 {
c19d1205
ZW
11129 /* Doubleword load/store: 8-bit offset, scaled by 4. */
11130 if (value >= 0)
11131 newval |= (1 << 23);
11132 else
11133 value = -value;
11134 if (value % 4 != 0)
11135 {
11136 as_bad_where (fixP->fx_file, fixP->fx_line,
11137 _("offset not a multiple of 4"));
11138 break;
11139 }
11140 value /= 4;
11141 if (value >= 0xff)
11142 {
11143 as_bad_where (fixP->fx_file, fixP->fx_line,
11144 _("offset out of range"));
11145 break;
11146 }
11147 newval &= ~0xff;
b99bd4ef 11148 }
c19d1205 11149 else if ((newval & 0x000f0000) == 0x000f0000)
b99bd4ef 11150 {
c19d1205
ZW
11151 /* PC-relative, 12-bit offset. */
11152 if (value >= 0)
11153 newval |= (1 << 23);
11154 else
11155 value = -value;
11156 if (value >= 0xfff)
11157 {
11158 as_bad_where (fixP->fx_file, fixP->fx_line,
11159 _("offset out of range"));
11160 break;
11161 }
11162 newval &= ~0xfff;
b99bd4ef 11163 }
c19d1205 11164 else if ((newval & 0x00000100) == 0x00000100)
b99bd4ef 11165 {
c19d1205
ZW
11166 /* Writeback: 8-bit, +/- offset. */
11167 if (value >= 0)
11168 newval |= (1 << 9);
11169 else
11170 value = -value;
11171 if (value >= 0xff)
11172 {
11173 as_bad_where (fixP->fx_file, fixP->fx_line,
11174 _("offset out of range"));
11175 break;
11176 }
11177 newval &= ~0xff;
b99bd4ef 11178 }
c19d1205 11179 else if ((newval & 0x00000f00) == 0x00000e00)
b99bd4ef 11180 {
c19d1205
ZW
11181 /* T-instruction: positive 8-bit offset. */
11182 if (value < 0 || value >= 0xff)
b99bd4ef 11183 {
c19d1205
ZW
11184 as_bad_where (fixP->fx_file, fixP->fx_line,
11185 _("offset out of range"));
11186 break;
b99bd4ef 11187 }
c19d1205
ZW
11188 newval &= ~0xff;
11189 newval |= value;
b99bd4ef
NC
11190 }
11191 else
b99bd4ef 11192 {
c19d1205
ZW
11193 /* Positive 12-bit or negative 8-bit offset. */
11194 int limit;
11195 if (value >= 0)
b99bd4ef 11196 {
c19d1205
ZW
11197 newval |= (1 << 23);
11198 limit = 0xfff;
11199 }
11200 else
11201 {
11202 value = -value;
11203 limit = 0xff;
11204 }
11205 if (value > limit)
11206 {
11207 as_bad_where (fixP->fx_file, fixP->fx_line,
11208 _("offset out of range"));
11209 break;
b99bd4ef 11210 }
c19d1205 11211 newval &= ~limit;
b99bd4ef 11212 }
b99bd4ef 11213
c19d1205
ZW
11214 newval |= value;
11215 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
11216 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
11217 break;
404ff6b5 11218
c19d1205
ZW
11219 case BFD_RELOC_ARM_SHIFT_IMM:
11220 newval = md_chars_to_number (buf, INSN_SIZE);
11221 if (((unsigned long) value) > 32
11222 || (value == 32
11223 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
11224 {
11225 as_bad_where (fixP->fx_file, fixP->fx_line,
11226 _("shift expression is too large"));
11227 break;
11228 }
404ff6b5 11229
c19d1205
ZW
11230 if (value == 0)
11231 /* Shifts of zero must be done as lsl. */
11232 newval &= ~0x60;
11233 else if (value == 32)
11234 value = 0;
11235 newval &= 0xfffff07f;
11236 newval |= (value & 0x1f) << 7;
11237 md_number_to_chars (buf, newval, INSN_SIZE);
11238 break;
404ff6b5 11239
c19d1205 11240 case BFD_RELOC_ARM_T32_IMMEDIATE:
92e90b6e 11241 case BFD_RELOC_ARM_T32_IMM12:
e9f89963 11242 case BFD_RELOC_ARM_T32_ADD_PC12:
c19d1205
ZW
11243 /* We claim that this fixup has been processed here,
11244 even if in fact we generate an error because we do
11245 not have a reloc for it, so tc_gen_reloc will reject it. */
11246 fixP->fx_done = 1;
404ff6b5 11247
c19d1205
ZW
11248 if (fixP->fx_addsy
11249 && ! S_IS_DEFINED (fixP->fx_addsy))
11250 {
11251 as_bad_where (fixP->fx_file, fixP->fx_line,
11252 _("undefined symbol %s used as an immediate value"),
11253 S_GET_NAME (fixP->fx_addsy));
11254 break;
11255 }
404ff6b5 11256
c19d1205
ZW
11257 newval = md_chars_to_number (buf, THUMB_SIZE);
11258 newval <<= 16;
11259 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
404ff6b5 11260
e9f89963
PB
11261 /* FUTURE: Implement analogue of negate_data_op for T32. */
11262 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE)
11263 newimm = encode_thumb32_immediate (value);
11264 else
92e90b6e 11265 {
e9f89963
PB
11266 /* 12 bit immediate for addw/subw. */
11267 if (value < 0)
11268 {
11269 value = -value;
11270 newval ^= 0x00a00000;
11271 }
92e90b6e
PB
11272 if (value > 0xfff)
11273 newimm = (unsigned int) FAIL;
11274 else
11275 newimm = value;
11276 }
cc8a6dd0 11277
c19d1205 11278 if (newimm == (unsigned int)FAIL)
3631a3c8 11279 {
c19d1205
ZW
11280 as_bad_where (fixP->fx_file, fixP->fx_line,
11281 _("invalid constant (%lx) after fixup"),
11282 (unsigned long) value);
11283 break;
3631a3c8
NC
11284 }
11285
c19d1205
ZW
11286 newval |= (newimm & 0x800) << 15;
11287 newval |= (newimm & 0x700) << 4;
11288 newval |= (newimm & 0x0ff);
cc8a6dd0 11289
c19d1205
ZW
11290 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
11291 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
11292 break;
a737bd4d 11293
3eb17e6b 11294 case BFD_RELOC_ARM_SMC:
c19d1205
ZW
11295 if (((unsigned long) value) > 0xffff)
11296 as_bad_where (fixP->fx_file, fixP->fx_line,
3eb17e6b 11297 _("invalid smc expression"));
2fc8bdac 11298 newval = md_chars_to_number (buf, INSN_SIZE);
c19d1205
ZW
11299 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
11300 md_number_to_chars (buf, newval, INSN_SIZE);
11301 break;
a737bd4d 11302
c19d1205 11303 case BFD_RELOC_ARM_SWI:
adbaf948 11304 if (fixP->tc_fix_data != 0)
c19d1205
ZW
11305 {
11306 if (((unsigned long) value) > 0xff)
11307 as_bad_where (fixP->fx_file, fixP->fx_line,
11308 _("invalid swi expression"));
2fc8bdac 11309 newval = md_chars_to_number (buf, THUMB_SIZE);
c19d1205
ZW
11310 newval |= value;
11311 md_number_to_chars (buf, newval, THUMB_SIZE);
11312 }
11313 else
11314 {
11315 if (((unsigned long) value) > 0x00ffffff)
11316 as_bad_where (fixP->fx_file, fixP->fx_line,
11317 _("invalid swi expression"));
2fc8bdac 11318 newval = md_chars_to_number (buf, INSN_SIZE);
c19d1205
ZW
11319 newval |= value;
11320 md_number_to_chars (buf, newval, INSN_SIZE);
11321 }
11322 break;
a737bd4d 11323
c19d1205
ZW
11324 case BFD_RELOC_ARM_MULTI:
11325 if (((unsigned long) value) > 0xffff)
11326 as_bad_where (fixP->fx_file, fixP->fx_line,
11327 _("invalid expression in load/store multiple"));
11328 newval = value | md_chars_to_number (buf, INSN_SIZE);
11329 md_number_to_chars (buf, newval, INSN_SIZE);
11330 break;
a737bd4d 11331
c19d1205 11332 case BFD_RELOC_ARM_PCREL_BRANCH:
c19d1205 11333#ifdef OBJ_ELF
2fc8bdac 11334 case BFD_RELOC_ARM_PLT32:
c19d1205 11335#endif
a737bd4d 11336
c19d1205 11337 /* We are going to store value (shifted right by two) in the
2fc8bdac
ZW
11338 instruction, in a 24 bit, signed field. Bits 0 and 1 must be
11339 clear, and bits 26 through 32 either all clear or all set. */
11340 if (value & 0x00000003)
c19d1205 11341 as_bad_where (fixP->fx_file, fixP->fx_line,
2fc8bdac
ZW
11342 _("misaligned branch destination"));
11343 if ((value & (offsetT)0xfe000000) != (offsetT)0
11344 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
11345 as_bad_where (fixP->fx_file, fixP->fx_line,
11346 _("branch out of range"));
a737bd4d 11347
2fc8bdac 11348 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 11349 {
2fc8bdac
ZW
11350 newval = md_chars_to_number (buf, INSN_SIZE);
11351 newval |= (value >> 2) & 0x00ffffff;
11352 md_number_to_chars (buf, newval, INSN_SIZE);
c19d1205 11353 }
c19d1205 11354 break;
a737bd4d 11355
c19d1205 11356 case BFD_RELOC_ARM_PCREL_BLX:
2fc8bdac
ZW
11357 /* BLX allows bit 1 to be set in the branch destination, since
11358 it targets a Thumb instruction which is only required to be
11359 aligned modulo 2. Other constraints are as for B/BL. */
11360 if (value & 0x00000001)
11361 as_bad_where (fixP->fx_file, fixP->fx_line,
11362 _("misaligned BLX destination"));
11363 if ((value & (offsetT)0xfe000000) != (offsetT)0
11364 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
11365 as_bad_where (fixP->fx_file, fixP->fx_line,
11366 _("branch out of range"));
a737bd4d 11367
2fc8bdac
ZW
11368 if (fixP->fx_done || !seg->use_rela_p)
11369 {
11370 offsetT hbit;
11371 hbit = (value >> 1) & 1;
11372 value = (value >> 2) & 0x00ffffff;
a737bd4d 11373
2fc8bdac
ZW
11374 newval = md_chars_to_number (buf, INSN_SIZE);
11375 newval |= value | hbit << 24;
11376 md_number_to_chars (buf, newval, INSN_SIZE);
11377 }
c19d1205 11378 break;
a737bd4d 11379
c19d1205 11380 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */
2fc8bdac
ZW
11381 /* CZB can only branch forward. */
11382 if (value & ~0x7e)
11383 as_bad_where (fixP->fx_file, fixP->fx_line,
11384 _("branch out of range"));
a737bd4d 11385
2fc8bdac
ZW
11386 if (fixP->fx_done || !seg->use_rela_p)
11387 {
11388 newval = md_chars_to_number (buf, THUMB_SIZE);
c19d1205 11389 newval |= ((value & 0x2e) << 2) | ((value & 0x40) << 3);
2fc8bdac
ZW
11390 md_number_to_chars (buf, newval, THUMB_SIZE);
11391 }
c19d1205 11392 break;
a737bd4d 11393
c19d1205 11394 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
2fc8bdac
ZW
11395 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
11396 as_bad_where (fixP->fx_file, fixP->fx_line,
11397 _("branch out of range"));
a737bd4d 11398
2fc8bdac
ZW
11399 if (fixP->fx_done || !seg->use_rela_p)
11400 {
11401 newval = md_chars_to_number (buf, THUMB_SIZE);
11402 newval |= (value & 0x1ff) >> 1;
11403 md_number_to_chars (buf, newval, THUMB_SIZE);
11404 }
c19d1205 11405 break;
a737bd4d 11406
c19d1205 11407 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
2fc8bdac
ZW
11408 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
11409 as_bad_where (fixP->fx_file, fixP->fx_line,
11410 _("branch out of range"));
a737bd4d 11411
2fc8bdac
ZW
11412 if (fixP->fx_done || !seg->use_rela_p)
11413 {
11414 newval = md_chars_to_number (buf, THUMB_SIZE);
11415 newval |= (value & 0xfff) >> 1;
11416 md_number_to_chars (buf, newval, THUMB_SIZE);
11417 }
c19d1205 11418 break;
a737bd4d 11419
c19d1205 11420 case BFD_RELOC_THUMB_PCREL_BRANCH20:
2fc8bdac
ZW
11421 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
11422 as_bad_where (fixP->fx_file, fixP->fx_line,
11423 _("conditional branch out of range"));
404ff6b5 11424
2fc8bdac
ZW
11425 if (fixP->fx_done || !seg->use_rela_p)
11426 {
11427 offsetT newval2;
11428 addressT S, J1, J2, lo, hi;
404ff6b5 11429
2fc8bdac
ZW
11430 S = (value & 0x00100000) >> 20;
11431 J2 = (value & 0x00080000) >> 19;
11432 J1 = (value & 0x00040000) >> 18;
11433 hi = (value & 0x0003f000) >> 12;
11434 lo = (value & 0x00000ffe) >> 1;
6c43fab6 11435
2fc8bdac
ZW
11436 newval = md_chars_to_number (buf, THUMB_SIZE);
11437 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11438 newval |= (S << 10) | hi;
11439 newval2 |= (J1 << 13) | (J2 << 11) | lo;
11440 md_number_to_chars (buf, newval, THUMB_SIZE);
11441 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
11442 }
c19d1205 11443 break;
6c43fab6 11444
c19d1205
ZW
11445 case BFD_RELOC_THUMB_PCREL_BLX:
11446 case BFD_RELOC_THUMB_PCREL_BRANCH23:
2fc8bdac
ZW
11447 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
11448 as_bad_where (fixP->fx_file, fixP->fx_line,
11449 _("branch out of range"));
404ff6b5 11450
2fc8bdac
ZW
11451 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
11452 /* For a BLX instruction, make sure that the relocation is rounded up
11453 to a word boundary. This follows the semantics of the instruction
11454 which specifies that bit 1 of the target address will come from bit
11455 1 of the base address. */
11456 value = (value + 1) & ~ 1;
404ff6b5 11457
2fc8bdac 11458 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 11459 {
2fc8bdac
ZW
11460 offsetT newval2;
11461
11462 newval = md_chars_to_number (buf, THUMB_SIZE);
11463 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11464 newval |= (value & 0x7fffff) >> 12;
11465 newval2 |= (value & 0xfff) >> 1;
11466 md_number_to_chars (buf, newval, THUMB_SIZE);
11467 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
c19d1205 11468 }
c19d1205 11469 break;
404ff6b5 11470
c19d1205 11471 case BFD_RELOC_THUMB_PCREL_BRANCH25:
2fc8bdac
ZW
11472 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
11473 as_bad_where (fixP->fx_file, fixP->fx_line,
11474 _("branch out of range"));
6c43fab6 11475
2fc8bdac
ZW
11476 if (fixP->fx_done || !seg->use_rela_p)
11477 {
11478 offsetT newval2;
11479 addressT S, I1, I2, lo, hi;
6c43fab6 11480
2fc8bdac
ZW
11481 S = (value & 0x01000000) >> 24;
11482 I1 = (value & 0x00800000) >> 23;
11483 I2 = (value & 0x00400000) >> 22;
11484 hi = (value & 0x003ff000) >> 12;
11485 lo = (value & 0x00000ffe) >> 1;
6c43fab6 11486
2fc8bdac
ZW
11487 I1 = !(I1 ^ S);
11488 I2 = !(I2 ^ S);
a737bd4d 11489
2fc8bdac
ZW
11490 newval = md_chars_to_number (buf, THUMB_SIZE);
11491 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11492 newval |= (S << 10) | hi;
11493 newval2 |= (I1 << 13) | (I2 << 11) | lo;
11494 md_number_to_chars (buf, newval, THUMB_SIZE);
11495 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
11496 }
11497 break;
a737bd4d 11498
2fc8bdac
ZW
11499 case BFD_RELOC_8:
11500 if (fixP->fx_done || !seg->use_rela_p)
11501 md_number_to_chars (buf, value, 1);
c19d1205 11502 break;
a737bd4d 11503
c19d1205 11504 case BFD_RELOC_16:
2fc8bdac 11505 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 11506 md_number_to_chars (buf, value, 2);
c19d1205 11507 break;
a737bd4d 11508
c19d1205
ZW
11509#ifdef OBJ_ELF
11510 case BFD_RELOC_ARM_TLS_GD32:
11511 case BFD_RELOC_ARM_TLS_LE32:
11512 case BFD_RELOC_ARM_TLS_IE32:
11513 case BFD_RELOC_ARM_TLS_LDM32:
11514 case BFD_RELOC_ARM_TLS_LDO32:
11515 S_SET_THREAD_LOCAL (fixP->fx_addsy);
11516 /* fall through */
6c43fab6 11517
c19d1205
ZW
11518 case BFD_RELOC_ARM_GOT32:
11519 case BFD_RELOC_ARM_GOTOFF:
11520 case BFD_RELOC_ARM_TARGET2:
2fc8bdac
ZW
11521 if (fixP->fx_done || !seg->use_rela_p)
11522 md_number_to_chars (buf, 0, 4);
c19d1205
ZW
11523 break;
11524#endif
6c43fab6 11525
c19d1205
ZW
11526 case BFD_RELOC_RVA:
11527 case BFD_RELOC_32:
11528 case BFD_RELOC_ARM_TARGET1:
11529 case BFD_RELOC_ARM_ROSEGREL32:
11530 case BFD_RELOC_ARM_SBREL32:
11531 case BFD_RELOC_32_PCREL:
2fc8bdac 11532 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 11533 md_number_to_chars (buf, value, 4);
c19d1205 11534 break;
6c43fab6 11535
c19d1205
ZW
11536#ifdef OBJ_ELF
11537 case BFD_RELOC_ARM_PREL31:
2fc8bdac 11538 if (fixP->fx_done || !seg->use_rela_p)
c19d1205
ZW
11539 {
11540 newval = md_chars_to_number (buf, 4) & 0x80000000;
11541 if ((value ^ (value >> 1)) & 0x40000000)
11542 {
11543 as_bad_where (fixP->fx_file, fixP->fx_line,
11544 _("rel31 relocation overflow"));
11545 }
11546 newval |= value & 0x7fffffff;
11547 md_number_to_chars (buf, newval, 4);
11548 }
11549 break;
c19d1205 11550#endif
a737bd4d 11551
c19d1205 11552 case BFD_RELOC_ARM_CP_OFF_IMM:
8f06b2d8 11553 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
c19d1205
ZW
11554 if (value < -1023 || value > 1023 || (value & 3))
11555 as_bad_where (fixP->fx_file, fixP->fx_line,
11556 _("co-processor offset out of range"));
11557 cp_off_common:
11558 sign = value >= 0;
11559 if (value < 0)
11560 value = -value;
8f06b2d8
PB
11561 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
11562 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
11563 newval = md_chars_to_number (buf, INSN_SIZE);
11564 else
11565 newval = get_thumb32_insn (buf);
11566 newval &= 0xff7fff00;
c19d1205
ZW
11567 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
11568 if (value == 0)
11569 newval &= ~WRITE_BACK;
8f06b2d8
PB
11570 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
11571 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
11572 md_number_to_chars (buf, newval, INSN_SIZE);
11573 else
11574 put_thumb32_insn (buf, newval);
c19d1205 11575 break;
a737bd4d 11576
c19d1205 11577 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
8f06b2d8 11578 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
c19d1205
ZW
11579 if (value < -255 || value > 255)
11580 as_bad_where (fixP->fx_file, fixP->fx_line,
11581 _("co-processor offset out of range"));
11582 goto cp_off_common;
6c43fab6 11583
c19d1205
ZW
11584 case BFD_RELOC_ARM_THUMB_OFFSET:
11585 newval = md_chars_to_number (buf, THUMB_SIZE);
11586 /* Exactly what ranges, and where the offset is inserted depends
11587 on the type of instruction, we can establish this from the
11588 top 4 bits. */
11589 switch (newval >> 12)
11590 {
11591 case 4: /* PC load. */
11592 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
11593 forced to zero for these loads; md_pcrel_from has already
11594 compensated for this. */
11595 if (value & 3)
11596 as_bad_where (fixP->fx_file, fixP->fx_line,
11597 _("invalid offset, target not word aligned (0x%08lX)"),
11598 (((unsigned int) fixP->fx_frag->fr_address
11599 + (unsigned int) fixP->fx_where) & ~3) + value);
a737bd4d 11600
c19d1205
ZW
11601 if (value & ~0x3fc)
11602 as_bad_where (fixP->fx_file, fixP->fx_line,
11603 _("invalid offset, value too big (0x%08lX)"),
11604 (long) value);
a737bd4d 11605
c19d1205
ZW
11606 newval |= value >> 2;
11607 break;
a737bd4d 11608
c19d1205
ZW
11609 case 9: /* SP load/store. */
11610 if (value & ~0x3fc)
11611 as_bad_where (fixP->fx_file, fixP->fx_line,
11612 _("invalid offset, value too big (0x%08lX)"),
11613 (long) value);
11614 newval |= value >> 2;
11615 break;
6c43fab6 11616
c19d1205
ZW
11617 case 6: /* Word load/store. */
11618 if (value & ~0x7c)
11619 as_bad_where (fixP->fx_file, fixP->fx_line,
11620 _("invalid offset, value too big (0x%08lX)"),
11621 (long) value);
11622 newval |= value << 4; /* 6 - 2. */
11623 break;
a737bd4d 11624
c19d1205
ZW
11625 case 7: /* Byte load/store. */
11626 if (value & ~0x1f)
11627 as_bad_where (fixP->fx_file, fixP->fx_line,
11628 _("invalid offset, value too big (0x%08lX)"),
11629 (long) value);
11630 newval |= value << 6;
11631 break;
a737bd4d 11632
c19d1205
ZW
11633 case 8: /* Halfword load/store. */
11634 if (value & ~0x3e)
11635 as_bad_where (fixP->fx_file, fixP->fx_line,
11636 _("invalid offset, value too big (0x%08lX)"),
11637 (long) value);
11638 newval |= value << 5; /* 6 - 1. */
11639 break;
a737bd4d 11640
c19d1205
ZW
11641 default:
11642 as_bad_where (fixP->fx_file, fixP->fx_line,
11643 "Unable to process relocation for thumb opcode: %lx",
11644 (unsigned long) newval);
11645 break;
11646 }
11647 md_number_to_chars (buf, newval, THUMB_SIZE);
11648 break;
a737bd4d 11649
c19d1205
ZW
11650 case BFD_RELOC_ARM_THUMB_ADD:
11651 /* This is a complicated relocation, since we use it for all of
11652 the following immediate relocations:
a737bd4d 11653
c19d1205
ZW
11654 3bit ADD/SUB
11655 8bit ADD/SUB
11656 9bit ADD/SUB SP word-aligned
11657 10bit ADD PC/SP word-aligned
a737bd4d 11658
c19d1205
ZW
11659 The type of instruction being processed is encoded in the
11660 instruction field:
a737bd4d 11661
c19d1205
ZW
11662 0x8000 SUB
11663 0x00F0 Rd
11664 0x000F Rs
11665 */
11666 newval = md_chars_to_number (buf, THUMB_SIZE);
11667 {
11668 int rd = (newval >> 4) & 0xf;
11669 int rs = newval & 0xf;
11670 int subtract = !!(newval & 0x8000);
a737bd4d 11671
c19d1205
ZW
11672 /* Check for HI regs, only very restricted cases allowed:
11673 Adjusting SP, and using PC or SP to get an address. */
11674 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
11675 || (rs > 7 && rs != REG_SP && rs != REG_PC))
11676 as_bad_where (fixP->fx_file, fixP->fx_line,
11677 _("invalid Hi register with immediate"));
a737bd4d 11678
c19d1205
ZW
11679 /* If value is negative, choose the opposite instruction. */
11680 if (value < 0)
11681 {
11682 value = -value;
11683 subtract = !subtract;
11684 if (value < 0)
11685 as_bad_where (fixP->fx_file, fixP->fx_line,
11686 _("immediate value out of range"));
11687 }
a737bd4d 11688
c19d1205
ZW
11689 if (rd == REG_SP)
11690 {
11691 if (value & ~0x1fc)
11692 as_bad_where (fixP->fx_file, fixP->fx_line,
11693 _("invalid immediate for stack address calculation"));
11694 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
11695 newval |= value >> 2;
11696 }
11697 else if (rs == REG_PC || rs == REG_SP)
11698 {
11699 if (subtract || value & ~0x3fc)
11700 as_bad_where (fixP->fx_file, fixP->fx_line,
11701 _("invalid immediate for address calculation (value = 0x%08lX)"),
11702 (unsigned long) value);
11703 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
11704 newval |= rd << 8;
11705 newval |= value >> 2;
11706 }
11707 else if (rs == rd)
11708 {
11709 if (value & ~0xff)
11710 as_bad_where (fixP->fx_file, fixP->fx_line,
11711 _("immediate value out of range"));
11712 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
11713 newval |= (rd << 8) | value;
11714 }
11715 else
11716 {
11717 if (value & ~0x7)
11718 as_bad_where (fixP->fx_file, fixP->fx_line,
11719 _("immediate value out of range"));
11720 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
11721 newval |= rd | (rs << 3) | (value << 6);
11722 }
11723 }
11724 md_number_to_chars (buf, newval, THUMB_SIZE);
11725 break;
a737bd4d 11726
c19d1205
ZW
11727 case BFD_RELOC_ARM_THUMB_IMM:
11728 newval = md_chars_to_number (buf, THUMB_SIZE);
11729 if (value < 0 || value > 255)
11730 as_bad_where (fixP->fx_file, fixP->fx_line,
11731 _("invalid immediate: %ld is too large"),
11732 (long) value);
11733 newval |= value;
11734 md_number_to_chars (buf, newval, THUMB_SIZE);
11735 break;
a737bd4d 11736
c19d1205
ZW
11737 case BFD_RELOC_ARM_THUMB_SHIFT:
11738 /* 5bit shift value (0..32). LSL cannot take 32. */
11739 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
11740 temp = newval & 0xf800;
11741 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
11742 as_bad_where (fixP->fx_file, fixP->fx_line,
11743 _("invalid shift value: %ld"), (long) value);
11744 /* Shifts of zero must be encoded as LSL. */
11745 if (value == 0)
11746 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
11747 /* Shifts of 32 are encoded as zero. */
11748 else if (value == 32)
11749 value = 0;
11750 newval |= value << 6;
11751 md_number_to_chars (buf, newval, THUMB_SIZE);
11752 break;
a737bd4d 11753
c19d1205
ZW
11754 case BFD_RELOC_VTABLE_INHERIT:
11755 case BFD_RELOC_VTABLE_ENTRY:
11756 fixP->fx_done = 0;
11757 return;
6c43fab6 11758
c19d1205
ZW
11759 case BFD_RELOC_UNUSED:
11760 default:
11761 as_bad_where (fixP->fx_file, fixP->fx_line,
11762 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
11763 }
6c43fab6
RE
11764}
11765
c19d1205
ZW
11766/* Translate internal representation of relocation info to BFD target
11767 format. */
a737bd4d 11768
c19d1205
ZW
11769arelent *
11770tc_gen_reloc (asection * section ATTRIBUTE_UNUSED,
11771 fixS * fixp)
a737bd4d 11772{
c19d1205
ZW
11773 arelent * reloc;
11774 bfd_reloc_code_real_type code;
a737bd4d 11775
c19d1205 11776 reloc = xmalloc (sizeof (arelent));
a737bd4d 11777
c19d1205
ZW
11778 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
11779 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11780 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
a737bd4d 11781
2fc8bdac
ZW
11782 if (fixp->fx_pcrel)
11783 fixp->fx_offset = reloc->address;
c19d1205 11784 reloc->addend = fixp->fx_offset;
a737bd4d 11785
c19d1205 11786 switch (fixp->fx_r_type)
a737bd4d 11787 {
c19d1205
ZW
11788 case BFD_RELOC_8:
11789 if (fixp->fx_pcrel)
11790 {
11791 code = BFD_RELOC_8_PCREL;
11792 break;
11793 }
a737bd4d 11794
c19d1205
ZW
11795 case BFD_RELOC_16:
11796 if (fixp->fx_pcrel)
11797 {
11798 code = BFD_RELOC_16_PCREL;
11799 break;
11800 }
6c43fab6 11801
c19d1205
ZW
11802 case BFD_RELOC_32:
11803 if (fixp->fx_pcrel)
11804 {
11805 code = BFD_RELOC_32_PCREL;
11806 break;
11807 }
a737bd4d 11808
c19d1205
ZW
11809 case BFD_RELOC_NONE:
11810 case BFD_RELOC_ARM_PCREL_BRANCH:
11811 case BFD_RELOC_ARM_PCREL_BLX:
11812 case BFD_RELOC_RVA:
11813 case BFD_RELOC_THUMB_PCREL_BRANCH7:
11814 case BFD_RELOC_THUMB_PCREL_BRANCH9:
11815 case BFD_RELOC_THUMB_PCREL_BRANCH12:
11816 case BFD_RELOC_THUMB_PCREL_BRANCH20:
11817 case BFD_RELOC_THUMB_PCREL_BRANCH23:
11818 case BFD_RELOC_THUMB_PCREL_BRANCH25:
11819 case BFD_RELOC_THUMB_PCREL_BLX:
11820 case BFD_RELOC_VTABLE_ENTRY:
11821 case BFD_RELOC_VTABLE_INHERIT:
11822 code = fixp->fx_r_type;
11823 break;
a737bd4d 11824
c19d1205
ZW
11825 case BFD_RELOC_ARM_LITERAL:
11826 case BFD_RELOC_ARM_HWLITERAL:
11827 /* If this is called then the a literal has
11828 been referenced across a section boundary. */
11829 as_bad_where (fixp->fx_file, fixp->fx_line,
11830 _("literal referenced across section boundary"));
11831 return NULL;
a737bd4d 11832
c19d1205
ZW
11833#ifdef OBJ_ELF
11834 case BFD_RELOC_ARM_GOT32:
11835 case BFD_RELOC_ARM_GOTOFF:
11836 case BFD_RELOC_ARM_PLT32:
11837 case BFD_RELOC_ARM_TARGET1:
11838 case BFD_RELOC_ARM_ROSEGREL32:
11839 case BFD_RELOC_ARM_SBREL32:
11840 case BFD_RELOC_ARM_PREL31:
11841 case BFD_RELOC_ARM_TARGET2:
11842 case BFD_RELOC_ARM_TLS_LE32:
11843 case BFD_RELOC_ARM_TLS_LDO32:
11844 code = fixp->fx_r_type;
11845 break;
a737bd4d 11846
c19d1205
ZW
11847 case BFD_RELOC_ARM_TLS_GD32:
11848 case BFD_RELOC_ARM_TLS_IE32:
11849 case BFD_RELOC_ARM_TLS_LDM32:
11850 /* BFD will include the symbol's address in the addend.
11851 But we don't want that, so subtract it out again here. */
11852 if (!S_IS_COMMON (fixp->fx_addsy))
11853 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
11854 code = fixp->fx_r_type;
11855 break;
11856#endif
a737bd4d 11857
c19d1205
ZW
11858 case BFD_RELOC_ARM_IMMEDIATE:
11859 as_bad_where (fixp->fx_file, fixp->fx_line,
11860 _("internal relocation (type: IMMEDIATE) not fixed up"));
11861 return NULL;
a737bd4d 11862
c19d1205
ZW
11863 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
11864 as_bad_where (fixp->fx_file, fixp->fx_line,
11865 _("ADRL used for a symbol not defined in the same file"));
11866 return NULL;
a737bd4d 11867
c19d1205
ZW
11868 case BFD_RELOC_ARM_OFFSET_IMM:
11869 if (fixp->fx_addsy != NULL
11870 && !S_IS_DEFINED (fixp->fx_addsy)
11871 && S_IS_LOCAL (fixp->fx_addsy))
a737bd4d 11872 {
c19d1205
ZW
11873 as_bad_where (fixp->fx_file, fixp->fx_line,
11874 _("undefined local label `%s'"),
11875 S_GET_NAME (fixp->fx_addsy));
11876 return NULL;
a737bd4d
NC
11877 }
11878
c19d1205
ZW
11879 as_bad_where (fixp->fx_file, fixp->fx_line,
11880 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
11881 return NULL;
a737bd4d 11882
c19d1205
ZW
11883 default:
11884 {
11885 char * type;
6c43fab6 11886
c19d1205
ZW
11887 switch (fixp->fx_r_type)
11888 {
11889 case BFD_RELOC_NONE: type = "NONE"; break;
11890 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
11891 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
3eb17e6b 11892 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
c19d1205
ZW
11893 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
11894 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
11895 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
8f06b2d8 11896 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
c19d1205
ZW
11897 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
11898 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
11899 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
11900 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
11901 default: type = _("<unknown>"); break;
11902 }
11903 as_bad_where (fixp->fx_file, fixp->fx_line,
11904 _("cannot represent %s relocation in this object file format"),
11905 type);
11906 return NULL;
11907 }
a737bd4d 11908 }
6c43fab6 11909
c19d1205
ZW
11910#ifdef OBJ_ELF
11911 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
11912 && GOT_symbol
11913 && fixp->fx_addsy == GOT_symbol)
11914 {
11915 code = BFD_RELOC_ARM_GOTPC;
11916 reloc->addend = fixp->fx_offset = reloc->address;
11917 }
11918#endif
6c43fab6 11919
c19d1205 11920 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6c43fab6 11921
c19d1205
ZW
11922 if (reloc->howto == NULL)
11923 {
11924 as_bad_where (fixp->fx_file, fixp->fx_line,
11925 _("cannot represent %s relocation in this object file format"),
11926 bfd_get_reloc_code_name (code));
11927 return NULL;
11928 }
6c43fab6 11929
c19d1205
ZW
11930 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
11931 vtable entry to be used in the relocation's section offset. */
11932 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11933 reloc->address = fixp->fx_offset;
6c43fab6 11934
c19d1205 11935 return reloc;
6c43fab6
RE
11936}
11937
c19d1205 11938/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6c43fab6 11939
c19d1205
ZW
11940void
11941cons_fix_new_arm (fragS * frag,
11942 int where,
11943 int size,
11944 expressionS * exp)
6c43fab6 11945{
c19d1205
ZW
11946 bfd_reloc_code_real_type type;
11947 int pcrel = 0;
6c43fab6 11948
c19d1205
ZW
11949 /* Pick a reloc.
11950 FIXME: @@ Should look at CPU word size. */
11951 switch (size)
11952 {
11953 case 1:
11954 type = BFD_RELOC_8;
11955 break;
11956 case 2:
11957 type = BFD_RELOC_16;
11958 break;
11959 case 4:
11960 default:
11961 type = BFD_RELOC_32;
11962 break;
11963 case 8:
11964 type = BFD_RELOC_64;
11965 break;
11966 }
6c43fab6 11967
c19d1205
ZW
11968 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
11969}
6c43fab6 11970
c19d1205
ZW
11971#if defined OBJ_COFF || defined OBJ_ELF
11972void
11973arm_validate_fix (fixS * fixP)
6c43fab6 11974{
c19d1205
ZW
11975 /* If the destination of the branch is a defined symbol which does not have
11976 the THUMB_FUNC attribute, then we must be calling a function which has
11977 the (interfacearm) attribute. We look for the Thumb entry point to that
11978 function and change the branch to refer to that function instead. */
11979 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
11980 && fixP->fx_addsy != NULL
11981 && S_IS_DEFINED (fixP->fx_addsy)
11982 && ! THUMB_IS_FUNC (fixP->fx_addsy))
6c43fab6 11983 {
c19d1205 11984 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
6c43fab6 11985 }
c19d1205
ZW
11986}
11987#endif
6c43fab6 11988
c19d1205
ZW
11989int
11990arm_force_relocation (struct fix * fixp)
11991{
11992#if defined (OBJ_COFF) && defined (TE_PE)
11993 if (fixp->fx_r_type == BFD_RELOC_RVA)
11994 return 1;
11995#endif
6c43fab6 11996
c19d1205
ZW
11997 /* Resolve these relocations even if the symbol is extern or weak. */
11998 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
11999 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
0110f2b8
PB
12000 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
12001 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
12002 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
12003 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12)
c19d1205 12004 return 0;
a737bd4d 12005
c19d1205 12006 return generic_force_reloc (fixp);
404ff6b5
AH
12007}
12008
c19d1205
ZW
12009#ifdef OBJ_COFF
12010/* This is a little hack to help the gas/arm/adrl.s test. It prevents
12011 local labels from being added to the output symbol table when they
12012 are used with the ADRL pseudo op. The ADRL relocation should always
12013 be resolved before the binbary is emitted, so it is safe to say that
12014 it is adjustable. */
404ff6b5 12015
c19d1205
ZW
12016bfd_boolean
12017arm_fix_adjustable (fixS * fixP)
404ff6b5 12018{
c19d1205
ZW
12019 if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
12020 return 1;
12021 return 0;
404ff6b5 12022}
c19d1205 12023#endif
404ff6b5 12024
c19d1205
ZW
12025#ifdef OBJ_ELF
12026/* Relocations against Thumb function names must be left unadjusted,
12027 so that the linker can use this information to correctly set the
12028 bottom bit of their addresses. The MIPS version of this function
12029 also prevents relocations that are mips-16 specific, but I do not
12030 know why it does this.
404ff6b5 12031
c19d1205
ZW
12032 FIXME:
12033 There is one other problem that ought to be addressed here, but
12034 which currently is not: Taking the address of a label (rather
12035 than a function) and then later jumping to that address. Such
12036 addresses also ought to have their bottom bit set (assuming that
12037 they reside in Thumb code), but at the moment they will not. */
404ff6b5 12038
c19d1205
ZW
12039bfd_boolean
12040arm_fix_adjustable (fixS * fixP)
404ff6b5 12041{
c19d1205
ZW
12042 if (fixP->fx_addsy == NULL)
12043 return 1;
404ff6b5 12044
c19d1205
ZW
12045 if (THUMB_IS_FUNC (fixP->fx_addsy)
12046 && fixP->fx_subsy == NULL)
12047 return 0;
a737bd4d 12048
c19d1205
ZW
12049 /* We need the symbol name for the VTABLE entries. */
12050 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12051 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12052 return 0;
404ff6b5 12053
c19d1205
ZW
12054 /* Don't allow symbols to be discarded on GOT related relocs. */
12055 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
12056 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
12057 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
12058 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
12059 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
12060 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
12061 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
12062 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
12063 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
12064 return 0;
a737bd4d 12065
c19d1205 12066 return 1;
a737bd4d 12067}
404ff6b5 12068
c19d1205
ZW
12069const char *
12070elf32_arm_target_format (void)
404ff6b5 12071{
c19d1205
ZW
12072#ifdef TE_SYMBIAN
12073 return (target_big_endian
12074 ? "elf32-bigarm-symbian"
12075 : "elf32-littlearm-symbian");
12076#elif defined (TE_VXWORKS)
12077 return (target_big_endian
12078 ? "elf32-bigarm-vxworks"
12079 : "elf32-littlearm-vxworks");
12080#else
12081 if (target_big_endian)
12082 return "elf32-bigarm";
12083 else
12084 return "elf32-littlearm";
12085#endif
404ff6b5
AH
12086}
12087
c19d1205
ZW
12088void
12089armelf_frob_symbol (symbolS * symp,
12090 int * puntp)
404ff6b5 12091{
c19d1205
ZW
12092 elf_frob_symbol (symp, puntp);
12093}
12094#endif
404ff6b5 12095
c19d1205 12096/* MD interface: Finalization. */
a737bd4d 12097
c19d1205
ZW
12098/* A good place to do this, although this was probably not intended
12099 for this kind of use. We need to dump the literal pool before
12100 references are made to a null symbol pointer. */
a737bd4d 12101
c19d1205
ZW
12102void
12103arm_cleanup (void)
12104{
12105 literal_pool * pool;
a737bd4d 12106
c19d1205
ZW
12107 for (pool = list_of_pools; pool; pool = pool->next)
12108 {
12109 /* Put it at the end of the relevent section. */
12110 subseg_set (pool->section, pool->sub_section);
12111#ifdef OBJ_ELF
12112 arm_elf_change_section ();
12113#endif
12114 s_ltorg (0);
12115 }
404ff6b5
AH
12116}
12117
c19d1205
ZW
12118/* Adjust the symbol table. This marks Thumb symbols as distinct from
12119 ARM ones. */
404ff6b5 12120
c19d1205
ZW
12121void
12122arm_adjust_symtab (void)
404ff6b5 12123{
c19d1205
ZW
12124#ifdef OBJ_COFF
12125 symbolS * sym;
404ff6b5 12126
c19d1205
ZW
12127 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
12128 {
12129 if (ARM_IS_THUMB (sym))
12130 {
12131 if (THUMB_IS_FUNC (sym))
12132 {
12133 /* Mark the symbol as a Thumb function. */
12134 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
12135 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
12136 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
404ff6b5 12137
c19d1205
ZW
12138 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
12139 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
12140 else
12141 as_bad (_("%s: unexpected function type: %d"),
12142 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
12143 }
12144 else switch (S_GET_STORAGE_CLASS (sym))
12145 {
12146 case C_EXT:
12147 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
12148 break;
12149 case C_STAT:
12150 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
12151 break;
12152 case C_LABEL:
12153 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
12154 break;
12155 default:
12156 /* Do nothing. */
12157 break;
12158 }
12159 }
a737bd4d 12160
c19d1205
ZW
12161 if (ARM_IS_INTERWORK (sym))
12162 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
404ff6b5 12163 }
c19d1205
ZW
12164#endif
12165#ifdef OBJ_ELF
12166 symbolS * sym;
12167 char bind;
404ff6b5 12168
c19d1205 12169 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
404ff6b5 12170 {
c19d1205
ZW
12171 if (ARM_IS_THUMB (sym))
12172 {
12173 elf_symbol_type * elf_sym;
404ff6b5 12174
c19d1205
ZW
12175 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
12176 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
404ff6b5 12177
c19d1205
ZW
12178 if (! bfd_is_arm_mapping_symbol_name (elf_sym->symbol.name))
12179 {
12180 /* If it's a .thumb_func, declare it as so,
12181 otherwise tag label as .code 16. */
12182 if (THUMB_IS_FUNC (sym))
12183 elf_sym->internal_elf_sym.st_info =
12184 ELF_ST_INFO (bind, STT_ARM_TFUNC);
12185 else
12186 elf_sym->internal_elf_sym.st_info =
12187 ELF_ST_INFO (bind, STT_ARM_16BIT);
12188 }
12189 }
12190 }
12191#endif
404ff6b5
AH
12192}
12193
c19d1205 12194/* MD interface: Initialization. */
404ff6b5 12195
a737bd4d 12196static void
c19d1205 12197set_constant_flonums (void)
a737bd4d 12198{
c19d1205 12199 int i;
404ff6b5 12200
c19d1205
ZW
12201 for (i = 0; i < NUM_FLOAT_VALS; i++)
12202 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
12203 abort ();
a737bd4d 12204}
404ff6b5 12205
c19d1205
ZW
12206void
12207md_begin (void)
a737bd4d 12208{
c19d1205
ZW
12209 unsigned mach;
12210 unsigned int i;
404ff6b5 12211
c19d1205
ZW
12212 if ( (arm_ops_hsh = hash_new ()) == NULL
12213 || (arm_cond_hsh = hash_new ()) == NULL
12214 || (arm_shift_hsh = hash_new ()) == NULL
12215 || (arm_psr_hsh = hash_new ()) == NULL
12216 || (arm_reg_hsh = hash_new ()) == NULL
12217 || (arm_reloc_hsh = hash_new ()) == NULL)
12218 as_fatal (_("virtual memory exhausted"));
12219
12220 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
12221 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
12222 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
12223 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
12224 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
12225 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
12226 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
12227 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
12228 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
12229 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i));
12230#ifdef OBJ_ELF
12231 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
12232 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i));
12233#endif
12234
12235 set_constant_flonums ();
404ff6b5 12236
c19d1205
ZW
12237 /* Set the cpu variant based on the command-line options. We prefer
12238 -mcpu= over -march= if both are set (as for GCC); and we prefer
12239 -mfpu= over any other way of setting the floating point unit.
12240 Use of legacy options with new options are faulted. */
12241 if (legacy_cpu != -1)
404ff6b5 12242 {
c19d1205
ZW
12243 if (mcpu_cpu_opt != -1 || march_cpu_opt != -1)
12244 as_bad (_("use of old and new-style options to set CPU type"));
12245
12246 mcpu_cpu_opt = legacy_cpu;
404ff6b5 12247 }
c19d1205
ZW
12248 else if (mcpu_cpu_opt == -1)
12249 mcpu_cpu_opt = march_cpu_opt;
404ff6b5 12250
c19d1205
ZW
12251 if (legacy_fpu != -1)
12252 {
12253 if (mfpu_opt != -1)
12254 as_bad (_("use of old and new-style options to set FPU type"));
03b1477f
RE
12255
12256 mfpu_opt = legacy_fpu;
12257 }
12258 else if (mfpu_opt == -1)
12259 {
c19d1205 12260#if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
39c2da32
RE
12261 /* Some environments specify a default FPU. If they don't, infer it
12262 from the processor. */
03b1477f
RE
12263 if (mcpu_fpu_opt != -1)
12264 mfpu_opt = mcpu_fpu_opt;
12265 else
12266 mfpu_opt = march_fpu_opt;
39c2da32
RE
12267#else
12268 mfpu_opt = FPU_DEFAULT;
12269#endif
03b1477f
RE
12270 }
12271
12272 if (mfpu_opt == -1)
12273 {
12274 if (mcpu_cpu_opt == -1)
12275 mfpu_opt = FPU_DEFAULT;
12276 else if (mcpu_cpu_opt & ARM_EXT_V5)
12277 mfpu_opt = FPU_ARCH_VFP_V2;
12278 else
12279 mfpu_opt = FPU_ARCH_FPA;
12280 }
12281
12282 if (mcpu_cpu_opt == -1)
12283 mcpu_cpu_opt = CPU_DEFAULT;
12284
12285 cpu_variant = mcpu_cpu_opt | mfpu_opt;
12286
f17c130b 12287#if defined OBJ_COFF || defined OBJ_ELF
b99bd4ef 12288 {
7cc69913
NC
12289 unsigned int flags = 0;
12290
12291#if defined OBJ_ELF
12292 flags = meabi_flags;
d507cf36
PB
12293
12294 switch (meabi_flags)
33a392fb 12295 {
d507cf36 12296 case EF_ARM_EABI_UNKNOWN:
7cc69913 12297#endif
d507cf36
PB
12298 /* Set the flags in the private structure. */
12299 if (uses_apcs_26) flags |= F_APCS26;
12300 if (support_interwork) flags |= F_INTERWORK;
12301 if (uses_apcs_float) flags |= F_APCS_FLOAT;
c19d1205 12302 if (pic_code) flags |= F_PIC;
d507cf36
PB
12303 if ((cpu_variant & FPU_ANY) == FPU_NONE
12304 || (cpu_variant & FPU_ANY) == FPU_ARCH_VFP) /* VFP layout only. */
7cc69913
NC
12305 flags |= F_SOFT_FLOAT;
12306
d507cf36
PB
12307 switch (mfloat_abi_opt)
12308 {
12309 case ARM_FLOAT_ABI_SOFT:
12310 case ARM_FLOAT_ABI_SOFTFP:
12311 flags |= F_SOFT_FLOAT;
12312 break;
33a392fb 12313
d507cf36
PB
12314 case ARM_FLOAT_ABI_HARD:
12315 if (flags & F_SOFT_FLOAT)
12316 as_bad (_("hard-float conflicts with specified fpu"));
12317 break;
12318 }
03b1477f 12319
c19d1205 12320 /* Using VFP conventions (even if soft-float). */
7cc69913
NC
12321 if (cpu_variant & FPU_VFP_EXT_NONE)
12322 flags |= F_VFP_FLOAT;
f17c130b 12323
fde78edd 12324#if defined OBJ_ELF
d507cf36
PB
12325 if (cpu_variant & FPU_ARCH_MAVERICK)
12326 flags |= EF_ARM_MAVERICK_FLOAT;
d507cf36
PB
12327 break;
12328
8cb51566 12329 case EF_ARM_EABI_VER4:
c19d1205 12330 /* No additional flags to set. */
d507cf36
PB
12331 break;
12332
12333 default:
12334 abort ();
12335 }
7cc69913 12336#endif
b99bd4ef
NC
12337 bfd_set_private_flags (stdoutput, flags);
12338
12339 /* We have run out flags in the COFF header to encode the
12340 status of ATPCS support, so instead we create a dummy,
c19d1205 12341 empty, debug section called .arm.atpcs. */
b99bd4ef
NC
12342 if (atpcs)
12343 {
12344 asection * sec;
12345
12346 sec = bfd_make_section (stdoutput, ".arm.atpcs");
12347
12348 if (sec != NULL)
12349 {
12350 bfd_set_section_flags
12351 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
12352 bfd_set_section_size (stdoutput, sec, 0);
12353 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
12354 }
12355 }
7cc69913 12356 }
f17c130b 12357#endif
b99bd4ef
NC
12358
12359 /* Record the CPU type as well. */
12360 switch (cpu_variant & ARM_CPU_MASK)
12361 {
12362 case ARM_2:
12363 mach = bfd_mach_arm_2;
12364 break;
12365
c19d1205 12366 case ARM_3: /* Also ARM_250. */
b99bd4ef
NC
12367 mach = bfd_mach_arm_2a;
12368 break;
12369
c19d1205 12370 case ARM_6: /* Also ARM_7. */
b89dddec
RE
12371 mach = bfd_mach_arm_3;
12372 break;
12373
b99bd4ef 12374 default:
5a6c6817 12375 mach = bfd_mach_arm_unknown;
b99bd4ef 12376 break;
b99bd4ef
NC
12377 }
12378
12379 /* Catch special cases. */
e16bb312
NC
12380 if (cpu_variant & ARM_CEXT_IWMMXT)
12381 mach = bfd_mach_arm_iWMMXt;
12382 else if (cpu_variant & ARM_CEXT_XSCALE)
b99bd4ef 12383 mach = bfd_mach_arm_XScale;
fde78edd
NC
12384 else if (cpu_variant & ARM_CEXT_MAVERICK)
12385 mach = bfd_mach_arm_ep9312;
b99bd4ef
NC
12386 else if (cpu_variant & ARM_EXT_V5E)
12387 mach = bfd_mach_arm_5TE;
12388 else if (cpu_variant & ARM_EXT_V5)
12389 {
b89dddec 12390 if (cpu_variant & ARM_EXT_V4T)
b99bd4ef
NC
12391 mach = bfd_mach_arm_5T;
12392 else
12393 mach = bfd_mach_arm_5;
12394 }
b89dddec 12395 else if (cpu_variant & ARM_EXT_V4)
b99bd4ef 12396 {
b89dddec 12397 if (cpu_variant & ARM_EXT_V4T)
b99bd4ef
NC
12398 mach = bfd_mach_arm_4T;
12399 else
12400 mach = bfd_mach_arm_4;
12401 }
b89dddec 12402 else if (cpu_variant & ARM_EXT_V3M)
b99bd4ef
NC
12403 mach = bfd_mach_arm_3M;
12404
12405 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
12406}
12407
c19d1205 12408/* Command line processing. */
b99bd4ef 12409
c19d1205
ZW
12410/* md_parse_option
12411 Invocation line includes a switch not recognized by the base assembler.
12412 See if it's a processor-specific option.
b99bd4ef 12413
c19d1205
ZW
12414 This routine is somewhat complicated by the need for backwards
12415 compatibility (since older releases of gcc can't be changed).
12416 The new options try to make the interface as compatible as
12417 possible with GCC.
b99bd4ef 12418
c19d1205 12419 New options (supported) are:
b99bd4ef 12420
c19d1205
ZW
12421 -mcpu=<cpu name> Assemble for selected processor
12422 -march=<architecture name> Assemble for selected architecture
12423 -mfpu=<fpu architecture> Assemble for selected FPU.
12424 -EB/-mbig-endian Big-endian
12425 -EL/-mlittle-endian Little-endian
12426 -k Generate PIC code
12427 -mthumb Start in Thumb mode
12428 -mthumb-interwork Code supports ARM/Thumb interworking
b99bd4ef 12429
c19d1205 12430 For now we will also provide support for:
b99bd4ef 12431
c19d1205
ZW
12432 -mapcs-32 32-bit Program counter
12433 -mapcs-26 26-bit Program counter
12434 -macps-float Floats passed in FP registers
12435 -mapcs-reentrant Reentrant code
12436 -matpcs
12437 (sometime these will probably be replaced with -mapcs=<list of options>
12438 and -matpcs=<list of options>)
b99bd4ef 12439
c19d1205
ZW
12440 The remaining options are only supported for back-wards compatibility.
12441 Cpu variants, the arm part is optional:
12442 -m[arm]1 Currently not supported.
12443 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
12444 -m[arm]3 Arm 3 processor
12445 -m[arm]6[xx], Arm 6 processors
12446 -m[arm]7[xx][t][[d]m] Arm 7 processors
12447 -m[arm]8[10] Arm 8 processors
12448 -m[arm]9[20][tdmi] Arm 9 processors
12449 -mstrongarm[110[0]] StrongARM processors
12450 -mxscale XScale processors
12451 -m[arm]v[2345[t[e]]] Arm architectures
12452 -mall All (except the ARM1)
12453 FP variants:
12454 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
12455 -mfpe-old (No float load/store multiples)
12456 -mvfpxd VFP Single precision
12457 -mvfp All VFP
12458 -mno-fpu Disable all floating point instructions
b99bd4ef 12459
c19d1205
ZW
12460 The following CPU names are recognized:
12461 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
12462 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
12463 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
12464 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
12465 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
12466 arm10t arm10e, arm1020t, arm1020e, arm10200e,
12467 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
b99bd4ef 12468
c19d1205 12469 */
b99bd4ef 12470
c19d1205 12471const char * md_shortopts = "m:k";
b99bd4ef 12472
c19d1205
ZW
12473#ifdef ARM_BI_ENDIAN
12474#define OPTION_EB (OPTION_MD_BASE + 0)
12475#define OPTION_EL (OPTION_MD_BASE + 1)
b99bd4ef 12476#else
c19d1205
ZW
12477#if TARGET_BYTES_BIG_ENDIAN
12478#define OPTION_EB (OPTION_MD_BASE + 0)
b99bd4ef 12479#else
c19d1205
ZW
12480#define OPTION_EL (OPTION_MD_BASE + 1)
12481#endif
b99bd4ef 12482#endif
b99bd4ef 12483
c19d1205 12484struct option md_longopts[] =
b99bd4ef 12485{
c19d1205
ZW
12486#ifdef OPTION_EB
12487 {"EB", no_argument, NULL, OPTION_EB},
12488#endif
12489#ifdef OPTION_EL
12490 {"EL", no_argument, NULL, OPTION_EL},
b99bd4ef 12491#endif
c19d1205
ZW
12492 {NULL, no_argument, NULL, 0}
12493};
b99bd4ef 12494
c19d1205 12495size_t md_longopts_size = sizeof (md_longopts);
b99bd4ef 12496
c19d1205 12497struct arm_option_table
b99bd4ef 12498{
c19d1205
ZW
12499 char *option; /* Option name to match. */
12500 char *help; /* Help information. */
12501 int *var; /* Variable to change. */
12502 int value; /* What to change it to. */
12503 char *deprecated; /* If non-null, print this message. */
12504};
b99bd4ef 12505
c19d1205
ZW
12506struct arm_option_table arm_opts[] =
12507{
12508 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
12509 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
12510 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
12511 &support_interwork, 1, NULL},
12512 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
12513 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
12514 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
12515 1, NULL},
12516 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
12517 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
12518 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
12519 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
12520 NULL},
b99bd4ef 12521
c19d1205
ZW
12522 /* These are recognized by the assembler, but have no affect on code. */
12523 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
12524 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
b99bd4ef 12525
c19d1205
ZW
12526 /* DON'T add any new processors to this list -- we want the whole list
12527 to go away... Add them to the processors table instead. */
12528 {"marm1", NULL, &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
12529 {"m1", NULL, &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
12530 {"marm2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
12531 {"m2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
12532 {"marm250", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
12533 {"m250", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
12534 {"marm3", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
12535 {"m3", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
12536 {"marm6", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
12537 {"m6", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
12538 {"marm600", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
12539 {"m600", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
12540 {"marm610", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
12541 {"m610", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
12542 {"marm620", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
12543 {"m620", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
12544 {"marm7", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
12545 {"m7", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
12546 {"marm70", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
12547 {"m70", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
12548 {"marm700", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
12549 {"m700", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
12550 {"marm700i", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
12551 {"m700i", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
12552 {"marm710", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
12553 {"m710", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
12554 {"marm710c", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
12555 {"m710c", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
12556 {"marm720", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
12557 {"m720", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
12558 {"marm7d", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
12559 {"m7d", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
12560 {"marm7di", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
12561 {"m7di", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
12562 {"marm7m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
12563 {"m7m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
12564 {"marm7dm", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
12565 {"m7dm", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
12566 {"marm7dmi", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
12567 {"m7dmi", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
12568 {"marm7100", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
12569 {"m7100", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
12570 {"marm7500", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
12571 {"m7500", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
12572 {"marm7500fe", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
12573 {"m7500fe", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
12574 {"marm7t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
12575 {"m7t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
12576 {"marm7tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
12577 {"m7tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
12578 {"marm710t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
12579 {"m710t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
12580 {"marm720t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
12581 {"m720t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
12582 {"marm740t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
12583 {"m740t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
12584 {"marm8", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
12585 {"m8", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
12586 {"marm810", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
12587 {"m810", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
12588 {"marm9", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
12589 {"m9", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
12590 {"marm9tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
12591 {"m9tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
12592 {"marm920", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
12593 {"m920", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
12594 {"marm940", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
12595 {"m940", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
12596 {"mstrongarm", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
12597 {"mstrongarm110", NULL, &legacy_cpu, ARM_ARCH_V4,
12598 N_("use -mcpu=strongarm110")},
12599 {"mstrongarm1100", NULL, &legacy_cpu, ARM_ARCH_V4,
12600 N_("use -mcpu=strongarm1100")},
12601 {"mstrongarm1110", NULL, &legacy_cpu, ARM_ARCH_V4,
12602 N_("use -mcpu=strongarm1110")},
12603 {"mxscale", NULL, &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
12604 {"miwmmxt", NULL, &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
12605 {"mall", NULL, &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
7ed4c4c5 12606
c19d1205
ZW
12607 /* Architecture variants -- don't add any more to this list either. */
12608 {"mv2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
12609 {"marmv2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
12610 {"mv2a", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
12611 {"marmv2a", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
12612 {"mv3", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
12613 {"marmv3", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
12614 {"mv3m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
12615 {"marmv3m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
12616 {"mv4", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
12617 {"marmv4", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
12618 {"mv4t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
12619 {"marmv4t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
12620 {"mv5", NULL, &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
12621 {"marmv5", NULL, &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
12622 {"mv5t", NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
12623 {"marmv5t", NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
12624 {"mv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
12625 {"marmv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
7ed4c4c5 12626
c19d1205
ZW
12627 /* Floating point variants -- don't add any more to this list either. */
12628 {"mfpe-old", NULL, &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
12629 {"mfpa10", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
12630 {"mfpa11", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
12631 {"mno-fpu", NULL, &legacy_fpu, 0,
12632 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
7ed4c4c5 12633
c19d1205
ZW
12634 {NULL, NULL, NULL, 0, NULL}
12635};
7ed4c4c5 12636
c19d1205 12637struct arm_cpu_option_table
7ed4c4c5 12638{
c19d1205
ZW
12639 char *name;
12640 int value;
12641 /* For some CPUs we assume an FPU unless the user explicitly sets
12642 -mfpu=... */
12643 int default_fpu;
12644};
7ed4c4c5 12645
c19d1205
ZW
12646/* This list should, at a minimum, contain all the cpu names
12647 recognized by GCC. */
12648static struct arm_cpu_option_table arm_cpus[] =
12649{
12650 {"all", ARM_ANY, FPU_ARCH_FPA},
12651 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA},
12652 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA},
12653 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA},
12654 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA},
12655 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA},
12656 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA},
12657 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA},
12658 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA},
12659 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA},
12660 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA},
12661 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA},
12662 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA},
12663 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA},
12664 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA},
12665 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA},
12666 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA},
12667 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA},
12668 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA},
12669 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA},
12670 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12671 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA},
12672 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12673 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12674 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA},
12675 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA},
12676 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA},
12677 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA},
12678 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12679 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA},
12680 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA},
12681 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA},
12682 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA},
12683 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA},
12684 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA},
12685 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA},
12686 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA},
12687 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA},
12688 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA},
12689 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA},
12690 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12691 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12692 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12693 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA},
12694 /* For V5 or later processors we default to using VFP; but the user
12695 should really set the FPU type explicitly. */
12696 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
12697 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12698 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12699 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12700 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12701 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
12702 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
db8ac8f9 12703 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
c19d1205
ZW
12704 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
12705 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
db8ac8f9
PB
12706 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12707 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
c19d1205 12708 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1},
db8ac8f9 12709 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1},
c19d1205
ZW
12710 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12711 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12712 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1},
12713 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
db8ac8f9 12714 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
c19d1205
ZW
12715 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12716 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12717 {"arm1136js", ARM_ARCH_V6, FPU_NONE},
12718 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE},
12719 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2},
12720 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2},
12721 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2},
12722 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE},
db8ac8f9
PB
12723 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE},
12724 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2},
c19d1205
ZW
12725 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE},
12726 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2},
12727 /* ??? XSCALE is really an architecture. */
12728 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2},
12729 /* ??? iwmmxt is not a processor. */
12730 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2},
12731 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2},
12732 /* Maverick */
12733 {"ep9312", ARM_ARCH_V4T | ARM_CEXT_MAVERICK, FPU_ARCH_MAVERICK},
12734 {NULL, 0, 0}
12735};
7ed4c4c5 12736
c19d1205 12737struct arm_arch_option_table
7ed4c4c5 12738{
c19d1205
ZW
12739 char *name;
12740 int value;
12741 int default_fpu;
12742};
7ed4c4c5 12743
c19d1205
ZW
12744/* This list should, at a minimum, contain all the architecture names
12745 recognized by GCC. */
12746static struct arm_arch_option_table arm_archs[] =
12747{
12748 {"all", ARM_ANY, FPU_ARCH_FPA},
12749 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
12750 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
12751 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
12752 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
12753 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
12754 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
12755 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
12756 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
12757 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12758 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
12759 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
12760 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
12761 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
12762 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
12763 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
12764 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
12765 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
12766 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
12767 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
12768 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
12769 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
12770 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
12771 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
12772 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
12773 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
12774 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
12775 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
12776 {NULL, 0, 0}
12777};
7ed4c4c5 12778
c19d1205
ZW
12779/* ISA extensions in the co-processor space. */
12780struct arm_option_value_table
12781{
12782 char *name;
12783 int value;
12784};
7ed4c4c5 12785
c19d1205
ZW
12786static struct arm_option_value_table arm_extensions[] =
12787{
12788 {"maverick", ARM_CEXT_MAVERICK},
12789 {"xscale", ARM_CEXT_XSCALE},
12790 {"iwmmxt", ARM_CEXT_IWMMXT},
12791 {NULL, 0}
12792};
7ed4c4c5 12793
c19d1205
ZW
12794/* This list should, at a minimum, contain all the fpu names
12795 recognized by GCC. */
12796static struct arm_option_value_table arm_fpus[] =
12797{
12798 {"softfpa", FPU_NONE},
12799 {"fpe", FPU_ARCH_FPE},
12800 {"fpe2", FPU_ARCH_FPE},
12801 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
12802 {"fpa", FPU_ARCH_FPA},
12803 {"fpa10", FPU_ARCH_FPA},
12804 {"fpa11", FPU_ARCH_FPA},
12805 {"arm7500fe", FPU_ARCH_FPA},
12806 {"softvfp", FPU_ARCH_VFP},
12807 {"softvfp+vfp", FPU_ARCH_VFP_V2},
12808 {"vfp", FPU_ARCH_VFP_V2},
12809 {"vfp9", FPU_ARCH_VFP_V2},
12810 {"vfp10", FPU_ARCH_VFP_V2},
12811 {"vfp10-r0", FPU_ARCH_VFP_V1},
12812 {"vfpxd", FPU_ARCH_VFP_V1xD},
12813 {"arm1020t", FPU_ARCH_VFP_V1},
12814 {"arm1020e", FPU_ARCH_VFP_V2},
12815 {"arm1136jfs", FPU_ARCH_VFP_V2},
12816 {"arm1136jf-s", FPU_ARCH_VFP_V2},
12817 {"maverick", FPU_ARCH_MAVERICK},
12818 {NULL, 0}
12819};
7ed4c4c5 12820
c19d1205
ZW
12821static struct arm_option_value_table arm_float_abis[] =
12822{
12823 {"hard", ARM_FLOAT_ABI_HARD},
12824 {"softfp", ARM_FLOAT_ABI_SOFTFP},
12825 {"soft", ARM_FLOAT_ABI_SOFT},
12826 {NULL, 0}
12827};
7ed4c4c5 12828
c19d1205
ZW
12829#ifdef OBJ_ELF
12830/* We only know how to output GNU and ver 4 (AAELF) formats. */
12831static struct arm_option_value_table arm_eabis[] =
12832{
12833 {"gnu", EF_ARM_EABI_UNKNOWN},
12834 {"4", EF_ARM_EABI_VER4},
12835 {NULL, 0}
12836};
12837#endif
7ed4c4c5 12838
c19d1205
ZW
12839struct arm_long_option_table
12840{
12841 char * option; /* Substring to match. */
12842 char * help; /* Help information. */
12843 int (* func) (char * subopt); /* Function to decode sub-option. */
12844 char * deprecated; /* If non-null, print this message. */
12845};
7ed4c4c5
NC
12846
12847static int
c19d1205 12848arm_parse_extension (char * str, int * opt_p)
7ed4c4c5 12849{
c19d1205 12850 while (str != NULL && *str != 0)
7ed4c4c5 12851 {
c19d1205
ZW
12852 struct arm_option_value_table * opt;
12853 char * ext;
12854 int optlen;
7ed4c4c5 12855
c19d1205
ZW
12856 if (*str != '+')
12857 {
12858 as_bad (_("invalid architectural extension"));
12859 return 0;
12860 }
7ed4c4c5 12861
c19d1205
ZW
12862 str++;
12863 ext = strchr (str, '+');
7ed4c4c5 12864
c19d1205
ZW
12865 if (ext != NULL)
12866 optlen = ext - str;
12867 else
12868 optlen = strlen (str);
7ed4c4c5 12869
c19d1205
ZW
12870 if (optlen == 0)
12871 {
12872 as_bad (_("missing architectural extension"));
12873 return 0;
12874 }
7ed4c4c5 12875
c19d1205
ZW
12876 for (opt = arm_extensions; opt->name != NULL; opt++)
12877 if (strncmp (opt->name, str, optlen) == 0)
12878 {
12879 *opt_p |= opt->value;
12880 break;
12881 }
7ed4c4c5 12882
c19d1205
ZW
12883 if (opt->name == NULL)
12884 {
12885 as_bad (_("unknown architectural extnsion `%s'"), str);
12886 return 0;
12887 }
7ed4c4c5 12888
c19d1205
ZW
12889 str = ext;
12890 };
7ed4c4c5 12891
c19d1205
ZW
12892 return 1;
12893}
7ed4c4c5 12894
c19d1205
ZW
12895static int
12896arm_parse_cpu (char * str)
7ed4c4c5 12897{
c19d1205
ZW
12898 struct arm_cpu_option_table * opt;
12899 char * ext = strchr (str, '+');
12900 int optlen;
7ed4c4c5 12901
c19d1205
ZW
12902 if (ext != NULL)
12903 optlen = ext - str;
7ed4c4c5 12904 else
c19d1205 12905 optlen = strlen (str);
7ed4c4c5 12906
c19d1205 12907 if (optlen == 0)
7ed4c4c5 12908 {
c19d1205
ZW
12909 as_bad (_("missing cpu name `%s'"), str);
12910 return 0;
7ed4c4c5
NC
12911 }
12912
c19d1205
ZW
12913 for (opt = arm_cpus; opt->name != NULL; opt++)
12914 if (strncmp (opt->name, str, optlen) == 0)
12915 {
12916 mcpu_cpu_opt = opt->value;
12917 mcpu_fpu_opt = opt->default_fpu;
7ed4c4c5 12918
c19d1205
ZW
12919 if (ext != NULL)
12920 return arm_parse_extension (ext, &mcpu_cpu_opt);
7ed4c4c5 12921
c19d1205
ZW
12922 return 1;
12923 }
7ed4c4c5 12924
c19d1205
ZW
12925 as_bad (_("unknown cpu `%s'"), str);
12926 return 0;
7ed4c4c5
NC
12927}
12928
c19d1205
ZW
12929static int
12930arm_parse_arch (char * str)
7ed4c4c5 12931{
c19d1205
ZW
12932 struct arm_arch_option_table *opt;
12933 char *ext = strchr (str, '+');
12934 int optlen;
7ed4c4c5 12935
c19d1205
ZW
12936 if (ext != NULL)
12937 optlen = ext - str;
7ed4c4c5 12938 else
c19d1205 12939 optlen = strlen (str);
7ed4c4c5 12940
c19d1205 12941 if (optlen == 0)
7ed4c4c5 12942 {
c19d1205
ZW
12943 as_bad (_("missing architecture name `%s'"), str);
12944 return 0;
7ed4c4c5
NC
12945 }
12946
7ed4c4c5 12947
c19d1205
ZW
12948 for (opt = arm_archs; opt->name != NULL; opt++)
12949 if (streq (opt->name, str))
12950 {
12951 march_cpu_opt = opt->value;
12952 march_fpu_opt = opt->default_fpu;
7ed4c4c5 12953
c19d1205
ZW
12954 if (ext != NULL)
12955 return arm_parse_extension (ext, &march_cpu_opt);
7ed4c4c5 12956
c19d1205
ZW
12957 return 1;
12958 }
12959
12960 as_bad (_("unknown architecture `%s'\n"), str);
12961 return 0;
7ed4c4c5 12962}
eb043451 12963
c19d1205
ZW
12964static int
12965arm_parse_fpu (char * str)
12966{
12967 struct arm_option_value_table * opt;
b99bd4ef 12968
c19d1205
ZW
12969 for (opt = arm_fpus; opt->name != NULL; opt++)
12970 if (streq (opt->name, str))
12971 {
12972 mfpu_opt = opt->value;
12973 return 1;
12974 }
b99bd4ef 12975
c19d1205
ZW
12976 as_bad (_("unknown floating point format `%s'\n"), str);
12977 return 0;
12978}
12979
12980static int
12981arm_parse_float_abi (char * str)
b99bd4ef 12982{
c19d1205 12983 struct arm_option_value_table * opt;
b99bd4ef 12984
c19d1205
ZW
12985 for (opt = arm_float_abis; opt->name != NULL; opt++)
12986 if (streq (opt->name, str))
12987 {
12988 mfloat_abi_opt = opt->value;
12989 return 1;
12990 }
cc8a6dd0 12991
c19d1205
ZW
12992 as_bad (_("unknown floating point abi `%s'\n"), str);
12993 return 0;
12994}
b99bd4ef 12995
c19d1205
ZW
12996#ifdef OBJ_ELF
12997static int
12998arm_parse_eabi (char * str)
12999{
13000 struct arm_option_value_table *opt;
cc8a6dd0 13001
c19d1205
ZW
13002 for (opt = arm_eabis; opt->name != NULL; opt++)
13003 if (streq (opt->name, str))
13004 {
13005 meabi_flags = opt->value;
13006 return 1;
13007 }
13008 as_bad (_("unknown EABI `%s'\n"), str);
13009 return 0;
13010}
13011#endif
cc8a6dd0 13012
c19d1205
ZW
13013struct arm_long_option_table arm_long_opts[] =
13014{
13015 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
13016 arm_parse_cpu, NULL},
13017 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
13018 arm_parse_arch, NULL},
13019 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
13020 arm_parse_fpu, NULL},
13021 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
13022 arm_parse_float_abi, NULL},
13023#ifdef OBJ_ELF
13024 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
13025 arm_parse_eabi, NULL},
13026#endif
13027 {NULL, NULL, 0, NULL}
13028};
cc8a6dd0 13029
c19d1205
ZW
13030int
13031md_parse_option (int c, char * arg)
13032{
13033 struct arm_option_table *opt;
13034 struct arm_long_option_table *lopt;
b99bd4ef 13035
c19d1205 13036 switch (c)
b99bd4ef 13037 {
c19d1205
ZW
13038#ifdef OPTION_EB
13039 case OPTION_EB:
13040 target_big_endian = 1;
13041 break;
13042#endif
cc8a6dd0 13043
c19d1205
ZW
13044#ifdef OPTION_EL
13045 case OPTION_EL:
13046 target_big_endian = 0;
13047 break;
13048#endif
b99bd4ef 13049
c19d1205
ZW
13050 case 'a':
13051 /* Listing option. Just ignore these, we don't support additional
13052 ones. */
13053 return 0;
b99bd4ef 13054
c19d1205
ZW
13055 default:
13056 for (opt = arm_opts; opt->option != NULL; opt++)
13057 {
13058 if (c == opt->option[0]
13059 && ((arg == NULL && opt->option[1] == 0)
13060 || streq (arg, opt->option + 1)))
13061 {
13062#if WARN_DEPRECATED
13063 /* If the option is deprecated, tell the user. */
13064 if (opt->deprecated != NULL)
13065 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
13066 arg ? arg : "", _(opt->deprecated));
13067#endif
b99bd4ef 13068
c19d1205
ZW
13069 if (opt->var != NULL)
13070 *opt->var = opt->value;
cc8a6dd0 13071
c19d1205
ZW
13072 return 1;
13073 }
13074 }
b99bd4ef 13075
c19d1205
ZW
13076 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
13077 {
13078 /* These options are expected to have an argument. */
13079 if (c == lopt->option[0]
13080 && arg != NULL
13081 && strncmp (arg, lopt->option + 1,
13082 strlen (lopt->option + 1)) == 0)
13083 {
13084#if WARN_DEPRECATED
13085 /* If the option is deprecated, tell the user. */
13086 if (lopt->deprecated != NULL)
13087 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
13088 _(lopt->deprecated));
13089#endif
b99bd4ef 13090
c19d1205
ZW
13091 /* Call the sup-option parser. */
13092 return lopt->func (arg + strlen (lopt->option) - 1);
13093 }
13094 }
a737bd4d 13095
c19d1205
ZW
13096 return 0;
13097 }
a394c00f 13098
c19d1205
ZW
13099 return 1;
13100}
a394c00f 13101
c19d1205
ZW
13102void
13103md_show_usage (FILE * fp)
a394c00f 13104{
c19d1205
ZW
13105 struct arm_option_table *opt;
13106 struct arm_long_option_table *lopt;
a394c00f 13107
c19d1205 13108 fprintf (fp, _(" ARM-specific assembler options:\n"));
a394c00f 13109
c19d1205
ZW
13110 for (opt = arm_opts; opt->option != NULL; opt++)
13111 if (opt->help != NULL)
13112 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
a394c00f 13113
c19d1205
ZW
13114 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
13115 if (lopt->help != NULL)
13116 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
a394c00f 13117
c19d1205
ZW
13118#ifdef OPTION_EB
13119 fprintf (fp, _("\
13120 -EB assemble code for a big-endian cpu\n"));
a394c00f
NC
13121#endif
13122
c19d1205
ZW
13123#ifdef OPTION_EL
13124 fprintf (fp, _("\
13125 -EL assemble code for a little-endian cpu\n"));
a737bd4d 13126#endif
c19d1205 13127}
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